# Breath_led **Repository Path**: Core_Kingdom/breath_led ## Basic Information - **Project Name**: Breath_led - **Description**: A100T-FPGA Demo工程;原型验证环境,脚本自动化综合; - **Primary Language**: Verilog - **License**: MulanPSL-2.0 - **Default Branch**: master - **Homepage**: None - **GVP Project**: No ## Statistics - **Stars**: 2 - **Forks**: 2 - **Created**: 2022-06-11 - **Last Updated**: 2023-08-02 ## Categories & Tags **Categories**: Uncategorized **Tags**: None ## README # Breath_led #### 介绍 A100T-FPGA Demo工程;原型验证环境,脚本自动化综合; #### 软件架构 环境中需要vivado工具,vcs,verdi 我也有已安装好的EDA环境,下载直接使用: [IC-EDA虚拟机:点击跳转](https://blog.csdn.net/weixin_40377195/article/details/124956898?spm=1001.2014.3001.5502) #### 安装教程 ``` git clone https://gitee.com/Core_Kingdom/breath_led.git ``` #### SRAM和DDR板卡差异说明 根据自己板卡型号修改下面的`pin.xdc`文件,目前是DDR板卡时钟约束; ![在这里插入图片描述](https://img-blog.csdnimg.cn/a2892db68c9d4d999c7eff17ece311a9.png) #### 使用说明 1.启动仿真 ``` make vcs ``` ![输入图片说明](https://images.gitee.com/uploads/images/2022/0611/160719_b7600531_5033787.png "屏幕截图.png") 2.启动verdi查看波形 ``` make verdi ``` ![输入图片说明](https://images.gitee.com/uploads/images/2022/0611/160832_78ec32f1_5033787.png "屏幕截图.png") 3.FPGA综合 ``` make built ``` ![输入图片说明](https://images.gitee.com/uploads/images/2022/0611/161031_897cab99_5033787.png "屏幕截图.png") 显示如下综合成功,回车退出一下; ![输入图片说明](https://images.gitee.com/uploads/images/2022/0611/161404_22425f26_5033787.png "屏幕截图.png") 4.FPGA GUI查看 综合已完成,可直接烧写; ![输入图片说明](https://images.gitee.com/uploads/images/2022/0611/161513_2ffb8e56_5033787.png "屏幕截图.png") 5 FPGA BIT文件烧写 板卡链连接虚拟机; ![输入图片说明](https://images.gitee.com/uploads/images/2022/0611/161714_f02ca3b5_5033787.png "屏幕截图.png") 6 FPGA MCS文件 FLash固化 添加Flash型号; **![输入图片说明](https://images.gitee.com/uploads/images/2022/0611/161814_4eeecd20_5033787.png "屏幕截图.png")** 具体型号如下 ![输入图片说明](https://images.gitee.com/uploads/images/2022/0611/161849_238c2a23_5033787.png "屏幕截图.png") 选择生成好的MCS文件进行固化; ![输入图片说明](https://images.gitee.com/uploads/images/2022/0611/162015_170957ae_5033787.png "屏幕截图.png") 7 效果 FPGA板卡 LED0呼吸闪烁;