# FiveStage-MIPS-CPU

**Repository Path**: EricDracula/FiveStage-MIPS-CPU

## Basic Information

- **Project Name**: FiveStage-MIPS-CPU
- **Description**: Complete a 5-stage MIPS CPU with multi-level interrupts and dynamic branch prediction on logisim and verilog
- **Primary Language**: Verilog
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2017-11-22
- **Last Updated**: 2020-12-19

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

### 支持多级嵌套中断和动态分支预测的5段流水MIPS CPU
#### 具体内容请参考requirement.docx和report