diff --git "a/vendor/xinlingyu_92_3061M/Document/\344\270\212\346\265\267\346\265\267\346\200\235MCU\345\274\200\345\217\221\350\200\205\344\275\223\351\252\214\344\275\234\345\223\201\346\217\220\344\272\244\357\274\232\346\231\272\350\203\275\346\262\271\347\203\237\346\234\272-92\345\217\267.doc" "b/vendor/xinlingyu_92_3061M/Document/\344\270\212\346\265\267\346\265\267\346\200\235MCU\345\274\200\345\217\221\350\200\205\344\275\223\351\252\214\344\275\234\345\223\201\346\217\220\344\272\244\357\274\232\346\231\272\350\203\275\346\262\271\347\203\237\346\234\272-92\345\217\267.doc" new file mode 100644 index 0000000000000000000000000000000000000000..2e4eea92815ee080795a679479e4bcccc9a7cc63 Binary files /dev/null and "b/vendor/xinlingyu_92_3061M/Document/\344\270\212\346\265\267\346\265\267\346\200\235MCU\345\274\200\345\217\221\350\200\205\344\275\223\351\252\214\344\275\234\345\223\201\346\217\220\344\272\244\357\274\232\346\231\272\350\203\275\346\262\271\347\203\237\346\234\272-92\345\217\267.doc" differ diff --git a/vendor/xinlingyu_92_3061M/Project/.vscode/.attachinit b/vendor/xinlingyu_92_3061M/Project/.vscode/.attachinit new file mode 100644 index 0000000000000000000000000000000000000000..98fc97a1ec3ad3a285b60c323da900a13c19c432 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/.vscode/.attachinit @@ -0,0 +1,16 @@ +echo debug_tool = openocd(HiSpark-Trace)\n +echo Initializing remote target...\n +define pio_reset_halt_target +monitor reset halt +set var $pc=0x03000004 +end +define pio_reset_run_target +monitor reset +end +target extended-remote :3333 +monitor init +monitor halt +tbreak main +define pio_restart_target +pio_reset_halt_target +echo Initialization completed\n \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/.vscode/.launchinit b/vendor/xinlingyu_92_3061M/Project/.vscode/.launchinit new file mode 100644 index 0000000000000000000000000000000000000000..48a239daaa0f0d96f89d1f42cb4568a66dfe00d4 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/.vscode/.launchinit @@ -0,0 +1,17 @@ +echo debug_tool = openocd(HiSpark-Trace)\n +echo Initializing remote target...\n +define pio_reset_halt_target +monitor reset halt +set var $pc=0x03000004 +end +define pio_reset_run_target +monitor reset +end +target extended-remote :3333 +monitor init +load +pio_reset_halt_target +tbreak main +define pio_restart_target +pio_reset_halt_target +echo Initialization completed\n \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/.vscode/c_cpp_properties.json b/vendor/xinlingyu_92_3061M/Project/.vscode/c_cpp_properties.json new file mode 100644 index 0000000000000000000000000000000000000000..c5c9e546a4f11cb1cdb3353856750be5193ee802 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/.vscode/c_cpp_properties.json @@ -0,0 +1,21 @@ +{ + "configurations": [ + { + "name": "c/cpp plugin configurations", + "compilerPath": "c:\\Program Files\\HiSpark Studio\\tools\\Windows\\cc_riscv32_musl_fp_win\\bin\\riscv32-linux-musl-gcc.exe", + "includePath": [ + "${workspaceFolder}/**" + ], + "browse": { + "limitSymbolsToIncludedHeaders": true, + "path": [ + "${workspaceFolder}/**" + ] + }, + "defines": [ + "FLOAT_SUPPORT" + ] + } + ], + "version": 4 +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/.vscode/launch.json b/vendor/xinlingyu_92_3061M/Project/.vscode/launch.json new file mode 100644 index 0000000000000000000000000000000000000000..4e78868d98d55bb2f92d1627cea1173075b11b50 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/.vscode/launch.json @@ -0,0 +1,60 @@ +{ + "configurations": [ + { + "type": "deveco-device-tool-debug", + "request": "launch", + "name": "GDB Launch (Download and Reset Program)", + "debugInitPath": "${workspaceFolder}/.vscode", + "servertype": "openocd(HiSpark-Trace)", + "executable": "./out/bin/target.elf", + "toolchainBinDir": "${command:toolsPath}\\Windows\\cc_riscv32_musl_fp_win\\bin", + "internalConsoleOptions": "openOnSessionStart", + "serverpath": "${command:toolsPath}\\hw_openocd\\bin\\openocd.exe", + "serverArgs": [ + "-c", + "tcl_port 6666", + "-c", + "telnet_port 4444", + "-c", + "adapter speed 5000", + "-c", + "gdb_port 3333", + "-s", + "${command:toolsPath}\\hw_openocd", + "-f", + "interface\\cmsis-dap.cfg", + "-f", + "target\\3061MNPICA-swd.cfg" + ], + "svdFile": "${command:projectWizardExtensionPath}\\resources\\debug\\svd\\3061MNPICA.svd" + }, + { + "type": "deveco-device-tool-debug", + "request": "attach", + "name": "GDB Attach (Attach to Running Program)", + "debugInitPath": "${workspaceFolder}/.vscode", + "servertype": "openocd(HiSpark-Trace)", + "executable": "./out/bin/target.elf", + "toolchainBinDir": "${command:toolsPath}\\Windows\\cc_riscv32_musl_fp_win\\bin", + "internalConsoleOptions": "openOnSessionStart", + "serverpath": "${command:toolsPath}\\hw_openocd\\bin\\openocd.exe", + "serverArgs": [ + "-c", + "tcl_port 6666", + "-c", + "telnet_port 4444", + "-c", + "adapter speed 5000", + "-c", + "gdb_port 3333", + "-s", + "${command:toolsPath}\\hw_openocd", + "-f", + "interface\\cmsis-dap.cfg", + "-f", + "target\\3061MNPICA-swd.cfg" + ], + "svdFile": "${command:projectWizardExtensionPath}\\resources\\debug\\svd\\3061MNPICA.svd" + } + ] +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/.vscode/problems.json b/vendor/xinlingyu_92_3061M/Project/.vscode/problems.json new file mode 100644 index 0000000000000000000000000000000000000000..7308ea9c41c5bb7781d058755ba49755f8b1322a --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/.vscode/problems.json @@ -0,0 +1 @@ +[{"key":0,"message":"warning: implicit declaration of function 'PAJ7620U2_Init'; did you mean 'PAJ7620U2_Handler'? [-Wimplicit-function-declaration]","file":"c:\\Users\\xulid\\Desktop\\Desktop\\Workspace\\3061M\\Project\\user\\main.c","line":"74","column":"5","displayLine":"74","type":"warning"},{"key":1,"message":"warning: no previous prototype for 'PAJ7620U2_I2C_WriteData' [-Wmissing-prototypes]","file":"c:\\Users\\xulid\\Desktop\\Desktop\\Workspace\\3061M\\Project\\user\\PAJ7620U2.c","line":"99","column":"6","displayLine":"99","type":"warning"},{"key":2,"message":"warning: no previous prototype for 'PAJ7620U2_I2C_ReadData' [-Wmissing-prototypes]","file":"c:\\Users\\xulid\\Desktop\\Desktop\\Workspace\\3061M\\Project\\user\\PAJ7620U2.c","line":"107","column":"15","displayLine":"107","type":"warning"},{"key":3,"message":"warning: passing argument 3 of 'HAL_I2C_MasterWriteBlocking' from incompatible pointer type [-Wincompatible-pointer-types]","file":"c:\\Users\\xulid\\Desktop\\Desktop\\Workspace\\3061M\\Project\\user\\PAJ7620U2.c","line":"111","column":"48","displayLine":"111","type":"warning"},{"key":4,"message":"warning: passing argument 3 of 'HAL_I2C_MasterReadBlocking' from incompatible pointer type [-Wincompatible-pointer-types]","file":"c:\\Users\\xulid\\Desktop\\Desktop\\Workspace\\3061M\\Project\\user\\PAJ7620U2.c","line":"112","column":"47","displayLine":"112","type":"warning"},{"key":5,"message":"warning: no previous prototype for 'PAJ7620U2_Init' [-Wmissing-prototypes]","file":"c:\\Users\\xulid\\Desktop\\Desktop\\Workspace\\3061M\\Project\\user\\PAJ7620U2.c","line":"117","column":"6","displayLine":"117","type":"warning"},{"key":6,"message":"warning: pointer targets in passing argument 2 of 'HAL_UART_WriteBlocking' differ in signedness [-Wpointer-sign]","file":"c:\\Users\\xulid\\Desktop\\Desktop\\Workspace\\3061M\\Project\\user\\PAJ7620U2.c","line":"131","column":"42","displayLine":"131","type":"warning"},{"key":7,"message":"warning: pointer targets in passing argument 2 of 'HAL_UART_WriteBlocking' differ in signedness [-Wpointer-sign]","file":"c:\\Users\\xulid\\Desktop\\Desktop\\Workspace\\3061M\\Project\\user\\PAJ7620U2.c","line":"135","column":"42","displayLine":"135","type":"warning"},{"key":8,"message":"warning: pointer targets in passing argument 2 of 'HAL_UART_WriteBlocking' differ in signedness [-Wpointer-sign]","file":"c:\\Users\\xulid\\Desktop\\Desktop\\Workspace\\3061M\\Project\\user\\PAJ7620U2.c","line":"145","column":"53","displayLine":"145","type":"warning"},{"key":9,"message":"warning: pointer targets in passing argument 2 of 'HAL_UART_WriteBlocking' differ in signedness [-Wpointer-sign]","file":"c:\\Users\\xulid\\Desktop\\Desktop\\Workspace\\3061M\\Project\\user\\PAJ7620U2.c","line":"146","column":"53","displayLine":"146","type":"warning"},{"key":10,"message":"warning: pointer targets in passing argument 2 of 'HAL_UART_WriteBlocking' differ in signedness [-Wpointer-sign]","file":"c:\\Users\\xulid\\Desktop\\Desktop\\Workspace\\3061M\\Project\\user\\PAJ7620U2.c","line":"147","column":"53","displayLine":"147","type":"warning"},{"key":11,"message":"warning: pointer targets in passing argument 2 of 'HAL_UART_WriteBlocking' differ in signedness [-Wpointer-sign]","file":"c:\\Users\\xulid\\Desktop\\Desktop\\Workspace\\3061M\\Project\\user\\PAJ7620U2.c","line":"148","column":"53","displayLine":"148","type":"warning"},{"key":12,"message":"warning: pointer targets in passing argument 2 of 'HAL_UART_WriteBlocking' differ in signedness [-Wpointer-sign]","file":"c:\\Users\\xulid\\Desktop\\Desktop\\Workspace\\3061M\\Project\\user\\PAJ7620U2.c","line":"149","column":"53","displayLine":"149","type":"warning"},{"key":13,"message":"warning: pointer targets in passing argument 2 of 'HAL_UART_WriteBlocking' differ in signedness [-Wpointer-sign]","file":"c:\\Users\\xulid\\Desktop\\Desktop\\Workspace\\3061M\\Project\\user\\PAJ7620U2.c","line":"150","column":"53","displayLine":"150","type":"warning"},{"key":14,"message":"warning: pointer targets in passing argument 2 of 'HAL_UART_WriteBlocking' differ in signedness [-Wpointer-sign]","file":"c:\\Users\\xulid\\Desktop\\Desktop\\Workspace\\3061M\\Project\\user\\PAJ7620U2.c","line":"151","column":"53","displayLine":"151","type":"warning"},{"key":15,"message":"warning: pointer targets in passing argument 2 of 'HAL_UART_WriteBlocking' differ in signedness [-Wpointer-sign]","file":"c:\\Users\\xulid\\Desktop\\Desktop\\Workspace\\3061M\\Project\\user\\PAJ7620U2.c","line":"152","column":"53","displayLine":"152","type":"warning"}] \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/.vscode/settings.json b/vendor/xinlingyu_92_3061M/Project/.vscode/settings.json new file mode 100644 index 0000000000000000000000000000000000000000..eebccf7d550c788776c4ad4b4682eb5e1d5685be --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/.vscode/settings.json @@ -0,0 +1,6 @@ +{ + "files.associations": { + "typedefs.h": "c", + "debug.h": "c" + } +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/Project.hiproj b/vendor/xinlingyu_92_3061M/Project/Project.hiproj new file mode 100644 index 0000000000000000000000000000000000000000..0e66f371bc581c46dce499acbb27cb4ab6dad8bc --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/Project.hiproj @@ -0,0 +1,75 @@ +[information] +series_name=3061m +board=ECBMCU201MPC +sdk_path=c:\Users\xulid\Desktop\Desktop\Workspace\3061M\Resource\open_mcu-master\src +flash=131072 +board_build.mcu=3061MNPICA +platform=vendorhm +json_path=ECBMCU201MPC.json +project_type=MCU + +[chipconfig] +chipconfig=true + +[variabletrace] +variabletrace=true + +[compile] +tool_chain=cc_riscv32_musl_fp_win +link_c_library_in_toolchain=yes +link_c_library_in_compilationchain=yes +custom_build_command=undefined -d FLOAT_SUPPORT +custom_clean_command=undefined +map_path=./out/bin/target.map +compile_type=debug +constant_type=float +optimization=O0 +warning=yes +werror=no +wno_unused_function=no +wno_unused_label=no +wno_unused_parameter=no +wno_unused_variable=no +wno_missing_prototypes=no +static_library_enable=no +static_library_name= +static_library_dependency_header_file= +static_library_source_file= +fstack_protector_strong=no +extern_staticlib_path= +extern_staticlib_include= +global_macro_definition={"FLOAT_SUPPORT":""} +generate_crc=no +generate_checksum=no +generate_target_hex=yes +parse_elf_for_livewatch=no +parse_analysis_json=yes +padding=no + +[debug] +elf_path=./out/bin/target.elf +breakpoints_limitation=3 +client=gdb +tool=HiSpark-Trace +interface=swd +speed=5000 +openocd_interface_file= +openocd_target_file= +timeout=60000 +port=3333 + +[upload] +bin_path=./out/bin/target.bin +protocol=swd +reset=1 +burn_verification=0 +debug_board=HiSpark-Link +frequency=5000 +address=0x3000000 +partition_length=0x20000 + +[console] +port= +baud=115200 +stop_bit=0 +parity=N diff --git a/vendor/xinlingyu_92_3061M/Project/analyzerJson/assembleFile.asm b/vendor/xinlingyu_92_3061M/Project/analyzerJson/assembleFile.asm new file mode 100644 index 0000000000000000000000000000000000000000..d82649edf3fbcc764e440b4f2682048eefc89030 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/analyzerJson/assembleFile.asm @@ -0,0 +1,12121 @@ + +c:\Users\xulid\Desktop\Desktop\Workspace\3061M\Project\out\bin\target.elf: file format elf32-littleriscv + + +Disassembly of section .text.entry: + +03000004 <_start>: + 3000004: 4fc0006f j 3000500 + +03000008 : + 3000008: 4680006f j 3000470 + 300000c: 4640006f j 3000470 + 3000010: 4600006f j 3000470 + 3000014: 45c0006f j 3000470 + 3000018: 4580006f j 3000470 + 300001c: 4540006f j 3000470 + 3000020: 4500006f j 3000470 + 3000024: 44c0006f j 3000470 + 3000028: 4480006f j 3000470 + 300002c: 4440006f j 3000470 + 3000030: 4400006f j 3000470 + 3000034: 43c0006f j 3000470 + 3000038: 4380006f j 3000470 + 300003c: 4340006f j 3000470 + 3000040: 4300006f j 3000470 + 3000044: 42c0006f j 3000470 + 3000048: 4280006f j 3000470 + 300004c: 4240006f j 3000470 + 3000050: 4200006f j 3000470 + 3000054: 41c0006f j 3000470 + 3000058: 4180006f j 3000470 + 300005c: 4140006f j 3000470 + 3000060: 4100006f j 3000470 + 3000064: 40c0006f j 3000470 + 3000068: 4080006f j 3000470 + 300006c: 4040006f j 3000470 + 3000070: 2640006f j 30002d4 + 3000074: 2600006f j 30002d4 + 3000078: 25c0006f j 30002d4 + 300007c: 2580006f j 30002d4 + 3000080: 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05612c23 sw s6,88(sp) + 3000282: 05712e23 sw s7,92(sp) + 3000286: 07812023 sw s8,96(sp) + 300028a: 07912223 sw s9,100(sp) + 300028e: 07a12423 sw s10,104(sp) + 3000292: 07b12623 sw s11,108(sp) + 3000296: 11010593 addi a1,sp,272 + 300029a: 06b12823 sw a1,112(sp) + 300029e: 06312a23 sw gp,116(sp) + 30002a2: 06412c23 sw tp,120(sp) + 30002a6: 34102573 csrr a0,mepc + 30002aa: 300025f3 csrr a1,mstatus + 30002ae: 34302673 csrr a2,mtval + 30002b2: 342026f3 csrr a3,mcause + 30002b6: 06a12e23 sw a0,124(sp) + 30002ba: 08b12023 sw a1,128(sp) + 30002be: 08c12223 sw a2,132(sp) + 30002c2: 08d12423 sw a3,136(sp) + 30002c6: 00010513 mv a0,sp + 30002ca: 30047073 csrci mstatus,8 + 30002ce: 310010ef jal ra,30015de + +030002d2 : + 30002d2: a001 j 30002d2 + +030002d4 : + 30002d4: f6010113 addi sp,sp,-160 + 30002d8: 00a12623 sw a0,12(sp) + 30002dc: 00b12823 sw a1,16(sp) + 30002e0: 7ed02573 csrr a0,0x7ed + 30002e4: bfe025f3 csrr a1,0xbfe + 30002e8: bfe51073 csrw 0xbfe,a0 + 30002ec: 00b12c23 sw a1,24(sp) + 30002f0: 300025f3 csrr a1,mstatus + 30002f4: 00b12e23 sw a1,28(sp) + 30002f8: 341025f3 csrr a1,mepc + 30002fc: 02b12023 sw a1,32(sp) + 3000300: 34202573 csrr a0,mcause + 3000304: 000025b7 lui a1,0x2 + 3000308: 80058593 addi a1,a1,-2048 # 1800 + 300030c: 3005a073 csrs mstatus,a1 + 3000310: 00000597 auipc a1,0x0 + 3000314: 01058593 addi a1,a1,16 # 3000320 + 3000318: 34159073 csrw mepc,a1 + 300031c: 30200073 mret + +03000320 : + 3000320: 00512023 sw t0,0(sp) + 3000324: 00612223 sw t1,4(sp) + 3000328: 00712423 sw t2,8(sp) + 300032c: 00c12a23 sw a2,20(sp) + 3000330: 02112223 sw ra,36(sp) + 3000334: 02d12423 sw a3,40(sp) + 3000338: 02e12623 sw a4,44(sp) + 300033c: 02f12823 sw a5,48(sp) + 3000340: 03012a23 sw a6,52(sp) + 3000344: 03112c23 sw a7,56(sp) + 3000348: 03c12e23 sw t3,60(sp) + 300034c: 05d12023 sw t4,64(sp) + 3000350: 05e12223 sw t5,68(sp) + 3000354: 05f12423 sw t6,72(sp) + 3000358: 04012627 fsw ft0,76(sp) + 300035c: 04112827 fsw ft1,80(sp) + 3000360: 04212a27 fsw ft2,84(sp) + 3000364: 04312c27 fsw ft3,88(sp) + 3000368: 04412e27 fsw ft4,92(sp) + 300036c: 06512027 fsw ft5,96(sp) + 3000370: 06612227 fsw ft6,100(sp) + 3000374: 06712427 fsw ft7,104(sp) + 3000378: 06a12627 fsw fa0,108(sp) + 300037c: 06b12827 fsw fa1,112(sp) + 3000380: 06c12a27 fsw fa2,116(sp) + 3000384: 06d12c27 fsw fa3,120(sp) + 3000388: 06e12e27 fsw fa4,124(sp) + 300038c: 08f12027 fsw fa5,128(sp) + 3000390: 09012227 fsw fa6,132(sp) + 3000394: 09112427 fsw fa7,136(sp) + 3000398: 09c12627 fsw ft8,140(sp) + 300039c: 09d12827 fsw ft9,144(sp) + 30003a0: 09e12a27 fsw ft10,148(sp) + 30003a4: 09f12c27 fsw ft11,152(sp) + 30003a8: 0ff57513 andi a0,a0,255 + 30003ac: 7c3000ef jal ra,300136e + 30003b0: 00412303 lw t1,4(sp) + 30003b4: 00812383 lw t2,8(sp) + 30003b8: 01412603 lw a2,20(sp) + 30003bc: 02412083 lw ra,36(sp) + 30003c0: 02812683 lw a3,40(sp) + 30003c4: 02c12703 lw a4,44(sp) + 30003c8: 03012783 lw a5,48(sp) + 30003cc: 03412803 lw a6,52(sp) + 30003d0: 03812883 lw a7,56(sp) + 30003d4: 03c12e03 lw t3,60(sp) + 30003d8: 04012e83 lw t4,64(sp) + 30003dc: 04412f03 lw t5,68(sp) + 30003e0: 04812f83 lw t6,72(sp) + 30003e4: 04c12007 flw ft0,76(sp) + 30003e8: 05012087 flw ft1,80(sp) + 30003ec: 05412107 flw ft2,84(sp) + 30003f0: 05812187 flw ft3,88(sp) + 30003f4: 05c12207 flw ft4,92(sp) + 30003f8: 06012287 flw ft5,96(sp) + 30003fc: 06412307 flw ft6,100(sp) + 3000400: 06812387 flw ft7,104(sp) + 3000404: 06c12507 flw fa0,108(sp) + 3000408: 07012587 flw fa1,112(sp) + 300040c: 07412607 flw fa2,116(sp) + 3000410: 07812687 flw fa3,120(sp) + 3000414: 07c12707 flw fa4,124(sp) + 3000418: 08012787 flw fa5,128(sp) + 300041c: 08412807 flw fa6,132(sp) + 3000420: 08812887 flw fa7,136(sp) + 3000424: 08c12e07 flw ft8,140(sp) + 3000428: 09012e87 flw ft9,144(sp) + 300042c: 09412f07 flw ft10,148(sp) + 3000430: 09812f87 flw ft11,152(sp) + +03000434 : + 3000434: 01c12503 lw a0,28(sp) + 3000438: 300022f3 csrr t0,mstatus + 300043c: 02012583 lw a1,32(sp) + 3000440: 0082f293 andi t0,t0,8 + 3000444: 0002923b bnei t0,0,300044c + 3000448: f7757513 andi a0,a0,-137 + +0300044c : + 300044c: 30051073 csrw mstatus,a0 + 3000450: 00012283 lw t0,0(sp) + 3000454: 34159073 csrw mepc,a1 + 3000458: 01812503 lw a0,24(sp) + 300045c: bfe51073 csrw 0xbfe,a0 + 3000460: 01012583 lw a1,16(sp) + 3000464: 00c12503 lw a0,12(sp) + 3000468: 0a010113 addi sp,sp,160 + 300046c: 30200073 mret + +03000470 : + 3000470: f6010113 addi sp,sp,-160 + 3000474: fff11f8b stmia {ra,t0-t6,a0-a7},(sp) + 3000478: f6010113 addi sp,sp,-160 + 300047c: 34202573 csrr a0,mcause + 3000480: 00b00313 li t1,11 + 3000484: 02650c63 beq a0,t1,30004bc + 3000488: 00800313 li t1,8 + 300048c: 02650863 beq a0,t1,30004bc + 3000490: 800005b7 lui a1,0x80000 + 3000494: 0ff00613 li a2,255 + 3000498: 00b575b3 and a1,a0,a1 + 300049c: 00c57533 and a0,a0,a2 + 30004a0: 00c00613 li a2,12 + 30004a4: d4c506e3 beq a0,a2,30001f0 + 30004a8: da058de3 beqz a1,3000262 + 30004ac: 0a010113 addi sp,sp,160 + 30004b0: fff10f8b ldmia {ra,t0-t6,a0-a7},(sp) + 30004b4: 0a010113 addi sp,sp,160 + 30004b8: 30200073 mret + +030004bc : + 30004bc: 000023b7 lui t2,0x2 + 30004c0: 80038393 addi t2,t2,-2048 # 1800 + 30004c4: 3003a073 csrs mstatus,t2 + 30004c8: 341022f3 csrr t0,mepc + 30004cc: 00428293 addi t0,t0,4 + 30004d0: 34129073 csrw mepc,t0 + 30004d4: 0a010113 addi sp,sp,160 + 30004d8: fff10f8b ldmia {ra,t0-t6,a0-a7},(sp) + 30004dc: 0a010113 addi sp,sp,160 + 30004e0: 30200073 mret + +030004e4 : + 30004e4: 0072dc63 bge t0,t2,30004fc + 30004e8: 00032e03 lw t3,0(t1) + 30004ec: 01c2a023 sw t3,0(t0) + 30004f0: 00428293 addi t0,t0,4 + 30004f4: 00430313 addi t1,t1,4 + 30004f8: fedff06f j 30004e4 + +030004fc : + 30004fc: 00008067 ret + +03000500 : + 3000500: 30005073 csrwi mstatus,0 + 3000504: 30405073 csrwi mie,0 + 3000508: 30047073 csrci mstatus,8 + 300050c: 00000297 auipc t0,0x0 + 3000510: afc28293 addi t0,t0,-1284 # 3000008 + 3000514: 00128293 addi t0,t0,1 + 3000518: 30529073 csrw mtvec,t0 + 300051c: 7ef0d073 csrwi 0x7ef,1 + +03000520 : + 3000520: 147102b7 lui t0,0x14710 + 3000524: 1202a303 lw t1,288(t0) # 14710120 + 3000528: 00136313 ori t1,t1,1 + 300052c: 1262a023 sw t1,288(t0) + 3000530: 1242a303 lw t1,292(t0) + 3000534: 00136313 ori t1,t1,1 + 3000538: 1262a223 sw t1,292(t0) + 300053c: fedcc2b7 lui t0,0xfedcc + 3000540: a9828293 addi t0,t0,-1384 # fedcba98 + 3000544: 14710337 lui t1,0x14710 + 3000548: 20030313 addi t1,t1,512 # 14710200 + 300054c: 00532023 sw t0,0(t1) + 3000550: 01001197 auipc gp,0x1001 + 3000554: 2ce18193 addi gp,gp,718 # 400181e <__global_pointer$> + 3000558: 01007117 auipc sp,0x1007 + 300055c: 6a810113 addi sp,sp,1704 # 4007c00 <__INTERRUPT_STACK_BEGIN__> + 3000560: 143002b7 lui t0,0x14300 + 3000564: 00828293 addi t0,t0,8 # 14300008 + 3000568: 0002a303 lw t1,0(t0) + 300056c: 02037313 andi t1,t1,32 + 3000570: 0062a023 sw t1,0(t0) + 3000574: 140002b7 lui t0,0x14000 + 3000578: 00000313 li t1,0 + 300057c: 0262a223 sw t1,36(t0) # 14000024 + 3000580: 0262a423 sw t1,40(t0) + 3000584: 0262a623 sw t1,44(t0) + 3000588: 0262a823 sw t1,48(t0) + 300058c: 0462a423 sw t1,72(t0) + +03000590 : + 3000590: 101082b7 lui t0,0x10108 + 3000594: 30028293 addi t0,t0,768 # 10108300 + 3000598: 0002a303 lw t1,0(t0) + 300059c: 00136313 ori t1,t1,1 + 30005a0: 0062a023 sw t1,0(t0) + 30005a4: 01000297 auipc t0,0x1000 + 30005a8: a5c28293 addi t0,t0,-1444 # 4000000 + 30005ac: 01008317 auipc t1,0x1008 + 30005b0: a5430313 addi t1,t1,-1452 # 4008000 + 30005b4: 00000393 li t2,0 + +030005b8 : + 30005b8: 0072a023 sw t2,0(t0) + 30005bc: 00428293 addi t0,t0,4 + 30005c0: fe62cce3 blt t0,t1,30005b8 + +030005c4 : + 30005c4: ff000297 auipc t0,0xff000 + 30005c8: a3c28293 addi t0,t0,-1476 # 2000000 + 30005cc: 00000317 auipc t1,0x0 + 30005d0: 13830313 addi t1,t1,312 # 3000704 + 30005d4: ff000397 auipc t2,0xff000 + 30005d8: a2c38393 addi t2,t2,-1492 # 2000000 + 30005dc: f09ff0ef jal ra,30004e4 + +030005e0 : + 30005e0: 01000297 auipc t0,0x1000 + 30005e4: a2028293 addi t0,t0,-1504 # 4000000 + 30005e8: 00000317 auipc t1,0x0 + 30005ec: 11c30313 addi t1,t1,284 # 3000704 + 30005f0: 01000397 auipc t2,0x1000 + 30005f4: a1038393 addi t2,t2,-1520 # 4000000 + 30005f8: eedff0ef jal ra,30004e4 + +030005fc : + 30005fc: 01000297 auipc t0,0x1000 + 3000600: a2428293 addi t0,t0,-1500 # 4000020 + 3000604: 00008317 auipc t1,0x8 + 3000608: 63c30313 addi t1,t1,1596 # 3008c40 <__data_load> + 300060c: 01000397 auipc t2,0x1000 + 3000610: af038393 addi t2,t2,-1296 # 40000fc + 3000614: ed1ff0ef jal ra,30004e4 + +03000618 : + 3000618: 000012b7 lui t0,0x1 + 300061c: b0028293 addi t0,t0,-1280 # b00 + 3000620: 3b029073 csrw pmpaddr0,t0 + 3000624: 004002b7 lui t0,0x400 + 3000628: 40028293 addi t0,t0,1024 # 400400 + 300062c: 3b129073 csrw pmpaddr1,t0 + 3000630: 008002b7 lui t0,0x800 + 3000634: 3b229073 csrw pmpaddr2,t0 + 3000638: 008022b7 lui t0,0x802 + 300063c: 3b329073 csrw pmpaddr3,t0 + 3000640: 00c002b7 lui t0,0xc00 + 3000644: 3b429073 csrw pmpaddr4,t0 + 3000648: 010002b7 lui t0,0x1000 + 300064c: 3b529073 csrw pmpaddr5,t0 + 3000650: 010022b7 lui t0,0x1002 + 3000654: 3b629073 csrw pmpaddr6,t0 + 3000658: 070002b7 lui t0,0x7000 + 300065c: 40028293 addi t0,t0,1024 # 7000400 + 3000660: 3b729073 csrw pmpaddr7,t0 + 3000664: f33332b7 lui t0,0xf3333 + 3000668: 33328293 addi t0,t0,819 # f3333333 + 300066c: 7d829073 csrw 0x7d8,t0 + 3000670: 8d8892b7 lui t0,0x8d889 + 3000674: d8b28293 addi t0,t0,-629 # 8d888d8b + 3000678: 3a029073 csrw pmpcfg0,t0 + 300067c: 8b8b92b7 lui t0,0x8b8b9 + 3000680: d8828293 addi t0,t0,-632 # 8b8b8d88 + 3000684: 3a129073 csrw pmpcfg1,t0 + 3000688: 7c005073 csrwi 0x7c0,0 + 300068c: 0ff0000f fence + 3000690: 7c105073 csrwi 0x7c1,0 + 3000694: 0ff0000f fence + 3000698: 000022b7 lui t0,0x2 + 300069c: 00828293 addi t0,t0,8 # 2008 + 30006a0: 3002a073 csrs mstatus,t0 + 30006a4: 02000293 li t0,32 + 30006a8: 3012a073 csrs misa,t0 + 30006ac: 111112b7 lui t0,0x11111 + 30006b0: 11128293 addi t0,t0,273 # 11111111 + 30006b4: bc029073 csrw 0xbc0,t0 + 30006b8: bc129073 csrw 0xbc1,t0 + 30006bc: bc229073 csrw 0xbc2,t0 + 30006c0: bc329073 csrw 0xbc3,t0 + 30006c4: bc429073 csrw 0xbc4,t0 + 30006c8: bc529073 csrw 0xbc5,t0 + 30006cc: bc629073 csrw 0xbc6,t0 + 30006d0: bc729073 csrw 0xbc7,t0 + 30006d4: bc829073 csrw 0xbc8,t0 + 30006d8: bc929073 csrw 0xbc9,t0 + 30006dc: bca29073 csrw 0xbca,t0 + 30006e0: bcb29073 csrw 0xbcb,t0 + 30006e4: bcc29073 csrw 0xbcc,t0 + 30006e8: bcd29073 csrw 0xbcd,t0 + 30006ec: bce29073 csrw 0xbce,t0 + 30006f0: bcf29073 csrw 0xbcf,t0 + 30006f4: 00000073 ecall + 30006f8: 014000ef jal ra,300070c + 30006fc: 36d060ef jal ra,3007268
+ +03000700 : + 3000700: 0000006f j 3000700 + +Disassembly of section .text: + +03000704 : + 3000704: 1141 addi sp,sp,-16 + 3000706: c622 sw s0,12(sp) + 3000708: 0800 addi s0,sp,16 + 300070a: a001 j 300070a + +0300070c : + 300070c: 1101 addi sp,sp,-32 + 300070e: ce06 sw ra,28(sp) + 3000710: cc22 sw s0,24(sp) + 3000712: 1000 addi s0,sp,32 + 3000714: fec40793 addi a5,s0,-20 + 3000718: 853e mv a0,a5 + 300071a: 3e2070ef jal ra,3007afc + 300071e: 87aa mv a5,a0 + 3000720: c391 beqz a5,3000724 + 3000722: 37cd jal ra,3000704 + 3000724: fec42783 lw a5,-20(s0) + 3000728: 853e mv a0,a5 + 300072a: 792000ef jal ra,3000ebc + 300072e: 053000ef jal ra,3000f80 + 3000732: fec42783 lw a5,-20(s0) + 3000736: 853e mv a0,a5 + 3000738: 25b1 jal ra,3000d84 + 300073a: 479000ef jal ra,30013b2 + 300073e: 23e5 jal ra,3000d26 + 3000740: 2b51 jal ra,3000cd4 + 3000742: 0001 nop + 3000744: 40f2 lw ra,28(sp) + 3000746: 4462 lw s0,24(sp) + 3000748: 6105 addi sp,sp,32 + 300074a: 8082 ret + +0300074c : + 300074c: 1101 addi sp,sp,-32 + 300074e: ce22 sw s0,28(sp) + 3000750: 1000 addi s0,sp,32 + 3000752: fea42623 sw a0,-20(s0) + 3000756: fec42783 lw a5,-20(s0) + 300075a: d017f753 fcvt.s.wu fa4,a5 + 300075e: 030087b7 lui a5,0x3008 + 3000762: 6c47a787 flw fa5,1732(a5) # 30086c4 <__rodata_start> + 3000766: 18f777d3 fdiv.s fa5,fa4,fa5 + 300076a: 040007b7 lui a5,0x4000 + 300076e: 02f7a027 fsw fa5,32(a5) # 4000020 + 3000772: 0001 nop + 3000774: 4472 lw s0,28(sp) + 3000776: 6105 addi sp,sp,32 + 3000778: 8082 ret + +0300077a : + 300077a: 7179 addi sp,sp,-48 + 300077c: d606 sw ra,44(sp) + 300077e: d422 sw s0,40(sp) + 3000780: 1800 addi s0,sp,48 + 3000782: fe040793 addi a5,s0,-32 + 3000786: 863e mv a2,a5 + 3000788: 4591 li a1,4 + 300078a: 4501 li a0,0 + 300078c: 2391 jal ra,3000cd0 + 300078e: fd040793 addi a5,s0,-48 + 3000792: 863e mv a2,a5 + 3000794: 4589 li a1,2 + 3000796: 4501 li a0,0 + 3000798: 2b25 jal ra,3000cd0 + 300079a: fe042703 lw a4,-32(s0) + 300079e: 5aa597b7 lui a5,0x5aa59 + 30007a2: 66978793 addi a5,a5,1641 # 5aa59669 + 30007a6: 00f71763 bne a4,a5,30007b4 + 30007aa: fd042703 lw a4,-48(s0) + 30007ae: 57fd li a5,-1 + 30007b0: 00f71463 bne a4,a5,30007b8 + 30007b4: 4781 li a5,0 + 30007b6: a011 j 30007ba + 30007b8: 4785 li a5,1 + 30007ba: 853e mv a0,a5 + 30007bc: 50b2 lw ra,44(sp) + 30007be: 5422 lw s0,40(sp) + 30007c0: 6145 addi sp,sp,48 + 30007c2: 8082 ret + +030007c4 : + 30007c4: 711d addi sp,sp,-96 + 30007c6: ce86 sw ra,92(sp) + 30007c8: cca2 sw s0,88(sp) + 30007ca: 1080 addi s0,sp,96 + 30007cc: fdc40793 addi a5,s0,-36 + 30007d0: 863e mv a2,a5 + 30007d2: 45d1 li a1,20 + 30007d4: 4501 li a0,0 + 30007d6: 29ed jal ra,3000cd0 + 30007d8: 18100737 lui a4,0x18100 + 30007dc: fdc42783 lw a5,-36(s0) + 30007e0: 83c1 srli a5,a5,0x10 + 30007e2: 9bfd andi a5,a5,-1 + 30007e4: 0ff7f693 andi a3,a5,255 + 30007e8: 433c lw a5,64(a4) + 30007ea: 0ff6f693 andi a3,a3,255 + 30007ee: f007f793 andi a5,a5,-256 + 30007f2: 8fd5 or a5,a5,a3 + 30007f4: c33c sw a5,64(a4) + 30007f6: 18100737 lui a4,0x18100 + 30007fa: fdc42783 lw a5,-36(s0) + 30007fe: 83a1 srli a5,a5,0x8 + 3000800: 9bfd andi a5,a5,-1 + 3000802: 0ff7f693 andi a3,a5,255 + 3000806: 433c lw a5,64(a4) + 3000808: 0ff6f693 andi a3,a3,255 + 300080c: 06a2 slli a3,a3,0x8 + 300080e: 7641 lui a2,0xffff0 + 3000810: 0ff60613 addi a2,a2,255 # ffff00ff + 3000814: 8ff1 and a5,a5,a2 + 3000816: 8fd5 or a5,a5,a3 + 3000818: c33c sw a5,64(a4) + 300081a: 18100737 lui a4,0x18100 + 300081e: fdc42783 lw a5,-36(s0) + 3000822: 0ff7f693 andi a3,a5,255 + 3000826: 433c lw a5,64(a4) + 3000828: 0ff6f693 andi a3,a3,255 + 300082c: 06c2 slli a3,a3,0x10 + 300082e: ff010637 lui a2,0xff010 + 3000832: 167d addi a2,a2,-1 # ff00ffff + 3000834: 8ff1 and a5,a5,a2 + 3000836: 8fd5 or a5,a5,a3 + 3000838: c33c sw a5,64(a4) + 300083a: fe042783 lw a5,-32(s0) + 300083e: 83c1 srli a5,a5,0x10 + 3000840: 9bfd andi a5,a5,-1 + 3000842: 9f81 uxtb a5 + 3000844: fef42623 sw a5,-20(s0) + 3000848: fe042783 lw a5,-32(s0) + 300084c: 83a1 srli a5,a5,0x8 + 300084e: 9bfd andi a5,a5,-1 + 3000850: 9f81 uxtb a5 + 3000852: 07a2 slli a5,a5,0x8 + 3000854: 873e mv a4,a5 + 3000856: fec42783 lw a5,-20(s0) + 300085a: 8fd9 or a5,a5,a4 + 300085c: fef42623 sw a5,-20(s0) + 3000860: fe042783 lw a5,-32(s0) + 3000864: 9f81 uxtb a5 + 3000866: 07c2 slli a5,a5,0x10 + 3000868: 873e mv a4,a5 + 300086a: fec42783 lw a5,-20(s0) + 300086e: 8fd9 or a5,a5,a4 + 3000870: fef42623 sw a5,-20(s0) + 3000874: fdc42783 lw a5,-36(s0) + 3000878: 83e1 srli a5,a5,0x18 + 300087a: 9f81 uxtb a5 + 300087c: 07e2 slli a5,a5,0x18 + 300087e: 873e mv a4,a5 + 3000880: fec42783 lw a5,-20(s0) + 3000884: 8fd9 or a5,a5,a4 + 3000886: fef42623 sw a5,-20(s0) + 300088a: 181007b7 lui a5,0x18100 + 300088e: fec42703 lw a4,-20(s0) + 3000892: c3f8 sw a4,68(a5) + 3000894: fcc40793 addi a5,s0,-52 + 3000898: 863e mv a2,a5 + 300089a: 45d5 li a1,21 + 300089c: 4501 li a0,0 + 300089e: 290d jal ra,3000cd0 + 30008a0: 18000737 lui a4,0x18000 + 30008a4: fd042783 lw a5,-48(s0) + 30008a8: 86be mv a3,a5 + 30008aa: 6789 lui a5,0x2 + 30008ac: 17fd addi a5,a5,-1 # 1fff + 30008ae: 8ff5 and a5,a5,a3 + 30008b0: 01079613 slli a2,a5,0x10 + 30008b4: 8241 srli a2,a2,0x10 + 30008b6: 6785 lui a5,0x1 + 30008b8: 973e add a4,a4,a5 + 30008ba: 80872783 lw a5,-2040(a4) # 17fff808 + 30008be: 6689 lui a3,0x2 + 30008c0: 16fd addi a3,a3,-1 # 1fff + 30008c2: 8ef1 and a3,a3,a2 + 30008c4: 06c2 slli a3,a3,0x10 + 30008c6: e0010637 lui a2,0xe0010 + 30008ca: 167d addi a2,a2,-1 # e000ffff + 30008cc: 8ff1 and a5,a5,a2 + 30008ce: 8fd5 or a5,a5,a3 + 30008d0: 80f72423 sw a5,-2040(a4) + 30008d4: 18000737 lui a4,0x18000 + 30008d8: fd042783 lw a5,-48(s0) + 30008dc: 83c1 srli a5,a5,0x10 + 30008de: 86be mv a3,a5 + 30008e0: 6785 lui a5,0x1 + 30008e2: 17fd addi a5,a5,-1 # fff + 30008e4: 8ff5 and a5,a5,a3 + 30008e6: 01079613 slli a2,a5,0x10 + 30008ea: 8241 srli a2,a2,0x10 + 30008ec: 6785 lui a5,0x1 + 30008ee: 973e add a4,a4,a5 + 30008f0: 80872783 lw a5,-2040(a4) # 17fff808 + 30008f4: 6685 lui a3,0x1 + 30008f6: 16fd addi a3,a3,-1 # fff + 30008f8: 8ef1 and a3,a3,a2 + 30008fa: 767d lui a2,0xfffff + 30008fc: 8ff1 and a5,a5,a2 + 30008fe: 8fd5 or a5,a5,a3 + 3000900: 80f72423 sw a5,-2040(a4) + 3000904: fe042783 lw a5,-32(s0) + 3000908: 83e1 srli a5,a5,0x18 + 300090a: 0ff7f713 andi a4,a5,255 + 300090e: 185007b7 lui a5,0x18500 + 3000912: cb98 sw a4,16(a5) + 3000914: 18000737 lui a4,0x18000 + 3000918: fd442783 lw a5,-44(s0) + 300091c: 86be mv a3,a5 + 300091e: 6785 lui a5,0x1 + 3000920: 17fd addi a5,a5,-1 # fff + 3000922: 8ff5 and a5,a5,a3 + 3000924: 01079613 slli a2,a5,0x10 + 3000928: 8241 srli a2,a2,0x10 + 300092a: 6785 lui a5,0x1 + 300092c: 973e add a4,a4,a5 + 300092e: 80472783 lw a5,-2044(a4) # 17fff804 + 3000932: 6685 lui a3,0x1 + 3000934: 16fd addi a3,a3,-1 # fff + 3000936: 8ef1 and a3,a3,a2 + 3000938: 767d lui a2,0xfffff + 300093a: 8ff1 and a5,a5,a2 + 300093c: 8fd5 or a5,a5,a3 + 300093e: 80f72223 sw a5,-2044(a4) + 3000942: fd842783 lw a5,-40(s0) + 3000946: 83a5 srli a5,a5,0x9 + 3000948: 853e mv a0,a5 + 300094a: 3509 jal ra,300074c + 300094c: 18200737 lui a4,0x18200 + 3000950: fcc42783 lw a5,-52(s0) + 3000954: 1ff7f793 andi a5,a5,511 + 3000958: 01079693 slli a3,a5,0x10 + 300095c: 82c1 srli a3,a3,0x10 + 300095e: 531c lw a5,32(a4) + 3000960: 1ff6f693 andi a3,a3,511 + 3000964: e007f793 andi a5,a5,-512 + 3000968: 8fd5 or a5,a5,a3 + 300096a: d31c sw a5,32(a4) + 300096c: 18201737 lui a4,0x18201 + 3000970: fcc42783 lw a5,-52(s0) + 3000974: 83c1 srli a5,a5,0x10 + 3000976: 1ff7f793 andi a5,a5,511 + 300097a: 01079693 slli a3,a5,0x10 + 300097e: 82c1 srli a3,a3,0x10 + 3000980: 531c lw a5,32(a4) + 3000982: 1ff6f693 andi a3,a3,511 + 3000986: e007f793 andi a5,a5,-512 + 300098a: 8fd5 or a5,a5,a3 + 300098c: d31c sw a5,32(a4) + 300098e: fbc40793 addi a5,s0,-68 + 3000992: 863e mv a2,a5 + 3000994: 45d9 li a1,22 + 3000996: 4501 li a0,0 + 3000998: 256d jal ra,3001042 + 300099a: 18000737 lui a4,0x18000 + 300099e: fbc42783 lw a5,-68(s0) + 30009a2: 86be mv a3,a5 + 30009a4: 6789 lui a5,0x2 + 30009a6: 17fd addi a5,a5,-1 # 1fff + 30009a8: 8ff5 and a5,a5,a3 + 30009aa: 01079613 slli a2,a5,0x10 + 30009ae: 8241 srli a2,a2,0x10 + 30009b0: 6785 lui a5,0x1 + 30009b2: 973e add a4,a4,a5 + 30009b4: 81472783 lw a5,-2028(a4) # 17fff814 + 30009b8: 6689 lui a3,0x2 + 30009ba: 16fd addi a3,a3,-1 # 1fff + 30009bc: 8ef1 and a3,a3,a2 + 30009be: 06c2 slli a3,a3,0x10 + 30009c0: e0010637 lui a2,0xe0010 + 30009c4: 167d addi a2,a2,-1 # e000ffff + 30009c6: 8ff1 and a5,a5,a2 + 30009c8: 8fd5 or a5,a5,a3 + 30009ca: 80f72a23 sw a5,-2028(a4) + 30009ce: 18000737 lui a4,0x18000 + 30009d2: fbc42783 lw a5,-68(s0) + 30009d6: 83c1 srli a5,a5,0x10 + 30009d8: 86be mv a3,a5 + 30009da: 6785 lui a5,0x1 + 30009dc: 17fd addi a5,a5,-1 # fff + 30009de: 8ff5 and a5,a5,a3 + 30009e0: 01079613 slli a2,a5,0x10 + 30009e4: 8241 srli a2,a2,0x10 + 30009e6: 6785 lui a5,0x1 + 30009e8: 973e add a4,a4,a5 + 30009ea: 81472783 lw a5,-2028(a4) # 17fff814 + 30009ee: 6685 lui a3,0x1 + 30009f0: 16fd addi a3,a3,-1 # fff + 30009f2: 8ef1 and a3,a3,a2 + 30009f4: 767d lui a2,0xfffff + 30009f6: 8ff1 and a5,a5,a2 + 30009f8: 8fd5 or a5,a5,a3 + 30009fa: 80f72a23 sw a5,-2028(a4) + 30009fe: 18000737 lui a4,0x18000 + 3000a02: fc042783 lw a5,-64(s0) + 3000a06: 86be mv a3,a5 + 3000a08: 6789 lui a5,0x2 + 3000a0a: 17fd addi a5,a5,-1 # 1fff + 3000a0c: 8ff5 and a5,a5,a3 + 3000a0e: 01079613 slli a2,a5,0x10 + 3000a12: 8241 srli a2,a2,0x10 + 3000a14: 6785 lui a5,0x1 + 3000a16: 973e add a4,a4,a5 + 3000a18: 81872783 lw a5,-2024(a4) # 17fff818 + 3000a1c: 6689 lui a3,0x2 + 3000a1e: 16fd addi a3,a3,-1 # 1fff + 3000a20: 8ef1 and a3,a3,a2 + 3000a22: 06c2 slli a3,a3,0x10 + 3000a24: e0010637 lui a2,0xe0010 + 3000a28: 167d addi a2,a2,-1 # e000ffff + 3000a2a: 8ff1 and a5,a5,a2 + 3000a2c: 8fd5 or a5,a5,a3 + 3000a2e: 80f72c23 sw a5,-2024(a4) + 3000a32: 18000737 lui a4,0x18000 + 3000a36: fc042783 lw a5,-64(s0) + 3000a3a: 83c1 srli a5,a5,0x10 + 3000a3c: 86be mv a3,a5 + 3000a3e: 6785 lui a5,0x1 + 3000a40: 17fd addi a5,a5,-1 # fff + 3000a42: 8ff5 and a5,a5,a3 + 3000a44: 01079613 slli a2,a5,0x10 + 3000a48: 8241 srli a2,a2,0x10 + 3000a4a: 6785 lui a5,0x1 + 3000a4c: 973e add a4,a4,a5 + 3000a4e: 81872783 lw a5,-2024(a4) # 17fff818 + 3000a52: 6685 lui a3,0x1 + 3000a54: 16fd addi a3,a3,-1 # fff + 3000a56: 8ef1 and a3,a3,a2 + 3000a58: 767d lui a2,0xfffff + 3000a5a: 8ff1 and a5,a5,a2 + 3000a5c: 8fd5 or a5,a5,a3 + 3000a5e: 80f72c23 sw a5,-2024(a4) + 3000a62: 18000737 lui a4,0x18000 + 3000a66: fc442783 lw a5,-60(s0) + 3000a6a: 86be mv a3,a5 + 3000a6c: 6789 lui a5,0x2 + 3000a6e: 17fd addi a5,a5,-1 # 1fff + 3000a70: 8ff5 and a5,a5,a3 + 3000a72: 01079613 slli a2,a5,0x10 + 3000a76: 8241 srli a2,a2,0x10 + 3000a78: 6785 lui a5,0x1 + 3000a7a: 973e add a4,a4,a5 + 3000a7c: 81c72783 lw a5,-2020(a4) # 17fff81c + 3000a80: 6689 lui a3,0x2 + 3000a82: 16fd addi a3,a3,-1 # 1fff + 3000a84: 8ef1 and a3,a3,a2 + 3000a86: 06c2 slli a3,a3,0x10 + 3000a88: e0010637 lui a2,0xe0010 + 3000a8c: 167d addi a2,a2,-1 # e000ffff + 3000a8e: 8ff1 and a5,a5,a2 + 3000a90: 8fd5 or a5,a5,a3 + 3000a92: 80f72e23 sw a5,-2020(a4) + 3000a96: 18000737 lui a4,0x18000 + 3000a9a: fc442783 lw a5,-60(s0) + 3000a9e: 83c1 srli a5,a5,0x10 + 3000aa0: 86be mv a3,a5 + 3000aa2: 6785 lui a5,0x1 + 3000aa4: 17fd addi a5,a5,-1 # fff + 3000aa6: 8ff5 and a5,a5,a3 + 3000aa8: 01079613 slli a2,a5,0x10 + 3000aac: 8241 srli a2,a2,0x10 + 3000aae: 6785 lui a5,0x1 + 3000ab0: 973e add a4,a4,a5 + 3000ab2: 81c72783 lw a5,-2020(a4) # 17fff81c + 3000ab6: 6685 lui a3,0x1 + 3000ab8: 16fd addi a3,a3,-1 # fff + 3000aba: 8ef1 and a3,a3,a2 + 3000abc: 767d lui a2,0xfffff + 3000abe: 8ff1 and a5,a5,a2 + 3000ac0: 8fd5 or a5,a5,a3 + 3000ac2: 80f72e23 sw a5,-2020(a4) + 3000ac6: 18000737 lui a4,0x18000 + 3000aca: fc842783 lw a5,-56(s0) + 3000ace: 86be mv a3,a5 + 3000ad0: 6789 lui a5,0x2 + 3000ad2: 17fd addi a5,a5,-1 # 1fff + 3000ad4: 8ff5 and a5,a5,a3 + 3000ad6: 01079613 slli a2,a5,0x10 + 3000ada: 8241 srli a2,a2,0x10 + 3000adc: 6785 lui a5,0x1 + 3000ade: 973e add a4,a4,a5 + 3000ae0: 82072783 lw a5,-2016(a4) # 17fff820 + 3000ae4: 6689 lui a3,0x2 + 3000ae6: 16fd addi a3,a3,-1 # 1fff + 3000ae8: 8ef1 and a3,a3,a2 + 3000aea: 06c2 slli a3,a3,0x10 + 3000aec: e0010637 lui a2,0xe0010 + 3000af0: 167d addi a2,a2,-1 # e000ffff + 3000af2: 8ff1 and a5,a5,a2 + 3000af4: 8fd5 or a5,a5,a3 + 3000af6: 82f72023 sw a5,-2016(a4) + 3000afa: 18000737 lui a4,0x18000 + 3000afe: fc842783 lw a5,-56(s0) + 3000b02: 83c1 srli a5,a5,0x10 + 3000b04: 86be mv a3,a5 + 3000b06: 6785 lui a5,0x1 + 3000b08: 17fd addi a5,a5,-1 # fff + 3000b0a: 8ff5 and a5,a5,a3 + 3000b0c: 01079613 slli a2,a5,0x10 + 3000b10: 8241 srli a2,a2,0x10 + 3000b12: 6785 lui a5,0x1 + 3000b14: 973e add a4,a4,a5 + 3000b16: 82072783 lw a5,-2016(a4) # 17fff820 + 3000b1a: 6685 lui a3,0x1 + 3000b1c: 16fd addi a3,a3,-1 # fff + 3000b1e: 8ef1 and a3,a3,a2 + 3000b20: 767d lui a2,0xfffff + 3000b22: 8ff1 and a5,a5,a2 + 3000b24: 8fd5 or a5,a5,a3 + 3000b26: 82f72023 sw a5,-2016(a4) + 3000b2a: fac40793 addi a5,s0,-84 + 3000b2e: 863e mv a2,a5 + 3000b30: 45dd li a1,23 + 3000b32: 4501 li a0,0 + 3000b34: 2339 jal ra,3001042 + 3000b36: 18000737 lui a4,0x18000 + 3000b3a: fac42783 lw a5,-84(s0) + 3000b3e: 86be mv a3,a5 + 3000b40: 6789 lui a5,0x2 + 3000b42: 17fd addi a5,a5,-1 # 1fff + 3000b44: 8ff5 and a5,a5,a3 + 3000b46: 01079613 slli a2,a5,0x10 + 3000b4a: 8241 srli a2,a2,0x10 + 3000b4c: 6785 lui a5,0x1 + 3000b4e: 973e add a4,a4,a5 + 3000b50: 82472783 lw a5,-2012(a4) # 17fff824 + 3000b54: 6689 lui a3,0x2 + 3000b56: 16fd addi a3,a3,-1 # 1fff + 3000b58: 8ef1 and a3,a3,a2 + 3000b5a: 06c2 slli a3,a3,0x10 + 3000b5c: e0010637 lui a2,0xe0010 + 3000b60: 167d addi a2,a2,-1 # e000ffff + 3000b62: 8ff1 and a5,a5,a2 + 3000b64: 8fd5 or a5,a5,a3 + 3000b66: 82f72223 sw a5,-2012(a4) + 3000b6a: 18000737 lui a4,0x18000 + 3000b6e: fac42783 lw a5,-84(s0) + 3000b72: 83c1 srli a5,a5,0x10 + 3000b74: 86be mv a3,a5 + 3000b76: 6785 lui a5,0x1 + 3000b78: 17fd addi a5,a5,-1 # fff + 3000b7a: 8ff5 and a5,a5,a3 + 3000b7c: 01079613 slli a2,a5,0x10 + 3000b80: 8241 srli a2,a2,0x10 + 3000b82: 6785 lui a5,0x1 + 3000b84: 973e add a4,a4,a5 + 3000b86: 82472783 lw a5,-2012(a4) # 17fff824 + 3000b8a: 6685 lui a3,0x1 + 3000b8c: 16fd addi a3,a3,-1 # fff + 3000b8e: 8ef1 and a3,a3,a2 + 3000b90: 767d lui a2,0xfffff + 3000b92: 8ff1 and a5,a5,a2 + 3000b94: 8fd5 or a5,a5,a3 + 3000b96: 82f72223 sw a5,-2012(a4) + 3000b9a: 18000737 lui a4,0x18000 + 3000b9e: fb042783 lw a5,-80(s0) + 3000ba2: 86be mv a3,a5 + 3000ba4: 6789 lui a5,0x2 + 3000ba6: 17fd addi a5,a5,-1 # 1fff + 3000ba8: 8ff5 and a5,a5,a3 + 3000baa: 01079613 slli a2,a5,0x10 + 3000bae: 8241 srli a2,a2,0x10 + 3000bb0: 6785 lui a5,0x1 + 3000bb2: 973e add a4,a4,a5 + 3000bb4: 82872783 lw a5,-2008(a4) # 17fff828 + 3000bb8: 6689 lui a3,0x2 + 3000bba: 16fd addi a3,a3,-1 # 1fff + 3000bbc: 8ef1 and a3,a3,a2 + 3000bbe: 06c2 slli a3,a3,0x10 + 3000bc0: e0010637 lui a2,0xe0010 + 3000bc4: 167d addi a2,a2,-1 # e000ffff + 3000bc6: 8ff1 and a5,a5,a2 + 3000bc8: 8fd5 or a5,a5,a3 + 3000bca: 82f72423 sw a5,-2008(a4) + 3000bce: 18000737 lui a4,0x18000 + 3000bd2: fb042783 lw a5,-80(s0) + 3000bd6: 83c1 srli a5,a5,0x10 + 3000bd8: 86be mv a3,a5 + 3000bda: 6785 lui a5,0x1 + 3000bdc: 17fd addi a5,a5,-1 # fff + 3000bde: 8ff5 and a5,a5,a3 + 3000be0: 01079613 slli a2,a5,0x10 + 3000be4: 8241 srli a2,a2,0x10 + 3000be6: 6785 lui a5,0x1 + 3000be8: 973e add a4,a4,a5 + 3000bea: 82872783 lw a5,-2008(a4) # 17fff828 + 3000bee: 6685 lui a3,0x1 + 3000bf0: 16fd addi a3,a3,-1 # fff + 3000bf2: 8ef1 and a3,a3,a2 + 3000bf4: 767d lui a2,0xfffff + 3000bf6: 8ff1 and a5,a5,a2 + 3000bf8: 8fd5 or a5,a5,a3 + 3000bfa: 82f72423 sw a5,-2008(a4) + 3000bfe: 18000737 lui a4,0x18000 + 3000c02: fb442783 lw a5,-76(s0) + 3000c06: 86be mv a3,a5 + 3000c08: 6789 lui a5,0x2 + 3000c0a: 17fd addi a5,a5,-1 # 1fff + 3000c0c: 8ff5 and a5,a5,a3 + 3000c0e: 01079613 slli a2,a5,0x10 + 3000c12: 8241 srli a2,a2,0x10 + 3000c14: 6785 lui a5,0x1 + 3000c16: 973e add a4,a4,a5 + 3000c18: 82c72783 lw a5,-2004(a4) # 17fff82c + 3000c1c: 6689 lui a3,0x2 + 3000c1e: 16fd addi a3,a3,-1 # 1fff + 3000c20: 8ef1 and a3,a3,a2 + 3000c22: 06c2 slli a3,a3,0x10 + 3000c24: e0010637 lui a2,0xe0010 + 3000c28: 167d addi a2,a2,-1 # e000ffff + 3000c2a: 8ff1 and a5,a5,a2 + 3000c2c: 8fd5 or a5,a5,a3 + 3000c2e: 82f72623 sw a5,-2004(a4) + 3000c32: 18000737 lui a4,0x18000 + 3000c36: fb442783 lw a5,-76(s0) + 3000c3a: 83c1 srli a5,a5,0x10 + 3000c3c: 86be mv a3,a5 + 3000c3e: 6785 lui a5,0x1 + 3000c40: 17fd addi a5,a5,-1 # fff + 3000c42: 8ff5 and a5,a5,a3 + 3000c44: 01079613 slli a2,a5,0x10 + 3000c48: 8241 srli a2,a2,0x10 + 3000c4a: 6785 lui a5,0x1 + 3000c4c: 973e add a4,a4,a5 + 3000c4e: 82c72783 lw a5,-2004(a4) # 17fff82c + 3000c52: 6685 lui a3,0x1 + 3000c54: 16fd addi a3,a3,-1 # fff + 3000c56: 8ef1 and a3,a3,a2 + 3000c58: 767d lui a2,0xfffff + 3000c5a: 8ff1 and a5,a5,a2 + 3000c5c: 8fd5 or a5,a5,a3 + 3000c5e: 82f72623 sw a5,-2004(a4) + 3000c62: 18000737 lui a4,0x18000 + 3000c66: fb842783 lw a5,-72(s0) + 3000c6a: 86be mv a3,a5 + 3000c6c: 6789 lui a5,0x2 + 3000c6e: 17fd addi a5,a5,-1 # 1fff + 3000c70: 8ff5 and a5,a5,a3 + 3000c72: 01079613 slli a2,a5,0x10 + 3000c76: 8241 srli a2,a2,0x10 + 3000c78: 6785 lui a5,0x1 + 3000c7a: 973e add a4,a4,a5 + 3000c7c: 83072783 lw a5,-2000(a4) # 17fff830 + 3000c80: 6689 lui a3,0x2 + 3000c82: 16fd addi a3,a3,-1 # 1fff + 3000c84: 8ef1 and a3,a3,a2 + 3000c86: 06c2 slli a3,a3,0x10 + 3000c88: e0010637 lui a2,0xe0010 + 3000c8c: 167d addi a2,a2,-1 # e000ffff + 3000c8e: 8ff1 and a5,a5,a2 + 3000c90: 8fd5 or a5,a5,a3 + 3000c92: 82f72823 sw a5,-2000(a4) + 3000c96: 18000737 lui a4,0x18000 + 3000c9a: fb842783 lw a5,-72(s0) + 3000c9e: 83c1 srli a5,a5,0x10 + 3000ca0: 86be mv a3,a5 + 3000ca2: 6785 lui a5,0x1 + 3000ca4: 17fd addi a5,a5,-1 # fff + 3000ca6: 8ff5 and a5,a5,a3 + 3000ca8: 01079613 slli a2,a5,0x10 + 3000cac: 8241 srli a2,a2,0x10 + 3000cae: 6785 lui a5,0x1 + 3000cb0: 973e add a4,a4,a5 + 3000cb2: 83072783 lw a5,-2000(a4) # 17fff830 + 3000cb6: 6685 lui a3,0x1 + 3000cb8: 16fd addi a3,a3,-1 # fff + 3000cba: 8ef1 and a3,a3,a2 + 3000cbc: 767d lui a2,0xfffff + 3000cbe: 8ff1 and a5,a5,a2 + 3000cc0: 8fd5 or a5,a5,a3 + 3000cc2: 82f72823 sw a5,-2000(a4) + 3000cc6: 0001 nop + 3000cc8: 40f6 lw ra,92(sp) + 3000cca: 4466 lw s0,88(sp) + 3000ccc: 6125 addi sp,sp,96 + 3000cce: 8082 ret + +03000cd0 : + 3000cd0: 3720006f j 3001042 + +03000cd4 : + 3000cd4: 1141 addi sp,sp,-16 + 3000cd6: c606 sw ra,12(sp) + 3000cd8: c422 sw s0,8(sp) + 3000cda: 0800 addi s0,sp,16 + 3000cdc: 3c79 jal ra,300077a + 3000cde: 87aa mv a5,a0 + 3000ce0: 0017c793 xori a5,a5,1 + 3000ce4: 9f81 uxtb a5 + 3000ce6: eb9d bnez a5,3000d1c + 3000ce8: 4585 li a1,1 + 3000cea: 18000537 lui a0,0x18000 + 3000cee: 2849 jal ra,3000d80 + 3000cf0: 4585 li a1,1 + 3000cf2: 18200537 lui a0,0x18200 + 3000cf6: 2069 jal ra,3000d80 + 3000cf8: 4585 li a1,1 + 3000cfa: 18201537 lui a0,0x18201 + 3000cfe: 2049 jal ra,3000d80 + 3000d00: 34d1 jal ra,30007c4 + 3000d02: 4581 li a1,0 + 3000d04: 18000537 lui a0,0x18000 + 3000d08: 28a5 jal ra,3000d80 + 3000d0a: 4581 li a1,0 + 3000d0c: 18200537 lui a0,0x18200 + 3000d10: 2885 jal ra,3000d80 + 3000d12: 4581 li a1,0 + 3000d14: 18201537 lui a0,0x18201 + 3000d18: 20a5 jal ra,3000d80 + 3000d1a: a011 j 3000d1e + 3000d1c: 0001 nop + 3000d1e: 40b2 lw ra,12(sp) + 3000d20: 4422 lw s0,8(sp) + 3000d22: 0141 addi sp,sp,16 + 3000d24: 8082 ret + +03000d26 : + 3000d26: 1141 addi sp,sp,-16 + 3000d28: c606 sw ra,12(sp) + 3000d2a: c422 sw s0,8(sp) + 3000d2c: 0800 addi s0,sp,16 + 3000d2e: 4585 li a1,1 + 3000d30: 18100537 lui a0,0x18100 + 3000d34: 20b1 jal ra,3000d80 + 3000d36: 18100737 lui a4,0x18100 + 3000d3a: 531c lw a5,32(a4) + 3000d3c: 66c1 lui a3,0x10 + 3000d3e: 8fd5 or a5,a5,a3 + 3000d40: d31c sw a5,32(a4) + 3000d42: 18100737 lui a4,0x18100 + 3000d46: 431c lw a5,0(a4) + 3000d48: 0017e793 ori a5,a5,1 + 3000d4c: c31c sw a5,0(a4) + 3000d4e: 000f47b7 lui a5,0xf4 + 3000d52: 24078593 addi a1,a5,576 # f4240 + 3000d56: 0c800513 li a0,200 + 3000d5a: 234d jal ra,30012fc + 3000d5c: 18100737 lui a4,0x18100 + 3000d60: 531c lw a5,32(a4) + 3000d62: 0017e793 ori a5,a5,1 + 3000d66: d31c sw a5,32(a4) + 3000d68: 000f47b7 lui a5,0xf4 + 3000d6c: 24078593 addi a1,a5,576 # f4240 + 3000d70: 02800513 li a0,40 + 3000d74: 2361 jal ra,30012fc + 3000d76: 0001 nop + 3000d78: 40b2 lw ra,12(sp) + 3000d7a: 4422 lw s0,8(sp) + 3000d7c: 0141 addi sp,sp,16 + 3000d7e: 8082 ret + +03000d80 : + 3000d80: 0d10106f j 3002650 + +03000d84 : + 3000d84: 715d addi sp,sp,-80 + 3000d86: c686 sw ra,76(sp) + 3000d88: c4a2 sw s0,72(sp) + 3000d8a: 0880 addi s0,sp,80 + 3000d8c: faa42e23 sw a0,-68(s0) + 3000d90: 100007b7 lui a5,0x10000 + 3000d94: fcf42423 sw a5,-56(s0) + 3000d98: fbc42783 lw a5,-68(s0) + 3000d9c: fef42023 sw a5,-32(s0) + 3000da0: fe042703 lw a4,-32(s0) + 3000da4: 4785 li a5,1 + 3000da6: 00f71663 bne a4,a5,3000db2 + 3000daa: 3e800593 li a1,1000 + 3000dae: 4529 li a0,10 + 3000db0: 23b1 jal ra,30012fc + 3000db2: fc840793 addi a5,s0,-56 + 3000db6: 853e mv a0,a5 + 3000db8: 58e010ef jal ra,3002346 + 3000dbc: 0001 nop + 3000dbe: 40b6 lw ra,76(sp) + 3000dc0: 4426 lw s0,72(sp) + 3000dc2: 6161 addi sp,sp,80 + 3000dc4: 8082 ret + +03000dc6 : + 3000dc6: 7179 addi sp,sp,-48 + 3000dc8: d622 sw s0,44(sp) + 3000dca: 1800 addi s0,sp,48 + 3000dcc: fca42e23 sw a0,-36(s0) + 3000dd0: fcb42c23 sw a1,-40(s0) + 3000dd4: fdc42783 lw a5,-36(s0) + 3000dd8: fef42423 sw a5,-24(s0) + 3000ddc: fe842703 lw a4,-24(s0) + 3000de0: 023c37b7 lui a5,0x23c3 + 3000de4: 45f78793 addi a5,a5,1119 # 23c345f + 3000de8: 00e7e863 bltu a5,a4,3000df8 + 3000dec: 023c37b7 lui a5,0x23c3 + 3000df0: 46078793 addi a5,a5,1120 # 23c3460 + 3000df4: fef42423 sw a5,-24(s0) + 3000df8: fe842703 lw a4,-24(s0) + 3000dfc: 023c37b7 lui a5,0x23c3 + 3000e00: 46078793 addi a5,a5,1120 # 23c3460 + 3000e04: 02f777b3 remu a5,a4,a5 + 3000e08: ef81 bnez a5,3000e20 + 3000e0a: fe842703 lw a4,-24(s0) + 3000e0e: 023c37b7 lui a5,0x23c3 + 3000e12: 46078793 addi a5,a5,1120 # 23c3460 + 3000e16: 02f757b3 divu a5,a4,a5 + 3000e1a: fef42623 sw a5,-20(s0) + 3000e1e: a821 j 3000e36 + 3000e20: fe842703 lw a4,-24(s0) + 3000e24: 023c37b7 lui a5,0x23c3 + 3000e28: 46078793 addi a5,a5,1120 # 23c3460 + 3000e2c: 02f757b3 divu a5,a4,a5 + 3000e30: 0785 addi a5,a5,1 + 3000e32: fef42623 sw a5,-20(s0) + 3000e36: fec42703 lw a4,-20(s0) + 3000e3a: 4791 li a5,4 + 3000e3c: 00e7f563 bgeu a5,a4,3000e46 + 3000e40: 4791 li a5,4 + 3000e42: fef42623 sw a5,-20(s0) + 3000e46: fd842783 lw a5,-40(s0) + 3000e4a: fec42703 lw a4,-20(s0) + 3000e4e: c398 sw a4,0(a5) + 3000e50: 0001 nop + 3000e52: 5432 lw s0,44(sp) + 3000e54: 6145 addi sp,sp,48 + 3000e56: 8082 ret + +03000e58 : + 3000e58: 7179 addi sp,sp,-48 + 3000e5a: d606 sw ra,44(sp) + 3000e5c: d422 sw s0,40(sp) + 3000e5e: 1800 addi s0,sp,48 + 3000e60: fca42e23 sw a0,-36(s0) + 3000e64: fdc42783 lw a5,-36(s0) + 3000e68: 4705 li a4,1 + 3000e6a: 02e78063 beq a5,a4,3000e8a + 3000e6e: 4705 li a4,1 + 3000e70: 00e7e663 bltu a5,a4,3000e7c + 3000e74: 4709 li a4,2 + 3000e76: 02e78163 beq a5,a4,3000e98 + 3000e7a: a025 j 3000ea2 + 3000e7c: 017d87b7 lui a5,0x17d8 + 3000e80: 84078793 addi a5,a5,-1984 # 17d7840 + 3000e84: fef42623 sw a5,-20(s0) + 3000e88: a01d j 3000eae + 3000e8a: 01c9c7b7 lui a5,0x1c9c + 3000e8e: 38078793 addi a5,a5,896 # 1c9c380 + 3000e92: fef42623 sw a5,-20(s0) + 3000e96: a821 j 3000eae + 3000e98: 5d0010ef jal ra,3002468 + 3000e9c: fea42623 sw a0,-20(s0) + 3000ea0: a039 j 3000eae + 3000ea2: 67a1 lui a5,0x8 + 3000ea4: d0078793 addi a5,a5,-768 # 7d00 + 3000ea8: fef42623 sw a5,-20(s0) + 3000eac: 0001 nop + 3000eae: fec42783 lw a5,-20(s0) + 3000eb2: 853e mv a0,a5 + 3000eb4: 50b2 lw ra,44(sp) + 3000eb6: 5422 lw s0,40(sp) + 3000eb8: 6145 addi sp,sp,48 + 3000eba: 8082 ret + +03000ebc : + 3000ebc: 7179 addi sp,sp,-48 + 3000ebe: d606 sw ra,44(sp) + 3000ec0: d422 sw s0,40(sp) + 3000ec2: 1800 addi s0,sp,48 + 3000ec4: fca42e23 sw a0,-36(s0) + 3000ec8: 147107b7 lui a5,0x14710 + 3000ecc: fef42623 sw a5,-20(s0) + 3000ed0: fdc42503 lw a0,-36(s0) + 3000ed4: 3751 jal ra,3000e58 + 3000ed6: fea42423 sw a0,-24(s0) + 3000eda: fec42703 lw a4,-20(s0) + 3000ede: 6785 lui a5,0x1 + 3000ee0: 97ba add a5,a5,a4 + 3000ee2: 9407a783 lw a5,-1728(a5) # 940 + 3000ee6: fef42223 sw a5,-28(s0) + 3000eea: fe040793 addi a5,s0,-32 + 3000eee: 85be mv a1,a5 + 3000ef0: fe842503 lw a0,-24(s0) + 3000ef4: 3dc9 jal ra,3000dc6 + 3000ef6: fe042783 lw a5,-32(s0) + 3000efa: 8bbd andi a5,a5,15 + 3000efc: 0ff7f713 andi a4,a5,255 + 3000f00: fe442783 lw a5,-28(s0) + 3000f04: 8b3d andi a4,a4,15 + 3000f06: 0712 slli a4,a4,0x4 + 3000f08: f0f7f793 andi a5,a5,-241 + 3000f0c: 8fd9 or a5,a5,a4 + 3000f0e: fef42223 sw a5,-28(s0) + 3000f12: fe442783 lw a5,-28(s0) + 3000f16: 00100737 lui a4,0x100 + 3000f1a: 8fd9 or a5,a5,a4 + 3000f1c: fef42223 sw a5,-28(s0) + 3000f20: fe442783 lw a5,-28(s0) + 3000f24: 00400737 lui a4,0x400 + 3000f28: 8fd9 or a5,a5,a4 + 3000f2a: fef42223 sw a5,-28(s0) + 3000f2e: fe442783 lw a5,-28(s0) + 3000f32: 00400737 lui a4,0x400 + 3000f36: 8fd9 or a5,a5,a4 + 3000f38: fef42223 sw a5,-28(s0) + 3000f3c: fe442783 lw a5,-28(s0) + 3000f40: 00100737 lui a4,0x100 + 3000f44: 8fd9 or a5,a5,a4 + 3000f46: fef42223 sw a5,-28(s0) + 3000f4a: fe442703 lw a4,-28(s0) + 3000f4e: fec42683 lw a3,-20(s0) + 3000f52: 6785 lui a5,0x1 + 3000f54: 97b6 add a5,a5,a3 + 3000f56: 94e7a023 sw a4,-1728(a5) # 940 + 3000f5a: 0001 nop + 3000f5c: fec42703 lw a4,-20(s0) + 3000f60: 6785 lui a5,0x1 + 3000f62: 97ba add a5,a5,a4 + 3000f64: 9407a783 lw a5,-1728(a5) # 940 + 3000f68: 83d1 srli a5,a5,0x14 + 3000f6a: 8b85 andi a5,a5,1 + 3000f6c: 0ff7f713 andi a4,a5,255 + 3000f70: 4785 li a5,1 + 3000f72: fef705e3 beq a4,a5,3000f5c + 3000f76: 0001 nop + 3000f78: 50b2 lw ra,44(sp) + 3000f7a: 5422 lw s0,40(sp) + 3000f7c: 6145 addi sp,sp,48 + 3000f7e: 8082 ret + +03000f80 : + 3000f80: 1141 addi sp,sp,-16 + 3000f82: c622 sw s0,12(sp) + 3000f84: 0800 addi s0,sp,16 + 3000f86: 143807b7 lui a5,0x14380 + 3000f8a: 0007a023 sw zero,0(a5) # 14380000 + 3000f8e: 14380737 lui a4,0x14380 + 3000f92: 431c lw a5,0(a4) + 3000f94: 0017e793 ori a5,a5,1 + 3000f98: c31c sw a5,0(a4) + 3000f9a: 0001 nop + 3000f9c: 4432 lw s0,12(sp) + 3000f9e: 0141 addi sp,sp,16 + 3000fa0: 8082 ret + +03000fa2 : + 3000fa2: 1141 addi sp,sp,-16 + 3000fa4: c606 sw ra,12(sp) + 3000fa6: c422 sw s0,8(sp) + 3000fa8: 0800 addi s0,sp,16 + 3000faa: 14380537 lui a0,0x14380 + 3000fae: 5bc010ef jal ra,300256a + 3000fb2: 87aa mv a5,a0 + 3000fb4: 853e mv a0,a5 + 3000fb6: 40b2 lw ra,12(sp) + 3000fb8: 4422 lw s0,8(sp) + 3000fba: 0141 addi sp,sp,16 + 3000fbc: 8082 ret + +03000fbe : + 3000fbe: 1101 addi sp,sp,-32 + 3000fc0: ce22 sw s0,28(sp) + 3000fc2: 1000 addi s0,sp,32 + 3000fc4: fea42623 sw a0,-20(s0) + 3000fc8: fec42783 lw a5,-20(s0) + 3000fcc: 1007a783 lw a5,256(a5) + 3000fd0: 83c1 srli a5,a5,0x10 + 3000fd2: 8b85 andi a5,a5,1 + 3000fd4: 9f81 uxtb a5 + 3000fd6: e38d bnez a5,3000ff8 + 3000fd8: fec42783 lw a5,-20(s0) + 3000fdc: 1007a783 lw a5,256(a5) + 3000fe0: 83cd srli a5,a5,0x13 + 3000fe2: 8b85 andi a5,a5,1 + 3000fe4: 9f81 uxtb a5 + 3000fe6: eb89 bnez a5,3000ff8 + 3000fe8: fec42783 lw a5,-20(s0) + 3000fec: 1007a783 lw a5,256(a5) + 3000ff0: 83d1 srli a5,a5,0x14 + 3000ff2: 8b85 andi a5,a5,1 + 3000ff4: 9f81 uxtb a5 + 3000ff6: c3a9 beqz a5,3001038 + 3000ff8: fec42703 lw a4,-20(s0) + 3000ffc: 10c72783 lw a5,268(a4) # 1438010c + 3001000: 000806b7 lui a3,0x80 + 3001004: 8fd5 or a5,a5,a3 + 3001006: 10f72623 sw a5,268(a4) + 300100a: fec42703 lw a4,-20(s0) + 300100e: 10c72783 lw a5,268(a4) + 3001012: 66c1 lui a3,0x10 + 3001014: 8fd5 or a5,a5,a3 + 3001016: 10f72623 sw a5,268(a4) + 300101a: fec42703 lw a4,-20(s0) + 300101e: 10c72783 lw a5,268(a4) + 3001022: 001006b7 lui a3,0x100 + 3001026: 8fd5 or a5,a5,a3 + 3001028: 10f72623 sw a5,268(a4) + 300102c: fec42783 lw a5,-20(s0) + 3001030: 2007a023 sw zero,512(a5) + 3001034: 4785 li a5,1 + 3001036: a011 j 300103a + 3001038: 4781 li a5,0 + 300103a: 853e mv a0,a5 + 300103c: 4472 lw s0,28(sp) + 300103e: 6105 addi sp,sp,32 + 3001040: 8082 ret + +03001042 : + 3001042: 7179 addi sp,sp,-48 + 3001044: d606 sw ra,44(sp) + 3001046: d422 sw s0,40(sp) + 3001048: 1800 addi s0,sp,48 + 300104a: fca42e23 sw a0,-36(s0) + 300104e: fcb42c23 sw a1,-40(s0) + 3001052: fcc42a23 sw a2,-44(s0) + 3001056: 147107b7 lui a5,0x14710 + 300105a: fef42423 sw a5,-24(s0) + 300105e: fd442783 lw a5,-44(s0) + 3001062: e399 bnez a5,3001068 + 3001064: 4785 li a5,1 + 3001066: aa15 j 300119a + 3001068: fdc42703 lw a4,-36(s0) + 300106c: 4785 li a5,1 + 300106e: 00e7e763 bltu a5,a4,300107c + 3001072: fd842703 lw a4,-40(s0) + 3001076: 47e5 li a5,25 + 3001078: 00e7f463 bgeu a5,a4,3001080 + 300107c: 4785 li a5,1 + 300107e: aa31 j 300119a + 3001080: fe842783 lw a5,-24(s0) + 3001084: 439c lw a5,0(a5) + 3001086: 8b85 andi a5,a5,1 + 3001088: 9f81 uxtb a5 + 300108a: c399 beqz a5,3001090 + 300108c: 4785 li a5,1 + 300108e: a231 j 300119a + 3001090: fe842783 lw a5,-24(s0) + 3001094: fedcc737 lui a4,0xfedcc + 3001098: a9870713 addi a4,a4,-1384 # fedcba98 + 300109c: 20e7a023 sw a4,512(a5) # 14710200 + 30010a0: fdc42783 lw a5,-36(s0) + 30010a4: e781 bnez a5,30010ac + 30010a6: 008007b7 lui a5,0x800 + 30010aa: a019 j 30010b0 + 30010ac: 008017b7 lui a5,0x801 + 30010b0: fef42223 sw a5,-28(s0) + 30010b4: fd842783 lw a5,-40(s0) + 30010b8: 0792 slli a5,a5,0x4 + 30010ba: fe442703 lw a4,-28(s0) + 30010be: 97ba add a5,a5,a4 + 30010c0: fef42223 sw a5,-28(s0) + 30010c4: fe442783 lw a5,-28(s0) + 30010c8: 0027d713 srli a4,a5,0x2 + 30010cc: 004007b7 lui a5,0x400 + 30010d0: 17fd addi a5,a5,-1 # 3fffff + 30010d2: 00f77633 and a2,a4,a5 + 30010d6: fe842703 lw a4,-24(s0) + 30010da: 435c lw a5,4(a4) + 30010dc: 004006b7 lui a3,0x400 + 30010e0: 16fd addi a3,a3,-1 # 3fffff + 30010e2: 8ef1 and a3,a3,a2 + 30010e4: 068a slli a3,a3,0x2 + 30010e6: ff000637 lui a2,0xff000 + 30010ea: 060d addi a2,a2,3 # ff000003 + 30010ec: 8ff1 and a5,a5,a2 + 30010ee: 8fd5 or a5,a5,a3 + 30010f0: c35c sw a5,4(a4) + 30010f2: fe842703 lw a4,-24(s0) + 30010f6: 431c lw a5,0(a4) + 30010f8: 8ff7f793 andi a5,a5,-1793 + 30010fc: 1007e793 ori a5,a5,256 + 3001100: c31c sw a5,0(a4) + 3001102: fe842703 lw a4,-24(s0) + 3001106: 431c lw a5,0(a4) + 3001108: d00006b7 lui a3,0xd0000 + 300110c: 16fd addi a3,a3,-1 # cfffffff + 300110e: 8efd and a3,a3,a5 + 3001110: 100007b7 lui a5,0x10000 + 3001114: 8fd5 or a5,a5,a3 + 3001116: c31c sw a5,0(a4) + 3001118: fe842703 lw a4,-24(s0) + 300111c: 431c lw a5,0(a4) + 300111e: 0017e793 ori a5,a5,1 + 3001122: c31c sw a5,0(a4) + 3001124: 0001 nop + 3001126: fe842783 lw a5,-24(s0) + 300112a: 439c lw a5,0(a5) + 300112c: 8b85 andi a5,a5,1 + 300112e: 9f81 uxtb a5 + 3001130: fbfd bnez a5,3001126 + 3001132: 0001 nop + 3001134: fe842783 lw a5,-24(s0) + 3001138: 439c lw a5,0(a5) + 300113a: 8399 srli a5,a5,0x6 + 300113c: 8b8d andi a5,a5,3 + 300113e: 9f81 uxtb a5 + 3001140: fbf5 bnez a5,3001134 + 3001142: fe842503 lw a0,-24(s0) + 3001146: 3da5 jal ra,3000fbe + 3001148: 87aa mv a5,a0 + 300114a: c399 beqz a5,3001150 + 300114c: 4785 li a5,1 + 300114e: a0b1 j 300119a + 3001150: fe042623 sw zero,-20(s0) + 3001154: a00d j 3001176 + 3001156: fe842783 lw a5,-24(s0) + 300115a: 6007a703 lw a4,1536(a5) # 10000600 + 300115e: fd442683 lw a3,-44(s0) + 3001162: fec42783 lw a5,-20(s0) + 3001166: 078a slli a5,a5,0x2 + 3001168: 97b6 add a5,a5,a3 + 300116a: c398 sw a4,0(a5) + 300116c: fec42783 lw a5,-20(s0) + 3001170: 0785 addi a5,a5,1 + 3001172: fef42623 sw a5,-20(s0) + 3001176: fec42703 lw a4,-20(s0) + 300117a: 478d li a5,3 + 300117c: fce7fde3 bgeu a5,a4,3001156 + 3001180: fe842703 lw a4,-24(s0) + 3001184: 10c72783 lw a5,268(a4) + 3001188: 0107e793 ori a5,a5,16 + 300118c: 10f72623 sw a5,268(a4) + 3001190: fe842783 lw a5,-24(s0) + 3001194: 2007a023 sw zero,512(a5) + 3001198: 4781 li a5,0 + 300119a: 853e mv a0,a5 + 300119c: 50b2 lw ra,44(sp) + 300119e: 5422 lw s0,40(sp) + 30011a0: 6145 addi sp,sp,48 + 30011a2: 8082 ret + +030011a4 : + 30011a4: 7179 addi sp,sp,-48 + 30011a6: d622 sw s0,44(sp) + 30011a8: 1800 addi s0,sp,48 + 30011aa: fca42e23 sw a0,-36(s0) + 30011ae: fe042623 sw zero,-20(s0) + 30011b2: a081 j 30011f2 + 30011b4: 030087b7 lui a5,0x3008 + 30011b8: 6c878713 addi a4,a5,1736 # 30086c8 + 30011bc: fec42683 lw a3,-20(s0) + 30011c0: 47b1 li a5,12 + 30011c2: 02f687b3 mul a5,a3,a5 + 30011c6: 97ba add a5,a5,a4 + 30011c8: 439c lw a5,0(a5) + 30011ca: fdc42703 lw a4,-36(s0) + 30011ce: 00f71d63 bne a4,a5,30011e8 + 30011d2: fec42703 lw a4,-20(s0) + 30011d6: 47b1 li a5,12 + 30011d8: 02f70733 mul a4,a4,a5 + 30011dc: 030087b7 lui a5,0x3008 + 30011e0: 6c878793 addi a5,a5,1736 # 30086c8 + 30011e4: 97ba add a5,a5,a4 + 30011e6: a829 j 3001200 + 30011e8: fec42783 lw a5,-20(s0) + 30011ec: 0785 addi a5,a5,1 + 30011ee: fef42623 sw a5,-20(s0) + 30011f2: fec42703 lw a4,-20(s0) + 30011f6: 02d00793 li a5,45 + 30011fa: fae7fde3 bgeu a5,a4,30011b4 + 30011fe: 4781 li a5,0 + 3001200: 853e mv a0,a5 + 3001202: 5432 lw s0,44(sp) + 3001204: 6145 addi sp,sp,48 + 3001206: 8082 ret + +03001208 : + 3001208: 1101 addi sp,sp,-32 + 300120a: ce22 sw s0,28(sp) + 300120c: 1000 addi s0,sp,32 + 300120e: fea42623 sw a0,-20(s0) + 3001212: feb42423 sw a1,-24(s0) + 3001216: 0001 nop + 3001218: 4472 lw s0,28(sp) + 300121a: 6105 addi sp,sp,32 + 300121c: 8082 ret + +0300121e : + 300121e: 1141 addi sp,sp,-16 + 3001220: c622 sw s0,12(sp) + 3001222: 0800 addi s0,sp,16 + 3001224: 143807b7 lui a5,0x14380 + 3001228: 479c lw a5,8(a5) + 300122a: 853e mv a0,a5 + 300122c: 4432 lw s0,12(sp) + 300122e: 0141 addi sp,sp,16 + 3001230: 8082 ret + +03001232 : + 3001232: 7179 addi sp,sp,-48 + 3001234: d606 sw ra,44(sp) + 3001236: d422 sw s0,40(sp) + 3001238: 1800 addi s0,sp,48 + 300123a: fca42e23 sw a0,-36(s0) + 300123e: 37c5 jal ra,300121e + 3001240: fea42623 sw a0,-20(s0) + 3001244: 3bb9 jal ra,3000fa2 + 3001246: 872a mv a4,a0 + 3001248: 000f47b7 lui a5,0xf4 + 300124c: 24078793 addi a5,a5,576 # f4240 + 3001250: 02f757b3 divu a5,a4,a5 + 3001254: fdc42703 lw a4,-36(s0) + 3001258: 02f707b3 mul a5,a4,a5 + 300125c: fef42423 sw a5,-24(s0) + 3001260: 3f7d jal ra,300121e + 3001262: fea42223 sw a0,-28(s0) + 3001266: fe442703 lw a4,-28(s0) + 300126a: fec42783 lw a5,-20(s0) + 300126e: 40f707b3 sub a5,a4,a5 + 3001272: fef42023 sw a5,-32(s0) + 3001276: fe042703 lw a4,-32(s0) + 300127a: fe842783 lw a5,-24(s0) + 300127e: fef761e3 bltu a4,a5,3001260 + 3001282: 0001 nop + 3001284: 50b2 lw ra,44(sp) + 3001286: 5422 lw s0,40(sp) + 3001288: 6145 addi sp,sp,48 + 300128a: 8082 ret + +0300128c : + 300128c: 7179 addi sp,sp,-48 + 300128e: d606 sw ra,44(sp) + 3001290: d422 sw s0,40(sp) + 3001292: 1800 addi s0,sp,48 + 3001294: fca42e23 sw a0,-36(s0) + 3001298: fe042623 sw zero,-20(s0) + 300129c: a809 j 30012ae + 300129e: 3e800513 li a0,1000 + 30012a2: 3f41 jal ra,3001232 + 30012a4: fec42783 lw a5,-20(s0) + 30012a8: 0785 addi a5,a5,1 + 30012aa: fef42623 sw a5,-20(s0) + 30012ae: fec42703 lw a4,-20(s0) + 30012b2: fdc42783 lw a5,-36(s0) + 30012b6: fef764e3 bltu a4,a5,300129e + 30012ba: 0001 nop + 30012bc: 50b2 lw ra,44(sp) + 30012be: 5422 lw s0,40(sp) + 30012c0: 6145 addi sp,sp,48 + 30012c2: 8082 ret + +030012c4 : + 30012c4: 7179 addi sp,sp,-48 + 30012c6: d606 sw ra,44(sp) + 30012c8: d422 sw s0,40(sp) + 30012ca: 1800 addi s0,sp,48 + 30012cc: fca42e23 sw a0,-36(s0) + 30012d0: fe042623 sw zero,-20(s0) + 30012d4: a809 j 30012e6 + 30012d6: 3e800513 li a0,1000 + 30012da: 3f4d jal ra,300128c + 30012dc: fec42783 lw a5,-20(s0) + 30012e0: 0785 addi a5,a5,1 + 30012e2: fef42623 sw a5,-20(s0) + 30012e6: fec42703 lw a4,-20(s0) + 30012ea: fdc42783 lw a5,-36(s0) + 30012ee: fef764e3 bltu a4,a5,30012d6 + 30012f2: 0001 nop + 30012f4: 50b2 lw ra,44(sp) + 30012f6: 5422 lw s0,40(sp) + 30012f8: 6145 addi sp,sp,48 + 30012fa: 8082 ret + +030012fc : + 30012fc: 1101 addi sp,sp,-32 + 30012fe: ce06 sw ra,28(sp) + 3001300: cc22 sw s0,24(sp) + 3001302: 1000 addi s0,sp,32 + 3001304: fea42623 sw a0,-20(s0) + 3001308: feb42423 sw a1,-24(s0) + 300130c: fe842783 lw a5,-24(s0) + 3001310: 3e800713 li a4,1000 + 3001314: 02e78063 beq a5,a4,3001334 + 3001318: 000f4737 lui a4,0xf4 + 300131c: 24070713 addi a4,a4,576 # f4240 + 3001320: 00e78e63 beq a5,a4,300133c + 3001324: 4705 li a4,1 + 3001326: 00e78363 beq a5,a4,300132c + 300132a: a829 j 3001344 + 300132c: fec42503 lw a0,-20(s0) + 3001330: 3f51 jal ra,30012c4 + 3001332: a809 j 3001344 + 3001334: fec42503 lw a0,-20(s0) + 3001338: 3f91 jal ra,300128c + 300133a: a029 j 3001344 + 300133c: fec42503 lw a0,-20(s0) + 3001340: 3dcd jal ra,3001232 + 3001342: 0001 nop + 3001344: 0001 nop + 3001346: 40f2 lw ra,28(sp) + 3001348: 4462 lw s0,24(sp) + 300134a: 6105 addi sp,sp,32 + 300134c: 8082 ret + +0300134e : + 300134e: 1101 addi sp,sp,-32 + 3001350: ce22 sw s0,28(sp) + 3001352: 1000 addi s0,sp,32 + 3001354: fea42623 sw a0,-20(s0) + 3001358: 0ff0000f fence + 300135c: fec42783 lw a5,-20(s0) + 3001360: 82be mv t0,a5 + 3001362: bf029073 csrw 0xbf0,t0 + 3001366: 0001 nop + 3001368: 4472 lw s0,28(sp) + 300136a: 6105 addi sp,sp,32 + 300136c: 8082 ret + +0300136e : + 300136e: 1101 addi sp,sp,-32 + 3001370: ce06 sw ra,28(sp) + 3001372: cc22 sw s0,24(sp) + 3001374: 1000 addi s0,sp,32 + 3001376: fea42623 sw a0,-20(s0) + 300137a: 040007b7 lui a5,0x4000 + 300137e: 0fc78713 addi a4,a5,252 # 40000fc + 3001382: fec42783 lw a5,-20(s0) + 3001386: 078e slli a5,a5,0x3 + 3001388: 97ba add a5,a5,a4 + 300138a: 4394 lw a3,0(a5) + 300138c: 040007b7 lui a5,0x4000 + 3001390: 0fc78713 addi a4,a5,252 # 40000fc + 3001394: fec42783 lw a5,-20(s0) + 3001398: 078e slli a5,a5,0x3 + 300139a: 97ba add a5,a5,a4 + 300139c: 43dc lw a5,4(a5) + 300139e: 853e mv a0,a5 + 30013a0: 9682 jalr a3 + 30013a2: fec42503 lw a0,-20(s0) + 30013a6: 3765 jal ra,300134e + 30013a8: 0001 nop + 30013aa: 40f2 lw ra,28(sp) + 30013ac: 4462 lw s0,24(sp) + 30013ae: 6105 addi sp,sp,32 + 30013b0: 8082 ret + +030013b2 : + 30013b2: 1101 addi sp,sp,-32 + 30013b4: ce22 sw s0,28(sp) + 30013b6: 1000 addi s0,sp,32 + 30013b8: fe042623 sw zero,-20(s0) + 30013bc: a82d j 30013f6 + 30013be: 040007b7 lui a5,0x4000 + 30013c2: 0fc78713 addi a4,a5,252 # 40000fc + 30013c6: fec42783 lw a5,-20(s0) + 30013ca: 078e slli a5,a5,0x3 + 30013cc: 97ba add a5,a5,a4 + 30013ce: 03002737 lui a4,0x3002 + 30013d2: c5270713 addi a4,a4,-942 # 3001c52 + 30013d6: c398 sw a4,0(a5) + 30013d8: 040007b7 lui a5,0x4000 + 30013dc: 0fc78713 addi a4,a5,252 # 40000fc + 30013e0: fec42783 lw a5,-20(s0) + 30013e4: 078e slli a5,a5,0x3 + 30013e6: 97ba add a5,a5,a4 + 30013e8: 0007a223 sw zero,4(a5) + 30013ec: fec42783 lw a5,-20(s0) + 30013f0: 0785 addi a5,a5,1 + 30013f2: fef42623 sw a5,-20(s0) + 30013f6: fec42703 lw a4,-20(s0) + 30013fa: 07200793 li a5,114 + 30013fe: fce7f0e3 bgeu a5,a4,30013be + 3001402: 0001 nop + 3001404: 4472 lw s0,28(sp) + 3001406: 6105 addi sp,sp,32 + 3001408: 8082 ret + +0300140a : + 300140a: 1101 addi sp,sp,-32 + 300140c: ce06 sw ra,28(sp) + 300140e: cc22 sw s0,24(sp) + 3001410: 1000 addi s0,sp,32 + 3001412: fea42623 sw a0,-20(s0) + 3001416: feb42423 sw a1,-24(s0) + 300141a: fec42223 sw a2,-28(s0) + 300141e: fe842783 lw a5,-24(s0) + 3001422: eb89 bnez a5,3001434 + 3001424: 06300593 li a1,99 + 3001428: 030097b7 lui a5,0x3009 + 300142c: 8f078513 addi a0,a5,-1808 # 30088f0 + 3001430: 3be1 jal ra,3001208 + 3001432: a001 j 3001432 + 3001434: fec42703 lw a4,-20(s0) + 3001438: 07200793 li a5,114 + 300143c: 00e7fb63 bgeu a5,a4,3001452 + 3001440: 06400593 li a1,100 + 3001444: 030097b7 lui a5,0x3009 + 3001448: 8f078513 addi a0,a5,-1808 # 30088f0 + 300144c: 3b75 jal ra,3001208 + 300144e: 4789 li a5,2 + 3001450: a81d j 3001486 + 3001452: 040007b7 lui a5,0x4000 + 3001456: 0fc78713 addi a4,a5,252 # 40000fc + 300145a: fec42783 lw a5,-20(s0) + 300145e: 078e slli a5,a5,0x3 + 3001460: 97ba add a5,a5,a4 + 3001462: 4398 lw a4,0(a5) + 3001464: 030027b7 lui a5,0x3002 + 3001468: c5278793 addi a5,a5,-942 # 3001c52 + 300146c: 00f70463 beq a4,a5,3001474 + 3001470: 478d li a5,3 + 3001472: a811 j 3001486 + 3001474: fe442603 lw a2,-28(s0) + 3001478: fe842583 lw a1,-24(s0) + 300147c: fec42503 lw a0,-20(s0) + 3001480: 7e4000ef jal ra,3001c64 + 3001484: 4781 li a5,0 + 3001486: 853e mv a0,a5 + 3001488: 40f2 lw ra,28(sp) + 300148a: 4462 lw s0,24(sp) + 300148c: 6105 addi sp,sp,32 + 300148e: 8082 ret + +03001490 : + 3001490: 7139 addi sp,sp,-64 + 3001492: de06 sw ra,60(sp) + 3001494: dc22 sw s0,56(sp) + 3001496: 0080 addi s0,sp,64 + 3001498: fca42623 sw a0,-52(s0) + 300149c: fcc42703 lw a4,-52(s0) + 30014a0: 47e5 li a5,25 + 30014a2: 00e7f863 bgeu a5,a4,30014b2 + 30014a6: fcc42703 lw a4,-52(s0) + 30014aa: 07200793 li a5,114 + 30014ae: 00e7fb63 bgeu a5,a4,30014c4 + 30014b2: 0c300593 li a1,195 + 30014b6: 030097b7 lui a5,0x3009 + 30014ba: 8f078513 addi a0,a5,-1808 # 30088f0 + 30014be: 33a9 jal ra,3001208 + 30014c0: 4789 li a5,2 + 30014c2: a8cd j 30015b4 + 30014c4: fcc42703 lw a4,-52(s0) + 30014c8: 47fd li a5,31 + 30014ca: 02e7e063 bltu a5,a4,30014ea + 30014ce: 4705 li a4,1 + 30014d0: fcc42783 lw a5,-52(s0) + 30014d4: 00f717b3 sll a5,a4,a5 + 30014d8: fef42623 sw a5,-20(s0) + 30014dc: fec42783 lw a5,-20(s0) + 30014e0: 3047a7f3 csrrs a5,mie,a5 + 30014e4: fcf42c23 sw a5,-40(s0) + 30014e8: a0e9 j 30015b2 + 30014ea: fcc42703 lw a4,-52(s0) + 30014ee: 03f00793 li a5,63 + 30014f2: 02e7ef63 bltu a5,a4,3001530 + 30014f6: fcc42783 lw a5,-52(s0) + 30014fa: 1781 addi a5,a5,-32 + 30014fc: fef42623 sw a5,-20(s0) + 3001500: be0027f3 csrr a5,0xbe0 + 3001504: fcf42e23 sw a5,-36(s0) + 3001508: fdc42783 lw a5,-36(s0) + 300150c: fef42223 sw a5,-28(s0) + 3001510: 4705 li a4,1 + 3001512: fec42783 lw a5,-20(s0) + 3001516: 00f717b3 sll a5,a4,a5 + 300151a: fe442703 lw a4,-28(s0) + 300151e: 8fd9 or a5,a5,a4 + 3001520: fef42223 sw a5,-28(s0) + 3001524: fe442783 lw a5,-28(s0) + 3001528: 82be mv t0,a5 + 300152a: be029073 csrw 0xbe0,t0 + 300152e: a051 j 30015b2 + 3001530: fcc42703 lw a4,-52(s0) + 3001534: 05f00793 li a5,95 + 3001538: 04e7e063 bltu a5,a4,3001578 + 300153c: fcc42783 lw a5,-52(s0) + 3001540: fc078793 addi a5,a5,-64 + 3001544: fef42623 sw a5,-20(s0) + 3001548: be1027f3 csrr a5,0xbe1 + 300154c: fef42023 sw a5,-32(s0) + 3001550: fe042783 lw a5,-32(s0) + 3001554: fef42223 sw a5,-28(s0) + 3001558: 4705 li a4,1 + 300155a: fec42783 lw a5,-20(s0) + 300155e: 00f717b3 sll a5,a4,a5 + 3001562: fe442703 lw a4,-28(s0) + 3001566: 8fd9 or a5,a5,a4 + 3001568: fef42223 sw a5,-28(s0) + 300156c: fe442783 lw a5,-28(s0) + 3001570: 82be mv t0,a5 + 3001572: be129073 csrw 0xbe1,t0 + 3001576: a835 j 30015b2 + 3001578: fcc42783 lw a5,-52(s0) + 300157c: fa078793 addi a5,a5,-96 + 3001580: fef42623 sw a5,-20(s0) + 3001584: be2027f3 csrr a5,0xbe2 + 3001588: fef42423 sw a5,-24(s0) + 300158c: fe842783 lw a5,-24(s0) + 3001590: fef42223 sw a5,-28(s0) + 3001594: 4705 li a4,1 + 3001596: fec42783 lw a5,-20(s0) + 300159a: 00f717b3 sll a5,a4,a5 + 300159e: fe442703 lw a4,-28(s0) + 30015a2: 8fd9 or a5,a5,a4 + 30015a4: fef42223 sw a5,-28(s0) + 30015a8: fe442783 lw a5,-28(s0) + 30015ac: 82be mv t0,a5 + 30015ae: be229073 csrw 0xbe2,t0 + 30015b2: 4781 li a5,0 + 30015b4: 853e mv a0,a5 + 30015b6: 50f2 lw ra,60(sp) + 30015b8: 5462 lw s0,56(sp) + 30015ba: 6121 addi sp,sp,64 + 30015bc: 8082 ret + +030015be : + 30015be: 1101 addi sp,sp,-32 + 30015c0: ce22 sw s0,28(sp) + 30015c2: 1000 addi s0,sp,32 + 30015c4: fea42623 sw a0,-20(s0) + 30015c8: 0001 nop + 30015ca: 4472 lw s0,28(sp) + 30015cc: 6105 addi sp,sp,32 + 30015ce: 8082 ret + +030015d0 : + 30015d0: 1141 addi sp,sp,-16 + 30015d2: c622 sw s0,12(sp) + 30015d4: 0800 addi s0,sp,16 + 30015d6: 0001 nop + 30015d8: 4432 lw s0,12(sp) + 30015da: 0141 addi sp,sp,16 + 30015dc: 8082 ret + +030015de : + 30015de: 1101 addi sp,sp,-32 + 30015e0: ce06 sw ra,28(sp) + 30015e2: cc22 sw s0,24(sp) + 30015e4: 1000 addi s0,sp,32 + 30015e6: fea42623 sw a0,-20(s0) + 30015ea: fec42503 lw a0,-20(s0) + 30015ee: 3fc1 jal ra,30015be + 30015f0: 37c5 jal ra,30015d0 + 30015f2: 0001 nop + 30015f4: 40f2 lw ra,28(sp) + 30015f6: 4462 lw s0,24(sp) + 30015f8: 6105 addi sp,sp,32 + 30015fa: 8082 ret + +030015fc : + 30015fc: 1101 addi sp,sp,-32 + 30015fe: ce06 sw ra,28(sp) + 3001600: cc22 sw s0,24(sp) + 3001602: 1000 addi s0,sp,32 + 3001604: fea42623 sw a0,-20(s0) + 3001608: fec42783 lw a5,-20(s0) + 300160c: eb89 bnez a5,300161e + 300160e: 12d00593 li a1,301 + 3001612: 030097b7 lui a5,0x3009 + 3001616: 8f078513 addi a0,a5,-1808 # 30088f0 + 300161a: 36fd jal ra,3001208 + 300161c: a001 j 300161c + 300161e: fec42503 lw a0,-20(s0) + 3001622: 3f71 jal ra,30015be + 3001624: 3775 jal ra,30015d0 + 3001626: 0001 nop + 3001628: 40f2 lw ra,28(sp) + 300162a: 4462 lw s0,24(sp) + 300162c: 6105 addi sp,sp,32 + 300162e: 8082 ret + +03001630 : + 3001630: 711d addi sp,sp,-96 + 3001632: cea2 sw s0,92(sp) + 3001634: 1080 addi s0,sp,96 + 3001636: faa42623 sw a0,-84(s0) + 300163a: fab42423 sw a1,-88(s0) + 300163e: fac42223 sw a2,-92(s0) + 3001642: fac42783 lw a5,-84(s0) + 3001646: 17e1 addi a5,a5,-8 + 3001648: 471d li a4,7 + 300164a: 2af76363 bltu a4,a5,30018f0 + 300164e: 00279713 slli a4,a5,0x2 + 3001652: 030097b7 lui a5,0x3009 + 3001656: 91078793 addi a5,a5,-1776 # 3008910 + 300165a: 97ba add a5,a5,a4 + 300165c: 439c lw a5,0(a5) + 300165e: 8782 jr a5 + 3001660: bc8027f3 csrr a5,0xbc8 + 3001664: faf42a23 sw a5,-76(s0) + 3001668: fb442783 lw a5,-76(s0) + 300166c: faf42823 sw a5,-80(s0) + 3001670: fa842783 lw a5,-88(s0) + 3001674: 078a slli a5,a5,0x2 + 3001676: 8bf1 andi a5,a5,28 + 3001678: 473d li a4,15 + 300167a: 00f717b3 sll a5,a4,a5 + 300167e: fff7c793 not a5,a5 + 3001682: fb042703 lw a4,-80(s0) + 3001686: 8ff9 and a5,a5,a4 + 3001688: faf42823 sw a5,-80(s0) + 300168c: fa842783 lw a5,-88(s0) + 3001690: 078a slli a5,a5,0x2 + 3001692: 8bf1 andi a5,a5,28 + 3001694: fa442703 lw a4,-92(s0) + 3001698: 00f717b3 sll a5,a4,a5 + 300169c: fb042703 lw a4,-80(s0) + 30016a0: 8fd9 or a5,a5,a4 + 30016a2: faf42823 sw a5,-80(s0) + 30016a6: fb042783 lw a5,-80(s0) + 30016aa: 82be mv t0,a5 + 30016ac: bc829073 csrw 0xbc8,t0 + 30016b0: a489 j 30018f2 + 30016b2: bc9027f3 csrr a5,0xbc9 + 30016b6: faf42e23 sw a5,-68(s0) + 30016ba: fbc42783 lw a5,-68(s0) + 30016be: faf42c23 sw a5,-72(s0) + 30016c2: fa842783 lw a5,-88(s0) + 30016c6: 078a slli a5,a5,0x2 + 30016c8: 8bf1 andi a5,a5,28 + 30016ca: 473d li a4,15 + 30016cc: 00f717b3 sll a5,a4,a5 + 30016d0: fff7c793 not a5,a5 + 30016d4: fb842703 lw a4,-72(s0) + 30016d8: 8ff9 and a5,a5,a4 + 30016da: faf42c23 sw a5,-72(s0) + 30016de: fa842783 lw a5,-88(s0) + 30016e2: 078a slli a5,a5,0x2 + 30016e4: 8bf1 andi a5,a5,28 + 30016e6: fa442703 lw a4,-92(s0) + 30016ea: 00f717b3 sll a5,a4,a5 + 30016ee: fb842703 lw a4,-72(s0) + 30016f2: 8fd9 or a5,a5,a4 + 30016f4: faf42c23 sw a5,-72(s0) + 30016f8: fb842783 lw a5,-72(s0) + 30016fc: 82be mv t0,a5 + 30016fe: bc929073 csrw 0xbc9,t0 + 3001702: aac5 j 30018f2 + 3001704: bca027f3 csrr a5,0xbca + 3001708: fcf42223 sw a5,-60(s0) + 300170c: fc442783 lw a5,-60(s0) + 3001710: fcf42023 sw a5,-64(s0) + 3001714: fa842783 lw a5,-88(s0) + 3001718: 078a slli a5,a5,0x2 + 300171a: 8bf1 andi a5,a5,28 + 300171c: 473d li a4,15 + 300171e: 00f717b3 sll a5,a4,a5 + 3001722: fff7c793 not a5,a5 + 3001726: fc042703 lw a4,-64(s0) + 300172a: 8ff9 and a5,a5,a4 + 300172c: fcf42023 sw a5,-64(s0) + 3001730: fa842783 lw a5,-88(s0) + 3001734: 078a slli a5,a5,0x2 + 3001736: 8bf1 andi a5,a5,28 + 3001738: fa442703 lw a4,-92(s0) + 300173c: 00f717b3 sll a5,a4,a5 + 3001740: fc042703 lw a4,-64(s0) + 3001744: 8fd9 or a5,a5,a4 + 3001746: fcf42023 sw a5,-64(s0) + 300174a: fc042783 lw a5,-64(s0) + 300174e: 82be mv t0,a5 + 3001750: bca29073 csrw 0xbca,t0 + 3001754: aa79 j 30018f2 + 3001756: bcb027f3 csrr a5,0xbcb + 300175a: fcf42623 sw a5,-52(s0) + 300175e: fcc42783 lw a5,-52(s0) + 3001762: fcf42423 sw a5,-56(s0) + 3001766: fa842783 lw a5,-88(s0) + 300176a: 078a slli a5,a5,0x2 + 300176c: 8bf1 andi a5,a5,28 + 300176e: 473d li a4,15 + 3001770: 00f717b3 sll a5,a4,a5 + 3001774: fff7c793 not a5,a5 + 3001778: fc842703 lw a4,-56(s0) + 300177c: 8ff9 and a5,a5,a4 + 300177e: fcf42423 sw a5,-56(s0) + 3001782: fa842783 lw a5,-88(s0) + 3001786: 078a slli a5,a5,0x2 + 3001788: 8bf1 andi a5,a5,28 + 300178a: fa442703 lw a4,-92(s0) + 300178e: 00f717b3 sll a5,a4,a5 + 3001792: fc842703 lw a4,-56(s0) + 3001796: 8fd9 or a5,a5,a4 + 3001798: fcf42423 sw a5,-56(s0) + 300179c: fc842783 lw a5,-56(s0) + 30017a0: 82be mv t0,a5 + 30017a2: bcb29073 csrw 0xbcb,t0 + 30017a6: a2b1 j 30018f2 + 30017a8: bcc027f3 csrr a5,0xbcc + 30017ac: fcf42a23 sw a5,-44(s0) + 30017b0: fd442783 lw a5,-44(s0) + 30017b4: fcf42823 sw a5,-48(s0) + 30017b8: fa842783 lw a5,-88(s0) + 30017bc: 078a slli a5,a5,0x2 + 30017be: 8bf1 andi a5,a5,28 + 30017c0: 473d li a4,15 + 30017c2: 00f717b3 sll a5,a4,a5 + 30017c6: fff7c793 not a5,a5 + 30017ca: fd042703 lw a4,-48(s0) + 30017ce: 8ff9 and a5,a5,a4 + 30017d0: fcf42823 sw a5,-48(s0) + 30017d4: fa842783 lw a5,-88(s0) + 30017d8: 078a slli a5,a5,0x2 + 30017da: 8bf1 andi a5,a5,28 + 30017dc: fa442703 lw a4,-92(s0) + 30017e0: 00f717b3 sll a5,a4,a5 + 30017e4: fd042703 lw a4,-48(s0) + 30017e8: 8fd9 or a5,a5,a4 + 30017ea: fcf42823 sw a5,-48(s0) + 30017ee: fd042783 lw a5,-48(s0) + 30017f2: 82be mv t0,a5 + 30017f4: bcc29073 csrw 0xbcc,t0 + 30017f8: a8ed j 30018f2 + 30017fa: bcd027f3 csrr a5,0xbcd + 30017fe: fcf42e23 sw a5,-36(s0) + 3001802: fdc42783 lw a5,-36(s0) + 3001806: fcf42c23 sw a5,-40(s0) + 300180a: fa842783 lw a5,-88(s0) + 300180e: 078a slli a5,a5,0x2 + 3001810: 8bf1 andi a5,a5,28 + 3001812: 473d li a4,15 + 3001814: 00f717b3 sll a5,a4,a5 + 3001818: fff7c793 not a5,a5 + 300181c: fd842703 lw a4,-40(s0) + 3001820: 8ff9 and a5,a5,a4 + 3001822: fcf42c23 sw a5,-40(s0) + 3001826: fa842783 lw a5,-88(s0) + 300182a: 078a slli a5,a5,0x2 + 300182c: 8bf1 andi a5,a5,28 + 300182e: fa442703 lw a4,-92(s0) + 3001832: 00f717b3 sll a5,a4,a5 + 3001836: fd842703 lw a4,-40(s0) + 300183a: 8fd9 or a5,a5,a4 + 300183c: fcf42c23 sw a5,-40(s0) + 3001840: fd842783 lw a5,-40(s0) + 3001844: 82be mv t0,a5 + 3001846: bcd29073 csrw 0xbcd,t0 + 300184a: a065 j 30018f2 + 300184c: bce027f3 csrr a5,0xbce + 3001850: fef42223 sw a5,-28(s0) + 3001854: fe442783 lw a5,-28(s0) + 3001858: fef42023 sw a5,-32(s0) + 300185c: fa842783 lw a5,-88(s0) + 3001860: 078a slli a5,a5,0x2 + 3001862: 8bf1 andi a5,a5,28 + 3001864: 473d li a4,15 + 3001866: 00f717b3 sll a5,a4,a5 + 300186a: fff7c793 not a5,a5 + 300186e: fe042703 lw a4,-32(s0) + 3001872: 8ff9 and a5,a5,a4 + 3001874: fef42023 sw a5,-32(s0) + 3001878: fa842783 lw a5,-88(s0) + 300187c: 078a slli a5,a5,0x2 + 300187e: 8bf1 andi a5,a5,28 + 3001880: fa442703 lw a4,-92(s0) + 3001884: 00f717b3 sll a5,a4,a5 + 3001888: fe042703 lw a4,-32(s0) + 300188c: 8fd9 or a5,a5,a4 + 300188e: fef42023 sw a5,-32(s0) + 3001892: fe042783 lw a5,-32(s0) + 3001896: 82be mv t0,a5 + 3001898: bce29073 csrw 0xbce,t0 + 300189c: a899 j 30018f2 + 300189e: bcf027f3 csrr a5,0xbcf + 30018a2: fef42623 sw a5,-20(s0) + 30018a6: fec42783 lw a5,-20(s0) + 30018aa: fef42423 sw a5,-24(s0) + 30018ae: fa842783 lw a5,-88(s0) + 30018b2: 078a slli a5,a5,0x2 + 30018b4: 8bf1 andi a5,a5,28 + 30018b6: 473d li a4,15 + 30018b8: 00f717b3 sll a5,a4,a5 + 30018bc: fff7c793 not a5,a5 + 30018c0: fe842703 lw a4,-24(s0) + 30018c4: 8ff9 and a5,a5,a4 + 30018c6: fef42423 sw a5,-24(s0) + 30018ca: fa842783 lw a5,-88(s0) + 30018ce: 078a slli a5,a5,0x2 + 30018d0: 8bf1 andi a5,a5,28 + 30018d2: fa442703 lw a4,-92(s0) + 30018d6: 00f717b3 sll a5,a4,a5 + 30018da: fe842703 lw a4,-24(s0) + 30018de: 8fd9 or a5,a5,a4 + 30018e0: fef42423 sw a5,-24(s0) + 30018e4: fe842783 lw a5,-24(s0) + 30018e8: 82be mv t0,a5 + 30018ea: bcf29073 csrw 0xbcf,t0 + 30018ee: a011 j 30018f2 + 30018f0: 0001 nop + 30018f2: 0001 nop + 30018f4: 4476 lw s0,92(sp) + 30018f6: 6125 addi sp,sp,96 + 30018f8: 8082 ret + +030018fa : + 30018fa: 7159 addi sp,sp,-112 + 30018fc: d686 sw ra,108(sp) + 30018fe: d4a2 sw s0,104(sp) + 3001900: 1880 addi s0,sp,112 + 3001902: f8a42e23 sw a0,-100(s0) + 3001906: f8b42c23 sw a1,-104(s0) + 300190a: f9c42783 lw a5,-100(s0) + 300190e: 838d srli a5,a5,0x3 + 3001910: fef42623 sw a5,-20(s0) + 3001914: fec42703 lw a4,-20(s0) + 3001918: 479d li a5,7 + 300191a: 2ae7e563 bltu a5,a4,3001bc4 + 300191e: fec42783 lw a5,-20(s0) + 3001922: 00279713 slli a4,a5,0x2 + 3001926: 030097b7 lui a5,0x3009 + 300192a: 93078793 addi a5,a5,-1744 # 3008930 + 300192e: 97ba add a5,a5,a4 + 3001930: 439c lw a5,0(a5) + 3001932: 8782 jr a5 + 3001934: bc0027f3 csrr a5,0xbc0 + 3001938: faf42823 sw a5,-80(s0) + 300193c: fb042783 lw a5,-80(s0) + 3001940: faf42623 sw a5,-84(s0) + 3001944: f9c42783 lw a5,-100(s0) + 3001948: 078a slli a5,a5,0x2 + 300194a: 8bf1 andi a5,a5,28 + 300194c: 473d li a4,15 + 300194e: 00f717b3 sll a5,a4,a5 + 3001952: fff7c793 not a5,a5 + 3001956: fac42703 lw a4,-84(s0) + 300195a: 8ff9 and a5,a5,a4 + 300195c: faf42623 sw a5,-84(s0) + 3001960: f9c42783 lw a5,-100(s0) + 3001964: 078a slli a5,a5,0x2 + 3001966: 8bf1 andi a5,a5,28 + 3001968: f9842703 lw a4,-104(s0) + 300196c: 00f717b3 sll a5,a4,a5 + 3001970: fac42703 lw a4,-84(s0) + 3001974: 8fd9 or a5,a5,a4 + 3001976: faf42623 sw a5,-84(s0) + 300197a: fac42783 lw a5,-84(s0) + 300197e: 82be mv t0,a5 + 3001980: bc029073 csrw 0xbc0,t0 + 3001984: ac81 j 3001bd4 + 3001986: bc1027f3 csrr a5,0xbc1 + 300198a: faf42c23 sw a5,-72(s0) + 300198e: fb842783 lw a5,-72(s0) + 3001992: faf42a23 sw a5,-76(s0) + 3001996: f9c42783 lw a5,-100(s0) + 300199a: 078a slli a5,a5,0x2 + 300199c: 8bf1 andi a5,a5,28 + 300199e: 473d li a4,15 + 30019a0: 00f717b3 sll a5,a4,a5 + 30019a4: fff7c793 not a5,a5 + 30019a8: fb442703 lw a4,-76(s0) + 30019ac: 8ff9 and a5,a5,a4 + 30019ae: faf42a23 sw a5,-76(s0) + 30019b2: f9c42783 lw a5,-100(s0) + 30019b6: 078a slli a5,a5,0x2 + 30019b8: 8bf1 andi a5,a5,28 + 30019ba: f9842703 lw a4,-104(s0) + 30019be: 00f717b3 sll a5,a4,a5 + 30019c2: fb442703 lw a4,-76(s0) + 30019c6: 8fd9 or a5,a5,a4 + 30019c8: faf42a23 sw a5,-76(s0) + 30019cc: fb442783 lw a5,-76(s0) + 30019d0: 82be mv t0,a5 + 30019d2: bc129073 csrw 0xbc1,t0 + 30019d6: aafd j 3001bd4 + 30019d8: bc2027f3 csrr a5,0xbc2 + 30019dc: fcf42023 sw a5,-64(s0) + 30019e0: fc042783 lw a5,-64(s0) + 30019e4: faf42e23 sw a5,-68(s0) + 30019e8: f9c42783 lw a5,-100(s0) + 30019ec: 078a slli a5,a5,0x2 + 30019ee: 8bf1 andi a5,a5,28 + 30019f0: 473d li a4,15 + 30019f2: 00f717b3 sll a5,a4,a5 + 30019f6: fff7c793 not a5,a5 + 30019fa: fbc42703 lw a4,-68(s0) + 30019fe: 8ff9 and a5,a5,a4 + 3001a00: faf42e23 sw a5,-68(s0) + 3001a04: f9c42783 lw a5,-100(s0) + 3001a08: 078a slli a5,a5,0x2 + 3001a0a: 8bf1 andi a5,a5,28 + 3001a0c: f9842703 lw a4,-104(s0) + 3001a10: 00f717b3 sll a5,a4,a5 + 3001a14: fbc42703 lw a4,-68(s0) + 3001a18: 8fd9 or a5,a5,a4 + 3001a1a: faf42e23 sw a5,-68(s0) + 3001a1e: fbc42783 lw a5,-68(s0) + 3001a22: 82be mv t0,a5 + 3001a24: bc229073 csrw 0xbc2,t0 + 3001a28: a275 j 3001bd4 + 3001a2a: bc3027f3 csrr a5,0xbc3 + 3001a2e: fcf42423 sw a5,-56(s0) + 3001a32: fc842783 lw a5,-56(s0) + 3001a36: fcf42223 sw a5,-60(s0) + 3001a3a: f9c42783 lw a5,-100(s0) + 3001a3e: 078a slli a5,a5,0x2 + 3001a40: 8bf1 andi a5,a5,28 + 3001a42: 473d li a4,15 + 3001a44: 00f717b3 sll a5,a4,a5 + 3001a48: fff7c793 not a5,a5 + 3001a4c: fc442703 lw a4,-60(s0) + 3001a50: 8ff9 and a5,a5,a4 + 3001a52: fcf42223 sw a5,-60(s0) + 3001a56: f9c42783 lw a5,-100(s0) + 3001a5a: 078a slli a5,a5,0x2 + 3001a5c: 8bf1 andi a5,a5,28 + 3001a5e: f9842703 lw a4,-104(s0) + 3001a62: 00f717b3 sll a5,a4,a5 + 3001a66: fc442703 lw a4,-60(s0) + 3001a6a: 8fd9 or a5,a5,a4 + 3001a6c: fcf42223 sw a5,-60(s0) + 3001a70: fc442783 lw a5,-60(s0) + 3001a74: 82be mv t0,a5 + 3001a76: bc329073 csrw 0xbc3,t0 + 3001a7a: aaa9 j 3001bd4 + 3001a7c: bc4027f3 csrr a5,0xbc4 + 3001a80: fcf42823 sw a5,-48(s0) + 3001a84: fd042783 lw a5,-48(s0) + 3001a88: fcf42623 sw a5,-52(s0) + 3001a8c: f9c42783 lw a5,-100(s0) + 3001a90: 078a slli a5,a5,0x2 + 3001a92: 8bf1 andi a5,a5,28 + 3001a94: 473d li a4,15 + 3001a96: 00f717b3 sll a5,a4,a5 + 3001a9a: fff7c793 not a5,a5 + 3001a9e: fcc42703 lw a4,-52(s0) + 3001aa2: 8ff9 and a5,a5,a4 + 3001aa4: fcf42623 sw a5,-52(s0) + 3001aa8: f9c42783 lw a5,-100(s0) + 3001aac: 078a slli a5,a5,0x2 + 3001aae: 8bf1 andi a5,a5,28 + 3001ab0: f9842703 lw a4,-104(s0) + 3001ab4: 00f717b3 sll a5,a4,a5 + 3001ab8: fcc42703 lw a4,-52(s0) + 3001abc: 8fd9 or a5,a5,a4 + 3001abe: fcf42623 sw a5,-52(s0) + 3001ac2: fcc42783 lw a5,-52(s0) + 3001ac6: 82be mv t0,a5 + 3001ac8: bc429073 csrw 0xbc4,t0 + 3001acc: a221 j 3001bd4 + 3001ace: bc5027f3 csrr a5,0xbc5 + 3001ad2: fcf42c23 sw a5,-40(s0) + 3001ad6: fd842783 lw a5,-40(s0) + 3001ada: fcf42a23 sw a5,-44(s0) + 3001ade: f9c42783 lw a5,-100(s0) + 3001ae2: 078a slli a5,a5,0x2 + 3001ae4: 8bf1 andi a5,a5,28 + 3001ae6: 473d li a4,15 + 3001ae8: 00f717b3 sll a5,a4,a5 + 3001aec: fff7c793 not a5,a5 + 3001af0: fd442703 lw a4,-44(s0) + 3001af4: 8ff9 and a5,a5,a4 + 3001af6: fcf42a23 sw a5,-44(s0) + 3001afa: f9c42783 lw a5,-100(s0) + 3001afe: 078a slli a5,a5,0x2 + 3001b00: 8bf1 andi a5,a5,28 + 3001b02: f9842703 lw a4,-104(s0) + 3001b06: 00f717b3 sll a5,a4,a5 + 3001b0a: fd442703 lw a4,-44(s0) + 3001b0e: 8fd9 or a5,a5,a4 + 3001b10: fcf42a23 sw a5,-44(s0) + 3001b14: fd442783 lw a5,-44(s0) + 3001b18: 82be mv t0,a5 + 3001b1a: bc529073 csrw 0xbc5,t0 + 3001b1e: a85d j 3001bd4 + 3001b20: bc6027f3 csrr a5,0xbc6 + 3001b24: fef42023 sw a5,-32(s0) + 3001b28: fe042783 lw a5,-32(s0) + 3001b2c: fcf42e23 sw a5,-36(s0) + 3001b30: f9c42783 lw a5,-100(s0) + 3001b34: 078a slli a5,a5,0x2 + 3001b36: 8bf1 andi a5,a5,28 + 3001b38: 473d li a4,15 + 3001b3a: 00f717b3 sll a5,a4,a5 + 3001b3e: fff7c793 not a5,a5 + 3001b42: fdc42703 lw a4,-36(s0) + 3001b46: 8ff9 and a5,a5,a4 + 3001b48: fcf42e23 sw a5,-36(s0) + 3001b4c: f9c42783 lw a5,-100(s0) + 3001b50: 078a slli a5,a5,0x2 + 3001b52: 8bf1 andi a5,a5,28 + 3001b54: f9842703 lw a4,-104(s0) + 3001b58: 00f717b3 sll a5,a4,a5 + 3001b5c: fdc42703 lw a4,-36(s0) + 3001b60: 8fd9 or a5,a5,a4 + 3001b62: fcf42e23 sw a5,-36(s0) + 3001b66: fdc42783 lw a5,-36(s0) + 3001b6a: 82be mv t0,a5 + 3001b6c: bc629073 csrw 0xbc6,t0 + 3001b70: a095 j 3001bd4 + 3001b72: bc7027f3 csrr a5,0xbc7 + 3001b76: fef42423 sw a5,-24(s0) + 3001b7a: fe842783 lw a5,-24(s0) + 3001b7e: fef42223 sw a5,-28(s0) + 3001b82: f9c42783 lw a5,-100(s0) + 3001b86: 078a slli a5,a5,0x2 + 3001b88: 8bf1 andi a5,a5,28 + 3001b8a: 473d li a4,15 + 3001b8c: 00f717b3 sll a5,a4,a5 + 3001b90: fff7c793 not a5,a5 + 3001b94: fe442703 lw a4,-28(s0) + 3001b98: 8ff9 and a5,a5,a4 + 3001b9a: fef42223 sw a5,-28(s0) + 3001b9e: f9c42783 lw a5,-100(s0) + 3001ba2: 078a slli a5,a5,0x2 + 3001ba4: 8bf1 andi a5,a5,28 + 3001ba6: f9842703 lw a4,-104(s0) + 3001baa: 00f717b3 sll a5,a4,a5 + 3001bae: fe442703 lw a4,-28(s0) + 3001bb2: 8fd9 or a5,a5,a4 + 3001bb4: fef42223 sw a5,-28(s0) + 3001bb8: fe442783 lw a5,-28(s0) + 3001bbc: 82be mv t0,a5 + 3001bbe: bc729073 csrw 0xbc7,t0 + 3001bc2: a809 j 3001bd4 + 3001bc4: f9842603 lw a2,-104(s0) + 3001bc8: f9c42583 lw a1,-100(s0) + 3001bcc: fec42503 lw a0,-20(s0) + 3001bd0: 3485 jal ra,3001630 + 3001bd2: 0001 nop + 3001bd4: 0001 nop + 3001bd6: 50b6 lw ra,108(sp) + 3001bd8: 5426 lw s0,104(sp) + 3001bda: 6165 addi sp,sp,112 + 3001bdc: 8082 ret + +03001bde : + 3001bde: 1101 addi sp,sp,-32 + 3001be0: ce06 sw ra,28(sp) + 3001be2: cc22 sw s0,24(sp) + 3001be4: 1000 addi s0,sp,32 + 3001be6: fea42623 sw a0,-20(s0) + 3001bea: feb42423 sw a1,-24(s0) + 3001bee: fec42703 lw a4,-20(s0) + 3001bf2: 47e5 li a5,25 + 3001bf4: 00e7f863 bgeu a5,a4,3001c04 + 3001bf8: fec42703 lw a4,-20(s0) + 3001bfc: 07200793 li a5,114 + 3001c00: 00e7fb63 bgeu a5,a4,3001c16 + 3001c04: 18c00593 li a1,396 + 3001c08: 030097b7 lui a5,0x3009 + 3001c0c: 8f078513 addi a0,a5,-1808 # 30088f0 + 3001c10: 21bd jal ra,300207e + 3001c12: 4789 li a5,2 + 3001c14: a815 j 3001c48 + 3001c16: fe842783 lw a5,-24(s0) + 3001c1a: c791 beqz a5,3001c26 + 3001c1c: fe842703 lw a4,-24(s0) + 3001c20: 47bd li a5,15 + 3001c22: 00e7fb63 bgeu a5,a4,3001c38 + 3001c26: 18d00593 li a1,397 + 3001c2a: 030097b7 lui a5,0x3009 + 3001c2e: 8f078513 addi a0,a5,-1808 # 30088f0 + 3001c32: 21b1 jal ra,300207e + 3001c34: 4795 li a5,5 + 3001c36: a809 j 3001c48 + 3001c38: fec42783 lw a5,-20(s0) + 3001c3c: 1799 addi a5,a5,-26 + 3001c3e: fe842583 lw a1,-24(s0) + 3001c42: 853e mv a0,a5 + 3001c44: 395d jal ra,30018fa + 3001c46: 4781 li a5,0 + 3001c48: 853e mv a0,a5 + 3001c4a: 40f2 lw ra,28(sp) + 3001c4c: 4462 lw s0,24(sp) + 3001c4e: 6105 addi sp,sp,32 + 3001c50: 8082 ret + +03001c52 : + 3001c52: 1101 addi sp,sp,-32 + 3001c54: ce22 sw s0,28(sp) + 3001c56: 1000 addi s0,sp,32 + 3001c58: fea42623 sw a0,-20(s0) + 3001c5c: 0001 nop + 3001c5e: 4472 lw s0,28(sp) + 3001c60: 6105 addi sp,sp,32 + 3001c62: 8082 ret + +03001c64 : + 3001c64: 1101 addi sp,sp,-32 + 3001c66: ce22 sw s0,28(sp) + 3001c68: 1000 addi s0,sp,32 + 3001c6a: fea42623 sw a0,-20(s0) + 3001c6e: feb42423 sw a1,-24(s0) + 3001c72: fec42223 sw a2,-28(s0) + 3001c76: 040007b7 lui a5,0x4000 + 3001c7a: 0fc78713 addi a4,a5,252 # 40000fc + 3001c7e: fec42783 lw a5,-20(s0) + 3001c82: 078e slli a5,a5,0x3 + 3001c84: 97ba add a5,a5,a4 + 3001c86: fe442703 lw a4,-28(s0) + 3001c8a: c3d8 sw a4,4(a5) + 3001c8c: 040007b7 lui a5,0x4000 + 3001c90: 0fc78713 addi a4,a5,252 # 40000fc + 3001c94: fec42783 lw a5,-20(s0) + 3001c98: 078e slli a5,a5,0x3 + 3001c9a: 97ba add a5,a5,a4 + 3001c9c: fe842703 lw a4,-24(s0) + 3001ca0: c398 sw a4,0(a5) + 3001ca2: 0001 nop + 3001ca4: 4472 lw s0,28(sp) + 3001ca6: 6105 addi sp,sp,32 + 3001ca8: 8082 ret + +03001caa : + 3001caa: 1141 addi sp,sp,-16 + 3001cac: c622 sw s0,12(sp) + 3001cae: 0800 addi s0,sp,16 + 3001cb0: 101007b7 lui a5,0x10100 + 3001cb4: 43f8 lw a4,68(a5) + 3001cb6: 67c1 lui a5,0x10 + 3001cb8: 17f9 addi a5,a5,-2 # fffe + 3001cba: 00f776b3 and a3,a4,a5 + 3001cbe: 101007b7 lui a5,0x10100 + 3001cc2: ea510737 lui a4,0xea510 + 3001cc6: 9736 add a4,a4,a3 + 3001cc8: c3f8 sw a4,68(a5) + 3001cca: 0001 nop + 3001ccc: 4432 lw s0,12(sp) + 3001cce: 0141 addi sp,sp,16 + 3001cd0: 8082 ret + +03001cd2 : + 3001cd2: 1141 addi sp,sp,-16 + 3001cd4: c622 sw s0,12(sp) + 3001cd6: 0800 addi s0,sp,16 + 3001cd8: 101007b7 lui a5,0x10100 + 3001cdc: 43f8 lw a4,68(a5) + 3001cde: 67c1 lui a5,0x10 + 3001ce0: 17fd addi a5,a5,-1 # ffff + 3001ce2: 8ff9 and a5,a5,a4 + 3001ce4: 0017e693 ori a3,a5,1 + 3001ce8: 101007b7 lui a5,0x10100 + 3001cec: ea510737 lui a4,0xea510 + 3001cf0: 9736 add a4,a4,a3 + 3001cf2: c3f8 sw a4,68(a5) + 3001cf4: 0001 nop + 3001cf6: 4432 lw s0,12(sp) + 3001cf8: 0141 addi sp,sp,16 + 3001cfa: 8082 ret + +03001cfc : + 3001cfc: 1101 addi sp,sp,-32 + 3001cfe: ce22 sw s0,28(sp) + 3001d00: 1000 addi s0,sp,32 + 3001d02: fea42623 sw a0,-20(s0) + 3001d06: fec42783 lw a5,-20(s0) + 3001d0a: c791 beqz a5,3001d16 + 3001d0c: fec42703 lw a4,-20(s0) + 3001d10: 4785 li a5,1 + 3001d12: 00f71463 bne a4,a5,3001d1a + 3001d16: 4785 li a5,1 + 3001d18: a011 j 3001d1c + 3001d1a: 4781 li a5,0 + 3001d1c: 8b85 andi a5,a5,1 + 3001d1e: 9f81 uxtb a5 + 3001d20: 853e mv a0,a5 + 3001d22: 4472 lw s0,28(sp) + 3001d24: 6105 addi sp,sp,32 + 3001d26: 8082 ret + +03001d28 : + 3001d28: 1101 addi sp,sp,-32 + 3001d2a: ce22 sw s0,28(sp) + 3001d2c: 1000 addi s0,sp,32 + 3001d2e: fea42623 sw a0,-20(s0) + 3001d32: fec42783 lw a5,-20(s0) + 3001d36: 0087b793 sltiu a5,a5,8 + 3001d3a: 9f81 uxtb a5 + 3001d3c: 853e mv a0,a5 + 3001d3e: 4472 lw s0,28(sp) + 3001d40: 6105 addi sp,sp,32 + 3001d42: 8082 ret + +03001d44 : + 3001d44: 1101 addi sp,sp,-32 + 3001d46: ce22 sw s0,28(sp) + 3001d48: 1000 addi s0,sp,32 + 3001d4a: fea42623 sw a0,-20(s0) + 3001d4e: fec42783 lw a5,-20(s0) + 3001d52: 0087b793 sltiu a5,a5,8 + 3001d56: 9f81 uxtb a5 + 3001d58: 853e mv a0,a5 + 3001d5a: 4472 lw s0,28(sp) + 3001d5c: 6105 addi sp,sp,32 + 3001d5e: 8082 ret + +03001d60 : + 3001d60: 1101 addi sp,sp,-32 + 3001d62: ce22 sw s0,28(sp) + 3001d64: 1000 addi s0,sp,32 + 3001d66: fea42623 sw a0,-20(s0) + 3001d6a: fec42783 lw a5,-20(s0) + 3001d6e: 0087b793 sltiu a5,a5,8 + 3001d72: 9f81 uxtb a5 + 3001d74: 853e mv a0,a5 + 3001d76: 4472 lw s0,28(sp) + 3001d78: 6105 addi sp,sp,32 + 3001d7a: 8082 ret + +03001d7c : + 3001d7c: 1101 addi sp,sp,-32 + 3001d7e: ce22 sw s0,28(sp) + 3001d80: 1000 addi s0,sp,32 + 3001d82: fea42623 sw a0,-20(s0) + 3001d86: fec42783 lw a5,-20(s0) + 3001d8a: 0807b793 sltiu a5,a5,128 + 3001d8e: 9f81 uxtb a5 + 3001d90: 853e mv a0,a5 + 3001d92: 4472 lw s0,28(sp) + 3001d94: 6105 addi sp,sp,32 + 3001d96: 8082 ret + +03001d98 : + 3001d98: 1101 addi sp,sp,-32 + 3001d9a: ce22 sw s0,28(sp) + 3001d9c: 1000 addi s0,sp,32 + 3001d9e: fea42623 sw a0,-20(s0) + 3001da2: fec42783 lw a5,-20(s0) + 3001da6: cb99 beqz a5,3001dbc + 3001da8: fec42703 lw a4,-20(s0) + 3001dac: 4785 li a5,1 + 3001dae: 00f70763 beq a4,a5,3001dbc + 3001db2: fec42703 lw a4,-20(s0) + 3001db6: 4789 li a5,2 + 3001db8: 00f71463 bne a4,a5,3001dc0 + 3001dbc: 4785 li a5,1 + 3001dbe: a011 j 3001dc2 + 3001dc0: 4781 li a5,0 + 3001dc2: 8b85 andi a5,a5,1 + 3001dc4: 9f81 uxtb a5 + 3001dc6: 853e mv a0,a5 + 3001dc8: 4472 lw s0,28(sp) + 3001dca: 6105 addi sp,sp,32 + 3001dcc: 8082 ret + +03001dce : + 3001dce: 1101 addi sp,sp,-32 + 3001dd0: ce22 sw s0,28(sp) + 3001dd2: 1000 addi s0,sp,32 + 3001dd4: fea42623 sw a0,-20(s0) + 3001dd8: fec42783 lw a5,-20(s0) + 3001ddc: c791 beqz a5,3001de8 + 3001dde: fec42703 lw a4,-20(s0) + 3001de2: 4785 li a5,1 + 3001de4: 00f71463 bne a4,a5,3001dec + 3001de8: 4785 li a5,1 + 3001dea: a011 j 3001dee + 3001dec: 4781 li a5,0 + 3001dee: 8b85 andi a5,a5,1 + 3001df0: 9f81 uxtb a5 + 3001df2: 853e mv a0,a5 + 3001df4: 4472 lw s0,28(sp) + 3001df6: 6105 addi sp,sp,32 + 3001df8: 8082 ret + +03001dfa : + 3001dfa: 1101 addi sp,sp,-32 + 3001dfc: ce22 sw s0,28(sp) + 3001dfe: 1000 addi s0,sp,32 + 3001e00: fea42623 sw a0,-20(s0) + 3001e04: fec42783 lw a5,-20(s0) + 3001e08: 0407b793 sltiu a5,a5,64 + 3001e0c: 9f81 uxtb a5 + 3001e0e: 853e mv a0,a5 + 3001e10: 4472 lw s0,28(sp) + 3001e12: 6105 addi sp,sp,32 + 3001e14: 8082 ret + +03001e16 : + 3001e16: 7179 addi sp,sp,-48 + 3001e18: d622 sw s0,44(sp) + 3001e1a: 1800 addi s0,sp,48 + 3001e1c: fca42e23 sw a0,-36(s0) + 3001e20: fcb42c23 sw a1,-40(s0) + 3001e24: fdc42783 lw a5,-36(s0) + 3001e28: fef42623 sw a5,-20(s0) + 3001e2c: fd842783 lw a5,-40(s0) + 3001e30: cb89 beqz a5,3001e42 + 3001e32: fec42703 lw a4,-20(s0) + 3001e36: fd842783 lw a5,-40(s0) + 3001e3a: 02f757b3 divu a5,a4,a5 + 3001e3e: fef42623 sw a5,-20(s0) + 3001e42: fec42703 lw a4,-20(s0) + 3001e46: 003d17b7 lui a5,0x3d1 + 3001e4a: 8ff78793 addi a5,a5,-1793 # 3d08ff + 3001e4e: 00e7fc63 bgeu a5,a4,3001e66 + 3001e52: fec42703 lw a4,-20(s0) + 3001e56: 007277b7 lui a5,0x727 + 3001e5a: 0e078793 addi a5,a5,224 # 7270e0 + 3001e5e: 00e7e463 bltu a5,a4,3001e66 + 3001e62: 4785 li a5,1 + 3001e64: a011 j 3001e68 + 3001e66: 4781 li a5,0 + 3001e68: 8b85 andi a5,a5,1 + 3001e6a: 9f81 uxtb a5 + 3001e6c: 853e mv a0,a5 + 3001e6e: 5432 lw s0,44(sp) + 3001e70: 6145 addi sp,sp,48 + 3001e72: 8082 ret + +03001e74 : + 3001e74: 7179 addi sp,sp,-48 + 3001e76: d622 sw s0,44(sp) + 3001e78: 1800 addi s0,sp,48 + 3001e7a: fca42e23 sw a0,-36(s0) + 3001e7e: fcb42c23 sw a1,-40(s0) + 3001e82: fdc42703 lw a4,-36(s0) + 3001e86: 01c9c7b7 lui a5,0x1c9c + 3001e8a: 38078793 addi a5,a5,896 # 1c9c380 + 3001e8e: 00e7f463 bgeu a5,a4,3001e96 + 3001e92: 4781 li a5,0 + 3001e94: a08d j 3001ef6 + 3001e96: fd842703 lw a4,-40(s0) + 3001e9a: 07f00793 li a5,127 + 3001e9e: 00e7f463 bgeu a5,a4,3001ea6 + 3001ea2: 4781 li a5,0 + 3001ea4: a889 j 3001ef6 + 3001ea6: fd842703 lw a4,-40(s0) + 3001eaa: 4799 li a5,6 + 3001eac: 00e7f963 bgeu a5,a4,3001ebe + 3001eb0: fdc42703 lw a4,-36(s0) + 3001eb4: fd842783 lw a5,-40(s0) + 3001eb8: 02f707b3 mul a5,a4,a5 + 3001ebc: a031 j 3001ec8 + 3001ebe: fdc42703 lw a4,-36(s0) + 3001ec2: 4799 li a5,6 + 3001ec4: 02f707b3 mul a5,a4,a5 + 3001ec8: fef42623 sw a5,-20(s0) + 3001ecc: fec42703 lw a4,-20(s0) + 3001ed0: 05f5e7b7 lui a5,0x5f5e + 3001ed4: 0ff78793 addi a5,a5,255 # 5f5e0ff + 3001ed8: 00e7fc63 bgeu a5,a4,3001ef0 + 3001edc: fec42703 lw a4,-20(s0) + 3001ee0: 11e1a7b7 lui a5,0x11e1a + 3001ee4: 30078793 addi a5,a5,768 # 11e1a300 + 3001ee8: 00e7e463 bltu a5,a4,3001ef0 + 3001eec: 4785 li a5,1 + 3001eee: a011 j 3001ef2 + 3001ef0: 4781 li a5,0 + 3001ef2: 8b85 andi a5,a5,1 + 3001ef4: 9f81 uxtb a5 + 3001ef6: 853e mv a0,a5 + 3001ef8: 5432 lw s0,44(sp) + 3001efa: 6145 addi sp,sp,48 + 3001efc: 8082 ret + +03001efe : + 3001efe: 7179 addi sp,sp,-48 + 3001f00: d622 sw s0,44(sp) + 3001f02: 1800 addi s0,sp,48 + 3001f04: fca42e23 sw a0,-36(s0) + 3001f08: fcb42c23 sw a1,-40(s0) + 3001f0c: fdc42783 lw a5,-36(s0) + 3001f10: fef42623 sw a5,-20(s0) + 3001f14: fd842783 lw a5,-40(s0) + 3001f18: cb91 beqz a5,3001f2c + 3001f1a: fd842783 lw a5,-40(s0) + 3001f1e: 0785 addi a5,a5,1 + 3001f20: fec42703 lw a4,-20(s0) + 3001f24: 02f757b3 divu a5,a4,a5 + 3001f28: fef42623 sw a5,-20(s0) + 3001f2c: fec42703 lw a4,-20(s0) + 3001f30: 08f0d7b7 lui a5,0x8f0d + 3001f34: 18178793 addi a5,a5,385 # 8f0d181 + 3001f38: 00f737b3 sltu a5,a4,a5 + 3001f3c: 9f81 uxtb a5 + 3001f3e: 853e mv a0,a5 + 3001f40: 5432 lw s0,44(sp) + 3001f42: 6145 addi sp,sp,48 + 3001f44: 8082 ret + +03001f46 : + 3001f46: 7179 addi sp,sp,-48 + 3001f48: d622 sw s0,44(sp) + 3001f4a: 1800 addi s0,sp,48 + 3001f4c: fca42e23 sw a0,-36(s0) + 3001f50: fcb42c23 sw a1,-40(s0) + 3001f54: fdc42783 lw a5,-36(s0) + 3001f58: fef42623 sw a5,-20(s0) + 3001f5c: fd842783 lw a5,-40(s0) + 3001f60: cb91 beqz a5,3001f74 + 3001f62: fd842783 lw a5,-40(s0) + 3001f66: 0785 addi a5,a5,1 + 3001f68: fec42703 lw a4,-20(s0) + 3001f6c: 02f757b3 divu a5,a4,a5 + 3001f70: fef42623 sw a5,-20(s0) + 3001f74: fec42703 lw a4,-20(s0) + 3001f78: 05f5e7b7 lui a5,0x5f5e + 3001f7c: 10178793 addi a5,a5,257 # 5f5e101 + 3001f80: 00f737b3 sltu a5,a4,a5 + 3001f84: 9f81 uxtb a5 + 3001f86: 853e mv a0,a5 + 3001f88: 5432 lw s0,44(sp) + 3001f8a: 6145 addi sp,sp,48 + 3001f8c: 8082 ret + +03001f8e : + 3001f8e: 1101 addi sp,sp,-32 + 3001f90: ce22 sw s0,28(sp) + 3001f92: 1000 addi s0,sp,32 + 3001f94: fea42623 sw a0,-20(s0) + 3001f98: fec42783 lw a5,-20(s0) + 3001f9c: c385 beqz a5,3001fbc + 3001f9e: fec42703 lw a4,-20(s0) + 3001fa2: 4785 li a5,1 + 3001fa4: 00f70c63 beq a4,a5,3001fbc + 3001fa8: fec42703 lw a4,-20(s0) + 3001fac: 4789 li a5,2 + 3001fae: 00f70763 beq a4,a5,3001fbc + 3001fb2: fec42703 lw a4,-20(s0) + 3001fb6: 478d li a5,3 + 3001fb8: 00f71463 bne a4,a5,3001fc0 + 3001fbc: 4785 li a5,1 + 3001fbe: a011 j 3001fc2 + 3001fc0: 4781 li a5,0 + 3001fc2: 8b85 andi a5,a5,1 + 3001fc4: 9f81 uxtb a5 + 3001fc6: 853e mv a0,a5 + 3001fc8: 4472 lw s0,28(sp) + 3001fca: 6105 addi sp,sp,32 + 3001fcc: 8082 ret + +03001fce : + 3001fce: 1101 addi sp,sp,-32 + 3001fd0: ce22 sw s0,28(sp) + 3001fd2: 1000 addi s0,sp,32 + 3001fd4: fea42623 sw a0,-20(s0) + 3001fd8: fec42783 lw a5,-20(s0) + 3001fdc: c385 beqz a5,3001ffc + 3001fde: fec42703 lw a4,-20(s0) + 3001fe2: 4785 li a5,1 + 3001fe4: 00f70c63 beq a4,a5,3001ffc + 3001fe8: fec42703 lw a4,-20(s0) + 3001fec: 4789 li a5,2 + 3001fee: 00f70763 beq a4,a5,3001ffc + 3001ff2: fec42703 lw a4,-20(s0) + 3001ff6: 478d li a5,3 + 3001ff8: 00f71463 bne a4,a5,3002000 + 3001ffc: 4785 li a5,1 + 3001ffe: a011 j 3002002 + 3002000: 4781 li a5,0 + 3002002: 8b85 andi a5,a5,1 + 3002004: 9f81 uxtb a5 + 3002006: 853e mv a0,a5 + 3002008: 4472 lw s0,28(sp) + 300200a: 6105 addi sp,sp,32 + 300200c: 8082 ret + +0300200e : + 300200e: 1101 addi sp,sp,-32 + 3002010: ce06 sw ra,28(sp) + 3002012: cc22 sw s0,24(sp) + 3002014: 1000 addi s0,sp,32 + 3002016: fea42623 sw a0,-20(s0) + 300201a: feb42423 sw a1,-24(s0) + 300201e: fec42703 lw a4,-20(s0) + 3002022: 100007b7 lui a5,0x10000 + 3002026: 00f70a63 beq a4,a5,300203a + 300202a: 64b00593 li a1,1611 + 300202e: 030097b7 lui a5,0x3009 + 3002032: 95078513 addi a0,a5,-1712 # 3008950 + 3002036: 20a1 jal ra,300207e + 3002038: a001 j 3002038 + 300203a: fe842503 lw a0,-24(s0) + 300203e: 3ba9 jal ra,3001d98 + 3002040: 87aa mv a5,a0 + 3002042: 0017c793 xori a5,a5,1 + 3002046: 9f81 uxtb a5 + 3002048: cb89 beqz a5,300205a + 300204a: 64c00593 li a1,1612 + 300204e: 030097b7 lui a5,0x3009 + 3002052: 95078513 addi a0,a5,-1712 # 3008950 + 3002056: 2025 jal ra,300207e + 3002058: a839 j 3002076 + 300205a: fe842783 lw a5,-24(s0) + 300205e: 8b8d andi a5,a5,3 + 3002060: 0ff7f693 andi a3,a5,255 + 3002064: fec42703 lw a4,-20(s0) + 3002068: 10072783 lw a5,256(a4) # ea510100 + 300206c: 8a8d andi a3,a3,3 + 300206e: 9bf1 andi a5,a5,-4 + 3002070: 8fd5 or a5,a5,a3 + 3002072: 10f72023 sw a5,256(a4) + 3002076: 40f2 lw ra,28(sp) + 3002078: 4462 lw s0,24(sp) + 300207a: 6105 addi sp,sp,32 + 300207c: 8082 ret + +0300207e : + 300207e: 98aff06f j 3001208 + +03002082 : + 3002082: 7179 addi sp,sp,-48 + 3002084: d606 sw ra,44(sp) + 3002086: d422 sw s0,40(sp) + 3002088: 1800 addi s0,sp,48 + 300208a: fca42e23 sw a0,-36(s0) + 300208e: fdc42783 lw a5,-36(s0) + 3002092: eb89 bnez a5,30020a4 + 3002094: 07100593 li a1,113 + 3002098: 030097b7 lui a5,0x3009 + 300209c: 96c78513 addi a0,a5,-1684 # 300896c + 30020a0: 3ff9 jal ra,300207e + 30020a2: a001 j 30020a2 + 30020a4: fdc42783 lw a5,-36(s0) + 30020a8: 4398 lw a4,0(a5) + 30020aa: 100007b7 lui a5,0x10000 + 30020ae: 00f70a63 beq a4,a5,30020c2 + 30020b2: 07200593 li a1,114 + 30020b6: 030097b7 lui a5,0x3009 + 30020ba: 96c78513 addi a0,a5,-1684 # 300896c + 30020be: 37c1 jal ra,300207e + 30020c0: a001 j 30020c0 + 30020c2: fdc42783 lw a5,-36(s0) + 30020c6: 43dc lw a5,4(a5) + 30020c8: 853e mv a0,a5 + 30020ca: 390d jal ra,3001cfc + 30020cc: 87aa mv a5,a0 + 30020ce: 0017c793 xori a5,a5,1 + 30020d2: 9f81 uxtb a5 + 30020d4: cb91 beqz a5,30020e8 + 30020d6: 07400593 li a1,116 + 30020da: 030097b7 lui a5,0x3009 + 30020de: 96c78513 addi a0,a5,-1684 # 300896c + 30020e2: 3f71 jal ra,300207e + 30020e4: 4785 li a5,1 + 30020e6: ac99 j 300233c + 30020e8: fdc42783 lw a5,-36(s0) + 30020ec: 479c lw a5,8(a5) + 30020ee: 853e mv a0,a5 + 30020f0: 3925 jal ra,3001d28 + 30020f2: 87aa mv a5,a0 + 30020f4: 0017c793 xori a5,a5,1 + 30020f8: 9f81 uxtb a5 + 30020fa: cb91 beqz a5,300210e + 30020fc: 07500593 li a1,117 + 3002100: 030097b7 lui a5,0x3009 + 3002104: 96c78513 addi a0,a5,-1684 # 300896c + 3002108: 3f9d jal ra,300207e + 300210a: 4785 li a5,1 + 300210c: ac05 j 300233c + 300210e: fdc42783 lw a5,-36(s0) + 3002112: 47dc lw a5,12(a5) + 3002114: 853e mv a0,a5 + 3002116: 319d jal ra,3001d7c + 3002118: 87aa mv a5,a0 + 300211a: 0017c793 xori a5,a5,1 + 300211e: 9f81 uxtb a5 + 3002120: cb91 beqz a5,3002134 + 3002122: 07600593 li a1,118 + 3002126: 030097b7 lui a5,0x3009 + 300212a: 96c78513 addi a0,a5,-1684 # 300896c + 300212e: 3f81 jal ra,300207e + 3002130: 4785 li a5,1 + 3002132: a429 j 300233c + 3002134: fdc42783 lw a5,-36(s0) + 3002138: 4b9c lw a5,16(a5) + 300213a: 853e mv a0,a5 + 300213c: 3121 jal ra,3001d44 + 300213e: 87aa mv a5,a0 + 3002140: 0017c793 xori a5,a5,1 + 3002144: 9f81 uxtb a5 + 3002146: cb91 beqz a5,300215a + 3002148: 07700593 li a1,119 + 300214c: 030097b7 lui a5,0x3009 + 3002150: 96c78513 addi a0,a5,-1684 # 300896c + 3002154: 372d jal ra,300207e + 3002156: 4785 li a5,1 + 3002158: a2d5 j 300233c + 300215a: fdc42783 lw a5,-36(s0) + 300215e: 4fdc lw a5,28(a5) + 3002160: 853e mv a0,a5 + 3002162: 3efd jal ra,3001d60 + 3002164: 87aa mv a5,a0 + 3002166: 0017c793 xori a5,a5,1 + 300216a: 9f81 uxtb a5 + 300216c: cb91 beqz a5,3002180 + 300216e: 07800593 li a1,120 + 3002172: 030097b7 lui a5,0x3009 + 3002176: 96c78513 addi a0,a5,-1684 # 300896c + 300217a: 3711 jal ra,300207e + 300217c: 4785 li a5,1 + 300217e: aa7d j 300233c + 3002180: fdc42783 lw a5,-36(s0) + 3002184: 539c lw a5,32(a5) + 3002186: 853e mv a0,a5 + 3002188: 3199 jal ra,3001dce + 300218a: 87aa mv a5,a0 + 300218c: 0017c793 xori a5,a5,1 + 3002190: 9f81 uxtb a5 + 3002192: cb91 beqz a5,30021a6 + 3002194: 07a00593 li a1,122 + 3002198: 030097b7 lui a5,0x3009 + 300219c: 96c78513 addi a0,a5,-1684 # 300896c + 30021a0: 3df9 jal ra,300207e + 30021a2: 4785 li a5,1 + 30021a4: aa61 j 300233c + 30021a6: fdc42783 lw a5,-36(s0) + 30021aa: 53dc lw a5,36(a5) + 30021ac: 853e mv a0,a5 + 30021ae: 31b1 jal ra,3001dfa + 30021b0: 87aa mv a5,a0 + 30021b2: 0017c793 xori a5,a5,1 + 30021b6: 9f81 uxtb a5 + 30021b8: cb91 beqz a5,30021cc + 30021ba: 07b00593 li a1,123 + 30021be: 030097b7 lui a5,0x3009 + 30021c2: 96c78513 addi a0,a5,-1684 # 300896c + 30021c6: 3d65 jal ra,300207e + 30021c8: 4785 li a5,1 + 30021ca: aa8d j 300233c + 30021cc: fdc42783 lw a5,-36(s0) + 30021d0: 4f9c lw a5,24(a5) + 30021d2: 853e mv a0,a5 + 30021d4: 36d1 jal ra,3001d98 + 30021d6: 87aa mv a5,a0 + 30021d8: 0017c793 xori a5,a5,1 + 30021dc: 9f81 uxtb a5 + 30021de: cb91 beqz a5,30021f2 + 30021e0: 07c00593 li a1,124 + 30021e4: 030097b7 lui a5,0x3009 + 30021e8: 96c78513 addi a0,a5,-1684 # 300896c + 30021ec: 3d49 jal ra,300207e + 30021ee: 4785 li a5,1 + 30021f0: a2b1 j 300233c + 30021f2: 100017b7 lui a5,0x10001 + 30021f6: f0478793 addi a5,a5,-252 # 10000f04 + 30021fa: 670d lui a4,0x3 + 30021fc: 06e70713 addi a4,a4,110 # 306e <__bss_size__+0x14e> + 3002200: c398 sw a4,0(a5) + 3002202: fdc42783 lw a5,-36(s0) + 3002206: 439c lw a5,0(a5) + 3002208: fef42623 sw a5,-20(s0) + 300220c: 040007b7 lui a5,0x4000 + 3002210: fec42703 lw a4,-20(s0) + 3002214: 48e7aa23 sw a4,1172(a5) # 4000494 + 3002218: fdc42503 lw a0,-36(s0) + 300221c: 2d15 jal ra,3002850 + 300221e: 87aa mv a5,a0 + 3002220: c399 beqz a5,3002226 + 3002222: 4785 li a5,1 + 3002224: aa21 j 300233c + 3002226: 3451 jal ra,3001caa + 3002228: fdc42783 lw a5,-36(s0) + 300222c: 43dc lw a5,4(a5) + 300222e: 8b85 andi a5,a5,1 + 3002230: 0ff7f693 andi a3,a5,255 + 3002234: fec42703 lw a4,-20(s0) + 3002238: 431c lw a5,0(a4) + 300223a: 8a85 andi a3,a3,1 + 300223c: 9bf9 andi a5,a5,-2 + 300223e: 8fd5 or a5,a5,a3 + 3002240: c31c sw a5,0(a4) + 3002242: fdc42783 lw a5,-36(s0) + 3002246: 479c lw a5,8(a5) + 3002248: 8bbd andi a5,a5,15 + 300224a: 0ff7f693 andi a3,a5,255 + 300224e: fec42703 lw a4,-20(s0) + 3002252: 435c lw a5,4(a4) + 3002254: 8abd andi a3,a3,15 + 3002256: 9bc1 andi a5,a5,-16 + 3002258: 8fd5 or a5,a5,a3 + 300225a: c35c sw a5,4(a4) + 300225c: fdc42783 lw a5,-36(s0) + 3002260: 47dc lw a5,12(a5) + 3002262: 0ff7f693 andi a3,a5,255 + 3002266: fec42703 lw a4,-20(s0) + 300226a: 471c lw a5,8(a4) + 300226c: 0ff6f693 andi a3,a3,255 + 3002270: f007f793 andi a5,a5,-256 + 3002274: 8fd5 or a5,a5,a3 + 3002276: c71c sw a5,8(a4) + 3002278: fdc42783 lw a5,-36(s0) + 300227c: 4b9c lw a5,16(a5) + 300227e: 8bbd andi a5,a5,15 + 3002280: 0ff7f693 andi a3,a5,255 + 3002284: fec42703 lw a4,-20(s0) + 3002288: 475c lw a5,12(a4) + 300228a: 8abd andi a3,a3,15 + 300228c: 9bc1 andi a5,a5,-16 + 300228e: 8fd5 or a5,a5,a3 + 3002290: c75c sw a5,12(a4) + 3002292: fdc42783 lw a5,-36(s0) + 3002296: 4fdc lw a5,28(a5) + 3002298: 8bbd andi a5,a5,15 + 300229a: 0ff7f693 andi a3,a5,255 + 300229e: fec42703 lw a4,-20(s0) + 30022a2: 475c lw a5,12(a4) + 30022a4: 8abd andi a3,a3,15 + 30022a6: 0692 slli a3,a3,0x4 + 30022a8: f0f7f793 andi a5,a5,-241 + 30022ac: 8fd5 or a5,a5,a3 + 30022ae: c75c sw a5,12(a4) + 30022b0: fec42703 lw a4,-20(s0) + 30022b4: 4b1c lw a5,16(a4) + 30022b6: 9bf9 andi a5,a5,-2 + 30022b8: cb1c sw a5,16(a4) + 30022ba: 0001 nop + 30022bc: fec42783 lw a5,-20(s0) + 30022c0: 4fdc lw a5,28(a5) + 30022c2: 8b85 andi a5,a5,1 + 30022c4: 0ff7f713 andi a4,a5,255 + 30022c8: 4785 li a5,1 + 30022ca: fef719e3 bne a4,a5,30022bc + 30022ce: 3411 jal ra,3001cd2 + 30022d0: fdc42503 lw a0,-36(s0) + 30022d4: 2d3d jal ra,3002912 + 30022d6: 87aa mv a5,a0 + 30022d8: c399 beqz a5,30022de + 30022da: 4785 li a5,1 + 30022dc: a085 j 300233c + 30022de: 0001 nop + 30022e0: fec42703 lw a4,-20(s0) + 30022e4: 6785 lui a5,0x1 + 30022e6: 97ba add a5,a5,a4 + 30022e8: f107a783 lw a5,-240(a5) # f10 + 30022ec: 8b85 andi a5,a5,1 + 30022ee: 0ff7f713 andi a4,a5,255 + 30022f2: 4785 li a5,1 + 30022f4: fef716e3 bne a4,a5,30022e0 + 30022f8: fdc42783 lw a5,-36(s0) + 30022fc: 53dc lw a5,36(a5) + 30022fe: 03f7f793 andi a5,a5,63 + 3002302: 0ff7f693 andi a3,a5,255 + 3002306: fec42703 lw a4,-20(s0) + 300230a: 10c72783 lw a5,268(a4) + 300230e: 03f6f693 andi a3,a3,63 + 3002312: fc07f793 andi a5,a5,-64 + 3002316: 8fd5 or a5,a5,a3 + 3002318: 10f72623 sw a5,268(a4) + 300231c: fdc42783 lw a5,-36(s0) + 3002320: 539c lw a5,32(a5) + 3002322: 8b85 andi a5,a5,1 + 3002324: 0ff7f693 andi a3,a5,255 + 3002328: fec42703 lw a4,-20(s0) + 300232c: 10872783 lw a5,264(a4) + 3002330: 8a85 andi a3,a3,1 + 3002332: 9bf9 andi a5,a5,-2 + 3002334: 8fd5 or a5,a5,a3 + 3002336: 10f72423 sw a5,264(a4) + 300233a: 4781 li a5,0 + 300233c: 853e mv a0,a5 + 300233e: 50b2 lw ra,44(sp) + 3002340: 5422 lw s0,40(sp) + 3002342: 6145 addi sp,sp,48 + 3002344: 8082 ret + +03002346 : + 3002346: 7179 addi sp,sp,-48 + 3002348: d606 sw ra,44(sp) + 300234a: d422 sw s0,40(sp) + 300234c: 1800 addi s0,sp,48 + 300234e: fca42e23 sw a0,-36(s0) + 3002352: fdc42783 lw a5,-36(s0) + 3002356: eb89 bnez a5,3002368 + 3002358: 10a00593 li a1,266 + 300235c: 030097b7 lui a5,0x3009 + 3002360: 96c78513 addi a0,a5,-1684 # 300896c + 3002364: 3b29 jal ra,300207e + 3002366: a001 j 3002366 + 3002368: fdc42783 lw a5,-36(s0) + 300236c: 4398 lw a4,0(a5) + 300236e: 100007b7 lui a5,0x10000 + 3002372: 00f70a63 beq a4,a5,3002386 + 3002376: 10b00593 li a1,267 + 300237a: 030097b7 lui a5,0x3009 + 300237e: 96c78513 addi a0,a5,-1684 # 300896c + 3002382: 39f5 jal ra,300207e + 3002384: a001 j 3002384 + 3002386: fdc42783 lw a5,-36(s0) + 300238a: 4f9c lw a5,24(a5) + 300238c: 853e mv a0,a5 + 300238e: 3429 jal ra,3001d98 + 3002390: 87aa mv a5,a0 + 3002392: 0017c793 xori a5,a5,1 + 3002396: 9f81 uxtb a5 + 3002398: cb91 beqz a5,30023ac + 300239a: 10c00593 li a1,268 + 300239e: 030097b7 lui a5,0x3009 + 30023a2: 96c78513 addi a0,a5,-1684 # 300896c + 30023a6: 39e1 jal ra,300207e + 30023a8: 4785 li a5,1 + 30023aa: a005 j 30023ca + 30023ac: fdc42783 lw a5,-36(s0) + 30023b0: 439c lw a5,0(a5) + 30023b2: fef42623 sw a5,-20(s0) + 30023b6: 38d5 jal ra,3001caa + 30023b8: fdc42783 lw a5,-36(s0) + 30023bc: 4f9c lw a5,24(a5) + 30023be: 85be mv a1,a5 + 30023c0: fec42503 lw a0,-20(s0) + 30023c4: 31a9 jal ra,300200e + 30023c6: 3231 jal ra,3001cd2 + 30023c8: 4781 li a5,0 + 30023ca: 853e mv a0,a5 + 30023cc: 50b2 lw ra,44(sp) + 30023ce: 5422 lw s0,40(sp) + 30023d0: 6145 addi sp,sp,48 + 30023d2: 8082 ret + +030023d4 : + 30023d4: 1101 addi sp,sp,-32 + 30023d6: ce06 sw ra,28(sp) + 30023d8: cc22 sw s0,24(sp) + 30023da: 1000 addi s0,sp,32 + 30023dc: 040007b7 lui a5,0x4000 + 30023e0: 4947a783 lw a5,1172(a5) # 4000494 + 30023e4: fef42623 sw a5,-20(s0) + 30023e8: fec42703 lw a4,-20(s0) + 30023ec: 100007b7 lui a5,0x10000 + 30023f0: 00f70a63 beq a4,a5,3002404 + 30023f4: 12200593 li a1,290 + 30023f8: 030097b7 lui a5,0x3009 + 30023fc: 96c78513 addi a0,a5,-1684 # 300896c + 3002400: 39bd jal ra,300207e + 3002402: a001 j 3002402 + 3002404: fec42783 lw a5,-20(s0) + 3002408: 439c lw a5,0(a5) + 300240a: 8b85 andi a5,a5,1 + 300240c: 9f81 uxtb a5 + 300240e: 853e mv a0,a5 + 3002410: 2b91 jal ra,3002964 + 3002412: fea42423 sw a0,-24(s0) + 3002416: fec42783 lw a5,-20(s0) + 300241a: 43dc lw a5,4(a5) + 300241c: 8bbd andi a5,a5,15 + 300241e: 9f81 uxtb a5 + 3002420: 853e mv a0,a5 + 3002422: 23b5 jal ra,300298e + 3002424: 872a mv a4,a0 + 3002426: fe842783 lw a5,-24(s0) + 300242a: 02e7d7b3 divu a5,a5,a4 + 300242e: fef42423 sw a5,-24(s0) + 3002432: fec42783 lw a5,-20(s0) + 3002436: 479c lw a5,8(a5) + 3002438: 9f81 uxtb a5 + 300243a: 853e mv a0,a5 + 300243c: 2341 jal ra,30029bc + 300243e: fea42223 sw a0,-28(s0) + 3002442: fe442783 lw a5,-28(s0) + 3002446: 4719 li a4,6 + 3002448: 00e7f363 bgeu a5,a4,300244e + 300244c: 4799 li a5,6 + 300244e: fe842703 lw a4,-24(s0) + 3002452: 02f707b3 mul a5,a4,a5 + 3002456: fef42423 sw a5,-24(s0) + 300245a: fe842783 lw a5,-24(s0) + 300245e: 853e mv a0,a5 + 3002460: 40f2 lw ra,28(sp) + 3002462: 4462 lw s0,24(sp) + 3002464: 6105 addi sp,sp,32 + 3002466: 8082 ret + +03002468 : + 3002468: 1101 addi sp,sp,-32 + 300246a: ce06 sw ra,28(sp) + 300246c: cc22 sw s0,24(sp) + 300246e: 1000 addi s0,sp,32 + 3002470: 040007b7 lui a5,0x4000 + 3002474: 4947a783 lw a5,1172(a5) # 4000494 + 3002478: fef42423 sw a5,-24(s0) + 300247c: fe842703 lw a4,-24(s0) + 3002480: 100007b7 lui a5,0x10000 + 3002484: 00f70a63 beq a4,a5,3002498 + 3002488: 13700593 li a1,311 + 300248c: 030097b7 lui a5,0x3009 + 3002490: 96c78513 addi a0,a5,-1684 # 300896c + 3002494: 36ed jal ra,300207e + 3002496: a001 j 3002496 + 3002498: 3f35 jal ra,30023d4 + 300249a: fea42623 sw a0,-20(s0) + 300249e: fe842783 lw a5,-24(s0) + 30024a2: 47dc lw a5,12(a5) + 30024a4: 8bbd andi a5,a5,15 + 30024a6: 9f81 uxtb a5 + 30024a8: 853e mv a0,a5 + 30024aa: 2b91 jal ra,30029fe + 30024ac: fea42223 sw a0,-28(s0) + 30024b0: fe442783 lw a5,-28(s0) + 30024b4: cb89 beqz a5,30024c6 + 30024b6: fec42703 lw a4,-20(s0) + 30024ba: fe442783 lw a5,-28(s0) + 30024be: 02f757b3 divu a5,a4,a5 + 30024c2: fef42623 sw a5,-20(s0) + 30024c6: fec42783 lw a5,-20(s0) + 30024ca: 853e mv a0,a5 + 30024cc: 40f2 lw ra,28(sp) + 30024ce: 4462 lw s0,24(sp) + 30024d0: 6105 addi sp,sp,32 + 30024d2: 8082 ret + +030024d4 : + 30024d4: 1101 addi sp,sp,-32 + 30024d6: ce06 sw ra,28(sp) + 30024d8: cc22 sw s0,24(sp) + 30024da: 1000 addi s0,sp,32 + 30024dc: 040007b7 lui a5,0x4000 + 30024e0: 4947a783 lw a5,1172(a5) # 4000494 + 30024e4: fef42423 sw a5,-24(s0) + 30024e8: fe842703 lw a4,-24(s0) + 30024ec: 100007b7 lui a5,0x10000 + 30024f0: 00f70a63 beq a4,a5,3002504 + 30024f4: 14c00593 li a1,332 + 30024f8: 030097b7 lui a5,0x3009 + 30024fc: 96c78513 addi a0,a5,-1684 # 300896c + 3002500: 3ebd jal ra,300207e + 3002502: a001 j 3002502 + 3002504: fe842783 lw a5,-24(s0) + 3002508: 1007a783 lw a5,256(a5) + 300250c: 8b8d andi a5,a5,3 + 300250e: 9f81 uxtb a5 + 3002510: fef42223 sw a5,-28(s0) + 3002514: fe442783 lw a5,-28(s0) + 3002518: 4705 li a4,1 + 300251a: 02e78063 beq a5,a4,300253a + 300251e: 4705 li a4,1 + 3002520: 00e7e663 bltu a5,a4,300252c + 3002524: 4709 li a4,2 + 3002526: 02e78163 beq a5,a4,3002548 + 300252a: a01d j 3002550 + 300252c: 017d87b7 lui a5,0x17d8 + 3002530: 84078793 addi a5,a5,-1984 # 17d7840 + 3002534: fef42623 sw a5,-20(s0) + 3002538: a015 j 300255c + 300253a: 01c9c7b7 lui a5,0x1c9c + 300253e: 38078793 addi a5,a5,896 # 1c9c380 + 3002542: fef42623 sw a5,-20(s0) + 3002546: a819 j 300255c + 3002548: 3705 jal ra,3002468 + 300254a: fea42623 sw a0,-20(s0) + 300254e: a039 j 300255c + 3002550: 67a1 lui a5,0x8 + 3002552: d0078793 addi a5,a5,-768 # 7d00 + 3002556: fef42623 sw a5,-20(s0) + 300255a: 0001 nop + 300255c: fec42783 lw a5,-20(s0) + 3002560: 853e mv a0,a5 + 3002562: 40f2 lw ra,28(sp) + 3002564: 4462 lw s0,24(sp) + 3002566: 6105 addi sp,sp,32 + 3002568: 8082 ret + +0300256a : + 300256a: 7179 addi sp,sp,-48 + 300256c: d606 sw ra,44(sp) + 300256e: d422 sw s0,40(sp) + 3002570: 1800 addi s0,sp,48 + 3002572: fca42e23 sw a0,-36(s0) + 3002576: fdc42783 lw a5,-36(s0) + 300257a: eb89 bnez a5,300258c + 300257c: 16900593 li a1,361 + 3002580: 030097b7 lui a5,0x3009 + 3002584: 96c78513 addi a0,a5,-1684 # 300896c + 3002588: 3cdd jal ra,300207e + 300258a: a001 j 300258a + 300258c: 040007b7 lui a5,0x4000 + 3002590: 4947a703 lw a4,1172(a5) # 4000494 + 3002594: 100007b7 lui a5,0x10000 + 3002598: 00f70a63 beq a4,a5,30025ac + 300259c: 16a00593 li a1,362 + 30025a0: 030097b7 lui a5,0x3009 + 30025a4: 96c78513 addi a0,a5,-1684 # 300896c + 30025a8: 3cd9 jal ra,300207e + 30025aa: a001 j 30025aa + 30025ac: 3725 jal ra,30024d4 + 30025ae: fea42423 sw a0,-24(s0) + 30025b2: 67a1 lui a5,0x8 + 30025b4: d0078793 addi a5,a5,-768 # 7d00 + 30025b8: fef42623 sw a5,-20(s0) + 30025bc: fdc42503 lw a0,-36(s0) + 30025c0: be5fe0ef jal ra,30011a4 + 30025c4: fea42223 sw a0,-28(s0) + 30025c8: fe442783 lw a5,-28(s0) + 30025cc: e781 bnez a5,30025d4 + 30025ce: fec42783 lw a5,-20(s0) + 30025d2: a895 j 3002646 + 30025d4: fe442783 lw a5,-28(s0) + 30025d8: 43dc lw a5,4(a5) + 30025da: 4715 li a4,5 + 30025dc: 04f76a63 bltu a4,a5,3002630 + 30025e0: 00279713 slli a4,a5,0x2 + 30025e4: 030097b7 lui a5,0x3009 + 30025e8: 9a878793 addi a5,a5,-1624 # 30089a8 + 30025ec: 97ba add a5,a5,a4 + 30025ee: 439c lw a5,0(a5) + 30025f0: 8782 jr a5 + 30025f2: fe842783 lw a5,-24(s0) + 30025f6: fef42623 sw a5,-20(s0) + 30025fa: a825 j 3002632 + 30025fc: 040007b7 lui a5,0x4000 + 3002600: 4947a783 lw a5,1172(a5) # 4000494 + 3002604: 439c lw a5,0(a5) + 3002606: 8b85 andi a5,a5,1 + 3002608: 9f81 uxtb a5 + 300260a: 853e mv a0,a5 + 300260c: 2ea1 jal ra,3002964 + 300260e: fea42623 sw a0,-20(s0) + 3002612: a005 j 3002632 + 3002614: 35c1 jal ra,30024d4 + 3002616: fea42023 sw a0,-32(s0) + 300261a: 3b6d jal ra,30023d4 + 300261c: 87aa mv a5,a0 + 300261e: fe042603 lw a2,-32(s0) + 3002622: 85be mv a1,a5 + 3002624: fe442503 lw a0,-28(s0) + 3002628: 2209 jal ra,300272a + 300262a: fea42623 sw a0,-20(s0) + 300262e: a011 j 3002632 + 3002630: 0001 nop + 3002632: fec42783 lw a5,-20(s0) + 3002636: e791 bnez a5,3002642 + 3002638: 67a1 lui a5,0x8 + 300263a: d0078793 addi a5,a5,-768 # 7d00 + 300263e: fef42623 sw a5,-20(s0) + 3002642: fec42783 lw a5,-20(s0) + 3002646: 853e mv a0,a5 + 3002648: 50b2 lw ra,44(sp) + 300264a: 5422 lw s0,40(sp) + 300264c: 6145 addi sp,sp,48 + 300264e: 8082 ret + +03002650 : + 3002650: 7179 addi sp,sp,-48 + 3002652: d606 sw ra,44(sp) + 3002654: d422 sw s0,40(sp) + 3002656: 1800 addi s0,sp,48 + 3002658: fca42e23 sw a0,-36(s0) + 300265c: fcb42c23 sw a1,-40(s0) + 3002660: fdc42783 lw a5,-36(s0) + 3002664: eb89 bnez a5,3002676 + 3002666: 19c00593 li a1,412 + 300266a: 030097b7 lui a5,0x3009 + 300266e: 96c78513 addi a0,a5,-1684 # 300896c + 3002672: 3431 jal ra,300207e + 3002674: a001 j 3002674 + 3002676: 040007b7 lui a5,0x4000 + 300267a: 4947a703 lw a4,1172(a5) # 4000494 + 300267e: 100007b7 lui a5,0x10000 + 3002682: 00f70a63 beq a4,a5,3002696 + 3002686: 19d00593 li a1,413 + 300268a: 030097b7 lui a5,0x3009 + 300268e: 96c78513 addi a0,a5,-1684 # 300896c + 3002692: 32f5 jal ra,300207e + 3002694: a001 j 3002694 + 3002696: fd842703 lw a4,-40(s0) + 300269a: 4785 li a5,1 + 300269c: 00f70e63 beq a4,a5,30026b8 + 30026a0: fd842783 lw a5,-40(s0) + 30026a4: cb91 beqz a5,30026b8 + 30026a6: 19f00593 li a1,415 + 30026aa: 030097b7 lui a5,0x3009 + 30026ae: 96c78513 addi a0,a5,-1684 # 300896c + 30026b2: 32f1 jal ra,300207e + 30026b4: 4785 li a5,1 + 30026b6: a0ad j 3002720 + 30026b8: fdc42503 lw a0,-36(s0) + 30026bc: ae9fe0ef jal ra,30011a4 + 30026c0: fea42623 sw a0,-20(s0) + 30026c4: fec42783 lw a5,-20(s0) + 30026c8: c799 beqz a5,30026d6 + 30026ca: fec42783 lw a5,-20(s0) + 30026ce: 43d8 lw a4,4(a5) + 30026d0: 4795 li a5,5 + 30026d2: 00e7f463 bgeu a5,a4,30026da + 30026d6: 4785 li a5,1 + 30026d8: a0a1 j 3002720 + 30026da: fec42783 lw a5,-20(s0) + 30026de: 43d4 lw a3,4(a5) + 30026e0: 040007b7 lui a5,0x4000 + 30026e4: 02478713 addi a4,a5,36 # 4000024 + 30026e8: 02400793 li a5,36 + 30026ec: 02f687b3 mul a5,a3,a5 + 30026f0: 97ba add a5,a5,a4 + 30026f2: 479c lw a5,8(a5) + 30026f4: e399 bnez a5,30026fa + 30026f6: 4785 li a5,1 + 30026f8: a025 j 3002720 + 30026fa: fec42783 lw a5,-20(s0) + 30026fe: 43d4 lw a3,4(a5) + 3002700: 040007b7 lui a5,0x4000 + 3002704: 02478713 addi a4,a5,36 # 4000024 + 3002708: 02400793 li a5,36 + 300270c: 02f687b3 mul a5,a3,a5 + 3002710: 97ba add a5,a5,a4 + 3002712: 479c lw a5,8(a5) + 3002714: fd842583 lw a1,-40(s0) + 3002718: fec42503 lw a0,-20(s0) + 300271c: 9782 jalr a5 + 300271e: 4781 li a5,0 + 3002720: 853e mv a0,a5 + 3002722: 50b2 lw ra,44(sp) + 3002724: 5422 lw s0,40(sp) + 3002726: 6145 addi sp,sp,48 + 3002728: 8082 ret + +0300272a : + 300272a: 7139 addi sp,sp,-64 + 300272c: de06 sw ra,60(sp) + 300272e: dc22 sw s0,56(sp) + 3002730: 0080 addi s0,sp,64 + 3002732: fca42623 sw a0,-52(s0) + 3002736: fcb42423 sw a1,-56(s0) + 300273a: fcc42223 sw a2,-60(s0) + 300273e: fcc42783 lw a5,-52(s0) + 3002742: eb89 bnez a5,3002754 + 3002744: 2af00593 li a1,687 + 3002748: 030097b7 lui a5,0x3009 + 300274c: 96c78513 addi a0,a5,-1684 # 300896c + 3002750: 27a1 jal ra,3002e98 + 3002752: a001 j 3002752 + 3002754: 040007b7 lui a5,0x4000 + 3002758: 4947a783 lw a5,1172(a5) # 4000494 + 300275c: eb89 bnez a5,300276e + 300275e: 2b000593 li a1,688 + 3002762: 030097b7 lui a5,0x3009 + 3002766: 96c78513 addi a0,a5,-1684 # 300896c + 300276a: 273d jal ra,3002e98 + 300276c: a001 j 300276c + 300276e: fe042623 sw zero,-20(s0) + 3002772: fcc42783 lw a5,-52(s0) + 3002776: 43d8 lw a4,4(a5) + 3002778: 02400793 li a5,36 + 300277c: 02f70733 mul a4,a4,a5 + 3002780: 040007b7 lui a5,0x4000 + 3002784: 02478793 addi a5,a5,36 # 4000024 + 3002788: 97ba add a5,a5,a4 + 300278a: fef42423 sw a5,-24(s0) + 300278e: fe842783 lw a5,-24(s0) + 3002792: 4fdc lw a5,28(a5) + 3002794: e399 bnez a5,300279a + 3002796: 4781 li a5,0 + 3002798: a07d j 3002846 + 300279a: fe842783 lw a5,-24(s0) + 300279e: 4fdc lw a5,28(a5) + 30027a0: fcc42503 lw a0,-52(s0) + 30027a4: 9782 jalr a5 + 30027a6: fea42223 sw a0,-28(s0) + 30027aa: fe442703 lw a4,-28(s0) + 30027ae: 478d li a5,3 + 30027b0: 00f71763 bne a4,a5,30027be + 30027b4: fc442783 lw a5,-60(s0) + 30027b8: fef42623 sw a5,-20(s0) + 30027bc: a085 j 300281c + 30027be: fe442783 lw a5,-28(s0) + 30027c2: eb81 bnez a5,30027d2 + 30027c4: 017d87b7 lui a5,0x17d8 + 30027c8: 84078793 addi a5,a5,-1984 # 17d7840 + 30027cc: fef42623 sw a5,-20(s0) + 30027d0: a0b1 j 300281c + 30027d2: fe442703 lw a4,-28(s0) + 30027d6: 4785 li a5,1 + 30027d8: 00f71963 bne a4,a5,30027ea + 30027dc: 01c9c7b7 lui a5,0x1c9c + 30027e0: 38078793 addi a5,a5,896 # 1c9c380 + 30027e4: fef42623 sw a5,-20(s0) + 30027e8: a815 j 300281c + 30027ea: fe442703 lw a4,-28(s0) + 30027ee: 4789 li a5,2 + 30027f0: 02f71663 bne a4,a5,300281c + 30027f4: 040007b7 lui a5,0x4000 + 30027f8: 4947a783 lw a5,1172(a5) # 4000494 + 30027fc: 47dc lw a5,12(a5) + 30027fe: 8391 srli a5,a5,0x4 + 3002800: 8bbd andi a5,a5,15 + 3002802: 9f81 uxtb a5 + 3002804: 853e mv a0,a5 + 3002806: 2ae5 jal ra,30029fe + 3002808: fea42023 sw a0,-32(s0) + 300280c: fc842703 lw a4,-56(s0) + 3002810: fe042783 lw a5,-32(s0) + 3002814: 02f757b3 divu a5,a4,a5 + 3002818: fef42623 sw a5,-20(s0) + 300281c: fe842783 lw a5,-24(s0) + 3002820: 539c lw a5,32(a5) + 3002822: e399 bnez a5,3002828 + 3002824: 4781 li a5,0 + 3002826: a005 j 3002846 + 3002828: fe842783 lw a5,-24(s0) + 300282c: 539c lw a5,32(a5) + 300282e: fcc42503 lw a0,-52(s0) + 3002832: 9782 jalr a5 + 3002834: fca42e23 sw a0,-36(s0) + 3002838: fdc42783 lw a5,-36(s0) + 300283c: 0785 addi a5,a5,1 + 300283e: fec42703 lw a4,-20(s0) + 3002842: 02f757b3 divu a5,a4,a5 + 3002846: 853e mv a0,a5 + 3002848: 50f2 lw ra,60(sp) + 300284a: 5462 lw s0,56(sp) + 300284c: 6121 addi sp,sp,64 + 300284e: 8082 ret + +03002850 : + 3002850: 7179 addi sp,sp,-48 + 3002852: d606 sw ra,44(sp) + 3002854: d422 sw s0,40(sp) + 3002856: 1800 addi s0,sp,48 + 3002858: fca42e23 sw a0,-36(s0) + 300285c: fdc42783 lw a5,-36(s0) + 3002860: 43dc lw a5,4(a5) + 3002862: 853e mv a0,a5 + 3002864: 2201 jal ra,3002964 + 3002866: fea42623 sw a0,-20(s0) + 300286a: fdc42783 lw a5,-36(s0) + 300286e: 479c lw a5,8(a5) + 3002870: 853e mv a0,a5 + 3002872: 2a31 jal ra,300298e + 3002874: fea42423 sw a0,-24(s0) + 3002878: fe842583 lw a1,-24(s0) + 300287c: fec42503 lw a0,-20(s0) + 3002880: d96ff0ef jal ra,3001e16 + 3002884: 87aa mv a5,a0 + 3002886: 0017c793 xori a5,a5,1 + 300288a: 9f81 uxtb a5 + 300288c: c399 beqz a5,3002892 + 300288e: 4785 li a5,1 + 3002890: a8a5 j 3002908 + 3002892: fec42703 lw a4,-20(s0) + 3002896: fe842783 lw a5,-24(s0) + 300289a: 02f757b3 divu a5,a4,a5 + 300289e: fef42623 sw a5,-20(s0) + 30028a2: fdc42783 lw a5,-36(s0) + 30028a6: 47dc lw a5,12(a5) + 30028a8: 85be mv a1,a5 + 30028aa: fec42503 lw a0,-20(s0) + 30028ae: dc6ff0ef jal ra,3001e74 + 30028b2: 87aa mv a5,a0 + 30028b4: 0017c793 xori a5,a5,1 + 30028b8: 9f81 uxtb a5 + 30028ba: c399 beqz a5,30028c0 + 30028bc: 4785 li a5,1 + 30028be: a0a9 j 3002908 + 30028c0: fdc42783 lw a5,-36(s0) + 30028c4: 47dc lw a5,12(a5) + 30028c6: 4719 li a4,6 + 30028c8: 00e7f363 bgeu a5,a4,30028ce + 30028cc: 4799 li a5,6 + 30028ce: fec42703 lw a4,-20(s0) + 30028d2: 02f707b3 mul a5,a4,a5 + 30028d6: fef42623 sw a5,-20(s0) + 30028da: fdc42783 lw a5,-36(s0) + 30028de: 4b9c lw a5,16(a5) + 30028e0: 85be mv a1,a5 + 30028e2: fec42503 lw a0,-20(s0) + 30028e6: e18ff0ef jal ra,3001efe + 30028ea: 87aa mv a5,a0 + 30028ec: cf89 beqz a5,3002906 + 30028ee: fdc42783 lw a5,-36(s0) + 30028f2: 4fdc lw a5,28(a5) + 30028f4: 85be mv a1,a5 + 30028f6: fec42503 lw a0,-20(s0) + 30028fa: e4cff0ef jal ra,3001f46 + 30028fe: 87aa mv a5,a0 + 3002900: c399 beqz a5,3002906 + 3002902: 4781 li a5,0 + 3002904: a011 j 3002908 + 3002906: 4785 li a5,1 + 3002908: 853e mv a0,a5 + 300290a: 50b2 lw ra,44(sp) + 300290c: 5422 lw s0,40(sp) + 300290e: 6145 addi sp,sp,48 + 3002910: 8082 ret + +03002912 : + 3002912: 7179 addi sp,sp,-48 + 3002914: d622 sw s0,44(sp) + 3002916: 1800 addi s0,sp,48 + 3002918: fca42e23 sw a0,-36(s0) + 300291c: fdc42783 lw a5,-36(s0) + 3002920: 539c lw a5,32(a5) + 3002922: e791 bnez a5,300292e + 3002924: 017d87b7 lui a5,0x17d8 + 3002928: 84078793 addi a5,a5,-1984 # 17d7840 + 300292c: a029 j 3002936 + 300292e: 01c9c7b7 lui a5,0x1c9c + 3002932: 38078793 addi a5,a5,896 # 1c9c380 + 3002936: fef42623 sw a5,-20(s0) + 300293a: fdc42783 lw a5,-36(s0) + 300293e: 53dc lw a5,36(a5) + 3002940: 0785 addi a5,a5,1 + 3002942: fec42703 lw a4,-20(s0) + 3002946: 02f75733 divu a4,a4,a5 + 300294a: 000f47b7 lui a5,0xf4 + 300294e: 24078793 addi a5,a5,576 # f4240 + 3002952: 00f71463 bne a4,a5,300295a + 3002956: 4781 li a5,0 + 3002958: a011 j 300295c + 300295a: 4785 li a5,1 + 300295c: 853e mv a0,a5 + 300295e: 5432 lw s0,44(sp) + 3002960: 6145 addi sp,sp,48 + 3002962: 8082 ret + +03002964 : + 3002964: 1101 addi sp,sp,-32 + 3002966: ce22 sw s0,28(sp) + 3002968: 1000 addi s0,sp,32 + 300296a: fea42623 sw a0,-20(s0) + 300296e: fec42783 lw a5,-20(s0) + 3002972: e791 bnez a5,300297e + 3002974: 017d87b7 lui a5,0x17d8 + 3002978: 84078793 addi a5,a5,-1984 # 17d7840 + 300297c: a029 j 3002986 + 300297e: 01c9c7b7 lui a5,0x1c9c + 3002982: 38078793 addi a5,a5,896 # 1c9c380 + 3002986: 853e mv a0,a5 + 3002988: 4472 lw s0,28(sp) + 300298a: 6105 addi sp,sp,32 + 300298c: 8082 ret + +0300298e : + 300298e: 7179 addi sp,sp,-48 + 3002990: d622 sw s0,44(sp) + 3002992: 1800 addi s0,sp,48 + 3002994: fca42e23 sw a0,-36(s0) + 3002998: fdc42783 lw a5,-36(s0) + 300299c: e789 bnez a5,30029a6 + 300299e: 4785 li a5,1 + 30029a0: fef42623 sw a5,-20(s0) + 30029a4: a031 j 30029b0 + 30029a6: fdc42783 lw a5,-36(s0) + 30029aa: 0785 addi a5,a5,1 + 30029ac: fef42623 sw a5,-20(s0) + 30029b0: fec42783 lw a5,-20(s0) + 30029b4: 853e mv a0,a5 + 30029b6: 5432 lw s0,44(sp) + 30029b8: 6145 addi sp,sp,48 + 30029ba: 8082 ret + +030029bc : + 30029bc: 7179 addi sp,sp,-48 + 30029be: d622 sw s0,44(sp) + 30029c0: 1800 addi s0,sp,48 + 30029c2: fca42e23 sw a0,-36(s0) + 30029c6: fdc42783 lw a5,-36(s0) + 30029ca: fef42623 sw a5,-20(s0) + 30029ce: fec42703 lw a4,-20(s0) + 30029d2: 4795 li a5,5 + 30029d4: 00e7e563 bltu a5,a4,30029de + 30029d8: 4799 li a5,6 + 30029da: fef42623 sw a5,-20(s0) + 30029de: fec42703 lw a4,-20(s0) + 30029e2: 07f00793 li a5,127 + 30029e6: 00e7f663 bgeu a5,a4,30029f2 + 30029ea: 07f00793 li a5,127 + 30029ee: fef42623 sw a5,-20(s0) + 30029f2: fec42783 lw a5,-20(s0) + 30029f6: 853e mv a0,a5 + 30029f8: 5432 lw s0,44(sp) + 30029fa: 6145 addi sp,sp,48 + 30029fc: 8082 ret + +030029fe : + 30029fe: 7179 addi sp,sp,-48 + 3002a00: d622 sw s0,44(sp) + 3002a02: 1800 addi s0,sp,48 + 3002a04: fca42e23 sw a0,-36(s0) + 3002a08: fdc42783 lw a5,-36(s0) + 3002a0c: fef42623 sw a5,-20(s0) + 3002a10: fec42703 lw a4,-20(s0) + 3002a14: 479d li a5,7 + 3002a16: 00e7f663 bgeu a5,a4,3002a22 + 3002a1a: 47a1 li a5,8 + 3002a1c: fef42623 sw a5,-20(s0) + 3002a20: a031 j 3002a2c + 3002a22: fec42783 lw a5,-20(s0) + 3002a26: 0785 addi a5,a5,1 + 3002a28: fef42623 sw a5,-20(s0) + 3002a2c: fec42783 lw a5,-20(s0) + 3002a30: 853e mv a0,a5 + 3002a32: 5432 lw s0,44(sp) + 3002a34: 6145 addi sp,sp,48 + 3002a36: 8082 ret + +03002a38 : + 3002a38: 7179 addi sp,sp,-48 + 3002a3a: d606 sw ra,44(sp) + 3002a3c: d422 sw s0,40(sp) + 3002a3e: 1800 addi s0,sp,48 + 3002a40: fca42e23 sw a0,-36(s0) + 3002a44: fcb42c23 sw a1,-40(s0) + 3002a48: fdc42783 lw a5,-36(s0) + 3002a4c: eb89 bnez a5,3002a5e + 3002a4e: 34d00593 li a1,845 + 3002a52: 030097b7 lui a5,0x3009 + 3002a56: 96c78513 addi a0,a5,-1684 # 300896c + 3002a5a: 293d jal ra,3002e98 + 3002a5c: a001 j 3002a5c + 3002a5e: 040007b7 lui a5,0x4000 + 3002a62: 4947a783 lw a5,1172(a5) # 4000494 + 3002a66: eb89 bnez a5,3002a78 + 3002a68: 34e00593 li a1,846 + 3002a6c: 030097b7 lui a5,0x3009 + 3002a70: 96c78513 addi a0,a5,-1684 # 300896c + 3002a74: 2115 jal ra,3002e98 + 3002a76: a001 j 3002a76 + 3002a78: 040007b7 lui a5,0x4000 + 3002a7c: 4947a783 lw a5,1172(a5) # 4000494 + 3002a80: fef42623 sw a5,-20(s0) + 3002a84: fdc42783 lw a5,-36(s0) + 3002a88: 279e lhu a5,8(a5) + 3002a8a: 873e mv a4,a5 + 3002a8c: fec42783 lw a5,-20(s0) + 3002a90: 97ba add a5,a5,a4 + 3002a92: fef42423 sw a5,-24(s0) + 3002a96: fe842783 lw a5,-24(s0) + 3002a9a: 439c lw a5,0(a5) + 3002a9c: fef42223 sw a5,-28(s0) + 3002aa0: fd842783 lw a5,-40(s0) + 3002aa4: 8b85 andi a5,a5,1 + 3002aa6: c7c1 beqz a5,3002b2e + 3002aa8: fe442783 lw a5,-28(s0) + 3002aac: 9fa1 uxth a5 + 3002aae: 01079713 slli a4,a5,0x10 + 3002ab2: 8741 srai a4,a4,0x10 + 3002ab4: fdc42783 lw a5,-36(s0) + 3002ab8: 27bc lbu a5,10(a5) + 3002aba: 86be mv a3,a5 + 3002abc: 4785 li a5,1 + 3002abe: 00d797b3 sll a5,a5,a3 + 3002ac2: 07c2 slli a5,a5,0x10 + 3002ac4: 87c1 srai a5,a5,0x10 + 3002ac6: 8fd9 or a5,a5,a4 + 3002ac8: 07c2 slli a5,a5,0x10 + 3002aca: 87c1 srai a5,a5,0x10 + 3002acc: 01079693 slli a3,a5,0x10 + 3002ad0: 82c1 srli a3,a3,0x10 + 3002ad2: fe442783 lw a5,-28(s0) + 3002ad6: 6741 lui a4,0x10 + 3002ad8: 177d addi a4,a4,-1 # ffff + 3002ada: 8f75 and a4,a4,a3 + 3002adc: 76c1 lui a3,0xffff0 + 3002ade: 8ff5 and a5,a5,a3 + 3002ae0: 8fd9 or a5,a5,a4 + 3002ae2: fef42223 sw a5,-28(s0) + 3002ae6: fe442783 lw a5,-28(s0) + 3002aea: 83c1 srli a5,a5,0x10 + 3002aec: 9fa1 uxth a5 + 3002aee: 01079713 slli a4,a5,0x10 + 3002af2: 8741 srai a4,a4,0x10 + 3002af4: fdc42783 lw a5,-36(s0) + 3002af8: 27bc lbu a5,10(a5) + 3002afa: 86be mv a3,a5 + 3002afc: 4785 li a5,1 + 3002afe: 00d797b3 sll a5,a5,a3 + 3002b02: 07c2 slli a5,a5,0x10 + 3002b04: 87c1 srai a5,a5,0x10 + 3002b06: fff7c793 not a5,a5 + 3002b0a: 07c2 slli a5,a5,0x10 + 3002b0c: 87c1 srai a5,a5,0x10 + 3002b0e: 8ff9 and a5,a5,a4 + 3002b10: 07c2 slli a5,a5,0x10 + 3002b12: 87c1 srai a5,a5,0x10 + 3002b14: 01079713 slli a4,a5,0x10 + 3002b18: 8341 srli a4,a4,0x10 + 3002b1a: fe442783 lw a5,-28(s0) + 3002b1e: 0742 slli a4,a4,0x10 + 3002b20: 66c1 lui a3,0x10 + 3002b22: 16fd addi a3,a3,-1 # ffff + 3002b24: 8ff5 and a5,a5,a3 + 3002b26: 8fd9 or a5,a5,a4 + 3002b28: fef42223 sw a5,-28(s0) + 3002b2c: a059 j 3002bb2 + 3002b2e: fe442783 lw a5,-28(s0) + 3002b32: 9fa1 uxth a5 + 3002b34: 01079713 slli a4,a5,0x10 + 3002b38: 8741 srai a4,a4,0x10 + 3002b3a: fdc42783 lw a5,-36(s0) + 3002b3e: 27bc lbu a5,10(a5) + 3002b40: 86be mv a3,a5 + 3002b42: 4785 li a5,1 + 3002b44: 00d797b3 sll a5,a5,a3 + 3002b48: 07c2 slli a5,a5,0x10 + 3002b4a: 87c1 srai a5,a5,0x10 + 3002b4c: fff7c793 not a5,a5 + 3002b50: 07c2 slli a5,a5,0x10 + 3002b52: 87c1 srai a5,a5,0x10 + 3002b54: 8ff9 and a5,a5,a4 + 3002b56: 07c2 slli a5,a5,0x10 + 3002b58: 87c1 srai a5,a5,0x10 + 3002b5a: 01079693 slli a3,a5,0x10 + 3002b5e: 82c1 srli a3,a3,0x10 + 3002b60: fe442783 lw a5,-28(s0) + 3002b64: 6741 lui a4,0x10 + 3002b66: 177d addi a4,a4,-1 # ffff + 3002b68: 8f75 and a4,a4,a3 + 3002b6a: 76c1 lui a3,0xffff0 + 3002b6c: 8ff5 and a5,a5,a3 + 3002b6e: 8fd9 or a5,a5,a4 + 3002b70: fef42223 sw a5,-28(s0) + 3002b74: fe442783 lw a5,-28(s0) + 3002b78: 83c1 srli a5,a5,0x10 + 3002b7a: 9fa1 uxth a5 + 3002b7c: 01079713 slli a4,a5,0x10 + 3002b80: 8741 srai a4,a4,0x10 + 3002b82: fdc42783 lw a5,-36(s0) + 3002b86: 27bc lbu a5,10(a5) + 3002b88: 86be mv a3,a5 + 3002b8a: 4785 li a5,1 + 3002b8c: 00d797b3 sll a5,a5,a3 + 3002b90: 07c2 slli a5,a5,0x10 + 3002b92: 87c1 srai a5,a5,0x10 + 3002b94: 8fd9 or a5,a5,a4 + 3002b96: 07c2 slli a5,a5,0x10 + 3002b98: 87c1 srai a5,a5,0x10 + 3002b9a: 01079713 slli a4,a5,0x10 + 3002b9e: 8341 srli a4,a4,0x10 + 3002ba0: fe442783 lw a5,-28(s0) + 3002ba4: 0742 slli a4,a4,0x10 + 3002ba6: 66c1 lui a3,0x10 + 3002ba8: 16fd addi a3,a3,-1 # ffff + 3002baa: 8ff5 and a5,a5,a3 + 3002bac: 8fd9 or a5,a5,a4 + 3002bae: fef42223 sw a5,-28(s0) + 3002bb2: fe442703 lw a4,-28(s0) + 3002bb6: fe842783 lw a5,-24(s0) + 3002bba: c398 sw a4,0(a5) + 3002bbc: 0001 nop + 3002bbe: 50b2 lw ra,44(sp) + 3002bc0: 5422 lw s0,40(sp) + 3002bc2: 6145 addi sp,sp,48 + 3002bc4: 8082 ret + +03002bc6 : + 3002bc6: 7179 addi sp,sp,-48 + 3002bc8: d606 sw ra,44(sp) + 3002bca: d422 sw s0,40(sp) + 3002bcc: 1800 addi s0,sp,48 + 3002bce: fca42e23 sw a0,-36(s0) + 3002bd2: fdc42783 lw a5,-36(s0) + 3002bd6: eb89 bnez a5,3002be8 + 3002bd8: 36500593 li a1,869 + 3002bdc: 030097b7 lui a5,0x3009 + 3002be0: 96c78513 addi a0,a5,-1684 # 300896c + 3002be4: 2c55 jal ra,3002e98 + 3002be6: a001 j 3002be6 + 3002be8: 040007b7 lui a5,0x4000 + 3002bec: 4947a783 lw a5,1172(a5) # 4000494 + 3002bf0: eb89 bnez a5,3002c02 + 3002bf2: 36600593 li a1,870 + 3002bf6: 030097b7 lui a5,0x3009 + 3002bfa: 96c78513 addi a0,a5,-1684 # 300896c + 3002bfe: 2c69 jal ra,3002e98 + 3002c00: a001 j 3002c00 + 3002c02: 040007b7 lui a5,0x4000 + 3002c06: 4947a783 lw a5,1172(a5) # 4000494 + 3002c0a: fef42623 sw a5,-20(s0) + 3002c0e: fdc42783 lw a5,-36(s0) + 3002c12: 279e lhu a5,8(a5) + 3002c14: 873e mv a4,a5 + 3002c16: fec42783 lw a5,-20(s0) + 3002c1a: 97ba add a5,a5,a4 + 3002c1c: fef42423 sw a5,-24(s0) + 3002c20: fe842783 lw a5,-24(s0) + 3002c24: 439c lw a5,0(a5) + 3002c26: fef42223 sw a5,-28(s0) + 3002c2a: fe442783 lw a5,-28(s0) + 3002c2e: 9fa1 uxth a5 + 3002c30: 873e mv a4,a5 + 3002c32: fdc42783 lw a5,-36(s0) + 3002c36: 27bc lbu a5,10(a5) + 3002c38: 40f757b3 sra a5,a4,a5 + 3002c3c: 8b85 andi a5,a5,1 + 3002c3e: 00f037b3 snez a5,a5 + 3002c42: 9f81 uxtb a5 + 3002c44: 853e mv a0,a5 + 3002c46: 50b2 lw ra,44(sp) + 3002c48: 5422 lw s0,40(sp) + 3002c4a: 6145 addi sp,sp,48 + 3002c4c: 8082 ret + +03002c4e : + 3002c4e: 7179 addi sp,sp,-48 + 3002c50: d606 sw ra,44(sp) + 3002c52: d422 sw s0,40(sp) + 3002c54: 1800 addi s0,sp,48 + 3002c56: fca42e23 sw a0,-36(s0) + 3002c5a: fcb42c23 sw a1,-40(s0) + 3002c5e: fdc42783 lw a5,-36(s0) + 3002c62: eb89 bnez a5,3002c74 + 3002c64: 37900593 li a1,889 + 3002c68: 030097b7 lui a5,0x3009 + 3002c6c: 96c78513 addi a0,a5,-1684 # 300896c + 3002c70: 2425 jal ra,3002e98 + 3002c72: a001 j 3002c72 + 3002c74: 040007b7 lui a5,0x4000 + 3002c78: 4947a783 lw a5,1172(a5) # 4000494 + 3002c7c: eb89 bnez a5,3002c8e + 3002c7e: 37a00593 li a1,890 + 3002c82: 030097b7 lui a5,0x3009 + 3002c86: 96c78513 addi a0,a5,-1684 # 300896c + 3002c8a: 2439 jal ra,3002e98 + 3002c8c: a001 j 3002c8c + 3002c8e: 040007b7 lui a5,0x4000 + 3002c92: 4947a783 lw a5,1172(a5) # 4000494 + 3002c96: fef42623 sw a5,-20(s0) + 3002c9a: fdc42783 lw a5,-36(s0) + 3002c9e: 279e lhu a5,8(a5) + 3002ca0: 873e mv a4,a5 + 3002ca2: fec42783 lw a5,-20(s0) + 3002ca6: 97ba add a5,a5,a4 + 3002ca8: fef42423 sw a5,-24(s0) + 3002cac: fe842783 lw a5,-24(s0) + 3002cb0: 439c lw a5,0(a5) + 3002cb2: fef42223 sw a5,-28(s0) + 3002cb6: fd842783 lw a5,-40(s0) + 3002cba: 8b85 andi a5,a5,1 + 3002cbc: c3a9 beqz a5,3002cfe + 3002cbe: fe442783 lw a5,-28(s0) + 3002cc2: 83c1 srli a5,a5,0x10 + 3002cc4: 9fa1 uxth a5 + 3002cc6: 01079713 slli a4,a5,0x10 + 3002cca: 8741 srai a4,a4,0x10 + 3002ccc: fdc42783 lw a5,-36(s0) + 3002cd0: 27bc lbu a5,10(a5) + 3002cd2: 86be mv a3,a5 + 3002cd4: 4785 li a5,1 + 3002cd6: 00d797b3 sll a5,a5,a3 + 3002cda: 07c2 slli a5,a5,0x10 + 3002cdc: 87c1 srai a5,a5,0x10 + 3002cde: 8fd9 or a5,a5,a4 + 3002ce0: 07c2 slli a5,a5,0x10 + 3002ce2: 87c1 srai a5,a5,0x10 + 3002ce4: 01079713 slli a4,a5,0x10 + 3002ce8: 8341 srli a4,a4,0x10 + 3002cea: fe442783 lw a5,-28(s0) + 3002cee: 0742 slli a4,a4,0x10 + 3002cf0: 66c1 lui a3,0x10 + 3002cf2: 16fd addi a3,a3,-1 # ffff + 3002cf4: 8ff5 and a5,a5,a3 + 3002cf6: 8fd9 or a5,a5,a4 + 3002cf8: fef42223 sw a5,-28(s0) + 3002cfc: a0a1 j 3002d44 + 3002cfe: fe442783 lw a5,-28(s0) + 3002d02: 83c1 srli a5,a5,0x10 + 3002d04: 9fa1 uxth a5 + 3002d06: 01079713 slli a4,a5,0x10 + 3002d0a: 8741 srai a4,a4,0x10 + 3002d0c: fdc42783 lw a5,-36(s0) + 3002d10: 27bc lbu a5,10(a5) + 3002d12: 86be mv a3,a5 + 3002d14: 4785 li a5,1 + 3002d16: 00d797b3 sll a5,a5,a3 + 3002d1a: 07c2 slli a5,a5,0x10 + 3002d1c: 87c1 srai a5,a5,0x10 + 3002d1e: fff7c793 not a5,a5 + 3002d22: 07c2 slli a5,a5,0x10 + 3002d24: 87c1 srai a5,a5,0x10 + 3002d26: 8ff9 and a5,a5,a4 + 3002d28: 07c2 slli a5,a5,0x10 + 3002d2a: 87c1 srai a5,a5,0x10 + 3002d2c: 01079713 slli a4,a5,0x10 + 3002d30: 8341 srli a4,a4,0x10 + 3002d32: fe442783 lw a5,-28(s0) + 3002d36: 0742 slli a4,a4,0x10 + 3002d38: 66c1 lui a3,0x10 + 3002d3a: 16fd addi a3,a3,-1 # ffff + 3002d3c: 8ff5 and a5,a5,a3 + 3002d3e: 8fd9 or a5,a5,a4 + 3002d40: fef42223 sw a5,-28(s0) + 3002d44: fe442703 lw a4,-28(s0) + 3002d48: fe842783 lw a5,-24(s0) + 3002d4c: c398 sw a4,0(a5) + 3002d4e: 0001 nop + 3002d50: 50b2 lw ra,44(sp) + 3002d52: 5422 lw s0,40(sp) + 3002d54: 6145 addi sp,sp,48 + 3002d56: 8082 ret + +03002d58 : + 3002d58: 7179 addi sp,sp,-48 + 3002d5a: d606 sw ra,44(sp) + 3002d5c: d422 sw s0,40(sp) + 3002d5e: 1800 addi s0,sp,48 + 3002d60: fca42e23 sw a0,-36(s0) + 3002d64: fdc42783 lw a5,-36(s0) + 3002d68: eb89 bnez a5,3002d7a + 3002d6a: 38f00593 li a1,911 + 3002d6e: 030097b7 lui a5,0x3009 + 3002d72: 96c78513 addi a0,a5,-1684 # 300896c + 3002d76: 220d jal ra,3002e98 + 3002d78: a001 j 3002d78 + 3002d7a: 040007b7 lui a5,0x4000 + 3002d7e: 4947a783 lw a5,1172(a5) # 4000494 + 3002d82: eb89 bnez a5,3002d94 + 3002d84: 39000593 li a1,912 + 3002d88: 030097b7 lui a5,0x3009 + 3002d8c: 96c78513 addi a0,a5,-1684 # 300896c + 3002d90: 2221 jal ra,3002e98 + 3002d92: a001 j 3002d92 + 3002d94: 040007b7 lui a5,0x4000 + 3002d98: 4947a783 lw a5,1172(a5) # 4000494 + 3002d9c: fef42623 sw a5,-20(s0) + 3002da0: fdc42783 lw a5,-36(s0) + 3002da4: 279e lhu a5,8(a5) + 3002da6: 873e mv a4,a5 + 3002da8: fec42783 lw a5,-20(s0) + 3002dac: 97ba add a5,a5,a4 + 3002dae: fef42423 sw a5,-24(s0) + 3002db2: fe842783 lw a5,-24(s0) + 3002db6: 439c lw a5,0(a5) + 3002db8: fef42223 sw a5,-28(s0) + 3002dbc: fe442783 lw a5,-28(s0) + 3002dc0: 83c1 srli a5,a5,0x10 + 3002dc2: 9fa1 uxth a5 + 3002dc4: 873e mv a4,a5 + 3002dc6: fdc42783 lw a5,-36(s0) + 3002dca: 27bc lbu a5,10(a5) + 3002dcc: 40f757b3 sra a5,a4,a5 + 3002dd0: 8b85 andi a5,a5,1 + 3002dd2: 00f037b3 snez a5,a5 + 3002dd6: 9f81 uxtb a5 + 3002dd8: 853e mv a0,a5 + 3002dda: 50b2 lw ra,44(sp) + 3002ddc: 5422 lw s0,40(sp) + 3002dde: 6145 addi sp,sp,48 + 3002de0: 8082 ret + +03002de2 : + 3002de2: 7179 addi sp,sp,-48 + 3002de4: d606 sw ra,44(sp) + 3002de6: d422 sw s0,40(sp) + 3002de8: 1800 addi s0,sp,48 + 3002dea: fca42e23 sw a0,-36(s0) + 3002dee: fcb42c23 sw a1,-40(s0) + 3002df2: fdc42783 lw a5,-36(s0) + 3002df6: eb89 bnez a5,3002e08 + 3002df8: 3a200593 li a1,930 + 3002dfc: 030097b7 lui a5,0x3009 + 3002e00: 96c78513 addi a0,a5,-1684 # 300896c + 3002e04: 2851 jal ra,3002e98 + 3002e06: a001 j 3002e06 + 3002e08: 040007b7 lui a5,0x4000 + 3002e0c: 4947a783 lw a5,1172(a5) # 4000494 + 3002e10: eb89 bnez a5,3002e22 + 3002e12: 3a300593 li a1,931 + 3002e16: 030097b7 lui a5,0x3009 + 3002e1a: 96c78513 addi a0,a5,-1684 # 300896c + 3002e1e: 28ad jal ra,3002e98 + 3002e20: a001 j 3002e20 + 3002e22: 040007b7 lui a5,0x4000 + 3002e26: 4947a783 lw a5,1172(a5) # 4000494 + 3002e2a: fef42623 sw a5,-20(s0) + 3002e2e: fdc42783 lw a5,-36(s0) + 3002e32: 279e lhu a5,8(a5) + 3002e34: 873e mv a4,a5 + 3002e36: fec42783 lw a5,-20(s0) + 3002e3a: 97ba add a5,a5,a4 + 3002e3c: fef42423 sw a5,-24(s0) + 3002e40: fe842783 lw a5,-24(s0) + 3002e44: 43dc lw a5,4(a5) + 3002e46: fef42223 sw a5,-28(s0) + 3002e4a: fd842783 lw a5,-40(s0) + 3002e4e: cf99 beqz a5,3002e6c + 3002e50: fe442783 lw a5,-28(s0) + 3002e54: 0017e793 ori a5,a5,1 + 3002e58: fef42223 sw a5,-28(s0) + 3002e5c: fe442783 lw a5,-28(s0) + 3002e60: 7741 lui a4,0xffff0 + 3002e62: 177d addi a4,a4,-1 # fffeffff + 3002e64: 8ff9 and a5,a5,a4 + 3002e66: fef42223 sw a5,-28(s0) + 3002e6a: a829 j 3002e84 + 3002e6c: fe442783 lw a5,-28(s0) + 3002e70: 9bf9 andi a5,a5,-2 + 3002e72: fef42223 sw a5,-28(s0) + 3002e76: fe442783 lw a5,-28(s0) + 3002e7a: 7741 lui a4,0xffff0 + 3002e7c: 177d addi a4,a4,-1 # fffeffff + 3002e7e: 8ff9 and a5,a5,a4 + 3002e80: fef42223 sw a5,-28(s0) + 3002e84: fe442703 lw a4,-28(s0) + 3002e88: fe842783 lw a5,-24(s0) + 3002e8c: c3d8 sw a4,4(a5) + 3002e8e: 0001 nop + 3002e90: 50b2 lw ra,44(sp) + 3002e92: 5422 lw s0,40(sp) + 3002e94: 6145 addi sp,sp,48 + 3002e96: 8082 ret + +03002e98 : + 3002e98: b70fe06f j 3001208 + +03002e9c : + 3002e9c: 7179 addi sp,sp,-48 + 3002e9e: d606 sw ra,44(sp) + 3002ea0: d422 sw s0,40(sp) + 3002ea2: 1800 addi s0,sp,48 + 3002ea4: fca42e23 sw a0,-36(s0) + 3002ea8: fdc42783 lw a5,-36(s0) + 3002eac: eb89 bnez a5,3002ebe + 3002eae: 3ba00593 li a1,954 + 3002eb2: 030097b7 lui a5,0x3009 + 3002eb6: 96c78513 addi a0,a5,-1684 # 300896c + 3002eba: 3ff9 jal ra,3002e98 + 3002ebc: a001 j 3002ebc + 3002ebe: 040007b7 lui a5,0x4000 + 3002ec2: 4947a783 lw a5,1172(a5) # 4000494 + 3002ec6: eb89 bnez a5,3002ed8 + 3002ec8: 3bb00593 li a1,955 + 3002ecc: 030097b7 lui a5,0x3009 + 3002ed0: 96c78513 addi a0,a5,-1684 # 300896c + 3002ed4: 37d1 jal ra,3002e98 + 3002ed6: a001 j 3002ed6 + 3002ed8: 040007b7 lui a5,0x4000 + 3002edc: 4947a783 lw a5,1172(a5) # 4000494 + 3002ee0: fef42623 sw a5,-20(s0) + 3002ee4: fdc42783 lw a5,-36(s0) + 3002ee8: 279e lhu a5,8(a5) + 3002eea: 873e mv a4,a5 + 3002eec: fec42783 lw a5,-20(s0) + 3002ef0: 97ba add a5,a5,a4 + 3002ef2: fef42423 sw a5,-24(s0) + 3002ef6: fe842783 lw a5,-24(s0) + 3002efa: 43dc lw a5,4(a5) + 3002efc: 8b85 andi a5,a5,1 + 3002efe: 9f81 uxtb a5 + 3002f00: c399 beqz a5,3002f06 + 3002f02: 4785 li a5,1 + 3002f04: a011 j 3002f08 + 3002f06: 4781 li a5,0 + 3002f08: fef42223 sw a5,-28(s0) + 3002f0c: fe442783 lw a5,-28(s0) + 3002f10: 853e mv a0,a5 + 3002f12: 50b2 lw ra,44(sp) + 3002f14: 5422 lw s0,40(sp) + 3002f16: 6145 addi sp,sp,48 + 3002f18: 8082 ret + +03002f1a : + 3002f1a: 7179 addi sp,sp,-48 + 3002f1c: d606 sw ra,44(sp) + 3002f1e: d422 sw s0,40(sp) + 3002f20: 1800 addi s0,sp,48 + 3002f22: fca42e23 sw a0,-36(s0) + 3002f26: fcb42c23 sw a1,-40(s0) + 3002f2a: fdc42783 lw a5,-36(s0) + 3002f2e: eb89 bnez a5,3002f40 + 3002f30: 3cc00593 li a1,972 + 3002f34: 030097b7 lui a5,0x3009 + 3002f38: 96c78513 addi a0,a5,-1684 # 300896c + 3002f3c: 3fb1 jal ra,3002e98 + 3002f3e: a001 j 3002f3e + 3002f40: 040007b7 lui a5,0x4000 + 3002f44: 4947a783 lw a5,1172(a5) # 4000494 + 3002f48: eb89 bnez a5,3002f5a + 3002f4a: 3cd00593 li a1,973 + 3002f4e: 030097b7 lui a5,0x3009 + 3002f52: 96c78513 addi a0,a5,-1684 # 300896c + 3002f56: 3789 jal ra,3002e98 + 3002f58: a001 j 3002f58 + 3002f5a: 040007b7 lui a5,0x4000 + 3002f5e: 4947a703 lw a4,1172(a5) # 4000494 + 3002f62: 100007b7 lui a5,0x10000 + 3002f66: 00f70a63 beq a4,a5,3002f7a + 3002f6a: 3ce00593 li a1,974 + 3002f6e: 030097b7 lui a5,0x3009 + 3002f72: 96c78513 addi a0,a5,-1684 # 300896c + 3002f76: 370d jal ra,3002e98 + 3002f78: a001 j 3002f78 + 3002f7a: fd842503 lw a0,-40(s0) + 3002f7e: 810ff0ef jal ra,3001f8e + 3002f82: 87aa mv a5,a0 + 3002f84: 0017c793 xori a5,a5,1 + 3002f88: 9f81 uxtb a5 + 3002f8a: cb89 beqz a5,3002f9c + 3002f8c: 3cf00593 li a1,975 + 3002f90: 030097b7 lui a5,0x3009 + 3002f94: 96c78513 addi a0,a5,-1684 # 300896c + 3002f98: 3701 jal ra,3002e98 + 3002f9a: a89d j 3003010 + 3002f9c: 040007b7 lui a5,0x4000 + 3002fa0: 4947a783 lw a5,1172(a5) # 4000494 + 3002fa4: fef42623 sw a5,-20(s0) + 3002fa8: fdc42783 lw a5,-36(s0) + 3002fac: 279e lhu a5,8(a5) + 3002fae: 873e mv a4,a5 + 3002fb0: fec42783 lw a5,-20(s0) + 3002fb4: 97ba add a5,a5,a4 + 3002fb6: fef42423 sw a5,-24(s0) + 3002fba: fd842703 lw a4,-40(s0) + 3002fbe: 478d li a5,3 + 3002fc0: 00f71a63 bne a4,a5,3002fd4 + 3002fc4: fe842703 lw a4,-24(s0) + 3002fc8: 435c lw a5,4(a4) + 3002fca: 010006b7 lui a3,0x1000 + 3002fce: 8fd5 or a5,a5,a3 + 3002fd0: c35c sw a5,4(a4) + 3002fd2: a83d j 3003010 + 3002fd4: cd7fe0ef jal ra,3001caa + 3002fd8: 040007b7 lui a5,0x4000 + 3002fdc: 4947a703 lw a4,1172(a5) # 4000494 + 3002fe0: fd842783 lw a5,-40(s0) + 3002fe4: 8b8d andi a5,a5,3 + 3002fe6: 0ff7f693 andi a3,a5,255 + 3002fea: 10072783 lw a5,256(a4) + 3002fee: 8a8d andi a3,a3,3 + 3002ff0: 0692 slli a3,a3,0x4 + 3002ff2: fcf7f793 andi a5,a5,-49 + 3002ff6: 8fd5 or a5,a5,a3 + 3002ff8: 10f72023 sw a5,256(a4) + 3002ffc: cd7fe0ef jal ra,3001cd2 + 3003000: fe842703 lw a4,-24(s0) + 3003004: 435c lw a5,4(a4) + 3003006: ff0006b7 lui a3,0xff000 + 300300a: 16fd addi a3,a3,-1 # feffffff + 300300c: 8ff5 and a5,a5,a3 + 300300e: c35c sw a5,4(a4) + 3003010: 50b2 lw ra,44(sp) + 3003012: 5422 lw s0,40(sp) + 3003014: 6145 addi sp,sp,48 + 3003016: 8082 ret + +03003018 : + 3003018: 7179 addi sp,sp,-48 + 300301a: d606 sw ra,44(sp) + 300301c: d422 sw s0,40(sp) + 300301e: 1800 addi s0,sp,48 + 3003020: fca42e23 sw a0,-36(s0) + 3003024: fdc42783 lw a5,-36(s0) + 3003028: eb89 bnez a5,300303a + 300302a: 3e400593 li a1,996 + 300302e: 030097b7 lui a5,0x3009 + 3003032: 96c78513 addi a0,a5,-1684 # 300896c + 3003036: 358d jal ra,3002e98 + 3003038: a001 j 3003038 + 300303a: 040007b7 lui a5,0x4000 + 300303e: 4947a783 lw a5,1172(a5) # 4000494 + 3003042: eb89 bnez a5,3003054 + 3003044: 3e500593 li a1,997 + 3003048: 030097b7 lui a5,0x3009 + 300304c: 96c78513 addi a0,a5,-1684 # 300896c + 3003050: 35a1 jal ra,3002e98 + 3003052: a001 j 3003052 + 3003054: 040007b7 lui a5,0x4000 + 3003058: 4947a783 lw a5,1172(a5) # 4000494 + 300305c: fef42623 sw a5,-20(s0) + 3003060: fdc42783 lw a5,-36(s0) + 3003064: 279e lhu a5,8(a5) + 3003066: 873e mv a4,a5 + 3003068: fec42783 lw a5,-20(s0) + 300306c: 97ba add a5,a5,a4 + 300306e: fef42423 sw a5,-24(s0) + 3003072: fe842783 lw a5,-24(s0) + 3003076: 43dc lw a5,4(a5) + 3003078: 83e1 srli a5,a5,0x18 + 300307a: 8b85 andi a5,a5,1 + 300307c: 0ff7f713 andi a4,a5,255 + 3003080: 4785 li a5,1 + 3003082: 00f71463 bne a4,a5,300308a + 3003086: 478d li a5,3 + 3003088: a811 j 300309c + 300308a: 040007b7 lui a5,0x4000 + 300308e: 4947a783 lw a5,1172(a5) # 4000494 + 3003092: 1007a783 lw a5,256(a5) + 3003096: 8391 srli a5,a5,0x4 + 3003098: 8b8d andi a5,a5,3 + 300309a: 9f81 uxtb a5 + 300309c: 853e mv a0,a5 + 300309e: 50b2 lw ra,44(sp) + 30030a0: 5422 lw s0,40(sp) + 30030a2: 6145 addi sp,sp,48 + 30030a4: 8082 ret + +030030a6 : + 30030a6: 7179 addi sp,sp,-48 + 30030a8: d606 sw ra,44(sp) + 30030aa: d422 sw s0,40(sp) + 30030ac: 1800 addi s0,sp,48 + 30030ae: fca42e23 sw a0,-36(s0) + 30030b2: fcb42c23 sw a1,-40(s0) + 30030b6: fdc42783 lw a5,-36(s0) + 30030ba: eb89 bnez a5,30030cc + 30030bc: 3f700593 li a1,1015 + 30030c0: 030097b7 lui a5,0x3009 + 30030c4: 96c78513 addi a0,a5,-1684 # 300896c + 30030c8: 3bc1 jal ra,3002e98 + 30030ca: a001 j 30030ca + 30030cc: 040007b7 lui a5,0x4000 + 30030d0: 4947a783 lw a5,1172(a5) # 4000494 + 30030d4: eb89 bnez a5,30030e6 + 30030d6: 3f800593 li a1,1016 + 30030da: 030097b7 lui a5,0x3009 + 30030de: 96c78513 addi a0,a5,-1684 # 300896c + 30030e2: 3b5d jal ra,3002e98 + 30030e4: a001 j 30030e4 + 30030e6: fd842503 lw a0,-40(s0) + 30030ea: ee5fe0ef jal ra,3001fce + 30030ee: 87aa mv a5,a0 + 30030f0: 0017c793 xori a5,a5,1 + 30030f4: 9f81 uxtb a5 + 30030f6: cb89 beqz a5,3003108 + 30030f8: 3f900593 li a1,1017 + 30030fc: 030097b7 lui a5,0x3009 + 3003100: 96c78513 addi a0,a5,-1684 # 300896c + 3003104: 3b51 jal ra,3002e98 + 3003106: a885 j 3003176 + 3003108: 040007b7 lui a5,0x4000 + 300310c: 4947a783 lw a5,1172(a5) # 4000494 + 3003110: fef42623 sw a5,-20(s0) + 3003114: fdc42783 lw a5,-36(s0) + 3003118: 279e lhu a5,8(a5) + 300311a: 873e mv a4,a5 + 300311c: fec42783 lw a5,-20(s0) + 3003120: 97ba add a5,a5,a4 + 3003122: fef42423 sw a5,-24(s0) + 3003126: fe842783 lw a5,-24(s0) + 300312a: 43dc lw a5,4(a5) + 300312c: 83e1 srli a5,a5,0x18 + 300312e: 8b85 andi a5,a5,1 + 3003130: 9f81 uxtb a5 + 3003132: fef42223 sw a5,-28(s0) + 3003136: fe442703 lw a4,-28(s0) + 300313a: 4785 li a5,1 + 300313c: 02f71163 bne a4,a5,300315e + 3003140: fd842783 lw a5,-40(s0) + 3003144: 8b8d andi a5,a5,3 + 3003146: 0ff7f693 andi a3,a5,255 + 300314a: fe842703 lw a4,-24(s0) + 300314e: 431c lw a5,0(a4) + 3003150: 8a8d andi a3,a3,3 + 3003152: 06a2 slli a3,a3,0x8 + 3003154: cff7f793 andi a5,a5,-769 + 3003158: 8fd5 or a5,a5,a3 + 300315a: c31c sw a5,0(a4) + 300315c: a829 j 3003176 + 300315e: fd842783 lw a5,-40(s0) + 3003162: 8b8d andi a5,a5,3 + 3003164: 0ff7f693 andi a3,a5,255 + 3003168: fe842703 lw a4,-24(s0) + 300316c: 431c lw a5,0(a4) + 300316e: 8a8d andi a3,a3,3 + 3003170: 9bf1 andi a5,a5,-4 + 3003172: 8fd5 or a5,a5,a3 + 3003174: c31c sw a5,0(a4) + 3003176: 50b2 lw ra,44(sp) + 3003178: 5422 lw s0,40(sp) + 300317a: 6145 addi sp,sp,48 + 300317c: 8082 ret + +0300317e : + 300317e: 7179 addi sp,sp,-48 + 3003180: d606 sw ra,44(sp) + 3003182: d422 sw s0,40(sp) + 3003184: 1800 addi s0,sp,48 + 3003186: fca42e23 sw a0,-36(s0) + 300318a: fdc42783 lw a5,-36(s0) + 300318e: eb89 bnez a5,30031a0 + 3003190: 40c00593 li a1,1036 + 3003194: 030097b7 lui a5,0x3009 + 3003198: 96c78513 addi a0,a5,-1684 # 300896c + 300319c: 39f5 jal ra,3002e98 + 300319e: a001 j 300319e + 30031a0: 040007b7 lui a5,0x4000 + 30031a4: 4947a783 lw a5,1172(a5) # 4000494 + 30031a8: eb89 bnez a5,30031ba + 30031aa: 40d00593 li a1,1037 + 30031ae: 030097b7 lui a5,0x3009 + 30031b2: 96c78513 addi a0,a5,-1684 # 300896c + 30031b6: 31cd jal ra,3002e98 + 30031b8: a001 j 30031b8 + 30031ba: 040007b7 lui a5,0x4000 + 30031be: 4947a783 lw a5,1172(a5) # 4000494 + 30031c2: fef42623 sw a5,-20(s0) + 30031c6: fdc42783 lw a5,-36(s0) + 30031ca: 279e lhu a5,8(a5) + 30031cc: 873e mv a4,a5 + 30031ce: fec42783 lw a5,-20(s0) + 30031d2: 97ba add a5,a5,a4 + 30031d4: fef42423 sw a5,-24(s0) + 30031d8: fe842783 lw a5,-24(s0) + 30031dc: 43dc lw a5,4(a5) + 30031de: 83e1 srli a5,a5,0x18 + 30031e0: 8b85 andi a5,a5,1 + 30031e2: 9f81 uxtb a5 + 30031e4: fef42223 sw a5,-28(s0) + 30031e8: fe442703 lw a4,-28(s0) + 30031ec: 4785 li a5,1 + 30031ee: 00f71963 bne a4,a5,3003200 + 30031f2: fe842783 lw a5,-24(s0) + 30031f6: 439c lw a5,0(a5) + 30031f8: 83a1 srli a5,a5,0x8 + 30031fa: 8b8d andi a5,a5,3 + 30031fc: 9f81 uxtb a5 + 30031fe: a031 j 300320a + 3003200: fe842783 lw a5,-24(s0) + 3003204: 439c lw a5,0(a5) + 3003206: 8b8d andi a5,a5,3 + 3003208: 9f81 uxtb a5 + 300320a: 853e mv a0,a5 + 300320c: 50b2 lw ra,44(sp) + 300320e: 5422 lw s0,40(sp) + 3003210: 6145 addi sp,sp,48 + 3003212: 8082 ret + +03003214 : + 3003214: 7179 addi sp,sp,-48 + 3003216: d606 sw ra,44(sp) + 3003218: d422 sw s0,40(sp) + 300321a: 1800 addi s0,sp,48 + 300321c: fca42e23 sw a0,-36(s0) + 3003220: fcb42c23 sw a1,-40(s0) + 3003224: fdc42783 lw a5,-36(s0) + 3003228: eb89 bnez a5,300323a + 300322a: 42100593 li a1,1057 + 300322e: 030097b7 lui a5,0x3009 + 3003232: 96c78513 addi a0,a5,-1684 # 300896c + 3003236: 318d jal ra,3002e98 + 3003238: a001 j 3003238 + 300323a: 040007b7 lui a5,0x4000 + 300323e: 4947a783 lw a5,1172(a5) # 4000494 + 3003242: eb89 bnez a5,3003254 + 3003244: 42200593 li a1,1058 + 3003248: 030097b7 lui a5,0x3009 + 300324c: 96c78513 addi a0,a5,-1684 # 300896c + 3003250: 31a1 jal ra,3002e98 + 3003252: a001 j 3003252 + 3003254: 040007b7 lui a5,0x4000 + 3003258: 4947a783 lw a5,1172(a5) # 4000494 + 300325c: fef42623 sw a5,-20(s0) + 3003260: fdc42783 lw a5,-36(s0) + 3003264: 279e lhu a5,8(a5) + 3003266: 873e mv a4,a5 + 3003268: fec42783 lw a5,-20(s0) + 300326c: 97ba add a5,a5,a4 + 300326e: fef42423 sw a5,-24(s0) + 3003272: fd842783 lw a5,-40(s0) + 3003276: 8b85 andi a5,a5,1 + 3003278: 0ff7f693 andi a3,a5,255 + 300327c: fe842703 lw a4,-24(s0) + 3003280: 431c lw a5,0(a4) + 3003282: 8a85 andi a3,a3,1 + 3003284: 9bf9 andi a5,a5,-2 + 3003286: 8fd5 or a5,a5,a3 + 3003288: c31c sw a5,0(a4) + 300328a: 0001 nop + 300328c: 50b2 lw ra,44(sp) + 300328e: 5422 lw s0,40(sp) + 3003290: 6145 addi sp,sp,48 + 3003292: 8082 ret + +03003294 : + 3003294: 7179 addi sp,sp,-48 + 3003296: d606 sw ra,44(sp) + 3003298: d422 sw s0,40(sp) + 300329a: 1800 addi s0,sp,48 + 300329c: fca42e23 sw a0,-36(s0) + 30032a0: fdc42783 lw a5,-36(s0) + 30032a4: eb89 bnez a5,30032b6 + 30032a6: 43000593 li a1,1072 + 30032aa: 030097b7 lui a5,0x3009 + 30032ae: 96c78513 addi a0,a5,-1684 # 300896c + 30032b2: 36dd jal ra,3002e98 + 30032b4: a001 j 30032b4 + 30032b6: 040007b7 lui a5,0x4000 + 30032ba: 4947a783 lw a5,1172(a5) # 4000494 + 30032be: eb89 bnez a5,30032d0 + 30032c0: 43100593 li a1,1073 + 30032c4: 030097b7 lui a5,0x3009 + 30032c8: 96c78513 addi a0,a5,-1684 # 300896c + 30032cc: 36f1 jal ra,3002e98 + 30032ce: a001 j 30032ce + 30032d0: 040007b7 lui a5,0x4000 + 30032d4: 4947a783 lw a5,1172(a5) # 4000494 + 30032d8: fef42623 sw a5,-20(s0) + 30032dc: fdc42783 lw a5,-36(s0) + 30032e0: 279e lhu a5,8(a5) + 30032e2: 873e mv a4,a5 + 30032e4: fec42783 lw a5,-20(s0) + 30032e8: 97ba add a5,a5,a4 + 30032ea: fef42423 sw a5,-24(s0) + 30032ee: fe842783 lw a5,-24(s0) + 30032f2: 439c lw a5,0(a5) + 30032f4: 8b85 andi a5,a5,1 + 30032f6: 9f81 uxtb a5 + 30032f8: 853e mv a0,a5 + 30032fa: 50b2 lw ra,44(sp) + 30032fc: 5422 lw s0,40(sp) + 30032fe: 6145 addi sp,sp,48 + 3003300: 8082 ret + +03003302 : + 3003302: 7179 addi sp,sp,-48 + 3003304: d606 sw ra,44(sp) + 3003306: d422 sw s0,40(sp) + 3003308: 1800 addi s0,sp,48 + 300330a: fca42e23 sw a0,-36(s0) + 300330e: fcb42c23 sw a1,-40(s0) + 3003312: fdc42783 lw a5,-36(s0) + 3003316: eb89 bnez a5,3003328 + 3003318: 44000593 li a1,1088 + 300331c: 030097b7 lui a5,0x3009 + 3003320: 96c78513 addi a0,a5,-1684 # 300896c + 3003324: 3e95 jal ra,3002e98 + 3003326: a001 j 3003326 + 3003328: 040007b7 lui a5,0x4000 + 300332c: 4947a783 lw a5,1172(a5) # 4000494 + 3003330: eb89 bnez a5,3003342 + 3003332: 44100593 li a1,1089 + 3003336: 030097b7 lui a5,0x3009 + 300333a: 96c78513 addi a0,a5,-1684 # 300896c + 300333e: 3ea9 jal ra,3002e98 + 3003340: a001 j 3003340 + 3003342: fd842703 lw a4,-40(s0) + 3003346: 4785 li a5,1 + 3003348: 00f70d63 beq a4,a5,3003362 + 300334c: fd842783 lw a5,-40(s0) + 3003350: cb89 beqz a5,3003362 + 3003352: 44200593 li a1,1090 + 3003356: 030097b7 lui a5,0x3009 + 300335a: 96c78513 addi a0,a5,-1684 # 300896c + 300335e: 3e2d jal ra,3002e98 + 3003360: a20d j 3003482 + 3003362: 040007b7 lui a5,0x4000 + 3003366: 4947a783 lw a5,1172(a5) # 4000494 + 300336a: fef42623 sw a5,-20(s0) + 300336e: fdc42783 lw a5,-36(s0) + 3003372: 279e lhu a5,8(a5) + 3003374: 873e mv a4,a5 + 3003376: fec42783 lw a5,-20(s0) + 300337a: 97ba add a5,a5,a4 + 300337c: fdc42703 lw a4,-36(s0) + 3003380: 2738 lbu a4,10(a4) + 3003382: 97ba add a5,a5,a4 + 3003384: fef42423 sw a5,-24(s0) + 3003388: fd842703 lw a4,-40(s0) + 300338c: 4785 li a5,1 + 300338e: 02f71f63 bne a4,a5,30033cc + 3003392: fe842783 lw a5,-24(s0) + 3003396: 439c lw a5,0(a5) + 3003398: 83c1 srli a5,a5,0x10 + 300339a: 8b85 andi a5,a5,1 + 300339c: 0ff7f713 andi a4,a5,255 + 30033a0: 4785 li a5,1 + 30033a2: 02f71563 bne a4,a5,30033cc + 30033a6: fe842703 lw a4,-24(s0) + 30033aa: 431c lw a5,0(a4) + 30033ac: 76c1 lui a3,0xffff0 + 30033ae: 16fd addi a3,a3,-1 # fffeffff + 30033b0: 8ff5 and a5,a5,a3 + 30033b2: c31c sw a5,0(a4) + 30033b4: 040007b7 lui a5,0x4000 + 30033b8: 4987c783 lbu a5,1176(a5) # 4000498 + 30033bc: 0785 addi a5,a5,1 + 30033be: 0ff7f713 andi a4,a5,255 + 30033c2: 040007b7 lui a5,0x4000 + 30033c6: 48e78c23 sb a4,1176(a5) # 4000498 + 30033ca: a089 j 300340c + 30033cc: fd842783 lw a5,-40(s0) + 30033d0: ef95 bnez a5,300340c + 30033d2: fe842783 lw a5,-24(s0) + 30033d6: 439c lw a5,0(a5) + 30033d8: 83c1 srli a5,a5,0x10 + 30033da: 8b85 andi a5,a5,1 + 30033dc: 9f81 uxtb a5 + 30033de: e79d bnez a5,300340c + 30033e0: fe842703 lw a4,-24(s0) + 30033e4: 431c lw a5,0(a4) + 30033e6: 66c1 lui a3,0x10 + 30033e8: 8fd5 or a5,a5,a3 + 30033ea: c31c sw a5,0(a4) + 30033ec: 040007b7 lui a5,0x4000 + 30033f0: 4987c783 lbu a5,1176(a5) # 4000498 + 30033f4: cf81 beqz a5,300340c + 30033f6: 040007b7 lui a5,0x4000 + 30033fa: 4987c783 lbu a5,1176(a5) # 4000498 + 30033fe: 17fd addi a5,a5,-1 + 3003400: 0ff7f713 andi a4,a5,255 + 3003404: 040007b7 lui a5,0x4000 + 3003408: 48e78c23 sb a4,1176(a5) # 4000498 + 300340c: 040007b7 lui a5,0x4000 + 3003410: 4987c783 lbu a5,1176(a5) # 4000498 + 3003414: eb85 bnez a5,3003444 + 3003416: fd842783 lw a5,-40(s0) + 300341a: e78d bnez a5,3003444 + 300341c: 10000737 lui a4,0x10000 + 3003420: 6785 lui a5,0x1 + 3003422: 973e add a4,a4,a5 + 3003424: a5072783 lw a5,-1456(a4) # ffffa50 + 3003428: 9bf9 andi a5,a5,-2 + 300342a: a4f72823 sw a5,-1456(a4) + 300342e: 10000737 lui a4,0x10000 + 3003432: 6785 lui a5,0x1 + 3003434: 973e add a4,a4,a5 + 3003436: a5072783 lw a5,-1456(a4) # ffffa50 + 300343a: 66c1 lui a3,0x10 + 300343c: 8fd5 or a5,a5,a3 + 300343e: a4f72823 sw a5,-1456(a4) + 3003442: a081 j 3003482 + 3003444: 040007b7 lui a5,0x4000 + 3003448: 4987c783 lbu a5,1176(a5) # 4000498 + 300344c: cb9d beqz a5,3003482 + 300344e: fd842703 lw a4,-40(s0) + 3003452: 4785 li a5,1 + 3003454: 02f71763 bne a4,a5,3003482 + 3003458: 10000737 lui a4,0x10000 + 300345c: 6785 lui a5,0x1 + 300345e: 973e add a4,a4,a5 + 3003460: a5072783 lw a5,-1456(a4) # ffffa50 + 3003464: 76c1 lui a3,0xffff0 + 3003466: 16fd addi a3,a3,-1 # fffeffff + 3003468: 8ff5 and a5,a5,a3 + 300346a: a4f72823 sw a5,-1456(a4) + 300346e: 10000737 lui a4,0x10000 + 3003472: 6785 lui a5,0x1 + 3003474: 973e add a4,a4,a5 + 3003476: a5072783 lw a5,-1456(a4) # ffffa50 + 300347a: 0017e793 ori a5,a5,1 + 300347e: a4f72823 sw a5,-1456(a4) + 3003482: 50b2 lw ra,44(sp) + 3003484: 5422 lw s0,40(sp) + 3003486: 6145 addi sp,sp,48 + 3003488: 8082 ret + +0300348a : + 300348a: 7179 addi sp,sp,-48 + 300348c: d606 sw ra,44(sp) + 300348e: d422 sw s0,40(sp) + 3003490: 1800 addi s0,sp,48 + 3003492: fca42e23 sw a0,-36(s0) + 3003496: fdc42783 lw a5,-36(s0) + 300349a: eb89 bnez a5,30034ac + 300349c: 46200593 li a1,1122 + 30034a0: 030097b7 lui a5,0x3009 + 30034a4: 96c78513 addi a0,a5,-1684 # 300896c + 30034a8: 3ac5 jal ra,3002e98 + 30034aa: a001 j 30034aa + 30034ac: 040007b7 lui a5,0x4000 + 30034b0: 4947a783 lw a5,1172(a5) # 4000494 + 30034b4: eb89 bnez a5,30034c6 + 30034b6: 46300593 li a1,1123 + 30034ba: 030097b7 lui a5,0x3009 + 30034be: 96c78513 addi a0,a5,-1684 # 300896c + 30034c2: 3ad9 jal ra,3002e98 + 30034c4: a001 j 30034c4 + 30034c6: 040007b7 lui a5,0x4000 + 30034ca: 4947a783 lw a5,1172(a5) # 4000494 + 30034ce: fef42623 sw a5,-20(s0) + 30034d2: fdc42783 lw a5,-36(s0) + 30034d6: 279e lhu a5,8(a5) + 30034d8: 873e mv a4,a5 + 30034da: fec42783 lw a5,-20(s0) + 30034de: 97ba add a5,a5,a4 + 30034e0: fdc42703 lw a4,-36(s0) + 30034e4: 2738 lbu a4,10(a4) + 30034e6: 97ba add a5,a5,a4 + 30034e8: fef42423 sw a5,-24(s0) + 30034ec: fe842783 lw a5,-24(s0) + 30034f0: 439c lw a5,0(a5) + 30034f2: 83c1 srli a5,a5,0x10 + 30034f4: 8b85 andi a5,a5,1 + 30034f6: 9f81 uxtb a5 + 30034f8: 0017c793 xori a5,a5,1 + 30034fc: 9f81 uxtb a5 + 30034fe: 853e mv a0,a5 + 3003500: 50b2 lw ra,44(sp) + 3003502: 5422 lw s0,40(sp) + 3003504: 6145 addi sp,sp,48 + 3003506: 8082 ret + +03003508 : + 3003508: 1101 addi sp,sp,-32 + 300350a: ce22 sw s0,28(sp) + 300350c: 1000 addi s0,sp,32 + 300350e: fea42623 sw a0,-20(s0) + 3003512: fec42783 lw a5,-20(s0) + 3003516: c791 beqz a5,3003522 + 3003518: fec42703 lw a4,-20(s0) + 300351c: 4785 li a5,1 + 300351e: 00f71463 bne a4,a5,3003526 + 3003522: 4785 li a5,1 + 3003524: a011 j 3003528 + 3003526: 4781 li a5,0 + 3003528: 8b85 andi a5,a5,1 + 300352a: 9f81 uxtb a5 + 300352c: 853e mv a0,a5 + 300352e: 4472 lw s0,28(sp) + 3003530: 6105 addi sp,sp,32 + 3003532: 8082 ret + +03003534 : + 3003534: 1101 addi sp,sp,-32 + 3003536: ce22 sw s0,28(sp) + 3003538: 1000 addi s0,sp,32 + 300353a: fea42623 sw a0,-20(s0) + 300353e: fec42783 lw a5,-20(s0) + 3003542: c791 beqz a5,300354e + 3003544: fec42703 lw a4,-20(s0) + 3003548: 4785 li a5,1 + 300354a: 00f71463 bne a4,a5,3003552 + 300354e: 4785 li a5,1 + 3003550: a011 j 3003554 + 3003552: 4781 li a5,0 + 3003554: 8b85 andi a5,a5,1 + 3003556: 9f81 uxtb a5 + 3003558: 853e mv a0,a5 + 300355a: 4472 lw s0,28(sp) + 300355c: 6105 addi sp,sp,32 + 300355e: 8082 ret + +03003560 : + 3003560: 1101 addi sp,sp,-32 + 3003562: ce22 sw s0,28(sp) + 3003564: 1000 addi s0,sp,32 + 3003566: fea42623 sw a0,-20(s0) + 300356a: fec42783 lw a5,-20(s0) + 300356e: 0ff7f793 andi a5,a5,255 + 3003572: cb81 beqz a5,3003582 + 3003574: fec42783 lw a5,-20(s0) + 3003578: f007f793 andi a5,a5,-256 + 300357c: e399 bnez a5,3003582 + 300357e: 4785 li a5,1 + 3003580: a011 j 3003584 + 3003582: 4781 li a5,0 + 3003584: 8b85 andi a5,a5,1 + 3003586: 9f81 uxtb a5 + 3003588: 853e mv a0,a5 + 300358a: 4472 lw s0,28(sp) + 300358c: 6105 addi sp,sp,32 + 300358e: 8082 ret + +03003590 : + 3003590: 1101 addi sp,sp,-32 + 3003592: ce22 sw s0,28(sp) + 3003594: 1000 addi s0,sp,32 + 3003596: fea42623 sw a0,-20(s0) + 300359a: fec42703 lw a4,-20(s0) + 300359e: 4785 li a5,1 + 30035a0: 04f70e63 beq a4,a5,30035fc + 30035a4: fec42703 lw a4,-20(s0) + 30035a8: 4789 li a5,2 + 30035aa: 04f70963 beq a4,a5,30035fc + 30035ae: fec42703 lw a4,-20(s0) + 30035b2: 4791 li a5,4 + 30035b4: 04f70463 beq a4,a5,30035fc + 30035b8: fec42703 lw a4,-20(s0) + 30035bc: 47a1 li a5,8 + 30035be: 02f70f63 beq a4,a5,30035fc + 30035c2: fec42703 lw a4,-20(s0) + 30035c6: 47c1 li a5,16 + 30035c8: 02f70a63 beq a4,a5,30035fc + 30035cc: fec42703 lw a4,-20(s0) + 30035d0: 02000793 li a5,32 + 30035d4: 02f70463 beq a4,a5,30035fc + 30035d8: fec42703 lw a4,-20(s0) + 30035dc: 04000793 li a5,64 + 30035e0: 00f70e63 beq a4,a5,30035fc + 30035e4: fec42703 lw a4,-20(s0) + 30035e8: 08000793 li a5,128 + 30035ec: 00f70863 beq a4,a5,30035fc + 30035f0: fec42703 lw a4,-20(s0) + 30035f4: 0ff00793 li a5,255 + 30035f8: 00f71463 bne a4,a5,3003600 + 30035fc: 4785 li a5,1 + 30035fe: a011 j 3003602 + 3003600: 4781 li a5,0 + 3003602: 8b85 andi a5,a5,1 + 3003604: 9f81 uxtb a5 + 3003606: 853e mv a0,a5 + 3003608: 4472 lw s0,28(sp) + 300360a: 6105 addi sp,sp,32 + 300360c: 8082 ret + +0300360e : + 300360e: 1101 addi sp,sp,-32 + 3003610: ce22 sw s0,28(sp) + 3003612: 1000 addi s0,sp,32 + 3003614: fea42623 sw a0,-20(s0) + 3003618: fec42703 lw a4,-20(s0) + 300361c: 478d li a5,3 + 300361e: 02f70963 beq a4,a5,3003650 + 3003622: fec42703 lw a4,-20(s0) + 3003626: 4789 li a5,2 + 3003628: 02f70463 beq a4,a5,3003650 + 300362c: fec42703 lw a4,-20(s0) + 3003630: 4785 li a5,1 + 3003632: 00f70f63 beq a4,a5,3003650 + 3003636: fec42783 lw a5,-20(s0) + 300363a: cb99 beqz a5,3003650 + 300363c: fec42703 lw a4,-20(s0) + 3003640: 4791 li a5,4 + 3003642: 00f70763 beq a4,a5,3003650 + 3003646: fec42703 lw a4,-20(s0) + 300364a: 4795 li a5,5 + 300364c: 00f71463 bne a4,a5,3003654 + 3003650: 4785 li a5,1 + 3003652: a011 j 3003656 + 3003654: 4781 li a5,0 + 3003656: 8b85 andi a5,a5,1 + 3003658: 9f81 uxtb a5 + 300365a: 853e mv a0,a5 + 300365c: 4472 lw s0,28(sp) + 300365e: 6105 addi sp,sp,32 + 3003660: 8082 ret + +03003662 : + 3003662: 1101 addi sp,sp,-32 + 3003664: ce06 sw ra,28(sp) + 3003666: cc22 sw s0,24(sp) + 3003668: 1000 addi s0,sp,32 + 300366a: fea42623 sw a0,-20(s0) + 300366e: feb42423 sw a1,-24(s0) + 3003672: fec42223 sw a2,-28(s0) + 3003676: fec42703 lw a4,-20(s0) + 300367a: 145007b7 lui a5,0x14500 + 300367e: 04f70863 beq a4,a5,30036ce + 3003682: fec42703 lw a4,-20(s0) + 3003686: 145017b7 lui a5,0x14501 + 300368a: 04f70263 beq a4,a5,30036ce + 300368e: fec42703 lw a4,-20(s0) + 3003692: 145027b7 lui a5,0x14502 + 3003696: 02f70c63 beq a4,a5,30036ce + 300369a: fec42703 lw a4,-20(s0) + 300369e: 145037b7 lui a5,0x14503 + 30036a2: 02f70663 beq a4,a5,30036ce + 30036a6: fec42703 lw a4,-20(s0) + 30036aa: 145047b7 lui a5,0x14504 + 30036ae: 02f70063 beq a4,a5,30036ce + 30036b2: fec42703 lw a4,-20(s0) + 30036b6: 145057b7 lui a5,0x14505 + 30036ba: 00f70a63 beq a4,a5,30036ce + 30036be: 18e00593 li a1,398 + 30036c2: 030097b7 lui a5,0x3009 + 30036c6: 9c078513 addi a0,a5,-1600 # 30089c0 + 30036ca: 2d51 jal ra,3003d5e + 30036cc: a001 j 30036cc + 30036ce: fe842503 lw a0,-24(s0) + 30036d2: 3579 jal ra,3003560 + 30036d4: 87aa mv a5,a0 + 30036d6: 0017c793 xori a5,a5,1 + 30036da: 9f81 uxtb a5 + 30036dc: cb89 beqz a5,30036ee + 30036de: 18f00593 li a1,399 + 30036e2: 030097b7 lui a5,0x3009 + 30036e6: 9c078513 addi a0,a5,-1600 # 30089c0 + 30036ea: 2d95 jal ra,3003d5e + 30036ec: a089 j 300372e + 30036ee: fe442503 lw a0,-28(s0) + 30036f2: 3d19 jal ra,3003508 + 30036f4: 87aa mv a5,a0 + 30036f6: 0017c793 xori a5,a5,1 + 30036fa: 9f81 uxtb a5 + 30036fc: cb89 beqz a5,300370e + 30036fe: 19000593 li a1,400 + 3003702: 030097b7 lui a5,0x3009 + 3003706: 9c078513 addi a0,a5,-1600 # 30089c0 + 300370a: 2d91 jal ra,3003d5e + 300370c: a00d j 300372e + 300370e: fe442703 lw a4,-28(s0) + 3003712: 4785 li a5,1 + 3003714: 00f71563 bne a4,a5,300371e + 3003718: fe842783 lw a5,-24(s0) + 300371c: a011 j 3003720 + 300371e: 4781 li a5,0 + 3003720: fec42683 lw a3,-20(s0) + 3003724: fe842703 lw a4,-24(s0) + 3003728: 070a slli a4,a4,0x2 + 300372a: 9736 add a4,a4,a3 + 300372c: c31c sw a5,0(a4) + 300372e: 40f2 lw ra,28(sp) + 3003730: 4462 lw s0,24(sp) + 3003732: 6105 addi sp,sp,32 + 3003734: 8082 ret + +03003736 : + 3003736: 1101 addi sp,sp,-32 + 3003738: ce06 sw ra,28(sp) + 300373a: cc22 sw s0,24(sp) + 300373c: 1000 addi s0,sp,32 + 300373e: fea42623 sw a0,-20(s0) + 3003742: feb42423 sw a1,-24(s0) + 3003746: fec42223 sw a2,-28(s0) + 300374a: fec42703 lw a4,-20(s0) + 300374e: 145007b7 lui a5,0x14500 + 3003752: 04f70863 beq a4,a5,30037a2 + 3003756: fec42703 lw a4,-20(s0) + 300375a: 145017b7 lui a5,0x14501 + 300375e: 04f70263 beq a4,a5,30037a2 + 3003762: fec42703 lw a4,-20(s0) + 3003766: 145027b7 lui a5,0x14502 + 300376a: 02f70c63 beq a4,a5,30037a2 + 300376e: fec42703 lw a4,-20(s0) + 3003772: 145037b7 lui a5,0x14503 + 3003776: 02f70663 beq a4,a5,30037a2 + 300377a: fec42703 lw a4,-20(s0) + 300377e: 145047b7 lui a5,0x14504 + 3003782: 02f70063 beq a4,a5,30037a2 + 3003786: fec42703 lw a4,-20(s0) + 300378a: 145057b7 lui a5,0x14505 + 300378e: 00f70a63 beq a4,a5,30037a2 + 3003792: 1b700593 li a1,439 + 3003796: 030097b7 lui a5,0x3009 + 300379a: 9c078513 addi a0,a5,-1600 # 30089c0 + 300379e: 23c1 jal ra,3003d5e + 30037a0: a001 j 30037a0 + 30037a2: fe842503 lw a0,-24(s0) + 30037a6: 3b6d jal ra,3003560 + 30037a8: 87aa mv a5,a0 + 30037aa: 0017c793 xori a5,a5,1 + 30037ae: 9f81 uxtb a5 + 30037b0: cb89 beqz a5,30037c2 + 30037b2: 1b800593 li a1,440 + 30037b6: 030097b7 lui a5,0x3009 + 30037ba: 9c078513 addi a0,a5,-1600 # 30089c0 + 30037be: 2345 jal ra,3003d5e + 30037c0: a095 j 3003824 + 30037c2: fe442503 lw a0,-28(s0) + 30037c6: 33bd jal ra,3003534 + 30037c8: 87aa mv a5,a0 + 30037ca: 0017c793 xori a5,a5,1 + 30037ce: 9f81 uxtb a5 + 30037d0: cb89 beqz a5,30037e2 + 30037d2: 1b900593 li a1,441 + 30037d6: 030097b7 lui a5,0x3009 + 30037da: 9c078513 addi a0,a5,-1600 # 30089c0 + 30037de: 2341 jal ra,3003d5e + 30037e0: a091 j 3003824 + 30037e2: fe442783 lw a5,-28(s0) + 30037e6: ef99 bnez a5,3003804 + 30037e8: fec42783 lw a5,-20(s0) + 30037ec: 4007a703 lw a4,1024(a5) + 30037f0: fe842783 lw a5,-24(s0) + 30037f4: fff7c793 not a5,a5 + 30037f8: 8f7d and a4,a4,a5 + 30037fa: fec42783 lw a5,-20(s0) + 30037fe: 40e7a023 sw a4,1024(a5) + 3003802: a00d j 3003824 + 3003804: fe442703 lw a4,-28(s0) + 3003808: 4785 li a5,1 + 300380a: 00f71d63 bne a4,a5,3003824 + 300380e: fec42783 lw a5,-20(s0) + 3003812: 4007a703 lw a4,1024(a5) + 3003816: fe842783 lw a5,-24(s0) + 300381a: 8f5d or a4,a4,a5 + 300381c: fec42783 lw a5,-20(s0) + 3003820: 40e7a023 sw a4,1024(a5) + 3003824: 40f2 lw ra,28(sp) + 3003826: 4462 lw s0,24(sp) + 3003828: 6105 addi sp,sp,32 + 300382a: 8082 ret + +0300382c : + 300382c: 1101 addi sp,sp,-32 + 300382e: ce06 sw ra,28(sp) + 3003830: cc22 sw s0,24(sp) + 3003832: 1000 addi s0,sp,32 + 3003834: fea42623 sw a0,-20(s0) + 3003838: feb42423 sw a1,-24(s0) + 300383c: fec42703 lw a4,-20(s0) + 3003840: 145007b7 lui a5,0x14500 + 3003844: 04f70863 beq a4,a5,3003894 + 3003848: fec42703 lw a4,-20(s0) + 300384c: 145017b7 lui a5,0x14501 + 3003850: 04f70263 beq a4,a5,3003894 + 3003854: fec42703 lw a4,-20(s0) + 3003858: 145027b7 lui a5,0x14502 + 300385c: 02f70c63 beq a4,a5,3003894 + 3003860: fec42703 lw a4,-20(s0) + 3003864: 145037b7 lui a5,0x14503 + 3003868: 02f70663 beq a4,a5,3003894 + 300386c: fec42703 lw a4,-20(s0) + 3003870: 145047b7 lui a5,0x14504 + 3003874: 02f70063 beq a4,a5,3003894 + 3003878: fec42703 lw a4,-20(s0) + 300387c: 145057b7 lui a5,0x14505 + 3003880: 00f70a63 beq a4,a5,3003894 + 3003884: 25c00593 li a1,604 + 3003888: 030097b7 lui a5,0x3009 + 300388c: 9c078513 addi a0,a5,-1600 # 30089c0 + 3003890: 21f9 jal ra,3003d5e + 3003892: a001 j 3003892 + 3003894: fe842503 lw a0,-24(s0) + 3003898: 31e1 jal ra,3003560 + 300389a: 87aa mv a5,a0 + 300389c: 0017c793 xori a5,a5,1 + 30038a0: 9f81 uxtb a5 + 30038a2: cb89 beqz a5,30038b4 + 30038a4: 25d00593 li a1,605 + 30038a8: 030097b7 lui a5,0x3009 + 30038ac: 9c078513 addi a0,a5,-1600 # 30089c0 + 30038b0: 217d jal ra,3003d5e + 30038b2: a821 j 30038ca + 30038b4: fec42783 lw a5,-20(s0) + 30038b8: 41c7a703 lw a4,1052(a5) + 30038bc: fe842783 lw a5,-24(s0) + 30038c0: 8f5d or a4,a4,a5 + 30038c2: fec42783 lw a5,-20(s0) + 30038c6: 40e7ae23 sw a4,1052(a5) + 30038ca: 40f2 lw ra,28(sp) + 30038cc: 4462 lw s0,24(sp) + 30038ce: 6105 addi sp,sp,32 + 30038d0: 8082 ret + +030038d2 : + 30038d2: 1101 addi sp,sp,-32 + 30038d4: ce06 sw ra,28(sp) + 30038d6: cc22 sw s0,24(sp) + 30038d8: 1000 addi s0,sp,32 + 30038da: fea42623 sw a0,-20(s0) + 30038de: feb42423 sw a1,-24(s0) + 30038e2: fec42703 lw a4,-20(s0) + 30038e6: 145007b7 lui a5,0x14500 + 30038ea: 04f70863 beq a4,a5,300393a + 30038ee: fec42703 lw a4,-20(s0) + 30038f2: 145017b7 lui a5,0x14501 + 30038f6: 04f70263 beq a4,a5,300393a + 30038fa: fec42703 lw a4,-20(s0) + 30038fe: 145027b7 lui a5,0x14502 + 3003902: 02f70c63 beq a4,a5,300393a + 3003906: fec42703 lw a4,-20(s0) + 300390a: 145037b7 lui a5,0x14503 + 300390e: 02f70663 beq a4,a5,300393a + 3003912: fec42703 lw a4,-20(s0) + 3003916: 145047b7 lui a5,0x14504 + 300391a: 02f70063 beq a4,a5,300393a + 300391e: fec42703 lw a4,-20(s0) + 3003922: 145057b7 lui a5,0x14505 + 3003926: 00f70a63 beq a4,a5,300393a + 300392a: 26900593 li a1,617 + 300392e: 030097b7 lui a5,0x3009 + 3003932: 9c078513 addi a0,a5,-1600 # 30089c0 + 3003936: 2125 jal ra,3003d5e + 3003938: a001 j 3003938 + 300393a: fe842503 lw a0,-24(s0) + 300393e: 310d jal ra,3003560 + 3003940: 87aa mv a5,a0 + 3003942: 0017c793 xori a5,a5,1 + 3003946: 9f81 uxtb a5 + 3003948: cb89 beqz a5,300395a + 300394a: 26a00593 li a1,618 + 300394e: 030097b7 lui a5,0x3009 + 3003952: 9c078513 addi a0,a5,-1600 # 30089c0 + 3003956: 2121 jal ra,3003d5e + 3003958: a00d j 300397a + 300395a: fe842583 lw a1,-24(s0) + 300395e: fec42503 lw a0,-20(s0) + 3003962: 35e9 jal ra,300382c + 3003964: fec42783 lw a5,-20(s0) + 3003968: 4107a703 lw a4,1040(a5) + 300396c: fe842783 lw a5,-24(s0) + 3003970: 8f5d or a4,a4,a5 + 3003972: fec42783 lw a5,-20(s0) + 3003976: 40e7a823 sw a4,1040(a5) + 300397a: 40f2 lw ra,28(sp) + 300397c: 4462 lw s0,24(sp) + 300397e: 6105 addi sp,sp,32 + 3003980: 8082 ret + +03003982 : + 3003982: 1101 addi sp,sp,-32 + 3003984: ce06 sw ra,28(sp) + 3003986: cc22 sw s0,24(sp) + 3003988: 1000 addi s0,sp,32 + 300398a: fea42623 sw a0,-20(s0) + 300398e: feb42423 sw a1,-24(s0) + 3003992: fec42703 lw a4,-20(s0) + 3003996: 145007b7 lui a5,0x14500 + 300399a: 04f70863 beq a4,a5,30039ea + 300399e: fec42703 lw a4,-20(s0) + 30039a2: 145017b7 lui a5,0x14501 + 30039a6: 04f70263 beq a4,a5,30039ea + 30039aa: fec42703 lw a4,-20(s0) + 30039ae: 145027b7 lui a5,0x14502 + 30039b2: 02f70c63 beq a4,a5,30039ea + 30039b6: fec42703 lw a4,-20(s0) + 30039ba: 145037b7 lui a5,0x14503 + 30039be: 02f70663 beq a4,a5,30039ea + 30039c2: fec42703 lw a4,-20(s0) + 30039c6: 145047b7 lui a5,0x14504 + 30039ca: 02f70063 beq a4,a5,30039ea + 30039ce: fec42703 lw a4,-20(s0) + 30039d2: 145057b7 lui a5,0x14505 + 30039d6: 00f70a63 beq a4,a5,30039ea + 30039da: 27800593 li a1,632 + 30039de: 030097b7 lui a5,0x3009 + 30039e2: 9c078513 addi a0,a5,-1600 # 30089c0 + 30039e6: 2ea5 jal ra,3003d5e + 30039e8: a001 j 30039e8 + 30039ea: fe842503 lw a0,-24(s0) + 30039ee: 3e8d jal ra,3003560 + 30039f0: 87aa mv a5,a0 + 30039f2: 0017c793 xori a5,a5,1 + 30039f6: 9f81 uxtb a5 + 30039f8: cb89 beqz a5,3003a0a + 30039fa: 27900593 li a1,633 + 30039fe: 030097b7 lui a5,0x3009 + 3003a02: 9c078513 addi a0,a5,-1600 # 30089c0 + 3003a06: 2ea1 jal ra,3003d5e + 3003a08: a831 j 3003a24 + 3003a0a: fec42783 lw a5,-20(s0) + 3003a0e: 4107a703 lw a4,1040(a5) + 3003a12: fe842783 lw a5,-24(s0) + 3003a16: fff7c793 not a5,a5 + 3003a1a: 8f7d and a4,a4,a5 + 3003a1c: fec42783 lw a5,-20(s0) + 3003a20: 40e7a823 sw a4,1040(a5) + 3003a24: 40f2 lw ra,28(sp) + 3003a26: 4462 lw s0,24(sp) + 3003a28: 6105 addi sp,sp,32 + 3003a2a: 8082 ret + +03003a2c : + 3003a2c: 1101 addi sp,sp,-32 + 3003a2e: ce06 sw ra,28(sp) + 3003a30: cc22 sw s0,24(sp) + 3003a32: 1000 addi s0,sp,32 + 3003a34: fea42623 sw a0,-20(s0) + 3003a38: fec42703 lw a4,-20(s0) + 3003a3c: 145007b7 lui a5,0x14500 + 3003a40: 04f70863 beq a4,a5,3003a90 + 3003a44: fec42703 lw a4,-20(s0) + 3003a48: 145017b7 lui a5,0x14501 + 3003a4c: 04f70263 beq a4,a5,3003a90 + 3003a50: fec42703 lw a4,-20(s0) + 3003a54: 145027b7 lui a5,0x14502 + 3003a58: 02f70c63 beq a4,a5,3003a90 + 3003a5c: fec42703 lw a4,-20(s0) + 3003a60: 145037b7 lui a5,0x14503 + 3003a64: 02f70663 beq a4,a5,3003a90 + 3003a68: fec42703 lw a4,-20(s0) + 3003a6c: 145047b7 lui a5,0x14504 + 3003a70: 02f70063 beq a4,a5,3003a90 + 3003a74: fec42703 lw a4,-20(s0) + 3003a78: 145057b7 lui a5,0x14505 + 3003a7c: 00f70a63 beq a4,a5,3003a90 + 3003a80: 29a00593 li a1,666 + 3003a84: 030097b7 lui a5,0x3009 + 3003a88: 9c078513 addi a0,a5,-1600 # 30089c0 + 3003a8c: 2cc9 jal ra,3003d5e + 3003a8e: a001 j 3003a8e + 3003a90: fec42783 lw a5,-20(s0) + 3003a94: 4187a783 lw a5,1048(a5) + 3003a98: 0ff7f793 andi a5,a5,255 + 3003a9c: 853e mv a0,a5 + 3003a9e: 40f2 lw ra,28(sp) + 3003aa0: 4462 lw s0,24(sp) + 3003aa2: 6105 addi sp,sp,32 + 3003aa4: 8082 ret + +03003aa6 : + 3003aa6: 7179 addi sp,sp,-48 + 3003aa8: d606 sw ra,44(sp) + 3003aaa: d422 sw s0,40(sp) + 3003aac: 1800 addi s0,sp,48 + 3003aae: fca42e23 sw a0,-36(s0) + 3003ab2: fdc42783 lw a5,-36(s0) + 3003ab6: eb89 bnez a5,3003ac8 + 3003ab8: 02b00593 li a1,43 + 3003abc: 030097b7 lui a5,0x3009 + 3003ac0: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003ac4: 2c69 jal ra,3003d5e + 3003ac6: a001 j 3003ac6 + 3003ac8: fdc42783 lw a5,-36(s0) + 3003acc: 4398 lw a4,0(a5) + 3003ace: 145007b7 lui a5,0x14500 + 3003ad2: 04f70d63 beq a4,a5,3003b2c + 3003ad6: fdc42783 lw a5,-36(s0) + 3003ada: 4398 lw a4,0(a5) + 3003adc: 145017b7 lui a5,0x14501 + 3003ae0: 04f70663 beq a4,a5,3003b2c + 3003ae4: fdc42783 lw a5,-36(s0) + 3003ae8: 4398 lw a4,0(a5) + 3003aea: 145027b7 lui a5,0x14502 + 3003aee: 02f70f63 beq a4,a5,3003b2c + 3003af2: fdc42783 lw a5,-36(s0) + 3003af6: 4398 lw a4,0(a5) + 3003af8: 145037b7 lui a5,0x14503 + 3003afc: 02f70863 beq a4,a5,3003b2c + 3003b00: fdc42783 lw a5,-36(s0) + 3003b04: 4398 lw a4,0(a5) + 3003b06: 145047b7 lui a5,0x14504 + 3003b0a: 02f70163 beq a4,a5,3003b2c + 3003b0e: fdc42783 lw a5,-36(s0) + 3003b12: 4398 lw a4,0(a5) + 3003b14: 145057b7 lui a5,0x14505 + 3003b18: 00f70a63 beq a4,a5,3003b2c + 3003b1c: 02c00593 li a1,44 + 3003b20: 030097b7 lui a5,0x3009 + 3003b24: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003b28: 2c1d jal ra,3003d5e + 3003b2a: a001 j 3003b2a + 3003b2c: fdc42783 lw a5,-36(s0) + 3003b30: 43dc lw a5,4(a5) + 3003b32: 853e mv a0,a5 + 3003b34: 3435 jal ra,3003560 + 3003b36: 87aa mv a5,a0 + 3003b38: 0017c793 xori a5,a5,1 + 3003b3c: 9f81 uxtb a5 + 3003b3e: cb89 beqz a5,3003b50 + 3003b40: 02d00593 li a1,45 + 3003b44: 030097b7 lui a5,0x3009 + 3003b48: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003b4c: 2c09 jal ra,3003d5e + 3003b4e: a81d j 3003b84 + 3003b50: fe042623 sw zero,-20(s0) + 3003b54: a01d j 3003b7a + 3003b56: 4705 li a4,1 + 3003b58: fec42783 lw a5,-20(s0) + 3003b5c: 00f717b3 sll a5,a4,a5 + 3003b60: 86be mv a3,a5 + 3003b62: fdc42703 lw a4,-36(s0) + 3003b66: fec42783 lw a5,-20(s0) + 3003b6a: 078e slli a5,a5,0x3 + 3003b6c: 97ba add a5,a5,a4 + 3003b6e: c794 sw a3,8(a5) + 3003b70: fec42783 lw a5,-20(s0) + 3003b74: 0785 addi a5,a5,1 + 3003b76: fef42623 sw a5,-20(s0) + 3003b7a: fec42703 lw a4,-20(s0) + 3003b7e: 479d li a5,7 + 3003b80: fce7fbe3 bgeu a5,a4,3003b56 + 3003b84: 50b2 lw ra,44(sp) + 3003b86: 5422 lw s0,40(sp) + 3003b88: 6145 addi sp,sp,48 + 3003b8a: 8082 ret + +03003b8c : + 3003b8c: 1101 addi sp,sp,-32 + 3003b8e: ce06 sw ra,28(sp) + 3003b90: cc22 sw s0,24(sp) + 3003b92: 1000 addi s0,sp,32 + 3003b94: fea42623 sw a0,-20(s0) + 3003b98: feb42423 sw a1,-24(s0) + 3003b9c: fec42223 sw a2,-28(s0) + 3003ba0: fec42783 lw a5,-20(s0) + 3003ba4: eb89 bnez a5,3003bb6 + 3003ba6: 04f00593 li a1,79 + 3003baa: 030097b7 lui a5,0x3009 + 3003bae: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003bb2: 2275 jal ra,3003d5e + 3003bb4: a001 j 3003bb4 + 3003bb6: fec42783 lw a5,-20(s0) + 3003bba: 4398 lw a4,0(a5) + 3003bbc: 145007b7 lui a5,0x14500 + 3003bc0: 04f70d63 beq a4,a5,3003c1a + 3003bc4: fec42783 lw a5,-20(s0) + 3003bc8: 4398 lw a4,0(a5) + 3003bca: 145017b7 lui a5,0x14501 + 3003bce: 04f70663 beq a4,a5,3003c1a + 3003bd2: fec42783 lw a5,-20(s0) + 3003bd6: 4398 lw a4,0(a5) + 3003bd8: 145027b7 lui a5,0x14502 + 3003bdc: 02f70f63 beq a4,a5,3003c1a + 3003be0: fec42783 lw a5,-20(s0) + 3003be4: 4398 lw a4,0(a5) + 3003be6: 145037b7 lui a5,0x14503 + 3003bea: 02f70863 beq a4,a5,3003c1a + 3003bee: fec42783 lw a5,-20(s0) + 3003bf2: 4398 lw a4,0(a5) + 3003bf4: 145047b7 lui a5,0x14504 + 3003bf8: 02f70163 beq a4,a5,3003c1a + 3003bfc: fec42783 lw a5,-20(s0) + 3003c00: 4398 lw a4,0(a5) + 3003c02: 145057b7 lui a5,0x14505 + 3003c06: 00f70a63 beq a4,a5,3003c1a + 3003c0a: 05000593 li a1,80 + 3003c0e: 030097b7 lui a5,0x3009 + 3003c12: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003c16: 22a1 jal ra,3003d5e + 3003c18: a001 j 3003c18 + 3003c1a: fe842503 lw a0,-24(s0) + 3003c1e: 3289 jal ra,3003560 + 3003c20: 87aa mv a5,a0 + 3003c22: 0017c793 xori a5,a5,1 + 3003c26: 9f81 uxtb a5 + 3003c28: cb89 beqz a5,3003c3a + 3003c2a: 05100593 li a1,81 + 3003c2e: 030097b7 lui a5,0x3009 + 3003c32: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003c36: 2225 jal ra,3003d5e + 3003c38: a815 j 3003c6c + 3003c3a: fe442503 lw a0,-28(s0) + 3003c3e: 38dd jal ra,3003534 + 3003c40: 87aa mv a5,a0 + 3003c42: 0017c793 xori a5,a5,1 + 3003c46: 9f81 uxtb a5 + 3003c48: cb89 beqz a5,3003c5a + 3003c4a: 05200593 li a1,82 + 3003c4e: 030097b7 lui a5,0x3009 + 3003c52: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003c56: 2221 jal ra,3003d5e + 3003c58: a811 j 3003c6c + 3003c5a: fec42783 lw a5,-20(s0) + 3003c5e: 439c lw a5,0(a5) + 3003c60: fe442603 lw a2,-28(s0) + 3003c64: fe842583 lw a1,-24(s0) + 3003c68: 853e mv a0,a5 + 3003c6a: 34f1 jal ra,3003736 + 3003c6c: 40f2 lw ra,28(sp) + 3003c6e: 4462 lw s0,24(sp) + 3003c70: 6105 addi sp,sp,32 + 3003c72: 8082 ret + +03003c74 : + 3003c74: 1101 addi sp,sp,-32 + 3003c76: ce06 sw ra,28(sp) + 3003c78: cc22 sw s0,24(sp) + 3003c7a: 1000 addi s0,sp,32 + 3003c7c: fea42623 sw a0,-20(s0) + 3003c80: feb42423 sw a1,-24(s0) + 3003c84: fec42223 sw a2,-28(s0) + 3003c88: fec42783 lw a5,-20(s0) + 3003c8c: eb89 bnez a5,3003c9e + 3003c8e: 05f00593 li a1,95 + 3003c92: 030097b7 lui a5,0x3009 + 3003c96: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003c9a: 20d1 jal ra,3003d5e + 3003c9c: a001 j 3003c9c + 3003c9e: fec42783 lw a5,-20(s0) + 3003ca2: 4398 lw a4,0(a5) + 3003ca4: 145007b7 lui a5,0x14500 + 3003ca8: 04f70d63 beq a4,a5,3003d02 + 3003cac: fec42783 lw a5,-20(s0) + 3003cb0: 4398 lw a4,0(a5) + 3003cb2: 145017b7 lui a5,0x14501 + 3003cb6: 04f70663 beq a4,a5,3003d02 + 3003cba: fec42783 lw a5,-20(s0) + 3003cbe: 4398 lw a4,0(a5) + 3003cc0: 145027b7 lui a5,0x14502 + 3003cc4: 02f70f63 beq a4,a5,3003d02 + 3003cc8: fec42783 lw a5,-20(s0) + 3003ccc: 4398 lw a4,0(a5) + 3003cce: 145037b7 lui a5,0x14503 + 3003cd2: 02f70863 beq a4,a5,3003d02 + 3003cd6: fec42783 lw a5,-20(s0) + 3003cda: 4398 lw a4,0(a5) + 3003cdc: 145047b7 lui a5,0x14504 + 3003ce0: 02f70163 beq a4,a5,3003d02 + 3003ce4: fec42783 lw a5,-20(s0) + 3003ce8: 4398 lw a4,0(a5) + 3003cea: 145057b7 lui a5,0x14505 + 3003cee: 00f70a63 beq a4,a5,3003d02 + 3003cf2: 06000593 li a1,96 + 3003cf6: 030097b7 lui a5,0x3009 + 3003cfa: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003cfe: 2085 jal ra,3003d5e + 3003d00: a001 j 3003d00 + 3003d02: fe842503 lw a0,-24(s0) + 3003d06: 38a9 jal ra,3003560 + 3003d08: 87aa mv a5,a0 + 3003d0a: 0017c793 xori a5,a5,1 + 3003d0e: 9f81 uxtb a5 + 3003d10: cb89 beqz a5,3003d22 + 3003d12: 06100593 li a1,97 + 3003d16: 030097b7 lui a5,0x3009 + 3003d1a: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003d1e: 2081 jal ra,3003d5e + 3003d20: a81d j 3003d56 + 3003d22: fe442503 lw a0,-28(s0) + 3003d26: fe2ff0ef jal ra,3003508 + 3003d2a: 87aa mv a5,a0 + 3003d2c: 0017c793 xori a5,a5,1 + 3003d30: 9f81 uxtb a5 + 3003d32: cb89 beqz a5,3003d44 + 3003d34: 06200593 li a1,98 + 3003d38: 030097b7 lui a5,0x3009 + 3003d3c: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003d40: 2839 jal ra,3003d5e + 3003d42: a811 j 3003d56 + 3003d44: fec42783 lw a5,-20(s0) + 3003d48: 439c lw a5,0(a5) + 3003d4a: fe442603 lw a2,-28(s0) + 3003d4e: fe842583 lw a1,-24(s0) + 3003d52: 853e mv a0,a5 + 3003d54: 3239 jal ra,3003662 + 3003d56: 40f2 lw ra,28(sp) + 3003d58: 4462 lw s0,24(sp) + 3003d5a: 6105 addi sp,sp,32 + 3003d5c: 8082 ret + +03003d5e : + 3003d5e: caafd06f j 3001208 + +03003d62 : + 3003d62: 1101 addi sp,sp,-32 + 3003d64: ce06 sw ra,28(sp) + 3003d66: cc22 sw s0,24(sp) + 3003d68: 1000 addi s0,sp,32 + 3003d6a: fea42623 sw a0,-20(s0) + 3003d6e: feb42423 sw a1,-24(s0) + 3003d72: fec42783 lw a5,-20(s0) + 3003d76: eb89 bnez a5,3003d88 + 3003d78: 0a300593 li a1,163 + 3003d7c: 030097b7 lui a5,0x3009 + 3003d80: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003d84: 3fe9 jal ra,3003d5e + 3003d86: a001 j 3003d86 + 3003d88: fec42783 lw a5,-20(s0) + 3003d8c: 4398 lw a4,0(a5) + 3003d8e: 145007b7 lui a5,0x14500 + 3003d92: 04f70d63 beq a4,a5,3003dec + 3003d96: fec42783 lw a5,-20(s0) + 3003d9a: 4398 lw a4,0(a5) + 3003d9c: 145017b7 lui a5,0x14501 + 3003da0: 04f70663 beq a4,a5,3003dec + 3003da4: fec42783 lw a5,-20(s0) + 3003da8: 4398 lw a4,0(a5) + 3003daa: 145027b7 lui a5,0x14502 + 3003dae: 02f70f63 beq a4,a5,3003dec + 3003db2: fec42783 lw a5,-20(s0) + 3003db6: 4398 lw a4,0(a5) + 3003db8: 145037b7 lui a5,0x14503 + 3003dbc: 02f70863 beq a4,a5,3003dec + 3003dc0: fec42783 lw a5,-20(s0) + 3003dc4: 4398 lw a4,0(a5) + 3003dc6: 145047b7 lui a5,0x14504 + 3003dca: 02f70163 beq a4,a5,3003dec + 3003dce: fec42783 lw a5,-20(s0) + 3003dd2: 4398 lw a4,0(a5) + 3003dd4: 145057b7 lui a5,0x14505 + 3003dd8: 00f70a63 beq a4,a5,3003dec + 3003ddc: 0a400593 li a1,164 + 3003de0: 030097b7 lui a5,0x3009 + 3003de4: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003de8: 3f9d jal ra,3003d5e + 3003dea: a001 j 3003dea + 3003dec: fe842503 lw a0,-24(s0) + 3003df0: f70ff0ef jal ra,3003560 + 3003df4: 87aa mv a5,a0 + 3003df6: 0017c793 xori a5,a5,1 + 3003dfa: 9f81 uxtb a5 + 3003dfc: cb89 beqz a5,3003e0e + 3003dfe: 0a500593 li a1,165 + 3003e02: 030097b7 lui a5,0x3009 + 3003e06: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003e0a: 3f91 jal ra,3003d5e + 3003e0c: a025 j 3003e34 + 3003e0e: fec42783 lw a5,-20(s0) + 3003e12: 4398 lw a4,0(a5) + 3003e14: fe842783 lw a5,-24(s0) + 3003e18: 078a slli a5,a5,0x2 + 3003e1a: 97ba add a5,a5,a4 + 3003e1c: 4398 lw a4,0(a5) + 3003e1e: fec42783 lw a5,-20(s0) + 3003e22: 4394 lw a3,0(a5) + 3003e24: fe842783 lw a5,-24(s0) + 3003e28: 8f3d xor a4,a4,a5 + 3003e2a: fe842783 lw a5,-24(s0) + 3003e2e: 078a slli a5,a5,0x2 + 3003e30: 97b6 add a5,a5,a3 + 3003e32: c398 sw a4,0(a5) + 3003e34: 40f2 lw ra,28(sp) + 3003e36: 4462 lw s0,24(sp) + 3003e38: 6105 addi sp,sp,32 + 3003e3a: 8082 ret + +03003e3c : + 3003e3c: 1101 addi sp,sp,-32 + 3003e3e: ce22 sw s0,28(sp) + 3003e40: 1000 addi s0,sp,32 + 3003e42: fea42623 sw a0,-20(s0) + 3003e46: feb42423 sw a1,-24(s0) + 3003e4a: fec42223 sw a2,-28(s0) + 3003e4e: fec42783 lw a5,-20(s0) + 3003e52: 439c lw a5,0(a5) + 3003e54: 4087a683 lw a3,1032(a5) + 3003e58: fe842783 lw a5,-24(s0) + 3003e5c: fff7c713 not a4,a5 + 3003e60: fec42783 lw a5,-20(s0) + 3003e64: 439c lw a5,0(a5) + 3003e66: 8f75 and a4,a4,a3 + 3003e68: 40e7a423 sw a4,1032(a5) + 3003e6c: fec42783 lw a5,-20(s0) + 3003e70: 439c lw a5,0(a5) + 3003e72: 4047a683 lw a3,1028(a5) + 3003e76: fec42783 lw a5,-20(s0) + 3003e7a: 439c lw a5,0(a5) + 3003e7c: fe842703 lw a4,-24(s0) + 3003e80: 8f55 or a4,a4,a3 + 3003e82: 40e7a223 sw a4,1028(a5) + 3003e86: fe442703 lw a4,-28(s0) + 3003e8a: 478d li a5,3 + 3003e8c: 02f71063 bne a4,a5,3003eac + 3003e90: fec42783 lw a5,-20(s0) + 3003e94: 439c lw a5,0(a5) + 3003e96: 40c7a683 lw a3,1036(a5) + 3003e9a: fec42783 lw a5,-20(s0) + 3003e9e: 439c lw a5,0(a5) + 3003ea0: fe842703 lw a4,-24(s0) + 3003ea4: 8f55 or a4,a4,a3 + 3003ea6: 40e7a623 sw a4,1036(a5) + 3003eaa: a005 j 3003eca + 3003eac: fec42783 lw a5,-20(s0) + 3003eb0: 439c lw a5,0(a5) + 3003eb2: 40c7a683 lw a3,1036(a5) + 3003eb6: fe842783 lw a5,-24(s0) + 3003eba: fff7c713 not a4,a5 + 3003ebe: fec42783 lw a5,-20(s0) + 3003ec2: 439c lw a5,0(a5) + 3003ec4: 8f75 and a4,a4,a3 + 3003ec6: 40e7a623 sw a4,1036(a5) + 3003eca: 0001 nop + 3003ecc: 4472 lw s0,28(sp) + 3003ece: 6105 addi sp,sp,32 + 3003ed0: 8082 ret + +03003ed2 : + 3003ed2: 1101 addi sp,sp,-32 + 3003ed4: ce22 sw s0,28(sp) + 3003ed6: 1000 addi s0,sp,32 + 3003ed8: fea42623 sw a0,-20(s0) + 3003edc: feb42423 sw a1,-24(s0) + 3003ee0: fec42223 sw a2,-28(s0) + 3003ee4: fec42783 lw a5,-20(s0) + 3003ee8: 439c lw a5,0(a5) + 3003eea: 4047a683 lw a3,1028(a5) + 3003eee: fe842783 lw a5,-24(s0) + 3003ef2: fff7c713 not a4,a5 + 3003ef6: fec42783 lw a5,-20(s0) + 3003efa: 439c lw a5,0(a5) + 3003efc: 8f75 and a4,a4,a3 + 3003efe: 40e7a223 sw a4,1028(a5) + 3003f02: fec42783 lw a5,-20(s0) + 3003f06: 439c lw a5,0(a5) + 3003f08: 4087a683 lw a3,1032(a5) + 3003f0c: fe842783 lw a5,-24(s0) + 3003f10: fff7c713 not a4,a5 + 3003f14: fec42783 lw a5,-20(s0) + 3003f18: 439c lw a5,0(a5) + 3003f1a: 8f75 and a4,a4,a3 + 3003f1c: 40e7a423 sw a4,1032(a5) + 3003f20: fe442703 lw a4,-28(s0) + 3003f24: 4785 li a5,1 + 3003f26: 02f71063 bne a4,a5,3003f46 + 3003f2a: fec42783 lw a5,-20(s0) + 3003f2e: 439c lw a5,0(a5) + 3003f30: 40c7a683 lw a3,1036(a5) + 3003f34: fec42783 lw a5,-20(s0) + 3003f38: 439c lw a5,0(a5) + 3003f3a: fe842703 lw a4,-24(s0) + 3003f3e: 8f55 or a4,a4,a3 + 3003f40: 40e7a623 sw a4,1036(a5) + 3003f44: a005 j 3003f64 + 3003f46: fec42783 lw a5,-20(s0) + 3003f4a: 439c lw a5,0(a5) + 3003f4c: 40c7a683 lw a3,1036(a5) + 3003f50: fe842783 lw a5,-24(s0) + 3003f54: fff7c713 not a4,a5 + 3003f58: fec42783 lw a5,-20(s0) + 3003f5c: 439c lw a5,0(a5) + 3003f5e: 8f75 and a4,a4,a3 + 3003f60: 40e7a623 sw a4,1036(a5) + 3003f64: 0001 nop + 3003f66: 4472 lw s0,28(sp) + 3003f68: 6105 addi sp,sp,32 + 3003f6a: 8082 ret + +03003f6c : + 3003f6c: 1101 addi sp,sp,-32 + 3003f6e: ce06 sw ra,28(sp) + 3003f70: cc22 sw s0,24(sp) + 3003f72: 1000 addi s0,sp,32 + 3003f74: fea42623 sw a0,-20(s0) + 3003f78: feb42423 sw a1,-24(s0) + 3003f7c: fec42223 sw a2,-28(s0) + 3003f80: fec42783 lw a5,-20(s0) + 3003f84: eb89 bnez a5,3003f96 + 3003f86: 0ef00593 li a1,239 + 3003f8a: 030097b7 lui a5,0x3009 + 3003f8e: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003f92: 33f1 jal ra,3003d5e + 3003f94: a001 j 3003f94 + 3003f96: fec42783 lw a5,-20(s0) + 3003f9a: 4398 lw a4,0(a5) + 3003f9c: 145007b7 lui a5,0x14500 + 3003fa0: 04f70d63 beq a4,a5,3003ffa + 3003fa4: fec42783 lw a5,-20(s0) + 3003fa8: 4398 lw a4,0(a5) + 3003faa: 145017b7 lui a5,0x14501 + 3003fae: 04f70663 beq a4,a5,3003ffa + 3003fb2: fec42783 lw a5,-20(s0) + 3003fb6: 4398 lw a4,0(a5) + 3003fb8: 145027b7 lui a5,0x14502 + 3003fbc: 02f70f63 beq a4,a5,3003ffa + 3003fc0: fec42783 lw a5,-20(s0) + 3003fc4: 4398 lw a4,0(a5) + 3003fc6: 145037b7 lui a5,0x14503 + 3003fca: 02f70863 beq a4,a5,3003ffa + 3003fce: fec42783 lw a5,-20(s0) + 3003fd2: 4398 lw a4,0(a5) + 3003fd4: 145047b7 lui a5,0x14504 + 3003fd8: 02f70163 beq a4,a5,3003ffa + 3003fdc: fec42783 lw a5,-20(s0) + 3003fe0: 4398 lw a4,0(a5) + 3003fe2: 145057b7 lui a5,0x14505 + 3003fe6: 00f70a63 beq a4,a5,3003ffa + 3003fea: 0f000593 li a1,240 + 3003fee: 030097b7 lui a5,0x3009 + 3003ff2: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003ff6: 33a5 jal ra,3003d5e + 3003ff8: a001 j 3003ff8 + 3003ffa: fe842503 lw a0,-24(s0) + 3003ffe: d62ff0ef jal ra,3003560 + 3004002: 87aa mv a5,a0 + 3004004: 0017c793 xori a5,a5,1 + 3004008: 9f81 uxtb a5 + 300400a: cb91 beqz a5,300401e + 300400c: 0f100593 li a1,241 + 3004010: 030097b7 lui a5,0x3009 + 3004014: 9e078513 addi a0,a5,-1568 # 30089e0 + 3004018: 3399 jal ra,3003d5e + 300401a: 4785 li a5,1 + 300401c: aa91 j 3004170 + 300401e: fe442503 lw a0,-28(s0) + 3004022: decff0ef jal ra,300360e + 3004026: 87aa mv a5,a0 + 3004028: 0017c793 xori a5,a5,1 + 300402c: 9f81 uxtb a5 + 300402e: cb91 beqz a5,3004042 + 3004030: 0f200593 li a1,242 + 3004034: 030097b7 lui a5,0x3009 + 3004038: 9e078513 addi a0,a5,-1568 # 30089e0 + 300403c: 330d jal ra,3003d5e + 300403e: 4785 li a5,1 + 3004040: aa05 j 3004170 + 3004042: fec42783 lw a5,-20(s0) + 3004046: 439c lw a5,0(a5) + 3004048: fe842583 lw a1,-24(s0) + 300404c: 853e mv a0,a5 + 300404e: 3a15 jal ra,3003982 + 3004050: fe442703 lw a4,-28(s0) + 3004054: 478d li a5,3 + 3004056: 00f70763 beq a4,a5,3004064 + 300405a: fe442703 lw a4,-28(s0) + 300405e: 4789 li a5,2 + 3004060: 00f71a63 bne a4,a5,3004074 + 3004064: fe442603 lw a2,-28(s0) + 3004068: fe842583 lw a1,-24(s0) + 300406c: fec42503 lw a0,-20(s0) + 3004070: 33f1 jal ra,3003e3c + 3004072: a0f5 j 300415e + 3004074: fe442703 lw a4,-28(s0) + 3004078: 4791 li a5,4 + 300407a: 04f71e63 bne a4,a5,30040d6 + 300407e: fec42783 lw a5,-20(s0) + 3004082: 439c lw a5,0(a5) + 3004084: 40c7a683 lw a3,1036(a5) + 3004088: fe842783 lw a5,-24(s0) + 300408c: fff7c713 not a4,a5 + 3004090: fec42783 lw a5,-20(s0) + 3004094: 439c lw a5,0(a5) + 3004096: 8f75 and a4,a4,a3 + 3004098: 40e7a623 sw a4,1036(a5) + 300409c: fec42783 lw a5,-20(s0) + 30040a0: 439c lw a5,0(a5) + 30040a2: 4047a683 lw a3,1028(a5) + 30040a6: fe842783 lw a5,-24(s0) + 30040aa: fff7c713 not a4,a5 + 30040ae: fec42783 lw a5,-20(s0) + 30040b2: 439c lw a5,0(a5) + 30040b4: 8f75 and a4,a4,a3 + 30040b6: 40e7a223 sw a4,1028(a5) + 30040ba: fec42783 lw a5,-20(s0) + 30040be: 439c lw a5,0(a5) + 30040c0: 4087a683 lw a3,1032(a5) + 30040c4: fec42783 lw a5,-20(s0) + 30040c8: 439c lw a5,0(a5) + 30040ca: fe842703 lw a4,-24(s0) + 30040ce: 8f55 or a4,a4,a3 + 30040d0: 40e7a423 sw a4,1032(a5) + 30040d4: a069 j 300415e + 30040d6: fe442703 lw a4,-28(s0) + 30040da: 4785 li a5,1 + 30040dc: 00f70563 beq a4,a5,30040e6 + 30040e0: fe442783 lw a5,-28(s0) + 30040e4: eb89 bnez a5,30040f6 + 30040e6: fe442603 lw a2,-28(s0) + 30040ea: fe842583 lw a1,-24(s0) + 30040ee: fec42503 lw a0,-20(s0) + 30040f2: 33c5 jal ra,3003ed2 + 30040f4: a0ad j 300415e + 30040f6: fe442703 lw a4,-28(s0) + 30040fa: 4795 li a5,5 + 30040fc: 06f71163 bne a4,a5,300415e + 3004100: fec42783 lw a5,-20(s0) + 3004104: 439c lw a5,0(a5) + 3004106: 40c7a683 lw a3,1036(a5) + 300410a: fe842783 lw a5,-24(s0) + 300410e: fff7c713 not a4,a5 + 3004112: fec42783 lw a5,-20(s0) + 3004116: 439c lw a5,0(a5) + 3004118: 8f75 and a4,a4,a3 + 300411a: 40e7a623 sw a4,1036(a5) + 300411e: fec42783 lw a5,-20(s0) + 3004122: 439c lw a5,0(a5) + 3004124: 4047a683 lw a3,1028(a5) + 3004128: fe842783 lw a5,-24(s0) + 300412c: fff7c713 not a4,a5 + 3004130: fec42783 lw a5,-20(s0) + 3004134: 439c lw a5,0(a5) + 3004136: 8f75 and a4,a4,a3 + 3004138: 40e7a223 sw a4,1028(a5) + 300413c: fec42783 lw a5,-20(s0) + 3004140: 439c lw a5,0(a5) + 3004142: 4087a683 lw a3,1032(a5) + 3004146: fe842783 lw a5,-24(s0) + 300414a: fff7c713 not a4,a5 + 300414e: fec42783 lw a5,-20(s0) + 3004152: 439c lw a5,0(a5) + 3004154: 8f75 and a4,a4,a3 + 3004156: 40e7a423 sw a4,1032(a5) + 300415a: 4785 li a5,1 + 300415c: a811 j 3004170 + 300415e: fec42783 lw a5,-20(s0) + 3004162: 439c lw a5,0(a5) + 3004164: fe842583 lw a1,-24(s0) + 3004168: 853e mv a0,a5 + 300416a: f68ff0ef jal ra,30038d2 + 300416e: 4781 li a5,0 + 3004170: 853e mv a0,a5 + 3004172: 40f2 lw ra,28(sp) + 3004174: 4462 lw s0,24(sp) + 3004176: 6105 addi sp,sp,32 + 3004178: 8082 ret + +0300417a : + 300417a: 7179 addi sp,sp,-48 + 300417c: d606 sw ra,44(sp) + 300417e: d422 sw s0,40(sp) + 3004180: 1800 addi s0,sp,48 + 3004182: fca42e23 sw a0,-36(s0) + 3004186: fcb42c23 sw a1,-40(s0) + 300418a: fdc42783 lw a5,-36(s0) + 300418e: eb89 bnez a5,30041a0 + 3004190: 11300593 li a1,275 + 3004194: 030097b7 lui a5,0x3009 + 3004198: 9e078513 addi a0,a5,-1568 # 30089e0 + 300419c: 36c9 jal ra,3003d5e + 300419e: a001 j 300419e + 30041a0: fdc42783 lw a5,-36(s0) + 30041a4: 4398 lw a4,0(a5) + 30041a6: 145007b7 lui a5,0x14500 + 30041aa: 04f70d63 beq a4,a5,3004204 + 30041ae: fdc42783 lw a5,-36(s0) + 30041b2: 4398 lw a4,0(a5) + 30041b4: 145017b7 lui a5,0x14501 + 30041b8: 04f70663 beq a4,a5,3004204 + 30041bc: fdc42783 lw a5,-36(s0) + 30041c0: 4398 lw a4,0(a5) + 30041c2: 145027b7 lui a5,0x14502 + 30041c6: 02f70f63 beq a4,a5,3004204 + 30041ca: fdc42783 lw a5,-36(s0) + 30041ce: 4398 lw a4,0(a5) + 30041d0: 145037b7 lui a5,0x14503 + 30041d4: 02f70863 beq a4,a5,3004204 + 30041d8: fdc42783 lw a5,-36(s0) + 30041dc: 4398 lw a4,0(a5) + 30041de: 145047b7 lui a5,0x14504 + 30041e2: 02f70163 beq a4,a5,3004204 + 30041e6: fdc42783 lw a5,-36(s0) + 30041ea: 4398 lw a4,0(a5) + 30041ec: 145057b7 lui a5,0x14505 + 30041f0: 00f70a63 beq a4,a5,3004204 + 30041f4: 11400593 li a1,276 + 30041f8: 030097b7 lui a5,0x3009 + 30041fc: 9e078513 addi a0,a5,-1568 # 30089e0 + 3004200: 3eb9 jal ra,3003d5e + 3004202: a001 j 3004202 + 3004204: fd842503 lw a0,-40(s0) + 3004208: b58ff0ef jal ra,3003560 + 300420c: 87aa mv a5,a0 + 300420e: 0017c793 xori a5,a5,1 + 3004212: 9f81 uxtb a5 + 3004214: cb89 beqz a5,3004226 + 3004216: 11500593 li a1,277 + 300421a: 030097b7 lui a5,0x3009 + 300421e: 9e078513 addi a0,a5,-1568 # 30089e0 + 3004222: 3e35 jal ra,3003d5e + 3004224: a899 j 300427a + 3004226: fe042623 sw zero,-20(s0) + 300422a: a099 j 3004270 + 300422c: fdc42703 lw a4,-36(s0) + 3004230: fec42783 lw a5,-20(s0) + 3004234: 078e slli a5,a5,0x3 + 3004236: 97ba add a5,a5,a4 + 3004238: 479c lw a5,8(a5) + 300423a: fd842703 lw a4,-40(s0) + 300423e: 02f71463 bne a4,a5,3004266 + 3004242: fdc42703 lw a4,-36(s0) + 3004246: fec42783 lw a5,-20(s0) + 300424a: 078e slli a5,a5,0x3 + 300424c: 97ba add a5,a5,a4 + 300424e: 47dc lw a5,12(a5) + 3004250: cb99 beqz a5,3004266 + 3004252: fdc42703 lw a4,-36(s0) + 3004256: fec42783 lw a5,-20(s0) + 300425a: 078e slli a5,a5,0x3 + 300425c: 97ba add a5,a5,a4 + 300425e: 47dc lw a5,12(a5) + 3004260: fdc42503 lw a0,-36(s0) + 3004264: 9782 jalr a5 + 3004266: fec42783 lw a5,-20(s0) + 300426a: 0785 addi a5,a5,1 + 300426c: fef42623 sw a5,-20(s0) + 3004270: fec42703 lw a4,-20(s0) + 3004274: 479d li a5,7 + 3004276: fae7fbe3 bgeu a5,a4,300422c + 300427a: 50b2 lw ra,44(sp) + 300427c: 5422 lw s0,40(sp) + 300427e: 6145 addi sp,sp,48 + 3004280: 8082 ret + +03004282 : + 3004282: 7179 addi sp,sp,-48 + 3004284: d606 sw ra,44(sp) + 3004286: d422 sw s0,40(sp) + 3004288: 1800 addi s0,sp,48 + 300428a: fca42e23 sw a0,-36(s0) + 300428e: fdc42783 lw a5,-36(s0) + 3004292: fef42423 sw a5,-24(s0) + 3004296: fe842783 lw a5,-24(s0) + 300429a: eb89 bnez a5,30042ac + 300429c: 12700593 li a1,295 + 30042a0: 030097b7 lui a5,0x3009 + 30042a4: 9e078513 addi a0,a5,-1568 # 30089e0 + 30042a8: 3c5d jal ra,3003d5e + 30042aa: a001 j 30042aa + 30042ac: fe842783 lw a5,-24(s0) + 30042b0: 4398 lw a4,0(a5) + 30042b2: 145007b7 lui a5,0x14500 + 30042b6: 04f70d63 beq a4,a5,3004310 + 30042ba: fe842783 lw a5,-24(s0) + 30042be: 4398 lw a4,0(a5) + 30042c0: 145017b7 lui a5,0x14501 + 30042c4: 04f70663 beq a4,a5,3004310 + 30042c8: fe842783 lw a5,-24(s0) + 30042cc: 4398 lw a4,0(a5) + 30042ce: 145027b7 lui a5,0x14502 + 30042d2: 02f70f63 beq a4,a5,3004310 + 30042d6: fe842783 lw a5,-24(s0) + 30042da: 4398 lw a4,0(a5) + 30042dc: 145037b7 lui a5,0x14503 + 30042e0: 02f70863 beq a4,a5,3004310 + 30042e4: fe842783 lw a5,-24(s0) + 30042e8: 4398 lw a4,0(a5) + 30042ea: 145047b7 lui a5,0x14504 + 30042ee: 02f70163 beq a4,a5,3004310 + 30042f2: fe842783 lw a5,-24(s0) + 30042f6: 4398 lw a4,0(a5) + 30042f8: 145057b7 lui a5,0x14505 + 30042fc: 00f70a63 beq a4,a5,3004310 + 3004300: 12800593 li a1,296 + 3004304: 030097b7 lui a5,0x3009 + 3004308: 9e078513 addi a0,a5,-1568 # 30089e0 + 300430c: 3c89 jal ra,3003d5e + 300430e: a001 j 300430e + 3004310: fe042623 sw zero,-20(s0) + 3004314: fe042223 sw zero,-28(s0) + 3004318: fe842783 lw a5,-24(s0) + 300431c: 439c lw a5,0(a5) + 300431e: 853e mv a0,a5 + 3004320: f0cff0ef jal ra,3003a2c + 3004324: fea42023 sw a0,-32(s0) + 3004328: a0b1 j 3004374 + 300432a: 4705 li a4,1 + 300432c: fec42783 lw a5,-20(s0) + 3004330: 00f717b3 sll a5,a4,a5 + 3004334: 873e mv a4,a5 + 3004336: fe042783 lw a5,-32(s0) + 300433a: 8ff9 and a5,a5,a4 + 300433c: fef42223 sw a5,-28(s0) + 3004340: fe442783 lw a5,-28(s0) + 3004344: c39d beqz a5,300436a + 3004346: fe842783 lw a5,-24(s0) + 300434a: fe442703 lw a4,-28(s0) + 300434e: c3d8 sw a4,4(a5) + 3004350: fe842783 lw a5,-24(s0) + 3004354: 439c lw a5,0(a5) + 3004356: fe442583 lw a1,-28(s0) + 300435a: 853e mv a0,a5 + 300435c: cd0ff0ef jal ra,300382c + 3004360: fe442583 lw a1,-28(s0) + 3004364: fe842503 lw a0,-24(s0) + 3004368: 3d09 jal ra,300417a + 300436a: fec42783 lw a5,-20(s0) + 300436e: 0785 addi a5,a5,1 + 3004370: fef42623 sw a5,-20(s0) + 3004374: fe042703 lw a4,-32(s0) + 3004378: fec42783 lw a5,-20(s0) + 300437c: 00f757b3 srl a5,a4,a5 + 3004380: f7cd bnez a5,300432a + 3004382: 0001 nop + 3004384: 50b2 lw ra,44(sp) + 3004386: 5422 lw s0,40(sp) + 3004388: 6145 addi sp,sp,48 + 300438a: 8082 ret + +0300438c : + 300438c: 7179 addi sp,sp,-48 + 300438e: d606 sw ra,44(sp) + 3004390: d422 sw s0,40(sp) + 3004392: 1800 addi s0,sp,48 + 3004394: fca42e23 sw a0,-36(s0) + 3004398: fcb42c23 sw a1,-40(s0) + 300439c: fcc42a23 sw a2,-44(s0) + 30043a0: fdc42783 lw a5,-36(s0) + 30043a4: eb89 bnez a5,30043b6 + 30043a6: 14200593 li a1,322 + 30043aa: 030097b7 lui a5,0x3009 + 30043ae: 9e078513 addi a0,a5,-1568 # 30089e0 + 30043b2: 3275 jal ra,3003d5e + 30043b4: a001 j 30043b4 + 30043b6: fdc42783 lw a5,-36(s0) + 30043ba: 4398 lw a4,0(a5) + 30043bc: 145007b7 lui a5,0x14500 + 30043c0: 04f70d63 beq a4,a5,300441a + 30043c4: fdc42783 lw a5,-36(s0) + 30043c8: 4398 lw a4,0(a5) + 30043ca: 145017b7 lui a5,0x14501 + 30043ce: 04f70663 beq a4,a5,300441a + 30043d2: fdc42783 lw a5,-36(s0) + 30043d6: 4398 lw a4,0(a5) + 30043d8: 145027b7 lui a5,0x14502 + 30043dc: 02f70f63 beq a4,a5,300441a + 30043e0: fdc42783 lw a5,-36(s0) + 30043e4: 4398 lw a4,0(a5) + 30043e6: 145037b7 lui a5,0x14503 + 30043ea: 02f70863 beq a4,a5,300441a + 30043ee: fdc42783 lw a5,-36(s0) + 30043f2: 4398 lw a4,0(a5) + 30043f4: 145047b7 lui a5,0x14504 + 30043f8: 02f70163 beq a4,a5,300441a + 30043fc: fdc42783 lw a5,-36(s0) + 3004400: 4398 lw a4,0(a5) + 3004402: 145057b7 lui a5,0x14505 + 3004406: 00f70a63 beq a4,a5,300441a + 300440a: 14300593 li a1,323 + 300440e: 030097b7 lui a5,0x3009 + 3004412: 9e078513 addi a0,a5,-1568 # 30089e0 + 3004416: 32a1 jal ra,3003d5e + 3004418: a001 j 3004418 + 300441a: fd842503 lw a0,-40(s0) + 300441e: 972ff0ef jal ra,3003590 + 3004422: 87aa mv a5,a0 + 3004424: 0017c793 xori a5,a5,1 + 3004428: 9f81 uxtb a5 + 300442a: cb89 beqz a5,300443c + 300442c: 14400593 li a1,324 + 3004430: 030097b7 lui a5,0x3009 + 3004434: 9e078513 addi a0,a5,-1568 # 30089e0 + 3004438: 321d jal ra,3003d5e + 300443a: a091 j 300447e + 300443c: fe042623 sw zero,-20(s0) + 3004440: a815 j 3004474 + 3004442: fdc42703 lw a4,-36(s0) + 3004446: fec42783 lw a5,-20(s0) + 300444a: 078e slli a5,a5,0x3 + 300444c: 97ba add a5,a5,a4 + 300444e: 479c lw a5,8(a5) + 3004450: fd842703 lw a4,-40(s0) + 3004454: 00f71b63 bne a4,a5,300446a + 3004458: fdc42703 lw a4,-36(s0) + 300445c: fec42783 lw a5,-20(s0) + 3004460: 078e slli a5,a5,0x3 + 3004462: 97ba add a5,a5,a4 + 3004464: fd442703 lw a4,-44(s0) + 3004468: c7d8 sw a4,12(a5) + 300446a: fec42783 lw a5,-20(s0) + 300446e: 0785 addi a5,a5,1 + 3004470: fef42623 sw a5,-20(s0) + 3004474: fec42703 lw a4,-20(s0) + 3004478: 479d li a5,7 + 300447a: fce7f4e3 bgeu a5,a4,3004442 + 300447e: 50b2 lw ra,44(sp) + 3004480: 5422 lw s0,40(sp) + 3004482: 6145 addi sp,sp,48 + 3004484: 8082 ret + +03004486 : + 3004486: 1101 addi sp,sp,-32 + 3004488: ce22 sw s0,28(sp) + 300448a: 1000 addi s0,sp,32 + 300448c: fea42623 sw a0,-20(s0) + 3004490: fec42783 lw a5,-20(s0) + 3004494: c385 beqz a5,30044b4 + 3004496: fec42703 lw a4,-20(s0) + 300449a: 4785 li a5,1 + 300449c: 00f70c63 beq a4,a5,30044b4 + 30044a0: fec42703 lw a4,-20(s0) + 30044a4: 4789 li a5,2 + 30044a6: 00f70763 beq a4,a5,30044b4 + 30044aa: fec42703 lw a4,-20(s0) + 30044ae: 478d li a5,3 + 30044b0: 00f71463 bne a4,a5,30044b8 + 30044b4: 4785 li a5,1 + 30044b6: a011 j 30044ba + 30044b8: 4781 li a5,0 + 30044ba: 8b85 andi a5,a5,1 + 30044bc: 9f81 uxtb a5 + 30044be: 853e mv a0,a5 + 30044c0: 4472 lw s0,28(sp) + 30044c2: 6105 addi sp,sp,32 + 30044c4: 8082 ret + +030044c6 : + 30044c6: 1101 addi sp,sp,-32 + 30044c8: ce22 sw s0,28(sp) + 30044ca: 1000 addi s0,sp,32 + 30044cc: fea42623 sw a0,-20(s0) + 30044d0: fec42783 lw a5,-20(s0) + 30044d4: c791 beqz a5,30044e0 + 30044d6: fec42703 lw a4,-20(s0) + 30044da: 4785 li a5,1 + 30044dc: 00f71463 bne a4,a5,30044e4 + 30044e0: 4785 li a5,1 + 30044e2: a011 j 30044e6 + 30044e4: 4781 li a5,0 + 30044e6: 8b85 andi a5,a5,1 + 30044e8: 9f81 uxtb a5 + 30044ea: 853e mv a0,a5 + 30044ec: 4472 lw s0,28(sp) + 30044ee: 6105 addi sp,sp,32 + 30044f0: 8082 ret + +030044f2 : + 30044f2: 1101 addi sp,sp,-32 + 30044f4: ce22 sw s0,28(sp) + 30044f6: 1000 addi s0,sp,32 + 30044f8: fea42623 sw a0,-20(s0) + 30044fc: fec42703 lw a4,-20(s0) + 3004500: 67c1 lui a5,0x10 + 3004502: 00f737b3 sltu a5,a4,a5 + 3004506: 9f81 uxtb a5 + 3004508: 853e mv a0,a5 + 300450a: 4472 lw s0,28(sp) + 300450c: 6105 addi sp,sp,32 + 300450e: 8082 ret + +03004510 : + 3004510: 1101 addi sp,sp,-32 + 3004512: ce22 sw s0,28(sp) + 3004514: 1000 addi s0,sp,32 + 3004516: fea42623 sw a0,-20(s0) + 300451a: fec42703 lw a4,-20(s0) + 300451e: 4785 li a5,1 + 3004520: 00f70563 beq a4,a5,300452a + 3004524: fec42783 lw a5,-20(s0) + 3004528: e399 bnez a5,300452e + 300452a: 4785 li a5,1 + 300452c: a011 j 3004530 + 300452e: 4781 li a5,0 + 3004530: 8b85 andi a5,a5,1 + 3004532: 9f81 uxtb a5 + 3004534: 853e mv a0,a5 + 3004536: 4472 lw s0,28(sp) + 3004538: 6105 addi sp,sp,32 + 300453a: 8082 ret + +0300453c : + 300453c: 1101 addi sp,sp,-32 + 300453e: ce22 sw s0,28(sp) + 3004540: 1000 addi s0,sp,32 + 3004542: fea42623 sw a0,-20(s0) + 3004546: fec42783 lw a5,-20(s0) + 300454a: 4007b793 sltiu a5,a5,1024 + 300454e: 9f81 uxtb a5 + 3004550: 853e mv a0,a5 + 3004552: 4472 lw s0,28(sp) + 3004554: 6105 addi sp,sp,32 + 3004556: 8082 ret + +03004558 : + 3004558: 1101 addi sp,sp,-32 + 300455a: ce22 sw s0,28(sp) + 300455c: 1000 addi s0,sp,32 + 300455e: fea42623 sw a0,-20(s0) + 3004562: fec42783 lw a5,-20(s0) + 3004566: 4007b793 sltiu a5,a5,1024 + 300456a: 9f81 uxtb a5 + 300456c: 853e mv a0,a5 + 300456e: 4472 lw s0,28(sp) + 3004570: 6105 addi sp,sp,32 + 3004572: 8082 ret + +03004574 : + 3004574: 1101 addi sp,sp,-32 + 3004576: ce22 sw s0,28(sp) + 3004578: 1000 addi s0,sp,32 + 300457a: fea42623 sw a0,-20(s0) + 300457e: fec42703 lw a4,-20(s0) + 3004582: 4785 li a5,1 + 3004584: 00f70563 beq a4,a5,300458e + 3004588: fec42783 lw a5,-20(s0) + 300458c: e399 bnez a5,3004592 + 300458e: 4785 li a5,1 + 3004590: a011 j 3004594 + 3004592: 4781 li a5,0 + 3004594: 8b85 andi a5,a5,1 + 3004596: 9f81 uxtb a5 + 3004598: 853e mv a0,a5 + 300459a: 4472 lw s0,28(sp) + 300459c: 6105 addi sp,sp,32 + 300459e: 8082 ret + +030045a0 : + 30045a0: 1101 addi sp,sp,-32 + 30045a2: ce22 sw s0,28(sp) + 30045a4: 1000 addi s0,sp,32 + 30045a6: fea42623 sw a0,-20(s0) + 30045aa: fec42783 lw a5,-20(s0) + 30045ae: 0107b793 sltiu a5,a5,16 + 30045b2: 9f81 uxtb a5 + 30045b4: 853e mv a0,a5 + 30045b6: 4472 lw s0,28(sp) + 30045b8: 6105 addi sp,sp,32 + 30045ba: 8082 ret + +030045bc : + 30045bc: 1101 addi sp,sp,-32 + 30045be: ce22 sw s0,28(sp) + 30045c0: 1000 addi s0,sp,32 + 30045c2: fea42623 sw a0,-20(s0) + 30045c6: fec42783 lw a5,-20(s0) + 30045ca: 00f037b3 snez a5,a5 + 30045ce: 9f81 uxtb a5 + 30045d0: 853e mv a0,a5 + 30045d2: 4472 lw s0,28(sp) + 30045d4: 6105 addi sp,sp,32 + 30045d6: 8082 ret + +030045d8 : + 30045d8: 1101 addi sp,sp,-32 + 30045da: ce22 sw s0,28(sp) + 30045dc: 1000 addi s0,sp,32 + 30045de: fea42623 sw a0,-20(s0) + 30045e2: fec42703 lw a4,-20(s0) + 30045e6: 4785 li a5,1 + 30045e8: 00f70563 beq a4,a5,30045f2 + 30045ec: fec42783 lw a5,-20(s0) + 30045f0: e399 bnez a5,30045f6 + 30045f2: 4785 li a5,1 + 30045f4: a011 j 30045f8 + 30045f6: 4781 li a5,0 + 30045f8: 8b85 andi a5,a5,1 + 30045fa: 9f81 uxtb a5 + 30045fc: 853e mv a0,a5 + 30045fe: 4472 lw s0,28(sp) + 3004600: 6105 addi sp,sp,32 + 3004602: 8082 ret + +03004604 : + 3004604: 1101 addi sp,sp,-32 + 3004606: ce22 sw s0,28(sp) + 3004608: 1000 addi s0,sp,32 + 300460a: fea42623 sw a0,-20(s0) + 300460e: fec42783 lw a5,-20(s0) + 3004612: 0107b793 sltiu a5,a5,16 + 3004616: 9f81 uxtb a5 + 3004618: 853e mv a0,a5 + 300461a: 4472 lw s0,28(sp) + 300461c: 6105 addi sp,sp,32 + 300461e: 8082 ret + +03004620 : + 3004620: 1101 addi sp,sp,-32 + 3004622: ce22 sw s0,28(sp) + 3004624: 1000 addi s0,sp,32 + 3004626: fea42623 sw a0,-20(s0) + 300462a: fec42783 lw a5,-20(s0) + 300462e: 0107b793 sltiu a5,a5,16 + 3004632: 9f81 uxtb a5 + 3004634: 853e mv a0,a5 + 3004636: 4472 lw s0,28(sp) + 3004638: 6105 addi sp,sp,32 + 300463a: 8082 ret + +0300463c : + 300463c: 1101 addi sp,sp,-32 + 300463e: ce22 sw s0,28(sp) + 3004640: 1000 addi s0,sp,32 + 3004642: fea42623 sw a0,-20(s0) + 3004646: fec42783 lw a5,-20(s0) + 300464a: 0107b793 sltiu a5,a5,16 + 300464e: 9f81 uxtb a5 + 3004650: 853e mv a0,a5 + 3004652: 4472 lw s0,28(sp) + 3004654: 6105 addi sp,sp,32 + 3004656: 8082 ret + +03004658 : + 3004658: 1101 addi sp,sp,-32 + 300465a: ce06 sw ra,28(sp) + 300465c: cc22 sw s0,24(sp) + 300465e: 1000 addi s0,sp,32 + 3004660: fea42623 sw a0,-20(s0) + 3004664: feb42423 sw a1,-24(s0) + 3004668: fec42783 lw a5,-20(s0) + 300466c: 43dc lw a5,4(a5) + 300466e: 853e mv a0,a5 + 3004670: 3d19 jal ra,3004486 + 3004672: 87aa mv a5,a0 + 3004674: 0017c793 xori a5,a5,1 + 3004678: 9f81 uxtb a5 + 300467a: cb91 beqz a5,300468e + 300467c: 09000593 li a1,144 + 3004680: 030097b7 lui a5,0x3009 + 3004684: 9fc78513 addi a0,a5,-1540 # 30089fc + 3004688: 2c31 jal ra,30048a4 + 300468a: 4785 li a5,1 + 300468c: a439 j 300489a + 300468e: fec42783 lw a5,-20(s0) + 3004692: 479c lw a5,8(a5) + 3004694: 853e mv a0,a5 + 3004696: 3d05 jal ra,30044c6 + 3004698: 87aa mv a5,a0 + 300469a: 0017c793 xori a5,a5,1 + 300469e: 9f81 uxtb a5 + 30046a0: cb91 beqz a5,30046b4 + 30046a2: 09100593 li a1,145 + 30046a6: 030097b7 lui a5,0x3009 + 30046aa: 9fc78513 addi a0,a5,-1540 # 30089fc + 30046ae: 2add jal ra,30048a4 + 30046b0: 4785 li a5,1 + 30046b2: a2e5 j 300489a + 30046b4: fec42783 lw a5,-20(s0) + 30046b8: 4b9c lw a5,16(a5) + 30046ba: 853e mv a0,a5 + 30046bc: 3d1d jal ra,30044f2 + 30046be: 87aa mv a5,a0 + 30046c0: 0017c793 xori a5,a5,1 + 30046c4: 9f81 uxtb a5 + 30046c6: cb91 beqz a5,30046da + 30046c8: 09200593 li a1,146 + 30046cc: 030097b7 lui a5,0x3009 + 30046d0: 9fc78513 addi a0,a5,-1540 # 30089fc + 30046d4: 2ac1 jal ra,30048a4 + 30046d6: 4785 li a5,1 + 30046d8: a2c9 j 300489a + 30046da: fec42783 lw a5,-20(s0) + 30046de: 4bdc lw a5,20(a5) + 30046e0: 853e mv a0,a5 + 30046e2: 3de9 jal ra,30045bc + 30046e4: 87aa mv a5,a0 + 30046e6: 0017c793 xori a5,a5,1 + 30046ea: 9f81 uxtb a5 + 30046ec: cb91 beqz a5,3004700 + 30046ee: 09400593 li a1,148 + 30046f2: 030097b7 lui a5,0x3009 + 30046f6: 9fc78513 addi a0,a5,-1540 # 30089fc + 30046fa: 226d jal ra,30048a4 + 30046fc: 4785 li a5,1 + 30046fe: aa71 j 300489a + 3004700: fe842783 lw a5,-24(s0) + 3004704: eb91 bnez a5,3004718 + 3004706: 09500593 li a1,149 + 300470a: 030097b7 lui a5,0x3009 + 300470e: 9fc78513 addi a0,a5,-1540 # 30089fc + 3004712: 2a49 jal ra,30048a4 + 3004714: 4785 li a5,1 + 3004716: a251 j 300489a + 3004718: fec42783 lw a5,-20(s0) + 300471c: 4bdc lw a5,20(a5) + 300471e: fe842703 lw a4,-24(s0) + 3004722: 00f77463 bgeu a4,a5,300472a + 3004726: 4785 li a5,1 + 3004728: aa8d j 300489a + 300472a: fec42783 lw a5,-20(s0) + 300472e: 4f9c lw a5,24(a5) + 3004730: 853e mv a0,a5 + 3004732: 355d jal ra,30045d8 + 3004734: 87aa mv a5,a0 + 3004736: 0017c793 xori a5,a5,1 + 300473a: 9f81 uxtb a5 + 300473c: cb91 beqz a5,3004750 + 300473e: 09b00593 li a1,155 + 3004742: 030097b7 lui a5,0x3009 + 3004746: 9fc78513 addi a0,a5,-1540 # 30089fc + 300474a: 2aa9 jal ra,30048a4 + 300474c: 4785 li a5,1 + 300474e: a2b1 j 300489a + 3004750: fec42783 lw a5,-20(s0) + 3004754: 5bdc lw a5,52(a5) + 3004756: 853e mv a0,a5 + 3004758: 3575 jal ra,3004604 + 300475a: 87aa mv a5,a0 + 300475c: 0017c793 xori a5,a5,1 + 3004760: 9f81 uxtb a5 + 3004762: cb91 beqz a5,3004776 + 3004764: 09c00593 li a1,156 + 3004768: 030097b7 lui a5,0x3009 + 300476c: 9fc78513 addi a0,a5,-1540 # 30089fc + 3004770: 2a15 jal ra,30048a4 + 3004772: 4785 li a5,1 + 3004774: a21d j 300489a + 3004776: fec42783 lw a5,-20(s0) + 300477a: 5b9c lw a5,48(a5) + 300477c: 853e mv a0,a5 + 300477e: 354d jal ra,3004620 + 3004780: 87aa mv a5,a0 + 3004782: 0017c793 xori a5,a5,1 + 3004786: 9f81 uxtb a5 + 3004788: cb91 beqz a5,300479c + 300478a: 09d00593 li a1,157 + 300478e: 030097b7 lui a5,0x3009 + 3004792: 9fc78513 addi a0,a5,-1540 # 30089fc + 3004796: 2239 jal ra,30048a4 + 3004798: 4785 li a5,1 + 300479a: a201 j 300489a + 300479c: fec42783 lw a5,-20(s0) + 30047a0: 4fbc lw a5,88(a5) + 30047a2: 853e mv a0,a5 + 30047a4: 3bf5 jal ra,30045a0 + 30047a6: 87aa mv a5,a0 + 30047a8: 0017c793 xori a5,a5,1 + 30047ac: 9f81 uxtb a5 + 30047ae: cb91 beqz a5,30047c2 + 30047b0: 09e00593 li a1,158 + 30047b4: 030097b7 lui a5,0x3009 + 30047b8: 9fc78513 addi a0,a5,-1540 # 30089fc + 30047bc: 20e5 jal ra,30048a4 + 30047be: 4785 li a5,1 + 30047c0: a8e9 j 300489a + 30047c2: fec42783 lw a5,-20(s0) + 30047c6: 4ffc lw a5,92(a5) + 30047c8: 853e mv a0,a5 + 30047ca: 3d8d jal ra,300463c + 30047cc: 87aa mv a5,a0 + 30047ce: 0017c793 xori a5,a5,1 + 30047d2: 9f81 uxtb a5 + 30047d4: cb91 beqz a5,30047e8 + 30047d6: 09f00593 li a1,159 + 30047da: 030097b7 lui a5,0x3009 + 30047de: 9fc78513 addi a0,a5,-1540 # 30089fc + 30047e2: 20c9 jal ra,30048a4 + 30047e4: 4785 li a5,1 + 30047e6: a855 j 300489a + 30047e8: fec42783 lw a5,-20(s0) + 30047ec: 43d8 lw a4,4(a5) + 30047ee: 4789 li a5,2 + 30047f0: 00f70863 beq a4,a5,3004800 + 30047f4: fec42783 lw a5,-20(s0) + 30047f8: 43d8 lw a4,4(a5) + 30047fa: 478d li a5,3 + 30047fc: 08f71e63 bne a4,a5,3004898 + 3004800: fec42783 lw a5,-20(s0) + 3004804: 47dc lw a5,12(a5) + 3004806: 853e mv a0,a5 + 3004808: 3b15 jal ra,300453c + 300480a: 87aa mv a5,a0 + 300480c: 0017c793 xori a5,a5,1 + 3004810: 9f81 uxtb a5 + 3004812: cb91 beqz a5,3004826 + 3004814: 0a300593 li a1,163 + 3004818: 030097b7 lui a5,0x3009 + 300481c: 9fc78513 addi a0,a5,-1540 # 30089fc + 3004820: 2051 jal ra,30048a4 + 3004822: 4785 li a5,1 + 3004824: a89d j 300489a + 3004826: fec42783 lw a5,-20(s0) + 300482a: 4fdc lw a5,28(a5) + 300482c: 853e mv a0,a5 + 300482e: 31cd jal ra,3004510 + 3004830: 87aa mv a5,a0 + 3004832: 0017c793 xori a5,a5,1 + 3004836: 9f81 uxtb a5 + 3004838: cb91 beqz a5,300484c + 300483a: 0a400593 li a1,164 + 300483e: 030097b7 lui a5,0x3009 + 3004842: 9fc78513 addi a0,a5,-1540 # 30089fc + 3004846: 28b9 jal ra,30048a4 + 3004848: 4785 li a5,1 + 300484a: a881 j 300489a + 300484c: fec42783 lw a5,-20(s0) + 3004850: 53bc lw a5,96(a5) + 3004852: 853e mv a0,a5 + 3004854: 3305 jal ra,3004574 + 3004856: 87aa mv a5,a0 + 3004858: 0017c793 xori a5,a5,1 + 300485c: 9f81 uxtb a5 + 300485e: cb91 beqz a5,3004872 + 3004860: 0a500593 li a1,165 + 3004864: 030097b7 lui a5,0x3009 + 3004868: 9fc78513 addi a0,a5,-1540 # 30089fc + 300486c: 2825 jal ra,30048a4 + 300486e: 4785 li a5,1 + 3004870: a02d j 300489a + 3004872: fec42783 lw a5,-20(s0) + 3004876: 53fc lw a5,100(a5) + 3004878: 853e mv a0,a5 + 300487a: 39f9 jal ra,3004558 + 300487c: 87aa mv a5,a0 + 300487e: 0017c793 xori a5,a5,1 + 3004882: 9f81 uxtb a5 + 3004884: cb91 beqz a5,3004898 + 3004886: 0a600593 li a1,166 + 300488a: 030097b7 lui a5,0x3009 + 300488e: 9fc78513 addi a0,a5,-1540 # 30089fc + 3004892: 2809 jal ra,30048a4 + 3004894: 4785 li a5,1 + 3004896: a011 j 300489a + 3004898: 4781 li a5,0 + 300489a: 853e mv a0,a5 + 300489c: 40f2 lw ra,28(sp) + 300489e: 4462 lw s0,24(sp) + 30048a0: 6105 addi sp,sp,32 + 30048a2: 8082 ret + +030048a4 : + 30048a4: 965fc06f j 3001208 + +030048a8 : + 30048a8: 7179 addi sp,sp,-48 + 30048aa: d622 sw s0,44(sp) + 30048ac: 1800 addi s0,sp,48 + 30048ae: fca42e23 sw a0,-36(s0) + 30048b2: fcb42c23 sw a1,-40(s0) + 30048b6: fdc42783 lw a5,-36(s0) + 30048ba: 4798 lw a4,8(a5) + 30048bc: 4785 li a5,1 + 30048be: 02f71663 bne a4,a5,30048ea + 30048c2: fd842783 lw a5,-40(s0) + 30048c6: 01079713 slli a4,a5,0x10 + 30048ca: feff07b7 lui a5,0xfeff0 + 30048ce: 8f7d and a4,a4,a5 + 30048d0: fd842683 lw a3,-40(s0) + 30048d4: 67c1 lui a5,0x10 + 30048d6: eff78793 addi a5,a5,-257 # feff + 30048da: 8ff5 and a5,a5,a3 + 30048dc: 8f5d or a4,a4,a5 + 30048de: 010007b7 lui a5,0x1000 + 30048e2: 8fd9 or a5,a5,a4 + 30048e4: fef42623 sw a5,-20(s0) + 30048e8: a00d j 300490a + 30048ea: fd842783 lw a5,-40(s0) + 30048ee: 01079713 slli a4,a5,0x10 + 30048f2: 00fe07b7 lui a5,0xfe0 + 30048f6: 8f7d and a4,a4,a5 + 30048f8: fd842783 lw a5,-40(s0) + 30048fc: 0fe7f793 andi a5,a5,254 + 3004900: 8f5d or a4,a4,a5 + 3004902: 67c1 lui a5,0x10 + 3004904: 8fd9 or a5,a5,a4 + 3004906: fef42623 sw a5,-20(s0) + 300490a: fdc42783 lw a5,-36(s0) + 300490e: 4398 lw a4,0(a5) + 3004910: 141007b7 lui a5,0x14100 + 3004914: 00f71a63 bne a4,a5,3004928 + 3004918: 040007b7 lui a5,0x4000 + 300491c: 49c78793 addi a5,a5,1180 # 400049c + 3004920: fec42703 lw a4,-20(s0) + 3004924: c3d8 sw a4,4(a5) + 3004926: a839 j 3004944 + 3004928: fdc42783 lw a5,-36(s0) + 300492c: 4398 lw a4,0(a5) + 300492e: 141017b7 lui a5,0x14101 + 3004932: 00f71963 bne a4,a5,3004944 + 3004936: 040007b7 lui a5,0x4000 + 300493a: 49c78793 addi a5,a5,1180 # 400049c + 300493e: fec42703 lw a4,-20(s0) + 3004942: cb98 sw a4,16(a5) + 3004944: 0001 nop + 3004946: 5432 lw s0,44(sp) + 3004948: 6145 addi sp,sp,48 + 300494a: 8082 ret + +0300494c : + 300494c: 7179 addi sp,sp,-48 + 300494e: d606 sw ra,44(sp) + 3004950: d422 sw s0,40(sp) + 3004952: 1800 addi s0,sp,48 + 3004954: fca42e23 sw a0,-36(s0) + 3004958: fdc42783 lw a5,-36(s0) + 300495c: 4705 li a4,1 + 300495e: c3f8 sw a4,68(a5) + 3004960: fdc42783 lw a5,-36(s0) + 3004964: 4398 lw a4,0(a5) + 3004966: 431c lw a5,0(a4) + 3004968: 9bf1 andi a5,a5,-4 + 300496a: c31c sw a5,0(a4) + 300496c: fdc42783 lw a5,-36(s0) + 3004970: 439c lw a5,0(a5) + 3004972: 0e07a223 sw zero,228(a5) + 3004976: fdc42783 lw a5,-36(s0) + 300497a: 439c lw a5,0(a5) + 300497c: 01000737 lui a4,0x1000 + 3004980: 177d addi a4,a4,-1 # ffffff + 3004982: 0ee7a023 sw a4,224(a5) + 3004986: fdc42783 lw a5,-36(s0) + 300498a: 4398 lw a4,0(a5) + 300498c: 0d472783 lw a5,212(a4) + 3004990: 1007e793 ori a5,a5,256 + 3004994: 0cf72a23 sw a5,212(a4) + 3004998: fdc42783 lw a5,-36(s0) + 300499c: 4398 lw a4,0(a5) + 300499e: 0d472783 lw a5,212(a4) + 30049a2: 0107e793 ori a5,a5,16 + 30049a6: 0cf72a23 sw a5,212(a4) + 30049aa: fdc42783 lw a5,-36(s0) + 30049ae: 4398 lw a4,0(a5) + 30049b0: 0d472783 lw a5,212(a4) + 30049b4: 0017e793 ori a5,a5,1 + 30049b8: 0cf72a23 sw a5,212(a4) + 30049bc: fe042623 sw zero,-20(s0) + 30049c0: a099 j 3004a06 + 30049c2: fdc42783 lw a5,-36(s0) + 30049c6: 4398 lw a4,0(a5) + 30049c8: 0d472783 lw a5,212(a4) + 30049cc: 9bbd andi a5,a5,-17 + 30049ce: 0cf72a23 sw a5,212(a4) + 30049d2: 000f47b7 lui a5,0xf4 + 30049d6: 24078593 addi a1,a5,576 # f4240 + 30049da: 4515 li a0,5 + 30049dc: 204d jal ra,3004a7e + 30049de: fdc42783 lw a5,-36(s0) + 30049e2: 4398 lw a4,0(a5) + 30049e4: 0d472783 lw a5,212(a4) + 30049e8: 0107e793 ori a5,a5,16 + 30049ec: 0cf72a23 sw a5,212(a4) + 30049f0: 000f47b7 lui a5,0xf4 + 30049f4: 24078593 addi a1,a5,576 # f4240 + 30049f8: 4515 li a0,5 + 30049fa: 2051 jal ra,3004a7e + 30049fc: fec42783 lw a5,-20(s0) + 3004a00: 0785 addi a5,a5,1 + 3004a02: fef42623 sw a5,-20(s0) + 3004a06: fec42703 lw a4,-20(s0) + 3004a0a: 47a1 li a5,8 + 3004a0c: fae7fbe3 bgeu a5,a4,30049c2 + 3004a10: fdc42783 lw a5,-36(s0) + 3004a14: 4398 lw a4,0(a5) + 3004a16: 0d472783 lw a5,212(a4) + 3004a1a: 0107e793 ori a5,a5,16 + 3004a1e: 0cf72a23 sw a5,212(a4) + 3004a22: fdc42783 lw a5,-36(s0) + 3004a26: 4398 lw a4,0(a5) + 3004a28: 0d472783 lw a5,212(a4) + 3004a2c: 0017e793 ori a5,a5,1 + 3004a30: 0cf72a23 sw a5,212(a4) + 3004a34: fdc42783 lw a5,-36(s0) + 3004a38: 4398 lw a4,0(a5) + 3004a3a: 0d472783 lw a5,212(a4) + 3004a3e: 9bf9 andi a5,a5,-2 + 3004a40: 0cf72a23 sw a5,212(a4) + 3004a44: 000f47b7 lui a5,0xf4 + 3004a48: 24078593 addi a1,a5,576 # f4240 + 3004a4c: 4529 li a0,10 + 3004a4e: 2805 jal ra,3004a7e + 3004a50: fdc42783 lw a5,-36(s0) + 3004a54: 4398 lw a4,0(a5) + 3004a56: 0d472783 lw a5,212(a4) + 3004a5a: 0017e793 ori a5,a5,1 + 3004a5e: 0cf72a23 sw a5,212(a4) + 3004a62: fdc42783 lw a5,-36(s0) + 3004a66: 4398 lw a4,0(a5) + 3004a68: 0d472783 lw a5,212(a4) + 3004a6c: eff7f793 andi a5,a5,-257 + 3004a70: 0cf72a23 sw a5,212(a4) + 3004a74: 0001 nop + 3004a76: 50b2 lw ra,44(sp) + 3004a78: 5422 lw s0,40(sp) + 3004a7a: 6145 addi sp,sp,48 + 3004a7c: 8082 ret + +03004a7e : + 3004a7e: 87ffc06f j 30012fc + +03004a82 : + 3004a82: 1101 addi sp,sp,-32 + 3004a84: ce06 sw ra,28(sp) + 3004a86: cc22 sw s0,24(sp) + 3004a88: 1000 addi s0,sp,32 + 3004a8a: fea42623 sw a0,-20(s0) + 3004a8e: fec42783 lw a5,-20(s0) + 3004a92: 439c lw a5,0(a5) + 3004a94: 0e07a783 lw a5,224(a5) + 3004a98: 83b5 srli a5,a5,0xd + 3004a9a: 8b85 andi a5,a5,1 + 3004a9c: 0ff7f713 andi a4,a5,255 + 3004aa0: 4785 li a5,1 + 3004aa2: 00f71e63 bne a4,a5,3004abe + 3004aa6: fec42503 lw a0,-20(s0) + 3004aaa: 354d jal ra,300494c + 3004aac: fec42783 lw a5,-20(s0) + 3004ab0: 4398 lw a4,0(a5) + 3004ab2: 0e072783 lw a5,224(a4) + 3004ab6: 6689 lui a3,0x2 + 3004ab8: 8fd5 or a5,a5,a3 + 3004aba: 0ef72023 sw a5,224(a4) + 3004abe: fec42783 lw a5,-20(s0) + 3004ac2: 47bc lw a5,72(a5) + 3004ac4: cb99 beqz a5,3004ada + 3004ac6: fec42783 lw a5,-20(s0) + 3004aca: 4bfc lw a5,84(a5) + 3004acc: c799 beqz a5,3004ada + 3004ace: fec42783 lw a5,-20(s0) + 3004ad2: 4bfc lw a5,84(a5) + 3004ad4: fec42503 lw a0,-20(s0) + 3004ad8: 9782 jalr a5 + 3004ada: fec42783 lw a5,-20(s0) + 3004ade: 439c lw a5,0(a5) + 3004ae0: 0e07a223 sw zero,228(a5) + 3004ae4: fec42783 lw a5,-20(s0) + 3004ae8: 439c lw a5,0(a5) + 3004aea: 01000737 lui a4,0x1000 + 3004aee: 177d addi a4,a4,-1 # ffffff + 3004af0: 0ee7a023 sw a4,224(a5) + 3004af4: fec42783 lw a5,-20(s0) + 3004af8: 4705 li a4,1 + 3004afa: c3f8 sw a4,68(a5) + 3004afc: 0001 nop + 3004afe: 40f2 lw ra,28(sp) + 3004b00: 4462 lw s0,24(sp) + 3004b02: 6105 addi sp,sp,32 + 3004b04: 8082 ret + +03004b06 : + 3004b06: 7179 addi sp,sp,-48 + 3004b08: d622 sw s0,44(sp) + 3004b0a: 1800 addi s0,sp,48 + 3004b0c: fca42e23 sw a0,-36(s0) + 3004b10: fcb42c23 sw a1,-40(s0) + 3004b14: fcc42a23 sw a2,-44(s0) + 3004b18: fe042623 sw zero,-20(s0) + 3004b1c: fe042423 sw zero,-24(s0) + 3004b20: fd842703 lw a4,-40(s0) + 3004b24: 4791 li a5,4 + 3004b26: 0ce7e263 bltu a5,a4,3004bea + 3004b2a: fd842783 lw a5,-40(s0) + 3004b2e: 00279713 slli a4,a5,0x2 + 3004b32: 030097b7 lui a5,0x3009 + 3004b36: a1878793 addi a5,a5,-1512 # 3008a18 + 3004b3a: 97ba add a5,a5,a4 + 3004b3c: 439c lw a5,0(a5) + 3004b3e: 8782 jr a5 + 3004b40: fdc42783 lw a5,-36(s0) + 3004b44: 439c lw a5,0(a5) + 3004b46: 0e07a703 lw a4,224(a5) + 3004b4a: 6785 lui a5,0x1 + 3004b4c: 20078793 addi a5,a5,512 # 1200 + 3004b50: 8ff9 and a5,a5,a4 + 3004b52: fef42423 sw a5,-24(s0) + 3004b56: fe842783 lw a5,-24(s0) + 3004b5a: fef42623 sw a5,-20(s0) + 3004b5e: a079 j 3004bec + 3004b60: fdc42783 lw a5,-36(s0) + 3004b64: 439c lw a5,0(a5) + 3004b66: 0dc7a783 lw a5,220(a5) + 3004b6a: 83f9 srli a5,a5,0x1e + 3004b6c: 8b85 andi a5,a5,1 + 3004b6e: 9f81 uxtb a5 + 3004b70: fef42623 sw a5,-20(s0) + 3004b74: a8a5 j 3004bec + 3004b76: fdc42783 lw a5,-36(s0) + 3004b7a: 439c lw a5,0(a5) + 3004b7c: 4f9c lw a5,24(a5) + 3004b7e: 8b85 andi a5,a5,1 + 3004b80: 9f81 uxtb a5 + 3004b82: 873e mv a4,a5 + 3004b84: fd442783 lw a5,-44(s0) + 3004b88: 8f99 sub a5,a5,a4 + 3004b8a: 0017b793 seqz a5,a5 + 3004b8e: 9f81 uxtb a5 + 3004b90: fef42423 sw a5,-24(s0) + 3004b94: fdc42783 lw a5,-36(s0) + 3004b98: 439c lw a5,0(a5) + 3004b9a: 0e07a783 lw a5,224(a5) + 3004b9e: 83d5 srli a5,a5,0x15 + 3004ba0: 8b85 andi a5,a5,1 + 3004ba2: 9f81 uxtb a5 + 3004ba4: 873e mv a4,a5 + 3004ba6: fe842783 lw a5,-24(s0) + 3004baa: 8fd9 or a5,a5,a4 + 3004bac: fef42423 sw a5,-24(s0) + 3004bb0: fe842783 lw a5,-24(s0) + 3004bb4: fef42623 sw a5,-20(s0) + 3004bb8: a815 j 3004bec + 3004bba: fdc42783 lw a5,-36(s0) + 3004bbe: 439c lw a5,0(a5) + 3004bc0: 0d87a783 lw a5,216(a5) + 3004bc4: 83a1 srli a5,a5,0x8 + 3004bc6: 8bfd andi a5,a5,31 + 3004bc8: 9f81 uxtb a5 + 3004bca: 0107b793 sltiu a5,a5,16 + 3004bce: 9f81 uxtb a5 + 3004bd0: fef42623 sw a5,-20(s0) + 3004bd4: a821 j 3004bec + 3004bd6: fdc42783 lw a5,-36(s0) + 3004bda: 439c lw a5,0(a5) + 3004bdc: 0d87a783 lw a5,216(a5) + 3004be0: 8bfd andi a5,a5,31 + 3004be2: 9f81 uxtb a5 + 3004be4: fef42623 sw a5,-20(s0) + 3004be8: a011 j 3004bec + 3004bea: 0001 nop + 3004bec: fec42783 lw a5,-20(s0) + 3004bf0: 853e mv a0,a5 + 3004bf2: 5432 lw s0,44(sp) + 3004bf4: 6145 addi sp,sp,48 + 3004bf6: 8082 ret + +03004bf8 : + 3004bf8: 7139 addi sp,sp,-64 + 3004bfa: 03010293 addi t0,sp,48 + 3004bfe: 0062928b stmia {ra,s0,s2-s3},(t0) + 3004c02: 0080 addi s0,sp,64 + 3004c04: fca42623 sw a0,-52(s0) + 3004c08: fcb42423 sw a1,-56(s0) + 3004c0c: fcc42223 sw a2,-60(s0) + 3004c10: e0efc0ef jal ra,300121e + 3004c14: fea42623 sw a0,-20(s0) + 3004c18: 4781 li a5,0 + 3004c1a: 4801 li a6,0 + 3004c1c: fef42023 sw a5,-32(s0) + 3004c20: ff042223 sw a6,-28(s0) + 3004c24: 14380537 lui a0,0x14380 + 3004c28: 943fd0ef jal ra,300256a + 3004c2c: 872a mv a4,a0 + 3004c2e: 3e800793 li a5,1000 + 3004c32: 02f75733 divu a4,a4,a5 + 3004c36: fcc42783 lw a5,-52(s0) + 3004c3a: 57dc lw a5,44(a5) + 3004c3c: 02f707b3 mul a5,a4,a5 + 3004c40: fcf42c23 sw a5,-40(s0) + 3004c44: fc042e23 sw zero,-36(s0) + 3004c48: fcc42783 lw a5,-52(s0) + 3004c4c: 439c lw a5,0(a5) + 3004c4e: 0e07a703 lw a4,224(a5) + 3004c52: 001017b7 lui a5,0x101 + 3004c56: 80178793 addi a5,a5,-2047 # 100801 + 3004c5a: 8ff9 and a5,a5,a4 + 3004c5c: c791 beqz a5,3004c68 + 3004c5e: fcc42503 lw a0,-52(s0) + 3004c62: 3505 jal ra,3004a82 + 3004c64: 4785 li a5,1 + 3004c66: a0d1 j 3004d2a + 3004c68: fc442603 lw a2,-60(s0) + 3004c6c: fc842583 lw a1,-56(s0) + 3004c70: fcc42503 lw a0,-52(s0) + 3004c74: 3d49 jal ra,3004b06 + 3004c76: 87aa mv a5,a0 + 3004c78: c395 beqz a5,3004c9c + 3004c7a: fc842703 lw a4,-56(s0) + 3004c7e: 4789 li a5,2 + 3004c80: 00f71c63 bne a4,a5,3004c98 + 3004c84: fcc42783 lw a5,-52(s0) + 3004c88: 4398 lw a4,0(a5) + 3004c8a: 0e072783 lw a5,224(a4) + 3004c8e: 002006b7 lui a3,0x200 + 3004c92: 8fd5 or a5,a5,a3 + 3004c94: 0ef72023 sw a5,224(a4) + 3004c98: 4781 li a5,0 + 3004c9a: a841 j 3004d2a + 3004c9c: d82fc0ef jal ra,300121e + 3004ca0: fca42a23 sw a0,-44(s0) + 3004ca4: fd442703 lw a4,-44(s0) + 3004ca8: fec42783 lw a5,-20(s0) + 3004cac: 00e7fb63 bgeu a5,a4,3004cc2 + 3004cb0: fd442703 lw a4,-44(s0) + 3004cb4: fec42783 lw a5,-20(s0) + 3004cb8: 40f707b3 sub a5,a4,a5 + 3004cbc: 893e mv s2,a5 + 3004cbe: 4981 li s3,0 + 3004cc0: a811 j 3004cd4 + 3004cc2: fd442703 lw a4,-44(s0) + 3004cc6: fec42783 lw a5,-20(s0) + 3004cca: 40f707b3 sub a5,a4,a5 + 3004cce: 17fd addi a5,a5,-1 + 3004cd0: 893e mv s2,a5 + 3004cd2: 4981 li s3,0 + 3004cd4: fe042683 lw a3,-32(s0) + 3004cd8: fe442703 lw a4,-28(s0) + 3004cdc: 012687b3 add a5,a3,s2 + 3004ce0: 863e mv a2,a5 + 3004ce2: 00d63633 sltu a2,a2,a3 + 3004ce6: 01370833 add a6,a4,s3 + 3004cea: 01060733 add a4,a2,a6 + 3004cee: 883a mv a6,a4 + 3004cf0: fef42023 sw a5,-32(s0) + 3004cf4: ff042223 sw a6,-28(s0) + 3004cf8: fdc42703 lw a4,-36(s0) + 3004cfc: fe442783 lw a5,-28(s0) + 3004d00: 00e7ee63 bltu a5,a4,3004d1c + 3004d04: fdc42703 lw a4,-36(s0) + 3004d08: fe442783 lw a5,-28(s0) + 3004d0c: 00f71d63 bne a4,a5,3004d26 + 3004d10: fd842703 lw a4,-40(s0) + 3004d14: fe042783 lw a5,-32(s0) + 3004d18: 00e7f763 bgeu a5,a4,3004d26 + 3004d1c: fd442783 lw a5,-44(s0) + 3004d20: fef42623 sw a5,-20(s0) + 3004d24: b715 j 3004c48 + 3004d26: 0001 nop + 3004d28: 478d li a5,3 + 3004d2a: 853e mv a0,a5 + 3004d2c: 03010293 addi t0,sp,48 + 3004d30: 0062828b ldmia {ra,s0,s2-s3},(t0) + 3004d34: 6121 addi sp,sp,64 + 3004d36: 8082 ret + +03004d38 : + 3004d38: 7179 addi sp,sp,-48 + 3004d3a: d606 sw ra,44(sp) + 3004d3c: d422 sw s0,40(sp) + 3004d3e: 1800 addi s0,sp,48 + 3004d40: fca42e23 sw a0,-36(s0) + 3004d44: fcb42c23 sw a1,-40(s0) + 3004d48: 87b2 mv a5,a2 + 3004d4a: fcf40ba3 sb a5,-41(s0) + 3004d4e: 4601 li a2,0 + 3004d50: 458d li a1,3 + 3004d52: fdc42503 lw a0,-36(s0) + 3004d56: 354d jal ra,3004bf8 + 3004d58: fea42623 sw a0,-20(s0) + 3004d5c: fec42783 lw a5,-20(s0) + 3004d60: c781 beqz a5,3004d68 + 3004d62: fec42783 lw a5,-20(s0) + 3004d66: a80d j 3004d98 + 3004d68: fd842783 lw a5,-40(s0) + 3004d6c: 00879713 slli a4,a5,0x8 + 3004d70: 6785 lui a5,0x1 + 3004d72: f0078793 addi a5,a5,-256 # f00 + 3004d76: 8ff9 and a5,a5,a4 + 3004d78: fef42423 sw a5,-24(s0) + 3004d7c: fd744783 lbu a5,-41(s0) + 3004d80: fe842703 lw a4,-24(s0) + 3004d84: 8fd9 or a5,a5,a4 + 3004d86: fef42423 sw a5,-24(s0) + 3004d8a: fdc42783 lw a5,-36(s0) + 3004d8e: 439c lw a5,0(a5) + 3004d90: fe842703 lw a4,-24(s0) + 3004d94: d398 sw a4,32(a5) + 3004d96: 4781 li a5,0 + 3004d98: 853e mv a0,a5 + 3004d9a: 50b2 lw ra,44(sp) + 3004d9c: 5422 lw s0,40(sp) + 3004d9e: 6145 addi sp,sp,48 + 3004da0: 8082 ret + +03004da2 : + 3004da2: 7179 addi sp,sp,-48 + 3004da4: d606 sw ra,44(sp) + 3004da6: d422 sw s0,40(sp) + 3004da8: 1800 addi s0,sp,48 + 3004daa: fca42e23 sw a0,-36(s0) + 3004dae: fcb42c23 sw a1,-40(s0) + 3004db2: fdc42783 lw a5,-36(s0) + 3004db6: 4798 lw a4,8(a5) + 3004db8: 4785 li a5,1 + 3004dba: 0af71c63 bne a4,a5,3004e72 + 3004dbe: fdc42783 lw a5,-36(s0) + 3004dc2: 579c lw a5,40(a5) + 3004dc4: ebb5 bnez a5,3004e38 + 3004dc6: 040007b7 lui a5,0x4000 + 3004dca: 49c78713 addi a4,a5,1180 # 400049c + 3004dce: fd842683 lw a3,-40(s0) + 3004dd2: 47b1 li a5,12 + 3004dd4: 02f687b3 mul a5,a3,a5 + 3004dd8: 97ba add a5,a5,a4 + 3004dda: 43dc lw a5,4(a5) + 3004ddc: 83a1 srli a5,a5,0x8 + 3004dde: fef407a3 sb a5,-17(s0) + 3004de2: fef44783 lbu a5,-17(s0) + 3004de6: 863e mv a2,a5 + 3004de8: 4589 li a1,2 + 3004dea: fdc42503 lw a0,-36(s0) + 3004dee: 37a9 jal ra,3004d38 + 3004df0: fea42423 sw a0,-24(s0) + 3004df4: fe842783 lw a5,-24(s0) + 3004df8: c781 beqz a5,3004e00 + 3004dfa: fe842783 lw a5,-24(s0) + 3004dfe: a07d j 3004eac + 3004e00: 040007b7 lui a5,0x4000 + 3004e04: 49c78713 addi a4,a5,1180 # 400049c + 3004e08: fd842683 lw a3,-40(s0) + 3004e0c: 47b1 li a5,12 + 3004e0e: 02f687b3 mul a5,a3,a5 + 3004e12: 97ba add a5,a5,a4 + 3004e14: 43dc lw a5,4(a5) + 3004e16: fef407a3 sb a5,-17(s0) + 3004e1a: fef44783 lbu a5,-17(s0) + 3004e1e: 863e mv a2,a5 + 3004e20: 4589 li a1,2 + 3004e22: fdc42503 lw a0,-36(s0) + 3004e26: 3f09 jal ra,3004d38 + 3004e28: fea42423 sw a0,-24(s0) + 3004e2c: fe842783 lw a5,-24(s0) + 3004e30: cfad beqz a5,3004eaa + 3004e32: fe842783 lw a5,-24(s0) + 3004e36: a89d j 3004eac + 3004e38: 040007b7 lui a5,0x4000 + 3004e3c: 49c78713 addi a4,a5,1180 # 400049c + 3004e40: fd842683 lw a3,-40(s0) + 3004e44: 47b1 li a5,12 + 3004e46: 02f687b3 mul a5,a3,a5 + 3004e4a: 97ba add a5,a5,a4 + 3004e4c: 43dc lw a5,4(a5) + 3004e4e: 83a1 srli a5,a5,0x8 + 3004e50: fef407a3 sb a5,-17(s0) + 3004e54: fef44783 lbu a5,-17(s0) + 3004e58: 863e mv a2,a5 + 3004e5a: 4589 li a1,2 + 3004e5c: fdc42503 lw a0,-36(s0) + 3004e60: 3de1 jal ra,3004d38 + 3004e62: fea42423 sw a0,-24(s0) + 3004e66: fe842783 lw a5,-24(s0) + 3004e6a: c3a1 beqz a5,3004eaa + 3004e6c: fe842783 lw a5,-24(s0) + 3004e70: a835 j 3004eac + 3004e72: 040007b7 lui a5,0x4000 + 3004e76: 49c78713 addi a4,a5,1180 # 400049c + 3004e7a: fd842683 lw a3,-40(s0) + 3004e7e: 47b1 li a5,12 + 3004e80: 02f687b3 mul a5,a3,a5 + 3004e84: 97ba add a5,a5,a4 + 3004e86: 43dc lw a5,4(a5) + 3004e88: fef407a3 sb a5,-17(s0) + 3004e8c: fef44783 lbu a5,-17(s0) + 3004e90: 863e mv a2,a5 + 3004e92: 4589 li a1,2 + 3004e94: fdc42503 lw a0,-36(s0) + 3004e98: 3545 jal ra,3004d38 + 3004e9a: fea42423 sw a0,-24(s0) + 3004e9e: fe842783 lw a5,-24(s0) + 3004ea2: c781 beqz a5,3004eaa + 3004ea4: fe842783 lw a5,-24(s0) + 3004ea8: a011 j 3004eac + 3004eaa: 4781 li a5,0 + 3004eac: 853e mv a0,a5 + 3004eae: 50b2 lw ra,44(sp) + 3004eb0: 5422 lw s0,40(sp) + 3004eb2: 6145 addi sp,sp,48 + 3004eb4: 8082 ret + +03004eb6 : + 3004eb6: 7179 addi sp,sp,-48 + 3004eb8: d606 sw ra,44(sp) + 3004eba: d422 sw s0,40(sp) + 3004ebc: 1800 addi s0,sp,48 + 3004ebe: fca42e23 sw a0,-36(s0) + 3004ec2: fcb42c23 sw a1,-40(s0) + 3004ec6: fdc42783 lw a5,-36(s0) + 3004eca: 4798 lw a4,8(a5) + 3004ecc: 4785 li a5,1 + 3004ece: 0af71d63 bne a4,a5,3004f88 + 3004ed2: fdc42783 lw a5,-36(s0) + 3004ed6: 579c lw a5,40(a5) + 3004ed8: ebbd bnez a5,3004f4e + 3004eda: 040007b7 lui a5,0x4000 + 3004ede: 49c78713 addi a4,a5,1180 # 400049c + 3004ee2: fd842683 lw a3,-40(s0) + 3004ee6: 47b1 li a5,12 + 3004ee8: 02f687b3 mul a5,a3,a5 + 3004eec: 97ba add a5,a5,a4 + 3004eee: 43dc lw a5,4(a5) + 3004ef0: 83e1 srli a5,a5,0x18 + 3004ef2: fef407a3 sb a5,-17(s0) + 3004ef6: fef44783 lbu a5,-17(s0) + 3004efa: 863e mv a2,a5 + 3004efc: 4589 li a1,2 + 3004efe: fdc42503 lw a0,-36(s0) + 3004f02: 3d1d jal ra,3004d38 + 3004f04: fea42423 sw a0,-24(s0) + 3004f08: fe842783 lw a5,-24(s0) + 3004f0c: c781 beqz a5,3004f14 + 3004f0e: fe842783 lw a5,-24(s0) + 3004f12: a84d j 3004fc4 + 3004f14: 040007b7 lui a5,0x4000 + 3004f18: 49c78713 addi a4,a5,1180 # 400049c + 3004f1c: fd842683 lw a3,-40(s0) + 3004f20: 47b1 li a5,12 + 3004f22: 02f687b3 mul a5,a3,a5 + 3004f26: 97ba add a5,a5,a4 + 3004f28: 43dc lw a5,4(a5) + 3004f2a: 83c1 srli a5,a5,0x10 + 3004f2c: fef407a3 sb a5,-17(s0) + 3004f30: fef44783 lbu a5,-17(s0) + 3004f34: 863e mv a2,a5 + 3004f36: 4589 li a1,2 + 3004f38: fdc42503 lw a0,-36(s0) + 3004f3c: 3bf5 jal ra,3004d38 + 3004f3e: fea42423 sw a0,-24(s0) + 3004f42: fe842783 lw a5,-24(s0) + 3004f46: cfb5 beqz a5,3004fc2 + 3004f48: fe842783 lw a5,-24(s0) + 3004f4c: a8a5 j 3004fc4 + 3004f4e: 040007b7 lui a5,0x4000 + 3004f52: 49c78713 addi a4,a5,1180 # 400049c + 3004f56: fd842683 lw a3,-40(s0) + 3004f5a: 47b1 li a5,12 + 3004f5c: 02f687b3 mul a5,a3,a5 + 3004f60: 97ba add a5,a5,a4 + 3004f62: 43dc lw a5,4(a5) + 3004f64: 83e1 srli a5,a5,0x18 + 3004f66: fef407a3 sb a5,-17(s0) + 3004f6a: fef44783 lbu a5,-17(s0) + 3004f6e: 863e mv a2,a5 + 3004f70: 4589 li a1,2 + 3004f72: fdc42503 lw a0,-36(s0) + 3004f76: 33c9 jal ra,3004d38 + 3004f78: fea42423 sw a0,-24(s0) + 3004f7c: fe842783 lw a5,-24(s0) + 3004f80: c3a9 beqz a5,3004fc2 + 3004f82: fe842783 lw a5,-24(s0) + 3004f86: a83d j 3004fc4 + 3004f88: 040007b7 lui a5,0x4000 + 3004f8c: 49c78713 addi a4,a5,1180 # 400049c + 3004f90: fd842683 lw a3,-40(s0) + 3004f94: 47b1 li a5,12 + 3004f96: 02f687b3 mul a5,a3,a5 + 3004f9a: 97ba add a5,a5,a4 + 3004f9c: 43dc lw a5,4(a5) + 3004f9e: 83c1 srli a5,a5,0x10 + 3004fa0: fef407a3 sb a5,-17(s0) + 3004fa4: fef44783 lbu a5,-17(s0) + 3004fa8: 863e mv a2,a5 + 3004faa: 4589 li a1,2 + 3004fac: fdc42503 lw a0,-36(s0) + 3004fb0: 3361 jal ra,3004d38 + 3004fb2: fea42423 sw a0,-24(s0) + 3004fb6: fe842783 lw a5,-24(s0) + 3004fba: c781 beqz a5,3004fc2 + 3004fbc: fe842783 lw a5,-24(s0) + 3004fc0: a011 j 3004fc4 + 3004fc2: 4781 li a5,0 + 3004fc4: 853e mv a0,a5 + 3004fc6: 50b2 lw ra,44(sp) + 3004fc8: 5422 lw s0,40(sp) + 3004fca: 6145 addi sp,sp,48 + 3004fcc: 8082 ret + +03004fce : + 3004fce: 7179 addi sp,sp,-48 + 3004fd0: d606 sw ra,44(sp) + 3004fd2: d422 sw s0,40(sp) + 3004fd4: 1800 addi s0,sp,48 + 3004fd6: fca42e23 sw a0,-36(s0) + 3004fda: fcb42c23 sw a1,-40(s0) + 3004fde: fdc42783 lw a5,-36(s0) + 3004fe2: 4398 lw a4,0(a5) + 3004fe4: 0d072783 lw a5,208(a4) + 3004fe8: cff7f793 andi a5,a5,-769 + 3004fec: 0cf72823 sw a5,208(a4) + 3004ff0: fdc42783 lw a5,-36(s0) + 3004ff4: 4398 lw a4,0(a5) + 3004ff6: 0d072783 lw a5,208(a4) + 3004ffa: 0047e793 ori a5,a5,4 + 3004ffe: 0cf72823 sw a5,208(a4) + 3005002: fdc42783 lw a5,-36(s0) + 3005006: 4398 lw a4,0(a5) + 3005008: 0d072783 lw a5,208(a4) + 300500c: 0087e793 ori a5,a5,8 + 3005010: 0cf72823 sw a5,208(a4) + 3005014: fdc42783 lw a5,-36(s0) + 3005018: 4398 lw a4,0(a5) + 300501a: fd842783 lw a5,-40(s0) + 300501e: 0017b793 seqz a5,a5 + 3005022: 0ff7f693 andi a3,a5,255 + 3005026: 0d072783 lw a5,208(a4) + 300502a: 8a85 andi a3,a3,1 + 300502c: 9bf9 andi a5,a5,-2 + 300502e: 8fd5 or a5,a5,a3 + 3005030: 0cf72823 sw a5,208(a4) + 3005034: fd842703 lw a4,-40(s0) + 3005038: 4785 li a5,1 + 300503a: 00f71463 bne a4,a5,3005042 + 300503e: 4781 li a5,0 + 3005040: a01d j 3005066 + 3005042: 4601 li a2,0 + 3005044: 4585 li a1,1 + 3005046: fdc42503 lw a0,-36(s0) + 300504a: 31fd jal ra,3004d38 + 300504c: fea42623 sw a0,-20(s0) + 3005050: fec42783 lw a5,-20(s0) + 3005054: c799 beqz a5,3005062 + 3005056: fdc42503 lw a0,-36(s0) + 300505a: 3425 jal ra,3004a82 + 300505c: fec42783 lw a5,-20(s0) + 3005060: a019 j 3005066 + 3005062: fec42783 lw a5,-20(s0) + 3005066: 853e mv a0,a5 + 3005068: 50b2 lw ra,44(sp) + 300506a: 5422 lw s0,40(sp) + 300506c: 6145 addi sp,sp,48 + 300506e: 8082 ret + +03005070 : + 3005070: 7179 addi sp,sp,-48 + 3005072: d606 sw ra,44(sp) + 3005074: d422 sw s0,40(sp) + 3005076: 1800 addi s0,sp,48 + 3005078: fca42e23 sw a0,-36(s0) + 300507c: 4601 li a2,0 + 300507e: 45bd li a1,15 + 3005080: fdc42503 lw a0,-36(s0) + 3005084: 3955 jal ra,3004d38 + 3005086: fea42623 sw a0,-20(s0) + 300508a: fec42783 lw a5,-20(s0) + 300508e: c799 beqz a5,300509c + 3005090: fdc42503 lw a0,-36(s0) + 3005094: 32fd jal ra,3004a82 + 3005096: fec42783 lw a5,-20(s0) + 300509a: a015 j 30050be + 300509c: 4601 li a2,0 + 300509e: 4581 li a1,0 + 30050a0: fdc42503 lw a0,-36(s0) + 30050a4: 3e91 jal ra,3004bf8 + 30050a6: fea42623 sw a0,-20(s0) + 30050aa: fdc42783 lw a5,-36(s0) + 30050ae: fec42703 lw a4,-20(s0) + 30050b2: c7b8 sw a4,72(a5) + 30050b4: fdc42503 lw a0,-36(s0) + 30050b8: 32e9 jal ra,3004a82 + 30050ba: fec42783 lw a5,-20(s0) + 30050be: 853e mv a0,a5 + 30050c0: 50b2 lw ra,44(sp) + 30050c2: 5422 lw s0,40(sp) + 30050c4: 6145 addi sp,sp,48 + 30050c6: 8082 ret + +030050c8 : + 30050c8: 7179 addi sp,sp,-48 + 30050ca: d606 sw ra,44(sp) + 30050cc: d422 sw s0,40(sp) + 30050ce: 1800 addi s0,sp,48 + 30050d0: fca42e23 sw a0,-36(s0) + 30050d4: fe042623 sw zero,-20(s0) + 30050d8: a859 j 300516e + 30050da: fdc42783 lw a5,-36(s0) + 30050de: 5798 lw a4,40(a5) + 30050e0: fdc42783 lw a5,-36(s0) + 30050e4: 53dc lw a5,36(a5) + 30050e6: 17fd addi a5,a5,-1 + 30050e8: 00f71a63 bne a4,a5,30050fc + 30050ec: 4601 li a2,0 + 30050ee: 4599 li a1,6 + 30050f0: fdc42503 lw a0,-36(s0) + 30050f4: 3191 jal ra,3004d38 + 30050f6: fea42623 sw a0,-20(s0) + 30050fa: a801 j 300510a + 30050fc: 4601 li a2,0 + 30050fe: 4595 li a1,5 + 3005100: fdc42503 lw a0,-36(s0) + 3005104: 3915 jal ra,3004d38 + 3005106: fea42623 sw a0,-20(s0) + 300510a: fec42783 lw a5,-20(s0) + 300510e: c799 beqz a5,300511c + 3005110: fdc42503 lw a0,-36(s0) + 3005114: 32bd jal ra,3004a82 + 3005116: fec42783 lw a5,-20(s0) + 300511a: a0a5 j 3005182 + 300511c: 4605 li a2,1 + 300511e: 4591 li a1,4 + 3005120: fdc42503 lw a0,-36(s0) + 3005124: 3cd1 jal ra,3004bf8 + 3005126: fea42623 sw a0,-20(s0) + 300512a: fec42783 lw a5,-20(s0) + 300512e: c799 beqz a5,300513c + 3005130: fdc42503 lw a0,-36(s0) + 3005134: 32b9 jal ra,3004a82 + 3005136: fec42783 lw a5,-20(s0) + 300513a: a0a1 j 3005182 + 300513c: fdc42783 lw a5,-36(s0) + 3005140: 4398 lw a4,0(a5) + 3005142: fdc42783 lw a5,-36(s0) + 3005146: 539c lw a5,32(a5) + 3005148: 5358 lw a4,36(a4) + 300514a: 9f01 uxtb a4 + 300514c: a398 sb a4,0(a5) + 300514e: fdc42783 lw a5,-36(s0) + 3005152: 539c lw a5,32(a5) + 3005154: 00178713 addi a4,a5,1 + 3005158: fdc42783 lw a5,-36(s0) + 300515c: d398 sw a4,32(a5) + 300515e: fdc42783 lw a5,-36(s0) + 3005162: 579c lw a5,40(a5) + 3005164: 00178713 addi a4,a5,1 + 3005168: fdc42783 lw a5,-36(s0) + 300516c: d798 sw a4,40(a5) + 300516e: fdc42783 lw a5,-36(s0) + 3005172: 5798 lw a4,40(a5) + 3005174: fdc42783 lw a5,-36(s0) + 3005178: 53dc lw a5,36(a5) + 300517a: f6f760e3 bltu a4,a5,30050da + 300517e: fec42783 lw a5,-20(s0) + 3005182: 853e mv a0,a5 + 3005184: 50b2 lw ra,44(sp) + 3005186: 5422 lw s0,40(sp) + 3005188: 6145 addi sp,sp,48 + 300518a: 8082 ret + +0300518c : + 300518c: 7179 addi sp,sp,-48 + 300518e: d606 sw ra,44(sp) + 3005190: d422 sw s0,40(sp) + 3005192: 1800 addi s0,sp,48 + 3005194: fca42e23 sw a0,-36(s0) + 3005198: a0b1 j 30051e4 + 300519a: fdc42783 lw a5,-36(s0) + 300519e: 539c lw a5,32(a5) + 30051a0: 239c lbu a5,0(a5) + 30051a2: 9f81 uxtb a5 + 30051a4: 863e mv a2,a5 + 30051a6: 4589 li a1,2 + 30051a8: fdc42503 lw a0,-36(s0) + 30051ac: 3671 jal ra,3004d38 + 30051ae: fea42623 sw a0,-20(s0) + 30051b2: fec42783 lw a5,-20(s0) + 30051b6: c799 beqz a5,30051c4 + 30051b8: fdc42503 lw a0,-36(s0) + 30051bc: 30d9 jal ra,3004a82 + 30051be: fec42783 lw a5,-20(s0) + 30051c2: a815 j 30051f6 + 30051c4: fdc42783 lw a5,-36(s0) + 30051c8: 539c lw a5,32(a5) + 30051ca: 00178713 addi a4,a5,1 + 30051ce: fdc42783 lw a5,-36(s0) + 30051d2: d398 sw a4,32(a5) + 30051d4: fdc42783 lw a5,-36(s0) + 30051d8: 579c lw a5,40(a5) + 30051da: 00178713 addi a4,a5,1 + 30051de: fdc42783 lw a5,-36(s0) + 30051e2: d798 sw a4,40(a5) + 30051e4: fdc42783 lw a5,-36(s0) + 30051e8: 5798 lw a4,40(a5) + 30051ea: fdc42783 lw a5,-36(s0) + 30051ee: 53dc lw a5,36(a5) + 30051f0: faf765e3 bltu a4,a5,300519a + 30051f4: 4781 li a5,0 + 30051f6: 853e mv a0,a5 + 30051f8: 50b2 lw ra,44(sp) + 30051fa: 5422 lw s0,40(sp) + 30051fc: 6145 addi sp,sp,48 + 30051fe: 8082 ret + +03005200 : + 3005200: 7139 addi sp,sp,-64 + 3005202: de06 sw ra,60(sp) + 3005204: dc22 sw s0,56(sp) + 3005206: 0080 addi s0,sp,64 + 3005208: fca42623 sw a0,-52(s0) + 300520c: fcc42783 lw a5,-52(s0) + 3005210: eb89 bnez a5,3005222 + 3005212: 4f400593 li a1,1268 + 3005216: 030097b7 lui a5,0x3009 + 300521a: 9fc78513 addi a0,a5,-1540 # 30089fc + 300521e: 2de1 jal ra,30058f6 + 3005220: a001 j 3005220 + 3005222: fcc42783 lw a5,-52(s0) + 3005226: 4398 lw a4,0(a5) + 3005228: 141007b7 lui a5,0x14100 + 300522c: 02f70163 beq a4,a5,300524e + 3005230: fcc42783 lw a5,-52(s0) + 3005234: 4398 lw a4,0(a5) + 3005236: 141017b7 lui a5,0x14101 + 300523a: 00f70a63 beq a4,a5,300524e + 300523e: 4f500593 li a1,1269 + 3005242: 030097b7 lui a5,0x3009 + 3005246: 9fc78513 addi a0,a5,-1540 # 30089fc + 300524a: 2575 jal ra,30058f6 + 300524c: a001 j 300524c + 300524e: fcc42783 lw a5,-52(s0) + 3005252: 439c lw a5,0(a5) + 3005254: 853e mv a0,a5 + 3005256: b14fd0ef jal ra,300256a + 300525a: fea42423 sw a0,-24(s0) + 300525e: fe842583 lw a1,-24(s0) + 3005262: fcc42503 lw a0,-52(s0) + 3005266: bf2ff0ef jal ra,3004658 + 300526a: 87aa mv a5,a0 + 300526c: c399 beqz a5,3005272 + 300526e: 4785 li a5,1 + 3005270: a4ad j 30054da + 3005272: fcc42783 lw a5,-52(s0) + 3005276: 4709 li a4,2 + 3005278: c3f8 sw a4,68(a5) + 300527a: fcc42783 lw a5,-52(s0) + 300527e: 439c lw a5,0(a5) + 3005280: 0e07a223 sw zero,228(a5) + 3005284: fcc42783 lw a5,-52(s0) + 3005288: 439c lw a5,0(a5) + 300528a: 01000737 lui a4,0x1000 + 300528e: 177d addi a4,a4,-1 # ffffff + 3005290: 0ee7a023 sw a4,224(a5) + 3005294: fcc42783 lw a5,-52(s0) + 3005298: 4fb4 lw a3,88(a5) + 300529a: fcc42783 lw a5,-52(s0) + 300529e: 4398 lw a4,0(a5) + 30052a0: 87b6 mv a5,a3 + 30052a2: 8bbd andi a5,a5,15 + 30052a4: 0ff7f693 andi a3,a5,255 + 30052a8: 10c72783 lw a5,268(a4) + 30052ac: 8abd andi a3,a3,15 + 30052ae: 9bc1 andi a5,a5,-16 + 30052b0: 8fd5 or a5,a5,a3 + 30052b2: 10f72623 sw a5,268(a4) + 30052b6: fcc42783 lw a5,-52(s0) + 30052ba: 4fbc lw a5,88(a5) + 30052bc: 07a5 addi a5,a5,9 + 30052be: fef42223 sw a5,-28(s0) + 30052c2: fcc42783 lw a5,-52(s0) + 30052c6: 4fbc lw a5,88(a5) + 30052c8: 07a1 addi a5,a5,8 + 30052ca: fef42023 sw a5,-32(s0) + 30052ce: fcc42783 lw a5,-52(s0) + 30052d2: 4bd8 lw a4,20(a5) + 30052d4: 67e1 lui a5,0x18 + 30052d6: 6a078793 addi a5,a5,1696 # 186a0 + 30052da: 02e7ee63 bltu a5,a4,3005316 + 30052de: fcc42783 lw a5,-52(s0) + 30052e2: 4bdc lw a5,20(a5) + 30052e4: 0786 slli a5,a5,0x1 + 30052e6: fe842703 lw a4,-24(s0) + 30052ea: 02f75733 divu a4,a4,a5 + 30052ee: fe042783 lw a5,-32(s0) + 30052f2: 40f707b3 sub a5,a4,a5 + 30052f6: fef42623 sw a5,-20(s0) + 30052fa: fec42783 lw a5,-20(s0) + 30052fe: fff78713 addi a4,a5,-1 + 3005302: 67c1 lui a5,0x10 + 3005304: 17fd addi a5,a5,-1 # ffff + 3005306: 8f7d and a4,a4,a5 + 3005308: fec42783 lw a5,-20(s0) + 300530c: 07c2 slli a5,a5,0x10 + 300530e: 8fd9 or a5,a5,a4 + 3005310: fef42623 sw a5,-20(s0) + 3005314: a8b9 j 3005372 + 3005316: fe842703 lw a4,-24(s0) + 300531a: 06400793 li a5,100 + 300531e: 02f75733 divu a4,a4,a5 + 3005322: 02400793 li a5,36 + 3005326: 02f70733 mul a4,a4,a5 + 300532a: fcc42783 lw a5,-52(s0) + 300532e: 4bdc lw a5,20(a5) + 3005330: 02f75733 divu a4,a4,a5 + 3005334: fe042783 lw a5,-32(s0) + 3005338: 40f707b3 sub a5,a4,a5 + 300533c: 07c2 slli a5,a5,0x10 + 300533e: fef42623 sw a5,-20(s0) + 3005342: fe842703 lw a4,-24(s0) + 3005346: 06400793 li a5,100 + 300534a: 02f757b3 divu a5,a4,a5 + 300534e: 00679713 slli a4,a5,0x6 + 3005352: fcc42783 lw a5,-52(s0) + 3005356: 4bdc lw a5,20(a5) + 3005358: 02f75733 divu a4,a4,a5 + 300535c: fe442783 lw a5,-28(s0) + 3005360: 8f1d sub a4,a4,a5 + 3005362: 67c1 lui a5,0x10 + 3005364: 17fd addi a5,a5,-1 # ffff + 3005366: 8ff9 and a5,a5,a4 + 3005368: fec42703 lw a4,-20(s0) + 300536c: 8fd9 or a5,a5,a4 + 300536e: fef42623 sw a5,-20(s0) + 3005372: fcc42783 lw a5,-52(s0) + 3005376: 439c lw a5,0(a5) + 3005378: fec42703 lw a4,-20(s0) + 300537c: c3d8 sw a4,4(a5) + 300537e: fcc42783 lw a5,-52(s0) + 3005382: 4b9c lw a5,16(a5) + 3005384: 07c2 slli a5,a5,0x10 + 3005386: fcf42e23 sw a5,-36(s0) + 300538a: fcc42783 lw a5,-52(s0) + 300538e: 4ffc lw a5,92(a5) + 3005390: 8bbd andi a5,a5,15 + 3005392: fdc42703 lw a4,-36(s0) + 3005396: 8fd9 or a5,a5,a4 + 3005398: fcf42c23 sw a5,-40(s0) + 300539c: fcc42783 lw a5,-52(s0) + 30053a0: 439c lw a5,0(a5) + 30053a2: fd842703 lw a4,-40(s0) + 30053a6: c798 sw a4,8(a5) + 30053a8: fcc42783 lw a5,-52(s0) + 30053ac: 5bd4 lw a3,52(a5) + 30053ae: fcc42783 lw a5,-52(s0) + 30053b2: 4398 lw a4,0(a5) + 30053b4: 87b6 mv a5,a3 + 30053b6: 8bbd andi a5,a5,15 + 30053b8: 0ff7f693 andi a3,a5,255 + 30053bc: 0c872783 lw a5,200(a4) + 30053c0: 8abd andi a3,a3,15 + 30053c2: 9bc1 andi a5,a5,-16 + 30053c4: 8fd5 or a5,a5,a3 + 30053c6: 0cf72423 sw a5,200(a4) + 30053ca: fcc42783 lw a5,-52(s0) + 30053ce: 5b94 lw a3,48(a5) + 30053d0: fcc42783 lw a5,-52(s0) + 30053d4: 4398 lw a4,0(a5) + 30053d6: 87b6 mv a5,a3 + 30053d8: 8bbd andi a5,a5,15 + 30053da: 0ff7f693 andi a3,a5,255 + 30053de: 0cc72783 lw a5,204(a4) + 30053e2: 8abd andi a3,a3,15 + 30053e4: 9bc1 andi a5,a5,-16 + 30053e6: 8fd5 or a5,a5,a3 + 30053e8: 0cf72623 sw a5,204(a4) + 30053ec: fcc42783 lw a5,-52(s0) + 30053f0: 43d4 lw a3,4(a5) + 30053f2: fcc42783 lw a5,-52(s0) + 30053f6: 4398 lw a4,0(a5) + 30053f8: 87b6 mv a5,a3 + 30053fa: 8b8d andi a5,a5,3 + 30053fc: 0ff7f693 andi a3,a5,255 + 3005400: 431c lw a5,0(a4) + 3005402: 8a8d andi a3,a3,3 + 3005404: 9bf1 andi a5,a5,-4 + 3005406: 8fd5 or a5,a5,a3 + 3005408: c31c sw a5,0(a4) + 300540a: fcc42783 lw a5,-52(s0) + 300540e: 4f94 lw a3,24(a5) + 3005410: fcc42783 lw a5,-52(s0) + 3005414: 4398 lw a4,0(a5) + 3005416: 87b6 mv a5,a3 + 3005418: 8b85 andi a5,a5,1 + 300541a: 0ff7f693 andi a3,a5,255 + 300541e: 431c lw a5,0(a4) + 3005420: 8a85 andi a3,a3,1 + 3005422: 0692 slli a3,a3,0x4 + 3005424: 9bbd andi a5,a5,-17 + 3005426: 8fd5 or a5,a5,a3 + 3005428: c31c sw a5,0(a4) + 300542a: fcc42783 lw a5,-52(s0) + 300542e: 43d8 lw a4,4(a5) + 3005430: 4789 li a5,2 + 3005432: 00f70863 beq a4,a5,3005442 + 3005436: fcc42783 lw a5,-52(s0) + 300543a: 43d8 lw a4,4(a5) + 300543c: 478d li a5,3 + 300543e: 08f71963 bne a4,a5,30054d0 + 3005442: fcc42783 lw a5,-52(s0) + 3005446: 47d4 lw a3,12(a5) + 3005448: fcc42783 lw a5,-52(s0) + 300544c: 4398 lw a4,0(a5) + 300544e: 87b6 mv a5,a3 + 3005450: 3ff7f793 andi a5,a5,1023 + 3005454: 01079693 slli a3,a5,0x10 + 3005458: 82c1 srli a3,a3,0x10 + 300545a: 475c lw a5,12(a4) + 300545c: 3ff6f693 andi a3,a3,1023 + 3005460: c007f793 andi a5,a5,-1024 + 3005464: 8fd5 or a5,a5,a3 + 3005466: c75c sw a5,12(a4) + 3005468: fcc42783 lw a5,-52(s0) + 300546c: 4fd4 lw a3,28(a5) + 300546e: fcc42783 lw a5,-52(s0) + 3005472: 4398 lw a4,0(a5) + 3005474: 87b6 mv a5,a3 + 3005476: 8b85 andi a5,a5,1 + 3005478: 0ff7f693 andi a3,a5,255 + 300547c: 475c lw a5,12(a4) + 300547e: 8a85 andi a3,a3,1 + 3005480: 06e2 slli a3,a3,0x18 + 3005482: ff000637 lui a2,0xff000 + 3005486: 167d addi a2,a2,-1 # feffffff + 3005488: 8ff1 and a5,a5,a2 + 300548a: 8fd5 or a5,a5,a3 + 300548c: c75c sw a5,12(a4) + 300548e: fcc42783 lw a5,-52(s0) + 3005492: 53b8 lw a4,96(a5) + 3005494: 4785 li a5,1 + 3005496: 02f71d63 bne a4,a5,30054d0 + 300549a: fcc42783 lw a5,-52(s0) + 300549e: 4398 lw a4,0(a5) + 30054a0: 4b1c lw a5,16(a4) + 30054a2: 004006b7 lui a3,0x400 + 30054a6: 8fd5 or a5,a5,a3 + 30054a8: cb1c sw a5,16(a4) + 30054aa: fcc42783 lw a5,-52(s0) + 30054ae: 53f4 lw a3,100(a5) + 30054b0: fcc42783 lw a5,-52(s0) + 30054b4: 4398 lw a4,0(a5) + 30054b6: 87b6 mv a5,a3 + 30054b8: 3ff7f793 andi a5,a5,1023 + 30054bc: 01079693 slli a3,a5,0x10 + 30054c0: 82c1 srli a3,a3,0x10 + 30054c2: 4b1c lw a5,16(a4) + 30054c4: 3ff6f693 andi a3,a3,1023 + 30054c8: c007f793 andi a5,a5,-1024 + 30054cc: 8fd5 or a5,a5,a3 + 30054ce: cb1c sw a5,16(a4) + 30054d0: fcc42783 lw a5,-52(s0) + 30054d4: 4705 li a4,1 + 30054d6: c3f8 sw a4,68(a5) + 30054d8: 4781 li a5,0 + 30054da: 853e mv a0,a5 + 30054dc: 50f2 lw ra,60(sp) + 30054de: 5462 lw s0,56(sp) + 30054e0: 6121 addi sp,sp,64 + 30054e2: 8082 ret + +030054e4 : + 30054e4: 7139 addi sp,sp,-64 + 30054e6: de06 sw ra,60(sp) + 30054e8: dc22 sw s0,56(sp) + 30054ea: 0080 addi s0,sp,64 + 30054ec: fca42e23 sw a0,-36(s0) + 30054f0: 87ae mv a5,a1 + 30054f2: fcc42a23 sw a2,-44(s0) + 30054f6: fcd42823 sw a3,-48(s0) + 30054fa: fce42623 sw a4,-52(s0) + 30054fe: fcf41d23 sh a5,-38(s0) + 3005502: fdc42783 lw a5,-36(s0) + 3005506: c781 beqz a5,300550e + 3005508: fd442783 lw a5,-44(s0) + 300550c: eb89 bnez a5,300551e + 300550e: 57b00593 li a1,1403 + 3005512: 030097b7 lui a5,0x3009 + 3005516: 9fc78513 addi a0,a5,-1540 # 30089fc + 300551a: 2ef1 jal ra,30058f6 + 300551c: a001 j 300551c + 300551e: fdc42783 lw a5,-36(s0) + 3005522: 4398 lw a4,0(a5) + 3005524: 141007b7 lui a5,0x14100 + 3005528: 02f70163 beq a4,a5,300554a + 300552c: fdc42783 lw a5,-36(s0) + 3005530: 4398 lw a4,0(a5) + 3005532: 141017b7 lui a5,0x14101 + 3005536: 00f70a63 beq a4,a5,300554a + 300553a: 57c00593 li a1,1404 + 300553e: 030097b7 lui a5,0x3009 + 3005542: 9fc78513 addi a0,a5,-1540 # 30089fc + 3005546: 2e45 jal ra,30058f6 + 3005548: a001 j 3005548 + 300554a: fda45703 lhu a4,-38(s0) + 300554e: 3ff00793 li a5,1023 + 3005552: 00e7fb63 bgeu a5,a4,3005568 + 3005556: 57d00593 li a1,1405 + 300555a: 030097b7 lui a5,0x3009 + 300555e: 9fc78513 addi a0,a5,-1540 # 30089fc + 3005562: 2e51 jal ra,30058f6 + 3005564: 4785 li a5,1 + 3005566: aaad j 30056e0 + 3005568: fd042783 lw a5,-48(s0) + 300556c: eb91 bnez a5,3005580 + 300556e: 57e00593 li a1,1406 + 3005572: 030097b7 lui a5,0x3009 + 3005576: 9fc78513 addi a0,a5,-1540 # 30089fc + 300557a: 2eb5 jal ra,30058f6 + 300557c: 4785 li a5,1 + 300557e: a28d j 30056e0 + 3005580: fcc42783 lw a5,-52(s0) + 3005584: eb91 bnez a5,3005598 + 3005586: 57f00593 li a1,1407 + 300558a: 030097b7 lui a5,0x3009 + 300558e: 9fc78513 addi a0,a5,-1540 # 30089fc + 3005592: 2695 jal ra,30058f6 + 3005594: 4785 li a5,1 + 3005596: a2a9 j 30056e0 + 3005598: fdc42783 lw a5,-36(s0) + 300559c: 43f8 lw a4,68(a5) + 300559e: 4785 li a5,1 + 30055a0: 00f70b63 beq a4,a5,30055b6 + 30055a4: 58000593 li a1,1408 + 30055a8: 030097b7 lui a5,0x3009 + 30055ac: 9fc78513 addi a0,a5,-1540 # 30089fc + 30055b0: 2699 jal ra,30058f6 + 30055b2: 4785 li a5,1 + 30055b4: a235 j 30056e0 + 30055b6: fe042623 sw zero,-20(s0) + 30055ba: fdc42783 lw a5,-36(s0) + 30055be: 439c lw a5,0(a5) + 30055c0: 0e07a223 sw zero,228(a5) + 30055c4: fdc42783 lw a5,-36(s0) + 30055c8: 439c lw a5,0(a5) + 30055ca: 01000737 lui a4,0x1000 + 30055ce: 177d addi a4,a4,-1 # ffffff + 30055d0: 0ee7a023 sw a4,224(a5) + 30055d4: fdc42783 lw a5,-36(s0) + 30055d8: 4398 lw a4,0(a5) + 30055da: ebf007b7 lui a5,0xebf00 + 30055de: 97ba add a5,a5,a4 + 30055e0: 00f037b3 snez a5,a5 + 30055e4: 9f81 uxtb a5 + 30055e6: fef42623 sw a5,-20(s0) + 30055ea: 4605 li a2,1 + 30055ec: 4585 li a1,1 + 30055ee: fdc42503 lw a0,-36(s0) + 30055f2: e06ff0ef jal ra,3004bf8 + 30055f6: fea42423 sw a0,-24(s0) + 30055fa: fe842783 lw a5,-24(s0) + 30055fe: cf89 beqz a5,3005618 + 3005600: fdc42783 lw a5,-36(s0) + 3005604: fe842703 lw a4,-24(s0) + 3005608: c7b8 sw a4,72(a5) + 300560a: fdc42503 lw a0,-36(s0) + 300560e: c74ff0ef jal ra,3004a82 + 3005612: fe842783 lw a5,-24(s0) + 3005616: a0e9 j 30056e0 + 3005618: fdc42783 lw a5,-36(s0) + 300561c: 4711 li a4,4 + 300561e: c3f8 sw a4,68(a5) + 3005620: fdc42783 lw a5,-36(s0) + 3005624: fd442703 lw a4,-44(s0) + 3005628: d398 sw a4,32(a5) + 300562a: fdc42783 lw a5,-36(s0) + 300562e: fd042703 lw a4,-48(s0) + 3005632: d3d8 sw a4,36(a5) + 3005634: fdc42783 lw a5,-36(s0) + 3005638: 0207a423 sw zero,40(a5) # ebf00028 + 300563c: fdc42783 lw a5,-36(s0) + 3005640: fcc42703 lw a4,-52(s0) + 3005644: d7d8 sw a4,44(a5) + 3005646: fda45783 lhu a5,-38(s0) + 300564a: 85be mv a1,a5 + 300564c: fdc42503 lw a0,-36(s0) + 3005650: a58ff0ef jal ra,30048a8 + 3005654: 4581 li a1,0 + 3005656: fdc42503 lw a0,-36(s0) + 300565a: 3a95 jal ra,3004fce + 300565c: fea42423 sw a0,-24(s0) + 3005660: fe842783 lw a5,-24(s0) + 3005664: cf89 beqz a5,300567e + 3005666: fdc42783 lw a5,-36(s0) + 300566a: fe842703 lw a4,-24(s0) + 300566e: c7b8 sw a4,72(a5) + 3005670: fdc42503 lw a0,-36(s0) + 3005674: c0eff0ef jal ra,3004a82 + 3005678: fe842783 lw a5,-24(s0) + 300567c: a095 j 30056e0 + 300567e: fec42583 lw a1,-20(s0) + 3005682: fdc42503 lw a0,-36(s0) + 3005686: 3805 jal ra,3004eb6 + 3005688: fea42423 sw a0,-24(s0) + 300568c: fe842783 lw a5,-24(s0) + 3005690: cf89 beqz a5,30056aa + 3005692: fdc42783 lw a5,-36(s0) + 3005696: fe842703 lw a4,-24(s0) + 300569a: c7b8 sw a4,72(a5) + 300569c: fdc42503 lw a0,-36(s0) + 30056a0: be2ff0ef jal ra,3004a82 + 30056a4: fe842783 lw a5,-24(s0) + 30056a8: a825 j 30056e0 + 30056aa: fdc42503 lw a0,-36(s0) + 30056ae: 3c29 jal ra,30050c8 + 30056b0: fea42423 sw a0,-24(s0) + 30056b4: fe842783 lw a5,-24(s0) + 30056b8: cf89 beqz a5,30056d2 + 30056ba: fdc42783 lw a5,-36(s0) + 30056be: fe842703 lw a4,-24(s0) + 30056c2: c7b8 sw a4,72(a5) + 30056c4: fdc42503 lw a0,-36(s0) + 30056c8: bbaff0ef jal ra,3004a82 + 30056cc: fe842783 lw a5,-24(s0) + 30056d0: a801 j 30056e0 + 30056d2: fdc42503 lw a0,-36(s0) + 30056d6: 3a69 jal ra,3005070 + 30056d8: fea42423 sw a0,-24(s0) + 30056dc: fe842783 lw a5,-24(s0) + 30056e0: 853e mv a0,a5 + 30056e2: 50f2 lw ra,60(sp) + 30056e4: 5462 lw s0,56(sp) + 30056e6: 6121 addi sp,sp,64 + 30056e8: 8082 ret + +030056ea : + 30056ea: 7139 addi sp,sp,-64 + 30056ec: de06 sw ra,60(sp) + 30056ee: dc22 sw s0,56(sp) + 30056f0: 0080 addi s0,sp,64 + 30056f2: fca42e23 sw a0,-36(s0) + 30056f6: 87ae mv a5,a1 + 30056f8: fcc42a23 sw a2,-44(s0) + 30056fc: fcd42823 sw a3,-48(s0) + 3005700: fce42623 sw a4,-52(s0) + 3005704: fcf41d23 sh a5,-38(s0) + 3005708: fdc42783 lw a5,-36(s0) + 300570c: c781 beqz a5,3005714 + 300570e: fd442783 lw a5,-44(s0) + 3005712: eb89 bnez a5,3005724 + 3005714: 5bf00593 li a1,1471 + 3005718: 030097b7 lui a5,0x3009 + 300571c: 9fc78513 addi a0,a5,-1540 # 30089fc + 3005720: 2ad9 jal ra,30058f6 + 3005722: a001 j 3005722 + 3005724: fdc42783 lw a5,-36(s0) + 3005728: 4398 lw a4,0(a5) + 300572a: 141007b7 lui a5,0x14100 + 300572e: 02f70163 beq a4,a5,3005750 + 3005732: fdc42783 lw a5,-36(s0) + 3005736: 4398 lw a4,0(a5) + 3005738: 141017b7 lui a5,0x14101 + 300573c: 00f70a63 beq a4,a5,3005750 + 3005740: 5c000593 li a1,1472 + 3005744: 030097b7 lui a5,0x3009 + 3005748: 9fc78513 addi a0,a5,-1540 # 30089fc + 300574c: 226d jal ra,30058f6 + 300574e: a001 j 300574e + 3005750: fda45703 lhu a4,-38(s0) + 3005754: 3ff00793 li a5,1023 + 3005758: 00e7fb63 bgeu a5,a4,300576e + 300575c: 5c100593 li a1,1473 + 3005760: 030097b7 lui a5,0x3009 + 3005764: 9fc78513 addi a0,a5,-1540 # 30089fc + 3005768: 2279 jal ra,30058f6 + 300576a: 4785 li a5,1 + 300576c: a241 j 30058ec + 300576e: fd042783 lw a5,-48(s0) + 3005772: eb91 bnez a5,3005786 + 3005774: 5c200593 li a1,1474 + 3005778: 030097b7 lui a5,0x3009 + 300577c: 9fc78513 addi a0,a5,-1540 # 30089fc + 3005780: 2a9d jal ra,30058f6 + 3005782: 4785 li a5,1 + 3005784: a2a5 j 30058ec + 3005786: fcc42783 lw a5,-52(s0) + 300578a: eb91 bnez a5,300579e + 300578c: 5c300593 li a1,1475 + 3005790: 030097b7 lui a5,0x3009 + 3005794: 9fc78513 addi a0,a5,-1540 # 30089fc + 3005798: 2ab9 jal ra,30058f6 + 300579a: 4785 li a5,1 + 300579c: aa81 j 30058ec + 300579e: fdc42783 lw a5,-36(s0) + 30057a2: 43f8 lw a4,68(a5) + 30057a4: 4785 li a5,1 + 30057a6: 00f70b63 beq a4,a5,30057bc + 30057aa: 5c400593 li a1,1476 + 30057ae: 030097b7 lui a5,0x3009 + 30057b2: 9fc78513 addi a0,a5,-1540 # 30089fc + 30057b6: 2281 jal ra,30058f6 + 30057b8: 4785 li a5,1 + 30057ba: aa0d j 30058ec + 30057bc: fe042623 sw zero,-20(s0) + 30057c0: fdc42783 lw a5,-36(s0) + 30057c4: 439c lw a5,0(a5) + 30057c6: 0e07a223 sw zero,228(a5) + 30057ca: fdc42783 lw a5,-36(s0) + 30057ce: 439c lw a5,0(a5) + 30057d0: 01000737 lui a4,0x1000 + 30057d4: 177d addi a4,a4,-1 # ffffff + 30057d6: 0ee7a023 sw a4,224(a5) + 30057da: fdc42783 lw a5,-36(s0) + 30057de: 4398 lw a4,0(a5) + 30057e0: ebf007b7 lui a5,0xebf00 + 30057e4: 97ba add a5,a5,a4 + 30057e6: 00f037b3 snez a5,a5 + 30057ea: 9f81 uxtb a5 + 30057ec: fef42423 sw a5,-24(s0) + 30057f0: fdc42783 lw a5,-36(s0) + 30057f4: 470d li a4,3 + 30057f6: c3f8 sw a4,68(a5) + 30057f8: fdc42783 lw a5,-36(s0) + 30057fc: fd442703 lw a4,-44(s0) + 3005800: d398 sw a4,32(a5) + 3005802: fdc42783 lw a5,-36(s0) + 3005806: fd042703 lw a4,-48(s0) + 300580a: d3d8 sw a4,36(a5) + 300580c: fdc42783 lw a5,-36(s0) + 3005810: 0207a423 sw zero,40(a5) # ebf00028 + 3005814: fdc42783 lw a5,-36(s0) + 3005818: fcc42703 lw a4,-52(s0) + 300581c: d7d8 sw a4,44(a5) + 300581e: fda45783 lhu a5,-38(s0) + 3005822: 85be mv a1,a5 + 3005824: fdc42503 lw a0,-36(s0) + 3005828: 880ff0ef jal ra,30048a8 + 300582c: 4609 li a2,2 + 300582e: 4585 li a1,1 + 3005830: fdc42503 lw a0,-36(s0) + 3005834: bc4ff0ef jal ra,3004bf8 + 3005838: fea42623 sw a0,-20(s0) + 300583c: fec42783 lw a5,-20(s0) + 3005840: cf89 beqz a5,300585a + 3005842: fdc42783 lw a5,-36(s0) + 3005846: fec42703 lw a4,-20(s0) + 300584a: c7b8 sw a4,72(a5) + 300584c: fdc42503 lw a0,-36(s0) + 3005850: a32ff0ef jal ra,3004a82 + 3005854: fec42783 lw a5,-20(s0) + 3005858: a851 j 30058ec + 300585a: 4581 li a1,0 + 300585c: fdc42503 lw a0,-36(s0) + 3005860: f6eff0ef jal ra,3004fce + 3005864: fea42623 sw a0,-20(s0) + 3005868: fec42783 lw a5,-20(s0) + 300586c: cf89 beqz a5,3005886 + 300586e: fdc42783 lw a5,-36(s0) + 3005872: fec42703 lw a4,-20(s0) + 3005876: c7b8 sw a4,72(a5) + 3005878: fdc42503 lw a0,-36(s0) + 300587c: a06ff0ef jal ra,3004a82 + 3005880: fec42783 lw a5,-20(s0) + 3005884: a0a5 j 30058ec + 3005886: fe842583 lw a1,-24(s0) + 300588a: fdc42503 lw a0,-36(s0) + 300588e: d14ff0ef jal ra,3004da2 + 3005892: fea42623 sw a0,-20(s0) + 3005896: fec42783 lw a5,-20(s0) + 300589a: cf89 beqz a5,30058b4 + 300589c: fdc42783 lw a5,-36(s0) + 30058a0: fec42703 lw a4,-20(s0) + 30058a4: c7b8 sw a4,72(a5) + 30058a6: fdc42503 lw a0,-36(s0) + 30058aa: 9d8ff0ef jal ra,3004a82 + 30058ae: fec42783 lw a5,-20(s0) + 30058b2: a82d j 30058ec + 30058b4: fdc42503 lw a0,-36(s0) + 30058b8: 38d1 jal ra,300518c + 30058ba: fea42623 sw a0,-20(s0) + 30058be: fec42783 lw a5,-20(s0) + 30058c2: cf89 beqz a5,30058dc + 30058c4: fdc42783 lw a5,-36(s0) + 30058c8: fec42703 lw a4,-20(s0) + 30058cc: c7b8 sw a4,72(a5) + 30058ce: fdc42503 lw a0,-36(s0) + 30058d2: 9b0ff0ef jal ra,3004a82 + 30058d6: fec42783 lw a5,-20(s0) + 30058da: a809 j 30058ec + 30058dc: fdc42503 lw a0,-36(s0) + 30058e0: f90ff0ef jal ra,3005070 + 30058e4: fea42623 sw a0,-20(s0) + 30058e8: fec42783 lw a5,-20(s0) + 30058ec: 853e mv a0,a5 + 30058ee: 50f2 lw ra,60(sp) + 30058f0: 5462 lw s0,56(sp) + 30058f2: 6121 addi sp,sp,64 + 30058f4: 8082 ret + +030058f6 : + 30058f6: 913fb06f j 3001208 + +030058fa : + 30058fa: 1101 addi sp,sp,-32 + 30058fc: ce06 sw ra,28(sp) + 30058fe: cc22 sw s0,24(sp) + 3005900: 1000 addi s0,sp,32 + 3005902: fea42623 sw a0,-20(s0) + 3005906: feb42423 sw a1,-24(s0) + 300590a: fec42703 lw a4,-20(s0) + 300590e: 77c1 lui a5,0xffff0 + 3005910: 8f7d and a4,a4,a5 + 3005912: 147f07b7 lui a5,0x147f0 + 3005916: 00f70a63 beq a4,a5,300592a + 300591a: 08b00593 li a1,139 + 300591e: 030097b7 lui a5,0x3009 + 3005922: a2c78513 addi a0,a5,-1492 # 3008a2c + 3005926: 3fc1 jal ra,30058f6 + 3005928: a001 j 3005928 + 300592a: fec42783 lw a5,-20(s0) + 300592e: fe842703 lw a4,-24(s0) + 3005932: c398 sw a4,0(a5) + 3005934: 0001 nop + 3005936: 40f2 lw ra,28(sp) + 3005938: 4462 lw s0,24(sp) + 300593a: 6105 addi sp,sp,32 + 300593c: 8082 ret + +0300593e : + 300593e: 1101 addi sp,sp,-32 + 3005940: ce06 sw ra,28(sp) + 3005942: cc22 sw s0,24(sp) + 3005944: 1000 addi s0,sp,32 + 3005946: fea42623 sw a0,-20(s0) + 300594a: feb42423 sw a1,-24(s0) + 300594e: fec42703 lw a4,-20(s0) + 3005952: 77c1 lui a5,0xffff0 + 3005954: 8f7d and a4,a4,a5 + 3005956: 147f07b7 lui a5,0x147f0 + 300595a: 00f70a63 beq a4,a5,300596e + 300595e: 0ba00593 li a1,186 + 3005962: 030097b7 lui a5,0x3009 + 3005966: a2c78513 addi a0,a5,-1492 # 3008a2c + 300596a: 3771 jal ra,30058f6 + 300596c: a001 j 300596c + 300596e: fe842703 lw a4,-24(s0) + 3005972: 478d li a5,3 + 3005974: 00e7fa63 bgeu a5,a4,3005988 + 3005978: 0bb00593 li a1,187 + 300597c: 030097b7 lui a5,0x3009 + 3005980: a2c78513 addi a0,a5,-1492 # 3008a2c + 3005984: 3f8d jal ra,30058f6 + 3005986: a839 j 30059a4 + 3005988: fe842783 lw a5,-24(s0) + 300598c: 8b8d andi a5,a5,3 + 300598e: 0ff7f693 andi a3,a5,255 + 3005992: fec42703 lw a4,-20(s0) + 3005996: 431c lw a5,0(a4) + 3005998: 8a8d andi a3,a3,3 + 300599a: 0692 slli a3,a3,0x4 + 300599c: fcf7f793 andi a5,a5,-49 + 30059a0: 8fd5 or a5,a5,a3 + 30059a2: c31c sw a5,0(a4) + 30059a4: 40f2 lw ra,28(sp) + 30059a6: 4462 lw s0,24(sp) + 30059a8: 6105 addi sp,sp,32 + 30059aa: 8082 ret + +030059ac : + 30059ac: 1101 addi sp,sp,-32 + 30059ae: ce06 sw ra,28(sp) + 30059b0: cc22 sw s0,24(sp) + 30059b2: 1000 addi s0,sp,32 + 30059b4: fea42623 sw a0,-20(s0) + 30059b8: feb42423 sw a1,-24(s0) + 30059bc: fec42703 lw a4,-20(s0) + 30059c0: 77c1 lui a5,0xffff0 + 30059c2: 8f7d and a4,a4,a5 + 30059c4: 147f07b7 lui a5,0x147f0 + 30059c8: 00f70a63 beq a4,a5,30059dc + 30059cc: 0d200593 li a1,210 + 30059d0: 030097b7 lui a5,0x3009 + 30059d4: a2c78513 addi a0,a5,-1492 # 3008a2c + 30059d8: 3f39 jal ra,30058f6 + 30059da: a001 j 30059da + 30059dc: fe842703 lw a4,-24(s0) + 30059e0: 478d li a5,3 + 30059e2: 00e7fa63 bgeu a5,a4,30059f6 + 30059e6: 0d300593 li a1,211 + 30059ea: 030097b7 lui a5,0x3009 + 30059ee: a2c78513 addi a0,a5,-1492 # 3008a2c + 30059f2: 3711 jal ra,30058f6 + 30059f4: a835 j 3005a30 + 30059f6: fe842783 lw a5,-24(s0) + 30059fa: 8385 srli a5,a5,0x1 + 30059fc: 8b85 andi a5,a5,1 + 30059fe: 0ff7f693 andi a3,a5,255 + 3005a02: fec42703 lw a4,-20(s0) + 3005a06: 431c lw a5,0(a4) + 3005a08: 8a85 andi a3,a3,1 + 3005a0a: 06a2 slli a3,a3,0x8 + 3005a0c: eff7f793 andi a5,a5,-257 + 3005a10: 8fd5 or a5,a5,a3 + 3005a12: c31c sw a5,0(a4) + 3005a14: fe842783 lw a5,-24(s0) + 3005a18: 8b85 andi a5,a5,1 + 3005a1a: 0ff7f693 andi a3,a5,255 + 3005a1e: fec42703 lw a4,-20(s0) + 3005a22: 431c lw a5,0(a4) + 3005a24: 8a85 andi a3,a3,1 + 3005a26: 069e slli a3,a3,0x7 + 3005a28: f7f7f793 andi a5,a5,-129 + 3005a2c: 8fd5 or a5,a5,a3 + 3005a2e: c31c sw a5,0(a4) + 3005a30: 40f2 lw ra,28(sp) + 3005a32: 4462 lw s0,24(sp) + 3005a34: 6105 addi sp,sp,32 + 3005a36: 8082 ret + +03005a38 : + 3005a38: 1101 addi sp,sp,-32 + 3005a3a: ce06 sw ra,28(sp) + 3005a3c: cc22 sw s0,24(sp) + 3005a3e: 1000 addi s0,sp,32 + 3005a40: fea42623 sw a0,-20(s0) + 3005a44: feb42423 sw a1,-24(s0) + 3005a48: fec42703 lw a4,-20(s0) + 3005a4c: 77c1 lui a5,0xffff0 + 3005a4e: 8f7d and a4,a4,a5 + 3005a50: 147f07b7 lui a5,0x147f0 + 3005a54: 00f70a63 beq a4,a5,3005a68 + 3005a58: 0ed00593 li a1,237 + 3005a5c: 030097b7 lui a5,0x3009 + 3005a60: a2c78513 addi a0,a5,-1492 # 3008a2c + 3005a64: 3d49 jal ra,30058f6 + 3005a66: a001 j 3005a66 + 3005a68: fe842703 lw a4,-24(s0) + 3005a6c: 4785 li a5,1 + 3005a6e: 00e7fa63 bgeu a5,a4,3005a82 + 3005a72: 0ee00593 li a1,238 + 3005a76: 030097b7 lui a5,0x3009 + 3005a7a: a2c78513 addi a0,a5,-1492 # 3008a2c + 3005a7e: 3da5 jal ra,30058f6 + 3005a80: a839 j 3005a9e + 3005a82: fe842783 lw a5,-24(s0) + 3005a86: 8b85 andi a5,a5,1 + 3005a88: 0ff7f693 andi a3,a5,255 + 3005a8c: fec42703 lw a4,-20(s0) + 3005a90: 431c lw a5,0(a4) + 3005a92: 8a85 andi a3,a3,1 + 3005a94: 06a6 slli a3,a3,0x9 + 3005a96: dff7f793 andi a5,a5,-513 + 3005a9a: 8fd5 or a5,a5,a3 + 3005a9c: c31c sw a5,0(a4) + 3005a9e: 40f2 lw ra,28(sp) + 3005aa0: 4462 lw s0,24(sp) + 3005aa2: 6105 addi sp,sp,32 + 3005aa4: 8082 ret + +03005aa6 : + 3005aa6: 1101 addi sp,sp,-32 + 3005aa8: ce06 sw ra,28(sp) + 3005aaa: cc22 sw s0,24(sp) + 3005aac: 1000 addi s0,sp,32 + 3005aae: fea42623 sw a0,-20(s0) + 3005ab2: feb42423 sw a1,-24(s0) + 3005ab6: fec42703 lw a4,-20(s0) + 3005aba: 77c1 lui a5,0xffff0 + 3005abc: 8f7d and a4,a4,a5 + 3005abe: 147f07b7 lui a5,0x147f0 + 3005ac2: 00f70a63 beq a4,a5,3005ad6 + 3005ac6: 10500593 li a1,261 + 3005aca: 030097b7 lui a5,0x3009 + 3005ace: a2c78513 addi a0,a5,-1492 # 3008a2c + 3005ad2: 3515 jal ra,30058f6 + 3005ad4: a001 j 3005ad4 + 3005ad6: fe842703 lw a4,-24(s0) + 3005ada: 4785 li a5,1 + 3005adc: 00e7fa63 bgeu a5,a4,3005af0 + 3005ae0: 10600593 li a1,262 + 3005ae4: 030097b7 lui a5,0x3009 + 3005ae8: a2c78513 addi a0,a5,-1492 # 3008a2c + 3005aec: 3529 jal ra,30058f6 + 3005aee: a839 j 3005b0c + 3005af0: fe842783 lw a5,-24(s0) + 3005af4: 8b85 andi a5,a5,1 + 3005af6: 0ff7f693 andi a3,a5,255 + 3005afa: fec42703 lw a4,-20(s0) + 3005afe: 431c lw a5,0(a4) + 3005b00: 8a85 andi a3,a3,1 + 3005b02: 06aa slli a3,a3,0xa + 3005b04: bff7f793 andi a5,a5,-1025 + 3005b08: 8fd5 or a5,a5,a3 + 3005b0a: c31c sw a5,0(a4) + 3005b0c: 40f2 lw ra,28(sp) + 3005b0e: 4462 lw s0,24(sp) + 3005b10: 6105 addi sp,sp,32 + 3005b12: 8082 ret + +03005b14 : + 3005b14: 7179 addi sp,sp,-48 + 3005b16: d622 sw s0,44(sp) + 3005b18: 1800 addi s0,sp,48 + 3005b1a: fca42e23 sw a0,-36(s0) + 3005b1e: 147f07b7 lui a5,0x147f0 + 3005b22: fef42623 sw a5,-20(s0) + 3005b26: fdc42783 lw a5,-36(s0) + 3005b2a: 0107d713 srli a4,a5,0x10 + 3005b2e: 6785 lui a5,0x1 + 3005b30: 17fd addi a5,a5,-1 # fff + 3005b32: 8ff9 and a5,a5,a4 + 3005b34: fef42423 sw a5,-24(s0) + 3005b38: fec42703 lw a4,-20(s0) + 3005b3c: fe842783 lw a5,-24(s0) + 3005b40: 97ba add a5,a5,a4 + 3005b42: fef42223 sw a5,-28(s0) + 3005b46: fe442703 lw a4,-28(s0) + 3005b4a: 77c1 lui a5,0xffff0 + 3005b4c: 8f7d and a4,a4,a5 + 3005b4e: 147f07b7 lui a5,0x147f0 + 3005b52: 00f70463 beq a4,a5,3005b5a + 3005b56: 4781 li a5,0 + 3005b58: a019 j 3005b5e + 3005b5a: fe442783 lw a5,-28(s0) + 3005b5e: 853e mv a0,a5 + 3005b60: 5432 lw s0,44(sp) + 3005b62: 6145 addi sp,sp,48 + 3005b64: 8082 ret + +03005b66 : + 3005b66: 7179 addi sp,sp,-48 + 3005b68: d606 sw ra,44(sp) + 3005b6a: d422 sw s0,40(sp) + 3005b6c: 1800 addi s0,sp,48 + 3005b6e: fca42e23 sw a0,-36(s0) + 3005b72: fdc42503 lw a0,-36(s0) + 3005b76: 3f79 jal ra,3005b14 + 3005b78: fea42623 sw a0,-20(s0) + 3005b7c: fdc42703 lw a4,-36(s0) + 3005b80: 67c1 lui a5,0x10 + 3005b82: 17fd addi a5,a5,-1 # ffff + 3005b84: 8ff9 and a5,a5,a4 + 3005b86: fef42423 sw a5,-24(s0) + 3005b8a: fe842583 lw a1,-24(s0) + 3005b8e: fec42503 lw a0,-20(s0) + 3005b92: 33a5 jal ra,30058fa + 3005b94: 4781 li a5,0 + 3005b96: 853e mv a0,a5 + 3005b98: 50b2 lw ra,44(sp) + 3005b9a: 5422 lw s0,40(sp) + 3005b9c: 6145 addi sp,sp,48 + 3005b9e: 8082 ret + +03005ba0 : + 3005ba0: 7179 addi sp,sp,-48 + 3005ba2: d606 sw ra,44(sp) + 3005ba4: d422 sw s0,40(sp) + 3005ba6: 1800 addi s0,sp,48 + 3005ba8: fca42e23 sw a0,-36(s0) + 3005bac: fcb42c23 sw a1,-40(s0) + 3005bb0: fd842703 lw a4,-40(s0) + 3005bb4: 478d li a5,3 + 3005bb6: 00e7fb63 bgeu a5,a4,3005bcc + 3005bba: 07800593 li a1,120 + 3005bbe: 030097b7 lui a5,0x3009 + 3005bc2: a4c78513 addi a0,a5,-1460 # 3008a4c + 3005bc6: 3b05 jal ra,30058f6 + 3005bc8: 4791 li a5,4 + 3005bca: a821 j 3005be2 + 3005bcc: fdc42503 lw a0,-36(s0) + 3005bd0: 3791 jal ra,3005b14 + 3005bd2: fea42623 sw a0,-20(s0) + 3005bd6: fd842583 lw a1,-40(s0) + 3005bda: fec42503 lw a0,-20(s0) + 3005bde: 33f9 jal ra,30059ac + 3005be0: 4781 li a5,0 + 3005be2: 853e mv a0,a5 + 3005be4: 50b2 lw ra,44(sp) + 3005be6: 5422 lw s0,40(sp) + 3005be8: 6145 addi sp,sp,48 + 3005bea: 8082 ret + +03005bec : + 3005bec: 7179 addi sp,sp,-48 + 3005bee: d606 sw ra,44(sp) + 3005bf0: d422 sw s0,40(sp) + 3005bf2: 1800 addi s0,sp,48 + 3005bf4: fca42e23 sw a0,-36(s0) + 3005bf8: fcb42c23 sw a1,-40(s0) + 3005bfc: fd842703 lw a4,-40(s0) + 3005c00: 4785 li a5,1 + 3005c02: 00e7fb63 bgeu a5,a4,3005c18 + 3005c06: 09300593 li a1,147 + 3005c0a: 030097b7 lui a5,0x3009 + 3005c0e: a4c78513 addi a0,a5,-1460 # 3008a4c + 3005c12: 31d5 jal ra,30058f6 + 3005c14: 4791 li a5,4 + 3005c16: a821 j 3005c2e + 3005c18: fdc42503 lw a0,-36(s0) + 3005c1c: 3de5 jal ra,3005b14 + 3005c1e: fea42623 sw a0,-20(s0) + 3005c22: fd842583 lw a1,-40(s0) + 3005c26: fec42503 lw a0,-20(s0) + 3005c2a: 3db5 jal ra,3005aa6 + 3005c2c: 4781 li a5,0 + 3005c2e: 853e mv a0,a5 + 3005c30: 50b2 lw ra,44(sp) + 3005c32: 5422 lw s0,40(sp) + 3005c34: 6145 addi sp,sp,48 + 3005c36: 8082 ret + +03005c38 : + 3005c38: 7179 addi sp,sp,-48 + 3005c3a: d606 sw ra,44(sp) + 3005c3c: d422 sw s0,40(sp) + 3005c3e: 1800 addi s0,sp,48 + 3005c40: fca42e23 sw a0,-36(s0) + 3005c44: fcb42c23 sw a1,-40(s0) + 3005c48: fd842703 lw a4,-40(s0) + 3005c4c: 4785 li a5,1 + 3005c4e: 00e7fb63 bgeu a5,a4,3005c64 + 3005c52: 0ae00593 li a1,174 + 3005c56: 030097b7 lui a5,0x3009 + 3005c5a: a4c78513 addi a0,a5,-1460 # 3008a4c + 3005c5e: 3961 jal ra,30058f6 + 3005c60: 4791 li a5,4 + 3005c62: a821 j 3005c7a + 3005c64: fdc42503 lw a0,-36(s0) + 3005c68: 3575 jal ra,3005b14 + 3005c6a: fea42623 sw a0,-20(s0) + 3005c6e: fd842583 lw a1,-40(s0) + 3005c72: fec42503 lw a0,-20(s0) + 3005c76: 33c9 jal ra,3005a38 + 3005c78: 4781 li a5,0 + 3005c7a: 853e mv a0,a5 + 3005c7c: 50b2 lw ra,44(sp) + 3005c7e: 5422 lw s0,40(sp) + 3005c80: 6145 addi sp,sp,48 + 3005c82: 8082 ret + +03005c84 : + 3005c84: 7179 addi sp,sp,-48 + 3005c86: d606 sw ra,44(sp) + 3005c88: d422 sw s0,40(sp) + 3005c8a: 1800 addi s0,sp,48 + 3005c8c: fca42e23 sw a0,-36(s0) + 3005c90: fcb42c23 sw a1,-40(s0) + 3005c94: fd842703 lw a4,-40(s0) + 3005c98: 478d li a5,3 + 3005c9a: 00e7fb63 bgeu a5,a4,3005cb0 + 3005c9e: 0cb00593 li a1,203 + 3005ca2: 030097b7 lui a5,0x3009 + 3005ca6: a4c78513 addi a0,a5,-1460 # 3008a4c + 3005caa: 31b1 jal ra,30058f6 + 3005cac: 4791 li a5,4 + 3005cae: a821 j 3005cc6 + 3005cb0: fdc42503 lw a0,-36(s0) + 3005cb4: 3585 jal ra,3005b14 + 3005cb6: fea42623 sw a0,-20(s0) + 3005cba: fd842583 lw a1,-40(s0) + 3005cbe: fec42503 lw a0,-20(s0) + 3005cc2: 39b5 jal ra,300593e + 3005cc4: 4781 li a5,0 + 3005cc6: 853e mv a0,a5 + 3005cc8: 50b2 lw ra,44(sp) + 3005cca: 5422 lw s0,40(sp) + 3005ccc: 6145 addi sp,sp,48 + 3005cce: 8082 ret + +03005cd0 : + 3005cd0: 1101 addi sp,sp,-32 + 3005cd2: ce22 sw s0,28(sp) + 3005cd4: 1000 addi s0,sp,32 + 3005cd6: fea42623 sw a0,-20(s0) + 3005cda: fec42783 lw a5,-20(s0) + 3005cde: cb99 beqz a5,3005cf4 + 3005ce0: fec42703 lw a4,-20(s0) + 3005ce4: 4785 li a5,1 + 3005ce6: 00f70763 beq a4,a5,3005cf4 + 3005cea: fec42703 lw a4,-20(s0) + 3005cee: 4789 li a5,2 + 3005cf0: 00f71463 bne a4,a5,3005cf8 + 3005cf4: 4785 li a5,1 + 3005cf6: a011 j 3005cfa + 3005cf8: 4781 li a5,0 + 3005cfa: 8b85 andi a5,a5,1 + 3005cfc: 9f81 uxtb a5 + 3005cfe: 853e mv a0,a5 + 3005d00: 4472 lw s0,28(sp) + 3005d02: 6105 addi sp,sp,32 + 3005d04: 8082 ret + +03005d06 : + 3005d06: 1101 addi sp,sp,-32 + 3005d08: ce22 sw s0,28(sp) + 3005d0a: 1000 addi s0,sp,32 + 3005d0c: fea42623 sw a0,-20(s0) + 3005d10: fec42783 lw a5,-20(s0) + 3005d14: c791 beqz a5,3005d20 + 3005d16: fec42703 lw a4,-20(s0) + 3005d1a: 4785 li a5,1 + 3005d1c: 00f71463 bne a4,a5,3005d24 + 3005d20: 4785 li a5,1 + 3005d22: a011 j 3005d26 + 3005d24: 4781 li a5,0 + 3005d26: 8b85 andi a5,a5,1 + 3005d28: 9f81 uxtb a5 + 3005d2a: 853e mv a0,a5 + 3005d2c: 4472 lw s0,28(sp) + 3005d2e: 6105 addi sp,sp,32 + 3005d30: 8082 ret + +03005d32 : + 3005d32: 1101 addi sp,sp,-32 + 3005d34: ce22 sw s0,28(sp) + 3005d36: 1000 addi s0,sp,32 + 3005d38: fea42623 sw a0,-20(s0) + 3005d3c: fec42783 lw a5,-20(s0) + 3005d40: c791 beqz a5,3005d4c + 3005d42: fec42703 lw a4,-20(s0) + 3005d46: 4785 li a5,1 + 3005d48: 00f71463 bne a4,a5,3005d50 + 3005d4c: 4785 li a5,1 + 3005d4e: a011 j 3005d52 + 3005d50: 4781 li a5,0 + 3005d52: 8b85 andi a5,a5,1 + 3005d54: 9f81 uxtb a5 + 3005d56: 853e mv a0,a5 + 3005d58: 4472 lw s0,28(sp) + 3005d5a: 6105 addi sp,sp,32 + 3005d5c: 8082 ret + +03005d5e : + 3005d5e: 1101 addi sp,sp,-32 + 3005d60: ce22 sw s0,28(sp) + 3005d62: 1000 addi s0,sp,32 + 3005d64: fea42623 sw a0,-20(s0) + 3005d68: fec42783 lw a5,-20(s0) + 3005d6c: 00f037b3 snez a5,a5 + 3005d70: 9f81 uxtb a5 + 3005d72: 853e mv a0,a5 + 3005d74: 4472 lw s0,28(sp) + 3005d76: 6105 addi sp,sp,32 + 3005d78: 8082 ret + +03005d7a : + 3005d7a: 1101 addi sp,sp,-32 + 3005d7c: ce22 sw s0,28(sp) + 3005d7e: 1000 addi s0,sp,32 + 3005d80: fea42623 sw a0,-20(s0) + 3005d84: fec42783 lw a5,-20(s0) + 3005d88: cb99 beqz a5,3005d9e + 3005d8a: fec42703 lw a4,-20(s0) + 3005d8e: 4785 li a5,1 + 3005d90: 00f70763 beq a4,a5,3005d9e + 3005d94: fec42703 lw a4,-20(s0) + 3005d98: 4789 li a5,2 + 3005d9a: 00f71463 bne a4,a5,3005da2 + 3005d9e: 4785 li a5,1 + 3005da0: a011 j 3005da4 + 3005da2: 4781 li a5,0 + 3005da4: 8b85 andi a5,a5,1 + 3005da6: 9f81 uxtb a5 + 3005da8: 853e mv a0,a5 + 3005daa: 4472 lw s0,28(sp) + 3005dac: 6105 addi sp,sp,32 + 3005dae: 8082 ret + +03005db0 : + 3005db0: 1101 addi sp,sp,-32 + 3005db2: ce06 sw ra,28(sp) + 3005db4: cc22 sw s0,24(sp) + 3005db6: 1000 addi s0,sp,32 + 3005db8: fea42623 sw a0,-20(s0) + 3005dbc: fec42783 lw a5,-20(s0) + 3005dc0: eb89 bnez a5,3005dd2 + 3005dc2: 02800593 li a1,40 + 3005dc6: 030097b7 lui a5,0x3009 + 3005dca: a8c78513 addi a0,a5,-1396 # 3008a8c + 3005dce: 3625 jal ra,30058f6 + 3005dd0: a001 j 3005dd0 + 3005dd2: fec42783 lw a5,-20(s0) + 3005dd6: 4398 lw a4,0(a5) + 3005dd8: 143007b7 lui a5,0x14300 + 3005ddc: 02f70f63 beq a4,a5,3005e1a + 3005de0: fec42783 lw a5,-20(s0) + 3005de4: 4398 lw a4,0(a5) + 3005de6: 143017b7 lui a5,0x14301 + 3005dea: 02f70863 beq a4,a5,3005e1a + 3005dee: fec42783 lw a5,-20(s0) + 3005df2: 4398 lw a4,0(a5) + 3005df4: 143027b7 lui a5,0x14302 + 3005df8: 02f70163 beq a4,a5,3005e1a + 3005dfc: fec42783 lw a5,-20(s0) + 3005e00: 4398 lw a4,0(a5) + 3005e02: 143037b7 lui a5,0x14303 + 3005e06: 00f70a63 beq a4,a5,3005e1a + 3005e0a: 02900593 li a1,41 + 3005e0e: 030097b7 lui a5,0x3009 + 3005e12: a8c78513 addi a0,a5,-1396 # 3008a8c + 3005e16: 34c5 jal ra,30058f6 + 3005e18: a001 j 3005e18 + 3005e1a: fec42783 lw a5,-20(s0) + 3005e1e: 4bdc lw a5,20(a5) + 3005e20: 853e mv a0,a5 + 3005e22: 3f35 jal ra,3005d5e + 3005e24: 87aa mv a5,a0 + 3005e26: 0017c793 xori a5,a5,1 + 3005e2a: 9f81 uxtb a5 + 3005e2c: cb91 beqz a5,3005e40 + 3005e2e: 02b00593 li a1,43 + 3005e32: 030097b7 lui a5,0x3009 + 3005e36: a8c78513 addi a0,a5,-1396 # 3008a8c + 3005e3a: 3c75 jal ra,30058f6 + 3005e3c: 4785 li a5,1 + 3005e3e: aa6d j 3005ff8 + 3005e40: fec42783 lw a5,-20(s0) + 3005e44: 4f9c lw a5,24(a5) + 3005e46: 853e mv a0,a5 + 3005e48: 3f19 jal ra,3005d5e + 3005e4a: 87aa mv a5,a0 + 3005e4c: 0017c793 xori a5,a5,1 + 3005e50: 9f81 uxtb a5 + 3005e52: cb91 beqz a5,3005e66 + 3005e54: 02c00593 li a1,44 + 3005e58: 030097b7 lui a5,0x3009 + 3005e5c: a8c78513 addi a0,a5,-1396 # 3008a8c + 3005e60: 3c59 jal ra,30058f6 + 3005e62: 4785 li a5,1 + 3005e64: aa51 j 3005ff8 + 3005e66: fec42783 lw a5,-20(s0) + 3005e6a: 479c lw a5,8(a5) + 3005e6c: 853e mv a0,a5 + 3005e6e: 358d jal ra,3005cd0 + 3005e70: 87aa mv a5,a0 + 3005e72: 0017c793 xori a5,a5,1 + 3005e76: 9f81 uxtb a5 + 3005e78: cb91 beqz a5,3005e8c + 3005e7a: 02d00593 li a1,45 + 3005e7e: 030097b7 lui a5,0x3009 + 3005e82: a8c78513 addi a0,a5,-1396 # 3008a8c + 3005e86: 3c85 jal ra,30058f6 + 3005e88: 4785 li a5,1 + 3005e8a: a2bd j 3005ff8 + 3005e8c: fec42783 lw a5,-20(s0) + 3005e90: 4b9c lw a5,16(a5) + 3005e92: 853e mv a0,a5 + 3005e94: 3d79 jal ra,3005d32 + 3005e96: 87aa mv a5,a0 + 3005e98: 0017c793 xori a5,a5,1 + 3005e9c: 9f81 uxtb a5 + 3005e9e: cb91 beqz a5,3005eb2 + 3005ea0: 02e00593 li a1,46 + 3005ea4: 030097b7 lui a5,0x3009 + 3005ea8: a8c78513 addi a0,a5,-1396 # 3008a8c + 3005eac: 34a9 jal ra,30058f6 + 3005eae: 4785 li a5,1 + 3005eb0: a2a1 j 3005ff8 + 3005eb2: fec42783 lw a5,-20(s0) + 3005eb6: 47dc lw a5,12(a5) + 3005eb8: 853e mv a0,a5 + 3005eba: 35c1 jal ra,3005d7a + 3005ebc: 87aa mv a5,a0 + 3005ebe: 0017c793 xori a5,a5,1 + 3005ec2: 9f81 uxtb a5 + 3005ec4: cb91 beqz a5,3005ed8 + 3005ec6: 02f00593 li a1,47 + 3005eca: 030097b7 lui a5,0x3009 + 3005ece: a8c78513 addi a0,a5,-1396 # 3008a8c + 3005ed2: 3415 jal ra,30058f6 + 3005ed4: 4785 li a5,1 + 3005ed6: a20d j 3005ff8 + 3005ed8: fec42783 lw a5,-20(s0) + 3005edc: 439c lw a5,0(a5) + 3005ede: 4705 li a4,1 + 3005ee0: c7d8 sw a4,12(a5) + 3005ee2: fec42783 lw a5,-20(s0) + 3005ee6: 439c lw a5,0(a5) + 3005ee8: fec42703 lw a4,-20(s0) + 3005eec: 4b58 lw a4,20(a4) + 3005eee: c398 sw a4,0(a5) + 3005ef0: fec42783 lw a5,-20(s0) + 3005ef4: 439c lw a5,0(a5) + 3005ef6: fec42703 lw a4,-20(s0) + 3005efa: 4f18 lw a4,24(a4) + 3005efc: cf98 sw a4,24(a5) + 3005efe: fec42783 lw a5,-20(s0) + 3005f02: 4398 lw a4,0(a5) + 3005f04: 471c lw a5,8(a4) + 3005f06: f7f7f793 andi a5,a5,-129 + 3005f0a: c71c sw a5,8(a4) + 3005f0c: fec42783 lw a5,-20(s0) + 3005f10: 4398 lw a4,0(a5) + 3005f12: fec42783 lw a5,-20(s0) + 3005f16: 2fd4 lbu a3,28(a5) + 3005f18: 471c lw a5,8(a4) + 3005f1a: 8a85 andi a3,a3,1 + 3005f1c: 0696 slli a3,a3,0x5 + 3005f1e: fdf7f793 andi a5,a5,-33 + 3005f22: 8fd5 or a5,a5,a3 + 3005f24: c71c sw a5,8(a4) + 3005f26: fec42783 lw a5,-20(s0) + 3005f2a: 47d4 lw a3,12(a5) + 3005f2c: fec42783 lw a5,-20(s0) + 3005f30: 4398 lw a4,0(a5) + 3005f32: 87b6 mv a5,a3 + 3005f34: 8b8d andi a5,a5,3 + 3005f36: 0ff7f693 andi a3,a5,255 + 3005f3a: 471c lw a5,8(a4) + 3005f3c: 8a8d andi a3,a3,3 + 3005f3e: 068a slli a3,a3,0x2 + 3005f40: 9bcd andi a5,a5,-13 + 3005f42: 8fd5 or a5,a5,a3 + 3005f44: c71c sw a5,8(a4) + 3005f46: fec42783 lw a5,-20(s0) + 3005f4a: 4b94 lw a3,16(a5) + 3005f4c: fec42783 lw a5,-20(s0) + 3005f50: 4398 lw a4,0(a5) + 3005f52: 87b6 mv a5,a3 + 3005f54: 8b85 andi a5,a5,1 + 3005f56: 0ff7f693 andi a3,a5,255 + 3005f5a: 471c lw a5,8(a4) + 3005f5c: 8a85 andi a3,a3,1 + 3005f5e: 0686 slli a3,a3,0x1 + 3005f60: 9bf5 andi a5,a5,-3 + 3005f62: 8fd5 or a5,a5,a3 + 3005f64: c71c sw a5,8(a4) + 3005f66: fec42783 lw a5,-20(s0) + 3005f6a: 4798 lw a4,8(a5) + 3005f6c: 4789 li a5,2 + 3005f6e: 00f71a63 bne a4,a5,3005f82 + 3005f72: fec42783 lw a5,-20(s0) + 3005f76: 4398 lw a4,0(a5) + 3005f78: 471c lw a5,8(a4) + 3005f7a: 0017e793 ori a5,a5,1 + 3005f7e: c71c sw a5,8(a4) + 3005f80: a805 j 3005fb0 + 3005f82: fec42783 lw a5,-20(s0) + 3005f86: 4398 lw a4,0(a5) + 3005f88: 471c lw a5,8(a4) + 3005f8a: 9bf9 andi a5,a5,-2 + 3005f8c: c71c sw a5,8(a4) + 3005f8e: fec42783 lw a5,-20(s0) + 3005f92: 479c lw a5,8(a5) + 3005f94: fec42703 lw a4,-20(s0) + 3005f98: 4318 lw a4,0(a4) + 3005f9a: 00f037b3 snez a5,a5 + 3005f9e: 0ff7f693 andi a3,a5,255 + 3005fa2: 471c lw a5,8(a4) + 3005fa4: 8a85 andi a3,a3,1 + 3005fa6: 069a slli a3,a3,0x6 + 3005fa8: fbf7f793 andi a5,a5,-65 + 3005fac: 8fd5 or a5,a5,a3 + 3005fae: c71c sw a5,8(a4) + 3005fb0: fec42783 lw a5,-20(s0) + 3005fb4: 4398 lw a4,0(a5) + 3005fb6: fec42783 lw a5,-20(s0) + 3005fba: 2ff4 lbu a3,30(a5) + 3005fbc: 4f5c lw a5,28(a4) + 3005fbe: 8a85 andi a3,a3,1 + 3005fc0: 0686 slli a3,a3,0x1 + 3005fc2: 9bf5 andi a5,a5,-3 + 3005fc4: 8fd5 or a5,a5,a3 + 3005fc6: cf5c sw a5,28(a4) + 3005fc8: fec42783 lw a5,-20(s0) + 3005fcc: 4398 lw a4,0(a5) + 3005fce: fec42783 lw a5,-20(s0) + 3005fd2: 2ff4 lbu a3,30(a5) + 3005fd4: 4f5c lw a5,28(a4) + 3005fd6: 8a85 andi a3,a3,1 + 3005fd8: 9bf9 andi a5,a5,-2 + 3005fda: 8fd5 or a5,a5,a3 + 3005fdc: cf5c sw a5,28(a4) + 3005fde: fec42783 lw a5,-20(s0) + 3005fe2: 4398 lw a4,0(a5) + 3005fe4: fec42783 lw a5,-20(s0) + 3005fe8: 3fd4 lbu a3,29(a5) + 3005fea: 4f5c lw a5,28(a4) + 3005fec: 8a85 andi a3,a3,1 + 3005fee: 068a slli a3,a3,0x2 + 3005ff0: 9bed andi a5,a5,-5 + 3005ff2: 8fd5 or a5,a5,a3 + 3005ff4: cf5c sw a5,28(a4) + 3005ff6: 4781 li a5,0 + 3005ff8: 853e mv a0,a5 + 3005ffa: 40f2 lw ra,28(sp) + 3005ffc: 4462 lw s0,24(sp) + 3005ffe: 6105 addi sp,sp,32 + 3006000: 8082 ret + +03006002 : + 3006002: 1101 addi sp,sp,-32 + 3006004: ce06 sw ra,28(sp) + 3006006: cc22 sw s0,24(sp) + 3006008: 1000 addi s0,sp,32 + 300600a: fea42623 sw a0,-20(s0) + 300600e: fec42783 lw a5,-20(s0) + 3006012: eb89 bnez a5,3006024 + 3006014: 0bc00593 li a1,188 + 3006018: 030097b7 lui a5,0x3009 + 300601c: a8c78513 addi a0,a5,-1396 # 3008a8c + 3006020: 22c5 jal ra,3006200 + 3006022: a001 j 3006022 + 3006024: fec42783 lw a5,-20(s0) + 3006028: 4398 lw a4,0(a5) + 300602a: 143007b7 lui a5,0x14300 + 300602e: 02f70f63 beq a4,a5,300606c + 3006032: fec42783 lw a5,-20(s0) + 3006036: 4398 lw a4,0(a5) + 3006038: 143017b7 lui a5,0x14301 + 300603c: 02f70863 beq a4,a5,300606c + 3006040: fec42783 lw a5,-20(s0) + 3006044: 4398 lw a4,0(a5) + 3006046: 143027b7 lui a5,0x14302 + 300604a: 02f70163 beq a4,a5,300606c + 300604e: fec42783 lw a5,-20(s0) + 3006052: 4398 lw a4,0(a5) + 3006054: 143037b7 lui a5,0x14303 + 3006058: 00f70a63 beq a4,a5,300606c + 300605c: 0bd00593 li a1,189 + 3006060: 030097b7 lui a5,0x3009 + 3006064: a8c78513 addi a0,a5,-1396 # 3008a8c + 3006068: 2a61 jal ra,3006200 + 300606a: a001 j 300606a + 300606c: fec42783 lw a5,-20(s0) + 3006070: 4398 lw a4,0(a5) + 3006072: 471c lw a5,8(a4) + 3006074: 0807e793 ori a5,a5,128 + 3006078: c71c sw a5,8(a4) + 300607a: 0001 nop + 300607c: 40f2 lw ra,28(sp) + 300607e: 4462 lw s0,24(sp) + 3006080: 6105 addi sp,sp,32 + 3006082: 8082 ret + +03006084 : + 3006084: 7179 addi sp,sp,-48 + 3006086: d606 sw ra,44(sp) + 3006088: d422 sw s0,40(sp) + 300608a: 1800 addi s0,sp,48 + 300608c: fca42e23 sw a0,-36(s0) + 3006090: fdc42783 lw a5,-36(s0) + 3006094: eb89 bnez a5,30060a6 + 3006096: 0d800593 li a1,216 + 300609a: 030097b7 lui a5,0x3009 + 300609e: a8c78513 addi a0,a5,-1396 # 3008a8c + 30060a2: 2ab9 jal ra,3006200 + 30060a4: a001 j 30060a4 + 30060a6: fdc42783 lw a5,-36(s0) + 30060aa: fef42623 sw a5,-20(s0) + 30060ae: fec42783 lw a5,-20(s0) + 30060b2: 4398 lw a4,0(a5) + 30060b4: 143007b7 lui a5,0x14300 + 30060b8: 02f70f63 beq a4,a5,30060f6 + 30060bc: fec42783 lw a5,-20(s0) + 30060c0: 4398 lw a4,0(a5) + 30060c2: 143017b7 lui a5,0x14301 + 30060c6: 02f70863 beq a4,a5,30060f6 + 30060ca: fec42783 lw a5,-20(s0) + 30060ce: 4398 lw a4,0(a5) + 30060d0: 143027b7 lui a5,0x14302 + 30060d4: 02f70163 beq a4,a5,30060f6 + 30060d8: fec42783 lw a5,-20(s0) + 30060dc: 4398 lw a4,0(a5) + 30060de: 143037b7 lui a5,0x14303 + 30060e2: 00f70a63 beq a4,a5,30060f6 + 30060e6: 0da00593 li a1,218 + 30060ea: 030097b7 lui a5,0x3009 + 30060ee: a8c78513 addi a0,a5,-1396 # 3008a8c + 30060f2: 2239 jal ra,3006200 + 30060f4: a001 j 30060f4 + 30060f6: fec42783 lw a5,-20(s0) + 30060fa: 439c lw a5,0(a5) + 30060fc: 4bdc lw a5,20(a5) + 30060fe: 8385 srli a5,a5,0x1 + 3006100: 8b85 andi a5,a5,1 + 3006102: 0ff7f713 andi a4,a5,255 + 3006106: 4785 li a5,1 + 3006108: 02f71363 bne a4,a5,300612e + 300610c: fec42783 lw a5,-20(s0) + 3006110: 4398 lw a4,0(a5) + 3006112: 531c lw a5,32(a4) + 3006114: 0017e793 ori a5,a5,1 + 3006118: d31c sw a5,32(a4) + 300611a: fec42783 lw a5,-20(s0) + 300611e: 53dc lw a5,36(a5) + 3006120: c799 beqz a5,300612e + 3006122: fec42783 lw a5,-20(s0) + 3006126: 53dc lw a5,36(a5) + 3006128: fec42503 lw a0,-20(s0) + 300612c: 9782 jalr a5 + 300612e: fec42783 lw a5,-20(s0) + 3006132: 439c lw a5,0(a5) + 3006134: 4bdc lw a5,20(a5) + 3006136: 8b85 andi a5,a5,1 + 3006138: 0ff7f713 andi a4,a5,255 + 300613c: 4785 li a5,1 + 300613e: 02f71263 bne a4,a5,3006162 + 3006142: fec42783 lw a5,-20(s0) + 3006146: 439c lw a5,0(a5) + 3006148: 4705 li a4,1 + 300614a: c7d8 sw a4,12(a5) + 300614c: fec42783 lw a5,-20(s0) + 3006150: 539c lw a5,32(a5) + 3006152: cb81 beqz a5,3006162 + 3006154: fec42783 lw a5,-20(s0) + 3006158: 539c lw a5,32(a5) + 300615a: fec42503 lw a0,-20(s0) + 300615e: 9782 jalr a5 + 3006160: 0001 nop + 3006162: 0001 nop + 3006164: 50b2 lw ra,44(sp) + 3006166: 5422 lw s0,40(sp) + 3006168: 6145 addi sp,sp,48 + 300616a: 8082 ret + +0300616c : + 300616c: 1101 addi sp,sp,-32 + 300616e: ce06 sw ra,28(sp) + 3006170: cc22 sw s0,24(sp) + 3006172: 1000 addi s0,sp,32 + 3006174: fea42623 sw a0,-20(s0) + 3006178: feb42423 sw a1,-24(s0) + 300617c: fec42223 sw a2,-28(s0) + 3006180: fec42783 lw a5,-20(s0) + 3006184: eb89 bnez a5,3006196 + 3006186: 0fa00593 li a1,250 + 300618a: 030097b7 lui a5,0x3009 + 300618e: a8c78513 addi a0,a5,-1396 # 3008a8c + 3006192: 20bd jal ra,3006200 + 3006194: a001 j 3006194 + 3006196: fe442783 lw a5,-28(s0) + 300619a: eb89 bnez a5,30061ac + 300619c: 0fb00593 li a1,251 + 30061a0: 030097b7 lui a5,0x3009 + 30061a4: a8c78513 addi a0,a5,-1396 # 3008a8c + 30061a8: 28a1 jal ra,3006200 + 30061aa: a001 j 30061aa + 30061ac: fe842503 lw a0,-24(s0) + 30061b0: 3e99 jal ra,3005d06 + 30061b2: 87aa mv a5,a0 + 30061b4: 0017c793 xori a5,a5,1 + 30061b8: 9f81 uxtb a5 + 30061ba: cb89 beqz a5,30061cc + 30061bc: 0fc00593 li a1,252 + 30061c0: 030097b7 lui a5,0x3009 + 30061c4: a8c78513 addi a0,a5,-1396 # 3008a8c + 30061c8: 2825 jal ra,3006200 + 30061ca: a001 j 30061ca + 30061cc: fe842783 lw a5,-24(s0) + 30061d0: cb91 beqz a5,30061e4 + 30061d2: 4705 li a4,1 + 30061d4: 00e79e63 bne a5,a4,30061f0 + 30061d8: fec42783 lw a5,-20(s0) + 30061dc: fe442703 lw a4,-28(s0) + 30061e0: d3d8 sw a4,36(a5) + 30061e2: a809 j 30061f4 + 30061e4: fec42783 lw a5,-20(s0) + 30061e8: fe442703 lw a4,-28(s0) + 30061ec: d398 sw a4,32(a5) + 30061ee: a019 j 30061f4 + 30061f0: 4785 li a5,1 + 30061f2: a011 j 30061f6 + 30061f4: 4781 li a5,0 + 30061f6: 853e mv a0,a5 + 30061f8: 40f2 lw ra,28(sp) + 30061fa: 4462 lw s0,24(sp) + 30061fc: 6105 addi sp,sp,32 + 30061fe: 8082 ret + +03006200 : + 3006200: 808fb06f j 3001208 + +03006204 : + 3006204: 1101 addi sp,sp,-32 + 3006206: ce22 sw s0,28(sp) + 3006208: 1000 addi s0,sp,32 + 300620a: fea42623 sw a0,-20(s0) + 300620e: fec42783 lw a5,-20(s0) + 3006212: 0047b793 sltiu a5,a5,4 + 3006216: 9f81 uxtb a5 + 3006218: 853e mv a0,a5 + 300621a: 4472 lw s0,28(sp) + 300621c: 6105 addi sp,sp,32 + 300621e: 8082 ret + +03006220 : + 3006220: 1101 addi sp,sp,-32 + 3006222: ce22 sw s0,28(sp) + 3006224: 1000 addi s0,sp,32 + 3006226: fea42623 sw a0,-20(s0) + 300622a: fec42783 lw a5,-20(s0) + 300622e: c791 beqz a5,300623a + 3006230: fec42703 lw a4,-20(s0) + 3006234: 4785 li a5,1 + 3006236: 00f71463 bne a4,a5,300623e + 300623a: 4785 li a5,1 + 300623c: a011 j 3006240 + 300623e: 4781 li a5,0 + 3006240: 8b85 andi a5,a5,1 + 3006242: 9f81 uxtb a5 + 3006244: 853e mv a0,a5 + 3006246: 4472 lw s0,28(sp) + 3006248: 6105 addi sp,sp,32 + 300624a: 8082 ret + +0300624c : + 300624c: 1101 addi sp,sp,-32 + 300624e: ce22 sw s0,28(sp) + 3006250: 1000 addi s0,sp,32 + 3006252: fea42623 sw a0,-20(s0) + 3006256: fec42703 lw a4,-20(s0) + 300625a: 4791 li a5,4 + 300625c: 00e7e463 bltu a5,a4,3006264 + 3006260: 4785 li a5,1 + 3006262: a011 j 3006266 + 3006264: 4781 li a5,0 + 3006266: 853e mv a0,a5 + 3006268: 4472 lw s0,28(sp) + 300626a: 6105 addi sp,sp,32 + 300626c: 8082 ret + +0300626e : + 300626e: 1101 addi sp,sp,-32 + 3006270: ce22 sw s0,28(sp) + 3006272: 1000 addi s0,sp,32 + 3006274: fea42623 sw a0,-20(s0) + 3006278: fec42783 lw a5,-20(s0) + 300627c: c385 beqz a5,300629c + 300627e: fec42703 lw a4,-20(s0) + 3006282: 4785 li a5,1 + 3006284: 00f70c63 beq a4,a5,300629c + 3006288: fec42703 lw a4,-20(s0) + 300628c: 4789 li a5,2 + 300628e: 00f70763 beq a4,a5,300629c + 3006292: fec42703 lw a4,-20(s0) + 3006296: 478d li a5,3 + 3006298: 00f71463 bne a4,a5,30062a0 + 300629c: 4785 li a5,1 + 300629e: a011 j 30062a2 + 30062a0: 4781 li a5,0 + 30062a2: 853e mv a0,a5 + 30062a4: 4472 lw s0,28(sp) + 30062a6: 6105 addi sp,sp,32 + 30062a8: 8082 ret + +030062aa : + 30062aa: 1101 addi sp,sp,-32 + 30062ac: ce22 sw s0,28(sp) + 30062ae: 1000 addi s0,sp,32 + 30062b0: fea42623 sw a0,-20(s0) + 30062b4: fec42783 lw a5,-20(s0) + 30062b8: 0107b793 sltiu a5,a5,16 + 30062bc: 9f81 uxtb a5 + 30062be: 853e mv a0,a5 + 30062c0: 4472 lw s0,28(sp) + 30062c2: 6105 addi sp,sp,32 + 30062c4: 8082 ret + +030062c6 : + 30062c6: 1101 addi sp,sp,-32 + 30062c8: ce22 sw s0,28(sp) + 30062ca: 1000 addi s0,sp,32 + 30062cc: fea42623 sw a0,-20(s0) + 30062d0: fec42783 lw a5,-20(s0) + 30062d4: 0057b793 sltiu a5,a5,5 + 30062d8: 9f81 uxtb a5 + 30062da: 853e mv a0,a5 + 30062dc: 4472 lw s0,28(sp) + 30062de: 6105 addi sp,sp,32 + 30062e0: 8082 ret + +030062e2 : + 30062e2: 7179 addi sp,sp,-48 + 30062e4: d622 sw s0,44(sp) + 30062e6: 1800 addi s0,sp,48 + 30062e8: fca42e23 sw a0,-36(s0) + 30062ec: fcb42c23 sw a1,-40(s0) + 30062f0: fd842783 lw a5,-40(s0) + 30062f4: e399 bnez a5,30062fa + 30062f6: 4781 li a5,0 + 30062f8: a005 j 3006318 + 30062fa: fd842783 lw a5,-40(s0) + 30062fe: 0017d713 srli a4,a5,0x1 + 3006302: fdc42783 lw a5,-36(s0) + 3006306: 973e add a4,a4,a5 + 3006308: fd842783 lw a5,-40(s0) + 300630c: 02f757b3 divu a5,a4,a5 + 3006310: fef42623 sw a5,-20(s0) + 3006314: fec42783 lw a5,-20(s0) + 3006318: 853e mv a0,a5 + 300631a: 5432 lw s0,44(sp) + 300631c: 6145 addi sp,sp,48 + 300631e: 8082 ret + +03006320 : + 3006320: 1101 addi sp,sp,-32 + 3006322: ce06 sw ra,28(sp) + 3006324: cc22 sw s0,24(sp) + 3006326: 1000 addi s0,sp,32 + 3006328: fea42623 sw a0,-20(s0) + 300632c: fec42783 lw a5,-20(s0) + 3006330: 439c lw a5,0(a5) + 3006332: 43bc lw a5,64(a5) + 3006334: 83cd srli a5,a5,0x13 + 3006336: 8b85 andi a5,a5,1 + 3006338: 0ff7f713 andi a4,a5,255 + 300633c: 4785 li a5,1 + 300633e: 06f71b63 bne a4,a5,30063b4 + 3006342: fec42783 lw a5,-20(s0) + 3006346: 4398 lw a4,0(a5) + 3006348: 4f7c lw a5,92(a4) + 300634a: 9bf9 andi a5,a5,-2 + 300634c: cf7c sw a5,92(a4) + 300634e: fec42783 lw a5,-20(s0) + 3006352: 4398 lw a4,0(a5) + 3006354: 5f1c lw a5,56(a4) + 3006356: fff006b7 lui a3,0xfff00 + 300635a: 16fd addi a3,a3,-1 # ffefffff + 300635c: 8ff5 and a5,a5,a3 + 300635e: df1c sw a5,56(a4) + 3006360: fec42783 lw a5,-20(s0) + 3006364: 4398 lw a4,0(a5) + 3006366: 5f1c lw a5,56(a4) + 3006368: fff806b7 lui a3,0xfff80 + 300636c: 16fd addi a3,a3,-1 # fff7ffff + 300636e: 8ff5 and a5,a5,a3 + 3006370: df1c sw a5,56(a4) + 3006372: fec42783 lw a5,-20(s0) + 3006376: 4398 lw a4,0(a5) + 3006378: 437c lw a5,68(a4) + 300637a: 000806b7 lui a3,0x80 + 300637e: 8fd5 or a5,a5,a3 + 3006380: c37c sw a5,68(a4) + 3006382: fec42783 lw a5,-20(s0) + 3006386: 4398 lw a4,0(a5) + 3006388: 5b1c lw a5,48(a4) + 300638a: 1007e793 ori a5,a5,256 + 300638e: db1c sw a5,48(a4) + 3006390: fec42783 lw a5,-20(s0) + 3006394: 4398 lw a4,0(a5) + 3006396: 5b1c lw a5,48(a4) + 3006398: 2007e793 ori a5,a5,512 + 300639c: db1c sw a5,48(a4) + 300639e: fec42783 lw a5,-20(s0) + 30063a2: 57fc lw a5,108(a5) + 30063a4: c7b9 beqz a5,30063f2 + 30063a6: fec42783 lw a5,-20(s0) + 30063aa: 57fc lw a5,108(a5) + 30063ac: fec42503 lw a0,-20(s0) + 30063b0: 9782 jalr a5 + 30063b2: a081 j 30063f2 + 30063b4: 0001 nop + 30063b6: fec42783 lw a5,-20(s0) + 30063ba: 439c lw a5,0(a5) + 30063bc: 4ffc lw a5,92(a5) + 30063be: 8391 srli a5,a5,0x4 + 30063c0: 8b85 andi a5,a5,1 + 30063c2: 0ff7f713 andi a4,a5,255 + 30063c6: 4785 li a5,1 + 30063c8: fef707e3 beq a4,a5,30063b6 + 30063cc: fec42783 lw a5,-20(s0) + 30063d0: 4398 lw a4,0(a5) + 30063d2: 437c lw a5,68(a4) + 30063d4: 001006b7 lui a3,0x100 + 30063d8: 8fd5 or a5,a5,a3 + 30063da: c37c sw a5,68(a4) + 30063dc: fec42783 lw a5,-20(s0) + 30063e0: 5bbc lw a5,112(a5) + 30063e2: cb81 beqz a5,30063f2 + 30063e4: fec42783 lw a5,-20(s0) + 30063e8: 5bbc lw a5,112(a5) + 30063ea: fec42503 lw a0,-20(s0) + 30063ee: 9782 jalr a5 + 30063f0: 0001 nop + 30063f2: 0001 nop + 30063f4: 40f2 lw ra,28(sp) + 30063f6: 4462 lw s0,24(sp) + 30063f8: 6105 addi sp,sp,32 + 30063fa: 8082 ret + +030063fc : + 30063fc: 1101 addi sp,sp,-32 + 30063fe: ce06 sw ra,28(sp) + 3006400: cc22 sw s0,24(sp) + 3006402: 1000 addi s0,sp,32 + 3006404: fea42623 sw a0,-20(s0) + 3006408: fec42783 lw a5,-20(s0) + 300640c: 4398 lw a4,0(a5) + 300640e: 5f1c lw a5,56(a4) + 3006410: ffe006b7 lui a3,0xffe00 + 3006414: 16fd addi a3,a3,-1 # ffdfffff + 3006416: 8ff5 and a5,a5,a3 + 3006418: df1c sw a5,56(a4) + 300641a: fec42783 lw a5,-20(s0) + 300641e: 4398 lw a4,0(a5) + 3006420: 437c lw a5,68(a4) + 3006422: 002006b7 lui a3,0x200 + 3006426: 8fd5 or a5,a5,a3 + 3006428: c37c sw a5,68(a4) + 300642a: fec42783 lw a5,-20(s0) + 300642e: 5bfc lw a5,116(a5) + 3006430: c799 beqz a5,300643e + 3006432: fec42783 lw a5,-20(s0) + 3006436: 5bfc lw a5,116(a5) + 3006438: fec42503 lw a0,-20(s0) + 300643c: 9782 jalr a5 + 300643e: 0001 nop + 3006440: 40f2 lw ra,28(sp) + 3006442: 4462 lw s0,24(sp) + 3006444: 6105 addi sp,sp,32 + 3006446: 8082 ret + +03006448 : + 3006448: 1101 addi sp,sp,-32 + 300644a: ce22 sw s0,28(sp) + 300644c: 1000 addi s0,sp,32 + 300644e: fea42623 sw a0,-20(s0) + 3006452: fec42783 lw a5,-20(s0) + 3006456: 4b9c lw a5,16(a5) + 3006458: 4711 li a4,4 + 300645a: 06f76e63 bltu a4,a5,30064d6 + 300645e: 00279713 slli a4,a5,0x2 + 3006462: 030097b7 lui a5,0x3009 + 3006466: aac78793 addi a5,a5,-1364 # 3008aac + 300646a: 97ba add a5,a5,a4 + 300646c: 439c lw a5,0(a5) + 300646e: 8782 jr a5 + 3006470: fec42783 lw a5,-20(s0) + 3006474: 439c lw a5,0(a5) + 3006476: 57d8 lw a4,44(a5) + 3006478: fec42783 lw a5,-20(s0) + 300647c: 439c lw a5,0(a5) + 300647e: 00276713 ori a4,a4,2 + 3006482: d7d8 sw a4,44(a5) + 3006484: a891 j 30064d8 + 3006486: fec42783 lw a5,-20(s0) + 300648a: 439c lw a5,0(a5) + 300648c: 57d8 lw a4,44(a5) + 300648e: fec42783 lw a5,-20(s0) + 3006492: 439c lw a5,0(a5) + 3006494: 00676713 ori a4,a4,6 + 3006498: d7d8 sw a4,44(a5) + 300649a: a83d j 30064d8 + 300649c: fec42783 lw a5,-20(s0) + 30064a0: 439c lw a5,0(a5) + 30064a2: 57d8 lw a4,44(a5) + 30064a4: fec42783 lw a5,-20(s0) + 30064a8: 439c lw a5,0(a5) + 30064aa: 08276713 ori a4,a4,130 + 30064ae: d7d8 sw a4,44(a5) + 30064b0: a025 j 30064d8 + 30064b2: fec42783 lw a5,-20(s0) + 30064b6: 439c lw a5,0(a5) + 30064b8: 57d8 lw a4,44(a5) + 30064ba: fec42783 lw a5,-20(s0) + 30064be: 439c lw a5,0(a5) + 30064c0: 08676713 ori a4,a4,134 + 30064c4: d7d8 sw a4,44(a5) + 30064c6: a809 j 30064d8 + 30064c8: fec42783 lw a5,-20(s0) + 30064cc: 4398 lw a4,0(a5) + 30064ce: 575c lw a5,44(a4) + 30064d0: 9bf5 andi a5,a5,-3 + 30064d2: d75c sw a5,44(a4) + 30064d4: a011 j 30064d8 + 30064d6: 0001 nop + 30064d8: 4472 lw s0,28(sp) + 30064da: 6105 addi sp,sp,32 + 30064dc: 8082 ret + +030064de : + 30064de: 7179 addi sp,sp,-48 + 30064e0: d606 sw ra,44(sp) + 30064e2: d422 sw s0,40(sp) + 30064e4: 1800 addi s0,sp,48 + 30064e6: fca42e23 sw a0,-36(s0) + 30064ea: fdc42783 lw a5,-36(s0) + 30064ee: eb89 bnez a5,3006500 + 30064f0: 09700593 li a1,151 + 30064f4: 030097b7 lui a5,0x3009 + 30064f8: ac078513 addi a0,a5,-1344 # 3008ac0 + 30064fc: 3311 jal ra,3006200 + 30064fe: a001 j 30064fe + 3006500: fdc42783 lw a5,-36(s0) + 3006504: 4398 lw a4,0(a5) + 3006506: 140007b7 lui a5,0x14000 + 300650a: 02f70f63 beq a4,a5,3006548 + 300650e: fdc42783 lw a5,-36(s0) + 3006512: 4398 lw a4,0(a5) + 3006514: 140017b7 lui a5,0x14001 + 3006518: 02f70863 beq a4,a5,3006548 + 300651c: fdc42783 lw a5,-36(s0) + 3006520: 4398 lw a4,0(a5) + 3006522: 140027b7 lui a5,0x14002 + 3006526: 02f70163 beq a4,a5,3006548 + 300652a: fdc42783 lw a5,-36(s0) + 300652e: 4398 lw a4,0(a5) + 3006530: 140037b7 lui a5,0x14003 + 3006534: 00f70a63 beq a4,a5,3006548 + 3006538: 09800593 li a1,152 + 300653c: 030097b7 lui a5,0x3009 + 3006540: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006544: 3975 jal ra,3006200 + 3006546: a001 j 3006546 + 3006548: fdc42783 lw a5,-36(s0) + 300654c: 47bc lw a5,72(a5) + 300654e: cb91 beqz a5,3006562 + 3006550: 09900593 li a1,153 + 3006554: 030097b7 lui a5,0x3009 + 3006558: ac078513 addi a0,a5,-1344 # 3008ac0 + 300655c: 3155 jal ra,3006200 + 300655e: 4785 li a5,1 + 3006560: ae0d j 3006892 + 3006562: fdc42783 lw a5,-36(s0) + 3006566: 47fc lw a5,76(a5) + 3006568: cb91 beqz a5,300657c + 300656a: 09a00593 li a1,154 + 300656e: 030097b7 lui a5,0x3009 + 3006572: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006576: 3169 jal ra,3006200 + 3006578: 4785 li a5,1 + 300657a: ae21 j 3006892 + 300657c: fdc42783 lw a5,-36(s0) + 3006580: 479c lw a5,8(a5) + 3006582: 853e mv a0,a5 + 3006584: 3141 jal ra,3006204 + 3006586: 87aa mv a5,a0 + 3006588: 0017c793 xori a5,a5,1 + 300658c: 9f81 uxtb a5 + 300658e: cb91 beqz a5,30065a2 + 3006590: 09c00593 li a1,156 + 3006594: 030097b7 lui a5,0x3009 + 3006598: ac078513 addi a0,a5,-1344 # 3008ac0 + 300659c: 3195 jal ra,3006200 + 300659e: 4785 li a5,1 + 30065a0: accd j 3006892 + 30065a2: fdc42783 lw a5,-36(s0) + 30065a6: 47dc lw a5,12(a5) + 30065a8: 853e mv a0,a5 + 30065aa: 399d jal ra,3006220 + 30065ac: 87aa mv a5,a0 + 30065ae: 0017c793 xori a5,a5,1 + 30065b2: 9f81 uxtb a5 + 30065b4: cb91 beqz a5,30065c8 + 30065b6: 09d00593 li a1,157 + 30065ba: 030097b7 lui a5,0x3009 + 30065be: ac078513 addi a0,a5,-1344 # 3008ac0 + 30065c2: 393d jal ra,3006200 + 30065c4: 4785 li a5,1 + 30065c6: a4f1 j 3006892 + 30065c8: fdc42783 lw a5,-36(s0) + 30065cc: 4b9c lw a5,16(a5) + 30065ce: 853e mv a0,a5 + 30065d0: 39b5 jal ra,300624c + 30065d2: 87aa mv a5,a0 + 30065d4: 0017c793 xori a5,a5,1 + 30065d8: 9f81 uxtb a5 + 30065da: cb91 beqz a5,30065ee + 30065dc: 09e00593 li a1,158 + 30065e0: 030097b7 lui a5,0x3009 + 30065e4: ac078513 addi a0,a5,-1344 # 3008ac0 + 30065e8: 3921 jal ra,3006200 + 30065ea: 4785 li a5,1 + 30065ec: a45d j 3006892 + 30065ee: fdc42783 lw a5,-36(s0) + 30065f2: 4bdc lw a5,20(a5) + 30065f4: 853e mv a0,a5 + 30065f6: 39a5 jal ra,300626e + 30065f8: 87aa mv a5,a0 + 30065fa: 0017c793 xori a5,a5,1 + 30065fe: 9f81 uxtb a5 + 3006600: cb91 beqz a5,3006614 + 3006602: 09f00593 li a1,159 + 3006606: 030097b7 lui a5,0x3009 + 300660a: ac078513 addi a0,a5,-1344 # 3008ac0 + 300660e: 3ecd jal ra,3006200 + 3006610: 4785 li a5,1 + 3006612: a441 j 3006892 + 3006614: fdc42783 lw a5,-36(s0) + 3006618: 4f9c lw a5,24(a5) + 300661a: 853e mv a0,a5 + 300661c: 3989 jal ra,300626e + 300661e: 87aa mv a5,a0 + 3006620: 0017c793 xori a5,a5,1 + 3006624: 9f81 uxtb a5 + 3006626: cb91 beqz a5,300663a + 3006628: 0a000593 li a1,160 + 300662c: 030097b7 lui a5,0x3009 + 3006630: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006634: 36f1 jal ra,3006200 + 3006636: 4785 li a5,1 + 3006638: aca9 j 3006892 + 300663a: fdc42783 lw a5,-36(s0) + 300663e: 5b9c lw a5,48(a5) + 3006640: 853e mv a0,a5 + 3006642: 31a5 jal ra,30062aa + 3006644: 87aa mv a5,a0 + 3006646: 0017c793 xori a5,a5,1 + 300664a: 9f81 uxtb a5 + 300664c: cb91 beqz a5,3006660 + 300664e: 0a100593 li a1,161 + 3006652: 030097b7 lui a5,0x3009 + 3006656: ac078513 addi a0,a5,-1344 # 3008ac0 + 300665a: 365d jal ra,3006200 + 300665c: 4785 li a5,1 + 300665e: ac15 j 3006892 + 3006660: fdc42783 lw a5,-36(s0) + 3006664: 5bdc lw a5,52(a5) + 3006666: 853e mv a0,a5 + 3006668: 3189 jal ra,30062aa + 300666a: 87aa mv a5,a0 + 300666c: 0017c793 xori a5,a5,1 + 3006670: 9f81 uxtb a5 + 3006672: cb91 beqz a5,3006686 + 3006674: 0a200593 li a1,162 + 3006678: 030097b7 lui a5,0x3009 + 300667c: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006680: 3641 jal ra,3006200 + 3006682: 4785 li a5,1 + 3006684: a439 j 3006892 + 3006686: fdc42783 lw a5,-36(s0) + 300668a: 5fbc lw a5,120(a5) + 300668c: 853e mv a0,a5 + 300668e: 3925 jal ra,30062c6 + 3006690: 87aa mv a5,a0 + 3006692: 0017c793 xori a5,a5,1 + 3006696: 9f81 uxtb a5 + 3006698: cb91 beqz a5,30066ac + 300669a: 0a300593 li a1,163 + 300669e: 030097b7 lui a5,0x3009 + 30066a2: ac078513 addi a0,a5,-1344 # 3008ac0 + 30066a6: 3ea9 jal ra,3006200 + 30066a8: 4785 li a5,1 + 30066aa: a2e5 j 3006892 + 30066ac: fdc42783 lw a5,-36(s0) + 30066b0: 4398 lw a4,0(a5) + 30066b2: 5b1c lw a5,48(a4) + 30066b4: 9bf9 andi a5,a5,-2 + 30066b6: db1c sw a5,48(a4) + 30066b8: 0001 nop + 30066ba: fdc42783 lw a5,-36(s0) + 30066be: 439c lw a5,0(a5) + 30066c0: 4f9c lw a5,24(a5) + 30066c2: 838d srli a5,a5,0x3 + 30066c4: 8b85 andi a5,a5,1 + 30066c6: 0ff7f713 andi a4,a5,255 + 30066ca: 4785 li a5,1 + 30066cc: fef707e3 beq a4,a5,30066ba + 30066d0: fdc42783 lw a5,-36(s0) + 30066d4: 439c lw a5,0(a5) + 30066d6: 853e mv a0,a5 + 30066d8: e93fb0ef jal ra,300256a + 30066dc: fea42623 sw a0,-20(s0) + 30066e0: fdc42783 lw a5,-36(s0) + 30066e4: 5fb4 lw a3,120(a5) + 30066e6: fdc42783 lw a5,-36(s0) + 30066ea: 4398 lw a4,0(a5) + 30066ec: 87b6 mv a5,a3 + 30066ee: 8bbd andi a5,a5,15 + 30066f0: 0ff7f693 andi a3,a5,255 + 30066f4: 4f3c lw a5,88(a4) + 30066f6: 8abd andi a3,a3,15 + 30066f8: 9bc1 andi a5,a5,-16 + 30066fa: 8fd5 or a5,a5,a3 + 30066fc: cf3c sw a5,88(a4) + 30066fe: fdc42783 lw a5,-36(s0) + 3006702: 4398 lw a4,0(a5) + 3006704: fdc42783 lw a5,-36(s0) + 3006708: 07c7c683 lbu a3,124(a5) + 300670c: 4b3c lw a5,80(a4) + 300670e: 8a85 andi a3,a3,1 + 3006710: 9bf9 andi a5,a5,-2 + 3006712: 8fd5 or a5,a5,a3 + 3006714: cb3c sw a5,80(a4) + 3006716: fdc42783 lw a5,-36(s0) + 300671a: 439c lw a5,0(a5) + 300671c: 4fbc lw a5,88(a5) + 300671e: fef42423 sw a5,-24(s0) + 3006722: fdc42783 lw a5,-36(s0) + 3006726: 43d8 lw a4,4(a5) + 3006728: 46c1 li a3,16 + 300672a: fe842783 lw a5,-24(s0) + 300672e: 40f687b3 sub a5,a3,a5 + 3006732: fec42683 lw a3,-20(s0) + 3006736: 02f6d7b3 divu a5,a3,a5 + 300673a: 00e7f463 bgeu a5,a4,3006742 + 300673e: 4785 li a5,1 + 3006740: aa89 j 3006892 + 3006742: 4741 li a4,16 + 3006744: fe842783 lw a5,-24(s0) + 3006748: 40f707b3 sub a5,a4,a5 + 300674c: fec42703 lw a4,-20(s0) + 3006750: 02f757b3 divu a5,a4,a5 + 3006754: 079a slli a5,a5,0x6 + 3006756: fef42223 sw a5,-28(s0) + 300675a: fdc42783 lw a5,-36(s0) + 300675e: 43dc lw a5,4(a5) + 3006760: 85be mv a1,a5 + 3006762: fe442503 lw a0,-28(s0) + 3006766: 3eb5 jal ra,30062e2 + 3006768: fea42023 sw a0,-32(s0) + 300676c: fdc42783 lw a5,-36(s0) + 3006770: 439c lw a5,0(a5) + 3006772: 0207a423 sw zero,40(a5) + 3006776: fdc42783 lw a5,-36(s0) + 300677a: 439c lw a5,0(a5) + 300677c: 0207a223 sw zero,36(a5) + 3006780: fdc42783 lw a5,-36(s0) + 3006784: 439c lw a5,0(a5) + 3006786: fe042703 lw a4,-32(s0) + 300678a: 03f77713 andi a4,a4,63 + 300678e: d798 sw a4,40(a5) + 3006790: fdc42783 lw a5,-36(s0) + 3006794: 439c lw a5,0(a5) + 3006796: fe042703 lw a4,-32(s0) + 300679a: 8319 srli a4,a4,0x6 + 300679c: d3d8 sw a4,36(a5) + 300679e: fdc42783 lw a5,-36(s0) + 30067a2: 439c lw a5,0(a5) + 30067a4: 0207a623 sw zero,44(a5) + 30067a8: fdc42783 lw a5,-36(s0) + 30067ac: 4794 lw a3,8(a5) + 30067ae: fdc42783 lw a5,-36(s0) + 30067b2: 4398 lw a4,0(a5) + 30067b4: 87b6 mv a5,a3 + 30067b6: 8b8d andi a5,a5,3 + 30067b8: 0ff7f693 andi a3,a5,255 + 30067bc: 575c lw a5,44(a4) + 30067be: 8a8d andi a3,a3,3 + 30067c0: 0696 slli a3,a3,0x5 + 30067c2: f9f7f793 andi a5,a5,-97 + 30067c6: 8fd5 or a5,a5,a3 + 30067c8: d75c sw a5,44(a4) + 30067ca: fdc42783 lw a5,-36(s0) + 30067ce: 47d4 lw a3,12(a5) + 30067d0: fdc42783 lw a5,-36(s0) + 30067d4: 4398 lw a4,0(a5) + 30067d6: 87b6 mv a5,a3 + 30067d8: 8b85 andi a5,a5,1 + 30067da: 0ff7f693 andi a3,a5,255 + 30067de: 575c lw a5,44(a4) + 30067e0: 8a85 andi a3,a3,1 + 30067e2: 068e slli a3,a3,0x3 + 30067e4: 9bdd andi a5,a5,-9 + 30067e6: 8fd5 or a5,a5,a3 + 30067e8: d75c sw a5,44(a4) + 30067ea: fdc42503 lw a0,-36(s0) + 30067ee: 39a9 jal ra,3006448 + 30067f0: fdc42783 lw a5,-36(s0) + 30067f4: 02c7c783 lbu a5,44(a5) + 30067f8: cbb1 beqz a5,300684c + 30067fa: fdc42783 lw a5,-36(s0) + 30067fe: 4398 lw a4,0(a5) + 3006800: 575c lw a5,44(a4) + 3006802: 0107e793 ori a5,a5,16 + 3006806: d75c sw a5,44(a4) + 3006808: fdc42783 lw a5,-36(s0) + 300680c: 5bd4 lw a3,52(a5) + 300680e: fdc42783 lw a5,-36(s0) + 3006812: 4398 lw a4,0(a5) + 3006814: 87b6 mv a5,a3 + 3006816: 8bbd andi a5,a5,15 + 3006818: 0ff7f693 andi a3,a5,255 + 300681c: 5b5c lw a5,52(a4) + 300681e: 8abd andi a3,a3,15 + 3006820: 06a2 slli a3,a3,0x8 + 3006822: 767d lui a2,0xfffff + 3006824: 0ff60613 addi a2,a2,255 # fffff0ff + 3006828: 8ff1 and a5,a5,a2 + 300682a: 8fd5 or a5,a5,a3 + 300682c: db5c sw a5,52(a4) + 300682e: fdc42783 lw a5,-36(s0) + 3006832: 5b94 lw a3,48(a5) + 3006834: fdc42783 lw a5,-36(s0) + 3006838: 4398 lw a4,0(a5) + 300683a: 87b6 mv a5,a3 + 300683c: 8bbd andi a5,a5,15 + 300683e: 0ff7f693 andi a3,a5,255 + 3006842: 5b5c lw a5,52(a4) + 3006844: 8abd andi a3,a3,15 + 3006846: 9bc1 andi a5,a5,-16 + 3006848: 8fd5 or a5,a5,a3 + 300684a: db5c sw a5,52(a4) + 300684c: fdc42783 lw a5,-36(s0) + 3006850: 5f98 lw a4,56(a5) + 3006852: 4785 li a5,1 + 3006854: 00f71c63 bne a4,a5,300686c + 3006858: fdc42783 lw a5,-36(s0) + 300685c: 439c lw a5,0(a5) + 300685e: 5b94 lw a3,48(a5) + 3006860: fdc42783 lw a5,-36(s0) + 3006864: 439c lw a5,0(a5) + 3006866: 6731 lui a4,0xc + 3006868: 8f55 or a4,a4,a3 + 300686a: db98 sw a4,48(a5) + 300686c: fdc42783 lw a5,-36(s0) + 3006870: 439c lw a5,0(a5) + 3006872: 5b98 lw a4,48(a5) + 3006874: fdc42783 lw a5,-36(s0) + 3006878: 439c lw a5,0(a5) + 300687a: 30176713 ori a4,a4,769 + 300687e: db98 sw a4,48(a5) + 3006880: fdc42783 lw a5,-36(s0) + 3006884: 4705 li a4,1 + 3006886: c7b8 sw a4,72(a5) + 3006888: fdc42783 lw a5,-36(s0) + 300688c: 4705 li a4,1 + 300688e: c7f8 sw a4,76(a5) + 3006890: 4781 li a5,0 + 3006892: 853e mv a0,a5 + 3006894: 50b2 lw ra,44(sp) + 3006896: 5422 lw s0,40(sp) + 3006898: 6145 addi sp,sp,48 + 300689a: 8082 ret + +0300689c : + 300689c: 7139 addi sp,sp,-64 + 300689e: 03010293 addi t0,sp,48 + 30068a2: 0062928b stmia {ra,s0,s2-s3},(t0) + 30068a6: 0080 addi s0,sp,64 + 30068a8: fca42623 sw a0,-52(s0) + 30068ac: fcb42423 sw a1,-56(s0) + 30068b0: fcc42223 sw a2,-60(s0) + 30068b4: fcd42023 sw a3,-64(s0) + 30068b8: fcc42783 lw a5,-52(s0) + 30068bc: eb89 bnez a5,30068ce + 30068be: 11500593 li a1,277 + 30068c2: 030097b7 lui a5,0x3009 + 30068c6: ac078513 addi a0,a5,-1344 # 3008ac0 + 30068ca: 3a1d jal ra,3006200 + 30068cc: a001 j 30068cc + 30068ce: fcc42783 lw a5,-52(s0) + 30068d2: 4398 lw a4,0(a5) + 30068d4: 140007b7 lui a5,0x14000 + 30068d8: 02f70f63 beq a4,a5,3006916 + 30068dc: fcc42783 lw a5,-52(s0) + 30068e0: 4398 lw a4,0(a5) + 30068e2: 140017b7 lui a5,0x14001 + 30068e6: 02f70863 beq a4,a5,3006916 + 30068ea: fcc42783 lw a5,-52(s0) + 30068ee: 4398 lw a4,0(a5) + 30068f0: 140027b7 lui a5,0x14002 + 30068f4: 02f70163 beq a4,a5,3006916 + 30068f8: fcc42783 lw a5,-52(s0) + 30068fc: 4398 lw a4,0(a5) + 30068fe: 140037b7 lui a5,0x14003 + 3006902: 00f70a63 beq a4,a5,3006916 + 3006906: 11600593 li a1,278 + 300690a: 030097b7 lui a5,0x3009 + 300690e: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006912: 30fd jal ra,3006200 + 3006914: a001 j 3006914 + 3006916: fc842783 lw a5,-56(s0) + 300691a: eb89 bnez a5,300692c + 300691c: 11700593 li a1,279 + 3006920: 030097b7 lui a5,0x3009 + 3006924: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006928: 38e1 jal ra,3006200 + 300692a: a001 j 300692a + 300692c: fcc42783 lw a5,-52(s0) + 3006930: 4bdc lw a5,20(a5) + 3006932: cb91 beqz a5,3006946 + 3006934: 11800593 li a1,280 + 3006938: 030097b7 lui a5,0x3009 + 300693c: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006940: 23bd jal ra,3006eae + 3006942: 4785 li a5,1 + 3006944: a249 j 3006ac6 + 3006946: fc442783 lw a5,-60(s0) + 300694a: eb91 bnez a5,300695e + 300694c: 11900593 li a1,281 + 3006950: 030097b7 lui a5,0x3009 + 3006954: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006958: 2b99 jal ra,3006eae + 300695a: 4785 li a5,1 + 300695c: a2ad j 3006ac6 + 300695e: 14380537 lui a0,0x14380 + 3006962: c09fb0ef jal ra,300256a + 3006966: 872a mv a4,a0 + 3006968: 3e800793 li a5,1000 + 300696c: 02f75733 divu a4,a4,a5 + 3006970: fc042783 lw a5,-64(s0) + 3006974: 02f707b3 mul a5,a4,a5 + 3006978: fef42023 sw a5,-32(s0) + 300697c: fe042223 sw zero,-28(s0) + 3006980: fe442783 lw a5,-28(s0) + 3006984: eb89 bnez a5,3006996 + 3006986: fe442783 lw a5,-28(s0) + 300698a: ef99 bnez a5,30069a8 + 300698c: fe042703 lw a4,-32(s0) + 3006990: 57f9 li a5,-2 + 3006992: 00e7fb63 bgeu a5,a4,30069a8 + 3006996: 11b00593 li a1,283 + 300699a: 030097b7 lui a5,0x3009 + 300699e: ac078513 addi a0,a5,-1344 # 3008ac0 + 30069a2: 2331 jal ra,3006eae + 30069a4: 4785 li a5,1 + 30069a6: a205 j 3006ac6 + 30069a8: fcc42783 lw a5,-52(s0) + 30069ac: 47b8 lw a4,72(a5) + 30069ae: 4785 li a5,1 + 30069b0: 10f71463 bne a4,a5,3006ab8 + 30069b4: fcc42783 lw a5,-52(s0) + 30069b8: 470d li a4,3 + 30069ba: c7b8 sw a4,72(a5) + 30069bc: fc442783 lw a5,-60(s0) + 30069c0: fef42623 sw a5,-20(s0) + 30069c4: fc842783 lw a5,-56(s0) + 30069c8: fef42423 sw a5,-24(s0) + 30069cc: fcc42783 lw a5,-52(s0) + 30069d0: 4398 lw a4,0(a5) + 30069d2: 5f1c lw a5,56(a4) + 30069d4: fdf7f793 andi a5,a5,-33 + 30069d8: df1c sw a5,56(a4) + 30069da: fcc42783 lw a5,-52(s0) + 30069de: 4398 lw a4,0(a5) + 30069e0: 5b1c lw a5,48(a4) + 30069e2: 1007e793 ori a5,a5,256 + 30069e6: db1c sw a5,48(a4) + 30069e8: 837fa0ef jal ra,300121e + 30069ec: fca42e23 sw a0,-36(s0) + 30069f0: fdc42783 lw a5,-36(s0) + 30069f4: fcf42c23 sw a5,-40(s0) + 30069f8: a865 j 3006ab0 + 30069fa: 825fa0ef jal ra,300121e + 30069fe: fca42c23 sw a0,-40(s0) + 3006a02: fd842703 lw a4,-40(s0) + 3006a06: fdc42783 lw a5,-36(s0) + 3006a0a: 00e7fb63 bgeu a5,a4,3006a20 + 3006a0e: fd842703 lw a4,-40(s0) + 3006a12: fdc42783 lw a5,-36(s0) + 3006a16: 40f707b3 sub a5,a4,a5 + 3006a1a: 893e mv s2,a5 + 3006a1c: 4981 li s3,0 + 3006a1e: a811 j 3006a32 + 3006a20: fd842703 lw a4,-40(s0) + 3006a24: fdc42783 lw a5,-36(s0) + 3006a28: 40f707b3 sub a5,a4,a5 + 3006a2c: 17fd addi a5,a5,-1 + 3006a2e: 893e mv s2,a5 + 3006a30: 4981 li s3,0 + 3006a32: fd242823 sw s2,-48(s0) + 3006a36: fd342a23 sw s3,-44(s0) + 3006a3a: fe442703 lw a4,-28(s0) + 3006a3e: fd442783 lw a5,-44(s0) + 3006a42: 02e7e463 bltu a5,a4,3006a6a + 3006a46: fe442703 lw a4,-28(s0) + 3006a4a: fd442783 lw a5,-44(s0) + 3006a4e: 00f71863 bne a4,a5,3006a5e + 3006a52: fe042703 lw a4,-32(s0) + 3006a56: fd042783 lw a5,-48(s0) + 3006a5a: 00e7e863 bltu a5,a4,3006a6a + 3006a5e: fcc42783 lw a5,-52(s0) + 3006a62: 4705 li a4,1 + 3006a64: c7b8 sw a4,72(a5) + 3006a66: 478d li a5,3 + 3006a68: a8b9 j 3006ac6 + 3006a6a: fcc42783 lw a5,-52(s0) + 3006a6e: 439c lw a5,0(a5) + 3006a70: 4f9c lw a5,24(a5) + 3006a72: 8395 srli a5,a5,0x5 + 3006a74: 8b85 andi a5,a5,1 + 3006a76: 0ff7f713 andi a4,a5,255 + 3006a7a: 4785 li a5,1 + 3006a7c: 00f71363 bne a4,a5,3006a82 + 3006a80: a805 j 3006ab0 + 3006a82: fcc42783 lw a5,-52(s0) + 3006a86: 4398 lw a4,0(a5) + 3006a88: fe842783 lw a5,-24(s0) + 3006a8c: 2394 lbu a3,0(a5) + 3006a8e: 431c lw a5,0(a4) + 3006a90: 0ff6f693 andi a3,a3,255 + 3006a94: f007f793 andi a5,a5,-256 + 3006a98: 8fd5 or a5,a5,a3 + 3006a9a: c31c sw a5,0(a4) + 3006a9c: fe842783 lw a5,-24(s0) + 3006aa0: 0785 addi a5,a5,1 + 3006aa2: fef42423 sw a5,-24(s0) + 3006aa6: fec42783 lw a5,-20(s0) + 3006aaa: 17fd addi a5,a5,-1 + 3006aac: fef42623 sw a5,-20(s0) + 3006ab0: fec42783 lw a5,-20(s0) + 3006ab4: f3b9 bnez a5,30069fa + 3006ab6: a019 j 3006abc + 3006ab8: 4789 li a5,2 + 3006aba: a031 j 3006ac6 + 3006abc: fcc42783 lw a5,-52(s0) + 3006ac0: 4705 li a4,1 + 3006ac2: c7b8 sw a4,72(a5) + 3006ac4: 4781 li a5,0 + 3006ac6: 853e mv a0,a5 + 3006ac8: 03010293 addi t0,sp,48 + 3006acc: 0062828b ldmia {ra,s0,s2-s3},(t0) + 3006ad0: 6121 addi sp,sp,64 + 3006ad2: 8082 ret + +03006ad4 : + 3006ad4: 1101 addi sp,sp,-32 + 3006ad6: ce06 sw ra,28(sp) + 3006ad8: cc22 sw s0,24(sp) + 3006ada: 1000 addi s0,sp,32 + 3006adc: fea42623 sw a0,-20(s0) + 3006ae0: fec42783 lw a5,-20(s0) + 3006ae4: eb89 bnez a5,3006af6 + 3006ae6: 16200593 li a1,354 + 3006aea: 030097b7 lui a5,0x3009 + 3006aee: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006af2: 2e75 jal ra,3006eae + 3006af4: a001 j 3006af4 + 3006af6: fec42783 lw a5,-20(s0) + 3006afa: 4398 lw a4,0(a5) + 3006afc: 140007b7 lui a5,0x14000 + 3006b00: 02f70f63 beq a4,a5,3006b3e + 3006b04: fec42783 lw a5,-20(s0) + 3006b08: 4398 lw a4,0(a5) + 3006b0a: 140017b7 lui a5,0x14001 + 3006b0e: 02f70863 beq a4,a5,3006b3e + 3006b12: fec42783 lw a5,-20(s0) + 3006b16: 4398 lw a4,0(a5) + 3006b18: 140027b7 lui a5,0x14002 + 3006b1c: 02f70163 beq a4,a5,3006b3e + 3006b20: fec42783 lw a5,-20(s0) + 3006b24: 4398 lw a4,0(a5) + 3006b26: 140037b7 lui a5,0x14003 + 3006b2a: 00f70a63 beq a4,a5,3006b3e + 3006b2e: 16300593 li a1,355 + 3006b32: 030097b7 lui a5,0x3009 + 3006b36: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006b3a: 2e95 jal ra,3006eae + 3006b3c: a001 j 3006b3c + 3006b3e: fec42783 lw a5,-20(s0) + 3006b42: 4fdc lw a5,28(a5) + 3006b44: eb89 bnez a5,3006b56 + 3006b46: 16400593 li a1,356 + 3006b4a: 030097b7 lui a5,0x3009 + 3006b4e: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006b52: 2eb1 jal ra,3006eae + 3006b54: a001 j 3006b54 + 3006b56: fec42783 lw a5,-20(s0) + 3006b5a: 47b8 lw a4,72(a5) + 3006b5c: 478d li a5,3 + 3006b5e: 0af71f63 bne a4,a5,3006c1c + 3006b62: a8a1 j 3006bba + 3006b64: fec42783 lw a5,-20(s0) + 3006b68: 439c lw a5,0(a5) + 3006b6a: 4f9c lw a5,24(a5) + 3006b6c: 8395 srli a5,a5,0x5 + 3006b6e: 8b85 andi a5,a5,1 + 3006b70: 0ff7f713 andi a4,a5,255 + 3006b74: 4785 li a5,1 + 3006b76: 04f70763 beq a4,a5,3006bc4 + 3006b7a: fec42783 lw a5,-20(s0) + 3006b7e: 4fdc lw a5,28(a5) + 3006b80: fec42703 lw a4,-20(s0) + 3006b84: 4318 lw a4,0(a4) + 3006b86: 239c lbu a5,0(a5) + 3006b88: 0ff7f693 andi a3,a5,255 + 3006b8c: 431c lw a5,0(a4) + 3006b8e: 0ff6f693 andi a3,a3,255 + 3006b92: f007f793 andi a5,a5,-256 + 3006b96: 8fd5 or a5,a5,a3 + 3006b98: c31c sw a5,0(a4) + 3006b9a: fec42783 lw a5,-20(s0) + 3006b9e: 4fdc lw a5,28(a5) + 3006ba0: 00178713 addi a4,a5,1 + 3006ba4: fec42783 lw a5,-20(s0) + 3006ba8: cfd8 sw a4,28(a5) + 3006baa: fec42783 lw a5,-20(s0) + 3006bae: 53dc lw a5,36(a5) + 3006bb0: fff78713 addi a4,a5,-1 + 3006bb4: fec42783 lw a5,-20(s0) + 3006bb8: d3d8 sw a4,36(a5) + 3006bba: fec42783 lw a5,-20(s0) + 3006bbe: 53dc lw a5,36(a5) + 3006bc0: f3d5 bnez a5,3006b64 + 3006bc2: a011 j 3006bc6 + 3006bc4: 0001 nop + 3006bc6: fec42783 lw a5,-20(s0) + 3006bca: 53dc lw a5,36(a5) + 3006bcc: eba1 bnez a5,3006c1c + 3006bce: fec42783 lw a5,-20(s0) + 3006bd2: 439c lw a5,0(a5) + 3006bd4: 5f94 lw a3,56(a5) + 3006bd6: fec42783 lw a5,-20(s0) + 3006bda: 439c lw a5,0(a5) + 3006bdc: 777d lui a4,0xfffff + 3006bde: fdf70713 addi a4,a4,-33 # ffffefdf + 3006be2: 8f75 and a4,a4,a3 + 3006be4: df98 sw a4,56(a5) + 3006be6: fec42783 lw a5,-20(s0) + 3006bea: 439c lw a5,0(a5) + 3006bec: 43f4 lw a3,68(a5) + 3006bee: fec42783 lw a5,-20(s0) + 3006bf2: 439c lw a5,0(a5) + 3006bf4: 6705 lui a4,0x1 + 3006bf6: 02070713 addi a4,a4,32 # 1020 + 3006bfa: 8f55 or a4,a4,a3 + 3006bfc: c3f8 sw a4,68(a5) + 3006bfe: fec42783 lw a5,-20(s0) + 3006c02: 4705 li a4,1 + 3006c04: c7b8 sw a4,72(a5) + 3006c06: fec42783 lw a5,-20(s0) + 3006c0a: 4bfc lw a5,84(a5) + 3006c0c: cb81 beqz a5,3006c1c + 3006c0e: fec42783 lw a5,-20(s0) + 3006c12: 4bfc lw a5,84(a5) + 3006c14: fec42503 lw a0,-20(s0) + 3006c18: 9782 jalr a5 + 3006c1a: 0001 nop + 3006c1c: 0001 nop + 3006c1e: 40f2 lw ra,28(sp) + 3006c20: 4462 lw s0,24(sp) + 3006c22: 6105 addi sp,sp,32 + 3006c24: 8082 ret + +03006c26 : + 3006c26: 1101 addi sp,sp,-32 + 3006c28: ce06 sw ra,28(sp) + 3006c2a: cc22 sw s0,24(sp) + 3006c2c: 1000 addi s0,sp,32 + 3006c2e: fea42623 sw a0,-20(s0) + 3006c32: feb42423 sw a1,-24(s0) + 3006c36: fec42223 sw a2,-28(s0) + 3006c3a: fec42783 lw a5,-20(s0) + 3006c3e: eb89 bnez a5,3006c50 + 3006c40: 1e100593 li a1,481 + 3006c44: 030097b7 lui a5,0x3009 + 3006c48: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006c4c: 248d jal ra,3006eae + 3006c4e: a001 j 3006c4e + 3006c50: fec42783 lw a5,-20(s0) + 3006c54: 4398 lw a4,0(a5) + 3006c56: 140007b7 lui a5,0x14000 + 3006c5a: 02f70f63 beq a4,a5,3006c98 + 3006c5e: fec42783 lw a5,-20(s0) + 3006c62: 4398 lw a4,0(a5) + 3006c64: 140017b7 lui a5,0x14001 + 3006c68: 02f70863 beq a4,a5,3006c98 + 3006c6c: fec42783 lw a5,-20(s0) + 3006c70: 4398 lw a4,0(a5) + 3006c72: 140027b7 lui a5,0x14002 + 3006c76: 02f70163 beq a4,a5,3006c98 + 3006c7a: fec42783 lw a5,-20(s0) + 3006c7e: 4398 lw a4,0(a5) + 3006c80: 140037b7 lui a5,0x14003 + 3006c84: 00f70a63 beq a4,a5,3006c98 + 3006c88: 1e200593 li a1,482 + 3006c8c: 030097b7 lui a5,0x3009 + 3006c90: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006c94: 2c29 jal ra,3006eae + 3006c96: a001 j 3006c96 + 3006c98: fe842783 lw a5,-24(s0) + 3006c9c: eb89 bnez a5,3006cae + 3006c9e: 1e300593 li a1,483 + 3006ca2: 030097b7 lui a5,0x3009 + 3006ca6: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006caa: 2411 jal ra,3006eae + 3006cac: a001 j 3006cac + 3006cae: fec42783 lw a5,-20(s0) + 3006cb2: 4f98 lw a4,24(a5) + 3006cb4: 4785 li a5,1 + 3006cb6: 00f70b63 beq a4,a5,3006ccc + 3006cba: 1e400593 li a1,484 + 3006cbe: 030097b7 lui a5,0x3009 + 3006cc2: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006cc6: 22e5 jal ra,3006eae + 3006cc8: 4785 li a5,1 + 3006cca: a051 j 3006d4e + 3006ccc: fe442783 lw a5,-28(s0) + 3006cd0: eb91 bnez a5,3006ce4 + 3006cd2: 1e500593 li a1,485 + 3006cd6: 030097b7 lui a5,0x3009 + 3006cda: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006cde: 2ac1 jal ra,3006eae + 3006ce0: 4785 li a5,1 + 3006ce2: a0b5 j 3006d4e + 3006ce4: fec42783 lw a5,-20(s0) + 3006ce8: 47f8 lw a4,76(a5) + 3006cea: 4785 li a5,1 + 3006cec: 04f71e63 bne a4,a5,3006d48 + 3006cf0: fec42783 lw a5,-20(s0) + 3006cf4: 4711 li a4,4 + 3006cf6: c7f8 sw a4,76(a5) + 3006cf8: fec42783 lw a5,-20(s0) + 3006cfc: fe842703 lw a4,-24(s0) + 3006d00: d398 sw a4,32(a5) + 3006d02: fec42783 lw a5,-20(s0) + 3006d06: fe442703 lw a4,-28(s0) + 3006d0a: d798 sw a4,40(a5) + 3006d0c: fec42783 lw a5,-20(s0) + 3006d10: 02c7c783 lbu a5,44(a5) + 3006d14: cf81 beqz a5,3006d2c + 3006d16: fec42783 lw a5,-20(s0) + 3006d1a: 439c lw a5,0(a5) + 3006d1c: 5f98 lw a4,56(a5) + 3006d1e: fec42783 lw a5,-20(s0) + 3006d22: 439c lw a5,0(a5) + 3006d24: 7d076713 ori a4,a4,2000 + 3006d28: df98 sw a4,56(a5) + 3006d2a: a00d j 3006d4c + 3006d2c: fec42783 lw a5,-20(s0) + 3006d30: 439c lw a5,0(a5) + 3006d32: 5f94 lw a3,56(a5) + 3006d34: fec42783 lw a5,-20(s0) + 3006d38: 439c lw a5,0(a5) + 3006d3a: 00020737 lui a4,0x20 + 3006d3e: 78070713 addi a4,a4,1920 # 20780 + 3006d42: 8f55 or a4,a4,a3 + 3006d44: df98 sw a4,56(a5) + 3006d46: a019 j 3006d4c + 3006d48: 4789 li a5,2 + 3006d4a: a011 j 3006d4e + 3006d4c: 4781 li a5,0 + 3006d4e: 853e mv a0,a5 + 3006d50: 40f2 lw ra,28(sp) + 3006d52: 4462 lw s0,24(sp) + 3006d54: 6105 addi sp,sp,32 + 3006d56: 8082 ret + +03006d58 : + 3006d58: 7179 addi sp,sp,-48 + 3006d5a: d606 sw ra,44(sp) + 3006d5c: d422 sw s0,40(sp) + 3006d5e: 1800 addi s0,sp,48 + 3006d60: fca42e23 sw a0,-36(s0) + 3006d64: fdc42783 lw a5,-36(s0) + 3006d68: eb89 bnez a5,3006d7a + 3006d6a: 1fd00593 li a1,509 + 3006d6e: 030097b7 lui a5,0x3009 + 3006d72: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006d76: 2a25 jal ra,3006eae + 3006d78: a001 j 3006d78 + 3006d7a: fdc42783 lw a5,-36(s0) + 3006d7e: 539c lw a5,32(a5) + 3006d80: eb89 bnez a5,3006d92 + 3006d82: 1fe00593 li a1,510 + 3006d86: 030097b7 lui a5,0x3009 + 3006d8a: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006d8e: 2205 jal ra,3006eae + 3006d90: a001 j 3006d90 + 3006d92: fdc42783 lw a5,-36(s0) + 3006d96: 4398 lw a4,0(a5) + 3006d98: 140007b7 lui a5,0x14000 + 3006d9c: 02f70f63 beq a4,a5,3006dda + 3006da0: fdc42783 lw a5,-36(s0) + 3006da4: 4398 lw a4,0(a5) + 3006da6: 140017b7 lui a5,0x14001 + 3006daa: 02f70863 beq a4,a5,3006dda + 3006dae: fdc42783 lw a5,-36(s0) + 3006db2: 4398 lw a4,0(a5) + 3006db4: 140027b7 lui a5,0x14002 + 3006db8: 02f70163 beq a4,a5,3006dda + 3006dbc: fdc42783 lw a5,-36(s0) + 3006dc0: 4398 lw a4,0(a5) + 3006dc2: 140037b7 lui a5,0x14003 + 3006dc6: 00f70a63 beq a4,a5,3006dda + 3006dca: 1ff00593 li a1,511 + 3006dce: 030097b7 lui a5,0x3009 + 3006dd2: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006dd6: 28e1 jal ra,3006eae + 3006dd8: a001 j 3006dd8 + 3006dda: fdc42783 lw a5,-36(s0) + 3006dde: 47f8 lw a4,76(a5) + 3006de0: 4791 li a5,4 + 3006de2: 0cf71163 bne a4,a5,3006ea4 + 3006de6: a889 j 3006e38 + 3006de8: fdc42783 lw a5,-36(s0) + 3006dec: 439c lw a5,0(a5) + 3006dee: 4f9c lw a5,24(a5) + 3006df0: 8391 srli a5,a5,0x4 + 3006df2: 8b85 andi a5,a5,1 + 3006df4: 0ff7f713 andi a4,a5,255 + 3006df8: 4785 li a5,1 + 3006dfa: 04f70463 beq a4,a5,3006e42 + 3006dfe: fdc42783 lw a5,-36(s0) + 3006e02: 439c lw a5,0(a5) + 3006e04: 439c lw a5,0(a5) + 3006e06: fef42623 sw a5,-20(s0) + 3006e0a: fdc42783 lw a5,-36(s0) + 3006e0e: 539c lw a5,32(a5) + 3006e10: fec42703 lw a4,-20(s0) + 3006e14: 9f01 uxtb a4 + 3006e16: a398 sb a4,0(a5) + 3006e18: fdc42783 lw a5,-36(s0) + 3006e1c: 539c lw a5,32(a5) + 3006e1e: 00178713 addi a4,a5,1 + 3006e22: fdc42783 lw a5,-36(s0) + 3006e26: d398 sw a4,32(a5) + 3006e28: fdc42783 lw a5,-36(s0) + 3006e2c: 579c lw a5,40(a5) + 3006e2e: fff78713 addi a4,a5,-1 + 3006e32: fdc42783 lw a5,-36(s0) + 3006e36: d798 sw a4,40(a5) + 3006e38: fdc42783 lw a5,-36(s0) + 3006e3c: 579c lw a5,40(a5) + 3006e3e: f7cd bnez a5,3006de8 + 3006e40: a011 j 3006e44 + 3006e42: 0001 nop + 3006e44: fdc42783 lw a5,-36(s0) + 3006e48: 579c lw a5,40(a5) + 3006e4a: e38d bnez a5,3006e6c + 3006e4c: fdc42783 lw a5,-36(s0) + 3006e50: 439c lw a5,0(a5) + 3006e52: 5f94 lw a3,56(a5) + 3006e54: fdc42783 lw a5,-36(s0) + 3006e58: 439c lw a5,0(a5) + 3006e5a: 7701 lui a4,0xfffe0 + 3006e5c: faf70713 addi a4,a4,-81 # fffdffaf + 3006e60: 8f75 and a4,a4,a3 + 3006e62: df98 sw a4,56(a5) + 3006e64: fdc42783 lw a5,-36(s0) + 3006e68: 4705 li a4,1 + 3006e6a: c7f8 sw a4,76(a5) + 3006e6c: fdc42783 lw a5,-36(s0) + 3006e70: 439c lw a5,0(a5) + 3006e72: 43f4 lw a3,68(a5) + 3006e74: fdc42783 lw a5,-36(s0) + 3006e78: 439c lw a5,0(a5) + 3006e7a: 00020737 lui a4,0x20 + 3006e7e: 05070713 addi a4,a4,80 # 20050 + 3006e82: 8f55 or a4,a4,a3 + 3006e84: c3f8 sw a4,68(a5) + 3006e86: fdc42783 lw a5,-36(s0) + 3006e8a: 4fbc lw a5,88(a5) + 3006e8c: cf81 beqz a5,3006ea4 + 3006e8e: fdc42783 lw a5,-36(s0) + 3006e92: 579c lw a5,40(a5) + 3006e94: eb81 bnez a5,3006ea4 + 3006e96: fdc42783 lw a5,-36(s0) + 3006e9a: 4fbc lw a5,88(a5) + 3006e9c: fdc42503 lw a0,-36(s0) + 3006ea0: 9782 jalr a5 + 3006ea2: 0001 nop + 3006ea4: 0001 nop + 3006ea6: 50b2 lw ra,44(sp) + 3006ea8: 5422 lw s0,40(sp) + 3006eaa: 6145 addi sp,sp,48 + 3006eac: 8082 ret + +03006eae : + 3006eae: b5afa06f j 3001208 + +03006eb2 : + 3006eb2: 7179 addi sp,sp,-48 + 3006eb4: d606 sw ra,44(sp) + 3006eb6: d422 sw s0,40(sp) + 3006eb8: 1800 addi s0,sp,48 + 3006eba: fca42e23 sw a0,-36(s0) + 3006ebe: fe042623 sw zero,-20(s0) + 3006ec2: fdc42783 lw a5,-36(s0) + 3006ec6: 439c lw a5,0(a5) + 3006ec8: 43bc lw a5,64(a5) + 3006eca: 83a9 srli a5,a5,0xa + 3006ecc: 8b85 andi a5,a5,1 + 3006ece: 0ff7f713 andi a4,a5,255 + 3006ed2: 4785 li a5,1 + 3006ed4: 02f71763 bne a4,a5,3006f02 + 3006ed8: fdc42783 lw a5,-36(s0) + 3006edc: 439c lw a5,0(a5) + 3006ede: 43bc lw a5,64(a5) + 3006ee0: 83a9 srli a5,a5,0xa + 3006ee2: 8b85 andi a5,a5,1 + 3006ee4: 9f81 uxtb a5 + 3006ee6: 873e mv a4,a5 + 3006ee8: fec42783 lw a5,-20(s0) + 3006eec: 8fd9 or a5,a5,a4 + 3006eee: fef42623 sw a5,-20(s0) + 3006ef2: fdc42783 lw a5,-36(s0) + 3006ef6: 4398 lw a4,0(a5) + 3006ef8: 437c lw a5,68(a4) + 3006efa: 4007e793 ori a5,a5,1024 + 3006efe: c37c sw a5,68(a4) + 3006f00: a0c1 j 3006fc0 + 3006f02: fdc42783 lw a5,-36(s0) + 3006f06: 439c lw a5,0(a5) + 3006f08: 43bc lw a5,64(a5) + 3006f0a: 83a5 srli a5,a5,0x9 + 3006f0c: 8b85 andi a5,a5,1 + 3006f0e: 0ff7f713 andi a4,a5,255 + 3006f12: 4785 li a5,1 + 3006f14: 02f71763 bne a4,a5,3006f42 + 3006f18: fdc42783 lw a5,-36(s0) + 3006f1c: 439c lw a5,0(a5) + 3006f1e: 43bc lw a5,64(a5) + 3006f20: 83a5 srli a5,a5,0x9 + 3006f22: 8b85 andi a5,a5,1 + 3006f24: 9f81 uxtb a5 + 3006f26: 873e mv a4,a5 + 3006f28: fec42783 lw a5,-20(s0) + 3006f2c: 8fd9 or a5,a5,a4 + 3006f2e: fef42623 sw a5,-20(s0) + 3006f32: fdc42783 lw a5,-36(s0) + 3006f36: 4398 lw a4,0(a5) + 3006f38: 437c lw a5,68(a4) + 3006f3a: 2007e793 ori a5,a5,512 + 3006f3e: c37c sw a5,68(a4) + 3006f40: a041 j 3006fc0 + 3006f42: fdc42783 lw a5,-36(s0) + 3006f46: 439c lw a5,0(a5) + 3006f48: 43bc lw a5,64(a5) + 3006f4a: 83a1 srli a5,a5,0x8 + 3006f4c: 8b85 andi a5,a5,1 + 3006f4e: 0ff7f713 andi a4,a5,255 + 3006f52: 4785 li a5,1 + 3006f54: 02f71763 bne a4,a5,3006f82 + 3006f58: fdc42783 lw a5,-36(s0) + 3006f5c: 439c lw a5,0(a5) + 3006f5e: 43bc lw a5,64(a5) + 3006f60: 83a1 srli a5,a5,0x8 + 3006f62: 8b85 andi a5,a5,1 + 3006f64: 9f81 uxtb a5 + 3006f66: 873e mv a4,a5 + 3006f68: fec42783 lw a5,-20(s0) + 3006f6c: 8fd9 or a5,a5,a4 + 3006f6e: fef42623 sw a5,-20(s0) + 3006f72: fdc42783 lw a5,-36(s0) + 3006f76: 4398 lw a4,0(a5) + 3006f78: 437c lw a5,68(a4) + 3006f7a: 1007e793 ori a5,a5,256 + 3006f7e: c37c sw a5,68(a4) + 3006f80: a081 j 3006fc0 + 3006f82: fdc42783 lw a5,-36(s0) + 3006f86: 439c lw a5,0(a5) + 3006f88: 43bc lw a5,64(a5) + 3006f8a: 839d srli a5,a5,0x7 + 3006f8c: 8b85 andi a5,a5,1 + 3006f8e: 0ff7f713 andi a4,a5,255 + 3006f92: 4785 li a5,1 + 3006f94: 02f71663 bne a4,a5,3006fc0 + 3006f98: fdc42783 lw a5,-36(s0) + 3006f9c: 439c lw a5,0(a5) + 3006f9e: 43bc lw a5,64(a5) + 3006fa0: 839d srli a5,a5,0x7 + 3006fa2: 8b85 andi a5,a5,1 + 3006fa4: 9f81 uxtb a5 + 3006fa6: 873e mv a4,a5 + 3006fa8: fec42783 lw a5,-20(s0) + 3006fac: 8fd9 or a5,a5,a4 + 3006fae: fef42623 sw a5,-20(s0) + 3006fb2: fdc42783 lw a5,-36(s0) + 3006fb6: 4398 lw a4,0(a5) + 3006fb8: 437c lw a5,68(a4) + 3006fba: 0807e793 ori a5,a5,128 + 3006fbe: c37c sw a5,68(a4) + 3006fc0: fec42783 lw a5,-20(s0) + 3006fc4: c79d beqz a5,3006ff2 + 3006fc6: fdc42783 lw a5,-36(s0) + 3006fca: fec42703 lw a4,-20(s0) + 3006fce: cbb8 sw a4,80(a5) + 3006fd0: fdc42783 lw a5,-36(s0) + 3006fd4: 4f98 lw a4,24(a5) + 3006fd6: 4785 li a5,1 + 3006fd8: 00f71d63 bne a4,a5,3006ff2 + 3006fdc: fdc42783 lw a5,-36(s0) + 3006fe0: 53fc lw a5,100(a5) + 3006fe2: cb81 beqz a5,3006ff2 + 3006fe4: fdc42783 lw a5,-36(s0) + 3006fe8: 53fc lw a5,100(a5) + 3006fea: fdc42503 lw a0,-36(s0) + 3006fee: 9782 jalr a5 + 3006ff0: 0001 nop + 3006ff2: 0001 nop + 3006ff4: 50b2 lw ra,44(sp) + 3006ff6: 5422 lw s0,40(sp) + 3006ff8: 6145 addi sp,sp,48 + 3006ffa: 8082 ret + +03006ffc : + 3006ffc: 7179 addi sp,sp,-48 + 3006ffe: d606 sw ra,44(sp) + 3007000: d422 sw s0,40(sp) + 3007002: 1800 addi s0,sp,48 + 3007004: fca42e23 sw a0,-36(s0) + 3007008: fdc42783 lw a5,-36(s0) + 300700c: eb89 bnez a5,300701e + 300700e: 2d200593 li a1,722 + 3007012: 030097b7 lui a5,0x3009 + 3007016: ac078513 addi a0,a5,-1344 # 3008ac0 + 300701a: 3d51 jal ra,3006eae + 300701c: a001 j 300701c + 300701e: fdc42783 lw a5,-36(s0) + 3007022: fef42623 sw a5,-20(s0) + 3007026: fec42783 lw a5,-20(s0) + 300702a: 4398 lw a4,0(a5) + 300702c: 140007b7 lui a5,0x14000 + 3007030: 02f70f63 beq a4,a5,300706e + 3007034: fec42783 lw a5,-20(s0) + 3007038: 4398 lw a4,0(a5) + 300703a: 140017b7 lui a5,0x14001 + 300703e: 02f70863 beq a4,a5,300706e + 3007042: fec42783 lw a5,-20(s0) + 3007046: 4398 lw a4,0(a5) + 3007048: 140027b7 lui a5,0x14002 + 300704c: 02f70163 beq a4,a5,300706e + 3007050: fec42783 lw a5,-20(s0) + 3007054: 4398 lw a4,0(a5) + 3007056: 140037b7 lui a5,0x14003 + 300705a: 00f70a63 beq a4,a5,300706e + 300705e: 2d400593 li a1,724 + 3007062: 030097b7 lui a5,0x3009 + 3007066: ac078513 addi a0,a5,-1344 # 3008ac0 + 300706a: 3591 jal ra,3006eae + 300706c: a001 j 300706c + 300706e: fec42783 lw a5,-20(s0) + 3007072: 439c lw a5,0(a5) + 3007074: 43bc lw a5,64(a5) + 3007076: 8395 srli a5,a5,0x5 + 3007078: 8b85 andi a5,a5,1 + 300707a: 0ff7f713 andi a4,a5,255 + 300707e: 4785 li a5,1 + 3007080: 00f70d63 beq a4,a5,300709a + 3007084: fec42783 lw a5,-20(s0) + 3007088: 439c lw a5,0(a5) + 300708a: 43bc lw a5,64(a5) + 300708c: 83b1 srli a5,a5,0xc + 300708e: 8b85 andi a5,a5,1 + 3007090: 0ff7f713 andi a4,a5,255 + 3007094: 4785 li a5,1 + 3007096: 00f71563 bne a4,a5,30070a0 + 300709a: fec42503 lw a0,-20(s0) + 300709e: 3c1d jal ra,3006ad4 + 30070a0: fec42783 lw a5,-20(s0) + 30070a4: 439c lw a5,0(a5) + 30070a6: 43bc lw a5,64(a5) + 30070a8: 8391 srli a5,a5,0x4 + 30070aa: 8b85 andi a5,a5,1 + 30070ac: 0ff7f713 andi a4,a5,255 + 30070b0: 4785 li a5,1 + 30070b2: 02f70863 beq a4,a5,30070e2 + 30070b6: fec42783 lw a5,-20(s0) + 30070ba: 439c lw a5,0(a5) + 30070bc: 43bc lw a5,64(a5) + 30070be: 8399 srli a5,a5,0x6 + 30070c0: 8b85 andi a5,a5,1 + 30070c2: 0ff7f713 andi a4,a5,255 + 30070c6: 4785 li a5,1 + 30070c8: 00f70d63 beq a4,a5,30070e2 + 30070cc: fec42783 lw a5,-20(s0) + 30070d0: 439c lw a5,0(a5) + 30070d2: 43bc lw a5,64(a5) + 30070d4: 83c5 srli a5,a5,0x11 + 30070d6: 8b85 andi a5,a5,1 + 30070d8: 0ff7f713 andi a4,a5,255 + 30070dc: 4785 li a5,1 + 30070de: 00f71563 bne a4,a5,30070e8 + 30070e2: fec42503 lw a0,-20(s0) + 30070e6: 398d jal ra,3006d58 + 30070e8: fec42783 lw a5,-20(s0) + 30070ec: 439c lw a5,0(a5) + 30070ee: 43bc lw a5,64(a5) + 30070f0: 83d5 srli a5,a5,0x15 + 30070f2: 8b85 andi a5,a5,1 + 30070f4: 0ff7f713 andi a4,a5,255 + 30070f8: 4785 li a5,1 + 30070fa: 00f71663 bne a4,a5,3007106 + 30070fe: fec42503 lw a0,-20(s0) + 3007102: afaff0ef jal ra,30063fc + 3007106: fec42783 lw a5,-20(s0) + 300710a: 439c lw a5,0(a5) + 300710c: 43bc lw a5,64(a5) + 300710e: 83cd srli a5,a5,0x13 + 3007110: 8b85 andi a5,a5,1 + 3007112: 0ff7f713 andi a4,a5,255 + 3007116: 4785 li a5,1 + 3007118: 00f70d63 beq a4,a5,3007132 + 300711c: fec42783 lw a5,-20(s0) + 3007120: 439c lw a5,0(a5) + 3007122: 43bc lw a5,64(a5) + 3007124: 83d1 srli a5,a5,0x14 + 3007126: 8b85 andi a5,a5,1 + 3007128: 0ff7f713 andi a4,a5,255 + 300712c: 4785 li a5,1 + 300712e: 00f71663 bne a4,a5,300713a + 3007132: fec42503 lw a0,-20(s0) + 3007136: 9eaff0ef jal ra,3006320 + 300713a: fec42783 lw a5,-20(s0) + 300713e: 439c lw a5,0(a5) + 3007140: 43bc lw a5,64(a5) + 3007142: 7807f793 andi a5,a5,1920 + 3007146: c789 beqz a5,3007150 + 3007148: fec42503 lw a0,-20(s0) + 300714c: 339d jal ra,3006eb2 + 300714e: 0001 nop + 3007150: 0001 nop + 3007152: 50b2 lw ra,44(sp) + 3007154: 5422 lw s0,40(sp) + 3007156: 6145 addi sp,sp,48 + 3007158: 8082 ret + +0300715a : + 300715a: 1101 addi sp,sp,-32 + 300715c: ce06 sw ra,28(sp) + 300715e: cc22 sw s0,24(sp) + 3007160: 1000 addi s0,sp,32 + 3007162: fea42623 sw a0,-20(s0) + 3007166: feb42423 sw a1,-24(s0) + 300716a: fec42223 sw a2,-28(s0) + 300716e: fec42783 lw a5,-20(s0) + 3007172: eb89 bnez a5,3007184 + 3007174: 2f800593 li a1,760 + 3007178: 030097b7 lui a5,0x3009 + 300717c: ac078513 addi a0,a5,-1344 # 3008ac0 + 3007180: 333d jal ra,3006eae + 3007182: a001 j 3007182 + 3007184: fec42783 lw a5,-20(s0) + 3007188: 4398 lw a4,0(a5) + 300718a: 140007b7 lui a5,0x14000 + 300718e: 02f70f63 beq a4,a5,30071cc + 3007192: fec42783 lw a5,-20(s0) + 3007196: 4398 lw a4,0(a5) + 3007198: 140017b7 lui a5,0x14001 + 300719c: 02f70863 beq a4,a5,30071cc + 30071a0: fec42783 lw a5,-20(s0) + 30071a4: 4398 lw a4,0(a5) + 30071a6: 140027b7 lui a5,0x14002 + 30071aa: 02f70163 beq a4,a5,30071cc + 30071ae: fec42783 lw a5,-20(s0) + 30071b2: 4398 lw a4,0(a5) + 30071b4: 140037b7 lui a5,0x14003 + 30071b8: 00f70a63 beq a4,a5,30071cc + 30071bc: 2f900593 li a1,761 + 30071c0: 030097b7 lui a5,0x3009 + 30071c4: ac078513 addi a0,a5,-1344 # 3008ac0 + 30071c8: 31dd jal ra,3006eae + 30071ca: a001 j 30071ca + 30071cc: fe842703 lw a4,-24(s0) + 30071d0: 47a1 li a5,8 + 30071d2: 08e7e363 bltu a5,a4,3007258 + 30071d6: fe842783 lw a5,-24(s0) + 30071da: 00279713 slli a4,a5,0x2 + 30071de: 030097b7 lui a5,0x3009 + 30071e2: adc78793 addi a5,a5,-1316 # 3008adc + 30071e6: 97ba add a5,a5,a4 + 30071e8: 439c lw a5,0(a5) + 30071ea: 8782 jr a5 + 30071ec: fec42783 lw a5,-20(s0) + 30071f0: fe442703 lw a4,-28(s0) + 30071f4: cbf8 sw a4,84(a5) + 30071f6: a09d j 300725c + 30071f8: fec42783 lw a5,-20(s0) + 30071fc: fe442703 lw a4,-28(s0) + 3007200: cfb8 sw a4,88(a5) + 3007202: a8a9 j 300725c + 3007204: fec42783 lw a5,-20(s0) + 3007208: fe442703 lw a4,-28(s0) + 300720c: cff8 sw a4,92(a5) + 300720e: a0b9 j 300725c + 3007210: fec42783 lw a5,-20(s0) + 3007214: fe442703 lw a4,-28(s0) + 3007218: d3b8 sw a4,96(a5) + 300721a: a089 j 300725c + 300721c: fec42783 lw a5,-20(s0) + 3007220: fe442703 lw a4,-28(s0) + 3007224: d3f8 sw a4,100(a5) + 3007226: a81d j 300725c + 3007228: fec42783 lw a5,-20(s0) + 300722c: fe442703 lw a4,-28(s0) + 3007230: d7b8 sw a4,104(a5) + 3007232: a02d j 300725c + 3007234: fec42783 lw a5,-20(s0) + 3007238: fe442703 lw a4,-28(s0) + 300723c: d7f8 sw a4,108(a5) + 300723e: a839 j 300725c + 3007240: fec42783 lw a5,-20(s0) + 3007244: fe442703 lw a4,-28(s0) + 3007248: dbb8 sw a4,112(a5) + 300724a: a809 j 300725c + 300724c: fec42783 lw a5,-20(s0) + 3007250: fe442703 lw a4,-28(s0) + 3007254: dbf8 sw a4,116(a5) + 3007256: a019 j 300725c + 3007258: 4785 li a5,1 + 300725a: a011 j 300725e + 300725c: 4781 li a5,0 + 300725e: 853e mv a0,a5 + 3007260: 40f2 lw ra,28(sp) + 3007262: 4462 lw s0,24(sp) + 3007264: 6105 addi sp,sp,32 + 3007266: 8082 ret + +03007268
: + 3007268: 1141 addi sp,sp,-16 + 300726a: c606 sw ra,12(sp) + 300726c: c422 sw s0,8(sp) + 300726e: 0800 addi s0,sp,16 + 3007270: 42e010ef jal ra,300869e + 3007274: 4605 li a2,1 + 3007276: 040007b7 lui a5,0x4000 + 300727a: 78c78593 addi a1,a5,1932 # 400078c + 300727e: 040007b7 lui a5,0x4000 + 3007282: 50478513 addi a0,a5,1284 # 4000504 + 3007286: 3245 jal ra,3006c26 + 3007288: 4605 li a2,1 + 300728a: 040007b7 lui a5,0x4000 + 300728e: 7fc78593 addi a1,a5,2044 # 40007fc + 3007292: 040007b7 lui a5,0x4000 + 3007296: 58478513 addi a0,a5,1412 # 4000584 + 300729a: 3271 jal ra,3006c26 + 300729c: 040007b7 lui a5,0x4000 + 30072a0: 4b478513 addi a0,a5,1204 # 40004b4 + 30072a4: d5ffe0ef jal ra,3006002 + 30072a8: 040007b7 lui a5,0x4000 + 30072ac: 4dc78513 addi a0,a5,1244 # 40004dc + 30072b0: d53fe0ef jal ra,3006002 + 30072b4: 2bd5 jal ra,30078a8 + 30072b6: 040007b7 lui a5,0x4000 + 30072ba: 7f47a703 lw a4,2036(a5) # 40007f4 + 30072be: 040007b7 lui a5,0x4000 + 30072c2: 7f87a783 lw a5,2040(a5) # 40007f8 + 30072c6: 04f70663 beq a4,a5,3007312 + 30072ca: 040007b7 lui a5,0x4000 + 30072ce: 7f87a783 lw a5,2040(a5) # 40007f8 + 30072d2: 00178693 addi a3,a5,1 + 30072d6: 04000737 lui a4,0x4000 + 30072da: 7ed72c23 sw a3,2040(a4) # 40007f8 + 30072de: 04000737 lui a4,0x4000 + 30072e2: 79070713 addi a4,a4,1936 # 4000790 + 30072e6: 97ba add a5,a5,a4 + 30072e8: 3e800693 li a3,1000 + 30072ec: 4605 li a2,1 + 30072ee: 85be mv a1,a5 + 30072f0: 040007b7 lui a5,0x4000 + 30072f4: 50478513 addi a0,a5,1284 # 4000504 + 30072f8: 2579 jal ra,3007986 + 30072fa: 040007b7 lui a5,0x4000 + 30072fe: 7f87a703 lw a4,2040(a5) # 40007f8 + 3007302: 06400793 li a5,100 + 3007306: 02f77733 remu a4,a4,a5 + 300730a: 040007b7 lui a5,0x4000 + 300730e: 7ee7ac23 sw a4,2040(a5) # 40007f8 + 3007312: 040037b7 lui a5,0x4003 + 3007316: 0007a703 lw a4,0(a5) # 4003000 + 300731a: 040037b7 lui a5,0x4003 + 300731e: 0047a783 lw a5,4(a5) # 4003004 + 3007322: 10f70963 beq a4,a5,3007434 + 3007326: 040037b7 lui a5,0x4003 + 300732a: 00878793 addi a5,a5,8 # 4003008 + 300732e: 3398 lbu a4,1(a5) + 3007330: 040037b7 lui a5,0x4003 + 3007334: 00e78423 sb a4,8(a5) # 4003008 + 3007338: 040037b7 lui a5,0x4003 + 300733c: 00878793 addi a5,a5,8 # 4003008 + 3007340: 23b8 lbu a4,2(a5) + 3007342: 040037b7 lui a5,0x4003 + 3007346: 00878793 addi a5,a5,8 # 4003008 + 300734a: b398 sb a4,1(a5) + 300734c: 040037b7 lui a5,0x4003 + 3007350: 00878793 addi a5,a5,8 # 4003008 + 3007354: 33b8 lbu a4,3(a5) + 3007356: 040037b7 lui a5,0x4003 + 300735a: 00878793 addi a5,a5,8 # 4003008 + 300735e: a3b8 sb a4,2(a5) + 3007360: 040037b7 lui a5,0x4003 + 3007364: 0047a783 lw a5,4(a5) # 4003004 + 3007368: 04001737 lui a4,0x4001 + 300736c: 80070713 addi a4,a4,-2048 # 4000800 + 3007370: 97ba add a5,a5,a4 + 3007372: 2398 lbu a4,0(a5) + 3007374: 040037b7 lui a5,0x4003 + 3007378: 00878793 addi a5,a5,8 # 4003008 + 300737c: b3b8 sb a4,3(a5) + 300737e: 040037b7 lui a5,0x4003 + 3007382: 0047a783 lw a5,4(a5) # 4003004 + 3007386: 00178693 addi a3,a5,1 + 300738a: 04003737 lui a4,0x4003 + 300738e: 00d72223 sw a3,4(a4) # 4003004 + 3007392: 04001737 lui a4,0x4001 + 3007396: 80070713 addi a4,a4,-2048 # 4000800 + 300739a: 97ba add a5,a5,a4 + 300739c: 3e800693 li a3,1000 + 30073a0: 4605 li a2,1 + 30073a2: 85be mv a1,a5 + 30073a4: 040007b7 lui a5,0x4000 + 30073a8: 50478513 addi a0,a5,1284 # 4000504 + 30073ac: 2be9 jal ra,3007986 + 30073ae: 040037b7 lui a5,0x4003 + 30073b2: 0047a703 lw a4,4(a5) # 4003004 + 30073b6: 678d lui a5,0x3 + 30073b8: 80078793 addi a5,a5,-2048 # 2800 + 30073bc: 02f77733 remu a4,a4,a5 + 30073c0: 040037b7 lui a5,0x4003 + 30073c4: 00e7a223 sw a4,4(a5) # 4003004 + 30073c8: 040037b7 lui a5,0x4003 + 30073cc: 0087c703 lbu a4,8(a5) # 4003008 + 30073d0: 03100793 li a5,49 + 30073d4: 06f71063 bne a4,a5,3007434 + 30073d8: 040037b7 lui a5,0x4003 + 30073dc: 00878793 addi a5,a5,8 # 4003008 + 30073e0: 3398 lbu a4,1(a5) + 30073e2: 03000793 li a5,48 + 30073e6: 04f71763 bne a4,a5,3007434 + 30073ea: 040037b7 lui a5,0x4003 + 30073ee: 00878793 addi a5,a5,8 # 4003008 + 30073f2: 23b8 lbu a4,2(a5) + 30073f4: 03000793 li a5,48 + 30073f8: 02f71e63 bne a4,a5,3007434 + 30073fc: 040037b7 lui a5,0x4003 + 3007400: 00878793 addi a5,a5,8 # 4003008 + 3007404: 33b8 lbu a4,3(a5) + 3007406: 03100793 li a5,49 + 300740a: 00f71763 bne a4,a5,3007418 + 300740e: 040037b7 lui a5,0x4003 + 3007412: 000786a3 sb zero,13(a5) # 400300d + 3007416: a839 j 3007434 + 3007418: 040037b7 lui a5,0x4003 + 300741c: 00878793 addi a5,a5,8 # 4003008 + 3007420: 33b8 lbu a4,3(a5) + 3007422: 03200793 li a5,50 + 3007426: 00f71763 bne a4,a5,3007434 + 300742a: 040037b7 lui a5,0x4003 + 300742e: 4705 li a4,1 + 3007430: 00e786a3 sb a4,13(a5) # 400300d + 3007434: 2b99 jal ra,300798a + 3007436: b541 j 30072b6 + +03007438 : + 3007438: 7179 addi sp,sp,-48 + 300743a: d606 sw ra,44(sp) + 300743c: d422 sw s0,40(sp) + 300743e: 1800 addi s0,sp,48 + 3007440: fca42e23 sw a0,-36(s0) + 3007444: fdc42783 lw a5,-36(s0) + 3007448: fef42623 sw a5,-20(s0) + 300744c: 040037b7 lui a5,0x4003 + 3007450: 00d7c783 lbu a5,13(a5) # 400300d + 3007454: ef91 bnez a5,3007470 + 3007456: 040037b7 lui a5,0x4003 + 300745a: 4705 li a4,1 + 300745c: 00e786a3 sb a4,13(a5) # 400300d + 3007460: 4601 li a2,0 + 3007462: 45a1 li a1,8 + 3007464: 040007b7 lui a5,0x4000 + 3007468: 66c78513 addi a0,a5,1644 # 400066c + 300746c: 260d jal ra,300778e + 300746e: a821 j 3007486 + 3007470: 040037b7 lui a5,0x4003 + 3007474: 000786a3 sb zero,13(a5) # 400300d + 3007478: 4605 li a2,1 + 300747a: 45a1 li a1,8 + 300747c: 040007b7 lui a5,0x4000 + 3007480: 66c78513 addi a0,a5,1644 # 400066c + 3007484: 2629 jal ra,300778e + 3007486: 0001 nop + 3007488: 50b2 lw ra,44(sp) + 300748a: 5422 lw s0,40(sp) + 300748c: 6145 addi sp,sp,48 + 300748e: 8082 ret + +03007490 : + 3007490: 1101 addi sp,sp,-32 + 3007492: ce06 sw ra,28(sp) + 3007494: cc22 sw s0,24(sp) + 3007496: 1000 addi s0,sp,32 + 3007498: fea42623 sw a0,-20(s0) + 300749c: 4605 li a2,1 + 300749e: 040007b7 lui a5,0x4000 + 30074a2: 78c78593 addi a1,a5,1932 # 400078c + 30074a6: 040007b7 lui a5,0x4000 + 30074aa: 50478513 addi a0,a5,1284 # 4000504 + 30074ae: f78ff0ef jal ra,3006c26 + 30074b2: 040007b7 lui a5,0x4000 + 30074b6: 7f47a783 lw a5,2036(a5) # 40007f4 + 30074ba: 00178693 addi a3,a5,1 + 30074be: 04000737 lui a4,0x4000 + 30074c2: 7ed72a23 sw a3,2036(a4) # 40007f4 + 30074c6: 04000737 lui a4,0x4000 + 30074ca: 78c74703 lbu a4,1932(a4) # 400078c + 30074ce: 040006b7 lui a3,0x4000 + 30074d2: 79068693 addi a3,a3,1936 # 4000790 + 30074d6: 97b6 add a5,a5,a3 + 30074d8: a398 sb a4,0(a5) + 30074da: 040007b7 lui a5,0x4000 + 30074de: 7f47a703 lw a4,2036(a5) # 40007f4 + 30074e2: 06400793 li a5,100 + 30074e6: 02f77733 remu a4,a4,a5 + 30074ea: 040007b7 lui a5,0x4000 + 30074ee: 7ee7aa23 sw a4,2036(a5) # 40007f4 + 30074f2: 0001 nop + 30074f4: 40f2 lw ra,28(sp) + 30074f6: 4462 lw s0,24(sp) + 30074f8: 6105 addi sp,sp,32 + 30074fa: 8082 ret + +030074fc : + 30074fc: 1101 addi sp,sp,-32 + 30074fe: ce06 sw ra,28(sp) + 3007500: cc22 sw s0,24(sp) + 3007502: 1000 addi s0,sp,32 + 3007504: fea42623 sw a0,-20(s0) + 3007508: 4605 li a2,1 + 300750a: 040007b7 lui a5,0x4000 + 300750e: 7fc78593 addi a1,a5,2044 # 40007fc + 3007512: 040007b7 lui a5,0x4000 + 3007516: 58478513 addi a0,a5,1412 # 4000584 + 300751a: f0cff0ef jal ra,3006c26 + 300751e: 040037b7 lui a5,0x4003 + 3007522: 0007a783 lw a5,0(a5) # 4003000 + 3007526: 00178693 addi a3,a5,1 + 300752a: 04003737 lui a4,0x4003 + 300752e: 00d72023 sw a3,0(a4) # 4003000 + 3007532: 04000737 lui a4,0x4000 + 3007536: 7fc74703 lbu a4,2044(a4) # 40007fc + 300753a: 040016b7 lui a3,0x4001 + 300753e: 80068693 addi a3,a3,-2048 # 4000800 + 3007542: 97b6 add a5,a5,a3 + 3007544: a398 sb a4,0(a5) + 3007546: 040037b7 lui a5,0x4003 + 300754a: 0007a703 lw a4,0(a5) # 4003000 + 300754e: 678d lui a5,0x3 + 3007550: 80078793 addi a5,a5,-2048 # 2800 + 3007554: 02f77733 remu a4,a4,a5 + 3007558: 040037b7 lui a5,0x4003 + 300755c: 00e7a023 sw a4,0(a5) # 4003000 + 3007560: 0001 nop + 3007562: 40f2 lw ra,28(sp) + 3007564: 4462 lw s0,24(sp) + 3007566: 6105 addi sp,sp,32 + 3007568: 8082 ret + +0300756a : + 300756a: 1101 addi sp,sp,-32 + 300756c: ce06 sw ra,28(sp) + 300756e: cc22 sw s0,24(sp) + 3007570: 1000 addi s0,sp,32 + 3007572: fea42623 sw a0,-20(s0) + 3007576: 040037b7 lui a5,0x4003 + 300757a: 00d7c703 lbu a4,13(a5) # 400300d + 300757e: 4785 li a5,1 + 3007580: 00f71d63 bne a4,a5,300759a + 3007584: 040037b7 lui a5,0x4003 + 3007588: 0107a783 lw a5,16(a5) # 4003010 + 300758c: 00178713 addi a4,a5,1 + 3007590: 040037b7 lui a5,0x4003 + 3007594: 00e7a823 sw a4,16(a5) # 4003010 + 3007598: a0b1 j 30075e4 + 300759a: 040037b7 lui a5,0x4003 + 300759e: 00078623 sb zero,12(a5) # 400300c + 30075a2: 040037b7 lui a5,0x4003 + 30075a6: 0007a823 sw zero,16(a5) # 4003010 + 30075aa: 4601 li a2,0 + 30075ac: 4591 li a1,4 + 30075ae: 040007b7 lui a5,0x4000 + 30075b2: 6fc78513 addi a0,a5,1788 # 40006fc + 30075b6: 2ae1 jal ra,300778e + 30075b8: 4601 li a2,0 + 30075ba: 04000593 li a1,64 + 30075be: 040007b7 lui a5,0x4000 + 30075c2: 74478513 addi a0,a5,1860 # 4000744 + 30075c6: 22e1 jal ra,300778e + 30075c8: 4601 li a2,0 + 30075ca: 45a1 li a1,8 + 30075cc: 040007b7 lui a5,0x4000 + 30075d0: 6fc78513 addi a0,a5,1788 # 40006fc + 30075d4: 2a6d jal ra,300778e + 30075d6: 4601 li a2,0 + 30075d8: 4589 li a1,2 + 30075da: 040007b7 lui a5,0x4000 + 30075de: 6fc78513 addi a0,a5,1788 # 40006fc + 30075e2: 2275 jal ra,300778e + 30075e4: 040037b7 lui a5,0x4003 + 30075e8: 0107a703 lw a4,16(a5) # 4003010 + 30075ec: 47a9 li a5,10 + 30075ee: 18e7fa63 bgeu a5,a4,3007782 + 30075f2: 040037b7 lui a5,0x4003 + 30075f6: 0007a823 sw zero,16(a5) # 4003010 + 30075fa: 040037b7 lui a5,0x4003 + 30075fe: 00c7c783 lbu a5,12(a5) # 400300c + 3007602: 4711 li a4,4 + 3007604: 16f76a63 bltu a4,a5,3007778 + 3007608: 00279713 slli a4,a5,0x2 + 300760c: 030097b7 lui a5,0x3009 + 3007610: b0078793 addi a5,a5,-1280 # 3008b00 + 3007614: 97ba add a5,a5,a4 + 3007616: 439c lw a5,0(a5) + 3007618: 8782 jr a5 + 300761a: 040037b7 lui a5,0x4003 + 300761e: 4705 li a4,1 + 3007620: 00e78623 sb a4,12(a5) # 400300c + 3007624: 4601 li a2,0 + 3007626: 4591 li a1,4 + 3007628: 040007b7 lui a5,0x4000 + 300762c: 6fc78513 addi a0,a5,1788 # 40006fc + 3007630: 2ab9 jal ra,300778e + 3007632: 4601 li a2,0 + 3007634: 04000593 li a1,64 + 3007638: 040007b7 lui a5,0x4000 + 300763c: 74478513 addi a0,a5,1860 # 4000744 + 3007640: 22b9 jal ra,300778e + 3007642: 4601 li a2,0 + 3007644: 45a1 li a1,8 + 3007646: 040007b7 lui a5,0x4000 + 300764a: 6fc78513 addi a0,a5,1788 # 40006fc + 300764e: 2281 jal ra,300778e + 3007650: 4601 li a2,0 + 3007652: 4589 li a1,2 + 3007654: 040007b7 lui a5,0x4000 + 3007658: 6fc78513 addi a0,a5,1788 # 40006fc + 300765c: 2a0d jal ra,300778e + 300765e: a21d j 3007784 + 3007660: 040037b7 lui a5,0x4003 + 3007664: 4709 li a4,2 + 3007666: 00e78623 sb a4,12(a5) # 400300c + 300766a: 4605 li a2,1 + 300766c: 4591 li a1,4 + 300766e: 040007b7 lui a5,0x4000 + 3007672: 6fc78513 addi a0,a5,1788 # 40006fc + 3007676: 2a21 jal ra,300778e + 3007678: 4601 li a2,0 + 300767a: 04000593 li a1,64 + 300767e: 040007b7 lui a5,0x4000 + 3007682: 74478513 addi a0,a5,1860 # 4000744 + 3007686: 2221 jal ra,300778e + 3007688: 4601 li a2,0 + 300768a: 45a1 li a1,8 + 300768c: 040007b7 lui a5,0x4000 + 3007690: 6fc78513 addi a0,a5,1788 # 40006fc + 3007694: 28ed jal ra,300778e + 3007696: 4601 li a2,0 + 3007698: 4589 li a1,2 + 300769a: 040007b7 lui a5,0x4000 + 300769e: 6fc78513 addi a0,a5,1788 # 40006fc + 30076a2: 20f5 jal ra,300778e + 30076a4: a0c5 j 3007784 + 30076a6: 040037b7 lui a5,0x4003 + 30076aa: 470d li a4,3 + 30076ac: 00e78623 sb a4,12(a5) # 400300c + 30076b0: 4601 li a2,0 + 30076b2: 4591 li a1,4 + 30076b4: 040007b7 lui a5,0x4000 + 30076b8: 6fc78513 addi a0,a5,1788 # 40006fc + 30076bc: 28c9 jal ra,300778e + 30076be: 4605 li a2,1 + 30076c0: 04000593 li a1,64 + 30076c4: 040007b7 lui a5,0x4000 + 30076c8: 74478513 addi a0,a5,1860 # 4000744 + 30076cc: 20c9 jal ra,300778e + 30076ce: 4601 li a2,0 + 30076d0: 45a1 li a1,8 + 30076d2: 040007b7 lui a5,0x4000 + 30076d6: 6fc78513 addi a0,a5,1788 # 40006fc + 30076da: 2855 jal ra,300778e + 30076dc: 4601 li a2,0 + 30076de: 4589 li a1,2 + 30076e0: 040007b7 lui a5,0x4000 + 30076e4: 6fc78513 addi a0,a5,1788 # 40006fc + 30076e8: 205d jal ra,300778e + 30076ea: a869 j 3007784 + 30076ec: 040037b7 lui a5,0x4003 + 30076f0: 4711 li a4,4 + 30076f2: 00e78623 sb a4,12(a5) # 400300c + 30076f6: 4601 li a2,0 + 30076f8: 4591 li a1,4 + 30076fa: 040007b7 lui a5,0x4000 + 30076fe: 6fc78513 addi a0,a5,1788 # 40006fc + 3007702: 2071 jal ra,300778e + 3007704: 4601 li a2,0 + 3007706: 04000593 li a1,64 + 300770a: 040007b7 lui a5,0x4000 + 300770e: 74478513 addi a0,a5,1860 # 4000744 + 3007712: 28b5 jal ra,300778e + 3007714: 4605 li a2,1 + 3007716: 45a1 li a1,8 + 3007718: 040007b7 lui a5,0x4000 + 300771c: 6fc78513 addi a0,a5,1788 # 40006fc + 3007720: 20bd jal ra,300778e + 3007722: 4601 li a2,0 + 3007724: 4589 li a1,2 + 3007726: 040007b7 lui a5,0x4000 + 300772a: 6fc78513 addi a0,a5,1788 # 40006fc + 300772e: 2085 jal ra,300778e + 3007730: a891 j 3007784 + 3007732: 040037b7 lui a5,0x4003 + 3007736: 4705 li a4,1 + 3007738: 00e78623 sb a4,12(a5) # 400300c + 300773c: 4601 li a2,0 + 300773e: 4591 li a1,4 + 3007740: 040007b7 lui a5,0x4000 + 3007744: 6fc78513 addi a0,a5,1788 # 40006fc + 3007748: 2099 jal ra,300778e + 300774a: 4601 li a2,0 + 300774c: 04000593 li a1,64 + 3007750: 040007b7 lui a5,0x4000 + 3007754: 74478513 addi a0,a5,1860 # 4000744 + 3007758: 281d jal ra,300778e + 300775a: 4601 li a2,0 + 300775c: 45a1 li a1,8 + 300775e: 040007b7 lui a5,0x4000 + 3007762: 6fc78513 addi a0,a5,1788 # 40006fc + 3007766: 2025 jal ra,300778e + 3007768: 4605 li a2,1 + 300776a: 4589 li a1,2 + 300776c: 040007b7 lui a5,0x4000 + 3007770: 6fc78513 addi a0,a5,1788 # 40006fc + 3007774: 2829 jal ra,300778e + 3007776: a039 j 3007784 + 3007778: 040037b7 lui a5,0x4003 + 300777c: 00078623 sb zero,12(a5) # 400300c + 3007780: a011 j 3007784 + 3007782: 0001 nop + 3007784: 0001 nop + 3007786: 40f2 lw ra,28(sp) + 3007788: 4462 lw s0,24(sp) + 300778a: 6105 addi sp,sp,32 + 300778c: 8082 ret + +0300778e : + 300778e: ce6fc06f j 3003c74 + +03007792 : + 3007792: 1101 addi sp,sp,-32 + 3007794: ce06 sw ra,28(sp) + 3007796: cc22 sw s0,24(sp) + 3007798: 1000 addi s0,sp,32 + 300779a: fea42623 sw a0,-20(s0) + 300779e: 040037b7 lui a5,0x4003 + 30077a2: 0147a783 lw a5,20(a5) # 4003014 + 30077a6: 00178713 addi a4,a5,1 + 30077aa: 040037b7 lui a5,0x4003 + 30077ae: 00e7aa23 sw a4,20(a5) # 4003014 + 30077b2: 040037b7 lui a5,0x4003 + 30077b6: 0147a703 lw a4,20(a5) # 4003014 + 30077ba: 3e800793 li a5,1000 + 30077be: 00e7fd63 bgeu a5,a4,30077d8 + 30077c2: 040037b7 lui a5,0x4003 + 30077c6: 0007aa23 sw zero,20(a5) # 4003014 + 30077ca: 4585 li a1,1 + 30077cc: 040007b7 lui a5,0x4000 + 30077d0: 6b478513 addi a0,a5,1716 # 40006b4 + 30077d4: d8efc0ef jal ra,3003d62 + 30077d8: 0001 nop + 30077da: 40f2 lw ra,28(sp) + 30077dc: 4462 lw s0,24(sp) + 30077de: 6105 addi sp,sp,32 + 30077e0: 8082 ret + +030077e2 : + 30077e2: 1101 addi sp,sp,-32 + 30077e4: ce06 sw ra,28(sp) + 30077e6: cc22 sw s0,24(sp) + 30077e8: 1000 addi s0,sp,32 + 30077ea: 87aa mv a5,a0 + 30077ec: 872e mv a4,a1 + 30077ee: fef407a3 sb a5,-17(s0) + 30077f2: 87ba mv a5,a4 + 30077f4: fef40723 sb a5,-18(s0) + 30077f8: 040037b7 lui a5,0x4003 + 30077fc: fef44703 lbu a4,-17(s0) + 3007800: 00e78c23 sb a4,24(a5) # 4003018 + 3007804: 040037b7 lui a5,0x4003 + 3007808: 01878793 addi a5,a5,24 # 4003018 + 300780c: fee44703 lbu a4,-18(s0) + 3007810: b398 sb a4,1(a5) + 3007812: 6789 lui a5,0x2 + 3007814: 71078713 addi a4,a5,1808 # 2710 + 3007818: 4689 li a3,2 + 300781a: 040037b7 lui a5,0x4003 + 300781e: 01878613 addi a2,a5,24 # 4003018 + 3007822: 0e600593 li a1,230 + 3007826: 040007b7 lui a5,0x4000 + 300782a: 60478513 addi a0,a5,1540 # 4000604 + 300782e: ebdfd0ef jal ra,30056ea + 3007832: 0001 nop + 3007834: 40f2 lw ra,28(sp) + 3007836: 4462 lw s0,24(sp) + 3007838: 6105 addi sp,sp,32 + 300783a: 8082 ret + +0300783c : + 300783c: 1101 addi sp,sp,-32 + 300783e: ce06 sw ra,28(sp) + 3007840: cc22 sw s0,24(sp) + 3007842: 1000 addi s0,sp,32 + 3007844: 87aa mv a5,a0 + 3007846: fef407a3 sb a5,-17(s0) + 300784a: 040037b7 lui a5,0x4003 + 300784e: fef44703 lbu a4,-17(s0) + 3007852: 00e78c23 sb a4,24(a5) # 4003018 + 3007856: 6789 lui a5,0x2 + 3007858: 71078713 addi a4,a5,1808 # 2710 + 300785c: 4685 li a3,1 + 300785e: 040037b7 lui a5,0x4003 + 3007862: 01878613 addi a2,a5,24 # 4003018 + 3007866: 0e600593 li a1,230 + 300786a: 040007b7 lui a5,0x4000 + 300786e: 60478513 addi a0,a5,1540 # 4000604 + 3007872: e79fd0ef jal ra,30056ea + 3007876: 6789 lui a5,0x2 + 3007878: 71078713 addi a4,a5,1808 # 2710 + 300787c: 4685 li a3,1 + 300787e: 040037b7 lui a5,0x4003 + 3007882: 01878613 addi a2,a5,24 # 4003018 + 3007886: 0e700593 li a1,231 + 300788a: 040007b7 lui a5,0x4000 + 300788e: 60478513 addi a0,a5,1540 # 4000604 + 3007892: c53fd0ef jal ra,30054e4 + 3007896: 040037b7 lui a5,0x4003 + 300789a: 0187c783 lbu a5,24(a5) # 4003018 + 300789e: 853e mv a0,a5 + 30078a0: 40f2 lw ra,28(sp) + 30078a2: 4462 lw s0,24(sp) + 30078a4: 6105 addi sp,sp,32 + 30078a6: 8082 ret + +030078a8 : + 30078a8: 1101 addi sp,sp,-32 + 30078aa: ce06 sw ra,28(sp) + 30078ac: cc22 sw s0,24(sp) + 30078ae: 1000 addi s0,sp,32 + 30078b0: 4501 li a0,0 + 30078b2: 3769 jal ra,300783c + 30078b4: 87aa mv a5,a0 + 30078b6: 873e mv a4,a5 + 30078b8: 02000793 li a5,32 + 30078bc: 0af71463 bne a4,a5,3007964 + 30078c0: fe0407a3 sb zero,-17(s0) + 30078c4: a81d j 30078fa + 30078c6: fef44783 lbu a5,-17(s0) + 30078ca: 03009737 lui a4,0x3009 + 30078ce: b1470713 addi a4,a4,-1260 # 3008b14 + 30078d2: 0786 slli a5,a5,0x1 + 30078d4: 97ba add a5,a5,a4 + 30078d6: 2394 lbu a3,0(a5) + 30078d8: fef44783 lbu a5,-17(s0) + 30078dc: 03009737 lui a4,0x3009 + 30078e0: b1470713 addi a4,a4,-1260 # 3008b14 + 30078e4: 0786 slli a5,a5,0x1 + 30078e6: 97ba add a5,a5,a4 + 30078e8: 339c lbu a5,1(a5) + 30078ea: 85be mv a1,a5 + 30078ec: 8536 mv a0,a3 + 30078ee: 3dd5 jal ra,30077e2 + 30078f0: fef44783 lbu a5,-17(s0) + 30078f4: 0785 addi a5,a5,1 + 30078f6: fef407a3 sb a5,-17(s0) + 30078fa: fef44703 lbu a4,-17(s0) + 30078fe: 03200793 li a5,50 + 3007902: fce7f2e3 bgeu a5,a4,30078c6 + 3007906: fe040723 sb zero,-18(s0) + 300790a: a81d j 3007940 + 300790c: fee44783 lbu a5,-18(s0) + 3007910: 03009737 lui a4,0x3009 + 3007914: b7c70713 addi a4,a4,-1156 # 3008b7c + 3007918: 0786 slli a5,a5,0x1 + 300791a: 97ba add a5,a5,a4 + 300791c: 2394 lbu a3,0(a5) + 300791e: fee44783 lbu a5,-18(s0) + 3007922: 03009737 lui a4,0x3009 + 3007926: b7c70713 addi a4,a4,-1156 # 3008b7c + 300792a: 0786 slli a5,a5,0x1 + 300792c: 97ba add a5,a5,a4 + 300792e: 339c lbu a5,1(a5) + 3007930: 85be mv a1,a5 + 3007932: 8536 mv a0,a3 + 3007934: 357d jal ra,30077e2 + 3007936: fee44783 lbu a5,-18(s0) + 300793a: 0785 addi a5,a5,1 + 300793c: fef40723 sb a5,-18(s0) + 3007940: fee44703 lbu a4,-18(s0) + 3007944: 47f5 li a5,29 + 3007946: fce7f3e3 bgeu a5,a4,300790c + 300794a: 3e800693 li a3,1000 + 300794e: 4651 li a2,20 + 3007950: 030097b7 lui a5,0x3009 + 3007954: bb878593 addi a1,a5,-1096 # 3008bb8 + 3007958: 040007b7 lui a5,0x4000 + 300795c: 50478513 addi a0,a5,1284 # 4000504 + 3007960: 201d jal ra,3007986 + 3007962: a829 j 300797c + 3007964: 3e800693 li a3,1000 + 3007968: 4661 li a2,24 + 300796a: 030097b7 lui a5,0x3009 + 300796e: bd078593 addi a1,a5,-1072 # 3008bd0 + 3007972: 040007b7 lui a5,0x4000 + 3007976: 50478513 addi a0,a5,1284 # 4000504 + 300797a: 2031 jal ra,3007986 + 300797c: 0001 nop + 300797e: 40f2 lw ra,28(sp) + 3007980: 4462 lw s0,24(sp) + 3007982: 6105 addi sp,sp,32 + 3007984: 8082 ret + +03007986 : + 3007986: f17fe06f j 300689c + +0300798a : + 300798a: 1101 addi sp,sp,-32 + 300798c: ce06 sw ra,28(sp) + 300798e: cc22 sw s0,24(sp) + 3007990: 1000 addi s0,sp,32 + 3007992: 04300513 li a0,67 + 3007996: 355d jal ra,300783c + 3007998: 87aa mv a5,a0 + 300799a: fef407a3 sb a5,-17(s0) + 300799e: fef44783 lbu a5,-17(s0) + 30079a2: 4721 li a4,8 + 30079a4: 0ae78963 beq a5,a4,3007a56 + 30079a8: 4721 li a4,8 + 30079aa: 00f74c63 blt a4,a5,30079c2 + 30079ae: 4709 li a4,2 + 30079b0: 06e78063 beq a5,a4,3007a10 + 30079b4: 4711 li a4,4 + 30079b6: 06e78e63 beq a5,a4,3007a32 + 30079ba: 4705 li a4,1 + 30079bc: 02e78863 beq a5,a4,30079ec + 30079c0: aa0d j 3007af2 + 30079c2: 02000713 li a4,32 + 30079c6: 0ce78b63 beq a5,a4,3007a9c + 30079ca: 02000713 li a4,32 + 30079ce: 00f74663 blt a4,a5,30079da + 30079d2: 4741 li a4,16 + 30079d4: 0ae78263 beq a5,a4,3007a78 + 30079d8: aa29 j 3007af2 + 30079da: 04000713 li a4,64 + 30079de: 0ee78063 beq a5,a4,3007abe + 30079e2: 08000713 li a4,128 + 30079e6: 0ee78963 beq a5,a4,3007ad8 + 30079ea: a221 j 3007af2 + 30079ec: 3e800693 li a3,1000 + 30079f0: 4611 li a2,4 + 30079f2: 030097b7 lui a5,0x3009 + 30079f6: bec78593 addi a1,a5,-1044 # 3008bec + 30079fa: 040007b7 lui a5,0x4000 + 30079fe: 50478513 addi a0,a5,1284 # 4000504 + 3007a02: 3751 jal ra,3007986 + 3007a04: 040037b7 lui a5,0x4003 + 3007a08: 4705 li a4,1 + 3007a0a: 00e786a3 sb a4,13(a5) # 400300d + 3007a0e: a0d5 j 3007af2 + 3007a10: 3e800693 li a3,1000 + 3007a14: 4619 li a2,6 + 3007a16: 030097b7 lui a5,0x3009 + 3007a1a: bf478593 addi a1,a5,-1036 # 3008bf4 + 3007a1e: 040007b7 lui a5,0x4000 + 3007a22: 50478513 addi a0,a5,1284 # 4000504 + 3007a26: 3785 jal ra,3007986 + 3007a28: 040037b7 lui a5,0x4003 + 3007a2c: 000786a3 sb zero,13(a5) # 400300d + 3007a30: a0c9 j 3007af2 + 3007a32: 3e800693 li a3,1000 + 3007a36: 4619 li a2,6 + 3007a38: 030097b7 lui a5,0x3009 + 3007a3c: bfc78593 addi a1,a5,-1028 # 3008bfc + 3007a40: 040007b7 lui a5,0x4000 + 3007a44: 50478513 addi a0,a5,1284 # 4000504 + 3007a48: 3f3d jal ra,3007986 + 3007a4a: 040037b7 lui a5,0x4003 + 3007a4e: 4705 li a4,1 + 3007a50: 00e786a3 sb a4,13(a5) # 400300d + 3007a54: a879 j 3007af2 + 3007a56: 3e800693 li a3,1000 + 3007a5a: 461d li a2,7 + 3007a5c: 030097b7 lui a5,0x3009 + 3007a60: c0478593 addi a1,a5,-1020 # 3008c04 + 3007a64: 040007b7 lui a5,0x4000 + 3007a68: 50478513 addi a0,a5,1284 # 4000504 + 3007a6c: 3f29 jal ra,3007986 + 3007a6e: 040037b7 lui a5,0x4003 + 3007a72: 000786a3 sb zero,13(a5) # 400300d + 3007a76: a8b5 j 3007af2 + 3007a78: 3e800693 li a3,1000 + 3007a7c: 4625 li a2,9 + 3007a7e: 030097b7 lui a5,0x3009 + 3007a82: c0c78593 addi a1,a5,-1012 # 3008c0c + 3007a86: 040007b7 lui a5,0x4000 + 3007a8a: 50478513 addi a0,a5,1284 # 4000504 + 3007a8e: 3de5 jal ra,3007986 + 3007a90: 040037b7 lui a5,0x4003 + 3007a94: 4705 li a4,1 + 3007a96: 00e786a3 sb a4,13(a5) # 400300d + 3007a9a: a8a1 j 3007af2 + 3007a9c: 3e800693 li a3,1000 + 3007aa0: 4629 li a2,10 + 3007aa2: 030097b7 lui a5,0x3009 + 3007aa6: c1878593 addi a1,a5,-1000 # 3008c18 + 3007aaa: 040007b7 lui a5,0x4000 + 3007aae: 50478513 addi a0,a5,1284 # 4000504 + 3007ab2: 3dd1 jal ra,3007986 + 3007ab4: 040037b7 lui a5,0x4003 + 3007ab8: 000786a3 sb zero,13(a5) # 400300d + 3007abc: a81d j 3007af2 + 3007abe: 3e800693 li a3,1000 + 3007ac2: 462d li a2,11 + 3007ac4: 030097b7 lui a5,0x3009 + 3007ac8: c2478593 addi a1,a5,-988 # 3008c24 + 3007acc: 040007b7 lui a5,0x4000 + 3007ad0: 50478513 addi a0,a5,1284 # 4000504 + 3007ad4: 3d4d jal ra,3007986 + 3007ad6: a831 j 3007af2 + 3007ad8: 3e800693 li a3,1000 + 3007adc: 463d li a2,15 + 3007ade: 030097b7 lui a5,0x3009 + 3007ae2: c3078593 addi a1,a5,-976 # 3008c30 + 3007ae6: 040007b7 lui a5,0x4000 + 3007aea: 50478513 addi a0,a5,1284 # 4000504 + 3007aee: 3d61 jal ra,3007986 + 3007af0: 0001 nop + 3007af2: 0001 nop + 3007af4: 40f2 lw ra,28(sp) + 3007af6: 4462 lw s0,24(sp) + 3007af8: 6105 addi sp,sp,32 + 3007afa: 8082 ret + +03007afc : + 3007afc: 715d addi sp,sp,-80 + 3007afe: c686 sw ra,76(sp) + 3007b00: c4a2 sw s0,72(sp) + 3007b02: 0880 addi s0,sp,80 + 3007b04: faa42e23 sw a0,-68(s0) + 3007b08: 100007b7 lui a5,0x10000 + 3007b0c: fcf42423 sw a5,-56(s0) + 3007b10: fc042623 sw zero,-52(s0) + 3007b14: 478d li a5,3 + 3007b16: fcf42823 sw a5,-48(s0) + 3007b1a: 03000793 li a5,48 + 3007b1e: fcf42a23 sw a5,-44(s0) + 3007b22: 4785 li a5,1 + 3007b24: fcf42c23 sw a5,-40(s0) + 3007b28: 4789 li a5,2 + 3007b2a: fef42023 sw a5,-32(s0) + 3007b2e: 4789 li a5,2 + 3007b30: fef42223 sw a5,-28(s0) + 3007b34: fe042423 sw zero,-24(s0) + 3007b38: 47e1 li a5,24 + 3007b3a: fef42623 sw a5,-20(s0) + 3007b3e: fc840793 addi a5,s0,-56 + 3007b42: 853e mv a0,a5 + 3007b44: d3efa0ef jal ra,3002082 + 3007b48: 87aa mv a5,a0 + 3007b4a: c399 beqz a5,3007b50 + 3007b4c: 4785 li a5,1 + 3007b4e: a039 j 3007b5c + 3007b50: fe042703 lw a4,-32(s0) + 3007b54: fbc42783 lw a5,-68(s0) + 3007b58: c398 sw a4,0(a5) + 3007b5a: 4781 li a5,0 + 3007b5c: 853e mv a0,a5 + 3007b5e: 40b6 lw ra,76(sp) + 3007b60: 4426 lw s0,72(sp) + 3007b62: 6161 addi sp,sp,80 + 3007b64: 8082 ret + +03007b66 : + 3007b66: 1141 addi sp,sp,-16 + 3007b68: c606 sw ra,12(sp) + 3007b6a: c422 sw s0,8(sp) + 3007b6c: 0800 addi s0,sp,16 + 3007b6e: 4585 li a1,1 + 3007b70: 14502537 lui a0,0x14502 + 3007b74: 2599 jal ra,30081ba + 3007b76: 040007b7 lui a5,0x4000 + 3007b7a: 66c78793 addi a5,a5,1644 # 400066c + 3007b7e: 14502737 lui a4,0x14502 + 3007b82: c398 sw a4,0(a5) + 3007b84: 040007b7 lui a5,0x4000 + 3007b88: 66c78793 addi a5,a5,1644 # 400066c + 3007b8c: 4721 li a4,8 + 3007b8e: c3d8 sw a4,4(a5) + 3007b90: 040007b7 lui a5,0x4000 + 3007b94: 66c78513 addi a0,a5,1644 # 400066c + 3007b98: 2c89 jal ra,3007dea + 3007b9a: 040007b7 lui a5,0x4000 + 3007b9e: 66c78793 addi a5,a5,1644 # 400066c + 3007ba2: 43dc lw a5,4(a5) + 3007ba4: 4605 li a2,1 + 3007ba6: 85be mv a1,a5 + 3007ba8: 040007b7 lui a5,0x4000 + 3007bac: 66c78513 addi a0,a5,1644 # 400066c + 3007bb0: 2c1d jal ra,3007de6 + 3007bb2: 040007b7 lui a5,0x4000 + 3007bb6: 66c78793 addi a5,a5,1644 # 400066c + 3007bba: 43dc lw a5,4(a5) + 3007bbc: 4605 li a2,1 + 3007bbe: 85be mv a1,a5 + 3007bc0: 040007b7 lui a5,0x4000 + 3007bc4: 66c78513 addi a0,a5,1644 # 400066c + 3007bc8: 36d9 jal ra,300778e + 3007bca: 040007b7 lui a5,0x4000 + 3007bce: 66c78793 addi a5,a5,1644 # 400066c + 3007bd2: 43dc lw a5,4(a5) + 3007bd4: 4615 li a2,5 + 3007bd6: 85be mv a1,a5 + 3007bd8: 040007b7 lui a5,0x4000 + 3007bdc: 66c78513 addi a0,a5,1644 # 400066c + 3007be0: 2409 jal ra,3007de2 + 3007be2: 040007b7 lui a5,0x4000 + 3007be6: 66c78793 addi a5,a5,1644 # 400066c + 3007bea: 4741 li a4,16 + 3007bec: c3d8 sw a4,4(a5) + 3007bee: 040007b7 lui a5,0x4000 + 3007bf2: 66c78513 addi a0,a5,1644 # 400066c + 3007bf6: 2ad5 jal ra,3007dea + 3007bf8: 040007b7 lui a5,0x4000 + 3007bfc: 66c78793 addi a5,a5,1644 # 400066c + 3007c00: 43dc lw a5,4(a5) + 3007c02: 4601 li a2,0 + 3007c04: 85be mv a1,a5 + 3007c06: 040007b7 lui a5,0x4000 + 3007c0a: 66c78513 addi a0,a5,1644 # 400066c + 3007c0e: 2ae1 jal ra,3007de6 + 3007c10: 040007b7 lui a5,0x4000 + 3007c14: 66c78793 addi a5,a5,1644 # 400066c + 3007c18: 43dc lw a5,4(a5) + 3007c1a: 4601 li a2,0 + 3007c1c: 85be mv a1,a5 + 3007c1e: 040007b7 lui a5,0x4000 + 3007c22: 66c78513 addi a0,a5,1644 # 400066c + 3007c26: 36a5 jal ra,300778e + 3007c28: 040007b7 lui a5,0x4000 + 3007c2c: 66c78793 addi a5,a5,1644 # 400066c + 3007c30: 43dc lw a5,4(a5) + 3007c32: 4601 li a2,0 + 3007c34: 85be mv a1,a5 + 3007c36: 040007b7 lui a5,0x4000 + 3007c3a: 66c78513 addi a0,a5,1644 # 400066c + 3007c3e: 2255 jal ra,3007de2 + 3007c40: 4585 li a1,1 + 3007c42: 14501537 lui a0,0x14501 + 3007c46: 2b95 jal ra,30081ba + 3007c48: 040007b7 lui a5,0x4000 + 3007c4c: 6b478793 addi a5,a5,1716 # 40006b4 + 3007c50: 14501737 lui a4,0x14501 + 3007c54: c398 sw a4,0(a5) + 3007c56: 040007b7 lui a5,0x4000 + 3007c5a: 6b478793 addi a5,a5,1716 # 40006b4 + 3007c5e: 4705 li a4,1 + 3007c60: c3d8 sw a4,4(a5) + 3007c62: 040007b7 lui a5,0x4000 + 3007c66: 6b478513 addi a0,a5,1716 # 40006b4 + 3007c6a: 2241 jal ra,3007dea + 3007c6c: 040007b7 lui a5,0x4000 + 3007c70: 6b478793 addi a5,a5,1716 # 40006b4 + 3007c74: 43dc lw a5,4(a5) + 3007c76: 4605 li a2,1 + 3007c78: 85be mv a1,a5 + 3007c7a: 040007b7 lui a5,0x4000 + 3007c7e: 6b478513 addi a0,a5,1716 # 40006b4 + 3007c82: 2295 jal ra,3007de6 + 3007c84: 040007b7 lui a5,0x4000 + 3007c88: 6b478793 addi a5,a5,1716 # 40006b4 + 3007c8c: 43dc lw a5,4(a5) + 3007c8e: 4605 li a2,1 + 3007c90: 85be mv a1,a5 + 3007c92: 040007b7 lui a5,0x4000 + 3007c96: 6b478513 addi a0,a5,1716 # 40006b4 + 3007c9a: 3cd5 jal ra,300778e + 3007c9c: 040007b7 lui a5,0x4000 + 3007ca0: 6b478793 addi a5,a5,1716 # 40006b4 + 3007ca4: 43dc lw a5,4(a5) + 3007ca6: 4615 li a2,5 + 3007ca8: 85be mv a1,a5 + 3007caa: 040007b7 lui a5,0x4000 + 3007cae: 6b478513 addi a0,a5,1716 # 40006b4 + 3007cb2: 2a05 jal ra,3007de2 + 3007cb4: 4585 li a1,1 + 3007cb6: 14505537 lui a0,0x14505 + 3007cba: 2301 jal ra,30081ba + 3007cbc: 040007b7 lui a5,0x4000 + 3007cc0: 6fc78793 addi a5,a5,1788 # 40006fc + 3007cc4: 14505737 lui a4,0x14505 + 3007cc8: c398 sw a4,0(a5) + 3007cca: 040007b7 lui a5,0x4000 + 3007cce: 6fc78793 addi a5,a5,1788 # 40006fc + 3007cd2: 4739 li a4,14 + 3007cd4: c3d8 sw a4,4(a5) + 3007cd6: 040007b7 lui a5,0x4000 + 3007cda: 6fc78513 addi a0,a5,1788 # 40006fc + 3007cde: 2231 jal ra,3007dea + 3007ce0: 040007b7 lui a5,0x4000 + 3007ce4: 6fc78793 addi a5,a5,1788 # 40006fc + 3007ce8: 43dc lw a5,4(a5) + 3007cea: 4605 li a2,1 + 3007cec: 85be mv a1,a5 + 3007cee: 040007b7 lui a5,0x4000 + 3007cf2: 6fc78513 addi a0,a5,1788 # 40006fc + 3007cf6: 28c5 jal ra,3007de6 + 3007cf8: 040007b7 lui a5,0x4000 + 3007cfc: 6fc78793 addi a5,a5,1788 # 40006fc + 3007d00: 43dc lw a5,4(a5) + 3007d02: 4605 li a2,1 + 3007d04: 85be mv a1,a5 + 3007d06: 040007b7 lui a5,0x4000 + 3007d0a: 6fc78513 addi a0,a5,1788 # 40006fc + 3007d0e: 3441 jal ra,300778e + 3007d10: 040007b7 lui a5,0x4000 + 3007d14: 6fc78793 addi a5,a5,1788 # 40006fc + 3007d18: 43dc lw a5,4(a5) + 3007d1a: 4615 li a2,5 + 3007d1c: 85be mv a1,a5 + 3007d1e: 040007b7 lui a5,0x4000 + 3007d22: 6fc78513 addi a0,a5,1788 # 40006fc + 3007d26: 2875 jal ra,3007de2 + 3007d28: 4585 li a1,1 + 3007d2a: 14503537 lui a0,0x14503 + 3007d2e: 2171 jal ra,30081ba + 3007d30: 040007b7 lui a5,0x4000 + 3007d34: 74478793 addi a5,a5,1860 # 4000744 + 3007d38: 14503737 lui a4,0x14503 + 3007d3c: c398 sw a4,0(a5) + 3007d3e: 040007b7 lui a5,0x4000 + 3007d42: 74478793 addi a5,a5,1860 # 4000744 + 3007d46: 04000713 li a4,64 + 3007d4a: c3d8 sw a4,4(a5) + 3007d4c: 040007b7 lui a5,0x4000 + 3007d50: 74478513 addi a0,a5,1860 # 4000744 + 3007d54: 2859 jal ra,3007dea + 3007d56: 040007b7 lui a5,0x4000 + 3007d5a: 74478793 addi a5,a5,1860 # 4000744 + 3007d5e: 43dc lw a5,4(a5) + 3007d60: 4605 li a2,1 + 3007d62: 85be mv a1,a5 + 3007d64: 040007b7 lui a5,0x4000 + 3007d68: 74478513 addi a0,a5,1860 # 4000744 + 3007d6c: 28ad jal ra,3007de6 + 3007d6e: 040007b7 lui a5,0x4000 + 3007d72: 74478793 addi a5,a5,1860 # 4000744 + 3007d76: 43dc lw a5,4(a5) + 3007d78: 4605 li a2,1 + 3007d7a: 85be mv a1,a5 + 3007d7c: 040007b7 lui a5,0x4000 + 3007d80: 74478513 addi a0,a5,1860 # 4000744 + 3007d84: 3429 jal ra,300778e + 3007d86: 040007b7 lui a5,0x4000 + 3007d8a: 74478793 addi a5,a5,1860 # 4000744 + 3007d8e: 43dc lw a5,4(a5) + 3007d90: 4615 li a2,5 + 3007d92: 85be mv a1,a5 + 3007d94: 040007b7 lui a5,0x4000 + 3007d98: 74478513 addi a0,a5,1860 # 4000744 + 3007d9c: 2099 jal ra,3007de2 + 3007d9e: 030077b7 lui a5,0x3007 + 3007da2: 43878613 addi a2,a5,1080 # 3007438 + 3007da6: 45c1 li a1,16 + 3007da8: 040007b7 lui a5,0x4000 + 3007dac: 66c78513 addi a0,a5,1644 # 400066c + 3007db0: ddcfc0ef jal ra,300438c + 3007db4: 040007b7 lui a5,0x4000 + 3007db8: 66c78613 addi a2,a5,1644 # 400066c + 3007dbc: 030047b7 lui a5,0x3004 + 3007dc0: 28278593 addi a1,a5,642 # 3004282 + 3007dc4: 06f00513 li a0,111 + 3007dc8: 2305 jal ra,30082e8 + 3007dca: 4585 li a1,1 + 3007dcc: 06f00513 li a0,111 + 3007dd0: 2b11 jal ra,30082e4 + 3007dd2: 06f00513 li a0,111 + 3007dd6: 2329 jal ra,30082e0 + 3007dd8: 0001 nop + 3007dda: 40b2 lw ra,12(sp) + 3007ddc: 4422 lw s0,8(sp) + 3007dde: 0141 addi sp,sp,16 + 3007de0: 8082 ret + +03007de2 : + 3007de2: 98afc06f j 3003f6c + +03007de6 : + 3007de6: da7fb06f j 3003b8c + +03007dea : + 3007dea: cbdfb06f j 3003aa6 + +03007dee : + 3007dee: 1141 addi sp,sp,-16 + 3007df0: c606 sw ra,12(sp) + 3007df2: c422 sw s0,8(sp) + 3007df4: 0800 addi s0,sp,16 + 3007df6: 4585 li a1,1 + 3007df8: 14100537 lui a0,0x14100 + 3007dfc: 2e7d jal ra,30081ba + 3007dfe: 040007b7 lui a5,0x4000 + 3007e02: 60478793 addi a5,a5,1540 # 4000604 + 3007e06: 14100737 lui a4,0x14100 + 3007e0a: c398 sw a4,0(a5) + 3007e0c: 040007b7 lui a5,0x4000 + 3007e10: 60478793 addi a5,a5,1540 # 4000604 + 3007e14: 4705 li a4,1 + 3007e16: c3d8 sw a4,4(a5) + 3007e18: 040007b7 lui a5,0x4000 + 3007e1c: 60478793 addi a5,a5,1540 # 4000604 + 3007e20: 0007a423 sw zero,8(a5) + 3007e24: 040007b7 lui a5,0x4000 + 3007e28: 60478793 addi a5,a5,1540 # 4000604 + 3007e2c: 4729 li a4,10 + 3007e2e: cb98 sw a4,16(a5) + 3007e30: 040007b7 lui a5,0x4000 + 3007e34: 60478793 addi a5,a5,1540 # 4000604 + 3007e38: 6761 lui a4,0x18 + 3007e3a: 6a070713 addi a4,a4,1696 # 186a0 + 3007e3e: cbd8 sw a4,20(a5) + 3007e40: 040007b7 lui a5,0x4000 + 3007e44: 60478793 addi a5,a5,1540 # 4000604 + 3007e48: 0207a023 sw zero,32(a5) + 3007e4c: 040007b7 lui a5,0x4000 + 3007e50: 60478793 addi a5,a5,1540 # 4000604 + 3007e54: 0007ac23 sw zero,24(a5) + 3007e58: 040007b7 lui a5,0x4000 + 3007e5c: 60478793 addi a5,a5,1540 # 4000604 + 3007e60: 0407ac23 sw zero,88(a5) + 3007e64: 040007b7 lui a5,0x4000 + 3007e68: 60478793 addi a5,a5,1540 # 4000604 + 3007e6c: 0407ae23 sw zero,92(a5) + 3007e70: 040007b7 lui a5,0x4000 + 3007e74: 60478793 addi a5,a5,1540 # 4000604 + 3007e78: 6709 lui a4,0x2 + 3007e7a: 71070713 addi a4,a4,1808 # 2710 + 3007e7e: d7d8 sw a4,44(a5) + 3007e80: 040007b7 lui a5,0x4000 + 3007e84: 60478793 addi a5,a5,1540 # 4000604 + 3007e88: 0407a223 sw zero,68(a5) + 3007e8c: 040007b7 lui a5,0x4000 + 3007e90: 60478513 addi a0,a5,1540 # 4000604 + 3007e94: b6cfd0ef jal ra,3005200 + 3007e98: 0001 nop + 3007e9a: 40b2 lw ra,12(sp) + 3007e9c: 4422 lw s0,8(sp) + 3007e9e: 0141 addi sp,sp,16 + 3007ea0: 8082 ret + +03007ea2 : + 3007ea2: 1101 addi sp,sp,-32 + 3007ea4: ce06 sw ra,28(sp) + 3007ea6: cc22 sw s0,24(sp) + 3007ea8: 1000 addi s0,sp,32 + 3007eaa: 4585 li a1,1 + 3007eac: 14300537 lui a0,0x14300 + 3007eb0: 2629 jal ra,30081ba + 3007eb2: 14300537 lui a0,0x14300 + 3007eb6: eb4fa0ef jal ra,300256a + 3007eba: 872a mv a4,a0 + 3007ebc: 000f47b7 lui a5,0xf4 + 3007ec0: 24078793 addi a5,a5,576 # f4240 + 3007ec4: 02f75733 divu a4,a4,a5 + 3007ec8: 1f400793 li a5,500 + 3007ecc: 02f707b3 mul a5,a4,a5 + 3007ed0: fef42623 sw a5,-20(s0) + 3007ed4: 040007b7 lui a5,0x4000 + 3007ed8: 4b478793 addi a5,a5,1204 # 40004b4 + 3007edc: 14300737 lui a4,0x14300 + 3007ee0: c398 sw a4,0(a5) + 3007ee2: fec42783 lw a5,-20(s0) + 3007ee6: fff78713 addi a4,a5,-1 + 3007eea: 040007b7 lui a5,0x4000 + 3007eee: 4b478793 addi a5,a5,1204 # 40004b4 + 3007ef2: cbd8 sw a4,20(a5) + 3007ef4: fec42783 lw a5,-20(s0) + 3007ef8: fff78713 addi a4,a5,-1 + 3007efc: 040007b7 lui a5,0x4000 + 3007f00: 4b478793 addi a5,a5,1204 # 40004b4 + 3007f04: cf98 sw a4,24(a5) + 3007f06: 040007b7 lui a5,0x4000 + 3007f0a: 4b478793 addi a5,a5,1204 # 40004b4 + 3007f0e: 4705 li a4,1 + 3007f10: c798 sw a4,8(a5) + 3007f12: 040007b7 lui a5,0x4000 + 3007f16: 4b478793 addi a5,a5,1204 # 40004b4 + 3007f1a: 0007a623 sw zero,12(a5) + 3007f1e: 040007b7 lui a5,0x4000 + 3007f22: 4b478793 addi a5,a5,1204 # 40004b4 + 3007f26: 4705 li a4,1 + 3007f28: cb98 sw a4,16(a5) + 3007f2a: 040007b7 lui a5,0x4000 + 3007f2e: 4b478793 addi a5,a5,1204 # 40004b4 + 3007f32: 4705 li a4,1 + 3007f34: afd8 sb a4,28(a5) + 3007f36: 040007b7 lui a5,0x4000 + 3007f3a: 4b478793 addi a5,a5,1204 # 40004b4 + 3007f3e: 00078ea3 sb zero,29(a5) + 3007f42: 040007b7 lui a5,0x4000 + 3007f46: 4b478793 addi a5,a5,1204 # 40004b4 + 3007f4a: 00078f23 sb zero,30(a5) + 3007f4e: 040007b7 lui a5,0x4000 + 3007f52: 4b478513 addi a0,a5,1204 # 40004b4 + 3007f56: e5bfd0ef jal ra,3005db0 + 3007f5a: 040007b7 lui a5,0x4000 + 3007f5e: 4b478613 addi a2,a5,1204 # 40004b4 + 3007f62: 030067b7 lui a5,0x3006 + 3007f66: 08478593 addi a1,a5,132 # 3006084 + 3007f6a: 02000513 li a0,32 + 3007f6e: 2ead jal ra,30082e8 + 3007f70: 030077b7 lui a5,0x3007 + 3007f74: 56a78613 addi a2,a5,1386 # 300756a + 3007f78: 4581 li a1,0 + 3007f7a: 040007b7 lui a5,0x4000 + 3007f7e: 4b478513 addi a0,a5,1204 # 40004b4 + 3007f82: 9eafe0ef jal ra,300616c + 3007f86: 4585 li a1,1 + 3007f88: 02000513 li a0,32 + 3007f8c: 2ea1 jal ra,30082e4 + 3007f8e: 02000513 li a0,32 + 3007f92: 26b9 jal ra,30082e0 + 3007f94: 0001 nop + 3007f96: 40f2 lw ra,28(sp) + 3007f98: 4462 lw s0,24(sp) + 3007f9a: 6105 addi sp,sp,32 + 3007f9c: 8082 ret + +03007f9e : + 3007f9e: 1101 addi sp,sp,-32 + 3007fa0: ce06 sw ra,28(sp) + 3007fa2: cc22 sw s0,24(sp) + 3007fa4: 1000 addi s0,sp,32 + 3007fa6: 4585 li a1,1 + 3007fa8: 14301537 lui a0,0x14301 + 3007fac: 2439 jal ra,30081ba + 3007fae: 14301537 lui a0,0x14301 + 3007fb2: db8fa0ef jal ra,300256a + 3007fb6: 872a mv a4,a0 + 3007fb8: 000f47b7 lui a5,0xf4 + 3007fbc: 24078793 addi a5,a5,576 # f4240 + 3007fc0: 02f75733 divu a4,a4,a5 + 3007fc4: 1f400793 li a5,500 + 3007fc8: 02f707b3 mul a5,a4,a5 + 3007fcc: fef42623 sw a5,-20(s0) + 3007fd0: 040007b7 lui a5,0x4000 + 3007fd4: 4dc78793 addi a5,a5,1244 # 40004dc + 3007fd8: 14301737 lui a4,0x14301 + 3007fdc: c398 sw a4,0(a5) + 3007fde: fec42783 lw a5,-20(s0) + 3007fe2: fff78713 addi a4,a5,-1 + 3007fe6: 040007b7 lui a5,0x4000 + 3007fea: 4dc78793 addi a5,a5,1244 # 40004dc + 3007fee: cbd8 sw a4,20(a5) + 3007ff0: fec42783 lw a5,-20(s0) + 3007ff4: fff78713 addi a4,a5,-1 + 3007ff8: 040007b7 lui a5,0x4000 + 3007ffc: 4dc78793 addi a5,a5,1244 # 40004dc + 3008000: cf98 sw a4,24(a5) + 3008002: 040007b7 lui a5,0x4000 + 3008006: 4dc78793 addi a5,a5,1244 # 40004dc + 300800a: 4705 li a4,1 + 300800c: c798 sw a4,8(a5) + 300800e: 040007b7 lui a5,0x4000 + 3008012: 4dc78793 addi a5,a5,1244 # 40004dc + 3008016: 0007a623 sw zero,12(a5) + 300801a: 040007b7 lui a5,0x4000 + 300801e: 4dc78793 addi a5,a5,1244 # 40004dc + 3008022: 4705 li a4,1 + 3008024: cb98 sw a4,16(a5) + 3008026: 040007b7 lui a5,0x4000 + 300802a: 4dc78793 addi a5,a5,1244 # 40004dc + 300802e: 4705 li a4,1 + 3008030: afd8 sb a4,28(a5) + 3008032: 040007b7 lui a5,0x4000 + 3008036: 4dc78793 addi a5,a5,1244 # 40004dc + 300803a: 00078ea3 sb zero,29(a5) + 300803e: 040007b7 lui a5,0x4000 + 3008042: 4dc78793 addi a5,a5,1244 # 40004dc + 3008046: 00078f23 sb zero,30(a5) + 300804a: 040007b7 lui a5,0x4000 + 300804e: 4dc78513 addi a0,a5,1244 # 40004dc + 3008052: d5ffd0ef jal ra,3005db0 + 3008056: 040007b7 lui a5,0x4000 + 300805a: 4dc78613 addi a2,a5,1244 # 40004dc + 300805e: 030067b7 lui a5,0x3006 + 3008062: 08478593 addi a1,a5,132 # 3006084 + 3008066: 02100513 li a0,33 + 300806a: 2cbd jal ra,30082e8 + 300806c: 030077b7 lui a5,0x3007 + 3008070: 79278613 addi a2,a5,1938 # 3007792 + 3008074: 4581 li a1,0 + 3008076: 040007b7 lui a5,0x4000 + 300807a: 4dc78513 addi a0,a5,1244 # 40004dc + 300807e: 8eefe0ef jal ra,300616c + 3008082: 4585 li a1,1 + 3008084: 02100513 li a0,33 + 3008088: 2cb1 jal ra,30082e4 + 300808a: 02100513 li a0,33 + 300808e: 2c89 jal ra,30082e0 + 3008090: 0001 nop + 3008092: 40f2 lw ra,28(sp) + 3008094: 4462 lw s0,24(sp) + 3008096: 6105 addi sp,sp,32 + 3008098: 8082 ret + +0300809a : + 300809a: 1101 addi sp,sp,-32 + 300809c: ce22 sw s0,28(sp) + 300809e: 1000 addi s0,sp,32 + 30080a0: fea42623 sw a0,-20(s0) + 30080a4: 0001 nop + 30080a6: 4472 lw s0,28(sp) + 30080a8: 6105 addi sp,sp,32 + 30080aa: 8082 ret + +030080ac : + 30080ac: 1141 addi sp,sp,-16 + 30080ae: c606 sw ra,12(sp) + 30080b0: c422 sw s0,8(sp) + 30080b2: 0800 addi s0,sp,16 + 30080b4: 4585 li a1,1 + 30080b6: 14000537 lui a0,0x14000 + 30080ba: 2201 jal ra,30081ba + 30080bc: 040007b7 lui a5,0x4000 + 30080c0: 50478793 addi a5,a5,1284 # 4000504 + 30080c4: 14000737 lui a4,0x14000 + 30080c8: c398 sw a4,0(a5) + 30080ca: 040007b7 lui a5,0x4000 + 30080ce: 50478793 addi a5,a5,1284 # 4000504 + 30080d2: 6771 lui a4,0x1c + 30080d4: 20070713 addi a4,a4,512 # 1c200 + 30080d8: c3d8 sw a4,4(a5) + 30080da: 040007b7 lui a5,0x4000 + 30080de: 50478793 addi a5,a5,1284 # 4000504 + 30080e2: 470d li a4,3 + 30080e4: c798 sw a4,8(a5) + 30080e6: 040007b7 lui a5,0x4000 + 30080ea: 50478793 addi a5,a5,1284 # 4000504 + 30080ee: 0007a623 sw zero,12(a5) + 30080f2: 040007b7 lui a5,0x4000 + 30080f6: 50478793 addi a5,a5,1284 # 4000504 + 30080fa: 4711 li a4,4 + 30080fc: cb98 sw a4,16(a5) + 30080fe: 040007b7 lui a5,0x4000 + 3008102: 50478793 addi a5,a5,1284 # 4000504 + 3008106: 0007aa23 sw zero,20(a5) + 300810a: 040007b7 lui a5,0x4000 + 300810e: 50478793 addi a5,a5,1284 # 4000504 + 3008112: 4705 li a4,1 + 3008114: cf98 sw a4,24(a5) + 3008116: 040007b7 lui a5,0x4000 + 300811a: 50478793 addi a5,a5,1284 # 4000504 + 300811e: 02078623 sb zero,44(a5) + 3008122: 040007b7 lui a5,0x4000 + 3008126: 50478793 addi a5,a5,1284 # 4000504 + 300812a: 4721 li a4,8 + 300812c: db98 sw a4,48(a5) + 300812e: 040007b7 lui a5,0x4000 + 3008132: 50478793 addi a5,a5,1284 # 4000504 + 3008136: 4721 li a4,8 + 3008138: dbd8 sw a4,52(a5) + 300813a: 040007b7 lui a5,0x4000 + 300813e: 50478793 addi a5,a5,1284 # 4000504 + 3008142: 0207ac23 sw zero,56(a5) + 3008146: 040007b7 lui a5,0x4000 + 300814a: 50478793 addi a5,a5,1284 # 4000504 + 300814e: 0607ac23 sw zero,120(a5) + 3008152: 040007b7 lui a5,0x4000 + 3008156: 50478793 addi a5,a5,1284 # 4000504 + 300815a: 06078e23 sb zero,124(a5) + 300815e: 040007b7 lui a5,0x4000 + 3008162: 50478513 addi a0,a5,1284 # 4000504 + 3008166: b78fe0ef jal ra,30064de + 300816a: 030087b7 lui a5,0x3008 + 300816e: 09a78613 addi a2,a5,154 # 300809a + 3008172: 4591 li a1,4 + 3008174: 040007b7 lui a5,0x4000 + 3008178: 50478513 addi a0,a5,1284 # 4000504 + 300817c: 2285 jal ra,30082dc + 300817e: 030077b7 lui a5,0x3007 + 3008182: 49078613 addi a2,a5,1168 # 3007490 + 3008186: 4585 li a1,1 + 3008188: 040007b7 lui a5,0x4000 + 300818c: 50478513 addi a0,a5,1284 # 4000504 + 3008190: 22b1 jal ra,30082dc + 3008192: 040007b7 lui a5,0x4000 + 3008196: 50478613 addi a2,a5,1284 # 4000504 + 300819a: 030077b7 lui a5,0x3007 + 300819e: ffc78593 addi a1,a5,-4 # 3006ffc + 30081a2: 4571 li a0,28 + 30081a4: 2291 jal ra,30082e8 + 30081a6: 4585 li a1,1 + 30081a8: 4571 li a0,28 + 30081aa: 2a2d jal ra,30082e4 + 30081ac: 4571 li a0,28 + 30081ae: 2a0d jal ra,30082e0 + 30081b0: 0001 nop + 30081b2: 40b2 lw ra,12(sp) + 30081b4: 4422 lw s0,8(sp) + 30081b6: 0141 addi sp,sp,16 + 30081b8: 8082 ret + +030081ba : + 30081ba: c96fa06f j 3002650 + +030081be : + 30081be: 1101 addi sp,sp,-32 + 30081c0: ce22 sw s0,28(sp) + 30081c2: 1000 addi s0,sp,32 + 30081c4: fea42623 sw a0,-20(s0) + 30081c8: 0001 nop + 30081ca: 4472 lw s0,28(sp) + 30081cc: 6105 addi sp,sp,32 + 30081ce: 8082 ret + +030081d0 : + 30081d0: 1141 addi sp,sp,-16 + 30081d2: c606 sw ra,12(sp) + 30081d4: c422 sw s0,8(sp) + 30081d6: 0800 addi s0,sp,16 + 30081d8: 4585 li a1,1 + 30081da: 14002537 lui a0,0x14002 + 30081de: 3ff1 jal ra,30081ba + 30081e0: 040007b7 lui a5,0x4000 + 30081e4: 58478793 addi a5,a5,1412 # 4000584 + 30081e8: 14002737 lui a4,0x14002 + 30081ec: c398 sw a4,0(a5) + 30081ee: 040007b7 lui a5,0x4000 + 30081f2: 58478793 addi a5,a5,1412 # 4000584 + 30081f6: 000e1737 lui a4,0xe1 + 30081fa: c3d8 sw a4,4(a5) + 30081fc: 040007b7 lui a5,0x4000 + 3008200: 58478793 addi a5,a5,1412 # 4000584 + 3008204: 470d li a4,3 + 3008206: c798 sw a4,8(a5) + 3008208: 040007b7 lui a5,0x4000 + 300820c: 58478793 addi a5,a5,1412 # 4000584 + 3008210: 0007a623 sw zero,12(a5) + 3008214: 040007b7 lui a5,0x4000 + 3008218: 58478793 addi a5,a5,1412 # 4000584 + 300821c: 4711 li a4,4 + 300821e: cb98 sw a4,16(a5) + 3008220: 040007b7 lui a5,0x4000 + 3008224: 58478793 addi a5,a5,1412 # 4000584 + 3008228: 0007aa23 sw zero,20(a5) + 300822c: 040007b7 lui a5,0x4000 + 3008230: 58478793 addi a5,a5,1412 # 4000584 + 3008234: 4705 li a4,1 + 3008236: cf98 sw a4,24(a5) + 3008238: 040007b7 lui a5,0x4000 + 300823c: 58478793 addi a5,a5,1412 # 4000584 + 3008240: 02078623 sb zero,44(a5) + 3008244: 040007b7 lui a5,0x4000 + 3008248: 58478793 addi a5,a5,1412 # 4000584 + 300824c: 4721 li a4,8 + 300824e: db98 sw a4,48(a5) + 3008250: 040007b7 lui a5,0x4000 + 3008254: 58478793 addi a5,a5,1412 # 4000584 + 3008258: 4721 li a4,8 + 300825a: dbd8 sw a4,52(a5) + 300825c: 040007b7 lui a5,0x4000 + 3008260: 58478793 addi a5,a5,1412 # 4000584 + 3008264: 0207ac23 sw zero,56(a5) + 3008268: 040007b7 lui a5,0x4000 + 300826c: 58478793 addi a5,a5,1412 # 4000584 + 3008270: 0607ac23 sw zero,120(a5) + 3008274: 040007b7 lui a5,0x4000 + 3008278: 58478793 addi a5,a5,1412 # 4000584 + 300827c: 06078e23 sb zero,124(a5) + 3008280: 040007b7 lui a5,0x4000 + 3008284: 58478513 addi a0,a5,1412 # 4000584 + 3008288: a56fe0ef jal ra,30064de + 300828c: 030087b7 lui a5,0x3008 + 3008290: 1be78613 addi a2,a5,446 # 30081be + 3008294: 4591 li a1,4 + 3008296: 040007b7 lui a5,0x4000 + 300829a: 58478513 addi a0,a5,1412 # 4000584 + 300829e: 283d jal ra,30082dc + 30082a0: 030077b7 lui a5,0x3007 + 30082a4: 4fc78613 addi a2,a5,1276 # 30074fc + 30082a8: 4585 li a1,1 + 30082aa: 040007b7 lui a5,0x4000 + 30082ae: 58478513 addi a0,a5,1412 # 4000584 + 30082b2: 202d jal ra,30082dc + 30082b4: 040007b7 lui a5,0x4000 + 30082b8: 58478613 addi a2,a5,1412 # 4000584 + 30082bc: 030077b7 lui a5,0x3007 + 30082c0: ffc78593 addi a1,a5,-4 # 3006ffc + 30082c4: 4579 li a0,30 + 30082c6: 200d jal ra,30082e8 + 30082c8: 4585 li a1,1 + 30082ca: 4579 li a0,30 + 30082cc: 2821 jal ra,30082e4 + 30082ce: 4579 li a0,30 + 30082d0: 2801 jal ra,30082e0 + 30082d2: 0001 nop + 30082d4: 40b2 lw ra,12(sp) + 30082d6: 4422 lw s0,8(sp) + 30082d8: 0141 addi sp,sp,16 + 30082da: 8082 ret + +030082dc : + 30082dc: e7ffe06f j 300715a + +030082e0 : + 30082e0: 9b0f906f j 3001490 + +030082e4 : + 30082e4: 8fbf906f j 3001bde + +030082e8 : + 30082e8: 922f906f j 300140a + +030082ec : + 30082ec: 1141 addi sp,sp,-16 + 30082ee: c606 sw ra,12(sp) + 30082f0: c422 sw s0,8(sp) + 30082f2: 0800 addi s0,sp,16 + 30082f4: 018807b7 lui a5,0x1880 + 30082f8: 2b178513 addi a0,a5,689 # 18802b1 + 30082fc: 2e79 jal ra,300869a + 30082fe: 4581 li a1,0 + 3008300: 018807b7 lui a5,0x1880 + 3008304: 2b178513 addi a0,a5,689 # 18802b1 + 3008308: 2679 jal ra,3008696 + 300830a: 4581 li a1,0 + 300830c: 018807b7 lui a5,0x1880 + 3008310: 2b178513 addi a0,a5,689 # 18802b1 + 3008314: 2ebd jal ra,3008692 + 3008316: 4585 li a1,1 + 3008318: 018807b7 lui a5,0x1880 + 300831c: 2b178513 addi a0,a5,689 # 18802b1 + 3008320: 26bd jal ra,300868e + 3008322: 4589 li a1,2 + 3008324: 018807b7 lui a5,0x1880 + 3008328: 2b178513 addi a0,a5,689 # 18802b1 + 300832c: 2eb9 jal ra,300868a + 300832e: 018c07b7 lui a5,0x18c0 + 3008332: 31178513 addi a0,a5,785 # 18c0311 + 3008336: 2695 jal ra,300869a + 3008338: 4581 li a1,0 + 300833a: 018c07b7 lui a5,0x18c0 + 300833e: 31178513 addi a0,a5,785 # 18c0311 + 3008342: 2e91 jal ra,3008696 + 3008344: 4581 li a1,0 + 3008346: 018c07b7 lui a5,0x18c0 + 300834a: 31178513 addi a0,a5,785 # 18c0311 + 300834e: 2691 jal ra,3008692 + 3008350: 4585 li a1,1 + 3008352: 018c07b7 lui a5,0x18c0 + 3008356: 31178513 addi a0,a5,785 # 18c0311 + 300835a: 2e15 jal ra,300868e + 300835c: 4589 li a1,2 + 300835e: 018c07b7 lui a5,0x18c0 + 3008362: 31178513 addi a0,a5,785 # 18c0311 + 3008366: 2615 jal ra,300868a + 3008368: 018407b7 lui a5,0x1840 + 300836c: 23078513 addi a0,a5,560 # 1840230 + 3008370: 262d jal ra,300869a + 3008372: 4581 li a1,0 + 3008374: 018407b7 lui a5,0x1840 + 3008378: 23078513 addi a0,a5,560 # 1840230 + 300837c: 2e29 jal ra,3008696 + 300837e: 4581 li a1,0 + 3008380: 018407b7 lui a5,0x1840 + 3008384: 23078513 addi a0,a5,560 # 1840230 + 3008388: 2629 jal ra,3008692 + 300838a: 4585 li a1,1 + 300838c: 018407b7 lui a5,0x1840 + 3008390: 23078513 addi a0,a5,560 # 1840230 + 3008394: 2ced jal ra,300868e + 3008396: 4589 li a1,2 + 3008398: 018407b7 lui a5,0x1840 + 300839c: 23078513 addi a0,a5,560 # 1840230 + 30083a0: 24ed jal ra,300868a + 30083a2: 016807b7 lui a5,0x1680 + 30083a6: 23078513 addi a0,a5,560 # 1680230 + 30083aa: 2cc5 jal ra,300869a + 30083ac: 4581 li a1,0 + 30083ae: 016807b7 lui a5,0x1680 + 30083b2: 23078513 addi a0,a5,560 # 1680230 + 30083b6: 24c5 jal ra,3008696 + 30083b8: 4581 li a1,0 + 30083ba: 016807b7 lui a5,0x1680 + 30083be: 23078513 addi a0,a5,560 # 1680230 + 30083c2: 2cc1 jal ra,3008692 + 30083c4: 4585 li a1,1 + 30083c6: 016807b7 lui a5,0x1680 + 30083ca: 23078513 addi a0,a5,560 # 1680230 + 30083ce: 24c1 jal ra,300868e + 30083d0: 4589 li a1,2 + 30083d2: 016807b7 lui a5,0x1680 + 30083d6: 23078513 addi a0,a5,560 # 1680230 + 30083da: 2c45 jal ra,300868a + 30083dc: 001c07b7 lui a5,0x1c0 + 30083e0: 23078513 addi a0,a5,560 # 1c0230 + 30083e4: 2c5d jal ra,300869a + 30083e6: 4581 li a1,0 + 30083e8: 001c07b7 lui a5,0x1c0 + 30083ec: 23078513 addi a0,a5,560 # 1c0230 + 30083f0: 245d jal ra,3008696 + 30083f2: 4581 li a1,0 + 30083f4: 001c07b7 lui a5,0x1c0 + 30083f8: 23078513 addi a0,a5,560 # 1c0230 + 30083fc: 2c59 jal ra,3008692 + 30083fe: 4585 li a1,1 + 3008400: 001c07b7 lui a5,0x1c0 + 3008404: 23078513 addi a0,a5,560 # 1c0230 + 3008408: 2459 jal ra,300868e + 300840a: 4589 li a1,2 + 300840c: 001c07b7 lui a5,0x1c0 + 3008410: 23078513 addi a0,a5,560 # 1c0230 + 3008414: 2c9d jal ra,300868a + 3008416: 011407b7 lui a5,0x1140 + 300841a: 23078513 addi a0,a5,560 # 1140230 + 300841e: 2cb5 jal ra,300869a + 3008420: 4581 li a1,0 + 3008422: 011407b7 lui a5,0x1140 + 3008426: 23078513 addi a0,a5,560 # 1140230 + 300842a: 24b5 jal ra,3008696 + 300842c: 4581 li a1,0 + 300842e: 011407b7 lui a5,0x1140 + 3008432: 23078513 addi a0,a5,560 # 1140230 + 3008436: 2cb1 jal ra,3008692 + 3008438: 4585 li a1,1 + 300843a: 011407b7 lui a5,0x1140 + 300843e: 23078513 addi a0,a5,560 # 1140230 + 3008442: 24b1 jal ra,300868e + 3008444: 4589 li a1,2 + 3008446: 011407b7 lui a5,0x1140 + 300844a: 23078513 addi a0,a5,560 # 1140230 + 300844e: 2c35 jal ra,300868a + 3008450: 011c07b7 lui a5,0x11c0 + 3008454: 23078513 addi a0,a5,560 # 11c0230 + 3008458: 2489 jal ra,300869a + 300845a: 4581 li a1,0 + 300845c: 011c07b7 lui a5,0x11c0 + 3008460: 23078513 addi a0,a5,560 # 11c0230 + 3008464: 2c0d jal ra,3008696 + 3008466: 4581 li a1,0 + 3008468: 011c07b7 lui a5,0x11c0 + 300846c: 23078513 addi a0,a5,560 # 11c0230 + 3008470: 240d jal ra,3008692 + 3008472: 4585 li a1,1 + 3008474: 011c07b7 lui a5,0x11c0 + 3008478: 23078513 addi a0,a5,560 # 11c0230 + 300847c: 2c09 jal ra,300868e + 300847e: 4589 li a1,2 + 3008480: 011c07b7 lui a5,0x11c0 + 3008484: 23078513 addi a0,a5,560 # 11c0230 + 3008488: 2409 jal ra,300868a + 300848a: 012407b7 lui a5,0x1240 + 300848e: 23078513 addi a0,a5,560 # 1240230 + 3008492: 2421 jal ra,300869a + 3008494: 4581 li a1,0 + 3008496: 012407b7 lui a5,0x1240 + 300849a: 23078513 addi a0,a5,560 # 1240230 + 300849e: 2ae5 jal ra,3008696 + 30084a0: 4581 li a1,0 + 30084a2: 012407b7 lui a5,0x1240 + 30084a6: 23078513 addi a0,a5,560 # 1240230 + 30084aa: 22e5 jal ra,3008692 + 30084ac: 4585 li a1,1 + 30084ae: 012407b7 lui a5,0x1240 + 30084b2: 23078513 addi a0,a5,560 # 1240230 + 30084b6: 2ae1 jal ra,300868e + 30084b8: 4589 li a1,2 + 30084ba: 012407b7 lui a5,0x1240 + 30084be: 23078513 addi a0,a5,560 # 1240230 + 30084c2: 22e1 jal ra,300868a + 30084c4: 010407b7 lui a5,0x1040 + 30084c8: 23078513 addi a0,a5,560 # 1040230 + 30084cc: 22f9 jal ra,300869a + 30084ce: 4581 li a1,0 + 30084d0: 010407b7 lui a5,0x1040 + 30084d4: 23078513 addi a0,a5,560 # 1040230 + 30084d8: 2a7d jal ra,3008696 + 30084da: 4581 li a1,0 + 30084dc: 010407b7 lui a5,0x1040 + 30084e0: 23078513 addi a0,a5,560 # 1040230 + 30084e4: 227d jal ra,3008692 + 30084e6: 4585 li a1,1 + 30084e8: 010407b7 lui a5,0x1040 + 30084ec: 23078513 addi a0,a5,560 # 1040230 + 30084f0: 2a79 jal ra,300868e + 30084f2: 4589 li a1,2 + 30084f4: 010407b7 lui a5,0x1040 + 30084f8: 23078513 addi a0,a5,560 # 1040230 + 30084fc: 2279 jal ra,300868a + 30084fe: 73100513 li a0,1841 + 3008502: 2a61 jal ra,300869a + 3008504: 4581 li a1,0 + 3008506: 73100513 li a0,1841 + 300850a: 2271 jal ra,3008696 + 300850c: 4581 li a1,0 + 300850e: 73100513 li a0,1841 + 3008512: 2241 jal ra,3008692 + 3008514: 4585 li a1,1 + 3008516: 73100513 li a0,1841 + 300851a: 2a95 jal ra,300868e + 300851c: 4589 li a1,2 + 300851e: 73100513 li a0,1841 + 3008522: 22a5 jal ra,300868a + 3008524: 019007b7 lui a5,0x1900 + 3008528: 23378513 addi a0,a5,563 # 1900233 + 300852c: 22bd jal ra,300869a + 300852e: 4581 li a1,0 + 3008530: 019007b7 lui a5,0x1900 + 3008534: 23378513 addi a0,a5,563 # 1900233 + 3008538: 2ab9 jal ra,3008696 + 300853a: 4581 li a1,0 + 300853c: 019007b7 lui a5,0x1900 + 3008540: 23378513 addi a0,a5,563 # 1900233 + 3008544: 22b9 jal ra,3008692 + 3008546: 4585 li a1,1 + 3008548: 019007b7 lui a5,0x1900 + 300854c: 23378513 addi a0,a5,563 # 1900233 + 3008550: 2a3d jal ra,300868e + 3008552: 4589 li a1,2 + 3008554: 019007b7 lui a5,0x1900 + 3008558: 23378513 addi a0,a5,563 # 1900233 + 300855c: 223d jal ra,300868a + 300855e: 019407b7 lui a5,0x1940 + 3008562: 23378513 addi a0,a5,563 # 1940233 + 3008566: 2a15 jal ra,300869a + 3008568: 4589 li a1,2 + 300856a: 019407b7 lui a5,0x1940 + 300856e: 23378513 addi a0,a5,563 # 1940233 + 3008572: 2215 jal ra,3008696 + 3008574: 4581 li a1,0 + 3008576: 019407b7 lui a5,0x1940 + 300857a: 23378513 addi a0,a5,563 # 1940233 + 300857e: 2a11 jal ra,3008692 + 3008580: 4585 li a1,1 + 3008582: 019407b7 lui a5,0x1940 + 3008586: 23378513 addi a0,a5,563 # 1940233 + 300858a: 2211 jal ra,300868e + 300858c: 4589 li a1,2 + 300858e: 019407b7 lui a5,0x1940 + 3008592: 23378513 addi a0,a5,563 # 1940233 + 3008596: 28d5 jal ra,300868a + 3008598: 012807b7 lui a5,0x1280 + 300859c: 23378513 addi a0,a5,563 # 1280233 + 30085a0: 28ed jal ra,300869a + 30085a2: 4581 li a1,0 + 30085a4: 012807b7 lui a5,0x1280 + 30085a8: 23378513 addi a0,a5,563 # 1280233 + 30085ac: 20ed jal ra,3008696 + 30085ae: 4581 li a1,0 + 30085b0: 012807b7 lui a5,0x1280 + 30085b4: 23378513 addi a0,a5,563 # 1280233 + 30085b8: 28e9 jal ra,3008692 + 30085ba: 4585 li a1,1 + 30085bc: 012807b7 lui a5,0x1280 + 30085c0: 23378513 addi a0,a5,563 # 1280233 + 30085c4: 20e9 jal ra,300868e + 30085c6: 4589 li a1,2 + 30085c8: 012807b7 lui a5,0x1280 + 30085cc: 23378513 addi a0,a5,563 # 1280233 + 30085d0: 286d jal ra,300868a + 30085d2: 012c07b7 lui a5,0x12c0 + 30085d6: 23378513 addi a0,a5,563 # 12c0233 + 30085da: 20c1 jal ra,300869a + 30085dc: 4589 li a1,2 + 30085de: 012c07b7 lui a5,0x12c0 + 30085e2: 23378513 addi a0,a5,563 # 12c0233 + 30085e6: 2845 jal ra,3008696 + 30085e8: 4581 li a1,0 + 30085ea: 012c07b7 lui a5,0x12c0 + 30085ee: 23378513 addi a0,a5,563 # 12c0233 + 30085f2: 2045 jal ra,3008692 + 30085f4: 4585 li a1,1 + 30085f6: 012c07b7 lui a5,0x12c0 + 30085fa: 23378513 addi a0,a5,563 # 12c0233 + 30085fe: 2841 jal ra,300868e + 3008600: 4589 li a1,2 + 3008602: 012c07b7 lui a5,0x12c0 + 3008606: 23378513 addi a0,a5,563 # 12c0233 + 300860a: 2041 jal ra,300868a + 300860c: 017807b7 lui a5,0x1780 + 3008610: 23178513 addi a0,a5,561 # 1780231 + 3008614: 2059 jal ra,300869a + 3008616: 4581 li a1,0 + 3008618: 017807b7 lui a5,0x1780 + 300861c: 23178513 addi a0,a5,561 # 1780231 + 3008620: 289d jal ra,3008696 + 3008622: 4581 li a1,0 + 3008624: 017807b7 lui a5,0x1780 + 3008628: 23178513 addi a0,a5,561 # 1780231 + 300862c: 209d jal ra,3008692 + 300862e: 4585 li a1,1 + 3008630: 017807b7 lui a5,0x1780 + 3008634: 23178513 addi a0,a5,561 # 1780231 + 3008638: 2899 jal ra,300868e + 300863a: 4589 li a1,2 + 300863c: 017807b7 lui a5,0x1780 + 3008640: 23178513 addi a0,a5,561 # 1780231 + 3008644: 2099 jal ra,300868a + 3008646: 017c07b7 lui a5,0x17c0 + 300864a: 23178513 addi a0,a5,561 # 17c0231 + 300864e: 20b1 jal ra,300869a + 3008650: 4581 li a1,0 + 3008652: 017c07b7 lui a5,0x17c0 + 3008656: 23178513 addi a0,a5,561 # 17c0231 + 300865a: 2835 jal ra,3008696 + 300865c: 4581 li a1,0 + 300865e: 017c07b7 lui a5,0x17c0 + 3008662: 23178513 addi a0,a5,561 # 17c0231 + 3008666: 2035 jal ra,3008692 + 3008668: 4585 li a1,1 + 300866a: 017c07b7 lui a5,0x17c0 + 300866e: 23178513 addi a0,a5,561 # 17c0231 + 3008672: 2831 jal ra,300868e + 3008674: 4589 li a1,2 + 3008676: 017c07b7 lui a5,0x17c0 + 300867a: 23178513 addi a0,a5,561 # 17c0231 + 300867e: 2031 jal ra,300868a + 3008680: 0001 nop + 3008682: 40b2 lw ra,12(sp) + 3008684: 4422 lw s0,8(sp) + 3008686: 0141 addi sp,sp,16 + 3008688: 8082 ret + +0300868a : + 300868a: dfafd06f j 3005c84 + +0300868e : + 300868e: daafd06f j 3005c38 + +03008692 : + 3008692: d5afd06f j 3005bec + +03008696 : + 3008696: d0afd06f j 3005ba0 + +0300869a : + 300869a: cccfd06f j 3005b66 + +0300869e : + 300869e: 1141 addi sp,sp,-16 + 30086a0: c606 sw ra,12(sp) + 30086a2: c422 sw s0,8(sp) + 30086a4: 0800 addi s0,sp,16 + 30086a6: 3199 jal ra,30082ec + 30086a8: 3411 jal ra,30080ac + 30086aa: 361d jal ra,30081d0 + 30086ac: ff6ff0ef jal ra,3007ea2 + 30086b0: 30fd jal ra,3007f9e + 30086b2: f3cff0ef jal ra,3007dee + 30086b6: cb0ff0ef jal ra,3007b66 + 30086ba: 0001 nop + 30086bc: 40b2 lw ra,12(sp) + 30086be: 4422 lw s0,8(sp) + 30086c0: 0141 addi sp,sp,16 + 30086c2: 8082 ret + +030086c4 <__rodata_start>: + 30086c4: 9680 pop {ra,s0-s6},384 + 30086c6: 4b18 lw a4,16(a4) + +030086c8 : + 30086c8: 0000 1400 0000 0000 0140 0000 1000 1400 ........@....... + 30086d8: 0000 0000 0144 0000 2000 1400 0000 0000 ....D.... ...... + 30086e8: 0148 0000 3000 1400 0000 0000 014c 0000 H....0......L... + 30086f8: 0000 1430 0000 0000 0240 0000 1000 1430 ..0.....@.....0. + 3008708: 0000 0000 0244 0000 2000 1430 0000 0000 ....D.... 0..... + 3008718: 0248 0000 3000 1430 0000 0000 024c 0000 H....00.....L... + 3008728: 0000 1438 0000 0000 0040 0000 0000 1420 ..8.....@..... . + 3008738: 0000 0000 0180 0000 1000 1420 0000 0000 .......... ..... + 3008748: 0184 0000 0000 1410 0000 0000 01c0 0000 ................ + 3008758: 1000 1410 0000 0000 01c4 0000 0000 1460 ..............`. + 3008768: 0001 0000 02c0 0000 0000 1470 0000 0000 ..........p..... + 3008778: 0440 0000 1000 1470 0000 0000 0444 0000 @.....p.....D... + 3008788: 2000 1470 0000 0000 0448 0000 3000 1470 . p.....H....0p. + 3008798: 0000 0000 044c 0000 0000 1440 0000 0000 ....L.....@..... + 30087a8: 0200 0000 0000 14b0 0000 0000 0280 0000 ................ + 30087b8: 1000 14b0 0000 0000 0284 0000 2000 14b0 ............. .. + 30087c8: 0000 0000 0288 0000 0000 1c00 0000 0000 ................ + 30087d8: 0300 0000 0000 1450 0000 0000 0480 0000 ......P......... + 30087e8: 1000 1450 0000 0000 0484 0000 2000 1450 ..P.......... P. + 30087f8: 0000 0000 0488 0000 3000 1450 0000 0000 .........0P..... + 3008808: 048c 0000 4000 1450 0000 0000 0490 0000 .....@P......... + 3008818: 5000 1450 0000 0000 0494 0000 1000 1440 .PP...........@. + 3008828: 0004 0000 03c0 0000 0000 14c0 0000 0000 ................ + 3008838: 04c0 0000 1000 14c0 0000 0000 04c4 0000 ................ + 3008848: 0000 147d 0000 0000 0b00 0000 0000 1480 ..}............. + 3008858: 0000 0000 0380 0000 0000 14a0 0000 0000 ................ + 3008868: 0400 0000 1000 14a0 0000 0000 0404 0000 ................ + 3008878: 2000 14a0 0000 0000 0408 0000 3000 14a0 . ...........0.. + 3008888: 0000 0000 040c 0000 0000 1001 0000 0000 ................ + 3008898: 0340 0000 0000 1810 0005 0000 0a60 0000 @...........`... + 30088a8: 0000 1830 0005 0000 0a70 0000 0000 1840 ..0.....p.....@. + 30088b8: 0005 0000 0a80 0000 0000 1820 0005 0000 .......... ..... + 30088c8: 0a90 0000 1000 1820 0005 0000 0a90 0004 ...... ......... + 30088d8: 0000 1800 0002 0000 0a00 0000 0000 1471 ..............q. + 30088e8: 0003 0000 0500 0000 2e2e 642f 6972 6576 ........../drive + 30088f8: 7372 622f 7361 2f65 7273 2f63 6e69 6574 rs/base/src/inte + 3008908: 7272 7075 2e74 0063 1660 0300 16b2 0300 rrupt.c.`....... + 3008918: 1704 0300 1756 0300 17a8 0300 17fa 0300 ....V........... + 3008928: 184c 0300 189e 0300 1934 0300 1986 0300 L.......4....... + 3008938: 19d8 0300 1a2a 0300 1a7c 0300 1ace 0300 ....*...|....... + 3008948: 1b20 0300 1b72 0300 2e2e 642f 6972 6576 ...r...../drive + 3008958: 7372 632f 6772 692f 636e 632f 6772 695f rs/crg/inc/crg_i + 3008968: 2e70 0068 2e2e 642f 6972 6576 7372 632f p.h.../drivers/c + 3008978: 6772 732f 6372 632f 6772 632e 0000 0000 rg/src/crg.c.... + 3008988: 0000 0000 0001 0000 0002 0000 0003 0000 ................ + 3008998: 0004 0000 0005 0000 0006 0000 0007 0000 ................ + 30089a8: 25f2 0300 25fc 0300 2614 0300 25f2 0300 .%...%...&...%.. + 30089b8: 2630 0300 25f2 0300 2e2e 642f 6972 6576 0&...%..../drive + 30089c8: 7372 672f 6970 2f6f 6e69 2f63 7067 6f69 rs/gpio/inc/gpio + 30089d8: 695f 2e70 0068 0000 2e2e 642f 6972 6576 _ip.h...../drive + 30089e8: 7372 672f 6970 2f6f 7273 2f63 7067 6f69 rs/gpio/src/gpio + 30089f8: 632e 0000 2e2e 642f 6972 6576 7372 692f .c..../drivers/i + 3008a08: 6332 732f 6372 692f 6332 632e 0000 0000 2c/src/i2c.c.... + 3008a18: 4b40 0300 4b60 0300 4b76 0300 4bba 0300 @K..`K..vK...K.. + 3008a28: 4bd6 0300 2e2e 642f 6972 6576 7372 692f .K..../drivers/i + 3008a38: 636f 676d 692f 636e 692f 636f 676d 695f ocmg/inc/iocmg_i + 3008a48: 2e70 0068 2e2e 642f 6972 6576 7372 692f p.h.../drivers/i + 3008a58: 636f 676d 732f 6372 692f 636f 676d 632e ocmg/src/iocmg.c + 3008a68: 0000 0000 2e2e 642f 6972 6576 7372 742f ....../drivers/t + 3008a78: 6d69 7265 692f 636e 742f 6d69 7265 695f imer/inc/timer_i + 3008a88: 2e70 0068 2e2e 642f 6972 6576 7372 742f p.h.../drivers/t + 3008a98: 6d69 7265 732f 6372 742f 6d69 7265 632e imer/src/timer.c + 3008aa8: 0000 0000 6470 0300 6486 0300 649c 0300 ....pd...d...d.. + 3008ab8: 64b2 0300 64c8 0300 2e2e 642f 6972 6576 .d...d..../drive + 3008ac8: 7372 752f 7261 2f74 7273 2f63 6175 7472 rs/uart/src/uart + 3008ad8: 632e 0000 71ec 0300 71f8 0300 7204 0300 .c...q...q...r.. + 3008ae8: 7210 0300 721c 0300 7228 0300 7234 0300 .r...r..(r..4r.. + 3008af8: 7240 0300 724c 0300 761a 0300 7660 0300 @r..Lr...v..`v.. + 3008b08: 76a6 0300 76ec 0300 7732 0300 .v...v..2w.. + +03008b14 : + 3008b14: 00ef 0737 1738 0639 0041 0042 2d46 0f47 ..7.8.9.A.B.F-G. + 3008b24: 3c48 0049 1e4a 204c 1051 105e 2760 4280 H. + 3008b64: 3d5e 9665 9767 cd69 016a 2c6d 016e 0172 ^=e.g.i.j.m,n.r. + 3008b74: 3573 0074 0177 0000 s5t.w... + +03008b7c : + 3008b7c: 00ef 0041 0042 00ef 3c48 0049 1051 2083 ..A.B...H + + + + + + + + + + + diff --git a/vendor/xinlingyu_92_3061M/Project/build/ide_entry.py b/vendor/xinlingyu_92_3061M/Project/build/ide_entry.py new file mode 100644 index 0000000000000000000000000000000000000000..163938d98295905b7dea0509aa7ad01b25c46726 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/build/ide_entry.py @@ -0,0 +1,204 @@ +# !/usr/bin/env python +# -*- coding: utf-8 -*- + +# @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +# following disclaimer in the documentation and/or other materials provided with the distribution. +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote +# products derived from this software without specific prior written permission. +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# ide_entry.py Function implementation: ide build entry file, which is used to +# copy code and invoke build compilation scripts. + +import os +import sys +import stat +import pathlib +import glob +import tarfile +import zipfile +import platform +import shutil +from configparser import ConfigParser +import shlex +import subprocess +from build import remove_readonly + +from build_gn import read_json_file + + +def copy_code(product, copy_path): + ''' + Function description: Code copy phase for CI build work. + ''' + + # Instantiation parameter check. + if not isinstance(copy_path, str): + raise TypeError("copy_path in para type error {}".format( + type(copy_path))) + if not isinstance(product, str): + raise TypeError("product in para type error {}".format( + type(product))) + + if pathlib.Path(copy_path).exists(): + shutil.rmtree(os.path.realpath(copy_path), onerror=remove_readonly) + + copy_abspath = pathlib.Path(copy_path).resolve() + copyjson_path = pathlib.Path.cwd()\ + .joinpath('chip', "{}".format(product), 'codecopy.json') + copyjson_content = read_json_file(copyjson_path) + for module_path in copyjson_content['modules']: + if pathlib.Path(module_path).is_dir(): + traversal_path(copy_abspath, module_path) + elif pathlib.Path(module_path).is_file(): + parent_path = pathlib.Path(module_path).parent + copy_parent_path = pathlib.Path(copy_abspath).joinpath(parent_path) + if not copy_parent_path.exists(): + os.makedirs(copy_parent_path) + shutil.copy(module_path, copy_parent_path) + + +def traversal_path(copy_path, module_path): + ''' + Function description: Traverse the path and then perform the create + and copy work. + ''' + + ipbefore_list = [] + ipafter_list = [] + cur_sys = platform.system() + + for (dirpath, _, filenames) in os.walk(module_path): + if cur_sys == 'Windows': + ipbefore_list = dirpath.split('\\') + elif cur_sys == 'Linux': + ipbefore_list = dirpath.split('/') + ipafter_list = [] + for ipdir in ipbefore_list: + if ipdir.startswith('v') and '.' in ipdir: + continue + ipafter_list.append(ipdir) + dirprocesspath = '/'.join(ipafter_list) + dest_path = pathlib.Path(copy_path).joinpath(dirprocesspath) + if not dest_path.exists(): + os.makedirs(dest_path) + for file in filenames: + if 'entry.py' in file or 'trustlist.json' in file: + continue + source_file = pathlib.Path(dirpath).joinpath(file) + shutil.copy(source_file, dest_path) + + +def untar(filename): + ''' + Function description: Decompress the tar or tar.gz file. + ''' + + tar = tarfile.open(filename) + tar.extractall(pathlib.Path()) + tar.close() + + +def unzip(filename): + ''' + Function description: Decompress the zip file. + ''' + + max_size = 1 * 1024 * 1024 * 500 + cur_size = 0 + + zip_file = zipfile.ZipFile(filename) + filename = filename.split('.')[0] + if not os.path.isdir(filename): + os.mkdir(filename) + for names in zip_file.infolist(): + cur_size += names.file_size + if cur_size > max_size: + break + zip_file.extract(names.filename, filename) + zip_file.close() + + +def del_decfile(tools_path): + ''' + Function description: Delete the decompressed files. + ''' + + file_lst = glob.glob(tools_path + '/*') + filename_lst = [os.path.basename(i) for i in file_lst if '.' not in os.path.basename(i)] + for filename in filename_lst: + shutil.rmtree(filename, onerror=remove_readonly) + + +def un_alltools(tools_path): + ''' + Function description: Decompress all compilation tools. + ''' + + # Judgment system. + cur_sys = platform.system() + path = str(pathlib.Path(tools_path).joinpath(cur_sys)) + cur_path = os.getcwd() + + os.chdir(path) + del_decfile(path) + + # Decompress all compressed files. + file_lst = glob.glob(path + '/*') + filename_lst = [os.path.basename(i) for i in file_lst] + for filename in filename_lst: + if '.' in filename: + suffix = filename.split('.')[-1] + if suffix == 'gz' or suffix == 'tar': + untar(filename) + if suffix == 'zip': + unzip(filename) + os.chdir(os.path.realpath(cur_path)) + + +def ide_entry(argv): + ''' + Function description: ci entry function. + ''' + + # Save the path of the full package tool. + tools_path = str(pathlib.Path().cwd().joinpath('tools', 'toolchain')) + if len(argv) == 3: + copy_chip = argv[1] + copy_path = argv[2] + else: + copy_chip = '3065h' + copy_path = '../mcu_pro' + + # Decompress all compilation tools. + un_alltools(tools_path) + + # Detach the chip package. + copy_code(copy_chip, copy_path) + + os.chdir(pathlib.Path(copy_path).resolve()) + # Write the path of the full package tool to the config.ini file. + config_path = pathlib.Path().cwd().joinpath('build', 'config.ini') + config = ConfigParser() + config.read(config_path) + config.set('gn_args', 'tools_path', tools_path) + flags = os.O_WRONLY | os.O_CREAT | os.O_TRUNC + modes = stat.S_IWUSR | stat.S_IRUSR + with os.fdopen(os.open(config_path, flags, modes), 'w+') as configini: + config.write(configini) + + os.makedirs("ohos_bundles") + + +if __name__ == "__main__": + sys.exit(ide_entry(sys.argv)) diff --git a/vendor/xinlingyu_92_3061M/Project/build/packet_create.py b/vendor/xinlingyu_92_3061M/Project/build/packet_create.py new file mode 100644 index 0000000000000000000000000000000000000000..73add298718142d38237681df82a13eb3d6f37d0 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/build/packet_create.py @@ -0,0 +1,460 @@ +#!/usr/bin/env python3 +# coding=utf-8 + +''' +# @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +# following disclaimer in the documentation and/or other materials provided with the distribution. +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote +# products derived from this software without specific prior written permission. +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# ide_entry.py Function implementation: ide build entry file, which is used to +# copy code and invoke build compilation scripts. +''' +import struct +import sys +import os +import stat +import pathlib +import zlib +import copy +import socket +import collections +from configparser import ConfigParser + + +class Crc16: + POLYNOMIAL = 0x1021 + PRESET = 0x0000 + _tab = [] + + def __init__(self): + self._tab = [self._initial(i) for i in range(256)] + + def crc(self, string): + crc = self.PRESET + for c in string: + crc = self._update_crc(crc, ord(c)) + return crc + + def crcb(self, i): + crc = self.PRESET + for c in i: + crc = self._update_crc(crc, c) + return crc + + def _initial(self, c): + crc = 0 + c = c << 8 + for _i in range(8): + if (crc ^ c) & 0x8000: + crc = (crc << 1) ^ self.POLYNOMIAL + else: + crc = crc << 1 + c = c << 1 + return crc + + def _update_crc(self, crc, c): + cc = 0xff & int(c) + + tmp = (crc >> 8) ^ cc + crc = (crc << 8) ^ self._tab[tmp & 0xff] + crc = crc & 0xffff + return crc + + +def get_config(name): + deveco_path = './.deveco/deveco.ini' + env = "env:" + name + config = ConfigParser() + config.read(deveco_path) + init_value = 'no' + config_dict = dict(generate_crc=init_value, generate_checksum=init_value, padding=init_value) + if name == init_value: + return config_dict + key = 'generate_crc' + if key in config[env]: + config_dict[key] = config[env].get(key) + key = 'generate_checksum' + if key in config[env]: + config_dict[key] = config[env].get(key) + key = 'padding' + if key in config[env]: + config_dict[key] = config[env].get(key) + return config_dict + + +def packet_bin(output_path, input_list): + t = Crc16() + path_list = [] + burn_addr_list = [] + burn_size_list = [] + image_size_list = [] + type_list = [] + for item in input_list: + path, burn_addr, burn_size, burn_type = item.split("|") + image_size = os.path.getsize(path) + path_list.append(path) + burn_addr_list.append(int(burn_addr)) + burn_size_list.append(int(burn_size)) + image_size_list.append(image_size) + type_list.append(int(burn_type)) + + flag = 0xefbeaddf + crc = 0 + image_num = len(path_list) + head_len = image_num * 52 + 12 + total_file_size = sum(image_size_list) + head_len + + flags = os.O_RDWR | os.O_CREAT + modes = stat.S_IWUSR | stat.S_IRUSR + with os.fdopen(os.open(output_path, flags, modes), 'wb+') as file: + file.write(struct.pack('IHHI', flag, crc, image_num, total_file_size)) + start_index = head_len + times = 0 + for path in path_list: + path_name = os.path.basename(path) + file.write( + struct.pack('32sIIIII', bytes(path_name, 'ascii'), start_index, + image_size_list[times], burn_addr_list[times], + burn_size_list[times], type_list[times])) + start_index = start_index + image_size_list[times] + 16 + times += 1 + + for path in path_list: + with os.fdopen(os.open(path, flags, modes), 'rb+') as subfile: + data = subfile.read() + file.write(data) + file.write(struct.pack('IIII', 0, 0, 0, 0)) + + file.flush() + file.seek(6) + newdata = file.read(head_len - 6) + crc16 = t.crcb(newdata) + file.seek(4) + file.write(struct.pack('H', crc16)) + + +def get_len_addr_type(line): + data = int(line[1:9], 16) + length = data >> 24 + addr = (data >> 8) & 0xffff + data_type = data & 0xff + ext_data = int(line[10:13], 16) + Information = collections.namedtuple('Information', ['length', 'addr', 'data_type', 'ext_data']) + return Information(length, addr, data_type, ext_data) + + +def is_start_linear_addr_rec_line(data_type): + return True if data_type == 5 else False + + +def is_ext_linear_addr_rec_line(data_type): + return True if data_type == 4 else False + + +def add_ext_linear_addr_record(fp, addr): + checksum = 0 + data = [] + data.append(':02000004') + checksum += 6 + checksum += (addr & 0xff) + checksum += ((addr >> 8) & 0xff) + data.append("%04x".upper() % (addr)) + checksum = (0x100 - checksum % 0x100) & 0xFF + data.append("%02x".upper() % (checksum)) + data.append('\n') + fp.writelines(data) + + +def add_data_of_crc(fp, addr, crc_val): + checksum = 0 + data = [] + data.append(':04') + checksum += 4 + data.append("%04x".upper() % (addr)) + checksum += (addr & 0xff) + checksum += ((addr >> 8) & 0xff) + data.append('00') + data.append("%08x".upper() % (socket.htonl(crc_val))) + checksum += (crc_val & 0xff) + checksum += ((crc_val >> 8) & 0xff) + checksum += ((crc_val >> 16) & 0xff) + checksum += ((crc_val >> 24) & 0xff) + checksum = (0x100 - checksum % 0x100) & 0xFF + data.append("%02x".upper() % (checksum)) + data.append('\n') + fp.writelines(data) + + +def add_crc(fp, ext_addr, address, crc_val): + addr = address + if addr > 0xFFFF: + add_ext_linear_addr_record(fp, ext_addr + 1) + addr = 0 + add_data_of_crc(fp, addr, crc_val) + + +def gen_crc_padding(fp, lines, crc_val): + is_start_linear_addr_rec = False + ext_linear_addr = 0 + next_addr = 0 + + for line in lines: + length, addr, data_type, ext_data = get_len_addr_type(line) + if is_ext_linear_addr_rec_line(data_type): + ext_linear_addr = ext_data + if not is_start_linear_addr_rec_line(data_type): + next_addr = addr + length + else: + if not is_start_linear_addr_rec: + is_start_linear_addr_rec = True + add_crc(fp, ext_linear_addr, next_addr, crc_val) + fp.writelines(line) + + +def gen_crc_for_hex(filename, crc_val): + flags = os.O_RDWR + modes = stat.S_IWUSR | stat.S_IRUSR + + lines = [] + with os.fdopen(os.open(filename, flags, modes), 'r') as file: + lines = file.readlines() + + flag = os.O_RDWR | os.O_CREAT + with os.fdopen(os.open(filename, flag, modes), 'w+') as file: + gen_crc_padding(file, lines, crc_val) + + +def gen_crc(filename, filename_hex): + flags = os.O_RDWR + modes = stat.S_IWUSR | stat.S_IRUSR + with os.fdopen(os.open(filename, flags, modes), 'rb') as f: + data = f.read() + crc_val = zlib.crc32(data) & 0xFFFFFFFF + with os.fdopen(os.open(filename, flags, modes), 'rb+') as file: + file.seek(0, 2) + crc_val = socket.htonl(crc_val) + file.write(struct.pack('I', crc_val)) + gen_crc_for_hex(filename_hex, crc_val) + + +def findfiles(path, types): + file_list = [] + files = os.listdir(path) + for f in files: + npath = "{}/{}".format(path, f) + if os.path.isfile(npath): + if os.path.splitext(npath)[-1] in types: + file_list.append(npath) + return file_list + + +def packet_bin_with_padding(file, length, val): + while length >= 32: + file.write(struct.pack('IIIIIIII', + val, val, val, val, val, val, val, val)) + length = length - 32 + while length >= 4: + file.write(struct.pack('I', val)) + length = length - 4 + while length > 0: + file.write(struct.pack('B', val & 0xFF)) + length = length - 1 + + +def gen_padding_for_bin(filename, max_len, pad_bit): + flags = os.O_RDWR | os.O_CREAT + modes = stat.S_IWUSR | stat.S_IRUSR + with os.fdopen(os.open(filename, flags, modes), 'ab+') as file: + pad_val = 0xFFFFFFFF + if pad_bit == '0': + pad_val = 0 + image_size = os.path.getsize(filename) + pad_len = max_len - image_size + packet_bin_with_padding(file, pad_len, pad_val) + return pad_len + + +def get_hex_addr(lines): + ext_addr = 0 + next_addr = 0 + for line in lines: + length, addr, data_type, ext_data = get_len_addr_type(line) + if data_type == 4: + ext_addr = ext_data + if data_type == 0: + next_addr = addr + length + return ext_addr, next_addr + + +def get_line_pad_len(addr, max_pad_len): + line_space_size = 0xFFFF - addr + 1 + pad_len = 16 if max_pad_len >= 16 else max_pad_len + if pad_len > line_space_size: + pad_len = line_space_size + return pad_len + + +def gen_ext_addr_rec(ext_addr): + checksum = 0 + data = '' + data += ':02000004' + checksum += 6 + checksum += (ext_addr & 0xff) + checksum += ((ext_addr >> 8) & 0xff) + data += "%04x".upper() % ext_addr + checksum = (0x100 - (checksum & 0xFF)) & 0xFF + data += "%02x\n".upper() % (checksum) + return data + + +def gen_padding_line_rec(addr, length, pad_bit): + checksum = 0 + data = '' + data += ":%02x".upper() % length + checksum += length & 0xff + checksum += (addr & 0xff) + checksum += ((addr >> 8) & 0xff) + data += "%04x00".upper() % addr + pad_val = 0xFF if pad_bit == '1' else 0 + for _i in range(length): + data += "%02x".upper() % pad_val + checksum += pad_val + checksum = (0x100 - (checksum & 0xFF)) & 0xFF + data += "%02x\n".upper() % (checksum) + return data + + +def gen_padding_lines_for_hex(ext_addr, addr, length, pad_bit): + lines = [] + + while length > 0: + pad_len = get_line_pad_len(addr, length) + lines.append(gen_padding_line_rec(addr, pad_len, pad_bit)) + length -= pad_len + addr += pad_len + if addr == 0x10000 and length > 0: + ext_addr += 1 + lines.append(gen_ext_addr_rec(ext_addr)) + addr = 0 + return lines + + +def gen_padding_for_hex(filename, pad_len, pad_bit): + ''' + Generate padding for target.hex + ''' + flags = os.O_RDWR + modes = stat.S_IWUSR | stat.S_IRUSR + lines = [] + ext_addr = int(0) + next_addr = int(0) + with os.fdopen(os.open(filename, flags, modes), 'r') as file: + lines = file.readlines() + ext_addr, next_addr = get_hex_addr(lines) + + start_linear_addr_rec = lines[-2] + end_of_file_rec = lines[-1] + lines.pop() + lines.pop() + + lines += gen_padding_lines_for_hex(ext_addr, next_addr, pad_len, pad_bit) + lines += start_linear_addr_rec + lines += end_of_file_rec + + flag = os.O_RDWR | os.O_CREAT + with os.fdopen(os.open(filename, flag, modes), 'w+') as file: + file.writelines(lines) + + +def gen_checksum_list(filename): + ''' + Generate Checksum list + ''' + path = "./out/bin" + type_list = ['.bin', '.hex'] + file_list = findfiles(path, type_list) + checksum_list = [] + + flags = os.O_RDWR | os.O_CREAT + modes = stat.S_IWUSR | stat.S_IRUSR + for item in file_list: + with os.fdopen(os.open(item, flags, modes), 'rb') as f: + data = f.read() + crc_val = zlib.crc32(data) & 0xFFFFFFFF + file_crc_dict = {} + file_crc_dict['file'] = os.path.split(item)[1] + file_crc_dict['crc'] = hex(crc_val) + checksum_list.append(file_crc_dict) + + with os.fdopen(os.open(filename, flags, modes), 'w') as f: + for info in checksum_list: + file_name = "{}\n".format(info['file']) + f.write(file_name) + crc_str = "CRC:{}\n\n".format(info['crc']) + f.write(crc_str) + + +def main(argv): + ''' + Function description: + 1. add crc for target.bin and hex.bin if generate_crc = yes + 2. add padding for target.bin if padding enable + 3. generate checksum_list.txt and print in IDE TERMINAL windows + 4. Combine loader.bin with image.bin into allinone.bin. + ''' + chipname = 'no' + flashsize = 0 + if len(argv) == 3: + chipname = argv[1] + flashsize = argv[2] + cfg_dict = get_config(chipname) + cfg_dict['max_len'] = flashsize + + loaderbin_path = "./middleware/hisilicon/loaderboot/loader.bin" + targetbin_path = "./out/bin/target.bin" + targethex_path = "./out/bin/target.hex" + allinonebin_path = "./out/bin/allinone.bin" + chksumlisttxt_path = "./out/bin/checksum_list.txt" + str_padding = "padding" + + curpath = pathlib.Path().cwd() + bootloaderpath = curpath.joinpath(loaderbin_path) + eflashpath = curpath.joinpath(targetbin_path) + output_path = curpath.joinpath(allinonebin_path) + + if cfg_dict.get('generate_crc') == 'yes': + gen_crc(targetbin_path, targethex_path) + + if cfg_dict.get(str_padding) != 'no': + pad_len = gen_padding_for_bin(targetbin_path, + int(cfg_dict.get('max_len')), + cfg_dict.get(str_padding)) + gen_padding_for_hex(targethex_path, pad_len, cfg_dict.get(str_padding)) + + input_list = [ + "{}|{}|{}|0".format( + bootloaderpath, 0x2000000, 0x2000000 + 0x3FFF), + "{}|{}|{}|1".format( + eflashpath, 0x3000000, 0x3000000 + 0x27FFF) + ] + + packet_bin(output_path, input_list) + + if cfg_dict.get('generate_checksum') == 'yes': + gen_checksum_list(chksumlisttxt_path) + + +if __name__ == "__main__": + sys.exit(main(sys.argv)) diff --git a/vendor/xinlingyu_92_3061M/Project/build/toolchain/BUILD.gn b/vendor/xinlingyu_92_3061M/Project/build/toolchain/BUILD.gn new file mode 100644 index 0000000000000000000000000000000000000000..282da139fe593eb7d8f6c12f4c4e3968e3863490 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/build/toolchain/BUILD.gn @@ -0,0 +1,28 @@ +# @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +# following disclaimer in the documentation and/or other materials provided with the distribution. +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote +# products derived from this software without specific prior written permission. +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# BUILD.gn Function implementation: Pre-configuration of the Compilation Toolchain + +import("//build/toolchain/config.gni") + +hcc_toolchain("riscv32_hcc") { + build_compiler_prefix = "riscv32-linux-musl" + cc = "${build_compiler_prefix}-gcc" + cxx = "${build_compiler_prefix}-g++" + ar = "${build_compiler_prefix}-ar" + ld = cc +} + diff --git a/vendor/xinlingyu_92_3061M/Project/build/toolchain/config.gni b/vendor/xinlingyu_92_3061M/Project/build/toolchain/config.gni new file mode 100644 index 0000000000000000000000000000000000000000..2fb29c7582612e0109592c4d7921a2a7cef83fb2 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/build/toolchain/config.gni @@ -0,0 +1,131 @@ +# @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +# following disclaimer in the documentation and/or other materials provided with the distribution. +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote +# products derived from this software without specific prior written permission. +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# config.gni Function implementation: Global parameter definition and template configuration + +declare_args() { + build_type = "" + build_compiler_specified = "" +} + +template("hcc_toolchain") { + toolchain(target_name) { + assert(defined(invoker.ar), "gcc toolchain must specify a \"ar\" value") + assert(defined(invoker.cc), "gcc toolchain must specify a \"cc\" value") + assert(defined(invoker.cxx), "gcc toolchain must specify a \"cxx\" value") + assert(defined(invoker.ld), "gcc toolchain must specify a \"ld\" value") + + cc = invoker.cc + cxx = invoker.cxx + ar = invoker.ar + ld = invoker.ld + + need_strip = false + if(defined(invoker.strip)) { + strip = invoker.strip + need_strip = true + } + + tool("cc") { + depfile = "{{output}}.d" + command = "$cc -MMD -MF $depfile {{defines}} {{include_dirs}} {{cflags}} -c {{source}} -o {{output}}" + depsformat = "gcc" + description = "cross compiler {{output}}" + outputs = [ + "{{source_out_dir}}/{{source_name_part}}.o", + ] + } + tool("cxx") { + depfile = "{{output}}.d" + command = "$cxx -MMD -MF $depfile {{defines}} {{include_dirs}} {{cflags}} -c {{source}} -o {{output}}" + depsformat = "gcc" + description = "CXX {{output}}" + outputs = [ + "{{source_out_dir}}/{{target_output_name}}.{{source_name_part}}.o", + ] + } + tool("asm") { + depfile = "{{output}}.d" + command = "$cc -MMD -MF $depfile {{defines}} {{include_dirs}} {{cflags}} {{asmflags}} -c {{source}} -o {{output}}" + depsformat = "gcc" + description = "cross compiler {{output}}" + outputs = [ + "{{source_out_dir}}/{{source_name_part}}.o" + ] + } + tool("alink") { + outfile = "{{output_dir}}/{{target_output_name}}{{output_extension}}" + rspfile = "{{output}}.rsp" + rspfile_content = "{{inputs}}" + command = "$ar cr {{output}} @\"$rspfile\"" + + description = "AR {{output}}" + outputs = [ + outfile + ] + + default_output_dir = "{{root_out_dir}}/libs" + default_output_extension = ".a" + output_prefix = "lib" + } + tool("solink") { + outfile = "{{output_dir}}/{{target_output_name}}{{output_extension}}" + rspfile = "{{output}}.rsp" + rspfile_content = "{{inputs}}" + command = "$ld -shared -Wl,--start-group {{ldflags}} " + + "{{inputs}} {{libs}} -Wl,--end-group -o $outfile" + if(need_strip) { + command += "&& $strip $outfile" + } + description = "SOLINK $outfile" + outputs = [ + outfile + ] + + default_output_dir = "{{root_out_dir}}" + default_output_extension = ".so" + output_prefix = "lib" + } + tool("link") { + outfile = "{{output_dir}}/bin/{{target_output_name}}{{output_extension}}" + rspfile = "$outfile.rsp" + command = "$ld -Wl,--start-group {{ldflags}} " + + "-Wl,--whole-archive @$rspfile -Wl,--no-whole-archive {{libs}} -Wl,--end-group -o $outfile" + if(need_strip) { + command += "&& $strip $outfile" + } + + description = "LINK $outfile" + default_output_dir = "{{root_out_dir}}" + rspfile_content = "{{inputs}}" + outputs = [ + outfile + ] + } + tool("stamp") { + if (host_os == "win") { + command = "cmd /c type nul > \"{{output}}\"" + } else { + command = "/usr/bin/touch {{output}}" + } + description = "STAMP {{output}}" + } + tool("copy") { + command = "cp -afd {{source}} {{output}}" + description = "COPY {{source}} {{output}}" + } + } +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/anavref.h b/vendor/xinlingyu_92_3061M/Project/chip/3061m/anavref.h new file mode 100644 index 0000000000000000000000000000000000000000..47f74aa42d46049028ad1e22bbe653d87b02f75a --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/anavref.h @@ -0,0 +1,92 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file anavref.h + * @author MCU Driver Team + * @brief anavref register mapping structure + */ + +/* Macro definitions */ +#ifndef McuMagicTag_ANAVREF_IP_H +#define McuMagicTag_ANAVREF_IP_H + +#include "baseinc.h" + +/** + * @brief Define the union VREF_CTRL_REG0 + */ +typedef union { + unsigned int reg; + struct { + unsigned int da_ref_enh : 1; /**< vref enable */ + unsigned int reserved0 : 31; + } BIT; +} volatile VREF_CTRL_REG0; + +/** + * @brief Define the union VREF_CTRL_REG1 + */ +typedef union { + unsigned int reg; + struct { + unsigned int da_ref_chop_enh : 1; /**< vref chopping enable */ + unsigned int reserved0 : 15; + unsigned int da_ref_temp_trim_enh : 1; /**< vref High-precision mode enable */ + unsigned int reserved1 : 15; + } BIT; +} volatile VREF_CTRL_REG1; + + +/** + * @brief Define the union VREF_TRIM_REG0 + */ +typedef union { + unsigned int reg; + struct { + unsigned int da_iref_trim : 8; /**< iref trim */ + unsigned int da_ref_vref_trim : 8; /**< IBIAS voltage trim */ + unsigned int da_ref_vbg_trim : 8; /**< vref voltage trim */ + unsigned int da_ref_buf_trim : 8; /**< vref buffer trim */ + } BIT; +} volatile VREF_TRIM_REG0; + +/** + * @brief Define the union VREF_TRIM_REG1 + */ +typedef union { + unsigned int reg; + struct { + unsigned int da_ref_temp_trim3 : 8; /**< Benchmark temperature drift trim information */ + unsigned int da_ref_temp_trim2 : 8; /**< Benchmark temperature drift trim information */ + unsigned int da_ref_temp_trim1 : 8; /**< Benchmark temperature drift trim information */ + unsigned int da_ref_temp_trim0 : 8; /**< Benchmark temperature drift trim information */ + } BIT; +} volatile VREF_TRIM_REG1; + +/** + * @brief Define the VREF_RegStruct + */ +typedef struct { + VREF_CTRL_REG0 VREF_CTRL0; /**< Offset address: 0x0000000U*/ + unsigned int space0[7]; + VREF_CTRL_REG1 VREF_CTRL1; /**< Offset address: 0x0000020U*/ + unsigned int space1[7]; + VREF_TRIM_REG0 VREF_TRIM0; /**< Offset address: 0x0000040U*/ + VREF_TRIM_REG1 VREF_TRIM1; /**< Offset address: 0x0000044U*/ +} volatile VREF_RegStruct; + +#endif /* McuMagicTag_ANAVREF_IP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/baseaddr.h b/vendor/xinlingyu_92_3061M/Project/chip/3061m/baseaddr.h new file mode 100644 index 0000000000000000000000000000000000000000..961f0725b38d3c52f57151c60cb2a644d9f368ce --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/baseaddr.h @@ -0,0 +1,202 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file baseaddr.h + * @author MCU Driver Team + * @brief Definition of MCU register baseaddress + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_BASEADDR_H +#define McuMagicTag_BASEADDR_H + +#define CRG_BASE (void *)0x10000000 +#define CMM_BASE (void *)0x10010000 +#define CFD_BASE (void *)0x10010000 +#define SYSCTRL0_BASE (void *)0x10100000 +#define SYSCTRL1_BASE (void *)0x10100000 +#define UART0_BASE (void *)0x14000000 +#define UART1_BASE (void *)0x14001000 +#define UART2_BASE (void *)0x14002000 +#define UART3_BASE (void *)0x14003000 + +#define I2C0_BASE (void *)0x14100000 +#define I2C1_BASE (void *)0x14101000 +#define SPI0_BASE (void *)0x14200000 +#define SPI1_BASE (void *)0x14201000 +#define TIMER0_BASE (void *)0x14300000 +#define TIMER1_BASE (void *)0x14301000 +#define TIMER2_BASE (void *)0x14302000 +#define TIMER3_BASE (void *)0x14303000 + +#define SYSTICK_BASE (void *)0x14380000 +#define WWDG_BASE (void *)0x14400000 +#define IWDG_BASE (void *)0x14401000 +#define GPIO0_BASE (void *)0x14500000 +#define GPIO1_BASE (void *)0x14501000 +#define GPIO2_BASE (void *)0x14502000 +#define GPIO3_BASE (void *)0x14503000 +#define GPIO4_BASE (void *)0x14504000 +#define GPIO5_BASE (void *)0x14505000 +#define CAN_BASE (void *)0x14600000 +#define GPT0_BASE (void *)0x14700000 +#define GPT1_BASE (void *)0x14701000 +#define GPT2_BASE (void *)0x14702000 +#define GPT3_BASE (void *)0x14703000 + +#define EFC_BASE (void *)0x14710000 +#define FOTP_BASE (void *)0x14720000 +#define HPM_BASE (void *)0x147D0000 +#define PMC_BASE (void *)0x147E0000 +#define IOCMG_BASE (void *)0x147F0000 +#define CRC_BASE (void *)0x14800000 +#define APT0_BASE (void *)0x14A00000 +#define APT1_BASE (void *)0x14A01000 +#define APT2_BASE (void *)0x14A02000 +#define APT3_BASE (void *)0x14A03000 + +#define CAPM0_BASE (void *)0x14B00000 +#define CAPM1_BASE (void *)0x14B01000 +#define CAPM2_BASE (void *)0x14B02000 +#define CAPM_COMM_BASE (void *)0x14B03000 + +#define QDM0_BASE (void *)0x14C00000 +#define QDM1_BASE (void *)0x14C01000 +#define ADC0_BASE (void *)0x18000000 +#define VREF_BASE (void *)0x18100000 +#define PGA0_BASE (void *)0x18200000 +#define PGA1_BASE (void *)0x18201000 +#define ACMP0_BASE (void *)0x18300000 +#define DAC0_BASE (void *)0x18400000 + +#define TSENSOR_BASE (void *)0x18500000 +#define ANA_CTRL_TOP_BASE (void *)0x18600000 + +#define DMA_BASE (void *)0x1C000000 +#define DMA_CHANNEL0_BASE (void *)0x1C000100 +#define DMA_CHANNEL1_BASE (void *)0x1C000120 +#define DMA_CHANNEL2_BASE (void *)0x1C000140 +#define DMA_CHANNEL3_BASE (void *)0x1C000160 +#define DMA_CHANNEL4_BASE (void *)0x1C000180 +#define DMA_CHANNEL5_BASE (void *)0x1C0001A0 + +#define CRG ((CRG_RegStruct *)CRG_BASE) +#define CMM ((CMM_RegStruct *)CMM_BASE) +#define CFD ((CFD_RegStruct *)CFD_BASE) +#define SYSCTRL0 ((SYSCTRL0_RegStruct *)SYSCTRL0_BASE) +#define SYSCTRL1 ((SYSCTRL1_RegStruct *)SYSCTRL1_BASE) +#define UART0 ((UART_RegStruct *)UART0_BASE) +#define UART1 ((UART_RegStruct *)UART1_BASE) +#define UART2 ((UART_RegStruct *)UART2_BASE) +#define UART3 ((UART_RegStruct *)UART3_BASE) +#define I2C0 ((I2C_RegStruct *)I2C0_BASE) +#define I2C1 ((I2C_RegStruct *)I2C1_BASE) +#define SPI0 ((SPI_RegStruct *)SPI0_BASE) +#define SPI1 ((SPI_RegStruct *)SPI1_BASE) +#define TIMER0 ((TIMER_RegStruct *)TIMER0_BASE) +#define TIMER1 ((TIMER_RegStruct *)TIMER1_BASE) +#define TIMER2 ((TIMER_RegStruct *)TIMER2_BASE) +#define TIMER3 ((TIMER_RegStruct *)TIMER3_BASE) +#define SYSTICK ((SYSTICK_RegStruct *)SYSTICK_BASE) +#define WWDG ((WWDG_RegStruct *)WWDG_BASE) +#define IWDG ((IWDG_RegStruct *)IWDG_BASE) +#define GPIO0 ((GPIO_RegStruct *)GPIO0_BASE) +#define GPIO1 ((GPIO_RegStruct *)GPIO1_BASE) +#define GPIO2 ((GPIO_RegStruct *)GPIO2_BASE) +#define GPIO3 ((GPIO_RegStruct *)GPIO3_BASE) +#define GPIO4 ((GPIO_RegStruct *)GPIO4_BASE) +#define GPIO5 ((GPIO_RegStruct *)GPIO5_BASE) + +#define CAN ((CAN_RegStruct *)CAN_BASE) +#define GPT0 ((GPT_RegStruct *)GPT0_BASE) +#define GPT1 ((GPT_RegStruct *)GPT1_BASE) +#define GPT2 ((GPT_RegStruct *)GPT2_BASE) +#define GPT3 ((GPT_RegStruct *)GPT3_BASE) +#define EFC ((EFC_RegStruct *)EFC_BASE) +#define FOTP ((FOTP_RegStruct *)FOTP_BASE) +#define HPM ((HPM_RegStruct *)HPM_BASE) +#define PMC ((PMC_RegStruct *)PMC_BASE) +#define CRC ((CRC_RegStruct *)CRC_BASE) +#define APT0 ((APT_RegStruct *)APT0_BASE) +#define APT1 ((APT_RegStruct *)APT1_BASE) +#define APT2 ((APT_RegStruct *)APT2_BASE) +#define APT3 ((APT_RegStruct *)APT3_BASE) +#define CAPM0 ((CAPM_RegStruct *)CAPM0_BASE) +#define CAPM1 ((CAPM_RegStruct *)CAPM1_BASE) +#define CAPM2 ((CAPM_RegStruct *)CAPM2_BASE) +#define CAPM_COMM ((CAPM_COMM_RegStruct *)CAPM_COMM_BASE) +#define QDM0 ((QDM_RegStruct *)QDM0_BASE) +#define QDM1 ((QDM_RegStruct *)QDM1_BASE) +#define ADC0 ((ADC_RegStruct *)ADC0_BASE) +#define PGA0 ((PGA_RegStruct *)PGA0_BASE) +#define PGA1 ((PGA_RegStruct *)PGA1_BASE) +#define DAC0 ((DAC_RegStruct *)DAC0_BASE) +#define TSENSOR ((TSENSOR_RegStruct *)TSENSOR_BASE) +#define ACMP0 ((ACMP_RegStruct *)ACMP0_BASE) +#define DMA ((DMA_RegStruct *)DMA_BASE) +#define DMA_CHANNEL0 ((DMA_ChannelRegStruct *)DMA_CHANNEL0_BASE) +#define DMA_CHANNEL1 ((DMA_ChannelRegStruct *)DMA_CHANNEL1_BASE) +#define DMA_CHANNEL2 ((DMA_ChannelRegStruct *)DMA_CHANNEL2_BASE) +#define DMA_CHANNEL3 ((DMA_ChannelRegStruct *)DMA_CHANNEL3_BASE) +#define DMA_CHANNEL4 ((DMA_ChannelRegStruct *)DMA_CHANNEL4_BASE) +#define DMA_CHANNEL5 ((DMA_ChannelRegStruct *)DMA_CHANNEL5_BASE) +#define IOCMG ((IOConfig_RegStruct*)IOCMG_BASE) +#define VREF ((VREF_RegStruct *)VREF_BASE) + +#define IsCRGInstance(instance) ((instance) == CRG) +#define IsCMMInstance(instance) ((instance) == CMM) +#define IsCFDInstance(instance) ((instance) == CFD) +#define IsSYSCTRLInstance(instance) (((instance) == SYSCTRL0) || ((instance) == SYSCTRL1)) +#define IsUARTInstance(instance) (((instance) == UART0) || ((instance) == UART1) || \ + ((instance) == UART2) || ((instance) == UART3)) +#define IsI2CInstance(instance) (((instance) == I2C0) || ((instance) == I2C1)) +#define IsSPIInstance(instance) (((instance) == SPI0) || ((instance) == SPI1)) +#define IsTIMERInstance(instance) (((instance) == TIMER0) || ((instance) == TIMER1) || \ + ((instance) == TIMER2) || ((instance) == TIMER3)) +#define IsSYSTICKInstance(instance) ((instance) == SYSTICK) +#define IsWWDGInstance(instance) ((instance) == WWDG) +#define IsIWDGInstance(instance) ((instance) == IWDG) +#define IsGPIOInstance(instance) (((instance) == GPIO0) || ((instance) == GPIO1) || \ + ((instance) == GPIO2) || ((instance) == GPIO3) || \ + ((instance) == GPIO4) || ((instance) == GPIO5)) +#define IsCANInstance(instance) ((instance) == CAN) +#define IsGPTInstance(instance) (((instance) == GPT0) || ((instance) == GPT1) || \ + ((instance) == GPT2) || ((instance) == GPT3)) +#define IsEFCInstance(instance) ((instance) == EFC) +#define IsFOTPInstance(instance) ((instance) == FOTP) +#define IsHPMInstance(instance) ((instance) == HPM) +#define IsPMCInstance(instance) ((instance) == PMC) +#define IsIOCMGInstance(instance) ((instance) == IOCMG) +#define IsCRCInstance(instance) ((instance) == CRC) +#define IsAPTInstance(instance) (((instance) == APT0) || ((instance) == APT1) || \ + ((instance) == APT2) || ((instance) == APT3)) +#define IsCAPMInstance(instance) (((instance) == CAPM0) || ((instance) == CAPM1) || ((instance) == CAPM2)) +#define IsCAPMCOMMInstance(instance) ((instance) == CAPM_COMM) +#define IsQDMInstance(instance) (((instance) == QDM0) || ((instance) == QDM1)) +#define IsADCInstance(instance) ((instance) == ADC0) +#define IsPGAInstance(instance) (((instance) == PGA0) || ((instance) == PGA1)) +#define IsDACInstance(instance) ((instance) == DAC0) +#define IsACMPInstance(instance) ((instance) == ACMP0) +#define IsDMAInstance(instance) ((instance) == DMA) +#define IsDMACHXInstance(instance) (((instance) == DMA_CHANNEL0) || ((instance) == DMA_CHANNEL1) || \ + ((instance) == DMA_CHANNEL2) || ((instance) == DMA_CHANNEL3) || \ + ((instance) == DMA_CHANNEL4) || ((instance) == DMA_CHANNEL5)) +#define SRAM_START 0x4000000 +#define SRAM_END 0x4007FFF +#define REGISTER_START 0x10000000 +#define REGISTER_END 0x1C000FFF +#endif /* McuMagicTag_BASEADDR_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinc.h b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinc.h new file mode 100644 index 0000000000000000000000000000000000000000..3994c66172cb80dd824661c20ebb376f48523a5a --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinc.h @@ -0,0 +1,37 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file chipinc.h + * @author MCU Driver Team + * @brief Contains chip-related header files. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_CHIPINC_H +#define McuMagicTag_CHIPINC_H + +/* Includes ------------------------------------------------------------------ */ +#include "feature.h" +#include "info.h" +#include "baseaddr.h" +#include "locktype.h" +#include "interrupt_ip.h" +#include "sysctrl.h" +#include "systick.h" +#include "ip_crg_common.h" + +#endif /* McuMagicTag_CHIPINC_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/anatrim/anatrim.c b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/anatrim/anatrim.c new file mode 100644 index 0000000000000000000000000000000000000000..00b3ca0bcddef2c30958862b5c7ffb8845abb93e --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/anatrim/anatrim.c @@ -0,0 +1,128 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file anatrim.c + * @author MCU Driver Team + * @brief Chip Init modlue. + * @details Calibration of analog module parameters. + */ +#include "anatrim.h" + +float g_tsensorGain = 0.00041f; + +/** + * @brief Calculate the conversion gain of the tsensor. + * @param data, original data. + * @retval None + */ +static void CalculateGain(unsigned int data) +{ + g_tsensorGain = ((float)(data) / 10000000.0f); +} + +/** + * @brief Obtains the chip ID. + * @param None + * @retval None + */ +static bool CHIP_GetInfo(void) +{ + FOTP_INFO_RGN0_NUMBER_4 emptyData; + FOTP_INFO_RGN0_NUMBER_2 idData; + FOTP_InfoGet(FOTP_INFO_RNG0, 4U, (void *)&emptyData.comData); /* 4 is the number of fotp_empty_flag in otp */ + FOTP_InfoGet(FOTP_INFO_RNG0, 2U, (void *)&idData.comData); /* 2 is the number of idData in otp */ + if (emptyData.REG.fotp_empty_flag != 0x5AA59669 || idData.REG.chip_id == 0xFFFFFFFF) { + return false; + } + return true; +} + +/** + * @brief Analog module trim. + * @param None + * @retval None + */ +static void CHIP_AnalogTrim(void) +{ + FOTP_INFO_RGN0_NUMBER_20 trimData20; + FOTP_InfoGet(FOTP_INFO_RNG0, 20U, (void *)&trimData20.comData); /* 20 is the number of trim data in otp */ + /* VREF */ + VREF->VREF_TRIM0.BIT.da_iref_trim = trimData20.REG.data0.da_iref_trim; + VREF->VREF_TRIM0.BIT.da_ref_vref_trim = trimData20.REG.data0.da_ref_vref_trim; + VREF->VREF_TRIM0.BIT.da_ref_vbg_trim = trimData20.REG.data0.da_ref_vbg_trim; + unsigned int value = trimData20.REG.data1.da_ref_temp_trim3; + value |= (trimData20.REG.data1.da_ref_temp_trim2 << 8U); /* Shift left by 8 bits */ + value |= (trimData20.REG.data1.da_ref_temp_trim1 << 16U); /* Shift left by 16 bits */ + value |= (trimData20.REG.data0.da_ref_temp_trim0 << 24U); /* Shift left by 24 bits */ + VREF->VREF_TRIM1.reg = value; + + FOTP_INFO_RGN0_NUMBER_21 trimData21; + FOTP_InfoGet(FOTP_INFO_RNG0, 21U, (void *)&trimData21.comData); /* 21 is the number of trim data in otp */ + /* ADC */ + ADC0->ADC_OEGE_TRIM.BIT.cfg_gain_cali_trim = trimData21.REG.data1.saradc_gain; + ADC0->ADC_OEGE_TRIM.BIT.cfg_ofst_cali_trim = trimData21.REG.data1.saradc_offset; + + /* TSENSOR */ + TSENSOR->TSENSOR_TRIM.reg = trimData20.REG.data1.da_ref_vptat_trim; + ADC0->ADC_TSENSOR_TRIM.BIT.cfg_tsensor_ofst_trim = trimData21.REG.data2.ts_offset; + CalculateGain(trimData21.REG.data3.ts_gain); + + /* PGA */ + PGA0->PGA_TRIM.BIT.da_pga_vos_trim = trimData21.REG.data0.da_pga0_vos_trim; + PGA1->PGA_TRIM.BIT.da_pga_vos_trim = trimData21.REG.data0.da_pga1_vos_trim; + + FOTP_INFO_RGN0_NUMBER_22 trimData22; + FOTP_InfoGet(FOTP_INFO_RNG0, 22U, (void *)&trimData22.comData); /* 22 is the number of trim data in otp */ + ADC0->ADC_PGA0_OEGE_TRIM0.BIT.cfg_pga0_gain_trim2 = trimData22.REG.data0.pga0_gain2; + ADC0->ADC_PGA0_OEGE_TRIM0.BIT.cfg_pga0_ofst_trim2 = trimData22.REG.data0.pga0_offset2; + ADC0->ADC_PGA0_OEGE_TRIM1.BIT.cfg_pga0_gain_trim4 = trimData22.REG.data1.pga0_gain4; + ADC0->ADC_PGA0_OEGE_TRIM1.BIT.cfg_pga0_ofst_trim4 = trimData22.REG.data1.pga0_offset4; + ADC0->ADC_PGA0_OEGE_TRIM2.BIT.cfg_pga0_gain_trim8 = trimData22.REG.data2.pga0_gain8; + ADC0->ADC_PGA0_OEGE_TRIM2.BIT.cfg_pga0_ofst_trim8 = trimData22.REG.data2.pga0_offset8; + ADC0->ADC_PGA0_OEGE_TRIM3.BIT.cfg_pga0_gain_trim16 = trimData22.REG.data3.pga0_gain16; + ADC0->ADC_PGA0_OEGE_TRIM3.BIT.cfg_pga0_ofst_trim16 = trimData22.REG.data3.pga0_offset16; + + FOTP_INFO_RGN0_NUMBER_23 trimData23; + FOTP_InfoGet(FOTP_INFO_RNG0, 23U, (void *)&trimData23.comData); /* 23 is the number of trim data in otp */ + ADC0->ADC_PGA1_OEGE_TRIM0.BIT.cfg_pga1_gain_trim2 = trimData23.REG.data0.pga1_gain2; + ADC0->ADC_PGA1_OEGE_TRIM0.BIT.cfg_pga1_ofst_trim2 = trimData23.REG.data0.pga1_offset2; + ADC0->ADC_PGA1_OEGE_TRIM1.BIT.cfg_pga1_gain_trim4 = trimData23.REG.data1.pga1_gain4; + ADC0->ADC_PGA1_OEGE_TRIM1.BIT.cfg_pga1_ofst_trim4 = trimData23.REG.data1.pga1_offset4; + ADC0->ADC_PGA1_OEGE_TRIM2.BIT.cfg_pga1_gain_trim8 = trimData23.REG.data2.pga1_gain8; + ADC0->ADC_PGA1_OEGE_TRIM2.BIT.cfg_pga1_ofst_trim8 = trimData23.REG.data2.pga1_offset8; + ADC0->ADC_PGA1_OEGE_TRIM3.BIT.cfg_pga1_gain_trim16 = trimData23.REG.data3.pga1_gain16; + ADC0->ADC_PGA1_OEGE_TRIM3.BIT.cfg_pga1_ofst_trim16 = trimData23.REG.data3.pga1_offset16; +} + +/** + * @brief Parameter calibration entry of the analog module. + * @param None + * @retval None + */ +void ANATRIM_Entry(void) +{ + if (CHIP_GetInfo() == false) { /* If the chip information is incorrect, calibration is not performed */ + return; + } + HAL_CRG_IpEnableSet((void *)ADC0, IP_CLK_ENABLE); /* Enable the clock for calibration */ + HAL_CRG_IpEnableSet((void *)PGA0, IP_CLK_ENABLE); + HAL_CRG_IpEnableSet((void *)PGA1, IP_CLK_ENABLE); + CHIP_AnalogTrim(); + HAL_CRG_IpEnableSet((void *)ADC0, IP_CLK_DISABLE); /* The clock is disabled after calibration */ + HAL_CRG_IpEnableSet((void *)PGA0, IP_CLK_DISABLE); + HAL_CRG_IpEnableSet((void *)PGA1, IP_CLK_DISABLE); +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/anatrim/anatrim.h b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/anatrim/anatrim.h new file mode 100644 index 0000000000000000000000000000000000000000..b5eef3e8294290a7314e145875b352219e730025 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/anatrim/anatrim.h @@ -0,0 +1,36 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file anatrim.h + * @author MCU Driver Team + * @brief Chip Init modlue. + * @details Calibration of analog module parameters. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_ANATRIM_H +#define McuMagicTag_ANATRIM_H +#include "baseinc.h" +#include "fotp_info_read.h" +#include "anavref.h" +#include "tsensor_ip.h" +#include "adc_ip.h" +#include "pga_ip.h" +#include "crg.h" +void ANATRIM_Entry(void); +extern float g_tsensorGain; +#endif /* McuMagicTag_ANATRIM_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/anavrefinit/anavrefinit.c b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/anavrefinit/anavrefinit.c new file mode 100644 index 0000000000000000000000000000000000000000..ee6a5ab86218ab939e746d045acd6fdca2f47249 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/anavrefinit/anavrefinit.c @@ -0,0 +1,39 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file anavrefinit.c + * @author MCU Driver Team + * @brief anavref init modlue. + * @details anavref initialization function during startup + */ + +#include "anavrefinit.h" + +/** + * @brief Set Crg Core clock select + * @param None + * @retval None + */ +void ANAVREF_Init(void) +{ + HAL_CRG_IpEnableSet(VREF_BASE, IP_CLK_ENABLE); + VREF->VREF_CTRL1.BIT.da_ref_temp_trim_enh = 0x1; + VREF->VREF_CTRL0.BIT.da_ref_enh = BASE_CFG_ENABLE; + BASE_FUNC_DELAY_US(200); /* delay 200us */ + VREF->VREF_CTRL1.BIT.da_ref_chop_enh = BASE_CFG_ENABLE; + BASE_FUNC_DELAY_US(40); /* delay 40us */ +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/anavrefinit/anavrefinit.h b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/anavrefinit/anavrefinit.h new file mode 100644 index 0000000000000000000000000000000000000000..56396fe15f156743be4fb513f098026cd0aff153 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/anavrefinit/anavrefinit.h @@ -0,0 +1,32 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file anavrefint.h + * @author MCU Driver Team + * @brief anavref init modlue. + * @details anavref initialization function during startup + */ + +#ifndef McuMagicTag_ANAVREF_H +#define McuMagicTag_ANAVREF_H + +#include "baseinc.h" +#include "crg.h" +#include "anavref.h" + +void ANAVREF_Init(void); +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/chipinit.c b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/chipinit.c new file mode 100644 index 0000000000000000000000000000000000000000..3cea5d59b1672bebf678748d5d06d8938d9b9a63 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/chipinit.c @@ -0,0 +1,69 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file chipint.c + * @author MCU Driver Team + * @brief Chip Init modlue. + * @details Declare a function that needs to be executed as soon as the C + * runtime environment is ready + */ +#include "chipinc.h" +#include "crginit.h" +#include "systickinit.h" +#include "flashinit.h" +#include "anavrefinit.h" +#include "anatrim.h" +#include "crg.h" +#include "interrupt.h" +#include "chipinit.h" + +/** + * @brief Chip Init Fail Process, deadloop if Chip Init fail + * @param None + * @retval None + */ +static inline void Chip_InitFail(void) +{ + while (1) { + ; + } +} + +/** + * @brief Chip Init + * @param None + * @retval None + */ +void Chip_Init(void) +{ + CRG_CoreClkSelect coreClkSelect; + /* Config CRG */ + if (CRG_Config(&coreClkSelect) != BASE_STATUS_OK) { + Chip_InitFail(); + } + + /* Config FLASH Clock */ + FLASH_ClockConfig(coreClkSelect); + SYSTICK_Init(); + /* Set CoreClock Select after FLASH Config Done */ + CRG_SetCoreClockSelect(coreClkSelect); + + IRQ_Init(); + ANAVREF_Init(); + ANATRIM_Entry(); + /* User Add Code Here */ +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/chipinit.h b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/chipinit.h new file mode 100644 index 0000000000000000000000000000000000000000..07a7fd202fdcd1f7c24d08df94636a289b0ec6a5 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/chipinit.h @@ -0,0 +1,31 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file chipinit.h + * @author MCU Driver Team + * @brief Chip Init modlue. + * @details Declare a function that needs to be executed as soon as the C + * runtime environment is ready + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_CHIPINIT_H +#define McuMagicTag_CHIPINIT_H + +void Chip_Init(void); + +#endif /* McuMagicTag_CHIPINIT_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/crginit/crginit.c b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/crginit/crginit.c new file mode 100644 index 0000000000000000000000000000000000000000..ab884e9ab70210a361bb042d3ef2ae2ba8f89699 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/crginit/crginit.c @@ -0,0 +1,65 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file crginit.c + * @author MCU Driver Team + * @brief crg init modlue. + * @details crg initialization function during startup + */ +#include "crginit.h" + +/** + * @brief CRG Config + * @param coreClkSelect OutPut core clock select value + * @retval None + */ +__weak BASE_StatusType CRG_Config(CRG_CoreClkSelect *coreClkSelect) +{ + BASE_FUNC_ASSERT_PARAM(coreClkSelect != NULL); + + CRG_Handle crg; + crg.baseAddress = CRG; + crg.pllRefClkSelect = CRG_PLL_REF_CLK_SELECT_HOSC; + crg.pllFbDiv = 0x30; /* PLL loop divider ratio = 0x30 */ + crg.pllPreDiv = CRG_PLL_PREDIV_4; + crg.pllPostDiv = CRG_PLL_POSTDIV_2; + crg.coreClkSelect = CRG_CORE_CLK_SELECT_PLL; + crg.handleEx.pllPostDiv2 = CRG_PLL_POSTDIV2_3; + crg.handleEx.clk1MSelect = CRG_1M_CLK_SELECT_HOSC; /* Set the 1MHz clock select. */ + crg.handleEx.clk1MDiv = 0x18; /* 0x18 : ensure that the 1MHz clock frequency is 1 MHz. */ + if (HAL_CRG_Init(&crg) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + *coreClkSelect = crg.coreClkSelect; + return BASE_STATUS_OK; +} + +/** + * @brief Set Crg Core clock select + * @param coreClkSelect Input core clock select value + * @retval None + */ +void CRG_SetCoreClockSelect(CRG_CoreClkSelect coreClkSelect) +{ + CRG_Handle crg; + crg.baseAddress = CRG; + crg.coreClkSelect = coreClkSelect; + if (crg.coreClkSelect == CRG_CORE_CLK_SELECT_TCXO) { /* If an external crystal oscillator is selected. */ + BASE_FUNC_DELAY_MS(10); /* 10: delay 10ms, wait clokc stable. */ + } + HAL_CRG_SetCoreClockSelect(&crg); +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/crginit/crginit.h b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/crginit/crginit.h new file mode 100644 index 0000000000000000000000000000000000000000..82ea33c91dc0b9d190af83367b166032243f709b --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/crginit/crginit.h @@ -0,0 +1,33 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file crginit.h + * @author MCU Driver Team + * @brief crg init modlue. + * @details crg initialization function during startup + */ + +#ifndef McuMagicTag_CRGINIT_H +#define McuMagicTag_CRGINIT_H + +#include "baseinc.h" +#include "crg.h" + +BASE_StatusType CRG_Config(CRG_CoreClkSelect *coreClkSelect); +void CRG_SetCoreClockSelect(CRG_CoreClkSelect coreClkSelect); + +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/flashinit/flashinit.c b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/flashinit/flashinit.c new file mode 100644 index 0000000000000000000000000000000000000000..38a9be2df4dbf98f3e54e0bfdc1e64eae99f79d7 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/flashinit/flashinit.c @@ -0,0 +1,111 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file flashinit.c + * @author MCU Driver Team + * @brief flash init modlue. + * @details flash initialization function during startup + */ +#include "chipinit.h" +#include "crg.h" +#include "flash_ip.h" +#include "flashinit.h" + +#define FLASH_BASE_FREQ (375 * 100 * 1000) /* 37.5MHz. */ +#define FLASH_MAX_DIV 4 + +/** + * @brief Get the Rounding up value + * @param frequence frequnce + * @param div Output Divison + * @retval None + */ +static void SetFlashDiv(unsigned int frequency, unsigned int *nreadDiv) +{ + unsigned int div; + unsigned int freq = frequency; + /* Get frequency divider of flash. */ + if (freq < FLASH_BASE_FREQ) { + freq = FLASH_BASE_FREQ; + } + /* Get the flash frequency division based on the frequency. */ + if ((freq % FLASH_BASE_FREQ) == 0) { + div = freq / FLASH_BASE_FREQ; + } else { + div = (freq / FLASH_BASE_FREQ) + 1; + } + /* Ensure the flash frequency division is valid. */ + if (div > FLASH_MAX_DIV) { + div = FLASH_MAX_DIV; + } + *nreadDiv = div; +} + +/** + * @brief Get the Rounding up value + * @param coreClkSelect Core Clock select + * @retval Frequency of Flash + */ +static unsigned int GetFlashFreq(CRG_CoreClkSelect coreClkSelect) +{ + unsigned int hclk; + /* Get frequency of flash. */ + switch (coreClkSelect) { + case CRG_CORE_CLK_SELECT_HOSC: + hclk = HOSC_FREQ; + break; + case CRG_CORE_CLK_SELECT_TCXO: + hclk = XTRAIL_FREQ; + break; + case CRG_CORE_CLK_SELECT_PLL: + hclk = HAL_CRG_GetPllFreq(); + break; + default: + hclk = LOSC_FREQ; + break; + } + return hclk; +} + +/** + * @brief Set flash clock frequence base on hclk + * @param coreClkSelect core clock select + * @retval None + */ +void FLASH_ClockConfig(CRG_CoreClkSelect coreClkSelect) +{ + EFC_RegStruct *efc = EFC; + EFLASH_CLK_CFG_REG cfg; + unsigned int hclk; + unsigned int nreadDiv; + + /* Step 1: Set nread_div */ + hclk = GetFlashFreq(coreClkSelect); + cfg.reg = efc->EFLASH_CLK_CFG.reg; + SetFlashDiv(hclk, &nreadDiv); + cfg.BIT.nread_div = nreadDiv; + cfg.BIT.busclk_sw_req = BASE_CFG_SET; + cfg.BIT.cur_read_vref_cal = BASE_CFG_SET; + + /* Step 2: Wait Busclk_sw_req */ + cfg.BIT.cur_read_vref_cal = BASE_CFG_SET; + cfg.BIT.busclk_sw_req = BASE_CFG_SET; + efc->EFLASH_CLK_CFG.reg = cfg.reg; + while (efc->EFLASH_CLK_CFG.BIT.busclk_sw_req == BASE_CFG_SET) { + ; + } +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/flashinit/flashinit.h b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/flashinit/flashinit.h new file mode 100644 index 0000000000000000000000000000000000000000..a5bd950870a3100cea7c2ea32efb3b47a3c8f61a --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/flashinit/flashinit.h @@ -0,0 +1,32 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file flashinit.h + * @author MCU Driver Team + * @brief flash init modlue. + * @details flash initialization function during startup + */ + +#ifndef McuMagicTag_FLASHINIT_H +#define McuMagicTag_FLASHINIT_H + +#include "baseinc.h" +#include "crg.h" + +void FLASH_ClockConfig(CRG_CoreClkSelect coreClkSelect); + +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/systickinit/systickinit.c b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/systickinit/systickinit.c new file mode 100644 index 0000000000000000000000000000000000000000..2d787dc26e51f8ed990ec0da05dbf270f7e60021 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/systickinit/systickinit.c @@ -0,0 +1,48 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file systickinit.c + * @author MCU Driver Team + * @brief systick init modlue. + * @details systick initialization function during startup + */ +#include "baseaddr.h" +#include "crg.h" +#include "systick.h" +#include "systickinit.h" + +/** + * @brief Init the systick + * @param None + * @retval None + */ +void SYSTICK_Init(void) +{ + SYSTICK->TIMER_CTRL.reg = 0; + SYSTICK->TIMER_CTRL.BIT.enable = 1; +} + +/** + * @brief Get the Systick frep(Hz) + * @param None + * @retval Clock frep of systick(Hz) + */ +unsigned int SYSTICK_GetCRGHZ(void) +{ + /* Get the Systick IP */ + return HAL_CRG_GetIpFreq(SYSTICK_BASE); +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/systickinit/systickinit.h b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/systickinit/systickinit.h new file mode 100644 index 0000000000000000000000000000000000000000..7a8710ad348912b685744dc32c061d5b19fb3e27 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/chipinit/systickinit/systickinit.h @@ -0,0 +1,29 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file systickinit.h + * @author MCU Driver Team + * @brief systick init modlue. + * @details systick initialization function during startup + */ + +#ifndef McuMagicTag_SYSTICKINIT_H +#define McuMagicTag_SYSTICKINIT_H + +void SYSTICK_Init(void); +unsigned int SYSTICK_GetCRGHZ(void); +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/codecopy.json b/vendor/xinlingyu_92_3061M/Project/chip/3061m/codecopy.json new file mode 100644 index 0000000000000000000000000000000000000000..e482c90187f535e3a8d11a0c9eb521ec48bf5220 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/codecopy.json @@ -0,0 +1,50 @@ +{ + "modules": [ + "application/user", + "build", + "chip/3061m", + "chip/target", + "drivers/debug", + "generatecode", + "middleware/control_library", + "middleware/hisilicon/loaderboot", + "middleware/hisilicon/nostask/arch", + "middleware/hisilicon/nostask/config", + "middleware/hisilicon/nostask/include", + "middleware/hisilicon/libboundscheck_v1.1.16", + "middleware/hisilicon/nostask/kernel", + "middleware/hisilicon/nostask/nos_api", + "middleware/thirdparty/sysroot", + "tools/uttest", + "bundle.json" + ], + + "ip_drive_file": ["acmp", "adc", "apt", "base", "can", "capm", "cmm", "crc", "crg", + "dac", "dma", "flash", "gpio", "gpt", "i2c", "pga", "pmc", "qdm", "spi", + "timer", "tsensor", "uart", "iwdg", "iocmg", "wwdg"], + "acmp" : ["common", "acmp_v1", "testcase_v1"], + "adc" : ["common", "adc_v1", "testcase_v1"], + "apt" : ["common", "apt_v1", "testcase_v1"], + "base" : ["common", "base_v0"], + "can" : ["common", "can_v0", "testcase_v0"], + "capm" : ["common", "capm_v1", "testcase_v1"], + "cmm" : ["common", "cmm_v1", "testcase_v1"], + "crc" : ["common", "crc_v1", "testcase_v1"], + "crg" : ["common", "crg_v1", "testcase_v1"], + "dac" : ["common", "dac_v1", "testcase_v1"], + "dma" : ["common", "dma_v1", "testcase_v1"], + "flash" : ["common", "flash_v1", "testcase_v1"], + "gpio" : ["common", "gpio_v0", "testcase_v0"], + "gpt" : ["common_v1", "gpt_v1", "testcase_v1"], + "i2c" : ["common", "i2c_v1", "testcase_v1"], + "pga" : ["common", "pga_v1", "testcase_v1"], + "pmc" : ["common", "pmc_v1", "testcase_v1"], + "qdm" : ["common", "qdm_v0", "testcase_v0"], + "spi" : ["common", "spi_v1", "testcase_v1"], + "timer" : ["common", "timer_v1", "testcase_v1"], + "tsensor" : ["common", "tsensor_v1", "testcase_v1"], + "uart" : ["common", "uart_v1", "testcase_v1"], + "iwdg" : ["common", "iwdg_v1", "testcase_v1"], + "iocmg" : ["common", "iocmg_v1", "testcase_v1"], + "wwdg" : ["common", "wwdg_v1", "testcase_v1"] +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/flash.lds b/vendor/xinlingyu_92_3061M/Project/chip/3061m/flash.lds new file mode 100644 index 0000000000000000000000000000000000000000..655283e94cee058b008b9fb37f74bf054cbb6ed5 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/flash.lds @@ -0,0 +1,202 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file flash.lds + * @author MCU Application Driver Team + * @brief RISCV flash link script + */ + +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +/* USER CODE BEGIN 0 */ +/* USER CODE 区域内代码不会被覆盖，区域外会被生成的默认代码覆盖（其余USER CODE 区域同理） */ +/* USER CODE END 0 */ + +SRAM_START = 0x4000000; +SRAM_END = 0x4000000 + 32K; + +RAM_CODE_START = 0x2000000; +RAM_CODE_SIZE = 0; + +RAM_RESERVE_DATA_START = SRAM_START + RAM_CODE_SIZE; +RAM_RESERVE_DATA_SIZE = 0; + +RAM_DIAGNOSE_BUF_START = RAM_RESERVE_DATA_START + RAM_RESERVE_DATA_SIZE; +RAM_DIAGNOSE_BUF_SIZE = 0x20; + +STACK_SRAM_BOUND_SIZE = 0x10; + +RAM_START = RAM_RESERVE_DATA_START + RAM_RESERVE_DATA_SIZE + RAM_DIAGNOSE_BUF_SIZE; +RAM_SIZE = 0x5000 - RAM_CODE_SIZE - RAM_RESERVE_DATA_SIZE - RAM_DIAGNOSE_BUF_SIZE - STACK_SRAM_BOUND_SIZE; +RAM_END = SRAM_END; + +STACK_SRAM_BOUND_START = RAM_START + RAM_SIZE; + +STACK_START = STACK_SRAM_BOUND_START + STACK_SRAM_BOUND_SIZE; + +NMI_STACK_SIZE = 1024; +STACK_SIZE = 0x3000 - NMI_STACK_SIZE; +INIT_STACK_SIZE = 1024; + +FLASH_START = 0x3000000; +FLASH_SIZE = 0x1fffc; + +MEMORY +{ + /* ram for code */ + RAM_CODE(xr) : ORIGIN = RAM_CODE_START, LENGTH = RAM_CODE_SIZE + + /* ram for reserved data */ + RAM_RESERVE_DATA(rw) : ORIGIN = RAM_RESERVE_DATA_START, LENGTH = RAM_RESERVE_DATA_SIZE + + /* ram for diagnose buf */ + RAM_DIAGNOSE_BUF(rw) : ORIGIN = RAM_DIAGNOSE_BUF_START, LENGTH = RAM_DIAGNOSE_BUF_SIZE + + /* ram for common bss and data */ + RAM_DATA(xrw) : ORIGIN = RAM_START, LENGTH = RAM_SIZE + + /* ram for common bss and data */ + STACK_SRAM_BOUND(xrw) : ORIGIN = STACK_SRAM_BOUND_START, LENGTH = STACK_SRAM_BOUND_SIZE + + /* ram for stack */ + RAM_STACK(xrw) : ORIGIN = STACK_START, LENGTH = STACK_SIZE + NMI_STACK_SIZE + + /*magic number */ + FLASH_MAGIC(rw) : ORIGIN = FLASH_START, LENGTH = 4 + + /* ram for target */ + FLASH_CODE(rx) : ORIGIN = FLASH_START + 4, LENGTH = FLASH_SIZE + +/* USER CODE BEGIN 1 */ +/* USER CODE 区域内代码不会被覆盖，区域外会被生成的默认代码覆盖（其余USER CODE 区域同理） */ +/* USER CODE END 1 */ +} + +SECTIONS +{ + /* The startup code goes first into FLASH */ + .data.magic : ALIGN(4) + { + KEEP(*(.data.magic)) + } > FLASH_MAGIC + + /* The startup code goes first into FLASH_CODE */ + .text.entry : ALIGN(4) + { + KEEP(*(.text.entry)) + } > FLASH_CODE + + /* Stack in SRAM at Highest addresses */ + .stacks (NOLOAD) : + { + . = ALIGN(4); + __SYSTEM_STACK_BEGIN__ = ORIGIN(RAM_STACK); + KEEP(*(.stacks)) + __SYSTEM_STACK_END__ = ORIGIN(RAM_STACK) + STACK_SIZE; + . = ALIGN(0x20); + __INTERRUPT_STACK_BEGIN__ = __SYSTEM_STACK_END__; + . = ALIGN(0x20); + __NMI_STACK_BEGIN__ = __SYSTEM_STACK_END__; + __nmi_stack_bottom = .; + . += NMI_STACK_SIZE; + __nmi_stack_top = .; + } > RAM_STACK + __stack_top = __SYSTEM_STACK_END__; + __init_stack_top = __SYSTEM_STACK_BEGIN__ + INIT_STACK_SIZE; + __irq_stack_top = __SYSTEM_STACK_END__; + + .text.sram : ALIGN(4) + { + __sram_code_load_addr = LOADADDR(.text.sram); + __sram_code_start_addr = .; + *(.text.sram) + . = ALIGN(4); + __sram_code_end_addr = .; + } > RAM_CODE AT > FLASH_CODE + + .reserved.data : ALIGN(4) + { + __reserved_code_load_addr = LOADADDR(.reserved.data); + __reserved_code_start_addr = .; + *(.reserved.data*) + . = ALIGN(4); + __reserved_code_end_addr = .; + } > RAM_RESERVE_DATA AT > FLASH_CODE + + .text : ALIGN(4) + { + __start_addr = .; + *(.text*) + *(.ram.text*) + . = ALIGN(4); + __rodata_start = .; + *(.rodata*) + . = ALIGN(4); + __rodata_end = .; + *(.got*) + __text_end = .; + } > FLASH_CODE + + /* data section */ + .data : ALIGN(4) + { + __data_load = LOADADDR(.data); + __data_start = .; + *(.data*) + . = ALIGN(4); + __data_end = .; + } > RAM_DATA AT> FLASH_CODE + __data_size = __data_end - __data_start; + + .stackBound : ALIGN(4) + { + __stack_sram_bound_data_load = LOADADDR(.stackBound); + __stack_sram_bound_data_start = .; + *(STACK_SRAM_BOUND) + . = ALIGN(4); + __stack_sram_bound_data_end = .; + } > STACK_SRAM_BOUND AT> FLASH_CODE + + .checkSum (NOLOAD) : ALIGN(4) + { + __checksum_addr = .; + *(CHECKSUM) + __checksum_end = .; + } > FLASH_CODE + + /* bss section */ + .bss (NOLOAD) : ALIGN(4) + { + __bss_begin__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM_DATA + __bss_size__ = __bss_end__ - __bss_begin__; + __global_pointer$ = __data_start + ((__data_size + __bss_size__) / 2); + + .ramBuf (NOLOAD) : ALIGN(4) + { + *(RAM_DIAGNOSE_BUF) + } > RAM_DIAGNOSE_BUF + +/* USER CODE BEGIN 2 */ +/* USER CODE 区域内代码不会被覆盖，区域外会被生成的默认代码覆盖（其余USER CODE 区域同理） */ +/* USER CODE END 2 */ +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/fotp/fotp.h b/vendor/xinlingyu_92_3061M/Project/chip/3061m/fotp/fotp.h new file mode 100644 index 0000000000000000000000000000000000000000..10f4979fe62f28c5c4b8c5c212fb3b16c0c66dd8 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/fotp/fotp.h @@ -0,0 +1,499 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file fotp.h + * @author MCU Driver Team + * @brief This file provides firmware functions to manage the following + * functionalities of the system control register. + * + Register Struct of FOTP RNG0 and FOTP RNG1 + */ +#ifndef McuMagicTag_FOTP_H +#define McuMagicTag_FOTP_H + +#define FOTP_INFO_REG_MAX_ID 25 /* Max index of fotp info rng 0 and rng 1 */ + +typedef enum { + FOTP_INFO_RNG0, + FOTP_INFO_RNG1, + FOTP_INFO_MAXTYPE, +} FOTP_InfoRngType; + +typedef struct { + unsigned int data[4]; +} FOTP_CommonData; + +/* + * FOTP INFO RNG0 + */ +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int DIEID_STD_VER : 3; + unsigned int MR_FLAG : 1; + unsigned int LOTID0 : 6; + unsigned int LOTID1 : 6; + unsigned int LOTID2 : 6; + unsigned int LOTID3 : 6; + unsigned int LOTID4 : 4; + } data0; + struct { + unsigned int LOTID4 : 2; + unsigned int LOTID5 : 6; + unsigned int WAFERID : 5; + unsigned int DIEX : 8; + unsigned int DIEY : 8; + unsigned int PASSFLAG_RT_CP : 1; + unsigned int reserved : 2; + } data1; + unsigned int reserved[2]; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_0; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int YEAR : 6; + unsigned int MON : 4; + unsigned int DAY : 5; + unsigned int HOUR : 5; + unsigned int MIN : 6; + unsigned int SEC : 6; + } data0; + struct { + unsigned int LOSC_CTRIM : 8; + unsigned int HOSC_CTRM : 9; + unsigned int PMU_BG_TRIM : 5; + unsigned int PMU_CLDO_TRIM : 5; + unsigned int reserved : 5; + } data1; + unsigned int reserved[2]; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_1; + +typedef union { + FOTP_CommonData comData; + struct { + unsigned int chip_id; + unsigned int reserved; + struct { + unsigned int version_id : 8; + unsigned int reserved : 24; + } data2; + unsigned int customer_id; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_2; + +typedef union { + FOTP_CommonData comData; + struct { + unsigned int fotp_empty_flag; + unsigned int reserved[3]; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_4; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int info_rgn0_unlock : 8; + unsigned int reserved : 24; + } data0; + unsigned int reserved0; + struct { + unsigned int info_rgn2_unlock : 8; + unsigned int reserved : 24; + } data2; + unsigned int reserved1; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_5; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int bootrom_debug_enable : 8; + unsigned int reserved : 24; + } data0; + struct { + unsigned int bootrom_hide_disable : 1; + unsigned int reserved : 31; + } data1; + struct { + unsigned int ef_bist_intf_enable : 1; + unsigned int reserved : 31; + } data2; + struct { + unsigned int dft_jtag_enable : 1; + unsigned int reserved : 31; + } data3; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_6; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int cpu_fpu_enable : 1; + unsigned int reserved0 : 7; + unsigned int sysram_size_cfg : 3; + unsigned int reserved1 : 5; + unsigned int eflash_size_cfg : 10; + unsigned int reserved2 : 5; + unsigned int cpu_maxfreq_cfg : 1; + } data0; + unsigned int reserved[3]; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_7; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int adc0_enable : 1; + unsigned int dac0_enable : 1; + unsigned int pga0_enable : 1; + unsigned int pga1_enable : 1; + unsigned int acmp0_enable : 1; + unsigned int reserved : 27; + } data0; + unsigned int reserved[3]; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_8; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int apt0_enable : 1; + unsigned int apt1_enable : 1; + unsigned int apt2_enable : 1; + unsigned int apt3_enable : 1; + unsigned int reserved0 : 12; + unsigned int can_enable : 1; + unsigned int reserved1 : 15; + } data0; + unsigned int reserved[3]; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_9; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int IDDQ_DVDD : 8; + unsigned int IDDQ_AVDD : 8; + unsigned int reserved : 16; + } data0; + unsigned int reserved[3]; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_10; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int hpm_core : 16; + unsigned int reserved : 16; + } data0; + unsigned int reserved[3]; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_11; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int PASSFLAG_CP_RT : 1; + unsigned int reserved : 31; + } data0; + unsigned int reserved[3]; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_13; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int PASSFLAG_FT_HT : 1; + unsigned int reserved : 31; + } data0; + unsigned int reserved[3]; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_16; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int DVS_FLOW_FLAG : 1; + unsigned int DVS_PASS_FLAG : 1; + unsigned int reserved : 30; + } data0; + unsigned int reserved[3]; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_17; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int FAILFLAG_ALL : 2; + unsigned int reserved : 30; + } data0; + unsigned int reserved[3]; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_18; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int PASSFLAG_FT_RT : 1; + unsigned int reserved : 31; + } data0; + unsigned int reserved[3]; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_19; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int da_ref_vbg_trim : 8; + unsigned int da_ref_vref_trim : 8; + unsigned int da_iref_trim : 8; + unsigned int da_ref_temp_trim0 : 8; + } data0; + struct { + unsigned int da_ref_temp_trim1 : 8; + unsigned int da_ref_temp_trim2 : 8; + unsigned int da_ref_temp_trim3 : 8; + unsigned int da_ref_vptat_trim : 8; + } data1; + struct { + unsigned int da_ref_buf_trim : 8; + unsigned int da_dac_trim : 8; + unsigned int da_acmp_trim : 8; + unsigned int da_sar_trim0 : 8; + } data2; + struct { + unsigned int da_sar_trim1 : 8; + unsigned int da_ana_top_trim0 : 8; + unsigned int da_ana_top_trim1 : 8; + unsigned int reserved : 8; + } data3; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_20; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int da_pga0_vos_trim : 9; + unsigned int reserved : 7; + unsigned int da_pga1_vos_trim : 9; + unsigned int reserved1 : 7; + } data0; + struct { + unsigned int saradc_gain : 13; + unsigned int reserved : 3; + unsigned int saradc_offset : 12; + unsigned int reserved1 : 4; + } data1; + struct { + unsigned int ts_offset : 12; + unsigned int reserved : 4; + unsigned int dac_gain : 11; + unsigned int reserved1 : 5; + } data2; + struct { + unsigned int dac_offset : 9; + unsigned int ts_gain : 23; + } data3; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_21; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int pga0_gain2 : 13; + unsigned int reserved : 3; + unsigned int pga0_offset2 : 12; + unsigned int reserved1 : 4; + } data0; + struct { + unsigned int pga0_gain4 : 13; + unsigned int reserved : 3; + unsigned int pga0_offset4 : 12; + unsigned int reserved1 : 4; + } data1; + struct { + unsigned int pga0_gain8 : 13; + unsigned int reserved : 3; + unsigned int pga0_offset8 : 12; + unsigned int reserved1 : 4; + } data2; + struct { + unsigned int pga0_gain16 : 13; + unsigned int reserved : 3; + unsigned int pga0_offset16 : 12; + unsigned int reserved1 : 4; + } data3; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_22; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int pga1_gain2 : 13; + unsigned int reserved : 3; + unsigned int pga1_offset2 : 12; + unsigned int reserved1 : 4; + } data0; + struct { + unsigned int pga1_gain4 : 13; + unsigned int reserved : 3; + unsigned int pga1_offset4 : 12; + unsigned int reserved1 : 4; + } data1; + struct { + unsigned int pga1_gain8 : 13; + unsigned int reserved : 3; + unsigned int pga1_offset8 : 12; + unsigned int reserved1 : 4; + } data2; + struct { + unsigned int pga1_gain16 : 13; + unsigned int reserved : 3; + unsigned int pga1_offset16 : 12; + unsigned int reserved1 : 4; + } data3; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_23; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int adc_weight3_trim : 9; + unsigned int reserved : 7; + unsigned int adc_weight4_trim : 10; + unsigned int reserved1 : 6; + } data0; + struct { + unsigned int adc_weight5_trim : 11; + unsigned int reserved : 5; + unsigned int adc_weight6_trim : 12; + unsigned int reserved1 : 4; + } data1; + struct { + unsigned int adc_weight7_trim : 12; + unsigned int reserved : 4; + unsigned int adc_weight8_trim : 13; + unsigned int reserved1 : 3; + } data2; + struct { + unsigned int adc_weight9_trim : 14; + unsigned int reserved : 2; + unsigned int adc_weight10_trim : 15; + unsigned int reserved1 : 1; + } data3; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_24; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int adc_weight11_trim : 15; + unsigned int reserved : 1; + unsigned int adc_weight12_trim : 16; + } data0; + struct { + unsigned int adc_weight13_trim : 17; + unsigned int reserved : 15; + } data1; + struct { + unsigned int adc_weight14_trim : 18; + unsigned int reserved : 14; + } data2; + struct { + unsigned int adc_weight15_trim : 19; + unsigned int reserved : 13; + } data3; + } REG; +} volatile FOTP_INFO_RGN0_NUMBER_25; + +/* + * FOTP INFO RNG1 + */ +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int protection_level : 8; + unsigned int reserved : 24; + } data0; + unsigned int reserved[3]; + } REG; +} volatile FOTP_INFO_RGN1_NUMBER_0; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int uart0_enable : 1; + unsigned int uart1_enable : 1; + unsigned int uart2_enable : 1; + unsigned int uart3_enable : 1; + unsigned int reserved : 28; + } data0; + struct { + unsigned int func_jtag_enable : 8; + unsigned int sysram_parity_disable : 1; + unsigned int reserved : 23; + } data1; + struct { + unsigned int uart_boot_enable : 1; + unsigned int spi_boot_enable : 1; + unsigned int i2c_boot_enable : 1; + unsigned int can_boot_enable : 1; + unsigned int reserved : 28; + } data2; + struct { + unsigned int main_rgn0_size : 10; + unsigned int reserved : 22; + } data3; + } REG; +} volatile FOTP_INFO_RGN1_NUMBER_1; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int info_rgn1_unlock : 8; + unsigned int reserved : 24; + } data0; + unsigned int reserved[3]; + } REG; +} volatile FOTP_INFO_RGN1_NUMBER_2; + +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/fotp/fotp_info_read.c b/vendor/xinlingyu_92_3061M/Project/chip/3061m/fotp/fotp_info_read.c new file mode 100644 index 0000000000000000000000000000000000000000..0f46d5dd190ba4c29a4cfb4a4a8629f2a789c47c --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/fotp/fotp_info_read.c @@ -0,0 +1,106 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file fotp_info_read.c + * @author MCU Driver Team + * @brief This file provides firmware functions to manage the following + * functionalities of the fotp control register. + * + FOTP INFO Read API + */ +#include "chipinc.h" +#include "flash.h" +#include "fotp_info_read.h" +#define FOTP_INFO_RNG0_BASEADDR 0x800000 +#define FOTP_INFO_RNG1_BASEADDR 0x801000 +#define REG_WORDS_NUM 16 +#define FLASH_READ_128BIT 1 + +/** + * @brief Read Four words of FOTP. + * @param efc Flash control register base address + * @retval BASE_STATUS_ERROR fail. + * @retval BASE_STATUS_OK success. + */ +static unsigned int FOTP_CheckReadStatus(EFC_RegStruct *efc) +{ + /* Check for errors in the flash reading process. */ + if (efc->INT_RAW_STATUS.BIT.int_raw_err_illegal || + efc->INT_RAW_STATUS.BIT.int_raw_err_ecc_corr || + efc->INT_RAW_STATUS.BIT.int_raw_err_ecc_chk) { + efc->INT_CLEAR.BIT.int_clr_err_ecc_corr = BASE_CFG_SET; + efc->INT_CLEAR.BIT.int_clr_err_illegal = BASE_CFG_SET; + efc->INT_CLEAR.BIT.int_clr_err_ecc_chk = BASE_CFG_SET; + efc->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief Read Four words of FOTP. + * @param type FOTP Range Type + * @param index FOTP register index + * @param buf Buffer of read data + * @retval BASE_STATUS_ERROR fail. + * @retval BASE_STATUS_OK success. + */ +unsigned int FOTP_InfoGet(FOTP_InfoRngType type, unsigned int index, FOTP_CommonData *buf) +{ + EFC_RegStruct *p = EFC; + unsigned int addr; + + if (buf == NULL) { + return BASE_STATUS_ERROR; + } + + if ((type >= FOTP_INFO_MAXTYPE) || (index > FOTP_INFO_REG_MAX_ID)) { + return BASE_STATUS_ERROR; + } + + /* If there is a read command, return */ + if (p->EFLASH_CMD.BIT.cmd_start) { + return BASE_STATUS_ERROR; + } + + p->MAGIC_LOCK = FLASH_KEY_REGISTER_UNLOCK_VALUE; + + /* Configure the read command parameters and start the read command */ + addr = (type == FOTP_INFO_RNG0) ? FOTP_INFO_RNG0_BASEADDR : FOTP_INFO_RNG1_BASEADDR; + addr += index * REG_WORDS_NUM; + p->EFLASH_ADDR.BIT.cmd_addr = addr >> 2; /* Right shift 2 bit change to word */ + p->EFLASH_CMD.BIT.cmd_code = FLASH_OPERATION_READ; + p->EFLASH_CMD.BIT.cmd_read_size = FLASH_READ_128BIT; + p->EFLASH_CMD.BIT.cmd_start = BASE_CFG_SET; + + while (p->EFLASH_CMD.BIT.cmd_start) { + ; + } + while (p->EFLASH_CMD.BIT.exec_state) { + ; + } + /* read error, clear interrupt and return */ + if (FOTP_CheckReadStatus(p) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + /* Read data from FIFO to buffer */ + for (unsigned int i = 0; i < sizeof(buf->data) / sizeof(buf->data[0]); ++i) { + buf->data[i] = p->FLASH_RDATA; + } + p->INT_CLEAR.BIT.int_clr_finish = BASE_CFG_SET; + p->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; + return BASE_STATUS_OK; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/fotp/fotp_info_read.h b/vendor/xinlingyu_92_3061M/Project/chip/3061m/fotp/fotp_info_read.h new file mode 100644 index 0000000000000000000000000000000000000000..2a78077f1c8fd720903b3ca6ef8664c021598657 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/fotp/fotp_info_read.h @@ -0,0 +1,31 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file fotp_info_read.h + * @author MCU Driver Team + * @brief This file provides firmware functions to manage the following + * functionalities of the system control register. + * + FOTP Register Read API + */ +#ifndef McuMagicTag_FOTP_INFO_READ_H +#define McuMagicTag_FOTP_INFO_READ_H + +#include "fotp.h" + +unsigned int FOTP_InfoGet(FOTP_InfoRngType type, unsigned int index, FOTP_CommonData *buf); + +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/info.h b/vendor/xinlingyu_92_3061M/Project/chip/3061m/info.h new file mode 100644 index 0000000000000000000000000000000000000000..fde26d300289ff050fbb53b0e9a1422d9367f5a6 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/info.h @@ -0,0 +1,30 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file info.h + * @author MCU Driver Team + * @brief Defines chip attributes. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_INFO_H +#define McuMagicTag_INFO_H + +#define CHIP_DELAY_CYCLES_PER_LOOP (4) /**< CPU cycles. Known number of this CPU cycles required to execute the \ + BASE_FUNC_delay() loop. */ + +#endif /* McuMagicTag_INFO_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/interrupt_ip.h b/vendor/xinlingyu_92_3061M/Project/chip/3061m/interrupt_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..07bdf6b064c8b699db210798bec9f90103a14e60 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/interrupt_ip.h @@ -0,0 +1,183 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file interrupt_ip.h + * @author MCU Driver Team + * @brief interrupt module driver. + * This file define the interrupt number + */ + +#ifndef MCUMagicTag_INTERRUPT_IP_H +#define MCUMagicTag_INTERRUPT_IP_H + +/* Typedef definitions -------------------------------------------------------*/ +#define MSTATUS_MIE 0x00000008U /**< mie in mstatus */ +#define MSTATUS_MPIE 0x00000080U /**< mpie in mstatus */ +#define UINT32_CUT_MASK 0xFFFFFFFFU + +#define IRQ_PRIO_HIGHEST 15 /**< Highest priority of a hardware interrupt. */ +#define IRQ_PRIO_LOWEST 1 /**< Lowest priority of a hardware interrupt. */ + +/** + * @brief Count of system interrupt vector. + * The number of standard interrupts inside the CPU. The interrupt number + * is 0~25. The software interrupt nesting scheme cannot use standard + * interrupts, which means that external system integration will ensure + * that no standard interrupts will be triggered. + */ +#define IRQ_VECTOR_CNT 26 + +/** + * @brief Count of local interrupt vector 0 - 5, enabled by CSR mie 26 -31 bit. + */ +#define IRQ_MIE_VECTOR_CNT 6 + +/** + * @brief Count of IRQ controlled by CSR mie + */ +#define IRQ_MIE_TOTAL_CNT (IRQ_VECTOR_CNT + IRQ_MIE_VECTOR_CNT) +#define IRQ_LOCIEN1_OFFSET 64 +#define IRQ_LOCIEN2_OFFSET 96 +#define IRQ_LOCIEN3_OFFSET 128 + +/** + * @brief rv_custom_csr + * locipri0~15 are registers that control the priority of interrupts, + * and every 4 bits control the priority of an interrupt + */ +#define LOCIPRI0 0xBC0 +#define LOCIPRI1 0xBC1 +#define LOCIPRI2 0xBC2 +#define LOCIPRI3 0xBC3 +#define LOCIPRI4 0xBC4 +#define LOCIPRI5 0xBC5 +#define LOCIPRI6 0xBC6 +#define LOCIPRI7 0xBC7 +#define LOCIPRI8 0xBC8 +#define LOCIPRI9 0xBC9 +#define LOCIPRI10 0xBCA +#define LOCIPRI11 0xBCB +#define LOCIPRI12 0xBCC +#define LOCIPRI13 0xBCD +#define LOCIPRI14 0xBCE +#define LOCIPRI15 0xBCF + +#define LOCIPRI(x) LOCIPRI##x + +/** + * @brief locien0~3 are registers that control interrupt enable + */ +#define LOCIEN0 0xBE0 +#define LOCIEN1 0xBE1 +#define LOCIEN2 0xBE2 +#define LOCIEN3 0xBE3 + +/** + * @brief locipd0~3 are registers that control the interrupt flag bit. Each bit + * controls an interrupt. If the corresponding bit bit is 1, it means the + * corresponding interrupt is triggered. + */ +#define LOCIPD0 0xBE8 +#define LOCIPD1 0xBE9 +#define LOCIPD2 0xBEA +#define LOCIPD3 0xBEB + +/** + * @brief Locipclr is the register that clears the interrupt flag bit, and the + * corresponding interrupt number is assigned to the locipclr register, + * and the hardware will clear the corresponding interrupt flag bit, that + * is, the corresponding locipd bit is set + */ +#define LOCIPCLR 0xBF0 + +/** + * @brief The maximum number of interrupts supported, excluding 26 internal standard + * interrupts, up to 230 external non-standard interrupts can be supported + */ +#define IRQ_NUM 256 + +/* ---------- Interrupt Number Definition ----------------------------------- */ +typedef enum { + IRQ_SOFTWARE = 26, /* The first 0~25 interrupts are the internal standard interrupts of the CPU, + and the customizable external non-standard interrupts start from 26 */ + IRQ_UART3 = 27, + + IRQ_UART0 = 28, + IRQ_UART1 = 29, + IRQ_UART2 = 30, + IRQ_MTIMER = 31, + IRQ_TIMER0 = 32, + IRQ_TIMER1 = 33, + IRQ_TIMER2 = 34, + IRQ_TIMER3 = 35, + IRQ_GPT0_INT = 36, + IRQ_GPT0_PRD_INT = 37, + IRQ_GPT1_INT = 38, + IRQ_GPT1_PRD_INT = 39, + IRQ_WWDG = 40, + + IRQ_I2C0 = 42, + IRQ_I2C1 = 43, + IRQ_SPI0 = 44, + IRQ_SPI1 = 45, + IRQ_CAN = 46, + + IRQ_APT0_EVT = 48, + IRQ_APT0_TMR = 49, + IRQ_APT1_EVT = 50, + IRQ_APT1_TMR = 51, + IRQ_APT2_EVT = 52, + IRQ_APT2_TMR = 53, + IRQ_APT3_EVT = 54, + IRQ_APT3_TMR = 55, + + IRQ_CMM = 68, + IRQ_CFD = 68, + IRQ_CAPM0 = 70, + IRQ_CAPM1 = 71, + IRQ_CAPM2 = 72, + IRQ_QDM0 = 73, + IRQ_QDM1 = 74, + IRQ_DMA_TC = 77, + IRQ_DMA_ERR = 78, + IRQ_SYSRAM_PARITY_ERR = 79, + IRQ_EFC = 81, + IRQ_EFC_ERR = 82, + IRQ_ACMP_INT = 84, + IRQ_PVD = 85, + IRQ_GPT2_INT = 86, + IRQ_GPT2_PRD_INT = 87, + IRQ_GPT3_INT = 88, + IRQ_GPT3_PRD_INT = 89, + IRQ_ADC0_EVENT = 91, + IRQ_ADC0_ERR = 92, + IRQ_ADC0_INT0 = 93, + IRQ_ADC0_INT1 = 94, + IRQ_ADC0_INT2 = 95, + IRQ_ADC0_INT3 = 96, + + IRQ_GPIO0 = 109, + IRQ_GPIO1 = 110, + IRQ_GPIO2 = 111, + IRQ_GPIO3 = 112, + IRQ_GPIO4 = 113, + IRQ_GPIO5 = 114, + + IRQ_MAX, /**< The maximum number of interrupts currently supported */ +} IRQ_ID; + +#endif /* MCUMagicTag_INTERRUPT_IP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/ioconfig.h b/vendor/xinlingyu_92_3061M/Project/chip/3061m/ioconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..7e5a9eaf06898dfe94087117a58b372c9bfdeca1 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/ioconfig.h @@ -0,0 +1,126 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file ioconfig.h + * @author MCU Driver Team + * @brief ioconfig module driver + * @details This file provides IOConfig register mapping structure. + */ + +/* Macro definitions */ +#ifndef McuMagicTag_IOCONFIG_H +#define McuMagicTag_IOCONFIG_H + +typedef union { + unsigned int reg; + struct { + unsigned int func : 4; /**< IO function selection. */ + unsigned int ds : 2; /**< Pin drive capability selection. */ + unsigned int reserved0 : 1; + unsigned int pd : 1; /**< Pin pull down control. */ + unsigned int pu : 1; /**< Pin pull up control. */ + unsigned int sr : 1; /**< Electrical level shift speed control. */ + unsigned int se : 1; /**< Schmidt input control. */ + unsigned int reserved1 : 21; + } BIT; +} volatile IOCMG_REG; + +typedef struct { + IOCMG_REG IOCFG_GPIO0_2; /**< Pin GPIO0_2 IO Config Register, offset address:0x000000U */ + unsigned char space0[12]; + IOCMG_REG IOCFG_GPIO5_0; /**< Pin GPIO5_0 IO Config Register, offset address:0x000010U */ + unsigned char space1[4]; +#ifdef CHIP_3061MNPICA /* Only CHIP_3061MNPICA is supported. */ + IOCMG_REG IOCFG_GPIO3_3; /**< Pin GPIO3_3 IO Config Register, offset address:0x000018U */ +#else + unsigned char space2[4]; +#endif +#ifdef CHIP_3061MNPICA /* Only CHIP_3061MNPICA is supported. */ + IOCMG_REG IOCFG_GPIO2_4; /**< Pin GPIO2_4 IO Config Register, offset address:0x00001CU */ +#else + unsigned char space3[4]; +#endif + unsigned char space4[224]; + IOCMG_REG IOCFG_GPIO0_7; /**< Pin GPIO0_7 IO Config Register, offset address:0x000100U */ +#ifdef CHIP_3061MNPICA /* Only CHIP_3061MNPICA is supported. */ + IOCMG_REG IOCFG_GPIO5_1; /**< Pin GPIO5_1 IO Config Register, offset address:0x000104U */ +#else + unsigned char space5[4]; +#endif + IOCMG_REG IOCFG_GPIO2_7; /**< Pin GPIO2_7 IO Config Register, offset address:0x000108U */ + IOCMG_REG IOCFG_GPIO2_6; /**< Pin GPIO2_6 IO Config Register, offset address:0x00010CU */ + IOCMG_REG IOCFG_GPIO2_5; /**< Pin GPIO2_5 IO Config Register, offset address:0x000110U */ +#ifdef CHIP_3061MNPICA /* Only CHIP_3061MNPICA is supported. */ + IOCMG_REG IOCFG_GPIO5_2; /**< Pin GPIO5_2 IO Config Register, offset address:0x000114U */ +#else + unsigned char space6[4]; +#endif + IOCMG_REG IOCFG_GPIO3_7; /**< Pin GPIO3_7 IO Config Register, offset address:0x000118U */ + IOCMG_REG IOCFG_GPIO3_6; /**< Pin GPIO3_6 IO Config Register, offset address:0x00011CU */ + IOCMG_REG IOCFG_GPIO3_5; /**< Pin GPIO3_5 IO Config Register, offset address:0x000120U */ +#ifdef CHIP_3061MNPICA /* Only CHIP_3061MNPICA is supported. */ + IOCMG_REG IOCFG_GPIO5_3; /**< Pin GPIO5_3 IO Config Register, offset address:0x000124U */ +#else + unsigned char space7[4]; +#endif + IOCMG_REG IOCFG_GPIO1_5; /**< Pin GPIO1_5 IO Config Register, offset address:0x000128U */ + IOCMG_REG IOCFG_GPIO1_6; /**< Pin GPIO1_6 IO Config Register, offset address:0x00012CU */ + IOCMG_REG IOCFG_GPIO1_7; /**< Pin GPIO1_7 IO Config Register, offset address:0x000130U */ + IOCMG_REG IOCFG_GPIO4_7; /**< Pin GPIO4_7 IO Config Register, offset address:0x000134U */ +#ifdef CHIP_3061MNPICA /* Only CHIP_3061MNPICA is supported. */ + IOCMG_REG IOCFG_GPIO4_5; /**< Pin GPIO4_5 IO Config Register, offset address:0x000138U */ + IOCMG_REG IOCFG_GPIO4_6; /**< Pin GPIO4_6 IO Config Register, offset address:0x00013CU */ + IOCMG_REG IOCFG_GPIO1_3; /**< Pin GPIO1_3 IO Config Register, offset address:0x000140U */ + IOCMG_REG IOCFG_GPIO1_4; /**< Pin GPIO1_4 IO Config Register, offset address:0x000144U */ +#else + unsigned char space8[16]; +#endif + IOCMG_REG IOCFG_GPIO3_0; /**< Pin GPIO3_0 IO Config Register, offset address:0x000148U */ + IOCMG_REG IOCFG_GPIO3_1; /**< Pin GPIO3_1 IO Config Register, offset address:0x00014CU */ + IOCMG_REG IOCFG_GPIO3_2; /**< Pin GPIO3_2 IO Config Register, offset address:0x000150U */ + IOCMG_REG IOCFG_GPIO4_0; /**< Pin GPIO4_0 IO Config Register, offset address:0x000154U */ + IOCMG_REG IOCFG_EF_BIST_INTF; /**< Pin EF_BIST_INTF IO Config Register, offset address:0x000158U */ + IOCMG_REG IOCFG_GPIO4_1; /**< Pin GPIO4_1 IO Config Register, offset address:0x00015CU */ + IOCMG_REG IOCFG_GPIO4_2; /**< Pin GPIO4_2 IO Config Register, offset address:0x000160U */ +#ifdef CHIP_3061MNPICA /* Only CHIP_3061MNPICA is supported. */ + IOCMG_REG IOCFG_GPIO4_3; /**< Pin GPIO4_3 IO Config Register, offset address:0x000164U */ + IOCMG_REG IOCFG_GPIO1_0; /**< Pin GPIO1_0 IO Config Register, offset address:0x000168U */ + IOCMG_REG IOCFG_GPIO1_1; /**< Pin GPIO1_1 IO Config Register, offset address:0x00016CU */ + IOCMG_REG IOCFG_GPIO3_4; /**< Pin GPIO3_4 IO Config Register, offset address:0x000170U */ + IOCMG_REG IOCFG_GPIO4_4; /**< Pin GPIO4_4 IO Config Register, offset address:0x000174U */ +#else + unsigned char space9[20]; +#endif + IOCMG_REG IOCFG_GPIO2_0; /**< Pin GPIO2_0 IO Config Register, offset address:0x000178U */ + IOCMG_REG IOCFG_GPIO2_1; /**< Pin GPIO2_1 IO Config Register, offset address:0x00017CU */ +#ifdef CHIP_3061MNPICA /* Only CHIP_3061MNPICA is supported. */ + IOCMG_REG IOCFG_GPIO2_2; /**< Pin GPIO2_2 IO Config Register, offset address:0x000180U */ + IOCMG_REG IOCFG_GPIO2_3; /**< Pin GPIO2_3 IO Config Register, offset address:0x000184U */ +#else + unsigned char space10[8]; +#endif + IOCMG_REG IOCFG_GPIO0_0; /**< Pin GPIO0_0 IO Config Register, offset address:0x000188U */ + IOCMG_REG IOCFG_GPIO0_1; /**< Pin GPIO0_1 IO Config Register, offset address:0x00018CU */ + IOCMG_REG IOCFG_GPIO0_3; /**< Pin GPIO0_3 IO Config Register, offset address:0x000190U */ + IOCMG_REG IOCFG_GPIO0_4; /**< Pin GPIO0_4 IO Config Register, offset address:0x000194U */ + IOCMG_REG IOCFG_GPIO1_2; /**< Pin GPIO1_2 IO Config Register, offset address:0x000198U */ + unsigned char space11[4]; + IOCMG_REG IOCFG_GPIO0_5; /**< Pin GPIO0_5 IO Config Register, offset address:0x0001A0U */ + IOCMG_REG IOCFG_GPIO0_6; /**< Pin GPIO0_6 IO Config Register, offset address:0x0001A4U */ +} volatile IOConfig_RegStruct; + +#endif /* McuMagicTag_IOCONFIG_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/iomap/iomap.h b/vendor/xinlingyu_92_3061M/Project/chip/3061m/iomap/iomap.h new file mode 100644 index 0000000000000000000000000000000000000000..e9c6f92d91f5c166c77e9c1c229bb6da9b932e6b --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/iomap/iomap.h @@ -0,0 +1,320 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file iomap.h + * @author MCU Driver Team + * @brief Defines chip pin map and function mode. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_IOMAP_H +#define McuMagicTag_IOMAP_H + +/* get offset value of member in type struct */ +#define OFFSET_OF(type, member) (unsigned int)(&(((type *)0)->member)) + +#define IOCMG_PIN_MUX(regx, funcNum, regValueDefault) \ + (unsigned int)(((OFFSET_OF(IOConfig_RegStruct, regx) & 0x00000FFF) << 16) | \ + (((regValueDefault) & 0xFFFFFFF0) | (funcNum))) +/* pin function mode info ---------------------------------------------------- */ +#define GPIO0_7_AS_GPIO0_7 IOCMG_PIN_MUX(IOCFG_GPIO0_7, FUNC_MODE_0, 0x02b1) +#define GPIO0_7_AS_JTAG_TRSTN IOCMG_PIN_MUX(IOCFG_GPIO0_7, FUNC_MODE_1, 0x02b1) +#define GPIO0_7_AS_SPI0_CSN0 IOCMG_PIN_MUX(IOCFG_GPIO0_7, FUNC_MODE_2, 0x02b1) +#define GPIO0_7_AS_UART1_CTSN IOCMG_PIN_MUX(IOCFG_GPIO0_7, FUNC_MODE_3, 0x02b1) +#define GPIO0_7_AS_CAPM1_IN IOCMG_PIN_MUX(IOCFG_GPIO0_7, FUNC_MODE_4, 0x02b1) +#define GPIO0_7_AS_POE0 IOCMG_PIN_MUX(IOCFG_GPIO0_7, FUNC_MODE_5, 0x02b1) +#define GPIO0_7_AS_ACMP0_OUT IOCMG_PIN_MUX(IOCFG_GPIO0_7, FUNC_MODE_6, 0x02b1) +#define GPIO0_7_AS_ADC_AIN4 IOCMG_PIN_MUX(IOCFG_GPIO0_7, FUNC_MODE_12, 0x02b1) + +/* Only CHIP_3061MNPICA and CHIP_3061MNPIC8 is supported. */ +#if defined (CHIP_3061MNPICA) || defined (CHIP_3061MNPIC8) +#define GPIO5_1_AS_GPIO5_1 IOCMG_PIN_MUX(IOCFG_GPIO5_1, FUNC_MODE_0, 0x0230) +#define GPIO5_1_AS_ADC0_STATUS IOCMG_PIN_MUX(IOCFG_GPIO5_1, FUNC_MODE_5, 0x0230) +#define GPIO5_1_AS_ADC_EXT_TRIG3 IOCMG_PIN_MUX(IOCFG_GPIO5_1, FUNC_MODE_6, 0x0230) +#define GPIO5_1_AS_ADC_AIN5 IOCMG_PIN_MUX(IOCFG_GPIO5_1, FUNC_MODE_12, 0x0230) +#endif + +#define GPIO2_7_AS_GPIO2_7 IOCMG_PIN_MUX(IOCFG_GPIO2_7, FUNC_MODE_0, 0x0230) +#define GPIO2_7_AS_SPI0_CLK IOCMG_PIN_MUX(IOCFG_GPIO2_7, FUNC_MODE_2, 0x0230) +#define GPIO2_7_AS_UART1_RTSN IOCMG_PIN_MUX(IOCFG_GPIO2_7, FUNC_MODE_3, 0x0230) +#define GPIO2_7_AS_PGA0_OUT IOCMG_PIN_MUX(IOCFG_GPIO2_7, FUNC_MODE_13, 0x0230) + +#define GPIO2_6_AS_GPIO2_6 IOCMG_PIN_MUX(IOCFG_GPIO2_6, FUNC_MODE_0, 0x0230) +#define GPIO2_6_AS_SPI0_RXD IOCMG_PIN_MUX(IOCFG_GPIO2_6, FUNC_MODE_2, 0x0230) +#define GPIO2_6_AS_APT_EVTMP5 IOCMG_PIN_MUX(IOCFG_GPIO2_6, FUNC_MODE_6, 0x0230) +#define GPIO2_6_AS_ADC_AIN6 IOCMG_PIN_MUX(IOCFG_GPIO2_6, FUNC_MODE_12, 0x0230) +#define GPIO2_6_AS_PGA0_N0 IOCMG_PIN_MUX(IOCFG_GPIO2_6, FUNC_MODE_13, 0x0230) +#define GPIO2_6_AS_ACMP_N3 IOCMG_PIN_MUX(IOCFG_GPIO2_6, FUNC_MODE_14, 0x0230) + +#define GPIO2_5_AS_GPIO2_5 IOCMG_PIN_MUX(IOCFG_GPIO2_5, FUNC_MODE_0, 0x0230) +#define GPIO2_5_AS_SPI0_TXD IOCMG_PIN_MUX(IOCFG_GPIO2_5, FUNC_MODE_2, 0x0230) +#define GPIO2_5_AS_APT_EVTIO5 IOCMG_PIN_MUX(IOCFG_GPIO2_5, FUNC_MODE_6, 0x0230) +#define GPIO2_5_AS_ADC_AIN7 IOCMG_PIN_MUX(IOCFG_GPIO2_5, FUNC_MODE_12, 0x0230) +#define GPIO2_5_AS_PGA0_P0 IOCMG_PIN_MUX(IOCFG_GPIO2_5, FUNC_MODE_13, 0x0230) +#define GPIO2_5_AS_ACMP_P3 IOCMG_PIN_MUX(IOCFG_GPIO2_5, FUNC_MODE_14, 0x0230) + +/* Only CHIP_3061MNPICA and CHIP_3061MNPIC8 is supported. */ +#if defined (CHIP_3061MNPICA) || defined (CHIP_3061MNPIC8) +#define GPIO5_2_AS_GPIO5_2 IOCMG_PIN_MUX(IOCFG_GPIO5_2, FUNC_MODE_0, 0x0230) +#define GPIO5_2_AS_GPT2_PWM IOCMG_PIN_MUX(IOCFG_GPIO5_2, FUNC_MODE_1, 0x0230) +#define GPIO5_2_AS_ADC0_STATUS IOCMG_PIN_MUX(IOCFG_GPIO5_2, FUNC_MODE_5, 0x0230) +#define GPIO5_2_AS_ADC_EXT_TRIG2 IOCMG_PIN_MUX(IOCFG_GPIO5_2, FUNC_MODE_6, 0x0230) +#define GPIO5_2_AS_ADC_AIN8 IOCMG_PIN_MUX(IOCFG_GPIO5_2, FUNC_MODE_12, 0x0230) +#endif + +#define GPIO3_7_AS_GPIO3_7 IOCMG_PIN_MUX(IOCFG_GPIO3_7, FUNC_MODE_0, 0x0230) +#define GPIO3_7_AS_GPT3_PWM IOCMG_PIN_MUX(IOCFG_GPIO3_7, FUNC_MODE_1, 0x0230) +#define GPIO3_7_AS_SPI0_CSN1 IOCMG_PIN_MUX(IOCFG_GPIO3_7, FUNC_MODE_2, 0x0230) +#define GPIO3_7_AS_ACMP0_OUT IOCMG_PIN_MUX(IOCFG_GPIO3_7, FUNC_MODE_6, 0x0230) +#define GPIO3_7_AS_ADC_AIN9 IOCMG_PIN_MUX(IOCFG_GPIO3_7, FUNC_MODE_12, 0x0230) + +#define GPIO3_6_AS_GPIO3_6 IOCMG_PIN_MUX(IOCFG_GPIO3_6, FUNC_MODE_0, 0x0230) +#define GPIO3_6_AS_CAN_RX IOCMG_PIN_MUX(IOCFG_GPIO3_6, FUNC_MODE_1, 0x0230) +#define GPIO3_6_AS_ADC_AIN10 IOCMG_PIN_MUX(IOCFG_GPIO3_6, FUNC_MODE_12, 0x0230) +#define GPIO3_6_AS_ACMP_N4 IOCMG_PIN_MUX(IOCFG_GPIO3_6, FUNC_MODE_13, 0x0230) + +#define GPIO3_5_AS_GPIO3_5 IOCMG_PIN_MUX(IOCFG_GPIO3_5, FUNC_MODE_0, 0x0230) +#define GPIO3_5_AS_CAN_TX IOCMG_PIN_MUX(IOCFG_GPIO3_5, FUNC_MODE_1, 0x0230) +#define GPIO3_5_AS_ADC_EXT_TRIG0 IOCMG_PIN_MUX(IOCFG_GPIO3_5, FUNC_MODE_4, 0x0230) +#define GPIO3_5_AS_ADC_AIN11 IOCMG_PIN_MUX(IOCFG_GPIO3_5, FUNC_MODE_12, 0x0230) +#define GPIO3_5_AS_ACMP_P4 IOCMG_PIN_MUX(IOCFG_GPIO3_5, FUNC_MODE_13, 0x0230) + +/* Only CHIP_3061MNPICA and CHIP_3061MNPIC8 is supported. */ +#if defined (CHIP_3061MNPICA) || defined (CHIP_3061MNPIC8) +#define GPIO5_3_AS_GPIO5_3 IOCMG_PIN_MUX(IOCFG_GPIO5_3, FUNC_MODE_0, 0x0230) +#define GPIO5_3_AS_ADC0_STATUS IOCMG_PIN_MUX(IOCFG_GPIO5_3, FUNC_MODE_5, 0x0230) +#define GPIO5_3_AS_ADC_EXT_TRIG1 IOCMG_PIN_MUX(IOCFG_GPIO5_3, FUNC_MODE_6, 0x0230) +#define GPIO5_3_AS_ADC_AIN12 IOCMG_PIN_MUX(IOCFG_GPIO5_3, FUNC_MODE_12, 0x0230) +#endif + +#define GPIO1_5_AS_GPIO1_5 IOCMG_PIN_MUX(IOCFG_GPIO1_5, FUNC_MODE_0, 0x0230) +#define GPIO1_5_AS_SMB1_ALERTN IOCMG_PIN_MUX(IOCFG_GPIO1_5, FUNC_MODE_2, 0x0230) +#define GPIO1_5_AS_UART2_TXD IOCMG_PIN_MUX(IOCFG_GPIO1_5, FUNC_MODE_3, 0x0230) +#define GPIO1_5_AS_CAPM1_IN IOCMG_PIN_MUX(IOCFG_GPIO1_5, FUNC_MODE_4, 0x0230) +#define GPIO1_5_AS_ADC_AIN13 IOCMG_PIN_MUX(IOCFG_GPIO1_5, FUNC_MODE_12, 0x0230) +#define GPIO1_5_AS_PGA1_P0 IOCMG_PIN_MUX(IOCFG_GPIO1_5, FUNC_MODE_13, 0x0230) + +#define GPIO1_6_AS_GPIO1_6 IOCMG_PIN_MUX(IOCFG_GPIO1_6, FUNC_MODE_0, 0x0230) +#define GPIO1_6_AS_SMB1_SUSN IOCMG_PIN_MUX(IOCFG_GPIO1_6, FUNC_MODE_2, 0x0230) +#define GPIO1_6_AS_UART2_RXD IOCMG_PIN_MUX(IOCFG_GPIO1_6, FUNC_MODE_3, 0x0230) +#define GPIO1_6_AS_CAPM2_IN IOCMG_PIN_MUX(IOCFG_GPIO1_6, FUNC_MODE_4, 0x0230) +#define GPIO1_6_AS_ADC_AIN14 IOCMG_PIN_MUX(IOCFG_GPIO1_6, FUNC_MODE_12, 0x0230) +#define GPIO1_6_AS_PGA1_N0 IOCMG_PIN_MUX(IOCFG_GPIO1_6, FUNC_MODE_13, 0x0230) + +#define GPIO1_7_AS_GPIO1_7 IOCMG_PIN_MUX(IOCFG_GPIO1_7, FUNC_MODE_0, 0x0230) +#define GPIO1_7_AS_I2C1_SCL IOCMG_PIN_MUX(IOCFG_GPIO1_7, FUNC_MODE_2, 0x0230) +#define GPIO1_7_AS_UART2_CTSN IOCMG_PIN_MUX(IOCFG_GPIO1_7, FUNC_MODE_3, 0x0230) +#define GPIO1_7_AS_CAPM0_IN IOCMG_PIN_MUX(IOCFG_GPIO1_7, FUNC_MODE_4, 0x0230) +#define GPIO1_7_AS_APT_EVTMP6 IOCMG_PIN_MUX(IOCFG_GPIO1_7, FUNC_MODE_6, 0x0230) +#define GPIO1_7_AS_PGA1_OUT IOCMG_PIN_MUX(IOCFG_GPIO1_7, FUNC_MODE_13, 0x0230) + +#define GPIO4_7_AS_GPIO4_7 IOCMG_PIN_MUX(IOCFG_GPIO4_7, FUNC_MODE_0, 0x0230) +#define GPIO4_7_AS_POE1 IOCMG_PIN_MUX(IOCFG_GPIO4_7, FUNC_MODE_1, 0x0230) +#define GPIO4_7_AS_I2C1_SDA IOCMG_PIN_MUX(IOCFG_GPIO4_7, FUNC_MODE_2, 0x0230) +#define GPIO4_7_AS_UART2_RTSN IOCMG_PIN_MUX(IOCFG_GPIO4_7, FUNC_MODE_3, 0x0230) +#define GPIO4_7_AS_ADC0_STATUS IOCMG_PIN_MUX(IOCFG_GPIO4_7, FUNC_MODE_4, 0x0230) +#define GPIO4_7_AS_ADC_AIN15 IOCMG_PIN_MUX(IOCFG_GPIO4_7, FUNC_MODE_12, 0x0230) +#define GPIO4_7_AS_DAC_OUT IOCMG_PIN_MUX(IOCFG_GPIO4_7, FUNC_MODE_13, 0x0230) + +/* Only CHIP_3061MNPICA and CHIP_3061MNPIC8 is supported. */ +#if defined (CHIP_3061MNPICA) || defined (CHIP_3061MNPIC8) +#define GPIO4_5_AS_GPIO4_5 IOCMG_PIN_MUX(IOCFG_GPIO4_5, FUNC_MODE_0, 0x0230) +#define GPIO4_5_AS_I2C0_SCL IOCMG_PIN_MUX(IOCFG_GPIO4_5, FUNC_MODE_2, 0x0230) +#define GPIO4_5_AS_UART3_CTSN IOCMG_PIN_MUX(IOCFG_GPIO4_5, FUNC_MODE_3, 0x0230) +#define GPIO4_5_AS_SPI1_CSN0 IOCMG_PIN_MUX(IOCFG_GPIO4_5, FUNC_MODE_4, 0x0230) +#define GPIO4_5_AS_QDM0_A IOCMG_PIN_MUX(IOCFG_GPIO4_5, FUNC_MODE_5, 0x0230) + +#define GPIO4_6_AS_GPIO4_6 IOCMG_PIN_MUX(IOCFG_GPIO4_6, FUNC_MODE_0, 0x0220) +#define GPIO4_6_AS_I2C0_SDA IOCMG_PIN_MUX(IOCFG_GPIO4_6, FUNC_MODE_2, 0x0220) +#define GPIO4_6_AS_UART3_RTSN IOCMG_PIN_MUX(IOCFG_GPIO4_6, FUNC_MODE_3, 0x0220) +#define GPIO4_6_AS_SPI1_CLK IOCMG_PIN_MUX(IOCFG_GPIO4_6, FUNC_MODE_4, 0x0220) +#define GPIO4_6_AS_QDM0_B IOCMG_PIN_MUX(IOCFG_GPIO4_6, FUNC_MODE_5, 0x0220) + +#define GPIO1_3_AS_GPIO1_3 IOCMG_PIN_MUX(IOCFG_GPIO1_3, FUNC_MODE_0, 0x0230) +#define GPIO1_3_AS_CAN_RX IOCMG_PIN_MUX(IOCFG_GPIO1_3, FUNC_MODE_1, 0x0230) +#define GPIO1_3_AS_SMB0_ALERTN IOCMG_PIN_MUX(IOCFG_GPIO1_3, FUNC_MODE_2, 0x0230) +#define GPIO1_3_AS_UART3_TXD IOCMG_PIN_MUX(IOCFG_GPIO1_3, FUNC_MODE_3, 0x0230) +#define GPIO1_3_AS_SPI1_TXD IOCMG_PIN_MUX(IOCFG_GPIO1_3, FUNC_MODE_4, 0x0230) +#define GPIO1_3_AS_QDM0_INDEX IOCMG_PIN_MUX(IOCFG_GPIO1_3, FUNC_MODE_5, 0x0230) +#define GPIO1_3_AS_QDM0_SYNC IOCMG_PIN_MUX(IOCFG_GPIO1_3, FUNC_MODE_6, 0x0230) + +#define GPIO1_4_AS_GPIO1_4 IOCMG_PIN_MUX(IOCFG_GPIO1_4, FUNC_MODE_0, 0x0230) +#define GPIO1_4_AS_CAN_TX IOCMG_PIN_MUX(IOCFG_GPIO1_4, FUNC_MODE_1, 0x0230) +#define GPIO1_4_AS_SMB0_SUSN IOCMG_PIN_MUX(IOCFG_GPIO1_4, FUNC_MODE_2, 0x0230) +#define GPIO1_4_AS_UART3_RXD IOCMG_PIN_MUX(IOCFG_GPIO1_4, FUNC_MODE_3, 0x0230) +#define GPIO1_4_AS_SPI1_RXD IOCMG_PIN_MUX(IOCFG_GPIO1_4, FUNC_MODE_4, 0x0230) +#endif + +#define GPIO3_0_AS_GPIO3_0 IOCMG_PIN_MUX(IOCFG_GPIO3_0, FUNC_MODE_0, 0x0230) +#define GPIO3_0_AS_APT0_PWMA IOCMG_PIN_MUX(IOCFG_GPIO3_0, FUNC_MODE_1, 0x0230) +#define GPIO3_0_AS_SPI1_CSN1 IOCMG_PIN_MUX(IOCFG_GPIO3_0, FUNC_MODE_4, 0x0230) + +#define GPIO3_1_AS_GPIO3_1 IOCMG_PIN_MUX(IOCFG_GPIO3_1, FUNC_MODE_0, 0x0230) +#define GPIO3_1_AS_APT1_PWMA IOCMG_PIN_MUX(IOCFG_GPIO3_1, FUNC_MODE_1, 0x0230) +#define GPIO3_1_AS_I2C1_SCL IOCMG_PIN_MUX(IOCFG_GPIO3_1, FUNC_MODE_2, 0x0230) + +#define GPIO3_2_AS_GPIO3_2 IOCMG_PIN_MUX(IOCFG_GPIO3_2, FUNC_MODE_0, 0x0230) +#define GPIO3_2_AS_APT2_PWMA IOCMG_PIN_MUX(IOCFG_GPIO3_2, FUNC_MODE_1, 0x0230) +#define GPIO3_2_AS_I2C1_SDA IOCMG_PIN_MUX(IOCFG_GPIO3_2, FUNC_MODE_2, 0x0230) +#define GPIO3_2_AS_SPI1_CSN0 IOCMG_PIN_MUX(IOCFG_GPIO3_2, FUNC_MODE_4, 0x0230) + +/* Only CHIP_3061MNPICA and CHIP_3061MNPIC8 is supported. */ +#if defined (CHIP_3061MNPICA) || defined (CHIP_3061MNPIC8) +#define GPIO3_3_AS_GPIO3_3 IOCMG_PIN_MUX(IOCFG_GPIO3_3, FUNC_MODE_0, 0x0230) +#define GPIO3_3_AS_APT3_PWMA IOCMG_PIN_MUX(IOCFG_GPIO3_3, FUNC_MODE_1, 0x0230) +#define GPIO3_3_AS_POE2 IOCMG_PIN_MUX(IOCFG_GPIO3_3, FUNC_MODE_2, 0x0230) +#define GPIO3_3_AS_WAKEUP2 IOCMG_PIN_MUX(IOCFG_GPIO3_3, FUNC_MODE_6, 0x0230) +#endif + +#define GPIO4_0_AS_GPIO4_0 IOCMG_PIN_MUX(IOCFG_GPIO4_0, FUNC_MODE_0, 0x0230) +#define GPIO4_0_AS_APT0_PWMB IOCMG_PIN_MUX(IOCFG_GPIO4_0, FUNC_MODE_1, 0x0230) +#define GPIO4_0_AS_UART3_TXD IOCMG_PIN_MUX(IOCFG_GPIO4_0, FUNC_MODE_3, 0x0230) +#define GPIO4_0_AS_SPI1_CLK IOCMG_PIN_MUX(IOCFG_GPIO4_0, FUNC_MODE_4, 0x0230) + +#define GPIO4_1_AS_GPIO4_1 IOCMG_PIN_MUX(IOCFG_GPIO4_1, FUNC_MODE_0, 0x0230) +#define GPIO4_1_AS_APT1_PWMB IOCMG_PIN_MUX(IOCFG_GPIO4_1, FUNC_MODE_1, 0x0230) +#define GPIO4_1_AS_UART3_RXD IOCMG_PIN_MUX(IOCFG_GPIO4_1, FUNC_MODE_3, 0x0230) +#define GPIO4_1_AS_SPI1_RXD IOCMG_PIN_MUX(IOCFG_GPIO4_1, FUNC_MODE_4, 0x0230) + +#define GPIO4_2_AS_GPIO4_2 IOCMG_PIN_MUX(IOCFG_GPIO4_2, FUNC_MODE_0, 0x0230) +#define GPIO4_2_AS_APT2_PWMB IOCMG_PIN_MUX(IOCFG_GPIO4_2, FUNC_MODE_1, 0x0230) +#define GPIO4_2_AS_I2C0_SCL IOCMG_PIN_MUX(IOCFG_GPIO4_2, FUNC_MODE_2, 0x0230) +#define GPIO4_2_AS_SPI1_TXD IOCMG_PIN_MUX(IOCFG_GPIO4_2, FUNC_MODE_4, 0x0230) + +/* Only CHIP_3061MNPICA and CHIP_3061MNPIC8 is supported. */ +#if defined (CHIP_3061MNPICA) || defined (CHIP_3061MNPIC8) +#define GPIO4_3_AS_GPIO4_3 IOCMG_PIN_MUX(IOCFG_GPIO4_3, FUNC_MODE_0, 0x0230) +#define GPIO4_3_AS_APT3_PWMB IOCMG_PIN_MUX(IOCFG_GPIO4_3, FUNC_MODE_1, 0x0230) +#define GPIO4_3_AS_I2C0_SDA IOCMG_PIN_MUX(IOCFG_GPIO4_3, FUNC_MODE_2, 0x0230) +#define GPIO4_3_AS_SPI1_CSN1 IOCMG_PIN_MUX(IOCFG_GPIO4_3, FUNC_MODE_4, 0x0230) +#define GPIO4_3_AS_SPI0_CSN0 IOCMG_PIN_MUX(IOCFG_GPIO4_3, FUNC_MODE_5, 0x0230) + +#define GPIO1_0_AS_GPIO1_0 IOCMG_PIN_MUX(IOCFG_GPIO1_0, FUNC_MODE_0, 0x0230) +#define GPIO1_0_AS_APT0_PWMA IOCMG_PIN_MUX(IOCFG_GPIO1_0, FUNC_MODE_1, 0x0230) +#define GPIO1_0_AS_UART1_TXD IOCMG_PIN_MUX(IOCFG_GPIO1_0, FUNC_MODE_3, 0x0230) +#define GPIO1_0_AS_SPI0_CLK IOCMG_PIN_MUX(IOCFG_GPIO1_0, FUNC_MODE_5, 0x0230) + +#define GPIO1_1_AS_GPIO1_1 IOCMG_PIN_MUX(IOCFG_GPIO1_1, FUNC_MODE_0, 0x0230) +#define GPIO1_1_AS_APT1_PWMA IOCMG_PIN_MUX(IOCFG_GPIO1_1, FUNC_MODE_1, 0x0230) +#define GPIO1_1_AS_UART1_RXD IOCMG_PIN_MUX(IOCFG_GPIO1_1, FUNC_MODE_3, 0x0230) +#define GPIO1_1_AS_SPI0_RXD IOCMG_PIN_MUX(IOCFG_GPIO1_1, FUNC_MODE_5, 0x0230) + +#define GPIO3_4_AS_GPIO3_4 IOCMG_PIN_MUX(IOCFG_GPIO3_4, FUNC_MODE_0, 0x0230) +#define GPIO3_4_AS_APT2_PWMA IOCMG_PIN_MUX(IOCFG_GPIO3_4, FUNC_MODE_1, 0x0230) +#define GPIO3_4_AS_I2C1_SCL IOCMG_PIN_MUX(IOCFG_GPIO3_4, FUNC_MODE_2, 0x0230) +#define GPIO3_4_AS_UART1_CTSN IOCMG_PIN_MUX(IOCFG_GPIO3_4, FUNC_MODE_3, 0x0230) +#define GPIO3_4_AS_SPI0_TXD IOCMG_PIN_MUX(IOCFG_GPIO3_4, FUNC_MODE_5, 0x0230) + +#define GPIO4_4_AS_GPIO4_4 IOCMG_PIN_MUX(IOCFG_GPIO4_4, FUNC_MODE_0, 0x0230) +#define GPIO4_4_AS_APT3_PWMA IOCMG_PIN_MUX(IOCFG_GPIO4_4, FUNC_MODE_1, 0x0230) +#define GPIO4_4_AS_I2C1_SDA IOCMG_PIN_MUX(IOCFG_GPIO4_4, FUNC_MODE_2, 0x0230) +#define GPIO4_4_AS_UART1_RTSN IOCMG_PIN_MUX(IOCFG_GPIO4_4, FUNC_MODE_3, 0x0230) +#define GPIO4_4_AS_SPI0_CSN1 IOCMG_PIN_MUX(IOCFG_GPIO4_4, FUNC_MODE_5, 0x0230) +#endif + +#define GPIO2_0_AS_GPIO2_0 IOCMG_PIN_MUX(IOCFG_GPIO2_0, FUNC_MODE_0, 0x0230) +#define GPIO2_0_AS_I2C0_SCL IOCMG_PIN_MUX(IOCFG_GPIO2_0, FUNC_MODE_1, 0x0230) +#define GPIO2_0_AS_SMB1_ALERTN IOCMG_PIN_MUX(IOCFG_GPIO2_0, FUNC_MODE_2, 0x0230) +#define GPIO2_0_AS_UART3_TXD IOCMG_PIN_MUX(IOCFG_GPIO2_0, FUNC_MODE_3, 0x0230) +#define GPIO2_0_AS_CAPM2_IN IOCMG_PIN_MUX(IOCFG_GPIO2_0, FUNC_MODE_4, 0x0230) +#define GPIO2_0_AS_QDM1_A IOCMG_PIN_MUX(IOCFG_GPIO2_0, FUNC_MODE_5, 0x0230) +#define GPIO2_0_AS_APT_EVTMP4 IOCMG_PIN_MUX(IOCFG_GPIO2_0, FUNC_MODE_6, 0x0230) + +#define GPIO2_1_AS_GPIO2_1 IOCMG_PIN_MUX(IOCFG_GPIO2_1, FUNC_MODE_0, 0x0230) +#define GPIO2_1_AS_I2C0_SDA IOCMG_PIN_MUX(IOCFG_GPIO2_1, FUNC_MODE_1, 0x0230) +#define GPIO2_1_AS_SMB1_SUSN IOCMG_PIN_MUX(IOCFG_GPIO2_1, FUNC_MODE_2, 0x0230) +#define GPIO2_1_AS_UART3_RXD IOCMG_PIN_MUX(IOCFG_GPIO2_1, FUNC_MODE_3, 0x0230) +#define GPIO2_1_AS_CAPM1_IN IOCMG_PIN_MUX(IOCFG_GPIO2_1, FUNC_MODE_4, 0x0230) +#define GPIO2_1_AS_QDM1_B IOCMG_PIN_MUX(IOCFG_GPIO2_1, FUNC_MODE_5, 0x0230) +#define GPIO2_1_AS_APT_EVTIO4 IOCMG_PIN_MUX(IOCFG_GPIO2_1, FUNC_MODE_6, 0x0230) + +#define GPIO5_0_AS_GPIO5_0 IOCMG_PIN_MUX(IOCFG_GPIO5_0, FUNC_MODE_0, 0x0230) +#define GPIO5_0_AS_GPT2_PWM IOCMG_PIN_MUX(IOCFG_GPIO5_0, FUNC_MODE_1, 0x0230) +#define GPIO5_0_AS_QDM1_SYNC IOCMG_PIN_MUX(IOCFG_GPIO5_0, FUNC_MODE_3, 0x0230) +#define GPIO5_0_AS_CAPM0_IN IOCMG_PIN_MUX(IOCFG_GPIO5_0, FUNC_MODE_4, 0x0230) +#define GPIO5_0_AS_QDM1_INDEX IOCMG_PIN_MUX(IOCFG_GPIO5_0, FUNC_MODE_5, 0x0230) +#define GPIO5_0_AS_WAKEUP0 IOCMG_PIN_MUX(IOCFG_GPIO5_0, FUNC_MODE_6, 0x0230) + +/* Only CHIP_3061MNPICA and CHIP_3061MNPIC8 is supported. */ +#if defined (CHIP_3061MNPICA) || defined (CHIP_3061MNPIC8) +#define GPIO2_2_AS_GPIO2_2 IOCMG_PIN_MUX(IOCFG_GPIO2_2, FUNC_MODE_0, 0x0230) +#define GPIO2_2_AS_CAN_RX IOCMG_PIN_MUX(IOCFG_GPIO2_2, FUNC_MODE_1, 0x0230) +#define GPIO2_2_AS_UART0_TXD IOCMG_PIN_MUX(IOCFG_GPIO2_2, FUNC_MODE_2, 0x0230) +#define GPIO2_2_AS_UART2_TXD IOCMG_PIN_MUX(IOCFG_GPIO2_2, FUNC_MODE_3, 0x0230) +#define GPIO2_2_AS_CAPM2_IN IOCMG_PIN_MUX(IOCFG_GPIO2_2, FUNC_MODE_4, 0x0230) + +#define GPIO2_3_AS_GPIO2_3 IOCMG_PIN_MUX(IOCFG_GPIO2_3, FUNC_MODE_0, 0x0230) +#define GPIO2_3_AS_CAN_TX IOCMG_PIN_MUX(IOCFG_GPIO2_3, FUNC_MODE_1, 0x0230) +#define GPIO2_3_AS_UART0_RXD IOCMG_PIN_MUX(IOCFG_GPIO2_3, FUNC_MODE_2, 0x0230) +#define GPIO2_3_AS_UART2_RXD IOCMG_PIN_MUX(IOCFG_GPIO2_3, FUNC_MODE_3, 0x0230) +#define GPIO2_3_AS_CAPM1_IN IOCMG_PIN_MUX(IOCFG_GPIO2_3, FUNC_MODE_4, 0x0230) +#endif + +#define GPIO0_0_AS_GPIO0_0 IOCMG_PIN_MUX(IOCFG_GPIO0_0, FUNC_MODE_0, 0x02b1) +#define GPIO0_0_AS_JTAG_TCK IOCMG_PIN_MUX(IOCFG_GPIO0_0, FUNC_MODE_1, 0x02b1) +#define GPIO0_0_AS_UART0_CTSN IOCMG_PIN_MUX(IOCFG_GPIO0_0, FUNC_MODE_3, 0x02b1) +#define GPIO0_0_AS_UART2_CTSN IOCMG_PIN_MUX(IOCFG_GPIO0_0, FUNC_MODE_4, 0x02b1) + +#define GPIO0_1_AS_GPIO0_1 IOCMG_PIN_MUX(IOCFG_GPIO0_1, FUNC_MODE_0, 0x0311) +#define GPIO0_1_AS_JTAG_TMS IOCMG_PIN_MUX(IOCFG_GPIO0_1, FUNC_MODE_1, 0x0311) +#define GPIO0_1_AS_UART0_RTSN IOCMG_PIN_MUX(IOCFG_GPIO0_1, FUNC_MODE_3, 0x0311) +#define GPIO0_1_AS_UART2_RTSN IOCMG_PIN_MUX(IOCFG_GPIO0_1, FUNC_MODE_4, 0x0311) + +#define GPIO0_2_AS_GPIO0_2 IOCMG_PIN_MUX(IOCFG_GPIO0_2, FUNC_MODE_0, 0x0731) +#define GPIO0_2_AS_RESETN IOCMG_PIN_MUX(IOCFG_GPIO0_2, FUNC_MODE_1, 0x0731) +#define GPIO0_2_AS_SYS_RSTN_OUT IOCMG_PIN_MUX(IOCFG_GPIO0_2, FUNC_MODE_2, 0x0731) + +#define GPIO0_3_AS_GPIO0_3 IOCMG_PIN_MUX(IOCFG_GPIO0_3, FUNC_MODE_0, 0x0230) +#define GPIO0_3_AS_UART0_TXD IOCMG_PIN_MUX(IOCFG_GPIO0_3, FUNC_MODE_3, 0x0230) +#define GPIO0_3_AS_XTAL_OUT IOCMG_PIN_MUX(IOCFG_GPIO0_3, FUNC_MODE_12, 0x0230) + +#define GPIO0_4_AS_GPIO0_4 IOCMG_PIN_MUX(IOCFG_GPIO0_4, FUNC_MODE_0, 0x0230) +#define GPIO0_4_AS_GPT0_PWM IOCMG_PIN_MUX(IOCFG_GPIO0_4, FUNC_MODE_2, 0x0230) +#define GPIO0_4_AS_UART0_RXD IOCMG_PIN_MUX(IOCFG_GPIO0_4, FUNC_MODE_3, 0x0230) +#define GPIO0_4_AS_XTAL_IN IOCMG_PIN_MUX(IOCFG_GPIO0_4, FUNC_MODE_12, 0x0230) + +/* Only CHIP_3061MNPICA and CHIP_3061MNPIC8 is supported. */ +#if defined (CHIP_3061MNPICA) || defined (CHIP_3061MNPIC8) +#define GPIO2_4_AS_GPIO2_4 IOCMG_PIN_MUX(IOCFG_GPIO2_4, FUNC_MODE_0, 0x0230) +#define GPIO2_4_AS_GPT0_PWM IOCMG_PIN_MUX(IOCFG_GPIO2_4, FUNC_MODE_2, 0x0230) +#define GPIO2_4_AS_CAPM2_IN IOCMG_PIN_MUX(IOCFG_GPIO2_4, FUNC_MODE_4, 0x0230) +#define GPIO2_4_AS_WAKEUP3 IOCMG_PIN_MUX(IOCFG_GPIO2_4, FUNC_MODE_6, 0x0230) +#define GPIO2_4_AS_PMC2CORE_POR_N IOCMG_PIN_MUX(IOCFG_GPIO2_4, FUNC_MODE_11, 0x0230) +#endif + +#define GPIO1_2_AS_GPIO1_2 IOCMG_PIN_MUX(IOCFG_GPIO1_2, FUNC_MODE_0, 0x06b0) +#define GPIO1_2_AS_UPDATE_MODE IOCMG_PIN_MUX(IOCFG_GPIO1_2, FUNC_MODE_1, 0x06b0) +#define GPIO1_2_AS_UART2_TXD IOCMG_PIN_MUX(IOCFG_GPIO1_2, FUNC_MODE_3, 0x06b0) +#define GPIO1_2_AS_TEST_CLK IOCMG_PIN_MUX(IOCFG_GPIO1_2, FUNC_MODE_5, 0x06b0) + +#define GPIO0_5_AS_GPIO0_5 IOCMG_PIN_MUX(IOCFG_GPIO0_5, FUNC_MODE_0, 0x0221) +#define GPIO0_5_AS_JTAG_TDO IOCMG_PIN_MUX(IOCFG_GPIO0_5, FUNC_MODE_1, 0x0221) +#define GPIO0_5_AS_GPT1_PWM IOCMG_PIN_MUX(IOCFG_GPIO0_5, FUNC_MODE_2, 0x0221) +#define GPIO0_5_AS_UART1_RXD IOCMG_PIN_MUX(IOCFG_GPIO0_5, FUNC_MODE_3, 0x0221) +#define GPIO0_5_AS_CAPM2_IN IOCMG_PIN_MUX(IOCFG_GPIO0_5, FUNC_MODE_4, 0x0221) +#define GPIO0_5_AS_ADC_AIN2 IOCMG_PIN_MUX(IOCFG_GPIO0_5, FUNC_MODE_12, 0x0221) +#define GPIO0_5_AS_ACMP_P2 IOCMG_PIN_MUX(IOCFG_GPIO0_5, FUNC_MODE_13, 0x0221) + +#define GPIO0_6_AS_GPIO0_6 IOCMG_PIN_MUX(IOCFG_GPIO0_6, FUNC_MODE_0, 0x0331) +#define GPIO0_6_AS_JTAG_TDI IOCMG_PIN_MUX(IOCFG_GPIO0_6, FUNC_MODE_1, 0x0331) +#define GPIO0_6_AS_UART1_TXD IOCMG_PIN_MUX(IOCFG_GPIO0_6, FUNC_MODE_3, 0x0331) +#define GPIO0_6_AS_CAPM0_IN IOCMG_PIN_MUX(IOCFG_GPIO0_6, FUNC_MODE_4, 0x0331) +#define GPIO0_6_AS_ADC_AIN3 IOCMG_PIN_MUX(IOCFG_GPIO0_6, FUNC_MODE_12, 0x0331) +#define GPIO0_6_AS_ACMP_N2 IOCMG_PIN_MUX(IOCFG_GPIO0_6, FUNC_MODE_13, 0x0331) +#define GPIO0_6_AS_TSENSOR_OUT IOCMG_PIN_MUX(IOCFG_GPIO0_6, FUNC_MODE_14, 0x0331) + +#endif /* McuMagicTag_IOMAP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/ip_crg/ip_crg_common.c b/vendor/xinlingyu_92_3061M/Project/chip/3061m/ip_crg/ip_crg_common.c new file mode 100644 index 0000000000000000000000000000000000000000..79bb68eab124dc6690b24c91fa340ec1331225bb --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/ip_crg/ip_crg_common.c @@ -0,0 +1,127 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file ip_crg_common.c + * @author MCU Driver Team + * @brief Contains ip crg common header files. + */ + +/* Includes ----------------------------------------------------------------- */ +#include "baseaddr.h" +#include "ip_crg_common.h" + +/** + * @brief Get IP frequency by ip register base address + * @param ipBaseAddr The ip base address + * @retval The bus frequency where the IP is located + */ +#ifdef FPGA +unsigned int CHIP_GetIpFreqHz(const void *ipBaseAddr) +{ + void *highRateIp[] = { /* Defines the module base address for FPGA development. */ + SYSCTRL1_BASE, + CRC_BASE, + APT0_BASE, APT1_BASE, APT2_BASE, APT3_BASE, + CAPM0_BASE, CAPM1_BASE, CAPM2_BASE, CAPM_COMM_BASE, + QDM0_BASE, + ADC0_BASE, + PGA0_BASE, PGA1_BASE, + ACMP0_BASE, + }; + + if (ipBaseAddr == IWDG_BASE) { /* The IWDG working clock is LOSC clock. */ + return CHIP_IP_CLK_LOSC; + } else if (ipBaseAddr == CAN_BASE) { /* The CAN working clock is HOSC. */ + return CHIP_IP_CLK_CAN; + } else { + for (unsigned int i = 0; i < sizeof(highRateIp) / sizeof(highRateIp[0]); ++i) { + if (ipBaseAddr == highRateIp[i]) { + return CHIP_IP_CLK_HS; + } + } + return CHIP_IP_CLK_LS; /* The base address does not match, return LOSC freq. */ + } +} +#endif + +static const CHIP_CrgIpMatchInfo g_crgIpMatch[] = { + {UART0_BASE, CRG_IP_NONE_CLK_SEL, 0x140, 0}, + {UART1_BASE, CRG_IP_NONE_CLK_SEL, 0x144, 0}, + {UART2_BASE, CRG_IP_NONE_CLK_SEL, 0x148, 0}, + {UART3_BASE, CRG_IP_NONE_CLK_SEL, 0x14C, 0}, + {TIMER0_BASE, CRG_IP_NONE_CLK_SEL, 0x240, 0}, + {TIMER1_BASE, CRG_IP_NONE_CLK_SEL, 0x244, 0}, + {TIMER2_BASE, CRG_IP_NONE_CLK_SEL, 0x248, 0}, + {TIMER3_BASE, CRG_IP_NONE_CLK_SEL, 0x24C, 0}, + {SYSTICK_BASE, CRG_IP_NONE_CLK_SEL, 0x40, 0}, + {SPI0_BASE, CRG_IP_NONE_CLK_SEL, 0x180, 0}, + {SPI1_BASE, CRG_IP_NONE_CLK_SEL, 0x184, 0}, + {I2C0_BASE, CRG_IP_NONE_CLK_SEL, 0x1C0, 0}, + {I2C1_BASE, CRG_IP_NONE_CLK_SEL, 0x1C4, 0}, + {CAN_BASE, CRG_IP_CAN, 0x2C0, 0}, + {GPT0_BASE, CRG_IP_NONE_CLK_SEL, 0x440, 0}, + {GPT1_BASE, CRG_IP_NONE_CLK_SEL, 0x444, 0}, + {GPT2_BASE, CRG_IP_NONE_CLK_SEL, 0x448, 0}, + {GPT3_BASE, CRG_IP_NONE_CLK_SEL, 0x44C, 0}, + {WWDG_BASE, CRG_IP_NONE_CLK_SEL, 0x200, 0}, + {CAPM0_BASE, CRG_IP_NONE_CLK_SEL, 0x280, 0}, + {CAPM1_BASE, CRG_IP_NONE_CLK_SEL, 0x284, 0}, + {CAPM2_BASE, CRG_IP_NONE_CLK_SEL, 0x288, 0}, + {DMA_BASE, CRG_IP_NONE_CLK_SEL, 0x300, 0}, + {GPIO0_BASE, CRG_IP_NONE_CLK_SEL, 0x480, 0}, + {GPIO1_BASE, CRG_IP_NONE_CLK_SEL, 0x484, 0}, + {GPIO2_BASE, CRG_IP_NONE_CLK_SEL, 0x488, 0}, + {GPIO3_BASE, CRG_IP_NONE_CLK_SEL, 0x48C, 0}, + {GPIO4_BASE, CRG_IP_NONE_CLK_SEL, 0x490, 0}, + {GPIO5_BASE, CRG_IP_NONE_CLK_SEL, 0x494, 0}, + {IWDG_BASE, CRG_IP_IWDG, 0x3C0, 0}, + {QDM0_BASE, CRG_IP_NONE_CLK_SEL, 0x4C0, 0}, + {QDM1_BASE, CRG_IP_NONE_CLK_SEL, 0x4C4, 0}, + {HPM_BASE, CRG_IP_NONE_CLK_SEL, 0xB00, 0}, + {CRC_BASE, CRG_IP_NONE_CLK_SEL, 0x380, 0}, + {APT0_BASE, CRG_IP_NONE_CLK_SEL, 0x400, 0}, + {APT1_BASE, CRG_IP_NONE_CLK_SEL, 0x404, 0}, + {APT2_BASE, CRG_IP_NONE_CLK_SEL, 0x408, 0}, + {APT3_BASE, CRG_IP_NONE_CLK_SEL, 0x40C, 0}, + {CMM_BASE, CRG_IP_NONE_CLK_SEL, 0x0340, 0}, + {VREF_BASE, CRG_IP_ANA, 0xA60, 0}, + {ACMP0_BASE, CRG_IP_ANA, 0xA70, 0}, + {DAC0_BASE, CRG_IP_ANA, 0xA80, 0}, + {PGA0_BASE, CRG_IP_ANA, 0xA90, 0}, + {PGA1_BASE, CRG_IP_ANA, 0xA90, 4}, + + {ADC0_BASE, CRG_IP_ADC, 0xA00, 0}, + + {EFC_BASE, CRG_IP_EFC, 0x500, 0}, +}; + +/** + * @brief Get IP Match Info, @see g_crgIpMatch + * @param baseAddr The ip base address + * @retval The Address(offset) in g_crgIpMatch if match success + * @retval 0 if match fail + */ +CHIP_CrgIpMatchInfo *GetCrgIpMatchInfo(const void *baseAddr) +{ + unsigned int i; + for (i = 0; i < sizeof(g_crgIpMatch) / sizeof(g_crgIpMatch[0]); ++i) { + if (baseAddr == g_crgIpMatch[i].ipBaseAddr) { + return (CHIP_CrgIpMatchInfo *)&g_crgIpMatch[i]; + } + } + return (CHIP_CrgIpMatchInfo *)0; /* The base address does not match, return 0. */ +} diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/ip_crg/ip_crg_common.h b/vendor/xinlingyu_92_3061M/Project/chip/3061m/ip_crg/ip_crg_common.h new file mode 100644 index 0000000000000000000000000000000000000000..9ed469fa8ed8b67eced7dee63a8b6aa8b23fc9f7 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/ip_crg/ip_crg_common.h @@ -0,0 +1,82 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file ip_crg_common.h + * @author MCU Driver Team + * @brief Contains crg ip common header files. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_IP_CRG_COMMON_H +#define McuMagicTag_IP_CRG_COMMON_H + +/** + * @brief define the frequence of hosc, losc and xtrail + */ +#define HOSC_FREQ 25000000U +#define LOSC_FREQ 32000U + +#ifdef FPGA +#define FLASH_SUPPORT +typedef enum { + CHIP_IP_CLK_LOSC = LOSC_FREQ, + CHIP_IP_CLK_CAN = HOSC_FREQ, +#ifdef FLASH_SUPPORT + CHIP_IP_CLK_LS = HOSC_FREQ, + CHIP_IP_CLK_HS = HOSC_FREQ, +#else + CHIP_IP_CLK_LS = HOSC_FREQ, + CHIP_IP_CLK_HS = HOSC_FREQ, +#endif +} CHIP_IpRate; +#else +typedef enum { + CHIP_IP_CLK_LOSC = 32000U, + CHIP_IP_CLK_CAN = 25000000U, + CHIP_IP_CLK_LS = 25000000U, + CHIP_IP_CLK_HS = 25000000U, +} CHIP_IpRate; +#endif + +/** + * @brief CRG Ip Type, Sorting based on operable registers + */ +typedef enum { + CRG_IP_NONE_CLK_SEL = 0x00, + CRG_IP_CAN = 0x01, + CRG_IP_ADC = 0x02, + CRG_IP_EFC = 0x03, + CRG_IP_IWDG = 0x04, + CRG_IP_ANA = 0x05, + CRG_IP_MAX_TYPE = 0x06, +} CHIP_CrgIpType; + +/** + * @brief CRG register and IP address matching relationship table + */ +typedef struct { + void *ipBaseAddr; /**< Ip base address */ + CHIP_CrgIpType type; /**< Ip type, @see CHIP_CrgIpType */ + unsigned short regOffset; /**< Offset in CRG registers */ + unsigned char bitOffset; /**< Bit Offset in CRG register */ +} CHIP_CrgIpMatchInfo; + +unsigned int CHIP_GetIpFreqHz(const void *ipBaseAddr); +CHIP_CrgIpMatchInfo *GetCrgIpMatchInfo(const void *baseAddr); +extern unsigned int HAL_CRG_GetIpFreq(const void *baseAddress); + +#endif /* McuMagicTag_IP_CRG_COMMON_H */ diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/locktype.h b/vendor/xinlingyu_92_3061M/Project/chip/3061m/locktype.h new file mode 100644 index 0000000000000000000000000000000000000000..08b87ff323fa96916a32bd204b309d4d4d7bbc0f --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/locktype.h @@ -0,0 +1,43 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file locktype.h + * @author MCU Driver Team + * @brief This file lists all types that need to be locked on the chip. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_LOCKTYPE_H +#define McuMagicTag_LOCKTYPE_H + +/* Typedef definitions ------------------------------------------------------- */ +/** + * @brief This enum defines all hardware locks integrated by this MCU. + */ +typedef enum { + CHIP_LOCK_GPIO0 = 0, + CHIP_LOCK_GPIO1 = 1, + CHIP_LOCK_GPIO2 = 2, + CHIP_LOCK_GPIO3 = 3, + CHIP_LOCK_GPIO4 = 4, + CHIP_LOCK_GPIO5 = 5, + CHIP_LOCK_GPIO6 = 6, + CHIP_LOCK_GPIO7 = 7, + CHIP_LOCK_TOTAL +} CHIP_LockType; + +#endif /* McuMagicTag_LOCKTYPE_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/startup.S b/vendor/xinlingyu_92_3061M/Project/chip/3061m/startup.S new file mode 100644 index 0000000000000000000000000000000000000000..8aedfa8f6d20cf1dc6a88b224c57ebec789a9f51 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/startup.S @@ -0,0 +1,720 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file startup.S + * @author MCU Application Driver Team + * @brief RISC-V trap handling and startup code + */ + +#ifndef ENTRY_S +#define ENTRY_S + +#include "feature.h" + +.extern __stack_top +.extern __irq_stack_top +.extern SysErrNmiEntry +.extern SysErrExcEntry +.extern trap_entry +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) +.extern g_RiscvPrivMode +#endif + +#ifdef __riscv64 +#define LREG ld +#define SREG sd +#define FLREG fld +#define FSREG fsd +#define REGBYTES 8 +#else +#define LREG lw +#define SREG sw +#define FLREG flw +#define FSREG fsw +#define REGBYTES 4 +#endif + +#define NESTED_IRQ_SUPPORT +#define COMPILE_LDM /**< Support stmia and ldmia instruction */ + +#ifdef FLOAT_SUPPORT +#define TOTAL_INT_SIZE_ON_STACK (40 * REGBYTES) +#else +#define TOTAL_INT_SIZE_ON_STACK (20 * REGBYTES) +#endif + +#define SYSERR_INT_SIZE_ON_STACK (28 * REGBYTES) + +#define MSTATUS_MPP_MACHINE 0x00001800 +#define MCAUSE_ECALL_FROM_MMODE 11 +#define MCAUSE_ECALL_FROM_UMODE 8 +#define EXC_SIZE_ON_STACK (160) + +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_MPIE 0x00000080 +#define MCAUSE_MASK_INT_BIT 0x80000000 +#define MCAUSE_MASK_INT_NUM 0x000000FF + +#define locipri0 0xBC0 +#define locipri1 0xBC1 +#define locipri2 0xBC2 +#define locipri3 0xBC3 +#define locipri4 0xBC4 +#define locipri5 0xBC5 +#define locipri6 0xBC6 +#define locipri7 0xBC7 +#define locipri8 0xBC8 +#define locipri9 0xBC9 +#define locipri10 0xBCA +#define locipri11 0xBCB +#define locipri12 0xBCC +#define locipri13 0xBCD +#define locipri14 0xBCE +#define locipri15 0xBCF + +#define EFC_BASE_ADDR 0x14710000 /* efc base address */ +#define EFC_MAGIC_LOCK_RW 0x14710200 /* cmd operation magic word protection register */ +#define EFC_MAGIC_NUMBER 0xFEDCBA98 /* magic number */ +#define SYSRAM_ERROR 0x10108300 +#define SC_SYS_STAT_ADDR 0x10100018 /**< System state register address */ +#define TIMER0_CONTROL 0x14300008 +#define TIMER0_INTENABLE (1 << 5) +#define UART0_BASE_ADDR 0x14000000 +#define IBRD_OFFSET 0x24 +#define FBRD_OFFSET 0x28 +#define LCR_H_OFFSET 0x2C +#define CR_OFFSET 0x30 +#define DMACR_OFFSET 0x48 + +.equ cipri, 0x7ED +.equ prithd, 0xBFE + + .section .data.magic + .word 0xA37E95BD /* eflash magic number, bootrom will check it */ + + .section .text.entry + .global _start + .option norvc +_start: + j handle_reset + +.macro push_reg + addi sp, sp, -(TOTAL_INT_SIZE_ON_STACK) +#ifdef COMPILE_LDM + stmia {ra, t0-t2, a0-a7, t3-t6}, (sp) +#else + SREG ra, 0 * REGBYTES(sp) + SREG t0, 1 * REGBYTES(sp) + SREG t1, 2 * REGBYTES(sp) + SREG t2, 3 * REGBYTES(sp) + SREG a0, 4 * REGBYTES(sp) + SREG a1, 5 * REGBYTES(sp) + SREG a2, 6 * REGBYTES(sp) + SREG a3, 7 * REGBYTES(sp) + SREG a4, 8 * REGBYTES(sp) + SREG a5, 9 * REGBYTES(sp) + SREG a6, 10 * REGBYTES(sp) + SREG a7, 11 * REGBYTES(sp) + SREG t3, 12 * REGBYTES(sp) + SREG t4, 13 * REGBYTES(sp) + SREG t5, 14 * REGBYTES(sp) + SREG t6, 15 * REGBYTES(sp) +#endif + addi sp, sp, -(TOTAL_INT_SIZE_ON_STACK) +.endm + +.macro pop_reg + addi sp, sp, TOTAL_INT_SIZE_ON_STACK +#ifdef COMPILE_LDM + ldmia {ra, t0-t2, a0-a7, t3-t6},(sp) +#else + LREG ra, 0 * REGBYTES(sp) + LREG t0, 1 * REGBYTES(sp) + LREG t1, 2 * REGBYTES(sp) + LREG t2, 3 * REGBYTES(sp) + LREG a0, 4 * REGBYTES(sp) + LREG a1, 5 * REGBYTES(sp) + LREG a2, 6 * REGBYTES(sp) + LREG a3, 7 * REGBYTES(sp) + LREG a4, 8 * REGBYTES(sp) + LREG a5, 9 * REGBYTES(sp) + LREG a6, 10 * REGBYTES(sp) + LREG a7, 11 * REGBYTES(sp) + LREG t3, 12 * REGBYTES(sp) + LREG t4, 13 * REGBYTES(sp) + LREG t5, 14 * REGBYTES(sp) + LREG t6, 15 * REGBYTES(sp) +#endif + addi sp, sp, TOTAL_INT_SIZE_ON_STACK +.endm + +.macro SAVE_SYSERR_REGS + addi sp,sp,-(SYSERR_INT_SIZE_ON_STACK) + SREG s0, 16 * REGBYTES(sp) + SREG s1, 17 * REGBYTES(sp) + SREG s2, 18 * REGBYTES(sp) + SREG s3, 19 * REGBYTES(sp) + SREG s4, 20 * REGBYTES(sp) + SREG s5, 21 * REGBYTES(sp) + SREG s6, 22 * REGBYTES(sp) + SREG s7, 23 * REGBYTES(sp) + SREG s8, 24 * REGBYTES(sp) + SREG s9, 25 * REGBYTES(sp) + SREG s10, 26 * REGBYTES(sp) + SREG s11, 27 * REGBYTES(sp) + + addi a1, sp, (TOTAL_INT_SIZE_ON_STACK + SYSERR_INT_SIZE_ON_STACK) + SREG a1, 28 * REGBYTES(sp) /* save original sp */ + + SREG gp, 29 * REGBYTES(sp) + SREG tp, 30 * REGBYTES(sp) + + csrr a0, mepc + csrr a1, mstatus + csrr a2, mtval + csrr a3, mcause + # csrr a4, ccause + + SREG a0, 31 * REGBYTES(sp) /* mepc */ + SREG a1, 32 * REGBYTES(sp) /* mstatus */ + SREG a2, 33 * REGBYTES(sp) /* mtval */ + SREG a3, 34 * REGBYTES(sp) /* mcause */ + # SREG a4, 35 * REGBYTES(sp) /* ccause */ + mv a0,sp +.endm + +/* The interrupt vector table must be aligned with 4 bytes */ +.align 2 +TrapHandler: + j TrapVector /* trap and INT 0 */ + j TrapVector /* INT 1 */ + j TrapVector /* INT 2 */ + j TrapVector /* INT 3 */ + j TrapVector /* INT 4 */ + j TrapVector /* INT 5 */ + j TrapVector /* INT 6 */ + j TrapVector /* INT 7 */ + j TrapVector /* INT 8 */ + j TrapVector /* INT 9 */ + j TrapVector /* INT 10 */ + j TrapVector /* INT 11 */ + j TrapVector /* INT 12 */ + j TrapVector /* INT 13 */ + j TrapVector /* INT 14 */ + j TrapVector /* INT 15 */ + j TrapVector /* INT 16 */ + j TrapVector /* INT 17 */ + j TrapVector /* INT 18 */ + j TrapVector /* INT 19 */ + j TrapVector /* INT 20 */ + j TrapVector /* INT 21 */ + j TrapVector /* INT 22 */ + j TrapVector /* INT 23 */ + j TrapVector /* INT 24 */ + j TrapVector /* INT 25 */ + + j IntHandler /* INT 26 */ + j IntHandler /* INT 27 */ + j IntHandler /* INT 28 */ + j IntHandler /* INT 29 */ + j IntHandler /* INT 30 */ + j IntHandler /* INT 31 */ + j IntHandler /* INT 32 */ + j IntHandler /* INT 33 */ + j IntHandler /* INT 34 */ + j IntHandler /* INT 35 */ + j IntHandler /* INT 36 */ + j IntHandler /* INT 37 */ + j IntHandler /* INT 38 */ + j IntHandler /* INT 39 */ + j IntHandler /* INT 40 */ + j IntHandler /* INT 41 */ + j IntHandler /* INT 42 */ + j IntHandler /* INT 43 */ + j IntHandler /* INT 44 */ + j IntHandler /* INT 45 */ + j IntHandler /* INT 46 */ + j IntHandler /* INT 47 */ + j IntHandler /* INT 48 */ + j IntHandler /* INT 49 */ + j IntHandler /* INT 50 */ + j IntHandler /* INT 51 */ + j IntHandler /* INT 52 */ + j IntHandler /* INT 53 */ + j IntHandler /* INT 54 */ + j IntHandler /* INT 55 */ + j IntHandler /* INT 56 */ + j IntHandler /* INT 57 */ + j IntHandler /* INT 58 */ + j IntHandler /* INT 59 */ + j IntHandler /* INT 60 */ + j IntHandler /* INT 61 */ + j IntHandler /* INT 62 */ + j IntHandler /* INT 63 */ + j IntHandler /* INT 64 */ + j IntHandler /* INT 65 */ + j IntHandler /* INT 66 */ + j IntHandler /* INT 67 */ + j IntHandler /* INT 68 */ + j IntHandler /* INT 69 */ + j IntHandler /* INT 70 */ + j IntHandler /* INT 71 */ + j IntHandler /* INT 72 */ + j IntHandler /* INT 73 */ + j IntHandler /* INT 74 */ + j IntHandler /* INT 75 */ + j IntHandler /* INT 76 */ + j IntHandler /* INT 77 */ + j IntHandler /* INT 78 */ + j IntHandler /* INT 79 */ + j IntHandler /* INT 80 */ + j IntHandler /* INT 81 */ + j IntHandler /* INT 82 */ + j IntHandler /* INT 83 */ + j IntHandler /* INT 84 */ + j IntHandler /* INT 85 */ + j IntHandler /* INT 86 */ + j IntHandler /* INT 87 */ + j IntHandler /* INT 88 */ + j IntHandler /* INT 89 */ + j IntHandler /* INT 90 */ + j IntHandler /* INT 91 */ + j IntHandler /* INT 92 */ + j IntHandler /* INT 93 */ + j IntHandler /* INT 94 */ + j IntHandler /* INT 95 */ + j IntHandler /* INT 96 */ + j IntHandler /* INT 97 */ + j IntHandler /* INT 98 */ + j IntHandler /* INT 99 */ + j IntHandler /* INT 100 */ + j IntHandler /* INT 101 */ + j IntHandler /* INT 102 */ + j IntHandler /* INT 103 */ + j IntHandler /* INT 104 */ + j IntHandler /* INT 105 */ + j IntHandler /* INT 106 */ + j IntHandler /* INT 107 */ + j IntHandler /* INT 108 */ + j IntHandler /* INT 109 */ + j IntHandler /* INT 110 */ + j IntHandler /* INT 111 */ + j IntHandler /* INT 112 */ + j IntHandler /* INT 113 */ + j IntHandler /* INT 114 */ + j IntHandler /* INT 115 */ + j IntHandler /* INT 116 */ + j IntHandler /* INT 117 */ + j IntHandler /* INT 118 */ + j IntHandler /* INT 119 */ + j IntHandler /* INT 120 */ + j IntHandler /* INT 121 */ + +.align 2 +NmiEntry: + SAVE_SYSERR_REGS + call SysErrNmiEntry +deadLoop1: + tail deadLoop1 + nop + +.align 2 +TrapEntry: + SAVE_SYSERR_REGS + /* Exception run with interrupts masked */ + csrc mstatus, MSTATUS_MIE + call SysErrExcEntry +deadLoop2: + tail deadLoop2 + +.align 2 +IntHandler: + addi sp, sp, -(TOTAL_INT_SIZE_ON_STACK) + + SREG a0, 3 * REGBYTES(sp) + SREG a1, 4 * REGBYTES(sp) + +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + la a0, g_RiscvPrivMode + lw a1, (a0) + addi a1, a1, 1 + sw a1, (a0) +#endif + +#if defined(HARD_NESTED_IRQ_SUPPORT) && (HARD_NESTED_IRQ_SUPPORT == 1) + csrr a0, mcause +#else + csrr a0, cipri + csrr a1, prithd + csrw prithd, a0 /* read prithd */ + SREG a1, 6 * REGBYTES(sp) /* save prithd */ + csrr a1, mstatus /* read mstatus */ + SREG a1, 7 * REGBYTES(sp) /* save mstatus */ + csrr a1, mepc /* read mepc */ + SREG a1, 8 * REGBYTES(sp) /* save mepc */ + + csrr a0, mcause + + li a1, (3<<11) + csrs mstatus, a1 + la a1, custom_nested_irq_main_handler_entry + csrw mepc, a1 + mret +#endif + +.align 2 +custom_nested_irq_main_handler_entry: + SREG t0, 0 * REGBYTES(sp) + SREG t1, 1 * REGBYTES(sp) + SREG t2, 2 * REGBYTES(sp) + SREG a2, 5 * REGBYTES(sp) + SREG ra, 9 * REGBYTES(sp) + SREG a3, 10 * REGBYTES(sp) + SREG a4, 11 * REGBYTES(sp) + SREG a5, 12 * REGBYTES(sp) + SREG a6, 13 * REGBYTES(sp) + SREG a7, 14 * REGBYTES(sp) + SREG t3, 15 * REGBYTES(sp) + SREG t4, 16 * REGBYTES(sp) + SREG t5, 17 * REGBYTES(sp) + SREG t6, 18 * REGBYTES(sp) + +#ifdef FLOAT_SUPPORT + FSREG f0, 19 * REGBYTES(sp) + FSREG f1, 20 * REGBYTES(sp) + FSREG f2, 21 * REGBYTES(sp) + FSREG f3, 22 * REGBYTES(sp) + FSREG f4, 23 * REGBYTES(sp) + FSREG f5, 24 * REGBYTES(sp) + FSREG f6, 25 * REGBYTES(sp) + FSREG f7, 26 * REGBYTES(sp) + FSREG f10, 27 * REGBYTES(sp) + FSREG f11, 28 * REGBYTES(sp) + FSREG f12, 29 * REGBYTES(sp) + FSREG f13, 30 * REGBYTES(sp) + FSREG f14, 31 * REGBYTES(sp) + FSREG f15, 32 * REGBYTES(sp) + FSREG f16, 33 * REGBYTES(sp) + FSREG f17, 34 * REGBYTES(sp) + FSREG f28, 35 * REGBYTES(sp) + FSREG f29, 36 * REGBYTES(sp) + FSREG f30, 37 * REGBYTES(sp) + FSREG f31, 38 * REGBYTES(sp) +#endif + + andi a0, a0, MCAUSE_MASK_INT_NUM + call InterruptEntry + + LREG t1, 1 * REGBYTES(sp) + LREG t2, 2 * REGBYTES(sp) + LREG a2, 5 * REGBYTES(sp) + LREG ra, 9 * REGBYTES(sp) + LREG a3, 10 * REGBYTES(sp) + LREG a4, 11 * REGBYTES(sp) + LREG a5, 12 * REGBYTES(sp) + LREG a6, 13 * REGBYTES(sp) + LREG a7, 14 * REGBYTES(sp) + LREG t3, 15 * REGBYTES(sp) + LREG t4, 16 * REGBYTES(sp) + LREG t5, 17 * REGBYTES(sp) + LREG t6, 18 * REGBYTES(sp) + +#ifdef FLOAT_SUPPORT + FLREG f0, 19 * REGBYTES(sp) + FLREG f1, 20 * REGBYTES(sp) + FLREG f2, 21 * REGBYTES(sp) + FLREG f3, 22 * REGBYTES(sp) + FLREG f4, 23 * REGBYTES(sp) + FLREG f5, 24 * REGBYTES(sp) + FLREG f6, 25 * REGBYTES(sp) + FLREG f7, 26 * REGBYTES(sp) + FLREG f10, 27 * REGBYTES(sp) + FLREG f11, 28 * REGBYTES(sp) + FLREG f12, 29 * REGBYTES(sp) + FLREG f13, 30 * REGBYTES(sp) + FLREG f14, 31 * REGBYTES(sp) + FLREG f15, 32 * REGBYTES(sp) + FLREG f16, 33 * REGBYTES(sp) + FLREG f17, 34 * REGBYTES(sp) + FLREG f28, 35 * REGBYTES(sp) + FLREG f29, 36 * REGBYTES(sp) + FLREG f30, 37 * REGBYTES(sp) + FLREG f31, 38 * REGBYTES(sp) +#endif + +quit_int: + /* + * Since the interrupt is already turned off when loading mstatus (after entering the interrupt, + * the hardware will turn off the interrupt, so when saving mstatus, the interrupt is already turned off), + * so there is no need to turn off the interrupt separately. + */ + +#if defined(HARD_NESTED_IRQ_SUPPORT) && (HARD_NESTED_IRQ_SUPPORT == 1) + LREG t0, 0 * REGBYTES(sp) +#else + LREG a0, 7 * REGBYTES(sp) /* load mstatus */ + csrr t0, mstatus + LREG a1, 8 * REGBYTES(sp) /* load mepc */ + andi t0, t0, MSTATUS_MIE + bnei t0, 0, restore_mstatus + andi a0, a0, ~(MSTATUS_MIE | MSTATUS_MPIE) +restore_mstatus: + csrw mstatus, a0 + + LREG t0, 0 * REGBYTES(sp) + csrw mepc, a1 + LREG a0, 6 * REGBYTES(sp) /* load prithd */ + csrw prithd, a0 +#endif + +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + la a0, g_RiscvPrivMode + lw a1, (a0) + addi a1, a1, -1 + sw a1, (a0) +#endif + + LREG a1, 4 * REGBYTES(sp) /* 2 consecutive csrw instructions will have a bubble */ + + LREG a0, 3 * REGBYTES(sp) + + addi sp, sp, TOTAL_INT_SIZE_ON_STACK + + mret + +.align 2 +TrapVector: + push_reg + csrr a0, mcause + li t1, MCAUSE_ECALL_FROM_MMODE +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + beq a0, t1, switch_to_umode +#else + beq a0, t1, switch_to_mmode +#endif + li t1, MCAUSE_ECALL_FROM_UMODE + beq a0, t1, switch_to_mmode + + li a1, MCAUSE_MASK_INT_BIT + li a2, MCAUSE_MASK_INT_NUM + and a1, a0, a1 + and a0, a0, a2 + + li a2, 0xc + beq a0, a2, NmiEntry + beqz a1, TrapEntry + pop_reg + mret + +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) +.align 2 +switch_to_umode: + li t2, MSTATUS_MPP_MACHINE + csrc mstatus, t2 + csrr t0, mepc + addi t0, t0, 4 + csrw mepc, t0 + pop_reg + mret +#endif + +.align 2 +switch_to_mmode: + li t2, MSTATUS_MPP_MACHINE + csrs mstatus, t2 + csrr t0, mepc + addi t0, t0, 4 + csrw mepc, t0 + pop_reg + mret + +.align 2 +mem_cpy: + bge t0, t2, cpy_done + lw t3, (t1) + sw t3, (t0) + addi t0, t0, 4 + addi t1, t1, 4 + j mem_cpy +cpy_done: + ret + +.align 2 +handle_reset: + csrwi mstatus, 0 + csrwi mie, 0 + csrci mstatus, 0x08 + la t0, TrapHandler + addi t0, t0, 1 + csrw mtvec, t0 + csrwi 0x7EF, 0x1 /* lock mtvec */ + +#if defined(HARD_NESTED_IRQ_SUPPORT) && (HARD_NESTED_IRQ_SUPPORT == 1) + csrwi 0x7C8, 0x1 /* enable hardware nest interrupt support */ +#endif + +flash_init: +/* eflash prefetch enable */ + li t0, EFC_BASE_ADDR + lw t1, 0x120(t0) + ori t1, t1, 1 + sw t1, 0x120(t0) + +/* eflash cache enable */ + lw t1, 0x124(t0) + ori t1, t1, 1 + sw t1, 0x124(t0) + +/* enable flash cmd */ + li t0, EFC_MAGIC_NUMBER + li t1, EFC_MAGIC_LOCK_RW + sw t0, (t1) + +/* initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + .option pop + +/* initialize stack pointer */ + la sp, __stack_top + +/* timer0 interrupt enable */ + li t0, TIMER0_CONTROL + lw t1, (t0) + andi t1, t1, TIMER0_INTENABLE + sw t1, (t0) + +/* uart0 deinit */ + li t0, 0x14000000 + li t1, 0 + sw t1, IBRD_OFFSET(t0) + sw t1, FBRD_OFFSET(t0) + sw t1, LCR_H_OFFSET(t0) + sw t1, CR_OFFSET(t0) + sw t1, DMACR_OFFSET(t0) + +/* perform the rest of initialization in C */ +clear_sram: + /* clear sysram parity error */ + li t0, SYSRAM_ERROR + lw t1, (t0) + ori t1, t1, 1 + sw t1, (t0) + + la t0, SRAM_START + la t1, SRAM_END + li t2, 0 + +clear_sram_loop: + sw t2, (t0) /* clear all sram */ + addi t0, t0, 4 /* increment clear index pointer */ + blt t0, t1, clear_sram_loop /* are we at the end yet, if not , contiue till the end */ + +start_coderom_code_copy: + la t0, __sram_code_start_addr /* SRAM addr */ + la t1, __sram_code_load_addr /* ROM addr */ + la t2, __sram_code_end_addr + jal mem_cpy + +start_reserved_data_copy: + la t0, __reserved_code_start_addr /* SRAM addr */ + la t1, __reserved_code_load_addr /* ROM addr */ + la t2, __reserved_code_end_addr + jal mem_cpy + +start_coderom_data_copy: + la t0, __data_start /* SRAM addr */ + la t1, __data_load /* ROM addr */ + la t2, __data_end + jal mem_cpy + +pmp_init: + li t0, 0xB00 + csrw pmpaddr0, t0 + li t0, 0x400400 /* 0x2C00~0x1000FFF, BOOTROM, enable R+X */ + csrw pmpaddr1, t0 + li t0, 0x800000 /* 0x1001000~0x1FFFFFF, Reserved: diable R+X+W */ + csrw pmpaddr2, t0 + li t0, 0x802000 /* 0x2000000~0x2007FFF, SYSRAM_ITCM */ + csrw pmpaddr3, t0 + li t0, 0xC00000 /* 0x2008000 ~ 0x2FFFFFF, Reserved: disable R+X+W */ + csrw pmpaddr4, t0 + li t0, 0x1000000 /* 0x3000000 ~ 0x03FFFFFF: EFLASH: enable R+X */ + csrw pmpaddr5, t0 + li t0, 0x1002000 /* 0x4000000 ~ 0x04007FFF: SYSTEM_DTCM enable R+W */ + csrw pmpaddr6, t0 + li t0,0x7000400 /* 0x4008000 ~ 0x01C000FFF: REGISTER R+W */ + csrw pmpaddr7, t0 + + li t0,0xf3333333 /* register TOR-R-W */ + csrw 0x7d8,t0 +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + li t0,0x0d080d8b /* 0x0d:TOR-R-X; 0x0b:TOR-R-W; 0x08:TOR; 0x0c:TOR-x; 0x09:TOR-R */ + csrw pmpcfg0,t0 + li t0,0x0b0b0d08 + csrw pmpcfg1,t0 +#else + li t0,0x8d888d8b /* 0x0d:TOR-R-X; 0x0b:TOR-R-W; 0x08:TOR; 0x0c:TOR-x; 0x09:TOR-R */ + csrw pmpcfg0,t0 + li t0,0x8b8b8d88 + csrw pmpcfg1,t0 +#endif + +/* disable Icache */ + csrwi 0x7C0, 0x0 /* disable ICACHE */ + fence + +/* disable Dcache */ + csrwi 0x7C1, 0x0 /* disable DCACHE */ + fence + +/* support float and mie */ + li t0,0x2008 + csrs mstatus,t0 + li t0,0x20 + csrs misa,t0 + +/* Interrupt set default priority = 1*/ + li t0, 0x11111111 + csrw locipri0, t0 + csrw locipri1, t0 + csrw locipri2, t0 + csrw locipri3, t0 + csrw locipri4, t0 + csrw locipri5, t0 + csrw locipri6, t0 + csrw locipri7, t0 + csrw locipri8, t0 + csrw locipri9, t0 + csrw locipri10, t0 + csrw locipri11, t0 + csrw locipri12, t0 + csrw locipri13, t0 + csrw locipri14, t0 + csrw locipri15, t0 + + ecall + jal Chip_Init + +/* jump to C func. */ + jal main + +dead_loop: + j dead_loop + +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/sysctrl.h b/vendor/xinlingyu_92_3061M/Project/chip/3061m/sysctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..b23f23aa63b8904c1b4f1f6cc4ec89fd0bcbe8c6 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/sysctrl.h @@ -0,0 +1,563 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file sysctrl.h + * @author MCU Driver Team + * @brief This file provides firmware functions to manage the following + * functionalities of the system control register. + * + Register Struct of SYSCTRL + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_SYSCTRL_H +#define McuMagicTag_SYSCTRL_H + +/* Includes ------------------------------------------------------------------ */ +#include "baseaddr.h" +#include "typedefs.h" + +/* Macro definitions ---------------------------------------------------------*/ +#define SC_LOCKEN_VALID_HIGH_BIT 0xEA510000U /**< Upper 16 active bits of the SC_LOCKEN register */ +#define SC_LOW_BIT_MASK 0x0000FFFFU /**< Obtains the mask of the lower 16 bits. */ +#define SC_LOCKEN_CRG_DISABLE_MASK 0x0000FFFEU /**< CRG write protection disable mask in SC_LOCKEN */ +#define SC_LOCKEN_CRG_ENABLE_MASK 0x00000001U /**< CRG write protection enable mask in SC_LOCKEN */ +#define SC_LOCKEN_SC_DISABLE_MASK 0x0000FFFDU /**< SC write protection disable mask in SC_LOCKEN */ +#define SC_LOCKEN_SC_ENABLE_MASK 0x00000002U /**< SC write protection enbale mask in SC_LOCKEN */ + + +/** + * @brief Records the offsets of various states in the CPU status register. + */ +typedef enum { + SYSCTRL_NMI_BIT = 0x00000000U, + SYSCTRL_LOCKUP_BIT = 0x00000002U, + SYSCTRL_HARD_FAULT_BIT = 0x00000003U, + SYSCTRL_DEBUG_BIT = 0x00000004U, + SYSCTRL_SLEEP_BIT = 0x00000005U, + SYSCTRL_PC_VALID_BIT = 0x0000001FU +} SYSCTRL_CPU_Status; + +/** + * @brief FUNC_JTAG_SEL_REG register function item. + */ +typedef enum { + SYSCTRL_FUNC_JTAG_CORESIGHT = 0x00000000U, + SYSCTRL_FUNC_JYAG_EFLASH = 0x00000001U +} SYSCTRL_FUNC_JTAG_Status; + +/** + * @brief System soft reset register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int softresreq : 1; /**< Set any value to make system soft reset. */ + unsigned int reserved : 31; + } BIT; +} volatile SC_SYS_RES_REG; + +/** + * @brief Record the number of resets(soft reset, pin reset). + */ +typedef union { + unsigned int reg; + struct { + unsigned int soft_rst_cnt : 16; /**< Number of soft resets. */ + unsigned int ext_rst_cnt : 16; /**< Number of reset times of the RESETN pin. */ + } BIT; +} volatile SC_RST_CNT0_REG; + +/** + * @brief Record the number of resets(wdg reset, iwdg reset). + */ +typedef union { + unsigned int reg; + struct { + unsigned int wdg_rst_cnt : 16; /**< Number of WDG resets. */ + unsigned int iwdg_rst_cnt : 16; /**< Number of IWDG resets. */ + } BIT; +} volatile SC_RST_CNT1_REG; + +/** + * @brief System status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int update_mode_clear : 1; /**< System upgrade flag clear register, 0:not clear, 1:clear. */ + unsigned int reserved0 : 3; + unsigned int update_mode : 1; /**< System upgrade flag, 0:not upgrade, 1:upgrade. */ + unsigned int reserved1 : 27; + } BIT; +} volatile SC_SYS_STAT_REG; + +/** + * @brief Software interrupt register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int software_int : 1; /**< Software interrupt register, writing 1 generates a software interrupt. */ + unsigned int reserved : 31; + } BIT; +} volatile SC_SOFT_INT_REG; + +/** + * @brief Software interrupt event ID register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int swint_evt_id : 32; /**< Software interrupt event ID. */ + } BIT; +} volatile SC_SOFT_EVT_ID_REG; + +/** + * @brief Lock register of key registers. + */ +typedef union { + unsigned int reg; + struct { + unsigned int crg_cfg_lock : 1; /**< Write protection for CRG, 0: write enabled, 1: write disabled. */ + unsigned int sc_cfg_lock : 1; /**< Write protection for SYSCTRL, 0: write enabled, 1: write disabled. */ + unsigned int reserved : 30; + } BIT; +} volatile SC_LOCKEN_REG; + +/** + * @brief SC dedicated hard reset register 0. (CH) This register is not reset by a system soft reset. + */ +typedef union { + unsigned int reg; + struct { + unsigned int sc_hrst_reg0 : 32; /**< If the value is 0xA5A5A5, the CPU stops starting the system. */ + } BIT; +} volatile SC_HRST_REG0_REG; + +/** + * @brief User dedicated hard reset register 0. (CH) This register is not reset by a system soft reset. + */ +typedef union { + unsigned int reg; + struct { + unsigned int user_hrst_reg0 : 32; /**< User-dedicated hard reset register 0. */ + } BIT; +} volatile USER_HRST_REG0_REG; + +/** + * @brief User dedicated hard reset register 1. (CH) This register is not reset by a system soft reset. + */ +typedef union { + unsigned int reg; + struct { + unsigned int user_hrst_reg1 : 32; /**< User-dedicated hard reset register 1. */ + } BIT; +} volatile USER_HRST_REG1_REG; + +/** + * @brief User dedicated POR reset register 0. (CH) This register is reset only by a POR reset. + */ +typedef union { + unsigned int reg; + struct { + unsigned int user_por_reg0 : 32; /**< User dedicated POR reset register 0. */ + } BIT; +} volatile USER_POR_REG0_REG; + +/** + * @brief User dedicated POR reset register 1. (CH) This register is reset only by a POR reset. + */ +typedef union { + unsigned int reg; + struct { + unsigned int user_por_reg1 : 32; /**< User dedicated POR reset register 1. */ + } BIT; +} volatile USER_POR_REG1_REG; + +/** + * @brief User dedicated register 0. + */ +typedef union { + unsigned int reg; + struct { + unsigned int user_reg0 : 32; /**< User dedicated register 0. */ + } BIT; +} volatile USER_REG0_REG; + +/** + * @brief User dedicated register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int user_reg1 : 32; /**< User dedicated register 1. */ + } BIT; +} volatile USER_REG1_REG; + +/** + * @brief SYSCTRL0 register. + */ +typedef struct _SYSCTRL0_Regstruct { + char space0[4]; + SC_SYS_RES_REG SC_SYS_RES; /**< System soft reset register, offset address: 0x0004. */ + SC_RST_CNT0_REG SC_RST_CNT0; /**< Reset count register 0, offset address: 0x0008. */ + SC_RST_CNT1_REG SC_RST_CNT1; /**< Reset count register 1, offset address: 0x000C. */ + char space1[8]; + SC_SYS_STAT_REG SC_SYS_STAT; /**< System boot mode register, offset address: 0x0018. */ + char space2[4]; + SC_SOFT_INT_REG SC_SOFT_INT; /**< Software interrupt register, offset address: 0x0020. */ + SC_SOFT_EVT_ID_REG SC_SOFT_EVT_ID; /**< Software interrupt event ID register, offset address: 0x0024. */ + char space3[28]; + SC_LOCKEN_REG SC_LOCKEN; /**< Lock register of key registers, offset address: 0x0044. */ + char space4[440]; + SC_HRST_REG0_REG SC_HRST_REG0; /**< SC dedicated hard reset register 0, offset address: 0x0200. */ + char space5[3068]; + USER_POR_REG0_REG USER_POR_REG0; /**< User dedicated POR reset register 0, offset address: 0x0E00. */ + USER_POR_REG1_REG USER_POR_REG1; /**< User dedicated POR reset register 1, offset address: 0x0E04. */ + char space6[56]; + USER_HRST_REG0_REG USER_HRST_REG0; /**< User dedicated hard reset register 0, offset address: 0x0E40. */ + USER_HRST_REG1_REG USER_HRST_REG1; /**< User dedicated hard reset register 1, offset address: 0x0E44. */ + char space7[56]; + USER_REG0_REG USER_REG0; /**< User dedicated register 0, offset address: 0x0E80. */ + USER_REG1_REG USER_REG1; /**< User dedicated register 1, offset address: 0x0E84. */ +} volatile SYSCTRL0_RegStruct; + +/** + * @brief APT enable register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int apt0_run : 1; /**< APT0 enable control, 0：enable, 1:enable. */ + unsigned int apt1_run : 1; /**< APT1 enable control, 0：enable, 1:enable. */ + unsigned int apt2_run : 1; /**< APT2 enable control, 0：enable, 1:enable. */ + unsigned int apt3_run : 1; /**< APT3 enable control, 0：enable, 1:enable. */ + unsigned int reserved : 28; + } BIT; +} volatile APT_RUN_REG; + +/** + * @brief Poe filter register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int poe0_filter_level : 8; /**< Number of POE0 Filter Cycles. */ + unsigned int poe1_filter_level : 8; /**< Number of POE1 Filter Cycles. */ + unsigned int poe2_filter_level : 8; /**< Number of POE2 Filter Cycles. */ + unsigned int poe0_filter_en : 1; /**< POE0 filter enable, 0：enable, 1:enable. */ + unsigned int poe1_filter_en : 1; /**< POE1 filter enable, 0：enable, 1:enable. */ + unsigned int poe2_filter_en : 1; /**< POE2 filter enable, 0：enable, 1:enable. */ + unsigned int reserved : 5; + } BIT; +} volatile APT_POE_FILTER_REG; + +/** + * @brief APT_EVTIO_FILTER register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int apt_evtio4_filter_level : 8; /**< Number of APT EVTIO4 Filter Cycles. */ + unsigned int apt_evtio5_filter_level : 8; /**< Number of APT EVTIO5 Filter Cycles. */ + unsigned int reserved0 : 8; + unsigned int apt_evtio4_filter_en : 1; /**< APT EVTIO4 FILTER enable, 0：enable, 1:enable. */ + unsigned int apt_evtio5_filter_en : 1; /**< APT EVTIO5 FILTER enable, 0：enable, 1:enable. */ + unsigned int reserved1 : 6; + } BIT; +} volatile APT_EVTIO_FILTER_REG; + +/** + * @brief APT_EVTMP_FILTER register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int apt_evtmp4_filter_level : 8; /**< Number of APT EVTMP4 Filter Periods. */ + unsigned int apt_evtmp5_filter_level : 8; /**< Number of APT EVTMP5 Filter Periods. */ + unsigned int apt_evtmp6_filter_level : 8; /**< Number of APT EVTMP6 Filter Periods. */ + unsigned int apt_evtmp4_filter_en : 1; /**< APT EVTMP4 FILTER enable, 0：enable, 1:enable. */ + unsigned int apt_evtmp5_filter_en : 1; /**< APT EVTMP5 FILTER enable, 0：enable, 1:enable. */ + unsigned int apt_evtmp6_filter_en : 1; /**< APT EVTMP6 FILTER enable, 0：enable, 1:enable. */ + unsigned int reserved : 5; + } BIT; +} volatile APT_EVTMP_FILTER_REG; + +/** + * @brief XTAL_CFG register. + * + */ +typedef union { + unsigned int reg; + struct { + unsigned int osc_ds : 4; /**< Crystal I/O Drive Capability Configuration. */ + unsigned int ose_e : 1; /**< Crystal I/O resonance buffer enable, 0:disable, 1:enable. */ + unsigned int osc_ie : 1; /**< Crystal I/O clock input enable, 0:disable, 1:enable. */ + unsigned int reserved : 26; + } BIT; +} volatile XTAL_CFG_REG; + +/** + * @brief Sysram parity check register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int sysram_parity_err_clr : 1; /**< SYSRAM parity error status clear, write any value to clear. */ + unsigned int sysram0_parity_err : 1; /**< SYSRAM Parity Error Status, 0:no error, 1:error. */ + unsigned int sysram1_parity_err : 1; /**< SYSRAM Parity Error Status, 0:no error, 1:error. */ + unsigned int reserved : 29; + } BIT; +} volatile SYSRAM_ERR_REG; + +/** + * @brief SYSRAM_MAP register. + * + */ +typedef union { + unsigned int reg; + struct { + unsigned int sysram_split : 3; /**< SYSRAM space allocation. */ + unsigned int reserved : 29; + } BIT; +} volatile SYSRAM_MAP_REG; + +/** + * @brief PVD_CFG register. + * + */ +typedef union { + unsigned int reg; + struct { + unsigned int pvd_en : 1; /**< PVD enable flag, 0:disable, 1:enable. */ + unsigned int pvd_rise_thd : 3; /**< PVD rising edge threshold. */ + unsigned int pvd_fall_thd : 3; /**< PVD falling edge threshold. */ + unsigned int reserved : 25; + } BIT; +} volatile PVD_CFG_REG; + +/** + * @brief PVD_STATUS register. + * + */ +typedef union { + unsigned int reg; + struct { + unsigned int pvd_toggle : 1; /**< PVD triggering flag. */ + unsigned int reserved : 31; + } BIT; +} volatile PVD_STATUS_REG; + +/** + * @brief CPU status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cpu_in_nmi_hdlr : 1; /**< CPU NMI processing status. 0: non-NMI processing state, + 1: NMI processing status. */ + unsigned int cpu_ra_wr_en : 1; /**< cpu_ra_wr enable. */ + unsigned int cpu_lockup_mode : 1; /**< CPU LOCKUP status. 0: non-lockup state, 1: lockup state. */ + unsigned int cpu_hard_fault_mode : 1; /**< Indicates the hard fault status of the CPU. 0: non-hard_fault state, + 1: hard_fault. */ + unsigned int cpu_debug_mode : 1; /**< Indicates the CPU debug status. 0: non-debug state, + 1: debug state. */ + unsigned int cpu_sleep_mode : 1; /**< CPU sleep status. 0: non-sleep state, 1: sleep state. */ + unsigned int reserved : 25; + unsigned int cpu_pc_valid : 1; /**< Valid status of the CPU PC value. 0: The PC value is invalid, + 1: The PC value is valid. */ + } BIT; +} volatile CPU_STATUS_REG; + +/** + * @brief SYSCTRL1 register. + */ +typedef struct _SYSCTRL1_RegStruct { + char space0[0x8000]; + APT_RUN_REG APT_RUN; /**< APT enable control register, offset address: 0x8000. */ + char space1[12]; + APT_POE_FILTER_REG APT_POE_FILTER; /**< APT PoE filtering control register, offset address: 0x8010. */ + APT_EVTIO_FILTER_REG APT_EVTIO_FILTER; /**< APT EVTIO filtering control register, offset address: 0x8014. */ + APT_EVTMP_FILTER_REG APT_EVTMP_FILTER; /**< APT EVTMP filtering control register, offset address: 0x8018. */ + char space2[228]; + XTAL_CFG_REG XTAL_CFG; /**< Crystal I/O control register, offset address: 0x8100. */ + char space3[508]; + SYSRAM_ERR_REG SYSRAM_ERR; /**< SYSRAM parity check status register, offset address: 0x8300. */ + SYSRAM_MAP_REG SYS_MAP; /**< SYSRAM space allocation register, offset address: 0x8304. */ + char space4[248]; + PVD_CFG_REG PVD_CFG; /**< PVD configuration register, offset address: 0x8400. */ + PVD_STATUS_REG PVD_STATUS; /**< PVD status register, offset address: 0x8404. */ + char space5[3064]; + CPU_STATUS_REG CPU_STATUS; /**< CPU status register, offset address: 0x9000. */ +} volatile SYSCTRL1_RegStruct; + +/** + * @brief Make system soft reset. + * @param None + * @retval None. + */ +static inline void DCL_SYSCTRL_SoftReset(void) +{ + SYSCTRL0->SC_SYS_RES.BIT.softresreq = 1; +} + +/** + * @brief Get number of soft resets. + * @param None + * @retval Number of soft resets. + */ +static inline unsigned short DCL_SYSCTRL_GetSoftResetConut(void) +{ + return SYSCTRL0->SC_RST_CNT0.BIT.soft_rst_cnt; +} + +/** + * @brief Get number of reset times of the RESETN pin. + * @param None + * @retval Number of reset times of the RESETN pin. + */ +static inline unsigned short DCL_SYSCTRL_GetPinResetConut(void) +{ + return SYSCTRL0->SC_RST_CNT0.BIT.ext_rst_cnt; +} + +/** + * @brief Get number of WDG resets. + * @param None + * @retval Number of WDG resets. + */ +static inline unsigned short DCL_SYSCTRL_GetWdgResetConut(void) +{ + return SYSCTRL0->SC_RST_CNT1.BIT.wdg_rst_cnt; +} + +/** + * @brief Get number of IWDG resets. + * @param None + * @retval Number of IWDG resets. + */ +static inline unsigned short DCL_SYSCTRL_GetIWdgResetConut(void) +{ + return SYSCTRL0->SC_RST_CNT1.BIT.iwdg_rst_cnt; +} + +/** + * @brief Set the write protection for SYSCTRL registers disable. + * @param None + * @retval None. + */ +static inline void DCL_SYSCTRL_ScWriteProtectionDisable(void) +{ + /* Set the corresponding bit without affecting the other bits and set the high 16 bits to EA51 to write to. */ + SYSCTRL0->SC_LOCKEN.reg = (SYSCTRL0->SC_LOCKEN.reg & SC_LOCKEN_SC_DISABLE_MASK) + SC_LOCKEN_VALID_HIGH_BIT; +} + +/** + * @brief Set the write protection for SYSCTRL registers enable. + * @param None + * @retval None. + */ +static inline void DCL_SYSCTRL_ScWriteProtectionEnable(void) +{ + /* Set the corresponding bit without affecting the other bits and set the high 16 bits to EA51 to write to. */ + SYSCTRL0->SC_LOCKEN.reg = ((SYSCTRL0->SC_LOCKEN.reg & SC_LOW_BIT_MASK) | SC_LOCKEN_SC_ENABLE_MASK) + + SC_LOCKEN_VALID_HIGH_BIT; +} + +/** + * @brief Set the write protection for CRG-related registers disable. + * @param None + * @retval None. + */ +static inline void DCL_SYSCTRL_CrgWriteProtectionDisable(void) +{ + /* Set the corresponding bit without affecting the other bits and set the high 16 bits to EA51 to write to. */ + SYSCTRL0->SC_LOCKEN.reg = (SYSCTRL0->SC_LOCKEN.reg & SC_LOCKEN_CRG_DISABLE_MASK) + SC_LOCKEN_VALID_HIGH_BIT; +} + +/** + * @brief Set the Set the write protection for CRG-related registers enable. + * @param None + * @retval None. + */ +static inline void DCL_SYSCTRL_CrgWriteProtectionEnable(void) +{ + /* Set the corresponding bit without affecting the other bits and set the high 16 bits to EA51 to write to. */ + SYSCTRL0->SC_LOCKEN.reg = ((SYSCTRL0->SC_LOCKEN.reg & SC_LOW_BIT_MASK) | SC_LOCKEN_CRG_ENABLE_MASK) + + SC_LOCKEN_VALID_HIGH_BIT; +} + +/** + * @brief Set software interrupt register, writing 1 generates a software interrupt. + * @param None + * @retval None. + */ +static inline void DCL_SYSCTRL_GenerateSoftInterrupt(void) +{ + SYSCTRL0->SC_SOFT_INT.BIT.software_int = 1; +} + +/** + * @brief Set Software interrupt event ID. + * @param id the software interrupt event ID. + * @retval None. + */ +static inline void DCL_SYSCTRL_SetSoftInterruptEventId(unsigned int id) +{ + SYSCTRL0->SC_SOFT_EVT_ID.BIT.swint_evt_id = id; +} + +/** + * @brief Get Software interrupt event ID. + * @param None + * @retval The value of software interrupt event ID. + */ +static inline unsigned int DCL_SYSCTRL_GetSoftInterruptEventId(void) +{ + return SYSCTRL0->SC_SOFT_EVT_ID.BIT.swint_evt_id; +} + +/** + * @brief Get SYSRAM Parity Error Status. + * @param None. + * @retval 0:no error, 1:error. + */ +static inline unsigned int DCL_SYSCTRL_GetSysramParityErrorStatus(void) +{ + return SYSCTRL1->SYSRAM_ERR.BIT.sysram0_parity_err; +} + +/** + * @brief Set SYSRAM parity error status clear. + * @param None. + * @retval None. + */ +static inline void DCL_SYSCTRL_ClearSysramParityError(void) +{ + SYSCTRL1->SYSRAM_ERR.BIT.sysram_parity_err_clr = 1; /* Write any value to clear. */ +} + +/** + * @brief Get CPU status. + * @param offset Bit offset of CPU status. + * @retval true or false + */ +static inline bool DCL_SYSCTRL_CheckCpuStatus(SYSCTRL_CPU_Status offset) +{ + return ((SYSCTRL1->CPU_STATUS.reg) & (1 << offset)) == 0 ? false : true; +} +#endif /* McuMagicTag_SYSCTRL_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/3061m/systick.h b/vendor/xinlingyu_92_3061M/Project/chip/3061m/systick.h new file mode 100644 index 0000000000000000000000000000000000000000..8e4f42eb30db1e8c1a5235d91582b184f4a3282b --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/3061m/systick.h @@ -0,0 +1,110 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file systick.h + * @author MCU Driver Team + * @brief SYSTICK module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the SYSTICK. + * + SYSTICK register mapping structure + * + Get SysTick counter + */ + + +#ifndef McuMagicTag_SYSTICK_H +#define McuMagicTag_SYSTICK_H + +/* Includes ------------------------------------------------------------------*/ +#include "baseaddr.h" +#include "systickinit.h" +/** + * @addtogroup SYSTICK + * @{ + */ + +/** + * @defgroup SYSTICK_IP SYSTICK_IP + * @brief SYSTICK_IP: systick + * @{ + */ + +/** + * @defgroup SYSTICK_Param_Def SYSTICK Parameters Definition + * @brief Definition of SYSTICK configuration parameters. + * @{ + */ + +#define SYSTICK_MAX_VALUE 0xFFFFFFFFUL + +/** + * @} + */ + +/** + * @brief SYSTICK control register structure. + */ +typedef union { + unsigned int reg; + struct { + unsigned int enable : 1; /**< Mtimer enable. */ + unsigned int clksrc : 1; /**< Mtimer clock source select. */ + unsigned int stop_tmr_en : 2; /**< Parameter change test. */ + unsigned int reserved : 28; + } BIT; +} TIMER_CTRL_REG; + +/** + * @brief SYSTICK DIV control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int div : 10; /**< Timer frequency division control. */ + unsigned int reserved : 22; + } BIT; +} TIMER_DIV_REG; + +/** + * @brief SYSTICK register structure + */ +typedef struct { + TIMER_CTRL_REG TIMER_CTRL; /**< Mtimer control register. Offset address: 0x00000000U. */ + TIMER_DIV_REG TIMER_DIV; /**< Mtimer frequency divider register. Offset address: 0x00000004U. */ + unsigned int MTIME; /**< Mtimer count value lower 32-bit register. Offset address: 0x00000008U. */ + unsigned int MTIME_H; /**< Upper 32-bit register for Mtimer count value. Offset address: 0x0000000CU. */ + unsigned int MTIMECMP; /**< Mtimer comparison value lower 32-bit register. Offset address: 0x00000010U. */ + unsigned int MTIMECMP_H; /**< Upper 32-bit Mtimer comparison value register. Offset address: 0x00000014U. */ +} volatile SYSTICK_RegStruct; + +/** + * @} + */ + +/** + * @brief Get the systick + * @param None + * @retval The SysTick Value + */ +static inline unsigned int DCL_SYSTICK_GetTick(void) +{ + return SYSTICK->MTIME; /* Systick value(Lower 32bit register) */ +} + +/** + * @} + */ +#endif /* McuMagicTag_SYSTICK_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/chip/target/userconfig.json b/vendor/xinlingyu_92_3061M/Project/chip/target/userconfig.json new file mode 100644 index 0000000000000000000000000000000000000000..855b1d10e96b82ff6e565d2c04653800ad711097 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/chip/target/userconfig.json @@ -0,0 +1,132 @@ +{ + "system": [ + { + "name": "compile", + "subsystem": [ + { + "name": "static_lib", + "component": [ + { + "name": "", + "target_type": "static", + "sources": [], + "includes": [], + "define": [], + "libs": [], + "lds_scripts": [], + "cflags": [], + "asmflags": [], + "ldflags": [] + } + ] + }, + { + "name": "compile_frame", + "cflags": [ + "-O0", + "-pipe", + "-Wall", + "-Wextra", + "-Winit-self", + "-Wmissing-include-dirs", + "-Wtrampolines", + "-Werror=undef", + "-Wpointer-arith", + "-Wlogical-op", + "-Wstrict-prototypes", + "-Wmissing-prototypes", + "-Wjump-misses-init", + "-Wformat=2", + "-Wfloat-equal", + "-Wdate-time", + "-Wswitch-default", + "-Wimplicit-fallthrough=2", + "-Wno-missing-declarations", + "-std=gnu11", + "-fsigned-char", + "-fno-builtin", + "-ffreestanding", + "-nostdlib", + "-fno-exceptions", + "-fno-unwind-tables", + "-fno-short-enums", + "-fno-common", + "-freg-struct-return", + "-mabi=ilp32f", + "-march=rv32imfc", + "-fno-strict-aliasing", + "-fdata-sections", + "-ffunction-sections", + "-falign-functions=2", + "-fno-schedule-insns", + "-fno-optimize-strlen", + "-fno-aggressive-loop-optimizations", + "-Wa,-enable-c-lbu-sb", + "-Wa,-enable-c-lhu-sh", + "-msmall-data-limit=0", + "-fimm-compare", + "-femit-muliadd", + "-fmerge-immshf", + "-femit-uxtb-uxth", + "-femit-lli", + "-fldm-stm-optimize", + "-fno-inline-small-functions", + "-mtune=size", + "-mpush-pop", + "-femit-clz", + "-madjust-regorder", + "-madjust-const-cost", + "-freorder-commu-args", + "-fimm-compare-expand", + "-frmv-str-zero", + "-mfp-const-opt", + "-mswitch-jump-table", + "-frtl-sequence-abstract", + "-frtl-hoist-sink", + "-fsafe-alias-multipointer", + "-finline-optimize-size", + "-fmuliadd-expand", + "-mlli-expand", + "-Wa,-mcjal-expand", + "-foptimize-reg-alloc", + "-fsplit-multi-zero-assignments", + "-floop-optimize-size", + "-mpattern-abstract", + "-foptimize-pro-and-epilogue", + "-fstrict-volatile-bitfields", + "-Wcast-align", + "-fstrong-eval-order", + "-Wunused", + "-Wvla", + "-Wshadow", + "-fvisibility=hidden", + "-fsingle-precision-constant" + ], + "asmflags": [], + "ldflags": [ + "-Wl,-Map,bin/target.map", + "-Wl,--enjal16", + "-Wl,--gc-section", + "-Wl,--cjal-relax", + "-Wl,--dslf", + "-Wl,--jal-transfer", + "-nostdlib", + "-static", + "-lgcc", + "-lc", + "-Wl,-Bsymbolic", + "-rdynamic", + "-Wl,--no-undefined" + ], + "define": [ + "FLOAT_SUPPORT" + ], + "nocheck": [], + "extlibspath": [], + "extlibsname": [], + "extlibsinclude": [] + } + ] + } + ] +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/acmp/common/inc/acmp.h b/vendor/xinlingyu_92_3061M/Project/drivers/acmp/common/inc/acmp.h new file mode 100644 index 0000000000000000000000000000000000000000..6f894dcf7d2a58a7811ea54e2f9efddceb583be2 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/acmp/common/inc/acmp.h @@ -0,0 +1,101 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file acmp.h + * @author MCU Driver Team. + * @brief ACMP module driver. + * This file provides functions declaration of the Comparator. + * + Comparator's Initialization and de-initialization functions + * + Set Comparator's hysteresis voltage function + * + Set blocking function. + * + Interrupt handling and register. + */ +#ifndef McuMagicTag_ACMP_H +#define McuMagicTag_ACMP_H +#include "acmp_ip.h" + +#ifdef ACMP_PARAM_CHECK +#define ACMP_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#else +#define ACMP_ASSERT_PARAM(para) ((void)0U) +#endif + +/** + * @defgroup ACMP ACMP + * @brief ACMP module. + * @{ + */ + +/** + * @defgroup ACMP_Common ACMP Common + * @brief ACMP common external module. + * @{ + */ + + +/** + * @defgroup ACMP_Handle_Definition ACMP Handle Definition + * @{ + */ + +/** + * @brief ACMP Handle + */ +typedef struct _ACMP_Handle { + ACMP_RegStruct *baseAddress; /**< ACMP registers base address. */ + ACMP_InOutConfig inOutConfig; /**< ACMP input and output setting. */ + ACMP_FilterCtrl filterCtrl; /**< ACMP filter setting. */ + unsigned short hysteresisVol; /**< ACMP hysteresis voltage setting. */ + ACMP_UserCallBack userCallBack; /**< ACMP user callback function. */ + volatile bool interruptEn; /**< ACMP interrupt enable. */ + ACMP_ExtendHandle handleEx; /**< ACMP extended parameter. */ +} ACMP_Handle; + +typedef void (* ACMP_CallBackType)(void *handle); +/** + * @} + */ + +/** + * @defgroup ACMP_API_Declaration ACMP HAL API + * @{ + */ +BASE_StatusType HAL_ACMP_Init(ACMP_Handle *acmpHandle); +BASE_StatusType HAL_ACMP_DeInit(ACMP_Handle *acmpHandle); +void HAL_ACMP_SetHystVol(ACMP_Handle *acmpHandle, ACMP_HystVol voltage); +void HAL_ACMP_BlkingValid(ACMP_Handle *acmpHandle); +void HAL_ACMP_BlkingInvalid(ACMP_Handle *acmpHandle); + +/* ACMP output result selection. */ +BASE_StatusType HAL_ACMP_ResultSelect(ACMP_Handle *acmpHandle, ACMP_ResultSelect resultSelect); + +/* ACMP interrupt service function and user callback registration function. */ +void HAL_ACMP_IrqHandler(void *handle); +BASE_StatusType HAL_ACMP_RegisterCallBack(ACMP_Handle *uartHandle, ACMP_CallBackFun_Type typeID, + ACMP_CallBackType pCallback); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/acmp/inc/acmp_ex.h b/vendor/xinlingyu_92_3061M/Project/drivers/acmp/inc/acmp_ex.h new file mode 100644 index 0000000000000000000000000000000000000000..8291c1897481c4beb66452bb0069a257670b37af --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/acmp/inc/acmp_ex.h @@ -0,0 +1,51 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file acmp_ex.h + * @author MCU Driver Team + * @brief ACMP module driver. + * @details This file provides extend functions declaration of the acmp, + * + Set trim value. + */ + +/* Includes ------------------------------------------------------------------*/ +#ifndef McuMagicTag_ACMP_EX_H +#define McuMagicTag_ACMP_EX_H + +#include "acmp.h" + +/** + * @addtogroup ACMP_IP + * @{ + */ + +/** + * @defgroup ACMP_EX_API_Declaration ACMP HAL API EX + * @{ + */ + +/* ACMP trim value setting. */ +BASE_StatusType HAL_ACMP_SetTrimValueEx(ACMP_Handle *acmpHandle, unsigned char trimValue); + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_ACMP_EX_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/acmp/inc/acmp_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/acmp/inc/acmp_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..16c8de9401fd3f83159001189ce5ea655897d938 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/acmp/inc/acmp_ip.h @@ -0,0 +1,673 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file acmp_ip.h + * @author MCU Driver Team + * @brief ACMP module driver. + * This file provides DCL functions to manage ACMP and Definitions of specific parameters. + * + Definition of ACMP configuration parameters. + * + ACMP register mapping structure. + * + Parameters check functions. + * + Direct configuration layer interface. + */ + +#ifndef McuMagicTag_ACMP_IP_H +#define McuMagicTag_ACMP_IP_H + +#include "baseinc.h" + +#ifdef ACMP_PARAM_CHECK +#define ACMP_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define ACMP_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define ACMP_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define ACMP_ASSERT_PARAM(para) ((void)0U) +#define ACMP_PARAM_CHECK_NO_RET(para) ((void)0U) +#define ACMP_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +#define ACMP_FILTER_STEP_MAX_VALUE 0x00000FFFEU + +/** + * @addtogroup ACMP + * @{ + */ + +/** + * @defgroup ACMP_IP ACMP_IP + * @brief ACMP_IP: acmp_v1. + * @{ + */ + +/** + * @defgroup ACMP_Param_Def ACMP Parameters Definition + * @brief Definition of ACMP configuration parameters + * @{ + */ + +/** + * @brief Comparator blking source type + * @details Description: + * + ACMP_BLKING_SRC_SOFT ---- The software configuration masks the window. + * + ACMP_BLKING_SRC_APT0 ---- APT0 output mask window. + * + ACMP_BLKING_SRC_APT1 ---- APT1 output mask window. + * + ACMP_BLKING_SRC_APT2 ---- APT2 output mask window. + * + ACMP_BLKING_SRC_APT3 ---- APT3 output mask window. + */ +typedef enum { + ACMP_BLKING_SRC_SOFT = 0x00000000U, + ACMP_BLKING_SRC_APT0 = 0x00000001U, + ACMP_BLKING_SRC_APT1 = 0x00000002U, + ACMP_BLKING_SRC_APT2 = 0x00000003U, + ACMP_BLKING_SRC_APT3 = 0x00000004U, +} ACMP_BlkingSrcType; + +/** + * @brief Comparator hysteresis voltage + * @details Description: + * + ACMP_HYS_VOL_ZERO ---- Hysteresis voltage 0 mv. + * + ACMP_HYS_VOL_10MV ---- Hysteresis voltage 10 mv. + * + ACMP_HYS_VOL_20MV ---- Hysteresis voltage 20 mv. + * + ACMP_HYS_VOL_30MV ---- Hysteresis voltage 30 mv. + */ +typedef enum { + ACMP_HYS_VOL_ZERO = 0x00000000U, + ACMP_HYS_VOL_10MV = 0x00000001U, + ACMP_HYS_VOL_20MV = 0x00000002U, + ACMP_HYS_VOL_30MV = 0x00000003U, +} ACMP_HystVol; + +/** + * @brief ACMP P port input select. + * @details Description: + * + ACMP_INPUT_P_SELECT0 ---- Signal source PGA0_OUT. + * + ACMP_INPUT_P_SELECT1 ---- Signal source PGA1_OUT. + * + ACMP_INPUT_P_SELECT2 ---- From pin (GPIO0_5). + * + ACMP_INPUT_P_SELECT3 ---- From pin (GPIO2_5). + * + ACMP_INPUT_P_SELECT4 ---- From pin (GPIO3_5). + * + ACMP_INPUT_P_SELECT5 ---- Signal source DAC_OUT. + */ +typedef enum { + ACMP_INPUT_P_SELECT0 = 0x00000000U, + ACMP_INPUT_P_SELECT1 = 0x00000001U, + ACMP_INPUT_P_SELECT2 = 0x00000002U, + ACMP_INPUT_P_SELECT3 = 0x00000003U, + ACMP_INPUT_P_SELECT4 = 0x00000004U, + ACMP_INPUT_P_SELECT5 = 0x00000005U, +} ACMP_InputPSel; + +/** + * @brief ACMP N port input select. + * @details Description: + * + ACMP_INPUT_N_SELECT0 ---- Signal source DAC_OUT. + * + ACMP_INPUT_N_SELECT1 ---- None. + * + ACMP_INPUT_N_SELECT2 ---- From pin (GPIO0_6). + * + ACMP_INPUT_N_SELECT3 ---- From pin (GPIO2_6). + * + ACMP_INPUT_N_SELECT4 ---- From pin (GPIO3_6). + * + ACMP_INPUT_N_SELECT5 ---- Signal source DAC_OUT. + */ +typedef enum { + ACMP_INPUT_N_SELECT0 = 0x00000000U, + ACMP_INPUT_N_SELECT1 = 0x00000001U, + ACMP_INPUT_N_SELECT2 = 0x00000002U, + ACMP_INPUT_N_SELECT3 = 0x00000003U, + ACMP_INPUT_N_SELECT4 = 0x00000004U, + ACMP_INPUT_N_SELECT5 = 0x00000005U, +} ACMP_InputNSel; + +/** + * @brief Comparator output polarity + */ +typedef enum { + ACMP_OUT_NOT_INVERT = 0x00000000U, + ACMP_OUT_INVERT = 0x00000001U, +} ACMP_OutputPolarity; + +/** + * @brief ACMP output selection + * @details Description: + * + ACMP_RESULT_SIMULATION ---- Simulate the original comparison result. + * + ACMP_RESULT_FILTER ---- Digital Filtering Comparison Results. + * + ACMP_RESULT_FILTER_BLOCK ---- Digital Filtering and Blocking Comparison Results. + */ +typedef enum { + ACMP_RESULT_SIMULATION = 0x00000000U, + ACMP_RESULT_FILTER = 0x00000001U, + ACMP_RESULT_FILTER_BLOCK = 0x00000002U, +} ACMP_ResultSelect; + +/** + * @brief Comparator filter mode + * @details Description: + * + ACMP_FILTER_NONE ---- Raw analog comparison. + * + ACMP_FILTER_BLOCK ---- Blocking function. + * + ACMP_FILTER_FILTER ---- Filtering funciton. + * + ACMP_FILTER_BOTH ---- Filtering and Blocking function. + */ +typedef enum { + ACMP_FILTER_NONE = 0x00000000U, + ACMP_FILTER_BLOCK = 0x00000001U, + ACMP_FILTER_FILTER = 0x00000002U, + ACMP_FILTER_BOTH = 0x00000003U, +} ACMP_FilterMode; + +/** + * @brief Comparator filter control structure + */ +typedef struct { + ACMP_FilterMode filterMode; /**< ACMP filter mode. */ + ACMP_BlkingSrcType blkingSrcSelect; /**< Blocking source select.*/ + unsigned short filterStep; /**< Filter Step. */ + bool blkingPorty; /**< Polarity select of the mask window. */ +} ACMP_FilterCtrl; + +/** + * @brief Comparator input and output configuration structure + */ +typedef struct { + ACMP_OutputPolarity polarity; /**< output polarity settings */ + ACMP_InputPSel inputPNum; /**< ACMP input positive number */ + ACMP_InputNSel inputNNum; /**< ACMP input negative number */ +} ACMP_InOutConfig; + +/** + * @brief ACMP user callback function type. + */ +typedef enum { + ACMP_POS_INT = 0x00000000U, + ACMP_NEG_INT = 0x00000001U, + ACMP_EDGE_INT = 0x00000002U, +} ACMP_CallBackFun_Type; + +/** + * @brief ACMP user interrupt callback function. + */ +typedef struct { + void (* AcmpPositiveCallBack)(void *handle); /**< Rising edge interrupt callback function. */ + void (* AcmpNegativeCallBack)(void *handle); /**< Falling edge interrupt callback function. */ + void (* AcmpEdgedCallBack)(void *handle); /**< Flip edge interrupt callback function. */ +} ACMP_UserCallBack; + +/** + * @brief ACMP extend configure. + */ +typedef struct { +} ACMP_ExtendHandle; + +/** + * @} + */ + +/** + * @defgroup ACMP_REG_Definition ACMP Register Structure. + * @brief ACMP Register Structure Definition. + * @{ + */ + +/** + * @brief ACMP control reg 0. + */ +typedef union { + unsigned int reg; + struct { + unsigned int da_acmp_enh : 1; /**< Comparator enable signal. */ + unsigned int reserved_0 : 31; + } BIT; +} volatile ACMP_CTRL_REG0; + +/** + * @brief ACMP control reg 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int da_acmp_input_psel : 3; /**< Input P vin selection */ + unsigned int da_acmp_input_nsel : 3; /**< Input N vin selection */ + unsigned int reserved_0 : 26; + } BIT; +} volatile ACMP_CTRL_REG1; + +/** + * @brief ACMP control reg 2. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_acmp_out_sel : 2; /**< Comparator output result selection: + 0: original comparison result; + 1: result after filtering; + 2: masked result; + 3: 0. */ + unsigned int cfg_acmp_out_inv : 1; /**< Comparator result polarity selection: + 0: The result is not reversed. + 1: The result is reversed. */ + unsigned int reserved_0 : 29; + } BIT; +} volatile ACMP_CTRL_REG2; + +/** + * @brief ACMP filtering control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_acmp_filter_en : 1; /**< Comparator filtering enable: + 0: disabled; + 1: enabled. */ + unsigned int cfg_acmp_filter_step : 16; /**< Filter step size of the comparator. */ + unsigned int reserved_0 : 15; + } BIT; +} volatile ACMP_CTRL_REG3; + +/** + * @brief ACMP mask control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_acmp_blk_en : 1; /**< Comparator mask enable: + 0: disabled; + 1: enabled. */ + unsigned int reserved_0 : 7; + unsigned int cfg_acmp_blk_sel : 3; /**< Comparator Mask Window Selection: + 0: The window is masked by software. + 1: APT0 output mask window; + 2: APT1 output mask window; + 3: APT2 output mask window; + 4: APT3 output mask window; + else: 0. */ + unsigned int reserved_1 : 5; + unsigned int cfg_acmp_blk_win : 1; /**< The software configuration mask window is displayed. */ + unsigned int reserved_2 : 7; + unsigned int cfg_acmp_blk_pol_sel : 1; /**< Select the polarity of the mask window. + 0: The high-level mask window is valid. + 1: The low-level shielding window is valid. */ + unsigned int cfg_acmp_blk_rslt_pol : 1; /**< Polarity selection of the masking result: + 0: The masking result is low level. + 1: The masking result is high level. */ + unsigned int reserved_3 : 6; + } BIT; +} volatile ACMP_CTRL_REG4; + + +/** + * @brief ACMP interrupt raw status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int intr_acmp_edge : 1; /**< Comparison result reversal edge interrupt status. */ + unsigned int intr_acmp_neg : 1; /**< Comparison result falling edge interrupt status. */ + unsigned int intr_acmp_pos : 1; /**< Interrupt status on the rising edge of comparison result. */ + unsigned int reserved : 29; + } BIT; +} volatile ACMP_INTR_REG; + + +/** + * @brief Masked ACMP interrupt status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int intr_acmp_edge_msk : 1; /**< Status of comparison result reversal edge masked interrupt. */ + unsigned int intr_acmp_neg_msk : 1; /**< Int status after falling edge of comparison result is masked. */ + unsigned int intr_acmp_pos_msk : 1; /**< Int status after rising edge of comparison result is masked. */ + unsigned int reserved : 29; + } BIT; +} volatile ACMP_INTR_MSK_REG; + + +/** + * @brief ACMP interrupt mask. + */ +typedef union { + unsigned int reg; + struct { + unsigned int intr_acmp_edge_mask : 1; /**< Comparison result reversal edge interrupt mask register: + 0: mask interrupts. + 1: not masked. */ + unsigned int intr_acmp_neg_mask : 1; /**< Comparison result falling edge interrupt mask register: + 0: mask interrupts. + 1: not masked. */ + unsigned int intr_acmp_pos_mask : 1; /**< Comparison result rising edge interrupt mask register: + 0: mask interrupts. + 1: not masked. */ + unsigned int reserved : 29; + } BIT; +} volatile ACMP_INTR_MASK_REG; + + +/** + * @brief ACMP result register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cmp_ana_rslt : 1; /**< Original comparison result. */ + unsigned int cmp_filter_rslt : 1; /**< Filtered result of the comparator. */ + unsigned int cmp_blk_rslt : 1; /**< Result after the comparator is masked. */ + unsigned int reserved : 29; + } BIT; +} volatile ACMP_RSLT_REG; + +/** + * @brief ACMP enable delay register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_acmp_en_dly : 8; /**< Indicates the delay for enabling ACMP (us). */ + unsigned int reserved : 24; + } BIT; +} volatile ACMP_EN_DLY_REG; + +/** + * @brief ACMP test register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int da_acmp_test_enh : 1; /**< Test enable signal: + 0: disabled; + 1: enabled. */ + unsigned int da_acmp_test_sel : 8; /**< Test signal strobe. */ + unsigned int reserved : 23; + } BIT; +} volatile ACMP_TEST_REG; + + +/** + * @brief ACMP TRIM register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int da_acmp_trim : 8; /**< ACMP TIRM register. */ + unsigned int reserved : 24; + } BIT; +} volatile ACMP_TRIM_REG; + + +/** + * @brief ACMP reserved register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int da_acmp_rsv : 2; /**< Reserved comparator register: + <1: 0>: The hysteresis voltage is selected. */ + unsigned int reserved : 30; + } BIT; +} volatile ACMP_RSV_REG; + +/** + * @brief ACMP registers definition structure. + */ +typedef struct _ACMP_RegStruct { + ACMP_CTRL_REG0 ACMP_CTRL0; /**< ACMP control register 0. Offset address: 0x00000000U. */ + ACMP_CTRL_REG1 ACMP_CTRL1; /**< ACMP control register 1. Offset address: 0x00000004U. */ + ACMP_CTRL_REG2 ACMP_CTRL2; /**< ACMP control register 2. Offset address: 0x00000008U. */ + char space0[52]; + ACMP_CTRL_REG3 ACMP_CTRL3; /**< ACMP filtering control register. Offset address: 0x00000040U. */ + ACMP_CTRL_REG4 ACMP_CTRL4; /**< ACMP mask control register. Offset address: 0x00000044U. */ + char space1[8]; + ACMP_INTR_REG ACMP_INTR; /**< ACMP interrupt raw status register. Offset address: 0x00000050U. */ + ACMP_INTR_MSK_REG ACMP_INTR_MSK; /**< Masked ACMP interrupt status register. Offset address: 0x00000054U. */ + ACMP_INTR_MASK_REG ACMP_INTR_MASK; /**< ACMP interrupt mask register. Offset address: 0x00000058U. */ + char space2[20]; + ACMP_RSLT_REG ACMP_RSLT; /**< ACMP result register. Offset address: 0x00000070U. */ + char space3[12]; + ACMP_EN_DLY_REG ACMP_EN_DLY; /**< ACMP enable delay register. Offset address: 0x00000080U. */ + char space4[4]; + ACMP_TRIM_REG ACMP_TRIM; /**< ACMP TRIM register. Offset address: 0x00000088U. */ + ACMP_RSV_REG ACMP_RSV; /**< ACMP reserved register. Offset address: 0x0000008CU. */ +} volatile ACMP_RegStruct; + +/* Parameter Check------------------------------------------------------------------ */ +/** + * @brief Verify ACMP output polarity configuration. + * @param polarity: ACMP output polarity + * @retval true + * @retval false + */ +static inline bool IsACMPOutputPolarity(ACMP_OutputPolarity polarity) +{ + return ((polarity == ACMP_OUT_NOT_INVERT) || (polarity == ACMP_OUT_INVERT)); +} + +/** + * @brief Verify ACMP input P number. + * @param pNumber: ACMP output source select + * @retval true + * @retval false + */ +static inline bool IsACMPInputPNumber(ACMP_InputPSel pNumber) +{ + return (pNumber <= ACMP_INPUT_P_SELECT5); +} + +/** + * @brief Verify ACMP input N number. + * @param NNumber: ACMP output source select + * @retval true + * @retval false + */ +static inline bool IsACMPInputNNumber(ACMP_InputNSel NNumber) +{ + return (NNumber <= ACMP_INPUT_N_SELECT5); +} + +/** + * @brief Verify ACMP blocking source type. + * @param BlkingSrcType: ACMP output source select + * @retval true + * @retval false + */ +static inline bool IsACMPBlkingSrcType(ACMP_BlkingSrcType BlkingSrcType) +{ + return (BlkingSrcType <= ACMP_BLKING_SRC_APT3); +} + +/** + * @brief Verify ACMP output result selection + * @param resultSelection: ACMP output source selection. + * @retval true + * @retval false + */ +static inline bool IsACMPResultSeletion(ACMP_ResultSelect resultSelection) +{ + return (resultSelection <= ACMP_RESULT_FILTER_BLOCK); +} + +/* Direct configuration layer ------------------------------------------------*/ +/** + * @brief Set input switch + * @param acmpx: ACMP register base address. + * @param inputP: ACMP inputP selection. @ref ACMP_VinSel + * @param inputN: ACMP inputN selection. @ref ACMP_VinSel + * @retval None. + */ +static inline void DCL_ACMP_SetInputSwith(ACMP_RegStruct *acmpx, ACMP_InputPSel inputP, ACMP_InputNSel inputN) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + ACMP_PARAM_CHECK_NO_RET(inputP >= ACMP_INPUT_P_SELECT0); + ACMP_PARAM_CHECK_NO_RET(inputP <= ACMP_INPUT_P_SELECT5); + ACMP_PARAM_CHECK_NO_RET(inputN >= ACMP_INPUT_N_SELECT0); + ACMP_PARAM_CHECK_NO_RET(inputN <= ACMP_INPUT_N_SELECT5); + acmpx->ACMP_CTRL1.BIT.da_acmp_input_nsel = inputN; /* Input port on the P side. */ + acmpx->ACMP_CTRL1.BIT.da_acmp_input_psel = inputP; /* Input port on the N side. */ +} + +/** + * @brief ACMP output(deshark and synchronize) source. + * @param acmp: ACMP register base address. + * @param resultSelection: config value. @ref ACMP_ResultSelect + * @retval None. + */ +static inline void DCL_ACMP_SetCmpOutputSrc(ACMP_RegStruct *acmpx, ACMP_ResultSelect resultSelection) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + ACMP_PARAM_CHECK_NO_RET(resultSelection >= ACMP_RESULT_SIMULATION); + ACMP_PARAM_CHECK_NO_RET(resultSelection <= ACMP_RESULT_FILTER_BLOCK); + acmpx->ACMP_CTRL2.BIT.cfg_acmp_out_sel = resultSelection; /* ACMP output result select. */ +} + +/** + * @brief Comparator enable blking function + * @param acmpx: ACMP register base address. + * @retval None. + */ +static inline void DCL_ACMP_EnableCmpBlking(ACMP_RegStruct *acmpx) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + acmpx->ACMP_CTRL4.BIT.cfg_acmp_blk_en = BASE_CFG_ENABLE; +} + +/** + * @brief Comparator disable blking function + * @param acmpx: ACMP register base address. + * @retval None. + */ +static inline void DCL_ACMP_DisableCmpBlking(ACMP_RegStruct *acmpx) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + acmpx->ACMP_CTRL4.BIT.cfg_acmp_blk_en = BASE_CFG_DISABLE; +} + +/** + * @brief Enable the software masking window. + * @param acmpx: ACMP register base address. + * @retval None. + */ +static inline void DCL_ACMP_EnableSoftBlking(ACMP_RegStruct *acmpx) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + acmpx->ACMP_CTRL4.BIT.cfg_acmp_blk_win = BASE_CFG_ENABLE; +} + +/** + * @brief Disable the software masking window. + * @param acmpx: ACMP register base address. + * @retval None. + */ +static inline void DCL_ACMP_DisableSoftBlking(ACMP_RegStruct *acmpx) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + acmpx->ACMP_CTRL4.BIT.cfg_acmp_blk_win = BASE_CFG_DISABLE; +} + +/** + * @brief Set blking source. + * @param acmpx: ACMP register base address. + * @param source: Source of blking. @ref ACMP_BlkingSrcType + * @retval None. + */ +static inline void DCL_ACMP_SetCmpBlkingSource(ACMP_RegStruct *acmpx, ACMP_BlkingSrcType source) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + ACMP_PARAM_CHECK_NO_RET(source >= ACMP_BLKING_SRC_SOFT); + ACMP_PARAM_CHECK_NO_RET(source <= ACMP_BLKING_SRC_APT3); + acmpx->ACMP_CTRL4.BIT.cfg_acmp_blk_sel = source; +} + +/** + * @brief Set comparator hysteresis voltage. + * @param acmpx: ACMP register base address. + * @param volSelect: Hysteresis voltage selection. @ref ACMP_HystVol + * @retval None. + */ +static inline void DCL_ACMP_SetCmpHysteresisVoltage(ACMP_RegStruct *acmpx, ACMP_HystVol volSelect) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + ACMP_PARAM_CHECK_NO_RET(volSelect >= ACMP_HYS_VOL_ZERO); + ACMP_PARAM_CHECK_NO_RET(volSelect <= ACMP_HYS_VOL_30MV); + acmpx->ACMP_RSV.BIT.da_acmp_rsv = volSelect; +} + +/** + * @brief Set comparator's output polarity + * @param acmp: ACMP register base address. + * @param polarity: output polarity. @ref ACMP_OutputPolarity + * @retval None. + */ +static inline void DCL_ACMP_SetCmpOutputPolarity(ACMP_RegStruct *acmpx, ACMP_OutputPolarity polarity) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + ACMP_PARAM_CHECK_NO_RET(polarity >= ACMP_OUT_NOT_INVERT); + ACMP_PARAM_CHECK_NO_RET(polarity <= ACMP_OUT_INVERT); + acmpx->ACMP_CTRL2.BIT.cfg_acmp_out_inv = polarity; +} + +/** + * @brief Reading compare result after blocking. + * @param acmp: ACMP register base address. + * @retval Blocked result. + */ +static inline unsigned int DCL_ACMP_GetCmpOutValueAfterBlking(ACMP_RegStruct *acmpx) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + return acmpx->ACMP_RSLT.BIT.cmp_blk_rslt; +} + +/** + * @brief Reading compare result after filtering. + * @param acmp: ACMP register base address. + * @retval filtered result. + */ +static inline unsigned int DCL_ACMP_GetCmpOutValueAfterFilter(ACMP_RegStruct *acmpx) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + return acmpx->ACMP_RSLT.BIT.cmp_filter_rslt; +} + +/** + * @brief Reading original compare result + * @param acmp: ACMP register base address. + * @retval original result. + */ +static inline unsigned int DCL_ACMP_GetCmpOutValueOriginal(ACMP_RegStruct *acmpx) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + return acmpx->ACMP_RSLT.BIT.cmp_ana_rslt; +} + +/** + * @brief Set deshark step by clock. + * @param acmp: ACMP register base address. + * @param step: ACMP filter step. + * @retval None. + */ +static inline void DCL_ACMP_SetFilterStep(ACMP_RegStruct *acmpx, unsigned short step) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + ACMP_PARAM_CHECK_NO_RET(step <= ACMP_FILTER_STEP_MAX_VALUE); + acmpx->ACMP_CTRL3.BIT.cfg_acmp_filter_step = step; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/acmp/src/acmp.c b/vendor/xinlingyu_92_3061M/Project/drivers/acmp/src/acmp.c new file mode 100644 index 0000000000000000000000000000000000000000..4112f18c84520c2ca3f6838567e8dbde43c1d9f0 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/acmp/src/acmp.c @@ -0,0 +1,313 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file acmp.c + * @author MCU Driver Team. + * @brief ACMP HAL level module driver. + * This file provides firmware functions to manage the following + * functionalities of ACMP. + * + Comparator's Initialization and de-initialization functions + * + Set Comparator's hysteresis voltage function + * + Set software blking valid function + * + Set software blking invalid function + */ +#include "acmp.h" +#include "assert.h" + + +/* Define -------------- */ +#define ACMP_INTERRUPT_ENABLE 0b111 +#define ACMP_POS_INTERUPT 0b100 +#define ACMP_NEG_INTERUPT 0b010 +#define ACMP_EDGE_INTERRUPT 0b001 + + +/** + * @brief Input and output initialization of comparator + * @param acmpHandle: ACMP handle. + * @retval None. + */ +static void ACMP_InputOutputInit(ACMP_Handle *acmpHandle) +{ + ACMP_ASSERT_PARAM(acmpHandle != NULL); + ACMP_ASSERT_PARAM(IsACMPInstance(acmpHandle->baseAddress)); + ACMP_PARAM_CHECK_NO_RET(IsACMPOutputPolarity(acmpHandle->inOutConfig.polarity)); + /* Check input multiplexing selection and input switch selection */ + ACMP_PARAM_CHECK_NO_RET(IsACMPInputPNumber(acmpHandle->inOutConfig.inputPNum)); + ACMP_PARAM_CHECK_NO_RET(IsACMPInputNNumber(acmpHandle->inOutConfig.inputNNum)); + /* input positive selection */ + acmpHandle->baseAddress->ACMP_CTRL1.BIT.da_acmp_input_psel = acmpHandle->inOutConfig.inputPNum; + /* input negative selection */ + acmpHandle->baseAddress->ACMP_CTRL1.BIT.da_acmp_input_nsel = acmpHandle->inOutConfig.inputNNum; + /* output polarity selection */ + acmpHandle->baseAddress->ACMP_CTRL2.BIT.cfg_acmp_out_inv = acmpHandle->inOutConfig.polarity; +} + +/** + * @brief Filter initialization of comparator + * @param acmpHandle: ACMP handle. + * @retval None. + */ +static void ACMP_FilterInit(ACMP_Handle *acmpHandle) +{ + ACMP_ASSERT_PARAM(acmpHandle != NULL); + ACMP_ASSERT_PARAM(IsACMPInstance(acmpHandle->baseAddress)); + unsigned short blkingSrc; + switch (acmpHandle->filterCtrl.filterMode) { + case ACMP_FILTER_NONE: /* The filtering function is not applicable. */ + acmpHandle->baseAddress->ACMP_CTRL3.BIT.cfg_acmp_filter_en = BASE_CFG_DISABLE; /* Disable filtering */ + acmpHandle->baseAddress->ACMP_CTRL4.BIT.cfg_acmp_blk_en = BASE_CFG_DISABLE; /* Disable blocking */ + + acmpHandle->baseAddress->ACMP_CTRL2.BIT.cfg_acmp_out_sel = 0x0; /* 0x0: Output raw comparison result. */ + break; + case ACMP_FILTER_BLOCK: /* Use the blockinng function. */ + acmpHandle->baseAddress->ACMP_CTRL4.BIT.cfg_acmp_blk_en = BASE_CFG_ENABLE; /* Enable blocking. */ + blkingSrc = acmpHandle->filterCtrl.blkingSrcSelect; + acmpHandle->baseAddress->ACMP_CTRL4.BIT.cfg_acmp_blk_sel = blkingSrc; /* Setting Blking source */ + if (blkingSrc == ACMP_BLKING_SRC_SOFT) { + /* Sets the polarity of the window.. */ + acmpHandle->baseAddress->ACMP_CTRL4.BIT.cfg_acmp_blk_pol_sel = acmpHandle->filterCtrl.blkingPorty; + } else { + /* Blocking source from apt window. */ + acmpHandle->baseAddress->ACMP_CTRL4.BIT.cfg_acmp_blk_pol_sel = BASE_CFG_ENABLE; + acmpHandle->baseAddress->ACMP_CTRL4.BIT.cfg_acmp_blk_rslt_pol = BASE_CFG_DISABLE; + } + acmpHandle->baseAddress->ACMP_CTRL2.BIT.cfg_acmp_out_sel = 0x2; /* 0x2: Outputs digital filtered and + masked comparison results */ + break; + case ACMP_FILTER_FILTER: /* Set the filtering function. */ + acmpHandle->baseAddress->ACMP_CTRL3.BIT.cfg_acmp_filter_en = BASE_CFG_ENABLE; /* Enable filtering. */ + /* Filter length setting. */ + acmpHandle->baseAddress->ACMP_CTRL3.BIT.cfg_acmp_filter_step = acmpHandle->filterCtrl.filterStep; + + acmpHandle->baseAddress->ACMP_CTRL2.BIT.cfg_acmp_out_sel = 0x1; /* 0x1: Outputs filtering result. */ + break; + case ACMP_FILTER_BOTH: /* Use filtering and shielding functions. */ + acmpHandle->baseAddress->ACMP_CTRL3.BIT.cfg_acmp_filter_en = BASE_CFG_ENABLE; /* Enable filtering. */ + acmpHandle->baseAddress->ACMP_CTRL3.BIT.cfg_acmp_filter_step = acmpHandle->filterCtrl.filterStep; + + acmpHandle->baseAddress->ACMP_CTRL4.BIT.cfg_acmp_blk_en = BASE_CFG_ENABLE; /* Enable blocking. */ + blkingSrc = acmpHandle->filterCtrl.blkingSrcSelect; + acmpHandle->baseAddress->ACMP_CTRL4.BIT.cfg_acmp_blk_sel = blkingSrc; /* Setting blocking source. */ + if (blkingSrc == ACMP_BLKING_SRC_SOFT) { + /* Setting Blking source from software. */ + acmpHandle->baseAddress->ACMP_CTRL4.BIT.cfg_acmp_blk_pol_sel = acmpHandle->filterCtrl.blkingPorty; + } else { + /* Blocking source from apt window. */ + acmpHandle->baseAddress->ACMP_CTRL4.BIT.cfg_acmp_blk_pol_sel = BASE_CFG_ENABLE; + acmpHandle->baseAddress->ACMP_CTRL4.BIT.cfg_acmp_blk_rslt_pol = BASE_CFG_DISABLE; + } + acmpHandle->baseAddress->ACMP_CTRL2.BIT.cfg_acmp_out_sel = 0x2; /* 0x2: Outputs digital filtered and + masked comparison results */ + break; + default: + acmpHandle->baseAddress->ACMP_CTRL3.BIT.cfg_acmp_filter_en = BASE_CFG_DISABLE; /* Disable filtering. */ + acmpHandle->baseAddress->ACMP_CTRL4.BIT.cfg_acmp_blk_en = BASE_CFG_DISABLE; /* Disable blocking. */ + break; + } +} + +/** + * @brief Comparator HAL Init + * @param acmpHandle: ACMP handle. + * @retval BASE_StatusType: OK, ERROR + */ +BASE_StatusType HAL_ACMP_Init(ACMP_Handle *acmpHandle) +{ + ACMP_ASSERT_PARAM(acmpHandle != NULL); + ACMP_ASSERT_PARAM(IsACMPInstance(acmpHandle->baseAddress)); + /* Parameter macro check. */ + ACMP_PARAM_CHECK_WITH_RET(acmpHandle->hysteresisVol >= ACMP_HYS_VOL_ZERO, BASE_STATUS_ERROR); + ACMP_PARAM_CHECK_WITH_RET(acmpHandle->hysteresisVol <= ACMP_HYS_VOL_30MV, BASE_STATUS_ERROR); + ACMP_PARAM_CHECK_WITH_RET(acmpHandle->filterCtrl.filterStep >= 0, BASE_STATUS_ERROR); + ACMP_PARAM_CHECK_WITH_RET(acmpHandle->filterCtrl.filterStep <= ACMP_FILTER_STEP_MAX_VALUE, BASE_STATUS_ERROR); + ACMP_PARAM_CHECK_WITH_RET(IsACMPBlkingSrcType(acmpHandle->filterCtrl.blkingSrcSelect), BASE_STATUS_ERROR); + /* Enable ACMP. */ + acmpHandle->baseAddress->ACMP_CTRL0.BIT.da_acmp_enh = BASE_CFG_ENABLE; + /* Enable ACMP interrupt. */ + if (acmpHandle->interruptEn == BASE_CFG_SET) { + acmpHandle->baseAddress->ACMP_INTR_MASK.reg = ACMP_INTERRUPT_ENABLE; /* Configure acmp interrupt. */ + } else { + acmpHandle->baseAddress->ACMP_INTR_MASK.reg = BASE_CFG_UNSET; /* Disable acmp interrupt. */ + } + /* ACMP input and output settings. */ + ACMP_InputOutputInit(acmpHandle); + /* ACMP comparison filtering function. */ + ACMP_FilterInit(acmpHandle); + /* Set hysteresis voltage */ + HAL_ACMP_SetHystVol(acmpHandle, acmpHandle->hysteresisVol); + + BASE_FUNC_DELAY_US(150); /* After the configuration is complete, a delay of 150 us is required. */ + return BASE_STATUS_OK; +} + +/** + * @brief Comparator HAL DeInit + * @param acmpHandle: ACMP handle. + * @retval BASE_StatusType: OK, ERROR + */ +BASE_StatusType HAL_ACMP_DeInit(ACMP_Handle *acmpHandle) +{ + ACMP_ASSERT_PARAM(acmpHandle != NULL); + ACMP_ASSERT_PARAM(IsACMPInstance(acmpHandle->baseAddress)); + acmpHandle->baseAddress->ACMP_CTRL0.reg = BASE_CFG_DISABLE; /* Disable ACMP. */ + acmpHandle->baseAddress->ACMP_CTRL1.reg = BASE_CFG_DISABLE; /* Clears the input and output status. */ + acmpHandle->baseAddress->ACMP_CTRL2.reg = BASE_CFG_DISABLE; /* Clears the comparison result selection. */ + acmpHandle->baseAddress->ACMP_INTR.reg = BASE_CFG_DISABLE; /* Clear all interrrupt. */ + acmpHandle->userCallBack.AcmpEdgedCallBack = NULL; /* Clears all user callback functions. */ + acmpHandle->userCallBack.AcmpNegativeCallBack = NULL; + acmpHandle->userCallBack.AcmpPositiveCallBack = NULL; + return BASE_STATUS_OK; +} + +/** + * @brief Set hysteresis Voltage + * @param acmpHandle: ACMP handle. + * @param voltage: hysteresis voltage to be set. @ref ACMP_HystVol + * @retval None. + */ +void HAL_ACMP_SetHystVol(ACMP_Handle *acmpHandle, ACMP_HystVol voltage) +{ + ACMP_ASSERT_PARAM(acmpHandle != NULL); + ACMP_ASSERT_PARAM(IsACMPInstance(acmpHandle->baseAddress)); + ACMP_PARAM_CHECK_NO_RET(voltage >= ACMP_HYS_VOL_ZERO); + ACMP_PARAM_CHECK_NO_RET(voltage <= ACMP_HYS_VOL_30MV); + acmpHandle->baseAddress->ACMP_RSV.BIT.da_acmp_rsv = voltage; /* Hysteresis voltage setting. */ +} + +/** + * @brief Set blocking valid + * @param acmpHandle: ACMP handle. + * @retval None. + */ +void HAL_ACMP_BlkingValid(ACMP_Handle *acmpHandle) +{ + ACMP_ASSERT_PARAM(acmpHandle != NULL); + ACMP_ASSERT_PARAM(IsACMPInstance(acmpHandle->baseAddress)); + /* Enable Blocking function. */ + acmpHandle->baseAddress->ACMP_CTRL4.BIT.cfg_acmp_blk_en = BASE_CFG_ENABLE; +} + +/** + * @brief Set blocking invalid + * @param acmpHandle: ACMP handle. + * @retval None. + */ +void HAL_ACMP_BlkingInvalid(ACMP_Handle *acmpHandle) +{ + ACMP_ASSERT_PARAM(acmpHandle != NULL); + ACMP_ASSERT_PARAM(IsACMPInstance(acmpHandle->baseAddress)); + acmpHandle->baseAddress->ACMP_CTRL4.BIT.cfg_acmp_blk_en = BASE_CFG_DISABLE; /* Disable blocking function. */ +} + +/** + * @brief Sets the output result of ACMP. + * @param acmpHandle: ACMP handle. + * @param resultSelect: ACMP result output options. + * @retval BASE_StatusType: OK, ERROR. + */ +BASE_StatusType HAL_ACMP_ResultSelect(ACMP_Handle *acmpHandle, ACMP_ResultSelect resultSelect) +{ + ACMP_ASSERT_PARAM(acmpHandle != NULL); + ACMP_ASSERT_PARAM(IsACMPInstance(acmpHandle->baseAddress)); + ACMP_PARAM_CHECK_WITH_RET(IsACMPResultSeletion(resultSelect), BASE_STATUS_ERROR); + /* Output result selection of the comparator. */ + switch (resultSelect) { + case ACMP_RESULT_SIMULATION: + acmpHandle->baseAddress->ACMP_CTRL2.BIT.cfg_acmp_out_sel = 0x0; /* 0x0: Original comparison results. */ + break; + case ACMP_RESULT_FILTER: + acmpHandle->baseAddress->ACMP_CTRL2.BIT.cfg_acmp_out_sel = 0x1; /* 0x1: Resulter after filtering. */ + break; + case ACMP_RESULT_FILTER_BLOCK: + acmpHandle->baseAddress->ACMP_CTRL2.BIT.cfg_acmp_out_sel = 0x2; /* 0x2: Resulter after filtering + and blocking. */ + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief ACMP Interrupt service processing function. + * @param handle ACMP handle. + * @retval None. + */ +void HAL_ACMP_IrqHandler(void *handle) +{ + ACMP_ASSERT_PARAM(handle != NULL); + ACMP_Handle *acmpHandle = (ACMP_Handle *)handle; + ACMP_ASSERT_PARAM(IsACMPInstance(acmpHandle->baseAddress)); + /* Check interrupt type */ + if (acmpHandle->baseAddress->ACMP_INTR_MSK.BIT.intr_acmp_pos_msk == BASE_CFG_ENABLE) { + /* Rising Edge Interrupt. */ + acmpHandle->baseAddress->ACMP_INTR.reg = ACMP_POS_INTERUPT; /* Clears the rising edge interrupt. */ + /* Call the rising edge user interrupt function. */ + if (acmpHandle->userCallBack.AcmpPositiveCallBack != NULL) { + acmpHandle->userCallBack.AcmpPositiveCallBack(acmpHandle); + } + } + if (acmpHandle->baseAddress->ACMP_INTR_MSK.BIT.intr_acmp_neg_msk == BASE_CFG_ENABLE) { + /* Falling Edge Interrupt. */ + acmpHandle->baseAddress->ACMP_INTR.reg = ACMP_NEG_INTERUPT; /* Clears falling Edge Interrupt. */ + /* Call the falling edge user interrupt function. */ + if (acmpHandle->userCallBack.AcmpNegativeCallBack != NULL) { + acmpHandle->userCallBack.AcmpNegativeCallBack(acmpHandle); + } + } + if (acmpHandle->baseAddress->ACMP_INTR_MSK.BIT.intr_acmp_edge_msk == BASE_CFG_ENABLE) { + /* Flip edge interrupt. */ + acmpHandle->baseAddress->ACMP_INTR.reg = ACMP_EDGE_INTERRUPT; /* Clears Flip edge interrupt. */ + /* Call flip edge user interrupt function. */ + if (acmpHandle->userCallBack.AcmpEdgedCallBack != NULL) { + acmpHandle->userCallBack.AcmpEdgedCallBack(acmpHandle); + } + } + return; +} + +/** + * @brief Register the callback function of ACMP handle. + * @param acmpHandle Acmp Handle + * @param typeID CallBack function type of user, @ref ACMP_CallBackFun_Type + * @param callBackFunc CallBack function of user, @ref ACMM_CallBackType + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Parameter check fail + */ +BASE_StatusType HAL_ACMP_RegisterCallBack(ACMP_Handle *acmpHandle, ACMP_CallBackFun_Type typeID, + ACMP_CallBackType callBackFunc) +{ + ACMP_ASSERT_PARAM(acmpHandle != NULL); + ACMP_ASSERT_PARAM(callBackFunc != NULL); + ACMP_ASSERT_PARAM(IsACMPInstance(acmpHandle->baseAddress)); + /* Registers user callback function. */ + switch (typeID) { + case ACMP_POS_INT: /* Register rising edge user callback function */ + acmpHandle->userCallBack.AcmpPositiveCallBack = callBackFunc; + break; + case ACMP_NEG_INT: /* Register failing edge user callback function */ + acmpHandle->userCallBack.AcmpNegativeCallBack = callBackFunc; + break; + case ACMP_EDGE_INT: /* Register fliping edge user callback function */ + acmpHandle->userCallBack.AcmpEdgedCallBack = callBackFunc; + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/acmp/src/acmp_ex.c b/vendor/xinlingyu_92_3061M/Project/drivers/acmp/src/acmp_ex.c new file mode 100644 index 0000000000000000000000000000000000000000..3ccc008a83dca573ef5ba0210dd053a66fa4a23e --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/acmp/src/acmp_ex.c @@ -0,0 +1,45 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file acmp_ex.c + * @author MCU Driver Team + * @brief ACMP module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the acmp. + * + Set ACMP trim value functions. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "acmp_ex.h" + +/* Macro definitions ---------------------------------------------------------*/ +#define TRIM_MAX_VALUE 255 + +/** + * @brief Trim value setting + * @param acmpHandle acmp handle. + * @param trimValue trim value. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_ACMP_SetTrimValueEx(ACMP_Handle *acmpHandle, unsigned char trimValue) +{ + ACMP_ASSERT_PARAM(acmpHandle != NULL); + ACMP_ASSERT_PARAM(IsACMPInstance(acmpHandle->baseAddress)); + ACMP_PARAM_CHECK_WITH_RET((trimValue < TRIM_MAX_VALUE), BASE_STATUS_ERROR); + acmpHandle->baseAddress->ACMP_TRIM.BIT.da_acmp_trim = trimValue; /* Trim value setting. */ + return BASE_STATUS_OK; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/adc/common/inc/adc.h b/vendor/xinlingyu_92_3061M/Project/drivers/adc/common/inc/adc.h new file mode 100644 index 0000000000000000000000000000000000000000..c32b8cae599b02f6af3e520218b617685a2257c6 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/adc/common/inc/adc.h @@ -0,0 +1,128 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file adc.h + * @author MCU Driver Team + * @brief ADC module driver + * @details This file provides functions declaration of the ADC, + * + ADC initialization function. + * + Start ADC sample and conversion. + * + Start ADC sample and conversion with interrupt. + * + Start ADC sample and conversion with DMA. + * + Start ADC sample and conversion synchronously. + * + Query the ADC conversion result. + * + Single channel and multichannel software trigger functions. + * + Interrupt callback function and user registration function. + * This file also provides the definition of the ADC handle structure. + */ + +/* Macro definitions */ +#ifndef McuMagicTag_ADC_H +#define McuMagicTag_ADC_H + +#include "adc_ip.h" +#include "dma.h" +#include "dac.h" +#include "interrupt.h" + +/** + * @defgroup ADC ADC + * @brief ADC module. + * @{ + */ + +/** + * @defgroup ADC_Common ADC Common + * @brief ADC common external module. + * @{ + */ + +/** + * @defgroup ADC_Handle_Definition ADC Handle Definition + * @{ + */ + +/** + * @brief The definition of the ADC handle structure. + */ +typedef struct _ADC_Handle { + ADC_RegStruct *baseAddress; /**< ADC registers base address */ + ADC_PriorityMode socPriority; /**< ADC clock divider */ + DMA_Handle *dmaHandle; /**< ADC_DMA control */ + unsigned int adcDmaChn; /**< ADC_DMA channel */ + ADC_OverState overState; /**< ADC overflow state */ + struct { + unsigned short finishMode; /**< sample finish mode, defined in ADC_SOCFinishMode */ + } ADC_SOCxParam[SOC_MAX_NUM]; + struct { + unsigned short socxFinish; /**< After each SOC is completed, the corresponding bit is set as 1 */ + } ADC_IntxParam[INT_MAX_NUM]; + ADC_UserCallBack userCallBack; /**< ADC User Callback Function */ + ADC_ExtendHandle handleEx; /**< ADC extend handle */ +} ADC_Handle; + +/** + * @brief The definition of the ADC callback function. + */ +typedef void (* ADC_CallbackType)(void *handle); + +/** + * @} + */ + +/** + * @defgroup ADC_API_Declaration ADC HAL API + * @{ + */ +BASE_StatusType HAL_ADC_Init(ADC_Handle *adcHandle); +BASE_StatusType HAL_ADC_Deinit(ADC_Handle *adcHandle); +BASE_StatusType HAL_ADC_ConfigureSoc(ADC_Handle *adcHandle, ADC_SOCNumber soc, SOC_Param *socParam); +BASE_StatusType HAL_ADC_StartDma(ADC_Handle *adcHandle, unsigned int startSoc, + unsigned int endSoc, unsigned int *saveData); +BASE_StatusType HAL_ADC_StartIt(ADC_Handle *adcHandle); +BASE_StatusType HAL_ADC_SoftTrigMultiSample(ADC_Handle *adcHandle, ADC_SoftMultiTrig syncTrig); +BASE_StatusType HAL_ADC_SoftTrigSample(ADC_Handle *adcHandle, unsigned int soc); +unsigned int HAL_ADC_GetConvResult(ADC_Handle *adcHandle, unsigned int soc); +BASE_StatusType HAL_ADC_CheckSocFinish(ADC_Handle *adcHandle, unsigned int soc); +void HAL_ADC_RegisterCallBack(ADC_Handle *adcHandle, ADC_CallbackFunType typeID, ADC_CallbackType pCallback); +BASE_StatusType HAL_ADC_InitForVdda(ADC_RegStruct *adcx, ADC_SOCNumber soc, DAC_RegStruct *dacx, bool useDac); +float HAL_ADC_GetVddaByDac(ADC_RegStruct *adcx, ADC_SOCNumber soc, DAC_RegStruct *dacx, bool useDac); +unsigned int HAL_ADC_GetTransResultByVdda(ADC_RegStruct *adcx, ADC_SOCNumber soc, float vdda); +#if defined (CHIP_3061MNPICA) || defined (CHIP_3061MNPIKA) || defined (CHIP_3061MNPIC8) || defined (CHIP_3061MNPIK8) +void HAL_ADC_IrqHandlerInt0(void *handle); +#endif +void HAL_ADC_IrqHandlerInt1(void *handle); +void HAL_ADC_IrqHandlerInt2(void *handle); +void HAL_ADC_IrqHandlerInt3(void *handle); +#if defined (CHIP_3065HRPIRZ) || defined (CHIP_3065HRPICZ) || defined (CHIP_3061HRPIKZ) || \ + defined (AU302PDF51) || defined (AU302NDF51) || defined (AU301LDF51) || defined (CHIP_3065ARPIRZ) +void HAL_ADC_IrqHandlerInt4(void *handle); +#endif +void HAL_ADC_IrqHandlerOver(void *handle); +void HAL_ADC_IrqHandlerAllEvent(void *handle); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/adc/inc/adc_ex.h b/vendor/xinlingyu_92_3061M/Project/drivers/adc/inc/adc_ex.h new file mode 100644 index 0000000000000000000000000000000000000000..afe259321ae32bf5ae78674c44d81bdaff4689a2 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/adc/inc/adc_ex.h @@ -0,0 +1,65 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file adc_ex.h + * @author MCU Driver Team + * @brief ADC module driver + * @details This file provides functions declaration of the ADC extend function. + */ + +/* Macro definitions */ +#ifndef McuMagicTag_ADC_EX_H +#define McuMagicTag_ADC_EX_H + +#include "adc.h" +#define ADC_ANA_MUX ((ADC_ANA_MUX_APB_RegStruct *)0x18003000) + +/** + * @addtogroup ADC_IP + * @{ + */ + +/** + * @defgroup ADC_EX_API_Declaration ADC HAL API EX + * @{ + */ +BASE_StatusType HAL_ADC_EnableSocCotinueModeEx(ADC_Handle *adcHandle, ADC_SOCNumber soc); +BASE_StatusType HAL_ADC_DisableSocCotinueModeEx(ADC_Handle *adcHandle, ADC_SOCNumber soc); +BASE_StatusType HAL_ADC_GetControllerStatusEx(ADC_Handle *adcHandle); +BASE_StatusType HAL_ADC_CheckOversamplingFinishEx(ADC_Handle *adcHandle); +unsigned int HAL_ADC_GetOversamplingResultEx(ADC_Handle *adcHandle); +BASE_StatusType HAL_ADC_ConfigureOversamplingEx(ADC_Handle *adcHandle, ADC_SOCNumber soc, ADC_OversamplingParam *param); +BASE_StatusType HAL_ADC_ConfigureWorkModeEx(ADC_Handle *adcHandle, ADC_WorkMode mode); +BASE_StatusType HAL_ADC_EnablePPBxEventIntEx(ADC_Handle *adcHandle); +BASE_StatusType HAL_ADC_DisablePPBxEventIntEx(ADC_Handle *adcHandle); +BASE_StatusType HAL_ADC_ConfigurePPBxEx(ADC_Handle *adcHandle, ADC_SOCNumber soc, ADC_PPBNumber ppb, + PPB_Function *fun); +BASE_StatusType HAL_ADC_SetPPBxOffsetEx(ADC_Handle *adcHandle, ADC_PPBNumber ppb, int offset); +BASE_StatusType HAL_ADC_SetPPBxThresholdEx(ADC_Handle *adcHandle, ADC_PPBNumber ppb, int up, int dn); +BASE_StatusType HAL_ADC_SetPPBxErrorRefEx(ADC_Handle *adcHandle, ADC_PPBNumber ppb, unsigned int ref); +int HAL_ADC_GetPPBxErrorResultEx(ADC_Handle *adcHandle, ADC_PPBNumber ppb); +unsigned int HAL_ADC_GetPPBxDelayCntEx(ADC_Handle *adcHandle, ADC_PPBNumber ppb); +BASE_StatusType HAL_ADC_InitForVddaEx(ADC_RegStruct *adcx, ADC_SOCNumber soc); +float HAL_ADC_GetVddaEx(ADC_RegStruct *adcx, ADC_SOCNumber soc); +/** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/adc/inc/adc_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/adc/inc/adc_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..80882def2f720e53d1c3615f339e5bb8719c2146 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/adc/inc/adc_ip.h @@ -0,0 +1,3052 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file adc_ip.h + * @author MCU Driver Team + * @brief ADC module driver + * @details This file provides DCL functions to manage ADC and Definition of specific parameters. + * + Definition of ADC configuration parameters. + * + ADC register mapping structure. + * + Parameters check functions. + * + Direct configuration layer interface. + */ + +/* Macro definitions */ +#ifndef McuMagicTag_ADC_IP_H +#define McuMagicTag_ADC_IP_H + +#include "baseinc.h" + +#define SOC_MAX_NUM 16 +#define INT_MAX_NUM 4 +#define DMA_OVER_MASK 0x00010000 +#define INT_OVER_MASK 0x0000FFFF +#define EVENT_TYPE 16 + +#ifdef ADC_PARAM_CHECK +#define ADC_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define ADC_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define ADC_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define ADC_ASSERT_PARAM(para) ((void)0U) +#define ADC_PARAM_CHECK_NO_RET(para) ((void)0U) +#define ADC_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +/** + * @addtogroup ADC + * @{ + */ + +/** + * @defgroup ADC_IP ADC_IP + * @brief ADC_IP: adc_v1. + * @{ + */ + +/** + * @defgroup ADC_REG_Definition ADC Register Structure. + * @brief ADC Register Structure Definition. + * @{ + */ +/** + * @brief Define the union ADC_RESULT0_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result0 : 12; /**< SOC0 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT0_REG; + +/** + * @brief Define the union ADC_RESULT1_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result1 : 12; /**< SOC1 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT1_REG; + +/** + * @brief Define the union ADC_RESULT2_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result2 : 12; /**< SOC2 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT2_REG; + +/** + * @brief Define the union ADC_RESULT3_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result3 : 12; /**< SOC3 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT3_REG; + +/** + * @brief Define the union ADC_RESULT4_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result4 : 12; /**< SOC4 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT4_REG; + +/** + * @brief Define the union ADC_RESULT5_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result5 : 12; /**< SOC5 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT5_REG; + +/** + * @brief Define the union ADC_RESULT6_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result6 : 12; /**< SOC6 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT6_REG; + +/** + * @brief Define the union ADC_RESULT7_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result7 : 12; /**< SOC7 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT7_REG; + +/** + * @brief Define the union ADC_RESULT8_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result8 : 12; /**< SOC8 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT8_REG; + +/** + * @brief Define the union ADC_RESULT9_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result9 : 12; /**< SOC9 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT9_REG; + +/** + * @brief Define the union ADC_RESULT10_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result10 : 12; /**< SOC10 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT10_REG; + +/** + * @brief Define the union ADC_RESULT11_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result11 : 12; /**< SOC11 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT11_REG; + +/** + * @brief Define the union ADC_RESULT12_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result12 : 12; /**< SOC12 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT12_REG; + +/** + * @brief Define the union ADC_RESULT13_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result13 : 12; /**< SOC13 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT13_REG; + +/** + * @brief Define the union ADC_RESULT14_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result14 : 12; /**< SOC14 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT14_REG; + +/** + * @brief Define the union ADC_RESULT15_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result15 : 12; /**< SOC15 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT15_REG; + +/** + * @brief Define the union ADC_EOC_FLAG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int eoc0_flag : 1; /**< Status of eoc0. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc1_flag : 1; /**< Status of eoc1. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc2_flag : 1; /**< Status of eoc2. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc3_flag : 1; /**< Status of eoc3. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc4_flag : 1; /**< Status of eoc4. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc5_flag : 1; /**< Status of eoc5. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc6_flag : 1; /**< Status of eoc6. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc7_flag : 1; /**< Status of eoc7. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc8_flag : 1; /**< Status of eoc8. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc9_flag : 1; /**< Status of eoc9. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc10_flag : 1; /**< Status of eoc10. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc11_flag : 1; /**< Status of eoc11. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc12_flag : 1; /**< Status of eoc12. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc13_flag : 1; /**< Status of eoc13. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc14_flag : 1; /**< Status of eoc14. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc15_flag : 1; /**< Status of eoc15. 0: conversion is not complete. 1: conversion is complete */ + unsigned int reserved0 : 16; + } BIT; +} volatile ADC_EOC_FLAG_REG; + +/** + * @brief Define the union ADC_SOC0_CFG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_soc0_ch_sel : 5; /**< Channel selection */ + unsigned int cfg_soc0_samptime_sel : 4; /**< Sampling Period Selection */ + unsigned int cfg_soc0_trig_sel : 5; /**< Trigger source selection */ + unsigned int cfg_soc0_cont_en : 1; /**< Continuous conversion mode enable bit */ + unsigned int reserved0 : 17; + } BIT; +} volatile ADC_SOC0_CFG_REG; + +/** + * @brief Define the union ADC_SOC1_CFG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_soc1_ch_sel : 5; /**< Channel selection */ + unsigned int cfg_soc1_samptime_sel : 4; /**< Sampling Period Selection */ + unsigned int cfg_soc1_trig_sel : 5; /**< Trigger source selection */ + unsigned int cfg_soc1_cont_en : 1; /**< Continuous conversion mode enable bit */ + unsigned int reserved0 : 17; + } BIT; +} volatile ADC_SOC1_CFG_REG; + +/** + * @brief Define the union ADC_SOC2_CFG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_soc2_ch_sel : 5; /**< Channel selection */ + unsigned int cfg_soc2_samptime_sel : 4; /**< Sampling Period Selection */ + unsigned int cfg_soc2_trig_sel : 5; /**< Trigger source selection */ + unsigned int cfg_soc2_cont_en : 1; /**< Continuous conversion mode enable bit */ + unsigned int reserved0 : 17; + } BIT; +} volatile ADC_SOC2_CFG_REG; + +/** + * @brief Define the union ADC_SOC3_CFG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_soc3_ch_sel : 5; /**< Channel selection */ + unsigned int cfg_soc3_samptime_sel : 4; /**< Sampling Period Selection */ + unsigned int cfg_soc3_trig_sel : 5; /**< Trigger source selection */ + unsigned int cfg_soc3_cont_en : 1; /**< Continuous conversion mode enable bit */ + unsigned int reserved0 : 17; + } BIT; +} volatile ADC_SOC3_CFG_REG; + +/** + * @brief Define the union ADC_SOC4_CFG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_soc4_ch_sel : 5; /**< Channel selection */ + unsigned int cfg_soc4_samptime_sel : 4; /**< Sampling Period Selection */ + unsigned int cfg_soc4_trig_sel : 5; /**< Trigger source selection */ + unsigned int cfg_soc4_cont_en : 1; /**< Continuous conversion mode enable bit */ + unsigned int reserved0 : 17; + } BIT; +} volatile ADC_SOC4_CFG_REG; + +/** + * @brief Define the union ADC_SOC5_CFG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_soc5_ch_sel : 5; /**< Channel selection */ + unsigned int cfg_soc5_samptime_sel : 4; /**< Sampling Period Selection */ + unsigned int cfg_soc5_trig_sel : 5; /**< Trigger source selection */ + unsigned int cfg_soc5_cont_en : 1; /**< Continuous conversion mode enable bit */ + unsigned int reserved0 : 17; + } BIT; +} volatile ADC_SOC5_CFG_REG; + +/** + * @brief Define the union ADC_SOC6_CFG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_soc6_ch_sel : 5; /**< Channel selection */ + unsigned int cfg_soc6_samptime_sel : 4; /**< Sampling Period Selection */ + unsigned int cfg_soc6_trig_sel : 5; /**< Trigger source selection */ + unsigned int cfg_soc6_cont_en : 1; /**< Continuous conversion mode enable bit */ + unsigned int reserved0 : 17; + } BIT; +} volatile ADC_SOC6_CFG_REG; + +/** + * @brief Define the union ADC_SOC7_CFG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_soc7_ch_sel : 5; /**< Channel selection */ + unsigned int cfg_soc7_samptime_sel : 4; /**< Sampling Period Selection */ + unsigned int cfg_soc7_trig_sel : 5; /**< Trigger source selection */ + unsigned int cfg_soc7_cont_en : 1; /**< Continuous conversion mode enable bit */ + unsigned int reserved0 : 17; + } BIT; +} volatile ADC_SOC7_CFG_REG; + +/** + * @brief Define the union ADC_SOC8_CFG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_soc8_ch_sel : 5; /**< Channel selection */ + unsigned int cfg_soc8_samptime_sel : 4; /**< Sampling Period Selection */ + unsigned int cfg_soc8_trig_sel : 5; /**< Trigger source selection */ + unsigned int cfg_soc8_cont_en : 1; /**< Continuous conversion mode enable bit */ + unsigned int reserved0 : 17; + } BIT; +} volatile ADC_SOC8_CFG_REG; + +/** + * @brief Define the union ADC_SOC9_CFG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_soc9_ch_sel : 5; /**< Channel selection */ + unsigned int cfg_soc9_samptime_sel : 4; /**< Sampling Period Selection */ + unsigned int cfg_soc9_trig_sel : 5; /**< Trigger source selection */ + unsigned int cfg_soc9_cont_en : 1; /**< Continuous conversion mode enable bit */ + unsigned int reserved0 : 17; + } BIT; +} volatile ADC_SOC9_CFG_REG; + +/** + * @brief Define the union ADC_SOC10_CFG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_soc10_ch_sel : 5; /**< Channel selection */ + unsigned int cfg_soc10_samptime_sel : 4; /**< Sampling Period Selection */ + unsigned int cfg_soc10_trig_sel : 5; /**< Trigger source selection */ + unsigned int cfg_soc10_cont_en : 1; /**< Continuous conversion mode enable bit */ + unsigned int reserved0 : 17; + } BIT; +} volatile ADC_SOC10_CFG_REG; + +/** + * @brief Define the union ADC_SOC11_CFG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_soc11_ch_sel : 5; /**< Channel selection */ + unsigned int cfg_soc11_samptime_sel : 4; /**< Sampling Period Selection */ + unsigned int cfg_soc11_trig_sel : 5; /**< Trigger source selection */ + unsigned int cfg_soc11_cont_en : 1; /**< Continuous conversion mode enable bit */ + unsigned int reserved0 : 17; + } BIT; +} volatile ADC_SOC11_CFG_REG; + +/** + * @brief Define the union ADC_SOC12_CFG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_soc12_ch_sel : 5; /**< Channel selection */ + unsigned int cfg_soc12_samptime_sel : 4; /**< Sampling Period Selection */ + unsigned int cfg_soc12_trig_sel : 5; /**< Trigger source selection */ + unsigned int cfg_soc12_cont_en : 1; /**< Continuous conversion mode enable bit */ + unsigned int reserved0 : 17; + } BIT; +} volatile ADC_SOC12_CFG_REG; + +/** + * @brief Define the union ADC_SOC13_CFG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_soc13_ch_sel : 5; /**< Channel selection */ + unsigned int cfg_soc13_samptime_sel : 4; /**< Sampling Period Selection */ + unsigned int cfg_soc13_trig_sel : 5; /**< Trigger source selection */ + unsigned int cfg_soc13_cont_en : 1; /**< Continuous conversion mode enable bit */ + unsigned int reserved0 : 17; + } BIT; +} volatile ADC_SOC13_CFG_REG; + +/** + * @brief Define the union ADC_SOC14_CFG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_soc14_ch_sel : 5; /**< Channel selection */ + unsigned int cfg_soc14_samptime_sel : 4; /**< Sampling Period Selection */ + unsigned int cfg_soc14_trig_sel : 5; /**< Trigger source selection */ + unsigned int cfg_soc14_cont_en : 1; /**< Continuous conversion mode enable bit */ + unsigned int reserved0 : 17; + } BIT; +} volatile ADC_SOC14_CFG_REG; + +/** + * @brief Define the union ADC_SOC15_CFG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_soc15_ch_sel : 5; /**< Channel selection */ + unsigned int cfg_soc15_samptime_sel : 4; /**< Sampling Period Selection */ + unsigned int cfg_soc15_trig_sel : 5; /**< Trigger source selection */ + unsigned int cfg_soc15_cont_en : 1; /**< Continuous conversion mode enable bit */ + unsigned int reserved0 : 17; + } BIT; +} volatile ADC_SOC15_CFG_REG; + +/** + * @brief Define the union ADC_SOFT_TRIG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_soc0_soft_trig : 1; /**< SOC0 triggered by software */ + unsigned int cfg_soc1_soft_trig : 1; /**< SOC1 triggered by software */ + unsigned int cfg_soc2_soft_trig : 1; /**< SOC2 triggered by software */ + unsigned int cfg_soc3_soft_trig : 1; /**< SOC3 triggered by software */ + unsigned int cfg_soc4_soft_trig : 1; /**< SOC4 triggered by software */ + unsigned int cfg_soc5_soft_trig : 1; /**< SOC5 triggered by software */ + unsigned int cfg_soc6_soft_trig : 1; /**< SOC6 triggered by software */ + unsigned int cfg_soc7_soft_trig : 1; /**< SOC7 triggered by software */ + unsigned int cfg_soc8_soft_trig : 1; /**< SOC8 triggered by software */ + unsigned int cfg_soc9_soft_trig : 1; /**< SOC9 triggered by software */ + unsigned int cfg_soc10_soft_trig : 1; /**< SOC10 triggered by software */ + unsigned int cfg_soc11_soft_trig : 1; /**< SOC11 triggered by software */ + unsigned int cfg_soc12_soft_trig : 1; /**< SOC12 triggered by software */ + unsigned int cfg_soc13_soft_trig : 1; /**< SOC13 triggered by software */ + unsigned int cfg_soc14_soft_trig : 1; /**< SOC14 triggered by software */ + unsigned int cfg_soc15_soft_trig : 1; /**< SOC15 triggered by software */ + unsigned int reserved0 : 16; + } BIT; +} volatile ADC_SOFT_TRIG_REG; + +/** + * @brief Define the union ADC_ARBT0_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_soc_priority : 16; /**< Priority configuration */ + unsigned int reserved0 : 16; + } BIT; +} volatile ADC_ARBT0_REG; + +/** + * @brief Define the union ADC_ARBT1_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_rr_pointer_reset : 1; /**< Reset Poll Pointer */ + unsigned int reserved0 : 31; + } BIT; +} volatile ADC_ARBT1_REG; + +/** + * @brief Define the union ADC_ARBT2_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int rr_pointer : 4; /**< Priority polling pointer */ + unsigned int reserved0 : 28; + } BIT; +} volatile ADC_ARBT2_REG; + +/** + * @brief Define the union ADC_OVERSAMP_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_oversamp_en : 1; /**< Oversampling enable bit */ + unsigned int reserved0 : 3; + unsigned int cfg_oversamp_soc_sel : 4; /**< Selecting a specified SoC for oversampling */ + unsigned int cfg_oversamp_n : 4; /**< Configuring the Oversampling Multiple */ + unsigned int cfg_oversamp_m : 4; /**< Oversampling precision truncation */ + unsigned int reserved1 : 16; + } BIT; +} volatile ADC_OVERSAMP_REG; + +/** + * @brief Define the union ADC_OVERSAMP_RESULT_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int oversamp_data : 16; /**< Oversampling result. The lower bits (12 to 16 bits) are valid */ + unsigned int reserved0 : 16; + } BIT; +} volatile ADC_OVERSAMP_RESULT_REG; + +/** + * @brief Define the union ADC_PPB0_CTRL0_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int cfg_ppb0_dly_en : 1; /**< Sampling delay count enable bit */ + unsigned int cfg_ppb0_offset_en : 1; /**< Offset result count enable */ + unsigned int cfg_ppb0_detect_en : 1; /**< Threshold detection enable */ + unsigned int cfg_ppb0_soc_sel : 4; /**< Select soc */ + unsigned int reserved1 : 12; + unsigned int cfg_ppb0_offset : 12; /**< set offset value. 1-bit sign bit, 11-bit integer bit */ + } BIT; +} volatile ADC_PPB0_CTRL0_REG; + +/** + * @brief Define the union ADC_PPB0_CTRL1_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_ppb0_dnlimit : 13; /**< Lower threshold of error detection */ + unsigned int cfg_ppb0_uplimit : 13; /**< Upper threshold of error detection */ + unsigned int reserved0 : 6; + } BIT; +} volatile ADC_PPB0_CTRL1_REG; + +/** + * @brief Define the union ADC_PPB0_CTRL2_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_ppb0_ref : 12; /**< Error reference value (unsigned number, 12-bit integer) */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_PPB0_CTRL2_REG; + +/** + * @brief Define the union ADC_PPB0_RESULT_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int ppb0_error_data : 13; /**< Error calculation result */ + unsigned int reserved0 : 3; + unsigned int ppb0_dly_stamp : 16; /**< Sample delay count value */ + } BIT; +} volatile ADC_PPB0_RESULT_REG; + +/** + * @brief Define the union ADC_PPB1_CTRL0_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int cfg_ppb1_dly_en : 1; /**< Sampling delay count enable bit */ + unsigned int cfg_ppb1_offset_en : 1; /**< Offset result count enable */ + unsigned int cfg_ppb1_detect_en : 1; /**< Threshold detection enable */ + unsigned int cfg_ppb1_soc_sel : 4; /**< Select soc */ + unsigned int reserved1 : 12; + unsigned int cfg_ppb1_offset : 12; /**< set offset value. 1-bit sign bit, 11-bit integer bit */ + } BIT; +} volatile ADC_PPB1_CTRL0_REG; + +/** + * @brief Define the union ADC_PPB1_CTRL1_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_ppb1_dnlimit : 13; /**< Lower threshold of error detection */ + unsigned int cfg_ppb1_uplimit : 13; /**< Upper threshold of error detection */ + unsigned int reserved0 : 6; + } BIT; +} volatile ADC_PPB1_CTRL1_REG; + +/** + * @brief Define the union ADC_PPB1_CTRL2_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_ppb1_ref : 12; /**< Error reference value (unsigned number, 12-bit integer) */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_PPB1_CTRL2_REG; + +/** + * @brief Define the union ADC_PPB1_RESULT_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int ppb1_error_data : 13; /**< Error calculation result */ + unsigned int reserved0 : 3; + unsigned int ppb1_dly_stamp : 16; /**< Sample delay count value */ + } BIT; +} volatile ADC_PPB1_RESULT_REG; + +/** + * @brief Define the union ADC_PPB2_CTRL0_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int cfg_ppb2_dly_en : 1; /**< Sampling delay count enable bit */ + unsigned int cfg_ppb2_offset_en : 1; /**< Offset result count enable */ + unsigned int cfg_ppb2_detect_en : 1; /**< Threshold detection enable */ + unsigned int cfg_ppb2_soc_sel : 4; /**< Select soc */ + unsigned int reserved1 : 12; + unsigned int cfg_ppb2_offset : 12; /**< set offset value. 1-bit sign bit, 11-bit integer bit */ + } BIT; +} volatile ADC_PPB2_CTRL0_REG; + +/** + * @brief Define the union ADC_PPB2_CTRL1_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_ppb2_dnlimit : 13; /**< Lower threshold of error detection */ + unsigned int cfg_ppb2_uplimit : 13; /**< Upper threshold of error detection */ + unsigned int reserved0 : 6; + } BIT; +} volatile ADC_PPB2_CTRL1_REG; + +/** + * @brief Define the union ADC_PPB2_CTRL2_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_ppb2_ref : 12; /**< Error reference value (unsigned number, 12-bit integer) */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_PPB2_CTRL2_REG; + +/** + * @brief Define the union ADC_PPB2_RESULT_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int ppb2_error_data : 13; /**< Error calculation result */ + unsigned int reserved0 : 3; + unsigned int ppb2_dly_stamp : 16; /**< Sample delay count value */ + } BIT; +} volatile ADC_PPB2_RESULT_REG; + +/** + * @brief Define the union ADC_PPB3_CTRL0_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int cfg_ppb3_dly_en : 1; /**< Sampling delay count enable bit */ + unsigned int cfg_ppb3_offset_en : 1; /**< Offset result count enable */ + unsigned int cfg_ppb3_detect_en : 1; /**< Threshold detection enable */ + unsigned int cfg_ppb3_soc_sel : 4; /**< Select soc */ + unsigned int reserved1 : 12; + unsigned int cfg_ppb3_offset : 12; /**< set offset value. 1-bit sign bit, 11-bit integer bit */ + } BIT; +} volatile ADC_PPB3_CTRL0_REG; + +/** + * @brief Define the union ADC_PPB3_CTRL1_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_ppb3_dnlimit : 13; /**< Lower threshold of error detection */ + unsigned int cfg_ppb3_uplimit : 13; /**< Upper threshold of error detection */ + unsigned int reserved0 : 6; + } BIT; +} volatile ADC_PPB3_CTRL1_REG; + +/** + * @brief Define the union ADC_PPB3_CTRL2_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_ppb3_ref : 12; /**< Error reference value (unsigned number, 12-bit integer) */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_PPB3_CTRL2_REG; + +/** + * @brief Define the union ADC_PPB3_RESULT_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int ppb3_error_data : 13; /**< Error calculation result */ + unsigned int reserved0 : 3; + unsigned int ppb3_dly_stamp : 16; /**< Sample delay count value */ + } BIT; +} volatile ADC_PPB3_RESULT_REG; + +/** + * @brief Define the union ADC_INT_DATA_0_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_intr_data_sel0 : 16; /**< Configuration SoC selection data completion interrupt 0 */ + unsigned int cfg_intr_data_sel1 : 16; /**< Configuration SoC selection data completion interrupt 1 */ + } BIT; +} volatile ADC_INT_DATA_0_REG; + +/** + * @brief Define the union ADC_INT_DATA_1_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_intr_data_sel2 : 16; /**< Configuration SoC selection data completion interrupt 2 */ + unsigned int cfg_intr_data_sel3 : 16; /**< Configuration SoC selection data completion interrupt 3 */ + } BIT; +} volatile ADC_INT_DATA_1_REG; + +/** + * @brief Define the union ADC_INT_DATA_FLAG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int intr_data_flag0 : 1; /**< Raw status of data completion interrupt 0 */ + unsigned int intr_data_flag1 : 1; /**< Raw status of data completion interrupt 1 */ + unsigned int intr_data_flag2 : 1; /**< Raw status of data completion interrupt 2 */ + unsigned int intr_data_flag3 : 1; /**< Raw status of data completion interrupt 3 */ + unsigned int reserved0 : 28; + } BIT; +} volatile ADC_INT_DATA_FLAG_REG; + +/** + * @brief Define the union ADC_INT_DATA_MSK_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int intr_data_flag0_msk : 1; /**< Masked interrupt status of data completion interrupt 0 */ + unsigned int intr_data_flag1_msk : 1; /**< Masked interrupt status of data completion interrupt 1 */ + unsigned int intr_data_flag2_msk : 1; /**< Masked interrupt status of data completion interrupt 2 */ + unsigned int intr_data_flag3_msk : 1; /**< Masked interrupt status of data completion interrupt 3 */ + unsigned int reserved0 : 28; + } BIT; +} volatile ADC_INT_DATA_MSK_REG; + +/* Define the union ADC_DATA_FLAG_MASK_REG */ +/** + * @brief Define the union ADC_INT_DATA_FLAG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int intr_data_flag0_mask : 1; /**< Interrupt mask flag of data completion interrupt 0 */ + unsigned int intr_data_flag1_mask : 1; /**< Interrupt mask flag of data completion interrupt 1 */ + unsigned int intr_data_flag2_mask : 1; /**< Interrupt mask flag of data completion interrupt 2 */ + unsigned int intr_data_flag3_mask : 1; /**< Interrupt mask flag of data completion interrupt 3 */ + unsigned int reserved0 : 28; + } BIT; +} volatile ADC_DATA_FLAG_MASK_REG; + +/** + * @brief Define the union ADC_EVENT_INT_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int intr_ppb0_zero_det : 1; /**< Raw status of PPB0 zero-crossing interrupt */ + unsigned int intr_ppb0_uplimit_det : 1; /**< Raw status of PPB0 up threshold interrupt */ + unsigned int intr_ppb0_dnlimit_det : 1; /**< Raw status of PPB0 down threshold interrupt */ + unsigned int intr_ppb0_error_data_vld : 1; /**< Raw status of PPB0 error calculation interrupt */ + unsigned int intr_ppb1_zero_det : 1; /**< Raw status of PPB1 zero-crossing interrupt */ + unsigned int intr_ppb1_uplimit_det : 1; /**< Raw status of PPB1 up threshold interrupt */ + unsigned int intr_ppb1_dnlimit_det : 1; /**< Raw status of PPB1 down threshold interrupt */ + unsigned int intr_ppb1_error_data_vld : 1; /**< Raw status of PPB1 error calculation interrupt */ + unsigned int intr_ppb2_zero_det : 1; /**< Raw status of PPB2 zero-crossing interrupt */ + unsigned int intr_ppb2_uplimit_det : 1; /**< Raw status of PPB2 up threshold interrupt */ + unsigned int intr_ppb2_dnlimit_det : 1; /**< Raw status of PPB2 down threshold interrupt */ + unsigned int intr_ppb2_error_data_vld : 1; /**< Raw status of PPB2 error calculation interrupt */ + unsigned int intr_ppb3_zero_det : 1; /**< Raw status of PPB3 zero-crossing interrupt */ + unsigned int intr_ppb3_uplimit_det : 1; /**< Raw status of PPB3 up threshold interrupt */ + unsigned int intr_ppb3_dnlimit_det : 1; /**< Raw status of PPB3 down threshold interrupt */ + unsigned int intr_ppb3_error_data_vld : 1; /**< Raw status of PPB3 error calculation interrupt */ + unsigned int intr_oversamp_data_vld : 1; /**< Raw status of oversampling completion interrupt */ + unsigned int intr_cali_done : 1; /**< Raw status of calibration completed interrupt */ + unsigned int reserved0 : 14; + } BIT; +} volatile ADC_EVENT_INT_REG; + +/** + * @brief Define the union ADC_EVENT_INT_MSK_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int intr_ppb0_zero_det_msk : 1; /**< Masked status of PPB0 zero-crossing interrupt */ + unsigned int intr_ppb0_uplimit_det_msk : 1; /**< Masked status of PPB0 up threshold interrupt */ + unsigned int intr_ppb0_dnlimit_det_msk : 1; /**< Masked status of PPB0 down threshold interrupt */ + unsigned int intr_ppb0_error_data_vld_msk : 1; /**< Masked status of PPB0 error calculation interrupt */ + unsigned int intr_ppb1_zero_det_msk : 1; /**< Masked status of PPB1 zero-crossing interrupt */ + unsigned int intr_ppb1_uplimit_det_msk : 1; /**< Masked status of PPB1 up threshold interrupt */ + unsigned int intr_ppb1_dnlimit_det_msk : 1; /**< Masked status of PPB1 down threshold interrupt */ + unsigned int intr_ppb1_error_data_vld_msk : 1; /**< Masked status of PPB1 error calculation interrupt */ + unsigned int intr_ppb2_zero_det_msk : 1; /**< Masked status of PPB2 zero-crossing interrupt */ + unsigned int intr_ppb2_uplimit_det_msk : 1; /**< Masked status of PPB2 up threshold interrupt */ + unsigned int intr_ppb2_dnlimit_det_msk : 1; /**< Masked status of PPB2 down threshold interrupt */ + unsigned int intr_ppb2_error_data_vld_msk : 1; /**< Masked status of PPB2 error calculation interrupt */ + unsigned int intr_ppb3_zero_det_msk : 1; /**< Masked status of PPB3 zero-crossing interrupt */ + unsigned int intr_ppb3_uplimit_det_msk : 1; /**< Masked status of PPB3 up threshold interrupt */ + unsigned int intr_ppb3_dnlimit_det_msk : 1; /**< Masked status of PPB3 down threshold interrupt */ + unsigned int intr_ppb3_error_data_vld_msk : 1; /**< Masked status of PPB3 error calculation interrupt */ + unsigned int intr_oversamp_data_vld_msk : 1; /**< Masked status of oversampling completion interrupt */ + unsigned int intr_cali_done_msk : 1; /**< Masked status of calibration completed interrupt */ + unsigned int reserved0 : 14; + } BIT; +} volatile ADC_EVENT_INT_MSK_REG; + +/** + * @brief Define the union ADC_EVENT_INT_MASK_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int intr_ppb0_zero_det_mask : 1; /**< Mask flag of PPB0 zero-crossing interrupt */ + unsigned int intr_ppb0_uplimit_det_mask : 1; /**< Mask flag of PPB0 up threshold interrupt */ + unsigned int intr_ppb0_dnlimit_det_mask : 1; /**< Mask flag of PPB0 down threshold interrupt */ + unsigned int intr_ppb0_error_data_vld_mask : 1; /**< Mask flag of PPB0 error calculation interrupt */ + unsigned int intr_ppb1_zero_det_mask : 1; /**< Mask flag of PPB1 zero-crossing interrupt */ + unsigned int intr_ppb1_uplimit_det_mask : 1; /**< Mask flag of PPB1 up threshold interrupt */ + unsigned int intr_ppb1_dnlimit_det_mask : 1; /**< Mask flag of PPB1 down threshold interrupt */ + unsigned int intr_ppb1_error_data_vld_mask : 1; /**< Mask flag of PPB1 error calculation interrupt */ + unsigned int intr_ppb2_zero_det_mask : 1; /**< Mask flag of PPB2 zero-crossing interrupt */ + unsigned int intr_ppb2_uplimit_det_mask : 1; /**< Mask flag of PPB2 up threshold interrupt */ + unsigned int intr_ppb2_dnlimit_det_mask : 1; /**< Mask flag of PPB2 down threshold interrupt */ + unsigned int intr_ppb2_error_data_vld_mask : 1; /**< Mask flag of PPB2 error calculation interrupt */ + unsigned int intr_ppb3_zero_det_mask : 1; /**< Mask flag of PPB3 zero-crossing interrupt */ + unsigned int intr_ppb3_uplimit_det_mask : 1; /**< Mask flag of PPB3 up threshold interrupt */ + unsigned int intr_ppb3_dnlimit_det_mask : 1; /**< Mask flag of PPB3 down threshold interrupt */ + unsigned int intr_ppb3_error_data_vld_mask : 1; /**< Mask flag of PPB3 error calculation interrupt */ + unsigned int intr_oversamp_data_vld_mask : 1; /**< Mask flag of oversampling completion interrupt */ + unsigned int intr_cali_done_mask : 1; /**< Mask flag of calibration completed interrupt */ + unsigned int reserved0 : 14; + } BIT; +} volatile ADC_EVENT_INT_MASK_REG; + +/** + * @brief Define the union ADC_ERR_INT_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int intr_soc0_trig_over_flag : 1; /**< Raw status of soc0 trigger overflow */ + unsigned int intr_soc1_trig_over_flag : 1; /**< Raw status of soc1 trigger overflow */ + unsigned int intr_soc2_trig_over_flag : 1; /**< Raw status of soc2 trigger overflow */ + unsigned int intr_soc3_trig_over_flag : 1; /**< Raw status of soc3 trigger overflow */ + unsigned int intr_soc4_trig_over_flag : 1; /**< Raw status of soc4 trigger overflow */ + unsigned int intr_soc5_trig_over_flag : 1; /**< Raw status of soc5 trigger overflow */ + unsigned int intr_soc6_trig_over_flag : 1; /**< Raw status of soc6 trigger overflow */ + unsigned int intr_soc7_trig_over_flag : 1; /**< Raw status of soc7 trigger overflow */ + unsigned int intr_soc8_trig_over_flag : 1; /**< Raw status of soc8 trigger overflow */ + unsigned int intr_soc9_trig_over_flag : 1; /**< Raw status of soc9 trigger overflow */ + unsigned int intr_soc10_trig_over_flag : 1; /**< Raw status of soc10 trigger overflow */ + unsigned int intr_soc11_trig_over_flag : 1; /**< Raw status of soc11 trigger overflow */ + unsigned int intr_soc12_trig_over_flag : 1; /**< Raw status of soc12 trigger overflow */ + unsigned int intr_soc13_trig_over_flag : 1; /**< Raw status of soc13 trigger overflow */ + unsigned int intr_soc14_trig_over_flag : 1; /**< Raw status of soc14 trigger overflow */ + unsigned int intr_soc15_trig_over_flag : 1; /**< Raw status of soc15 trigger overflow */ + unsigned int intr_dma_req_over_flag : 1; /**< Raw status of dma request overflow */ + unsigned int reserved0 : 15; + } BIT; +} volatile ADC_ERR_INT_REG; + +/** + * @brief Define the union ADC_ERR_INT_MSK_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int intr_soc0_trig_over_flag_msk : 1; /**< Masked status of soc0 trigger overflow */ + unsigned int intr_soc1_trig_over_flag_msk : 1; /**< Masked status of soc1 trigger overflow */ + unsigned int intr_soc2_trig_over_flag_msk : 1; /**< Masked status of soc2 trigger overflow */ + unsigned int intr_soc3_trig_over_flag_msk : 1; /**< Masked status of soc3 trigger overflow */ + unsigned int intr_soc4_trig_over_flag_msk : 1; /**< Masked status of soc4 trigger overflow */ + unsigned int intr_soc5_trig_over_flag_msk : 1; /**< Masked status of soc5 trigger overflow */ + unsigned int intr_soc6_trig_over_flag_msk : 1; /**< Masked status of soc6 trigger overflow */ + unsigned int intr_soc7_trig_over_flag_msk : 1; /**< Masked status of soc7 trigger overflow */ + unsigned int intr_soc8_trig_over_flag_msk : 1; /**< Masked status of soc8 trigger overflow */ + unsigned int intr_soc9_trig_over_flag_msk : 1; /**< Masked status of soc9 trigger overflow */ + unsigned int intr_soc10_trig_over_flag_msk : 1; /**< Masked status of soc10 trigger overflow */ + unsigned int intr_soc11_trig_over_flag_msk : 1; /**< Masked status of soc11 trigger overflow */ + unsigned int intr_soc12_trig_over_flag_msk : 1; /**< Masked status of soc12 trigger overflow */ + unsigned int intr_soc13_trig_over_flag_msk : 1; /**< Masked status of soc13 trigger overflow */ + unsigned int intr_soc14_trig_over_flag_msk : 1; /**< Masked status of soc14 trigger overflow */ + unsigned int intr_soc15_trig_over_flag_msk : 1; /**< Masked status of soc15 trigger overflow */ + unsigned int intr_dma_req_over_flag_msk : 1; /**< Masked status of dma request overflow */ + unsigned int reserved0 : 15; + } BIT; +} volatile ADC_ERR_INT_MSK_REG; + +/** + * @brief Define the union ADC_ERR_INT_MASK_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int intr_soc0_trig_over_flag_mask : 1; /**< Mask flag of soc0 trigger overflow */ + unsigned int intr_soc1_trig_over_flag_mask : 1; /**< Mask flag of soc1 trigger overflow */ + unsigned int intr_soc2_trig_over_flag_mask : 1; /**< Mask flag of soc2 trigger overflow */ + unsigned int intr_soc3_trig_over_flag_mask : 1; /**< Mask flag of soc3 trigger overflow */ + unsigned int intr_soc4_trig_over_flag_mask : 1; /**< Mask flag of soc4 trigger overflow */ + unsigned int intr_soc5_trig_over_flag_mask : 1; /**< Mask flag of soc5 trigger overflow */ + unsigned int intr_soc6_trig_over_flag_mask : 1; /**< Mask flag of soc6 trigger overflow */ + unsigned int intr_soc7_trig_over_flag_mask : 1; /**< Mask flag of soc7 trigger overflow */ + unsigned int intr_soc8_trig_over_flag_mask : 1; /**< Mask flag of soc8 trigger overflow */ + unsigned int intr_soc9_trig_over_flag_mask : 1; /**< Mask flag of soc9 trigger overflow */ + unsigned int intr_soc10_trig_over_flag_mask : 1; /**< Mask flag of soc10 trigger overflow */ + unsigned int intr_soc11_trig_over_flag_mask : 1; /**< Mask flag of soc11 trigger overflow */ + unsigned int intr_soc12_trig_over_flag_mask : 1; /**< Mask flag of soc12 trigger overflow */ + unsigned int intr_soc13_trig_over_flag_mask : 1; /**< Mask flag of soc13 trigger overflow */ + unsigned int intr_soc14_trig_over_flag_mask : 1; /**< Mask flag of soc14 trigger overflow */ + unsigned int intr_soc15_trig_over_flag_mask : 1; /**< Mask flag of soc15 trigger overflow */ + unsigned int intr_dma_req_over_flag_mask : 1; /**< Mask flag of dma request overflow */ + unsigned int reserved0 : 15; + } BIT; +} volatile ADC_ERR_INT_MASK_REG; + +/** + * @brief Define the union ADC_DMA_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_dma_soc_sel : 4; /**< Configuring the DMA function for a specified soc */ + unsigned int cfg_dma_sing_req_sel : 1; /**< DMA single request signal enable */ + unsigned int cfg_dma_brst_req_sel : 1; /**< DMA burst request signal enable */ + unsigned int reserved0 : 26; + } BIT; +} volatile ADC_DMA_REG; + +/** + * @brief Define the union ADC_EN_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_adc_en : 1; /**< ADC Controller Enable */ + unsigned int reserved0 : 31; + } BIT; +} volatile ADC_EN_REG; + +/** + * @brief Define the union ADC_EN_DLY_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_en_dly : 8; /**< Delay time after ADC is enabled (us) */ + unsigned int reserved0 : 24; + } BIT; +} volatile ADC_EN_DLY_REG; + +/** + * @brief Define the union ADC_MODE_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_adc_mode : 2; /**< ADC Operating Mode */ + unsigned int reserved0 : 30; + } BIT; +} volatile ADC_MODE_REG; + +/** + * @brief Define the union ADC_OEGE_CH_SEL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_oege_ch_sel0 : 5; /**< Connection channel select, compensated by cfg_gain0/cfg_ofst0 */ + unsigned int reserved0 : 3; + unsigned int cfg_oege_ch_sel1 : 5; /**< Connection channel select, compensated by cfg_gain1/cfg_ofst1 */ + unsigned int reserved1 : 3; + unsigned int cfg_oege_ch_sel2 : 5; /**< Connection channel select, compensated by cfg_gain2/cfg_ofst2 */ + unsigned int reserved2 : 11; + } BIT; +} volatile ADC_OEGE_CH_SEL_REG; + +/** + * @brief Define the union ADC_OEGE_CTRL0_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_ofst0 : 12; /**< Set OE value. 1-bit sign bit, 10-bit integer bit, 1-bit decimal bit */ + unsigned int reserved0 : 4; + unsigned int cfg_gain0 : 13; /**< Set GE value. Unsigned number, 1-bit integer, 12-bit decimal */ + unsigned int reserved1 : 3; + } BIT; +} volatile ADC_OEGE_CTRL0_REG; + +/** + * @brief Define the union ADC_OEGE_CTRL1_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_ofst1 : 12; /**< Set OE value. 1-bit sign bit, 10-bit integer bit, 1-bit decimal bit */ + unsigned int reserved0 : 4; + unsigned int cfg_gain1 : 13; /**< Set GE value. Unsigned number, 1-bit integer, 12-bit decimal */ + unsigned int reserved1 : 3; + } BIT; +} volatile ADC_OEGE_CTRL1_REG; + +/** + * @brief Define the union ADC_OEGE_CTRL2_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_ofst2 : 12; /**< Set OE value. 1-bit sign bit, 10-bit integer bit, 1-bit decimal bit */ + unsigned int reserved0 : 4; + unsigned int cfg_gain2 : 13; /**< Set GE value. Unsigned number, 1-bit integer, 12-bit decimal */ + unsigned int reserved1 : 3; + } BIT; +} volatile ADC_OEGE_CTRL2_REG; + +/** + * @brief Define the union ADC_PROCESS0_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_ofst_cali : 12; /**< Level-2 offset compensation, 1-bit sign, 10-bit integer, 1-bit decimal */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_PROCESS0_REG; + +/** + * @brief Define the union ADC_PROCESS1_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_noise_add_en : 1; /**< Digital noise addition enable */ + unsigned int cfg_w_norm_sel : 1; + unsigned int cfg_noise_add_bits : 3; /**< Digital noise size */ + unsigned int reserved0 : 27; + } BIT; +} volatile ADC_PROCESS1_REG; + +/** + * @brief Define the union ADC_STATUS_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_busy : 1; /**< ADC working status */ + unsigned int reserved0 : 31; + } BIT; +} volatile ADC_STATUS_REG; + +/** + * @brief Define the union ADC_WEIGHT_CFG15_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_weight15 : 19; /**< Weight configuration value of capacitor 15 */ + unsigned int reserved0 : 13; + } BIT; +} volatile ADC_WEIGHT_CFG15_REG; + +/** + * @brief Define the union ADC_WEIGHT_CFG14_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_weight14 : 18; /**< Weight configuration value of capacitor 14 */ + unsigned int reserved0 : 14; + } BIT; +} volatile ADC_WEIGHT_CFG14_REG; + +/** + * @brief Define the union ADC_WEIGHT_CFG13_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_weight13 : 17; /**< Weight configuration value of capacitor 13 */ + unsigned int reserved0 : 15; + } BIT; +} volatile ADC_WEIGHT_CFG13_REG; + +/** + * @brief Define the union ADC_WEIGHT_CFG12_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_weight12 : 16; /**< Weight configuration value of capacitor 12 */ + unsigned int reserved0 : 16; + } BIT; +} volatile ADC_WEIGHT_CFG12_REG; + +/** + * @brief Define the union ADC_WEIGHT_CFG11_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_weight11 : 15; /**< Weight configuration value of capacitor 11 */ + unsigned int reserved0 : 17; + } BIT; +} volatile ADC_WEIGHT_CFG11_REG; + +/** + * @brief Define the union ADC_WEIGHT_CFG10_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_weight10 : 15; /**< Weight configuration value of capacitor 10 */ + unsigned int reserved0 : 17; + } BIT; +} volatile ADC_WEIGHT_CFG10_REG; + +/** + * @brief Define the union ADC_WEIGHT_CFG9_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_weight9 : 14; /**< Weight configuration value of capacitor 9 */ + unsigned int reserved0 : 18; + } BIT; +} volatile ADC_WEIGHT_CFG9_REG; + +/** + * @brief Define the union ADC_WEIGHT_CFG8_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_weight8 : 13; /**< Weight configuration value of capacitor 8 */ + unsigned int reserved0 : 19; + } BIT; +} volatile ADC_WEIGHT_CFG8_REG; + +/** + * @brief Define the union ADC_WEIGHT_CFG7_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_weight7 : 12; /**< Weight configuration value of capacitor 7 */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_WEIGHT_CFG7_REG; + +/** + * @brief Define the union ADC_WEIGHT_CFG6_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_weight6 : 12; /**< Weight configuration value of capacitor 6 */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_WEIGHT_CFG6_REG; + +/** + * @brief Define the union ADC_WEIGHT_CFG5_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_weight5 : 11; /**< Weight configuration value of capacitor 5 */ + unsigned int reserved0 : 21; + } BIT; +} volatile ADC_WEIGHT_CFG5_REG; + +/** + * @brief Define the union ADC_WEIGHT_CFG4_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_weight4 : 10; /**< Weight configuration value of capacitor 4 */ + unsigned int reserved0 : 22; + } BIT; +} volatile ADC_WEIGHT_CFG4_REG; + +/** + * @brief Define the union ADC_WEIGHT_CFG3_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_weight3 : 9; /**< Weight configuration value of capacitor 3 */ + unsigned int reserved0 : 23; + } BIT; +} volatile ADC_WEIGHT_CFG3_REG; + +/** + * @brief Define the union ADC_CAP_TRG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_mode1_start : 1; /**< Trigger logic auto-calibration weight value */ + unsigned int cfg_weight_ini : 1; /**< Initialize the weight and load the weight value */ + unsigned int reserved0 : 30; + } BIT; +} volatile ADC_CAP_TRG_REG; + +/** + * @brief Define the union ADC_CAP_M1_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_mode1_acc_sel : 3; /**< Mode 1 Accumulated Times Selection */ + unsigned int cfg_cap_index : 4; /**< Mode 1 Start Capacitor Configuration */ + unsigned int cfg_weight_limit_sel : 3; /**< Weight upper and lower limit gear selection */ + unsigned int cfg_mode1_caplsb_sel : 1; /**< Mode 1 low-bit capacitor enable */ + unsigned int cfg_weight_limit_bypass : 1; /**< Weight upper and lower threshold bypass enable */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_CAP_M1_REG; + +/** + * @brief Define the union ADC_ANA_CTRL0_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_inmux_en : 1; /**< Channel selection control enable signal */ + unsigned int cfg_comp_chop_en : 1; /**< Chopper enable signal of the ADC comparator */ + unsigned int cfg_latch_dly_sel : 1; /**< Sets whether to delay one cycle. */ + unsigned int cfg_muxtime_sel : 2; /**< Channel early switch period selection */ + unsigned int reserved0 : 11; + unsigned int cfg_sar_comp : 4; /**< ADC COMP reserved register */ + unsigned int cfg_sar_vcm : 4; /**< ADC VCM reserved register */ + unsigned int cfg_sar_vref : 4; /**< ADC VREF reserved register */ + unsigned int cfg_sar_samp_cap_sel : 4; /**< Number of ADC sampling capacitors */ + } BIT; +} volatile ADC_ANA_CTRL0_REG; + +/** + * @brief Define the union ADC_AVDD_EN_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_avdd_en : 1; /**< ADC inner channel AVDD/3 control register */ + unsigned int reserved0 : 31; + } BIT; +} volatile ADC_AVDD_EN_REG; + +/** + * @brief Define the union ADC_TSENSOR_TRIM_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_tsensor_ofst_trim : 12; /**< Tsensor offset compensation trim value */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_TSENSOR_TRIM_REG; + +/** + * @brief Define the union ADC_OEGE_TRIM_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_ofst_cali_trim : 12; /**< ADC General Gain Calibration Trim Value */ + unsigned int reserved0 : 4; + unsigned int cfg_gain_cali_trim : 13; /**< ADC general offset calibration trim value */ + unsigned int reserved1 : 3; + } BIT; +} volatile ADC_OEGE_TRIM_REG; + +/** + * @brief Define the union ADC_PGA0_OEGE_TRIM0_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_pga0_ofst_trim2 : 12; /**< Gain calibration trim value */ + unsigned int reserved0 : 4; + unsigned int cfg_pga0_gain_trim2 : 13; /**< Offset calibration trim value */ + unsigned int reserved1 : 3; + } BIT; +} volatile ADC_PGA0_OEGE_TRIM0_REG; + +/** + * @brief Define the union ADC_PGA0_OEGE_TRIM1_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_pga0_ofst_trim4 : 12; /**< Gain calibration trim value */ + unsigned int reserved0 : 4; + unsigned int cfg_pga0_gain_trim4 : 13; /**< Offset calibration trim value */ + unsigned int reserved1 : 3; + } BIT; +} volatile ADC_PGA0_OEGE_TRIM1_REG; + +/** + * @brief Define the union ADC_PGA0_OEGE_TRIM2_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_pga0_ofst_trim8 : 12; /**< Gain calibration trim value */ + unsigned int reserved0 : 4; + unsigned int cfg_pga0_gain_trim8 : 13; /**< Offset calibration trim value */ + unsigned int reserved1 : 3; + } BIT; +} volatile ADC_PGA0_OEGE_TRIM2_REG; + +/** + * @brief Define the union ADC_PGA0_OEGE_TRIM3_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_pga0_ofst_trim16 : 12; /**< Gain calibration trim value */ + unsigned int reserved0 : 4; + unsigned int cfg_pga0_gain_trim16 : 13; /**< Offset calibration trim value */ + unsigned int reserved1 : 3; + } BIT; +} volatile ADC_PGA0_OEGE_TRIM3_REG; + +/** + * @brief Define the union ADC_PGA1_OEGE_TRIM0_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_pga1_ofst_trim2 : 12; /**< Gain calibration trim value */ + unsigned int reserved0 : 4; + unsigned int cfg_pga1_gain_trim2 : 13; /**< Offset calibration trim value */ + unsigned int reserved1 : 3; + } BIT; +} volatile ADC_PGA1_OEGE_TRIM0_REG; + +/** + * @brief Define the union ADC_PGA1_OEGE_TRIM1_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_pga1_ofst_trim4 : 12; /**< Gain calibration trim value */ + unsigned int reserved0 : 4; + unsigned int cfg_pga1_gain_trim4 : 13; /**< Offset calibration trim value */ + unsigned int reserved1 : 3; + } BIT; +} volatile ADC_PGA1_OEGE_TRIM1_REG; + +/** + * @brief Define the union ADC_PGA1_OEGE_TRIM2_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_pga1_ofst_trim8 : 12; /**< Gain calibration trim value */ + unsigned int reserved0 : 4; + unsigned int cfg_pga1_gain_trim8 : 13; /**< Offset calibration trim value */ + unsigned int reserved1 : 3; + } BIT; +} volatile ADC_PGA1_OEGE_TRIM2_REG; + +/** + * @brief Define the union ADC_PGA1_OEGE_TRIM3_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_pga1_ofst_trim16 : 12; /**< Gain calibration trim value */ + unsigned int reserved0 : 4; + unsigned int cfg_pga1_gain_trim16 : 13; /**< Offset calibration trim value */ + unsigned int reserved1 : 3; + } BIT; +} volatile ADC_PGA1_OEGE_TRIM3_REG; + +/** + * @brief Define the union ADC_ANA_TRIM_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_sar_trim0 : 8; /**< ADC analog trim register 0 */ + unsigned int cfg_sar_trim1 : 8; /**< ADC analog trim register 1 */ + unsigned int reserved0 : 16; + } BIT; +} volatile ADC_ANA_TRIM_REG; + +/** + * @brief Define the ADC_RegStruct + */ +typedef struct { + ADC_RESULT0_REG ADC_RESULT0; /**< Offset address: 0x00000000U, Result register0 */ + ADC_RESULT1_REG ADC_RESULT1; /**< Offset address: 0x00000004U, Result register1 */ + ADC_RESULT2_REG ADC_RESULT2; /**< Offset address: 0x00000008U, Result register2 */ + ADC_RESULT3_REG ADC_RESULT3; /**< Offset address: 0x0000000CU, Result register3 */ + ADC_RESULT4_REG ADC_RESULT4; /**< Offset address: 0x00000010U, Result register4 */ + ADC_RESULT5_REG ADC_RESULT5; /**< Offset address: 0x00000014U, Result register5 */ + ADC_RESULT6_REG ADC_RESULT6; /**< Offset address: 0x00000018U, Result register6 */ + ADC_RESULT7_REG ADC_RESULT7; /**< Offset address: 0x0000001CU, Result register7 */ + ADC_RESULT8_REG ADC_RESULT8; /**< Offset address: 0x00000020U, Result register8 */ + ADC_RESULT9_REG ADC_RESULT9; /**< Offset address: 0x00000024U, Result register9 */ + ADC_RESULT10_REG ADC_RESULT10; /**< Offset address: 0x00000028U, Result register10 */ + ADC_RESULT11_REG ADC_RESULT11; /**< Offset address: 0x0000002CU, Result register11 */ + ADC_RESULT12_REG ADC_RESULT12; /**< Offset address: 0x00000030U, Result register12 */ + ADC_RESULT13_REG ADC_RESULT13; /**< Offset address: 0x00000034U, Result register13 */ + ADC_RESULT14_REG ADC_RESULT14; /**< Offset address: 0x00000038U, Result register14 */ + ADC_RESULT15_REG ADC_RESULT15; /**< Offset address: 0x0000003CU, Result register15 */ + unsigned int space0[12]; + ADC_EOC_FLAG_REG ADC_EOC_FLAG; /**< Offset address: 0x00000070U, EOC status register */ + unsigned int space1[35]; + ADC_SOC0_CFG_REG ADC_SOC0_CFG; /**< Offset address: 0x00000100U, SOC0 configuration register */ + ADC_SOC1_CFG_REG ADC_SOC1_CFG; /**< Offset address: 0x00000104U, SOC1 configuration register */ + ADC_SOC2_CFG_REG ADC_SOC2_CFG; /**< Offset address: 0x00000108U, SOC2 configuration register */ + ADC_SOC3_CFG_REG ADC_SOC3_CFG; /**< Offset address: 0x0000010CU, SOC3 configuration register */ + ADC_SOC4_CFG_REG ADC_SOC4_CFG; /**< Offset address: 0x00000110U, SOC4 configuration register */ + ADC_SOC5_CFG_REG ADC_SOC5_CFG; /**< Offset address: 0x00000114U, SOC5 configuration register */ + ADC_SOC6_CFG_REG ADC_SOC6_CFG; /**< Offset address: 0x00000118U, SOC6 configuration register */ + ADC_SOC7_CFG_REG ADC_SOC7_CFG; /**< Offset address: 0x0000011CU, SOC7 configuration register */ + ADC_SOC8_CFG_REG ADC_SOC8_CFG; /**< Offset address: 0x00000120U, SOC8 configuration register */ + ADC_SOC9_CFG_REG ADC_SOC9_CFG; /**< Offset address: 0x00000124U, SOC9 configuration register */ + ADC_SOC10_CFG_REG ADC_SOC10_CFG; /**< Offset address: 0x00000128U, SOC10 configuration register */ + ADC_SOC11_CFG_REG ADC_SOC11_CFG; /**< Offset address: 0x0000012CU, SOC11 configuration register */ + ADC_SOC12_CFG_REG ADC_SOC12_CFG; /**< Offset address: 0x00000130U, SOC12 configuration register */ + ADC_SOC13_CFG_REG ADC_SOC13_CFG; /**< Offset address: 0x00000134U, SOC13 configuration register */ + ADC_SOC14_CFG_REG ADC_SOC14_CFG; /**< Offset address: 0x00000138U, SOC14 configuration register */ + ADC_SOC15_CFG_REG ADC_SOC15_CFG; /**< Offset address: 0x0000013CU, SOC15 configuration register */ + unsigned int space2[8]; + ADC_SOFT_TRIG_REG ADC_SOFT_TRIG; /**< Offset address: 0x00000160U, Software trigger register */ + unsigned int space3[39]; + ADC_ARBT0_REG ADC_ARBT0; /**< Offset address: 0x00000200U, Priority register0 */ + ADC_ARBT1_REG ADC_ARBT1; /**< Offset address: 0x00000204U, Priority register1 */ + ADC_ARBT2_REG ADC_ARBT2; /**< Offset address: 0x00000208U, Priority register2 */ + unsigned int space4[5]; + ADC_OVERSAMP_REG ADC_OVERSAMP; /**< Offset address: 0x00000220U, Oversampling setting register */ + ADC_OVERSAMP_RESULT_REG ADC_OVERSAMP_RESULT; /**< Offset address: 0x00000224U, Oversampling result register */ + unsigned int space5[10]; + ADC_PPB0_CTRL0_REG ADC_PPB0_CTRL0; /**< Offset address: 0x00000250U, PPB0 configuration register0 */ + ADC_PPB0_CTRL1_REG ADC_PPB0_CTRL1; /**< Offset address: 0x00000254U, PPB0 configuration register1 */ + ADC_PPB0_CTRL2_REG ADC_PPB0_CTRL2; /**< Offset address: 0x00000258U, PPB0 configuration register2 */ + ADC_PPB0_RESULT_REG ADC_PPB0_RESULT; /**< Offset address: 0x0000025CU, PPB0 result register */ + ADC_PPB1_CTRL0_REG ADC_PPB1_CTRL0; /**< Offset address: 0x00000260U, PPB1 configuration register0 */ + ADC_PPB1_CTRL1_REG ADC_PPB1_CTRL1; /**< Offset address: 0x00000264U, PPB1 configuration register1 */ + ADC_PPB1_CTRL2_REG ADC_PPB1_CTRL2; /**< Offset address: 0x00000268U, PPB1 configuration register2 */ + ADC_PPB1_RESULT_REG ADC_PPB1_RESULT; /**< Offset address: 0x0000026CU, PPB1 result register */ + ADC_PPB2_CTRL0_REG ADC_PPB2_CTRL0; /**< Offset address: 0x00000270U, PPB2 configuration register0 */ + ADC_PPB2_CTRL1_REG ADC_PPB2_CTRL1; /**< Offset address: 0x00000274U, PPB2 configuration register1 */ + ADC_PPB2_CTRL2_REG ADC_PPB2_CTRL2; /**< Offset address: 0x00000278U, PPB2 configuration register2 */ + ADC_PPB2_RESULT_REG ADC_PPB2_RESULT; /**< Offset address: 0x0000027CU, PPB2 result register */ + ADC_PPB3_CTRL0_REG ADC_PPB3_CTRL0; /**< Offset address: 0x00000280U, PPB3 configuration register0 */ + ADC_PPB3_CTRL1_REG ADC_PPB3_CTRL1; /**< Offset address: 0x00000284U, PPB3 configuration register1 */ + ADC_PPB3_CTRL2_REG ADC_PPB3_CTRL2; /**< Offset address: 0x00000288U, PPB3 configuration register2 */ + ADC_PPB3_RESULT_REG ADC_PPB3_RESULT; /**< Offset address: 0x0000028CU, PPB3 result register */ + unsigned int space6[8]; + ADC_INT_DATA_0_REG ADC_INT_DATA_0; /**< Offset address: 0x000002B0U, Data interrupt register0 */ + ADC_INT_DATA_1_REG ADC_INT_DATA_1; /**< Offset address: 0x000002B4U, Data interrupt register1 */ + ADC_INT_DATA_FLAG_REG ADC_INT_DATA_FLAG; /**< Offset address: 0x000002B8U, Raw data interrupt register */ + ADC_INT_DATA_MSK_REG ADC_INT_DATA_MSK; /**< Offset address: 0x000002BCU, Masked data interrupt register */ + ADC_DATA_FLAG_MASK_REG ADC_DATA_FLAG_MASK; /**< Offset address: 0x000002C0U, Data interrupt mask register */ + ADC_EVENT_INT_REG ADC_EVENT_INT; /**< Offset address: 0x000002C4U, Raw event interrupt register */ + ADC_EVENT_INT_MSK_REG ADC_EVENT_INT_MSK; /**< Offset address: 0x000002C8U, Masked event interrupt register */ + ADC_EVENT_INT_MASK_REG ADC_EVENT_INT_MASK; /**< Offset address: 0x000002CCU, Event interrupt mask register */ + ADC_ERR_INT_REG ADC_ERR_INT; /**< Offset address: 0x000002D0U, Raw error interrupt register */ + ADC_ERR_INT_MSK_REG ADC_ERR_INT_MSK; /**< Offset address: 0x000002D4U, Masked error interrupt register */ + ADC_ERR_INT_MASK_REG ADC_ERR_INT_MASK; /**< Offset address: 0x000002D8U, Error interrupt mask register */ + unsigned int space7[5]; + ADC_DMA_REG ADC_DMA; /**< Offset address: 0x000002F0U, DMA configuration register */ + unsigned int space8[3]; + ADC_EN_REG ADC_EN; /**< Offset address: 0x00000300U, Enable Register */ + unsigned int space9[3]; + ADC_EN_DLY_REG ADC_EN_DLY; /**< Offset address: 0x00000310U, Enable Delay Register */ + unsigned int space10[59]; + ADC_MODE_REG ADC_MODE; /**< Offset address: 0x00000400U, Mode configuration register */ + unsigned int space11[7]; + ADC_OEGE_CH_SEL_REG ADC_OEGE_CH_SEL; /**< Offset address: 0x00000420U, OE and GE channel register */ + unsigned int space12[7]; + ADC_OEGE_CTRL0_REG ADC_OEGE_CTRL0; /**< Offset address: 0x00000440U, OE and GE configuration register0 */ + ADC_OEGE_CTRL1_REG ADC_OEGE_CTRL1; /**< Offset address: 0x00000444U, OE and GE configuration register1 */ + ADC_OEGE_CTRL2_REG ADC_OEGE_CTRL2; /**< Offset address: 0x00000448U, OE and GE configuration register2 */ + unsigned int space13[5]; + ADC_PROCESS0_REG ADC_PROCESS0; /**< Offset address: 0x00000460U, Data processing register0 */ + ADC_PROCESS1_REG ADC_PROCESS1; /**< Offset address: 0x00000464U, Data processing register1 */ + unsigned int space14[6]; + ADC_STATUS_REG ADC_STATUS; /**< Offset address: 0x00000480U, ADC status register */ + unsigned int space15[31]; + ADC_WEIGHT_CFG15_REG ADC_WEIGHT_CFG15; /**< Offset address: 0x00000500U, Capacitor weight register */ + ADC_WEIGHT_CFG14_REG ADC_WEIGHT_CFG14; /**< Offset address: 0x00000504U, Capacitor weight register */ + ADC_WEIGHT_CFG13_REG ADC_WEIGHT_CFG13; /**< Offset address: 0x00000508U, Capacitor weight register */ + ADC_WEIGHT_CFG12_REG ADC_WEIGHT_CFG12; /**< Offset address: 0x0000050CU, Capacitor weight register */ + ADC_WEIGHT_CFG11_REG ADC_WEIGHT_CFG11; /**< Offset address: 0x00000510U, Capacitor weight register */ + ADC_WEIGHT_CFG10_REG ADC_WEIGHT_CFG10; /**< Offset address: 0x00000514U, Capacitor weight register */ + ADC_WEIGHT_CFG9_REG ADC_WEIGHT_CFG9; /**< Offset address: 0x00000518U, Capacitor weight register */ + ADC_WEIGHT_CFG8_REG ADC_WEIGHT_CFG8; /**< Offset address: 0x0000051CU, Capacitor weight register */ + ADC_WEIGHT_CFG7_REG ADC_WEIGHT_CFG7; /**< Offset address: 0x00000520U, Capacitor weight register */ + ADC_WEIGHT_CFG6_REG ADC_WEIGHT_CFG6; /**< Offset address: 0x00000524U, Capacitor weight register */ + ADC_WEIGHT_CFG5_REG ADC_WEIGHT_CFG5; /**< Offset address: 0x00000528U, Capacitor weight register */ + ADC_WEIGHT_CFG4_REG ADC_WEIGHT_CFG4; /**< Offset address: 0x0000052CU, Capacitor weight register */ + ADC_WEIGHT_CFG3_REG ADC_WEIGHT_CFG3; /**< Offset address: 0x00000530U, Capacitor weight register */ + unsigned int space16[3]; + ADC_CAP_TRG_REG ADC_CAP_TRG; /**< Offset address: 0x00000540U, Calibration enable register */ + unsigned int space17[3]; + ADC_CAP_M1_REG ADC_CAP_M1; /**< Offset address: 0x00000550U, Capacitor calibration register */ + unsigned int space18[64]; + ADC_ANA_CTRL0_REG ADC_ANA_CTRL0; /**< Offset address: 0x00000654U, Analog register0 */ + ADC_AVDD_EN_REG ADC_AVDD_EN; /**< Offset address: 0x00000658U, AVDD/3 enable register0 */ + unsigned int space19[106]; + ADC_TSENSOR_TRIM_REG ADC_TSENSOR_TRIM; /**< Offset address: 0x00000800U, Tsensor trim register */ + ADC_OEGE_TRIM_REG ADC_OEGE_TRIM; /**< Offset address: 0x00000804U, OE and GE common trim register */ + unsigned int space20[2]; + ADC_PGA0_OEGE_TRIM0_REG ADC_PGA0_OEGE_TRIM0; /**< Offset address: 0x00000810U, PGA0 OE and GE trim register0 */ + ADC_PGA0_OEGE_TRIM1_REG ADC_PGA0_OEGE_TRIM1; /**< Offset address: 0x00000814U, PGA0 OE and GE trim register1 */ + ADC_PGA0_OEGE_TRIM2_REG ADC_PGA0_OEGE_TRIM2; /**< Offset address: 0x00000818U, PGA0 OE and GE trim register2 */ + ADC_PGA0_OEGE_TRIM3_REG ADC_PGA0_OEGE_TRIM3; /**< Offset address: 0x0000081CU, PGA0 OE and GE trim register3 */ + ADC_PGA1_OEGE_TRIM0_REG ADC_PGA1_OEGE_TRIM0; /**< Offset address: 0x00000820U, PGA1 OE and GE trim register0 */ + ADC_PGA1_OEGE_TRIM1_REG ADC_PGA1_OEGE_TRIM1; /**< Offset address: 0x00000824U, PGA1 OE and GE trim register1 */ + ADC_PGA1_OEGE_TRIM2_REG ADC_PGA1_OEGE_TRIM2; /**< Offset address: 0x00000828U, PGA1 OE and GE trim register2 */ + ADC_PGA1_OEGE_TRIM3_REG ADC_PGA1_OEGE_TRIM3; /**< Offset address: 0x0000082CU, PGA1 OE and GE trim register3 */ + unsigned int space21[4]; + ADC_ANA_TRIM_REG ADC_ANA_TRIM; /**< Offset address: 0x00000840U, Analog trim register */ +} volatile ADC_RegStruct; +/** + * @} + */ + +/** + * @defgroup ADC_Param_Def ADC Parameters Definition + * @brief Description of ADC configuration parameters. + * @{ + */ + +/** + * @brief ADC sample input. + * @details Channel type: + * + ADC_CH_ADCINA0 -- ADCIN0 is converted, number 0 + * + ADC_CH_ADCINA1 -- ADCIN1 is converted, number 1 + * + ADC_CH_ADCINA2 -- ADCIN2 is converted, number 2 + * + ADC_CH_ADCINA3 -- ADCIN3 is converted, number 3 + * + ADC_CH_ADCINA4 -- ADCIN4 is converted, number 4 + * + ADC_CH_ADCINA5 -- ADCIN5 is converted, number 5 + * + ADC_CH_ADCINA6 -- ADCIN6 is converted, number 6 + * + ADC_CH_ADCINA7 -- ADCIN7 is converted, number 7 + * + ADC_CH_ADCINA8 -- ADCIN8 is converted, number 8 + * + ADC_CH_ADCINA9 -- ADCIN9 is converted, number 9 + * + ADC_CH_ADCINA10 -- ADCIN10 is converted, number 10 + * + ADC_CH_ADCINA11 -- ADCIN11 is converted, number 11 + * + ADC_CH_ADCINA12 -- ADCIN12 is converted, number 12 + * + ADC_CH_ADCINA13 -- ADCIN13 is converted, number 13 + * + ADC_CH_ADCINA14 -- ADCIN14 is converted, number 14 + * + ADC_CH_ADCINA15 -- ADCIN15 is converted, number 15 + * + ADC_CH_ADCINA16 -- ADCIN16 is converted, number 16 + * + ADC_CH_ADCINA17 -- ADCIN17 is converted, number 17 + * + ADC_CH_ADCINA18 -- ADCIN18 is converted, number 18 + * + ADC_CH_ADCINA19 -- ADCIN19 is converted, number 19 + */ +typedef enum { + ADC_CH_ADCINA0 = 0x00000000U, + ADC_CH_ADCINA1 = 0x00000001U, + ADC_CH_ADCINA2 = 0x00000002U, + ADC_CH_ADCINA3 = 0x00000003U, + ADC_CH_ADCINA4 = 0x00000004U, + ADC_CH_ADCINA5 = 0x00000005U, + ADC_CH_ADCINA6 = 0x00000006U, + ADC_CH_ADCINA7 = 0x00000007U, + ADC_CH_ADCINA8 = 0x00000008U, + ADC_CH_ADCINA9 = 0x00000009U, + ADC_CH_ADCINA10 = 0x0000000AU, + ADC_CH_ADCINA11 = 0x0000000BU, + ADC_CH_ADCINA12 = 0x0000000CU, + ADC_CH_ADCINA13 = 0x0000000DU, + ADC_CH_ADCINA14 = 0x0000000EU, + ADC_CH_ADCINA15 = 0x0000000FU, + ADC_CH_ADCINA16 = 0x00000010U, + ADC_CH_ADCINA17 = 0x00000011U, + ADC_CH_ADCINA18 = 0x00000012U, + ADC_CH_ADCINA19 = 0x00000013U, +} ADC_Input; + +/** + * @brief ADC SOC(start of conversion) classification. + */ +typedef enum { + ADC_SOC_NUM0 = 0x00000000U, + ADC_SOC_NUM1 = 0x00000001U, + ADC_SOC_NUM2 = 0x00000002U, + ADC_SOC_NUM3 = 0x00000003U, + ADC_SOC_NUM4 = 0x00000004U, + ADC_SOC_NUM5 = 0x00000005U, + ADC_SOC_NUM6 = 0x00000006U, + ADC_SOC_NUM7 = 0x00000007U, + ADC_SOC_NUM8 = 0x00000008U, + ADC_SOC_NUM9 = 0x00000009U, + ADC_SOC_NUM10 = 0x0000000AU, + ADC_SOC_NUM11 = 0x0000000BU, + ADC_SOC_NUM12 = 0x0000000CU, + ADC_SOC_NUM13 = 0x0000000DU, + ADC_SOC_NUM14 = 0x0000000EU, + ADC_SOC_NUM15 = 0x0000000FU +} ADC_SOCNumber; + +/** + * @brief ADC four interrupt classification. + * @details Interrupt type: + * + ADC_INT_NUMBER0 -- ADCINT0 interrupt + * + ADC_INT_NUMBER1 -- ADCINT1 interrupt + * + ADC_INT_NUMBER2 -- ADCINT2 interrupt + * + ADC_INT_NUMBER3 -- ADCINT3 interrupt + */ +typedef enum { + ADC_INT_NUMBER0 = 0x00000000U, + ADC_INT_NUMBER1 = 0x00000001U, + ADC_INT_NUMBER2 = 0x00000002U, + ADC_INT_NUMBER3 = 0x00000003U +} ADC_IntNumber; + +/** + * @brief ADC supports peripherals trigger source. + */ +typedef enum { + ADC_TRIGSOC_SOFT = 0x00000000U, + ADC_TRIGSOC_APT0_SOCA = 0x00000001U, + ADC_TRIGSOC_APT0_SOCB = 0x00000002U, + ADC_TRIGSOC_APT1_SOCA = 0x00000003U, + ADC_TRIGSOC_APT1_SOCB = 0x00000004U, + ADC_TRIGSOC_APT2_SOCA = 0x00000005U, + ADC_TRIGSOC_APT2_SOCB = 0x00000006U, + ADC_TRIGSOC_APT3_SOCA = 0x00000007U, + ADC_TRIGSOC_APT3_SOCB = 0x00000008U, + ADC_TRIGSOC_GPT0 = 0x00000009U, + ADC_TRIGSOC_GPT1 = 0x0000000AU, + ADC_TRIGSOC_GPT2 = 0x0000000BU, + ADC_TRIGSOC_GPT3 = 0x0000000CU, + ADC_TRIGSOC_TIMER0 = 0x000000DU, + ADC_TRIGSOC_TIMER1 = 0x000000EU, + ADC_TRIGSOC_TIMER2 = 0x000000FU, + ADC_TRIGSOC_TIMER3 = 0x00000010U, + ADC_TRIGSOC_GPIOPD5 = 0x00000011U, + ADC_TRIGSOC_GPIOPF3 = 0x00000012U, + ADC_TRIGSOC_GPIOPF2 = 0x00000013U, + ADC_TRIGSOC_GPIOPF1 = 0x00000014U, +} ADC_TrigSource; + +/** + * @brief The type of DMA request. + * @details DMA request type: + * + ADC_DMA_SINGLEREQ -- single request + * + ADC_DMA_BURSTREQ -- burst request + */ +typedef enum { + ADC_DMA_SINGLEREQ = 0x00000000U, + ADC_DMA_BURSTREQ = 0x00000001U +} ADC_DMARequestType; + +/** + * @brief The priority mode of SOCs sample simultaneously. + * @details Priority mode: + * + ADC_PRIMODE_ALL_ROUND -- Round robin mode is used for all + * + ADC_PRIMODE_SOC0 -- SOC0 higher priority, others in round + * + ADC_PRIMODE_TO_SOC1 -- SOC 0-1 higher priority, others in round + * + ADC_PRIMODE_TO_SOC2 -- SOC 0-2 higher priority, others in round + * + ADC_PRIMODE_TO_SOC3 -- SOC 0-3 higher priority, others in round + * + ADC_PRIMODE_TO_SOC4 -- SOC 0-4 higher priority, others in round + * + ADC_PRIMODE_TO_SOC5 -- SOC 0-5 higher priority, others in round + * + ADC_PRIMODE_TO_SOC6 -- SOC 0-6 higher priority, others in round + * + ADC_PRIMODE_TO_SOC7 -- SOC 0-7 higher priority, others in round + * + ADC_PRIMODE_TO_SOC8 -- SOC 0-8 higher priority, others in round + * + ADC_PRIMODE_TO_SOC9 -- SOC 0-9 higher priority, others in round + * + ADC_PRIMODE_TO_SOC10 -- SOC 0-10 higher priority, others in round + * + ADC_PRIMODE_TO_SOC11 -- SOC 0-11 higher priority, others in round + * + ADC_PRIMODE_TO_SOC12 -- SOC 0-12 higher priority, others in round + * + ADC_PRIMODE_TO_SOC13 -- SOC 0-13 higher priority, others in round + * + ADC_PRIMODE_TO_SOC14 -- SOC 0-14 higher priority, others in round + * + ADC_PRIMODE_ALL_PRIORITY -- SOC 0-15 higher priority, others in round + */ +typedef enum { + ADC_PRIMODE_ALL_ROUND = 0x00000000U, + ADC_PRIMODE_SOC0 = 0x00000001U, + ADC_PRIMODE_TO_SOC1 = 0x00000003U, + ADC_PRIMODE_TO_SOC2 = 0x00000007U, + ADC_PRIMODE_TO_SOC3 = 0x0000000FU, + ADC_PRIMODE_TO_SOC4 = 0x0000001FU, + ADC_PRIMODE_TO_SOC5 = 0x0000003FU, + ADC_PRIMODE_TO_SOC6 = 0x0000007FU, + ADC_PRIMODE_TO_SOC7 = 0x000000FFU, + ADC_PRIMODE_TO_SOC8 = 0x000001FFU, + ADC_PRIMODE_TO_SOC9 = 0x000003FFU, + ADC_PRIMODE_TO_SOC10 = 0x000007FFU, + ADC_PRIMODE_TO_SOC11 = 0x00000FFFU, + ADC_PRIMODE_TO_SOC12 = 0x00001FFFU, + ADC_PRIMODE_TO_SOC13 = 0x00003FFFU, + ADC_PRIMODE_TO_SOC14 = 0x00007FFFU, + ADC_PRIMODE_ALL_PRIORITY = 0x0000FFFFU +} ADC_PriorityMode; + +/** + * @brief The number of PPB(post processing block). + */ +typedef enum { + ADC_PPB_NUM0 = 0x00000000U, + ADC_PPB_NUM1 = 0x00000001U, + ADC_PPB_NUM2 = 0x00000002U, + ADC_PPB_NUM3 = 0x00000003U +} ADC_PPBNumber; + +/** + * @brief ADC Oversampling Right Shift Bits. + * @details: + * + ADC_RIGHTSHIFT_BIT0 -- Non-displacement + * + ADC_RIGHTSHIFT_BIT1 -- Shift 1 bit to the right + * + ADC_RIGHTSHIFT_BIT2 -- Shift 2 bit to the right + * + ADC_RIGHTSHIFT_BIT3 -- Shift 3 bit to the right + * + ADC_RIGHTSHIFT_BIT4 -- Shift 4 bit to the right + * + ADC_RIGHTSHIFT_BIT5 -- Shift 5 bit to the right + * + ADC_RIGHTSHIFT_BIT6 -- Shift 6 bit to the right + * + ADC_RIGHTSHIFT_BIT7 -- Shift 7 bit to the right + * + ADC_RIGHTSHIFT_BIT8 -- Shift 8 bit to the right + */ +typedef enum { + ADC_RIGHTSHIFT_BIT0 = 0x00000000U, + ADC_RIGHTSHIFT_BIT1 = 0x00000001U, + ADC_RIGHTSHIFT_BIT2 = 0x00000002U, + ADC_RIGHTSHIFT_BIT3 = 0x00000003U, + ADC_RIGHTSHIFT_BIT4 = 0x00000004U, + ADC_RIGHTSHIFT_BIT5 = 0x00000005U, + ADC_RIGHTSHIFT_BIT6 = 0x00000006U, + ADC_RIGHTSHIFT_BIT7 = 0x00000007U, + ADC_RIGHTSHIFT_BIT8 = 0x00000008U, +} ADC_OversamplingRightShift; + +/** + * @brief ADC Oversampling Multiple. + * @details: + * + ADC_OVERSAMPLING_8X -- The sampling result is 8 times + * + ADC_OVERSAMPLING_16X -- The sampling result is 16 times + * + ADC_OVERSAMPLING_32X -- The sampling result is 32 times + * + ADC_OVERSAMPLING_64X -- The sampling result is 64 times + * + ADC_OVERSAMPLING_128X -- The sampling result is 128 times + * + ADC_OVERSAMPLING_256X -- The sampling result is 256 times + */ +typedef enum { + ADC_OVERSAMPLING_8X = 0x00000003U, + ADC_OVERSAMPLING_16X = 0x00000004U, + ADC_OVERSAMPLING_32X = 0x00000005U, + ADC_OVERSAMPLING_64X = 0x00000006U, + ADC_OVERSAMPLING_128X = 0x00000007U, + ADC_OVERSAMPLING_256X = 0x00000008U, +} ADC_OversamplingMultiple; + +/** + * @brief ADC sampling time, unit: adc_clk. + */ +typedef enum { + ADC_SOCSAMPLE_5CLK = 0x00000000U, + ADC_SOCSAMPLE_7CLK = 0x00000001U, + ADC_SOCSAMPLE_10CLK = 0x00000002U, + ADC_SOCSAMPLE_12CLK = 0x00000003U, + ADC_SOCSAMPLE_15CLK = 0x00000004U, + ADC_SOCSAMPLE_22CLK = 0x00000005U, + ADC_SOCSAMPLE_30CLK = 0x00000006U, + ADC_SOCSAMPLE_50CLK = 0x00000007U, + ADC_SOCSAMPLE_75CLK = 0x00000008U, + ADC_SOCSAMPLE_100CLK = 0x00000009U, + ADC_SOCSAMPLE_125CLK = 0x0000000AU, + ADC_SOCSAMPLE_150CLK = 0x0000000BU, + ADC_SOCSAMPLE_200CLK = 0x0000000CU, + ADC_SOCSAMPLE_300CLK = 0x0000000DU, + ADC_SOCSAMPLE_400CLK = 0x0000000EU, + ADC_SOCSAMPLE_500CLK = 0x0000000FU +} ADC_SOCSampleCycle; + +/** + * @brief The mode of SOCs finish sample and conversion. + * @details Priority mode: + * + ADC_SOCFINISH_NONE -- Interruption and DMA are not reported when sampling is complete + * + ADC_SOCFINISH_DMA -- DMA is reported when sampling is complete + * + ADC_SOCFINISH_INT0 -- Interruption 0 is reported when sampling is complete + * + ADC_SOCFINISH_INT1 -- Interruption 1 is reported when sampling is complete + * + ADC_SOCFINISH_INT2 -- Interruption 2 is reported when sampling is complete + * + ADC_SOCFINISH_INT3 -- Interruption 3 is reported when sampling is complete + */ +typedef enum { + ADC_SOCFINISH_NONE = 0x00000001U, + ADC_SOCFINISH_DMA = 0x00000002U, + ADC_SOCFINISH_INT0 = 0x00000003U, + ADC_SOCFINISH_INT1 = 0x00000004U, + ADC_SOCFINISH_INT2 = 0x00000005U, + ADC_SOCFINISH_INT3 = 0x00000006U +} ADC_SOCFinishMode; + +/** + * @brief The mode of ADC work. + * @details Priority mode: + * + ADC_WORKMODE_NORMAL -- Normal Work + * + ADC_WORKMODE_CAPACITY1 -- Calibration Mode 1 + */ +typedef enum { + ADC_WORKMODE_NORMAL = 0x00000000U, + ADC_WORKMODE_CAPACITY1 = 0x00000001U, +} ADC_WorkMode; + +/** + * @brief The type of interrupt call back functions. + */ +typedef enum { + ADC_CALLBACK_INT0 = 0x00000000U, + ADC_CALLBACK_INT1 = 0x00000001U, + ADC_CALLBACK_INT2 = 0x00000002U, + ADC_CALLBACK_INT3 = 0x00000003U, + ADC_CALLBACK_DMA = 0x000000004U, + ADC_CALLBACK_DMAERROR = 0x000000005U, + ADC_CALLBACK_DMAOVER = 0x00000006U, + ADC_CALLBACK_TRIGOVER = 0x00000007U, + ADC_CALLBACK_EVENT_OVERSAMPLING = 0x000000008U, + ADC_CALLBACK_EVENT_PPB0_ZERO = 0x00000010U, + ADC_CALLBACK_EVENT_PPB0_UP = 0x00000011U, + ADC_CALLBACK_EVENT_PPB0_DOWN = 0x00000012U, + ADC_CALLBACK_EVENT_PPB0_ERROR = 0x00000013U, + ADC_CALLBACK_EVENT_PPB1_ZERO = 0x000000014U, + ADC_CALLBACK_EVENT_PPB1_UP = 0x00000015U, + ADC_CALLBACK_EVENT_PPB1_DOWN = 0x00000016U, + ADC_CALLBACK_EVENT_PPB1_ERROR = 0x00000017U, + ADC_CALLBACK_EVENT_PPB2_ZERO = 0x00000018U, + ADC_CALLBACK_EVENT_PPB2_UP = 0x00000019U, + ADC_CALLBACK_EVENT_PPB2_DOWN = 0x0000001AU, + ADC_CALLBACK_EVENT_PPB2_ERROR = 0x0000001BU, + ADC_CALLBACK_EVENT_PPB3_ZERO = 0x0000001CU, + ADC_CALLBACK_EVENT_PPB3_UP = 0x0000001DU, + ADC_CALLBACK_EVENT_PPB3_DOWN = 0x0000001EU, + ADC_CALLBACK_EVENT_PPB3_ERROR = 0x0000001FU, +} ADC_CallbackFunType; + +/** + * @brief PPB function enable bit. + */ +typedef struct { + bool detect; /**< Function: zero-crossing detection, upper threshold detection, and lower threshold detection */ + bool offset; /**< Result Data Offset */ + bool delay; /**< Recording the sampling delay */ +} PPB_Function; + +/* + * Each bit indicates the software triggering status of the SOC. The value 1 indicates enable + * and the value 0 indicates disable. + */ +typedef union { + unsigned int softTrigVal; + struct { + unsigned int trigSoc0 : 1; + unsigned int trigSoc1 : 1; + unsigned int trigSoc2 : 1; + unsigned int trigSoc3 : 1; + unsigned int trigSoc4 : 1; + unsigned int trigSoc5 : 1; + unsigned int trigSoc6 : 1; + unsigned int trigSoc7 : 1; + unsigned int trigSoc8 : 1; + unsigned int trigSoc9 : 1; + unsigned int trigSoc10 : 1; + unsigned int trigSoc11 : 1; + unsigned int trigSoc12 : 1; + unsigned int trigSoc13 : 1; + unsigned int trigSoc14 : 1; + unsigned int trigSoc15 : 1; + unsigned int reserved : 16; + } BIT; +} ADC_SoftMultiTrig; + + +/** + * @brief The definition of synchronous sampling parameter structure. + */ +typedef struct { + ADC_OversamplingMultiple multiple; /**< Multiplier of Oversampling Accumulation */ + ADC_OversamplingRightShift rightShift; /**< Select sampling accuracy by shifting right bits */ + bool oversamplingInt; /**< Select sampling accuracy by shifting right bits */ +} ADC_OversamplingParam; + +/** + * @brief The definition of SOC parameter structure. + */ +typedef struct { + ADC_Input adcInput; /**< SOC specified input */ + ADC_SOCSampleCycle sampleTotalTime; /**< SOC specified input sample total time */ + ADC_TrigSource trigSource; /**< SOC specified input periph trigger source */ + bool continueMode; /**< SOC specified input interrupt trigger source */ + ADC_SOCFinishMode finishMode; /**< SOC specified input mode of finishing sample and conversion */ +} SOC_Param; + +/** + * @brief The definition of ADC overflow status. + */ +typedef union { + unsigned int trigOver; + unsigned int dmaReqOver; +} ADC_OverState; + +/** + * @brief The definition of extend handle structure. + */ +typedef struct _ADC_ExtendHandle { +} ADC_ExtendHandle; + +/** + * @brief The definition of callback. + */ +typedef struct { + void (* Int0FinishCallBack)(void *handle); /**< ADC interrupt complete callback function for users */ + void (* Int1FinishCallBack)(void *handle); /**< ADC interrupt complete callback function for users */ + void (* Int2FinishCallBack)(void *handle); /**< ADC interrupt complete callback function for users */ + void (* Int3FinishCallBack)(void *handle); /**< ADC interrupt complete callback function for users */ + void (* DmaFinishCallBack)(void *handle); /**< ADC DMA finish callback function for users */ + void (* OverSamplingFinishCallBack)(void *handle); /**< ADC DMA finish callback function for users */ + void (* DmaErrorCallBack)(void *handle); /**< ADC DMA transmission error callback function for users */ + void (* DmaOverCallBack)(void *handle); /**< ADC DMA overflow callback function for users */ + void (* TrigOverCallBack)(void *handle); /**< ADC DMA overflow callback function for users */ + void (* PPBEventCallBack[EVENT_TYPE])(void *handle); /**< (PPB0~PPB3) PPBx_ZRRO, PPBx_UP,PPBx_DOWN, PPBx_ERROR */ +} ADC_UserCallBack; +/** + * @} + */ + +/* ADC DCL Functions */ +/** + * @brief Check ADC PPB. + * @param ppb PPB number of ADC. + * @retval bool + */ +static inline bool IsADCPostProcessingBlock(ADC_PPBNumber ppb) +{ + return (ppb >= ADC_PPB_NUM0) && (ppb <= ADC_PPB_NUM3); +} + +/** + * @brief Check ADC work mode. + * @param mode work mode of ADC. + * @retval bool + */ +static inline bool IsADCWorkMode(ADC_WorkMode mode) +{ + return (mode >= ADC_WORKMODE_NORMAL) && (mode <= ADC_WORKMODE_CAPACITY1); +} + +/** + * @brief Check ADC oversampling multiple parameter. + * @param multiple oversampling multiple of SOC. + * @retval bool + */ +static inline bool IsADCOversamplingMultiple(ADC_OversamplingMultiple multiple) +{ + return (multiple >= ADC_OVERSAMPLING_8X) && (multiple <= ADC_OVERSAMPLING_256X); +} + +/** + * @brief Check bit of right shift in oversampling. + * @param bit bit of right shift. + * @retval bool + */ +static inline bool IsADCOversamplingRightShift(ADC_OversamplingRightShift bit) +{ + return (bit >= ADC_RIGHTSHIFT_BIT0) && (bit <= ADC_RIGHTSHIFT_BIT8); +} + +/** + * @brief Check ADC sample input. + * @param input Number of input. + * @retval bool + */ +static inline bool IsADCSampleChannel(ADC_Input input) +{ + return (input >= ADC_CH_ADCINA0) && (input <= ADC_CH_ADCINA19); +} + +/** + * @brief Check ADC SOC(start of conversion). Each SOC selects a unique input for sampling. The sample parameters + * are configured through the SOC. + * @param soc Number of SOC. + * @retval bool + */ +static inline bool IsADCSOCx(ADC_SOCNumber soc) +{ + return (soc >= ADC_SOC_NUM0) && (soc <= ADC_SOC_NUM15); +} + +/** + * @brief Check ADC interrupt parameter. + * @param intx Number of interrupt. + * @retval bool + */ +static inline bool IsADCIntx(ADC_IntNumber intx) +{ + return (intx >= ADC_INT_NUMBER0) && (intx <= ADC_INT_NUMBER3); +} + +/** + * @brief Check SOC trigger source. + * @param trig Type of trigger source. + * @retval bool + */ +static inline bool IsADCTrigSource(ADC_TrigSource trig) +{ + return (trig >= ADC_TRIGSOC_SOFT) && (trig <= ADC_TRIGSOC_GPIOPF1); +} + +/** + * @brief Check SOC DMA Request Type. + * @param dmaType Type of DMA Request. + * @retval bool + */ +static inline bool IsADCReqDMAType(ADC_DMARequestType dmaType) +{ + return (dmaType == ADC_DMA_SINGLEREQ) || (dmaType == ADC_DMA_BURSTREQ); +} + +/** + * @brief Check mode of completion of SOC sample + * @param mode Type of completion. + * @retval bool + */ +static inline bool IsADCFinishMode(ADC_SOCFinishMode mode) +{ + return (mode >= ADC_SOCFINISH_NONE) && (mode <= ADC_SOCFINISH_INT3); +} + +/** + * @brief Check ADC sample priority parameter. + * @param mode Priority mode of SOC. + * @retval bool + */ +static inline bool IsADCPriorityMode(ADC_PriorityMode mode) +{ + return (mode >= ADC_PRIMODE_ALL_ROUND) && (mode <= ADC_PRIMODE_ALL_PRIORITY); +} + +/** + * @brief Check time of total ADC sampling time. + * @param acqps Time of total ADC sampling time. + * @retval bool + */ +static inline bool IsADCTotalTime(unsigned int acqps) +{ + return (acqps <= ADC_SOCSAMPLE_500CLK); +} + +/** + * @brief Enable AVDD/3 Channal. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_EnableAvddChannel(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_AVDD_EN.BIT.cfg_avdd_en = true; +} + +/** + * @brief Disable AVDD/3 Channal. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_DisableAvddChannel(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_AVDD_EN.BIT.cfg_avdd_en = false; +} + +/** + * @brief Configuring the interrupt source used by the SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_SetSOCxBlindInt0(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + unsigned int shiftBit = (unsigned int)socx; + adcx->ADC_INT_DATA_0.reg |= (1U << shiftBit); +} + +/** + * @brief Obtains the SOC ID that use interrupt. + * @param adcx ADC register base address. + * @retval unsigned int, Obtains the SOC ID that uses this interrupt. + */ +static inline unsigned int DCL_ADC_GetSOCxBlindInt0(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_INT_DATA_0_REG value; + value.reg = adcx->ADC_INT_DATA_0.reg; + return value.BIT.cfg_intr_data_sel0; +} + +/** + * @brief Configuring the interrupt source used by the SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_SetSOCxBlindInt1(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + unsigned int shiftBit = (unsigned int)socx + 16; /* Offset 16 bits configuration */ + adcx->ADC_INT_DATA_0.reg |= (1U << shiftBit); +} + +/** + * @brief Obtains the SOC ID that use interrupt. + * @param adcx ADC register base address. + * @retval unsigned int, Obtains the SOC ID that uses this interrupt. + */ +static inline unsigned int DCL_ADC_GetSOCxBlindInt1(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_INT_DATA_0_REG value; + value.reg = adcx->ADC_INT_DATA_0.reg; + return value.BIT.cfg_intr_data_sel1; +} + +/** + * @brief Configuring the interrupt source used by the SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_SetSOCxBlindInt2(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + unsigned int shiftBit = (unsigned int)socx; + adcx->ADC_INT_DATA_1.reg |= (1U << shiftBit); +} + +/** + * @brief Obtains the SOC ID that use interrupt. + * @param adcx ADC register base address. + * @retval unsigned int, Obtains the SOC ID that uses this interrupt. + */ +static inline unsigned int DCL_ADC_GetSOCxBlindInt2(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_INT_DATA_1_REG value; + value.reg = adcx->ADC_INT_DATA_1.reg; + return value.BIT.cfg_intr_data_sel2; +} + +/** + * @brief Configuring the interrupt source used by the SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_SetSOCxBlindInt3(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + unsigned int shiftBit = (unsigned int)socx + 16; /* Offset 16 bits configuration */ + adcx->ADC_INT_DATA_1.reg |= (1U << shiftBit); +} + +/** + * @brief Obtains the SOC ID that use interrupt. + * @param adcx ADC register base address. + * @retval unsigned int, Obtains the SOC ID that uses this interrupt. + */ +static inline unsigned int DCL_ADC_GetSOCxBlindInt3(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_INT_DATA_1_REG value; + value.reg = adcx->ADC_INT_DATA_1.reg; + return value.BIT.cfg_intr_data_sel3; +} + +/** + * @brief Enable ADC interrupt. + * @param adcx ADC register base address. + * @param intx Number of ADC interrupt controller, @ref ADC_IntNumber. + * @retval None. + */ +static inline void DCL_ADC_EnableIntx(ADC_RegStruct * const adcx, ADC_IntNumber intx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCIntx(intx)); + adcx->ADC_DATA_FLAG_MASK.reg |= (1U << (unsigned int)intx); +} + +/** + * @brief Disable ADC interrupt. + * @param adcx ADC register base address. + * @param intx Number of ADC interrupt controller, @ref ADC_IntNumber. + * @retval None. + */ +static inline void DCL_ADC_DisableIntx(ADC_RegStruct * const adcx, ADC_IntNumber intx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCIntx(intx)); + adcx->ADC_DATA_FLAG_MASK.reg &= ~(1U << (unsigned int)intx); +} + +/** + * @brief ADC clear interruption. + * @param adcx ADC register base address. + * @param intx Number of ADC interrupt controller, @ref ADC_IntNumber. + * @retval None. + */ +static inline void DCL_ADC_ClearIntx(ADC_RegStruct * const adcx, ADC_IntNumber intx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCIntx(intx)); + adcx->ADC_INT_DATA_FLAG.reg = (1U << (unsigned int)intx); +} + +/** + * @brief Calculate the base address of the SOC registers with different numbers.This interface is invoked by the DCL, + * and parameter verification has been completed at the DCL functions. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval addr, the base address of the SOC registers. + */ +static unsigned int ADC_GetCTRLAddr(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + unsigned int addr; + addr = (uintptr_t)(void *)&(adcx->ADC_SOC0_CFG); + addr += ((unsigned int)socx * 4); /* Register base address difference 4 */ + return addr; +} + +/** + * @brief Configure the corresponding input for the SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @param input ADC input, @ref ADC_Input. + * @retval None. + */ +static inline void DCL_ADC_SOCxSelectChannel(ADC_RegStruct * const adcx, ADC_SOCNumber socx, ADC_Input input) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx) && IsADCSampleChannel(input)); + ADC_SOC0_CFG_REG *soc = NULL; + unsigned int addr = ADC_GetCTRLAddr(adcx, socx); /* Get the Address After Translation */ + soc = (ADC_SOC0_CFG_REG *)(void *)(uintptr_t)addr; + soc->BIT.cfg_soc0_ch_sel = (unsigned int)input; + if (input == ADC_CH_ADCINA18) { + DCL_ADC_EnableAvddChannel(adcx); + } +} + +/** + * @brief Configure the trigger source for the SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @param trig Source of trigger, @ref ADC_TrigSource. + * @retval None. + */ +static inline void DCL_ADC_SOCxSelcetTrigSource(ADC_RegStruct * const adcx, ADC_SOCNumber socx, ADC_TrigSource trig) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx) && IsADCTrigSource(trig)); + unsigned int addr = ADC_GetCTRLAddr(adcx, socx); /* Obtaining the Address for Configuring the SOC */ + ADC_SOC0_CFG_REG *soc = NULL; + soc = (ADC_SOC0_CFG_REG *)(void *)(uintptr_t)addr; + soc->BIT.cfg_soc0_trig_sel = (unsigned int)trig; +} + +/** + * @brief Configure the capacitor charging time for the SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @param acqps Capacitor charging time. + * @retval None. + */ +static inline void DCL_ADC_SOCxSetAcqps(ADC_RegStruct * const adcx, ADC_SOCNumber socx, unsigned int acqps) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + ADC_PARAM_CHECK_NO_RET(acqps <= 15); /* The value of acqps ranges from 0 to 15 */ + unsigned int addr = ADC_GetCTRLAddr(adcx, socx); + ADC_SOC0_CFG_REG *soc = NULL; + soc = (ADC_SOC0_CFG_REG *)(void *)(uintptr_t)addr; + soc->BIT.cfg_soc0_samptime_sel = acqps; +} + +/** + * @brief ADC uses software-triggered sampling. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_SOCxSoftTrigger(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + adcx->ADC_SOFT_TRIG.reg |= (1U << (unsigned int)socx); +} + +/** + * @brief Multiple channels trigger software sampling. + * @param adcx ADC register base address. + * @param val The val bits range from 0 to 0xFFFF. Writing 1 indicates triggering. + * @retval None. + */ +static inline void DCL_ADC_SOCxMultiSoftTrigger(ADC_RegStruct * const adcx, unsigned int val) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(val <= 0xFFFF); /* The value of val ranges from 0 to 0xFFFF */ + adcx->ADC_SOFT_TRIG.reg = val; +} + +/** + * @brief Configuring the SOC Priority. + * @param adcx ADC register base address. + * @param priorityMode Mode of SOC priority, @ref ADC_PriorityMode. + * @retval None. + */ +static inline void DCL_ADC_SOCxSetPriority(ADC_RegStruct * const adcx, ADC_PriorityMode priorityMode) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCPriorityMode(priorityMode)); + adcx->ADC_ARBT0.reg = priorityMode; +} + +/** + * @brief Get current poll pointer. This pointer holds the last converted poll SOC. + * @param adcx ADC register base address. + * @retval None. + */ +static inline unsigned int DCL_ADC_QueryPollPoint(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + return adcx->ADC_ARBT2.reg; +} + +/** + * @brief The poll pointer is reset by software. After the software is set to 1, the rr_pointer is set to 16. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_ResetPollPoint(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_ARBT1.BIT.cfg_rr_pointer_reset = BASE_CFG_SET; +} + +/** + * @brief Set the specified SOC as the DAM request trigger source. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_DMARequestSource(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + adcx->ADC_DMA.BIT.cfg_dma_soc_sel = socx; +} + +/** + * @brief ADC enable DMA burst request. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_EnableDMABurstReq(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_DMA.BIT.cfg_dma_brst_req_sel = BASE_CFG_ENABLE; +} + +/** + * @brief ADC disable DMA burst request. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_DisableDMABurstReq(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_DMA.BIT.cfg_dma_brst_req_sel = BASE_CFG_DISABLE; +} + +/** + * @brief ADC enable DMA single request. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_EnableDMASingleReq(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_DMA.BIT.cfg_dma_sing_req_sel = BASE_CFG_ENABLE; +} + +/** + * @brief ADC disable DMA single request. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_DisableDMASingleReq(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_DMA.BIT.cfg_dma_sing_req_sel = BASE_CFG_DISABLE; +} + +/** + * @brief Configure post processing module(PPB) for the SOC. + * @param adcx ADC register base address. + * @param num Number of PPB. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_SOCxSelectPPBx(ADC_RegStruct * const adcx, ADC_PPBNumber num, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCPostProcessingBlock(num)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + ADC_PPB0_CTRL0_REG *ppb; + uintptr_t addr = (uintptr_t)(void *)&(adcx->ADC_PPB0_CTRL0); + ppb = (ADC_PPB0_CTRL0_REG *)(void *)(addr + 0x10U * (unsigned int)num); /* Get PPB configuration base address */ + ppb->BIT.cfg_ppb0_soc_sel = (unsigned int)socx; +} + +/** + * @brief Set the compensation offset. + * @param adcx ADC register base address. + * @param num Number of PPB. + * @param offset Offset compensation value. + * @retval None. + */ +static inline void DCL_ADC_SetPPBxOffset(ADC_RegStruct * const adcx, ADC_PPBNumber num, unsigned int offset) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCPostProcessingBlock(num)); + ADC_PARAM_CHECK_NO_RET(offset <= 0xFFF); + ADC_PPB0_CTRL0_REG *ppb; + uintptr_t addr = (uintptr_t)(void *)&(adcx->ADC_PPB0_CTRL0); + ppb = (ADC_PPB0_CTRL0_REG *)(void *)(addr + 0x10U * (unsigned int)num); /* Get PPB configuration base address */ + ppb->BIT.cfg_ppb0_offset = offset; +} + +/** + * @brief Setting the PPB Function. + * @param adcx ADC register base address. + * @param num Number of PPB. + * @param fun PPB function configuration. + * @retval None. + */ +static inline void DCL_ADC_SetPPBxFunction(ADC_RegStruct * const adcx, ADC_PPBNumber num, PPB_Function *fun) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCPostProcessingBlock(num)); + ADC_ASSERT_PARAM(fun != NULL); + ADC_PPB0_CTRL0_REG *ppb; + uintptr_t addr = (uintptr_t)(void *)&(adcx->ADC_PPB0_CTRL0); + ppb = (ADC_PPB0_CTRL0_REG *)(void *)(addr + 0x10U * (unsigned int)num); /* Get PPB configuration base address */ + ppb->BIT.cfg_ppb0_detect_en = fun->detect; + ppb->BIT.cfg_ppb0_offset_en = fun->offset; + ppb->BIT.cfg_ppb0_dly_en = fun->delay; +} + +/** + * @brief Set the upper and down thresholds. + * @param adcx ADC register base address. + * @param num Number of PPB. + * @param up Upper threshold, the most significant bit is the sign bit. + * @param dn Down threshold, the most significant bit is the sign bit. + * @retval None. + */ +static inline void DCL_ADC_SetPPBxThreshold(ADC_RegStruct * const adcx, ADC_PPBNumber num, + unsigned int up, unsigned int dn) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCPostProcessingBlock(num)); + ADC_PARAM_CHECK_NO_RET(up <= 0x1FFF); + ADC_PARAM_CHECK_NO_RET(dn <= 0x1FFF); + ADC_PPB0_CTRL1_REG *ppb; + uintptr_t addr = (uintptr_t)(void *)&(adcx->ADC_PPB0_CTRL1); + ppb = (ADC_PPB0_CTRL1_REG *)(void *)(addr + 0x10U * (unsigned int)num); /* Get PPB configuration base address */ + ppb->BIT.cfg_ppb0_uplimit = up; + ppb->BIT.cfg_ppb0_dnlimit = dn; +} + +/** + * @brief Setting the Error reference value. + * @param adcx ADC register base address. + * @param num Number of PPB. + * @param ref Error reference value. + * @retval None. + */ +static inline void DCL_ADC_SetPPBxErrorRef(ADC_RegStruct * const adcx, ADC_PPBNumber num, unsigned int ref) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCPostProcessingBlock(num)); + ADC_PARAM_CHECK_NO_RET(ref <= 0xFFF); + ADC_PPB0_CTRL2_REG *ppb; + uintptr_t addr = (uintptr_t)(void *)&(adcx->ADC_PPB0_CTRL2); + ppb = (ADC_PPB0_CTRL2_REG *)(void *)(addr + 0x10U * (unsigned int)num); /* Get PPB configuration base address */ + ppb->BIT.cfg_ppb0_ref = ref; +} + +/** + * @brief Read sample delay count value. + * @param adcx ADC register base address. + * @param num Number of PPB. + * @retval unsigned int, delay count value. The unit is the system frequency period. + */ +static inline unsigned int DCL_ADC_GetPPBxDelayCnt(ADC_RegStruct * const adcx, ADC_PPBNumber num) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_ASSERT_PARAM(IsADCPostProcessingBlock(num)); + ADC_PPB0_RESULT_REG *ppb; + uintptr_t addr = (uintptr_t)(void *)&(adcx->ADC_PPB0_RESULT); + ppb = (ADC_PPB0_RESULT_REG *)(void *)(addr + 0x10U * (unsigned int)num); + unsigned int dly = ppb->reg; + return (dly >> 16U); /* dly_stamp is in the upper 16 bits */ +} + +/** + * @brief Obtain the error calculation result. + * @param adcx ADC register base address. + * @param num Number of PPB. + * @retval unsigned int, Error Result, the most significant bit is the sign bit. + */ +static inline unsigned int DCL_ADC_GetPPBxErrorResult(ADC_RegStruct * const adcx, ADC_PPBNumber num) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_ASSERT_PARAM(IsADCPostProcessingBlock(num)); + ADC_PPB0_RESULT_REG *ppb; + uintptr_t addr = (uintptr_t)(void *)&(adcx->ADC_PPB0_RESULT); + ppb = (ADC_PPB0_RESULT_REG *)(void *)(addr + 0x10U * (unsigned int)num); /* Get PPB configuration base address */ + return ppb->BIT.ppb0_error_data; +} + +/** + * @brief Check whether the error calculation result is complete. + * @param adcx ADC register base address. + * @param num Number of PPB. + * @retval unsigned int, Not 0: Finish, 0: Not finish. + */ +static inline unsigned int DCL_ADC_CheckPPBxErrorResultFinish(ADC_RegStruct * const adcx, ADC_PPBNumber num) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_ASSERT_PARAM(IsADCPostProcessingBlock(num)); + unsigned int value = adcx->ADC_EVENT_INT.reg; + unsigned int shfit = 3 + 4 * num; /* 3 and 4 are used to convert the error result status bits */ + value = (value & (1U << shfit)); + return value; +} + +/** + * @brief Enable PPB interrupts. + * @param adcx ADC register base address. + * @retval void. + */ +static inline void DCL_ADC_EnablePPBxEventInt(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_EVENT_INT_MASK.reg |= 0xFFFF; +} + +/** + * @brief Disable PPB interrupts. + * @param adcx ADC register base address. + * @retval void. + */ +static inline void DCL_ADC_DisablePPBxEventInt(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + unsigned int value = adcx->ADC_EVENT_INT_MASK.reg; + value = (value & 0xFFFF0000); + adcx->ADC_EVENT_INT_MASK.reg = value; +} + +/** + * @brief Clear PPB interrupt. + * @param adcx ADC register base address. + * @retval void. + */ +static inline void DCL_ADC_ClearPPBxEventInt(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_EVENT_INT.reg |= 0xFFFF; +} + +/** + * @brief Get the status of event interrupt. + * @param adcx ADC register base address. + * @retval unsigned int, status of event interrupt. + */ +static inline unsigned int DCL_ADC_GetEventIntStatus(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + return adcx->ADC_EVENT_INT_MSK.reg; +} + +/** + * @brief Read ADC conversion result. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval unsigned int, result. + */ +static inline unsigned int DCL_ADC_ReadSOCxResult(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_ASSERT_PARAM(IsADCSOCx(socx)); + ADC_RESULT0_REG *result; + uintptr_t addr = (uintptr_t)(void *)adcx; + /* The address interval of the result register is 4 */ + result = (ADC_RESULT0_REG *)(void *)(addr + 4 * (unsigned int)socx); + return result->reg; +} + +/** + * @brief Obtain the ADC oversampling status. + * @param adcx ADC register base address. + * @retval unsigned int, 1: Finish, 0: Not finish. + */ +static inline unsigned int DCL_ADC_GetOversamplingState(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + return adcx->ADC_EVENT_INT.BIT.intr_oversamp_data_vld; +} + +/** + * @brief Reset the ADC oversampling status, also clear oversampling interrupt. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_ResetOversamplingState(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_EVENT_INT.BIT.intr_oversamp_data_vld = BASE_CFG_SET; +} + +/** + * @brief Read ADC oversampling conversion result. + * @param adcx ADC register base address. + * @retval None. + */ +static inline unsigned int DCL_ADC_ReadOversamplingResult(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + return adcx->ADC_OVERSAMP_RESULT.reg; +} + +/** + * @brief Select SOC Progress Oversampling. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_SoCSelectOversampling(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + adcx->ADC_OVERSAMP.BIT.cfg_oversamp_soc_sel = socx; +} + +/** + * @brief Setting Oversampling Parameters. + * @param adcx ADC register base address. + * @param multiple ADC oversampling Accumulation Multiple. + * @param rightShift Number of bits shifted right in the oversampling result, used for truncation precision. + * @retval None. + */ +static inline void DCL_ADC_SetOversamplingParam(ADC_RegStruct * const adcx, ADC_OversamplingMultiple multiple, + ADC_OversamplingRightShift rightShift) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCOversamplingMultiple(multiple)); + ADC_PARAM_CHECK_NO_RET(IsADCOversamplingMultiple(rightShift)); + adcx->ADC_OVERSAMP.BIT.cfg_oversamp_n = multiple; /* Configuring the Oversampling Multiple */ + adcx->ADC_OVERSAMP.BIT.cfg_oversamp_m = rightShift; /* Configuring the Bits Shifted Right in Oversampling */ +} + +/** + * @brief Enable oversampling function. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_EnableOversampling(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_OVERSAMP.BIT.cfg_oversamp_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disbale oversampling function. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_DisableOversampling(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_OVERSAMP.BIT.cfg_oversamp_en = BASE_CFG_DISABLE; +} + +/** + * @brief Enable ADC oversampling interrupt. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_EnableOversamplingInt(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_EVENT_INT_MASK.BIT.intr_oversamp_data_vld_mask = BASE_CFG_ENABLE; +} + +/** + * @brief Disable ADC oversampling interrupt. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_DisableOversamplingInt(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_EVENT_INT_MASK.BIT.intr_oversamp_data_vld_mask = BASE_CFG_DISABLE; +} + +/** + * @brief Enable Analog Power. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_Enable(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_EN.BIT.cfg_adc_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable Analog Power. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_Disable(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_EN.BIT.cfg_adc_en = BASE_CFG_DISABLE; +} + +/** + * @brief Obtain the SOC conversion status. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval unsigned int, Not 0: Finish, 0: Not finish. + */ +static inline unsigned int DCL_ADC_GetConvState(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_ASSERT_PARAM(IsADCSOCx(socx)); + unsigned int ret = adcx->ADC_EOC_FLAG.reg; + return (ret & ((1U << (unsigned int)socx))); +} + +/** + * @brief Clears the SOC completion flag. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_ResetConvState(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + unsigned int ret = (1U << (unsigned int)socx); + adcx->ADC_EOC_FLAG.reg = ret; +} + +/** + * @brief Obtains the input ID currently configured for the SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval unisgned int, input number of soc. + */ +static inline unsigned int DCL_ADC_GetSOCxInputChannel(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_ASSERT_PARAM(IsADCSOCx(socx)); + unsigned int address = (uintptr_t)(void *)&(adcx->ADC_SOC0_CFG); + address += ((unsigned int)socx * 4); /* Register base address difference 4 */ + ADC_SOC0_CFG_REG *soc = NULL; + soc = (ADC_SOC0_CFG_REG *)(void *)(uintptr_t)address; + return soc->BIT.cfg_soc0_ch_sel; +} + +/** + * @brief Enable SOC for continuous conversion. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_EnableSOCxContinue(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + unsigned int addr = ADC_GetCTRLAddr(adcx, socx); /* Obtains the SOC base address */ + ADC_SOC0_CFG_REG *soc = NULL; + soc = (ADC_SOC0_CFG_REG *)(void *)(uintptr_t)addr; + soc->BIT.cfg_soc0_cont_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable SOC for continuous conversion. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_DisableSOCxContinue(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + unsigned int addr = ADC_GetCTRLAddr(adcx, socx); /* Obtains the SOC base address */ + ADC_SOC0_CFG_REG *soc = NULL; + soc = (ADC_SOC0_CFG_REG *)(void *)(uintptr_t)addr; + soc->BIT.cfg_soc0_cont_en = BASE_CFG_DISABLE; +} + +/** + * @brief Set the working mode. + * @param adcx ADC register base address. + * @param mode Work mode of ADC. + * @retval None. + */ +static inline void DCL_ADC_SetWorkMode(ADC_RegStruct * const adcx, ADC_WorkMode mode) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCWorkMode(mode)); + adcx->ADC_MODE.reg = mode; +} + +/** + * @brief Enable error interrupt. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_EnableErrorInt(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_ERR_INT_MASK.reg = 0x1FFFF; +} + +/** + * @brief Disbale error interrupt. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_DisbaleErrorInt(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_ERR_INT_MASK.reg = BASE_CFG_DISABLE; +} + +/** + * @brief Clear error interrupt. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_ClearErrorInt(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + unsigned int overFlag = adcx->ADC_ERR_INT.reg; + adcx->ADC_ERR_INT.reg = overFlag; +} + +/** + * @brief Get status of error interrupt. + * @param adcx ADC register base address. + * @retval unsigned int, status of error interrupt. + */ +static inline unsigned int DCL_ADC_GetErrorIntStatus(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + return adcx->ADC_ERR_INT_MSK.reg; +} + +/** + * @brief Obtains the ADC controller status. + * @param adcx ADC register base address. + * @retval unsigned int, ADC controller status. + */ +static inline unsigned int DCL_ADC_GetControllerStatus(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + return adcx->ADC_STATUS.reg; +} + +/** + * @brief Obtains the ADC controller status. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @param offset Customized calibration offset parameter.12-bit signed decimal number. The most significant bit is the + * sign bit, and the least significant bit is the one-bit decimal place. The value is stored in twos complement format. + * @param gain Customized calibration gain parameter.13-bit unsigned decimal number. The most significant bit is an + * integer bit, and the other bits are 12-bit decimal places. + * @retval None. + */ +static inline void DCL_ADC_CalibrationGroup0(ADC_RegStruct * const adcx, ADC_SOCNumber socx, + unsigned int offset, unsigned int gain) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + ADC_PARAM_CHECK_NO_RET(offset <= 0xFFF); + ADC_PARAM_CHECK_NO_RET(gain <= 0x1FFF); + adcx->ADC_OEGE_CH_SEL.BIT.cfg_oege_ch_sel0 = socx; + adcx->ADC_OEGE_CTRL0.BIT.cfg_ofst0 = offset; /* Configure the offset */ + adcx->ADC_OEGE_CTRL0.BIT.cfg_gain0 = gain; /* Configure the gain */ +} + + +/** + * @brief Obtains the ADC controller status. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @param offset Customized calibration offset parameter.12-bit signed decimal number. The most significant bit is the + * sign bit, and the least significant bit is the one-bit decimal place. The value is stored in twos complement format. + * @param gain Customized calibration gain parameter.13-bit unsigned decimal number. The most significant bit is an + * integer bit, and the other bits are 12-bit decimal places. + * @retval None. + */ +static inline void DCL_ADC_CalibrationGroup1(ADC_RegStruct * const adcx, ADC_SOCNumber socx, + unsigned int offset, unsigned int gain) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + ADC_PARAM_CHECK_NO_RET(offset <= 0xFFF); + ADC_PARAM_CHECK_NO_RET(gain <= 0x1FFF); + adcx->ADC_OEGE_CH_SEL.BIT.cfg_oege_ch_sel1 = socx; + adcx->ADC_OEGE_CTRL1.BIT.cfg_ofst1 = offset; /* Configure the offset */ + adcx->ADC_OEGE_CTRL1.BIT.cfg_gain1 = gain; /* Configure the gain */ +} + +/** + * @brief Obtains the ADC controller status. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @param offset Customized calibration offset parameter.12-bit signed decimal number. The most significant bit is the + * sign bit, and the least significant bit is the one-bit decimal place. The value is stored in twos complement format. + * @param gain Customized calibration gain parameter.13-bit unsigned decimal number. The most significant bit is an + * integer bit, and the other bits are 12-bit decimal places. + * @retval None. + */ +static inline void DCL_ADC_CalibrationGroup2(ADC_RegStruct * const adcx, ADC_SOCNumber socx, + unsigned int offset, unsigned int gain) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + ADC_PARAM_CHECK_NO_RET(offset <= 0xFFF); + ADC_PARAM_CHECK_NO_RET(gain <= 0x1FFF); + adcx->ADC_OEGE_CH_SEL.BIT.cfg_oege_ch_sel2 = socx; + adcx->ADC_OEGE_CTRL2.BIT.cfg_ofst2 = offset; /* Configure the offset */ + adcx->ADC_OEGE_CTRL2.BIT.cfg_gain2 = gain; /* Configure the gain */ +} +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_ADC_IP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/adc/src/adc.c b/vendor/xinlingyu_92_3061M/Project/drivers/adc/src/adc.c new file mode 100644 index 0000000000000000000000000000000000000000..fd90dde466d90607d761b02972d528a9721f972b --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/adc/src/adc.c @@ -0,0 +1,620 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file adc.c + * @author MCU Driver Team + * @brief ADC module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the ADC. + * + ADC initialization function. + * + Start ADC sample and conversion. + * + Start ADC sample and conversion with interrupt. + * + Start ADC sample and conversion with DMA. + * + Query the ADC conversion result. + * + Single and multichannel software trigger functions. + * + Interrupt callback function and user registration function. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "adc.h" +#include "crg.h" + +/** + * @brief Initialize the ADC hardware controller.After the controller is initialized, the ADC sampling is + * triggered at least 100 us later. + * @param adcHandle ADC handle. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_ADC_Init(ADC_Handle *adcHandle) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_PARAM_CHECK_WITH_RET(IsADCPriorityMode(adcHandle->socPriority) == true, BASE_STATUS_ERROR); + DCL_ADC_SOCxSetPriority(adcHandle->baseAddress, adcHandle->socPriority); + adcHandle->baseAddress->ADC_ANA_CTRL0.BIT.cfg_sar_samp_cap_sel = 0x4; /* Set the Number of Sampling Capacitors */ + adcHandle->baseAddress->ADC_EN.reg = BASE_CFG_ENABLE; /* Enable ADC Controller */ + BASE_FUNC_DelayUs(100); /* Wait for 100 us until the ADC controller is stable */ + return BASE_STATUS_OK; +} + +/** + * @brief DeInitialize the ADC hardware controller. + * @param adcHandle ADC handle. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_ADC_Deinit(ADC_Handle *adcHandle) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + adcHandle->baseAddress->ADC_EN.reg = BASE_CFG_DISABLE; + return BASE_STATUS_OK; +} + +/** + * @brief configurating the specified SOC parameters. + * @param adcHandle ADC handle. + * @param soc ID of SOC(start of conversion), managing the specific sample inputs. + * @param socParam Param struct of SOC. This is related to the peripheral circuit design, @ref SOC_Param. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_ADC_ConfigureSoc(ADC_Handle *adcHandle, ADC_SOCNumber soc, SOC_Param *socParam) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + ADC_ASSERT_PARAM(socParam != NULL); + ADC_PARAM_CHECK_WITH_RET(IsADCSampleChannel(socParam->adcInput) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCTotalTime(socParam->sampleTotalTime) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCTrigSource(socParam->trigSource) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCFinishMode(socParam->finishMode) == true, BASE_STATUS_ERROR); + DCL_ADC_SOCxSelectChannel(adcHandle->baseAddress, soc, socParam->adcInput); /* Set channel */ + DCL_ADC_SOCxSetAcqps(adcHandle->baseAddress, soc, socParam->sampleTotalTime); /* Set sampling time */ + DCL_ADC_SOCxSelcetTrigSource(adcHandle->baseAddress, soc, socParam->trigSource); /* Set trigger source */ + if (socParam->continueMode == true) { /* Continuous Mode Judgment */ + DCL_ADC_EnableSOCxContinue(adcHandle->baseAddress, soc); + } else { + DCL_ADC_DisableSOCxContinue(adcHandle->baseAddress, soc); + } + adcHandle->ADC_SOCxParam[soc].finishMode = socParam->finishMode; + return BASE_STATUS_OK; +} + +/** + * @brief Callback function that ADC completes the sample conversion and uses the DMA to complete the transmission. + * @param handle ADC handle. + * @retval None. + */ +static void ADC_DMATransFinish(void *handle) +{ + ADC_ASSERT_PARAM(handle != NULL); + ADC_Handle *adcHandle = (ADC_Handle *)(handle); + if (adcHandle->userCallBack.DmaFinishCallBack != NULL) { + adcHandle->userCallBack.DmaFinishCallBack(adcHandle); /* Callback User Registration Function */ + } + return; +} + +/** + * @brief Callback function that ADC falis to use DMA. + * @param handle ADC handle. + * @retval None. + */ +static void ADC_DMATransError(void *handle) +{ + ADC_ASSERT_PARAM(handle != NULL); + ADC_Handle *adcHandle = (ADC_Handle *)(handle); + if (adcHandle->userCallBack.DmaErrorCallBack != NULL) { + adcHandle->userCallBack.DmaErrorCallBack(adcHandle); /* Callback User Registration Function */ + } + return; +} + +/** + * @brief Start the ADC conversion and enable ADC DMA. After the SOC conversion using the DMA is complete, use the DMA + * to transfer data The DMA can transfer the sampling results of consecutive SOCs. The start and end of DMA transfer + * are determined by startSoc and endSoc. + * @param adcHandle ADC handle. + * @param startSoc First SOC result for DMA transfer. + * @param endSoc Last SOC result for DMA transfer. + * @param saveData Address where the converted result is saved. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_ADC_StartDma(ADC_Handle *adcHandle, unsigned int startSoc, + unsigned int endSoc, unsigned int *saveData) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(startSoc) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(endSoc) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(startSoc <= endSoc, BASE_STATUS_ERROR); + ADC_ASSERT_PARAM(saveData != NULL); + ADC_ASSERT_PARAM(adcHandle->dmaHandle != NULL); + ADC_PARAM_CHECK_WITH_RET(IsDmaChannelNum(adcHandle->adcDmaChn) == true, BASE_STATUS_ERROR); + unsigned int dmaSOCx = 0; + unsigned int dataLength = endSoc - startSoc + 1; + for (int i = 0; i < SOC_MAX_NUM; i++) { /* The DMA request is generated by the last SOC */ + if (adcHandle->ADC_SOCxParam[i].finishMode == ADC_SOCFINISH_DMA) { + dmaSOCx = i; + } + } + DCL_ADC_DMARequestSource(adcHandle->baseAddress, dmaSOCx); /* Enable the DMA function of the ADC */ + DCL_ADC_EnableDMABurstReq(adcHandle->baseAddress); /* Enable the DMA burst request */ + DCL_ADC_EnableDMASingleReq(adcHandle->baseAddress); /* Enable the DMA single request */ + uintptr_t srcAddr = (uintptr_t)(void *)(adcHandle->baseAddress); + srcAddr = srcAddr + 4 * startSoc; /* The base address difference of adjacent SOC result registers is 4 */ + adcHandle->dmaHandle->userCallBack.DMA_CallbackFuns[adcHandle->adcDmaChn].ChannelFinishCallBack = + ADC_DMATransFinish; + adcHandle->dmaHandle->userCallBack.DMA_CallbackFuns[adcHandle->adcDmaChn].ChannelErrorCallBack = ADC_DMATransError; + BASE_StatusType ret = HAL_DMA_StartIT(adcHandle->dmaHandle, srcAddr, (uintptr_t)(void *)(saveData), + dataLength, adcHandle->adcDmaChn); + return ret; +} + +/** + * @brief Start the ADC conversion and enable ADC interrupt. After the SOC completes sample conversion, the ADC + * interrupt is reported. + * @param adcHandle ADC handle. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_ADC_StartIt(ADC_Handle *adcHandle) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + unsigned int intVal = 0; + for (int i = 0; i < SOC_MAX_NUM; i++) { + intVal = adcHandle->ADC_SOCxParam[i].finishMode; + switch (intVal) { + case ADC_SOCFINISH_INT0: + DCL_ADC_SetSOCxBlindInt0(adcHandle->baseAddress, i); /* The SOC selects to use interrupt 0 */ + break; + case ADC_SOCFINISH_INT1: + DCL_ADC_SetSOCxBlindInt1(adcHandle->baseAddress, i); /* The SOC selects to use interrupt 1 */ + break; + case ADC_SOCFINISH_INT2: + DCL_ADC_SetSOCxBlindInt2(adcHandle->baseAddress, i); /* The SOC selects to use interrupt 2 */ + break; + case ADC_SOCFINISH_INT3: + DCL_ADC_SetSOCxBlindInt3(adcHandle->baseAddress, i); /* The SOC selects to use interrupt 3 */ + break; + default: + break; + } + } /* Enable ADC Interrupt */ + DCL_ADC_EnableIntx(adcHandle->baseAddress, ADC_INT_NUMBER0); + DCL_ADC_EnableIntx(adcHandle->baseAddress, ADC_INT_NUMBER1); + DCL_ADC_EnableIntx(adcHandle->baseAddress, ADC_INT_NUMBER2); + DCL_ADC_EnableIntx(adcHandle->baseAddress, ADC_INT_NUMBER3); + return BASE_STATUS_OK; +} + +/** + * @brief The software triggers multiple SCOs for sampling at the same time. + * @param adcHandle ADC handle. + * @param syncTrig Triggering Parameters. The lower 16 bits correspond to one SOC. If this bit is set to 1, the + * software triggers the SOC. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_ADC_SoftTrigMultiSample(ADC_Handle *adcHandle, ADC_SoftMultiTrig syncTrig) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + unsigned int val = syncTrig.softTrigVal; + ADC_PARAM_CHECK_WITH_RET(val <= 0xFFFF, BASE_STATUS_ERROR); + DCL_ADC_SOCxMultiSoftTrigger(adcHandle->baseAddress, val); /* Software triggering for multiple SOC */ + return BASE_STATUS_OK; +} + +/** + * @brief The software triggers only one soc. + * @param adcHandle ADC handle. + * @param soc ID of SOC. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_ADC_SoftTrigSample(ADC_Handle *adcHandle, unsigned int soc) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + DCL_ADC_SOCxSoftTrigger(adcHandle->baseAddress, soc); /* Software triggers a single SOC */ + return BASE_STATUS_OK; +} + +/** + * @brief Obtains the sample result after SOC conversion. + * @param adcHandle ADC handle. + * @param soc ID of SOC. + * @retval unsigned int value of ADC convert result. + */ +unsigned int HAL_ADC_GetConvResult(ADC_Handle *adcHandle, unsigned int soc) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + return DCL_ADC_ReadSOCxResult(adcHandle->baseAddress, soc); +} + + +/** + * @brief Check the SOC completion flag. + * @param adcHandle ADC handle. + * @param soc ID of SOC. + * @retval BASE_STATUS_ERROR: The SOC does not complete the data sampling conversion. + * @retval BASE_STATUS_OK: The SOC has completed data sampling conversion. + */ +BASE_StatusType HAL_ADC_CheckSocFinish(ADC_Handle *adcHandle, unsigned int soc) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + if (DCL_ADC_GetConvState(adcHandle->baseAddress, soc) == 0) { + return BASE_STATUS_ERROR; /* The SOC does not complete the conversion */ + } + DCL_ADC_ResetConvState(adcHandle->baseAddress, soc); /* Clear flag bit */ + return BASE_STATUS_OK; +} + +/** + * @brief The ADC completes the interrupt processing. + * @param adcHandle ADC handle. + * @param intx ADC interrupt type number @ref ADC_IntNumber. + * @retval None. + */ +static void ADC_IntxClearEoc(ADC_Handle *adcHandle, unsigned int intx) +{ + unsigned int eocFlag = adcHandle->baseAddress->ADC_EOC_FLAG.reg; + ADC_INT_DATA_0_REG intData0; + ADC_INT_DATA_1_REG intData1; + unsigned int eocMask = 0; + switch (intx) { + case ADC_INT_NUMBER0: /* Read Interrupt Configuration */ + intData0.reg = adcHandle->baseAddress->ADC_INT_DATA_0.reg; + eocMask = intData0.BIT.cfg_intr_data_sel0; + break; + case ADC_INT_NUMBER1: /* Read Interrupt Configuration */ + intData0.reg = adcHandle->baseAddress->ADC_INT_DATA_0.reg; + eocMask = intData0.BIT.cfg_intr_data_sel1; + break; + case ADC_INT_NUMBER2: /* Read Interrupt Configuration */ + intData1.reg = adcHandle->baseAddress->ADC_INT_DATA_1.reg; + eocMask = intData1.BIT.cfg_intr_data_sel2; + break; + case ADC_INT_NUMBER3: /* Read Interrupt Configuration */ + intData1.reg = adcHandle->baseAddress->ADC_INT_DATA_1.reg; + eocMask = intData1.BIT.cfg_intr_data_sel3; + break; + default: + break; + } + unsigned int eoc = eocFlag & eocMask; + adcHandle->ADC_IntxParam[intx].socxFinish = eoc; + for (int i = 0; i < SOC_MAX_NUM; i++) { + unsigned int val = (1 << i); + if (eoc & val) { + adcHandle->baseAddress->ADC_EOC_FLAG.reg = val; /* Clear the EOC flag */ + } + } +} + +/** + * @brief The ADC overflow interrupt processing + * @param adcHandle ADC handle. + * @retval None. + */ +void HAL_ADC_IrqHandlerOver(void *handle) +{ + ADC_ASSERT_PARAM(handle != NULL); + ADC_Handle *adcHandle = (ADC_Handle *)handle; + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + unsigned int overState = adcHandle->baseAddress->ADC_ERR_INT_MSK.reg; + unsigned int overFlag = adcHandle->baseAddress->ADC_ERR_INT.reg; + adcHandle->baseAddress->ADC_ERR_INT.reg = overFlag; + adcHandle->overState.trigOver = (overState & 0xFFFF); /* Save trigger overflow status */ + adcHandle->overState.dmaReqOver = (overState & 0x10000); /* Save dma request overflow status */ + if (adcHandle->userCallBack.TrigOverCallBack != NULL && adcHandle->overState.trigOver != 0) { + adcHandle->userCallBack.TrigOverCallBack(handle); /* Callback User Registration Function */ + } + if (adcHandle->userCallBack.DmaOverCallBack != NULL && adcHandle->overState.dmaReqOver != 0) { + adcHandle->userCallBack.DmaOverCallBack(handle); /* Callback User Registration Function */ + } +} + +#if defined (CHIP_3061MNPICA) || defined (CHIP_3061MNPIKA) || defined (CHIP_3061MNPIC8) || defined (CHIP_3061MNPIK8) +/** + * @brief ADC Interrupt0 service processing function. + * @param handle ADC handle. + * @retval None. + */ +void HAL_ADC_IrqHandlerInt0(void *handle) +{ + ADC_ASSERT_PARAM(handle != NULL); + ADC_Handle *adcHandle = (ADC_Handle *)handle; + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_IntxClearEoc(adcHandle, ADC_INT_NUMBER0); /* Clear conversion completion flag */ + DCL_ADC_ClearIntx(adcHandle->baseAddress, ADC_INT_NUMBER0); + if (adcHandle->userCallBack.Int0FinishCallBack != NULL) { + adcHandle->userCallBack.Int0FinishCallBack(handle); + } +} +#endif +/** + * @brief ADC Interrupt1 service processing function. + * @param handle ADC handle. + * @retval None. + */ +void HAL_ADC_IrqHandlerInt1(void *handle) +{ + ADC_ASSERT_PARAM(handle != NULL); + ADC_Handle *adcHandle = (ADC_Handle *)handle; + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_IntxClearEoc(adcHandle, ADC_INT_NUMBER1); /* Clear conversion completion flag */ + DCL_ADC_ClearIntx(adcHandle->baseAddress, ADC_INT_NUMBER1); + if (adcHandle->userCallBack.Int1FinishCallBack != NULL) { + adcHandle->userCallBack.Int1FinishCallBack(handle); + } +} + +/** + * @brief ADC Interrupt2 service processing function. + * @param handle ADC handle. + * @retval None. + */ +void HAL_ADC_IrqHandlerInt2(void *handle) +{ + ADC_ASSERT_PARAM(handle != NULL); + ADC_Handle *adcHandle = (ADC_Handle *)handle; + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_IntxClearEoc(adcHandle, ADC_INT_NUMBER2); /* Clear conversion completion flag */ + DCL_ADC_ClearIntx(adcHandle->baseAddress, ADC_INT_NUMBER2); + if (adcHandle->userCallBack.Int2FinishCallBack != NULL) { + adcHandle->userCallBack.Int2FinishCallBack(handle); + } +} + +/** + * @brief ADC Interrupt3 service processing function. + * @param handle ADC handle. + * @retval None. + */ +void HAL_ADC_IrqHandlerInt3(void *handle) +{ + ADC_ASSERT_PARAM(handle != NULL); + ADC_Handle *adcHandle = (ADC_Handle *)handle; + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_IntxClearEoc(adcHandle, ADC_INT_NUMBER3); /* Clear conversion completion flag */ + DCL_ADC_ClearIntx(adcHandle->baseAddress, ADC_INT_NUMBER3); + if (adcHandle->userCallBack.Int3FinishCallBack != NULL) { + adcHandle->userCallBack.Int3FinishCallBack(handle); + } +} +/** + * @brief Event interrupt callback processing. + * @param adcHandle ADC handle. + * @param ppb Work mode of ADC. + * @param eventStatus Status of the event interrupt. + * @retval None. + */ +static void ADC_EventCallBack(ADC_Handle *handle, unsigned int ppb, unsigned int eventStatus) +{ + for (unsigned int i = 0; i < 4; ++i) { /* Each PPB has 4 interrupt types */ + unsigned int index = 4 * ppb + i; /* Each PPB has 4 interrupt types */ + if (handle->userCallBack.PPBEventCallBack[index] != NULL && (eventStatus & (1U << index)) != 0) { + handle->userCallBack.PPBEventCallBack[index](handle); + } + } +} +/** + * @brief ADC extended interrupt service processing function. + * @param handle Event handle. + * @retval None. + */ +void HAL_ADC_IrqHandlerAllEvent(void *handle) +{ + ADC_ASSERT_PARAM(handle != NULL); + ADC_Handle *adcHandle = (ADC_Handle *)handle; + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + unsigned int eventStatus = adcHandle->baseAddress->ADC_EVENT_INT_MSK.reg; + if (adcHandle->baseAddress->ADC_EVENT_INT_MSK.BIT.intr_oversamp_data_vld_msk == BASE_CFG_ENABLE) { + adcHandle->baseAddress->ADC_EVENT_INT.BIT.intr_oversamp_data_vld = BASE_CFG_SET; + if (adcHandle->userCallBack.OverSamplingFinishCallBack != NULL) { + adcHandle->userCallBack.OverSamplingFinishCallBack(handle); /* Oversampling callback function */ + } + return; + } + for (unsigned int i = 0; i < 4; ++i) { /* Each ADC has 4 PPB */ + unsigned int tmp = 0xF << (4U * i); /* Each PPB has 4 interrupt types */ + if ((tmp & eventStatus) != 0) { + adcHandle->baseAddress->ADC_EVENT_INT.reg = tmp; + ADC_EventCallBack(handle, i, eventStatus); /* PPB event callback function */ + break; + } + } + return; +} + +/** + * @brief User callback function registration interface for event type. + * @param adcHandle ADC handle. + * @param typeID Id of callback function type. + * @param pCallback Pointer of the specified callbcak function. + * @retval None. + */ +static void ADC_RegieterEventCallBack(ADC_Handle *adcHandle, ADC_CallbackFunType typeID, ADC_CallbackType pCallback) +{ + if (typeID > ADC_CALLBACK_EVENT_PPB3_ERROR || typeID < ADC_CALLBACK_EVENT_PPB0_ZERO) { + return; + } + unsigned int index = ((unsigned int)typeID & 0xF); + adcHandle->userCallBack.PPBEventCallBack[index] = pCallback; +} + +/** + * @brief User callback function registration interface. + * @param adcHandle ADC handle. + * @param typeID Id of callback function type. + * @param pCallback Pointer of the specified callbcak function. + * @retval None. + */ +void HAL_ADC_RegisterCallBack(ADC_Handle *adcHandle, ADC_CallbackFunType typeID, ADC_CallbackType pCallback) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(pCallback != NULL); + switch (typeID) { /* Register the callback function based on the interrupt type */ + case ADC_CALLBACK_INT0: + adcHandle->userCallBack.Int0FinishCallBack = pCallback; /* Sampling finsish interrupt 0 callback function */ + break; + case ADC_CALLBACK_INT1: + adcHandle->userCallBack.Int1FinishCallBack = pCallback; /* Sampling finsish interrupt 1 callback function */ + break; + case ADC_CALLBACK_INT2: + adcHandle->userCallBack.Int2FinishCallBack = pCallback; /* Sampling finsish interrupt 2 callback function */ + break; + case ADC_CALLBACK_INT3: + adcHandle->userCallBack.Int3FinishCallBack = pCallback; /* Sampling finsish interrupt 3 callback function */ + break; + case ADC_CALLBACK_DMA: + adcHandle->userCallBack.DmaFinishCallBack = pCallback; /* Dma transfer finish callback function */ + break; + case ADC_CALLBACK_DMAERROR: + adcHandle->userCallBack.DmaErrorCallBack = pCallback; /* Dma transfer error callback function */ + break; + case ADC_CALLBACK_DMAOVER: + adcHandle->userCallBack.DmaOverCallBack = pCallback; /* Dma request over callback function */ + break; + case ADC_CALLBACK_TRIGOVER: + adcHandle->userCallBack.TrigOverCallBack = pCallback; /* trigger over callback function */ + break; + case ADC_CALLBACK_EVENT_OVERSAMPLING: /* Oversampling callback function */ + adcHandle->userCallBack.OverSamplingFinishCallBack = pCallback; + break; + default: + ADC_RegieterEventCallBack(adcHandle, typeID, pCallback); /* PPB Function Callback Function */ + break; + } +} + + +/** + * @brief Initialize the ADC and DAC for VDDA. + * Note: + * (1) Ensure that the ADC clock is turned on and the ADC has been initialized using before use. + * (2) The mapping between the ADC and DAC must be configured as follows: + * ADC0 -- DAC0 + * (3) The soc parameter must be set to an SOC that is not occupied in the ADC. + * (4) The user-configured DAC output value need >= 512. + * @param dacx DAC register base address. + * @param adcx ADC register base address. + * @param soc ID of SOC(start of conversion), managing the specific sample inputs. + * @param dacx DAC register base address. + * @param useDac ture: dacx has been used, false: dacx has not been used. + * @retval BASE_StatusType. + */ +BASE_StatusType HAL_ADC_InitForVdda(ADC_RegStruct *adcx, ADC_SOCNumber soc, DAC_RegStruct *dacx, bool useDac) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_ASSERT_PARAM(IsDACInstance(dacx)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + HAL_CRG_IpEnableSet(DAC0_BASE, IP_CLK_ENABLE); /* DAC0 clock enable. */ + HAL_CRG_IpClkSelectSet(DAC0_BASE, 0); + DAC_Handle dac = {0}; + dac.baseAddress = dacx; + /* DAC cannot be full scale, otherwise ADC will not sense the power supply fluctuation of AVDD */ + unsigned int valueOfDac = 892; /* 892 is the recommended value for the DAC */ + if (useDac == false) { /* Check whether the DAC is used */ + dac.dacValue = valueOfDac; + HAL_DAC_Init(&dac); + } else { + valueOfDac = dac.baseAddress->DAC_VALUE.reg; + } + if (valueOfDac < 512) { /* The user-configured DAC output value need >= 512 */ + return BASE_STATUS_ERROR; + } + ADC_Handle adc = {0}; + adc.baseAddress = adcx; + SOC_Param socParam = {0}; + socParam.adcInput = ADC_CH_ADCINA17; /* DAC input */ + socParam.sampleTotalTime = ADC_SOCSAMPLE_500CLK; /* adc sample total time set as 500 cycle */ + socParam.trigSource = ADC_TRIGSOC_SOFT; + socParam.continueMode = BASE_CFG_DISABLE; + socParam.finishMode = ADC_SOCFINISH_NONE; + HAL_ADC_ConfigureSoc(&adc, soc, &socParam); + return BASE_STATUS_OK; +} + +/** + * @brief The DAC is sampled by using the ADC and converted to the VDDA voltage of the DAC. + * @param adcx ADC register base address. + * @param soc ID of SOC(start of conversion), managing the specific sample inputs. + * @param dacx DAC register base address. + * @param useDac ture: dacx has been used, false: dacx has not been used. + * @retval float, The reference voltage. + */ +float HAL_ADC_GetVddaByDac(ADC_RegStruct *adcx, ADC_SOCNumber soc, DAC_RegStruct *dacx, bool useDac) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_ASSERT_PARAM(IsDACInstance(dacx)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + unsigned int valueOfDac = 892; /* 892 is the recommended value for the DAC */ + if (useDac == true) { /* Check whether the DAC is used */ + valueOfDac = dacx->DAC_VALUE.reg; + } + if (valueOfDac < 512) { /* The user-configured DAC output value need >= 512 */ + return 0.0f; + } + unsigned ret = 0; + unsigned int count = 0; + ADC_Handle adc = {0}; + adc.baseAddress = adcx; + float voltage = 0.0f; + for (unsigned int i = 0; i < 10; ++i) { /* Average of 10 times */ + HAL_ADC_SoftTrigSample(&adc, soc); + BASE_FUNC_DELAY_US(4); /* delay 4 us */ + if (HAL_ADC_CheckSocFinish(&adc, soc) == BASE_STATUS_ERROR) { + continue; + } + count++; + unsigned int tmp = HAL_ADC_GetConvResult(&adc, soc); + ret += tmp; + } + if (count == 0) { + return 0.0f; + } + float ori = (float)ret / (float)count; + /* 256.0, 3.33333 and 4096.0 are used to convert the voltage */ + voltage = 1024.0f / (float)valueOfDac * 3.33333f * ori / 4096.0f; + return voltage; +} + +/** + * @brief set an external reference source to convert the original sampling results of the ADC. + * @param adcx ADC register base address. + * @param soc ID of SOC(start of conversion), managing the specific sample inputs. + * @param vdda Voltage Drain Drain. + * @retval unsigned int, Sampled results after using the reference voltage. + */ +unsigned int HAL_ADC_GetTransResultByVdda(ADC_RegStruct *adcx, ADC_SOCNumber soc, float vdda) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + if (vdda < 2.6f || vdda > 3.63f) { /* 2.6v ~ 3.63v is reasonable value range of VDDA */ + return 0; + } + unsigned int oriAdcResult = DCL_ADC_ReadSOCxResult(adcx, soc); + float tmp = 3.33333f / vdda * (float)oriAdcResult; /* ADC full scale from 3.33333v to VDDA */ + /* If the actual VDDA value is greater than the standard voltage value, the actual result is greater than 0xFFF */ + unsigned int ret = (unsigned int)tmp; + return ret; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/adc/src/adc_ex.c b/vendor/xinlingyu_92_3061M/Project/drivers/adc/src/adc_ex.c new file mode 100644 index 0000000000000000000000000000000000000000..adf8fd5255d56e571abd1fbfef0fcfc15f06095f --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/adc/src/adc_ex.c @@ -0,0 +1,338 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file adc_ex.c + * @author MCU Driver Team + * @brief ADC module driver. + * @details This file provides firmware functions to manage the following extend function. + * + ADC Oversampling Function Configuration and Usage Definition. + * + ADC PPB Function Configuration and Usage Definition. + */ + +/* Includes ------------------------------------------------------------------*/ + +#include "adc_ex.h" + +/** + * @brief Enable SOC for continuous conversion. + * @param adcHandle ADC handle. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_ADC_EnableSocCotinueModeEx(ADC_Handle *adcHandle, ADC_SOCNumber soc) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + DCL_ADC_EnableSOCxContinue(adcHandle->baseAddress, soc); /* Enable continuous conversion */ + return BASE_STATUS_OK; +} + +/** + * @brief Disable SOC for continuous conversion. + * @param adcHandle ADC handle. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_ADC_DisableSocCotinueModeEx(ADC_Handle *adcHandle, ADC_SOCNumber soc) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + DCL_ADC_DisableSOCxContinue(adcHandle->baseAddress, soc); /* Disbale continuous conversion */ + return BASE_STATUS_OK; +} + +/** + * @brief Obtaining ADC Controller Status. + * @param adcHandle ADC handle. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_ADC_GetControllerStatusEx(ADC_Handle *adcHandle) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + unsigned int status = adcHandle->baseAddress->ADC_STATUS.reg; + return (status == 0 ? BASE_STATUS_OK : BASE_STATUS_BUSY); +} + +/** + * @brief Obtaining ADC Controller Status. + * @param adcHandle ADC handle. + * @retval BASE status type. OK, SOC has completed, ERROR, SOC does not complete. + */ +BASE_StatusType HAL_ADC_CheckOversamplingFinishEx(ADC_Handle *adcHandle) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + if (DCL_ADC_GetOversamplingState(adcHandle->baseAddress) == 0) { + return BASE_STATUS_ERROR; /* The SOC does not complete the conversion */ + } + DCL_ADC_ResetOversamplingState(adcHandle->baseAddress); /* Clear flag bit */ + return BASE_STATUS_OK; +} + +/** + * @brief Obtaining ADC Controller Status. + * @param adcHandle ADC handle. + * @retval unsigned int, result of ADC oversampling result. + */ +unsigned int HAL_ADC_GetOversamplingResultEx(ADC_Handle *adcHandle) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + return DCL_ADC_ReadOversamplingResult(adcHandle->baseAddress); +} + +/** + * @brief Configuring ADC Oversampling Parameters. + * @param adcHandle ADC handle. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @param param Configure param of oversampling. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_ADC_ConfigureOversamplingEx(ADC_Handle *adcHandle, ADC_SOCNumber soc, ADC_OversamplingParam *param) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(param != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCOversamplingMultiple(param->multiple), BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCOversamplingRightShift(param->rightShift), BASE_STATUS_ERROR); + unsigned int accuracy = 12 + param->multiple - param->rightShift; /* ADC default sampling precision is 12 bits */ + if (accuracy < 12 || accuracy > 16) { /* oversampling effective accuracy: 12 ~ 16 bits */ + return BASE_STATUS_ERROR; + } + unsigned int value = 1; + value |= ((unsigned int)soc << 4U); /* Shift left 4 bits to configure the soc */ + value |= ((unsigned int)param->multiple << 8U); /* Shift left 8 bits to configure the multiple */ + value |= ((unsigned int)param->rightShift << 12U); /* Shift left 12 bits to configure the rightShift */ + adcHandle->baseAddress->ADC_OVERSAMP.reg = value; + if (param->oversamplingInt == true) { + DCL_ADC_EnableOversamplingInt(adcHandle->baseAddress); + } + return BASE_STATUS_OK; +} + +/** + * @brief Configuring the Working Mode of the ADC Controller. + * @param adcHandle ADC handle. + * @param mode Work mode of ADC. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_ADC_ConfigureWorkModeEx(ADC_Handle *adcHandle, ADC_WorkMode mode) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_PARAM_CHECK_WITH_RET(IsADCWorkMode(mode) == true, BASE_STATUS_ERROR); + adcHandle->baseAddress->ADC_MODE.reg = mode; /* Configuring the Working Mode */ + return BASE_STATUS_OK; +} + +/** + * @brief Enable PPB interrupt. + * @param adcHandle ADC handle. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_ADC_EnablePPBxEventIntEx(ADC_Handle *adcHandle) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + adcHandle->baseAddress->ADC_EVENT_INT_MASK.reg |= 0xFFFF; + return BASE_STATUS_OK; +} + +/** + * @brief Disbale PPB interrupt. + * @param adcHandle ADC handle. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_ADC_DisablePPBxEventIntEx(ADC_Handle *adcHandle) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + unsigned int value = adcHandle->baseAddress->ADC_EVENT_INT_MASK.reg; + value = (value & 0xFFFF0000); /* The lower 16 bits of the PPB event interrupt is disabled. */ + adcHandle->baseAddress->ADC_EVENT_INT_MASK.reg = value; + return BASE_STATUS_OK; +} + +/** + * @brief Event interrupt callback function registration interface. + * @param adcHandle ADC handle. + * @param soc ID of SOC. + * @param ppb Number of PPB. + * @param fun PPB function configuration. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_ADC_ConfigurePPBxEx(ADC_Handle *adcHandle, ADC_SOCNumber soc, ADC_PPBNumber ppb, PPB_Function *fun) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc), BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCPostProcessingBlock(ppb), BASE_STATUS_ERROR); + ADC_ASSERT_PARAM(fun != NULL); + DCL_ADC_SOCxSelectPPBx(adcHandle->baseAddress, ppb, soc); /* Selecting SOC that needs to use the PPB function */ + DCL_ADC_SetPPBxFunction(adcHandle->baseAddress, ppb, fun); /* Configuring the PPB Function */ + return BASE_STATUS_OK; +} + +/** + * @brief Set the upper and down thresholds. + * @param adcHandle ADC handle. + * @param ppb Number of PPB. + * @param up Upper threshold. + * @param dn Down threshold. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_ADC_SetPPBxThresholdEx(ADC_Handle *adcHandle, ADC_PPBNumber ppb, int up, int dn) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_PARAM_CHECK_WITH_RET(IsADCPostProcessingBlock(ppb), BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(-4096 <= up && up <= 4095, BASE_STATUS_ERROR); /* Threshold Range: -4096 ~ 4095 */ + ADC_PARAM_CHECK_WITH_RET(-4096 <= dn && dn <= 4095, BASE_STATUS_ERROR); /* Threshold Range: -4096 ~ 4095 */ + if (up < dn) { + return BASE_STATUS_ERROR; + } + unsigned int upTemp = (0x1FFF & (unsigned int)up); /* The lower 13 bits are valid */ + unsigned int dnTemp = (0x1FFF & (unsigned int)dn); /* The lower 13 bits are valid */ + DCL_ADC_SetPPBxThreshold(adcHandle->baseAddress, ppb, upTemp, dnTemp); + return BASE_STATUS_OK; +} + +/** + * @brief Set the compensation offset. + * @param adcHandle ADC handle. + * @param ppb Number of PPB. + * @param offset Offset compensation value. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_ADC_SetPPBxOffsetEx(ADC_Handle *adcHandle, ADC_PPBNumber ppb, int offset) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_PARAM_CHECK_WITH_RET(IsADCPostProcessingBlock(ppb), BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(-2048 <= offset && offset <= 2047, BASE_STATUS_ERROR); /* Offset Range: -2048 ~ 2047 */ + unsigned int temp = (0xFFF & (unsigned int)offset); /* The lower 12 bits are valid */ + DCL_ADC_SetPPBxOffset(adcHandle->baseAddress, ppb, temp); + return BASE_STATUS_OK; +} + +/** + * @brief Setting the Error reference value. + * @param adcHandle ADC handle. + * @param ppb Number of PPB. + * @param ref Error reference value. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_ADC_SetPPBxErrorRefEx(ADC_Handle *adcHandle, ADC_PPBNumber ppb, unsigned int ref) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_PARAM_CHECK_WITH_RET(IsADCPostProcessingBlock(ppb), BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(ref <= 0xFFF, BASE_STATUS_ERROR); + DCL_ADC_SetPPBxErrorRef(adcHandle->baseAddress, ppb, ref); /* Setting the Error reference value */ + return BASE_STATUS_OK; +} + +/** + * @brief Get the error calculation result. + * @param adcHandle ADC handle. + * @param ppb Number of PPB. + * @retval unsigned int, Error Result. + */ +int HAL_ADC_GetPPBxErrorResultEx(ADC_Handle *adcHandle, ADC_PPBNumber ppb) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_PARAM_CHECK_WITH_RET(IsADCPostProcessingBlock(ppb), BASE_STATUS_ERROR); + unsigned int ret = DCL_ADC_GetPPBxErrorResult(adcHandle->baseAddress, ppb); + if ((ret & 0x1000) == 0x1000) { /* Check whether the value is negative */ + ret |= 0xFFFFE000; + ret = ~(ret - 1); + return (0 - (int)ret); + } + return (int)ret; +} + +/** + * @brief Get the error calculation result. + * @param adcHandle ADC handle. + * @param ppb Number of PPB. + * @retval unsigned int, delay count value. The unit is the system frequency period. + */ +unsigned int HAL_ADC_GetPPBxDelayCntEx(ADC_Handle *adcHandle, ADC_PPBNumber ppb) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_PARAM_CHECK_WITH_RET(IsADCPostProcessingBlock(ppb), BASE_STATUS_ERROR); + return DCL_ADC_GetPPBxDelayCnt(adcHandle->baseAddress, ppb); +} + +/** + * @brief Initialize the ADC for VDDA/3. + * Note: + * (1) Ensure that the ADC clock is turned on and the ADC has been initialized using before use. + * (2) The soc parameter must be set to an SOC that is not occupied in the ADC. + * @param adcx ADC register base address. + * @param soc ID of SOC(start of conversion), managing the specific sample inputs. + * @retval BASE_StatusType. + */ +BASE_StatusType HAL_ADC_InitForVddaEx(ADC_RegStruct *adcx, ADC_SOCNumber soc) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + ADC_Handle adc = {0}; + adc.baseAddress = adcx; + SOC_Param socParam = {0}; + socParam.adcInput = ADC_CH_ADCINA18; /* VDD/3 input */ + socParam.sampleTotalTime = ADC_SOCSAMPLE_500CLK; /* adc sample total time set as 500 cycle */ + socParam.trigSource = ADC_TRIGSOC_SOFT; + socParam.continueMode = BASE_CFG_DISABLE; + socParam.finishMode = ADC_SOCFINISH_NONE; + HAL_ADC_ConfigureSoc(&adc, soc, &socParam); + return BASE_STATUS_OK; +} + +/** + * @brief The VDD/3 is sampled by using the ADC and converted to the VDDA voltage. + * @param adcx ADC register base address. + * @param soc ID of SOC(start of conversion), managing the specific sample inputs. + * @retval float, The reference voltage. + */ +float HAL_ADC_GetVddaEx(ADC_RegStruct *adcx, ADC_SOCNumber soc) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + unsigned ret = 0; + unsigned int count = 0; + ADC_Handle adc = {0}; + adc.baseAddress = adcx; + float voltage = 0.0f; + for (unsigned int i = 0; i < 10; ++i) { /* Average of 10 times */ + HAL_ADC_SoftTrigSample(&adc, soc); + BASE_FUNC_DELAY_US(4); /* 4: wait convert finish, 4us */ + if (HAL_ADC_CheckSocFinish(&adc, soc) == BASE_STATUS_ERROR) { + continue; + } + count++; + unsigned int tmp = HAL_ADC_GetConvResult(&adc, soc); + ret += tmp; + } + if (count == 0) { + return 0.0f; /* convert fail */ + } + float ori = (float)ret / (float)count; + /* 3.0, 3.33333 and 4096.0 are used to convert the voltage, VDD/3 */ + voltage = 3.0 *3.33333f * ori / 4096.0f; + return voltage; +} diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/apt/common/inc/apt.h b/vendor/xinlingyu_92_3061M/Project/drivers/apt/common/inc/apt.h new file mode 100644 index 0000000000000000000000000000000000000000..331709f574796885759d5a269f567b33c4d269fe --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/apt/common/inc/apt.h @@ -0,0 +1,357 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file apt.h + * @author MCU Driver Team + * @brief APT module driver. + * @details This file provides functions declaration of the APT module. + * + APT handle structure definition. + * + Initialization and de-initialization functions. + * + APT Service Functions. + */ + +#ifndef McuMagicTag_APT_H +#define McuMagicTag_APT_H + +#include "apt_ip.h" + +#define EM_OUT_EVT_FILTER_EN 0x0f +#define EM_CMB_MODE_OFFSET 16 +#define EM_CMB_MODE_INTERVAL 4 +#define EM_CMB_SRC_SEL_INTERVAL 4 +#define EM_OR_INTERVAL 16 +#define EM_CMB_EVT_NUM 4 +#define EM_COMBINE_A1_SRC_ENABLE_ALL 0xF +/** + * @defgroup APT APT + * @brief APT module. + * @{ + */ + + +/** + * @defgroup APT_Common APT Common + * @brief APT common external module. + * @{ + */ + +/** + * @defgroup APT_Handle_Definition APT Handle Definition + * @{ + */ + +/* + Basic type AHBL ALBH AHBH ALBL + ___ __ __ ___ __ __ + ChannelA __| |__ |___| __| |__ |___| + __ __ ___ ___ __ __ + ChannelB |___| __| |__ __| |__ |___| +*/ +/** + * @brief Basic PWM waveform type. + * @details waveform type: + * + APT_PWM_BASIC_A_HIGH_B_LOW -- Basic PWM waveform type 1. + * + APT_PWM_BASIC_A_LOW_B_HIGH -- Basic PWM waveform type 2. + * + APT_PWM_BASIC_A_HIGH_B_HIGH -- Basic PWM waveform type 3. + * + APT_PWM_BASIC_A_LOW_B_LOW -- Basic PWM waveform type 4. + */ +typedef enum { + APT_PWM_BASIC_A_HIGH_B_LOW = 0x00000000U, + APT_PWM_BASIC_A_LOW_B_HIGH = 0x00000001U, + APT_PWM_BASIC_A_HIGH_B_HIGH = 0x00000002U, + APT_PWM_BASIC_A_LOW_B_LOW = 0x00000003U, +} APT_PWMBasicType; + +/** + * @brief The actual outputs of PWM channelA and channelB. + * @details Output: + * + APT_PWM_OUT_BASIC_TYPE = 0x00000000U -- PWM channel output the waveform according to basic PWM type. + * + APT_PWM_OUT_ALWAYS_LOW = 0x00000001U -- PWM channel output low level. + * + APT_PWM_OUT_ALWAYS_HIGH = 0x00000002U -- PWM channel output high level. + */ +typedef enum { + APT_PWM_OUT_BASIC_TYPE = 0x00000000U, + APT_PWM_OUT_ALWAYS_LOW = 0x00000001U, + APT_PWM_OUT_ALWAYS_HIGH = 0x00000002U, +} APT_PWMChannelOutType; + +/** + * @brief PWM waveform configuration handle of APT module. + */ +typedef struct { + APT_PWMBasicType basicType; /**< Basic PWM waveform type. */ + APT_PWMChannelOutType chAOutType; /**< Actual output of PWM channelA. */ + APT_PWMChannelOutType chBOutType; /**< Actual output of PWM channelB. */ + APT_CountMode cntMode; /**< Count mode of APT time-base counter. */ + unsigned short dividerFactor; /**< Divider factor. The range is 0~4095. */ + unsigned short timerPeriod; /**< Count period of APT time-base timer. */ + unsigned short divInitVal; /**< Initial value of divider. */ + unsigned short cntInitVal; /**< Initial value of time-base counter */ + unsigned short cntCmpLeftEdge; /**< Count compare point of the left edge of PWM waveform. */ + unsigned short cntCmpRightEdge; /**< Count compare point of the right edge of PWM waveform. */ + APT_BufferLoadMode cntCmpLoadMode; /**< Buffer load mode of PWM waveform count compare value. */ + unsigned int cntCmpLoadEvt; /**< Buffer load event of PWM waveform count compare value. */ + unsigned short deadBandCnt; /**< Count value of dead-band counter. In units of APT clock. */ +} APT_PWMWaveForm; + +/** + * @brief ADC trigger configuration handle of APT module. + */ +typedef struct { + bool trgEnSOCA; /**< Enable of ADC trigger source SOCA. */ + APT_ADCTriggerSource trgSrcSOCA; /**< Source of ADC trigger source SOCA. */ + unsigned short trgScaleSOCA; /**< Scale of ADC trigger source SOCA. */ + unsigned short cntCmpSOCA; /**< Count compare point of ADC trigger source SOCA when using CMPA */ + bool trgEnSOCB; /**< Enable of ADC trigger source SOCB. */ + APT_ADCTriggerSource trgSrcSOCB; /**< Source of ADC trigger source SOCB. */ + unsigned short trgScaleSOCB; /**< Scale of ADC trigger source SOCB. */ + unsigned short cntCmpSOCB; /**< Count compare point of ADC trigger source SOCB when using CMPB */ + APT_BufferLoadMode cntCmpLoadMode; /**< Buffer load mode of ADC trigger count compare value. */ + unsigned int cntCmpLoadEvt; /**< Buffer load event of ADC trigger count compare value. */ +} APT_ADCTrigger; + +/** + * @brief Timer interrupt configuration handle of APT module. + */ +typedef struct { + bool tmrInterruptEn; /**< Enable of APT module timer interrupt. */ + APT_TimerInterruptSrc tmrInterruptSrc; /**< Source of APT module timer interrupt. */ + unsigned short tmrInterruptScale; /**< Scale of APT module timer interrupt. */ +} APT_TimerInterrupt; + +/** + * @brief Output control protection configuration handle of APT module. + */ +typedef struct { + bool ocEventEn; /**< Enable of output control event. */ + APT_OutCtrlEvent ocEvent; /**< Output control event. Limited to IO events or system events. */ + APT_OutCtrlMode ocEventMode; /**< Output control protection mode. */ + APT_CBCClearMode cbcClrMode; /**< Event clear mode when using cycle-by-cycle mode. */ + APT_EMEventPolarity evtPolarity; /**< Event effective polarity. */ + APT_OutCtrlAction ocAction; /**< Output control protection action. */ + APT_EmulationMode emMode; /**< emulation mode */ + bool ocEvtInterruptEn; /**< Enable of output control event interrupt. */ +} APT_OutCtrlProtect; + +/** + * @brief Source event of event magnagement. + */ +typedef enum { + APT_EM_ORIGINAL_SRC_POE0 = 0x00000001U, + APT_EM_ORIGINAL_SRC_POE1 = 0x00000002U, + APT_EM_ORIGINAL_SRC_POE2 = 0x00000004U, + APT_EM_ORIGINAL_SRC_ACMP0 = 0x00000008U, + APT_EM_ORIGINAL_SRC_ACMP1 = 0x00000010U, + APT_EM_ORIGINAL_SRC_ACMP2 = 0x00000020U, + APT_EM_ORIGINAL_SRC_EVTMP4 = 0x00000040U, + APT_EM_ORIGINAL_SRC_EVTMP5 = 0x00000080U, + APT_EM_ORIGINAL_SRC_EVTMP6 = 0x00000100U, +} APT_EMOriginalEvtSrc; + +/** + * @brief Filter mask bit. + */ +typedef enum { + APT_EM_POE0_INVERT_BIT = 0x00000001U, + APT_EM_POE1_INVERT_BIT = 0x00000002U, + APT_EM_POE2_INVERT_BIT = 0x00000004U, + APT_EM_ACMP0_INVERT_BIT = 0x00000008U, + APT_EM_ACMP1_INVERT_BIT = 0x00000010U, + APT_EM_ACMP2_INVERT_BIT = 0x00000020U, + APT_EM_EVTMP4_INVERT_BIT = 0x00000040U, + APT_EM_EVTMP5_INVERT_BIT = 0x00000080U, + APT_EM_EVTMP6_INVERT_BIT = 0x00000100U, +} APT_EMPolarityMskBit; + +/** + * @brief System protect event; + */ +typedef enum { + APT_SYS_EVT_DEBUG = 0x00000010U, + APT_SYS_EVT_CLK = 0x00000020U, + APT_SYS_EVT_MEM = 0x00000040U, +} APT_SysOcEvent; + +/** + * @brief Output control protection configuration handle of APT module. + */ +typedef struct { + bool ocEventEnEx; /**< oc event enable */ + APT_OutCtrlMode ocEventModeEx; /**< Output control protection mode. */ + APT_CBCClearMode cbcClrModeEx; /**< Event clear mode when using cycle-by-cycle mode. */ + APT_OutCtrlAction ocActionEx; /**< Output control protection channel A action. */ + APT_OutCtrlAction ocActionBEx; /**< Output control protection channel B action. */ + bool ocEvtInterruptEnEx; /**< Enable of output control event interrupt. */ + APT_SysOcEvent ocSysEvent; /**< System protect event */ + APT_EMOriginalEvtSrc originalEvtEx; /**< Event management's event source */ + APT_EMPolarityMskBit evtPolarityMaskEx; /**< Event effective polarity. */ + unsigned char filterCycleNumEx; /**< input source event filter */ +} APT_OutCtrlProtectEx; + +/** + * @brief struct of EM conbine event + */ +typedef struct { + APT_EMCombineEvtSrc emEvtSrc; /**< combine event selection */ + APT_EMCombineEvtMode emEvtCombineMode; /**< event combine mode */ + APT_EMEventPolarity emEvtPolar; /**< event source polarity */ + unsigned int emEvtOrEnBits; /**< event logic or enable bits */ +} APT_CombineEvt; + +/** + * @brief Shield window and capture configurations + */ +typedef struct { + bool wdEnable; /**< Shield windows enable bit */ + bool emCapEnable; /**< Enable EM captrue functions */ + APT_EMCombineEvent eventSel; /**< Window source event selection */ + APT_MaskWinResetMode wdStartAndCapClr; /**< Window's offset start count and EM capture clear condition */ + unsigned short wdOffset; /**< Window's offset value */ + unsigned short wdWidth; /**< Window's width value */ + APT_MaskWinPolarity wdPolar; /**< Window's polarity */ +} APT_WdAndCap; + + +/** + * @brief Valley switch configurations + */ +typedef struct { + bool vsEnable; /**< Valley switch enable */ + APT_EMEdgeFilterMode vsFilerEdgeSel; /**< Filter edge selection */ + unsigned char vsFilterCnt; /**< Filter edge count */ + APT_ValleyCapRstType vsClrType; /**< Clear type */ + APT_ValleyCountEdge vsCapEdgeSel; /**< Capture edge selection */ + unsigned char vsCapStartEdge; /**< Capture start edge */ + unsigned char vsCapEndEdge; /**< Capture end edge */ + APT_ValleyDelayMode vsCapDelayMode; /**< Capture delay mode */ + unsigned short vsCapSoftDelay; /**< Capture software calibrate value */ +} APT_ValleySw; + +/** + * @brief Event management handle of APT module + */ +typedef struct { + bool emEnable; /**< Enable bit of event management */ + APT_CombineEvt emEvt[EM_CMB_EVT_NUM]; /**< Combine events configuration */ + APT_WdAndCap emWdAndCap; /**< Shield windows and capture configuration */ + APT_ValleySw emValleySw; /**< Valley switch configuration */ +} APT_EventManage; + +/** + * @brief Synchronization handle of slave APT module. + */ +typedef struct { + unsigned short divPhase; /**< Divider phase when receiving APT synchronization pulse. */ + unsigned short cntPhase; /**< Counter phase when receiving APT synchronization pulse. */ + APT_SyncCountMode syncCntMode; /**< Count mode when receiving APT synchronization pulse. */ + APT_SyncInSrc syncInSrc; /**< Sync-in source of APT module */ + unsigned short cntrSyncSrc; + /**< Sync-in source of time-base counter synchronization + A logical OR of valid values can be passed as the cntrSyncSrc parameter. + Valid values for cntrSyncSrc are: + APT_CNTR_SYNC_SRC_COMBINE_EVENT_A1 - Enable combine event A1 as the counter synchronization source. + APT_CNTR_SYNC_SRC_COMBINE_EVENT_B1 - Enable combine event B1 as the counter synchronization source. + APT_CNTR_SYNC_SRC_SYNCIN - Enable Sync-In source as the counter synchronization source. */ +} APT_SlaveSyncIn; + +/** + * @brief Definition of callback function type. + */ +typedef void (* APT_CallbackType)(void *aptHandle); + +/** + * @brief Definition of callback function type. + */ +typedef struct { + void (* EvtInterruptCallBack)(void *handle); + void (* TmrInterruptCallBack)(void *handle); +} APT_UserCallBack; + +/** + * @brief The definition of the APT handle structure. + */ +typedef struct _APT_Handle { + APT_RegStruct *baseAddress; /**< Register base address. */ + APT_PWMWaveForm waveform; /**< PWM waveform configuration handle. */ + APT_ADCTrigger adcTrg; /**< ADC trigger configuration handle. */ + APT_TimerInterrupt tmrInterrupt; /**< Timer interrupt configuration handle. */ + APT_UserCallBack userCallBack; /**< Interrupt callback function when APT event happens. */ + APT_ExtendHandle handleEx; /**< extra handle */ +} APT_Handle; +/** + * @} + */ + +/** + * @defgroup APT_API_Declaration APT HAL API + * @{ + */ + +/** + * @brief Definition of callback function ID. + */ +typedef enum { + APT_TIMER_INTERRUPT = 0x00000000U, + APT_EVENT_INTERRUPT = 0x00000001U, +} APT_InterruputType; + +BASE_StatusType HAL_APT_PWMInit(APT_Handle *aptHandle); +BASE_StatusType HAL_APT_PWMDeInit(APT_Handle *aptHandle); +BASE_StatusType HAL_APT_ProtectInit(APT_Handle *aptHandle, APT_OutCtrlProtect *protect); +BASE_StatusType HAL_APT_ProtectDeInit(APT_Handle *aptHandle, APT_OutCtrlProtect *protect); +BASE_StatusType HAL_APT_ProtectInitEx(APT_Handle *aptHandle, APT_OutCtrlProtectEx *protect); +BASE_StatusType HAL_APT_ProtectDeInitEx(APT_Handle *aptHandle, APT_OutCtrlProtectEx *protect); +void HAL_APT_ForcePWMOutputLow(APT_Handle *aptHandle); +BASE_StatusType HAL_APT_MasterSyncInit(APT_Handle *aptHandle, unsigned short syncOutSrc); +BASE_StatusType HAL_APT_SlaveSyncInit(APT_Handle *aptHandle, APT_SlaveSyncIn *slaveSyncIn); +void HAL_APT_StartModule(unsigned int aptRunMask); +void HAL_APT_StopModule(unsigned int aptRunMask); +BASE_StatusType HAL_APT_SetPWMDuty(APT_Handle *aptHandle, unsigned short cntCmpLeftEdge, \ + unsigned short cntCmpRightEdge); +BASE_StatusType HAL_APT_SetPWMDutyByNumber(APT_Handle *aptHandle, unsigned int duty); +BASE_StatusType HAL_APT_SetADCTriggerTime(APT_Handle *aptHandle, unsigned short cntCmpSOCA, unsigned short cntCmpSOCB); +void HAL_APT_EventIrqHandler(void *handle); +void HAL_APT_TimerIrqHandler(void *handle); +void HAL_APT_RegisterCallBack(APT_Handle *aptHandle, APT_InterruputType typeID, APT_CallbackType pCallback); +BASE_StatusType HAL_APT_EMInit(APT_Handle *aptHandle, APT_EventManage *eventManage); +unsigned short HAL_APT_EMGetCapValue(APT_Handle *aptHandle); +void HAL_APT_EMSetWdOffsetAndWidth(APT_Handle *aptHandle, unsigned short offset, unsigned short width); +void HAL_APT_EMSetValleySwithSoftDelay(APT_Handle *aptHandle, unsigned short calibrate); +BASE_StatusType HAL_APT_ChangeOutputType(APT_Handle *aptHandle, + APT_PWMChannel channel, + APT_PWMChannelOutType aptAction); + +/* Attribute configuration of each reference point. */ +BASE_StatusType APT_ConfigRefA(APT_Handle *aptHandle, APT_RefDotParameters *refDotParameters); +BASE_StatusType APT_ConfigRefB(APT_Handle *aptHandle, APT_RefDotParameters *refDotParameters); +BASE_StatusType APT_ConfigRefC(APT_Handle *aptHandle, APT_RefDotParameters *refDotParameters); +BASE_StatusType APT_ConfigRefD(APT_Handle *aptHandle, APT_RefDotParameters *refDotParameters); +/* Combination configuration of reference point attributes. */ +BASE_StatusType HAL_APT_ConfigRefDot(APT_Handle *aptHandle, APT_RefDotSelect refDotSelect, + APT_RefDotParameters *refDotParameters); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_APT_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/apt/inc/apt_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/apt/inc/apt_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..dfba827111c152557eaa037dbe132302670b9b0c --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/apt/inc/apt_ip.h @@ -0,0 +1,3470 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file apt_ip.h + * @author MCU Driver Team + * @brief Header file containing APT module DCL driver functions. + * This file provides functions to manage the following functionalities of APT module. + * + Definition of APT configuration parameters. + * + APT registers mapping structure. + * + Direct Configuration Layer driver functions. + */ + +#ifndef McuMagicTag_APT_IP_H +#define McuMagicTag_APT_IP_H + +#include "baseinc.h" + +#ifdef APT_PARAM_CHECK + #define APT_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM + #define APT_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET + #define APT_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else + #define APT_ASSERT_PARAM(para) ((void)0U) + #define APT_PARAM_CHECK_NO_RET(para) ((void)0U) + #define APT_PARAM_CHECK_WITH_RET(param, ret) ((void)0U) +#endif + +/** + * @addtogroup APT + * @{ + */ + +/** + * @defgroup APT_IP APT_IP + * @brief APT_IP: apt_v1. + * @{ + */ + +/** + * @defgroup APT_Param_Def APT Parameters Definition + * @brief Definition of APT configuration parameters + * @{ + */ + +/* Bitmask of the aptx_run bits in SYSCTRL1 register. */ +#define RUN_APT0 0x00000001U +#define RUN_APT1 0x00000002U +#define RUN_APT2 0x00000004U +#define RUN_APT3 0x00000008U + +/* Limited values for some configuration items of APT module. */ +#define DIVIDER_FACTOR_MAX 0x00000FFFU +#define TIMEBASE_COUNTER_MAX 0x0000FFFFU +#define TIMER_INTERRUPT_CNT_MAX 0x0000000FU +#define ADC_CONVERSION_START_CNT_MAX 0x0000000FU +#define VCAP_STARY_STOP_EDGE_CNT_MAX 0x0000000FU +#define EDGE_FILTER_EDGE_CNT_MAX 0x0000000FU +#define CNTR_SYNC_SOURCE_MAX 0x00000007U +#define SYNC_OUT_SOURCE_MAX 0x000000FFU +#define GLOBAL_LOAD_CNT_MAX 0x0000000FU + +/* Values that can be passed to DCL_APT_SetPeriodLoadEvent() as the loadEvent parameter. */ +#define APT_PERIOD_LOAD_EVENT_ZERO 0x00000001U +#define APT_PERIOD_LOAD_EVENT_A1 0x00000004U +#define APT_PERIOD_LOAD_EVENT_B1 0x00000008U +#define APT_PERIOD_LOAD_EVENT_SYNC 0x00000010U + +/* Values that can be passed to DCL_APT_SetCompareLoadEvent() as the loadEvent parameter. */ +#define APT_COMPARE_LOAD_EVENT_ZERO 0x00000001U +#define APT_COMPARE_LOAD_EVENT_PERIOD 0x00000002U +#define APT_COMPARE_LOAD_EVENT_A1 0x00000004U +#define APT_COMPARE_LOAD_EVENT_B1 0x00000008U +#define APT_COMPARE_LOAD_EVENT_SYNC 0x00000010U + +/* Values that can be returned by DCL_APT_GetCounterDirection(). */ +#define APT_COUNTER_STATUS_COUNT_DOWN 0x00000000U +#define APT_COUNTER_STATUS_COUNT_UP 0x00000001U + +/* Values that can be passed to DCL_APT_SetPWMActionLoadEvent() and + * DCL_APT_SetSwContActionLoadEvent() as the loadEvent parameter. */ +#define APT_ACTION_LOAD_EVENT_ZERO 0x00000001U +#define APT_ACTION_LOAD_EVENT_PERIOD 0x00000002U +#define APT_ACTION_LOAD_EVENT_A1 0x00000004U +#define APT_ACTION_LOAD_EVENT_B1 0x00000008U +#define APT_ACTION_LOAD_EVENT_SYNC 0x00000010U + + +/* Values that can be passed to DCL_APT_SetDGConfigLoadEvent(), DCL_APT_SetREDCounterLoadEvent() and + * DCL_APT_SetFEDCounterLoadEvent() as the loadEvent parameter. */ + +#define APT_DEAD_BAND_LOAD_EVENT_ZERO 0x00000001U +#define APT_DEAD_BAND_LOAD_EVENT_PERIOD 0x00000002U + +/* Values that can be passed to DCL_APT_SetEMEventOR() as the event1OREn and event1OREn parameter. */ +#define APT_EM_OR_EN_GPIO_EVENT_1 0x00000001U +#define APT_EM_OR_EN_GPIO_EVENT_2 0x00000002U +#define APT_EM_OR_EN_GPIO_EVENT_3 0x00000004U +#define APT_EM_OR_EN_MXU_EVENT_1 0x00000008U +#define APT_EM_OR_EN_MXU_EVENT_2 0x00000010U +#define APT_EM_OR_EN_MXU_EVENT_3 0x00000020U +#define APT_EM_OR_EN_MXU_EVENT_4 0x00000040U +#define APT_EM_OR_EN_MXU_EVENT_5 0x00000080U +#define APT_EM_OR_EN_MXU_EVENT_6 0x00000100U +#define APT_EM_OR_EN_MXU_EVENT_7 0x00000200U +#define APT_EM_OR_EN_MXU_EVENT_8 0x00000400U +#define APT_EM_OR_EN_MXU_EVENT_9 0x00000800U +#define APT_EM_OR_EN_MXU_EVENT_10 0x00001000U +#define APT_EM_OR_EN_MXU_EVENT_11 0x00002000U +#define APT_EM_OR_EN_MXU_EVENT_12 0x00004000U + +/* Values that can be passed to DCL_APT_SetTimeBaseCounterSyncSrc() as the cntrSyncSrc parameter. */ +#define APT_CNTR_SYNC_SRC_COMBINE_EVENT_A1 0x00000001U +#define APT_CNTR_SYNC_SRC_COMBINE_EVENT_B1 0x00000002U +#define APT_CNTR_SYNC_SRC_SYNCIN 0x00000004U + +/* Values that can be passed to DCL_APT_SetSyncOutPulseSrc() as the syncOutSrc parameter. */ +#define APT_SYNC_OUT_ON_CNTR_ZERO 0x00000001U +#define APT_SYNC_OUT_ON_CNTR_PERIOD 0x00000002U +#define APT_SYNC_OUT_ON_COMBINE_EVENT_A1 0x00000004U +#define APT_SYNC_OUT_ON_COMBINE_EVENT_B1 0x00000008U +#define APT_SYNC_OUT_ON_CNTR_CMPB 0x00000020U +#define APT_SYNC_OUT_ON_CNTR_CMPC 0x00000040U +#define APT_SYNC_OUT_ON_CNTR_CMPD 0x00000080U + +/* Values that can be passed to DCL_APT_SetGlobalLoadPrescale() as the glbLoadEvt parameter. */ +#define APT_GLB_LOAD_ON_CNTR_ZERO 0x00000001U +#define APT_GLB_LOAD_ON_CNTR_PERIOD 0x00000002U +#define APT_GLB_LOAD_ON_CNTR_SYNC 0x00000004U + +/** + * @brief APT Extra Handle. + */ +typedef struct { + ; +} APT_ExtendHandle; + +/** + * @brief Emulation stop mode of APT module. + */ +typedef enum { + APT_EMULATION_NO_STOP = 0x00000001U, + APT_EMULATION_STOP_COUNTER = 0x00000002U, + APT_EMULATION_STOP_APT = 0x00000003U, +} APT_EmulationMode; + +/** + * @brief Count mode of time-base counter. + */ +typedef enum { + APT_COUNT_MODE_UP = 0x00000000U, + APT_COUNT_MODE_DOWN = 0x00000001U, + APT_COUNT_MODE_UP_DOWN = 0x00000002U, + APT_COUNT_MODE_FREEZE = 0x00000003U, +} APT_CountMode; + +/** + * @brief Count mode after synchronization for slave APT module. + */ +typedef enum { + APT_COUNT_MODE_AFTER_SYNC_DOWN = 0x00000000U, + APT_COUNT_MODE_AFTER_SYNC_UP = 0x00000001U, +} APT_SyncCountMode; + +/** + * @brief Count compare reference of time-base counter. + */ +typedef enum { + APT_COMPARE_REFERENCE_A = 0x00000000U, + APT_COMPARE_REFERENCE_B = 0x00000001U, + APT_COMPARE_REFERENCE_C = 0x00000002U, + APT_COMPARE_REFERENCE_D = 0x00000003U, +} APT_CompareRef; + +/** + * @brief Buffer load mode of the registers that support buffer register. + * @details Load mode: + * + APT_BUFFER_DISABLE -- Disable register buffer + * + APT_BUFFER_INDEPENDENT_LOAD -- Enable register buffer and load independently + * + APT_BUFFER_GLOBAL_LOAD -- enable register buffer and load globally + */ +typedef enum { + APT_BUFFER_DISABLE = 0x00000000U, + APT_BUFFER_INDEPENDENT_LOAD = 0x00000001U, + APT_BUFFER_GLOBAL_LOAD = 0x00000003U, +} APT_BufferLoadMode; + +/** + * @brief PWM waveform output channel. + */ +typedef enum { + APT_PWM_CHANNEL_A = 0x00000000U, + APT_PWM_CHANNEL_B = 0x00000001U, +} APT_PWMChannel; + +/** + * @brief PWM waveform action on PWM action events. + */ +typedef enum { + APT_PWM_ACTION_HOLD = 0x00000000U, + APT_PWM_ACTION_LOW = 0x00000001U, + APT_PWM_ACTION_HIGH = 0x00000002U, + APT_PWM_ACTION_TOGGLE = 0x00000003U, +} APT_PWMAction; + +/** + * @brief Count compare event for generating PWM waveform actions. + * The enumeration values are the register bit field offset of the corresponding action events. + */ +typedef enum { + APT_PWM_ACTION_ON_TIMEBASE_ZERO = 0U, + APT_PWM_ACTION_ON_TIMEBASE_PERIOD = 2U, + APT_PWM_ACTION_ON_CMPA_COUNT_UP = 4U, + APT_PWM_ACTION_ON_CMPA_COUNT_DOWN = 6U, + APT_PWM_ACTION_ON_CMPB_COUNT_UP = 8U, + APT_PWM_ACTION_ON_CMPB_COUNT_DOWN = 10U, + APT_PWM_ACTION_ON_CMPC_COUNT_UP = 12U, + APT_PWM_ACTION_ON_CMPC_COUNT_DOWN = 14U, + APT_PWM_ACTION_ON_CMPD_COUNT_UP = 16U, + APT_PWM_ACTION_ON_CMPD_COUNT_DOWN = 18U, + APT_PWM_ACTION_ON_C1_COUNT_UP = 20U, + APT_PWM_ACTION_ON_C1_COUNT_DOWN = 22U, + APT_PWM_ACTION_ON_C2_COUNT_UP = 24U, + APT_PWM_ACTION_ON_C2_COUNT_DOWN = 26U, +} APT_PWMActionEvent; + +/** + * @brief PWM action when using software continuous action. + */ +typedef enum { + APT_PWM_CONTINUOUS_ACTION_HOLD = 0x00000000U, + APT_PWM_CONTINUOUS_ACTION_LOW = 0x00000001U, + APT_PWM_CONTINUOUS_ACTION_HIGH = 0x00000002U, +} APT_PWMContAction; + +/** + * @brief PWM Generation event C1 and C2. + */ +typedef enum { + APT_PWM_GENERATION_EVENT_C1 = 0x00000000U, + APT_PWM_GENERATION_EVENT_C2 = 0x00000001U, +} APT_PGEventCx; + +/** + * @brief Source of PWM Generation event C1 and C2. + */ +typedef enum { + APT_PG_EVT_C_FORBIDDEN = 0x00000000U, + APT_PG_EVT_C_COMBINE_EVENT_A1 = 0x00000001U, + APT_PG_EVT_C_COMBINE_EVENT_A2 = 0x00000002U, + APT_PG_EVT_C_COMBINE_EVENT_B1 = 0x00000003U, + APT_PG_EVT_C_COMBINE_EVENT_B2 = 0x00000004U, + APT_PG_EVT_C_COMBINE_EVENT_FILT = 0x00000005U, + APT_PG_EVT_C_IO_EVENT1 = 0x00000006U, + APT_PG_EVT_C_IO_EVENT2 = 0x00000007U, + APT_PG_EVT_C_IO_EVENT3 = 0x00000008U, + APT_PG_EVT_C_SYNC_IN = 0x00000009U, +} APT_PGEventCxSrc; + +/** + * @brief Input source of Dead-Band rising edge delay counter. + * @details Input source: + * + APT_DB_RED_INPUT_PWM_A -- Dead-Band rising edge delay input is PWM channel A + * + APT_DB_RED_INPUT_PWM_B -- Dead-Band rising edge delay input is PWM channel B + */ +typedef enum { + APT_DB_RED_INPUT_PWM_A = 0x00000000U, + APT_DB_RED_INPUT_PWM_B = 0x00000001U, +} APT_REDInput; + +/** + * @brief Output mode of Dead-Band rising edge delay counter. + * @details Output mode: + * + APT_DB_RED_OUTPUT_NOT_INVERT -- Dead-Band rising edge delay output is not inverted + * + APT_DB_RED_OUTPUT_INVERT -- Dead-Band rising edge delay output is inverted + * + APT_DB_RED_OUTPUT_PWM_A -- Dead-Band rising edge delay is bypassed + */ +typedef enum { + APT_DB_RED_OUTPUT_NOT_INVERT = 0x00000000U, + APT_DB_RED_OUTPUT_INVERT = 0x00000002U, + APT_DB_RED_OUTPUT_PWM_A = 0x00000003U, +} APT_REDOutMode; + +/** + * @brief Input source of Dead-Band falling edge delay counter. + * @details Input source: + * + APT_DB_FED_INPUT_PWM_B -- Dead-Band falling edge delay input is PWM channel B + * + APT_DB_FED_INPUT_PWM_A -- Dead-Band falling edge delay input is PWM channel A + * + APT_DB_FED_INPUT_RED_OUT -- Falling edge delay input is rising edge delay output + * + APT_DB_FED_INPUT_ZERO -- Dead-Band falling edge delay input is 0 + */ +typedef enum { + APT_DB_FED_INPUT_PWM_B = 0x00000000U, + APT_DB_FED_INPUT_PWM_A = 0x00000001U, + APT_DB_FED_INPUT_RED_OUT = 0x00000002U, + APT_DB_FED_INPUT_ZERO = 0x00000003U, +} APT_FEDInput; + +/** + * @brief Output mode of Dead-Band falling edge delay counter. + * @details Output mode: + * + APT_DB_FED_OUTPUT_NOT_INVERT -- Dead-Band falling edge delay output is not inverted + * + APT_DB_FED_OUTPUT_INVERT -- Dead-Band falling edge delay output is inverted + * + APT_DB_FED_OUTPUT_PWM_B -- Dead-Band falling edge delay is bypassed + */ +typedef enum { + APT_DB_FED_OUTPUT_NOT_INVERT = 0x00000000U, /**< Dead-Band falling edge delay output is not inverted */ + APT_DB_FED_OUTPUT_INVERT = 0x00000002U, /**< Dead-Band falling edge delay output is inverted */ + APT_DB_FED_OUTPUT_PWM_B = 0x00000003U, /**< Dead-Band falling edge delay is bypassed */ +} APT_FEDOutMode; + +/** + * @brief Output control events. + */ +typedef enum { + APT_OC_NO_EVENT = 0x00000000U, + APT_OC_GPIO_EVENT_1 = 0x00000001U, + APT_OC_GPIO_EVENT_2 = 0x00000002U, + APT_OC_GPIO_EVENT_3 = 0x00000004U, + APT_OC_SYSTEM_EVENT_1 = 0x00000010U, + APT_OC_SYSTEM_EVENT_2 = 0x00000020U, + APT_OC_SYSTEM_EVENT_3 = 0x00000040U, + APT_OC_COMBINE_EVENT_A1 = 0x00000100U, + APT_OC_COMBINE_EVENT_A2 = 0x00000200U, + APT_OC_COMBINE_EVENT_B1 = 0x00000400U, + APT_OC_COMBINE_EVENT_B2 = 0x00000800U, +} APT_OutCtrlEvent; + +/** + * @brief Output control event mode. + */ +typedef enum { + APT_OUT_CTRL_ONE_SHOT = 0x00000000U, + APT_OUT_CTRL_CYCLE_BY_CYBLE = 0x00000001U, +} APT_OutCtrlMode; + +/** + * @brief Advanced output control events take into consideration of the direction of time-base counter. + * The enumeration values are the register bit field offset of the corresponding output control events. + */ +typedef enum { + APT_OC_EVT_GPIO_OR_SYSTEM_UP = 0U, + APT_OC_EVT_COMBINE_EVENT_A1_UP = 3U, + APT_OC_EVT_COMBINE_EVENT_A2_UP = 6U, + APT_OC_EVT_COMBINE_EVENT_B1_UP = 9U, + APT_OC_EVT_COMBINE_EVENT_B2_UP = 12U, + APT_OC_EVT_GPIO_OR_SYSTEM_DOWN = 16U, + APT_OC_EVT_COMBINE_EVENT_A1_DOWN = 19U, + APT_OC_EVT_COMBINE_EVENT_A2_DOWN = 22U, + APT_OC_EVT_COMBINE_EVENT_B1_DOWN = 25U, + APT_OC_EVT_COMBINE_EVENT_B2_DOWN = 28U, +} APT_OutCtrlEventDir; + +/** + * @brief Output control action. + * @details Control action: + * + APT_OUT_CTRL_ACTION_DISABLE -- Disable output protect control. Output PWM directly + * + APT_OUT_CTRL_ACTION_LOW -- Output low level + * + APT_OUT_CTRL_ACTION_HIGH -- Output high level + * + APT_OUT_CTRL_ACTION_HOLD -- Hold the current output state + * + APT_OUT_CTRL_ACTION_TOGGLE -- Toggle the current output state + * + APT_OUT_CTRL_ACTION_HIGH_Z -- High-impedance output + */ +typedef enum { + APT_OUT_CTRL_ACTION_DISABLE = 0x00000000U, + APT_OUT_CTRL_ACTION_LOW = 0x00000001U, + APT_OUT_CTRL_ACTION_HIGH = 0x00000002U, + APT_OUT_CTRL_ACTION_HOLD = 0x00000003U, + APT_OUT_CTRL_ACTION_TOGGLE = 0x00000004U, + APT_OUT_CTRL_ACTION_HIGH_Z = 0x00000005U, +} APT_OutCtrlAction; + +/** + * @brief Event latch clear mode of cycle-by-cycle output control mode. + */ +typedef enum { + APT_CLEAR_CBC_ON_CNTR_ZERO = 0x00000001U, + APT_CLEAR_CBC_ON_CNTR_PERIOD = 0x00000002U, + APT_CLEAR_CBC_ON_CNTR_ZERO_PERIOD = 0x00000003U, +} APT_CBCClearMode; + +/** + * @brief Source of timer interrupt. + */ +typedef enum { + APT_INT_SRC_CNTR_DISABLE = 0x00000000U, + APT_INT_SRC_CNTR_ZERO = 0x00000001U, + APT_INT_SRC_CNTR_PERIOD = 0x00000002U, + APT_INT_SRC_CNTR_ZERO_PERIOD = 0x00000003U, + APT_INT_SRC_CNTR_CMPA_UP = 0x00000004U, + APT_INT_SRC_CNTR_CMPA_DOWN = 0x00000005U, + APT_INT_SRC_CNTR_CMPB_UP = 0x00000006U, + APT_INT_SRC_CNTR_CMPB_DOWN = 0x00000007U, + APT_INT_SRC_CNTR_CMPC_UP = 0x00000008U, + APT_INT_SRC_CNTR_CMPC_DOWN = 0x00000009U, + APT_INT_SRC_CNTR_CMPD_UP = 0x0000000AU, + APT_INT_SRC_CNTR_CMPD_DOWN = 0x0000000BU, +} APT_TimerInterruptSrc; + +/** + * @brief ADC trigger channels. + */ +typedef enum { + APT_ADC_CONVERSION_START_A = 0x00000001U, + APT_ADC_CONVERSION_START_B = 0x00000002U, +} APT_ADCTriggerChannel; + +/** + * @brief Source of ADC trigger channels. + */ +typedef enum { + APT_CS_SRC_COMBINE_EVENT_A1 = 0x00000000U, + APT_CS_SRC_CNTR_ZERO = 0x00000001U, + APT_CS_SRC_CNTR_PERIOD = 0x00000002U, + APT_CS_SRC_CNTR_ZERO_PERIOD = 0x00000003U, + APT_CS_SRC_CNTR_CMPA_UP = 0x00000004U, + APT_CS_SRC_CNTR_CMPA_DOWN = 0x00000005U, + APT_CS_SRC_CNTR_CMPB_UP = 0x00000006U, + APT_CS_SRC_CNTR_CMPB_DOWN = 0x00000007U, + APT_CS_SRC_CNTR_CMPC_UP = 0x00000008U, + APT_CS_SRC_CNTR_CMPC_DOWN = 0x00000009U, + APT_CS_SRC_CNTR_CMPD_UP = 0x0000000AU, + APT_CS_SRC_CNTR_CMPD_DOWN = 0x0000000BU, +} APT_ADCTriggerSource; + +/** + * @brief DMA request source of ADC Converter Start submodule. + */ +typedef enum { + APT_CS_DMA_REQ_SRC_DISABLE = 0x00000000U, + APT_CS_DMA_REQ_SRC_CHANNEL_A = 0x00000001U, + APT_CS_DMA_REQ_SRC_CHANNEL_B = 0x00000002U, +} APT_ADCTrgDMAReqSrc; + +/** + * @brief DMA request type of ADC Converter Start submodule. + */ +typedef enum { + APT_CS_DMA_SINGLE_REQUEST = 0x00000000U, + APT_CS_DMA_BURST_REQUEST = 0x00000002U, +} APT_ADCTrgDMAReqType; + +/** + * @brief Polarity of the events of Event Management submodule. + * @details Polarity: + * + APT_EM_EVENT_POLARITY_NOT_INVERT -- High active. + * + APT_EM_EVENT_POLARITY_INVERT -- Low active. + * + APT_EM_EVENT_POLARITY_FORCE_LOW -- Force event to low level. + * + APT_EM_EVENT_POLARITY_FORCE_HIGH -- Force event to high level. + */ +typedef enum { + APT_EM_EVENT_POLARITY_NOT_INVERT = 0x00000000U, + APT_EM_EVENT_POLARITY_INVERT = 0x00000001U, + APT_EM_EVENT_POLARITY_FORCE_LOW = 0x00000002U, + APT_EM_EVENT_POLARITY_FORCE_HIGH = 0x00000003U, +} APT_EMEventPolarity; + +/** + * @brief GPIO events and system events of Event Management submodule. + * The enumeration values are the register bit field offset of the corresponding GPIO/system events. + */ +typedef enum { + APT_EM_GPIO_EVENT_1 = 0U, + APT_EM_GPIO_EVENT_2 = 2U, + APT_EM_GPIO_EVENT_3 = 4U, + APT_EM_GPIO_EVENT_4 = 6U, + APT_EM_GPIO_EVENT_5 = 8U, + APT_EM_SYSTEM_EVENT_1 = 16U, + APT_EM_SYSTEM_EVENT_2 = 18U, + APT_EM_SYSTEM_EVENT_3 = 20U, +} APT_EMIOSysEvent; + +/** + * @brief Multiplexing events of Event Management submodule. + * The enumeration values are the register bit field offset of the corresponding multiplexing events. + */ +typedef enum { + APT_EM_MP_EVENT_1 = 0U, + APT_EM_MP_EVENT_2 = 2U, + APT_EM_MP_EVENT_3 = 4U, + APT_EM_MP_EVENT_4 = 6U, + APT_EM_MP_EVENT_5 = 8U, + APT_EM_MP_EVENT_6 = 10U, +} APT_EMMuxEvent; + +/** + * @brief Event Module of Event Management submodule. + */ +typedef enum { + APT_EM_MODULE_A = 0x00000000U, + APT_EM_MODULE_B = 0x00000001U, +} APT_EMGroup; + +/** + * @brief Group of combine event source input. + */ +typedef enum { + APT_EM_COMBINE_SRC_GRP_A1 = 0x00000000U, + APT_EM_COMBINE_SRC_GRP_A2 = 0x00000001U, + APT_EM_COMBINE_SRC_GRP_B1 = 0x00000002U, + APT_EM_COMBINE_SRC_GRP_B2 = 0x00000003U, +} APT_EMCombineEvtSrcGrp; + +/** + * @brief Source of combine events A1, A2, B1, B2. + */ +typedef enum { + APT_EM_COMBINE_SRC_EVT_1 = 0x00000000U, + APT_EM_COMBINE_SRC_EVT_2 = 0x00000001U, + APT_EM_COMBINE_SRC_EVT_3 = 0x00000002U, + APT_EM_COMBINE_SRC_EVT_MP_1 = 0x00000003U, + APT_EM_COMBINE_SRC_EVT_MP_2 = 0x00000004U, + APT_EM_COMBINE_SRC_EVT_MP_3 = 0x00000005U, + APT_EM_COMBINE_SRC_EVT_MP_4 = 0x00000006U, + APT_EM_COMBINE_SRC_EVT_MP_5 = 0x00000007U, + APT_EM_COMBINE_SRC_EVT_MP_6 = 0x00000008U, + APT_EM_COMBINE_SRC_ALL_EVENT_OR = 0x0000000FU, /* based on EM_AOR_EN/EM_BOR_EN */ +} APT_EMCombineEvtSrc; + +/** + * @brief Combine events of Event Management submodule. + */ +typedef enum { + APT_EM_COMBINE_EVENT_A1 = 0x00000000U, + APT_EM_COMBINE_EVENT_A2 = 0x00000001U, + APT_EM_COMBINE_EVENT_B1 = 0x00000002U, + APT_EM_COMBINE_EVENT_B2 = 0x00000003U, +} APT_EMCombineEvent; + +/** + * @brief Combine Mode of combine events A1, A2, B1, B2. + * @details combine mode: + * + The combine result is set output to low level + * + The combine result is qual to event 1 + * + The combine result is the logical AND of group event 1 high level and group event 2 low level + * + The combine result is the logical AND of group event 1 high level and group event 2 low level + * + The combine result is the logical AND of group event 1 high level and group event 2 high level + * + The combine result is the logical AND of group event 1 low level and group event 2 low level + */ +typedef enum { + APT_EM_COMBINE_LOW_LEVEL = 0x00000000U, + APT_EM_COMBINE_EVT1 = 0x00000001U, + APT_EM_COMBINE_EVT1_H_AND_EVT2_L = 0x00000002U, + APT_EM_COMBINE_EVT1_H_AND_EVT2_H = 0x00000003U, + APT_EM_COMBINE_EVT1_L_AND_EVT2_H = 0x00000004U, + APT_EM_COMBINE_EVT2 = 0x00000005U, +} APT_EMCombineEvtMode; + +/** + * @brief Output type of combine events. + * @details Output type: + * +APT_EM_COMBINE_EVENT_OUT_ORIG_SIGNAL -- The source of combine event is unfiltered + * +APT_EM_COMBINE_EVENT_OUT_FILT_SIGNAL -- The source of combine event is filtered + */ +typedef enum { + APT_EM_COMBINE_EVENT_OUT_ORIG_SIGNAL = 0x00000000U, + APT_EM_COMBINE_EVENT_OUT_FILT_SIGNAL = 0x00000001U, +} APT_EMCombineEventOut; + +/** + * @brief Polarity of mask window. + */ +typedef enum { + APT_BLANK_EVENT_INSIDE_MASK_WIN = 0x00000000U, + APT_BLANK_EVENT_OUTSIDE_MASK_WIN = 0x00000001U, +} APT_MaskWinPolarity; + +/** + * @brief Reset mode of mask window and count capture. + */ +typedef enum { + APT_RESET_MASK_WIN_DISABLE = 0x00000000U, + APT_RESET_MASK_WIN_CNTR_ZERO = 0x00000001U, + APT_RESET_MASK_WIN_CNTR_PERIOD = 0x00000002U, + APT_RESET_MASK_WIN_CNTR_ZERO_PERIOD = 0x00000003U, +} APT_MaskWinResetMode; + +/** + * @brief Clock source of valley capture. + */ +typedef enum { + APT_VALLY_CAP_USE_MAIN_CLOCK = 0x00000000U, + APT_VALLEY_CAP_USE_DIVIDER_CLOCK = 0x00000001U, +} APT_ValleyCapClkMode; + +/** + * @brief Trigger source of valley capture. + */ +typedef enum { + APT_VALLEY_CAP_SRC_DISABLE = 0x00000000U, + APT_VALLEY_CAP_SRC_CNTR_ZERO = 0x00000001U, + APT_VALLEY_CAP_SRC_CNTR_PERIOD = 0x00000002U, + APT_VALLEY_CAP_SRC_CNTR_ZERO_PERIOD = 0x00000003U, + APT_VALLEY_CAP_SRC_COMBINE_EVENT_A1 = 0x00000004U, + APT_VALLEY_CAP_SRC_COMBINE_EVENT_A2 = 0x00000005U, + APT_VALLEY_CAP_SRC_COMBINE_EVENT_B1 = 0x00000006U, + APT_VALLEY_CAP_SRC_COMBINE_EVENT_B2 = 0x00000007U, +} APT_ValleyCapRstType; + +/** + * @brief Edge type of valley capture. + */ +typedef enum { + APT_VALLEY_CAP_RISING_EDGE = 0x00000000U, + APT_VALLEY_CAP_FALLING_EDGE = 0x00000001U, +} APT_ValleyCapEdgeType; + +/** + * @brief Delay calibration of valley capture. + * @details Delay calibration: + * + APT_VCAP_SW_DELAY -- Delay value = software delay value + * + APT_VCAP_VCNT_DELAY_DIVIDE_1_SW_DELAY -- Delay value = capture count value + software delay value + * + APT_VCAP_VCNT_DELAY_DIVIDE_2_SW_DELAY -- Delay value = capture count value / 2 + software delay value + * + APT_VCAP_VCNT_DELAY_DIVIDE_4_SW_DELAY -- Delay value = capture count value / 4 + software delay value + * + APT_VCAP_VCNT_DELAY_DIVIDE_8_SW_DELAY -- Delay value = capture count value / 8 + software delay value + * + APT_VCAP_VCNT_DELAY_DIVIDE_16_SW_DELAY -- Delay value = capture count value / 16 + software delay value + * + APT_VCAP_VCNT_DELAY_DIVIDE_32_SW_DELAY -- Delay value = capture count value / 32 + software delay value + */ +typedef enum { + APT_VCAP_SW_DELAY = 0x00000000U, + APT_VCAP_VCNT_DELAY_DIVIDE_1_SW_DELAY = 0x00000001U, + APT_VCAP_VCNT_DELAY_DIVIDE_2_SW_DELAY = 0x00000002U, + APT_VCAP_VCNT_DELAY_DIVIDE_4_SW_DELAY = 0x00000003U, + APT_VCAP_VCNT_DELAY_DIVIDE_8_SW_DELAY = 0x00000004U, + APT_VCAP_VCNT_DELAY_DIVIDE_16_SW_DELAY = 0x00000005U, + APT_VCAP_VCNT_DELAY_DIVIDE_32_SW_DELAY = 0x00000006U, +} APT_ValleyDelayMode; + +/** + * @brief Start and stop edge of valley capture. + */ +typedef enum { + APT_VALLEY_COUNT_START_EDGE = 0x00000000U, + APT_VALLEY_COUNT_STOP_EDGE = 0x00000001U, +} APT_ValleyCountEdge; + +/** + * @brief Edge filter mode of Event Management submodule. + */ +typedef enum { + APT_EM_EDGEFILTER_MODE_RISING = 0x00000000U, + APT_EM_EDGEFILTER_MODE_FALLING = 0x00000002U, + APT_EM_EDGEFILTER_MODE_BOTH = 0x00000003U, +} APT_EMEdgeFilterMode; + +/** + * @brief Sync-in source of slave APT module. + */ +typedef enum { + APT_SYNCIN_SRC_APT0_SYNCOUT = 0x00000000U, + APT_SYNCIN_SRC_APT1_SYNCOUT = 0x00000001U, + APT_SYNCIN_SRC_APT2_SYNCOUT = 0x00000002U, + APT_SYNCIN_SRC_APT3_SYNCOUT = 0x00000003U, + APT_SYNCIN_SRC_APT4_SYNCOUT = 0x00000004U, + APT_SYNCIN_SRC_APT5_SYNCOUT = 0x00000005U, + APT_SYNCIN_SRC_APT6_SYNCOUT = 0x00000006U, + APT_SYNCIN_SRC_APT7_SYNCOUT = 0x00000007U, + APT_SYNCIN_SRC_APT8_SYNCOUT = 0x00000008U, + APT_SYNCIN_SRC_CAPM0_SYNCOUT = 0x00000009U, + APT_SYNCIN_SRC_CAPM1_SYNCOUT = 0x0000000AU, + APT_SYNCIN_SRC_CAPM2_SYNCOUT = 0x0000000BU, + APT_SYNCIN_SRC_GPIO_EVENT_4 = 0x0000000CU, + APT_SYNCIN_SRC_GPIO_EVENT_5 = 0x0000000DU, + APT_SYNCIN_SRC_DISABLE = 0x0000000EU, +} APT_SyncInSrc; + +/** + * @brief Sync-out mode of master APT module. + * @details Sync-out mode: + * + APT_SYNCOUT_ONE_SHOT_MODE -- One-Shot synchronization mode + * + APT_SYNCOUT_MULTIPLE_MODE -- Multiple synchronization mode + */ +typedef enum { + APT_SYNCOUT_ONE_SHOT_MODE = 0x00000000U, + APT_SYNCOUT_MULTIPLE_MODE = 0x00000001U, +} APT_SyncOutMode; + +/** + * @brief Selection of sync-out latch when using one-shot sync-out mode. + * @details Sync-out latch: + * + APT_SYNCOUT_LATCH_SET_ON_SW_FORCE -- Select rg_latset_otsyn as the latch set condition + * + APT_SYNCOUT_LATCH_SET_ON_GLB_LOAD -- Select rg_latset_otgld as the latch set condition + */ +typedef enum { + APT_SYNCOUT_LATCH_SET_ON_SW_FORCE = 0x00000000U, + APT_SYNCOUT_LATCH_SET_ON_GLB_LOAD = 0x00000001U, +} APT_SyncOutLatSetSel; + +/** + * @brief Source of peripheral synchronization. + */ +typedef enum { + APT_PER_SYNCOUT_SRC_DISABLE = 0x00000000U, + APT_PER_SYNCOUT_SRC_CNTR_ZERO = 0x00000001U, + APT_PER_SYNCOUT_SRC_CNTR_PERIOD = 0x00000002U, + APT_PER_SYNCOUT_SRC_CNTR_ZERO_PERIOD = 0x00000003U, + APT_PER_SYNCOUT_SRC_CNTR_CMPC_UP = 0x00000004U, + APT_PER_SYNCOUT_SRC_CNTR_CMPC_DOWN = 0x00000005U, + APT_PER_SYNCOUT_SRC_CNTR_CMPD_UP = 0x00000006U, + APT_PER_SYNCOUT_SRC_CNTR_CMPD_DOWN = 0x00000007U, +} APT_PeriphSyncOutSrc; + +/** + * @brief Global buffer load mode. + */ +typedef enum { + APT_GLB_LOAD_ONE_SHOT_MODE = 0x00000000U, + APT_GLB_LOAD_MULTIPLE_MODE = 0x00000001U, +} APT_GlobalLoadMode; + +/** + * @brief The buffer of the registers that support buffer register. + */ +typedef enum { + APT_REG_BUFFER_TC_PRD = 0x00000001U, + APT_REG_BUFFER_TC_REFA = 0x00000002U, + APT_REG_BUFFER_TC_REFB = 0x00000004U, + APT_REG_BUFFER_TC_REFC = 0x00000008U, + APT_REG_BUFFER_TC_REFD = 0x00000010U, + APT_REG_BUFFER_PG_ACT_A = 0x00000040U, + APT_REG_BUFFER_PG_ACT_B = 0x00000080U, + APT_REG_BUFFER_PG_OUT_FRC = 0x00000100U, + APT_REG_BUFFER_DG_RED = 0x00000400U, + APT_REG_BUFFER_DG_FED = 0x00000800U, + APT_REG_BUFFER_DG_CFG = 0x00001000U, +} APT_RegBuffer; + +/** + * @brief Software force events. + */ +typedef enum { + APT_FORCE_EVENT_COUNTER_SYNC = 0x00000001U, + APT_FORCE_EVENT_SYNCOUT = 0x00000010U, + APT_FORCE_EVENT_SYNC_PERIPH = 0x00000100U, + APT_FORCE_EVENT_GLOBAL_LOAD = 0x00001000U, + APT_FORCE_EVENT_VALLEY_CAP_RST = 0x00010000U, + APT_FORCE_EVENT_ADC_START_A = 0x00100000U, + APT_FORCE_EVENT_ADC_START_B = 0x00200000U, + APT_FORCE_EVENT_TIMER_INTERRUPT = 0x01000000U, + APT_FORCE_EVENT_PWM_ACTION_BUF_LOAD = 0x10000000U, +} APT_ForceEvtType; + +/** + * @brief Software force events. + * @details Reference point selection. + * + APT_REFERENCE_DOTA -- Select referece dot A as action trigger point. + * + APT_REFERENCE_DOTB -- Select referece dot B as action trigger point. + * + APT_REFERENCE_DOTC -- Select referece dot C as action trigger point. + * + APT_REFERENCE_DOTD -- Select referece dot D as action trigger point. + */ +typedef enum { + APT_REFERENCE_DOTA = 0x00000000U, + APT_REFERENCE_DOTB = 0x00000001U, + APT_REFERENCE_DOTC = 0x00000002U, + APT_REFERENCE_DOTD = 0x00000003U, +} APT_RefDotSelect; + +/** + * @brief Configure action point parameters. + * @details Property of the action point. + * + refDotValue -- the action point value. + * + refDotDivValue -- frequency division value of the action point. + * + pwmChannel -- number of channels for which the action point needs to be changed. @ref APT_PWMChannel + * + actionEvent -- action event configure of reference point. @ref APT_PWMActionEvent + * + action -- triggle action of reference point. @ref APT_PWMAction + * @note: the value of Reference Point must be less than or equal to the value of period. + */ +typedef struct { + unsigned int refDotValue; + APT_PWMChannel pwmChannel; /* PWM channel selection. */ + APT_PWMActionEvent actionEvent; /* Point triggle action event. */ + APT_PWMAction action; /* Point action. */ +} APT_RefDotParameters; +/** + * @} + */ + +/** + * @defgroup APT_REG_Definition APT Register Structure. + * @brief APT Register Structure Definition. + * @{ + */ +typedef union { + unsigned int reg; + struct { + unsigned int sub_version : 4; /**< ip subversion */ + unsigned int main_version : 4; /**< ip main verison */ + unsigned int reserved0 : 24; + } BIT; +} volatile VER_INFO_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_cnt_mode : 2; /**< timer work mode */ + unsigned int reserved1 : 14; + unsigned int rg_div_fac : 12; /**< divider factor */ + unsigned int rg_emu_stop : 2; /**< emulation stop mode */ + unsigned int reserved2 : 2; + } BIT; +} volatile TC_MODE_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_cnt_phs : 16; /**< timer's phase */ + unsigned int reserved3 : 15; + unsigned int rg_cnt_dir : 1; /**< timer count direction */ + } BIT; +} volatile TC_PHS_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_cnt_ovrid : 16; /**< timer count init value */ + unsigned int reserved4 : 15; + unsigned int rg_cnt_ovrid_en : 1; /**< timer and divider init enable */ + } BIT; +} volatile TC_OVRID_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_cnt_prd : 16; /* count period */ + unsigned int reserved5 : 16; + } BIT; +} volatile TC_PRD_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_cnt_refa : 16; /* reference A counter value */ + unsigned int reserved6 : 16; + } BIT; +} volatile TC_REFA_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_cnt_refb : 16; /* reference B counter value */ + unsigned int reserved7 : 16; + } BIT; +} volatile TC_REFB_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_cnt_refc : 16; /* reference C counter value */ + unsigned int reserved8 : 16; + } BIT; +} volatile TC_REFC_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_cnt_refd : 16; /* reference D counter value */ + unsigned int reserved9 : 16; + } BIT; +} volatile TC_REFD_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_prd_buf_en : 1; /**< period buffer enable */ + unsigned int rg_prd_gld_en : 1; /**< period global buffer enable */ + unsigned int reserved10 : 2; + unsigned int rg_refa_buf_en : 1; /**< reference A buffer enable */ + unsigned int rg_refa_gld_en : 1; /**< reference A global buffer enable */ + unsigned int rg_refb_buf_en : 1; /**< reference B buffer enable */ + unsigned int rg_refb_gld_en : 1; /**< reference B global buffer enable */ + unsigned int rg_refc_buf_en : 1; /**< reference C buffer enable */ + unsigned int rg_refc_gld_en : 1; /**< reference C global buffer enable */ + unsigned int rg_refd_buf_en : 1; /**< reference D buffer enable */ + unsigned int rg_refd_gld_en : 1; /**< reference D global buffer enable */ + unsigned int reserved11 : 20; + } BIT; +} volatile TC_BUF_EN_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_prd_ld_zroen : 1; /**< period value register load at zero */ + unsigned int reserved12 : 1; + unsigned int rg_prd_ld_a1en : 1; /**< period value load at evt_a1 */ + unsigned int rg_prd_ld_b1en : 1; /**< period value load at evt_b1 */ + unsigned int rg_prd_ld_synen : 1; /**< period value load at sync signal input */ + unsigned int reserved13 : 27; + } BIT; +} volatile TC_PRD_LOAD_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_refa_ld_zroen : 1; /**< reference A value load at zero */ + unsigned int rg_refa_ld_prden : 1; /**< reference A value load at period */ + unsigned int rg_refa_ld_a1en : 1; /**< reference A value load at evt_a1 */ + unsigned int rg_refa_ld_b1en : 1; /**< reference A value load at evt_b1 */ + unsigned int rg_refa_ld_synen : 1; /**< reference A value load at sync signal input */ + unsigned int reserved14 : 3; + unsigned int rg_refb_ld_zroen : 1; /**< reference B value load at zero */ + unsigned int rg_refb_ld_prden : 1; /**< reference B value load at period */ + unsigned int rg_refb_ld_a1en : 1; /**< reference B value load at evt_a1 */ + unsigned int rg_refb_ld_b1en : 1; /**< reference B value load at evt_b1 */ + unsigned int rg_refb_ld_synen : 1; /**< reference B value load at sync signal input */ + unsigned int reserved15 : 3; + unsigned int rg_refc_ld_zroen : 1; /**< reference C value load at zero */ + unsigned int rg_refc_ld_prden : 1; /**< reference C value load at period */ + unsigned int rg_refc_ld_a1en : 1; /**< reference C value load at evt_a1 */ + unsigned int rg_refc_ld_b1en : 1; /**< reference C value load at evt_b1 */ + unsigned int rg_refc_ld_synen : 1; /**< reference C value load at sync signal input */ + unsigned int reserved16 : 3; + unsigned int rg_refd_ld_zroen : 1; /**< reference D value load at zero */ + unsigned int rg_refd_ld_prden : 1; /**< reference D value load at period */ + unsigned int rg_refd_ld_a1en : 1; /**< reference D value load at evt_a1 */ + unsigned int rg_refd_ld_b1en : 1; /**< reference D value load at evt_b1 */ + unsigned int rg_refd_ld_synen : 1; /**< reference D value load at sync signal input */ + unsigned int reserved17 : 3; + } BIT; +} volatile TC_REF_LOAD_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_mskwd_psel : 1; /**< mask window polarity */ + unsigned int reserved18 : 30; + unsigned int rg_mskwd_en : 1; /**< mask window enable */ + } BIT; +} volatile TC_MWD_EN_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_mwd_refa : 16; /**< mask window reference value A */ + unsigned int reserved19 : 16; + } BIT; +} volatile TC_MWDREFA_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_mwd_refb : 16; /**< mask window reference value B */ + unsigned int reserved20 : 16; + } BIT; +} volatile TC_MWDREFB_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_mwdrefa_act_inc : 2; /**< action at reference A increase */ + unsigned int rg_mwdrefa_act_dec : 2; /**< action at reference A decrease */ + unsigned int rg_mwdrefb_act_inc : 2; /**< action at reference B increase */ + unsigned int rg_mwdrefb_act_dec : 2; /**< action at reference B decrease */ + unsigned int reserved21 : 24; + } BIT; +} volatile TC_MWD_ACT_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_mwdrefa_buf_en : 1; /**< mask window reference A buffer enable */ + unsigned int rg_mwdrefa_gld_en : 1; /**< mask window reference A global buffer enable */ + unsigned int rg_mwdrefb_buf_en : 1; /**< mask window reference B buffer enable */ + unsigned int rg_mwdrefb_gld_en : 1; /**< mask window reference B global buffer enable */ + unsigned int rg_mwd_act_buf_en : 1; /**< mask window action buffer enable */ + unsigned int rg_mwd_act_gld_en : 1; /**< mask window action global buffer enable */ + unsigned int reserved22 : 26; + } BIT; +} volatile TC_MWD_BUF_EN_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_mwdrefa_ld_zroen : 1; /**< mask window refrence A load at zero enable */ + unsigned int rg_mwdrefa_ld_prden : 1; /**< mask window refrence A load at period enable */ + unsigned int reserved23 : 1; + unsigned int rg_mwdrefb_ld_zroen : 1; /**< mask window refrence B load at zero enable */ + unsigned int rg_mwdrefb_ld_prden : 1; /**< mask window refrence B load at period enable */ + unsigned int reserved24 : 1; + unsigned int rg_mwd_act_ld_zroen : 1; /**< mask window action register load at zero enable */ + unsigned int rg_mwd_act_ld_prden : 1; /**< mask window action register load at period enable */ + unsigned int reserved25 : 24; + } BIT; +} volatile TC_MWD_LOAD_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int ro_cnt_val : 16; /**< counter value */ + unsigned int ro_div_cnt : 12; /**< divider value */ + unsigned int reserved26 : 3; + unsigned int ro_cnt_dir : 1; /**< count direction */ + } BIT; +} volatile TC_STS_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_pga_act_zro : 2; /**< PG channel A action at zero */ + unsigned int rg_pga_act_prd : 2; /**< PG channel A action at period */ + unsigned int rg_pga_act_refa_inc : 2; /**< PG channel A action at reference A increase */ + unsigned int rg_pga_act_refa_dec : 2; /**< PG channel A action at reference A decrease */ + unsigned int rg_pga_act_refb_inc : 2; /**< PG channel A action at reference B increase */ + unsigned int rg_pga_act_refb_dec : 2; /**< PG channel A action at reference B decrease */ + unsigned int rg_pga_act_refc_inc : 2; /**< PG channel A action at reference C increase */ + unsigned int rg_pga_act_refc_dec : 2; /**< PG channel A action at reference C decrease */ + unsigned int rg_pga_act_refd_inc : 2; /**< PG channel A action at reference D increase */ + unsigned int rg_pga_act_refd_dec : 2; /**< PG channel A action at reference D decrease */ + unsigned int rg_pga_act_evtc1_inc : 2; /**< PG channel A action at evt_c1 increase */ + unsigned int rg_pga_act_evtc1_dec : 2; /**< PG channel A action at evt_c1 decrease */ + unsigned int rg_pga_act_evtc2_inc : 2; /**< PG channel A action at evt_c2 increase */ + unsigned int rg_pga_act_evtc2_dec : 2; /**< PG channel A action at evt_c2 decrease */ + unsigned int reserved27 : 4; + } BIT; +} volatile PG_ACT_A_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_pgb_act_zro : 2; /**< PG channel A action at zero */ + unsigned int rg_pgb_act_prd : 2; /**< PG channel A action at period */ + unsigned int rg_pgb_act_refa_inc : 2; /**< PG channel A action at reference A increase */ + unsigned int rg_pgb_act_refa_dec : 2; /**< PG channel A action at reference A decrease */ + unsigned int rg_pgb_act_refb_inc : 2; /**< PG channel A action at reference B increase */ + unsigned int rg_pgb_act_refb_dec : 2; /**< PG channel A action at reference B decrease */ + unsigned int rg_pgb_act_refc_inc : 2; /**< PG channel A action at reference C increase */ + unsigned int rg_pgb_act_refc_dec : 2; /**< PG channel A action at reference C decrease */ + unsigned int rg_pgb_act_refd_inc : 2; /**< PG channel A action at reference D increase */ + unsigned int rg_pgb_act_refd_dec : 2; /**< PG channel A action at reference D decrease */ + unsigned int rg_pgb_act_evtc1_inc : 2; /**< PG channel A action at evt_c1 increase */ + unsigned int rg_pgb_act_evtc1_dec : 2; /**< PG channel A action at evt_c1 decrease */ + unsigned int rg_pgb_act_evtc2_inc : 2; /**< PG channel A action at evt_c2 increase */ + unsigned int rg_pgb_act_evtc2_dec : 2; /**< PG channel A action at evt_c2 decrease */ + unsigned int reserved28 : 4; + } BIT; +} volatile PG_ACT_B_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_pga_act_evt_frc : 2; /**< channel A force action select */ + unsigned int rg_pga_evt_frc : 1; /**< enable a force action at channel A */ + unsigned int reserved29 : 1; + unsigned int rg_pgb_act_evt_frc : 2; /**< channel A force action select */ + unsigned int rg_pgb_evt_frc : 1; /**< enable a force action at channel A */ + unsigned int reserved30 : 25; + } BIT; +} volatile PG_ACT_FRC_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_pga_frc_act : 2; /**< channel A force output action select */ + unsigned int rg_pga_frc_en : 1; /**< channel A force output action enable */ + unsigned int reserved31 : 1; + unsigned int rg_pgb_frc_act : 2; /**< channel A force output action select */ + unsigned int rg_pgb_frc_en : 1; /**< channel A force output action enable */ + unsigned int reserved32 : 25; + } BIT; +} volatile PG_OUT_FRC_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_acta_buf_en : 1; /**< channel A action value buffer enable */ + unsigned int rg_acta_gld_en : 1; /**< channel A action value global buffer enable */ + unsigned int rg_actb_buf_en : 1; /**< channel B action value buffer enable */ + unsigned int rg_actb_gld_en : 1; /**< channel B action value global buffer enable */ + unsigned int rg_frc_buf_en : 1; /**< force output config buffer enable */ + unsigned int rg_frc_gld_en : 1; /**< force output config global buffer enable */ + unsigned int reserved33 : 26; + } BIT; +} volatile PG_BUF_EN_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_pga_actld_zroen : 1; /**< enable PG channel A action value independent load at zero */ + unsigned int rg_pga_actld_prden : 1; /**< enable PG channel A action value independent load at period */ + unsigned int rg_pga_actld_a1en : 1; /**< enable PG channel A action value independent load at evt_a1 */ + unsigned int rg_pga_actld_b1en : 1; /**< enable PG channel A action value independent load at evt_b1 */ + unsigned int rg_pga_actld_synen : 1; /**< enable PG channel A action value independent load at sync signal */ + unsigned int reserved34 : 3; + unsigned int rg_pgb_actld_zroen : 1; /**< enable PG channel B action value independent load at zero */ + unsigned int rg_pgb_actld_prden : 1; /**< enable PG channel B action value independent load at period */ + unsigned int rg_pgb_actld_a1en : 1; /**< enable PG channel B action value independent load at evt_a1 */ + unsigned int rg_pgb_actld_b1en : 1; /**< enable PG channel B action value independent load at evt_b1 */ + unsigned int rg_pgb_actld_synen : 1; /**< enable PG channel B action value independent load at sync signal */ + unsigned int reserved35 : 3; + unsigned int rg_pg_frcld_zroen : 1; /**< enable force action config value independent load at zero */ + unsigned int rg_pg_frcld_prden : 1; /**< enable force action config value independent load at period */ + unsigned int reserved36 : 2; + unsigned int rg_pg_frcld_synen : 1; /**< enable force action config value independent load at sync signal */ + unsigned int reserved37 : 3; + unsigned int reserved38 : 8; + } BIT; +} volatile PG_ACT_LD_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_pga_evtc1_sel : 4; /**< pga_evtc1 source select */ + unsigned int rg_pga_evtc2_sel : 4; /**< pga_evtc2 source select */ + unsigned int rg_pgb_evtc1_sel : 4; /**< pgb_evtc1 source select */ + unsigned int rg_pgb_evtc2_sel : 4; /**< pgb_evtc2 source select */ + unsigned int reserved39 : 16; + } BIT; +} volatile PG_EVTC_SEL_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_dg_red : 16; /**< deadband time at rising edge */ + unsigned int reserved0 : 16; + } BIT; +} volatile DG_RED_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_dg_fed : 16; /**< deadband timer at falling edge */ + unsigned int reserved0 : 16; + } BIT; +} volatile DG_FED_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_dg_red_isel : 2; /**< rising edge delay source input select */ + unsigned int rg_dg_fed_isel : 2; /**< falling edge delay source input select */ + unsigned int rg_dg_red_osel : 2; /**< rising edge delay polarity select */ + unsigned int rg_dg_fed_osel : 2; /**< falling edge delay polarity select */ + unsigned int rg_dga_osel : 1; /**< dga output waveform swap select */ + unsigned int rg_dgb_osel : 1; /**< dgb output waveform swap select */ + unsigned int reserved42 : 22; + } BIT; +} volatile DG_CFG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_red_buf_en : 1; /**< rising edge delay value buffer enable */ + unsigned int rg_red_gld_en : 1; /**< rising edge delay value global buffer enable */ + unsigned int rg_fed_buf_en : 1; /**< falling edge delay value buffer enable */ + unsigned int rg_fed_gld_en : 1; /**< falling edge delay value global buffer enable */ + unsigned int rg_cfg_buf_en : 1; /**< deadband config buffer enable */ + unsigned int rg_cfg_gld_en : 1; /**< deadband config global enable */ + unsigned int reserved43 : 26; + } BIT; +} volatile DG_BUF_EN_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_red_ld_zroen : 1; /**< rising edge delay value load independent at zero */ + unsigned int rg_red_ld_prden : 1; /**< rising edge delay value load independent at period */ + unsigned int reserved44 : 6; + unsigned int rg_fed_ld_zroen : 1; /**< falling edge delay value load independent at zero */ + unsigned int rg_fed_ld_prden : 1; /**< falling edge delay value load independent at period */ + unsigned int reserved45 : 6; + unsigned int rg_cfg_ld_zroen : 1; /**< deadband config register value load independent at zero */ + unsigned int rg_cfg_ld_prden : 1; /**< deadband config register value load independent at period */ + unsigned int reserved46 : 14; + } BIT; +} volatile DG_BUF_LOAD_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_oc_en_evt1 : 1; /**< evtio1 output control enable */ + unsigned int rg_oc_en_evt2 : 1; /**< evtio2 output control enable */ + unsigned int rg_oc_en_evt3 : 1; /**< evtio3 output control enable */ + unsigned int reserved47 : 1; + unsigned int rg_oc_en_evts1 : 1; /**< evts1 output control enable */ + unsigned int rg_oc_en_evts2 : 1; /**< evts2 output control enable */ + unsigned int rg_oc_en_evts3 : 1; /**< evts3 output control enable */ + unsigned int reserved48 : 1; + unsigned int rg_oc_en_evta1 : 1; /**< evta1 output control enable */ + unsigned int rg_oc_en_evta2 : 1; /**< evta2 output control enable */ + unsigned int rg_oc_en_evtb1 : 1; /**< evtb1 output control enable */ + unsigned int rg_oc_en_evtb2 : 1; /**< evtb2 output control enable */ + unsigned int reserved49 : 4; + unsigned int rg_oc_mode_evt1 : 1; /**< evtio1 output mode select */ + unsigned int rg_oc_mode_evt2 : 1; /**< evtio2 output mode select */ + unsigned int rg_oc_mode_evt3 : 1; /**< evtio3 output mode select */ + unsigned int reserved50 : 1; + unsigned int rg_oc_mode_evts1 : 1; /**< evts1 output mode select */ + unsigned int rg_oc_mode_evts2 : 1; /**< evts2 output mode select */ + unsigned int rg_oc_mode_evts3 : 1; /**< evts3 output mode select */ + unsigned int reserved51 : 1; + unsigned int rg_oc_mode_evta1 : 1; /**< evta1 output mode select */ + unsigned int rg_oc_mode_evta2 : 1; /**< evta2 output mode select */ + unsigned int rg_oc_mode_evtb1 : 1; /**< evtb1 output mode select */ + unsigned int rg_oc_mode_evtb2 : 1; /**< evtb2 output mode select */ + unsigned int reserved52 : 4; + } BIT; +} volatile OC_MODE_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_oc_laten_evt1 : 1; /**< output control evtio1 latch event enable */ + unsigned int rg_oc_laten_evt2 : 1; /**< output control evtio2 latch event enable */ + unsigned int rg_oc_laten_evt3 : 1; /**< output control evtio3 latch event enable */ + unsigned int reserved53 : 1; + unsigned int rg_oc_laten_evts1 : 1; /**< output control evtis1 latch event enable */ + unsigned int rg_oc_laten_evts2 : 1; /**< output control evtis2 latch event enable */ + unsigned int rg_oc_laten_evts3 : 1; /**< output control evtis3 latch event enable */ + unsigned int reserved54 : 1; + unsigned int rg_oc_laten_evta1 : 1; /**< output control evtia1 latch event enable */ + unsigned int rg_oc_laten_evta2 : 1; /**< output control evtia2 latch event enable */ + unsigned int rg_oc_laten_evtb1 : 1; /**< output control evtib1 latch event enable */ + unsigned int rg_oc_laten_evtb2 : 1; /**< output control evtib2 latch event enable */ + unsigned int reserved55 : 20; + } BIT; +} volatile OC_LAT_EN_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_oca_evtio_inc : 3; /**< channel A output control action at evtio increase */ + unsigned int rg_oca_evta1_inc : 3; /**< channel A output control action at evta1 increase */ + unsigned int rg_oca_evta2_inc : 3; /**< channel A output control action at evta2 increase */ + unsigned int rg_oca_evtb1_inc : 3; /**< channel A output control action at evtb1 increase */ + unsigned int rg_oca_evtb2_inc : 3; /**< channel A output control action at evtb2 increase */ + unsigned int reserved56 : 1; + unsigned int rg_oca_evtio_dec : 3; /**< channel A output control action at evtio decrease */ + unsigned int rg_oca_evta1_dec : 3; /**< channel A output control action at evta1 decrease */ + unsigned int rg_oca_evta2_dec : 3; /**< channel A output control action at evta2 decrease */ + unsigned int rg_oca_evtb1_dec : 3; /**< channel A output control action at evtb1 decrease */ + unsigned int rg_oca_evtb2_dec : 3; /**< channel A output control action at evtb2 decrease */ + unsigned int reserved57 : 1; + } BIT; +} volatile OC_ACT_A_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_ocb_evtio_inc : 3; /**< channel B output control action at evtio increase */ + unsigned int rg_ocb_evta1_inc : 3; /**< channel B output control action at evta1 increase */ + unsigned int rg_ocb_evta2_inc : 3; /**< channel B output control action at evta2 increase */ + unsigned int rg_ocb_evtb1_inc : 3; /**< channel B output control action at evtb1 increase */ + unsigned int rg_ocb_evtb2_inc : 3; /**< channel B output control action at evtb2 increase */ + unsigned int reserved58 : 1; + unsigned int rg_ocb_evtio_dec : 3; /**< channel B output control action at evtio decrease */ + unsigned int rg_ocb_evta1_dec : 3; /**< channel B output control action at evta1 decrease */ + unsigned int rg_ocb_evta2_dec : 3; /**< channel B output control action at evta2 decrease */ + unsigned int rg_ocb_evtb1_dec : 3; /**< channel B output control action at evtb1 decrease */ + unsigned int rg_ocb_evtb2_dec : 3; /**< channel B output control action at evtb2 decrease */ + unsigned int reserved59 : 1; + } BIT; +} volatile OC_ACT_B_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int ro_oc_flag_evt1 : 1; /**< output control evtio1 flag */ + unsigned int ro_oc_flag_evt2 : 1; /**< output control evtio2 flag */ + unsigned int ro_oc_flag_evt3 : 1; /**< output control evtio3 flag */ + unsigned int reserved60 : 1; + unsigned int ro_oc_flag_evts1 : 1; /**< output control evts1 flag */ + unsigned int ro_oc_flag_evts2 : 1; /**< output control evts2 flag */ + unsigned int ro_oc_flag_evts3 : 1; /**< output control evts3 flag */ + unsigned int reserved61 : 1; + unsigned int ro_oc_flag_evta1 : 1; /**< output control evta1 flag */ + unsigned int ro_oc_flag_evta2 : 1; /**< output control evta2 flag */ + unsigned int ro_oc_flag_evtb1 : 1; /**< output control evtb1 flag */ + unsigned int ro_oc_flag_evtb2 : 1; /**< output control evtb2 flag */ + unsigned int reserved62 : 3; + unsigned int ro_int_flag_evt : 1; /**< output control event interrupt flag */ + unsigned int rg_oc_clr_evt1 : 1; /**< output control evtio1 clear bit */ + unsigned int rg_oc_clr_evt2 : 1; /**< output control evtio2 clear bit */ + unsigned int rg_oc_clr_evt3 : 1; /**< output control evtio3 clear bit */ + unsigned int reserved63 : 1; + unsigned int rg_oc_clr_evts1 : 1; /**< output control evts1 clear bit */ + unsigned int rg_oc_clr_evts2 : 1; /**< output control evts2 clear bit */ + unsigned int rg_oc_clr_evts3 : 1; /**< output control evts3 clear bit */ + unsigned int reserved64 : 1; + unsigned int rg_oc_clr_evta1 : 1; /**< output control evta1 clear bit */ + unsigned int rg_oc_clr_evta2 : 1; /**< output control evta2 clear bit */ + unsigned int rg_oc_clr_evtb1 : 1; /**< output control evtb1 clear bit */ + unsigned int rg_oc_clr_evtb2 : 1; /**< output control evtb2 clear bit */ + unsigned int reserved65 : 3; + unsigned int rg_int_clr_evt : 1; /**< output control event interrupt clear bit */ + } BIT; +} volatile OC_EVT_FLAG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_oc_clr_zroen_evt1 : 1; /**< enable clear evtio1 at zero */ + unsigned int rg_oc_clr_zroen_evt2 : 1; /**< enable clear evtio2 at zero */ + unsigned int rg_oc_clr_zroen_evt3 : 1; /**< enable clear evtio3 at zero */ + unsigned int reserved66 : 1; + unsigned int rg_oc_clr_zroen_evts1 : 1; /**< enable clear evts1 at zero */ + unsigned int rg_oc_clr_zroen_evts2 : 1; /**< enable clear evts2 at zero */ + unsigned int rg_oc_clr_zroen_evts3 : 1; /**< enable clear evts3 at zero */ + unsigned int reserved67 : 1; + unsigned int rg_oc_clr_zroen_evta1 : 1; /**< enable clear evta1 at zero */ + unsigned int rg_oc_clr_zroen_evta2 : 1; /**< enable clear evta2 at zero */ + unsigned int rg_oc_clr_zroen_evtb1 : 1; /**< enable clear evtb1 at zero */ + unsigned int rg_oc_clr_zroen_evtb2 : 1; /**< enable clear evtb2 at zero */ + unsigned int reserved68 : 4; + unsigned int rg_oc_clr_prden_evt1 : 1; /**< enable clear evtio1 at period */ + unsigned int rg_oc_clr_prden_evt2 : 1; /**< enable clear evtio2 at period */ + unsigned int rg_oc_clr_prden_evt3 : 1; /**< enable clear evtio3 at period */ + unsigned int reserved69 : 1; + unsigned int rg_oc_clr_prden_evts1 : 1; /**< enable clear evts1 at period */ + unsigned int rg_oc_clr_prden_evts2 : 1; /**< enable clear evts2 at period */ + unsigned int rg_oc_clr_prden_evts3 : 1; /**< enable clear evts3 at period */ + unsigned int reserved70 : 1; + unsigned int rg_oc_clr_prden_evta1 : 1; /**< enable clear evta1 at period */ + unsigned int rg_oc_clr_prden_evta2 : 1; /**< enable clear evta2 at period */ + unsigned int rg_oc_clr_prden_evtb1 : 1; /**< enable clear evtb1 at period */ + unsigned int rg_oc_clr_prden_evtb2 : 1; /**< enable clear evtb2 at period */ + unsigned int reserved71 : 4; + } BIT; +} volatile OC_PRD_CLR_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_oc_frc_evt1 : 1; /**< force enable evtio1 event */ + unsigned int rg_oc_frc_evt2 : 1; /**< force enable evtio2 event */ + unsigned int rg_oc_frc_evt3 : 1; /**< force enable evtio3 event */ + unsigned int reserved72 : 1; + unsigned int rg_oc_frc_evts1 : 1; /**< force enable evts1 event */ + unsigned int rg_oc_frc_evts2 : 1; /**< force enable evts2 event */ + unsigned int rg_oc_frc_evts3 : 1; /**< force enable evts3 event */ + unsigned int reserved73 : 1; + unsigned int rg_oc_frc_evta1 : 1; /**< force enable evta1 event */ + unsigned int rg_oc_frc_evta2 : 1; /**< force enable evta2 event */ + unsigned int rg_oc_frc_evtb1 : 1; /**< force enable evtb1 event */ + unsigned int rg_oc_frc_evtb2 : 1; /**< force enable evtb2 event */ + unsigned int reserved74 : 20; + } BIT; +} volatile OC_FRC_EVT_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_int_en_evt1 : 1; /**< enable evtio1 intterrupt */ + unsigned int rg_int_en_evt2 : 1; /**< enable evtio2 intterrupt */ + unsigned int rg_int_en_evt3 : 1; /**< enable evtio3 intterrupt */ + unsigned int reserved75 : 1; + unsigned int rg_int_en_evts1 : 1; /**< enable evts1 intterrupt */ + unsigned int rg_int_en_evts2 : 1; /**< enable evts2 intterrupt */ + unsigned int rg_int_en_evts3 : 1; /**< enable evts3 intterrupt */ + unsigned int reserved76 : 1; + unsigned int rg_int_en_evta1 : 1; /**< enable evta1 intterrupt */ + unsigned int rg_int_en_evta2 : 1; /**< enable evta2 intterrupt */ + unsigned int rg_int_en_evtb1 : 1; /**< enable evtb1 intterrupt */ + unsigned int rg_int_en_evtb2 : 1; /**< enable evtb2 intterrupt */ + unsigned int reserved77 : 20; + } BIT; +} volatile INT_EVT_EN_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_int_en_tmr : 1; /**< enable timer interrupt */ + unsigned int reserved0 : 31; + } BIT; +} volatile INT_TMR_EN_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int ro_int_flag_tmr : 1; /**< timer interrupt clear bit */ + unsigned int reserved79 : 15; + unsigned int rg_int_clr_tmr : 1; /**< timer interrupt flag */ + unsigned int reserved80 : 15; + } BIT; +} volatile INT_TMR_FLAG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_int_tmr_sel : 4; /**< timer interrupt source select */ + unsigned int reserved81 : 28; + } BIT; +} volatile INT_TMR_SEL_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_int_prsc_prd : 4; /**< timer interrupt scale ratio */ + unsigned int reserved82 : 4; + unsigned int ro_int_prsc_cnt : 4; /**< timer interrupt scale ratio value read register */ + unsigned int reserved83 : 4; + unsigned int rg_int_prsc_phs : 4; /**< timer interrupt scale ratio phase value */ + unsigned int reserved84 : 4; + unsigned int rg_int_prsc_synen : 1; /**< timer interrupt scale ratio phase value */ + unsigned int rg_int_prsc_frc : 1; + unsigned int reserved85 : 6; + } BIT; +} volatile INT_PRSC_CFG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_csa_tmr_sel : 4; /**< timer condition to trigger adc sample through SOCA */ + unsigned int reserved86 : 12; + unsigned int rg_csa_en_cs : 1; /**< timer trigger adc sample through SOCA enable */ + unsigned int reserved87 : 15; + } BIT; +} volatile CS_TMR_SELA_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_csb_tmr_sel : 4; /**< timer condition to trigger adc sample through SOCB */ + unsigned int reserved88 : 12; + unsigned int rg_csb_en_cs : 1; /**< timer trigger adc sample through SOCB enable */ + unsigned int reserved89 : 15; + } BIT; +} volatile CS_TMR_SELB_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_csa_prsc_prd : 4; /**< trigger adc scale ratio through SOCB */ + unsigned int reserved90 : 12; + unsigned int rg_csa_prsc_phs : 4; /**< trigger adc scale ratio phase value through SOCB */ + unsigned int reserved91 : 4; + unsigned int rg_csa_prsc_synen : 1; /**< trigger adc scale ratio phase value sync enable through SOCB */ + unsigned int rg_csa_prsc_frc : 1; /**< trigger adc scale ratio phase value force enable through SOCB */ + unsigned int reserved92 : 6; + } BIT; +} volatile CS_PRSCA_CFG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_csb_prsc_prd : 4; /**< trigger adc scale ratio through SOCB */ + unsigned int reserved93 : 12; + unsigned int rg_csb_prsc_phs : 4; /**< trigger adc scale ratio phase value through SOCB */ + unsigned int reserved94 : 4; + unsigned int rg_csb_prsc_synen : 1; /**< trigger adc scale ratio phase value sync enable through SOCB */ + unsigned int rg_csb_prsc_frc : 1; /**< trigger adc scale ratio phase value force enable through SOCB */ + unsigned int reserved95 : 6; + } BIT; +} volatile CS_PRSCB_CFG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int ro_csa_flag : 1; /**< SOCA adc start sample flag */ + unsigned int ro_csb_flag : 1; /**< SOCB adc start sample flag */ + unsigned int reserved96 : 14; + unsigned int rg_csa_clr_flag : 1; /**< SOCA adc start sample flag clear bit */ + unsigned int rg_csb_clr_flag : 1; /**< SOCB adc start sample flag clear bit */ + unsigned int reserved97 : 14; + } BIT; +} volatile CS_FLAG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_dma_breq_sel : 2; /**< DMA Burst request source select */ + unsigned int rg_dma_sreq_sel : 2; /**< DMA single request source select */ + unsigned int reserved98 : 28; + } BIT; +} volatile CS_DMA_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_evtio1_psel : 2; /**< evtio1's polarity */ + unsigned int rg_evtio2_psel : 2; /**< evtio2's polarity */ + unsigned int rg_evtio3_psel : 2; /**< evtio3's polarity */ + unsigned int rg_evtio4_psel : 2; /**< evtio4's polarity */ + unsigned int rg_evtio5_psel : 2; /**< evtio5's polarity */ + unsigned int reserved99 : 6; + unsigned int rg_evtsys1_psel : 2; /**< evts1's polarity */ + unsigned int rg_evtsys2_psel : 2; /**< evts2's polarity */ + unsigned int rg_evtsys3_psel : 2; /**< evts3's polarity */ + unsigned int reserved100 : 10; + } BIT; +} volatile EM_EVTIO_PSEL_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_evtmp1_psel : 2; /**< evtmp1's polarity */ + unsigned int rg_evtmp2_psel : 2; /**< evtmp2's polarity */ + unsigned int rg_evtmp3_psel : 2; /**< evtmp3's polarity */ + unsigned int rg_evtmp4_psel : 2; /**< evtmp4's polarity */ + unsigned int rg_evtmp5_psel : 2; /**< evtmp5's polarity */ + unsigned int rg_evtmp6_psel : 2; /**< evtmp6's polarity */ + unsigned int reserved101 : 20; + } BIT; +} volatile EM_EVTMP_PSEL_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_em_a1_oren : 9; /**< group A event 1 logic OR source enable */ + unsigned int reserved102 : 7; + unsigned int rg_em_a2_oren : 9; /**< group A event 2 logic OR source enable */ + unsigned int reserved103 : 7; + } BIT; +} volatile EM_AOR_EN_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_em_b1_oren : 9; /**< group B event 1 logic OR source enable */ + unsigned int reserved104 : 7; + unsigned int rg_em_b2_oren : 9; /**< group B event 2 logic OR source enable */ + unsigned int reserved105 : 7; + } BIT; +} volatile EM_BOR_EN_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_em_a1_sel : 4; /**< group A event 1 source select */ + unsigned int rg_em_a2_sel : 4; /**< group A event 2 source select */ + unsigned int rg_em_b1_sel : 4; /**< group B event 1 source select */ + unsigned int rg_em_b2_sel : 4; /**< group B event 2 source select */ + unsigned int rg_evta1t_sel : 3; /**< evta1t source select */ + unsigned int reserved106 : 1; + unsigned int rg_evta2t_sel : 3; /**< evta2t source select */ + unsigned int reserved107 : 1; + unsigned int rg_evtb1t_sel : 3; /**< evtb1t source select */ + unsigned int reserved108 : 1; + unsigned int rg_evtb2t_sel : 3; /**< evtb2t source select */ + unsigned int reserved109 : 1; + } BIT; +} volatile EM_MRG_SEL_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_evta1_sel : 1; /**< em_evta1 event source select */ + unsigned int rg_evta2_sel : 1; /**< em_evta2 event source select */ + unsigned int rg_evtb1_sel : 1; /**< em_evtb1 event source select */ + unsigned int rg_evtb2_sel : 1; /**< em_evtb2 event source select */ + unsigned int rg_evtfilt_sel : 2; /**< em_evfilt event source select */ + unsigned int reserved110 : 26; + } BIT; +} volatile EM_OUT_SEL_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_syni_sel : 4; /**< em_evt_syni source select */ + unsigned int reserved111 : 12; + unsigned int ro_syni_flag : 1; /**< em_evt_syni event active flag */ + unsigned int reserved112 : 3; + unsigned int rg_syni_clr : 1; /**< em_evt_syni event active flag clear bit */ + unsigned int reserved113 : 11; + } BIT; +} volatile SYNI_CFG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_syncnt_a1en : 1; /**< TC value sync at em_evta1_pulse */ + unsigned int rg_syncnt_b1en : 1; /**< TC value sync at em_evtb1_pulse */ + unsigned int rg_syncnt_synien : 1; /**< TC value sync at em_synci_pulse */ + unsigned int reserved114 : 29; + } BIT; +} volatile SYNCNT_CFG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_syno_zroen : 1; /**< sync out at zero enable */ + unsigned int rg_syno_prden : 1; /**< sync out at period enable */ + unsigned int rg_syno_a1en : 1; /**< sync out at a1 enable */ + unsigned int rg_syno_b1en : 1; /**< sync out at b1 enable */ + unsigned int reserved115 : 1; + unsigned int rg_syno_refben : 1; /**< sync out at reference B match enable */ + unsigned int rg_syno_refcen : 1; /**< sync out at reference C match enable */ + unsigned int rg_syno_refden : 1; /**< sync out at reference D match enable */ + unsigned int rg_mode_syno : 1; /**< sync out mode select */ + unsigned int rg_latset_sel : 1; /**< latch condition */ + unsigned int rg_latset_otsyn : 1; /**< control a sync out latch bit enable */ + unsigned int reserved116 : 21; + } BIT; +} volatile SYNO_CFG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_gld_zroen : 1; /**< enable global load when count zero */ + unsigned int rg_gld_prden : 1; /**< enable global load when count period */ + unsigned int rg_gld_cntsynen : 1; /**< enable global load when em_cnt_syn enable */ + unsigned int reserved117 : 5; + unsigned int rg_gld_prsc_prd : 4; /**< global load scale ratio */ + unsigned int rg_mode_gld : 1; /**< buffer global load mode select */ + unsigned int reserved118 : 3; + unsigned int rg_latset_otgld : 1; /**< control a global latch bit enable */ + unsigned int reserved119 : 15; + } BIT; +} volatile GLB_LOAD_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int tc_prd_ld_sts : 1; /**< count period buffer status */ + unsigned int tc_refa_ld_sts : 1; /**< reference A buffer status */ + unsigned int tc_refb_ld_sts : 1; /**< reference B buffer status */ + unsigned int tc_refc_ld_sts : 1; /**< reference C buffer status */ + unsigned int tc_refd_ld_sts : 1; /**< reference D buffer status */ + unsigned int reserved120 : 3; + unsigned int pg_act_a_ld_sts : 1; /**< channel A action buffer status */ + unsigned int pg_act_b_ld_sts : 1; /**< channel B buffer status */ + unsigned int pg_out_frc_ld_sts : 1; /**< PG putput force buffer status */ + unsigned int reserved121 : 1; + unsigned int dg_red_ld_sts : 1; /**< DG rising edge buffer status */ + unsigned int dg_fed_ld_sts : 1; /**< DG falling edge buffer status */ + unsigned int dg_cfg_ld_sts : 1; /**< DG config buffer status */ + unsigned int reserved122 : 1; + unsigned int tc_mwdrefa_ld_sts : 1; + unsigned int tc_mwdrefb_ld_sts : 1; + unsigned int tc_mwd_act_ld_sts : 1; + unsigned int reserved123 : 13; + } BIT; +} volatile LOAD_STS_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_syncnt_frc : 1; /**< force an em_cnt_syn event */ + unsigned int reserved124 : 3; + unsigned int rg_syno_frc : 1; /**< force an apt_syno event */ + unsigned int reserved125 : 3; + unsigned int reserved126 : 4; + unsigned int rg_gld_frc : 1; /**< force an em_glb_ld event*/ + unsigned int reserved127 : 3; + unsigned int reserved128 : 4; + unsigned int rg_csa_syn_frc : 1; /**< force a SOCA trigger */ + unsigned int rg_csb_syn_frc : 1; /**< force a SOCB trigger */ + unsigned int reserved129 : 2; + unsigned int rg_int_syn_frc : 1; /**< force timer interrupt scale load sync init value */ + unsigned int reserved130 : 3; + unsigned int rg_synpg_frc : 1; /**< force create waveform buffer indepent load trigger event */ + unsigned int reserved131 : 3; + } BIT; +} volatile SYN_FRC_REG; + +/** + * @brief APT registers definition structure. + */ +typedef struct { + VER_INFO_REG VER_INFO; /**< VER_INFO_REG. Offset address 0x00000000U. */ + unsigned int reserved0[3]; + TC_MODE_REG TC_MODE; /**< TC_MODE_REG. Offset address 0x00000010U. */ + TC_PHS_REG TC_PHS; /**< TC_PHS_REG. Offset address 0x00000014U. */ + TC_OVRID_REG TC_OVRID; /**< TC_OVRID_REG. Offset address 0x00000018U. */ + unsigned int reserved1; + TC_PRD_REG TC_PRD; /**< TC_PRD_REG. Offset address 0x00000020U. */ + unsigned int reserved2[3]; + TC_REFA_REG TC_REFA; /**< TC_REFA_REG. Offset address 0x00000030U. */ + TC_REFB_REG TC_REFB; /**< TC_REFB_REG. Offset address 0x00000034U. */ + TC_REFC_REG TC_REFC; /**< TC_REFC_REG. Offset address 0x00000038U. */ + TC_REFD_REG TC_REFD; /**< TC_REFD_REG. Offset address 0x0000003CU. */ + unsigned int reserved3[4]; + TC_BUF_EN_REG TC_BUF_EN; /**< TC_BUF_EN_REG. Offset address 0x00000040U. */ + TC_PRD_LOAD_REG TC_PRD_LOAD; /**< TC_PRD_LOAD_REG. Offset address 0x00000050U. */ + TC_REF_LOAD_REG TC_REF_LOAD; /**< TC_REF_LOAD_REG. Offset address 0x00000054U. */ + TC_MWD_EN_REG TC_MWD_EN; /**< TC_MWD_EN_REG. Offset address 0x0000005CU. */ + TC_MWDREFA_REG TC_MWDREFA; /**< TC_MWDREFA_REG. Offset address 0x00000060U. */ + TC_MWDREFB_REG TC_MWDREFB; /**< TC_MWDREFB_REG. Offset address 0x00000064U. */ + TC_MWD_ACT_REG TC_MWD_ACT; /**< TC_MWD_ACT_REG. Offset address 0x00000068U. */ + TC_MWD_BUF_EN_REG TC_MWD_BUF_EN; /**< TC_MWD_BUF_EN_REG. Offset address 0x0000006cU. */ + TC_MWD_LOAD_REG TC_MWD_LOAD; /**< TC_MWD_LOAD_REG. Offset address 0x00000070U. */ + TC_STS_REG TC_STS; /**< TC_STS_REG. Offset address 0x00000060U. */ + unsigned int reserved4[34]; + PG_ACT_A_REG PG_ACT_A; /**< PG_ACT_A_REG. Offset address 0x00000100U. */ + PG_ACT_B_REG PG_ACT_B; /**< PG_ACT_B_REG. Offset address 0x00000104U. */ + unsigned int reserved5[2]; + PG_ACT_FRC_REG PG_ACT_FRC; /**< PG_ACT_FRC_REG. Offset address 0x00000110U. */ + PG_OUT_FRC_REG PG_OUT_FRC; /**< PG_OUT_FRC_REG. Offset address 0x00000114U. */ + unsigned int reserved6[2]; + PG_BUF_EN_REG PG_BUF_EN; /**< PG_BUF_EN_REG. Offset address 0x00000120U. */ + unsigned int reserved7[3]; + PG_ACT_LD_REG PG_ACT_LD; /**< PG_ACT_LD_REG. Offset address 0x00000130U. */ + unsigned int reserved8[3]; + PG_EVTC_SEL_REG PG_EVTC_SEL; /**< PG_EVTC_SEL_REG. Offset address 0x00000140U. */ + unsigned int reserved9[47]; + DG_RED_REG DG_RED; /**< DG_RED_REG. Offset address 0x00000200U. */ + DG_FED_REG DG_FED; /**< DG_FED_REG. Offset address 0x00000204U. */ + DG_CFG_REG DG_CFG; /**< DG_CFG_REG. Offset address 0x00000208U. */ + unsigned int reserved10; + DG_BUF_EN_REG DG_BUF_EN; /**< DG_BUF_EN_REG. Offset address 0x00000210U. */ + DG_BUF_LOAD_REG DG_BUF_LOAD; /**< DG_BUF_LOAD_REG. Offset address 0x00000214U. */ + unsigned int reserved11[58]; + OC_MODE_REG OC_MODE; /**< OC_MODE_REG. Offset address 0x00000300U. */ + OC_LAT_EN_REG OC_LAT_EN; /**< OC_LAT_EN_REG. Offset address 0x00000304U. */ + unsigned int reserved12[2]; + OC_ACT_A_REG OC_ACT_A; /**< OC_ACT_A_REG. Offset address 0x00000310U. */ + OC_ACT_B_REG OC_ACT_B; /**< OC_ACT_B_REG. Offset address 0x00000314U. */ + unsigned int reserved13[2]; + OC_EVT_FLAG_REG OC_EVT_FLAG; /**< OC_EVT_FLAG_REG. Offset address 0x00000320U. */ + OC_PRD_CLR_REG OC_PRD_CLR; /**< OC_PRD_CLR_REG. Offset address 0x00000324U. */ + unsigned int reserved14[2]; + OC_FRC_EVT_REG OC_FRC_EVT; /**< OC_FRC_EVT_REG. Offset address 0x00000330U. */ + unsigned int reserved15[55]; + INT_EVT_EN_REG INT_EVT_EN; /**< INT_EVT_EN_REG. Offset address 0x00000410U. */ + INT_TMR_EN_REG INT_TMR_EN; /**< INT_TMR_EN_REG. Offset address 0x00000414U. */ + unsigned int reserved16[2]; + INT_TMR_FLAG_REG INT_TMR_FLAG; /**< INT_TMR_FLAG_REG. Offset address 0x00000420U. */ + INT_TMR_SEL_REG INT_TMR_SEL; /**< INT_TMR_SEL_REG. Offset address 0x00000424U. */ + INT_PRSC_CFG_REG INT_PRSC_CFG; /**< INT_PRSC_CFG_REG. Offset address 0x00000428U. */ + unsigned int reserved17[53]; + CS_TMR_SELA_REG CS_TMR_SELA; /**< CS_TMR_SELA_REG. Offset address 0x00000500U. */ + CS_TMR_SELB_REG CS_TMR_SELB; /**< CS_TMR_SELB_REG. Offset address 0x00000504U. */ + CS_PRSCA_CFG_REG CS_PRSCA_CFG; /**< CS_PRSCA_CFG_REG. Offset address 0x00000508U. */ + CS_PRSCB_CFG_REG CS_PRSCB_CFG; /**< CS_PRSCB_CFG_REG. Offset address 0x0000050CU. */ + CS_FLAG_REG CS_FLAG; /**< CS_FLAG_REG. Offset address 0x00000510U. */ + unsigned int reserved18[3]; + CS_DMA_REG CS_DMA; /**< CS_DMA_REG. Offset address 0x00000520U. */ + unsigned int reserved19[55]; + EM_EVTIO_PSEL_REG EM_EVTIO_PSEL; /**< EM_EVTIO_PSEL_REG. Offset address 0x00000600U. */ + EM_EVTMP_PSEL_REG EM_EVTMP_PSEL; /**< EM_EVTMP_PSEL_REG. Offset address 0x00000604U. */ + EM_AOR_EN_REG EM_AOR_EN; /**< EM_AOR_EN_REG. Offset address 0x00000608U. */ + EM_BOR_EN_REG EM_BOR_EN; /**< EM_BOR_EN_REG. Offset address 0x0000060CU. */ + EM_MRG_SEL_REG EM_MRG_SEL; /**< EM_MRG_SEL_REG. Offset address 0x00000610U. */ + EM_OUT_SEL_REG EM_OUT_SEL; /**< EM_OUT_SEL_REG. Offset address 0x00000614U. */ + unsigned int reserved20[58]; + SYNI_CFG_REG SYNI_CFG; /**< SYNI_CFG_REG. Offset address 0x00000700U. */ + SYNCNT_CFG_REG SYNCNT_CFG; /**< SYNCNT_CFG_REG. Offset address 0x00000704U. */ + SYNO_CFG_REG SYNO_CFG; /**< SYNO_CFG_REG. Offset address 0x00000708U. */ + unsigned int reserved21; + GLB_LOAD_REG GLB_LOAD; /**< GLB_LOAD_REG. Offset address 0x000000710U. */ + unsigned int reserved22[3]; + LOAD_STS_REG LOAD_STS; /**< LOAD_STS_REG. Offset address 0x000000720U. */ + unsigned int reserved23[3]; + SYN_FRC_REG SYN_FRC; /**< SYN_FRC_REG. Offset address 0x00000730U. */ +} volatile APT_RegStruct; + +/** + * @brief Set the emulation stop mode of APT module. + * @param aptx APT register base address. + * @param emuMode Emulation stop mode. + * @retval None. + */ +static inline void DCL_APT_SetEmulationMode(APT_RegStruct *aptx, APT_EmulationMode emuMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(emuMode <= APT_EMULATION_STOP_APT); + aptx->TC_MODE.BIT.rg_emu_stop = emuMode; +} + +/** + * @brief Set the time-base divider factor. + * @param aptx APT register base address. + * @param divFactor Time-base divider factor. + * @retval None. + */ +static inline void DCL_APT_SetDividerFactor(APT_RegStruct *aptx, unsigned short divFactor) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(divFactor <= DIVIDER_FACTOR_MAX); + aptx->TC_MODE.BIT.rg_div_fac = divFactor; +} + +/** + * @brief Get the time-base divider factor. + * @param aptx APT register base address. + * @retval unsigned short: time-base divider factor. + */ +static inline unsigned short DCL_APT_GetDividerFactor(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->TC_MODE.BIT.rg_div_fac); +} + +/** + * @brief Set the count mode of time-base counter. + * @param aptx APT register base address. + * @param cntMode Count mode. + * @retval None. + */ +static inline void DCL_APT_SetTimeBaseCountMode(APT_RegStruct *aptx, APT_CountMode cntMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(cntMode <= APT_COUNT_MODE_FREEZE); + aptx->TC_MODE.BIT.rg_cnt_mode = cntMode; +} + +/** + * @brief Set the period of time-base counter. + * @param aptx APT register base address. + * @param periodCnt Time-base counter period. + * @retval None. + */ +static inline void DCL_APT_SetTimeBasePeriod(APT_RegStruct *aptx, unsigned short periodCnt) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->TC_PRD.BIT.rg_cnt_prd = periodCnt; +} + +/** + * @brief Get the period of time-base counter. + * @param aptx APT register base address. + * @retval unsigned short: time-base counter period + */ +static inline unsigned short DCL_APT_GetTimeBasePeriod(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->TC_PRD.BIT.rg_cnt_prd); +} + +/** + * @brief Set the count mode of slave APT module after synchronization. + * @param aptx APT register base address. + * @param syncCntMode Count mode after synchronization. + * @retval None. + */ +static inline void DCL_APT_SetCountModeAfterSync(APT_RegStruct *aptx, APT_SyncCountMode syncCntMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(syncCntMode >= APT_COUNT_MODE_AFTER_SYNC_DOWN); + APT_PARAM_CHECK_NO_RET(syncCntMode <= APT_COUNT_MODE_AFTER_SYNC_UP); + aptx->TC_PHS.BIT.rg_cnt_dir = syncCntMode; +} + +/** + * @brief Set the counter phase after synchronization. + * @param aptx APT register base address. + * @param cntPhase Counter phase after synchronization. + * @retval None. + */ +static inline void DCL_APT_SetCounterPhase(APT_RegStruct *aptx, unsigned short cntPhase) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + TC_PHS_REG tmp = aptx->TC_PHS; + tmp.BIT.rg_cnt_phs = cntPhase; + aptx->TC_PHS = tmp; +} + +/** + * @brief Set the software override value of time-base counter. + * @param aptx APT register base address. + * @param cntOvrid Software override value of time-base counter. + * @retval None. + */ +static inline void DCL_APT_SetCounterOverride(APT_RegStruct *aptx, unsigned short cntOvrid) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + TC_OVRID_REG tmp = aptx->TC_OVRID; + tmp.BIT.rg_cnt_ovrid = cntOvrid; + aptx->TC_OVRID = tmp; +} + +/** + * @brief Force software override on time-base divider and counter. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_ForceOverride(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->TC_OVRID.BIT.rg_cnt_ovrid_en = BASE_CFG_SET; +} + +/** + * @brief Set the count compare reference value of time-base counter. + * @param aptx APT register base address. + * @param ref Count compare reference. + * @param cntCmp Count compare reference value of counter. + * @retval None. + */ +static inline void DCL_APT_SetCounterCompare(APT_RegStruct *aptx, APT_CompareRef ref, unsigned short cntCmp) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ref >= APT_COMPARE_REFERENCE_A); + APT_PARAM_CHECK_NO_RET(ref <= APT_COMPARE_REFERENCE_D); + TC_REFA_REG tmpA; + TC_REFB_REG tmpB; + TC_REFC_REG tmpC; + TC_REFD_REG tmpD; + switch (ref) { + case APT_COMPARE_REFERENCE_A: + tmpA = aptx->TC_REFA; + tmpA.BIT.rg_cnt_refa = cntCmp; + aptx->TC_REFA = tmpA; + break; + case APT_COMPARE_REFERENCE_B: + tmpB = aptx->TC_REFB; + tmpB.BIT.rg_cnt_refb = cntCmp; + aptx->TC_REFB = tmpB; + break; + case APT_COMPARE_REFERENCE_C: + tmpC = aptx->TC_REFC; + tmpC.BIT.rg_cnt_refc = cntCmp; + aptx->TC_REFC = tmpC; + break; + case APT_COMPARE_REFERENCE_D: + tmpD = aptx->TC_REFD; + tmpD.BIT.rg_cnt_refd = cntCmp; + aptx->TC_REFD = tmpD; + break; + default: + break; + } +} + +/** + * @brief Get the count compare reference value of time-base counter. + * @param aptx APT register base address. + * @param ref Count compare reference. + * @retval unsigned short: Count compare reference value of counter. + */ +static inline unsigned short DCL_APT_GetCounterCompare(APT_RegStruct *aptx, APT_CompareRef ref) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_WITH_RET(ref >= APT_COMPARE_REFERENCE_A, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(ref <= APT_COMPARE_REFERENCE_D, BASE_STATUS_ERROR); + switch (ref) { + case APT_COMPARE_REFERENCE_A: + return (aptx->TC_REFA.BIT.rg_cnt_refa); + case APT_COMPARE_REFERENCE_B: + return (aptx->TC_REFB.BIT.rg_cnt_refb); + case APT_COMPARE_REFERENCE_C: + return (aptx->TC_REFC.BIT.rg_cnt_refc); + case APT_COMPARE_REFERENCE_D: + return (aptx->TC_REFD.BIT.rg_cnt_refd); + default: + return 0; + } +} + +/** + * @brief Set the buffer load mode of time-base period register. + * @param aptx APT register base address. + * @param prdLoadMode Buffer load mode of time-base period register. + * @retval None. + */ +static inline void DCL_APT_SetPeriodLoadMode(APT_RegStruct *aptx, APT_BufferLoadMode prdLoadMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(prdLoadMode >= APT_BUFFER_DISABLE); + APT_PARAM_CHECK_NO_RET(prdLoadMode <= APT_BUFFER_GLOBAL_LOAD); + aptx->TC_BUF_EN.reg &= (~0b11); /* Clear rg_prd_buf_en and rg_prd_gld_en */ + aptx->TC_BUF_EN.reg |= prdLoadMode; /* Write rg_prd_buf_en and rg_prd_gld_en */ +} + +/** + * @brief Enable the buffer load events of TC_PRD register + * @param aptx APT register base address. + * @param loadEvent The buffer load events of TC_PRD register + * A logical OR of valid values that can be passed as the loadEvent parameter + * Valid values for loadEvent are: + * APT_PERIOD_LOAD_EVENT_ZERO - When counter value equal to zeor + * APT_PERIOD_LOAD_EVENT_A1 - When combined event A1 is valid + * APT_PERIOD_LOAD_EVENT_B1 - When combined event B1 is valid + * APT_PERIOD_LOAD_EVENT_SYNC - When synchronization event is valid + * @retval None. + */ +static inline void DCL_APT_SetPeriodLoadEvent(APT_RegStruct *aptx, unsigned int prdLoadEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->TC_PRD_LOAD.reg = prdLoadEvent; +} + +/** + * @brief Set the buffer load mode of count compare reference register. + * @param aptx APT register base address. + * @param ref Count compare reference. + * @param cmpLoadMode Buffer load mode of count compare reference register. + * @retval None. + */ +static inline void DCL_APT_SetCompareLoadMode(APT_RegStruct *aptx, + APT_CompareRef ref, + APT_BufferLoadMode cmpLoadMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ref >= APT_COMPARE_REFERENCE_A); + APT_PARAM_CHECK_NO_RET(ref <= APT_COMPARE_REFERENCE_D); + APT_PARAM_CHECK_NO_RET(cmpLoadMode >= APT_BUFFER_DISABLE); + APT_PARAM_CHECK_NO_RET(cmpLoadMode <= APT_BUFFER_GLOBAL_LOAD); + unsigned int offsetA = 4; /* Buffer mode control bits offset of reference A */ + unsigned int tcBufField = 2; /* Field width of buffer load mode setting */ + unsigned int offset = offsetA + ref * tcBufField; + aptx->TC_BUF_EN.reg &= (~(0b11 << offset)); /* Clear rg_refx_gld_en and rg_refx_buf_en */ + aptx->TC_BUF_EN.reg |= (cmpLoadMode << offset); /* Write rg_refx_gld_en and rg_refx_buf_en */ +} + +/** + * @brief Enable the buffer load events of TC_REFA, TC_REFB, TC_REFC, TC_REFD register + * @param aptx APT register base address. + * @param ref Count compare reference + * @param loadEvent The buffer load events of TC_REFA, TC_REFB, TC_REFC, TC_REFD register + * A logical OR of valid values can be passed as the loadEvent parameter + * Valid values for loadEvent are: + * APT_COMPARE_LOAD_EVENT_ZERO - When counter value equal to zero + * APT_COMPARE_LOAD_EVENT_PERIOD - When counter value equal to period + * APT_COMPARE_LOAD_EVENT_A1 - When combined event A1 is valid + * APT_COMPARE_LOAD_EVENT_B1 - When combined event B1 is valid + * APT_COMPARE_LOAD_EVENT_SYNC - When synchronization event is valid + * @retval None. + */ +static inline void DCL_APT_SetCompareLoadEvent(APT_RegStruct *aptx, APT_CompareRef ref, unsigned int cmpLoadEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ref >= APT_COMPARE_REFERENCE_A); + APT_PARAM_CHECK_NO_RET(ref <= APT_COMPARE_REFERENCE_D); + unsigned int refBufField = 8; /* Field width of compare reference load event setting */ + aptx->TC_REF_LOAD.reg &= (~(0x1F << (ref * refBufField))); /* Clear bit field for load event selection */ + aptx->TC_REF_LOAD.reg |= (cmpLoadEvent << (ref * refBufField)); +} + +/** + * @brief Get the value of time-base divider. + * @param aptx APT register base address. + * @retval unsigned short: The value of time-base divider value. + */ +static inline unsigned short DCL_APT_GetDividerValue(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->TC_STS.BIT.ro_div_cnt); +} + +/** + * @brief Get the value of time-base counter. + * @param aptx APT register base address. + * @retval unsigned short: The value of time-base counter. + */ +static inline unsigned short DCL_APT_GetCounterValue(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->TC_STS.BIT.ro_cnt_val); +} + +/** + * @brief Return time base counter direction + * @param aptx APT register base address. + * @retval unsigned short: The direction of time base counter + * Valid return values are: + * APT_COUNTER_STATUS_COUNT_DOWN - The counter is counting down + * APT_COUNTER_STATUS_COUNT_UP - The counter is counting up + */ +static inline unsigned short DCL_APT_GetCounterDirection(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->TC_STS.BIT.ro_cnt_dir); +} + +/* --------------------------------------------------------------------------------------------- */ +/* PWM Generation (PG) submodule Direct Configuration Layer functions -------------------------- */ +/* --------------------------------------------------------------------------------------------- */ +/** + * @brief Set PWM waveform action on corresponding event. + * @param aptx APT register base address. + * @param channel PWM output channel. + * @param actEvent PWM waveform action event. + * @param action PWM waveform action. + * @retval None. + */ +static inline void DCL_APT_SetPWMAction(APT_RegStruct *aptx, + APT_PWMChannel channel, + APT_PWMActionEvent actEvent, + APT_PWMAction action) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(channel >= APT_PWM_CHANNEL_A); + APT_PARAM_CHECK_NO_RET(channel <= APT_PWM_CHANNEL_B); + APT_PARAM_CHECK_NO_RET(actEvent >= APT_PWM_ACTION_ON_TIMEBASE_ZERO); + APT_PARAM_CHECK_NO_RET(actEvent <= APT_PWM_ACTION_ON_C2_COUNT_DOWN); + APT_PARAM_CHECK_NO_RET(action <= APT_PWM_ACTION_TOGGLE); + if (channel == APT_PWM_CHANNEL_A) { + aptx->PG_ACT_A.reg &= (~(0b11 << actEvent)); + aptx->PG_ACT_A.reg |= (action << actEvent); + } else if (channel == APT_PWM_CHANNEL_B) { + aptx->PG_ACT_B.reg &= (~(0b11 << actEvent)); + aptx->PG_ACT_B.reg |= (action << actEvent); + } +} + +/** + * @brief Select the event source of PWM Generation event C1 or C2. + * This function is only used when C1 or C2 event is selected as PWM action event. + * @param aptx APT register base address. + * @param channel PWM output channel. + * @param eventCx The PWM Generation event, should be C1 or C2. + * @param eventCxSrc The trigger source of PWM Generation event C1 or C2. + * @retval None. + */ +static inline void DCL_APT_SelectCxEventSource(APT_RegStruct *aptx, + APT_PWMChannel channel, + APT_PGEventCx eventCx, + APT_PGEventCxSrc eventCxSrc) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET((channel >= APT_PWM_CHANNEL_A) && (channel <= APT_PWM_CHANNEL_B)); + APT_PARAM_CHECK_NO_RET(eventCx >= APT_PWM_GENERATION_EVENT_C1); + APT_PARAM_CHECK_NO_RET(eventCx <= APT_PWM_GENERATION_EVENT_C2); + APT_PARAM_CHECK_NO_RET(eventCxSrc >= APT_PG_EVT_C_FORBIDDEN); + APT_PARAM_CHECK_NO_RET(eventCxSrc <= APT_PG_EVT_C_SYNC_IN); + unsigned int chOffset = 8; /* Bit field offset of PWM output channel */ + unsigned int cxOffset = 4; /* Bit field offset of event Cx */ + aptx->PG_EVTC_SEL.reg &= (~(0b1111 << (channel * chOffset + eventCx * cxOffset))); + aptx->PG_EVTC_SEL.reg |= eventCxSrc << (channel * chOffset + eventCx * cxOffset); +} + +/** + * @brief Set the buffer load mode of PWM action register. + * @param aptx APT register base address. + * @param channel PWM output channel. + * @param loadMode Buffer load mode. + * @retval None. + */ +static inline void DCL_APT_SetPWMActionLoadMode(APT_RegStruct *aptx, + APT_PWMChannel channel, + APT_BufferLoadMode loadMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(channel >= APT_PWM_CHANNEL_A); + APT_PARAM_CHECK_NO_RET(channel <= APT_PWM_CHANNEL_B); + APT_PARAM_CHECK_NO_RET(loadMode >= APT_BUFFER_DISABLE); + APT_PARAM_CHECK_NO_RET(loadMode <= APT_BUFFER_GLOBAL_LOAD); + unsigned int bufFieldWidth = 2; /* Bit field width of buffer load mode setting */ + aptx->PG_BUF_EN.reg &= (~(0b11 << (channel * bufFieldWidth))); /* Clear rg_actx_gld_en and rg_actx_buf_en */ + aptx->PG_BUF_EN.reg |= (loadMode << (channel * bufFieldWidth)); /* Write rg_actx_gld_en and rg_actx_buf_en */ +} + +/** + * @brief Enable the buffer load events of PG_ACT_A or PG_ACT_B register + * @param aptx APT register base address. + * @param channel PWM output channel. + * @param loadEvent The buffer load events of PG_ACT_A or PG_ACT_B register + * A logical OR of valid values can be passed as the loadEvent parameter + * Valid values for loadEvent are: + * APT_ACTION_LOAD_EVENT_ZERO - When counter value equal to zero + * APT_ACTION_LOAD_EVENT_PERIOD - When counter value equal to period + * APT_ACTION_LOAD_EVENT_A1 - When combined event A1 is valid + * APT_ACTION_LOAD_EVENT_B1 - When combined event B1 is valid + * APT_ACTION_LOAD_EVENT_SYNC - When synchronization event is valid + * @retval None. + */ +static inline void DCL_APT_SetPWMActionLoadEvent(APT_RegStruct *aptx, + APT_PWMChannel channel, + unsigned int loadEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(channel >= APT_PWM_CHANNEL_A); + APT_PARAM_CHECK_NO_RET(channel <= APT_PWM_CHANNEL_B); + unsigned int actBufField = 8; /* Field width of PWM action load event setting */ + aptx->PG_ACT_LD.reg &= (~(0x1F << (channel * actBufField))); + aptx->PG_ACT_LD.reg |= (loadEvent << (channel * actBufField)); +} + +/** + * @brief Set the PWM waveform action on one-shot action software event. + * @param aptx APT register base address. + * @param channel PWM output channel. + * @param action PWM waveform action. + * @retval None. + */ +static inline void DCL_APT_SetSwOneShotPWMAction(APT_RegStruct *aptx, APT_PWMChannel channel, APT_PWMAction action) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(channel >= APT_PWM_CHANNEL_A); + APT_PARAM_CHECK_NO_RET(channel <= APT_PWM_CHANNEL_B); + APT_PARAM_CHECK_NO_RET(action >= APT_PWM_ACTION_HOLD); + APT_PARAM_CHECK_NO_RET(action <= APT_PWM_ACTION_TOGGLE); + if (channel == APT_PWM_CHANNEL_A) { + aptx->PG_ACT_FRC.BIT.rg_pga_act_evt_frc = action; + } else if (channel == APT_PWM_CHANNEL_B) { + aptx->PG_ACT_FRC.BIT.rg_pgb_act_evt_frc = action; + } +} + +/** + * @brief Force one-shot software event. + * @param aptx APT register base address. + * @param channel PWM output channel. + * @retval None. + */ +static inline void DCL_APT_ForceSwOneShotPWMAction(APT_RegStruct *aptx, APT_PWMChannel channel) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(channel >= APT_PWM_CHANNEL_A); + APT_PARAM_CHECK_NO_RET(channel <= APT_PWM_CHANNEL_B); + if (channel == APT_PWM_CHANNEL_A) { + aptx->PG_ACT_FRC.BIT.rg_pga_evt_frc = BASE_CFG_SET; + } else if (channel == APT_PWM_CHANNEL_B) { + aptx->PG_ACT_FRC.BIT.rg_pgb_evt_frc = BASE_CFG_SET; + } +} + +/** + * @brief Set the PWM waveform action on continuous action software event. + * @param aptx APT register base address. + * @param channel PWM output channel. + * @param action PWM waveform action + * @retval None. + */ +static inline void DCL_APT_SetSwContPWMAction(APT_RegStruct *aptx, APT_PWMChannel channel, APT_PWMContAction action) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(channel >= APT_PWM_CHANNEL_A); + APT_PARAM_CHECK_NO_RET(channel <= APT_PWM_CHANNEL_B); + APT_PARAM_CHECK_NO_RET(action >= APT_PWM_CONTINUOUS_ACTION_HOLD); + APT_PARAM_CHECK_NO_RET(action <= APT_PWM_CONTINUOUS_ACTION_HIGH); + if (channel == APT_PWM_CHANNEL_A) { + aptx->PG_OUT_FRC.BIT.rg_pga_frc_act = action; + } else if (channel == APT_PWM_CHANNEL_B) { + aptx->PG_OUT_FRC.BIT.rg_pgb_frc_act = action; + } +} + +static void APT_ForcePWMAOutputLow(APT_RegStruct *aptx) +{ + unsigned int risingOutSelect = aptx->DG_CFG.BIT.rg_dg_red_osel; + unsigned int fallingOutSelect = aptx->DG_CFG.BIT.rg_dg_fed_osel; + unsigned int risingInSelect = aptx->DG_CFG.BIT.rg_dg_red_isel; + unsigned int fallingInSelect = aptx->DG_CFG.BIT.rg_dg_fed_isel; + /* Enable force output. */ + aptx->PG_OUT_FRC.BIT.rg_pga_frc_en = BASE_CFG_ENABLE; + /* if PWMA invert */ + if (((risingOutSelect == APT_DB_RED_OUTPUT_INVERT) && (risingInSelect == APT_DB_RED_INPUT_PWM_A)) || \ + ((fallingOutSelect == APT_DB_FED_OUTPUT_INVERT) && (fallingInSelect == APT_DB_FED_INPUT_PWM_A))) { + aptx->PG_OUT_FRC.BIT.rg_pga_frc_act = APT_PWM_CONTINUOUS_ACTION_HIGH; /* if invert, set high */ + } else { /* if PWMA not invert */ + aptx->PG_OUT_FRC.BIT.rg_pga_frc_act = APT_PWM_CONTINUOUS_ACTION_LOW; /* if not invert, set low */ + } + return; +} + +static void APT_ForcePWMBOutputLow(APT_RegStruct *aptx) +{ + unsigned int risingOutSelect = aptx->DG_CFG.BIT.rg_dg_red_osel; + unsigned int fallingOutSelect = aptx->DG_CFG.BIT.rg_dg_fed_osel; + unsigned int risingInSelect = aptx->DG_CFG.BIT.rg_dg_red_isel; + unsigned int fallingInSelect = aptx->DG_CFG.BIT.rg_dg_fed_isel; + /* Enable force output */ + aptx->PG_OUT_FRC.BIT.rg_pgb_frc_en = BASE_CFG_ENABLE; + /* if PWMB invert */ + if (((risingOutSelect == APT_DB_RED_OUTPUT_INVERT) && (risingInSelect == APT_DB_RED_INPUT_PWM_B)) || \ + ((fallingOutSelect == APT_DB_FED_OUTPUT_INVERT) && (fallingInSelect == APT_DB_FED_INPUT_PWM_B))) { + aptx->PG_OUT_FRC.BIT.rg_pgb_frc_act = APT_PWM_CONTINUOUS_ACTION_HIGH; /* if invert, set high */ + } else { /* if PWMB not invert */ + aptx->PG_OUT_FRC.BIT.rg_pgb_frc_act = APT_PWM_CONTINUOUS_ACTION_LOW; /* if not invert, set low */ + } + return; +} + +/** + * @brief Both PWMA and PWMB output low level. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_ForcePWMOutputLow(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + + APT_ForcePWMAOutputLow(aptx); + APT_ForcePWMBOutputLow(aptx); + + return; +} + +/** + * @brief Set the buffer load mode of continuous aciton software event register. + * @param aptx APT register base address. + * @param loadMode Buffer load mode. + * @retval None. + */ +static inline void DCL_APT_SetSwContActionLoadMode(APT_RegStruct *aptx, APT_BufferLoadMode loadMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(loadMode >= APT_BUFFER_DISABLE); + APT_PARAM_CHECK_NO_RET(loadMode <= APT_BUFFER_GLOBAL_LOAD); + unsigned int bufFieldWidth = 4; /* Bit field width of buffer load mode setting */ + aptx->PG_BUF_EN.reg &= (~(0b11 << bufFieldWidth)); /* Clear rg_frc_gld_en and rg_frc_buf_en */ + aptx->PG_BUF_EN.reg |= (loadMode << bufFieldWidth); /* Write rg_frc_gld_en and rg_frc_buf_en */ +} + +/** + * @brief Enable the buffer load events of PG_OUT_FRC register + * @param aptx APT register base address. + * @param channel PWM output channel + * @param loadEvent The buffer load events of PG_OUT_FRC register + * A logical OR of valid values can be passed as the loadEvent parameter + * Valid values for loadEvent are: + * APT_ACTION_LOAD_EVENT_ZERO - When counter value equal to zero + * APT_ACTION_LOAD_EVENT_PERIOD - When counter value equal to period + * APT_ACTION_LOAD_EVENT_SYNC - When synchronization event is valid + * @retval None. + */ +static inline void DCL_APT_SetSwContActionLoadEvent(APT_RegStruct *aptx, unsigned int loadEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + unsigned int actBufField = 16; /* Field width of continuous PWM action load event setting */ + aptx->PG_ACT_LD.reg &= (~(0x1F << actBufField)); + aptx->PG_ACT_LD.reg |= (loadEvent << actBufField); +} + +/** + * @brief Enable continuous action software event. + * @param aptx APT register base address. + * @param channel PWM output channel. + * @retval None. + */ +static inline void DCL_APT_EnableSwContPWMAction(APT_RegStruct *aptx, APT_PWMChannel channel) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(channel >= APT_PWM_CHANNEL_A); + APT_PARAM_CHECK_NO_RET(channel <= APT_PWM_CHANNEL_B); + if (channel == APT_PWM_CHANNEL_A) { + aptx->PG_OUT_FRC.BIT.rg_pga_frc_en = BASE_CFG_SET; + } else if (channel == APT_PWM_CHANNEL_B) { + aptx->PG_OUT_FRC.BIT.rg_pgb_frc_en = BASE_CFG_SET; + } +} + +/** + * @brief Disable continuous action software event. + * @param aptx APT register base address. + * @param channel PWM output channel. + * @retval None. + */ +static inline void DCL_APT_DisableSwContPWMAction(APT_RegStruct *aptx, APT_PWMChannel channel) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(channel >= APT_PWM_CHANNEL_A); + APT_PARAM_CHECK_NO_RET(channel <= APT_PWM_CHANNEL_B); + if (channel == APT_PWM_CHANNEL_A) { + aptx->PG_OUT_FRC.BIT.rg_pga_frc_en = BASE_CFG_UNSET; + } else if (channel == APT_PWM_CHANNEL_B) { + aptx->PG_OUT_FRC.BIT.rg_pgb_frc_en = BASE_CFG_UNSET; + } +} + +/* --------------------------------------------------------------------------------------------- */ +/* Dead-Band Generation (DG) submodule Direct Configuration Layer functions -------------------- */ +/* --------------------------------------------------------------------------------------------- */ +/** + * @brief Configure the rising edge delay (RED) of Dead-Band Generation. + * @param aptx APT register base address. + * @param redInput The input source of RED counter. + * @param redOutMode The output of RED counter. + * @param dgaOutSwap The swap mode of Dead-Band Generation output signal A. + * true - Select the output of FED counter. + * false - Select the output of RED counter. + * @param redCount The count value of RED counter, in units of APT clock. + * @retval None. + */ +static inline void DCL_APT_SetDeadBandRisingEdge(APT_RegStruct *aptx, + APT_REDInput redInput, + APT_REDOutMode redOutMode, + bool dgaOutSwap, + unsigned short redCount) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(redInput >= APT_DB_RED_INPUT_PWM_A); + APT_PARAM_CHECK_NO_RET(redInput <= APT_DB_RED_INPUT_PWM_B); + APT_PARAM_CHECK_NO_RET(redOutMode >= APT_DB_RED_OUTPUT_NOT_INVERT); + APT_PARAM_CHECK_NO_RET(redOutMode <= APT_DB_RED_OUTPUT_PWM_A); + aptx->DG_CFG.BIT.rg_dg_red_isel = redInput; + aptx->DG_CFG.BIT.rg_dg_red_osel = redOutMode; + aptx->DG_CFG.BIT.rg_dga_osel = dgaOutSwap; + aptx->DG_RED.BIT.rg_dg_red = redCount; +} + +/** + * @brief Configure the falling edge delay (FED) of Dead-Band Generation. + * @param aptx APT register base address. + * @param fedInput The input source of FED counter. + * @param fedOutMode The output of FED counter. + * @param dgbOutSwap The swap mode of Dead-Band Generation output signal B. + * true - Select the output of RED counter. + * false - Select the output of FED counter. + * @param fedCount The count value of FED counter, in units of APT clock. + * @retval None. + */ +static inline void DCL_APT_SetDeadBandFallingEdge(APT_RegStruct *aptx, + APT_FEDInput fedInput, + APT_FEDOutMode fedOutMode, + bool dgbOutSwap, + unsigned short fedCount) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(fedInput >= APT_DB_FED_INPUT_PWM_B); + APT_PARAM_CHECK_NO_RET(fedInput <= APT_DB_FED_INPUT_ZERO); + APT_PARAM_CHECK_NO_RET(fedOutMode >= APT_DB_FED_OUTPUT_NOT_INVERT); + APT_PARAM_CHECK_NO_RET(fedOutMode <= APT_DB_FED_OUTPUT_PWM_B); + aptx->DG_CFG.BIT.rg_dg_fed_isel = fedInput; + aptx->DG_CFG.BIT.rg_dg_fed_osel = fedOutMode; + aptx->DG_CFG.BIT.rg_dgb_osel = dgbOutSwap; + aptx->DG_FED.BIT.rg_dg_fed = fedCount; +} + +/** + * @brief Set buffer load mode of Dead-Band configuration register. + * @param aptx APT register base address. + * @param dgCfgLoadMode Buffer load mode. + * @retval None. + */ +static inline void DCL_APT_SetDGConfigLoadMode(APT_RegStruct *aptx, APT_BufferLoadMode dgCfgLoadMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(dgCfgLoadMode >= APT_BUFFER_DISABLE); + APT_PARAM_CHECK_NO_RET(dgCfgLoadMode <= APT_BUFFER_GLOBAL_LOAD); + unsigned int bufFieldWidth = 4; /* Bit field width of buffer load mode setting */ + aptx->DG_BUF_EN.reg &= (~(0b11 << bufFieldWidth)); /* Clear rg_cfg_gld_en and rg_cfg_buf_en */ + aptx->DG_BUF_EN.reg |= (dgCfgLoadMode << bufFieldWidth); /* Write rg_cfg_gld_en and rg_cfg_buf_en */ +} + +/** + * @brief Enable the buffer load events of DG_CFG register. + * @param aptx APT register base address. + * @param loadEvent The buffer load events of DG_CFG register. + * A logical OR of valid values can be passed as the loadEvent parameter. + * Valid values for loadEvent are: + * APT_DEAD_BAND_LOAD_EVENT_ZERO - When time base counter value equal to zero. + * APT_DEAD_BAND_LOAD_EVENT_PERIOD - When time base counter value equal to period. + * @retval None. + */ +static inline void DCL_APT_SetDGConfigLoadEvent(APT_RegStruct *aptx, unsigned int dgCfgLoadEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + unsigned int dgBufField = 16; /* Field width of continuous PWM action load event setting */ + aptx->DG_BUF_LOAD.reg &= (~(0b11 << dgBufField)); + aptx->DG_BUF_LOAD.reg |= (dgCfgLoadEvent << dgBufField); +} + +/** + * @brief Set buffer load mode of Dead-Band rising edge delay counter register. + * @param aptx APT register base address. + * @param redCntLoadMode Buffer load mode. + * @retval None. + */ +static inline void DCL_APT_SetREDCounterLoadMode(APT_RegStruct *aptx, APT_BufferLoadMode redCntLoadMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(redCntLoadMode >= APT_BUFFER_DISABLE); + APT_PARAM_CHECK_NO_RET(redCntLoadMode <= APT_BUFFER_GLOBAL_LOAD); + aptx->DG_BUF_EN.reg &= (~(0b11 << 0)); /* Clear rg_red_gld_en and rg_red_buf_en */ + aptx->DG_BUF_EN.reg |= (redCntLoadMode << 0); /* Write rg_red_gld_en and rg_red_buf_en */ +} + +/** + * @brief Enable the buffer load events of DG_RED register + * @param aptx APT register base address. + * @param loadEvent The buffer load events of DG_RED register. + * A logical OR of valid values can be passed as the loadEvent parameter. + * Valid values for loadEvent are: + * APT_DEAD_BAND_LOAD_EVENT_ZERO - When time base counter value equal to zero. + * APT_DEAD_BAND_LOAD_EVENT_PERIOD - When time base counter value equal to period. + * @retval None. + */ +static inline void DCL_APT_SetREDCounterLoadEvent(APT_RegStruct *aptx, unsigned int redCntLoadEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->DG_BUF_LOAD.reg &= (~(0b11 << 0)); + aptx->DG_BUF_LOAD.reg |= (redCntLoadEvent << 0); +} + +/** + * @brief Set buffer load mode of Dead-Band falling edge delay counter register. + * @param aptx APT register base address. + * @param fedCntLoadMode Buffer load mode. + * @retval None. + */ +static inline void DCL_APT_SetFEDCounterLoadMode(APT_RegStruct *aptx, APT_BufferLoadMode fedCntLoadMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(fedCntLoadMode >= APT_BUFFER_DISABLE); + APT_PARAM_CHECK_NO_RET(fedCntLoadMode <= APT_BUFFER_GLOBAL_LOAD); + unsigned int bufFieldWidth = 2; /* Bit field width of buffer load mode setting */ + aptx->DG_BUF_EN.reg &= (~(0b11 << bufFieldWidth)); /* Clear rg_fed_gld_en and rg_fed_buf_en */ + aptx->DG_BUF_EN.reg |= (fedCntLoadMode << bufFieldWidth); /* Write rg_fed_gld_en and rg_fed_buf_en */ +} + +/** + * @brief Enable the buffer load events of DG_FED register. + * @param aptx APT register base address. + * @param loadEvent The buffer load events of DG_FED register. + * A logical OR of valid values can be passed as the loadEvent parameter. + * Valid values for loadEvent are: + * APT_DEAD_BAND_LOAD_EVENT_ZERO - When time base counter value equal to zero. + * APT_DEAD_BAND_LOAD_EVENT_PERIOD - When time base counter value equal to period. + * @retval None. + */ +static inline void DCL_APT_SetFEDCounterLoadEvent(APT_RegStruct *aptx, unsigned int fedCntLoadEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + unsigned int dgBufField = 8; /* Field width of continuous PWM action load event setting */ + aptx->DG_BUF_LOAD.reg &= (~(0b11 << dgBufField)); + aptx->DG_BUF_LOAD.reg |= (fedCntLoadEvent << dgBufField); +} + +/* --------------------------------------------------------------------------------------------- */ +/* Output Control (OC) submodule Direct Configuration Layer functions -------------------------- */ +/* --------------------------------------------------------------------------------------------- */ +/** + * @brief Enable an output control event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval None. + */ +static inline void DCL_APT_EnableOutCtrlEvent(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + aptx->OC_MODE.reg |= ocEvent; +} + +/** + * @brief Disable an output control event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval None. + */ +static inline void DCL_APT_DisableOutCtrlEvent(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + aptx->OC_MODE.reg &= ~ocEvent; +} + +/** + * @brief Clear OC_MODE register. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_ClearOCEventReg(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->OC_MODE.reg = 0; +} + +/** + * @brief Set output control mode of an output control event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @param ocEventMode Output control mode. + * @retval None. + */ +static inline void DCL_APT_SetOutCtrlEventMode(APT_RegStruct *aptx, + APT_OutCtrlEvent ocEvent, + APT_OutCtrlMode ocEventMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET((ocEvent >= APT_OC_NO_EVENT) && (ocEvent <= APT_OC_COMBINE_EVENT_B2)); + APT_PARAM_CHECK_NO_RET(ocEventMode >= APT_OUT_CTRL_ONE_SHOT); + APT_PARAM_CHECK_NO_RET(ocEventMode <= APT_OUT_CTRL_CYCLE_BY_CYBLE); + unsigned ocModeOffset = 16; /* Offset of output control mode setting */ + if (ocEventMode == APT_OUT_CTRL_ONE_SHOT) { + aptx->OC_MODE.reg &= (~(ocEvent << ocModeOffset)); /* Set rg_oc_mode_evtx to 0 */ + } else if (ocEventMode == APT_OUT_CTRL_CYCLE_BY_CYBLE) { + aptx->OC_MODE.reg |= (ocEvent << ocModeOffset); /* Set rg_oc_mode_evtx to 1 */ + } +} + +/** + * @brief Set output control action of an output control event. + * @param aptx APT register base address. + * @param channel PWM output channel. + * @param ocEvtDir Output control event that takes into consideration of counter direction. + * @param ocAction Output control action. + * @retval None. + */ +static inline void DCL_APT_SetOutCtrlAction(APT_RegStruct *aptx, + APT_PWMChannel channel, + APT_OutCtrlEventDir ocEvtDir, + APT_OutCtrlAction ocAction) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(channel >= APT_PWM_CHANNEL_A); + APT_PARAM_CHECK_NO_RET(channel <= APT_PWM_CHANNEL_B); + APT_PARAM_CHECK_NO_RET(ocEvtDir >= APT_OC_EVT_GPIO_OR_SYSTEM_UP); + APT_PARAM_CHECK_NO_RET(ocEvtDir <= APT_OC_EVT_COMBINE_EVENT_B2_DOWN); + APT_PARAM_CHECK_NO_RET(ocAction >= APT_OUT_CTRL_ACTION_DISABLE); + APT_PARAM_CHECK_NO_RET(ocAction <= APT_OUT_CTRL_ACTION_HIGH_Z); + if (channel == APT_PWM_CHANNEL_A) { + aptx->OC_ACT_A.reg &= (~(0b111 << ocEvtDir)); + aptx->OC_ACT_A.reg |= (ocAction << ocEvtDir); + } else if (channel == APT_PWM_CHANNEL_B) { + aptx->OC_ACT_B.reg &= (~(0b111 << ocEvtDir)); + aptx->OC_ACT_B.reg |= (ocAction << ocEvtDir); + } +} + +/** + * @brief Get the flag of an output control event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval bool: true, false. + */ +static inline bool DCL_APT_GetOutCtrlEventFlag(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_WITH_RET(ocEvent >= APT_OC_NO_EVENT, false); + APT_PARAM_CHECK_WITH_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2, false); + return ((aptx->OC_EVT_FLAG.reg & ocEvent) == ocEvent); +} + +/** + * @brief Clear the flag of an output control event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval None. + */ +static inline void DCL_APT_ClearOutCtrlEventFlag(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + unsigned int ocFlgOffset = 16; /* Offset of output control flag clear */ + aptx->OC_EVT_FLAG.reg |= (ocEvent << ocFlgOffset); +} + +/** + * @brief Enable the event latch of an output control event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval None. + */ +static inline void DCL_APT_EnableOutCtrlEventLatch(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + aptx->OC_LAT_EN.reg |= ocEvent; +} + +/** + * @brief Disable the event latch of an output control event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval None. + */ +static inline void DCL_APT_DisableOutCtrlEventLatch(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + aptx->OC_LAT_EN.reg &= ~ocEvent; +} + +/** + * @brief Set cycle-by-cycle event latch clear event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @param clrMode Latche clear event of cycle-by-cycle event. + * @retval None. + */ +static inline void DCL_APT_SetCBCLatchClearEvent(APT_RegStruct *aptx, + APT_OutCtrlEvent ocEvent, + APT_CBCClearMode clrMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + APT_PARAM_CHECK_NO_RET(clrMode >= APT_CLEAR_CBC_ON_CNTR_ZERO); + APT_PARAM_CHECK_NO_RET(clrMode <= APT_CLEAR_CBC_ON_CNTR_ZERO_PERIOD); + unsigned int cbcClrOffsetZero = 0; /* Offset of CBC latch clear on counter equal to 0 */ + unsigned int cbcClrOffsetPrd = 16; /* Offset of CBC latch clear on counter euqal to period */ + unsigned int mask = (ocEvent << cbcClrOffsetPrd) | (ocEvent << cbcClrOffsetZero); + mask &= clrMode; + aptx->OC_PRD_CLR.reg |= mask; +} + +/** + * @brief Enable a software output control event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval None. + */ +static inline void DCL_APT_EnableSwOutCtrlEvent(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + aptx->OC_FRC_EVT.reg |= ocEvent; +} + +/** + * @brief Disable a software output control event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval None. + */ +static inline void DCL_APT_DisableSwOutCtrlEvent(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + aptx->OC_FRC_EVT.reg &= (~ocEvent); +} + +/* --------------------------------------------------------------------------------------------- */ +/* Interrupt Generation (IG) submodule Direct Configuration Layer functions -------------------- */ +/* --------------------------------------------------------------------------------------------- */ +/** + * @brief Enable the output control event to generate an event interrupt. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval None. + */ +static inline void DCL_APT_EnableEventInterrupt(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + aptx->INT_EVT_EN.reg |= ocEvent; +} + +/** + * @brief Disable the output control event to generate an event interrupt.. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval None. + */ +static inline void DCL_APT_DisableEventInterrupt(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + aptx->INT_EVT_EN.reg &= (~ocEvent); +} + +/** + * @brief Enable timer interrupt of APT module. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_EnableTimerInterrupt(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->INT_TMR_EN.BIT.rg_int_en_tmr = BASE_CFG_SET; +} + +/** + * @brief Disable timer interrupt of APT module. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_DisableTimerInterrupt(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->INT_TMR_EN.BIT.rg_int_en_tmr = BASE_CFG_UNSET; +} + +/** + * @brief Get the event interrupt flag. + * @param aptx APT register base address. + * @retval bool: true, false. + */ +static inline bool DCL_APT_GetEventInterruptFlag(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->OC_EVT_FLAG.BIT.ro_int_flag_evt); +} + +/** + * @brief Clear the event interrupt flag. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_ClearEventInterruptFlag(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->OC_EVT_FLAG.BIT.rg_int_clr_evt = BASE_CFG_SET; +} + +/** + * @brief Get the timer interrupt flag. + * @param aptx APT register base address. + * @retval bool: true, false. + */ +static inline bool DCL_APT_GetTimerInterruptFlag(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->INT_TMR_FLAG.BIT.ro_int_flag_tmr); +} + +/** + * @brief Clear the timer interrupt flag. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_ClearTimerInterruptFlag(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->INT_TMR_FLAG.BIT.rg_int_clr_tmr = BASE_CFG_SET; +} + +/** + * @brief Select the source of timer interrupt. + * @param aptx APT register base address. + * @param tmrIntSrc Source of timer interrupt. + * @retval None. + */ +static inline void DCL_APT_SetTimerInterruptSrc(APT_RegStruct *aptx, APT_TimerInterruptSrc tmrIntSrc) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(tmrIntSrc >= APT_INT_SRC_CNTR_DISABLE); + APT_PARAM_CHECK_NO_RET(tmrIntSrc <= APT_INT_SRC_CNTR_CMPD_DOWN); + aptx->INT_TMR_SEL.BIT.rg_int_tmr_sel = tmrIntSrc; +} + +/** + * @brief Enable the synchronization of timer interrupt scale initial count value. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_EnableTimerInterruptCountSyncInit(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->INT_PRSC_CFG.BIT.rg_int_prsc_synen = BASE_CFG_SET; +} + +/** + * @brief Disable the synchronization of timer interrupt scale initial count value. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_DisableTimerInterruptCountSyncInit(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->INT_PRSC_CFG.BIT.rg_int_prsc_synen = BASE_CFG_UNSET; +} + +/** + * @brief Set the initial count value of timer interrupt scale. + * @param aptx APT register base address. + * @param intCntInitVal Initial count value of timer interrupt scale. + * @retval None. + */ +static inline void DCL_APT_SetTimerInterruptCountSyncInitVal(APT_RegStruct *aptx, unsigned short intCntInitVal) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(intCntInitVal <= TIMER_INTERRUPT_CNT_MAX); + aptx->INT_PRSC_CFG.BIT.rg_int_prsc_phs = intCntInitVal; +} + +/** + * @brief Set the count period of timer interrupt scale. + * @param aptx APT register base address. + * @param intCntPeriod Count period of timer interrupt scale. + * @retval None. + */ +static inline void DCL_APT_SetTimerInterruptCountPeriod(APT_RegStruct *aptx, unsigned short intCntPeriod) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(intCntPeriod <= TIMER_INTERRUPT_CNT_MAX); + aptx->INT_PRSC_CFG.BIT.rg_int_prsc_prd = intCntPeriod; +} + +/** + * @brief Get the count value of timer interrupt scale. + * @param aptx APT register base address. + * @retval unsigned short: Count value of timer interrupt scale. + */ +static inline unsigned short DCL_APT_GetTimerInterruptCount(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->INT_PRSC_CFG.BIT.ro_int_prsc_cnt); +} + +/** + * @brief Force the count value of timer interrupt scale to increase. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_ForceTimerInterruptCountIncr(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->INT_PRSC_CFG.BIT.rg_int_prsc_frc = BASE_CFG_SET; +} + +/* --------------------------------------------------------------------------------------------- */ +/* ADC Converter Start (CS) submodule Direct Configuration Layer functions --------------------- */ +/* --------------------------------------------------------------------------------------------- */ +/** + * @brief Enable the ADC trigger channel. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @retval None. + */ +static inline void DCL_APT_EnableADCTrigger(APT_RegStruct *aptx, APT_ADCTriggerChannel csTrgCh) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csTrgCh >= APT_ADC_CONVERSION_START_A); + APT_PARAM_CHECK_NO_RET(csTrgCh <= APT_ADC_CONVERSION_START_B); + if (csTrgCh == APT_ADC_CONVERSION_START_A) { + aptx->CS_TMR_SELA.BIT.rg_csa_en_cs = BASE_CFG_SET; + } else if (csTrgCh == APT_ADC_CONVERSION_START_B) { + aptx->CS_TMR_SELB.BIT.rg_csb_en_cs = BASE_CFG_SET; + } +} + +/** + * @brief Disable the ADC trigger channel. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @retval None. + */ +static inline void DCL_APT_DisableADCTrigger(APT_RegStruct *aptx, APT_ADCTriggerChannel csTrgCh) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csTrgCh >= APT_ADC_CONVERSION_START_A); + APT_PARAM_CHECK_NO_RET(csTrgCh <= APT_ADC_CONVERSION_START_B); + if (csTrgCh == APT_ADC_CONVERSION_START_A) { + aptx->CS_TMR_SELA.BIT.rg_csa_en_cs = BASE_CFG_UNSET; + } else if (csTrgCh == APT_ADC_CONVERSION_START_B) { + aptx->CS_TMR_SELB.BIT.rg_csb_en_cs = BASE_CFG_UNSET; + } +} + +/** + * @brief Select the source of ADC trigger channel. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @param csTrgSrc Source of ADC trigger. + * @retval None. + */ +static inline void DCL_APT_SetADCTriggerSrc(APT_RegStruct *aptx, + APT_ADCTriggerChannel csTrgCh, + APT_ADCTriggerSource csTrgSrc) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csTrgCh >= APT_ADC_CONVERSION_START_A); + APT_PARAM_CHECK_NO_RET(csTrgCh <= APT_ADC_CONVERSION_START_B); + APT_PARAM_CHECK_NO_RET(csTrgSrc <= APT_CS_SRC_CNTR_CMPD_DOWN); + if (csTrgCh == APT_ADC_CONVERSION_START_A) { + aptx->CS_TMR_SELA.BIT.rg_csa_tmr_sel = csTrgSrc; + } else if (csTrgCh == APT_ADC_CONVERSION_START_B) { + aptx->CS_TMR_SELB.BIT.rg_csb_tmr_sel = csTrgSrc; + } +} + +/** + * @brief Enable synchronization of ADC trigger scale initial count value. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @retval None. + */ +static inline void DCL_APT_EnableADCTriggerCountSyncInit(APT_RegStruct *aptx, APT_ADCTriggerChannel csTrgCh) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csTrgCh >= APT_ADC_CONVERSION_START_A); + APT_PARAM_CHECK_NO_RET(csTrgCh <= APT_ADC_CONVERSION_START_B); + if (csTrgCh == APT_ADC_CONVERSION_START_A) { + aptx->CS_PRSCA_CFG.BIT.rg_csa_prsc_synen = BASE_CFG_SET; + } else if (csTrgCh == APT_ADC_CONVERSION_START_B) { + aptx->CS_PRSCB_CFG.BIT.rg_csb_prsc_synen = BASE_CFG_SET; + } +} + +/** + * @brief Disable synchronization of ADC trigger scale initial count value. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @retval None. + */ +static inline void DCL_APT_DisableADCTriggerCountSyncInit(APT_RegStruct *aptx, APT_ADCTriggerChannel csTrgCh) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csTrgCh >= APT_ADC_CONVERSION_START_A); + APT_PARAM_CHECK_NO_RET(csTrgCh <= APT_ADC_CONVERSION_START_B); + if (csTrgCh == APT_ADC_CONVERSION_START_A) { + aptx->CS_PRSCA_CFG.BIT.rg_csa_prsc_synen = BASE_CFG_UNSET; + } else if (csTrgCh == APT_ADC_CONVERSION_START_B) { + aptx->CS_PRSCB_CFG.BIT.rg_csb_prsc_synen = BASE_CFG_UNSET; + } +} + +/** + * @brief Set the initial count value of ADC trigger scale. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @param csCntInitVal Initial count value of ADC trigger scale. + * @retval None. + */ +static inline void DCL_APT_SetADCTriggerCountSyncInitVal(APT_RegStruct *aptx, + APT_ADCTriggerChannel csTrgCh, + unsigned short csCntInitVal) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csTrgCh >= APT_ADC_CONVERSION_START_A); + APT_PARAM_CHECK_NO_RET(csTrgCh <= APT_ADC_CONVERSION_START_B); + APT_PARAM_CHECK_NO_RET(csCntInitVal <= ADC_CONVERSION_START_CNT_MAX); + if (csTrgCh == APT_ADC_CONVERSION_START_A) { + aptx->CS_PRSCA_CFG.BIT.rg_csa_prsc_phs = csCntInitVal; + } else if (csTrgCh == APT_ADC_CONVERSION_START_B) { + aptx->CS_PRSCB_CFG.BIT.rg_csb_prsc_phs = csCntInitVal; + } +} + +/** + * @brief Set the count period of ADC trigger scale. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @param csCntPeriod Count period of ADC trigger scale. + * @retval None. + */ +static inline void DCL_APT_SetADCTriggerCountPeriod(APT_RegStruct *aptx, + APT_ADCTriggerChannel csTrgCh, + unsigned short csCntPeriod) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csTrgCh >= APT_ADC_CONVERSION_START_A); + APT_PARAM_CHECK_NO_RET(csTrgCh <= APT_ADC_CONVERSION_START_B); + APT_PARAM_CHECK_NO_RET(csCntPeriod <= ADC_CONVERSION_START_CNT_MAX); + if (csTrgCh == APT_ADC_CONVERSION_START_A) { + aptx->CS_PRSCA_CFG.BIT.rg_csa_prsc_prd = csCntPeriod; + } else if (csTrgCh == APT_ADC_CONVERSION_START_B) { + aptx->CS_PRSCB_CFG.BIT.rg_csb_prsc_prd = csCntPeriod; + } +} + +/** + * @brief Force the count value of ADC trigger scale to increase. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @retval None. + */ +static inline void DCL_APT_ForceADCTriggerCountIncr(APT_RegStruct *aptx, APT_ADCTriggerChannel csTrgCh) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csTrgCh >= APT_ADC_CONVERSION_START_A); + APT_PARAM_CHECK_NO_RET(csTrgCh <= APT_ADC_CONVERSION_START_B); + if (csTrgCh == APT_ADC_CONVERSION_START_A) { + aptx->CS_PRSCA_CFG.BIT.rg_csa_prsc_frc = BASE_CFG_SET; + } else if (csTrgCh == APT_ADC_CONVERSION_START_B) { + aptx->CS_PRSCB_CFG.BIT.rg_csb_prsc_frc = BASE_CFG_SET; + } +} + +/** + * @brief Get the flag of ADC trigger. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @retval bool: true, false. + */ +static inline bool DCL_APT_GetADCTriggerFlag(APT_RegStruct *aptx, APT_ADCTriggerChannel csTrgCh) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_WITH_RET(csTrgCh >= APT_ADC_CONVERSION_START_A, false); + APT_PARAM_CHECK_WITH_RET(csTrgCh <= APT_ADC_CONVERSION_START_B, false); + return ((aptx->CS_FLAG.reg & csTrgCh) == csTrgCh); +} + +/** + * @brief Clear the flag of ADC trigger. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @retval None. + */ +static inline void DCL_APT_ClearADCTriggerFlag(APT_RegStruct *aptx, APT_ADCTriggerChannel csTrgCh) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csTrgCh >= APT_ADC_CONVERSION_START_A); + APT_PARAM_CHECK_NO_RET(csTrgCh <= APT_ADC_CONVERSION_START_B); + unsigned int trgFlgOffset = 16; /* Offset of ADC trigget flag clear */ + aptx->CS_FLAG.reg |= (csTrgCh << trgFlgOffset); +} + +/** + * @brief Configure the DMA request of ADC trigger. + * @param aptx APT register base address. + * @param csDMAReqSrc DMA request source of ADC Converter Start submodule. + * @param csDMAType DMA request type of ADC Converter Start submodule. + * @retval None. + */ +static inline void DCL_APT_SetADCTriggerDMAReq(APT_RegStruct *aptx, + APT_ADCTrgDMAReqSrc csDMAReqSrc, + APT_ADCTrgDMAReqType csDMAType) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csDMAReqSrc >= APT_CS_DMA_REQ_SRC_DISABLE); + APT_PARAM_CHECK_NO_RET(csDMAReqSrc <= APT_CS_DMA_REQ_SRC_CHANNEL_B); + APT_PARAM_CHECK_NO_RET(csDMAType <= APT_CS_DMA_SINGLE_REQUEST); + APT_PARAM_CHECK_NO_RET(csDMAType <= APT_CS_DMA_BURST_REQUEST); + aptx->CS_DMA.reg &= (~(0b11 << csDMAType)); + aptx->CS_DMA.reg |= (csDMAReqSrc << csDMAType); +} + +/* --------------------------------------------------------------------------------------------- */ +/* Event Management (EM) submodule Direct Configuration Layer functions ------------------------ */ +/* --------------------------------------------------------------------------------------------- */ +/** + * @brief Set the polarity of GPIO/system event. + * @param aptx APT register base address. + * @param ioSysEvt GPIO or system event. + * @param ioSysEvtPolar Event polarity. + * @retval None. + */ +static inline void DCL_APT_SetIOSysEventPolarity(APT_RegStruct *aptx, + APT_EMIOSysEvent ioSysEvt, + APT_EMEventPolarity ioSysEvtPolar) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ioSysEvt >= APT_EM_GPIO_EVENT_1); + APT_PARAM_CHECK_NO_RET(ioSysEvt <= APT_EM_SYSTEM_EVENT_3); + APT_PARAM_CHECK_NO_RET(ioSysEvtPolar >= APT_EM_EVENT_POLARITY_NOT_INVERT); + APT_PARAM_CHECK_NO_RET(ioSysEvtPolar <= APT_EM_EVENT_POLARITY_FORCE_HIGH); + aptx->EM_EVTIO_PSEL.reg &= (~(0b11 << ioSysEvt)); + aptx->EM_EVTIO_PSEL.reg |= (ioSysEvtPolar << ioSysEvt); +} + +/** + * @brief Set the polarity of multiplexing event. + * @param aptx APT register base address. + * @param mpEvt Multiplexing event. + * @param mpEvtPolar Event polarity. + * @retval None. + */ +static inline void DCL_APT_SetMpEventPolarity(APT_RegStruct *aptx, + APT_EMMuxEvent mpEvt, + APT_EMEventPolarity mpEvtPolar) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(mpEvt >= APT_EM_MP_EVENT_1); + APT_PARAM_CHECK_NO_RET(mpEvt <= APT_EM_MP_EVENT_6); + APT_PARAM_CHECK_NO_RET(mpEvtPolar >= APT_EM_EVENT_POLARITY_NOT_INVERT); + APT_PARAM_CHECK_NO_RET(mpEvtPolar <= APT_EM_EVENT_POLARITY_FORCE_HIGH); + aptx->EM_EVTMP_PSEL.reg &= (~(0b11 << mpEvt)); + aptx->EM_EVTMP_PSEL.reg |= (mpEvtPolar << mpEvt); +} + +/** + * @brief When the logicial OR result of GPIO events and MUX events is selected as the source of EM group event, + * this function is called to enable which events can participate in the logical OR operation. + * @param aptx APT register base address. + * @param emGroup The group of Event Management, which can be APT_EM_MODULE_A or APT_EM_MODULE_B. + * Each EM group has 2 events. All the 4 group events are enumerated in APT_EMGroupEvent. + * @param event1OREn The logical OR operation source of group event 1. + * @param event2OREn The logical OR operation source of group event 2. + * event1OREn and event2ORE are the logical OR of some valid values. + * Each valid values indicates that the corresponding event is enabled to participate in the + * logical OR operation of EM group event source. These valid values are: + * APT_EM_OR_EN_GPIO_EVENT_1 - GPIO event 1 is enabled + * APT_EM_OR_EN_GPIO_EVENT_2 - GPIO event 2 is enabled + * APT_EM_OR_EN_GPIO_EVENT_3 - GPIO event 3 is enabled + * APT_EM_OR_EN_MUX_EVENT_1 - MUX event 1 is enabled + * APT_EM_OR_EN_MUX_EVENT_2 - MUX event 2 is enabled + * APT_EM_OR_EN_MUX_EVENT_3 - MUX event 3 is enabled + * APT_EM_OR_EN_MUX_EVENT_4 - MUX event 4 is enabled + * APT_EM_OR_EN_MUX_EVENT_5 - MUX event 5 is enabled + * APT_EM_OR_EN_MUX_EVENT_6 - MUX event 6 is enabled + * @retval None. + */ +static inline void DCL_APT_SetEMEventOR(APT_RegStruct *aptx, + APT_EMGroup emGroup, + unsigned short event1OREn, + unsigned short event2OREn) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(emGroup >= APT_EM_MODULE_A); + APT_PARAM_CHECK_NO_RET(emGroup <= APT_EM_MODULE_B); + if (emGroup == APT_EM_MODULE_A) { + aptx->EM_AOR_EN.BIT.rg_em_a1_oren = event1OREn; + aptx->EM_AOR_EN.BIT.rg_em_a2_oren = event2OREn; + } else if (emGroup == APT_EM_MODULE_B) { + aptx->EM_BOR_EN.BIT.rg_em_b1_oren = event1OREn; + aptx->EM_BOR_EN.BIT.rg_em_b2_oren = event2OREn; + } +} + +/** + * @brief Select the combine event source of GRP_A1, GRP_A2, GRP_B1, GRP_B2. + * @param aptx APT register base address. + * @param evtGroup Combine event source group. + * @param combineEvtSrc Combine event source. + * @retval None. + */ +static inline void DCL_APT_SetCombineGroupSrc(APT_RegStruct *aptx, + APT_EMCombineEvtSrcGrp evtGroup, + APT_EMCombineEvtSrc combineEvtSrc) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(evtGroup >= APT_EM_COMBINE_SRC_GRP_A1); + APT_PARAM_CHECK_NO_RET(evtGroup <= APT_EM_COMBINE_SRC_GRP_B2); + APT_PARAM_CHECK_NO_RET(combineEvtSrc >= APT_EM_COMBINE_SRC_EVT_1); + APT_PARAM_CHECK_NO_RET(combineEvtSrc <= APT_EM_COMBINE_SRC_ALL_EVENT_OR); + unsigned int grpEvtFieldWidth = 4; /* Bit field width of combine event group input source setting */ + aptx->EM_MRG_SEL.reg &= (~(0b1111 << (evtGroup * grpEvtFieldWidth))); + aptx->EM_MRG_SEL.reg |= (combineEvtSrc << (evtGroup * grpEvtFieldWidth)); +} + +/** + * @brief Select Combine Mode + * @param aptx APT register base address. + * @param cmbEvt Combine event. + * @param cmbMode Combine mode. + * @retval None. + */ +static inline void DCL_APT_SetCombineEventSrc(APT_RegStruct *aptx, + APT_EMCombineEvent cmbEvt, + APT_EMCombineEvtMode cmbMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(cmbEvt >= APT_EM_COMBINE_EVENT_A1); + APT_PARAM_CHECK_NO_RET(cmbEvt <= APT_EM_COMBINE_EVENT_B2); + APT_PARAM_CHECK_NO_RET(cmbMode >= APT_EM_COMBINE_LOW_LEVEL); + APT_PARAM_CHECK_NO_RET(cmbMode <= APT_EM_COMBINE_EVT2); + unsigned int cmbModeOffset = 16; /* Offset of combine mode */ + unsigned int cmbModeFieldWidth = 4; /* Bit field width of combine mode */ + aptx->EM_MRG_SEL.reg &= (~(0b111 << (cmbModeOffset + cmbEvt * cmbModeFieldWidth))); + aptx->EM_MRG_SEL.reg |= (cmbMode << (cmbModeOffset + cmbEvt * cmbModeFieldWidth)); +} + +/** + * @brief Select the source of Event Management submodule filter event. + * @param aptx APT register base address. + * @param cmbEvt Combine event. + * @retval None. + */ +static inline void DCL_APT_SelectFilterEventInput(APT_RegStruct *aptx, APT_EMCombineEvent cmbEvt) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(cmbEvt >= APT_EM_COMBINE_EVENT_A1); + APT_PARAM_CHECK_NO_RET(cmbEvt <= APT_EM_COMBINE_EVENT_B2); + aptx->EM_OUT_SEL.BIT.rg_evtfilt_sel = cmbEvt; +} + +/** + * @brief Set the output type of combine event. + * @param aptx APT register base address. + * @param cmbEvt Combine event. + * @param filter Whether the output of combine event is filtered. + * @retval None. + */ +static inline void DCL_APT_SetCombineEventOut(APT_RegStruct *aptx, + APT_EMCombineEvent cmbEvt, + APT_EMCombineEventOut filter) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(cmbEvt >= APT_EM_COMBINE_EVENT_A1); + APT_PARAM_CHECK_NO_RET(cmbEvt <= APT_EM_COMBINE_EVENT_B2); + APT_PARAM_CHECK_NO_RET(filter >= APT_EM_COMBINE_EVENT_OUT_ORIG_SIGNAL); + APT_PARAM_CHECK_NO_RET(filter <= APT_EM_COMBINE_EVENT_OUT_FILT_SIGNAL); + aptx->EM_OUT_SEL.reg &= (~(0b1 << cmbEvt)); + aptx->EM_OUT_SEL.reg |= (filter << cmbEvt); +} + +/** + * @brief Select the sync-in source of slave APT module. + * @param aptx APT register base address. + * @param syncInSrc Sync-in source of slave APT module. + * @retval None. + */ +static inline void DCL_APT_SelectSyncInPulseSrc(APT_RegStruct *aptx, APT_SyncInSrc syncInSrc) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(syncInSrc >= APT_SYNCIN_SRC_APT0_SYNCOUT); + APT_PARAM_CHECK_NO_RET(syncInSrc <= APT_SYNCIN_SRC_DISABLE); + aptx->SYNI_CFG.BIT.rg_syni_sel = syncInSrc; +} + +/** + * @brief Get the flag of sync-in pulse. + * @param aptx APT register base address. + * @retval bool: true, false. + */ +static inline bool DCL_APT_GetSyncInPulseFlag(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->SYNI_CFG.BIT.ro_syni_flag); +} + +/** + * @brief Clear the flag of sync-in pulse. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_ClearSyncInPulseFlag(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->SYNI_CFG.BIT.rg_syni_clr = BASE_CFG_SET; +} + +/** + * @brief Select the synchronization source of the time-base counter. + * @param aptx APT register base address. + * @param cntrSyncSrc The selection of synchronization source for the time-base counter. + * A logical OR of valid values can be passed as the cntrSyncSrc parameter. + * Valid values for cntrSyncSrc are: + * APT_CNTR_SYNC_SRC_COMBINE_EVENT_A1 - Enable combine event A1 as the counter synchronization source. + * APT_CNTR_SYNC_SRC_COMBINE_EVENT_B1 - Enable combine event B1 as the counter synchronization source. + * APT_CNTR_SYNC_SRC_SYNCIN - Enable Sync-In source as the counter synchronization source. + * @retval None. + */ +static inline void DCL_APT_SetTimeBaseCounterSyncSrc(APT_RegStruct *aptx, unsigned short cntrSyncSrc) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(cntrSyncSrc <= CNTR_SYNC_SOURCE_MAX); + aptx->SYNCNT_CFG.reg = cntrSyncSrc; +} + +/** + * @brief Select the source of synchronization out pulse. + * @param aptx APT register base address. + * @param syncOutSrc The source of synchronization out pulse. + * A logical OR of valid values can be passed as the syncOutSrc parameter. + * Valid values for syncOutSrc are: + * APT_SYNC_OUT_ON_CNTR_ZERO - Generate a sync out pulse when counter equals zero. + * APT_SYNC_OUT_ON_CNTR_PERIOD - Generate a sync out pulse when counter equals period. + * APT_SYNC_OUT_ON_COMBINE_EVENT_A1 - Generate a sync out pulse when combine event A1 happens. + * APT_SYNC_OUT_ON_COMBINE_EVENT_B1 - Generate a sync out pulse when combine event B1 happens. + * APT_SYNC_OUT_ON_CNTR_CMPB - Generate a sync out pulse when counter equals CMPB. + * APT_SYNC_OUT_ON_CNTR_CMPC - Generate a sync out pulse when counter equals CMPC. + * APT_SYNC_OUT_ON_CNTR_CMPD - Generate a sync out pulse when counter equals CMPD. + * @retval None. + */ +static inline void DCL_APT_SetSyncOutPulseSrc(APT_RegStruct *aptx, unsigned short syncOutSrc) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(syncOutSrc <= SYNC_OUT_SOURCE_MAX); + aptx->SYNO_CFG.reg &= (~(0xFF << 0)); + aptx->SYNO_CFG.reg |= (syncOutSrc << 0); +} + +/** + * @brief Set synchronization mode of master APT module. + * @param aptx APT register base address. + * @param syncOutMode Synchronization mode of master APT module. + * @retval None. + */ +static inline void DCL_APT_SetSyncOutMode(APT_RegStruct *aptx, APT_SyncOutMode syncOutMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(syncOutMode >= APT_SYNCOUT_ONE_SHOT_MODE); + APT_PARAM_CHECK_NO_RET(syncOutMode <= APT_SYNCOUT_MULTIPLE_MODE); + aptx->SYNO_CFG.BIT.rg_mode_syno = syncOutMode; +} + +/** + * @brief Select the latch source of one-shot sync-out mode. + * @param aptx APT register base address. + * @param latSetSel Latch source of one-shot sync-out mode. + * @retval None. + */ +static inline void DCL_APT_SelectSyncOutOneShotLatch(APT_RegStruct *aptx, APT_SyncOutLatSetSel latSetSel) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(latSetSel >= APT_SYNCOUT_LATCH_SET_ON_SW_FORCE); + APT_PARAM_CHECK_NO_RET(latSetSel <= APT_SYNCOUT_LATCH_SET_ON_GLB_LOAD); + aptx->SYNO_CFG.BIT.rg_latset_sel = latSetSel; +} + +/** + * @brief When in one-shot sync out mode and rg_latset_otsyn is selected as the latch set condition, + * this function is called to turn the one-shot latch condition ON. + * Upon occurrence of a chosen sync out source event, a sync out pulse is generated and the latch + * will be cleared. Hence writing 1 to rg_latset_otsyn will allow a sync out event to pass through + * and block other sync out source event. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_SetSyncOutOneShotLatch(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->SYNO_CFG.BIT.rg_latset_otsyn = BASE_CFG_SET; +} + +/** + * @brief Select the pulse that causes global buffer load. + * @param aptx APT register base address. + * @param glbLoadEvt The pulse that causes global buffer load. + * A logical OR of valid values can be passed as the syncOutSrc parameter. + * Valid values for gloLoadTrg are: + * APT_GLB_LOAD_ON_CNTR_ZERO - Global buffer load when counter equals zero. + * APT_GLB_LOAD_ON_CNTR_PERIOD - Global buffer load when counter equals period. + * APT_GLB_LOAD_ON_CNTR_SYNC - Global buffer load when counter sync is effective. + * @retval None. + */ +static inline void DCL_APT_SetGlobalLoadEvent(APT_RegStruct *aptx, unsigned short glbLoadEvt) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->GLB_LOAD.reg &= (~(0b111 << 0)); + aptx->GLB_LOAD.reg |= (glbLoadEvt << 0); +} + +/** + * @brief Set the prescale value of multiple global buffer load mode. + * @param aptx APT register base address. + * @param gldCntPeriod Prescale value of multiple global buffer load mode. + * @retval None. + */ +static inline void DCL_APT_SetGlobalLoadPrescale(APT_RegStruct *aptx, unsigned short gldCntPeriod) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(gldCntPeriod <= GLOBAL_LOAD_CNT_MAX); + aptx->GLB_LOAD.BIT.rg_gld_prsc_prd = gldCntPeriod; +} + +/** + * @brief Set the global buffer load mode. + * @param aptx APT register base address. + * @param glbLoadMode Global buffer load mode. + * @retval None. + */ +static inline void DCL_APT_SetGlobalLoadMode(APT_RegStruct *aptx, APT_GlobalLoadMode glbLoadMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(glbLoadMode >= APT_GLB_LOAD_ONE_SHOT_MODE); + APT_PARAM_CHECK_NO_RET(glbLoadMode <= APT_GLB_LOAD_MULTIPLE_MODE); + aptx->GLB_LOAD.BIT.rg_mode_gld = glbLoadMode; +} + +/** + * @brief When in one-shot global buffer load mode, this function is called to turn the one-shot latch condition ON. + * Upon occurrence of a chosen global buffer load event, the registers that is set to global buffer load mode + * will load the buffer, and the one-shot latch will be cleared. Hence writing 1 to rg_latset_otgld will + * allow a global buffer load event to pass through and block other global buffer load event. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_SetGlobalLoadOneShotLatch(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->GLB_LOAD.BIT.rg_latset_otgld = BASE_CFG_SET; +} + +/** + * @brief Get buffer status of the registers that enable buffer load. + * @param aptx The base address of APT module. + * @param regBuf The buffer of the registers that enable buffer load. + * @retval true: The register buffer is full. + * @retval false: The register buffer is not full. + */ +static inline bool DCL_APT_GetRegBufferStatus(APT_RegStruct *aptx, APT_RegBuffer regBuf) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_WITH_RET(regBuf <= APT_REG_BUFFER_DG_CFG, false); + return ((aptx->LOAD_STS.reg & regBuf) == regBuf); +} + +/** + * @brief Generate a synchronization force event. + * @param aptx The base address of APT module. + * @param frcEvt Synchronization force event. + * @retval None. + */ +static inline void DCL_APT_ForceEvent(APT_RegStruct *aptx, APT_ForceEvtType frcEvt) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(frcEvt <= APT_FORCE_EVENT_PWM_ACTION_BUF_LOAD); + aptx->SYN_FRC.reg |= frcEvt; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_APT_IP_H */ diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/apt/src/apt.c b/vendor/xinlingyu_92_3061M/Project/drivers/apt/src/apt.c new file mode 100644 index 0000000000000000000000000000000000000000..e0ac4efddc38afd1eeffba63f1cc088dac1eb659 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/apt/src/apt.c @@ -0,0 +1,1432 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file apt.c + * @author MCU Driver Team + * @brief APT module driver. + * @details This file provides firmware functions to manage the following functionalities of APT module. + * + Initialization and de-initialization functions + * + APT module synchronization functions. + * + PWM waveform configuration and ADC trigger time configuration functions. + * + Interrupt callback function and user registration function + */ + +#include "apt.h" +#include "crg.h" +#define MAX_DUTY 100 +#define ALL_EVT_INT_FLAGS 0xf770000U +#define RERF 4 +/** + * @brief The parameters of PWM waveform. + */ +typedef struct { + APT_PWMAction leftEdgeActA; /**< Action on the left edge of PWM channel A. */ + APT_PWMAction rightEdgeActA; /**< Action on the right edge of PWM channel A. */ + APT_PWMAction leftEdgeActB; /**< Action on the left edge of PWM channel B. */ + APT_PWMAction rightEdgeActB; /**< Action on the right edge of PWM channel B. */ + APT_REDInput redInput; /**< Input source of Dead-Band rising edge delay counter. */ + APT_REDOutMode redOutMode; /**< Output mode of Dead-Band rising edge delay counter. */ + APT_FEDInput fedInput; /**< Input source of Dead-Band falling edge delay counter. */ + APT_FEDOutMode fedOutMode; /**< Output mode of Dead-Band falling edge delay counter. */ +} APT_WaveformPara; + +/** + * @brief Initialize the time-base counter of APT module. + * @param aptHandle APT module handle. + * @retval None. + */ +static void APT_TimeBaseInit(APT_Handle *aptHandle) +{ + aptHandle->baseAddress->TC_MODE.BIT.rg_cnt_mode = aptHandle->waveform.cntMode; + aptHandle->baseAddress->TC_MODE.BIT.rg_div_fac = aptHandle->waveform.dividerFactor; + /* Disable buffer mode of TC_PRD */ + aptHandle->baseAddress->TC_BUF_EN.reg &= (~(0b11 << 0)); + aptHandle->baseAddress->TC_PRD.BIT.rg_cnt_prd = aptHandle->waveform.timerPeriod; + /* Set the override value of divier and timebase counter */ + aptHandle->baseAddress->TC_OVRID.BIT.rg_cnt_ovrid = aptHandle->waveform.cntInitVal; + aptHandle->baseAddress->TC_OVRID.BIT.rg_cnt_ovrid_en = 1; +} + +/** + * @brief Initialize the count compare points for PWM waveform generation. + * @param aptHandle APT module handle. + * @retval None. + */ +static void APT_SetPWMCompareVal(APT_Handle *aptHandle) +{ + /* Configure the compare point along the left and right edges of PWM waveform */ + TC_REFC_REG tmpC; + TC_REFD_REG tmpD; + /* Set the value of the active register of CMPC and CMPD */ + tmpC = aptHandle->baseAddress->TC_REFC; + tmpC.BIT.rg_cnt_refc = aptHandle->waveform.cntCmpLeftEdge; + aptHandle->baseAddress->TC_REFC = tmpC; + tmpD = aptHandle->baseAddress->TC_REFD; + tmpD.BIT.rg_cnt_refd = aptHandle->waveform.cntCmpRightEdge; + aptHandle->baseAddress->TC_REFD = tmpD; + /* Set the buffer load mode of CMPC and CMPD */ + if (aptHandle->waveform.cntCmpLoadMode == APT_BUFFER_DISABLE) { + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refc_buf_en = 0; + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refd_buf_en = 0; + } else { + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refc_buf_en = 1; + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refd_buf_en = 1; + unsigned int gldLdEn = (aptHandle->waveform.cntCmpLoadMode == APT_BUFFER_GLOBAL_LOAD) ? 1 : 0; + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refc_gld_en = gldLdEn; + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refd_gld_en = gldLdEn; + /* Set buffer load event */ + unsigned int refBufField = 8; /* reference buffer field */ + aptHandle->baseAddress->TC_REF_LOAD.reg &= (~(0x1F << (APT_COMPARE_REFERENCE_C * refBufField))); + aptHandle->baseAddress->TC_REF_LOAD.reg &= (~(0x1F << (APT_COMPARE_REFERENCE_D * refBufField))); + aptHandle->baseAddress->TC_REF_LOAD.reg |= + (aptHandle->waveform.cntCmpLoadEvt << (APT_COMPARE_REFERENCE_C * refBufField)); + aptHandle->baseAddress->TC_REF_LOAD.reg |= + (aptHandle->waveform.cntCmpLoadEvt << (APT_COMPARE_REFERENCE_D * refBufField)); + /* Set the value of the buffer register of CMPC and CMPD */ + tmpC = aptHandle->baseAddress->TC_REFC; /* read register */ + tmpC.BIT.rg_cnt_refc = aptHandle->waveform.cntCmpLeftEdge; + aptHandle->baseAddress->TC_REFC = tmpC; /* write back changed data back to register */ + tmpD = aptHandle->baseAddress->TC_REFD; /* read register */ + tmpD.BIT.rg_cnt_refd = aptHandle->waveform.cntCmpRightEdge; + aptHandle->baseAddress->TC_REFD = tmpD; /* write back changed data back to register */ + } +} + +/** + * @brief Configure the basic PWM A waveform output according to the waveform parameters. + * @param aptHandle APT module handle. + * @param wavePara PWM waveform parameter. + * @retval None. + */ +static void APT_SetOutputABasicType(APT_Handle *aptHandle, const APT_WaveformPara *wavePara) +{ + switch (aptHandle->waveform.cntMode) { + case APT_COUNT_MODE_UP: + aptHandle->baseAddress->PG_ACT_A.BIT.rg_pga_act_refc_inc = wavePara->leftEdgeActA; + aptHandle->baseAddress->PG_ACT_A.BIT.rg_pga_act_refd_inc = wavePara->rightEdgeActA; + break; + case APT_COUNT_MODE_DOWN: + aptHandle->baseAddress->PG_ACT_A.BIT.rg_pga_act_refc_dec = wavePara->rightEdgeActA; + aptHandle->baseAddress->PG_ACT_A.BIT.rg_pga_act_refd_dec = wavePara->leftEdgeActA; + break; + case APT_COUNT_MODE_UP_DOWN: + aptHandle->baseAddress->PG_ACT_A.BIT.rg_pga_act_refc_inc = wavePara->leftEdgeActA; + aptHandle->baseAddress->PG_ACT_A.BIT.rg_pga_act_refd_dec = wavePara->rightEdgeActA; + break; + default: + break; + } + return; +} + +/** + * @brief Configure the basic PWM B waveform output according to the waveform parameters. + * @param aptHandle APT module handle. + * @param wavePara PWM waveform parameter. + * @retval None. + */ +static void APT_SetOutputBBasicType(APT_Handle *aptHandle, const APT_WaveformPara *wavePara) +{ + switch (aptHandle->waveform.cntMode) { + case APT_COUNT_MODE_UP: + aptHandle->baseAddress->PG_ACT_B.BIT.rg_pgb_act_refc_inc = wavePara->leftEdgeActB; + aptHandle->baseAddress->PG_ACT_B.BIT.rg_pgb_act_refd_inc = wavePara->rightEdgeActB; + break; + case APT_COUNT_MODE_DOWN: + aptHandle->baseAddress->PG_ACT_B.BIT.rg_pgb_act_refc_dec = wavePara->rightEdgeActB; + aptHandle->baseAddress->PG_ACT_B.BIT.rg_pgb_act_refd_dec = wavePara->leftEdgeActB; + break; + case APT_COUNT_MODE_UP_DOWN: + aptHandle->baseAddress->PG_ACT_B.BIT.rg_pgb_act_refc_inc = wavePara->leftEdgeActB; + aptHandle->baseAddress->PG_ACT_B.BIT.rg_pgb_act_refd_dec = wavePara->rightEdgeActB; + break; + default: + break; + } + return; +} + +/** + * @brief Configure the basic PWM waveform output according to the waveform parameters. + * @param aptHandle APT module handle. + * @param wavePara PWM waveform parameter. + * @retval None. + */ +static void APT_SetPWMBasicType(APT_Handle *aptHandle, const APT_WaveformPara *wavePara) +{ + /* Configure PWM waveform of PWM channel A */ + if (aptHandle->waveform.chAOutType == APT_PWM_OUT_BASIC_TYPE) { + APT_SetOutputABasicType(aptHandle, wavePara); + } + /* Configure PWM waveform of PWM channel B */ + if (aptHandle->waveform.chBOutType == APT_PWM_OUT_BASIC_TYPE) { + APT_SetOutputBBasicType(aptHandle, wavePara); + } + /* Configure dead band of PWM channel A and channel B */ + if (aptHandle->waveform.chAOutType == APT_PWM_OUT_BASIC_TYPE && + aptHandle->waveform.chBOutType == APT_PWM_OUT_BASIC_TYPE) { + aptHandle->baseAddress->DG_CFG.BIT.rg_dg_red_isel = wavePara->redInput; + aptHandle->baseAddress->DG_CFG.BIT.rg_dg_red_osel = wavePara->redOutMode; + aptHandle->baseAddress->DG_RED.BIT.rg_dg_red = aptHandle->waveform.deadBandCnt; + aptHandle->baseAddress->DG_CFG.BIT.rg_dg_fed_isel = wavePara->fedInput; + aptHandle->baseAddress->DG_CFG.BIT.rg_dg_fed_osel = wavePara->fedOutMode; + aptHandle->baseAddress->DG_FED.BIT.rg_dg_fed = aptHandle->waveform.deadBandCnt; + } +} + +/** + * @brief Set the actual outputs of PWM channelA and channelB when basic PWM waveform type is not used. + * @param aptHandle APT module handle. + * @retval None. + */ +static void APT_SetContWaveform(APT_Handle *aptHandle) +{ + if (aptHandle->waveform.chAOutType != APT_PWM_OUT_BASIC_TYPE) { + unsigned int contActA = (aptHandle->waveform.chAOutType == APT_PWM_OUT_ALWAYS_LOW) ? 0b01 : 0b10; + aptHandle->baseAddress->PG_ACT_A.BIT.rg_pga_act_zro = contActA; + } + if (aptHandle->waveform.chBOutType != APT_PWM_OUT_BASIC_TYPE) { + unsigned int contActB = (aptHandle->waveform.chBOutType == APT_PWM_OUT_ALWAYS_LOW) ? 0b01 : 0b10; + aptHandle->baseAddress->PG_ACT_B.BIT.rg_pgb_act_zro = contActB; + } +} + +/** + * @brief Initialize the PWM waveform parameters according to the selected PWM basic type. + * @param aptHandle APT module handle. + * @retval None. + */ +static void APT_SetPWMWaveform(APT_Handle *aptHandle) +{ + APT_SetContWaveform(aptHandle); + /* Configure the basic type of PWM waveform */ + APT_WaveformPara wavePara = {0, 0, 0, 0, 0, 0, 0, 0}; + switch (aptHandle->waveform.basicType) { + case APT_PWM_BASIC_A_HIGH_B_LOW: + wavePara.leftEdgeActA = APT_PWM_ACTION_HIGH; + wavePara.rightEdgeActA = APT_PWM_ACTION_LOW; + wavePara.leftEdgeActB = APT_PWM_ACTION_HIGH; + wavePara.rightEdgeActB = APT_PWM_ACTION_LOW; + wavePara.redInput = APT_DB_RED_INPUT_PWM_A; + wavePara.redOutMode = APT_DB_RED_OUTPUT_NOT_INVERT; + wavePara.fedInput = APT_DB_FED_INPUT_PWM_B; + wavePara.fedOutMode = APT_DB_FED_OUTPUT_INVERT; + break; + case APT_PWM_BASIC_A_LOW_B_HIGH: + wavePara.leftEdgeActA = APT_PWM_ACTION_LOW; + wavePara.rightEdgeActA = APT_PWM_ACTION_HIGH; + wavePara.leftEdgeActB = APT_PWM_ACTION_LOW; + wavePara.rightEdgeActB = APT_PWM_ACTION_HIGH; + wavePara.fedInput = APT_DB_FED_INPUT_PWM_A; + wavePara.fedOutMode = APT_DB_FED_OUTPUT_INVERT; + wavePara.redInput = APT_DB_RED_INPUT_PWM_B; + wavePara.redOutMode = APT_DB_RED_OUTPUT_NOT_INVERT; + break; + case APT_PWM_BASIC_A_HIGH_B_HIGH: + wavePara.leftEdgeActA = APT_PWM_ACTION_HIGH; + wavePara.rightEdgeActA = APT_PWM_ACTION_LOW; + wavePara.leftEdgeActB = APT_PWM_ACTION_HIGH; + wavePara.rightEdgeActB = APT_PWM_ACTION_LOW; + wavePara.redInput = APT_DB_RED_INPUT_PWM_A; + wavePara.redOutMode = APT_DB_RED_OUTPUT_NOT_INVERT; + wavePara.fedInput = APT_DB_FED_INPUT_PWM_B; + wavePara.fedOutMode = APT_DB_FED_OUTPUT_NOT_INVERT; + break; + case APT_PWM_BASIC_A_LOW_B_LOW: + wavePara.leftEdgeActA = APT_PWM_ACTION_LOW; + wavePara.rightEdgeActA = APT_PWM_ACTION_HIGH; + wavePara.leftEdgeActB = APT_PWM_ACTION_LOW; + wavePara.rightEdgeActB = APT_PWM_ACTION_HIGH; + wavePara.fedInput = APT_DB_FED_INPUT_PWM_A; + wavePara.fedOutMode = APT_DB_FED_OUTPUT_NOT_INVERT; + wavePara.redInput = APT_DB_RED_INPUT_PWM_B; + wavePara.redOutMode = APT_DB_RED_OUTPUT_NOT_INVERT; + break; + default: + break; + } + APT_SetPWMBasicType(aptHandle, &wavePara); +} + +/** + * @brief Initialize the count compare points for triggering ADC sampling. + * @param aptHandle APT module handle. + * @retval None. + */ +static void APT_SetADCTrgCompareVal(APT_Handle *aptHandle) +{ + /* Configure the count compare point for triggering SOCA and SOCB */ + TC_REFA_REG tmpA; + TC_REFB_REG tmpB; + /* Set the value of active register for CMPA and CMPB */ + tmpA = aptHandle->baseAddress->TC_REFA; /* read register */ + tmpA.BIT.rg_cnt_refa = aptHandle->adcTrg.cntCmpSOCA; + aptHandle->baseAddress->TC_REFA = tmpA; /* write back changed data to register */ + tmpB = aptHandle->baseAddress->TC_REFB; + tmpB.BIT.rg_cnt_refb = aptHandle->adcTrg.cntCmpSOCB; + aptHandle->baseAddress->TC_REFB = tmpB; + /* Set the buffer load mode of CMPA and CMPB */ + if (aptHandle->adcTrg.cntCmpLoadMode == APT_BUFFER_DISABLE) { + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refa_buf_en = 0; /* disable buffer function */ + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refb_buf_en = 0; /* disable buffer function */ + } else { + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refa_buf_en = 1; + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refb_buf_en = 1; + /* Set global buffer */ + unsigned int gldLdEn = (aptHandle->adcTrg.cntCmpLoadMode == APT_BUFFER_GLOBAL_LOAD) ? 1 : 0; + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refa_gld_en = gldLdEn; + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refb_gld_en = gldLdEn; + /* Set buffer load event */ + unsigned int refBufField = 8; + aptHandle->baseAddress->TC_REF_LOAD.reg &= (~(0x1F << (APT_COMPARE_REFERENCE_A * refBufField))); + aptHandle->baseAddress->TC_REF_LOAD.reg &= (~(0x1F << (APT_COMPARE_REFERENCE_B * refBufField))); + aptHandle->baseAddress->TC_REF_LOAD.reg |= + (aptHandle->adcTrg.cntCmpLoadEvt << (APT_COMPARE_REFERENCE_A * refBufField)); + aptHandle->baseAddress->TC_REF_LOAD.reg |= + (aptHandle->adcTrg.cntCmpLoadEvt << (APT_COMPARE_REFERENCE_B * refBufField)); + /* Set the value of buffer register for CMPA and CMPB */ + tmpA = aptHandle->baseAddress->TC_REFA; + tmpA.BIT.rg_cnt_refa = aptHandle->adcTrg.cntCmpSOCA; + aptHandle->baseAddress->TC_REFA = tmpA; + tmpB = aptHandle->baseAddress->TC_REFB; + tmpB.BIT.rg_cnt_refb = aptHandle->adcTrg.cntCmpSOCB; + aptHandle->baseAddress->TC_REFB = tmpB; + } +} + +/** + * @brief Initialize the ADC trigger function of APT module. + * @param aptHandle APT module handle + * @retval None. + */ +static void APT_SetADCTrigger(APT_Handle *aptHandle) +{ + APT_PARAM_CHECK_NO_RET(aptHandle->adcTrg.trgScaleSOCA <= ADC_CONVERSION_START_CNT_MAX); + APT_PARAM_CHECK_NO_RET(aptHandle->adcTrg.trgScaleSOCB <= ADC_CONVERSION_START_CNT_MAX); + /* Configure ADC trigger source SOCA */ + aptHandle->baseAddress->CS_TMR_SELA.BIT.rg_csa_tmr_sel = aptHandle->adcTrg.trgSrcSOCA; + aptHandle->baseAddress->CS_PRSCA_CFG.BIT.rg_csa_prsc_prd = aptHandle->adcTrg.trgScaleSOCA; + aptHandle->baseAddress->CS_TMR_SELA.BIT.rg_csa_en_cs = aptHandle->adcTrg.trgEnSOCA; + /* Configure ADC trigger source SOCB */ + aptHandle->baseAddress->CS_TMR_SELB.BIT.rg_csb_tmr_sel = aptHandle->adcTrg.trgSrcSOCB; + aptHandle->baseAddress->CS_PRSCB_CFG.BIT.rg_csb_prsc_prd = aptHandle->adcTrg.trgScaleSOCB; + aptHandle->baseAddress->CS_TMR_SELB.BIT.rg_csb_en_cs = aptHandle->adcTrg.trgEnSOCB; +} + +/** + * @brief Initialize the timer interrupt of APT module. + * @param aptHandle APT module handle. + * @retval None. + */ +static void APT_SetTimerInterrupt(APT_Handle *aptHandle) +{ + APT_PARAM_CHECK_NO_RET(aptHandle->tmrInterrupt.tmrInterruptScale <= TIMER_INTERRUPT_CNT_MAX); + aptHandle->baseAddress->INT_TMR_SEL.BIT.rg_int_tmr_sel = aptHandle->tmrInterrupt.tmrInterruptSrc; + aptHandle->baseAddress->INT_PRSC_CFG.BIT.rg_int_prsc_prd = aptHandle->tmrInterrupt.tmrInterruptScale; + aptHandle->baseAddress->INT_TMR_EN.BIT.rg_int_en_tmr = aptHandle->tmrInterrupt.tmrInterruptEn; +} + +/** + * @brief Initialize the APT hardware configuration based on the APT module handle. + * @param aptHandle APT module handle. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_PWMInit(APT_Handle *aptHandle) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + APT_PARAM_CHECK_WITH_RET(aptHandle->waveform.dividerFactor <= DIVIDER_FACTOR_MAX, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->waveform.divInitVal <= aptHandle->waveform.dividerFactor, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->waveform.cntInitVal < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->waveform.cntCmpLeftEdge > 0, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->waveform.cntCmpLeftEdge < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->waveform.cntCmpRightEdge > 0, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->waveform.cntCmpRightEdge < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->adcTrg.cntCmpSOCA >= 0, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->adcTrg.cntCmpSOCA < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->adcTrg.cntCmpSOCB >= 0, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->adcTrg.cntCmpSOCB < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + APT_TimeBaseInit(aptHandle); + APT_SetPWMCompareVal(aptHandle); + APT_SetPWMWaveform(aptHandle); + APT_SetADCTrgCompareVal(aptHandle); + APT_SetADCTrigger(aptHandle); + APT_SetTimerInterrupt(aptHandle); + return BASE_STATUS_OK; +} + +/** + * @brief Deinitialize the APT hardware configuration. + * @param aptHandle APT module handle. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_PWMDeInit(APT_Handle *aptHandle) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + /* CallBack function set null. */ + aptHandle->userCallBack.EvtInterruptCallBack = NULL; + aptHandle->userCallBack.TmrInterruptCallBack = NULL; + /* Reset the Interrupt register. */ + aptHandle->baseAddress->INT_TMR_EN.BIT.rg_int_en_tmr = BASE_CFG_UNSET; + aptHandle->baseAddress->CS_TMR_SELA.BIT.rg_csa_en_cs = BASE_CFG_UNSET; + aptHandle->baseAddress->CS_TMR_SELB.BIT.rg_csb_en_cs = BASE_CFG_UNSET; + /* Reset reference points of APT. */ + aptHandle->baseAddress->TC_BUF_EN.reg = 0x0; + aptHandle->baseAddress->TC_REFA.reg = 0x0; + aptHandle->baseAddress->TC_REFB.reg = 0x0; + aptHandle->baseAddress->TC_REFC.reg = 0x0; + aptHandle->baseAddress->TC_REFD.reg = 0x0; + aptHandle->baseAddress->TC_PRD.BIT.rg_cnt_prd = 0x2710; /* 0x2710: default value */ + aptHandle->baseAddress->PG_ACT_A.reg = 0x0; /* Clear action register. */ + aptHandle->baseAddress->PG_ACT_B.reg = 0x0; + return BASE_STATUS_OK; +} + +/** + * @brief Configure output control protection mode. + * @param aptHandle APT module handle. + * @param protect Output control protection event handle. + * @retval None. + */ +static void APT_SetOutCtrlProtectMode(APT_Handle *aptHandle, APT_OutCtrlProtect *protect) +{ + /* Set output control protect mode */ + unsigned int ocModeOffset = 16; + unsigned int cbcClrOffsetPrd = 16; + if (protect->ocEventMode == APT_OUT_CTRL_ONE_SHOT) { + aptHandle->baseAddress->OC_MODE.reg &= (~(protect->ocEvent << ocModeOffset)); + } else if (protect->ocEventMode == APT_OUT_CTRL_CYCLE_BY_CYBLE) { + aptHandle->baseAddress->OC_MODE.reg |= (protect->ocEvent << ocModeOffset); + if ((protect->cbcClrMode & APT_CLEAR_CBC_ON_CNTR_ZERO) ==APT_CLEAR_CBC_ON_CNTR_ZERO) { + aptHandle->baseAddress->OC_PRD_CLR.reg |= protect->ocEvent; + } + if ((protect->cbcClrMode & APT_CLEAR_CBC_ON_CNTR_PERIOD) == APT_CLEAR_CBC_ON_CNTR_PERIOD) { + aptHandle->baseAddress->OC_PRD_CLR.reg |= (protect->ocEvent << cbcClrOffsetPrd); + } + } +} + +/** + * @brief Output control protection action selection. + * @param aptHandle APT module handle. + * @param ocAction Out control action. + * @param protect Output control protection event handle. + * @param outCtrlEvent output settings. + * @retval None. + */ +static void APT_SetOutCtrlAction(APT_Handle *aptHandle, APT_OutCtrlAction ocAction, APT_OutCtrlEventDir outCtrlEvent) +{ + /* Set output control action when counting up */ + aptHandle->baseAddress->OC_ACT_A.reg &= (~(0b111 << outCtrlEvent)); + aptHandle->baseAddress->OC_ACT_A.reg |= (ocAction << outCtrlEvent); + aptHandle->baseAddress->OC_ACT_B.reg &= (~(0b111 << outCtrlEvent)); + aptHandle->baseAddress->OC_ACT_B.reg |= (ocAction << outCtrlEvent); +} + +/** + * @brief Indicates the configuration of protection actions for different channels(PWMA and PWMB output action). + * @param aptHandle APT module handle. @ref APT_Handle + * @param ocActionA PWMA output action control. @ref APT_OutCtrlAction + * @param ocActionB PWMB output action control. @ref APT_OutCtrlAction + * @param outCtrlEvent Action configuration in different counting directions. @ref APT_OutCtrlEventDir + * @retval None. + */ +static void APT_SetOutCtrlActionEx(APT_Handle *aptHandle, APT_OutCtrlAction ocActionA, APT_OutCtrlAction ocActionB, + APT_OutCtrlEventDir outCtrlEvent) +{ + /* Set output control action when counting up */ + aptHandle->baseAddress->OC_ACT_A.reg &= (~(0b111 << outCtrlEvent)); + aptHandle->baseAddress->OC_ACT_A.reg |= (ocActionA << outCtrlEvent); + aptHandle->baseAddress->OC_ACT_B.reg &= (~(0b111 << outCtrlEvent)); + aptHandle->baseAddress->OC_ACT_B.reg |= (ocActionB << outCtrlEvent); +} + +/** + * @brief Change APT's OC Event to EM Event. + * @param ocEvent OC Event. + * @param emEvent EM Event. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +static BASE_StatusType APT_ChangeOcEventToEmEvent(APT_OutCtrlEvent ocEvent, APT_EMIOSysEvent *emEvent) +{ + APT_ASSERT_PARAM(emEvent != NULL); + switch (ocEvent) { + case APT_OC_GPIO_EVENT_1: + *emEvent = APT_EM_GPIO_EVENT_1; + break; + case APT_OC_GPIO_EVENT_2: + *emEvent = APT_EM_GPIO_EVENT_2; + break; + case APT_OC_GPIO_EVENT_3: + *emEvent = APT_EM_GPIO_EVENT_3; + break; + case APT_OC_SYSTEM_EVENT_1: + *emEvent = APT_EM_SYSTEM_EVENT_1; + break; + case APT_OC_SYSTEM_EVENT_2: + *emEvent = APT_EM_SYSTEM_EVENT_2; + break; + case APT_OC_SYSTEM_EVENT_3: + *emEvent = APT_EM_SYSTEM_EVENT_3; + break; + default: + return BASE_STATUS_ERROR; + } + + return BASE_STATUS_OK; +} + +/** + * @brief Set combine event out control action. + * @param aptHandle APT module handle. + * @param protect Output control protection event handle. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +static BASE_StatusType APT_SetCombieEvtOutCtrl(APT_Handle *aptHandle, APT_OutCtrlProtect *protect) +{ + switch (protect->ocEvent) { + case APT_OC_COMBINE_EVENT_A1: + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_COMBINE_EVENT_A1_UP); + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_COMBINE_EVENT_A1_DOWN); + break; + case APT_OC_COMBINE_EVENT_A2: + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_COMBINE_EVENT_A2_UP); + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_COMBINE_EVENT_A2_DOWN); + break; + case APT_OC_COMBINE_EVENT_B1: + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_COMBINE_EVENT_B1_UP); + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_COMBINE_EVENT_B1_DOWN); + break; + case APT_OC_COMBINE_EVENT_B2: + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_COMBINE_EVENT_B2_UP); + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_COMBINE_EVENT_B2_DOWN); + break; + default: + return BASE_STATUS_ERROR; + } + + return BASE_STATUS_OK; +} + +/** + * @brief Setting emulation mode of APT module. + * @param aptHandle APT module handle. + * @param protect Output control protection event handle. + * @retval None. + */ +static void APT_OcSetEmulation(APT_Handle *aptHandle, APT_OutCtrlProtect *protect) +{ + aptHandle->baseAddress->TC_MODE.BIT.rg_emu_stop = protect->emMode; + if (protect->emMode > APT_EMULATION_NO_STOP) { + aptHandle->baseAddress->OC_MODE.reg |= APT_OC_SYSTEM_EVENT_1; + } +} + +/** + * @brief Initialize the output control protection event of APT module. + * @param aptHandle APT module handle. + * @param protect Output control protection event handle. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_ProtectInit(APT_Handle *aptHandle, APT_OutCtrlProtect *protect) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(protect != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + APT_PARAM_CHECK_WITH_RET(protect->ocEvent >= APT_OC_GPIO_EVENT_1, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(protect->ocEvent <= APT_OC_COMBINE_EVENT_B2, BASE_STATUS_ERROR); + APT_SetOutCtrlProtectMode(aptHandle, protect); + /* Emultion settings */ + APT_OcSetEmulation(aptHandle, protect); + + if ((protect->ocEvent >= APT_OC_COMBINE_EVENT_A1) && (protect->ocEvent <= APT_OC_COMBINE_EVENT_B2)) { + if (APT_SetCombieEvtOutCtrl(aptHandle, protect) == BASE_STATUS_ERROR) { + return BASE_STATUS_ERROR; + } + } else { + /* Set IO event polarity */ + APT_EMIOSysEvent ioSysEvt; + if (APT_ChangeOcEventToEmEvent(protect->ocEvent, &ioSysEvt) == BASE_STATUS_OK) { + aptHandle->baseAddress->EM_EVTIO_PSEL.reg &= (~(0b11 << ioSysEvt)); + aptHandle->baseAddress->EM_EVTIO_PSEL.reg |= (protect->evtPolarity << ioSysEvt); + } + /* Set output control action when counting up */ + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_GPIO_OR_SYSTEM_UP); + /* Set output control action when counting down */ + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_GPIO_OR_SYSTEM_DOWN); + } + if (protect->ocEventEn == BASE_CFG_ENABLE) { + aptHandle->baseAddress->OC_MODE.reg |= (protect->ocEvent); + } else { + aptHandle->baseAddress->OC_MODE.reg &= (~(protect->ocEvent)); + } + if (protect->ocEvtInterruptEn == BASE_CFG_ENABLE) { + aptHandle->baseAddress->INT_EVT_EN.reg |= (protect->ocEvent); + } else { + aptHandle->baseAddress->INT_EVT_EN.reg &= (~(protect->ocEvent)); + } + return BASE_STATUS_OK; +} + +/** + * @brief Setting protect source event filter, only support the same filter value. + * @param filterNum filter cycle number. + * @retval None. + */ +static void APT_SetEMEventFilterEx(unsigned char filterNum) +{ + unsigned int srcEvent; + unsigned int enableOffset = 24; + unsigned int valueShift = 8; + unsigned int maxEventNum = 3; /* every register can config 3 event's filer */ + for (srcEvent = 0; srcEvent < maxEventNum; srcEvent++) { + SYSCTRL1->APT_POE_FILTER.reg |= 0x1 << (enableOffset + srcEvent); + SYSCTRL1->APT_POE_FILTER.reg |= (((unsigned int)filterNum & 0xff) << (valueShift * srcEvent)); + SYSCTRL1->APT_EVTMP_FILTER.reg |= 0x1 << (enableOffset + srcEvent); + SYSCTRL1->APT_EVTMP_FILTER.reg |= (((unsigned int)filterNum & 0xff) << (valueShift * srcEvent)); + } +} + +/** + * @brief Set protect source event polarity. + * @param aptHandle APT module handle. + * @param polarityMask polarity bit mask. + * @retval None. + */ +static void APT_SetProtectSrcEventPolarityEx(APT_Handle *aptHandle, unsigned int polarityMask) +{ + unsigned int curEvent; + unsigned int curPolarity; + unsigned int curMpEventNum; /* System Compare Event Sources */ + unsigned int curIoEventNum; /* I/O Event Source */ + /* Sets the polarity of the trigger source. */ + for (int i = 0; i <= APT_EM_COMBINE_SRC_EVT_MP_6; i++) { + curEvent = i; + curPolarity = (polarityMask >> curEvent) & 0x01; + if (curEvent >= APT_EM_COMBINE_SRC_EVT_MP_1) { + curMpEventNum = (curEvent - APT_EM_COMBINE_SRC_EVT_MP_1) << 1; + /* set ACMP0~2 and EVTMP4~6 event polarity */ + aptHandle->baseAddress->EM_EVTMP_PSEL.reg &= (~(0b11 << curMpEventNum)); + aptHandle->baseAddress->EM_EVTMP_PSEL.reg |= (curPolarity << curMpEventNum); + } else { + /* set IO event polarity */ + curIoEventNum = curEvent << 1; + aptHandle->baseAddress->EM_EVTIO_PSEL.reg &= (~(0b11 << curIoEventNum)); + aptHandle->baseAddress->EM_EVTIO_PSEL.reg |= (curPolarity << curIoEventNum); + } + } +} + +/** + * @brief Configure output control protection mode. + * @param aptHandle APT module handle. + * @param protect Output control protection event handle. + * @retval None. + */ +static void APT_SetSysEventProtectModeEx(APT_Handle *aptHandle, APT_OutCtrlProtectEx *protect) +{ + /* Set output control protect mode */ + unsigned int ocModeOffset = 16; + unsigned int cbcClrOffsetPrd = 16; + if (protect->ocEventModeEx == APT_OUT_CTRL_ONE_SHOT) { + aptHandle->baseAddress->OC_MODE.reg &= (~(protect->ocSysEvent << ocModeOffset)); + } else if (protect->ocEventModeEx == APT_OUT_CTRL_CYCLE_BY_CYBLE) { + aptHandle->baseAddress->OC_MODE.reg |= (protect->ocSysEvent << ocModeOffset); + if ((protect->cbcClrModeEx & APT_CLEAR_CBC_ON_CNTR_ZERO) ==APT_CLEAR_CBC_ON_CNTR_ZERO) { + aptHandle->baseAddress->OC_PRD_CLR.reg |= protect->ocSysEvent; + } + if ((protect->cbcClrModeEx & APT_CLEAR_CBC_ON_CNTR_PERIOD) == APT_CLEAR_CBC_ON_CNTR_PERIOD) { + aptHandle->baseAddress->OC_PRD_CLR.reg |= (protect->ocSysEvent << cbcClrOffsetPrd); + } + } +} + +/** + * @brief System event protect initialize. + * @param aptHandle APT module handle. + * @param protect Output control protection event data. + * @retval None. + */ +static void APT_SysProtectInitEx(APT_Handle *aptHandle, APT_OutCtrlProtectEx *protect) +{ + APT_SetSysEventProtectModeEx(aptHandle, protect); + if (protect->ocEventEnEx == BASE_CFG_ENABLE) { + aptHandle->baseAddress->OC_MODE.reg |= protect->ocSysEvent; + } else { + aptHandle->baseAddress->OC_MODE.reg &= (~(protect->ocSysEvent)); + } + if (protect->ocEvtInterruptEnEx == BASE_CFG_ENABLE) { + aptHandle->baseAddress->INT_EVT_EN.reg |= protect->ocSysEvent; + } else { + aptHandle->baseAddress->INT_EVT_EN.reg &= (~(protect->ocSysEvent)); + } +} + +/** + * @brief Initialize the output control protection event of APT module (Extended interface). + * @param aptHandle APT module handle. + * @param protect Output control protection event data. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_ProtectInitEx(APT_Handle *aptHandle, APT_OutCtrlProtectEx *protect) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(protect != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + APT_PARAM_CHECK_WITH_RET(protect->originalEvtEx >= 0, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(protect->originalEvtEx <= 0x1FF, BASE_STATUS_ERROR); /* 0x1FF : all event enable */ + unsigned int cbcClrOffsetPrd = 16; + aptHandle->baseAddress->OC_MODE.reg = 0x0; /* clear OC_MODE resgiter */ + aptHandle->baseAddress->TC_MODE.BIT.rg_emu_stop = 0x0; /* don't stop APT when emulation */ + aptHandle->baseAddress->OC_PRD_CLR.reg = 0x0; /* clear OC_PRD_CLR register */ + APT_SysProtectInitEx(aptHandle, protect); + /* event management configuration */ + aptHandle->baseAddress->EM_MRG_SEL.BIT.rg_em_a1_sel = EM_COMBINE_A1_SRC_ENABLE_ALL; /* open logic OR */ + aptHandle->baseAddress->EM_AOR_EN.BIT.rg_em_a1_oren = protect->originalEvtEx; /* open selected event */ + APT_SetProtectSrcEventPolarityEx(aptHandle, protect->evtPolarityMaskEx); + APT_SetEMEventFilterEx(protect->filterCycleNumEx); + aptHandle->baseAddress->EM_MRG_SEL.BIT.rg_evta1t_sel= APT_EM_COMBINE_EVT1; /* all event input to combine event A1 */ + /* out control configuration */ + APT_SetOutCtrlActionEx(aptHandle, protect->ocActionEx, protect->ocActionBEx, APT_OC_EVT_COMBINE_EVENT_A1_UP); + APT_SetOutCtrlActionEx(aptHandle, protect->ocActionEx, protect->ocActionBEx, APT_OC_EVT_COMBINE_EVENT_A1_DOWN); + /* system event protect setting. */ + APT_SetOutCtrlActionEx(aptHandle, protect->ocActionEx, protect->ocActionBEx, APT_OC_EVT_GPIO_OR_SYSTEM_UP); + APT_SetOutCtrlActionEx(aptHandle, protect->ocActionEx, protect->ocActionBEx, APT_OC_EVT_GPIO_OR_SYSTEM_DOWN); + aptHandle->baseAddress->OC_MODE.BIT.rg_oc_mode_evta1 = protect->ocEventModeEx; /* set protect mode */ + if ((protect->cbcClrModeEx & APT_CLEAR_CBC_ON_CNTR_ZERO) ==APT_CLEAR_CBC_ON_CNTR_ZERO) { + aptHandle->baseAddress->OC_PRD_CLR.reg |= APT_OC_COMBINE_EVENT_A1; /* set CBC clear mode */ + } + if ((protect->cbcClrModeEx & APT_CLEAR_CBC_ON_CNTR_PERIOD) == APT_CLEAR_CBC_ON_CNTR_PERIOD) { + aptHandle->baseAddress->OC_PRD_CLR.reg |= (APT_OC_COMBINE_EVENT_A1 << cbcClrOffsetPrd); + } + if (protect->ocEventEnEx == BASE_CFG_ENABLE) { + aptHandle->baseAddress->OC_MODE.reg |= APT_OC_COMBINE_EVENT_A1; /* OC input combine event A1 */ + } else { + aptHandle->baseAddress->OC_MODE.reg &= (~(APT_OC_COMBINE_EVENT_A1)); + } + if (protect->ocEvtInterruptEnEx == BASE_CFG_ENABLE) { + aptHandle->baseAddress->INT_EVT_EN.reg |= (APT_OC_COMBINE_EVENT_A1); + } else { + aptHandle->baseAddress->INT_EVT_EN.reg &= (~(APT_OC_COMBINE_EVENT_A1)); /* enable combine event A1 interrupt */ + } + return BASE_STATUS_OK; +} + +/** + * @brief De-initialize the output control protection event of APT module (Extended interface). + * @param aptHandle APT module handle. + * @param protect Output control protection event handle. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_ProtectDeInitEx(APT_Handle *aptHandle, APT_OutCtrlProtectEx *protect) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(protect != NULL); + protect->ocEventEnEx = BASE_CFG_DISABLE; + aptHandle->baseAddress->OC_MODE.reg = 0x700070; /* 0x7000070: default value */ + + return BASE_STATUS_OK; +} + +/** + * @brief De-initialize the output control protection event of APT module. + * @param aptHandle APT module handle. + * @param protect Output control protection event handle. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_ProtectDeInit(APT_Handle *aptHandle, APT_OutCtrlProtect *protect) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(protect != NULL); + protect->ocEventEn = BASE_CFG_DISABLE; + aptHandle->baseAddress->OC_MODE.reg = 0x700070; /* 0x7000070: default value */ + + return BASE_STATUS_OK; +} + +/** + * @brief Set event management's source events polarity. + * @param aptHandle APT module handle. + * @param emEvtSrc Source event selection. + * @param emEvtPolar Event polarity. + * @retval None. + */ +static void APT_SetEMInputEvtPolarity(APT_Handle *aptHandle, APT_EMCombineEvtSrc emEvtSrc, + APT_EMEventPolarity emEvtPolar) +{ + unsigned int eventPolarity; + if (emEvtSrc >= APT_EM_COMBINE_SRC_EVT_MP_1) { + /* set multiplex event polarity */ + eventPolarity = (emEvtSrc - APT_EM_COMBINE_SRC_EVT_MP_1) << 1; + aptHandle->baseAddress->EM_EVTMP_PSEL.reg &= (~(0b11 << eventPolarity)); + aptHandle->baseAddress->EM_EVTMP_PSEL.reg |= (emEvtPolar << eventPolarity); + } else { + /* set io event polarity */ + eventPolarity = (emEvtSrc) << 1; + aptHandle->baseAddress->EM_EVTIO_PSEL.reg &= (~(0b11 << eventPolarity)); + aptHandle->baseAddress->EM_EVTIO_PSEL.reg |= (emEvtPolar << eventPolarity); + } +} + + +/** + * @brief Set event management's source events input and event combine. + * (if enable logic or function, it do not support setting polarity, need use DCL to set polarity.) + * @param aptHandle APT module handle. + * @param emEvent EM event handle. + * @retval None. + */ +static void APT_EMCombineEventInit(APT_Handle *aptHandle, APT_CombineEvt *emEvent) +{ + unsigned int evtNum; + for (evtNum = 0; evtNum < EM_CMB_EVT_NUM; evtNum++) { + /* if select logical or */ + aptHandle->baseAddress->EM_MRG_SEL.reg |= emEvent[evtNum].emEvtSrc << (evtNum * EM_CMB_SRC_SEL_INTERVAL); + if (emEvent[evtNum].emEvtSrc == APT_EM_COMBINE_SRC_ALL_EVENT_OR) { + /* enable logical or events */ + if (evtNum < APT_EM_COMBINE_EVENT_B1) { + aptHandle->baseAddress->EM_AOR_EN.reg |= (emEvent[evtNum].emEvtOrEnBits << (evtNum * EM_OR_INTERVAL)); + } else { + aptHandle->baseAddress->EM_BOR_EN.reg |= (emEvent[evtNum].emEvtOrEnBits << \ + ((evtNum - APT_EM_COMBINE_EVENT_B1) * EM_OR_INTERVAL)); + } + } else { + /* set input event's polarity */ + APT_SetEMInputEvtPolarity(aptHandle, emEvent[evtNum].emEvtSrc, emEvent[evtNum].emEvtPolar); + } + aptHandle->baseAddress->EM_MRG_SEL.reg |= (emEvent[evtNum].emEvtCombineMode << \ + (evtNum * EM_CMB_MODE_INTERVAL)) << EM_CMB_MODE_OFFSET; + } +} + +/* + * @brief Initialize mask window and capture function of event management at up down mode. + * (do not support across cycles mask window). + * @param aptHandle APT module handle. + * @param emWdAndCp Mask window and capture configuration handle. + * @param totalWidth offset add window size value. + * @retval None. + */ +static void APT_EMWdAndCapUpDownModeInit(APT_Handle *aptHandle, APT_WdAndCap *emWdAndCap, unsigned int totalWidth) +{ + unsigned int pointA; /* window left point */ + unsigned int pointB; /* window right point */ + + if (totalWidth <= (aptHandle->waveform.timerPeriod)) { /* total width is little than period value */ + aptHandle->baseAddress->TC_MWDREFB.reg = totalWidth; + aptHandle->baseAddress->TC_MWD_ACT.BIT.rg_mwdrefa_act_inc = APT_PWM_ACTION_HIGH; + aptHandle->baseAddress->TC_MWD_ACT.BIT.rg_mwdrefb_act_inc = APT_PWM_ACTION_LOW; + } else { /* total width bigger than period */ + /* left point smaller or equal than period */ + if ((emWdAndCap->wdOffset) <= (aptHandle->waveform.timerPeriod)) { + /* 2: up down mode waveform period is (timer period * 2) */ + pointB = (2 * aptHandle->waveform.timerPeriod) - totalWidth; + aptHandle->baseAddress->TC_MWDREFB.reg = pointB; + aptHandle->baseAddress->TC_MWD_ACT.BIT.rg_mwdrefa_act_inc = APT_PWM_ACTION_HIGH; + aptHandle->baseAddress->TC_MWD_ACT.BIT.rg_mwdrefb_act_dec = APT_PWM_ACTION_LOW; + } else { /* left point bigger than period */ + /* 2: up down mode waveform period is (timer period * 2) */ + pointA = (2 * aptHandle->waveform.timerPeriod) - emWdAndCap->wdOffset; + aptHandle->baseAddress->TC_MWDREFA.reg = pointA; + aptHandle->baseAddress->TC_MWD_ACT.BIT.rg_mwdrefa_act_dec = APT_PWM_ACTION_HIGH; + aptHandle->baseAddress->TC_MWD_ACT.BIT.rg_mwdrefb_act_dec = APT_PWM_ACTION_LOW; + } + } +} + +/* + * @brief Initialize mask window and capture function of event management(do not support across cycles mask window). + * @param aptHandle APT module handle. + * @param emWdAndCp Mask window and capture configuration handle. + * @retval None. + */ +static void APT_EMWdAndCapInit(APT_Handle *aptHandle, APT_WdAndCap *emWdAndCap) +{ + unsigned int totalWidth; + if (emWdAndCap->wdEnable == true) { + /* filter source select */ + aptHandle->baseAddress->EM_OUT_SEL.BIT.rg_evtfilt_sel = emWdAndCap->eventSel; + /* enable mask window */ + aptHandle->baseAddress->TC_MWD_EN.BIT.rg_mskwd_en = BASE_CFG_ENABLE; + /* set polarity */ + aptHandle->baseAddress->TC_MWD_EN.BIT.rg_mskwd_psel = emWdAndCap->wdPolar; + /* set compare value */ + aptHandle->baseAddress->TC_MWDREFA.reg = emWdAndCap->wdOffset; + totalWidth = emWdAndCap->wdOffset + emWdAndCap->wdWidth; + if (aptHandle->waveform.cntMode == APT_COUNT_MODE_UP_DOWN) { + APT_EMWdAndCapUpDownModeInit(aptHandle, emWdAndCap, totalWidth); + } else if (aptHandle->waveform.cntMode == APT_COUNT_MODE_UP) { + aptHandle->baseAddress->TC_MWDREFB.reg = totalWidth; + aptHandle->baseAddress->TC_MWD_ACT.BIT.rg_mwdrefa_act_inc = APT_PWM_ACTION_HIGH; + aptHandle->baseAddress->TC_MWD_ACT.BIT.rg_mwdrefb_act_inc = APT_PWM_ACTION_LOW; + } else if (aptHandle->waveform.cntMode == APT_COUNT_MODE_DOWN) { + aptHandle->baseAddress->TC_MWDREFB.reg = totalWidth; + aptHandle->baseAddress->TC_MWD_ACT.BIT.rg_mwdrefa_act_dec = APT_PWM_ACTION_HIGH; + aptHandle->baseAddress->TC_MWD_ACT.BIT.rg_mwdrefb_act_dec = APT_PWM_ACTION_LOW; + } else { + return; + } + } + return; +} + +/** + * @brief Event management initialization interface. + * @param aptHandle APT module handle. + * @param eventManage Event management handle. + * @retval None. + */ +BASE_StatusType HAL_APT_EMInit(APT_Handle *aptHandle, APT_EventManage *eventManage) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(eventManage != NULL); + if (eventManage->emEnable == true) { /* event manage enable */ + APT_EMCombineEventInit(aptHandle, eventManage->emEvt); /* init combine event */ + if (eventManage->emWdAndCap.wdEnable == true) { + aptHandle->baseAddress->EM_OUT_SEL.reg |= EM_OUT_EVT_FILTER_EN; + APT_EMWdAndCapInit(aptHandle, &(eventManage->emWdAndCap)); + } + return BASE_STATUS_OK; + } + return BASE_STATUS_ERROR; +} + + +/** + * @brief Get capture value of Event management. + * @param aptHandle APT module handle. + * @retval unsigned short: Capture counting value. + */ +unsigned short HAL_APT_EMGetCapValue(APT_Handle *aptHandle) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + BASE_FUNC_UNUSED(aptHandle); + unsigned short capValue = 0; + return capValue; /* v1 don't have this function return 0 */ +} + +/** + * @brief Set vallet switch's software calibrate of Event management. + * @param aptHandle APT module handle. + * @param calibrate Delay calibration. + * @retval None. + */ +void HAL_APT_EMSetValleySwithSoftDelay(APT_Handle *aptHandle, unsigned short calibrate) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + BASE_FUNC_UNUSED(aptHandle); /* v1 don't have this function */ + BASE_FUNC_UNUSED(calibrate); /* v1 don't have this function */ + return; +} + +/** + * @brief Disable PWMA and PWMB output. PWMA and PWMB output low level. + * @param aptHandle APT module handle. + * @retval None. + */ +void HAL_APT_ForcePWMOutputLow(APT_Handle *aptHandle) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + DCL_APT_ForcePWMOutputLow(aptHandle->baseAddress); + + return; +} + +/** + * @brief Initialize the master APT module when using multiple sync-out mode. + * @param aptHandle APT module handle. + * @param syncOutSrc Master APT module synchronization source. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_MasterSyncInit(APT_Handle *aptHandle, unsigned short syncOutSrc) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + APT_PARAM_CHECK_WITH_RET(syncOutSrc <= SYNC_OUT_SOURCE_MAX, BASE_STATUS_ERROR); + /* Configure the sync-out pulse source of APT module synchronization */ + aptHandle->baseAddress->SYNO_CFG.reg &= (~(0xFF << 0)); + aptHandle->baseAddress->SYNO_CFG.reg |= (syncOutSrc << 0); + aptHandle->baseAddress->SYNO_CFG.BIT.rg_mode_syno = APT_SYNCOUT_MULTIPLE_MODE; + return BASE_STATUS_OK; +} + +/** + * @brief Initialize the slave APT module. + * @param aptHandle APT module handle. + * @param slaveSyncIn Slave APT module synchronization handle. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_SlaveSyncInit(APT_Handle *aptHandle, APT_SlaveSyncIn *slaveSyncIn) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(slaveSyncIn != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + APT_PARAM_CHECK_WITH_RET(slaveSyncIn->divPhase <= aptHandle->waveform.dividerFactor, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(slaveSyncIn->cntPhase < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(slaveSyncIn->cntrSyncSrc <= CNTR_SYNC_SOURCE_MAX, BASE_STATUS_ERROR); + + aptHandle->baseAddress->TC_PHS.BIT.rg_cnt_dir = slaveSyncIn->syncCntMode; + TC_PHS_REG tmp = aptHandle->baseAddress->TC_PHS; + tmp.BIT.rg_cnt_phs = slaveSyncIn->cntPhase; + aptHandle->baseAddress->TC_PHS = tmp; + + aptHandle->baseAddress->SYNI_CFG.BIT.rg_syni_sel = slaveSyncIn->syncInSrc; + aptHandle->baseAddress->SYNCNT_CFG.reg = slaveSyncIn->cntrSyncSrc; + return BASE_STATUS_OK; +} + +/** + * @brief Start all of the used APT modules simultaneously. + * @param aptRunMask A logical OR of valid values that can be passed as the aptRunMask. + * Valid values for aptRunMask are: + * RUN_APT0 - apt0_run bit in SYSCTRL1 register. + * RUN_APT1 - apt1_run bit in SYSCTRL1 register. + * RUN_APT2 - apt2_run bit in SYSCTRL1 register. + * RUN_APT3 - apt3_run bit in SYSCTRL1 register. + * RUN_APT4 - apt4_run bit in SYSCTRL1 register. + * RUN_APT5 - apt5_run bit in SYSCTRL1 register. + * RUN_APT6 - apt6_run bit in SYSCTRL1 register. + * RUN_APT7 - apt7_run bit in SYSCTRL1 register. + * RUN_APT8 - apt8_run bit in SYSCTRL1 register. + * @retval None. + */ +void HAL_APT_StartModule(unsigned int aptRunMask) +{ + SYSCTRL1->APT_RUN.reg |= aptRunMask; +} + +/** + * @brief Stop all of the used APT modules simultaneously. + * @param aptRunMask A logical OR of valid values that can be passed as the aptRunMask. + * Valid values for aptRunMask are: + * RUN_APT0 - apt0_run bit in SYSCTRL1 register. + * RUN_APT1 - apt1_run bit in SYSCTRL1 register. + * RUN_APT2 - apt2_run bit in SYSCTRL1 register. + * RUN_APT3 - apt3_run bit in SYSCTRL1 register. + * RUN_APT4 - apt4_run bit in SYSCTRL1 register. + * RUN_APT5 - apt5_run bit in SYSCTRL1 register. + * RUN_APT6 - apt6_run bit in SYSCTRL1 register. + * RUN_APT7 - apt7_run bit in SYSCTRL1 register. + * RUN_APT8 - apt8_run bit in SYSCTRL1 register. + * @retval None. + */ +void HAL_APT_StopModule(unsigned int aptRunMask) +{ + SYSCTRL1->APT_RUN.reg &= (~aptRunMask); +} + +/** + * @brief Set the count compare points along the left and right edges of PWM waveform. + * @param aptHandle APT module handle. + * @param cntCmpLeftEdge The count compare point of the left edge of PWM waveform. Pull High on left edge. + * @param cntCmpRightEdge The count compare point of the right edge of PWM waveform. Pull Low on right edge. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_SetPWMDuty(APT_Handle *aptHandle, unsigned short cntCmpLeftEdge, \ + unsigned short cntCmpRightEdge) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + APT_PARAM_CHECK_WITH_RET(cntCmpLeftEdge > 0, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(cntCmpLeftEdge < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(cntCmpRightEdge > 0, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(cntCmpRightEdge < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + TC_REFC_REG tmpC; + TC_REFD_REG tmpD; + tmpC = aptHandle->baseAddress->TC_REFC; + tmpC.BIT.rg_cnt_refc = cntCmpLeftEdge; + aptHandle->baseAddress->TC_REFC = tmpC; + tmpD = aptHandle->baseAddress->TC_REFD; + tmpD.BIT.rg_cnt_refd = cntCmpRightEdge; + aptHandle->baseAddress->TC_REFD = tmpD; + return BASE_STATUS_OK; +} + +/** + * @brief Set the count compare points along the left and right edges of PWM waveform. + * @param aptHandle APT module handle. + * @param duty PWM duty. Range: 1 ~ 99. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_SetPWMDutyByNumber(APT_Handle *aptHandle, unsigned int duty) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + APT_PARAM_CHECK_WITH_RET(duty < MAX_DUTY, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(duty > 0, BASE_STATUS_ERROR); + + unsigned int cntCmpLeftEdge, cntCmpRightEdge; + TC_REFC_REG tmpC; + TC_REFD_REG tmpD; + + if (aptHandle->waveform.cntMode == APT_COUNT_MODE_UP_DOWN) { + cntCmpLeftEdge = aptHandle->waveform.timerPeriod - \ + (int)(((float)aptHandle->waveform.timerPeriod / MAX_DUTY) * duty); + cntCmpRightEdge = cntCmpLeftEdge; + } else { + cntCmpLeftEdge = 1; + cntCmpRightEdge = (int)(((float)aptHandle->waveform.timerPeriod / MAX_DUTY) * duty + cntCmpLeftEdge); + } + tmpC = aptHandle->baseAddress->TC_REFC; + tmpC.BIT.rg_cnt_refc = cntCmpLeftEdge; + aptHandle->baseAddress->TC_REFC = tmpC; + tmpD = aptHandle->baseAddress->TC_REFD; + tmpD.BIT.rg_cnt_refd = cntCmpRightEdge; + aptHandle->baseAddress->TC_REFD = tmpD; + return BASE_STATUS_OK; +} + +/** + * @brief Set the count compare points to trigger the ADC sampling. + * @param aptHandle APT module handle. + * @param cntCmpSOCA The count compare point for triggering SOCA. + * @param cntCmpSOCB The count compare point for triggering SOCB. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_SetADCTriggerTime(APT_Handle *aptHandle, unsigned short cntCmpSOCA, unsigned short cntCmpSOCB) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + APT_PARAM_CHECK_WITH_RET(cntCmpSOCA > 0, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(cntCmpSOCA < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(cntCmpSOCB > 0, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(cntCmpSOCB < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + TC_REFA_REG tmpA; + TC_REFB_REG tmpB; + tmpA = aptHandle->baseAddress->TC_REFA; + tmpA.BIT.rg_cnt_refa = cntCmpSOCA; + aptHandle->baseAddress->TC_REFA = tmpA; + tmpB = aptHandle->baseAddress->TC_REFB; + tmpB.BIT.rg_cnt_refb = cntCmpSOCB; + aptHandle->baseAddress->TC_REFB = tmpB; + return BASE_STATUS_OK; +} + +/** + * @brief set outputs of channelA when use APT_PWM_BASIC_A_HIGH_B_HIGH. + * @param aptHandle APT module handle. + * @param aptAction output action type. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +static BASE_StatusType APT_SetActionChannelA(APT_Handle *aptHandle, APT_PWMChannelOutType aptAction) +{ + switch (aptAction) { + case APT_PWM_OUT_BASIC_TYPE: + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pga_frc_en = BASE_CFG_UNSET; /* disable force action */ + break; + case APT_PWM_OUT_ALWAYS_LOW: + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pga_frc_act = APT_PWM_OUT_ALWAYS_LOW; /* force output low */ + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pga_frc_en = BASE_CFG_SET; + break; + case APT_PWM_OUT_ALWAYS_HIGH: + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pga_frc_act = APT_PWM_OUT_ALWAYS_HIGH; /* force output high */ + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pga_frc_en = BASE_CFG_SET; + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief set outputs of channelB when use APT_PWM_BASIC_A_HIGH_B_HIGH. + * @param aptHandle APT module handle. + * @param aptAction output action type. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +static BASE_StatusType APT_SetActionChannelB(APT_Handle *aptHandle, APT_PWMChannelOutType aptAction) +{ + switch (aptAction) { + case APT_PWM_OUT_BASIC_TYPE: + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pgb_frc_en = BASE_CFG_UNSET; /* disable force action */ + break; + case APT_PWM_OUT_ALWAYS_LOW: + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pgb_frc_act = APT_PWM_OUT_ALWAYS_LOW; /* force output low */ + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pgb_frc_en = BASE_CFG_SET; + break; + case APT_PWM_OUT_ALWAYS_HIGH: + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pgb_frc_act = APT_PWM_OUT_ALWAYS_HIGH; /* force output high */ + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pgb_frc_en = BASE_CFG_SET; + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief Change outputs of channelA and channelB when use APT_PWM_BASIC_A_HIGH_B_HIGH. + * @param aptHandle APT module handle. + * @param channel channel number. + * @param aptAction output action type. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_ChangeOutputType(APT_Handle *aptHandle, APT_PWMChannel channel, APT_PWMChannelOutType aptAction) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(aptHandle->baseAddress != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + APT_PARAM_CHECK_WITH_RET(channel >= APT_PWM_CHANNEL_A, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(channel <= APT_PWM_CHANNEL_B, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptAction >= APT_PWM_OUT_BASIC_TYPE, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptAction <= APT_PWM_OUT_ALWAYS_HIGH, BASE_STATUS_ERROR); + /* only use in APT_PWM_BASIC_A_HIGH_B_HIGH mode */ + if (aptHandle->waveform.basicType != APT_PWM_BASIC_A_HIGH_B_HIGH) { + return BASE_STATUS_ERROR; + } + if (channel == APT_PWM_CHANNEL_A) { + return APT_SetActionChannelA(aptHandle, aptAction); /* set channnelA's action */ + } else if (channel == APT_PWM_CHANNEL_B) { + return APT_SetActionChannelB(aptHandle, aptAction); /* set channelB's action */ + } else { + return BASE_STATUS_ERROR; /* error channnel number */ + } +} + +/** + * @brief APT event interrupt service processing function. + * @param handle APT module handle. + * @retval None. + */ +void HAL_APT_EventIrqHandler(void *handle) +{ + APT_ASSERT_PARAM(handle != NULL); + APT_Handle *aptHandle = (APT_Handle *)handle; + /* Continuous protection cannot clear the event flag. Clear the event flag by users. */ + if (aptHandle->baseAddress->OC_MODE.BIT.rg_oc_mode_evta1 == 0x1) { /* Protection by period. */ + /* Interrupt of the periodic protection clear event. */ + aptHandle->baseAddress->OC_EVT_FLAG.reg |= ALL_EVT_INT_FLAGS; + } + aptHandle->baseAddress->OC_EVT_FLAG.BIT.rg_int_clr_evt = 1; /* clear event flag */ + if (aptHandle->userCallBack.EvtInterruptCallBack != NULL) { + aptHandle->userCallBack.EvtInterruptCallBack(aptHandle); + } +} + +/** + * @brief APT timer interrupt service processing function. + * @param handle APT module handle. + * @retval None. + */ +void HAL_APT_TimerIrqHandler(void *handle) +{ + APT_ASSERT_PARAM(handle != NULL); + APT_Handle *aptHandle = (APT_Handle *)handle; + aptHandle->baseAddress->INT_TMR_FLAG.BIT.rg_int_clr_tmr = 1; /* clear timer interrupt flag */ + if (aptHandle->userCallBack.TmrInterruptCallBack != NULL) { + aptHandle->userCallBack.TmrInterruptCallBack(aptHandle); + } +} + +/** + * @brief Interrupt callback functions registration interface. + * @param aptHandle APT module handle. + * @param typeID ID of callback function type. + * @param pCallback Pointer for the user callback function. + * @retval None. + */ +void HAL_APT_RegisterCallBack(APT_Handle *aptHandle, APT_InterruputType typeID, APT_CallbackType pCallback) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + switch (typeID) { + case APT_TIMER_INTERRUPT: + aptHandle->userCallBack.TmrInterruptCallBack = pCallback; /* register timer interrupt callback */ + break; + case APT_EVENT_INTERRUPT: + aptHandle->userCallBack.EvtInterruptCallBack = pCallback; /* register event interrupt callback */ + break; + default: + break; + } +} + +/** + * @brief Set window's offset and width of Event management. + * @param aptHandle APT module handle. + * @param offset Window's offset. + * @param width Window's width. + * @note Not support this function in this version. Empty Function. + * @retval None. + */ +void HAL_APT_EMSetWdOffsetAndWidth(APT_Handle *aptHandle, unsigned short offset, unsigned short width) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + BASE_FUNC_UNUSED(aptHandle); /* Not support this function */ + BASE_FUNC_UNUSED(offset); + BASE_FUNC_UNUSED(width); + return; +} + +/** + * @brief Attribute configuration of the reference point. + * @param aptHandle APT module handle. + * @param refDotParameters Attribute structure of a reference point. + * @retval BASE_StatusType: OK, ERROR. + */ +static BASE_StatusType APT_ConfigAction(APT_Handle *aptHandle, APT_RefDotParameters *refDotParameters) +{ + /* Action configuration of the reference point of channel B. */ + if (refDotParameters->pwmChannel == APT_PWM_CHANNEL_B) { + aptHandle->baseAddress->PG_ACT_B.reg &= (~(0b11 << refDotParameters->actionEvent)); /* Reset configuration */ + aptHandle->baseAddress->PG_ACT_B.reg |= (refDotParameters->action << refDotParameters->actionEvent); + return BASE_STATUS_OK; + } + /* Action configuration of the reference point of channel A. */ + if (refDotParameters->pwmChannel == APT_PWM_CHANNEL_A) { + aptHandle->baseAddress->PG_ACT_A.reg &= (~(0b11 << refDotParameters->actionEvent)); /* Reset configuration */ + aptHandle->baseAddress->PG_ACT_A.reg |= (refDotParameters->action << refDotParameters->actionEvent); + return BASE_STATUS_OK; + } + return BASE_STATUS_ERROR; +} + +/** + * @brief Configure the value and action of the reference point A. + * @param aptHandle APT module handle. + * @param refDotParameters Reference point A configuration property set. + * @retval BASE_StatusType: OK, ERROR. + */ +BASE_StatusType APT_ConfigRefA(APT_Handle *aptHandle, APT_RefDotParameters *refDotParameters) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(aptHandle->baseAddress != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + /* Check the attributes of the reference point A: PWM Channel. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel >= APT_PWM_CHANNEL_A, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel <= APT_PWM_CHANNEL_B, BASE_STATUS_ERROR); + /* Check the attributes of the reference point A: triggle action event. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent >= APT_PWM_ACTION_ON_TIMEBASE_ZERO, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent <= APT_PWM_ACTION_ON_C2_COUNT_DOWN, BASE_STATUS_ERROR); + /* Check the attributes of the reference point A: triggle action. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->action <= APT_PWM_ACTION_TOGGLE, BASE_STATUS_ERROR); + /* Change reference dot A value and division value. */ + aptHandle->baseAddress->TC_REFA.BIT.rg_cnt_refa = refDotParameters->refDotValue; + /* Reference dot A triggle event and action */ + return APT_ConfigAction(aptHandle, refDotParameters); +} + +/** + * @brief Configure the value and action of the reference point B. + * @param aptHandle APT module handle. + * @param refDotParameters Reference point B configuration property set. + * @retval BASE_StatusType: OK, ERROR. + */ +BASE_StatusType APT_ConfigRefB(APT_Handle *aptHandle, APT_RefDotParameters *refDotParameters) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(aptHandle->baseAddress != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + /* Check the attributes of the reference point B: PWM Channel. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel >= APT_PWM_CHANNEL_A, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel <= APT_PWM_CHANNEL_B, BASE_STATUS_ERROR); + /* Check the attributes of the reference point B: triggle action event. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent >= APT_PWM_ACTION_ON_TIMEBASE_ZERO, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent <= APT_PWM_ACTION_ON_C2_COUNT_DOWN, BASE_STATUS_ERROR); + /* Check the attributes of the reference point B: triggle action. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->action <= APT_PWM_ACTION_TOGGLE, BASE_STATUS_ERROR); + /* Change reference dot B value and division value. */ + aptHandle->baseAddress->TC_REFB.BIT.rg_cnt_refb = refDotParameters->refDotValue; + /* Reference dot B triggle event and action. */ + return APT_ConfigAction(aptHandle, refDotParameters); +} + +/** + * @brief Configure the value and action of the reference point C. + * @param aptHandle APT module handle. + * @param refDotParameters Reference point C configuration property set. + * @retval BASE_StatusType: OK, ERROR. + */ +BASE_StatusType APT_ConfigRefC(APT_Handle *aptHandle, APT_RefDotParameters *refDotParameters) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(aptHandle->baseAddress != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + /* Check the attributes of the reference point C: PWM Channel. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel >= APT_PWM_CHANNEL_A, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel <= APT_PWM_CHANNEL_B, BASE_STATUS_ERROR); + /* Check the attributes of the reference point C: triggle action event. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent >= APT_PWM_ACTION_ON_TIMEBASE_ZERO, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent <= APT_PWM_ACTION_ON_C2_COUNT_DOWN, BASE_STATUS_ERROR); + /* Check the attributes of the reference point C: triggle action. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->action <= APT_PWM_ACTION_TOGGLE, BASE_STATUS_ERROR); + /* Change reference dot C value and division value. */ + aptHandle->baseAddress->TC_REFC.BIT.rg_cnt_refc = refDotParameters->refDotValue; + /* Reference dot C triggle event and action. */ + return APT_ConfigAction(aptHandle, refDotParameters); +} + +/** + * @brief Configure the value and action of the reference point D. + * @param aptHandle APT module handle. + * @param refDotParameters Reference point D configuration property set. + * @retval BASE_StatusType: OK, ERROR. + */ +BASE_StatusType APT_ConfigRefD(APT_Handle *aptHandle, APT_RefDotParameters *refDotParameters) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(aptHandle->baseAddress != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + /* Check the attributes of the reference point D: PWM Channel. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel >= APT_PWM_CHANNEL_A, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel <= APT_PWM_CHANNEL_B, BASE_STATUS_ERROR); + /* Check the attributes of the reference point D: triggle action event. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent >= APT_PWM_ACTION_ON_TIMEBASE_ZERO, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent <= APT_PWM_ACTION_ON_C2_COUNT_DOWN, BASE_STATUS_ERROR); + /* Check the attributes of the reference point D: triggle action. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->action <= APT_PWM_ACTION_TOGGLE, BASE_STATUS_ERROR); + /* Change reference dot D value and division value. */ + aptHandle->baseAddress->TC_REFD.BIT.rg_cnt_refd = refDotParameters->refDotValue; + /* Reference dot D triggle event and action. */ + return APT_ConfigAction(aptHandle, refDotParameters); +} + + +/** + * @brief Attribute configuration of any reference point. + * @param aptHandle APT module handle. + * @param refDotSelect Selection of reference points. + * @param refDotParameters The properties of the reference point. + * @retval BASE_StatusType: OK, ERROR. + */ +BASE_StatusType HAL_APT_ConfigRefDot(APT_Handle *aptHandle, APT_RefDotSelect refDotSelect, + APT_RefDotParameters *refDotParameters) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(aptHandle->baseAddress != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + /* Reference point configuration, which must be point A, point B, point C, and point D. */ + APT_PARAM_CHECK_WITH_RET(refDotSelect >= APT_REFERENCE_DOTA, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotSelect <= APT_REFERENCE_DOTD, BASE_STATUS_ERROR); + /* Channels A and B are optional. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel >= APT_PWM_CHANNEL_A, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel <= APT_PWM_CHANNEL_B, BASE_STATUS_ERROR); + /* Trigger event type check. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent >= APT_PWM_ACTION_ON_TIMEBASE_ZERO, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent <= APT_PWM_ACTION_ON_C2_COUNT_DOWN, BASE_STATUS_ERROR); + /* There are four types of trigger actions. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->action <= APT_PWM_ACTION_TOGGLE, BASE_STATUS_ERROR); + /* Transfer table for setting reference dot. */ + BASE_StatusType (* APT_RefDotConfigTable[RERF])(APT_Handle *, APT_RefDotParameters *) = {APT_ConfigRefA, + APT_ConfigRefB, + APT_ConfigRefC, + APT_ConfigRefD}; + return APT_RefDotConfigTable[refDotSelect](aptHandle, refDotParameters); /* Configure reference point. */ +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/base/common/inc/baseinc.h b/vendor/xinlingyu_92_3061M/Project/drivers/base/common/inc/baseinc.h new file mode 100644 index 0000000000000000000000000000000000000000..2f9c37a89631f631cb6d7726bafb8a18cf2f56a7 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/base/common/inc/baseinc.h @@ -0,0 +1,39 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file baseinc.h + * @author MCU Driver Team + * @brief BASE module driver + * @details Contains BASE-related header files. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_BASEINC_H +#define McuMagicTag_BASEINC_H + +/* Includes ------------------------------------------------------------------ */ +#include "chipinc.h" +#include "typedefs.h" +#include "assert.h" +#include "clock.h" +#include "lock.h" +#include "generalfunc.h" +#include "base_math.h" +#include "reset.h" +#include "interrupt.h" + +#endif /* McuMagicTag_BASEINC_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/assert.h b/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/assert.h new file mode 100644 index 0000000000000000000000000000000000000000..4d17a1c80fa18e4dcc8b3519b76a8e3da3dfb74b --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/assert.h @@ -0,0 +1,96 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file assert.h + * @author MCU Driver Team + * @brief BASE module driver + * @details This file provides functions declaration of the assert, + * + BASE_FUNC_PARAMCHECK_NO_RET macro function definition. + * + BASE_FUNC_PARAMCHECK_WITH_RET macro function definition. + * + BASE_FUNC_ASSERT_PARAM macro function definition. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_ASSERT_H +#define McuMagicTag_ASSERT_H + +/* Includes ------------------------------------------------------------------ */ +#include "chipinc.h" +#include "typedefs.h" +/** + * @defgroup BASE BASE + * @brief BASE module. + * @{ + */ + +void AssertErrorLog(char *file, unsigned int line); + +/** + * @defgroup ASSERT Assert Definition + * @brief Definition of different assert. + * @{ + */ + +/** + * @defgroup ASSERT_Macro ASSERT Macro Function Definition + * @{ + */ +/* Macro definitions --------------------------------------------------------- */ +#if (BASE_DEFINE_USE_ASSERT == BASE_CFG_ENABLE) +#define BASE_FUNC_PARAMCHECK_NO_RET(param) \ + do { \ + if (!(param)) { \ + AssertErrorLog(__FILE__, __LINE__); \ + return; \ + } \ + } while (0) + +#define BASE_FUNC_PARAMCHECK_WITH_RET(param, ret) \ + do { \ + if (!(param)) { \ + AssertErrorLog(__FILE__, __LINE__); \ + return ret; \ + } \ + } while (0) + +#define BASE_FUNC_ASSERT_PARAM(param) \ + do { \ + if (!(param)) { \ + AssertErrorLog(__FILE__, __LINE__); \ + while (1) { \ + }; \ + } \ + } while (0) + +#else +#define BASE_FUNC_ASSERT_PARAM(param) ((void)0U) +#define BASE_FUNC_PARAMCHECK_NO_RET(param) ((void)0U) +#define BASE_FUNC_PARAMCHECK_WITH_RET(param, ret) ((void)0U) + +#endif /* BASE_DEFINE_USE_ASSERT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_ASSERT_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/base_math.h b/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/base_math.h new file mode 100644 index 0000000000000000000000000000000000000000..defe9cb0080157e55bdc47842b376a1cb1284f86 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/base_math.h @@ -0,0 +1,116 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file base_math.h + * @author MCU Driver Team + * @brief BASE module driver + * @details This file provides functions declaration of math + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_BASE_MATH_H +#define McuMagicTag_BASE_MATH_H + +/* Includes ------------------------------------------------------------------ */ +#include "chipinc.h" +#include "typedefs.h" +#include "assert.h" + +/** + * @defgroup BASE BASE + * @brief BASE module. + * @{ + */ + +/** + * @defgroup MATH Math Definition + * @brief Definition of MATH Definition. + * @{ + */ + +/** + * @defgroup MATH_STRUCTURE_DEFINITION math structure Definition + * @brief Definition of math structure Definition. + * @{ + */ +/* Typedef definitions ------------------------------------------------------- */ +/** + * @brief sin, cos status definition. + */ +typedef struct { + int sin : 16; + int cos : 16; +} BASE_MathTypeSinCos; + +/** + * @brief q-axis d-axis status definition. + */ +typedef struct { + int q : 16; + int d : 16; +} BASE_MathTypeQD; + +/** + * @brief current component a,b status definition. + */ +typedef struct { + int a : 16; + int b : 16; +} BASE_MathTypeAB; + +/** + * @brief alpha-axis beta-axis status definition. + */ +typedef struct { + int alpha : 16; + int beta : 16; +} BASE_MathTypeAlphaBeta; +/** + * @} + */ +/** + * @defgroup MATH_API_DEFINITION Math API + * @brief Definition of math API Definition. + * @{ + */ +/* Macro definitions --------------------------------------------------------- */ +#define BASE_MATH_ABS(x) ((x) < 0 ? -(x) : (x)) + +/* Radian to angle. */ +#define BASE_MATH_RADIAN_TO_ANGLE(radian) ((radian) * 57.295779524) + +/* Exported global functions ------------------------------------------------- */ +BASE_MathTypeSinCos BASE_MATH_GetSinCos(short angle); +float BASE_MATH_GetSin(float angle); +float BASE_MATH_GetCos(float angle); +float BASE_MATH_Sqrt(const float x); +float BASE_MATH_Pow(float x, int n); +BASE_MathTypeAlphaBeta BASE_MATH_Clarke(BASE_MathTypeAB input); +BASE_MathTypeQD BASE_MATH_Park(BASE_MathTypeAlphaBeta input, short theta); +BASE_MathTypeAlphaBeta BASE_MATH_RevPark(BASE_MathTypeQD input, short theta); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_BASE_MATH_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/clock.h b/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/clock.h new file mode 100644 index 0000000000000000000000000000000000000000..0f5df18e35b2a500dcbe60358d22fe6d54f5f6ba --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/clock.h @@ -0,0 +1,105 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file clock.h + * @author MCU Driver Team + * @brief BASE module driver + * @brief Include the header file of the clock.c file. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_CLOCK_H +#define McuMagicTag_CLOCK_H + +/* Includes ------------------------------------------------------------------ */ +#include "chipinc.h" +#include "typedefs.h" + +/** + * @defgroup BASE BASE + * @brief BASE module. + * @{ + */ + +/** + * @defgroup CLOCK Clock Definition + * @brief Definition of Clock Definition. + * @{ + */ + +/** + * @defgroup CLOCK_ENUM_DEFINITION Delay Enum Definition + * @brief Definition of BASE_DelayUnit enum + * @{ + */ + +/* Typedef definitions ------------------------------------------------------- */ +/** + * @brief Multiples of the parameters of the delay function based on microseconds in different time units. + * @details BASE_DelayUnit: + * + BASE_DEFINE_DELAY_SECS -- Needed delay amount is in seconds + * + BASE_DEFINE_DELAY_MILLISECS -- Needed delay amount is in milliseconds + * + BASE_DEFINE_DELAY_MICROSECS -- Needed delay amount is in microseconds + */ +typedef enum { + BASE_DEFINE_DELAY_SECS = 1, + BASE_DEFINE_DELAY_MILLISECS = 1000, + BASE_DEFINE_DELAY_MICROSECS = 1000000 +} BASE_DelayUnit; +/** + * @} + */ + +/** + * @defgroup CLOCK_MACRO_DEFINITION Delay Macro Function Definition + * @brief Definition of BASE_DelayUnit macro. + * @{ + */ +/* Macro definitions --------------------------------------------------------- */ +#define BASE_DEFINE_DELAY_MS_IN_SEC 1000 +#define BASE_DEFINE_DELAY_US_IN_MS 1000 + +#define BASE_FUNC_DELAY_S(n) BASE_FUNC_Delay(n, BASE_DEFINE_DELAY_SECS) +#define BASE_FUNC_DELAY_MS(n) BASE_FUNC_Delay(n, BASE_DEFINE_DELAY_MILLISECS) +#define BASE_FUNC_DELAY_US(n) BASE_FUNC_Delay(n, BASE_DEFINE_DELAY_MICROSECS) +/** + * @} + */ + +/** + * @defgroup CLOCK_API_DEFINITION Clock Delay API + * @brief Definition of clcok API. + * @{ + */ +/* Exported global functions ------------------------------------------------------------------ */ +unsigned int BASE_FUNC_GetCpuFreqHz(void); +void BASE_FUNC_Delay(unsigned int delay, BASE_DelayUnit units); +void BASE_FUNC_DelayUs(unsigned int us); +void BASE_FUNC_DelayMs(unsigned int ms); +void BASE_FUNC_DelaySeconds(unsigned int seconds); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_CLOCK_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/generalfunc.h b/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/generalfunc.h new file mode 100644 index 0000000000000000000000000000000000000000..06ef81bbb2b9a396f1318cf988ff61fdeabdcaa4 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/generalfunc.h @@ -0,0 +1,109 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file generalfunc.h + * @author MCU Driver Team + * @brief BASE module driver + * @details This file provides functions declaration of the basic function + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_GENERAL_FUNC_H +#define McuMagicTag_GENERAL_FUNC_H + +/* Includes ------------------------------------------------------------------ */ +#include "chipinc.h" +#include "typedefs.h" +#include "assert.h" +#include "clock.h" + +/** + * @defgroup BASE BASE + * @brief BASE module. + * @{ + */ + +/** + * @defgroup GeneralFunc GeneralFunc Definition + * @brief Definition of GeneralFunc function. + * @{ + */ + +/* Typedef definitions ------------------------------------------------------- */ +/** + * @defgroup BASIC_Structure_Definition BASE_AverageHandle Definition + * @{ + */ + +/** + * @brief Structure for configuring and controlling averaging + */ +typedef struct { + unsigned int cnt; /**< Used to record the divisor of the average */ + float *buf; /**< Buffer pointer */ + unsigned int size; /**< Buffer size */ + unsigned int at; /**< Index value of the currently inserted value */ + unsigned int calNum; /**< Total number to be averaged */ + float total; /**< Current Cumulative Sum */ +} BASE_AverageHandle; +/** + * @} + */ + +/** + * @defgroup BASIC_Structure_Definition BASE_FSM_Handle Definition + * @{ + */ +typedef BASE_FSM_Status (*FunType)(void); +/** + * @brief General state machine handle + */ +typedef struct { + FunType funList[BASE_DEFINE_FSM_END + 1]; /**< function list */ + BASE_FSM_Status nextFun; /**< next function status */ +} BASE_FSM_Handle; +/** + * @} + */ + +/** + * @defgroup GENERAL_API_Definition GENERAL_API + * @{ + */ +/* Exported global functions ------------------------------------------------- */ +unsigned int BASE_FUNC_GetTick(void); +unsigned int BASE_FUNC_FindArrayValue(const unsigned short *nums, unsigned int leng, unsigned int value); +unsigned char BASE_FUNC_CalcSumByte(const unsigned char *pt, unsigned int len); +unsigned short BASE_FUNC_CalcSumShort(unsigned char const * pt, unsigned int len); +BASE_StatusType BASE_FUNC_AverageInit(unsigned int index, float *buf, unsigned int size, unsigned int calNum); +float BASE_FUNC_GetSlipAverageVal(unsigned int index, float val); +void BASE_FUNC_AverageDeInit(unsigned int index); +void BASE_FSM_FunRegister(BASE_FSM_Status index, FunType funAddress); +void BASE_FSM_Run(unsigned int delayTime, BASE_DelayUnit delayUnit); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_GENERAL_FUNC_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/interrupt.h b/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/interrupt.h new file mode 100644 index 0000000000000000000000000000000000000000..1fa09615b9f1968f63a7edd416f1996e8dad5c63 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/interrupt.h @@ -0,0 +1,318 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file interrupt.h + * @author MCU Driver Team + * @brief BASE module driver + * @brief Header file containing functions prototypes of Interrupt HAL library. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_INTERRUPT_H +#define McuMagicTag_INTERRUPT_H + +/* Includes ------------------------------------------------------------------*/ +#include "feature.h" +#include "interrupt_ip.h" + +/* Macro definitions ---------------------------------------------------------*/ +#define INTERRUPT_USE_ASSERT +#ifdef INTERRUPT_USE_ASSERT +#define INTERRUPT_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define INTERRUPT_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define INTERRUPT_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define INTERRUPT_ASSERT_PARAM(para) ((void)0U) +#define INTERRUPT_PARAM_CHECK_NO_RET ((void)0U) +#define INTERRUPT_PARAM_CHECK_WITH_RET ((void)0U) +#endif +/** + * @defgroup BASE BASE + * @brief BASE module. + * @{ + */ + +/** + * @defgroup INTERRUPT Interrupt Definition + * @brief Definition of Interrupt Definition. + * @{ + */ + +/** + * @defgroup INTERRUPT_MACRO Macro Definition + * @brief Definition of Interrupt Definition. + * @{ + */ + +/** + * @brief IRQ module error code + */ +#define IRQ_ERRNO_PROC_FUNC_NULL 1 /**< Non-interrupted callback function */ +#define IRQ_ERRNO_NUM_INVALID 2 /**< Interrupt Number invalid */ +#define IRQ_ERRNO_ALREADY_CREATED 3 /**< Interrupt function is created */ +#define IRQ_ERRNO_NOT_CREATED 4 /**< Interrupt function not create */ +#define IRQ_ERRNO_PRIORITY_INVALID 5 /**< Invalid priority */ + +#define RISCV_U_MODE 0x8 /**< The Value in mcause for umode */ +#define RISCV_M_MODE 0xB /**< The Value in mcause for mmode */ +/** + * @} + */ + +/** + * @defgroup ASM Interrupt ASM Function Definition + * @brief Definition of Interrupt ASM Function Definition. + * @{ + */ + +/** + * @brief Read standard csr registers + */ +#define READ_CSR(csrReg) ({ \ + unsigned int tmp_; \ + asm volatile ("csrr %0, " #csrReg : "=r"(tmp_)); \ + tmp_; \ +}) + + +/** + * @brief Write standard csr registers + */ +#define WRITE_CSR(csrReg, csrVal) do { \ + if (__builtin_constant_p(csrVal) && ((unsigned int)(csrVal) < 32)) { \ + asm volatile ("csrw " #csrReg ", %0" :: "i"(csrVal)); \ + } else { \ + asm volatile ("csrw " #csrReg ", %0" :: "r"(csrVal)); \ + } \ +} while (0) + +/** + * @brief Set standard csr registers + */ +#define SET_CSR(csrReg, csrBit) do { \ + unsigned int tmp_; \ + if (__builtin_constant_p(csrBit) && ((unsigned int)(csrBit) < 32)) { \ + asm volatile ("csrrs %0, " #csrReg ", %1" : "=r"(tmp_) : "i"(csrBit)); \ + } else { \ + asm volatile ("csrrs %0, " #csrReg ", %1" : "=r"(tmp_): "r"(csrBit)); \ + } \ + (void)tmp_; \ +} while (0) + +/** + * @brief Clear standard csr registers + */ +#define CLEAR_CSR(csrReg, csrBit) do { \ + unsigned int tmp_; \ + if (__builtin_constant_p(csrBit) && ((unsigned int)(csrBit) < 32)) { \ + asm volatile ("csrrc %0, " #csrReg ", %1" : "=r"(tmp_) : "i"(csrBit)); \ + } else { \ + asm volatile ("csrrc %0, " #csrReg ", %1" : "=r"(tmp_) : "r"(csrBit)); \ + } \ + (void)tmp_; \ +} while (0) + +/** + * @brief Read the custom defined registers of the chip + */ +#define READ_CUSTOM_CSR(csrReg) ({ \ + unsigned int tmp_; \ + asm volatile ("csrr %0, %1" : "=r"(tmp_) : "i"(csrReg)); \ + tmp_; \ +}) + +/** + * @brief Write the custom defined registers of the chip + */ +#define WRITE_CUSTOM_CSR_VAL(csrRegAddr, csrVal) do { \ + if (__builtin_constant_p(csrVal)) { \ + asm volatile("li t0," "%0" : : "i"(csrVal)); \ + } else { \ + asm volatile("mv t0," "%0" : : "r"(csrVal)); \ + } \ + asm volatile("csrw %0, t0" :: "i"(csrRegAddr)); \ +} while (0) + +/** + * @brief Set the custom defined registers of the chip + */ +#define SET_CUSTOM_CSR(csrRegAddr, csrBit) do { \ + if (__builtin_constant_p(csrBit) && ((unsigned int)(csrBit) < 32)) { \ + asm volatile("li t0," "%0" : : "i"(csrBit)); \ + } else { \ + asm volatile("mv t0," "%0" : : "r"(csrBit)); \ + } \ + asm volatile("csrs %0, t0" :: "i"(csrRegAddr)); \ +} while (0) + +/** + * @brief Clear the custom defined registers of the chip + */ +#define CLEAR_CUSTOM_CSR(csrRegAddr, csrBit) do { \ + if (__builtin_constant_p(csrBit) && ((unsigned int)(csrBit) < 32)) { \ + asm volatile("li t0," "%0" : : "i"(csrBit)); \ + } else { \ + asm volatile("mv t0," "%0" : : "r"(csrBit)); \ + } \ + asm volatile("csrc %0, t0" :: "i"(csrRegAddr)); \ +} while (0) + +/* Configure the locipri register, that is, configure the interrupt priority */ +/** + * @brief Get the local interrupt register number. + */ +#define GET_LOCAL_INTER_CONFIGREG_NUM(interIndex) ((unsigned int)(interIndex) >> 3) + +/** + * @brief Set local interrupt registers priority. + */ +#define SET_LOCAL_INTER_NUM_PRI(configNum, priNum, pri) do { \ + unsigned int interPriVal = READ_CUSTOM_CSR(LOCIPRI(configNum)); \ + /* clear the irqNum-th local interrupt priority */ \ + interPriVal &= (~((0xfU << (((unsigned int)(priNum) & 0x7U) << 2)) & UINT32_CUT_MASK)); \ + /* set the irqNum-th local interrupt priority */ \ + interPriVal |= ((unsigned int)(pri) << (((unsigned int)(priNum) & 0x7U) << 2)); \ + WRITE_CUSTOM_CSR_VAL(LOCIPRI(configNum), interPriVal); \ +} while (0) + +/** + * @brief Get local interrupt registers priority. + */ +#define GET_LOCAL_INTER_NUM_PRI(configNum, priNum, pri) do { \ + (pri) = READ_CUSTOM_CSR(LOCIPRI(configNum)); \ + /* Get the irqNum-th local interrupt priority */ \ + (pri) >>= (((unsigned int)(priNum) & 0x7U) << 2); \ + (pri) &= 0x7U; \ +} while (0) + +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) +/** + * @brief Riscv mode switch in user mode + */ +#define RISCV_PRIV_MODE_SWITCH(priv) do { \ + if ((priv) == RISCV_U_MODE) { \ + asm volatile ("ecall"); \ + } \ +} while (0) +#else +#define RISCV_PRIV_MODE_SWITCH(priv) (void)(0) +#endif +/** + * @} + */ + +/** + * @brief Clear external interrupt + * @param irqNum external interrupt number + * @retval BASE_STATUS_OK or IRQ_ERRNO_NUM_INVALID or IRQ_ERRNO_NOT_CREATED + */ +static inline void IRQ_ClearN(unsigned int irqNum) +{ + asm volatile("fence"); + WRITE_CUSTOM_CSR_VAL(LOCIPCLR, irqNum); +} +/** + * @defgroup INTERRUPT_STRUCTURE_DEFINITION Interrupt Structure Definition + * @brief Definition of interrupt STRUCTURE. + * @{ + */ +typedef void (* IRQ_PROC_FUNC)(void *arg); + +/** + * @brief Interrupt Handle Structure + */ +typedef struct { + IRQ_PROC_FUNC pfnHandler; + void *param; +} IRQ_ARG_FUNC; + +/** + * @brief System error context Structure + */ +typedef struct { + unsigned int ra; + unsigned int t0; + unsigned int t1; + unsigned int t2; + unsigned int a0; + unsigned int a1; + unsigned int a2; + unsigned int a3; + unsigned int a4; + unsigned int a5; + unsigned int a6; + unsigned int a7; + unsigned int t3; + unsigned int t4; + unsigned int t5; + unsigned int t6; + unsigned int s0; + unsigned int s1; + unsigned int s2; + unsigned int s3; + unsigned int s4; + unsigned int s5; + unsigned int s6; + unsigned int s7; + unsigned int s8; + unsigned int s9; + unsigned int s10; + unsigned int s11; + unsigned int sp; + unsigned int gp; + unsigned int tp; + unsigned int mepc; + unsigned int mstatus; + unsigned int mtval; + unsigned int mcause; + unsigned int ccause; +} SyserrContext; +/** + * @} + */ + +/** + * @defgroup INTERRUPT_API_DEFINITION Interrupt API + * @brief Definition of interrupt API. + * @{ + */ +unsigned int IRQ_SetPriority(unsigned int irqNum, unsigned int priority); +unsigned int IRQ_GetPriority(unsigned int irqNum, unsigned int *priority); +void IRQ_Enable(void); +void IRQ_Disable(void); +unsigned int IRQ_EnableN(unsigned int irqNum); +unsigned int IRQ_DisableN(unsigned int irqNum); +void IRQ_Init(void); +unsigned int IRQ_Register(unsigned int irqNum, IRQ_PROC_FUNC func, void *arg); +unsigned int IRQ_Unregister(unsigned int irqNum); +unsigned int IRQ_ClearAll(void); +void SysErrNmiEntry(const SyserrContext *context); +void SysErrExcEntry(const SyserrContext *context); +void InterruptEntry(unsigned int irqNum); +void SysErrPrint(const SyserrContext *context); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_INTERRUPT_H */ diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/lock.h b/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/lock.h new file mode 100644 index 0000000000000000000000000000000000000000..451ca83fd0d143803499a528936fa98156d03ebc --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/lock.h @@ -0,0 +1,83 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file lock.h + * @author MCU Driver Team + * @brief BASE module driver + * @details This file provides functions declaration of lock + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_LOCK_H +#define McuMagicTag_LOCK_H + +/* Includes ------------------------------------------------------------------ */ +#include "chipinc.h" +#include "typedefs.h" +#include "assert.h" + +/** + * @defgroup BASE BASE + * @brief BASE module. + * @{ + */ + +/** + * @defgroup LOCK Lock Definition + * @brief Definition of LOCK Definition. + * @{ + */ + +/** + * @defgroup LOCK_ENUM_DEFINITION BASE_LockStatus Definition + * @brief Definition of LOCK Definition. + * @{ + */ +/* Typedef definitions ------------------------------------------------------- */ +/** + * @brief Lock status definition + */ +typedef enum { + BASE_STATUS_UNLOCKED = 0, + BASE_STATUS_LOCKED = 1 +} BASE_LockStatus; +/** + * @} + */ + +/** + * @defgroup LOCK_API_DEFINITION Lock API + * @brief Definition of lock API Definition. + * @{ + */ +/* Exported global functions ------------------------------------------------- */ +bool BASE_FUNC_SoftwareLock(unsigned int * const addr); +void BASE_FUNC_SoftwareUnLock(unsigned int * const addr); +bool BASE_FUNC_HardwareLock(CHIP_LockType const hwIndex); +void BASE_FUNC_HardwareUnLock(CHIP_LockType const hwIndex); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_LOCK_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/reset.h b/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/reset.h new file mode 100644 index 0000000000000000000000000000000000000000..ffc144081bcfd140b9eaf597d88b4b872eeab37b --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/reset.h @@ -0,0 +1,60 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file reset.h + * @author MCU Driver Team + * @brief BASE module driver + * @details This file provides functions declaration of reset + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_RESET_H +#define McuMagicTag_RESET_H + +/* Includes ------------------------------------------------------------------ */ +#include "chipinc.h" +/** + * @defgroup BASE BASE + * @brief BASE module. + * @{ + */ + +/** + * @defgroup RESET Reset Definition + * @brief Definition of RESET Definition. + * @{ + */ + +/** + * @defgroup RESET_API_DEFINITION RESET API Definition + * @brief Definition of RESET API Definition. + * @{ + */ +/* Exported global functions ------------------------------------------------- */ +void BASE_FUNC_SoftReset(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_RESET_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/typedefs.h b/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/typedefs.h new file mode 100644 index 0000000000000000000000000000000000000000..2af04be5ad6e5248e3504be4c1e21e9e1e561546 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/base/inc/typedefs.h @@ -0,0 +1,137 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file typedefs.h + * @author MCU Driver Team + * @brief BASE module driver + * @brief This file contains generic definitions + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_TYPEDEFS_H +#define McuMagicTag_TYPEDEFS_H +/** + * @defgroup BASE BASE + * @brief BASE module. + * @{ + */ + +/** + * @defgroup TYPRDEF Typedef Definition + * @brief Definition of RESET Definition. + * @{ + */ + +/** + * @defgroup TYPEDEF_MACRO_DEFINITION TYPEDEF MACRO Definition + * @brief Definition of TYPEDEF MACRO Definition. + * @{ + */ +/* Macro definitions --------------------------------------------------------- */ +#ifndef bool +#define bool _Bool +#endif /* bool */ + +#ifndef false +#define false 0 +#endif /* false */ + +#ifndef true +#define true 1 +#endif /* true */ + +#ifndef NULL +#define NULL ((void *)0) +#endif /* NULL */ + +#ifndef FLT_EPSILON +#define FLT_EPSILON 0.000001 +#endif /* float min error definition */ + +#ifndef INT16_MAX +#define INT16_MAX 0x7FFF +#endif /* INT16_MAX */ + +#ifndef INT16_MIN +#define INT16_MIN (-0x8000) +#endif /* INT16_MIN */ + +#ifndef INT_MAX +#define INT_MAX 0x7FFFFFFF +#endif /* INT_MAX */ + +#ifndef UINT_MAX +#define UINT_MAX 0xFFFFFFFFU +#endif /* UINT_MAX */ + +#define BASE_FUNC_UNUSED(X) (void)(X) + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +#define BASE_CFG_UNSET 0x00 +#define BASE_CFG_SET 0x01 + +#define BASE_CFG_DISABLE 0x00 +#define BASE_CFG_ENABLE 0x01 + +#define RAM_CODE __attribute__((section(".text.sram"))) +#define RESERVED_DATA __attribute__((section(".reserved.data"))) + +typedef int intptr_t; +typedef unsigned int uintptr_t; +/** + * @} + */ + +/** + * @defgroup TYPEDEF_ENUM_DEFINITION TYPEDEF ENUM Definition + * @brief Definition of TYPEDEF ENUM Definition. + * @{ + */ +/** + * @brief BASE Status structures definition + */ +typedef enum { + BASE_STATUS_OK = 0x00000000U, + BASE_STATUS_ERROR = 0x00000001U, + BASE_STATUS_BUSY = 0x00000002U, + BASE_STATUS_TIMEOUT = 0x00000003U, + BASE_STATUS_NOT_SUPPORT = 0x00000004U, +} BASE_StatusType; + +/** + * @brief Indicates the status of the general state machine. The user should add the service status to this enum. + */ +typedef enum { + BASE_FSM_START, + BASE_DEFINE_FSM_END +} BASE_FSM_Status; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_TYPEDEFS_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/base/src/assert.c b/vendor/xinlingyu_92_3061M/Project/drivers/base/src/assert.c new file mode 100644 index 0000000000000000000000000000000000000000..b99ca6cad3598e4dcf75784b4c49feda472f1379 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/base/src/assert.c @@ -0,0 +1,38 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file assert.c + * @author MCU Driver Team + * @brief Provides weak Error logger function. + */ + +/* Includes ------------------------------------------------------------------ */ +#include "assert.h" +#include "typedefs.h" + +/** + * @brief Error logger function. + * @param file Pointer to the name of the file where the error occurs. + * @param line Number of the line where the error occurs. + * @retval None. + */ +__weak void AssertErrorLog(char *file, unsigned int line) +{ + /* Use only if the user apllication is not defined. */ + BASE_FUNC_UNUSED(file); + BASE_FUNC_UNUSED(line); +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/base/src/base_math.c b/vendor/xinlingyu_92_3061M/Project/drivers/base/src/base_math.c new file mode 100644 index 0000000000000000000000000000000000000000..05a2063e628d16b96df27e70a8692409bc1c0445 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/base/src/base_math.c @@ -0,0 +1,392 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file base_math.c + * @author MCU Driver Team + * @brief Provides functions about math. + */ + +/* Includes ------------------------------------------------------------------ */ +#include "base_math.h" + +/* Private macro ------------------------------------------------------------- */ +#if (BASE_MATH_SINCOS_MIDDLE_TABLE == BASE_CFG_ENABLE) +#define TRIGONOMETRIC_MAPPING_TABLE { \ + 0X0000, 0X012D, 0X01F6, 0X02BF, 0X0388, 0X0451, 0X051A, 0X05E3, \ + 0X06AC, 0X0775, 0X083D, 0X0906, 0X09CE, 0X0A97, 0X0B5F, 0X0C27, \ + 0X0CEF, 0X0DB7, 0X0E7F, 0X0F47, 0X100E, 0X10D6, 0X119D, 0X1264, \ + 0X132B, 0X13F2, 0X14B8, 0X157F, 0X1645, 0X170A, 0X17D0, 0X1896, \ + 0X195B, 0X1A20, 0X1AE4, 0X1BA9, 0X1C6D, 0X1D31, 0X1DF5, 0X1EB8, \ + 0X1F7B, 0X203E, 0X2100, 0X21C2, 0X2284, 0X2345, 0X2407, 0X24C7, \ + 0X2588, 0X2648, 0X2707, 0X27C7, 0X2886, 0X2944, 0X2A02, 0X2AC0, \ + 0X2B7D, 0X2C3A, 0X2CF7, 0X2DB3, 0X2E6E, 0X2F29, 0X2FE4, 0X309E, \ + 0X3158, 0X3211, 0X32CA, 0X3382, 0X343A, 0X34F2, 0X35A8, 0X365F, \ + 0X3714, 0X37CA, 0X387E, 0X3932, 0X39E6, 0X3A99, 0X3B4C, 0X3BFD, \ + 0X3CAF, 0X3D60, 0X3E10, 0X3EBF, 0X3F6E, 0X401D, 0X40CA, 0X4177, \ + 0X4224, 0X42D0, 0X437B, 0X4425, 0X44CF, 0X4578, 0X4621, 0X46C9, \ + 0X4770, 0X4816, 0X48BC, 0X4961, 0X4A06, 0X4AA9, 0X4B4C, 0X4BEF, \ + 0X4C90, 0X4D31, 0X4DD1, 0X4E70, 0X4F0F, 0X4FAC, 0X5049, 0X50E5, \ + 0X5181, 0X521C, 0X52B5, 0X534E, 0X53E7, 0X547E, 0X5515, 0X55AB, \ + 0X5640, 0X56D4, 0X5767, 0X57F9, 0X588B, 0X591C, 0X59AC, 0X5A3B, \ + 0X5AC9, 0X5B56, 0X5BE3, 0X5C6E, 0X5CF9, 0X5D83, 0X5E0B, 0X5E93, \ + 0X5F1A, 0X5FA0, 0X6026, 0X60AA, 0X612D, 0X61B0, 0X6231, 0X62B2, \ + 0X6331, 0X63B0, 0X642D, 0X64AA, 0X6526, 0X65A0, 0X661A, 0X6693, \ + 0X670B, 0X6782, 0X67F7, 0X686C, 0X68E0, 0X6953, 0X69C4, 0X6A35, \ + 0X6AA5, 0X6B13, 0X6B81, 0X6BEE, 0X6C59, 0X6CC4, 0X6D2D, 0X6D96, \ + 0X6DFD, 0X6E63, 0X6EC9, 0X6F2D, 0X6F90, 0X6FF2, 0X7053, 0X70B3, \ + 0X7112, 0X716F, 0X71CC, 0X7227, 0X7282, 0X72DB, 0X7333, 0X738A, \ + 0X73E0, 0X7435, 0X7489, 0X74DB, 0X752D, 0X757D, 0X75CC, 0X761B, \ + 0X7668, 0X76B3, 0X76FE, 0X7747, 0X7790, 0X77D7, 0X781D, 0X7862, \ + 0X78A6, 0X78E8, 0X792A, 0X796A, 0X79A9, 0X79E7, 0X7A24, 0X7A5F, \ + 0X7A9A, 0X7AD3, 0X7B0B, 0X7B42, 0X7B77, 0X7BAC, 0X7BDF, 0X7C11, \ + 0X7C42, 0X7C71, 0X7CA0, 0X7CCD, 0X7CF9, 0X7D24, 0X7D4E, 0X7D76, \ + 0X7D9D, 0X7DC3, 0X7DE8, 0X7E0C, 0X7E2E, 0X7E4F, 0X7E6F, 0X7E8E, \ + 0X7EAB, 0X7EC8, 0X7EE3, 0X7EFD, 0X7F15, 0X7F2D, 0X7F43, 0X7F58, \ + 0X7F6B, 0X7F7E, 0X7F8F, 0X7F9F, 0X7FAE, 0X7FBC, 0X7FC8, 0X7FD3, \ + 0X7FDD, 0X7FE5, 0X7FED, 0X7FF3, 0X7FF8, 0X7FFC, 0X7FFE, 0X7FFF } +#elif (BASE_MATH_SINCOS_MIDDLE_TABLE == BASE_CFG_DISABLE) +#define TRIGONOMETRIC_MAPPING_TABLE { \ + 0x0000, 0x00C9, 0x0192, 0x025B, 0x0324, 0x03ED, 0x04B6, 0x057F, \ + 0x0647, 0x0710, 0x07D9, 0x08A2, 0x096A, 0x0A33, 0x0AFB, 0x0BC3, \ + 0x0C8B, 0x0D53, 0x0E1B, 0x0EE3, 0x0FAB, 0x1072, 0x1139, 0x1201, \ + 0x12C8, 0x138E, 0x1455, 0x151B, 0x15E2, 0x16A8, 0x176D, 0x1833, \ + 0x18F8, 0x19BD, 0x1A82, 0x1B47, 0x1C0B, 0x1CCF, 0x1D93, 0x1E56, \ + 0x1F19, 0x1FDC, 0x209F, 0x2161, 0x2223, 0x22E5, 0x23A6, 0x2467, \ + 0x2528, 0x25E8, 0x26A8, 0x2767, 0x2826, 0x28E5, 0x29A3, 0x2A61, \ + 0x2B1F, 0x2BDC, 0x2C98, 0x2D55, 0x2E11, 0x2ECC, 0x2F87, 0x3041, \ + 0x30FB, 0x31B5, 0x326E, 0x3326, 0x33DE, 0x3496, 0x354D, 0x3604, \ + 0x36BA, 0x376F, 0x3824, 0x38D8, 0x398C, 0x3A40, 0x3AF2, 0x3BA5, \ + 0x3C56, 0x3D07, 0x3DB8, 0x3E68, 0x3F17, 0x3FC5, 0x4073, 0x4121, \ + 0x41CE, 0x427A, 0x4325, 0x43D0, 0x447A, 0x4524, 0x45CD, 0x4675, \ + 0x471C, 0x47C3, 0x4869, 0x490F, 0x49B4, 0x4A58, 0x4AFB, 0x4B9E, \ + 0x4C3F, 0x4CE1, 0x4D81, 0x4E21, 0x4EBF, 0x4F5E, 0x4FFB, 0x5097, \ + 0x5133, 0x51CE, 0x5269, 0x5302, 0x539B, 0x5433, 0x54CA, 0x5560, \ + 0x55F5, 0x568A, 0x571D, 0x57B0, 0x5842, 0x58D4, 0x5964, 0x59F3, \ + 0x5A82, 0x5B10, 0x5B9D, 0x5C29, 0x5CB4, 0x5D3E, 0x5DC7, 0x5E50, \ + 0x5ED7, 0x5F5E, 0x5FE3, 0x6068, 0x60EC, 0x616F, 0x61F1, 0x6271, \ + 0x62F2, 0x6371, 0x63EF, 0x646C, 0x64E8, 0x6563, 0x65DD, 0x6657, \ + 0x66CF, 0x6746, 0x67BD, 0x6832, 0x68A6, 0x6919, 0x698C, 0x69FD, \ + 0x6A6D, 0x6ADC, 0x6B4A, 0x6BB8, 0x6C24, 0x6C8F, 0x6CF9, 0x6D62, \ + 0x6DCA, 0x6E30, 0x6E96, 0x6EFB, 0x6F5F, 0x6FC1, 0x7023, 0x7083, \ + 0x70E2, 0x7141, 0x719E, 0x71FA, 0x7255, 0x72AF, 0x7307, 0x735F, \ + 0x73B5, 0x740B, 0x745F, 0x74B2, 0x7504, 0x7555, 0x75A5, 0x75F4, \ + 0x7641, 0x768E, 0x76D9, 0x7723, 0x776C, 0x77B4, 0x77FA, 0x7840, \ + 0x7884, 0x78C7, 0x7909, 0x794A, 0x798A, 0x79C8, 0x7A05, 0x7A42, \ + 0x7A7D, 0x7AB6, 0x7AEF, 0x7B26, 0x7B5D, 0x7B92, 0x7BC5, 0x7BF8, \ + 0x7C29, 0x7C5A, 0x7C89, 0x7CB7, 0x7CE3, 0x7D0F, 0x7D39, 0x7D62, \ + 0x7D8A, 0x7DB0, 0x7DD6, 0x7DFA, 0x7E1D, 0x7E3F, 0x7E5F, 0x7E7F, \ + 0x7E9D, 0x7EBA, 0x7ED5, 0x7EF0, 0x7F09, 0x7F21, 0x7F38, 0x7F4D, \ + 0x7F62, 0x7F75, 0x7F87, 0x7F97, 0x7FA7, 0x7FB5, 0x7FC2, 0x7FCE, \ + 0x7FD8, 0x7FE1, 0x7FE9, 0x7FF0, 0x7FF6, 0x7FFA, 0x7FFD, 0x7FFF } +#endif + +#define BASE_MATH_SIN_COS_MASK 0x0300u /**< All mask values of sincos */ +#define BASE_MATH_ANGLED0_90 0x0200u /**< Mask value of sincos ranging from 0 to 90 degrees */ +#define BASE_MATH_ANGLED90_180 0x0300u /**< Mask value of sincos ranging from 90 to 180 degrees */ +#define BASE_MATH_ANGLED180_270 0x0000u /**< Mask value of sincos ranging from 180 to 270 degrees */ +#define BASE_MATH_ANGLED270_360 0x0100u /**< Mask value of sincos ranging from 270 to 360 degrees */ +#define BASE_MATH_PAI 3.141592653 +#define BASE_MATH_FACTORIAL3_RECIPROCAL 0.166666667 /**< 1/6. */ +#define BASE_MATH_FACTORIAL5_RECIPROCAL 0.008333333 /**< 1/120. */ +#define BASE_MATH_FACTORIAL7_RECIPROCAL 0.000198413 /**< 1/5040. */ +#define BASE_MATH_ANGLE90 90 +#define BASE_MATH_ANGLE180 180 +#define BASE_MATH_ANGLE180_RECIPROCAL 0.005555556 /**< 1/180. */ +#define BASE_MATH_ANGLE270 270 +#define BASE_MATH_ANGLE360 360 + +#define BASE_DEFINE_MAPPING_TABLE_SIZE 255 +/** Value to be added to convert a signed 16-bit value to an unsigned 16-bit value. */ +#define BASE_DEFINE_INT16_ADDITIONS_VAL 32768 + +#define BASE_DEFINE_DIV_SQRT3 (int)0x49E6 /**< 1/sqrt(3) = 0.5773315 in q15 format. */ + +/* Private variables --------------------------------------------------------- */ +const short g_triFunMappingTable[] = TRIGONOMETRIC_MAPPING_TABLE; /**< trigonometric look-up table. */ + +/** + * @brief Calculate the value of the input angle by looking up the table. Data in Q15 format. + * @param angle: Angle value to be calculated. + * @retval Calculation result in BASE_MathTypeSinCos Structure. + */ +BASE_MathTypeSinCos BASE_MATH_GetSinCos(short angle) +{ + BASE_MathTypeSinCos ret = {0}; + unsigned short uhindex; + + /* Move the zero to ensure that the mapping result is positive. */ + uhindex = (unsigned short)((int)BASE_DEFINE_INT16_ADDITIONS_VAL + (int)angle); + + /* Shift right by 6 bits. */ + uhindex /= (unsigned short)64; /* 64:Reserved 10-bit precision. */ + + switch ((unsigned short)(uhindex) & BASE_MATH_SIN_COS_MASK) { + case BASE_MATH_ANGLED0_90: /* 0 ~ 90° */ + ret.sin = g_triFunMappingTable[(unsigned char)(uhindex)]; + ret.cos = g_triFunMappingTable[(unsigned char)(BASE_DEFINE_MAPPING_TABLE_SIZE - (unsigned char)(uhindex))]; + break; + + case BASE_MATH_ANGLED90_180: /* 90 ~ 180° */ + ret.sin = g_triFunMappingTable[(unsigned char)(BASE_DEFINE_MAPPING_TABLE_SIZE - (unsigned char)(uhindex))]; + ret.cos = -g_triFunMappingTable[(unsigned char)(uhindex)]; + break; + + case BASE_MATH_ANGLED180_270: /* 180 ~ 270° */ + ret.sin = -g_triFunMappingTable[(unsigned char)(uhindex)]; + ret.cos = -g_triFunMappingTable[(unsigned char)(BASE_DEFINE_MAPPING_TABLE_SIZE - (unsigned char)(uhindex))]; + break; + + case BASE_MATH_ANGLED270_360: /* 270 ~ 360° */ + ret.sin = -g_triFunMappingTable[(unsigned char)(BASE_DEFINE_MAPPING_TABLE_SIZE - (unsigned char)(uhindex))]; + ret.cos = g_triFunMappingTable[(unsigned char)(uhindex)]; + break; + + default: + break; + } + + return ret; +} + +/** + * @brief Using Taylor Expansion to Calculate Sin Values in 90 Degrees. + * @param angle Angle value to be calculated. Note: 0 <= angle <= 90. + * @retval float Calculated sin value. + */ +static float BASE_MATH_CalSinIn90(float angle) +{ + float radian = angle * BASE_MATH_PAI * BASE_MATH_ANGLE180_RECIPROCAL; + float radian3 = radian * radian * radian; /* power(3) */ + float radian5 = radian3 * radian * radian; + float radian7 = radian5 * radian * radian; /* power(7) */ + /* Using Taylor Expansion to Calculate Sin Values in 90 Degrees. */ + return (radian - radian3 * BASE_MATH_FACTORIAL3_RECIPROCAL + radian5 * BASE_MATH_FACTORIAL5_RECIPROCAL \ + - radian7 * BASE_MATH_FACTORIAL7_RECIPROCAL); +} + +/** + * @brief Using Taylor Expansion to Calculate Sin Values for Any Angle. + * @param angle Angle value to be calculated. + * @retval float Calculated sin value. + */ +float BASE_MATH_GetSin(float angle) +{ + float angleIn360; + angleIn360 = (int)angle % BASE_MATH_ANGLE360 + angle - (int)angle; + if (angleIn360 < 0) { + angleIn360 = angleIn360 + BASE_MATH_ANGLE360; + } + if (angleIn360 < BASE_MATH_ANGLE90) { /* 0 ~ 90° */ + return BASE_MATH_CalSinIn90(angleIn360); + } + if (angleIn360 < BASE_MATH_ANGLE180) { /* 90 ~ 180° */ + return BASE_MATH_CalSinIn90(BASE_MATH_ANGLE180 - angleIn360); + } + if (angleIn360 < BASE_MATH_ANGLE270) { /* 180 ~ 270° */ + return -BASE_MATH_CalSinIn90(angleIn360 - BASE_MATH_ANGLE180); + } + return -BASE_MATH_CalSinIn90(BASE_MATH_ANGLE360 - angleIn360); /* 270 ~ 360° */ +} + +/** + * @brief Using Taylor Expansion to Calculate Sin Values for Any Angle. + * @param angle Angle value to be calculated. + * @retval float Calculated sin value. + */ +float BASE_MATH_GetCos(float angle) +{ + float angleIn360; + angleIn360 = (int)angle % BASE_MATH_ANGLE360 + angle - (int)angle; + if (angleIn360 < 0) { + angleIn360 = angleIn360 + BASE_MATH_ANGLE360; + } + if (angleIn360 < BASE_MATH_ANGLE90) { /* 0 ~ 90° */ + return BASE_MATH_CalSinIn90(BASE_MATH_ANGLE90 - angleIn360); + } + if (angleIn360 < BASE_MATH_ANGLE180) { /* 90 ~ 180° */ + return -BASE_MATH_CalSinIn90(angleIn360 - BASE_MATH_ANGLE90); + } + if (angleIn360 < BASE_MATH_ANGLE270) { /* 180 ~ 270° */ + return -BASE_MATH_CalSinIn90(BASE_MATH_ANGLE270 - angleIn360); + } + return BASE_MATH_CalSinIn90(angleIn360 - BASE_MATH_ANGLE270); /* 270 ~ 360° */ +} + +/** + * @brief Using newton iteration method to realize sqrt. + * @param x Value to be squared. + * @retval float Value after square. + */ +float BASE_MATH_Sqrt(const float x) +{ + BASE_FUNC_ASSERT_PARAM(x >= FLT_EPSILON); + const float xHalf = 0.5f * x; /* 0.5f : coefficients. */ + + union { + float x; + unsigned int i; + } u; + u.x = x; + u.i = 0x5f3759df - (u.i >> 1); /* 0x5f3759df : Magic numbers for sqrt. */ + return x * u.x * (1.5f - xHalf * u.x * u.x); /* 1.5f : coefficients. */ +} + +/** + * @brief Compute x to the n power. + * @param x Cardinality to be calculated. + * @param n Power exponent to be calculated. + * @retval float Calculated value. + */ +float BASE_MATH_Pow(float x, int n) +{ + /* check x not equal zero */ + if (x > -FLT_EPSILON && x < FLT_EPSILON) { + return 0.0f; + } + float value = x; + int power = n; + float res = 1.0; + if (power < 0) { + value = 1 / value; + power = -power; + } + /* power multiplication */ + for (unsigned int i = 0; i < (unsigned int)power; ++i) { + res *= value; + } + return res; +} + +/** + * @brief This function performs Clarke conversion. Data in Q15 format. The conversion formula is as follows: + * alpha = a; + * beta = 1 / sqrt3 * a + 2 / sqrt3 *b. + * @param input Current values of a\b items. + * @retval BASE_MathTypeAlphaBeta Conversion result in BASE_MathTypeAlphaBeta Structure. + */ +BASE_MathTypeAlphaBeta BASE_MATH_Clarke(BASE_MathTypeAB input) +{ + BASE_MathTypeAlphaBeta ret; + int aDivSort3, bDivSort3, betaTmp32; + + /* qIalpha = qIas. */ + ret.alpha = input.a; + + aDivSort3 = BASE_DEFINE_DIV_SQRT3 * (int)input.a; + + bDivSort3 = BASE_DEFINE_DIV_SQRT3 * (int)input.b; + + /* qIbeta = (2*qIbs+qIas)/sqrt(3). */ + /* Because BASE_DEFINE_DIV_SQRT3 is in the Q15 format, divide it by 32768 to ensure that the result is correct. */ + betaTmp32 = (aDivSort3 + bDivSort3 + bDivSort3) >> 15; /* 15:Move 15 bits to the right, keep Q15 format. */ + + /* Check saturation of Ibeta */ + if (betaTmp32 > INT16_MAX) { + ret.beta = INT16_MAX; + } else if (betaTmp32 < INT16_MIN) { + ret.beta = INT16_MIN; + } else { + ret.beta = (short)(betaTmp32); + } + + return ret; +} + +/** + * @brief This function performs Park coordinate conversion. Data in Q15 format. The conversion formula is as follows: + * id = alpha * cos(theta) + beta * sin(theta); + * iq = -alpha * sin(theta) + beta * cos(theta). + * @param input stator values alpha and beta in BASE_MathTypeAlphaBeta format. + * @param theta rotating frame angular position. + * @retval BASE_MathTypeQD Conversion result in BASE_MathTypeQD Structure. + */ +BASE_MathTypeQD BASE_MATH_Park(BASE_MathTypeAlphaBeta input, short theta) +{ + BASE_MathTypeQD ret; + BASE_MathTypeSinCos thetaSinCos; + int d1, d2, q1, q2, tmp32; + + thetaSinCos = BASE_MATH_GetSinCos(theta); + + /* No overflow guaranteed. */ + d1 = input.alpha * (int)thetaSinCos.cos; + + /* No overflow guaranteed. */ + d2 = input.beta * (int)thetaSinCos.sin; + + /* Id component in Q1.15 Format. */ + tmp32 = (d1 + d2) >> 15; /* 15:Move 15 bits to the right, keep Q15 format. */ + + /* Check saturation of Id. */ + if (tmp32 > INT16_MAX) { + ret.d = INT16_MAX; + } else if (tmp32 < INT16_MIN) { + ret.d = INT16_MIN; + } else { + ret.d = (short)(tmp32); + } + + /* No overflow guaranteed. */ + q1 = input.alpha * (int)thetaSinCos.sin; + + /* No overflow guaranteed. */ + q2 = input.beta * (int)thetaSinCos.cos; + + /* Iq component in Q1.15 Format. */ + tmp32 = (q2 - q1) >> 15; /* 15:Move 15 bits to the right, keep Q15 format. */ + + /* Check saturation of Iq. */ + if (tmp32 > INT16_MAX) { + ret.q = INT16_MAX; + } else if (tmp32 < INT16_MIN) { + ret.q = INT16_MIN; + } else { + ret.q = (short)(tmp32); + } + + return ret; +} + +/** + * @brief This function performs Reverse Park coordinate conversion. Data in Q15 format. The conversion formula is as + * follows: alpha = d * cos(theta) - q * sin(theta); + * beta = d * sin(theta) + q * cos(theta). + * @param input stator voltage Vq and Vd in BASE_MathTypeQD format. + * @param theta rotating frame angular position. + * @retval BASE_MathTypeAlphaBeta Conversion result in BASE_MathTypeAlphaBeta Structure. + */ +BASE_MathTypeAlphaBeta BASE_MATH_RevPark(BASE_MathTypeQD input, short theta) +{ + int alpha1, alpha2, beta1, beta2; + BASE_MathTypeSinCos thetaSinCos; + BASE_MathTypeAlphaBeta ret; + + thetaSinCos = BASE_MATH_GetSinCos(theta); + + /* No overflow guaranteed. */ + alpha1 = input.q * (int)thetaSinCos.sin; + alpha2 = input.d * (int)thetaSinCos.cos; + + ret.alpha = (short)((alpha2 - alpha1) >> 15); /* 15:Move 15 bits to the right, keep Q15 format. */ + + beta1 = input.q * (int)thetaSinCos.cos; + beta2 = input.d * (int)thetaSinCos.sin; + + ret.beta = (short)((beta1 + beta2) >> 15); /* 15:Move 15 bits to the right, keep Q15 format. */ + + return ret; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/base/src/clock.c b/vendor/xinlingyu_92_3061M/Project/drivers/base/src/clock.c new file mode 100644 index 0000000000000000000000000000000000000000..5a3641258b33b055ced05dea17d3e98d414711f4 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/base/src/clock.c @@ -0,0 +1,103 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file clock.c + * @author MCU Driver Team + * @brief Provides functions related to the dominant frequency operation and delay. + */ + +/* Includes ------------------------------------------------------------------ */ +#include "ip_crg_common.h" +#include "crg.h" +#include "clock.h" + +/** + * @brief Get the current CPU frequency. + * @param None. + * @retval System clock frequency in Hz. + */ +unsigned int BASE_FUNC_GetCpuFreqHz(void) +{ + return HAL_CRG_GetCoreClkFreq(); +} + +/** + * @brief Delay number of us. + * @param us The number of us to delay. + * @retval None. + */ +void BASE_FUNC_DelayUs(unsigned int us) +{ + unsigned int preTick = DCL_SYSTICK_GetTick(); + unsigned int tickInUs = (SYSTICK_GetCRGHZ() / CRG_FREQ_1MHz) * us; + unsigned int curTick; + unsigned int delta; + + /* Wait until the delta is greater than tickInUs */ + do { + curTick = DCL_SYSTICK_GetTick(); + delta = (curTick >= preTick) ? curTick - preTick : SYSTICK_MAX_VALUE - preTick + curTick + 1; + } while (delta < tickInUs); +} + +/** + * @brief Delay number of ms. + * @param ms The number of ms to delay. + * @retval None. + */ +void BASE_FUNC_DelayMs(unsigned int ms) +{ + for (unsigned int i = 0; i < ms; ++i) { + BASE_FUNC_DelayUs(BASE_DEFINE_DELAY_US_IN_MS); + } +} + +/** + * @brief Delay number of seconds. + * @param seconds The number of seconds to delay. + * @retval None. + */ +void BASE_FUNC_DelaySeconds(unsigned int seconds) +{ + for (unsigned int i = 0; i < seconds; ++i) { + BASE_FUNC_DelayMs(BASE_DEFINE_DELAY_MS_IN_SEC); + } +} + +/** + * @brief Delay for a certain period of time based on parameters delay and units. + * @param delay The number of 'units' to delay. + * @param units Specifies the delay unit. + * @retval None. + */ +void BASE_FUNC_Delay(unsigned int delay, BASE_DelayUnit units) +{ + switch (units) { + case BASE_DEFINE_DELAY_SECS: + BASE_FUNC_DelaySeconds(delay); + break; + case BASE_DEFINE_DELAY_MILLISECS: + BASE_FUNC_DelayMs(delay); + break; + case BASE_DEFINE_DELAY_MICROSECS: + BASE_FUNC_DelayUs(delay); + break; + default: + break; + } + return; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/base/src/generalfunc.c b/vendor/xinlingyu_92_3061M/Project/drivers/base/src/generalfunc.c new file mode 100644 index 0000000000000000000000000000000000000000..91c2d2fc2ab38218af936aa99e53618748561738 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/base/src/generalfunc.c @@ -0,0 +1,223 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file basic.c + * @author MCU Driver Team + * @brief BASE module driver + * @details This file provides firmware functions to manage the following + * functionalities of the basic functions. + * + Verifying the timeout function + * + 8-bit, 16-bit checksum function + * + Sliding averaging function + * + General state machine + * @verbatim + * Sliding averaging interface usage: + * 1) Call the BASE_FUNC_AverageInit() function to initialize and configure the buffer, + * average the window size, and set the index value for identification. + * 2) Call the BASE_FUNC_GetSlipAverageVal() function based on the index value transferred + * in the initialization function to obtain the average value of the current window. + * 3) Call the BASE_FUNC_AverageDeInit() function to close the current index channel. + * + * General state machine usage: + * 1) Add your status to enum BASE_FSM_Status; + * 2) Write your code for each state. Note that the function prototype is BASE_FSM_Status xxx(void); + * 3) Use BASE_FSM_FunRegister() to register your functions and their status; + * 4) Start the state machine using BASE_FSM_Run(). + * @endverbatim + */ + +/* Includes ------------------------------------------------------------------ */ +#include "generalfunc.h" + +/* Private variables --------------------------------------------------------- */ +BASE_AverageHandle g_averageHandle[BASE_DEFINE_SLIPAVERAGE_NUM]; +BASE_FSM_Handle g_fsmHandle; + +/** + * @brief Obtains the current tick value. + * @retval unsigned int. Current tick value. + */ +unsigned int BASE_FUNC_GetTick(void) +{ + return DCL_SYSTICK_GetTick(); +} + +/** + * @brief Query an element in an array using dichotomous lookup. Note: Arrays are sorted in ascending order. + * Returns the left index when the array element does not exist. + * @param nums Array to be searched. + * @param leng Array Length. + * @param value Value to be searched for. + * @return unsigned int Index value corresponding to value. + */ +unsigned int BASE_FUNC_FindArrayValue(const unsigned short *nums, unsigned int leng, unsigned int value) +{ + BASE_FUNC_ASSERT_PARAM(nums != NULL); + BASE_FUNC_PARAMCHECK_WITH_RET(leng > 0, 0); + unsigned int left = 0; + unsigned int right = leng - 1; + while (left < right) { + unsigned int mid = (left + right) / 2; + if (value >= nums[mid] && value < nums[mid + 1]) { + return mid; + } else if (value < nums[mid]) { + right = mid - 1; + } else { + left = mid + 1; + } + } + return left; +} + +/** + * @brief 8-bit checksum. + * @param pt Pointer to the data to be computed. + * @param len Data length. + * @return unsigned char Calculation result. + */ +unsigned char BASE_FUNC_CalcSumByte(const unsigned char *pt, unsigned int len) +{ + BASE_FUNC_ASSERT_PARAM(pt != NULL); + BASE_FUNC_PARAMCHECK_WITH_RET((len > 0), 0); + + unsigned int sum = 0; + /* calculate sum value */ + while (len--) { + sum += *pt; + pt++; + } + /* Use 8 digits */ + return (unsigned char)sum; +} + +/** + * @brief 16-bit checksum. + * @param pt Pointer to the data to be computed. + * @param len Data length. + * @return unsigned char Calculation result. + */ +unsigned short BASE_FUNC_CalcSumShort(unsigned char const * pt, unsigned int len) +{ + BASE_FUNC_ASSERT_PARAM(pt != NULL); + BASE_FUNC_PARAMCHECK_WITH_RET((len > 0), 0); + unsigned int sum = 0; + /* calculate sum value */ + while (len--) { + sum += *pt; + pt++; + } + /* Use 16 digits */ + return (unsigned short)sum; +} + +/** + * @brief Sliding average initialization function. + * @param index User-entered index value used to identify the channel, in [0, BASE_DEFINE_SLIPAVERAGE_NUM). + * @param buf Pointer to the ring buffer, it stores historical data. + * @param size Ring buffer size. + * @param calNum Indicates the average window size, that is, the number of pieces of data to be averaged. + * @return BASE_StatusType @ref BASE_StatusType. + */ +BASE_StatusType BASE_FUNC_AverageInit(unsigned int index, float *buf, unsigned int size, unsigned int calNum) +{ + /* verify param */ + BASE_FUNC_ASSERT_PARAM(buf != NULL); + BASE_FUNC_PARAMCHECK_WITH_RET((calNum > 0), BASE_STATUS_ERROR); + BASE_FUNC_PARAMCHECK_WITH_RET((size >= calNum), BASE_STATUS_ERROR); + BASE_FUNC_PARAMCHECK_WITH_RET((index < BASE_DEFINE_SLIPAVERAGE_NUM), BASE_STATUS_ERROR); + /* init handle's member */ + g_averageHandle[index].buf = buf; + g_averageHandle[index].size = size; + g_averageHandle[index].at = 0; + g_averageHandle[index].calNum = calNum; + g_averageHandle[index].total = 0; + g_averageHandle[index].cnt = 0; + + return BASE_STATUS_OK; +} + +/** + * @brief Transfer new data and return the average value after the new data is inserted. + * @param index Index value of the handle array, which is set by the user in the initialization function. + * @param val Data value. + * @return float Calculated average. + */ +float BASE_FUNC_GetSlipAverageVal(unsigned int index, float val) +{ + /* verify param */ + BASE_FUNC_ASSERT_PARAM(index < BASE_DEFINE_SLIPAVERAGE_NUM); + /* The processing data volume does not reach the constant average amount. */ + if (g_averageHandle[index].cnt < g_averageHandle[index].calNum) { + (g_averageHandle[index].cnt)++; + g_averageHandle[index].total += val; + g_averageHandle[index].buf[g_averageHandle[index].at] = val; + (g_averageHandle[index].at)++; + return g_averageHandle[index].total / g_averageHandle[index].cnt; /* g_averageHandle[index].cnt > 0 */ + } + /* The processing data volume reach the constant average amount. */ + g_averageHandle[index].total += val - g_averageHandle[index].buf[(g_averageHandle[index].at + \ + g_averageHandle[index].size - g_averageHandle[index].calNum) % \ + g_averageHandle[index].size]; + g_averageHandle[index].buf[g_averageHandle[index].at] = val; + g_averageHandle[index].at = (g_averageHandle[index].at + 1) % g_averageHandle[index].size; + return g_averageHandle[index].total / g_averageHandle[index].calNum; /* g_averageHandle[index].calNum > 0 */ +} + +/** + * @brief Disables the channel specified by index. + * @param index Index value of the handle array, which is set by the user in the initialization function. + * @return None. + */ +void BASE_FUNC_AverageDeInit(unsigned int index) +{ + /* verify param */ + BASE_FUNC_ASSERT_PARAM(index < BASE_DEFINE_SLIPAVERAGE_NUM); + g_averageHandle[index].buf = NULL; +} + +/** + * @brief Registering functions to the state machine. Note that the function prototype is BASE_FSM_Status xxx(void). + * @param index Status of the function. + * @param funAddress Function Pointer. + * @return None. + */ +void BASE_FSM_FunRegister(BASE_FSM_Status index, FunType funAddress) +{ + BASE_FUNC_PARAMCHECK_NO_RET(index >= BASE_FSM_START && index <= BASE_DEFINE_FSM_END); + g_fsmHandle.funList[index] = funAddress; +} + +/** + * @brief Start the state machine. + * @param delayTime State switching delay time. + * @param delayUnit Indicates the unit of the state switch delay. + * @return None. + */ +void BASE_FSM_Run(unsigned int delayTime, BASE_DelayUnit delayUnit) +{ + g_fsmHandle.nextFun = BASE_FSM_START; + + FunType execFun; + while (1) { + execFun = g_fsmHandle.funList[g_fsmHandle.nextFun]; + g_fsmHandle.nextFun = execFun(); + if (g_fsmHandle.nextFun < BASE_FSM_START || g_fsmHandle.nextFun > BASE_DEFINE_FSM_END) { + break; + } + BASE_FUNC_Delay(delayTime, delayUnit); + } +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/base/src/interrupt.c b/vendor/xinlingyu_92_3061M/Project/drivers/base/src/interrupt.c new file mode 100644 index 0000000000000000000000000000000000000000..c85e5fc1b270c78920d3b3a3d9da1bf5a1029733 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/base/src/interrupt.c @@ -0,0 +1,555 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file interrupt.c + * @author MCU Driver Team + * @brief Provides the handle template functions for processing exceptions and interrupts supported by the current + * functionalities of the interrupt. + * + Initialization and de-initialization functions + * + Regester and de-regester interrupt + * + Enable and disable interrupt + * + Configure interrupt + */ + +/* Includes ------------------------------------------------------------------ */ +#include "interrupt.h" +#include "baseinc.h" + +/* Macro definitions ---------------------------------------------------------*/ + +/* Typedef definitions -------------------------------------------------------*/ +void IRQ_PriorityInit(void); +static void IRQ_DummyHandler(void *arg); +static void IRQ_SetCallBack(unsigned int irqNum, IRQ_PROC_FUNC func, void *arg); + +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) +static inline unsigned int IRQ_GetCpuPrivilege(void); + +static struct IRQ_Mask { + unsigned int irqMie; + unsigned int irqLocien0; + unsigned int irqLocien1; + unsigned int irqLocien2; + unsigned int irqLocien3; +} g_irqMask; + +volatile unsigned int g_RiscvPrivMode = 0; +#endif + +/** + * @brief Interrupt vector table, supports up to IRQ_MAX interrupts, except for IRQ_VECTOR_CNT internal + * standard interrupts, which can be configured according to actual conditions. + */ +IRQ_ARG_FUNC g_irqCallbackFunc[IRQ_MAX]; + +/* Initialization and de-initialization functions ----------------------------*/ +/** + * @brief Exception/Interrupt Handler Entry. + * @param irqNum external interrupt number. + * @retval None + */ +void InterruptEntry(unsigned int irqNum) +{ + g_irqCallbackFunc[irqNum].pfnHandler(g_irqCallbackFunc[irqNum].param); + IRQ_ClearN(irqNum); +} + +/** + * @brief Irq initialization. + * @param none. + * @retval None + */ +void IRQ_Init(void) +{ + unsigned int index; + + for (index = 0; index < IRQ_MAX; index++) { + g_irqCallbackFunc[index].pfnHandler = IRQ_DummyHandler; + g_irqCallbackFunc[index].param = NULL; + } +} + +/* Register and Unregister interrupt -----------------------------------------*/ +/** + * @brief Register IRQ Callback function and parameter. + * @param irqNum External interrupt number. + * @param func Callback function. + * @param arg Parameter of callback function. + * @retval BASE_STATUS_OK(success) or IRQ_ERRNO_ALREADY_CREATED(fail) or IRQ_ERRNO_NUM_INVALID. + * @note In the corresponding interrupt handler, manually clear the interrupt source and the corresponding interrupt + * flag bit (call the IRQ_ClearN function to clear the interrupt), otherwise the interrupt will always be + * triggered. + */ +unsigned int IRQ_Register(unsigned int irqNum, IRQ_PROC_FUNC func, void *arg) +{ + INTERRUPT_ASSERT_PARAM(func != NULL); + INTERRUPT_PARAM_CHECK_WITH_RET(irqNum < IRQ_MAX, IRQ_ERRNO_NUM_INVALID); + + if (g_irqCallbackFunc[irqNum].pfnHandler != IRQ_DummyHandler) { + return IRQ_ERRNO_ALREADY_CREATED; + } + IRQ_SetCallBack(irqNum, func, arg); + return BASE_STATUS_OK; +} + +/** + * @brief Unregister IRQ Callback. + * @param irqNum External interrupt number. + * @retval BASE_STATUS_OK or IRQ_ERRNO_NUM_INVALID. + */ +unsigned int IRQ_Unregister(unsigned int irqNum) +{ + INTERRUPT_PARAM_CHECK_WITH_RET(irqNum < IRQ_MAX, IRQ_ERRNO_NUM_INVALID); + g_irqCallbackFunc[irqNum].pfnHandler = IRQ_DummyHandler; + g_irqCallbackFunc[irqNum].param = NULL; + return BASE_STATUS_OK; +} + +/* Enable and disable interrupt ----------------------------------------------*/ +/** + * @brief Global Interrupt Enable. + * @retval None. + */ +void IRQ_Enable(void) +{ +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + unsigned int priv = IRQ_GetCpuPrivilege(); + + RISCV_PRIV_MODE_SWITCH(priv); + + g_irqMask.irqMie |= READ_CSR(mie); + g_irqMask.irqLocien0 |= READ_CUSTOM_CSR(LOCIEN0); + g_irqMask.irqLocien1 |= READ_CUSTOM_CSR(LOCIEN1); + g_irqMask.irqLocien2 |= READ_CUSTOM_CSR(LOCIEN2); + g_irqMask.irqLocien3 |= READ_CUSTOM_CSR(LOCIEN3); + + WRITE_CSR(mie, g_irqMask.irqMie); + WRITE_CUSTOM_CSR_VAL(LOCIEN0, g_irqMask.irqLocien0); + WRITE_CUSTOM_CSR_VAL(LOCIEN1, g_irqMask.irqLocien1); + WRITE_CUSTOM_CSR_VAL(LOCIEN2, g_irqMask.irqLocien2); + WRITE_CUSTOM_CSR_VAL(LOCIEN3, g_irqMask.irqLocien3); + + RISCV_PRIV_MODE_SWITCH(priv); +#else + SET_CSR(mstatus, MSTATUS_MIE); +#endif +} + +/** + * @brief Global Interrupt Disable. + * @retval BASE_STATUS_OK. + * @note Must be called in Interrupt(Machine mode) + */ +void IRQ_Disable(void) +{ +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + unsigned int priv = IRQ_GetCpuPrivilege(); + + RISCV_PRIV_MODE_SWITCH(priv); + + g_irqMask.irqMie = READ_CSR(mie); + g_irqMask.irqLocien0 = READ_CUSTOM_CSR(LOCIEN0); + g_irqMask.irqLocien1 = READ_CUSTOM_CSR(LOCIEN1); + g_irqMask.irqLocien2 = READ_CUSTOM_CSR(LOCIEN2); + g_irqMask.irqLocien3 = READ_CUSTOM_CSR(LOCIEN3); + + WRITE_CSR(mie, 0); + WRITE_CUSTOM_CSR_VAL(LOCIEN0, 0); + WRITE_CUSTOM_CSR_VAL(LOCIEN1, 0); + WRITE_CUSTOM_CSR_VAL(LOCIEN2, 0); + WRITE_CUSTOM_CSR_VAL(LOCIEN3, 0); + + RISCV_PRIV_MODE_SWITCH(priv); +#else + CLEAR_CSR(mstatus, MSTATUS_MIE | MSTATUS_MPIE); +#endif +} + +/** + * @brief Enable the specified interrupt. + * @param irqNum External interrupt number. + * @retval BASE_STATUS_OK or IRQ_ERRNO_NUM_INVALID. + */ +unsigned int IRQ_EnableN(unsigned int irqNum) +{ + unsigned int irqOrder; + unsigned int locienVal; +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + unsigned int priv = IRQ_GetCpuPrivilege(); +#endif + + INTERRUPT_PARAM_CHECK_WITH_RET((irqNum >= IRQ_VECTOR_CNT && irqNum < IRQ_MAX), IRQ_ERRNO_NUM_INVALID); + + /* The interrupt enable bits that can be controlled in the mie register (32 bits), up to 32 + can be controlled, and each bit corresponds to an interrupt enable */ + + RISCV_PRIV_MODE_SWITCH(priv); + + if (irqNum < IRQ_MIE_TOTAL_CNT) { + irqOrder = 1U << irqNum; + SET_CSR(mie, irqOrder); + } else if (irqNum < IRQ_LOCIEN1_OFFSET) { + irqOrder = irqNum - IRQ_MIE_TOTAL_CNT; + locienVal = READ_CUSTOM_CSR(LOCIEN0); + locienVal |= (1U << irqOrder); + WRITE_CUSTOM_CSR_VAL(LOCIEN0, locienVal); + } else if (irqNum < IRQ_LOCIEN2_OFFSET) { + irqOrder = irqNum - IRQ_LOCIEN1_OFFSET; + locienVal = READ_CUSTOM_CSR(LOCIEN1); + locienVal |= (1U << irqOrder); + WRITE_CUSTOM_CSR_VAL(LOCIEN1, locienVal); + } else { + irqOrder = irqNum - IRQ_LOCIEN2_OFFSET; + locienVal = READ_CUSTOM_CSR(LOCIEN2); + locienVal |= (1U << irqOrder); + WRITE_CUSTOM_CSR_VAL(LOCIEN2, locienVal); + } + + RISCV_PRIV_MODE_SWITCH(priv); + + return BASE_STATUS_OK; +} + +/** + * @brief Disable the specified interrupt. + * @param irqNum External interrupt number. + * @retval BASE_STATUS_OK or IRQ_ERRNO_NUM_INVALID or IRQ_ERRNO_NOT_CREATED. + */ +unsigned int IRQ_DisableN(unsigned int irqNum) +{ + unsigned int irqOrder; +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + unsigned int priv = IRQ_GetCpuPrivilege(); +#endif + + INTERRUPT_PARAM_CHECK_WITH_RET((irqNum >= IRQ_VECTOR_CNT && irqNum < IRQ_MAX), IRQ_ERRNO_NUM_INVALID); + INTERRUPT_PARAM_CHECK_WITH_RET((g_irqCallbackFunc[irqNum].pfnHandler != IRQ_DummyHandler), IRQ_ERRNO_NOT_CREATED); + + RISCV_PRIV_MODE_SWITCH(priv); + + if (irqNum < IRQ_MIE_TOTAL_CNT) { + irqOrder = 1U << irqNum; + CLEAR_CSR(mie, irqOrder); + } else if (irqNum < IRQ_LOCIEN1_OFFSET) { + irqOrder = 1U << (irqNum - IRQ_MIE_TOTAL_CNT); + CLEAR_CUSTOM_CSR(LOCIEN0, irqOrder); + } else if (irqNum < IRQ_LOCIEN2_OFFSET) { + irqOrder = 1U << (irqNum - IRQ_LOCIEN1_OFFSET); + CLEAR_CUSTOM_CSR(LOCIEN1, irqOrder); + } else { + irqOrder = 1U << (irqNum - IRQ_LOCIEN2_OFFSET); + CLEAR_CUSTOM_CSR(LOCIEN2, irqOrder); + } + + RISCV_PRIV_MODE_SWITCH(priv); + + return BASE_STATUS_OK; +} + +/** + * @brief Print RISCV register. + * @param context. + * @note The actual code is generated by IDE + * @retval None. + */ +__weak void SysErrPrint(const SyserrContext *context) +{ + BASE_FUNC_UNUSED(context); +} + +/** + * @brief System error completion processing + * @param None. + * @retval None. + */ +static void SysErrFinish(void) +{ +} + +/** + * @brief Exception Handler Entry. + * @param context error context. + * @retval None. + */ +void SysErrExcEntry(const SyserrContext *context) +{ + SysErrPrint(context); + SysErrFinish(); +} + +/** + * @brief NMI Interrupt Handler Entry. + * @param context error context. + * @retval None. + */ +void SysErrNmiEntry(const SyserrContext *context) +{ + INTERRUPT_ASSERT_PARAM(context != NULL); + SysErrPrint(context); + SysErrFinish(); +} +/** + * @brief Set the priority of local interrupt. + * @param intNum GROUP NUM. + * @param interPriNum Local interrupt number, which equals external interrupt number - IRQ_VECTOR_CN. + * @param prior local int prioroty. + * @retval None + */ +static void SetLocalIntNumPri(unsigned int intNum, unsigned int interPriNum, unsigned int prior) +{ + switch (intNum) { + case 8: /* GROUP8 */ + SET_LOCAL_INTER_NUM_PRI(8, interPriNum, prior); + break; + case 9: /* GROUP9 */ + SET_LOCAL_INTER_NUM_PRI(9, interPriNum, prior); + break; + case 10: /* GROUP10 */ + SET_LOCAL_INTER_NUM_PRI(10, interPriNum, prior); + break; + case 11: /* GROUP11 */ + SET_LOCAL_INTER_NUM_PRI(11, interPriNum, prior); + break; + case 12: /* GROUP12 */ + SET_LOCAL_INTER_NUM_PRI(12, interPriNum, prior); + break; + case 13: /* GROUP13 */ + SET_LOCAL_INTER_NUM_PRI(13, interPriNum, prior); + break; + case 14: /* GROUP14 */ + SET_LOCAL_INTER_NUM_PRI(14, interPriNum, prior); + break; + case 15: /* GROUP15 */ + SET_LOCAL_INTER_NUM_PRI(15, interPriNum, prior); + break; + default: + break; + } +} +/** + * @brief Set the priority of local interrupt. + * @param interPriNum Local interrupt number, which equals external interrupt number - IRQ_VECTOR_CN. + * @param prior Priority of this local interrupt to be set. + * @retval None. + */ +static void IRQ_SetLocalPriority(unsigned int interPriNum, unsigned int prior) +{ +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + unsigned int priv = IRQ_GetCpuPrivilege(); +#endif + RISCV_PRIV_MODE_SWITCH(priv); + unsigned int intNum = GET_LOCAL_INTER_CONFIGREG_NUM(interPriNum); + switch (intNum) { + case 0: /* GROUP0 */ + SET_LOCAL_INTER_NUM_PRI(0, interPriNum, prior); + break; + case 1: /* GROUP1 */ + SET_LOCAL_INTER_NUM_PRI(1, interPriNum, prior); + break; + case 2: /* GROUP2 */ + SET_LOCAL_INTER_NUM_PRI(2, interPriNum, prior); + break; + case 3: /* GROUP3 */ + SET_LOCAL_INTER_NUM_PRI(3, interPriNum, prior); + break; + case 4: /* GROUP4 */ + SET_LOCAL_INTER_NUM_PRI(4, interPriNum, prior); + break; + case 5: /* GROUP5 */ + SET_LOCAL_INTER_NUM_PRI(5, interPriNum, prior); + break; + case 6: /* GROUP6 */ + SET_LOCAL_INTER_NUM_PRI(6, interPriNum, prior); + break; + case 7: /* GROUP7 */ + SET_LOCAL_INTER_NUM_PRI(7, interPriNum, prior); + break; + default: + SetLocalIntNumPri(intNum, interPriNum, prior); + break; + } + RISCV_PRIV_MODE_SWITCH(priv); +} + +/** + * @brief Set the priority of external interrupt. + * @param irqNum External interrupt number. + * @param priority. + * @retval IRQ_ERRNO_NUM_INVALID or IRQ_ERRNO_PRIORITY_INVALID or BASE_STATUS_OK. + */ +unsigned int IRQ_SetPriority(unsigned int irqNum, unsigned int priority) +{ + INTERRUPT_PARAM_CHECK_WITH_RET((irqNum >= IRQ_VECTOR_CNT && irqNum < IRQ_MAX), IRQ_ERRNO_NUM_INVALID); + INTERRUPT_PARAM_CHECK_WITH_RET((priority >= IRQ_PRIO_LOWEST && priority <= IRQ_PRIO_HIGHEST), \ + IRQ_ERRNO_PRIORITY_INVALID); + + /* The locipri register is specifically used to configure the priority of the + external non-standard interrupts of the CPU, so the number of internal + standard interrupts should be subtracted */ + IRQ_SetLocalPriority(irqNum - IRQ_VECTOR_CNT, priority); + + return BASE_STATUS_OK; +} +/** + * @brief Get the priority of local interrupt. + * @param intNum GROUP NUM. + * @param interPriNum Local interrupt number, which equals external interrupt number - IRQ_VECTOR_CN. + * @param prior local int prioroty. + * @retval None + */ +static void GetLocaIntNumPri(unsigned int intNum, unsigned int interPriNum, unsigned int prior) +{ + switch (intNum) { + case 8: /* GROUP8 */ + GET_LOCAL_INTER_NUM_PRI(8, interPriNum, prior); + break; + case 9: /* GROUP9 */ + GET_LOCAL_INTER_NUM_PRI(9, interPriNum, prior); + break; + case 10: /* GROUP10 */ + GET_LOCAL_INTER_NUM_PRI(10, interPriNum, prior); + break; + case 11: /* GROUP11 */ + GET_LOCAL_INTER_NUM_PRI(11, interPriNum, prior); + break; + case 12: /* GROUP12 */ + GET_LOCAL_INTER_NUM_PRI(12, interPriNum, prior); + break; + case 13: /* GROUP13 */ + GET_LOCAL_INTER_NUM_PRI(13, interPriNum, prior); + break; + case 14: /* GROUP14 */ + GET_LOCAL_INTER_NUM_PRI(14, interPriNum, prior); + break; + case 15: /* GROUP15 */ + GET_LOCAL_INTER_NUM_PRI(15, interPriNum, prior); + break; + default: + break; + } +} + +/** + * @brief Get the priority of local interrupt. + * @param interPriNum Local interrupt number, which equals external interrupt number - IRQ_VECTOR_CN. + * @retval prior Priority of this local interrupt to be set. + */ +static unsigned int IRQ_GetLocalPriority(unsigned int interPriNum) +{ +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + unsigned int priv = IRQ_GetCpuPrivilege(); +#endif + unsigned int prior = 0; + RISCV_PRIV_MODE_SWITCH(priv); + unsigned int intNum = GET_LOCAL_INTER_CONFIGREG_NUM(interPriNum); + switch (intNum) { + case 0: /* GROUP0 */ + GET_LOCAL_INTER_NUM_PRI(0, interPriNum, prior); + break; + case 1: /* GROUP1 */ + GET_LOCAL_INTER_NUM_PRI(1, interPriNum, prior); + break; + case 2: /* GROUP2 */ + GET_LOCAL_INTER_NUM_PRI(2, interPriNum, prior); + break; + case 3: /* GROUP3 */ + GET_LOCAL_INTER_NUM_PRI(3, interPriNum, prior); + break; + case 4: /* GROUP4 */ + GET_LOCAL_INTER_NUM_PRI(4, interPriNum, prior); + break; + case 5: /* GROUP5 */ + GET_LOCAL_INTER_NUM_PRI(5, interPriNum, prior); + break; + case 6: /* GROUP6 */ + GET_LOCAL_INTER_NUM_PRI(6, interPriNum, prior); + break; + case 7: /* GROUP7 */ + GET_LOCAL_INTER_NUM_PRI(7, interPriNum, prior); + break; + default: + GetLocaIntNumPri(intNum, interPriNum, prior); + break; + } + RISCV_PRIV_MODE_SWITCH(priv); + return prior; +} +/** + * @brief Get the priority of external interrupt. + * @param irqNum External interrupt number. + * @output priority. + * @retval IRQ_ERRNO_NUM_INVALID or IRQ_ERRNO_PRIORITY_INVALID or BASE_STATUS_OK. + */ +unsigned int IRQ_GetPriority(unsigned int irqNum, unsigned int *priority) +{ + INTERRUPT_PARAM_CHECK_WITH_RET(irqNum < IRQ_MAX, IRQ_ERRNO_NUM_INVALID); + + /* The locipri register is specifically used to configure the priority of the + external non-standard interrupts of the CPU, so the number of internal + standard interrupts should be subtracted */ + *priority = IRQ_GetLocalPriority(irqNum - IRQ_VECTOR_CNT); + + return BASE_STATUS_OK; +} + +/** + * @brief Clear all external interrupts + * @retval BASE_STATUS_OK or IRQ_ERRNO_NOT_CREATED + */ +unsigned int IRQ_ClearAll(void) +{ + unsigned int index; + for (index = IRQ_VECTOR_CNT; index < IRQ_MAX; index++) { + IRQ_ClearN(index); + } + return BASE_STATUS_OK; +} + +/** + * @brief Interrupt dummy handler + * @param arg Not used + * @retval None. + */ +static void IRQ_DummyHandler(void *arg) +{ + BASE_FUNC_UNUSED(arg); +} + +/** + * @brief Construct a new irq setcallback object + * @param irqNum external interrupt number + * @param func callback function + * @param arg callback arg + * @retval None. + */ +static inline void IRQ_SetCallBack(unsigned int irqNum, IRQ_PROC_FUNC func, void *arg) +{ + g_irqCallbackFunc[irqNum].param = arg; + g_irqCallbackFunc[irqNum].pfnHandler = func; +} + +/** + * @brief Get CPU Privilege by ecall + * @param none + * @retval mcause value + */ +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) +static inline unsigned int IRQ_GetCpuPrivilege(void) +{ + return (g_RiscvPrivMode == 0) ? RISCV_U_MODE : RISCV_M_MODE; +} +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/base/src/lock.c b/vendor/xinlingyu_92_3061M/Project/drivers/base/src/lock.c new file mode 100644 index 0000000000000000000000000000000000000000..764a7cf2827ab69694f446d9c6f0b5ed55a10122 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/base/src/lock.c @@ -0,0 +1,82 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file lock.c + * @author MCU Driver Team + * @brief Provides functions about locks. + */ + +/* Includes ------------------------------------------------------------------ */ +#include "lock.h" + +/* Global Variables----------------------------------------------------------- */ +unsigned int g_baseLock[CHIP_LOCK_TOTAL]; /**< Used to store the hardware lock status */ + +/** + * @brief Attempt to acquire a lock for the specified address. + * @param addr Point to the address where the lock is obtained. + * @retval true, Succeeded in obtaining the lock. + * @retval false, Failed to obtain the lock. The resource has been locked. + */ +bool BASE_FUNC_SoftwareLock(unsigned int * const addr) +{ + BASE_FUNC_PARAMCHECK_WITH_RET(addr, false); + + unsigned int tmpLocked = *addr; + *addr = BASE_STATUS_LOCKED; + /* Atomic exchange instructions are not supported. Lock determination and locking may be interrupted by */ + /* interrupts. To ensure atomicity, disable the corresponding interrupts. */ + if (tmpLocked == BASE_STATUS_UNLOCKED) { + return true; + } + return false; +} + +/** + * @brief Releases the lock of the specified address. + * @param addr Point to the address that releases the lock. + * @retval None. + */ +void BASE_FUNC_SoftwareUnLock(unsigned int * const addr) +{ + BASE_FUNC_PARAMCHECK_NO_RET(addr); + + *addr = BASE_STATUS_UNLOCKED; +} + +/** + * @brief Attempt to acquire a lock on the specified hardware resource by hwIndex. + * @param hwIndex Hardware Resource ID. + * @retval true, Succeeded in obtaining the Hardware Resource lock. + * @retval false, Failed to obtain the Hardware Resource lock. The resource has been locked. + */ +bool BASE_FUNC_HardwareLock(CHIP_LockType const hwIndex) +{ + BASE_FUNC_PARAMCHECK_WITH_RET((hwIndex >= 0 && hwIndex < CHIP_LOCK_TOTAL), false); + return BASE_FUNC_SoftwareLock(&g_baseLock[hwIndex]); +} + +/** + * @brief Releases the lock of a specified hardware resource. + * @param hwIndex Hardware Resource ID. + * @retval None. + */ +void BASE_FUNC_HardwareUnLock(CHIP_LockType const hwIndex) +{ + BASE_FUNC_PARAMCHECK_NO_RET(hwIndex >= 0 && hwIndex < CHIP_LOCK_TOTAL); + BASE_FUNC_SoftwareUnLock(&g_baseLock[hwIndex]); +} diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/base/src/reset.c b/vendor/xinlingyu_92_3061M/Project/drivers/base/src/reset.c new file mode 100644 index 0000000000000000000000000000000000000000..c7c4e0858ac40356e4733462413f3d2ca2c6d2e0 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/base/src/reset.c @@ -0,0 +1,41 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file reset.c + * @author MCU Driver Team + * @brief Provides functions related to software reset. + */ + +/* Includes ------------------------------------------------------------------ */ +#include "reset.h" +#include "crg_ip.h" + +/** + * @brief Soft reset interface + * @retval None. + */ +void BASE_FUNC_SoftReset(void) +{ + DCL_SYSCTRL_ScWriteProtectionDisable(); + /* Set core clock as CRG_CORE_CLK_SELECT_HOSC. */ + DCL_CRG_SetCoreClkSel(CRG, CRG_CORE_CLK_SELECT_HOSC); + DCL_SYSCTRL_SoftReset(); + + while (1) { + __asm__ volatile ("nop"); + } +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/can/common/inc/can.h b/vendor/xinlingyu_92_3061M/Project/drivers/can/common/inc/can.h new file mode 100644 index 0000000000000000000000000000000000000000..b9f2e930a1821f22107b5972ca0e7ca4d72ed459 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/can/common/inc/can.h @@ -0,0 +1,110 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file can.h + * @author MCU Driver Team + * @brief CAN module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the CAN. + * + Definition of the CAN handle structure. + * + Initialization and de-initialization functions. + * + Sending and receiving CAN data frames functions. + * + Interrupt handler function and user registration callback function. + */ + +/* Includes ------------------------------------------------------------------*/ +#ifndef McuMagicTag_CAN_H +#define McuMagicTag_CAN_H + +#include "can_ip.h" + + +/** + * @defgroup CAN CAN + * @brief CAN module. + * @{ + */ + +/** + * @defgroup CAN_Common CAN Common + * @brief CAN common external module. + * @{ + */ + +/** + * @defgroup CAN_Handle_Definition ADC Handle Definition + * @{ + */ + +/** + * @brief Definition of the CAN handle structure. + */ +typedef struct _CAN_Handle { + CAN_RegStruct *baseAddress; /**< CAN registers base address */ + CAN_TypeMode typeMode; /**< Work mode */ + CAN_TestMode_Configure *testModeConfigure; /**< Test mode configure */ + CAN_Seg1_Phase seg1Phase; /**< Seg1Phase: Phase Buffer Section 1, propagation section */ + CAN_Seg2_Phase seg2Phase; /**< Seg2Phase: Phase Buffer Section 2 */ + unsigned int prescalser; /**< CAN frequency divider, range: 1 ~ 64 */ + CAN_Sync_Jump_Width sjw; /**< Sync jump width coefficient */ + volatile CAN_State_Type state; /**< Transmit status of the CAN. */ + volatile CANFrame *rxFrame; /**< Rx buff */ + CAN_FilterConfigure *rxFilter; /**< Received Frame Filtering Configuration */ + unsigned int rxFIFODepth; /**< Number of receive FIFO composed by packet objects */ + bool autoRetrans; /**< Automatic retransmission of interfered message */ + + CAN_UserCallBack userCallBack; /**< User call back function of CAN */ + CAN_ExtendHandle handleEx; /**< CAN extend handle */ +} CAN_Handle; + +typedef void (* CAN_CallbackType)(void *handle); +/** + * @} + */ + +/** + * @defgroup CAN_API_Declaration CAN HAL API + * @{ + */ +BASE_StatusType HAL_CAN_Init(CAN_Handle *canHandle); +BASE_StatusType HAL_CAN_DeInit(CAN_Handle *canHandle); +BASE_StatusType HAL_CAN_ReadIT(CAN_Handle *canHandle, CANFrame *data, CAN_FilterConfigure *filterConfigure); +BASE_StatusType HAL_CAN_Write(CAN_Handle *canHandle, CANFrame *data); + +/* CAN status */ +CAN_ErrorStatus HAL_CAN_GetErrorStatus(CAN_Handle *canHandle); +unsigned int HAL_CAN_GetErrorStatusCode(CAN_Handle *canHandle); +CAN_BusOffStatus HAL_CAN_GetBusOffStatus(CAN_Handle *canHandle); +CAN_MessageReceiveStatus HAL_CAN_MessageReceiveStatus(CAN_Handle *canHandle); +CAN_MessageSendStatus HAL_CAN_MessageSendStatus(CAN_Handle *canHandle); +/* CAN interrupt service funciton. */ +void HAL_CAN_IrqHandler(void *handle); +BASE_StatusType HAL_CAN_RegisterCallBack(CAN_Handle *canHandle, CAN_CallBackFunType typeID, + CAN_CallbackType pCallback); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_CAN_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/can/inc/can_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/can/inc/can_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..f25c3836c013ae5d0ff6fecd18c3a1503a4beaa3 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/can/inc/can_ip.h @@ -0,0 +1,1738 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file can_ip.h + * @author MCU Driver Team + * @brief CAN module driver. + * @details This file provides DCL functions to manage CAN and Definition of + * specific parameters + * + Definition of CAN configuration parameters. + * + CAN register mapping structure. + * + Parameters check functions. + * + Direct configuration layer interface + */ + +/* Macro definitions */ +#ifndef McuMagicTag_CAN_IP_H +#define McuMagicTag_CAN_IP_H + +#define PRESCALSER_MIN 1 +#define PRESCALSER_MAX 64 + +#define MESSAGE_NUMBER_MIN 1 +#define MESSAGE_NUMBER_MAX 32 + +#ifdef CAN_PARAM_CHECK +#define CAN_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define CAN_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define CAN_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define CAN_ASSERT_PARAM(para) ((void)0U) +#define CAN_PARAM_CHECK_NO_RET(para) ((void)0U) +#define CAN_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +#include "baseinc.h" + +/** + * @addtogroup CAN + * @{ + */ + +/** + * @defgroup CAN_IP CAN_IP + * @brief CAN_IP: can_v0. + * @{ + */ + +/** + * @defgroup CAN_Param_Def CAN Parameters Definition + * @brief Definition of CAN configuration parameters. + * @{ + */ + +/** + * @brief Extent handle definition of CAN + */ +typedef struct { +} CAN_ExtendHandle; + +/** + * @brief Type ID of the callback function registered by the user. + */ +typedef enum { + CAN_WRITE_FINISH = 0x00000000U, + CAN_READ_FINISH = 0x00000001U, + CAN_TRNS_ERROR = 0x00000002U +} CAN_CallBackFunType; + +/** + * @brief Type define of user callback function + */ +typedef struct { + void (* WriteFinishCallBack)(void *handle); /**< CAN tx interrupt complete callback function for users */ + void (* ReadFinishCallBack)(void *handle); /**< CAN rx interrupt complete callback function for users */ + void (* TransmitErrorCallBack)(void *handle); /**< CAN mode error callback function for users */ +} CAN_UserCallBack; + +/** + * @brief CAN state type. + */ +typedef enum { + CAN_STATE_NONE_INIT = 0x00000000U, + CAN_STATE_READY = 0x00000001U, + CAN_STATE_BUSY_TX = 0x00000002U, + CAN_STATE_BUSY_RX = 0x00000003u, +} CAN_State_Type; + +/** + * @brief Error status code: the last error status on the CAN bus. + */ +typedef enum { + CAN_ERROR_NONE = 0x00000000U, + CAN_ERROR_PADDING = 0x00000001U, + CAN_ERROR_FORMAL = 0x00000002U, + CAN_ERROR_ANSWER = 0x00000003U, + CAN_ERROR_BIT1 = 0x00000004U, + CAN_ERROR_BIT0 = 0x00000005U, + CAN_ERROR_CRC = 0x00000006U +} CAN_ERROR_StatusCode; + +/** + * @brief Indicates the error status. + * @details CAN Error Status Code: + * +CAN_ACTIVE_ERROR: active error defined by the CAN protocol; + * +CAN_PASSIVE_ERROR: passive error defined by the CAN protocol. + */ +typedef enum { + CAN_ACTIVE_ERROR = 0x00000000U, + CAN_PASSIVE_ERROR = 0x00000001U +} CAN_ErrorStatus; + +/** + * @brief Bus-off status. + * @details CAN Bus-off Status: + * CAN_BUSSOFF_OFF: The CAN module is not in the bus-off state. + * CAN_BUSSOFF_ON: The CAN module is in the bus-off state. + */ +typedef enum { + CAN_BUSOFF_OFF = 0x00000000U, + CAN_BUSOFF_ON = 0x00000001U +} CAN_BusOffStatus; + +/** + * @brief Status of CAN message receive status. + * @details CAN message receive status: + * CAN_MESSAGE_RECEIVE_OK: receive message success. + * CAN_MESSAGE_RECEIVE_ERROR: receive message error. + */ +typedef enum { + CAN_MESSAGE_RECEIVE_OK = 0x00000000U, + CAN_MESSAGE_RECEIVE_ERROR = 0x00000001U +}CAN_MessageReceiveStatus; + +/** + * @brief Status of CAN message send status. + * @details CAN message receive status: + * CAN_MESSAGE_SEND_OK: send message success. + * CAN_MESSAGE_SEND_ERROR: send message error. + */ +typedef enum { + CAN_MESSAGE_SEND_OK = 0x00000000U, + CAN_MESSAGE_SEND_ERROR = 0x00000001U +}CAN_MessageSendStatus; + +/** + * @brief Work mode select. + */ +typedef enum { + CAN_MODE_NORMAL = 0x00000000U, + CAN_MODE_TEST = 0x00000001U +} CAN_TypeMode; + +/** + * @brief Test status select in test mode. + * @details Mode type: + * + loopBack mode, 1: enabele, rx can receive tx frame ; 0: disable + * + silent mode, 1: enabele, cannot send frame to others; 0: disable + * + basic mode, 1: enable, IF1 used for tx buffer, IF2 used for rx buffer; 0: disable + */ +typedef struct { + unsigned int loopBack; + unsigned int silent; + unsigned int basic; +} CAN_TestMode_Configure; + +/** + * @brief The type of CAN frame. + * @details CAN frame type: + * + CAN_TYPEFRAME_STD_DATA -- Standard data frame + * + CAN_TYPEFRAME_EXT_DATA -- Extended data Frame + * + CAN_TYPEFRAME_STD_REMOTE -- Standard remote frame + * + CAN_TYPEFRAME_EXT_REMOTE -- Extended remote Frame + */ +typedef enum { + CAN_TYPEFRAME_STD_DATA = 0x00000000U, + CAN_TYPEFRAME_EXT_DATA = 0x00000001U, + CAN_TYPEFRAME_STD_REMOTE = 0x00000002U, + CAN_TYPEFRAME_EXT_REMOTE = 0x00000003U +} CAN_TypeFrame; + +/** + * @brief Type of the received frame after filtering. + * @details Filtering receive frame type: + * + CAN_FILTERFRAME_STD_DATA -- Standard data frame + * + CAN_FILTERFRAME_EXT_DATA -- Extended data frame + * + CAN_FILTERFRAME_STD_EXT_DATA -- Standard remote frame + */ +typedef enum { + CAN_FILTERFRAME_STD_DATA = 0x00000000U, + CAN_FILTERFRAME_EXT_DATA = 0x00000001U, + CAN_FILTERFRAME_STD_EXT_DATA = 0x00000002U +} CAN_FilterFrame; + +/** + * @brief Time quanta of phase buffer section 1 and propagation section. + */ +typedef enum { + CAN_SEG1_2TQ = 0x00000002U, + CAN_SEG1_3TQ = 0x00000003U, + CAN_SEG1_4TQ = 0x00000004U, + CAN_SEG1_5TQ = 0x00000005U, + CAN_SEG1_6TQ = 0x00000006U, + CAN_SEG1_7TQ = 0x00000007U, + CAN_SEG1_8TQ = 0x00000008U, + CAN_SEG1_9TQ = 0x00000009U, + CAN_SEG1_10TQ = 0x0000000AU, + CAN_SEG1_11TQ = 0x0000000BU, + CAN_SEG1_12TQ = 0x0000000CU, + CAN_SEG1_13TQ = 0x0000000DU, + CAN_SEG1_14TQ = 0x0000000EU, + CAN_SEG1_15TQ = 0x0000000FU, + CAN_SEG1_16TQ = 0x00000010U +} CAN_Seg1_Phase; + +/** + * @brief Time quanta of phase buffer section 2. + */ +typedef enum { + CAN_SEG2_1TQ = 0x00000001U, + CAN_SEG2_2TQ = 0x00000002U, + CAN_SEG2_3TQ = 0x00000003U, + CAN_SEG2_4TQ = 0x00000004U, + CAN_SEG2_5TQ = 0x00000005U, + CAN_SEG2_6TQ = 0x00000006U, + CAN_SEG2_7TQ = 0x00000007U, + CAN_SEG2_8TQ = 0x00000008U +} CAN_Seg2_Phase; + +/** + * @brief Time quanta of Sync Jump Width. + */ +typedef enum { + CAN_SJW_1TQ = 0x00000001U, + CAN_SJW_2TQ = 0x00000002U, + CAN_SJW_3TQ = 0x00000003U, + CAN_SJW_4TQ = 0x00000004U +} CAN_Sync_Jump_Width; + +/** + * @brief Error status code: the last error status on the CAN bus. + */ +typedef enum { + CAN_WRITE_MASK = 0x00000008U, + CAN_READ_MASK = 0x00000010U, + CAN_EPASS_MASK = 0x00000020U, + CAN_EWARN_MASK = 0x00000040U, + CAN_BOFF_MASK = 0x00000080U, +} CAN_StatusMask; + +/** + * @brief CAN data frame format. + */ +typedef struct { + CAN_TypeFrame type; + unsigned int dataLength; + unsigned int CANId; + unsigned char frame[8]; +} CANFrame; + +/** + * @brief Received frame filtering configuration parameters. + */ +typedef struct { + CAN_FilterFrame receiveType; + unsigned int filterID; + unsigned int filterMask; +} CAN_FilterConfigure; + +/** + * @brief Bit timing parameters. + */ +typedef struct { + unsigned int Tseg2 : 3; + unsigned int Tseg1 : 4; + unsigned int SJW : 2; + unsigned int BRP : 1; +} Bit_Timing; +/** + * @} + */ + +/** + * @defgroup CAN_Reg_Def CAN Register Definition + * @brief CAN register mapping structure. + * @{ + */ + +/** + * @brief CAN control register, Control of basic functions. + */ +typedef union { + unsigned int reg; + struct { + unsigned int Init : 1; /**< Initialization enable. */ + unsigned int IE : 1; /**< Module interrupt enable. */ + unsigned int SIE : 1; /**< Status change interrupt enable. */ + unsigned int EIE : 1; /**< Error interrupt enable. */ + unsigned int reserved0 : 1; + unsigned int DAR : 1; /**< Automatic retransmission enable. */ + unsigned int CCE : 1; /**< Configuration change enable. */ + unsigned int Test : 1; /**< Test mode enable. */ + unsigned int reserved1 : 24; + } BIT; +} volatile CAN_CONTROL_REG; + +/** + * @brief CAN status register register.CAN error count register + */ +typedef union { + unsigned int reg; + struct { + unsigned int LEC : 3; /**< Error status code, used to indicate last error status on CAN bus. */ + unsigned int TxOk : 1; /**< Indicates the packet sending status. */ + unsigned int RxOk : 1; /**< Indicates the packet receiving status. */ + unsigned int Epass : 1; /**< Indicates the error status. */ + unsigned int Ewarn : 1; /**< Warning status. */ + unsigned int Boff : 1; /**< Bus-off status. */ + unsigned int reserved0 : 24; + } BIT; +} volatile CAN_STATUS_REG; + +/** + * @brief CAN error count register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int TEC : 8; /**< Indicates transmission error counter. */ + unsigned int REC : 7; /**< Receive error counter. */ + unsigned int RP : 1; /**< Indicates passive error reception status. */ + unsigned int reserved0 : 16; + } BIT; +} volatile CAN_ERROR_COUNTER_REG; + +/** + * @brief bit time register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int BRP : 6; /**< Baud rate coefficient. */ + unsigned int SJW : 2; /**< Resync jump width. */ + unsigned int TSeg1 : 4; /**< Phase buffer segment 1. */ + unsigned int TSeg2 : 3; /**< Phase buffer segment 2. */ + unsigned int reserved0 : 17; + } BIT; +} volatile BIT_TIMING_REG; + +/** + * @brief CAN interrupt register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int IntId : 16; /**< Interrupt packet object ID. */ + unsigned int reserved0 : 16; + } BIT; +} volatile CAN_INTERRUPT_REG; + +/** + * @brief CAN test register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int : 2; + unsigned int Basic : 1; /**< Basic mode enable. */ + unsigned int Silent : 1; /**< Silent mode enable. */ + unsigned int Lback : 1; /**< Loop back mode enable. */ + unsigned int Tx : 2; /**< CAN_TX pin control. */ + unsigned int Rx : 1; /**< Monitors the CAN_RX pin. */ + unsigned int reserved0 : 24; + } BIT; +} volatile CAN_TEST_REG; + +/** + * @brief Baud rate coefficient extension register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int BRPE : 4; /**< Baud rate coefficient expansion. */ + unsigned int reserved0 : 28; + } BIT; +} volatile BRP_EXTENSION_REG; + +/** + * @brief Request register for IF1 command. + */ +typedef union { + unsigned int reg; + struct { + unsigned int MessageNumber : 6; /**< Message object serial number. */ + unsigned int reserved0 : 9; + unsigned int BUSY : 1; /**< Busy signal. */ + unsigned int reserved1 : 16; + } BIT; +} volatile IF1_COMMAND_REQUEST_REG; + +/** + * @brief IF1 command mask register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DataB : 1; /**< Command mask, which controls the transmission of IF1_DATAB. */ + unsigned int DataA : 1; /**< Command mask, which controls the transmission of IF1_DATAA. */ + unsigned int TxRqstNewDat : 1; /**< Command mask, which controls the TxRqst bit or NewDat bit of + the packet object. */ + unsigned int ClrIntPnd : 1; /**< Command mask, which is used to clear the interrupts of the + packet object to be processed. */ + unsigned int Control : 1; /**< Command mask, which controls the transmission of IF1_MESSAGE_CONTROL. */ + unsigned int Arb : 1; /**< Command mask, which controls the transmission of IF1_ARBITRATION. */ + unsigned int Mask : 1; /**< Command mask, which controls the transmission of IF1_MASK.*/ + unsigned int WRRD : 1; /**< Read/Write command, which controls the transfer direction + of the IF1 packet buffer register and Message RAM. */ + unsigned int reserved0 : 24; + } BIT; +} volatile IF1_COMMAND_MASK_REG; + +/** + * @brief IF1 mask register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int Msk : 16; /**< Mask of the 15th to 0th bits of the packet object ID + which are used for packet receiving and filtering. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF1_MASK1_REG; + +/** + * @brief IF1 mask register 2. + */ +typedef union { + unsigned int reg; + struct { + unsigned int Msk : 13; /**< Mask of the 28th to 16th bits of the packet object ID + which are used to filter received packets. */ + unsigned int reserved0 : 1; + unsigned int MDir : 1; /**< Indicates the direction bit mask of the packet object + which is used for filtering received packets. */ + unsigned int MXtd : 1; /**< Indicates the extended ID (Xtd) mask of the packet object + which is used for filtering received packets. */ + unsigned int reserved1 : 16; + } BIT; +} volatile IF1_MASK2_REG; + +/** + * @brief IF1 arbitration register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ID : 16; /**< Bits 15 to 0 of the packet ID of the packet object. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF1_ARBITRATION1_REG; + +/** + * @brief IF1 arbitration register 2. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ID : 13; /**< Bits 28 to 16 of packet ID of packet object. */ + unsigned int Dir : 1; /**< Indicates direction of the packet object. */ + unsigned int Xtd : 1; /**< Indicates format of received and sent frames of packet object. */ + unsigned int MsgVal : 1; /**< Packet object validity enable. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF1_ARBITRATION2_REG; + +/** + * @brief IF1 packet control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DLC : 4; /**< Data length. */ + unsigned int reserved0 : 3; + unsigned int EoB : 1; /**< Indicates the multi-packet receiving mode. */ + unsigned int TxRqst : 1; /**< Transfer request. */ + unsigned int RmtEn : 1; /**< Remote frame enable. */ + unsigned int RxIE : 1; /**< RX interrupt enable. */ + unsigned int TxIE : 1; /**< TX interrupt enable. */ + unsigned int Umask : 1; /**< Indicates whether the packet object uses the packet mask + which is used for packet receiving and filtering. */ + unsigned int IntPnd : 1; /**< Indicates the interrupt to be processed of the packet object. */ + unsigned int MsgLst : 1; /**< Indicates the packet loss flag of the packet object + parameter is valid only when packet object is in the receive direction. */ + unsigned int NewDat : 1; /**< Write status of the new data of the message object. */ + unsigned int reserved1 : 16; + } BIT; +} volatile IF1_MESSAGE_CONTROL_REG; + +/** + * @brief IF1 data A1 register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DATA0 : 8; /**< CAN frame data byte 0. */ + unsigned int DATA1 : 8; /**< CAN frame data byte 1. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF1_DATAA1_REG; + +/** + * @brief IF1 data A2 register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DATA2 : 8; /**< CAN frame data byte 2. */ + unsigned int DATA3 : 8; /**< CAN frame data byte 3. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF1_DATAA2_REG; + +/** + * @brief IF1 data B1 register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DATA4 : 8; /**< CAN frame data byte 4. */ + unsigned int DATA5 : 8; /**< CAN frame data byte 5. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF1_DATAB1_REG; + +/** + * @brief IF1 data B2 register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DATA6 : 8; /**< CAN frame data byte 6. */ + unsigned int DATA7 : 8; /**< CAN frame data byte 7. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF1_DATAB2_REG; + +/** + * @brief IF2 command request register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int MessageNumber : 6; /**< Indicates the sequence number of a packet object. */ + unsigned int reserved0 : 9; + unsigned int BUSY : 1; /**< Busy sign. */ + unsigned int reserved1 : 16; + } BIT; +} volatile IF2_COMMAND_REQUEST_REG; + +/** + * @brief IF2 command mask register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DataB : 1; /**< Command mask, which controls the transmission of IF2_DATAB. */ + unsigned int DataA : 1; /**< Command mask, which controls the transmission of IF2_DATAA. */ + unsigned int TxRqstNewDat : 1;/**< Command mask, which controls TxRqst bit or NewDat bit of packet object. */ + unsigned int ClrIntPnd : 1; /**< Command mask, which is used to clear interrupts of packet + object to be processed. */ + unsigned int Control : 1; /**< Command mask, which controls the transmission of IF2_MESSAGE_CONTROL. */ + unsigned int Arb : 1; /**< Command mask, which controls the transmission of IF2_ARBITRATION. */ + unsigned int Mask : 1; /**< Command mask, which controls the transmission of IF2_MASK. */ + unsigned int WRRD : 1; /**< Read/Write command, which controls the transfer direction of + the IF2 packet buffer register and Message RAM. */ + unsigned int reserved0 : 24; + } BIT; +} volatile IF2_COMMAND_MASK_REG; + +/** + * @brief IF2 mask register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int Msk : 16; /**< Mask of the 15th to 0th bits of the packet object ID + which are used for packet receiving and filtering. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF2_MASK1_REG; + +/** + * @brief IF2 mask register 2. + */ +typedef union { + unsigned int reg; + struct { + unsigned int Msk : 13; /**< Mask of the 28th to 16th bits of the packet object ID + which are used for packet receiving and filtering. */ + unsigned int reserved0 : 1; + unsigned int MDir : 1; /**< Indicates the direction bit mask of the packet object + which is used for packet receiving and filtering. */ + unsigned int MXtd : 1; /**< Extended ID mask (Xtd) of a packet object + which is used for packet receiving and filtering. */ + unsigned int reserved1 : 16; + } BIT; +} volatile IF2_MASK2_REG; + +/** + * @brief IF2 arbitration register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ID : 16; /**< Bits 15 to 0 of the packet ID of the packet object. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF2_ARBITRATION1_REG; + +/** + * @brief IF2 arbitration register 2. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ID : 13; /**< Bits 28 to 16 of the packet ID of the packet object.*/ + unsigned int Dir : 1; /**< Indicates the direction of the packet object.*/ + unsigned int Xtd : 1; /**< Indicates format of received and sent frames of packet object.*/ + unsigned int MsgVal : 1; /**< Packet object validity enable.*/ + unsigned int reserved0 : 16; + } BIT; +} volatile IF2_ARBITRATION2_REG; + +/** + * @brief IF2 packet control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DLC : 4; /**< Data length */ + unsigned int reserved0 : 3; + unsigned int EoB : 1; /**< Indicates the multi-packet receiving mode. */ + unsigned int TxRqst : 1; /**< Transfer request. */ + unsigned int RmtEn : 1; /**< Remote frame enable. */ + unsigned int RxIE : 1; /**< RX interrupt enable. */ + unsigned int TxIE : 1; /**< TX interrupt enable. */ + unsigned int Umask : 1; /**< Indicates whether the packet object uses the packet mask + which is used for packet receiving and filtering. */ + unsigned int IntPnd : 1; /**< Indicates the interrupt to be processed of the packet object. */ + unsigned int MsgLst : 1; /**< Indicates the packet loss flag of the packet object + This parameter is valid only when packet object is in receive direction. */ + unsigned int NewDat : 1; /**< Indicates the frame data ID of the packet object. */ + unsigned int reserved1 : 16; + } BIT; +} volatile IF2_MESSAGE_CONTROL_REG; + +/** + * @brief IF2 data A1 register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DATA0 : 8; /**< CAN frame data byte 0. */ + unsigned int DATA1 : 8; /**< CAN frame data byte 1. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF2_DATAA1_REG; + +/** + * @brief IF2 data A2 register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DATA2 : 8; /**< CAN frame data byte 2. */ + unsigned int DATA3 : 8; /**< CAN frame data byte 3. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF2_DATAA2_REG; + +/** + * @brief IF2 data B1 register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DATA4 : 8; /**< CAN frame data byte 4. */ + unsigned int DATA5 : 8; /**< CAN frame data byte 5. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF2_DATAB1_REG; + +/** + * @brief IF2 data B2 register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DATA6 : 8; /**< CAN frame data byte 6. */ + unsigned int DATA7 : 8; /**< CAN frame data byte 7. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF2_DATAB2_REG; + +/** + * @brief Transfer request status register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int TxRqst16_1 : 16; /**< Transfer request status. + Each bit of TxRqst16-1 corresponds to packet object 16-1. */ + unsigned int reserved0 : 16; + } BIT; +} volatile TRANSMISSION_REQUEST1_REG; + +/** + * @brief Transfer request status register 2. + */ +typedef union { + unsigned int reg; + struct { + unsigned int TxRqst32_17 : 16; /**< Transfer request status. + Each bit of TxRqst32-17 corresponds to packet objects 32-17. */ + unsigned int reserved0 : 16; + } BIT; +} volatile TRANSMISSION_REQUEST2_REG; + +/** + * @brief New data status register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int NewDat16_1 : 16; /**< New data write status. + NewDat16-1 Each bit corresponds to the packet object 16-1. */ + unsigned int reserved0 : 16; + } BIT; +} volatile NEW_DATA1_REG; + +/** + * @brief New data status register 2. + */ +typedef union { + unsigned int reg; + struct { + unsigned int NewDat32_17 : 16; /**< New data write status. + Each bit of NewDat32-17 corresponds to packet objects 32-17. */ + unsigned int reserved0 : 16; + } BIT; +} volatile NEW_DATA2_REG; + +/** + * @brief Interrupt pending status register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int IntPnd16_1 : 16; /**< Interrupt Pending Status. + Each bit of IntPnd16-1 corresponds to packet object 16-1. */ + unsigned int reserved0 : 16; + } BIT; +} volatile INTERRUPT_PENDING1_REG; + +/** + * @brief Interrupt pending status register 2. + */ +typedef union { + unsigned int reg; + struct { + unsigned int IntPnd32_17 : 16; /**< Interrupt Pending Status. + Each bit of IntPnd32-17 corresponds to packet objects 32-17. */ + unsigned int reserved0 : 16; + } BIT; +} volatile INTERRUPT_PENDING2_REG; + +/** + * @brief Packet validity status register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int MsgVal16_1 : 16; /**< Indicates the validity status of the packet object + Each bit of MsgVal16-1 corresponds to packet object 16-1. */ + unsigned int reserved0 : 16; + } BIT; +} volatile MESSAGE_VALID1_REG; + +/** + * @brief Packet validity status register 2. + */ +typedef union { + unsigned int reg; + struct { + unsigned int MsgVal32_17 : 16; /**< Indicates the validity status of the packet object. + Each bit of MsgVal32-17 corresponds to packet objects 32-17. */ + unsigned int reserved0 : 16; + } BIT; +} volatile MESSAGE_VALID2_REG; + +/** + * @brief Register mapping structure. + */ +typedef struct _CAN_RegStruct { + CAN_CONTROL_REG CAN_CONTROL; /**< CAN control register, Offset address: 0x00000000U. */ + CAN_STATUS_REG CAN_STATUS; /**< CAN status register. Offset address: 0x00000004U.*/ + CAN_ERROR_COUNTER_REG CAN_ERROR_COUNTER; /**< CAN error count register. Offset address: 0x00000008U.*/ + BIT_TIMING_REG BIT_TIMING; /**< Bit time register. Offset address: 0x0000000CU. */ + CAN_INTERRUPT_REG CAN_INTERRUPT; /**< CAN interrupt register. Offset address: 0x00000010U. */ + CAN_TEST_REG CAN_TEST; /**< CAN debug register. Offset address: 0x00000014U. */ + BRP_EXTENSION_REG BRP_EXTENSION; /**< BRP extension register. Offset address: 0x00000018U. */ + char space0[4]; + IF1_COMMAND_REQUEST_REG IF1_COMMAND_REQUEST; /**< IF1 command request register. Offset address: 0x00000020U. */ + IF1_COMMAND_MASK_REG IF1_COMMAND_MASK; /**< IF1 command mask register. Offset address: 0x00000024U. */ + IF1_MASK1_REG IF1_MASK1; /**< IF1 mask register 1. Offset address: 0x00000028U. */ + IF1_MASK2_REG IF1_MASK2; /**< IF1 mask register 2. Offset address: 0x0000002CU. */ + IF1_ARBITRATION1_REG IF1_ARBITRATION1; /**< IF1 arbitration register 1. Offset address: 0x00000030U. */ + IF1_ARBITRATION2_REG IF1_ARBITRATION2; /**< IF1 arbitration register 2. Offset address: 0x00000034U. */ + IF1_MESSAGE_CONTROL_REG IF1_MESSAGE_CONTROL; /**< IF1 packet control register. Offset address: 0x00000038U. */ + IF1_DATAA1_REG IF1_DATAA1; /**< IF1 data A1 register. Offset address: 0x0000003CU. */ + IF1_DATAA2_REG IF1_DATAA2; /**< IF1 data A2 register. Offset address: 0x00000040U. */ + IF1_DATAB1_REG IF1_DATAB1; /**< IF1 data B1 register. Offset address: 0x00000044U. */ + IF1_DATAB2_REG IF1_DATAB2; /**< IF1 data B2 register. Offset address: 0x00000048U. */ + char space1[52]; + IF2_COMMAND_REQUEST_REG IF2_COMMAND_REQUEST; /**< IF2 command request register. Offset address: 0x00000080U. */ + IF2_COMMAND_MASK_REG IF2_COMMAND_MASK; /**< IF2 command mask register. Offset address: 0x00000084U. */ + IF2_MASK1_REG IF2_MASK1; /**< IF2 mask register 1. Offset address: 0x00000088U. */ + IF2_MASK2_REG IF2_MASK2; /**< IF2 mask register 2. Offset address: 0x0000008CU. */ + IF2_ARBITRATION1_REG IF2_ARBITRATION1; /**< IF2 arbitration register 1. Offset address: 0x00000090U. */ + IF2_ARBITRATION2_REG IF2_ARBITRATION2; /**< IF2 arbitration register 2. Offset address: 0x00000094U. */ + IF2_MESSAGE_CONTROL_REG IF2_MESSAGE_CONTROL; /**< IF2 packet control register. Offset address: 0x00000098U.*/ + IF2_DATAA1_REG IF2_DATAA1; /**< IF2 data A1 register. Offset address: 0x0000009CU. */ + IF2_DATAA2_REG IF2_DATAA2; /**< IF2 data A2 register. Offset address: 0x000000A0U. */ + IF2_DATAB1_REG IF2_DATAB1; /**< IF2 data B1 register. Offset address: 0x000000A4U. */ + IF2_DATAB2_REG IF2_DATAB2; /**< IF2 data B2 register. Offset address: 0x000000A8U. */ + char space2[84]; + TRANSMISSION_REQUEST1_REG TRANSMISSION_REQUEST1;/**< Trans_request status reg 1. Offset address: 0x00000100U. */ + TRANSMISSION_REQUEST2_REG TRANSMISSION_REQUEST2;/**< Trans_request status reg 2. Offset address: 0x00000104U. */ + char space3[24]; + NEW_DATA1_REG NEW_DATA1; /**< New data status register 1. Offset address: 0x00000120U. */ + NEW_DATA2_REG NEW_DATA2; /**< New data status register 2. Offset address: 0x00000124U. */ + char space4[24]; + INTERRUPT_PENDING1_REG INTERRUPT_PENDING1; /**< INT pending status reg 1. Offset address: 0x00000140U. */ + INTERRUPT_PENDING2_REG INTERRUPT_PENDING2; /**< INT pending status reg 2. Offset address: 0x00000144U. */ + char space5[24]; + MESSAGE_VALID1_REG MESSAGE_VALID1; /**< Packet validity status reg 1. Offset address: 0x00000160U. */ + MESSAGE_VALID2_REG MESSAGE_VALID2; /**< Packet validity status reg 2. Offset address: 0x00000164U.*/ +} volatile CAN_RegStruct; +/** + * @} + */ + + +/** + * @brief Check CAN typemode parameter. + * @param typemode Work mode, @ref CAN_TypeMode + * @retval bool + */ +static inline bool IsCanMode(CAN_TypeMode typemode) +{ + return (typemode == CAN_MODE_NORMAL) || (typemode == CAN_MODE_TEST); +} + +/** + * @brief Check CAN prescalser parameter. + * @param prescalser Bit timing prescalser. + * @retval bool + */ +static inline bool IsCanPrescalser(unsigned int prescalser) +{ + return prescalser >= PRESCALSER_MIN && prescalser <= PRESCALSER_MAX; +} + +/** + * @brief Check CAN seg1Phase parameter. + * @param seg1Phase Phase buffer section 1, @ref CAN_Seg1_Phase + * @retval bool + */ +static inline bool IsCanSeg1phase(CAN_Seg1_Phase seg1Phase) +{ + return (seg1Phase >= CAN_SEG1_2TQ) && (seg1Phase <= CAN_SEG1_16TQ); +} + +/** + * @brief Check CAN seg2Phase parameter. + * @param seg2Phase Phase buffer section 2, @ref CAN_Seg2_Phase + * @retval bool + */ +static inline bool IsCanSeg2phase(CAN_Seg2_Phase seg2Phase) +{ + return (seg2Phase >= CAN_SEG2_1TQ) && (seg2Phase <= CAN_SEG2_8TQ); +} + +/** + * @brief Check CAN syncJumpWidth parameter. + * @param syncJumpWidth Sync jump width, @ref CAN_Sync_Jump_Width + * @retval bool + */ +static inline bool IsCanSJW(CAN_Sync_Jump_Width syncJumpWidth) +{ + return (syncJumpWidth >= CAN_SJW_1TQ) && (syncJumpWidth <= CAN_SJW_4TQ); +} + +/* Direct configuration layer */ +/** + * @brief CAN bit timing setting. + * @param canx CAN register base address. + * @param bitSetting CAN bit timing parameter, @ref Bit_Timing + * @retval None. + */ +static inline void DCL_CAN_BitSetting(CAN_RegStruct * const canx, Bit_Timing bitSetting) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + CAN_PARAM_CHECK_NO_RET(bitSetting.Tseg1 > 0); + canx->CAN_CONTROL.reg |= 0x00000041U; /* Bit_Timing setting, [0] and [6] bit need are set, others clear */ + unsigned int val = bitSetting.BRP; /* The prescalser is set to the lower 6 bits, [5:0] */ + val |= (bitSetting.SJW) << 6; /* The sjw needs to be shifted leftwards by 6 bits, range : 0~3 */ + val |= (bitSetting.Tseg1) << 8; /* The seg1Phase needs to be shifted leftwards by 8 bits, range : 1~15 */ + val |= (bitSetting.Tseg2) << 12; /* The seg2Phase needs to be shifted leftwards by 12 bits, range : 0~63 */ + canx->BIT_TIMING.reg = val; +} + +/** + * @brief CAN interrupt enable. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_EnableInterrupt(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.IE = BASE_CFG_ENABLE; +} + +/** + * @brief CAN interrupt disable. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_DisableInterrupt(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.IE = BASE_CFG_DISABLE; +} + +/** + * @brief CAN status interrupt enable. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_EnableStatusInterrupt(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.SIE = BASE_CFG_ENABLE; +} + +/** + * @brief CAN status interrupt disable. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_DisableStatusInterrupt(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.SIE = BASE_CFG_DISABLE; +} + +/** + * @brief CAN error interrupt enable. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_EnableErrorInterrupt(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.EIE = BASE_CFG_ENABLE; +} + +/** + * @brief CAN error interrupt disable. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_DisableErrorInterrupt(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.EIE = BASE_CFG_DISABLE; +} + +/** + * @brief Enable Automatic Retransmission + * @param canx CAN register base address. + * @retval None + */ +static inline void DCL_CAN_EnableAutoRetrans(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.DAR = BASE_CFG_DISABLE; +} + +/** + * @brief Disable Automatic Retransmission + * @param canx CAN register base address. + * @retval None + */ +static inline void DCL_CAN_DisableAutoRetrans(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.DAR = BASE_CFG_ENABLE; +} + +/** + * @brief Enable CAN test mode + * @param canx CAN register base address. + * @retval None + */ +static inline void DCL_CAN_EnableTestMode(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.Test = BASE_CFG_ENABLE; +} + +/** + * @brief Disable CAN test mode + * @param canx CAN register base address. + * @retval None + */ +static inline void DCL_CAN_DisableTestMode(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.Test = BASE_CFG_DISABLE; +} + +/** + * @brief Enable CAN bit timing config + * @param canx CAN register base address. + * @retval None + */ +static inline void DCL_CAN_EnableBitTimingConfig(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.CCE = BASE_CFG_ENABLE; +} + +/** + * @brief Disable CAN bit timing config + * @param canx CAN register base address. + * @retval None + */ +static inline void DCL_CAN_DisableBitTimingConfig(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.CCE = BASE_CFG_DISABLE; +} + +/** + * @brief Enable CAN Init. + * @param canx CAN register base address. + * @retval None + */ +static inline void DCL_CAN_EnableInit(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.Init = BASE_CFG_ENABLE; +} + +/** + * @brief Disable CAN init. + * @param canx CAN register base address. + * @retval None + */ +static inline void DCL_CAN_DisableInit(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.Init = BASE_CFG_DISABLE; +} + +/** + * @brief Initializes a specified packet object. + * @param canx CAN register base address. + * @param objID ID of message object. + * @retval None. + */ +static inline void DCL_CAN_InitObj(CAN_RegStruct * const canx, unsigned int objID) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + CAN_PARAM_CHECK_NO_RET((objID >= MESSAGE_NUMBER_MIN) && (objID <= MESSAGE_NUMBER_MAX)); + unsigned int busy; + canx->IF1_COMMAND_REQUEST.reg = objID; + do { + busy = canx->IF1_COMMAND_REQUEST.BIT.BUSY; + } while (busy == 0x00000001U); + return; +} + +/** + * @brief Get IF1 CAN status + * @param canx CAN register base address. + * @retval bool: 0 command is being executed, 1 command has been completed. + */ +static inline bool DCL_CAN_GetIF1Status(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_COMMAND_REQUEST.BIT.BUSY; +} + +/** + * @brief Setting IF1 message number + * @param canx CAN register base address. + * @param objID message number + * @retval None + */ +static inline void DCL_CAN_SetIF1MessageNumber(CAN_RegStruct * const canx, unsigned int objID) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + CAN_PARAM_CHECK_NO_RET((objID >= MESSAGE_NUMBER_MIN) && (objID <= MESSAGE_NUMBER_MAX)); + canx->IF1_COMMAND_REQUEST.BIT.MessageNumber = objID; +} + +/** + * @brief Query the CAN interrupt generation source. + * @param canx CAN register base address. + * @retval IDs of the packet objects for which the interrupt is generated. + */ +static inline unsigned int DCL_CAN_GetInterruptID(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->CAN_INTERRUPT.reg; +} + +/** + * @brief Confrguration command mask + * @param canx CAN register base address. + * @param maskValue Mask value for command register. + * @retval None + */ +static inline void DCL_CAN_ConfigMaskValue(CAN_RegStruct * const canx, unsigned int maskValue) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_COMMAND_MASK.reg = maskValue; +} + +/** + * @brief Get IF2 CAN status. + * @param canx CAN register base address. + * @retval bool: 0 command is being executed, 1 command has been completed. + */ +static inline bool DCL_CAN_GetIF2Status(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_COMMAND_REQUEST.BIT.BUSY; +} + +/** + * @brief Setting IF2 message number. + * @param canx CAN register base address. + * @param objID message number. + * @retval None + */ +static inline void DCL_CAN_SetIF2MessageNumber(CAN_RegStruct * const canx, unsigned int objID) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + CAN_PARAM_CHECK_NO_RET((objID >= MESSAGE_NUMBER_MIN) && (objID <= MESSAGE_NUMBER_MAX)); + canx->IF2_COMMAND_REQUEST.BIT.MessageNumber = objID; +} + +/** + * @brief Enable CAN loop back mode. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_EnableLoopBack(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_TEST.BIT.Lback = BASE_CFG_ENABLE; +} + +/** + * @brief Disable CAN loop back mode. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_DisableLoopBack(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_TEST.BIT.Lback = BASE_CFG_DISABLE; +} + +/** + * @brief Enable CAN silent mode. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_EnableSilent(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_TEST.BIT.Silent = BASE_CFG_ENABLE; +} + +/** + * @brief Disable CAN silent mode. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_DisableSilent(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_TEST.BIT.Silent = BASE_CFG_DISABLE; +} + +/** + * @brief Enable CAN basic mode. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_EnableBasic(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_TEST.BIT.Basic = BASE_CFG_ENABLE; +} + +/** + * @brief Disable CAN basic mode. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_DisableBasic(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_TEST.BIT.Basic = BASE_CFG_DISABLE; +} + +/** + * @brief Config IF1_ARBITRATION1. + * @param canx CAN register base address. + * @param maskValue Mask value for arbitration 1 register. + * @retval None. + */ +static inline void DCL_CAN_ConfigIF1ARBITRATION1(CAN_RegStruct * const canx, unsigned int maskValue) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_ARBITRATION1.reg = maskValue; +} + +/** + * @brief Low bit(0-15) obj ID number using IF1. + * @param canx CAN register base address. + * @retval unsigned int: Low bit ID number. + */ +static inline unsigned int DCL_CAN_GetIF1LoWBitObjNumber(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_ARBITRATION1.BIT.ID; +} + +/** + * @brief Config IF1_ARBITRATION2. + * @param canx CAN register base address. + * @param maskValue Mask value for arbitration 2 register. + * @retval None. + */ +static inline void DCL_CAN_ConfigIF1ARBITRATION2(CAN_RegStruct * const canx, unsigned int maskValue) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_ARBITRATION2.reg = maskValue; +} + +/** + * @brief Config IF2_ARBITRATION1. + * @param canx CAN register base address. + * @param maskValue Mask value for arbitration 1 register. + * @retval None. + */ +static inline void DCL_CAN_ConfigIF2ARBITRATION1(CAN_RegStruct * const canx, unsigned int maskValue) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_ARBITRATION1.reg = maskValue; +} + +/** + * @brief Low bit(0-15) obj ID number using IF2. + * @param canx CAN register base address. + * @retval unsigned int: Low bit ID number. + */ +static inline unsigned int DCL_CAN_GetIF2LoWBitObjNumber(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_ARBITRATION1.BIT.ID; +} + +/** + * @brief Config IF2_ARBITRATION2. + * @param canx CAN register base address. + * @param maskValue Mask value for arbitration 2 register. + * @retval None + */ +static inline void DCL_CAN_ConfigIF2ARBITRATION2(CAN_RegStruct * const canx, unsigned int maskValue) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_ARBITRATION2.reg = maskValue; +} + +/** + * @brief Get objection format of transmitted and received frame of IF2. + * @param canx CAN register base address. + * @retval bool: 0: Message object receives and transmits frames in standard format. + * @retval 1: Message object receives and transmits frames in extended format. + */ +static inline bool DCL_CAN_GetIF2ObjFormat(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_ARBITRATION2.BIT.Xtd; +} + +/** + * @brief Get objection format of transmitted and received frame of IF1. + * @param canx CAN register base address. + * @retval bool: 0: Message object receives and transmits frames in standard format. + * @retval 1: Message object receives and transmits frames in extended format. + */ +static inline bool DCL_CAN_GetIF1ObjFormat(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_ARBITRATION2.BIT.Xtd; +} + +/** + * @brief Get direction of transmitted and received frame of IF1. + * @param canx CAN register base address. + * @retval bool: 0: Message object is received in receive direction. + * @retval 1: Message object is in transmit direction. + */ +static inline bool DCL_CAN_GetIF1ObjDirection(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_ARBITRATION2.BIT.Dir; +} + +/** + * @brief Get the status of whether objection is valid using IF1. + * @param canx CAN register base address. + * @retval bool: 1 message object valid, 0 message object invalid. + */ +static inline bool DCL_CAN_GetIF1ObjStatus(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_ARBITRATION2.BIT.MsgVal; +} + +/** + * @brief high bit(16-28) obj ID number using IF1. + * @param canx CAN register base address. + * @retval unsigned int: high bit ID number. + */ +static inline unsigned int DCL_CAN_GetIF1HighBitObjNumber(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_ARBITRATION2.BIT.ID; +} + +/** + * @brief Get direction of transmitted and received frame of IF2. + * @param canx CAN register base address. + * @retval bool: 0: Message object is received in receive direction. + * @retval 1: Message object is in transmit direction. + */ +static inline bool DCL_CAN_GetIF2ObjDirection(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_ARBITRATION2.BIT.Dir; +} + +/** + * @brief Get the status of whether objection is valid using IF2. + * @param canx CAN register base address. + * @retval bool: 1: message object valid. + * @retval 0: message object invalid. + */ +static inline bool DCL_CAN_GetIF2ObjStatus(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_ARBITRATION2.BIT.MsgVal; +} + +/** + * @brief high bit(16-28) obj ID number using IF2 + * @param canx CAN register base address. + * @retval unsigned int: high bit ID number + */ +static inline unsigned int DCL_CAN_GetIF2HighBitObjNumber(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_ARBITRATION2.BIT.ID; +} + +/** + * @brief Get obj data length using IF2. + * @param canx CAN register base address. + * @retval unsigned int: data length + */ +static inline unsigned int DCL_CAN_GetIF2ObjDataLength(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_MESSAGE_CONTROL.BIT.DLC; +} + +/** + * @brief config message control using IF2 + * @param canx CAN register base address. + * @param messageControlValue Message control command value. + * @retval None + */ +static inline void DCL_CAN_ConfigIF2MessageControl(CAN_RegStruct * const canx, unsigned int messageControlValue) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_MESSAGE_CONTROL.reg = messageControlValue; +} + +/** + * @brief Get obj data length using IF1 + * @param canx CAN register base address. + * @retval unsigned int: message object data length + */ +static inline unsigned int DCL_CAN_GetIF1ObjDataLength(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_MESSAGE_CONTROL.BIT.DLC; +} + +/** + * @brief config message control using IF1 + * @param canx CAN register base address. + * @param messageControlValue Message control command value. + * @retval None + */ +static inline void DCL_CAN_ConfigIF1MessageControl(CAN_RegStruct * const canx, unsigned int messageControlValue) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_MESSAGE_CONTROL.reg = messageControlValue; +} + +/** + * @brief Get A1 data using IF2 + * @param canx CAN register base address. + * @retval byte 1 and byte 2 of data + */ +static inline unsigned int DCL_CAN_GetIF2ObjDataA1(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_DATAA1.reg; +} + +/** + * @brief Set A1 data using IF2 + * @param canx CAN register base address. + * @param dataA1 Data of A1. + * @retval None. + */ +static inline void DCL_CAN_SetIF2ObjDataA1(CAN_RegStruct * const canx, unsigned int dataA1) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_DATAA1.reg = dataA1; +} + +/** + * @brief Get A2 data using IF2 + * @param canx CAN register base address. + * @retval byte 3 and byte 4 of data + */ +static inline unsigned int DCL_CAN_GetIF2ObjDataA2(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_DATAA2.reg; +} + +/** + * @brief Set A2 data using IF2 + * @param canx CAN register base address. + * @param dataA2 Data of A2. + * @retval None. + */ +static inline void DCL_CAN_SetIF2ObjDataA2(CAN_RegStruct * const canx, unsigned int dataA2) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_DATAA2.reg = dataA2; +} + +/** + * @brief Get B1 data using IF2 + * @param canx CAN register base address. + * @retval byte 5 and byte 6 of data + */ +static inline unsigned int DCL_CAN_GetIF2ObjDataB1(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_DATAB1.reg; +} + +/** + * @brief Set B1 data using IF2, set byte 5 and byte 6 of data. + * @param canx CAN register base address. + * @param dataB1 Data of B1. + * @retval None. + */ +static inline void DCL_CAN_SetIF2ObjDataB1(CAN_RegStruct * const canx, unsigned int dataB1) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_DATAB1.reg = dataB1; +} + +/** + * @brief Get B2 data using IF2 + * @param canx CAN register base address. + * @retval byte 7 and byte 8 of data + */ +static inline unsigned int DCL_CAN_GetIF2ObjDataB2(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_DATAB2.reg; +} + +/** + * @brief Set B2 data using IF2, set byte 7 and byte 8 of data + * @param canx CAN register base address. + * @param dataB2 Data of B2. + * @retval None. + */ +static inline void DCL_CAN_SetIF2ObjDataB2(CAN_RegStruct * const canx, unsigned int dataB2) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_DATAB2.reg = dataB2; +} + +/** + * @brief Get A1 data using IF1. + * @param canx CAN register base address. + * @retval byte 1 and byte 2 of data. + */ +static inline unsigned int DCL_CAN_GetIF1ObjDataA1(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_DATAA1.reg; +} + +/** + * @brief Set A1 data using IF1, Set byte 1 and byte 2 of data + * @param canx CAN register base address. + * @param dataA1 Data of A1. + * @retval None. + */ +static inline void DCL_CAN_SetIF1ObjDataA1(CAN_RegStruct * const canx, unsigned int dataA1) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_DATAA1.reg = dataA1; +} + +/** + * @brief Get A2 data using IF1 + * @param canx CAN register base address. + * @retval byte 3 and byte 4 of data + */ +static inline unsigned int DCL_CAN_GetIF1ObjDataA2(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_DATAA2.reg; +} + +/** + * @brief Set A2 data using IF1, Set byte 3 and byte 4 of data + * @param canx CAN register base address. + * @param dataA2 Data of A2. + * @retval None. + */ +static inline void DCL_CAN_SetIF1ObjDataA2(CAN_RegStruct * const canx, unsigned int dataA2) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_DATAA2.reg = dataA2; +} + +/** + * @brief Get B1 data using IF1 + * @param canx CAN register base address. + * @retval byte 5 and byte 6 of data + */ +static inline unsigned int DCL_CAN_GetIF1ObjDataB1(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_DATAB1.reg; +} + +/** + * @brief Set B1 data using IF1, Set byte 5 and byte 6 of data + * @param canx CAN register base address. + * @param dataB1 Data of B1. + * @retval None. + */ +static inline void DCL_CAN_SetIF1ObjDataB1(CAN_RegStruct * const canx, unsigned int dataB1) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_DATAB1.reg = dataB1; +} + +/** + * @brief Get B2 data using IF1 + * @param canx CAN register base address. + * @retval byte 7 and byte 8 of data + */ +static inline unsigned int DCL_CAN_GetIF1ObjDataB2(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_DATAB2.reg; +} + +/** + * @brief Set B2 data using IF1, Set byte 7 and byte 8 of data + * @param canx CAN register base address. + * @param dataB2 Data of B2. + * @retval None. + */ +static inline void DCL_CAN_SetIF1ObjDataB2(CAN_RegStruct * const canx, unsigned int dataB2) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_DATAB2.reg = dataB2; +} + +/** + * @brief Set IF2 mask + * @param canx CAN register base address. + * @param mask Mask value + * @retval None + */ +static inline void DCL_CAN_SetIF2Mask(CAN_RegStruct * const canx, unsigned int mask) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_MASK2.reg = mask; +} + +/** + * @brief Set objection mask using IF2 + * @param canx CAN register base address. + * @param maskChg Mask value. + * @retval None + */ +static inline void DCL_CAN_SetIF2ObjFilterMask(CAN_RegStruct * const canx, unsigned int maskChg) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_MASK1.reg = maskChg; +} + +/** + * @brief Set IF1 mask + * @param canx CAN register base address. + * @param mask Mask value. + * @retval None + */ +static inline void DCL_CAN_SetIF1Mask(CAN_RegStruct * const canx, unsigned int mask) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_MASK2.reg = mask; +} + +/** + * @brief Set objection mask using IF1 + * @param canx CAN register base address. + * @param maskChg Mask value. + * @retval None + */ +static inline void DCL_CAN_SetIF1ObjFilterMask(CAN_RegStruct * const canx, unsigned int maskChg) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_MASK1.reg = maskChg; +} + +/** + * @brief Set command mask using IF2.return + * @param canx CAN register base address. + * @param commandMask command mask value. + * @retval None + */ +static inline void DCL_CAN_SetIF2CommandMask(CAN_RegStruct * const canx, unsigned int commandMask) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_COMMAND_MASK.reg = commandMask; +} + +/** + * @brief Get Can Status + * @param canx CAN register base address. + * @retval Overall status of the CAN. + */ +static inline unsigned int DCL_CAN_GetStatus(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->CAN_STATUS.reg; +} + +/** + * @brief Get object interrupt ID. + * @param canx CAN register base address. + * @retval Interrupt status of obj 1 to 16 + */ +static inline unsigned int DCL_CAN_GetInterruptPend1(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->INTERRUPT_PENDING1.reg; +} + +/** + * @brief Get objects interrupt ID. + * @param canx CAN register base address. + * @retval Interrupt status of obj 17 to 32 + */ +static inline unsigned int DCL_CAN_GetInterruptPend2(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->INTERRUPT_PENDING2.reg; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_CAN_IP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/can/src/can.c b/vendor/xinlingyu_92_3061M/Project/drivers/can/src/can.c new file mode 100644 index 0000000000000000000000000000000000000000..13a403cecbdfe15a30ce7e054d3c7cb194e84114 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/can/src/can.c @@ -0,0 +1,663 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file can.c + * @author MCU Driver Team + * @brief CAN module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the CAN. + * + Initialization and de-initialization functions + * + Sending and receiving CAN data frames functions + * + Interrupt handling function and user registration callback function + * + CAN data frame filtering function + */ + +/* Includes ------------------------------------------------------------------*/ +#include "can.h" +#include "interrupt.h" + +/* Macro definitions ---------------------------------------------------------*/ + +#define BOUND_ID 24 /* ObjID 1 ~ 24 used for receive, 25 ~ 32 used for send */ +#define CAN_OBJ_MAXNUM 32 + +#define CAN_EFF_FLAG 0x80000000 /* EFF/SFF is set in the MSB */ +#define CAN_RTR_FLAG 0x40000000 /* Remote transmission request */ +#define CAN_ERR_FLAG 0x20000000 /* Error message frame */ + +/* Valid bits in CAN ID for frame formats */ +#define CAN_STD_MASK 0x000007FF /* Standard frame format (SFF) */ +#define CAN_EXT_MASK 0x1FFFFFFF /* Extended frame format (EFF) */ +#define CAN_ERR_MASK 0x1FFFFFFF /* Omit EFF, RTR, ERR flags */ +#define CAN_TIME_WAIT 11 /* CAN initialization wait time */ + +static unsigned int g_stdRecvMap = 0x00000FFF; +static unsigned int g_extRecvMap = 0x00FFF000; +static unsigned int g_allSendMap = 0xFF000000; +static unsigned int g_allRecvMap = 0x00FFFFFF; + +static unsigned int g_msgObj[CAN_OBJ_MAXNUM] = {0}; + +static BASE_StatusType CAN_ReadCallback(CAN_Handle *canHandle, unsigned int objId); +static BASE_StatusType CAN_ConfigReadReq(CAN_Handle *canHandle, unsigned int objId); +static BASE_StatusType WriteFinishClear(CAN_Handle *canHandle, unsigned int objId); +static void CAN_ReceiveFilter(CAN_Handle *canHandle, const CAN_FilterConfigure *filterConfigure, unsigned int objId); +static void CAN_WaitTime(CAN_Handle *canHandle); +static void CAN_AutoRetrans(CAN_Handle *canHandle); + +/* Initialization and de-initialization functions ----------------------------*/ +/** + * @brief Wait 11 CAN bit time. + * @param canHandle CAN handle. + * @retval void + */ +static void CAN_WaitTime(CAN_Handle *canHandle) +{ + /* CAN clock frequency */ + unsigned int canFrep = HAL_CRG_GetIpFreq((void *)canHandle->baseAddress) / (canHandle->prescalser); + unsigned int waitTime = canFrep / (1 + canHandle->seg1Phase + canHandle->seg2Phase); + /* 1000000 equals 1 us to wait for 11 time bits */ + unsigned int waitTimeCount = CAN_TIME_WAIT * ((1000000) / waitTime); + BASE_FUNC_DelayUs(waitTimeCount); +} + +/** + * @brief CAN Setting Automatic Retransmission. + * @param canHandle CAN handle. + * @retval void + */ +static void CAN_AutoRetrans(CAN_Handle *canHandle) +{ + if (canHandle->autoRetrans == BASE_CFG_DISABLE) { + /* Turn off auto retransmission */ + canHandle->baseAddress->CAN_CONTROL.BIT.DAR = BASE_CFG_ENABLE; + } else { + /* Turn on auto retransmission */ + canHandle->baseAddress->CAN_CONTROL.BIT.DAR = BASE_CFG_DISABLE; + } +} + +/** + * @brief Initialize the CAN hardware configuration and configure parameters based on the specified handle. + * @param canHandle CAN handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT + */ +BASE_StatusType HAL_CAN_Init(CAN_Handle *canHandle) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + CAN_PARAM_CHECK_WITH_RET(IsCanMode(canHandle->typeMode), BASE_STATUS_ERROR); /* Check initialization parameters */ + CAN_PARAM_CHECK_WITH_RET(IsCanPrescalser(canHandle->prescalser), BASE_STATUS_ERROR); + CAN_PARAM_CHECK_WITH_RET(IsCanSeg1phase(canHandle->seg1Phase), BASE_STATUS_ERROR); + CAN_PARAM_CHECK_WITH_RET(IsCanSeg2phase(canHandle->seg2Phase), BASE_STATUS_ERROR); + CAN_PARAM_CHECK_WITH_RET(IsCanSJW(canHandle->sjw), BASE_STATUS_ERROR); + unsigned int busy; + /* Step1: init enable */ + canHandle->baseAddress->CAN_CONTROL.BIT.Init = BASE_CFG_ENABLE; + /* Step2: configuration command mask register, set 0xF3 to write into packet objects */ + canHandle->baseAddress->IF1_COMMAND_MASK.reg = 0xF3; + /* Step3 ~ 4: init packet object 1 ~ 32 */ + for (int i = 1; i <= CAN_OBJ_MAXNUM; i++) { + canHandle->baseAddress->IF1_COMMAND_REQUEST.reg = i; + do { + busy = canHandle->baseAddress->IF1_COMMAND_REQUEST.BIT.BUSY; + } while (busy == BASE_CFG_ENABLE); + } + /* Step5: Bit_Timing setting enable, [0]bit and [6]bit need are set, others clear */ + canHandle->baseAddress->CAN_CONTROL.reg = 0x41; + /* Step6: Bit_Timing configuration */ + unsigned int val = canHandle->prescalser - 1; /* The prescalser is set to the lower 6 bits, [5:0] */ + val |= (canHandle->sjw - 1) << 6; /* The sjw needs to be shifted leftwards by 6 bits, [7:6] */ + val |= (canHandle->seg1Phase - 1) << 8; /* The seg1Phase needs to be shifted leftwards by 8 bits, [11:8] */ + val |= (canHandle->seg2Phase - 1) << 12; /* The seg2Phase needs to be shifted leftwards by 12 bits, [14:12] */ + canHandle->baseAddress->BIT_TIMING.reg = val; + /* Step7: setting interrupt configuration, error interrupt and module interrupt */ + canHandle->baseAddress->CAN_CONTROL.reg = 0x0B; + /* Step8: setting automatic retransmission */ + CAN_AutoRetrans(canHandle); + /* Step9: finish init */ + if (canHandle->typeMode == CAN_MODE_TEST && canHandle->testModeConfigure != NULL) { + canHandle->baseAddress->CAN_CONTROL.BIT.Test = BASE_CFG_ENABLE; + canHandle->baseAddress->CAN_TEST.BIT.Lback = canHandle->testModeConfigure->loopBack; + canHandle->baseAddress->CAN_TEST.BIT.Silent = canHandle->testModeConfigure->silent; + canHandle->baseAddress->CAN_TEST.BIT.Basic = canHandle->testModeConfigure->basic; + } + canHandle->baseAddress->CAN_CONTROL.BIT.Init = BASE_CFG_DISABLE; + /* Each packet object configuration before read CAN frame */ + for (int i = 1; i <= CAN_OBJ_MAXNUM; i++) { + if (i <= BOUND_ID) { + CAN_ConfigReadReq(canHandle, i); /* The default configuration is no filter receive */ + } + g_msgObj[i - 1] = 0; + } + CAN_WaitTime(canHandle); + canHandle->state = CAN_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief DeInitialize the CAN and restoring default parameters based on the specified handle. + * @param canHandle CAN handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT + */ +BASE_StatusType HAL_CAN_DeInit(CAN_Handle *canHandle) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + canHandle->baseAddress->CAN_CONTROL.reg = BASE_CFG_DISABLE; /* Disables the control register. */ + canHandle->baseAddress->CAN_STATUS.reg = BASE_CFG_DISABLE; /* Clear the status of the CAN. */ + canHandle->userCallBack.ReadFinishCallBack = NULL; /* Clear all user call back function. */ + canHandle->userCallBack.TransmitErrorCallBack = NULL; + canHandle->userCallBack.WriteFinishCallBack = NULL; + canHandle->state = CAN_STATE_NONE_INIT; /* Set the CAN to the uninitialized state. */ + return BASE_STATUS_OK; +} + +/** + * @brief CAN error status. + * @param canHandle CAN handle. + * @retval CAN_ErrorStatus: + * CAN_PASSIVE_ERROR: CAN is in passive error. + * CAN_ACTIVE_ERROR: CAN is in active error. + */ +CAN_ErrorStatus HAL_CAN_GetErrorStatus(CAN_Handle *canHandle) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + CAN_STATUS_REG canStatus; + /* CAN error status reg. */ + canStatus.reg = canHandle->baseAddress->CAN_STATUS.reg; + if (canStatus.BIT.Epass == BASE_CFG_ENABLE) { + return CAN_PASSIVE_ERROR; /* Passive error */ + } + return CAN_ACTIVE_ERROR; /* active error */ +} + +/** + * @brief Return the specified CAN error status code. + * @param canHandle CAN handle. + * @retval CAN bus error status. @ref CAN_ERROR_StatusCode + * @note CAN_ERROR_NONE -- No error normal. + * CAN_ERROR_PADDING -- Filling error. + * CAN_ERROR_FORMAL -- The format is incorrect. + * CAN_ERROR_ANSWER -- response error. + * CAN_ERROR_BIT1 -- Bit 1 error. + * CAN_ERROR_BIT0 -- bit 0 error. + * CAN_ERROR_CRC -- CRC error. + */ +unsigned int HAL_CAN_GetErrorStatusCode(CAN_Handle *canHandle) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + CAN_STATUS_REG canStatus; + canStatus.reg = canHandle->baseAddress->CAN_STATUS.reg; /* Obtains the full status of the CAN. */ + unsigned int errorStatus = canStatus.BIT.LEC; + return errorStatus; +} + +/** + * @brief CAN Bus-off status. + * @param canHandle CAN handle. + * @retval CAN Bus off status: + * CAN_BUSOFF_ON: In bus-off state. + * CAN_BUSOFF_OFF: Not in the bus-off state. + */ +CAN_BusOffStatus HAL_CAN_GetBusOffStatus(CAN_Handle *canHandle) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + CAN_STATUS_REG canStatus; /* CAN status reg. */ + canStatus.reg = canHandle->baseAddress->CAN_STATUS.reg; /* Obtains all status of the CAN. */ + if (canStatus.BIT.Boff == BASE_CFG_ENABLE) { + return CAN_BUSOFF_ON; + } + return CAN_BUSOFF_OFF; +} + +/** + * @brief CAN message receive status. + * @param canHandle CAN handle. + * @retval CAN message receive status: + * CAN_MESSAGE_RECEIVE_OK: message receive successful. + * CAN_MESSAGE_RECEIVE_ERROR: message receive failed. + */ +CAN_MessageReceiveStatus HAL_CAN_MessageReceiveStatus(CAN_Handle *canHandle) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + CAN_STATUS_REG canStatus; + /* Obtains the CAN RX status. */ + canStatus.reg = canHandle->baseAddress->CAN_STATUS.reg; + if (canStatus.BIT.RxOk == BASE_CFG_ENABLE) { + return CAN_MESSAGE_RECEIVE_OK; /* CAN receive succeeded. */ + } + return CAN_MESSAGE_RECEIVE_ERROR; +} + +/** + * @brief CAN message send status. + * @param canHandle CAN handle. + * @retval CAN message send status: + * CAN_MESSAGE_SEND_OK: message send successful. + * CAN_MESSAGE_SEND_ERROR: message send failed. + */ +CAN_MessageSendStatus HAL_CAN_MessageSendStatus(CAN_Handle *canHandle) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + CAN_STATUS_REG canStatus; + /* Obtains the CAN RX status. */ + canStatus.reg = canHandle->baseAddress->CAN_STATUS.reg; + if (canStatus.BIT.TxOk == BASE_CFG_ENABLE) { + return CAN_MESSAGE_SEND_OK; /* CAN send succeeded. */ + } + return CAN_MESSAGE_SEND_ERROR; +} + +/** + * @brief Padding can data frame 8-bit data. + * @param canHandle CAN handle. + * @param data Pointer address of the CAN data frame to be sent, @ref CANFrame + * @retval None. + */ +static void WriteData(CAN_Handle *canHandle, CANFrame *data) +{ + IF1_DATAA1_REG dataA1; + dataA1.BIT.DATA0 = data->frame[0]; /* Data of bit 0 */ + dataA1.BIT.DATA1 = data->frame[1]; /* Data of bit 0 */ + canHandle->baseAddress->IF1_DATAA1 = dataA1; + IF1_DATAA2_REG dataA2; + dataA2.BIT.DATA2 = data->frame[2]; /* Data of bit 2 */ + dataA2.BIT.DATA3 = data->frame[3]; /* Data of bit 3 */ + canHandle->baseAddress->IF1_DATAA2 = dataA2; + IF1_DATAB1_REG dataB1; + dataB1.BIT.DATA4 = data->frame[4]; /* Data of bit 4 */ + dataB1.BIT.DATA5 = data->frame[5]; /* Data of bit 5 */ + canHandle->baseAddress->IF1_DATAB1 = dataB1; + IF1_DATAB2_REG dataB2; + dataB2.BIT.DATA6 = data->frame[6]; /* Data of bit 6 */ + dataB2.BIT.DATA7 = data->frame[7]; /* Data of bit 7 */ + canHandle->baseAddress->IF1_DATAB2 = dataB2; +} + +/** + * @brief Send data immediately. + * @param canHandle CAN handle. + * @param data Pointer address of the CAN data frame to be sent, @ref CANFrame + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT + * @note: + * IF1 and IF2 have the same functions. To facilitate management, + * IF1 is used for sending and IF2 is used for receiving. + */ +BASE_StatusType HAL_CAN_Write(CAN_Handle *canHandle, CANFrame *data) +{ + CAN_ASSERT_PARAM(canHandle != NULL && data != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + CAN_PARAM_CHECK_WITH_RET(data->dataLength <= 8, BASE_STATUS_ERROR); /* CAN frame length: 1 ~ 8 */ + if (canHandle->state != CAN_STATE_READY) { + return BASE_STATUS_BUSY; + } + canHandle->state = CAN_STATE_BUSY_TX; + unsigned int objId = 0; + unsigned int id; + for (int i = BOUND_ID + 1; i <= CAN_OBJ_MAXNUM; i++) { + if (g_msgObj[i - 1] == 0) { + g_msgObj[i - 1] = 1; + objId = i; + break; + } + } + if (objId == 0) { + return BASE_STATUS_ERROR; + } + /* Step1: write id into register arbitration according frame type */ + switch (data->type) { + case CAN_TYPEFRAME_STD_DATA: /* Standard data frame */ + id = (data->CANId & CAN_STD_MASK) << 2; /* Bit[12:2] = CANId */ + id |= 0xA000; /* [15:13] = 0x05 */ + canHandle->baseAddress->IF1_ARBITRATION1.reg = 0x00; + break; + case CAN_TYPEFRAME_EXT_DATA: /* Extended data frame */ + id = (data->CANId & CAN_EXT_MASK) >> 16; /* Bit[12:0] = CANId(28bit~16bit) */ + id |= 0xE000; /* [15:13] = 0x07 */ + canHandle->baseAddress->IF1_ARBITRATION1.reg = (data->CANId & 0xFFFF); /* write lower 16bits CANId */ + break; + case CAN_TYPEFRAME_STD_REMOTE: /* Standard remote frame */ + id = (data->CANId & CAN_EXT_MASK) << 2; /* Bit[12:2] = CANId */ + id |= 0x8000; /* [15:13] = 0x04 */ + canHandle->baseAddress->IF1_ARBITRATION1.reg = 0x00; + break; + case CAN_TYPEFRAME_EXT_REMOTE: /* Extended remote frame */ + id = (data->CANId & CAN_EXT_MASK) >> 16; /* Bit[12:0] = CANId(28bit~16bit) */ + id |= 0xC000; /* [15:13] = 0x06 */ + canHandle->baseAddress->IF1_ARBITRATION1.reg = (data->CANId & 0xFFFF); /* write lower 16bits CANId */ + break; + default: + return BASE_STATUS_ERROR; + } + canHandle->baseAddress->IF1_ARBITRATION2.reg = id; + /* Step2: setting mask register 2 */ + canHandle->baseAddress->IF1_MASK2.reg = 0x8000; + /* Step3: setting mask register 1 */ + canHandle->baseAddress->IF1_MASK1.reg = 0x0000; + /* Step4: setting message control register */ + canHandle->baseAddress->IF1_MESSAGE_CONTROL.reg |= 0x8980; + canHandle->baseAddress->IF1_MESSAGE_CONTROL.BIT.DLC = data->dataLength; + /* Step5: write data to be sent */ + WriteData(canHandle, data); + /* Step6: send configuration to packet objects */ + canHandle->baseAddress->IF1_COMMAND_MASK.reg = 0xF3; + /* Step7: write IF1 request command */ + canHandle->baseAddress->IF1_COMMAND_REQUEST.BIT.MessageNumber = objId; + canHandle->state = CAN_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief Interrupt receiving callback function. + * @param canHandle CAN handle. + * @param objId Indicates the packet object ID. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +static BASE_StatusType CAN_ReadCallback(CAN_Handle *canHandle, unsigned int objId) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + CAN_PARAM_CHECK_WITH_RET(canHandle->rxFrame != NULL, BASE_STATUS_ERROR); + CAN_PARAM_CHECK_WITH_RET((objID >= MESSAGE_NUMBER_MIN) && (objID <= MESSAGE_NUMBER_MAX), BASE_STATUS_ERROR); + unsigned int busy, id, idLow, idHigh, extendedFrame, remoteFrame; + /* Step1: setting request transfer to packet object */ + canHandle->baseAddress->IF2_COMMAND_MASK.reg = 0x7F; /* 0x7F indicates reading data from the packet object */ + /* Step2: Request specififed packet object */ + canHandle->baseAddress->IF2_COMMAND_REQUEST.BIT.MessageNumber = objId; + do { + busy = canHandle->baseAddress->IF2_COMMAND_REQUEST.BIT.BUSY; + } while (busy != 0x00); + /* Step3: Obtains packet information */ + extendedFrame = canHandle->baseAddress->IF2_ARBITRATION2.BIT.Xtd; + remoteFrame = canHandle->baseAddress->IF2_ARBITRATION2.BIT.Dir; + if (extendedFrame == BASE_CFG_ENABLE) { + idLow = canHandle->baseAddress->IF2_ARBITRATION1.BIT.ID; + idHigh = canHandle->baseAddress->IF2_ARBITRATION2.BIT.ID; + id = idLow; + idHigh <<= 16; /* High 16 bits ID */ + id |= idHigh; + canHandle->rxFrame->CANId = id; + id |= CAN_EFF_FLAG; + if (remoteFrame == BASE_CFG_ENABLE) { + id |= CAN_RTR_FLAG; + canHandle->rxFrame->type = CAN_TYPEFRAME_EXT_REMOTE; + } else { + canHandle->rxFrame->type = CAN_TYPEFRAME_EXT_DATA; + } + } else { + id = canHandle->baseAddress->IF2_ARBITRATION2.BIT.ID; + id >>= 2; /* 2: Standard frame CAN id. */ + canHandle->rxFrame->CANId = id; + if (remoteFrame == BASE_CFG_ENABLE) { + id |= CAN_RTR_FLAG; + canHandle->rxFrame->type = CAN_TYPEFRAME_STD_REMOTE; + } else { + canHandle->rxFrame->type = CAN_TYPEFRAME_STD_DATA; + } + } + canHandle->rxFrame->dataLength = canHandle->baseAddress->IF2_MESSAGE_CONTROL.BIT.DLC; + canHandle->rxFrame->frame[0] = canHandle->baseAddress->IF2_DATAA1.BIT.DATA0; /* Data of bit 0 */ + canHandle->rxFrame->frame[1] = canHandle->baseAddress->IF2_DATAA1.BIT.DATA1; /* Data of bit 1 */ + canHandle->rxFrame->frame[2] = canHandle->baseAddress->IF2_DATAA2.BIT.DATA2; /* Data of bit 2 */ + canHandle->rxFrame->frame[3] = canHandle->baseAddress->IF2_DATAA2.BIT.DATA3; /* Data of bit 3 */ + canHandle->rxFrame->frame[4] = canHandle->baseAddress->IF2_DATAB1.BIT.DATA4; /* Data of bit 4 */ + canHandle->rxFrame->frame[5] = canHandle->baseAddress->IF2_DATAB1.BIT.DATA5; /* Data of bit 5 */ + canHandle->rxFrame->frame[6] = canHandle->baseAddress->IF2_DATAB2.BIT.DATA6; /* Data of bit 6 */ + canHandle->rxFrame->frame[7] = canHandle->baseAddress->IF2_DATAB2.BIT.DATA7; /* Data of bit 7 */ + return BASE_STATUS_OK; +} + +/** + * @brief CAN Bus receive filtering configuration. + * @param canHandle CAN handle. + * @param CAN_FilterConfigure handle of filtering configuration, @ref CAN_FilterConfigure + * @param objId Indicates the packet object ID. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +static void CAN_ReceiveFilter(CAN_Handle *canHandle, const CAN_FilterConfigure *filterConfigure, unsigned int objId) +{ + unsigned int id, idChg; + unsigned int mask, maskChg; + idChg = filterConfigure->filterID & 0xFFFF; + maskChg = filterConfigure->filterMask & 0xFFFF; + switch (filterConfigure->receiveType) { + case CAN_FILTERFRAME_STD_DATA: + id = (filterConfigure->filterID & CAN_STD_MASK) << 2; /* Bit[12:2] = CANId */ + id |= 0x8000; + idChg = 0x0000; + /* Shift left by 2 bits. The upper 11 bits of [12:0] are used */ + mask = (filterConfigure->filterMask & CAN_STD_MASK) << 2; + mask |= 0xC000; + maskChg = 0x0000; + break; + case CAN_FILTERFRAME_EXT_DATA: + id = (filterConfigure->filterID & CAN_EXT_MASK) >> 16; /* Bit[12:0] = CANId(28bit ~ 16bit) */ + id |= 0xC000; + /* write lower 16bits CANId */ + mask = (filterConfigure->filterMask & CAN_EXT_MASK) >> 16; /* Remove the lower 16 bits */ + mask |= 0xC000; + break; + case CAN_FILTERFRAME_STD_EXT_DATA: + id = (filterConfigure->filterID & CAN_EXT_MASK) >> 16; /* Remove the lower 16 bits */ + id |= 0xC000; + mask = (filterConfigure->filterMask & CAN_EXT_MASK) >> 16; /* Remove the lower 16 bits */ + mask |= 0x4000; /* [15]MXtd = 0 */ + break; + default: + return; + } + canHandle->baseAddress->IF2_ARBITRATION2.reg = id; + canHandle->baseAddress->IF2_ARBITRATION1.reg = idChg; + canHandle->baseAddress->IF2_MASK2.reg = mask; + canHandle->baseAddress->IF2_MASK1.reg = maskChg; + if (canHandle->rxFIFODepth > BOUND_ID) { + canHandle->rxFIFODepth = BOUND_ID; + } + if (objId < canHandle->rxFIFODepth) { /* packet objects form the receiving FIFO */ + canHandle->baseAddress->IF2_MESSAGE_CONTROL.reg = 0x1408; /* EOB is set 0 */ + } else { + canHandle->baseAddress->IF2_MESSAGE_CONTROL.reg = 0x1488; /* EOB is set 1 */ + } + /* Step5: send configuration to packet objects */ + canHandle->baseAddress->IF2_COMMAND_MASK.reg = 0x00F3; + /* Step6: write IF2 request command */ + canHandle->baseAddress->IF2_COMMAND_REQUEST.BIT.MessageNumber = objId; + canHandle->baseAddress->IF2_COMMAND_REQUEST.BIT.BUSY = 0x01; +} + +/** + * @brief Receive CAN data frames asynchronously. + * @param canHandle CAN handle. + * @param data Address for storing CAN data frames, @ref CANFrame + * @param filterConfigure handle of filtering configuration, @ref CAN_FilterConfigure + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_CAN_ReadIT(CAN_Handle *canHandle, CANFrame *data, CAN_FilterConfigure *filterConfigure) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + CAN_PARAM_CHECK_WITH_RET(data != NULL, BASE_STATUS_ERROR); + CAN_PARAM_CHECK_WITH_RET(filterConfigure != NULL, BASE_STATUS_ERROR); + if (canHandle->state != CAN_STATE_READY) { + return BASE_STATUS_BUSY; + } + canHandle->state = CAN_STATE_BUSY_RX; + canHandle->rxFrame = data; + canHandle->rxFilter = filterConfigure; + for (int i = 1; i <= BOUND_ID; i++) { + CAN_ReceiveFilter(canHandle, filterConfigure, i); + } + canHandle->state = CAN_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief Pre-configuration of Receive CAN Data Frames. + * @param canHandle CAN handle. + * @param objId Indicates the packet object ID. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +static BASE_StatusType CAN_ConfigReadReq(CAN_Handle *canHandle, unsigned int objId) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + unsigned int map = 1; + map <<= objId - 1; + /* Step1: write id into register arbitration according frame type */ + if ((map & g_stdRecvMap) != 0) { /* STD DATA FRAME */ + canHandle->baseAddress->IF2_ARBITRATION2.reg = 0x8000; + canHandle->baseAddress->IF2_ARBITRATION1.reg = 0x0000; + } else if ((map & g_extRecvMap) != 0) { /* EXTENDED DATA FRAME */ + canHandle->baseAddress->IF2_ARBITRATION2.reg = 0xC000; + canHandle->baseAddress->IF2_ARBITRATION1.reg = 0x0000; + } else { + return BASE_STATUS_ERROR; + } + /* Step2: setting mask register 2 */ + canHandle->baseAddress->IF2_MASK2.reg = 0xC000; + /* Step3: setting mask register 1 */ + canHandle->baseAddress->IF2_MASK1.reg = 0x0000; + /* Step4: setting message control register. By default, there is no RX FIFO and no filtering is performed */ + canHandle->baseAddress->IF2_MESSAGE_CONTROL.reg = 0x1488; + /* Step5: send configuration to packet objects */ + canHandle->baseAddress->IF2_COMMAND_MASK.reg = 0x00F3; + /* Step6: write IF2 request command */ + canHandle->baseAddress->IF2_COMMAND_REQUEST.BIT.MessageNumber = objId; + canHandle->baseAddress->IF2_COMMAND_REQUEST.BIT.BUSY = BASE_CFG_ENABLE; + return BASE_STATUS_OK; +} + +/** + * @brief The object of the sent packet is cleared. + * @param canHandle CAN handle. + * @param objId Indicates the packet object ID. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +static BASE_StatusType WriteFinishClear(CAN_Handle *canHandle, unsigned int objId) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + unsigned int busy; + canHandle->baseAddress->IF2_COMMAND_MASK.reg = 0x7F; + canHandle->baseAddress->IF2_COMMAND_REQUEST.BIT.MessageNumber = objId; + do { + busy = canHandle->baseAddress->IF2_COMMAND_REQUEST.BIT.BUSY; + } while (busy != 0x00); + return BASE_STATUS_OK; +} + +/** + * @brief Write interrupt service function. + * @param canHandle CAN handle. + * @param irqIndex Packet object interrupt ID. + * @retval None. + */ +static void WriteIrqService(CAN_Handle *canHandle, unsigned int irqIndex) +{ + WriteFinishClear(canHandle, irqIndex); + g_msgObj[irqIndex - 1] = 0; + if (canHandle->userCallBack.WriteFinishCallBack != NULL) { + canHandle->userCallBack.WriteFinishCallBack(canHandle); + } +} + +/** + * @brief Read interrupt service function. + * @param canHandle CAN handle. + * @param irqIndex Packet object interrupt ID. + * @retval None. + */ +static void ReadIrqService(CAN_Handle *canHandle, unsigned int irqIndex) +{ + CAN_ReadCallback(canHandle, irqIndex); + if (canHandle->userCallBack.ReadFinishCallBack != NULL) { + canHandle->userCallBack.ReadFinishCallBack(canHandle); + } +} + +/** + * @brief CAN interrupt service processing function. + * @param handle CAN handle. + * @retval None. + */ +void HAL_CAN_IrqHandler(void *handle) +{ + CAN_ASSERT_PARAM(handle != NULL); + CAN_Handle *canHandle = (CAN_Handle *)handle; + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + unsigned int irqIndex; + unsigned int idLow, idHigh, id; + irqIndex = canHandle->baseAddress->CAN_INTERRUPT.reg; + /* Status interrupt ID: 0x8000 */ + if (irqIndex == 0x8000) { + /* Offline status of the CAN bus. */ + unsigned int statusBusoff = canHandle->baseAddress->CAN_STATUS.BIT.Boff; + if (statusBusoff == BASE_CFG_ENABLE) { /* true when the bus-off state is displayed. */ + canHandle->baseAddress->CAN_CONTROL.BIT.Init = 0x01; + __asm__ volatile ("nop"); /* Hold-off time */ + canHandle->baseAddress->CAN_CONTROL.BIT.Init = 0x00; + } + if (canHandle->userCallBack.TransmitErrorCallBack != NULL) { + canHandle->userCallBack.TransmitErrorCallBack(canHandle); + } + } else if (irqIndex >= 0x01 && irqIndex <= 0x20) { /* Packet object interrupt ID from 0x01 to 0x20 */ + idLow = canHandle->baseAddress->INTERRUPT_PENDING1.BIT.IntPnd16_1; + idHigh = canHandle->baseAddress->INTERRUPT_PENDING2.BIT.IntPnd32_17; + id = idLow; + id |= idHigh << 16; /* High 16 bits ID */ + if (id & g_allSendMap) { /* Write complete */ + WriteIrqService(canHandle, irqIndex); + } + if (id & g_allRecvMap) { + ReadIrqService(canHandle, irqIndex); + } + } + return; +} + +/** + * @brief Handle CAN interrupt request. + * @param canHandle CAN handle. + * @param typeID Id of callback function type, @ref CAN_CallBackFunType + * @param pCallback Pointer of the specified callbcak function, @ref CAN_CallbackType + * @retval BASE_StatusType: BASE_STATUS_ERROR register error, BASE_STATUS_OK register success. + */ +BASE_StatusType HAL_CAN_RegisterCallBack(CAN_Handle *canHandle, CAN_CallBackFunType typeID, CAN_CallbackType pCallback) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + switch (typeID) { + case CAN_WRITE_FINISH: /* CAN write finish call back. */ + canHandle->userCallBack.WriteFinishCallBack = pCallback; + break; + case CAN_READ_FINISH: /* CAN read finish call back. */ + canHandle->userCallBack.ReadFinishCallBack = pCallback; + break; + case CAN_TRNS_ERROR: /* CAN transmit finish call back. */ + canHandle->userCallBack.TransmitErrorCallBack = pCallback; + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/capm/common/inc/capm.h b/vendor/xinlingyu_92_3061M/Project/drivers/capm/common/inc/capm.h new file mode 100644 index 0000000000000000000000000000000000000000..eae8fb20bad03d5a509b137ce38d78dc353e8a71 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/capm/common/inc/capm.h @@ -0,0 +1,186 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file capm.h + * @author MCU Driver Team + * @brief CAPM module driver + * @details This file provides firmware CAPM Handle Structure and functions + * prototypes to manage the following functionalities of the CAPM. + * + CAPM handle structure definition. + * + Initialization and de-initialization functions. + * + CAPM Service Functions. + */ +#ifndef McuMagicTag_CAPM_H +#define McuMagicTag_CAPM_H + +#include "typedefs.h" +#include "dma.h" +#include "capm_ip.h" + +/** + * @defgroup CAPM CAPM + * @brief CAPM module. + * @{ + */ + +/** + * @defgroup CAPM_Common CAPM Common + * @brief CAPM common external module. + * @{ + */ + + +/** + * @defgroup CAPM_Common_Param CAPM Common Parameters + * @{ + */ +#define CAPM_NUM_0 0 +#define CAPM_NUM_1 1 +#define CAPM_NUM_2 2 + +/** + * @brief Capture edge mode + */ +typedef enum { + CAPM_FALLING, + CAPM_RISING, +} CAPM_CapEvent; + +/** + * @brief Reset mode + */ +typedef enum { + CAPM_NOTRESET, + CAPM_RESET, +} CAPM_RegRestMode; + +/** + * @brief Signal level + */ +typedef enum { + CAPM_LOW_LEVEL, + CAPM_UP_EDGE, + CAPM_DOWN_EDGE, + CAPM_HIGHT_LEVEL, +} CAPM_CaptureLevel; + +/** + * @brief Numbers of ECR + */ +typedef enum { + CAPM_ECR_NUM1, + CAPM_ECR_NUM2, + CAPM_ECR_NUM3, + CAPM_ECR_NUM4 +} CAPM_ECRNum; + +/** + * @brief Used ECR of next load + */ +typedef enum { + CAPM_NEXT_LOAD_ECR1, + CAPM_NEXT_LOAD_ECR2, + CAPM_NEXT_LOAD_ECR3, + CAPM_NEXT_LOAD_ECR4, +} CAPM_NextLoadECR; + +/** + * @brief CAPM callback function type + */ +typedef enum { + CAPM_EVT_FINISH = 0x00000000U, + CAPM_DMA_ERROR = 0x00000001U, + CAPM_DMA_FINISH = 0x00000002U +} CAPM_CallbackFuncType; + +/** + * @} + */ + +/** + * @defgroup CAPM_Handle_Definition CAPM Handle Definition + * @{ + */ + +/** + * @brief Configurations of each capture register + */ +typedef struct CapmCapRegConfig { + CAPM_CapEvent capEvent; + CAPM_RegRestMode regReset; +} CAPM_CapRegConfig; + +/** + * @brief The definition of the CAPM handle structure + */ +typedef struct _CAPM_Handle { + CAPM_RegStruct *baseAddress; /**< base address */ + unsigned int tscntDiv; /**< TSR count division, value range: 0~65535 */ + DMA_Handle *dmaHandle; /**< DMA handle */ + unsigned int dmaChannel; /**< Used DMA channel */ + + unsigned int preScale; /**< preScale factor. value range: 0~127 */ + unsigned int deburrNum; /**< deburr level. value range:0~8192. 0: Disable deburr */ + unsigned int useCapNum; /**< number of cap to be use. + value range: 1~CAPM_MAX_CAP_REG_NUM */ + unsigned int triggleDmaReg; /**< which ECR to triggle DMA interrupt. + value range:1 ~ useCapNum */ + unsigned int syncPhs; /**< TSRֵ sync phase value */ + bool enableSync; /**< enable sync */ + CAPM_SyncSrc syncSrc; /**< CAPM synchronized input source */ + unsigned int enableIntFlags; /**< enable interrupt */ + CAPM_CapMode capMode; /**< capture mode. continue or one-shot */ + CAPM_InputSrc inputSrc; /**< capture input source */ + CAPM_CapRegConfig capRegConfig[CAPM_MAX_CAP_REG_NUM]; /**< each capture register configuration */ + CAPM_UserCallBack userCallBack; /**< CAPM Interrupt callback functions.*/ + CAPM_ExtendHandle handleEx; /**< CAPM extend parameter */ +} CAPM_Handle; + +typedef void (* CAPM_CallbackType)(void *handle); +/** + * @} + */ + +/** + * @defgroup CAPM_API_Declaration CAPM HAL API + * @{ + */ +BASE_StatusType HAL_CAPM_Init(CAPM_Handle *handle); +BASE_StatusType HAL_CAPM_DeInit(CAPM_Handle *handle); + +unsigned int HAL_CAPM_GetECRValue(CAPM_Handle *handle, CAPM_ECRNum ecrNum); +unsigned char HAL_CAPM_GetCrtEdge(CAPM_Handle *handle); +unsigned char HAL_CAPM_GetNextLoadECRNum(CAPM_Handle *handle); +BASE_StatusType HAL_CAPM_GetECRValueDMA(CAPM_Handle *handle, unsigned int *saveData, unsigned int dataLength); + +void HAL_CAPM_SetSyncPhs(CAPM_Handle *handle, unsigned int phase); +unsigned int HAL_CAPM_GetSyncPhs(CAPM_Handle *handle); + +void HAL_CAPM_IrqHandler(void *handle); +void HAL_CAPM_RegisterCallback(CAPM_Handle *capmHandle, CAPM_CallbackFuncType typeID, CAPM_CallbackType pCallback); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/capm/inc/capm_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/capm/inc/capm_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..7fa19345f545f69ead15d6e970d41e4c0bfb56a3 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/capm/inc/capm_ip.h @@ -0,0 +1,1854 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file capm_ip.h + * @author MCU Driver Team + * @brief CAPM DCL level module driver. + * @details This file provides DCL functions to manage CAPM and Definition of + * specific parameters. + * + Definition of CAPM configuration parameters. + * + CAPM register mapping structure. + * + Direct configuration layer interface. + */ +#ifndef McuMagicTag_CAPM_IP_H +#define McuMagicTag_CAPM_IP_H + +#include "baseinc.h" +#include "baseaddr.h" + +#ifdef CAPM_PARAM_CHECK +#define CAPM_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define CAPM_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define CAPM_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define CAPM_ASSERT_PARAM(para) ((void)0U) +#define CAPM_PARAM_CHECK_NO_RET(para) ((void)0U) +#define CAPM_PARAM_CHECK_WITH_RET(param, ret) ((void)0U) +#endif + +/** + * @addtogroup CAPM + * @{ + */ + +/** + * @defgroup CAPM_IP CAPM_IP + * @brief CAPM_IP: capm_v1. + * @{ + */ + +/** + * @defgroup CAPM_Param_Def CAPM Parameters Definition + * @brief Definition of CAPM configuration parameters + * @{ + */ + +#define CAPM_IP_VER_MASK 0x0F000000U +#define CAPM_NEXT_LOAD_REG_MASK 0x00000003U +#define CAPM_INTERRUPT_MASK 0x0000001FU +#define CAPM_MAX_FILTER_VALUE 16 +#define CAPM_MAX_PRESCALE 127 +#define CAPM_MAX_CAP_REG_NUM 4 +#define CAPM_MAX_FILTER_LEVEL 0x00001FFFU +#define CAPM_BIT_SHIFT_TWO 2 +#define CAPM_MAX_INTERRUPT_NUMBER 8 + +#define CAPM0_BASEADDR CAPM0 +#define CAPM1_BASEADDR CAPM1 +#define CAPM2_BASEADDR CAPM2 + +/** + * @brief EAR count types. + * @details Count type: + * + CAPM_COUNT_NONE -- EAR do not count + * + CAPM_COUNT_RISING_EDGE -- EAR counting at rising edge + * + CAPM_COUNT_FALLING_EDGE -- EAR counting at falling edge + * + CAPM_COUNT_DOUBLE_EDGE -- EAR counting at rising edge or edge + */ +typedef enum { + CAPM_COUNT_NONE = 0x00000000U, + CAPM_COUNT_RISING_EDGE = 0x00000001U, + CAPM_COUNT_FALLING_EDGE = 0x00000002U, + CAPM_COUNT_DOUBLE_EDGE = 0x00000003U, +} CAPM_CountType; + +/** + * @brief Interrupt types. + * @details Type: + * + CAPM_REG1CAP -- ECR0 interrupt + * + CAPM_REG2CAP -- ECR1 interrupt + * + CAPM_REG3CAP -- ECR2 interrupt + * + CAPM_REG4CAP -- ECR3 interrupt + * + CAPM_TSROVF -- TSR register overflow interrupt + * + CAPM_ECROVF -- ECR register overflow interrupt + * + CAPM_EARCMPMATCH -- EAR compare match interrupt + * + CAPM_EAROVF -- EAR register overflow interrupt + * + CAPM_DMAREQOVF -- DMA require overflow interrupt + */ +typedef enum { + CAPM_REG1CAP = 0x00000001U, + CAPM_REG2CAP = 0x00000002U, + CAPM_REG3CAP = 0x00000004U, + CAPM_REG4CAP = 0x00000008U, + CAPM_TSROVF = 0x00000010U, + CAPM_ECROVF = 0x00000020U, + CAPM_EARCMPMATCH = 0x00000040U, + CAPM_EAROVF = 0x00000080U, + CAPM_DMAREQOVF = 0x00000100U, +} CAPM_Interrupt; + +/** + * @brief ECR number to be used. + */ +typedef enum { + CAPM_EVT0 = 0x00000000U, + CAPM_EVT1 = 0x00000001U, + CAPM_EVT2 = 0x00000002U, + CAPM_EVT3 = 0x00000003U, +} CampConfigCapRegNum; + +/** + * @brief CAPM capture mode. + * @details Capture mode: + * + CAPM_CONTINUECAP -- continue cap + * + CAPM_ONESHOTCAP -- one-shot cap + */ +typedef enum { + CAPM_CONTINUECAP = 0x00000000U, /**< continue cap */ + CAPM_ONESHOTCAP = 0x00000001U, /**< one-shot cap */ +} CAPM_CapMode; + +/** + * @brief CAPM capture edge. + * @details Capture edge: + * + CAPM_FALLING_EDGE -- capture falling edge + * + CAPM_RISING_EDGE -- capture rising edge + */ +typedef enum { + CAPM_FALLING_EDGE = 0x00000000U, + CAPM_RISING_EDGE = 0x00000001U, +} CAPM_POLAR; + +/** + * @brief CAPM input source selection. + * @details Capture edge: + * + CAPM_INPUT -- CAPMx_IN + * + CAPM_NONE -- No input source + */ +typedef enum { + CAPM_INPUT = 0x00000000U, + CAPM_NONE = 0x00000001U, +} CAPM_InputSrc; + +/** + * @brief CAPM sync input source selection. + * @details Capture edge: + * + CAPM_SYNC_SRC_NONE -- source none + * + CAPM_SYNC_SRC_APT0 -- source apt0 + * + CAPM_SYNC_SRC_APT1 -- source apt1 + * + CAPM_SYNC_SRC_APT2 -- source apt2 + * + CAPM_SYNC_SRC_APT3 -- source apt3 + * + CAPM_SYNC_SRC_APT4 -- source apt4 + * + CAPM_SYNC_SRC_APT5 -- source apt5 + * + CAPM_SYNC_SRC_APT6 -- source apt6 + * + CAPM_SYNC_SRC_APT7 -- source apt7 + * + CAPM_SYNC_SRC_APT8 -- source apt8 + */ +typedef enum { + CAPM_SYNC_SRC_NONE = 0x00000000U, + CAPM_SYNC_SRC_APT0 = 0x00000001U, + CAPM_SYNC_SRC_APT1 = 0x00000002U, + CAPM_SYNC_SRC_APT2 = 0x00000003U, + CAPM_SYNC_SRC_APT3 = 0x00000004U, + CAPM_SYNC_SRC_APT4 = 0x00000005U, + CAPM_SYNC_SRC_APT5 = 0x00000006U, + CAPM_SYNC_SRC_APT6 = 0x00000007U, + CAPM_SYNC_SRC_APT7 = 0x00000008U, + CAPM_SYNC_SRC_APT8 = 0x00000009U, +} CAPM_SyncSrc; + +/** + * @} + */ + +/** + * @defgroup CAPM_REG_Definition CAPM Register Structure. + * @brief CAPM Register Structure Definition. + * @{ + */ + +/** + * @brief CAPM revision information registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved1 : 24; + unsigned int revision : 4; /**< IP version number. */ + unsigned int reserved0 : 4; + } BIT; +} volatile REV_INFO_REG; + +/** + * @brief CAPM time-stamp divider registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int tscnt_div : 16; /**< Counter division. */ + unsigned int reserved : 16; + } BIT; +} volatile TSR_DIV_REG; + +/** + * @brief CAPM edge amount registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int ear : 16; /**< Edge count value. */ + unsigned int reserved : 16; + } BIT; +} volatile EAR_REG; + +/** + * @brief EAR compare value registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int earcmp : 16; /**< Edge count compare value. */ + unsigned int reserved : 16; + } BIT; +} volatile EAR_CMP_REG; + +/** + * @brief Event capture sequence registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int nxtldecr : 2; /**< Read next loaded ECR. */ + unsigned int crt_edge : 2; /**< Current input signal level. */ + unsigned int reserved : 28; + } BIT; +} volatile ECSEQR_REG; + +/** + * @brief Filter control registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int ft_en : 1; /**< Filter function enable. */ + unsigned int ft_lev : 13; /**< Filter level. */ + unsigned int reserved : 18; + } BIT; +} volatile FTCR_REG; + +/** + * @brief CCR0 registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int evt0pol : 1; /**< Event0 capture edge selection. */ + unsigned int evt0rst : 1; /**< Event0 reset TSR. */ + unsigned int evt1pol : 1; /**< Event0 capture edge selection. */ + unsigned int evt1rst : 1; /**< Event0 reset TSR. */ + unsigned int evt2pol : 1; /**< Event1 capture edge selection. */ + unsigned int evt2rst : 1; /**< Event1 reset TSR. */ + unsigned int evt3pol : 1; /**< Event2 capture edge selection. */ + unsigned int evt3rst : 1; /**< Event2 reset TSR. */ + unsigned int ecrlden : 1; /**< Capture enable. */ + unsigned int dmaevt_sel : 2; /**< DMA request event selection. */ + unsigned int psc : 8; /**< Pre-division coefficient of the input signal. */ + unsigned int cnt_edge_sel : 2; /**< Edge type selection of edge count.*/ + unsigned int reserved : 11; + } BIT; +} volatile CCR0_REG; + +/** + * @brief CCR1 registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 3; + unsigned int emu_stop_en : 1; /**< Emulation stop TSR enable. */ + unsigned int reserved1 : 28; + } BIT; +} volatile CCR1_REG; + +/** + * @brief CCR2 registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int cap_mode : 1; /**< Capture mode selection. */ + unsigned int seq_stop : 2; /**< End of capture sequence/Boundary of circulation. */ + unsigned int reserved : 29; + } BIT; +} volatile CCR2_REG; + +/** + * @brief CAPM interrupt enable registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int evt0_en : 1; /**< Event0 interrupt enable. */ + unsigned int evt1_en : 1; /**< Event1 interrupt enable. */ + unsigned int evt2_en : 1; /**< Event2 interrupt enable. */ + unsigned int evt3_en : 1; /**< Event3 interrupt enable. */ + unsigned int tsr_ovf_en : 1; /**< TSR overflow interrupt enable. */ + unsigned int ecr_ovf_en : 1; /**< Capture overflow interrupt enable. */ + unsigned int earcmp_match_en : 1; /**< Edge count compare match interrupt enable. */ + unsigned int ear_ovf_en : 1; /**< Edge count overflow interrupt enable. */ + unsigned int dmareq_ovf_en : 1; /**< DMA request overflow interrupt enable. */ + unsigned int reserved : 23; + } BIT; +} volatile INTENR_REG; + +/** + * @brief CAPM initial interrupt registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int evt0_raw : 1; /**< Event0 initial interrupt. */ + unsigned int evt1_raw : 1; /**< Event1 initial interrupt. */ + unsigned int evt2_raw : 1; /**< Event2 initial interrupt. */ + unsigned int evt3_raw : 1; /**< Event3 initial interrupt. */ + unsigned int tsr_ovf_raw : 1; /**< TSR overflow initial interrupt. */ + unsigned int ecr_ovf_raw : 1; /**< Capture overflow initial interrupt. */ + unsigned int earcmp_match_raw : 1; /**< Edge count compare match initial interrupt. */ + unsigned int ear_ovf_raw : 1; /**< Edge count overflow initial interrupt. */ + unsigned int dmareq_ovf_raw : 1; /**< DMA request overflow initial interrupt. */ + unsigned int reserved : 23; + } BIT; +} volatile INTRAWR_REG; + +/** + * @brief CAPM interrupt injection registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int evt0_inj : 1; /**< Event0 interrupt injection. */ + unsigned int evt1_inj : 1; /**< Event1 interrupt injection. */ + unsigned int evt2_inj : 1; /**< Event2 interrupt injection. */ + unsigned int evt3_inj : 1; /**< Event3 interrupt injection. */ + unsigned int tsr_ovf_inj : 1; /**< TSR overflow interrupt injection. */ + unsigned int ecr_ovf_inj : 1; /**< Capture overflow interrupt injection. */ + unsigned int earcmp_match_inj : 1; /**< Edge count compare match interrupt injection. */ + unsigned int ear_ovf_inj : 1; /**< Edge count overflow interrupt injection. */ + unsigned int dmareq_ovf_inj : 1; /**< DMA request overflow interrupt injection. */ + unsigned int reserved : 23; + } BIT; +} volatile INTINJR_REG; + +/** + * @brief CAPM interrupt status registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int evt0_int : 1; /**< Event0 interrupt status. */ + unsigned int evt1_int : 1; /**< Event1 interrupt status. */ + unsigned int evt2_int : 1; /**< Event2 interrupt status. */ + unsigned int evt3_int : 1; /**< Event3 interrupt status. */ + unsigned int tsr_ovf_int : 1; /**< TSR overflow interrupt status. */ + unsigned int ecr_ovf_int : 1; /**< Capture overflow interrupt status. */ + unsigned int earcmp_match_int : 1; /**< Edge count compare match interrupt status. */ + unsigned int ear_ovf_int : 1; /**< Edge count overflow interrupt status. */ + unsigned int dmareq_ovf_int : 1; /**< DMA request overflow interrupt status. */ + unsigned int reserved : 23; + } BIT; +} volatile INTFLGR_REG; + +/** + * @brief Event interrupt + */ +typedef enum { + CAPM_INTREG1CAP = 0x00000000U, + CAPM_INTREG2CAP = 0x00000001U, + CAPM_INTREG3CAP = 0x00000002U, + CAPM_INTREG4CAP = 0x00000003U, + CAPM_INTTSROVF = 0x00000004U, + CAPM_INTECROVF = 0x00000005U, + CAPM_INTEARCMPMATCH = 0x00000006U, + CAPM_INTEAROVF = 0x00000007U, + CAPM_INTDMAREQOVF = 0x00000008U, +} CAPM_IntEvent; + +/** + * @brief CAPM Interrupt callback functions. + * + */ +typedef void (*EvtCallbackType)(void *handle, CAPM_IntEvent intValue); +typedef struct { + EvtCallbackType EvtFinishCallback; /**< event finish callback function. */ + void (*DmaFinishCallback)(void *handle); /**< DMA finish callback function. */ + void (*DmaErrorCallback)(void *handle); /**< DMA error callback function. */ +} CAPM_UserCallBack; + +/** + * @brief CAPM extend handle. + */ +typedef struct _CAPM_ExtendeHandle { +} CAPM_ExtendHandle; + +/** + * @brief CAPM registers definition structure. + */ +typedef struct { + REV_INFO_REG REV_INFO; /**< CAPM revision information register, offset address: 0x0000. */ + unsigned int tsr; /**< CAPM time-stamp register, offset address: 0x0004. */ + TSR_DIV_REG TSR_DIV; /**< CAPM time-stamp divider register, offset address: 0x0008. */ + EAR_REG EAR; /**< CAPM edge amount register, offset address: 0x000C. */ + EAR_CMP_REG EAR_CMP; /**< EAR compare value register, offset address: 0x0010. */ + unsigned int SYNC_PHS; /**< Sync phase, offset address: 0x0014. */ + unsigned int ECR0; /**< Event0 capture register, offset address: 0x0018. */ + unsigned int ECR1; /**< Event1 capture register, offset address: 0x001C. */ + unsigned int ECR2; /**< Event2 capture register, offset address: 0x0020. */ + unsigned int ECR3; /**< Event3 capture register, offset address: 0x0024. */ + ECSEQR_REG ECSEQR; /**< Event capture sequence register, offset address: 0x0028. */ + FTCR_REG FTCR; /**< Filter control register, offset address: 0x002C. */ + CCR0_REG CCR0; /**< CCR0 register, offset address: 0x0030. */ + CCR1_REG CCR1; /**< CCR1 register, offset address: 0x0034. */ + CCR2_REG CCR2; /**< CCR2 register, offset address: 0x0038. */ + unsigned int reserve; + INTENR_REG INTENR; /**< CAPM interrupt enable register, offset address: 0x0040. */ + INTRAWR_REG INTRAWR; /**< CAPM initial interrupt register, offset address: 0x0044. */ + INTINJR_REG INTINJR; /**< CAPM interrupt injection register, offset address: 0x0048. */ + INTFLGR_REG INTFLGR; /**< CAPM interrupt status register, offset address: 0x004C. */ +} volatile CAPM_RegStruct; + +/** + * @brief Capture module general control registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int restart_capm0 : 1; /**< CAPM0 start a new single round capture. */ + unsigned int restart_capm1 : 1; /**< CAPM1 start a new single round capture. */ + unsigned int restart_capm2 : 1; /**< CAPM2 start a new single round capture. */ + unsigned int reserved1 : 5; + unsigned int tsr_stop_capm0 : 1; /**< CAPM0 TSR stop count enable. */ + unsigned int tsr_stop_capm1 : 1; /**< CAPM1 TSR stop count enable. */ + unsigned int tsr_stop_capm2 : 1; /**< CAPM2 TSR stop count enable. */ + unsigned int reserved2 : 5; + unsigned int stat_rst_capm0 : 1; /**< CAPM0 work state reset. */ + unsigned int stat_rst_capm1 : 1; /**< CAPM1 work state reset. */ + unsigned int stat_rst_capm2 : 1; /**< CAPM2 work state reset. */ + unsigned int reserve3 : 5; + unsigned int sync_sw_capm0 : 1; /**< Triggle CAPM0 sync, TSR reset, capture sequence reset. */ + unsigned int sync_sw_capm1 : 1; /**< Triggle CAPM1 sync, TSR reset, capture sequence reset. */ + unsigned int sync_sw_capm2 : 1; /**< Triggle CAPM2 sync, TSR reset, capture sequence reset. */ + unsigned int reserve4 : 5; + } BIT; +} volatile CAPM_GENE_CR_REG; + +/** + * @brief Sync selection register for CAPM0 structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int capm0_sync_sel : 4; /**< CAPM0 hardware sync source selection. */ + unsigned int capm0_synci_en : 1; /**< CAPM0 sync enable. */ + unsigned int reserved : 27; + }BIT; +} volatile SYNC_SELR0_REG; + +/** + * @brief Sync selection register for CAPM1 structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int capm1_sync_sel : 4; /**< CAPM1 hardware sync source selection. */ + unsigned int capm1_synci_en : 1; /**< CAPM1 sync enable. */ + unsigned int reserved : 27; + }BIT; +} volatile SYNC_SELR1_REG; + +/** + * @brief Sync selection register for CAPM2 structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int capm2_sync_sel : 4; /**< CAPM2 hardware sync source selection. */ + unsigned int capm2_synci_en : 1; /**< CAPM2 sync enable. */ + unsigned int reserved : 27; + }BIT; +} volatile SYNC_SELR2_REG; + +/** + * @brief Input source selection register for CAPM0 structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int capm0_in_sel : 1; /**< CAPM0 input source selection. */ + unsigned int reserved : 31; + }BIT; +} volatile INPUT_SELR0_REG; + +/** + * @brief Input source selection register for CAPM1 structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int capm1_in_sel : 1; /**< CAPM1 input source selection. */ + unsigned int reserved : 31; + }BIT; +} volatile INPUT_SELR1_REG; + +/** + * @brief Input source selection register for CAPM2 structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int capm2_in_sel : 1; /**< CAPM2 input source selection. */ + unsigned int reserved : 31; + }BIT; +} volatile INPUT_SELR2_REG; + +/** + * @brief Define the CAPM common register struct. + */ +typedef struct { + REV_INFO_REG REV_INFO; /**< Revision information, offset address: 0x0000. */ + CAPM_GENE_CR_REG CAPM_GENE_CR; /**< Capture module general control register, offset address: 0x0004. */ + SYNC_SELR0_REG SYNC_SELR0; /**< Sync selection register for CAPM0, offset address: 0x0008. */ + SYNC_SELR1_REG SYNC_SELR1; /**< Sync selection register for CAPM1, offset address: 0x000C. */ + SYNC_SELR2_REG SYNC_SELR2; /**< Sync selection register for CAPM2, offset address: 0x0010. */ + unsigned char reserved[20]; + INPUT_SELR0_REG INPUT_SELR0; /**< Input source selection register for CAPM0, offset address: 0x0028. */ + INPUT_SELR1_REG INPUT_SELR1; /**< Input source selection register for CAPM1, offset address: 0x002C. */ + INPUT_SELR2_REG INPUT_SELR2; /**< Input source selection register for CAPM2, offset address: 0x0030. */ +} volatile CAPM_COMM_RegStruct; + + +/** + * @brief Get CAPM IP's version. + * @param capmx: CAPM register base address. + * @retval CAPM IP's version. + */ +static inline unsigned int DCL_CAPM_GetIPVer(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return (capmx->REV_INFO.reg) & CAPM_IP_VER_MASK; +} + +/** + * @brief Get TSR value. + * @param capmx: CAPM register base address. + * @retval TSR value. + */ +static inline unsigned int DCL_CAPM_GetTSR(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->tsr; +} +/** + * @brief Set TSR divide value. + * @param capmx: CAPM register base address. + * @param divValue: Divide value. Range: 0~65535 + * @retval None. + */ +static inline void DCL_CAPM_SetTSRDiv(CAPM_RegStruct * const capmx, unsigned short divValue) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->TSR_DIV.BIT.tscnt_div = divValue; + return; +} + +/** + * @brief Get EAR value. + * @param capmx: CAPM register base address. + * @retval EAR value. + */ +static inline unsigned int DCL_CAPM_GetEar(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->EAR.BIT.ear; +} + +/** + * @brief Get EAR_CMP value. + * @param capmx: CAPM register base address. + * @retval EAR_CMP value. + */ +static inline unsigned int DCL_CAPM_GetEarCmp(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->EAR_CMP.BIT.earcmp; +} + +/** + * @brief Set sync phase value. + * @param capmx: CAPM register base address. + * @param syncPhs: Phase value. Range: 0~0xFFFF FFFF. + * @retval None. + */ +static inline void DCL_CAPM_SetSyncPhase(CAPM_RegStruct * const capmx, unsigned int syncPhs) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->SYNC_PHS = syncPhs; + return; +} + +/** + * @brief Get sync phase value. + * @param capmx: CAPM register base address. + * @retval Phase value. + */ +static inline unsigned int DCL_CAPM_GetSyncPhase(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->SYNC_PHS; +} + +/** + * @brief Get ECR0 value. + * @param capmx: CAPM register base address. + * @retval ECR0 value. + */ +static inline unsigned int DCL_CAPM_GetECR0(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->ECR0; +} + +/** + * @brief Get ECR1 value. + * @param capmx: CAPM register base address. + * @retval ECR1 value. + */ +static inline unsigned int DCL_CAPM_GetECR1(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->ECR1; +} + +/** + * @brief Get ECR2 value. + * @param capmx: CAPM register base address. + * @retval ECR2 value. + */ +static inline unsigned int DCL_CAPM_GetECR2(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->ECR2; +} + +/** + * @brief Get ECR3 value. + * @param capmx: CAPM register base address. + * @retval ECR3 value. + */ +static inline unsigned int DCL_CAPM_GetECR3(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->ECR3; +} + +/** + * @brief Get current signal level. + * @param capmx: CAPM register base address. + * @retval Signal level. + */ +static inline unsigned char DCL_CAPM_GetCRTEdge(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return (capmx->ECSEQR.BIT.crt_edge); +} + +/** + * @brief Get next ECR number. + * @param capmx: CAPM register base address. + * @retval Next ECR number. + */ +static inline unsigned char DCL_CAPM_GetNextECRNum(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return (capmx->ECSEQR.BIT.nxtldecr); +} + +/** + * @brief Set capture rising edge register. + * @param capmx: CAPM register base address. + * @param capReg: Capture rising edge register. + * Input argument value: 0(CapReg 1),1(CapReg 2),2(CapReg 3),3(CapReg 4).Register set value:1,4,16,64. + * @retval None. + */ +static inline void DCL_CAPM_RisingCap(CAPM_RegStruct * const capmx, unsigned int capReg) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + if (capReg > CAPM_MAX_CAP_REG_NUM) { + return; + } + capmx->CCR0.reg |= (unsigned int)((1 << capReg) * (1 << capReg)); + return; +} + +/** + * @brief Set capture falling edge register. + * @param capmx: CAPM register base address. + * @param capReg: Capture falling edge register. + * Input argument value:0(CapReg 1),1(CapReg 2),2(CapReg 3),3(CapReg 4).Register set value:1,4,16,64. + * @retval None. + */ +static inline void DCL_CAPM_FallingCap(CAPM_RegStruct * const capmx, unsigned int capReg) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + if (capReg > CAPM_MAX_CAP_REG_NUM) { + return; + } + capmx->CCR0.reg &= (~(unsigned int)((1 << capReg) * (1 << capReg))); + return; +} + +/** + * @brief Enable capture register reset TSR function. + * @param capmx: CAPM register base address. + * @param capReg: Reset TSR's capture register. + * Input argument value:0(CapReg 1),1(CapReg 2),2(CapReg 3),3(CapReg 4).Register set value:2,8,32,128. + * @retval None. + */ +static inline void DCL_CAPM_EnableCapReset(CAPM_RegStruct * const capmx, unsigned int capReg) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + if (capReg > CAPM_MAX_CAP_REG_NUM) { + return; + } + capmx->CCR0.reg |= (unsigned int)((CAPM_BIT_SHIFT_TWO * (1 << capReg) * (1 << capReg))); + return; +} + +/** + * @brief Disable capture register reset TSR function. + * @param capmx: CAPM register base address. + * @param capReg: Non-reset TSR's capture register. + * Input argument value:0(CapReg 1),1(CapReg 2),2(CapReg 3),3(CapReg 4).Register set value:2,8,32,128. + * @retval None. + */ +static inline void DCL_CAPM_DisableCapReset(CAPM_RegStruct * const capmx, unsigned int capReg) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + if (capReg > CAPM_MAX_CAP_REG_NUM) { + return; + } + capmx->CCR0.reg &= ~(unsigned int)(CAPM_BIT_SHIFT_TWO * (1 << capReg) * (1 << capReg)); + return; +} + +/** + * @brief Set ECR0 capture falling edge. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ECR0FallingCap(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR0.BIT.evt0pol = CAPM_FALLING_EDGE; + return; +} + +/** + * @brief Set ECR0 capture rising edge. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ECR0RisingCap(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR0.BIT.evt0pol = CAPM_RISING_EDGE; + return; +} + +/** + * @brief Enable ECR0 reset after each capture action. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableECR0CapReset(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR0.BIT.evt0rst = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable ECR0 reset after each capture action. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableECR0CapReset(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR0.BIT.evt0rst = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Set ECR1 capture falling edge. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ECR1FallingCap(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR0.BIT.evt1pol = CAPM_FALLING_EDGE; + return; +} + +/** + * @brief Set ECR1 capture rising edge. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ECR1RisingCap(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR0.BIT.evt1pol = CAPM_RISING_EDGE; + return; +} + +/** + * @brief Enable ECR1 reset after each capture action. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableECR1CapReset(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR0.BIT.evt1rst = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable ECR1 reset after each capture action. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableECR1CapReset(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR0.BIT.evt1rst = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Set ECR2 capture falling edge. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ECR2FallingCap(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR0.BIT.evt2pol = CAPM_FALLING_EDGE; + return; +} + +/** + * @brief Set ECR2 capture rising edge. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ECR2RisingCap(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR0.BIT.evt2pol = CAPM_RISING_EDGE; + return; +} + +/** + * @brief Enable ECR2 reset after each capture action. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableECR2CapReset(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR0.BIT.evt2rst = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable ECR2 reset after each capture action. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableECR2CapReset(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR0.BIT.evt2rst = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Set ECR2 capture Falling edge. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ECR3FallingCap(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR0.BIT.evt3pol = CAPM_FALLING_EDGE; + return; +} + +/** + * @brief Set ECR2 capture Rising edge. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ECR3RisingCap(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR0.BIT.evt3pol = CAPM_RISING_EDGE; + return; +} + +/** + * @brief Enable ECR3 after each capture action. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableECR3CapReset(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR0.BIT.evt3rst = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable ECR3 after each capture action. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableECR3CapReset(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR0.BIT.evt3rst = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Enable capture register load. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableCapRegLoad(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR0.BIT.ecrlden = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable capture register load. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableCapRegLoad(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR0.BIT.ecrlden = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Set the capture register's number which trggle DMA interrupt. + * @param capmx: CAPM register base address. + * @param capNum: Capture register number. + * @retval None. + */ +static inline void DCL_CAPM_SetDMATriggleReg(CAPM_RegStruct * const capmx, CampConfigCapRegNum capNum) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + CAPM_PARAM_CHECK_NO_RET(capNum >= 0); + CAPM_PARAM_CHECK_NO_RET(capNum < CAPM_MAX_CAP_REG_NUM); + capmx->CCR0.BIT.dmaevt_sel = capNum; + return; +} + +/** + * @brief Set prescale value. + * @param base: CAPM register base address. + * @param preScale PreScale value. Range: 0, 1, 2, 3 ... 127. + * @retval None. + */ +static inline void DCL_CAPM_SetPreScale(CAPM_RegStruct * const capmx, unsigned short preScale) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + CAPM_PARAM_CHECK_NO_RET(preScale <= CAPM_MAX_PRESCALE); + capmx->CCR0.BIT.psc = preScale; + return; +} + +/** + * @brief Set count edge type. + * @param capmx: CAPM register base address. + * @param countType: Count edge type. + * @retval None. + */ +static inline void DCL_CAPM_SetCountType(CAPM_RegStruct * const capmx, CAPM_CountType countType) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR0.BIT.cnt_edge_sel = countType; + return; +} + +/** + * @brief Set filer value. + * @param capmx: CAPM register base address. + * @param filterValue: Filter value. Range: 0 ~ 8191. + * @retval None. + */ +static inline void DCL_CAPM_SetFilterLevel(CAPM_RegStruct * const capmx, unsigned short filterValue) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->FTCR.BIT.ft_lev = filterValue; + return; +} + +/** + * @brief Get filer value. + * @param capmx: CAPM register base address. + * @retval Filer value. + */ +static inline unsigned int DCL_CAPM_GetFilterLevel(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->FTCR.BIT.ft_lev; +} + +/** + * @brief Enable input filter. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableFilter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->FTCR.BIT.ft_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable input filter. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableFilter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->FTCR.BIT.ft_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Restart CAPM0 one-shot capture. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_RestartOneShotCap0(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.restart_capm0 = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Restart CAPM1 one-shot capture. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_RestartOneShotCap1(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.restart_capm1 = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Restart CAPM2 one-shot capture. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_RestartOneShotCap2(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.restart_capm2 = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Suspend capm0 TSR count. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_SuspendTSRCount0(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.tsr_stop_capm0 = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Resume capm0 TSR counter. + * @param capmx: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ResumeTSRCount0(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.tsr_stop_capm0 = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Suspend capm1 TSR count. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_SuspendTSRCount1(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.tsr_stop_capm1 = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Resume capm1 TSR counter. + * @param capmx: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ResumeTSRCount1(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.tsr_stop_capm1 = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Suspend capm2 TSR count. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_SuspendTSRCount2(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.tsr_stop_capm2 = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Resume capm0 TSR counter. + * @param capmx: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ResumeTSRCount2(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.tsr_stop_capm2 = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Reset capm0 TSR value. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ResetTSRCount0(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.stat_rst_capm0 = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Reset capm1 TSR value. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ResetTSRCount1(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.stat_rst_capm1 = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Reset capm2 TSR value. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ResetTSRCount2(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.stat_rst_capm2 = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Set capture mode. + * @param capmx: CAPM register base address. + * @param capMode: Capture mode. + * @retval None. + */ +static inline void DCL_CAPM_SetCapMode(CAPM_RegStruct * const capmx, CAPM_CapMode capMode) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + CAPM_PARAM_CHECK_NO_RET(capMode == CAPM_CONTINUECAP || capMode == CAPM_ONESHOTCAP); + capmx->CCR2.BIT.cap_mode = capMode; + return; +} + +/** + * @brief Set capture stop on which register's capture event. + * @param capmx: CAPM register base address. + * @param capNum: Stop capture register number. + * @retval None. + */ +static inline void DCL_CAPM_SetStopSeq(CAPM_RegStruct * const capmx, CampConfigCapRegNum capNum) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + CAPM_PARAM_CHECK_NO_RET(capNum >= 0); + CAPM_PARAM_CHECK_NO_RET(capNum < CAPM_MAX_CAP_REG_NUM); + capmx->CCR2.BIT.seq_stop = capNum; + return; +} + +/** + * @brief Enable capm0 sync input. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableSyncIn0(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->SYNC_SELR0.BIT.capm0_synci_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Enable capm1 sync input. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableSyncIn1(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->SYNC_SELR1.BIT.capm1_synci_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Enable capm2 sync input. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableSyncIn2(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->SYNC_SELR2.BIT.capm2_synci_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable capm0 sync input. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableSyncIn0(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->SYNC_SELR0.BIT.capm0_synci_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Disable capm1 sync input. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableSyncIn1(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->SYNC_SELR1.BIT.capm1_synci_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Disable capm2 sync input. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableSyncIn2(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->SYNC_SELR2.BIT.capm2_synci_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Triggle a software sync event for capm0. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_TriggleSoftSync0(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.sync_sw_capm0 = BASE_CFG_SET; + return; +} + +/** + * @brief Triggle a software sync event for capm1. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_TriggleSoftSync1(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.sync_sw_capm1 = BASE_CFG_SET; + return; +} + +/** + * @brief Triggle a software sync event for capm2. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_TriggleSoftSync2(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.sync_sw_capm2 = BASE_CFG_SET; + return; +} + +/** + * @brief Clear all CAPM interrupt flags. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ClearAllInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTRAWR.reg = 0x1FF; + return; +} + +/** + * @brief Clear specific interrupt. + * @param capmx: CAPM register base address. + * @param eventNumber: Specific interrupt. + * @retval None. + */ +static inline void DCL_CAPM_ClearInter(CAPM_RegStruct * const capmx, CAPM_Interrupt eventNumber) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTRAWR.reg |= (unsigned int)eventNumber; + return; +} + +/** + * @brief Enable specific interrupt. + * @param capmx: CAPM register base address. + * @param eventNumber: Specific interrupt. + * @retval None. + */ +static inline void DCL_CAPM_EnableInter(CAPM_RegStruct * const capmx, CAPM_Interrupt eventNumber) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.reg |= (unsigned int)eventNumber; + return; +} + +/** + * @brief Disable specific interrupt. + * @param capmx: CAPM register base address. + * @param eventNumber: Specific interrupt. + * @retval None. + */ +static inline void DCL_CAPM_DisableInter(CAPM_RegStruct * const capmx, CAPM_Interrupt eventNumber) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.reg &= (~(unsigned int)eventNumber); + return; +} + +/** + * @brief Enable event1 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableEvt1Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.evt0_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable event1 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableEvt1Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.evt0_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Enable event2 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableEvt2Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.evt1_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable event2 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableEvt2Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.evt1_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Enable event3 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableEvt3Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.evt2_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable event3 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableEvt3Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.evt2_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Enable event4 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableEvt4Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.evt3_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable event4 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableEvt4Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.evt3_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Enable TSR overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableTsrovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.tsr_ovf_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable TSR overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableTsrovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.tsr_ovf_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Enable ECR overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableEcrovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.ecr_ovf_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable ECR overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableEcrovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.ecr_ovf_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Enable EAR compare match interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableEARCMPMatchInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.earcmp_match_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable EAR compare match interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableEARCMPMatchInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.earcmp_match_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Enable EAR overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableEarovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.ear_ovf_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable EAR overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableEarovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.ear_ovf_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Enable DMA overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableDmaovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.dmareq_ovf_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable DMA overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableDmaovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.dmareq_ovf_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Get all interrupt flags. + * @param capmx: CAPM register base address. + * @retval Interrupt flags. + */ +static inline unsigned int DCL_CAPM_GetInterFlag(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->INTFLGR.reg; +} + +/** + * @brief Inject interrupts by software. + * @param capmx: CAPM register base address. + * @param eventNumber: Inject interrupt. + * @retval None. + */ +static inline void DCL_CAPM_InjectInter(CAPM_RegStruct * const capmx, CAPM_Interrupt eventNumber) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTFLGR.reg |= (unsigned int)eventNumber; + return; +} + +/** + * @brief Inject event1 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_InjectEvt1Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTINJR.BIT.evt0_inj |= 0x01; + return; +} + +/** + * @brief Inject event2 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_InjectEvt2Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTINJR.BIT.evt1_inj |= 0x01; + return; +} + +/** + * @brief Inject event3 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_InjectEvt3Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTINJR.BIT.evt2_inj |= 0x01; + return; +} + +/** + * @brief Inject event4 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_InjectEvt4Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTINJR.BIT.evt3_inj |= 0x01; + return; +} + +/** + * @brief Inject TSR overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_IngectTsrovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTINJR.BIT.tsr_ovf_inj |= 0x01; + return; +} + +/** + * @brief Inject ECR overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_InjectEcrovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTINJR.BIT.ecr_ovf_inj |= 0x01; + return; +} + +/** + * @brief Inject EAR overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_InjectEarOvfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTINJR.BIT.ear_ovf_inj |= 0x01; + return; +} + +/** + * @brief Enable emulation stop TSR count. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableEmuStopTSR(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.emu_stop_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable emulation stop TSR count. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableEmuStopTSR(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.emu_stop_en = BASE_CFG_DISABLE; +} + +/** + * @brief Disable TSR count stop control + * @param capmComm: CAPM_COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableTSRStop(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.tsr_stop_capm0 = BASE_CFG_DISABLE; + capmComm->CAPM_GENE_CR.BIT.tsr_stop_capm1 = BASE_CFG_DISABLE; + capmComm->CAPM_GENE_CR.BIT.tsr_stop_capm2 = BASE_CFG_DISABLE; +} + +/** + * @brief Set CAPM0 input source + * @param capmComm: CAPM_COMM register base address. + * @param src: source selection + * @retval None. + */ +static inline void DCL_CAPM_SetInputSEL0(CAPM_COMM_RegStruct * const capmComm, CAPM_InputSrc src) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->INPUT_SELR0.BIT.capm0_in_sel = src; +} + +/** + * @brief Set CAPM1 input source + * @param capmComm: CAPM_COMM register base address. + * @param src: source selection + * @retval None. + */ +static inline void DCL_CAPM_SetInputSEL1(CAPM_COMM_RegStruct * const capmComm, CAPM_InputSrc src) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->INPUT_SELR1.BIT.capm1_in_sel = src; +} + +/** + * @brief Set CAPM2 input source + * @param capmComm: CAPM_COMM register base address. + * @param src: source selection + * @retval None. + */ +static inline void DCL_CAPM_SetInputSEL2(CAPM_COMM_RegStruct * const capmComm, CAPM_InputSrc src) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->INPUT_SELR2.BIT.capm2_in_sel = src; +} + +/** + * @brief Set CAPM0 sync input source + * @param capmComm: CAPM_COMM register base address. + * @param src: apt source selection + * @retval None. + */ +static inline void DCL_CAPM_SetSyncInput0(CAPM_COMM_RegStruct * const capmComm, CAPM_SyncSrc src) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + CAPM_PARAM_CHECK_NO_RET(src >= CAPM_SYNC_SRC_NONE); + CAPM_PARAM_CHECK_NO_RET(src <= CAPM_SYNC_SRC_APT8); + capmComm->SYNC_SELR0.BIT.capm0_sync_sel = src; +} + +/** + * @brief Set CAPM1 sync input source + * @param capmComm: CAPM_COMM register base address. + * @param src: apt source selection + * @retval None. + */ +static inline void DCL_CAPM_SetSyncInput1(CAPM_COMM_RegStruct * const capmComm, CAPM_SyncSrc src) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + CAPM_PARAM_CHECK_NO_RET(src >= CAPM_SYNC_SRC_NONE); + CAPM_PARAM_CHECK_NO_RET(src <= CAPM_SYNC_SRC_APT8); + capmComm->SYNC_SELR1.BIT.capm1_sync_sel = src; +} + +/** + * @brief Set CAPM2 sync input source + * @param capmComm: CAPM_COMM register base address. + * @param src: apt source selection + * @retval None. + */ +static inline void DCL_CAPM_SetSyncInput2(CAPM_COMM_RegStruct * const capmComm, CAPM_SyncSrc src) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + CAPM_PARAM_CHECK_NO_RET(src >= CAPM_SYNC_SRC_NONE); + CAPM_PARAM_CHECK_NO_RET(src <= CAPM_SYNC_SRC_APT8); + capmComm->SYNC_SELR2.BIT.capm2_sync_sel = src; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/capm/src/capm.c b/vendor/xinlingyu_92_3061M/Project/drivers/capm/src/capm.c new file mode 100644 index 0000000000000000000000000000000000000000..0372e3915882e3234a61dbdc0b292a29af7e1b63 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/capm/src/capm.c @@ -0,0 +1,439 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file capm.c + * @author MCU Driver Team. + * @brief CAPM HAL level module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the CAPM. + * + Initialization and de-initialization functions. + * + Get CAPM ECR value and next load ECR number. + * + Get CAPM CRT edge. + * + Enable/Disable CAPM sync function. + * + Get/Set CAPM sync phase(TSR) value. + * + Config CAPM interrupt function. + */ +#include "capm.h" +#include "assert.h" +#include "interrupt.h" + +/** + * @brief Config whether the ECR capture event need reset TSR. + * @param handle: CAPM handle. + * @param number: ECR number. + * @retval None. + */ +static inline void CAPM_SetCapReset(CAPM_Handle *handle, unsigned int number) +{ + CAPM_ASSERT_PARAM(handle != NULL); + CAPM_ASSERT_PARAM(IsCAPMInstance(handle->baseAddress)); + CAPM_PARAM_CHECK_NO_RET(number <= CAPM_MAX_CAP_REG_NUM); + if (handle->capRegConfig[number].regReset == CAPM_RESET) { + /* Enable ECR capture event need reset TSR */ + DCL_CAPM_EnableCapReset(handle->baseAddress, number); + } else { + /* Disable ECR capture event need reset TSR */ + DCL_CAPM_DisableCapReset(handle->baseAddress, number); + } + return; +} + +/** + * @brief Config triggle ECR capture event source. + * @param handle: CAPM handle. + * @retval BASE status type: BASE_STATUS_OK, BASE_STATUS_ERROR. + */ +static BASE_StatusType CAPM_SetRegCaptureEvent(CAPM_Handle *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + CAPM_PARAM_CHECK_WITH_RET(handle->useCapNum <= CAPM_MAX_CAP_REG_NUM, BASE_STATUS_ERROR); + unsigned int i; + for (i = 0; i < handle->useCapNum; i++) { + if (handle->capRegConfig[i].capEvent == CAPM_RISING) { /* CAPM rising capture. */ + DCL_CAPM_RisingCap(handle->baseAddress, i); + CAPM_SetCapReset(handle, i); + } else if (handle->capRegConfig[i].capEvent == CAPM_FALLING) { /* CAPM falling capture. */ + DCL_CAPM_FallingCap(handle->baseAddress, i); + CAPM_SetCapReset(handle, i); + } else { + return BASE_STATUS_ERROR; + } + } + return BASE_STATUS_OK; +} + +/** + * @brief Set deburr number. + * @param handle: CAPM handle. + * @retval BASE status type: BASE_STATUS_OK, BASE_STATUS_ERROR. + */ +static BASE_StatusType CAPM_SetDeburrNum(CAPM_Handle *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + if ((handle->deburrNum > 0) && (handle->deburrNum <= CAPM_MAX_FILTER_LEVEL)) { + DCL_CAPM_EnableFilter(handle->baseAddress); + DCL_CAPM_SetFilterLevel(handle->baseAddress, handle->deburrNum - 1); + } else { + /* deburrNum = 0: Disable filter. */ + DCL_CAPM_DisableFilter(handle->baseAddress); + } + return BASE_STATUS_OK; +} + +/** + * @brief IRQ Handler + * @param handle: CAPM handle. + * @retval None + */ +void HAL_CAPM_IrqHandler(void *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + CAPM_Handle *useHandle = (CAPM_Handle *)handle; + CAPM_ASSERT_PARAM(IsCAPMInstance(useHandle->baseAddress)); + if (useHandle->userCallBack.EvtFinishCallback != NULL) { + /* Get interrupt flag. */ + unsigned int intMask = DCL_CAPM_GetInterFlag(useHandle->baseAddress); + unsigned int intBit; + for (unsigned int i = 0; i <= CAPM_INTDMAREQOVF; i++) { + if (((intMask >> i) & 0x1) == 0x1) { + intBit = (intMask & (0x1 << i)); + /* Clear interrupt. */ + DCL_CAPM_ClearInter(useHandle->baseAddress, intBit); + useHandle->userCallBack.EvtFinishCallback(useHandle, i); + } + } + } + return; +} + +/** + * @brief Register IRQ callback functions + * @param capmHandle: CAPM handle. + * @param typeID: callback function type ID. + * @param pCallback: pointer of callback function. + * @retval None + */ +void HAL_CAPM_RegisterCallback(CAPM_Handle *capmHandle, CAPM_CallbackFuncType typeID, CAPM_CallbackType pCallback) +{ + CAPM_ASSERT_PARAM(capmHandle != NULL); + CAPM_ASSERT_PARAM(IsCAPMInstance(capmHandle->baseAddress)); + CAPM_ASSERT_PARAM(pCallback != NULL); + + switch (typeID) { + case CAPM_EVT_FINISH: + capmHandle->userCallBack.EvtFinishCallback = (EvtCallbackType)pCallback; /**< Event finish callback. */ + break; + case CAPM_DMA_ERROR: + capmHandle->userCallBack.DmaErrorCallback = pCallback; /**< DMA error callback function. */ + break; + case CAPM_DMA_FINISH: + capmHandle->userCallBack.DmaFinishCallback = pCallback; /**< DMA finish callback function. */ + default: + return; + } +} + +/** + * @brief DMA error interrupt service routine. + * @param handle: CAPM handle. + * @retval None. + */ +static void CAPM_DmaErrorIRQService(void *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + + CAPM_Handle *useHandle = (CAPM_Handle *)handle; + if (useHandle->userCallBack.DmaErrorCallback != NULL) { /* if callback not equal to null */ + useHandle->userCallBack.DmaErrorCallback(useHandle); + } + return; +} + +/** + * @brief DMA finish interrupt service routine. + * @param handle: CAPM handle. + * @retval None. + */ +static void CAPM_DmaFinishIRQService(void *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + + CAPM_Handle *useHandle = (CAPM_Handle *)handle; + if (useHandle->userCallBack.DmaFinishCallback != NULL) { /* if callback not equal to null */ + useHandle->userCallBack.DmaFinishCallback(useHandle); + } + return; +} + +/** + * @brief Get camp number. + * @param handle: CAPM handle. + * @retval camp number. + */ +static unsigned char CAPM_GetCapmNumber(CAPM_Handle *capmHandle) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmHandle->baseAddress)); + if (capmHandle->baseAddress == CAPM0_BASE) { + return CAPM_NUM_0; /* capm0 */ + } else if (capmHandle->baseAddress == CAPM1_BASE) { + return CAPM_NUM_1; /* capm1 */ + } else if (capmHandle->baseAddress == CAPM2_BASE) { + return CAPM_NUM_2; /* capm2 */ + } else { + return CAPM_NUM_0; + } +} + +/** + * @brief Setting camp sync. + * @param capmHandle: CAPM handle. + * @param capmNum: capm number. + * @retval camp number. + */ +static void CAPM_SyncSetByNumber(CAPM_Handle *capmHandle, unsigned char capmNum) +{ + switch (capmNum) { + case CAPM_NUM_0: + DCL_CAPM_EnableSyncIn0(CAPM_COMM); /* enable capm0 sync */ + DCL_CAPM_SetSyncInput0(CAPM_COMM, capmHandle->syncSrc); + break; + case CAPM_NUM_1: + DCL_CAPM_EnableSyncIn1(CAPM_COMM); /* enable capm1 sync */ + DCL_CAPM_SetSyncInput1(CAPM_COMM, capmHandle->syncSrc); + break; + case CAPM_NUM_2: + DCL_CAPM_EnableSyncIn2(CAPM_COMM); /* enable capm2 sync */ + DCL_CAPM_SetSyncInput2(CAPM_COMM, capmHandle->syncSrc); + break; + default: + break; + } +} + +/** + * @brief Disable sync by capm number. + * @param capmNum: CAPM number. + * @retval None. + */ +static void CAPM_SyncDisableByNumber(unsigned char capmNum) +{ + switch (capmNum) { + case CAPM_NUM_0: + DCL_CAPM_DisableSyncIn0(CAPM_COMM); /* disable capm0 sync */ + break; + case CAPM_NUM_1: + DCL_CAPM_DisableSyncIn1(CAPM_COMM); /* disable camp1 sync */ + break; + case CAPM_NUM_2: + DCL_CAPM_DisableSyncIn2(CAPM_COMM); /* disable capm2 sync */ + break; + default: + break; + } +} + +/** + * @brief Capm sync initialize. + * @param capmHandle: CAPM handle. + * @retval None. + */ +static void CAPM_SyncInit(CAPM_Handle *capmHandle) +{ + unsigned char capmNum; + CAPM_ASSERT_PARAM(capmHandle != NULL); + capmNum = CAPM_GetCapmNumber(capmHandle); + if (capmHandle->enableSync == true) { /* if enable sync */ + CAPM_SyncSetByNumber(capmHandle, capmNum); + } else { /* if do not enable sync */ + CAPM_SyncDisableByNumber(capmNum); + } +} + +/** + * @brief Capm select input. + * @param capmHandle: CAPM handle. + * @retval None. + */ +static BASE_StatusType CAPM_InputSel(CAPM_Handle *capmHandle) +{ + CAPM_ASSERT_PARAM(capmHandle != NULL); + if (capmHandle->baseAddress == CAPM0_BASE) { + DCL_CAPM_SetInputSEL0(CAPM_COMM, capmHandle->inputSrc); /* set capm0 input selection */ + } else if (capmHandle->baseAddress == CAPM1_BASE) { + DCL_CAPM_SetInputSEL1(CAPM_COMM, capmHandle->inputSrc); /* set capm1 input selection */ + } else if (capmHandle->baseAddress == CAPM2_BASE) { + DCL_CAPM_SetInputSEL2(CAPM_COMM, capmHandle->inputSrc); /* set capm2 input selection */ + } else { /* error value */ + return BASE_STATUS_ERROR; + } + + return BASE_STATUS_OK; +} + +/** + * @brief CAPM initialize function. + * @param handle: CAPM handle. + * @retval BASE status type: BASE_STATUS_OK, BASE_STATUS_ERROR. + */ +BASE_StatusType HAL_CAPM_Init(CAPM_Handle *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + CAPM_ASSERT_PARAM(IsCAPMInstance(handle->baseAddress)); + CAPM_PARAM_CHECK_WITH_RET(handle->useCapNum <= CAPM_MAX_CAP_REG_NUM, BASE_STATUS_ERROR); + CAPM_PARAM_CHECK_WITH_RET(handle->preScale <= CAPM_MAX_PRESCALE, BASE_STATUS_ERROR); + /* Init CAPM TSR division. */ + DCL_CAPM_SetTSRDiv(handle->baseAddress, handle->tscntDiv); + /* Init CAPM capture mode. */ + DCL_CAPM_SetCapMode(handle->baseAddress, handle->capMode); + DCL_CAPM_SetStopSeq(handle->baseAddress, handle->useCapNum - 1); + CAPM_SetDeburrNum(handle); + /* Init CAPM prescale. */ + DCL_CAPM_SetPreScale(handle->baseAddress, handle->preScale); + DCL_CAPM_SetDMATriggleReg(handle->baseAddress, handle->useCapNum - 1); + CAPM_SetRegCaptureEvent(handle); + CAPM_SyncInit(handle); + if (CAPM_InputSel(handle) == BASE_STATUS_ERROR) { + return BASE_STATUS_ERROR; + } + DCL_CAPM_DisableTSRStop((CAPM_COMM_RegStruct *) CAPM_COMM); + /* Enable CAPM interrupt. */ + DCL_CAPM_EnableInter(handle->baseAddress, handle->enableIntFlags); + DCL_CAPM_EnableCapRegLoad(handle->baseAddress); + + return BASE_STATUS_OK; +} + +/** + * @brief CAPM deinitialize function. + * @param handle: CAPM handle. + * @retval BASE status type: BASE_STATUS_OK, BASE_STATUS_ERROR. + */ +BASE_StatusType HAL_CAPM_DeInit(CAPM_Handle *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + CAPM_ASSERT_PARAM(IsCAPMInstance(handle->baseAddress)); + /* Clear interrupt callback function. */ + handle->userCallBack.EvtFinishCallback = NULL; + handle->userCallBack.DmaErrorCallback = NULL; + handle->userCallBack.DmaFinishCallback = NULL; + + /* Clear enable operations. */ + DCL_CAPM_DisableInter(handle->baseAddress, handle->enableIntFlags); + DCL_CAPM_DisableCapRegLoad(handle->baseAddress); + return BASE_STATUS_OK; +} + +/** + * @brief Get ECR value. + * @param handle: CAPM handle. + * @param ecrNum: ECR number. + * @retval ECR value. + */ +unsigned int HAL_CAPM_GetECRValue(CAPM_Handle *handle, CAPM_ECRNum ecrNum) +{ + CAPM_ASSERT_PARAM(handle != NULL); + CAPM_PARAM_CHECK_WITH_RET(ecrNum > 0, BASE_STATUS_ERROR); + CAPM_PARAM_CHECK_WITH_RET(ecrNum < CAPM_MAX_CAP_REG_NUM, BASE_STATUS_ERROR); + switch (ecrNum) { + case CAPM_ECR_NUM1: + return DCL_CAPM_GetECR0(handle->baseAddress); /* Get ECR0 value. */ + case CAPM_ECR_NUM2: + return DCL_CAPM_GetECR1(handle->baseAddress); /* Get ECR1 value. */ + case CAPM_ECR_NUM3: + return DCL_CAPM_GetECR2(handle->baseAddress); /* Get ECR2 value. */ + case CAPM_ECR_NUM4: + return DCL_CAPM_GetECR3(handle->baseAddress); /* Get ECR3 value. */ + default: + return BASE_STATUS_OK; + } +} + +/** + * @brief Get current signal level. + * @param handle: CAPM handle. + * @retval Current signal level: CAPM_LOW_LEVEL, CAPM_UP_EDGE, CAPM_DOWN_EDGE, CAPM_HIGH_LEVEL. + */ +unsigned char HAL_CAPM_GetCrtEdge(CAPM_Handle *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + return DCL_CAPM_GetCRTEdge(handle->baseAddress); +} + +/** + * @brief Get the number of next ECR to be loaded. + * @param handle: CAPM handle. + * @retval Next ECR number:NEXT_LOAD_ECR0, NEXT_LOAD_ECR1, NEXT_LOAD_ECR2, NEXT_LOAD_ECR3. + */ +unsigned char HAL_CAPM_GetNextLoadECRNum(CAPM_Handle *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + return DCL_CAPM_GetNextECRNum(handle->baseAddress); +} + +/** + * @brief Set sync phase value. + * @param handle: CAPM handle. + * @param phase: Default sync phase value. + * @retval None. + */ +void HAL_CAPM_SetSyncPhs(CAPM_Handle *handle, unsigned int phase) +{ + CAPM_ASSERT_PARAM(handle != NULL); + DCL_CAPM_SetSyncPhase(handle->baseAddress, phase); + return; +} + +/** + * @brief Get sync phase value. + * @param handle: CAPM handle. + * @retval Sync phase value. + */ +unsigned int HAL_CAPM_GetSyncPhs(CAPM_Handle *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + return DCL_CAPM_GetSyncPhase(handle->baseAddress); +} + +/** + * @brief Get ECR register value by DMA. + * @param handle: CAPM handle. + * @param distAddr: Distance address. + * @param dataLength: CAPM handle. + * @retval BASE status type: BASE_STATUS_OK, BASE_STATUS_ERROR. + */ +BASE_StatusType HAL_CAPM_GetECRValueDMA(CAPM_Handle *handle, unsigned int *distAddr, + unsigned int dataLength) +{ + CAPM_ASSERT_PARAM(handle != NULL); + CAPM_ASSERT_PARAM(handle->dmaHandle != NULL); + CAPM_ASSERT_PARAM(distAddr != NULL); + CAPM_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + unsigned int channel; + channel = handle->dmaChannel; + if (channel >= CHANNEL_MAX_NUM) { + return BASE_STATUS_ERROR; + } + /* Config DMA callback. */ + handle->dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelFinishCallBack = CAPM_DmaFinishIRQService; + handle->dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelErrorCallBack = CAPM_DmaErrorIRQService; + /* Get ECR value by DMA. */ + if (HAL_DMA_StartIT(handle->dmaHandle, (unsigned int)(uintptr_t)(void *)&(handle->baseAddress->ECR0), + (unsigned int)(uintptr_t)(void *)distAddr, dataLength, channel) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/cfd/common/inc/cfd.h b/vendor/xinlingyu_92_3061M/Project/drivers/cfd/common/inc/cfd.h new file mode 100644 index 0000000000000000000000000000000000000000..c697a72fd4f227c3b61a618b8bdca8627d2cbfd4 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/cfd/common/inc/cfd.h @@ -0,0 +1,111 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cfd.h + * @author MCU Driver Team + * @brief CFD module driver. + * @details This file provides firmware CFD Handle structure and Functions + * prototypes to manage the following functionalities of the CFD module. + * + Initialization and de-initialization functions + * + config the register of CFD module + */ + +#ifndef McuMagicTag_CFD_H +#define McuMagicTag_CFD_H + +/* Includes ------------------------------------------------------------------ */ +#include "cfd_ip.h" + +/* Macro definitions ---------------------------------------------------------*/ +/** + * @defgroup CFD CFD + * @brief CFD module. + * @{ + */ + +/** + * @defgroup CFD_Common CFD Common + * @brief CFD common external module. + * @{ + */ + +/** + * @defgroup CFD_Handle_Definition CFD Handle Definition + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ + +/** + * @brief CFD module configurable item. + */ +typedef enum { + CFD_CFG_UPPER_BOUND = 0x00000001U, + CFD_CFG_INT_TYPE = 0x00000002U, + CFD_CFG_MAX +} CFD_CFG_TYPE; + +/** + * @brief CFD handle. + */ +typedef struct _CFD_Handle { + CFD_RegStruct *baseAddress; /**< CFD registers base address. */ + unsigned char upperBound; /**< Upper boundary. */ + unsigned int interruptType; /**< Enabled interrupt type. */ + CFD_UserCallBack userCallBack; /**< CFD Interrupt callback functions.*/ + CFD_ExtendHandle handleEx; /**< CFD extend parameter */ +} CFD_Handle; + +/** + * @brief Typedef callback function of CFD + */ +typedef void (*CFD_CallBackFuncType)(void *handle); + +/** + * @} + */ + +/** + * @defgroup CFD_API_Declaration CFD HAL API + * @{ + */ + +/* Hardware abstraction layer functions -------------------------------------------------------- */ +BASE_StatusType HAL_CFD_Init(CFD_Handle *handle); +BASE_StatusType HAL_CFD_DeInit(CFD_Handle *handle); +BASE_StatusType CFD_RspInit(CFD_Handle *handle); +BASE_StatusType CFD_RspDeInit(CFD_Handle *handle); +BASE_StatusType HAL_CFD_Config(CFD_Handle *handle, CFD_CFG_TYPE cfgType); +void HAL_CFD_GetConfig(CFD_Handle *handle); +void HAL_CFD_Start(CFD_Handle *handle); +void HAL_CFD_Stop(CFD_Handle *handle); +BASE_StatusType HAL_CFD_RegisterCallback(CFD_Handle *handle, CFD_Interrupt_Type type, CFD_CallBackFuncType callback); +void HAL_CFD_IrqHandler(void *handle); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_UART_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/cfd/inc/cfd_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/cfd/inc/cfd_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..8af191578e19aeceb8149a26a24eff4eb7d688a8 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/cfd/inc/cfd_ip.h @@ -0,0 +1,284 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cfd_ip.h + * @author MCU Driver Team + * @brief CFD module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the CFD. + * + Register Struct of CFD + * + CFD Register Map struct + * + Direct Configuration Layer functions of CFD + */ + +#ifndef McuMagicTag_CFD_IP_H +#define McuMagicTag_CFD_IP_H + +/* Includes ------------------------------------------------------------------ */ +#include "baseinc.h" +#include "cmm_ip.h" +#include "crg_ip.h" +/* Macro definitions ---------------------------------------------------------*/ +#ifdef CFD_PARAM_CHECK + #define CFD_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM + #define CFD_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET + #define CFD_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else + #define CFD_ASSERT_PARAM(para) ((void)0U) + #define CFD_PARAM_CHECK_NO_RET(para) ((void)0U) + #define CFD_PARAM_CHECK_WITH_RET(param, ret) ((void)0U) +#endif +/** + * @addtogroup CFD + * @{ + */ + +/** + * @defgroup CFD_IP + * @{ + */ + +/** + * @defgroup CFD_Param_Def CFD Parameters Definition + * @brief Description of CFD configuration parameters. + * @{ + */ + +/* Typedef definitions ------------------------------------------------------- */ +/** + * @brief The CFD module interrupt type mask. + */ +typedef enum { + CFD_INT_CHECK_END_MASK = 0x00000002U, + CFD_INT_PLL_REF_CLOCK_STOP_MASK = 0x00000008U, + CFD_INT_MAX_MASK +} CFD_Interrupt_Type; + +/** + * @} + */ + +/** + * @brief CFD interrupt callback functions. + * + */ +typedef struct { + void (*PllClockStopCallback)(void *handle); /**< Pll clock stop callback function. */ + void (*CheckEndCallback)(void *handle); /**< End of each check callback function. */ +} CFD_UserCallBack; + +/** + * @brief CFD extend handle. + */ +typedef struct _CFD_ExtendeHandle { +} CFD_ExtendHandle; + + +/** + * @brief CFD register mapping structure. + */ +typedef CMM_RegStruct CFD_RegStruct; + +/** + * @} + */ + +/** + * @brief Enable CFD module. + * @param cfdx CFD register base address. + * @retval None. + */ +static inline void DCL_CFD_Enable(CFD_RegStruct *cfdx) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + cfdx->CMCTRL.BIT.cfen = BASE_CFG_ENABLE; + cfdx->CMCTRL.BIT.cmen = BASE_CFG_ENABLE; +} + +/** + * @brief Disable CFD module. + * @param cfdx CFD register base address. + * @retval None. + */ +static inline void DCL_CFD_Disable(CFD_RegStruct *cfdx) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + cfdx->CMCTRL.BIT.cfen = BASE_CFG_DISABLE; + cfdx->CMCTRL.BIT.cmen = BASE_CFG_DISABLE; +} + +/** + * @brief Sets the target and reference clock source of the CFD. + * @param cfdx CFD register base address. + * @retval None. + */ +static inline void DCL_CFD_SetCfdClock(CFD_RegStruct *cfdx) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + if (DCL_CRG_GetPllRefClkSel(CRG) == CRG_PLL_REF_CLK_SELECT_HOSC) { + cfdx->CMTGTCTRL.BIT.tgtsel = CMM_TARGET_CLK_HOSC; + } else { + cfdx->CMTGTCTRL.BIT.tgtsel = CMM_TARGET_CLK_TCXO; + } + cfdx->CMTGTCTRL.BIT.tgtscale = CMM_TARGET_FREQ_DIV_8192; /* target clock frequence 8192 division. */ + cfdx->CMREFCTRL.BIT.refsel = CMM_REF_CLK_LOSC; + cfdx->CMREFCTRL.BIT.refdiv = CMM_REF_FREQ_DIV_0; +} + +/** + * @brief Sets the upper boundary of the detection window. + * @param cfdx CFD register base address. + * @param value The value of the upper bound. + * @retval None. + */ +static inline void DCL_CFD_SetWindowUpperBound(CFD_RegStruct *cfdx, unsigned int value) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + CMWDOH_Reg cfdwdoh; + cfdwdoh.reg = cfdx->CMWDOH.reg; /* Retain the cmwdoh original value. */ + cfdwdoh.BIT.cfdwdoh = value; + cfdx->CMWDOH.reg = cfdwdoh.reg; +} + +/** + * @brief Gets the upper boundary of the detection window. + * @param cfdx CFD register base address. + * @retval The value of the upper bound. + */ +static inline unsigned int DCL_CFD_GetWindowUpperBound(CFD_RegStruct *cfdx) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + CMWDOH_Reg cfdwdoh; + cfdwdoh.reg = cfdx->CMWDOH.reg; + return cfdwdoh.BIT.cfdwdoh; +} + +/** + * @brief Internal counter count latch value. + * @param cfdx CFD register base address. + * @retval unsigned int. latch value. + */ +static inline unsigned int DCL_CFD_GetCntValue(CFD_RegStruct *cfdx) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + return cfdx->CMCNTLOCK.BIT.cmcnt_lock; +} + +/** + * @brief Enables the specified type of interrupt. + * @param cfdx CFD register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CFD_EnableInterrupt(CFD_RegStruct *cfdx, CFD_Interrupt_Type type) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + CFD_PARAM_CHECK_NO_RET(type == CFD_INT_CHECK_END_MASK || \ + type == CFD_INT_PLL_REF_CLOCK_STOP_MASK); + cfdx->CMINTENA.reg |= type; +} + +/** + * @brief Disables the specified type of interrupt. + * @param cfdx CFD register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CFD_DisableInterrupt(CFD_RegStruct *cfdx, CFD_Interrupt_Type type) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + CFD_PARAM_CHECK_NO_RET(type == CFD_INT_CHECK_END_MASK || \ + type == CFD_INT_PLL_REF_CLOCK_STOP_MASK); + cfdx->CMINTENA.reg &= (~type); +} + +/** + * @brief Get CFD interrupt type. + * @param cfdx CFD register base address. + * @retval unsigned int. + */ +static inline unsigned int DCL_CFD_GetInterruptType(CFD_RegStruct *cfdx) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + return cfdx->CMINTENA.reg; +} + +/** + * @brief Check whether the specified interrupt is triggered. + * @param cfdx CFD register base address. + * @param type Mask of the interrupt type. + * @retval bool. + */ +static inline bool DCL_CFD_GetInterruptStatus(CFD_RegStruct *cfdx, CFD_Interrupt_Type type) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + CFD_PARAM_CHECK_WITH_RET(type == CFD_INT_CHECK_END_MASK || \ + type == CFD_INT_PLL_REF_CLOCK_STOP_MASK, false); + return (cfdx->CMINTSTS.reg & type) == 0 ? false : true; +} + +/** + * @brief Clears interrupts of the specified type. + * @param cfdx CFD register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CFD_ClearInterrupt(CFD_RegStruct *cfdx, CFD_Interrupt_Type type) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + CFD_PARAM_CHECK_NO_RET(type == CFD_INT_CHECK_END_MASK || \ + type == CFD_INT_PLL_REF_CLOCK_STOP_MASK); + cfdx->CMINTRAW.reg |= type; +} + +/** + * @brief Injects interrupts of the specified type. + * @param cfdx CFD register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CFD_EnableInterruptInject(CFD_RegStruct *cfdx, CFD_Interrupt_Type type) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + CFD_PARAM_CHECK_NO_RET(type == CFD_INT_CHECK_END_MASK || \ + type == CFD_INT_PLL_REF_CLOCK_STOP_MASK); + cfdx->CMINTINJ.reg |= type; +} + +/** + * @brief Stop injecting interrupts of a specified type. + * @param cfdx CFD register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CFD_DisableInterruptInject(CFD_RegStruct *cfdx, CFD_Interrupt_Type type) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + CFD_PARAM_CHECK_NO_RET(type == CFD_INT_CHECK_END_MASK || \ + type == CFD_INT_PLL_REF_CLOCK_STOP_MASK); + cfdx->CMINTINJ.reg &= (~type); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_CFD_IP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/cfd/src/cfd.c b/vendor/xinlingyu_92_3061M/Project/drivers/cfd/src/cfd.c new file mode 100644 index 0000000000000000000000000000000000000000..76f51e03cafdfb10fe3024a6dbc132f7d9b7797c --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/cfd/src/cfd.c @@ -0,0 +1,181 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cfd.c + * @author MCU Driver Team + * @brief CFD module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the CFD. + * + Initialization and de-initialization functions. + * + Config the register of cfd. + * + Interrupt callback function and user registration function. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "cfd.h" + +/** + * @brief Perform initial configuration based on the handle. + * @param handle CFD handle. + * @retval @ref BASE_StatusType. + */ +BASE_StatusType HAL_CFD_Init(CFD_Handle *handle) +{ + CFD_ASSERT_PARAM(handle != NULL); + CFD_ASSERT_PARAM(IsCFDInstance(handle->baseAddress)); + DCL_CFD_SetWindowUpperBound(handle->baseAddress, handle->upperBound); + DCL_CFD_EnableInterrupt(handle->baseAddress, handle->interruptType); + /* Set CFD clock. */ + if (handle->baseAddress->CMWDOH.BIT.cmwdoh == 0xFFFF) { + DCL_CFD_SetCfdClock(handle->baseAddress); + } + return BASE_STATUS_OK; +} + +/** + * @brief Deinitialize configurations based on the handle. + * @param handle CFD handle. + * @retval @ref BASE_StatusType. + */ +BASE_StatusType HAL_CFD_DeInit(CFD_Handle *handle) +{ + CFD_ASSERT_PARAM(handle != NULL); + CFD_ASSERT_PARAM(IsCFDInstance(handle->baseAddress)); + /* Clear interrupt callback function. */ + handle->userCallBack.PllClockStopCallback = NULL; + handle->userCallBack.CheckEndCallback = NULL; + /* Clear register value. */ + DCL_CFD_DisableInterrupt(handle->baseAddress, BASE_CFG_DISABLE); + return BASE_STATUS_OK; +} + +/** + * @brief Set this parameter based on the configuration item parameters. + * @param handle CFD handle. + * @param cfgType Configurable item. @ref CFD_CFG_TYPE. + * @retval @ref BASE_StatusType. + */ +BASE_StatusType HAL_CFD_Config(CFD_Handle *handle, CFD_CFG_TYPE cfgType) +{ + CFD_ASSERT_PARAM(handle != NULL); + CFD_ASSERT_PARAM(IsCFDInstance(handle->baseAddress)); + /* CFD config type. */ + switch (cfgType) { + case CFD_CFG_UPPER_BOUND: /* Config upperbound. */ + DCL_CFD_SetWindowUpperBound(handle->baseAddress, handle->upperBound); + break; + case CFD_CFG_INT_TYPE: /* Config interrupt type. */ + DCL_CFD_EnableInterrupt(handle->baseAddress, handle->interruptType); + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief Reads the register configuration value to the handle. + * @param handle CFD handle. + * @retval None. + */ +void HAL_CFD_GetConfig(CFD_Handle *handle) +{ + CFD_ASSERT_PARAM(handle != NULL); + CFD_ASSERT_PARAM(IsCFDInstance(handle->baseAddress)); + handle->upperBound = DCL_CFD_GetWindowUpperBound(handle->baseAddress); + handle->interruptType = DCL_CFD_GetInterruptType(handle->baseAddress); +} + +/** + * @brief Start CFD Module. + * @param handle CFD handle. + * @retval None. + */ +void HAL_CFD_Start(CFD_Handle *handle) +{ + CFD_ASSERT_PARAM(handle != NULL); + CFD_ASSERT_PARAM(IsCFDInstance(handle->baseAddress)); + DCL_CFD_Enable(handle->baseAddress); +} + +/** + * @brief Stop CFD Module. + * @param handle CFD handle. + * @retval None. + */ +void HAL_CFD_Stop(CFD_Handle *handle) +{ + CFD_ASSERT_PARAM(handle != NULL); + CFD_ASSERT_PARAM(IsCFDInstance(handle->baseAddress)); + DCL_CFD_Disable(handle->baseAddress); +} + +/** + * @brief Registers the interrupt function to the specified interrupt type. + * @param handle CFD handle. + * @param type Specified interrupt type. + * @param callback Interrupt callback function. + * @retval @ref BASE_StatusType. + */ +BASE_StatusType HAL_CFD_RegisterCallback(CFD_Handle *handle, CFD_Interrupt_Type type, CFD_CallBackFuncType callback) +{ + CFD_ASSERT_PARAM(handle != NULL); + CFD_ASSERT_PARAM(callback != NULL); + CFD_ASSERT_PARAM(IsCFDInstance(handle->baseAddress)); + /* Interrupt type. */ + switch (type) { + case CFD_INT_PLL_REF_CLOCK_STOP_MASK: /* Clock stop interrupt. */ + handle->userCallBack.PllClockStopCallback = callback; + break; + case CFD_INT_CHECK_END_MASK: /* Check end interrupt. */ + handle->userCallBack.CheckEndCallback = callback; + break; + default: + return BASE_STATUS_ERROR; + } + + return BASE_STATUS_OK; +} + +/** + * @brief Interrupt service processing function. + * @param handle CFD Handle. + * @retval None. + */ +void HAL_CFD_IrqHandler(void *handle) +{ + CFD_ASSERT_PARAM(handle != NULL); + CFD_Handle *cfdHandle = (CFD_Handle *)handle; + CFD_ASSERT_PARAM(IsCFDInstance(cfdHandle->baseAddress)); + + /* PLL clock stop interrupt. */ + if (cfdHandle->baseAddress->CMINTSTS.BIT.clk_fail_int == 0x01) { + cfdHandle->baseAddress->CMINTRAW.BIT.clk_fail_raw = BASE_CFG_SET; + if (cfdHandle->userCallBack.PllClockStopCallback) { + cfdHandle->userCallBack.PllClockStopCallback(cfdHandle); + } + } + + /* Check end interrupt. */ + if (cfdHandle->baseAddress->CMINTSTS.BIT.chk_end_int == 0x01) { + cfdHandle->baseAddress->CMINTRAW.BIT.chk_end_raw = BASE_CFG_SET; + if (cfdHandle->userCallBack.CheckEndCallback) { + cfdHandle->userCallBack.CheckEndCallback(cfdHandle); + } + } +} diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/cmm/common/inc/cmm.h b/vendor/xinlingyu_92_3061M/Project/drivers/cmm/common/inc/cmm.h new file mode 100644 index 0000000000000000000000000000000000000000..fedc5f3680e16c738531803a24eea25efe811b87 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/cmm/common/inc/cmm.h @@ -0,0 +1,121 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cmm.h + * @author MCU Driver Team + * @brief CMM module driver. + * @details This file provides firmware CMM Handle structure and Functions + * prototypes to manage the following functionalities of the CMM module. + * + Initialization and de-initialization functions + * + config the register of CMM module + */ + +#ifndef McuMagicTag_CMM_H +#define McuMagicTag_CMM_H + +/* Includes ------------------------------------------------------------------ */ +#include "cmm_ip.h" + +/* Macro definitions ---------------------------------------------------------*/ +/** + * @defgroup CMM CMM + * @brief CMM module. + * @{ + */ + +/** + * @defgroup CMM_Common CMM Common + * @brief CMM common external module. + * @{ + */ + +/** + * @defgroup CMM_Handle_Definition CMM Handle Definition + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ + +/** + * @brief CMM module configurable item. + */ +typedef enum { + CMM_CFG_TRIGGER_MODE = 0x00000001U, + CMM_CFG_TARGET_SOURCE = 0x00000002U, + CMM_CFG_TARGET_FREQ_DIV = 0x00000003U, + CMM_CFG_REF_SOURCE = 0x00000004U, + CMM_CFG_REF_FREQ_DIV = 0x00000005U, + CMM_CFG_UPPER_BOUND = 0x00000006U, + CMM_CFG_LOWER_BOUND = 0x00000007U, + CMM_CFG_INT_TYPE = 0x00000008U, + CMM_CFG_MAX +} CMM_CFG_TYPE; + +/** + * @brief CMM handle. + */ +typedef struct _CMM_Handle { + CMM_RegStruct *baseAddress; /**< CMM registers base address. */ + CMM_Trigger_Mode mode; /**< Effective edge of the target clock. */ + CMM_Target_Freq_Div_Value targetFreqDivision; /**< Frequency divider of the working target clock. */ + CMM_Ref_Freq_Div_Value refFreqDivision; /**< Frequency divider of the working reference clock. */ + CMM_Target_Clock_Source targetClockSource; /**< Working target clock source selection. */ + CMM_Ref_Clock_Source refClockSource; /**< Working reference clock source selection. */ + unsigned short upperBound; /**< Upper bound of window. */ + unsigned short lowerBound; /**< Lower bound of window. */ + CMM_Interrupt_Type interruptType; /**< Enabled interrupt type. */ + CMM_UserCallBack userCallBack; /**< CMM Interrupt callback functions.*/ + CMM_ExtendHandle handleEx; /**< CMM extend parameter */ +} CMM_Handle; + +/** + * @brief Typedef callback function of CMM + */ +typedef void (*CMM_CallBackFuncType)(void *handle); + +/** + * @} + */ + +/** + * @defgroup CMM_API_Declaration CMM HAL API + * @{ + */ + +/* Hardware abstraction layer functions -------------------------------------------------------- */ +BASE_StatusType HAL_CMM_Init(CMM_Handle *handle); +BASE_StatusType HAL_CMM_DeInit(CMM_Handle *handle); +BASE_StatusType HAL_CMM_Config(CMM_Handle *handle, CMM_CFG_TYPE cfgType); +void HAL_CMM_GetConfig(CMM_Handle *handle); +void HAL_CMM_Start(CMM_Handle *handle); +void HAL_CMM_Stop(CMM_Handle *handle); +BASE_StatusType HAL_CMM_RegisterCallback(CMM_Handle *handle, CMM_Interrupt_Type type, CMM_CallBackFuncType callback); +void HAL_CMM_IrqHandler(void *handle); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_UART_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/cmm/inc/cmm_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/cmm/inc/cmm_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..129916eb37eeff34667f26700c1a7b5a96ae6d12 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/cmm/inc/cmm_ip.h @@ -0,0 +1,612 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cmm_ip.h + * @author MCU Driver Team + * @brief CMM module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the CMM. + * + Register Struct of CMM + * + CMM Register Map struct + * + Direct Configuration Layer functions of CMM + */ + +#ifndef McuMagicTag_CMM_IP_H +#define McuMagicTag_CMM_IP_H + +/* Includes ------------------------------------------------------------------ */ +#include "baseinc.h" +/* Macro definitions ------------------------------------------------------- */ +#ifdef CMM_PARAM_CHECK + #define CMM_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM + #define CMM_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET + #define CMM_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else + #define CMM_ASSERT_PARAM(para) ((void)0U) + #define CMM_PARAM_CHECK_NO_RET(para) ((void)0U) + #define CMM_PARAM_CHECK_WITH_RET(param, ret) ((void)0U) +#endif +/** + * @addtogroup CMM + * @{ + */ + +/** + * @defgroup CMM_IP: cmm_v1 + * @{ + */ + +/** + * @defgroup CMM_Param_Def CMM Parameters Definition + * @brief Description of CMM configuration parameters. + * @{ + */ + +/* Typedef definitions ------------------------------------------------------- */ +typedef enum { + CMM_TRIGGER_RISE = 0x00000000U, + CMM_TRIGGER_FALL = 0x00000001U, + CMM_TRIGGER_BOTH = 0x00000002U, + CMM_TRIGGER_NONE = 0x00000003U, + CMM_TRIGGER_MAX +} CMM_Trigger_Mode; + +typedef enum { + CMM_TARGET_FREQ_DIV_0 = 0x00000000U, + CMM_TARGET_FREQ_DIV_32 = 0x00000001U, + CMM_TARGET_FREQ_DIV_128 = 0x00000002U, + CMM_TARGET_FREQ_DIV_1024 = 0x00000003U, + CMM_TARGET_FREQ_DIV_8192 = 0x00000004U, + CMM_TARGET_FREQ_DIV_MAX +} CMM_Target_Freq_Div_Value; + +typedef enum { + CMM_REF_FREQ_DIV_0 = 0x00000000U, + CMM_REF_FREQ_DIV_4 = 0x00000001U, + CMM_REF_FREQ_DIV_8 = 0x00000002U, + CMM_REF_FREQ_DIV_32 = 0x00000003U, + CMM_REF_FREQ_DIV_MAX +} CMM_Ref_Freq_Div_Value; + +typedef enum { + CMM_TARGET_CLK_LOSC = 0x00000000U, + CMM_TARGET_CLK_HOSC = 0x00000001U, + CMM_TARGET_CLK_TCXO = 0x00000002U, + CMM_TARGET_CLK_HS_SYS = 0x00000003U, + CMM_TARGET_CLK_MAX +} CMM_Target_Clock_Source; + +typedef enum { + CMM_REF_CLK_LOSC = 0x00000000U, + CMM_REF_CLK_HOSC = 0x00000001U, + CMM_REF_CLK_TCXO = 0x00000002U, + CMM_REF_CLK_HS_SYS = 0x00000003U, + CMM_REF_CLK_MAX +} CMM_Ref_Clock_Source; + +typedef enum { + CMM_INT_COUNTER_OVERFLOW_MASK = 0x00000001U, + CMM_INT_CHECK_END_MASK = 0x00000002U, + CMM_INT_FREQ_ERR_MASK = 0x00000004U, + CMM_INT_CLOCK_FAIL_MASK = 0x00000008U, + CMM_INT_MAX +} CMM_Interrupt_Type; + +/** + * @} + */ + +/** + * @defgroup CMM_Reg_Def CMM Register Definition + * @brief Description CMM register mapping structure. + * @{ + */ + +/** + * @brief CMM version registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int month_day : 16; /**< Month and day. */ + unsigned int year : 8; /**< Year. */ + unsigned int release_ver : 3; /**< Version information. */ + unsigned int reserved0 : 5; + } BIT; +} volatile CMVER_Reg; + +/** + * @brief CMM control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cmen : 1; /**< CMM enable or disable. */ + unsigned int cfen : 1; /**< CFD clock failure detection enable. */ + unsigned int reserved0 : 30; + } BIT; +} volatile CMCTRL_Reg; + +/** + * @brief CMM target clock control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int tgtsel : 3; /**< CMM target clock source. */ + unsigned int reserved0 : 1; + unsigned int tgtscale : 3; /**< CMM target clock divide factor. */ + unsigned int reserved1 : 1; + unsigned int reserved2 : 24; + } BIT; +} volatile CMTGTCTRL_Reg; + +/** + * @brief CMM reference clock control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int refsel : 2; /**< CMM reference clock source. */ + unsigned int reserved0 : 2; + unsigned int refdiv : 2; /**< CMM reference clock divide factor. */ + unsigned int reserved1 : 26; + } BIT; +} volatile CMREFCTRL_Reg; + +/** + * @brief CMM check window upper bound registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cmwdoh : 16; /**< CMM clock frequence error check window upper bound value. */ + unsigned int cfdwdoh : 16; /**< CMM clock failure check window upper bound value. */ + } BIT; +} volatile CMWDOH_Reg; + +/** + * @brief CMM check window low bound registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cmwdol : 16; /**< CMM check window low bound value. */ + unsigned int reserved0 : 16; + } BIT; +} volatile CMWDOL_Reg; + +/** + * @brief CMM count locked value registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cmcnt_lock : 16; /**< CMM count locked value */ + unsigned int reserved0 : 16; + } BIT; +} volatile CMCNTLOCK_Reg; + +/** + * @brief CMM interrupt enable registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cnt_ovf_en : 1; /**< CMM count overflow interrupt enable. */ + unsigned int chk_end_en : 1; /**< CMM check end interrupt enable. */ + unsigned int freq_err_en : 1; /**< CMM frequence error interrupt enable. */ + unsigned int clk_fail_en : 1; /**< CMM clock failure interrupt enable. */ + unsigned int reserved0 : 28; + } BIT; +} volatile CMINTENA_Reg; + +/** + * @brief CMM interrupt status registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cnt_ovf_int : 1; /**< CMM count overflow interrupt status. */ + unsigned int chk_end_int : 1; /**< CMM check end interrupt status. */ + unsigned int freq_err_int : 1; /**< CMM frequence error interrupt status. */ + unsigned int clk_fail_int : 1; /**< CMM clock failure interrupt status. */ + unsigned int reserved0 : 28; + } BIT; +} volatile CMINTSTS_Reg; + +/** + * @brief CMM initial interrupt registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cnt_ovf_raw : 1; /**< CMM count overflow initial interrupt. */ + unsigned int chk_end_raw : 1; /**< CMM check end initial interrupt. */ + unsigned int freq_err_raw : 1; /**< CMM frequence error initial interrupt. */ + unsigned int clk_fail_raw : 1; /**< CMM clock failure initial interrupt. */ + unsigned int reserved0 : 28; + } BIT; +} volatile CMINTRAW_Reg; + +/** + * @brief CMM interrupt injection registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cnt_ovf_inj : 1; /**< CMM frequence error interrupt injection. */ + unsigned int chk_end_inj : 1; /**< CMM check end interrupt injection. */ + unsigned int freq_err_inj : 1; /**< CMM frequence error interrupt injection. */ + unsigned int clk_fail_inj : 1; /**< CMM clock failure interrupt injection. */ + unsigned int reserved0 : 28; + } BIT; +} volatile CMINTINJ_Reg; + +/** + * @brief CMM status registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cnt_frozen : 1; /**< CMM counter frozen status. */ + unsigned int reserved0 : 31; + } BIT; +} volatile CMSTS_Reg; + +/** + * @brief CMM Interrupt callback functions. + * + */ +typedef struct { + void (*FreqErrorCallback)(void *handle); /**< Clock frequency error callback function */ + void (*CheckEndCallback)(void *handle); /**< End of each check callback function */ + void (*CountOverflowCallback)(void *handle); /**< Count Overflow callback function */ +} CMM_UserCallBack; + +/** + * @brief CMM extend handle. + */ +typedef struct _CMM_ExtendeHandle { +} CMM_ExtendHandle; + +/** + * @brief CMM register mapping structure. + */ +typedef struct { + CMVER_Reg CMVER; /**< CMM version register, offset address: 0x0000. */ + CMCTRL_Reg CMCTRL; /**< CMM control register, offset address: 0x0004. */ + CMTGTCTRL_Reg CMTGTCTRL; /**< CMM target clock control register, offset address: 0x0008. */ + CMREFCTRL_Reg CMREFCTRL; /**< CMM reference clock control register, offset address: 0x000C. */ + CMWDOH_Reg CMWDOH; /**< CMM check window upper bound register, offset address: 0x0010. */ + CMWDOL_Reg CMWDOL; /**< CMM check window low bound register, offset address: 0x0014. */ + CMCNTLOCK_Reg CMCNTLOCK; /**< CMM count locked value register, offset address: 0x0018. */ + CMINTENA_Reg CMINTENA; /**< CMM interrupt enable register, offset address: 0x001C. */ + CMINTSTS_Reg CMINTSTS; /**< CMM interrupt status register, offset address: 0x0020. */ + CMINTRAW_Reg CMINTRAW; /**< CMM initial interrupt register, offset address: 0x0024. */ + CMINTINJ_Reg CMINTINJ; /**< CMM interrupt injection register, offset address: 0x0028. */ + CMSTS_Reg CMSTS; /**< CMM status register, offset Address: 0x002C. */ +} volatile CMM_RegStruct; + +/** + * @} + */ +/** + * @brief Get CMM's release ver and year and month day. + * @param cmmx CMM register base address. + * @retval None. + */ +static inline unsigned int DCL_CMM_GetVersion(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + return cmmx->CMVER.reg; +} + + +/** + * @brief Enable CMM's clock monitor function. + * @param cmmx CMM register base address. + * @retval None. + */ +static inline void DCL_CMM_Enable(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + cmmx->CMCTRL.BIT.cmen = BASE_CFG_ENABLE; +} + +/** + * @brief Disable CMM's clock monitor function. + * @param cmmx CMM register base address. + * @retval None. + */ +static inline void DCL_CMM_Disable(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + cmmx->CMCTRL.BIT.cmen = BASE_CFG_DISABLE; +} + +/** + * @brief Sets the frequency divider of the target clock. + * @param cmmx CMM register base address. + * @param value Specified frequency divider. + * @retval None. + */ +static inline void DCL_CMM_SetTargetClockFreqDivision(CMM_RegStruct *cmmx, CMM_Target_Freq_Div_Value value) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_NO_RET(value < CMM_TARGET_FREQ_DIV_MAX); + cmmx->CMTGTCTRL.BIT.tgtscale = value; +} + +/** + * @brief Gets the frequency divider of the target clock. + * @param cmmx CMM register base address. + * @retval unsigned int @ref CMM_Target_Freq_Div_Value. + */ +static inline unsigned int DCL_CMM_GetTargetClockFreqDivision(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + return cmmx->CMTGTCTRL.BIT.tgtscale; +} + +/** + * @brief Sets the target clock source. + * @param cmmx CMM register base address. + * @param clockSource Specifies the type of the clock source. + * @retval None. + */ +static inline void DCL_CMM_SetTargetClockSource(CMM_RegStruct *cmmx, CMM_Target_Clock_Source clockSource) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_NO_RET(clockSource < CMM_TARGET_CLK_MAX); + cmmx->CMTGTCTRL.BIT.tgtsel = clockSource; +} + +/** + * @brief Gets the target clock source. + * @param cmmx CMM register base address. + * @retval unsigned int @ref CMM_Target_Clock_Source. + */ +static inline unsigned int DCL_CMM_GetTargetClockSource(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + return cmmx->CMTGTCTRL.BIT.tgtsel; +} + +/** + * @brief Sets the frequency divider of the reference clock. + * @param cmmx CMM register base address. + * @param value Specified frequency divider. + * @retval None. + */ +static inline void DCL_CMM_SetRefClockFreqDivision(CMM_RegStruct *cmmx, CMM_Ref_Freq_Div_Value value) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_NO_RET(value < CMM_REF_FREQ_DIV_MAX); + cmmx->CMREFCTRL.BIT.refdiv = value; +} + +/** + * @brief Gets the frequency divider of the reference clock. + * @param cmmx CMM register base address. + * @retval unsigned int @ref CMM_Ref_Freq_Div_Value. + */ +static inline unsigned int DCL_CMM_GetRefClockFreqDivision(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + return cmmx->CMREFCTRL.BIT.refdiv; +} + +/** + * @brief Sets the reference clock source. + * @param cmmx CMM register base address. + * @param clockSource Specified reference clock source. + * @retval None. + */ +static inline void DCL_CMM_SetRefClockSource(CMM_RegStruct *cmmx, CMM_Ref_Clock_Source clockSource) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_NO_RET(clockSource < CMM_REF_CLK_MAX); + cmmx->CMREFCTRL.BIT.refsel = clockSource; +} + +/** + * @brief Gets the reference clock source. + * @param cmmx CMM register base address. + * @retval unsigned int @ref CMM_Ref_Clock_Source. + */ +static inline unsigned int DCL_CMM_GetRefClockSource(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + return cmmx->CMREFCTRL.BIT.refsel; +} + +/** + * @brief Set the cmm's upper boundary of the detection windowL. + * @param cmmx CMM register base address. + * @param value The value of the cmm upper bound. + * @retval None. + */ +static inline void DCL_CMM_SetCmmWindowUpperBound(CMM_RegStruct *cmmx, unsigned short value) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + cmmx->CMWDOH.BIT.cmwdoh = value; +} + +/** + * @brief Gets the cmm's upper boundary of the detection window. + * @param cmmx CMM register base address. + * @retval The value of the cmm's upper bound. + */ +static inline unsigned short DCL_CMM_GetCmmWindowUpperBound(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + return cmmx->CMWDOH.BIT.cmwdoh; +} + +/** + * @brief Sets the cmm's lower boundary of the detection window. + * @param cmmx CMM register base address. + * @param value The value of the cmm's lower bound. + * @retval None. + */ +static inline void DCL_CMM_SetCmmWindowLowerBound(CMM_RegStruct *cmmx, unsigned short value) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + cmmx->CMWDOL.BIT.cmwdol = value; +} + +/** + * @brief Gets the lower boundary of the detection window. + * @param cmmx CMM register base address. + * @retval The value of the cmm's lower bound. + */ +static inline unsigned short DCL_CMM_GetCmmWindowLowerBound(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + return cmmx->CMWDOL.BIT.cmwdol; +} + +/** + * @brief Internal counter count latch value. + * @param cmmx CMM register base address. + * @retval unsigned short. latch value. + */ +static inline unsigned short DCL_CMM_GetCntValue(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + return cmmx->CMCNTLOCK.BIT.cmcnt_lock; +} + +/** + * @brief check whether is interrupt type. + * @param type Mask of the interrupt type. + * @retval bool. + */ +static inline bool IsCMMInterruptType(CMM_Interrupt_Type type) +{ + return (type == CMM_INT_COUNTER_OVERFLOW_MASK || \ + type == CMM_INT_CHECK_END_MASK || \ + type == CMM_INT_CLOCK_FAIL_MASK || \ + type == CMM_INT_FREQ_ERR_MASK); +} + +/** + * @brief Enables the specified type of interrupt. + * @param cmmx CMM register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CMM_EnableInterrupt(CMM_RegStruct *cmmx, CMM_Interrupt_Type type) +{ + /* if define macro CMM_PARAM_CHECK, function of param check is valid */ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_NO_RET(IsCMMInterruptType(type)); + cmmx->CMINTENA.reg |= type; +} + +/** + * @brief Disables the specified type of interrupt. + * @param cmmx CMM register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CMM_DisableInterrupt(CMM_RegStruct *cmmx, CMM_Interrupt_Type type) +{ + /* if define macro CMM_PARAM_CHECK, function of param check is valid */ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_NO_RET(IsCMMInterruptType(type)); + cmmx->CMINTENA.reg &= (~type); +} + +/** + * @brief Check whether the specified interrupt is triggered. + * @param cmmx CMM register base address. + * @param type Mask of the interrupt type. + * @retval bool. + */ +static inline bool DCL_CMM_GetInterruptStatus(CMM_RegStruct *cmmx, CMM_Interrupt_Type type) +{ + /* if define macro CMM_PARAM_CHECK, function of param check is valid */ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_WITH_RET(IsCMMInterruptType(type), false); + return (cmmx->CMINTSTS.reg & type) == 0 ? false : true; +} + +/** + * @brief Clears interrupts of the specified type. + * @param cmmx CMM register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CMM_ClearInterrupt(CMM_RegStruct *cmmx, CMM_Interrupt_Type type) +{ + /* if define macro CMM_PARAM_CHECK, function of param check is valid */ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_NO_RET(IsCMMInterruptType(type)); + cmmx->CMINTRAW.reg |= type; +} + +/** + * @brief Injects interrupts of the specified type. + * @param cmmx CMM register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CMM_EnableInterruptInject(CMM_RegStruct *cmmx, CMM_Interrupt_Type type) +{ + /* if define macro CMM_PARAM_CHECK, function of param check is valid */ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_NO_RET(IsCMMInterruptType(type)); + cmmx->CMINTINJ.reg |= type; +} + +/** + * @brief Stop injecting interrupts of a specified type. + * @param cmmx CMM register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CMM_DisableInterruptInject(CMM_RegStruct *cmmx, CMM_Interrupt_Type type) +{ + /* if define macro CMM_PARAM_CHECK, function of param check is valid */ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_NO_RET(IsCMMInterruptType(type)); + cmmx->CMINTINJ.reg &= (~type); +} + +/** + * @brief Check cmm cnt whether is frozen or not. + * @param cmmx CMM register base address. + * @retval bool. + */ +static inline bool DCL_CMM_CheckCntFrozenState(CMM_RegStruct *cmmx) +{ + /* if define macro CMM_PARAM_CHECK, function of param check is valid */ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + return cmmx->CMSTS.BIT.cnt_frozen; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_CMM_IP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/cmm/src/cmm.c b/vendor/xinlingyu_92_3061M/Project/drivers/cmm/src/cmm.c new file mode 100644 index 0000000000000000000000000000000000000000..fbc8e26bb6ed2b714025a89022fe338ae902e91d --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/cmm/src/cmm.c @@ -0,0 +1,235 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cmm.c + * @author MCU Driver Team + * @brief CMM module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the CMM. + * + Initialization and de-initialization functions. + * + Config the register of CMM. + * + Interrupt callback function and user registration function. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "cmm.h" + +/** + * @brief Perform initial configuration based on the handle. + * @param handle CMM handle. + * @retval @ref BASE_StatusType. + */ +BASE_StatusType HAL_CMM_Init(CMM_Handle *handle) +{ + /* param check */ + CMM_ASSERT_PARAM(handle != NULL); + CMM_ASSERT_PARAM(IsCMMInstance(handle->baseAddress)); + CMM_PARAM_CHECK_WITH_RET(handle->targetClockSource < CMM_TARGET_CLK_MAX, BASE_STATUS_ERROR); + CMM_PARAM_CHECK_WITH_RET(handle->targetFreqDivision < CMM_TARGET_FREQ_DIV_MAX, BASE_STATUS_ERROR); + CMM_PARAM_CHECK_WITH_RET(handle->refClockSource < CMM_REF_CLK_MAX, BASE_STATUS_ERROR); + CMM_PARAM_CHECK_WITH_RET(handle->refFreqDivision < CMM_REF_FREQ_DIV_MAX, BASE_STATUS_ERROR); + CMM_PARAM_CHECK_WITH_RET(handle->interruptType < CMM_INT_MAX, BASE_STATUS_ERROR); + /* init handle value into register */ + /* Init CMM target clock. */ + DCL_CMM_SetTargetClockSource(handle->baseAddress, handle->targetClockSource); + DCL_CMM_SetTargetClockFreqDivision(handle->baseAddress, handle->targetFreqDivision); + /* Init CMM reference clock. */ + DCL_CMM_SetRefClockSource(handle->baseAddress, handle->refClockSource); + DCL_CMM_SetRefClockFreqDivision(handle->baseAddress, handle->refFreqDivision); + /* Init CMM UpperBound and LowerBound. */ + DCL_CMM_SetCmmWindowUpperBound(handle->baseAddress, handle->upperBound); + DCL_CMM_SetCmmWindowLowerBound(handle->baseAddress, handle->lowerBound); + DCL_CMM_EnableInterrupt(handle->baseAddress, handle->interruptType); + return BASE_STATUS_OK; +} + +/** + * @brief Deinitialize configurations based on the handle. + * @param handle CMM handle. + * @retval @ref BASE_StatusType. + */ +BASE_StatusType HAL_CMM_DeInit(CMM_Handle *handle) +{ + CMM_ASSERT_PARAM(handle != NULL); + CMM_ASSERT_PARAM(IsCMMInstance(handle->baseAddress)); + /* Clear interrupt callback function. */ + handle->userCallBack.FreqErrorCallback = NULL; + handle->userCallBack.CheckEndCallback = NULL; + handle->userCallBack.CountOverflowCallback = NULL; + /* Disables the specified type of interrupt. */ + DCL_CMM_DisableInterrupt(handle->baseAddress, handle->interruptType); + return BASE_STATUS_OK; +} + +/** + * @brief Set this parameter based on the configuration item parameters. + * @param handle CMM handle. + * @param cfgType Configurable item. @ref CMM_CFG_TYPE. + * @retval @ref BASE_StatusType. + */ +BASE_StatusType HAL_CMM_Config(CMM_Handle *handle, CMM_CFG_TYPE cfgType) +{ + /* param check */ + CMM_ASSERT_PARAM(handle != NULL); + CMM_ASSERT_PARAM(IsCMMInstance(handle->baseAddress)); + CMM_PARAM_CHECK_WITH_RET(handle->targetClockSource < CMM_TARGET_CLK_MAX, BASE_STATUS_ERROR); + CMM_PARAM_CHECK_WITH_RET(handle->targetFreqDivision < CMM_TARGET_FREQ_DIV_MAX, BASE_STATUS_ERROR); + CMM_PARAM_CHECK_WITH_RET(handle->refClockSource < CMM_REF_CLK_MAX, BASE_STATUS_ERROR); + CMM_PARAM_CHECK_WITH_RET(handle->refFreqDivision < CMM_REF_FREQ_DIV_MAX, BASE_STATUS_ERROR); + CMM_PARAM_CHECK_WITH_RET(handle->interruptType < CMM_INT_MAX, BASE_STATUS_ERROR); + /* config register value with different type of cmm member */ + switch (cfgType) { + case CMM_CFG_UPPER_BOUND: + DCL_CMM_SetCmmWindowUpperBound(handle->baseAddress, handle->upperBound); /* upperBound value */ + break; + case CMM_CFG_LOWER_BOUND: + DCL_CMM_SetCmmWindowLowerBound(handle->baseAddress, handle->lowerBound); /* lowerBound value */ + break; + case CMM_CFG_TARGET_SOURCE: + DCL_CMM_SetTargetClockSource(handle->baseAddress, handle->targetClockSource); /* target Clock Source */ + break; + case CMM_CFG_TARGET_FREQ_DIV: + /* target Freq Division */ + DCL_CMM_SetTargetClockFreqDivision(handle->baseAddress, handle->targetFreqDivision); + break; + case CMM_CFG_REF_SOURCE: + DCL_CMM_SetRefClockSource(handle->baseAddress, handle->refClockSource); /* ref Clock Source */ + break; + case CMM_CFG_REF_FREQ_DIV: + DCL_CMM_SetRefClockFreqDivision(handle->baseAddress, handle->refFreqDivision); /* ref Freq Division */ + break; + case CMM_CFG_INT_TYPE: + DCL_CMM_EnableInterrupt(handle->baseAddress, handle->interruptType); /* interrupt Type */ + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief Reads the register configuration value to the handle. + * @param handle CMM handle. + * @retval None. + */ +void HAL_CMM_GetConfig(CMM_Handle *handle) +{ + /* param check */ + CMM_ASSERT_PARAM(handle != NULL); + CMM_ASSERT_PARAM(IsCMMInstance(handle->baseAddress)); + /* Get config of cmm member from register */ + handle->upperBound = DCL_CMM_GetCmmWindowUpperBound(handle->baseAddress); + handle->lowerBound = DCL_CMM_GetCmmWindowLowerBound(handle->baseAddress); + handle->targetClockSource = DCL_CMM_GetTargetClockSource(handle->baseAddress); + handle->targetFreqDivision = DCL_CMM_GetTargetClockFreqDivision(handle->baseAddress); + handle->refClockSource = DCL_CMM_GetRefClockSource(handle->baseAddress); + handle->refFreqDivision = DCL_CMM_GetRefClockFreqDivision(handle->baseAddress); +} + +/** + * @brief Start CMM Module. + * @param handle CMM handle. + * @retval None. + */ +void HAL_CMM_Start(CMM_Handle *handle) +{ + CMM_ASSERT_PARAM(handle != NULL); + CMM_ASSERT_PARAM(IsCMMInstance(handle->baseAddress)); + DCL_CMM_Enable(handle->baseAddress); +} + +/** + * @brief Stop CMM Module. + * @param handle CMM handle. + * @retval None. + */ +void HAL_CMM_Stop(CMM_Handle *handle) +{ + CMM_ASSERT_PARAM(handle != NULL); + CMM_ASSERT_PARAM(IsCMMInstance(handle->baseAddress)); + DCL_CMM_Disable(handle->baseAddress); +} + +/** + * @brief Registers the interrupt function to the specified interrupt type. + * @param handle CMM handle. + * @param type Specified interrupt type. + * @param callback Interrupt callback function. + * @retval @ref BASE_StatusType. + */ +BASE_StatusType HAL_CMM_RegisterCallback(CMM_Handle *handle, CMM_Interrupt_Type type, CMM_CallBackFuncType callback) +{ + CMM_ASSERT_PARAM(handle != NULL); + CMM_ASSERT_PARAM(callback != NULL); + CMM_ASSERT_PARAM(IsCMMInstance(handle->baseAddress)); + + switch (type) { + case CMM_INT_FREQ_ERR_MASK: /* Frequence error interrupt. */ + handle->userCallBack.FreqErrorCallback = callback; + break; + case CMM_INT_CHECK_END_MASK: /* Check end interrupt. */ + handle->userCallBack.CheckEndCallback = callback; + break; + case CMM_INT_COUNTER_OVERFLOW_MASK: /* Counter overflow interrupt. */ + handle->userCallBack.CountOverflowCallback = callback; + break; + default: + return BASE_STATUS_ERROR; + } + + return BASE_STATUS_OK; +} + +/** + * @brief Interrupt service processing function. + * @param handle CMM Handle. + * @retval None. + */ +void HAL_CMM_IrqHandler(void *handle) +{ + CMM_ASSERT_PARAM(handle != NULL); + CMM_Handle *cmmHandle = (CMM_Handle *)handle; + CMM_ASSERT_PARAM(IsCMMInstance(cmmHandle->baseAddress)); + + /* Frequence error interrupt. */ + if (cmmHandle->baseAddress->CMINTSTS.BIT.freq_err_int == 0x01) { + cmmHandle->baseAddress->CMINTRAW.BIT.freq_err_raw = BASE_CFG_SET; + /* Disable and then enable the CMM to ensure that the CMM can still work. */ + cmmHandle->baseAddress->CMCTRL.BIT.cmen = BASE_CFG_UNSET; + cmmHandle->baseAddress->CMCTRL.BIT.cmen = BASE_CFG_SET; + if (cmmHandle->userCallBack.FreqErrorCallback) { + cmmHandle->userCallBack.FreqErrorCallback(cmmHandle); + } + } + + /* Check end interrupt. */ + if (cmmHandle->baseAddress->CMINTSTS.BIT.chk_end_int == 0x01) { + cmmHandle->baseAddress->CMINTRAW.BIT.chk_end_raw = BASE_CFG_SET; + if (cmmHandle->userCallBack.CheckEndCallback) { + cmmHandle->userCallBack.CheckEndCallback(cmmHandle); + } + } + + /* Counter overflow interrupt. */ + if (cmmHandle->baseAddress->CMINTSTS.BIT.cnt_ovf_int == 0x01) { + cmmHandle->baseAddress->CMINTRAW.BIT.cnt_ovf_raw = BASE_CFG_SET; + if (cmmHandle->userCallBack.CountOverflowCallback) { + cmmHandle->userCallBack.CountOverflowCallback(cmmHandle); + } + } +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/crc/common/inc/crc.h b/vendor/xinlingyu_92_3061M/Project/drivers/crc/common/inc/crc.h new file mode 100644 index 0000000000000000000000000000000000000000..4e73620c05caf05518bfda0d24fd5189aec22445 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/crc/common/inc/crc.h @@ -0,0 +1,100 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file crc.h + * @author MCU Driver Team + * @brief CRC module driver + * @details The header file contains the following declaration: + * + CRC handle structure definition. + * + Initialization functions. + * + CRC Set And Get Functions. + * + Interrupt Handler Functions. + */ + +#ifndef McuMagicTag_CRC_H +#define McuMagicTag_CRC_H +/* Includes ------------------------------------------------------------------*/ +#include "crc_ip.h" + +/* Macro definition */ +/** + * @defgroup CRC CRC + * @brief CRC module. + * @{ + */ + +/** + * @defgroup CRC_Common CRC Common + * @brief CRC common external module. + * @{ + */ + +/** + * @defgroup CRC_Handle_Definition CRC Handle Definition + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ +typedef void (* CRC_CallbackType)(void *handle); + +/** + * @brief CRC handle structure definition. + */ +typedef struct _CRC_Handle { + CRC_RegStruct *baseAddress; /**< CRC Registers */ + CRC_InputDataFormat inputDataFormat; /**< CRC byte mode */ + CRC_PolynomialMode polyMode; /**< CRC polynomial mode */ + CRC_InitValueType initValueType; /**< CRC init value type */ + CRC_ResultXorValueType resultXorValueType; /**< CRC result xor value type */ + CRC_ReverseEnableType reverseEnableType; /**< input and output reverse type */ + CRC_XorEndianEnableType xorEndianEnbaleType; /**< xor enable and endian enable type */ + CRC_UserCallBack userCallBack; /**< User callback */ + CRC_ExtendHandle handleEx; /**< CRC extend parameter */ +} CRC_Handle; + +/** + * @} + */ + +/** + * @defgroup CRC_API_Declaration CRC HAL API + * @{ + */ +BASE_StatusType HAL_CRC_Init(CRC_Handle *handle); +void HAL_CRC_DeInit(CRC_Handle *handle); +unsigned int HAL_CRC_SetInputDataGetCheck(CRC_Handle *handle, unsigned int data); +unsigned int HAL_CRC_Accumulate(CRC_Handle *handle, const void *pData, unsigned int length); +unsigned int HAL_CRC_Calculate(CRC_Handle *handle, const void *pData, unsigned int length); +bool HAL_CRC_CheckInputData(CRC_Handle *handle, const void *pData, unsigned int length, unsigned int crcValue); +void HAL_CRC_SetCheckInData(CRC_Handle *handle, unsigned int data); +unsigned int HAL_CRC_LoadCheckInData(CRC_Handle *handle); +void HAL_CRC_RegisterCallback(CRC_Handle *handle, CRC_CallbackType callBackFunc); +void HAL_CRC_IrqHandler(void *handle); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_CRC_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/crc/inc/crc_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/crc/inc/crc_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..3eb7502f1913cab00c87866d97d465bd95198978 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/crc/inc/crc_ip.h @@ -0,0 +1,613 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file crc_ip.h + * @author MCU Driver Team + * @brief CRC module driver + * @details The header file contains the following declaration: + * + CRC configuration enums. + * + CRC register structures. + * + CRC DCL Functions. + * + Parameters check functions. + */ + +#ifndef McuMagicTag_CRC_IP_H +#define McuMagicTag_CRC_IP_H +/* Includes ------------------------------------------------------------------*/ +#include "baseinc.h" +/* Macro definitions -------------------------------------------------------*/ + +#ifdef CRC_PARAM_CHECK + #define CRC_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM + #define CRC_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET + #define CRC_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else + #define CRC_ASSERT_PARAM(para) ((void)0U) + #define CRC_PARAM_CHECK_NO_RET(para) ((void)0U) + #define CRC_PARAM_CHECK_WITH_RET(param, ret) ((void)0U) +#endif + +#define TYPE_POLY_MASK 0x0000000FU +#define TYPE_INIT_MASK 0x00000F00U +#define TYPE_XOR_VALUE_MASK 0x000F0000U +#define TYPE_REVERSE_ENABLE_MASK 0x0F000000U +#define TYPE_XOR_ENDIAN_ENABLE_MASK 0xF0000000U + +#define TYPE_ENDIAN_MSB_BIT 0x10000000U +#define TYPE_XOR_ENABLE_BIT 0x20000000U +#define TYPE_OUTPUT_REVERSE_ENABLE_BIT 0x01000000U +#define TYPE_BYTE_REVERSE_ENABLE_BIT 0x02000000U +/** + * @addtogroup CRC + * @{ + */ + +/** + * @defgroup CRC_IP CRC_IP + * @brief CRC_IP: crc_v1. + * @{ + */ + +/** + * @defgroup CRC_Param_Def CRC Parameters Definition + * @brief Description of CRC configuration parameters. + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ +typedef enum { + CRC8_07_POLY_MODE = 0x00000000U, + CRC8_07_POLY_MODE_BK = 0x00000001U, + CRC16_8005_POLY_MODE = 0x00000002U, + CRC16_1021_POLY_MODE = 0x00000003U, + CRC32_04C11D87_POLY_MODE = 0x00000004U, + CRC32_04C11D87_POLY_MODE_BK = 0x00000005U, + CRC_POLY_MODE_MAX +} CRC_PolynomialMode; + +typedef enum { + TYPE_CRC_INIT_VALUE_00 = 0x00000100U, + TYPE_CRC_INIT_VALUE_FF = 0x00000200U, + TYPE_CRC_INIT_VALUE_0000 = 0x00000300U, + TYPE_CRC_INIT_VALUE_FFFF = 0x00000400U, + TYPE_CRC_INIT_VALUE_FFFFFFFF = 0x00000500U +} CRC_InitValueType; + +typedef enum { + CRC_INIT_VALUE_00 = 0x00000000U, + CRC_INIT_VALUE_FF = 0x000000FFU, + CRC_INIT_VALUE_0000 = 0x00000000U, + CRC_INIT_VALUE_FFFF = 0x0000FFFFU, + CRC_INIT_VALUE_FFFFFFFF = 0xFFFFFFFFU +} CRC_InitValue; + +typedef enum { + TYPE_CRC_XOR_VALUE_00 = 0x00010000U, + TYPE_CRC_XOR_VALUE_55 = 0x00020000U, + TYPE_CRC_XOR_VALUE_0000 = 0x00030000U, + TYPE_CRC_XOR_VALUE_FFFF = 0x00040000U, + TYPE_CRC_XOR_VALUE_00000000 = 0x00050000U, + TYPE_CRC_XOR_VALUE_FFFFFFFF = 0x00060000U +} CRC_ResultXorValueType; + +typedef enum { + CRC_XOR_VALUE_00 = 0x00000000U, + CRC_XOR_VALUE_55 = 0x00000055U, + CRC_XOR_VALUE_0000 = 0x00000000U, + CRC_XOR_VALUE_FFFF = 0x0000FFFFU, + CRC_XOR_VALUE_00000000 = 0x00000000U, + CRC_XOR_VALUE_FFFFFFFF = 0xFFFFFFFFU +} CRC_ResultXorValue; + +typedef enum { + REVERSE_INPUT_FALSE_OUTPUT_FALSE = 0x00000000U, + REVERSE_INPUT_FALSE_OUTPUT_TRUE = 0x01000000U, + REVERSE_INPUT_TURE_OUTPUT_FALSE = 0x02000000U, + REVERSE_INPUT_TURE_OUTPUT_TRUE = 0x03000000U +} CRC_ReverseEnableType; + +typedef enum { + DISABLE_XOR_ENABLE_LSB = 0x00000000U, + DISABLE_XOR_ENABLE_MSB = 0x10000000U, + ENABLE_XOR_ENABLE_LSB = 0x20000000U, + ENABLE_XOR_ENABLE_MSB = 0x30000000U +} CRC_XorEndianEnableType; + +/** + * @brief CRC byte type register configuration. + */ +typedef enum { + CRC_MODE_BIT8 = 0x00000000U, + CRC_MODE_BIT16 = 0x00000001U, + CRC_MODE_BIT32 = 0x00000002U +} CRC_InputDataFormat; + +/** + * @brief CRC algorithm type. + */ +typedef enum { + CRC8 = ENABLE_XOR_ENABLE_LSB | REVERSE_INPUT_FALSE_OUTPUT_FALSE | TYPE_CRC_XOR_VALUE_00 | \ + TYPE_CRC_INIT_VALUE_00 | CRC8_07_POLY_MODE, + CRC8_ITU = ENABLE_XOR_ENABLE_LSB | REVERSE_INPUT_FALSE_OUTPUT_FALSE | TYPE_CRC_XOR_VALUE_55 | \ + TYPE_CRC_INIT_VALUE_00 | CRC8_07_POLY_MODE, + CRC8_ROHC = ENABLE_XOR_ENABLE_LSB | REVERSE_INPUT_TURE_OUTPUT_TRUE | TYPE_CRC_XOR_VALUE_00 | \ + TYPE_CRC_INIT_VALUE_FF | CRC8_07_POLY_MODE, + CRC16_IBM = ENABLE_XOR_ENABLE_LSB | REVERSE_INPUT_TURE_OUTPUT_TRUE | TYPE_CRC_XOR_VALUE_0000 | \ + TYPE_CRC_INIT_VALUE_0000 | CRC16_8005_POLY_MODE, + CRC16_MAXIM = ENABLE_XOR_ENABLE_LSB | REVERSE_INPUT_TURE_OUTPUT_TRUE | TYPE_CRC_XOR_VALUE_FFFF | \ + TYPE_CRC_INIT_VALUE_0000 | CRC16_8005_POLY_MODE, + CRC16_USB = ENABLE_XOR_ENABLE_LSB | REVERSE_INPUT_TURE_OUTPUT_TRUE | TYPE_CRC_XOR_VALUE_FFFF | \ + TYPE_CRC_INIT_VALUE_FFFF | CRC16_8005_POLY_MODE, + CRC16_MODBUS = ENABLE_XOR_ENABLE_LSB | REVERSE_INPUT_TURE_OUTPUT_TRUE | TYPE_CRC_XOR_VALUE_0000 | \ + TYPE_CRC_INIT_VALUE_FFFF | CRC16_8005_POLY_MODE, + CRC16_CCITT = ENABLE_XOR_ENABLE_LSB | REVERSE_INPUT_TURE_OUTPUT_TRUE | TYPE_CRC_XOR_VALUE_0000 | \ + TYPE_CRC_INIT_VALUE_0000 | CRC16_1021_POLY_MODE, + CRC16_CCITT_FALSE = ENABLE_XOR_ENABLE_LSB | REVERSE_INPUT_FALSE_OUTPUT_FALSE | TYPE_CRC_XOR_VALUE_0000 | \ + TYPE_CRC_INIT_VALUE_FFFF | CRC16_1021_POLY_MODE, + CRC16_X25 = ENABLE_XOR_ENABLE_LSB | REVERSE_INPUT_TURE_OUTPUT_TRUE | TYPE_CRC_XOR_VALUE_FFFF | \ + TYPE_CRC_INIT_VALUE_FFFF | CRC16_1021_POLY_MODE, + CRC16_XMODEM = ENABLE_XOR_ENABLE_LSB | REVERSE_INPUT_FALSE_OUTPUT_FALSE | TYPE_CRC_XOR_VALUE_0000 | \ + TYPE_CRC_INIT_VALUE_0000 | CRC16_1021_POLY_MODE, + CRC32 = ENABLE_XOR_ENABLE_LSB | REVERSE_INPUT_TURE_OUTPUT_TRUE | TYPE_CRC_XOR_VALUE_FFFFFFFF | \ + TYPE_CRC_INIT_VALUE_FFFFFFFF | CRC32_04C11D87_POLY_MODE, + CRC32_MPEG2 = ENABLE_XOR_ENABLE_LSB | REVERSE_INPUT_FALSE_OUTPUT_FALSE | TYPE_CRC_XOR_VALUE_00000000 | \ + TYPE_CRC_INIT_VALUE_FFFFFFFF | CRC32_04C11D87_POLY_MODE, + CRC_ALG_MODE_MAX +} CRC_AlgorithmMode; + +/** + * @brief CRC extend handle. + */ +typedef struct _CRC_ExtendeHandle { + CRC_AlgorithmMode algoMode; /**< CRC calculate algorithm mode */ +} CRC_ExtendHandle; + +/** + * @brief CRC user callback. + */ +typedef struct { +} CRC_UserCallBack; +/** + * @} + */ + +/** + * @defgroup CRC_Reg_Def CRC Register Definition + * @brief Description CRC register mapping structure. + * @{ + */ + +/** + * @brief CRC calc poly register union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int crc_calc_poly : 3; /**< crc calc polynomial set. */ + unsigned int reserved0 : 29; + } BIT; +} volatile CRC_CALC_CFG_REG; + +/** + * @brief CRC soft reset register union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int crc_calc_reset : 1; /**< crc calc soft reset signal. */ + unsigned int reserved0 : 31; + } BIT; +} volatile CRC_CALC_RESET_REG; + +/** + * @brief CRC init register union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int crc_calc_init : 1; /**< crc init value load signal. */ + unsigned int reserved0 : 31; + } BIT; +} volatile CRC_CALC_INIT_REG; + +/** + * @brief CRC pre set register union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int crc_pre_byte_reverse : 1; /**< crc pre byte reverse enable. */ + unsigned int crc_pre_endian_mode : 1; /**< crc pre endian set mode. */ + unsigned int reserved0 : 30; + } BIT; +} volatile CRC_PRE_CFG_REG; + +/** + * @brief CRC post set register union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int crc_post_xor_enable : 1; /**< crc result xor enable. */ + unsigned int crc_post_out_reverse : 1; /**< crc result reverse enable. */ + unsigned int reserved0 : 30; + } BIT; +} volatile CRC_POST_CFG_REG; + +/** + * @brief CRC assemble registers structure definition + */ +typedef struct { + CRC_CALC_CFG_REG CRC_CALC_CFG; /**< crc calc poly register. */ + CRC_CALC_RESET_REG CRC_CALC_RESET; /**< crc soft reset register. */ + CRC_CALC_INIT_REG CRC_CALC_INIT; /**< crc init register. */ + unsigned int crc_post_xor_value; /**< crc post process xor value register. */ + unsigned int crc_calc_init_value; /**< crc init value register. */ + unsigned int crc_data_in; /**< crc input data register. */ + unsigned int crc_out; /**< crc result register. */ + CRC_PRE_CFG_REG CRC_PRE_CFG; /**< crc pre set register. */ + CRC_POST_CFG_REG CRC_POST_CFG; /**< crc post set register. */ +} volatile CRC_RegStruct; + +/** + * @} + */ +/** + * @brief Set CRC polyniaml mode. + * @param crcx Value of @ref CRC_RegStruct. + * @param polyMode Value of @ref CRC_PolynomialMode. + * @retval None. + */ +static inline void DCL_CRC_SetPolynomialMode(CRC_RegStruct *crcx, CRC_PolynomialMode polyMode) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + CRC_PARAM_CHECK_NO_RET(polyMode < CRC_POLY_MODE_MAX && polyMode >= CRC8_07_POLY_MODE); + crcx->CRC_CALC_CFG.BIT.crc_calc_poly = polyMode; +} + +/** + * @brief Get CRC polyniaml mode. + * @param crcx Value of @ref CRC_RegStruct. + * @retval CRC_PolynomialMode. + */ +static inline CRC_PolynomialMode DCL_CRC_GetPolynomialMode(CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + return crcx->CRC_CALC_CFG.BIT.crc_calc_poly; +} + +/** + * @brief Set CRC soft reset function. + * @param crcx Value of @ref CRC_RegStruct. + * @retval None. + */ +static inline void DCL_CRC_SoftReset(CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + crcx->CRC_CALC_RESET.BIT.crc_calc_reset = BASE_CFG_SET; +} + +/** + * @brief Enable CRC init function. + * @param crcx Value of @ref CRC_RegStruct. + * @retval None. + */ +static inline void DCL_CRC_LoadInitValue(CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + crcx->CRC_CALC_INIT.BIT.crc_calc_init = BASE_CFG_SET; +} + +/** + * @brief Set CRC result xor value function. + * @param crcx Value of @ref CRC_RegStruct. + * @param value Value of CRC calulate result. + * @retval None. + */ +static inline void DCL_CRC_SetResultXorValue(CRC_RegStruct *crcx, unsigned int value) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + crcx->crc_post_xor_value = value; +} + +/** + * @brief Get CRC result xor value function. + * @param crcx Value of @ref CRC_RegStruct. + * @retval unsigned int value of result xor value. + */ +static inline unsigned int DCL_CRC_GetResultXorValue(CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + return crcx->crc_post_xor_value; +} + +/** + * @brief Set CRC init value function. + * @param crcx Value of @ref CRC_RegStruct. + * @param initValue value of CRC calulate init value. + * @retval None. + */ +static inline void DCL_CRC_SetInitValue(CRC_RegStruct *crcx, unsigned int initValue) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + crcx->crc_calc_init_value = initValue; +} + +/** + * @brief Get CRC init value function. + * @param crcx Value of @ref CRC_RegStruct. + * @retval unsigned int init value. + */ +static inline unsigned int DCL_CRC_GetInitValue(CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + return crcx->crc_calc_init_value; +} + +/** + * @brief Set CRC data 8 in value function. + * @param crcx Value of @ref CRC_RegStruct. + * @param data value of CRC calulate data value. + * @retval None. + */ +static inline void DCL_CRC_SetInputData8(CRC_RegStruct *crcx, unsigned char data) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + volatile unsigned char *crcData8 = (unsigned char *)(void *)(&crcx->crc_data_in); + *(crcData8) = data; +} + +/** + * @brief Set CRC data 16 in value function. + * @param crcx Value of @ref CRC_RegStruct. + * @param data value of CRC calulate data value. + * @retval None. + */ +static inline void DCL_CRC_SetInputData16(CRC_RegStruct *crcx, unsigned short data) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + volatile unsigned short *crcData16 = (unsigned short *)(void *)(&crcx->crc_data_in); + *(crcData16) = data; +} + +/** + * @brief Set CRC data 32 in value function. + * @param crcx Value of @ref CRC_RegStruct. + * @param data value of CRC calulate data value. + * @retval None. + */ +static inline void DCL_CRC_SetInputData32(CRC_RegStruct *crcx, unsigned int data) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + crcx->crc_data_in = data; +} + +/** + * @brief Get CRC data in value function. + * @param crcx Value of @ref CRC_RegStruct. + * @retval unsigned int crc data in. + */ +static inline unsigned int DCL_CRC_GetInputData(CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + return crcx->crc_data_in; +} + +/** + * @brief Get CRC data in value function. + * @param crcx Value of @ref CRC_RegStruct. + * @retval unsigned int crc data out. + */ +static inline unsigned int DCL_CRC_GetOutputData(CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + return crcx->crc_out; +} + +/** + * @brief Set CRC input data endian mode function. + * @param crcx Value of @ref CRC_RegStruct. + * @param mode true means big endian, false means little endian. + * @retval None. + */ +static inline void DCL_CRC_SetEndianMode(CRC_RegStruct *crcx, bool mode) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + crcx->CRC_PRE_CFG.BIT.crc_pre_endian_mode = mode; +} + +/** + * @brief Get CRC input data endian mode function. + * @param crcx Value of @ref CRC_RegStruct. + * @retval bool crc endian mode. + */ +static inline bool DCL_CRC_GetEndianMode(CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + return crcx->CRC_PRE_CFG.BIT.crc_pre_endian_mode; +} + +/** + * @brief Set CRC input data byte reverse function. + * @param crcx Value of @ref CRC_RegStruct. + * @param mode true means reverse, false means none. + * @retval None. + */ +static inline void DCL_CRC_SetByteReverseMode(CRC_RegStruct *crcx, bool mode) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + crcx->CRC_PRE_CFG.BIT.crc_pre_byte_reverse = mode; +} + +/** + * @brief Get CRC input data byte reverse function. + * @param crcx Value of @ref CRC_RegStruct. + * @retval bool crc byte reverse mode. + */ +static inline bool DCL_CRC_GetByteReverseMode(CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + return crcx->CRC_PRE_CFG.BIT.crc_pre_byte_reverse; +} + +/** + * @brief Set CRC output result reverse function. + * @param crcx Value of @ref CRC_RegStruct. + * @param mode true means reverse, false means none. + * @retval None. + */ +static inline void DCL_CRC_SetOutputReverseMode(CRC_RegStruct *crcx, bool mode) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + crcx->CRC_POST_CFG.BIT.crc_post_out_reverse = mode; +} + +/** + * @brief Get CRC output result reverse function. + * @param crcx Value of @ref CRC_RegStruct. + * @retval bool crc out reverse mode. + */ +static inline bool DCL_CRC_GetOutputReverseMode(CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + return crcx->CRC_POST_CFG.BIT.crc_post_out_reverse; +} + +/** + * @brief Set CRC result xor mode function. + * @param crcx Value of @ref CRC_RegStruct. + * @param mode true means reverse, false means none. + * @retval None. + */ +static inline void DCL_CRC_SetXorResultMode(CRC_RegStruct *crcx, bool mode) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + crcx->CRC_POST_CFG.BIT.crc_post_xor_enable = mode; /* 0 means disable, 1 means enable */ +} + +/** + * @brief Get CRC result xor mode function. + * @param crcx Value of @ref CRC_RegStruct. + * @retval bool crc xor enable mode. + */ +static inline bool DCL_CRC_GetXorResultMode(CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + return crcx->CRC_POST_CFG.BIT.crc_post_xor_enable; +} + +/** + * @brief Check crc polynomial mode. + * @param mode Value of @ref CRC_PolynomialMode. + * @retval Bool + */ +static inline bool IsCrcPolynomial(unsigned int mode) +{ + /* Check crc polynomial mode. */ + return (mode == CRC8_07_POLY_MODE || mode == CRC8_07_POLY_MODE_BK || \ + mode == CRC16_8005_POLY_MODE || mode == CRC16_1021_POLY_MODE || \ + mode == CRC32_04C11D87_POLY_MODE || mode == CRC32_04C11D87_POLY_MODE_BK); +} + +/** + * @brief Check crc init value type. + * @param mode Value of @ref CRC_InitValueType. + * @retval Bool + */ +static inline bool IsCrcInitValueType(unsigned int value) +{ + /* Check crc polynomial mode. */ + return (value == TYPE_CRC_INIT_VALUE_00 || value == TYPE_CRC_INIT_VALUE_FF || \ + value == TYPE_CRC_INIT_VALUE_0000 || value == TYPE_CRC_INIT_VALUE_FFFF || \ + value == TYPE_CRC_INIT_VALUE_FFFFFFFF); +} + +/** + * @brief Check crc result xor value type. + * @param mode Value of @ref CRC_ResultXorValueType. + * @retval Bool + */ +static inline bool IsCrcResultXorValueType(unsigned int value) +{ + /* Check crc polynomial mode. */ + return (value == TYPE_CRC_XOR_VALUE_00 || value == TYPE_CRC_XOR_VALUE_55 || \ + value == TYPE_CRC_XOR_VALUE_0000 || value == TYPE_CRC_XOR_VALUE_FFFF || \ + value == TYPE_CRC_XOR_VALUE_00000000 || value == TYPE_CRC_XOR_VALUE_FFFFFFFF); +} + +/** + * @brief Check crc reverse enable type. + * @param mode Value of @ref CRC_ReverseEnableType. + * @retval Bool + */ +static inline bool IsCrcXorEndianEnableType(unsigned int type) +{ + /* Check crc reverse enable type. */ + return (type == ENABLE_XOR_ENABLE_LSB || type == ENABLE_XOR_ENABLE_MSB || \ + type == DISABLE_XOR_ENABLE_LSB || type == DISABLE_XOR_ENABLE_MSB); +} + +/** + * @brief Check crc reverse enable type. + * @param mode Value of @ref CRC_ReverseEnableType. + * @retval Bool + */ +static inline bool IsCrcReverseEnableType(unsigned int type) +{ + /* Check crc reverse enable type. */ + return (type == REVERSE_INPUT_FALSE_OUTPUT_FALSE || type == REVERSE_INPUT_FALSE_OUTPUT_TRUE || \ + type == REVERSE_INPUT_TURE_OUTPUT_FALSE || type == REVERSE_INPUT_TURE_OUTPUT_TRUE); +} + +/** + * @brief Check crc valid byte mode. + * @param mode Value of @ref CRC_InputDataFormat. + * @retval Bool + */ +static inline bool IsCrcInputDataFormat(unsigned int mode) +{ + return (mode == CRC_MODE_BIT8 || + mode == CRC_MODE_BIT16 || + mode == CRC_MODE_BIT32); +} + +/** + * @brief Check crc algorithm mode. + * @param mode Value of @ref CRC_AlgorithmMode. + * @retval Bool + */ +static inline bool IsCrcAlgorithm(CRC_AlgorithmMode mode) +{ + /* Check crc algorithm mode. */ + return (mode == CRC8 || mode == CRC8_ITU || \ + mode == CRC8_ROHC || mode == CRC16_IBM || \ + mode == CRC16_MAXIM || mode == CRC16_USB || \ + mode == CRC16_MODBUS || mode == CRC16_CCITT || \ + mode == CRC16_CCITT_FALSE || mode == CRC16_X25 || \ + mode == CRC16_XMODEM || mode == CRC32 || \ + mode == CRC32_MPEG2); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_CRC_IP_H */ diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/crc/src/crc.c b/vendor/xinlingyu_92_3061M/Project/drivers/crc/src/crc.c new file mode 100644 index 0000000000000000000000000000000000000000..5b010ead2fa18dbe2bf184685ed0833a9c2a52c5 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/crc/src/crc.c @@ -0,0 +1,441 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file crc.c + * @author MCU Driver Team + * @brief CRC module driver + * @details This file provides firmware functions to manage the following functionalities of the GPIO. + * + Initialization functions. + * + CRC Set And Get Functions. + * + Interrupt Handler Functions. + */ + +/* Includes ------------------------------------------------------------------ */ +#include "interrupt.h" +#include "crc.h" + +#define WORD_DIV_BYTE_SIZE 4 +#define WORD_DIV_DOUBLE_SIZE 2 + +#define OFFSET_ONE_BYTE 1 +#define OFFSET_TWO_BYTE 2 +#define OFFSET_THREE_BYTE 3 + +#define BIT_SHIFT24 24 +#define BIT_SHIFT16 16 +#define BIT_SHIFT8 8 + +#define REMAINDER_SIZE_ONE 1 +#define REMAINDER_SIZE_TWO 2 +#define REMAINDER_SIZE_THREE 3 +#define REMAINDER_RANGE_THREE 3 +#define REMAINDER_RANGE_ONE 1 + +#define CRC8_MODE_07_REG_VALUE 0 +#define CRC16_MODE_8005_REG_VALUE 2 +#define CRC16_MODE_1021_REG_VALUE 3 +#define CRC32_MODE_04C11D87_REG_VALUE 4 + +static void CRC_Handle_8(CRC_Handle *handle, const unsigned char *pData, unsigned int length); +static void CRC_Handle_16(CRC_Handle *handle, const unsigned short *pData, unsigned int length); +static void CRC_Handle_32(CRC_Handle *handle, const unsigned int *pData, unsigned int length); +static void CRC_SetPolynomialModeByAlgorithm(CRC_Handle *handle, CRC_AlgorithmMode algorithmMode); +static void CRC_SetXorEndianReverseEnableByAlgorithm(CRC_Handle *handle, CRC_AlgorithmMode algorithmMode); +static void CRC_SetXorValueByAlgorithm(CRC_Handle *handle, CRC_AlgorithmMode algorithmMode); +static void CRC_SetInitValueByAlgorithm(CRC_Handle *handle, CRC_AlgorithmMode algorithmMode); +static void CRC_SetResultXorValue(CRC_Handle *handle, CRC_ResultXorValueType type); +static void CRC_SetInitValue(CRC_Handle *handle, CRC_InitValueType type); + +/** + * @brief Initializing CRC register values. + * @param handle Value of @ref CRC_Handle. + * @retval BASE_StatusType BASE Status. + */ +BASE_StatusType HAL_CRC_Init(CRC_Handle *handle) +{ + /* PARAM check */ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + CRC_PARAM_CHECK_WITH_RET(IsCrcInputDataFormat(handle->inputDataFormat), BASE_STATUS_ERROR); + DCL_CRC_SoftReset(handle->baseAddress); + if (IsCrcAlgorithm(handle->handleEx.algoMode)) { + /* Algorithm Mode Parameter Configuration */ + CRC_SetPolynomialModeByAlgorithm(handle, handle->handleEx.algoMode); + CRC_SetXorEndianReverseEnableByAlgorithm(handle, handle->handleEx.algoMode); + CRC_SetXorValueByAlgorithm(handle, handle->handleEx.algoMode); + CRC_SetInitValueByAlgorithm(handle, handle->handleEx.algoMode); + } else { + /* CRC PARAM check */ + CRC_PARAM_CHECK_WITH_RET(IsCrcPolynomial(handle->polyMode), BASE_STATUS_ERROR); + CRC_PARAM_CHECK_WITH_RET(IsCrcInitValueType(handle->initValueType), BASE_STATUS_ERROR); + CRC_PARAM_CHECK_WITH_RET(IsCrcResultXorValueType(handle->resultXorValueType), BASE_STATUS_ERROR); + CRC_PARAM_CHECK_WITH_RET(IsCrcReverseEnableType(handle->reverseEnableType), BASE_STATUS_ERROR); + CRC_PARAM_CHECK_WITH_RET(IsCrcXorEndianEnableType(handle->xorEndianEnbaleType), BASE_STATUS_ERROR); + unsigned int polyMode = handle->polyMode; /* algorithmic polynomial mode */ + bool inputEndianMode = ((handle->xorEndianEnbaleType & TYPE_ENDIAN_MSB_BIT) == TYPE_ENDIAN_MSB_BIT); + bool inputByteReverse = + ((handle->reverseEnableType & TYPE_BYTE_REVERSE_ENABLE_BIT) == TYPE_BYTE_REVERSE_ENABLE_BIT); + bool outputReverse = + ((handle->reverseEnableType & TYPE_OUTPUT_REVERSE_ENABLE_BIT) == TYPE_OUTPUT_REVERSE_ENABLE_BIT); + bool resultXorEnable = ((handle->xorEndianEnbaleType & TYPE_XOR_ENABLE_BIT) == TYPE_XOR_ENABLE_BIT); + /* DCL CRC set parameters */ + DCL_CRC_SetPolynomialMode(handle->baseAddress, polyMode); + DCL_CRC_SetEndianMode(handle->baseAddress, inputEndianMode); + DCL_CRC_SetByteReverseMode(handle->baseAddress, inputByteReverse); + DCL_CRC_SetOutputReverseMode(handle->baseAddress, outputReverse); + DCL_CRC_SetXorResultMode(handle->baseAddress, resultXorEnable); + /* Extended Interface Parameter Settings */ + if (handle->baseAddress->CRC_POST_CFG.BIT.crc_post_xor_enable == BASE_CFG_ENABLE) { + CRC_SetResultXorValue(handle, handle->resultXorValueType); + } + CRC_SetInitValue(handle, handle->initValueType); + DCL_CRC_LoadInitValue(handle->baseAddress); + } + return BASE_STATUS_OK; +} + +/** + * @brief DeInitializing CRC register values. + * @param handle Value of @ref CRC_Handle. + * @retval None. + */ +void HAL_CRC_DeInit(CRC_Handle *handle) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + /* Reset CRC calculation data */ + DCL_CRC_SoftReset(handle->baseAddress); +} + +/** + * @brief Set CRC input data and get CRC output. + * @param handle Value of @ref CRC_Handle. + * @param data CRC input data. + * @retval unsigned int CRC output data. + */ +unsigned int HAL_CRC_SetInputDataGetCheck(CRC_Handle *handle, unsigned int data) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + DCL_CRC_SetInputData32(handle->baseAddress, data); /* Set CRC input data */ + return DCL_CRC_GetOutputData(handle->baseAddress); +} + +/** + * @brief Compute the 8, 16 or 32-bit CRC value of an 8, 16 or + 32-bit data buffer starting with the previously computed CRC as initialization value. + * @param handle Value of @ref CRC_Handle. + * @param pData Pointer to the input data buffer. + * @param length pData array length. + * @retval unsigned int CRC output data. + */ +unsigned int HAL_CRC_Accumulate(CRC_Handle *handle, const void *pData, unsigned int length) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(pData != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + switch (handle->inputDataFormat) { + case CRC_MODE_BIT8: + CRC_Handle_8(handle, (unsigned char *)pData, length); /* Input register to compute 8-bit data value */ + break; + case CRC_MODE_BIT16: + CRC_Handle_16(handle, (unsigned short *)pData, length); /* Input register to compute 16-bit data value */ + break; + case CRC_MODE_BIT32: + CRC_Handle_32(handle, (unsigned int *)pData, length); /* Input register to compute 32-bit data value */ + break; + default: + break; + } + return DCL_CRC_GetOutputData(handle->baseAddress); +} + +/** + * @brief Compute the 8, 16 or 32-bit CRC value of an 8, 16 or + 32-bit data buffer starting with default initialization value. + * @param handle Value of @ref CRC_Handle. + * @param pData Pointer to the input data buffer. + * @param length pData array length. + * @retval unsigned int CRC output data. + */ +unsigned int HAL_CRC_Calculate(CRC_Handle *handle, const void *pData, unsigned int length) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(pData != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + DCL_CRC_LoadInitValue(handle->baseAddress); /* load init value */ + return HAL_CRC_Accumulate(handle, pData, length); +} + +/** + * @brief Compute the 8-bit input data to the CRC calculator. + * @param handle Value of @ref CRC_Handle. + * @param pData Pointer to the input data buffer. + * @param length pData array length. + * @retval unsigned int CRC output data. + */ +static void CRC_Handle_8(CRC_Handle *handle, const unsigned char *pData, unsigned int length) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(pData != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + volatile unsigned char *crcData8 = (unsigned char *)(void *)(&handle->baseAddress->crc_data_in); + for (unsigned int i = 0; i < length; i++) { + *(crcData8) = pData[i]; /* input crc data */ + } +} + +/** + * @brief Compute the 16-bit input data to the CRC calculator. + * @param handle Value of @ref CRC_Handle. + * @param pData Pointer to the input data buffer. + * @param length pData array length. + * @retval unsigned int CRC output data. + */ +static void CRC_Handle_16(CRC_Handle *handle, const unsigned short *pData, unsigned int length) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(pData != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + volatile unsigned short *crcData16 = (unsigned short *)(void *)(&handle->baseAddress->crc_data_in); + for (unsigned int i = 0; i < length; i++) { + *(crcData16) = pData[i]; /* input crc data */ + } +} + +/** + * @brief Compute the 32-bit input data to the CRC calculator. + * @param handle Value of @ref CRC_Handle. + * @param pData Pointer to the input data buffer. + * @param length pData array length. + * @retval unsigned int CRC output data. + */ +static void CRC_Handle_32(CRC_Handle *handle, const unsigned int *pData, unsigned int length) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(pData != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + volatile unsigned int *crcData32 = (unsigned int *)(void *)(&handle->baseAddress->crc_data_in); + for (unsigned int i = 0; i < length; i++) { + *(crcData32) = pData[i]; /* input crc data */ + } +} + +/** + * @brief Check whether the recived data CRC value is the same as the expected value. + * @param handle Value of @ref CRC_Handle. + * @param pData Pointer to the input data buffer, + exact input data byte mode is provided by handle->inputDataFormat. + * @param length pData array length. + * @param crcValue CRC check value. + * @retval unsigned int CRC check result + */ +bool HAL_CRC_CheckInputData(CRC_Handle *handle, const void *pData, unsigned int length, unsigned int crcValue) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(pData != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + return (HAL_CRC_Calculate(handle, pData, length) == crcValue); +} + +/** + * @brief Set CRC check_in data to register. + * @param handle Value of @ref CRC_Handle. + * @retval None. + */ +void HAL_CRC_SetCheckInData(CRC_Handle *handle, unsigned int data) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + handle->baseAddress->crc_calc_init_value = data; +} + +/** + * @brief Load CRC check_in register data to crc_out register. + * @param handle Value of @ref CRC_Handle. + * @retval unsigned int Reversed check_in data. + */ +unsigned int HAL_CRC_LoadCheckInData(CRC_Handle *handle) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + DCL_CRC_LoadInitValue(handle->baseAddress); + return DCL_CRC_GetInitValue(handle->baseAddress); +} + +/** + * @brief Register CRC interrupt callback. + * @param handle Value of @ref CRC_handle. + * @param callBackFunc Value of @ref CRC_CallbackType. + * @retval None + */ +void HAL_CRC_RegisterCallback(CRC_Handle *handle, CRC_CallbackType callBackFunc) +{ + BASE_FUNC_UNUSED(handle); + BASE_FUNC_UNUSED(callBackFunc); +} + +/** + * @brief Interrupt handler processing function. + * @param handle CRC_Handle. + * @retval None. + */ +void HAL_CRC_IrqHandler(void *handle) +{ + BASE_FUNC_UNUSED(handle); + return; +} + +/** + * @brief Set CRC init value by algorithmMode. + * @param handle Value of @ref CRC_Handle. + * @param algorithmMode value of CRC algorithm. + * @retval None. + */ +static void CRC_SetInitValueByAlgorithm(CRC_Handle *handle, CRC_AlgorithmMode algorithmMode) +{ + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + /* 0x000000FF : MASK of initValueType in crc algorithm */ + unsigned int initValueType = (algorithmMode & TYPE_INIT_MASK); + CRC_SetInitValue(handle, initValueType); + DCL_CRC_LoadInitValue(handle->baseAddress); +} + + +/** + * @brief Set CRC xor value by algorithmMode. + * @param handle Value of @ref CRC_Handle. + * @param algorithmMode value of CRC algorithm. + * @retval None. + */ +static void CRC_SetXorValueByAlgorithm(CRC_Handle *handle, CRC_AlgorithmMode algorithmMode) +{ + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + unsigned int xorValueType = (algorithmMode & TYPE_XOR_VALUE_MASK); + if (handle->baseAddress->CRC_POST_CFG.BIT.crc_post_xor_enable == BASE_CFG_ENABLE) { + /* Setting result xor value */ + CRC_SetResultXorValue(handle, xorValueType); + } +} + +/** + * @brief Set CRC xor endian reverse enable type by algorithmMode. + * @param handle Value of @ref CRC_Handle. + * @param algorithmMode value of CRC algorithm. + * @retval None. + */ +static void CRC_SetXorEndianReverseEnableByAlgorithm(CRC_Handle *handle, CRC_AlgorithmMode algorithmMode) +{ + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + /* 0x000000FF : MASK of initValueType in crc algorithm */ + unsigned int xorEndianEnableType = (algorithmMode & TYPE_XOR_ENDIAN_ENABLE_MASK); + unsigned int reverseEnableType = (algorithmMode & TYPE_REVERSE_ENABLE_MASK); + if ((IsCrcXorEndianEnableType(xorEndianEnableType))) { + /* config register */ + DCL_CRC_SetEndianMode(handle->baseAddress, + ((xorEndianEnableType & TYPE_ENDIAN_MSB_BIT) == TYPE_ENDIAN_MSB_BIT)); + DCL_CRC_SetXorResultMode(handle->baseAddress, + ((xorEndianEnableType & TYPE_XOR_ENABLE_BIT) == TYPE_XOR_ENABLE_BIT)); + } + if (IsCrcReverseEnableType(reverseEnableType)) { + /* config register */ + DCL_CRC_SetByteReverseMode(handle->baseAddress, + ((reverseEnableType & TYPE_BYTE_REVERSE_ENABLE_BIT) == TYPE_BYTE_REVERSE_ENABLE_BIT)); + DCL_CRC_SetOutputReverseMode(handle->baseAddress, + ((reverseEnableType & TYPE_OUTPUT_REVERSE_ENABLE_BIT) == TYPE_OUTPUT_REVERSE_ENABLE_BIT)); + } +} + +/** + * @brief Set CRC Polynomial Mode by algorithmMode. + * @param handle Value of @ref CRC_Handle. + * @param algorithmMode value of CRC algorithm. + * @retval None. + */ +static void CRC_SetPolynomialModeByAlgorithm(CRC_Handle *handle, CRC_AlgorithmMode algorithmMode) +{ + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + unsigned int polynomialMode = (algorithmMode & TYPE_POLY_MASK); + if (IsCrcPolynomial(polynomialMode)) { + DCL_CRC_SetPolynomialMode(handle->baseAddress, polynomialMode); + } +} + +/** + * @brief Set CRC xor value mode. + * @param handle Value of @ref CRC_Handle. + * @param type Value of @ref CRC_ResultXorValueType + * @retval None. + */ +static void CRC_SetResultXorValue(CRC_Handle *handle, CRC_ResultXorValueType type) +{ + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + CRC_PARAM_CHECK_NO_RET(IsCrcResultXorValueType(type)); + switch (type) { + case TYPE_CRC_XOR_VALUE_00: /* xor value tyep 00 */ + *(unsigned char *)(void *)(&handle->baseAddress->crc_post_xor_value) = CRC_XOR_VALUE_00; + break; + case TYPE_CRC_XOR_VALUE_55: + *(unsigned char *)(void *)(&handle->baseAddress->crc_post_xor_value) = CRC_XOR_VALUE_55; + break; + case TYPE_CRC_XOR_VALUE_0000: /* xor value type 0000 */ + *(unsigned short *)(void *)(&handle->baseAddress->crc_post_xor_value) = CRC_XOR_VALUE_0000; + break; + case TYPE_CRC_XOR_VALUE_FFFF: + *(unsigned short *)(void *)(&handle->baseAddress->crc_post_xor_value) = CRC_XOR_VALUE_FFFF; + break; + case TYPE_CRC_XOR_VALUE_00000000: /* xor value type 00000000 */ + *(unsigned int *)(void *)(&handle->baseAddress->crc_post_xor_value) = CRC_XOR_VALUE_00000000; + break; + case TYPE_CRC_XOR_VALUE_FFFFFFFF: /* xor value type FFFFFFFF */ + *(unsigned int *)(void *)(&handle->baseAddress->crc_post_xor_value) = CRC_XOR_VALUE_FFFFFFFF; + break; + default: + break; + } +} + +/** + * @brief Set CRC init value. + * @param handle Value of @ref CRC_Handle. + * @param type Value of @ref CRC_InitValueType. + * @retval None. + */ +static void CRC_SetInitValue(CRC_Handle *handle, CRC_InitValueType type) +{ + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + CRC_PARAM_CHECK_NO_RET(IsCrcInitValueType(type)); + switch (type) { + case TYPE_CRC_INIT_VALUE_00: /* init value type 00 */ + *(unsigned char *)(void *)(&handle->baseAddress->crc_calc_init_value) = CRC_INIT_VALUE_00; + break; + case TYPE_CRC_INIT_VALUE_FF: /* init value type FF */ + *(unsigned char *)(void *)(&handle->baseAddress->crc_calc_init_value) = CRC_INIT_VALUE_FF; + break; + case TYPE_CRC_INIT_VALUE_0000: /* init value type 0000 */ + *(unsigned short *)(void *)(&handle->baseAddress->crc_calc_init_value) = CRC_INIT_VALUE_0000; + break; + case TYPE_CRC_INIT_VALUE_FFFF: /* init value type FFFF */ + *(unsigned short *)(void *)(&handle->baseAddress->crc_calc_init_value) = CRC_INIT_VALUE_FFFF; + break; + case TYPE_CRC_INIT_VALUE_FFFFFFFF: /* init value type FFFFFFFF */ + *(unsigned int *)(void *)(&handle->baseAddress->crc_calc_init_value) = CRC_INIT_VALUE_FFFFFFFF; + break; + default: + break; + } +} diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/crg/common/inc/crg.h b/vendor/xinlingyu_92_3061M/Project/drivers/crg/common/inc/crg.h new file mode 100644 index 0000000000000000000000000000000000000000..ed10ef58869e5d68ad31c9f4e4fd6d238715a281 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/crg/common/inc/crg.h @@ -0,0 +1,123 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file crg.h + * @author MCU Driver Team + * @brief CRG module driver + * @details This file provides firmware CRG Handle Structure and functions + * prototypes to manage the following functionalities of the CRG. + * + Config CRG + * + Config IP Clock + * + Get the Config of CRG + * + Get the frequency of cpu and IP + */ +#ifndef McuMagicTag_CRG_H +#define McuMagicTag_CRG_H + +/* Includes ------------------------------------------------------------------*/ +#include "crg_ip.h" + +/* Macro definitions ---------------------------------------------------------*/ + +/** + * @defgroup CRG CRG + * @brief CRG module. + * @{ + */ + +/** + * @defgroup CRG_Common CRG Common + * @brief CRG common external module. + * @{ + */ + +/** + * @defgroup CRG_Handle_Definition CRG Handle Definition + * @{ + */ +/** + * @brief Typedef callback function of CRG + */ +typedef void (*CRG_CallBackFunc)(void *param); + +/** + * @brief CRG Handle, include clock config and ip clock ip config + */ +typedef struct { + CRG_RegStruct *baseAddress; /**< Base address of CLOCK register */ + CRG_PllRefClkSelect pllRefClkSelect; /**< PLL Refer clock selection */ + CRG_PllPreDiv pllPreDiv; /**< PLL pre division */ + unsigned int pllFbDiv; /**< PLL loop divider ratio */ + CRG_PllPostDiv pllPostDiv; /**< PLL post ratio */ + bool pllPd; /**< Pll Power down or not */ + CRG_CoreClkSelect coreClkSelect; /**< Core clock selection */ + CRG_ExtendHandle handleEx; /**< CRG handle extra */ +} CRG_Handle; +/** + * @} + */ + +/** + * @defgroup CRG_API_Declaration CRG HAL API + * @{ + */ +BASE_StatusType HAL_CRG_Init(const CRG_Handle *handle); + +BASE_StatusType HAL_CRG_DeInit(const CRG_Handle *handle); + +BASE_StatusType HAL_CRG_GetConfig(CRG_Handle *handle); + +BASE_StatusType HAL_CRG_SetCoreClockSelect(CRG_Handle *handle); + +BASE_StatusType HAL_CRG_InitWithTargetFrequence(const CRG_Handle *handle, unsigned int targetFreq); + +BASE_StatusType HAL_CRG_IpEnableSet(const void *baseAddress, unsigned int enable); + +BASE_StatusType HAL_CRG_IpEnableGet(const void *baseAddress, unsigned int *enable); + +BASE_StatusType HAL_CRG_IpClkSelectSet(const void *baseAddress, unsigned int select); + +BASE_StatusType HAL_CRG_IpClkSelectGet(const void *baseAddress, unsigned int *select); + +BASE_StatusType HAL_CRG_IpClkResetSet(const void *baseAddress, unsigned int reset); + +BASE_StatusType HAL_CRG_IpClkResetGet(const void *baseAddress, unsigned int *reset); + +BASE_StatusType HAL_CRG_IpClkDivSet(const void *baseAddress, unsigned int div); + +BASE_StatusType HAL_CRG_IpClkDivGet(const void *baseAddress, unsigned int *div); + +void HAL_CRG_PvdResetEnable(bool enable); + +unsigned int HAL_CRG_GetPllFreq(void); + +unsigned int HAL_CRG_GetCoreClkFreq(void); + +unsigned int HAL_CRG_GetIpFreq(const void *ipBaseAddr); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_CRG_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/crg/inc/crg_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/crg/inc/crg_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..3ee147c20c22ec13f36d00c7fa8935b46776824f --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/crg/inc/crg_ip.h @@ -0,0 +1,1730 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file crg_ip.h + * @author MCU Driver Team + * @brief TIMER module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the TIMER. + * + CRG register mapping structure + * + Direct Configuration Layer functions of CRG + */ +#ifndef McuMagicTag_CRG_IP_H +#define McuMagicTag_CRG_IP_H + +/* Includes ------------------------------------------------------------------*/ +#include "baseinc.h" + +/** + * @addtogroup CRG + * @{ + */ + +/** + * @defgroup CRG_IP CRG_IP + * @brief CRG_IP: crg_v1 + * @{ + */ + +/** + * @defgroup CRG_Param_Def CRG Parameters Definition + * @brief Definition of CRG configuration parameters. + * @{ + */ +#ifdef CRG_PARAM_CHECK +#define CRG_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define CRG_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define CRG_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define CRG_ASSERT_PARAM(para) ((void)0U) +#define CRG_PARAM_CHECK_NO_RET(para) ((void)0U) +#define CRG_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +#define IP_CLK_DISABLE 0x00000000U /**< IP Clock disable bitmask */ +#define IP_CLK_ENABLE 0x00000001U /**< IP Clock disable bitmask */ +#define HPM_CLK_ENABLE 0x00000001U /**< HPM Clock enable bitmask */ +#define HPM_1M_CLK_ENABLE 0x00000002U /**< HPM 1M Clock enable bitmask */ +#define IP_SYSCLK_ENABLE 0x00000002U /**< IP SysClock disable bitmask, Only valid for ADC */ + +#define DAC_DIV_BITLEN 4U /**< DIV bit length */ +#define DAC_DIV_MASK ((1 << DAC_DIV_BITLEN) - 1) /**< DAC div mask, base on the bit length */ + +#define ADC_DIV_FACTOR (1 << 1) /**< ADC div min factor */ +#define CRG_1MHZ_CLK_MAX_DIV 63 +#define CRG_FREQ_1MHz (1000 * 1000) +#define CRG_CLK_PFD_MIN_FREQ (4 * CRG_FREQ_1MHz) +#define CRG_CLK_PFD_MAX_FREQ (75 * CRG_FREQ_1MHz / 10) +#define CRG_CLK_VCO_MIN_FREQ (100 * CRG_FREQ_1MHz) +#define CRG_CLK_VCO_MAX_FREQ (300 * CRG_FREQ_1MHz) +#define CRG_CLK_TARGET_MAX_FREQ (150 * CRG_FREQ_1MHz) +#define CRG_CLK_PST2_MAX_FREQ (100 * CRG_FREQ_1MHz) +/** + * @brief PLL refer clock Select + */ +typedef enum { + CRG_PLL_REF_CLK_SELECT_HOSC = 0, + CRG_PLL_REF_CLK_SELECT_XTAL = 1, +} CRG_PllRefClkSelect; + +/** + * @brief PLL previous divsion value in register + */ +typedef enum { + CRG_PLL_PREDIV_1 = 0, + CRG_PLL_PREDIV_2 = 1, + CRG_PLL_PREDIV_3 = 2, + CRG_PLL_PREDIV_4 = 3, + CRG_PLL_PREDIV_5 = 4, + CRG_PLL_PREDIV_6 = 5, + CRG_PLL_PREDIV_7 = 6, + CRG_PLL_PREDIV_8 = 7, +} CRG_PllPreDiv; + +/** + * @brief PLL previous divison value in Calc frequency + */ +typedef enum { + PLL_PREDIV_OUT_1 = 1, + PLL_PREDIV_OUT_2 = 2, + PLL_PREDIV_OUT_3 = 3, + PLL_PREDIV_OUT_4 = 4, + PLL_PREDIV_OUT_5 = 5, + PLL_PREDIV_OUT_6 = 6, + PLL_PREDIV_OUT_7 = 7, + PLL_PREDIV_OUT_8 = 8, +} PLL_PreDivOut; + +/** + * @brief PLL post division 1 value in register + */ +typedef enum { + CRG_PLL_POSTDIV_1 = 0, + CRG_PLL_POSTDIV_2 = 1, + CRG_PLL_POSTDIV_3 = 2, + CRG_PLL_POSTDIV_4 = 3, + CRG_PLL_POSTDIV_5 = 4, + CRG_PLL_POSTDIV_6 = 5, + CRG_PLL_POSTDIV_7 = 6, + CRG_PLL_POSTDIV_8 = 7, +} CRG_PllPostDiv; + +/** + * @brief PLL post division 2 value in register + */ +typedef enum { + CRG_PLL_POSTDIV2_1 = 0, + CRG_PLL_POSTDIV2_2 = 1, + CRG_PLL_POSTDIV2_3 = 2, + CRG_PLL_POSTDIV2_4 = 3, + CRG_PLL_POSTDIV2_5 = 4, + CRG_PLL_POSTDIV2_6 = 5, + CRG_PLL_POSTDIV2_7 = 6, + CRG_PLL_POSTDIV2_8_MAX = 7, +} CRG_PllPostDiv2; + + +/** + * @brief Core clock selection + * @note default select HOSC + */ +typedef enum { + CRG_CORE_CLK_SELECT_HOSC = 0, + CRG_CORE_CLK_SELECT_TCXO = 1, + CRG_CORE_CLK_SELECT_PLL = 2, +} CRG_CoreClkSelect; + +/** + * @brief Core clock selection 2 + * @note default select HOSC + */ +typedef enum { + CRG_CORE_CLK2_SELECT_HOSC = 0, + CRG_CORE_CLK2_SELECT_TCXO = 1, + CRG_CORE_CLK2_SELECT_PLL = 2, +} CRG_CoreClkSelect2; + +/** + * @brief 1M clock selection + * @note default select HOSC + */ +typedef enum { + CRG_1M_CLK_SELECT_HOSC = 0, + CRG_1M_CLK_SELECT_TCXO = 1, +} CRG_1MClkSelect; + +/** + * @brief PLL frequency multiplication range + */ +typedef enum { + CRG_PLL_FBDIV_MIN = 6, + CRG_PLL_FBDIV_MAX = 127, +} CRG_PllFbDivRange; + +/** + * @brief PLL diagnose post div selection + */ +typedef enum { + CRG_PLL_DIG_POST_DIV_SELECT_FREF = 0, + CRG_PLL_DIG_POST_DIV_SELECT_PLL = 1, +} CRG_PllDigPostDivInSelect; + +/** + * @brief PLL diagnose loct detect lpsel + */ +typedef enum { + CRG_PLL_DIG_LOCKDET_LP_SELECT_2048 = 0, + CRG_PLL_DIG_LOCKDET_LP_SELECT_1024 = 1, + CRG_PLL_DIG_LOCKDET_LP_SELECT_512 = 2, + CRG_PLL_DIG_LOCKDET_LP_SELECT_256 = 3, +} CRG_PllDigLockDetLpSelect; + +/** + * @brief PLL Test selection + */ +typedef enum { + CRG_PLL_TEST_SELECT_FPFD = 0, + CRG_PLL_TEST_SELECT_CKFB = 1, + CRG_PLL_TEST_SELECT_LOCKDET_OUTPUT = 2, + CRG_PLL_TEST_SELECT_FOUTPOSTDIV_128 = 3, + CRG_PLL_TEST_SELECT_OUTPUT_0 = 4, +} CRG_PllDigTestSelect; + +/** + * @brief CRG Test Clock Select + */ +typedef enum { + CRG_TEST_CLK_PLL_PFD = 0x00000000U, + CRG_TEST_CLK_HOSC = 0x00000001U, + CRG_TEST_CLK_LOSC = 0x00000002U, + CRG_TEST_CLK_TCXO = 0x00000003U, + CRG_TEST_CLK_BG_CHOPPER = 0x00000004U, + CRG_TEST_CLK_ADC_DIV4 = 0x00000005U, + CRG_TEST_CLK_HCLK_DIV6 = 0x00000006U, + CRG_TEST_CLK_HOSC_DIV = 0x00000007U, +} CRG_TestClkSel; + +/** + * @brief ADC source clock select + */ +typedef enum { + CRG_ADC_CLK_ASYN_HOSC = 0, + CRG_ADC_CLK_ASYN_TCXO = 1, + CRG_ADC_CLK_ASYN_PLL_DIV = 2, + CRG_ADC_CLK_SYN_CORE = 3, +} CRG_AdcClkSelect; + +/** + * @brief ADC synchronous and asynchronous clock source selection + */ +typedef enum { + CRG_ADC_CLK_ASYNCHRONOUS = 0, + CRG_ADC_CLK_SYNCHRONOUS = 1, +} CRG_AdcClkModeSelect; + +/** + * @brief ADC Div set Value + */ +typedef enum { + CRG_ADC_DIV_1 = 0, + CRG_ADC_DIV_2 = 1, + CRG_ADC_DIV_3 = 2, + CRG_ADC_DIV_4 = 3, +} CRG_AdcDiv; + +/** + * @brief CRG Extra Handle, include CRG's other config + */ +typedef struct { + CRG_PllPostDiv2 pllPostDiv2; /**< PLL post 2 ratio */ + CRG_1MClkSelect clk1MSelect; /**< 1M clock selection */ + unsigned int clk1MDiv; /**< 1M clock ratio */ +} CRG_ExtendHandle; + +/** + * @brief PLL Divison Config + */ +typedef struct { + unsigned int PreDiv; + unsigned int fbDiv; + unsigned int postDiv; +} CRG_PllDivCfg; + +/** + * @brief APB_HS_SUBSYS IP config + */ +typedef union { + unsigned int value; + struct { + unsigned int clkEnMask : 16; + unsigned int softResetReq : 16; + } BIT; +} volatile CRG_IpWoClkSelectCfg; + +/** + * @brief ADC config + * @see PERI_CRG41_Reg and PERI_CRG42_Reg and PERI_CRG43_Reg + */ +typedef union { + unsigned int value[2]; + struct { + unsigned int eflash_cken : 1; + unsigned int reserved : 31; + unsigned int eflash_clk_tick_cksel : 1; + unsigned int reserved1 : 31; + } BIT; +} volatile CRG_EfcIpCfg; + +typedef union { + unsigned int value[2]; + struct { + unsigned int clk_adc_div0 : 2; + unsigned int reserved : 6; + unsigned int clk_adc_div1 : 2; + unsigned int reserved1 : 22; + unsigned int clk_adc_cken : 1; + unsigned int reserved2 : 15; + unsigned int adc_srst_req : 1; + unsigned int reserved3 : 7; + unsigned int cfg_adc_ckmode_sel : 1; + unsigned int reserved4 : 7; + } BIT; +} volatile CRG_AdcIpCfg; + +/** + * @brief DAC config + * @see PERI_CRG45_Reg + */ +typedef union { + unsigned int value; + struct { + unsigned int clkEnMask : 3; + unsigned int reserved_0 : 1; + unsigned int div : 12; + unsigned int softResetReq : 3; + unsigned int reserved_1 : 13; + } BIT; +} volatile CRG_DacIpCfg; + +/** + * @brief ANA config + * @see PERI_CRG664_Reg - PERI_CRG677_Reg + */ +typedef union { + unsigned int value; + struct { + unsigned int reserved : 16; + unsigned int ip_srst_req : 1; + unsigned int reserved1 : 15; + } BIT; +} volatile CRG_AnaIpCfg; + +/** + * @brief IP match info for ip process + */ +typedef struct { + void *baseAddr; /**< Base address of ip */ + unsigned int offset; /**< The offset in CRG_RegStruct */ + unsigned int idx; /**< index in Reg, for example: 0 -capm0_cken 1 - capm1_cken in PERI_CRG30_Reg */ +} CRG_IpMatchInfo; + +/** + * @} + */ + +/** + * @brief CRG REG0 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pll_ref_cksel : 1; /**< pll reference select */ + unsigned int reserved : 31; + } BIT; +} volatile PERI_CRG0_REG; + +/** + * @brief CRG REG1 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pll_prediv : 4; /**< predivider value */ + unsigned int reserved : 28; + } BIT; +} volatile PERI_CRG1_REG; + +/** + * @brief CRG REG2 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pll_fbdiv : 8; /**< feedback divider value */ + unsigned int reserved : 24; + } BIT; +} volatile PERI_CRG2_REG; + +/** + * @brief CRG REG3 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pll_postdiv1 : 4; /**< post divider value */ + unsigned int pll_postdiv2 : 4; + unsigned int reserved : 24; + } BIT; +} volatile PERI_CRG3_REG; + +/** + * @brief CRG REG4 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pll_pd : 1; /**< pll power down */ + unsigned int reserved : 31; + } BIT; +} volatile PERI_CRG4_REG; + +/** + * @brief CRG REG 7 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pll_lock : 1; /**< pll lock flag */ + unsigned int reserved : 31; + } BIT; +} volatile PERI_CRG7_REG; + +/** + * @brief CRG REG 8 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pll_lock_deglitch : 1; /**< pll out without deburring */ + unsigned int reserved : 31; + } BIT; +} volatile PERI_CRG8_REG; + +/** + * @brief CRG REG64 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int clk_pst1_sw_sel : 2; /**< hclk_sw_sel select */ + unsigned int reserved : 2; + unsigned int clk_pst2_sw_sel : 2; /**< clk_pst2_sw_sel select */ + unsigned int reserved1 : 2; + unsigned int reserved2 : 24; + } BIT; +} volatile PERI_CRG64_REG; + +/** + * @brief CRG REG65 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pvd_rst_enable : 1; /**< pvd reset enable */ + unsigned int reserved : 3; + unsigned int reserved1 : 28; + } BIT; +} volatile PERI_CRG65_REG; + +/** + * @brief CRG REG66 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int clk_1m_ini_cksel : 1; /**< clock 1M selection */ + unsigned int reserved : 3; + unsigned int reserved1 : 28; + } BIT; +} volatile PERI_CRG66_REG; + +/** + * @brief CRG REG registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int clk_1m_div : 6; /**< clock 1M divide */ + unsigned int reserved : 2; + unsigned int reserved1 : 24; + } BIT; +} volatile PERI_CRG67_REG; + +/** + * @brief CRG REG80 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int uart0_cken : 1; /**< uart0 clock enable */ + unsigned int reserved : 15; + unsigned int uart0_srst_req : 1; /**< uart0 reset request */ + unsigned int reserved1 : 15; + } BIT; +} volatile PERI_CRG80_REG; + +/** + * @brief CRG REG81 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int uart1_cken : 1; /**< uart1 clock enable */ + unsigned int reserved : 15; + unsigned int uart1_srst_req : 1; /**< uart1 reset request */ + unsigned int reserved1 : 15; + } BIT; +} volatile PERI_CRG81_REG; + +/** + * @brief CRG REG82 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int uart2_cken : 1; /**< uart2 clock enable */ + unsigned int reserved : 15; + unsigned int uart2_srst_req : 1; /**< uart2 reset request */ + unsigned int reserved1 : 15; + } BIT; +} volatile PERI_CRG82_REG; + +/** + * @brief CRG REG83 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int uart3_cken : 1; /**< uart3 clock enable */ + unsigned int reserved : 15; + unsigned int uart3_srst_req : 1; /**< uart3 reset request */ + unsigned int reserved1 : 15; + } BIT; +} volatile PERI_CRG83_REG; + +/** + * @brief CRG REG96 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int spi0_cken : 1; /**< spi0 clock enable */ + unsigned int reserved : 15; + unsigned int spi0_srst_req : 1; /**< spi0 reset request */ + unsigned int reserved1 : 15; + } BIT; +} volatile PERI_CRG96_REG; + +/** + * @brief CRG REG97 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int spi1_cken : 1; /**< spi1 clock enable */ + unsigned int reserved : 15; + unsigned int spi1_srst_req : 1; /**< spi1 reset request */ + unsigned int reserved1 : 15; + } BIT; +} volatile PERI_CRG97_REG; + +/** + * @brief CRG REG112 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int i2c0_cken : 1; /**< i2c0 clock enable */ + unsigned int reserved : 15; + unsigned int i2c0_srst_req : 1; /**< i2c0 reset request */ + unsigned int reserved1 : 15; + } BIT; +} volatile PERI_CRG112_REG; + +/** + * @brief CRG REG113 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int i2c1_cken : 1; /**< i2c1 clock enable */ + unsigned int reserved : 15; + unsigned int i2c1_srst_req : 1; /**< i2c1 reset request */ + unsigned int reserved1 : 15; + } BIT; +} volatile PERI_CRG113_REG; + +/** + * @brief CRG REG128 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int wwdg_cken : 1; /**< wwdg clock enable */ + unsigned int reserved : 15; + unsigned int wwdg_srst_req : 1; /**< wwdg reset request */ + unsigned int reserved1 : 15; + } BIT; +} volatile PERI_CRG128_REG; + +/** + * @brief CRG REG144 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int timer0_cken : 1; /**< timer0 clock enable */ + unsigned int reserved : 15; + unsigned int timer0_srst_req : 1; /**< timer0 reset request */ + unsigned int reserved1 : 15; + } BIT; +} volatile PERI_CRG144_REG; + +/** + * @brief CRG REG145 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int timer1_cken : 1; /**< timer1 clock enable */ + unsigned int reserved : 15; + unsigned int timer1_srst_req : 1; /**< timer1 reset request */ + unsigned int reserved1 : 15; + } BIT; +} volatile PERI_CRG145_REG; + +/** + * @brief CRG REG146 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int timer2_cken : 1; /**< timer2 clock enable */ + unsigned int reserved : 15; + unsigned int timer2_srst_req : 1; /**< timer2 reset request */ + unsigned int reserved1 : 15; + } BIT; +} volatile PERI_CRG146_REG; + +/** + * @brief CRG REG147 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int timer3_cken : 1; /**< timer3 clock enable */ + unsigned int reserved : 15; + unsigned int timer3_srst_req : 1; /**< timer3 reset request */ + unsigned int reserved1 : 15; + } BIT; +} volatile PERI_CRG147_REG; + +/** + * @brief CRG REG160 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int capm0_cken : 1; /**< capm0 clock enable */ + unsigned int reserved : 15; + unsigned int capm0_srst_req : 1; /**< capm1 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG160_REG; + +/** + * @brief CRG REG161 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int capm1_cken : 1; /**< capm1 clock enable */ + unsigned int reserved : 15; + unsigned int capm1_srst_req : 1; /**< capm1 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG161_REG; + +/** + * @brief CRG REG162 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int capm2_cken : 1; /**< capm2 clock enable */ + unsigned int reserved : 15; + unsigned int capm2_srst_req : 1; /**< capm2 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG162_REG; + +/** + * @brief CRG REG176 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int can_cken : 1; /**< can clock enable */ + unsigned int reserved : 15; + unsigned int can_srst_req : 1; /**< can reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG176_REG; + +/** + * @brief CRG REG192 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int dma_cken : 1; /**< dma clock enable */ + unsigned int reserved : 15; + unsigned int dma_srst_req : 1; /**< dma reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG192_REG; + +/** + * @brief CRG REG208 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cmm_cken : 1; /**< cmm clock enable */ + unsigned int reserved : 15; + unsigned int cmm_srst_req : 1; /**< cmm reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG208_REG; + +/** + * @brief CRG REG224 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int crc_cken : 1; /**< crc clock enable */ + unsigned int reserved : 15; + unsigned int crc_srst_req : 1; /**< crc reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG224_REG; + +/** + * @brief CRG REG240 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int iwdg_cken : 1; /**< iwdg clock enable */ + unsigned int reserved : 15; + unsigned int iwdg_srst_req : 1; /**< iwdg reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG240_REG; + +/** + * @brief CRG REG256 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int apt0_cken : 1; /**< apt0 clock enable */ + unsigned int reserved : 15; + unsigned int apt0_srst_req : 1; /**< apt0 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG256_REG; + +/** + * @brief CRG REG257 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int apt1_cken : 1; /**< apt1 clock enable */ + unsigned int reserved : 15; + unsigned int apt1_srst_req : 1; /**< apt1 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG257_REG; + +/** + * @brief CRG REG258 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int apt2_cken : 1; /**< apt2 clock enable */ + unsigned int reserved : 15; + unsigned int apt2_srst_req : 1; /**< apt2 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG258_REG; + +/** + * @brief CRG REG259 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int apt3_cken : 1; /**< apt3 clock enable */ + unsigned int reserved : 15; + unsigned int apt3_srst_req : 1; /**< apt3 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG259_REG; + +/** + * @brief CRG REG272 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int gpt0_cken : 1; /**< gpt0 clock enable */ + unsigned int reserved : 15; + unsigned int gpt0_srst_req : 1; /**< gpt0 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG272_REG; + +/** + * @brief CRG REG273 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int gpt1_cken : 1; /**< gpt1 clock enable */ + unsigned int reserved : 15; + unsigned int gpt1_srst_req : 1; /**< gpt1 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG273_REG; + +/** + * @brief CRG REG274 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int gpt2_cken : 1; /**< gpt2 clock enable */ + unsigned int reserved : 15; + unsigned int gpt2_srst_req : 1; /**< gpt2 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG274_REG; + +/** + * @brief CRG REG275 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int gpt3_cken : 1; /**< gpt3 clock enable */ + unsigned int reserved : 15; + unsigned int gpt3_srst_req : 1; /**< gpt3 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG275_REG; + +/** + * @brief CRG REG288 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int gpio0_cken : 1; /**< gpio0 clock enable */ + unsigned int reserved : 15; + unsigned int gpio0_srst_req : 1; /**< gpio0 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG288_REG; + +/** + * @brief CRG REG289 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int gpio1_cken : 1; /**< gpio1 clock enable */ + unsigned int reserved : 15; + unsigned int gpio1_srst_req : 1; /**< gpio1 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG289_REG; + +/** + * @brief CRG REG290 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int gpio2_cken : 1; /**< gpio2 clock enable */ + unsigned int reserved : 15; + unsigned int gpio2_srst_req : 1; /**< gpio2 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG290_REG; + +/** + * @brief CRG REG291 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int gpio3_cken : 1; /**< gpio3 clock enable */ + unsigned int reserved : 15; + unsigned int gpio3_srst_req : 1; /**< gpio3 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG291_REG; + +/** + * @brief CRG REG292 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int gpio4_cken : 1; /**< gpio4 clock enable */ + unsigned int reserved : 15; + unsigned int gpio4_srst_req : 1; /**< gpio4 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG292_REG; + +/** + * @brief CRG REG293 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int gpio5_cken : 1; /**< gpio5 clock enable */ + unsigned int reserved : 15; + unsigned int gpio5_srst_req : 1; /**< gpio5 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG293_REG; + +/** + * @brief CRG REG304 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int qdm0_cken : 1; /**< qdm0 clock enable */ + unsigned int reserved : 15; + unsigned int qdm0_srst_req : 1; /**< qdm0 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG304_REG; + +/** + * @brief CRG REG305 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int qdm1_cken : 1; /**< qdm1 clock enable */ + unsigned int reserved : 15; + unsigned int qdm1_srst_req : 1; /**< qdm1 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG305_REG; + +/** + * @brief CRG REG320 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int eflash_cken : 1; /**< eflash clock enable */ + unsigned int reserved : 15; + unsigned int reserved1 : 16; + } BIT; +} volatile PERI_CRG320_REG; + +/** + * @brief CRG REG639 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int test_clk_en : 1; /**< test clock enable */ + unsigned int reserved : 15; + unsigned int test_clk_sel : 3; /**< test clock select */ + unsigned int reserved1 : 13; + } BIT; +} volatile PERI_CRG639_REG; + +/** + * @brief CRG REG640 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int clk_adc_div0 : 2; /**< adc divide register 0 */ + unsigned int reserved : 6; + unsigned int clk_adc_div1 : 2; /**< adc divide register 1 */ + unsigned int reserved1 : 22; + } BIT; +} volatile PERI_CRG640_REG; + +/** + * @brief CRG REG641 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_cken : 1; /**< adc clock enable */ + unsigned int reserved : 15; + unsigned int adc_srst_req : 1; /**< adc reset request */ + unsigned int reserved1 : 7; + unsigned int adc_clk_mode : 1; /**< adc clock selection */ + unsigned int reserved2 : 7; + } BIT; +} volatile PERI_CRG641_REG; + +/** + * @brief CRG REG656 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int clk_bg_chopper_div : 6; /**< clk_bg_chopper divide factor */ + unsigned int reserved : 2; + unsigned int clk_bg_chopper_div_bypass : 1; /**< clk_bg_chopper divide bypass signal */ + unsigned int reserved1 : 23; + } BIT; +} volatile PERI_CRG656_REG; + +/** + * @brief CRG REG660 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int clk_ana_cken : 1; /**< anolog clock enable */ + unsigned int reserved : 15; + unsigned int ana_srst_req : 1; /**< anolog reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG660_REG; + +/** + * @brief CRG REG664 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved : 16; + unsigned int vref_srst_req : 1; /**< VREF reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG664_REG; + +/** + * @brief CRG REG668 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved : 16; + unsigned int acmp_srst_req : 1; /**< acmp reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG668_REG; + +/** + * @brief CRG REG672 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved : 16; + unsigned int dac_srst_req : 1; /**< dac reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG672_REG; + +/** + * @brief CRG REG676 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved : 16; + unsigned int pga0_srst_req : 1; /**< pga0 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG676_REG; + +/** + * @brief CRG REG677 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved : 16; + unsigned int pga1_srst_req : 1; /**< pga1 reset request */ + unsigned int reserved1 : 7; + unsigned int reserved2 : 8; + } BIT; +} volatile PERI_CRG677_REG; + + +/** + * @brief HOSC CTRL4 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int hosc_pd : 1; /**< HOSC power down enable bit */ + unsigned int reserved : 31; + } BIT; +} volatile HOSC_PD_REG; + +/** + * @brief HOSC CTRL5 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int hosc_lock : 1; /**< HOSC lock signal */ + unsigned int reserved : 31; + } BIT; +} volatile HOSC_LOCK_REG; + +typedef struct { + PERI_CRG0_REG PERI_CRG0; /**< CRG0 register. Offset address 0x00000000U. */ + PERI_CRG1_REG PERI_CRG1; /**< CRG1 register. Offset address 0x00000004U. */ + PERI_CRG2_REG PERI_CRG2; /**< CRG2 register. Offset address 0x00000008U. */ + PERI_CRG3_REG PERI_CRG3; /**< CRG3 register. Offset address 0x0000000CU. */ + PERI_CRG4_REG PERI_CRG4; /**< CRG4 register. Offset address 0x00000010U. */ + unsigned char reserved0[8]; + PERI_CRG7_REG PERI_CRG7; /**< CRG7 register. Offset address 0x0000001CU. */ + PERI_CRG8_REG PERI_CRG8; /**< CRG8 register. Offset address 0x00000020U. */ + unsigned char reserved1[0xdc]; + PERI_CRG64_REG PERI_CRG64; /**< CRG64 register. Offset address 0x00000100U. */ + PERI_CRG65_REG PERI_CRG65; /**< CRG65 register. Offset address 0x00000104U. */ + PERI_CRG66_REG PERI_CRG66; /**< CRG66 register. Offset address 0x00000108U. */ + PERI_CRG67_REG PERI_CRG67; /**< CRG67 register. Offset address 0x0000010CU. */ + unsigned char reserved2[0x30]; + PERI_CRG80_REG PERI_CRG80; /**< CRG80 register. Offset address 0x00000140U. */ + PERI_CRG81_REG PERI_CRG81; /**< CRG81 register. Offset address 0x00000144U. */ + PERI_CRG82_REG PERI_CRG82; /**< CRG82 register. Offset address 0x00000148U. */ + PERI_CRG83_REG PERI_CRG83; /**< CRG83 register. Offset address 0x0000014CU. */ + unsigned char reserved3[0x30]; + PERI_CRG96_REG PERI_CRG96; /**< CRG96 register. Offset address 0x00000180U. */ + PERI_CRG97_REG PERI_CRG97; /**< CRG97 register. Offset address 0x00000184U. */ + unsigned char reserved4[0x38]; + PERI_CRG112_REG PERI_CRG112; /**< CRG112 register. Offset address 0x000001C0U. */ + PERI_CRG113_REG PERI_CRG113; /**< CRG113 register. Offset address 0x000001C4U. */ + unsigned char reserved5[0x38]; + PERI_CRG128_REG PERI_CRG128; /**< CRG128 register. Offset address 0x00000200U. */ + unsigned char reserved6[0x3c]; + PERI_CRG144_REG PERI_CRG144; /**< CRG144 register. Offset address 0x00000240U. */ + PERI_CRG145_REG PERI_CRG145; /**< CRG145 register. Offset address 0x00000244U. */ + PERI_CRG146_REG PERI_CRG146; /**< CRG146 register. Offset address 0x00000248U. */ + PERI_CRG147_REG PERI_CRG147; /**< CRG147 register. Offset address 0x0000024CU. */ + unsigned char reserved7[0x30]; + PERI_CRG160_REG PERI_CRG160; /**< CRG160 register. Offset address 0x00000280U. */ + PERI_CRG161_REG PERI_CRG161; /**< CRG161 register. Offset address 0x00000284U. */ + PERI_CRG162_REG PERI_CRG162; /**< CRG162 register. Offset address 0x00000288U. */ + unsigned char reserved8[0x34]; + PERI_CRG176_REG PERI_CRG176; /**< CRG176 register. Offset address 0x000002C0U. */ + unsigned char reserved9[0x3c]; + PERI_CRG192_REG PERI_CRG192; /**< CRG192 register. Offset address 0x00000300U. */ + unsigned char reserved10[0x3c]; + PERI_CRG208_REG PERI_CRG208; /**< CRG208 register. Offset address 0x00000340U. */ + unsigned char reserved11[0x3c]; + PERI_CRG224_REG PERI_CRG224; /**< CRG224 register. Offset address 0x00000380U. */ + unsigned char reserved12[0x3c]; + PERI_CRG240_REG PERI_CRG240; /**< CRG240 register. Offset address 0x000003C0U. */ + unsigned char reserved13[0x3c]; + PERI_CRG256_REG PERI_CRG256; /**< CRG256 register. Offset address 0x00000400U. */ + PERI_CRG257_REG PERI_CRG257; /**< CRG257 register. Offset address 0x00000404U. */ + PERI_CRG258_REG PERI_CRG258; /**< CRG258 register. Offset address 0x00000408U. */ + PERI_CRG259_REG PERI_CRG259; /**< CRG259 register. Offset address 0x0000040CU. */ + unsigned char reserved14[0x30]; + PERI_CRG272_REG PERI_CRG272; /**< CRG272 register. Offset address 0x00000440U. */ + PERI_CRG273_REG PERI_CRG273; /**< CRG273 register. Offset address 0x00000444U. */ + PERI_CRG274_REG PERI_CRG274; /**< CRG274 register. Offset address 0x00000448U. */ + PERI_CRG275_REG PERI_CRG275; /**< CRG275 register. Offset address 0x0000044CU. */ + unsigned char reserved15[0x30]; + PERI_CRG288_REG PERI_CRG288; /**< CRG288 register. Offset address 0x00000480U. */ + PERI_CRG289_REG PERI_CRG289; /**< CRG289 register. Offset address 0x00000484U. */ + PERI_CRG290_REG PERI_CRG290; /**< CRG290 register. Offset address 0x00000488U. */ + PERI_CRG291_REG PERI_CRG291; /**< CRG291 register. Offset address 0x0000048cU. */ + PERI_CRG292_REG PERI_CRG292; /**< CRG292 register. Offset address 0x00000490U. */ + PERI_CRG293_REG PERI_CRG293; /**< CRG293 register. Offset address 0x00000494U. */ + unsigned char reserved16[0x28]; + PERI_CRG304_REG PERI_CRG304; /**< CRG304 register. Offset address 0x000004C0U. */ + PERI_CRG305_REG PERI_CRG305; /**< CRG305 register. Offset address 0x000004C4U. */ + unsigned char reserved17[0x38]; + PERI_CRG320_REG PERI_CRG320; /**< CRG320 register. Offset address 0x00000500U. */ + unsigned char reserved18[0x4f8]; + PERI_CRG639_REG PERI_CRG639; /**< CRG639 register. Offset address 0x000009FCU. */ + PERI_CRG640_REG PERI_CRG640; /**< CRG640 register. Offset address 0x00000A00U. */ + PERI_CRG641_REG PERI_CRG641; /**< CRG640 register. Offset address 0x00000A04U. */ + unsigned char reserved19[0x38]; + PERI_CRG656_REG PERI_CRG656; /**< CRG656 register. Offset address 0x00000A40U. */ + unsigned char reserved20[0xc]; + PERI_CRG660_REG PERI_CRG660; /**< CRG660 register. Offset address 0x00000A50U. */ + unsigned char reserved21[0xc]; + PERI_CRG664_REG PERI_CRG664; /**< CRG664 register. Offset address 0x00000A60U. */ + unsigned char reserved22[0xc]; + PERI_CRG668_REG PERI_CRG668; /**< CRG668 register. Offset address 0x00000A70U. */ + unsigned char reserved23[0xc]; + PERI_CRG672_REG PERI_CRG672; /**< CRG672 register. Offset address 0x00000A80U. */ + unsigned char reserved24[0xc]; + PERI_CRG676_REG PERI_CRG676; /**< CRG676 register. Offset address 0x00000A90U. */ + PERI_CRG677_REG PERI_CRG677; /**< CRG677 register. Offset address 0x00000A94U. */ + unsigned char reserved25[1140]; + HOSC_PD_REG HOSC_PD; /**< HOSC_PD register. Offset address 0x000000F0CU. */ + HOSC_LOCK_REG HOSC_LOCK; /**< HOSC_LOCK register. Offset address 0x000000F10U. */ +} volatile CRG_RegStruct; + +/** + * @} + */ + +/* Parameter Check -----------------------------------------------------------*/ +/** + * @brief Verify pll_ref_cksel configuration + * @param clkSelect pll_ref_cksel + * @retval true + * @retval false + */ +static inline bool IsCrgPllRefClkSelect(CRG_PllRefClkSelect clkSelect) +{ + return ((clkSelect == CRG_PLL_REF_CLK_SELECT_HOSC) || + (clkSelect == CRG_PLL_REF_CLK_SELECT_XTAL)); +} + +/** + * @brief Verify Crg pll_prediv configuration + * @param preDiv pll prediv value + * @retval true + * @retval false + */ +static inline bool IsCrgPllPreDiv(CRG_PllPreDiv preDiv) +{ + return ((preDiv >= CRG_PLL_PREDIV_1) && + (preDiv <= CRG_PLL_PREDIV_8)); +} + +/** + * @brief Verify Crg pll_postdiv configuration + * @param postDiv pll_postdiv value + * @retval true + * @retval false + */ +static inline bool IsCrgPllPostDiv(CRG_PllPostDiv postDiv) +{ + return ((postDiv >= CRG_PLL_POSTDIV_1) && + (postDiv <= CRG_PLL_POSTDIV_8)); +} + +/** + * @brief Verify Crg pll_postdiv2 configuration + * @param postDiv pll_postdiv2 value + * @retval true + * @retval false + */ +static inline bool IsCrgPllPostDiv2(CRG_PllPostDiv2 postDiv) +{ + return ((postDiv >= CRG_PLL_POSTDIV2_1) && + (postDiv <= CRG_PLL_POSTDIV2_8_MAX)); +} + +/** + * @brief Verify Crg pll_fbdiv configuration + * @param fbDiv pll fbdiv value + * @retval true + * @retval false + */ +static inline bool IsCrgPllFbDiv(unsigned int fbDiv) +{ + return (fbDiv <= CRG_PLL_FBDIV_MAX); +} + +/** + * @brief Verify Crg pll_digpostdiv_in_sel configuration + * @param select pll_digpostdiv_in_sel value + * @retval true + * @retval false + */ +static inline bool IsCrgPllDigPostDivInSel(CRG_PllDigPostDivInSelect select) +{ + return ((select == CRG_PLL_DIG_POST_DIV_SELECT_FREF) || + (select == CRG_PLL_DIG_POST_DIV_SELECT_PLL)); +} + +/** + * @brief Verify Crg core_cksel configuration + * @param select core_cksel value + * @retval true + * @retval false + */ +static inline bool IsCrgCoreCkSel(CRG_CoreClkSelect select) +{ + return ((select == CRG_CORE_CLK_SELECT_HOSC) || + (select == CRG_CORE_CLK_SELECT_TCXO) || + (select == CRG_CORE_CLK_SELECT_PLL)); +} + +/** + * @brief Verify Crg configuration + * @param select 1M clock selection + * @retval true + * @retval false + */ +static inline bool IsCrg1MCkSel(CRG_1MClkSelect select) +{ + return ((select == CRG_1M_CLK_SELECT_HOSC) || + (select == CRG_1M_CLK_SELECT_TCXO)); +} + +/** + * @brief Verify Crg configuration + * @param div 1M clock ratio + * @retval true + * @retval false + */ +static inline bool IsCrg1MCkDiv(unsigned int div) +{ + return (div <= CRG_1MHZ_CLK_MAX_DIV); +} + +/** + * @brief Verify Crg Ip (exclude adc) clock enable configuration + * @param enable ip clock enable value + * @retval true + * @retval false + */ +static inline bool IsCrgIpClkEnable(unsigned int enable) +{ + return ((enable == IP_CLK_DISABLE) || + (enable == IP_CLK_ENABLE)); +} + +/** + * @brief Check the PLL PreDiv is valid or not + * @param clkPllRef PLL Refer clock + * @param preDiv PLL Previous Divsion + * @retval true + * @retval false + */ +static inline bool IsCrgValidPreDiv(unsigned int pllRefFreq, unsigned int preDiv) +{ + unsigned int freq = pllRefFreq; + if (preDiv != 0) { + freq /= preDiv; + } + return (freq >= CRG_CLK_PFD_MIN_FREQ) && (freq <= CRG_CLK_PFD_MAX_FREQ); +} + +/** + * @brief Check the PLL FbDiv is valid or not + * @param clkPfdFreq PLL PFD clock + * @param fdDiv PLL FD Divsion + * @retval true + * @retval false + */ +static inline bool IsCrgValidFdDiv(unsigned int clkPfdFreq, unsigned int fdDiv) +{ + if (clkPfdFreq > 30000000U) { /* The maximum speed of the external clock source is 30000000U. */ + return false; + } else if (fdDiv > CRG_PLL_FBDIV_MAX) { + return false; + } + + unsigned int freq = (fdDiv > 0x6) ? (clkPfdFreq * fdDiv) : (clkPfdFreq * 0x6); /* 0x0-0x6: divided by 0x6 */ + return (freq >= CRG_CLK_VCO_MIN_FREQ) && (freq <= CRG_CLK_VCO_MAX_FREQ); +} + +/** + * @brief Check the PLL PostDiv is valid or not + * @param clkPllRef PLL Vco clock + * @param postDiv PLL Post Divsion + * @retval true + * @retval false + */ +static inline bool IsCrgValidPostDiv(unsigned int clkVcoFreq, unsigned int postDiv) +{ + unsigned int freq = clkVcoFreq; + if (postDiv != 0) { + freq /= (postDiv + 1); + } + return (freq <= CRG_CLK_TARGET_MAX_FREQ); +} + +/** + * @brief Check the PLL PostDiv is valid or not + * @param clkPllRef PLL Vco clock + * @param postDiv2 PLL Post Divsion2 + * @retval true + * @retval false + */ +static inline bool IsCrgValidPostDiv2(unsigned int clkVcoFreq, unsigned int postDiv2) +{ + unsigned int freq = clkVcoFreq; + if (postDiv2 != 0) { + freq /= (postDiv2 + 1); + } + return (freq <= CRG_CLK_PST2_MAX_FREQ); +} + +/** + * @brief Check the adc clock select value + * @param adcClkSelect the value of adc clock select + * @retval true + * @retval false + */ +static inline bool IsCrgAdcClkModeSelect(CRG_AdcClkSelect adcClkSelect) +{ + return (adcClkSelect == CRG_ADC_CLK_ASYN_HOSC || \ + adcClkSelect == CRG_ADC_CLK_ASYN_TCXO || \ + adcClkSelect == CRG_ADC_CLK_ASYN_PLL_DIV || \ + adcClkSelect == CRG_ADC_CLK_SYN_CORE); +} + +/** + * @brief Check the adc clock div value + * @param div the value of adc clock div + * @retval true + * @retval false + */ +static inline bool IsCrgAdcClkDiv(CRG_AdcDiv div) +{ + return (div == CRG_ADC_DIV_1 || \ + div == CRG_ADC_DIV_2 || \ + div == CRG_ADC_DIV_3 || \ + div == CRG_ADC_DIV_4); +} + +/** + * @brief Set Pll Ref clock select + * @param clk Clock register base address + * @param clkSel clock source select + * @retval None + */ +static inline void DCL_CRG_SetPllRefClkSel(CRG_RegStruct *clk, CRG_PllRefClkSelect clkSel) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + CRG_PARAM_CHECK_NO_RET(IsCrgPllRefClkSelect(clkSel)); + clk->PERI_CRG0.BIT.pll_ref_cksel = (unsigned int)clkSel; +} + +/** + * @brief Get Pll Ref clock selection + * @param clk Clock register base address + * @retval pll_ref_cksel Ref clock selection + */ +static inline CRG_PllRefClkSelect DCL_CRG_GetPllRefClkSel(const CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + return (CRG_PllRefClkSelect)clk->PERI_CRG0.BIT.pll_ref_cksel; +} + +/** + * @brief Set prevous division ratio + * @param clk Clock register base address + * @param preDiv prevous division ratio + * @retval None + */ +static inline void DCL_CRG_SetPllPreDiv(CRG_RegStruct *clk, CRG_PllPreDiv preDiv) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + CRG_PARAM_CHECK_NO_RET(IsCrgPllPreDiv(preDiv)); + clk->PERI_CRG1.BIT.pll_prediv = (unsigned int)preDiv; +} + +/** + * @brief Get prevous division ratio + * @param clk Clock register base address + * @retval prediv prevous division ratio + */ +static inline CRG_PllPreDiv DCL_CRG_GetPllPreDiv(const CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + return (CRG_PllPreDiv)clk->PERI_CRG1.BIT.pll_prediv; +} + +/** + * @brief Set PLL frequency multiplication factor + * @param clk Clock register base address + * @param fbDiv Multiplication factor + * @retval None + */ +static inline void DCL_CRG_SetPllFbDiv(CRG_RegStruct *clk, unsigned int fbDiv) +{ + unsigned int div = fbDiv; + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + CRG_PARAM_CHECK_NO_RET(IsCrgPllFbDiv(fbDiv)); + clk->PERI_CRG2.BIT.pll_fbdiv = div; +} + +/** + * @brief Get PLL frequency multiplication factor + * @param clk Clock register base address + * @retval pll_fbdiv Multiplication factor + */ +static inline unsigned int DCL_CRG_GetPllFbDiv(const CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + return clk->PERI_CRG2.BIT.pll_fbdiv; +} + +/** + * @brief Set PLL post division ratio + * @param clk Clock register base address + * @param postDiv Post division ratio + * @retval None + */ +static inline void DCL_CRG_SetPllPostDiv1(CRG_RegStruct *clk, CRG_PllPostDiv postDiv) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + CRG_PARAM_CHECK_NO_RET(IsCrgPllPostDiv(postDiv)); + clk->PERI_CRG3.BIT.pll_postdiv1 = (unsigned int)postDiv; +} + +/** + * @brief Get PLL post division ratio + * @param clk Clock register base address + * @retval pll_postdiv Post division ratio + */ +static inline CRG_PllPostDiv DCL_CRG_GetPllPostDiv1(const CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + return (CRG_PllPostDiv)clk->PERI_CRG3.BIT.pll_postdiv1; +} + +/** + * @brief Set PLL post division ratio + * @param clk Clock register base address + * @param postDiv Post division ratio + * @retval None + */ +static inline void DCL_CRG_SetPllPostDiv2(CRG_RegStruct *clk, CRG_PllPostDiv postDiv) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + CRG_PARAM_CHECK_NO_RET(IsCrgPllPostDiv(postDiv)); + clk->PERI_CRG3.BIT.pll_postdiv2 = (unsigned int)postDiv; +} + +/** + * @brief Get PLL post division ratio + * @param clk Clock register base address + * @retval pll_postdiv Post division ratio + */ +static inline CRG_PllPostDiv DCL_CRG_GetPllPostDiv2(const CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + return (CRG_PllPostDiv)clk->PERI_CRG3.BIT.pll_postdiv2; +} + +/** + * @brief Set PLL Power + * @param clk Clock register base address + * @param pd pll power down or not + * @retval None + */ +static inline void DCL_CRG_SetPllPd(CRG_RegStruct *clk, bool pd) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + clk->PERI_CRG4.BIT.pll_pd = (unsigned int)pd; +} + +/** + * @brief Get PLL power status + * @param clk Clock register base address + * @retval 0: power up, 1: power down + */ +static inline bool DCL_CRG_GetPllPd(const CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + return clk->PERI_CRG4.BIT.pll_pd; +} + +/** + * @brief Set core clock selection + * @param clk Clock register base address + * @param select Core clock selection + * @retval None + */ +static inline void DCL_CRG_SetCoreClkSel(CRG_RegStruct *clk, CRG_CoreClkSelect select) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + CRG_PARAM_CHECK_NO_RET(IsCrgCoreCkSel(select)); + clk->PERI_CRG64.BIT.clk_pst1_sw_sel = select; +} + +/** + * @brief Get core clock selection + * @param clk Clock register base address + * @retval Core clock selection + */ +static inline unsigned int DCL_CRG_GetCoreClkSel(const CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + return clk->PERI_CRG64.BIT.clk_pst1_sw_sel; +} + +/** + * @brief Set core clock selection + * @param clk Clock register base address + * @param select Core clock selection + * @retval None + */ +static inline void DCL_CRG_SetAdcAsynClkSel(CRG_RegStruct *clk, CRG_CoreClkSelect select) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + CRG_PARAM_CHECK_NO_RET(IsCrgCoreCkSel(select)); + clk->PERI_CRG64.BIT.clk_pst2_sw_sel = select; +} + +/** + * @brief Get adc core clock selection + * @param clk Clock register base address + * @retval Core clock selection + */ +static inline unsigned int DCL_CRG_GetAdcAsynClkSel(const CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + return clk->PERI_CRG64.BIT.clk_pst2_sw_sel; +} + +/** + * @brief Set 1M clock selection + * @param clk Clock register base address + * @param select Core clock selection + * @retval None + */ +static inline void DCL_CRG_Set1MClkSel(CRG_RegStruct *clk, CRG_1MClkSelect select) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + CRG_PARAM_CHECK_NO_RET(IsCrg1MCkSel(select)); + clk->PERI_CRG66.BIT.clk_1m_ini_cksel = select; +} + +/** + * @brief Get 1M clock selection + * @param clk Clock register base address + * @retval Core clock selection + */ +static inline unsigned int DCL_CRG_Get1MClkSel(const CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + return clk->PERI_CRG66.BIT.clk_1m_ini_cksel; +} + +/** + * @brief Set 1M clock division ratio + * @param clk Clock register base address + * @param div Division ratio + * @retval None + */ +static inline void DCL_CRG_Set1MClkDiv(CRG_RegStruct *clk, unsigned int div) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + CRG_PARAM_CHECK_NO_RET(div <= CRG_1MHZ_CLK_MAX_DIV); + clk->PERI_CRG67.BIT.clk_1m_div = div; +} + +/** + * @brief Enable test clock function + * @param clk Clock register base address + * @retval None + */ +static inline void DCL_CRG_TestClkEnable(CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + clk->PERI_CRG639.BIT.test_clk_en = BASE_CFG_ENABLE; /* Enable the test clock. */ +} + +/** + * @brief Disable test clock function + * @param clk Clock register base address + * @retval None + */ +static inline void DCL_CRG_TestClkDisable(CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + clk->PERI_CRG639.BIT.test_clk_en = BASE_CFG_DISABLE; /* Disable the test clock. */ +} + +/** + * @brief CRG test clock select. + * @param clk Clock register base address + * @param clkSel Clock select. + * @retval None + */ +static inline void DCL_CRG_TestClkSel(CRG_RegStruct *clk, CRG_TestClkSel clkSel) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + CRG_PARAM_CHECK_NO_RET(clkSel >= CRG_TEST_CLK_PLL_PFD); + CRG_PARAM_CHECK_NO_RET(clkSel <= CRG_TEST_CLK_HOSC_DIV); + clk->PERI_CRG639.BIT.test_clk_sel = clkSel; /* Set the test clock select. */ +} +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_CRG_IP_H */ diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/crg/src/crg.c b/vendor/xinlingyu_92_3061M/Project/drivers/crg/src/crg.c new file mode 100644 index 0000000000000000000000000000000000000000..9dd7c7af8581a282c3f21ee08b4168d57e62a66d --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/crg/src/crg.c @@ -0,0 +1,1130 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file crg.c + * @author MCU Driver Team + * @brief CRG module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the CRG. + * + Initialization and de-initialization functions + * + Config the register of CRG + * + Config the register of IP,such as Uart,Timer and so on + */ + +/* Includes ------------------------------------------------------------------*/ +#include "crg.h" +/* Macro definitions ---------------------------------------------------------*/ +#define CRG_HOSC_CTRL2_ADDR 0x10000F04 +/* Private Function -----------------------------------------------------------*/ +static unsigned int CRG_GetPllRefIni(CRG_PllRefClkSelect pllRefClkSelect); +static unsigned int CRG_GetPreDivValue(CRG_PllPreDiv pllPredDiv); +static unsigned int CRG_GetPllFbDivValue(unsigned int pllFbDiv); +static unsigned int CRG_GetPllPostDivValue(unsigned int pllPostDiv); +static inline unsigned int CRG_GetVcoFreq(void); +static BASE_StatusType CRG_IsValidPllConfig(const CRG_Handle *handle); +static void CRG_GetPllOptConfig(unsigned int targetFreq, unsigned int pllRefFreq, CRG_PllDivCfg *div); +static BASE_StatusType CRG_IsValid1MHzConfig(const CRG_Handle *handle); + +static void CRG_IpWoClkSelEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable); +static void CRG_IpWoClkSelResetSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int reset); +static unsigned int CRG_IpWoClkSelEnableGet(const CHIP_CrgIpMatchInfo *matchInfo); +static unsigned int CRG_IpWoClkSelResetGet(const CHIP_CrgIpMatchInfo *matchInfo); + +static void CRG_AdcEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable); +static void CRG_AdcDivSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int div); +static void CRG_AdcClkSelectSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int clkSelect); +static unsigned int CRG_AdcEnableGet(const CHIP_CrgIpMatchInfo *matchInfo); +static unsigned int CRG_AdcClkSelectGet(const CHIP_CrgIpMatchInfo *matchInfo); +static unsigned int CRG_AdcDivGet(const CHIP_CrgIpMatchInfo *matchInfo); + +static void CRG_EfcEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable); +static unsigned int CRG_EfcEnableGet(const CHIP_CrgIpMatchInfo *matchInfo); +static void CRG_AnaEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable); +static unsigned int CRG_AnaEnableGet(const CHIP_CrgIpMatchInfo *matchInfo); + +#ifndef FPGA +static unsigned int CRG_GetAdcIpFreq(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int baseClkRate, + unsigned int coreClkFreq); +#endif + +typedef CHIP_CrgIpMatchInfo *(*FindFunc)(const void *baseAddress); +typedef void (*SetFunc)(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int value); +typedef unsigned int (*GetFunc)(const CHIP_CrgIpMatchInfo *matchInfo); + +typedef struct { + CHIP_CrgIpType type; + SetFunc resetSet; + SetFunc enableSet; + SetFunc clkSelSet; + SetFunc clkDivSet; + GetFunc resetGet; + GetFunc enableGet; + GetFunc clkSelGet; + GetFunc clkDivGet; +} CRG_IpProc; + +static CRG_IpProc g_ipClkProc[CRG_IP_MAX_TYPE] = { + {CRG_IP_NONE_CLK_SEL, + CRG_IpWoClkSelResetSet, CRG_IpWoClkSelEnableSet, NULL, NULL, + CRG_IpWoClkSelResetGet, CRG_IpWoClkSelEnableGet, NULL, NULL}, + {CRG_IP_CAN, + CRG_IpWoClkSelResetSet, CRG_IpWoClkSelEnableSet, NULL, NULL, + CRG_IpWoClkSelResetGet, CRG_IpWoClkSelEnableGet, NULL, NULL}, + {CRG_IP_ADC, + NULL, CRG_AdcEnableSet, CRG_AdcClkSelectSet, CRG_AdcDivSet, + NULL, CRG_AdcEnableGet, CRG_AdcClkSelectGet, CRG_AdcDivGet}, + {CRG_IP_EFC, + NULL, CRG_EfcEnableSet, NULL, NULL, + NULL, CRG_EfcEnableGet, NULL, NULL}, + {CRG_IP_IWDG, + CRG_IpWoClkSelResetSet, CRG_IpWoClkSelEnableSet, NULL, NULL, + CRG_IpWoClkSelResetGet, CRG_IpWoClkSelEnableGet, NULL, NULL}, + {CRG_IP_ANA, + CRG_IpWoClkSelResetSet, CRG_AnaEnableSet, NULL, NULL, + CRG_IpWoClkSelResetGet, CRG_AnaEnableGet, NULL, NULL} +}; + +static CRG_RegStruct *g_crgBaseAddr; +static unsigned char g_anaEnableFlag = 0; + +/* Public Function -----------------------------------------------------------*/ +/** + * @brief Clock Init + * @param handle CRG Handle + * @retval BASE_STATUS_ERROR Parameter Check fail + * @retval BASE_STATUS_OK Success + */ +BASE_StatusType HAL_CRG_Init(const CRG_Handle *handle) +{ + CRG_ASSERT_PARAM(handle != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(handle->baseAddress)); + /* Check the validity of PLL-related parameters. */ + CRG_PARAM_CHECK_WITH_RET(IsCrgPllRefClkSelect(handle->pllRefClkSelect), BASE_STATUS_ERROR); + CRG_PARAM_CHECK_WITH_RET(IsCrgPllPreDiv(handle->pllPreDiv), BASE_STATUS_ERROR); + CRG_PARAM_CHECK_WITH_RET(IsCrgPllFbDiv(handle->pllFbDiv), BASE_STATUS_ERROR); + CRG_PARAM_CHECK_WITH_RET(IsCrgPllPostDiv(handle->pllPostDiv), BASE_STATUS_ERROR); + CRG_PARAM_CHECK_WITH_RET(IsCrgPllPostDiv2(handle->handleEx.pllPostDiv2), BASE_STATUS_ERROR); + /* Check the Clock Source and Frequency Divider of the 1 MHz Clock. */ + CRG_PARAM_CHECK_WITH_RET(IsCrg1MCkSel(handle->handleEx.clk1MSelect), BASE_STATUS_ERROR); + CRG_PARAM_CHECK_WITH_RET(IsCrg1MCkDiv(handle->handleEx.clk1MDiv), BASE_STATUS_ERROR); + CRG_PARAM_CHECK_WITH_RET(IsCrgCoreCkSel(handle->coreClkSelect), BASE_STATUS_ERROR); + + *(unsigned int *)CRG_HOSC_CTRL2_ADDR = 0x306E; /* Optimized HOSC temperature drift performance parameter. */ + + CRG_RegStruct *reg = handle->baseAddress; + g_crgBaseAddr = (void *)reg; + /* Check the validity of the PLL parameter configuration. */ + if (CRG_IsValidPllConfig(handle) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + /* Disable the write protection function of the CRG register. */ + DCL_SYSCTRL_CrgWriteProtectionDisable(); + + reg->PERI_CRG0.BIT.pll_ref_cksel = handle->pllRefClkSelect; + reg->PERI_CRG1.BIT.pll_prediv = handle->pllPreDiv; + reg->PERI_CRG2.BIT.pll_fbdiv = handle->pllFbDiv; + reg->PERI_CRG3.BIT.pll_postdiv1 = handle->pllPostDiv; + reg->PERI_CRG3.BIT.pll_postdiv2 = handle->handleEx.pllPostDiv2; + reg->PERI_CRG4.BIT.pll_pd = BASE_CFG_UNSET; + + while (reg->PERI_CRG7.BIT.pll_lock != BASE_CFG_SET) { + ; /* Wait for PLL to lock */ + } + + DCL_SYSCTRL_CrgWriteProtectionEnable(); + /* Check the 1MHz clock parameter configuration. */ + if (CRG_IsValid1MHzConfig(handle) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + while (reg->HOSC_LOCK.BIT.hosc_lock != BASE_CFG_SET) { + ; /* Wait for HOSC to lock */ + } + /* Set the Clock Source and Frequency Divider of the 1 MHz Clock. */ + reg->PERI_CRG67.BIT.clk_1m_div = handle->handleEx.clk1MDiv; + reg->PERI_CRG66.BIT.clk_1m_ini_cksel = handle->handleEx.clk1MSelect; + return BASE_STATUS_OK; +} + +/** + * @brief Set Crg Core clock by target frequecy + * @param handle CRG handle + * @param targetFreq Target Frequency, unit: Hz. + * @retval BASE_STATUS_ERROR Parameter Check fail + * @retval BASE_STATUS_OK Success + */ +BASE_StatusType HAL_CRG_InitWithTargetFrequence(const CRG_Handle *handle, unsigned int targetFreq) +{ + CRG_ASSERT_PARAM(handle != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(handle->baseAddress)); + CRG_PARAM_CHECK_WITH_RET(IsCrgPllRefClkSelect(handle->pllRefClkSelect), BASE_STATUS_ERROR); + CRG_PARAM_CHECK_WITH_RET((targetFreq <= CRG_CLK_TARGET_MAX_FREQ), BASE_STATUS_ERROR); + + CRG_Handle crgHandle; + CRG_PllDivCfg divCfg; + unsigned int pllRefFreq; + unsigned int fbFreq; + unsigned int temp; + /* Check the validity of the external crystal oscillator frequency. */ + if ((handle->pllRefClkSelect == CRG_PLL_REF_CLK_SELECT_XTAL) && \ + (XTRAIL_FREQ > 30000000U)) { /* The maximum of the external clock source is 30000000U. */ + return BASE_STATUS_ERROR; + } + /* Obtain the clock frequency based on the clock source. */ + pllRefFreq = (handle->pllRefClkSelect == CRG_PLL_REF_CLK_SELECT_HOSC) ? HOSC_FREQ : XTRAIL_FREQ; + CRG_GetPllOptConfig(targetFreq, pllRefFreq, &divCfg); + crgHandle = *handle; + crgHandle.pllPreDiv = divCfg.PreDiv; + crgHandle.pllFbDiv = divCfg.fbDiv; + crgHandle.pllPostDiv = divCfg.postDiv; + /* Calculate the posdiv2 frequency divider. */ + fbFreq = (pllRefFreq / (divCfg.PreDiv + 1)) * (divCfg.fbDiv + 1); + for (unsigned int i = CRG_PLL_POSTDIV2_1; i <= CRG_PLL_POSTDIV2_8_MAX; i++) { + temp = fbFreq / (i + 1); + if (temp <= CRG_CLK_PST2_MAX_FREQ) { /* The maximum value is used when the configuration is valid. */ + crgHandle.handleEx.pllPostDiv2 = i; + break; + } + if (i == CRG_PLL_POSTDIV2_8_MAX) { /* No valid value. */ + return BASE_STATUS_ERROR; + } + } + return HAL_CRG_Init(&crgHandle); +} + +/** + * @brief Clock Deinit + * @param handle CRG Handle + * @retval BASE_STATUS_OK + */ +BASE_StatusType HAL_CRG_DeInit(const CRG_Handle *handle) +{ + CRG_ASSERT_PARAM(handle != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(handle->baseAddress)); + CRG_RegStruct *reg = handle->baseAddress; + DCL_SYSCTRL_CrgWriteProtectionDisable(); + + reg->PERI_CRG0.BIT.pll_ref_cksel = 0x0; /* 0x0: default value */ + reg->PERI_CRG1.BIT.pll_prediv = 0x3; /* 0x3: default value */ + reg->PERI_CRG2.BIT.pll_fbdiv = 0x30; /* 0x30: default value */ + reg->PERI_CRG3.BIT.pll_postdiv1 = 0x1; /* 0x0: default value */ + reg->PERI_CRG4.BIT.pll_pd = 0x1; /* 0x1: default value */ + + DCL_SYSCTRL_CrgWriteProtectionEnable(); + + reg->PERI_CRG67.BIT.clk_1m_div = 0x29; /* 0x29: default value */ + reg->PERI_CRG66.BIT.clk_1m_ini_cksel = 0x0; /* 0x0: default value */ + return BASE_STATUS_OK; +} + +/** + * @brief Get Clock Config + * @param handle CRG Handle + * @retval BASE_STATUS_OK Success + */ +BASE_StatusType HAL_CRG_GetConfig(CRG_Handle *handle) +{ + CRG_ASSERT_PARAM(handle != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(handle->baseAddress)); + /* Obtains configuration parameters from registers. */ + CRG_RegStruct *reg = handle->baseAddress; + handle->pllRefClkSelect = reg->PERI_CRG0.BIT.pll_ref_cksel; + handle->pllPreDiv = reg->PERI_CRG1.BIT.pll_prediv; + handle->pllFbDiv = reg->PERI_CRG2.BIT.pll_fbdiv; + handle->pllPostDiv = reg->PERI_CRG3.BIT.pll_postdiv1; + handle->handleEx.pllPostDiv2 = reg->PERI_CRG3.BIT.pll_postdiv2; + /* Enable the PLL and start the PLL output clock frequency. */ + handle->pllPd = reg->PERI_CRG4.BIT.pll_pd; + handle->coreClkSelect = reg->PERI_CRG64.BIT.clk_pst1_sw_sel; + /* Get the 1MHz clock select and frequency division. */ + handle->handleEx.clk1MDiv = reg->PERI_CRG67.BIT.clk_1m_div; + handle->handleEx.clk1MSelect = reg->PERI_CRG66.BIT.clk_1m_ini_cksel; + return BASE_STATUS_OK; +} + +/** + * @brief Set CRG Core Clock Select + * @param handle CRG Handle + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Paramter check fail + */ +BASE_StatusType HAL_CRG_SetCoreClockSelect(CRG_Handle *handle) +{ + CRG_ASSERT_PARAM(handle != 0); + CRG_ASSERT_PARAM(IsCRGInstance(handle->baseAddress)); + CRG_PARAM_CHECK_WITH_RET(IsCrgCoreCkSel(handle->coreClkSelect), BASE_STATUS_ERROR); + + CRG_RegStruct *reg = handle->baseAddress; + /* The write protection of the CRG register needs to be disabled. */ + DCL_SYSCTRL_CrgWriteProtectionDisable(); + DCL_CRG_SetCoreClkSel(reg, handle->coreClkSelect); + DCL_SYSCTRL_CrgWriteProtectionEnable(); + + return BASE_STATUS_OK; +} + +/** + * @brief Get PLL Clock Frequence + * @param None + * @retval unsigned int PLL clock frequency + */ +static inline unsigned int CRG_GetVcoFreq(void) +{ + unsigned int freq; + unsigned int regFbdiv; + CRG_RegStruct *crg = g_crgBaseAddr; + + CRG_ASSERT_PARAM(IsCRGInstance(crg)); + CRG_ASSERT_PARAM((XTRAIL_FREQ <= 30000000U)); /* The maximum of the external clock source is 30000000U. */ + + freq = CRG_GetPllRefIni(crg->PERI_CRG0.BIT.pll_ref_cksel); + freq /= CRG_GetPreDivValue(crg->PERI_CRG1.BIT.pll_prediv); + regFbdiv = CRG_GetPllFbDivValue(crg->PERI_CRG2.BIT.pll_fbdiv); /* Get the value of the fbdiv register. */ + freq *= (regFbdiv >= 0x06) ? regFbdiv : 0x06; /* 0x0-0x6: divided by 0x6 */ + return freq; +} + +/** + * @brief Get PLL Clock Frequence + * @param None + * @retval unsigned int PLL clock frequency + */ +unsigned int HAL_CRG_GetPllFreq(void) +{ + unsigned int freq; + unsigned int pllPostDivValue; + CRG_RegStruct *crg = g_crgBaseAddr; + + CRG_ASSERT_PARAM(IsCRGInstance(crg)); + freq = CRG_GetVcoFreq(); + pllPostDivValue = CRG_GetPllPostDivValue((CRG_PllPostDiv)crg->PERI_CRG3.BIT.pll_postdiv1); + /* Calculate the PLL output clock frequency based on the VCO clock frequency and post-division coefficient. */ + if (pllPostDivValue != 0) { + freq /= pllPostDivValue; + } + return freq; +} + +/** + * @brief Get Core Clock Frequence + * @param None + * @retval unsigned int Core clock frequency + */ +unsigned int HAL_CRG_GetCoreClkFreq(void) +{ + unsigned int freq; + unsigned int coreClkSelect; + CRG_RegStruct *crg = g_crgBaseAddr; + + CRG_ASSERT_PARAM(IsCRGInstance(crg)); + coreClkSelect = crg->PERI_CRG64.BIT.clk_pst1_sw_sel; + switch (coreClkSelect) { + case CRG_CORE_CLK_SELECT_HOSC: /* The clock source is an internal high-speed clock. */ + freq = HOSC_FREQ; + break; + + case CRG_CORE_CLK_SELECT_TCXO: /* The clock source is the external crystal oscillator clock. */ + freq = XTRAIL_FREQ; + break; + + case CRG_CORE_CLK_SELECT_PLL: /* The clock source is the PLL. */ + freq = HAL_CRG_GetPllFreq(); + break; + + default: + freq = LOSC_FREQ; + break; + } + return freq; +} + +/** + * @brief Get Clock Frequence + * @param handle CRG Handle + * @retval Frequece of IP + */ +unsigned int HAL_CRG_GetIpFreq(const void *baseAddress) +{ + CRG_ASSERT_PARAM(baseAddress != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); +#ifdef FPGA + /* Use this function to obtain the clock frequency during the FPGA phase. */ + return CHIP_GetIpFreqHz(baseAddress); +#else + unsigned int hclk = HAL_CRG_GetCoreClkFreq(); + unsigned int freq = LOSC_FREQ; + unsigned int coreClkFreq; + /* Get the CRG type of the target IP. */ + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + if (p == NULL) { + return freq; + } + switch (p->type) { + case CRG_IP_NONE_CLK_SEL: + case CRG_IP_EFC: + case CRG_IP_ANA: + freq = hclk; /* Returns the internal high speed clock frequency. */ + break; + + case CRG_IP_CAN: + freq = CRG_GetPllRefIni(g_crgBaseAddr->PERI_CRG0.BIT.pll_ref_cksel); + break; + + case CRG_IP_ADC: + /* Get core clock frequence for calculating the ADC clock frequency. */ + coreClkFreq = HAL_CRG_GetCoreClkFreq(); + freq = CRG_GetAdcIpFreq(p, CRG_GetVcoFreq(), coreClkFreq); + break; + + case CRG_IP_IWDG: /* The IWDG clock frequency is an internal low-speed clock. */ + default: + break; + } + if (freq == 0) { + freq = LOSC_FREQ; + } + return freq; +#endif +} + +/** + * @brief Enable clock of ip + * @param baseAddress Ip base address + * @param enable enable mask + * @retval BASE_STATUS_ERROR Can't find the Match or operation is not support + * @retval BASE_STATUS_OK Operation Success + */ +BASE_StatusType HAL_CRG_IpEnableSet(const void *baseAddress, unsigned int enable) +{ + CRG_ASSERT_PARAM(baseAddress != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + /* Check the validity of the input parameters. */ + CRG_PARAM_CHECK_WITH_RET((enable == IP_CLK_ENABLE || enable == IP_CLK_DISABLE), BASE_STATUS_ERROR); + /* Get the CRG type of the target IP. */ + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + if ((p == NULL) || (p->type >= CRG_IP_MAX_TYPE)) { + return BASE_STATUS_ERROR; + } + if (g_ipClkProc[p->type].enableSet == NULL) { + return BASE_STATUS_ERROR; + } + g_ipClkProc[p->type].enableSet(p, enable); + return BASE_STATUS_OK; +} + +/** + * @brief Get clock enable status of ip + * @param baseAddress Ip base address + * @param enable parameter out for ip enable status + * @retval BASE_STATUS_ERROR Can't find the Match or operation is not support + * @retval BASE_STATUS_OK Operation Success + */ +BASE_StatusType HAL_CRG_IpEnableGet(const void *baseAddress, unsigned int *enable) +{ + CRG_ASSERT_PARAM(baseAddress != NULL); + CRG_ASSERT_PARAM(enable != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + /* Get the CRG type of the target IP. */ + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + if ((p == NULL) || (p->type < 0) || (p->type >= CRG_IP_MAX_TYPE)) { + return BASE_STATUS_ERROR; + } + if (g_ipClkProc[p->type].enableGet == NULL) { + return BASE_STATUS_ERROR; + } + *enable = g_ipClkProc[p->type].enableGet(p); /* Returns the module clock enable status. */ + return BASE_STATUS_OK; +} + +/** + * @brief Set clock select ip + * @param baseAddress Ip base address + * @param select clock select, @see CRG_APBLsClkSelect for ip in apb_ls_subsys or CRG_AdcClkSelect for adc + * @retval BASE_STATUS_OK success + * @retval BASE_STATUS_ERROR fail + */ +BASE_StatusType HAL_CRG_IpClkSelectSet(const void *baseAddress, unsigned int select) +{ + CRG_ASSERT_PARAM(baseAddress != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + if ((p == NULL) || (p->type >= CRG_IP_MAX_TYPE)) { + return BASE_STATUS_ERROR; + } + if (g_ipClkProc[p->type].clkSelSet == NULL) { + return BASE_STATUS_ERROR; + } + g_ipClkProc[p->type].clkSelSet(p, select); /* Clock selection of the configuration module. */ + return BASE_STATUS_OK; +} + +/** + * @brief Get clock select of ip + * @param baseAddress Ip base address + * @param clkSel Get clkSet value + * @retval BASE_STATUS_OK + * @retval BASE_STATUS_ERROR Match Fail or Not support + */ +BASE_StatusType HAL_CRG_IpClkSelectGet(const void *baseAddress, unsigned int *clkSel) +{ + CRG_ASSERT_PARAM(baseAddress != NULL); + CRG_ASSERT_PARAM(clkSel != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + /* Get the CRG type of the target IP. */ + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + if ((p == NULL) || (p->type >= CRG_IP_MAX_TYPE)) { + return BASE_STATUS_ERROR; + } + if (g_ipClkProc[p->type].clkSelGet == NULL) { + return BASE_STATUS_ERROR; + } + *clkSel = g_ipClkProc[p->type].clkSelGet(p); /* Obtains the module clock selection. */ + return BASE_STATUS_OK; +} + +/** + * @brief Reset/Set clock of ip + * @param baseAddress Ip base address + * @param reset Set reset value + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Match Fail or Not support + */ +BASE_StatusType HAL_CRG_IpClkResetSet(const void *baseAddress, unsigned int reset) +{ + CRG_ASSERT_PARAM(baseAddress != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + CRG_PARAM_CHECK_WITH_RET((reset == BASE_CFG_SET || reset == BASE_CFG_UNSET), BASE_STATUS_ERROR); + /* Get the CRG type of the target IP. */ + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + if ((p == NULL) || (p->type >= CRG_IP_MAX_TYPE)) { + return BASE_STATUS_ERROR; + } + if (g_ipClkProc[p->type].resetSet == NULL) { + return BASE_STATUS_ERROR; + } + g_ipClkProc[p->type].resetSet(p, reset); /* Configure the reset value of the module clock. */ + return BASE_STATUS_OK; +} + +/** + * @brief Get clock select of ip + * @param baseAddress Ip base address + * @param reset Get reset value + * @retval BASE_STATUS_OK Success + * @retval BASE_CFG_UNSET Match Fail or Not support + */ +BASE_StatusType HAL_CRG_IpClkResetGet(const void *baseAddress, unsigned int *reset) +{ + CRG_ASSERT_PARAM(baseAddress != NULL); + CRG_ASSERT_PARAM(reset != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + /* Get the CRG type of the target IP. */ + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + if ((p == NULL) || (p->type >= CRG_IP_MAX_TYPE)) { + return BASE_STATUS_ERROR; + } + if (g_ipClkProc[p->type].resetGet == NULL) { + return BASE_STATUS_ERROR; + } + *reset = g_ipClkProc[p->type].resetGet(p); /* Query the reset status of the module clock. */ + return BASE_STATUS_OK; +} + +/** + * @brief Reset/Set clock of ip + * @param baseAddress Ip base address + * @param div set div value + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Match Fail or Not support + */ +BASE_StatusType HAL_CRG_IpClkDivSet(const void *baseAddress, unsigned int div) +{ + CRG_ASSERT_PARAM(baseAddress != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + if ((p == NULL) || (p->type >= CRG_IP_MAX_TYPE)) { + return BASE_STATUS_ERROR; + } + if (g_ipClkProc[p->type].clkDivSet == NULL) { + return BASE_STATUS_ERROR; + } + g_ipClkProc[p->type].clkDivSet(p, div); /* Configure the clock frequency divider of the module. */ + return BASE_STATUS_OK; +} + +/** + * @brief Get clock select of ip + * @param baseAddress Ip base address + * @param div get div value + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Match Fail or Not support + */ +BASE_StatusType HAL_CRG_IpClkDivGet(const void *baseAddress, unsigned int *div) +{ + CRG_ASSERT_PARAM(baseAddress != NULL); + CRG_ASSERT_PARAM(div != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + /* Get the CRG type of the target IP. */ + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + if ((p == NULL) || (p->type >= CRG_IP_MAX_TYPE)) { + return BASE_STATUS_ERROR; + } + if (g_ipClkProc[p->type].clkDivGet == NULL) { + return BASE_STATUS_ERROR; + } + *div = g_ipClkProc[p->type].clkDivGet(p); /* Get the clock frequency division coefficient of a module. */ + return BASE_STATUS_OK; +} + +/** + * @brief PVD reset function enable switch + * @param pvd reset enable select + * @retval None + */ +void HAL_CRG_PvdResetEnable(bool enable) +{ + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + g_crgBaseAddr->PERI_CRG65.BIT.pvd_rst_enable = enable; +} + +/** + * @brief Based on the target frequency, obtain the post division of the pll + * @param targetFreq Target frequency + * @param clkPfdFreq The freq of Pll after frequency multiplication + * @param divCfg Output Pll division config + * @retval None + */ +static void CRG_GetPllTargetFreqPostDiv(unsigned int targetFreq, unsigned int preDiv, unsigned int fbDiv, + unsigned int clkPfdFreq, CRG_PllDivCfg *divCfg) +{ + unsigned int clkVcoFreq; + unsigned int freq; + unsigned int delta; + unsigned int minDelta = 0xFFFFFFFF; /* Set the maximum value and initialize the default value. */ + unsigned int postDiv; + + clkVcoFreq = clkPfdFreq * fbDiv; + for (unsigned int i = CRG_PLL_POSTDIV_1; i <= CRG_PLL_POSTDIV_8; i++) { + postDiv = i; + /* Check whether the frequency after frequency division is valid. */ + if (!IsCrgValidPostDiv(clkVcoFreq, postDiv)) { + continue; + } + freq = clkVcoFreq / (postDiv + 1); + delta = (targetFreq >= freq) ? targetFreq - freq : freq - targetFreq; + if (delta < minDelta) { /* Updating Configuration Parameter Values. */ + minDelta = delta; + divCfg->PreDiv = preDiv; + divCfg->fbDiv = fbDiv; + divCfg->postDiv = i; + } + } +} + +/** + * @brief Based on the target frequency, obtain the optimal frequency division coefficient of the pll + * @param targetFreq Target frequency + * @param pllRefFreq Pll refer clock frequency + * @param divCfg Output Pll division config + * @retval None + */ +static void CRG_GetPllOptConfig(unsigned int targetFreq, unsigned int pllRefFreq, CRG_PllDivCfg *divCfg) +{ + unsigned int preDiv[] = {CRG_PLL_PREDIV_1, CRG_PLL_PREDIV_2, CRG_PLL_PREDIV_3, CRG_PLL_PREDIV_4, CRG_PLL_PREDIV_5, + CRG_PLL_PREDIV_6, CRG_PLL_PREDIV_7, CRG_PLL_PREDIV_8}; + unsigned int preDivOut; + unsigned int clkPfdFreq; + /* Configuring PLL Parameter Initialization. */ + divCfg->PreDiv = CRG_PLL_PREDIV_1; + divCfg->fbDiv = CRG_PLL_FBDIV_MIN; + divCfg->postDiv = CRG_PLL_POSTDIV_1; + + for (unsigned int i = 0; i < sizeof(preDiv) / sizeof(preDiv[0]); ++i) { + preDivOut = CRG_GetPreDivValue(preDiv[i]); + /* Check whether the frequency value after pre-division is valid. */ + if (!IsCrgValidPreDiv(pllRefFreq, preDivOut)) { + continue; + } + clkPfdFreq = pllRefFreq / preDivOut; + + for (unsigned int j = CRG_PLL_FBDIV_MIN; j <= CRG_PLL_FBDIV_MAX; ++j) { + /* Check whether the frequency value after frequency multiplication is valid. */ + if (!IsCrgValidFdDiv(clkPfdFreq, j)) { + continue; + } + /* Get the post division of the pll. */ + CRG_GetPllTargetFreqPostDiv(targetFreq, preDiv[i], j, clkPfdFreq, divCfg); + } + } +} + +#ifndef FPGA +/** + * @brief Get ADC Clock Frequence + * @param matchInfo match info + * @param baseClkRate clock rate + * @param coreClkFreq core clock rate + * @retval Ip Frequence + */ +static unsigned int CRG_GetAdcIpFreq(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int baseClkRate, + unsigned int coreClkFreq) +{ + CRG_ASSERT_PARAM(matchInfo != NULL); + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + + unsigned int clkSel; + unsigned int clkDiv; + unsigned int pst2Div; + unsigned int freq = 0; + + /* Obtains the clock source selection of the ADC. */ + const CRG_IpProc *proc = &g_ipClkProc[matchInfo->type]; + if (proc->clkSelGet == NULL) { + return 0; + } + clkSel = proc->clkSelGet(matchInfo); + /* Calculate the frequency from the ADC's clock source. */ + if (clkSel == CRG_ADC_CLK_SYN_CORE) { + freq = coreClkFreq; + } else if (clkSel == CRG_ADC_CLK_ASYN_HOSC) { + freq = HOSC_FREQ; + } else if (clkSel == CRG_ADC_CLK_ASYN_TCXO) { + /* The maximum speed of the external clock source is 30000000U. */ + freq = (XTRAIL_FREQ > 30000000U) ? 0 : XTRAIL_FREQ; + } else if (clkSel == CRG_ADC_CLK_ASYN_PLL_DIV) { + pst2Div = CRG_GetPllPostDivValue((CRG_PllPostDiv)g_crgBaseAddr->PERI_CRG3.BIT.pll_postdiv2); + freq = baseClkRate / pst2Div; + } + + /* Obtain the frequency divider based on the ADC clock source. */ + if (proc->clkDivGet == NULL) { + return 0; + } + clkDiv = proc->clkDivGet(matchInfo); + /* Calculate the clock frequency of the ADC. */ + return (freq / (clkDiv + 1)); +} + +#endif +/** + * @brief Check is Valid Pll Config + * @param CRG_Handle CRG handle + * @retval BASE_STATUS_OK Check Success + * @retval BASE_STATUS_ERROR Check Fail + */ +static BASE_StatusType CRG_IsValidPllConfig(const CRG_Handle *handle) +{ + unsigned int preDiv; + unsigned int freq; + + freq = CRG_GetPllRefIni(handle->pllRefClkSelect); + preDiv = CRG_GetPreDivValue(handle->pllPreDiv); + /* Check the validity of the prescaled clock frequency. */ + if (!IsCrgValidPreDiv(freq, preDiv)) { + return BASE_STATUS_ERROR; + } + freq /= preDiv; + /* Check the validity of the clock frequency after frequency multiplication. */ + if (!IsCrgValidFdDiv(freq, handle->pllFbDiv)) { + return BASE_STATUS_ERROR; + } + freq *= (handle->pllFbDiv > 0x06) ? handle->pllFbDiv : 0x06; /* 0x0-0x6: divided by 0x6 */ + /* Check whether the PLL output frequency is valid. */ + if (IsCrgValidPostDiv(freq, handle->pllPostDiv) && IsCrgValidPostDiv2(freq, handle->handleEx.pllPostDiv2)) { + return BASE_STATUS_OK; + } + return BASE_STATUS_ERROR; +} + +/** + * @brief Check is Valid 1MHz Config + * @param CRG_Handle CRG handle + * @retval BASE_STATUS_OK Check Success + * @retval BASE_STATUS_ERROR Check Fail + */ +static BASE_StatusType CRG_IsValid1MHzConfig(const CRG_Handle *handle) +{ + unsigned int freq; + /* Get the ref frequency of the 1 MHz clock. */ + freq = (handle->handleEx.clk1MSelect == CRG_1M_CLK_SELECT_HOSC) ? HOSC_FREQ : XTRAIL_FREQ; + /* Check whether the 1MHz output frequency is valid. */ + if ((freq / (handle->handleEx.clk1MDiv + 1)) == CRG_FREQ_1MHz) { + return BASE_STATUS_OK; + } + return BASE_STATUS_ERROR; +} + +/** + * @brief Get clock frequence + * @param crg CRG_RegStruct + * @retval The frequence fo clock + */ +static inline unsigned int CRG_GetPllRefIni(CRG_PllRefClkSelect pllRefClkSelect) +{ + /* The maximum speed of the external clock source is 30000000U. */ + if (pllRefClkSelect == CRG_PLL_REF_CLK_SELECT_XTAL && XTRAIL_FREQ > 30000000U) { + return 0; + } + return (pllRefClkSelect == (unsigned int)CRG_PLL_REF_CLK_SELECT_HOSC) ? HOSC_FREQ : XTRAIL_FREQ; +} + +/** + * @brief Get previous division Value before PLL + * @param crg CRG_RegStruct + * @retval Previous Div value + */ +static inline unsigned int CRG_GetPreDivValue(CRG_PllPreDiv pllPredDiv) +{ + unsigned int preDiv; + if (pllPredDiv <= CRG_PLL_PREDIV_1) { /* 0 or 1 returns PLL_PREDIV_OUT_1. */ + preDiv = PLL_PREDIV_OUT_1; + } else { + preDiv = pllPredDiv + 1; + } + return preDiv; +} + +/** + * @brief Get PLL loop divider ratio + * @param crg CRG_RegStruct + * @retval PLL loop divider ratio + */ +static inline unsigned int CRG_GetPllFbDivValue(unsigned int pllFbDiv) +{ + unsigned int div = pllFbDiv; + /* Check the validity of the minimum frequency multiplication parameter. */ + if (div < CRG_PLL_FBDIV_MIN) { + div = CRG_PLL_FBDIV_MIN; + } + /* Check the validity of the maximum frequency multiplication parameter. */ + if (div > CRG_PLL_FBDIV_MAX) { + div = CRG_PLL_FBDIV_MAX; + } + return div; +} + +/** + * @brief Get post division Value after PLL + * @param crg CRG_RegStruct + * @retval Previous Div value + */ +static inline unsigned int CRG_GetPllPostDivValue(unsigned int pllPostDiv) +{ + unsigned int div = pllPostDiv; + if (div > CRG_PLL_POSTDIV_8) { + div = (CRG_PLL_POSTDIV_8 + 1); /* If the postdiv is greater than 8, set this postdiv to 8. */ + } else { + div += 1; + } + return div; +} + +/** + * @brief Enable Set of IP in APB_HS_SUBSYS + * @param matchInfo IP without Clock select match info + * @param enable BASE_CFG_SET or BASE_CFG_UNSET + * @retval None + */ +static void CRG_IpWoClkSelEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable) +{ + CRG_ASSERT_PARAM(matchInfo != NULL); + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_IpWoClkSelectCfg *p = (CRG_IpWoClkSelectCfg *)(void *)(base + matchInfo->regOffset); + CRG_IpWoClkSelectCfg cfg; + cfg.value = p->value; + if (enable & IP_CLK_ENABLE) { /* Set enable of target ip. */ + cfg.BIT.clkEnMask |= 1 << matchInfo->bitOffset; + cfg.BIT.softResetReq &= ~(1 << matchInfo->bitOffset); + } else { + cfg.BIT.clkEnMask &= ~(1 << matchInfo->bitOffset); /* Disable of target ip. */ + cfg.BIT.softResetReq |= (1 << matchInfo->bitOffset); + } + p->value = cfg.value; +} + +/** + * @brief Get Enable status of IP in APB_HS_SUBSYS + * @param matchInfo IP without Clock select match info + * @retval Clock Enable status + */ +static unsigned int CRG_IpWoClkSelEnableGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + CRG_ASSERT_PARAM(matchInfo != NULL); + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + /* Get enable status of target ip. */ + CRG_IpWoClkSelectCfg *p = (CRG_IpWoClkSelectCfg *)(void *)(base + matchInfo->regOffset); + CRG_IpWoClkSelectCfg cfg; + + cfg.value = p->value; + return (cfg.BIT.clkEnMask & (1 << matchInfo->bitOffset)) == 0 ? false : true; +} + +/** + * @brief Reset/undo reset of IP in APB_HS_SUBSYS + * @param matchInfo IP without Clock select match info + * @param reset BASE_CFG_SET or BASE_CFG_UNSET + * @retval None + */ +static void CRG_IpWoClkSelResetSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int reset) +{ + CRG_ASSERT_PARAM(matchInfo != NULL); + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_IpWoClkSelectCfg *p = (CRG_IpWoClkSelectCfg *)(void *)(base + matchInfo->regOffset); + CRG_IpWoClkSelectCfg cfg; + cfg.value = p->value; + if (reset & BASE_CFG_SET) { + cfg.BIT.softResetReq |= 1 << matchInfo->bitOffset; /* reset of target ip. */ + } else { + cfg.BIT.softResetReq &= ~(1 << matchInfo->bitOffset); /* Undo reset of target ip. */ + } + p->value = cfg.value; +} + +/** + * @brief Get Reset status of IP in APB_HS_SUBSYS + * @param matchInfo IP without Clock select match info + * @retval Clock select reset status + */ +static unsigned int CRG_IpWoClkSelResetGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + CRG_ASSERT_PARAM(matchInfo != NULL); + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + /* Get the reset status of target ip. */ + CRG_IpWoClkSelectCfg *p = (CRG_IpWoClkSelectCfg *)(void *)(base + matchInfo->regOffset); + CRG_IpWoClkSelectCfg cfg; + cfg.value = p->value; + return (cfg.BIT.softResetReq & (1 << matchInfo->bitOffset)) ? BASE_CFG_SET : BASE_CFG_UNSET; +} + +/** + * @brief Enable/Disable ADC Clock + * @param matchInfo ADC match info + * @param enable IP_CLK_ENABLE + * @retval None + */ +static void CRG_AdcEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable) +{ + CRG_ASSERT_PARAM(matchInfo != NULL); + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + CRG_AdcIpCfg cfg; + cfg.value[1] = p->value[1]; + if (enable) { /* Enables and Deassert reset the ADC clock. */ + cfg.BIT.clk_adc_cken = BASE_CFG_SET; + cfg.BIT.adc_srst_req = BASE_CFG_UNSET; + } else { /* Disable and reset the ADC clock. */ + cfg.BIT.clk_adc_cken = BASE_CFG_UNSET; + cfg.BIT.adc_srst_req = BASE_CFG_UNSET; + } + p->value[1] = cfg.value[1]; +} + +/** + * @brief Get Enable status of ADC + * @param matchInfo ADC match info + * @retval Cken of ADC + */ +static unsigned int CRG_AdcEnableGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + CRG_ASSERT_PARAM(matchInfo != NULL); + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + unsigned int enable; + /* Get the enable status of the ADC clock gating. */ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + enable = ((p->BIT.clk_adc_cken != 0)) ? IP_CLK_ENABLE : IP_CLK_DISABLE; + return enable; +} + +/** + * @brief Set ADC Clock Select + * @param matchInfo ADC match info + * @param clkSelect @see CRG_AdcClkSelect + * @retval None + */ +static void CRG_AdcClkSelectSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int clkSelect) +{ + CRG_ASSERT_PARAM(matchInfo != NULL); + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + CRG_PARAM_CHECK_NO_RET(IsCrgAdcClkModeSelect(clkSelect)); + + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + if (clkSelect == CRG_ADC_CLK_SYN_CORE) { + p->BIT.cfg_adc_ckmode_sel = BASE_CFG_SET; /* use sync clock */ + } else { + DCL_SYSCTRL_CrgWriteProtectionDisable(); + g_crgBaseAddr->PERI_CRG64.BIT.clk_pst2_sw_sel = clkSelect; /* write clock selection */ + DCL_SYSCTRL_CrgWriteProtectionEnable(); + p->BIT.cfg_adc_ckmode_sel = BASE_CFG_UNSET; + } +} + +/** + * @brief Get ADC Clock Select + * @param matchInfo ADC match info + * @retval Adc Clock select @see CRG_AdcClkSelect + */ +static unsigned int CRG_AdcClkSelectGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + CRG_ASSERT_PARAM(matchInfo != NULL); + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + if (p->BIT.cfg_adc_ckmode_sel == BASE_CFG_SET) { + return CRG_ADC_CLK_SYN_CORE; /* Synchronous clock signal */ + } + return g_crgBaseAddr->PERI_CRG64.BIT.clk_pst2_sw_sel; /* asynchronous clock signal */ +} + +/** + * @brief Set ADC Div + * @param matchInfo ADC match info + * @param div Adc clock division + * @retval None + */ +static void CRG_AdcDivSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int div) +{ + CRG_ASSERT_PARAM(matchInfo != NULL); + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + CRG_PARAM_CHECK_NO_RET(IsCrgAdcClkDiv(div)); + + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + unsigned int clkMode = p->BIT.cfg_adc_ckmode_sel; + if (clkMode == CRG_ADC_CLK_SYNCHRONOUS) { + p->BIT.clk_adc_div1 = div; /* write div to I1 */ + } else { + p->BIT.clk_adc_div0 = div; /* write div to I0 */ + } +} + +/** + * @brief Get ADC clock division + * @param matchInfo ADC match info + * @retval Adc clock division + */ +static unsigned int CRG_AdcDivGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + CRG_ASSERT_PARAM(matchInfo != NULL); + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + + unsigned int clkMode = p->BIT.cfg_adc_ckmode_sel; + + if (clkMode == CRG_ADC_CLK_SYNCHRONOUS) { + return p->BIT.clk_adc_div1; /* return div value I1 */ + } + return p->BIT.clk_adc_div0; /* return div valye I0 */ +} + +/** + * @brief Enable Clock of EFC + * @param matchInfo EFC match Info + * @param enable IP_CLK_ENABLE or IP_CRG_DISABLE + */ +static void CRG_EfcEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable) +{ + CRG_ASSERT_PARAM(matchInfo != NULL); + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + /* Enables or disables EFC clock gating. */ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_EfcIpCfg *p = (CRG_EfcIpCfg *)(void *)(base + matchInfo->regOffset); + p->BIT.eflash_cken = (enable & IP_CLK_ENABLE) ? BASE_CFG_SET : BASE_CFG_UNSET; +} + +/** + * @brief Disable Clock of EFC + * @param matchInfo EFC match Info + * @return unsigned int IP_CLK_ENABLE or IP_CRG_DISABLE + */ +static unsigned int CRG_EfcEnableGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + CRG_ASSERT_PARAM(matchInfo != NULL); + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + /* Get the value of the EFC register in the CRG. */ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_EfcIpCfg *p = (CRG_EfcIpCfg *)(void *)(base + matchInfo->regOffset); + return p->BIT.eflash_cken; +} + + +/** + * @brief Enable Clock of ANA + * @param matchInfo ANA match Info + * @param enable IP_CLK_ENABLE or IP_CRG_DISABLE + */ +static void CRG_AnaEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable) +{ + CRG_ASSERT_PARAM(matchInfo != NULL); + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + CRG_PARAM_CHECK_NO_RET(enable == IP_CLK_ENABLE || enable == IP_CLK_DISABLE); + + /* Get the value of the ANA IP register in the CRG. */ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_AnaIpCfg *p = (CRG_AnaIpCfg *)(void *)(base + matchInfo->regOffset + matchInfo->bitOffset); + + if ((enable == IP_CLK_ENABLE) && (p->BIT.ip_srst_req == BASE_CFG_SET)) { + p->BIT.ip_srst_req = BASE_CFG_UNSET; + g_anaEnableFlag++; /* count enable analog IP number */ + } else if ((enable == IP_CLK_DISABLE) && (p->BIT.ip_srst_req == BASE_CFG_UNSET)) { + p->BIT.ip_srst_req = BASE_CFG_SET; + if (g_anaEnableFlag > 0) { + g_anaEnableFlag--; /* Decreasing the count to enable the analog IP number. */ + } + } + + if ((g_anaEnableFlag == 0) && (enable == IP_CLK_DISABLE)) { /* all analog clock disable */ + CRG->PERI_CRG660.BIT.clk_ana_cken = BASE_CFG_UNSET; + CRG->PERI_CRG660.BIT.ana_srst_req = BASE_CFG_SET; + } else if ((g_anaEnableFlag > 0) && (enable == IP_CLK_ENABLE)) { /* all analog clock enable */ + CRG->PERI_CRG660.BIT.ana_srst_req = BASE_CFG_UNSET; + CRG->PERI_CRG660.BIT.clk_ana_cken = BASE_CFG_SET; + } +} + +/** + * @brief Get Clock of ANA + * @param matchInfo ANA match Info + * @return unsigned int IP_CLK_ENABLE or IP_CRG_DISABLE + */ +static unsigned int CRG_AnaEnableGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + CRG_ASSERT_PARAM(matchInfo != NULL); + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + + /* Get the value of the ANA IP register in the CRG. */ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_AnaIpCfg *p = (CRG_AnaIpCfg *)(void *)(base + matchInfo->regOffset + matchInfo->bitOffset); + /* The clock is enabled based on the IP reset status. */ + return (p->BIT.ip_srst_req) ? BASE_CFG_UNSET : BASE_CFG_SET; +} diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/dac/common/inc/dac.h b/vendor/xinlingyu_92_3061M/Project/drivers/dac/common/inc/dac.h new file mode 100644 index 0000000000000000000000000000000000000000..4849c0926f119e9da7ff28e028190b5e3f9030ab --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/dac/common/inc/dac.h @@ -0,0 +1,81 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dac.h + * @author MCU Driver Team. + * @brief DAC module driver. + * This file provides functions declaration of the Comparator. + * + DAC's Initialization and de-initialization functions + * + Set DAC value function + */ +#ifndef McuMagicTag_DAC_H +#define McuMagicTag_DAC_H + +#include "dac_ip.h" + +/** + * @defgroup DAC DAC + * @brief DAC module. + * @{ + */ + +/** + * @defgroup DAC_Common DAC Common + * @brief DAC common external module. + * @{ + */ + +/** + * @defgroup DAC_Handle_Definition DAC Handle Definition + * @{ + */ + +/** + * @brief DAC Handle + */ +typedef struct _DAC_Handle { + DAC_RegStruct *baseAddress; /**< DAC registers base address. */ + volatile unsigned int dacValue; /**< DAC configuration value. */ + + DAC_ExtendHandle handleEx; /* DAC Handle Ex. */ +} DAC_Handle; + +/** + * @} + */ + +/** + * @defgroup DAC_API_Declaration DAC HAL API + * @{ + */ +/* DAC APIs */ +BASE_StatusType HAL_DAC_Init(DAC_Handle *dacHandle); +BASE_StatusType HAL_DAC_DeInit(DAC_Handle *dacHandle); +void HAL_DAC_SetValue(DAC_Handle *dacHandle, unsigned int value); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/dac/inc/dac_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/dac/inc/dac_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..f51391252836e3bcae9231ca514b35c496c8643b --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/dac/inc/dac_ip.h @@ -0,0 +1,180 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dac_ip.h + * @author MCU Driver Team + * @brief DAC module driver. + * This file provides DCL functions to manage DAC and Definitions of specific parameters. + * + Definition of DAC configuration parameters. + * + DAC register mapping structure. + * + Parameters check functions. + * + Direct configuration layer interface. + */ +#ifndef McuMagicTag_DAC_IP_H +#define McuMagicTag_DAC_IP_H + +#include "baseinc.h" + +#ifdef DAC_PARAM_CHECK +#define DAC_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define DAC_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define DAC_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define DAC_ASSERT_PARAM(para) ((void)0U) +#define DAC_PARAM_CHECK_NO_RET(para) ((void)0U) +#define DAC_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +#define DAC_MAX_OUT_VALUE 0x3FF + +/** + * @addtogroup DAC + * @{ + */ + +/** + * @defgroup DAC_IP DAC_IP + * @brief DAC_IP: dac_v1. + * @{ + */ + +/** + * @defgroup DAC_REG_Definition DAC Register Structure. + * @brief DAC Register Structure Definition. + * @{ + */ + +/** + * @brief Extent handle definition of DAC. + */ +typedef struct { +} DAC_ExtendHandle; + +/** + * @brief Control register 0. + */ +typedef union { + unsigned int reg; + struct { + unsigned int da_dac_enh : 1; /**< DAC Enable. */ + unsigned int reserved_0 : 31; + } BIT; +} volatile DAC_CTRL_REG0; + +/** + * @brief Control register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_dac_vset : 10; /**< DAC voltage level. */ + unsigned int reserved_0 : 22; + } BIT; +} volatile DAC_CTRL_REG1; + +/** + * @brief DAC TRIM register 0. + */ +typedef union { + unsigned int reg; + struct { + unsigned int da_dac_trim : 8; /**< ATE determines configured value, and system reset clears. */ + unsigned int reserved_0 : 24; + } BIT; +} volatile DAC_TRIM_REG0; + +/** + * @brief DAC TRIM register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_dac_k_trim : 11; /**< Value of DAC gain trim. */ + unsigned int reserved_0 : 5; + unsigned int cfg_dac_b_trim : 9; /**< Value of DAC offset trim. */ + unsigned int reserved_1 : 7; + } BIT; +} volatile DAC_TRIM_REG1; + +/** + * @brief DAC registers definition structure. + */ +typedef struct _DAC_RegStruct { + DAC_CTRL_REG0 DAC_CTRL; /**< DAC control register. Offset address: 0x00000000U */ + unsigned char space0[12]; + DAC_CTRL_REG1 DAC_VALUE; /**< DAC voltage level configuration register. Offset address: 0x00000010U */ +} volatile DAC_RegStruct; + +/* Parameter Check -----------------------------------------------------------*/ + +/** + * @brief Verify count value of the DAC sine wave interval. + * @param dacValue Pwm number, only valid if keep equ 0 + * @retval true + * @retval false + */ +static inline bool IsDacConfigureValue(unsigned short dacValue) +{ + return ((dacValue) <= DAC_MAX_OUT_VALUE); +} + +/** + * @brief Enable DAC + * @param dacx: DAC register base address. + * @retval None. + */ +static inline void DCL_DAC_Enable(DAC_RegStruct *dacx) +{ + DAC_ASSERT_PARAM(IsDACInstance(dacx)); + dacx->DAC_CTRL.BIT.da_dac_enh = BASE_CFG_ENABLE; +} + +/** + * @brief Disable DAC + * @param dacx: DAC register base address. + * @retval None. + */ +static inline void DCL_DAC_Disable(DAC_RegStruct *dacx) +{ + DAC_ASSERT_PARAM(IsDACInstance(dacx)); + dacx->DAC_CTRL.BIT.da_dac_enh = BASE_CFG_DISABLE; +} + +/** + * @brief Set DAC value + * @param dacx: DAC register base address. + * @param value: DAC value. + */ +static inline void DCL_DAC_SetValue(DAC_RegStruct *dacx, unsigned int value) +{ + DAC_ASSERT_PARAM(IsDACInstance(dacx)); + DAC_PARAM_CHECK_NO_RET(value <= DAC_MAX_OUT_VALUE); + dacx->DAC_VALUE.BIT.cfg_dac_vset = value; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/dac/src/dac.c b/vendor/xinlingyu_92_3061M/Project/drivers/dac/src/dac.c new file mode 100644 index 0000000000000000000000000000000000000000..7dbd89f6f90f1b5c7622971fb9793529c6aa5123 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/dac/src/dac.c @@ -0,0 +1,77 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dac.c + * @author MCU Driver Team. + * @brief DAC HAL level module driver. + * This file provides firmware functions to manage the following + * functionalities of the DAC and Comparator. + * + DAC's Initialization and de-initialization functions + * + Set DAC value function + */ +#include "dac.h" +#include "assert.h" + +/** + * @brief Set DAC value + * @param dacHandle: DAC handle. + * @param value: DAC value. + * @retval None. + */ +void HAL_DAC_SetValue(DAC_Handle *dacHandle, unsigned int value) +{ + DAC_ASSERT_PARAM(dacHandle != NULL); + DAC_ASSERT_PARAM(IsDACInstance(dacHandle->baseAddress)); + DAC_PARAM_CHECK_NO_RET(value <= DAC_MAX_OUT_VALUE); + /* Change the conversion value of the DAC. */ + dacHandle->baseAddress->DAC_VALUE.BIT.cfg_dac_vset = value; +} + +/** + * @brief DAC HAL Init + * @param dacHandle: DAC handle. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_DAC_Init(DAC_Handle *dacHandle) +{ + /* Repeat config stable time */ + BASE_FUNC_DELAY_US(4); /* delay 4us */ + DAC_ASSERT_PARAM(dacHandle != NULL); + DAC_ASSERT_PARAM(IsDACInstance(dacHandle->baseAddress)); + DAC_PARAM_CHECK_WITH_RET(IsDacConfigureValue(dacHandle->dacValue), BASE_STATUS_ERROR); + /* Conversion value of the DAC. */ + dacHandle->baseAddress->DAC_VALUE.BIT.cfg_dac_vset = dacHandle->dacValue; + /* Turn on the DAC. */ + dacHandle->baseAddress->DAC_CTRL.BIT.da_dac_enh = BASE_CFG_ENABLE; + /* Wait output stable */ + BASE_FUNC_DELAY_US(60); /* delay 60us */ + return BASE_STATUS_OK; +} + +/** + * @brief DAC HAL DeInit + * @param dacHandle: DAC handle. + * @retval BASE_StatusType: OK + */ +BASE_StatusType HAL_DAC_DeInit(DAC_Handle *dacHandle) +{ + DAC_ASSERT_PARAM(dacHandle != NULL); + DAC_ASSERT_PARAM(IsDACInstance(dacHandle->baseAddress)); + dacHandle->baseAddress->DAC_CTRL.reg = BASE_CFG_DISABLE; /* Disable DAC, clears the count value. */ + dacHandle->baseAddress->DAC_VALUE.reg = BASE_CFG_DISABLE; /* Clear DAC value. */ + return BASE_STATUS_OK; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/inc/debug.h b/vendor/xinlingyu_92_3061M/Project/drivers/debug/inc/debug.h new file mode 100644 index 0000000000000000000000000000000000000000..ce2a1aa5293eac2a7933168ef0a98811b74d65d8 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/inc/debug.h @@ -0,0 +1,90 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file debug.h + * @author MCU Driver Team + * @brief Header file containing functions prototypes of DEBUG module. + * + Initialization and de-initialization functions + * + Format print function + */ + +#ifndef McuMagicTag_DEBUG_H +#define McuMagicTag_DEBUG_H + +#include "uart.h" + +#ifdef DEBUG_PARAM_CHECK +#define DEBUG_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define DEBUG_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define DEBUG_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define DEBUG_ASSERT_PARAM(para) ((void)0U) +#define DEBUG_PARAM_CHECK_NO_RET(para) ((void)0U) +#define DEBUG_PARAM_CHECK_WITH_RET(param, ret) ((void)0U) +#endif + +/** + * @defgroup DEBUG DEBUG + * @brief DEBUG module. + * @{ + */ + + +/** + * @defgroup DEBUG_Common DEBUG Common + * @brief DEBUG common external module. + * @{ + */ + +/* Macro definitions for enabling the function of DEBUG_PRINT submodule */ +#define BAUDRATE 115200 + +#if (DBG_PRINTF_USE == DBG_USE_NO_PRINTF) +static inline int DBG_dummy(const char *format, ...) +{ + BASE_FUNC_UNUSED(format); + return 0; +} /* dummy debug function */ +#define DBG_PRINTF DBG_dummy /* Delete all print statement */ +#endif + +#if (DBG_PRINTF_USE == DBG_USE_UART_PRINTF) +#define DBG_PRINTF DBG_UartPrintf /**< Select the customized printf function */ +#endif + +/** + * @defgroup DEBUG_API_Declaration DEBUG HAL API + * @{ + */ +BASE_StatusType DBG_UartPrintInit(unsigned int baudRate); +BASE_StatusType DBG_UartPrintDeInit(void); + +/* Format print function */ +int DBG_UartPrintf(const char *format, ...); /* Supported format: %c, %s, %d, %u, %x, %X, %p, %f */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_DEBUG_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/cmd.h b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/cmd.h new file mode 100644 index 0000000000000000000000000000000000000000..ae00b8e9ea00eaafc5d78bd102250df206c96793 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/cmd.h @@ -0,0 +1,89 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cmd.h + * @author MCU Driver Team + * @brief Header file containing functions prototypes of DEBUG module. + * + Initialization and de-initialization functions + * + Format cmd function + */ +#ifndef CMD_H +#define CMD_H + +#include "module.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C"{ +#endif +#endif /* __cplusplus */ + +#ifndef CMD_REGESTER_MAX_NUM +#define CMD_REGESTER_MAX_NUM 128 // The maximum length of the command +#endif + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup CMD_Def CMD_Def + * @brief Command line registration initialization. + * @{ + */ + +/* Defines a function pointer to command registered function */ +typedef int (*pfncmd)(unsigned int argc, const char *argv[]); +/* defines the structure required for registering a function */ +struct cmdRegisterTable { + char *name; + pfncmd func; +}; + +/** + * @brief cmd_regester + * @attention None + * + * @param cmdName [IN] registration name, which is a character string + * @param func [IN] register the function corresponding to the name + * @retval void None + */ +void ExtCmdRegister(char *cmdName, pfncmd func); + +/** + * @brief get regester address + * @attention None + * + * @retval struct cmdRegisterTable * + */ +struct cmdRegisterTable *GetRegisterAddr(void); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ +/** + * @} + */ + +/** + * @} + */ +#endif /* __EXT_DEBUG_H__ */ diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/cmd_common.h b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/cmd_common.h new file mode 100644 index 0000000000000000000000000000000000000000..909206c802ff37ab0ef57a478b2d12e120b574af --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/cmd_common.h @@ -0,0 +1,109 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cmd_common.h + * @author MCU Driver Team + * @brief cmd module driver + * @details The header file contains the following declaration: + * + cmd configuration enums. + * + cmd register structures. + * + cmd DCL Functions. + * + Parameters check functions. + */ +#ifndef CMD_COMMON_H +#define CMD_COMMON_H + +/* Include Header Files */ +#include "type.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +/* Macro Definition */ +#define MATCH_CMD_BUF_CNT 8 + +#define ARGS_NUM_MAX 16 +#define CMD_BUF_MAX 128 + +#define CMD_NUM_MAX 5 + +#define DIR_KEY_HEAD (0x1b) +#define DEL ((char)255) +#define DEL7 ((char)127) + +#define CTL_CH(c) ((c) - 'a' + 1) +#define CTL_CH_C 3 /* define the ctl c key */ +#define CTL_CH_P 16 /* define the ctl p key */ +#define CTL_CH_N 14 /* define the ctl n key */ +#define CTL_BACKSPACE ('\b') +#define SPACE_KEY (' ') +#define TAB_KEY 9 /* define the tab key */ +#define ENTER_KEY1 13 /* define the '\r' */ +#define ENTER_KEY2 10 /* define the '\n' */ + +#define APP_CMD_ERR_PRINT(fmt...) EXT_ERR_PRINT(EXT_MODULE_APP_CMD, fmt) + +/** + * @addtogroup DEBUG + * @brief DEBUG module. + * @{ + */ + +/** + * @defgroup DEBUG_Log DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup CMD_COMMON_Def CMD_COMMON_Def + * @brief Common Command Line Interface. + * @{ + */ +/** + * @} + */ + +/** + * @brief Interprets the string of characters. + * @param cmdStr command string + * @argv At the command line, type a string of cosmonies + * @retval the following is the standard + */ +unsigned int CmdParserParam(char *cmdStr, const char *argv[]); +/** + * @brief Interprets the string of characters. + * @param None + * @retval None + */ +void ExtAppCmdProcess(void); +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ +/** + * @} + */ + +/** + * @} + */ +#endif /* __APP_COMMAND_H__ */ diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/command.h b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/command.h new file mode 100644 index 0000000000000000000000000000000000000000..4732fafa737aef17ef85136b70f101cd08bbb122 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/command.h @@ -0,0 +1,91 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file command.h + * @author MCU Driver Team + * @brief Header file containing functions prototypes of DEBUG module. + * + Initialization and de-initialization functions + * + Format command function + */ +#ifndef COMMAND_H +#define COMMAND_H + +#include "cmd.h" + +#define UART_SWITCH_CMD "soct_pq_tool" + +#define CMD_SECTION __attribute__((unused, section(".command"))) + +struct CmdTable { + const char *name; /* Command Name */ + int (*pfncmd)(unsigned int argc, const char *argv[]); +}; + +#define CMD_REGESTER(name, cmd) \ + struct CmdTable __cmd_##name CMD_SECTION = { #name, cmd } + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup COMMAND_Def COMMAND_Def + * @brief Command processing. + * @{ + */ + +/** + * @brief use cmd line to find cmd + * @attention None + * + * @param str [IN] command character string carried in the command line + * @retval struct cmdRegisterTable * + */ +struct cmdRegisterTable *ExtCmdFindCmd(const char *str); + +/** + * @brief use cmd line to match cmd read + * @attention None + * @param head [IN] enter a portion of the complete command you want at the command line + * @param res [out] the string array is used to store all matching strings + * @param len [IN] length of the string array + * @param findCnt [out] Number of matched strings + * @param tailId [out] Record the location of the last search + * @retval unsigned char Whether the matching is complete. + * If the matching is successful, true is returned. If the matching fails, false is returned + */ +unsigned char ExtCmdFindMatchCmd(const char *head, const char *res[], unsigned char resLen, unsigned char *findCnt, + unsigned int *tailId); +#define UESR_CMD_SECTION __attribute__((unused, section(".user_command"))) + +struct UserCmdTable { + unsigned short cmd; /* Command ID */ + int (*pfnUserMCUCmd)(unsigned char len, unsigned char* param); +}; + +#define USRER_CMD_REGESTER(pfn, cmd) \ + struct UserCmdTable __user_cmd_##pfn USER_CMD_SECTION = { cmd, pfn } +/** + * @} + */ + +/** + * @} + */ +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/common.h b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/common.h new file mode 100644 index 0000000000000000000000000000000000000000..0e13687c51ad8b406f5ed891b2d15c973cfad29f --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/common.h @@ -0,0 +1,90 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file common.h + * @author MCU Driver Team + * @brief Header file containing functions prototypes of cmd module. + * + Initialization and de-initialization functions + * + Format common function + */ +#ifndef COMMON_H +#define COMMON_H + +#include "type.h" +#include "ext_log.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* __cplusplus */ + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup CONFIG_Def CONFIG_Def + * @brief Processing Special Characters. + * @{ + */ + +#define EXT_ARRAY_COUNT(x) (sizeof(x) / sizeof(x[0])) +#define EXT_ALIGN_4(x) ((unsigned int)(x + 0x3) & (~0x3)) +#define CHAR_CR '\r' /* 0x0D */ +#define CHAR_LF '\n' /* 0x0A */ + +#define EXT_REG_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) /* Write by register address */ +#define EXT_REG_READ(addr, val) ((val) = *(volatile unsigned int *)(addr)) /* Read by register address */ +#define EXT_REG_READ32(addr) (*(volatile unsigned int *)(addr)) +#define EXT_REG_WRITE32(addr, val) (*(volatile unsigned int *)(addr) = (val)) +#define EXT_REG_WRITE_MASK(addr, val, mask) (*(volatile unsigned int *)((addr) & 0xFFFFFFFC) = \ + ((*(volatile unsigned int *)((addr)& 0xFFFFFFFC)) & (~(mask))) | ((val) & (mask))) +#define EXT_REG_TOOLWRITE(addr, val) (*(volatile unsigned int *)((addr) & 0xFFFFFFFC) = (val)) +#define EXT_REG_TOOLREAD(addr, val) ((val) = *(volatile unsigned int *)((addr) & 0xFFFFFFFC)) + +#define ABS(x) (((x) >= 0) ? (x) : -(x)) +#define MAX(a, b) (((a) >= (b)) ? (a) : (b)) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define CLIP(a) (((a) >= 0) ? (a) : 0) +#define CLIP2(m, n, a) (((a) > (m)) ? (m) : ((a) < (n) ? (n) : (a))) +#define CLIP3(low, high, x) (MAX(MIN((x), high), low)) +#define RSHFT(x, n) ((x) >= 1 ? \ + (((x) + (1 << ((n)-1))) >> (n)) : (-(((-(x)) + (1 << ((n)-1))) >> (n)))) + +#define ROUND_UP(x, align) (((x) + (align)-1) & ~((align)-1)) +#define ROUND_DOWN(x, align) ((x) & (~((align) - 1))) + +#define EXT_FENCE(void) do { \ + __asm__("fence\n\r"); \ +} while (0) +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ +/** + * @} + */ + +/** + * @} + */ +#endif /* __EXT_COMMON_H__ */ + diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/config.h b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/config.h new file mode 100644 index 0000000000000000000000000000000000000000..573eaa740ac7a203f9ae78031f6869fe11b32701 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/config.h @@ -0,0 +1,114 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file config.h + * @author MCU Driver Team + * @brief Header file containing functions prototypes of config module. + * + Initialization and de-initialization functions + * + Format config function + */ +#ifndef CONFIG_H +#define CONFIG_H + + +#include "module.h" +#include "type.h" +#include "typedefs.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C"{ +#endif +#endif /* __cplusplus */ + + +#define DATA_ITEM_MAX_LEN 256 /* maximum length of data items */ + +enum DataItem { + DATA_ITEM_EVENT, + DATA_ITEM_NUM_MAX, +}; + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup CONFIG_Def CONFIG_Def + * @brief Content read/write. + * @{ + */ + +/** + * @brief load_read Reads the content in the configuration address based on the address + * @attention None + * + * @param add [IN] Indicates the address to be read + * @param value [OUT] read content + * @param len [OUT] Length of the read content + * @retval None + */ +void ExtLoadRead(uintptr_t add, char *value, int len); + +/** + * @extLoadWrite Write the content in the configuration address according to the address + * @attention None + * + * @param add [IN] Address to be written + * @param value [IN] What is written + * @param len [IN] Length of the content to be written + * @retval None + */ +void ExtLoadWrite(uintptr_t add, const char *value, int len); + +/** + * @extConfigRead Reads content based on data items + * @attention None + * + * @param item [IN] Read Data Items + * @param value [OUT] Read content + * @param len [OUT] Length of the read content + * @retval None + */ +void ExtConfigRead(enum DataItem item, char *value, int len); + +/** + * @brief load_write Write content based on data items + * @attention Nonw + * + * @param item [IN] Data Items Written + * @param value [IN] Contents of write + * @param len [IN] Length of the content to be written + * @retval None + */ +void ExtConfigWrite(enum DataItem item, const char *value, int len); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ +/** + * @} + */ + +/** + * @} + */ +#endif /* __EXT_DEBUG_H__ */ diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/console.h b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/console.h new file mode 100644 index 0000000000000000000000000000000000000000..d870fd981997a0e12826627eb516f78b5de0611f --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/console.h @@ -0,0 +1,73 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file console.h + * @author MCU Driver Team + * @brief Header file containing functions prototypes of console module. + * + Initialization and de-initialization functions + * + Format console function + */ +#ifndef CONSOLE_H +#define CONSOLE_H + +#include "uart.h" + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup CONSOLE_Def CONSOLE_Def + * @brief Serial port printing initialization. + * @{ + */ + + /** + * @brief Read Status Query + * @{ + */ +int ConsoleGetQuery(void); + /** + * @brief Read a single character + * @{ + */ +int ConsoleGetc(void); + /** + * @brief Output String + * @{ + */ +int ConsolePuts(const char *str); + /** + * @brief Output Characters + * @{ + */ +void ConsolePutc(const char c); +/* Format print function */ +int UartPrintf(const char *format, ...); + +/* init console uart */ +void ConsoleInit(UART_Handle uart); +/** + * @} + */ + +/** + * @} + */ +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/dfx_debug.h b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/dfx_debug.h new file mode 100644 index 0000000000000000000000000000000000000000..69d44fb913539743b343396d7b8d75960d77b733 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/dfx_debug.h @@ -0,0 +1,74 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dfx_debug.h + * @author MCU Driver Team + * @brief Header file containing functions prototypes of DFX_DEBUG module. + * + Initialization and de-initialization functions + * + Format DFX_DEBUG function + */ +#ifndef DFX_DEBUG_H +#define DFX_DEBUG_H + +#include "module.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* __cplusplus */ + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup DFX_DEBUG_Def DFX_DEBUG_Def + * @brief Setting the Debug Mode. + * @{ + */ + +enum ExtDebugMode { + DEBUG, + RUNNING +}; +/** + * @brief extSetDebugMode + * @attention None + * + * @param ExtDebugMode [IN] Operation mode + * @retval None + */ +void ExtSetDebugMode(enum ExtDebugMode mode); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DFX_DEBUG_H */ diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/dfx_log.h b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/dfx_log.h new file mode 100644 index 0000000000000000000000000000000000000000..bbb51567b71a6c75aceca8082aa0d3b172dce1b0 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/dfx_log.h @@ -0,0 +1,142 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dfx_log.h + * @author MCU Driver Team + * @brief dfx_log module driver + * @details The header file contains the following declaration: + * + Perhaps and print the log content. + */ +#ifndef DFX_LOG_H +#define DFX_LOG_H + +#include "ext_log.h" + +#ifdef __cplusplus__ +#if __cplusplus__ +extern "C" { +#endif +#endif + +#define LOG_UINT_MAX_LEN 512 +#define LOG_MEM_POOL_MAX_LEN 1024 +#define LOG_LAST_WORD_MAX_LEN 1024 + +#define LOG_STATEMENT_MAX_LEN 20 + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup DFX_LOG_Def DFX_LOG_Def + * @brief Initialization of Miniaturized Logs. + * @{ + */ + +struct MemoryLog { + unsigned char enable; + unsigned char mmzBuf[LOG_MEM_POOL_MAX_LEN]; + unsigned int writePos; + unsigned int logLen; +}; +struct SysLogCtx { + unsigned char init; + char **modStr; + enum ExtLogLevel logLevel[EXT_MODULE_BUTT]; + struct MemoryLog memLog; +}; +struct SysDebugSwitch { + unsigned char enable; + struct SysLogCtx logCtx; +}; + +/** + * @brief get log context. + * @attention None + * + * @retval struct SysLogCtx *. + */ +struct SysLogCtx *GetLogCtx(void); + +/** + * @brief init log context. + * @attention None + * + * @param ctx: Pointer to the SysLogCtx structure to be initialized. + * @retval None + */ +void LogCtxInit(struct SysLogCtx *ctx); + +/** + * @brief init struct MemoryLog. + * @attention None + * + * @param memData: Pointer to the MemoryLog structure to be initialized + * @retval None + */ +void InitMemoryData(struct MemoryLog *memData); + +/** + * @brief get debug switch. + * @attention None + * + * @retval struct SysDebugSwitch *. + */ +struct SysDebugSwitch *GetDebugSwitch(void); + +/** + * @brief get memory data. + * @attention None + * + * @retval struct MemoryLog *. + */ +struct MemoryLog *GetMemoryData(void); + +/** + * @brief Register the dfx cmd + * @attention None + * + * @retval None + */ +void DfxCmdRegister(void); + +/** + * @brief get version info cmd + * @attention None + * + * @param argc: Number of input parameters. + * @param argv: Array of pointers + * @retval Return the setting result, success or failure. + */ +int CmdGetVersionInfo(void); + +#ifdef __cplusplus__ +#if __cplusplus__ +} +#endif +#endif /* end of __cplusplus */ +/** + * @} + */ + +/** + * @} + */ +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/errno.h b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/errno.h new file mode 100644 index 0000000000000000000000000000000000000000..df88fbf374587771b2c9d8b3e12351c3168c24bd --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/errno.h @@ -0,0 +1,65 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file errno.h + * @author MCU Driver Team + * @brief Header file containing functions prototypes of erron module. + * + Initialization and de-initialization functions + * + Format erron function + */ +#ifndef ERRNO_H +#define ERRNO_H + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* __cplusplus */ + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup ERRNO_Def ERRNO_Def + * @brief Define the success flag. + * @{ + */ + +/* Customize the required return value */ +typedef enum { + EXT_SUCCESS = 0x0, + EXT_ERR_USER_BUSY = 0x01060002, + EXT_INVALID = 0xFFFFFFFE, + EXT_FAILURE = 0xFFFFFFFF, +} EXT_MCU_ERRNO; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ +/** + * @} + */ + +/** + * @} + */ +#endif /* __EXT_ERRNO_H__ */ diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/event.h b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/event.h new file mode 100644 index 0000000000000000000000000000000000000000..7d7482e4429cf74763472b5c3ec96d86b499816a --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/event.h @@ -0,0 +1,143 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file event.h + * @author MCU Driver Team + * @brief Header file containing functions prototypes of erron module. + * + Defines the function of reporting initialization events. + */ +#ifndef EVENT_CODE_H +#define EVENT_CODE_H + +#include "module.h" +#include "type.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C"{ +#endif +#endif /* __cplusplus */ + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup EVENT_Def EVENT_Def + * @brief Definition of the Event Reporting Function. + * @{ + */ + +#define SYS_GPIO_GROUP_REPORT 0 +#define USER_CMD_MAX_LEN 8 +#define EVENT_MAX_LEN 5 + +#define REPORT_EVENT_DONE 0xFFFFFFFF + + +typedef enum { + REPORT_LAST_WORD_EVENT, +} REPORT_EVENT; + +typedef enum { + BUS_SLAVE_IRQ_INT_WRITE_START, + BUS_SLAVE_IRQ_INT_WRITE_END, + BUS_SLAVE_IRQ_INT_READ_START, + BUS_SLAVE_IRQ_INT_READ_END, + BUS_SLAVE_IRQ_PGM_WRITE_START, + BUS_SLAVE_IRQ_PGM_WRITE_END, + BUS_SLAVE_IRQ_PGM_READ_START, + BUS_SLAVE_IRQ_PGM_READ_END, + BUS_SLAVE_IRQ_INT_FIFO, + BUS_SLAVE_IRQ_EXCEPTION, + BUS_SLAVE_IRQ_BUTT +} BUSS_IRQ_Type; + +typedef struct { + unsigned short cmd; /* Commands delivered by the user */ + unsigned char ack; + unsigned char len; + unsigned char param[USER_CMD_MAX_LEN]; +} UserCmd; + +typedef void (*pfnCB)(unsigned int); + +typedef enum { + DATA_TYPE_NOISE, DATA_TYPE_SELF, DATA_TYPE_STYLUS, DATA_TYPE_MUTUAL +} DataType; + +typedef struct { + unsigned char eventType; + unsigned char ack; + unsigned char len; + unsigned char param[EVENT_MAX_LEN]; +} McuEvent; + +typedef struct { + unsigned int reportType; /* Report Type */ + McuEvent event; +} McuReport; + +typedef struct { + McuReport report; + pfnCB pfnevent; +} UserEventObj; + +typedef struct { + unsigned int reportLock; + int gpioHandle; + unsigned int reportAddr; + unsigned short cmdNotFoudCount; + unsigned short reportFailedCount; + UserEventObj eventObj; + UserCmd cmd; +} UserMgr; + +/** + * @brief report event + * @attention None + * + * @param report event struct + * @retval The return value indicates that the event is reported successfully or failed. + */ +int UserReportEvent(UserEventObj *eventObj); + +/** + * @brief init event + * @attention None + * + * @retval The return value indicates that the event is reported successfully or failed. + */ +int EventInit(void); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __EXT_DEBUG_H__ */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/ext_log.h b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/ext_log.h new file mode 100644 index 0000000000000000000000000000000000000000..1a211d0d9415e0d51ed8a5ccb114926cdb726dc6 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/ext_log.h @@ -0,0 +1,275 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file ext_loh.h + * @author MCU Driver Team + * @brief log module driver + * @details The header file contains the following declaration: + * + Definition of the Miniaturized Log Structure + * + Definition of Miniaturized Log Output Functions + */ +#ifndef EXT_LOG_H +#define EXT_LOG_H + +#include "module.h" +#include "console.h" +#include "file_id_defs.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C"{ +#endif +#endif /* __cplusplus */ + +/* Serial port print definition */ +#define EXT_PRINT UartPrintf +/** + * @brief Initializing the Log Output Level + */ +enum ExtLogLevel { + EXT_LOG_LEVEL_FATAL, + EXT_LOG_LEVEL_ERROR, + EXT_LOG_LEVEL_WARNING, + EXT_LOG_LEVEL_INFO, + EXT_LOG_LEVEL_DBG, + EXT_LOG_LEVEL_BUTT, +}; + +enum ExtLogLevelToken { + FATAL, + ERR, + WARN, + INFO, + DBG, +}; +#define MAKE_XML_ID_UINT32(a, b) ((unsigned int)(((unsigned short)(a)) | ((unsigned int)((unsigned short)(b))) << 16)) + +#define EXT_FATAL_PRINT(modId, fmt...) +#define EXT_ERR_PRINT(modId, fmt...) UartPrintf(fmt) +#define EXT_WARN_PRINT(modId, fmt...) +#define EXT_INFO_PRINT(modId, fmt...) UartPrintf(fmt) +#define EXT_DBG_PRINT(modId, fmt...) + +#ifndef CFG_DFX_MINILOG_SUPPORT +#define CFG_DFX_MINILOG_SUPPORT 1 +#endif + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup EXT_LOG_Def EXT_LOG_Def + * @brief Interface for Printing Miniaturized Logs. + * @{ + */ + +/** + * @defgroup Various types of miniaturized log output + * @brief log output external module. + * @{ + */ +int ExtDrvLogOutBuf(enum ExtLogLevel level, enum ExtModule modId, unsigned int xmlId, + const unsigned int* logBuf, unsigned short logBufLen); +int ExtDrvLogOut0(enum ExtLogLevel level, enum ExtModule modId, unsigned int xmlId); +int ExtDrvLogOut1(enum ExtLogLevel level, enum ExtModule modId, unsigned int xmlId, unsigned int d0); +int ExtDrvLogOut2(enum ExtLogLevel level, enum ExtModule modId, unsigned int xmlId, unsigned int d0, unsigned int d1); +int ExtDrvLogOut3(enum ExtLogLevel level, enum ExtModule modId, unsigned int xmlId, unsigned int d0, unsigned int d1, + unsigned int d2); + +/** + * @defgroup Printing and outputting miniaturized logs + * @brief log output external module. + * @{ + */ +int ExtDrvLogSetLogLevel(enum ExtModule modId, enum ExtLogLevel level); +int ExtDrvLogOutFmt(enum ExtLogLevel level, enum ExtModule id, const char *fmt, ...); + +#ifndef EXT_LOG_LEVEL +#define EXT_LOG_LEVEL EXT_LOG_LEVEL_DBG +#endif +#define EXT_LOG_0(level, modId, msg) LOG_##level##_0(modId, msg) +#define EXT_LOG_1(level, modId, msg, d0) LOG_##level##_1(modId, msg, d0) +#define EXT_LOG_2(level, modId, msg, d0, d1) LOG_##level##_2(modId, msg, d0, d1) +#define EXT_LOG_3(level, modId, msg, d0, d1, d2) LOG_##level##_3(modId, msg, d0, d1, d2) +#define EXT_LOG_BUF(level, modId, msg, logBuf, logBufLen) LOG_##level##_BUF(modId, msg, logBuf, logBufLen) + +#ifdef MAKE_PRIM_XML_PROCESS_IN + +#define LOG_FATAL_0(modId, msg) \ + { \ + _PRIM_ST_, _PRIM_PRI_ = 0, _PRIM_MSG_ = msg, _PRIM_LINE_ = __LINE__, \ + _PRIM_FILE_ID_ = __FILE_IDX__, _PRIM_MOD_ID_ = modId, _PRIM_END_ \ + } +#define LOG_FATAL_1(modId, msg, d0) LOG_FATAL_0(modId, msg) +#define LOG_FATAL_2(modId, msg, d0, d1) LOG_FATAL_0(modId, msg) +#define LOG_FATAL_3(modId, msg, d0, d1, d2) LOG_FATAL_0(modId, msg) +#define LOG_FATAL_BUF(modId, msg, logBuf, logBufLen) LOG_FATAL_0(modId, msg) +#define LOG_LAST_WORD_BUF(modId, msg, logBuf, logBufLen) LOG_FATAL_0(modId, msg) + + +#define LOG_ERR_0(modId, msg) \ + { \ + _PRIM_ST_, _PRIM_PRI_ = 1, _PRIM_MSG_ = msg, _PRIM_LINE_ = __LINE__, \ + _PRIM_FILE_ID_ = __FILE_IDX__, _PRIM_MOD_ID_ = modId, _PRIM_END_ \ + } +#define LOG_ERR_1(modId, msg, d0) LOG_ERR_0(modId, msg) +#define LOG_ERR_2(modId, msg, d0, d1) LOG_ERR_0(modId, msg) +#define LOG_ERR_3(modId, msg, d0, d1, d2) LOG_ERR_0(modId, msg) +#define LOG_ERR_BUF(modId, msg, logBuf, logBufLen) LOG_ERR_0(modId, msg) + +#define LOG_WARN_0(modId, msg) \ + { \ + _PRIM_ST_, _PRIM_PRI_ = 2, _PRIM_MSG_ = msg, _PRIM_LINE_ = __LINE__, \ + _PRIM_FILE_ID_ = __FILE_IDX__, _PRIM_MOD_ID_ = modId, _PRIM_END_ \ + } +#define LOG_WARN_1(modId, msg, d0) LOG_WARN_0(modId, msg) +#define LOG_WARN_2(modId, msg, d0, d1) LOG_WARN_0(modId, msg) +#define LOG_WARN_3(modId, msg, d0, d1, d2) LOG_WARN_0(modId, msg) +#define LOG_WARN_BUF(modId, msg, logBuf, logBufLen) LOG_WARN_0(modId, msg) + +#define LOG_INFO_0(modId, msg) \ + { \ + _PRIM_ST_, _PRIM_PRI_ = 3, _PRIM_MSG_ = msg, _PRIM_LINE_ = __LINE__, \ + _PRIM_FILE_ID_ = __FILE_IDX__, _PRIM_MOD_ID_ = modId, _PRIM_END_ \ + } +#define LOG_INFO_1(modId, msg, d0) LOG_INFO_0(modId, msg) +#define LOG_INFO_2(modId, msg, d0, d1) LOG_INFO_0(modId, msg) +#define LOG_INFO_3(modId, msg, d0, d1, d2) LOG_INFO_0(modId, msg) +#define LOG_INFO_BUF(modId, msg, logBuf, logBufLen) LOG_INFO_0(modId, msg) + +#define LOG_DBG_0(modId, msg) \ + { \ + _PRIM_ST_, _PRIM_PRI_ = 4, _PRIM_MSG_ = msg, _PRIM_LINE_ = __LINE__, \ + _PRIM_FILE_ID_ = __FILE_IDX__, _PRIM_MOD_ID_ = modId, _PRIM_END_ \ + } +#define LOG_DBG_1(modId, msg, d0) LOG_DBG_0(modId, msg) +#define LOG_DBG_2(modId, msg, d0, d1) LOG_DBG_0(modId, msg) +#define LOG_DBG_3(modId, msg, d0, d1, d2) LOG_DBG_0(modId, msg) +#define LOG_DBG_BUF(modId, msg, logBuf, logBufLen) LOG_DBG_0(modId, msg) + +#else + +#define MAKE_XML_ID_UINT32(a, b) ((unsigned int)(((unsigned short)(a)) | ((unsigned int)((unsigned short)(b))) << 16)) + +#define LOG_0(level, modId, msg) \ + ExtDrvLogOut0(level, modId, MAKE_XML_ID_UINT32(__LINE__, THIS_FILE_ID)) +#define LOG_1(level, modId, msg, d0) \ + ExtDrvLogOut1(level, modId, MAKE_XML_ID_UINT32(__LINE__, THIS_FILE_ID), d0) +#define LOG_2(level, modId, msg, d0, d1) \ + ExtDrvLogOut2(level, modId, MAKE_XML_ID_UINT32(__LINE__, THIS_FILE_ID), d0, d1) +#define LOG_3(level, modId, msg, d0, d1, d2) \ + ExtDrvLogOut3(level, modId, MAKE_XML_ID_UINT32(__LINE__, THIS_FILE_ID), d0, d1, d2) + +#if CFG_DFX_MINILOG_SUPPORT +#define LOG_FATAL_0(modId, msg) \ + LOG_0(EXT_LOG_LEVEL_FATAL, modId, msg) +#define LOG_FATAL_1(modId, msg, d0) \ + LOG_1(EXT_LOG_LEVEL_FATAL, modId, msg, d0) +#define LOG_FATAL_2(modId, msg, d0, d1) \ + LOG_2(EXT_LOG_LEVEL_FATAL, modId, msg, d0, d1) +#define LOG_FATAL_3(modId, msg, d0, d1, d2) \ + LOG_3(EXT_LOG_LEVEL_FATAL, modId, msg, d0, d1, d2) +#define LOG_ERR_0(modId, msg) \ + LOG_0(EXT_LOG_LEVEL_ERROR, modId, msg) +#define LOG_ERR_1(modId, msg, d0) \ + LOG_1(EXT_LOG_LEVEL_ERROR, modId, msg, d0) +#define LOG_ERR_2(modId, msg, d0, d1) \ + LOG_2(EXT_LOG_LEVEL_ERROR, modId, msg, d0, d1) +#define LOG_ERR_3(modId, msg, d0, d1, d2) \ + LOG_3(EXT_LOG_LEVEL_ERROR, modId, msg, d0, d1, d2) +#define LOG_WARN_0(modId, msg) \ + LOG_0(EXT_LOG_LEVEL_WARNING, modId, msg) +#define LOG_WARN_1(modId, msg, d0) \ + LOG_1(EXT_LOG_LEVEL_WARNING, modId, msg, d0) +#define LOG_WARN_2(modId, msg, d0, d1) \ + LOG_2(EXT_LOG_LEVEL_WARNING, modId, msg, d0, d1) +#define LOG_WARN_3(modId, msg, d0, d1, d2) \ + LOG_3(EXT_LOG_LEVEL_WARNING, modId, msg, d0, d1, d2) +#define LOG_INFO_0(modId, msg) \ + LOG_0(EXT_LOG_LEVEL_INFO, modId, msg) +#define LOG_INFO_1(modId, msg, d0) \ + LOG_1(EXT_LOG_LEVEL_INFO, modId, msg, d0) +#define LOG_INFO_2(modId, msg, d0, d1) \ + LOG_2(EXT_LOG_LEVEL_INFO, modId, msg, d0, d1) +#define LOG_INFO_3(modId, msg, d0, d1, d2) \ + LOG_3(EXT_LOG_LEVEL_INFO, modId, msg, d0, d1, d2) +#define LOG_DBG_0(modId, msg) \ + LOG_0(EXT_LOG_LEVEL_DBG, modId, msg) +#define LOG_DBG_1(modId, msg, d0) \ + LOG_1(EXT_LOG_LEVEL_DBG, modId, msg, d0) +#define LOG_DBG_2(modId, msg, d0, d1) \ + LOG_2(EXT_LOG_LEVEL_DBG, modId, msg, d0, d1) +#define LOG_DBG_3(modId, msg, d0, d1, d2) \ + LOG_3(EXT_LOG_LEVEL_DBG, modId, msg, d0, d1, d2) +#else +#define LOG_FATAL_0(modId, fmt...) ExtDrvLogOutFmt(EXT_LOG_LEVEL_FATAL, modId, fmt) +#define LOG_FATAL_1(modId, fmt...) LOG_FATAL_0(modId, fmt) +#define LOG_FATAL_2(modId, fmt...) LOG_FATAL_0(modId, fmt) +#define LOG_FATAL_3(modId, fmt...) LOG_FATAL_0(modId, fmt) +#define LOG_ERR_0(modId, fmt...) ExtDrvLogOutFmt(EXT_LOG_LEVEL_ERROR, modId, fmt) +#define LOG_ERR_1(modId, fmt...) LOG_ERR_0(modId, fmt) +#define LOG_ERR_2(modId, fmt...) LOG_ERR_0(modId, fmt) +#define LOG_ERR_3(modId, fmt...) LOG_ERR_0(modId, fmt) +#define LOG_WARN_0(modId, fmt...) ExtDrvLogOutFmt(EXT_LOG_LEVEL_WARNING, modId, fmt) +#define LOG_WARN_1(modId, fmt...) LOG_WARN_0(modId, fmt) +#define LOG_WARN_2(modId, fmt...) LOG_WARN_0(modId, fmt) +#define LOG_WARN_3(modId, fmt...) LOG_WARN_0(modId, fmt) +#define LOG_INFO_0(modId, fmt...) ExtDrvLogOutFmt(EXT_LOG_LEVEL_INFO, modId, fmt) +#define LOG_INFO_1(modId, fmt...) LOG_INFO_0(modId, fmt) +#define LOG_INFO_2(modId, fmt...) LOG_INFO_0(modId, fmt) +#define LOG_INFO_3(modId, fmt...) LOG_INFO_0(modId, fmt) +#define LOG_DBG_0(modId, fmt...) ExtDrvLogOutFmt(EXT_LOG_LEVEL_DBG, modId, fmt) +#define LOG_DBG_1(modId, fmt...) LOG_DBG_0(modId, fmt) +#define LOG_DBG_2(modId, fmt...) LOG_DBG_0(modId, fmt) +#define LOG_DBG_3(modId, fmt...) LOG_DBG_0(modId, fmt) +#endif + +#define LOG_BUF(level, modId, msg, logBuf, logBufLen) \ + ExtDrvLogOutBuf(level, modId, MAKE_XML_ID_UINT32(__LINE__, THIS_FILE_ID), logBuf, logBufLen) + + +#define LOG_FATAL_BUF(modId, msg, logBuf, logBufLen) \ + LOG_BUF(EXT_LOG_LEVEL_FATAL, modId, msg, logBuf, logBufLen) +#define LOG_ERR_BUF(modId, msg, logBuf, logBufLen) \ + LOG_BUF(EXT_LOG_LEVEL_ERROR, modId, msg, logBuf, logBufLen) +#define LOG_WARN_BUF(modId, msg, logBuf, logBufLen) \ + LOG_BUF(EXT_LOG_LEVEL_WARNING, modId, msg, logBuf, logBufLen) +#define LOG_INFO_BUF(modId, msg, logBuf, logBufLen) \ + LOG_BUF(EXT_LOG_LEVEL_INFO, modId, msg, logBuf, logBufLen) +#define LOG_DBG_BUF(modId, msg, logBuf, logBufLen) \ + LOG_BUF(EXT_LOG_LEVEL_DBG, modId, msg, logBuf, logBufLen) + +#endif + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __EXT_DEBUG_H__ */ diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/file_id_defs.h b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/file_id_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..b1005a51f8c2b53f5243d11420d2c639078cd2d2 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/file_id_defs.h @@ -0,0 +1,63 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file file_id_defs.h + * @author MCU Driver Team + * @brief file id module driver + * @details The header file contains the following declaration: + * +Definition of miniaturized log event IDs + */ +#ifndef FILE_ID_DEFS_H +#define FILE_ID_DEFS_H + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup FILE_ID_DEFS_Def FILE_ID_DEFS_Def + * @brief Define source files and ID. + * @{ + */ + +typedef enum { + FILE_ID_LOG_C = 2001, /* this is a test sample */ +} file_id_enum; + +#ifdef __cplusplus +#if __cplusplus + } +#endif +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* FILE_ID_DEFS_H */ diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/log.h b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/log.h new file mode 100644 index 0000000000000000000000000000000000000000..70653a310203f583776c9ff15bf47fb1b7959c83 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/log.h @@ -0,0 +1,146 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file log.h + * @author MCU Driver Team + * @brief log module driver + * @details The header file contains the following declaration: + * + Definition of log level settings for miniaturization. + * + Output of miniaturized logs based on different conditions. + */ +#ifndef LOG_H +#define LOG_H + +#include "ext_log.h" +#include "module.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C"{ +#endif +#endif /* __cplusplus */ + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup LOG_Def LOG_Def + * @brief Printing miniaturized logs. + * @{ + */ + +/** + * @brief Set Log Level. + * @attention None + * + * @param id [IN] ID of the module whose log level is to be set, which is defined by ExtModule. + * @param logLevel [IN] Log level, which is defined by ExtLogLevel. + * @retval int Whether the setting is successful + */ +int ExtSetLogLevel(enum ExtModule id, enum ExtLogLevel logLevel); + +/** + * @brief Used to report the content of a specified buffer to the message interface of the PC tool. + * @attention None + * + * @param logLevel [IN] Log level, which is defined by ExtLogLevel. + * @param modId [IN] Module ID, which is planned in advance based on the service scenario. + * @param msg [IN] The value is a character string constant and does not support carriage returns. + * The current version does not support parameter formatting. Only the character string is displayed. + * @param log_buf[IN] Log buffer + * @param log_buf_len[IN] Length of the log buffer, in bytes + * + * @retval None + */ +#define ExtLogBuf(logLevel, modId, msg, logBuf, logBufLen) EXT_LOG_BUF(logLevel, modId, msg, logBuf, logBufLen) + +/** + * @brief extLog0,Output logs without variables + * @attention None + * + * @param logLevel [IN] Log level, which is defined by ExtLogLevel + * @param modId [IN] Module ID, which is planned in advance based on the service scenario. + * @param msg [IN] The value is a character string constant and does not support carriage returns. + * The current version does not support parameter formatting. Only the character string is displayed. + * + * @retval None + */ +#define ExtLog0(logLevel, modId, msg) EXT_LOG_0(logLevel, modId, msg) + +/** + * @brief Logs with one int value are output + * @attention None + * + * @param logLevel [IN] Log level, which is defined by ExtLogLevel + * @param modId [IN] Module ID, which is planned in advance based on the service scenario. + * @param msg [IN] The value is a character string constant and does not support carriage returns. + * The current version does not support parameter formatting. Only the character string is displayed. + * @param d0 [IN] Variable of the unsigned int type + * + * @retval None + */ +#define ExtLog1(logLevel, modId, msg, d0) EXT_LOG_1(logLevel, modId, msg, d0) + +/** + * @brief Logs with two int values are output. + * @attention None + * + * @param logLevel [IN] Log level, which is defined by ExtLogLevel + * @param modId [IN] Module ID, which is planned in advance based on the service scenario. + * @param msg [IN] The value is a character string constant and does not support carriage returns. + * The current version does not support parameter formatting. Only the character string is displayed. + * @param d0 [IN] Variable of the unsigned int type + * @param d1 [IN] Variable of the unsigned int type + * + * @retval None + */ +#define ExtLog2(logLevel, modId, msg, d0, d1) EXT_LOG_2(logLevel, modId, msg, d0, d1) + +/** + * @brief Logs with three int values are output + * @attention None + * + * @param logLevel [IN] Log level, which is defined by ExtLogLevel + * @param modId [IN] Module ID, which is planned in advance based on the service scenario. + * @param msg [IN] The value is a character string constant and does not support carriage returns. + * The current version does not support parameter formatting. Only the character string is displayed. + * @param d0 [IN] Variable of the unsigned int type + * @param d1 [IN] Variable of the unsigned int type + * @param d2 [IN] Variable of the unsigned int type + * + * @retval None + */ +#define ExtLog3(logLevel, modId, msg, d0, d1, d2) EXT_LOG_3(logLevel, modId, msg, d0, d1, d2) + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __EXT_DEBUG_H__ */ diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/module.h b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/module.h new file mode 100644 index 0000000000000000000000000000000000000000..ca565e1f73f6571c8a46a3c330d13a222d8ae03e --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/module.h @@ -0,0 +1,96 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mpdule.h + * @author MCU Driver Team + * @brief Definition of the Miniaturized Log Module + * @details The header file contains the following declaration: + * + Definition of the ID of the miniaturized log module + */ +#ifndef MODULE_H +#define MODULE_H + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* __cplusplus */ + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup MODULE_Def MODULE_Def + * @brief define the device model. + * @{ + */ + +/* * Module ID flags */ +enum ExtModule { + EXT_MODULE_APP_MAIN, + EXT_MODULE_APP_CONSOLE, + EXT_MODULE_APP_CHIP, + EXT_MODULE_DRV_BASE, + EXT_MODULE_DRV_CHIPS, + EXT_MODULE_DRV_CRG, + EXT_MODULE_DRV_GPIO, + EXT_MODULE_DRV_I2C, + EXT_MODULE_DRV_IRQ, + EXT_MODULE_DRV_PINCTRL, + EXT_MODULE_DRV_TIMER, + EXT_MODULE_DRV_UART, + EXT_MODULE_DFX, + EXT_MODULE_BUTT +}; + +#define MODULE_ID_MASK 0xFF000000 +#define FEATURE_ID_MASK 0x00FF0000 +#define PARAM_USE_ID_MASK 0x0000FFFF + +#define MODULE_ID_OFFSET 0x18 +#define FEATURE_ID_OFFSET 0x10 +#define PARAM_USE_ID_OFFSET 0x8 + +#define SCENE_UINT_MAX_ID 0xFF + +#define SCENE_END_LABEL 0xABCDABCD + +#define STATE_CODE_MODULE_MASK 0x10 +#define STATE_CODE_MASK 0xFFFF0000 + +#define STATE_CODE(moduleId, stateCode) (moduleId << STATE_CODE_MODULE_MASK | (stateCode & STATE_CODE_MASK)) +#define STATE_CODE_ERR_CHECK(ret) ((ret & STATE_CODE_MASK) > EXT_RIGHT_UNKNOWN) +#define STATE_CODE_RIGHT_CHECK(ret) ((ret & STATE_CODE_MASK) <= EXT_RIGHT_UNKNOWN) + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __EXT__MODULE__ */ diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/type.h b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/type.h new file mode 100644 index 0000000000000000000000000000000000000000..2e4fdbfd3733bd9b6fc2c44fa4a02f4655c5cdcd --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/inc/type.h @@ -0,0 +1,73 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file type.h + * @author MCU Driver Team + * @brief type module driver + * @details The header file contains the following declaration: + * + Basic Data Type Definition + */ +#ifndef TYPE_H +#define TYPE_H + +#include "errno.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* __cplusplus */ + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup TYPE_Def TYPE_Def + * @brief define the return value type. + * @{ + */ + +/** + * @brief Basic Data Type Definition + */ +#ifndef NULL +#define NULL 0L +#endif +#define NULL_PTR ((void*)0) + +#define EXT_FALSE 0 +#define EXT_TRUE 1 + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __EXT_TYPE_H__ */ + diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/app_command.c b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/app_command.c new file mode 100644 index 0000000000000000000000000000000000000000..a512fcae2febd7498673f374609d3e29ff94587b --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/app_command.c @@ -0,0 +1,525 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file app_command.c + * @author MCU Driver Team + * @brief command module driver + * @details The header file contains the following declaration: + * + Receive and parse the command input through the serial port. + * + implementation of serial port output function + * + Key Character Detection + */ +#include +#include +#include "common.h" +#include "command.h" +#include "console.h" +#include "cmd_common.h" +#include "cmd.h" +#include "securec.h" + +typedef struct { + char ch; + char c; +} DirMapRes; + +/** + * @brief Command Input Keyword Initialization + */ +struct CmdInput { + char buf[CMD_BUF_MAX]; + size_t cursor; +}; + +/** + * @brief Initialize the command storage address. + */ +struct CmdRecord { + char cmdLogList[CMD_NUM_MAX][CMD_BUF_MAX]; + signed char max; + signed char addIdx; + signed char cur; +}; + +/** + * @brief Initialize the command sending variable. + */ +struct CmdCtx { + char cmdBuf[CMD_BUF_MAX]; + const char *argv[ARGS_NUM_MAX]; + unsigned char dirKeyLen; + char uartRxch; /* stores the characters */ + + struct CmdInput inputCmd; + struct CmdRecord cmdLog; +}; + +static struct CmdCtx g_cmdCtx = { 0 }; +static struct CmdCtx *AppCmdGetCtx(void) +{ + /* Initialize the structure value */ + return &g_cmdCtx; +} + +/** + * @brief Get Previous Command + * @param cmdLog: Commands from user + * @retval : Parse the subscript or error return value of a character string. + */ +static char *GetPreCmd(struct CmdRecord *cmdLog) +{ + if (cmdLog->max == 0) { /* Failed to initialize the maximum value */ + return NULL; + } + + if (cmdLog->max < CMD_NUM_MAX - 1) { + if (cmdLog->cur == 0) { + return NULL; + } + return cmdLog->cmdLogList[--cmdLog->cur]; + } + + if (cmdLog->cur == 0) { + if (cmdLog->addIdx == cmdLog->max) { + return NULL; + } + cmdLog->cur = cmdLog->max; + return cmdLog->cmdLogList[cmdLog->cur]; + } + + if (cmdLog->addIdx == cmdLog->cur - 1) { + return NULL; + } + return cmdLog->cmdLogList[--cmdLog->cur]; /* the pointer address is returned */ +} + +/** + * @brief Read the next command + * @param cmdLog: Commands from user + * @retval : Parse the subscript or error return value of a character string. + */ +static char *GetNextCmd(struct CmdRecord *cmdLog) +{ + if (cmdLog == NULL || cmdLog->max == 0) { /* Failed to initialize the maximum value */ + return NULL; + } + + if (cmdLog->max < CMD_NUM_MAX - 1) { + if (cmdLog->cur == cmdLog->max) { + return NULL; + } + return cmdLog->cmdLogList[++cmdLog->cur]; + } + + if (cmdLog->cur == cmdLog->max) { + if (cmdLog->addIdx == 0) { + return NULL; + } + cmdLog->cur = 0; + return cmdLog->cmdLogList[cmdLog->cur]; + } + + if (cmdLog->addIdx == cmdLog->cur + 1) { + return NULL; + } + return cmdLog->cmdLogList[++cmdLog->cur]; /* the pointer address is returned */ +} + +/** + * @brief Delete End Identifier + * @param inputcmd : Entered character string information. + * @retval None. + */ +static void CmdDeleteTailChar(struct CmdInput *inputCmd) +{ + if (inputCmd == NULL || inputCmd->cursor == 0) { + return; + } + /* Add a closing marker to a string */ + ConsolePutc(CTL_BACKSPACE); + ConsolePutc(SPACE_KEY); + ConsolePutc(CTL_BACKSPACE); + inputCmd->buf[--(inputCmd->cursor)] = '\0'; +} + +/** + * @brief Add a terminator at the end of a string + * @param inputcmd : Entered character string information. + * @retval None. + */ +static void CmdAddTailChar(struct CmdInput *inputCmd, char ch) +{ + if (inputCmd->cursor >= CMD_BUF_MAX - 1) { + return; + } + inputCmd->buf[(inputCmd->cursor)++] = ch; + /* Remove '\n' characters and add '\r\n' */ + ConsolePutc(ch); +} + +/** + * @brief Ignore the effects of key characters + * @param ch : Characters contained in the command + * @retval Indicates whether the implementation is successful. + */ +static unsigned char IgnoreCmdKey(char ch) +{ + /* end character and type character for the crt key */ + char ignoreKeys[] = {'\0', CTL_CH('a'), CTL_CH('b'), CTL_CH('e'), CTL_CH('f'), CTL_CH('x'), + CTL_CH('o'), CTL_CH('u')}; + + for (unsigned char i = 0; i < sizeof(ignoreKeys); i++) { + if (ch == ignoreKeys[i]) { + return EXT_TRUE; + } + } + return EXT_FALSE; +} + +/** + * @brief deleted Command Keys + * @param ch : Characters contained in the command + * @retval Indicates whether the implementation is successful. + */ +static unsigned char DeleteCmdKey(char ch) +{ + /* Backspace key delete key and other special key input */ + char deleteKeys[] = {DEL, DEL7, CTL_CH('h'), CTL_CH('d'), CTL_CH('k')}; + + for (unsigned char i = 0; i < sizeof(deleteKeys); i++) { + if (ch == deleteKeys[i]) { + return EXT_TRUE; + } + } + return EXT_FALSE; +} + +/** + * @brief Output Log Commands + * @param ch : Characters contained in the command + * @param cmdlog : Command log information + * @param input : Entering command information + * @retval None + */ +static void OutputLogCmd(struct CmdCtx *cmdCtx) +{ + char *cmd = NULL; + + cmd = (cmdCtx->uartRxch == CTL_CH('p')) ? GetPreCmd(&(cmdCtx->cmdLog)) : GetNextCmd(&(cmdCtx->cmdLog)); + /* If the value is empty, direct returned */ + if (cmd == NULL) { + return; + } + + /* Clears the array of characters */ + while (cmdCtx->inputCmd.cursor) { + CmdDeleteTailChar(&(cmdCtx->inputCmd)); + } + if (strncpy_s(cmdCtx->inputCmd.buf, CMD_BUF_MAX, cmd, strlen(cmd)) != EXT_SUCCESS) { + APP_CMD_ERR_PRINT("backup logcmd err\n"); + return; + } + /* Update pointer coordinates */ + cmdCtx->inputCmd.cursor = strlen(cmdCtx->inputCmd.buf); + EXT_PRINT("%s", cmdCtx->inputCmd.buf); +} + +/** + * @brief Output log commands + * @param cmd : Command string + * @param cmdlog : Command log information + * @retval Indicates whether the implementation is successful + */ +static int RecordCmd(const char *cmd, struct CmdRecord *cmdLog) +{ + /* not record uart switch cmd */ + if (strncmp(cmd, UART_SWITCH_CMD, strlen(UART_SWITCH_CMD)) == 0) { + return EXT_SUCCESS; + } + + /* clear buf and copy cmd to buf */ + memset_s(cmdLog->cmdLogList[cmdLog->addIdx], CMD_BUF_MAX, 0, CMD_BUF_MAX); + if (strncpy_s(cmdLog->cmdLogList[cmdLog->addIdx], CMD_BUF_MAX, cmd, strlen(cmd)) != EXT_SUCCESS) { + return EXT_FAILURE; + } + cmdLog->addIdx = (cmdLog->addIdx + 1) % CMD_NUM_MAX; + cmdLog->max = (cmdLog->addIdx > cmdLog->max) ? cmdLog->addIdx : cmdLog->max; + cmdLog->cur = cmdLog->addIdx; + return EXT_SUCCESS; +} + +/** + * @brief Clear the command and initialize the address + * @param inputCmd : Entering command information + * @retval None + */ +static void CleanInputCmd(struct CmdCtx *cmdCtx) +{ + /* the address pointer points to the start address */ + cmdCtx->inputCmd.buf[0] = '\0'; + cmdCtx->inputCmd.cursor = 0; + ConsolePuts("\n$ "); +} + +/** + * @brief Parse the arrow keys in the command. + * @param ch : Characters entered + * @param dirKeyLen : Arrow key flag + * @retval end character or non-direction character entered + */ +static char CmdDirectionKey(char ch, unsigned char *dirKeyLen) +{ + char c = '\0'; + DirMapRes dirMap[5] = { + /* Dir chd have 5 */ + {'D', CTL_CH('b')}, /* left key, convert to ctrl + b */ + {'C', CTL_CH('f')}, /* right key, convert to ctrl + c */ + {'H', CTL_CH('a')}, /* Home key, convert to ctrl + a */ + {'A', CTL_CH('p')}, /* up arrow, convert to ctrl + p */ + {'B', CTL_CH('n')} /* down arrow, convert to ctrl + n */ + }; + + if (*dirKeyLen == 0) { + if (ch == DIR_KEY_HEAD) { + *dirKeyLen = 1; + return c; + } + return ch; + } + + if (*dirKeyLen == 1) { + *dirKeyLen = (ch == '[') ? 2 : 0; /* 2 is directionKeyLen */ + return c; + } + + /* handle the third char sended by direction key */ + for (unsigned char i = 0; i < sizeof(dirMap) / sizeof(DirMapRes); i++) { + if (ch == dirMap[i].ch) { + c = dirMap[i].c; + break; + } + } + *dirKeyLen = 0; + return c; +} + +/** + * @brief tabkey alignment implementation + * @param res : Entered string + * @param inputCmd : Entering command information + * @retval None + */ +static void CompletesTabKey(const char *res, struct CmdInput *inputCmd) +{ + if (res == NULL || inputCmd == NULL) { + APP_CMD_ERR_PRINT("param err\n"); + return; + } + /* Obtains the array length */ + size_t len = strlen(res); + + while (len > inputCmd->cursor && inputCmd->cursor < CMD_BUF_MAX) { + /* Output Characters */ + ConsolePutc(res[inputCmd->cursor]); + + inputCmd->buf[inputCmd->cursor] = res[inputCmd->cursor]; + inputCmd->cursor++; + } +} + +/** + * @brief tabkey alignment implementation + * @param inputCmd : Entering command information + * @retval None + */ +static void CmdTabKey(struct CmdCtx *cmdCtx) +{ + const char* res[MATCH_CMD_BUF_CNT] = { NULL }; + /* Numeric element initialization */ + unsigned char findCnt = 0; + unsigned char cycle = 0; + unsigned int tailId = 0; + unsigned char searchFinish = EXT_TRUE; + + cmdCtx->inputCmd.buf[cmdCtx->inputCmd.cursor] = '\0'; + while (EXT_TRUE) { + /* The printing is performed cyclically until the tabkey detection is complete */ + searchFinish = ExtCmdFindMatchCmd(cmdCtx->inputCmd.buf, res, MATCH_CMD_BUF_CNT, &findCnt, &tailId); + cycle++; + if (searchFinish && cycle ==1) { + if (findCnt) { + CompletesTabKey(res[0], &(cmdCtx->inputCmd)); + } + break; + } + /* Print newline key after end */ + if (cycle == 1) { + EXT_PRINT("\n"); + } + /* cyclic print characters */ + for (unsigned char i = 0; i < findCnt; i++) { + EXT_PRINT("%s ", res[i]); + } + EXT_PRINT("\n"); + if (searchFinish) { + EXT_PRINT("$"); + EXT_PRINT("%s", cmdCtx->inputCmd.buf); + break; + } + /* Clear the count value */ + findCnt = 0; + } +} + +/** + * @brief tabkey alignment implementation + * @param inputCmd : Entering command information + * @param cmdBuf ；Command storage array + * @param cmdLog : Address for storing printed log information + * @retval None + */ +static void CmdEnterKey(struct CmdCtx *cmdCtx) +{ + if (cmdCtx->inputCmd.cursor == 0) { + ConsolePuts("\n$ "); + return; + } + + if (memcpy_s(cmdCtx->cmdBuf, CMD_BUF_MAX, cmdCtx->inputCmd.buf, cmdCtx->inputCmd.cursor) != EXT_SUCCESS) { + ConsolePuts("\n$ "); /* Add the end character */ + return; + } + cmdCtx->cmdBuf[cmdCtx->inputCmd.cursor] = '\0'; + + if (RecordCmd(cmdCtx->cmdBuf, &(cmdCtx->cmdLog)) != EXT_SUCCESS) { + ConsolePuts("\n$ "); /* Add the end character */ + return; + } + CleanInputCmd(cmdCtx); +} + +/** + * @brief Setting the log level + * @param None + * @retval Returns the value of the character's ASCII code + */ +static int CmdStrSetLevel(void) +{ + int ret; + for (unsigned char i = 0; i < EXT_MODULE_BUTT; i++) { + /* Setting the log level cyclically */ + ret = ExtDrvLogSetLogLevel(i, EXT_LOG_LEVEL_FATAL); + if (ret != EXT_SUCCESS) { + break; + } + } + return ret; +} + +typedef struct { + unsigned int ulEventBit; + void (*Func)(struct CmdCtx *cmdCtx); +} EventDoWithTable_t; +static const EventDoWithTable_t astDoWithTable[] = { + { CTL_CH_C, CleanInputCmd}, + { TAB_KEY, CmdTabKey}, /* detrct the tab key */ + { ENTER_KEY1, CmdEnterKey}, /* detected '\r' */ + { ENTER_KEY2, CmdEnterKey}, /* detected '\n' */ + { CTL_CH_P, OutputLogCmd}, + { CTL_CH_N, OutputLogCmd} +}; +/** + * @brief Parse characters one by one + * @param cmdCtx : string information + * @retval Returns the value of the character's ASCII code + */ +static int GetCmdStr(struct CmdCtx *cmdCtx) +{ + int ret = EXT_SUCCESS; + char c; + /* Query the status of the serial port register */ + while ((cmdCtx->uartRxch = ConsoleGetc()) != 0) { + if (cmdCtx->inputCmd.cursor >= CMD_BUF_MAX) { + APP_CMD_ERR_PRINT("\ncmd overflow\n"); + /* Clear Character Cache */ + CleanInputCmd(cmdCtx); + return EXT_FAILURE; + } + /* Get cmd direct key word */ + c = CmdDirectionKey(cmdCtx->uartRxch, &cmdCtx->dirKeyLen); + if (IgnoreCmdKey(c)) { + return ret; + } + /* Delete cmd key word */ + if (DeleteCmdKey(c)) { + CmdDeleteTailChar(&cmdCtx->inputCmd); + return ret; + } + /* Invoke the function drive table */ + for (unsigned int i = 0 ; i < (unsigned int)sizeof(astDoWithTable)/sizeof(astDoWithTable[0]); i ++) { + if ((unsigned int)c == astDoWithTable[i].ulEventBit) { + astDoWithTable[i].Func(cmdCtx); + return ret; + } + } + /* Setting the log level */ + if (c == CTL_CH('l')) { + ret = CmdStrSetLevel(); + return ret; + } + /* Add key word to tail */ + CmdAddTailChar(&cmdCtx->inputCmd, c); + } + return ret; +} + +/** + * @brief encapsulation of Serial Port Transmission + * @param None + * @retval None + */ +void ExtAppCmdProcess(void) +{ + int ret; + unsigned int argsNum; + struct cmdRegisterTable *cmd; + /* Initialize the structure */ + struct CmdCtx *cmdCtx = AppCmdGetCtx(); + ret = GetCmdStr(cmdCtx); + if ((ret != EXT_SUCCESS) || (cmdCtx->cmdBuf[0] == '\0')) { + return; + } + argsNum = CmdParserParam(cmdCtx->cmdBuf, cmdCtx->argv); + if (argsNum == 0) { + /* Clear the memory in the structure */ + (void)memset_s(&cmdCtx->inputCmd, sizeof(cmdCtx->inputCmd), 0, sizeof(cmdCtx->inputCmd)); + (void)memset_s(&cmdCtx->cmdBuf, sizeof(cmdCtx->cmdBuf), 0, sizeof(cmdCtx->cmdBuf)); + return; + } + cmd = ExtCmdFindCmd(cmdCtx->argv[0]); + if (cmd == NULL || cmd->func == NULL) { + /* Initialization Structure */ + (void)memset_s(&cmdCtx->inputCmd, sizeof(cmdCtx->inputCmd), 0, sizeof(cmdCtx->inputCmd)); + (void)memset_s(&cmdCtx->cmdBuf, sizeof(cmdCtx->cmdBuf), 0, sizeof(cmdCtx->cmdBuf)); + return; + } + cmd->func(argsNum, cmdCtx->argv); + EXT_PRINT("\n$ "); + /* Initialization Structure */ + (void)memset_s(&cmdCtx->inputCmd, sizeof(cmdCtx->inputCmd), 0, sizeof(cmdCtx->inputCmd)); + (void)memset_s(&cmdCtx->cmdBuf, sizeof(cmdCtx->cmdBuf), 0, sizeof(cmdCtx->cmdBuf)); +} diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/cmd.c b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/cmd.c new file mode 100644 index 0000000000000000000000000000000000000000..06a08d9c9af032af253e0e11ffffca1c10c55032 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/cmd.c @@ -0,0 +1,56 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cmd.c + * @author MCU Driver Team + * @brief cmd module driver + * @details The header file contains the following declaration: + * + basic register information assignment + */ +#include "cmd.h" +#include "console.h" +#include "ext_log.h" +struct cmdRegisterTable g_cmdRegister[CMD_REGESTER_MAX_NUM] = {0}; + +int g_cmdIndex = 0; + +/** + * @brief assign a value to the information in the RX register. + * @param None + * @retval the information in the RX register. + */ +struct cmdRegisterTable *GetRegisterAddr(void) +{ + return g_cmdRegister; +} + +/** + * @brief Registering a User-Defined Function + * @param cmdName : customize a name for the implemented function. + * @param func : pointer to the customized function. + * @retval None + */ +void ExtCmdRegister(char *cmdName, pfncmd func) +{ + if (g_cmdIndex >= CMD_REGESTER_MAX_NUM || g_cmdIndex < 0) { + EXT_PRINT("the number of registration commmamds has reached the maximum\n"); + return; + } + g_cmdRegister[g_cmdIndex].name = cmdName; /* enter the user-defined name */ + g_cmdRegister[g_cmdIndex].func = func; /* pointing a function pointer to a user-defined function */ + g_cmdIndex++; +} diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/cmd_common.c b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/cmd_common.c new file mode 100644 index 0000000000000000000000000000000000000000..b20ef5e77add7773264837e22fc8f3ca7757c13e --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/cmd_common.c @@ -0,0 +1,67 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cmd_common.c + * @author MCU Driver Team + * @brief cmd module driver + * @details The header file contains the following declaration: + * + total invoking of entry parameter parsing + */ +#include "cmd_common.h" + +/** + * @brief invoking of entry parameter parsing + * @param cdmStr : single character from user + * @param argv[] : Character string directly entered through the serial port + * @retval pointer address of the string + */ +unsigned int CmdParserParam(char *cmdStr, const char *argv[]) +{ + unsigned int nargs = 0; + + while (nargs < ARGS_NUM_MAX) { + /* skip any white space */ + while ((*cmdStr == ' ') || (*cmdStr == '\t')) { + ++cmdStr; + } + + /* end of line, no more args */ + if (*cmdStr == '\0') { + argv[nargs] = NULL; + return (nargs); + } + + /* begin of argument string */ + argv[nargs++] = cmdStr; + + /* find end of string */ + while ((*cmdStr != '\0') && (*cmdStr != ' ') && (*cmdStr != '\t')) { + ++cmdStr; + } + + /* end of line, no more args */ + if (*cmdStr == '\0') { + argv[nargs] = NULL; + return (nargs); + } + + /* terminate current arg */ + *cmdStr++ = '\0'; + } + return nargs; +} + diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/config.c b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/config.c new file mode 100644 index 0000000000000000000000000000000000000000..2cdb30cdd5e64406c5d3dc17519b9cd37cb590e6 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/config.c @@ -0,0 +1,143 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file config.c + * @author MCU Driver Team + * @brief config module driver + * @details The header file contains the following declaration: + * + Miniaturized logs are written based on addresses. + * + Abnormal event reporting + */ +#include +#include "config.h" +#include "common.h" +#include "console.h" +#include "type.h" +#include "string.h" +#include "securec.h" + +/** + * @brief read information by address + * @param add : register address of the information to be read + * @param value : storage array of read information + * @param len ： length of the information to be read + * @retval None. + */ +void ExtLoadRead(uintptr_t add, char *value, int len) +{ + /* Check whether the address is out of range */ + if (add > REGISTER_END || add < REGISTER_START) { + EXT_PRINT("The address is out of range"); + return; + } + /* check param vaild */ + if (value == NULL) { + EXT_PRINT("read data is null, please check value\n"); + return; + } + /* Read information cyclically */ + for (int i = 0; i < len; i++) { + *(value + i) = *(volatile char *)(add + i); + } +} + +/** + * @brief write information by address + * @param add : register address of the information to write + * @param value : storage array of write information + * @param len ： length of the information to write + * @retval None. + */ +void ExtLoadWrite(uintptr_t add, const char *value, int len) +{ + /* Check whether the address is out of range */ + if (add > REGISTER_END || add < REGISTER_START) { + EXT_PRINT("The address is out of range"); + return; + } + /* check param vaild */ + if (value == NULL) { + EXT_PRINT("write data is null, please check value\n"); + return; + } + /* Write information cyclically */ + for (int i = 0; i < len; i++) { + *(volatile char *)(add + i) = *(value + i); + } +} + +char g_dataItem[DATA_ITEM_NUM_MAX][DATA_ITEM_MAX_LEN]; + +/** + * @brief read information by config + * @param item : event that starts to read data + * @param value : storage array of read information + * @param len ： length of the information to be read + * @retval None. + */ +void ExtConfigRead(enum DataItem item, char *value, int len) +{ + /* Exceeded the maximum scenario value */ + if (item > DATA_ITEM_NUM_MAX) { + EXT_PRINT("The config has exceeded max vaule"); + return; + } + /* check param vaild */ + if (len >= DATA_ITEM_MAX_LEN) { + EXT_PRINT("The length of the read data exceeds 256\n"); + return; + } + if (value == NULL) { + EXT_PRINT("The read content is empty, read err"); + return; + } + /* Reads the data stored in the register */ + if (memcpy_s(value, len, &g_dataItem[item], len) != EXT_SUCCESS) { + EXT_PRINT("config read memcpy failed"); + } + return; +} + +/** + * @brief write information by config + * @param add : register address of the information to write + * @param value : storage array of write information + * @param len ： length of the information to write + * @retval None. + */ +void ExtConfigWrite(enum DataItem item, const char *value, int len) +{ + /* Exceeded the maximum scenario value */ + if (item > DATA_ITEM_NUM_MAX) { + EXT_PRINT("The config has exceeded max vaule"); + return; + } + /* check param vaild */ + if (len >= DATA_ITEM_MAX_LEN) { + EXT_PRINT("The length of the write data exceeds 256\n"); + return; + } + if (value == NULL) { + EXT_PRINT("The written content is empty, write err"); + return; + } + /* Writes data to a register for storage */ + if (memcpy_s(&g_dataItem[item], DATA_ITEM_MAX_LEN, value, len) != EXT_SUCCESS) { + EXT_PRINT("config write memcpy failed"); + } + return; +} diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/console.c b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/console.c new file mode 100644 index 0000000000000000000000000000000000000000..2c31c248893ea1eaa5063992946967db89c0c450 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/console.c @@ -0,0 +1,442 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file console.c + * @author MCU Driver Team + * @brief console module driver + * @details The header file contains the following declaration: + * + GPIO configuration enums. + * + GPIO register structures. + * + GPIO DCL Functions. + * + Parameters check functions. + */ +#include "console.h" +#include "errno.h" +#include "ext_log.h" +#include "dfx_log.h" +#define UART_READ_TIME_MS 1000 + +#define VA_START(v, l) __builtin_va_start(v, l) +#define VA_ARG(v, l) __builtin_va_arg(v, l) +#define VA_END(v) __builtin_va_end(v) + +#define DECIMAL_BASE 10U /* Cardinality of decimal numbers */ +#define HALF_ADJUST_BOUNDARY 5U /* The boundary for rounding the floating number */ +#define MAX_DIV_TIMES 31U + +typedef __builtin_va_list va_list; + +/* defines the number of output numbers */ +typedef enum { + BINARY = 2U, + OCTAL = 8U, + DECIMAL = 10U, + HEXADECIMAL = 16U, +} NumBase; +UART_Handle g_console_uart; + +/** + * @brief query the status of a serial port reading register + * @param uartHandle: indicates the serial port information corresponding to the value assignment + * @param isEmpty: pointer to the array that stores status information + * @retval whether data is received + */ +static BASE_StatusType QueryUartRxStatus(UART_Handle *uartHandle, unsigned char *isEmpty) +{ + *isEmpty = uartHandle->baseAddress->UART_FR.BIT.rxfe; /* read register status address */ + return BASE_STATUS_OK; +} + +/** + * @brief Single Character Output + * @param c: single character to be output + * @retval None + */ +void ConsolePutc(const char c) +{ + unsigned int length = 1; + unsigned char p; + /* add newline characters for standby */ + p = (unsigned char)c; + if (c == '\n') { + p = '\r'; + HAL_UART_WriteBlocking(&g_console_uart, &p, length, UART_READ_TIME_MS); + p = '\n'; + } + HAL_UART_WriteBlocking(&g_console_uart, &p, length, UART_READ_TIME_MS); +} + +/** + * @brief output the entire string. + * @param str: string to be output. + * @retval None + */ +int ConsolePuts(const char *str) +{ + int cnt = 0; + /* decompose a string into a single character output */ + while (*str != '\0') { + ConsolePutc(*str); + str++; + cnt++; + } + return cnt; +} + +/** + * @brief Read a single character + * @param None + * @retval ASCII value of the read character + */ +int ConsoleGetc(void) +{ + unsigned char rxStr; + unsigned int length = 1; + int ret; + + /* reads a single character from the serial port */ + ret = HAL_UART_ReadBlocking(&g_console_uart, &rxStr, length, UART_READ_TIME_MS); + if (ret == EXT_SUCCESS) { + return (int)rxStr; + } else { + return -1; + } +} + +/** + * @brief reads the register reception status + * @param None + * @retval register Status + */ +int ConsoleGetQuery(void) +{ + unsigned char isEmpty; + + QueryUartRxStatus(&g_console_uart, &isEmpty); + return !(isEmpty); +} + +/** + * @brief reads the pointer coordinates of the register. + * @param base: pointer initial address value. + * @param exponent: number of times the pointer needs to be moved + * @retval pointer coordinate value + */ +static unsigned long DBG_Pow(unsigned int base, unsigned int exponent) +{ + unsigned long ret = 1; + while (exponent--) { + ret *= base; + } + return ret; /* ret = base ^ exponent */ +} + +/** + * @brief calculate the number of digits entered + * @param num: numbers to be calculated + * @param base: number of digits entered + * @retval number of digits of the calculated number + */ +static unsigned int DBG_CountDigits(int num, NumBase base) +{ + unsigned int cnt = 0; + if (base == 0) { + return 0; + } + /* Cyclic Conversion Count */ + while (num != 0) { + cnt++; + if (cnt > MAX_DIV_TIMES) { + break; + } + num /= base; + } + /* Returns the number of digits */ + return cnt; +} + +/** + * @brief Output unsigned digits + * @param num: numbers to be output + * @param base: number of digits entered + * @param digits: number of digits output + * @retval None + */ +static void DBG_PutUnsignedNum(unsigned int num, NumBase base, unsigned int digits) +{ + unsigned char ch; + while (digits != 0) { + ch = num / DBG_Pow(base, digits - 1); + num %= DBG_Pow(base, digits - 1); + if (base == DECIMAL) { + ConsolePutc(ch + '0'); /* characters that convert numbers to decimal numbers */ + } else if (base == HEXADECIMAL) { + if (ch < DECIMAL_BASE) { + ConsolePutc(ch + '0'); /* Character that converts a number to a hexadecimal number */ + } else { + ConsolePutc(ch - DECIMAL_BASE + 'A'); + } + } + digits--; + } +} + +/** + * @brief print Numbers + * @param intNum: numbers to be output + * @retval returns the number of digits of the output number + */ +static unsigned int DBG_PrintInt(int intNum) +{ + unsigned int cnt; + if (intNum == 0) { + ConsolePutc('0'); /* add '0' */ + return 1; + } + if (intNum < 0) { + ConsolePutc('-'); /* need to manually add a negative sign */ + intNum = -intNum; + } + /* Calculate the number of digits */ + cnt = DBG_CountDigits(intNum, DECIMAL); + DBG_PutUnsignedNum(intNum, DECIMAL, cnt); + return cnt; +} + +/** + * @brief print hexadecimal digits + * @param hexNum: numbers to be output + * @retval returns the number of digits of the output number + */ +static unsigned int DBG_PrintHex(unsigned int hexNum) +{ + unsigned int cnt; + if (hexNum == 0) { + ConsolePutc('0'); /* add '0' */ + return 1; + } + /* Calculate the number of hexadecimal digits */ + cnt = DBG_CountDigits(hexNum, HEXADECIMAL); + DBG_PutUnsignedNum(hexNum, HEXADECIMAL, cnt); + return cnt; +} + +/** + * @brief Print Single Precision Decimals + * @param fltNum: numbers to be output + * @param precision: number of decimal places to print + * @retval returns the number of digits of the output number + */ +static unsigned int DBG_PrintFlt(float fltNum, unsigned int precision) +{ + unsigned int cnt = 0; + unsigned int floatScale; + + if (fltNum < 0) { + ConsolePutc('-'); + cnt += 1; + fltNum = -fltNum; + } + int integerVal = (int)fltNum; + floatScale = DBG_Pow(10, (precision + 1)); /* 10: decimal */ + int floatVal = (long)(floatScale * (fltNum - integerVal)); + /* Half-adjust: round up or round down */ + if (floatVal % DECIMAL_BASE >= HALF_ADJUST_BOUNDARY) { + floatVal = floatVal / DECIMAL_BASE + 1; + } else { + floatVal = floatVal / DECIMAL_BASE; + } + cnt += DBG_PrintInt(integerVal); + ConsolePutc('.'); + cnt += 1; + /* Pad 0 in float part */ + unsigned int fltCnt = DBG_CountDigits(floatVal, DECIMAL); + if (precision > fltCnt) { + for (unsigned int i = 0; i < precision - fltCnt; i++) { + ConsolePutc('0'); /* add '0' */ + } + } + DBG_PutUnsignedNum(floatVal, DECIMAL, fltCnt); /* print unsigned number */ + cnt += precision; + return cnt; +} + +/** + * @brief Resolving Special Characters + * @param ch: single character to be parsed + * @param *paramList: elements that implement parsing + * @retval returns the number of digits of the output number + */ +static unsigned int ParseSpecifier(const char ch, va_list *paramList) +{ + /* Value Definition Initialization */ + unsigned int cnt = 0; + unsigned int tmpCnt; + char chVal = 0; + const char *strVal = 0; + int intVal = 0; + unsigned int unsignedVal = 0; + unsigned int hexVal = 0; + float fltVal = 0; + switch (ch) { + case 'c': + chVal = VA_ARG(*paramList, int); /* Use type int because of byte alignment */ + ConsolePutc(chVal); + cnt += 1; + break; + case 's': + /* received 's', print the string */ + strVal = VA_ARG(*paramList, const char *); + cnt += ConsolePuts(strVal); + break; + case 'd': + /* Received character'd', print initialization */ + intVal = VA_ARG(*paramList, int); + cnt += DBG_PrintInt(intVal); + break; + case 'u': + unsignedVal = VA_ARG(*paramList, unsigned int); + tmpCnt = DBG_CountDigits(unsignedVal, DECIMAL); + DBG_PutUnsignedNum(unsignedVal, DECIMAL, tmpCnt); + cnt += tmpCnt; + break; + case 'x': + case 'X': + case 'p': + /* Received'p' and returned hexadecimal number */ + hexVal = VA_ARG(*paramList, unsigned int); + cnt += DBG_PrintHex(hexVal); + break; + case 'f': + fltVal = VA_ARG(*paramList, double); + cnt += DBG_PrintFlt(fltVal, 5); /* default precision: 5 */ + break; + default: + ConsolePutc(ch); /* Output the original input characters */ + cnt += 1; + break; + } + /* returns the count value */ + return cnt; +} + +/** + * @brief Printed number with width + * @param intNum: Numbers to be printed + * @param *paramList: Number of digits to be printed + * @retval returns the number of digits of the output number + */ +static unsigned int DBG_PrintIntWithField(int intNum, int fieldWidth) +{ + int zeroCnt = 0; + int digitsCnt = 0; + unsigned int cnt = 0; + + if (intNum == 0) { + ConsolePutc('0'); + return 1; + } + if (intNum < 0) { + ConsolePutc('-'); /* add symbol */ + cnt++; + intNum = -intNum; + digitsCnt = DBG_CountDigits(intNum, DECIMAL); /* get int value's width */ + zeroCnt = fieldWidth - digitsCnt; + for (int i = 0; i < zeroCnt; i++) { + ConsolePutc('0'); /* add '0' */ + cnt++; + } + cnt += digitsCnt; + } else { + digitsCnt = DBG_CountDigits(intNum, DECIMAL); /* get int value's width */ + cnt = digitsCnt; + zeroCnt = fieldWidth - digitsCnt; + for (int i = 0; i < zeroCnt; i++) { + ConsolePutc('0'); /* add '0' */ + cnt++; + } + } + DBG_PutUnsignedNum(intNum, DECIMAL, digitsCnt); + return cnt; +} + +/** + * @brief Convert a numeric string to a number + * @param **s: Number string to be converted + * @retval Number after conversion + */ +static int DBG_Atoi(const char **s) +{ + int i, c; + + for (i = 0; '0' <= (c = **s) && c <= '9'; ++*s) { + i = i * 10 + c - '0'; /* 10: decimal */ + } + return i; +} + +/** + * @brief Print the entry parameters + * @param *format: thing need to print + * @retval returns the number of digits of the output number + */ +int UartPrintf(const char *format, ...) +{ + /* Define Value Initialization */ + int cnt = 0; + int fieldWidth = 0; + int floatPrecision = 0; + float fltVal = 0; + int intVal = 0; + va_list paramList; + VA_START(paramList, format); + + while (*format != '\0') { + if (*format != '%') { + /* received '%', print characters directly */ + ConsolePutc(*format); + cnt += 1; + } else { + format++; + /* Check whether the value is an integer */ + if (*format == '0') { + format++; + fieldWidth = DBG_Atoi(&format); + intVal = VA_ARG(paramList, int); + cnt += DBG_PrintIntWithField(intVal, fieldWidth); + } else if (*format == '.') { + format++; + floatPrecision = DBG_Atoi(&format); /* Convert to Integer */ + fltVal = VA_ARG(paramList, double); + cnt += DBG_PrintFlt(fltVal, floatPrecision); + } else { + cnt += ParseSpecifier(*format, ¶mList); + } + } + format++; + } + VA_END(paramList); + /* Returns the value of count */ + return cnt; +} + +/* init console uart */ +void ConsoleInit(UART_Handle uart) +{ + g_console_uart = uart; + DfxCmdRegister(); +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/dfx_debug.c b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/dfx_debug.c new file mode 100644 index 0000000000000000000000000000000000000000..3084eb4c395eafe0a57d6bebda47dbbf8147cc9d --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/dfx_debug.c @@ -0,0 +1,43 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dfx_debug.c + * @author MCU Driver Team + * @brief debug module driver + * @details The header file contains the following declaration: + * + Setting the Debug Mode + */ +#include "dfx_debug.h" +#include "cmd.h" +#include "console.h" +#include "dfx_log.h" + +/** + * @brief Enables or disables the debug mode. + * @param mode: Status to be set + * @retval None. + */ +void ExtSetDebugMode(enum ExtDebugMode mode) +{ + struct SysDebugSwitch *debugSwitch = GetDebugSwitch(); + if (mode == RUNNING) { + debugSwitch->enable = 0; /* 0 indicates that the debug mode is disabled */ + return; + } + debugSwitch->enable = 1; /* not 0 indicates that the debug mode is enabled */ + return; +} diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/dfx_log.c b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/dfx_log.c new file mode 100644 index 0000000000000000000000000000000000000000..b0cba421d07a0b8d515ba0cfccaea257eada5a7d --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/dfx_log.c @@ -0,0 +1,468 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dfx_log.c + * @author MCU Driver Team + * @brief dfx_log module driver + * @details The header file contains the following declaration: + * + Small-scale log output + * + Miniaturized log output with different numbers of int types + */ +#include +#include "string.h" +#include "stdarg.h" +#include "type.h" +#include "dfx_log.h" +#include "common.h" +#include "log.h" +#include "ext_log.h" +#include "securec.h" + +#define EXT_DEFAULT_LOG_LEVEL EXT_LOG_LEVEL_ERROR +#define THIS_FILE_ID FILE_ID_LOG_C +static struct MemoryLog g_memoryLog = {0}; +#define DIVISOR 10 +#define EXT_MODULE_DFX 12 /* Test Version Information Cases */ +/* Address of the test case for obtaining version information */ +#define VERSION_INFO_ADDR 0x4000000 +/* Device Name */ +char *moduleStr[EXT_MODULE_BUTT] = { + "app_main", + "app_console", + "app_chip", + "drv_base", + "drv_chips", + "drv_crg", + "drv_gpio", + "drv_i2c", + "drv_irq", + "drv_pinctrl", + "drv_timer", + "drv_uart", + "dfx", +}; +/* Levels that can be set */ +char *ExtLogLevel1[6] = { + "EXT_LOG_LEVEL_FATAL", + "EXT_LOG_LEVEL_ERROR", + "EXT_LOG_LEVEL_WARNING", + "EXT_LOG_LEVEL_INFO", + "EXT_LOG_LEVEL_DBG", + "EXT_LOG_LEVEL_BUTT", +}; +struct SysLogCtx g_logCtx = { 0 }; +/** + * @defgroup log Common + * @brief Initialize miniaturization log information. + * @{ + */ +struct SysLogCtx *GetLogCtx(void) +{ + return &g_logCtx; +} +static struct SysDebugSwitch g_debugSwitch = {.enable = 1}; +struct SysDebugSwitch *GetDebugSwitch(void) +{ + /* Return Enable Initialization */ + return &g_debugSwitch; +} +/** + * @brief Initialize register information. + * @param memData: Register structure variable + * @retval None. + */ +void InitMemoryData(struct MemoryLog *memData) +{ + memData->enable = EXT_TRUE; + memData->logLen = 0; + memData->writePos = 0; +} + +/** + * @brief Obtains the value of register information. + * @param None. + * @retval memory address + */ +struct MemoryLog *GetMemoryData(void) +{ + return &g_memoryLog; +} + +/** + * @brief Initialize the environment information for miniaturization logs. + * @param ctx: Environment information of miniaturized logs + * @retval None. + */ +void LogCtxInit(struct SysLogCtx *ctx) +{ + ctx->modStr = moduleStr; + for (unsigned char i = 0; i < EXT_MODULE_BUTT; i++) { + ctx->logLevel[i] = EXT_DEFAULT_LOG_LEVEL; + } + ctx->init = EXT_TRUE; +} + +/** + * @brief Write the log to the memory. + * @param *memlog: memory address + * @param src: Stored Information + * @param cnt: Length of the stored information + * @retval None. + */ +static void PutLogToMem(struct MemoryLog *memLog, const char *src, unsigned char cnt) +{ + unsigned char len = cnt; /* default mem write pos < LOG_MEM_POOL_MAX_LEN - cnt */ + + if (cnt > LOG_MEM_POOL_MAX_LEN - memLog->writePos) { + len = LOG_MEM_POOL_MAX_LEN - memLog->writePos; + /* put log data to buf */ + if (memcpy_s(memLog->mmzBuf + memLog->writePos, LOG_MEM_POOL_MAX_LEN - memLog->writePos, src, len) != + EXT_SUCCESS) { + EXT_PRINT("put log to memory memcpy err\n"); + return; + } + /* if the data is full, the position pointer returns to the origin. */ + memLog->writePos = 0; + src += len; + len = cnt - len; + } + /* if the data is full, cyclic write log data */ + if (memcpy_s(memLog->mmzBuf + memLog->writePos, LOG_MEM_POOL_MAX_LEN - memLog->writePos, src, len) != EXT_SUCCESS) { + EXT_PRINT("put log to memory memcpy err\n"); + return; + } + + /* The pointer position is increased by the write length */ + memLog->writePos += len; + memLog->logLen += cnt; + if (memLog->logLen > LOG_MEM_POOL_MAX_LEN) { + memLog->logLen = LOG_MEM_POOL_MAX_LEN; + } +} + +/** + * @brief Calculates the length of an int number converted to a character string. + * @param num: number to calculate. + * @retval Length after being converted to a character string. + */ +static int CountNumberLen(unsigned int num) +{ + int count = 0; + do { + count += 1; + num = num/DIVISOR; + } while (num != 0); /* divided by 10 to round */ + return count; +} + +/** + * @brief Check whether the log output is proper. + * @param level: Specifies the log level. + * @param debugSwitch: Pointer to the debug mode + * @param modId: Device ID + * @param ctx Pointer to storing log information + * @retval Indicates whether the printing is successful. + */ +static unsigned int IsLogOutBufLegal(enum ExtLogLevel level, struct SysDebugSwitch *debugSwitch, + enum ExtModule modId, struct SysLogCtx *ctx) +{ + /* Check whether the value is out of range */ + if (level > EXT_LOG_LEVEL_BUTT || modId > EXT_MODULE_BUTT) + return EXT_FAILURE; + /* Checking the Status of debug */ + if (((!debugSwitch->enable) && (level != EXT_LOG_LEVEL_ERROR)) || (level > ctx->logLevel[modId])) { + return EXT_SUCCESS; + } + return EXT_FAILURE; +} + +/** + * @brief Log output and printing + * @param level: Specifies the log level. + * @param modId: Device ID + * @param id: device name + * @param logBuf: Character string information to be printed + * @param logBuflen: Indicates the length of the printed information. + * @retval Indicates whether the printing is successful. + */ +int ExtDrvLogOutBuf(enum ExtLogLevel level, enum ExtModule modId, unsigned int id, const unsigned int* logBuf, + unsigned short logBufLen) +{ + /* Check whether the array is empty */ + if (logBuf == NULL) + return EXT_FAILURE; + /* Value Definition Initialization */ + char buf[LOG_UINT_MAX_LEN] = { 0 }; + int cnt = 0; + int len = 0; + int count = 0; + + struct SysLogCtx *ctx = GetLogCtx(); + + struct SysDebugSwitch *debugSwitch = GetDebugSwitch(); + if (!ctx->init) { LogCtxInit(ctx); } /* Initialize the structure */ + if (!(IsLogOutBufLegal(level, debugSwitch, modId, ctx))) { return EXT_SUCCESS; } + cnt = sprintf_s(buf, LOG_UINT_MAX_LEN, "%u", id); + /* an error message is displayed when the return value is a negative value */ + if (cnt < 0) { + EXT_PRINT("sprintf err\n"); + return EXT_FAILURE; + } + len += cnt; + + unsigned short i = 0; + /* Write characters cyclically */ + for (; i < logBufLen; ++i) { + count = CountNumberLen(logBuf[i]); + if ((count + len + 1) >= LOG_UINT_MAX_LEN) { return EXT_FAILURE; } + cnt = sprintf_s(buf + len, LOG_UINT_MAX_LEN - len, " %u", logBuf[i]); + /* an error message is displayed when the return value is a negative value */ + if (cnt < 0) { + EXT_PRINT("sprintf err\n"); + return EXT_FAILURE; + } + len += cnt; + } + cnt = sprintf_s(buf + len, LOG_UINT_MAX_LEN - len, "\n"); + len += cnt; + /* an error message is displayed when the return value is a negative value */ + if (cnt < 0) { + EXT_PRINT("sprintf err\n"); + return EXT_FAILURE; + } else if (!ctx->memLog.enable) { + EXT_PRINT("%s", buf); + return EXT_SUCCESS; + } + + PutLogToMem(&ctx->memLog, buf, len); /* Storing the log information into the memory */ + return EXT_SUCCESS; +} + + +/** + * @brief get version info cmd + * @param None + * @retval Return the setting result, success or failure. + */ +int CmdGetVersionInfo(void) +{ + int versionInfo; + versionInfo = EXT_REG_READ32(VERSION_INFO_ADDR); + /* Print version information */ + ExtLog1(ERR, EXT_MODULE_DFX, "version info is : %x\n", versionInfo); + return EXT_SUCCESS; +} +/** + * @brief Processing log buffer + * @param len: Length of the processed data. + * @param level: Specifies the log level. + * @param modId: Device ID + * @param buf: Log information to be processed. + * @retval Indicates whether the printing is successful. + */ +static int DealLogBuf(int len, enum ExtLogLevel level, enum ExtModule modId, const char buf[]) +{ + struct SysLogCtx *ctx = GetLogCtx(); + struct SysDebugSwitch *debugSwitch = GetDebugSwitch(); + /* Checking the Status of debug */ + if (!debugSwitch->enable) { + if (level != EXT_LOG_LEVEL_ERROR) { + return EXT_SUCCESS; + } + } + + if (!ctx->init) { LogCtxInit(ctx); } /* Initialize the structure */ + + if (level > ctx->logLevel[modId]) { return EXT_SUCCESS; } + /* If the length is negative, an error value is returned */ + if (len < 0) { + EXT_PRINT("sprintf err\n"); + return EXT_FAILURE; + } + + if (!ctx->memLog.enable) { + EXT_PRINT("%s", buf); + return EXT_SUCCESS; + } + + PutLogToMem(&ctx->memLog, buf, len); /* Storing the log information into the memory */ + return EXT_SUCCESS; +} + +/** + * @brief Print with no int number + * @param level: Specifies the log level. + * @param modId: Device ID + * @param id: custom string variable + * @retval Indicates whether the printing is successful. + */ +int ExtDrvLogOut0(enum ExtLogLevel level, enum ExtModule modId, unsigned int id) +{ + /* Check whether the value is out of range */ + if (level > EXT_LOG_LEVEL_BUTT || modId > EXT_MODULE_BUTT) + return EXT_FAILURE; + char buf[LOG_UINT_MAX_LEN] = { 0 }; + int len = 0; + len = sprintf_s(buf, LOG_UINT_MAX_LEN, "%u\n", id); + if (len < 0) { + EXT_PRINT("sprintf err\n"); + return EXT_FAILURE; + } + /* Process logs and determine whether to write to memory */ + return (DealLogBuf(len, level, modId, buf)); +} + +/** + * @brief Print with an int number + * @param level: Specifies the log level. + * @param modId: Device ID + * @param id: custom string variable + * @param d0: User-defined first variable of the int type + * @retval Indicates whether the printing is successful. + */ +int ExtDrvLogOut1(enum ExtLogLevel level, enum ExtModule modId, unsigned int id, unsigned int d0) +{ + /* Check whether the value is out of range */ + if (level > EXT_LOG_LEVEL_BUTT || modId > EXT_MODULE_BUTT) + return EXT_FAILURE; + char buf[LOG_UINT_MAX_LEN] = { 0 }; + int len = 0; + len = sprintf_s(buf, LOG_UINT_MAX_LEN, "%u %u\n", id, d0); + if (len < 0) { + EXT_PRINT("sprintf err\n"); + return EXT_FAILURE; + } + /* Process logs and determine whether to write to memory */ + return (DealLogBuf(len, level, modId, buf)); +} + +/** + * @brief Print with two int numbers + * @param level: Specifies the log level. + * @param modId: Device ID + * @param id: custom string variable + * @param d0: User-defined first variable of the int type + * @param d1: User-defined second variable of the int type + * @retval Indicates whether the printing is successful. + */ +int ExtDrvLogOut2(enum ExtLogLevel level, enum ExtModule modId, unsigned int id, unsigned int d0, unsigned int d1) +{ + /* Check whether the value is out of range */ + if (level > EXT_LOG_LEVEL_BUTT || modId > EXT_MODULE_BUTT) + return EXT_FAILURE; + char buf[LOG_UINT_MAX_LEN] = { 0 }; + int len = 0; + len = sprintf_s(buf, LOG_UINT_MAX_LEN, "%u %u %u\n", id, d0, d1); + if (len < 0) { + EXT_PRINT("sprintf err\n"); + return EXT_FAILURE; + } + /* Process logs and determine whether to write to memory */ + return (DealLogBuf(len, level, modId, buf)); +} + +/** + * @brief Print with three int numbers + * @param level: Specifies the log level. + * @param modId: Device ID + * @param id: custom string variable + * @param d0: User-defined first variable of the int type + * @param d1: User-defined second variable of the int type + * @param d2: User-defined third variable of the int type + * @retval Indicates whether the printing is successful. + */ +int ExtDrvLogOut3(enum ExtLogLevel level, enum ExtModule modId, unsigned int id, unsigned int d0, unsigned int d1, + unsigned int d2) +{ + /* Check whether the value is out of range */ + if (level > EXT_LOG_LEVEL_BUTT || modId > EXT_MODULE_BUTT) + return EXT_FAILURE; + char buf[LOG_UINT_MAX_LEN] = { 0 }; + int len = 0; + len = sprintf_s(buf, LOG_UINT_MAX_LEN, "%u %u %u %u\n", id, d0, d1, d2); + if (len < 0) { + EXT_PRINT("sprintf err\n"); + return EXT_FAILURE; + } + /* Process logs and determine whether to write to memory */ + return (DealLogBuf(len, level, modId, buf)); +} + +/** + * @brief Setting the log level + * @param id: Indicates the device ID of the specified level + * @param level: Level set for the device + * @retval Indicates whether the printing is successful + */ +int ExtDrvLogSetLogLevel(enum ExtModule id, enum ExtLogLevel level) +{ + /* Exceeded the maximum value of the storage array */ + if (level >= EXT_LOG_LEVEL_BUTT || id >= EXT_MODULE_BUTT) { + EXT_PRINT("module or level unsupport\n"); + return EXT_FAILURE; + } + + struct SysLogCtx *ctx = GetLogCtx(); + + if (!ctx->init) { + LogCtxInit(ctx); /* Initialize the structure */ + } + ctx->logLevel[id] = level; + return EXT_SUCCESS; +} + +/** + * @brief Logs are output based on different levels + * @param level: Pre-set level + * @param id: Indicates the device ID of the output log + * @param fmt: character string to be output + * @retval Indicates whether the printing is successful + */ +int ExtDrvLogOutFmt(enum ExtLogLevel level, enum ExtModule id, const char *fmt, ...) +{ + /* define value initialization */ + va_list args; + + struct SysDebugSwitch *debugSwitch = GetDebugSwitch(); + if ((!debugSwitch->enable) && (level != EXT_LOG_LEVEL_ERROR)) { + return EXT_SUCCESS; + } + + /* Outputs character strings by level and ID */ + if (level >= EXT_LOG_LEVEL_BUTT || id >= EXT_MODULE_BUTT) { + EXT_PRINT("level %d or module %d err\n", level, id); + return EXT_FAILURE; + } + + char *tag = "FEWIDB"; + struct SysLogCtx *ctx = GetLogCtx(); + + if (!ctx->init) { + LogCtxInit(ctx); /* Initialize the structure */ + } + + if (level > ctx->logLevel[id]) { + return EXT_SUCCESS; + } + EXT_PRINT("%c-%s:", *(tag + level), ctx->modStr[id]); /* Calculate the print length */ + + va_start(args, fmt); + EXT_PRINT(fmt, args); + va_end(args); + EXT_PRINT("\r\n"); + return EXT_SUCCESS; +} diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/dfx_log_proc.c b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/dfx_log_proc.c new file mode 100644 index 0000000000000000000000000000000000000000..03e80edc115c3d1cfa54d01e765efdeb34f537d3 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/dfx_log_proc.c @@ -0,0 +1,195 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file gpio_ip.h + * @author MCU Driver Team + * @brief GPIO module driver + * @details The header file contains the following declaration: + * + GPIO configuration enums. + * + GPIO register structures. + * + GPIO DCL Functions. + * + Parameters check functions. + */ +#include +#include +#include "command.h" +#include "dfx_log.h" +#include "log.h" +#include "console.h" +#include "type.h" + +/** + * @brief show the log information. + * @param None + * @retval return whether the display is successful + */ +static int DrvLogShowLogLevel(void) +{ + struct SysLogCtx *ctx = GetLogCtx(); + + if (!ctx->init) { + LogCtxInit(ctx); /* Initialize the structure */ + } + + EXT_PRINT("\n"); + EXT_PRINT("\t ------- module log level -------\n"); /* Delimiter Display Title */ + struct SysDebugSwitch *debugSwitch = GetDebugSwitch(); + if (!debugSwitch->enable) { + EXT_PRINT("The debug mode is disabled, and only err-level information is output\n"); + } + EXT_PRINT("\n"); + EXT_PRINT("ModuleName ModuleId LogLevel\n"); + /* Displays log information line by line in sequence */ + for (unsigned char i = 0; i < EXT_MODULE_BUTT; i++) { + EXT_PRINT("%s\t", ctx->modStr[i]); + EXT_PRINT("%d\t", i); + EXT_PRINT("%d", ctx->logLevel[i]); + EXT_PRINT("\n"); + } + return EXT_SUCCESS; +} + +/** + * @brief write log to memory + * @param enable: Enables log writing to the memory + * @retval return whether the display is successful + */ +static int DrvLogPutLogToMem(unsigned char enable) +{ + if (enable != EXT_TRUE && enable != EXT_FALSE) { + EXT_PRINT("param err\n"); + return EXT_FAILURE; + } + + struct SysLogCtx *ctx = GetLogCtx(); + if (!ctx->init) { + LogCtxInit(ctx); /* Initialize the structure */ + } + /* Flag bit 1 to start writing */ + if (enable) { + ctx->memLog.enable = EXT_TRUE; + EXT_PRINT("log put memory:0x%x enable\n", ctx->memLog.mmzBuf); + } else { + ctx->memLog.enable = EXT_FALSE; + EXT_PRINT("log put memory disable\n"); + } + + /* Initialize Pointer */ + ctx->memLog.writePos = 0; + ctx->memLog.logLen = 0; + return EXT_SUCCESS; +} + +/** + * @brief print the logs stored in the memory + * @param None + * @retval None + */ +static void DrvLogPrintMemLog(void) +{ + struct SysLogCtx *ctx = GetLogCtx(); + if (!ctx->init) { + LogCtxInit(ctx); /* Initialize the structure */ + } + + if (!ctx->memLog.enable) { + EXT_PRINT("mem record log not enable\n"); + return; + } + + unsigned short i; + if (ctx->memLog.logLen == LOG_MEM_POOL_MAX_LEN) { + /* Logs are printed one by one */ + for (i = ctx->memLog.writePos; i < LOG_MEM_POOL_MAX_LEN; ++i) { + EXT_PRINT("%c", ctx->memLog.mmzBuf[i]); + } + } + + /* Cyclic Print Characters */ + for (i = 0; i < ctx->memLog.writePos; ++i) { + EXT_PRINT("%c", ctx->memLog.mmzBuf[i]); + } +} + +/** + * @brief Prints the help information about the log command + * @param None + * @retval None + */ +static void DrvLogCmdHelp(void) +{ + /* Print Command Prompt */ + EXT_PRINT("Usage:\n"); + EXT_PRINT("logcmd show show log info\n"); + EXT_PRINT("logcmd setlevel [moduleId][level] set log level(0:F,1:E,2:W,3:I,4:D)\n"); + EXT_PRINT("logcmd setmem [0/1] enable mem log(1: print to memory, 0: print to console)\n"); + EXT_PRINT("logcmd print print log from memory\n"); +} + +/** + * @brief Command Parsing of Driver Miniaturization Logs + * @param argc: Total number of input strings + * @param argv[]: Entered character string information. + * @retval return whether the display is successful + */ +static int DrvLogCmd(unsigned int argc, const char *argv[]) +{ + char *endp = NULL; + if (argc < 2) { /* 2 is agrc */ + DrvLogCmdHelp(); + return EXT_FAILURE; + } else if (strcmp(argv[1], "show") == 0) { + DrvLogShowLogLevel(); + } else if (strcmp(argv[1], "setlevel") == 0) { + if (argc < 4) { /* 4 is argc */ + DrvLogCmdHelp(); + return EXT_FAILURE; + } + unsigned int modId = strtoul(argv[2], &endp, 0); /* 2 is argv */ + unsigned int level = strtoul(argv[3], &endp, 0); /* 3 is argv */ + if (ExtDrvLogSetLogLevel(modId, level) != EXT_SUCCESS) { + EXT_PRINT("set log level err\n"); + return EXT_FAILURE; + } + EXT_PRINT("setlevel succsee!\r\n"); + } else if (strcmp(argv[1], "setmem") == 0) { + if (argc < 3) { /* 3 is argc */ + DrvLogCmdHelp(); + return EXT_FAILURE; + } + + unsigned char enable = (unsigned char)strtoul(argv[2], &endp, 0); /* 2 is argv */ + if (DrvLogPutLogToMem(enable) != EXT_SUCCESS) { + EXT_PRINT("set put mem err\n"); + return EXT_FAILURE; + } + } else if (strcmp(argv[1], "print") == 0) { + DrvLogPrintMemLog(); + } + + return EXT_SUCCESS; +} + +/** + * @brief init dfx + * @param None + * @retval None + */ +void DfxCmdRegister(void) +{ + ExtCmdRegister("logcmd", &DrvLogCmd); +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/event.c b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/event.c new file mode 100644 index 0000000000000000000000000000000000000000..0f8eb7a69e5646f6bd89945745b8448b39255e58 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/event.c @@ -0,0 +1,91 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file event.c + * @author MCU Driver Team + * @brief Header file containing functions prototypes of erron module. + * + Defines the function of reporting initialization events. + */ +#include "event.h" +#include "console.h" +#include "command.h" +#include "common.h" +#include "typedefs.h" + +UserMgr g_userMgr; + +/** + * @brief Event report. + * @param eventObj : Unsolicitedly reported events + * @retval Indicates whether the upload is successful. + */ +static inline int UserReport(UserEventObj *eventObj) +{ + unsigned int *reportAddr = (unsigned int *)&g_userMgr.reportAddr; + + /* Obtain reported events */ + *reportAddr = (uintptr_t)(void *)&eventObj->report; + EXT_PRINT("event report type: %u event type: %u ", eventObj->report.event.eventType, eventObj->report.reportType); + g_userMgr.reportLock = 0; + return EXT_SUCCESS; +} + +/** + * @brief Obtains the address for reporting events. + * @param None + * @retval Address to which the event is reported. + */ +static UserEventObj *UserGetEventObj(void) +{ + /* The event is locked and cannot be reported */ + if (g_userMgr.reportLock == 1) { + g_userMgr.reportFailedCount++; + return NULL; + } + + g_userMgr.reportLock = 1; + return &g_userMgr.eventObj; +} + +/** + * @brief Reporting an event + * @param eventObj: Structure for storing reported events + * @retval Indicates whether the upload is successful. + */ +int UserReportEvent(UserEventObj *eventObj) +{ + UserEventObj *obj = (UserEventObj *)UserGetEventObj(); + /* If it is locked, it cannot be reported */ + if (obj == NULL) { + return EXT_FAILURE; + } + + *obj = *eventObj; + + return UserReport(&g_userMgr.eventObj); +} + +/** + * @brief RInitializing event reporting + * @param None + * @retval For user-defined + */ +int EventInit(void) +{ + /* Users can customize event reporting based on their requirements */ + return 0; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/ext_command.c b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/ext_command.c new file mode 100644 index 0000000000000000000000000000000000000000..7bbf842c56e1565ac006ae0f39fe8ef3d4450c63 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/log/src/ext_command.c @@ -0,0 +1,123 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file ext_command.c + * @author MCU Driver Team + * @brief command module driver + * @details The header file contains the following declaration: + * + Mainly including query commands. + * + Mainly including matching command. + */ +#include +#include +#include "command.h" +#include "cmd.h" +#include "common.h" +#define USER_COMMAND_START 0x50000 +#define USER_COMMAND_END 0x60000 + +/** + * @brief Commands contained in the query string. + * @param cmd: Contains command information. + * @retval Indicates whether the query is successful. + */ +struct cmdRegisterTable *ExtCmdFindCmd(const char *cmd) +{ + struct cmdRegisterTable *cmdtp = GetRegisterAddr(); + const char *p = NULL; + + unsigned int tblLen = CMD_REGESTER_MAX_NUM; + unsigned int cmdLen; + + if (tblLen == 0 || cmd == NULL) { + return NULL; + } + + /* compare command name only until first dot */ + p = strchr(cmd, '.'); + cmdLen = (p == NULL) ? (unsigned char)strlen(cmd) : (unsigned char)(p - cmd); + + for (int i = 0; i < CMD_REGESTER_MAX_NUM; i++, cmdtp++) { + if (cmdtp->name == NULL) { + return NULL; + } + + if ((p != NULL) && (cmdLen != 0)) { + if (strncmp(cmd, cmdtp->name, cmdLen) == 0) { + return cmdtp; /* only match part before dot */ + } + } + + if (strcmp(cmd, cmdtp->name) == 0) { + return cmdtp; /* full match */ + } + } + return NULL; /* not found */ +} + +/** + * @brief Matches valid commands based on included commands. + * @param head: Command to be queried. + * @param resLen: Length of the string to be found. + * @param finCnt: Set the number of times to be searched. + * @param tailId: End Flag Character + * @retval Indicates whether the query is successful. + */ +static unsigned char IsFindMatchCmdParamLegal(const char *head, unsigned char resLen, unsigned char *findCnt, + const char *res[]) +{ + if (head == NULL || resLen == 0 || findCnt == NULL || res == NULL) { return EXT_FALSE; } + return EXT_TRUE; +} + +/** + * @brief Matches valid commands based on included commands. + * @param head: Command to be queried. + * @param *res[]: An array that temporarily stores strings. + * @param resLen: Length of the string to be found. + * @param finCnt: Set the number of times to be searched. + * @param tailId: End Flag Character + * @retval Indicates whether the query is successful. + */ +unsigned char ExtCmdFindMatchCmd(const char *head, const char *res[], unsigned char resLen, unsigned char *findCnt, + unsigned int *tailId) +{ + /* Define Value Initialization */ + unsigned char ret = EXT_TRUE; + unsigned int cmdId = 0; + size_t headLen = 0; + /* initialization structure */ + struct cmdRegisterTable *cmdtp = GetRegisterAddr(); + + if (!IsFindMatchCmdParamLegal(head, resLen, findCnt, res)) { return EXT_FALSE; } + headLen = strlen(head); + for (int i = 0; i < CMD_REGESTER_MAX_NUM; cmdtp++, cmdId++, i++) { + if (cmdtp->name == NULL) { break; } /* search finish */ + if (*findCnt >= resLen) { /* search not finish */ + ret = EXT_FALSE; + break; + } + + /* detect registered name */ + if ((*tailId > 0 && (unsigned int)cmdId < *tailId) || strlen(cmdtp->name) < (unsigned int)headLen + || strcmp(cmdtp->name, UART_SWITCH_CMD) == 0) { continue; } + + if (strncmp(head, cmdtp->name, headLen) == 0) { res[(*findCnt)++] = cmdtp->name; } + } + *tailId = cmdId; + return ret; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/debug/src/debug.c b/vendor/xinlingyu_92_3061M/Project/drivers/debug/src/debug.c new file mode 100644 index 0000000000000000000000000000000000000000..d7cb26bc333134cac586e36d16cb174fa28c0f18 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/debug/src/debug.c @@ -0,0 +1,416 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file debug.c + * @author MCU Driver Team + * @brief DEBUG module driver. + * This file provides functions to manage the following functionalities of the DEBUG module. + * + Initialization and de-initialization functions + * + Format string print function + */ + +#include "debug.h" + +#if (DBG_PRINTF_USE == DBG_USE_UART_PRINTF) +/* Macro definitions of stdarg.h to prevent using standard library */ +#define VA_START(v, l) __builtin_va_start(v, l) +#define VA_ARG(v, l) __builtin_va_arg(v, l) +#define VA_END(v) __builtin_va_end(v) + +#define DECIMAL_BASE 10U /* Cardinality of decimal numbers */ +#define HALF_ADJUST_BOUNDARY 5U /* The boundary for rounding the floating number */ +#define MAX_DIV_TIMES 31U +/* FLOAT_SCALE = DECIMAL_BASE ^ (FLOAT_PRECISION + 1) */ +#endif + +typedef __builtin_va_list va_list; + +#if (DBG_PRINTF_USE == DBG_USE_UART_PRINTF) +/** + * @brief Cardinality of binary, octal, decimal, and hexadecimal numbers. + */ +typedef enum { + BINARY = 2U, + OCTAL = 8U, + DECIMAL = 10U, + HEXADECIMAL = 16U, +} NumBase; +#endif + +#if (DBG_PRINTF_USE == DBG_USE_UART_PRINTF) +UART_Handle g_dbgUart; +/** + * @brief Initialize the UART port for DBG_UartPrintf(). + * @param baudRate The baud rate of UART port. + * @retval BASE_StatusType BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType DBG_UartPrintInit(unsigned int baudRate) +{ + g_dbgUart.baseAddress = DBG_PRINTF_UART_PORT; + g_dbgUart.baudRate = baudRate; + g_dbgUart.dataLength = UART_DATALENGTH_8BIT; + g_dbgUart.stopBits = UART_STOPBITS_ONE; + g_dbgUart.parity = UART_PARITY_NONE; + g_dbgUart.txMode = UART_MODE_BLOCKING; + g_dbgUart.rxMode = UART_MODE_BLOCKING; + g_dbgUart.fifoMode = true; + g_dbgUart.fifoTxThr = UART_FIFOFULL_ONE_EIGHT; + g_dbgUart.fifoRxThr = UART_FIFOFULL_ONE_EIGHT; + g_dbgUart.hwFlowCtr = UART_HW_FLOWCTR_DISABLE; + return HAL_UART_Init(&g_dbgUart); +} + +/** + * @brief De-initialize the UART port for DBG_UartPrintf(). + * @retval BASE_StatusType BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType DBG_UartPrintDeInit(void) +{ + return HAL_UART_DeInit(&g_dbgUart); +} +#endif + +/* Format string print function */ +#if (DBG_PRINTF_USE == DBG_USE_UART_PRINTF) +/** + * @brief Write a character to the UART port. + * @param ch The int promotion of the character to be written. + * @retval None. + */ +static void DBG_PrintCh(unsigned int ch) +{ + while (DBG_PRINTF_UART_PORT->UART_FR.BIT.txff == 1) { + ; + } + DBG_PRINTF_UART_PORT->UART_DR.BIT.data = (unsigned char)ch; +} + +/** + * @brief Print a string through the UART port. + * @param str The string to be printed. + * @retval int If succeeded, the total number of characters printed is returned. + * If the input parameter is wrong, a BASE_STATUS_ERROR is returned. + */ +static int DBG_PrintStr(const char *str) +{ + DEBUG_ASSERT_PARAM(str != NULL); + int cnt = 0; + while (*str != '\0') { + DBG_PrintCh(*str); + str++; + cnt++; + } + return cnt; +} + +/** + * @brief Raise base value to the power exponent value. + * @param base Base value. + * @param exponent Exponent value. + * @retval unsigned long The result of raising base to the power exponent. + */ +static unsigned long DBG_Pow(unsigned int base, unsigned int exponent) +{ + unsigned long ret = 1; + while (exponent--) { + ret *= base; + } + return ret; /* ret = base ^ exponent */ +} + +/** + * @brief Count the digits of the number. + * @param num The number to be counted. + * @param base The number base of num. + * @retval unsigned int The number of digits. + */ +static unsigned int DBG_CountDigits(int num, NumBase base) +{ + unsigned int cnt = 0; + if (base == 0) { + return 0; + } + while (num != 0) { + cnt++; + if (cnt > MAX_DIV_TIMES) { + break; + } + num /= base; + } + cnt = (cnt == 0) ? 1 : cnt; + return cnt; +} + +/** + * @brief Print unsigned number through UART port. + * @param num The unsigned number to be printed. + * @param base The number base of num. + * @param digits The digits of num. + */ +static void DBG_PutUnsignedNum(unsigned int num, NumBase base, unsigned int digits) +{ + unsigned char ch; + while (digits != 0) { + ch = num / DBG_Pow(base, digits - 1); + num %= DBG_Pow(base, digits - 1); + if (base == DECIMAL) { + DBG_PrintCh(ch + '0'); + } else if (base == HEXADECIMAL) { + if (ch < DECIMAL_BASE) { + DBG_PrintCh(ch + '0'); + } else { + DBG_PrintCh(ch - DECIMAL_BASE + 'A'); + } + } else { + break; + } + digits--; + } +} + +/** + * @brief Print decimal number through UART port. + * @param intNum The decimal number to be printed. + * @retval unsigned int The total number of characters printed. + */ +static unsigned int DBG_PrintInt(int intNum) +{ + unsigned int cnt; + if (intNum == 0) { + DBG_PrintCh('0'); + return 1; + } + if (intNum < 0) { + DBG_PrintCh('-'); + intNum = -intNum; + } + cnt = DBG_CountDigits(intNum, DECIMAL); + DBG_PutUnsignedNum(intNum, DECIMAL, cnt); + return cnt; +} + +/** + * @brief Print hexadecimal number through UART port. + * @param hexNum The hexadecimal number to be printed. + * @retval unsigned int The total number of characters printed. + */ +static unsigned int DBG_PrintHex(unsigned int hexNum) +{ + unsigned int cnt; + if (hexNum == 0) { + DBG_PrintCh('0'); + return 1; + } + cnt = DBG_CountDigits(hexNum, HEXADECIMAL); + DBG_PutUnsignedNum(hexNum, HEXADECIMAL, cnt); + return cnt; +} + +/** + * @brief Print floating-point number through UART port. + * @param fltNum The floating-point number to be printed. + * @retval unsigned int The total number of characters printed. + */ +static unsigned int DBG_PrintFlt(float fltNum, unsigned int precision) +{ + unsigned int cnt = 0; + unsigned int floatScale; + + if (fltNum < 0) { + DBG_PrintCh('-'); + cnt += 1; + fltNum = -fltNum; + } + int integerVal = (int)fltNum; + floatScale = DBG_Pow(10, (precision + 1)); /* 10: decimal */ + int floatVal = (long)(floatScale * (fltNum - integerVal)); + /* Half-adjust: round up or round down */ + if (floatVal % DECIMAL_BASE >= HALF_ADJUST_BOUNDARY) { + floatVal = floatVal / DECIMAL_BASE + 1; + } else { + floatVal = floatVal / DECIMAL_BASE; + } + cnt += DBG_PrintInt(integerVal); + DBG_PrintCh('.'); + cnt += 1; + /* Pad 0 in float part */ + unsigned int fltCnt = DBG_CountDigits(floatVal, DECIMAL); + if (precision > fltCnt) { + for (unsigned int i = 0; i < precision - fltCnt; i++) { + DBG_PrintCh('0'); /* add '0' */ + } + } + DBG_PutUnsignedNum(floatVal, DECIMAL, fltCnt); /* print unsigned number */ + cnt += precision; + return cnt; +} + +/** + * @brief Parse the format specifier and print the parameter by format. + * @param ch The format specifier. + * @param paramList The pointer of the variable parameter list. + * @retval unsigned int The total number of characters printed. + */ +static unsigned int ParseSpecifier(const char ch, va_list *paramList) +{ + unsigned int cnt = 0; + unsigned int tmpCnt; + char chVal = 0; + const char *strVal = NULL; + int intVal = 0; + unsigned int unsignedVal = 0; + unsigned int hexVal = 0; + float fltVal = 0; + switch (ch) { + case 'c': /* Character format data. */ + chVal = VA_ARG(*paramList, int); /* Use type int because of byte alignment */ + DBG_PrintCh(chVal); + cnt += 1; + break; + case 's': /* String format data. */ + strVal = VA_ARG(*paramList, const char *); + cnt += DBG_PrintStr(strVal); + break; + case 'd': /* Integer decimal data. */ + intVal = VA_ARG(*paramList, int); + cnt += DBG_PrintInt(intVal); + break; + case 'u': /* Unsigned decimal data. */ + unsignedVal = VA_ARG(*paramList, unsigned int); + tmpCnt = DBG_CountDigits(unsignedVal, DECIMAL); + DBG_PutUnsignedNum(unsignedVal, DECIMAL, tmpCnt); + cnt += tmpCnt; + break; + case 'x': /* Hexadecimal data. */ + case 'X': + case 'p': /* Address data. */ + hexVal = VA_ARG(*paramList, unsigned int); + cnt += DBG_PrintHex(hexVal); + break; + case 'f': /* Floating-point data. */ + fltVal = VA_ARG(*paramList, double); + cnt += DBG_PrintFlt(fltVal, 5); /* default precision: 5 */ + break; + default: + DBG_PrintCh(ch); + cnt += 1; + break; + } + return cnt; +} + +/** + * @brief Print decimal number with field width. + * @param intNum The decimal number to be printed. + * @param fieldWidth Field width. + * @retval unsigned int The total number of characters printed. + */ +static unsigned int DBG_PrintIntWithField(int intNum, int fieldWidth) +{ + int zeroCnt = 0; + int digitsCnt = 0; + unsigned int cnt = 0; + + if (intNum == 0) { + DBG_PrintCh('0'); + return 1; + } + if (intNum < 0) { + DBG_PrintCh('-'); /* add symbol */ + cnt++; + intNum = -intNum; + digitsCnt = DBG_CountDigits(intNum, DECIMAL); /* get int value's width */ + zeroCnt = fieldWidth - digitsCnt; + for (int i = 0; i < zeroCnt; i++) { + DBG_PrintCh('0'); /* add '0' */ + cnt++; + } + cnt += digitsCnt; + } else { + digitsCnt = DBG_CountDigits(intNum, DECIMAL); /* get int value's width */ + cnt = digitsCnt; + zeroCnt = fieldWidth - digitsCnt; + for (int i = 0; i < zeroCnt; i++) { + DBG_PrintCh('0'); /* add '0' */ + cnt++; + } + } + DBG_PutUnsignedNum(intNum, DECIMAL, digitsCnt); + return cnt; +} + +static int DBG_Atoi(const char **s) +{ + int i, c; + + for (i = 0; '0' <= (c = **s) && c <= '9'; ++*s) { + i = i * 10 + c - '0'; /* 10: decimal */ + } + return i; +} + +/** + * @brief Print format string through UART port, supporting %c, %s, %d, %u, %x, %X, %p, %f. + * %c To print a character. + * %s To print a string. + * %d To print a decimal value. + * %u To print an unsigned decimal value. + * %x, %X To print a hexadecimal value using upper case letters. + * %p To print a pointer as a hexadecimal value. + * %f To print a floating-point number with a fixed precision determined by FLOAT_PRECISION. + * @param format A string that contains the text to be printed and the format specifiers. + * @param ... Variable parameter list. + * @retval int If succeeded, the total number of characters printed is returned. + * If the input parameter is wrong, return BASE_STATUS_ERROR. + */ +int DBG_UartPrintf(const char *format, ...) +{ + DEBUG_ASSERT_PARAM(format != NULL); + int cnt = 0; + int fieldWidth = 0; + int floatPrecision = 0; + float fltVal = 0; + int intVal = 0; + va_list paramList; + VA_START(paramList, format); + + while (*format != '\0') { + if (*format != '%') { + DBG_PrintCh(*format); + cnt += 1; + } else { + format++; + if (*format == '0') { + format++; + fieldWidth = DBG_Atoi(&format); + intVal = VA_ARG(paramList, int); + cnt += DBG_PrintIntWithField(intVal, fieldWidth); + } else if (*format == '.') { + format++; + floatPrecision = DBG_Atoi(&format); + fltVal = VA_ARG(paramList, double); + cnt += DBG_PrintFlt(fltVal, floatPrecision); + } else { + cnt += ParseSpecifier(*format, ¶mList); + } + } + format++; + } + VA_END(paramList); + return cnt; +} +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/dma/common/inc/dma.h b/vendor/xinlingyu_92_3061M/Project/drivers/dma/common/inc/dma.h new file mode 100644 index 0000000000000000000000000000000000000000..acd7381b38059bb360c7643c23926bcd8389479f --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/dma/common/inc/dma.h @@ -0,0 +1,134 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dma.h + * @author MCU Driver Team + * @brief DMA module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the DMA. + * + The definition of the DMA handle structure. + * + Initialization and de-initialization functions + * + Peripheral querying the transmission functions. + * + Peripheral interrupt handler and callback registration functions. + */ + +/* Includes ------------------------------------------------------------------*/ +#ifndef McuMagicTag_DMA_H +#define McuMagicTag_DMA_H +#include "dma_ip.h" + +/** + * @defgroup DMA DMA + * @brief DMA module. + * @{ + */ + +/** + * @defgroup DMA_Common DMA Common + * @brief DMA common external module. + * @{ + */ + +/** + * @defgroup DMA_Handle_Definition DMA Handle Definition + * @{ + */ + +/** + * @brief The definition of the DMA handle structure. + */ +typedef struct _DMA_Handle { + DMA_RegStruct *baseAddress; /**< DMA common registers base address */ + struct { + DMA_ChannelRegStruct *channelAddr; /**< DMA channel registers base address */ + DMA_TransDirection direction; /**< The transmission direction type */ + DMA_RequestLineNum srcPeriph; /**< Source device request line, memory ignore configuration */ + DMA_RequestLineNum destPeriph; /**< Destination device request line, memory ignore configuration */ + DMA_AddrIncMode srcAddrInc; /**< Address increase configuration of source device */ + DMA_AddrIncMode destAddrInc; /**< Address increase configuration of destination device */ + DMA_BurstLength srcBurst; /**< Burst length of source device */ + DMA_BurstLength destBurst; /**< Burst length of destination device */ + DMA_TransmisWidth srcWidth; /**< Transfer width of source device */ + DMA_TransmisWidth destWidth; /**< Transfer width of destination device */ + void *pHandle; /**< Handle of the modules that use the DMA */ + unsigned int srcAddr; /**< Readback value from the source address to the register */ + unsigned int destAddr; /**< Readback value from the destnation address to the register */ + unsigned int controlVal; /**< Readback value of the DMA control register */ + unsigned int configVal; /**< Readback value of the DMA configuration register */ + } DMA_Channels[CHANNEL_MAX_NUM]; + DMA_UserCallBack userCallBack; /**< User callback */ + DMA_ExtendHandle handleEx; /**< DMA extend parameter */ +} DMA_Handle; + +/** + * @brief The definition of the DMA channel param structure. + */ +typedef struct { + DMA_RequestLineNum srcPeriph; /**< Source device request line, memory ignore configuration */ + DMA_RequestLineNum destPeriph; /**< Destination device request line, memory ignore configuration */ + DMA_TransDirection direction; /**< The transmission direction type */ + DMA_AddrIncMode srcAddrInc; /**< Address increase configuration of source device */ + DMA_AddrIncMode destAddrInc; /**< Address increase configuration of destination device */ + DMA_BurstLength srcBurst; /**< Burst length of source device */ + DMA_BurstLength destBurst; /**< Burst length of destination device */ + DMA_TransmisWidth srcWidth; /**< Transfer width of source device */ + DMA_TransmisWidth destWidth; /**< Transfer width of destination device */ + void *pHandle; /**< Parameter handle of the users callback function */ +} DMA_ChannelParam; + +typedef void (* DMA_CallbackType)(void *handle); +/** + * @} + */ + +/** + * @defgroup DMA_API_Declaration DMA HAL API + * @{ + */ +/* Hardware abstraction layer */ +BASE_StatusType HAL_DMA_Init(DMA_Handle *dmaHandle); +BASE_StatusType HAL_DMA_Deinit(DMA_Handle *dmaHandle); +BASE_StatusType HAL_DMA_Start(DMA_Handle *dmaHandle, unsigned int srcAddr, + unsigned int destAddr, unsigned int dataLength, unsigned int channel); +BASE_StatusType HAL_DMA_StartIT(DMA_Handle *dmaHandle, unsigned int srcAddr, + unsigned int destAddr, unsigned int dataLength, unsigned int channel); +BASE_StatusType HAL_DMA_StopChannel(DMA_Handle *dmaHandle, unsigned int channel); +BASE_StatusType HAL_DMA_GetChannelState(DMA_Handle *dmaHandle, unsigned int channel); +BASE_StatusType HAL_DMA_InitChannel(DMA_Handle *dmaHandle, DMA_ChannelParam *channelParam, unsigned int channel); +void HAL_DMA_IrqHandlerTc(void *handle); +void HAL_DMA_IrqHandlerError(void *handle); +void HAL_DMA_RegisterCallback(DMA_Handle *dmaHandle, DMA_CallbackFun_Type typeID, + DMA_ChannelNum channel, DMA_CallbackType pCallback); +BASE_StatusType HAL_DMA_ListAddNode(DMA_LinkList *head, DMA_LinkList *newNode); +BASE_StatusType HAL_DMA_InitNewNode(DMA_LinkList *node, const DMA_ChannelParam *param, + unsigned int srcAddr, unsigned int destAddr, unsigned int tranSize); +BASE_StatusType HAL_DMA_StartListTransfer(DMA_Handle *dmaHandle, DMA_LinkList *head, unsigned int channel); +#ifdef BASE_DEFINE_DMA_QUICKSTART +void HAL_DMA_QuickStart(DMA_Handle *dmaHandle, unsigned int channel); +#endif +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_DMA_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/dma/inc/dma_ex.h b/vendor/xinlingyu_92_3061M/Project/drivers/dma/inc/dma_ex.h new file mode 100644 index 0000000000000000000000000000000000000000..1cf910d31094096cac081da6a4d7a56f37f56540 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/dma/inc/dma_ex.h @@ -0,0 +1,50 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dma_ex.h + * @author MCU Driver Team + * @brief DMA module driver + * @details This file provides firmware functions to manage the following. + * functionalities of the DMA. + * + DMA Set Functions + */ + +#ifndef McuMagicTag_DMA_EX_H +#define McuMagicTag_DMA_EX_H + +#include "dma.h" + +/* Macro definitions ---------------------------------------------------------*/ +/** + * @addtogroup DMA_IP + * @{ + */ + +/** + * @defgroup DMA_EX_API_Declaration DMA HAL API EX + * @{ + */ + +void HAL_DMA_SetChannelPriorityEx(DMA_Handle *dmaHandle, unsigned int channel, DMA_ChannelPriority priority); +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_DMA_EX_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/dma/inc/dma_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/dma/inc/dma_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..156b280f51c84d94ea6415b5cd2c433bd8615005 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/dma/inc/dma_ip.h @@ -0,0 +1,919 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dma_ip.h + * @author MCU Driver Team + * @brief DMA module driver + * @details This file provides DCL functions to manage DMA and Definition of + * specific parameters. + * + Definition of DMA configuration parameters. + * + DMA register mapping structure. + * + Parameters check functions. + * + Direct configuration layer interface. + */ + +#ifndef McuMagicTag_DMA_IP_H +#define McuMagicTag_DMA_IP_H + +#include "baseinc.h" +#define CHANNEL_MAX_NUM 6 + +#define TRANSIZE_MAX 4095 +#define TRANS_BLOCK 4092 + +#ifdef DMA_PARAM_CHECK +#define DMA_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define DMA_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define DMA_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define DMA_ASSERT_PARAM(para) ((void)0U) +#define DMA_PARAM_CHECK_NO_RET(para) ((void)0U) +#define DMA_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +/** + * @addtogroup DMA + * @{ + */ + +/** + * @defgroup DMA_IP DMA_IP + * @brief DMA_IP: dma_v1. + * @{ + */ + +/** + * @defgroup DMA_Param_Def DMA Parameters Definition + * @brief Description of DMA configuration parameters. + * @{ + */ + +/** + * @brief Indicates the burst length of the destination device and the source device. + */ +typedef enum { + DMA_BURST_LENGTH_1 = 0x00000000U, + DMA_BURST_LENGTH_4 = 0x00000001U, + DMA_BURST_LENGTH_8 = 0x00000002U, + DMA_BURST_LENGTH_16 = 0x00000003U, + DMA_BURST_LENGTH_32 = 0x00000004U, + DMA_BURST_LENGTH_64 = 0x00000005U, + DMA_BURST_LENGTH_128 = 0x00000006U, + DMA_BURST_LENGTH_256 = 0x00000007U +} DMA_BurstLength; + +/** + * @brief DMA transfer width definition. + */ +typedef enum { + DMA_TRANSWIDTH_BYTE = 0x00000000U, + DMA_TRANSWIDTH_HALFWORD = 0x00000001U, + DMA_TRANSWIDTH_WORD = 0x00000002U +} DMA_TransmisWidth; + +/** + * @brief DMA channel ID, a smaller channel ID indicates a higher priority. + */ +typedef enum { + DMA_CHANNEL_ZERO = 0x00000000U, + DMA_CHANNEL_ONE = 0x00000001U, + DMA_CHANNEL_TWO = 0x00000002U, + DMA_CHANNEL_THREE = 0x00000003U, + DMA_CHANNEL_FOUR = 0x00000004U, + DMA_CHANNEL_FIVE = 0x00000005U, +} DMA_ChannelNum; + +/** + * @brief DMA callback type. + */ +typedef enum { + DMA_CHANNEL_FINISH = 0x00000000U, + DMA_CHANNEL_ERROR = 0x00000001U +} DMA_CallbackFun_Type; + +/** + * @brief DMA channel priority. + */ +typedef enum { + DMA_PRIORITY_LOW = 0x00000000U, + DMA_PRIORITY_MEDIUM = 0x00000001U, + DMA_PRIORITY_HIGH = 0x00000002U, + DMA_PRIORITY_HIGHEST = 0x00000003U, +} DMA_ChannelPriority; + +/** + * @brief DMA request peripheral. The multiplexed transmitter requires additional + * configuration of the system register. + * @details DMA request line type: + * + DMA_REQUEST_I2C0_RX -- I2C0_RX use the request line numbered 0 + * + DMA_REQUEST_I2C0_TX -- I2C0_TX use the request line numbered 1 + * + DMA_REQUEST_I2C1_RX -- I2C1_RX use the request line numbered 2 + * + DMA_REQUEST_I2C1_TX -- I2C1_RX use the request line numbered 3 + * + DMA_REQUEST_UART0_RX -- UART0_TX use the request line numbered 4 + * + DMA_REQUEST_UART0_TX -- UART0_TX use the request line numbered 5 + * + DMA_REQUEST_UART1_RX -- UART1_RX use the request line numbered 6 + * + DMA_REQUEST_UART1_TX -- UART1_TX use the request line numbered 7 + * + DMA_REQUEST_UART2_RX -- UART2_RX use the request line numbered 8 + * + DMA_REQUEST_UART2_TX -- UART2_TX use the request line numbered 9 + * + DMA_REQUEST_UART3_RX -- UART3_RX use the request line numbered 30 + * + DMA_REQUEST_UART3_TX -- UART3_TX use the request line numbered 31 + * + DMA_REQUEST_CAPM0 -- CAPM0 use the request line numbered 10 + * + DMA_REQUEST_CAPM1 -- CAPM1 use the request line numbered 11 + * + DMA_REQUEST_CAPM2 -- CAPM2 use the request line numbered 12 + * + DMA_REQUEST_ADC0 -- ADC0 use the request line numbered 13 + * + DMA_REQUEST_TIMER0 -- TIMER0 use the request line numbered 14 + * + DMA_REQUEST_TIMER1 -- TIMER1 use the request line numbered 15 + * + DMA_REQUEST_TIMER2 -- TIMER2 use the request line numbered 16 + * + DMA_REQUEST_TIMER3 -- TIMER3 use the request line numbered 17 + * + DMA_REQUEST_SPI0_RX -- SPI0_RX ause the request line numbered 18 + * + DMA_REQUEST_SPI0_TX -- SPI0_TX use the request line numbered 19 + * + DMA_REQUEST_SPI1_RX -- SPI1_RX use the request line numbered 20 + * + DMA_REQUEST_SPI1_TX -- SPI1_TX use the request line numbered 21 + * + DMA_REQUEST_APT0 -- APT0 use the request line numbered 22 + * + DMA_REQUEST_APT1 -- APT1 use the request line numbered 23 + * + DMA_REQUEST_APT2 -- APT2 use the request line numbered 24 + * + DMA_REQUEST_APT3 -- APT3 use the request line numbered 25 + * + DMA_REQUEST_GPT0 -- GPT0 use the request line numbered 26 + * + DMA_REQUEST_GPT1 -- GPT1 use the request line numbered 27 + * + DMA_REQUEST_GPT2 -- GPT2 use the request line numbered 28 + * + DMA_REQUEST_GPT3 -- GPT3 use the request line numbered 29 + * + DMA_REQUEST_MEM -- The source and destination devices are memory + */ +typedef enum { + DMA_REQUEST_I2C0_RX = 0x00000000U, + DMA_REQUEST_I2C0_TX = 0x00000001U, + DMA_REQUEST_I2C1_RX = 0x00000002U, + DMA_REQUEST_I2C1_TX = 0x00000003U, + DMA_REQUEST_UART0_RX = 0x00000004U, + DMA_REQUEST_UART0_TX = 0x00000005U, + DMA_REQUEST_UART1_RX = 0x00000006U, + DMA_REQUEST_UART1_TX = 0x00000007U, + DMA_REQUEST_UART2_RX = 0x00000008U, + DMA_REQUEST_UART2_TX = 0x00000009U, + DMA_REQUEST_UART3_RX = 0x0000001EU, + DMA_REQUEST_UART3_TX = 0x0000001FU, + DMA_REQUEST_CAPM0 = 0x0000000AU, + DMA_REQUEST_CAPM1 = 0x0000000BU, + DMA_REQUEST_CAPM2 = 0x0000000CU, + DMA_REQUEST_ADC0 = 0x0000000DU, + DMA_REQUEST_TIMER0 = 0x0000000EU, + DMA_REQUEST_TIMER1 = 0x0000000FU, + DMA_REQUEST_TIMER2 = 0x00000010U, + DMA_REQUEST_TIMER3 = 0x00000011U, + DMA_REQUEST_SPI0_RX = 0x00000012U, + DMA_REQUEST_SPI0_TX = 0x00000013U, + DMA_REQUEST_SPI1_RX = 0x00000014U, + DMA_REQUEST_SPI1_TX = 0x00000015U, + DMA_REQUEST_APT0 = 0x00000016U, + DMA_REQUEST_APT1 = 0x00000017U, + DMA_REQUEST_APT2 = 0x00000018U, + DMA_REQUEST_APT3 = 0x00000019U, + DMA_REQUEST_GPT0 = 0x0000001AU, + DMA_REQUEST_GPT1 = 0x0000001BU, + DMA_REQUEST_GPT2 = 0x0000001CU, + DMA_REQUEST_GPT3 = 0x0000001DU, + DMA_REQUEST_MEM = 0x00000020U, +} DMA_RequestLineNum; + +/** + * @brief DMA peripheral request line. The multiplexed transmitter requires additional + * configuration of the system register. + */ +typedef enum { + DMA_REQLINEVAL_0 = 0x00000000U, + DMA_REQLINEVAL_1 = 0x00000001U, + DMA_REQLINEVAL_2 = 0x00000002U, + DMA_REQLINEVAL_3 = 0x00000003U, + DMA_REQLINEVAL_4 = 0x00000004U, + DMA_REQLINEVAL_5 = 0x00000005U, + DMA_REQLINEVAL_6 = 0x00000006U, + DMA_REQLINEVAL_7 = 0x00000007U, + DMA_REQLINEVAL_8 = 0x00000008U, + DMA_REQLINEVAL_9 = 0x00000009U, + DMA_REQLINEVAL_10 = 0x0000000AU, + DMA_REQLINEVAL_11 = 0x0000000BU, + DMA_REQLINEVAL_12 = 0x0000000CU, + DMA_REQLINEVAL_13 = 0x0000000DU, + DMA_REQLINEVAL_14 = 0x0000000EU, + DMA_REQLINEVAL_15 = 0x0000000FU +} DMA_ReqLineVal; + +/** + * @brief Configuration value definition of the peripheral multiplexing DMA request line. + */ +typedef enum { + DMA_SYSCTRLSET_0 = 0x00000000U, + DMA_SYSCTRLSET_1 = 0x00000001U, + DMA_SYSCTRLSET_2 = 0x00000002U +} DMA_SysctrlSet; + +/** + * @brief DMA Transfer Byte Order. + */ +typedef enum { + DMA_BYTEORDER_SMALLENDIAN = 0x00000000U, + DMA_BYTEORDER_BIGENDIAN = 0x00000001U +} DMA_ByteOrder; + +/** + * @brief Define the transmission direction type and data flow controller. + * @details Transmission direction type: + * + DMA_MEMORY_TO_MEMORY_BY_DMAC -- Direc: memory to memory, control: DMA + * + DMA_MEMORY_TO_PERIPH_BY_DMAC -- Direc: memory to peripheral, control: DMA + * + DMA_PERIPH_TO_MEMORY_BY_DMAC -- Direc: peripheral to memory, control: DMA + * + DMA_PERIPH_TO_PERIPH_BY_DMAC -- irec: peripheral to peripheral, control: DMA + * + DMA_PERIPH_TO_PERIPH_BY_DES -- Direc: peripheral to peripheral, control: destination peripheral + * + DMA_MEMORY_TO_PERIPH_BY_DES -- Direc: memory to peripheral, control: destination peripheral + * + DMA_PERIPH_TO_MEMORY_BY_SRC -- Direc: peripheral to memory, control: source peripheral + * + DMA_PERIPH_TO_PERIPH_BY_SRC -- Direc: peripheral to peripheral, control: source peripheral + */ +typedef enum { + DMA_MEMORY_TO_MEMORY_BY_DMAC = 0x00000000U, + DMA_MEMORY_TO_PERIPH_BY_DMAC = 0x00000001U, + DMA_PERIPH_TO_MEMORY_BY_DMAC = 0x00000002U, + DMA_PERIPH_TO_PERIPH_BY_DMAC = 0x00000003U, + DMA_PERIPH_TO_PERIPH_BY_DES = 0x00000004U, + DMA_MEMORY_TO_PERIPH_BY_DES = 0x00000005U, + DMA_PERIPH_TO_MEMORY_BY_SRC = 0x00000006U, + DMA_PERIPH_TO_PERIPH_BY_SRC = 0x00000007U +} DMA_TransDirection; + +/** + * @brief Address increase configuration. Peripherals can only be set to unaltered, memory can be set to two mode. + */ +typedef enum { + DMA_ADDR_UNALTERED = 0x00000000U, + DMA_ADDR_INCREASE = 0x00000001U +} DMA_AddrIncMode; + +/** + * @brief DMA extend handle. + */ +typedef struct _DMA_ExtendHandle { +} DMA_ExtendHandle; + +/** + * @brief DMA user callback. + */ +typedef struct { + struct { + void (* ChannelFinishCallBack)(void *handle); + void (* ChannelErrorCallBack)(void *handle); + } DMA_CallbackFuns[CHANNEL_MAX_NUM]; +} DMA_UserCallBack; +/** + * @} + */ + +/** + * @defgroup DMA_Reg_Def DMA Register Definition + * @brief Description DMA register mapping structure. + * @{ + */ + +/** + * @brief DMA interrupt status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ch0_int_stat : 1; /**< Masked interrupt status of channel 0. */ + unsigned int ch1_int_stat : 1; /**< Masked interrupt status of channel 1. */ + unsigned int ch2_int_stat : 1; /**< Masked interrupt status of channel 2. */ + unsigned int ch3_int_stat : 1; /**< Masked interrupt status of channel 3. */ + unsigned int ch4_int_stat : 1; /**< Masked interrupt status of channel 4. */ + unsigned int ch5_int_stat : 1; /**< Masked interrupt status of channel 5. */ + unsigned int reserved0 : 26; + } BIT; +} volatile DMA_INT_STAT_REG; + +/** + * @brief DMA transfer completion interrupt status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ch0_int_tc_stat : 1; /**< Masked transfer completion interrupt status of channel 0. */ + unsigned int ch1_int_tc_stat : 1; /**< Masked transfer completion interrupt status of channel 1. */ + unsigned int ch2_int_tc_stat : 1; /**< Masked transfer completion interrupt status of channel 2. */ + unsigned int ch3_int_tc_stat : 1; /**< Masked transfer completion interrupt status of channel 3. */ + unsigned int ch4_int_tc_stat : 1; /**< Masked transfer completion interrupt status of channel 4. */ + unsigned int ch5_int_tc_stat : 1; /**< Masked transfer completion interrupt status of channel 5. */ + unsigned int reserved0 : 26; + } BIT; +} volatile DMA_INT_TC_STAT_REG; + +/** + * @brief DMA transfer completion interrupt clear register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ch0_int_tc_clr : 1; /**< Clear the channel 0 transfer completion interrupt. */ + unsigned int ch1_int_tc_clr : 1; /**< Clear the channel 1 transfer completion interrupt. */ + unsigned int ch2_int_tc_clr : 1; /**< Clear the channel 2 transfer completion interrupt. */ + unsigned int ch3_int_tc_clr : 1; /**< Clear the channel 3 transfer completion interrupt. */ + unsigned int ch4_int_tc_clr : 1; /**< Clear the channel 4 transfer completion interrupt. */ + unsigned int ch5_int_tc_clr : 1; /**< Clear the channel 5 transfer completion interrupt. */ + unsigned int reserved0 : 26; + } BIT; +} volatile DMA_INT_TC_CLR_REG; + +/** + * @brief DMA error interrupt status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ch0_int_err_stat : 1; /**< Masked error interrupt status of channel 0. */ + unsigned int ch1_int_err_stat : 1; /**< Masked error interrupt status of channel 1. */ + unsigned int ch2_int_err_stat : 1; /**< Masked error interrupt status of channel 2. */ + unsigned int ch3_int_err_stat : 1; /**< Masked error interrupt status of channel 3. */ + unsigned int ch4_int_err_stat : 1; /**< Masked error interrupt status of channel 4. */ + unsigned int ch5_int_err_stat : 1; /**< Masked error interrupt status of channel 5. */ + unsigned int reserved0 : 26; + } BIT; +} volatile DMA_INT_ERR_STAT_REG; + +/** + * @brief DMA error interrupt clear register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ch0_int_err_clr : 1; /**< Clear channel 0 error interrupt. */ + unsigned int ch1_int_err_clr : 1; /**< Clear channel 1 error interrupt. */ + unsigned int ch2_int_err_clr : 1; /**< Clear channel 2 error interrupt. */ + unsigned int ch3_int_err_clr : 1; /**< Clear channel 3 error interrupt. */ + unsigned int ch4_int_err_clr : 1; /**< Clear channel 4 error interrupt. */ + unsigned int ch5_int_err_clr : 1; /**< Clear channel 5 error interrupt. */ + unsigned int reserved0 : 26; + } BIT; +} volatile DMA_INT_ERR_CLR_REG; + +/** + * @brief DMA raw transfer completion interrupt register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ch0_raw_int_tc : 1; /**< Raw transfer completion interrupt status of channel 0. */ + unsigned int ch1_raw_int_tc : 1; /**< Raw transfer completion interrupt status of channel 1. */ + unsigned int ch2_raw_int_tc : 1; /**< Raw transfer completion interrupt status of channel 2. */ + unsigned int ch3_raw_int_tc : 1; /**< Raw transfer completion interrupt status of channel 3. */ + unsigned int ch4_raw_int_tc : 1; /**< Raw transfer completion interrupt status of channel 4. */ + unsigned int ch5_raw_int_tc : 1; /**< Raw transfer completion interrupt status of channel 5. */ + unsigned int reserved0 : 26; + } BIT; +} volatile DMA_RAW_INT_TC_STAT_REG; + +/** + * @brief DMA raw error interrupt register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ch0_raw_int_err : 1; /**< Raw error interrupt status of channel 0. */ + unsigned int ch1_raw_int_err : 1; /**< Raw error interrupt status of channel 1. */ + unsigned int ch2_raw_int_err : 1; /**< Raw error interrupt status of channel 2. */ + unsigned int ch3_raw_int_err : 1; /**< Raw error interrupt status of channel 3. */ + unsigned int ch4_raw_int_err : 1; /**< Raw error interrupt status of channel 4. */ + unsigned int ch5_raw_int_err : 1; /**< Raw error interrupt status of channel 5. */ + unsigned int reserved0 : 26; + } BIT; +} volatile DMA_RAW_INT_ERR_STAT_REG; + +/** + * @brief DMA channel enable status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ch0_enabled : 1; /**< Channel 0 enable status. */ + unsigned int ch1_enabled : 1; /**< Channel 1 enable status. */ + unsigned int ch2_enabled : 1; /**< Channel 2 enable status. */ + unsigned int ch3_enabled : 1; /**< Channel 3 enable status. */ + unsigned int ch4_enabled : 1; /**< Channel 4 enable status. */ + unsigned int ch5_enabled : 1; /**< Channel 5 enable status. */ + unsigned int reserved0 : 26; + } BIT; +} volatile DMA_ENABLED_CHNS_REG; + +/** + * @brief DMA parameter configuration register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int dma_enable : 1; /**< DMA controller enable. */ + unsigned int reserved0 : 31; + } BIT; +} volatile DMA_CONFIG_REG; + + +/** + * @brief DMA request line synchronization enable. + */ +typedef union { + unsigned int reg; + struct { + unsigned int dma_sync_disable : 32; /**< Control whether the request line needs to be synchronized.. */ + } BIT; +} volatile DMA_SYNC_REG; + +/** + * @brief Source address register of DMA channel n (n = 0, 1, 2, 3). + */ +typedef union { + unsigned int reg; + struct { + unsigned int src_addr : 32; /**< DMA source address. */ + } BIT; +} volatile DMA_Cn_SRC_ADDR_REG; + +/** + * @brief Destination address register of DMA channel n (n = 0, 1, 2, 3). + */ +typedef union { + unsigned int reg; + struct { + unsigned int dest_addr : 32; /**< DMA destination address. */ + } BIT; +} volatile DMA_Cn_DEST_ADDR_REG; + +/** + * @brief Linked list information register for DMA channel n (n = 0, 1, 2, 3). + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 2; + unsigned int ll_item : 30; /**< Address of the next linked list node. */ + } BIT; +} volatile DMA_Cn_LLI_REG; + +/** + * @brief DMA channel n (n = 0, 1, 2, 3) control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int trans_size : 12; /**< Length of the DMA transfer, provided that the DMA flow controller. */ + unsigned int sbsize : 3; /**< Burst length of the source device. */ + unsigned int dbsize : 3; /**< Burst length of the destination device. */ + unsigned int swidth : 3; /**< Transfer bit width of the source device, + which cannot be greater than Master bit width. */ + unsigned int dwidth : 3; /**< Transfer bit width of the destination device, + which cannot be greater than Master bit width. */ + unsigned int reserved0 : 2; + unsigned int src_incr : 1; /**< Set the incremental mode of the source address. */ + unsigned int dest_incr : 1; /**< Set the incremental mode of the destination address. */ + unsigned int reserved1 : 3; + unsigned int int_tc_enable : 1; /**< Transfer completion interrupt enable. */ + } BIT; +} volatile DMA_Cn_CONTROL_REG; + +/** + * @brief DMA channel n (n = 0, 1, 2, 3) configuration register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ch_en : 1; /**< Channel enable. */ + unsigned int src_periph : 5; /**< Source device, ignore this field if memory device. */ + unsigned int dest_periph : 5; /**< Destination device, ignore this field if memory device. */ + unsigned int flow_ctrl : 3; /**< Flow control and transmission Type. */ + unsigned int err_int_msk : 1; /**< Error interrupt mask flag. */ + unsigned int tc_int_msk : 1; /**< Transfer completion interrupt mask flag. */ + unsigned int ch_lock : 1; /**< Lock transmission enable on the bus. */ + unsigned int ch_active : 1; /**< Whether the data in the channel FIFO. */ + unsigned int ch_halt : 1; /**< Whether ignore DMA requests. */ + unsigned int reserved0 : 5; + unsigned int ch_priority : 2; /**< Channel Priority, larger value indicates a higher priority. */ + unsigned int reserved1 : 6; + } BIT; +} volatile DMA_Cn_CONFIG_REG; + +/** + * @brief DMA register mapping structure. + */ +typedef struct { + DMA_INT_STAT_REG DMA_INT_STAT; /**< DMA interrupt status register. + Offset address: 0x00000000U. */ + DMA_INT_TC_STAT_REG DMA_INT_TC_STAT; /**< DMA transfer completion interrupt status register. + Offset address: 0x00000004U. */ + DMA_INT_TC_CLR_REG DMA_INT_TC_CLR; /**< DMA transfer completion interrupt clear register. + Offset address: 0x00000008U. */ + DMA_INT_ERR_STAT_REG DMA_INT_ERR_STAT; /**< DMA error interrupt status register. + Offset address: 0x0000000CU. */ + DMA_INT_ERR_CLR_REG DMA_INT_ERR_CLR; /**< DMA error interrupt clear register. + Offset address: 0x00000010U. */ + DMA_RAW_INT_TC_STAT_REG DMA_RAW_INT_TC_STAT; /**< DMA raw transfer completion interrupt register. + Offset address: 0x00000014U. */ + DMA_RAW_INT_ERR_STAT_REG DMA_RAW_INT_ERR_STAT; /**< DMA raw error interrupt register. + Offset address: 0x00000018U. */ + DMA_ENABLED_CHNS_REG DMA_ENABLED_CHNS; /**< DMA channel enable status register. + Offset address: 0x0000001CU. */ + unsigned char space0[16]; + DMA_CONFIG_REG DMA_CONFIG; /**< DMA parameter configuration register. + Offset address: 0x00000030U. */ + DMA_SYNC_REG DMA_SYNC; /**< DMA request line synchronization enable. + Offset address: 0x00000034U. */ + unsigned char space1[200]; + DMA_Cn_SRC_ADDR_REG DMA_C0_SRC_ADDR; /**< Source address register of DMA channel 0. + Offset address: 0x00000100U. */ + DMA_Cn_DEST_ADDR_REG DMA_C0_DEST_ADDR; /**< Destination address register of DMA channel 0. + Offset address: 0x00000104U. */ + DMA_Cn_LLI_REG DMA_C0_LLI; /**< Linked list information register for DMA channel 0. + Offset address: 0x00000108U. */ + DMA_Cn_CONTROL_REG DMA_C0_CONTROL; /**< DMA channel 0 control register. + Offset address: 0x0000010CU. */ + DMA_Cn_CONFIG_REG DMA_C0_CONFIG; /**< DMA channel 0 configuration register. + Offset address: 0x00000110U. */ + unsigned char space2[12]; + DMA_Cn_SRC_ADDR_REG DMA_C1_SRC_ADDR; /**< Source address register of DMA channel 1. + Offset address: 0x00000120U. */ + DMA_Cn_DEST_ADDR_REG DMA_C1_DEST_ADDR; /**< Destination address register of DMA channel 1. + Offset address: 0x00000124U. */ + DMA_Cn_LLI_REG DMA_C1_LLI; /**< Linked list information register for DMA channel 1. + Offset address: 0x00000128U. */ + DMA_Cn_CONTROL_REG DMA_C1_CONTROL; /**< DMA channel 1 control register. + Offset address: 0x0000012CU. */ + DMA_Cn_CONFIG_REG DMA_C1_CONFIG; /**< DMA channel 1 configuration register. + Offset address: 0x00000130U. */ + unsigned char space3[12]; + DMA_Cn_SRC_ADDR_REG DMA_C2_SRC_ADDR; /**< Source address register of DMA channel 2. + Offset address: 0x00000140U. */ + DMA_Cn_DEST_ADDR_REG DMA_C2_DEST_ADDR; /**< Destination address register of DMA channel 2. + Offset address: 0x00000144U. */ + DMA_Cn_LLI_REG DMA_C2_LLI; /**< Linked list information register for DMA channel 2. + Offset address: 0x00000148U. */ + DMA_Cn_CONTROL_REG DMA_C2_CONTROL; /**< DMA channel 2 control register. + Offset address: 0x0000014CU. */ + DMA_Cn_CONFIG_REG DMA_C2_CONFIG; /**< DMA channel 2 configuration register. + Offset address: 0x00000150U. */ + unsigned char space4[12]; + DMA_Cn_SRC_ADDR_REG DMA_C3_SRC_ADDR; /**< Source address register of DMA channel 3. + Offset address: 0x00000160U. */ + DMA_Cn_DEST_ADDR_REG DMA_C3_DEST_ADDR; /**< Destination address register of DMA channel 3. + Offset address: 0x00000164U. */ + DMA_Cn_LLI_REG DMA_C3_LLI; /**< Linked list information register for DMA channel 3. + Offset address: 0x00000168U. */ + DMA_Cn_CONTROL_REG DMA_C3_CONTROL; /**< DMA channel 3 control register. + Offset address: 0x0000016CU. */ + DMA_Cn_CONFIG_REG DMA_C3_CONFIG; /**< DMA channel 3 configuration register. + Offset address: 0x00000170U. */ + unsigned char space5[12]; + DMA_Cn_SRC_ADDR_REG DMA_C4_SRC_ADDR; /**< Source address register of DMA channel 4. + Offset address: 0x00000180U. */ + DMA_Cn_DEST_ADDR_REG DMA_C4_DEST_ADDR; /**< Destination address register of DMA channel 4. + Offset address: 0x00000184U. */ + DMA_Cn_LLI_REG DMA_C4_LLI; /**< Linked list information register for DMA channel 4. + Offset address: 0x00000188U. */ + DMA_Cn_CONTROL_REG DMA_C4_CONTROL; /**< DMA channel 4 control register. + Offset address: 0x0000018CU. */ + DMA_Cn_CONFIG_REG DMA_C4_CONFIG; /**< DMA channel 4 configuration register. + Offset address: 0x00000190U. */ + unsigned char space6[12]; + DMA_Cn_SRC_ADDR_REG DMA_C5_SRC_ADDR; /**< Source address register of DMA channel 5. + Offset address: 0x00000200U. */ + DMA_Cn_DEST_ADDR_REG DMA_C5_DEST_ADDR; /**< Destination address register of DMA channel 5. + Offset address: 0x00000204U. */ + DMA_Cn_LLI_REG DMA_C5_LLI; /**< Linked list information register for DMA channel 5. + Offset address: 0x00000208U. */ + DMA_Cn_CONTROL_REG DMA_C5_CONTROL; /**< DMA channel 5 control register. + Offset address: 0x0000020CU. */ + DMA_Cn_CONFIG_REG DMA_C5_CONFIG; /**< DMA channel 5 configuration register. + Offset address: 0x00000210U. */ +} volatile DMA_RegStruct; + +/** + * @brief Channel register mapping structure. + */ +typedef struct { + DMA_Cn_SRC_ADDR_REG DMA_Cn_SRC_ADDR; /**< Source address register of DMA channel. */ + DMA_Cn_DEST_ADDR_REG DMA_Cn_DEST_ADDR; /**< Destination address register of DMA channel. */ + DMA_Cn_LLI_REG DMA_Cn_LLI; /**< Linked list information register for DMA channel. */ + DMA_Cn_CONTROL_REG DMA_Cn_CONTROL; /**< DMA channel control register. */ + DMA_Cn_CONFIG_REG DMA_Cn_CONFIG; /**< DMA channel configuration register. */ +} volatile DMA_ChannelRegStruct; + +/** + * @brief DMA linked list structure. + */ +typedef struct _DMA_LinkList { + unsigned int srcAddr; /**< Source device start address. */ + unsigned int destAddr; /**< Destination device start address. */ + struct _DMA_LinkList *lliNext; /**< Pointer to the next node. */ + DMA_Cn_CONTROL_REG control; /**< Channel parameters configured for the node. */ +} DMA_LinkList; + +/** + * @brief A large amount of block data needs to be Splitd. Split functions need to transfer the following structure. + */ +typedef struct { + unsigned int srcAddr; /**< Source device start address. */ + unsigned int destAddr; /**< Destination device start address. */ + unsigned int srcIn; /**< Source address single increment size. */ + unsigned int destIn; /**< destnation address single increment size. */ + unsigned int chnParam; /**< Channel parameters configured for the splited node. */ + unsigned int totalSize; /**< Total amount of block data. */ +} DMA_SplitParam; +/** + * @} + */ + + +/** + * @brief Check DMA channel num parameter. + * @param channel The number of channel. + * @retval bool + */ +static inline bool IsDmaChannelNum(DMA_ChannelNum channel) +{ + /* channel 0-5 */ + if ((channel == DMA_CHANNEL_ZERO) || (channel == DMA_CHANNEL_ONE) || + (channel == DMA_CHANNEL_TWO) || (channel == DMA_CHANNEL_THREE) || + (channel == DMA_CHANNEL_FOUR) || (channel == DMA_CHANNEL_FIVE)) { + return true; + } + return false; +} + +/** + * @brief Check DMA channel transfer width. + * @param width DMA transfer width. + * @retval bool + */ +static inline bool IsDmaWidth(DMA_TransmisWidth width) +{ + if ((width == DMA_TRANSWIDTH_BYTE) || + (width == DMA_TRANSWIDTH_HALFWORD) || + (width == DMA_TRANSWIDTH_WORD)) { + return true; + } + return false; +} + +/** + * @brief Check DMA channel burst length. + * @param burstLength DMA transfer burst length. + * @retval bool + */ +static inline bool IsDmaBurstLength(DMA_BurstLength burstLength) +{ + if ((burstLength == DMA_BURST_LENGTH_1) || (burstLength == DMA_BURST_LENGTH_4) || + (burstLength == DMA_BURST_LENGTH_8) || (burstLength == DMA_BURST_LENGTH_16) || + (burstLength == DMA_BURST_LENGTH_32) || (burstLength == DMA_BURST_LENGTH_64) || + (burstLength == DMA_BURST_LENGTH_128) || (burstLength == DMA_BURST_LENGTH_256)) { + return true; + } + return false; +} + +/** + * @brief Check DMA type of address change. + * @param byteOrder DMA source/destination address change type. + * @retval bool + */ +static inline bool IsDmaAddrMode(DMA_AddrIncMode addrMode) +{ + return (addrMode == DMA_ADDR_UNALTERED) || (addrMode == DMA_ADDR_INCREASE); +} + +/** + * @brief Check DMA type of direction. + * @param direction DMA transmfer direction. + * @retval bool + */ +static inline bool IsDmaDirection(DMA_TransDirection direction) +{ + if ((direction == DMA_MEMORY_TO_MEMORY_BY_DMAC) || (direction == DMA_MEMORY_TO_PERIPH_BY_DMAC) || + (direction == DMA_PERIPH_TO_MEMORY_BY_DMAC) || (direction == DMA_PERIPH_TO_PERIPH_BY_DMAC) || + (direction == DMA_PERIPH_TO_PERIPH_BY_DES) || (direction == DMA_MEMORY_TO_PERIPH_BY_DES) || + (direction == DMA_PERIPH_TO_MEMORY_BY_SRC) || (direction == DMA_PERIPH_TO_PERIPH_BY_SRC)) { + return true; + } + return false; +} + +/** + * @brief Check DMA channel priority. + * @param priority DMA channel priority. + * @retval bool + */ +static inline bool IsDmaPriority(DMA_ChannelPriority priority) +{ + if ((priority == DMA_PRIORITY_LOW) || (priority == DMA_PRIORITY_MEDIUM) || + (priority == DMA_PRIORITY_HIGH) || (priority == DMA_PRIORITY_HIGHEST)) { + return true; + } + return false; +} + +/** + * @brief Check DMA num of request peripheral. + * @param reqPeriph peripherals supported by the DMA. + * @retval bool + */ +static inline bool IsDmaReqPeriph(DMA_RequestLineNum reqPeriph) +{ + return (reqPeriph >= DMA_REQUEST_I2C0_RX) && (reqPeriph <= DMA_REQUEST_MEM); +} + +/** + * @brief Check whether the address is valid. + * @param address Address for the DMA to transfer data. + * @retval bool + */ +static inline bool IsDmaValidAddress(unsigned int address) +{ + return (address >= SRAM_START && address <= SRAM_END) || (address >= REGISTER_START && address <= REGISTER_END); +} + +/** + * @brief DMA configurate the direction. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_SetDirection(DMA_ChannelRegStruct * const dmaChannelx, DMA_TransDirection direction) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(IsDmaDirection(direction)); + dmaChannelx->DMA_Cn_CONFIG.BIT.flow_ctrl = direction; +} + +/** + * @brief DMA configurate the address of source. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_SetSrcAddr(DMA_ChannelRegStruct * const dmaChannelx, unsigned int srcAddr) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(srcAddr > 0); + dmaChannelx->DMA_Cn_SRC_ADDR.BIT.src_addr = srcAddr; +} + +/** + * @brief DMA configurate the address of destnation. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_SetDestAddr(DMA_ChannelRegStruct * const dmaChannelx, unsigned int destAddr) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(destAddr > 0); + dmaChannelx->DMA_Cn_DEST_ADDR.BIT.dest_addr = destAddr; +} + +/** + * @brief DMA configurate the address mode of source. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_SetSrcAddrMode(DMA_ChannelRegStruct * const dmaChannelx, DMA_AddrIncMode srcAddrInc) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(IsDmaAddrMode(srcAddrInc)); + dmaChannelx->DMA_Cn_CONTROL.BIT.src_incr = srcAddrInc; +} + +/** + * @brief DMA configurate the address mode of destnation. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_SetDestAddrMode(DMA_ChannelRegStruct * const dmaChannelx, DMA_AddrIncMode destAddrInc) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(IsDmaAddrMode(destAddrInc)); + dmaChannelx->DMA_Cn_CONTROL.BIT.dest_incr = destAddrInc; +} + +/** + * @brief DMA configurate the bit width of source. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_SetSrcWidth(DMA_ChannelRegStruct * const dmaChannelx, DMA_TransmisWidth srcWidth) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(IsDmaWidth(srcWidth)); + dmaChannelx->DMA_Cn_CONTROL.BIT.swidth = srcWidth; +} + +/** + * @brief DMA configurate the bit width of destnation. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_SetDestWidth(DMA_ChannelRegStruct * const dmaChannelx, DMA_TransmisWidth destWidth) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(IsDmaWidth(destWidth)); + dmaChannelx->DMA_Cn_CONTROL.BIT.dwidth = destWidth; +} + +/** + * @brief DMA configurate the burst size of source. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_SetSrcBurst(DMA_ChannelRegStruct * const dmaChannelx, DMA_BurstLength srcBurst) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(IsDmaBurstLength(srcBurst)); + dmaChannelx->DMA_Cn_CONTROL.BIT.sbsize = srcBurst; +} + +/** + * @brief DMA configurate the burst size of source. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_SetDestBurst(DMA_ChannelRegStruct * const dmaChannelx, DMA_BurstLength destBurst) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(IsDmaBurstLength(destBurst)); + dmaChannelx->DMA_Cn_CONTROL.BIT.dbsize = destBurst; +} + +/** + * @brief DMA configurate the transfer size. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_SetTransferSize(DMA_ChannelRegStruct * const dmaChannelx, unsigned int dataLength) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(dataLength <= 0xFFF); + dmaChannelx->DMA_Cn_CONTROL.BIT.trans_size = dataLength; +} + +/** + * @brief Enable channel completion interrupt. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_EnableIT(DMA_ChannelRegStruct * const dmaChannelx) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + dmaChannelx->DMA_Cn_CONTROL.BIT.int_tc_enable = BASE_CFG_ENABLE; + dmaChannelx->DMA_Cn_CONFIG.BIT.tc_int_msk = BASE_CFG_ENABLE; +} + +/** + * @brief Disable channel completion interrupt. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_DisableIT(DMA_ChannelRegStruct * const dmaChannelx) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + dmaChannelx->DMA_Cn_CONFIG.BIT.tc_int_msk = BASE_CFG_DISABLE; +} + +/** + * @brief Enables the channel to start transmission. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_EnableChannel(DMA_ChannelRegStruct * const dmaChannelx) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + dmaChannelx->DMA_Cn_CONFIG.BIT.ch_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable the channel to start transmission. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_DisableChannel(DMA_ChannelRegStruct * const dmaChannelx) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + dmaChannelx->DMA_Cn_CONFIG.BIT.ch_en = BASE_CFG_DISABLE; +} +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_DMA_IP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/dma/src/dma.c b/vendor/xinlingyu_92_3061M/Project/drivers/dma/src/dma.c new file mode 100644 index 0000000000000000000000000000000000000000..860a9ad72cf80c38b91c26fbae21a5145b355b70 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/dma/src/dma.c @@ -0,0 +1,722 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dma.c + * @author MCU Driver Team + * @brief DMA module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the DMA. + * + Initialization and de-initialization functions. + * + Start DMA transfer with interrupt mode. + * + Start DMA transfer without interrupt mode. + * + Stop DMA transfer and query the state of DMA. + * + Interrupt callback function and user registration function. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "dma.h" + +static DMA_LinkList g_listTable[LISTNODE_MAX] = {0}; +static unsigned int g_listIndex = 0; + +static BASE_StatusType DMA_SetChannelAndDirection(DMA_Handle *dmaHandle, unsigned int srcAddr, unsigned int destAddr, + unsigned int dataLength, unsigned int channel); +static BASE_StatusType DMA_SetDirection(DMA_Handle *dmaHandle, unsigned int channel); +static BASE_StatusType DMA_SetChannel(DMA_Handle *dmaHandle, unsigned int srcAddr, unsigned int destAddr, + unsigned int dataLength, unsigned int channel); + +static void DMA_SplitToBlock(DMA_LinkList *node, DMA_SplitParam *split); +/** + * @brief Initialize the DMA hardware controller configuration. + * @param dmaHandle DMA handle. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +BASE_StatusType HAL_DMA_Init(DMA_Handle *dmaHandle) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + dmaHandle->baseAddress->DMA_CONFIG.BIT.dma_enable = BASE_CFG_ENABLE; /* Enable the DMA controller */ + dmaHandle->baseAddress->DMA_INT_ERR_CLR.reg |= 0x3F; + dmaHandle->baseAddress->DMA_INT_TC_CLR.reg |= 0x3F; + dmaHandle->baseAddress->DMA_SYNC.reg = 0x00; + dmaHandle->baseAddress->DMA_C0_CONFIG.reg = 0x00; + dmaHandle->baseAddress->DMA_C1_CONFIG.reg = 0x00; + dmaHandle->baseAddress->DMA_C2_CONFIG.reg = 0x00; + dmaHandle->baseAddress->DMA_C3_CONFIG.reg = 0x00; + dmaHandle->baseAddress->DMA_C4_CONFIG.reg = 0x00; + dmaHandle->baseAddress->DMA_C5_CONFIG.reg = 0x00; + + dmaHandle->DMA_Channels[0].channelAddr = DMA_CHANNEL0; /* Setting the base Address of channel 0 registers */ + dmaHandle->DMA_Channels[1].channelAddr = DMA_CHANNEL1; /* Setting the base Address of channel 1 registers */ + dmaHandle->DMA_Channels[2].channelAddr = DMA_CHANNEL2; /* Setting the base Address of channel 2 registers */ + dmaHandle->DMA_Channels[3].channelAddr = DMA_CHANNEL3; /* Setting the base Address of channel 3 registers */ + dmaHandle->DMA_Channels[4].channelAddr = DMA_CHANNEL4; /* Setting the base Address of channel 4 registers */ + dmaHandle->DMA_Channels[5].channelAddr = DMA_CHANNEL5; /* Setting the base Address of channel 5 registers */ + return BASE_STATUS_OK; +} + +/** + * @brief DeInitialize the DMA, close all channels. + * @param dmaHandle DMA handle. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +BASE_StatusType HAL_DMA_Deinit(DMA_Handle *dmaHandle) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + dmaHandle->baseAddress->DMA_INT_ERR_CLR.reg |= 0x3F; + dmaHandle->baseAddress->DMA_INT_TC_CLR.reg |= 0x3F; + dmaHandle->baseAddress->DMA_C0_CONFIG.reg = 0x00; + dmaHandle->baseAddress->DMA_C1_CONFIG.reg = 0x00; + dmaHandle->baseAddress->DMA_C2_CONFIG.reg = 0x00; + dmaHandle->baseAddress->DMA_C3_CONFIG.reg = 0x00; + dmaHandle->baseAddress->DMA_C4_CONFIG.reg = 0x00; + dmaHandle->baseAddress->DMA_C5_CONFIG.reg = 0x00; + dmaHandle->baseAddress->DMA_CONFIG.BIT.dma_enable = BASE_CFG_DISABLE; + /* Clean callback */ + for (unsigned int i = 0; i < CHANNEL_MAX_NUM; i++) { + dmaHandle->userCallBack.DMA_CallbackFuns[i].ChannelFinishCallBack = NULL; + dmaHandle->userCallBack.DMA_CallbackFuns[i].ChannelErrorCallBack = NULL; + } + return BASE_STATUS_OK; +} + +/** + * @brief Return the specified DMA channel state. + * @param dmaHandle DMA handle. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval Channel state: BASE_STATUS_BUSY, BASE_STATUS_OK. + */ +BASE_StatusType HAL_DMA_GetChannelState(DMA_Handle *dmaHandle, unsigned int channel) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + DMA_PARAM_CHECK_WITH_RET(IsDmaChannelNum(channel) == true, BASE_STATUS_ERROR); + unsigned int chns = dmaHandle->baseAddress->DMA_ENABLED_CHNS.reg; /* Obtains the channel enabling status */ + unsigned int channelStatus = chns & (1 << channel); + if (channelStatus == (uintptr_t)(1 << channel)) { + return BASE_STATUS_BUSY; + } + return BASE_STATUS_OK; +} + +/** + * @brief Modifying DMA channel parameters. + * @param dmaHandle DMA handle. + * @param channelParam DMA specific channel handle. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +BASE_StatusType HAL_DMA_InitChannel(DMA_Handle *dmaHandle, DMA_ChannelParam *channelParam, unsigned int channel) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(channelParam != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + DMA_PARAM_CHECK_WITH_RET(IsDmaDirection(channelParam->direction) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaReqPeriph(channelParam->srcPeriph) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaReqPeriph(channelParam->destPeriph) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaWidth(channelParam->srcWidth) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaWidth(channelParam->destWidth) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaBurstLength(channelParam->srcBurst) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaBurstLength(channelParam->destBurst) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaAddrMode(channelParam->srcAddrInc) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaAddrMode(channelParam->destAddrInc) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaChannelNum(channel) == true, BASE_STATUS_ERROR); + dmaHandle->DMA_Channels[channel].direction = channelParam->direction; + dmaHandle->DMA_Channels[channel].srcPeriph = channelParam->srcPeriph; + dmaHandle->DMA_Channels[channel].destPeriph = channelParam->destPeriph; + dmaHandle->DMA_Channels[channel].srcWidth = channelParam->srcWidth; + dmaHandle->DMA_Channels[channel].destWidth = channelParam->destWidth; + dmaHandle->DMA_Channels[channel].srcBurst = channelParam->srcBurst; + dmaHandle->DMA_Channels[channel].destBurst = channelParam->destBurst; + dmaHandle->DMA_Channels[channel].srcAddrInc = channelParam->srcAddrInc; + dmaHandle->DMA_Channels[channel].destAddrInc = channelParam->destAddrInc; + dmaHandle->DMA_Channels[channel].pHandle = channelParam->pHandle; + return BASE_STATUS_OK; +} + +/** + * @brief Configuring the DMA source device. + * @param dmaHandle DMA handle. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval None. + */ +static void DMA_SetSrcPeriph(DMA_Handle *dmaHandle, unsigned int channel) +{ + unsigned int periphNum = dmaHandle->DMA_Channels[channel].srcPeriph; + if (periphNum >= DMA_REQUEST_MEM) { + return; + } + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONFIG.BIT.src_periph = periphNum; +} + +/** + * @brief Configuring the DMA destination device. + * @param dmaHandle DMA handle. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval None. + */ +static void DMA_SetDestPeriph(DMA_Handle *dmaHandle, unsigned int channel) +{ + unsigned int periphNum = dmaHandle->DMA_Channels[channel].destPeriph; + if (periphNum >= DMA_REQUEST_MEM) { + return; + } + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONFIG.BIT.dest_periph = periphNum; +} + +/** + * @brief Configuring the transmission direction of the DMA channel. + * @param dmaHandle DMA handle. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +static BASE_StatusType DMA_SetDirection(DMA_Handle *dmaHandle, unsigned int channel) +{ + unsigned int direction = dmaHandle->DMA_Channels[channel].direction; + DMA_PARAM_CHECK_WITH_RET(IsDmaDirection(direction) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaReqPeriph(dmaHandle->DMA_Channels[channel].srcPeriph) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaReqPeriph(dmaHandle->DMA_Channels[channel].destPeriph) == true, BASE_STATUS_ERROR); + /* Setting Channel Configuration Parameters */ + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONFIG.BIT.flow_ctrl = direction; + switch (direction) { + case DMA_MEMORY_TO_PERIPH_BY_DMAC: + DMA_SetDestPeriph(dmaHandle, channel); + break; + /* The transfer type is peripheral to memory, flow control is controlled by DMA */ + case DMA_PERIPH_TO_MEMORY_BY_DMAC: + DMA_SetSrcPeriph(dmaHandle, channel); + break; + case DMA_PERIPH_TO_PERIPH_BY_DMAC: + DMA_SetSrcPeriph(dmaHandle, channel); + DMA_SetDestPeriph(dmaHandle, channel); + break; + /* The transfer type is peripheral to peripheral, flow control is controlled by destination periphera */ + case DMA_PERIPH_TO_PERIPH_BY_DES: + DMA_SetSrcPeriph(dmaHandle, channel); + DMA_SetDestPeriph(dmaHandle, channel); + break; + case DMA_MEMORY_TO_PERIPH_BY_DES: + DMA_SetDestPeriph(dmaHandle, channel); + break; + /* The transfer type is peripheral to memory, flow control is controlled by source periphera */ + case DMA_PERIPH_TO_MEMORY_BY_SRC: + DMA_SetSrcPeriph(dmaHandle, channel); + break; + case DMA_PERIPH_TO_PERIPH_BY_SRC: + DMA_SetSrcPeriph(dmaHandle, channel); + DMA_SetDestPeriph(dmaHandle, channel); + break; + default: + break; + } + return BASE_STATUS_OK; +} + +/** + * @brief Calculate the configured value based on the channel configuration parameters. + * @param dmaHandle DMA handle. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval val Calculation result. + */ +static unsigned int DMA_CalControlval(DMA_Handle *dmaHandle, unsigned int channel) +{ + unsigned int val = 0x80000000; /* 0x80000000 indicates int_tc_enable is set */ + val |= (dmaHandle->DMA_Channels[channel].srcBurst) << 12; /* Shift left by 12 bits for source burst */ + val |= (dmaHandle->DMA_Channels[channel].destBurst) << 15; /* Shift left by 15 bits for destination burst */ + val |= (dmaHandle->DMA_Channels[channel].srcWidth) << 18; /* Shift left by 18 bits for source width */ + val |= (dmaHandle->DMA_Channels[channel].destWidth) << 21; /* Shift left by 21 bits for destination width */ + val |= (dmaHandle->DMA_Channels[channel].srcAddrInc) << 26; /* Shift left by 26 bits for source address */ + val |= (dmaHandle->DMA_Channels[channel].destAddrInc) << 27; /* Shift left by 27 bits for destination address */ + return val; +} + +/** + * @brief Configuring Segmentation Parameters. + * @param dmaHandle DMA handle. + * @param srcAddr Data source address. + * @param destAddr Data destination address + * @param dataLength Length of data to be transferred. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval None. + */ +static void DMA_ConfigureSplit(DMA_Handle *dmaHandle, unsigned int srcAddr, + unsigned int destAddr, unsigned int dataLength, unsigned int channel) +{ + unsigned int val = DMA_CalControlval(dmaHandle, channel); /* Convert the configuration parameter to the value */ + DMA_SplitParam split; + split.chnParam = val; /* Setting channel parameters by val */ + split.srcAddr = srcAddr; + split.destAddr = destAddr; + split.srcIn = dmaHandle->DMA_Channels[channel].srcAddrInc * (1 << dmaHandle->DMA_Channels[channel].srcWidth); + split.destIn = dmaHandle->DMA_Channels[channel].destAddrInc * (1 << dmaHandle->DMA_Channels[channel].destWidth); + split.totalSize = dataLength; + DMA_LinkList *head = &(g_listTable[g_listIndex]); + g_listIndex++; + head->lliNext = NULL; + val |= TRANS_BLOCK; /* Set the size of the data to be transferred, TRANS_BLOCK is 4092 */ + head->control.reg = val; + DMA_SplitToBlock(head, &split); + /* After DMA_SplitToBlock return, head->control.reg[31] int_tc_enable is set 0 */ + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONTROL.reg = head->control.reg; + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_LLI.reg = (uintptr_t)(void *)head->lliNext; +} + +/** + * @brief Configuring DMA channel and direction. + * @param dmaHandle DMA handle. + * @param srcAddr Data source address. + * @param destAddr Data destination address + * @param dataLength Length of data to be transferred. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +static BASE_StatusType DMA_SetChannelAndDirection(DMA_Handle *dmaHandle, unsigned int srcAddr, unsigned int destAddr, + unsigned int dataLength, unsigned int channel) +{ + DMA_PARAM_CHECK_WITH_RET(IsDmaValidAddress(srcAddr), BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaValidAddress(destAddr), BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaValidAddress(srcAddr + dataLength), BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaValidAddress(destAddr + dataLength), BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaChannelNum(channel) == true, BASE_STATUS_ERROR); + if (HAL_DMA_GetChannelState(dmaHandle, channel) != BASE_STATUS_OK) { + return BASE_STATUS_BUSY; + } + /* Indicates whether to clear the corresponding channel interrupt */ + dmaHandle->baseAddress->DMA_INT_ERR_CLR.reg |= (1 << channel); + dmaHandle->baseAddress->DMA_INT_TC_CLR.reg |= (1 << channel); + if (DMA_SetChannel(dmaHandle, srcAddr, destAddr, dataLength, channel) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + /* Setting channel direction */ + if (DMA_SetDirection(dmaHandle, channel) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief Configuring DMA channel transmission parameters. + * @param dmaHandle DMA handle. + * @param srcAddr Data source address. + * @param destAddr Data destination address + * @param dataLength Length of data to be transferred. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +static BASE_StatusType DMA_SetChannel(DMA_Handle *dmaHandle, unsigned int srcAddr, unsigned int destAddr, + unsigned int dataLength, unsigned int channel) +{ + DMA_PARAM_CHECK_WITH_RET(IsDmaWidth(dmaHandle->DMA_Channels[channel].srcWidth) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaWidth(dmaHandle->DMA_Channels[channel].destWidth) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaBurstLength(dmaHandle->DMA_Channels[channel].srcBurst) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaBurstLength(dmaHandle->DMA_Channels[channel].destBurst) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaAddrMode(dmaHandle->DMA_Channels[channel].srcAddrInc) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaAddrMode(dmaHandle->DMA_Channels[channel].destAddrInc) == true, BASE_STATUS_ERROR); + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_SRC_ADDR.reg = srcAddr; + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_DEST_ADDR.reg = destAddr; + /* If the data size is greater than 4095, data needs to be transferred in blocks */ + if (dataLength > TRANSIZE_MAX) { + if (g_listIndex >= LISTNODE_MAX) { + return BASE_STATUS_ERROR; + } + DMA_ConfigureSplit(dmaHandle, srcAddr, destAddr, dataLength, channel); + } else { + unsigned int val = DMA_CalControlval(dmaHandle, channel); + val |= dataLength; + /* Configure the corresponding channel control parameters based on the value */ + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONTROL.reg = val; /**/ + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_LLI.reg = 0x00; + } + return BASE_STATUS_OK; +} + +/** + * @brief DMA start data transfer without interrupt enable. + * @param dmaHandle DMA handle. + * @param srcAddr Data source address. + * @param destAddr Data destination address + * @param dataLength Length of data to be transferred + * @param channel DMA channel num @ref DMA_ChannelNum. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +BASE_StatusType HAL_DMA_Start(DMA_Handle *dmaHandle, unsigned int srcAddr, + unsigned int destAddr, unsigned int dataLength, unsigned int channel) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + BASE_StatusType status; + /* Setting channel parameter */ + status = DMA_SetChannelAndDirection(dmaHandle, srcAddr, destAddr, dataLength, channel); + if (status != BASE_STATUS_OK) { + return status; + } + /* Mask completion interrupts and error interrupts, enable channels */ + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONFIG.reg &= ~(0x0000C000); + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONFIG.BIT.ch_en = BASE_CFG_ENABLE; +#ifdef BASE_DEFINE_DMA_QUICKSTART + dmaHandle->DMA_Channels[channel].srcAddr = dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_SRC_ADDR.reg; + dmaHandle->DMA_Channels[channel].destAddr = dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_DEST_ADDR.reg; + dmaHandle->DMA_Channels[channel].controlVal = dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONTROL.reg; + dmaHandle->DMA_Channels[channel].configVal = dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONFIG.reg; +#endif + return BASE_STATUS_OK; +} + +/** + * @brief DMA start data transfer with interrupt enable. + * @param dmaHandle DMA handle. + * @param srcAddr Data source address. + * @param destAddr Data destination address + * @param dataLength Length of data to be transferred + * @param channel DMA channel num @ref DMA_ChannelNum. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +BASE_StatusType HAL_DMA_StartIT(DMA_Handle *dmaHandle, unsigned int srcAddr, + unsigned int destAddr, unsigned int dataLength, unsigned int channel) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + BASE_StatusType status; + /* Setting channel parameter */ + status = DMA_SetChannelAndDirection(dmaHandle, srcAddr, destAddr, dataLength, channel); + if (status != BASE_STATUS_OK) { + return status; + } + /* Set tc_int_msk, err_int_msk, ch_en */ + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONFIG.reg |= 0xC001; +#ifdef BASE_DEFINE_DMA_QUICKSTART + dmaHandle->DMA_Channels[channel].srcAddr = dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_SRC_ADDR.reg; + dmaHandle->DMA_Channels[channel].destAddr = dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_DEST_ADDR.reg; + dmaHandle->DMA_Channels[channel].controlVal = dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONTROL.reg; + dmaHandle->DMA_Channels[channel].configVal = dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONFIG.reg; +#endif + return BASE_STATUS_OK; +} + +/** + * @brief DMA specified channel stops transporting. + * @param dmaHandle DMA handle. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +BASE_StatusType HAL_DMA_StopChannel(DMA_Handle *dmaHandle, unsigned int channel) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + DMA_PARAM_CHECK_WITH_RET(IsDmaChannelNum(channel) == true, BASE_STATUS_ERROR); + /* Ignore subsequent DMA requests */ + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONFIG.BIT.ch_halt = BASE_CFG_ENABLE; + unsigned int active; + /* Processes the remaining data in the channel FIFO */ + do { + active = dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONFIG.BIT.ch_active; + } while (active != 0); + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONFIG.BIT.ch_en = BASE_CFG_DISABLE; + return BASE_STATUS_OK; +} + +/** + * @brief DMA specified channel transfer complete interrupt service processing function. + * @param dmaHandle DMA handle. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval None. + */ +static void DMA_ChannelIrqHandlerTc(DMA_Handle *dmaHandle, unsigned int channel) +{ + unsigned int finishStatus = dmaHandle->baseAddress->DMA_INT_TC_STAT.reg; + if ((finishStatus & (1 << channel)) != 0) { + dmaHandle->baseAddress->DMA_INT_TC_CLR.reg |= (1 << channel); /* Clear channel tc interrupt */ + if (dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelFinishCallBack != NULL) { + dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelFinishCallBack( + dmaHandle->DMA_Channels[channel].pHandle); + } + } + return; +} + +/** + * @brief DMA specified channel error interrupt service processing function. + * @param dmaHandle DMA handle. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval None. + */ +static void DMA_ChannelIrqHandlerError(DMA_Handle *dmaHandle, unsigned int channel) +{ + unsigned int errorStatus = dmaHandle->baseAddress->DMA_INT_ERR_STAT.reg; + if ((errorStatus & (1 << channel)) != 0) { + dmaHandle->baseAddress->DMA_INT_ERR_CLR.reg |= (1 << channel); /* Clear channel err interrupt */ + if (dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelErrorCallBack != NULL) { + dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelErrorCallBack( + dmaHandle->DMA_Channels[channel].pHandle); + } + } + return; +} + +/** + * @brief DMA transfer complete interrupt service processing function. + * @param handle DMA handle. + * @retval None. + */ +void HAL_DMA_IrqHandlerTc(void *handle) +{ + DMA_ASSERT_PARAM(handle != NULL); + DMA_Handle *dmaHandle = (DMA_Handle *)handle; + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + unsigned int intStatus = dmaHandle->baseAddress->DMA_INT_STAT.reg; + for (int i = 0; i < CHANNEL_MAX_NUM; i++) { + if (intStatus & (1 << i)) { /* DMA channel status */ + DMA_ChannelIrqHandlerTc(dmaHandle, i); + } + } + return; +} + +/** + * @brief DMA error interrupt service processing function. + * @param handle DMA handle. + * @retval None. + */ +void HAL_DMA_IrqHandlerError(void *handle) +{ + DMA_ASSERT_PARAM(handle != NULL); + DMA_Handle *dmaHandle = (DMA_Handle *)handle; + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + unsigned int intStatus = dmaHandle->baseAddress->DMA_INT_STAT.reg; + for (int i = 0; i < CHANNEL_MAX_NUM; i++) { + if (intStatus & (1 << i)) { /* DMA channel status */ + DMA_ChannelIrqHandlerError(dmaHandle, i); + } + } + return; +} + +/** + * @brief User callback function registration interface. + * @param dmaHandle DMA handle. + * @param typeID Id of callback function type. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @param pCallback pointer of the specified callbcak function. + * @retval None. + */ +void HAL_DMA_RegisterCallback(DMA_Handle *dmaHandle, DMA_CallbackFun_Type typeID, + DMA_ChannelNum channel, DMA_CallbackType pCallback) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + DMA_PARAM_CHECK_NO_RET(IsDmaChannelNum(channel) == true); + switch (typeID) { + case DMA_CHANNEL_FINISH: + dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelFinishCallBack = pCallback; + break; + case DMA_CHANNEL_ERROR: + dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelErrorCallBack = pCallback; + break; + default: + return; + } +} + +/** + * @brief Find the last node in the linked list. + * @param head Pointer to the transfer header of the linked list. + * @retval retNode End node of the linked list. + */ +static DMA_LinkList* DMA_FindListEndNode(DMA_LinkList *head) +{ + DMA_LinkList* retNode = head; + while (retNode->lliNext != NULL) { + retNode = retNode->lliNext; + } + return retNode; +} + +/** + * @brief Add a new node to the end of the linked list. + * @param head Pointer to the transfer header of the linked list. + * @param newNode Node to be added. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +BASE_StatusType HAL_DMA_ListAddNode(DMA_LinkList *head, DMA_LinkList *newNode) +{ + DMA_ASSERT_PARAM(head != NULL); + DMA_ASSERT_PARAM(newNode != NULL); + DMA_LinkList *node = NULL; + node = DMA_FindListEndNode(head); + if (node != NULL) { + node->lliNext = newNode; + node->control.BIT.int_tc_enable = 0x0; /* current node does not trigger the transfer completion interrupt */ + newNode->control.BIT.int_tc_enable = 0x01; /* current node trigger the transfer completion interrupt */ + } + return BASE_STATUS_OK; +} + +/** + * @brief Create a new node and add it to the end of the linked list. + * @param head Linked blocked head node. + * @param split Argument handle that splits into small blocks. + * @param index Sequence number of the new node in the linked list. + * @param controlVal Channel control parameters for the new node. + * @retval None. + */ +static void DMA_CreateNode(DMA_LinkList *head, DMA_SplitParam *split, unsigned int index, unsigned int controlVal) +{ + if (g_listIndex >= LISTNODE_MAX) { + return; + } + DMA_LinkList *newNode = &(g_listTable[g_listIndex]); + g_listIndex++; + newNode->srcAddr = split->srcAddr + (index * TRANS_BLOCK * split->srcIn); + newNode->destAddr = split->destAddr + (index * TRANS_BLOCK * split->destIn); + newNode->lliNext = NULL; + newNode->control.reg = controlVal; /* Channel parameters configured for the node */ + HAL_DMA_ListAddNode(head, newNode); +} + +/** + * @brief The upper limit of a DMA transfer is TRANSIZE_MAX. If the upper limit is greater than this value, + * the DMA needs to be divided into small blocks, and each small block is linked for transmission. + * @param head Linked blocked head node. + * @param split Argument handle that splits into small blocks. + * @retval None. + */ +static void DMA_SplitToBlock(DMA_LinkList *head, DMA_SplitParam *split) +{ + unsigned int totalSize = split->totalSize; + unsigned remainSize = totalSize % TRANS_BLOCK; + unsigned int index, controlVal; + for (index = 1; index < totalSize / TRANS_BLOCK; index++) { /* Block transfer based on the 4092 size */ + controlVal = split->chnParam; + controlVal |= TRANS_BLOCK; + DMA_CreateNode(head, split, index, controlVal); + } + if (remainSize != 0) { /* The remaining data size is less than 4092 */ + controlVal = split->chnParam; + controlVal |= remainSize; + DMA_CreateNode(head, split, index, controlVal); + } +} + +/** + * @brief In DMA chain transmission, initialize each node. + * @param node Node to be initialized. + * @param param Channel transmission parameters. + * @param srcAddr Transport source address of this node. + * @param destAddr Transport destnation address of this node. + * @param tranSize Data transmitted by this node. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +BASE_StatusType HAL_DMA_InitNewNode(DMA_LinkList *node, const DMA_ChannelParam *param, + unsigned int srcAddr, unsigned int destAddr, unsigned int tranSize) +{ + DMA_ASSERT_PARAM(node != NULL); + DMA_ASSERT_PARAM(param != NULL); + DMA_PARAM_CHECK_WITH_RET(IsDmaValidAddress(srcAddr), BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaValidAddress(destAddr), BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(tranSize > 0, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaValidAddress(srcAddr + tranSize), BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaValidAddress(destAddr + tranSize), BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaBurstLength(param->srcBurst) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaBurstLength(param->destBurst) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaWidth(param->srcWidth) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaWidth(param->destWidth) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaAddrMode(param->srcAddrInc) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaAddrMode(param->destAddrInc) == true, BASE_STATUS_ERROR); + node->srcAddr = srcAddr; + node->destAddr = destAddr; + node->lliNext = NULL; + unsigned int val = 0x80000000; /* 0x80000000 indicates int_tc_enable */ + val |= (param->srcBurst) << 12; /* Shift left by 12 bits for source burst */ + val |= (param->destBurst) << 15; /* Shift left by 15 bits for destination burst */ + val |= (param->srcWidth) << 18; /* Shift left by 18 bits for source width */ + val |= (param->destWidth) << 21; /* Shift left by 21 bits for destination width */ + val |= (param->srcAddrInc) << 26; /* Shift left by 26 bits for source address */ + val |= (param->destAddrInc) << 27; /* Shift left by 27 bits for destination address */ + if (tranSize > TRANSIZE_MAX) { + DMA_SplitParam split; + split.chnParam = val; + split.srcAddr = srcAddr; + split.destAddr = destAddr; + /* Source and destnation address single increment size */ + split.srcIn = param->srcAddrInc * (1 << param->srcWidth); + split.destIn = param->destAddrInc * (1 << param->destWidth); + split.totalSize = tranSize; + val |= TRANS_BLOCK; + node->control.reg = val; + DMA_SplitToBlock(node, &split); /* Shift left by 27 bits for destination address */ + } else { + val |= tranSize; + node->control.reg = val; + } + return BASE_STATUS_OK; +} + +/** + * @brief Start DMA chain transmission. Chain transfer, which is used to transfer data to discontinuous + * address spaces in memory. After the transmission task of the last node is complete, an interrupt is reported. + * @param dmaHandle DMA handle. + * @param head Pointer to the transfer header of the linked list. + * @param channel DMA channel num @ref DMA_ChannelNum. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +BASE_StatusType HAL_DMA_StartListTransfer(DMA_Handle *dmaHandle, DMA_LinkList *head, unsigned int channel) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(head != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + DMA_PARAM_CHECK_WITH_RET(IsDmaChannelNum(channel) == true, BASE_STATUS_ERROR); + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_SRC_ADDR.reg = head->srcAddr; + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_DEST_ADDR.reg = head->destAddr; + if (head->lliNext != NULL) { + /* Configure the next node address of the linked list */ + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_LLI.reg = (uintptr_t)(void *)head->lliNext; + } else { + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_LLI.reg = 0x00; + } + if (head->lliNext == head) { + head->control.BIT.int_tc_enable = 0; /* current node does not trigger the transfer completion interrupt */ + } + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONTROL.reg = head->control.reg; + DMA_SetDirection(dmaHandle, channel); + /* Set tc_int_msk, ch_en */ + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONFIG.BIT.tc_int_msk = BASE_CFG_ENABLE; + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONFIG.BIT.ch_en = BASE_CFG_ENABLE; + return BASE_STATUS_OK; +} + +#ifdef BASE_DEFINE_DMA_QUICKSTART +/** + * @brief DMA start data transfer without parameter verification Use the parameters of the last DMA configuration. + * @param dmaHandle DMA handle. + * @param channel DMA channel num @ref DMA_ChannelNum. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +void HAL_DMA_QuickStart(DMA_Handle *dmaHandle, unsigned int channel) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + DMA_PARAM_CHECK_NO_RET(IsDmaChannelNum(channel)); + /* Readback value configuration channel parameters */ + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_SRC_ADDR.reg = dmaHandle->DMA_Channels[channel].srcAddr; + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_DEST_ADDR.reg = dmaHandle->DMA_Channels[channel].destAddr; + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONTROL.reg = dmaHandle->DMA_Channels[channel].controlVal; + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONFIG.reg = dmaHandle->DMA_Channels[channel].configVal; +} +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/dma/src/dma_ex.c b/vendor/xinlingyu_92_3061M/Project/drivers/dma/src/dma_ex.c new file mode 100644 index 0000000000000000000000000000000000000000..d70c792cc971935343d6f4907494de15fcc4338e --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/dma/src/dma_ex.c @@ -0,0 +1,42 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dma_ex.c + * @author MCU Driver Team + * @brief DMA module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the DMA. + * + DMA Set Functions. + */ + +/* Includes ------------------------------------------------------------------*/ + +#include "dma_ex.h" +/** + * @brief Configuring the Transmission Channel Priority on the DMA. + * @param dmaHandle DMA handle. + * @param channel DMA channel num @ref DMA_ChannelNum. + * @param priority DMA channel num @ref DMA_ChannelPriority. + * @retval None. + */ +void HAL_DMA_SetChannelPriorityEx(DMA_Handle *dmaHandle, unsigned int channel, DMA_ChannelPriority priority) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_PARAM_CHECK_NO_RET(IsDmaChannelNum(channel)); + DMA_PARAM_CHECK_NO_RET(IsDmaPriority(priority)); + dmaHandle->DMA_Channels[channel].channelAddr->DMA_Cn_CONFIG.BIT.ch_priority = priority; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/flash/common/inc/flash.h b/vendor/xinlingyu_92_3061M/Project/drivers/flash/common/inc/flash.h new file mode 100644 index 0000000000000000000000000000000000000000..ede119d3018fc371357ebda9ce5c883ee8d41a8b --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/flash/common/inc/flash.h @@ -0,0 +1,124 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file flash.h + * @author MCU Driver Team + * @brief FLASH module driver. + * @details This file provides firmware functions to manage the following functionalities of the FLASH. + * + Basic parameter configuration macro. + * + FLASH parameter handle definition. + * + Initialization and de-initialization functions. + * + Definition of flash read/write erase functions. + */ +#ifndef McuMagicTag_FLASH_H +#define McuMagicTag_FLASH_H + +/* Includes ---------------------------------------------------------------------*/ +#include "flash_ip.h" + +/** + * @defgroup FLASH FLASH + * @brief FLASH module. + * @{ + */ + +/** + * @defgroup FLASH_Common FLASH Common + * @brief FLASH common external module. + * @{ + */ + +/* Macro definitions -----------------------------------------------------------*/ + +/** + * @defgroup FLASH_Handle_Definition FLASH Handle Definition + * @{ + */ + +/** + * @brief Module Status Enumeration Definition + */ +typedef enum { + FLASH_STATE_RESET = 0x00000000U, + FLASH_STATE_READY = 0x00000001U, + FLASH_STATE_PGM = 0x00000002U, + FLASH_STATE_ERASE = 0x00000003U, + FLASH_STATE_ERROR = 0x00000004U +} FLASH_StateType; + +/** + * @brief Module handle structure definition + */ +typedef struct _FLASH_Handle { + EFC_RegStruct *baseAddress; /**< Register base address. */ + FLASH_PE_OpMode peMode; /**< PE operation type. For details, see FLASH_PE_OpMode. */ + volatile unsigned int destAddr; /**< Destination address for storing interrupt operations. */ + volatile unsigned int srcAddr; /**< Used to store the source address in interrupt mode. */ + volatile unsigned int writeLen; /**< Indicates the length of the data to be written in interrupt mode. */ + volatile unsigned int eraseNum; /**< Used to store the number of erase blocks in interrupt mode. */ + FLASH_StateType state; /**< Running status of the flash module. For details, see FLASH_StateType. */ + FLASH_UserCallBcak userCallBack; /**< User-defined callback function. */ + FLASH_ExtendHandle handleEx; /**< Extend handle, configuring some special parameters. */ +} FLASH_Handle; + +/** + * @brief Callback Function Type Definition. + */ +typedef void (*FLASH_CallbackFunType)(void *handle, FLASH_CallBackEvent event, unsigned int opAddr); +/** + * @} + */ + +/** + * @defgroup FLASH_API_Declaration FLASH HAL API + * @{ + */ +BASE_StatusType HAL_FLASH_Init(FLASH_Handle *handle); +BASE_StatusType HAL_FLASH_DeInit(FLASH_Handle *handle); +BASE_StatusType HAL_FLASH_RegisterCallback(FLASH_Handle *handle, FLASH_CallbackFunType pcallback); +BASE_StatusType HAL_FLASH_WriteBlocking(FLASH_Handle *handle, unsigned int srcAddr, + unsigned int destAddr, unsigned int srcLen); +BASE_StatusType HAL_FLASH_EraseBlocking(FLASH_Handle *handle, + FLASH_EraseMode eraseMode, + FLASH_SectorAddr startAddr, + unsigned int eraseNum); +BASE_StatusType HAL_FLASH_WriteIT(FLASH_Handle *handle, unsigned int srcAddr, + unsigned int destAddr, unsigned int srcLen); +BASE_StatusType HAL_FLASH_EraseIT(FLASH_Handle *handle, + FLASH_EraseMode eraseMode, + FLASH_SectorAddr startAddr, + unsigned int eraseNum); +BASE_StatusType HAL_FLASH_Read(FLASH_Handle *handle, + unsigned int srcAddr, + unsigned int readLen, + unsigned char *dataBuff, + unsigned int buffLen); +void HAL_FLASH_IrqHandler(void *handle); +void HAL_FLASH_IrqHandlerError(void *handle); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* #ifndef McuMagicTag_FLASH_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/flash/inc/flash_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/flash/inc/flash_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..1492bacf6075e829910ff5838cad824518812d4a --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/flash/inc/flash_ip.h @@ -0,0 +1,1156 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file flash_ip.h + * @author MCU Driver Team + * @brief FLASH module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the FLASH. + * + Register definition structure + * + Basic parameter configuration macro + */ + +/* Define to prevent recursive inclusion ----------------------------------------*/ +#ifndef McuMagicTag_FLASH_IP_H +#define McuMagicTag_FLASH_IP_H + +/* Includes ---------------------------------------------------------------------*/ +#include "baseinc.h" + +/* Macro definitions -----------------------------------------------------------*/ +#ifdef FLASH_PARAM_CHECK +#define FLASH_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define FLASH_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define FLASH_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define FLASH_ASSERT_PARAM(para) ((void)0U) +#define FLASH_PARAM_CHECK_NO_RET(para) ((void)0U) +#define FLASH_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +/** + * @addtogroup FLASH + * @{ + */ + +/** + * @defgroup FLASH_IP FLASH_IP + * @brief FLASH_IP: flash_v1 + * @{ + */ + +#define FLASH_BASE 0x0U /* Flash PE operation base address. */ +#define FLASH_READ_BASE 0x3000000U /* Base address for the flash read operation. */ +#define FLASH_ONE_PAGE_SIZE 0x400U /* Size of a page, unit: bytes. 1K. */ +#define FLASH_ONE_PAGE_WORD_SIZE 0x100U /* Size of a page, unit: word. 1K. */ + +#define FLASH_KEY_REGISTER_UNLOCK_VALUE 0xFEDCBA98 +#define FLASH_KEY_REGISTER_LOCK_VALUE 0x0 + +#define FLASH_MAX_PGM_BYTE_SIZE 0x100 +#define FLASH_MAX_PGM_WORD_SIZE 0x40 +#define FLASH_MIN_PGM_BYTES_SIZE 0x10 +#define FLASH_MIN_PGM_WORDS_SIZE 4 +#define FLASH_PGM_WORDS_LEGAL_DIVISOR 4 +#define FLASH_ONE_WORD_BYTES_SIZE 4 + +#define FLASH_PGM_WDATA_BYTE_SIZE 8 +#define FLASH_INFORMATUON_CAPACITY_POS 16 +#define FLASH_INFORMATUON_CAPACITY_MASK (0xFFFF << FLASH_INFORMATUON_CAPACITY_POS) + +#define FLASH_PGM_WBUF_CNT_POS 8 +#define FLASH_PGM_WBUF_CNT_MASK (0xFF << FLASH_PGM_WBUF_CNT_POS) + +#define FLASH_MAX_CMD_PROGRAM_SIZE 0x10 /* The value is cmd program size, unit: 32bits. */ + +#define FLASH_SRAM_START_ADDRESS 0x04000000 +#define FLASH_SRAM_END_ADDRESS 0x04007FFF +#define FLASH_MAIN_RNG_START_ADDRESS 0x03000000 + +/* Only CHIP_3061MNPICA, CHIP_3061MNPIKA is supported 128K. */ +#if defined (CHIP_3061MNPICA) || defined (CHIP_3061MNPIKA) +#define FLASH_MAIN_RNG_END_ADDRESS 0x0301FFFF +#define FLASH_MAX_SIZE 0x20000U /* Flash space size 128k bytes. */ +#define FLASH_MAX_PAGE_NUM 128 +#else +#define FLASH_MAIN_RNG_END_ADDRESS 0x0300FFFF /* The chip only is supported 64K. */ +#define FLASH_MAX_SIZE 0x10000U /* Flash space size 64k bytes. */ +#define FLASH_MAX_PAGE_NUM 64 /* The chip only is supported 64K. */ +#endif + +/** + * @defgroup FLASH_Param_Def FLASH Parameters Definition + * @brief Definition of FLASH configuration parameters. + * @{ + */ +/* Typedef definitions --------------------------------------------------------*/ +/** + * @brief PE Operation Mode Enumeration Definition. + */ +typedef enum { + FLASH_PE_OP_BLOCK = 0x00000000U, + FLASH_PE_OP_IT = 0x00000001U +} FLASH_PE_OpMode; + +/** + * @brief Erase operation type enumeration definition. + */ +typedef enum { + FLASH_ERASE_MODE_PAGE = 0x00000004U, + FLASH_ERASE_MODE_CHIP = 0x00000006U +} FLASH_EraseMode; + +/** + * @brief Flash page address enumeration. + */ +typedef enum { + FLASH_PAGE_0 = FLASH_BASE, + FLASH_PAGE_1 = FLASH_BASE + FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_2 = FLASH_BASE + 2 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_3 = FLASH_BASE + 3 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_4 = FLASH_BASE + 4 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_5 = FLASH_BASE + 5 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_6 = FLASH_BASE + 6 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_7 = FLASH_BASE + 7 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_8 = FLASH_BASE + 8 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_9 = FLASH_BASE + 9 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_10 = FLASH_BASE + 10 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_11 = FLASH_BASE + 11 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_12 = FLASH_BASE + 12 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_13 = FLASH_BASE + 13 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_14 = FLASH_BASE + 14 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_15 = FLASH_BASE + 15 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_16 = FLASH_BASE + 16 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_17 = FLASH_BASE + 17 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_18 = FLASH_BASE + 18 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_19 = FLASH_BASE + 19 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_20 = FLASH_BASE + 20 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_21 = FLASH_BASE + 21 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_22 = FLASH_BASE + 22 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_23 = FLASH_BASE + 23 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_24 = FLASH_BASE + 24 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_25 = FLASH_BASE + 25 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_26 = FLASH_BASE + 26 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_27 = FLASH_BASE + 27 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_28 = FLASH_BASE + 28 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_29 = FLASH_BASE + 29 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_30 = FLASH_BASE + 30 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_31 = FLASH_BASE + 31 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_32 = FLASH_BASE + 32 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_33 = FLASH_BASE + 33 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_34 = FLASH_BASE + 34 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_35 = FLASH_BASE + 35 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_36 = FLASH_BASE + 36 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_37 = FLASH_BASE + 37 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_38 = FLASH_BASE + 38 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_39 = FLASH_BASE + 39 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_40 = FLASH_BASE + 40 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_41 = FLASH_BASE + 41 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_42 = FLASH_BASE + 42 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_43 = FLASH_BASE + 43 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_44 = FLASH_BASE + 44 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_45 = FLASH_BASE + 45 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_46 = FLASH_BASE + 46 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_47 = FLASH_BASE + 47 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_48 = FLASH_BASE + 48 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_49 = FLASH_BASE + 49 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_50 = FLASH_BASE + 50 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_51 = FLASH_BASE + 51 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_52 = FLASH_BASE + 52 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_53 = FLASH_BASE + 53 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_54 = FLASH_BASE + 54 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_55 = FLASH_BASE + 55 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_56 = FLASH_BASE + 56 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_57 = FLASH_BASE + 57 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_58 = FLASH_BASE + 58 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_59 = FLASH_BASE + 59 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_60 = FLASH_BASE + 60 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_61 = FLASH_BASE + 61 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_62 = FLASH_BASE + 62 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_63 = FLASH_BASE + 63 * FLASH_ONE_PAGE_SIZE, + /* Only CHIP_3061MNPICA, CHIP_3061MNPIKA is supported 128K. */ +#if defined (CHIP_3061MNPICA) || defined (CHIP_3061MNPIKA) + FLASH_PAGE_64 = FLASH_BASE + 64 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_65 = FLASH_BASE + 65 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_66 = FLASH_BASE + 66 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_67 = FLASH_BASE + 67 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_68 = FLASH_BASE + 68 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_69 = FLASH_BASE + 69 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_70 = FLASH_BASE + 70 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_71 = FLASH_BASE + 71 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_72 = FLASH_BASE + 72 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_73 = FLASH_BASE + 73 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_74 = FLASH_BASE + 74 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_75 = FLASH_BASE + 75 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_76 = FLASH_BASE + 76 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_77 = FLASH_BASE + 77 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_78 = FLASH_BASE + 78 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_79 = FLASH_BASE + 79 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_80 = FLASH_BASE + 80 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_81 = FLASH_BASE + 81 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_82 = FLASH_BASE + 82 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_83 = FLASH_BASE + 83 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_84 = FLASH_BASE + 84 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_85 = FLASH_BASE + 85 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_86 = FLASH_BASE + 86 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_87 = FLASH_BASE + 87 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_88 = FLASH_BASE + 88 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_89 = FLASH_BASE + 89 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_90 = FLASH_BASE + 90 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_91 = FLASH_BASE + 91 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_92 = FLASH_BASE + 92 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_93 = FLASH_BASE + 93 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_94 = FLASH_BASE + 94 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_95 = FLASH_BASE + 95 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_96 = FLASH_BASE + 96 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_97 = FLASH_BASE + 97 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_98 = FLASH_BASE + 98 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_99 = FLASH_BASE + 99 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_100 = FLASH_BASE + 100 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_101 = FLASH_BASE + 101 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_102 = FLASH_BASE + 102 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_103 = FLASH_BASE + 103 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_104 = FLASH_BASE + 104 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_105 = FLASH_BASE + 105 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_106 = FLASH_BASE + 106 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_107 = FLASH_BASE + 107 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_108 = FLASH_BASE + 108 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_109 = FLASH_BASE + 109 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_110 = FLASH_BASE + 110 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_111 = FLASH_BASE + 111 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_112 = FLASH_BASE + 112 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_113 = FLASH_BASE + 113 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_114 = FLASH_BASE + 114 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_115 = FLASH_BASE + 115 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_116 = FLASH_BASE + 116 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_117 = FLASH_BASE + 117 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_118 = FLASH_BASE + 118 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_119 = FLASH_BASE + 119 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_120 = FLASH_BASE + 120 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_121 = FLASH_BASE + 121 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_122 = FLASH_BASE + 122 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_123 = FLASH_BASE + 123 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_124 = FLASH_BASE + 124 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_125 = FLASH_BASE + 125 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_126 = FLASH_BASE + 126 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_127 = FLASH_BASE + 127 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_MAX = FLASH_PAGE_127 +#else + FLASH_PAGE_MAX = FLASH_PAGE_63 +#endif +} FLASH_SectorAddr; + +/** + * @brief Flash operation word enumeration definition. + */ +typedef enum { + FLASH_OPERATION_READ = 0x00000001U, + FLASH_OPERATION_PROGRAM = 0x00000002U, + FLASH_OPERATION_ERASE = 0x00000004U, + FLASH_OPERATION_MASS_ERASE = 0x00000006U +} FLASH_OperationType; + +/** + * @brief Flash operation cmd code enumeration definition. + */ +typedef enum { + FLASH_CMD_READ = 0x00000001U, + FLASH_CMD_MAIN_PROGEAM = 0x00000002U, + FLASH_CMD_INFO_PROGEAM = 0x00000003U, + FLASH_CMD_MAIN_ERASE = 0x00000004U, + FLASH_CMD_INFO_ERASE = 0x00000005U, + FLASH_CMD_MASS_ERASE = 0x00000006U +} FLASH_CmdCodeType; + +/** + * @brief Callback Triggering Event Enumeration Definition + */ +typedef enum { + FLASH_WRITE_EVENT_SUCCESS, + FLASH_WRITE_EVENT_DONE, + FLASH_WRITE_EVENT_FAIL, + FLASH_ERASE_EVENT_SUCCESS, + FLASH_ERASE_EVENT_DONE, + FLASH_ERASE_EVENT_FAIL, +} FLASH_CallBackEvent; + +/** + * @brief FLASH extend handle, configuring some special parameters. + */ +typedef struct { + unsigned int onceOperateLen; /* Length of the flash memory to be operaten, write unit: byte, erase unit: page. */ +} FLASH_ExtendHandle; + +/** + * @brief User-defined callback function. + */ +typedef struct { + /** Event callback function of the flash module */ + void (*FlashCallBack)(void *handle, FLASH_CallBackEvent event, unsigned int opAddr); +} FLASH_UserCallBcak; +/** + * @} + */ + +/** + * @defgroup FLASH_Reg_Def FLASH Register Definition + * @brief register mapping structure + * @{ + */ + +/** + * @brief EFLASH command registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cmd_start : 1; /**< Write 0:no effect, 1:start cmd operation; + Read 0:cmd operation is complete, 1:cmd operation isn't complete. */ + unsigned int reserved0 : 5; + unsigned int exec_state : 2; /**< Read 0: no operation or operation completed, + 1: an operation is being performed, + 2: the operation is complete. */ + unsigned int cmd_code : 3; /**< Values represent 1: read, + 2: main_rgn Program, + 3: info_rgn Program, + 4: main_rgn Erase, + 5: info_rgn Erase, + 6: mass erase. */ + unsigned int reserved1 : 9; + unsigned int cmd_pgm_size : 6; /**< Program Size, unit:word(32bits). + 0x0:2, 0x1:4, 0x2:8,..., 0x0F:60, 0x10:64, + other values are invalid. */ + unsigned int reserved2 : 2; + unsigned int cmd_read_size : 2; /**< Read Size, unit:word(32bits). 0x0:1, 0x1:4, 0x2:8, 0x3:12. */ + unsigned int reserved3 : 2; + } BIT; +} volatile EFLASH_CMD_REG; + +/** + * @brief EFLASH address registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 2; + unsigned int cmd_addr : 22; /**< Program, erase, or read start address register. Unit:byte(8bits). + start address of Main_rgn: 0x00_0000, + start address of info_rgn: 0x80_0000, + note: the lower 2 bits cannot be written. */ + unsigned int reserved1 : 8; + } BIT; +} volatile EFLASH_ADDR_REG; + +/** + * @brief Command configuration registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int int_mode : 1; /**< Command operation mode 0:blocking mode, 1:interrupt mode. */ + unsigned int reserved1 : 30; + } BIT; +} volatile CMD_CFG_COMMON_REG; + +/** + * @brief The raw interrupt status registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 4; + unsigned int int_raw_finish : 1; /**< Operation completion status, + 0:no operation performed or operation completed, + 1:the operation completed. */ + unsigned int reserved1 : 11; + unsigned int int_raw_err_illegal : 1; /**< Invalid cmd operation errors, 0:no errors, + 1:cmd operation error. */ + unsigned int int_raw_err_erase : 1; /**< ERASE error, 0:pass, 1:failure. */ + unsigned int int_raw_err_ahb : 1; /**< AHB request error, 0:no errors, 1:AHB read address request + exceeds the range of MAIN Information Region or + AHB write request occurs. */ + unsigned int int_raw_err_ecc_corr : 1; /**< MAIN Information Region Read Data ECC Correction Error, + 0:no errors, 1:Uncorrectable ECC error occurred. */ + unsigned int int_raw_err_ecc_chk : 1; /**< MAIN Information Region read data ECC error, 0:no errors, + 1:an ECC check error occurred. */ + unsigned int reserved2 : 11; + } BIT; +} volatile INT_RAW_STATUS_REG; + +/** + * @brief The interrupt status registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 4; + unsigned int int_finish : 1; /**< Operation completion status, + 0:no operation performed or operation completed, + 1:the operation completed. */ + unsigned int reserved1 : 11; + unsigned int int_err_illegal : 1; /**< Invalid cmd operation errors, 0:no errors, + 1:cmd operation error. */ + unsigned int int_err_erase : 1; /**< ERASE error, 0:pass, 1:failure. */ + unsigned int int_err_ahb : 1; /**< AHB request error, 0:no errors, 1:AHB read address request + exceeds the range of MAIN Information Region or + AHB write request occurs. */ + unsigned int int_err_ecc_corr : 1; /**< MAIN Information Region Read Data ECC Correction Error, 0:no errors, + 1:Uncorrectable ECC error occurred. */ + unsigned int int_err_ecc_chk : 1; /**< MAIN Information Region read data ECC error, 0:no errors, + 1:an ECC check error occurred. */ + unsigned int reserved2 : 11; + } BIT; +} volatile INT_STATUS_REG; + +/** + * @brief The interrupt enable configuration registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 4; + unsigned int int_en_finish : 1; /**< Operation completion interrupt enable, 0:disable, 1:enable. */ + unsigned int reserved1 : 11; + unsigned int int_en_err_illegal : 1; /**< Invalid Cmd operation error interrupt enable, + 0:disable, 1:enable. */ + unsigned int int_en_err_erase : 1; /**< ERASE error interrupt enable, 0:disable, 1:enable. */ + unsigned int int_en_err_ahb : 1; /**< AHB request error interrupt enable, 0:disable, 1:enable. */ + unsigned int int_en_err_ecc_corr : 1; /**< Main Information region read data ECC correction error interrupt, + 0:disable, 1:enable. */ + unsigned int int_en_err_ecc_chk : 1; /**< Main Information region read data ECC check error interrupt enable, + 0:disable, 1:enable. */ + unsigned int reserved2 : 11; + } BIT; +} volatile INT_ENABLE_REG; + +/** + * @brief Interrupt clear registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 4; + unsigned int int_clr_finish : 1; /**< Operation completion interrupt clear, 0:not clear, + 1:clear raw interrupts and interrupt status. */ + unsigned int reserved1 : 11; + unsigned int int_clr_err_illegal : 1; /**< Invalid CMD operation error interrupt clear, 0:not clear, + 1:clear raw interrupts and interrupt status. */ + unsigned int int_clr_err_erase : 1; /**< erase error interrupt clear, 0:not clear, + 1:clear raw interrupts and interrupt status. */ + unsigned int int_clr_err_ahb : 1; /**< AHB request error interrupt clear, 0:not clear, + 1:clear raw interrupts and interrupt status. */ + unsigned int int_clr_err_ecc_corr : 1; /**< Main Information region read data ECC correction error + interrupt clear, 0:not clear, + 1:clear raw interrupts and interrupt status. */ + unsigned int int_clr_err_ecc_chk : 1; /**< Main Information region read data ECC error interrupt clear, + 0:not clear, 1:clear raw interrupts and interrupt status. */ + unsigned int reserved2 : 11; + } BIT; +} volatile INT_CLEAR_REG; + +/** + * @brief Prefetch control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int prefetch_enable : 1; /**< Prefetch control enable, 0:disabled, 1:enable. */ + unsigned int reserved0 : 7; + unsigned int prefetch_invalid_req : 1; /**< Cache Data Invalid Request Control. */ + unsigned int reserved1 : 23; + } BIT; +} volatile PREFETCH_CTRL_REG; + +/** + * @brief Cache control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cache_enable : 1; /**< Prefetch control enable, 0:disabled, 1:enable. */ + unsigned int reserved0 : 3; + unsigned int cache_replacement_sel : 1; /**< Cache replacement policy selection, 0:PLRU policy, + 1:round robin policy. */ + unsigned int reserved1 : 3; + unsigned int cache_invalid_req : 1; /**< Cache data invalid request, 0:invalidation, + 1:request cache invalid. */ + unsigned int reserved2 : 3; + unsigned int cache_policy_sel : 1; /**< Selecting a cache policy, 0:Normal Cache, + 1:Branch Cache. */ + unsigned int reserved3 : 19; + } BIT; +} volatile CACHE_CTRL_REG; + +/** + * @brief Flash ECC error detection and correction enable control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int flash_main_ecc_check_enable : 1; /**< Flash Main region error detection enable, + 0:no ECC check, 1:ECC check. */ + unsigned int flash_main_ecc_correct_enable : 1; /**< Flash Main region error correction enable, + 0:no ECC correction, 1:ECC correction. */ + unsigned int flash_info_ecc_check_enable : 1; /**< Flash Information region ECC error detection enable, + 0:no ECC check, 1:ECC check. */ + unsigned int flash_info_ecc_correct_enable : 1; /**< Flash Information region ECC error correction function, + 0:no ECC correction, 1:ECC correction. */ + unsigned int flash_ecc_blank_filter_enable : 1; /**< Flash unprogrammed area ECC mask and filter enable, + 0:disable, 1:enable. */ + unsigned int reserved0 : 27; + } BIT; +} volatile FLASH_ECC_CTRL_REG; + +/** + * @brief Flash status registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int opcode_illegal : 3; /**< Invalid opcode value. */ + unsigned int reserved0 : 1; + unsigned int mid_illegal : 3; /**< Invalid mid value. */ + unsigned int reserved1 : 1; + unsigned int info_rgn0_illegal : 1; /**< Illegally operation info_rgn0, 0:no error, + 1:illegally access occurs. */ + unsigned int info_rgn1_illegal : 1; /**< Illegally operation info_rgn1, 0:no error, + 1:illegally access occurs. */ + unsigned int info_rgn2_illegal : 1; /**< Illegally operation info_rgn2, 0:no error, + 1:illegally access occurs. */ + unsigned int reserved2 : 1; + unsigned int main_rgn0_illegal : 1; /**< Illegally operation main_rgn0, 0:no error, + 1:illegally access occurs. */ + unsigned int main_rgn1_illegal : 1; /**< Illegally operation main_rgn1, 0:no error, + 1:illegally access occurs. */ + unsigned int reserved3 : 2; + unsigned int parameter_illegal : 1; /**< Operation parameter is valid, 0:no error, + 1:Operation parameter error. */ + unsigned int address_unmap : 1; /**< Operation address out-of-bounds, 0:no error, + 1:address out-of-bounds error. */ + unsigned int reserved4 : 14; + } BIT; +} volatile FLASH_STATUS_REG; + +/** + * @brief Main region 0 start address registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 2; + unsigned int main_rgn0_start_addr : 15; /**< Region0 Access Start Address, Unit:Word(32bit). */ + unsigned int reserved1 : 15; + } BIT; +} volatile FLASH_REGION_0_START_ADDR_REG; + +/** + * @brief Main region 0 end address registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 2; + unsigned int main_rgn0_end_addr : 15; /**< Region0 Access End Address, Unit:Word(32bit). */ + unsigned int reserved1 : 15; + } BIT; +} volatile FLASH_REGION_0_END_ADDR_REG; + +/** + * @brief Main region0 control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int main_rgn0_mid_r : 8; /**< Indicates the mid that allows the read operation on region0. */ + unsigned int main_rgn0_mid_p : 8; /**< Indicates the MID that allows programming operations on region0. */ + unsigned int main_rgn0_mid_e : 8; /**< Indicates the MID that allows the erase operation on region0. */ + unsigned int reserved0 : 7; + unsigned int main_rgn0_active : 1; /**< Activate Zone Access Control, 0:not activated, 1:activated. */ + } BIT; +} volatile FLASH_REGION_0_CTRL_REG; + +/** + * @brief Main region 1 start address registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 2; + unsigned int main_rgn1_start_addr : 15; /**< Region1 Access Start Address, Unit:Word(32bit). */ + unsigned int reserved1 : 15; + } BIT; +} volatile FLASH_REGION_1_START_ADDR_REG; + +/** + * @brief Main region 1 end address registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 2; + unsigned int main_rgn1_end_addr : 15; /**< Region1 Access end Address, Unit:Word(32bit). */ + unsigned int reserved1 : 15; + } BIT; +} volatile FLASH_REGION_1_END_ADDR_REG; + +/** + * @brief Main region1 control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int main_rgn1_mid_r : 8; /**< Indicates the mid that allows the read operation on region1. */ + unsigned int main_rgn1_mid_p : 8; /**< Indicates the MID that allows programming operations on region1. */ + unsigned int main_rgn1_mid_e : 8; /**< Indicates the MID that allows the erase operation on region1. */ + unsigned int reserved0 : 7; + unsigned int main_rgn1_active : 1; /**< Activate Zone Access Control, 0:not activated, 1:activated. */ + } BIT; +} volatile FLASH_REGION_1_CTRL_REG; + +/** + * @brief Flash Module information 1 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int page_size : 16; /**< Info_rgn0/info_rgn1 capacity, unit:byte. */ + unsigned int information_capacity : 16; /**< Eflash page capacity, unit:byte. */ + } BIT; +} volatile EFLASH_CAPACITY_1_REG; + +/** + * @brief Flash Module information 2 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int io_read_length : 4; /**< Read I/O size. */ + unsigned int io_write_length_information : 4; /**< Write info region I/O size. */ + unsigned int io_write_length_main : 4; /**< Write main region I/O size. */ + unsigned int min_pgm_size_information : 4; /**< Minimal programming size of information region. */ + unsigned int min_pgm_size_main : 4; /**< Minimal programming size of main region. */ + unsigned int max_pgm_size : 4; /**< Max programming size. */ + unsigned int min_erase_size : 4; /**< Minimal erase size. */ + unsigned int reserved0 : 4; + } BIT; +} volatile EFLASH_CAPACITY_2_REG; + +/** + * @brief Flash clears the programming data buffer registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pgm_wdata_clr : 1; /**< Clear Control, 0:no effect, 1:clear current buffer. */ + unsigned int reserved0 : 7; + unsigned int pgm_wbuf_cnt : 8; /**< Obtains the size of the data in the buffer, unit:word. */ + unsigned int reserved1 : 16; + } BIT; +} volatile BUF_CLEAR_REG; + +/** + * @brief Flash clock divider registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 4; + unsigned int nread_div : 4; /**< Ratio of the system bus master clock to EFlash clock (n + 1). */ + unsigned int reserved1 : 12; + unsigned int busclk_sw_req : 1; /**< Check the cur_read_vref_cal or nread_div switchover is complete, + read 0:no finish, 1:finish. */ + unsigned int busclk_sw_protect : 1; /**< Frequency switching process protection, 0:enable, 1:disable. */ + unsigned int cur_read_vref_cal : 1; /**< Flash reference voltage calibration completion indicator. */ + unsigned int reserved2 : 1; + unsigned int data_vld_sel : 2; /**< Data_vld: one beat in advance or one beat later, + 0x0 and 0x01:no change, 0x02:take an early beat, + 0x03:delay a beat */ + unsigned int reserved3 : 6; + } BIT; +} volatile EFLASH_CLK_CFG_REG; + +/** + * @brief FLASH Register definition structure + */ +typedef struct { + EFLASH_CMD_REG EFLASH_CMD; /**< Command register, Offset Address: 0x0000. */ + EFLASH_ADDR_REG EFLASH_ADDR; /**< Address register, Offset Address: 0x0004. */ + unsigned char space0[120]; + CMD_CFG_COMMON_REG CMD_CFG_COMMON; /**< CMD configuration register, + Offset Address: 0x0080. */ + unsigned char space1[124]; + INT_RAW_STATUS_REG INT_RAW_STATUS; /**< Raw interrupt status register, + Offset Address: 0x0100. */ + INT_STATUS_REG INT_STATUS; /**< Interrupt status register, + Offset Address: 0x0104. */ + INT_ENABLE_REG INT_ENABLE; /**< Interrupt enable configuration register, + Offset Address: 0x0108. */ + INT_CLEAR_REG INT_CLEAR; /**< Interrupt clear register, + Offset Address: 0x010c. */ + unsigned char space2[16]; + PREFETCH_CTRL_REG PREFETCH_CTRL; /**< Prefetch control register, + Offset Address: 0x0120. */ + CACHE_CTRL_REG CACHE_CTRL; /**< Cache control register, Offset Address: 0x0124. */ + unsigned char space3[4]; + FLASH_ECC_CTRL_REG FLASH_ECC_CTRL; /**< Flash ECC error detection and correction enable + control register, Offset Address: 0x012c. */ + FLASH_STATUS_REG FLASH_STATUS; /**< CMD operation flash status register, + Offset Address: 0x0130. */ + unsigned char space4[4]; + unsigned int AHB_ERR_ADDR; /**< AHB error request address record register, + Offset Address: 0x0138. */ + unsigned char space5[8]; + FLASH_REGION_0_START_ADDR_REG FLASH_REGION0_START_ADDR; /**< Main region 0 start address, + Offset Address: 0x0144. */ + FLASH_REGION_0_END_ADDR_REG FLASH_REGION0_END_ADDR; /**< Main region 0 end address, + Offset Address: 0x0148. */ + FLASH_REGION_0_CTRL_REG FLASH_REGION0_CTRL; /**< Main region0 control register, + Offset Address: 0x014c. */ + FLASH_REGION_1_START_ADDR_REG FLASH_REGION1_START_ADDR; /**< Main region 1 start address, + Offset Address: 0x0150. */ + FLASH_REGION_1_END_ADDR_REG FLASH_REGION1_END_ADDR; /**< Main region 1 end address, + Offset Address: 0x0154. */ + FLASH_REGION_1_CTRL_REG FLASH_REGION1_CTRL; /**< Main region 1 control register, + Offset Address: 0x0158. */ + unsigned char space6[164]; + unsigned int MAGIC_LOCK; /**< CMD magic word protection register, + Offset Address: 0x0200. */ + unsigned char space7[492]; + unsigned int EFLASH_CAPACITY_0; /**< Module information register 0, + Offset Address: 0x03f0. */ + EFLASH_CAPACITY_1_REG EFLASH_CAPACITY_1; /**< Module information register 1, + Offset Address: 0x03f4. */ + EFLASH_CAPACITY_2_REG EFLASH_CAPACITY_2; /**< Module information register 2, + Offset Address: 0x03f8. */ + unsigned char space8[4]; + unsigned int PGM_WDATA; /**< Program data register, Offset Address: 0x0400. */ + unsigned char space9[508]; + unsigned int FLASH_RDATA; /**< Read data register, Offset Address: 0x0600. */ + BUF_CLEAR_REG BUF_CLEAR; /**< Programming data buffer cleanup register, + Offset Address: 0x0604. */ + unsigned int space10[206]; + EFLASH_CLK_CFG_REG EFLASH_CLK_CFG; /**< Clock divider register, Offset Address: 0x0940. */ +} volatile EFC_RegStruct; + +/** + * @} + */ + +/* Parameter check definition-------------------------------------------*/ +/** + * @brief Check Operation mode selection. + * @param opMode Flash Operation mode. + * @retval true + * @retval false + */ +static inline bool IsFlashOperationMode(FLASH_PE_OpMode opMode) +{ + return (opMode == FLASH_PE_OP_BLOCK || + opMode == FLASH_PE_OP_IT); +} + +/** + * @brief Check flash cmd code. + * @param cmdCode Flash cmd code. + * @retval true + * @retval false + */ +static inline bool IsFlashCmdCode(FLASH_CmdCodeType cmdCode) +{ + return (cmdCode == FLASH_CMD_READ || cmdCode == FLASH_CMD_MAIN_PROGEAM || \ + cmdCode == FLASH_CMD_INFO_PROGEAM || cmdCode == FLASH_CMD_MAIN_ERASE || \ + cmdCode == FLASH_CMD_INFO_ERASE || cmdCode == FLASH_CMD_MASS_ERASE); +} + +/** + * @brief Check flash cmd program size. + * @param size cmd program size, unit:Word(32bit). + * @retval true + * @retval false + */ +static inline bool IsFlashCmdProgramSize(unsigned int size) +{ + return size <= FLASH_MAX_CMD_PROGRAM_SIZE; +} + +/** + * @brief Check flash program address. + * @param addr program address, unit:Byte(8bit). + * @retval true + * @retval false + */ +static inline bool IsFlashProgramAddress(unsigned int addr) +{ + return (((addr % FLASH_MIN_PGM_BYTES_SIZE) == 0) && (addr < FLASH_MAX_SIZE)); +} + +/** + * @brief Check flash erase address. + * @param addr erase address, unit:Byte(8bit). + * @retval true + * @retval false + */ +static inline bool IsFlashEraseAddress(unsigned int addr) +{ + return ((addr % FLASH_ONE_PAGE_SIZE) == 0) && (addr <= FLASH_PAGE_MAX); +} + +/** + * @brief Check flash write source addresss. + * @param addr write source addresss. + * @retval true + * @retval false + */ +static inline bool IsFlashWriteSrcAddress(unsigned int addr) +{ + return ((addr >= FLASH_SRAM_START_ADDRESS && addr <= FLASH_SRAM_END_ADDRESS) || + (addr >= FLASH_MAIN_RNG_START_ADDRESS && addr <= FLASH_MAIN_RNG_END_ADDRESS)); +} + +/** + * @brief Check flash erase mode. + * @param mode flash erase mode. + * @retval true + * @retval false + */ +static inline bool IsFlashEraseMode(FLASH_EraseMode mode) +{ + return (mode == FLASH_ERASE_MODE_PAGE || mode == FLASH_ERASE_MODE_CHIP); +} + +/** + * @brief Enable flash command start. + * @param efc FLASH register base address. + * @retval None. + */ +static inline void DCL_FLASH_CmdStartEnable(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + efcx->EFLASH_CMD.BIT.cmd_start = BASE_CFG_ENABLE; +} + +/** + * @brief Disable flash command start. + * @param efcx FLASH register base address. + * @retval None. + */ +static inline void DCL_FLASH_CmdStartDisable(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + efcx->EFLASH_CMD.BIT.cmd_start = BASE_CFG_DISABLE; +} + +/** + * @brief Getting flash command start State. + * @param efcx FLASH register base address. + * @retval command start value, 1: Operation complete or no operation, 0: Operation is not complete. + */ +static inline unsigned int DCL_FLASH_GetCmdStartState(const EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + return efcx->EFLASH_CMD.BIT.cmd_start; +} + +/** + * @brief Setting FLASH cmd code. + * @param efcx FLASH register base address. + * @param cmdCode flash cmd code. + * @retval None. + */ +static inline void DCL_FLASH_SetCmdCode(EFC_RegStruct *efcx, FLASH_CmdCodeType cmdCode) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + FLASH_PARAM_CHECK_NO_RET(IsFlashCmdCode(cmdCode)); + efcx->EFLASH_CMD.BIT.cmd_code = cmdCode; +} + +/** + * @brief Getting FLASH cmd code. + * @param efcx FLASH register base address. + * @param cmdCode flash cmd code. + * @retval cmd code, 1:READ, 2:FLASH_CMD_MAIN_PROGEAM, 3:FLASH_CMD_INFO_PROGEAM, 4:FLASH_CMD_MAIN_ERASE, + 5:FLASH_CMD_INFO_ERASE, 6:FLASH_CMD_MASS_ERASE. + */ +static inline unsigned int DCL_FLASH_GetCmdCode(const EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + return efcx->EFLASH_CMD.BIT.cmd_code; +} + +/** + * @brief Setting FLASH cmd program size. + * @param efcx FLASH register base address. + * @param size flash cmd program size, unit:Word(32bit). + * @retval None. + */ +static inline void DCL_FLASH_SetCmdProgramSize(EFC_RegStruct *efcx, unsigned int size) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + FLASH_PARAM_CHECK_NO_RET(IsFlashCmdProgramSize(size)); + efcx->EFLASH_CMD.BIT.cmd_pgm_size = size; +} + +/** + * @brief Getting FLASH cmd program size. + * @param efcx FLASH register base address. + * @retval cmd program size, unit:Word(32bit). + */ +static inline unsigned int DCL_FLASH_GetCmdProgramSize(const EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + return efcx->EFLASH_CMD.BIT.cmd_pgm_size; +} + +/** + * @brief Setting FLASH program start address. + * @param efcx FLASH register base address. + * @param addr flash cmd program start address, unit:Byte(8bit). + * @retval None. + */ +static inline void DCL_FLASH_SetProgramAddress(EFC_RegStruct *efcx, unsigned int addr) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + FLASH_PARAM_CHECK_NO_RET(IsFlashProgramAddress(addr)); + efcx->EFLASH_ADDR.BIT.cmd_addr = addr; +} + +/** + * @brief Setting FLASH erase start address. + * @param efcx FLASH register base address. + * @param addr flash cmd erase start address, unit:Byte(8bit). + * @retval None. + */ +static inline void DCL_FLASH_SetEraseAddress(EFC_RegStruct *efcx, unsigned int addr) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + FLASH_PARAM_CHECK_NO_RET(IsFlashEraseAddress(addr)); + efcx->EFLASH_ADDR.BIT.cmd_addr = addr; +} + +/** + * @brief Getting FLASH cmd program, erase, read start address. + * @param efcx FLASH register base address. + * @retval cmd program, erase, read start address, unit:Byte(8bit). + */ +static inline unsigned int DCL_FLASH_GetCmdStartAddress(const EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + return efcx->EFLASH_ADDR.BIT.cmd_addr; +} + +/** + * @brief Setting FLASH operation mode. + * @param efcx FLASH register base address. + * @param mode flash operation mode. + * @retval None. + */ +static inline void DCL_FLASH_SetOptMode(EFC_RegStruct *efcx, FLASH_PE_OpMode mode) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + FLASH_PARAM_CHECK_NO_RET(IsFlashOperationMode(mode)); + efcx->CMD_CFG_COMMON.BIT.int_mode = mode; +} + +/** + * @brief Getting FLASH operation mode. + * @param efcx FLASH register base address. + * @retval operation mode, 0:FLASH_PE_OP_BLOCK, 1:FLASH_PE_OP_IT. + */ +static inline unsigned int DCL_FLASH_GetOptMode(const EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + return efcx->CMD_CFG_COMMON.BIT.int_mode; +} + +/** + * @brief Obtains the interrupt status. + * @param efcx FLASH register base address. + * @retval Interrupt Status. + */ +static inline unsigned int DCL_FLASH_GetInterrupRawtStatus(const EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + return efcx->INT_RAW_STATUS.reg; +} + +/** + * @brief Configuring Interrupt Enable. + * @param efcx FLASH register base address. + * @param intrEn Corresponding interrupt enable bit, for example, 110011. + * @retval None. + */ +static inline void DCL_FLASH_SetInterruptEn(EFC_RegStruct *efcx, unsigned int intrEn) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + efcx->INT_ENABLE.reg = intrEn; +} + +/** + * @brief Obtaining the Interrupt Enable Configuration. + * @param efcx FLASH register base address. + * @retval Interrupt enable value. + */ +static inline unsigned int DCL_FLASH_GetInterruptEnState(const EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + return efcx->INT_ENABLE.reg; +} + +/** + * @brief Clear Interrupt. + * @param efcx FLASH register base address. + * @param intrRaw Corresponding interrupt bit, for example, 110011. + * @retval None. + */ +static inline void DCL_FLASH_ClearIrq(EFC_RegStruct *efcx, unsigned int intrRaw) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + efcx->INT_CLEAR.reg = intrRaw; +} + +/** + * @brief FLASH cache invalid request enable. + * @param efcx FLASH register base address. + * @retval None. + */ +static inline void DCL_FLASH_CacheInvalidRequestEnable(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + efcx->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_ENABLE; +} + +/** + * @brief FLASH cache invalid request disable. + * @param efcx FLASH register base address. + * @retval None. + */ +static inline void DCL_FLASH_CacheInvalidRequestDisable(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + efcx->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_DISABLE; +} + +/** + * @brief Getting FLASH cache invalid request state. + * @param efcx FLASH register base address. + * @retval state 0:The latest invalid request has been completed, + 1:The latest invalid request is not completed. + */ +static inline unsigned int DCL_FLASH_GetCacheInvalidRequestState(const EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + return efcx->CACHE_CTRL.BIT.cache_invalid_req; +} + +/** + * @brief Getting FLASH command operation status. + * @param efcx FLASH register base address. + * @retval command operation status. + */ +static inline unsigned int DCL_FLASH_GetCommandOptStatus(const EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + return efcx->FLASH_STATUS.reg; +} + +/** + * @brief Setting FLASH magic lock. + * @param efcx FLASH register base address. + * @retval None. + */ +static inline void DCL_FLASH_MagicLock(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + efcx->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; +} + +/** + * @brief Setting FLASH magic unlock. + * @param efcx FLASH register base address. + * @retval None. + */ +static inline void DCL_FLASH_MagicUnlock(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + efcx->MAGIC_LOCK = FLASH_KEY_REGISTER_UNLOCK_VALUE; +} + +/** + * @brief Getting FLASH magic lock. + * @param efcx FLASH register base address. + * @retval The value of magic lock, The value 0xFEDC_BA98 indicates magic unlock, others values is magic lock. + */ +static inline unsigned int DCL_FLASH_GetMagicLock(const EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + return efcx->MAGIC_LOCK; +} + +/** + * @brief Setting FLASH program wdata value. + * @param efcx FLASH register base address. + * @param value The value of program wdata. + * @retval None. + */ +static inline void DCL_FLASH_SetProgramWdata(EFC_RegStruct *efcx, unsigned int value) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + efcx->PGM_WDATA = value; +} + +/** + * @brief FLASH program wdata celar enable. + * @param efcx FLASH register base address. + * @retval None. + */ +static inline void DCL_FLASH_ProgramWdataClearEnable(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + efcx->BUF_CLEAR.BIT.pgm_wdata_clr = BASE_CFG_ENABLE; +} + +/** + * @brief FLASH program wdata celar disable. + * @param efcx FLASH register base address. + * @retval None. + */ +static inline void DCL_FLASH_ProgramWdataClearDisable(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + efcx->BUF_CLEAR.BIT.pgm_wdata_clr = BASE_CFG_DISABLE; +} + +/** + * @brief Getting FLASH buf clear value. + * @param efcx FLASH register base address. + * @retval None. + */ +static inline unsigned int DCL_FLASH_GetBufClearValue(const EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(IsEFCInstance(efcx)); + return efcx->BUF_CLEAR.reg; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* #ifndef McuMagicTag_FLASH_IP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/flash/src/flash.c b/vendor/xinlingyu_92_3061M/Project/drivers/flash/src/flash.c new file mode 100644 index 0000000000000000000000000000000000000000..aff56ee931b3b4106dac09cd702dbf807f20a72e --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/flash/src/flash.c @@ -0,0 +1,749 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file flash.c + * @author MCU Driver Team + * @brief FLASH module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the FLASH. + * + Initialization and de-initialization functions. + * + Read, write, and erase functions. + */ + +/* Includes ------------------------------------------------------------------ */ +#include "flash.h" + +#define FLASH_CRC_SAVE_BUFFER_LEN 2 +#define FLASH_ALL_INTERRUPT_ENABLE 0x001F0010 +#define FLASH_ERR_INTERRUPT_MASK 0x001F0000 +#define FLASH_CMD_INTERRUPT_MASK 0x00000010 + +#define FLASH_KEY_REGISTER_UNLOCK_VALUE 0xFEDCBA98 +#define FLASH_KEY_REGISTER_LOCK_VALUE 0x0 + +#define FLASH_INT_ERR_ECC_CHK_MASK (1 << 20) +#define FLASH_INT_ERR_ECC_CORR_MASK (1 << 19) +#define FLASH_INT_ERR_AHB_MASK (1 << 18) +#define FLASH_INT_ERR_SMWR_MASK (1 << 17) +#define FLASH_INT_ERR_ILLEGAL_MASK (1 << 16) +#define FLASH_INT_FINISH_MASK (1<< 4) + +#define FLASH_INT_CLEAR_ALL 0xFFFFFFFF + +/** + * @brief Check whether errors occur. + * @param handle FLASH handle. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +static BASE_StatusType CheckErrorStatus(FLASH_Handle *handle) +{ + /* Check whether errors occur. */ + if (handle->baseAddress->INT_RAW_STATUS.BIT.int_raw_err_illegal || + handle->baseAddress->INT_RAW_STATUS.BIT.int_raw_err_erase) { + return BASE_STATUS_ERROR; + } + if (handle->baseAddress->FLASH_STATUS.reg != 0) { + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief Writes to the flash memory in the unit of words. + * @param handle FLASH handle. + * @param wordNum Number of size written, unit: word. + * @retval None. + */ +static void FlashPopulateDefaults(FLASH_Handle *handle, const unsigned int wordNum) +{ + /* Complement missing data values. */ + if (wordNum % FLASH_MIN_PGM_WORDS_SIZE) { + for (unsigned int i = (wordNum % FLASH_MIN_PGM_WORDS_SIZE); i < FLASH_MIN_PGM_WORDS_SIZE; i++) { + handle->baseAddress->PGM_WDATA = 0xFFFFFFFF; /* The default value of flash is 0xFFFFFFFF. */ + } + } +} + +/** + * @brief Writes to the flash memory in the unit of words. + * @param handle FLASH handle. + * @param srcAddr Start address of the data buffer to be written. + * @param destAddr Flash destination address, which must be word-aligned. + * @param size Number of size written, unit: byte. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +static BASE_StatusType FLASH_WriteWords(FLASH_Handle *handle, + const unsigned int srcAddr, + const unsigned int destAddr, + const unsigned int size) +{ + unsigned int *data = NULL; + unsigned int i; + unsigned int writeSize; + unsigned int wordNum; + /* Make sure the last operation is complete. */ + if (handle->baseAddress->EFLASH_CMD.BIT.cmd_start) { + return BASE_STATUS_BUSY; + } + + /* Get the number of last remaining data. */ + wordNum = size / FLASH_ONE_WORD_BYTES_SIZE; + wordNum += ((size % FLASH_ONE_WORD_BYTES_SIZE) == 0) ? 0 : 1; + + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_UNLOCK_VALUE; + /* The mask of program wdata celar is 0xFF. */ + if ((handle->baseAddress->BUF_CLEAR.reg >> FLASH_PGM_WBUF_CNT_POS) & 0xFF) { + handle->baseAddress->BUF_CLEAR.BIT.pgm_wdata_clr = BASE_CFG_SET; /* program wdata celar enable. */ + } + + /* Step 1: Calculated the cmd program size, get srcAddress and get destAddress. */ + writeSize = ((wordNum % FLASH_MIN_PGM_WORDS_SIZE) != 0) ? (wordNum / FLASH_MIN_PGM_WORDS_SIZE + 1) : + wordNum / FLASH_MIN_PGM_WORDS_SIZE; + data = (unsigned int *)(uintptr_t)srcAddr; + handle->baseAddress->EFLASH_ADDR.BIT.cmd_addr = destAddr; + for (i = 0; i < wordNum; i++) { + handle->baseAddress->PGM_WDATA = *data; + data++; + } + /* Complement missing data values. */ + FlashPopulateDefaults(handle, wordNum); + + /* Step 2: Configure the parameters and start programming. */ + handle->baseAddress->EFLASH_CMD.BIT.cmd_pgm_size = writeSize; + handle->baseAddress->EFLASH_CMD.BIT.cmd_code = FLASH_OPERATION_PROGRAM; + handle->baseAddress->EFLASH_CMD.BIT.cmd_start = BASE_CFG_SET; + + /* Step 3: If the blocking mode is used, wait until the program operation is complete. */ + if (handle->peMode == FLASH_PE_OP_BLOCK) { + while (handle->baseAddress->EFLASH_CMD.BIT.cmd_start) { + ; + } + if (CheckErrorStatus(handle) != BASE_STATUS_OK) { + /* Clears data in the cache and clears the interrupt flag. */ + handle->baseAddress->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_SET; + handle->baseAddress->INT_CLEAR.reg = FLASH_INT_CLEAR_ALL; + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; + return BASE_STATUS_ERROR; + } + handle->baseAddress->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_SET; + handle->baseAddress->INT_CLEAR.reg = FLASH_INT_CLEAR_ALL; + } + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; + return BASE_STATUS_OK; +} + +/** + * @brief Obtains the number of words to be supplemented for write alignment to prevent cross-page write. + * @param handle FLASH handle. + * @retval Words. + */ +static unsigned int FLASH_GetWriteAlignmentWords(FLASH_Handle *handle) +{ + unsigned int numWords; + /* Step 1: Calculate the number of words occupied at the start address. */ + numWords = handle->destAddr % FLASH_MAX_PGM_WORD_SIZE; + if (numWords > 0) { + /* Step 2: Calculate the number of words in the remaining space of the ROW. */ + return FLASH_MAX_PGM_WORD_SIZE - numWords; + } + return 0; +} + +/** + * @brief Flash erase operation. + * @param handle FLASH handle. + * @param startAddr Erasing start address, which must be aligned with the minimum erasing unit. + * @param mode Erasing operation mode, supporting chip,and page. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +static BASE_StatusType FLASH_EraseWithMode(FLASH_Handle *handle, unsigned int startAddr, unsigned int mode) +{ + /* Make sure the last operation is complete. */ + if (handle->baseAddress->EFLASH_CMD.BIT.cmd_start) { + return BASE_STATUS_BUSY; + } + + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_UNLOCK_VALUE; + + /* Step 1: Configure the erase start address and erase mode, then make cmd_satrt enable. */ + handle->baseAddress->EFLASH_ADDR.BIT.cmd_addr = startAddr; + handle->baseAddress->EFLASH_CMD.BIT.cmd_code = mode; + handle->baseAddress->EFLASH_CMD.BIT.cmd_start = BASE_CFG_SET; + + /* Step 2: If the blocking mode is used, wait until the erase operation is complete. */ + if (handle->peMode == FLASH_PE_OP_BLOCK) { + while (handle->baseAddress->EFLASH_CMD.BIT.cmd_start) { + ; + } + /* Check whether errors occur. */ + if (handle->baseAddress->INT_RAW_STATUS.BIT.int_raw_err_illegal || + handle->baseAddress->INT_RAW_STATUS.BIT.int_raw_err_erase) { + handle->baseAddress->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_SET; + handle->baseAddress->INT_CLEAR.reg = FLASH_INT_CLEAR_ALL; + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; + return BASE_STATUS_ERROR; + } + if (handle->baseAddress->FLASH_STATUS.reg != 0) { + handle->baseAddress->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_SET; + handle->baseAddress->INT_CLEAR.reg = FLASH_INT_CLEAR_ALL; + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; + return BASE_STATUS_ERROR; + } + } + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; + return BASE_STATUS_OK; +} + +/** + * @brief Write interrupt processing function, + * which completes the internal processing of the write operation in interrupt mode. + * @param handle FLASH handle. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +static BASE_StatusType FLASH_WriteHandler(FLASH_Handle *handle) +{ + unsigned int dataLeft; + unsigned int tempAddr; + BASE_StatusType ret; + /* If the number of bytes to be written is greater than a Row, + data is written based on the bytes number of a row. */ + if ((handle->writeLen / FLASH_MAX_PGM_BYTE_SIZE) > 0) { + handle->handleEx.onceOperateLen = FLASH_MAX_PGM_BYTE_SIZE; + ret = FLASH_WriteWords(handle, handle->srcAddr, handle->destAddr, FLASH_MAX_PGM_BYTE_SIZE); + if (ret != BASE_STATUS_OK) { + handle->handleEx.onceOperateLen = 0; + return ret; + } + } else if (handle->writeLen > 0) { + /* If the number of bytes to be written is less than a Row, + data is written in the unit of words. In addition, if data is less than one word, complete one word. */ + dataLeft = handle->writeLen; + + /* Updata the srcAddress, destAddress and write length. */ + tempAddr = (dataLeft / FLASH_ONE_WORD_BYTES_SIZE); + if (tempAddr == 0) { + tempAddr = FLASH_ONE_WORD_BYTES_SIZE; + } else { /* Get the address change value, aligned with 4words. */ + tempAddr = ((tempAddr % FLASH_ONE_WORD_BYTES_SIZE) == 0) ? tempAddr : + ((tempAddr / FLASH_ONE_WORD_BYTES_SIZE + 1) * FLASH_ONE_WORD_BYTES_SIZE); + } + handle->handleEx.onceOperateLen = tempAddr; + + ret = FLASH_WriteWords(handle, handle->srcAddr, handle->destAddr, dataLeft); + if (ret != BASE_STATUS_OK) { + handle->handleEx.onceOperateLen = 0; + return ret; + } + } + return BASE_STATUS_OK; +} + +/** + * @brief Erase interrupt processing function, + * which completes the internal processing of the erase operation in interrupt mode. + * @param handle FLASH handle. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +static BASE_StatusType FLASH_EraseHandler(FLASH_Handle *handle) +{ + /* Check whether the erasing mode is valid. */ + FLASH_PARAM_CHECK_WITH_RET((handle->destAddr <= (FLASH_PAGE_MAX / FLASH_ONE_WORD_BYTES_SIZE)), BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET((handle->destAddr % (FLASH_ONE_PAGE_WORD_SIZE) == 0), BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET((((FLASH_MAX_PAGE_NUM - (handle->destAddr / FLASH_ONE_PAGE_WORD_SIZE)) >=\ + handle->eraseNum) && handle->eraseNum > 0), BASE_STATUS_ERROR); + + BASE_StatusType ret; + handle->handleEx.onceOperateLen = 0x01; /* Erase 1 page at a time. */ + ret = FLASH_EraseWithMode(handle, handle->destAddr, FLASH_ERASE_MODE_PAGE); + if (ret != BASE_STATUS_OK) { + handle->handleEx.onceOperateLen = 0; + return ret; + } + return BASE_STATUS_OK; +} + +/** + * @brief Initializing the FLASH Module. + * @param handle FLASH handle. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +BASE_StatusType HAL_FLASH_Init(FLASH_Handle *handle) +{ + FLASH_ASSERT_PARAM(handle != NULL); + FLASH_ASSERT_PARAM(IsEFCInstance(handle->baseAddress)); + FLASH_PARAM_CHECK_WITH_RET(IsFlashOperationMode(handle->peMode), BASE_STATUS_ERROR); + + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_UNLOCK_VALUE; /* Unlock key registers */ + if (handle->peMode == FLASH_PE_OP_IT) { + /* Enable the interrupt mode and clear the interrupt flag bit. */ + handle->baseAddress->CMD_CFG_COMMON.BIT.int_mode = BASE_CFG_SET; + handle->baseAddress->INT_ENABLE.reg = FLASH_ALL_INTERRUPT_ENABLE; + handle->baseAddress->INT_CLEAR.reg = FLASH_ALL_INTERRUPT_ENABLE; + } else { + /* If blocking mode is used, disable int_mode. */ + handle->baseAddress->CMD_CFG_COMMON.BIT.int_mode = BASE_CFG_UNSET; + } + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; /* Lock key registers */ + handle->state = FLASH_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief Deinitialize the FLASH Module. + * @param handle FLASH handle. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +BASE_StatusType HAL_FLASH_DeInit(FLASH_Handle *handle) +{ + FLASH_ASSERT_PARAM(handle != NULL); + FLASH_ASSERT_PARAM(IsEFCInstance(handle->baseAddress)); + handle->state = FLASH_STATE_RESET; + handle->userCallBack.FlashCallBack = NULL; /* Clean interrupt callback functions. */ + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_UNLOCK_VALUE; + /* Disable interrupt mode and interrupt enable bit. */ + handle->baseAddress->CMD_CFG_COMMON.BIT.int_mode = BASE_CFG_UNSET; + handle->baseAddress->INT_ENABLE.reg = 0x00000000; + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; /* Locking Key Registers */ + return BASE_STATUS_OK; +} + +/** + * @brief Registering the Callback Function of the Flash Module. + * @param handle FLASH handle. + * @param pcallback Pointer to the callback function. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +BASE_StatusType HAL_FLASH_RegisterCallback(FLASH_Handle *handle, FLASH_CallbackFunType pcallback) +{ + FLASH_ASSERT_PARAM(handle != NULL); + FLASH_ASSERT_PARAM(IsEFCInstance(handle->baseAddress)); + handle->userCallBack.FlashCallBack = pcallback; + return BASE_STATUS_OK; +} + +/** + * @brief blocking write error handle. + * @param handle FLASH handle. + * @retval None. + */ +static void FLASH_WritteBlockingErrorHandle(FLASH_Handle *handle) +{ + handle->baseAddress->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_SET; + handle->baseAddress->INT_CLEAR.reg = FLASH_INT_CLEAR_ALL; + handle->state = FLASH_STATE_READY; +} + +/** + * @brief Write the flash memory in blocking mode. + * @param handle FLASH handle. + * @param srcAddr Start address of the data buffer to be written. + * @param destAddr Start address of the flash to be written.The address must be aligned with the minimum writable unit. + * @param srcLen Length of data to be written,unit:bytes. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +BASE_StatusType HAL_FLASH_WriteBlocking(FLASH_Handle *handle, unsigned int srcAddr, + unsigned int destAddr, const unsigned int srcLen) +{ + BASE_StatusType ret; + unsigned int i; + unsigned int currentLen; + unsigned int currentWords; + unsigned int dataLeft; + /* Check related parameters. */ + FLASH_ASSERT_PARAM(handle != NULL); + FLASH_ASSERT_PARAM(IsEFCInstance(handle->baseAddress)); + FLASH_PARAM_CHECK_WITH_RET((handle->peMode == FLASH_PE_OP_BLOCK), BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(handle->state == FLASH_STATE_READY, BASE_STATUS_ERROR); + /* Check whether the write address is valid. */ + FLASH_PARAM_CHECK_WITH_RET(IsFlashWriteSrcAddress(srcAddr), BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET((destAddr < FLASH_MAX_SIZE), BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET((destAddr % FLASH_MIN_PGM_BYTES_SIZE) == 0, BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(srcLen > 0, BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(srcLen <= (FLASH_MAX_SIZE - destAddr), BASE_STATUS_ERROR); + + handle->state = FLASH_STATE_PGM; + handle->destAddr = destAddr / FLASH_ONE_WORD_BYTES_SIZE; /* Convert the destination address unit to word. */ + handle->srcAddr = srcAddr; + + /* Get the number of words in the remaining space of the ROW. */ + currentWords = FLASH_GetWriteAlignmentWords(handle); + /* Step 1: If there is remaining space and write length greater than remaining space, + write data in the remaining space. */ + if (srcLen > (currentWords * FLASH_ONE_WORD_BYTES_SIZE) && currentWords > 0) { + ret = FLASH_WriteWords(handle, handle->srcAddr, handle->destAddr, (currentWords * FLASH_ONE_WORD_BYTES_SIZE)); + if (ret != BASE_STATUS_OK) { + FLASH_WritteBlockingErrorHandle(handle); + return ret; + } + handle->srcAddr += currentWords * FLASH_ONE_WORD_BYTES_SIZE; + handle->destAddr += currentWords; + currentLen = srcLen - currentWords * FLASH_ONE_WORD_BYTES_SIZE; + } else { + currentLen = srcLen; + } + /* Step 2: If the number of bytes to be written is greater than a Row, + data is written based on the bytes number of a row. */ + for (i = 0; i < currentLen / FLASH_MAX_PGM_BYTE_SIZE; i++) { + ret = FLASH_WriteWords(handle, handle->srcAddr, handle->destAddr, FLASH_MAX_PGM_BYTE_SIZE); + if (ret != BASE_STATUS_OK) { + FLASH_WritteBlockingErrorHandle(handle); + return ret; + } + handle->srcAddr += FLASH_MAX_PGM_WORD_SIZE * FLASH_ONE_WORD_BYTES_SIZE; + handle->destAddr += FLASH_MAX_PGM_WORD_SIZE; + } + + /* Get the number of last remaining data. */ + dataLeft = currentLen % FLASH_MAX_PGM_BYTE_SIZE; + if (dataLeft > 0) { /* This branch is executed only when the remaining data is not completely written. */ + ret = FLASH_WriteWords(handle, handle->srcAddr, handle->destAddr, dataLeft); + } + + FLASH_WritteBlockingErrorHandle(handle); + return ret; +} + +/** + * @brief WriteErase the flash memory in blocking mode. + * @param handle FLASH handle. + * @param eraseMode Erasing mode. The options are chip erasing and page erasing. + * @param startAddr Start address of the flash to be erase. The address must be aligned with the minimum erasable unit. + * @param eraseNum Number of pages to be erased. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +BASE_StatusType HAL_FLASH_EraseBlocking(FLASH_Handle *handle, FLASH_EraseMode eraseMode, + FLASH_SectorAddr startAddr, unsigned int eraseNum) +{ + /* Check related parameters. */ + FLASH_ASSERT_PARAM(handle != NULL); + FLASH_ASSERT_PARAM(IsEFCInstance(handle->baseAddress)); + FLASH_PARAM_CHECK_WITH_RET((handle->peMode == FLASH_PE_OP_BLOCK), BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(handle->state == FLASH_STATE_READY, BASE_STATUS_ERROR); + /* Check whether the erasing mode is valid. */ + FLASH_PARAM_CHECK_WITH_RET(IsFlashEraseMode(eraseMode), BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET((startAddr <= FLASH_PAGE_MAX), BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET((startAddr % FLASH_ONE_PAGE_SIZE == 0) || (eraseMode == FLASH_ERASE_MODE_CHIP),\ + BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(eraseNum > 0 && eraseNum <= (FLASH_MAX_PAGE_NUM - startAddr / FLASH_ONE_PAGE_SIZE),\ + BASE_STATUS_ERROR); + + BASE_StatusType ret = BASE_STATUS_OK; + + handle->eraseNum = eraseNum; + handle->destAddr = startAddr / sizeof(unsigned int); /* Convert the destination address unit to word. */ + handle->state = FLASH_STATE_ERASE; + + if (eraseMode == FLASH_ERASE_MODE_CHIP) { + /* If the FLASH_ERASE_MODE_CHIP mode is used, all contents in the flash memory are erased. */ + ret = FLASH_EraseWithMode(handle, handle->destAddr, FLASH_ERASE_MODE_CHIP); + if (ret != BASE_STATUS_OK) { + handle->baseAddress->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_SET; + handle->state = FLASH_STATE_READY; + return ret; + } + } else if (eraseMode == FLASH_ERASE_MODE_PAGE) { + /* If the FLASH_ERASE_MODE_PAGE mode is used, erasing requires page-by-page. */ + while (handle->eraseNum) { + ret = FLASH_EraseHandler(handle); + if (ret != BASE_STATUS_OK) { + handle->baseAddress->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_SET; + handle->state = FLASH_STATE_READY; + return ret; + } + /* Updata the erase destAddress and erase number. */ + handle->destAddr += FLASH_ONE_PAGE_SIZE / sizeof(unsigned int); + handle->eraseNum--; + } + } + /* Clear the data in the cache to invalidate the data. */ + handle->baseAddress->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_SET; + handle->state = FLASH_STATE_READY; + return ret; +} + +/** + * @brief Write the flash memory in interrupt mode. + * @param handle FLASH handle. + * @param srcAddr Start address of the data buffer to be written. + * @param destAddr Start address of the flash to be written.The address must be aligned with the minimum writable unit. + * @param srcLen Length of data to be written,unit:bytes. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +BASE_StatusType HAL_FLASH_WriteIT(FLASH_Handle *handle, unsigned int srcAddr, + unsigned int destAddr, unsigned int srcLen) +{ + unsigned int currentWords; + BASE_StatusType ret; + /* Check the validity of the base address and operation mode of the flash memory. */ + FLASH_ASSERT_PARAM(handle != NULL); + FLASH_ASSERT_PARAM(IsEFCInstance(handle->baseAddress)); + FLASH_PARAM_CHECK_WITH_RET((handle->peMode == FLASH_PE_OP_IT), BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(handle->state == FLASH_STATE_READY, BASE_STATUS_ERROR); + /* Check whether the write address is valid. */ + FLASH_PARAM_CHECK_WITH_RET(IsFlashWriteSrcAddress(srcAddr), BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET((destAddr < FLASH_MAX_SIZE), BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET((destAddr % FLASH_MIN_PGM_BYTES_SIZE) == 0, BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET((srcLen > 0), BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(srcLen <= (FLASH_MAX_SIZE - destAddr), BASE_STATUS_ERROR); + + handle->state = FLASH_STATE_PGM; + handle->destAddr = destAddr / FLASH_ONE_WORD_BYTES_SIZE; /* Convert the destination address unit to word. */ + handle->srcAddr = srcAddr; + handle->writeLen = srcLen; + + /* Get the number of words in the remaining space of the ROW. */ + currentWords = FLASH_GetWriteAlignmentWords(handle); + /* If there is remaining space and write length greater than remaining space, + write data in the remaining space. */ + if (handle->writeLen > (currentWords * FLASH_ONE_WORD_BYTES_SIZE) && currentWords > 0) { + handle->handleEx.onceOperateLen = (currentWords * FLASH_ONE_WORD_BYTES_SIZE); + ret = FLASH_WriteWords(handle, handle->srcAddr, handle->destAddr, (currentWords * FLASH_ONE_WORD_BYTES_SIZE)); + if (ret != BASE_STATUS_OK) { + handle->handleEx.onceOperateLen = 0; + handle->state = FLASH_STATE_READY; + return ret; + } + } else { + /* Write the last remaining data. */ + ret = FLASH_WriteHandler(handle); + if (ret != BASE_STATUS_OK) { + handle->state = FLASH_STATE_READY; + return ret; + } + } + return BASE_STATUS_OK; +} + +/** + * @brief WriteErase the flash memory in interrupt mode. + * @param handle FLASH handle. + * @param eraseMode Erasing mode. The options are chip erasing and page erasing. + * @param startAddr Start address of the flash to be erase. The address must be aligned with the minimum erasable unit. + * @param eraseNum Number of pages to be erased. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +BASE_StatusType HAL_FLASH_EraseIT(FLASH_Handle *handle, FLASH_EraseMode eraseMode, + FLASH_SectorAddr startAddr, unsigned int eraseNum) +{ + BASE_StatusType ret = BASE_STATUS_OK; + FLASH_ASSERT_PARAM(handle != NULL); + FLASH_ASSERT_PARAM(IsEFCInstance(handle->baseAddress)); + FLASH_PARAM_CHECK_WITH_RET((handle->peMode == FLASH_PE_OP_IT), BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET((handle->state == FLASH_STATE_READY), BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(IsFlashEraseMode(eraseMode), BASE_STATUS_ERROR); + /* Check whether the address is valid. */ + FLASH_PARAM_CHECK_WITH_RET((startAddr <= FLASH_PAGE_MAX), BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET((startAddr % FLASH_ONE_PAGE_SIZE == 0) || (eraseMode == FLASH_ERASE_MODE_CHIP),\ + BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(eraseNum > 0 && eraseNum <= (FLASH_MAX_PAGE_NUM - startAddr / FLASH_ONE_PAGE_SIZE),\ + BASE_STATUS_ERROR); + /* Obtains the value entered by the user. */ + handle->eraseNum = eraseNum; + handle->state = FLASH_STATE_ERASE; + handle->destAddr = startAddr / sizeof(unsigned int); /* Convert the destination address unit to word. */ + + if (eraseMode == FLASH_ERASE_MODE_CHIP) { + /* If the FLASH_ERASE_MODE_CHIP mode is used, all contents in the flash memory are erased. */ + handle->handleEx.onceOperateLen = handle->eraseNum; + ret = FLASH_EraseWithMode(handle, handle->destAddr, FLASH_ERASE_MODE_CHIP); + if (ret != BASE_STATUS_OK) { + handle->handleEx.onceOperateLen = 0; + handle->state = FLASH_STATE_READY; + return ret; + } + } else if (eraseMode == FLASH_ERASE_MODE_PAGE) { + /* If the FLASH_ERASE_MODE_PAGE mode is used, erasing requires page-by-page. */ + ret = FLASH_EraseHandler(handle); + if (ret != BASE_STATUS_OK) { + handle->state = FLASH_STATE_READY; + return ret; + } + } + return BASE_STATUS_OK; +} + +/** + * @brief Interface for reading data from the flash memory. + * @param handle FLASH handle. + * @param srcAddr Flash address of the data to be read. The address must be aligned with the minimum readable unit. + * @param readLen Read Data Length,unit:bytes. + * @param dataBuff Buffer for storing read data. + * @param buffLen Buffer size for storing read data,unit:bytes. + * @retval BASE_StatusType: BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT. + */ +BASE_StatusType HAL_FLASH_Read(FLASH_Handle *handle, + unsigned int srcAddr, + unsigned int readLen, + unsigned char *dataBuff, + unsigned int buffLen) +{ + unsigned char *ptemp = NULL; + unsigned char *dtemp = NULL; + unsigned int tempLen = readLen; +#ifndef FLASH_PARAM_CHECK + BASE_FUNC_UNUSED(handle); /* Used to avoid code check alarm prompts. */ +#endif + FLASH_ASSERT_PARAM(handle != NULL); + FLASH_ASSERT_PARAM(IsEFCInstance(handle->baseAddress)); + FLASH_ASSERT_PARAM(dataBuff != NULL); + FLASH_PARAM_CHECK_WITH_RET(srcAddr < FLASH_MAX_SIZE, BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(readLen <= (FLASH_MAX_SIZE - srcAddr), BASE_STATUS_ERROR); + + dtemp = dataBuff; + /* The basic offset address needs to be added to srcAddress. */ + ptemp = (unsigned char *)(uintptr_t)srcAddr + FLASH_READ_BASE; + if (readLen > buffLen) { + return BASE_STATUS_ERROR; + } + while (tempLen > 0) { /* Read data cyclically. */ + tempLen--; + *dtemp++ = *ptemp++; + } + return BASE_STATUS_OK; +} + +/** + * @brief Interrupt Processing Write. + * @param handle FLASH handle. + * @param status Interrupt status + * @retval None + */ +static void InterruptWriteHandle(FLASH_Handle *handle, unsigned int status) +{ + /* Check whether the parameter is valid. */ + FLASH_PARAM_CHECK_NO_RET(IsFlashWriteSrcAddress(handle->srcAddr)); + FLASH_PARAM_CHECK_NO_RET((handle->destAddr % FLASH_MIN_PGM_WORDS_SIZE) == 0); + FLASH_PARAM_CHECK_NO_RET((handle->destAddr <= (FLASH_MAX_SIZE / FLASH_ONE_WORD_BYTES_SIZE))); + FLASH_PARAM_CHECK_NO_RET(handle->writeLen <= (FLASH_MAX_SIZE - (handle->destAddr * FLASH_ONE_WORD_BYTES_SIZE))); + /* One operation complete */ + if ((status & FLASH_INT_FINISH_MASK) > 0) { + if (handle->userCallBack.FlashCallBack != NULL) { + handle->userCallBack.FlashCallBack(handle, FLASH_WRITE_EVENT_SUCCESS, handle->destAddr); + } + } + /* All operations are complete. */ + if (handle->writeLen == 0) { + if (handle->userCallBack.FlashCallBack != NULL) { + handle->userCallBack.FlashCallBack(handle, FLASH_WRITE_EVENT_DONE, handle->destAddr); + } + handle->baseAddress->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_SET; + handle->state = FLASH_STATE_READY; + } else { + FLASH_WriteHandler(handle); + } +} + +/** + * @brief Interrupt processing erase. + * @param handle FLASH handle. + * @param status Interrupt status + * @retval None + */ +static void InterruptEraseHandle(FLASH_Handle *handle, unsigned int status) +{ + /* One operation complete */ + if ((status & FLASH_INT_FINISH_MASK) > 0) { + if (handle->userCallBack.FlashCallBack != NULL) { + handle->userCallBack.FlashCallBack(handle, FLASH_ERASE_EVENT_SUCCESS, handle->destAddr); + } + } + /* All operations are complete. */ + if (handle->eraseNum == 0) { + if (handle->userCallBack.FlashCallBack != NULL) { + handle->userCallBack.FlashCallBack(handle, FLASH_ERASE_EVENT_DONE, handle->destAddr); + } + handle->baseAddress->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_SET; + handle->state = FLASH_STATE_READY; + } else { + FLASH_EraseHandler(handle); + } +} + +/** + * @brief Interrupt Handling Function. + * @param handle Handle pointers + * @retval None + */ +void HAL_FLASH_IrqHandler(void *handle) +{ + FLASH_Handle *flashHandle = (FLASH_Handle *)handle; + unsigned int status; + FLASH_ASSERT_PARAM(flashHandle != NULL); + FLASH_ASSERT_PARAM(IsEFCInstance(flashHandle->baseAddress)); + FLASH_PARAM_CHECK_NO_RET(flashHandle->peMode == FLASH_PE_OP_IT); + + status = flashHandle->baseAddress->INT_RAW_STATUS.reg; + flashHandle->baseAddress->INT_CLEAR.reg = status & FLASH_CMD_INTERRUPT_MASK; + /* Invoke the function for programming or erasing. */ + if (flashHandle->state == FLASH_STATE_PGM) { /* If state is FLASH_STATE_PGM, call write callback function. */ + if (flashHandle->writeLen < flashHandle->handleEx.onceOperateLen) { + flashHandle->writeLen = 0; + flashHandle->destAddr += flashHandle->handleEx.onceOperateLen >> 0x02; + } else { + flashHandle->writeLen -= flashHandle->handleEx.onceOperateLen; + flashHandle->srcAddr += flashHandle->handleEx.onceOperateLen; + flashHandle->destAddr += flashHandle->handleEx.onceOperateLen >> 0x02; /* Unit conversion to word */ + } + flashHandle->handleEx.onceOperateLen = 0; + InterruptWriteHandle(flashHandle, status); + } else if (flashHandle->state == FLASH_STATE_ERASE) { + if (flashHandle->handleEx.onceOperateLen != 0x00) { /* Erase page data valid. */ + flashHandle->destAddr += + (FLASH_ONE_PAGE_SIZE * flashHandle->handleEx.onceOperateLen) / sizeof(unsigned int); + flashHandle->eraseNum -= flashHandle->handleEx.onceOperateLen; + } else { + flashHandle->eraseNum = 0; /* Illegal state generation, and the status data is cleared. */ + } + flashHandle->handleEx.onceOperateLen = 0; + + /* If state is FLASH_STATE_ERASE, call erase callback function. */ + InterruptEraseHandle(flashHandle, status); + } +} + +/** + * @brief Flash Error interrupt Handling Function. + * @param handle Handle pointers + * @retval None + */ +void HAL_FLASH_IrqHandlerError(void *handle) +{ + FLASH_Handle *flashHandle = (FLASH_Handle *)handle; + unsigned int status; + FLASH_ASSERT_PARAM(flashHandle != NULL); + FLASH_ASSERT_PARAM(IsEFCInstance(flashHandle->baseAddress)); + status = flashHandle->baseAddress->INT_RAW_STATUS.reg; + flashHandle->baseAddress->INT_CLEAR.reg = status & FLASH_ERR_INTERRUPT_MASK; + + /* If any error occurs, call the programming error or erase error callback function. */ + if ((status & (FLASH_INT_ERR_ECC_CHK_MASK | FLASH_INT_ERR_ECC_CORR_MASK | + FLASH_INT_ERR_AHB_MASK | FLASH_INT_ERR_SMWR_MASK | FLASH_INT_ERR_ILLEGAL_MASK)) > 0) { + if (flashHandle->userCallBack.FlashCallBack != NULL) { + switch (flashHandle->state) { + case FLASH_STATE_PGM : /* If state is FLASH_STATE_PGM, call write error callback function. */ + flashHandle->userCallBack.FlashCallBack(flashHandle, FLASH_WRITE_EVENT_FAIL, flashHandle->destAddr); + break; + case FLASH_STATE_ERASE : /* If state is FLASH_STATE_ERASE, call erase error callback function. */ + flashHandle->userCallBack.FlashCallBack(flashHandle, FLASH_ERASE_EVENT_FAIL, flashHandle->destAddr); + break; + default: + break; + } + } + flashHandle->state = FLASH_STATE_READY; + } +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/gpio/common/inc/gpio.h b/vendor/xinlingyu_92_3061M/Project/drivers/gpio/common/inc/gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..21cb00f3e7f361032b7a1ad4aab4d122193747a4 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/gpio/common/inc/gpio.h @@ -0,0 +1,95 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file gpio.h + * @author MCU Driver Team + * @brief GPIO module driver + * @details The header file contains the following declaration: + * + GPIO handle structure definition. + * + Initialization functions. + * + GPIO Set And Get Functions. + * + Interrupt Service Functions. + */ + +#ifndef McuMagicTag_GPIO_H +#define McuMagicTag_GPIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "gpio_ip.h" + +/* Macro definition */ +/** + * @defgroup GPIO GPIO + * @brief GPIO module. + * @{ + */ + +/** + * @defgroup GPIO_Common GPIO Common + * @brief GPIO common external module. + * @{ + */ + +/** + * @defgroup GPIO_Handle_Definition GPIO Handle Definition + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ +typedef void (* GPIO_CallbackType)(void *param); + +typedef struct _GPIO_Handle { + GPIO_RegStruct *baseAddress; /**< GPIO Registers. */ + unsigned int pins; /**< Selected GPIO Pins. */ + GPIO_UserCallBcak userCallBack; /**< User-defined callback function. */ + GPIO_ExtendHandle handleEx; /**< Extend handle, configuring some special parameters. */ +} GPIO_Handle; + +/** + * @} + */ + +/** + * @defgroup GPIO_API_Declaration GPIO HAL API + * @{ + */ +void HAL_GPIO_Init(GPIO_Handle *handle); +void HAL_GPIO_DeInit(GPIO_Handle *handle); +void HAL_GPIO_SetDirection(GPIO_Handle *handle, unsigned int pins, GPIO_Direction dir); +void HAL_GPIO_SetValue(GPIO_Handle *handle, unsigned int pins, GPIO_Value value); +GPIO_InterruptMode HAL_GPIO_GetPinIrqType(GPIO_Handle *handle, GPIO_PIN pin); +GPIO_Value HAL_GPIO_GetPinValue(GPIO_Handle *handle, GPIO_PIN pin); +unsigned int HAL_GPIO_GetAllValue(GPIO_Handle *handle); +GPIO_Direction HAL_GPIO_GetPinDirection(GPIO_Handle *handle, GPIO_PIN pin); +unsigned int HAL_GPIO_GetAllDirection(GPIO_Handle *handle); +void HAL_GPIO_TogglePin(GPIO_Handle *handle, unsigned int pins); +BASE_StatusType HAL_GPIO_SetIrqType(GPIO_Handle *handle, unsigned int pins, GPIO_InterruptMode mode); +void HAL_GPIO_RegisterCallBack(GPIO_Handle *handle, GPIO_PIN pin, GPIO_CallbackType pCallback); +void HAL_GPIO_IrqHandler(void *handle); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_GPIO_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/gpio/inc/gpio_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/gpio/inc/gpio_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..ebf8d09eba2dd87e2f420ae95de21f18e9087d0e --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/gpio/inc/gpio_ip.h @@ -0,0 +1,678 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file gpio_ip.h + * @author MCU Driver Team + * @brief GPIO module driver + * @details The header file contains the following declaration: + * + GPIO configuration enums. + * + GPIO register structures. + * + GPIO DCL Functions. + * + Parameters check functions. + */ + +#ifndef McuMagicTag_GPIO_IP_H +#define McuMagicTag_GPIO_IP_H + +/* Includes ------------------------------------------------------------------*/ +#include "baseinc.h" +/* Macro definitions ---------------------------------------------------------*/ +#ifdef GPIO_PARAM_CHECK + #define GPIO_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM + #define GPIO_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET + #define GPIO_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else + #define GPIO_ASSERT_PARAM(para) ((void)0U) + #define GPIO_PARAM_CHECK_NO_RET(para) ((void)0U) + #define GPIO_PARAM_CHECK_WITH_RET(param, ret) ((void)0U) +#endif + +/** + * @addtogroup GPIO + * @{ + */ + +/** + * @defgroup GPIO_IP + * @{ + */ + +/* Macro definitions ---------------------------------------------------------*/ +#define GPIO_PIN_NUM (0x00000008U) +#define GPIO_PIN_MASK (0x000000FFU) + +/** + * @defgroup GPIO_Param_Def GPIO Parameters Definition + * @brief Description of GPIO configuration parameters. + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ +/** + * @brief GPIO PIN enum definition + */ +typedef enum { + GPIO_PIN_0 = 0x00000001U, + GPIO_PIN_1 = 0x00000002U, + GPIO_PIN_2 = 0x00000004U, + GPIO_PIN_3 = 0x00000008U, + GPIO_PIN_4 = 0x00000010U, + GPIO_PIN_5 = 0x00000020U, + GPIO_PIN_6 = 0x00000040U, + GPIO_PIN_7 = 0x00000080U, + GPIO_PIN_ALL = 0x000000FFU +} GPIO_PIN; + +/** + * @brief GPIO PIN value enum definition. + */ +typedef enum { + GPIO_LOW_LEVEL = 0x00000000U, + GPIO_HIGH_LEVEL = 0x00000001U +} GPIO_Value; + +/** + * @brief GPIO direction mode enum definition. + * @details status flag: + * + GPIO_INPUT_MODE -- GPIO pin as input, + * maximum input voltage of 3.63V for all types of I/O except 5V I/O, + * maximum input voltage of 5.0V for 5V I/O type. + * + GPIO_OUTPUT_MODE -- GPIO pin as output, + */ +typedef enum { + GPIO_INPUT_MODE = 0x00000000U, + GPIO_OUTPUT_MODE = 0x00000001U +} GPIO_Direction; + +/** + * @brief GPIO interrupt mode enum definition. + */ +typedef enum { + GPIO_INT_TYPE_FALL_EDGE = 0x00000000U, + GPIO_INT_TYPE_RISE_EDGE = 0x00000001U, + GPIO_INT_TYPE_LOW_LEVEL = 0x00000002U, + GPIO_INT_TYPE_HIGH_LEVEL = 0x00000003U, + GPIO_INT_TYPE_BOTH_EDGE = 0x00000004U, + GPIO_INT_TYPE_NONE = 0x00000005U +} GPIO_InterruptMode; + +/** + * @brief GPIO extend handle, configuring some special parameters. + */ +typedef struct { +} GPIO_ExtendHandle; + +/** + * @brief User-defined callback function. + */ +typedef struct { + /* GPIO pin callback functions */ + struct { + GPIO_PIN pin; + void (*callbackFunc)(void* handle); + } GPIO_CallbackFuncs[GPIO_PIN_NUM]; +} GPIO_UserCallBcak; + +/** + * @} + */ + +/** + * @defgroup GPIO_Reg_Def GPIO Register Definition + * @brief Description GPIO register mapping structure. + * @{ + */ + +/** + * @brief GPIO data registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pin0 : 1; /**< pin0 0:Input Data, 1:OutPut Data. */ + unsigned int pin1 : 1; /**< pin1 0:Input Data, 1:OutPut Data. */ + unsigned int pin2 : 1; /**< pin2 0:Input Data, 1:OutPut Data. */ + unsigned int pin3 : 1; /**< pin3 0:Input Data, 1:OutPut Data. */ + unsigned int pin4 : 1; /**< pin4 0:Input Data, 1:OutPut Data. */ + unsigned int pin5 : 1; /**< pin5 0:Input Data, 1:OutPut Data. */ + unsigned int pin6 : 1; /**< pin6 0:Input Data, 1:OutPut Data. */ + unsigned int pin7 : 1; /**< pin7 0:Input Data, 1:OutPut Data. */ + unsigned int reserved0 : 24; + } BIT; +} volatile GPIO_DATA_REG[256]; + +/** + * @brief GPIO direction registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pin0 : 1; /**< pin0 0:Input Direction, 1:OutPut Direction. */ + unsigned int pin1 : 1; /**< pin1 0:Input Direction, 1:OutPut Direction. */ + unsigned int pin2 : 1; /**< pin2 0:Input Direction, 1:OutPut Direction. */ + unsigned int pin3 : 1; /**< pin3 0:Input Direction, 1:OutPut Direction. */ + unsigned int pin4 : 1; /**< pin4 0:Input Direction, 1:OutPut Direction. */ + unsigned int pin5 : 1; /**< pin5 0:Input Direction, 1:OutPut Direction. */ + unsigned int pin6 : 1; /**< pin6 0:Input Direction, 1:OutPut Direction. */ + unsigned int pin7 : 1; /**< pin7 0:Input Direction, 1:OutPut Direction. */ + unsigned int reserved0 : 24; + } BIT; +} volatile GPIO_DIR_REG; + +/** + * @brief GPIO interrupt type registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pin0 : 1; /**< pin0 0:edge interrupt, 1:level interrupt. */ + unsigned int pin1 : 1; /**< pin1 0:edge interrupt, 1:level interrupt. */ + unsigned int pin2 : 1; /**< pin2 0:edge interrupt, 1:level interrupt. */ + unsigned int pin3 : 1; /**< pin3 0:edge interrupt, 1:level interrupt. */ + unsigned int pin4 : 1; /**< pin4 0:edge interrupt, 1:level interrupt. */ + unsigned int pin5 : 1; /**< pin5 0:edge interrupt, 1:level interrupt. */ + unsigned int pin6 : 1; /**< pin6 0:edge interrupt, 1:level interrupt. */ + unsigned int pin7 : 1; /**< pin7 0:edge interrupt, 1:level interrupt. */ + unsigned int reserved0 : 24; + } BIT; +} volatile GPIO_IS_REG; + +/** + * @brief GPIO edge type registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pin0 : 1; /**< pin0 0:rising or falling edge, 1: both edge. */ + unsigned int pin1 : 1; /**< pin1 0:rising or falling edge, 1: both edge. */ + unsigned int pin2 : 1; /**< pin2 0:rising or falling edge, 1: both edge. */ + unsigned int pin3 : 1; /**< pin3 0:rising or falling edge, 1: both edge. */ + unsigned int pin4 : 1; /**< pin4 0:rising or falling edge, 1: both edge. */ + unsigned int pin5 : 1; /**< pin5 0:rising or falling edge, 1: both edge. */ + unsigned int pin6 : 1; /**< pin6 0:rising or falling edge, 1: both edge. */ + unsigned int pin7 : 1; /**< pin7 0:rising or falling edge, 1: both edge. */ + unsigned int reserved0 : 24; + } BIT; +} volatile GPIO_IBE_REG; + +/** + * @brief GPIO interrupt condition registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pin0 : 1; /**< pin0 0:falling edge / low level, 1:rising edge / high level. */ + unsigned int pin1 : 1; /**< pin1 0:falling edge / low level, 1:rising edge / high level. */ + unsigned int pin2 : 1; /**< pin2 0:falling edge / low level, 1:rising edge / high level. */ + unsigned int pin3 : 1; /**< pin3 0:falling edge / low level, 1:rising edge / high level. */ + unsigned int pin4 : 1; /**< pin4 0:falling edge / low level, 1:rising edge / high level. */ + unsigned int pin5 : 1; /**< pin5 0:falling edge / low level, 1:rising edge / high level. */ + unsigned int pin6 : 1; /**< pin6 0:falling edge / low level, 1:rising edge / high level. */ + unsigned int pin7 : 1; /**< pin7 0:falling edge / low level, 1:rising edge / high level. */ + unsigned int reserved0 : 24; + } BIT; +} volatile GPIO_IEV_REG; + +/** + * @brief GPIO interrupt enable registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pin0 : 1; /**< pin0 0:mask interrupt, 1:unmask interrupt. */ + unsigned int pin1 : 1; /**< pin1 0:mask interrupt, 1:unmask interrupt. */ + unsigned int pin2 : 1; /**< pin2 0:mask interrupt, 1:unmask interrupt. */ + unsigned int pin3 : 1; /**< pin3 0:mask interrupt, 1:unmask interrupt. */ + unsigned int pin4 : 1; /**< pin4 0:mask interrupt, 1:unmask interrupt. */ + unsigned int pin5 : 1; /**< pin5 0:mask interrupt, 1:unmask interrupt. */ + unsigned int pin6 : 1; /**< pin6 0:mask interrupt, 1:unmask interrupt. */ + unsigned int pin7 : 1; /**< pin7 0:mask interrupt, 1:unmask interrupt. */ + unsigned int reserved0 : 24; + } BIT; +} volatile GPIO_IE_REG; + +/** + * @brief GPIO original interrupt signal registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pin0 : 1; /**< pin0 0:no interrupt, 1:has interrupt. */ + unsigned int pin1 : 1; /**< pin1 0:no interrupt, 1:has interrupt. */ + unsigned int pin2 : 1; /**< pin2 0:no interrupt, 1:has interrupt. */ + unsigned int pin3 : 1; /**< pin3 0:no interrupt, 1:has interrupt. */ + unsigned int pin4 : 1; /**< pin4 0:no interrupt, 1:has interrupt. */ + unsigned int pin5 : 1; /**< pin5 0:no interrupt, 1:has interrupt. */ + unsigned int pin6 : 1;; /**< pin6 0:no interrupt, 1:has interrupt. */ + unsigned int pin7 : 1; /**< pin7 0:no interrupt, 1:has interrupt. */ + unsigned int reserved0 : 24; + } BIT; +} volatile GPIO_RIS_REG; + +/** + * @brief GPIO mask interrupt signal registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pin0 : 1; /**< pin0 0:no interrupt, 1:has interrupt. */ + unsigned int pin1 : 1; /**< pin1 0:no interrupt, 1:has interrupt. */ + unsigned int pin2 : 1; /**< pin2 0:no interrupt, 1:has interrupt. */ + unsigned int pin3 : 1; /**< pin3 0:no interrupt, 1:has interrupt. */ + unsigned int pin4 : 1; /**< pin4 0:no interrupt, 1:has interrupt. */ + unsigned int pin5 : 1; /**< pin5 0:no interrupt, 1:has interrupt. */ + unsigned int pin6 : 1; /**< pin6 0:no interrupt, 1:has interrupt. */ + unsigned int pin7 : 1; /**< pin7 0:no interrupt, 1:has interrupt. */ + unsigned int reserved0 : 24; + } BIT; +} volatile GPIO_MIS_REG; + +/** + * @brief GPIO interrupt clear registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pin0 : 1; /**< pin0 0:no effect, 1:clear interrupt. */ + unsigned int pin1 : 1; /**< pin1 0:no effect, 1:clear interrupt. */ + unsigned int pin2 : 1; /**< pin2 0:no effect, 1:clear interrupt. */ + unsigned int pin3 : 1; /**< pin3 0:no effect, 1:clear interrupt. */ + unsigned int pin4 : 1; /**< pin4 0:no effect, 1:clear interrupt. */ + unsigned int pin5 : 1; /**< pin5 0:no effect, 1:clear interrupt. */ + unsigned int pin6 : 1; /**< pin6 0:no effect, 1:clear interrupt. */ + unsigned int pin7 : 1; /**< pin7 0:no effect, 1:clear interrupt. */ + unsigned int reserved0 : 24; + } BIT; +} volatile GPIO_IC_REG; + +/** + * @brief GPIO assemble registers structure definition + */ +typedef struct { + GPIO_DATA_REG GPIO_DATA; /**< gpio data register. Offset Address: 0x000～0x3FC.*/ + GPIO_DIR_REG GPIO_DIR; /**< gpio direction register. Offset Address: 0x400. */ + GPIO_IS_REG GPIO_IS; /**< gpio interrupt type register. Offset Address: 0x404. */ + GPIO_IBE_REG GPIO_IBE; /**< gpio edge type register. Offset Address: 0x408. */ + GPIO_IEV_REG GPIO_IEV; /**< gpio interrupt condition register. Offset Address: 0x40C. */ + GPIO_IE_REG GPIO_IE; /**< gpio interrupt enable register. Offset Address: 0x410. */ + GPIO_RIS_REG GPIO_RIS; /**< gpio original interrupt register. Offset Address: 0x414. */ + GPIO_MIS_REG GPIO_MIS; /**< gpio mask interrupt register. Offset Address: 0x418. */ + GPIO_IC_REG GPIO_IC; /**< gpio interrupt clear register. Offset Address: 0x41C. */ +} volatile GPIO_RegStruct; +/** + * @} + */ + +/** + * @brief Struct of map GPIO register and lock type. + */ +typedef struct { + GPIO_RegStruct *gpioGroup; + CHIP_LockType lockType; +} GPIO_MatchLockType; + +/** + * @brief Check gpio value parameter. + * @param value Value of @ref GPIO_Value + * @retval Bool. + */ +static inline bool IsGpioValue(GPIO_Value value) +{ + return (value == GPIO_LOW_LEVEL || value == GPIO_HIGH_LEVEL); +} + +/** + * @brief Check gpio direction parameter. + * @param dir Value of @ref GPIO_Direction. + * @retval Bool. + */ +static inline bool IsGpioDirection(GPIO_Direction dir) +{ + return (dir == GPIO_INPUT_MODE || dir == GPIO_OUTPUT_MODE); +} + +/** + * @brief Check gpio pins parameter. + * @param pins OR logical combination of pin. + * @retval Bool. + */ +static inline bool IsGpioPins(unsigned int pins) +{ + return ((pins & GPIO_PIN_MASK) != BASE_CFG_UNSET) && ((pins & ~GPIO_PIN_MASK) == BASE_CFG_UNSET); +} + +/** + * @brief Check gpio pin parameter. + * @param pin Value of @ref GPIO_PIN. + * @retval Bool. + */ +static inline bool IsGpioPin(GPIO_PIN pin) +{ + /* Check whether gpio pin */ + return (pin == GPIO_PIN_0 || pin == GPIO_PIN_1 || \ + pin == GPIO_PIN_2 || pin == GPIO_PIN_3 || \ + pin == GPIO_PIN_4 || pin == GPIO_PIN_5 || \ + pin == GPIO_PIN_6 || pin == GPIO_PIN_7 || \ + pin == GPIO_PIN_ALL); +} + +/** + * @brief Check gpio interrupt mode parameter. + * @param mode Value of @ref GPIO_InterruptMode. + * @retval Bool. + */ +static inline bool IsGpioITMode(GPIO_InterruptMode mode) +{ + /* Check whether gpio interrupt mode */ + return (mode == GPIO_INT_TYPE_HIGH_LEVEL || \ + mode == GPIO_INT_TYPE_LOW_LEVEL || \ + mode == GPIO_INT_TYPE_RISE_EDGE || \ + mode == GPIO_INT_TYPE_FALL_EDGE || \ + mode == GPIO_INT_TYPE_BOTH_EDGE || \ + mode == GPIO_INT_TYPE_NONE); +} + +/** + * @brief Setting GPIO pin level + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @param value Value of @ref GPIO_Value. + * @retval None. + */ +static inline void DCL_GPIO_SetValue(GPIO_RegStruct *gpiox, unsigned int pins, GPIO_Value value) +{ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + GPIO_PARAM_CHECK_NO_RET(IsGpioValue(value)); + gpiox->GPIO_DATA[pins].reg = (value == GPIO_HIGH_LEVEL ? pins : BASE_CFG_UNSET); /* Set GPIO pin level */ +} + +/** + * @brief Getting all GPIO level. + * @param gpiox Value of @ref GPIO_RegStruct. + * @retval unsigned int All GPIO pin level. + */ +static inline unsigned int DCL_GPIO_GetAllValue(const GPIO_RegStruct *gpiox) +{ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + return gpiox->GPIO_DATA[GPIO_PIN_MASK].reg & GPIO_PIN_MASK; /* Get all GPIO level. */ +} + +/** + * @brief Getting pin GPIO level. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pin OR logical combination of pin. + * @retval unsigned int GPIO pin level. + */ +static inline GPIO_Value DCL_GPIO_GetPinValue(const GPIO_RegStruct *gpiox, GPIO_PIN pin) +{ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_ASSERT_PARAM(IsGpioPin(pin)); + /* Get pin GPIO level. */ + return (gpiox->GPIO_DATA[GPIO_PIN_MASK].reg & pin) == BASE_CFG_UNSET ? GPIO_LOW_LEVEL : GPIO_HIGH_LEVEL; +} + +/** + * @brief Setting GPIO pin direction. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @param dir Value of @ref GPIO_Direction. + * @retval None. + */ +static inline void DCL_GPIO_SetDirection(GPIO_RegStruct *gpiox, unsigned int pins, GPIO_Direction dir) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + GPIO_PARAM_CHECK_NO_RET(IsGpioDirection(dir)); + if (dir == GPIO_INPUT_MODE) { /* Set GPIO pin direction */ + gpiox->GPIO_DIR.reg &= ~pins; + } else if (dir == GPIO_OUTPUT_MODE) { + gpiox->GPIO_DIR.reg |= pins; + } +} + +/** + * @brief Getting GPIO pin direction. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pin OR logical combination of pin. + * @retval GPIO direction, 0:input mode, 1:output mode. + */ +static inline GPIO_Direction DCL_GPIO_GetPinDirection(const GPIO_RegStruct *gpiox, GPIO_PIN pin) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_ASSERT_PARAM(IsGpioPin(pin)); + return (gpiox->GPIO_DIR.reg & pin) == BASE_CFG_UNSET ? GPIO_INPUT_MODE : GPIO_OUTPUT_MODE; +} + +/** + * @brief Getting GPIO all pin direction. + * @param gpiox Value of @ref GPIO_RegStruct. + * @retval unsigned int All GPIO pin direction. + */ +static inline unsigned int DCL_GPIO_GetAllPinDirection(const GPIO_RegStruct *gpiox) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + return gpiox->GPIO_DIR.reg & GPIO_PIN_MASK; +} + +/** + * @brief Setting GPIO pins edge trigger. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @retval None. + */ +static inline void DCL_GPIO_SetPinsEdgeTrigger(GPIO_RegStruct *gpiox, unsigned int pins) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + gpiox->GPIO_IS.reg &= ~pins; +} + +/** + * @brief Setting GPIO pins level trigger. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @retval None. + */ +static inline void DCL_GPIO_SetPinsLevelTrigger(GPIO_RegStruct *gpiox, unsigned int pins) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + gpiox->GPIO_IS.reg |= pins; +} + +/** + * @brief Getting GPIO pin trigger type. + * @param gpiox Value of @ref GPIO_RegStruct. + * @retval trigger type, 0:edge trigger; 1:level trigger. + */ +static inline unsigned int DCL_GPIO_GetPinsTriggerType(const GPIO_RegStruct *gpiox) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + return (gpiox->GPIO_IS.reg & GPIO_PIN_MASK); +} + +/** + * @brief Setting GPIO pins single edge trigger. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @retval None. + */ +static inline void DCL_GPIO_SetPinsSingleEdgeTrigger(GPIO_RegStruct *gpiox, unsigned int pins) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + gpiox->GPIO_IBE.reg &= ~pins; +} + +/** + * @brief Setting GPIO pins both edge trigger. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @retval None. + */ +static inline void DCL_GPIO_SetPinsBothEdgeTrigger(GPIO_RegStruct *gpiox, unsigned int pins) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + gpiox->GPIO_IBE.reg |= pins; +} + +/** + * @brief Getting GPIO pin edge trigger type. + * @param gpiox Value of @ref GPIO_RegStruct. + * @retval edge trigger type, pin value is 0:signle edge trigger; 1:both edge trigger. + */ +static inline unsigned int DCL_GPIO_GetPinsEdgeTriggerType(const GPIO_RegStruct *gpiox) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + return (gpiox->GPIO_IBE.reg & GPIO_PIN_MASK); +} + +/** + * @brief Setting GPIO pins falling edge or low level trigger. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @retval None. + */ +static inline void DCL_GPIO_SetPinsFallingEdgeOrLowLevelTrigger(GPIO_RegStruct *gpiox, unsigned int pins) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + gpiox->GPIO_IEV.reg &= ~pins; +} + +/** + * @brief Setting GPIO pins rising edge or high level trigger. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @retval None. + */ +static inline void DCL_GPIO_SetPinsRisingEdgeOrHighLevelTrigger(GPIO_RegStruct *gpiox, unsigned int pins) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + gpiox->GPIO_IEV.reg |= pins; +} + +/** + * @brief Getting GPIO pins trigger condition type. + * @param gpiox Value of @ref GPIO_RegStruct. + * @retval trigger condition type, pin value is 0:falling edge or low level trigger; + * @retval trigger condition type, pin value is 1:rising edge or high level trigger. + */ +static inline unsigned int DCL_GPIO_GetPinsTriggerConditionType(const GPIO_RegStruct *gpiox) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + return (gpiox->GPIO_IEV.reg & GPIO_PIN_MASK); +} + +/** + * @brief Clear all gpio interrupt signal. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @retval None. + */ +static inline void DCL_GPIO_ClearIrq(GPIO_RegStruct *gpiox, unsigned int pins) +{ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + gpiox->GPIO_IC.reg |= pins; +} + +/** + * @brief Enable gpio group interrupt. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pins. + * @retval None. + */ +static inline void DCL_GPIO_EnableIrq(GPIO_RegStruct *gpiox, unsigned int pins) +{ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + /* must clear interrupt first, prevents interrupts triggered by previous output mode. */ + DCL_GPIO_ClearIrq(gpiox, pins); + gpiox->GPIO_IE.reg |= pins; +} + +/** + * @brief Disable gpio interrupt. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @retval None. + */ +static inline void DCL_GPIO_DisableIrq(GPIO_RegStruct *gpiox, unsigned int pins) +{ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + gpiox->GPIO_IE.reg &= ~pins; +} + +/** + * @brief Getting all values of GPIO IE register. + * @param gpiox Value of @ref GPIO_RegStruct. + * @retval unsigned int All values of GPIO IE register. + */ +static inline unsigned int DCL_GPIO_GetIE(const GPIO_RegStruct *gpiox) +{ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + return gpiox->GPIO_IE.reg & GPIO_PIN_MASK; +} + +/** + * @brief Getting all values of GPIO RIS register. + * @param gpiox Value of @ref GPIO_RegStruct. + * @retval unsigned int All values of GPIO RIS register. + */ +static inline unsigned int DCL_GPIO_GetRIS(const GPIO_RegStruct *gpiox) +{ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + return gpiox->GPIO_RIS.reg & GPIO_PIN_MASK; +} + +/** + * @brief Getting all values of GPIO MIS register. + * @param gpiox Value of @ref GPIO_RegStruct. + * @retval unsigned int All values of GPIO MIS register. + */ +static inline unsigned int DCL_GPIO_GetMIS(const GPIO_RegStruct *gpiox) +{ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + return gpiox->GPIO_MIS.reg & GPIO_PIN_MASK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_GPIO_IP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/gpio/src/gpio.c b/vendor/xinlingyu_92_3061M/Project/drivers/gpio/src/gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..1a3e1a20f0bb25dd30740f969836ed0a25a7479f --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/gpio/src/gpio.c @@ -0,0 +1,330 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file gpio.c + * @author MCU Driver Team + * @brief GPIO module driver + * @details This file provides firmware functions to manage the following functionalities of the GPIO. + * + GPIO configuration definetion. + * + Initialization functions. + * + GPIO Set And Get Functions. + * + Interrupt Service Functions. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "gpio.h" + +static void GPIO_ExcuteCallBack(GPIO_Handle *handle, GPIO_PIN pin); +static void GPIO_SetLevelIrqType(GPIO_Handle *handle, unsigned int pins, GPIO_InterruptMode mode); +static void GPIO_SetEdgeIrqType(GPIO_Handle *handle, unsigned int pins, GPIO_InterruptMode mode); + +/** + * @brief Initializing GPIO register values. + * @param handle Value of @ref GPIO_Handle. + * @retval None. + */ +void HAL_GPIO_Init(GPIO_Handle *handle) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(handle->pins)); + + /* Register GPIO callback ID */ + for (unsigned int i = 0; i < GPIO_PIN_NUM; i++) { + handle->userCallBack.GPIO_CallbackFuncs[i].pin = (1 << i); + } +} + +/** + * @brief DeInitializing GPIO register values. + * @param handle Value of @ref GPIO_Handle. + * @retval None. + */ +void HAL_GPIO_DeInit(GPIO_Handle *handle) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + /* Clean GPIO callback ID and interrupt callback functions. */ + for (unsigned int i = 0; i < GPIO_PIN_NUM; i++) { + handle->userCallBack.GPIO_CallbackFuncs[i].pin = 0x00000000; + handle->userCallBack.GPIO_CallbackFuncs[i].callbackFunc = NULL; + } + handle->pins = 0x00000000; /* Reset GPIO pins. */ +} + +/** + * @brief Setting GPIO pins direction. + * @param handle Value of @ref GPIO_Handle. + * @param pins OR logical combination of pin. + * @param dir GPIO pin direction. + * @retval None. + */ +void HAL_GPIO_SetDirection(GPIO_Handle *handle, unsigned int pins, GPIO_Direction dir) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + GPIO_PARAM_CHECK_NO_RET(IsGpioDirection(dir)); + DCL_GPIO_SetDirection(handle->baseAddress, pins, dir); +} + +/** + * @brief Setting GPIO pins level + * @param handle Value of @ref GPIO_Handle. + * @param pins OR logical combination of pin. + * @param value Value of @ref GPIO_Value. + * @retval None. + */ +void HAL_GPIO_SetValue(GPIO_Handle *handle, unsigned int pins, GPIO_Value value) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + GPIO_PARAM_CHECK_NO_RET(IsGpioValue(value)); + DCL_GPIO_SetValue(handle->baseAddress, pins, value); +} + +/** + * @brief Getting GPIO pin level + * @param handle Value of @ref GPIO_Handle. + * @param pin Value of @ref GPIO_PIN. + * @retval GPIO_Value Value of @ref GPIO_Value. + */ +GPIO_Value HAL_GPIO_GetPinValue(GPIO_Handle *handle, GPIO_PIN pin) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_ASSERT_PARAM(IsGpioPin(pin)); + return (handle->baseAddress->GPIO_DATA[GPIO_PIN_MASK].reg & pin) == BASE_CFG_UNSET ? \ + GPIO_LOW_LEVEL : GPIO_HIGH_LEVEL; +} + +/** + * @brief Getting GPIO pins level + * @param handle Value of @ref GPIO_Handle. + * @retval unsigned int Value of all GPIO pin. + */ +unsigned int HAL_GPIO_GetAllValue(GPIO_Handle *handle) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + return handle->baseAddress->GPIO_DATA[GPIO_PIN_MASK].reg & GPIO_PIN_MASK; +} + +/** + * @brief Getting GPIO pin direction + * @param handle Value of @ref GPIO_Handle. + * @param pin GPIO pin. + * @retval Value of @ref BASE_StatusType. + */ +GPIO_Direction HAL_GPIO_GetPinDirection(GPIO_Handle *handle, GPIO_PIN pin) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_ASSERT_PARAM(IsGpioPin(pin)); + return (handle->baseAddress->GPIO_DIR.reg & pin) == BASE_CFG_UNSET ? GPIO_INPUT_MODE : GPIO_OUTPUT_MODE; +} + +/** + * @brief Getting GPIO pins direction + * @param handle Value of @ref GPIO_Handle. + * @retval Value of @ref BASE_StatusType. + */ +unsigned int HAL_GPIO_GetAllDirection(GPIO_Handle *handle) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + return handle->baseAddress->GPIO_DIR.reg & GPIO_PIN_MASK; +} + +/** + * @brief Toggle GPIO level + * @param handle Value of @ref GPIO_Handle. + * @param pins GPIO pins. + * @retval None. + */ +void HAL_GPIO_TogglePin(GPIO_Handle *handle, unsigned int pins) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + handle->baseAddress->GPIO_DATA[pins].reg ^= pins; +} + +/** + * @brief Get GPIO pin interrupt types. + * @param handle Value of @ref GPIO_Handle. + * @param pin Value of @ref GPIO_PIN. + * @retval GPIO_InterruptMode Value of @ref GPIO_InterruptMode. + */ +GPIO_InterruptMode HAL_GPIO_GetPinIrqType(GPIO_Handle *handle, GPIO_PIN pin) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_ASSERT_PARAM(IsGpioPin(pin)); + /* If disable pin interrupt, return None mode */ + if ((handle->baseAddress->GPIO_IE.reg & pin) == BASE_CFG_UNSET) { + return GPIO_INT_TYPE_NONE; + } + unsigned int iev = ((handle->baseAddress->GPIO_IEV.reg & pin) != 0) ? 1 : 0; /* 1: iev effect. */ + unsigned int is = ((handle->baseAddress->GPIO_IS.reg & pin) != 0) ? 2 : 0; /* 2: is effect. */ + unsigned int ibe = ((handle->baseAddress->GPIO_IBE.reg & pin) != 0) ? 4 : 0; /* 4: ibe effect. */ + unsigned int value = (iev | is | ibe); + if (value >= GPIO_INT_TYPE_NONE) { + return GPIO_INT_TYPE_NONE; + } + return value; +} + +/** + * @brief Set GPIO level interrupt types. + * @param handle Value of @ref GPIO_Handle. + * @param pins OR logical combination of pin. + * @param mode Value of @ref GPIO_InterruptMode. + * @retval None. + */ +static void GPIO_SetLevelIrqType(GPIO_Handle *handle, unsigned int pins, GPIO_InterruptMode mode) +{ + handle->baseAddress->GPIO_IBE.reg &= ~pins; /* Disable edge detection */ + handle->baseAddress->GPIO_IS.reg |= pins; /* Enable level detection */ + if (mode == GPIO_INT_TYPE_HIGH_LEVEL) { + handle->baseAddress->GPIO_IEV.reg |= pins; + } else { + handle->baseAddress->GPIO_IEV.reg &= ~pins; + } +} + +/** + * @brief Set GPIO edge interrupt types. + * @param handle Value of @ref GPIO_Handle. + * @param pins OR logical combination of pin. + * @param mode Value of @ref GPIO_InterruptMode. + * @retval None. + */ +static void GPIO_SetEdgeIrqType(GPIO_Handle *handle, unsigned int pins, GPIO_InterruptMode mode) +{ + handle->baseAddress->GPIO_IS.reg &= ~pins; /* Disable level detection. */ + handle->baseAddress->GPIO_IBE.reg &= ~pins; /* Clear detection on both edges. */ + if (mode == GPIO_INT_TYPE_RISE_EDGE) { + handle->baseAddress->GPIO_IEV.reg |= pins; + } else { + handle->baseAddress->GPIO_IEV.reg &= ~pins; + } +} + +/** + * @brief Setting GPIO interrupt mode. + * @param handle Value of @ref GPIO_Handle. + * @param pins OR logical combination of pin. + * @param mode Value of @ref GPIO_InterruptMode. + * @retval Value of @ref BASE_StatusType. + */ +BASE_StatusType HAL_GPIO_SetIrqType(GPIO_Handle *handle, unsigned int pins, GPIO_InterruptMode mode) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_PARAM_CHECK_WITH_RET(IsGpioPins(pins), BASE_STATUS_ERROR); + GPIO_PARAM_CHECK_WITH_RET(IsGpioITMode(mode), BASE_STATUS_ERROR); + + /* It must be disabled to avoid triggering interrupts during configuration. */ + DCL_GPIO_DisableIrq(handle->baseAddress, pins); + + if ((mode == GPIO_INT_TYPE_HIGH_LEVEL) || (mode == GPIO_INT_TYPE_LOW_LEVEL)) { + GPIO_SetLevelIrqType(handle, pins, mode); + } else if (mode == GPIO_INT_TYPE_BOTH_EDGE) { + handle->baseAddress->GPIO_IEV.reg &= ~pins; + handle->baseAddress->GPIO_IS.reg &= ~pins; + handle->baseAddress->GPIO_IBE.reg |= pins; + } else if ((mode == GPIO_INT_TYPE_RISE_EDGE) || (mode == GPIO_INT_TYPE_FALL_EDGE)) { + GPIO_SetEdgeIrqType(handle, pins, mode); + } else if (mode == GPIO_INT_TYPE_NONE) { + /* No interruptMode: disable everything. */ + handle->baseAddress->GPIO_IEV.reg &= ~pins; + handle->baseAddress->GPIO_IS.reg &= ~pins; + handle->baseAddress->GPIO_IBE.reg &= ~pins; + return BASE_STATUS_ERROR; + } + + DCL_GPIO_EnableIrq(handle->baseAddress, pins); + return BASE_STATUS_OK; +} + +/** + * @brief Handle GPIO interrupt request. + * @param handle Value of @ref GPIO_Handle. + * @param pin Value of @ref GPIO_PIN. + * @retval None. + */ +static void GPIO_ExcuteCallBack(GPIO_Handle *handle, GPIO_PIN pin) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pin)); + for (unsigned int i = 0; i < GPIO_PIN_NUM; i++) { + if (handle->userCallBack.GPIO_CallbackFuncs[i].pin == pin) { + if (handle->userCallBack.GPIO_CallbackFuncs[i].callbackFunc != NULL) { + handle->userCallBack.GPIO_CallbackFuncs[i].callbackFunc(handle); + } + } + } +} + +/** + * @brief Handle GPIO interrupt request. + * @param handle Interrupt parameter. + * @retval None. + */ +void HAL_GPIO_IrqHandler(void *handle) +{ + GPIO_Handle *gpioHandle = (GPIO_Handle *)handle; + GPIO_ASSERT_PARAM(gpioHandle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(gpioHandle->baseAddress)); + unsigned int position = 0x00000000U; + unsigned int pinCurrent = 0x00000000U; + unsigned int mis = DCL_GPIO_GetMIS(gpioHandle->baseAddress); /* Queries the masked GPIO interrupt status. */ + + /* Determine which pin sets the callback function. */ + while ((mis >> position) != BASE_CFG_UNSET) { + pinCurrent = mis & (1 << position); + if (pinCurrent) { + gpioHandle->pins = pinCurrent; + DCL_GPIO_ClearIrq(gpioHandle->baseAddress, pinCurrent); + GPIO_ExcuteCallBack(gpioHandle, pinCurrent); + } + position++; + } +} + +/** + * @brief Handle GPIO interrupt request. + * @param handle Value of @ref GPIO_Handle. + * @param pin Value of @ref GPIO_PIN. + * @param pCallback Value of @ref GPIO_CallbackType. + * @retval None. + */ +void HAL_GPIO_RegisterCallBack(GPIO_Handle *handle, GPIO_PIN pin, GPIO_CallbackType pCallback) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPin(pin)); + for (unsigned int i = 0; i < GPIO_PIN_NUM; i++) { + if (handle->userCallBack.GPIO_CallbackFuncs[i].pin == pin) { + handle->userCallBack.GPIO_CallbackFuncs[i].callbackFunc = pCallback; + } + } +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/gpt/common/inc/gpt.h b/vendor/xinlingyu_92_3061M/Project/drivers/gpt/common/inc/gpt.h new file mode 100644 index 0000000000000000000000000000000000000000..bebbc326c512a0ee6a199246a88d2274f87a2d8f --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/gpt/common/inc/gpt.h @@ -0,0 +1,134 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file gpt.c + * @author MCU Driver Team + * @brief GPT module driver. + * @details This file provides firmware GPT Handle Structure and functions + * prototypes to manage the following functionalities of the GPT. + * + Initialization and de-initialization functions + * + config the register of GPT + * + interrupt register and register functions + */ + +#ifndef McuMagicTag_GPT_H +#define McuMagicTag_GPT_H + +/* Includes-------------------------------------------------------------------*/ +#include "gpt_ip.h" + +/** + * @defgroup GPT GPT + * @brief GPT module. + * @{ + */ + +/** + * @defgroup GPT_Common GPT Common + * @brief GPT common external module. + * @{ + */ + +/** + * @defgroup GPT_Handle_Definition GPT Handle Definition + * @{ + */ +typedef struct { + GPT_RegStruct *baseAddress; /**< Base address of GPT register. */ + GPT_CountMode cntMode; /**< GPT count mode. */ + unsigned int clockDiv; /**< GPT clock div. */ + volatile GPT_RefValueAction refA0; /**< GPT refA0 action setting. */ + volatile GPT_RefValueAction refB0; /**< GPT refB0 action setting. */ + volatile unsigned int period; /**< PWM period. */ + volatile unsigned int pwmNum; /**< PWM number, only valid when pwmKeep is false. */ + bool pwmKeep; /**< PWM output mode. */ + bool bufLoad; /**< Indicates whether the cache is loaded immediately. */ + bool triggleAdcPeriod; /**< triggle ADC when PWM counting period out finish. */ + bool triggleAdcOutFinish; /**< triggle ADC when PWM out finish. */ + + GPT_UserCallBack userCallBack; /**< User callback function of GPT. */ + GPT_ExtendHandle handleEx; /**< GPT extend handle. */ +} GPT_Handle; + +typedef void (* GPT_CallBackFunc)(void *handle); + +/** + * @} + */ + +/** + * @defgroup GPT_API_Declaration GPT HAL API + * @{ + */ +/** + * GPT Control functions + */ +BASE_StatusType HAL_GPT_Init(GPT_Handle *handle); + +void HAL_GPT_Start(GPT_Handle *handle); + +void HAL_GPT_Stop(GPT_Handle *handle); + +BASE_StatusType HAL_GPT_Config(GPT_Handle *handle); + +BASE_StatusType HAL_GPT_GetConfig(GPT_Handle *handle); + +/* Setting PWM reference points and corresponding actions */ +BASE_StatusType HAL_GPT_SetReferCounterAndAction(GPT_Handle *handle, const GPT_ReferCfg *refer); + +void HAL_GPT_GetReferCounterAndAction(GPT_Handle *handle, GPT_ReferCfg *refer); + +/* GPT frequency divider and period. */ +BASE_StatusType HAL_GPT_SetCountPeriod(GPT_Handle *handle, unsigned int period); + +unsigned int HAL_GPT_GetCountPeriod(GPT_Handle *handle); + +BASE_StatusType HAL_GPT_SetDivFactor(GPT_Handle *handle, unsigned int div); + +unsigned int HAL_GPT_GetDivFactor(GPT_Handle *handle); + +/* GPT cache loading settings and cache status. */ +BASE_StatusType HAL_GPT_SetBufferLoad(GPT_Handle *handle, GPT_SetOption bufferLoad); + +unsigned int HAL_GPT_GetBufferLoadStatus(GPT_Handle *handle); + +/* Output completion interrupt configuration for the GPT channel. */ +BASE_StatusType HAL_GPT_SetOutFinishInt(GPT_Handle *handle, GPT_SetOption outFinishInt); + +/* GPT period interrupt configuration. */ +BASE_StatusType HAL_GPT_SetPeriodInt(GPT_Handle *handle, GPT_SetOption periodInt); + +/* GPT interrupt service and callback registration functions */ +void HAL_GPT_IrqOutFinishHandler(void *handle); + +void HAL_GPT_IrqPeriodHandler(void *handle); + +BASE_StatusType HAL_GPT_RegisterCallBack(GPT_Handle *gptHandle, GPT_CallBackFunType typeID, + GPT_CallBackFunc pCallback); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_GPT_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/gpt/inc/gpt_ex.h b/vendor/xinlingyu_92_3061M/Project/drivers/gpt/inc/gpt_ex.h new file mode 100644 index 0000000000000000000000000000000000000000..0247b76d606c72b09d7c78bcd78bef8ca4255ebc --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/gpt/inc/gpt_ex.h @@ -0,0 +1,68 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file gpt_ex.h + * @author MCU Driver Team + * @brief GPT module driver. + * @details This file provides firmware functions to manage the extension + * functionalities of the GPT. + */ + +#ifndef McuMagicTag_GPT_EX_H +#define McuMagicTag_GPT_EX_H + +#include "gpt.h" + +/** + * @addtogroup GPT_IP + * @{ + */ + +/** + * @defgroup GPT_EX_API_Declaration GPT HAL API EX + * @{ + */ + +/* The current count value of the counter. */ +unsigned int HAL_GPT_GetCounterValueEx(GPT_Handle *handle); + +/* Period trigger for DMA and ADC. */ +BASE_StatusType HAL_GPT_TriggerDMAEnableEx(GPT_Handle *handle, GPT_TriggerDMAType triggerDMAType); + +BASE_StatusType HAL_GPT_TriggerDMADisableEx(GPT_Handle *handle, GPT_TriggerDMAType triggerDMAType); + +BASE_StatusType HAL_GPT_TriggerADCEnableEx(GPT_Handle *handle, GPT_TriggerADCType triggerADCType); + +BASE_StatusType HAL_GPT_TriggerADCDisableEx(GPT_Handle *handle, GPT_TriggerADCType triggerADCType); + +/* Current PWM Number, Only valid when PWM0_CFG.rg_pwm0_keep = 1 */ +unsigned int HAL_GPT_GetCurrentPWM0NumberEx(GPT_Handle *handle); + +/* Injected PWM output completion interrupt, which takes effect only when PWM waves are output. */ +BASE_StatusType HAL_GPT_SoftInjOutFinIntEx(GPT_Handle *handle, GPT_SetOption softInjOutFin); + +/* Injected PWM period finish interrupt, which takes effect only when PWM waves are output. */ +BASE_StatusType HAL_GPT_SoftInjPeriodFinIntEx(GPT_Handle *handle, GPT_SetOption softInjPeriod); + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_GPT_EX_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/gpt/inc/gpt_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/gpt/inc/gpt_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..cd963ee656d5d60e4787e885d976aa756d4308c8 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/gpt/inc/gpt_ip.h @@ -0,0 +1,950 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file gpt_ip.h + * @author MCU Driver Team + * @brief GPT module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the GPT. + * + Register Struct of GPT + * + GPT Register Map struct + * + Direct Configuration Layer functions of GPT + */ + +#ifndef McuMagicTag_GPT_IP_H +#define McuMagicTag_GPT_IP_H + +/* Includes-------------------------------------------------------------------*/ +#include "baseinc.h" + +/* Macro definitions ---------------------------------------------------------*/ +#ifdef GPT_PARAM_CHECK +#define GPT_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define GPT_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define GPT_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define GPT_ASSERT_PARAM(para) ((void)0U) +#define GPT_PARAM_CHECK_NO_RET(para) ((void)0U) +#define GPT_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +#define GPT_PWM_MAX_NUM 0x000003FFU +#define GPT_PWM_PERIOD_MIN_VALUE 0x00000002U +#define GPT_PWM_PERIOD_MAX_VALUE 0x0000FFFFUL +#define GPT_PWM_DIV_FACTOR_MAX_VALUE 0x00000FFFUL +#define GPT_TC_PRD_MAX_VALUE 0x0000FFFFUL +#define GPT_DIV_FACTOR_MAX_VALUE 0x00000FFFUL + +/** + * @addtogroup GPT + * @{ + */ +/** + * @defgroup GPT_IP GPT_IP + * @brief GPT_IP: gpt_v1. + * @{ + */ + +/** + * @defgroup GPT_Param_Def GPT Parameters Definition + * @brief Description of GPT configuration parameters. + * @{ + */ + +/** + * @brief GPT common enable setting. + */ +typedef enum { + GPT_SET_DISABLE = 0x00000000U, + GPT_SET_ENABLE = 0x00000001U, +} GPT_SetOption; + +/** + * @brief Trigger DMA request option. + * @details DMA request type: + * + GPT_PWM0_TRIGGER_DMA -- pwm output finish triggle + * + GPT_PERIOD_TRIGGER_DMA -- gpt period triggle + * + GPT_PWM0_PERIOD_TRIGGER_DMA -- pwm output finish and gpt period triggle + */ +typedef enum { + GPT_PWM0_TRIGGER_DMA = 0x00000001U, + GPT_PERIOD_TRIGGER_DMA = 0x00000002U, + GPT_PWM0_PERIOD_TRIGGER_DMA = 0x00000003U, +} GPT_TriggerDMAType; + +/** + * @brief Trigger ADC request option. + * @details ADC request type: + * + GPT_PWM0_TRIGGER_ADC -- pwm output finish triggle + * + GPT_PERIOD_TRIGGER_ADC -- gpt period triggle + * + GPT_PWM0_PERIOD_TRIGGER_ADC -- pwm output finish and gpt period triggle + */ +typedef enum { + GPT_PWM0_TRIGGER_ADC = 0x00000001U, + GPT_PERIOD_TRIGGER_ADC = 0x00000002U, + GPT_PWM0_PERIOD_TRIGGER_ADC = 0x00000003U, +} GPT_TriggerADCType; + +/** + * @brief GPT cache loading status. + * @details Loading status: + * + GPT_PERIOD_LOAD_STATUS -- Status of the count period register buffer. + * + GPT_REFERA0_LOAD_STATUS -- Status of the counter reference value A0 register buffer + * + GPT_REFERB0_LOAD_STATUS -- Status of the counter reference value B0 register buffer + * + GPT_ACT0_LOAD_STATUS -- Status of the channel action configuration register buffer + * + GPT_PWM0_CFG_LOAD_STATUS -- Status of the configuration register buffer for channel. + */ +typedef enum { + GPT_PERIOD_LOAD_STATUS = 0x00000001U, + GPT_REFERA0_LOAD_STATUS = 0x00000002U, + GPT_REFERB0_LOAD_STATUS = 0x00000004U, + GPT_ACT0_LOAD_STATUS = 0x00000100U, + GPT_PWM0_CFG_LOAD_STATUS = 0x00001000U, +} GPT_LoadStatus; + +/** + * @brief GPT count mode. + */ +typedef enum { + GPT_COUNT_UP = 0x00000000U, + GPT_COUNT_DOWN = 0x00000001U +} GPT_CountMode; + +/** + * @brief PWM output action for referent dot. + * @details Output action: + * + GPT_ACTION_NO_ACTION -- Prohibit action. + * + GPT_ACTION_OUTPUT_LOW -- Low level. + * + GPT_ACTION_OUTPUT_HIGH -- High level. + * + GPT_ACTION_OUTPUT_FLIP -- Flip the level. + */ +typedef enum { + GPT_ACTION_NO_ACTION = 0x00000000U, + GPT_ACTION_OUTPUT_LOW = 0x00000001U, + GPT_ACTION_OUTPUT_HIGH = 0x00000002U, + GPT_ACTION_OUTPUT_FLIP = 0x00000003U +} GPT_ActionType; + +/** + * @brief GPT PWM output reference dot and action. + */ +typedef struct { + unsigned int refdot; + GPT_ActionType refAction; +}GPT_RefValueAction; + +/** + * @brief GPT reference dot and action config. + */ +typedef struct { + GPT_RefValueAction refA0; + GPT_RefValueAction refB0; +} GPT_ReferCfg; + +/** + * @brief GPT user interrupt callback function type. + * @details Function type: + * + GPT_INT_PWM_OUTPUT_FIN -- PWM output finish. + * + GPT_INT_PERIOD -- PWM period output finish. + */ +typedef enum { + GPT_INT_PWM_OUTPUT_FIN = 0x00000001, + GPT_INT_PERIOD = 0x00000002 +}GPT_CallBackFunType; + +/** + * @brief GPT user interrupt callback function. + */ +typedef struct { + void (* PWMOutPutFin)(void *handle); /**< GPT PWM channel out finish callback function for users */ + void (* PWMPeriod)(void *handle); /**< GPT PWM period output finish callback function for users */ +} GPT_UserCallBack; + +/** + * @brief GPT extend configure + */ +typedef struct { + bool periodIntEnable; /**< PWM period output finish interrupt. */ + bool outputFinIntEnable; /**< PWM channel output finish interrupt. */ +} GPT_ExtendHandle; + +/** + * @} + */ + +/** + * @defgroup GPT_Reg_Def GPT Register Definition + * @brief register mapping structure + * @{ + */ + +/** + * @brief GPT Version structure + */ +typedef union { + unsigned int reg; + struct { + unsigned int sub_version : 4; /**< Subversion number. */ + unsigned int main_version : 4; /**< Major version number. */ + unsigned int reserved : 24; + } BIT; +} volatile GPT_VER_INFO_REG; + +/** + * @brief Frequency division coefficient register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rg_div_fac : 12; /**< Frequency division coefficient. + Frequency divider = Frequency division coefficient + 1. */ + unsigned int reserved : 20; + } BIT; +} volatile GPT_TC_DIV_REG; + +/** + * @brief Count period register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rg_cnt_prd : 16; /**< Counting period of the counter. */ + unsigned int reserved : 16; + } BIT; +} volatile GPT_TC_PRD_REG; + +/** + * @brief Count reference value A0 register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rg_cnt_refa0 : 16; /**< Count reference value A0, Less than or equal to count period. */ + unsigned int reserved : 16; + } BIT; +} volatile GPT_TC_REFA0_REG; + +/** + * @brief Count reference value B0 register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rg_cnt_refb0 : 16; /**< Count reference value B0, Less than or equal to count period. */ + unsigned int reserved : 16; + } BIT; +} volatile GPT_TC_REFB0_REG; + +/** + * @brief Count status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ro_cnt_val : 16; /**< Current count value of the counterr. */ + unsigned int ro_div_cnt : 12; /**< Current count value of the divide. */ + unsigned int reserved : 4; + } BIT; +} volatile GPT_TC_STS_REG; + +/** + * @brief Channel action configuration register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rg_pg_act0_refa0 : 2; /**< When counter is equal to the reference value A0, + PWM output of Channel acts. */ + unsigned int reserved : 2; + unsigned int rg_pg_act0_refb0 : 2; /**< When counter is equal to the reference value A0, + PWM output of Channel acts. */ + unsigned int reserved1 : 26; + } BIT; +} volatile GPT_PG_ACT0_REG; + +/** + * @brief Interrupt enable register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rg_prd_int_en : 1; /**< PWM period output finish interrupt enable. */ + unsigned int reserved : 3; + unsigned int rg_pwm0_int_en : 1; /**< PWM output finish interrupt enable. */ + unsigned int reserved1 : 27; + } BIT; +} volatile GPT_INT_EN_REG; + +/** + * @brief Interrupt flag register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ro_prd_int_flag : 1; /**< Interrupt flag of periodic interrupt. */ + unsigned int reserved : 3; + unsigned int ro_pwm0_int_flag : 1; /**< Interrupt flag of output completion interrupt of channel. */ + unsigned int reserved1 : 11; + unsigned int rg_prd_int_clr : 1; /**< Periodic interrupt clear. Writing 1 clears the bit. */ + unsigned int reserved2 : 3; + unsigned int rg_pwm0_int_clr : 1; /**< Channel output finish interrupt clear. Writing 1 clears the bit. */ + unsigned int reserved3 : 11; + } BIT; +} volatile GPT_INT_FLAG_REG; + +/** + * @brief Interrupt injection register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rg_prd_int_inj : 1; /**< Software injection period finish interrupt. Writing 1 clears */ + unsigned int reserved : 3; + unsigned int rg_pwm0_int_inj : 1; /**< Software injection output finish interrupt. Writing 1 clears */ + unsigned int reserved1 : 27; + } BIT; +} volatile GPT_INT_INJ_REG; + +/** + * @brief SOC/DMA request enable register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rg_soc_prd_en : 1; /**< Enable for generating the ADC signal at end of counting period. */ + unsigned int rg_soc_pwm0_en : 1; /**< Enable for channel output completion to generate ADC signal. */ + unsigned int reserved : 2; + unsigned int rg_dsr_prd_en : 1; /**< DMA single request signal at end of the counting period. */ + unsigned int rg_dsr_pwm0_en : 1; /**< DMA single request signal after the output of channel is complete. */ + unsigned int reserved1 : 2; + unsigned int rg_dbr_prd_en : 1; /**< DMA burst request signal at end of the counting period. */ + unsigned int rg_dbr_pwm0_en : 1; /**< DMA burst request signal after output of channel is complete. */ + unsigned int reserved2 : 22; + } BIT; +} volatile GPT_SOCDR_EN_REG; + +/** + * @brief Channel configuration register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rg_pwm0_num : 10; /**< Number of PWM output by channel. */ + unsigned int reserved : 21; + unsigned int rg_pwm0_keep : 1; /**< PWM output mode of channel. */ + } BIT; +} volatile GPT_PWM0_CFG_REG; + +/** + * @brief GPT enable register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rg_gpt_en : 1; /**< GPT enable control. 0: The GPT channel is disabled. + 1: The GPT channel is enabled. */ + unsigned int reserved : 31; + } BIT; +} volatile GPT_EN_REG; + +/** + * @brief Channel status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ro_pwm0_num_sta : 10; /**< Number of output PWMs of channel. */ + unsigned int reserved : 21; + unsigned int ro_pwm0_run_sta : 1; /**< Output status of channel. */ + } BIT; +} volatile GPT_PWM0_STA_REG; + +/** + * @brief Buffer loading enable register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rg_buf_load_en : 1; /**< Buffer loading enable for registers that support buffer function. */ + unsigned int reserved : 31; + } BIT; +} volatile GPT_BUF_LOAD_EN_REG; + +/** + * @brief Buffer loading status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int tc_prd_ld_sts : 1; /**< Status of the count cycle register buffer. */ + unsigned int tc_refa0_ld_sts : 1; /**< Status of the counter reference value A0 register buffer. */ + unsigned int tc_refb0_ld_sts : 1; /**< Status of the count reference value B0 register buffer. */ + unsigned int reserved : 5; + unsigned int pg_act0_ld_sts : 1; /**< Status of the channel action configuration register buffer. */ + unsigned int reserved1 : 3; + unsigned int pwm0_cfg_ld_sts : 1; /**< Status of the channel configuration register buffer. */ + unsigned int reserved2 : 19; + } BIT; +} volatile GPT_LOAD_STS_REG; + +/** + * @brief Register mapping structure of GPT. + */ +typedef struct { + GPT_VER_INFO_REG GPT_VER_INFO; /**< Version information register, offset address: 0x00000000U */ + unsigned int resereved_0[3]; + GPT_TC_DIV_REG GPT_TC_DIV; /**< Frequency division coefficient register, offset address: 0x00000010U */ + GPT_TC_PRD_REG GPT_TC_PRD; /**< Count cycle register, offset address: 0x00000014U */ + GPT_TC_REFA0_REG GPT_TC_REFA0; /**< Count reference value A0 register, offset address: 0x00000018U */ + GPT_TC_REFB0_REG GPT_TC_REFB0; /**< Count reference value B0 register, offset address: 0x0000001CU */ + unsigned int reserved_1[4]; + GPT_TC_STS_REG GPT_TC_STS; /**< Count status register, offset address: 0x00000030U */ + unsigned int reserved_2[51]; + GPT_PG_ACT0_REG GPT_PG_ACT0; /**< Channel action configuration register, offset address: 0x00000100U */ + unsigned int reserved_3[63]; + GPT_INT_EN_REG GPT_INT_EN; /**< Interrupt enable register, offset address: 0x00000200U */ + GPT_INT_FLAG_REG GPT_INT_FLAG; /**< Interrupt flag register, offset address: 0x00000204U */ + GPT_INT_INJ_REG GPT_INT_INJ; /**< Interrupt injection register, offset address: 0x00000208U */ + unsigned int reserved_4[61]; + GPT_SOCDR_EN_REG GPT_SOCDR_EN; /**< ADC/DMA request enable register, offset address: 0x00000300U */ + unsigned int reserved_5[63]; + GPT_PWM0_CFG_REG GPT_PWM0_CFG; /**< Channel configuration register, offset address: 0x00000400U */ + unsigned int reserved_6[2]; + GPT_EN_REG GPT_EN; /**< GPT enable register., offset address: 0x0000040CU */ + GPT_PWM0_STA_REG GPT_PWM0_STA; /**< Channel status register, offset address: 0x00000410U */ + unsigned int reserved_7[59]; + GPT_BUF_LOAD_EN_REG GPT_BUF_LOAD_EN; /**< Cache loading enable register, offset address: 0x00000500U */ + GPT_LOAD_STS_REG GPT_LOAD_STS; /**< Buffer loading status register, offset address: 0x00000504U */ +} volatile GPT_RegStruct; + +/** + * @} + */ + +/* Parameter Check -----------------------------------------------------------*/ + +/** + * @brief Verify GPT max pwm num + * @param num Pwm number, only valid if keep equ 0 + * @retval true + * @retval false + */ +static inline bool IsGptPwmNum(unsigned int num) +{ + return ((num) <= GPT_PWM_MAX_NUM); +} + +/** + * @brief Verify GPT div value + * @param div division factor of GPT + * @retval true + * @retval false + */ +static inline bool IsGptDiv(unsigned int div) +{ + return (div <= GPT_PWM_DIV_FACTOR_MAX_VALUE); +} + +/** + * @brief Verify GPT period value + * @param period Period of GPT + * @retval true + * @retval false + */ +static inline bool IsGptPeriod(unsigned int period) +{ + return ((period >= GPT_PWM_PERIOD_MIN_VALUE) && (period <= GPT_PWM_PERIOD_MAX_VALUE)); +} + +/** + * @brief Verify GPT ref dot value + * @param value value of GPT ref dot + * @retval true + * @retval false + */ +static inline bool IsGptRefDot(unsigned int value) +{ + return (value <= GPT_TC_PRD_MAX_VALUE); +} + +/** + * @brief Verify GPT period value + * @param period Period of GPT + * @retval true + * @retval false + */ +static inline bool IsGptAction(unsigned int action) +{ + return (action <= GPT_ACTION_OUTPUT_FLIP); +} + +/** + * @brief Verify GPT period value + * @param period Period of GPT + * @retval true + * @retval false + */ +static inline bool IsGptSetOption(unsigned int option) +{ + return ((option == BASE_CFG_SET) || (option == BASE_CFG_UNSET)); +} + +/** + * @brief Verify GPT triggle DMA type + * @param period Period of GPT + * @retval true + * @retval false + */ +static inline bool IsGptTriggleDMAType(unsigned int triggleType) +{ + return ((triggleType <= GPT_PWM0_PERIOD_TRIGGER_DMA) && (triggleType >= GPT_PWM0_TRIGGER_DMA)); +} + + +/* Direct Configuration Layer Functions --------------------------------------*/ +/** + * @brief Set PWM Period + * @param gptx GPTx register baseAddr + * @param period Number of cycles of PWM + * @retval None + */ +static inline void DCL_GPT_SetPeriod(GPT_RegStruct *gptx, unsigned int period) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_PARAM_CHECK_NO_RET(IsGptPeriod(period)); + /* Setting the GPT Period */ + GPT_TC_PRD_REG prd; + prd.reg = gptx->GPT_TC_PRD.reg; + prd.BIT.rg_cnt_prd = period; + gptx->GPT_TC_PRD.reg = prd.reg; +} + +/** + * @brief Get PWM Period + * @param gptx GPTx register baseAdd + * @retval period Number of cycles of PWM + */ +static inline unsigned int DCL_GPT_GetPeriod(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_TC_PRD_REG prd; + prd.reg = gptx->GPT_TC_PRD.reg; + return prd.BIT.rg_cnt_prd; +} + +/** + * @brief Set GPT buffer load + * @param gptx GPTx register baseAddr + * @param buffLoad Buffer loading + * @retval None + */ +static inline void DCL_GPT_SetBufLoad(GPT_RegStruct *gptx, bool buffLoad) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + /* 0x1: enable the buffer load, 0: disable the buffer load */ + GPT_BUF_LOAD_EN_REG load; + load.reg = gptx->GPT_BUF_LOAD_EN.reg; + load.BIT.rg_buf_load_en = buffLoad; + gptx->GPT_BUF_LOAD_EN.reg = load.reg; +} + +/** + * @brief Get GPT buffer load status + * @param gptx GPTx register baseAddr + * @retval bool 1: buffer load enable, 0: buffer load disable. + */ +static inline bool DCL_GPT_GetBufLoad(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_TC_PRD_REG prd; + prd.reg = gptx->GPT_TC_PRD.reg; + return prd.BIT.rg_cnt_prd; +} + +/** + * @brief Set GPT PWM output mode + * @param gptx GPTx register baseAddr + * @param keepEnable KeepEnable 1: Outputs PWM waves all the time, 0: Fixed number of PWM waves are output. + * @retval None + */ +static inline void DCL_GPT_SetOutputMode(GPT_RegStruct *gptx, bool keepEnable) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_PWM0_CFG_REG outMode; + /* PWM output mode. 1: continuous output of PWM waveforms; 0: output of a fixed number of PWMs. */ + outMode.reg = gptx->GPT_PWM0_CFG.reg; + outMode.BIT.rg_pwm0_keep = keepEnable; + gptx->GPT_PWM0_CFG.reg = outMode.reg; +} + +/** + * @brief Get GPT PWM output mode + * @param gptx GPTx register baseAddr + * @retval bool 1: Outputs PWM waves all the time, 0: Fixed number of PWM waves are output. + */ +static inline bool DCL_GPT_GetOutputMode(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_PWM0_CFG_REG outMode; + outMode.reg = gptx->GPT_PWM0_CFG.reg; + return outMode.BIT.rg_pwm0_keep; +} + +/** + * @brief Set GPT PWM output numbers, only valid when 'rg_pwm0_keep' is set to false. + * @param gptx GPTx register baseAddr + * @param pwmNumber The number of output PWMs. + * @retval None + */ +static inline void DCL_GPT_SetPWMNumber(GPT_RegStruct *gptx, bool pwmNumber) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + /* Specifies the number of output PWM wavelengths. This parameter is valid only when PWM output mode is fixed. */ + GPT_PWM0_CFG_REG pwmset; + pwmset.reg = gptx->GPT_PWM0_CFG.reg; + pwmset.BIT.rg_pwm0_num = pwmNumber; + gptx->GPT_PWM0_CFG.reg = pwmset.reg; +} + +/** + * @brief Obtains the sequence number of the PWM wave that is being output in a channel. + * @param gptx GPTx register baseAddr + * @retval When PWM0_CFG.rg_pwm0_keep is 1, the value is always 0. + * When PWM0_CFG.rg_pwm0_keep is 0, PWM0_STA.ro_pwm0_num_sta indicates + * sequence number of the PWM wave being output by channel. + */ +static inline unsigned int DCL_GPT_GetChannelPWMNumber(GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_PWM0_STA_REG pwmStatus; + pwmStatus.reg = gptx->GPT_PWM0_STA.reg; + return pwmStatus.BIT.ro_pwm0_num_sta; +} + +/** + * @brief PWM output status + * @param gptx GPTx register baseAddr + * @retval bool : 0: Channel does not output PWM waves. + * 1: Channel is outputting PWM waves. + */ +static inline bool DCL_GPT_GetPWMOutPutStatus(GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_PWM0_STA_REG pwmStatus; + pwmStatus.reg = gptx->GPT_PWM0_STA.reg; + return pwmStatus.BIT.ro_pwm0_run_sta; +} + +/** + * @brief Enable output period finish interrupt of software injection channel, only valid when GPT outputs PWM + * @param gptx GPTx register baseAddr + * @retval None + */ +static inline void DCL_GPT_InjPeriodIntrruptEn(GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + /* 0x1: enables the software injection period finish interrupt, + 0x0: disables the software injection period finish interrupt. */ + GPT_INT_INJ_REG injEn; + injEn.reg = gptx->GPT_INT_INJ.reg; + injEn.BIT.rg_prd_int_inj = BASE_CFG_ENABLE; + gptx->GPT_INT_INJ.reg = injEn.reg; +} + +/** + * @brief Enable output finish interrupt of software injection channel, only valid when GPT outputs PWM + * @param gptx GPTx register baseAddr + * @retval None + */ +static inline void DCL_GPT_InjOutFinishIntrruptEn(GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + /* 0x1: enables the software injection output finish interrupt, + 0x0: disables the software injection output finish interrupt. */ + GPT_INT_INJ_REG injEn; + injEn.reg = gptx->GPT_INT_INJ.reg; + injEn.BIT.rg_pwm0_int_inj = BASE_CFG_ENABLE; + gptx->GPT_INT_INJ.reg = injEn.reg; +} + +/** + * @brief Enable for generating the DMA burst request signal after the output of channel is complete. + * @param gptx GPTx register baseAddr + * @param enable bool: + * 0: The DMA burst request is disabled when the output of channel is complete. + * 1: The DMA burst request signal is generated when the output of channel is complete. + * @retval None + */ +static inline void DCL_GPT_SetBurstDMAReqOutFin(GPT_RegStruct *gptx, bool enable) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + /* Sets the DMA burst request. 0x1:enable, 0x0:disable */ + GPT_SOCDR_EN_REG socDMA; + socDMA.reg = gptx->GPT_SOCDR_EN.reg; + socDMA.BIT.rg_dbr_pwm0_en = enable; + gptx->GPT_SOCDR_EN.reg = socDMA.reg; +} + +/** + * @brief Enable for generating the DMA single request signal after the output of channel is complete. + * @param gptx GPTx register baseAddr + * @param enable bool: + * 0: The DMA single request is disabled when the output of channel is complete. + * 1: The DMA single request signal is generated when the output of channel is complete. + * @retval None + */ +static inline void DCL_GPT_SetSingleDMAReqOutFin(GPT_RegStruct *gptx, bool enable) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_SOCDR_EN_REG socDMA; + /* Single DMA request when pwm out finish, 0x1: enable, 0:disable */ + socDMA.reg = gptx->GPT_SOCDR_EN.reg; + socDMA.BIT.rg_dsr_pwm0_en = enable; + gptx->GPT_SOCDR_EN.reg = socDMA.reg; +} + +/** + * @brief Enable for generating the DMA single request signal at the end of the counting period. + * @param gptx GPTx register baseAddr + * @param enable bool: + * 0: The DMA single request is disabled at the end of the counting period. + * 1: The DMA single request signal is generated at the end of the counting period. + * @retval None + */ +static inline void DCL_GPT_SetSingleDMAReqPeriod(GPT_RegStruct *gptx, bool enable) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + /* Single DMA request when pwm period output finish, 0x1: enable, 0:disable */ + GPT_SOCDR_EN_REG socDMA; + socDMA.reg = gptx->GPT_SOCDR_EN.reg; + socDMA.BIT.rg_dsr_prd_en = enable; + gptx->GPT_SOCDR_EN.reg = socDMA.reg; +} + +/** + * @brief Enable for generating the DMA burst request signal at the end of the counting period. + * @param gptx GPTx register baseAddr + * @param enable bool: + * 0: The DMA burst request is disabled at the end of the counting period. + * 1: The DMA burst request signal is generated at the end of the counting period. + * @retval None + */ +static inline void DCL_GPT_SetBurstDMAReqPeriod(GPT_RegStruct *gptx, bool enable) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_SOCDR_EN_REG socDMA; + /* Sets whether to initiate a DMA burst request after the PWM period output finish. */ + socDMA.reg = gptx->GPT_SOCDR_EN.reg; + socDMA.BIT.rg_dbr_prd_en = enable; + gptx->GPT_SOCDR_EN.reg = socDMA.reg; +} + +/** + * @brief Enable for generating the ADC signal at the end of the counting period. + * @param gptx GPTx register baseAddr + * @param enable bool: + * 0: The ADC signal is disabled when the counting period ends. + * 1: The ADC signal is generated at the end of the counting period. + * @retval None + */ +static inline void DCL_GPT_SetADCReqPeriod(GPT_RegStruct *gptx, bool enable) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + /* Sets whether to initiate an ADC request after the PWM period output finish. */ + GPT_SOCDR_EN_REG socDMA; + socDMA.reg = gptx->GPT_SOCDR_EN.reg; + socDMA.BIT.rg_soc_prd_en = enable; + gptx->GPT_SOCDR_EN.reg = socDMA.reg; +} + +/** + * @brief Enables the SOC signal generated when the output of channel is complete. + * @param gptx GPTx register baseAddr + * @param enable bool: + 0: The SOC signal is disabled when the output of channel is complete. + 1: The SoC signal is generated when the output of channel is complete. + * @retval None + */ +static inline void DCL_GPT_SetADCReqOutFin(GPT_RegStruct *gptx, bool enable) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + /* Sets whether to initiate an ADC request after the PWM output finish. */ + GPT_SOCDR_EN_REG socDMA; + socDMA.reg = gptx->GPT_SOCDR_EN.reg; + socDMA.BIT.rg_soc_pwm0_en = enable; + gptx->GPT_SOCDR_EN.reg = socDMA.reg; +} + + +/** + * @brief Set PWM Divider factor + * @param gptx GPTx register baseAddr + * @param div divison factor + * @retval None + */ +static inline void DCL_GPT_SetDiv(GPT_RegStruct *gptx, unsigned int div) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_PARAM_CHECK_NO_RET(IsGptDiv(div)); + GPT_TC_DIV_REG gptDiv; + /* Sets the frequency division of GPT. The value ranges from 1 to 4095. */ + gptDiv.reg = gptx->GPT_TC_DIV.reg; + gptDiv.BIT.rg_div_fac = div; + gptx->GPT_TC_DIV.reg = gptDiv.reg; +} + +/** + * @brief Get PWM Divider factor + * @param gptx GPTx register baseAddr + * @retval div divison factor + */ +static inline unsigned int DCL_GPT_GetDiv(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_TC_DIV_REG div; + div.reg = gptx->GPT_TC_DIV.reg; + return div.BIT.rg_div_fac; +} + +/** + * @brief Get PWM current count value of the divider + * @param gptx GPTx register baseAddr + * @retval divcnt Counter of current div counter value + */ +static inline unsigned int DCL_GPT_GetDivCnt(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_TC_STS_REG value; + value.reg = gptx->GPT_TC_STS.reg; + return value.BIT.ro_div_cnt; +} + +/** + * @brief Set PWM Current Counter value + * @param gptx GPTx register baseAddr + * @retval counter The current count value of the counter. + */ +static inline unsigned int DCL_GPT_GetCounterValue(GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_TC_STS_REG value; + value.reg = gptx->GPT_TC_STS.reg; + return value.BIT.ro_cnt_val; +} + +/** + * @brief Set Reference A Action + * @param gptx GPTx register baseAddr + * @param action When the counter is equal to the reference value A, the PWM output action, @ref GPT_ActionType + * @retval None + */ +static inline void DCL_GPT_SetRefAAction(GPT_RegStruct *gptx, GPT_ActionType action) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_PARAM_CHECK_NO_RET(IsGptAction(action)); + gptx->GPT_PG_ACT0.BIT.rg_pg_act0_refa0 = action; +} + +/** + * @brief Get Reference A Action + * @param gptx GPTx register baseAddr + * @retval action When the counter is equal to the reference value A, the PWM output action + */ +static inline unsigned int DCL_GPT_GetRefAAction(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + return gptx->GPT_PG_ACT0.BIT.rg_pg_act0_refa0; +} + +/** + * @brief Set Reference B Action + * @param gptx GPTx register baseAddr + * @param action When the counter is equal to the reference value B, the PWM output action, @ref GPT_ActionType + * @retval None + */ +static inline void DCL_GPT_SetRefBAction(GPT_RegStruct *gptx, GPT_ActionType action) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_PARAM_CHECK_NO_RET(IsGptAction(action)); + gptx->GPT_PG_ACT0.BIT.rg_pg_act0_refb0 = action; +} + +/** + * @brief Get Reference B Action + * @param gptx GPTx register baseAddr + * @retval action When the counter is equal to the reference value B, the PWM output action + */ +static inline unsigned int DCL_GPT_GetRefBAction(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + return gptx->GPT_PG_ACT0.BIT.rg_pg_act0_refb0; +} + +/** + * @brief Set Interrupt Enable/Disable + * @param gptx GPTx register baseAddr + * @param enable interrupt enable or disable + * @retval None + */ +static inline void DCL_GPT_SetInterruptEn(GPT_RegStruct *gptx, bool enable) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + gptx->GPT_INT_EN.BIT.rg_pwm0_int_en = enable; +} + +/** + * @brief Set Interrupt Enable/Disable + * @param gptx GPTx register baseAddr + * @retval enable interrupt enable or disable + */ +static inline unsigned int DCL_GPT_GetInterruptEn(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + return gptx->GPT_INT_EN.BIT.rg_pwm0_int_en; +} + +/** + * @brief Set Period Interrupt Enable/Disable + * @param gptx GPTx register baseAddr + * @param enable interrupt enable or disable + * @retval None + */ +static inline void DCL_GPT_SetPeriodInterruptEn(GPT_RegStruct *gptx, bool enable) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + gptx->GPT_INT_EN.BIT.rg_prd_int_en = enable; +} + +/** + * @brief Get Period Interrupt Enable/Disable + * @param gptx GPTx register baseAddr + * @retval enable interrupt enable or disable + */ +static inline unsigned int DCL_GPT_GetPeriodInterruptEn(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + return gptx->GPT_INT_EN.BIT.rg_prd_int_en; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_GPT_IP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/gpt/src/gpt.c b/vendor/xinlingyu_92_3061M/Project/drivers/gpt/src/gpt.c new file mode 100644 index 0000000000000000000000000000000000000000..0ad8dad388214382a995450c9c52fe45d75d2509 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/gpt/src/gpt.c @@ -0,0 +1,446 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file gpt.c + * @author MCU Driver Team + * @brief GPT module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the GPT. + * + Initialization function of GPT + * + Clock Configuration of GPT + * + Get GPT State and Apply GPT + */ + +#include "gpt.h" + +static unsigned int GPT_GetKeepState(GPT_Handle *handle); + +/** + * @brief Get Keep state + * @param handle GPT Handle + * @retval keep 0: Outputs a fixed number of square waves + * 1: Output continuous square wave + */ +static unsigned int GPT_GetKeepState(GPT_Handle *handle) +{ + GPT_PWM0_CFG_REG pwm0Cfg; + pwm0Cfg.reg = handle->baseAddress->GPT_PWM0_CFG.reg; + return pwm0Cfg.BIT.rg_pwm0_keep; +} + +/** + * @brief Init the GPT. + * @param handle GPT Handle. + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Paramter check fail + */ +BASE_StatusType HAL_GPT_Init(GPT_Handle *handle) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + + HAL_GPT_Stop(handle); + if (HAL_GPT_Config(handle) == BASE_STATUS_ERROR) { + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief Start GPT + * @param handle GPT Handle. + * @retval None + */ +void HAL_GPT_Start(GPT_Handle *handle) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + /* Enables the GPT to output PWM waves according to the configuration. */ + GPT_EN_REG gptEn; + gptEn.BIT.rg_gpt_en = BASE_CFG_SET; + handle->baseAddress->GPT_EN.reg = gptEn.reg; +} + +/** + * @brief Stop GPT + * @param handle GPT Handle. + * @retval None + */ +void HAL_GPT_Stop(GPT_Handle *handle) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + /* Disable the GPT to output PWM waves. */ + GPT_EN_REG gptEn; + gptEn.BIT.rg_gpt_en = BASE_CFG_UNSET; + handle->baseAddress->GPT_EN.reg = gptEn.reg; +} + +/** + * @brief GPT Configuration + * @param handle GPT Handle. + * @retval BASE_STATUS_OK + * @retval BASE_STATUS_ERROR + */ +BASE_StatusType HAL_GPT_Config(GPT_Handle *handle) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + GPT_PARAM_CHECK_WITH_RET(IsGptPeriod(handle->period), BASE_STATUS_ERROR); + GPT_PARAM_CHECK_WITH_RET(IsGptDiv(handle->clockDiv), BASE_STATUS_ERROR); + GPT_PARAM_CHECK_WITH_RET(IsGptRefDot(handle->refA0.refdot), BASE_STATUS_ERROR); + GPT_PARAM_CHECK_WITH_RET(IsGptRefDot(handle->refB0.refdot), BASE_STATUS_ERROR); + GPT_PARAM_CHECK_WITH_RET(handle->refA0.refdot <= handle->refB0.refdot, BASE_STATUS_ERROR); + GPT_PARAM_CHECK_WITH_RET(handle->refB0.refdot <= handle->period, BASE_STATUS_ERROR); + GPT_PARAM_CHECK_WITH_RET(IsGptAction(handle->refA0.refAction), BASE_STATUS_ERROR); + GPT_PARAM_CHECK_WITH_RET(IsGptAction(handle->refB0.refAction), BASE_STATUS_ERROR); + GPT_PARAM_CHECK_WITH_RET(IsGptPwmNum(handle->pwmNum), BASE_STATUS_ERROR); + + GPT_RegStruct *gptReg; + gptReg = handle->baseAddress; + /* Configure whether to enable cache loading. */ + gptReg->GPT_BUF_LOAD_EN.BIT.rg_buf_load_en = handle->bufLoad; + + /* Configuring the Cycle and Frequency Divider */ + gptReg->GPT_TC_DIV.reg = handle->clockDiv; + gptReg->GPT_TC_PRD.reg = handle->period; + /* Set the count reference point and the corresponding reference action. */ + gptReg->GPT_TC_REFA0.reg = handle->refA0.refdot; + gptReg->GPT_PG_ACT0.BIT.rg_pg_act0_refa0 = handle->refA0.refAction; + gptReg->GPT_TC_REFB0.reg = handle->refB0.refdot; + gptReg->GPT_PG_ACT0.BIT.rg_pg_act0_refb0 = handle->refB0.refAction; + + /* Sets the PWM output mode: outputs infinite PWM waves and outputs fixed number PWM. */ + gptReg->GPT_PWM0_CFG.BIT.rg_pwm0_keep = handle->pwmKeep; + /* Sets the number of output PWM wavelengths. This parameter is valid only when outputs fixed number PWM. */ + gptReg->GPT_PWM0_CFG.BIT.rg_pwm0_num = handle->pwmNum; + + /* Sets the GPT output completion interrupt and periodic interrupt. */ + gptReg->GPT_INT_EN.BIT.rg_prd_int_en = handle->handleEx.periodIntEnable; + gptReg->GPT_INT_EN.BIT.rg_pwm0_int_en = handle->handleEx.outputFinIntEnable; + + /* ADC Trigger Sampling Configuration */ + gptReg->GPT_SOCDR_EN.BIT.rg_soc_pwm0_en = handle->triggleAdcOutFinish; + gptReg->GPT_SOCDR_EN.BIT.rg_soc_prd_en = handle->triggleAdcPeriod; + return BASE_STATUS_OK; +} + +/** + * @brief Obtains GPT configuration parameters. + * @param handle GPT Handle. + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Fail + */ +BASE_StatusType HAL_GPT_GetConfig(GPT_Handle *handle) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + + GPT_RegStruct *gptReg = handle->baseAddress; + /* Obtains the configuration parameters of the PWM wavelength. */ + handle->clockDiv = gptReg->GPT_TC_DIV.reg; + handle->period = gptReg->GPT_TC_PRD.reg; + handle->refA0.refdot = gptReg->GPT_TC_REFA0.reg; + handle->refB0.refdot = gptReg->GPT_TC_REFB0.reg; + handle->refA0.refAction = gptReg->GPT_PG_ACT0.BIT.rg_pg_act0_refa0; + handle->refB0.refAction = gptReg->GPT_PG_ACT0.BIT.rg_pg_act0_refb0; + /* Obtains the cache loading status. */ + handle->bufLoad = gptReg->GPT_BUF_LOAD_EN.BIT.rg_buf_load_en; + + /* Obtaining the Interrupt Status */ + handle->handleEx.periodIntEnable = gptReg->GPT_INT_EN.BIT.rg_prd_int_en; + handle->handleEx.outputFinIntEnable = gptReg->GPT_INT_EN.BIT.rg_pwm0_int_en; + + /* Obtains ADC configuration parameters. */ + handle->triggleAdcOutFinish = gptReg->GPT_SOCDR_EN.BIT.rg_soc_pwm0_en; + handle->triggleAdcPeriod = gptReg->GPT_SOCDR_EN.BIT.rg_soc_prd_en; + + /* Obtains the PWM output mode. */ + GPT_PWM0_CFG_REG pwm0Cfg; + pwm0Cfg.reg = gptReg->GPT_PWM0_CFG.reg; + handle->pwmKeep = GPT_GetKeepState(handle); + handle->pwmNum = pwm0Cfg.BIT.rg_pwm0_num; + return BASE_STATUS_OK; +} + +/** + * @brief Set GPT count reference value and action configuration. + * @param handle GPT Handle. + * @param refer Input Pointer to the reference, @ref GPT_ReferCfg + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Parameter check fail + */ +BASE_StatusType HAL_GPT_SetReferCounterAndAction(GPT_Handle *handle, const GPT_ReferCfg *refer) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(refer != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + + unsigned int period = handle->baseAddress->GPT_TC_PRD.reg; + /* Verifying ref value parameters */ + if ((refer->refA0.refdot > period) || (refer->refB0.refdot > period)) { + return BASE_STATUS_ERROR; + } + GPT_RegStruct *gptReg = handle->baseAddress; + /* Set reference value parameters. */ + gptReg->GPT_TC_REFA0.reg = refer->refA0.refdot; + gptReg->GPT_TC_REFB0.reg = refer->refB0.refdot; + /* Set reference dot action */ + gptReg->GPT_PG_ACT0.BIT.rg_pg_act0_refa0 = refer->refA0.refAction; + gptReg->GPT_PG_ACT0.BIT.rg_pg_act0_refb0 = refer->refB0.refAction; + return BASE_STATUS_OK; +} + +/** + * @brief Get GPT count reference value and action configuration + * @param handle GPT Handle. + * @param refer Pointer to the reference, @ref GPT_ReferCfg + * @retval None + */ +void HAL_GPT_GetReferCounterAndAction(GPT_Handle *handle, GPT_ReferCfg *refer) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(refer != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + GPT_RegStruct *gptReg = handle->baseAddress; + /* Obtain the reference value of PWM. */ + refer->refA0.refdot = gptReg->GPT_TC_REFA0.reg; + refer->refB0.refdot = gptReg->GPT_TC_REFB0.reg; + /* The action of obtaining a reference value. */ + refer->refA0.refAction = gptReg->GPT_PG_ACT0.BIT.rg_pg_act0_refa0; + refer->refB0.refAction = gptReg->GPT_PG_ACT0.BIT.rg_pg_act0_refb0; +} + +/** + * @brief Set GPT counting period + * @param handle GPT Handle. + * @param period Counting period. + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Parameter check fail + */ +BASE_StatusType HAL_GPT_SetCountPeriod(GPT_Handle *handle, unsigned int period) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + GPT_PARAM_CHECK_WITH_RET(IsGptPeriod(period), BASE_STATUS_ERROR); + /* Sets the GPT counting period. The larger the value, the longer the period time. */ + GPT_TC_PRD_REG periodReg; + periodReg.reg = handle->baseAddress->GPT_TC_PRD.reg; + periodReg.BIT.rg_cnt_prd = period; + handle->baseAddress->GPT_TC_PRD.reg = periodReg.reg; + return BASE_STATUS_OK; +} + +/** + * @brief Get GPT Period + * @param handle GPT Handle. + * @retval unsigned int GPT Counting Period. + */ +unsigned int HAL_GPT_GetCountPeriod(GPT_Handle *handle) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + GPT_TC_PRD_REG periodReg; + /* return period value index */ + periodReg.reg = handle->baseAddress->GPT_TC_PRD.reg; + return periodReg.BIT.rg_cnt_prd; +} + +/** + * @brief Set GPT divider factor + * @param handle GPT Handle. + * @param div Input divider factor, Frequency division multiple equal configured + * frequency division factor + 1 + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Parameter check fail + */ +BASE_StatusType HAL_GPT_SetDivFactor(GPT_Handle *handle, unsigned int div) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + GPT_PARAM_CHECK_WITH_RET((div <= GPT_DIV_FACTOR_MAX_VALUE), BASE_STATUS_ERROR); + GPT_TC_DIV_REG divReg; + + /* Frequency division multiple = configured frequency division factor + 1 */ + divReg.reg = handle->baseAddress->GPT_TC_DIV.reg; + divReg.BIT.rg_div_fac = div; + handle->baseAddress->GPT_TC_DIV.reg = divReg.reg; + return BASE_STATUS_OK; +} + +/** + * @brief Get GPT Divison Factor + * @param handle GPT Handle + * @retval divCnt The current count value of the divider + */ +unsigned int HAL_GPT_GetDivFactor(GPT_Handle *handle) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + + GPT_TC_DIV_REG tcValue; + /* Obtains the frequency division value of the counter. */ + tcValue.reg = handle->baseAddress->GPT_TC_DIV.reg; + return tcValue.BIT.rg_div_fac; +} + +/** + * @brief Set GPT Cache Load Enable/Disable for Cache-enabled Registers + * @param handle GPT Handle + * @param bufferLoad Cache load enable/disable, @ref GPT_SetOption + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Fail + */ +BASE_StatusType HAL_GPT_SetBufferLoad(GPT_Handle *handle, GPT_SetOption bufferLoad) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + GPT_PARAM_CHECK_WITH_RET(IsGptSetOption(bufferLoad), BASE_STATUS_ERROR); + + GPT_BUF_LOAD_EN_REG bufLoadEn; + /* Set buffer load of GPT */ + bufLoadEn.reg = handle->baseAddress->GPT_BUF_LOAD_EN.reg; + bufLoadEn.BIT.rg_buf_load_en = bufferLoad; + handle->baseAddress->GPT_BUF_LOAD_EN.reg = bufLoadEn.reg; + return BASE_STATUS_OK; +} + +/** + * @brief Get Buffer status + * @param handle GPT Handle + * @retval loadStatus @ref GPT_LoadStatus + */ +unsigned int HAL_GPT_GetBufferLoadStatus(GPT_Handle *handle) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + + return handle->baseAddress->GPT_LOAD_STS.reg; +} + + +/** + * @brief Set GPT PWM output finish interrupt + * @param handle GPT Handle + * @param outFinishInt Out finish interrupt enable/disable @ref GPT_SetOption + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Fail + */ +BASE_StatusType HAL_GPT_SetOutFinishInt(GPT_Handle *handle, GPT_SetOption outFinishInt) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + GPT_PARAM_CHECK_WITH_RET(IsGptSetOption(outFinishInt), BASE_STATUS_ERROR); + /* Set output finish interrupt, 0x1: enabel, 0x0: disable. */ + GPT_INT_EN_REG intEn; + intEn.reg = handle->baseAddress->GPT_INT_EN.reg; + intEn.BIT.rg_pwm0_int_en = outFinishInt; + handle->baseAddress->GPT_INT_EN.reg = intEn.reg; + return BASE_STATUS_OK; +} + +/** + * @brief Set GPT period interrupt enable + * @param handle GPT Handle + * @param periodInt Period interrupt enable/disable @ref GPT_SetOption + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Fail + */ +BASE_StatusType HAL_GPT_SetPeriodInt(GPT_Handle *handle, GPT_SetOption periodInt) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + GPT_PARAM_CHECK_WITH_RET(IsGptSetOption(periodInt), BASE_STATUS_ERROR); + /* Set period output finish interrupt, 0x1: enable, 0x0:disable. */ + GPT_INT_EN_REG intEn; + intEn.reg = handle->baseAddress->GPT_INT_EN.reg; + intEn.BIT.rg_prd_int_en = periodInt; + handle->baseAddress->GPT_INT_EN.reg = intEn.reg; + return BASE_STATUS_OK; +} + +/** + * @brief Gpt pwm output finish interrupt service processing function. + * @param handle GPT Handle + * @retval None + */ +void HAL_GPT_IrqOutFinishHandler(void *handle) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_Handle *gptHandle = (GPT_Handle *)handle; + GPT_ASSERT_PARAM(IsGPTInstance(gptHandle->baseAddress)); + /* Check interrupt whether the injection interrupt */ + /* period and finish interrupt */ + if (gptHandle->baseAddress->GPT_INT_FLAG.BIT.ro_pwm0_int_flag == BASE_CFG_ENABLE) { + /* channel out put finish interrupt */ + gptHandle->baseAddress->GPT_INT_FLAG.BIT.rg_pwm0_int_clr = BASE_CFG_ENABLE; + if (gptHandle->userCallBack.PWMOutPutFin != NULL) { + gptHandle->userCallBack.PWMOutPutFin(gptHandle); + } + } + return; +} + +/** + * @brief Gpt period interrupt service processing function. + * @param handle GPT Handle + * @retval None + */ +void HAL_GPT_IrqPeriodHandler(void *handle) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_Handle *gptHandle = (GPT_Handle *)handle; + GPT_ASSERT_PARAM(IsGPTInstance(gptHandle->baseAddress)); + + if (gptHandle->baseAddress->GPT_INT_FLAG.BIT.ro_prd_int_flag == BASE_CFG_ENABLE) { + /* period interrupt */ + gptHandle->baseAddress->GPT_INT_FLAG.BIT.rg_prd_int_clr = BASE_CFG_ENABLE; + if (gptHandle->userCallBack.PWMPeriod != NULL) { + gptHandle->userCallBack.PWMPeriod(gptHandle); + } + } + return; +} + +/** + * @brief User callback function registration interface. + * @param gptHandle GPT handle. + * @param typeID Id of callback function type. @ref GPT_CallBackFunType + * @param pCallback pointer of the specified callbcak function. @ref GPT_CallBackFunc + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR fail + */ +BASE_StatusType HAL_GPT_RegisterCallBack(GPT_Handle *gptHandle, GPT_CallBackFunType typeID, + GPT_CallBackFunc pCallback) +{ + GPT_ASSERT_PARAM(gptHandle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(gptHandle->baseAddress)); + /* Registering interrupt callback function according to different types */ + switch (typeID) { + case GPT_INT_PERIOD: + /* Registers function for handling period output finish interrupt. */ + gptHandle->userCallBack.PWMPeriod = pCallback; + break; + case GPT_INT_PWM_OUTPUT_FIN: + /* Registers function for handling output finish interrupt. */ + gptHandle->userCallBack.PWMOutPutFin = pCallback; + break; + default: + return BASE_STATUS_ERROR; /* Failed to register the callback function. */ + } + return BASE_STATUS_OK; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/gpt/src/gpt_ex.c b/vendor/xinlingyu_92_3061M/Project/drivers/gpt/src/gpt_ex.c new file mode 100644 index 0000000000000000000000000000000000000000..44aaff7bd1a57b2f61146b18b33df3dd5f875ef2 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/gpt/src/gpt_ex.c @@ -0,0 +1,243 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file gpt_ex.c + * @author MCU Driver Team + * @brief GPT module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the GPT. + * + Initialization function of GPT + * + Clock Configuration of GPT + * + Get GPT State and Apply GPT + */ + +#include "gpt_ex.h" + +/** + * @brief Get GPT Counter Value + * @param handle GPT Handle + * @retval counter The current count value of the counter + */ +unsigned int HAL_GPT_GetCounterValueEx(GPT_Handle *handle) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + /* Returns count value of the counter. */ + GPT_TC_STS_REG tcValue; + tcValue.reg = handle->baseAddress->GPT_TC_STS.reg; + return tcValue.BIT.ro_cnt_val; +} + +/** + * @brief GPT Trigger DMA Enable + * @param handle GPT Handle + * @param triggerDMAType Trigger DMA Type Mask, @ref GPT_TriggerDMAType + * @retval BASE_STATUS_OK Setting succeeded. + * @retval BASE_STATUS_ERROR Setting failed. + */ +BASE_StatusType HAL_GPT_TriggerDMAEnableEx(GPT_Handle *handle, GPT_TriggerDMAType triggerDMAType) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + + GPT_SOCDR_EN_REG socdrEn; + /* Set GPT trigger DMA enable flags */ + socdrEn.reg = handle->baseAddress->GPT_SOCDR_EN.reg; + switch (triggerDMAType) { + case GPT_PWM0_TRIGGER_DMA: /* DMA request is triggered when the PWM output finish. */ + socdrEn.BIT.rg_dbr_pwm0_en = BASE_CFG_ENABLE; + socdrEn.BIT.rg_dsr_pwm0_en = BASE_CFG_ENABLE; + break; + case GPT_PERIOD_TRIGGER_DMA: /* DMA request is triggered when the PWM period output finish. */ + socdrEn.BIT.rg_dbr_prd_en = BASE_CFG_ENABLE; + socdrEn.BIT.rg_dsr_prd_en = BASE_CFG_ENABLE; + break; + /* DMA request is triggered when the PWM output finish or period output finish. */ + case GPT_PWM0_PERIOD_TRIGGER_DMA: + socdrEn.BIT.rg_dbr_pwm0_en = BASE_CFG_ENABLE; + socdrEn.BIT.rg_dsr_pwm0_en = BASE_CFG_ENABLE; + socdrEn.BIT.rg_dbr_prd_en = BASE_CFG_ENABLE; + socdrEn.BIT.rg_dsr_prd_en = BASE_CFG_ENABLE; + break; + default: + return BASE_STATUS_ERROR; /* Failed to set the DMA trigger. */ + } + handle->baseAddress->GPT_SOCDR_EN.reg = socdrEn.reg; + return BASE_STATUS_OK; +} + +/** + * @brief GPT Trigger DMA Disable + * @param handle GPT Handle + * @param triggerDMAType Trigger DMA Type Mask, @ref GPT_TriggerDMAType + * @retval BASE_STATUS_OK succeeded. + * @retval BASE_STATUS_ERROR failed. + */ +BASE_StatusType HAL_GPT_TriggerDMADisableEx(GPT_Handle *handle, GPT_TriggerDMAType triggerDMAType) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + + GPT_SOCDR_EN_REG socdrEn; + /* Set GPT trigger DMA enable flags */ + socdrEn.reg = handle->baseAddress->GPT_SOCDR_EN.reg; + switch (triggerDMAType) { + case GPT_PWM0_TRIGGER_DMA: /* Disables triggering DMA request when the PWM output finish. */ + socdrEn.BIT.rg_dbr_pwm0_en = BASE_CFG_DISABLE; + socdrEn.BIT.rg_dsr_pwm0_en = BASE_CFG_DISABLE; + break; + case GPT_PERIOD_TRIGGER_DMA: /* Disables triggering DMA request when the PWM period out finish. */ + socdrEn.BIT.rg_dbr_prd_en = BASE_CFG_DISABLE; + socdrEn.BIT.rg_dsr_prd_en = BASE_CFG_DISABLE; + break; + /* Disables triggering DMA request when the PWM output finish or period output finish. */ + case GPT_PWM0_PERIOD_TRIGGER_DMA: + socdrEn.BIT.rg_dbr_pwm0_en = BASE_CFG_DISABLE; + socdrEn.BIT.rg_dsr_pwm0_en = BASE_CFG_DISABLE; + socdrEn.BIT.rg_dbr_prd_en = BASE_CFG_DISABLE; + socdrEn.BIT.rg_dsr_prd_en = BASE_CFG_DISABLE; + break; + default: + return BASE_STATUS_ERROR; /* Failed to set the DMA trigger. */ + } + handle->baseAddress->GPT_SOCDR_EN.reg = socdrEn.reg; + return BASE_STATUS_OK; +} + +/** + * @brief GPT Trigger ADC Enable + * @param handle GPT Handle + * @param triggerADCType ADC Type Mask, @ref GPT_TriggerADCType + * @retval BASE_STATUS_OK succeeded. + * @retval BASE_STATUS_ERROR failed. + */ +BASE_StatusType HAL_GPT_TriggerADCEnableEx(GPT_Handle *handle, GPT_TriggerADCType triggerADCType) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + + GPT_SOCDR_EN_REG socdrEn; + /* Set GPT trigger ADC enable flags */ + socdrEn.reg = handle->baseAddress->GPT_SOCDR_EN.reg; + switch (triggerADCType) { + case GPT_PWM0_TRIGGER_ADC: /* Enable triggering ADC request when the PWM output finish. */ + socdrEn.BIT.rg_soc_pwm0_en = BASE_CFG_ENABLE; + break; + case GPT_PERIOD_TRIGGER_ADC: /* Enable triggering ADC request when the PWM period output finish. */ + socdrEn.BIT.rg_soc_prd_en = BASE_CFG_ENABLE; + break; + /* Enable triggering ADC request when the PWM period output finish and PWM output finish. */ + case GPT_PWM0_PERIOD_TRIGGER_ADC: + socdrEn.BIT.rg_soc_pwm0_en = BASE_CFG_ENABLE; + socdrEn.BIT.rg_soc_prd_en = BASE_CFG_ENABLE; + break; + default: + return BASE_STATUS_ERROR; /* Failed to set the ADC trigger. */ + } + handle->baseAddress->GPT_SOCDR_EN.reg = socdrEn.reg; + return BASE_STATUS_OK; +} + +/** + * @brief GPT Trigger ADC Disable + * @param handle GPT Handle + * @param triggerADCType Trigger DMA Type Mask, @ref GPT_TriggerADCType + * @retval BASE_STATUS_OK succeeded. + * @retval BASE_STATUS_ERROR failed. + */ +BASE_StatusType HAL_GPT_TriggerADCDisableEx(GPT_Handle *handle, GPT_TriggerADCType triggerADCType) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + + GPT_SOCDR_EN_REG socdrEn; + /* Set GPT trigger ADC enable flags */ + socdrEn.reg = handle->baseAddress->GPT_SOCDR_EN.reg; + switch (triggerADCType) { + case GPT_PWM0_TRIGGER_ADC: /* Disable triggering ADC request when the PWM output finish. */ + socdrEn.BIT.rg_soc_pwm0_en = BASE_CFG_DISABLE; + break; + case GPT_PERIOD_TRIGGER_ADC: /* Disable triggering ADC request when the PWM period output finish. */ + socdrEn.BIT.rg_soc_prd_en = BASE_CFG_DISABLE; + break; + /* Disable triggering ADC request when the PWM output finish and period output finish. */ + case GPT_PWM0_PERIOD_TRIGGER_ADC: + socdrEn.BIT.rg_soc_pwm0_en = BASE_CFG_DISABLE; + socdrEn.BIT.rg_soc_prd_en = BASE_CFG_DISABLE; + break; + default: + return BASE_STATUS_ERROR; /* Failed to set the ADC trigger. */ + } + handle->baseAddress->GPT_SOCDR_EN.reg = socdrEn.reg; + return BASE_STATUS_OK; +} + +/** + * @brief Get Current PWM0 Number + * @param handle GPT Handle + * @retval pwmNumber Current PWM0 Number, Only valid when PWM0_CFG.rg_pwm0_keep = 1 + */ +unsigned int HAL_GPT_GetCurrentPWM0NumberEx(GPT_Handle *handle) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + + GPT_PWM0_STA_REG pwm0Stat; + /* Clear GPT trigger ADC enable flags */ + pwm0Stat.reg = handle->baseAddress->GPT_PWM0_STA.reg; + return pwm0Stat.BIT.ro_pwm0_num_sta; +} + +/** + * @brief Injected PWM output completion interrupt, which takes effect only when PWM waves are output. + * @param handle GPT Handle + * @param softInjOutFin 1: enable 0: disable @ref GPT_SetOption + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Parameter check fail + */ +BASE_StatusType HAL_GPT_SoftInjOutFinIntEx(GPT_Handle *handle, GPT_SetOption softInjOutFin) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + GPT_PARAM_CHECK_WITH_RET(IsGptSetOption(softInjOutFin), BASE_STATUS_ERROR); + /* Software injection PWM period output finish interrupt. */ + GPT_INT_INJ_REG intInj; + intInj.reg = handle->baseAddress->GPT_INT_INJ.reg; + intInj.BIT.rg_pwm0_int_inj = softInjOutFin; + handle->baseAddress->GPT_INT_INJ.reg = intInj.reg; + return BASE_STATUS_OK; +} + +/** + * @brief Injected PWM period finish interrupt, which takes effect only when PWM waves are output. + * @param handle GPT Handle + * @param softInjPeriod 1: enable 0: disable, @ref GPT_SetOption + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Parameter check fail + */ +BASE_StatusType HAL_GPT_SoftInjPeriodFinIntEx(GPT_Handle *handle, GPT_SetOption softInjPeriod) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + GPT_PARAM_CHECK_WITH_RET(IsGptSetOption(softInjPeriod), BASE_STATUS_ERROR); + /* Software injection PWM output finish interrupt. */ + GPT_INT_INJ_REG intInj; + intInj.reg = handle->baseAddress->GPT_INT_INJ.reg; + intInj.BIT.rg_prd_int_inj = softInjPeriod; + handle->baseAddress->GPT_INT_INJ.reg = intInj.reg; + return BASE_STATUS_OK; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/i2c/common/inc/i2c.h b/vendor/xinlingyu_92_3061M/Project/drivers/i2c/common/inc/i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..decd4f3b3e9b8587e9c1424bf393efe0436a5c0f --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/i2c/common/inc/i2c.h @@ -0,0 +1,169 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file i2c.h + * @author MCU Driver Team, + * @brief I2C module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the I2C. + * + Initialization and de-initialization functions. + * + Peripheral transmit and receiving functions. + * + I2C parameter handle definition. + * + Basic Configuration Parameter Enumeration Definition. + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef McuMagicTag_I2C_H +#define McuMagicTag_I2C_H + +/* Includes ------------------------------------------------------------------*/ +#include "dma.h" +#include "i2c_ip.h" + +/** + * @defgroup I2C I2C + * @brief I2C module. + * @{ + */ + +/** + * @defgroup I2C_Common I2C Common + * @brief I2C common external module. + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ + +/** + * @defgroup I2C_Handle_Definition I2C Handle Definition + * @{ + */ + +/** + * @brief Module Status Enumeration Definition + */ +typedef enum { + I2C_STATE_RESET = 0x00000000U, + I2C_STATE_READY = 0x00000001U, + I2C_STATE_BUSY = 0x00000002U, + I2C_STATE_BUSY_MASTER_TX = 0x00000003U, + I2C_STATE_BUSY_MASTER_RX = 0x00000004U, + I2C_STATE_BUSY_SLAVE_TX = 0x00000005U, + I2C_STATE_BUSY_SLAVE_RX = 0x00000006U, + I2C_STATE_TIMEOUT = 0x00000007U, + I2C_STATE_ERROR = 0x00000008U, +} I2C_StateType; + +/** + * @brief Module handle structure definition + */ +typedef struct _I2C_Handle { + I2C_RegStruct *baseAddress; /**< Register base address. */ + I2C_ModeSelectType functionMode; /**< Set master or slave. */ + I2C_AddressMode addrMode; /**< 7bit or 10bit. */ + unsigned int slaveOwnAddress; /**< Own address as slave. */ + unsigned int sdaHoldTime; /**< SDA hold time. */ + unsigned int freq; /**< Operating Frequency. */ + unsigned int ignoreAckFlag; /**< Ignore the response flag bit. */ + unsigned int generalCallMode; /**< General call mode. */ + + volatile unsigned char *transferBuff; /**< Transmission Data buffer. */ + volatile unsigned int transferSize; /**< Transmission Data Length. */ + volatile unsigned int transferCount; /**< Transferred Data Count. */ + + unsigned int timeout; /**< Timeout period. */ + unsigned int rxWaterMark; /**< RX threshold configuration. */ + unsigned int txWaterMark; /**< TX threshold configuration. */ + unsigned int rxDmaCh; /**< RX DMA channel */ + unsigned int txDmaCh; /**< TX DMA channel */ + DMA_Handle *dmaHandle; /**< DMA handle */ + + I2C_StateType state; /**< Running Status. */ + BASE_StatusType errorCode; /**< Error Code. */ + I2C_UserCallBack userCallBack; /**< User-defined callback function. */ + I2C_ExtendHandle handleEx; /**< Extend handle, configuring some special parameters. */ +} I2C_Handle; +/** + * @} + */ + +/** + * @defgroup I2C_API_Declaration I2C HAL API + * @{ + */ +/** + * @brief Callback Function Type Definition. + */ +typedef void (*I2C_CallbackFunType)(void *handle); + +/* Function Interface Definition -------------------------------------------------------*/ +BASE_StatusType HAL_I2C_Init(I2C_Handle *handle); +BASE_StatusType HAL_I2C_Deinit(I2C_Handle *handle); +BASE_StatusType HAL_I2C_RegisterCallback(I2C_Handle *handle, I2C_CallbackId callbackID, I2C_CallbackFunType pcallback); +BASE_StatusType HAL_I2C_MasterReadBlocking(I2C_Handle *handle, + unsigned short devAddr, + unsigned char *rData, + unsigned int dataSize, + unsigned int timeout); +BASE_StatusType HAL_I2C_MasterWriteBlocking(I2C_Handle *handle, + unsigned short devAddr, + unsigned char *wData, + unsigned int dataSize, + unsigned int timeout); +BASE_StatusType HAL_I2C_SlaveReadBlocking(I2C_Handle *handle, + unsigned char *rData, + unsigned int dataSize, + unsigned int timeout); +BASE_StatusType HAL_I2C_SlaveWriteBlocking(I2C_Handle *handle, + unsigned char *wData, + unsigned int dataSize, + unsigned int timeout); + +BASE_StatusType HAL_I2C_MasterReadIT(I2C_Handle *handle, + unsigned short devAddr, + unsigned char *rData, + unsigned int dataSize); +BASE_StatusType HAL_I2C_MasterWriteIT(I2C_Handle *handle, + unsigned short devAddr, + unsigned char *wData, + unsigned int dataSize); +BASE_StatusType HAL_I2C_SlaveReadIT(I2C_Handle *handle, unsigned char *rData, unsigned int dataSize); +BASE_StatusType HAL_I2C_SlaveWriteIT(I2C_Handle *handle, unsigned char *wData, unsigned int dataSize); + +BASE_StatusType HAL_I2C_MasterReadDMA(I2C_Handle *handle, + unsigned short devAddr, + unsigned char *rData, + unsigned int dataSize); +BASE_StatusType HAL_I2C_MasterWriteDMA(I2C_Handle *handle, + unsigned short devAddr, + unsigned char *wData, + unsigned int dataSize); +BASE_StatusType HAL_I2C_SlaveReadDMA(I2C_Handle *handle, unsigned char *rData, unsigned int dataSize); +BASE_StatusType HAL_I2C_SlaveWriteDMA(I2C_Handle *handle, unsigned char *wData, unsigned int dataSize); +void HAL_I2C_IrqHandler(void *handle); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* #ifndef McuMagicTag_I2C_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/i2c/inc/i2c_ex.h b/vendor/xinlingyu_92_3061M/Project/drivers/i2c/inc/i2c_ex.h new file mode 100644 index 0000000000000000000000000000000000000000..5cc50448655c7ca7d2db0fd4765e876f7c224217 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/i2c/inc/i2c_ex.h @@ -0,0 +1,57 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file i2c_ex.h + * @author MCU Driver Team + * @brief I2C module driver + * @details The header file contains the following declaration: + * + Setting the Special Function Configuration. + */ + +#ifndef McuMagicTag_I2C_EX_H +#define McuMagicTag_I2C_EX_H + +/* Includes ------------------------------------------------------------------*/ +#include "i2c.h" +/* Macro definitions ---------------------------------------------------------*/ +/** + * @addtogroup I2C_IP + * @{ + */ + +/** + * @defgroup I2C_EX_API_Declaration I2C HAL API EX + * @{ + */ +BASE_StatusType HAL_I2C_SetDataTransferSequenceEx(I2C_Handle *handle, I2C_DataTransferSequenceType sequence); +BASE_StatusType HAL_I2C_SetSclStretchModeEx(I2C_Handle *handle, I2C_ClockStretchType clkStretch); +BASE_StatusType HAL_I2C_SetSclLowTimeoutEx(I2C_Handle *handle, unsigned int sclLowTimeout); +BASE_StatusType HAL_I2C_SetBusFreeTimeEx(I2C_Handle *handle, unsigned int busFreeTime); +BASE_StatusType HAL_I2C_Set10BitSlaveEnableEx(I2C_Handle *handle); +BASE_StatusType HAL_I2C_SetDeviceIdAddressEnableEx(I2C_Handle *handle); +BASE_StatusType HAL_I2C_SetStartByteEnableEx(I2C_Handle *handle); +BASE_StatusType HAL_I2C_SetOwnAddressMaskEx(I2C_Handle *handle, unsigned int addrMask); +BASE_StatusType HAL_I2C_SetOwnXmbAddressMaskEx(I2C_Handle *handle, unsigned int addrMask); +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_I2C_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/i2c/inc/i2c_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/i2c/inc/i2c_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..dcd04953db39ae046c8722dffc8ae861ca819e88 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/i2c/inc/i2c_ip.h @@ -0,0 +1,1960 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file i2c_ip.h + * @author MCU Driver Team + * @brief I2C module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the I2C. + * + Extended Configuration Parameter Struct Definition. + * + Register definition structure. + * + Timing command enumeration. + * + Direct configuration layer interface. + * + Basic parameter configuration macro. + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef McuMagicTag_I2C_IP_H +#define McuMagicTag_I2C_IP_H + +/* Includes ------------------------------------------------------------------*/ +#include "baseinc.h" + +/* Macro definitions --------------------------------------------------------- */ +#ifdef I2C_PARAM_CHECK +#define I2C_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define I2C_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define I2C_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define I2C_ASSERT_PARAM(para) ((void)0U) +#define I2C_PARAM_CHECK_NO_RET(para) ((void)0U) +#define I2C_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +/** + * @addtogroup I2C + * @{ + */ + +/** + * @defgroup I2C_IP I2C_IP + * @brief I2C_IP: i2c_v1 + * @{ + */ + +#define I2C_IGNORE_NAK_ENABLE BASE_CFG_ENABLE /**< Ignore acknowledgment configuration enable. */ +#define I2C_IGNORE_NAK_DISABLE BASE_CFG_DISABLE /**< Ignore acknowledgment configuration disable. */ + +#define I2C_STANDARD_FREQ_TH 100000 /**< Standard mode,the frequency band is less than or equal to 100 kHz. */ + +#define I2C_INTR_RAW_ALL_ENABLE 0x00FFFFFFU /**< 1111111111111 */ +#define I2C_INTR_RAW_ALL_DISABLE 0x00000000U /**< 0000000000000 */ + +#define I2C_INTR_EN_ALL_ENABLE 0x00FFFFFFU /**< 1111111111111 */ +#define I2C_INTR_EN_ALL_DISABLE 0x00000000U /**< 0000000000000 */ + +#define I2C_ONCE_TRANS_MAX_NUM 0x400 + +#define I2C_SCL_HIGH_TIME_POS 16 +#define I2C_SCL_HIGHT_TIME_MASK (0xFFFF << I2C_SCL_HIGH_TIME_POS) +#define I2C_SCL_LOW_TIME_POS 0 +#define I2C_SCL_LOW_TIME_MASK (0xFFFF << I2C_SCL_LOW_TIME_POS) + +#define I2C_SDA_HOLD_DURATION_POS 16 +#define I2C_SDA_HOLD_DURATION_MASK (0xFFFF << I2C_SDA_HOLD_DURATION_POS) + +#define I2C_TXFIFO_WDATA_POS 0 +#define I2C_TXFIFO_WDATA_MASK (0xFF << I2C_TXFIFO_WDATA_POS) +#define I2C_TXFIFO_CMD_POS 8 +#define I2C_TXFIFO_CMD_MASK (0xF << I2C_TXFIFO_CMD_POS) + +#define XMBUS_OWN_ADDRESS_MASK 0x3FF + +/** + * @defgroup I2C_Param_Def I2C Parameters Definition. + * @brief Definition of I2C configuration parameters. + * @{ + */ +/* Typedef definitions -------------------------------------------------------*/ +/** + * @brief Address Mode Selection Enumeration Definition + */ +typedef enum { + I2C_7_BITS = 0x00000000U, + I2C_10_BITS = 0x00000001U +} I2C_AddressMode; + +/** + * @brief I2C DMA operation type enumeration definition + */ +typedef enum { + I2C_DMA_OP_NONE = 0x00000000U, + I2C_DMA_OP_READ = 0x00000001U, + I2C_DMA_OP_WRITE = 0x00000002U, + I2C_DMA_OP_WRITE_READ = 0x00000003U +} I2C_DmaOperationType; + +/** + * @brief I2C mode selection enumeration definition + */ +typedef enum { + I2C_MODE_SELECT_NONE = 0x00000000U, + I2C_MODE_SELECT_MASTER_ONLY = 0x00000001U, + I2C_MODE_SELECT_SLAVE_ONLY = 0x00000002U, + I2C_MODE_SELECT_MASTER_SLAVE = 0x00000003U +} I2C_ModeSelectType; + +/** + * @brief Callback Function ID Enumeration Definition + */ +typedef enum { + I2C_MASTER_TX_COMPLETE_CB_ID = 0x00000000U, + I2C_MASTER_RX_COMPLETE_CB_ID = 0x00000001U, + I2C_SLAVE_TX_COMPLETE_CB_ID = 0x00000002U, + I2C_SLAVE_RX_COMPLETE_CB_ID = 0x00000003U, + I2C_ERROR_CB_ID = 0x00000004U, +} I2C_CallbackId; +/** + * @brief I2C operation timing enumeration definition + */ +typedef enum { + I2C_CMD_INT1 = 0x00000000U, + I2C_CMD_S = 0x00000001U, + I2C_CMD_M_TD_RACK_S_RD_TACK = 0x00000002U, + I2C_CMD_M_TD_RNACK_S_RD_TNACK = 0x00000003U, + I2C_CMD_M_TD_S_RD = 0x00000004U, + I2C_CMD_M_RD_TACK_S_TD_RACK = 0x00000005U, + I2C_CMD_M_RD_TNACK_S_TD_RNACK = 0x00000006U, + I2C_CMD_M_RD_S_TD = 0x00000007U, + I2C_CMD_M_TPEC_RACK_S_RPEC_TACK = 0x0000000AU, + I2C_CMD_M_TPEC_RNACK_S_RPEC_TNACK = 0x0000000BU, + I2C_CMD_M_RPEC_TACK_S_TPEC_RACK = 0x0000000DU, + I2C_CMD_M_RPEC_TNACK_S_TPEC_RNACK = 0x0000000EU, + I2C_CMD_P = 0x0000000FU +} I2C_CmdType; + +/** + * @brief I2C data transfer sequence enumeration definition. + */ +typedef enum { + I2C_BIG_BIT_FIRST = 0x00000000U, + I2C_LITTLE_BIT_FIRST = 0x00000001U, +} I2C_DataTransferSequenceType; + +/** + * @brief I2C clock stretching enumeration definition. + */ +typedef enum { + I2C_CLOCK_STRETCH_ENABLE = 0x00000000U, + I2C_CLOCK_STRETCH_DISABLE = 0x00000001U, +} I2C_ClockStretchType; + +/** + * @brief I2C extend handle, configuring some special parameters. + */ +typedef struct { + unsigned int spikeFilterTime; /**< The SDA and SCL Glitch Filtering Configuration. */ + unsigned int sdaDelayTime; /**< The SDA delay sampling configuration. */ + unsigned int slaveOwnXmbAddressEnable; /**< Enable the I2C second own address function. */ + unsigned int slaveOwnXmbAddress; /**< The second own address as slave. */ +} I2C_ExtendHandle; + +/** + * @brief User-defined callback function. + */ +typedef struct { + void (*TxCplCallback)(void* handle); /**< Sending completion callback function. */ + void (*RxCplCallback)(void* handle); /**< Receive completion callback function. */ + void (*ErrorCallback)(void* handle); /**< Error callback function. */ +} I2C_UserCallBack; + +/** + * @} + */ + +/** + * @defgroup I2C_Reg_Def I2C Register Definition + * @brief Description I2C register mapping structure + * @{ + */ + +/** + * @brief I2C mode configuration registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int mst_slv_function : 2; /**< Master and Slave Function Selection. */ + unsigned int lit_end : 1; /**< Data Transfer Sequence. 0:MSbit-First mode, 1:LSbit-First mode. */ + unsigned int xmb_pec_en : 1; /**< PEC calculation enable for SMBus and PMBus, + 0:disable, 1:enable. */ + unsigned int rack_mode : 1; /**< ACK/NACK receiving mode, 0:ack mode, 1:ignore ack. */ + unsigned int scl_stretch_disable : 1; /**< Clock stretching enable. 0:enable, 1:disable. */ + unsigned int reserved0 : 26; + } BIT; +} volatile I2C_MODE_REG; + +/** + * @brief I2C SCL high-level and low-level duration registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int scl_low_time : 16; /**< SCL Low Level Duration. */ + unsigned int scl_high_time : 16; /**< SCL High Level Duration. */ + } BIT; +} volatile I2C_SCL_CFG_REG; + +/** + * @brief I2C SDA timing configuration registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int sda_delay_time : 4; /**< SDA delay sampling configuration. */ + unsigned int reserved0 : 12; + unsigned int sda_hold_time : 16; /**< SDA hold time configuration. */ + } BIT; +} volatile I2C_SDA_CFG_REG; + +/** + * @brief I2C Slave Address Configuration registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int own_address : 10; /**< Own address as slave. */ + unsigned int reserved0 : 2; + unsigned int own_address_mask : 10; /**< Slave's own address mask. */ + unsigned int reserved1 : 2; + unsigned int i2c_general_call_en : 1; /**< Enable General Call Address Receiving, 0:disable, 1:enable. */ + unsigned int i2c_device_id_en : 1; /**< Enable the function of receiving device ID addresses, + 0:disable, 1:enable. */ + unsigned int i2c_start_byte_en : 1; /**< Enable START Byte Address Receiving, 0:disable, 1:enable. */ + unsigned int i2c_10bit_slave_en : 1; /**< Enable 10bit Slave Addressing Receiving, 0:disable, 1:enable. */ + unsigned int reserved2 : 4; + } BIT; +} volatile I2C_OWN_ADDR_REG; + +/** + * @brief I2C SMBus PMBus Device Dedicated Address Configuration registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int xmb_address : 10; /**< I2C SMBus PMBus Device Dedicated Address. */ + unsigned int reserved0 : 2; + unsigned int xmb_address_mask : 10; /**< I2C SMBus PMBus Device Private Address Mask. */ + unsigned int xmb_address_en : 1; /**< I2C SMBus PMBus Device Dedicated Address Enable, + 0:disable, 1:enable. */ + unsigned int reserved1 : 1; + unsigned int smb_host_notify_en : 1; /**< Enable receiving SMBus Host Address, 0:disable, 1:enable. */ + unsigned int smb_alert_response_en : 1; /**< Enable receiving SMBus Alert Response Address, + 0:disable, 1:enable. */ + unsigned int smb_dev_default_en : 1; /**< Enable receiving SMBus Device Default Address, + 0:disable, 1:enable. */ + unsigned int reserved2 : 1; + unsigned int pmb_zone_read_en : 1; /**< Enable RX PMBus Zone Read Address, 0:disable, 1:enable. */ + unsigned int pmb_zone_write_en : 1; /**< Enable PMBus Zone Write Address Receiving, + 0:disable, 1:enable. */ + unsigned int reserved3 : 2; + } BIT; +} volatile XMB_DEV_ADDR_REG; + +/** + * @brief Address received by the I2C slave, R/W bit registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rx_rw : 1; /**< The address received by the slave. */ + unsigned int rx_addr : 10; /**< R/W bit received by the slave. */ + unsigned int reserved0 : 21; + } BIT; +} volatile I2C_RX_ADDR_REG; + +/** + * @brief I2C TX FIFO registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int tx_fifo_wdata : 8; /**< The software writes the data to be sent, write only. */ + unsigned int mst_slv_cmd : 4; /**< Master Timing Command. */ + unsigned int reserved0 : 20; + } BIT; +} volatile I2C_TX_FIFO_REG; + +/** + * @brief I2C RX FIFO registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rx_fifo_rdata : 8; /**< The software writes the data to be receive, read only. */ + unsigned int reserved0 : 24; + } BIT; +} volatile I2C_RX_FIFO_REG; + +/** + * @brief I2C TX threshold registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int tx_watermark : 4; /**< TX FIFO Threshold. */ + unsigned int reserved0 : 28; + } BIT; +} volatile I2C_TX_WATERMARK_REG; + +/** + * @brief I2C RX threshold registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rx_watermark : 4; /**< RX FIFO Threshold. */ + unsigned int reserved0 : 28; + } BIT; +} volatile I2C_RX_WATERMARK_REG; + +/** + * @brief I2C control 1 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int mst_start : 1; /**< Master startup control, 0:disable, 1:enable. */ + unsigned int reserved0 : 1; + unsigned int rst_rx_fifo : 1; /**< Resetting the RX FIFO, 0:clearing completed, 1:clearing in progress. */ + unsigned int rst_tx_fifo : 1; /**< Resetting the TX FIFO, 0:clearing completed, 1:clearing in progress. */ + unsigned int reserved1 : 4; + unsigned int dma_operation : 2; /**< DMA operation control. */ + unsigned int dma_rx_lsreq_en : 1; /**< Flow control enable for the RX peripheral of the DMA I2C module, + 0:disable, 1:enable. */ + unsigned int reserved2 : 21; + } BIT; +} volatile I2C_CTRL1_REG; + +/** + * @brief I2C control 2 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int force_sda : 1; /**< Forcibly sets the value of an I2C pin, 0:set 0, 1:set 1. */ + unsigned int reserved0 : 3; + unsigned int force_scl : 1; /**< Forcibly sets the value of an I2C pin, 0:set 0, 1:set 1. */ + unsigned int reserved1 : 3; + unsigned int gpio_mode : 1; /**< The I2C pin is used as a GPIO pin. */ + unsigned int reserved2 : 3; + unsigned int smb_alert_n_oe_n : 1; /**< SMBus SMBALERT# Output Value, + 0:Low-level Open-Drain output, + 1:Open-Drain output high impedance. */ + unsigned int smb_alert_n_in : 1; /**< SMBus SMBALERT# Input value, + 0:Low level input, 1:High level input . */ + unsigned int reserved3 : 2; + unsigned int smb_suspend_n_oe_n : 1; /**< SMBus SMBSUS# is output, 0:push-pull output, + 1:no output, high impedance. */ + unsigned int smb_suspend_n_out : 1; /**< SMBus SMBSUS# Output Value, + 0:low level output, 1:high level output. */ + unsigned int smb_suspend_n_in : 1; /**< SMBus SMBSUS# Input Value, + 0:low level output, 1:high level output. */ + unsigned int reserved4 : 13; + } BIT; +} volatile I2C_CTRL2_REG; + +/** + * @brief I2C FIFO status registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rx_fifo_vld_num : 5; /**< Number of valid values in the RX FIFO. */ + unsigned int reserved0 : 3; + unsigned int tx_fifo_vld_num : 5; /**< Number of valid values in the TX FIFO. */ + unsigned int reserved1 : 3; + unsigned int reserved2 : 16; + } BIT; +} volatile I2C_FIFO_STAT_REG; + +/** + * @brief I2C state machine status registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 10; + unsigned int mst_cmd_exe : 4; /**< Sequence command being executed by the master. */ + unsigned int mst_busy : 1; /**< Master Busy, 0:master idle, 1:master busy. */ + unsigned int reserved1 : 6; + unsigned int slv_cmd_exe : 4; /**< Sequence command being executed by the slave node. */ + unsigned int slv_busy : 1; /**< Slave Busy, 0:slave idle, 1:slave busy. */ + unsigned int reserved3 : 4; + unsigned int i2c_bus_free : 1; /**< I2C bus idele, 0:i2c bus busy, 1:i2c bus idle. */ + unsigned int reserved2 : 1; + } BIT; +} volatile I2C_FSM_STAT_REG; + +/** + * @brief I2C raw interrupt registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int mst_rx_ack_unmatch_raw : 1; /**< The RX acknowledgment bit meets the expectation, + 0:match, 1:unmatch. */ + unsigned int rx_fifo_not_empty_raw : 1; /**< The RX FIFO is not empty, 0:no interrupt, 1:have interrupt. */ + unsigned int rx_ge_watermark_raw : 1; /**< The number of data records in the RX FIFO is greater than or + equal to the threshold, 0:no interrupt, 1:have interrupt. */ + unsigned int rx_fifo_full_raw : 1; /**< RX FIFO Full, 0:no interrupt, 1:have interrupt. */ + unsigned int tx_le_watermark_raw : 1; /**< The number of data records in the TX FIFO is less than or + equal to the threshold, 0:no interrupt, 1:have interrupt. */ + unsigned int tx_fifo_empty_raw : 1; /**< The TX FIFO is empty, 0:no interrupt, 1:have interrupt. */ + unsigned int tx_fifo_not_full_raw : 1; /**< The TX FIFO is not full, 0:no interrupt, 1:have interrupt. */ + unsigned int rx_data_ready_raw : 1; /**< The RX FIFO receives new data, + 0:no interrupt, 1:have interrupt. */ + unsigned int tx_data_request_raw : 1; /**< The TX FIFO requests new commands and data, + 0:no interrupt, 1:have interrupt. */ + unsigned int stop_det_raw : 1; /**< STOP detected, 0:no interrupt, 1:have interrupt. */ + unsigned int start_det_raw : 1; /**< Checked to START, 0:no interrupt, 1:have interrupt. */ + unsigned int arb_lost_raw : 1; /**< Arbitration loss, 0:no interrupt, 1:have interrupt. */ + unsigned int mst_cmd_done_raw : 1; /**< The master timing command is completed normally, + 0:no interrupt, 1:have interrupt. */ + unsigned int scl_low_timeout_raw : 1; /**< SCL Low Timeout Detected, 0:no interrupt, 1:have interrupt. */ + unsigned int smb_alert_raw : 1; /**< Falling edge of SMBus SMBALERT# input signal detected, + 0:no interrupt, 1:have interrupt. */ + unsigned int smb_suspend_raw : 1; /**< Falling edge of SMBus SMBALERT# input signal detected, + 0:no interrupt, 1:have interrupt. */ + unsigned int mst_cmd_int1_raw : 1; /**< Master timing command interrupt 1, + 0:no interrupt, 1:have interrupt. */ + unsigned int slv_cmd_int1_raw : 1; /**< Slave timing command interrupt 1, + 0:no interrupt, 1:have interrupt. */ + unsigned int mst_pec_check_fail_raw : 1; /**< The master checks the received PEC error, + 0:no interrupt, 1:have interrupt. */ + unsigned int slv_pec_check_fail_raw : 1; /**< The slave node checks the received PEC error, + 0:no interrupt, 1:have interrupt. */ + unsigned int slv_rx_ack_unmatch_raw : 1; /**< Check whether the Slave RX acknowledgment bit meets the + expectation of the timing command, + 0:no interrupt, 1:have interrupt. */ + unsigned int slv_addr_match_raw : 1; /**< The slave detects the received address matches, + 0:no interrupt, 1:have interrupt. */ + unsigned int reserved0 : 10; + } BIT; +} volatile I2C_INTR_RAW_REG; + +/** + * @brief I2C interrupt enable registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int mst_rx_ack_unmatch_en : 1; /**< The RX acknowledgment bit meets the expectation, + 0:disable, 1:enable. */ + unsigned int rx_fifo_not_empty_en : 1; /**< The RX FIFO is not empty, 0:disable, 1:enable. */ + unsigned int rx_ge_watermark_en : 1; /**< The rx_ge_watermark enable, 0:disable, 1:enable. */ + unsigned int rx_fifo_full_en : 1; /**< RX FIFO Full enable, 0:disable, 1:enable. */ + unsigned int tx_le_watermark_en : 1; /**< The tx_le_watermark, 0:disable, 1:enable. */ + unsigned int tx_fifo_empty_en : 1; /**< The TX FIFO is empty, 0:disable, 1:enable. */ + unsigned int tx_fifo_not_full_en : 1; /**< The TX FIFO is not full, 0:disable, 1:enable. */ + unsigned int rx_data_ready_en : 1; /**< The RX FIFO receives new data, 0:disable, 1:enable. */ + unsigned int tx_data_request_en : 1; /**< The TX FIFO requests new commands and data, + 0:disable, 1:enable. */ + unsigned int stop_det_en : 1; /**< STOP detected enable, 0:disable, 1:enable. */ + unsigned int start_det_en : 1; /**< Checked to START enable, 0:disable, 1:enable. */ + unsigned int arb_lost_en : 1; /**< Arbitration loss enable, 0:disable, 1:enable. */ + unsigned int mst_cmd_done_en : 1; /**< The master timing command is completed normally, + 0:disable, 1:enable. */ + unsigned int scl_low_timeout_en : 1; /**< SCL Low Timeout Detected enable, 0:disable, 1:enable. */ + unsigned int smb_alert_en : 1; /**< Falling edge of SMBus SMBALERT# input signal detected, + 0:disable, 1:enable. */ + unsigned int smb_suspend_en : 1; /**< Falling edge of SMBus SMBALERT# input signal detected, + 0:disable, 1:enable. */ + unsigned int mst_cmd_int1_en : 1; /**< Master timing command interrupt 1 enable, 0:disable, 1:enable. */ + unsigned int slv_cmd_int1_en : 1; /**< Slave timing command interrupt 1 enable, 0:disable, 1:enable. */ + unsigned int mst_pec_check_fail_en : 1; /**< The master checks the received PEC error, 0:disable, 1:enable. */ + unsigned int slv_pec_check_fail_en : 1; /**< The slave node checks the received PEC error, + 0:disable, 1:enable. */ + unsigned int slv_rx_ack_unmatch_en : 1; /**< Check whether the Slave RX acknowledgment bit meets the + expectation of the timing command, 0:disable, 1:enable. */ + unsigned int slv_addr_match_en : 1; /**< The slave detects the received address matches, + 0:disable, 1:enable. */ + unsigned int reserved0 : 10; + } BIT; +} volatile I2C_INTR_EN_REG; + +/** + * @brief I2C interrupt status registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int mst_rx_ack_unmatch_int : 1; /**< The RX acknowledgment bit meets the expectation, + 0:match, 1:unmatch. */ + unsigned int rx_fifo_not_empty_int : 1; /**< The RX FIFO is not empty, 0:no interrupt, 1:have interrupt. */ + unsigned int rx_ge_watermark_int : 1; /**< The number of data records in the RX FIFO is greater than or + equal to the threshold, 0:no interrupt, 1:have interrupt. */ + unsigned int rx_fifo_full_int : 1; /**< RX FIFO Full, 0:no interrupt, 1:have interrupt. */ + unsigned int tx_le_watermark_int : 1; /**< The number of data records in the TX FIFO is less than or + equal to the threshold, 0:no interrupt, 1:have interrupt. */ + unsigned int tx_fifo_empty_int : 1; /**< The TX FIFO is empty, 0:no interrupt, 1:have interrupt. */ + unsigned int tx_fifo_not_full_int : 1; /**< The TX FIFO is not full, 0:no interrupt, 1:have interrupt. */ + unsigned int rx_data_ready_int : 1; /**< The RX FIFO receives new data, + 0:no interrupt, 1:have interrupt. */ + unsigned int tx_data_request_int : 1; /**< The TX FIFO requests new commands and data, + 0:no interrupt, 1:have interrupt. */ + unsigned int stop_det_int : 1; /**< STOP detected, 0:no interrupt, 1:have interrupt. */ + unsigned int start_det_int : 1; /**< Checked to START, 0:no interrupt, 1:have interrupt. */ + unsigned int arb_lost_int : 1; /**< Arbitration loss, 0:no interrupt, 1:have interrupt. */ + unsigned int mst_cmd_done_int : 1; /**< The master timing command is completed normally, + 0:no interrupt, 1:have interrupt. */ + unsigned int scl_low_timeout_int : 1; /**< SCL Low Timeout Detected, 0:no interrupt, 1:have interrupt. */ + unsigned int smb_alert_int : 1; /**< Falling edge of SMBus SMBALERT# input signal detected, + 0:no interrupt, 1:have interrupt. */ + unsigned int smb_suspend_int : 1; /**< Falling edge of SMBus SMBALERT# input signal detected, + 0:no interrupt, 1:have interrupt. */ + unsigned int mst_cmd_int1 : 1; /**< Master timing command interrupt 1, + 0:no interrupt, 1:have interrupt. */ + unsigned int slv_cmd_int1 : 1; /**< Slave timing command interrupt 1, + 0:no interrupt, 1:have interrupt. */ + unsigned int mst_pec_check_fail_int : 1; /**< The master checks the received PEC error, + 0:no interrupt, 1:have interrupt. */ + unsigned int slv_pec_check_fail_int : 1; /**< The slave node checks the received PEC error, + 0:no interrupt, 1:have interrupt. */ + unsigned int slv_rx_ack_unmatch_int : 1; /**< Check whether the Slave RX acknowledgment bit meets the + expectation of the timing command, + 0:no interrupt, 1:have interrupt. */ + unsigned int slv_addr_match_int : 1; /**< The slave detects the received address matches, + 0:no interrupt, 1:have interrupt. */ + unsigned int reserved0 : 10; + } BIT; +} volatile I2C_INTR_STAT_REG; + +/** + * @brief I2C version number registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int version : 32; /**< I2C controller version. */ + } BIT; +} volatile I2C_VERSION_REG; + +/** + * @brief I2C SCL timeout threshold registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int scl_low_timeout : 23; /**< SCL low-level timeout configuration. */ + unsigned int reserved0 : 9; + } BIT; +} volatile I2C_SCL_TIMEOUT_REG; + +/** + * @brief I2C bus idle threshold registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int bus_free_time : 16; /**< Bus Idle Threshold. */ + unsigned int reserved0 : 16; + } BIT; +} volatile I2C_BUS_FREE_REG; + +/** + * @brief I2C SDA and SCL filtering configuration registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int spike_filter_time : 4; /**< SDA and SCL Glitch Filtering Configuration. */ + unsigned int reserved0 : 28; + } BIT; +} volatile I2C_FILTER_REG; + +/** + * @brief Define the I2C register structure + */ +typedef struct { + I2C_MODE_REG I2C_MODE; /**< I2C mode configuration register, Offset address: 0x0000U. */ + I2C_SCL_CFG_REG I2C_SCL_CFG; /**< I2C SCL high/low level time register, Offset address: 0x0004U. */ + I2C_SDA_CFG_REG I2C_SDA_CFG; /**< I2C SDA timing configuration register, Offset address: 0x0008U. */ + I2C_OWN_ADDR_REG I2C_OWN_ADDR; /**< I2C slave address configuration register, + Offset address: 0x000CU. */ + XMB_DEV_ADDR_REG XMB_DEV_ADDR; /**< I2C SMBus PMBus Device Dedicated Address Configuration register, + Offset address: 0x0010U. */ + unsigned char space0[4]; + I2C_RX_ADDR_REG I2C_RX_ADDR; /**< Address received by the I2C slave, R/W bit register, + Offset address: 0x0018U. */ + unsigned char space1[4]; + I2C_TX_FIFO_REG I2C_TX_FIFO; /**< I2C TX FIFO register, Offset address: 0x0020U. */ + I2C_RX_FIFO_REG I2C_RX_FIFO; /**< I2C_RX_FIFO register, Offset address: 0x0024U. */ + unsigned char space2[160]; + I2C_TX_WATERMARK_REG I2C_TX_WATERMARK; /**< I2C TX threshold register, Offset address: 0x00C8U. */ + I2C_RX_WATERMARK_REG I2C_RX_WATERMARK; /**< I2C RX threshold register, Offset address: 0x00CCU. */ + I2C_CTRL1_REG I2C_CTRL1; /**< I2C control register 1, Offset address: 0x00D0U. */ + I2C_CTRL2_REG I2C_CTRL2; /**< I2C control register 2, Offset address: 0x00D4U. */ + I2C_FIFO_STAT_REG I2C_FIFO_STAT; /**< I2C FIFO status register, Offset address: 0x00D8U. */ + I2C_FSM_STAT_REG I2C_FSM_STAT; /**< I2C state machine status register, Offset address: 0x00DCU. */ + I2C_INTR_RAW_REG I2C_INTR_RAW; /**< I2C raw interrupt register, Offset address: 0x00E0U. */ + I2C_INTR_EN_REG I2C_INTR_EN; /**< I2C interrupt enable register, Offset address: 0x00E4U. */ + I2C_INTR_STAT_REG I2C_INTR_STAT; /**< I2C interrupt status register, Offset address: 0x00E8U. */ + unsigned char space3[20]; + I2C_VERSION_REG I2C_VERSION; /**< I2C version number register, Offset address: 0x0100U. */ + I2C_SCL_TIMEOUT_REG I2C_SCL_TIMEOUT; /**< I2C SCL timeout threshold register, Offset address: 0x0104U. */ + I2C_BUS_FREE_REG I2C_BUS_FREE; /**< I2C bus idle threshold register, Offset address: 0x0108U. */ + I2C_FILTER_REG I2C_FILTER; /**< I2C SDA and SCL filtering configuration register, + Offset address: 0x010CU. */ +} volatile I2C_RegStruct; +/** + * @} + */ + +/* Parameter check definition-------------------------------------------*/ +/** + * @brief Check I2C function mode selection. + * @param functionMode I2C function mode type. + * @retval true + * @retval false + */ +static inline bool IsI2cFunctionMode(I2C_ModeSelectType functionMode) +{ + return (functionMode == I2C_MODE_SELECT_NONE || + functionMode == I2C_MODE_SELECT_MASTER_ONLY || + functionMode == I2C_MODE_SELECT_SLAVE_ONLY || + functionMode == I2C_MODE_SELECT_MASTER_SLAVE); +} + +/** + * @brief Check address mode selection. + * @param addrMode I2C instance + * @retval true + * @retval false + */ +static inline bool IsI2cAddressMode(I2C_AddressMode addrMode) +{ + return (addrMode == I2C_7_BITS || + addrMode == I2C_10_BITS); +} + +/** + * @brief Check i2c sda hold time. + * @param sdaHoldTime I2C instance + * @retval true + * @retval false + */ +static inline bool IsI2cSdaHoldTime(unsigned int sdaHoldTime) +{ + return (sdaHoldTime <= 0xFFFF); /* SdaHoldTime value is 0 to 0xFFFF */ +} + +/** + * @brief Check I2C general call mode. + * @param generalCallMode I2C general call mode. + * @retval true + * @retval false + */ +static inline bool IsI2cGeneralCallMode(unsigned int generalCallMode) +{ + return (generalCallMode == BASE_CFG_ENABLE || + generalCallMode == BASE_CFG_DISABLE); +} + +/** + * @brief Check I2C lit end mode. + * @param litEnd I2C lit end mode. + * @retval true + * @retval false + */ +static inline bool IsI2cLitEndMode(unsigned int litEnd) +{ + return (litEnd == BASE_CFG_ENABLE || + litEnd == BASE_CFG_DISABLE); +} + +/** + * @brief Check I2C scl stretch Disable mode. + * @param sclStretchDisable I2C scl stretch Disable mode. + * @retval true + * @retval false + */ +static inline bool IsI2cSclStretchDisableMode(unsigned int sclStretchDisable) +{ + return (sclStretchDisable == BASE_CFG_ENABLE || + sclStretchDisable == BASE_CFG_DISABLE); +} + +/** + * @brief Check i2c own address. + * @param ownAddress I2C own address. + * @retval true + * @retval false + */ +static inline bool IsI2cOwnAddressOrMask(unsigned int ownAddress) +{ + return (ownAddress <= XMBUS_OWN_ADDRESS_MASK); /* Own address value is 0 to 0x3FF */ +} + +/** + * @brief Check XMBus address. + * @param xmbusAddress XMBus address. + * @retval true + * @retval false + */ +static inline bool IsXMBusAddressOrMask(unsigned int xmbusAddress) +{ + return (xmbusAddress <= XMBUS_OWN_ADDRESS_MASK); /* XMBus address value is 0 to 0x3FF */ +} + +/** + * @brief Check XMBus address Enable. + * @param xmbusAddress XMBus address. + * @retval true + * @retval false + */ +static inline bool IsXMBusAddressEnable(unsigned int slaveOwnXmbAddressEnable) +{ + return (slaveOwnXmbAddressEnable == BASE_CFG_ENABLE || slaveOwnXmbAddressEnable == BASE_CFG_DISABLE); +} + +/** + * @brief Check i2c SDA and SCL Glitch Filtering Time Configuration. + * @param spikeFilterTime I2C SDA and SCL Glitch Filtering Time. + * @retval true + * @retval false + */ +static inline bool IsI2cSpikeFilterTime(unsigned int spikeFilterTime) +{ + return (spikeFilterTime <= 0xF); /* The spikeFilterTime value is 0 to 0xF */ +} + + +/** + * @brief Check i2c freq. + * @param freq I2C freq + * @retval true + * @retval false + */ +static inline bool IsI2cFreq(unsigned int freq) +{ + return (freq > 0); +} + +/** + * @brief Check i2c ignore ack flag. + * @param ignoreAckFlag I2C ignore ack flag. + * @retval true + * @retval false + */ +static inline bool IsI2cIgnoreAckFlag(unsigned int ignoreAckFlag) +{ + return (ignoreAckFlag == I2C_IGNORE_NAK_ENABLE || + ignoreAckFlag == I2C_IGNORE_NAK_DISABLE); +} + +/** + * @brief Check i2c tx water mark. + * @param txWaterMark I2C tx water mark. + * @retval true + * @retval false + */ +static inline bool IsI2cTxWaterMark(unsigned int txWaterMark) +{ + return (txWaterMark <= 0xF); /* The txWaterMark value is 0 to 0xF */ +} + +/** + * @brief Check i2c rx water mark. + * @param rxWaterMark I2C rx water mark. + * @retval true + * @retval false + */ +static inline bool IsI2cRxWaterMark(unsigned int rxWaterMark) +{ + return (rxWaterMark <= 0xF); /* The rxWaterMark value is 0 to 0xF */ +} + +/** + * @brief Check i2c DMA Operation type. + * @param mode I2C DMA Operation type. + * @retval true + * @retval false + */ +static inline bool IsI2CDmaOperationType(I2C_DmaOperationType mode) +{ + return (mode == I2C_DMA_OP_NONE || + mode == I2C_DMA_OP_WRITE || + mode == I2C_DMA_OP_READ || + mode == I2C_DMA_OP_WRITE_READ); +} + +/** + * @brief Check i2c set one bit value. + * @param value value is set. + * @retval true + * @retval false + */ +static inline bool IsI2cSetOneBitValue(unsigned int value) +{ + return (value == BASE_CFG_UNSET || value == BASE_CFG_SET); +} + +/** + * @brief Check i2c scl timeout value. + * @param time the value of scl time out. + * @retval true + * @retval false + */ +static inline bool IsI2cSclTimoutValue(unsigned int time) +{ + return (time <= 0x7FFFFF); /* The i2c scl timeout max value is 0x7FFFFF. */ +} + +/** + * @brief Check i2c bus free time value. + * @param time the value of bus free time. + * @retval true + * @retval false + */ +static inline bool IsI2cBusFreeTimeValue(unsigned int time) +{ + return (time <= 0xFFFF); /* The i2c bus free time max value is 0xFFFF. */ +} + +/** + * @brief Check i2c data transfer sequence value. + * @param arg data transfer sequence value. + * @retval true + * @retval false + */ +static inline bool IsI2cDataTransferSequence(I2C_DataTransferSequenceType arg) +{ + return (arg == I2C_BIG_BIT_FIRST || arg == I2C_LITTLE_BIT_FIRST); +} + +/** + * @brief Check i2c clock stretching enumeration value. + * @param arg clock stretching enumeration value. + * @retval true + * @retval false + */ +static inline bool IsI2cClockStretchValue(I2C_ClockStretchType arg) +{ + return (arg == I2C_CLOCK_STRETCH_ENABLE || arg == I2C_CLOCK_STRETCH_DISABLE); +} + +/** + * @brief Check i2c SCL low-level timeout value. + * @param sclLowTimeout SCL low-level timeout value. + * @retval true + * @retval false + */ +static inline bool IsI2cSclLowTimeout(unsigned int sclLowTimeout) +{ + return (sclLowTimeout <= 0x7FFFFF); /* The SCL low-level timeout upper limit is 0x7FFFFF. */ +} + +/** + * @brief Check i2c SDA delay time. + * @param sdaDelayTime The value of SDA delay time. + * @retval true + * @retval false + */ +static inline bool IsI2cSdaDelayTime(unsigned int sdaDelayTime) +{ + return (sdaDelayTime <= 0x0F); /* The SDA delay time upper limit is 0x0F. */ +} + +/** + * @brief Check i2c bus idle threshold value. + * @param busFreeTime bus idle threshold value. + * @retval true + * @retval false + */ +static inline bool IsI2cBusFreeTime(unsigned int busFreeTime) +{ + return (busFreeTime <= 0xFFFF); /* The SCL bus idle threshold is 0xFFFF. */ +} + +/** + * @brief DCL I2C mode function set. + * @param i2cx I2C register base address. + * @param function I2C mode function + * @retval None. + */ +static inline void DCL_I2C_SetFunction(I2C_RegStruct *i2cx, unsigned int function) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + I2C_ASSERT_PARAM(IsI2cFunctionMode(function)); + i2cx->I2C_MODE.BIT.mst_slv_function = function; +} + +/** + * @brief DCL I2C mode function get. + * @param i2cx I2C register base address. + * @retval I2C mode function. + */ +static inline unsigned int DCL_I2C_GetFunction(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_MODE.BIT.mst_slv_function; +} + +/** + * @brief DCL I2C endian set. + * @param i2cx I2C register base address. + * @param endian data transfer sequence enumeration value. + * @retval None. + */ +static inline void DCL_I2C_SetEndian(I2C_RegStruct *i2cx, I2C_DataTransferSequenceType endian) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + I2C_PARAM_CHECK_NO_RET(IsI2cDataTransferSequence(endian)); + i2cx->I2C_MODE.BIT.lit_end = endian; +} + +/** + * @brief DCL I2C endian get. + * @param i2cx I2C register base address. + * @retval I2C endian. + */ +static inline unsigned int DCL_I2C_GetEndian(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_MODE.BIT.lit_end; +} + +/** + * @brief DCL I2C enable PEC. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_PECEnable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_MODE.BIT.xmb_pec_en = BASE_CFG_ENABLE; +} + +/** + * @brief DCL I2C disable PEC. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_PECDisable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_MODE.BIT.xmb_pec_en = BASE_CFG_DISABLE; +} + +/** + * @brief DCL I2C PEC status get. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline unsigned int DCL_I2C_GetPECStatus(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_MODE.BIT.xmb_pec_en; +} + +/** + * @brief DCL I2C enable ignore rack mode. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_IgnoreRackModeEnable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_MODE.BIT.rack_mode = I2C_IGNORE_NAK_ENABLE; +} + +/** + * @brief DCL I2C disable ignore rack mode. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_IgnoreRackModeDisable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_MODE.BIT.rack_mode = I2C_IGNORE_NAK_DISABLE; +} + +/** + * @brief DCL I2C enable scl stretch function. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_SclStrechEnable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_MODE.BIT.scl_stretch_disable = BASE_CFG_DISABLE; +} + +/** + * @brief DCL I2C disable scl stretch function. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_SclStrechDisable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_MODE.BIT.scl_stretch_disable = BASE_CFG_ENABLE; +} + +/** + * @brief DCL Configuring i2c SDA Hold Time. + * @param i2cx I2C register base address. + * @param sdaHoldTime Sda hold time. + * @retval None. + */ +static inline void DCL_I2C_SetSdaHoldDuration(I2C_RegStruct *i2cx, unsigned short sdaHoldTime) +{ + unsigned int glbReg; + unsigned int temp; + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + /* Read the entire register and write it back. */ + temp = ((unsigned int)sdaHoldTime) << I2C_SDA_HOLD_DURATION_POS; + glbReg = (i2cx->I2C_SDA_CFG.reg & 0xF) | temp; + i2cx->I2C_SDA_CFG.reg = glbReg; +} + +/** + * @brief Get DCL Configuring i2c SDA Hold Time. + * @param i2cx I2C register base address. + * @retval Sda hold time, 0-65535. + */ +static inline int DCL_I2C_GetSdaHoldDuration(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return ((i2cx->I2C_SDA_CFG.reg >> I2C_SDA_HOLD_DURATION_POS) & 0xFFFF); /* The mask of sda hold time is 0xFFFF. */ +} + +/** + * @brief DCL Configuring i2c SDA delay Time. + * @param i2cx I2C register base address. + * @param delay Sda delay time. + * @retval None. + */ +static inline void DCL_I2C_SetSdaDelayTime(I2C_RegStruct *i2cx, unsigned delay) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + I2C_PARAM_CHECK_NO_RET(IsI2cSdaDelayTime(delay)); + i2cx->I2C_SDA_CFG.BIT.sda_delay_time = delay; +} + +/** + * @brief DCL Get i2c SDA delay Time. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline unsigned int DCL_I2C_GetSdaDelayTime(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_SDA_CFG.BIT.sda_delay_time; +} + +/** + * @brief DCL Configuring i2c SCL High Hold Time. + * @param i2cx I2C register base address. + * @param sclHighTime Scl high hold time. + * @retval None. + */ +static inline void DCL_I2C_SetHighDuration(I2C_RegStruct *i2cx, unsigned short sclHighTime) +{ + unsigned int tempReg; + unsigned int temp; + + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + tempReg = i2cx->I2C_SCL_CFG.reg; + /* Read the entire register and write it back. */ + temp = ((unsigned int)sclHighTime) << I2C_SCL_HIGH_TIME_POS; + tempReg = (i2cx->I2C_SCL_CFG.reg & I2C_SCL_LOW_TIME_MASK) | temp; + i2cx->I2C_SCL_CFG.reg = tempReg; +} + +/** + * @brief DCL get i2c SCL High Hold Time. + * @param i2cx I2C register base address. + * @retval Scl high hold time,0-65535. + */ +static inline int DCL_I2C_GetHighDuration(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return ((i2cx->I2C_SCL_CFG.reg >> I2C_SCL_HIGH_TIME_POS) & 0xFFFF); /* The mask of scl high hold time is 0xFFFF. */ +} + +/** + * @brief DCL Configuring i2c SCL low Hold Time. + * @param i2cx I2C register base address. + * @param sclLowTime The value of I2C SCL low time. + * @retval None. + */ +static inline void DCL_I2C_SetLowDuration(I2C_RegStruct *i2cx, unsigned short sclLowTime) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_SCL_CFG.BIT.scl_low_time = sclLowTime; +} + +/** + * @brief DCL Get i2c SCL low Hold Time. + * @param i2cx I2C register base address. + * @retval Scl low hold time,0-65535. + */ +static inline int DCL_I2C_GetLowDuration(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_SCL_CFG.BIT.scl_low_time; +} + +/** + * @brief DCL Set I2C owner Address. + * @param i2cx I2C register base address. + * @param ownAddr Slave address + * @retval None. + */ +static inline void DCL_I2C_SetOwnAddr(I2C_RegStruct *i2cx, unsigned int ownAddr) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + I2C_ASSERT_PARAM(IsI2cOwnAddressOrMask(ownAddr)); + i2cx->I2C_OWN_ADDR.BIT.own_address = ownAddr; +} + +/** + * @brief DCL Get I2C owner Address. + * @param i2cx I2C register base address. + * @retval I2C owner address. + */ +static inline unsigned int DCL_I2C_GetOwnAddr(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_OWN_ADDR.BIT.own_address; +} + +/** + * @brief DCL Set I2C owner address mask. + * @param i2cx I2C register base address. + * @param ownAddrMask The maske of I2C slave address. + * @retval None. + */ +static inline void DCL_I2C_SetOwnMaskAddr(I2C_RegStruct *i2cx, unsigned int ownAddrMask) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + I2C_ASSERT_PARAM(IsI2cOwnAddressOrMask(ownAddrMask)); + i2cx->I2C_OWN_ADDR.BIT.own_address_mask = ownAddrMask; +} + +/** + * @brief DCL Set I2C owner address mask. + * @param i2cx I2C register base address. + * @retval I2C owner address mask. + */ +static inline unsigned int DCL_I2C_GetOwnMaskAddr(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_OWN_ADDR.BIT.own_address_mask; +} + +/** + * @brief DCL Set I2C 10bit slave enable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_10BitSlaveEnable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_OWN_ADDR.BIT.i2c_10bit_slave_en = BASE_CFG_ENABLE; +} + +/** + * @brief DCL Set I2C 10bit slave disable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_10BitSlaveDisable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_OWN_ADDR.BIT.i2c_10bit_slave_en = BASE_CFG_DISABLE; +} + +/** + * @brief DCL Set XMBus Address. + * @param i2cx I2C register base address. + * @param xmbusAddr The address is used for I2C, SMBus and PMBus Device. + * @retval None. + */ +static inline void DCL_I2C_SetXMBusAddr(I2C_RegStruct *i2cx, unsigned int xmbusAddr) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + I2C_ASSERT_PARAM(IsXMBusAddressOrMask(xmbusAddr)); + i2cx->XMB_DEV_ADDR.BIT.xmb_address = xmbusAddr; +} + +/** + * @brief DCL Get XMBus Address. + * @param i2cx I2C register base address. + * @retval The address of I2C, SMBus and PMBus Device. + */ +static inline unsigned int DCL_I2C_GetXMBusAddr(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->XMB_DEV_ADDR.BIT.xmb_address; +} + +/** + * @brief DCL Set xmbus address mask. + * @param i2cx I2C register base address. + * @param xmbusAddrMask The maske of xmbus device address. + * @retval None. + */ +static inline void DCL_I2C_SetXMBusMaskAddr(I2C_RegStruct *i2cx, unsigned int xmbusAddrMask) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + I2C_ASSERT_PARAM(IsXMBusAddressOrMask(xmbusAddrMask)); + i2cx->XMB_DEV_ADDR.BIT.xmb_address_mask = xmbusAddrMask; +} + +/** + * @brief DCL Get XMBus device address mask. + * @param i2cx I2C register base address. + * @retval XMBus device address mask. + */ +static inline unsigned int DCL_I2C_GetXMBusMaskAddr(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->XMB_DEV_ADDR.BIT.xmb_address_mask; +} + +/** + * @brief DCL Set XMBus address enable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_XMBusAddressEnable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->XMB_DEV_ADDR.BIT.xmb_address_en = BASE_CFG_ENABLE; +} + +/** + * @brief DCL Set XMBus address disable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_XMBusAddressDisable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->XMB_DEV_ADDR.BIT.xmb_address_en = BASE_CFG_DISABLE; +} + +/** + * @brief DCL Set SMBus host notify enable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_SMBusHostNotifyEnable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->XMB_DEV_ADDR.BIT.smb_host_notify_en = BASE_CFG_ENABLE; +} + +/** + * @brief DCL Set SMBus host notify disable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_SMBusHostNotifyDisable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->XMB_DEV_ADDR.BIT.smb_host_notify_en = BASE_CFG_DISABLE; +} + +/** + * @brief DCL Set SMBus alert response enable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_SMBusAlertResponseEnable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->XMB_DEV_ADDR.BIT.smb_alert_response_en = BASE_CFG_ENABLE; +} + +/** + * @brief DCL Set SMBus SMBus alert response disable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_SMBusAlertResponseDisable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->XMB_DEV_ADDR.BIT.smb_alert_response_en = BASE_CFG_DISABLE; +} + +/** + * @brief DCL Set Receive SMBus device default address enable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_SMBusDevDefaultEnable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->XMB_DEV_ADDR.BIT.smb_dev_default_en = BASE_CFG_ENABLE; +} + +/** + * @brief DCL Set Receive SMBus device default address disable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_SMBusDevDefaultDisable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->XMB_DEV_ADDR.BIT.smb_dev_default_en = BASE_CFG_DISABLE; +} + +/** + * @brief DCL Set Receive PMBus Zone Read Address Enable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_PMBusZoneReadEnable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->XMB_DEV_ADDR.BIT.pmb_zone_read_en = BASE_CFG_ENABLE; +} + +/** + * @brief DCL Set Receive PMBus Zone Read Address Disable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_PMBusZoneReadDisable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->XMB_DEV_ADDR.BIT.pmb_zone_read_en = BASE_CFG_DISABLE; +} + +/** + * @brief DCL Set Receive PMBus Zone Write Address Enable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_PMBusZoneWriteEnable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->XMB_DEV_ADDR.BIT.pmb_zone_write_en = BASE_CFG_ENABLE; +} + +/** + * @brief DCL Set Receive PMBus Zone Write Address Disable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_PMBusZoneWriteDisable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->XMB_DEV_ADDR.BIT.pmb_zone_write_en = BASE_CFG_DISABLE; +} + +/** + * @brief DCL Set I2C start byte enable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_StartByteEnable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_OWN_ADDR.BIT.i2c_start_byte_en = BASE_CFG_ENABLE; +} + +/** + * @brief DCL Set I2C start byte disable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_StartByteDisable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_OWN_ADDR.BIT.i2c_start_byte_en = BASE_CFG_DISABLE; +} + +/** + * @brief DCL Set I2C device id enable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_DeviceIDEnable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_OWN_ADDR.BIT.i2c_device_id_en = BASE_CFG_ENABLE; +} + +/** + * @brief DCL Set I2C device id disable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_DeviceIDDisable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_OWN_ADDR.BIT.i2c_device_id_en = BASE_CFG_DISABLE; +} + +/** + * @brief DCL Set I2C general call enable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_GeneralCallEnable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_OWN_ADDR.BIT.i2c_general_call_en = BASE_CFG_ENABLE; +} + +/** + * @brief DCL Set I2C general call disable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_GeneralCallDisable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_OWN_ADDR.BIT.i2c_general_call_en = BASE_CFG_DISABLE; +} + +/** + * @brief Get the I2C RX received R/W Bits. + * @param i2cx I2C register base address. + * @retval The value of I2C RX received R/W Bits, 0: write, 1: read. + */ +static inline unsigned int DCL_I2C_GetRxReadOrWrite(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_RX_ADDR.BIT.rx_rw; +} + +/** + * @brief Get the I2C RX address. + * @param i2cx I2C register base address. + * @retval RX address. + */ +static inline unsigned int DCL_I2C_GetRxAddr(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_RX_ADDR.reg & 0x3FF; /* The mask of RX address is 0x3FF. */ +} + +/** + * @brief Set the I2C TX FIFO. + * @param i2cx I2C register base address. + * @param cmd I2C operation commands. + * @param data I2C operation data + * @retval None. + */ +static inline void DCL_I2C_SetTxFIFO(I2C_RegStruct *i2cx, I2C_CmdType cmd, unsigned char data) +{ + unsigned int temp; + + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + temp = (((unsigned int)cmd << I2C_TXFIFO_CMD_POS) & I2C_TXFIFO_CMD_MASK); + temp |= (((unsigned int)data << I2C_TXFIFO_WDATA_POS) & I2C_TXFIFO_WDATA_MASK); + i2cx->I2C_TX_FIFO.reg = temp; /* Set xommand and data */ +} + +/** + * @brief Get the I2C RX FIFO. + * @param i2cx I2C register base address. + * @retval RX FIFO data. + */ +static inline unsigned int DCL_I2C_GetRxFIFO(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_RX_FIFO.reg; +} + +/** + * @brief Set the I2C TX threshold. + * @param i2cx I2C register base address. + * @param waterMark I2C Tx threshold, 0-15. + * @retval None. + */ +static inline void DCL_I2C_SetTxWaterMark(I2C_RegStruct *i2cx, unsigned char waterMark) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + I2C_PARAM_CHECK_NO_RET(IsI2cTxWaterMark(waterMark)); + i2cx->I2C_TX_WATERMARK.BIT.tx_watermark = waterMark; +} + +/** + * @brief Get the I2C TX threshold. + * @param i2cx I2C register base address. + * @retval I2C tx threshold. + */ +static inline unsigned int DCL_I2C_GetTxWaterMark(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_TX_WATERMARK.BIT.tx_watermark; +} + +/** + * @brief Set the I2C RX threshold. + * @param i2cx I2C register base address. + * @param waterMark I2C Rx threshold, 0-15. + * @retval None. + */ +static inline void DCL_I2C_SetRxWaterMark(I2C_RegStruct *i2cx, unsigned char waterMark) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + I2C_PARAM_CHECK_NO_RET(IsI2cRxWaterMark(waterMark)); + i2cx->I2C_RX_WATERMARK.BIT.rx_watermark = waterMark; +} + +/** + * @brief Get the I2C RX threshold. + * @param i2cx I2C register base address. + * @retval I2C rx threshold. + */ +static inline int DCL_I2C_GetRxWaterMark(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_RX_WATERMARK.BIT.rx_watermark; +} + +/** + * @brief Set the I2C DMA mode. + * @param i2cx I2C register base address. + * @param mode I2C DMA operation mode. + * @retval None. + */ +static inline void DCL_I2C_SetDmaMode(I2C_RegStruct *i2cx, I2C_DmaOperationType mode) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + I2C_ASSERT_PARAM(IsI2CDmaOperationType(mode)); + i2cx->I2C_CTRL1.BIT.dma_operation = mode; +} + +/** + * @brief DCL Set Start I2C timing execution Enable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_SetMasterStartEnable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_CTRL1.BIT.mst_start = BASE_CFG_SET; +} + +/** + * @brief DCL Set Start I2C timing execution Disable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_SetMasterStartDisable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_CTRL1.BIT.mst_start = BASE_CFG_UNSET; +} + +/** + * @brief Get start and stop I2C timing status. + * @param i2cx I2C register base address. + * @retval start : 1, stop :0. + */ +static inline unsigned int DCL_I2C_GetStart(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_CTRL1.BIT.mst_start; +} + +/** + * @brief Rest Tx FIFO. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_ResetTxFIFO(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_CTRL1.BIT.rst_tx_fifo = BASE_CFG_SET; +} + +/** + * @brief Rest Rx FIFO. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_ResetRxFIFO(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_CTRL1.BIT.rst_rx_fifo = BASE_CFG_SET; +} + +/** + * @brief Set the SCL and SDA pins of the I2C to GPIO mode. + * @param i2cx I2C register base address. + * @param mode 0 disable,1 enable. + * @retval None. + */ +static inline void DCL_I2C_SetGpioMode(I2C_RegStruct *i2cx, unsigned char mode) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + I2C_ASSERT_PARAM(IsI2cSetOneBitValue(mode)); + i2cx->I2C_CTRL2.BIT.gpio_mode = mode; +} + +/** + * @brief Get the SCL and SDA pins of the I2C to GPIO mode. + * @param i2cx I2C register base address. + * @retval 0 or 1 + */ +static inline unsigned int DCL_I2C_GetGpioMode(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_CTRL2.BIT.gpio_mode; +} + +/** + * @brief Set the SDA output level. + * @param i2cx I2C register base address. + * @param level The sda output level. + * @retval 0 or 1. + */ +static inline void DCL_I2C_SetSdaLevel(I2C_RegStruct *i2cx, unsigned int level) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + I2C_ASSERT_PARAM(IsI2cSetOneBitValue(level)); + i2cx->I2C_CTRL2.BIT.force_sda = level; +} + +/** + * @brief Get the SDA output level. + * @param i2cx I2C register base address. + * @retval 0 or 1. + */ +static inline unsigned int DCL_I2C_GetSdaLevel(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_CTRL2.BIT.force_sda; +} + +/** + * @brief Set the SCL output level. + * @param i2cx I2C register base address. + * @param level The scl output level. + * @retval None. + */ +static inline void DCL_I2C_SetSclLevel(I2C_RegStruct *i2cx, unsigned int level) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + I2C_ASSERT_PARAM(IsI2cSetOneBitValue(level)); + i2cx->I2C_CTRL2.BIT.force_scl = level; +} + +/** + * @brief Get the SCL output level. + * @param i2cx I2C register base address. + * @retval 0 or 1. + */ +static inline unsigned int DCL_I2C_GetSclLevel(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_CTRL2.BIT.force_scl; +} + +/** + * @brief Get SMBus suspend_n_in level. + * @param i2cx I2C register base address. + * @retval 0 or 1. + */ +static inline unsigned int DCL_I2C_GetSMBusSuspendIn(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_CTRL2.BIT.smb_suspend_n_in; +} + +/** + * @brief Set SMBus suspend_n_out low level. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_SetSMBusSuspendOutLowLevel(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_CTRL2.BIT.smb_suspend_n_out = BASE_CFG_DISABLE; +} + +/** + * @brief Set SMBus suspend_n_out high level. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_SetSMBusSuspendOutHighLevel(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_CTRL2.BIT.smb_suspend_n_out = BASE_CFG_ENABLE; +} + +/** + * @brief Get SMBus suspend_n_out level. + * @param i2cx I2C register base address. + * @retval 0 or 1. + */ +static inline unsigned int DCL_I2C_GetSMBusSuspendOut(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_CTRL2.BIT.smb_suspend_n_out; +} + +/** + * @brief Set SMBus suspend_n_oe_n. + * @param i2cx I2C register base address. + * @param selcet The output value of SMBSUS#. + * @retval None. + */ +static inline void DCL_I2C_SetSMBusSuspendOe(I2C_RegStruct *i2cx, unsigned int selcet) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + I2C_ASSERT_PARAM(IsI2cSetOneBitValue(selcet)); + i2cx->I2C_CTRL2.BIT.smb_suspend_n_oe_n = selcet; +} + +/** + * @brief Get SMBus suspend_n_oe_n. + * @param i2cx I2C register base address. + * @retval 0 or 1. + */ +static inline unsigned int DCL_I2C_GetSMBusSuspendOe(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_CTRL2.BIT.smb_suspend_n_oe_n; +} + +/** + * @brief Get SMBus alert_n_in. + * @param i2cx I2C register base address. + * @retval 0 or 1. + */ +static inline unsigned int DCL_I2C_GetSMBusAlertIn(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_CTRL2.BIT.smb_alert_n_in; +} + +/** + * @brief Set SMBus alert_n_oe_n. + * @param i2cx I2C register base address. + * @param selcet The smbus alert set or unset. + * @retval None. + */ +static inline void DCL_I2C_SetSMBusAlertOe(I2C_RegStruct *i2cx, unsigned int selcet) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + I2C_ASSERT_PARAM(IsI2cSetOneBitValue(selcet)); + i2cx->I2C_CTRL2.BIT.smb_alert_n_oe_n = selcet; +} + +/** + * @brief Get SMBus alert_n_oe_n. + * @param i2cx I2C register base address. + * @retval The smbus alert value. + */ +static inline unsigned int DCL_I2C_GetSMBusAlertOe(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_CTRL2.BIT.smb_alert_n_oe_n; +} + +/** + * @brief Get the number of valid Tx FIFOs. + * @param i2cx I2C register base address. + * @retval Tx FIFO valid value. + */ +static inline unsigned int DCL_I2C_GetTxFIFOValidNum(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_FIFO_STAT.BIT.tx_fifo_vld_num; +} + +/** + * @brief Get the number of valid Rx FIFOs. + * @param i2cx I2C register base address. + * @retval Tx FIFO valid value. + */ +static inline unsigned int DCL_I2C_GetRxFIFOValidNum(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_FIFO_STAT.BIT.rx_fifo_vld_num; +} + +/** + * @brief Get the status of I2C bus. + * @param i2cx I2C register base address. + * @retval 0: bus busy, 1: bus free. + */ +static inline unsigned int DCL_I2C_GetI2cBusSatus(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_FSM_STAT.BIT.i2c_bus_free; +} + +/** + * @brief Clearing I2C raw interrupts. + * @param i2cx I2C register base address. + * @param cleanStatus Need to clean Raw status + * @retval None. + */ +static inline void DCL_I2C_CleanRawINT(I2C_RegStruct *i2cx, unsigned int cleanStatus) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_INTR_RAW.reg = cleanStatus; +} + +/** + * @brief Get I2C raw interrupts status. + * @param i2cx I2C register base address. + * @retval The value of I2C raw interrupts status. + */ +static inline unsigned int DCL_I2C_GetRawINTStatus(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_INTR_RAW.reg; +} + +/** + * @brief Set enable I2C interrupts. + * @param i2cx I2C register base address. + * @param enableSelect Need to set interrupt enable. + * @retval None. + */ +static inline void DCL_I2C_SetInterruptsEnable(I2C_RegStruct *i2cx, unsigned int enableSelect) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_INTR_EN.reg = enableSelect; +} + +/** + * @brief Get enable I2C interrupts. + * @param i2cx I2C register base address. + * @retval I2C interrupt enable value. + */ +static inline unsigned int DCL_I2C_GetInterruptsEnable(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_INTR_EN.reg; +} + +/** + * @brief Get I2C Interrupts Status. + * @param i2cx I2C register base address. + * @retval I2C interrupt status. + */ +static inline unsigned int DCL_I2C_GetInterruptsStatus(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_INTR_STAT.reg; +} + +/** + * @brief Get I2C version ID. + * @param i2cx I2C register base address. + * @retval I2C version ID. + */ +static inline unsigned int DCL_I2C_GetVersionID(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_VERSION.reg; +} + +/** + * @brief Set I2C SCL timeout. + * @param i2cx I2C register base address. + * @param timeout SCL low-level timeout configuration. + * @retval None. + */ +static inline void DCL_I2C_SetSclTimeout(I2C_RegStruct *i2cx, unsigned int timeout) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + I2C_ASSERT_PARAM(IsI2cSclTimoutValue(timeout)); + i2cx->I2C_SCL_TIMEOUT.reg = timeout; +} + +/** + * @brief Get I2C SCL timeout. + * @param i2cx I2C register base address. + * @retval I2C Scl timeout value. + */ +static inline unsigned int DCL_I2C_GetSclTimeout(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_SCL_TIMEOUT.BIT.scl_low_timeout; +} + +/** + * @brief I2C bus idle threshold configuration. + * @param i2cx I2C register base address. + * @param time The I2C bus idle threshold. + * @retval None. + */ +static inline void DCL_I2C_SetIdleThreshold(I2C_RegStruct *i2cx, unsigned int time) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + I2C_ASSERT_PARAM(IsI2cBusFreeTimeValue(time)); + i2cx->I2C_BUS_FREE.BIT.bus_free_time = time; +} + +/** + * @brief Get I2C bus idle threshold. + * @param i2cx I2C register base address. + * @retval I2C bus idle threshold. + */ +static inline unsigned int DCL_I2C_GetIdleThreshold(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_BUS_FREE.BIT.bus_free_time; +} + +/** + * @brief I2C filtering configuration. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_SetFilter(I2C_RegStruct *i2cx, unsigned int time) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + I2C_PARAM_CHECK_NO_RET(time <= 0xF); /* The maximum spike filter time is 0xF; */ + i2cx->I2C_FILTER.BIT.spike_filter_time = time; +} + +/** + * @brief Get I2C filtering configuration. + * @param i2cx I2C register base address. + * @retval I2C filtering configuration. + */ +static inline unsigned int DCL_I2C_GetFilter(const I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_FILTER.BIT.spike_filter_time; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* #ifndef McuMagicTag_I2C_IP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/i2c/src/i2c.c b/vendor/xinlingyu_92_3061M/Project/drivers/i2c/src/i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..8d3e8d6c21be55a250af7329557de3c107cab8bc --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/i2c/src/i2c.c @@ -0,0 +1,2037 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file i2c.c + * @author MCU Driver Team + * @brief I2C module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the I2C. + * + Initialization and de-initialization functions + * + Peripheral Control functions + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "i2c.h" + +/* Macro definitions ---------------------------------------------------------*/ +#define I2C_INTERFACE_INDEX_0 0 +#define I2C_INTERFACE_INDEX_1 1 +#define I2C_MAX_INDEX_NUM 2 + +#define I2C_MASTER_STATUS 0x00 +#define I2C_SLAVE_STATUS 0x01 + +#define I2C_MAX_FIFO_SIZE 16 +#define I2C_WAIT_TIMEOUT 0x400 +#define I2C_MAX_DEV_ADDR 0x3FF + +#define I2C_OPERATION_WRITE 0 +#define I2C_OPERATION_READ 1 + +#define I2C_SEND_ADDR_STATUS_NONE 0 +#define I2C_SEND_ADDR_STATUS_WRITE 1 +#define I2C_SEND_ADDR_STATUS_READ 2 + +#define I2C_DATA_OPT_SETP_PRE 1 +#define I2C_DATA_OPT_SETP_NORMAL 2 + +/* Enable scl_low_timeout\mst_cmd_done\arb_lost\tx_fifo_not_full\rx_fifo_not_empty\mst_rx_ack_unmatch */ +#define I2C_CFG_INTERRUPT_MASTER_RX 0x3843 + +/* Enable scl_low_timeout\mst_cmd_done\arb_lost\tx_fifo_not_full\mst_rx_ack_unmatch */ +#define I2C_CFG_INTERRUPT_MASTER_TX 0x3841 + +/* Enable slv_addr_match_int\slv_rx_ack_unmatch_int\stop_det_int */ +#define I2C_CFG_INTERRUPT_SLAVE 0x300200 +#define I2C_TICK_MS_DIV 1000 + +#define I2C_INTR_RAW_SLAVE_ADDR_MATCH_MASK (0x1 << 21) +#define I2C_INTR_RAW_SLAVE_ACK_UNMATCH_MASK (0x1 << 20) +#define I2C_INTR_RAW_SLAVE_PEC_CHECK_FAIL_MASK (0x1 << 19) +#define I2C_INTR_RAW_MASTER_PEC_CHECK_FAIL_MASK (0x1 << 18) +#define I2C_INTR_RAW_SLAVE_CMD_INT1_MASK (0x1 << 17) +#define I2C_INTR_RAW_MASTER_CMD_INT1_MASK (0x1 << 16) +#define I2C_INTR_RAW_SMB_SUSPEND_MASK (0x1 << 15) +#define I2C_INTR_RAW_SMB_ALERT_MASK (0x1 << 14) +#define I2C_INTR_RAW_SCL_LOW_TIMEOUT_MASK (0x1 << 13) +#define I2C_INTR_RAW_ALL_CMD_DONE_MASK (0x1 << 12) +#define I2C_INTR_RAW_ARB_LOST_MASK (0x1 << 11) +#define I2C_INTR_RAW_START_DET_MASK (0x1 << 10) +#define I2C_INTR_RAW_STOP_DET_MASK (0x1 << 9) +#define I2C_INTR_RAW_TX_DATA_REQUEST_MASK (0x1 << 8) +#define I2C_INTR_RAW_RX_DATA_READY_MASK (0x1 << 7) +#define I2C_INTR_RAW_TX_FIFO_NOT_FULL_MASK (0x1 << 6) +#define I2C_INTR_RAW_TX_FIFO_EMPTY_MASK (0x1 << 5) +#define I2C_INTR_RAW_TX_LE_WATERMARK_MASK (0x1 << 4) +#define I2C_INTR_RAW_RX_FIFO_FULL_MASK (0x1 << 3) +#define I2C_INTR_RAW_RX_GE_WATERMARK_MASK (0x1 << 2) +#define I2C_INTR_RAW_RX_FIFO_NOT_EMPTY_MASK (0x1 << 1) +#define I2C_INTR_RAW_ACK_BIT_UNMATCH_MASK (0x1 << 0) + +#define I2C_10BIT_SLAVE_READ_ADDR_MASK (0xFEFF0000) +#define I2C_10BIT_SLAVE_WRITE_ADDR_MASK (0x0000FEFF) +#define I2C_10BIT_SLAVE_READ_OPT_MASK (0x01000000) + +#define I2C_7BIT_SLAVE_READ_ADDR_MASK (0x00FE0000) +#define I2C_7BIT_SLAVE_WRITE_ADDR_MASK (0x000000FE) +#define I2C_7BIT_SLAVE_READ_OPT_MASK (0x00010000) + +#define I2C_SLAVE_WRITE_ADDR_POS 8 +#define I2C_SLAVE_READ_FIX_ADDR_POS 24 +#define I2C_SLAVE_READ_DEV_ADDR_POS 16 +#define I2C_SLAVE_ADDR_MASK 0xFF +#define I2C_10BIT_SLAVE_ADDR_POS 16 + +#define HIGH_HOLD_TIME_POS 16 +#define HIGH_HOLD_TIME_MASK 0xFFFF0000 +#define LOW_HOLD_TIME_MASK 0x0000FFFF + +#define DMA_RX_CHANNEL_POS 8 +#define DMA_CHANNEL_MASK 0x00FF + +#define COMMAND_ALL_DONE 0 +#define I2C_BUS_IS_FREE 1 +#define SLAVE_ADDRESS_MATCH 2 +#define TX_FIFO_NOT_FULL 3 +#define RX_FIFO_NOT_EMPTY 4 + +#define I2C_FREQ_HIGH_PARAMTER 8 +#define I2C_FREQ_LOW_PARAMTER 9 +#define I2C_ERROR_BIT_MASK 0x100801 /* slv_rx_ack_unmatch\arb_lost\mst_rx_ack_unmatch */ +#define I2C_SCL_LOW_TIMEOUT_MASK 0x2000 + +static BASE_StatusType DmaMasterReadData(I2C_Handle *handle, unsigned int size, unsigned int index); +static BASE_StatusType DmaMasterWriteData(I2C_Handle *handle, unsigned int size, unsigned int index); +static BASE_StatusType DmaSlaveReadData(I2C_Handle *handle, unsigned int size, unsigned int index); +static BASE_StatusType DmaSlaveWriteData(I2C_Handle *handle, unsigned int size, unsigned int index); + +typedef struct { + unsigned int txReadCmdCnt; + /* The lower 16 bits are used for write operations, + and the high 16 bits are used for read operations. */ + unsigned int slaveAddress; + unsigned int sendAddressStatus; +} I2C_InternalConfigParam; + +/* Some global parameters used for module internal operations */ +static volatile I2C_InternalConfigParam g_internalConfigParam[I2C_MAX_INDEX_NUM] = {0}; +static volatile unsigned int g_internalTxBuffDMA[I2C_MAX_INDEX_NUM][I2C_ONCE_TRANS_MAX_NUM] = {0}; +static volatile unsigned int g_dmaTransferSize = 0; +/** + * @brief Check all initial configuration parameters. + * @param handle I2C handle. + * @param clockFreq I2C work clock freq; + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType CheckAllInitParameters(I2C_Handle *handle, unsigned int clockFreq) +{ + /* Check the configuration of basic function parameters. */ + I2C_PARAM_CHECK_WITH_RET(IsI2cFunctionMode(handle->functionMode), BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(IsI2cAddressMode(handle->addrMode), BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(IsI2cSdaHoldTime(handle->sdaHoldTime), BASE_STATUS_ERROR); + /* Check whether the I2C freq is valid. */ + I2C_PARAM_CHECK_WITH_RET(IsI2cFreq(handle->freq), BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET((clockFreq > 0), BASE_STATUS_ERROR); + + if (handle->freq > clockFreq) { + return BASE_STATUS_ERROR; + } + /* Check the configuration of basic function parameters. */ + I2C_PARAM_CHECK_WITH_RET(IsI2cIgnoreAckFlag(handle->ignoreAckFlag), BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(IsI2cTxWaterMark(handle->txWaterMark), BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(IsI2cRxWaterMark(handle->rxWaterMark), BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(IsI2cSpikeFilterTime(handle->handleEx.spikeFilterTime), BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(IsI2cSdaDelayTime(handle->handleEx.sdaDelayTime), BASE_STATUS_ERROR); + + /* Checking the own address and generalCall parameter enable when is used as slave. */ + if (handle->functionMode == I2C_MODE_SELECT_SLAVE_ONLY || handle->functionMode == I2C_MODE_SELECT_MASTER_SLAVE) { + I2C_PARAM_CHECK_WITH_RET(IsI2cOwnAddressOrMask(handle->slaveOwnAddress), BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(IsI2cGeneralCallMode(handle->generalCallMode), BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(IsXMBusAddressEnable(handle->handleEx.slaveOwnXmbAddressEnable), BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(IsXMBusAddressOrMask(handle->handleEx.slaveOwnXmbAddress), BASE_STATUS_ERROR); + } + return BASE_STATUS_OK; +} + +/** + * @brief Configuring the I2C Slave Device Address. + * @param handle I2C handle. + * @param devAddr Slave device address + * @retval None. + */ +static void SetSlaveDevAddr(I2C_Handle *handle, const unsigned int devAddr) +{ + unsigned int addr; + + if (handle->addrMode == I2C_10_BITS) { + /* The upper 16 bits are the read operation address, and the lower 16 bits are the write operation address. */ + addr = (((devAddr << 16) & I2C_10BIT_SLAVE_READ_ADDR_MASK) | I2C_10BIT_SLAVE_READ_OPT_MASK) | + (devAddr & I2C_10BIT_SLAVE_WRITE_ADDR_MASK); + } else { + /* The upper 16 bits are the read operation address, and the lower 16 bits are the write operation address. */ + addr = (((devAddr << 16) & I2C_7BIT_SLAVE_READ_ADDR_MASK) | I2C_7BIT_SLAVE_READ_OPT_MASK) | + (devAddr & I2C_7BIT_SLAVE_WRITE_ADDR_MASK); + } + + if (handle->baseAddress == I2C0) { + g_internalConfigParam[I2C_INTERFACE_INDEX_0].slaveAddress = addr; + } else if (handle->baseAddress == I2C1) { + g_internalConfigParam[I2C_INTERFACE_INDEX_1].slaveAddress = addr; + } +} + +/** + * @brief I2C Bus clear. + * @param handle I2C handle. + * @retval None. + */ +static void I2cBusClear(I2C_Handle *handle) +{ + handle->state = I2C_STATE_READY; + handle->baseAddress->I2C_MODE.BIT.mst_slv_function = I2C_STATE_RESET; + /* Clears interrupts and disables interrupt reporting to + facilitate switching between different working modes. */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + + /* Set the SCL and SDA pins of the I2C to GPIO mode. */ + handle->baseAddress->I2C_CTRL2.BIT.gpio_mode = BASE_CFG_ENABLE; + handle->baseAddress->I2C_CTRL2.BIT.force_scl = BASE_CFG_ENABLE; + handle->baseAddress->I2C_CTRL2.BIT.force_sda = BASE_CFG_ENABLE; + /* The device that controls the bus to be pulled down needs to release the bus within the 9 clocks. */ + for (unsigned int index = 0; index < 9; index++) { + handle->baseAddress->I2C_CTRL2.BIT.force_scl = BASE_CFG_UNSET; + BASE_FUNC_DELAY_US(5); /* The I2C timing is required. The delay is about 5 μs. */ + handle->baseAddress->I2C_CTRL2.BIT.force_scl = BASE_CFG_SET; + BASE_FUNC_DELAY_US(5); /* The I2C timing is required. The delay is about 5 μs. */ + } + handle->baseAddress->I2C_CTRL2.BIT.force_scl = BASE_CFG_ENABLE; + handle->baseAddress->I2C_CTRL2.BIT.force_sda = BASE_CFG_ENABLE; + /* I2C start */ + handle->baseAddress->I2C_CTRL2.BIT.force_sda = BASE_CFG_UNSET; + BASE_FUNC_DELAY_US(10); /* The I2C timing is required. The delay is about 10 μs. */ + /* I2C stop */ + handle->baseAddress->I2C_CTRL2.BIT.force_sda = BASE_CFG_SET; + handle->baseAddress->I2C_CTRL2.BIT.gpio_mode = BASE_CFG_DISABLE; /* Exit the I2C GPIO mode. */ +} + +/** + * @brief Setting Error Handling. + * @param handle I2C handle. + * @retval None. + */ +static void SetErrorHandling(I2C_Handle *handle) +{ + /* If the low level times out, the I2C bus is cleared and the bus is expected to be released. */ + if (handle->baseAddress->I2C_INTR_RAW.BIT.scl_low_timeout_raw == BASE_CFG_ENABLE) { + I2cBusClear(handle); + handle->baseAddress->I2C_INTR_RAW.BIT.scl_low_timeout_raw = BASE_CFG_ENABLE; + } + + if (handle->errorCode != BASE_STATUS_OK && handle->userCallBack.ErrorCallback != NULL) { + handle->userCallBack.ErrorCallback(handle); + } + /* Clears interrupts and disables interrupt reporting to + facilitate switching between different working modes. */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + + handle->state = I2C_STATE_READY; +} + +/** + * @brief Item is checked for readiness. + * @param handle I2C handle. + * @param checkItem The item to be checked. + * @param opt Read or write flag. + * @retval false, item is not ready. true, item is ready. + */ +static unsigned int CheckItemStatus(I2C_Handle *handle, unsigned int checkItem, unsigned int opt) +{ + unsigned int ret = 0; + unsigned int tempStatusValue = 0; + switch (checkItem) { + case COMMAND_ALL_DONE: + /* The 0x1200 is the bit of mst_cmd_done_raw and stop_det_raw. */ + tempStatusValue = (handle->baseAddress->I2C_INTR_RAW.reg & 0x1200); /* Check the I2C is all command done. */ + ret = tempStatusValue; + break; + case I2C_BUS_IS_FREE: + /* The I2C bus is free. */ + ret = handle->baseAddress->I2C_FSM_STAT.BIT.i2c_bus_free; + break; + case SLAVE_ADDRESS_MATCH: + /* Slave servers are matched */ + tempStatusValue = (handle->baseAddress->I2C_RX_ADDR.BIT.rx_rw == opt) ? 1 : 0; + tempStatusValue |= handle->baseAddress->I2C_INTR_RAW.BIT.slv_addr_match_raw; + ret = tempStatusValue; + break; + case TX_FIFO_NOT_FULL: + /* Tx fifo is not full. */ + ret = ((handle->baseAddress->I2C_FIFO_STAT.BIT.tx_fifo_vld_num < I2C_MAX_FIFO_SIZE)) ? 1 : 0; + break; + case RX_FIFO_NOT_EMPTY: + /* Rx fifo is not empty. */ + ret = handle->baseAddress->I2C_FIFO_STAT.BIT.rx_fifo_vld_num; + break; + default: + break; + } + return ret; +} + +/** + * @brief Wait for the item status to be ready. + * @param handle I2C handle. + * @param checkItem The item to be checked. + * @param opt Read or write flag. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType WaitStatusReady(I2C_Handle *handle, unsigned int checkItem, unsigned int opt) +{ + unsigned int preTick = DCL_SYSTICK_GetTick(); + unsigned int curTick; + unsigned long long delta = 0; + unsigned long long targetDelta = HAL_CRG_GetIpFreq(SYSTICK_BASE) / I2C_TICK_MS_DIV * handle->timeout; + + while (true) { + if (handle->baseAddress->I2C_INTR_RAW.reg & I2C_ERROR_BIT_MASK) { + SetErrorHandling(handle); + return BASE_STATUS_ERROR; + } + + /* Check the status of the item is ready. */ + if (CheckItemStatus(handle, checkItem, opt)) { + if (checkItem == SLAVE_ADDRESS_MATCH) { + /* Clear slave address match raw interrupt */ + handle->baseAddress->I2C_INTR_RAW.BIT.slv_addr_match_raw = BASE_CFG_SET; + } + return BASE_STATUS_OK; + } + + curTick = DCL_SYSTICK_GetTick(); + delta += curTick > preTick ? curTick - preTick : SYSTICK_MAX_VALUE - preTick + curTick; + if (delta >= targetDelta) { /* Check timeout. */ + break; + } + preTick = curTick; + } + return BASE_STATUS_TIMEOUT; +} + +/** + * @brief Set the sending data and operation commands. + * @param handle I2C handle. + * @param cmd Operation commands. + * @param data Sending data. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType SetTxFIFODataAndCmd(I2C_Handle *handle, I2C_CmdType cmd, unsigned char data) +{ + BASE_StatusType ret; + unsigned int temp; + + ret = WaitStatusReady(handle, TX_FIFO_NOT_FULL, I2C_OPERATION_WRITE); + if (ret != BASE_STATUS_OK) { + return ret; + } + /* The 8 to 11 bits are the Timing Commands, and the 0 to 7 bits are the write data. */ + temp = (((unsigned int)cmd << I2C_TXFIFO_CMD_POS) & I2C_TXFIFO_CMD_MASK); + temp |= (((unsigned int)data << I2C_TXFIFO_WDATA_POS) & I2C_TXFIFO_WDATA_MASK); + handle->baseAddress->I2C_TX_FIFO.reg = temp; /* Sets the data and commands to be sent. */ + return BASE_STATUS_OK; +} + +/** + * @brief Send a write command to the slave device. + * @param handle I2C handle. + * @param index The number of I2C. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType SendSlaveAddressWriteCmd(I2C_Handle *handle, unsigned int index) +{ + BASE_StatusType ret; + unsigned char addr; + /* Write slave address */ + if (handle->addrMode == I2C_10_BITS) { /* 10bit address Configuration */ + if (handle->transferCount == 0) { + /* The first address of a 10-bit address configuration */ + addr = (unsigned char)((g_internalConfigParam[index].slaveAddress >> I2C_SLAVE_WRITE_ADDR_POS) & + I2C_SLAVE_ADDR_MASK); + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_TD_RACK_S_RD_TACK, addr); + if (ret != BASE_STATUS_OK) { + return ret; + } + /* The second address of the 10-bit address configuration */ + addr = (unsigned char)(g_internalConfigParam[index].slaveAddress & I2C_SLAVE_ADDR_MASK); + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_TD_RACK_S_RD_TACK, addr); + if (ret != BASE_STATUS_OK) { + return ret; + } + } else { + addr = (unsigned char)((g_internalConfigParam[index].slaveAddress >> I2C_SLAVE_WRITE_ADDR_POS) & + I2C_SLAVE_ADDR_MASK); + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_TD_RACK_S_RD_TACK, addr); + if (ret != BASE_STATUS_OK) { + return ret; + } + } + } else { /* 7bit address Configuration */ + addr = (unsigned char)(g_internalConfigParam[index].slaveAddress & I2C_SLAVE_ADDR_MASK); + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_TD_RACK_S_RD_TACK, addr); + if (ret != BASE_STATUS_OK) { + return ret; + } + } + return BASE_STATUS_OK; +} + +/** + * @brief Send a read command to the slave device. + * @param handle I2C handle. + * @param index The number of I2C. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType SendSlaveAddressReadCmd(I2C_Handle *handle, unsigned int index) +{ + BASE_StatusType ret; + unsigned char addr; + /* Write slave address */ + if (handle->addrMode == I2C_10_BITS) { /* 10bit address Configuration */ + if (handle->transferCount == 0) { + /* The first address of a 10-bit address configuration */ + addr = (unsigned char)((g_internalConfigParam[index].slaveAddress >> I2C_SLAVE_READ_FIX_ADDR_POS) & + I2C_SLAVE_ADDR_MASK); + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_TD_RACK_S_RD_TACK, addr); + if (ret != BASE_STATUS_OK) { + return ret; + } + /* The second address of the 10-bit address configuration */ + addr = (unsigned char)((g_internalConfigParam[index].slaveAddress >> I2C_SLAVE_READ_DEV_ADDR_POS) & + I2C_SLAVE_ADDR_MASK); + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_TD_RACK_S_RD_TACK, addr); + if (ret != BASE_STATUS_OK) { + return ret; + } + } else { + addr = (unsigned char)((g_internalConfigParam[index].slaveAddress >> I2C_SLAVE_READ_FIX_ADDR_POS) & + I2C_SLAVE_ADDR_MASK); + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_TD_RACK_S_RD_TACK, addr); + if (ret != BASE_STATUS_OK) { + return ret; + } + } + } else { /* 7bit address Configuration */ + addr = (unsigned char)((g_internalConfigParam[index].slaveAddress >> I2C_SLAVE_READ_DEV_ADDR_POS) & + I2C_SLAVE_ADDR_MASK); + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_TD_RACK_S_RD_TACK, addr); + if (ret != BASE_STATUS_OK) { + return ret; + } + } + return BASE_STATUS_OK; +} + +/** + * @brief I2C Parameter Configuration in blocking. + * @param handle I2C handle. + * @param transferStatus The status is used to indicate read or write. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType I2C_ConfigParametersAndStartBlocking(I2C_Handle *handle, unsigned int transferStatus) +{ + BASE_StatusType ret; + /* Startup Control */ + handle->baseAddress->I2C_CTRL1.BIT.dma_operation = I2C_DMA_OP_NONE; + handle->baseAddress->I2C_CTRL1.BIT.rst_rx_fifo = BASE_CFG_SET; + handle->baseAddress->I2C_CTRL1.BIT.rst_tx_fifo = BASE_CFG_SET; + + handle->baseAddress->I2C_CTRL1.BIT.mst_start = (transferStatus == I2C_MASTER_STATUS) ? BASE_CFG_SET : + BASE_CFG_UNSET; + if (transferStatus == I2C_SLAVE_STATUS) { + return BASE_STATUS_OK; + } + /* Send I2C start */ + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_S, 0); /* Sets the start command to be sent. */ + if (ret != BASE_STATUS_OK) { + SetErrorHandling(handle); + return ret; + } + return ret; +} + +/** + * @brief Master send stop command in blocking. + * @param handle I2C handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType BlockingSendStopCommand(I2C_Handle *handle) +{ + BASE_StatusType ret; + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_P, 0); + if (ret != BASE_STATUS_OK) { + SetErrorHandling(handle); + return ret; + } + /* Wait until all commands are executed. */ + ret = WaitStatusReady(handle, COMMAND_ALL_DONE, I2C_OPERATION_WRITE); + handle->errorCode = ret; + SetErrorHandling(handle); + return ret; +} + +/** + * @brief The step of receive normal data in blocking as master. + * @param handle I2C handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType BlockingMasterRxDataOptStepNormal(I2C_Handle *handle) +{ + BASE_StatusType ret = BASE_STATUS_OK; + while (handle->transferCount < handle->transferSize) { + if (handle->transferCount == handle->transferSize - 1) { + /* Reads the last frame of data without ack. */ + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_RD_TNACK_S_TD_RNACK, 0); + } else { + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_RD_TACK_S_TD_RACK, 0); + } + if (ret != BASE_STATUS_OK) { + SetErrorHandling(handle); + return ret; + } + /* Wait the RX FIFO is not empty. */ + ret = WaitStatusReady(handle, RX_FIFO_NOT_EMPTY, I2C_OPERATION_READ); + if (ret != BASE_STATUS_OK) { + SetErrorHandling(handle); + return ret; + } + /* Obtains the data received from the RX FIFO. */ + *handle->transferBuff = handle->baseAddress->I2C_RX_FIFO.BIT.rx_fifo_rdata; + handle->transferBuff++; + handle->transferCount++; + } + return ret; +} + +/** + * @brief The step of transmit normal data in blocking as master. + * @param handle I2C handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType BlockingMasterTxDataOptStepNormal(I2C_Handle *handle) +{ + BASE_StatusType ret; + /* Sets data to be sent cyclically. */ + while (handle->transferCount < handle->transferSize) { + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_TD_RACK_S_RD_TACK, *handle->transferBuff); + if (ret != BASE_STATUS_OK) { + SetErrorHandling(handle); + return ret; + } + handle->transferBuff++; + handle->transferCount++; + } + return BASE_STATUS_OK; +} + +/** + * @brief The step of receive normal data in blocking as slave. + * @param handle I2C handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType BlockingSlaveRxDataOptStepNormal(I2C_Handle *handle) +{ + while (handle->transferCount < handle->transferSize) { + /* Sets the data to be received. */ + if (SetTxFIFODataAndCmd(handle, I2C_CMD_M_TD_RACK_S_RD_TACK, 0) != BASE_STATUS_OK) { + SetErrorHandling(handle); + return BASE_STATUS_TIMEOUT; + } + if (WaitStatusReady(handle, RX_FIFO_NOT_EMPTY, I2C_OPERATION_READ) != BASE_STATUS_OK) { + SetErrorHandling(handle); + return BASE_STATUS_TIMEOUT; + } + /* Obtains the data received in the RX FIFO. */ + *handle->transferBuff = handle->baseAddress->I2C_RX_FIFO.BIT.rx_fifo_rdata; + handle->transferBuff++; + handle->transferCount++; + } + return BASE_STATUS_OK; +} + +/** + * @brief Checking Interrupts Caused by I2C Timing Errors. + * @param handle I2C handle. + * @param status Status of the I2C. + * @retval true or false + */ +static bool IsInterruptErrorStatus(I2C_Handle *handle, unsigned int status) +{ + if (status & I2C_ERROR_BIT_MASK) { + /* If the low level times out, the I2C bus is cleared and the bus is expected to be released. */ + if (status & I2C_SCL_LOW_TIMEOUT_MASK) { + I2cBusClear(handle); + } + /* Disable */ + handle->errorCode = BASE_STATUS_ERROR; + handle->baseAddress->I2C_CTRL1.BIT.mst_start = BASE_CFG_DISABLE; + /* Clears interrupts and disables interrupt reporting to + facilitate switching between different working modes. */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + handle->state = I2C_STATE_READY; + if (handle->userCallBack.ErrorCallback != NULL) { + handle->userCallBack.ErrorCallback(handle); + } + return true; + } + return false; +} + +/** + * @brief Interrupt handle send start command. + * @param handle I2C handle. + * @param index The number of I2C. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType InterruptSendStart(I2C_Handle *handle, unsigned index) +{ + unsigned int temp; + if (g_internalConfigParam[index].sendAddressStatus <= I2C_SEND_ADDR_STATUS_NONE) { + return BASE_STATUS_OK; + } + + if (handle->baseAddress->I2C_FIFO_STAT.BIT.tx_fifo_vld_num < I2C_MAX_FIFO_SIZE) { + /* The 8 to 11 bits are the Timing Commands, and the 0 to 7 bits are the write data. */ + temp = (((unsigned int)I2C_CMD_S << I2C_TXFIFO_CMD_POS) & I2C_TXFIFO_CMD_MASK); + handle->baseAddress->I2C_TX_FIFO.reg = temp; /* Sets the data and commands to be sent. */ + } else { + return BASE_STATUS_ERROR; + } + switch (g_internalConfigParam[index].sendAddressStatus) { + case I2C_SEND_ADDR_STATUS_WRITE: + /* Send a write command to the slave. */ + if (SendSlaveAddressWriteCmd(handle, index) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + break; + case I2C_SEND_ADDR_STATUS_READ: + /* Send a read command to the slave. */ + if (SendSlaveAddressReadCmd(handle, index) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + break; + default: + break; + } + g_internalConfigParam[index].sendAddressStatus = I2C_SEND_ADDR_STATUS_NONE; + return BASE_STATUS_OK; +} + +/** + * @brief I2C Interrupt done Handling + * @param handle I2C handle. + * @param status I2C interrupt raw status. + * @retval None. + */ +static void InterruptAllDoneHandle(I2C_Handle *handle, unsigned int status) +{ + /* After all data transmission is complete, call the user's callback function. */ + unsigned int masterAllDone = status & I2C_INTR_RAW_ALL_CMD_DONE_MASK; + unsigned int slaveReceiveStop = status & I2C_INTR_RAW_STOP_DET_MASK; + unsigned int allDoneItFlag = (masterAllDone || slaveReceiveStop); + if ((handle->transferCount >= handle->transferSize) && allDoneItFlag) { + /* Clears interrupts and disables interrupt reporting to + facilitate switching between different working modes. */ + handle->baseAddress->I2C_CTRL1.BIT.mst_start = BASE_CFG_DISABLE; + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + if (handle->userCallBack.RxCplCallback != NULL && + (handle->state == I2C_STATE_BUSY_MASTER_RX || handle->state == I2C_STATE_BUSY_SLAVE_RX)) { + handle->userCallBack.RxCplCallback(handle); /* Invoke the RX callback processing function. */ + } else if (handle->userCallBack.TxCplCallback != NULL && + (handle->state == I2C_STATE_BUSY_MASTER_TX || handle->state == I2C_STATE_BUSY_SLAVE_TX)) { + handle->userCallBack.TxCplCallback(handle); /* Invoke the TX callback processing function. */ + } + handle->state = I2C_STATE_READY; + } +} + +/** + * @brief I2C interrupt TX handling + * @param handle I2C handle. + * @param index The number of I2C. + * @retval None. + */ +static void InterruptMasterTxHandle(I2C_Handle *handle, unsigned int index) +{ + I2C_ASSERT_PARAM(handle != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_ASSERT_PARAM(handle->transferBuff != NULL); + unsigned int temp; + /* Send a start command to the slave. */ + if (InterruptSendStart(handle, index) != BASE_STATUS_OK) { + return; + } + while (handle->baseAddress->I2C_FIFO_STAT.BIT.tx_fifo_vld_num < I2C_MAX_FIFO_SIZE && + handle->transferCount < handle->transferSize) { + /* Sets the data to be sent. */ + temp = (((unsigned int)I2C_CMD_M_TD_RACK_S_RD_TACK << I2C_TXFIFO_CMD_POS) & I2C_TXFIFO_CMD_MASK); + temp |= ((unsigned int)(*handle->transferBuff) & I2C_TXFIFO_WDATA_MASK); + handle->baseAddress->I2C_TX_FIFO.reg = temp; /* Sets the data and commands to be sent. */ + handle->transferBuff++; + handle->transferCount++; + } +} + +/** + * @brief I2C Interrupt RX Handling + * @param handle I2C handle. + * @param index The number of I2C. + * @retval None. + */ +static void InterruptMasterRxHandle(I2C_Handle *handle, unsigned int index) +{ + I2C_ASSERT_PARAM(handle != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_ASSERT_PARAM(handle->transferBuff != NULL); + /* Send a start command to the slave. */ + if (InterruptSendStart(handle, index) != BASE_STATUS_OK) { + return; + } + /* The I2C controller fills in the receive command and starts to receive data. */ + while (handle->baseAddress->I2C_FIFO_STAT.BIT.tx_fifo_vld_num < I2C_MAX_FIFO_SIZE && + g_internalConfigParam[index].txReadCmdCnt < handle->transferSize) { + if (g_internalConfigParam[index].txReadCmdCnt == handle->transferSize - 1) { + handle->baseAddress->I2C_TX_FIFO.reg = + (((unsigned int)I2C_CMD_M_RD_TNACK_S_TD_RNACK << I2C_TXFIFO_CMD_POS) & I2C_TXFIFO_CMD_MASK); + } else { /* Normal data transmission. */ + handle->baseAddress->I2C_TX_FIFO.reg = + (((unsigned int)I2C_CMD_M_RD_TACK_S_TD_RACK << I2C_TXFIFO_CMD_POS) & I2C_TXFIFO_CMD_MASK); + } + g_internalConfigParam[index].txReadCmdCnt++; + } + /* Obtains the data received in the RX FIFO. */ + while (handle->baseAddress->I2C_FIFO_STAT.BIT.rx_fifo_vld_num > 0 && + handle->transferCount < handle->transferSize) { + *handle->transferBuff++ = handle->baseAddress->I2C_RX_FIFO.BIT.rx_fifo_rdata; + handle->transferCount++; + } +} + +/** + * @brief I2C interrupt slave TX handling + * @param handle I2C handle. + * @retval None. + */ +static void InterruptSlaveTxHandle(I2C_Handle *handle) +{ + I2C_ASSERT_PARAM(handle != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_ASSERT_PARAM(handle->transferBuff != NULL); + unsigned int temp; + while (handle->baseAddress->I2C_FIFO_STAT.BIT.tx_fifo_vld_num < I2C_MAX_FIFO_SIZE && + handle->transferCount < handle->transferSize) { + if (handle->transferCount == handle->transferSize - 1) { /* no need ack. */ + temp = (((unsigned int)I2C_CMD_M_RD_TNACK_S_TD_RNACK << I2C_TXFIFO_CMD_POS) & I2C_TXFIFO_CMD_MASK); + temp |= ((unsigned int)(*handle->transferBuff) & I2C_TXFIFO_WDATA_MASK); + handle->baseAddress->I2C_TX_FIFO.reg = temp; /* Sets the data and commands to be sent. */ + } else { /* Normal data transmission. */ + temp = (((unsigned int)I2C_CMD_M_RD_TACK_S_TD_RACK << I2C_TXFIFO_CMD_POS) & I2C_TXFIFO_CMD_MASK); + temp |= ((unsigned int)(*handle->transferBuff) & I2C_TXFIFO_WDATA_MASK); + handle->baseAddress->I2C_TX_FIFO.reg = temp; /* Sets the data and commands to be sent. */ + } + handle->transferBuff++; + handle->transferCount++; + } +} + +/** + * @brief I2C interrupt slave RX handling + * @param handle I2C handle. + * @param index The number of I2C. + * @retval None. + */ +static void InterruptSlaveRxHandle(I2C_Handle *handle, unsigned int index) +{ + I2C_ASSERT_PARAM(handle != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_ASSERT_PARAM(handle->transferBuff != NULL); + /* Set the data receiving command. */ + while (handle->baseAddress->I2C_FIFO_STAT.BIT.tx_fifo_vld_num < I2C_MAX_FIFO_SIZE && + g_internalConfigParam[index].txReadCmdCnt < handle->transferSize) { + handle->baseAddress->I2C_TX_FIFO.reg = + (((unsigned int)I2C_CMD_M_TD_RACK_S_RD_TACK << I2C_TXFIFO_CMD_POS) & I2C_TXFIFO_CMD_MASK); + g_internalConfigParam[index].txReadCmdCnt++; + } + /* Obtained data from RX FIFO. */ + while (handle->baseAddress->I2C_FIFO_STAT.BIT.rx_fifo_vld_num > 0 && + handle->transferCount < handle->transferSize) { + *handle->transferBuff = handle->baseAddress->I2C_RX_FIFO.BIT.rx_fifo_rdata; + handle->transferBuff++; + handle->transferCount++; + } +} + +/** + * @brief ICallback function corresponding to the interrupt processing function. + * @param handle I2C handle. + * @param status Status of the I2C. + * @param index The number of I2C. + * @retval None. + */ +static void InterruptHandle(I2C_Handle *handle, unsigned int status, unsigned int index) +{ + if (handle->state == I2C_STATE_BUSY_MASTER_TX) { + InterruptMasterTxHandle(handle, index); /* Transfer data as a host. */ + return; + } else if (handle->state == I2C_STATE_BUSY_MASTER_RX) { + InterruptMasterRxHandle(handle, index); /* Receive data as a host. */ + return; + } else if (handle->state == I2C_STATE_BUSY_SLAVE_TX) { + if (status & I2C_INTR_RAW_SLAVE_ADDR_MATCH_MASK) { + /* Set TX FIFO the waterline. */ + handle->baseAddress->I2C_INTR_EN.BIT.tx_fifo_not_full_en = BASE_CFG_SET; + } + if (handle->baseAddress->I2C_RX_ADDR.BIT.rx_rw == I2C_OPERATION_READ) { + InterruptSlaveTxHandle(handle); /* Transfer data as slave. */ + } + return; + } else if (handle->state == I2C_STATE_BUSY_SLAVE_RX) { + if (status & I2C_INTR_RAW_SLAVE_ADDR_MATCH_MASK) { + /* Set TX FIFO the waterline. */ + handle->baseAddress->I2C_INTR_EN.BIT.tx_fifo_not_full_en = BASE_CFG_SET; + /* Set RX FIFO the waterline. */ + handle->baseAddress->I2C_INTR_EN.BIT.rx_fifo_not_empty_en = BASE_CFG_SET; + } + if (handle->baseAddress->I2C_RX_ADDR.BIT.rx_rw == I2C_OPERATION_WRITE) { + InterruptSlaveRxHandle(handle, index); /* Receive data as slave. */ + } + return; + } + handle->errorCode = BASE_STATUS_ERROR; + /* Clears interrupts and disables interrupt reporting to + facilitate switching between different working modes. */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->state = I2C_STATE_READY; /* Changing the I2C Bus Status. */ + if (handle->userCallBack.ErrorCallback != NULL) { + handle->userCallBack.ErrorCallback(handle); + } +} + +/** + * @brief DMA Command Configuration. + * @param handle I2C handle. + * @param cmd The command type of I2C. + * @param size The number of the data to be receiving or sending. + * @retval Value of the command. + */ +static unsigned int DmaConfigCommandData(I2C_Handle *handle, I2C_CmdType cmd, unsigned int size) +{ + unsigned int temp; + /* Sets the command data. */ + if ((cmd == I2C_CMD_M_RD_TACK_S_TD_RACK) && (size == 1) && (handle->transferCount >= handle->transferSize)) { + temp = (((unsigned int)I2C_CMD_M_RD_TNACK_S_TD_RNACK << I2C_TXFIFO_CMD_POS) & I2C_TXFIFO_CMD_MASK); + } else { + temp = (((unsigned int)cmd << I2C_TXFIFO_CMD_POS) & I2C_TXFIFO_CMD_MASK); + } + return temp; +} + +/** + * @brief Config commands and data in dma as master. + * @param handle I2C handle. + * @param txBuff Address of the data buff to be receiving or sending. + * @param cmd The command type of I2C. + * @param size The number of the data to be receiving or sending. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType DmaMasterConfigDataAndCmd(I2C_Handle *handle, unsigned int *txBuff, I2C_CmdType cmd, + unsigned int size) +{ + unsigned int temp; + unsigned int *tempTxBuff = txBuff; + unsigned char *tempsrcTxBuff = (unsigned char*)handle->transferBuff; + unsigned int tempSize = size; + while (tempSize) { + /* Sets the command data. */ + temp = DmaConfigCommandData(handle, cmd, tempSize); + /* Sets the normal data. */ + if (cmd == I2C_CMD_M_TD_RACK_S_RD_TACK) { + temp |= (((unsigned int)*tempsrcTxBuff << I2C_TXFIFO_WDATA_POS) & I2C_TXFIFO_WDATA_MASK); + tempsrcTxBuff++; + } else if ((cmd == I2C_CMD_M_RD_TACK_S_TD_RACK) && (tempSize > 1)) { + temp |= ((0x0 << I2C_TXFIFO_WDATA_POS) & I2C_TXFIFO_WDATA_MASK); + } + *tempTxBuff = temp; /* Set the combined data. */ + tempTxBuff++; + tempSize--; + temp = 0; + } + return BASE_STATUS_OK; +} + +/** + * @brief Config commands and data in dma as slave. + * @param handle I2C handle. + * @param txBuff Address of the data buff to be receiving or sending. + * @param cmd The command type of I2C. + * @param size The number of the data to be receiving or sending. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType DmaSlaveConfigDataAndCmd(I2C_Handle *handle, unsigned int *txBuff, I2C_CmdType cmd, + unsigned int size) +{ + unsigned int temp; + unsigned int *tempTxBuff = txBuff; + unsigned char *tempsrcTxBuff = (unsigned char*)handle->transferBuff; + unsigned int tempSize = size; + while (tempSize) { + /* Sets the command data. */ + temp = DmaConfigCommandData(handle, cmd, tempSize); + /* Sets the normal data. */ + if (cmd == I2C_CMD_M_RD_TACK_S_TD_RACK) { + temp |= (((unsigned int)*tempsrcTxBuff << I2C_TXFIFO_WDATA_POS) & I2C_TXFIFO_WDATA_MASK); + tempsrcTxBuff++; + } else if (cmd == I2C_CMD_M_TD_RACK_S_RD_TACK) { + temp |= ((0x0 << I2C_TXFIFO_WDATA_POS) & I2C_TXFIFO_WDATA_MASK); + } + *tempTxBuff = temp; /* Set the combined data. */ + tempTxBuff++; + tempSize--; + temp = 0; + } + return BASE_STATUS_OK; +} + +/** + * @brief I2C DMA Error Handling. + * @param handle I2C handle. + * @retval None. + */ +static void I2C_DmaErrorHandle(I2C_Handle *handle) +{ + /* Some settings when an error occurs. */ + handle->baseAddress->I2C_CTRL1.BIT.dma_operation = I2C_DMA_OP_NONE; + handle->baseAddress->I2C_CTRL1.BIT.mst_start = BASE_CFG_UNSET; + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + handle->errorCode = BASE_STATUS_ERROR; + if (handle->userCallBack.ErrorCallback != NULL) { + handle->userCallBack.ErrorCallback(handle); + } + handle->state = I2C_STATE_READY; +} + +/** + * @brief I2C DMA completes processing. + * @param handle I2C handle. + * @retval None. + */ +static void I2C_DmaDoneHandle(I2C_Handle *handle) +{ + /* Disable the DMA operation and configure parameters. */ + handle->baseAddress->I2C_CTRL1.BIT.dma_operation = I2C_DMA_OP_NONE; + handle->baseAddress->I2C_CTRL1.BIT.mst_start = BASE_CFG_UNSET; + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + /* Call the corresponding callback function. */ + if (handle->state == I2C_STATE_BUSY_MASTER_RX || handle->state == I2C_STATE_BUSY_SLAVE_RX) { + if (handle->userCallBack.RxCplCallback != NULL) { + handle->userCallBack.RxCplCallback(handle); + } + } else if (handle->state == I2C_STATE_BUSY_MASTER_TX || handle->state == I2C_STATE_BUSY_SLAVE_TX) { + if (handle->userCallBack.TxCplCallback != NULL) { + handle->userCallBack.TxCplCallback(handle); + } + } + handle->state = I2C_STATE_READY; +} + +/** + * @brief Wait until all I2C timings are processed. + * @param handle I2C handle. + * @retval None. + */ +static void DmaWaitHandleFinish(I2C_Handle *handle) +{ + unsigned int intrRwa; + unsigned int preTick; + unsigned int curTick; + unsigned long long delta; + unsigned long long targetDelta; + + delta = 0; + preTick = DCL_SYSTICK_GetTick(); + /* Set the timeout threshold to 10000ms. */ + targetDelta = HAL_CRG_GetIpFreq(SYSTICK_BASE) / I2C_TICK_MS_DIV * handle->timeout; + + while (true) { + /* Waiting for the last DMA transfer to complete. */ + intrRwa = handle->baseAddress->I2C_INTR_RAW.reg; + /* Check for errors. */ + if ((intrRwa & (I2C_INTR_RAW_ARB_LOST_MASK | I2C_INTR_RAW_ACK_BIT_UNMATCH_MASK | + I2C_INTR_RAW_SLAVE_ACK_UNMATCH_MASK)) > 0) { + I2C_DmaErrorHandle(handle); + break; + } + /* DMA transfer completed normally. */ + if ((intrRwa & (I2C_INTR_RAW_ALL_CMD_DONE_MASK | I2C_INTR_RAW_STOP_DET_MASK)) > 0) { + I2C_DmaDoneHandle(handle); + break; + } + curTick = DCL_SYSTICK_GetTick(); + delta += curTick > preTick ? curTick - preTick : SYSTICK_MAX_VALUE - preTick + curTick; + if (delta >= targetDelta) { /* Check timeout. */ + return; + } + preTick = curTick; + } +} + +/** + * @brief The I2C uses the DMA completion callback function registered by the DMA module. + * @param handle I2C handle. + * @retval None. + */ +static void DmaOptStepNormalFinishFun(void *handle) +{ + I2C_ASSERT_PARAM(handle != NULL); + I2C_Handle *i2cHandle = (I2C_Handle *)(handle); + I2C_ASSERT_PARAM(IsI2CInstance(i2cHandle->baseAddress)); + + BASE_StatusType ret = BASE_STATUS_OK; + unsigned int tempOnceTransferSize; + unsigned int index; + unsigned int offset; + + /* Determine which I2C is used. */ + index = (i2cHandle->baseAddress == I2C0) ? I2C_INTERFACE_INDEX_0 : I2C_INTERFACE_INDEX_1; + offset = i2cHandle->transferCount % I2C_ONCE_TRANS_MAX_NUM; + i2cHandle->transferBuff += (offset == 0) ? I2C_ONCE_TRANS_MAX_NUM : offset; /* Update Transferred Data. */ + + if (i2cHandle->transferCount < i2cHandle->transferSize) { + /* Determine the amount of data transmitted at a time. */ + tempOnceTransferSize = (g_dmaTransferSize >= I2C_ONCE_TRANS_MAX_NUM) ? I2C_ONCE_TRANS_MAX_NUM : + g_dmaTransferSize; + g_dmaTransferSize -= tempOnceTransferSize; + i2cHandle->transferCount += tempOnceTransferSize; + /* Configuring the I2C Timing */ + if (i2cHandle->state == I2C_STATE_BUSY_MASTER_RX) { + ret = DmaMasterReadData(i2cHandle, tempOnceTransferSize, index); + } else if (i2cHandle->state == I2C_STATE_BUSY_MASTER_TX) { + ret = DmaMasterWriteData(i2cHandle, tempOnceTransferSize, index); + } else if (i2cHandle->state == I2C_STATE_BUSY_SLAVE_RX) { + ret = DmaSlaveReadData(i2cHandle, tempOnceTransferSize, index); + } else if (i2cHandle->state == I2C_STATE_BUSY_SLAVE_TX) { + ret = DmaSlaveWriteData(i2cHandle, tempOnceTransferSize, index); + } + /* Check whether errors occur. */ + if (ret != BASE_STATUS_OK) { + SetErrorHandling(handle); + } + return; + } + SetTxFIFODataAndCmd(i2cHandle, I2C_CMD_P, 0); + DmaWaitHandleFinish(i2cHandle); +} + +/** + * @brief The I2C uses the DMA error callback function registered by the DMA module. + * @param handle I2C handle. + * @retval None. + */ +static void DmaErrorHandlerFun(void *handle) +{ + I2C_ASSERT_PARAM(handle != NULL); + I2C_Handle *i2cHandle = (I2C_Handle *)(handle); + I2C_ASSERT_PARAM(IsI2CInstance(i2cHandle->baseAddress)); + /* Disable the interrupt and call the error callback function. */ + i2cHandle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + i2cHandle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + i2cHandle->errorCode = BASE_STATUS_ERROR; + if (i2cHandle->userCallBack.ErrorCallback != NULL) { + i2cHandle->userCallBack.ErrorCallback(i2cHandle); + } + /* Stop DMA channel transfer. */ + HAL_DMA_StopChannel(i2cHandle->dmaHandle, i2cHandle->txDmaCh); + if (i2cHandle->state == I2C_STATE_BUSY_MASTER_RX || i2cHandle->state == I2C_STATE_BUSY_SLAVE_RX) { + HAL_DMA_StopChannel(i2cHandle->dmaHandle, i2cHandle->rxDmaCh); + } + i2cHandle->state = I2C_STATE_READY; +} + +/** + * @brief Receive data as master by the DMA module. + * @param handle I2C handle. + * @param size Number of the data to be transmitted. + * @param index The number of I2C. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType DmaMasterReadData(I2C_Handle *handle, unsigned int size, unsigned int index) +{ + /* Combine commands and data. */ + DmaMasterConfigDataAndCmd(handle, (unsigned int *)g_internalTxBuffDMA[index], I2C_CMD_M_RD_TACK_S_TD_RACK, size); + + /* Configuring the DMA Callback Function. */ + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->txDmaCh].ChannelFinishCallBack = NULL; + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->txDmaCh].ChannelErrorCallBack = DmaErrorHandlerFun; + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->rxDmaCh].ChannelFinishCallBack = DmaOptStepNormalFinishFun; + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->rxDmaCh].ChannelErrorCallBack = DmaErrorHandlerFun; + /* Start the DMA for data transmission. */ + if (HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t)g_internalTxBuffDMA[index], + (uintptr_t)&(handle->baseAddress->I2C_TX_FIFO.reg), + size, handle->txDmaCh) != BASE_STATUS_OK) { + handle->state = I2C_STATE_READY; + return BASE_STATUS_ERROR; + } + if (HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t)&(handle->baseAddress->I2C_RX_FIFO), + (uintptr_t)handle->transferBuff, size, + handle->rxDmaCh) != BASE_STATUS_OK) { + handle->state = I2C_STATE_READY; + return BASE_STATUS_ERROR; + } + handle->baseAddress->I2C_CTRL1.BIT.dma_operation = I2C_DMA_OP_WRITE_READ; + return BASE_STATUS_OK; +} + +/** + * @brief Transmit data as master by the DMA module. + * @param handle I2C handle. + * @param size Number of the data to be transmitted. + * @param index The number of I2C. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType DmaMasterWriteData(I2C_Handle *handle, unsigned int size, unsigned int index) +{ + /* Combine commands and data. */ + DmaMasterConfigDataAndCmd(handle, (unsigned int *)g_internalTxBuffDMA[index], I2C_CMD_M_TD_RACK_S_RD_TACK, size); + + /* Configuring the DMA Callback Function. */ + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->txDmaCh].ChannelFinishCallBack = DmaOptStepNormalFinishFun; + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->txDmaCh].ChannelErrorCallBack = DmaErrorHandlerFun; + /* Start the DMA for data transmission. */ + if (HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t)g_internalTxBuffDMA[index], + (uintptr_t)&(handle->baseAddress->I2C_TX_FIFO.reg), + size, handle->txDmaCh) != BASE_STATUS_OK) { + handle->state = I2C_STATE_READY; + return BASE_STATUS_ERROR; + } + handle->baseAddress->I2C_CTRL1.BIT.dma_operation = I2C_DMA_OP_WRITE; + return BASE_STATUS_OK; +} + +/** + * @brief Receive data as slave by the DMA module. + * @param handle I2C handle. + * @param size Number of the data to be transmitted. + * @param index The number of I2C. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType DmaSlaveReadData(I2C_Handle *handle, unsigned int size, unsigned int index) +{ + /* Combine commands and data. */ + DmaSlaveConfigDataAndCmd(handle, (unsigned int *)g_internalTxBuffDMA[index], I2C_CMD_M_TD_RACK_S_RD_TACK, size); + + /* Configuring the DMA Callback Function. */ + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->txDmaCh].ChannelFinishCallBack = NULL; + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->txDmaCh].ChannelErrorCallBack = DmaErrorHandlerFun; + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->rxDmaCh].ChannelFinishCallBack = DmaOptStepNormalFinishFun; + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->rxDmaCh].ChannelErrorCallBack = DmaErrorHandlerFun; + /* Start the DMA for data transmission. */ + if (HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t)&(handle->baseAddress->I2C_RX_FIFO), + (uintptr_t)handle->transferBuff, size, + handle->rxDmaCh) != BASE_STATUS_OK) { + handle->state = I2C_STATE_READY; + return BASE_STATUS_ERROR; + } + if (HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t)g_internalTxBuffDMA[index], + (uintptr_t)&(handle->baseAddress->I2C_TX_FIFO), + size, handle->txDmaCh) != BASE_STATUS_OK) { + handle->state = I2C_STATE_READY; + return BASE_STATUS_ERROR; + } + handle->baseAddress->I2C_CTRL1.BIT.dma_operation = I2C_DMA_OP_WRITE_READ; + return BASE_STATUS_OK; +} + +/** + * @brief Transmit data as slave by the DMA module. + * @param handle I2C handle. + * @param size Number of the data to be transmitted. + * @param index The number of I2C. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType DmaSlaveWriteData(I2C_Handle *handle, unsigned int size, unsigned int index) +{ + /* Combine commands and data. */ + DmaSlaveConfigDataAndCmd(handle, (unsigned int *)g_internalTxBuffDMA[index], I2C_CMD_M_RD_TACK_S_TD_RACK, size); + /* Configure DMA Parameters */ + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->txDmaCh].ChannelFinishCallBack = DmaOptStepNormalFinishFun; + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->txDmaCh].ChannelErrorCallBack = DmaErrorHandlerFun; + if (HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t)g_internalTxBuffDMA[index], + (uintptr_t)&(handle->baseAddress->I2C_TX_FIFO.reg), size, handle->txDmaCh) != BASE_STATUS_OK) { + handle->state = I2C_STATE_READY; + return BASE_STATUS_ERROR; + } + handle->baseAddress->I2C_CTRL1.BIT.dma_operation = I2C_DMA_OP_WRITE; + return BASE_STATUS_OK; +} + +/** + * @brief Transmit data by the DMA module. + * @param handle I2C handle. + * @param index The number of I2C. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType I2cTransferDataDma(I2C_Handle *handle, unsigned int index) +{ + BASE_StatusType ret = BASE_STATUS_OK; + unsigned int tempOnceTransferSize; + + g_dmaTransferSize = handle->transferSize; + /* Determine the amount of data transmitted at a time. */ + tempOnceTransferSize = (g_dmaTransferSize >= I2C_ONCE_TRANS_MAX_NUM) ? I2C_ONCE_TRANS_MAX_NUM : + g_dmaTransferSize; + g_dmaTransferSize -= tempOnceTransferSize; + handle->transferCount += tempOnceTransferSize; + /* Configuring the I2C Timing */ + if (handle->state == I2C_STATE_BUSY_MASTER_RX) { + ret = DmaMasterReadData(handle, tempOnceTransferSize, index); + } else if (handle->state == I2C_STATE_BUSY_MASTER_TX) { + ret = DmaMasterWriteData(handle, tempOnceTransferSize, index); + } else if (handle->state == I2C_STATE_BUSY_SLAVE_RX) { + ret = DmaSlaveReadData(handle, tempOnceTransferSize, index); + } else if (handle->state == I2C_STATE_BUSY_SLAVE_TX) { + ret = DmaSlaveWriteData(handle, tempOnceTransferSize, index); + } + /* Check whether errors occur. */ + if (ret != BASE_STATUS_OK) { + SetErrorHandling(handle); + } + return ret; +} + +/** + * @brief As Slave Multiplex Interrupt Write or Read. + * @param handle I2C handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType I2C_SlaveMultiplexIT(I2C_Handle *handle) +{ + unsigned int index = 0; + /* Determine which I2C is used. */ + index = (handle->baseAddress == I2C0) ? I2C_INTERFACE_INDEX_0 : I2C_INTERFACE_INDEX_1; + /* Parameter Settings. */ + g_internalConfigParam[index].txReadCmdCnt = 0; + g_internalConfigParam[index].sendAddressStatus = I2C_SEND_ADDR_STATUS_NONE; + /* Clean interrupt */ + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + /* Startup Control */ + handle->baseAddress->I2C_CTRL1.BIT.dma_operation = I2C_DMA_OP_NONE; + handle->baseAddress->I2C_CTRL1.BIT.rst_rx_fifo = BASE_CFG_SET; + handle->baseAddress->I2C_CTRL1.BIT.rst_tx_fifo = BASE_CFG_SET; + /* Enable interrupt */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_CFG_INTERRUPT_SLAVE; + return BASE_STATUS_OK; +} + +/** + * @brief Initializing the I2C Module. + * @param handle I2C handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_Init(I2C_Handle *handle) +{ + unsigned int clockFreq; + unsigned int val; + unsigned int tempReg; + unsigned int temp; + unsigned int tempSclLowTime; + unsigned int tempSclHighTime; + + I2C_ASSERT_PARAM(handle != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + + clockFreq = HAL_CRG_GetIpFreq((void *)handle->baseAddress); + if (CheckAllInitParameters(handle, clockFreq) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + + handle->state = I2C_STATE_BUSY; + /* Clears interrupts and disables interrupt reporting to facilitate switching between different working modes. */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + + /* Set SDA and SCL glitch filtering time. */ + handle->baseAddress->I2C_FILTER.BIT.spike_filter_time = handle->handleEx.spikeFilterTime; + /* Set SCL high and low duratiom time */ + tempSclLowTime = I2C_FREQ_LOW_PARAMTER + handle->handleEx.spikeFilterTime; + tempSclHighTime = I2C_FREQ_HIGH_PARAMTER + handle->handleEx.spikeFilterTime; + if (handle->freq <= I2C_STANDARD_FREQ_TH) { + /* scl_high_time = (fclk_i2c/fSCL) x 0.5 - 8 - spike_filter_time. */ + val = clockFreq / (handle->freq * 2) - tempSclHighTime; /* The clockFreq / (freq * 2) = cloclFreq/0.5/freq. */ + /* scl_low_time = (fclk_i2c/fSCL) x 0.5 - 9 - spike_filter_time. */ + val = ((val - 1) & LOW_HOLD_TIME_MASK) | ((val << HIGH_HOLD_TIME_POS) & HIGH_HOLD_TIME_MASK); + } else { + /* scl_high_time = (fclk_i2c/fSCL) x 0.36 - 8 - spike_filter_time. (n/100*36)=0.36n. */ + val = ((((clockFreq / 100) * 36) / handle->freq) - tempSclHighTime) << HIGH_HOLD_TIME_POS; + /* scl_low_time = (fclk_i2c/fSCL) x 0.64 - 9 - spike_filter_time. (n/100*64)=0.64n. */ + val |= (((((clockFreq / 100) * 64) / handle->freq) - tempSclLowTime) & LOW_HOLD_TIME_MASK); + } + handle->baseAddress->I2C_SCL_CFG.reg = val; + + /* Set sda hold duration.The value is fixed to 0xa */ + temp = ((handle->sdaHoldTime & 0x0000FFFF) << I2C_SDA_HOLD_DURATION_POS); + tempReg = (handle->handleEx.sdaDelayTime & 0x0000000F) | temp; + handle->baseAddress->I2C_SDA_CFG.reg = tempReg; + + /* Set I2C TX FIFO watermark */ + handle->baseAddress->I2C_TX_WATERMARK.BIT.tx_watermark = handle->txWaterMark; + /* Set I2C RX FIFO watermark */ + handle->baseAddress->I2C_RX_WATERMARK.BIT.rx_watermark = handle->rxWaterMark; + handle->baseAddress->I2C_MODE.BIT.mst_slv_function = handle->functionMode; + handle->baseAddress->I2C_MODE.BIT.rack_mode = handle->ignoreAckFlag; + + if (handle->functionMode == I2C_MODE_SELECT_SLAVE_ONLY || handle->functionMode == I2C_MODE_SELECT_MASTER_SLAVE) { + /* Sets the first own address of the slave. */ + handle->baseAddress->I2C_OWN_ADDR.BIT.own_address = handle->slaveOwnAddress; + handle->baseAddress->I2C_OWN_ADDR.BIT.i2c_general_call_en = handle->generalCallMode; + /* Sets the second own address of the slave. */ + if (handle->handleEx.slaveOwnXmbAddressEnable == BASE_CFG_ENABLE) { + handle->baseAddress->XMB_DEV_ADDR.BIT.xmb_address_en = BASE_CFG_ENABLE; + handle->baseAddress->XMB_DEV_ADDR.BIT.xmb_address = handle->handleEx.slaveOwnXmbAddress; + } + } + handle->state = I2C_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief Deinitialize the I2C module. + * @param handle I2C handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_Deinit(I2C_Handle *handle) +{ + I2C_ASSERT_PARAM(handle != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + + handle->state = I2C_STATE_BUSY; + /* Disable */ + handle->baseAddress->I2C_MODE.BIT.mst_slv_function = I2C_MODE_SELECT_NONE; + /* Clears interrupts and disables interrupt reporting to + facilitate switching between different working modes. */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + /* Clean interrupt callback functions. */ + handle->userCallBack.TxCplCallback = NULL; + handle->userCallBack.RxCplCallback = NULL; + handle->userCallBack.ErrorCallback = NULL; + handle->state = I2C_STATE_RESET; + + return BASE_STATUS_OK; +} + +/** + * @brief Callback Function Registration. + * @param handle I2C handle. + * @param callbackID Callback function ID. + * @param pcallback Pointer to the address of the registered callback function. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_RegisterCallback(I2C_Handle *handle, I2C_CallbackId callbackID, I2C_CallbackFunType pcallback) +{ + BASE_StatusType ret = BASE_STATUS_OK; + /* Check the parameter validity. */ + I2C_ASSERT_PARAM(handle != NULL && pcallback != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_ASSERT_PARAM(pcallback != NULL); + + if (handle->state == I2C_STATE_READY) { + switch (callbackID) { + case I2C_MASTER_TX_COMPLETE_CB_ID : + case I2C_SLAVE_TX_COMPLETE_CB_ID : + handle->userCallBack.TxCplCallback = pcallback; /* Invoke the transfer completion callback function. */ + break; + case I2C_MASTER_RX_COMPLETE_CB_ID : + case I2C_SLAVE_RX_COMPLETE_CB_ID : + handle->userCallBack.RxCplCallback = pcallback; /* Invoke the receive completion callback function. */ + break; + case I2C_ERROR_CB_ID : + handle->userCallBack.ErrorCallback = pcallback; /* Invoke the error callback function. */ + break; + default: + ret = BASE_STATUS_ERROR; + handle->errorCode = BASE_STATUS_ERROR; + break; + } + } else { /* If I2C state is not ready, don't invoke callback function. */ + ret = BASE_STATUS_ERROR; + handle->errorCode = BASE_STATUS_ERROR; + } + return ret; +} + +/** + * @brief Receiving data in blocking mode. + * @param handle I2C handle. + * @param devAddr Slave Device Address. + * @param rData Address of the data buff to be receiving. + * @param dataSize Number of the data to be receiving. + * @param timeout Timeout period,unit: ms. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_MasterReadBlocking(I2C_Handle *handle, unsigned short devAddr, unsigned char *rData, + unsigned int dataSize, unsigned int timeout) +{ + I2C_ASSERT_PARAM(handle != NULL && rData != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_PARAM_CHECK_WITH_RET(devAddr <= I2C_MAX_DEV_ADDR, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(timeout > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + + BASE_StatusType ret; + unsigned int index = 0; + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + + /* Determine which I2C is used. */ + index = (handle->baseAddress == I2C0) ? I2C_INTERFACE_INDEX_0 : I2C_INTERFACE_INDEX_1; + /* Waiting for the i2c bus to be idle. */ + ret = WaitStatusReady(handle, I2C_BUS_IS_FREE, I2C_SEND_ADDR_STATUS_WRITE); + if (ret != BASE_STATUS_OK) { + handle->errorCode = ret; + SetErrorHandling(handle); + return ret; + } + /* Configuring I2C Parameters. */ + handle->state = I2C_STATE_BUSY_MASTER_RX; + handle->transferBuff = rData; + handle->transferSize = dataSize; + handle->transferCount = 0; + handle->timeout = timeout; + SetSlaveDevAddr(handle, devAddr); + + /* step1 : Parameter Settings and startup Control. */ + ret = I2C_ConfigParametersAndStartBlocking(handle, I2C_MASTER_STATUS); + if (ret != BASE_STATUS_OK) { + handle->errorCode = ret; + SetErrorHandling(handle); + return ret; + } + /* step2 : Send slave address and read command. */ + ret = SendSlaveAddressReadCmd(handle, index); + if (ret != BASE_STATUS_OK) { + handle->errorCode = ret; + SetErrorHandling(handle); + return ret; + } + /* step3 : start receive data. */ + ret = BlockingMasterRxDataOptStepNormal(handle); + if (ret != BASE_STATUS_OK) { + handle->errorCode = ret; + SetErrorHandling(handle); + return ret; + } + /* step4 ：send stop CMD. */ + ret = BlockingSendStopCommand(handle); + + return ret; +} + +/** + * @brief Send data in blocking mode. + * @param handle I2C handle. + * @param devAddr Slave Device Address. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be sent. + * @param timeout Timeout period,unit: ms. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_MasterWriteBlocking(I2C_Handle *handle, unsigned short devAddr, unsigned char *wData, + unsigned int dataSize, unsigned int timeout) +{ + I2C_ASSERT_PARAM(handle != NULL && wData != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_PARAM_CHECK_WITH_RET(devAddr <= I2C_MAX_DEV_ADDR, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(timeout > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + + BASE_StatusType ret = BASE_STATUS_OK; + unsigned int index; + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + + /* Determine which I2C is used. */ + index = (handle->baseAddress == I2C0) ? I2C_INTERFACE_INDEX_0 : I2C_INTERFACE_INDEX_1; + + /* Configuring I2C Parameters. */ + handle->state = I2C_STATE_BUSY_MASTER_TX; + handle->transferBuff = wData; + handle->transferSize = dataSize; + handle->transferCount = 0; + handle->timeout = timeout; + SetSlaveDevAddr(handle, devAddr); + + /* Waiting for the i2c bus to be idle. */ + ret = WaitStatusReady(handle, I2C_BUS_IS_FREE, I2C_SEND_ADDR_STATUS_READ); + if (ret != BASE_STATUS_OK) { + handle->errorCode = ret; + SetErrorHandling(handle); + return ret; + } + + /* step1 : Parameter Settings and startup Control. */ + ret = I2C_ConfigParametersAndStartBlocking(handle, I2C_MASTER_STATUS); + if (ret != BASE_STATUS_OK) { + handle->errorCode = ret; + SetErrorHandling(handle); + return ret; + } + /* step2 : send slave addr */ + ret = SendSlaveAddressWriteCmd(handle, index); + if (ret != BASE_STATUS_OK) { + handle->errorCode = ret; + SetErrorHandling(handle); + return ret; + } + /* step3 : Send to slave data */ + ret = BlockingMasterTxDataOptStepNormal(handle); + if (ret != BASE_STATUS_OK) { + handle->errorCode = ret; + SetErrorHandling(handle); + return ret; + } + /* step4 : send stop CMD */ + ret = BlockingSendStopCommand(handle); + + return ret; +} + +/** + * @brief Receiving data in blocking mode as slave. + * @param handle I2C handle. + * @param rData Address of the data buff to be receiving. + * @param dataSize Number of the data to be receiving. + * @param timeout Timeout period,unit: ms. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SlaveReadBlocking(I2C_Handle *handle, unsigned char *rData, + unsigned int dataSize, unsigned int timeout) +{ + I2C_ASSERT_PARAM(handle != NULL && rData != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(timeout > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + + BASE_StatusType ret = BASE_STATUS_OK; + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + + /* Configuring I2C Parameters. */ + handle->state = I2C_STATE_BUSY_SLAVE_RX; + handle->transferBuff = rData; + handle->transferSize = dataSize; + handle->transferCount = 0; + handle->timeout = timeout; + + /* step1 : Parameter Settings. */ + I2C_ConfigParametersAndStartBlocking(handle, I2C_SLAVE_STATUS); + /* step2 : Waiting for slave address match. */ + ret = WaitStatusReady(handle, SLAVE_ADDRESS_MATCH, I2C_OPERATION_WRITE); + if (ret != BASE_STATUS_OK) { + handle->errorCode = ret; + SetErrorHandling(handle); + return ret; + } + /* step3 : Slave receives data from the master device. */ + ret = BlockingSlaveRxDataOptStepNormal(handle); + if (ret != BASE_STATUS_OK) { + handle->errorCode = ret; + SetErrorHandling(handle); + return ret; + } + /* step4 : Send stop CMD */ + ret = BlockingSendStopCommand(handle); + + return ret; +} + +/** + * @brief Send data in blocking mode as slave. + * @param handle I2C handle. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be sent. + * @param timeout Timeout period,unit: ms. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SlaveWriteBlocking(I2C_Handle *handle, unsigned char *wData, + unsigned int dataSize, unsigned int timeout) +{ + I2C_ASSERT_PARAM(handle != NULL && wData != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(timeout > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + + BASE_StatusType ret = BASE_STATUS_OK; + /* Clean interrupt */ + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + + /* Configuring Transmission Parameters of I2C. */ + handle->state = I2C_STATE_BUSY_SLAVE_TX; + handle->transferBuff = wData; + handle->transferSize = dataSize; + handle->transferCount = 0; + handle->timeout = timeout; + + /* Parameter Settings. */ + I2C_ConfigParametersAndStartBlocking(handle, I2C_SLAVE_STATUS); + + /* step1 : Waiting for slave address match. */ + ret = WaitStatusReady(handle, SLAVE_ADDRESS_MATCH, I2C_OPERATION_READ); + if (ret != BASE_STATUS_OK) { + handle->errorCode = ret; + SetErrorHandling(handle); + return ret; + } + /* step2 : Slave send data to the master device. */ + while (handle->transferCount < (handle->transferSize - 1)) { + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_RD_TACK_S_TD_RACK, *handle->transferBuff); + if (ret != BASE_STATUS_OK) { + handle->errorCode = ret; + SetErrorHandling(handle); + return ret; + } + handle->transferBuff++; + handle->transferCount++; + } + /* step3 : Slave send last data without ack to the master device. */ + if (handle->transferCount == (handle->transferSize - 1)) { + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_RD_TNACK_S_TD_RNACK, *handle->transferBuff); + if (ret != BASE_STATUS_OK) { + handle->errorCode = ret; + SetErrorHandling(handle); + return ret; + } + } + /* step4 : send stop CMD */ + ret = BlockingSendStopCommand(handle); + + return ret; +} + +/** + * @brief Receiving data in interrupts mode. + * @param handle I2C handle. + * @param devAddr Slave Device Address. + * @param rData Address of the data buff to be receiving. + * @param dataSize Number of the data to be receiving. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_MasterReadIT(I2C_Handle *handle, unsigned short devAddr, + unsigned char *rData, unsigned int dataSize) +{ + I2C_ASSERT_PARAM(handle != NULL && rData != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_PARAM_CHECK_WITH_RET(devAddr <= I2C_MAX_DEV_ADDR, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + + unsigned int index; + /* Determine which I2C is used. */ + index = (handle->baseAddress == I2C0) ? I2C_INTERFACE_INDEX_0 : I2C_INTERFACE_INDEX_1; + + /* Configuring I2C Parameters. */ + handle->state = I2C_STATE_BUSY_MASTER_RX; + handle->transferBuff = rData; + handle->transferSize = dataSize; + handle->transferCount = 0; + SetSlaveDevAddr(handle, devAddr); + g_internalConfigParam[index].txReadCmdCnt = 0; + g_internalConfigParam[index].sendAddressStatus = I2C_SEND_ADDR_STATUS_READ; + + /* Clean interrupt */ + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + + /* Startup Control */ + handle->baseAddress->I2C_CTRL1.BIT.dma_operation = I2C_DMA_OP_NONE; + handle->baseAddress->I2C_CTRL1.BIT.rst_rx_fifo = BASE_CFG_SET; + handle->baseAddress->I2C_CTRL1.BIT.rst_tx_fifo = BASE_CFG_SET; + handle->baseAddress->I2C_CTRL1.BIT.mst_start = BASE_CFG_SET; + + /* Enable interrupt */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_CFG_INTERRUPT_MASTER_RX; + + return BASE_STATUS_OK; +} + +/** + * @brief Send data in interrupts mode. + * @param handle I2C handle. + * @param devAddr Slave Device Address. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_MasterWriteIT(I2C_Handle *handle, unsigned short devAddr, + unsigned char *wData, unsigned int dataSize) +{ + I2C_ASSERT_PARAM(handle != NULL && wData != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_PARAM_CHECK_WITH_RET(devAddr <= I2C_MAX_DEV_ADDR, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + + unsigned int index; + /* Determine which I2C is used. */ + index = (handle->baseAddress == I2C0) ? I2C_INTERFACE_INDEX_0 : I2C_INTERFACE_INDEX_1; + + /* Configuring I2C Parameters. */ + handle->state = I2C_STATE_BUSY_MASTER_TX; + handle->transferBuff = wData; + handle->transferSize = dataSize; + handle->transferCount = 0; + SetSlaveDevAddr(handle, devAddr); + g_internalConfigParam[index].txReadCmdCnt = 0; + g_internalConfigParam[index].sendAddressStatus = I2C_SEND_ADDR_STATUS_WRITE; + + /* Clean interrupt */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_RAW_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + + /* Startup Control */ + handle->baseAddress->I2C_CTRL1.BIT.dma_operation = I2C_DMA_OP_NONE; + handle->baseAddress->I2C_CTRL1.BIT.rst_rx_fifo = BASE_CFG_SET; + handle->baseAddress->I2C_CTRL1.BIT.rst_tx_fifo = BASE_CFG_SET; + handle->baseAddress->I2C_CTRL1.BIT.mst_start = BASE_CFG_SET; + + /* Enable interrupt */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_CFG_INTERRUPT_MASTER_TX; + + return BASE_STATUS_OK; +} + +/** + * @brief Receiving data in interrupts mode as slave. + * @param handle I2C handle. + * @param rData Address of the data buff to be receiving. + * @param dataSize Number of the data to be receiving. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SlaveReadIT(I2C_Handle *handle, unsigned char *rData, unsigned int dataSize) +{ + BASE_StatusType ret = BASE_STATUS_OK; + + I2C_ASSERT_PARAM(handle != NULL && rData != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + + /* Configuring Transmission Parameters of I2C. */ + handle->state = I2C_STATE_BUSY_SLAVE_RX; + handle->transferBuff = rData; + handle->transferSize = dataSize; + handle->transferCount = 0; + + /* Configuring the I2C Timing */ + ret = I2C_SlaveMultiplexIT(handle); + + return ret; +} + +/** + * @brief Send data in interrupts mode as slave. + * @param handle I2C handle. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SlaveWriteIT(I2C_Handle *handle, unsigned char *wData, unsigned int dataSize) +{ + BASE_StatusType ret = BASE_STATUS_OK; + + I2C_ASSERT_PARAM(handle != NULL && wData != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + + /* Configuring Transmission Parameters of I2C. */ + handle->state = I2C_STATE_BUSY_SLAVE_TX; + handle->transferBuff = wData; + handle->transferSize = dataSize; + handle->transferCount = 0; + + /* Configuring the I2C Timing */ + ret = I2C_SlaveMultiplexIT(handle); + return ret; +} + +/** + * @brief Receiving data in DMA mode. + * @param handle I2C handle. + * @param devAddr Slave Device Address. + * @param rData Address of the data buff to be receiving. + * @param dataSize Number of the data to be receiving. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_MasterReadDMA(I2C_Handle *handle, unsigned short devAddr, + unsigned char *rData, unsigned int dataSize) +{ + I2C_ASSERT_PARAM(handle != NULL && rData != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + /* Check the DMA transfer handle and channel. */ + I2C_ASSERT_PARAM(handle->dmaHandle != NULL); + I2C_PARAM_CHECK_WITH_RET((handle->txDmaCh < CHANNEL_MAX_NUM), BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET((handle->rxDmaCh < CHANNEL_MAX_NUM), BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET((handle->rxDmaCh != handle->txDmaCh), BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(devAddr <= I2C_MAX_DEV_ADDR, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + + BASE_StatusType ret = BASE_STATUS_OK; + + unsigned int index; + /* Determine which I2C is used. */ + index = (handle->baseAddress == I2C0) ? I2C_INTERFACE_INDEX_0 : I2C_INTERFACE_INDEX_1; + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + + /* Configuring I2C Parameters. */ + handle->state = I2C_STATE_BUSY_MASTER_RX; + handle->transferBuff = rData; + handle->transferSize = dataSize; + handle->transferCount = 0; + SetSlaveDevAddr(handle, devAddr); + + /* Waiting for the i2c bus to be idle. */ + ret = WaitStatusReady(handle, I2C_BUS_IS_FREE, I2C_SEND_ADDR_STATUS_READ); + if (ret != BASE_STATUS_OK) { + handle->errorCode = ret; + SetErrorHandling(handle); + return ret; + } + + /* Startup Control */ + handle->baseAddress->I2C_CTRL1.BIT.rst_rx_fifo = BASE_CFG_SET; + handle->baseAddress->I2C_CTRL1.BIT.rst_tx_fifo = BASE_CFG_SET; + handle->baseAddress->I2C_CTRL1.BIT.mst_start = BASE_CFG_SET; + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_S, 0); /* Sets the start command to be sent. */ + if (ret != BASE_STATUS_OK) { + SetErrorHandling(handle); + return ret; + } + ret = SendSlaveAddressReadCmd(handle, index); /* Send Address to Slave. */ + if (ret != BASE_STATUS_OK) { + handle->errorCode = ret; + SetErrorHandling(handle); + return ret; + } + ret = I2cTransferDataDma(handle, index); + return ret; +} + +/** + * @brief Send data in DMA mode. + * @param handle I2C handle. + * @param devAddr Slave Device Address. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_MasterWriteDMA(I2C_Handle *handle, unsigned short devAddr, + unsigned char *wData, unsigned int dataSize) +{ + I2C_ASSERT_PARAM(handle != NULL && wData != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + /* Check the DMA transfer handle and channel. */ + I2C_ASSERT_PARAM(handle->dmaHandle != NULL); + I2C_PARAM_CHECK_WITH_RET((handle->txDmaCh < CHANNEL_MAX_NUM), BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(devAddr <= I2C_MAX_DEV_ADDR, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + + BASE_StatusType ret = BASE_STATUS_OK; + unsigned int index; + /* Determine which I2C is used. */ + index = (handle->baseAddress == I2C0) ? I2C_INTERFACE_INDEX_0 : I2C_INTERFACE_INDEX_1; + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + + /* Waiting for the i2c bus to be idle. */ + ret = WaitStatusReady(handle, I2C_BUS_IS_FREE, I2C_SEND_ADDR_STATUS_READ); + if (ret != BASE_STATUS_OK) { + handle->errorCode = ret; + SetErrorHandling(handle); + return ret; + } + /* Configuring I2C Parameters. */ + handle->state = I2C_STATE_BUSY_MASTER_TX; + handle->transferBuff = wData; + handle->transferSize = dataSize; + handle->transferCount = 0; + SetSlaveDevAddr(handle, devAddr); + + /* Startup Control */ + handle->baseAddress->I2C_CTRL1.BIT.rst_rx_fifo = BASE_CFG_SET; + handle->baseAddress->I2C_CTRL1.BIT.rst_tx_fifo = BASE_CFG_SET; + handle->baseAddress->I2C_CTRL1.BIT.mst_start = BASE_CFG_SET; + /* Send I2C start */ + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_S, 0); /* Sets the start command to be sent. */ + if (ret != BASE_STATUS_OK) { + SetErrorHandling(handle); + return ret; + } + /* send slave addr */ + ret = SendSlaveAddressWriteCmd(handle, index); + if (ret != BASE_STATUS_OK) { + SetErrorHandling(handle); + return ret; + } + ret = I2cTransferDataDma(handle, index); + + return ret; +} + +/** + * @brief Receiving data in DMA mode as slave. + * @param handle I2C handle. + * @param rData Address of the data buff to be receiving. + * @param dataSize Number of the data to be receiving. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SlaveReadDMA(I2C_Handle *handle, unsigned char *rData, unsigned int dataSize) +{ + I2C_ASSERT_PARAM(handle != NULL && rData != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + /* Check the DMA transfer handle and channel. */ + I2C_ASSERT_PARAM(handle->dmaHandle != NULL); + I2C_PARAM_CHECK_WITH_RET((handle->txDmaCh < CHANNEL_MAX_NUM), BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET((handle->rxDmaCh < CHANNEL_MAX_NUM), BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET((handle->rxDmaCh != handle->txDmaCh), BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + + BASE_StatusType ret = BASE_STATUS_OK; + unsigned int index; + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + /* Configuring Transmission Parameters of I2C. */ + handle->state = I2C_STATE_BUSY_SLAVE_RX; + handle->transferSize = dataSize; + handle->transferBuff = rData; + handle->transferCount = 0; + + /* Startup Control */ + handle->baseAddress->I2C_CTRL1.BIT.rst_rx_fifo = BASE_CFG_SET; + handle->baseAddress->I2C_CTRL1.BIT.rst_tx_fifo = BASE_CFG_SET; + handle->baseAddress->I2C_CTRL1.BIT.mst_start = BASE_CFG_UNSET; + ret = WaitStatusReady(handle, SLAVE_ADDRESS_MATCH, I2C_OPERATION_WRITE); /* Waiting to match master. */ + if (ret != BASE_STATUS_OK) { + SetErrorHandling(handle); + return ret; + } + + /* Determine which I2C is used. */ + index = (handle->baseAddress == I2C0) ? I2C_INTERFACE_INDEX_0 : I2C_INTERFACE_INDEX_1; + I2cTransferDataDma(handle, index); + return ret; +} + +/** + * @brief Send data in DMA mode as slave. + * @param handle I2C handle. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SlaveWriteDMA(I2C_Handle *handle, unsigned char *wData, unsigned int dataSize) +{ + I2C_ASSERT_PARAM(handle != NULL && wData != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + /* Check the DMA transfer handle and channel. */ + I2C_ASSERT_PARAM(handle->dmaHandle != NULL); + I2C_PARAM_CHECK_WITH_RET((handle->txDmaCh < CHANNEL_MAX_NUM), BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + + BASE_StatusType ret = BASE_STATUS_OK; + unsigned int index; + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + /* Configuring Transmission Parameters of I2C. */ + handle->state = I2C_STATE_BUSY_SLAVE_TX; + handle->transferSize = dataSize; + handle->transferBuff = wData; + handle->transferCount = 0; + + /* Startup Control */ + handle->baseAddress->I2C_CTRL1.BIT.rst_rx_fifo = BASE_CFG_SET; + handle->baseAddress->I2C_CTRL1.BIT.rst_tx_fifo = BASE_CFG_SET; + handle->baseAddress->I2C_CTRL1.BIT.mst_start = BASE_CFG_UNSET; + /* Waiting for slave address match. */ + ret = WaitStatusReady(handle, SLAVE_ADDRESS_MATCH, I2C_OPERATION_READ); + if (ret != BASE_STATUS_OK) { + SetErrorHandling(handle); + return ret; + } + /* Determine which I2C is used. */ + index = (handle->baseAddress == I2C0) ? I2C_INTERFACE_INDEX_0 : I2C_INTERFACE_INDEX_1; + I2cTransferDataDma(handle, index); + return ret; +} + +/** + * @brief Interrupt Handling Function. + * @param handle Handle pointers + * @retval None + */ +void HAL_I2C_IrqHandler(void *handle) +{ + I2C_Handle *i2cHandle = (I2C_Handle *)handle; + I2C_ASSERT_PARAM(i2cHandle != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(i2cHandle->baseAddress)); + + unsigned int status; + unsigned int index; + + status = i2cHandle->baseAddress->I2C_INTR_STAT.reg; + i2cHandle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + if (IsInterruptErrorStatus(i2cHandle, status)) { + return; + } + /* Determine which I2C is used. */ + index = (i2cHandle->baseAddress == I2C0) ? I2C_INTERFACE_INDEX_0 : I2C_INTERFACE_INDEX_1; + /* Callback interrupt handler function. */ + InterruptHandle(i2cHandle, status, index); + if ((i2cHandle->transferCount >= i2cHandle->transferSize) && + (!(status & (I2C_INTR_RAW_ALL_CMD_DONE_MASK | I2C_INTR_RAW_STOP_DET_MASK)))) { + if (i2cHandle->baseAddress->I2C_FIFO_STAT.BIT.tx_fifo_vld_num < I2C_MAX_FIFO_SIZE) { + i2cHandle->baseAddress->I2C_TX_FIFO.reg = + (((unsigned int)I2C_CMD_P << I2C_TXFIFO_CMD_POS) & I2C_TXFIFO_CMD_MASK); + i2cHandle->baseAddress->I2C_INTR_EN.BIT.tx_fifo_not_full_en = BASE_CFG_DISABLE; + i2cHandle->transferCount++; + } + } + /* After all data transmission is complete, call the user's callback function. */ + InterruptAllDoneHandle(i2cHandle, status); +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/i2c/src/i2c_ex.c b/vendor/xinlingyu_92_3061M/Project/drivers/i2c/src/i2c_ex.c new file mode 100644 index 0000000000000000000000000000000000000000..29e584d5ec466fe838381b32e8b6f3310e532252 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/i2c/src/i2c_ex.c @@ -0,0 +1,166 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file i2c_ex.c + * @author MCU Driver Team + * @brief I2C module driver + * @details The header file contains the following declaration: + * + Setting the Special Function Configuration. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "i2c_ex.h" + +/* Macro definitions ---------------------------------------------------------*/ + +/** + * @brief Set data transfer sequence. + * @param handle: I2C handle. + * @param sequence: data transfer sequence enumeration value. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SetDataTransferSequenceEx(I2C_Handle *handle, I2C_DataTransferSequenceType sequence) +{ + I2C_ASSERT_PARAM(handle != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_PARAM_CHECK_WITH_RET(IsI2cDataTransferSequence(sequence), BASE_STATUS_ERROR); + /**< Data Transfer Sequence. 0:I2C_BIG_BIT_FIRST, 1:I2C_LITTLE_BIT_FIRST. */ + handle->baseAddress->I2C_MODE.BIT.lit_end = sequence; + return BASE_STATUS_OK; +} + +/** + * @brief Set I2C clock stretching function. + * @param handle: I2C handle. + * @param clkStretch: clock stretching enumeration value. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SetSclStretchModeEx(I2C_Handle *handle, I2C_ClockStretchType clkStretch) +{ + I2C_ASSERT_PARAM(handle != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_PARAM_CHECK_WITH_RET(IsI2cClockStretchValue(clkStretch), BASE_STATUS_ERROR); + /**< Clock stretching enable. 0:enable, 1:disable. */ + handle->baseAddress->I2C_MODE.BIT.scl_stretch_disable = clkStretch; + return BASE_STATUS_OK; +} + +/** + * @brief Set I2C SCL low-level timeout. + * @param handle: I2C handle. + * @param sclLowTimeout: SCL low-level timeout value. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SetSclLowTimeoutEx(I2C_Handle *handle, unsigned int sclLowTimeout) +{ + I2C_ASSERT_PARAM(handle != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_PARAM_CHECK_WITH_RET(IsI2cSclLowTimeout(sclLowTimeout), BASE_STATUS_ERROR); + /* The unit of bus free time is I2C working clock cycle. */ + handle->baseAddress->I2C_SCL_TIMEOUT.BIT.scl_low_timeout = sclLowTimeout; + return BASE_STATUS_OK; +} + +/** + * @brief Set I2C bus idle threshold value. + * @param handle: I2C handle. + * @param busFreeTime: bus idle threshold value. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SetBusFreeTimeEx(I2C_Handle *handle, unsigned int busFreeTime) +{ + I2C_ASSERT_PARAM(handle != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_PARAM_CHECK_WITH_RET(IsI2cBusFreeTime(busFreeTime), BASE_STATUS_ERROR); + /* The unit of bus free time is I2C working clock cycle. */ + handle->baseAddress->I2C_BUS_FREE.BIT.bus_free_time = busFreeTime; + return BASE_STATUS_OK; +} + +/** + * @brief Set I2C slave receive 10-bit slave addressing. + * @param handle: I2C handle. + * @param arg: slave special function set enumeration value. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_Set10BitSlaveEnableEx(I2C_Handle *handle) +{ + I2C_ASSERT_PARAM(handle != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + /**< Enable the slave receives the 10bit addressing. */ + handle->baseAddress->I2C_OWN_ADDR.BIT.i2c_10bit_slave_en = BASE_CFG_SET; + return BASE_STATUS_OK; +} + +/** + * @brief Set I2C slave receive device ID address. + * @param handle: I2C handle. + * @param arg: slave special function set enumeration value. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SetDeviceIdAddressEnableEx(I2C_Handle *handle) +{ + I2C_ASSERT_PARAM(handle != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + /**< Enable the function of receiving device ID addresses. */ + handle->baseAddress->I2C_OWN_ADDR.BIT.i2c_device_id_en = BASE_CFG_SET; + return BASE_STATUS_OK; +} + +/** + * @brief Set I2C slave receive start byte address. + * @param handle: I2C handle. + * @param arg: slave special function set enumeration value. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SetStartByteEnableEx(I2C_Handle *handle) +{ + I2C_ASSERT_PARAM(handle != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + handle->baseAddress->I2C_OWN_ADDR.BIT.i2c_start_byte_en = BASE_CFG_SET; /**< Enable receiving START Byte Address. */ + return BASE_STATUS_OK; +} + +/** + * @brief Set I2C slave own address mask. + * @param handle: I2C handle. + * @param addrMask: own address mask. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SetOwnAddressMaskEx(I2C_Handle *handle, unsigned int addrMask) +{ + I2C_ASSERT_PARAM(handle != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_PARAM_CHECK_WITH_RET(IsI2cOwnAddressOrMask(addrMask), BASE_STATUS_ERROR); + handle->baseAddress->I2C_OWN_ADDR.BIT.own_address_mask = addrMask; /**< Slave's own address mask. */ + return BASE_STATUS_OK; +} + +/** + * @brief Set I2C slave XMBus address mask. + * @param handle: I2C handle. + * @param addrMask: XMBus address mask. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SetOwnXmbAddressMaskEx(I2C_Handle *handle, unsigned int addrMask) +{ + I2C_ASSERT_PARAM(handle != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_PARAM_CHECK_WITH_RET(IsXMBusAddressOrMask(addrMask), BASE_STATUS_ERROR); + handle->baseAddress->XMB_DEV_ADDR.BIT.xmb_address_mask = addrMask; /**< The second own address mask as slave. */ + return BASE_STATUS_OK; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/iocmg/common/iocmg.h b/vendor/xinlingyu_92_3061M/Project/drivers/iocmg/common/iocmg.h new file mode 100644 index 0000000000000000000000000000000000000000..5127d7a69a2a61c651b2a0d1f21b9ad6b5a73790 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/iocmg/common/iocmg.h @@ -0,0 +1,92 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file iocmg.h + * @author MCU Driver Team + * @brief IOCMG module driver + * @details This file provides functions declaration of iocmg + */ +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_IOCMG_H +#define McuMagicTag_IOCMG_H + +/* Includes ------------------------------------------------------------------ */ +#include "iocmg_ip.h" +/** + * @defgroup IOCMG ICOMG + * @brief IOCMG module. + * @{ + */ + +/** + * @defgroup IOCMG_Common IOMG Common + * @brief IOCMG common external module. + * @{ + */ + +/** + * @defgroup IOCMG_Handle_Definition IOCMG Handle Definition + * @{ + */ +typedef struct { + unsigned int pinTypedef; + IOCMG_PullMode pullMode; + IOCMG_SchmidtMode schmidtMode; + IOCMG_LevelShiftRate levelShiftRate; + IOCMG_DriveRate driveRate; + IOCMG_ExtendHandle handleEx; /**< Extend handle, configuring some special parameters. */ +} IOCMG_Handle; +/** + * @} + */ + +/** + * @defgroup IOCMG_API_Declaration IOCMG HAL API + * @{ + */ +/* Exported global functions ------------------------------------------------- */ +IOCMG_Status HAL_IOCMG_Init(IOCMG_Handle* handle); +IOCMG_Status HAL_IOCMG_SetPinAltFuncMode(unsigned int pinTypedef); +IOCMG_Status HAL_IOCMG_SetPinPullMode(unsigned int pinTypedef, IOCMG_PullMode pullMode); +IOCMG_Status HAL_IOCMG_SetPinSchmidtMode(unsigned int pinTypedef, IOCMG_SchmidtMode schmidtMode); +IOCMG_Status HAL_IOCMG_SetPinLevelShiftRate(unsigned int pinTypedef, IOCMG_LevelShiftRate levelShiftRate); +IOCMG_Status HAL_IOCMG_SetPinDriveRate(unsigned int pinTypedef, IOCMG_DriveRate driveRate); + +IOCMG_Status HAL_IOCMG_SetOscClkOutputMode(bool mode); +IOCMG_Status HAL_IOCMG_SetOscClkFuncMode(bool mode); +IOCMG_Status HAL_IOCMG_SetOscClkDriveRate(IOCMG_OscClkDriveRate oscClkDriveRate); + +IOCMG_FuncMode HAL_IOCMG_GetPinAltFuncMode(unsigned int pinTypedef); +IOCMG_PullMode HAL_IOCMG_GetPinPullMode(unsigned int pinTypedef); +IOCMG_SchmidtMode HAL_IOCMG_GetPinSchmidtMode(unsigned int pinTypedef); +IOCMG_LevelShiftRate HAL_IOCMG_GetPinLevelShiftRate(unsigned int pinTypedef); +IOCMG_DriveRate HAL_IOCMG_GetPinDriveRate(unsigned int pinTypedef); +bool HAL_IOCMG_GetOscClkOutputMode(void); +bool HAL_IOCMG_GetOscClkFuncMode(void); +IOCMG_OscClkDriveRate HAL_IOCMG_GetOscClkDriveRate(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_IOCMG_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/iocmg/inc/iocmg_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/iocmg/inc/iocmg_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..050b4cec599a076766f071bb6893b7d0edda6354 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/iocmg/inc/iocmg_ip.h @@ -0,0 +1,348 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file iocmg_ip.h + * @author MCU Driver Team + * @brief IOCMG module driver + * @details This file provides IOConfig register mapping structure. + */ + +/* Macro definitions */ +#ifndef McuMagicTag_IOCMG_IP_H +#define McuMagicTag_IOCMG_IP_H + +/* Includes ------------------------------------------------------------------ */ +#include "baseinc.h" +#include "ioconfig.h" +#include "iomap.h" +/* Macro definitions ---------------------------------------------------------*/ +#ifdef IOCMG_PARAM_CHECK + #define IOCMG_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM + #define IOCMG_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET + #define IOCMG_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else + #define IOCMG_ASSERT_PARAM(para) ((void)0U) + #define IOCMG_PARAM_CHECK_NO_RET(para) ((void)0U) + #define IOCMG_PARAM_CHECK_WITH_RET(param, ret) ((void)0U) +#endif +/** + * @addtogroup IOCMG + * @{ + */ + +/** + * @defgroup IOCMG_IP + * @{ + */ +#define IOCMG_BASE_ADDR_MASK 0xFFFF0000 +#define IOCMG_FUNC_NUM_MASK 0x0000000F +#define IOCMG_REG_VALUE_MASK 0x0000FFFF +/** + * @defgroup IOCMG_Param_Def IOCMG Parameters Definition + * @brief Description of IOCMG configuration parameters. + * @{ + */ +typedef enum { + FUNC_MODE_0 = 0u, + FUNC_MODE_1, + FUNC_MODE_2, + FUNC_MODE_3, + FUNC_MODE_4, + FUNC_MODE_5, + FUNC_MODE_6, + FUNC_MODE_7, + FUNC_MODE_8, + FUNC_MODE_9, + FUNC_MODE_10, + FUNC_MODE_11, + FUNC_MODE_12, + FUNC_MODE_13, + FUNC_MODE_14, + FUNC_MODE_15, + FUNC_MODE_MAX +} IOCMG_FuncMode; + +typedef enum { + SCHMIDT_DISABLE = 0u, + SCHMIDT_ENABLE +} IOCMG_SchmidtMode; + +typedef enum { + PULL_NONE = 0u, + PULL_DOWN, + PULL_UP, + PULL_BOTH, + PULL_MODE_MAX +} IOCMG_PullMode; + +typedef enum { + LEVEL_SHIFT_RATE_FAST = 0u, + LEVEL_SHIFT_RATE_SLOW, + LEVEL_SHIFT_RATE_MAX +} IOCMG_LevelShiftRate; + +typedef enum { + DRIVER_RATE_4 = 0u, + DRIVER_RATE_3, + DRIVER_RATE_2, + DRIVER_RATE_1, + DRIVER_RATE_MAX +} IOCMG_DriveRate; + +typedef enum { + OSC_CLK_DRIVER_RATE_1 = 0u, + OSC_CLK_DRIVER_RATE_2, + OSC_CLK_DRIVER_RATE_3, + OSC_CLK_DRIVER_RATE_4, + OSC_CLK_DRIVER_RATE_MAX +} IOCMG_OscClkDriveRate; + +typedef enum { + IOCMG_STATUS_OK, + IOCMG_BASE_ADDR_ERROR, + IOCMG_REG_ADDR_ERROR, + IOCMG_PIN_FUNC_ERROR, + IOCMG_PARAM_ERROR +} IOCMG_Status; + +/** + * @brief IOCMG extend handle, configuring some special parameters. + */ +typedef struct { +} IOCMG_ExtendHandle; +/** + * @} + */ + +/** + * @brief Set iocmg reg value. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @param regValue value of @ref IOCMG_REG. + * @retval None. + */ +static inline void DCL_IOCMG_SetRegValue(IOCMG_REG *iocmgRegx, unsigned int regValue) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + iocmgRegx->reg = regValue; +} + +/** + * @brief Get iocmg reg value. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @retval None. + */ +static inline unsigned int DCL_IOCMG_GetRegValue(IOCMG_REG *iocmgRegx) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + return iocmgRegx->reg; +} + +/** + * @brief Set iocmg function number mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @param funcnum value of @ref IOCMG_FuncMode. + * @retval None. + */ +static inline void DCL_IOCMG_SetFuncNum(IOCMG_REG *iocmgRegx, IOCMG_FuncMode funcnum) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + IOCMG_PARAM_CHECK_NO_RET(funcnum < FUNC_MODE_MAX && funcnum >= FUNC_MODE_0); + iocmgRegx->BIT.func = funcnum; +} + +/** + * @brief Get iocmg function number mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @retval Value of @ref IOCMG_FuncMode. + */ +static inline IOCMG_FuncMode DCL_IOCMG_GetFuncMode(IOCMG_REG *iocmgRegx) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + return iocmgRegx->BIT.func; +} + +/** + * @brief Set iocmg drive rate mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @param driveRate value of @ref IOCMG_DriveRate. + * @retval None. + */ +static inline void DCL_IOCMG_SetDriveRate(IOCMG_REG *iocmgRegx, IOCMG_DriveRate driveRate) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + IOCMG_PARAM_CHECK_NO_RET(driveRate < DRIVER_RATE_MAX && driveRate >= DRIVER_RATE_4); + iocmgRegx->BIT.ds = driveRate; +} + +/** + * @brief Get iocmg drive rate mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @retval Value of @ref IOCMG_DriveRate. + */ +static inline IOCMG_DriveRate DCL_IOCMG_GetDriveRate(IOCMG_REG *iocmgRegx) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + return iocmgRegx->BIT.ds; +} + +/** + * @brief Set iocmg pull up or down mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @param pullMode value of @ref IOCMG_PullMode. + * @retval None. + */ +static inline void DCL_IOCMG_SetPullMode(IOCMG_REG *iocmgRegx, IOCMG_PullMode pullMode) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + IOCMG_PARAM_CHECK_NO_RET(pullMode < PULL_MODE_MAX && pullMode >= PULL_NONE); + iocmgRegx->BIT.pu = (pullMode & 0x02) >> 1; /* 10b: pull up mode */ + iocmgRegx->BIT.pd = pullMode & 0x01; /* 01b: pull down mode */ +} + +/** + * @brief Get iocmg pull up or down mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @retval pullMode value of @ref IOCMG_PullMode. + */ +static inline IOCMG_PullMode DCL_IOCMG_GetPullMode(IOCMG_REG *iocmgRegx) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + unsigned int pullUpMode = iocmgRegx->BIT.pu; + unsigned int pullDownMode = iocmgRegx->BIT.pd; + return (pullUpMode << 1) | pullDownMode; /* 1: shift for up mode bit */ +} + +/** + * @brief Set iocmg level shift rate mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @param levelShiftRate value of @ref IOCMG_LevelShiftRate. + * @retval None. + */ +static inline void DCL_IOCMG_SetLevelShiftRate(IOCMG_REG *iocmgRegx, IOCMG_LevelShiftRate levelShiftRate) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + IOCMG_PARAM_CHECK_NO_RET(levelShiftRate < LEVEL_SHIFT_RATE_MAX && levelShiftRate >= LEVEL_SHIFT_RATE_FAST); + iocmgRegx->BIT.sr = levelShiftRate; +} + +/** + * @brief Get iocmg level shift rate mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @retval levelShiftRate value of @ref IOCMG_LevelShiftRate. + */ +static inline IOCMG_LevelShiftRate DCL_IOCMG_GetLevelShiftRate(IOCMG_REG *iocmgRegx) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + return iocmgRegx->BIT.sr; +} + +/** + * @brief Set iocmg schmidt enable mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @param schmidtMode value of @ref IOCMG_SchmidtMode. + * @retval None. + */ +static inline void DCL_IOCMG_SetSchmidtMode(IOCMG_REG *iocmgRegx, IOCMG_SchmidtMode schmidtMode) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + IOCMG_PARAM_CHECK_NO_RET(schmidtMode <= SCHMIDT_ENABLE && schmidtMode >= SCHMIDT_DISABLE); + iocmgRegx->BIT.se = schmidtMode; +} + +/** + * @brief Get iocmg schmidt enable mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @retval schmidtMode value of @ref IOCMG_SchmidtMode. + */ +static inline IOCMG_SchmidtMode DCL_IOCMG_GetSchmidtMode(IOCMG_REG *iocmgRegx) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + return iocmgRegx->BIT.se; +} + +/** + * @brief set iocmg OSC clock output mode. + * @param mode function enable or not. + * @retval None. + */ +static inline void DCL_IOCMG_SetOscClkOutputMode(bool mode) +{ + IOCMG_ASSERT_PARAM(mode == BASE_CFG_ENABLE || mode == BASE_CFG_DISABLE); + SYSCTRL1->XTAL_CFG.BIT.ose_e = mode; +} + +/** + * @brief Get iocmg OSC clock output mode. + * @param None + * @retval None. + */ +static inline bool DCL_IOCMG_GetOscClkOutputMode(void) +{ + return SYSCTRL1->XTAL_CFG.BIT.ose_e; +} + +/** + * @brief set iocmg OSC clock output mode. + * @param mode function enable or not. + * @retval None. + */ +static inline void DCL_IOCMG_SetOscClkFuncMode(bool mode) +{ + IOCMG_ASSERT_PARAM(mode == BASE_CFG_ENABLE || mode == BASE_CFG_DISABLE); + SYSCTRL1->XTAL_CFG.BIT.osc_ie = mode; +} + +/** + * @brief Get iocmg OSC clock output enable mode. + * @param None. + * @retval None. + */ +static inline bool DCL_IOCMG_GetOscClkFuncMode(void) +{ + return SYSCTRL1->XTAL_CFG.BIT.osc_ie; +} + +/** + * @brief Set iocmg OSC drive rate mode. + * @param oscClkDriveRate value of @ref IOCMG_DriveRate. + * @retval None. + */ +static inline void DCL_IOCMG_SetOscClkDriveRate(IOCMG_OscClkDriveRate oscClkDriveRate) +{ + IOCMG_PARAM_CHECK_NO_RET(oscClkDriveRate < OSC_CLK_DRIVER_RATE_MAX && oscClkDriveRate >= OSC_CLK_DRIVER_RATE_1); + SYSCTRL1->XTAL_CFG.BIT.osc_ds = oscClkDriveRate; +} + +/** + * @brief Get iocmg OSC drive rate mode. + * @param None. + * @retval oscClkDriveRate value of @ref IOCMG_DriveRate. + */ +static inline IOCMG_DriveRate DCL_IOCMG_GetOscClkDriveRate(void) +{ + return SYSCTRL1->XTAL_CFG.BIT.osc_ds; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_IOCMG_IP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/iocmg/src/iocmg.c b/vendor/xinlingyu_92_3061M/Project/drivers/iocmg/src/iocmg.c new file mode 100644 index 0000000000000000000000000000000000000000..f9d0d94ef2f9508a047821b14b04c9b1e7323c7e --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/iocmg/src/iocmg.c @@ -0,0 +1,283 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file iocmg.c + * @author MCU Driver Team + * @brief Provides functions about iocmg reg init and config. + */ + +/* Includes ---------------------------------------------------------------------- */ +#include "iocmg.h" +/* param definition -------------------------------------------------------------- */ +/* Function declaration----------------------------------------------------------- */ +static IOCMG_REG* IOCMG_GetRegAddr(unsigned int pinTypedef); + +IOCMG_Status HAL_IOCMG_Init(IOCMG_Handle* handle); +IOCMG_Status HAL_IOCMG_SetPinAltFuncMode(unsigned int pinTypedef); +IOCMG_Status HAL_IOCMG_SetPinPullMode(unsigned int pinTypedef, IOCMG_PullMode pullMode); +IOCMG_Status HAL_IOCMG_SetPinSchmidtMode(unsigned int pinTypedef, IOCMG_SchmidtMode schmidtMode); +IOCMG_Status HAL_IOCMG_SetPinLevelShiftRate(unsigned int pinTypedef, IOCMG_LevelShiftRate levelShiftRate); +IOCMG_Status HAL_IOCMG_SetPinDriveRate(unsigned int pinTypedef, IOCMG_DriveRate driveRate); +IOCMG_Status HAL_IOCMG_SetOscClkOutputMode(bool mode); +IOCMG_Status HAL_IOCMG_SetOscClkFuncMode(bool mode); +IOCMG_Status HAL_IOCMG_SetOscClkDriveRate(IOCMG_OscClkDriveRate oscClkDriveRate); + +IOCMG_FuncMode HAL_IOCMG_GetPinAltFuncMode(unsigned int pinTypedef); +IOCMG_PullMode HAL_IOCMG_GetPinPullMode(unsigned int pinTypedef); +IOCMG_SchmidtMode HAL_IOCMG_GetPinSchmidtMode(unsigned int pinTypedef); +IOCMG_LevelShiftRate HAL_IOCMG_GetPinLevelShiftRate(unsigned int pinTypedef); +IOCMG_DriveRate HAL_IOCMG_GetPinDriveRate(unsigned int pinTypedef); +bool HAL_IOCMG_GetOscClkOutputMode(void); +bool HAL_IOCMG_GetOscClkFuncMode(void); +IOCMG_OscClkDriveRate HAL_IOCMG_GetOscClkDriveRate(void); +/* Function definiton----------------------------------------------------------- */ +/** + * @brief Get pins iocmg reg address + * @param pinTypedef the pin type defined in iomap.h + * @retval IOCMG_REG iocmg reg address. + */ +static IOCMG_REG* IOCMG_GetRegAddr(unsigned int pinTypedef) +{ + /* decode pin's iocmg reg offset address in base address, and conver value to point address */ + unsigned int iocmgBaseAddrValue = (uintptr_t)IOCMG_BASE; + unsigned int iocmgRegOffsetAddrValue = (pinTypedef >> 16) & 0x00000FFF; /* 16 : shift 16 bit */ + IOCMG_REG* iocmgRegxAddr = (IOCMG_REG*)(void*)(iocmgBaseAddrValue + iocmgRegOffsetAddrValue); + if (!IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegxAddr & IOCMG_BASE_ADDR_MASK))) { + return NULL; + } + return iocmgRegxAddr; +} + +/** + * @brief Initial IOCMG reg by pin number and function mode. + * @param handle IOCMG_Handle. + * @retval status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_Init(IOCMG_Handle* handle) +{ + IOCMG_ASSERT_PARAM(handle != NULL); + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(handle->pinTypedef); + IOCMG_REG regValue = {0}; + regValue.BIT.func = (handle->pinTypedef & IOCMG_FUNC_NUM_MASK); + regValue.BIT.ds = handle->driveRate; + regValue.BIT.pd = handle->pullMode & 0x01; /* bit0 : pd */ + regValue.BIT.pu = handle->pullMode >> 1; /* bit1 : pu */ + regValue.BIT.se = handle->schmidtMode; + regValue.BIT.sr = handle->levelShiftRate; + DCL_IOCMG_SetRegValue(iocmgRegx, regValue.reg); + return IOCMG_STATUS_OK; +} + +/** + * @brief Set pins as function mode + * @param pinTypedef the pin type defined in iomap.h + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetPinAltFuncMode(unsigned int pinTypedef) +{ + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + /* get iocmg reg default value */ + unsigned int regValue = pinTypedef & IOCMG_REG_VALUE_MASK; + DCL_IOCMG_SetRegValue(iocmgRegx, regValue); + return IOCMG_STATUS_OK; +} + +/** + * @brief Get pins func number + * @param pinTypedef the pin type defined in iomap.h + * @retval pin func number @ref IOCMG_FuncMode. + */ +IOCMG_FuncMode HAL_IOCMG_GetPinAltFuncMode(unsigned int pinTypedef) +{ + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + return DCL_IOCMG_GetFuncMode(iocmgRegx); +} + +/** + * @brief Set pins pull mode + * @param pinTypedef the pin type defined in iomap.h + * @param pullMode function define as @ref IOCMG_PullMode + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetPinPullMode(unsigned int pinTypedef, IOCMG_PullMode pullMode) +{ + IOCMG_PARAM_CHECK_WITH_RET(pullMode < PULL_MODE_MAX && pullMode >= PULL_NONE, IOCMG_PARAM_ERROR); + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + DCL_IOCMG_SetPullMode(iocmgRegx, pullMode); + return IOCMG_STATUS_OK; +} + +/** + * @brief Get pins pull mode + * @param pinTypedef the pin type defined in iomap.h + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_PullMode HAL_IOCMG_GetPinPullMode(unsigned int pinTypedef) +{ + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + return DCL_IOCMG_GetPullMode(iocmgRegx); +} + +/** + * @brief Set Pin Schmidt Mode + * @param pinTypedef the pin type defined in iomap.h + * @param schmidtMode function define as @ref IOCMG_SchmidtMode + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetPinSchmidtMode(unsigned int pinTypedef, IOCMG_SchmidtMode schmidtMode) +{ + IOCMG_PARAM_CHECK_WITH_RET(schmidtMode <= SCHMIDT_ENABLE && schmidtMode >= SCHMIDT_DISABLE, IOCMG_PARAM_ERROR); + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + DCL_IOCMG_SetSchmidtMode(iocmgRegx, schmidtMode); + return IOCMG_STATUS_OK; +} + +/** + * @brief Get Pin Schmidt Mode + * @param pinTypedef the pin type defined in iomap.h + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_SchmidtMode HAL_IOCMG_GetPinSchmidtMode(unsigned int pinTypedef) +{ + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + return DCL_IOCMG_GetSchmidtMode(iocmgRegx); +} + +/** + * @brief Set Pin level Shift Rate Mode + * @param pinTypedef the pin type defined in iomap.h + * @param schmidtMode function define as @ref IOCMG_SchmidtMode + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetPinLevelShiftRate(unsigned int pinTypedef, IOCMG_LevelShiftRate levelShiftRate) +{ + IOCMG_PARAM_CHECK_WITH_RET(levelShiftRate < LEVEL_SHIFT_RATE_MAX, IOCMG_PARAM_ERROR); + IOCMG_PARAM_CHECK_WITH_RET(levelShiftRate >= LEVEL_SHIFT_RATE_FAST, IOCMG_PARAM_ERROR); + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + DCL_IOCMG_SetLevelShiftRate(iocmgRegx, levelShiftRate); + return IOCMG_STATUS_OK; +} + +/** + * @brief Get Pin Schmidt Mode + * @param pinTypedef the pin type defined in iomap.h + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_LevelShiftRate HAL_IOCMG_GetPinLevelShiftRate(unsigned int pinTypedef) +{ + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + return DCL_IOCMG_GetLevelShiftRate(iocmgRegx); +} + +/** + * @brief Set Pin drive Rate Mode + * @param pinTypedef the pin type defined in iomap.h + * @param driveRate function define as @ref IOCMG_DriveRate + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetPinDriveRate(unsigned int pinTypedef, IOCMG_DriveRate driveRate) +{ + /* get iocmg reg address */ + IOCMG_PARAM_CHECK_WITH_RET(driveRate < DRIVER_RATE_MAX && driveRate >= DRIVER_RATE_4, IOCMG_PARAM_ERROR); + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + DCL_IOCMG_SetDriveRate(iocmgRegx, driveRate); + return IOCMG_STATUS_OK; +} + +/** + * @brief Get Pin drive Rate Mode + * @param pinTypedef the pin type defined in iomap.h + * @retval Value of @ref IOCMG_DriveRate. + */ +IOCMG_DriveRate HAL_IOCMG_GetPinDriveRate(unsigned int pinTypedef) +{ + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + return DCL_IOCMG_GetDriveRate(iocmgRegx); +} + +/** + * @brief Set OSC Pin clock output enable mode + * @param mode function enable or not + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetOscClkOutputMode(bool mode) +{ + IOCMG_ASSERT_PARAM(mode == BASE_CFG_ENABLE || mode == BASE_CFG_DISABLE); + DCL_IOCMG_SetOscClkOutputMode(mode); + return IOCMG_STATUS_OK; +} + +/** + * @brief Get OSC Pin clock output enable mode + * @retval bool enable or not + */ +bool HAL_IOCMG_GetOscClkOutputMode(void) +{ + return DCL_IOCMG_GetOscClkOutputMode(); +} + +/** + * @brief Set OSC Pin function enable mode + * @param mode function enable or not + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetOscClkFuncMode(bool mode) +{ + IOCMG_ASSERT_PARAM(mode == BASE_CFG_ENABLE || mode == BASE_CFG_DISABLE); + DCL_IOCMG_SetOscClkFuncMode(mode); + return IOCMG_STATUS_OK; +} + +/** + * @brief Get OSC Pin Pin function enable mode + * @retval bool enable or not + */ +bool HAL_IOCMG_GetOscClkFuncMode(void) +{ + return DCL_IOCMG_GetOscClkFuncMode(); +} + +/** + * @brief Set OSC Pin drive rate mode + * @param driveRate osc drive rate + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetOscClkDriveRate(IOCMG_OscClkDriveRate oscClkDriveRate) +{ + IOCMG_PARAM_CHECK_WITH_RET(oscClkDriveRate < OSC_CLK_DRIVER_RATE_MAX && \ + oscClkDriveRate >= OSC_CLK_DRIVER_RATE_1, IOCMG_PARAM_ERROR); + DCL_IOCMG_SetOscClkDriveRate(oscClkDriveRate); + return IOCMG_STATUS_OK; +} + +/** + * @brief Get OSC Pin drive rate mode + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_OscClkDriveRate HAL_IOCMG_GetOscClkDriveRate(void) +{ + return DCL_IOCMG_GetOscClkDriveRate(); +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/iwdg/common/inc/iwdg.h b/vendor/xinlingyu_92_3061M/Project/drivers/iwdg/common/inc/iwdg.h new file mode 100644 index 0000000000000000000000000000000000000000..48dc1086b3c3423d2666d172bcf8bb41b6db8128 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/iwdg/common/inc/iwdg.h @@ -0,0 +1,97 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file iwdg.h + * @author MCU Driver Team + * @brief IWDG module driver + * @details The header file contains the following declaration: + * + IWDG handle structure definition. + * + Initialization functions. + * + IWDG Set And Get Functions. + * + Interrupt Handler Functions. + */ + +#ifndef McuMagicTag_IWDG_H +#define McuMagicTag_IWDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "iwdg_ip.h" +/** + * @defgroup IWDG IWDG + * @brief IWDG module. + * @{ + */ + +/** + * @defgroup IWDG_Common IWDG Common + * @brief IWDG common external module. + * @{ + */ + +/** + * @defgroup IWDG_Handle_Definition IWDG Handle Definition + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ +typedef void (* IWDG_CallbackType)(void *handle); + +/** + * @brief IWDG handle structure definition. + */ +typedef struct _IWDG_Handle { + IWDG_RegStruct *baseAddress; /**< IWDG Registers address. */ + unsigned int timeValue; /**< IWDG time value. */ + unsigned int freqDivValue; /**< IWDG freq div value. */ + IWDG_TimeType timeType; /**< IWDG time type. */ + bool enableIT; /**< true:enable false:disable interrupt. */ + IWDG_UserCallBack userCallBack; /**< User callback */ + IWDG_ExtendHandle handleEx; /**< IWDG extend parameter */ +} IWDG_Handle; + +/** + * @} + */ + +/** + * @defgroup IWDG_API_Declaration IWDG HAL API + * @{ + */ + +BASE_StatusType HAL_IWDG_Init(IWDG_Handle *handle); +void HAL_IWDG_SetTimeValue(IWDG_Handle *handle, unsigned int timeValue, IWDG_TimeType timeType); +unsigned int HAL_IWDG_GetLoadValue(IWDG_Handle *handle); +unsigned int HAL_IWDG_GetCounterValue(IWDG_Handle *handle); +void HAL_IWDG_Refresh(IWDG_Handle *handle); +void HAL_IWDG_Start(IWDG_Handle *handle); +void HAL_IWDG_Stop(IWDG_Handle *handle); +void HAL_IWDG_RegisterCallback(IWDG_Handle *handle, IWDG_CallbackType callBackFunc); +void HAL_IWDG_IrqHandler(void *handle); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_IWDG_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/iwdg/inc/iwdg_ex.h b/vendor/xinlingyu_92_3061M/Project/drivers/iwdg/inc/iwdg_ex.h new file mode 100644 index 0000000000000000000000000000000000000000..3467382a61769f377d2cb40e89324993bd4350cd --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/iwdg/inc/iwdg_ex.h @@ -0,0 +1,50 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file iwdg_ex.h + * @author MCU Driver Team + * @brief IWDG module driver + * @details The header file contains the following declaration: + * + IWDG Set And Get Functions. + */ + +#ifndef McuMagicTag_IWDG_EX_H +#define McuMagicTag_IWDG_EX_H + +/* Includes ------------------------------------------------------------------*/ +#include "iwdg.h" +/** + * @addtogroup IWDG_IP + * @{ + */ + +/** + * @defgroup IWDG_API_EX_Declaration IWDG HAL API EX + * @{ + */ +void HAL_IWDG_SetWindowValueEx(IWDG_Handle *handle, unsigned int windowValue, IWDG_TimeType timeType); +unsigned int HAL_IWDG_GetWindowValueEx(IWDG_Handle *handle); +void HAL_IWDG_EnableWindowModeEx(IWDG_Handle *handle); +void HAL_IWDG_DisableWindowModeEx(IWDG_Handle *handle); +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_IWDG_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/iwdg/inc/iwdg_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/iwdg/inc/iwdg_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..470629db788364cc108d65b16477b2eb0d71c585 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/iwdg/inc/iwdg_ip.h @@ -0,0 +1,439 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file iwdg_ip.h + * @author MCU Driver Team + * @brief IWDG module driver + * @details The header file contains the following declaration: + * + IWDG configuration enums. + * + IWDG register structures. + * + IWDG DCL Functions. + * + Parameters check functions. + */ + +#ifndef McuMagicTag_IWDG_IP_H +#define McuMagicTag_IWDG_IP_H + +/* Includes ------------------------------------------------------------------*/ +#include "baseinc.h" + +/* Macro definition */ + +#ifdef IWDG_PARAM_CHECK + #define IWDG_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM + #define IWDG_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET + #define IWDG_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else + #define IWDG_ASSERT_PARAM(para) ((void)0U) + #define IWDG_PARAM_CHECK_NO_RET(para) ((void)0U) + #define IWDG_PARAM_CHECK_WITH_RET(param, ret) ((void)0U) +#endif + +/** + * @addtogroup IWDG + * @{ + */ + +/** + * @defgroup IWDG_IP IWDG_IP + * @brief IWDG_IP: iwdg_v1. + * @{ + */ + +/** + * @defgroup IWDG_Param_Def IWDG Parameters Definition + * @brief Description of IWDG configuration parameters. + * @{ + */ +/* MACRO definitions -------------------------------------------------------*/ +#define FREQ_CONVERT_MS_UNIT 1000 +#define FREQ_CONVERT_US_UNIT 1000000 +#define IWDG_UNLOCK_REG_CMD 0x55 /* 0x55 CMD: key equal 0x55 will unlock all reg write function */ +#define IWDG_LOCK_REG_CMD 0xFF /* 0xFF CMD: key not equal 0x55 will lock reg write function except key reg */ + +/* Typedef definitions -------------------------------------------------------*/ +typedef enum { + IWDG_TIME_UNIT_TICK = 0x00000000U, + IWDG_TIME_UNIT_S = 0x00000001U, + IWDG_TIME_UNIT_MS = 0x00000002U, + IWDG_TIME_UNIT_US = 0x00000003U +} IWDG_TimeType; + +typedef enum { + IWDG_FREQ_DIV_NONE = 0x00000000U, + IWDG_FREQ_DIV_2 = 0x00000001U, + IWDG_FREQ_DIV_4 = 0x00000002U, + IWDG_FREQ_DIV_8 = 0x00000003U, + IWDG_FREQ_DIV_16 = 0x00000004U, + IWDG_FREQ_DIV_32 = 0x00000005U, + IWDG_FREQ_DIV_64 = 0x00000006U, + IWDG_FREQ_DIV_128 = 0x00000007U, + IWDG_FREQ_DIV_256 = 0x00000008U, + IWDG_FREQ_DIV_MAX +} IWDG_FreqDivType; + +/** + * @brief IWDG extend handle. + */ +typedef struct _IWDG_ExtendHandle { +} IWDG_ExtendHandle; + +/** + * @brief IWDG user callback. + */ +typedef struct { + void (* CallbackFunc)(void *handle); /**< IWDG callback Function */ +} IWDG_UserCallBack; +/** + * @} + */ + +/** + * @defgroup IWDG_Reg_Def IWDG Register Definition + * @brief Description IWDG register mapping structure. + * @{ + */ +/** + * @brief IWDG load init value. + */ +typedef union { + unsigned int reg; + struct { + unsigned int iwdg_load : 8; /**< init value. */ + unsigned int reserved0 : 24; + } BIT; +} volatile IWDG_LOAD_REG; + +/** + * @brief IWDG get current value. + */ +typedef union { + unsigned int reg; + struct { + unsigned int iwdg_value : 8; /**< current value. */ + unsigned int reserved0 : 24; + } BIT; +} volatile IWDG_VALUE_REG; + +/** + * @brief IWDG set window value. + */ +typedef union { + unsigned int reg; + struct { + unsigned int iwdg_window : 8; /**< window value. */ + unsigned int reserved0 : 24; + } BIT; +} volatile IWDG_WINDOW_REG; + +/** + * @brief IWDG cmd function value. + */ +typedef union { + unsigned int reg; + struct { + unsigned int iwdg_key : 8; /**< cmd function value. */ + unsigned int reserved0 : 24; + } BIT; +} volatile IWDG_KEY_REG; + +/** + * @brief IWDG clk pre div value. + */ +typedef union { + unsigned int reg; + struct { + unsigned int iwdg_pre_div : 4; /**< clk pre div value. */ + unsigned int reserved0 : 28; + } BIT; +} volatile IWDG_PRE_DIV_REG; + +/** + * @brief IWDG enable interrupt and reset. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int resen : 1; /**< enable reset. */ + unsigned int window_mode_en : 1; /**< enable window mode. */ + unsigned int reserved1 : 29; + } BIT; +} volatile IWDG_CONTROL_REG; + +/** + * @brief IWDG Register Structure definition. + */ +typedef struct { + IWDG_LOAD_REG IWDOG_LOAD; /**< IWDG load value register. */ + IWDG_VALUE_REG IWDOG_VALUE; /**< IWDG current value register. */ + IWDG_WINDOW_REG IWDOG_WINDOW; /**< IWDG Window value register. */ + IWDG_KEY_REG IWDOG_KEY; /**< IWDG instruction word register. */ + IWDG_PRE_DIV_REG IWDOG_PRE_DIV; /**< IWDG prescale register. */ + IWDG_CONTROL_REG IWDOG_CONTROL; /**< IWDG interrupt, reset and window enable register. */ +} volatile IWDG_RegStruct; + +/** + * @} + */ + +/** + * @brief Setting the load value of the IWDG counter. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @param loadValue Load value of the IWDG counter. + * @retval None. + */ +static inline void DCL_IWDG_SetLoadValue(IWDG_RegStruct *iwdgx, unsigned char loadValue) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + iwdgx->IWDOG_KEY.BIT.iwdg_key = IWDG_UNLOCK_REG_CMD; + iwdgx->IWDOG_LOAD.BIT.iwdg_load = loadValue; + iwdgx->IWDOG_KEY.BIT.iwdg_key = IWDG_LOCK_REG_CMD; +} + +/** + * @brief Getting the load value of the IWDG load register. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval unsigned char IWDG load value. + */ +static inline unsigned char DCL_IWDG_GetLoadValue(const IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + return iwdgx->IWDOG_LOAD.BIT.iwdg_load; +} + +/** + * @brief Getting the value of the IWDG counter register. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval unsigned char IWDG counter value. + */ +static inline unsigned char DCL_IWDG_GetCounterValue(const IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + return iwdgx->IWDOG_VALUE.BIT.iwdg_value; +} + +/** + * @brief Setting window value, windowValue need bigger than 4. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @param windowValue window value of the IWDG counter. + * @retval None. + */ +static inline void DCL_IWDG_SetWindowValue(IWDG_RegStruct *iwdgx, unsigned char windowValue) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + IWDG_PARAM_CHECK_NO_RET(windowValue > 4); /* litter than 4 could be error */ + iwdgx->IWDOG_KEY.BIT.iwdg_key = IWDG_UNLOCK_REG_CMD; + iwdgx->IWDOG_WINDOW.BIT.iwdg_window = windowValue; + iwdgx->IWDOG_KEY.BIT.iwdg_key = IWDG_LOCK_REG_CMD; +} + +/** + * @brief Getting window value, windowValue need bigger than 4. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @param windowValue window value of the IWDG counter. + * @retval unsigned char iwdg window value. + */ +static inline unsigned char DCL_IWDG_GetWindowValue(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + return iwdgx->IWDOG_WINDOW.BIT.iwdg_window; +} + +/** + * @brief Start iwdg function. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval None. + */ +static inline void DCL_IWDG_Start(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + iwdgx->IWDOG_KEY.BIT.iwdg_key = 0xCC; /* 0xCC CMD: start iwdg function */ +} + +/** + * @brief Stop iwdg function. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval None. + */ +static inline void DCL_IWDG_Stop(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + iwdgx->IWDOG_KEY.BIT.iwdg_key = 0xDD; /* 0xDD CMD: stop iwdg function */ +} + +/** + * @brief Clear interrupt and reload watchdog counter value. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval None. + */ +static inline void DCL_IWDG_Refresh(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + iwdgx->IWDOG_KEY.BIT.iwdg_key = 0xAA; /* 0xAA CMD: clear interrupt and reload value */ +} + +/** + * @brief Disable write and read IWDG registers except IWDG_LOCK. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval None. + */ +static inline void DCL_IWDG_LockReg(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + iwdgx->IWDOG_KEY.BIT.iwdg_key = 0xFF; /* 0xFF CMD: key not equal 0x55 will lock reg write function except key reg */ +} + +/** + * @brief Enable write and read IWDG registers. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval None. + */ +static inline void DCL_IWDG_UnlockReg(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + iwdgx->IWDOG_KEY.BIT.iwdg_key = 0x55; /* 0x55 CMD: key equal 0x55 will unlock all reg write function */ +} + +/** + * @brief Setting freq div value. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @param freqDiv freqDiv value of the IWDG counter. + * @retval None. + */ +static inline void DCL_IWDG_SetFreqDivValue(IWDG_RegStruct *iwdgx, IWDG_FreqDivType freqDiv) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + IWDG_PARAM_CHECK_NO_RET(freqDiv < IWDG_FREQ_DIV_MAX); + iwdgx->IWDOG_KEY.BIT.iwdg_key = IWDG_UNLOCK_REG_CMD; + iwdgx->IWDOG_PRE_DIV.BIT.iwdg_pre_div = freqDiv; /* freqDiv parameters set */ + iwdgx->IWDOG_KEY.BIT.iwdg_key = IWDG_UNLOCK_REG_CMD; +} + +/** + * @brief Getting freq div value. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @param freqDiv freqDiv value of the IWDG counter. + * @retval None. + */ +static inline unsigned char DCL_IWDG_GetFreqDivValue(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + return iwdgx->IWDOG_PRE_DIV.BIT.iwdg_pre_div; +} + +/** + * @brief Enable reset signal. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval None. + */ +static inline void DCL_IWDG_EnableReset(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + iwdgx->IWDOG_KEY.BIT.iwdg_key = IWDG_UNLOCK_REG_CMD; + iwdgx->IWDOG_CONTROL.BIT.resen = BASE_CFG_SET; + iwdgx->IWDOG_KEY.BIT.iwdg_key = IWDG_LOCK_REG_CMD; +} + +/** + * @brief Disable reset signal. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval None. + */ +static inline void DCL_IWDG_DisableReset(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + iwdgx->IWDOG_KEY.BIT.iwdg_key = IWDG_UNLOCK_REG_CMD; + iwdgx->IWDOG_CONTROL.BIT.resen = BASE_CFG_UNSET; + iwdgx->IWDOG_KEY.BIT.iwdg_key = IWDG_LOCK_REG_CMD; +} + +/** + * @brief Ensable Windows mode. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval None. + */ +static inline void DCL_IWDG_EnableWindowsMode(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + iwdgx->IWDOG_KEY.BIT.iwdg_key = IWDG_UNLOCK_REG_CMD; + iwdgx->IWDOG_CONTROL.BIT.window_mode_en = BASE_CFG_SET; + iwdgx->IWDOG_KEY.BIT.iwdg_key = IWDG_LOCK_REG_CMD; +} + +/** + * @brief Disable Windows mode. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval None. + */ +static inline void DCL_IWDG_DisableWindowsMode(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + iwdgx->IWDOG_KEY.BIT.iwdg_key = IWDG_UNLOCK_REG_CMD; + iwdgx->IWDOG_CONTROL.BIT.window_mode_en = BASE_CFG_UNSET; + iwdgx->IWDOG_KEY.BIT.iwdg_key = IWDG_LOCK_REG_CMD; +} + +/** + * @brief Get Windows mode. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval bool is enable or disable. + */ +static inline bool DCL_IWDG_GetWindowsMode(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + return iwdgx->IWDOG_CONTROL.BIT.window_mode_en; +} + +/** + * @brief check iwdg time type parameter. + * @param timeType Value of @ref IWDG_TimeType. + * @retval Bool. + */ +static inline bool IsIwdgTimeType(IWDG_TimeType timeType) +{ + return (timeType == IWDG_TIME_UNIT_TICK || + timeType == IWDG_TIME_UNIT_S || + timeType == IWDG_TIME_UNIT_MS || + timeType == IWDG_TIME_UNIT_US); +} + +/** + * @brief check iwdg time value parameter. + * @param baseAddress Value of @ref IWDG_RegStruct + * @param timeValue time value + * @param timeType Value of @ref IWDG_TimeType. + * @retval Bool. + */ +static inline bool IsIwdgTimeValue(IWDG_RegStruct *baseAddress, float timeValue, IWDG_TimeType timeType) +{ + float clockFreq = (float)HAL_CRG_GetIpFreq((void *)baseAddress); + float maxSecond = (float)(0xFFFFFFFF / clockFreq); /* 0xFFFFFFFF max input value */ + return ((timeType == IWDG_TIME_UNIT_TICK && timeValue <= 0xFFFFFFFF) || + (timeType == IWDG_TIME_UNIT_S && maxSecond >= timeValue) || + (timeType == IWDG_TIME_UNIT_MS && maxSecond >= timeValue / FREQ_CONVERT_MS_UNIT) || + (timeType == IWDG_TIME_UNIT_US && maxSecond >= timeValue / FREQ_CONVERT_US_UNIT)); +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_IWDG_IP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/iwdg/src/iwdg.c b/vendor/xinlingyu_92_3061M/Project/drivers/iwdg/src/iwdg.c new file mode 100644 index 0000000000000000000000000000000000000000..ff4181089e7d2eaed0ad8d7fa854692668d1df51 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/iwdg/src/iwdg.c @@ -0,0 +1,220 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file iwdg.c + * @author MCU Driver Team + * @brief IWDG module driver + * @details This file provides firmware functions to manage the following functionalities of the IWDG and IWDG. + * + Initialization functions. + * + IWDG Set And Get Functions. + * + Interrupt Handler Functions. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "iwdg.h" + +/* Macro definitions ---------------------------------------------------------*/ +#define IWDG_LOAD_VALUE_LIMIT 255 +#define IWDG_WINDOW_VALUE_UPPER_LIMIT 255 +#define IWDG_WINDOW_VALUE_LOWER_LIMIT 5 +static unsigned int IWDG_CalculateRegTimeout(IWDG_RegStruct *baseAddress, float timeValue, IWDG_TimeType timeType); + +/** + * @brief Initializing IWDG or IWDG register values + * @param handle Value of @ref IWDG_handle. + * @retval BASE_StatusType: OK, ERROR + */ +BASE_StatusType HAL_IWDG_Init(IWDG_Handle *handle) +{ + IWDG_ASSERT_PARAM(handle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(handle->baseAddress)); + IWDG_PARAM_CHECK_WITH_RET(IsIwdgTimeType(handle->timeType), BASE_STATUS_ERROR); + IWDG_PARAM_CHECK_WITH_RET(IsIwdgTimeValue(handle->baseAddress, handle->timeValue, handle->timeType), + BASE_STATUS_ERROR); + BASE_FUNC_DELAY_US(200); /* IWDG need delay 200 us */ + /* IWDG frequency division value less than 256 */ + unsigned int freqDivVal = (handle->freqDivValue > IWDG_FREQ_DIV_256) ? IWDG_FREQ_DIV_256 : handle->freqDivValue; + DCL_IWDG_SetFreqDivValue(handle->baseAddress, freqDivVal); + HAL_IWDG_SetTimeValue(handle, handle->timeValue, handle->timeType); + DCL_IWDG_EnableReset(handle->baseAddress); /* enable reset */ + return BASE_STATUS_OK; +} + +/** + * @brief Calculate Reg Timeout. + * @param timeValue Value to be load to iwdg. + * @param timeType Value of @ref IWDG_TimeType. + * @retval unsigned int timeout Value. + */ +static unsigned int IWDG_CalculateRegTimeout(IWDG_RegStruct *baseAddress, float timeValue, IWDG_TimeType timeType) +{ + float clockFreq = (float)HAL_CRG_GetIpFreq((void *)baseAddress); + unsigned int timeoutValue = 0x00000000U; + switch (timeType) { + case IWDG_TIME_UNIT_TICK: /* If the time type is tick, calculate the timeout value. */ + timeoutValue = (unsigned int)timeValue; + break; + case IWDG_TIME_UNIT_S: /* If the time type is s, calculate the timeout value. */ + timeoutValue = (unsigned int)(timeValue * clockFreq); + break; + case IWDG_TIME_UNIT_MS: /* If the time type is ms, calculate the timeout value. */ + timeoutValue = (unsigned int)(timeValue * clockFreq / FREQ_CONVERT_MS_UNIT); + break; + case IWDG_TIME_UNIT_US: /* If the time type is us, calculate the timeout value. */ + timeoutValue = (unsigned int)(timeValue * clockFreq / FREQ_CONVERT_US_UNIT); + break; + default: + break; + } + return timeoutValue; +} + +/** + * @brief Setting the load value of the IWDG counter. + * @param handle Value of @ref IWDG_handle. + * @param timeValue Load value of the IWDG counter. + * @param timeType IWDG time type. + * @retval None. + */ +void HAL_IWDG_SetTimeValue(IWDG_Handle *handle, unsigned int timeValue, IWDG_TimeType timeType) +{ + IWDG_ASSERT_PARAM(handle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(handle->baseAddress)); + IWDG_PARAM_CHECK_NO_RET(IsIwdgTimeType(timeType)); + IWDG_PARAM_CHECK_NO_RET(IsIwdgTimeValue(handle->baseAddress, timeValue, timeType)); + /* handle->baseAddress only could be configed IWDG or IWDG */ + unsigned int value = IWDG_CalculateRegTimeout(handle->baseAddress, timeValue, timeType); + unsigned int freqDiv = DCL_IWDG_GetFreqDivValue(handle->baseAddress); + value = (value / (1 << freqDiv)); + /* The upper limit of the loaded value is determined. */ + value = (value <= IWDG_LOAD_VALUE_LIMIT) ? value : IWDG_LOAD_VALUE_LIMIT; + DCL_IWDG_SetLoadValue(handle->baseAddress, value); +} + +/** + * @brief refresh the IWDG counter. + * @param handle Value of @ref IWDG_handle. + * @retval None. + */ +void HAL_IWDG_Refresh(IWDG_Handle *handle) +{ + IWDG_ASSERT_PARAM(handle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(handle->baseAddress)); + DCL_IWDG_Refresh(handle->baseAddress); +} + +/** + * @brief obtain the IWDG load value. + * @param handle Value of @ref IWDG_handle. + * @retval unsigned int Load value. + */ +unsigned int HAL_IWDG_GetLoadValue(IWDG_Handle *handle) +{ + IWDG_ASSERT_PARAM(handle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(handle->baseAddress)); + return DCL_IWDG_GetLoadValue(handle->baseAddress); +} + +/** + * @brief Refresh the IWDG counter value. + * @param handle Value of @ref IWDG_handle. + * @retval unsigned int Counter value. + */ +unsigned int HAL_IWDG_GetCounterValue(IWDG_Handle *handle) +{ + IWDG_ASSERT_PARAM(handle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(handle->baseAddress)); + + float res = (float)handle->baseAddress->IWDOG_VALUE.BIT.iwdg_value; + if (res >= 255) { /* 255 is IWDG maximum current count */ + return handle->timeValue; + } + unsigned int freq = HAL_CRG_GetIpFreq((void *)handle->baseAddress); + /* check clockFreq not equal zero */ + if (freq == 0) { + return 0; + } + unsigned int freqDiv = DCL_IWDG_GetFreqDivValue(handle->baseAddress); + switch (handle->timeType) { + case IWDG_TIME_UNIT_TICK: /* Number of tick currently calculated */ + res = res * (1 << freqDiv); + break; + case IWDG_TIME_UNIT_S: + /* Number of seconds currently calculated */ + res = res * (1 << freqDiv) / freq; + break; + case IWDG_TIME_UNIT_MS: + res = res * (1 << freqDiv) * FREQ_CONVERT_MS_UNIT / freq; + break; + case IWDG_TIME_UNIT_US: + /* Number of seconds currently calculated */ + res = res * (1 << freqDiv) * FREQ_CONVERT_US_UNIT / freq; + break; + default: + break; + } + return (unsigned int)res; /* return current counter value */ +} + +/** + * @brief Start the IWDG count. + * @param handle Value of @ref IWDG_handle. + * @retval None. + */ +void HAL_IWDG_Start(IWDG_Handle *handle) +{ + IWDG_ASSERT_PARAM(handle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(handle->baseAddress)); + DCL_IWDG_Start(handle->baseAddress); +} + +/** + * @brief Stop the IWDG count. + * @param handle Value of @ref IWDG_handle. + * @retval None. + */ +void HAL_IWDG_Stop(IWDG_Handle *handle) +{ + IWDG_ASSERT_PARAM(handle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(handle->baseAddress)); + DCL_IWDG_Stop(handle->baseAddress); +} + +/** + * @brief Register IWDG interrupt callback. + * @param handle Value of @ref IWDG_handle. + * @param callBackFunc Value of @ref IWDG_CallbackType. + * @retval None + */ +void HAL_IWDG_RegisterCallback(IWDG_Handle *handle, IWDG_CallbackType callBackFunc) +{ + BASE_FUNC_UNUSED(handle); + BASE_FUNC_UNUSED(callBackFunc); + /* This function is not supported. */ +} + +/** + * @brief Interrupt handler processing function. + * @param handle IWDG_Handle. + * @retval None. + */ +void HAL_IWDG_IrqHandler(void *handle) +{ + BASE_FUNC_UNUSED(handle); + /* This function is not supported. */ +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/iwdg/src/iwdg_ex.c b/vendor/xinlingyu_92_3061M/Project/drivers/iwdg/src/iwdg_ex.c new file mode 100644 index 0000000000000000000000000000000000000000..92a11f83534ee242a9310c1881317c12c4376e0c --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/iwdg/src/iwdg_ex.c @@ -0,0 +1,129 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file iwdg_ex.c + * @author MCU Driver Team + * @brief IWDG module driver + * @details This file provides firmware functions to manage the following functionalities of the IWDG and IWDG. + * + IWDG Set And Get Functions. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "iwdg_ex.h" + +/* Macro definitions ---------------------------------------------------------*/ +#define IWDG_WINDOW_VALUE_UPPER_LIMIT 255 +#define IWDG_WINDOW_VALUE_LOWER_LIMIT 5 + +static unsigned int IWDG_CalculateRegTimeoutEx(IWDG_RegStruct *baseAddress, float timeValue, IWDG_TimeType timeType); +/** + * @brief Setting the window value of the IWDG counter. + * @param handle Value of @ref IWDG_handle. + * @param windowValue Load value of the IWDG counter. + * @param timeType IWDG time type. + * @retval None. + */ +void HAL_IWDG_SetWindowValueEx(IWDG_Handle *handle, unsigned int windowValue, IWDG_TimeType timeType) +{ + IWDG_ASSERT_PARAM(handle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(handle->baseAddress)); + IWDG_PARAM_CHECK_NO_RET(IsIwdgTimeType(timeType)); + /* handle->baseAddress only could be configed IWDG or IWDG */ + if (handle->baseAddress->IWDOG_CONTROL.BIT.window_mode_en == BASE_CFG_SET) { + handle->timeType = timeType; + unsigned int value = IWDG_CalculateRegTimeoutEx(handle->baseAddress, windowValue, timeType); + unsigned int freqDiv = DCL_IWDG_GetFreqDivValue(handle->baseAddress); + value = (value / (1 << freqDiv)); + /* The upper limit of the window value is determined. */ + value = (value <= IWDG_WINDOW_VALUE_UPPER_LIMIT) ? value : IWDG_WINDOW_VALUE_UPPER_LIMIT; + /* IWDG window value litter than 4 could be error */ + value = (value < IWDG_WINDOW_VALUE_LOWER_LIMIT) ? IWDG_WINDOW_VALUE_LOWER_LIMIT : value; + /* window value only could be set litter than load value */ + value = (value < handle->baseAddress->IWDOG_LOAD.BIT.iwdg_load) ? value : + handle->baseAddress->IWDOG_LOAD.BIT.iwdg_load; + DCL_IWDG_SetWindowValue(handle->baseAddress, value); + } +} + +/** + * @brief Calculate Reg Timeout. + * @param timeValue Value to be load to iwdg. + * @param timeType Value of @ref IWDG_TimeType. + * @retval unsigned int timeout Value. + */ +static unsigned int IWDG_CalculateRegTimeoutEx(IWDG_RegStruct *baseAddress, float timeValue, IWDG_TimeType timeType) +{ + float clockFreq = (float)HAL_CRG_GetIpFreq((void *)baseAddress); + unsigned int timeoutValue = 0x00000000U; + + switch (timeType) { + case IWDG_TIME_UNIT_TICK: /* timeout value when time is tick */ + timeoutValue = (unsigned int)timeValue; + break; + case IWDG_TIME_UNIT_US: /* timeout value when time is us */ + timeoutValue = (unsigned int)(timeValue * clockFreq / FREQ_CONVERT_US_UNIT); + break; + case IWDG_TIME_UNIT_MS: /* timeout value when time is ms */ + timeoutValue = (unsigned int)(timeValue * clockFreq / FREQ_CONVERT_MS_UNIT); + break; + case IWDG_TIME_UNIT_S: /* timeout value when time is s */ + timeoutValue = (unsigned int)(timeValue * clockFreq); + break; + default: + break; + } + return timeoutValue; +} + +/** + * @brief Getting the window value of the IWDG counter. + * @param handle Value of @ref IWDG_handle. + * @retval unsigned int the value of window reg value. + */ +unsigned int HAL_IWDG_GetWindowValueEx(IWDG_Handle *handle) +{ + IWDG_ASSERT_PARAM(handle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(handle->baseAddress)); + IWDG_ASSERT_PARAM(IsIwdgTimeType(handle->timeType)); + /* handle->baseAddress only could be configed IWDG or IWDG */ + return DCL_IWDG_GetWindowValue(handle->baseAddress); +} + +/** + * @brief Enable window mode. + * @param handle Value of @ref IWDG_handle. + * @retval None. + */ +void HAL_IWDG_EnableWindowModeEx(IWDG_Handle *handle) +{ + IWDG_ASSERT_PARAM(handle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(handle->baseAddress)); + DCL_IWDG_EnableWindowsMode(handle->baseAddress); +} + +/** + * @brief Disable window mode. + * @param handle Value of @ref IWDG_handle. + * @retval None. + */ +void HAL_IWDG_DisableWindowModeEx(IWDG_Handle *handle) +{ + IWDG_ASSERT_PARAM(handle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(handle->baseAddress)); + DCL_IWDG_DisableWindowsMode(handle->baseAddress); +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/pga/common/inc/pga.h b/vendor/xinlingyu_92_3061M/Project/drivers/pga/common/inc/pga.h new file mode 100644 index 0000000000000000000000000000000000000000..4507a9f25f43ca984b0a00fb0240bc75eb5b93d8 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/pga/common/inc/pga.h @@ -0,0 +1,81 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pga.h + * @author MCU Driver Team + * @brief Programmable Gain Apmlifier HAL level module driver head file. + * This file provides firmware functions to manage the following + * functionalities of the Amplifier. + * + Initialization and de-initialization functions + * + Programmable Gain Amplifier set gain value functions + */ +#ifndef McuMagicTag_PGA_H +#define McuMagicTag_PGA_H + +#include "pga_ip.h" +#include "baseinc.h" + +/** + * @defgroup PGA PGA + * @brief PGA module. + * @{ + */ + +/** + * @defgroup PGA_Common PGA Common + * @brief PGA common external module. + * @{ + */ + +/** + * @defgroup PGA_Handle_Definition PGA Handle Definition + * @{ + */ +/** + * @brief The define of the PGA handle structure + */ +typedef struct _PGA_Handle { + PGA_RegStruct *baseAddress; /**< PGA registers base address. */ + PGA_GainValue gain; /**< PGA gain selection. */ + bool externalResistorMode; /**< PGA resistance mode. */ + + PGA_ExtendHandle handleEx; /**< PGA handle extend. */ +} PGA_Handle; + +/** + * @} + */ + +/** + * @defgroup PGA_API_Declaration PGA HAL API + * @{ + */ +BASE_StatusType HAL_PGA_Init(PGA_Handle *pgaHandle); /* Initializet function */ +BASE_StatusType HAL_PGA_DeInit(PGA_Handle *pgaHandle); /* Deinitialize function */ +void HAL_PGA_SetGain(PGA_Handle *pgaHandle, PGA_GainValue gain); /* Set amplifier's gain function */ +void HAL_PGA_Start(PGA_Handle *pgaHandle); /* Start PGA */ +void HAL_PGA_Stop(PGA_Handle *pgaHandle); /* Stop PGA */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/pga/inc/pga_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/pga/inc/pga_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..f2fad2ee2b0855cdb3c33220e39cd7032224718c --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/pga/inc/pga_ip.h @@ -0,0 +1,333 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pga_ip.h + * @author MCU Driver Team + * @brief Programmable Gain Amplifier module driver. + * This file provides DCL functions to manage amplifier. + * + Programmable Gain Amplifier register mapping strtucture. + * + Direct configuration layer interface. + */ + +#ifndef McuMagicTag_PGA_IP_H +#define McuMagicTag_PGA_IP_H + +#include "baseinc.h" + +#ifdef PGA_PARAM_CHECK +#define PGA_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define PGA_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define PGA_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define PGA_ASSERT_PARAM(para) ((void)0U) +#define PGA_PARAM_CHECK_NO_RET(para) ((void)0U) +#define PGA_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +#define PGA_PGA_MAX_GAIN 7 +#define PGA_MAX_GAIN_VALUE 3 +#define PGA_MAX_EXT_CAP_COMP 7 +#define PGA_EXT_VLAUE 3 +/** + * @addtogroup PGA + * @{ + */ + +/** + * @defgroup PGA_IP PGA_IP + * @brief PGA_IP: pga_v1. + * @{ + */ + +/** + * @defgroup PGA_REG_Definition PGA Register Structure. + * @brief PGA Register Structure Definition. + * @{ + */ + +/** + * @brief PGA gain value selection + */ +typedef enum { + PGA_GAIN_2X = 0x00000000U, + PGA_GAIN_4X = 0x00000001U, + PGA_GAIN_8X = 0x00000002U, + PGA_GAIN_16X = 0x00000003U, +} PGA_GainValue; + +/** + * @brief PGA gain value selection + */ +typedef enum { + PGA_EXT_COMPENSATION_2X = 0x00000000U, + PGA_EXT_COMPENSATION_3X = 0x00000001U, + PGA_EXT_COMPENSATION_4X = 0x00000002U, + PGA_EXT_COMPENSATION_5X = 0x00000003U, + PGA_EXT_COMPENSATION_6X = 0x00000004U, + PGA_EXT_COMPENSATION_7X = 0x00000005U, + PGA_EXT_COMPENSATION_8X = 0x00000006U, + PGA_EXT_COMPENSATION_9X = 0x00000007U, +} PGA_ExtCapCompValue; + +/** + * @brief Extent handle definition of PGA. + */ +typedef struct { + PGA_ExtCapCompValue extCapCompensation; /**< Feedforward Capacitance Compensation in PGA External Gain Mode. */ +} PGA_ExtendHandle; + +/** + * @brief PGA control 0. + */ +typedef union { + unsigned int reg; + struct { + unsigned int da_pga_enh : 1; /**< Overall enable of the PGA. */ + unsigned int reserved_0 : 31; + } BIT; +} volatile PGA_CTRL0_REG; + +/** + * @brief PGA control 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int da_pga_cf_ctrl : 3; /**< Feedforward capacitor compensation config in PGA external gain mode. */ + unsigned int reserved_0 : 5; + unsigned int da_pga_gain_ctrl : 3; /**< Gain configuration of the internal resistor of the PGA. */ + unsigned int reserved_1 : 5; + unsigned int da_pga_mode_ctrl : 2; /**< PGA mode configuration. 0: internal resistor gain mode; + 1: external resistor gain mode; */ + unsigned int reserved_2 : 14; + } BIT; +} volatile PGA_CTRL1_REG; + +/** + * @brief PGA control register 2. + */ +typedef union { + unsigned int reg; + struct { + unsigned int da_pga_ibias_sel : 4; /**< PGA bias current configuration level select. */ + unsigned int reserved_0 : 28; + } BIT; +} volatile PGA_CTRL2_REG; + +/** + * @brief PGA TRIM register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int da_pga_vos_trim : 9; /**< Offset trim information of the PGA. */ + unsigned int reserved_0 : 23; + } BIT; +} volatile PGA_TRIM_REG; + +/** + * @brief PGA test register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int da_pga_test_enh : 1; /**< PGA test enable. */ + unsigned int da_pga_test_sel : 2; /**< PGA test select. */ + unsigned int reserved_0 : 29; + } BIT; +} volatile PGA_TEST_REG; + +/** + * @brief PGA reserved register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int da_pga_cf_ctrl1 : 2; /**< Feedforward capacitor compensation config in external gain mode. */ + unsigned int reserved_0 : 30; + } BIT; +} volatile PGA_RSV_REG; + +/** + * @brief Register mapping structure. + */ +typedef struct _PGA_RegStruct { + PGA_CTRL0_REG PGA_CTRL0; /**< PGA control 0 register. Offset address: 0x00000000U. */ + PGA_CTRL1_REG PGA_CTRL1; /**< PGA control 1 register. Offset address: 0x00000004U. */ + PGA_CTRL2_REG PGA_CTRL2; /**< PGA control 2 register. Offset address: 0x00000008U. */ + unsigned char space0[20]; + PGA_TRIM_REG PGA_TRIM; /**< PGA TRIM register. Offset address: 0x00000020U. */ + unsigned char space1[28]; + PGA_TEST_REG PGA_TEST; /**< PGA test control register. Offset address: 0x00000040U. */ + unsigned char space2[28]; + PGA_RSV_REG PGA_RSV; /**< PGA reserved register. Offset address: 0x00000060U. */ +} volatile PGA_RegStruct; + +/* Parameter Check -----------------------------------------------------------*/ + +/** + * @brief Verify gain value of PGA. + * @param pgaGainValue pga gain value @ref PGA_GainValue + * @retval true + * @retval false + */ +static inline bool IsPgaGain(PGA_GainValue pgaGainValue) +{ + return (pgaGainValue <= PGA_MAX_GAIN_VALUE); +} + +/** + * @brief Verify feedforward capacitance compensation value. + * @param pgaExtCapCompValue feedforward capacitance compensation value @ref PGA_ExtCapCompValue + * @retval true + * @retval false + */ +static inline bool IsPgaExtCapCompensation(PGA_ExtCapCompValue pgaExtCapCompValue) +{ + return (pgaExtCapCompValue <= PGA_MAX_EXT_CAP_COMP); +} + +/* DCL layer -----------------------------------------------------------*/ +/** + * @brief Enable amplifier's output + * @param pgax: amplifier register base address. + * @retval None. + */ +static inline void DCL_PGA_EnableOut(PGA_RegStruct *pgax) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + pgax->PGA_CTRL0.BIT.da_pga_enh = BASE_CFG_ENABLE; +} + +/** + * @brief Disable amplifier's output + * @param pgax: amplifier register base address. + * @retval None. + */ +static inline void DCL_PGA_DisableOut(PGA_RegStruct *pgax) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + pgax->PGA_CTRL0.BIT.da_pga_enh = BASE_CFG_DISABLE; +} + +/** + * @brief Set amplifier's gain + * @param pgax: amplifier register base address. + * @param value: gain value. + * @retval None. + */ +static inline void DCL_PGA_SetGain(PGA_RegStruct *pgax, unsigned int value) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + PGA_PARAM_CHECK_NO_RET(value <= PGA_PGA_MAX_GAIN); + pgax->PGA_CTRL1.BIT.da_pga_gain_ctrl = value; +} + +/** + * @brief Get amplifier's gain + * @param pgax: amplifier register base address. + * @retval gain value. + */ +static inline unsigned int DCL_PGA_GetGain(PGA_RegStruct *pgax) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + return pgax->PGA_CTRL1.BIT.da_pga_gain_ctrl; +} + +/** + * @brief PGA mode configuration, enable external resistor gain mode. + * @param pgax: amplifier register base address. + * @retval None. + */ +static inline void DCL_PGA_EnableExtGainMode(PGA_RegStruct *pgax) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + pgax->PGA_CTRL1.BIT.da_pga_mode_ctrl = BASE_CFG_ENABLE; +} + +/** + * @brief PGA mode configuration, disable external resistor gain mode. + * @param pgax: amplifier register base address. + * @retval None. + */ +static inline void DCL_PGA_DisableExtGainMode(PGA_RegStruct *pgax) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + pgax->PGA_CTRL1.BIT.da_pga_mode_ctrl = BASE_CFG_DISABLE; +} + +/** + * @brief Fedforward capacitor compensation configuration in PGA external gain mode + * @param pgax: amplifier register base address. + * @param extValue: Configured value of the capacitor compensation. + * @retval None. + */ +static inline void DCL_PGA_SetExtCompensation(PGA_RegStruct *pgax, unsigned short extValue) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + PGA_PARAM_CHECK_NO_RET(extValue <= PGA_PGA_MAX_GAIN); + pgax->PGA_CTRL1.BIT.da_pga_cf_ctrl = extValue; +} + +/** + * @brief PGA enable Test mode. + * @param pgax: amplifier register base address. + * @retval None. + */ +static inline void DCL_PGA_EnableTestMode(PGA_RegStruct *pgax) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + pgax->PGA_TEST.BIT.da_pga_test_enh = BASE_CFG_ENABLE; +} + +/** + * @brief PGA disable Test mode. + * @param pgax: amplifier register base address. + * @retval None. + */ +static inline void DCL_PGA_DisableTestMode(PGA_RegStruct *pgax) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + pgax->PGA_TEST.BIT.da_pga_test_enh = BASE_CFG_DISABLE; +} + +/** + * @brief Set feedforward capacitance compensation in external gain mode. + * @param pgax: amplifier register base address. + * @param extBigvalue feedforward capacitance compensation. + * @retval None. + * @note To configure this register, must set da_pga_cf_ctrl to 111. + */ +static inline void DCL_PGA_SetExtCapCompValue(PGA_RegStruct *pgax, unsigned short extBigvalue) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + PGA_PARAM_CHECK_NO_RET(extBigvalue <= PGA_EXT_VLAUE); + pgax->PGA_RSV.BIT.da_pga_cf_ctrl1 = extBigvalue; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/pga/src/pga.c b/vendor/xinlingyu_92_3061M/Project/drivers/pga/src/pga.c new file mode 100644 index 0000000000000000000000000000000000000000..ebc94a1f6f9541d60872a5db6f5189f1be006b2d --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/pga/src/pga.c @@ -0,0 +1,101 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pga.c + * @author MCU Driver Team. + * @brief Programmable Gain Amplifier HAL level module driver. + * This file provides firmware functions to manage the following + * functionalities of the amplifier + * + Programmable Gain Amplifier's Initialization and de-initialization functions + * + Set amplifier's gain value + */ +#include "pga.h" +#include "assert.h" + +/** + * @brief PGA HAL Init + * @param pgaHandle: PGA handle. + * @retval BASE_StatusType. BASE_STATUS_OK: success, BASE_STATUS_ERROR: fail. + */ +BASE_StatusType HAL_PGA_Init(PGA_Handle *pgaHandle) +{ + PGA_ASSERT_PARAM(pgaHandle != NULL); + PGA_ASSERT_PARAM(IsPGAInstance(pgaHandle->baseAddress)); + PGA_PARAM_CHECK_WITH_RET(IsPgaGain(pgaHandle->gain), BASE_STATUS_ERROR); + PGA_PARAM_CHECK_WITH_RET(IsPgaExtCapCompensation(pgaHandle->handleEx.extCapCompensation), BASE_STATUS_ERROR); + /* Initial configuration of the PGA. */ + PGA_CTRL1_REG pgaControl1; + pgaControl1.reg = pgaHandle->baseAddress->PGA_CTRL1.reg; + pgaControl1.BIT.da_pga_mode_ctrl = pgaHandle->externalResistorMode; /* PGA mode configuration. */ + pgaControl1.BIT.da_pga_gain_ctrl = pgaHandle->gain; /* PGA gain setting. */ + pgaControl1.BIT.da_pga_cf_ctrl = pgaHandle->handleEx.extCapCompensation; + pgaHandle->baseAddress->PGA_CTRL1.reg = pgaControl1.reg; + /* Enable PGA */ + pgaHandle->baseAddress->PGA_CTRL0.BIT.da_pga_enh = BASE_CFG_ENABLE; + return BASE_STATUS_OK; +} + +/** + * @brief PGA HAL DeInit + * @param pgaHandle: PGA handle. + * @retval BASE_StatusType. + */ +BASE_StatusType HAL_PGA_DeInit(PGA_Handle *pgaHandle) +{ + PGA_ASSERT_PARAM(pgaHandle != NULL); + PGA_ASSERT_PARAM(IsPGAInstance(pgaHandle->baseAddress)); + pgaHandle->baseAddress->PGA_CTRL0.reg = BASE_CFG_DISABLE; /* Disable PGA. */ + pgaHandle->baseAddress->PGA_CTRL1.reg = BASE_CFG_DISABLE; /* Gain and mode deinitialization. */ + return BASE_STATUS_OK; +} + +/** + * @brief Set Gain value + * @param pgaHandle: PGA handle. + * @param gain: gain value. @ref PGA_GainValue + * @retval None. + */ +void HAL_PGA_SetGain(PGA_Handle *pgaHandle, PGA_GainValue gain) +{ + PGA_ASSERT_PARAM(pgaHandle != NULL); + PGA_ASSERT_PARAM(IsPGAInstance(pgaHandle->baseAddress)); + pgaHandle->baseAddress->PGA_CTRL1.BIT.da_pga_gain_ctrl = gain; /* Gain value setting. */ +} + +/** + * @brief Start PGA + * @param pgaHandle: PGA handle. + * @retval None + */ +void HAL_PGA_Start(PGA_Handle *pgaHandle) +{ + PGA_ASSERT_PARAM(pgaHandle != NULL); + PGA_ASSERT_PARAM(IsPGAInstance(pgaHandle->baseAddress)); + pgaHandle->baseAddress->PGA_CTRL0.BIT.da_pga_enh = BASE_CFG_ENABLE; /* Enable PGA. */ +} + +/** + * @brief Stop PGA + * @param pgaHandle: PGA handle. + * @retval None + */ +void HAL_PGA_Stop(PGA_Handle *pgaHandle) +{ + PGA_ASSERT_PARAM(pgaHandle != NULL); + PGA_ASSERT_PARAM(IsPGAInstance(pgaHandle->baseAddress)); + pgaHandle->baseAddress->PGA_CTRL0.BIT.da_pga_enh = BASE_CFG_DISABLE; /* Disable PGA. */ +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/pmc/common/inc/pmc.h b/vendor/xinlingyu_92_3061M/Project/drivers/pmc/common/inc/pmc.h new file mode 100644 index 0000000000000000000000000000000000000000..d05b66358cda7970a960926bcc8ca9d39eb379f9 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/pmc/common/inc/pmc.h @@ -0,0 +1,96 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pmc.h + * @author MCU Driver Team. + * @brief PMC module driver. + * This file provides functions declaration of PMC. + * + PMC's initialization and de-initialization functions. + * + Interface declaration of enter sleep, deepsleep and shutdowm mode. + * + PMC's register callback function. + */ + +#ifndef __McuMagicTag_PMC_H__ +#define __McuMagicTag_PMC_H__ +#include "pmc_ip.h" + +/** + * @defgroup PMC PMC + * @brief PMC module. + * @{ + */ + +/** + * @defgroup PMC_Common PMC Common + * @brief PMC common external module. + * @{ + */ + + +/** + * @defgroup PMC_Common_Param PMC Common Parameters + * @{ + */ + +/** + * @brief Definition of callback function type + */ +typedef void (* PMC_CallbackType)(void *pmcHandle); + +/** + * @brief PMC Handle + */ +typedef struct _PMC_Handle { + PMC_RegStruct *baseAddress; /**< Register base address. */ + PMC_LowpowerWakeupSrc wakeupSrc; /**< Wakeup source of deep sleep. */ + PMC_ActMode wakeupActMode; /**< Wakeup pin level mode of PMC module. */ + unsigned int wakeupTime; /**< Wakeup time of deep sleep. */ + bool pvdEnable; /**< PVD function enable. */ + PMC_PvdThreshold pvdThreshold; /**< PVD threshold voltage level. */ + PMC_UserCallBack userCallBack; /**< User-defined callback function. */ + PMC_ExtendHandle handleEx; /**< Extend handle, configuring some special parameters. */ +} PMC_Handle; + +/** + * @} + */ + +/** + * @defgroup PMC_API_Declaration PMC HAL API + * @{ + */ +void HAL_PMC_Init(PMC_Handle *handle); +void HAL_PMC_DeInit(PMC_Handle *handle); +void HAL_PMC_EnterSleepMode(void); +void HAL_PMC_EnterDeepSleepMode(PMC_Handle *handle); +void HAL_PMC_EnterShutdownMode(PMC_Handle *handle); +PMC_LowpowerType HAL_PMC_GetWakeupType(PMC_Handle *handle); +void HAL_PMC_RegisterCallback(PMC_Handle *handle, PMC_CallBackID callbackID, PMC_CallbackType pCallback); +void HAL_PMC_IrqHandler(void *handle); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/pmc/inc/pmc_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/pmc/inc/pmc_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..d3a4b234d276f380389d8caa96c18b84344fafc0 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/pmc/inc/pmc_ip.h @@ -0,0 +1,632 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pmc_ip.h + * @author MCU Driver Team + * @brief Header file containing PMC module DCL driver functions. + * This file provides functions to manage the following functionalities of PMC module. + * + Definition of PMC configuration parameters. + * + PMC registers mapping structures. + * + Direct Configutration Layer driver functions. + */ +#ifndef McuMagicTag_PMC_IP_H +#define McuMagicTag_PMC_IP_H + +#include "baseinc.h" + +#ifdef PMC_PARAM_CHECK +#define PMC_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define PMC_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define PMC_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define PMC_ASSERT_PARAM(para) ((void)0U) +#define PMC_PARAM_CHECK_NO_RET(para) ((void)0U) +#define PMC_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +#define PMC_WAKEUP_SRC_MARSK 0x3F +#define PMC_WAKEUP_ACT_MODE_MARSK 0x3 + +/** + * @addtogroup PMC + * @{ + */ + +/** + * @defgroup PMC_IP PMC_IP + * @brief PMC_IP: pmc_v1. + * @{ + */ + +/** + * @defgroup PMC_Param_Def PMC Parameters Definition + * @brief Definition of PMC configuration parameters + * @{ + */ + + +/** + * @brief wakeup pin level mode of PMC module. + * @details status flag: + * + PMC_WAKEUP_ACT_UP_EDGE -- Wakeup valid in up edge + * + PMC_WAKEUP_ACT_DOWN_EDGE -- Wakeup valid in down edge + * + PMC_WAKEUP_ACT_HIGH_LEVEL -- Wakeup valid in high edge + * + PMC_WAKEUP_ACT_LOW_LEVEL -- Wakeup valid in low edge + */ +typedef enum { + PMC_WAKEUP_ACT_UP_EDGE = 0x00000000U, + PMC_WAKEUP_ACT_DOWN_EDGE = 0x00000001U, + PMC_WAKEUP_ACT_HIGH_LEVEL = 0x00000002U, + PMC_WAKEUP_ACT_LOW_LEVEL = 0x00000003U, +} PMC_ActMode; + +/** + * @brief Wakeup source of deep sleep. + * @details status flag: + * + PMC_WAKEUP_0 -- Wakeup from DS_WAKEUP0. + * + PMC_WAKEUP_2 -- Wakeup from DS_WAKEUP2. + * + PMC_WAKEUP_3 -- Wakeup from DS_WAKEUP3. + * + PMC_WAKEUP_CNT -- Wakeup from timer. + * + PMC_WAKEUP_NONE --No Wakeup source. + */ +typedef enum { + PMC_WAKEUP_0 = 0x00000000U, + PMC_WAKEUP_2 = 0x00000002U, + PMC_WAKEUP_3 = 0x00000003U, + PMC_WAKEUP_CNT = 0x00000004U, + PMC_WAKEUP_NONE = 0x00000005U, +} PMC_LowpowerWakeupSrc; + +/** + * @brief Callback Triggering Event Enumeration Definition + */ +typedef enum { + PMC_PVD_INT_ID = 0x00, +} PMC_CallBackID; + +/** + * @brief Lowpower type. + * @details status flag: + * + PMC_LP_NONE -- Non-lowpower mode. + * + PMC_LP_DEEPSLEEP -- Deepsleep mode. + */ +typedef enum { + PMC_LP_NONE = 0x00000000U, + PMC_LP_DEEPSLEEP = 0x00000001U, +} PMC_LowpowerType; + +static unsigned int g_internalPvdValueTable[8][2] = { + {0x00, 0x00}, /* rising edge 2.18V, falling edge 2.08V. */ + {0x01, 0x01}, /* rising edge 2.28V, falling edge 2.18V. */ + {0x02, 0x02}, /* rising edge 2.38V, falling edge 2.28V. */ + {0x03, 0x03}, /* rising edge 2.48V, falling edge 2.38V. */ + {0x04, 0x04}, /* rising edge 2.58V, falling edge 2.48V. */ + {0x05, 0x05}, /* rising edge 2.68V, falling edge 2.58V. */ + {0x06, 0x06}, /* rising edge 2.78V, falling edge 2.68V. */ + {0x07, 0x07}, /* rising edge 2.88V, falling edge 2.78V. */ +}; + +/** + * @brief PMC PVD threshold voltage level. + * @details PMC_PVD_THRED_LEVEL, For details, see g_pvdValueTable. + */ +typedef enum { + PMC_PVD_THRED_LEVEL0 = 0x00000000U, + PMC_PVD_THRED_LEVEL1 = 0x00000001U, + PMC_PVD_THRED_LEVEL2 = 0x00000002U, + PMC_PVD_THRED_LEVEL3 = 0x00000003U, + PMC_PVD_THRED_LEVEL4 = 0x00000004U, + PMC_PVD_THRED_LEVEL5 = 0x00000005U, + PMC_PVD_THRED_LEVEL6 = 0x00000006U, + PMC_PVD_THRED_LEVEL7 = 0x00000007U, +} PMC_PvdThreshold; + +/** + * @brief PMC extend handle, configuring some special parameters. + */ +typedef struct { +} PMC_ExtendHandle; + +/** + * @brief User-defined callback function. + */ +typedef struct { + /** Event callback function of the flash module */ + void (*PmcCallBack)(void *handle); +} PMC_UserCallBack; + +/** + * @} + */ + +/** + * @defgroup PMC_REG_Definition PMC Register Structure. + * @brief PMC Register Structure Definition. + * @{ + */ + +/** + * @brief Low-power mode control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved_0 : 4; + unsigned int deepsleep_req : 1; /**< The system enters the deepsleep mode. */ + unsigned int reserved_1 : 27; + } BIT; +} volatile PMC_LOWPOWER_MODE; + +/** + * @brief Wakeup control in deepsleep mode registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int wakeup0_act_mode : 2; /**< Valid mode select of WakeUP0. */ + unsigned int reserved_3 : 2; + unsigned int wakeup2_act_mode : 2; /**< Valid mode select of wakeup2. */ + unsigned int wakeup3_act_mode : 2; /**< Valid mode select of wakeup3. */ + unsigned int wakeup0_en : 1; /**< Wakeup0 enable. */ + unsigned int reserved_2 : 1; + unsigned int wakeup2_en : 1; /**< Wakeup2 enable. */ + unsigned int wakeup3_en : 1; /**< Wakeup3 enable. */ + unsigned int reserved_0 : 4; + unsigned int cnt32k_wakeup_en : 1; /**< Scheduled wakeup enable. */ + unsigned int reserved_1 : 15; + } BIT; +} volatile PMC_WAKEUP_CTRL; + +/** + * @brief Low-power status query registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int wakeup_src_lock : 6; /**< Starts the wakeup source query. */ + unsigned int reserved_0 : 3; + unsigned int starup_from_deepsleep : 1; /**< Start from the deepsleep state. */ + unsigned int reserved_1 : 2; + unsigned int wakeup0_status : 1; /**< Wakeup0 wakeup source status. */ + unsigned int reserved_3 : 1; + unsigned int wakeup2_status : 1; /**< Wakeup2 wakeup source status. */ + unsigned int wakeup3_status : 1; /**< Wakeup3 wakeup source status. */ + unsigned int reserved_2 : 16; + } BIT; +} volatile PMC_LOWPOWER_STATUS; + +/** + * @brief PMC registers definition structure. + */ +typedef struct { + unsigned int reserved_0[128]; + PMC_LOWPOWER_MODE LOWPOWER_MODE; /**< Low-power mode control register. Offset address: 0x200. */ + unsigned int CNT32K_WAKE_CYC; /**< Timed wakeup period config reg. Offset address: 0x204. */ + PMC_WAKEUP_CTRL WAKEUP_CTRL; /**< Wakeup control register in deepsleep mode. + Offset address: 0x208. */ + PMC_LOWPOWER_STATUS LOWPOWER_STATUS; /**< Low-power status query register. Offset address: 0x20C. */ + unsigned int reserved_1[828]; + unsigned int AON_USER_REG0; /**< AON domain user register 0. Offset address: 0xF00. */ + unsigned int AON_USER_REG1; /**< AON domain user register 1. Offset address: 0xF04. */ + unsigned int AON_USER_REG2; /**< AON domain user register 2. Offset address: 0xF08. */ + unsigned int AON_USER_REG3; /**< AON domain user register 3. Offset address: 0xF0C. */ +} volatile PMC_RegStruct; + +/** + * @brief Check PVD threshold voltage level. + * @param value value of losc rtrim value. + * @retval true + * @retval false + */ +static inline bool IsPvdThreshold(PMC_PvdThreshold value) +{ + return (value == PMC_PVD_THRED_LEVEL0 || value == PMC_PVD_THRED_LEVEL1 || \ + value == PMC_PVD_THRED_LEVEL2 || value == PMC_PVD_THRED_LEVEL3 || \ + value == PMC_PVD_THRED_LEVEL4 || value == PMC_PVD_THRED_LEVEL5 || \ + value == PMC_PVD_THRED_LEVEL6 || value == PMC_PVD_THRED_LEVEL7); +} + +/** + * @brief Check PMC Wakeup source. + * @param wakeSrc value of Wakeup source. + * @retval true + * @retval false + */ +static inline bool IsWakeupSrc(PMC_LowpowerWakeupSrc wakeSrc) +{ + return (wakeSrc == PMC_WAKEUP_0 || \ + wakeSrc == PMC_WAKEUP_2 || wakeSrc == PMC_WAKEUP_3 || \ + wakeSrc == PMC_WAKEUP_CNT); +} + +/** + * @brief Check PMC active mode. + * @param mode value of active mode. + * @retval true + * @retval false + */ +static inline bool IsActiveMode(PMC_ActMode mode) +{ + return (mode == PMC_WAKEUP_ACT_UP_EDGE || mode == PMC_WAKEUP_ACT_DOWN_EDGE || \ + mode == PMC_WAKEUP_ACT_HIGH_LEVEL || mode == PMC_WAKEUP_ACT_LOW_LEVEL); +} + +/** + * @brief Enter sleep mode interface. + * @param None. + * @retval None. + */ +static inline void DCL_PMC_EnterSleep(void) +{ +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + /* If user mode is supported, make sure to execute WFI + commands in machine mode */ + static unsigned int priv = RISCV_U_MODE; + RISCV_PRIV_MODE_SWITCH(priv); + __asm("wfi"); + RISCV_PRIV_MODE_SWITCH(priv); +#else + /* Only machine mode, no need for mode switching */ + __asm("wfi"); +#endif +} + +/** + * @brief Enter deepsleep mode interface. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_EnterDeepSleep(PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->LOWPOWER_MODE.BIT.deepsleep_req = BASE_CFG_ENABLE; +} + +/** + * @brief Quit deepsleep mode interface. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_QuitDeepSleep(PMC_RegStruct * const pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->LOWPOWER_MODE.BIT.deepsleep_req = BASE_CFG_DISABLE; +} +/** + * @brief Setting wakeup timer cycle. + * @param pmcx PMC register base address. + * @param cycle Timer cycle value. + * @retval None. + */ +static inline void DCL_PMC_SetFixTimeWakeupTimer(PMC_RegStruct *pmcx, unsigned int cycle) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->CNT32K_WAKE_CYC = cycle; +} + +/** + * @brief Enable wakeup from timer. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_FixTimeWakeupEnable(PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->WAKEUP_CTRL.BIT.cnt32k_wakeup_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable wakeup from timer. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_FixTimeWakeupDisable(PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->WAKEUP_CTRL.BIT.cnt32k_wakeup_en = BASE_CFG_DISABLE; +} + +/** + * @brief Enable wakeup from WAKEUP0. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_Wakeup0Enable(PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->WAKEUP_CTRL.BIT.wakeup0_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable wakeup from WAKEUP0. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_Wakeup0Disable(PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->WAKEUP_CTRL.BIT.wakeup0_en = BASE_CFG_DISABLE; +} + +/** + * @brief Enable wakeup from WAKEUP2. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_Wakeup2Enable(PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->WAKEUP_CTRL.BIT.wakeup2_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable wakeup from WAKEUP2. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_Wakeup2Disable(PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->WAKEUP_CTRL.BIT.wakeup2_en = BASE_CFG_DISABLE; +} + +/** + * @brief Enable wakeup from WAKEUP3. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_Wakeup3Enable(PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->WAKEUP_CTRL.BIT.wakeup3_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable wakeup from WAKEUP3. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_Wakeup3Disable(PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->WAKEUP_CTRL.BIT.wakeup3_en = BASE_CFG_DISABLE; +} + +/** + * @brief Setting WAKEUP0 active level mode. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_SetWakeup0ActiveMode(PMC_RegStruct *pmcx, PMC_ActMode mode) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + PMC_PARAM_CHECK_NO_RET(IsActiveMode(mode)); + pmcx->WAKEUP_CTRL.BIT.wakeup0_act_mode = ((unsigned int)mode & PMC_WAKEUP_ACT_MODE_MARSK); +} + +/** + * @brief Setting WAKEUP2 active level mode. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_SetWakeup2ActiveMode(PMC_RegStruct *pmcx, PMC_ActMode mode) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + PMC_PARAM_CHECK_NO_RET(IsActiveMode(mode)); + pmcx->WAKEUP_CTRL.BIT.wakeup2_act_mode = ((unsigned int)mode & PMC_WAKEUP_ACT_MODE_MARSK); +} + +/** + * @brief Setting WAKEUP3 active level mode. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_SetWakeup3ActiveMode(PMC_RegStruct *pmcx, PMC_ActMode mode) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + PMC_PARAM_CHECK_NO_RET(IsActiveMode(mode)); + pmcx->WAKEUP_CTRL.BIT.wakeup3_act_mode = ((unsigned int)mode & PMC_WAKEUP_ACT_MODE_MARSK); +} + +/** + * @brief Getting WAKEUP0 status. + * @param pmcx PMC register base address. + * @retval Wakeup status. + */ +static inline bool DCL_PMC_GetWakeup0Status(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->LOWPOWER_STATUS.BIT.wakeup0_status); +} + +/** + * @brief Getting WAKEUP2 status. + * @param pmcx PMC register base address. + * @retval Wakeup status. + */ +static inline bool DCL_PMC_GetWakeup2Status(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->LOWPOWER_STATUS.BIT.wakeup2_status); +} + +/** + * @brief Getting WAKEUP3 status. + * @param pmcx PMC register base address. + * @retval Wakeup status. + */ +static inline bool DCL_PMC_GetWakeup3Status(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->LOWPOWER_STATUS.BIT.wakeup3_status); +} + +/** + * @brief Getting flag of wakeup from deepsleep mode. + * @param pmcx PMC register base address. + * @retval flag of wakeup from deepsleep mode. + */ +static inline bool DCL_PMC_GetStartupFromDeepSleepFlag(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->LOWPOWER_STATUS.BIT.starup_from_deepsleep); +} + +/** + * @brief Getting wakeup source. + * @param pmcx PMC register base address. + * @retval source of wakeup. + */ +static inline unsigned int DCL_PMC_GetWakeupSrc(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->LOWPOWER_STATUS.BIT.wakeup_src_lock & PMC_WAKEUP_SRC_MARSK); +} + +/** + * @brief Setting always on user's regsiter 0. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_SetAlwaysOnUserReg0(PMC_RegStruct *pmcx, unsigned int value) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->AON_USER_REG0 = value; +} + +/** + * @brief Getting always on user's regsiter 0. + * @param pmcx PMC register base address. + * @retval Register0's value. + */ +static inline unsigned int DCL_PMC_GetAlwaysOnUserReg0(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->AON_USER_REG0); +} + +/** + * @brief Setting always on user's regsiter 1. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_SetAlwaysOnUserReg1(PMC_RegStruct *pmcx, unsigned int value) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->AON_USER_REG1 = value; +} + +/** + * @brief Getting always on user's regsiter 1. + * @param pmcx PMC register base address. + * @retval Register1's value. + */ +static inline unsigned int DCL_PMC_GetAlwaysOnUserReg1(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->AON_USER_REG1); +} + +/** + * @brief Setting always on user's regsiter 2. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_SetAlwaysOnUserReg2(PMC_RegStruct *pmcx, unsigned int value) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->AON_USER_REG2 = value; +} + +/** + * @brief Getting always on user's regsiter 2. + * @param pmcx PMC register base address. + * @retval Register2's value. + */ +static inline unsigned int DCL_PMC_GetAlwaysOnUserReg2(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->AON_USER_REG2); +} + +/** + * @brief Setting always on user's regsiter 3. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_SetAlwaysOnUserReg3(PMC_RegStruct *pmcx, unsigned int value) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->AON_USER_REG3 = value; +} + +/** + * @brief Getting always on user's regsiter 3. + * @param pmcx PMC register base address. + * @retval Register3's value. + */ +static inline unsigned int DCL_PMC_GetAlwaysOnUserReg3(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->AON_USER_REG3); +} + +/** + * @brief Enable PVD function. + * @retval None. + */ +static inline void DCL_PMC_EnablePvd(void) +{ + SYSCTRL1_RegStruct *sysCtrl1x = SYSCTRL1_BASE; + sysCtrl1x->PVD_CFG.BIT.pvd_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable PVD function. + * @retval None. + */ +static inline void DCL_PMC_DisablePvd(void) +{ + SYSCTRL1_RegStruct *sysCtrl1x = SYSCTRL1_BASE; + sysCtrl1x->PVD_CFG.BIT.pvd_en = BASE_CFG_DISABLE; +} + +/** + * @brief Set PVD threshold. + * @param threshold PMC PVD threshold voltage level. + * @retval None. + */ +static inline void DCL_PMC_SetPvdThreshold(PMC_PvdThreshold threshold) +{ + PMC_ASSERT_PARAM(IsPvdThreshold(threshold)); + SYSCTRL1_RegStruct *sysCtrl1x = SYSCTRL1_BASE; + sysCtrl1x->PVD_CFG.BIT.pvd_fall_thd = g_internalPvdValueTable[threshold][0]; + sysCtrl1x->PVD_CFG.BIT.pvd_rise_thd = g_internalPvdValueTable[threshold][1]; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_PMC_IP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/pmc/src/pmc.c b/vendor/xinlingyu_92_3061M/Project/drivers/pmc/src/pmc.c new file mode 100644 index 0000000000000000000000000000000000000000..34ecd0747c1ab667d927ed129a91c0a8d443ccee --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/pmc/src/pmc.c @@ -0,0 +1,199 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pmc.c + * @author MCU Driver Team. + * @brief ACMP HAL level module driver. + * This file provides firmware functions to manage the following + * functionalities of the DAC and Comparator. + * + PMC's initialization and de-initialization functions. + * + Enter sleep, deepsleep mode functions. + */ + +#include "pmc_ip.h" +#include "pmc.h" + +#define WAKEUP_ENABLE_OFFSET 0x8 +#define WAKE_ACT_MODE_REG_WIDTH 0x2 + +/** + * @brief Setting deepsleep wakeup source. + * @param pmcHandle: PMC handle. + * @retval None. + */ +static void PMC_SetDeepSleepWakeupSrc(PMC_Handle *pmcHandle) +{ + PMC_ASSERT_PARAM(pmcHandle != NULL); + PMC_ASSERT_PARAM(IsPMCInstance(pmcHandle->baseAddress)); + PMC_PARAM_CHECK_NO_RET(IsWakeupSrc(pmcHandle->wakeupSrc)); + if (pmcHandle->wakeupSrc == PMC_WAKEUP_NONE) { /* No wakeup source. */ + return; + } + + if (pmcHandle->wakeupSrc == PMC_WAKEUP_CNT) { + pmcHandle->baseAddress->CNT32K_WAKE_CYC = pmcHandle->wakeupTime; /* Set wakeup time */ + pmcHandle->baseAddress->WAKEUP_CTRL.BIT.cnt32k_wakeup_en = BASE_CFG_ENABLE; /* Enable wakeup from timer */ + } else { + PMC_PARAM_CHECK_NO_RET(IsActiveMode(pmcHandle->wakeupActMode)); + pmcHandle->baseAddress->WAKEUP_CTRL.reg |= (pmcHandle->wakeupActMode) \ + << (pmcHandle->wakeupSrc * WAKE_ACT_MODE_REG_WIDTH); + pmcHandle->baseAddress->WAKEUP_CTRL.reg |= ((0x1 << pmcHandle->wakeupSrc) << WAKEUP_ENABLE_OFFSET); + } +} + +/** + * @brief Init PVD function. + * @param pmcHandle: PMC handle. + * @retval None. + */ +static void PMC_PvdInit(PMC_Handle *pmcHandle) +{ + PMC_ASSERT_PARAM(pmcHandle != NULL); + PMC_ASSERT_PARAM(IsPMCInstance(pmcHandle->baseAddress)); + PMC_PARAM_CHECK_NO_RET(pmcHandle->pvdThreshold <= PMC_PVD_THRED_LEVEL7); + if (pmcHandle->pvdEnable == BASE_CFG_ENABLE) { /* if PVD function is enable */ + DCL_PMC_EnablePvd(); + DCL_PMC_SetPvdThreshold(pmcHandle->pvdThreshold); /* set PVD threhold voltage */ + } else { + DCL_PMC_DisablePvd(); + } +} + +/** + * @brief PMC initialize interface. + * @param handle: PMC handle. + * @retval None. + */ +void HAL_PMC_Init(PMC_Handle *handle) +{ + PMC_ASSERT_PARAM(handle != NULL); + PMC_ASSERT_PARAM(IsPMCInstance(handle->baseAddress)); + PMC_PvdInit(handle); + PMC_SetDeepSleepWakeupSrc(handle); +} + +/** + * @brief PMC deinitialize interface. + * @param handle: PMC handle. + * @retval None. + */ +void HAL_PMC_DeInit(PMC_Handle *handle) +{ + PMC_ASSERT_PARAM(handle != NULL); + PMC_ASSERT_PARAM(IsPMCInstance(handle->baseAddress)); + DCL_PMC_DisablePvd(); + handle->baseAddress->WAKEUP_CTRL.reg = BASE_CFG_DISABLE; /* Disable all wakeup source. */ + handle->userCallBack.PmcCallBack = NULL; /* Clean interrupt callback functions. */ +} + +/** + * @brief Enter sleep interface. + * @param None. + * @retval None. + */ +void HAL_PMC_EnterSleepMode(void) +{ +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + /* If user mode is supported, make sure to execute WFI + commands in machine mode */ + static unsigned int priv = RISCV_U_MODE; + RISCV_PRIV_MODE_SWITCH(priv); + __asm("wfi"); + RISCV_PRIV_MODE_SWITCH(priv); +#else + __asm("wfi"); +#endif +} + +/** + * @brief Enter deep sleep interface. + * @param handle: PMC handle. + * @retval None. + */ +void HAL_PMC_EnterDeepSleepMode(PMC_Handle *handle) +{ + PMC_ASSERT_PARAM(handle != NULL); + PMC_ASSERT_PARAM(IsPMCInstance(handle->baseAddress)); + handle->baseAddress->LOWPOWER_MODE.BIT.deepsleep_req = BASE_CFG_ENABLE; +} + +/** + * @brief Enter shutdown interface. + * @param handle: PMC handle. + * @retval None. + */ +void HAL_PMC_EnterShutdownMode(PMC_Handle *handle) +{ + BASE_FUNC_UNUSED(handle); + /* The 3061M does not support this function. */ +} + +/** + * @brief Get wakeup source type. + * @param handle: PMC handle. + * @retval Lowpower type. + */ +PMC_LowpowerType HAL_PMC_GetWakeupType(PMC_Handle *handle) +{ + PMC_ASSERT_PARAM(handle != NULL); + PMC_ASSERT_PARAM(IsPMCInstance(handle->baseAddress)); + + PMC_LowpowerType wakeupMode; + bool deepsleepFlag = BASE_CFG_UNSET; /* Set as default. */ + deepsleepFlag = handle->baseAddress->LOWPOWER_STATUS.BIT.starup_from_deepsleep; + if (deepsleepFlag == BASE_CFG_SET) { /* If deepsleep flag is set */ + wakeupMode = PMC_LP_DEEPSLEEP; + } else { + wakeupMode = PMC_LP_NONE; + } + return wakeupMode; +} + +/** + * @brief Interrupt handler function. + * @param handle PMC module handle. + * @retval None. + */ +void HAL_PMC_IrqHandler(void *handle) +{ + PMC_ASSERT_PARAM(handle != NULL); + PMC_Handle *pmcHandle = (PMC_Handle *)handle; + PMC_ASSERT_PARAM(IsPMCInstance(pmcHandle->baseAddress)); + + SYSCTRL1_RegStruct *sysCtrl1x = SYSCTRL1_BASE; + if (sysCtrl1x->PVD_STATUS.BIT.pvd_toggle == 1) { /* PVD interrupt */ + if (pmcHandle->userCallBack.PmcCallBack != NULL) { + pmcHandle->userCallBack.PmcCallBack(pmcHandle); /* execute user's callback */ + } + } +} + +/** + * @brief Interrupt callback functions registration interface. + * @param handle PMC module handle. + * @param callbackID base callback id + * @param pCallback Pointer for the user callback function. + * @retval None. + */ +void HAL_PMC_RegisterCallback(PMC_Handle *handle, PMC_CallBackID callbackID, PMC_CallbackType pCallback) +{ + PMC_ASSERT_PARAM(handle != NULL); + PMC_ASSERT_PARAM(IsPMCInstance(handle->baseAddress)); + PMC_ASSERT_PARAM(pCallback != NULL); + BASE_FUNC_UNUSED(callbackID); /* This parameter is not used to prevent compilation errors. */ + handle->userCallBack.PmcCallBack = pCallback; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/qdm/common/inc/qdm.h b/vendor/xinlingyu_92_3061M/Project/drivers/qdm/common/inc/qdm.h new file mode 100644 index 0000000000000000000000000000000000000000..b890338e9219b53e8ee0127d8e9172eb89d6f367 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/qdm/common/inc/qdm.h @@ -0,0 +1,156 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file qdm.h + * @author MCU Driver Team + * @brief QDM HAL level module driver head file. + * @details This file provides firmware functions to manage the following + * functionalities of the QDM. + * + Initialization and de-initialization functions. + * + Capm Module Control functions. + * + Speed measure use M function. + * + Stall condition detection. + */ +#ifndef McuMagicTag_QDM_H +#define McuMagicTag_QDM_H + +#include "typedefs.h" +#include "qdm_ip.h" + +#define SECONDS_PER_MINUTES 60 + +/** + * @defgroup QDM QDM + * @brief QDM module. + * @{ + */ + +/** + * @defgroup QDM_Common QDM Common + * @brief QDM common external module. + * @{ + */ + + +/** + * @defgroup QDM_Common_Param QDM Common Parameters + * @{ + */ + +/** + * @brief QDM callback function type + */ +typedef enum { + QDM_TSU_CYCLE = 0x00000000U, + QDM_SPEED_LOSE = 0x00000001U, + QDM_INDEX_LOCKED = 0x00000002U, + QDM_DIR_CHANGE = 0x00000003U, + QDM_PHASE_ERROR = 0x00000004U, + QDM_POS_MATCH = 0x00000005U, + QDM_POS_READY = 0x00000006U, + QDM_POS_CNT_ERROR = 0x00000007U, + QDM_POS_CNT_OVERFLOW = 0x00000008U, + QDM_POS_CNT_UNDERFLOW = 0x00000009U +} QDM_CallbackFuncType; + +/** + * @} + */ + +/** + * @defgroup QDM_Handle_Definition QDM Handle Definition + * @{ + */ + +/** + * @brief configurations of QDU register + */ +typedef struct { + QDM_DecoderMode decoderMode; + QDM_Resolution resolution; + QDM_QtrgLockMode trgLockMode; + QDM_PtuMode ptuMode; + QDM_SwapSelect swap; + unsigned int polarity; +} QDMCtrlConfigure; + +/** + * @brief configurations of input filter level + */ +typedef struct { + unsigned int qdmAFilterLevel; + unsigned int qdmBFilterLevel; + unsigned int qdmZFilterLevel; +} QDMFilter; + +/** + * @brief configurations of input filter level + */ +typedef struct _QDM_handle { + QDM_RegStruct *baseAddress; /**< base address */ + QDM_EmulationMode emuMode; /**< emulation mode select */ + QDMFilter inputFilter; /**< filter settings */ + QDMCtrlConfigure ctrlConfig; /**< QDM control configurations */ + QDM_PcntMode pcntMode; /**< position count mode */ + QDM_PcntRstMode pcntRstMode; /**< position count reset mode */ + QDM_PcntIdxInitMode pcntIdxInitMode; /**< position count index initial mode */ + bool subModeEn; /**< sub-module enable */ + QDM_TSUPrescaler tsuPrescaler; /**< tsu prescaler */ + QDM_CEVTPrescaler cevtPrescaler; /**< cevt prescaler */ + unsigned int posInit; /**< init position */ + unsigned int posMax; /**< max position */ + unsigned int qcMax; /**< TSU maximum counter number, default zero */ + unsigned int period; /**< PTU period*/ + unsigned int interruptEn; /**< interrupt settings by bits */ + int motorLineNum; /**< encoder line number */ + int speedRpm; /**< motor speed */ + QDM_IndexLockMode lock_mode; /**< QDM Z index lock mode */ + QDM_UserCallBack userCallBack; /**< QDM Interrupt callback functions */ + QDM_ExtendHandle handleEx; /**< QDM extend parameter */ +} QDM_Handle; + +typedef void (* QDM_CallbackType)(void *handle); +/** + * @} + */ + +/** + * @defgroup QDM_API_Declaration QDM HAL API + * @{ + */ + +/* Hardware abstraction layer */ +BASE_StatusType HAL_QDM_Init(QDM_Handle *qdmHandle); +BASE_StatusType HAL_QDM_DeInit(QDM_Handle *qdmHandle); +void HAL_QDM_GetPhaseErrorStatus(const QDM_Handle *qdmHandle, unsigned int *errStatus); +void HAL_QDM_ReadPosCountAndDir(const QDM_Handle *qdmHandle, unsigned int *count, unsigned int *dir); +int HAL_QDM_GetSpeedRpmM(QDM_Handle *qdmHandle); +int HAL_QDM_GetSpeedRpmMT(QDM_Handle *qdmHandle); +void HAL_QDM_IrqHandler(void *handle); +void HAL_QDM_RegisterCallback(QDM_Handle *qdmHandle, QDM_CallbackFuncType typeID, QDM_CallbackType pCallback); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/qdm/inc/qdm_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/qdm/inc/qdm_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..e19e6caf2c51fae68db7c11f0a0a1bd46007cb03 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/qdm/inc/qdm_ip.h @@ -0,0 +1,1663 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file qdm_ip.h + * @author MCU Driver Team + * @brief Header file containing QDM module DCL driver functions. + * This file provides functions to manage the following functionalities of QDM module. + * + Definition of QDM configuration parameters. + * + QDM registers mapping structure. + * + Direct Configuration Layer driver functions. + */ + +#ifndef McuMagicTag_QDM_IP_H +#define McuMagicTag_QDM_IP_H + +#include "baseinc.h" + +#ifdef QDM_PARAM_CHECK +#define QDM_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define QDM_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define QDM_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define QDM_ASSERT_PARAM(para) ((void)0U) +#define QDM_PARAM_CHECK_NO_RET(para) ((void)0U) +#define QDM_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +#define QDM_MAX_FILTER_LEVEL 0x00001FFF +#define QDM_PPU_MAX_SYNCOUT_PW 0x00000FFF +/** + * @addtogroup QDM + * @{ + */ + +/** + * @defgroup QDM_IP QDM_IP + * @brief QDM_IP: qdm_v0. + * @{ + */ + +/** + * @defgroup QDM_Param_Def QDM Parameters Definition + * @brief Definition of QDM configuration parameters + * @{ + */ + + +/** + * @brief Emulation mode of QDM module. + * @details Emulation mode: + * + QDM_EMULATION_MODE_STOP_IMMEDIATELY -- The position counter, unit timer, + * capture timer all stop immediately. + * + QDM_EMULATION_MODE_STOP_AT_ROLLOVER -- + * The position counter, unit timer count until period rollover, + * and the capture timer counts until the next unit period event. + * + QDM_EMULATION_MODE_RUN_FREE -- The position counter, unit timer, + * capture timer are all unaffected by an emulation suspend. + */ +typedef enum { + QDM_EMULATION_MODE_STOP_IMMEDIATELY = 0x00000000U, + QDM_EMULATION_MODE_STOP_AT_ROLLOVER = 0x00000001U, + QDM_EMULATION_MODE_RUN_FREE = 0x00000002U, +} QDM_EmulationMode; + +/** + * @brief Status flag of QDM module. + * @details status flag: + * + QDM_STATUS_POS_CNT_ERR -- Position counter error + * + QDM_STATUS_1ST_IDX_OCCURRED -- First index pulse occurred + * + QDM_STATUS_DIR_ON_1ST_IDX -- Direction of first index event + * + QDM_STATUS_CAP_DIR_ERR -- Direction changed between position capture events + * + QDM_STATUS_TSU_OVERFLW_ERR -- Timer stamp timer overflow + * + QDM_STATUS_SPEED_LOST -- Speed lost status + * + QDM_STATUS_DIR_FLAG -- Quadrature direction + * + QDM_STATUS_UNIT_POS_EVENT -- Unit position event detected + */ +typedef enum { + QDM_STATUS_POS_CNT_ERR = 0x00000001U, + QDM_STATUS_1ST_IDX_OCCURRED = 0x00000002U, + QDM_STATUS_DIR_ON_1ST_IDX = 0x00000004U, + QDM_STATUS_CAP_DIR_ERR = 0x00000008U, + QDM_STATUS_TSU_OVERFLW_ERR = 0x00000010U, + QDM_STATUS_SPEED_LOST = 0x00000020U, + QDM_STATUS_DIR_FLAG = 0x00000040U, + QDM_STATUS_UNIT_POS_EVENT = 0x00000080U, +} QDM_StatusFlag; + +/** + * @brief Decoder mode of QDM module. + * @details Decoder mode + * + QDM_QUADRATURE_COUNT -- Quadrature-clock mode + * + QDM_CLOCK_DIR_COUNT -- Direction-count mode + * + QDM_NONSTANDARD_TYPE1 -- Non-standard mode 1 + * + QDM_NONSTANDARD_TYPE2 -- Non-standard mode 2 + */ +typedef enum { + QDM_QUADRATURE_COUNT = 0x00000000U, + QDM_CLOCK_DIR_COUNT = 0x00000001U, + QDM_NONSTANDARD_TYPE1 = 0x00000002U, + QDM_NONSTANDARD_TYPE2 = 0x00000003U, +} QDM_DecoderMode; + +/** + * @brief Decode resolution of QDM module. + * @details Decode resolution: + * + QDM_1X_RESOLUTION -- Count rising edge of QDMA/QDMB only + * + QDM_2X_RESOLUTION -- Count rising and falling edge of QDMA/QDMB + * + QDM_4X_RESOLUTION -- Count rising and falling edge of both QDMA and QDMB + */ +typedef enum { + QDM_1X_RESOLUTION = 0x00000000U, + QDM_2X_RESOLUTION = 0x00000001U, + QDM_4X_RESOLUTION = 0x00000002U, +} QDM_Resolution; + +/** + * @brief Count mode of position processing submodule. + */ +typedef enum { + QDM_PPU_COUNT_MODE_CLK_DIR = 0x00000000U, + QDM_PPU_COUNT_MODE_INCREASE = 0x00000001U, + QDM_PPU_COUNT_MODE_DECREASE = 0x00000002U, +} QDM_PPUCountMode; + +/** + * @brief Reset mode of position counter. + * @details Reset mode: + * + QDM_POSITION_RESET_IDX -- Reset position on the rising edge of inde pulse + * + QDM_POSITION_RESET_MAX_POS -- Reset position on maximum position QCNTMAX + * + QDM_POSITION_RESET_1ST_IDX -- Reset position on the first index pulse + * + QDM_POSITION_RESET_UNIT_TIME_OUT -- Reset position on a unit time trigger + */ +typedef enum { + QDM_POSITION_RESET_IDX = 0x00000000, + QDM_POSITION_RESET_MAX_POS = 0x00000001, + QDM_POSITION_RESET_1ST_IDX = 0x00000002, + QDM_POSITION_RESET_UNIT_TIME_OUT = 0x00000003, +} QDM_PosResetMode; + +/** + * @brief Initializaion mode of the index of position counter. + * @details Initializaion mode: + * + QDM_POSITION_INIT_DO_NOTHING -- No action is configured + * + QDM_POSITION_INIT_RISING_INDEX -- On rising edge of index + * + QDM_POSITION_INIT_FALLING_INDEX -- On falling edge of index + */ +typedef enum { + QDM_POSITION_INIT_DO_NOTHING = 0x00000000U, + QDM_POSITION_INIT_RISING_INDEX = 0x00000002U, + QDM_POSITION_INIT_FALLING_INDEX = 0x00000003U, +} QDM_PosIdxInitMode; + +/** + * @brief Shadow load mode of compare counter. + * @details Load mode: + * + QDM_COMPARE_LOAD_ON_ZERO -- Load on QPOSCNT = 0 + * + QDM_COMPARE_LOAD_ON_MATCH -- Load on QPOSCNT = QPOSCMP + */ +typedef enum { + QDM_COMPARE_LOAD_ON_ZERO = 0x00000000U, + QDM_COMPARE_LOAD_ON_MATCH = 0x00000001U, +} QDM_CompShadowLoad; + +/** + * @brief Polarity of sync-out pulse for position compare. + */ +typedef enum { + QDM_SYNC_OUT_HIGH = 0x00000000U, + QDM_SYNC_OUT_LOW = 0x00000001U, +} QDM_CompSyncOutPolarity; + +/** + * @brief Lock mode of index event. + * @details Lock mode: + * + QDM_LOCK_RESERVE -- Do not lock + * + QDM_LOCK_RISING_INDEX -- On rising edge of index + * + QDM_LOCK_FALLING_INDEX -- On falling edge of index + * + QDM_LOCK_SW_INDEX_MARKER -- On software index marker + */ +typedef enum { + QDM_LOCK_RESERVE = 0x00000000, + QDM_LOCK_RISING_INDEX = 0x00000001, + QDM_LOCK_FALLING_INDEX = 0x00000002, + QDM_LOCK_SW_INDEX_MARKER = 0x00000003, +} QDM_IndexLockMode; + +/** + * @brief Prescaler of Time Stamp Unit clock. + * @details Prescaler: + * + QDM_TSU_CLK_DIV_1 -- TSUCLK = SYSCLKOUT/1 + * + QDM_TSU_CLK_DIV_2 -- TSUCLK = SYSCLKOUT/2 + * + QDM_TSU_CLK_DIV_4 -- TSUCLK = SYSCLKOUT/4 + * + QDM_TSUE_CLK_DIV_8 -- TSUCLK = SYSCLKOUT/8 + * + QDM_TSU_CLK_DIV_16 -- TSUCLK = SYSCLKOUT/16 + * + QDM_TSU_CLK_DIV_32 -- TSUCLK = SYSCLKOUT/32 + * + QDM_TSU_CLK_DIV_64 -- TSUCLK = SYSCLKOUT/64 + * + QDM_TSU_CLK_DIV_128 -- TSUCLK = SYSCLKOUT/128 + * + QDM_TSU_CLK_DIV_256 -- TSUCLK = SYSCLKOUT/256 + */ +typedef enum { + QDM_TSU_CLK_DIV_1 = 0x00000000U, + QDM_TSU_CLK_DIV_2 = 0x00000001U, + QDM_TSU_CLK_DIV_4 = 0x00000002U, + QDM_TSUE_CLK_DIV_8 = 0x00000003U, + QDM_TSU_CLK_DIV_16 = 0x00000004U, + QDM_TSU_CLK_DIV_32 = 0x00000005U, + QDM_TSU_CLK_DIV_64 = 0x00000006U, + QDM_TSU_CLK_DIV_128 = 0x00000007U, + QDM_TSU_CLK_DIV_256 = 0x00000008U, +} QDM_TSUCLKPrescale; + +/** + * @brief Prescaler of Unit Position Event. + * @details Prescaler: + * + QDM_UNIT_POS_EVNT_DIV_1 -- UPEVNT = QCLK/1 + * + QDM_UNIT_POS_EVNT_DIV_2 -- UPEVNT = QCLK/2 + * + QDM_UNIT_POS_EVNT_DIV_4 -- UPEVNT = QCLK/4 + * + QDM_UNIT_POS_EVNT_DIV_8 -- UPEVNT = QCLK/8 + * + QDM_UNIT_POS_EVNT_DIV_16 -- UPEVNT = QCLK/16 + * + QDM_UNIT_POS_EVNT_DIV_32 -- UPEVNT = QCLK/32 + * + QDM_UNIT_POS_EVNT_DIV_64 -- UPEVNT = QCLK/64 + * + QDM_UNIT_POS_EVNT_DIV_128 -- UPEVNT = QCLK/128 + * + QDM_UNIT_POS_EVNT_DIV_256 -- UPEVNT = QCLK/256 + * + QDM_UNIT_POS_EVNT_DIV_512 -- UPEVNT = QCLK/512 + * + QDM_UNIT_POS_EVNT_DIV_1024 -- UPEVNT = QCLK/1024 + * + QDM_UNIT_POS_EVNT_DIV_2048 -- UPEVNT = QCLK/2048 + */ +typedef enum { + QDM_UNIT_POS_EVNT_DIV_1 = 0x00000000U, + QDM_UNIT_POS_EVNT_DIV_2 = 0x00000001U, + QDM_UNIT_POS_EVNT_DIV_4 = 0x00000002U, + QDM_UNIT_POS_EVNT_DIV_8 = 0x00000003U, + QDM_UNIT_POS_EVNT_DIV_16 = 0x00000004U, + QDM_UNIT_POS_EVNT_DIV_32 = 0x00000005U, + QDM_UNIT_POS_EVNT_DIV_64 = 0x00000006U, + QDM_UNIT_POS_EVNT_DIV_128 = 0x00000007U, + QDM_UNIT_POS_EVNT_DIV_256 = 0x00000008U, + QDM_UNIT_POS_EVNT_DIV_512 = 0x00000009U, + QDM_UNIT_POS_EVNT_DIV_1024 = 0x0000000AU, + QDM_UNIT_POS_EVNT_DIV_2048 = 0x0000000BU, +} QDM_UPEvntPrescale; + +/** + * @brief Lock mode of Time Stamp Unit. + * @details Lock mode: + * + QDM_TSU_LOCK_ON_SW_READ -- When software read QPOSCNT + * + QDM_TSU_LOCK_ON_UTTRG -- When unit time trigger happens + */ +typedef enum { + QDM_TSU_LOCK_ON_SW_READ = 0x00000000U, + QDM_TSU_LOCK_ON_UTTRG = 0x00000001U, +} QDM_TSULockMode; + +/** + * @brief Working mode of Period Trigger Unit. + */ +typedef enum { + QDM_PERIOD_TRIGGER_MODE = 0x00000000U, + QDM_WATCHDOG_MODE = 0x00000001U, +} QDM_PTUMode; + +/** + * @brief Lock mode of Period Trigger Unit. + * @details Lock mode: + * + QDM_LOCK_POSCNT_READ_BY_CPU -- When QPOSCNT read by CPU/DMA, + * QCTMR and QCPRD are locked + * + QDM_LOCK_UNIT_TIME_TRIGGER,-- When PTU is enabled and unit time triggers, + * QPOSCNT, QCTMR, QCPRD are locked + */ +typedef enum { + QDM_LOCK_POSCNT_READ_BY_CPU, + QDM_LOCK_UNIT_TIME_TRIGGER, +} QDM_TriggerLockMode; /* QPOSCNT, QCTMR, QCPRD lock event */ + +/** + * @brief Interrupt events of QMD module. + * @details Interrupt events: + * + QDM_INT_POS_CNT_ERROR -- Position count error + * + QDM_INT_PHASE_ERROR -- Quadrature phase error + * + QDM_INT_WATCHDOG -- Speed lost error + * + QDM_INT_DIR_CHANGE -- Quadrature direction change + * + QDM_INT_UNDERFLOW -- Position counter underflow + * + QDM_INT_OVERFLOW -- Position counter overflow + * + QDM_INT_POS_COMP_READY -- Position-compare ready + * + QDM_INT_POS_COMP_MATCH -- Position-compare match + * + QDM_INT_INDEX_EVNT_LATCH -- Index event lock + * + QDM_INT_UNIT_TIME_OUT -- Unit time-out + */ +typedef enum { + QDM_INT_POS_CNT_ERROR = 0x00000001U, + QDM_INT_PHASE_ERROR = 0x00000002U, + QDM_INT_WATCHDOG = 0x00000004U, + QDM_INT_DIR_CHANGE = 0x00000008U, + QDM_INT_UNDERFLOW = 0x00000010U, + QDM_INT_OVERFLOW = 0x00000020U, + QDM_INT_POS_COMP_READY = 0x00000040U, + QDM_INT_POS_COMP_MATCH = 0x00000080U, + QDM_INT_INDEX_EVNT_LATCH = 0x00000100U, + QDM_INT_UNIT_TIME_OUT = 0x00000200U, +} QDM_InterruptEvent; + +/** + * @brief QDM TSU prescaler + * @details prescaler values: + * + QDM_TSU_PRESCALER_EQUAL -- Equal to the clock cycle + * + QDM_TSU_PRESCALER_2X -- 2x clock cycle + * + QDM_TSU_PRESCALER_4X -- 2x clock cycle + * + QDM_TSU_PRESCALER_8X -- 8x clock cycle + * + QDM_TSU_PRESCALER_16X -- 16x clock cycle + * + QDM_TSU_PRESCALER_32X -- 32x clock cycle + * + QDM_TSU_PRESCALER_64X -- 64x clock cycle + * + QDM_TSU_PRESCALER_128X -- 128x clock cycle + * + QDM_TSU_PRESCALER_256X -- 256x clock cycle + */ +typedef enum { + QDM_TSU_PRESCALER_EQUAL = 0x00000000U, + QDM_TSU_PRESCALER_2X = 0x00000001U, + QDM_TSU_PRESCALER_4X = 0x00000002U, + QDM_TSU_PRESCALER_8X = 0x00000003U, + QDM_TSU_PRESCALER_16X = 0x00000004U, + QDM_TSU_PRESCALER_32X = 0x00000005U, + QDM_TSU_PRESCALER_64X = 0x00000006U, + QDM_TSU_PRESCALER_128X = 0x00000007U, + QDM_TSU_PRESCALER_256X = 0x00000008U, +} QDM_TSUPrescaler; + +/** + * @brief QDM CEVT prescaler + * @details prescaler values: + * + QDM_CEVT_PRESCALER_DIVI1 -- Don't divided + * + QDM_CEVT_PRESCALER_DIVI2 -- Divide by 2 + * + QDM_CEVT_PRESCALER_DIVI4 -- Divide by 4 + * + QDM_CEVT_PRESCALER_DIVI8 -- Divide by 8 + * + QDM_CEVT_PRESCALER_DIVI16 -- Divide by 16 + * + QDM_CEVT_PRESCALER_DIVI32 -- Divide by 32 + * + QDM_CEVT_PRESCALER_DIVI64 -- Divide by 64 + * + QDM_CEVT_PRESCALER_DIVI128 -- Divide by 128 + * + QDM_CEVT_PRESCALER_DIVI256 -- Divide by 256 + * + QDM_CEVT_PRESCALER_DIVI512 -- Divide by 512 + * + QDM_CEVT_PRESCALER_DIVI1024 -- Divide by 1024 + * + QDM_CEVT_PRESCALER_DIVI2048 -- Divide by 2048 + */ +typedef enum { + QDM_CEVT_PRESCALER_DIVI1 = 0x00000000U, + QDM_CEVT_PRESCALER_DIVI2 = 0x00000001U, + QDM_CEVT_PRESCALER_DIVI4 = 0x00000002U, + QDM_CEVT_PRESCALER_DIVI8 = 0x00000003U, + QDM_CEVT_PRESCALER_DIVI16 = 0x00000004U, + QDM_CEVT_PRESCALER_DIVI32 = 0x00000005U, + QDM_CEVT_PRESCALER_DIVI64 = 0x00000006U, + QDM_CEVT_PRESCALER_DIVI128 = 0x00000007U, + QDM_CEVT_PRESCALER_DIVI256 = 0x00000008U, + QDM_CEVT_PRESCALER_DIVI512 = 0x00000009U, + QDM_CEVT_PRESCALER_DIVI1024 = 0x0000000AU, + QDM_CEVT_PRESCALER_DIVI2048 = 0x0000000BU, +} QDM_CEVTPrescaler; + +/** + * @brief QDM counter reset mode + */ +typedef enum { + QDM_IDX_INIT_DISABLE = 0x00000000U, + QDM_IDX_INIT_AUTO = 0x00000001U, + QDM_IDX_INIT_Z_UP = 0x00000002U, + QDM_IDX_INIT_Z_DOWN = 0x00000003U, +} QDM_PcntIdxInitMode; + +/** + * @brief QDM lock triggle mode + */ +typedef enum { + QDM_TRG_BY_READ = 0x00000000U, + QDM_TRG_BY_CYCLE = 0x00000001U, +} QDM_QtrgLockMode; + +/** + * @brief QDM PTU work mode + */ +typedef enum { + QDM_PTU_MODE_CYCLE = 0x00000000U, + QDM_PTU_MODE_WATCHDOG = 0x00000001U, +} QDM_PtuMode; + +/** + * @brief QDM count mode + */ +typedef enum { + QDM_PCNT_MODE_BY_DIR = 0x00000000U, + QDM_PCNT_MODE_UP = 0x00000001U, + QDM_PCNT_MODE_DOWN = 0x00000002U, +} QDM_PcntMode; + +/** + * @brief QDM counter reset mode + */ +typedef enum { + QDM_PCNT_RST_AUTO = 0x00000000U, + QDM_PCNT_RST_OVF = 0x00000001U, + QDM_PCNT_RST_HARDWARE_ONCE = 0x00000002U, + QDM_PCNT_RST_BY_PTU = 0x00000003U, +} QDM_PcntRstMode; + +/** + * @brief QDM swap selection + */ +typedef enum { + QDM_SWAP_DISABLE = 0x00000000U, + QDM_SWAP_ENABLE = 0x00000001U, +} QDM_SwapSelect; + +/** + * @brief Check whether the EMU mode is used. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsEmuMode(unsigned int mode) +{ + if (mode == QDM_EMULATION_MODE_STOP_IMMEDIATELY || mode == QDM_EMULATION_MODE_STOP_AT_ROLLOVER || + mode == QDM_EMULATION_MODE_RUN_FREE) { + return true; + } + return false; +} + +/** + * @brief Check whether the Z Index lock mode is used. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsLockMode(unsigned int mode) +{ + if (mode == QDM_LOCK_RESERVE || mode == QDM_LOCK_RISING_INDEX || + mode == QDM_LOCK_FALLING_INDEX || mode == QDM_LOCK_SW_INDEX_MARKER) { + return true; + } + return false; +} + +/** + * @brief Check whether the Decode mode is used. + * @param mode QDM decode mode + * @retval true + * @retval false + */ +static inline bool IsDecodeMode(unsigned int mode) +{ + if (mode <= QDM_NONSTANDARD_TYPE2) { + return true; + } + return false; +} + +/** + * @brief Check whether the resolution is right. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsResolution(unsigned int mode) +{ + if (mode == QDM_1X_RESOLUTION || mode == QDM_2X_RESOLUTION || mode == QDM_4X_RESOLUTION) { + return true; + } + return false; +} + +/** + * @brief Check whether the swap is right. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsSwap(unsigned int mode) +{ + if (mode == QDM_SWAP_DISABLE || mode == QDM_SWAP_ENABLE) { + return true; + } + return false; +} + +/** + * @brief Check whether the lock triggle mode is used. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsTrgLockMode(unsigned int mode) +{ + if (mode == QDM_TRG_BY_READ || mode == QDM_TRG_BY_CYCLE) { + return true; + } + return false; +} + +/** + * @brief Check whether the ptu mode is used. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsPtuMode(unsigned int mode) +{ + if (mode == QDM_PTU_MODE_CYCLE || mode == QDM_PTU_MODE_WATCHDOG) { + return true; + } + return false; +} + +/** + * @brief Check whether the position counter is used. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsPcntMode(unsigned int mode) +{ + if (mode == QDM_PCNT_MODE_BY_DIR || mode == QDM_PCNT_MODE_UP || mode == QDM_PCNT_MODE_DOWN) { + return true; + } + return false; +} + +/** + * @brief Check whether the PcntRstMode is used. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsPcntRstMode(unsigned int mode) +{ + if (mode == QDM_PCNT_RST_AUTO || mode == QDM_PCNT_RST_OVF || + mode == QDM_PCNT_RST_HARDWARE_ONCE || mode == QDM_PCNT_RST_BY_PTU) { + return true; + } + return false; +} + +/** + * @brief Check whether the PcntIdxInitMode is used. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsPcntIdxInitMode(unsigned int mode) +{ + if (mode == QDM_IDX_INIT_DISABLE || mode == QDM_IDX_INIT_AUTO || + mode == QDM_IDX_INIT_Z_UP || mode == QDM_IDX_INIT_Z_DOWN) { + return true; + } + return false; +} + +/** + * @brief Check whether the TsuPrescaler is used. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsTsuPrescaler(unsigned int mode) +{ + /* Check whether the TSU prescaler is right. */ + if (mode == QDM_TSU_PRESCALER_EQUAL || mode == QDM_TSU_PRESCALER_2X || + mode == QDM_TSU_PRESCALER_4X || mode == QDM_TSU_PRESCALER_8X || + mode == QDM_TSU_PRESCALER_16X || mode == QDM_TSU_PRESCALER_32X || + mode == QDM_TSU_PRESCALER_64X || mode == QDM_TSU_PRESCALER_128X || + mode == QDM_TSU_PRESCALER_256X) { + return true; + } + return false; +} + +/** + * @brief Check whether the CevtPrescaler is used. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsCevtPrescaler(unsigned int mode) +{ + /* Check whether the CEVT prescaler is right. */ + if (mode == QDM_CEVT_PRESCALER_DIVI1 || mode == QDM_CEVT_PRESCALER_DIVI2 || + mode == QDM_CEVT_PRESCALER_DIVI4 || mode == QDM_CEVT_PRESCALER_DIVI8 || + mode == QDM_CEVT_PRESCALER_DIVI16 || mode == QDM_CEVT_PRESCALER_DIVI32 || + mode == QDM_CEVT_PRESCALER_DIVI64 || mode == QDM_CEVT_PRESCALER_DIVI128 || + mode == QDM_CEVT_PRESCALER_DIVI256 || mode == QDM_CEVT_PRESCALER_DIVI512 || + mode == QDM_CEVT_PRESCALER_DIVI1024 || mode == QDM_CEVT_PRESCALER_DIVI2048) { + return true; + } + return false; +} + +/** + * @brief Check whether the QDM_StatusFlag is used. + * @param status QDM status flag + * @retval true + * @retval false + */ +static inline bool IsQDMStatusMode(QDM_StatusFlag status) +{ + /* Check whether the QDM Status flag is right. */ + if (status == QDM_STATUS_POS_CNT_ERR || status == QDM_STATUS_1ST_IDX_OCCURRED || + status == QDM_STATUS_DIR_ON_1ST_IDX || status == QDM_STATUS_CAP_DIR_ERR || + status == QDM_STATUS_TSU_OVERFLW_ERR || status == QDM_STATUS_SPEED_LOST || + status == QDM_STATUS_DIR_FLAG || status == QDM_STATUS_UNIT_POS_EVENT) { + return true; + } + return false; +} + +/** + * @brief Check whether the QDM interrupt event type is right. + * @param status QDM interrupt event + * @retval true + * @retval false + */ +static inline bool IsQDMInterruptEvent(QDM_InterruptEvent intEvt) +{ + /* Check whether the QDM interrupt type is right. */ + QDM_PARAM_CHECK_WITH_RET(intEvt >= QDM_INT_POS_CNT_ERROR, BASE_STATUS_ERROR); + QDM_PARAM_CHECK_WITH_RET(intEvt <= QDM_INT_UNIT_TIME_OUT, BASE_STATUS_ERROR); + if (intEvt == QDM_INT_POS_CNT_ERROR || ((unsigned int)intEvt % 2U) == 0) { + return true; + } + return false; +} + +/** + * @} + */ + + +/** + * @defgroup QDM_REG_Definition QDM Register Structure. + * @brief QDM Register Structure Definition. + * @{ + */ + +/** + * @brief QDM version registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int month_day : 16; /**< Month and day. */ + unsigned int year : 8; /**< Year. */ + unsigned int release_substep : 1; /**< Version information. */ + unsigned int release_step : 1; /**< Version information. */ + unsigned int release_ver : 1; /**< Version information. */ + unsigned int reserved_0 : 5; + } BIT; +} volatile QDM_QDMVER_REG; + +/** + * @brief QDM emulation mode configuration registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int emu_mode : 2; /**< QDM emulation access mode. */ + unsigned int reserved_0 : 30; + } BIT; +} volatile QDM_QEMUMODE_REG; + +/** + * @brief QDM control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ptu_en : 1; /**< PTU period triggle unit enable. */ + unsigned int ppu_en : 1; /**< PPU position process unit enable. */ + unsigned int tsu_en : 1; /**< TSU timestamp unit enable. */ + unsigned int ptu_mode : 1; /**< PTU work mode. */ + unsigned int qtrg_lock_mode : 1; /**< QDM triggle locked mode selection. */ + unsigned int reserved_0 : 3; + unsigned int qdmi_polarity : 1; /**< Z pulse polarity selection. */ + unsigned int qdmb_polarity : 1; /**< B pulse polarity selection. */ + unsigned int qdma_polarity : 1; /**< A pulse polarity selection. */ + unsigned int qdm_ab_swap : 1; /**< Input signal swap of A pulse and B pulse. */ + unsigned int qdu_xclk : 2; /**< QDM position pulse frequency multiplication. */ + unsigned int qdu_mode : 2; /**< QDM decode mode. */ + unsigned int reserved_1 : 16; + } BIT; +} volatile QDM_QCTRL_REG; + +/** + * @brief PPU control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ppu_syncout_pw : 12; /**< Pulse width selection of position comparison sync output. */ + unsigned int ppu_syncout_pl : 1; /**< Polarity of position comparison sync output. */ + unsigned int syncout_en : 1; /**< Position comparison sync output enable. */ + unsigned int reserved_0 : 2; + unsigned int ppu_poscmp_en : 1; /**< Position comparison function enable. */ + unsigned int ppu_cmpshd_ld : 1; /**< Load mode of position comparison buffer register. */ + unsigned int ppu_cmpshd_en : 1; /**< Position comparison buffer register enable. */ + unsigned int reserved_1 : 1; + unsigned int pcnt_idx_lock_mode : 2; /**< Z pulse locked mode selection of position counter. */ + unsigned int pcnt_idx_init_mode : 2; /**< Z pulse initialization mode of position counter. */ + unsigned int pcnt_rst_mode : 2; /**< Reset selection of position counter. */ + unsigned int pcnt_mode : 2; /**< Count mode of position counter. */ + unsigned int pcnt_sw_init : 1; /**< Software initialization of position counter. */ + unsigned int reserved_2 : 3; + } BIT; +} volatile QDM_QPPUCTRL_REG; + +/** + * @brief TSU control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cevt_prescaler : 4; /**< Frequency division selection of the capture event CEVT. */ + unsigned int tsu_prescaler : 4; /**< TSU timing step length selection. */ + unsigned int qtmr_lock_mode : 1; /**< TSU locked mode. */ + unsigned int reserved_0 : 23; + } BIT; +} volatile QDM_QTSUCTRL_REG; + +/** + * @brief QDM interrupt enable registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pcnt_err_en : 1; /**< Position count error interrupt enable. */ + unsigned int qphs_err_en : 1; /**< Quadrature pulse error interrupt enable. */ + unsigned int sped_lst_en : 1; /**< QDM speed loss interrupt enable. */ + unsigned int qdir_chg_en : 1; /**< Quadrature direction change interrupt enable. */ + unsigned int pcnt_udf_en : 1; /**< Position counter underflow interrupt enable. */ + unsigned int pcnt_ovf_en : 1; /**< Position counter overflow interrupt enable. */ + unsigned int pcnt_cpr_en : 1; /**< Position comparision ready interrupt enable. */ + unsigned int pcnt_cpm_en : 1; /**< Position comparision match interrupt enable. */ + unsigned int indx_lck_en : 1; /**< Z pulse locked fuction interrupt enable. */ + unsigned int utmr_prd_en : 1; /**< PTU period interrupt enable. */ + unsigned int reserved_0 : 2; + unsigned int reserved_1 : 20; + } BIT; +} volatile QDM_QINTENA_REG; + +/** + * @brief QDM interrupt status registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pcnt_err_int : 1; /**< Position count error interrupt. */ + unsigned int qphs_err_int : 1; /**< Quadrature pulse error interrupt. */ + unsigned int sped_lst_int : 1; /**< QDM speed loss interrupt. */ + unsigned int qdir_chg_int : 1; /**< Quadrature direction change interrupt. */ + unsigned int pcnt_udf_int : 1; /**< Position counter underflow interrupt. */ + unsigned int pcnt_ovf_int : 1; /**< Position counter overflow interrupt. */ + unsigned int pcnt_cpr_int : 1; /**< Position comparision ready interrupt. */ + unsigned int pcnt_cpm_int : 1; /**< Position comparision match interrupt. */ + unsigned int indx_lck_int : 1; /**< Z pulse locked fuction interrupt. */ + unsigned int utmr_prd_int : 1; /**< PTU period interrupt. */ + unsigned int reserved_0 : 2; + unsigned int reserved_1 : 20; + } BIT; +} volatile QDM_QINTSTS_REG; + +/** + * @brief QDM initial interrupt registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pcnt_err_raw : 1; /**< Position count error initial interrupt. */ + unsigned int qphs_err_raw : 1; /**< Quadrature pulse error initial interrupt. */ + unsigned int sped_lst_raw : 1; /**< QDM speed loss initial interrupt. */ + unsigned int qdir_chg_raw : 1; /**< Quadrature direction change initial interrupt. */ + unsigned int pcnt_udf_raw : 1; /**< Position counter underflow initial interrupt. */ + unsigned int pcnt_ovf_raw : 1; /**< Position counter overflow initial interrupt. */ + unsigned int pcnt_cpr_raw : 1; /**< Position comparision ready initial interrupt. */ + unsigned int pcnt_cpm_raw : 1; /**< Position comparision match initial interrupt. */ + unsigned int indx_lck_raw : 1; /**< Z pulse locked fuction initial interrupt. */ + unsigned int utmr_prd_raw : 1; /**< PTU period initial interrupt. */ + unsigned int reserved_0 : 2; + unsigned int reserved_1 : 20; + } BIT; +} volatile QDM_QINTRAW_REG; + +/** + * @brief QDM injection interrupt registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pcnt_err_inj : 1; /**< Position count error injection interrupt. */ + unsigned int qphs_err_inj : 1; /**< Quadrature pulse error injection interrupt. */ + unsigned int sped_lst_inj : 1; /**< QDM speed loss injection interrupt. */ + unsigned int qdir_chg_inj : 1; /**< Quadrature direction change injection interrupt. */ + unsigned int pcnt_udf_inj : 1; /**< Position counter underflow injection interrupt. */ + unsigned int pcnt_ovf_inj : 1; /**< Position counter overflow injection interrupt. */ + unsigned int pcnt_cpr_inj : 1; /**< Position comparision ready injection interrupt. */ + unsigned int pcnt_cpm_inj : 1; /**< Position comparision match injection interrupt. */ + unsigned int indx_lck_inj : 1; /**< Z pulse locked fuction injection interrupt. */ + unsigned int utmr_prd_inj : 1; /**< PTU period injection interrupt. */ + unsigned int reserved_0 : 2; + unsigned int reserved_1 : 20; + } BIT; +} volatile QDM_QINTINJ_REG; + +/** + * @brief QDM status registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pcnt_err_sts : 1; /**< Position count error status. */ + unsigned int fidx_is_sts : 1; /**< Whether QDM passes the first Z-phase marker. */ + unsigned int fidx_dir_sts : 1; /**< The direction of QDM firstly passes the Z-phase marker. */ + unsigned int qcdr_err_sts : 1; /**< QDM capture direction error status. */ + unsigned int qctmr_ovf_sts : 1; /**< TSU timing count overflow status. */ + unsigned int sepd_lst_sts : 1; /**< QDM speed loss status. */ + unsigned int qdir_sts : 1; /**< QDM quadrature direction status. */ + unsigned int cevt_sts : 1; /**< QDM capture events status. */ + unsigned int reserved_0 : 24; + } BIT; +} volatile QDM_QDMSTS_REG; + +/** + * @brief QDM A-phase signal filter registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int qdma_ft_level : 13; /**< The filter level of A-phase signal. */ + unsigned int reserved_0 : 19; + } BIT; +} volatile QDM_QDMAFT_REG; + +/** + * @brief QDM B-phase signal filter registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int qdmb_ft_level : 13; /**< The filter level of B-phase signal. */ + unsigned int reserved_0 : 19; + } BIT; +} volatile QDM_QDMBFT_REG; + +/** + * @brief QDM Z-phase signal filter registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int qdmi_ft_level : 13; /**< The filter level of Z-phase signal. */ + unsigned int reserved_0 : 19; + } BIT; +} volatile QDM_QDMIFT_REG; + +/** + * @brief QDM Interrupt callback functions. + * + */ +typedef struct { + void (* PtuCycleTrgCallback)(void *handle); /**< PTU triggle interrupt callback */ + void (* SpeedLoseCallback)(void *handle); /**< speed lose detection callback */ + void (* ZIndexLockedCallBack)(void *handle); /**< Z index lock interrupt callback.*/ + void (* PositionCompareMatchCallBack)(void *handle); /**< Position compare match interrupt. */ + void (* PositionCompareReadyCallBack)(void *handle); /**< Position compare ready interrupt. */ + void (* PositionCounterOverflowCallBack)(void *handle); /**< Position counter overflow interrupt. */ + void (* PositionCounterUnderflowCallBack)(void *handle); /**< Position counter underflow interrupt. */ + void (* OrthogonalDirectionChangeCallBack)(void *handle); /**< Orthogonal direction change interrupt. */ + void (* OrthogonalPhaseErrorCallBack)(void *handle); /**< Orthogonal phase error interrupt. */ + void (* PositionCounterErrorCallBack)(void *handle); /**< Position counter error interrupt. */ +} QDM_UserCallBack; + +/** + * @brief QDM extend handle. + */ +typedef struct _QDM_ExtendeHandle { +} QDM_ExtendHandle; + +/** + * @brief QDM registers definition structure. + */ +typedef struct { + QDM_QDMVER_REG QDMVER; /**< QDM version register, offset address: 0x0000. */ + QDM_QEMUMODE_REG QEMUMODE; /**< QDM emulation mode configuration register, offset address: 0x0004. */ + QDM_QCTRL_REG QCTRL; /**< QDM control register, offset address: 0x0008. */ + QDM_QPPUCTRL_REG QPPUCTRL; /**< PPU control register, offset address: 0x000C. */ + QDM_QTSUCTRL_REG QTSUCTRL; /**< TSU control register, offset address: 0x0010. */ + QDM_QINTENA_REG QINTENA; /**< QDM interrupt enable register, offset address: 0x0014. */ + QDM_QINTSTS_REG QINTSTS; /**< QDM interrupt status register, offset address: 0x0018. */ + QDM_QINTRAW_REG QINTRAW; /**< QDM initial interrupt register, offset address: 0x001C. */ + QDM_QINTINJ_REG QINTINJ; /**< QDM injection interrupt register, offset address: 0x0020. */ + QDM_QDMSTS_REG QDMSTS; /**< QDM status register, offset address: 0x0024. */ + unsigned int QPOSCNT; /**< PPU position counter value, offset address: 0x0028. */ + unsigned int QPOSINIT; /**< PPU position counter initialization value, offset address: 0x002C. */ + unsigned int QPOSMAX; /**< PPU position counter maximum value, offset address: 0x0030. */ + unsigned int QPOSCMP; /**< PPU position counter compare value, offset address: 0x0034. */ + unsigned int QPOSILOCK; /**< PPU QPOSCNT inde locked value, offset address: 0x0038. */ + unsigned int QPOSLOCK; /**< PPU QPOSCNT locked value, offset address: 0x003C. */ + unsigned int QUTMR; /**< PTU counter value, offset address: 0x0040. */ + unsigned int QUPRD; /**< PTU period value, offset address: 0x0044. */ + unsigned int QCTMR; /**< TSU counter value, offset address: 0x0048. */ + unsigned int QCMAX; /**< TSU counter maximum value, offset address: 0x004C. */ + unsigned int QCPRD; /**< TSU-captured CEVT's period, offset address: 0x0050. */ + unsigned int QCTMRLOCK; /**< QCTMR locked value, offset address: 0x0054. */ + unsigned int QCPRDLOCK; /**< QCPRD locked value, offset address: 0x0058. */ + QDM_QDMAFT_REG QDMAFT; /**< QDM A-phase signal filter register, offset address: 0x005C. */ + QDM_QDMBFT_REG QDMBFT; /**< QDM B-phase signal filter register, offset address: 0x0060. */ + QDM_QDMIFT_REG QDMIFT; /**< QDM Z-phase signal filter register, offset address: 0x0064. */ + unsigned int QPOSCMPA; /**< QDM Position Counter Active Compare Value, offset address: 0x0068. */ +} volatile QDM_RegStruct; + +/** + * @brief Set the emulation mode of QDM module. + * @param qdmx QDM register base address. + * @param emuMode Emulation mode. + * @retval None. + */ +static inline void DCL_QDM_SetEmulationMode(QDM_RegStruct *qdmx, QDM_EmulationMode emuMode) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(emuMode >= QDM_EMULATION_MODE_STOP_IMMEDIATELY); + QDM_PARAM_CHECK_NO_RET(emuMode <= QDM_EMULATION_MODE_RUN_FREE); + qdmx->QEMUMODE.BIT.emu_mode = emuMode; +} + +/** + * @brief Get the working status of QDM module. + * @param qdmx QDM register base address. + * @param status Working status flag. + * @retval unsigned short The flag value. + */ +static inline bool DCL_QDM_GetModuleStatus(const QDM_RegStruct *qdmx, QDM_StatusFlag status) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_ASSERT_PARAM(IsQDMStatusMode(status)); + return ((qdmx->QDMSTS.reg & (unsigned int)status) == status); +} + +/** + * @brief Clear the specific working status of QDM module. + * @param qdmx QDM register base address. + * @param status Working status flag. + * @retval None. + */ +static inline void DCL_QDM_ClearModuleStatus(QDM_RegStruct *qdmx, QDM_StatusFlag status) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_ASSERT_PARAM(IsQDMStatusMode(status)); + qdmx->QDMSTS.reg |= (unsigned int)status; +} + +/* Quadrature Decoder Unit --------------------------------------------------------------------- */ +/** + * @brief Set the polarity of QDM module inputs. + * @param qdmx QDM register base address. + * @param ivtQDMA QDMA input. + * @param ivtQDMB QDMB input. + * @param ivtQDMI QDMI input. + * @retval None. + */ +static inline void DCL_QDM_SetInputPolarity(QDM_RegStruct *qdmx, bool ivtQDMA, bool ivtQDMB, bool ivtQDMI) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QCTRL.BIT.qdma_polarity = ivtQDMA; + qdmx->QCTRL.BIT.qdmb_polarity = ivtQDMB; + qdmx->QCTRL.BIT.qdmi_polarity = ivtQDMI; +} + +/** + * @brief Set the filter width of QDM module inputs. + * @param qdmx QDM register base address. + * @param filtWidthQDMA Filter width of QDMA input. + * @param filtWidthQDMB Filter width of QDMB input. + * @param filtWidthQDMI Filter width of QDMI input. + * @retval None. + */ +static inline void DCL_QDM_SetInputFilterWidth(QDM_RegStruct *qdmx, + unsigned short filtWidthQDMA, + unsigned short filtWidthQDMB, + unsigned short filtWidthQDMI) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(filtWidthQDMA <= QDM_MAX_FILTER_LEVEL); + QDM_PARAM_CHECK_NO_RET(filtWidthQDMB <= QDM_MAX_FILTER_LEVEL); + QDM_PARAM_CHECK_NO_RET(filtWidthQDMI <= QDM_MAX_FILTER_LEVEL); + /* Set QDM input filter width. */ + qdmx->QDMAFT.BIT.qdma_ft_level = filtWidthQDMA; + qdmx->QDMBFT.BIT.qdmb_ft_level = filtWidthQDMB; + qdmx->QDMIFT.BIT.qdmi_ft_level = filtWidthQDMI; +} + +/** + * @brief Swap the inputs of QDMA and QDMB. + * @param qdmx QDM register base address. + * @param swap Swap enable. + * @retval None. + */ +static inline void DCL_QDM_SetABSwap(QDM_RegStruct *qdmx, bool swap) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QCTRL.BIT.qdm_ab_swap = swap; +} + +/** + * @brief Set the decoder mode of QDM module. + * @param qdmx QDM register base address. + * @param decoderMode Decoder mode. + * @retval None. + */ +static inline void DCL_QDM_SetDecoderMode(QDM_RegStruct *qdmx, QDM_DecoderMode decoderMode) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(IsDecodeMode(decoderMode)); + qdmx->QCTRL.BIT.qdu_mode = decoderMode; +} + +/** + * @brief Set the resolution of decoder. + * @param qdmx QDM register base address. + * @param resolution Decoder resolution. + * @retval None. + */ +static inline void DCL_QDM_SetResolution(QDM_RegStruct *qdmx, QDM_Resolution resolution) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(resolution >= QDM_1X_RESOLUTION); + QDM_PARAM_CHECK_NO_RET(resolution <= QDM_4X_RESOLUTION); + qdmx->QCTRL.BIT.qdu_xclk = resolution; +} + +/* Position Process Unit ----------------------------------------------------------------------- */ +/** + * @brief Enable Position Process Unit. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_EnablePosProcess(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QCTRL.BIT.ppu_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable Position Process Unit. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_DisablePosProcess(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QCTRL.BIT.ppu_en = BASE_CFG_DISABLE; +} + +/** + * @brief Enable/Disable software initialization of position counter. + * @param qdmx QDM register base address. + * @param swInit Software enable. + * @retval None. + */ +static inline void DCL_QDM_SetSWPosInit(QDM_RegStruct *qdmx, bool swInit) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPPUCTRL.BIT.pcnt_sw_init = swInit; +} + +/** + * @brief Set the count mode of position counter. + * @param qdmx QDM register base address. + * @param cntMode Count mode. + * @retval None. + */ +static inline void DCL_QDM_SetCountMode(QDM_RegStruct *qdmx, QDM_PPUCountMode cntMode) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(cntMode >= QDM_PPU_COUNT_MODE_CLK_DIR); + QDM_PARAM_CHECK_NO_RET(cntMode <= QDM_PPU_COUNT_MODE_DECREASE); + qdmx->QPPUCTRL.BIT.pcnt_mode = cntMode; +} + +/** + * @brief Set the reset mode of position counter. + * @param qdmx QDM register base address. + * @param rstMode Reset mode. + * @retval None. + */ +static inline void DCL_QDM_SetPosResetMode(QDM_RegStruct *qdmx, QDM_PosResetMode rstMode) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(rstMode >= QDM_POSITION_RESET_IDX); + QDM_PARAM_CHECK_NO_RET(rstMode <= QDM_POSITION_RESET_UNIT_TIME_OUT); + qdmx->QPPUCTRL.BIT.pcnt_rst_mode = rstMode; +} + +/** + * @brief Set the initialization mode of position counter. + * @param qdmx QDM register base address. + * @param initMode Initialization mode. + * @retval None. + */ +static inline void DCL_QDM_SetPosInitMode(QDM_RegStruct *qdmx, QDM_PosIdxInitMode initMode) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(initMode >= QDM_POSITION_INIT_DO_NOTHING); + QDM_PARAM_CHECK_NO_RET(initMode <= QDM_POSITION_INIT_FALLING_INDEX); + qdmx->QPPUCTRL.BIT.pcnt_idx_init_mode = initMode; +} + +/** + * @brief Set the index lock mode. + * @param qdmx QDM register base address. + * @param lockMode Lock mode of index. + * @retval None. + */ +static inline void DCL_QDM_SetIndexLockMode(QDM_RegStruct *qdmx, QDM_IndexLockMode lockMode) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(lockMode >= QDM_LOCK_RESERVE); + QDM_PARAM_CHECK_NO_RET(lockMode <= QDM_LOCK_SW_INDEX_MARKER); + qdmx->QPPUCTRL.BIT.pcnt_idx_lock_mode = lockMode; +} + +/** + * @brief Set the initial value of position counter. + * @param qdmx QDM register base address. + * @param position Initial value. + * @retval None. + */ +static inline void DCL_QDM_SetInitialPos(QDM_RegStruct *qdmx, unsigned int position) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPOSINIT = position; +} + +/** + * @brief Set the max value of position counter. + * @param qdmx QDM register base address. + * @param maxPos Max value. + * @retval None. + */ +static inline void DCL_QDM_SetMaxPos(QDM_RegStruct *qdmx, unsigned int maxPos) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPOSMAX = maxPos; +} + +/** + * @brief Get the current value of position counter. + * @param qdmx QDM register base address. + * @retval unsigned int Value of position counter. + * @retval None. + */ +static inline unsigned int DCL_QDM_GetCurPos(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return (qdmx->QPOSCNT); +} + +/** + * @brief Enable position compare. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_EnablePosComp(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPPUCTRL.BIT.ppu_poscmp_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable position compare. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_DisablePosComp(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPPUCTRL.BIT.ppu_poscmp_en = BASE_CFG_DISABLE; +} + +/** + * @brief Set the position compare value. + * @param qdmx QDM register base address. + * @param compVal Compare value. + * @retval None. + */ +static inline void DCL_QDM_SetPosCompVal(QDM_RegStruct *qdmx, unsigned int compVal) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPOSCMP = compVal; +} + +/** + * @brief Enable position compare sync-out pulse. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_EnableCompSyncOut(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPPUCTRL.BIT.syncout_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable position compare sync-out pulse. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_DisableCompSyncOut(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPPUCTRL.BIT.syncout_en = BASE_CFG_DISABLE; +} + +/** + * @brief Set the pulse width of position compare sync-out pulse. + * @param qdmx QDM register base address. + * @param width Pulse width. + * @retval None. + */ +static inline void DCL_QDM_SetCompSyncOutWidth(QDM_RegStruct *qdmx, unsigned short width) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(width <= QDM_PPU_MAX_SYNCOUT_PW); + /* In units of 4 PCLK cycles */ + qdmx->QPPUCTRL.BIT.ppu_syncout_pw = width; +} + +/** + * @brief Set the polarity of position compare sync-out pulse. + * @param qdmx QDM register base address. + * @param polarity Sync-out pulse polarity. + * @retval None. + */ +static inline void DCL_QDM_SetCompSyncOutPolarity(QDM_RegStruct *qdmx, QDM_CompSyncOutPolarity polarity) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(polarity == QDM_SYNC_OUT_HIGH || polarity == QDM_SYNC_OUT_LOW); + qdmx->QPPUCTRL.BIT.ppu_syncout_pl = polarity; +} + +/** + * @brief Enable shadow mode of position compare. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_EnablePosCompShadow(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPPUCTRL.BIT.ppu_cmpshd_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable shadow mode of position compare. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_DisablePosCompShadow(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPPUCTRL.BIT.ppu_cmpshd_en = BASE_CFG_DISABLE; +} + +/** + * @brief Set the shadow load mode of position compare. + * @param qdmx QDM register base address. + * @param shadowMode Shadow load mode. + * @retval None. + */ +static inline void DCL_QDM_SetCompShadowMode(QDM_RegStruct *qdmx, QDM_CompShadowLoad shadowMode) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(shadowMode == QDM_COMPARE_LOAD_ON_ZERO || shadowMode == QDM_COMPARE_LOAD_ON_MATCH); + qdmx->QPPUCTRL.BIT.ppu_cmpshd_ld = shadowMode; +} + +/** + * @brief Get the position index lock value. + * @param qdmx QDM register base address. + * @retval unsigned int Index lock value. + */ +static inline unsigned int DCL_QDM_GetPosIndexLock(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return (qdmx->QPOSILOCK); +} + +/** + * @brief Get the unit time position lock value. + * @param qdmx QDM register base address. + * @retval unsigned int Unit time position lock value. + */ +static inline unsigned int DCL_QDM_GetPosUnitTimeLock(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return (qdmx->QPOSLOCK); +} + +/* Time Stamp Unit ----------------------------------------------------------------------------- */ +/** + * @brief Enable Time Stamp Unit capture. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_EnableTSUCap(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + /* EQEP_enableCapture */ + qdmx->QCTRL.BIT.tsu_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable Time Stamp Unit capture. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_DisableTSUCap(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + /* EQEP_disableCapture */ + qdmx->QCTRL.BIT.tsu_en = BASE_CFG_DISABLE; +} + +/** + * @brief Configure Time Stamp Unit capture. + * @param qdmx QDM register base address. + * @param tscPrsc Clock prescaler. + * @param evtPrsc Unit position event prescaler. + * @param tsuLock Time Stamp Unit lock mode. + * @retval None. + */ +static inline void DCL_QDM_ConfigTSUCap(QDM_RegStruct *qdmx, + QDM_TSUCLKPrescale tscPrsc, + QDM_UPEvntPrescale evtPrsc, + QDM_TSULockMode tsuLock) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + /* Check whether function parameters the is right. */ + QDM_PARAM_CHECK_NO_RET(tscPrsc >= QDM_TSU_CLK_DIV_1); + QDM_PARAM_CHECK_NO_RET(tscPrsc <= QDM_TSU_CLK_DIV_256); + QDM_PARAM_CHECK_NO_RET(evtPrsc >= QDM_UNIT_POS_EVNT_DIV_1); + QDM_PARAM_CHECK_NO_RET(evtPrsc <= QDM_UNIT_POS_EVNT_DIV_2048); + QDM_PARAM_CHECK_NO_RET(tsuLock == QDM_TSU_LOCK_ON_SW_READ || tsuLock == QDM_TSU_LOCK_ON_UTTRG); + qdmx->QTSUCTRL.BIT.tsu_prescaler = tscPrsc; + qdmx->QTSUCTRL.BIT.cevt_prescaler = evtPrsc; + qdmx->QTSUCTRL.BIT.qtmr_lock_mode = tsuLock; +} + +/** + * @brief Get the capture timer value. + * @param qdmx QDM register base address. + * @retval unsigned int The capture timer value. + */ +static inline unsigned int DCL_QDM_GetCapTimer(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return (qdmx->QCTMR); +} + +/** + * @brief Set the max value of capture timer. + * @param qdmx QDM register base address. + * @param maxCount Max value. + * @retval None. + */ +static inline void DCL_QDM_SetCapMaxCnt(QDM_RegStruct *qdmx, unsigned int maxCount) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QCMAX = maxCount; +} + +/** + * @brief Get the period of capture timer. + * @param qdmx QDM register base address. + * @retval unsigned int Period of capture timer. + */ +static inline unsigned int DCL_QDM_GetCapPeriod(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return (qdmx->QCPRD); +} + +/** + * @brief Get the lock value of capture timer. + * @param qdmx QDM register base address. + * @retval unsigned int Lock value. + */ +static inline unsigned int DCL_QDM_GetCapTimerLock(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return (qdmx->QCTMRLOCK); +} + +/** + * @brief Get the period value of capture timer. + * @param qdmx QDM register base address. + * @retval unsigned int Period value of capture timer. + */ +static inline unsigned int DCL_QDM_GetCapPeriodLock(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return (qdmx->QCPRDLOCK); +} + +/* Period Trigger Unit ------------------------------------------------------------------------- */ +/** + * @brief Enable Period Trigger Unit. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_EnablePeriodTrigger(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QCTRL.BIT.ptu_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable Period Trigger Unit. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_DisablePeriodTrigger(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QCTRL.BIT.ptu_en = BASE_CFG_DISABLE; +} + +/** + * @brief Set the working mode of Period Trigger Unit. + * @param qdmx QDM register base address. + * @param ptuMode Working mode of Period Trigger Unit. + * @retval None. + */ +static inline void DCL_QDM_SetPeriodTriggerUnitMode(QDM_RegStruct *qdmx, QDM_PTUMode ptuMode) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(ptuMode == QDM_PERIOD_TRIGGER_MODE || ptuMode == QDM_WATCHDOG_MODE); + qdmx->QCTRL.BIT.ptu_mode = ptuMode; +} + +/** + * @brief Set the trigger lock mode. + * @param qdmx QDM register base address. + * @param lockMode Trigger lock mode. + * @retval None. + */ +static inline void DCL_QDM_SetTriggerLockMode(QDM_RegStruct *qdmx, QDM_TriggerLockMode lockMode) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(lockMode == QDM_LOCK_POSCNT_READ_BY_CPU || lockMode == QDM_LOCK_UNIT_TIME_TRIGGER); + qdmx->QCTRL.BIT.qtrg_lock_mode = lockMode; +} + +/** + * @brief Set the period of unit time event. + * @param qdmx QDM register base address. + * @param period Period of unit time event. + * @retval None. + */ +static inline void DCL_QDM_SetTriggerPeriod(QDM_RegStruct *qdmx, unsigned int period) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QUPRD = period; +} + +/** + * @brief Get the value of period counter. + * @param qdmx QDM register base address. + * @retval unsigned int Value of period counter. + */ +static inline unsigned int DCL_QDM_GetPeriodCounter(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return (qdmx->QUTMR); +} + +/* Interrupt Generator ------------------------------------------------------------------------- */ +/** + * @brief Enable specific interrupt. + * @param qdmx QDM register base address. + * @param intEvt Interrupt event. + * @retval None. + */ +static inline void DCL_QDM_EnableInterrupt(QDM_RegStruct *qdmx, QDM_InterruptEvent intEvt) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + /* Check whether the QDM interrupt type is right. */ + QDM_PARAM_CHECK_NO_RET(IsQDMInterruptEvent(intEvt)); + qdmx->QINTENA.reg |= (unsigned int)intEvt; +} + +/** + * @brief Disable specific interrupt. + * @param qdmx QDM register base address. + * @param intEvt Interrupt event. + * @retval None. + */ +static inline void DCL_QDM_DisableInterrupt(QDM_RegStruct *qdmx, QDM_InterruptEvent intEvt) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + /* Check whether the QDM interrupt type is right. */ + QDM_PARAM_CHECK_NO_RET(IsQDMInterruptEvent(intEvt)); + qdmx->QINTENA.reg &= (~(unsigned int)intEvt); +} + +/** + * @brief Get the specific interrupt flag. + * @param qdmx QDM register base address. + * @param intEvt Interrupt event. + * @retval bool true, false. + */ +static inline bool DCL_QDM_GetInterruptFlag(QDM_RegStruct *qdmx, QDM_InterruptEvent intEvt) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + /* Check whether the QDM interrupt type is right. */ + QDM_ASSERT_PARAM(IsQDMInterruptEvent(intEvt)); + return ((qdmx->QINTSTS.reg & (unsigned int)intEvt) == intEvt); +} + +/** + * @brief Clear the specific interrupt flag. + * @param qdmx QDM register base address. + * @param intEvt Interrupt event. + * @retval None. + */ +static inline void DCL_QDM_ClearInterrupt(QDM_RegStruct *qdmx, QDM_InterruptEvent intEvt) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + /* Check whether the QDM interrupt type is right. */ + QDM_PARAM_CHECK_NO_RET(IsQDMInterruptEvent(intEvt)); + qdmx->QINTRAW.reg |= (unsigned int)intEvt; +} + +/** + * @brief Force a specific interrupt. + * @param qdmx QDM register base address. + * @param intEvt Interrupt event. + * @retval None. + */ +static inline void DCL_QDM_ForceInterrupt(QDM_RegStruct *qdmx, QDM_InterruptEvent intEvt) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + /* Check whether the QDM interrupt type is right. */ + QDM_PARAM_CHECK_NO_RET(IsQDMInterruptEvent(intEvt)); + qdmx->QINTINJ.reg |= (unsigned int)intEvt; +} + +/** + * @brief Enable speed lost raw interrupt. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_EnableSpedLstRaw(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QINTRAW.BIT.sped_lst_raw = BASE_CFG_ENABLE; +} + +/** + * @brief Enable PTU period raw interrupt. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_EnableUtmrPrdRaw(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QINTRAW.BIT.utmr_prd_raw = BASE_CFG_ENABLE; +} + +/** + * @brief Set the event status. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_SetCevtSts(QDM_RegStruct *qdmx, unsigned int status) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QDMSTS.BIT.cevt_sts = status; +} + +/** + * @brief Get the event status. + * @param qdmx QDM register base address. + * @retval unsigned int Value of cevt_sts. + */ +static inline unsigned int DCL_QDM_GetCevtSts(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return qdmx->QDMSTS.BIT.cevt_sts; +} + +/** + * @brief Get TSU overflow status. + * @param qdmx QDM register base address. + * @retval unsigned int Value of qctmr_ovf_sts. + */ +static inline unsigned int DCL_QDM_GetQctmrOvfSts(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return qdmx->QDMSTS.BIT.qctmr_ovf_sts; +} + +/** + * @brief Get quadrature direction status. + * @param qdmx QDM register base address. + * @retval unsigned int Value of qdir_sts. + */ +static inline unsigned int DCL_QDM_GetQdirSts(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return qdmx->QDMSTS.BIT.qdir_sts; +} + +/** + * @brief Get the direction error status. + * @param qdmx QDM register base address. + * @retval unsigned int Value of qcdr_err_sts. + */ +static inline unsigned int DCL_QDM_GetQcdrErrSts(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return qdmx->QDMSTS.BIT.qcdr_err_sts; +} + +/** + * @brief Get the position counter active compare value. + * @param qdmx QDM register base address. + * @retval unsigned int Value of qposcmpa. + */ +static inline unsigned int DCL_QDM_GetPositionCompareValue(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return qdmx->QPOSCMPA; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_QDM_IP_H */ diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/qdm/src/qdm.c b/vendor/xinlingyu_92_3061M/Project/drivers/qdm/src/qdm.c new file mode 100644 index 0000000000000000000000000000000000000000..5c0083d4d39d1c9dc33db16858bcb0881589cf4c --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/qdm/src/qdm.c @@ -0,0 +1,550 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file qdm.c + * @author MCU Driver Team. + * @brief QDM HAL level module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the QDM. + * + Initialization and de-initialization functions. + * + Qdm Module Control functions. + * + Speed measure use M function. + * + Stall condition detection. + */ +#include "qdm.h" +#include "interrupt.h" + +#define QDM_INT_MASK 0x38 +/** + * @brief Set Decoder configurations + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void QDM_DecoderConfig(QDM_Handle *qdmHandle) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + QDM_PARAM_CHECK_NO_RET(IsDecodeMode(qdmHandle->ctrlConfig.decoderMode)); + QDM_PARAM_CHECK_NO_RET(IsSwap(qdmHandle->ctrlConfig.swap)); + QDM_PARAM_CHECK_NO_RET(IsResolution(qdmHandle->ctrlConfig.resolution)); + QDM_PARAM_CHECK_NO_RET(IsTrgLockMode(qdmHandle->ctrlConfig.trgLockMode)); + QDM_PARAM_CHECK_NO_RET(IsPtuMode(qdmHandle->ctrlConfig.ptuMode)); + + /* input mode setting */ + qdmHandle->baseAddress->QCTRL.BIT.qdu_mode = qdmHandle->ctrlConfig.decoderMode; + /* swap */ + qdmHandle->baseAddress->QCTRL.BIT.qdm_ab_swap = qdmHandle->ctrlConfig.swap; + /* qdm xclk */ + qdmHandle->baseAddress->QCTRL.BIT.qdu_xclk = qdmHandle->ctrlConfig.resolution; + /* polarity */ + /* bit0: A input polarity, bit value: 0--direct input, 1--invert input */ + qdmHandle->baseAddress->QCTRL.BIT.qdma_polarity = (qdmHandle->ctrlConfig.polarity & 0x01); + /* bit1: B input polarity, bit value: 0--direct input, 1--invert input */ + qdmHandle->baseAddress->QCTRL.BIT.qdmb_polarity = ((qdmHandle->ctrlConfig.polarity >> 1) & 0x01); + /* bit2: index input polarity, bit value: 0--direct input, 1--invert input */ + qdmHandle->baseAddress->QCTRL.BIT.qdmi_polarity = ((qdmHandle->ctrlConfig.polarity >> 2) & 0x01); + /* lock mode */ + qdmHandle->baseAddress->QCTRL.BIT.qtrg_lock_mode = qdmHandle->ctrlConfig.trgLockMode; + /* ptu mode */ + qdmHandle->baseAddress->QCTRL.BIT.ptu_mode = qdmHandle->ctrlConfig.ptuMode; +} + +/** + * @brief Set counter configurations + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void QDM_CounterConfig(QDM_Handle *qdmHandle) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + QDM_PARAM_CHECK_NO_RET(IsPcntMode(qdmHandle->pcntMode)); + QDM_PARAM_CHECK_NO_RET(IsPcntRstMode(qdmHandle->pcntRstMode)); + QDM_PARAM_CHECK_NO_RET(IsPcntIdxInitMode(qdmHandle->pcntIdxInitMode)); + QDM_PARAM_CHECK_NO_RET(IsTsuPrescaler(qdmHandle->tsuPrescaler)); + QDM_PARAM_CHECK_NO_RET(IsCevtPrescaler(qdmHandle->cevtPrescaler)); + + /* set pcnt mode */ + qdmHandle->baseAddress->QPPUCTRL.BIT.pcnt_mode = qdmHandle->pcntMode; + qdmHandle->baseAddress->QPPUCTRL.BIT.pcnt_rst_mode = qdmHandle->pcntRstMode; + qdmHandle->baseAddress->QPPUCTRL.BIT.pcnt_idx_init_mode = qdmHandle->pcntIdxInitMode; + /* set TSU */ + qdmHandle->baseAddress->QTSUCTRL.BIT.tsu_prescaler = qdmHandle->tsuPrescaler; + qdmHandle->baseAddress->QTSUCTRL.BIT.cevt_prescaler = qdmHandle->cevtPrescaler; + /* set init value */ + qdmHandle->baseAddress->QPOSINIT = qdmHandle->posInit; + /* set count max value */ + qdmHandle->baseAddress->QPOSMAX = qdmHandle->posMax; + qdmHandle->baseAddress->QUPRD = qdmHandle->period; + qdmHandle->baseAddress->QCMAX = qdmHandle->qcMax; +} + +/** + * @brief enable submodules + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void QDM_EnableSubmodule(QDM_Handle *qdmHandle) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + if (qdmHandle->subModeEn == true) { + qdmHandle->baseAddress->QCTRL.BIT.ppu_en = BASE_CFG_ENABLE; + qdmHandle->baseAddress->QCTRL.BIT.ptu_en = BASE_CFG_ENABLE; + qdmHandle->baseAddress->QCTRL.BIT.tsu_en = BASE_CFG_ENABLE; + } +} + +/** + * @brief enable interrupt + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void QDM_InterruptEnable(QDM_Handle *qdmHandle) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + qdmHandle->baseAddress->QINTENA.reg = qdmHandle->interruptEn; +} + +/** + * @brief Speed lose interrupt. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void SpeedLose(QDM_Handle *qdmHandle) +{ + if (qdmHandle->userCallBack.SpeedLoseCallback != NULL) { + qdmHandle->userCallBack.SpeedLoseCallback(qdmHandle); + } +} + +/** + * @brief QDM Z index lock interrupt. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void ZIndexLock(QDM_Handle *qdmHandle) +{ + if (qdmHandle->userCallBack.ZIndexLockedCallBack != NULL) { + qdmHandle->userCallBack.ZIndexLockedCallBack(qdmHandle); + } +} + +/** + * @brief Orthogonal direction change interrupt. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void OrthoDirChange(QDM_Handle *qdmHandle) +{ + if (qdmHandle->userCallBack.OrthogonalDirectionChangeCallBack != NULL) { + qdmHandle->userCallBack.OrthogonalDirectionChangeCallBack(qdmHandle); + } +} + +/** + * @brief Orthogonal phase error interrupt. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void OrthoPhaseErr(QDM_Handle *qdmHandle) +{ + if (qdmHandle->userCallBack.OrthogonalPhaseErrorCallBack != NULL) { + qdmHandle->userCallBack.OrthogonalPhaseErrorCallBack(qdmHandle); + } +} + +/** + * @brief Position compare match interrupt. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void PosCompareMatch(QDM_Handle *qdmHandle) +{ + if (qdmHandle->userCallBack.PositionCompareMatchCallBack != NULL) { + qdmHandle->userCallBack.PositionCompareMatchCallBack(qdmHandle); + } +} + +/** + * @brief Position compare ready interrupt. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void PosCompareReady(QDM_Handle *qdmHandle) +{ + if (qdmHandle->userCallBack.PositionCompareReadyCallBack != NULL) { + qdmHandle->userCallBack.PositionCompareReadyCallBack(qdmHandle); + } +} + +/** + * @brief Position counter error interrupt. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void PosCounterErr(QDM_Handle *qdmHandle) +{ + if (qdmHandle->userCallBack.PositionCounterErrorCallBack != NULL) { + qdmHandle->userCallBack.PositionCounterErrorCallBack(qdmHandle); + } +} + +/** + * @brief Position counter overflow interrupt. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void PosCounterOverflow(QDM_Handle *qdmHandle) +{ + if (qdmHandle->userCallBack.PositionCounterOverflowCallBack != NULL) { + qdmHandle->userCallBack.PositionCounterOverflowCallBack(qdmHandle); + } +} + +/** + * @brief Position counter underflow interrupt. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void PosCounterUnderflow(QDM_Handle *qdmHandle) +{ + if (qdmHandle->userCallBack.PositionCounterUnderflowCallBack != NULL) { + qdmHandle->userCallBack.PositionCounterUnderflowCallBack(qdmHandle); + } +} + +/** + * @brief Other interrupt callback function. + * @param qdmHandle Value of @ref QDM_Handle. + * @param qinsts: Interrupt status register. + * @retval None + */ +static void OtherInterruptCallBack(QDM_Handle *qdmHandle, QDM_QINTSTS_REG qinsts) +{ + if (qinsts.BIT.qphs_err_int == BASE_CFG_SET) { + /* Orthogonal phase error interrupt. */ + OrthoPhaseErr(qdmHandle); + qdmHandle->baseAddress->QINTRAW.BIT.qphs_err_raw = BASE_CFG_ENABLE; + } + if (qinsts.BIT.pcnt_cpm_int == BASE_CFG_SET) { + /* Position compare match interrupt. */ + PosCompareMatch(qdmHandle); + qdmHandle->baseAddress->QINTRAW.BIT.pcnt_cpm_raw = BASE_CFG_ENABLE; + } + if (qinsts.BIT.pcnt_cpr_int == BASE_CFG_SET) { + /* Position compare ready interrupt. */ + PosCompareReady(qdmHandle); + qdmHandle->baseAddress->QINTRAW.BIT.pcnt_cpr_raw = BASE_CFG_ENABLE; + } + if (qinsts.BIT.pcnt_err_int == BASE_CFG_SET) { + /* Position counter error interrupt. */ + PosCounterErr(qdmHandle); + qdmHandle->baseAddress->QINTRAW.BIT.pcnt_err_raw = BASE_CFG_ENABLE; + } + if (qinsts.BIT.pcnt_ovf_int == BASE_CFG_SET) { + /* Position counter overflow interrupt. */ + PosCounterOverflow(qdmHandle); + qdmHandle->baseAddress->QINTRAW.BIT.pcnt_ovf_raw = BASE_CFG_ENABLE; + } + if (qinsts.BIT.pcnt_udf_int == BASE_CFG_SET) { + /* Position counter underflow interrupt. */ + PosCounterUnderflow(qdmHandle); + qdmHandle->baseAddress->QINTRAW.BIT.pcnt_udf_raw = BASE_CFG_ENABLE; + } +} + +/** + * @brief M-method speed calculation. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void CalculateSpeed(QDM_Handle *qdmHandle) +{ + unsigned int deltaValue, tmp, intFlag; + /* Last QPOSLOCK value */ + static unsigned int lastPoslockValue = 0; + int speed; + deltaValue = qdmHandle->baseAddress->QPOSLOCK; + /* The position count reset mode is overflow reset. */ + intFlag = (qdmHandle->baseAddress->QINTSTS.reg & QDM_INT_MASK); + if ((qdmHandle->pcntRstMode == QDM_PCNT_RST_OVF) && (intFlag == 0)) { + deltaValue = qdmHandle->baseAddress->QPOSLOCK - lastPoslockValue; + } + lastPoslockValue = qdmHandle->baseAddress->QPOSLOCK; + if (qdmHandle->baseAddress->QDMSTS.BIT.qdir_sts == 1) { /* forward */ + tmp = deltaValue >> qdmHandle->baseAddress->QCTRL.BIT.qdu_xclk; + speed = ((tmp * SECONDS_PER_MINUTES) / qdmHandle->motorLineNum) \ + * (BASE_FUNC_GetCpuFreqHz() / qdmHandle->period); + qdmHandle->speedRpm = speed; + } else { /* reverse */ + tmp = (qdmHandle->posMax - deltaValue) >> qdmHandle->baseAddress->QCTRL.BIT.qdu_xclk; + speed = ((tmp * SECONDS_PER_MINUTES) / qdmHandle->motorLineNum) \ + * (BASE_FUNC_GetCpuFreqHz() / qdmHandle->period); + qdmHandle->speedRpm = -speed; + } +} + +/** + * @brief IRQ Handler + * @param handle: QDM handle. + * @retval None + */ +void HAL_QDM_IrqHandler(void *handle) +{ + QDM_ASSERT_PARAM(handle != NULL); + QDM_Handle *qdmHandle = (QDM_Handle *)handle; + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + + if (qdmHandle->motorLineNum == 0 || qdmHandle->period == 0) { + /* clear interrupt */ + qdmHandle->baseAddress->QINTRAW.BIT.sped_lst_raw = BASE_CFG_ENABLE; + qdmHandle->baseAddress->QINTRAW.BIT.utmr_prd_raw = BASE_CFG_ENABLE; + return; + } + + QDM_QINTSTS_REG qinsts = qdmHandle->baseAddress->QINTSTS; + if (qinsts.BIT.utmr_prd_int == BASE_CFG_SET) { + CalculateSpeed(qdmHandle); + /* PTU timer cycle triggle interrupt */ + if (qdmHandle->userCallBack.PtuCycleTrgCallback != NULL) { + qdmHandle->userCallBack.PtuCycleTrgCallback(qdmHandle); + } + qdmHandle->baseAddress->QINTRAW.BIT.utmr_prd_raw = BASE_CFG_ENABLE; + } + if (qinsts.BIT.sped_lst_int == BASE_CFG_SET) { + /* speed lose interrupt */ + SpeedLose(qdmHandle); + qdmHandle->baseAddress->QINTRAW.BIT.sped_lst_raw = BASE_CFG_ENABLE; + } + if (qinsts.BIT.indx_lck_int == BASE_CFG_SET) { + /* QDM Z index lock interrupt. */ + ZIndexLock(qdmHandle); + qdmHandle->baseAddress->QINTRAW.BIT.indx_lck_raw = BASE_CFG_ENABLE; + } + if (qinsts.BIT.qdir_chg_int == BASE_CFG_SET) { + /* Orthogonal direction change interrupt. */ + OrthoDirChange(qdmHandle); + qdmHandle->baseAddress->QINTRAW.BIT.qdir_chg_raw = BASE_CFG_ENABLE; + } + OtherInterruptCallBack(qdmHandle, qinsts); + return; +} + +/** + * @brief Select the interrupt callback function by the switch-case. + * @param qdmHandle Value of @ref QDM_Handle. + * @param typeId: Interrupt type. + * @param pCallBack: Interrupt callback function. + * @retval None + */ +static void SelectInterruptCallback(QDM_Handle *qdmHandle, QDM_CallbackFuncType typeID, QDM_CallbackType pCallback) +{ + switch (typeID) { + case QDM_TSU_CYCLE: + /* PTU timer cycle triggle interrupt. */ + qdmHandle->userCallBack.PtuCycleTrgCallback = pCallback; + break; + case QDM_SPEED_LOSE: + /* Speed lose interrupt. */ + qdmHandle->userCallBack.SpeedLoseCallback = pCallback; + break; + case QDM_INDEX_LOCKED: + /* QDM Z index lock interrupt. */ + qdmHandle->userCallBack.ZIndexLockedCallBack = pCallback; + break; + case QDM_DIR_CHANGE: + /* Orthogonal direction change interrupt. */ + qdmHandle->userCallBack.OrthogonalDirectionChangeCallBack = pCallback; + break; + case QDM_PHASE_ERROR: + /* Orthogonal phase error interrupt. */ + qdmHandle->userCallBack.OrthogonalPhaseErrorCallBack = pCallback; + break; + case QDM_POS_MATCH: + /* Position compare match interrupt. */ + qdmHandle->userCallBack.PositionCompareMatchCallBack = pCallback; + break; + case QDM_POS_READY: + /* Position compare ready interrupt. */ + qdmHandle->userCallBack.PositionCompareReadyCallBack = pCallback; + break; + case QDM_POS_CNT_ERROR: + /* Position counter error interrupt. */ + qdmHandle->userCallBack.PositionCounterErrorCallBack = pCallback; + break; + case QDM_POS_CNT_OVERFLOW: + /* Position counter overflow interrupt. */ + qdmHandle->userCallBack.PositionCounterOverflowCallBack = pCallback; + break; + case QDM_POS_CNT_UNDERFLOW: + /* Position counter underflow interrupt. */ + qdmHandle->userCallBack.PositionCounterUnderflowCallBack = pCallback; + break; + default: + return; + } +} + +/** + * @brief Register IRQ callback functions + * @param qdmHandle Value of @ref QDM_Handle. + * @param typeID: callback function type ID. + * @param pCallback: pointer of callback function. + * @retval None + */ +void HAL_QDM_RegisterCallback(QDM_Handle *qdmHandle, QDM_CallbackFuncType typeID, QDM_CallbackType pCallback) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(pCallback != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + /* Select the interrupt callback function by the switch-case. */ + SelectInterruptCallback(qdmHandle, typeID, pCallback); +} + +/** + * @brief QDM initialization functions + * @param qdmHandle Value of @ref QDM_Handle. + * @retval BASE_StatusType:BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT + */ +BASE_StatusType HAL_QDM_Init(QDM_Handle *qdmHandle) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + QDM_PARAM_CHECK_WITH_RET(IsEmuMode(qdmHandle->emuMode), BASE_STATUS_ERROR); + QDM_PARAM_CHECK_WITH_RET(IsLockMode(qdmHandle->lock_mode), BASE_STATUS_ERROR); + + qdmHandle->baseAddress->QEMUMODE.BIT.emu_mode = qdmHandle->emuMode; + /* Set Z index locked mode. */ + if ((qdmHandle->interruptEn & QDM_INT_INDEX_EVNT_LATCH) == QDM_INT_INDEX_EVNT_LATCH) { + DCL_QDM_SetIndexLockMode(qdmHandle->baseAddress, qdmHandle->lock_mode); + } + /* Set input filter width. */ + DCL_QDM_SetInputFilterWidth(qdmHandle->baseAddress, qdmHandle->inputFilter.qdmAFilterLevel, \ + qdmHandle->inputFilter.qdmBFilterLevel, qdmHandle->inputFilter.qdmZFilterLevel); + QDM_DecoderConfig(qdmHandle); + QDM_CounterConfig(qdmHandle); + /* Enable interrupt. */ + QDM_InterruptEnable(qdmHandle); + QDM_EnableSubmodule(qdmHandle); + return BASE_STATUS_OK; +} + +/** + * @brief QDM deinitialization functions + * @param qdmHandle Value of @ref QDM_Handle. + * @retval BASE_StatusType:BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT + */ +BASE_StatusType HAL_QDM_DeInit(QDM_Handle *qdmHandle) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + /* Clear QDM interrupt callback functions. */ + qdmHandle->userCallBack.PtuCycleTrgCallback = NULL; + qdmHandle->userCallBack.SpeedLoseCallback = NULL; + + /* Disable interrupt. */ + qdmHandle->baseAddress->QINTENA.reg = BASE_CFG_DISABLE; + /* Disable submodules. */ + qdmHandle->baseAddress->QCTRL.BIT.ppu_en = BASE_CFG_DISABLE; + qdmHandle->baseAddress->QCTRL.BIT.ptu_en = BASE_CFG_DISABLE; + qdmHandle->baseAddress->QCTRL.BIT.tsu_en = BASE_CFG_DISABLE; + return BASE_STATUS_OK; +} + +/** + * @brief read position count register value and direct + * @param qdmHandle Value of @ref QDM_Handle. + * @param count: count value pointer. + * @param dir: dir. + * @retval none. + */ +void HAL_QDM_ReadPosCountAndDir(const QDM_Handle *qdmHandle, unsigned int *count, unsigned int *dir) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(count != NULL); + QDM_ASSERT_PARAM(dir != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + *count = qdmHandle->baseAddress->QPOSCNT; + *dir = qdmHandle->baseAddress->QDMSTS.BIT.qdir_sts; + + return; +} + +/** + * @brief get phase error status. + * @param qdmHandle Value of @ref QDM_Handle. + * @param errStatus: phase error status. + * @retval none. + */ +void HAL_QDM_GetPhaseErrorStatus(const QDM_Handle *qdmHandle, unsigned int *errStatus) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(errStatus != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + *errStatus = qdmHandle->baseAddress->QDMSTS.BIT.qcdr_err_sts; + + return; +} + +/** + * @brief Get motor speed use M method + * @param qdmHandle Value of @ref QDM_Handle. + * @retval int: motor's speed + */ +int HAL_QDM_GetSpeedRpmM(QDM_Handle *qdmHandle) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + return qdmHandle->speedRpm; +} + +/** + * @brief Get motor speed use MT method + * @param qdmHandle Value of @ref QDM_Handle. + * @retval int: motor's speed + */ +int HAL_QDM_GetSpeedRpmMT(QDM_Handle *qdmHandle) +{ + int rpm; + unsigned int utime; + unsigned int tmp; + + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + QDM_ASSERT_PARAM(qdmHandle->motorLineNum != 0); + qdmHandle->baseAddress->QDMSTS.BIT.cevt_sts = BASE_CFG_SET; /* clear cevt status bit */ + while (qdmHandle->baseAddress->QDMSTS.BIT.cevt_sts != BASE_CFG_SET) { + ; + } + if (qdmHandle->baseAddress->QDMSTS.BIT.qctmr_ovf_sts == BASE_CFG_SET) { + qdmHandle->baseAddress->QDMSTS.reg = BASE_CFG_SET; /* clear qctmr overflow status */ + return 0; + } + utime = BASE_FUNC_GetCpuFreqHz() / qdmHandle->motorLineNum; + tmp = utime << qdmHandle->baseAddress->QTSUCTRL.BIT.cevt_prescaler \ + >> qdmHandle->baseAddress->QTSUCTRL.BIT.tsu_prescaler >> qdmHandle->baseAddress->QCTRL.BIT.qdu_xclk; + rpm = tmp * SECONDS_PER_MINUTES / qdmHandle->baseAddress->QCPRD; + + if (qdmHandle->baseAddress->QDMSTS.BIT.qdir_sts == BASE_CFG_SET) { + qdmHandle->speedRpm = rpm; + } else { + qdmHandle->speedRpm = -rpm; + } + + return qdmHandle->speedRpm; +} diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/spi/common/inc/spi.h b/vendor/xinlingyu_92_3061M/Project/drivers/spi/common/inc/spi.h new file mode 100644 index 0000000000000000000000000000000000000000..f6c8ef2f4b2f3cefad30c345f51b1aa4b28b1bd7 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/spi/common/inc/spi.h @@ -0,0 +1,188 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file spi.h + * @author MCU Driver Team + * @brief SPI module driver. + * @details This file provides firmware functions to manage the following. + * functionalities of the SPI. + * + Initialization and de-initialization functions. + * + Peripheral transmit and receiving functions. + * + Enumerated definition of SPI basic parameter configuration. + */ +#ifndef McuMagicTag_SPI_H +#define McuMagicTag_SPI_H + +/* Includes ------------------------------------------------------------------*/ +#include "dma.h" +#include "spi_ip.h" + +/** + * @defgroup SPI SPI + * @brief SPI module. + * @{ + */ + + /** + * @defgroup SPI_Common SPI Common + * @brief SPI common external module. + * @{ + */ + +/* Macro definitions ---------------------------------------------------------*/ + +/* Definition of the chip selection configuration macro */ +#define SPI_CHIP_DESELECT 0 +#define SPI_CHIP_SELECT 1 + +/* Definition of the chip selection mode selection macro */ +#define SPI_CHIP_SELECT_MODE_INTERNAL 0 +#define SPI_CHIP_SELECT_MODE_CALLBACK 1 + +/** + * @defgroup SPI_Handle_Definition SPI Handle Definition + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ +/** + * @brief Callback Function ID Enumeration Definition. + */ +typedef enum { + SPI_TX_COMPLETE_CB_ID = 0x00000000U, + SPI_RX_COMPLETE_CB_ID = 0x00000001U, + SPI_TX_RX_COMPLETE_CB_ID = 0x00000002U, + SPI_ERROR_CB_ID = 0x00000003U, + SPI_CS_CB_ID = 0x00000004U +} HAL_SPI_CallbackID; + +/** + * @brief Module Status Enumeration Definition. + */ +typedef enum { + HAL_SPI_STATE_RESET = 0x00000000U, /**< Peripheral not Initialized */ + HAL_SPI_STATE_READY = 0x00000001U, /**< Peripheral Initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x00000002U, /**< An internal process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x00000003U, /**< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x00000004U, /**< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x00000005U, /**< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x00000006U, /**< SPI error state */ + HAL_SPI_STATE_ABORT = 0x00000007U /**< SPI abort is ongoing */ +} HAL_SPI_State; + +/** + * @brief Module handle structure definition. + */ +typedef struct _SPI_Handle { + SPI_RegStruct *baseAddress; /**< Register base address. */ + + unsigned int mode; /**< See HAL_SPI_Mode. */ + unsigned int csMode; /**< SPI_CHIP_SELECT_MODE_INTERNAL or SPI_CHIP_SELECT_MODE_CALLBACK. */ + unsigned int xFerMode; /**< See HAL_SPI_XferMode. */ + unsigned int clkPolarity; /**< See HAL_SPI_ClkPol. */ + unsigned int clkPhase; /**< See HAL_SPI_ClkPha. */ + unsigned int endian; /**< See HAL_SPI_Endian. */ + unsigned int frameFormat; /**< See HAL_SPI_FrameMode. */ + unsigned int dataWidth; /**< See HAL_SPI_DataWidth. */ + unsigned char freqScr; /**< Frequency scr, value range: 0 to 255. */ + unsigned char freqCpsdvsr; /**< Frequency Cpsdvsr, an even number ranging from 0 to 254. */ + unsigned char waitVal; /**< Number of beats waiting between write and read in National + Microwire frame format. */ + bool waitEn; /**< SPI Microwire waiting enable. */ + unsigned int txIntSize; /**< TX interrupt transmission threshold. */ + unsigned int rxIntSize; /**< RX interrupt transmission threshold. */ + + unsigned int txDMABurstSize; /**< TX DMA transmission threshold. */ + unsigned int rxDMABurstSize; /**< RX DMA transmission threshold. */ + DMA_Handle *dmaHandle; /**< SPI_DMA control handle*/ + unsigned int txDmaCh; /**< SPI DMA tx channel */ + unsigned int rxDmaCh; /**< SPI DMA rx channel */ + + unsigned int csCtrl; /**< Chip select status. */ + unsigned char *rxBuff; /**< Rx buffer pointer address. */ + unsigned char *txBuff; /**< Tx buffer pointer address. */ + unsigned int transferSize; /**< Total length of transmitted data. */ + unsigned int txCount; /**< Tx Length of data transferred. */ + unsigned int rxCount; /**< Rx Length of data transferred. */ + + HAL_SPI_State state; /**< Running Status. */ + BASE_StatusType errorCode; /**< Error Code. */ + SPI_UserCallBack userCallBack; /**< User callback. */ + SPI_ExtendHandle handleEx; /**< SPI extend parameter. */ +} SPI_Handle; +/** + * @} + */ + +/** + * @brief Callback Function Type Definition. + */ +typedef void (* SPI_CallbackFuncType)(void *handle); + +/** + * @defgroup SPI_API_Declaration SPI HAL API + * @{ + */ + +BASE_StatusType HAL_SPI_Init(SPI_Handle *handle); +BASE_StatusType HAL_SPI_Deinit(SPI_Handle *handle); +BASE_StatusType HAL_SPI_ConfigParameter(SPI_Handle *handle); +BASE_StatusType HAL_SPI_RegisterCallback(SPI_Handle *handle, + HAL_SPI_CallbackID callbackID, + SPI_CallbackFuncType pcallback); +BASE_StatusType HAL_SPI_ReadBlocking(SPI_Handle *handle, + unsigned char *rData, + unsigned int dataSize, + unsigned int timeout); +BASE_StatusType HAL_SPI_WriteBlocking(SPI_Handle *handle, + unsigned char *wData, + unsigned int dataSize, + unsigned int timeout); +BASE_StatusType HAL_SPI_WriteReadBlocking(SPI_Handle *handle, + unsigned char *rData, + unsigned char *wData, + unsigned int dataSize, + unsigned int timeout); +BASE_StatusType HAL_SPI_ReadIT(SPI_Handle *handle, unsigned char *rData, unsigned int dataSize); +BASE_StatusType HAL_SPI_WriteIT(SPI_Handle *handle, unsigned char *wData, unsigned int dataSize); +BASE_StatusType HAL_SPI_WriteReadIT(SPI_Handle *handle, + unsigned char *rData, + unsigned char *wData, + unsigned int dataSizeout); +BASE_StatusType HAL_SPI_ReadDMA(SPI_Handle *handle, unsigned char *rData, unsigned int dataSize); +BASE_StatusType HAL_SPI_WriteDMA(SPI_Handle *handle, unsigned char *wData, unsigned int dataSize); +BASE_StatusType HAL_SPI_WriteReadDMA(SPI_Handle *handle, + unsigned char *rData, + unsigned char *wData, + unsigned int dataSizeout); +BASE_StatusType HAL_SPI_DMAStop(SPI_Handle *handle); +BASE_StatusType HAL_SPI_ChipSelectChannelSet(SPI_Handle *handle, SPI_ChipSelectChannel channel); +BASE_StatusType HAL_SPI_ChipSelectChannelGet(SPI_Handle *handle, SPI_ChipSelectChannel *channel); +void HAL_SPI_IrqHandler(void *handle); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* #ifndef McuMagicTag_SPI_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/spi/inc/spi_ex.h b/vendor/xinlingyu_92_3061M/Project/drivers/spi/inc/spi_ex.h new file mode 100644 index 0000000000000000000000000000000000000000..22684be76f3a0fb8d1056b68b39ac08eead983de --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/spi/inc/spi_ex.h @@ -0,0 +1,49 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file spi_ex.h + * @author MCU Driver Team + * @brief SPI module driver. + * @details This file provides firmware functions to manage the following. + * functionalities of the SPI. + * + SPI Set Functions. + */ +#ifndef McuMagicTag_SPI_EX_H +#define McuMagicTag_SPI_EX_H +/* Includes ------------------------------------------------------------------*/ +#include "spi.h" + +/* Macro definitions ---------------------------------------------------------*/ +/** + * @addtogroup SPI_IP + * @{ + */ + +/** + * @defgroup SPI_EX_API_Declaration SPI HAL API EX + * @{ + */ +BASE_StatusType HAL_SPI_SetChipConfigSelectEx(SPI_Handle *handle, HAL_SPI_CHIP_CONFIG mode); +HAL_SPI_CHIP_CONFIG HAL_SPI_GetChipConfigSelectEx(SPI_Handle *handle); +/** + * @} + */ + +/** + * @} + */ +#endif /* #ifndef McuMagicTag_SPI_EX_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/spi/inc/spi_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/spi/inc/spi_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..b51a0a113b50ed717c8107f47a7459570addf51b --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/spi/inc/spi_ip.h @@ -0,0 +1,1237 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file spi_ip.h + * @author MCU Driver Team. + * @brief SPI module driver. + * @details This file provides firmware functions to manage the following. + * functionalities of the SPI. + * + Register definition structure. + * + Direct configuration layer interface. + * + Parameter check inline function. + */ +#ifndef McuMagicTag_SPI_IP_H +#define McuMagicTag_SPI_IP_H + +/* Includes ------------------------------------------------------------------*/ +#include "baseinc.h" +#ifdef SPI_PARAM_CHECK +#define SPI_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define SPI_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define SPI_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define SPI_ASSERT_PARAM(para) ((void)0U) +#define SPI_PARAM_CHECK_NO_RET(para) ((void)0U) +#define SPI_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +/** + * @addtogroup SPI + * @{ + */ + +/** + * @defgroup SPI_IP SPI_IP + * @brief SPI_IP: spi_v1. + * @{ + */ + +#define SPI_CR0_SCR_POS 8 +#define SPI_CR0_SCR_MASK (0xFF << SPI_CR0_SCR_POS) + +/** + * @defgroup SPI_Param_Def SPI Parameters Definition + * @brief Definition of SPI configuration parameters. + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ +/** + * @brief Master and Slave Device Enumeration Definition. + */ +typedef enum { + HAL_SPI_MASTER = 0x00000000U, + HAL_SPI_SLAVE = 0x00000001U +} HAL_SPI_Mode; + +/** + * @brief Clock Polarity Enumeration Definition. + */ +typedef enum { + HAL_SPI_CLKPOL_0 = 0x00000000U, + HAL_SPI_CLKPOL_1 = 0x00000001U +} HAL_SPI_ClkPol; + +/** + * @brief Clock Phase Enumeration Definition. + */ +typedef enum { + HAL_SPI_CLKPHA_0 = 0x00000000U, + HAL_SPI_CLKPHA_1 = 0x00000001U +} HAL_SPI_ClkPha; + +/** + * @brief Enumeration definition of data endian. + */ +typedef enum { + HAL_SPI_BIG_ENDIAN = 0x00000000U, + HAL_SPI_LITTILE_ENDIAN = 0x00000001U +} HAL_SPI_Endian; + +/** + * @brief Enumerated definition of data frame mode selection. + */ +typedef enum { + HAL_SPI_MODE_MOTOROLA = 0x00000000U, + HAL_SPI_MODE_TI = 0x00000001U, + HAL_SPI_MODE_MICROWIRE = 0x00000002U +} HAL_SPI_FrameMode; + +/** + * @brief Transmission Mode Selection Enumeration Definition. + */ +typedef enum { + HAL_XFER_MODE_BLOCKING = 0x00000000U, + HAL_XFER_MODE_INTERRUPTS = 0x00000001U, + HAL_XFER_MODE_DMA = 0x00000002U +} HAL_SPI_XferMode; + +/** + * @brief SPI Chip Select Config Definition. + */ +typedef enum { + HAL_SPI_CHIP_CONFIG_AUTO = 0x00000000U, + HAL_SPI_CHIP_CONFIG_ALTASENS = 0x00000001U, + HAL_SPI_CHIP_CONFIG_SOFR_UNSET = 0x00000002U, + HAL_SPI_CHIP_CONFIG_SOFR_SET = 0x00000003U +} HAL_SPI_CHIP_CONFIG; + +/** + * @brief Data Bit Width Enumeration Definition. + */ +typedef enum { + SPI_DATA_WIDTH_4BIT = 0x00000003U, + SPI_DATA_WIDTH_5BIT = 0x00000004U, + SPI_DATA_WIDTH_6BIT = 0x00000005U, + SPI_DATA_WIDTH_7BIT = 0x00000006U, + SPI_DATA_WIDTH_8BIT = 0x00000007U, + SPI_DATA_WIDTH_9BIT = 0x00000008U, + SPI_DATA_WIDTH_10BIT = 0x00000009U, + SPI_DATA_WIDTH_11BIT = 0x0000000aU, + SPI_DATA_WIDTH_12BIT = 0x0000000bU, + SPI_DATA_WIDTH_13BIT = 0x0000000cU, + SPI_DATA_WIDTH_14BIT = 0x0000000dU, + SPI_DATA_WIDTH_15BIT = 0x0000000eU, + SPI_DATA_WIDTH_16BIT = 0x0000000fU +} HAL_SPI_DataWidth; + +/** + * @brief Definitions of available parameters for interrupt Tx thresholds. + */ +typedef enum { + SPI_TX_INTERRUPT_SIZE_0 = 0x00000000U, + SPI_TX_INTERRUPT_SIZE_1 = 0x00000001U, + SPI_TX_INTERRUPT_SIZE_2 = 0x00000002U, + SPI_TX_INTERRUPT_SIZE_3 = 0x00000003U, + SPI_TX_INTERRUPT_SIZE_4 = 0x00000004U, + SPI_TX_INTERRUPT_SIZE_5 = 0x00000005U, + SPI_TX_INTERRUPT_SIZE_6 = 0x00000006U, + SPI_TX_INTERRUPT_SIZE_7 = 0x00000007U, + SPI_TX_INTERRUPT_SIZE_8 = 0x00000008U, + SPI_TX_INTERRUPT_SIZE_9 = 0x00000009U, + SPI_TX_INTERRUPT_SIZE_10 = 0x0000000AU, + SPI_TX_INTERRUPT_SIZE_11 = 0x0000000BU, + SPI_TX_INTERRUPT_SIZE_12 = 0x0000000CU, + SPI_TX_INTERRUPT_SIZE_13 = 0x0000000DU, + SPI_TX_INTERRUPT_SIZE_14 = 0x0000000EU, + SPI_TX_INTERRUPT_SIZE_15 = 0x0000000FU +} HAL_SPI_TxInterruptSize; + +/** + * @brief Definitions of available parameters for interrupt Rx thresholds. + */ +typedef enum { + SPI_RX_INTERRUPT_SIZE_0 = 0x00000000U, + SPI_RX_INTERRUPT_SIZE_1 = 0x00000001U, + SPI_RX_INTERRUPT_SIZE_2 = 0x00000002U, + SPI_RX_INTERRUPT_SIZE_3 = 0x00000003U, + SPI_RX_INTERRUPT_SIZE_4 = 0x00000004U, + SPI_RX_INTERRUPT_SIZE_5 = 0x00000005U, + SPI_RX_INTERRUPT_SIZE_6 = 0x00000006U, + SPI_RX_INTERRUPT_SIZE_7 = 0x00000007U, + SPI_RX_INTERRUPT_SIZE_8 = 0x00000008U, + SPI_RX_INTERRUPT_SIZE_9 = 0x00000009U, + SPI_RX_INTERRUPT_SIZE_10 = 0x0000000AU, + SPI_RX_INTERRUPT_SIZE_11 = 0x0000000BU, + SPI_RX_INTERRUPT_SIZE_12 = 0x0000000CU, + SPI_RX_INTERRUPT_SIZE_13 = 0x0000000DU, + SPI_RX_INTERRUPT_SIZE_14 = 0x0000000EU, + SPI_RX_INTERRUPT_SIZE_15 = 0x0000000FU, +} HAL_SPI_RxInterruptSize; + +/** + * @brief Definitions of available parameters for DMA Tx thresholds. + */ +typedef enum { + SPI_TX_DMA_BURST_SIZE_0 = 0x00000000U, + SPI_TX_DMA_BURST_SIZE_1 = 0x00000001U, + SPI_TX_DMA_BURST_SIZE_2 = 0x00000002U, + SPI_TX_DMA_BURST_SIZE_3 = 0x00000003U, + SPI_TX_DMA_BURST_SIZE_4 = 0x00000004U, + SPI_TX_DMA_BURST_SIZE_5 = 0x00000005U, + SPI_TX_DMA_BURST_SIZE_6 = 0x00000006U, + SPI_TX_DMA_BURST_SIZE_7 = 0x00000007U, + SPI_TX_DMA_BURST_SIZE_8 = 0x00000008U, + SPI_TX_DMA_BURST_SIZE_9 = 0x00000009U, + SPI_TX_DMA_BURST_SIZE_10 = 0x0000000AU, + SPI_TX_DMA_BURST_SIZE_11 = 0x0000000BU, + SPI_TX_DMA_BURST_SIZE_12 = 0x0000000CU, + SPI_TX_DMA_BURST_SIZE_13 = 0x0000000DU, + SPI_TX_DMA_BURST_SIZE_14 = 0x0000000EU, + SPI_TX_DMA_BURST_SIZE_15 = 0x0000000FU, +} HAL_SPI_TxDmaBurstSize; + +/** + * @brief Definitions of available parameters for DMA Rx thresholds. + */ +typedef enum { + SPI_RX_DMA_BURST_SIZE_0 = 0x00000000U, + SPI_RX_DMA_BURST_SIZE_1 = 0x00000001U, + SPI_RX_DMA_BURST_SIZE_2 = 0x00000002U, + SPI_RX_DMA_BURST_SIZE_3 = 0x00000003U, + SPI_RX_DMA_BURST_SIZE_4 = 0x00000004U, + SPI_RX_DMA_BURST_SIZE_5 = 0x00000005U, + SPI_RX_DMA_BURST_SIZE_6 = 0x00000006U, + SPI_RX_DMA_BURST_SIZE_7 = 0x00000007U, + SPI_RX_DMA_BURST_SIZE_8 = 0x00000008U, + SPI_RX_DMA_BURST_SIZE_9 = 0x00000009U, + SPI_RX_DMA_BURST_SIZE_10 = 0x0000000AU, + SPI_RX_DMA_BURST_SIZE_11 = 0x0000000BU, + SPI_RX_DMA_BURST_SIZE_12 = 0x0000000CU, + SPI_RX_DMA_BURST_SIZE_13 = 0x0000000DU, + SPI_RX_DMA_BURST_SIZE_14 = 0x0000000EU, + SPI_RX_DMA_BURST_SIZE_15 = 0x0000000FU, +} HAL_SPI_RxDmaBurstSize; + +/** + * @brief Defines the SPI chip select channel. + */ +typedef enum { + SPI_CHIP_SELECT_CHANNEL_0 = 0x00000000U, + SPI_CHIP_SELECT_CHANNEL_1 = 0x00000001U, + SPI_CHIP_SELECT_CHANNEL_2 = 0x00000002U, + SPI_CHIP_SELECT_CHANNEL_3 = 0x00000003U, + SPI_CHIP_SELECT_CHANNEL_MAX = 0x00000004U +} SPI_ChipSelectChannel; + +/** + * @brief SPI extend handle. + */ +typedef struct _SPI_ExtendHandle { +} SPI_ExtendHandle; + +/** + * @brief SPI user callback. + */ +typedef struct { + /* Sending completion callback function */ + void (* TxCpltCallback)(void *handle); + /* Receive completion callback function */ + void (* RxCpltCallback)(void *handle); + /* Receive and Sending completion callback function */ + void (* TxRxCpltCallback)(void *handle); + /* Error callback function */ + void (* ErrorCallback)(void *handle); + /* CS callback function */ + void (* CsCtrlCallback)(void *handle); +} SPI_UserCallBack; +/** + * @} + */ + +/** + * @defgroup SPI_Reg_Def SPI Register Definition + * @brief register mapping structure + * @{ + */ +/* Register Description Definition----------------------------------- */ + +/** + * @brief SPI clock, polarity, phase, frame format, data bit control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int dss : 4; /**< data width. */ + unsigned int frf : 2; /**< frame format: Motorola TI Mircowire. */ + unsigned int spo : 1; /**< motorola polarity. */ + unsigned int sph : 1; /**< motorola phase. */ + unsigned int scr : 8; /**< serial clock rate. */ + unsigned int reserved0 : 16; + } BIT; +} volatile SPICR0_REG; + +/** + * @brief SPI parameter control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int lbm : 1; /**< loopback mode enable. */ + unsigned int sse : 1; /**< SPI enable. */ + unsigned int ms : 1; /**< Master or Salve mode. */ + unsigned int reserved0 : 1; + unsigned int bitend : 1; /**< set the endian mode. */ + unsigned int reserved1 : 3; + unsigned int waitval : 7; /**< Microwire wait time. */ + unsigned int waiten : 1; /**< Microwire wait enable. */ + unsigned int reserved2 : 16; + } BIT; +} volatile SPICR1_REG; + +/** + * @brief SPI data FIFO register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int data : 16; /**< send and receive FIFO. */ + unsigned int reserved0 : 16; + } BIT; +} volatile SPIDR_REG; + +/** + * @brief SPI status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int tfe : 1; /**< tx FIFO empty flag. */ + unsigned int tnf : 1; /**< tx FIFO not full flag. */ + unsigned int rne : 1; /**< rx FIFO not empty flag. */ + unsigned int rff : 1; /**< rx FIFO full flag. */ + unsigned int bsy : 1; /**< SPI busy flag. */ + unsigned int reserved0 : 27; + } BIT; +} volatile SPISR_REG; + +/** + * @brief SPI clock divider register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cpsdvsr : 8; /**< clock divider value, value is even number between 2 and 254. */ + unsigned int reserved0 : 24; + } BIT; +} volatile SPICPSR_REG; + +/** + * @brief SPI interrupt mask control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rorim : 1; /**< rx overflow interrupt mask. */ + unsigned int rtim : 1; /**< rx timeout interrupt mask. */ + unsigned int rxim : 1; /**< rx FIFO interrupt mask. */ + unsigned int txim : 1; /**< tx FIFO interrupt mask. */ + unsigned int reserved0 : 28; + } BIT; +} volatile SPIIMSC_REG; + +/** + * @brief SPI raw interrupt status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rorris : 1; /**< raw status of the rx overflow interrupt. */ + unsigned int rtris : 1; /**< raw status of the rx timeout interrupt. */ + unsigned int rxris : 1; /**< raw status of the rx FIFO interrupt. */ + unsigned int txris : 1; /**< raw status of the tx FIFO interrupt. */ + unsigned int reserved0 : 28; + } BIT; +} volatile SPIRIS_REG; + +/** + * @brief SPI masked interrupt status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rormis : 1; /**< masked status of the rx overflow interrupt. */ + unsigned int rtmis : 1; /**< masked status of the rx timeout interrupt. */ + unsigned int rxmis : 1; /**< masked status of the rx FIFO interrupt. */ + unsigned int txmis : 1; /**< masked status of the tx FIFO interrupt. */ + unsigned int reserved0 : 28; + } BIT; +} volatile SPIMIS_REG; + +/** + * @brief SPI interrupt clear register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int roric : 1; /**< clear the rx overflow interrupt. */ + unsigned int rtic : 1; /**< clear the rx timeout interrupt. */ + unsigned int reserved0 : 30; + } BIT; +} volatile SPIICR_REG; + +/** + * @brief SPI DMA control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rxdmae : 1; /**< DMA rx FIFO enable. */ + unsigned int txdmae : 1; /**< DMA tx FIFO enable. */ + unsigned int rxdmalsreqe : 1; /**< DMA rx FIFO SPI flow control. */ + unsigned int reserved0 : 29; + } BIT; +} volatile SPIDMACR_REG; + +/** + * @brief SPI tx FIFO control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int txintsize : 4; /**< set the threshold of the tx FIFO request interrupt. */ + unsigned int reserved0 : 28; + } BIT; +} volatile SPITXFIFOCR_REG; + +/** + * @brief SPI rx FIFO control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rxintsize : 4; /**< set the threshold of the rx FIFO request interrupt. */ + unsigned int reserved0 : 28; + } BIT; +} volatile SPIRXFIFOCR_REG; + + +/** + * @brief SPI cs mode control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int spi_csn_sel : 2; /**< chip select. */ + unsigned int reserved0 : 2; + unsigned int spi_csn_mode : 2; /**< chip select mode. */ + unsigned int reserved1 : 26; + } BIT; +} volatile SPICSNCR_REG; + +/** + * @brief SPI Register definition structure + */ +typedef struct { + SPICR0_REG SPICR0; /**< SPI parameter control register 0. */ + SPICR1_REG SPICR1; /**< SPI parameter control register 1. */ + SPIDR_REG SPIDR; /**< SPI data FIFO register. */ + SPISR_REG SPISR; /**< SPI status register. */ + SPICPSR_REG SPICPSR; /**< SPI clock divider register. */ + SPIIMSC_REG SPIIMSC; /**< SPI interrupt mask control register. */ + SPIRIS_REG SPIRIS; /**< SPI raw interrupt status register. */ + SPIMIS_REG SPIMIS; /**< SPI masked interrupt status register. */ + SPIICR_REG SPIICR; /**< SPI interrupt clear register. */ + SPIDMACR_REG SPIDMACR; /**< SPI DMA control register. */ + SPITXFIFOCR_REG SPITXFIFOCR; /**< SPI tx FIFO control register. */ + SPIRXFIFOCR_REG SPIRXFIFOCR; /**< SPI rx FIFO control register. */ + SPICSNCR_REG SPICSNCR; /**< SPI cs mode control register. */ +} volatile SPI_RegStruct; +/** + * @} + */ + +/** + * @brief Check whether the SPI mode is used. + * @param mode Spi mode + * @retval true + * @retval false + */ +static inline bool IsSpiMode(unsigned int mode) +{ + if (mode == HAL_SPI_MASTER || mode == HAL_SPI_SLAVE) { + return true; + } + return false; +} + +/** + * @brief Check if the transfer mode specified for the SPI. + * @param xFermode Transfer mode. + * @retval true + * @retval false + */ +static inline bool IsSpiXferMode(unsigned int xFermode) +{ + if (xFermode == HAL_XFER_MODE_BLOCKING || + xFermode == HAL_XFER_MODE_INTERRUPTS || + xFermode == HAL_XFER_MODE_DMA) { + return true; + } + return false; +} + +/** + * @brief Checking SPI Polarity Parameters. + * @param clkPolarity Polarity Parameters. + * @retval true + * @retval false + */ +static inline bool IsSpiClkPolarity(unsigned int clkPolarity) +{ + if (clkPolarity == HAL_SPI_CLKPOL_0 || + clkPolarity == HAL_SPI_CLKPOL_1) { + return true; + } + return false; +} + +/** + * @brief Checking SPI Phase Parameters. + * @param clkPhase Phase Parameters. + * @retval true + * @retval false + */ +static inline bool IsSpiClkPhase(unsigned int clkPhase) +{ + if (clkPhase == HAL_SPI_CLKPHA_0 || + clkPhase == HAL_SPI_CLKPHA_1) { + return true; + } + return false; +} + +/** + * @brief Check the SPI big-endian configuration parameters. + * @param endian Big-endian configuration parameters. + * @retval true + * @retval false + */ +static inline bool IsSpiEndian(unsigned int endian) +{ + if (endian == HAL_SPI_BIG_ENDIAN || + endian == HAL_SPI_LITTILE_ENDIAN) { + return true; + } + return false; +} + +/** + * @brief Check the SPI frame format configuration. + * @param framFormat Frame format. + * @retval true + * @retval false + */ +static inline bool IsSpiFrameFormat(unsigned int framFormat) +{ + if (framFormat == HAL_SPI_MODE_MOTOROLA || + framFormat == HAL_SPI_MODE_TI || + framFormat == HAL_SPI_MODE_MICROWIRE) { + return true; + } + return false; +} + +/** + * @brief Checking the SPI Data Bit Width Configuration. + * @param dataWidth Data Bit Width. + * @retval true + * @retval false + */ +static inline bool IsSpiDataWidth(unsigned int dataWidth) +{ + if (dataWidth >= SPI_DATA_WIDTH_4BIT && dataWidth <= SPI_DATA_WIDTH_16BIT) { + return true; + } + return false; +} + +/** + * @brief Check the configuration of the waiting time between the TX and RX in the SPI microwire frame format. + * @param waitVal Waiting time. + * @retval true + * @retval false + */ +static inline bool IsSpiWaitVal(unsigned char waitVal) +{ + /* waitval value is 0 to 0x7f */ + if (waitVal <= 0x7f) { + return true; + } + return false; +} + +/** + * @brief Check the SPI interrupt TX threshold configuration. + * @param txIntSize TX threshold configuration. + * @retval true + * @retval false + */ +static inline bool IsSpiTxIntSize(unsigned int txIntSize) +{ + if (txIntSize <= SPI_TX_INTERRUPT_SIZE_15) { + return true; + } + return false; +} + +/** + * @brief Check the SPI interrupt RX threshold configuration. + * @param rxIntSize RX threshold configuration. + * @retval true + * @retval false + */ +static inline bool IsSpiRxIntSize(unsigned int rxIntSize) +{ + if (rxIntSize <= SPI_RX_INTERRUPT_SIZE_15) { + return true; + } + return false; +} + +/** + * @brief Check the SPI DMA TX threshold configuration. + * @param txDMABurstSize TX threshold. + * @retval true + * @retval false + */ +static inline bool IsSpiTxDmaBurstSize(unsigned int txDMABurstSize) +{ + if (txDMABurstSize <= SPI_TX_DMA_BURST_SIZE_15) { + return true; + } + return false; +} + +/** + * @brief Check the SPI DMA RX threshold configuration. + * @param rxDMABurstSize RX threshold. + * @retval true + * @retval false + */ +static inline bool IsSpiRxDmaBurstSize(unsigned int rxDMABurstSize) +{ + if (rxDMABurstSize <= SPI_RX_DMA_BURST_SIZE_15) { + return true; + } + return false; +} + +/** + * @brief Checking SPI frequency divider parameters. + * @param freqCpsdvsr Frequency division parameters to be checked. + * @retval true + * @retval false + */ +static inline bool IsSpiFreqCpsdvsr(unsigned char freqCpsdvsr) +{ + /* FreqCpsdvsr value is 0 to 255 */ + if (freqCpsdvsr >= 2) { + return true; + } + return false; +} + +/** + * @brief Setting SPI Chip Config Mode + * @param mode Spi Chip Config Mode + * @retval true + * @retval false + */ +static inline bool IsSpiChipConfigMode(unsigned int mode) +{ + if (mode <= HAL_SPI_CHIP_CONFIG_SOFR_SET) { + return true; + } + return false; +} + +/** + * @brief Setting SPI Chip Select Channel + * @param csn Spi Chip Select + * @retval true + * @retval false + */ +static inline bool IsSpiChipSelectChannel(unsigned int csn) +{ + if (csn < SPI_CHIP_SELECT_CHANNEL_MAX) { + return true; + } + return false; +} + +/* Direct configuration layer interface----------------------------------*/ +/** + * @brief SPI module enable. + * @param spix SPI register base address. + * @param spiEnable SPI enable or disable. + * @retval None. + */ +static inline void DCL_SPI_SetSpiEnable(SPI_RegStruct *spix, bool spiEnable) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPICR1.BIT.sse = spiEnable; +} + +/** + * @brief Get SPI enable status. + * @param spix SPI register base address. + * @retval bool SPI enable or disable. + */ +static inline bool DCL_SPI_GetSpiEnable(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR1.BIT.sse; +} + +/** + * @brief Set SPI loopback. + * @param spix SPI register base address. + * @param loop enable or disable + * @retval None. + */ +static inline void DCL_SPI_SetLoopBack(SPI_RegStruct *spix, bool loop) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPICR1.BIT.lbm = loop; +} + +/** + * @brief Get SPI loopback. + * @param spix SPI register base address. + * @retval bool loopback is enable or disable. + */ +static inline bool DCL_SPI_GetLoopBack(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR1.BIT.lbm; +} + +/** + * @brief Configuring SPI polarity + * @param spix SPI register base address. + * @param clkPolarity SPI Polarity,the value is 0 or 1. + * @retval None. + */ +static inline void DCL_SPI_SetClkPolarity(SPI_RegStruct *spix, unsigned int clkPolarity) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + SPI_PARAM_CHECK_NO_RET(IsSpiClkPolarity(clkPolarity)); + spix->SPICR0.BIT.spo = clkPolarity; +} + +/** + * @brief Get SPI polarity. + * @param spix SPI register base address. + * @retval SPI Polarity,the value is 0 or 1. + */ +static inline unsigned char DCL_SPI_GetClkPolarity(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR0.BIT.spo; +} + +/** + * @brief Configuring SPI phase. + * @param spix SPI register base address. + * @param clkPhase SPI phase,the value is 0 or 1. + * @retval None. + */ +static inline void DCL_SPI_SetClkPhase(SPI_RegStruct *spix, unsigned int clkPhase) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + SPI_PARAM_CHECK_NO_RET(IsSpiClkPhase(clkPhase)); + spix->SPICR0.BIT.sph = clkPhase; +} + +/** + * @brief Get SPI phase. + * @param spix SPI register base address. + * @retval SPI phase,the value is 0 or 1. + */ +static inline unsigned char DCL_SPI_GetClkPhase(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR0.BIT.sph; +} + +/** + * @brief SPI data big endian configuration. + * @param spix SPI register base address. + * @param bitEnd Big-endian configuration parameter. The value can be 0 or 1. + * @retval None. + */ +static inline void DCL_SPI_SetBitEnd(SPI_RegStruct *spix, unsigned int bitEnd) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + SPI_PARAM_CHECK_NO_RET(IsSpiEndian(bitEnd)); + spix->SPICR1.BIT.bitend = bitEnd; +} + +/** + * @brief Get SPI data big endian configuration. + * @param spix SPI register base address. + * @retval Big-endian configuration parameter. The value is 0 or 1. + */ +static inline unsigned char DCL_SPI_GetBitEnd(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR1.BIT.bitend; +} + +/** + * @brief SPI frame format configuration. + * @param spix SPI register base address. + * @param frameFormat Value: Motorola: 00, TI synchronous serial: 01, National Microwire: 10. + * @retval None. + */ +static inline void DCL_SPI_SetFrameFormat(SPI_RegStruct *spix, unsigned int frameFormat) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + SPI_PARAM_CHECK_NO_RET(IsSpiFrameFormat(frameFormat)); + spix->SPICR0.BIT.frf = frameFormat; +} + +/** + * @brief Get SPI frame format configuration. + * @param spix SPI register base address. + * @retval Motorola: 00, TI synchronous serial: 01, National Microwire: 10. + */ +static inline unsigned char DCL_SPI_GetFrameFormat(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR0.BIT.frf; +} + +/** + * @brief Configuring the SPI data bit width. + * @param spix SPI register base address. + * @param dataWidth The data bit width can be set to 4 to 16 bits. + * @retval None. + */ +static inline void DCL_SPI_SetDataWidth(SPI_RegStruct *spix, unsigned int dataWidth) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + SPI_PARAM_CHECK_NO_RET(IsSpiDataWidth(dataWidth)); + spix->SPICR0.BIT.dss = dataWidth; +} + +/** + * @brief Get the SPI data bit width configuring. + * @param spix SPI register base address. + * @retval SPI Data Bit Width configuring. + */ +static inline unsigned char DCL_SPI_GetDataWidth(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR0.BIT.dss; +} + +/** + * @brief SPI serial clock rate configuration. + * @param spix SPI register base address. + * @param freqScr Value range: 0 to 255. + * @retval None. + */ +static inline void DCL_SPI_SetFreqScr(SPI_RegStruct *spix, unsigned char freqScr) +{ + unsigned int cr0Reg; + unsigned int temp; + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + /* Read the entire register and write it back. */ + temp = ((unsigned int)freqScr) << SPI_CR0_SCR_POS; + cr0Reg = (spix->SPICR0.reg & (~SPI_CR0_SCR_MASK)) | temp; + spix->SPICR0.reg = cr0Reg; +} + +/** + * @brief Get SPI serial clock rate configuration. + * @param spix SPI register base address. + * @retval Value range: 0 to 255. + */ +static inline unsigned char DCL_SPI_GetFreqScr(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return ((spix->SPICR0.reg >> SPI_CR0_SCR_POS) & 0xFF); /* Minimum 8-bit mask 0xFF */ +} + +/** + * @brief SPI clock divider setting. + * @param spix SPI register base address. + * @param freqCpsdvsr The value must be an even number between 2 and 255. + * @retval None. + */ +static inline void DCL_SPI_SetFreqCpsdvsr(SPI_RegStruct *spix, unsigned char freqCpsdvsr) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + SPI_PARAM_CHECK_NO_RET(IsSpiFreqCpsdvsr(freqCpsdvsr)); + spix->SPICPSR.BIT.cpsdvsr = freqCpsdvsr; +} + +/** + * @brief Get SPI clock divider setting. + * @param spix SPI register base address. + * @retval The value is an even number between 2 and 255. + */ +static inline unsigned char DCL_SPI_GetFreqCpsdvsr(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICPSR.BIT.cpsdvsr; +} + +/** + * @brief Configuring the SPI TX threshold. + * @param spix SPI register base address. + * @param txIntSize The value can be 0-15. For details, see the register manual. + * @retval None. + */ +static inline void DCL_SPI_SetTxIntSize(SPI_RegStruct *spix, unsigned int txIntSize) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + SPI_PARAM_CHECK_NO_RET(IsSpiTxIntSize(txIntSize)); + spix->SPITXFIFOCR.BIT.txintsize = txIntSize; +} + +/** + * @brief Get the SPI TX threshold configuring. + * @param spix SPI register base address. + * @retval The value is 0-15. For details, see the register manual. + */ +static inline unsigned char DCL_SPI_GetTxIntSize(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPITXFIFOCR.BIT.txintsize; +} + +/** + * @brief Configuring the SPI RX threshold. + * @param spix SPI register base address. + * @param rxIntSize The value can be 0-15. For details, see the register manual. + * @retval None. + */ +static inline void DCL_SPI_SetRxIntSize(SPI_RegStruct *spix, unsigned int rxIntSize) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + SPI_PARAM_CHECK_NO_RET(IsSpiRxIntSize(rxIntSize)); + spix->SPIRXFIFOCR.BIT.rxintsize = rxIntSize; +} + +/** + * @brief Get the SPI RX threshold configuring. + * @param spix SPI register base address. + * @retval The value is 0-15. For details, see the register manual. + */ +static inline unsigned char DCL_SPI_GetRxIntSize(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPIRXFIFOCR.BIT.rxintsize; +} + +/** + * @brief Configuring the CS Channel. + * @param spix SPI register base address. + * @param channel SPI chip select channel. + * @retval None. + */ +static inline void DCL_SPI_SetChipSelect(SPI_RegStruct *spix, unsigned int channel) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + SPI_PARAM_CHECK_NO_RET(IsSpiChipSelectChannel(channel)); + spix->SPICSNCR.BIT.spi_csn_sel = channel; +} + +/** + * @brief Obtains the channel of the current CS. + * @param spix SPI register base address. + * @retval SPI_ChipSelectChannel. + */ +static inline unsigned char DCL_SPI_GetChipSelect(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICSNCR.BIT.spi_csn_sel; +} + +/** + * @brief SPI CHIP CONFIG SET. + * @param spix SPI register base address. + * @param mode The value can be 0-4. For details, see the register manual. + * @retval None. + */ +static inline void DCL_SPI_SetChipConfigSelect(SPI_RegStruct *spix, HAL_SPI_CHIP_CONFIG mode) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + SPI_PARAM_CHECK_NO_RET(IsSpiChipConfigMode(mode)); + spix->SPICSNCR.BIT.spi_csn_mode = mode; +} + +/** + * @brief SPI CHIP CONFIG GET. + * @param spix SPI register base address. + * @retval HAL_SPI_CHIP_CONFIG. + */ +static inline HAL_SPI_CHIP_CONFIG DCL_SPI_GetChipConfigSelect(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICSNCR.BIT.spi_csn_mode; +} + +/** + * @brief Setting the Master/Slave Mode. + * @param spix SPI register base address. + * @param mode @ref HAL_SPI_Mode. + * @retval None. + */ +static inline void DCL_SPI_SetMasterSlaveMode(SPI_RegStruct *spix, HAL_SPI_Mode mode) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + SPI_PARAM_CHECK_NO_RET(IsSpiMode(mode)); + spix->SPICR1.BIT.ms = mode; +} + +/** + * @brief Getting the Master/Slave Mode. + * @param spix SPI register base address. + * @retval HAL_SPI_Mode master or slave. + */ +static inline HAL_SPI_Mode DCL_SPI_GetMasterSlaveMode(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR1.BIT.ms; +} + +/** + * @brief Set microwire waitval. + * @param spix SPI register base address. + * @param value is microwire wait beats. + * @retval None. + */ +static inline void DCL_SPI_SetMircoWaitVal(SPI_RegStruct *spix, unsigned char value) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + SPI_PARAM_CHECK_NO_RET(IsSpiWaitVal(value)); + spix->SPICR1.BIT.waitval = value; +} + +/** + * @brief Get microwire waitval. + * @param spix SPI register base address. + * @retval unsigned char, For details, see the register manual + */ +static inline unsigned char DCL_SPI_GetMircoWaitVal(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR1.BIT.waitval; +} + +/** + * @brief Set microwire wait enable or disable. + * @param spix SPI register base address. + * @param waitEn is microwire wait enable or disable. + * @retval None. + */ +static inline void DCL_SPI_SetMircoWaitEn(SPI_RegStruct *spix, bool waitEn) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPICR1.BIT.waiten = waitEn; +} + +/** + * @brief Get microwire wait enable or disable. + * @param spix SPI register base address. + * @retval bool is microwire wait enable or disable + */ +static inline bool DCL_SPI_GetMircoWaitEn(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR1.BIT.waiten; +} + +/** + * @brief Put the data into the TX FIFO. + * @param spix SPI register base address. + * @param data is input data. + * @retval None. + */ +static inline void DCL_SPI_SetData(SPI_RegStruct *spix, unsigned short data) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPIDR.reg = data; +} + +/** + * @brief Get data from the RX FIFO. + * @param spix SPI register base address. + * @retval unsigned short data from the RX FIFO. + */ +static inline unsigned short DCL_SPI_GetData(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPIDR.reg; +} + +/** + * @brief Get whether the TX FIFO is empty. + * @param spix SPI register base address. + * @retval bool TX FIFO is not empty or is empty. + */ +static inline bool DCL_SPI_GetTxFifoEmpty(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPISR.BIT.tfe; +} + +/** + * @brief Get whether the TX FIFO is full. + * @param spix SPI register base address. + * @retval bool TX FIFO is not full or is full. + */ +static inline bool DCL_SPI_GetTxFifoFull(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPISR.BIT.tnf; +} + +/** + * @brief Get whether the RX FIFO is empty. + * @param spix SPI register base address. + * @retval bool RX FIFO is not empty or is empty. + */ +static inline bool DCL_SPI_GetRxFifoEmpty(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPISR.BIT.rne; +} + +/** + * @brief Get whether the RX FIFO is full. + * @param spix SPI register base address. + * @retval bool RX FIFO is not full or is full. + */ +static inline bool DCL_SPI_GetRxFifoFull(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPISR.BIT.rff; +} + +/** + * @brief Get Whether the SPI is busy. + * @param spix SPI register base address. + * @retval bool SPI is busy or not busy. + */ +static inline bool DCL_SPI_GetBusyFlag(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPISR.BIT.bsy; +} + +/** + * @brief Set the interrupt mask. + * @param spix SPI register base address. + * @param intMask For details, see the register manual. + * @retval None. + */ +static inline void DCL_SPI_SetIntMask(SPI_RegStruct *spix, unsigned int intMask) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPIIMSC.reg = intMask; +} + +/** + * @brief Get the interrupt mask. + * @param spix SPI register base address. + * @retval unsigned int interrupt mask. + */ +static inline unsigned int DCL_SPI_GetIntMask(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPIIMSC.reg; +} + +/** + * @brief Get SPIMIS register all mask interrupt status. + * @param spix SPI register base address. + * @retval unsigned short SPIMIS register interrupt mask. + */ +static inline unsigned int DCL_SPI_GetMisInt(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPIMIS.reg; +} + +/** + * @brief Clear RX timeout interrupt + * @param spix SPI register base address. + * @retval None. + */ +static inline void DCL_SPI_ClearRxTimeInt(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPIICR.BIT.roric = BASE_CFG_SET; +} + +/** + * @brief Clear RX overflow interrupt + * @param spix SPI register base address. + * @retval None. + */ +static inline void DCL_SPI_ClearRxOverInt(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPIICR.BIT.rtic = BASE_CFG_SET; +} + +/** + * @brief Set DMA FIFO enable register. + * @param spix SPI register base address. + * @param dmaCtl control DMA FIFO enable. + * @retval None. + */ +static inline void DCL_SPI_SetDmaTxFifo(SPI_RegStruct *spix, unsigned int dmaCtl) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPIDMACR.reg = dmaCtl; +} + +/** + * @brief Get DMA FIFO enable register status. + * @param spix SPI register base address. + * @retval unsigned int DMA Control Register Status. + */ +static inline unsigned int DCL_SPI_GetDmaTxFifo(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPIDMACR.reg; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* #ifndef McuMagicTag_SPI_IP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/spi/src/spi.c b/vendor/xinlingyu_92_3061M/Project/drivers/spi/src/spi.c new file mode 100644 index 0000000000000000000000000000000000000000..59a37f14a4ff0a995cbc355a71eee4e299a0d0d2 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/spi/src/spi.c @@ -0,0 +1,1171 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file spi.c + * @author MCU Driver Team + * @brief SPI module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the SPI. + * + Initialization and de-initialization functions + * + Peripheral Control functions + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "systick.h" +#include "spi.h" +/* Macro definitions ---------------------------------------------------------*/ +#define SPI_WAIT_TIMEOUT 0x400 + +#define SPI_DATA_WIDTH_SHIFT_8BIT 1 +#define SPI_DATA_WIDTH_SHIFT_16BIT 2 +#define SPI_WRITE_FIFO_SIZE 2 + +#define SPI_INTERRUPT_SET_ALL 0xF +#define SPI_DMA_FIFO_ENABLE 0x3 + +#define SPI_TICK_MS_DIV 1000 +/** + * @brief Check all initial configuration parameters. + * @param handle SPI handle. + * @retval BASE status type: OK, ERROR. + */ +static BASE_StatusType CheckAllInitParameters(SPI_Handle *handle) +{ + SPI_PARAM_CHECK_WITH_RET(IsSpiMode(handle->mode), BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(IsSpiXferMode(handle->xFerMode), BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(IsSpiEndian(handle->endian), BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(IsSpiFrameFormat(handle->frameFormat), BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(IsSpiDataWidth(handle->dataWidth), BASE_STATUS_ERROR); + /* Check spi freqCpsdvsr */ + if (handle->mode == HAL_SPI_MASTER) { + SPI_PARAM_CHECK_WITH_RET(IsSpiFreqCpsdvsr(handle->freqCpsdvsr), BASE_STATUS_ERROR); + } + /* Check motorola clkPolarity and clkPhase */ + if (handle->frameFormat == HAL_SPI_MODE_MOTOROLA) { + SPI_PARAM_CHECK_WITH_RET(IsSpiClkPolarity(handle->clkPolarity), BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(IsSpiClkPhase(handle->clkPhase), BASE_STATUS_ERROR); + } + /* Check microwire waitVal */ + if (handle->frameFormat == HAL_SPI_MODE_MICROWIRE) { + SPI_PARAM_CHECK_WITH_RET(IsSpiWaitVal(handle->waitVal), BASE_STATUS_ERROR); + } + /* Check tx rx interrupt size */ + if (handle->xFerMode == HAL_XFER_MODE_INTERRUPTS) { + SPI_PARAM_CHECK_WITH_RET(IsSpiTxIntSize(handle->txIntSize), BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(IsSpiRxIntSize(handle->rxIntSize), BASE_STATUS_ERROR); + } + /* Check tx rx dma burst size */ + if (handle->xFerMode == HAL_XFER_MODE_DMA) { + SPI_PARAM_CHECK_WITH_RET(IsSpiTxDmaBurstSize(handle->txDMABurstSize), BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(IsSpiRxDmaBurstSize(handle->rxDMABurstSize), BASE_STATUS_ERROR); + } + return BASE_STATUS_OK; +} + +/** + * @brief Configuring the Register Parameters of the Three Transfer Modes. + * @param handle SPI handle. + * @retval BASE status type: OK, ERROR. + */ +static BASE_StatusType ConfigThreeTransferParam(SPI_Handle *handle) +{ + SPI_ASSERT_PARAM(handle != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + /* Configurations related to the three transmission modes */ + if (handle->xFerMode == HAL_XFER_MODE_BLOCKING) { + handle->baseAddress->SPIIMSC.reg = 0x0; + } else if (handle->xFerMode == HAL_XFER_MODE_INTERRUPTS) { + handle->baseAddress->SPIIMSC.reg = SPI_INTERRUPT_SET_ALL; + /* Setting the rx and tx interrupt transfer size */ + handle->baseAddress->SPITXFIFOCR.BIT.txintsize = handle->txIntSize; + handle->baseAddress->SPIRXFIFOCR.BIT.rxintsize = handle->rxIntSize; + } else if (handle->xFerMode == HAL_XFER_MODE_DMA) { + handle->baseAddress->SPIIMSC.reg = 0x0; + /* Setting the DMA rx and tx burst transfer size */ + handle->baseAddress->SPITXFIFOCR.BIT.txintsize = handle->txDMABurstSize; + handle->baseAddress->SPIRXFIFOCR.BIT.rxintsize = handle->rxDMABurstSize; + } else { + /* xFerMode set error */ + handle->errorCode = BASE_STATUS_ERROR; + handle->state = HAL_SPI_STATE_RESET; + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief Internal chip select control. + * @param handle SPI handle. + * @param control SPI_CHIP_DESELECT or SPI_CHIP_SELECT + * @retval None. + */ +static void InternalCsControl(SPI_Handle *handle, unsigned int control) +{ + BASE_FUNC_UNUSED(handle); + BASE_FUNC_UNUSED(control); +} + +/** + * @brief Chip select control. + * @param handle SPI handle. + * @param control SPI_CHIP_DESELECT or SPI_CHIP_SELECT + * @retval None. + */ +static void SpiCsControl(SPI_Handle *handle, unsigned int control) +{ + /* The chip select signal is determined by the chip logic. */ + if (handle->csMode == SPI_CHIP_SELECT_MODE_INTERNAL) { + InternalCsControl(handle, control); + } else { + /* The chip select signal is determined by callback */ + if (handle->userCallBack.CsCtrlCallback != NULL) { + handle->csCtrl = control; + handle->userCallBack.CsCtrlCallback(handle); + } + } +} + +/** + * @brief Invoke rx tx callback function. + * @param handle SPI handle. + * @retval None. + */ +static void SpiRxTxCallack(void *handle) +{ + SPI_Handle *spiHandle = (SPI_Handle *) handle; + SPI_ASSERT_PARAM(spiHandle != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(spiHandle->baseAddress)); + if (spiHandle->txCount == spiHandle->transferSize) { + /* Invoke tx callback function. */ + if (spiHandle->userCallBack.TxCpltCallback != NULL) { + spiHandle->userCallBack.TxCpltCallback(spiHandle); + } + spiHandle->baseAddress->SPIIMSC.BIT.txim = 0x0; + } + + if (spiHandle->rxCount >= spiHandle->transferSize) { + /* Disable all interrupt */ + spiHandle->baseAddress->SPIIMSC.reg = 0x0; + /* Clear all interrupt */ + spiHandle->baseAddress->SPIICR.BIT.roric = BASE_CFG_SET; + spiHandle->baseAddress->SPIICR.BIT.rtic = BASE_CFG_SET; + + SpiCsControl(spiHandle, SPI_CHIP_DESELECT); + + /* Invoke rx callback function. */ + if (spiHandle->userCallBack.RxCpltCallback != NULL) { + spiHandle->userCallBack.RxCpltCallback(spiHandle); + } + /* Invoke tx rx callback function. */ + if (spiHandle->userCallBack.TxRxCpltCallback != NULL) { + spiHandle->userCallBack.TxRxCpltCallback(spiHandle); + } + spiHandle->state = HAL_SPI_STATE_READY; + } +} + +/** + * @brief Writes data from the buffer to the FIFO. + * @param handle SPI handle. + * @retval None. + */ +static void WriteData(SPI_Handle *handle) +{ + unsigned int size = 0; + while ((size < SPI_WRITE_FIFO_SIZE) && (handle->baseAddress->SPISR.BIT.tnf) && + (handle->transferSize > handle->txCount)) { + if (handle->dataWidth > SPI_DATA_WIDTH_8BIT) { + /* Only data needs to be read. Due to SPI characteristics, + data must be transmitted before data can be read. Therefore, 0x0 is transmitted. */ + if (handle->txBuff == NULL) { + handle->baseAddress->SPIDR.reg = 0x0; + handle->txCount += SPI_DATA_WIDTH_SHIFT_16BIT; + } else { + handle->baseAddress->SPIDR.reg = *(unsigned short *)handle->txBuff; + handle->txCount += SPI_DATA_WIDTH_SHIFT_16BIT; /* txCount is number of bytes transferred */ + handle->txBuff += SPI_DATA_WIDTH_SHIFT_16BIT; + } + } else { /* datawidth is 8bit */ + if (handle->txBuff == NULL) { + handle->baseAddress->SPIDR.reg = 0x0; + handle->txCount += SPI_DATA_WIDTH_SHIFT_8BIT; + } else { + handle->baseAddress->SPIDR.reg = *(unsigned char *)handle->txBuff; + handle->txCount += SPI_DATA_WIDTH_SHIFT_8BIT; /* txCount is number of bytes transferred */ + handle->txBuff += SPI_DATA_WIDTH_SHIFT_8BIT; + } + } + size++; + } +} + +/** + * @brief Reads data from the FIFO to the buffer. + * @param handle SPI handle. + * @retval None. + */ +static void ReadData(SPI_Handle *handle) +{ + unsigned short val; + + while ((handle->baseAddress->SPISR.BIT.rne) && (handle->transferSize > handle->rxCount)) { + if (handle->dataWidth > SPI_DATA_WIDTH_8BIT) { + /* When only data is transmitted, the data in the RX FIFO needs to be read. */ + if (handle->rxBuff == NULL) { + val = handle->baseAddress->SPIDR.reg; + BASE_FUNC_UNUSED(val); + handle->rxCount += SPI_DATA_WIDTH_SHIFT_16BIT; + } else { + *(unsigned short *)handle->rxBuff = handle->baseAddress->SPIDR.reg; + handle->rxCount += SPI_DATA_WIDTH_SHIFT_16BIT; + handle->rxBuff += SPI_DATA_WIDTH_SHIFT_16BIT; + } + } else { /* datawidth is 8bit */ + if (handle->rxBuff == NULL) { + val = handle->baseAddress->SPIDR.reg; + BASE_FUNC_UNUSED(val); + handle->rxCount += SPI_DATA_WIDTH_SHIFT_8BIT; + } else { + *(unsigned char *)handle->rxBuff = handle->baseAddress->SPIDR.reg & 0xff; + handle->rxCount += SPI_DATA_WIDTH_SHIFT_8BIT; + handle->rxBuff += SPI_DATA_WIDTH_SHIFT_8BIT; + } + } + } +} + +/** + * @brief Read/write based on input parameters. + * The Motorola SPI/TI synchronous serial interface is full-duplex. + * Each data is received. Even if only data needs to be transmitted, + * the RX FIFO needs to be cleared. + * @param handle SPI handle. + * @retval None. + */ +static void ReadWriteData(SPI_Handle *handle) +{ + unsigned int preTick = DCL_SYSTICK_GetTick(); + unsigned int curTick = preTick; + unsigned long long delta = 0; + /* Calculate the timeout tick. */ + unsigned long long targetDelta = HAL_CRG_GetIpFreq(SYSTICK_BASE) / SPI_TICK_MS_DIV * SPI_WAIT_TIMEOUT; + WriteData(handle); + while (true) { + /* Wait for the write operation to complete */ + if (handle->baseAddress->SPISR.BIT.bsy == BASE_CFG_UNSET && + handle->baseAddress->SPISR.BIT.tfe == BASE_CFG_SET && + handle->baseAddress->SPISR.BIT.rne == BASE_CFG_SET) { + break; + } + curTick = DCL_SYSTICK_GetTick(); + delta += curTick > preTick ? curTick - preTick : SYSTICK_MAX_VALUE - preTick + curTick; + /* Exit upon timeout */ + if (delta >= targetDelta) { + handle->errorCode = BASE_STATUS_TIMEOUT; + break; + } + preTick = curTick; + } + ReadData(handle); +} + +/** + * @brief Reads and writes data based on the interrupt flag. + * @param handle SPI handle. + * @retval None. + */ +static void ReadWriteInt(SPI_Handle *handle) +{ + /* 0x02 Receive timeout interrupt, 0x04 receive FIFO interrupt */ + if ((handle->mode == HAL_SPI_SLAVE) && + ((handle->baseAddress->SPIMIS.reg == 0x04) || + (handle->baseAddress->SPIMIS.reg == 0x02))) { + ReadData(handle); + } else { /* master mode */ + if (handle->baseAddress->SPIMIS.BIT.rxmis || handle->baseAddress->SPIMIS.BIT.rtmis) { + ReadData(handle); + } + if (handle->baseAddress->SPIMIS.BIT.txmis) { + WriteData(handle); + } + } +} + +/** + * @brief Blocking read data processing. + * @param handle SPI handle. + * @param timeout Timeout period,unit: ms. + * @retval None. + */ +static void ReadBlocking(SPI_Handle *handle, unsigned int timeout) +{ + unsigned int preTick = DCL_SYSTICK_GetTick(); + unsigned int curTick = preTick; + unsigned long long delta = 0; + unsigned long long targetDelta = HAL_CRG_GetIpFreq(SYSTICK_BASE) / SPI_TICK_MS_DIV * timeout; + + /* Pull down the CS before transmitting data. */ + SpiCsControl(handle, SPI_CHIP_SELECT); + if (!handle->baseAddress->SPICR1.BIT.sse) { + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_SET; /* spi enable */ + } + while (handle->transferSize > handle->rxCount) { + curTick = DCL_SYSTICK_GetTick(); + delta += curTick > preTick ? curTick - preTick : SYSTICK_MAX_VALUE - preTick + curTick; + if (delta >= targetDelta) { /* The configured timeout period is exceeded. */ + handle->errorCode = BASE_STATUS_TIMEOUT; + break; + } + ReadData(handle); + preTick = curTick; + } + /* Pull up the CS after transmitting data. */ + SpiCsControl(handle, SPI_CHIP_DESELECT); + handle->state = HAL_SPI_STATE_READY; +} + +/** + * @brief Blocking read/write data processing. + * @param handle SPI handle. + * @param timeout Timeout period,unit: ms. + * @retval None. + */ +static void ReadWriteBlocking(SPI_Handle *handle, unsigned int timeout) +{ + unsigned int preTick = DCL_SYSTICK_GetTick(); + unsigned int curTick = preTick; + unsigned long long delta = 0; + unsigned long long targetDelta = HAL_CRG_GetIpFreq(SYSTICK_BASE) / SPI_TICK_MS_DIV * timeout; + /* Pull down the CS before transmitting data. */ + SpiCsControl(handle, SPI_CHIP_SELECT); + if (!handle->baseAddress->SPICR1.BIT.sse) { + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_SET; /* spi enable */ + } + + while (handle->transferSize > handle->txCount || handle->transferSize > handle->rxCount) { + curTick = DCL_SYSTICK_GetTick(); + delta += curTick > preTick ? curTick - preTick : SYSTICK_MAX_VALUE - preTick + curTick; + if (delta >= targetDelta) { /* The configured timeout period is exceeded. */ + handle->errorCode = BASE_STATUS_TIMEOUT; + break; + } + ReadWriteData(handle); + preTick = curTick; + } + /* Pull up the CS after transmitting data. */ + SpiCsControl(handle, SPI_CHIP_DESELECT); + handle->state = HAL_SPI_STATE_READY; +} + +/** + * @brief SPI read/write parameter configuration. + * @param handle SPI handle. + * @param rData Address of the data buff to be Receiving. + * @param wData Address of the data buff to be sent. + * @param dataSiz Number of the data to be Receivingd and sent. + * @retval None. + */ +static void ConfigTransmissionParameter(SPI_Handle *handle, + unsigned char *rData, + unsigned char *wData, + unsigned int dataSize) +{ + handle->errorCode = BASE_STATUS_OK; + handle->rxBuff = rData; + handle->txBuff = wData; + if (handle->dataWidth > SPI_DATA_WIDTH_8BIT && + handle->xFerMode == HAL_XFER_MODE_DMA) { + handle->transferSize = dataSize / 2; /* Processes 2 bytes at a time */ + } else { + handle->transferSize = dataSize; + } + handle->txCount = 0; + handle->rxCount = 0; +} + +/** + * @brief SPI Clear Rx Fifo. + * @param handle SPI handle. + * @retval None. + */ +static void ClearSpiRxFifo(SPI_Handle *handle) +{ + /* Invalid data in the RX FIFO, Clearing the RX FIFO. */ + unsigned short val; + while (handle->baseAddress->SPISR.BIT.rne) { + val = handle->baseAddress->SPIDR.reg; + BASE_FUNC_UNUSED(val); + } +} + +/** + * @brief Initializing the SPI Module. + * @param handle SPI handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_Init(SPI_Handle *handle) +{ + unsigned int cr0Reg; + unsigned int temp; + unsigned char frCps; + SPI_ASSERT_PARAM(handle != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + /* Check whether initialization parameters are correctly set */ + if (CheckAllInitParameters(handle) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + + handle->state = HAL_SPI_STATE_BUSY; + + handle->baseAddress->SPICR1.BIT.lbm = BASE_CFG_UNSET; + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_UNSET; + handle->baseAddress->SPICR1.BIT.bitend = handle->endian; /* Setting the endian mode */ + handle->baseAddress->SPICR1.BIT.ms = handle->mode; + + temp = ((unsigned int)handle->freqScr) << SPI_CR0_SCR_POS; + cr0Reg = (handle->baseAddress->SPICR0.reg & (~SPI_CR0_SCR_MASK)) | temp; + handle->baseAddress->SPICR0.reg = cr0Reg; + + if (handle->mode == HAL_SPI_MASTER) { + frCps = handle->freqCpsdvsr; + /* Modulo 2 to get an even number */ + handle->baseAddress->SPICPSR.BIT.cpsdvsr = ((frCps % 2) == 0 ? frCps : frCps - 1); + } + if (handle->frameFormat == HAL_SPI_MODE_MOTOROLA) { + handle->baseAddress->SPICR0.BIT.sph = handle->clkPhase; + handle->baseAddress->SPICR0.BIT.spo = handle->clkPolarity; + } + + handle->baseAddress->SPICR0.BIT.frf = handle->frameFormat; + handle->baseAddress->SPICR0.BIT.dss = handle->dataWidth; + + /* Indicates whether to enable the Microwire wait period. */ + if ((handle->frameFormat == HAL_SPI_MODE_MICROWIRE) && (handle->waitEn == BASE_CFG_ENABLE)) { + handle->baseAddress->SPICR1.BIT.waitval = handle->waitVal; + handle->baseAddress->SPICR1.BIT.waiten = BASE_CFG_SET; + } else { + handle->baseAddress->SPICR1.BIT.waiten = BASE_CFG_UNSET; + } + + if (ConfigThreeTransferParam(handle) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + handle->state = HAL_SPI_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief Deinitialize the SPI module. + * @param handle SPI handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_Deinit(SPI_Handle *handle) +{ + SPI_ASSERT_PARAM(handle != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + + handle->state = HAL_SPI_STATE_BUSY; + + /* Disable rx and tx DMA, SPI disable */ + handle->baseAddress->SPIIMSC.reg = 0x0; + handle->baseAddress->SPIDMACR.BIT.rxdmae = BASE_CFG_UNSET; + handle->baseAddress->SPIDMACR.BIT.txdmae = BASE_CFG_UNSET; + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_UNSET; + handle->state = HAL_SPI_STATE_RESET; + /* Clean callback */ + handle->userCallBack.TxCpltCallback = NULL; + handle->userCallBack.RxCpltCallback = NULL; + handle->userCallBack.TxRxCpltCallback = NULL; + handle->userCallBack.ErrorCallback = NULL; + handle->userCallBack.CsCtrlCallback = NULL; + return BASE_STATUS_OK; +} + +/** + * @brief SPI Parameter Configuration. + * @param handle SPI handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_ConfigParameter(SPI_Handle *handle) +{ + unsigned int cr0Reg; + unsigned int temp; + unsigned char frCps; + SPI_ASSERT_PARAM(handle != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + if (CheckAllInitParameters(handle) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_UNSET; + handle->baseAddress->SPICR1.BIT.ms = handle->mode; + handle->baseAddress->SPICR0.BIT.frf = handle->frameFormat; + handle->baseAddress->SPICR0.BIT.dss = handle->dataWidth; + handle->baseAddress->SPICR1.BIT.bitend = handle->endian; + /* Set freqScr */ + temp = ((unsigned int)handle->freqScr) << SPI_CR0_SCR_POS; + cr0Reg = (handle->baseAddress->SPICR0.reg & (~SPI_CR0_SCR_MASK)) | temp; + handle->baseAddress->SPICR0.reg = cr0Reg; + + if (handle->mode == HAL_SPI_MASTER) { + frCps = handle->freqCpsdvsr; + /* Modulo 2 to get an even number */ + handle->baseAddress->SPICPSR.BIT.cpsdvsr = ((frCps % 2) == 0 ? frCps : frCps - 1); + } + if (handle->frameFormat == HAL_SPI_MODE_MOTOROLA) { + handle->baseAddress->SPICR0.BIT.sph = handle->clkPhase; + handle->baseAddress->SPICR0.BIT.spo = handle->clkPolarity; + } + + if (handle->frameFormat == HAL_SPI_MODE_MICROWIRE) { + handle->baseAddress->SPICR1.BIT.waitval = handle->waitVal; + } + + /* Setting the Interrupt Thresholds */ + if (handle->xFerMode == HAL_XFER_MODE_INTERRUPTS) { + handle->baseAddress->SPITXFIFOCR.BIT.txintsize = handle->txIntSize; + handle->baseAddress->SPIRXFIFOCR.BIT.rxintsize = handle->rxIntSize; + } else if (handle->xFerMode == HAL_XFER_MODE_DMA) { + handle->baseAddress->SPITXFIFOCR.BIT.txintsize = handle->txDMABurstSize; + handle->baseAddress->SPIRXFIFOCR.BIT.rxintsize = handle->rxDMABurstSize; + } else { + ; + } + + return BASE_STATUS_OK; +} + +/** + * @brief Callback Function Registration. + * @param handle SPI handle. + * @param callbackID Callback function ID.. + * @param pcallback Pointer to the address of the registered callback function. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_RegisterCallback(SPI_Handle *handle, + HAL_SPI_CallbackID callbackID, + SPI_CallbackFuncType pcallback) +{ + BASE_StatusType ret = BASE_STATUS_OK; + SPI_ASSERT_PARAM(handle != NULL && pcallback != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + + if (handle->state == HAL_SPI_STATE_READY) { + switch (callbackID) { + case SPI_TX_COMPLETE_CB_ID : + handle->userCallBack.TxCpltCallback = pcallback; + break; + case SPI_RX_COMPLETE_CB_ID : + handle->userCallBack.RxCpltCallback = pcallback; + break; + case SPI_TX_RX_COMPLETE_CB_ID : + handle->userCallBack.TxRxCpltCallback = pcallback; + break; + case SPI_ERROR_CB_ID : + handle->userCallBack.ErrorCallback = pcallback; + break; + case SPI_CS_CB_ID: + handle->userCallBack.CsCtrlCallback = pcallback; + break; + default : + handle->errorCode = BASE_STATUS_ERROR; + ret = BASE_STATUS_ERROR; + break; + } + } else { + handle->errorCode = BASE_STATUS_ERROR; + ret = BASE_STATUS_ERROR; + } + return ret; +} + +/** + * @brief Receiving data in blocking mode. + * @param handle SPI handle. + * @param rData Address of the data buff to be Receiving. + * @param dataSize Number of the data to be Receiving. + * @param timeout Timeout period,unit: ms. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_ReadBlocking(SPI_Handle *handle, + unsigned char *rData, + unsigned int dataSize, + unsigned int timeout) +{ + SPI_ASSERT_PARAM(handle != NULL && rData != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + SPI_PARAM_CHECK_WITH_RET(handle->state == HAL_SPI_STATE_READY, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + + handle->state = HAL_SPI_STATE_BUSY_RX; + /* Configuring SPI transmission parameters */ + ConfigTransmissionParameter(handle, rData, NULL, dataSize); + ClearSpiRxFifo(handle); /* If there is residual data in the read FIFO, clear the data. */ + if (handle->mode == HAL_SPI_MASTER) { + ReadWriteBlocking(handle, timeout); + } else { + ReadBlocking(handle, timeout); + } + + if (handle->errorCode != BASE_STATUS_OK) { + if (handle->userCallBack.ErrorCallback != NULL) { + handle->userCallBack.ErrorCallback(handle); + } + return handle->errorCode; + } + if (handle->userCallBack.RxCpltCallback != NULL) { + handle->userCallBack.RxCpltCallback(handle); + } + return BASE_STATUS_OK; +} + +/** + * @brief Send data in blocking mode. + * @param handle SPI handle. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be sent. + * @param timeout Timeout period,unit: ms. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_WriteBlocking(SPI_Handle *handle, + unsigned char *wData, + unsigned int dataSize, + unsigned int timeout) +{ + SPI_ASSERT_PARAM(handle != NULL && wData != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + + SPI_PARAM_CHECK_WITH_RET(handle->state == HAL_SPI_STATE_READY, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + + handle->state = HAL_SPI_STATE_BUSY_TX; + /* Configuring SPI transmission parameters */ + ConfigTransmissionParameter(handle, NULL, wData, dataSize); + ClearSpiRxFifo(handle); /* If there is residual data in the read FIFO, clear the data. */ + ReadWriteBlocking(handle, timeout); + if (handle->errorCode != BASE_STATUS_OK) { + if (handle->userCallBack.ErrorCallback != NULL) { + handle->userCallBack.ErrorCallback(handle); + } + return handle->errorCode; + } + if (handle->userCallBack.TxCpltCallback != NULL) { + handle->userCallBack.TxCpltCallback(handle); + } + return BASE_STATUS_OK; +} + +/** + * @brief Receiving and send data in blocking mode. + * @param handle SPI handle. + * @param rData Address of the data buff to be Receiving. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be Receivingd and sent. + * @param timeout Timeout period,unit: ms. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_WriteReadBlocking(SPI_Handle *handle, + unsigned char *rData, + unsigned char *wData, + unsigned int dataSize, + unsigned int timeout) +{ + SPI_ASSERT_PARAM(handle != NULL && rData != NULL && wData != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + + SPI_PARAM_CHECK_WITH_RET(handle->state == HAL_SPI_STATE_READY, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + + handle->state = HAL_SPI_STATE_BUSY_TX_RX; + /* Configuring SPI transmission parameters */ + ConfigTransmissionParameter(handle, rData, wData, dataSize); + ClearSpiRxFifo(handle); /* If there is residual data in the read FIFO, clear the data. */ + ReadWriteBlocking(handle, timeout); + if (handle->errorCode != BASE_STATUS_OK) { + if (handle->userCallBack.ErrorCallback != NULL) { + handle->userCallBack.ErrorCallback(handle); + } + return handle->errorCode; + } + if (handle->userCallBack.TxRxCpltCallback != NULL) { + handle->userCallBack.TxRxCpltCallback(handle); + } + return BASE_STATUS_OK; +} + +/** + * @brief Receiving data in interrupts mode. + * @param handle SPI handle. + * @param rData Address of the data buff to be Receiving. + * @param dataSize Number of the data to be Receiving. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_ReadIT(SPI_Handle *handle, unsigned char *rData, unsigned int dataSize) +{ + SPI_ASSERT_PARAM(handle != NULL && rData != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + + SPI_PARAM_CHECK_WITH_RET(handle->state == HAL_SPI_STATE_READY, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + + handle->state = HAL_SPI_STATE_BUSY_RX; + ConfigTransmissionParameter(handle, rData, NULL, dataSize); + ClearSpiRxFifo(handle); /* If there is residual data in the read FIFO, clear the data. */ + SpiCsControl(handle, SPI_CHIP_SELECT); + if (!handle->baseAddress->SPICR1.BIT.sse) { + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_SET; + } + /* Enable related interrupts. */ + if (handle->mode == HAL_SPI_MASTER) { + /* 0x0F indicate enables all interrupt. */ + handle->baseAddress->SPIIMSC.reg = 0x0F; + } else { + /* 0x07 indicate enables the RX FIFO, RX timeout, and RX overflow interrupt. */ + handle->baseAddress->SPIIMSC.reg = 0x07; + } + return BASE_STATUS_OK; +} + +/** + * @brief Send data in interrupts mode. + * @param handle SPI handle. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_WriteIT(SPI_Handle *handle, unsigned char *wData, unsigned int dataSize) +{ + SPI_ASSERT_PARAM(handle != NULL && wData != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + + SPI_PARAM_CHECK_WITH_RET(handle->state == HAL_SPI_STATE_READY, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + + handle->state = HAL_SPI_STATE_BUSY_TX; + ConfigTransmissionParameter(handle, NULL, wData, dataSize); + ClearSpiRxFifo(handle); /* If there is residual data in the read FIFO, clear the data. */ + /* interrupt enable */ + SpiCsControl(handle, SPI_CHIP_SELECT); + if (!handle->baseAddress->SPICR1.BIT.sse) { + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_SET; + } + /* 0x0F indicate enables all interrupt. */ + handle->baseAddress->SPIIMSC.reg = 0x0F; + + return BASE_STATUS_OK; +} + +/** + * @brief Receiving and send data in interrupts mode. + * @param handle SPI handle. + * @param rData Address of the data buff to be Receiving. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be Receiving and sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_WriteReadIT(SPI_Handle *handle, + unsigned char *rData, + unsigned char *wData, + unsigned int dataSize) +{ + SPI_ASSERT_PARAM(handle != NULL && rData != NULL && wData != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + + SPI_PARAM_CHECK_WITH_RET(handle->state == HAL_SPI_STATE_READY, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + + handle->state = HAL_SPI_STATE_BUSY_TX_RX; + ConfigTransmissionParameter(handle, rData, wData, dataSize); + ClearSpiRxFifo(handle); /* If there is residual data in the read FIFO, clear the data. */ + SpiCsControl(handle, SPI_CHIP_SELECT); + if (!handle->baseAddress->SPICR1.BIT.sse) { + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_SET; + } + /* 0x0F indicate enables all interrupt. */ + handle->baseAddress->SPIIMSC.reg = 0x0F; + + return BASE_STATUS_OK; +} + +/** + * @brief Wait until the SPI data transmission is complete. + * @param handle SPI handle. + * @retval None. + */ +static void WaitComplete(void *handle) +{ + SPI_ASSERT_PARAM(handle != NULL); + SPI_Handle *spiHandle = (SPI_Handle *)(handle); + SPI_ASSERT_PARAM(IsSPIInstance(spiHandle->baseAddress)); + while (true) { + /* Wait for the write operation to complete */ + if (spiHandle->baseAddress->SPISR.BIT.bsy == BASE_CFG_UNSET && + spiHandle->baseAddress->SPISR.BIT.tfe == BASE_CFG_SET && + spiHandle->baseAddress->SPISR.BIT.rne == BASE_CFG_UNSET) { + break; + } + } +} + +/** + * @brief SPI DMA read completion callback function. + * @param handle SPI handle. + * @retval None + */ +static void ReadDmaFinishFun(void *handle) +{ + SPI_ASSERT_PARAM(handle != NULL); + SPI_Handle *spiHandle = (SPI_Handle *)(handle); + SPI_ASSERT_PARAM(IsSPIInstance(spiHandle->baseAddress)); + /* Waiting for SPI data transfer to complete */ + WaitComplete(spiHandle); + SpiCsControl(spiHandle, SPI_CHIP_DESELECT); + + if (spiHandle->state == HAL_SPI_STATE_BUSY_RX) { + if (spiHandle->userCallBack.RxCpltCallback != NULL) { + spiHandle->userCallBack.RxCpltCallback(spiHandle); + } + } + + if (spiHandle->state == HAL_SPI_STATE_BUSY_TX_RX) { + if (spiHandle->userCallBack.TxRxCpltCallback != NULL) { + spiHandle->userCallBack.TxRxCpltCallback(spiHandle); + } + } + + if (spiHandle->state == HAL_SPI_STATE_BUSY_TX) { + if (spiHandle->userCallBack.TxCpltCallback != NULL) { + spiHandle->userCallBack.TxCpltCallback(spiHandle); + } + } + + spiHandle->state = HAL_SPI_STATE_READY; + /* Disable rx fifo DMA */ + spiHandle->baseAddress->SPIDMACR.BIT.rxdmae = BASE_CFG_UNSET; +} + +/** + * @brief SPI DMA write completion callback function. + * @param handle SPI handle. + * @retval None + */ +static void WriteDmaFinishFun(void *handle) +{ + SPI_ASSERT_PARAM(handle != NULL); + SPI_Handle *spiHandle = (SPI_Handle *)(handle); + SPI_ASSERT_PARAM(IsSPIInstance(spiHandle->baseAddress)); + /* Waiting for SPI data transfer to complete */ + WaitComplete(spiHandle); + SpiCsControl(spiHandle, SPI_CHIP_DESELECT); + /* Disable tx fifo DMA */ + spiHandle->baseAddress->SPIDMACR.BIT.txdmae = BASE_CFG_UNSET; + if (spiHandle->userCallBack.TxCpltCallback != NULL && spiHandle->state == HAL_SPI_STATE_READY) { + spiHandle->userCallBack.TxCpltCallback(spiHandle); + } + if (spiHandle->frameFormat == HAL_SPI_MODE_MICROWIRE) { + spiHandle->state = HAL_SPI_STATE_READY; + } +} + +/** + * @brief SPI DMA error callback function. + * @param handle SPI handle. + * @retval None + */ +static void DmaErrorFun(void *handle) +{ + SPI_ASSERT_PARAM(handle != NULL); + SPI_Handle *spiHandle = (SPI_Handle *)(handle); + SPI_ASSERT_PARAM(IsSPIInstance(spiHandle->baseAddress)); + SpiCsControl(spiHandle, SPI_CHIP_DESELECT); + /* Disable rx and tx fifo DMA */ + spiHandle->baseAddress->SPIDMACR.reg = 0; + + if (spiHandle->userCallBack.ErrorCallback != NULL) { + spiHandle->userCallBack.ErrorCallback(spiHandle); + } + spiHandle->state = HAL_SPI_STATE_READY; +} + +/** + * @brief DMA enable Configuration. + * @param handle SPI handle. + * @retval None + */ +static void EnableDma(SPI_Handle *handle) +{ + handle->baseAddress->SPIIMSC.reg = 0x0; + SpiCsControl(handle, SPI_CHIP_SELECT); + if (!handle->baseAddress->SPICR1.BIT.sse) { + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_SET; + } + handle->baseAddress->SPIDMACR.reg = SPI_DMA_FIFO_ENABLE; +} + +/** + * @brief SPI read and write configures the DMA for channel callback functions. + * @param handle SPI handle. + * @retval None + */ +static void SetDmaCallBack(SPI_Handle *handle) +{ + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->rxDmaCh].ChannelFinishCallBack = ReadDmaFinishFun; + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->rxDmaCh].ChannelErrorCallBack = DmaErrorFun; + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->txDmaCh].ChannelFinishCallBack = WriteDmaFinishFun; + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->txDmaCh].ChannelErrorCallBack = DmaErrorFun; +} + +/** + * @brief Receiving data in DMA mode. + * @param handle SPI handle. + * @param rData Address of the data buff to be Receiving. + * @param dataSize Number of the data to be Receiving. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_ReadDMA(SPI_Handle *handle, unsigned char *rData, unsigned int dataSize) +{ + static unsigned short writeVal = 0; + BASE_StatusType ret; + + SPI_ASSERT_PARAM(handle != NULL && rData != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + SPI_ASSERT_PARAM(handle->dmaHandle != NULL); /* Check the DMA transfer handle and channel. */ + SPI_PARAM_CHECK_WITH_RET(handle->txDmaCh < CHANNEL_MAX_NUM, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(handle->rxDmaCh < CHANNEL_MAX_NUM, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET((handle->rxDmaCh != handle->txDmaCh), BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(handle->state == HAL_SPI_STATE_READY, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + + handle->state = HAL_SPI_STATE_BUSY_RX; + /* Configuring SPI transmission parameters */ + ConfigTransmissionParameter(handle, rData, NULL, dataSize); + ClearSpiRxFifo(handle); /* If there is residual data in the read FIFO, clear the data. */ + SetDmaCallBack(handle); + /* To set the auto-increment mode of the source and destination addresses */ + handle->dmaHandle->DMA_Channels[handle->rxDmaCh].srcAddrInc = DMA_ADDR_UNALTERED; + handle->dmaHandle->DMA_Channels[handle->rxDmaCh].destAddrInc = DMA_ADDR_INCREASE; + handle->dmaHandle->DMA_Channels[handle->txDmaCh].srcAddrInc = DMA_ADDR_UNALTERED; + handle->dmaHandle->DMA_Channels[handle->txDmaCh].destAddrInc = DMA_ADDR_UNALTERED; + + /* DMA rx channel Interrupt Transfer */ + ret = HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t) & (handle->baseAddress->SPIDR.reg), + (uintptr_t)handle->rxBuff, handle->transferSize, handle->rxDmaCh); + if (ret != BASE_STATUS_OK) { + handle->state = HAL_SPI_STATE_READY; + return ret; + } + /* DMA tx channel Interrupt Transfer */ + if (handle->mode == HAL_SPI_MASTER) { + ret = HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t) & writeVal, (uintptr_t) & (handle->baseAddress->SPIDR.reg), + handle->transferSize, handle->txDmaCh); + if (ret != BASE_STATUS_OK) { + handle->state = HAL_SPI_STATE_READY; + return ret; + } + } + EnableDma(handle); + return ret; +} + +/** + * @brief Send data in DMA mode. + * @param handle SPI handle. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_WriteDMA(SPI_Handle *handle, unsigned char *wData, unsigned int dataSize) +{ + static unsigned short readVal; + BASE_StatusType ret; + + SPI_ASSERT_PARAM(handle != NULL && wData != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + SPI_ASSERT_PARAM(handle->dmaHandle != NULL); /* Check the DMA transfer handle and channel. */ + SPI_PARAM_CHECK_WITH_RET(handle->txDmaCh < CHANNEL_MAX_NUM, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(handle->rxDmaCh < CHANNEL_MAX_NUM, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET((handle->rxDmaCh != handle->txDmaCh), BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(handle->state == HAL_SPI_STATE_READY, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + + handle->state = HAL_SPI_STATE_BUSY_TX; + /* Configuring SPI transmission parameters */ + ConfigTransmissionParameter(handle, NULL, wData, dataSize); + ClearSpiRxFifo(handle); /* If there is residual data in the read FIFO, clear the data. */ + SetDmaCallBack(handle); + /* To set the auto-increment mode of the source and destination addresses */ + handle->dmaHandle->DMA_Channels[handle->rxDmaCh].srcAddrInc = DMA_ADDR_UNALTERED; + handle->dmaHandle->DMA_Channels[handle->rxDmaCh].destAddrInc = DMA_ADDR_UNALTERED; + handle->dmaHandle->DMA_Channels[handle->txDmaCh].srcAddrInc = DMA_ADDR_INCREASE; + handle->dmaHandle->DMA_Channels[handle->txDmaCh].destAddrInc = DMA_ADDR_UNALTERED; + /* DMA tx channel Interrupt Transfer */ + ret = HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t)handle->txBuff, + (uintptr_t) & (handle->baseAddress->SPIDR.reg), handle->transferSize, handle->txDmaCh); + if (ret != BASE_STATUS_OK) { + handle->state = HAL_SPI_STATE_READY; + return ret; + } + /* DMA rx channel Interrupt Transfer */ + ret = HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t) & (handle->baseAddress->SPIDR.reg), + (uintptr_t) & readVal, handle->transferSize, handle->rxDmaCh); + if (ret != BASE_STATUS_OK) { + handle->state = HAL_SPI_STATE_READY; + return ret; + } + EnableDma(handle); + return ret; +} + +/** + * @brief Receiving and send data in DMA mode. + * @param handle SPI handle. + * @param rData Address of the data buff to be Receiving. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be Receiving and sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_WriteReadDMA(SPI_Handle *handle, + unsigned char *rData, + unsigned char *wData, + unsigned int dataSize) +{ + BASE_StatusType ret; + + SPI_ASSERT_PARAM(handle != NULL && rData != NULL && wData != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + SPI_ASSERT_PARAM(handle->dmaHandle != NULL); /* Check the DMA transfer handle and channel. */ + SPI_PARAM_CHECK_WITH_RET(handle->txDmaCh < CHANNEL_MAX_NUM, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(handle->rxDmaCh < CHANNEL_MAX_NUM, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET((handle->rxDmaCh != handle->txDmaCh), BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(handle->state == HAL_SPI_STATE_READY, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + + handle->state = HAL_SPI_STATE_BUSY_TX_RX; + /* Configuring SPI transmission parameters */ + ConfigTransmissionParameter(handle, rData, wData, dataSize); + ClearSpiRxFifo(handle); /* If there is residual data in the read FIFO, clear the data. */ + SetDmaCallBack(handle); + /* To set the auto-increment mode of the source and destination addresses */ + handle->dmaHandle->DMA_Channels[handle->rxDmaCh].srcAddrInc = DMA_ADDR_UNALTERED; + handle->dmaHandle->DMA_Channels[handle->rxDmaCh].destAddrInc = DMA_ADDR_INCREASE; + handle->dmaHandle->DMA_Channels[handle->txDmaCh].srcAddrInc = DMA_ADDR_INCREASE; + handle->dmaHandle->DMA_Channels[handle->txDmaCh].destAddrInc = DMA_ADDR_UNALTERED; + /* DMA rx channel Interrupt Transfer */ + ret = HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t) & (handle->baseAddress->SPIDR.reg), + (uintptr_t)handle->rxBuff, handle->transferSize, handle->rxDmaCh); + if (ret != BASE_STATUS_OK) { + handle->state = HAL_SPI_STATE_READY; + return ret; + } + /* DMA tx channel Interrupt Transfer */ + ret = HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t)handle->txBuff, + (uintptr_t) & (handle->baseAddress->SPIDR.reg), handle->transferSize, handle->txDmaCh); + if (ret != BASE_STATUS_OK) { + handle->state = HAL_SPI_STATE_READY; + return ret; + } + EnableDma(handle); + return ret; +} + +/** + * @brief Stop DMA transfer. + * @param handle SPI handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_DMAStop(SPI_Handle *handle) +{ + SPI_ASSERT_PARAM(handle != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + BASE_StatusType ret; + + ret = HAL_DMA_StopChannel(handle->dmaHandle, handle->txDmaCh); + if (ret != BASE_STATUS_OK) { + return ret; + } + ret = HAL_DMA_StopChannel(handle->dmaHandle, handle->rxDmaCh); + return ret; +} + +/** + * @brief CS Channel Configuration. + * @param handle SPI handle. + * @param channel SPI CS channel.For details, see the enumeration definition of SPI_ChipSelectChannel. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_SPI_ChipSelectChannelSet(SPI_Handle *handle, SPI_ChipSelectChannel channel) +{ + SPI_ASSERT_PARAM(handle != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + /* Check the validity of the CS parameters. */ + SPI_PARAM_CHECK_WITH_RET(channel >= SPI_CHIP_SELECT_CHANNEL_0 && channel < SPI_CHIP_SELECT_CHANNEL_MAX, + BASE_STATUS_ERROR); + handle->baseAddress->SPICSNCR.BIT.spi_csn_sel = channel; + return BASE_STATUS_OK; +} + +/** + * @brief Obtains the currently configured CS channel. + * @param handle SPI handle. + * @param channel Pointer to the address for storing the obtained CS channel value. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_ChipSelectChannelGet(SPI_Handle *handle, SPI_ChipSelectChannel *channel) +{ + SPI_ASSERT_PARAM(handle != NULL && channel != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + *channel = handle->baseAddress->SPICSNCR.BIT.spi_csn_sel; + return BASE_STATUS_OK; +} + + +/** + * @brief Interrupt Handling Function. + * @param handle SPI_Handle. + * @retval None. + */ +void HAL_SPI_IrqHandler(void *handle) +{ + SPI_Handle *spiHandle = (SPI_Handle *)handle; + SPI_ASSERT_PARAM(spiHandle != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(spiHandle->baseAddress)); + /* Indicates that there is no interruption. */ + if (spiHandle->baseAddress->SPIMIS.reg == 0) { + return; + } + + /* Generating RX overflow interrupt. */ + if (spiHandle->baseAddress->SPIMIS.BIT.rormis) { + spiHandle->baseAddress->SPIIMSC.reg = 0x0; + /* Clear rx interrupt. */ + spiHandle->baseAddress->SPIICR.BIT.roric = BASE_CFG_SET; + spiHandle->baseAddress->SPIICR.BIT.rtic = BASE_CFG_SET; + + spiHandle->errorCode = BASE_STATUS_ERROR; + spiHandle->state = HAL_SPI_STATE_ERROR; + /* Invoke the error callback function. */ + if (spiHandle->userCallBack.ErrorCallback != NULL) { + spiHandle->userCallBack.ErrorCallback(spiHandle); + } + SpiCsControl(spiHandle, SPI_CHIP_DESELECT); + return; + } + /* Reads and writes data based on the interrupt flag. */ + ReadWriteInt(spiHandle); + SpiRxTxCallack(spiHandle); +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/spi/src/spi_ex.c b/vendor/xinlingyu_92_3061M/Project/drivers/spi/src/spi_ex.c new file mode 100644 index 0000000000000000000000000000000000000000..c13bb3526101ef79237fdc86af8414b321e8d7ca --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/spi/src/spi_ex.c @@ -0,0 +1,54 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file spi_ex.c + * @author MCU Driver Team + * @brief SPI module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the SPI. + * + Peripheral Control functions + */ + +/* Includes ------------------------------------------------------------------*/ +#include "spi_ex.h" + +/** + * @brief SPI SET CHIP CONGFIG SELECT. + * @param handle SPI_handle. + * @param mode SPI CS mode.For details, see the enumeration definition of HAL_SPI_CHIP_CONFIG + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_SPI_SetChipConfigSelectEx(SPI_Handle *handle, HAL_SPI_CHIP_CONFIG mode) +{ + SPI_ASSERT_PARAM(handle != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + SPI_PARAM_CHECK_WITH_RET(IsSpiChipConfigMode(mode), BASE_STATUS_ERROR); + handle->baseAddress->SPICSNCR.BIT.spi_csn_mode = mode; /* set chip mode */ + return BASE_STATUS_OK; +} + +/** + * @brief SPI GET CHIP CONGFIG SELECT. + * @param handle SPI_handle. + * @retval HAL_SPI_CHIP_CONFIG. + */ +HAL_SPI_CHIP_CONFIG HAL_SPI_GetChipConfigSelectEx(SPI_Handle *handle) +{ + SPI_ASSERT_PARAM(handle != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + return handle->baseAddress->SPICSNCR.BIT.spi_csn_mode; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/timer/common/inc/timer.h b/vendor/xinlingyu_92_3061M/Project/drivers/timer/common/inc/timer.h new file mode 100644 index 0000000000000000000000000000000000000000..edd902cdb380ab2190d96a75a885c6b37776fd17 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/timer/common/inc/timer.h @@ -0,0 +1,112 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file timer.h + * @author MCU Driver Team + * @brief TIMER module driver. + * @details This file provides firmware TIMER Handle structure and Functions + * prototypes to manage the following functionalities of the TIMER. + * + Initialization and de-initialization functions + * + config the register of timer + */ + +#ifndef McuMagicTag_TIMER_H +#define McuMagicTag_TIMER_H + +/* Includes ------------------------------------------------------------------*/ +#include "timer_ip.h" + +/* Macro definitions ---------------------------------------------------------*/ + +/** + * @defgroup TIMER TIMER + * @brief TIMER module. + * @{ + */ + +/** + * @defgroup TIMER_Common TIMER Common + * @brief TIMER common external module. + * @{ + */ + +/** + * @defgroup TIMER_Handle_Definition TIMER Handle Definition + * @{ + */ + +/** + * @brief Time base address and Configuration Structure definition + */ +typedef struct _TIMER_Handle { + TIMER_RegStruct *baseAddress; /**< Base address of timer. */ + TIMER_CountMode cntMode; /**< Timer cnt Mode. */ + TIMER_Mode mode; /**< Timer counting mode selection. */ + TIMER_PrescalerFactor prescaler; /**< Timer prescaler. */ + TIMER_Size size; /**< Timer size 16 or 32 bits. */ + volatile unsigned int load; /**< Period, set the TIMERx_LOAD. */ + volatile unsigned int bgLoad; /**< Backgroud period, set the TIMEx_BGLOAD. */ + bool interruptEn; /**< Interrupt enable or disable. */ + bool adcSocReqEnable; /**< Trigger ADC Enable Sampling. */ + bool dmaReqEnable; /**< Enable bit for DMA single request and DAM burst sampling. */ + TIMER_UserCallBack userCallBack; /**< Callback function of timer. */ + TIMER_ExtendHandle handleEx; /**< TIMER extend handle */ +} TIMER_Handle; + +/** + * @brief Typedef callback function of TIMER + */ +typedef void (*TIMER_CallBackFunc)(void *param); + +/** + * @} + */ + +/** + * @defgroup TIMER_API_Declaration TIMER HAL API + * @{ + */ +BASE_StatusType HAL_TIMER_Init(TIMER_Handle *handle); + +void HAL_TIMER_DeInit(TIMER_Handle *handle); + +void HAL_TIMER_Start(TIMER_Handle *handle); + +void HAL_TIMER_Stop(TIMER_Handle *handle); + +BASE_StatusType HAL_TIMER_Config(TIMER_Handle *handle, TIMER_CFG_TYPE cfgType); + +BASE_StatusType HAL_TIMER_GetConfig(TIMER_Handle *handle); + +BASE_StatusType HAL_TIMER_RegisterCallback(TIMER_Handle *handle, TIMER_InterruptType typeID, + TIMER_CallBackFunc callBackFunc); + +BASE_StatusType HAL_TIMER_UnRegisterCallback(TIMER_Handle *handle, TIMER_InterruptType typeID); + +void HAL_TIMER_IrqHandler(void *handle); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_TIMER_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/timer/inc/timer_ex.h b/vendor/xinlingyu_92_3061M/Project/drivers/timer/inc/timer_ex.h new file mode 100644 index 0000000000000000000000000000000000000000..0b04725c9bed5440f51fa2b4aa3b2d31c5be2c98 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/timer/inc/timer_ex.h @@ -0,0 +1,48 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file timer_ex.h + * @author MCU Driver Team + * @brief TIMER module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the TIMER. + * + Defines extended functions of the timer module. + */ +#ifndef McuMagicTag_TIMER_EX_H +#define McuMagicTag_TIMER_EX_H +#include "timer.h" +/** + * @addtogroup TIMER_IP + * @{ + */ + +/** + * @defgroup TIMER_EX_API_Declaration TIMER HAL API EX + * @{ + */ + +/* Setting DMA the request overflow interrupt */ +void HAL_TIMER_DMARequestOverFlowEx(TIMER_Handle *handle, bool overflow); +BASE_StatusType HAL_TIMER_TriggerAdcEx(TIMER_Handle *handle, bool enable); +/** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/timer/inc/timer_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/timer/inc/timer_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..877b9ffbe806289ce558ae147ddcb9bd08762f85 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/timer/inc/timer_ip.h @@ -0,0 +1,666 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file timer_ip.h + * @author MCU Driver Team + * @brief TIMER module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the TIMER. + * + TIMER register mapping structure + * + Direct Configuration Layer functions of TIMER + */ + + +#ifndef McuMagicTag_TIMER_IP_H +#define McuMagicTag_TIMER_IP_H + +/* Includes ------------------------------------------------------------------*/ +#include "baseinc.h" + +/** + * @addtogroup TIMER + * @{ + */ + +/** + * @defgroup TIMER_IP TIMER_IP + * @brief TIMER_IP: timer_v1 + * @{ + */ + +/** + * @defgroup TIMER_Param_Def TIMER Parameters Definition + * @brief Definition of TIMER configuration parameters. + * @{ + */ +#ifdef TIMER_PARAM_CHECK +#define TIMER_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define TIMER_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define TIMER_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define TIMER_ASSERT_PARAM(para) ((void)0U) +#define TIMER_PARAM_CHECK_NO_RET(para) ((void)0U) +#define TIMER_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +/** + * @brief Period min value + */ +#define PERIOD_MIN_VALUE 1 + +/** + * @brief Extent handle definition of timer + */ +typedef struct { +} TIMER_ExtendHandle; + +/** + * @brief TIMER type of user callback function + */ +typedef enum { + TIMER_PERIOD_FIN = 0x00000000U, + TIMER_OVER_FLOW = 0x00000001U, +} TIMER_InterruptType; + +/** + * @brief TIMER type of user callback function + */ +typedef struct { + void (* TimerPeriodFinCallBack)(void *handle); + void (* TimerOverFlowCallBack)(void *handle); +} TIMER_UserCallBack; + +/** + * @brief TIMER operating mode definition + */ +typedef enum { + TIMER_MODE_RUN_FREE = 0x00000000U, + TIMER_MODE_RUN_PERIODIC = 0x00000001U, + TIMER_MODE_RUN_ONTSHOT = 0x00000002U, +} TIMER_Mode; + +/** + * @brief TIMER counting mode definition + */ +typedef enum { + TIMER_COUNT_UP = 0x00000000U, + TIMER_COUNT_DOWN = 0x00000001U, +} TIMER_CountMode; + +/** + * @brief TIMER division factor definition + */ +typedef enum { + TIMERPRESCALER_NO_DIV = 0x00000000U, + TIMERPRESCALER_DIV_16 = 0x00000001U, + TIMERPRESCALER_DIV_256 = 0x00000002U, +} TIMER_PrescalerFactor; + +/** + * @brief TIMER couter size definition + */ +typedef enum { + TIMER_SIZE_16BIT = 0x00000000U, + TIMER_SIZE_32BIT = 0x00000001U, +} TIMER_Size; + +/** + * @brief Typedef TIMER Paramter Config type + */ +typedef enum { + TIMER_CFG_LOAD = 0x00000001, + TIMER_CFG_BGLOAD = 0x00000002, + TIMER_CFG_MODE = 0x00000004, + TIMER_CFG_INTERRUPT = 0x00000008, + TIMER_CFG_PRESCALER = 0x00000010, + TIMER_CFG_SIZE = 0x00000020, + TIMER_CFG_DMA_REQ = 0x00000040, + TIMER_CFG_ADC_REQ = 0x00000080, +} TIMER_CFG_TYPE; + +/** + * @} + */ + +/** + * @defgroup TIMER_Reg_Def TIMER Register Definition + * @brief register mapping structure + * @{ + */ + +/** + * @brief TIMER control register structure + */ +typedef union { + unsigned int reg; + struct { + unsigned int oneshot : 1; /**< Counting mode is single counting mode or periodic counting mode. */ + unsigned int timersize : 1; /**< 16-bit/32-bit counter operation mode. */ + unsigned int timerpre : 2; /**< This field is used to set the prescale factor of the timer. */ + unsigned int dmaovintenable : 1; /**< DMA request overflow interrupt mask. */ + unsigned int timerintenable : 1; /**< Timing interrupt mask. */ + unsigned int timermode : 1; /**< Indicates the count mode of a timer. */ + unsigned int timeren : 1; /**< Timer enable. */ + unsigned int reserved : 24; + } BIT; +} volatile TIMER_CONTROL_Reg; + +/** + * @brief TIMER original interrupt register + */ +typedef struct { + unsigned int timerris : 1; /**< Raw interrupt status of the timing interrupt. */ + unsigned int dmaovris : 1; /**< Raw status of the DMA request overflow interrupt. */ + unsigned int reserved : 30; +} volatile TIMER_RIS_Reg; + +/** + * @brief TIMER interrupt register of shield + */ +typedef struct { + unsigned int timermis : 1; /**< Masked timing interrupt status. */ + unsigned int dmaovmis : 1; /**< Status of the masked DMA request overflow interrupt. */ + unsigned int reserved : 30; +} volatile TIMER_MIS_Reg; + +/** + * @brief TIMER ControlB + */ +typedef union { + unsigned int reg; + struct { + unsigned int dmabreqen : 1; /**< DMA burst request enable. */ + unsigned int dmasreqen : 1; /**< DMA single request enable bit. */ + unsigned int socen : 1; /**< Enable bit for triggering the ADC sampling signal (SOC signal). */ + unsigned int reserved : 29; + } BIT; +} volatile TIMER_CONTROLB_Reg; + +/** + * @brief TIMER DMAOV_INTCLR + */ +typedef union { + unsigned int reg; + struct { + unsigned int dmaov_intclr : 1; /**< DMA request overflow interrupt clear bit. */ + unsigned int reserved : 30; + } BIT; +} volatile DMAOV_INTCLR_Reg; +/** + * @brief TIMER register structure + */ +typedef struct { + unsigned int timer_load; /**< Initial count value register, offset address: 0x00000000U */ + unsigned int timer_value; /**< Current count value register, offset address: 0x00000004U */ + TIMER_CONTROL_Reg TIMERx_CONTROL; /**< Timer control register, offset address: 0x00000008U */ + unsigned int timer_intclr; /**< Timing interrupt clear register, offset address: 0x0000000CU */ + TIMER_RIS_Reg TIMERx_RIS; /**< Raw interrupt register, offset address: 0x00000010U */ + TIMER_MIS_Reg TIMERx_MIS; /**< Masked interrupt register, offset address: 0x00000014U */ + unsigned int timerbgload; /**< Count value register in periodic mode, offset address: 0x00000018U */ + TIMER_CONTROLB_Reg TIMERx_CONTROLB; /**< Timerx control register B, offset address: 0x0000001CU */ + DMAOV_INTCLR_Reg DMAOV_INTCLR; /**< DMA request overflow INT clear register, offset address: 0x00000020U */ +} volatile TIMER_RegStruct; +/** + * @} + */ + +/* Parameter Check -----------------------------------------------------------*/ +/** + * @brief Verify Timer mode configuration + * @param mode Timer Mode, @ref TIMER_Mode + * @retval true + * @retval false + */ +static inline bool IsTimerMode(TIMER_Mode mode) +{ + return (((mode) == TIMER_MODE_RUN_FREE) || + ((mode) == TIMER_MODE_RUN_PERIODIC) || + ((mode) == TIMER_MODE_RUN_ONTSHOT)); +} + +/** + * @brief Verify Timer Interrupt Type + * @param mode Timer Interrupt Type, @ref TIMER_InterruptType + * @retval true + * @retval false + */ +static inline bool IsTimerInterruptType(TIMER_InterruptType interruptType) +{ + return (((interruptType) == TIMER_PERIOD_FIN) || + ((interruptType) == TIMER_OVER_FLOW)); +} + +/** + * @brief Verify Timer counter size configuration + * @param size Timer Size, @ref TIMER_Size + * @retval true + * @retval false + */ +static inline bool IsTimerSize(TIMER_Size size) +{ + return (((size) == TIMER_SIZE_16BIT) || + ((size) == TIMER_SIZE_32BIT)); +} + +/** + * @brief Verify Timer period configuration + * @param period + * @retval true + * @retval false + */ +static inline bool IsTimerPeriod(unsigned int period) +{ + return ((period) >= PERIOD_MIN_VALUE); +} + +/** + * @brief Verify Timer div configuration + * @param div @see TIMER_PrescalerFactor + * @retval true + * @retval false + */ +static inline bool IsTimerDiv(TIMER_PrescalerFactor div) +{ + return (((div) == TIMERPRESCALER_NO_DIV) || + ((div) == TIMERPRESCALER_DIV_16) || + ((div) == TIMERPRESCALER_DIV_256)); +} + +/** + * @brief Verify Timer interrupt configuration + * @param interruptEn + * @retval true + * @retval false + */ +static inline bool IsTimerInterrupt(unsigned int interruptEn) +{ + return (((interruptEn) == BASE_CFG_SET) || ((interruptEn) == BASE_CFG_UNSET)); +} + + +/* Direct configuration layer ------------------------------------------------*/ + +/** + * @brief Enable the timer, start to run + * @param timerx Timer register baseAddr + * @retval None + */ +static inline void DCL_TIMER_Enable(TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->TIMERx_CONTROL.BIT.timeren = BASE_CFG_SET; +} + +/** + * @brief Stop the timer + * @param timerx Timer register baseAddr + * @retval None + */ +static inline void DCL_TIMER_Disable(TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->TIMERx_CONTROL.BIT.timeren = BASE_CFG_UNSET; +} + +/** + * @brief Get the timer enable flag + * @param timerx Timer register baseAddr + * @retval None + */ +static inline bool DCL_TIMER_GetTimerEn(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_CONTROL.BIT.timeren; +} + +/** + * @brief Get current counter in timer + * @param timerx Timer register baseAddr + * @retval None + */ +static inline unsigned int DCL_TIMER_GetValue(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->timer_value; +} + +/** + * @brief Set the counter with load，which change timer value immediately + * @param timerx Timer register baseAddr + * @param period the init value of the counter + * @retval None + */ +static inline void DCL_TIMER_SetLoad(TIMER_RegStruct *timerx, unsigned int period) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + TIMER_PARAM_CHECK_NO_RET(IsTimerPeriod(period)); + timerx->timer_load = period; +} + +/** + * @brief Get the period of counter + * @param timerx Timer register baseAddr + * @retval None + */ +static inline unsigned int DCL_TIMER_GetLoad(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->timer_load; +} + +/** + * @brief Set the counter with period with bgload + * @param timerx Timer register baseAddr + * @param period the init value of the counter + * @retval None + */ +static inline void DCL_TIMER_SetBgLoad(TIMER_RegStruct *timerx, unsigned int period) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + TIMER_PARAM_CHECK_NO_RET(IsTimerPeriod(period)); + timerx->timerbgload = period; +} + +/** + * @brief Get the bgLoad of timer + * @param timerx Timer register baseAddr + * @retval None + */ +static inline unsigned int DCL_TIMER_GetBgLoad(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->timerbgload; +} + +/** + * @brief Enable timer interrupt + * @param timerx Timer register baseAddr + * @retval None + */ +static inline void DCL_TIMER_InterruptEnable(TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->TIMERx_CONTROL.BIT.timerintenable = BASE_CFG_SET; +} + +/** + * @brief Disable timer interrupt + * @param timerx Timer register baseAddr + * @retval None + */ +static inline void DCL_TIMER_InterruptDisable(TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->TIMERx_CONTROL.BIT.timerintenable = BASE_CFG_UNSET; +} + +/** + * @brief Get timer interrupt enable flag + * @param timerx Timer register baseAddr + * @retval None + */ +static inline bool DCL_TIMER_GetInterruptEnableFlag(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_CONTROL.BIT.timerintenable; +} + +/** + * @brief Set timer size + * @param timerx Timer register baseAddr + * @param size the size of counter, see @ref TIMER_Size + * @retval None + */ +static inline void DCL_TIMER_SetTimerSize(TIMER_RegStruct *timerx, TIMER_Size size) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + TIMER_PARAM_CHECK_NO_RET(IsTimerSize(size)); + timerx->TIMERx_CONTROL.BIT.timersize = (size == TIMER_SIZE_16BIT) ? BASE_CFG_UNSET : BASE_CFG_SET; +} + +/** + * @brief Set timer size + * @param timerx Timer register baseAddr + * @retval None + */ +static inline TIMER_Size DCL_TIMER_GetTimerSize(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_CONTROL.BIT.timersize; +} + +/** + * @brief Set the counting mode is single counting or periodic counting mode + * @param timerx Timer register baseAddr + * @param mode counter mode, see @ref TIMER_Mode + * @retval None + */ +static inline void DCL_TIMER_SetTimerMode(TIMER_RegStruct *timerx, TIMER_Mode mode) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + TIMER_PARAM_CHECK_NO_RET(IsTimerMode(mode)); + if (mode == TIMER_MODE_RUN_ONTSHOT) { + timerx->TIMERx_CONTROL.BIT.oneshot = BASE_CFG_SET; + } else { + timerx->TIMERx_CONTROL.BIT.oneshot = BASE_CFG_UNSET; + timerx->TIMERx_CONTROL.BIT.timermode = (mode == TIMER_MODE_RUN_FREE) ? BASE_CFG_UNSET : BASE_CFG_SET; + } +} + +/** + * @brief Get the counting mode is single counting or periodic counting mode + * @param timerx Timer register baseAddr + * @retval TIMER_Mode + */ +static inline TIMER_Mode DCL_TIMER_GetTimerMode(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + if (timerx->TIMERx_CONTROL.BIT.oneshot == BASE_CFG_SET) { + return TIMER_MODE_RUN_ONTSHOT; + } else { + return (timerx->TIMERx_CONTROL.BIT.timermode == BASE_CFG_SET) ? TIMER_MODE_RUN_PERIODIC : TIMER_MODE_RUN_FREE; + } +} + +/** + * @brief Set the prescaler factor of the timer + * @param timerx Timer register baseAddr + * @param factor prescaler factor, see @ref TIMER_PrescalerFactor + * @retval None + */ +static inline void DCL_TIMER_SetTimerPre(TIMER_RegStruct *timerx, TIMER_PrescalerFactor factor) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + TIMER_PARAM_CHECK_NO_RET(IsTimerDiv(factor)); + timerx->TIMERx_CONTROL.BIT.timerpre = factor; +} + +/** + * @brief Get the prescaler factor of the timer + * @param timerx Timer register baseAddr + * @retval TIMER_PrescalerFactor + */ +static inline TIMER_PrescalerFactor DCL_TIMER_GetTimerPre(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_CONTROL.BIT.timerpre; +} + +/** + * @brief Clear the time irq falg + * @param timerx Timer register baseAddr + * @retval None + */ +static inline void DCL_TIMER_IrqClear(TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->timer_intclr = BASE_CFG_SET; +} + +/** + * @brief Get Original interrupt state + * @param timerx Timer register baseAddr + * @retval bool + */ +static inline bool DCL_TIMER_GetTimerOriginalInterruptState(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_RIS.timerris; +} + +/** + * @brief Get the interrupt status of Timer after shielding + * @param timerx Timer register baseAddr + * @retval bool + */ +static inline bool DCL_TIMER_GetTimerShieldlInterruptState(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_MIS.timermis; +} + +/** + * @brief Get Timer Trigger ADC sample enable + * @param timerx Timer register baseAddr + * @retval bool + */ +static inline bool DCL_TIMER_GetTimerTriggerAdcRequest(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_CONTROLB.BIT.socen; +} + +/** + * @brief Set Timer Trigger ADC sample enable + * @param timerx Timer register baseAddr + * @retval None + */ +static inline void DCL_TIMER_SetTimerTriggerAdcRequest(TIMER_RegStruct *timerx, bool enable) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->TIMERx_CONTROLB.BIT.socen = enable; +} + +/** + * @brief Get DMA single request enable status + * @param timerx Timer register baseAddr + * @retval bool + */ +static inline bool DCL_TIMER_GetTimerDmaSingleRequest(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_CONTROLB.BIT.dmasreqen; +} + +/** + * @brief Set DMA single request + * @param timerx Timer register baseAddr + * @param enable DMA/ADC single trigger enable + * @retval None + */ +static inline void DCL_TIMER_SetTimerDmaSingleRequest(TIMER_RegStruct *timerx, bool enable) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->TIMERx_CONTROLB.BIT.dmasreqen = (unsigned int)enable; +} + +/** + * @brief Get DMA burst request enable status + * @param timerx Timer register baseAddr + * @retval bool + */ +static inline bool DCL_TIMER_GetTimerDmaBurstRequest(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_CONTROLB.BIT.dmabreqen; +} + +/** + * @brief Set DMA burst request + * @param timerx Timer register baseAddr + * @param enable DMA burst trigger enable + * @retval None + */ +static inline void DCL_TIMER_SetTimerDmaBurstRequest(TIMER_RegStruct *timerx, bool enable) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->TIMERx_CONTROLB.BIT.dmabreqen = (unsigned int)enable; +} + +/** + * @brief DMA request overflow interrupt enable + * @param timerx DMA Timer register baseAddr + * @retval None + */ +static inline void DCL_TIMER_DMAInterruptEnable(TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->TIMERx_CONTROL.BIT.dmaovintenable = BASE_CFG_SET; +} + +/** + * @brief Disabling the DMA overflow interrupt status + * @param timerx DMA Timer register baseAddr + * @retval None + */ +static inline void DCL_TIMER_DMAInterruptDisable(TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->TIMERx_CONTROL.BIT.dmaovintenable = BASE_CFG_UNSET; +} + +/** + * @brief DMA raw interrupt overflow flag + * @param timerx DMA Timer register baseAddr + * @retval bool + */ +static inline bool DCL_TIMER_GetDMAOriginalInterruptState(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_RIS.dmaovris; +} + +/** + * @brief Interrupt flag after DMA masking + * @param timerx Timer register baseAddr + * @retval bool + */ +static inline bool DCL_TIMER_GetTimerDMAShieldlInterruptState(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_MIS.dmaovmis; +} + +/** + * @brief Clears the DMA overflow interrupt flag. + * @param timerx Timer register baseAddr + * @retval None + */ +static inline void DCL_TIMER_DMAIrqClear(TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->DMAOV_INTCLR.BIT.dmaov_intclr = BASE_CFG_SET; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_TIMER_IP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/timer/src/timer.c b/vendor/xinlingyu_92_3061M/Project/drivers/timer/src/timer.c new file mode 100644 index 0000000000000000000000000000000000000000..2c74e91bb744957317245ebb54a024c02ffac35e --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/timer/src/timer.c @@ -0,0 +1,290 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file timer.c + * @author MCU Driver Team + * @brief TIMER module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the TIMER. + * + Initialization and de-initialization functions + * + config the register of timer + */ + +/* Includes ------------------------------------------------------------------*/ +#include "timer.h" +#include "timer_ex.h" +#include "interrupt.h" + +/** + * @brief Init the timer + * @param handle Timer Handle + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR parameter check fail + */ +BASE_StatusType HAL_TIMER_Init(TIMER_Handle *handle) +{ + TIMER_ASSERT_PARAM(handle != NULL); + TIMER_ASSERT_PARAM(IsTIMERInstance(handle->baseAddress)); + + TIMER_PARAM_CHECK_WITH_RET(IsTimerPeriod(handle->load), BASE_STATUS_ERROR); + TIMER_PARAM_CHECK_WITH_RET(IsTimerPeriod(handle->bgLoad), BASE_STATUS_ERROR); + TIMER_PARAM_CHECK_WITH_RET(IsTimerMode(handle->mode), BASE_STATUS_ERROR); + TIMER_PARAM_CHECK_WITH_RET(IsTimerSize(handle->size), BASE_STATUS_ERROR); + TIMER_PARAM_CHECK_WITH_RET(IsTimerDiv(handle->prescaler), BASE_STATUS_ERROR); + + /* Initialize the configuration parameters of the timer */ + handle->baseAddress->timer_intclr = BASE_CFG_SET; /* Writing to this register clears interrupt output of timer */ + handle->baseAddress->timer_load = handle->load; + handle->baseAddress->timerbgload = handle->bgLoad; + handle->baseAddress->TIMERx_CONTROL.BIT.timeren = BASE_CFG_DISABLE; + handle->baseAddress->TIMERx_CONTROL.BIT.timerintenable = handle->interruptEn; + + /* Sets the frequency divider and size of the timer module. */ + handle->baseAddress->TIMERx_CONTROL.BIT.timerpre = handle->prescaler; + handle->baseAddress->TIMERx_CONTROL.BIT.timersize = handle->size; + + /* Sets the running mode of the timer. */ + if (handle->mode == TIMER_MODE_RUN_ONTSHOT) { + handle->baseAddress->TIMERx_CONTROL.BIT.oneshot = BASE_CFG_SET; + } else { + handle->baseAddress->TIMERx_CONTROL.BIT.oneshot = BASE_CFG_UNSET; + handle->baseAddress->TIMERx_CONTROL.BIT.timermode = + (handle->mode == TIMER_MODE_RUN_FREE) ? BASE_CFG_UNSET : BASE_CFG_SET; + } + + /* Request for setting the DMA and ADC. */ + handle->baseAddress->TIMERx_CONTROLB.BIT.dmasreqen = handle->dmaReqEnable; + handle->baseAddress->TIMERx_CONTROLB.BIT.dmabreqen = handle->dmaReqEnable; + handle->baseAddress->TIMERx_CONTROLB.BIT.socen = handle->adcSocReqEnable; + return BASE_STATUS_OK; +} + +/** + * @brief DeInit the timer + * @param handle Timer Handle + * @retval None + */ +void HAL_TIMER_DeInit(TIMER_Handle *handle) +{ + TIMER_ASSERT_PARAM(handle != NULL); + TIMER_ASSERT_PARAM(IsTIMERInstance(handle->baseAddress)); + + /* Clears interrupts and masks interrupts. */ + handle->baseAddress->timer_intclr = BASE_CFG_SET; + handle->baseAddress->TIMERx_CONTROL.BIT.timerintenable = BASE_CFG_DISABLE; + handle->userCallBack.TimerPeriodFinCallBack = NULL; /* Clear all user call back function. */ + handle->userCallBack.TimerOverFlowCallBack = NULL; + /* The counter loading value is set to 0, and the timer is disabled. */ + handle->baseAddress->timer_load = 0; + handle->baseAddress->timerbgload = 0; + handle->baseAddress->TIMERx_CONTROL.reg = 0; + handle->baseAddress->TIMERx_CONTROLB.reg = 0; +} + +/** + * @brief Config Timer + * @param handle Timer Handle + * @param cfgType Timer configures, @ref TIMER_CFG_TYPE + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Parameter check fail + */ +BASE_StatusType HAL_TIMER_Config(TIMER_Handle *handle, TIMER_CFG_TYPE cfgType) +{ + TIMER_ASSERT_PARAM(handle != NULL); + TIMER_ASSERT_PARAM(IsTIMERInstance(handle->baseAddress)); + + /* Configure related registers based on the configuration type. */ + switch (cfgType) { + /* Configure timer count. */ + case TIMER_CFG_LOAD: + TIMER_PARAM_CHECK_WITH_RET(IsTimerPeriod(handle->load), BASE_STATUS_ERROR); + handle->baseAddress->timer_load = handle->load; + handle->bgLoad = handle->load; + break; + /* Configure timer reload count. */ + case TIMER_CFG_BGLOAD: + TIMER_PARAM_CHECK_WITH_RET(IsTimerPeriod(handle->bgLoad), BASE_STATUS_ERROR); + handle->baseAddress->timerbgload = handle->bgLoad; + break; + /* Configure timer work mode. */ + case TIMER_CFG_MODE: + DCL_TIMER_SetTimerMode(handle->baseAddress, handle->mode); + break; + /* Configure timer interrupt. */ + case TIMER_CFG_INTERRUPT: + handle->baseAddress->TIMERx_CONTROL.BIT.timerintenable = handle->interruptEn; + break; + /* Configure timer prescaler. */ + case TIMER_CFG_PRESCALER: + TIMER_PARAM_CHECK_WITH_RET(IsTimerDiv(handle->prescaler), BASE_STATUS_ERROR); + handle->baseAddress->TIMERx_CONTROL.BIT.timerpre = handle->prescaler; + break; + /* Configure the size of the timer counter. */ + case TIMER_CFG_SIZE: + TIMER_PARAM_CHECK_WITH_RET(IsTimerSize(handle->size), BASE_STATUS_ERROR); + handle->baseAddress->TIMERx_CONTROL.BIT.timersize = handle->size; + break; + /* Configure the DMA request. */ + case TIMER_CFG_DMA_REQ: + handle->baseAddress->TIMERx_CONTROLB.BIT.dmasreqen = handle->dmaReqEnable; + break; + /* Configure the ADC request. */ + case TIMER_CFG_ADC_REQ: + handle->baseAddress->TIMERx_CONTROLB.BIT.socen = handle->adcSocReqEnable; + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief Get Timer Config + * @param handle Timer Handle + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Parameter check fail + */ +BASE_StatusType HAL_TIMER_GetConfig(TIMER_Handle *handle) +{ + TIMER_ASSERT_PARAM(handle != NULL); + TIMER_ASSERT_PARAM(IsTIMERInstance(handle->baseAddress)); + + /* Obtain the parameters in the timer handle. */ + handle->load = handle->baseAddress->timer_load; + handle->bgLoad = handle->baseAddress->timerbgload; + handle->mode = handle->baseAddress->TIMERx_CONTROL.BIT.timermode; + handle->size = handle->baseAddress->TIMERx_CONTROL.BIT.timersize; + handle->prescaler = handle->baseAddress->TIMERx_CONTROL.BIT.timerpre; + handle->interruptEn = handle->baseAddress->TIMERx_CONTROL.BIT.timerintenable; + handle->dmaReqEnable = handle->baseAddress->TIMERx_CONTROLB.BIT.dmasreqen || + handle->baseAddress->TIMERx_CONTROLB.BIT.dmabreqen; + handle->adcSocReqEnable = handle->baseAddress->TIMERx_CONTROLB.BIT.socen; + handle->mode = DCL_TIMER_GetTimerMode(handle->baseAddress); + + return BASE_STATUS_OK; +} + +/** + * @brief Start timer. + * @param handle Timer Handle + * @retval None + */ +void HAL_TIMER_Start(TIMER_Handle *handle) +{ + TIMER_ASSERT_PARAM(handle != NULL); + TIMER_ASSERT_PARAM(IsTIMERInstance(handle->baseAddress)); + /* Enable timer */ + handle->baseAddress->TIMERx_CONTROL.BIT.timeren = BASE_CFG_SET; +} + +/** + * @brief Stop timer. + * @param handle Timer Handle + * @retval None + * @note Timer in OneShot Mode also need stop + */ +void HAL_TIMER_Stop(TIMER_Handle *handle) +{ + TIMER_ASSERT_PARAM(handle != NULL); + TIMER_ASSERT_PARAM(IsTIMERInstance(handle->baseAddress)); + /* Disables the timer. */ + handle->baseAddress->TIMERx_CONTROL.BIT.timeren = BASE_CFG_UNSET; + handle->baseAddress->timer_intclr = BASE_CFG_SET; +} + +/** + * @brief GPT Interrupt service processing function. + * @param handle TIMER Handle + * @retval None + */ +void HAL_TIMER_IrqHandler(void *handle) +{ + TIMER_ASSERT_PARAM(handle != NULL); + TIMER_Handle *timerHandle = (TIMER_Handle *)handle; + TIMER_ASSERT_PARAM(IsTIMERInstance(timerHandle->baseAddress)); + /* Check interrupt type */ + if (timerHandle->baseAddress->TIMERx_MIS.dmaovmis == BASE_CFG_ENABLE) { + /* DMA overflow interrupt */ + timerHandle->baseAddress->DMAOV_INTCLR.BIT.dmaov_intclr = BASE_CFG_ENABLE; + /* Call the timer DMA request overflow callback function of the user. */ + if (timerHandle->userCallBack.TimerOverFlowCallBack != NULL) { + timerHandle->userCallBack.TimerOverFlowCallBack(timerHandle); + } + } + if (timerHandle->baseAddress->TIMERx_MIS.timermis == BASE_CFG_ENABLE) { + /* TIMER Interrupt */ + timerHandle->baseAddress->timer_intclr = BASE_CFG_ENABLE; + /* Call the period finish callback function of the user. */ + if (timerHandle->userCallBack.TimerPeriodFinCallBack != NULL) { + timerHandle->userCallBack.TimerPeriodFinCallBack(timerHandle); + } + } + return; +} + +/** + * @brief Register the callback function of TIMER handle. + * @param handle Timer Handle + * @param typeID CallBack function type of user, @ref TIMER_InterruptType + * @param callBackFunc CallBack function of user, @ref TIMER_CallBackFunc + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Parameter check fail + */ +BASE_StatusType HAL_TIMER_RegisterCallback(TIMER_Handle *handle, TIMER_InterruptType typeID, + TIMER_CallBackFunc callBackFunc) +{ + TIMER_ASSERT_PARAM(handle != NULL); + TIMER_ASSERT_PARAM(callBackFunc != NULL); + TIMER_ASSERT_PARAM(IsTimerInterruptType(typeID)); + + /* Registers the user callback function. */ + switch (typeID) { + case TIMER_OVER_FLOW: + handle->userCallBack.TimerOverFlowCallBack = callBackFunc; /* User DMA request overflow function */ + break; + case TIMER_PERIOD_FIN: + handle->userCallBack.TimerPeriodFinCallBack = callBackFunc; /* User timer period finish call back. */ + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief Unregister the callback function of TIMER handle. + * @param handle Timer Handle + * @param typeID CallBack function of user, @ref TIMER_InterruptType + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Parameter check fail + */ +BASE_StatusType HAL_TIMER_UnRegisterCallback(TIMER_Handle *handle, TIMER_InterruptType typeID) +{ + TIMER_ASSERT_PARAM(handle != NULL); + /* Determine the callback function type. */ + switch (typeID) { + case TIMER_PERIOD_FIN: + handle->userCallBack.TimerPeriodFinCallBack = NULL; /* Periodic callback for timer period finish. */ + break; + case TIMER_OVER_FLOW: + handle->userCallBack.TimerOverFlowCallBack = NULL; /* Periodic callback for timer DMA over flow. */ + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/timer/src/timer_ex.c b/vendor/xinlingyu_92_3061M/Project/drivers/timer/src/timer_ex.c new file mode 100644 index 0000000000000000000000000000000000000000..b74d4bfe4d44b220a0da2fa3431cff4bb61f00bf --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/timer/src/timer_ex.c @@ -0,0 +1,57 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file timer_ex.c + * @author MCU Driver Team + * @brief TIMER module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the TIMER. + * + Implementation of extended functions of the timer module + */ + +#include "timer_ex.h" + +/** + * @brief Setting DMA request overflow interrupt. + * @param handle Timer Handle + * @param bool enable or disable interrupt of DMA request overflow. + * @retval None + */ +void HAL_TIMER_DMARequestOverFlowEx(TIMER_Handle *handle, bool overFlowSet) +{ + TIMER_ASSERT_PARAM(handle != NULL); + TIMER_ASSERT_PARAM(IsTIMERInstance(handle->baseAddress)); + handle->baseAddress->TIMERx_CONTROL.BIT.dmaovintenable = overFlowSet; + return; +} + +/** + * @brief Timer Trigger ADC Set + * @param handle Timer Handle + * @param enable 0: disable 1: enable + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Parameter check fail + */ +BASE_StatusType HAL_TIMER_TriggerAdcEx(TIMER_Handle *handle, bool enable) +{ + TIMER_ASSERT_PARAM(handle != NULL); + TIMER_ASSERT_PARAM(IsTIMERInstance(handle->baseAddress)); + + handle->baseAddress->TIMERx_CONTROLB.BIT.socen = enable; + + return BASE_STATUS_OK; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/tsensor/common/inc/tsensor.h b/vendor/xinlingyu_92_3061M/Project/drivers/tsensor/common/inc/tsensor.h new file mode 100644 index 0000000000000000000000000000000000000000..754e7791a0f60657affb38c471deaae8284b8b39 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/tsensor/common/inc/tsensor.h @@ -0,0 +1,53 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file tsensor.h + * @author MCU Driver Team + * @brief tsensor module driver + * @details This file provides API to manage tsensor. + */ + +/* Macro definitions */ +#ifndef McuMagicTag_TSENSOR_H +#define McuMagicTag_TSENSOR_H + +#include "tsensor_ip.h" + +/** + * @defgroup TSENSOR TSENSOR + * @brief TSENSOR module. + * @{ + */ + +/** + * @defgroup TSENSOR_Common TSENSOR Common + * @brief TSENSOR common external module. + * @{ + */ + +void HAL_TSENSOR_Init(void); +void HAL_TSENSOR_Deinit(void); +unsigned int HAL_TSENSOR_GetResult(void); +float HAL_TSENSOR_GetTemperature(void); +/** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/tsensor/inc/tsensor_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/tsensor/inc/tsensor_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..2b6c7e49f6978fa2de123a61e2777f7ed7c3a3a1 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/tsensor/inc/tsensor_ip.h @@ -0,0 +1,80 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file tsensor_ip.h + * @author MCU Driver Team + * @brief tsensor module driver + * @details This file provides dcl functions to manage tsensor and definition of + * specific parameters. + */ + +/* Macro definitions */ +#ifndef McuMagicTag_TSENSOR_IP_H +#define McuMagicTag_TSENSOR_IP_H + +#include "baseinc.h" + +/** + * @addtogroup TSENSOR + * @{ + */ + +/** + * @defgroup TSENSOR_IP TSENSOR_IP + * @brief TSENSOR_IP: tsensor_v1. + * @{ + */ + +/** + * @brief Define the union TSENSOR_CTRL_REG. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_tsensor_pd : 1; /* Enable switch bit */ + unsigned int reserved0 : 31; + } BIT; +} volatile TSENSOR_CTRL_REG; + +/** + * @brief Define the union TSENSOR_TRIM_REG. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfg_tsensor_trim : 8; /* trim infomation */ + unsigned int reserved0 : 24; + } BIT; +} volatile TSENSOR_TRIM_REG; + +/** + * @brief Define the tsensor resistor struct. + */ +typedef struct { + TSENSOR_CTRL_REG TSENSOR_CTRL; /**< Offset address: 0x00000000U */ + unsigned char space0[12]; + TSENSOR_TRIM_REG TSENSOR_TRIM; /**< Offset address: 0x00000010U */ +} volatile TSENSOR_RegStruct; + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_TSENSOR_IP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/tsensor/src/tsensor.c b/vendor/xinlingyu_92_3061M/Project/drivers/tsensor/src/tsensor.c new file mode 100644 index 0000000000000000000000000000000000000000..65966092dcc82ca23c6d7fd6af8005ba43f2ca5c --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/tsensor/src/tsensor.c @@ -0,0 +1,152 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file tsensor.c + * @author MCU Driver Team + * @brief tsensor module driver + * @details This file provides functions to manage tsensor and definition of + * specific parameters. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "crg.h" +#include "adc.h" +#include "fotp_info_read.h" +#include "anatrim.h" +#include "tsensor.h" + +#define NUM 16 +#define TSENSOR_SOC_NUM ADC_SOC_NUM15 /* This parameter can be modified according to the actual situation */ + +/** + * @brief ADC for tsensor clock initialization. + * @param None. + * @retval None. + */ +static void ADC_ClkEnable(void) +{ + unsigned int status = BASE_CFG_UNSET; + HAL_CRG_IpEnableGet(ADC0_BASE, &status); /* Check whether the ADC clock is enabled */ + if (status != IP_CLK_ENABLE) { + HAL_CRG_IpEnableSet(ADC0_BASE, IP_CLK_ENABLE); + HAL_CRG_IpClkSelectSet(ADC0_BASE, CRG_ADC_CLK_ASYN_PLL_DIV); + HAL_CRG_IpClkDivSet(ADC0_BASE, CRG_ADC_DIV_2); + } +} + +/** + * @brief ADC for tsensor sample configuration. + * @param None. + * @retval None. + */ +static void TSENSOR_SampleConfigure(void) +{ + ADC_Handle adcHandle = {0}; + adcHandle.baseAddress = ADC0; + adcHandle.socPriority = ADC_PRIMODE_ALL_ROUND; + HAL_ADC_Init(&adcHandle); /* ADC ADC initialization */ + + SOC_Param socParam = {0}; + socParam.adcInput = ADC_CH_ADCINA16; + socParam.sampleTotalTime = ADC_SOCSAMPLE_5CLK; + socParam.trigSource = ADC_TRIGSOC_SOFT; + socParam.continueMode = BASE_CFG_DISABLE; + socParam.finishMode = ADC_SOCFINISH_NONE; + unsigned int soc = TSENSOR_SOC_NUM; + HAL_ADC_ConfigureSoc(&adcHandle, soc, &socParam); /* ADC_CH_ADCINA16 Sampling Configuration */ + + TSENSOR_RegStruct *tsensor; + tsensor = TSENSOR; + tsensor->TSENSOR_CTRL.BIT.cfg_tsensor_pd = 0x0; + BASE_FUNC_DELAY_US(40); /* waite for 40us until stable */ +} + +/** + * @brief ADC Results Converted to Temperature. + * @param digital digital parameter of tsensor. + * @retval Temperature type: float, temperature of MCU, unit: ℃. + */ +static float TSENSOR_Conversion(unsigned int digital) +{ + float curV = ((float)digital / 4096.0f) * 3.3f; /* 4096.0 and 3.3 for voltage conversion */ + /* 1.228f and 25.0f are used as parameters to calculate result */ + float curTemp = (curV - 1.228f) / g_tsensorGain + 25.0f; + return curTemp; +} + +/** + * @brief Configuration of tsensor. + * @param None. + * @retval None. + */ +void HAL_TSENSOR_Init(void) +{ + ADC_ClkEnable(); + TSENSOR_SampleConfigure(); +} + +/** + * @brief Deinitialize of tsensor. + * @param None. + * @retval None. + */ +void HAL_TSENSOR_Deinit(void) +{ + TSENSOR_RegStruct *tsensor; + tsensor = TSENSOR; + tsensor->TSENSOR_CTRL.BIT.cfg_tsensor_pd = 0x1; +} + + +/** + * @brief Get the result from the tsensor. + * @param None. + * @retval result of tsensor. + */ +unsigned int HAL_TSENSOR_GetResult(void) +{ + unsigned int ret = 0; + unsigned int count = 0; + for (unsigned int i = 0; i < NUM; i++) { + unsigned int socRet; + DCL_ADC_SOCxSoftTrigger(ADC0, TSENSOR_SOC_NUM); + BASE_FUNC_DELAY_MS(1); /* waite for 1ms until conversion finish */ + DCL_ADC_GetConvState(ADC0, TSENSOR_SOC_NUM); + if (DCL_ADC_GetConvState(ADC0, TSENSOR_SOC_NUM) != BASE_CFG_UNSET) { + socRet = DCL_ADC_ReadSOCxResult(ADC0, TSENSOR_SOC_NUM); + ret += socRet; + count++; + DCL_ADC_ResetConvState(ADC0, TSENSOR_SOC_NUM); /* Set the sampling completion flag */ + } + } + if (count == 0) { + return 0xFFF; + } + return (ret / count); /* Average the results */ +} + +/** + * @brief Get the temperature from the tsensor. + * @param None. + * @retval Temperature type: float, temperature of MCU, unit: ℃. + */ +float HAL_TSENSOR_GetTemperature(void) +{ + unsigned int result = HAL_TSENSOR_GetResult(); + float temp = TSENSOR_Conversion(result); + return temp; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/uart/common/inc/uart.h b/vendor/xinlingyu_92_3061M/Project/drivers/uart/common/inc/uart.h new file mode 100644 index 0000000000000000000000000000000000000000..a80401c9f83fd517f814fac25f728e77c19e489e --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/uart/common/inc/uart.h @@ -0,0 +1,134 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file uart.h + * @author MCU Driver Team + * @brief UART module driver. + * @details This file provides functions declaration of the UART, + * + Initialization and de-initialization functions + * + Peripheral querying the state functions. + * + Peripheral transmit and abort functions. + * + Peripheral interrupt service and callback registration functions. + * This file also provides the definition of the UART handle structure. + */ + +/* Includes ------------------------------------------------------------------*/ +#ifndef McuMagicTag_UART_H +#define McuMagicTag_UART_H + +#include "uart_ip.h" +#include "dma.h" + +/** + * @defgroup UART UART + * @brief UART module. + * @{ + */ + +/** + * @defgroup UART_Common UART Common + * @brief UART common external module. + * @{ + */ + +/** + * @defgroup UART_Handle_Definition UART Handle Definition + * @{ + */ + +/** + * @brief The definition of the UART handle structure. + */ +typedef struct _UART_Handle { + UART_RegStruct *baseAddress; /**< UART registers base address */ + unsigned int baudRate; /**< UART communication baud rate */ + UART_DataLength dataLength; /**< The length of UART frame */ + UART_StopBits stopBits; /**< The stop bit of UART frame */ + UART_Parity_Mode parity; /**< The parity bit of UART frame */ + UART_Transmit_Mode txMode; /**< Tx transmit mode setting */ + UART_Transmit_Mode rxMode; /**< tx transmit mode setting */ + volatile unsigned char *txbuff; /**< Start address of tx */ + volatile unsigned char *rxbuff; /**< Start address of rx */ + volatile unsigned int txBuffSize; /**< The length of tx buff */ + volatile unsigned int rxBuffSize; /**< The length of rx buff */ + bool fifoMode; /**< The FIFO mode */ + UART_FIFO_Threshold fifoTxThr; /**< Interrupt threshold of tx FIFO */ + UART_FIFO_Threshold fifoRxThr; /**< Interrupt threshold of rx FIFO */ + UART_HW_FlowCtr hwFlowCtr; /**< UART hardware flow control */ + DMA_Handle *dmaHandle; /**< UART_DMA control */ + unsigned int uartDmaTxChn; /**< UART_DMA tx channel */ + unsigned int uartDmaRxChn; /**< UART_DMA rx channel */ + volatile UART_State_Type txState; /**< The tx status of UART */ + volatile UART_State_Type rxState; /**< The rx status of UART */ + UART_Error_Type errorType; /**< The error of UART */ + + UART_UserCallBack userCallBack; /**< User callback function of UART. */ + UART_ExtendHandle handleEx; /**< UART extend handle. */ +} UART_Handle; + +typedef void (* UART_CallbackType)(void *handle); +/** + * @} + */ + +/** + * @defgroup UART_API_Declaration UART HAL API + * @{ + */ +/* Peripheral initialization and deinitialize functions */ +BASE_StatusType HAL_UART_Init(UART_Handle *uartHandle); +BASE_StatusType HAL_UART_DeInit(UART_Handle *uartHandle); + +/* Peripheral querying the state functions */ +UART_State_Type HAL_UART_GetState(UART_Handle *uartHandle); + +/* Peripheral transmit and abort functions */ +BASE_StatusType HAL_UART_WriteBlocking(UART_Handle *uartHandle, unsigned char *srcData, + unsigned int dataLength, unsigned int blockingTime); +BASE_StatusType HAL_UART_WriteIT(UART_Handle *uartHandle, unsigned char *srcData, unsigned int dataLength); +BASE_StatusType HAL_UART_WriteDMA(UART_Handle *uartHandle, unsigned char *srcData, + unsigned int dataLength); +BASE_StatusType HAL_UART_ReadBlocking(UART_Handle *uartHandle, unsigned char *saveData, + unsigned int dataLength, unsigned int blockingTime); +BASE_StatusType HAL_UART_ReadIT(UART_Handle *uartHandle, unsigned char *saveData, unsigned int dataLength); +BASE_StatusType HAL_UART_ReadDMA(UART_Handle *uartHandle, unsigned char *saveData, + unsigned int dataLength); +BASE_StatusType HAL_UART_StopRead(UART_Handle *uartHandle); +BASE_StatusType HAL_UART_StopWrite(UART_Handle *uartHandle); + +/* brief Peripheral interrupt service and callback registration functions */ +void HAL_UART_IrqHandler(void *handle); +BASE_StatusType HAL_UART_RegisterCallBack(UART_Handle *uartHandle, UART_CallbackFun_Type typeID, + UART_CallbackType pCallback); + +/* UART read using DMA cyclically stored function */ +BASE_StatusType HAL_UART_ReadDMAAndCyclicallyStored(UART_Handle *uartHandle, unsigned char *saveData, + DMA_LinkList *tempNode, unsigned int dataLength); +unsigned int HAL_UART_ReadDMAGetPos(UART_Handle *uartHandle); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_UART_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/uart/inc/uart_ex.h b/vendor/xinlingyu_92_3061M/Project/drivers/uart/inc/uart_ex.h new file mode 100644 index 0000000000000000000000000000000000000000..12219f09247bfd202a8a32923a882518c3a5cc46 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/uart/inc/uart_ex.h @@ -0,0 +1,65 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file uart_ex.h + * @author MCU Driver Team + * @brief UART module driver. + * @details This file provides functions declaration of the UART, + * + Initialization and de-initialization functions + * + Peripheral querying the state functions. + * + Peripheral transmit and abort functions. + * + Peripheral interrupt service and callback registration functions. + * This file also provides the definition of the UART handle structure. + */ + +/* Includes ------------------------------------------------------------------*/ +#ifndef McuMagicTag_UART_EX_H +#define McuMagicTag_UART_EX_H + +#include "uart.h" + +/** + * @addtogroup UART_IP + * @{ + */ + +/** + * @defgroup UART_EX_API_Declaration UART HAL API EX + * @{ + */ +BASE_StatusType HAL_UART_OpenCharacterMatchEx(UART_Handle *uartHandle, unsigned char ch); + +BASE_StatusType HAL_UART_CloseCharacterMatchEx(UART_Handle *uartHandle); + +BASE_StatusType HAL_UART_EnableBaudDetectionEx(UART_Handle *uartHandle); + +BASE_StatusType HAL_UART_DisableBaudDetectionEx(UART_Handle *uartHandle); + +BASE_StatusType HAL_UART_SetRxWaiteTimeEx(UART_Handle *uartHandle, unsigned int cntOfBit); + +BASE_StatusType HAL_UART_SetOversampleMultipleEx(UART_Handle *uartHandle, UART_OversampleMultiple multiple); + +BASE_StatusType HAL_UART_SetDataSequenceModeEx(UART_Handle *uartHandle, UART_SequenceMode mode); + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_UART_EX_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/uart/inc/uart_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/uart/inc/uart_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..006cdaf3badeffe52ef7249961682999e301ab27 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/uart/inc/uart_ip.h @@ -0,0 +1,1118 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file uart_ip.h + * @author MCU Driver Team + * @brief UART module driver + * @details This file provides DCL functions to manage UART and Definition of + * specific parameters. + * + Definition of UART configuration parameters. + * + UART register mapping structure. + * + Parameters check functions. + * + Direct configuration layer interface. + */ + +/* Macro definitions */ +#ifndef McuMagicTag_UART_IP_H +#define McuMagicTag_UART_IP_H + +#include "baseinc.h" + +#ifdef UART_PARAM_CHECK +#define UART_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define UART_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define UART_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define UART_ASSERT_PARAM(para) ((void)0U) +#define UART_PARAM_CHECK_NO_RET(para) ((void)0U) +#define UART_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +#define UART_FIFOFULL_ONE_TWO 0x0000000FU +#define UART_FIFOFULL_ONE_EIGHT 0x00000008U + +/** + * @addtogroup UART + * @{ + */ + +/** + * @defgroup UART_IP UART_IP + * @brief UART_IP: uart_v1 + * @{ + */ + +/** + * @defgroup UART_Param_Def UART Parameters Definition + * @brief Definition of UART configuration parameters. + * @{ + */ + +/** + * @brief UART def of oversampling + */ +typedef enum { + UART_OVERSAMPLING_16X = 0x00000000U, + UART_OVERSAMPLING_15X = 0x00000001U, + UART_OVERSAMPLING_14X = 0x00000002U, + UART_OVERSAMPLING_13X = 0x00000003U, + UART_OVERSAMPLING_12X = 0x00000004U, +} UART_OversampleMultiple; + +/** + * @brief Extent handle definition of UART + */ +typedef struct { + UART_OversampleMultiple overSampleMultiple; /**< Oversampling multiplier */ + bool msbFirst; /**< Configures data transmission sequence */ +} UART_ExtendHandle; + +/** + * @brief Type ID of callback function registered by the user. + */ +typedef enum { + UART_WRITE_IT_FINISH = 0x00000000U, + UART_READ_IT_FINISH = 0x00000001U, + UART_WRITE_DMA_FINISH = 0x00000002U, + UART_READ_DMA_FINISH = 0x00000003U, + UART_TRNS_IT_ERROR = 0x00000004U, + UART_TRNS_DMA_ERROR = 0x00000005U, + UART_BAUD_DETECT_FINISH = 0x00000006U, + UART_BAUD_DETECT_ERROR = 0x00000007U, + UART_CHARACTER_MATCH = 0x00000008U +} UART_CallbackFun_Type; + +/** + * @brief User Callback Function Definition + */ +typedef struct { + void (* WriteItFinishCallBack)(void *handle); /**< UART tx interrupt complete callback + function for users */ + void (* ReadItFinishCallBack)(void *handle); /**< UART rx interrupt complete callback + function for users */ + void (* WriteDmaFinishCallBack)(void *handle); /**< UART tx DMA complete callback function + for users */ + void (* ReadDmaFinishCallBack)(void *handle); /**< UART rx DMA complete callback function + for users */ + void (* TransmitItErrorCallBack)(void *handle); /**< UART interrupt mode error callback + function for users */ + void (* TransmitDmaErrorCallBack)(void *handle); /**< UART interrupt mode error callback + function for users */ + void (* BaudDetectSuccessCallBack)(void *handle); /**< Callback function for successful + UART baud rate detection */ + void (* BaudDetectErrorCallBack)(void *handle); /**< UART baud rate detection failure + callback function */ + void (* CharacterMatchCallBack)(void *handle); /**< UART character matching callback + function. */ +}UART_UserCallBack; + +/** + * @brief Type of error callback functuions. + */ +typedef enum { + UART_ERROR_FRAME = 0x00000080U, + UART_ERROR_PARITY = 0x00000100U, + UART_ERROR_BREAK = 0x00000200U, + UART_ERROR_OVERFLOW = 0x00000400U +} UART_Error_Type; + +/** + * @brief The number of data bits transmitted or received in a frame. + */ +typedef enum { + UART_DATALENGTH_5BIT = 0x00000000U, + UART_DATALENGTH_6BIT = 0x00000001U, + UART_DATALENGTH_7BIT = 0x00000002U, + UART_DATALENGTH_8BIT = 0x00000003U +} UART_DataLength; + +/** + * @brief UART parity mode. + * @details parity mode: + * + UART_PARITY_ODD -- odd check + * + UART_PARITY_EVEN -- even check + * + UART_PARITY_NONE -- none odd or even check + * + UART_PARITY_MARK -- mark check + * + UART_PARITY_SPACE -- space check + */ +typedef enum { + UART_PARITY_ODD = 0x00000000U, + UART_PARITY_EVEN = 0x00000001U, + UART_PARITY_MARK = 0x00000002U, + UART_PARITY_SPACE = 0x00000003U, + UART_PARITY_NONE = 0x00000004U +} UART_Parity_Mode; + +/** + * @brief Stop bit setting. + * @details Stop bit type: + * + UART_STOPBITS_ONE -- frame with one stop bit + * + UART_STOPBITS_TWO -- frame with two stop bits + */ +typedef enum { + UART_STOPBITS_ONE = 0x00000000U, + UART_STOPBITS_TWO = 0x00000001U +} UART_StopBits; + +/** + * @brief Three transmit mode: blocking, DMA, interrupt. + */ +typedef enum { + UART_MODE_BLOCKING = 0x00000000U, + UART_MODE_INTERRUPT = 0x00000001U, + UART_MODE_DMA = 0x00000002U, + UART_MODE_DISABLE = 0x00000003U +} UART_Transmit_Mode; + +/** + * @brief Hardware flow control mode disable/enable. + */ +typedef enum { + UART_HW_FLOWCTR_DISABLE = 0x00000000U, + UART_HW_FLOWCTR_ENABLE = 0x00000001U +} UART_HW_FlowCtr; + +/** + * @brief UART running status: deinit, ready, busy, busy(TX), busy(RX). + */ +typedef enum { + UART_STATE_NONE_INIT = 0x00000000U, + UART_STATE_READY = 0x00000001U, + UART_STATE_BUSY = 0x00000002U, + UART_STATE_BUSY_TX = 0x00000003U, + UART_STATE_BUSY_RX = 0x00000004U, +} UART_State_Type; + +/** + * @brief UART RX/TX FIFO line interrupt threshold. An interrupt is triggered when the received or discovered data + * crosses the FIFO threshold. + * @details Description: + * + UART_FIFODEPTH_SIZE0 -- rxFIFO >= 0 Bytes, txFIFO <= 0 Bytes + * + UART_FIFODEPTH_SIZE1 -- rxFIFO >= 1 Bytes, txFIFO <= 1 Bytes + * + UART_FIFODEPTH_SIZE2 -- rxFIFO >= 2 Bytes, txFIFO <= 2 Bytes + * + UART_FIFODEPTH_SIZE3 -- rxFIFO >= 3 Bytes, txFIFO <= 3 Bytes + * + UART_FIFODEPTH_SIZE4 -- rxFIFO >= 4 Bytes, txFIFO <= 4 Bytes + * + UART_FIFODEPTH_SIZE5 -- rxFIFO >= 5 Bytes, txFIFO <= 5 Bytes + * + UART_FIFODEPTH_SIZE6 -- txFIFO <= 6 Bytes, txFIFO <= 6 Bytes + * + UART_FIFODEPTH_SIZE7 -- txFIFO <= 7 Bytes, txFIFO <= 7 Bytes + * + UART_FIFODEPTH_SIZE8 -- txFIFO <= 8 Bytes, txFIFO <= 8 Bytes + * + UART_FIFODEPTH_SIZE9 -- txFIFO <= 9 Bytes, txFIFO <= 9 Bytes + * + UART_FIFODEPTH_SIZE10 -- txFIFO <= 10 Bytes, txFIFO <= 10 Bytes + * + UART_FIFODEPTH_SIZE11 -- txFIFO <= 11 Bytes, txFIFO <= 11 Bytes + * + UART_FIFODEPTH_SIZE12 -- txFIFO <= 12 Bytes, txFIFO <= 12 Bytes + * + UART_FIFODEPTH_SIZE13 -- txFIFO <= 13 Bytes, txFIFO <= 13 Bytes + * + UART_FIFODEPTH_SIZE14 -- txFIFO <= 14 Bytes, txFIFO <= 14 Bytes + * + UART_FIFODEPTH_SIZE15 -- txFIFO <= 15 Bytes, txFIFO <= 15 Bytes + */ +typedef enum { + UART_FIFODEPTH_SIZE0 = 0x00000000U, + UART_FIFODEPTH_SIZE1 = 0x00000001U, + UART_FIFODEPTH_SIZE2 = 0x00000002U, + UART_FIFODEPTH_SIZE3 = 0x00000003U, + UART_FIFODEPTH_SIZE4 = 0x00000004U, + UART_FIFODEPTH_SIZE5 = 0x00000005U, + UART_FIFODEPTH_SIZE6 = 0x00000006U, + UART_FIFODEPTH_SIZE7 = 0x00000007U, + UART_FIFODEPTH_SIZE8 = 0x00000008U, + UART_FIFODEPTH_SIZE9 = 0x00000009U, + UART_FIFODEPTH_SIZE10 = 0x0000000AU, + UART_FIFODEPTH_SIZE11 = 0x0000000BU, + UART_FIFODEPTH_SIZE12 = 0x0000000CU, + UART_FIFODEPTH_SIZE13 = 0x0000000DU, + UART_FIFODEPTH_SIZE14 = 0x0000000EU, + UART_FIFODEPTH_SIZE15 = 0x0000000FU +} UART_FIFO_Threshold; + +/** + * @brief UART data transfer sequence. + */ +typedef enum { + UART_SEQUENCE_START_LSB = 0x00000000U, + UART_SEQUENCE_START_MSB = 0x00000001U, +} UART_SequenceMode; + +/** + * @} + */ + +/** + * @defgroup UART_Reg_Def UART Register Definition + * @brief register mapping structure + * @{ + */ + +/** + * @brief UART data register, which stores the RX data and TX data and reads the RX status from this register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int data : 8; /**< Receives data and transmits data. */ + unsigned int fe : 1; /**< Frame error. */ + unsigned int pe : 1; /**< Verification error. */ + unsigned int be : 1; /**< Break error. */ + unsigned int oe : 1; /**< Overflow error. */ + unsigned int reserved0 : 20; + } BIT; +} volatile UART_DR_REG; + +/** + * @brief Receive status register/error clear register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int fe : 1; /**< Frame error. */ + unsigned int pe : 1; /**< Verification error. */ + unsigned int be : 1; /**< Break error. */ + unsigned int oe : 1; /**< Overflow error. */ + unsigned int reserved0 : 28; + } BIT; +} volatile UART_RSR_REG; + +/** + * @brief UART flag register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cts : 1; /**< Hardware flow control status. */ + unsigned int reserved0 : 2; + unsigned int busy : 1; /**< UART busy/idle status bit. */ + unsigned int rxfe : 1; /**< RX FIFO empty flag. */ + unsigned int txff : 1; /**< TX FIFO full flag. */ + unsigned int rxff : 1; /**< RX FIFO full flag. */ + unsigned int txfe : 1; /**< TX FIFO empty flag. */ + unsigned int reserved1 : 24; + } BIT; +} volatile UART_FR_REG; + +/** + * @brief Integer baud rate register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int bauddivint : 16; /**< Integer baud rate divider value. */ + unsigned int reserved0 : 16; + } BIT; +} volatile UART_IBRD_REG; + +/** + * @brief Fractional baud rate register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int bauddivfrac : 6; /**< Fractional baud rate divider. */ + unsigned int reserved0 : 26; + } BIT; +} volatile UART_FBRD_REG; + +/** + * @brief Line control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int brk : 1; /**< Send a break. */ + unsigned int pen : 1; /**< Check select bit. */ + unsigned int eps : 1; /**< Parity check selection during transmission and reception. */ + unsigned int stp2 : 1; /**< TX frame tail stop bit select. */ + unsigned int fen : 1; /**< TX and RX FIFO enable control. */ + unsigned int wlen : 2; /**< Indicates the number of transmitted and received data bits in a frame. */ + unsigned int sps : 1; /**< Select stick parity. */ + unsigned int reserved0 : 24; + } BIT; +} volatile UART_LCR_H_REG; + +/** + * @brief UART_CR is a UART control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int uarten : 1; /**< UART enable. */ + unsigned int reserved0 : 6; + unsigned int lbe : 1; /**< Indicates whether to enable loopback. */ + unsigned int txe : 1; /**< UART TX enable. */ + unsigned int rxe : 1; /**< UART RX enable. */ + unsigned int dtr : 1; /**< UART time run. */ + unsigned int rts : 1; /**< Request to send. */ + unsigned int reserved1 : 2; + unsigned int rtsen : 1; /**< RTS hardware flow control enable. */ + unsigned int ctsen : 1; /**< CTS hardware flow control enable. */ + unsigned int reserved2 : 16; + } BIT; +} volatile UART_CR_REG; + +/** + * @brief Interrupt FIFO threshold select register. + * It is used to set the FIFO interrupt trigger threshold (UART_TXinTR or UART_RXinTR). + */ +typedef union { + unsigned int reg; + struct { + unsigned int txiflsel : 4; /**< Configure the threshold of the TX FIFO. */ + unsigned int reserved0 : 4; + unsigned int rxiflsel : 4; /**< RX FIFO threshold. */ + unsigned int reserved1 : 20; + } BIT; +} volatile UART_IFLS_REG; + +/** + * @brief Interrupt mask register, which is used to mask interrupts. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int ctsmim : 1; /**< Mask status of the CTS interrupt. */ + unsigned int reserved1 : 2; + unsigned int rxim : 1; /**< Mask status of the RX interrupt. */ + unsigned int txim : 1; /**< Mask status of the TX interrupt. */ + unsigned int rtim : 1; /**< Mask status of the RX timeout interrupt. */ + unsigned int feim : 1; /**< Mask status of the frame error interrupt. */ + unsigned int peim : 1; /**< Mask status of the parity interrupt. */ + unsigned int beim : 1; /**< Mask status of the break error interrupt. */ + unsigned int oeim : 1; /**< Mask status of the overflow error interrupt. */ + unsigned int reserved2 : 1; + unsigned int txfeim : 1; /**< Mask status of the TX FIFO empty interrupt. */ + unsigned int txfneim : 1; /**< Mask status of the TX FIFO non-empt interrupt. */ + unsigned int txtcim : 1; /**< Mask status of the TX completion interrupt. */ + unsigned int reserved3 : 1; + unsigned int rxfeim : 1; /**< Mask status of the RX FIFO empty interrupt. */ + unsigned int rxfneim : 1; /**< Mask status of the RX FIFO non-empt interrupt. */ + unsigned int rxffim : 1; /**< Mask status of the RX FIFO full interrupt. */ + unsigned int abdcim : 1; /**< Mask status of the auto-baud check completion interrupt. */ + unsigned int abdeim : 1; /**< Mask status of auto-baud detection error interrupts. */ + unsigned int cmim : 1; /**< Mask status of the character match success interrupt. */ + unsigned int reserved4 : 10; + } BIT; +} volatile UART_IMSC_REG; + +/** + * @brief Raw interrupt status register. The content of this register is not affected by interrupt mask register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int ctsmis : 1; /**< Raw CTS interrupt status. */ + unsigned int reserved1 : 2; + unsigned int rxris : 1; /**< Raw RX threshold interrupt status. */ + unsigned int txris : 1; /**< Original TX threshold interrupt status. */ + unsigned int rtris : 1; /**< Raw RX timeout interrupt status. */ + unsigned int feris : 1; /**< Raw frame error interrupt status. */ + unsigned int peris : 1; /**< Raw parity interrupt status. */ + unsigned int beris : 1; /**< Raw break error interrupt status. */ + unsigned int oeris : 1; /**< Raw overflow error interrupt status. */ + unsigned int reserved2 : 1; + unsigned int txferis : 1; /**< Original TX FIFO empty interrupt status. */ + unsigned int txfneris : 1; /**< Raw TX FIFO non-empty interrupt status. */ + unsigned int txtcris : 1; /**< Raw TX completion interrupt status. */ + unsigned int reserved3 : 1; + unsigned int rxferis : 1; /**< Raw RX FIFO empty interrupt status. */ + unsigned int rxfneris : 1; /**< Raw RX FIFO non-empty interrupt status. */ + unsigned int rxffris : 1; /**< Status of the raw RX FIFO full interrupt. */ + unsigned int abdcris : 1; /**< Raw auto-baud detection completion interrupt status. */ + unsigned int abderis : 1; /**< Raw auto-baud detection error interrupt status. */ + unsigned int cmris : 1; /**< Status of the original character matching success interrupt. */ + unsigned int reserved4 : 10; + } BIT; +} volatile UART_RIS_REG; + +/** + * @brief Masked interrupt status register. + * It is result of AND operation between raw interrupt status and interrupt mask. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int ctsmmis : 1; /**< Masked CTS interrupt status. */ + unsigned int reserved1 : 2; + unsigned int rxmis : 1; /**< Masked RX interrupt status. */ + unsigned int txmis : 1; /**< Masked TX interrupt status. */ + unsigned int rtmis : 1; /**< Masked RX timeout interrupt status. */ + unsigned int femis : 1; /**< Status of masked frame error interrupts. */ + unsigned int pemis : 1; /**< Masked parity interrupt status. */ + unsigned int bemis : 1; /**< Status of masked break error interrupts. */ + unsigned int oemis : 1; /**< Masked overflow error interrupt status. */ + unsigned int reserved2 : 1; + unsigned int txfeis : 1; /**< Masked TX FIFO empty interrupt status. */ + unsigned int txfneis : 1; /**< Status of the masked TX FIFO non-empty interrupt. */ + unsigned int txtcis : 1; /**< Masked TX completion interrupt status. */ + unsigned int reserved3 : 1; + unsigned int rxfeis : 1; /**< Masked RX FIFO empty interrupt status. */ + unsigned int rxfneis : 1; /**< Status of the masked RX FIFO non-empt interrupt. */ + unsigned int rxffis : 1; /**< Status of the masked RX FIFO full interrupt. */ + unsigned int abdcis : 1; /**< Status of the masked auto-baud check completion interrupt. */ + unsigned int abdeis : 1; /**< Status of masked auto-baud detection error interrupts. */ + unsigned int cmis : 1; /**< Masked character matching success interrupt status. */ + unsigned int reserved4 : 10; + } BIT; +} volatile UART_MIS_REG; + +/** + * @brief Interrupt clear register + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int ctsmic : 1; /**< Clears the CTS interrupt. */ + unsigned int reserved1 : 2; + unsigned int rxic : 1; /**< Clears the RX interrupt. */ + unsigned int txic : 1; /**< Clears the TX interrupt. */ + unsigned int rtic : 1; /**< Receive timeout interrupt clear. */ + unsigned int feic : 1; /**< Frame error interrupt clear. */ + unsigned int peic : 1; /**< Clears the parity interrupt. */ + unsigned int beic : 1; /**< Clears the break error interrupt. */ + unsigned int oeic : 1; /**< Clears the overflow error interrupt. */ + unsigned int reserved2 : 1; + unsigned int txfeic : 1; /**< Clears the TX FIFO empty interrupt status. */ + unsigned int txfneic : 1; /**< TX FIFO non-empty interrupt clear status. */ + unsigned int txtcic : 1; /**< Transmit completion interrupt clear status. */ + unsigned int reserved3 : 1; + unsigned int rxfeic : 1; /**< RX FIFO empty interrupt clear status. */ + unsigned int rxfneic : 1; /**< RX FIFO non-empty interrupt clear status. */ + unsigned int rxffic : 1; /**< RX FIFO full interrupt clear status. */ + unsigned int abdcic : 1; /**< Auto-baud detection completion interrupt clear status. */ + unsigned int abdeic : 1; /**< Auto-baud detection error interrupt clear status. */ + unsigned int cmic : 1; /**< Clears the character matching success interrupt. */ + unsigned int reserved4 : 10; + } BIT; +} volatile UART_ICR_REG; + +/** + * @brief DMA control register, which is used to enable DMA of TX FIFO and RX FIFO. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rxdmae : 1; /** DMA enable control for the RX FIFO. */ + unsigned int txdmae : 1; /** DMA enable control for the TX FIFO. */ + unsigned int dmaonerr : 1; /** DMA enable control for RX channel when UART error interrupt occurs. */ + unsigned int rxlastsreq_en : 1; /** REQ enable for the last data stream supported by the UART RX DMA. */ + unsigned int reserved0 : 28; + } BIT; +} volatile UART_DMACR_REG; + +/** + * @brief Data transfer sequence configuration register. It is used to configure data transfer sequence. + */ +typedef union { + unsigned int reg; + struct { + unsigned int msbfirst : 1; /**< Most significant bit before enable. */ + unsigned int reserved0 : 31; + } BIT; +} volatile UART_DS_REG; + +/** + * @brief RX timeout duration configuration register, which is used to configure conditions for determining RX timeout. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rtcfg : 24; /**< Indicates the receive timeout interval, in bits. */ + unsigned int reserved0 : 8; + } BIT; +} volatile UART_RTCFG_REG; + +/** + * @brief Oversampling configuration register. It is used to configure the oversampling multiple. + */ +typedef union { + unsigned int reg; + struct { + unsigned int spcfg : 4; /**< Configure the oversampling multiplier. */ + unsigned int reserved0 : 28; + } BIT; +} volatile UART_SPCFG_REG; + +/** + * @brief Auto-baud detection enable register. It is used to enable auto-baud detection function. + */ +typedef union { + unsigned int reg; + struct { + unsigned int abden : 1; /**< Auto-baud detection enable. */ + unsigned int reserved0 : 3; + unsigned int abdbusy : 1; /**< Auto-baud detection busy flag. */ + unsigned int abdenvld : 1; /**< The abden sign is already valid. */ + unsigned int reserved1 : 26; + } BIT; +} volatile UART_ABDEN_REG; + +/** + * @brief Character match configuration register, which is used to configure characters to be matched. + */ +typedef union { + unsigned int reg; + struct { + unsigned int chamat : 8; /**< Binary character to be matched. */ + unsigned int reserved0 : 23; + unsigned int cmen : 1; /**< Character match detection enable. */ + } BIT; +} volatile UART_CHARMATCH_REG; + +/** + * @brief Register mapping structure. + */ +typedef struct { + UART_DR_REG UART_DR; /**< Data register, offset address: 0x00000000U */ + UART_RSR_REG UART_RSR; /**< Receiving status/error clearing register, offset address: 0x00000004U */ + unsigned char space0[16]; + UART_FR_REG UART_FR; /**< Flag register, offset address: 0x00000018U */ + unsigned char space1[8]; + UART_IBRD_REG UART_IBRD; /**< Integer baud rate register, offset address: 0x00000024U */ + UART_FBRD_REG UART_FBRD; /**< Fractional baud rate register, offset address: 0x00000028U */ + UART_LCR_H_REG UART_LCR_H; /**< Wire control register, offset address: 0x0000002CU */ + UART_CR_REG UART_CR; /**< Control register, offset address: 0x00000030U */ + UART_IFLS_REG UART_IFLS; /**< Interrupt FIFO threshold register, offset address: 0x00000034U */ + UART_IMSC_REG UART_IMSC; /**< Interrupt mask status register, offset address: 0x00000038U */ + UART_RIS_REG UART_RIS; /**< Raw interrupt status register, offset address: 0x0000003CU */ + UART_MIS_REG UART_MIS; /**< Masked interrupt status register, offset address: 0x00000040U */ + UART_ICR_REG UART_ICR; /**< Interrupt clear register, offset address: 0x00000044U */ + UART_DMACR_REG UART_DMACR; /**< DMA control register register, offset address: 0x00000048U */ + unsigned char space2[4]; + UART_DS_REG UART_DS; /**< Data transfer sequence set register, offset address: 0x00000050U */ + UART_RTCFG_REG UART_RTCFG; /**< RX timeout duration configuration register, offset address: 0x00000054U */ + UART_SPCFG_REG UART_SPCFG; /**< Oversampling configuration register, offset address: 0x00000058U */ + UART_ABDEN_REG UART_ABDEN; /**< Auto-baud detection enable register, offset address: 0x0000005CU */ + UART_CHARMATCH_REG UART_CHARMATCH; /**< Character match configuration register, offset address: 0x00000060U */ +} volatile UART_RegStruct; +/** + * @} + */ + +/** + * @brief Check UART datalength parameter. + * @param datalength The number of data bits in a frame, @ref UART_DataLength + * @retval bool + */ +static inline bool IsUartDatalength(UART_DataLength datalength) +{ + return (datalength >= UART_DATALENGTH_5BIT) && (datalength <= UART_DATALENGTH_8BIT); +} + +/** + * @brief Check UART stopbits parameter. + * @param stopbits The number of stop bits in a frame, @ref UART_StopBits + * @retval bool + */ +static inline bool IsUartStopbits(UART_StopBits stopbits) +{ + return (stopbits == UART_STOPBITS_ONE) || (stopbits == UART_STOPBITS_TWO); +} + +/** + * @brief Check UART paritymode parameter. + * @param paritymode UART parity check mode, @ref UART_Parity_Mode + * @retval bool + */ +static inline bool IsUartParitymode(UART_Parity_Mode paritymode) +{ + if ((paritymode >= UART_PARITY_ODD) && (paritymode <= UART_PARITY_NONE)) { + return true; + } + return false; +} + +/** + * @brief Check UART transmode parameter. + * @param transmode Transmit mode, @ref UART_Transmit_Mode + * @retval bool + */ +static inline bool IsUartTransmode(UART_Transmit_Mode transmode) +{ + if ((transmode == UART_MODE_BLOCKING) || + (transmode == UART_MODE_INTERRUPT) || + (transmode == UART_MODE_DMA) || + (transmode == UART_MODE_DISABLE)) { + return true; + } + return false; +} + +/** + * @brief Check UART fifoThreshold parameter. + * @param fifoThreshold UART TX/RX FIFO line interrupt threshold, @ref UART_FIFO_Threshold + * @retval bool + */ +static inline bool IsUartFIFOThreshold(UART_FIFO_Threshold fifoThreshold) +{ + return (fifoThreshold >= UART_FIFODEPTH_SIZE0) && (fifoThreshold <= UART_FIFODEPTH_SIZE15); +} + + +/** + * @brief Check UART Oversampling multiple. + * @param multiple Oversampling multiple, @ref UART_OversampleMultiple + * @retval bool + */ +static inline bool IsUartOversampleMultiple(UART_OversampleMultiple multiple) +{ + return (multiple >= UART_OVERSAMPLING_16X) && (multiple <= UART_OVERSAMPLING_12X); +} + +/** + * @brief Check UART data transfer sequential mode. + * @param mode UART TX/RX sequential mode, @ref UART_SequenceMode + * @retval bool + */ +static inline bool IsUartSequenceMode(UART_SequenceMode mode) +{ + return (mode == UART_SEQUENCE_START_LSB) || (mode == UART_SEQUENCE_START_MSB); +} + +/* Direct configuration layer */ +/** + * @brief Send a character by UART + * @param uartx UART register base address. + * @param data Character to be sent. + * @retval None. + */ +static inline void DCL_UART_WriteData(UART_RegStruct * const uartx, unsigned char data) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_DR.BIT.data = data; +} + +/** + * @brief Receive a character from UART. + * @param uartx UART register base address. + * @retval Data, read the received data from the UART data register. + */ +static inline unsigned char DCL_UART_ReadData(const UART_RegStruct *uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_DR.BIT.data; +} + +/** + * @brief UART TX enable. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_WriteEnable(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CR.BIT.txe = BASE_CFG_ENABLE; +} + +/** + * @brief UART TX disable. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_WriteDisable(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CR.BIT.txe = BASE_CFG_DISABLE; +} + +/** + * @brief UART RX enable. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_ReadEnable(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CR.BIT.rxe = BASE_CFG_ENABLE; +} + +/** + * @brief UART RX disable. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_ReadDisable(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CR.BIT.rxe = BASE_CFG_DISABLE; +} + +/** + * @brief UART TX use DMA . + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_DMA_WriteEnable(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_DMACR.BIT.txdmae = BASE_CFG_ENABLE; +} + +/** + * @brief UART TX cannot use DMA . + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_DMA_WriteDisable(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_DMACR.BIT.txdmae = BASE_CFG_DISABLE; +} + +/** + * @brief UART RX use DMA . + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_DMA_ReadEnable(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_DMACR.BIT.rxdmae = BASE_CFG_ENABLE; +} + +/** + * @brief UART RX cannot use DMA . + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_DMA_ReadDisable(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_DMACR.BIT.rxdmae = BASE_CFG_DISABLE; +} + +/** + * @brief UART word length setting. + * @param uartx UART register base address. + * @param dataLength Word length of sending and receiving, @ref UART_DataLength + * @retval None. + */ +static inline void DCL_UART_SetDataLength(UART_RegStruct * const uartx, UART_DataLength dataLength) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + UART_PARAM_CHECK_NO_RET(IsUartDatalength(dataLength)); + uartx->UART_LCR_H.BIT.wlen = dataLength; +} + +/** + * @brief Gettintg UART word length. + * @param uartx UART register base address. + * @retval Word length. + */ +static inline unsigned int DCL_UART_GetDataLength(const UART_RegStruct * uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_LCR_H.BIT.wlen; +} + +/** + * @brief Setting UART odd parity check. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_SetParityOdd(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_LCR_H.BIT.eps = BASE_CFG_DISABLE; + uartx->UART_LCR_H.BIT.pen = BASE_CFG_ENABLE; +} + +/** + * @brief Setting UART even parity check. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_SetParityEven(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_LCR_H.BIT.eps = BASE_CFG_ENABLE; + uartx->UART_LCR_H.BIT.pen = BASE_CFG_ENABLE; +} + +/** + * @brief UART does not use parity check. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_SetParityNone(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_LCR_H.BIT.pen = BASE_CFG_DISABLE; +} + +/** + * @brief Getting UART odd/even parity check. + * @param uartx UART register base address. + * @retval Odd/even parity check, 0: odd, 1: even, 2: None. + */ +static inline unsigned int DCL_UART_GetParityCheck(const UART_RegStruct * uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + unsigned int eps = uartx->UART_LCR_H.BIT.eps; + unsigned int pen = uartx->UART_LCR_H.BIT.pen; + if (eps == 0) { + return UART_PARITY_NONE; + } else if (pen == 0) { + return UART_PARITY_ODD; + } else { + return UART_PARITY_EVEN; + } +} + +/** + * @brief Setting the stop bit. + * @param uartx UART register base address. + * @param bit One or two stop bit, @ref UART_StopBits + * @retval None. + */ +static inline void DCL_UART_SetStopBits(UART_RegStruct * const uartx, UART_StopBits bit) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + UART_PARAM_CHECK_NO_RET(IsUartStopbits(bit)); + uartx->UART_LCR_H.BIT.stp2 = bit; +} + +/** + * @brief Getting the stop bit. + * @param uartx UART register base address. + * @retval Stop bit of UART. + */ +static inline unsigned int DCL_UART_GetStopBits(const UART_RegStruct *uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_LCR_H.BIT.stp2; +} + +/** + * @brief UART uses hardware flow control. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_Enable_HwFlowCtr(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CR.BIT.ctsen = BASE_CFG_ENABLE; + uartx->UART_CR.BIT.rtsen = BASE_CFG_ENABLE; +} + +/** + * @brief UART uses hardware flow control. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_Disable_HwFlowCtr(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CR.BIT.ctsen = BASE_CFG_DISABLE; + uartx->UART_CR.BIT.rtsen = BASE_CFG_DISABLE; +} + +/** + * @brief UART Disable function of stick parity. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_DisableStickParity(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_LCR_H.BIT.sps = BASE_CFG_DISABLE; +} + +/** + * @brief UART enable function of stick parity 0-bit check. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_EnableStickParity_Zero(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_LCR_H.BIT.pen = BASE_CFG_ENABLE; + uartx->UART_LCR_H.BIT.eps = BASE_CFG_ENABLE; + uartx->UART_LCR_H.BIT.sps = BASE_CFG_ENABLE; +} + +/** + * @brief UART enable function of stick parity 1-bit check. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_EnableStickParity_One(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_LCR_H.BIT.pen = BASE_CFG_ENABLE; + uartx->UART_LCR_H.BIT.eps = BASE_CFG_DISABLE; + uartx->UART_LCR_H.BIT.sps = BASE_CFG_ENABLE; +} + +/** + * @brief UART enable interrupt of CTS. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_EnableCTSInt(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_LCR_H.BIT.pen = BASE_CFG_ENABLE; +} + +/** + * @brief UART clear interrupt of CTS. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_ClearCTSInt(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_ICR.BIT.ctsmic = BASE_CFG_ENABLE; + uartx->UART_IMSC.BIT.ctsmim = BASE_CFG_DISABLE; +} + +/** + * @brief UART get interrupt status of CTS. + * @param uartx UART register base address. + * @retval status, 1: Interrupt generation, 0: interrupt is not generated. + */ +static inline unsigned int DCL_UART_GetCTSIntStatus(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_MIS.BIT.ctsmmis; +} + +/** + * @brief Set the data bits. The first bit to be transmitted and received is the LSB. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_SetDataLSB(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_DS.BIT.msbfirst = 0; +} + +/** + * @brief Set the data bits. The first bit to be transmitted and received is the MSB. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_SetDataMSB(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_DS.BIT.msbfirst = 1; +} + +/** + * @brief Setting data sequences of UART. + * @param uartx UART register base address. + * @param bool 1: enable MSB 0: enable LSB. + * @retval None. + */ +static inline void DCL_UART_SetDataSequences(UART_RegStruct * const uartx, bool dataSequence) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_DS.BIT.msbfirst = dataSequence; +} + + +/** + * @brief Configuring the upper limit of receiving timeout. + * @param uartx UART register base address. + * @param timeOfBits timeout, time required to transmit a certain bit. + * @retval None. + */ +static inline void DCL_UART_SetRxTimeOut(UART_RegStruct * const uartx, unsigned int timeOfBits) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + UART_PARAM_CHECK_NO_RET(timeOfBits <= 0xFFFFFF); + uartx->UART_RTCFG.reg = timeOfBits; +} + +/** + * @brief Enable automatic baud rate detection. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_EnableBaudRateDetection(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_ABDEN.BIT.abden = BASE_CFG_ENABLE; +} + +/** + * @brief Disable automatic baud rate detection. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_DisableBaudRateDetection(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_ABDEN.BIT.abden = BASE_CFG_DISABLE; +} + +/** + * @brief Enable character adaptation. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_EnableMatchCharater(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CHARMATCH.BIT.cmen = BASE_CFG_ENABLE; +} + +/** + * @brief Disable character adaptation. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_DisableMatchCharater(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CHARMATCH.BIT.cmen = BASE_CFG_DISABLE; +} + +/** + * @brief Sets the character to be matched. + * @param uartx UART register base address. + * @param ascii ascii of character. + * @retval None. + */ +static inline void DCL_UART_SetMatchCharater(UART_RegStruct * const uartx, unsigned int ascii) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + UART_PARAM_CHECK_NO_RET(ascii <= 0xFF); + uartx->UART_CHARMATCH.BIT.chamat = ascii; +} + +/** + * @brief Sets UART oversampling multiple. + * @param uartx UART register base address. + * @param multiple Oversampling multiple, @ref UART_OversampleMultiple + * @retval None. + */ +static inline void DCL_UART_OversampleMultiple(UART_RegStruct * const uartx, UART_OversampleMultiple multiple) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + UART_PARAM_CHECK_NO_RET(IsUartOversampleMultiple(multiple)); + uartx->UART_SPCFG.BIT.spcfg = multiple; +} +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_UART_IP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/uart/src/uart.c b/vendor/xinlingyu_92_3061M/Project/drivers/uart/src/uart.c new file mode 100644 index 0000000000000000000000000000000000000000..f52b870c3fd627d4c71b67cb104d12d3bc0350b5 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/uart/src/uart.c @@ -0,0 +1,884 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file uart.c + * @author MCU Driver Team + * @brief UART module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the UART. + * + Initialization and de-initialization functions. + * + Peripheral send and receive functions in blocking mode. + * + Peripheral send and receive functions in interrupt mode. + * + Peripheral send and receive functions in DMA mode. + * + Peripheral stop sending and receiving functions in interrupt/DMA mode. + * + Interrupt callback function and user registration function. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "systick.h" +#include "uart.h" +/* Macro definitions ---------------------------------------------------------*/ + +#define OVERSAMPLING_PARAM 16 +#define SYSTICK_MS_DIV 1000 +#define PARITY_ODD 0x2 +#define PARITY_EVEN 0x6 +#define PARITY_MARK 0x82 +#define PARITY_SPACE 0x86 + +static unsigned int DivClosest(unsigned int x, unsigned int divisor) +{ + unsigned int ret; + if (divisor == 0) { + return 0; + } + ret = (((x) + ((divisor) / 2)) / (divisor)); /* Round up the result, add 1/2 */ + return ret; +} + +static void WriteDMAFinishFun(void *handle); +static void ReadDMAFinishFun(void *handle); +static void TransmitDMAErrorFun(void *handle); + +static void ReadITCallBack(UART_Handle *uartHandle); +static void WriteITCallBack(UART_Handle *uartHandle); +static void ErrorServiceCallback(UART_Handle *uartHandle); + +static void CharterMatchCallBack(UART_Handle *uartHandle); +static void BaudDetectCallBack(UART_Handle *uartHandle); + +static void UART_SetParityBit(UART_Handle *uartHandle); + + +/** + * @brief Baud rate detection interrupt callback function. + * @param uartHandle UART handle. + * @retval None. + */ +static void BaudDetectCallBack(UART_Handle *uartHandle) +{ + if (uartHandle->baseAddress->UART_MIS.BIT.abdcis == 0x01) { + uartHandle->baseAddress->UART_ABDEN.BIT.abden = BASE_CFG_DISABLE; + uartHandle->baseAddress->UART_IMSC.BIT.abdeim = BASE_CFG_DISABLE; + uartHandle->baseAddress->UART_IMSC.BIT.abdcim = BASE_CFG_DISABLE; + uartHandle->baseAddress->UART_ICR.BIT.abdcic = BASE_CFG_ENABLE; + /* After the baud rate automatic detection function is configured, enable UART. */ + uartHandle->baseAddress->UART_CR.BIT.txe = BASE_CFG_ENABLE; + uartHandle->baseAddress->UART_CR.BIT.rxe = BASE_CFG_ENABLE; + /* Call back user detect success function. */ + if (uartHandle->userCallBack.BaudDetectSuccessCallBack != NULL) { + uartHandle->userCallBack.BaudDetectSuccessCallBack(uartHandle); + } + } else { + /* Wait until UART is idle. */ + while (uartHandle->baseAddress->UART_ABDEN.BIT.abdbusy == 0x01) { + ; + } + uartHandle->baseAddress->UART_ICR.BIT.abdeic = BASE_CFG_ENABLE; + /* Call back user baud detect error function. */ + if (uartHandle->userCallBack.BaudDetectErrorCallBack != NULL) { + uartHandle->userCallBack.BaudDetectErrorCallBack(uartHandle); + } + } + return; +} + +/** + * @brief Character detection interrupt callback function. + * @param uartHandle UART handle. + * @retval None. + */ +static void CharterMatchCallBack(UART_Handle *uartHandle) +{ + uartHandle->baseAddress->UART_IMSC.BIT.cmim = BASE_CFG_DISABLE; + uartHandle->baseAddress->UART_ICR.BIT.cmic = BASE_CFG_ENABLE; + if (uartHandle->userCallBack.CharacterMatchCallBack != NULL) { + uartHandle->userCallBack.CharacterMatchCallBack(uartHandle); + } +} + +/** + * @brief Sets the parity bit of the UART. + * @param uartHandle UART handle. + * @retval None. + */ +static void UART_SetParityBit(UART_Handle *uartHandle) +{ + /* Sets the UART check mode. */ + switch (uartHandle->parity) { + case UART_PARITY_ODD: + uartHandle->baseAddress->UART_LCR_H.reg |= PARITY_ODD; /* Odd parity. */ + break; + case UART_PARITY_EVEN: + uartHandle->baseAddress->UART_LCR_H.reg |= PARITY_EVEN; /* Even parity. */ + break; + case UART_PARITY_MARK: + uartHandle->baseAddress->UART_LCR_H.reg |= PARITY_MARK; /* Marking parity */ + break; + case UART_PARITY_SPACE: + uartHandle->baseAddress->UART_LCR_H.reg |= PARITY_SPACE; /* space parity */ + break; + case UART_PARITY_NONE: + uartHandle->baseAddress->UART_LCR_H.BIT.pen = BASE_CFG_DISABLE; /* No parity */ + break; + default: + return; + } +} + +/** + * @brief Initialize the UART hardware configuration and configure parameters based on the specified handle. + * @param uartHandle UART handle. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_UART_Init(UART_Handle *uartHandle) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_PARAM_CHECK_WITH_RET(uartHandle->txState == UART_STATE_NONE_INIT, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(uartHandle->rxState == UART_STATE_NONE_INIT, BASE_STATUS_ERROR); + unsigned int uartClock, quot; + UART_PARAM_CHECK_WITH_RET(IsUartDatalength(uartHandle->dataLength), BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(IsUartStopbits(uartHandle->stopBits), BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(IsUartParitymode(uartHandle->parity), BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(IsUartTransmode(uartHandle->txMode), BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(IsUartTransmode(uartHandle->rxMode), BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(IsUartFIFOThreshold(uartHandle->fifoTxThr), BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(IsUartFIFOThreshold(uartHandle->fifoRxThr), BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(IsUartOversampleMultiple(uartHandle->handleEx.overSampleMultiple), BASE_STATUS_ERROR); + + uartHandle->baseAddress->UART_CR.BIT.uarten = BASE_CFG_DISABLE; + while (uartHandle->baseAddress->UART_FR.BIT.busy == 0x01) { + ; + } + + uartClock = HAL_CRG_GetIpFreq((void *)uartHandle->baseAddress); + + /* DCL OverSample Multiple check */ + uartHandle->baseAddress->UART_SPCFG.BIT.spcfg = uartHandle->handleEx.overSampleMultiple; + + /* DCL sequences setting */ + uartHandle->baseAddress->UART_DS.BIT.msbfirst = uartHandle->handleEx.msbFirst; + + /* The baud rate divider(BRD) based on the baud rate and clock frequency, calculation formula */ + unsigned int oversample = uartHandle->baseAddress->UART_SPCFG.reg; + if (uartHandle->baudRate > (uartClock / (OVERSAMPLING_PARAM - oversample))) { + return BASE_STATUS_ERROR; + } else { + unsigned int tmpClock = uartClock / (OVERSAMPLING_PARAM - oversample) * 64; /* 64 is for decimal parts */ + quot = DivClosest(tmpClock, uartHandle->baudRate); + } + /* Clear the baud rate divider register */ + uartHandle->baseAddress->UART_FBRD.reg = 0; + uartHandle->baseAddress->UART_IBRD.reg = 0; + /* The fractional baud rate divider value is stored to the lower 6 bits of the FBRD */ + uartHandle->baseAddress->UART_FBRD.reg = (quot & 0x3F); + /* Right shift 6 bits is the integer baud rate divider value, is stored to IBRD */ + uartHandle->baseAddress->UART_IBRD.reg = (quot >> 6); + uartHandle->baseAddress->UART_LCR_H.reg = 0; + uartHandle->baseAddress->UART_LCR_H.BIT.wlen = uartHandle->dataLength; /* Frame length seting */ + uartHandle->baseAddress->UART_LCR_H.BIT.stp2 = uartHandle->stopBits; /* Stop bit seting */ + UART_SetParityBit(uartHandle); + if (uartHandle->fifoMode == true) { /* FIFO threshold setting */ + uartHandle->baseAddress->UART_LCR_H.BIT.fen = BASE_CFG_ENABLE; + uartHandle->baseAddress->UART_IFLS.BIT.rxiflsel = uartHandle->fifoRxThr; + uartHandle->baseAddress->UART_IFLS.BIT.txiflsel = uartHandle->fifoTxThr; + } + if (uartHandle->hwFlowCtr == UART_HW_FLOWCTR_ENABLE) { /* Hardwarer flow control setting */ + uartHandle->baseAddress->UART_CR.reg |= 0xC000; + } + uartHandle->baseAddress->UART_CR.reg |= 0x301; /* Enable bit use 0x301 is to set txe/rxe/uarten */ + uartHandle->txState = UART_STATE_READY; + uartHandle->rxState = UART_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief DeInitialize the UART and restoring default parameters based on the specified handle. + * @param uartHandle UART handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_DeInit(UART_Handle *uartHandle) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + uartHandle->baseAddress->UART_CR.reg = BASE_CFG_DISABLE; + uartHandle->baseAddress->UART_ICR.reg |= 0xFFFF; /* Clear all interruptions. */ + uartHandle->baseAddress->UART_IMSC.reg = BASE_CFG_DISABLE; + uartHandle->baseAddress->UART_DMACR.reg = BASE_CFG_DISABLE; + uartHandle->baseAddress->UART_LCR_H.BIT.brk = BASE_CFG_DISABLE; + uartHandle->baseAddress->UART_LCR_H.BIT.fen = BASE_CFG_DISABLE; + uartHandle->baseAddress->UART_SPCFG.BIT.spcfg = BASE_CFG_DISABLE; /* Clear Oversampling Configuration */ + uartHandle->baseAddress->UART_DS.BIT.msbfirst = BASE_CFG_DISABLE; /* Clears the data receiving sequence. */ + uartHandle->userCallBack.WriteItFinishCallBack = NULL; /* Clear all user call back function. */ + uartHandle->userCallBack.ReadItFinishCallBack = NULL; + uartHandle->userCallBack.WriteDmaFinishCallBack = NULL; /* Clear user DMA call back function. */ + uartHandle->userCallBack.ReadDmaFinishCallBack = NULL; + uartHandle->userCallBack.TransmitDmaErrorCallBack = NULL; + uartHandle->userCallBack.TransmitItErrorCallBack = NULL; + uartHandle->userCallBack.BaudDetectErrorCallBack = NULL; /* Clear user baud detection callback function */ + uartHandle->userCallBack.BaudDetectSuccessCallBack = NULL; + uartHandle->userCallBack.CharacterMatchCallBack = NULL; /* Clear user character matching callback function */ + uartHandle->rxState = UART_STATE_NONE_INIT; /* Resets the UART status to uninitialized. */ + uartHandle->txState = UART_STATE_NONE_INIT; + return BASE_STATUS_OK; +} + +/** + * @brief Return the specified UART state. + * @param uartHandle UART handle. + * @retval UART state: UART_STATE_NONE_INIT(can not use), UART_STATE_READY, UART_STATE_BUSY + * @retval UART_STATE_BUSY_TX, UART_STATE_BUSY_RX. + */ +UART_State_Type HAL_UART_GetState(UART_Handle *uartHandle) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + if (uartHandle->txState == UART_STATE_NONE_INIT) { + return UART_STATE_NONE_INIT; /* Uart Rx and Tx are not initialized */ + } + if (uartHandle->txState == UART_STATE_READY && uartHandle->rxState == UART_STATE_READY) { + return UART_STATE_READY; /* Uart Rx and Tx are ready */ + } + if (uartHandle->txState == UART_STATE_READY) { + return UART_STATE_BUSY_RX; /* Uart Rx is busy */ + } + if (uartHandle->rxState == UART_STATE_READY) { + return UART_STATE_BUSY_TX; /* Uart Tx is busy */ + } + return UART_STATE_BUSY; /* Uart Rx and Tx are busy */ +} + +/** + * @brief Send data in blocking mode. + * @param uartHandle UART handle. + * @param srcData Address of the data buff to be sent. + * @param dataLength number of the data to be sent. + * @param blockingTime Blocking time, unit: milliseconds. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_WriteBlocking(UART_Handle *uartHandle, unsigned char *srcData, + unsigned int dataLength, unsigned int blockingTime) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_ASSERT_PARAM(srcData != NULL); + UART_PARAM_CHECK_WITH_RET(uartHandle->txMode == UART_MODE_BLOCKING, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + unsigned long long setTick = HAL_CRG_GetIpFreq(SYSTICK_BASE) / SYSTICK_MS_DIV * blockingTime; + UART_PARAM_CHECK_WITH_RET(setTick < SYSTICK_MAX_VALUE, BASE_STATUS_ERROR); + if (uartHandle->txState == UART_STATE_READY) { + uartHandle->txState = UART_STATE_BUSY_TX; + unsigned int txCount = dataLength; + unsigned char *src = srcData; + uartHandle->baseAddress->UART_IMSC.BIT.txim = BASE_CFG_DISABLE; /* Disable TX interrupt bit */ + uartHandle->baseAddress->UART_CR.BIT.txe = BASE_CFG_ENABLE; + unsigned long long deltaTick; + unsigned int preTick = DCL_SYSTICK_GetTick(); + unsigned int curTick = preTick; + while (txCount > 0x00) { + curTick = DCL_SYSTICK_GetTick(); + deltaTick = (curTick > preTick) ? (curTick - preTick) : (SYSTICK_MAX_VALUE - preTick + curTick); + if (deltaTick >= setTick) { + uartHandle->txState = UART_STATE_READY; + return BASE_STATUS_TIMEOUT; + } + if (uartHandle->baseAddress->UART_FR.BIT.txff == 0x01) { /* True when the TX FIFO is full */ + continue; + } + /* Blocking write to DR when register is empty */ + uartHandle->baseAddress->UART_DR.BIT.data = *(src); + src++; + txCount--; + } + } else { + return BASE_STATUS_BUSY; + } + uartHandle->txState = UART_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief Send data in interrupt mode. + * @param uartHandle UART handle. + * @param srcData Address of the data buff to be sent. + * @param dataLength Number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_WriteIT(UART_Handle *uartHandle, unsigned char *srcData, unsigned int dataLength) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_PARAM_CHECK_WITH_RET(uartHandle->txMode == UART_MODE_INTERRUPT, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(srcData != NULL, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + + if (uartHandle->txState == UART_STATE_READY) { + uartHandle->txState = UART_STATE_BUSY_TX; + uartHandle->txbuff = srcData; + uartHandle->txBuffSize = dataLength; + uartHandle->baseAddress->UART_ICR.BIT.txic = BASE_CFG_ENABLE; + if (uartHandle->fifoMode == true) { + uartHandle->baseAddress->UART_IMSC.BIT.txim = BASE_CFG_ENABLE; + } else { + uartHandle->baseAddress->UART_IMSC.BIT.txfeim = BASE_CFG_ENABLE; + } + } else { + return BASE_STATUS_BUSY; + } + return BASE_STATUS_OK; +} + +/** + * @brief Interrupt sending callback function. + * The hanler function is called when Tx interruption occurs. + * @param uartHandle UART handle. + * @retval None. + */ +static void WriteITCallBack(UART_Handle *uartHandle) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_ASSERT_PARAM(uartHandle->txbuff != NULL); + if (uartHandle->txState == UART_STATE_BUSY_TX) { + while (uartHandle->txBuffSize > 0) { + if (uartHandle->baseAddress->UART_FR.BIT.txff == 1) { /* True when the TX FIFO is full */ + break; + } + uartHandle->baseAddress->UART_DR.BIT.data = *(uartHandle->txbuff); + (uartHandle->txbuff)++; + uartHandle->txBuffSize -= 1; + } + if (uartHandle->txBuffSize == 0) { + uartHandle->baseAddress->UART_IMSC.reg &= 0xFFFFEFDF; /* Disable txim and txfeim */ + uartHandle->baseAddress->UART_ICR.reg |= 0x1020; /* Clear txic and txfeic */ + uartHandle->txState = UART_STATE_READY; + /* Call user call back function */ + if (uartHandle->userCallBack.WriteItFinishCallBack != NULL) { + uartHandle->userCallBack.WriteItFinishCallBack(uartHandle); + } + } + } + return; +} + +/** + * @brief Send data in DMA mode. + * @param uartHandle UART handle. + * @param srcData Address of the data buff to be sent. + * @param dataLength Number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_WriteDMA(UART_Handle *uartHandle, unsigned char *srcData, + unsigned int dataLength) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_PARAM_CHECK_WITH_RET(uartHandle->txMode == UART_MODE_DMA, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(srcData != NULL, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + unsigned int channel = uartHandle->uartDmaTxChn; + UART_PARAM_CHECK_WITH_RET(IsDmaChannelNum(channel) == true, BASE_STATUS_ERROR); + UART_ASSERT_PARAM(uartHandle->dmaHandle != NULL); + if (uartHandle->txState == UART_STATE_READY) { + uartHandle->txState = UART_STATE_BUSY_TX; + uartHandle->baseAddress->UART_IMSC.BIT.txim = BASE_CFG_DISABLE; /* Disable TX interrupt bit */ + uartHandle->dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelFinishCallBack = WriteDMAFinishFun; + uartHandle->dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelErrorCallBack = TransmitDMAErrorFun; + uartHandle->txbuff = srcData; + uartHandle->txBuffSize = dataLength; + if (HAL_DMA_StartIT(uartHandle->dmaHandle, (uintptr_t)(void *)uartHandle->txbuff, + (uintptr_t)(void *)&(uartHandle->baseAddress->UART_DR), \ + dataLength, channel) != BASE_STATUS_OK) { + uartHandle->txState = UART_STATE_READY; + return BASE_STATUS_ERROR; + } + uartHandle->baseAddress->UART_DMACR.BIT.txdmae = BASE_CFG_ENABLE; /* Enable TX DMA bit */ + } else { + return BASE_STATUS_BUSY; + } + return BASE_STATUS_OK; +} + +/** + * @brief Receive data in blocking mode. + * @param uartHandle UART handle. + * @param saveData Address of the data buff to be saved. + * @param dataLength Length of the data int the storage buffer. + * @param blockingTime Blocking time, unit: milliseconds. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_ReadBlocking(UART_Handle *uartHandle, unsigned char *saveData, + unsigned int dataLength, unsigned int blockingTime) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(saveData != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_PARAM_CHECK_WITH_RET(uartHandle->rxMode == UART_MODE_BLOCKING, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(blockingTime > 0, BASE_STATUS_ERROR); + unsigned long long setTick = HAL_CRG_GetIpFreq(SYSTICK_BASE) / SYSTICK_MS_DIV * blockingTime; + UART_PARAM_CHECK_WITH_RET(setTick < SYSTICK_MAX_VALUE, BASE_STATUS_ERROR); + if (uartHandle->rxState == UART_STATE_READY) { + uartHandle->rxState = UART_STATE_BUSY_RX; + unsigned int rxCount = dataLength; + unsigned char *save = saveData; + uartHandle->baseAddress->UART_IMSC.BIT.rxim = BASE_CFG_DISABLE; /* Disable RX interrupt bit */ + uartHandle->baseAddress->UART_ICR.reg = 0XFF; /* Clear interrupt flag */ + unsigned int tmp; + unsigned long long deltaTick; + unsigned int preTick = DCL_SYSTICK_GetTick(); + unsigned int curTick = preTick; + while (rxCount > 0) { + curTick = DCL_SYSTICK_GetTick(); + deltaTick = (curTick > preTick) ? (curTick - preTick) : (SYSTICK_MAX_VALUE - preTick + curTick); + if (deltaTick >= setTick) { + uartHandle->rxState = UART_STATE_READY; + return BASE_STATUS_TIMEOUT; + } + if (uartHandle->baseAddress->UART_FR.BIT.rxfe == 0x01) { + continue; + } + tmp = uartHandle->baseAddress->UART_DR.reg; + if (tmp & 0xF00) { /* True when receiving generated error */ + uartHandle->rxState = UART_STATE_READY; + return BASE_STATUS_ERROR; + } + *(save) = (tmp & 0xFF); /* The lower eight bits are the register data bits */ + save++; + rxCount--; + } + } else { + return BASE_STATUS_BUSY; + } + uartHandle->rxState = UART_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief Receive data in interrupt mode. + * @param uartHandle UART handle. + * @param saveData Address of the data buff to be saved. + * @param dataLength length of the data int the storage buffer. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_ReadIT(UART_Handle *uartHandle, unsigned char *saveData, unsigned int dataLength) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_ASSERT_PARAM(saveData != NULL); + UART_PARAM_CHECK_WITH_RET(uartHandle->rxMode == UART_MODE_INTERRUPT, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + if (uartHandle->rxState == UART_STATE_READY) { + uartHandle->rxState = UART_STATE_BUSY_RX; + uartHandle->rxbuff = saveData; + uartHandle->rxBuffSize = dataLength; + if (uartHandle->fifoMode == true) { + uartHandle->baseAddress->UART_IMSC.reg |= 0x7D0; /* Enable rx interrupt and rx timeout interrupt */ + } else { + uartHandle->baseAddress->UART_IMSC.reg |= 0x20780; /* Enable rx not empty interrupt */ + } + } else { + return BASE_STATUS_BUSY; + } + return BASE_STATUS_OK; +} + +/** + * @brief Interrupt receiving callback function. + * The hanler function is called when Rx interruption occurs. + * @param uartHandle UART handle. + * @retval None. + */ +static void ReadITCallBack(UART_Handle *uartHandle) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(uartHandle->rxbuff != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + if (uartHandle->rxState == UART_STATE_BUSY_RX) { + unsigned int tmp; + while (uartHandle->rxBuffSize > 0) { + if (uartHandle->baseAddress->UART_FR.BIT.rxfe == 0x01) { /* True when the RX FIFO is empty */ + break; + } + tmp = uartHandle->baseAddress->UART_DR.reg; + *(uartHandle->rxbuff) = (tmp & 0xFF); /* Read from DR when holding register/FIFO is not empty */ + uartHandle->rxbuff++; + uartHandle->rxBuffSize -= 1; + } + if (uartHandle->rxBuffSize == 0) { + uartHandle->baseAddress->UART_IMSC.reg &= 0xFFFDFFAF; /* Disable rxim ,rtim and rxfneim */ + uartHandle->rxState = UART_STATE_READY; + } + uartHandle->baseAddress->UART_ICR.reg |= 0x20050; /* Clear rxic, rtic and rxfneic */ + if (uartHandle->userCallBack.ReadItFinishCallBack != NULL && uartHandle->rxBuffSize == 0) { + uartHandle->userCallBack.ReadItFinishCallBack(uartHandle); + } + } + return; +} + +/** + * @brief Callback function of finishing receiving in DMA mode. + * The hanler function is called when Rx DMA Finish interruption occurs. + * @param handle DMA handle. + * @retval None. + */ +static void ReadDMAFinishFun(void *handle) +{ + UART_ASSERT_PARAM(handle != NULL); + UART_Handle *uartHandle = (UART_Handle *)(handle); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + uartHandle->rxState = UART_STATE_READY; + uartHandle->baseAddress->UART_DMACR.BIT.rxdmae = BASE_CFG_DISABLE; + uartHandle->rxBuffSize = 0; + if (uartHandle->userCallBack.ReadDmaFinishCallBack != NULL) { + uartHandle->userCallBack.ReadDmaFinishCallBack(uartHandle); /* User callback function */ + } + return; +} + +/** + * @brief Callback function of finishing sending in DMA mode. + * The hanler function is called when Tx DMA Finish interruption occurs. + * @param handle DMA handle. + * @retval None. + */ +static void WriteDMAFinishFun(void *handle) +{ + UART_ASSERT_PARAM(handle != NULL); + UART_Handle *uartHandle = (UART_Handle *)(handle); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + uartHandle->txState = UART_STATE_READY; + uartHandle->baseAddress->UART_DMACR.BIT.txdmae = BASE_CFG_DISABLE; + uartHandle->txBuffSize = 0; + if (uartHandle->userCallBack.WriteDmaFinishCallBack != NULL) { + uartHandle->userCallBack.WriteDmaFinishCallBack(uartHandle); /* User callback function */ + } + return; +} + +/** + * @brief Callback function of Tx/Rx error interrupt in DMA mode. + * The hanler function is called when Tx/Rx transmission error interruption occurs. + * @param handle DMA handle. + * @retval None. + */ +static void TransmitDMAErrorFun(void *handle) +{ + UART_ASSERT_PARAM(handle != NULL); + UART_Handle *uartHandle = (UART_Handle *)(handle); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + if (uartHandle->rxState == UART_STATE_BUSY_RX) { + uartHandle->baseAddress->UART_DMACR.BIT.rxdmae = BASE_CFG_DISABLE; + } + if (uartHandle->txState == UART_STATE_BUSY_TX) { + uartHandle->baseAddress->UART_DMACR.BIT.txdmae = BASE_CFG_DISABLE; + } + if (uartHandle->userCallBack.TransmitDmaErrorCallBack != NULL) { + uartHandle->userCallBack.TransmitDmaErrorCallBack(uartHandle); + } + uartHandle->txState = UART_STATE_READY; + uartHandle->rxState = UART_STATE_READY; + return; +} + +/** + * @brief Receive data in DMA mode. + * @param uartHandle UART handle. + * @param saveData Address of the data buff to be sent. + * @param dataLength number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_ReadDMA(UART_Handle *uartHandle, unsigned char *saveData, + unsigned int dataLength) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_ASSERT_PARAM(saveData != NULL); + UART_PARAM_CHECK_WITH_RET(uartHandle->rxMode == UART_MODE_DMA, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + unsigned int channel = uartHandle->uartDmaRxChn; + UART_PARAM_CHECK_WITH_RET(IsDmaChannelNum(channel) == true, BASE_STATUS_ERROR); + UART_ASSERT_PARAM(uartHandle->dmaHandle != NULL); + if (uartHandle->rxState == UART_STATE_READY) { + uartHandle->rxState = UART_STATE_BUSY_RX; + uartHandle->baseAddress->UART_IMSC.BIT.rxim = BASE_CFG_DISABLE; /* Disable RX interrupt bit */ + uartHandle->dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelFinishCallBack = ReadDMAFinishFun; + uartHandle->dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelErrorCallBack = TransmitDMAErrorFun; + uartHandle->rxbuff = saveData; + uartHandle->rxBuffSize = dataLength; + /* Can not masking overflow error, break error, check error, frame error interrupt */ + if (HAL_DMA_StartIT(uartHandle->dmaHandle, (uintptr_t)(void *)&(uartHandle->baseAddress->UART_DR), + (uintptr_t)(void *)uartHandle->rxbuff, dataLength, channel) != BASE_STATUS_OK) { + uartHandle->rxState = UART_STATE_READY; + return BASE_STATUS_ERROR; + } + uartHandle->baseAddress->UART_DMACR.BIT.rxdmae = BASE_CFG_ENABLE; /* Enable RX_DMA bit */ + } else { + return BASE_STATUS_BUSY; + } + return BASE_STATUS_OK; +} + +/** + * @brief Stop the process of sending data in interrupt or DMA mode. + * @param uartHandle UART handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_StopWrite(UART_Handle *uartHandle) /* Only support UART_MODE_INTERRUPT and UART_MODE_DMA */ +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_ASSERT_PARAM(uartHandle->dmaHandle != NULL); + UART_PARAM_CHECK_WITH_RET(IsDmaChannelNum(uartHandle->uartDmaTxChn) == true, BASE_STATUS_ERROR); + /* Blocking send interrupt and jugdement the status of txmode. */ + uartHandle->baseAddress->UART_IMSC.BIT.txim = BASE_CFG_DISABLE; + if (uartHandle->txMode == UART_MODE_DMA) { + uartHandle->baseAddress->UART_DMACR.BIT.txdmae = BASE_CFG_DISABLE; /* Close FIFO of DMA and Stop DMA channel. */ + if (HAL_DMA_StopChannel(uartHandle->dmaHandle, uartHandle->uartDmaTxChn) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + } + uartHandle->txState = UART_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief Stop the process of receiving data in interrupt or DMA mode. + * @param uartHandle UART handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_StopRead(UART_Handle *uartHandle) /* Only support UART_MODE_INTERRUPT and UART_MODE_DMA */ +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_ASSERT_PARAM(uartHandle->dmaHandle != NULL); + UART_PARAM_CHECK_WITH_RET(IsDmaChannelNum(uartHandle->uartDmaRxChn) == true, BASE_STATUS_ERROR); + unsigned int val = uartHandle->baseAddress->UART_IMSC.reg; + val &= 0xFFFDF82F; /* Disable bits: rxim, rtim, feim, peim, beim, oeim, rxfneim */ + uartHandle->baseAddress->UART_IMSC.reg = val; + if (uartHandle->rxMode == UART_MODE_DMA) { + uartHandle->baseAddress->UART_DMACR.BIT.rxdmae = BASE_CFG_DISABLE; + if (HAL_DMA_StopChannel(uartHandle->dmaHandle, uartHandle->uartDmaRxChn) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + } + uartHandle->rxState = UART_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief Error handler function of receiving. + * @param uartHandle UART handle. + * @retval None. + */ +static void ErrorServiceCallback(UART_Handle *uartHandle) +{ + unsigned int error = 0x00; + if (uartHandle->baseAddress->UART_MIS.BIT.oemis == BASE_CFG_ENABLE) { /* Overflow error interrupt */ + error |= uartHandle->baseAddress->UART_MIS.BIT.oemis; + uartHandle->baseAddress->UART_ICR.BIT.oeic = BASE_CFG_ENABLE; + } else if (uartHandle->baseAddress->UART_MIS.BIT.bemis == BASE_CFG_ENABLE) { /* Break error interrupt */ + error |= uartHandle->baseAddress->UART_MIS.BIT.bemis; + uartHandle->baseAddress->UART_ICR.BIT.beic = BASE_CFG_ENABLE; + } else if (uartHandle->baseAddress->UART_MIS.BIT.pemis == BASE_CFG_ENABLE) { /* Check error interrupt */ + error |= uartHandle->baseAddress->UART_MIS.BIT.pemis; + uartHandle->baseAddress->UART_ICR.BIT.peic = BASE_CFG_ENABLE; + } else if (uartHandle->baseAddress->UART_MIS.BIT.femis == BASE_CFG_ENABLE) { /* Frame error interrupt */ + error |= uartHandle->baseAddress->UART_MIS.BIT.femis; + uartHandle->baseAddress->UART_ICR.BIT.feic = BASE_CFG_ENABLE; + } + if (error != 0x00) { + uartHandle->errorType = error; + if (uartHandle->rxMode == UART_MODE_INTERRUPT && uartHandle->userCallBack.TransmitItErrorCallBack != NULL) { + uartHandle->userCallBack.TransmitItErrorCallBack(uartHandle); + } + } + return; +} + +/** + * @brief UART Interrupt service processing function. + * @param handle UART handle. + * @retval None. + */ +void HAL_UART_IrqHandler(void *handle) +{ + UART_ASSERT_PARAM(handle != NULL); + UART_Handle *uartHandle = (UART_Handle *)handle; + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + /* when tx interrupt is generated */ + if ((uartHandle->baseAddress->UART_MIS.BIT.txmis == 0x01) || + (uartHandle->baseAddress->UART_MIS.BIT.txfeis == 0x01)) { + WriteITCallBack(uartHandle); + } + /* when rx interrupt is generated */ + if ((uartHandle->baseAddress->UART_MIS.BIT.rxmis == 0x01 || uartHandle->baseAddress->UART_MIS.BIT.rtmis == 0x01) || + (uartHandle->baseAddress->UART_MIS.BIT.rxfneis == 0x1)) { + ReadITCallBack(uartHandle); + } + /* when charter match interrupt is generated */ + if (uartHandle->baseAddress->UART_MIS.BIT.cmis == 0x01) { + CharterMatchCallBack(uartHandle); + } + /* when baud detect interrupt is generated */ + if (uartHandle->baseAddress->UART_MIS.BIT.abdcis == 0x01 || uartHandle->baseAddress->UART_MIS.BIT.abdeis == 0x01) { + BaudDetectCallBack(uartHandle); + } + /* when error interrupt is generated */ + if ((uartHandle->baseAddress->UART_MIS.reg & 0x780) != 0) { + ErrorServiceCallback(uartHandle); + } + return; +} + +/** + * @brief User callback function registration interface. + * @param uartHandle UART handle. + * @param typeID Id of callback function type, @ref UART_CallbackFun_Type + * @param pCallback pointer of the specified callbcak function, @ref UART_CallbackType + * @retval BASE_StatusType: OK, ERROR. + */ +BASE_StatusType HAL_UART_RegisterCallBack(UART_Handle *uartHandle, UART_CallbackFun_Type typeID, + UART_CallbackType pCallback) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + switch (typeID) { + case UART_WRITE_IT_FINISH: + uartHandle->userCallBack.WriteItFinishCallBack = pCallback; /* Write INT finish callback register */ + break; + case UART_READ_IT_FINISH: + uartHandle->userCallBack.ReadItFinishCallBack = pCallback; /* Read INT finish callback register */ + break; + case UART_WRITE_DMA_FINISH: + uartHandle->userCallBack.WriteDmaFinishCallBack = pCallback; /* DMA write finish callback register */ + break; + case UART_READ_DMA_FINISH: + uartHandle->userCallBack.ReadDmaFinishCallBack = pCallback; /* DMA read finish callback register */ + break; + case UART_TRNS_IT_ERROR: + uartHandle->userCallBack.TransmitItErrorCallBack = pCallback; /* INT Trans error callback register */ + break; + case UART_TRNS_DMA_ERROR: + uartHandle->userCallBack.TransmitDmaErrorCallBack = pCallback; /* DMA Trans error callback register */ + break; + case UART_BAUD_DETECT_FINISH: + uartHandle->userCallBack.BaudDetectSuccessCallBack = pCallback; /* Baud detect finish callback register */ + break; + case UART_BAUD_DETECT_ERROR: + uartHandle->userCallBack.BaudDetectErrorCallBack = pCallback; /* Baud detect error callback register */ + break; + case UART_CHARACTER_MATCH: + uartHandle->userCallBack.CharacterMatchCallBack = pCallback; /* character match callback register */ + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief UART DAM(rx to memory), cyclically stores data to specified memory(saveData). + * @param uartHandle UART handle. + * @param saveData Address of the data buff to be sent. + * @param tempNode DMA Link List, @ref DMA_LinkList + * @param dataLength number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_ReadDMAAndCyclicallyStored(UART_Handle *uartHandle, unsigned char *saveData, + DMA_LinkList *tempNode, unsigned int dataLength) +{ + /* Param check */ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(tempNode != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_ASSERT_PARAM(saveData != NULL); + UART_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(uartHandle->rxMode == UART_MODE_DMA, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(IsDmaChannelNum(uartHandle->uartDmaRxChn) == true, BASE_STATUS_ERROR); + UART_ASSERT_PARAM(uartHandle->dmaHandle != NULL); + + unsigned int channel = uartHandle->uartDmaRxChn; + if (uartHandle->rxState == UART_STATE_READY) { + uartHandle->rxState = UART_STATE_BUSY_RX; + uartHandle->baseAddress->UART_IMSC.BIT.rxim = BASE_CFG_DISABLE; /* Disable RX interrupt bit */ + uartHandle->rxbuff = saveData; + uartHandle->rxBuffSize = dataLength; + + /* Init DAM Channel Params */ + DMA_ChannelParam dmaParams; + dmaParams.direction = uartHandle->dmaHandle->DMA_Channels[channel].direction; + dmaParams.srcAddrInc = uartHandle->dmaHandle->DMA_Channels[channel].srcAddrInc; + dmaParams.destAddrInc = uartHandle->dmaHandle->DMA_Channels[channel].destAddrInc; + dmaParams.srcPeriph = uartHandle->dmaHandle->DMA_Channels[channel].srcPeriph; + dmaParams.destPeriph = uartHandle->dmaHandle->DMA_Channels[channel].destPeriph; + dmaParams.srcWidth = uartHandle->dmaHandle->DMA_Channels[channel].srcWidth; + dmaParams.destWidth = uartHandle->dmaHandle->DMA_Channels[channel].destWidth; + dmaParams.srcBurst = uartHandle->dmaHandle->DMA_Channels[channel].srcBurst; + dmaParams.destBurst = uartHandle->dmaHandle->DMA_Channels[channel].destBurst; + + /* Initialize List Node */ + if (HAL_DMA_InitNewNode(tempNode, &dmaParams, (uintptr_t)(void *)&(uartHandle->baseAddress->UART_DR), \ + (uintptr_t)(void *)uartHandle->rxbuff, dataLength) != BASE_STATUS_OK) { + uartHandle->rxState = UART_STATE_READY; + return BASE_STATUS_ERROR; + } + if (HAL_DMA_ListAddNode(tempNode, tempNode) != BASE_STATUS_OK) { + uartHandle->rxState = UART_STATE_READY; + return BASE_STATUS_ERROR; + } + + /* Can not masking overflow error, break error, check error, frame error interrupt */ + if (HAL_DMA_StartListTransfer(uartHandle->dmaHandle, tempNode, channel) != BASE_STATUS_OK) { + uartHandle->rxState = UART_STATE_READY; + return BASE_STATUS_ERROR; + } + uartHandle->baseAddress->UART_DMACR.BIT.rxdmae = BASE_CFG_ENABLE; /* Enable RX_DMA bit */ + } else { + /* Rx not ready */ + return BASE_STATUS_BUSY; + } + /* All done */ + return BASE_STATUS_OK; +} + +/** + * @brief Obtains offset address of DMA transfer address relative to specified memory (rxbuff). + * @param uartHandle UART handle. + * @retval offset address of DMA transfer address relative to specified memory (rxbuff). + */ +unsigned int HAL_UART_ReadDMAGetPos(UART_Handle *uartHandle) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(uartHandle->dmaHandle != NULL); + UART_ASSERT_PARAM(uartHandle->rxbuff != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_PARAM_CHECK_WITH_RET(IsDmaChannelNum(uartHandle->uartDmaRxChn) == true, BASE_STATUS_ERROR); + UART_ASSERT_PARAM(uartHandle->dmaHandle->DMA_Channels[uartHandle->uartDmaRxChn].channelAddr != NULL); + unsigned int writePos = 0; + /* Obtain the read destination address */ + unsigned int readAddress = uartHandle->dmaHandle->\ + DMA_Channels[uartHandle->uartDmaRxChn].channelAddr->DMA_Cn_DEST_ADDR.reg; + if (readAddress > (uintptr_t)uartHandle->rxbuff) { + writePos = readAddress - (uintptr_t)uartHandle->rxbuff; /* Number of characters currently transferred */ + } else { + writePos = 0; + } + return writePos; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/uart/src/uart_ex.c b/vendor/xinlingyu_92_3061M/Project/drivers/uart/src/uart_ex.c new file mode 100644 index 0000000000000000000000000000000000000000..dd93b7c2998b1504429d1381253285b3de578e39 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/uart/src/uart_ex.c @@ -0,0 +1,142 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file uart_ex.c + * @author MCU Driver Team + * @brief UART module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the UART. + * + Initialization and de-initialization functions. + * + Peripheral send and receive functions in blocking mode. + * + Peripheral send and receive functions in interrupt mode. + * + Peripheral send and receive functions in DMA mode. + * + Peripheral stop sending and receiving functions in interrupt/DMA mode. + * + Interrupt callback function and user registration function. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "uart_ex.h" +/* Macro definitions ---------------------------------------------------------*/ + +/** + * @brief Open the character matching function of the UART RX and set the matching character. + * @param uartHandle UART handle. + * @param ch Characters to be matched. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_UART_OpenCharacterMatchEx(UART_Handle *uartHandle, unsigned char ch) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + uartHandle->baseAddress->UART_IMSC.BIT.cmim = BASE_CFG_ENABLE; + uartHandle->baseAddress->UART_CHARMATCH.BIT.chamat = (unsigned int)ch; /* Sets the matching character. */ + uartHandle->baseAddress->UART_CHARMATCH.BIT.cmen = BASE_CFG_ENABLE; + return BASE_STATUS_OK; +} + +/** + * @brief Close the character matching function of the UART RX. + * @param uartHandle UART handle. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_UART_CloseCharacterMatchEx(UART_Handle *uartHandle) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + uartHandle->baseAddress->UART_CHARMATCH.BIT.cmen = BASE_CFG_DISABLE; + uartHandle->baseAddress->UART_IMSC.BIT.cmim = BASE_CFG_DISABLE; /* Turn off character matching */ + return BASE_STATUS_OK; +} + +/** + * @brief Enable the UART to automatically identify the baud rate and enable the corresponding interrupt. + * @param uartHandle UART handle. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_UART_EnableBaudDetectionEx(UART_Handle *uartHandle) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + uartHandle->baseAddress->UART_CR.BIT.txe = BASE_CFG_DISABLE; + uartHandle->baseAddress->UART_CR.BIT.rxe = BASE_CFG_DISABLE; /* Disable TX and RX first */ + uartHandle->baseAddress->UART_IMSC.BIT.abdeim = BASE_CFG_ENABLE; + uartHandle->baseAddress->UART_IMSC.BIT.abdcim = BASE_CFG_ENABLE; + uartHandle->baseAddress->UART_ABDEN.BIT.abden = BASE_CFG_ENABLE; + return BASE_STATUS_OK; +} + +/** + * @brief Disable the UART to automatically identify the baud rate. + * @param uartHandle UART handle. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_UART_DisableBaudDetectionEx(UART_Handle *uartHandle) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + uartHandle->baseAddress->UART_ABDEN.BIT.abden = BASE_CFG_DISABLE; + uartHandle->baseAddress->UART_IMSC.BIT.abdeim = BASE_CFG_DISABLE; + uartHandle->baseAddress->UART_IMSC.BIT.abdcim = BASE_CFG_DISABLE; + uartHandle->baseAddress->UART_CR.BIT.txe = BASE_CFG_ENABLE; /* Enable TX */ + uartHandle->baseAddress->UART_CR.BIT.rxe = BASE_CFG_ENABLE; /* Enable RX */ + return BASE_STATUS_OK; +} + +/** + * @brief Configuring the upper limit of Rx timeout. + * @param uartHandle UART handle. + * @param cntOfBit timeout is defined as the time spent in transmitting N bits, numer of N is cntOfBit. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_UART_SetRxWaiteTimeEx(UART_Handle *uartHandle, unsigned int cntOfBit) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_PARAM_CHECK_WITH_RET(cntOfBit <= 0xFFFFFF, BASE_STATUS_ERROR); + uartHandle->baseAddress->UART_RTCFG.reg = cntOfBit; /* Set wait time */ + return BASE_STATUS_OK; +} + +/** + * @brief Sets UART oversampling multiple. + * @param uartHandle UART handle. + * @param multiple Oversampling multiple, @ref UART_OversampleMultiple + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_UART_SetOversampleMultipleEx(UART_Handle *uartHandle, UART_OversampleMultiple multiple) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_PARAM_CHECK_WITH_RET(IsUartOversampleMultiple(multiple), BASE_STATUS_ERROR); + uartHandle->baseAddress->UART_SPCFG.BIT.spcfg = multiple; /* Oversample setting */ + return BASE_STATUS_OK; +} + +/** + * @brief Sets the first bit of the character transmitted in the UART transmission. + * @param uartHandle UART handle. + * @param mode Sequence mode : LSB/MSB, @ref UART_SequenceMode + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_UART_SetDataSequenceModeEx(UART_Handle *uartHandle, UART_SequenceMode mode) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_PARAM_CHECK_WITH_RET(IsUartSequenceMode(mode), BASE_STATUS_ERROR); + uartHandle->baseAddress->UART_DS.BIT.msbfirst = mode; /* Data sequence setting */ + return BASE_STATUS_OK; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/wwdg/common/inc/wwdg.h b/vendor/xinlingyu_92_3061M/Project/drivers/wwdg/common/inc/wwdg.h new file mode 100644 index 0000000000000000000000000000000000000000..ecef61125ddb2175ffc3edd7aa9efefeab24cfce --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/wwdg/common/inc/wwdg.h @@ -0,0 +1,99 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file wwdg.h + * @author MCU Driver Team + * @brief WWDG module driver + * @details The header file contains the following declaration: + * + WWDG handle structure definition. + * + Initialization functions. + * + WWDG Set And Get Functions. + * + Interrupt Handler Functions. + */ + +#ifndef McuMagicTag_WWDG_H +#define McuMagicTag_WWDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "wwdg_ip.h" +/** + * @defgroup WWDG WWDG + * @brief WWDG module. + * @{ + */ + +/** + * @defgroup WWDG_Common WWDG Common + * @brief WWDG common external module. + * @{ + */ + +/** + * @defgroup WWDG_Handle_Definition WWDG Handle Definition + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ +typedef void (* WWDG_CallbackType)(void *handle); + +/** + * @brief WWDG handle structure definition. + */ +typedef struct _WWDG_Handle { + WWDG_RegStruct *baseAddress; /**< WWDG Registers address. */ + unsigned int timeValue; /**< WWDG time value. */ + unsigned int windowValue; /**< WWDG window value. */ + unsigned int freqDivValue; /**< WWDG freq div value. */ + WWDG_TimeType timeType; /**< WWDG time type. */ + bool enableIT; /**< true:enable false:disable interrupt. */ + WWDG_UserCallBack userCallBack; /**< User callback */ + WWDG_ExtendHandle handleEx; /**< WWDG extend parameter */ +} WWDG_Handle; + +/** + * @} + */ + +/** + * @defgroup WWDG_API_Declaration WWDG HAL API + * @{ + */ + +BASE_StatusType HAL_WWDG_Init(WWDG_Handle *handle); +void HAL_WWDG_SetTimeValue(WWDG_Handle *handle, unsigned int timeValue, WWDG_TimeType timeType); +unsigned int HAL_WWDG_GetLoadValue(WWDG_Handle *handle); +unsigned int HAL_WWDG_GetWindowValue(WWDG_Handle *handle); +unsigned int HAL_WWDG_GetCounterValue(WWDG_Handle *handle); +void HAL_WWDG_Refresh(WWDG_Handle *handle); +void HAL_WWDG_Start(WWDG_Handle *handle); +void HAL_WWDG_Stop(WWDG_Handle *handle); +void HAL_WWDG_RegisterCallback(WWDG_Handle *handle, WWDG_CallbackType callBackFunc); +void HAL_WWDG_IrqHandler(void *handle); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_WWDG_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/wwdg/inc/wwdg_ex.h b/vendor/xinlingyu_92_3061M/Project/drivers/wwdg/inc/wwdg_ex.h new file mode 100644 index 0000000000000000000000000000000000000000..6f520c3bd6b39a21e414e39d3b87f552d4228b88 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/wwdg/inc/wwdg_ex.h @@ -0,0 +1,49 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file wwdg_ex.h + * @author MCU Driver Team + * @brief WWDG module driver + * @details The header file contains the following declaration: + * + WWDG Set And Get Functions. + */ + +#ifndef McuMagicTag_WWDG_EX_H +#define McuMagicTag_WWDG_EX_H + +/* Includes ------------------------------------------------------------------*/ +#include "wwdg.h" +/** + * @addtogroup WWDG_IP + * @{ + */ + +/** + * @defgroup WWDG_API_EX_Declaration WWDG HAL API EX + * @{ + */ +void HAL_WWDG_EnableWindowModeEx(WWDG_Handle *handle); +void HAL_WWDG_DisableWindowModeEx(WWDG_Handle *handle); + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_WWDG_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/wwdg/inc/wwdg_ip.h b/vendor/xinlingyu_92_3061M/Project/drivers/wwdg/inc/wwdg_ip.h new file mode 100644 index 0000000000000000000000000000000000000000..35bf7ac5b365aa381c7e745d5d9ef0ce054350bc --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/wwdg/inc/wwdg_ip.h @@ -0,0 +1,516 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file wwdg_ip.h + * @author MCU Driver Team + * @brief WWDG module driver + * @details The header file contains the following declaration: + * + WWDG configuration enums. + * + WWDG register structures. + * + WWDG DCL Functions. + * + Parameters check functions. + */ + +#ifndef McuMagicTag_WWDG_IP_H +#define McuMagicTag_WWDG_IP_H + +/* Includes ------------------------------------------------------------------*/ +#include "baseinc.h" + +/* Macro definition */ + +#ifdef WWDG_PARAM_CHECK + #define WWDG_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM + #define WWDG_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET + #define WWDG_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else + #define WWDG_ASSERT_PARAM(para) ((void)0U) + #define WWDG_PARAM_CHECK_NO_RET(para) ((void)0U) + #define WWDG_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +/** + * @addtogroup WWDG + * @{ + */ + +/** + * @defgroup WWDG_IP WWDG_IP + * @brief WWDG_IP: wwdg_v1. + * @{ + */ + +/** + * @defgroup WWDG_Param_Def WWDG Parameters Definition + * @brief Description of WWDG configuration parameters. + * @{ + */ +/* MACRO definitions -------------------------------------------------------*/ +#define FREQ_CONVERT_MS_UNIT 1000 +#define FREQ_CONVERT_US_UNIT 1000000 +#define WWDG_UNLOCK_REG_CMD 0x55 /* 0x55 CMD: key equal 0x55 will unlock all reg write function */ +#define WWDG_LOCK_REG_CMD 0xFF /* 0xFF CMD: key not equal 0x55 will lock reg write function except key reg */ + +/* Typedef definitions -------------------------------------------------------*/ +typedef enum { + WWDG_TIME_UNIT_TICK = 0x00000000U, + WWDG_TIME_UNIT_S = 0x00000001U, + WWDG_TIME_UNIT_MS = 0x00000002U, + WWDG_TIME_UNIT_US = 0x00000003U +} WWDG_TimeType; + +typedef enum { + WWDG_FREQ_DIV_NONE = 0x00000000U, + WWDG_FREQ_DIV_2 = 0x00000001U, + WWDG_FREQ_DIV_4 = 0x00000002U, + WWDG_FREQ_DIV_8 = 0x00000003U, + WWDG_FREQ_DIV_16 = 0x00000004U, + WWDG_FREQ_DIV_32 = 0x00000005U, + WWDG_FREQ_DIV_64 = 0x00000006U, + WWDG_FREQ_DIV_128 = 0x00000007U, + WWDG_FREQ_DIV_256 = 0x00000008U, + WWDG_FREQ_DIV_512 = 0x00000009U, + WWDG_FREQ_DIV_1024 = 0x0000000AU, + WWDG_FREQ_DIV_2048 = 0x0000000BU, + WWDG_FREQ_DIV_4096 = 0x0000000CU, + WWDG_FREQ_DIV_8192 = 0x0000000DU, + WWDG_FREQ_DIV_MAX +} WWDG_FreqDivType; + +/** + * @brief WWDG extend handle. + */ +typedef struct _WWDG_ExtendHandle { +} WWDG_ExtendHandle; + +/** + * @brief WWDG user callback. + */ +typedef struct { + void (* CallbackFunc)(void *handle); /**< WWDG callback Function */ +} WWDG_UserCallBack; +/** + * @} + */ + +/** + * @defgroup WWDG_Reg_Def WWDG Register Definition + * @brief Description WWDG register mapping structure. + * @{ + */ +/** + * @brief WWDG load init value. + */ +typedef union { + unsigned int reg; + struct { + unsigned int wwdg_load : 16; /**< init value. */ + unsigned int reserved0 : 16; + } BIT; +} volatile WWDG_LOAD_REG; + +/** + * @brief WWDG get current value. + */ +typedef union { + unsigned int reg; + struct { + unsigned int wwdg_value : 16; /**< current value. */ + unsigned int reserved0 : 16; + } BIT; +} volatile WWDG_VALUE_REG; + +/** + * @brief WWDG set window value. + */ +typedef union { + unsigned int reg; + struct { + unsigned int wwdg_window : 16; /**< window value. */ + unsigned int reserved0 : 16; + } BIT; +} volatile WWDG_WINDOW_REG; + +/** + * @brief WWDG cmd function value. + */ +typedef union { + unsigned int reg; + struct { + unsigned int wwdg_key : 8; /**< cmd function value. */ + unsigned int reserved0 : 24; + } BIT; +} volatile WWDG_KEY_REG; + +/** + * @brief WWDG clk pre div value. + */ +typedef union { + unsigned int reg; + struct { + unsigned int wwdg_pre_div : 4; /**< clk pre div value. */ + unsigned int reserved0 : 28; + } BIT; +} volatile WWDG_PRE_DIV_REG; + +/** + * @brief WWDG enable interrupt and reset. + */ +typedef union { + unsigned int reg; + struct { + unsigned int inten : 1; /**< enable interrupt. */ + unsigned int resen : 1; /**< enable reset. */ + unsigned int window_mode_en : 1; /**< enable window mode. */ + unsigned int reserved0 : 29; + } BIT; +} volatile WWDG_CONTROL_REG; + +/** + * @brief WWDG orignal interrupt signal. + */ +typedef union { + unsigned int reg; + struct { + unsigned int wwdogris : 1; /**< original interrupt status. */ + unsigned int reserve : 31; + } BIT; +} volatile WWDG_RIS_REG; + +/** + * @brief mask interrupt signal. + */ +typedef union { + unsigned int reg; + struct { + unsigned int wwdogmis : 1; /**< maske interrupt status. */ + unsigned int reserve : 31; + } BIT; +} volatile WWDG_MIS_REG; + +/** + * @brief WWDG Register Structure definition. + */ +typedef struct { + WWDG_LOAD_REG WWDOG_LOAD; /**< WWDG load value register. */ + WWDG_VALUE_REG WWDOG_VALUE; /**< WWDG current value register. */ + WWDG_WINDOW_REG WWDOG_WINDOW; /**< WWDG Window value register. */ + WWDG_KEY_REG WWDOG_KEY; /**< WWDG instruction word register. */ + WWDG_PRE_DIV_REG WWDOG_PRE_DIV; /**< WWDG prescale register. */ + WWDG_CONTROL_REG WWDOG_CONTROL; /**< WWDG interrupt, reset and window enable register. */ + WWDG_RIS_REG WWDOG_RIS; /**< WWDG orignal interrupt register. */ + WWDG_MIS_REG WWDOG_MIS; /**< WWDG mask interrupt register. */ +} volatile WWDG_RegStruct; + +/** + * @} + */ + +/** + * @brief Setting the load value of the WWDG counter. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @param loadValue Load value of the WWDG counter. + * @retval None. + */ +static inline void DCL_WWDG_SetLoadValue(WWDG_RegStruct *wwdgx, unsigned short loadValue) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + wwdgx->WWDOG_KEY.BIT.wwdg_key = WWDG_UNLOCK_REG_CMD; + wwdgx->WWDOG_LOAD.BIT.wwdg_load = loadValue; + wwdgx->WWDOG_KEY.BIT.wwdg_key = WWDG_LOCK_REG_CMD; +} + +/** + * @brief Getting the load value of the WWDG load register. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @retval unsigned short WWDG load value. + */ +static inline unsigned short DCL_WWDG_GetLoadValue(const WWDG_RegStruct *wwdgx) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + return wwdgx->WWDOG_LOAD.BIT.wwdg_load; +} + +/** + * @brief Getting the value of the WWDG counter register. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @retval unsigned short WWDG counter value. + */ +static inline unsigned short DCL_WWDG_GetCounterValue(const WWDG_RegStruct *wwdgx) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + return wwdgx->WWDOG_VALUE.BIT.wwdg_value; +} + +/** + * @brief Setting window value. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @param windowValue window value of the WWDG counter. + * @retval None. + */ +static inline void DCL_WWDG_SetWindowValue(WWDG_RegStruct *wwdgx, unsigned short windowValue) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + wwdgx->WWDOG_KEY.BIT.wwdg_key = WWDG_UNLOCK_REG_CMD; + wwdgx->WWDOG_WINDOW.BIT.wwdg_window = windowValue; + wwdgx->WWDOG_KEY.BIT.wwdg_key = WWDG_LOCK_REG_CMD; +} + +/** + * @brief Getting window value, windowValue need bigger than 4. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @param windowValue window value of the WWDG counter. + * @retval unsigned short wwdg window value. + */ +static inline unsigned short DCL_WWDG_GetWindowValue(WWDG_RegStruct *wwdgx) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + return wwdgx->WWDOG_WINDOW.BIT.wwdg_window; +} + +/** + * @brief Start wwdg function. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @retval None. + */ +static inline void DCL_WWDG_Start(WWDG_RegStruct *wwdgx) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + wwdgx->WWDOG_KEY.BIT.wwdg_key = 0xCC; /* 0xCC CMD: start wwdg function */ +} + +/** + * @brief Stop wwdg function. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @retval None. + */ +static inline void DCL_WWDG_Stop(WWDG_RegStruct *wwdgx) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + wwdgx->WWDOG_KEY.BIT.wwdg_key = 0xDD; /* 0xDD CMD: stop wwdg function */ +} + +/** + * @brief Clear interrupt and reload watchdog counter value. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @retval None. + */ +static inline void DCL_WWDG_Refresh(WWDG_RegStruct *wwdgx) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + wwdgx->WWDOG_KEY.BIT.wwdg_key = 0xAA; /* 0xAA CMD: clear interrupt and reload value */ +} + +/** + * @brief Disable write and read WWDG registers except WWDG_LOCK. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @retval None. + */ +static inline void DCL_WWDG_LockReg(WWDG_RegStruct *wwdgx) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + wwdgx->WWDOG_KEY.BIT.wwdg_key = 0xFF; /* 0xFF CMD: key not equal 0x55 will lock reg write function except key reg */ +} + +/** + * @brief Enable write and read WWDG registers. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @retval None. + */ +static inline void DCL_WWDG_UnlockReg(WWDG_RegStruct *wwdgx) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + wwdgx->WWDOG_KEY.BIT.wwdg_key = 0x55; /* 0x55 CMD: key equal 0x55 will unlock all reg write function */ +} + +/** + * @brief Setting freq div value, value need litter than 13. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @param freqDiv freqDiv value of the WWDG counter. + * @retval None. + */ +static inline void DCL_WWDG_SetFreqDivValue(WWDG_RegStruct *wwdgx, WWDG_FreqDivType freqDiv) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + WWDG_PARAM_CHECK_NO_RET(freqDiv < WWDG_FREQ_DIV_MAX); + wwdgx->WWDOG_KEY.BIT.wwdg_key = WWDG_UNLOCK_REG_CMD; + wwdgx->WWDOG_PRE_DIV.BIT.wwdg_pre_div = freqDiv; /* freqDiv parameters set */ + wwdgx->WWDOG_KEY.BIT.wwdg_key = WWDG_UNLOCK_REG_CMD; +} + +/** + * @brief Getting freq div value, value need litter than 13. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @param freqDiv freqDiv value of the WWDG counter. + * @retval None. + */ +static inline unsigned char DCL_WWDG_GetFreqDivValue(WWDG_RegStruct *wwdgx) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + return wwdgx->WWDOG_PRE_DIV.BIT.wwdg_pre_div; +} + +/** + * @brief Enable reset signal. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @retval None. + */ +static inline void DCL_WWDG_EnableReset(WWDG_RegStruct *wwdgx) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + wwdgx->WWDOG_KEY.BIT.wwdg_key = WWDG_UNLOCK_REG_CMD; + wwdgx->WWDOG_CONTROL.BIT.resen = BASE_CFG_SET; + wwdgx->WWDOG_KEY.BIT.wwdg_key = WWDG_LOCK_REG_CMD; +} + +/** + * @brief Disable reset signal. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @retval None. + */ +static inline void DCL_WWDG_DisableReset(WWDG_RegStruct *wwdgx) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + wwdgx->WWDOG_KEY.BIT.wwdg_key = WWDG_UNLOCK_REG_CMD; + wwdgx->WWDOG_CONTROL.BIT.resen = BASE_CFG_UNSET; + wwdgx->WWDOG_KEY.BIT.wwdg_key = WWDG_LOCK_REG_CMD; +} + +/** + * @brief Start watchdog and enable interrupt signal. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @retval None. + */ +static inline void DCL_WWDG_EnableInterrupt(WWDG_RegStruct *wwdgx) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + wwdgx->WWDOG_KEY.BIT.wwdg_key = WWDG_UNLOCK_REG_CMD; + wwdgx->WWDOG_CONTROL.BIT.inten = BASE_CFG_SET; + wwdgx->WWDOG_KEY.BIT.wwdg_key = WWDG_LOCK_REG_CMD; +} + +/** + * @brief Disable interrupt signal. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @retval None. + */ +static inline void DCL_WWDG_DisableInterrupt(WWDG_RegStruct *wwdgx) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + wwdgx->WWDOG_KEY.BIT.wwdg_key = WWDG_UNLOCK_REG_CMD; + wwdgx->WWDOG_CONTROL.BIT.inten = BASE_CFG_UNSET; + wwdgx->WWDOG_KEY.BIT.wwdg_key = WWDG_LOCK_REG_CMD; +} + +/** + * @brief Ensable Windows mode. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @retval None. + */ +static inline void DCL_WWDG_EnableWindowsMode(WWDG_RegStruct *wwdgx) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + wwdgx->WWDOG_KEY.BIT.wwdg_key = WWDG_UNLOCK_REG_CMD; + wwdgx->WWDOG_CONTROL.BIT.window_mode_en = BASE_CFG_SET; + wwdgx->WWDOG_KEY.BIT.wwdg_key = WWDG_LOCK_REG_CMD; +} + +/** + * @brief Disable Windows mode. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @retval None. + */ +static inline void DCL_WWDG_DisableWindowsMode(WWDG_RegStruct *wwdgx) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + wwdgx->WWDOG_KEY.BIT.wwdg_key = WWDG_UNLOCK_REG_CMD; + wwdgx->WWDOG_CONTROL.BIT.window_mode_en = BASE_CFG_UNSET; + wwdgx->WWDOG_KEY.BIT.wwdg_key = WWDG_LOCK_REG_CMD; +} + +/** + * @brief Get Windows mode. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @retval bool is enable or disable. + */ +static inline bool DCL_WWDG_GetWindowsMode(WWDG_RegStruct *wwdgx) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + return wwdgx->WWDOG_CONTROL.BIT.window_mode_en; +} + +/** + * @brief Getting value of WWDG RIS register. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @retval unsigned int Value of WWDG RIS register. + */ +static inline unsigned int DCL_WWDG_GetRIS(WWDG_RegStruct *wwdgx) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + return wwdgx->WWDOG_RIS.BIT.wwdogris; +} + +/** + * @brief Getting value of WWDG MIS register. + * @param wwdgx Value of @ref WWDG_RegStruct. + * @retval unsigned int Value of WWDG MIS register. + */ +static inline unsigned int DCL_WWDG_GetMIS(WWDG_RegStruct *wwdgx) +{ + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgx)); + return wwdgx->WWDOG_MIS.BIT.wwdogmis; +} + +/** + * @brief check wwdg time type parameter. + * @param timeType Value of @ref WWDG_TimeType. + * @retval Bool. + */ +static inline bool IsWwdgTimeType(WWDG_TimeType timeType) +{ + return (timeType == WWDG_TIME_UNIT_TICK || + timeType == WWDG_TIME_UNIT_S || + timeType == WWDG_TIME_UNIT_MS || + timeType == WWDG_TIME_UNIT_US); +} + +/** + * @brief check wdg time value parameter. + * @param baseAddress Value of @ref WDG_RegStruct + * @param timeValue time value + * @param timeType Value of @ref WDG_TimeType. + * @retval Bool. + */ +static inline bool IsWwdgTimeValue(WWDG_RegStruct *baseAddress, float timeValue, WWDG_TimeType timeType) +{ + float clockFreq = (float)HAL_CRG_GetIpFreq((void *)baseAddress); + float maxSecond = (float)(0xFFFFFFFF / clockFreq); /* 0xFFFFFFFF max input value */ + return ((timeType == WWDG_TIME_UNIT_TICK && timeValue <= 0xFFFFFFFF) || + (timeType == WWDG_TIME_UNIT_S && maxSecond >= timeValue) || + (timeType == WWDG_TIME_UNIT_MS && maxSecond >= timeValue / FREQ_CONVERT_MS_UNIT) || + (timeType == WWDG_TIME_UNIT_US && maxSecond >= timeValue / FREQ_CONVERT_US_UNIT)); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_WWDG_IP_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/wwdg/src/wwdg.c b/vendor/xinlingyu_92_3061M/Project/drivers/wwdg/src/wwdg.c new file mode 100644 index 0000000000000000000000000000000000000000..aa00350dfa82078b7dc9b88cbdc33b622b34fef0 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/wwdg/src/wwdg.c @@ -0,0 +1,256 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file wwdg.c + * @author MCU Driver Team + * @brief WWDG module driver + * @details This file provides firmware functions to manage the following functionalities of the WWDG. + * + Initialization functions. + * + WWDG Set And Get Functions. + * + Interrupt Handler Functions. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "wwdg.h" + +/* Macro definitions ---------------------------------------------------------*/ +#define WWDG_LOAD_VALUE_LIMIT 65535 +#define WWDG_WINDOW_VALUE_LIMIT 65535 +static unsigned int WWDG_CalculateRegTimeout(WWDG_RegStruct *baseAddress, float timeValue, WWDG_TimeType timeType); + +/** + * @brief Initializing WWDG values + * @param handle Value of @ref WWDG_handle. + * @retval BASE_StatusType: OK, ERROR + */ +BASE_StatusType HAL_WWDG_Init(WWDG_Handle *handle) +{ + WWDG_ASSERT_PARAM(handle != NULL); + WWDG_ASSERT_PARAM(IsWWDGInstance(handle->baseAddress)); + WWDG_PARAM_CHECK_WITH_RET(IsWwdgTimeType(handle->timeType), BASE_STATUS_ERROR); + WWDG_PARAM_CHECK_WITH_RET(IsWwdgTimeValue(handle->baseAddress, handle->timeValue, handle->timeType), + BASE_STATUS_ERROR); + /* The frequency divide value cannot exceed 8192. */ + unsigned int freqDivVal = (handle->freqDivValue > WWDG_FREQ_DIV_MAX) ? WWDG_FREQ_DIV_8192 : handle->freqDivValue; + DCL_WWDG_SetFreqDivValue(handle->baseAddress, freqDivVal); + HAL_WWDG_SetTimeValue(handle, handle->timeValue, handle->timeType); + /* Window mode enable */ + if (handle->baseAddress->WWDOG_CONTROL.BIT.window_mode_en == BASE_CFG_ENABLE) { + unsigned int value = + WWDG_CalculateRegTimeout(handle->baseAddress, handle->windowValue, handle->timeType); + unsigned int freqDiv = DCL_WWDG_GetFreqDivValue(handle->baseAddress); + value = (value / (1 << freqDiv)); + /* The upper limit of the window value is determined. */ + value = (value <= WWDG_WINDOW_VALUE_LIMIT) ? value : WWDG_WINDOW_VALUE_LIMIT; + /* window value only could be set litter than load value */ + value = (value < handle->baseAddress->WWDOG_LOAD.BIT.wwdg_load) ? value : + handle->baseAddress->WWDOG_LOAD.BIT.wwdg_load; + DCL_WWDG_SetWindowValue(handle->baseAddress, value); + } + DCL_WWDG_EnableInterrupt(handle->baseAddress); /* enable interrupt */ + DCL_WWDG_EnableReset(handle->baseAddress); /* enable reset */ + return BASE_STATUS_OK; +} + +/** + * @brief Calculate Reg Timeout. + * @param timeValue Value to be load to wwdg. + * @param timeType Value of @ref WWDG_TimeType. + * @retval unsigned int timeout Value. + */ +static unsigned int WWDG_CalculateRegTimeout(WWDG_RegStruct *baseAddress, float timeValue, WWDG_TimeType timeType) +{ + float clockFreq = (float)HAL_CRG_GetIpFreq((void *)baseAddress); + unsigned int timeoutValue = 0x00000000U; + switch (timeType) { + case WWDG_TIME_UNIT_TICK: /* If the time type is tick, calculate the timeout value. */ + timeoutValue = (unsigned int)timeValue; + break; + case WWDG_TIME_UNIT_S: /* If the time type is s, calculate the timeout value. */ + timeoutValue = (unsigned int)(timeValue * clockFreq); + break; + case WWDG_TIME_UNIT_MS: /* If the time type is ms, calculate the timeout value. */ + timeoutValue = (unsigned int)(timeValue * clockFreq / FREQ_CONVERT_MS_UNIT); + break; + case WWDG_TIME_UNIT_US: /* If the time type is us, calculate the timeout value. */ + timeoutValue = (unsigned int)(timeValue * clockFreq / FREQ_CONVERT_US_UNIT); + break; + default: + break; + } + return timeoutValue; +} + +/** + * @brief Setting the load value of the WWDG counter. + * @param handle Value of @ref WWDG_handle. + * @param timeValue time value of the WWDG counter. + * @param timeType WWDG time type. + * @retval None. + */ +void HAL_WWDG_SetTimeValue(WWDG_Handle *handle, unsigned int timeValue, WWDG_TimeType timeType) +{ + WWDG_ASSERT_PARAM(handle != NULL); + WWDG_ASSERT_PARAM(IsWWDGInstance(handle->baseAddress)); + WWDG_PARAM_CHECK_NO_RET(IsWwdgTimeType(timeType)); + WWDG_PARAM_CHECK_NO_RET(IsWwdgTimeValue(handle->baseAddress, timeValue, timeType)); + /* handle->baseAddress only could be configed WWDG */ + unsigned int value = WWDG_CalculateRegTimeout(handle->baseAddress, timeValue, timeType); + unsigned int freqDiv = DCL_WWDG_GetFreqDivValue(handle->baseAddress); + value = (value / (1 << freqDiv)); + /* The upper limit of the loaded value is determined. */ + value = (value <= WWDG_LOAD_VALUE_LIMIT) ? value : WWDG_LOAD_VALUE_LIMIT; + DCL_WWDG_SetLoadValue(handle->baseAddress, value); +} + +/** + * @brief refresh the WWDG counter. + * @param handle Value of @ref WWDG_handle. + * @retval None. + */ +void HAL_WWDG_Refresh(WWDG_Handle *handle) +{ + WWDG_ASSERT_PARAM(handle != NULL); + WWDG_ASSERT_PARAM(IsWWDGInstance(handle->baseAddress)); + DCL_WWDG_Refresh(handle->baseAddress); +} + +/** + * @brief obtain the load value. + * @param handle Value of @ref WWDG_handle. + * @retval unsigned int time value. + */ +unsigned int HAL_WWDG_GetLoadValue(WWDG_Handle *handle) +{ + WWDG_ASSERT_PARAM(handle != NULL); + WWDG_ASSERT_PARAM(IsWWDGInstance(handle->baseAddress)); + return DCL_WWDG_GetLoadValue(handle->baseAddress); +} + +/** + * @brief Getting the window value of the WWDG counter. + * @param handle Value of @ref WWDG_handle. + * @retval unsigned int the value of window reg value. + */ +unsigned int HAL_WWDG_GetWindowValue(WWDG_Handle *handle) +{ + WWDG_ASSERT_PARAM(handle != NULL); + WWDG_ASSERT_PARAM(IsWWDGInstance(handle->baseAddress)); + /* handle->baseAddress only could be configed WWDG */ + return DCL_WWDG_GetWindowValue(handle->baseAddress); +} + +/** + * @brief Refresh the WWDG counter value. + * @param handle Value of @ref WWDG_handle. + * @retval unsigned int Counter value. + */ +unsigned int HAL_WWDG_GetCounterValue(WWDG_Handle *handle) +{ + WWDG_ASSERT_PARAM(handle != NULL); + WWDG_ASSERT_PARAM(IsWWDGInstance(handle->baseAddress)); + + float res = (float)handle->baseAddress->WWDOG_VALUE.BIT.wwdg_value; + if (res >= 65535) { /* 65535 is WWDG maximum current count */ + return handle->timeValue; + } + unsigned int freq = HAL_CRG_GetIpFreq((void *)handle->baseAddress); + /* check clockFreq not equal zero */ + if (freq == 0) { + return 0; + } + unsigned int freqDiv = DCL_WWDG_GetFreqDivValue(handle->baseAddress); + switch (handle->timeType) { + case WWDG_TIME_UNIT_TICK: + /* Number of tick currently calculated */ + res = res * (1 << freqDiv); + break; + case WWDG_TIME_UNIT_S: + /* Number of seconds currently calculated */ + res = res * (1 << freqDiv) / freq; + break; + case WWDG_TIME_UNIT_MS: + res = res * (1 << freqDiv) * FREQ_CONVERT_MS_UNIT / freq; + break; + case WWDG_TIME_UNIT_US: + /* Number of microseconds currently calculated */ + res = res * (1 << freqDiv) * FREQ_CONVERT_US_UNIT / freq; + break; + default: + break; + } + return (unsigned int)res; +} + +/** + * @brief Start the WWDG count. + * @param handle Value of @ref WWDG_handle. + * @retval None. + */ +void HAL_WWDG_Start(WWDG_Handle *handle) +{ + WWDG_ASSERT_PARAM(handle != NULL); + WWDG_ASSERT_PARAM(IsWWDGInstance(handle->baseAddress)); + DCL_WWDG_Start(handle->baseAddress); +} + +/** + * @brief Stop the WWDG count. + * @param handle Value of @ref WWDG_handle. + * @retval None. + */ +void HAL_WWDG_Stop(WWDG_Handle *handle) +{ + WWDG_ASSERT_PARAM(handle != NULL); + WWDG_ASSERT_PARAM(IsWWDGInstance(handle->baseAddress)); + DCL_WWDG_Stop(handle->baseAddress); +} + +/** + * @brief Register WWDG interrupt callback. + * @param handle Value of @ref WWDG_handle. + * @param callBackFunc Value of @ref WWDG_CallbackType. + * @retval None + */ +void HAL_WWDG_RegisterCallback(WWDG_Handle *handle, WWDG_CallbackType callBackFunc) +{ + WWDG_ASSERT_PARAM(handle != NULL); + WWDG_ASSERT_PARAM(IsWWDGInstance(handle->baseAddress)); + if (callBackFunc != NULL) { + /* Invoke the callback function. */ + handle->userCallBack.CallbackFunc = callBackFunc; + } +} + +/** + * @brief Interrupt handler processing function. + * @param handle WWDG_Handle. + * @retval None. + */ +void HAL_WWDG_IrqHandler(void *handle) +{ + WWDG_Handle *wwdgHandle = (WWDG_Handle *)handle; + WWDG_ASSERT_PARAM(wwdgHandle != NULL); + WWDG_ASSERT_PARAM(IsWWDGInstance(wwdgHandle->baseAddress)); + + if (wwdgHandle->baseAddress->WWDOG_MIS.BIT.wwdogmis == 0x01) { /* Interrupt flag is set, fed dog in callback */ + if (wwdgHandle->userCallBack.CallbackFunc) { + wwdgHandle->userCallBack.CallbackFunc(wwdgHandle); + } + } +} diff --git a/vendor/xinlingyu_92_3061M/Project/drivers/wwdg/src/wwdg_ex.c b/vendor/xinlingyu_92_3061M/Project/drivers/wwdg/src/wwdg_ex.c new file mode 100644 index 0000000000000000000000000000000000000000..36a32b1cc8b900879f4efea624930d4f615505a9 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/drivers/wwdg/src/wwdg_ex.c @@ -0,0 +1,52 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file wwdg_ex.c + * @author MCU Driver Team + * @brief WWDG module driver + * @details This file provides firmware functions to manage the following functionalities of the WWDG. + * + WWDG Set And Get Functions. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "wwdg_ex.h" + +/* Macro definitions ---------------------------------------------------------*/ +/** + * @brief Enable window mode. + * @param handle Value of @ref WWDG_handle. + * @retval None. + */ +void HAL_WWDG_EnableWindowModeEx(WWDG_Handle *handle) +{ + WWDG_ASSERT_PARAM(handle != NULL); + WWDG_ASSERT_PARAM(IsWWDGInstance(handle->baseAddress)); + DCL_WWDG_EnableWindowsMode(handle->baseAddress); +} + +/** + * @brief Disable window mode. + * @param handle Value of @ref WWDG_handle. + * @retval None. + */ +void HAL_WWDG_DisableWindowModeEx(WWDG_Handle *handle) +{ + WWDG_ASSERT_PARAM(handle != NULL); + WWDG_ASSERT_PARAM(IsWWDGInstance(handle->baseAddress)); + DCL_WWDG_DisableWindowsMode(handle->baseAddress); +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/adc_calibra/mcs_adcCalibr.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/adc_calibra/mcs_adcCalibr.c new file mode 100644 index 0000000000000000000000000000000000000000..a4fdeb63c5154c4493a0fcd5804b0cfe8f7a1492 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/adc_calibra/mcs_adcCalibr.c @@ -0,0 +1,98 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_adcCalibr.c + * @author MCU Algorithm Team + * @brief This file provides adc bias calibration function. 0722-7 + */ +#include "mcs_adcCalibr.h" +#include "mcs_assert.h" + + +/** + * @brief Get ADC result when ADC conversion completes. + * @param adcCalibr ADC calibration value. + * @param soc ID of SOC. + * @retval None. + */ +static unsigned int ADCCALIBR_GetSocResult(ADC_Handle *adcHandle, unsigned int soc) +{ + MCS_ASSERT_PARAM(adcHandle != NULL); + /* wait for ADC conversion complete */ + while (1) { + /* Check ADC conversion if completes. */ + if (HAL_ADC_CheckSocFinish(adcHandle, soc) == BASE_STATUS_OK) { + break; + } + } + return DCL_ADC_ReadSOCxResult(adcHandle->baseAddress, soc); +} + +/** + * @brief ADC calibration initialization. + * @param adcCalibr ADC calibration value. + * @retval None. + */ +void ADCCALIBR_Init(ADC_CALIBR_Handle *adcCalibr) +{ + MCS_ASSERT_PARAM(adcCalibr != NULL); + adcCalibr->adcShiftAccu = 0; + adcCalibr->cnt = 0; + adcCalibr->state = ADC_CALIBR_NOT_FINISH; +} + +/** + * @brief Compute current sampling adc offset. + * @param adcCalibr ADC calibration handle. + * @param adcHandle ADC handle. + * @param soc ID of SOC. + * @retval offset val. + */ +unsigned int ADCCALIBR_Exec(ADC_CALIBR_Handle *adcCalibr, ADC_Handle *adcHandle, unsigned int soc) +{ + MCS_ASSERT_PARAM(adcCalibr != NULL); + MCS_ASSERT_PARAM(adcHandle != NULL); + MCS_ASSERT_PARAM(adcCalibr->adcShiftAccu <= 4096 * ADC_CNT_POINTS); /* 4096: 12-bit adc precision. */ + adcCalibr->cnt++; + /* sum of 50 points value */ + if (adcCalibr->cnt > ADC_CNT_POINTS) { + adcCalibr->cnt = ADC_CNT_POINTS; + adcCalibr->state = ADC_CALIBR_FINISH; + return (unsigned int)((float)(adcCalibr->adcShiftAccu) / (float)ADC_CNT_POINTS); + } else { + adcCalibr->adcShiftAccu += ADCCALIBR_GetSocResult(adcHandle, soc); + adcCalibr->state = ADC_CALIBR_NOT_FINISH; + return 0; + } + /* Returns the offset sampling average */ + return 0; +} + +/** + * @brief Returns the motor control status based on whether the calibration is complete or not. + * @param adcCalibr ADC calibration handle. + * @retval bool. + */ +bool ADCCALIBR_IsFinish(ADC_CALIBR_Handle *adcCalibr) +{ + MCS_ASSERT_PARAM(adcCalibr != NULL); + if (adcCalibr->state == ADC_CALIBR_FINISH) { + return true; + } + + return false; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/adc_calibra/mcs_adcCalibr.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/adc_calibra/mcs_adcCalibr.h new file mode 100644 index 0000000000000000000000000000000000000000..87a21c0074b7507b2b256cf93de314208f033106 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/adc_calibra/mcs_adcCalibr.h @@ -0,0 +1,55 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_adcCalibr.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration for adc bias calibration function. + */ +#ifndef McuMagicTag_MCS_ADCCALIB_H +#define McuMagicTag_MCS_ADCCALIB_H + +#include "adc.h" +#include "typedefs.h" + +/* Macro definitions --------------------------------------------------------------------------- */ +#define ADC_CNT_POINTS 50 /* the number of continuous adc results for calibration */ + +/** + * @brief ADC temperature calibration state. + */ +typedef enum { + ADC_CALIBR_NOT_FINISH = 0, + ADC_CALIBR_FINISH +} ADC_CALIBR_State; + +/** + * @brief Adc temperature shift calibration structure. + */ +typedef struct { + unsigned int adcShiftAccu; + unsigned int cnt; + ADC_CALIBR_State state; +} ADC_CALIBR_Handle; + + +void ADCCALIBR_Init(ADC_CALIBR_Handle *adcCalibr); + +unsigned int ADCCALIBR_Exec(ADC_CALIBR_Handle *adcCalibr, ADC_Handle *adcHandle, unsigned int soc); + +bool ADCCALIBR_IsFinish(ADC_CALIBR_Handle *adcCalibr); + +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/brake/mcs_brake.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/brake/mcs_brake.c new file mode 100644 index 0000000000000000000000000000000000000000..357cce8d27ec5db3082e6e5b4cf66f55ae3d30d1 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/brake/mcs_brake.c @@ -0,0 +1,105 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_brake.c + * @author MCU Algorithm Team + * @brief This file provides functions of brake module. + */ +#include "mcs_brake.h" +#include "mcs_math.h" +#include "mcs_assert.h" + + +/** + * @brief Initialize brake handle. + * @param brake: Pointer of Brake Handle. + * @param brkParam: Brake parameters. + * @retval None. + */ +void BRAKE_Init(BRAKE_Handle *brake, BRAKE_Param *brkParam) +{ + MCS_ASSERT_PARAM(brake != NULL); + MCS_ASSERT_PARAM(brkParam != NULL); + MCS_ASSERT_PARAM(brkParam->ts > 0.0f); + /* Set brake parameter. */ + brake->brkParam = brkParam; + brake->sampleShiftDuty = brkParam->sampleWinTime / brkParam->ts; + /* Brake count. */ + brake->tickNum = (unsigned int)(brkParam->brkTime / brkParam->ts); +} + +/** + * @brief Clear historical values of brake handle. + * @param brake: Pointer of Brake Handle. + * @retval None. + */ +void BRAKE_Clear(BRAKE_Handle *brake) +{ + MCS_ASSERT_PARAM(brake != NULL); + brake->brkDuty = 0.0f; /* brake duty */ + /* counter for calculating brake time */ + brake->tickCnt = 0; + /* brake status */ + brake->brkFlg = 0; + + brake->brkFlg = BRAKE_WAIT; +} + +/** + * @brief Brake execution. + * @param brake: Pointer of Brake Handle. + * @param brkCurr: Sampling result of current during brake condition (A). + * @retval None. + */ +void BRAKE_Exec(BRAKE_Handle *brake, float brkCurr) +{ + MCS_ASSERT_PARAM(brake != NULL); + MCS_ASSERT_PARAM(brkCurr > 0.0f); + float dutyMax = 1.0f; + float curr = Abs(brkCurr); + float maxCurr = brake->brkParam->maxBrkCurr; + float sampleShiftDuty = brake->sampleShiftDuty; + unsigned int tickNum = brake->tickNum; + + if (brake->brkFlg == BRAKE_FINISHED) { + return; + } + + /* Collect statistics on the total braking duration */ + brake->tickCnt++; + if (brake->tickCnt >= tickNum) { + /* Time to push out the brakes */ + brake->brkFlg = BRAKE_FINISHED; + } + + if (curr < (maxCurr * brake->brkParam->fastBrkCurrCoeff)) { + brake->brkDuty += brake->brkParam->maxBrkDutyStep; + } else if (curr < maxCurr) { + brake->brkDuty += brake->brkParam->minBrkDutyStep; + } else { + brake->brkDuty -= brake->brkParam->maxBrkDutyStep; + } + + /* Reserved sampling window */ + brake->brkDuty = Clamp(brake->brkDuty, dutyMax - 2.0f * sampleShiftDuty, 0.0f); + if (curr <= (maxCurr * brake->brkParam->openLoopBrkCurrCoeff) && + brake->brkDuty >= dutyMax - 3.0f * sampleShiftDuty) { + /* Because the duty cycle is too large to collect the current, the brake open loop control */ + brake->brkDuty += brake->brkParam->openLoopBrkDutyStep; + brake->brkDuty = Clamp(brake->brkDuty, dutyMax, 0.0f); + } +} diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/brake/mcs_brake.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/brake/mcs_brake.h new file mode 100644 index 0000000000000000000000000000000000000000..26a867ae29bb5173db5f00939ae246cee9a90a12 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/brake/mcs_brake.h @@ -0,0 +1,61 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_brake.c + * @author MCU Algorithm Team + * @brief This file provides functions of brake module. + */ + +#ifndef McuMagicTag_MCS_BRAKE_H +#define McuMagicTag_MCS_BRAKE_H + +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief Brake Struct. + */ +typedef struct { + float ts; /**< control period (s). */ + float brkTime; /**< brake time (s). */ + float sampleWinTime; /**< sample shift. */ + float maxBrkCurr; /**< maximum brake current (A). */ + float minBrkDutyStep; /**< small brake duty step, recommend value: 0.001f. */ + float maxBrkDutyStep; /**< large brake duty step, recommend value: 0.005f. */ + float fastBrkCurrCoeff; /**< current threshold coefficient for fast braking, recommend value: 0.5f. */ + float openLoopBrkDutyStep; /**< open-loop brake duty step, recommend value: 0.0001f. */ + float openLoopBrkCurrCoeff; /**< current threshold coefficient for open-loop braking, recommend value: 0.2f. */ +} BRAKE_Param; + + +typedef struct { + float brkDuty; /**< pwm duty ratio of lower switch during brake condition (0~1). */ + float sampleShiftDuty; /**< phase shift duty of sample point for brake current (0~1). */ + unsigned int tickCnt; /**< counter for calculating brake time. */ + unsigned int tickNum; /**< count number corresponding to brake time. */ + unsigned char brkFlg; /**< brake status. */ + BRAKE_Param *brkParam; +} BRAKE_Handle; + +typedef enum { + BRAKE_WAIT = 0, + BRAKE_FINISHED +} BRAKE_Status; + +void BRAKE_Init(BRAKE_Handle *brake, BRAKE_Param *brkParam); +void BRAKE_Clear(BRAKE_Handle *brake); +void BRAKE_Exec(BRAKE_Handle *brake, float brkCurr); + +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/filter/mcs_filter.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/filter/mcs_filter.c new file mode 100644 index 0000000000000000000000000000000000000000..1aadd97a00b12c4029c8b1efa5f176be0cef2359 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/filter/mcs_filter.c @@ -0,0 +1,94 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_filter.c + * @author MCU Algorithm Team + * @brief This file provides functions of first-order filter. + */ + +#include "mcs_filter.h" +#include "mcs_math_const.h" +#include "mcs_assert.h" + +/** + * @brief Initialzer of first-order low-pass filter handle. + * @param lpfHandle First-order filter handle. + * @param ts Control period (s). + * @param fc Cut-off frequency (Hz). + * @retval None. + */ +void FOLPF_Init(FOFLT_Handle *lpfHandle, float ts, float fc) +{ + MCS_ASSERT_PARAM(lpfHandle != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + MCS_ASSERT_PARAM(fc > 0.0f); + lpfHandle->ts = ts; + lpfHandle->fc = fc; + + FOLPF_Clear(lpfHandle); + + /* y(k) = (1/(1+wcTs)) * y(k-1) + (wcTs/(1+wcTs)) * u(k) */ + float wcTs = DOUBLE_PI * fc * ts; + lpfHandle->a1 = 1.0f / (1.0f + wcTs); /* wcTs > 0 */ + lpfHandle->b1 = 1.0f - lpfHandle->a1; +} + +/** + * @brief Clear historical values of first-order filter handle. + * @param FOFLT_Handle First-order filter handle. + * @retval None. + */ +void FOLPF_Clear(FOFLT_Handle *lpfHandle) +{ + MCS_ASSERT_PARAM(lpfHandle != NULL); + lpfHandle->uLast = 0.0f; + lpfHandle->yLast = 0.0f; +} + +/**lpfBkwd + * @brief Calculation method of first-order filter. + * @param lpfHandle First-order filter handle. + * @param u The signal that wants to be filtered. + * @retval The signal that is filtered. + */ +float FOLPF_Exec(FOFLT_Handle *lpfHandle, float u) +{ + MCS_ASSERT_PARAM(lpfHandle != NULL); + float out; + /* Transfer Func: G(s) = kw/(s+w), k = 1. */ + /* y(k) = (1/(1+wcTs)) * y(k-1) + (wcTs/(1+wcTs)) * u(k) */ + out = lpfHandle->a1 * lpfHandle->yLast + lpfHandle->b1 * u; + lpfHandle->yLast = out; + return out; +} + +/** + * @brief Set ts of first-order filter. + * @param lpfHandle First-order filter handle. + * @param ts Control period (s). + * @retval None. + */ +void FOLPF_SetTs(FOFLT_Handle *lpfHandle, float ts) +{ + MCS_ASSERT_PARAM(lpfHandle != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + lpfHandle->ts = ts; + + float wcTs = DOUBLE_PI * lpfHandle->fc * ts; + lpfHandle->a1 = 1.0f / (1.0f + wcTs); /* wcTs > 0 */ + lpfHandle->b1 = 1.0f - lpfHandle->a1; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/filter/mcs_filter.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/filter/mcs_filter.h new file mode 100644 index 0000000000000000000000000000000000000000..7fee90fc94e294b1d802bd73aea34bfc45ec497d --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/filter/mcs_filter.h @@ -0,0 +1,61 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_filter.h + * @author MCU Algorithm Team + * @brief filter library. + * This file provides functions declaration of the filter module. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_FILTER_H +#define McuMagicTag_MCS_FILTER_H + +/* Typedef definitions ------------------------------------------------------------------------- */ + +/** + * @brief 1st-order Filter struct members and parameters. + * LPF(low-pass filter): y(k)=a1*y(k-1)+b1*u(k) + * HPF(high-pass filter): y(k)=a1*y(k-1)+b1*u(k)+b2*u(k-1) + */ +typedef struct { + float yLast; /**< Last output of 1st-order filter. */ + float uLast; /**< Last input variable. */ + float fc; /**< 1st-order filter cut-off frequency (Hz). */ + float ts; /**< 1st-order filter running period. */ + float a1; /**< Coefficient of 1st-order filter. */ + float b1; /**< Coefficient of 1st-order filter. */ + float b2; /**< Coefficient of 1st-order filter. */ +} FOFLT_Handle; + + +/** + * @defgroup FILTER_API FILTER API + * @brief Filter function API declaration. + * Transfer Func: G(s) = kw/(s+w), k = 1. + */ +void FOLPF_Init(FOFLT_Handle *lpfHandle, float ts, float fc); +void FOLPF_Clear(FOFLT_Handle *lpfHandle); +float FOLPF_Exec(FOFLT_Handle *lpfHandle, float u); +void FOLPF_SetTs(FOFLT_Handle *lpfHandle, float ts); + + +/** + * @} + */ + +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/filter/mcs_lpfRk4.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/filter/mcs_lpfRk4.c new file mode 100644 index 0000000000000000000000000000000000000000..47f495aab5afcaa5a8bb6808a79af486422ee420 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/filter/mcs_lpfRk4.c @@ -0,0 +1,82 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_LpfRk4.c + * @author MCU Algorithm Team + * @brief This file provides function of 4-order low-pass filter. + */ + +#include "mcs_lpfRk4.h" +#include "mcs_math_const.h" +#include "mcs_assert.h" +#include "mcs_math.h" + +#define RK4_GAIN (0.5f) +#define RK4_COEFF (0.1666667f) +#define LARGE_NUM (100000000.0f) +#define SMALL_NUM (-100000000.0f) + +/** + * @brief Clear historical values of 4-order low-pass filter handle. + * @param LPF_RK4_Handle 4-order low-pass filter handle. + * @retval None. + */ +void LPFRK4_Clear(LPF_RK4_Handle *lpf) +{ + MCS_ASSERT_PARAM(lpf != NULL); + lpf->y1 = 0.0f; +} + +/** + * @brief Calculation method of 4-order low-pass filter. + * @param LPF_RK4_Handle filter handle. + * @param u The signal that wants to be filtered. + * @param freq Cut-off frequency (Hz). + * @param ts Control period (s). + * @retval The signal that is filered. + */ +float LPFRK4_Exec(LPF_RK4_Handle *lpf, float u, float freq, float ts) +{ + MCS_ASSERT_PARAM(lpf != NULL); + MCS_ASSERT_PARAM(freq > 0.0f); + MCS_ASSERT_PARAM(ts > 0.0f); + float wc = freq * DOUBLE_PI; + float y1 = lpf->y1; + float k1, k2, k3, k4, temp; + + /* Calculate K1. */ + float diff = wc * (u - y1); + k1 = diff * ts; + temp = y1 + k1 * RK4_GAIN; + /* Calculate K2. */ + diff = wc * (u - temp); + k2 = diff * ts; + temp = y1 + k2 * RK4_GAIN; + /* Calculate K3. */ + diff = wc * (u - temp); + k3 = diff * ts; + temp = y1 + k3; + /* Calculate K4. */ + diff = wc * (u - temp); + k4 = diff * ts; + /* Calculate the final result. */ + y1 += (k1 + 2.0f * k2 + 2.0f * k3 + k4) * RK4_COEFF; + y1 = Clamp(y1, LARGE_NUM, SMALL_NUM); + lpf->y1 = y1; + + return y1; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/filter/mcs_lpfRk4.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/filter/mcs_lpfRk4.h new file mode 100644 index 0000000000000000000000000000000000000000..3cf8b2a7635095fbae0ec09e1c5a1348716ff662 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/filter/mcs_lpfRk4.h @@ -0,0 +1,39 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_LpfRk4.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of 4-order low-pass filter. + */ +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_LPFRK4_H +#define McuMagicTag_MCS_LPFRK4_H + + +/** + * @brief First Order Low-pass-filter by RK4. + */ +typedef struct { + float y1; +} LPF_RK4_Handle; + + +void LPFRK4_Clear(LPF_RK4_Handle *lpf); + +float LPFRK4_Exec(LPF_RK4_Handle *lpf, float u, float freq, float ts); + +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/filter/mcs_pll.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/filter/mcs_pll.c new file mode 100644 index 0000000000000000000000000000000000000000..8eba6cca05aae5031e81afbc7f24de4c447bf80a --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/filter/mcs_pll.c @@ -0,0 +1,142 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_pll.c + * @author MCU Algorithm Team + * @brief This file provides function of phase-locked loop (PLL) module. + */ + +#include "mcs_pll.h" +#include "mcs_math.h" +#include "mcs_math_const.h" +#include "mcs_assert.h" + +/** + * @brief Initialzer of Pll struct handle. + * @param pllHandle pll struct handle. + * @param ts control period (s). + * @param bdw bandwidth (Hz). + * @retval None. + */ +void PLL_Init(PLL_Handle *pllHandle, float ts, float bdw) +{ + MCS_ASSERT_PARAM(pllHandle != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + MCS_ASSERT_PARAM(bdw > 0.0f); + /* Reset PLL PID. */ + PID_Reset(&pllHandle->pi); + /* Initializing PLL Parameters. */ + pllHandle->ts = ts; + pllHandle->pi.upperLimit = LARGE_FLOAT; /* The upper limit value of the pid comp output. */ + pllHandle->pi.lowerLimit = -pllHandle->pi.upperLimit; + pllHandle->minAmp = 0.1f; /* Minimum value of the input value in case of the divergence of the PLL. */ + pllHandle->freq = 0.0f; + pllHandle->angle = 0.0f; + pllHandle->ratio = DOUBLE_PI * ts; + pllHandle->pllBdw = bdw; + pllHandle->pi.ts = pllHandle->ts; + PLL_ParamUpdate(pllHandle, pllHandle->pllBdw); +} + +/** + * @brief Updating PLL PI Parameters. + * @param pllHandle pll struct handle. + * @param bdw bandwidth (Hz). + * @retval None. + */ +void PLL_ParamUpdate(PLL_Handle *pllHandle, float bdw) +{ + MCS_ASSERT_PARAM(pllHandle != NULL); + MCS_ASSERT_PARAM(bdw > 0.0f); + float we = bdw * DOUBLE_PI; /* PLL bandwidth (unit: Hz) */ + pllHandle->pi.kp = 2.0f * we; /* 2.0f * we */ + pllHandle->pi.ki = we * we; +} + +/** + * @brief Reset the PLL handle, fill all parameters with zero. + * @param pllHandle PLL struct handle. + * @retval None. + */ +void PLL_Reset(PLL_Handle *pllHandle) +{ + MCS_ASSERT_PARAM(pllHandle != NULL); + /* Reset PLL PID parameters */ + PID_Reset(&(pllHandle->pi)); + pllHandle->minAmp = 0.0f; + pllHandle->ts = 0.0f; + pllHandle->ratio = 0.0f; + pllHandle->freq = 0.0f; + pllHandle->angle = 0; +} + +/** + * @brief Clear historical values of PLL controller. + * @param pllHandle PLL struct handle. + * @retval None. + */ +void PLL_Clear(PLL_Handle *pllHandle) +{ + MCS_ASSERT_PARAM(pllHandle != NULL); + PID_Clear(&pllHandle->pi); +} + +/** + * @brief Calculation method of PLL controller. + * @param pllHandle PLL struct handle. + * @param sinVal Input sin value. + * @param cosVal Input cos value. + * @retval None. + */ +void PLL_Exec(PLL_Handle *pllHandle, float sinVal, float cosVal) +{ + MCS_ASSERT_PARAM(pllHandle != NULL); + + float amplitude = Sqrt(sinVal * sinVal + cosVal * cosVal); + amplitude = (amplitude < pllHandle->minAmp) ? pllHandle->minAmp : amplitude; /* amplitude > minAmp > 0 */ + + TrigVal localTrigVal; + pllHandle->angle += pllHandle->freq * pllHandle->ratio; + pllHandle->angle = Mod(pllHandle->angle, DOUBLE_PI); + if (pllHandle->angle > ONE_PI) { + pllHandle->angle -= DOUBLE_PI; + } + if (pllHandle->angle < -ONE_PI) { + pllHandle->angle += DOUBLE_PI; + } + TrigCalc(&localTrigVal, pllHandle->angle); + + float err = sinVal * localTrigVal.cos - cosVal * localTrigVal.sin; + pllHandle->pi.error = err / amplitude; /* amplitude != 0 */ + pllHandle->freq = PI_Exec(&pllHandle->pi); +} + +/** + * @brief Set ts of PLL controller. + * @param pllHandle PLL struct handle. + * @param ts control period (s). + * @retval None. + */ +void PLL_SetTs(PLL_Handle *pllHandle, float ts) +{ + MCS_ASSERT_PARAM(pllHandle != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + /* It is need to modify the pid sample time, pll ratio when set PLL ts. */ + pllHandle->ts = ts; + PID_SetTs(&pllHandle->pi, ts); + pllHandle->ratio = DOUBLE_PI * ts; +} diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/filter/mcs_pll.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/filter/mcs_pll.h new file mode 100644 index 0000000000000000000000000000000000000000..7a0228b86188d164199bfa8e00d85c223f03efb1 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/filter/mcs_pll.h @@ -0,0 +1,72 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_pll.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of Phase-locked loop (PLL) module. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_PLL_H +#define McuMagicTag_MCS_PLL_H + +/* Includes ------------------------------------------------------------------------------------ */ +#include "mcs_pid_ctrl.h" + +/** + * @defgroup PLL_MODULE PLL MODULE + * @brief The PLL module. + * @{ + */ + +/** + * @defgroup PLL_STRUCT PLL STRUCT + * @brief The PLL module data structure. + * @{ + */ +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief PLL struct. + */ +typedef struct { + PID_Handle pi; /**< PI controller for the PLL. */ + float minAmp; /**< Minimum value of the input value in case of the divergence of the PLL. */ + float ts; /**< Control period of the PLL. */ + float ratio; /**< Conversion factor, ts * 65535 / TWO_PI. */ + float freq; /**< Output estimated frequency (Hz). */ + float angle; /**< Output estimated phasse angle. */ + float pllBdw; /**< pll bandWidth. */ +} PLL_Handle; + + +/** + * @defgroup PLL_API PLL API + * @brief The PLL module API definitions. + */ +void PLL_Init(PLL_Handle *pllHandle, float ts, float bdw); + +void PLL_Reset(PLL_Handle *pllHandle); + +void PLL_Clear(PLL_Handle *pllHandle); + +void PLL_Exec(PLL_Handle *pllHandle, float sinVal, float cosVal); + +void PLL_SetTs(PLL_Handle *pllHandle, float ts); + +void PLL_ParamUpdate(PLL_Handle *pllHandle, float bdw); + +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_curr_ctrl.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_curr_ctrl.c new file mode 100644 index 0000000000000000000000000000000000000000..17ecb6ee63172bb3496e662c2f2f514417fd64be --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_curr_ctrl.c @@ -0,0 +1,148 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_curr_ctrl.c + * @author MCU Algorithm Team + * @brief This file provides function of motor current control. + */ + +#include "typedefs.h" +#include "mcs_curr_ctrl.h" +#include "mcs_math_const.h" +#include "mcs_assert.h" +#include "mcs_curr_ff.h" + + +/** + * @brief Initialzer of Current controller. + * @param currHandle Current control handle. + * @param pidTable Motor control handle. + * @param mtrParam Motor parameters. + * @param idqRef idqRef. + * @param idqFbk idqFbk. + * @param busVolt Bus voltage. + * @param ts control period. + * @retval None. + */ +void CURRCTRL_Init(CURRCTRL_Handle *currHandle, MOTOR_Param *mtrParam, DqAxis *idqRef, DqAxis *idqFbk, + const PI_Param dAxisPi, const PI_Param qAxisPi, float ts) +{ + MCS_ASSERT_PARAM(currHandle != NULL); + MCS_ASSERT_PARAM(mtrParam != NULL); + MCS_ASSERT_PARAM(idqRef != NULL); + MCS_ASSERT_PARAM(idqFbk != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + /* Clear the control parameter. */ + CURRCTRL_Reset(currHandle); + /* Current Pointer. */ + currHandle->idqRef = idqRef; + currHandle->idqFbk = idqFbk; + currHandle->mtrParam = mtrParam; + /* The feedforward value is set to 0 by default. */ + currHandle->idqFf.d = 0.0f; + currHandle->idqFf.q = 0.0f; + + /* Parameter initialization. */ + currHandle->ts = ts; + currHandle->dAxisPi.ts = ts; + currHandle->qAxisPi.ts = ts; + + currHandle->dAxisPi.kp = dAxisPi.kp; + currHandle->dAxisPi.ki = dAxisPi.ki; + currHandle->qAxisPi.kp = qAxisPi.kp; + currHandle->qAxisPi.ki = qAxisPi.ki; + /* output voltage limit. */ + currHandle->outLimit = qAxisPi.upperLim; + currHandle->dAxisPi.upperLimit = dAxisPi.upperLim; + currHandle->dAxisPi.lowerLimit = dAxisPi.lowerLim; + currHandle->qAxisPi.upperLimit = qAxisPi.upperLim; + currHandle->qAxisPi.lowerLimit = qAxisPi.lowerLim; +} + +/** + * @brief Reset the current control handle, fill with zero, NULL. + * @param currHandle The current control handle. + * @retval None. + */ +void CURRCTRL_Reset(CURRCTRL_Handle *currHandle) +{ + MCS_ASSERT_PARAM(currHandle != NULL); + /* Reset the current control handle, fill with zero, NULL. */ + currHandle->idqRef = NULL; + currHandle->idqFbk = NULL; + currHandle->idqFf.d = 0.0f; + currHandle->idqFf.q = 0.0f; + currHandle->mtrParam = NULL; + currHandle->outLimit = 0.0f; + currHandle->ts = 0.0f; + /* Reset Dq axis PID current control */ + PID_Reset(&currHandle->dAxisPi); + PID_Reset(&currHandle->qAxisPi); +} + +/** + * @brief Clear historical values of current controller. + * @param currHandle Current controller struct handle. + * @retval None. + */ +void CURRCTRL_Clear(CURRCTRL_Handle *currHandle) +{ + MCS_ASSERT_PARAM(currHandle != NULL); + PID_Clear(&currHandle->dAxisPi); + PID_Clear(&currHandle->qAxisPi); +} + + +/** + * @brief Simplified current controller PI calculation. + * @param currHandle Current controller struct handle. + * @param voltRef Dq-axis voltage reference which is the output of current controller. + * @param spd speed (Hz). + * @param ffEnable Feedforward compensation enable. + * @retval None. + */ +void CURRCTRL_Exec(CURRCTRL_Handle *currHandle, DqAxis *vdqRef, float spd, int ffEnable) +{ + MCS_ASSERT_PARAM(currHandle != NULL); + MCS_ASSERT_PARAM(vdqRef != NULL); + DqAxis vdqFf; + + /* Calculate the current error of the dq axis. */ + currHandle->dAxisPi.error = currHandle->idqRef->d - currHandle->idqFbk->d; + currHandle->qAxisPi.error = currHandle->idqRef->q - currHandle->idqFbk->q; + CURRFF_Exec(&vdqFf, *currHandle->idqFbk, currHandle->mtrParam, spd, ffEnable); + currHandle->dAxisPi.feedforward = vdqFf.d; + currHandle->qAxisPi.feedforward = vdqFf.q; + /* Calculation of the PI of the Dq axis current. */ + vdqRef->d = PI_Exec(&currHandle->dAxisPi); + vdqRef->q = PI_Exec(&currHandle->qAxisPi); +} + +/** + * @brief Set ts of current controller. + * @param currHandle Current controller struct handle. + * @retval None. + */ +void CURRCTRL_SetTs(CURRCTRL_Handle *currHandle, float ts) +{ + MCS_ASSERT_PARAM(currHandle != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + currHandle->ts = ts; + /* Set d and q axes pid sample time. */ + PID_SetTs(&currHandle->dAxisPi, ts); + PID_SetTs(&currHandle->qAxisPi, ts); +} diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_curr_ctrl.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_curr_ctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..0fe6b555a4de5ca32d9c508d747d2fbb44f9ac5b --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_curr_ctrl.h @@ -0,0 +1,87 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_curr_ctrl.h + * @author MCU Algorithm Team + * @brief Current controller for motor control. + * This file provides functions declaration of the current controller module. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_CURR_CTRL_H +#define McuMagicTag_MCS_CURR_CTRL_H + +/* Includes ------------------------------------------------------------------------------------ */ +#include "mcs_typedef.h" +#include "mcs_pid_ctrl.h" +#include "mcs_mtr_param.h" + +/** + * @defgroup CURRENT_CONTROLLER CURRENT CONTROLLER MODULE + * @brief The current controller function. + * @{ + */ + +/** + * @defgroup CURRENT_CONTROLLER_STRUCT CURRENT CONTROLLER STRUCT + * @brief The current controller's data structure definition. + * @{ + */ + +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief Current controller struct members and parameters. + */ +typedef struct { + DqAxis *idqRef; /**< Current reference in the d-q coordinate (A). */ + DqAxis *idqFbk; /**< Current feedback in the d-q coordinate (A). */ + DqAxis idqFf; /**< Current feedforward value (V). */ + PID_Handle dAxisPi; /**< d-axis current PI controller. */ + PID_Handle qAxisPi; /**< q-axis current PI controller. */ + MOTOR_Param *mtrParam; /**< Motor parameters. */ + float outLimit; /**< Current controller output voltage limitation (V). */ + float ts; /**< Current controller control period (s). */ +} CURRCTRL_Handle; +/** + * @} + */ + +/** + * @defgroup CURRENT_CONTROLLER_API CURRENT CONTROLLER API + * @brief The current controller's API declaration. + * @{ + */ +void CURRCTRL_Init(CURRCTRL_Handle *currHandle, MOTOR_Param *mtrParam, DqAxis *idqRef, DqAxis *idqFbk, + const PI_Param dAxisPi, const PI_Param qAxisPi, float ts); + +void CURRCTRL_Reset(CURRCTRL_Handle *currHandle); + +void CURRCTRL_Clear(CURRCTRL_Handle *currHandle); + +void CURRCTRL_Exec(CURRCTRL_Handle *currHandle, DqAxis *vdqRef, float spd, int ffEnable); + +void CURRCTRL_SetTs(CURRCTRL_Handle *currHandle, float ts); + +/** + * @} + */ + +/** + * @} + */ + +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_curr_ff.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_curr_ff.c new file mode 100644 index 0000000000000000000000000000000000000000..84ae2854793305ec275d155c6b3edec68793e00a --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_curr_ff.c @@ -0,0 +1,50 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_curr_ff.c + * @author MCU Algorithm Team + * @brief This file provides current loop feedforward compensation declaration for motor control. + */ + +#include "mcs_curr_ff.h" +#include "mcs_math_const.h" +#include "mcs_assert.h" + +/** + * @brief Current loop feedforward compensation execution function. + * @param vdqFf DQ axis volt feedforward compensation value. + * @param idqFbk DQ axis feedback current value. + * @param param Motor parameters. + * @param spd Speed (Hz). + * @param enable Whether to enable feedforward compensation. + * @retval None. + */ +void CURRFF_Exec(DqAxis *vdqFf, DqAxis idqFbk, MOTOR_Param *param, float spd, int enable) +{ + MCS_ASSERT_PARAM(vdqFf != NULL); + MCS_ASSERT_PARAM(param != NULL); + /* The unit is converted from Hz to rad. */ + float we = spd * DOUBLE_PI; + if (enable) { + /* Calculate the feedforward compensation value. */ + vdqFf->d = -param->mtrLq * we * idqFbk.q; + vdqFf->q = we * (param->mtrLd * idqFbk.d + param->mtrPsif); + } else { + vdqFf->d = 0.0f; + vdqFf->q = 0.0f; + } +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_curr_ff.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_curr_ff.h new file mode 100644 index 0000000000000000000000000000000000000000..ba15e15b3c75bb1b2e5d5a170d9c9d681d2b204b --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_curr_ff.h @@ -0,0 +1,31 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_curr_ff.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of current loop feedforward compensation. + */ + +#ifndef McuMagicTag_MCS_CURR_FF_H +#define McuMagicTag_MCS_CURR_FF_H + +#include "mcs_typedef.h" +#include "mcs_mtr_param.h" + +void CURRFF_Exec(DqAxis *vdqRef, DqAxis idqFbk, MOTOR_Param *param, float spd, int enable); + +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_fw_ctrl.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_fw_ctrl.c new file mode 100644 index 0000000000000000000000000000000000000000..3100ef65cafce9dea01ed24d8af210a2649745f5 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_fw_ctrl.c @@ -0,0 +1,130 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_fw_ctrl.c + * @author MCU Algorithm Team + * @brief This file provides Flux-Weakening control for motor control. + */ +#include "mcs_fw_ctrl.h" +#include "mcs_math.h" +#include "mcs_math_const.h" +#include "mcs_assert.h" + +/** + * @brief Clear historical values of Flux-Weakening handle. + * @param fw Flux-Weakening struct handle. + * @retval None. + */ +static void FW_Clear(FW_Handle *fw) +{ + MCS_ASSERT_PARAM(fw != NULL); + fw->idRef = 0.0f; +} + +/** + * @brief Flux-Weakening control Handle Initialization. + * @param fw Flux-Weakening struct handle. + * @param ts Control period (s). + * @param enable Enable flux-weakening. + * @param currMax Maximum phase current (A). + * @param idDemag Demagnetizing d-axis current (A). + * @param thr . + * @retval None. + */ +void FW_Init(FW_Handle *fw, float ts, bool enable, float currMax, float idDemag, float thr, float slope) +{ + MCS_ASSERT_PARAM(fw != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + /* Indicates whether to enable the Flux-Weakening field function. */ + fw->enable = enable; + fw->ts = ts; + fw->udcThreshPer = thr * ONE_DIV_SQRT3; + /* id control slope */ + fw->idSlope = slope; + fw->idMaxAmp = (currMax < idDemag) ? currMax : idDemag; + fw->currMaxSquare = currMax * currMax; + FW_Clear(fw); +} + +/** + * @brief Flux-Weakening calculation execution function. + * @param fw Flux-Weakening struct handle. + * @param udqRef dq axis voltage reference. + * @param udc bus voltage. + * @param idqRefRaw Command value of the d and q axis current. + * @retval None. + */ +void FW_Exec(FW_Handle *fw, DqAxis udqRef, float udc, DqAxis *idqRefRaw) +{ + MCS_ASSERT_PARAM(fw != NULL); + MCS_ASSERT_PARAM(udc > 0.0f); + MCS_ASSERT_PARAM(idqRefRaw != NULL); + float udcLimit = udc * fw->udcThreshPer; + float voltRefAmp = Sqrt(udqRef.d * udqRef.d + udqRef.q * udqRef.q); + float voltErr = udcLimit - voltRefAmp; + float idRefRaw = idqRefRaw->d; + float iqRefRaw = idqRefRaw->q; + float iqRef; + float dir = (idqRefRaw->q > 0.0f) ? 1.0f : -1.0f; + + /* Check whether the Flux-Weakening field function is enabled. */ + if (!fw->enable) { + fw->idRef = idRefRaw; + /* if fw is disabled, just return without any change. */ + return; + } + float idStep = fw->idSlope * fw->ts; + /* Adjust the injection d-axis current based on the output voltage error. */ + /* When voltage error is positive, adjust id to idRefRaw, no need to fw. */ + if (voltErr >= 0.0f) { + fw->idRef += idStep; + if (fw->idRef > idRefRaw) { + fw->idRef = idRefRaw; + } + } else { + /* When voltage error is negative. Add negtive id to the motor, need to fw. */ + fw->idRef -= idStep; + if (fw->idRef < -fw->idMaxAmp) { + fw->idRef = -fw->idMaxAmp; + } + } + + /* Limit q-axis current output. */ + float idRefSquare = fw->idRef * fw->idRef; + if (idRefSquare + iqRefRaw * iqRefRaw > fw->currMaxSquare) { + iqRef = dir * Sqrt(fw->currMaxSquare - idRefSquare); + } else { + iqRef = iqRefRaw; + } + + idqRefRaw->d = fw->idRef; + idqRefRaw->q = iqRef; + + return; +} + +/** + * @brief Set ts of Flux-Weakening. + * @param fw Flux-Weakening struct handle. + * @param ts Control period (s). + * @retval None. + */ +void FW_SetTs(FW_Handle *fw, float ts) +{ + MCS_ASSERT_PARAM(fw != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + fw->ts = ts; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_fw_ctrl.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_fw_ctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..78ca1185335947d178f4c66467335e5f753cdb97 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_fw_ctrl.h @@ -0,0 +1,45 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_fw_ctrl.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of Flux-Weakening control. + */ +#ifndef McuMagicTag_MCS_FW_CTRL_H +#define McuMagicTag_MCS_FW_CTRL_H + +#include "typedefs.h" +#include "mcs_typedef.h" + +typedef struct { + bool enable; + float udcThreshPer; + float ts; + float idSlope; + float idRef; /* reference instruction value. */ + float idMaxAmp; /* Maximum id ingested */ + + float currMax; /* maximum phase current (A) */ + float currMaxSquare; /* square of maximum current. */ + float idDemag; /* demagnetizing d-axis current (A) */ +} FW_Handle; + +void FW_Init(FW_Handle *fw, float ts, bool enable, float currMax, float idDemag, float thr, float slope); + +void FW_Exec(FW_Handle *fw, DqAxis udqRef, float udc, DqAxis *idqRefRaw); + +void FW_SetTs(FW_Handle *fw, float ts); +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_if_ctrl.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_if_ctrl.c new file mode 100644 index 0000000000000000000000000000000000000000..7db97eb0396331a6dd88c837e402913093b17e94 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_if_ctrl.c @@ -0,0 +1,115 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_if_ctrl.c + * @author MCU Algorithm Team + * @brief This file provides function of I/F control. + */ + +#include "mcs_if_ctrl.h" +#include "mcs_assert.h" +#include "mcs_math_const.h" + +/** + * @brief Initialzer of I/F control struct handle. + * @param ifHandle I/F handle. + * @param targetAmp Target value of the I/F current (A). + * @param currSlope Current slope. + * @param stepAmpPeriod Step control period, using systick---spd_loop_ctrl_period (s). + * @param anglePeriod Calculation period of the I/F angle---curr_loop_ctrl_period (s). + * @retval None. + */ +void IF_Init(IF_Handle *ifHandle, float targetAmp, float currSlope, float stepAmpPeriod, float anglePeriod) +{ + MCS_ASSERT_PARAM(ifHandle != NULL); + MCS_ASSERT_PARAM(targetAmp > 0.0f); + MCS_ASSERT_PARAM(currSlope > 0.0f); + MCS_ASSERT_PARAM(anglePeriod > 0.0f); + MCS_ASSERT_PARAM(stepAmpPeriod > 0.0f); + /* Initialize IF parameters. */ + ifHandle->targetAmp = targetAmp; + ifHandle->stepAmp = currSlope * stepAmpPeriod; /* current step increment */ + ifHandle->curAmp = 0.0f; + /* Angle period. */ + ifHandle->anglePeriod = anglePeriod; + ifHandle->angle = 0.0f; +} + +/** + * @brief Clear historical values of first-order filter handle. + * @param ifHandle I/F control handle. + * @retval None. + */ +void IF_Clear(IF_Handle *ifHandle) +{ + MCS_ASSERT_PARAM(ifHandle != NULL); + ifHandle->curAmp = 0.0f; + ifHandle->angle = 0; +} + +/** + * @brief I/F current amplitude calculation. + * @param ifHandle I/F control handle. + * @retval I/F current amplitude (A). + */ +float IF_CurrAmpCalc(IF_Handle *ifHandle) +{ + MCS_ASSERT_PARAM(ifHandle != NULL); + /* Calculation of IF Current Amplitude */ + if (ifHandle->curAmp < ifHandle->targetAmp) { + ifHandle->curAmp += ifHandle->stepAmp; + } else { + ifHandle->curAmp = ifHandle->targetAmp; + } + + return ifHandle->curAmp; +} + +/** + * @brief I/F current angle calculation. + * @param ifHandle I/F control handle. + * @param spdRef Frequency of current vector. + * @retval I/F output angle. + */ +float IF_CurrAngleCalc(IF_Handle *ifHandle, float spdRef) +{ + MCS_ASSERT_PARAM(ifHandle != NULL); + /* Calculate IF angle. */ + ifHandle->angle += spdRef * DOUBLE_PI * ifHandle->anglePeriod; + /* Limit the angle: [-pi, pi]. */ + if (ifHandle->angle > ONE_PI) { + ifHandle->angle -= DOUBLE_PI; + } + if (ifHandle->angle < -ONE_PI) { + ifHandle->angle += DOUBLE_PI; + } + + return ifHandle->angle; +} + +/** + * @brief Set ts of I/F. + * @param ifHandle I/F control handle. + * @param ts Control period (s). + * @retval None. + */ +void IF_SetAngleTs(IF_Handle *ifHandle, float ts) +{ + MCS_ASSERT_PARAM(ifHandle != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + ifHandle->anglePeriod = ts; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_if_ctrl.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_if_ctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..cd32b5c78c3db8bb81b61594d2eb30fc5db68a79 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_if_ctrl.h @@ -0,0 +1,76 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_if_ctrl.h + * @author MCU Algorithm Team + * @brief Current controller for motor I/F control. + * This file provides functions declaration of I/F control. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_IF_CTRL_H +#define McuMagicTag_MCS_IF_CTRL_H + +/** + * @defgroup IF_MODULE I/F MODULE + * @brief The I/F motor control method module. + * @{ + */ + +/** + * @defgroup IF_STRUCT I/F STRUCT + * @brief The I/F motor control method data struct definition. + * @{ + */ +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief General IF controller struct members and parameters. + */ +typedef struct { + float anglePeriod; /**< Calculation period of the I/F angle (s). */ + float curAmpPeriod; /**< Calculation period of the I/F current amplitude (s). */ + + float targetAmp; /**< Target value of the I/F current (A). */ + float curAmp; /**< Current value of the I/F current (A). */ + float stepAmp; /**< Increment of the I/F current (A). */ + float angle; /**< I/F output angle. */ +} IF_Handle; + +/** + * @defgroup IF_API I/F API + * @brief The I/F motor control method API declaration. + * @{ + */ +void IF_Init(IF_Handle *ifHandle, float targetAmp, float currSlope, float stepAmpPeriod, float anglePeriod); + +void IF_Clear(IF_Handle *ifHandle); + +float IF_CurrAmpCalc(IF_Handle *ifHandle); + +float IF_CurrAngleCalc(IF_Handle *ifHandle, float spdRef); + +void IF_SetAngleTs(IF_Handle *ifHandle, float ts); + +/** + * @} + */ + +/** + * @} + */ + +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_pos_ctrl.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_pos_ctrl.c new file mode 100644 index 0000000000000000000000000000000000000000..1e8922633659b6abfefd9137611836683309599a --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_pos_ctrl.c @@ -0,0 +1,218 @@ +/** + * Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_posctrl.c + * @author MCU Algorithm Team + * @brief This file provides function of motor position control. + */ + +#include "typedefs.h" +#include "mcs_math_const.h" +#include "mcs_math.h" +#include "mcs_pos_ctrl.h" + +/** + * @brief Reset the position controller, fill with zero, NULL. + * @param posHandle position controller struct handle. + * @retval None. + */ +void POSCTRL_Clear(POSCTRL_Handle *posHandle) +{ + /* PID controller history values clear */ + posHandle->posPi.error = 0.0f; + posHandle->posPi.feedforward = 0.0f; + posHandle->posPi.differ = 0.0f; + posHandle->posPi.integral = 0.0f; + posHandle->posPi.saturation = 0.0f; + + posHandle->posTarget = 0.0f; + posHandle->posErr = 0.0f; +} + +/** + * @brief Position control initialization function. + * @param posHandle position controller struct handle. + * @param ts Control period. + */ +void POSCTRL_Init(POSCTRL_Handle *posHandle, const PID_Param *piCtrlTable, float ts) +{ + POSCTRL_Clear(posHandle); + posHandle->ts = ts; + + /* position PID controller initialization */ + posHandle->posPi.ts = posHandle->ts; + posHandle->posPi.kp = piCtrlTable->kp; + posHandle->posPi.ki = piCtrlTable->ki; + posHandle->posPi.kd = piCtrlTable->kd; + posHandle->posPi.ns = piCtrlTable->ns; + posHandle->posPi.ka = 1.0f / posHandle->posPi.kp; + posHandle->posPi.upperLimit = piCtrlTable->upperLim; + posHandle->posPi.lowerLimit = piCtrlTable->lowerLim; + + /* continuous mode: ramp controller initialization */ + RMG_Init(&posHandle->posRmg, posHandle->ts, posHandle->posRmg.slope * DOUBLE_PI); + posHandle->posRmg.ts = posHandle->ts; + + /* position feedback history values clear */ + posHandle->angFbkLoop = 0; + posHandle->angFbkPrev = 0.0f; + + /* position control mode configuration */ + posHandle->mode = POSCTRL_MODE_CONTINUOUS; +} + +/** + * @brief Position control mode settings. + * @param posHandle position controller struct handle. + * @param mode control mode. + */ +void POSCTRL_ModeSelect(POSCTRL_Handle *posHandle, POSCTRL_Mode mode) +{ + posHandle->mode = mode; +} + +/** + * @brief Set position change rate. + * @param posHandle Position controller struct handle. + * @param slope position change rate (Hz). + * @retval None. + */ +void POSCTRL_SetSlope(POSCTRL_Handle *posHandle, float slope) +{ + posHandle->posRmg.slope = slope; + posHandle->posRmg.delta = posHandle->posRmg.ts * posHandle->posRmg.slope * DOUBLE_PI; +} + +/** + * @brief Position ring target position setting. + * @param posHandle Position controller struct handle. + * @param posTarget Target location. + */ +void POSCTRL_SetTarget(POSCTRL_Handle *posHandle, float posTarget) +{ + posHandle->posTarget = posTarget; + posHandle->posTargetShadow = posTarget; +} + +/** + * @brief Absolute position calculation. + * @param posHandle Position controller struct handle. + * @param angFbk Angle feedback. + * @return float, Position feedback. + */ +float POSCTRL_AngleExpand(POSCTRL_Handle *posHandle, float angFbk) +{ + float angFbkPrevFloat = posHandle->angFbkPrev; + int loopPrev = posHandle->angFbkLoop; + int loop; + + /* unify feedback angle to ±2*pi */ + angFbk = Mod(angFbk, DOUBLE_PI); + /* unify feedback angle to 0 ~ 2*pi */ + if (angFbk < 0.0f) { + angFbk += DOUBLE_PI; + } + + /* check if angle rotates one cycle */ + if (angFbkPrevFloat > THREE_PI_DIV_TWO && angFbkPrevFloat <= DOUBLE_PI && angFbk < HALF_PI) { + loop = loopPrev + 1; + } else if (angFbk > THREE_PI_DIV_TWO && THREE_PI_DIV_TWO <= DOUBLE_PI && angFbkPrevFloat < HALF_PI) { + loop = loopPrev - 1; + } else { + loop = loopPrev; + } + + /* update prev value */ + posHandle->angFbkLoop = loop; + posHandle->angFbkPrev = angFbk; + + /* update output value */ + posHandle->posFbk = angFbk + loop * DOUBLE_PI; + + return posHandle->posFbk; +} + +/** + * @brief Position ring PID execution function. + * @param posHandle Position controller struct handle. + * @param posErr position error. + * @return float + */ +float POSCTRL_PidExec(POSCTRL_Handle *posHandle, float posErr) +{ + float spdRef; + posHandle->posPi.error = posErr; + spdRef = PID_Exec(&posHandle->posPi); + return spdRef; +} + +/** + * @brief position loop execution function. + * @param posHandle Position controller struct handle. + * @param posFbk Position feedback. + * @return float, Speed reference value. + */ +float POSCTRL_Exec(POSCTRL_Handle *posHandle, float posTarget, float posFbk) +{ + float posRef, spdRef; + posRef = RMG_Exec(&posHandle->posRmg, posTarget); + posHandle->posRef = posRef; + spdRef = POSCTRL_PidExec(posHandle, posRef - posFbk); + spdRef *= ONE_DIV_DOUBLE_PI; /* transfer spdRef from rad/s to Hz */ + posHandle->spdRef = spdRef; + return spdRef; +} + +/** + * @brief Set position loop kp parameter function. + * @param posHandle Position controller struct handle. + * @param kp PID-kp paramter. + */ +void POSCTRL_SetKp(POSCTRL_Handle *posHandle, float kp) +{ + posHandle->posPi.kp = kp; +} + +/** + * @brief Set position loop ki parameter function. + * @param posHandle Position controller struct handle. + * @param ki PID-ki paramter. + */ +void POSCTRL_SetKi(POSCTRL_Handle *posHandle, float ki) +{ + posHandle->posPi.ki = ki; +} + +/** + * @brief Set position loop kd parameter function. + * @param posHandle Position controller struct handle. + * @param kd PID-kd paramter. + */ +void POSCTRL_SetKd(POSCTRL_Handle *posHandle, float kd) +{ + posHandle->posPi.kd = kd; +} + +/** + * @brief Set position loop Ns parameter function. + * @param posHandle Position controller struct handle. + * @param ns ns paramter. + */ +void POSCTRL_SetNs(POSCTRL_Handle *posHandle, float ns) +{ + posHandle->posPi.ns = ns; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_pos_ctrl.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_pos_ctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..999dd359d69ee36bf1ada15490b5c3dc2a3d975a --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_pos_ctrl.h @@ -0,0 +1,97 @@ +/** + * Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_pos_ctrl.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of position control . + */ +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_MCS_POS_CTRL_H +#define McuMagicTag_MCS_MCS_POS_CTRL_H + +/* Includes ------------------------------------------------------------------------------------ */ +#include "mcs_typedef.h" +#include "mcs_pid_ctrl.h" +#include "mcs_ramp_mgmt.h" +#include "mcs_mtr_param.h" + + +/* Macro definitions --------------------------------------------------------------------------- */ + +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief Position control mode. + */ +typedef enum { + POSCTRL_MODE_CONTINUOUS = 0, + POSCTRL_MODE_TRAJ +} POSCTRL_Mode; + +/** + * @brief Position controller struct members and parameters. + */ +typedef struct { + PID_Handle posPi; /**< PI controller struct in the position controller. */ + float posTarget; /**< position controller input target value (rad) */ + float posTargetBk; + RMG_Handle posRmg; /**< position reference ramp management . */ + float ts; /**< position controller control period (s). */ + int angFbkLoop; /**< feedback position loop count. */ + float angFbkPrev; /**< feedback position in last cycle (rad). */ + float posFbk; /**< feedback position absolutely (rad). */ + float posIncRef; /**< position controller reference (rad) */ + float posIncRefPrev; /**< position controller reference in last cycle (rad) */ + float spdRef; /**< position controller outpur speed reference (Hz) */ + float posRef; /**< position controller reference (rad) */ + float posFbkPrev; + float posErr; + + /* trajectory planning */ + /* position controller work mode. 0: continuous mode; 1: trajectory control mode. */ + /* trajectory mode can only be enabled when input mode is set absolute position. */ + POSCTRL_Mode mode; + float posTargetShadow; + float runTime; /**< single trajectory control last time time (s). */ + float timeTick; /**< trajectory control inner timer (s) */ + float deltaTime; + float accMax; + float jerk; + int targetUpdateBlockFlag; /**< whether the position target can be update or not. 0: can be updated; 1: block */ + float deltaTimeSq; + float deltaTimeCu; + float timeStg[7]; +} POSCTRL_Handle; + +/** + * @defgroup POSITION_CONTROLLER_API POSITION CONTROLLER API + * @brief The position controller API declaration. + * @retval Speed Reference. + */ +void POSCTRL_Clear(POSCTRL_Handle *posHandle); +void POSCTRL_Init(POSCTRL_Handle *posHandle, const PID_Param *piCtrlTable, float ts); +float POSCTRL_PidExec(POSCTRL_Handle *posHandle, float posErr); +void POSCTRL_ModeSelect(POSCTRL_Handle *posHandle, POSCTRL_Mode mode); +void POSCTRL_SetSlope(POSCTRL_Handle *posHandle, float slope); +void POSCTRL_SetTarget(POSCTRL_Handle *posHandle, float posTarget); +float POSCTRL_Exec(POSCTRL_Handle *posHandle, float posTarget, float posFbk); +float POSCTRL_AngleExpand(POSCTRL_Handle *posHandle, float angFbk); +void POSCTRL_SetKp(POSCTRL_Handle *posHandle, float kp); +void POSCTRL_SetKi(POSCTRL_Handle *posHandle, float ki); +void POSCTRL_SetKd(POSCTRL_Handle *posHandle, float kd); +void POSCTRL_SetNs(POSCTRL_Handle *posHandle, float ns); + +#endif /* McuMagicTag_MCS_POS_CTRL_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_spd_ctrl.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_spd_ctrl.c new file mode 100644 index 0000000000000000000000000000000000000000..5f88e833e86c0cf5db91907df949fe5dc1640d7d --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_spd_ctrl.c @@ -0,0 +1,96 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_spd_ctrl.c + * @author MCU Algorithm Team + * @brief This file provides function of motor speed control. + */ + +#include "typedefs.h" +#include "mcs_spd_ctrl.h" +#include "mcs_assert.h" + +/** + * @brief Initialzer of speed control struct handle. + * @param spdHandle Speed control struct handle. + * @param PID_Param PI controller parameter table. + * @param ts Speed control period. + * @retval None. + */ +void SPDCTRL_Init(SPDCTRL_Handle *spdHandle, MOTOR_Param *mtrParam, const PI_Param piParam, float ts) +{ + MCS_ASSERT_PARAM(spdHandle != NULL); + MCS_ASSERT_PARAM(mtrParam != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + /* reset speed loop PI */ + PID_Reset(&spdHandle->spdPi); + /* Parameter Initialization. */ + spdHandle->mtrParam = mtrParam; + spdHandle->ts = ts; + spdHandle->spdPi.ts = ts; + spdHandle->spdPi.kp = piParam.kp; + spdHandle->spdPi.ki = piParam.ki; + spdHandle->outLimit = piParam.upperLim; + spdHandle->spdPi.upperLimit = piParam.upperLim; + spdHandle->spdPi.lowerLimit = piParam.lowerLim; +} + + +/** + * @brief Simplified speed controller PI calculation. + * @param spdHandle Speed controller struct handle. + * @param spdTarget The target speed value (Hz). + * @param spdFbk Motor electrical speed (Hz). + * @retval None. + */ +float SPDCTRL_Exec(SPDCTRL_Handle *spdHandle, float spdTarget, float spdFbk) +{ + MCS_ASSERT_PARAM(spdHandle != NULL); + float iqRef; + /* Speed error calculation */ + spdHandle->spdPi.error = spdTarget - spdFbk; + /* speed controller pid calculation */ + iqRef = PI_Exec(&spdHandle->spdPi); + return iqRef; +} + +/** + * @brief Clear historical values of speed controller. + * @param spdHandle Speed controller struct handle. + * @retval None. + */ +void SPDCTRL_Clear(SPDCTRL_Handle *spdHandle) +{ + MCS_ASSERT_PARAM(spdHandle != NULL); + PID_Clear(&spdHandle->spdPi); +} + +/** + * @brief Reset the speed controller, fill with zero, NULL. + * @param spdHandle Speed controller struct handle. + * @retval None. + */ +void SPDCTRL_Reset(SPDCTRL_Handle *spdHandle) +{ + MCS_ASSERT_PARAM(spdHandle != NULL); + /* Reset speed ring PI */ + PID_Reset(&spdHandle->spdPi); + /* Reset the speed controller, fill with zero, NULL. */ + spdHandle->outLimit = 0.0f; + spdHandle->mtrParam = NULL; + spdHandle->ts = 0.0f; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_spd_ctrl.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_spd_ctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..5767f3a29ba2bd306b503ea64bf50f830dfbdaa7 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_spd_ctrl.h @@ -0,0 +1,49 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_spd_ctrl.h + * @author MCU Algorithm Team + * @brief Speed controller for motor control. + * This file provides functions declaration of the speed controller module. + */ + +#ifndef McuMagicTag_MCS_SPD_CTRL_H +#define McuMagicTag_MCS_SPD_CTRL_H + +#include "mcs_typedef.h" +#include "mcs_pid_ctrl.h" +#include "mcs_mtr_param.h" + +/** + * @brief Speed controller struct members and parameters. + */ +typedef struct { + PID_Handle spdPi; /**< PI controller struct in the speed controller. */ + float outLimit; /**< Maximum of the speed controller output. */ + MOTOR_Param *mtrParam; /**< Motor parameters. */ + float ts; /**< Speed controller control period (s). */ +} SPDCTRL_Handle; + +void SPDCTRL_Init(SPDCTRL_Handle *spdHandle, MOTOR_Param *mtrParam, const PI_Param piParam, float ts); + +void SPDCTRL_Reset(SPDCTRL_Handle *spdHandle); + +void SPDCTRL_Clear(SPDCTRL_Handle *spdHandle); + +float SPDCTRL_Exec(SPDCTRL_Handle *spdHandle, float spdTarget, float spdFbk); + +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_startup.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_startup.c new file mode 100644 index 0000000000000000000000000000000000000000..3bc2138dd7080382b3912f4a0d08ac48f23de188 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_startup.c @@ -0,0 +1,75 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_startup.c + * @author MCU Algorithm Team + * @brief This file provides transition method from startup stage to run stage。 + */ + +#include "mcs_startup.h" +#include "mcs_math.h" +#include "mcs_assert.h" + +/** + * @brief Init the startup control handle. + * @param startHandle The startup coontrol handle. + * @param spdBegin The begin speed for transition process. + * @param spdEnd The end speed for transition process. + * @retval None. + */ +void STARTUP_Init(STARTUP_Handle *startHandle, float spdBegin, float spdEnd) +{ + MCS_ASSERT_PARAM(startHandle != NULL); + MCS_ASSERT_PARAM(spdBegin > 0.0f); + MCS_ASSERT_PARAM(spdEnd > 0.0f); + MCS_ASSERT_PARAM(spdBegin < spdEnd); + startHandle->stage = STARTUP_STAGE_CURR; + startHandle->spdBegin = spdBegin; + startHandle->spdEnd = spdEnd; + /* current AMP = slope * control period */ + startHandle->regionInv = 1.0f / (startHandle->spdEnd - startHandle->spdBegin); +} + +/** + * @brief Clear hisitory value, assign the stage to current change. + * @param startHandle The startup control handle. + * @retval None. + */ +void STARTUP_Clear(STARTUP_Handle *startHandle) +{ + MCS_ASSERT_PARAM(startHandle != NULL); + startHandle->stage = STARTUP_STAGE_CURR; +} + +/** + * @brief Calculate the reference current in the startup stage. + * @param startHandle The startup control handle. + * @param refHz The speed reference in the startup stage. + * @return The current AMP. + */ +float STARTUP_CurrCal(const STARTUP_Handle *startHandle, float refHz) +{ + MCS_ASSERT_PARAM(startHandle != NULL); + float out; + float tmp; + /* Calculate the reference current in the startup stage */ + tmp = startHandle->spdEnd - Abs(refHz); + tmp = tmp * startHandle->regionInv; + out = tmp * startHandle->initCurr; + + return out; +} diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_startup.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_startup.h new file mode 100644 index 0000000000000000000000000000000000000000..725cdd998e939f653cdde89488cd0eb9d5c918e9 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/foc_loop_ctrl/mcs_startup.h @@ -0,0 +1,63 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_startup.h + * @author MCU Algorithm Team + * @brief Motor transition process from one speed and angle to another speed and angle. + */ + + +#ifndef McuMagicTag_MCS_STARTUP_H +#define McuMagicTag_MCS_STARTUP_H + +/** + * @brief Startup process enum. + * @details Speed transition stages: + * + STARTUP_STAGE_CURR -- Stage of current AMP is changing + * + STARTUP_STAGE_SPD -- Stage of speed is changing + * + STARTUP_STAGE_SWITCH -- Stage of switch + * + STARTUP_STAGE_DETECT -- Stage of detect switch open loop + */ +typedef enum { + STARTUP_STAGE_CURR = 1, + STARTUP_STAGE_SPD, + STARTUP_STAGE_SWITCH, + STARTUP_STAGE_DETECT, +} STARTUP_Stage; + +/** + * @brief Startup handover method struct members and parameters. + */ +typedef struct { + STARTUP_Stage stage; /**< Startup switching status. */ + float spdBegin; /**< Startup switching start speed (Hz). */ + float spdEnd; /**< Startup switching end speed (Hz). */ + float regionInv; /**< Inverse of the speed region. */ + float initCurr; /**< The initial current (A). */ +} STARTUP_Handle; + + +/** + * @defgroup STARTUP_API STARTUP API + * @brief The startup management API declaration. + * @{ + */ +void STARTUP_Init(STARTUP_Handle *startHandle, float spdBegin, float spdEnd); +void STARTUP_Clear(STARTUP_Handle *startHandle); +float STARTUP_CurrCal(const STARTUP_Handle *startHandle, float refHz); + +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/math/mcs_math.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/math/mcs_math.c new file mode 100644 index 0000000000000000000000000000000000000000..d1e932f00d330b660027820e3f9f98d5d24e3403 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/math/mcs_math.c @@ -0,0 +1,557 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_math.c + * @author MCU Algorithm Team + * @brief This file provides common math functions including trigonometric, coordinate transformation, + * square root math calculation. + */ + +#include "mcs_math.h" +#include "mcs_math_const.h" +#include "mcs_assert.h" + +/* Macro definitions --------------------------------------------------------------------------- */ +#define SIN_TABLE \ + { \ + 0, 51, 101, 151, 202, 252, 302, 352, 403, 453, 503, 553, 604, 654, 704, 754, 805, 855, 905, 955, 1006, 1056, \ + 1106, 1156, 1207, 1257, 1307, 1357, 1407, 1458, 1508, 1558, 1608, 1659, 1709, 1759, 1809, 1859, 1909, \ + 1960, 2010, 2060, 2110, 2160, 2210, 2261, 2311, 2361, 2411, 2461, 2511, 2561, 2611, 2662, 2712, 2762, \ + 2812, 2862, 2912, 2962, 3012, 3062, 3112, 3162, 3212, 3262, 3312, 3362, 3412, 3462, 3512, 3562, 3612, \ + 3662, 3712, 3762, 3812, 3862, 3912, 3962, 4012, 4061, 4111, 4161, 4211, 4261, 4311, 4360, 4410, 4460, \ + 4510, 4560, 4609, 4659, 4709, 4759, 4808, 4858, 4908, 4958, 5007, 5057, 5107, 5156, 5206, 5255, 5305, \ + 5355, 5404, 5454, 5503, 5553, 5602, 5652, 5701, 5751, 5800, 5850, 5899, 5949, 5998, 6048, 6097, 6146, \ + 6196, 6245, 6294, 6344, 6393, 6442, 6492, 6541, 6590, 6639, 6689, 6738, 6787, 6836, 6885, 6934, 6983, \ + 7033, 7082, 7131, 7180, 7229, 7278, 7327, 7376, 7425, 7474, 7523, 7572, 7620, 7669, 7718, 7767, 7816, \ + 7865, 7913, 7962, 8011, 8060, 8108, 8157, 8206, 8254, 8303, 8352, 8400, 8449, 8497, 8546, 8594, 8643, \ + 8691, 8740, 8788, 8837, 8885, 8933, 8982, 9030, 9078, 9127, 9175, 9223, 9271, 9320, 9368, 9416, 9464, \ + 9512, 9560, 9608, 9656, 9704, 9752, 9800, 9848, 9896, 9944, 9992, 10040, 10088, 10136, 10183, 10231, \ + 10279, 10327, 10374, 10422, 10470, 10517, 10565, 10612, 10660, 10707, 10755, 10802, 10850, 10897, 10945, \ + 10992, 11039, 11087, 11134, 11181, 11228, 11276, 11323, 11370, 11417, 11464, 11511, 11558, 11605, 11652, \ + 11699, 11746, 11793, 11840, 11887, 11934, 11981, 12027, 12074, 12121, 12167, 12214, 12261, 12307, 12354, \ + 12400, 12447, 12493, 12540, 12586, 12633, 12679, 12725, 12772, 12818, 12864, 12910, 12957, 13003, 13049, \ + 13095, 13141, 13187, 13233, 13279, 13325, 13371, 13417, 13463, 13508, 13554, 13600, 13646, 13691, 13737, \ + 13783, 13828, 13874, 13919, 13965, 14010, 14056, 14101, 14146, 14192, 14237, 14282, 14327, 14373, 14418, \ + 14463, 14508, 14553, 14598, 14643, 14688, 14733, 14778, 14823, 14867, 14912, 14957, 15002, 15046, 15091, \ + 15136, 15180, 15225, 15269, 15314, 15358, 15402, 15447, 15491, 15535, 15580, 15624, 15668, 15712, 15756, \ + 15800, 15844, 15888, 15932, 15976, 16020, 16064, 16108, 16151, 16195, 16239, 16282, 16326, 16369, 16413, \ + 16456, 16500, 16543, 16587, 16630, 16673, 16717, 16760, 16803, 16846, 16889, 16932, 16975, 17018, 17061, \ + 17104, 17147, 17190, 17233, 17275, 17318, 17361, 17403, 17446, 17488, 17531, 17573, 17616, 17658, 17700, \ + 17743, 17785, 17827, 17869, 17911, 17953, 17995, 18037, 18079, 18121, 18163, 18205, 18247, 18288, 18330, \ + 18372, 18413, 18455, 18496, 18538, 18579, 18621, 18662, 18703, 18745, 18786, 18827, 18868, 18909, 18950, \ + 18991, 19032, 19073, 19114, 19155, 19195, 19236, 19277, 19317, 19358, 19398, 19439, 19479, 19520, 19560, \ + 19600, 19641, 19681, 19721, 19761, 19801, 19841, 19881, 19921, 19961, 20001, 20041, 20080, 20120, 20160, \ + 20199, 20239, 20278, 20318, 20357, 20397, 20436, 20475, 20514, 20554, 20593, 20632, 20671, 20710, 20749, \ + 20788, 20826, 20865, 20904, 20943, 20981, 21020, 21058, 21097, 21135, 21174, 21212, 21250, 21289, 21327, \ + 21365, 21403, 21441, 21479, 21517, 21555, 21593, 21630, 21668, 21706, 21744, 21781, 21819, 21856, 21894, \ + 21931, 21968, 22005, 22043, 22080, 22117, 22154, 22191, 22228, 22265, 22302, 22339, 22375, 22412, 22449, \ + 22485, 22522, 22558, 22595, 22631, 22667, 22704, 22740, 22776, 22812, 22848, 22884, 22920, 22956, 22992, \ + 23028, 23063, 23099, 23135, 23170, 23206, 23241, 23277, 23312, 23347, 23383, 23418, 23453, 23488, 23523, \ + 23558, 23593, 23628, 23662, 23697, 23732, 23767, 23801, 23836, 23870, 23904, 23939, 23973, 24007, 24042, \ + 24076, 24110, 24144, 24178, 24212, 24245, 24279, 24313, 24347, 24380, 24414, 24447, 24481, 24514, 24547, \ + 24581, 24614, 24647, 24680, 24713, 24746, 24779, 24812, 24845, 24878, 24910, 24943, 24975, 25008, 25040, \ + 25073, 25105, 25137, 25170, 25202, 25234, 25266, 25298, 25330, 25362, 25393, 25425, 25457, 25488, 25520, \ + 25551, 25583, 25614, 25646, 25677, 25708, 25739, 25770, 25801, 25832, 25863, 25894, 25925, 25955, 25986, \ + 26017, 26047, 26078, 26108, 26138, 26169, 26199, 26229, 26259, 26289, 26319, 26349, 26379, 26409, 26438, \ + 26468, 26498, 26527, 26557, 26586, 26616, 26645, 26674, 26703, 26732, 26761, 26790, 26819, 26848, 26877, \ + 26906, 26934, 26963, 26991, 27020, 27048, 27077, 27105, 27133, 27161, 27189, 27217, 27245, 27273, 27301, \ + 27329, 27356, 27384, 27412, 27439, 27467, 27494, 27521, 27549, 27576, 27603, 27630, 27657, 27684, 27711, \ + 27737, 27764, 27791, 27817, 27844, 27870, 27897, 27923, 27949, 27976, 28002, 28028, 28054, 28080, 28106, \ + 28132, 28157, 28183, 28209, 28234, 28260, 28285, 28310, 28336, 28361, 28386, 28411, 28436, 28461, 28486, \ + 28511, 28535, 28560, 28585, 28609, 28634, 28658, 28682, 28707, 28731, 28755, 28779, 28803, 28827, 28851, \ + 28875, 28898, 28922, 28946, 28969, 28993, 29016, 29039, 29063, 29086, 29109, 29132, 29155, 29178, 29201, \ + 29223, 29246, 29269, 29291, 29314, 29336, 29359, 29381, 29403, 29425, 29447, 29469, 29491, 29513, 29535, \ + 29557, 29578, 29600, 29622, 29643, 29664, 29686, 29707, 29728, 29749, 29770, 29791, 29812, 29833, 29854, \ + 29874, 29895, 29916, 29936, 29956, 29977, 29997, 30017, 30037, 30057, 30077, 30097, 30117, 30137, 30157, \ + 30176, 30196, 30215, 30235, 30254, 30273, 30292, 30312, 30331, 30350, 30369, 30387, 30406, 30425, 30443, \ + 30462, 30481, 30499, 30517, 30536, 30554, 30572, 30590, 30608, 30626, 30644, 30661, 30679, 30697, 30714, \ + 30732, 30749, 30767, 30784, 30801, 30818, 30835, 30852, 30869, 30886, 30903, 30919, 30936, 30952, 30969, \ + 30985, 31002, 31018, 31034, 31050, 31066, 31082, 31098, 31114, 31129, 31145, 31161, 31176, 31192, 31207, \ + 31222, 31237, 31253, 31268, 31283, 31298, 31312, 31327, 31342, 31357, 31371, 31386, 31400, 31414, 31429, \ + 31443, 31457, 31471, 31485, 31499, 31513, 31526, 31540, 31554, 31567, 31581, 31594, 31607, 31620, 31634, \ + 31647, 31660, 31673, 31685, 31698, 31711, 31724, 31736, 31749, 31761, 31773, 31786, 31798, 31810, 31822, \ + 31834, 31846, 31857, 31869, 31881, 31892, 31904, 31915, 31927, 31938, 31949, 31960, 31971, 31982, 31993, \ + 32004, 32015, 32025, 32036, 32047, 32057, 32067, 32078, 32088, 32098, 32108, 32118, 32128, 32138, 32148, \ + 32157, 32167, 32177, 32186, 32195, 32205, 32214, 32223, 32232, 32241, 32250, 32259, 32268, 32276, 32285, \ + 32294, 32302, 32311, 32319, 32327, 32335, 32343, 32351, 32359, 32367, 32375, 32383, 32390, 32398, 32405, \ + 32413, 32420, 32427, 32435, 32442, 32449, 32456, 32463, 32469, 32476, 32483, 32489, 32496, 32502, 32509, \ + 32515, 32521, 32527, 32533, 32539, 32545, 32551, 32557, 32562, 32568, 32573, 32579, 32584, 32589, 32595, \ + 32600, 32605, 32610, 32615, 32619, 32624, 32629, 32633, 32638, 32642, 32647, 32651, 32655, 32659, 32663, \ + 32667, 32671, 32675, 32679, 32682, 32686, 32689, 32693, 32696, 32700, 32703, 32706, 32709, 32712, 32715, \ + 32718, 32720, 32723, 32726, 32728, 32730, 32733, 32735, 32737, 32739, 32741, 32743, 32745, 32747, 32749, \ + 32751, 32752, 32754, 32755, 32756, 32758, 32759, 32760, 32761, 32762, 32763, 32764, 32764, 32765, 32766, \ + 32766, 32767, 32767, 32767, 32767, 32767 \ + } + +const float atanInBottom[50] = { 0.0f, 0.102040816326531f, 0.204081632653061f, 0.306122448979592f, \ + 0.408163265306122f, 0.510204081632653f, 0.612244897959184f, 0.714285714285714f, \ + 0.816326530612245f, 0.918367346938776f, 1.02040816326531f, 1.12244897959184f, \ + 1.22448979591837f, 1.32653061224490f, 1.42857142857143f, 1.53061224489796f, \ + 1.63265306122449f, 1.73469387755102f, 1.83673469387755f, 1.93877551020408f, \ + 2.04081632653061f, 2.14285714285714f, 2.24489795918367f, 2.34693877551020f, \ + 2.44897959183673f, 2.55102040816327f, 2.65306122448980f, 2.75510204081633f, \ + 2.85714285714286f, 2.95918367346939f, 3.06122448979592f, 3.16326530612245f, \ + 3.26530612244898f, 3.36734693877551f, 3.46938775510204f, 3.57142857142857f, \ + 3.67346938775510f, 3.77551020408163f, 3.87755102040816f, 3.97959183673469f, \ + 4.08163265306123f, 4.18367346938776f, 4.28571428571429f, 4.38775510204082f, \ + 4.48979591836735f, 4.59183673469388f, 4.69387755102041f, 4.79591836734694f, \ + 4.89795918367347f, 5.0f}; +const float atanValBottom[50] = { 0.0f, 0.101688851763077f, 0.201317108374641f, 0.297064212341043f, \ + 0.387523805780279f, 0.471777511180750f, 0.549374484771551f, 0.620249485982822f, \ + 0.684617164312781f, 0.742870628777664f, 0.795498829982770f, 0.843026590874922f, \ + 0.885975080852296f, 0.924838220488786f, 0.960070362405688f, 0.992081381881698f, \ + 1.02123631326852f, 1.04785756322372f, 1.07222842115668f, 1.09459707572452f, \ + 1.11518067358367f, 1.13416916698136f, 1.15172882709508f, 1.16800537775525f, \ + 1.18312674842090f, 1.19720546875916f, 1.21034073815249f, 1.22262020713844f, \ + 1.23412150740817f, 1.24491356451280f, 1.25505772401419f, 1.26460871813527f, \ + 1.27361549637858f, 1.28212194027307f, 1.29016747945525f, 1.29778762370819f, \ + 1.30501442335451f, 1.31187686849742f, 1.31840123598843f, 1.32461139163550f, \ + 1.33052905401396f, 1.33617402527335f, 1.34156439351790f, 1.34671671065198f, \ + 1.35164614900430f, 1.35636663955779f, 1.36089099420126f, 1.36523101407236f, \ + 1.36939758576738f, 1.37340076694502f}; +const float atanInMid[25] = { 5.0f, 5.625f, 6.25f, 6.875f, 7.5f, \ + 8.125f, 8.75f, 9.375f, 10.0f, 10.625f, \ + 11.25f, 11.875f, 12.5f, 13.125f, 13.75f, \ + 14.375f, 15.0f, 15.625f, 16.25f, 16.875f, \ + 17.5f, 18.125f, 18.75f, 19.375f, 20.0f}; +const float atanValMid[25] = { 1.373400766945016f, 1.394856701342369f, 1.41214106460850f, 1.42635474842025f, \ + 1.43824479449822f, 1.44833526937756f, 1.45700431965119f, 1.46453146390382f, \ + 1.47112767430373f, 1.47695511416556f, 1.48214044492746f, 1.48678401498740f, \ + 1.49096634108266f, 1.49475276751578f, 1.49819687306440f, 1.50134300079957f, \ + 1.50422816301907f, 1.50688349400616f, 1.50933537091213f, 1.51160628786678f, \ + 1.51371554438863f, 1.51567979250081f, 1.51751347523520f, 1.51922918085206f, \ + 1.52083793107295f}; +const float atanInTop[10] = { 20.0f, 128.888888888889f, 237.777777777778f, 346.666666666667f, \ + 455.555555555556f, 564.444444444445f, 673.333333333333f, 782.222222222222f, \ + 891.111111111111f, 1000.0f}; +const float atanValTop[10] = { 1.52083793107295f, 1.56303786177943f, 1.56659074411305f, 1.56791171941121f, \ + 1.56860120836944f, 1.56902467510518f, 1.56931117937196f, 1.56951791840043f, \ + 1.56967413275225f, 1.56979632712823f}; + +#define SIN_MASK 0x0C00 +#define U0_90 0x0800 +#define U90_180 0x0C00 +#define U180_270 0x0000 +#define U270_360 0x0400 +#define SIN_TAB_LEN 0x03FF +#define Q15_BASE 32768 +#define ANGLE_TO_INDEX_SHIFT 4 + +#define ATAN_INPUTVALUE_MIN 5.0f +#define ATAN_INPUTVALUE_MID 20.0f +#define ATAN_INPUTVALUE_MAX 1000.0f + +#define MATH_FACTORIAL3INVERSE 0.16666667f /**< 1 / 6 */ +#define MATH_FACTORIAL5INVERSE 0.008333333f /**< 1 / 120 */ +#define MATH_FACTORIAL7INVERSE 0.0001984127f /**< 1 / 5040 */ + +/* Private variables --------------------------------------------------------- */ +const short g_sinTable[SIN_TAB_LEN + 1] = SIN_TABLE; + + +/** + * @brief Using Taylor Expansion to Calculate Sin Values in rad. + * @param angle Angle value to be calculated. + * @retval float Calculated sin value. + */ +static float TaylorCalSinIn90(float angle) +{ + float radian = angle; + float radian3 = radian * radian * radian; /* power(3) */ + float radian5 = radian3 * radian * radian; + float radian7 = radian5 * radian * radian; /* power(7) */ + /* Using Taylor Expansion to Calculate Sin Values in 90 Degrees. */ + return (radian - radian3 * MATH_FACTORIAL3INVERSE + \ + radian5 * MATH_FACTORIAL5INVERSE - radian7 * MATH_FACTORIAL7INVERSE); +} + +/** + * @brief Using Taylor Expansion to Calculate Sin Values for Any Angle. + * @param angle Angle value to be calculated. + * @retval float Calculated sin value. + */ +float GetSin(float angle) +{ + /* limit the data scope to (0 - 2PI) */ + float angleIn2pi = Mod(angle, DOUBLE_PI); + if (angleIn2pi < 0) { + angleIn2pi = angleIn2pi + DOUBLE_PI; + } + if (angleIn2pi < HALF_PI) { /* 0 ~ 90° */ + return TaylorCalSinIn90(angleIn2pi); + } + if (angleIn2pi < ONE_PI) { /* 90 ~ 180° */ + return TaylorCalSinIn90(ONE_PI - angleIn2pi); + } + if (angleIn2pi < THREE_PI_DIV_TWO) { /* 180 ~ 270° */ + return -TaylorCalSinIn90(angleIn2pi - ONE_PI); + } + return -TaylorCalSinIn90(DOUBLE_PI - angleIn2pi); /* 270 ~ 360° */ +} + +/** + * @brief Using Taylor Expansion to Calculate Sin Values for Any Angle. + * @param angle Angle value to be calculated. + * @retval float Calculated sin value. + */ +float GetCos(float angle) +{ + /* limit the data scope to (0 - 2PI) */ + float angleIn2pi = Mod(angle, DOUBLE_PI); + if (angleIn2pi < 0) { + angleIn2pi = angleIn2pi + DOUBLE_PI; + } + if (angleIn2pi < HALF_PI) { /* 0 ~ 90° */ + return TaylorCalSinIn90(HALF_PI - angleIn2pi); + } + if (angleIn2pi < ONE_PI) { /* 90 ~ 180° */ + return -TaylorCalSinIn90(angleIn2pi - HALF_PI); + } + if (angleIn2pi < THREE_PI_DIV_TWO) { /* 180 ~ 270° */ + return -TaylorCalSinIn90(THREE_PI_DIV_TWO - angleIn2pi); + } + return TaylorCalSinIn90(angleIn2pi - THREE_PI_DIV_TWO); /* 270 ~ 360° */ +} + + +/** + * @brief Calculate sine and cosine function of the input angle. + * @param val: Output result, which contain the calculated sin, cos value. + * @param angle: The input parameter angle (rad). + * @retval None. + */ +void TrigCalc(TrigVal *val, float angle) +{ + MCS_ASSERT_PARAM(val != NULL); + val->sin = GetSin(angle); + val->cos = GetCos(angle); +} + +/** + * @brief Park transformation: transforms stator values alpha and beta, which + * belong to a stationary albe reference frame, to a rotor flux + * synchronous reference dq frame. + * @param albe: Input alpha beta axis value. + * @param angle: Input the theta angle (rad). + * @param dq: Output DQ axis value. + * @retval None + */ +void ParkCalc(const AlbeAxis *albe, float angle, DqAxis *dq) +{ + MCS_ASSERT_PARAM(albe != NULL); + MCS_ASSERT_PARAM(dq != NULL); + float alpha = albe->alpha; + float beta = albe->beta; + TrigVal localTrigVal; + /* The projection of ia, ib, and ic currents on alpha and beta axes is equivalent to that on d, q axes. */ + TrigCalc(&localTrigVal, angle); + dq->d = alpha * localTrigVal.cos + beta * localTrigVal.sin; + dq->q = -alpha * localTrigVal.sin + beta * localTrigVal.cos; +} + +/** + * @brief Inverse Park transformation: transforms stator values d and q, which + * belong to a rotor flux synchronous reference dq frame, to a stationary + * albe reference frame. + * @param dq: Input DQ axis value. + * @param angle: Input the theta angle (rad). + * @param albe: Output alpha beta axis value. + * @retval None + */ +void InvParkCalc(const DqAxis *dq, float angle, AlbeAxis *albe) +{ + MCS_ASSERT_PARAM(dq != NULL); + MCS_ASSERT_PARAM(albe != NULL); + float d = dq->d; + float q = dq->q; + TrigVal localTrigVal; + /* Inversely transform the d, q-axis current to alpha ,beta. */ + TrigCalc(&localTrigVal, angle); + albe->alpha = d * localTrigVal.cos - q * localTrigVal.sin; + albe->beta = d * localTrigVal.sin + q * localTrigVal.cos; +} + +/** + * @brief Clarke transformation: transforms stationary three-phase quantites to + * stationary albe quantites. + * @param uvw: Clarke struct handle. + * @param albe: AlbeAxis struct handle used to store the Clarke transform output. + * @retval None. + */ +void ClarkeCalc(const UvwAxis *uvw, AlbeAxis *albe) +{ + MCS_ASSERT_PARAM(uvw != NULL); + MCS_ASSERT_PARAM(albe != NULL); + albe->alpha = uvw->u; + albe->beta = ONE_DIV_SQRT3 * (uvw->u + 2.0f * uvw->v); +} + +/** + * @brief This function returns the absolute value of the input value. + * @param val: The quantity that wants to execute absolute operation. + * @retval The absolute value of the input value. + */ +float Abs(float val) +{ + return (val >= 0.0f) ? val : (-val); +} + +/** + * @brief Clamp operation. + * @param val Value that needs to be clamped. + * @param upperLimit The upper limitation. + * @param lowerLimit The lower limitation. + * @retval Clamped value. + */ +float Clamp(float val, float upperLimit, float lowerLimit) +{ + MCS_ASSERT_PARAM(upperLimit > lowerLimit); + float result; + /* Clamping Calculation. */ + if (val >= upperLimit) { + result = upperLimit; + } else if (val <= lowerLimit) { + result = lowerLimit; + } else { + result = val; + } + return result; +} + +/** + * @brief Get bigger value. + * @param val1 The value to be compared. + * @param val2 The value to be compared. + * @retval The greater value. + */ +float Max(float val1, float val2) +{ + return ((val1 >= val2) ? val1 : val2); +} + +/** + * @brief Get smaller value. + * @param val1 The value to be compared. + * @param val2 The value to be compared. + * @retval The smaller value. + */ +float Min(float val1, float val2) +{ + return ((val1 <= val2) ? val1 : val2); +} + +/** + * @brief Fast sqrt calculation using ASM. + * @param val Float val. + * @retval Sqrt result. + */ +float Sqrt(float val) +{ + MCS_ASSERT_PARAM(val >= 0.0f); + float rd = val; + + __asm volatile("fsqrt.s %0, %1" : "=f"(rd) : "f"(val)); + + return rd; +} + + +/** + * @brief Angle difference calculation. + * @param angle1 Angle to be substracted. + * @param angle2 Angle to substract. + * @retval Angle difference. + */ +float AngleSub(float angle1, float angle2) +{ + /* Calculate the error of the two angle. */ + float err = angle1 - angle2; + + /* If error between -pi to pi, return error without changes. */ + err = Mod(err, DOUBLE_PI); + if (err > ONE_PI) { + err -= DOUBLE_PI; + } else if (err < -ONE_PI) { + err += DOUBLE_PI; + } + + return err; +} + + +/** + * @brief Dichotomy to find the position of the target value in the array. + * @param u: Target Value. + * @param table: Pointer of Array. + * @param startIndex: Start Index + * @param maxIndex: Max Index. + * @retval Target index. + */ + +static unsigned short BinSearch(float u, const float *table, + unsigned short startIndex, + unsigned short maxIndex) +{ + MCS_ASSERT_PARAM(table != NULL); + /* The dot to the left of the dichotomy */ + unsigned short iLeft; + /* The dot to the right of the dichotomy */ + unsigned short iRight; + /* The point in the middle of the dichotomy */ + unsigned short iMid; + + /* Binary Search */ + iMid = startIndex; + iLeft = 0U; + iRight = maxIndex; + while ((unsigned short)(iRight - iLeft) > 1U) { + if (u < table[iMid]) { + /* The target value is a bit smaller than the current value on the left */ + iRight = iMid; + } else { + /* TThe target value is greater than the current value on the right */ + iLeft = iMid; + } + /* Get the next intermediate point */ + iMid = ((unsigned short)(iRight + iLeft)) >> 1; + } + return iLeft; +} + +/** + * @brief Dichotomy to find the position of the target value in the array. + * @param u: Target Value. + * @param table: Pointer of Array. + * @param fraction: Poniter ratio value addr. + * @param maxIndex: Max Index. + * @retval Target index. + */ +static unsigned short PreLookBinSearch(float u, const float *table, + unsigned short maxIndex, + float *fraction) +{ + MCS_ASSERT_PARAM(table != NULL); + MCS_ASSERT_PARAM(fraction != NULL); + /* Dichotomy to find the position of the target value in the array */ + unsigned short index; + if (u <= table[0U]) { + /* Less than the minimum value in the table */ + index = 0U; + *fraction = 0.0f; + } else if (u < table[maxIndex]) { + index = BinSearch(u, table, maxIndex >> 1U, maxIndex); + *fraction = (u - table[index]) / (table[index + 1U] - table[index]); + } else { + /* Greater than the minimum value in the table */ + index = maxIndex; + *fraction = 0.0f; + } + return index; +} + +/** + * @brief calculating arc tangent. + * @param u: Target Value. + * @retval Arctangent value of U. + */ +static float ATan(float u) +{ + float tmp = Abs(u); + float frac = 0.0f; + unsigned short index = 0; + float y = 0.0f; + if (tmp >= 0.0f && tmp < ATAN_INPUTVALUE_MIN) { + index = PreLookBinSearch(tmp, atanInBottom, 49U, &frac); /* atanInBottom Max Index is 49 */ + y = atanValBottom[index] + frac * (atanValBottom[index + 1] - atanValBottom[index]); + } else if (tmp >= ATAN_INPUTVALUE_MIN && tmp < ATAN_INPUTVALUE_MID) { + index = PreLookBinSearch(tmp, atanInMid, 24U, &frac); /* atanInMid Max Index is 24 */ + y = atanValMid[index] + frac * (atanValMid[index + 1] - atanValMid[index]); + } else if (tmp >= ATAN_INPUTVALUE_MID && tmp < ATAN_INPUTVALUE_MAX) { + index = PreLookBinSearch(tmp, atanInTop, 9U, &frac); /* atanInTop Max Index is 9 */ + y = atanValTop[index] + frac * (atanValTop[index + 1] - atanValTop[index]); + } else { + y = HALF_PI; /* The input parameter is greater than the maximum radian, The value is PI/2. */ + } + return (u > 0.0f)? y : (- y); +} + + +/** + * @brief modulo operation. + * @param val1 The value to be modulo. + * @param val2 The value to modulo. + * @retval modulo result. + */ +float Mod(float val1, float val2) +{ + MCS_ASSERT_PARAM(val2 > 0.0f); + + int temp = (int)(val1 / val2); + float res = val1 - (float)temp * val2; + return res; +} + + +/** + * @brief Atan2 arctangent calculation. + * @param x Floating-point value representing the X-axis coordinate. + * @param y Floating-point value representing the Y-axis coordinate. + * @retval The atan2 function returns the azimuth from the origin to the point (x, y), that is, + the angle from the x axis. It can also be understood as the argument of the complex number x+yi. + The unit of the returned value is radian. The value range is -pi ~ pi. + */ +float Atan2(float x, float y) +{ + float fZero = 0.0f; + if (x > fZero) { + return ATan(y / x); + } + if (x < fZero && y >= fZero) { + return ATan(y / x) + ONE_PI; + } + if (x < fZero && y < fZero) { + return ATan(y / x) - ONE_PI; + } + /* boundary condition */ + if ((Abs(x) < 0.0001f) && y > fZero) { + return (HALF_PI); + } + if (Abs(x) < 0.0001f && y < fZero) { + return -(HALF_PI); + } + /* default return */ + return fZero; +} + +/** + * @brief Saturation function for dead voltage computing. + * @param u The current amp of zero crossing point. + * @param delta Saturated output point. + * @return Saturation value ([-1.0f, 1.0f]). + */ +float Sat(float u, float delta) +{ + BASE_FUNC_ASSERT_PARAM(delta > 0.0f); + /* less than -0.1, return -1 */ + if (u < -delta) { + return -1.0f; + } else if (u > delta) { /* large than 0.1, return 1 */ + return 1.0f; + } else { + return (u / delta); /* all other values */ + } +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/math/mcs_math.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/math/mcs_math.h new file mode 100644 index 0000000000000000000000000000000000000000..0992dc10a9c4f71f3dd9d10092bfde7b38664ad6 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/math/mcs_math.h @@ -0,0 +1,63 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_math.h + * @author MCU Algorithm Team + * @brief Math library. + * This file provides math functions declaration of motor math module. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_MATH_H +#define McuMagicTag_MCS_MATH_H + +/* Includes ------------------------------------------------------------------------------------ */ +#include "mcs_typedef.h" +#include "base_math.h" + + +/** + * @brief sin cos define + */ +typedef struct { + float sin; /**< The sine value of input angle. */ + float cos; /**< The cosine value of input angle. */ +} TrigVal; + + +/** + * @defgroup MATH_API MATH API + * @brief The common math API definition. + * @{ + */ +float GetSin(float angle); +float GetCos(float angle); +void TrigCalc(TrigVal *val, float angle); +void ParkCalc(const AlbeAxis *albe, float angle, DqAxis *dq); +void InvParkCalc(const DqAxis *dq, float angle, AlbeAxis *albe); +void ClarkeCalc(const UvwAxis *uvw, AlbeAxis *albe); +float Abs(float val); +float Clamp(float val, float upperLimit, float lowerLimit); +float Max(float val1, float val2); +float Min(float val1, float val2); +float Sqrt(float val); +float AngleSub(float angle1, float angle2); +float Mod(float val1, float val2); +float Sat(float u, float delta); +float Atan2(float x, float y); + +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/math/mcs_math_const.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/math/mcs_math_const.h new file mode 100644 index 0000000000000000000000000000000000000000..6a605bd9ea428da9849e99ade12a2b7659405fe6 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/math/mcs_math_const.h @@ -0,0 +1,72 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_math_const.h + * @author MCU Algorithm Team + * @brief This file provides math constant macro definition functionality for + * managing math calculation number definitions. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_MCS_MATH_CONST_H +#define McuMagicTag_MCS_MATH_CONST_H + +/** + * @addtogroup MATH + * @brief Math const definition. + * @{ + */ + +/** + * @defgroup MATH_CONST MATH CONST + * @brief The common math const definition for motor control. + * @{ + */ +/* Macro definitions ---------------------------------------------------------*/ +#define ONE_DIV_THREE (0.3333333f) /**< 1/3 */ +#define TWO_DIV_THREE (0.6666667f) /**< 2/3 */ +#define ONE_PI_DIV_SIX (0.5235988f) /**< PI/6 */ +#define ONE_PI_DIV_THREE (1.047197f) /**< PI/3 */ +#define ONE_PI (3.141593f) /**< PI */ +#define DOUBLE_PI_DIV_THREE (2.094395f) /**< 2PI/3 */ +#define DOUBLE_PI (6.283185f) /**< 2*PI */ +#define SQRT3_DIV_TWO (0.8660254f) /**< Sqrt(3)/2 */ +#define ONE_DIV_SQRT3 (0.5773503f) /**< 1/sqrt(3) */ +#define ONE_DIV_DOUBLE_PI (0.1591549f) /**< 1/(2*PI) */ +#define RAD_TO_DEG (57.29578f) /**< 1/pi*180 */ +#define RAD_TO_DIGITAL (10430.06f) /**< 1/pi*32767 */ +#define DIGITAL_TO_RAD (0.00009587673f) /**< pi/32767 */ +#define HALF_PI (1.5707963f) /**< 0.5*pi */ +#define THREE_PI_DIV_TWO (4.7123890f) /**< 1.5*pi */ +#define ONE_DIV_SIX (0.16666667f) /**< 1/6 */ +#define SEVEN_DIV_SIX (1.16666667f) /**< 7/6 */ +#define SIXTY_FIVE_DIV_SIX (10.8333333f) /**< 65/6 */ +#define SEVENTY_ONE_DIV_SIX (11.8333333f) /**< 71/6 */ +#define ONE_DIV_NINE (0.11111111f) /**< 1/9 */ +#define ONE_DIV_TWELVE (0.08333333f) /**< 1/12 */ +#define SQRT2 (1.41421356f) /**< sqrt(2) */ +#define SMALL_FLOAT (0.00000001f) +#define LARGE_FLOAT (10000.0f) +/** + * @} + */ + + /** + * @} + */ + +#endif /* McuMagicTag_MCS_MATH_CONST_H */ diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/modulation/mcs_r1_svpwm.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/modulation/mcs_r1_svpwm.c new file mode 100644 index 0000000000000000000000000000000000000000..911f6702dfb85cd5613c0ac81ba9b9859c1cf11e --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/modulation/mcs_r1_svpwm.c @@ -0,0 +1,234 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_r1_svpwm.c + * @author MCU Algorithm Team + * @brief This file provides function of Space-vector pulse-width-modulation calculations + * in case of single shunt current sample and current reconstruction. + */ + + +#include "mcs_r1_svpwm.h" +#include "mcs_assert.h" + + +/** + * @brief R1SVPWM handlel init. + * @param r1svHandle The R1SVPWM handle. + * @param voltPu Voltage per unit value. + */ +void R1SVPWM_Init(R1SVPWM_Handle *r1svHandle, float voltPu, float samplePointShift, float sampleWindow) +{ + MCS_ASSERT_PARAM(r1svHandle != NULL); + MCS_ASSERT_PARAM(voltPu > 0.0f); + MCS_ASSERT_PARAM(sampleWindow >= 0.0f && sampleWindow < 1.0f); + MCS_ASSERT_PARAM(samplePointShift > -1.0f && samplePointShift < 1.0f); + /* Initialize the phase-shift sampling window size and sampling point offset. */ + r1svHandle->samplePointShift = samplePointShift; + r1svHandle->sampleWindow = sampleWindow; + /* Initialize the Voltage per unit value */ + r1svHandle->voltPu = voltPu; + r1svHandle->oneDivVoltPu = 1.0f / voltPu; +} + +/** + * @brief R1SVPWM clear. + * @param r1svHandle The R1SVPWM handle. + * @retval None. + */ +void R1SVPWM_Clear(R1SVPWM_Handle *r1svHandle) +{ + MCS_ASSERT_PARAM(r1svHandle != NULL); + /* Clear the historical values calculated by the R1 SVPWM. */ + r1svHandle->voltIndex = 0; + r1svHandle->voltIndexLast = 0; + r1svHandle->samplePoint[SOCA] = 0.0f; + r1svHandle->samplePoint[SOCB] = 0.0f; +} + +/** + * @brief Phase shift calculation for single resistance sampling. + * @param r1SvCalc R1 svpwm calculation handle. + * @param sampleWindow sample window. + * @retval None. + */ +void R1SVPWM_PhaseShift(R1SVPWM_CALC_Handle *r1SvCalc, float sampleWindow) +{ + MCS_ASSERT_PARAM(r1SvCalc != NULL); + MCS_ASSERT_PARAM(sampleWindow >= 0.0f && sampleWindow < 1.0f); + /* Pointer to the array of left and right comparison values. */ + float *compRight = r1SvCalc->compRight; + float *compLeft = r1SvCalc->compLeft; + /* Comparison of three levels. */ + float compMax = r1SvCalc->svCalc.comp[SVPWM_COMP_VAL_MAX]; + float compMid = r1SvCalc->svCalc.comp[SVPWM_COMP_VAL_MID]; + float compMin = r1SvCalc->svCalc.comp[SVPWM_COMP_VAL_MIN]; + /* action time of two vectors */ + float t1 = r1SvCalc->svCalc.t1; + float t2 = r1SvCalc->svCalc.t2; + /** + * PWM phase shift: + * When the action time t1 of the first vector is less than the minimum sampling window, + * the phase with the smallest comparison value(with the largest duty) shifts to the right. + */ + if (t1 < sampleWindow) { + compRight[SVPWM_COMP_VAL_MIN] = compMid - sampleWindow; + compLeft[SVPWM_COMP_VAL_MIN] = compMin + sampleWindow - t1; + } else { + compRight[SVPWM_COMP_VAL_MIN] = compMin; + compLeft[SVPWM_COMP_VAL_MIN] = compMin; + } + + /** + * When the action time t2 of the second vector is less than the minimum sampling window, + * the phase with the largest comparison value (minimum duty) shifts to the left. + */ + if (t2 < sampleWindow) { + compRight[SVPWM_COMP_VAL_MAX] = compMid + sampleWindow; + compLeft[SVPWM_COMP_VAL_MAX] = compMax - sampleWindow + t2; + } else { + compRight[SVPWM_COMP_VAL_MAX] = compMax; + compLeft[SVPWM_COMP_VAL_MAX] = compMax; + } + /* intermediate large unshifted phase */ + compRight[SVPWM_COMP_VAL_MID] = compMid; + compLeft[SVPWM_COMP_VAL_MID] = compMid; +} + +/** + * @brief The duty cycles of PWM wave of three-phase upper switches are + * calculated in the two-phase stationary coordinate system (albe). + * @param r1svHandle R1SVPWM struct handle. + * @param uAlbe Input voltage vector. + * @param dutyUvwLeft Three-phase left duty cycle. + * @param dutyUvwRight Three-phase right duty cycle. + * @retval None. + */ +void R1SVPWM_Exec(R1SVPWM_Handle *r1svHandle, const AlbeAxis *uAlbe, UvwAxis *dutyUvwLeft, UvwAxis *dutyUvwRight) +{ + MCS_ASSERT_PARAM(r1svHandle != NULL); + MCS_ASSERT_PARAM(uAlbe != NULL); + MCS_ASSERT_PARAM(dutyUvwLeft != NULL); + MCS_ASSERT_PARAM(dutyUvwRight != NULL); + R1SVPWM_CALC_Handle r1SvCalc; + float *samplePoint = r1svHandle->samplePoint; + r1SvCalc.svCalc.vAlpha = uAlbe->alpha * r1svHandle->oneDivVoltPu; + r1SvCalc.svCalc.vBeta = uAlbe->beta * r1svHandle->oneDivVoltPu; + + /* Sector Calculation */ + SVPWM_SectorCalc(&r1SvCalc.svCalc); + /** + * In control tick k, record the sector number of the voltage vector calculated in the k–1 tick. + * For the next tick(k+1), it is the voltage vector to be applied. + * Calculate the sector number of the voltage vector that actually acts on the (k+1)th tick. + */ + r1svHandle->voltIndexLast = r1svHandle->voltIndex; + r1svHandle->voltIndex = r1SvCalc.svCalc.sectorIndex; + + if (r1SvCalc.svCalc.sectorIndex < SVPWM_SECTOR_INDEX_MIN || r1SvCalc.svCalc.sectorIndex > SVPWM_SECTOR_INDEX_MAX) { + dutyUvwLeft->u = 0.5f; + dutyUvwLeft->v = 0.5f; + dutyUvwLeft->w = 0.5f; + dutyUvwRight->u = 0.5f; + dutyUvwRight->v = 0.5f; + dutyUvwRight->w = 0.5f; + samplePoint[SOCA] = 0.5f; + samplePoint[SOCB] = 0.5f; + return; + } + /* Calculate three comparison values: max, medium, and min. */ + SVPWM_CompareValCalc(&r1SvCalc.svCalc); + /* phase shift */ + R1SVPWM_PhaseShift(&r1SvCalc, r1svHandle->sampleWindow); + + /* Set sample point SOCA */ + samplePoint[SOCA] = r1SvCalc.compRight[SVPWM_COMP_VAL_MIN] + r1svHandle->samplePointShift; + /* Set sample point SOCB */ + samplePoint[SOCB] = r1SvCalc.compRight[SVPWM_COMP_VAL_MID] + r1svHandle->samplePointShift; + /* Three-phase duty cycle data index based on sector convert */ + SVPWM_IndexConvert(&r1SvCalc.svCalc); + + dutyUvwLeft->u = r1SvCalc.compLeft[r1SvCalc.svCalc.indexU]; + dutyUvwLeft->v = r1SvCalc.compLeft[r1SvCalc.svCalc.indexV]; + dutyUvwLeft->w = r1SvCalc.compLeft[r1SvCalc.svCalc.indexW]; + dutyUvwRight->u = r1SvCalc.compRight[r1SvCalc.svCalc.indexU]; + dutyUvwRight->v = r1SvCalc.compRight[r1SvCalc.svCalc.indexV]; + dutyUvwRight->w = r1SvCalc.compRight[r1SvCalc.svCalc.indexW]; +} + +/** + * @brief The stator current uvw is reconstructed from bus current according to the sector index + * of the output voltage vector. + * @param sectorIndex Sector index of the output voltage vector. + * @param currSocA Bus current at the sample point A. + * @param currSocB Bus current at the sample point B. + * @param curr The reconstructed stator current uvw. + * @retval None. + */ +void R1CurrReconstruct(unsigned int sectorIndex, float currSocA, float currSocB, UvwAxis *curr) +{ + MCS_ASSERT_PARAM(curr != NULL); + /* Reconstructed uvw three-phase current */ + float u; + float v; + float w; + + /* + * The stator current uvw is reconstructed from bus current according to the sector index + * of the output voltage vector. + */ + switch (sectorIndex) { + case SVPWM_ANGLE_0_TO_60_DEG: /* 0 ~ 60° Voltage vector sector */ + u = currSocA; + w = -currSocB; + v = -u - w; + break; + case SVPWM_ANGLE_60_TO_120_DEG: /* 60 ~ 120° Voltage vector sector */ + v = currSocA; + w = -currSocB; + u = -v - w; + break; + case SVPWM_ANGLE_120_TO_180_DEG: /* 120 ~ 180° Voltage vector sector */ + v = currSocA; + u = -currSocB; + w = -u - v; + break; + case SVPWM_ANGLE_180_TO_240_DEG: /* 180 ~ 240° Voltage vector sector */ + w = currSocA; + u = -currSocB; + v = -u - w; + break; + case SVPWM_ANGLE_240_TO_300_DEG: /* 240 ~ 300° Voltage vector sector */ + w = currSocA; + v = -currSocB; + u = -v - w; + break; + case SVPWM_ANGLE_300_TO_360_DEG: /* 300 ~ 360° Voltage vector sector */ + u = currSocA; + v = -currSocB; + w = -u - v; + break; + default: + u = 0.0f; + v = 0.0f; + w = 0.0f; + break; + } + curr->u = u; + curr->v = v; + curr->w = w; +} diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/modulation/mcs_r1_svpwm.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/modulation/mcs_r1_svpwm.h new file mode 100644 index 0000000000000000000000000000000000000000..3bc1990184ba15e720423f5f41f4c7037cb866a7 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/modulation/mcs_r1_svpwm.h @@ -0,0 +1,90 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_r1_svpwm.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of Space-vector pulse-width-modulation calculations. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_MCS_R1_SVPWM_H +#define McuMagicTag_MCS_R1_SVPWM_H + +/* Includes ------------------------------------------------------------------*/ +#include "mcs_typedef.h" +#include "mcs_svpwm.h" + +/** The ADC sampling twice for one resistor motor control application, SOCA + SOCB */ +#define SOCA 0 +#define SOCB 1 +#define R1_ADC_SAMPLE_NUMS 2 + +/** + * @brief Structure of temporary variables for R1SVPWM calculation. + */ +typedef struct { + SVPWM_CALC_Handle svCalc; + float compLeft[SVPWM_COMP_VAL_TOTAL]; + float compRight[SVPWM_COMP_VAL_TOTAL]; +} R1SVPWM_CALC_Handle; +/** + * @defgroup R1_SVPWM_MODULE R1 SVPWM MODULE + * @brief The SVPWM module for R1(One Resistor) application. + * @{ + */ + +/** + * @defgroup R1_SVPWM_STRUCT R1 SVPWM STRUCT + * @brief The SVPWM module's struct definition for R1(One Resistor) application. + * @{ + */ +/* Typedef definitions -------------------------------------------------------*/ +/** + * @brief R1SVPWM struct members and parameters. + */ +typedef struct { + float voltPu; /**< Voltage per unit value. */ + float oneDivVoltPu; /**< Reciprocal of voltage unit value. */ + float sampleWindow; /**< Sampling Window */ + float samplePointShift; /**< Sampling point phase shift */ + unsigned int voltIndex; /**< Index of voltage sector. */ + unsigned int voltIndexLast; /**< Index of last voltage sector. */ + float samplePoint[R1_ADC_SAMPLE_NUMS]; /**< Sample point of twice sample. */ +} R1SVPWM_Handle; +/** + * @} + */ + +/** + * @defgroup R1_SVPWM_API R1 SVPWM API + * @brief The SVPWM module's API declaration for R1(One Resistor) application. + * @{ + */ +void R1SVPWM_Init(R1SVPWM_Handle *r1svHandle, float voltPu, float samplePointShift, float sampleWindow); +void R1SVPWM_Clear(R1SVPWM_Handle *r1svHandle); +void R1SVPWM_Exec(R1SVPWM_Handle *r1svHandle, const AlbeAxis *uAlbe, UvwAxis *dutyUvwLeft, UvwAxis *dutyUvwRight); +void R1SVPWM_PhaseShift(R1SVPWM_CALC_Handle *r1SvCalc, float sampleWindow); +void R1CurrReconstruct(unsigned int sectorIndex, float currSocA, float currSocB, UvwAxis *curr); +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_MCS_SVPWM_H */ diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/modulation/mcs_svpwm.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/modulation/mcs_svpwm.c new file mode 100644 index 0000000000000000000000000000000000000000..71b595ecc030ba80d4eabe48b0882bc90ff976d0 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/modulation/mcs_svpwm.c @@ -0,0 +1,217 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_svpwm.c + * @author MCU Algorithm Team + * @brief This file provides function of Space-Vector Pulse-Width-Modulation(SVPWM) calculations. + */ + +#include "mcs_svpwm.h" +#include "mcs_math_const.h" +#include "mcs_assert.h" +#include "mcs_math.h" + +/* Macro definitions ---------------------------------------------------------*/ +/** + * @brief Initialzer of SVPWM handle. + * @param svHandle The SVPWM handle. + * @param voltPu The per-unit voltage value. + * @retval None. + */ +void SVPWM_Init(SVPWM_Handle *svHandle, float voltPu) +{ + MCS_ASSERT_PARAM(svHandle != NULL); + MCS_ASSERT_PARAM(voltPu > 0.0f); + svHandle->voltPu = voltPu; + svHandle->oneDivVoltPu = 1.0f / voltPu; +} + +/** + * @brief Calculate svpwm sector. + * @param svCalc The svpwm calc struct. + * @retval None. + */ +void SVPWM_SectorCalc(SVPWM_CALC_Handle *svCalc) +{ + MCS_ASSERT_PARAM(svCalc != NULL); + /* The initial sector is 0. */ + svCalc->sectorIndex = 0; + /* Three-level voltage calculation */ + svCalc->volt[SVPWM_VOLT_0] = svCalc->vBeta; + svCalc->volt[SVPWM_VOLT_1] = SQRT3_DIV_TWO * svCalc->vAlpha - 0.5f * svCalc->vBeta; + svCalc->volt[SVPWM_VOLT_2] = -SQRT3_DIV_TWO * svCalc->vAlpha - 0.5f * svCalc->vBeta; + + /* sector index calculate && calculate abs values (V) */ + if (svCalc->volt[SVPWM_VOLT_0] > 0.0f) { + svCalc->sectorIndex += SVPWM_SECTOR_ADD_1; + } else { + svCalc->volt[SVPWM_VOLT_0] = -svCalc->volt[SVPWM_VOLT_0]; + } + if (svCalc->volt[SVPWM_VOLT_1] > 0.0f) { + svCalc->sectorIndex += SVPWM_SECTOR_ADD_2; + } else { + svCalc->volt[SVPWM_VOLT_1] = -svCalc->volt[SVPWM_VOLT_1]; + } + if (svCalc->volt[SVPWM_VOLT_2] > 0.0f) { + svCalc->sectorIndex += SVPWM_SECTOR_ADD_4; + } else { + svCalc->volt[SVPWM_VOLT_2] = -svCalc->volt[SVPWM_VOLT_2]; + } +} + +/** + * @brief Calculate three comparison values: max, medium, and min.. + * @param svCalc The svpwm calc struct. + * @retval None. + */ +void SVPWM_CompareValCalc(SVPWM_CALC_Handle *svCalc) +{ + MCS_ASSERT_PARAM(svCalc != NULL); + /* Calculate the action time of the two vectors based on the sector. */ + switch (svCalc->sectorIndex) { + case SVPWM_ANGLE_0_TO_60_DEG: /* 0 ~ 60° Voltage vector sector */ + svCalc->t1 = svCalc->volt[SVPWM_VOLT_1]; + svCalc->t2 = svCalc->volt[SVPWM_VOLT_0]; + break; + case SVPWM_ANGLE_60_TO_120_DEG: /* 60 ~ 120° Voltage vector sector */ + svCalc->t1 = svCalc->volt[SVPWM_VOLT_1]; + svCalc->t2 = svCalc->volt[SVPWM_VOLT_2]; + break; + case SVPWM_ANGLE_120_TO_180_DEG: /* 120 ~ 180° Voltage vector sector */ + svCalc->t1 = svCalc->volt[SVPWM_VOLT_0]; + svCalc->t2 = svCalc->volt[SVPWM_VOLT_2]; + break; + case SVPWM_ANGLE_180_TO_240_DEG: /* 180 ~ 240° Voltage vector sector */ + svCalc->t1 = svCalc->volt[SVPWM_VOLT_0]; + svCalc->t2 = svCalc->volt[SVPWM_VOLT_1]; + break; + case SVPWM_ANGLE_240_TO_300_DEG: /* 240 ~ 300° Voltage vector sector */ + svCalc->t1 = svCalc->volt[SVPWM_VOLT_2]; + svCalc->t2 = svCalc->volt[SVPWM_VOLT_1]; + break; + case SVPWM_ANGLE_300_TO_360_DEG: /* 300 ~ 360° Voltage vector sector */ + svCalc->t1 = svCalc->volt[SVPWM_VOLT_2]; + svCalc->t2 = svCalc->volt[SVPWM_VOLT_0]; + break; + default: + break; + } + + /* The action time of two vectors is converted to three comparison values. */ + svCalc->comp[SVPWM_COMP_VAL_MIN] = (1.0f - svCalc->t1 - svCalc->t2) * 0.5f; + svCalc->comp[SVPWM_COMP_VAL_MID] = svCalc->comp[SVPWM_COMP_VAL_MIN] + svCalc->t1; + svCalc->comp[SVPWM_COMP_VAL_MAX] = svCalc->comp[SVPWM_COMP_VAL_MID] + svCalc->t2; +} + +/** + * @brief Three-phase duty cycle data index based on sector convert. + * @param svCalc The svpwm calc struct. + * @retval None. + */ +void SVPWM_IndexConvert(SVPWM_CALC_Handle *svCalc) +{ + MCS_ASSERT_PARAM(svCalc != NULL); + /* Three-phase duty cycle data index based on sector convert */ + switch (svCalc->sectorIndex) { + case SVPWM_ANGLE_0_TO_60_DEG: /* 0 ~ 60° Voltage vector sector */ + svCalc->indexU = SVPWM_COMP_VAL_MIN; + svCalc->indexV = SVPWM_COMP_VAL_MID; + svCalc->indexW = SVPWM_COMP_VAL_MAX; + break; + case SVPWM_ANGLE_60_TO_120_DEG: /* 60 ~ 120° Voltage vector sector */ + svCalc->indexU = SVPWM_COMP_VAL_MID; + svCalc->indexV = SVPWM_COMP_VAL_MIN; + svCalc->indexW = SVPWM_COMP_VAL_MAX; + break; + case SVPWM_ANGLE_120_TO_180_DEG: /* 120 ~ 180° Voltage vector sector */ + svCalc->indexU = SVPWM_COMP_VAL_MAX; + svCalc->indexV = SVPWM_COMP_VAL_MIN; + svCalc->indexW = SVPWM_COMP_VAL_MID; + break; + case SVPWM_ANGLE_180_TO_240_DEG: /* 180 ~ 240° Voltage vector sector */ + svCalc->indexU = SVPWM_COMP_VAL_MAX; + svCalc->indexV = SVPWM_COMP_VAL_MID; + svCalc->indexW = SVPWM_COMP_VAL_MIN; + break; + case SVPWM_ANGLE_240_TO_300_DEG: /* 240 ~ 300° Voltage vector sector */ + svCalc->indexU = SVPWM_COMP_VAL_MID; + svCalc->indexV = SVPWM_COMP_VAL_MAX; + svCalc->indexW = SVPWM_COMP_VAL_MIN; + break; + case SVPWM_ANGLE_300_TO_360_DEG: /* 300 ~ 360° Voltage vector sector */ + svCalc->indexU = SVPWM_COMP_VAL_MIN; + svCalc->indexV = SVPWM_COMP_VAL_MAX; + svCalc->indexW = SVPWM_COMP_VAL_MID; + break; + default: + break; + } +} + +/** + * @brief The duty cycles of PWM wave of three-phase upper switches are + * calculated in the two-phase stationary coordinate system (albe). + * @param svHandle The SVPWM struct handle. + * @param uAlbe Input voltage vector. + * @param dutyUvw Three-phase A compare value. + * @retval None. + */ +void SVPWM_Exec(const SVPWM_Handle *svHandle, const AlbeAxis *uAlbe, UvwAxis *dutyUvw) +{ + MCS_ASSERT_PARAM(svHandle != NULL); + MCS_ASSERT_PARAM(uAlbe != NULL); + MCS_ASSERT_PARAM(dutyUvw != NULL); + SVPWM_CALC_Handle svCalc; + + /* Amplitude limited */ + float voltMax = 1.0f / svHandle->oneDivVoltPu; + float amp = Sqrt(uAlbe->alpha * uAlbe->alpha + uAlbe->beta * uAlbe->beta); /* Voltage amplitude. */ + AlbeAxis uAlbeLimited; + float coeff; + if (amp < 0.001f) { + coeff = 1.0f; + } else { + coeff = voltMax / amp; /* Amplitude limit coefficient. */ + } + if (amp > voltMax) { + uAlbeLimited.alpha = uAlbe->alpha * coeff; + uAlbeLimited.beta = uAlbe->beta * coeff; + } else { + uAlbeLimited.alpha = uAlbe->alpha; + uAlbeLimited.beta = uAlbe->beta; + } + svCalc.vAlpha = uAlbeLimited.alpha * svHandle->oneDivVoltPu; + svCalc.vBeta = uAlbeLimited.beta * svHandle->oneDivVoltPu; + + /* Voltage vector sector calculation */ + SVPWM_SectorCalc(&svCalc); + /* Check whether the current sector is abnormal. */ + if (svCalc.sectorIndex < SVPWM_SECTOR_INDEX_MIN || svCalc.sectorIndex > SVPWM_SECTOR_INDEX_MAX) { + dutyUvw->u = 0.5f; + dutyUvw->v = 0.5f; + dutyUvw->w = 0.5f; + return; + } + /* Calculate three comparison values: max, medium, and min. */ + SVPWM_CompareValCalc(&svCalc); + /* Three-phase duty cycle data index based on sector convert */ + SVPWM_IndexConvert(&svCalc); + /* Output UVW three-phase duty cycle */ + dutyUvw->u = svCalc.comp[svCalc.indexU]; + dutyUvw->v = svCalc.comp[svCalc.indexV]; + dutyUvw->w = svCalc.comp[svCalc.indexW]; +} diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/modulation/mcs_svpwm.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/modulation/mcs_svpwm.h new file mode 100644 index 0000000000000000000000000000000000000000..fe636fa5faa08491fc2122f32e0b32e65a4e5657 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/modulation/mcs_svpwm.h @@ -0,0 +1,117 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_svpwm.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of Space-Vector Pulse-Width-Modulation(SVPWM) calculations. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_MCS_SVPWM_H +#define McuMagicTag_MCS_SVPWM_H + +/* Includes ------------------------------------------------------------------*/ +#include "mcs_typedef.h" + +/** Voltage vector sector */ +#define SVPWM_ANGLE_0_TO_60_DEG 3 +#define SVPWM_ANGLE_60_TO_120_DEG 1 +#define SVPWM_ANGLE_120_TO_180_DEG 5 +#define SVPWM_ANGLE_180_TO_240_DEG 4 +#define SVPWM_ANGLE_240_TO_300_DEG 6 +#define SVPWM_ANGLE_300_TO_360_DEG 2 + +/** The U-V-W phase compare value's index of APT timers. */ +#define SVPWM_COMP_VAL_MAX 2 +#define SVPWM_COMP_VAL_MID 1 +#define SVPWM_COMP_VAL_MIN 0 +#define SVPWM_COMP_VAL_TOTAL 3 + +/** The three voltage level to compare, for sector index decision. */ +#define SVPWM_VOLT_0 0 +#define SVPWM_VOLT_1 1 +#define SVPWM_VOLT_2 2 +#define SVPWM_VOLT_TOTAL 3 + +/** Sector index calculate: N = A + 2B + 4C */ +#define SVPWM_SECTOR_ADD_1 1 +#define SVPWM_SECTOR_ADD_2 2 +#define SVPWM_SECTOR_ADD_4 4 + +#define SVPWM_SECTOR_INDEX_MIN 1 +#define SVPWM_SECTOR_INDEX_MAX 6 + +/** + * @defgroup SVPWM_MODULE SVPWM MODULE + * @brief The Space-Vector Pulse-Width-Modulation(SVPWM) module. + * @{ + */ + +/** + * @defgroup SVPWM_STRUCT SVPWM STRUCT + * @brief The SVPWM module's data struct definition. + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ +/** + * @brief SVPWM struct members and parameters. + */ +typedef struct { + float voltPu; /**< Voltage per unit value. */ + float oneDivVoltPu; /**< Reciprocal of voltage unit value. */ +} SVPWM_Handle; + +/** + * @brief Structure of temporary variables for SVPWM calculation. + */ +typedef struct { + float vAlpha; /**< Voltage vector. */ + float vBeta; /**< Voltage vector. */ + float t1; /**< T1 are the action times of the sequential action vectors. */ + float t2; /**< T2 are the action times of the sequential action vectors. */ + unsigned short indexU; /**< U-phase duty cycle conversion index */ + unsigned short indexV; /**< V-phase duty cycle conversion index */ + unsigned short indexW; /**< W-phase duty cycle conversion index */ + unsigned int sectorIndex; /**< Sector index */ + float volt[SVPWM_VOLT_TOTAL]; /**< temporary voltage to calculate sector index */ + float comp[SVPWM_COMP_VAL_TOTAL]; /**< Duty cycle corresponding to the comparison value */ +} SVPWM_CALC_Handle; + +/** + * @} + */ + +/** + * @defgroup SVPWM_API SVPWM API + * @brief The SVPWM module's API declaration. + * @{ + */ +void SVPWM_Init(SVPWM_Handle *svHandle, float voltPu); +void SVPWM_SectorCalc(SVPWM_CALC_Handle *svCalc); +void SVPWM_CompareValCalc(SVPWM_CALC_Handle *svCalc); +void SVPWM_IndexConvert(SVPWM_CALC_Handle *svCalc); +void SVPWM_Exec(const SVPWM_Handle *svHandle, const AlbeAxis *uAlbe, UvwAxis *dutyUvw); +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_MCS_SVPWM_H */ diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/observer/mcs_fosmo.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/observer/mcs_fosmo.c new file mode 100644 index 0000000000000000000000000000000000000000..690bbb9514d55c72407a761daa6764d01d9d7f46 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/observer/mcs_fosmo.c @@ -0,0 +1,199 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_fosmo.c + * @author MCU Algorithm Team + * @brief This file provides functions of position sliding mode observer (SMO) module. + */ + +#include "mcs_fosmo.h" +#include "mcs_math_const.h" +#include "mcs_math.h" +#include "mcs_assert.h" + + +void FOSMO_Init(FOSMO_Handle *fosmo, const FOSMO_Param foSmoParam, const MOTOR_Param mtrParam, float ts) +{ + MCS_ASSERT_PARAM(fosmo != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + /* time sample, unit: s */ + fosmo->ts = ts; + /* filter coefficient */ + fosmo->a1 = 1.0f - (fosmo->ts * mtrParam.mtrRs / mtrParam.mtrLd); + fosmo->a2 = fosmo->ts / mtrParam.mtrLd; + + fosmo->kSmo = foSmoParam.gain; + fosmo->lambda = foSmoParam.lambda; /* SMO coefficient of cut-off frequency = lambda * we, unit: rad/2. */ + /* smo angle filcompAngle */ + fosmo->filCompAngle = Atan2(1.0f, 1.0f / fosmo->lambda); + fosmo->pllBdw = foSmoParam.pllBdw; + fosmo->fcLpf = foSmoParam.fcLpf; + + FOSMO_Clear(fosmo); + + fosmo->emfLpfMinFreq = foSmoParam.fcEmf; /* The minimum cutoff frequency of the back EMF filter is 2.0. */ + + PLL_Init(&fosmo->pll, fosmo->ts, fosmo->pllBdw); // bdw + + /* low pass filter cutoff freqency for speed estimation is 40Hz */ + FOLPF_Init(&fosmo->spdFilter, fosmo->ts, fosmo->fcLpf); +} + +/** + * @brief Set parameters for fosmo. + * @param fosmo The SMO handle. + * @param gain The smo gain. + * @param pllBdw The PLL bandwidth (Hz). + * @param fc The first-order low pass filter cut-off frequency. + * @retval None. + */ +void FOSMO_ParamUpdate(FOSMO_Handle *fosmo, float gain, float pllBdw, float fc) +{ + MCS_ASSERT_PARAM(fosmo != NULL); + MCS_ASSERT_PARAM(pllBdw > 0.0f); + MCS_ASSERT_PARAM(fc > 0.0f); + + fosmo->kSmo = gain; + fosmo->fcLpf = fc; + fosmo->pllBdw = pllBdw; + + /* Set PI parameters with given bandwidth */ + float we = DOUBLE_PI * pllBdw; + fosmo->pll.pi.kp = 2.0f * we; + fosmo->pll.pi.ki = we * we; + + /* Set LPF parameters with given fc */ + fosmo->spdFilter.fc = fc; + float wcTs = DOUBLE_PI * fc * fosmo->spdFilter.ts; + fosmo->spdFilter.a1 = 1.0f / (1.0f + wcTs); /* wcTs > 0 */ + fosmo->spdFilter.b1 = 1.0f - fosmo->spdFilter.a1; +} + + +/** + * @brief Clear historical values of SMO handle. + * @param fosmo SMO struct handle. + * @retval None. + */ +void FOSMO_Clear(FOSMO_Handle *fosmo) +{ + MCS_ASSERT_PARAM(fosmo != NULL); + /* Clear historical values of SMO handle */ + fosmo->ialbeEst.alpha = 0.0f; + fosmo->ialbeEst.beta = 0.0f; + fosmo->ialbeEstLast.alpha = 0.0f; + fosmo->ialbeEstLast.beta = 0.0f; + fosmo->emfEstUnFil.alpha = 0.0f; + fosmo->emfEstUnFil.beta = 0.0f; + fosmo->emfEstFil.alpha = 0.0f; + fosmo->emfEstFil.beta = 0.0f; + /* Clear historical values of PLL controller */ + PLL_Clear(&fosmo->pll); + /* Clear historical values of first-order fosmo speed filter */ + FOLPF_Clear(&fosmo->spdFilter); +} + +/** + * @brief Calculation method of first-order SMO. + * @param fosmo SMO struct handle. + * @param ialbeFbk Feedback currents in the alpha-beta coordinate (A). + * @param valbeRef FOC output voltages in alpha-beta coordinate (V). + * @param refHz The reference frequency (Hz). + * @retval None. + */ +void FOSMO_Exec(FOSMO_Handle *fosmo, const AlbeAxis *ialbeFbk, const AlbeAxis *valbeRef, float refHz) +{ + MCS_ASSERT_PARAM(fosmo != NULL); + MCS_ASSERT_PARAM(ialbeFbk != NULL); + MCS_ASSERT_PARAM(valbeRef != NULL); + float err; + float wcTs; + float fcAbs = Abs(refHz); + float filCompAngle; /* Compensation angle (rad) */ + float currAlpha = fosmo->ialbeEstLast.alpha; + float currBeta = fosmo->ialbeEstLast.beta; + float emfUnAlpha = fosmo->emfEstUnFil.alpha; + float emfUnBeta = fosmo->emfEstUnFil.beta; + /* Alpha beta current observation value */ + fosmo->ialbeEst.alpha = + (fosmo->a1 * currAlpha) + (fosmo->a2 * (valbeRef->alpha - emfUnAlpha)); + fosmo->ialbeEst.beta = + (fosmo->a1 * currBeta) + (fosmo->a2 * (valbeRef->beta - emfUnBeta)); + + fosmo->ialbeEstLast.alpha = fosmo->ialbeEst.alpha; + fosmo->ialbeEstLast.beta = fosmo->ialbeEst.beta; + + /* Estmated back EMF by sign function. */ + err = fosmo->ialbeEst.alpha - ialbeFbk->alpha; + fosmo->emfEstUnFil.alpha = fosmo->kSmo * ((err > 0.0f) ? 1.0f : -1.0f); + err = fosmo->ialbeEst.beta - ialbeFbk->beta; + fosmo->emfEstUnFil.beta = fosmo->kSmo * ((err > 0.0f) ? 1.0f : -1.0f); + + /* Estmated back EMF is filtered by first-order LPF. */ + if (fcAbs <= fosmo->emfLpfMinFreq) { + wcTs = fosmo->emfLpfMinFreq * DOUBLE_PI * fosmo->ts * fosmo->lambda; + } else { + wcTs = fcAbs * DOUBLE_PI * fosmo->ts * fosmo->lambda; + } + fosmo->emfEstFil.alpha = (fosmo->emfEstFil.alpha + wcTs * fosmo->emfEstUnFil.alpha) / (wcTs + 1.0f); + fosmo->emfEstFil.beta = (fosmo->emfEstFil.beta + wcTs * fosmo->emfEstUnFil.beta) / (wcTs + 1.0f); + + /* Get phase angle and frequency from BEMF by PLL. */ + PLL_Exec(&fosmo->pll, -fosmo->emfEstFil.alpha, fosmo->emfEstFil.beta); + + /* Compensation phase lag caused by the LPF. */ + filCompAngle = (refHz > 0.0f) ? (fosmo->filCompAngle) : AngleSub(ONE_PI, fosmo->filCompAngle); + fosmo->elecAngle = Mod(fosmo->pll.angle + filCompAngle, DOUBLE_PI); + if (fosmo->elecAngle > ONE_PI) { + fosmo->elecAngle -= DOUBLE_PI; + } + if (fosmo->elecAngle < -ONE_PI) { + fosmo->elecAngle += DOUBLE_PI; + } + /* Estmated speed is filtered by first-order LPF. */ + fosmo->spdEst = FOLPF_Exec(&fosmo->spdFilter, fosmo->pll.freq); +} + +/** + * @brief Set ts for first-order SMO. + * @param fosmo SMO struct handle. + * @param ts Control period (s). + * @retval None. + */ +void FOSMO_SetTs(FOSMO_Handle *fosmo, float ts) +{ + MCS_ASSERT_PARAM(fosmo != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + fosmo->ts = ts; + /* Set PLL ts and filter ts. */ + PLL_SetTs(&fosmo->pll, ts); + FOLPF_SetTs(&fosmo->spdFilter, ts); +} + +/** + * @brief Set coefficient of cut-off frequency(lambda * we rad/2) for first-order SMO. + * @param fosmo SMO struct handle. + * @param lambda SMO filter coefficient. + * @retval None. + */ +void FOSMO_SetLambda(FOSMO_Handle *fosmo, float lambda) +{ + MCS_ASSERT_PARAM(fosmo != NULL); + MCS_ASSERT_PARAM(lambda > 0.0f); + fosmo->lambda = lambda; + fosmo->filCompAngle = Atan2(1.0f, 1.0f / fosmo->lambda); +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/observer/mcs_fosmo.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/observer/mcs_fosmo.h new file mode 100644 index 0000000000000000000000000000000000000000..350842e232ae07b4e6bc40d94bfd2d06151e7768 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/observer/mcs_fosmo.h @@ -0,0 +1,106 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_fosmo.h + * @author MCU Algorithm Team + * @brief Sliding-mode observer (SMO) for motor position acquisition. + * This file provides position SMO and Phase-locked loop (PLL) declaration for motor control. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_FOSMO_H +#define McuMagicTag_MCS_FOSMO_H + +/* Includes ------------------------------------------------------------------------------------ */ +#include "mcs_mtr_param.h" +#include "mcs_typedef.h" +#include "mcs_pll.h" +#include "mcs_filter.h" + +/** + * @defgroup FOSMO_MODULE FOSMO MODULE + * @brief The First Order Sliding Mode Observer module. + * @{ + */ + +/** + * @defgroup FOSMO_STRUCT FOSMO STRUCT + * @brief The First Order Sliding Mode Observer's data struct definition. + * @{ + */ +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief Position SMO struct members and parameters. + */ +typedef struct { + float ts; /**< SMO control period (s). */ + float a1; /**< Coefficient of differential equation. */ + float a2; /**< Coefficient of differential equation. */ + float kSmo; /**< SMO gain. */ + float lambda; /**< SMO coefficient of cut-off frequency, its value = lambda * we. */ + float emfLpfMinFreq; /**< The minimum cut-off frequency of back-EMF filter. */ + float pllBdw; /**< The PLL bandwidth. */ + float fcLpf; /**< The cut-off frequency of First-order LPF for speed (Hz). */ + float filCompAngle; /**< Compensation angle (atan(1/lambda)) for the back-EMF filter. */ + float elecAngle; /**< SMO estimated electronic angle (rad). */ + float spdEst; /**< SMO estimated electronic speed (Hz). */ + AlbeAxis emfEstUnFil; /**< Estimated back-EMF in the alpha-beta coordinate by differential equation. */ + AlbeAxis ialbeEst; /**< SMO estimated currents in the alpha-beta coordinate. */ + AlbeAxis ialbeEstLast; /**< SMO history values of estimated currents in the alpha-beta coordinate. */ + AlbeAxis emfEstFil; /**< SMO estimated back-EMF in the alpha-beta coordinate. */ + PLL_Handle pll; /**< PLL handle. */ + FOFLT_Handle spdFilter; /**< First-order LPF for speed. */ +} FOSMO_Handle; + +/** + * @} + */ +typedef struct { + float gain; + float lambda; + float fcEmf; + float pllBdw; + float fcLpf; +} FOSMO_Param; + + +/** + * @defgroup FOSMO_API FOSMO API + * @brief The First Order Sliding Mode Observer's API declaration. + * @{ + */ + +void FOSMO_Init(FOSMO_Handle *fosmo, const FOSMO_Param foSmoParam, const MOTOR_Param mtrParam, float ts); + +void FOSMO_Exec(FOSMO_Handle *fosmo, const AlbeAxis *ialbeFbk, const AlbeAxis *valbeRef, float refHz); + +void FOSMO_ParamUpdate(FOSMO_Handle *fosmo, float gain, float pllBdw, float fc); + +void FOSMO_Clear(FOSMO_Handle *fosmo); + +void FOSMO_SetTs(FOSMO_Handle *fosmo, float ts); + +void FOSMO_SetLambda(FOSMO_Handle *fosmo, float lambda); +/** + * @} + */ + +/** + * @} + */ + +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/pfc/pfc_curr_ctrl.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/pfc/pfc_curr_ctrl.c new file mode 100644 index 0000000000000000000000000000000000000000..3eda2abd12bf64aa1f57a2af1fc57459cfb4d97c --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/pfc/pfc_curr_ctrl.c @@ -0,0 +1,50 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pfc_curr_ctrl.c + * @author MCU Algorithm Team + * @brief This file provides function of power factor correction(PFC) current control + */ +#include "pfc_curr_ctrl.h" +#include "mcs_assert.h" + + +/** + * @brief Clear historical values of power factor correction(PFC) current controller. + * @param currCtrl PFC current control structure + * @retval None. + */ +void PFC_CurrCtrlClear(PFC_CURRCTRL_Handle *currCtrl) +{ + MCS_ASSERT_PARAM(currCtrl != NULL); + currCtrl->currPiCtrl.differ = 0.0f; + currCtrl->currPiCtrl.integral = 0.0f; +} + +/** + * @brief Simplified power factor correction(PFC) current controller PI calculation. + * @param currCtrl PFC current control structure + * @retval None. + */ +void PFC_CurrCtrlExec(PFC_CURRCTRL_Handle *currCtrl) +{ + MCS_ASSERT_PARAM(currCtrl != NULL); + /* Calculate the current error of power factor correction(PFC). */ + currCtrl->currPiCtrl.error = currCtrl->currRef - currCtrl->unitCurrFdbk; + /* Calculation the output pwm duty of power factor correction(PFC) current. */ + currCtrl->pwmDuty = PI_Exec(&currCtrl->currPiCtrl); +} diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/pfc/pfc_curr_ctrl.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/pfc/pfc_curr_ctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..d7ed3d9fdea33b9eb039caf628e1ffe4fc06aca0 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/pfc/pfc_curr_ctrl.h @@ -0,0 +1,79 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pfc_curr_ctrl.h + * @author MCU Algorithm Team + * @brief Current loop control. This file provides function of power factor correction(PFC) current control + */ +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_PFC_CURR_CTRL_H +#define McuMagicTag_PFC_CURR_CTRL_H + +/* Includes ------------------------------------------------------------------------------------ */ +#include "mcs_pid_ctrl.h" + +/** + * @defgroup PFC_CURRENT_CONTROLLER PFC_CURRENT CONTROLLER MODULE + * @brief The current controller function. + * @{ + */ + +/** + * @defgroup PFC_CURRENT_CONTROLLER_STRUCT PFC_CURRENT CONTROLLER STRUCT + * @brief The current controller's data structure definition. + * @{ + */ + +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief current Controller Struct members and parameters. + */ +typedef struct { + float currRef; /* < current loop control reference current(A) */ + float currFdbk; /* < current loop control feedback current(A) */ + float unitCurrFdbk; /* < current loop control feedback unitary current */ + float maxCurrFdbk; /* < current loop control max feedback current(A) */ + float startCurrFdbk; /* < current loop control start feedback current(A) */ + float stopCurrFdbk; /* < current loop control stop feedback current(A) */ + float pwmDuty; /* < current loop control pulse width modulation(PWM) duty */ + float pwmOut; /* < current loop control PWM final output (output = cmpst + duty) */ + float rectVoltFdbk; /* < current loop control rectified feedback voltage(V) */ + float unitRectVoltFdbk; /* < current loop control rectified feedback unitary voltage */ + float compensation; + PID_Handle currPiCtrl; /* < current loop controller define */ +} PFC_CURRCTRL_Handle; +/** + * @} + */ + +/** + * @defgroup PFC_CURRENT_CONTROLLER_API PFC_CURRENT CONTROLLER API + * @brief The current controller's API declaration. + * @{ + */ + +void PFC_CurrCtrlClear(PFC_CURRCTRL_Handle *currCtrl); + +void PFC_CurrCtrlExec(PFC_CURRCTRL_Handle *currCtrl); +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_PFC_CURR_CTRL_H */ diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/pfc/pfc_volt_ctrl.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/pfc/pfc_volt_ctrl.c new file mode 100644 index 0000000000000000000000000000000000000000..1fdf5dfd345b3285d630936d4966f8fb7a3926bf --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/pfc/pfc_volt_ctrl.c @@ -0,0 +1,51 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pfc_volt_ctrl.c + * @author MCU Algorithm Team + * @brief This file provides function of power factor correction(PFC) voltage control + */ +#include "pfc_volt_ctrl.h" +#include "mcs_math.h" +#include "mcs_assert.h" + + +/** + * @brief Clear historical values of power factor correction(PFC) voltage controller. + * @param voltCtrl PFC voltage control structure + * @retval None. + */ +void PFC_VoltCtrlClear(PFC_VOLTCTRL_Handle *voltCtrl) +{ + MCS_ASSERT_PARAM(voltCtrl != NULL); + voltCtrl->voltPiCtrl.differ = 0.0f; + voltCtrl->voltPiCtrl.integral = 0.0f; +} + +/** + * @brief Simplified power factor correction(PFC) voltage controller PI calculation. + * @param voltCtrl PFC voltage control structure + * @retval None. + */ +void PFC_VoltCtrlExec(PFC_VOLTCTRL_Handle *voltCtrl) +{ + MCS_ASSERT_PARAM(voltCtrl != NULL); + /* Calculate the voltage error of power factor correction(PFC). */ + voltCtrl->voltPiCtrl.error = voltCtrl->uniVoltRef - voltCtrl->unitVoltFdbk; + /* Calculation the voltage loop control output of power factor correction(PFC). */ + voltCtrl->voltOut = PI_Exec(&voltCtrl->voltPiCtrl); +} diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/pfc/pfc_volt_ctrl.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/pfc/pfc_volt_ctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..b1f6e94d71b7f82675b413fd446f48cb8165a315 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/pfc/pfc_volt_ctrl.h @@ -0,0 +1,72 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pfc_volt_ctrl.h + * @author MCU Algorithm Team + * @brief Voltage loop control. This file provides function of power factor correction(PFC) voltage control + */ +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_PFC_VOLT_CTRL_H +#define McuMagicTag_PFC_VOLT_CTRL_H + +/* Includes ------------------------------------------------------------------------------------ */ +#include "mcs_pid_ctrl.h" + +/** + * @defgroup VOLTAGE_CONTROLLER VOLTAGE CONTROLLER MODULE + * @brief The voltage controller function. + * @{ + */ + +/** + * @defgroup VOLTAGE_CONTROLLER_STRUCT VOLTAGE CONTROLLER STRUCT + * @brief The voltage controller's data structure definition. + * @{ + */ + +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief Voltage controller struct. + */ +typedef struct { + float uniVoltRef; /* < voltage loop control unitary reference voltage(V) */ + float voltFdbk; /* < voltage loop control feedback voltage(V) */ + float unitVoltFdbk; /* < voltage loop control feedback unitary voltage */ + float startVolt; /* < voltage loop control start voltage(V) */ + float voltOut; /* < voltage loop control output */ + PID_Handle voltPiCtrl; /* < voltage loop controller define */ +} PFC_VOLTCTRL_Handle; +/** + * @} + */ + +/** + * @defgroup VOLTAGE_CONTROLLER_API VOLTAGE CONTROLLER API + * @brief The voltage controller's API declaration. + * @{ + */ +void PFC_VoltCtrlClear(PFC_VOLTCTRL_Handle *voltCtrl); + +void PFC_VoltCtrlExec(PFC_VOLTCTRL_Handle *voltCtrl); +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_PFC_VOLT_CTRL_H */ diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/pid_controller/mcs_pid_ctrl.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/pid_controller/mcs_pid_ctrl.c new file mode 100644 index 0000000000000000000000000000000000000000..f780fd62e3b0de8303393ed103f3e07ccbcfbb21 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/pid_controller/mcs_pid_ctrl.c @@ -0,0 +1,199 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_pid_ctrl.c + * @author MCU Algorithm Team + * @brief This file provides functions of general PID controller + */ + +#include "mcs_pid_ctrl.h" +#include "mcs_math.h" +#include "mcs_assert.h" + +/** + * @brief Reset all member variables of PID controller to zero. + * @param piHandle PID controller struct handle. + * @retval None. + */ +void PID_Reset(PID_Handle *pidHandle) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + /* Reset the PID parameter. */ + pidHandle->kp = 0.0f; + pidHandle->ki = 0.0f; + pidHandle->kd = 0.0f; + pidHandle->ns = 0.0f; + pidHandle->ka = 0.0f; + pidHandle->ts = 0.0f; + /* Reset the Limiting Value. */ + pidHandle->upperLimit = 0.0f; + pidHandle->lowerLimit = 0.0f; + + PID_Clear(pidHandle); +} + +/** + * @brief Clear historical values of PID controller. + * @param pidHandle PID controller struct handle. + * @retval None. + */ +void PID_Clear(PID_Handle *pidHandle) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + /* Clear historical values of PID controller. */ + pidHandle->differ = 0.0f; + pidHandle->integral = 0.0f; + pidHandle->saturation = 0.0f; + pidHandle->feedforward = 0.0f; + pidHandle->error = 0.0f; + pidHandle->errorLast = 0.0f; +} + +/** + * @brief Execute simplified PI controller calculation, static clamping, no feedforward. + * @param pidHandle PI controller struct handle. + * @retval PI control output. + */ +float PI_Exec(PID_Handle *pidHandle) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + /* Proportional Item */ + float p = pidHandle->kp * pidHandle->error; + + /* Integral Item */ + float i = pidHandle->ki * pidHandle->ts * pidHandle->error + pidHandle->integral; + i = Clamp(i, pidHandle->upperLimit, pidHandle->lowerLimit); + pidHandle->integral = i; + + /* static clamping and output calculaiton */ + float val = p + i + pidHandle->feedforward; + float out = Clamp(val, pidHandle->upperLimit, pidHandle->lowerLimit); + + return out; +} + +/** + * @brief Execute PID controller calculation. dynamic clamping, feedforward compensataion + * @param pidHandle PID controller struct handle. + * @retval PID control output. + */ +float PID_Exec(PID_Handle *pidHandle) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + /* Proportional Item */ + float error = pidHandle->error; + float errorLast = pidHandle->errorLast; + float ts = pidHandle->ts; + + float p = pidHandle->kp * error; + + /* Integral Item */ + float i = pidHandle->ki * ts * (error - pidHandle->ka * pidHandle->saturation) + pidHandle->integral; + i = Clamp(i, Max(0.0f, pidHandle->upperLimit), Min(0.0f, pidHandle->lowerLimit)); + pidHandle->integral = i; + + /* Differential Item */ + float kd = pidHandle->kd; + float ns = pidHandle->ns; + float d = 1.0f / (1.0f + ts * ns) * (kd * ns * error - kd * ns * errorLast + pidHandle->differ); + + pidHandle->errorLast = pidHandle->error; + pidHandle->differ = d; + + /* Output value update and saturation value calculation */ + float val = p + i + d + pidHandle->feedforward; + float out = Clamp(val, pidHandle->upperLimit, pidHandle->lowerLimit); + pidHandle->saturation = val - out; + + return out; +} + +/** + * @brief Set the proportional parameter kp of PID controller. + * @param pidHandle PID controller struct handle. + * @param kp The proportional parameter. + * @retval None. + */ +void PID_SetKp(PID_Handle *pidHandle, float kp) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + pidHandle->kp = kp; +} + +/** + * @brief Set the integral parameter ki of PID controller. + * @param pidHandle PID controller struct handle. + * @param ki The integral parameter. + * @retval None. + */ +void PID_SetKi(PID_Handle *pidHandle, float ki) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + pidHandle->ki = ki; +} + +/** + * @brief Set the derivative parameter kd of PID controller. + * @param pidHandle PID controller struct handle. + * @param kd The derivative parameter. + * @retval None. + */ +void PID_SetKd(PID_Handle *pidHandle, float kd) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + pidHandle->kd = kd; +} + +/** + * @brief Set the filter parameter of the differential item parameter ns of PID controller. + * @param pidHandle PID controller struct handle. + * @param ns Filter parameter of the differential item. + * @retval None. + */ +void PID_SetNs(PID_Handle *pidHandle, float ns) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + MCS_ASSERT_PARAM(ns >= 0.0f); + pidHandle->ns = ns; +} + +/** + * @brief Set the ts of PID controller. + * @param pidHandle PID controller struct handle. + * @param ts Control period (s). + * @retval None. + */ +void PID_SetTs(PID_Handle *pidHandle, float ts) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + MCS_ASSERT_PARAM(ts >= 0.0f); + pidHandle->ts = ts; +} + +/** + * @brief Set the derivative parameter upper and lower limit of PID controller. + * @param pidHandle PID controller struct handle. + * @param kd The derivative parameter. + * @retval None. + */ +void PID_SetLimit(PID_Handle *pidHandle, float limit) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + MCS_ASSERT_PARAM(limit >= 0.0f); + pidHandle->upperLimit = limit; + pidHandle->lowerLimit = -limit; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/pid_controller/mcs_pid_ctrl.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/pid_controller/mcs_pid_ctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..651850972cce1aff9a836b0a79fd3bd87f1755e5 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/pid_controller/mcs_pid_ctrl.h @@ -0,0 +1,105 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_pid_ctrl.h + * @author MCU Algorithm Team + * @brief General PI controller. + * This file provides functions declaration of the PI controller module. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_PID_CTRL_H +#define McuMagicTag_MCS_PID_CTRL_H + +/** + * @defgroup PID PID + * @brief The PID module. + * @{ + */ + +/** + * @defgroup PID_STRUCT PID STRUCT + * @brief The PID control structure definition. + * @{ + */ +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief General PID Controller struct members and parameters. + */ +typedef struct { + float error; /**< Error feedback. */ + float errorLast; /**< Error feedback history values. */ + float feedforward; /**< Feedforward item. */ + float integral; /**< Integral item. */ + float saturation; /**< Saturation value of the integral item. */ + float differ; /**< Differential item. */ + float kp; /**< Gained of the proportional item. */ + float ki; /**< Gained of the integral item, not multiplied by control period. */ + float kd; /**< Gained of the differential item. */ + float ns; /**< Filter parameter of the differential item. */ + float ka; /**< Gained of the saturation item. */ + float ts; /**< Control period (s) */ + float upperLimit; /**< The upper limit value of the pid comp output. */ + float lowerLimit; /**< The lower limit value of the pid output. */ +} PID_Handle; + +typedef struct { + float kp; + float ki; + float upperLim; + float lowerLim; +} PI_Param; + +typedef struct { + float kp; + float ki; + float kd; + float ns; /**< Filter parameter of the differential item. */ + float ka; /**< Gained of the saturation item. */ + float saturation; + float upperLim; + float lowerLim; +} PID_Param; +/** + * @} + */ + +/** + * @defgroup PID_API PID API + * @brief The PID control API definitions. + * @{ + */ +void PID_Reset(PID_Handle *pidHandle); +void PID_Clear(PID_Handle *pidHandle); +float PI_Exec(PID_Handle *pidHandle); +float PID_Exec(PID_Handle *pidHandle); + +void PID_SetKp(PID_Handle *pidHandle, float kp); +void PID_SetKi(PID_Handle *pidHandle, float ki); +void PID_SetKd(PID_Handle *pidHandle, float kd); +void PID_SetNs(PID_Handle *pidHandle, float ns); +void PID_SetTs(PID_Handle *pidHandle, float ts); +void PID_SetLimit(PID_Handle *pidHandle, float limit); +/** + * @} + */ + +/** + * @} + */ + +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/power/mcs_power_mgmt.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/power/mcs_power_mgmt.c new file mode 100644 index 0000000000000000000000000000000000000000..a15b3f660aadc85506a27d8e76f9f16732c227ad --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/power/mcs_power_mgmt.c @@ -0,0 +1,71 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_power_mgmt.c + * @author MCU Algorithm Team + * @brief This file provides functions of motor average power management. + */ + + +#include "mcs_power_mgmt.h" +#include "mcs_math.h" +#include "mcs_assert.h" + +/** + * @brief Init motor power management. + * @param avgPower Pointer of motor power handle. + * @param vdqRef Pointer of vdqRef handle. + * @param idqFbk Pointer of idqFbk handle. + * @retval None. + */ +void MotorPowerInit(POWER_Handle *avgPower, DqAxis *vdqRef, DqAxis *idqFbk) +{ + MCS_ASSERT_PARAM(avgPower != NULL); + MCS_ASSERT_PARAM(vdqRef != NULL); + MCS_ASSERT_PARAM(idqFbk != NULL); + /* Initialization. */ + avgPower->avgPower = 0.0f; + /* Initialization. */ + avgPower->vdqRef = vdqRef; + avgPower->idqFbk = idqFbk; +} + +/** + * @brief Power result value. + * @param avgPower Pointer of motor power handle. + * @retval Motor power value (w). + */ +float MotorPowerCalc(POWER_Handle *avgPower) +{ + MCS_ASSERT_PARAM(avgPower != NULL); + /* Calculate average power. */ + float activePower = 1.5f * (avgPower->idqFbk->d * avgPower->vdqRef->d + avgPower->idqFbk->q * avgPower->vdqRef->q); + avgPower->avgPower = activePower; + return activePower; +} + +/** + * @brief Clear motor power history value. + * @param avgPower Pointer of motor power handle. + * @retval None. + */ +void MotorPowerClear(POWER_Handle *avgPower) +{ + MCS_ASSERT_PARAM(avgPower != NULL); + /* Clear history value. */ + avgPower->avgPower = 0.0f; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/power/mcs_power_mgmt.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/power/mcs_power_mgmt.h new file mode 100644 index 0000000000000000000000000000000000000000..1133c06b2ac14f97ba7f9dc7f7790a957eb3b034 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/power/mcs_power_mgmt.h @@ -0,0 +1,44 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_power_mgmt.h + * @author MCU Algorithm Team + * @brief This file provides functions of motor average power management. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_POWER_MGMT_H +#define McuMagicTag_MCS_POWER_MGMT_H + +#include "mcs_typedef.h" + +/* Typedef definitions ------------------------------------------------------------------------- */ + +typedef struct { + float avgPower; /**< Average power. */ + DqAxis *idqFbk; /**< Current value of d, q axis. */ + DqAxis *vdqRef; /**< Voltage value of d, q axis. */ +} POWER_Handle; + + +void MotorPowerInit(POWER_Handle *avgPower, DqAxis *vdqRef, DqAxis *idqFbk); + +float MotorPowerCalc(POWER_Handle *avgPower); + +void MotorPowerClear(POWER_Handle *avgPower); + +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/protection/mcs_openphs_det.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/protection/mcs_openphs_det.c new file mode 100644 index 0000000000000000000000000000000000000000..2c195ebac247f2aac57f22979c026b49c6802184 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/protection/mcs_openphs_det.c @@ -0,0 +1,87 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_openphs_det.c + * @author MCU Algorithm Team + * @brief This file contains self-check open phase fault detection function data struct and api declaration. + */ + + +#include "mcs_openphs_det.h" +#include "mcs_assert.h" + + +/** + * @brief Open phase detection initialization. + * @param opp Open phase detection handle. + * @param minOpenPhsCurr Minimum current for open-phase detection (A). + * @retval None. + */ +void OPD_Init(OPD_Handle *opd, float minOpenPhsCurr) +{ + MCS_ASSERT_PARAM(opd != NULL); + MCS_ASSERT_PARAM(minOpenPhsCurr > 0.0f); + /* Minimum current for open-phase detection (A). */ + opd->minOpenPhsCurr = minOpenPhsCurr; + /* No phase open. */ + opd->isOpenPhsU = 0; + opd->isOpenPhsV = 0; + opd->isOpenPhsW = 0; +} + + +/** + * @brief Open phase detection execution. + * @param opd Open phase detection handle. + * @param iuvw Phase current feedback values (A). + * @retval Whether the motor is open phase, ture: open phase, 0: no open phase. + */ +bool OPD_Exec(OPD_Handle *opd, const float *iuvw) +{ + MCS_ASSERT_PARAM(opd != NULL); + MCS_ASSERT_PARAM(iuvw != NULL); + float minCurr = opd->minOpenPhsCurr; + /* Open phase detection for phase U */ + if (iuvw[OPD_V_U] <= minCurr && iuvw[OPD_W_U] <= minCurr) { /* 4th step curr */ + opd->isOpenPhsU = true; + } + /* Open phase detection for phase V */ + if (iuvw[OPD_U_V] <= minCurr && iuvw[OPD_W_V] <= minCurr) { /* 2th step curr */ + opd->isOpenPhsV = true; + } + + /* Open phase detection for phase W */ + if (iuvw[OPD_V_W] <= minCurr && iuvw[OPD_U_W] <= minCurr) { /* 2th ,4th step curr */ + opd->isOpenPhsW = true; + } + + return (opd->isOpenPhsU || opd->isOpenPhsV || opd->isOpenPhsW); +} + + +/** + * @brief Clear Open phase history value. + * @param opd Open phase detection handle. + * @retval None. + */ +void OPD_Clear(OPD_Handle *opd) +{ + MCS_ASSERT_PARAM(opd != NULL); + opd->isOpenPhsU = 0; + opd->isOpenPhsV = 0; + opd->isOpenPhsW = 0; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/protection/mcs_openphs_det.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/protection/mcs_openphs_det.h new file mode 100644 index 0000000000000000000000000000000000000000..771953d8658c923029c5175b3eb1e0d69a0bd745 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/protection/mcs_openphs_det.h @@ -0,0 +1,51 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_openphs_det.h + * @author MCU Algorithm Team + * @brief This file contains self-check open phase fault detection function data struct and api declaration. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_MCS_OPENPHS_DET_H +#define McuMagicTag_MCS_OPENPHS_DET_H + +#include "typedefs.h" + +typedef enum { + OPD_U_V = 0, + OPD_V_U, + OPD_V_W, + OPD_W_V, + OPD_W_U, + OPD_U_W, + OPD_END +} OPD_Index; + +typedef struct { + float minOpenPhsCurr; /* Minimum current for open-phase detection (A). */ + bool isOpenPhsU; + bool isOpenPhsV; + bool isOpenPhsW; +} OPD_Handle; + +void OPD_Init(OPD_Handle *opd, float minOpenPhsCurr); + +bool OPD_Exec(OPD_Handle *opd, const float *iuvw); + +void OPD_Clear(OPD_Handle *opd); +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/protection/mcs_stall_det.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/protection/mcs_stall_det.c new file mode 100644 index 0000000000000000000000000000000000000000..be54fab4cb36e46217697079d31cf92b73901172 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/protection/mcs_stall_det.c @@ -0,0 +1,90 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_stall_det.c + * @author MCU Algorithm Team + * @brief This file contains motor stalling protection data struct and api declaration. + */ + +#include "mcs_stall_det.h" +#include "mcs_assert.h" +#include "mcs_math.h" + + +/** + * @brief Initilization motor stalling protection function. + * @param stall Motor stalling handle. + * @param ts Ctrl period (s). + * @param currLimit The current amplitude that triggers fault. (A). + * @param spdLimit The speed amplitude that triggers fault. (Hz). + * @param timeLimit The threshold time that current amplitude over the limit (s). + * @retval None. + */ +void STD_Init(STD_Handle *stall, float currLimit, float spdLimit, float timeLimit, float ts) +{ + MCS_ASSERT_PARAM(stall != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + MCS_ASSERT_PARAM(currLimit > 0.0f); + MCS_ASSERT_PARAM(spdLimit > 0.0f); + MCS_ASSERT_PARAM(timeLimit > 0.0f); + /* Configuring parameters for stalling detection. */ + stall->ts = ts; + /* Current threshold and speed threshold for stalling fault. */ + stall->currAmpLimit = currLimit; + stall->spdLimit = spdLimit; + stall->timeLimit = timeLimit; + stall->timer = 0.0f; +} + + +/** + * @brief Motor stalling detection. + * @param stall Motor stalling handle. + * @param motorErrStatus Motor error status. + * @param spd Speed feedback (Hz). + * @param idq Dq-axis current feedback (A). + * @retval Whether the motor is stalled, 1: motor stall, 0: no stall. + */ +bool STD_Exec_ByCurrSpd(STD_Handle *stall, float spdFbk, float currAmp) +{ + MCS_ASSERT_PARAM(stall != NULL); + /* Calculate current amplitude. */ + float currAbs = Abs(currAmp); + float spdAbs = Abs(spdFbk); + /* Check if value goes over threshold for continuous cycles. */ + if (spdAbs > stall->spdLimit || currAbs < stall->currAmpLimit) { + stall->timer = 0.0f; + return false; + } + /* Time accumulation. */ + if (stall->timer < stall->timeLimit) { + stall->timer += stall->ts; + return false; + } + return true; +} + +/** + * @brief Clear stall history value. + * @param stall Motor stalling handle. + * @retval None. + */ +void STD_Clear(STD_Handle *stall) +{ + MCS_ASSERT_PARAM(stall != NULL); + stall->timer = 0.0f; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/protection/mcs_stall_det.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/protection/mcs_stall_det.h new file mode 100644 index 0000000000000000000000000000000000000000..67055498727e9c7d32170d9292e592e6bc6ebb94 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/protection/mcs_stall_det.h @@ -0,0 +1,44 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_stall_det.h + * @author MCU Algorithm Team + * @brief This file contains motor stalling protection data struct and api declaration. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_MCS_STALL_DET_H +#define McuMagicTag_MCS_STALL_DET_H + +#include "typedefs.h" + + +typedef struct { + float currAmpLimit; /**< Feedback current higher than this value triggers fault. (A). */ + float spdLimit; /**< Feedback speed lower than this value triggers fault (Hz). */ + float timeLimit; /**< The threshold time that current and speed feedback over ranges (s). */ + float timer; /**< Timer to get speed and current over range time. */ + float ts; /**< Ctrl period (s). */ +} STD_Handle; + +void STD_Init(STD_Handle *stall, float currLimit, float spdLimit, float timeLimit, float ts); + +bool STD_Exec_ByCurrSpd(STD_Handle *stall, float spdFbk, float currAmp); + +void STD_Clear(STD_Handle *stall); + +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/protection/mcs_unbalance_det.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/protection/mcs_unbalance_det.c new file mode 100644 index 0000000000000000000000000000000000000000..b7f24d89dc9dd01ab36f40de9adb55d569a85d99 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/protection/mcs_unbalance_det.c @@ -0,0 +1,225 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_unbalance_det.c + * @author MCU Algorithm Team + * @brief This file provides motor application for Three-phase imbalance detection. + */ + + +#include "mcs_unbalance_det.h" +#include "mcs_math.h" +#include "mcs_math_const.h" +#include "mcs_assert.h" + + +#define START_UNBAL_DET_TIME_S 5 + +/** + * @brief Initilization three-phase unbalance protection function. + * @param unbal Three-phase unbalance detect handle. + * @param currDelta Threshold for determining the zero-crossing point of the phase current. + * @param timeThr Time thredhold of duration , unit: s. + * @param unbalDegreeLim Threshold of the imbalance degree. + * @param ts Ctrl period (s). + * @retval None. + */ +void UNBAL_Init(UNBAL_Handle *unbal, float currDelta, float timeThr, float unbalDegreeLim, float ts) +{ + MCS_ASSERT_PARAM(unbal != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + unbal->detCntLimit = (unsigned int)(timeThr / ts); + unbal->unbalDegreeLimit = unbalDegreeLim; + /* Configuring Limit Times */ + unbal->delta = currDelta; + /* Restore the initial state. */ + unbal->startFlagLast = false; + unbal->startFlag = false; + unbal->ts = ts; + unbal->startupCnt = (unsigned int)(START_UNBAL_DET_TIME_S / ts); + unbal->detCnt = 0; + UNBAL_Clear(unbal); +} + + +/** + * @brief Get three-phase current rms. + * @param unbal Three-phase unbalance detect handle. + * @param iUvw Three-phase current (A). + * @retval None. + */ +static void UNBAL_RmsCurrCalc(UNBAL_Handle *unbal, UvwAxis iUvw) +{ + MCS_ASSERT_PARAM(unbal != NULL); + if (unbal->calFlag) { + /* rms integral */ + unbal->ia += (iUvw.u * iUvw.u * unbal->ts); + unbal->ib += (iUvw.v * iUvw.v * unbal->ts); + unbal->ic += (iUvw.w * iUvw.w * unbal->ts); + unbal->ia = Clamp(unbal->ia, LARGE_FLOAT, -LARGE_FLOAT); + unbal->ib = Clamp(unbal->ib, LARGE_FLOAT, -LARGE_FLOAT); + unbal->ic = Clamp(unbal->ic, LARGE_FLOAT, -LARGE_FLOAT); + + unbal->timeCnt++; + /* Filter out the incomplete period data before the calculation starts. */ + if (unbal->timeCnt < unbal->startupCnt) { + unbal->unbalDegree = 0.0f; + } else if (unbal->timeCnt > unbal->startupCnt + unbal->startupCnt) { + /* Current accumulation is abnormal. */ + unbal->calFlag = false; + unbal->unbalDegree = 0.0f; + unbal->timeCnt = 0; + } else { + if (unbal->startFlagLast != unbal->startFlag) { + unbal->timeCnt = unbal->startupCnt; + } + } + } +} + + +/** + * @brief Get three-phase current rms. + * @param unbal Three-phase unbalance detect handle. + * @param iuvwFbk Three-phase current (A). + * @retval None. + */ +static void UNBAL_RmsCurrGet(UNBAL_Handle *unbal, UvwAxis *iuvwFbk) +{ + UvwAxis iUvw; + float delta = unbal->delta; + + iUvw.u = iuvwFbk->u; + iUvw.v = iuvwFbk->v; + iUvw.w = iuvwFbk->w; + /* Current zero-crossing detection */ + if (iUvw.u < -delta && unbal->startFlag == false) { + unbal->zeroFlag = true; + } + /* Current cycle start judgment */ + if (iUvw.u > delta && unbal->startFlag == false && unbal->zeroFlag) { + unbal->startFlag = true; + unbal->zeroFlag = false; + } + + if (unbal->startFlag) { + /* Accumulated number of integral */ + unbal->integralCnt++; + /* Periodic zero crossing detection */ + if (iUvw.u < -delta) { + unbal->zeroFlag = true; + } + if (iUvw.u > delta && unbal->zeroFlag) { + unbal->zeroFlag = false; + unbal->startFlag = false; + } + } + UNBAL_RmsCurrCalc(unbal, iUvw); +} + + +/** + * @brief Three-phase unbalance calculation. + * @param unbal Three-phase unbalance detect handle. + * @param iuvwFbk Three-phase current (A). + * @param unbalFltCoeff Average filter coefficient for calculating current unbalance degree. + * @retval None. + */ +static void UNBAL_Calc(UNBAL_Handle *unbal, UvwAxis *iuvwFbk, float unbalFltCoeff) +{ + /* Get rms current */ + UNBAL_RmsCurrGet(unbal, iuvwFbk); + /* Current cycle sampling completed */ + if (unbal->startFlagLast != unbal->startFlag) { + unbal->calFlag = true; + if (Abs(unbal->ia) <= 1e-6) { /* Whether there is current */ + unbal->unbalDegree = 0.0f; + return; + } + /* Calculate the three-phase current rms value. */ + float time = (float)unbal->integralCnt * unbal->ts; + float ia = Sqrt(unbal->ia / time); + float ib = Sqrt(unbal->ib / time); + float ic = Sqrt(unbal->ic / time); + unbal->integralCnt = 0; + + /* Based on the symmetrical component method, + three groups of symmetrical components and three-phase currents are + decomposed under the condition of three-phase phase symmetry. + The relationship between amplitudes is as follows: */ + float ia1 = ONE_DIV_THREE * (ia + ib + ic); /* Ia1 = 1/3 * (ia + ib + ic) */ + float tmp = (ia - 0.5f * ib - 0.5f * ic) * (ia - 0.5f * ib - 0.5f * ic); + float tmp2 = 0.75f * (ib - ic) * (ib - ic); /* Ia2 = 1/3 * sqrt((ia - 0.5 * ib)^2 + 3/4 * (ib -ic)^2) */ + float tmp3 = 0.75f * (ic - ib) * (ic - ib); /* Ia0 = 1/3 * sqrt((ia - 0.5 * ib)^2 + 3/4 * (ic -ib)^2) */ + float ia2 = ONE_DIV_THREE * Sqrt(tmp + tmp2); + float ia0 = ONE_DIV_THREE * Sqrt(tmp + tmp3); + float ig = Sqrt(ia0 * ia0 + ia2 * ia2); /* Total unbalanced current */ + float igPer = ig / ia1; /* Current unbalance factor */ + unbal->unbalDegree = unbal->unbalDegree * (1.0f - unbalFltCoeff) + igPer * unbalFltCoeff; + /* Clear current history value */ + unbal->ia = 0.0f; + unbal->ib = 0.0f; + unbal->ic = 0.0f; + } + unbal->startFlagLast = unbal->startFlag; +} + + +/** + * @brief Three-phase unbalance protection detection. + * @param unbal Three-phase unbalance detect handle. + * @param iuvwFbk Three-phase current. + * @retval None. + */ +bool UNBAL_Det(UNBAL_Handle *unbal, UvwAxis *iuvwFbk, float unbalFltCoeff) +{ + MCS_ASSERT_PARAM(unbal != NULL); + MCS_ASSERT_PARAM(iuvwFbk != NULL); + + UNBAL_Calc(unbal, iuvwFbk, unbalFltCoeff); + /* The three-phase imbalance exceeds the limit value. */ + if (unbal->unbalDegree > unbal->unbalDegreeLimit) { + unbal->detCnt++; + /* Current out of balance fault is detected, */ + /* when the protection hysteresis count is greater than the threshold. */ + if (unbal->detCnt > unbal->detCntLimit) { + unbal->detCnt = 0; + return false; + } + } else { + unbal->detCnt = 0; + } + return true; +} + +/** + * @brief Clear historical status of three-phase unbalance detection. + * @param unbal Three-phase unbalance detect handle. + * @retval None. + */ +void UNBAL_Clear(UNBAL_Handle *unbal) +{ + MCS_ASSERT_PARAM(unbal != NULL); + /* Clear historical status */ + unbal->ia = 0.0f; + unbal->ib = 0.0f; + unbal->ic = 0.0f; + unbal->unbalDegree = 0.0f; + unbal->calFlag = false; + /* Detection time count. */ + unbal->timeCnt = 0; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/protection/mcs_unbalance_det.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/protection/mcs_unbalance_det.h new file mode 100644 index 0000000000000000000000000000000000000000..ac94519e49ddaeb103f9d35bac773f05833b1d91 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/protection/mcs_unbalance_det.h @@ -0,0 +1,55 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_unbalance_det.h + * @author MCU Algorithm Team + * @brief This file contains three-phase imbalance protection data struct and api declaration. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_MCS_UNBALANCE_DET_H +#define McuMagicTag_MCS_UNBALANCE_DET_H + +#include "typedefs.h" +#include "mcs_typedef.h" + +typedef struct { + unsigned int detCnt; + unsigned int detCntLimit; + unsigned int integralCnt; + unsigned int timeCnt; + unsigned int startupCnt; + bool startFlag; + bool startFlagLast; + bool zeroFlag; + bool calFlag; + float unbalDegree; + float unbalDegreeLimit; + float delta; + float ts; + float ia; + float ib; + float ic; +} UNBAL_Handle; + + +void UNBAL_Init(UNBAL_Handle *unbal, float currDelta, float timeThr, float unbalDegreeLim, float ts); + +bool UNBAL_Det(UNBAL_Handle *unbal, UvwAxis *iuvwFbk, float unbalFltCoeff); + +void UNBAL_Clear(UNBAL_Handle *unbal); +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/ramp/mcs_ramp_mgmt.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/ramp/mcs_ramp_mgmt.c new file mode 100644 index 0000000000000000000000000000000000000000..eaf9a3015108a6e57dc9d77a98350bae55325295 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/ramp/mcs_ramp_mgmt.c @@ -0,0 +1,96 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_ramp_mgmt.c + * @author MCU Algorithm Team + * @brief This file provides function of ramp function. + */ + +#include "mcs_ramp_mgmt.h" +#include "mcs_assert.h" + +/** + * @brief Initializer of RMG handle. + * @param rmg: Pointer of RMG handle. + * @param ts: Control period of the RMG module. + * @param slope: Target value divide time of variation. + * @retval None. + */ +void RMG_Init(RMG_Handle *rmg, float ts, float slope) +{ + MCS_ASSERT_PARAM(rmg != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + /* Initializer of RMG handle. */ + rmg->slope = slope; + rmg->yLast = 0.0f; + rmg->ts = ts; + rmg->delta = rmg->slope * rmg->ts; +} + +/** + * @brief Clear historical values of RMG handle. + * @param rmg: Pointer of RMG handle. + * @retval None. + */ +void RMG_Clear(RMG_Handle *rmg) +{ + MCS_ASSERT_PARAM(rmg != NULL); + rmg->yLast = 0.0f; +} + +/** + * @brief Ramp generation and management. + * @param rmg: Pointer of RMG handle. + */ +float RMG_Exec(RMG_Handle *rmg, float targetVal) +{ + MCS_ASSERT_PARAM(rmg != NULL); + float out; + /* Calculate the current output value based on the target value and slope. */ + if (rmg->yLast <= (targetVal - rmg->delta)) { + out = rmg->yLast + rmg->delta; + } else if (rmg->yLast >= (targetVal + rmg->delta)) { + out = rmg->yLast - rmg->delta; + } else { + out = rmg->yLast = targetVal; + } + /* Recording and outputting slope calculation results. */ + rmg->yLast = out; + return out; +} + +/** + * @brief Set ts for ramp. + * @param rmg Pointer of RMG handle. + * @retval The reference value which is ramped. + */ +void RMG_SetTs(RMG_Handle *rmg, float ts) +{ + MCS_ASSERT_PARAM(rmg != NULL); + /* Set ts. */ + rmg->ts = ts; + rmg->delta = rmg->slope * rmg->ts; +} + +void RMG_SetSlope(RMG_Handle *rmg, float slope) +{ + MCS_ASSERT_PARAM(rmg != NULL); + MCS_ASSERT_PARAM(slope > 0.0f); + /* Set slope. */ + rmg->slope = slope; + rmg->delta = rmg->slope * rmg->ts; +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/ramp/mcs_ramp_mgmt.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/ramp/mcs_ramp_mgmt.h new file mode 100644 index 0000000000000000000000000000000000000000..fecbbe48637d35752fde1c0fe94a6c2d10d2c527 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/ramp/mcs_ramp_mgmt.h @@ -0,0 +1,49 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_ramp_mgmt.h + * @author MCU Algorithm Team + * @brief Ramp generation and management for motor control. + * This file provides functions declaration of ramp generation and management module. + */ + +#ifndef McuMagicTag_MCS_RAMP_MGMT_H +#define McuMagicTag_MCS_RAMP_MGMT_H + + +/** + * @brief Ramp mgmt Struct. + */ +typedef struct { + float delta; /**< Step value per calculate period. */ + float yLast; /**< History value of output value. */ + float ts; /**< Control period of the RMG module. */ + float slope; /**< Slope, target value divide time of variation. */ +} RMG_Handle; + + +/** + * @defgroup RAMP_API RAMP API + * @brief The RAMP API definitions. + * @{ + */ +void RMG_Init(RMG_Handle *rmg, float ts, float slope); +void RMG_Clear(RMG_Handle *rmg); +float RMG_Exec(RMG_Handle *rmg, float targetVal); +void RMG_SetTs(RMG_Handle *rmg, float ts); +void RMG_SetSlope(RMG_Handle *rmg, float slope); +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/utilities/mcs_assert.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/utilities/mcs_assert.h new file mode 100644 index 0000000000000000000000000000000000000000..c61b1275c320343fdd8a3e76b93ba148a3186903 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/utilities/mcs_assert.h @@ -0,0 +1,57 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_assert.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of the assert. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_MCS_ASSERT_H +#define McuMagicTag_MCS_ASSERT_H + +/* Includes ------------------------------------------------------------------ */ +#include "baseinc.h" + +/** + * @defgroup MCS_ASSERT MCS_ASSERT + * @brief MCS ASSERT module. + * @{ + */ + +/** + * @defgroup ASSERT_Macro ASSERT Macro Function Definition + * @{ + */ +#ifdef MCS_PARAM_CHECK +#define MCS_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define MCS_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define MCS_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define MCS_ASSERT_PARAM(para) ((void)0U) +#define MCS_PARAM_CHECK_NO_RET(para) ((void)0U) +#define MCS_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +/** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/utilities/mcs_mtr_param.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/utilities/mcs_mtr_param.c new file mode 100644 index 0000000000000000000000000000000000000000..29eaffbf2dd2d4ec1fe946efc66c0058fcc5af98 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/utilities/mcs_mtr_param.c @@ -0,0 +1,47 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_mtr_param.c + * @author MCU Algorithm Team + * @brief This file provides data structure define of motor parameters. + */ + +#include "mcs_mtr_param.h" + + +/** + * @brief Initialzer of motor parameters. + * @param handle Motor parameters handle. + * @param motorTable Motor parameters table. + * @retval None. + */ + void MtrParamInit(MOTOR_Param *handle, const MOTOR_Param motorTable) +{ + MCS_ASSERT_PARAM(handle != NULL); + /* Initialzer of motor parameters */ + handle->mtrRs = motorTable.mtrRs; /* resistor of stator */ + handle->mtrLd = motorTable.mtrLd; /* inductance of D-axis */ + handle->mtrLq = motorTable.mtrLq; /* inductance of Q-axis */ + /* Average inductance, mtrLs = (mtrLd + mtrLq) * 0.5f */ + handle->mtrLs = (motorTable.mtrLd + motorTable.mtrLq) * 0.5f; + handle->mtrPsif = motorTable.mtrPsif; /* permanent magnet flux */ + handle->mtrNp = motorTable.mtrNp; /* numbers of pole pairs */ + handle->mtrJ = motorTable.mtrJ; /* rotor inertia */ + handle->maxElecSpd = motorTable.maxElecSpd; /* max elec speed */ + handle->maxCurr = motorTable.maxCurr; /* max current */ + handle->maxTrq = motorTable.maxTrq; /* max torque */ +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/utilities/mcs_mtr_param.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/utilities/mcs_mtr_param.h new file mode 100644 index 0000000000000000000000000000000000000000..678d58a30246a979b0b1f043b24ecd36581c4053 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/utilities/mcs_mtr_param.h @@ -0,0 +1,59 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_mtr_param.h + * @author MCU Algorithm Team + * @brief This file provides data structure define of motor parameters. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_MTR_PARAM_H +#define McuMagicTag_MCS_MTR_PARAM_H + +/* Typedef definitions ------------------------------------------------------------------------- */ +#include "mcs_assert.h" +/** + * @defgroup MOTOR_PARAMETER MOTOR PARAMETER + * @brief The motor parameter definitions. + * @{ + */ +/** + * @brief motor parameters data structure + */ +typedef struct { + unsigned short mtrNp; /**< Numbers of pole pairs. */ + float mtrRs; /**< Resistor of stator, Ohm. */ + float mtrLd; /**< Inductance of D-axis, H. */ + float mtrLq; /**< Inductance of Q-axis, H. */ + float mtrLs; /**< Average inductance, H. */ + float mtrPsif; /**< Permanent magnet flux, Wb. */ + float mtrJ; /**< Rotor inertia, Kg*m2. */ + float maxElecSpd; /**< Max elec speed, Hz. */ + float maxCurr; /**< Max current, A. */ + float maxTrq; /**< Max torque, Nm. */ + /* Encoder parameters */ + unsigned int mtrPPMR; /**< pulse per mechanical round */ + unsigned int zShift; /**< pulse Z shift */ +} MOTOR_Param; + + +void MtrParamInit(MOTOR_Param *handle, const MOTOR_Param motorTable); +/** + * @} + */ + +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/utilities/mcs_sys_status.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/utilities/mcs_sys_status.h new file mode 100644 index 0000000000000000000000000000000000000000..c26301fc82001cba9191939d103ef2850dd9eab4 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/utilities/mcs_sys_status.h @@ -0,0 +1,188 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_sys_status.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of system status. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_SYS_STATUS_H +#define McuMagicTag_MCS_SYS_STATUS_H + +/* Includes ------------------------------------------------------------------------------------ */ +#include "typedefs.h" +#include "mcs_assert.h" + +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief System status define + */ +typedef union { + unsigned short all; + struct { + unsigned short cmdStart : 1; /**< Indicates that a start system command has been received. */ + unsigned short cmdStop : 1; /**< Indicates that a stop system command has been received. */ + unsigned short isRunning : 1; /**< Indicates that the system is running (enable signal) */ + unsigned short sysError : 1; /**< Indicates that the system reports an error. */ + unsigned short poweron : 1; /**< Indicates that the power-on initialization phase is complete. */ + unsigned short capcharge : 1; /**< Indicates that the bootstrap capacitor charging phase is complete. */ + unsigned short adczero : 1; /**< The current sampling point is reset to zero after power-on. */ + } Bit; +} SysStatusReg; + +/** + * @brief Get status of Bit cmdStart. + * @param sysStatus System status register handle. + * @retval Status of Bit cmdStart. + */ +static inline bool SysGetCmdStart(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + bool ret; + ret = (sysStatus->Bit.cmdStart == 1) ? true : false; + return ret; +} + +/** + * @brief Set Bit cmdStart. + * @param sysStatus System status register handle. + * @retval None. + */ +static inline void SysCmdStartSet(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + sysStatus->Bit.cmdStart = 1; +} + +/** + * @brief Clear Bit cmdStart. + * @param handle System status register handle. + * @retval None. + */ +static inline void SysCmdStartClr(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + sysStatus->Bit.cmdStart = 0; +} + +/** + * @brief Get status of Bit cmdStop. + * @param sysStatus System status register handle. + * @retval Status of Bit cmdStart. + */ +static inline bool SysGetCmdStop(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + bool ret; + ret = (sysStatus->Bit.cmdStop == 1) ? true : false; + return ret; +} + +/** + * @brief Set Bit cmdStop. + * @param sysStatus System status register handle. + * @retval None. + */ +static inline void SysCmdStopSet(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + sysStatus->Bit.cmdStop = 1; +} + +/** + * @brief Clear Bit cmdStop. + * @param sysStatus System status register handle. + * @retval None. + */ +static inline void SysCmdStopClr(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + sysStatus->Bit.cmdStop = 0; +} + +/** + * @brief Get status of Bit isRunning. + * @param sysStatus System status register handle. + * @retval Status of Bit isRunning. + */ +static inline bool SysIsRunning(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + bool ret; + ret = (sysStatus->Bit.isRunning == 1) ? true : false; + return ret; +} + +/** + * @brief Set Bit isRuning. + * @param sysStatus System status register handle. + * @retval None. + */ +static inline void SysRunningSet(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + sysStatus->Bit.isRunning = 1; +} + +/** + * @brief Clear Bit isRuning. + * @param sysStatus System status register handle. + * @retval None. + */ +static inline void SysRunningClr(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + sysStatus->Bit.isRunning = 0; +} + +/** + * @brief Get status of Bit sysError. + * @param sysStatus System status register handle. + * @retval Status of Bit sysError. + */ +static inline bool SysIsError(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + bool ret; + ret = (sysStatus->Bit.sysError == 1) ? true : false; + return ret; +} + +/** + * @brief Set Bit sysError. + * @param sysStatus System status register handle. + * @retval None. + */ +static inline void SysErrorSet(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + sysStatus->Bit.sysError = 1; +} + +/** + * @brief Clear Bit sysError. + * @param sysStatus System status register handle. + * @retval None. + */ +static inline void SysErrorClr(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + sysStatus->Bit.sysError = 0; +} + +#endif diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/utilities/mcs_typedef.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/utilities/mcs_typedef.h new file mode 100644 index 0000000000000000000000000000000000000000..9a9fb890a7f6d090a6a412bb73d9a6d6319b1fc8 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/utilities/mcs_typedef.h @@ -0,0 +1,59 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_typedef.h + * @author MCU Algorithm Team + * @brief This file provides the definition of the motor basic data structure. + */ + +#ifndef McuMagicTag_MCS_TYPEDEF_H +#define McuMagicTag_MCS_TYPEDEF_H + + +/** + * @defgroup MCS COORDINATE + * @brief Motor Basic coordinate data structures. + * @{ + */ + +/** + * @brief Rotor synchronous rotation coordinate frame Variables. + */ +typedef struct { + float d; /**< Component d of the rotor synchronous rotation coordinate variable. */ + float q; /**< Component q of the rotor synchronous rotation coordinate variable. */ +} DqAxis; + +/** + * @brief Two-phase stationary coordinate frame variable. + */ +typedef struct { + float alpha; /**< Component alpha of the two-phase stationary coordinate variable. */ + float beta; /**< Component beta of the two-phase stationary coordinate variable. */ +} AlbeAxis; + +/** + * @brief Three-phase static coordinate frame variable. + */ +typedef struct { + float u; /**< Component u of the three-phase static coordinate frame variable. */ + float v; /**< Component v of the three-phase static coordinate frame variable. */ + float w; /**< Component w of the three-phase static coordinate frame variable. */ +} UvwAxis; + + +#endif /* McuMagicTag_MCS_TYPEDEF_H */ diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/vf/mcs_vf_ctrl.c b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/vf/mcs_vf_ctrl.c new file mode 100644 index 0000000000000000000000000000000000000000..ea2457a17f7f7ab60c670b7f8732ee89e27f7b3f --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/vf/mcs_vf_ctrl.c @@ -0,0 +1,155 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_vf_ctrl.c + * @author MCU Algorithm Team + * @brief This file provides functions declaration of v/f control. + */ + +#include "mcs_vf_ctrl.h" +#include "mcs_math.h" +#include "mcs_assert.h" +#include "mcs_math_const.h" + +/** + * @brief Init the vf control handle. + * @param vf The vf control handle. + * @param spdThr Minimum (spdThr[0]) and maximum(spdThr[1]) speed thresholds for ramp command. + * @param voltThr Minimum (voltThr[0]) and maximum(voltThr[1]) voltage for thresholds ramp command. + * @param ts Control period. + * @param spdCmd Motor target speed frequency (Hz). + * @param spdSlope Slope of motor speed reference. + * @retval None. + */ +void VF_Init(VF_Handle *vf, const float *spdThr, const float *voltThr, float ts, float spdCmd, float spdSlope) +{ + MCS_ASSERT_PARAM(vf != NULL); + MCS_ASSERT_PARAM(spdThr != NULL); + MCS_ASSERT_PARAM(voltThr != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + VF_Clear(vf); + RMG_Init(&vf->rmg, ts, spdSlope); + vf->spdCmd = spdCmd; + vf->ts = ts; + /* Set voltage-speed curve. */ + vf->spdThr[0] = spdThr[0]; /* The minimum vf speed. */ + vf->spdThr[1] = spdThr[1]; /* The maximum vf speed. */ + vf->voltThr[0] = voltThr[0]; /* The minimum voltage. */ + vf->voltThr[1] = voltThr[1]; /* The maximum vf voltage. */ + /* Calculate vf slope. */ + vf->slope = (voltThr[1] - voltThr[0]) / (spdThr[1] - spdThr[0]); + vf->ratio.d = 1.0f; + vf->ratio.q = 0.0f; +} + +/** + * @brief Vf control Execution. + * @param vf The vf control handle. + * @param vdqRef Dq axis voltage reference vf control. + * @retval None. + */ +void VF_Exec(VF_Handle *vf, DqAxis *vdqRef) +{ + MCS_ASSERT_PARAM(vf != NULL); + MCS_ASSERT_PARAM(vdqRef != NULL); + /* Vf speed generation. */ + vf->spdRef = RMG_Exec(&vf->rmg, vf->spdCmd); + float vs = 0.0f; + float lowSpdHz = vf->spdThr[0]; + float highSpdHz = vf->spdThr[1]; + float voltMin = vf->voltThr[0]; + float voltMax = vf->voltThr[1]; + /* When the vf reference speed is less than the minimum speed threshold, */ + /* the voltage is set to the minimum voltage threshold. */ + /* When the vf reference speed is greater than the maximum speed threshold, */ + /* the voltage is set to the maximum voltage threshold. */ + if (vf->spdRef < lowSpdHz) { + vs = voltMin; + } else if (vf->spdRef > highSpdHz) { + vs = voltMax; + } else { + vs = voltMin + vf->slope * (vf->spdRef - lowSpdHz); + } + /* Sets dq voltage based on the dq axis proportion */ + vf->vdqRef.d = vs * vf->ratio.d; + vf->vdqRef.q = vs * vf->ratio.q; + vf->vfAngle += DOUBLE_PI * vf->spdRef * vf->ts; + vf->vfAngle = Mod(vf->vfAngle, DOUBLE_PI); + if (vf->vfAngle > ONE_PI) { + vf->vfAngle -= DOUBLE_PI; + } + if (vf->vfAngle < -ONE_PI) { + vf->vfAngle += DOUBLE_PI; + } + vdqRef->d = vf->vdqRef.d; + vdqRef->q = vf->vdqRef.q; +} + +/** + * @brief Clear the vf control history value. + * @param vf The vf control handle. + * @retval None. + */ +void VF_Clear(VF_Handle *vf) +{ + MCS_ASSERT_PARAM(vf != NULL); + /* Clear history value. */ + vf->vfAngle = 0.0f; + vf->spdRef = 0.0f; + vf->vdqRef.d = 0.0f; + vf->vdqRef.q = 0.0f; +} + +/** + * @brief Set vf control period. + * @param vf The vf control handle. + * @param ts The updated vf control period. + * @retval None. + */ +void VF_SetTs(VF_Handle *vf, float ts) +{ + MCS_ASSERT_PARAM(vf != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + RMG_SetTs(&vf->rmg, ts); + vf->ts = ts; +} + +/** + * @brief Set the slope for the motor to accelerate to the target speed. + * @param vf The vf control handle. + * @param spdSlope The slope. + * @retval None. + */ +void VF_SetSpdSlope(VF_Handle *vf, float spdSlope) +{ + MCS_ASSERT_PARAM(vf != NULL); + RMG_SetSlope(&vf->rmg, spdSlope); +} + +/** + * @brief Set the voltage reference ratio of d, q axis. + * @param vf The vf control handle. + * @param dRatio D axis reference voltage ratio. + * @retval None. + */ +void VF_SetDRatio(VF_Handle *vf, float dRatio) +{ + MCS_ASSERT_PARAM(vf != NULL); + MCS_ASSERT_PARAM(dRatio >= 0.0f && dRatio <= 1.0f); + vf->ratio.d = dRatio; + vf->ratio.q = Sqrt(1.0f - dRatio * dRatio); +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/control_library/vf/mcs_vf_ctrl.h b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/vf/mcs_vf_ctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..5de22b3a0de93fde5284bdf1c6d6806f9466b307 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/control_library/vf/mcs_vf_ctrl.h @@ -0,0 +1,53 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_vf_ctrl.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of v/f control. + * + */ + +#ifndef McuMagicTag_MCS_VF_CTRL_H +#define McuMagicTag_MCS_VF_CTRL_H + + +#include "mcs_typedef.h" +#include "mcs_ramp_mgmt.h" + + +typedef struct { + float spdCmd; /**< Motor target speed frequency (Hz). */ + float spdRef; /**< Motor reference speed frequency (Hz). */ + float vfAngle; /**< Vf control angle. */ + float ts; /**< Control period. */ + float spdThr[2]; /**< Minimum (spdThr[0]) and maximum(spdThr[1]) speed thresholds for ramp command. */ + float voltThr[2]; /**< Minimum (voltThr[0]) and maximum(voltThr[1]) voltage for thresholds ramp command. */ + float slope; /**< Slope of the voltage-speed curve. */ + DqAxis ratio; /**< Proportion of dq-axis reference voltage. */ + DqAxis vdqRef; /**< Dq-axis reference voltage. */ + RMG_Handle rmg; /**< Ramp management structure */ +} VF_Handle; + + +void VF_Init(VF_Handle *vf, const float *spdThr, const float *voltThr, float ts, float spdCmd, float spdSlope); +void VF_Exec(VF_Handle *vf, DqAxis *vdqRef); +void VF_Clear(VF_Handle *vf); +void VF_SetTs(VF_Handle *vf, float ts); +void VF_SetSpdSlope(VF_Handle *vf, float spdSlope); +void VF_SetDRatio(VF_Handle *vf, float dRatio); + +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/LICENSE b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..42f2a83670c666eb8a37c96c31eb0e7eb019d8a0 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/LICENSE @@ -0,0 +1,124 @@ +木兰宽松许可证， 第2版 + +2020年1月 http://license.coscl.org.cn/MulanPSL2 + +您对“软件”的复制、使用、修改及分发受木兰宽松许可证，第2版（“本许可证”）的如下条款的约束： + +0. 定义 + +“软件” 是指由“贡献”构成的许可在“本许可证”下的程序和相关文档的集合。 + +“贡献” 是指由任一“贡献者”许可在“本许可证”下的受版权法保护的作品。 + +“贡献者” 是指将受版权法保护的作品许可在“本许可证”下的自然人或“法人实体”。 + +“法人实体” 是指提交贡献的机构及其“关联实体”。 + +“关联实体” 是指，对“本许可证”下的行为方而言，控制、受控制或与其共同受控制的机构，此处的控制是指有受控方或共同受控方至少50%直接或间接的投票权、资金或其他有价证券。 + +1. 授予版权许可 + +每个“贡献者”根据“本许可证”授予您永久性的、全球性的、免费的、非独占的、不可撤销的版权许可，您可以复制、使用、修改、分发其“贡献”，不论修改与否。 + +2. 授予专利许可 + +每个“贡献者”根据“本许可证”授予您永久性的、全球性的、免费的、非独占的、不可撤销的（根据本条规定撤销除外）专利许可，供您制造、委托制造、使用、许诺销售、销售、进口其“贡献”或以其他方式转移其“贡献”。前述专利许可仅限于“贡献者”现在或将来拥有或控制的其“贡献”本身或其“贡献”与许可“贡献”时的“软件”结合而将必然会侵犯的专利权利要求，不包括对“贡献”的修改或包含“贡献”的其他结合。如果您或您的“关联实体”直接或间接地，就“软件”或其中的“贡献”对任何人发起专利侵权诉讼（包括反诉或交叉诉讼）或其他专利维权行动，指控其侵犯专利权，则“本许可证”授予您对“软件”的专利许可自您提起诉讼或发起维权行动之日终止。 + +3. 无商标许可 + +“本许可证”不提供对“贡献者”的商品名称、商标、服务标志或产品名称的商标许可，但您为满足第4条规定的声明义务而必须使用除外。 + +4. 分发限制 + +您可以在任何媒介中将“软件”以源程序形式或可执行形式重新分发，不论修改与否，但您必须向接收者提供“本许可证”的副本，并保留“软件”中的版权、商标、专利及免责声明。 + +5. 免责声明与责任限制 + +“软件”及其中的“贡献”在提供时不带任何明示或默示的担保。在任何情况下，“贡献者”或版权所有者不对任何人因使用“软件”或其中的“贡献”而引发的任何直接或间接损失承担责任，不论因何种原因导致或者基于何种法律理论，即使其曾被建议有此种损失的可能性。 + +6. 语言 + +“本许可证”以中英文双语表述，中英文版本具有同等法律效力。如果中英文版本存在任何冲突不一致，以中文版为准。 + +条款结束 + +如何将木兰宽松许可证，第2版，应用到您的软件 + +如果您希望将木兰宽松许可证，第2版，应用到您的新软件，为了方便接收者查阅，建议您完成如下三步： + +1， 请您补充如下声明中的空白，包括软件名、软件的首次发表年份以及您作为版权人的名字； + +2， 请您在软件包的一级目录下创建以“LICENSE”为名的文件，将整个许可证文本放入该文件中； + +3， 请将如下声明文本放入每个源文件的头部注释中。 + +Copyright (c) [Year] [name of copyright holder] +[Software Name] is licensed under Mulan PSL v2. +You can use this software according to the terms and conditions of the Mulan PSL v2. +You may obtain a copy of Mulan PSL v2 at: + http://license.coscl.org.cn/MulanPSL2 +THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +See the Mulan PSL v2 for more details. +Mulan Permissive Software License,Version 2 +Mulan Permissive Software License,Version 2 (Mulan PSL v2) + +January 2020 http://license.coscl.org.cn/MulanPSL2 + +Your reproduction, use, modification and distribution of the Software shall be subject to Mulan PSL v2 (this License) with the following terms and conditions: + +0. Definition + +Software means the program and related documents which are licensed under this License and comprise all Contribution(s). + +Contribution means the copyrightable work licensed by a particular Contributor under this License. + +Contributor means the Individual or Legal Entity who licenses its copyrightable work under this License. + +Legal Entity means the entity making a Contribution and all its Affiliates. + +Affiliates means entities that control, are controlled by, or are under common control with the acting entity under this License, 'control' means direct or indirect ownership of at least fifty percent (50%) of the voting power, capital or other securities of controlled or commonly controlled entity. + +1. Grant of Copyright License + +Subject to the terms and conditions of this License, each Contributor hereby grants to you a perpetual, worldwide, royalty-free, non-exclusive, irrevocable copyright license to reproduce, use, modify, or distribute its Contribution, with modification or not. + +2. Grant of Patent License + +Subject to the terms and conditions of this License, each Contributor hereby grants to you a perpetual, worldwide, royalty-free, non-exclusive, irrevocable (except for revocation under this Section) patent license to make, have made, use, offer for sale, sell, import or otherwise transfer its Contribution, where such patent license is only limited to the patent claims owned or controlled by such Contributor now or in future which will be necessarily infringed by its Contribution alone, or by combination of the Contribution with the Software to which the Contribution was contributed. The patent license shall not apply to any modification of the Contribution, and any other combination which includes the Contribution. If you or your Affiliates directly or indirectly institute patent litigation (including a cross claim or counterclaim in a litigation) or other patent enforcement activities against any individual or entity by alleging that the Software or any Contribution in it infringes patents, then any patent license granted to you under this License for the Software shall terminate as of the date such litigation or activity is filed or taken. + +3. No Trademark License + +No trademark license is granted to use the trade names, trademarks, service marks, or product names of Contributor, except as required to fulfill notice requirements in section 4. + +4. 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IN THE CASE OF DIVERGENCE BETWEEN THE CHINESE AND ENGLISH VERSIONS, THE CHINESE VERSION SHALL PREVAIL. + +END OF THE TERMS AND CONDITIONS + +How to Apply the Mulan Permissive Software License,Version 2 (Mulan PSL v2) to Your Software + +To apply the Mulan PSL v2 to your work, for easy identification by recipients, you are suggested to complete following three steps: + +Fill in the blanks in following statement, including insert your software name, the year of the first publication of your software, and your name identified as the copyright owner; +Create a file named "LICENSE" which contains the whole context of this License in the first directory of your software package; +Attach the statement to the appropriate annotated syntax at the beginning of each source file. +Copyright (c) [Year] [name of copyright holder] +[Software Name] is licensed under Mulan PSL v2. +You can use this software according to the terms and conditions of the Mulan PSL v2. +You may obtain a copy of Mulan PSL v2 at: + http://license.coscl.org.cn/MulanPSL2 +THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +See the Mulan PSL v2 for more details. \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/Makefile b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..bdeee08550bc87b72e882f8541582de0e7dad468 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/Makefile @@ -0,0 +1,44 @@ +PROJECT=libboundscheck.so + +CC?=gcc + +OPTION = -fPIC +OPTION += -fstack-protector-all +OPTION += -D_FORTIFY_SOURCE=2 -O2 +OPTION += -Wformat=2 -Wfloat-equal -Wshadow +OPTION += -Wconversion +OPTION += -Wformat-security +OPTION += -Wextra +OPTION += --param ssp-buffer-size=4 +OPTION += -Warray-bounds +OPTION += -Wpointer-arith +OPTION += -Wcast-qual +OPTION += -Wstrict-prototypes +OPTION += -Wmissing-prototypes +OPTION += -Wstrict-overflow=1 +OPTION += -Wstrict-aliasing=2 +OPTION += -Wswitch -Wswitch-default + +CFLAG = -Wall -DNDEBUG -O2 $(OPTION) + +SOURCES=$(wildcard src/*.c) + +OBJECTS=$(patsubst %.c,%.o,$(SOURCES)) + +.PHONY:clean + +CFLAG += -Iinclude +LD_FLAG = -fPIC -s -Wl,-z,relro,-z,now,-z,noexecstack -fstack-protector-all + +$(PROJECT): $(OBJECTS) + mkdir -p lib + $(CC) -shared -o lib/$@ $(patsubst %.o,obj/%.o,$(notdir $(OBJECTS))) $(LD_FLAG) + @echo "finish $(PROJECT)" + +.c.o: + @mkdir -p obj + $(CC) -c $< $(CFLAG) -o obj/$(patsubst %.c,%.o,$(notdir $<)) + +clean: + -rm -rf obj lib + @echo "clean up" diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/README.en.md b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/README.en.md new file mode 100644 index 0000000000000000000000000000000000000000..60c477fe897827802759f8ff98f6d928ad3ddd9f --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/README.en.md @@ -0,0 +1,59 @@ +# libboundscheck + +#### Description + +- following the standard of C11 Annex K (bound-checking interfaces), functions of the common memory/string operation classes, such as memcpy_s, strcpy_s, are selected and implemented. + +- other standard functions in C11 Annex K will be analyzed in the future and implemented in this organization if necessary. + +- handles the release, update, and maintenance of bounds_checking_function. + +#### Function List + +- memcpy_s +- wmemcpy_s +- memmove_s +- wmemmove_s +- memset_s +- strcpy_s +- wcscpy_s +- strncpy_s +- wcsncpy_s +- strcat_s +- wcscat_s +- strncat_s +- wcsncat_s +- strtok_s +- wcstok_s +- sprintf_s +- swprintf_s +- vsprintf_s +- vswprintf_s +- snprintf_s +- vsnprintf_s +- scanf_s +- wscanf_s +- vscanf_s +- vwscanf_s +- fscanf_s +- fwscanf_s +- vfscanf_s +- vfwscanf_s +- sscanf_s +- swscanf_s +- vsscanf_s +- vswscanf_s +- gets_s + + +#### Build + +``` +CC=gcc make +``` +The generated Dynamic library libboundscheck.so is stored in the newly created directory lib. + +#### How to use +1. Copy the libboundscheck.so to the library file directory, for example: "/usr/local/lib/". + +2. To use the libboundscheck, add the “-lboundscheck” parameters to the compiler, for example: “gcc -g -o test test.c -lboundscheck”. \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/README.md b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/README.md new file mode 100644 index 0000000000000000000000000000000000000000..c16cbb17696c74ed845abf0449eadb239e409f6e --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/README.md @@ -0,0 +1,56 @@ +# libboundscheck + +#### 介绍 +- 遵循C11 Annex K (Bounds-checking interfaces)的标准，选取并实现了常见的内存/字符串操作类的函数，如memcpy_s、strcpy_s等函数。 +- 未来将分析C11 Annex K中的其他标准函数，如果有必要，将在该组织中实现。 +- 处理边界检查函数的版本发布、更新以及维护。 + +#### 函数清单 + +- memcpy_s +- wmemcpy_s +- memmove_s +- wmemmove_s +- memset_s +- strcpy_s +- wcscpy_s +- strncpy_s +- wcsncpy_s +- strcat_s +- wcscat_s +- strncat_s +- wcsncat_s +- strtok_s +- wcstok_s +- sprintf_s +- swprintf_s +- vsprintf_s +- vswprintf_s +- snprintf_s +- vsnprintf_s +- scanf_s +- wscanf_s +- vscanf_s +- vwscanf_s +- fscanf_s +- fwscanf_s +- vfscanf_s +- vfwscanf_s +- sscanf_s +- swscanf_s +- vsscanf_s +- vswscanf_s +- gets_s + +#### 构建方法 + +运行命令 +``` +make CC=gcc +``` +生成的动态库libboundscheck.so存放在新创建的lib目录下。 + +#### 使用方法 +1. 将构建生成的动态库libboundscheck.so放到库文件目录下，例如："/usr/local/lib/"。 + +2. 为使用libboundscheck，编译程序时需增加编译参数"-lboundscheck"，例如："gcc -g -o test test.c -lboundscheck"。 \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/include/securec.h b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/include/securec.h new file mode 100644 index 0000000000000000000000000000000000000000..b1dea967d8f5a6a14010ebf706fa5082fb229b4f --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/include/securec.h @@ -0,0 +1,637 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: The user of this secure c library should include this header file in you source code. + * This header file declare all supported API prototype of the library, + * such as memcpy_s, strcpy_s, wcscpy_s,strcat_s, strncat_s, sprintf_s, scanf_s, and so on. + * Create: 2014-02-25 + * Notes: Do not modify this file by yourself. + */ + +#ifndef SECUREC_H_5D13A042_DC3F_4ED9_A8D1_882811274C27 +#define SECUREC_H_5D13A042_DC3F_4ED9_A8D1_882811274C27 + +#include "securectype.h" +#ifndef SECUREC_HAVE_STDARG_H +#define SECUREC_HAVE_STDARG_H 1 +#endif + +#if SECUREC_HAVE_STDARG_H +#include +#endif + +#ifndef SECUREC_HAVE_ERRNO_H +#define SECUREC_HAVE_ERRNO_H 1 +#endif + +/* EINVAL ERANGE may defined in errno.h */ +#if SECUREC_HAVE_ERRNO_H +#if SECUREC_IN_KERNEL +#include +#else +#include +#endif +#endif + +/* Define error code */ +#if defined(SECUREC_NEED_ERRNO_TYPE) || !defined(__STDC_WANT_LIB_EXT1__) || \ + (defined(__STDC_WANT_LIB_EXT1__) && (!__STDC_WANT_LIB_EXT1__)) +#ifndef SECUREC_DEFINED_ERRNO_TYPE +#define SECUREC_DEFINED_ERRNO_TYPE +/* Just check whether macrodefinition exists. */ +#ifndef errno_t +typedef int errno_t; +#endif +#endif +#endif + +/* Success */ +#ifndef EOK +#define EOK 0 +#endif + +#ifndef EINVAL +/* The src buffer is not correct and destination buffer can not be reset */ +#define EINVAL 22 +#endif + +#ifndef EINVAL_AND_RESET +/* Once the error is detected, the dest buffer must be reset! Value is 22 or 128 */ +#define EINVAL_AND_RESET 150 +#endif + +#ifndef ERANGE +/* The destination buffer is not long enough and destination buffer can not be reset */ +#define ERANGE 34 +#endif + +#ifndef ERANGE_AND_RESET +/* Once the error is detected, the dest buffer must be reset! Value is 34 or 128 */ +#define ERANGE_AND_RESET 162 +#endif + +#ifndef EOVERLAP_AND_RESET +/* Once the buffer overlap is detected, the dest buffer must be reset! Value is 54 or 128 */ +#define EOVERLAP_AND_RESET 182 +#endif + +/* If you need export the function of this library in Win32 dll, use __declspec(dllexport) */ +#ifndef SECUREC_API +#if defined(SECUREC_DLL_EXPORT) +#if defined(_MSC_VER) +#define SECUREC_API __declspec(dllexport) +#else /* build for linux */ +#define SECUREC_API __attribute__((visibility("default"))) +#endif /* end of _MSC_VER and SECUREC_DLL_EXPORT */ +#elif defined(SECUREC_DLL_IMPORT) +#if defined(_MSC_VER) +#define SECUREC_API __declspec(dllimport) +#else +#define SECUREC_API +#endif /* end of _MSC_VER and SECUREC_DLL_IMPORT */ +#else +/* + * Standardized function declaration. If a security function is declared in the your code, + * it may cause a compilation alarm,Please delete the security function you declared. + * Adding extern under windows will cause the system to have inline functions to expand, + * so do not add the extern in default + */ +#if defined(_MSC_VER) +#define SECUREC_API +#else +#define SECUREC_API extern +#endif +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif +/* + * Description: The GetHwSecureCVersion function get SecureC Version string and version number. + * Parameter: verNumber - to store version number (for example value is 0x500 | 0xa) + * Return: version string + */ +SECUREC_API const char *GetHwSecureCVersion(unsigned short *verNumber); + +#if SECUREC_ENABLE_MEMSET +/* + * Description: The memset_s function copies the value of c (converted to an unsigned char) into each of + * the first count characters of the object pointed to by dest. + * Parameter: dest - destination address + * Parameter: destMax - The maximum length of destination buffer + * Parameter: c - the value to be copied + * Parameter: count - copies count bytes of value to dest + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t memset_s(void *dest, size_t destMax, int c, size_t count); +#endif + +#ifndef SECUREC_ONLY_DECLARE_MEMSET +#define SECUREC_ONLY_DECLARE_MEMSET 0 +#endif + +#if !SECUREC_ONLY_DECLARE_MEMSET + +#if SECUREC_ENABLE_MEMMOVE +/* + * Description: The memmove_s function copies n characters from the object pointed to by src + * into the object pointed to by dest. + * Parameter: dest - destination address + * Parameter: destMax - The maximum length of destination buffer + * Parameter: src - source address + * Parameter: count - copies count bytes from the src + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t memmove_s(void *dest, size_t destMax, const void *src, size_t count); +#endif + +#if SECUREC_ENABLE_MEMCPY +/* + * Description: The memcpy_s function copies n characters from the object pointed to + * by src into the object pointed to by dest. + * Parameter: dest - destination address + * Parameter: destMax - The maximum length of destination buffer + * Parameter: src - source address + * Parameter: count - copies count bytes from the src + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t memcpy_s(void *dest, size_t destMax, const void *src, size_t count); +#endif + +#if SECUREC_ENABLE_STRCPY +/* + * Description: The strcpy_s function copies the string pointed to by strSrc (including + * the terminating null character) into the array pointed to by strDest + * Parameter: strDest - destination address + * Parameter: destMax - The maximum length of destination buffer(including the terminating null character) + * Parameter: strSrc - source address + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t strcpy_s(char *strDest, size_t destMax, const char *strSrc); +#endif + +#if SECUREC_ENABLE_STRNCPY +/* + * Description: The strncpy_s function copies not more than n successive characters (not including + * the terminating null character) from the array pointed to by strSrc to the array pointed to by strDest. + * Parameter: strDest - destination address + * Parameter: destMax - The maximum length of destination buffer(including the terminating null character) + * Parameter: strSrc - source address + * Parameter: count - copies count characters from the src + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t strncpy_s(char *strDest, size_t destMax, const char *strSrc, size_t count); +#endif + +#if SECUREC_ENABLE_STRCAT +/* + * Description: The strcat_s function appends a copy of the string pointed to by strSrc (including + * the terminating null character) to the end of the string pointed to by strDest. + * Parameter: strDest - destination address + * Parameter: destMax - The maximum length of destination buffer(including the terminating null wide character) + * Parameter: strSrc - source address + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t strcat_s(char *strDest, size_t destMax, const char *strSrc); +#endif + +#if SECUREC_ENABLE_STRNCAT +/* + * Description: The strncat_s function appends not more than n successive characters (not including + * the terminating null character) + * from the array pointed to by strSrc to the end of the string pointed to by strDest. + * Parameter: strDest - destination address + * Parameter: destMax - The maximum length of destination buffer(including the terminating null character) + * Parameter: strSrc - source address + * Parameter: count - copies count characters from the src + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t strncat_s(char *strDest, size_t destMax, const char *strSrc, size_t count); +#endif + +#if SECUREC_ENABLE_VSPRINTF +/* + * Description: The vsprintf_s function is equivalent to the vsprintf function except for the parameter destMax + * and the explicit runtime-constraints violation + * Parameter: strDest - produce output according to a format,write to the character string strDest. + * Parameter: destMax - The maximum length of destination buffer(including the terminating null wide character) + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of characters printed(not including the terminating null byte '\0'), + * If an error occurred Return: -1. + */ +SECUREC_API int vsprintf_s(char *strDest, size_t destMax, const char *format, + va_list argList) SECUREC_ATTRIBUTE(3, 0); +#endif + +#if SECUREC_ENABLE_SPRINTF +/* + * Description: The sprintf_s function is equivalent to the sprintf function except for the parameter destMax + * and the explicit runtime-constraints violation + * Parameter: strDest - produce output according to a format ,write to the character string strDest. + * Parameter: destMax - The maximum length of destination buffer(including the terminating null byte '\0') + * Parameter: format - format string + * Return: the number of characters printed(not including the terminating null byte '\0'), + * If an error occurred Return: -1. +*/ +SECUREC_API int sprintf_s(char *strDest, size_t destMax, const char *format, ...) SECUREC_ATTRIBUTE(3, 4); +#endif + +#if SECUREC_ENABLE_VSNPRINTF +/* + * Description: The vsnprintf_s function is equivalent to the vsnprintf function except for + * the parameter destMax/count and the explicit runtime-constraints violation + * Parameter: strDest - produce output according to a format ,write to the character string strDest. + * Parameter: destMax - The maximum length of destination buffer(including the terminating null byte '\0') + * Parameter: count - do not write more than count bytes to strDest(not including the terminating null byte '\0') + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of characters printed(not including the terminating null byte '\0'), + * If an error occurred Return: -1.Pay special attention to returning -1 when truncation occurs. + */ +SECUREC_API int vsnprintf_s(char *strDest, size_t destMax, size_t count, const char *format, + va_list argList) SECUREC_ATTRIBUTE(4, 0); +#endif + +#if SECUREC_ENABLE_SNPRINTF +/* + * Description: The snprintf_s function is equivalent to the snprintf function except for + * the parameter destMax/count and the explicit runtime-constraints violation + * Parameter: strDest - produce output according to a format ,write to the character string strDest. + * Parameter: destMax - The maximum length of destination buffer(including the terminating null byte '\0') + * Parameter: count - do not write more than count bytes to strDest(not including the terminating null byte '\0') + * Parameter: format - format string + * Return: the number of characters printed(not including the terminating null byte '\0'), + * If an error occurred Return: -1.Pay special attention to returning -1 when truncation occurs. + */ +SECUREC_API int snprintf_s(char *strDest, size_t destMax, size_t count, const char *format, + ...) SECUREC_ATTRIBUTE(4, 5); +#endif + +#if SECUREC_SNPRINTF_TRUNCATED +/* + * Description: The vsnprintf_truncated_s function is equivalent to the vsnprintf_s function except + * no count parameter and return value + * Parameter: strDest - produce output according to a format ,write to the character string strDest + * Parameter: destMax - The maximum length of destination buffer(including the terminating null byte '\0') + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of characters printed(not including the terminating null byte '\0'), + * If an error occurred Return: -1.Pay special attention to returning destMax - 1 when truncation occurs +*/ +SECUREC_API int vsnprintf_truncated_s(char *strDest, size_t destMax, const char *format, + va_list argList) SECUREC_ATTRIBUTE(3, 0); + +/* + * Description: The snprintf_truncated_s function is equivalent to the snprintf_s function except + * no count parameter and return value + * Parameter: strDest - produce output according to a format,write to the character string strDest. + * Parameter: destMax - The maximum length of destination buffer(including the terminating null byte '\0') + * Parameter: format - format string + * Return: the number of characters printed(not including the terminating null byte '\0'), + * If an error occurred Return: -1.Pay special attention to returning destMax - 1 when truncation occurs. + */ +SECUREC_API int snprintf_truncated_s(char *strDest, size_t destMax, + const char *format, ...) SECUREC_ATTRIBUTE(3, 4); +#endif + +#if SECUREC_ENABLE_SCANF +/* + * Description: The scanf_s function is equivalent to fscanf_s with the argument stdin + * interposed before the arguments to scanf_s + * Parameter: format - format string + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int scanf_s(const char *format, ...); +#endif + +#if SECUREC_ENABLE_VSCANF +/* + * Description: The vscanf_s function is equivalent to scanf_s, with the variable argument list replaced by argList + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int vscanf_s(const char *format, va_list argList); +#endif + +#if SECUREC_ENABLE_SSCANF +/* + * Description: The sscanf_s function is equivalent to fscanf_s, except that input is obtained from a + * string (specified by the argument buffer) rather than from a stream + * Parameter: buffer - read character from buffer + * Parameter: format - format string + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int sscanf_s(const char *buffer, const char *format, ...); +#endif + +#if SECUREC_ENABLE_VSSCANF +/* + * Description: The vsscanf_s function is equivalent to sscanf_s, with the variable argument list + * replaced by argList + * Parameter: buffer - read character from buffer + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int vsscanf_s(const char *buffer, const char *format, va_list argList); +#endif + +#if SECUREC_ENABLE_FSCANF +/* + * Description: The fscanf_s function is equivalent to fscanf except that the c, s, and [ conversion specifiers + * apply to a pair of arguments (unless assignment suppression is indicated by a *) + * Parameter: stream - stdio file stream + * Parameter: format - format string + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int fscanf_s(FILE *stream, const char *format, ...); +#endif + +#if SECUREC_ENABLE_VFSCANF +/* + * Description: The vfscanf_s function is equivalent to fscanf_s, with the variable argument list + * replaced by argList + * Parameter: stream - stdio file stream + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int vfscanf_s(FILE *stream, const char *format, va_list argList); +#endif + +#if SECUREC_ENABLE_STRTOK +/* + * Description: The strtok_s function parses a string into a sequence of strToken, + * replace all characters in strToken string that match to strDelimit set with 0. + * On the first call to strtok_s the string to be parsed should be specified in strToken. + * In each subsequent call that should parse the same string, strToken should be NULL + * Parameter: strToken - the string to be delimited + * Parameter: strDelimit - specifies a set of characters that delimit the tokens in the parsed string + * Parameter: context - is a pointer to a char * variable that is used internally by strtok_s function + * Return: On the first call returns the address of the first non \0 character, otherwise NULL is returned. + * In subsequent calls, the strtoken is set to NULL, and the context set is the same as the previous call, + * return NULL if the *context string length is equal 0, otherwise return *context. + */ +SECUREC_API char *strtok_s(char *strToken, const char *strDelimit, char **context); +#endif + +#if SECUREC_ENABLE_GETS && !SECUREC_IN_KERNEL +/* + * Description: The gets_s function reads at most one less than the number of characters specified + * by destMax from the stream pointed to by stdin, into the array pointed to by buffer + * Parameter: buffer - destination address + * Parameter: destMax - The maximum length of destination buffer(including the terminating null character) + * Return: buffer if there was no runtime-constraint violation,If an error occurred Return: NULL. + */ +SECUREC_API char *gets_s(char *buffer, size_t destMax); +#endif + +#if SECUREC_ENABLE_WCHAR_FUNC +#if SECUREC_ENABLE_MEMCPY +/* + * Description: The wmemcpy_s function copies n successive wide characters from the object pointed to + * by src into the object pointed to by dest. + * Parameter: dest - destination address + * Parameter: destMax - The maximum length of destination buffer + * Parameter: src - source address + * Parameter: count - copies count wide characters from the src + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t wmemcpy_s(wchar_t *dest, size_t destMax, const wchar_t *src, size_t count); +#endif + +#if SECUREC_ENABLE_MEMMOVE +/* + * Description: The wmemmove_s function copies n successive wide characters from the object + * pointed to by src into the object pointed to by dest. + * Parameter: dest - destination address + * Parameter: destMax - The maximum length of destination buffer + * Parameter: src - source address + * Parameter: count - copies count wide characters from the src + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t wmemmove_s(wchar_t *dest, size_t destMax, const wchar_t *src, size_t count); +#endif + +#if SECUREC_ENABLE_STRCPY +/* + * Description: The wcscpy_s function copies the wide string pointed to by strSrc(including the terminating + * null wide character) into the array pointed to by strDest + * Parameter: strDest - destination address + * Parameter: destMax - The maximum length of destination buffer + * Parameter: strSrc - source address + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t wcscpy_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc); +#endif + +#if SECUREC_ENABLE_STRNCPY +/* + * Description: The wcsncpy_s function copies not more than n successive wide characters (not including the + * terminating null wide character) from the array pointed to by strSrc to the array pointed to by strDest + * Parameter: strDest - destination address + * Parameter: destMax - The maximum length of destination buffer(including the terminating wide character) + * Parameter: strSrc - source address + * Parameter: count - copies count wide characters from the src + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t wcsncpy_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc, size_t count); +#endif + +#if SECUREC_ENABLE_STRCAT +/* + * Description: The wcscat_s function appends a copy of the wide string pointed to by strSrc (including the + * terminating null wide character) to the end of the wide string pointed to by strDest + * Parameter: strDest - destination address + * Parameter: destMax - The maximum length of destination buffer(including the terminating wide character) + * Parameter: strSrc - source address + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t wcscat_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc); +#endif + +#if SECUREC_ENABLE_STRNCAT +/* + * Description: The wcsncat_s function appends not more than n successive wide characters (not including the + * terminating null wide character) from the array pointed to by strSrc to the end of the wide string pointed to + * by strDest. + * Parameter: strDest - destination address + * Parameter: destMax - The maximum length of destination buffer(including the terminating wide character) + * Parameter: strSrc - source address + * Parameter: count - copies count wide characters from the src + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t wcsncat_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc, size_t count); +#endif + +#if SECUREC_ENABLE_STRTOK +/* + * Description: The wcstok_s function is the wide-character equivalent of the strtok_s function + * Parameter: strToken - the string to be delimited + * Parameter: strDelimit - specifies a set of characters that delimit the tokens in the parsed string + * Parameter: context - is a pointer to a char * variable that is used internally by strtok_s function + * Return: a pointer to the first character of a token, or a null pointer if there is no token + * or there is a runtime-constraint violation. + */ +SECUREC_API wchar_t *wcstok_s(wchar_t *strToken, const wchar_t *strDelimit, wchar_t **context); +#endif + +#if SECUREC_ENABLE_VSPRINTF +/* + * Description: The vswprintf_s function is the wide-character equivalent of the vsprintf_s function + * Parameter: strDest - produce output according to a format,write to the character string strDest + * Parameter: destMax - The maximum length of destination buffer(including the terminating null) + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of characters printed(not including the terminating null wide character), + * If an error occurred Return: -1. + */ +SECUREC_API int vswprintf_s(wchar_t *strDest, size_t destMax, const wchar_t *format, va_list argList); +#endif + +#if SECUREC_ENABLE_SPRINTF +/* + * Description: The swprintf_s function is the wide-character equivalent of the sprintf_s function + * Parameter: strDest - produce output according to a format,write to the character string strDest + * Parameter: destMax - The maximum length of destination buffer(including the terminating null) + * Parameter: format - format string + * Return: the number of characters printed(not including the terminating null wide character), + * If an error occurred Return: -1. + */ +SECUREC_API int swprintf_s(wchar_t *strDest, size_t destMax, const wchar_t *format, ...); +#endif + +#if SECUREC_ENABLE_FSCANF +/* + * Description: The fwscanf_s function is the wide-character equivalent of the fscanf_s function + * Parameter: stream - stdio file stream + * Parameter: format - format string + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int fwscanf_s(FILE *stream, const wchar_t *format, ...); +#endif + +#if SECUREC_ENABLE_VFSCANF +/* + * Description: The vfwscanf_s function is the wide-character equivalent of the vfscanf_s function + * Parameter: stream - stdio file stream + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int vfwscanf_s(FILE *stream, const wchar_t *format, va_list argList); +#endif + +#if SECUREC_ENABLE_SCANF +/* + * Description: The wscanf_s function is the wide-character equivalent of the scanf_s function + * Parameter: format - format string + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int wscanf_s(const wchar_t *format, ...); +#endif + +#if SECUREC_ENABLE_VSCANF +/* + * Description: The vwscanf_s function is the wide-character equivalent of the vscanf_s function + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int vwscanf_s(const wchar_t *format, va_list argList); +#endif + +#if SECUREC_ENABLE_SSCANF +/* + * Description: The swscanf_s function is the wide-character equivalent of the sscanf_s function + * Parameter: buffer - read character from buffer + * Parameter: format - format string + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int swscanf_s(const wchar_t *buffer, const wchar_t *format, ...); +#endif + +#if SECUREC_ENABLE_VSSCANF +/* + * Description: The vswscanf_s function is the wide-character equivalent of the vsscanf_s function + * Parameter: buffer - read character from buffer + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int vswscanf_s(const wchar_t *buffer, const wchar_t *format, va_list argList); +#endif +#endif /* SECUREC_ENABLE_WCHAR_FUNC */ +#endif + +/* Those functions are used by macro,must declare hare, also for without function declaration warning */ +extern errno_t strncpy_error(char *strDest, size_t destMax, const char *strSrc, size_t count); +extern errno_t strcpy_error(char *strDest, size_t destMax, const char *strSrc); + +#if SECUREC_WITH_PERFORMANCE_ADDONS +/* Those functions are used by macro */ +extern errno_t memset_sOptAsm(void *dest, size_t destMax, int c, size_t count); +extern errno_t memset_sOptTc(void *dest, size_t destMax, int c, size_t count); +extern errno_t memcpy_sOptAsm(void *dest, size_t destMax, const void *src, size_t count); +extern errno_t memcpy_sOptTc(void *dest, size_t destMax, const void *src, size_t count); + +/* The strcpy_sp is a macro, not a function in performance optimization mode. */ +#define strcpy_sp(dest, destMax, src) ((__builtin_constant_p((destMax)) && \ + __builtin_constant_p((src))) ? \ + SECUREC_STRCPY_SM((dest), (destMax), (src)) : \ + strcpy_s((dest), (destMax), (src))) + +/* The strncpy_sp is a macro, not a function in performance optimization mode. */ +#define strncpy_sp(dest, destMax, src, count) ((__builtin_constant_p((count)) && \ + __builtin_constant_p((destMax)) && \ + __builtin_constant_p((src))) ? \ + SECUREC_STRNCPY_SM((dest), (destMax), (src), (count)) : \ + strncpy_s((dest), (destMax), (src), (count))) + +/* The strcat_sp is a macro, not a function in performance optimization mode. */ +#define strcat_sp(dest, destMax, src) ((__builtin_constant_p((destMax)) && \ + __builtin_constant_p((src))) ? \ + SECUREC_STRCAT_SM((dest), (destMax), (src)) : \ + strcat_s((dest), (destMax), (src))) + +/* The strncat_sp is a macro, not a function in performance optimization mode. */ +#define strncat_sp(dest, destMax, src, count) ((__builtin_constant_p((count)) && \ + __builtin_constant_p((destMax)) && \ + __builtin_constant_p((src))) ? \ + SECUREC_STRNCAT_SM((dest), (destMax), (src), (count)) : \ + strncat_s((dest), (destMax), (src), (count))) + +/* The memcpy_sp is a macro, not a function in performance optimization mode. */ +#define memcpy_sp(dest, destMax, src, count) (__builtin_constant_p((count)) ? \ + (SECUREC_MEMCPY_SM((dest), (destMax), (src), (count))) : \ + (__builtin_constant_p((destMax)) ? \ + (((size_t)(destMax) > 0 && \ + (((unsigned long long)(destMax) & (unsigned long long)(-2)) < SECUREC_MEM_MAX_LEN)) ? \ + memcpy_sOptTc((dest), (destMax), (src), (count)) : ERANGE) : \ + memcpy_sOptAsm((dest), (destMax), (src), (count)))) + +/* The memset_sp is a macro, not a function in performance optimization mode. */ +#define memset_sp(dest, destMax, c, count) (__builtin_constant_p((count)) ? \ + (SECUREC_MEMSET_SM((dest), (destMax), (c), (count))) : \ + (__builtin_constant_p((destMax)) ? \ + (((((unsigned long long)(destMax) & (unsigned long long)(-2)) < SECUREC_MEM_MAX_LEN)) ? \ + memset_sOptTc((dest), (destMax), (c), (count)) : ERANGE) : \ + memset_sOptAsm((dest), (destMax), (c), (count)))) + +#endif + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/include/securectype.h b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/include/securectype.h new file mode 100644 index 0000000000000000000000000000000000000000..69e79c2f9013e38bf42e87633f9bb3f16c930de8 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/include/securectype.h @@ -0,0 +1,585 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: Define internal used macro and data type. The marco of SECUREC_ON_64BITS + * will be determined in this header file, which is a switch for part + * of code. Some macro are used to suppress warning by MS compiler. + * Create: 2014-02-25 + * Notes: User can change the value of SECUREC_STRING_MAX_LEN and SECUREC_MEM_MAX_LEN + * macro to meet their special need, but The maximum value should not exceed 2G. + */ +/* + * [Standardize-exceptions]: Performance-sensitive + * [reason]: Strict parameter verification has been done before use + */ + +#ifndef SECURECTYPE_H_A7BBB686_AADA_451B_B9F9_44DACDAE18A7 +#define SECURECTYPE_H_A7BBB686_AADA_451B_B9F9_44DACDAE18A7 + +#ifndef SECUREC_USING_STD_SECURE_LIB +#if defined(_MSC_VER) && _MSC_VER >= 1400 +#if defined(__STDC_WANT_SECURE_LIB__) && (!__STDC_WANT_SECURE_LIB__) +/* Security functions have been provided since vs2005, default use of system library functions */ +#define SECUREC_USING_STD_SECURE_LIB 0 +#else +#define SECUREC_USING_STD_SECURE_LIB 1 +#endif +#else +#define SECUREC_USING_STD_SECURE_LIB 0 +#endif +#endif + +/* Compatibility with older Secure C versions, shielding VC symbol redefinition warning */ +#if defined(_MSC_VER) && (_MSC_VER >= 1400) && (!SECUREC_USING_STD_SECURE_LIB) +#ifndef SECUREC_DISABLE_CRT_FUNC +#define SECUREC_DISABLE_CRT_FUNC 1 +#endif +#ifndef SECUREC_DISABLE_CRT_IMP +#define SECUREC_DISABLE_CRT_IMP 1 +#endif +#else /* MSC VER */ +#ifndef SECUREC_DISABLE_CRT_FUNC +#define SECUREC_DISABLE_CRT_FUNC 0 +#endif +#ifndef SECUREC_DISABLE_CRT_IMP +#define SECUREC_DISABLE_CRT_IMP 0 +#endif +#endif + +#if SECUREC_DISABLE_CRT_FUNC +#ifdef __STDC_WANT_SECURE_LIB__ +#undef __STDC_WANT_SECURE_LIB__ +#endif +#define __STDC_WANT_SECURE_LIB__ 0 +#endif + +#if SECUREC_DISABLE_CRT_IMP +#ifdef _CRTIMP_ALTERNATIVE +#undef _CRTIMP_ALTERNATIVE +#endif +#define _CRTIMP_ALTERNATIVE /* Comment Microsoft *_s function */ +#endif + +/* Compile in kernel under macro control */ +#ifndef SECUREC_IN_KERNEL +#ifdef __KERNEL__ +#define SECUREC_IN_KERNEL 1 +#else +#define SECUREC_IN_KERNEL 0 +#endif +#endif + +/* make kernel symbols of functions available to loadable modules */ +#ifndef SECUREC_EXPORT_KERNEL_SYMBOL +#if SECUREC_IN_KERNEL +#define SECUREC_EXPORT_KERNEL_SYMBOL 1 +#else +#define SECUREC_EXPORT_KERNEL_SYMBOL 0 +#endif +#endif + +#if SECUREC_IN_KERNEL +#ifndef SECUREC_ENABLE_SCANF_FILE +#define SECUREC_ENABLE_SCANF_FILE 0 +#endif +#ifndef SECUREC_ENABLE_WCHAR_FUNC +#define SECUREC_ENABLE_WCHAR_FUNC 0 +#endif +#else /* SECUREC_IN_KERNEL */ +#ifndef SECUREC_ENABLE_SCANF_FILE +#define SECUREC_ENABLE_SCANF_FILE 1 +#endif +#ifndef SECUREC_ENABLE_WCHAR_FUNC +#define SECUREC_ENABLE_WCHAR_FUNC 1 +#endif +#endif + +/* Default secure function declaration, default declarations for non-standard functions */ +#ifndef SECUREC_SNPRINTF_TRUNCATED +#define SECUREC_SNPRINTF_TRUNCATED 1 +#endif + +#if SECUREC_USING_STD_SECURE_LIB +#if defined(_MSC_VER) && _MSC_VER >= 1400 +/* Declare secure functions that are not available in the VS compiler */ +#ifndef SECUREC_ENABLE_MEMSET +#define SECUREC_ENABLE_MEMSET 1 +#endif +/* VS 2005 have vsnprintf_s function */ +#ifndef SECUREC_ENABLE_VSNPRINTF +#define SECUREC_ENABLE_VSNPRINTF 0 +#endif +#ifndef SECUREC_ENABLE_SNPRINTF +/* VS 2005 have vsnprintf_s function Adapt the snprintf_s of the security function */ +#define snprintf_s _snprintf_s +#define SECUREC_ENABLE_SNPRINTF 0 +#endif +/* Before VS 2010 do not have v functions */ +#if _MSC_VER <= 1600 || defined(SECUREC_FOR_V_SCANFS) +#ifndef SECUREC_ENABLE_VFSCANF +#define SECUREC_ENABLE_VFSCANF 1 +#endif +#ifndef SECUREC_ENABLE_VSCANF +#define SECUREC_ENABLE_VSCANF 1 +#endif +#ifndef SECUREC_ENABLE_VSSCANF +#define SECUREC_ENABLE_VSSCANF 1 +#endif +#endif + +#else /* MSC VER */ +#ifndef SECUREC_ENABLE_MEMSET +#define SECUREC_ENABLE_MEMSET 0 +#endif +#ifndef SECUREC_ENABLE_SNPRINTF +#define SECUREC_ENABLE_SNPRINTF 0 +#endif +#ifndef SECUREC_ENABLE_VSNPRINTF +#define SECUREC_ENABLE_VSNPRINTF 0 +#endif +#endif + +#ifndef SECUREC_ENABLE_MEMMOVE +#define SECUREC_ENABLE_MEMMOVE 0 +#endif +#ifndef SECUREC_ENABLE_MEMCPY +#define SECUREC_ENABLE_MEMCPY 0 +#endif +#ifndef SECUREC_ENABLE_STRCPY +#define SECUREC_ENABLE_STRCPY 0 +#endif +#ifndef SECUREC_ENABLE_STRNCPY +#define SECUREC_ENABLE_STRNCPY 0 +#endif +#ifndef SECUREC_ENABLE_STRCAT +#define SECUREC_ENABLE_STRCAT 0 +#endif +#ifndef SECUREC_ENABLE_STRNCAT +#define SECUREC_ENABLE_STRNCAT 0 +#endif +#ifndef SECUREC_ENABLE_SPRINTF +#define SECUREC_ENABLE_SPRINTF 0 +#endif +#ifndef SECUREC_ENABLE_VSPRINTF +#define SECUREC_ENABLE_VSPRINTF 0 +#endif +#ifndef SECUREC_ENABLE_SSCANF +#define SECUREC_ENABLE_SSCANF 0 +#endif +#ifndef SECUREC_ENABLE_VSSCANF +#define SECUREC_ENABLE_VSSCANF 0 +#endif +#ifndef SECUREC_ENABLE_SCANF +#define SECUREC_ENABLE_SCANF 0 +#endif +#ifndef SECUREC_ENABLE_VSCANF +#define SECUREC_ENABLE_VSCANF 0 +#endif + +#ifndef SECUREC_ENABLE_FSCANF +#define SECUREC_ENABLE_FSCANF 0 +#endif +#ifndef SECUREC_ENABLE_VFSCANF +#define SECUREC_ENABLE_VFSCANF 0 +#endif +#ifndef SECUREC_ENABLE_STRTOK +#define SECUREC_ENABLE_STRTOK 0 +#endif +#ifndef SECUREC_ENABLE_GETS +#define SECUREC_ENABLE_GETS 0 +#endif + +#else /* SECUREC USE STD SECURE LIB */ + +#ifndef SECUREC_ENABLE_MEMSET +#define SECUREC_ENABLE_MEMSET 1 +#endif +#ifndef SECUREC_ENABLE_MEMMOVE +#define SECUREC_ENABLE_MEMMOVE 1 +#endif +#ifndef SECUREC_ENABLE_MEMCPY +#define SECUREC_ENABLE_MEMCPY 1 +#endif +#ifndef SECUREC_ENABLE_STRCPY +#define SECUREC_ENABLE_STRCPY 1 +#endif +#ifndef SECUREC_ENABLE_STRNCPY +#define SECUREC_ENABLE_STRNCPY 1 +#endif +#ifndef SECUREC_ENABLE_STRCAT +#define SECUREC_ENABLE_STRCAT 1 +#endif +#ifndef SECUREC_ENABLE_STRNCAT +#define SECUREC_ENABLE_STRNCAT 1 +#endif +#ifndef SECUREC_ENABLE_SPRINTF +#define SECUREC_ENABLE_SPRINTF 1 +#endif +#ifndef SECUREC_ENABLE_VSPRINTF +#define SECUREC_ENABLE_VSPRINTF 1 +#endif +#ifndef SECUREC_ENABLE_SNPRINTF +#define SECUREC_ENABLE_SNPRINTF 1 +#endif +#ifndef SECUREC_ENABLE_VSNPRINTF +#define SECUREC_ENABLE_VSNPRINTF 1 +#endif +#ifndef SECUREC_ENABLE_SSCANF +#define SECUREC_ENABLE_SSCANF 1 +#endif +#ifndef SECUREC_ENABLE_VSSCANF +#define SECUREC_ENABLE_VSSCANF 1 +#endif +#ifndef SECUREC_ENABLE_SCANF +#if SECUREC_ENABLE_SCANF_FILE +#define SECUREC_ENABLE_SCANF 1 +#else +#define SECUREC_ENABLE_SCANF 0 +#endif +#endif +#ifndef SECUREC_ENABLE_VSCANF +#if SECUREC_ENABLE_SCANF_FILE +#define SECUREC_ENABLE_VSCANF 1 +#else +#define SECUREC_ENABLE_VSCANF 0 +#endif +#endif + +#ifndef SECUREC_ENABLE_FSCANF +#if SECUREC_ENABLE_SCANF_FILE +#define SECUREC_ENABLE_FSCANF 1 +#else +#define SECUREC_ENABLE_FSCANF 0 +#endif +#endif +#ifndef SECUREC_ENABLE_VFSCANF +#if SECUREC_ENABLE_SCANF_FILE +#define SECUREC_ENABLE_VFSCANF 1 +#else +#define SECUREC_ENABLE_VFSCANF 0 +#endif +#endif + +#ifndef SECUREC_ENABLE_STRTOK +#define SECUREC_ENABLE_STRTOK 1 +#endif +#ifndef SECUREC_ENABLE_GETS +#define SECUREC_ENABLE_GETS 1 +#endif +#endif /* SECUREC_USE_STD_SECURE_LIB */ + +#if !SECUREC_ENABLE_SCANF_FILE +#if SECUREC_ENABLE_FSCANF +#undef SECUREC_ENABLE_FSCANF +#define SECUREC_ENABLE_FSCANF 0 +#endif +#if SECUREC_ENABLE_VFSCANF +#undef SECUREC_ENABLE_VFSCANF +#define SECUREC_ENABLE_VFSCANF 0 +#endif +#if SECUREC_ENABLE_SCANF +#undef SECUREC_ENABLE_SCANF +#define SECUREC_ENABLE_SCANF 0 +#endif +#if SECUREC_ENABLE_FSCANF +#undef SECUREC_ENABLE_FSCANF +#define SECUREC_ENABLE_FSCANF 0 +#endif + +#endif + +#if SECUREC_IN_KERNEL +#include +#include +#else +#ifndef SECUREC_HAVE_STDIO_H +#define SECUREC_HAVE_STDIO_H 1 +#endif +#ifndef SECUREC_HAVE_STRING_H +#define SECUREC_HAVE_STRING_H 1 +#endif +#ifndef SECUREC_HAVE_STDLIB_H +#define SECUREC_HAVE_STDLIB_H 1 +#endif +#if SECUREC_HAVE_STDIO_H +#include +#endif +#if SECUREC_HAVE_STRING_H +#include +#endif +#if SECUREC_HAVE_STDLIB_H +#include +#endif +#endif + +/* + * If you need high performance, enable the SECUREC_WITH_PERFORMANCE_ADDONS macro, default is enable. + * The macro is automatically closed on the windows platform and linux kernel + */ +#ifndef SECUREC_WITH_PERFORMANCE_ADDONS +#if SECUREC_IN_KERNEL +#define SECUREC_WITH_PERFORMANCE_ADDONS 0 +#else +#define SECUREC_WITH_PERFORMANCE_ADDONS 1 +#endif +#endif + +/* If enable SECUREC_COMPATIBLE_WIN_FORMAT, the output format will be compatible to Windows. */ +#if (defined(_WIN32) || defined(_WIN64) || defined(_MSC_VER)) && !defined(SECUREC_COMPATIBLE_LINUX_FORMAT) +#ifndef SECUREC_COMPATIBLE_WIN_FORMAT +#define SECUREC_COMPATIBLE_WIN_FORMAT +#endif +#endif + +#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) +/* On windows platform, can't use optimized function for there is no __builtin_constant_p like function */ +/* If need optimized macro, can define this: define __builtin_constant_p(x) 0 */ +#ifdef SECUREC_WITH_PERFORMANCE_ADDONS +#undef SECUREC_WITH_PERFORMANCE_ADDONS +#define SECUREC_WITH_PERFORMANCE_ADDONS 0 +#endif +#endif + +#if defined(__VXWORKS__) || defined(__vxworks) || defined(__VXWORKS) || defined(_VXWORKS_PLATFORM_) || \ + defined(SECUREC_VXWORKS_VERSION_5_4) +#ifndef SECUREC_VXWORKS_PLATFORM +#define SECUREC_VXWORKS_PLATFORM +#endif +#endif + +/* If enable SECUREC_COMPATIBLE_LINUX_FORMAT, the output format will be compatible to Linux. */ +#if !defined(SECUREC_COMPATIBLE_WIN_FORMAT) && !defined(SECUREC_VXWORKS_PLATFORM) +#ifndef SECUREC_COMPATIBLE_LINUX_FORMAT +#define SECUREC_COMPATIBLE_LINUX_FORMAT +#endif +#endif + +#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT +#ifndef SECUREC_HAVE_STDDEF_H +#define SECUREC_HAVE_STDDEF_H 1 +#endif +/* Some system may no stddef.h */ +#if SECUREC_HAVE_STDDEF_H +#if !SECUREC_IN_KERNEL +#include +#endif +#endif +#endif + +/* + * Add the -DSECUREC_SUPPORT_FORMAT_WARNING=1 compiler option to supoort -Wformat=2. + * Default does not check the format is that the same data type in the actual code. + * In the product is different in the original data type definition of VxWorks and Linux. + */ +#ifndef SECUREC_SUPPORT_FORMAT_WARNING +#define SECUREC_SUPPORT_FORMAT_WARNING 0 +#endif + +#if SECUREC_SUPPORT_FORMAT_WARNING +#define SECUREC_ATTRIBUTE(x, y) __attribute__((format(printf, (x), (y)))) +#else +#define SECUREC_ATTRIBUTE(x, y) +#endif + +/* + * Add the -DSECUREC_SUPPORT_BUILTIN_EXPECT=0 compiler option, if compiler can not support __builtin_expect. + */ +#ifndef SECUREC_SUPPORT_BUILTIN_EXPECT +#define SECUREC_SUPPORT_BUILTIN_EXPECT 1 +#endif + +#if SECUREC_SUPPORT_BUILTIN_EXPECT && defined(__GNUC__) && ((__GNUC__ > 3) || \ + (defined(__GNUC_MINOR__) && (__GNUC__ == 3 && __GNUC_MINOR__ > 3))) +/* + * This is a built-in function that can be used without a declaration, if warning for declaration not found occurred, + * you can add -DSECUREC_NEED_BUILTIN_EXPECT_DECLARE to compiler options + */ +#ifdef SECUREC_NEED_BUILTIN_EXPECT_DECLARE +long __builtin_expect(long exp, long c); +#endif + +#define SECUREC_LIKELY(x) __builtin_expect(!!(x), 1) +#define SECUREC_UNLIKELY(x) __builtin_expect(!!(x), 0) +#else +#define SECUREC_LIKELY(x) (x) +#define SECUREC_UNLIKELY(x) (x) +#endif + +/* Define the max length of the string */ +#ifndef SECUREC_STRING_MAX_LEN +#define SECUREC_STRING_MAX_LEN 0x7fffffffUL +#endif +#define SECUREC_WCHAR_STRING_MAX_LEN (SECUREC_STRING_MAX_LEN / sizeof(wchar_t)) + +/* Add SECUREC_MEM_MAX_LEN for memcpy and memmove */ +#ifndef SECUREC_MEM_MAX_LEN +#define SECUREC_MEM_MAX_LEN 0x7fffffffUL +#endif +#define SECUREC_WCHAR_MEM_MAX_LEN (SECUREC_MEM_MAX_LEN / sizeof(wchar_t)) + +#if SECUREC_STRING_MAX_LEN > 0x7fffffffUL +#error "max string is 2G" +#endif + +#if (defined(__GNUC__) && defined(__SIZEOF_POINTER__)) +#if (__SIZEOF_POINTER__ != 4) && (__SIZEOF_POINTER__ != 8) +#error "unsupported system" +#endif +#endif + +#if defined(_WIN64) || defined(WIN64) || defined(__LP64__) || defined(_LP64) +#define SECUREC_ON_64BITS +#endif + +#if (!defined(SECUREC_ON_64BITS) && defined(__GNUC__) && defined(__SIZEOF_POINTER__)) +#if __SIZEOF_POINTER__ == 8 +#define SECUREC_ON_64BITS +#endif +#endif + +#if defined(__SVR4) || defined(__svr4__) +#define SECUREC_ON_SOLARIS +#endif + +#if (defined(__hpux) || defined(_AIX) || defined(SECUREC_ON_SOLARIS)) +#define SECUREC_ON_UNIX +#endif + +/* + * Codes should run under the macro SECUREC_COMPATIBLE_LINUX_FORMAT in unknown system on default, + * and strtold. + * The function strtold is referenced first at ISO9899:1999(C99), and some old compilers can + * not support these functions. Here provides a macro to open these functions: + * SECUREC_SUPPORT_STRTOLD -- If defined, strtold will be used + */ +#ifndef SECUREC_SUPPORT_STRTOLD +#define SECUREC_SUPPORT_STRTOLD 0 +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT)) +#if defined(__USE_ISOC99) || \ + (defined(_AIX) && defined(_ISOC99_SOURCE)) || \ + (defined(__hpux) && defined(__ia64)) || \ + (defined(SECUREC_ON_SOLARIS) && (!defined(_STRICT_STDC) && !defined(__XOPEN_OR_POSIX)) || \ + defined(_STDC_C99) || defined(__EXTENSIONS__)) +#undef SECUREC_SUPPORT_STRTOLD +#define SECUREC_SUPPORT_STRTOLD 1 +#endif +#endif +#if ((defined(SECUREC_WRLINUX_BELOW4) || defined(_WRLINUX_BELOW4_))) +#undef SECUREC_SUPPORT_STRTOLD +#define SECUREC_SUPPORT_STRTOLD 0 +#endif +#endif + +#if SECUREC_WITH_PERFORMANCE_ADDONS + +#ifndef SECUREC_TWO_MIN +#define SECUREC_TWO_MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +/* For strncpy_s performance optimization */ +#define SECUREC_STRNCPY_SM(dest, destMax, src, count) \ + (((void *)(dest) != NULL && (const void *)(src) != NULL && (size_t)(destMax) > 0 && \ + (((unsigned long long)(destMax) & (unsigned long long)(-2)) < SECUREC_STRING_MAX_LEN) && \ + (SECUREC_TWO_MIN((size_t)(count), strlen(src)) + 1) <= (size_t)(destMax)) ? \ + (((size_t)(count) < strlen(src)) ? (memcpy((dest), (src), (count)), *((char *)(dest) + (count)) = '\0', EOK) : \ + (memcpy((dest), (src), strlen(src) + 1), EOK)) : (strncpy_error((dest), (destMax), (src), (count)))) + +#define SECUREC_STRCPY_SM(dest, destMax, src) \ + (((void *)(dest) != NULL && (const void *)(src) != NULL && (size_t)(destMax) > 0 && \ + (((unsigned long long)(destMax) & (unsigned long long)(-2)) < SECUREC_STRING_MAX_LEN) && \ + (strlen(src) + 1) <= (size_t)(destMax)) ? (memcpy((dest), (src), strlen(src) + 1), EOK) : \ + (strcpy_error((dest), (destMax), (src)))) + +/* For strcat_s performance optimization */ +#if defined(__GNUC__) +#define SECUREC_STRCAT_SM(dest, destMax, src) ({ \ + int catRet_ = EOK; \ + if ((void *)(dest) != NULL && (const void *)(src) != NULL && (size_t)(destMax) > 0 && \ + (((unsigned long long)(destMax) & (unsigned long long)(-2)) < SECUREC_STRING_MAX_LEN)) { \ + char *catTmpDst_ = (char *)(dest); \ + size_t catRestSize_ = (destMax); \ + while (catRestSize_ > 0 && *catTmpDst_ != '\0') { \ + ++catTmpDst_; \ + --catRestSize_; \ + } \ + if (catRestSize_ == 0) { \ + catRet_ = EINVAL; \ + } else if ((strlen(src) + 1) <= catRestSize_) { \ + memcpy(catTmpDst_, (src), strlen(src) + 1); \ + catRet_ = EOK; \ + } else { \ + catRet_ = ERANGE; \ + } \ + if (catRet_ != EOK) { \ + catRet_ = strcat_s((dest), (destMax), (src)); \ + } \ + } else { \ + catRet_ = strcat_s((dest), (destMax), (src)); \ + } \ + catRet_; \ +}) +#else +#define SECUREC_STRCAT_SM(dest, destMax, src) strcat_s((dest), (destMax), (src)) +#endif + +/* For strncat_s performance optimization */ +#if defined(__GNUC__) +#define SECUREC_STRNCAT_SM(dest, destMax, src, count) ({ \ + int ncatRet_ = EOK; \ + if ((void *)(dest) != NULL && (const void *)(src) != NULL && (size_t)(destMax) > 0 && \ + (((unsigned long long)(destMax) & (unsigned long long)(-2)) < SECUREC_STRING_MAX_LEN) && \ + (((unsigned long long)(count) & (unsigned long long)(-2)) < SECUREC_STRING_MAX_LEN)) { \ + char *ncatTmpDest_ = (char *)(dest); \ + size_t ncatRestSize_ = (size_t)(destMax); \ + while (ncatRestSize_ > 0 && *ncatTmpDest_ != '\0') { \ + ++ncatTmpDest_; \ + --ncatRestSize_; \ + } \ + if (ncatRestSize_ == 0) { \ + ncatRet_ = EINVAL; \ + } else if ((SECUREC_TWO_MIN((count), strlen(src)) + 1) <= ncatRestSize_) { \ + if ((size_t)(count) < strlen(src)) { \ + memcpy(ncatTmpDest_, (src), (count)); \ + *(ncatTmpDest_ + (count)) = '\0'; \ + } else { \ + memcpy(ncatTmpDest_, (src), strlen(src) + 1); \ + } \ + } else { \ + ncatRet_ = ERANGE; \ + } \ + if (ncatRet_ != EOK) { \ + ncatRet_ = strncat_s((dest), (destMax), (src), (count)); \ + } \ + } else { \ + ncatRet_ = strncat_s((dest), (destMax), (src), (count)); \ + } \ + ncatRet_; \ +}) +#else +#define SECUREC_STRNCAT_SM(dest, destMax, src, count) strncat_s((dest), (destMax), (src), (count)) +#endif + +/* This macro do not check buffer overlap by default */ +#define SECUREC_MEMCPY_SM(dest, destMax, src, count) \ + (!(((size_t)(destMax) == 0) || \ + (((unsigned long long)(destMax) & (unsigned long long)(-2)) > SECUREC_MEM_MAX_LEN) || \ + ((size_t)(count) > (size_t)(destMax)) || ((void *)(dest)) == NULL || ((const void *)(src) == NULL)) ? \ + (memcpy((dest), (src), (count)), EOK) : \ + (memcpy_s((dest), (destMax), (src), (count)))) + +#define SECUREC_MEMSET_SM(dest, destMax, c, count) \ + (!((((unsigned long long)(destMax) & (unsigned long long)(-2)) > SECUREC_MEM_MAX_LEN) || \ + ((void *)(dest) == NULL) || ((size_t)(count) > (size_t)(destMax))) ? \ + (memset((dest), (c), (count)), EOK) : \ + (memset_s((dest), (destMax), (c), (count)))) + +#endif +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/fscanf_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/fscanf_s.c new file mode 100644 index 0000000000000000000000000000000000000000..d3c7f06c12e730ae5576cefee203b87c23a887c5 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/fscanf_s.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: fscanf_s function + * Create: 2014-02-25 + */ + +#include "securec.h" + +/* + * + * The fscanf_s function is equivalent to fscanf except that the c, s, + * and [ conversion specifiers apply to a pair of arguments (unless assignment suppression is indicated by a*) + * The fscanf function reads data from the current position of stream into + * the locations given by argument (if any). Each argument must be a pointer + * to a variable of a type that corresponds to a type specifier in format. + * format controls the interpretation of the input fields and has the same + * form and function as the format argument for scanf. + * + * + * stream Pointer to FILE structure. + * format Format control string, see Format Specifications. + * ... Optional arguments. + * + * + * ... The converted value stored in user assigned address + * + * + * Each of these functions returns the number of fields successfully converted + * and assigned; the return value does not include fields that were read but + * not assigned. A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int fscanf_s(FILE *stream, const char *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vfscanf_s(stream, format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/fwscanf_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/fwscanf_s.c new file mode 100644 index 0000000000000000000000000000000000000000..bd0f12a966ade1359f4e19e60ec840a283a6d534 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/fwscanf_s.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: fwscanf_s function + * Create: 2014-02-25 + */ + +#include "securec.h" + +/* + * + * The fwscanf_s function is the wide-character equivalent of the fscanf_s function + * The fwscanf_s function reads data from the current position of stream into + * the locations given by argument (if any). Each argument must be a pointer + * to a variable of a type that corresponds to a type specifier in format. + * format controls the interpretation of the input fields and has the same + * form and function as the format argument for scanf. + * + * + * stream Pointer to FILE structure. + * format Format control string, see Format Specifications. + * ... Optional arguments. + * + * + * ... The converted value stored in user assigned address + * + * + * Each of these functions returns the number of fields successfully converted + * and assigned; the return value does not include fields that were read but + * not assigned. A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int fwscanf_s(FILE *stream, const wchar_t *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vfwscanf_s(stream, format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/gets_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/gets_s.c new file mode 100644 index 0000000000000000000000000000000000000000..d12495aa08e514f81c30a5ba42115b99f3412083 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/gets_s.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: gets_s function + * Create: 2014-02-25 + */ + +#include "securecutil.h" + +/* + * The parameter size is buffer size in byte + */ +SECUREC_INLINE void SecTrimCRLF(char *buffer, size_t size) +{ + size_t len = strlen(buffer); + --len; /* Unsigned integer wrapping is accepted and is checked afterwards */ + while (len < size && (buffer[len] == '\r' || buffer[len] == '\n')) { + buffer[len] = '\0'; + --len; /* Unsigned integer wrapping is accepted and is checked next loop */ + } +} + +/* + * + * The gets_s function reads at most one less than the number of characters + * specified by destMax from the std input stream, into the array pointed to by buffer + * The line consists of all characters up to and including + * the first newline character ('\n'). gets_s then replaces the newline + * character with a null character ('\0') before returning the line. + * If the first character read is the end-of-file character, a null character + * is stored at the beginning of buffer and NULL is returned. + * + * + * buffer Storage location for input string. + * destMax The size of the buffer. + * + * + * buffer is updated + * + * + * buffer Successful operation + * NULL Improper parameter or read fail + */ +char *gets_s(char *buffer, size_t destMax) +{ +#ifdef SECUREC_COMPATIBLE_WIN_FORMAT + size_t bufferSize = ((destMax == (size_t)(-1)) ? SECUREC_STRING_MAX_LEN : destMax); +#else + size_t bufferSize = destMax; +#endif + + if (buffer == NULL || bufferSize == 0 || bufferSize > SECUREC_STRING_MAX_LEN) { + SECUREC_ERROR_INVALID_PARAMTER("gets_s"); + return NULL; + } + + if (fgets(buffer, (int)bufferSize, SECUREC_STREAM_STDIN) != NULL) { + SecTrimCRLF(buffer, bufferSize); + return buffer; + } + + return NULL; +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/input.inl b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/input.inl new file mode 100644 index 0000000000000000000000000000000000000000..41d401cfd2e80e3b05a6b0623f0f2e85db6a16f5 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/input.inl @@ -0,0 +1,2229 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: Used by secureinput_a.c and secureinput_w.c to include. + * This file provides a template function for ANSI and UNICODE compiling by + * different type definition. The functions of SecInputS or + * SecInputSW provides internal implementation for scanf family API, such as sscanf_s, fscanf_s. + * Create: 2014-02-25 + * Notes: The formatted input processing results of integers on different platforms are different. + */ +/* + * [Standardize-exceptions] Use unsafe function: Performance-sensitive + * [reason] Always used in the performance critical path, + * and sufficient input validation is performed before calling + */ +#ifndef INPUT_INL_5D13A042_DC3F_4ED9_A8D1_882811274C27 +#define INPUT_INL_5D13A042_DC3F_4ED9_A8D1_882811274C27 + +#if SECUREC_IN_KERNEL +#if !defined(SECUREC_CTYPE_MACRO_ADAPT) +#include +#endif +#else +#if !defined(SECUREC_SYSAPI4VXWORKS) && !defined(SECUREC_CTYPE_MACRO_ADAPT) +#include +#ifdef SECUREC_FOR_WCHAR +#include /* For iswspace */ +#endif +#endif +#endif + +#ifndef EOF +#define EOF (-1) +#endif + +#define SECUREC_NUM_WIDTH_SHORT 0 +#define SECUREC_NUM_WIDTH_INT 1 +#define SECUREC_NUM_WIDTH_LONG 2 +#define SECUREC_NUM_WIDTH_LONG_LONG 3 /* Also long double */ + +#define SECUREC_BUFFERED_BLOK_SIZE 1024U + +#if defined(SECUREC_VXWORKS_PLATFORM) && !defined(va_copy) && !defined(__va_copy) +/* The name is the same as system macro. */ +#define __va_copy(dest, src) do { \ + size_t destSize_ = (size_t)sizeof(dest); \ + size_t srcSize_ = (size_t)sizeof(src); \ + if (destSize_ != srcSize_) { \ + SECUREC_MEMCPY_WARP_OPT((dest), (src), sizeof(va_list)); \ + } else { \ + SECUREC_MEMCPY_WARP_OPT(&(dest), &(src), sizeof(va_list)); \ + } \ +} SECUREC_WHILE_ZERO +#endif + +#define SECUREC_MULTI_BYTE_MAX_LEN 6 + +/* Compatibility macro name cannot be modifie */ +#ifndef UNALIGNED +#if !(defined(_M_IA64)) && !(defined(_M_AMD64)) +#define UNALIGNED +#else +#define UNALIGNED __unaligned +#endif +#endif + +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) +/* Max 64bit value is 0xffffffffffffffff */ +#define SECUREC_MAX_64BITS_VALUE 18446744073709551615ULL +#define SECUREC_MAX_64BITS_VALUE_DIV_TEN 1844674407370955161ULL +#define SECUREC_MAX_64BITS_VALUE_CUT_LAST_DIGIT 18446744073709551610ULL +#define SECUREC_MIN_64BITS_NEG_VALUE 9223372036854775808ULL +#define SECUREC_MAX_64BITS_POS_VALUE 9223372036854775807ULL +#define SECUREC_MIN_32BITS_NEG_VALUE 2147483648UL +#define SECUREC_MAX_32BITS_POS_VALUE 2147483647UL +#define SECUREC_MAX_32BITS_VALUE 4294967295UL +#define SECUREC_MAX_32BITS_VALUE_INC 4294967296UL +#define SECUREC_MAX_32BITS_VALUE_DIV_TEN 429496729UL +#define SECUREC_LONG_BIT_NUM ((unsigned int)(sizeof(long) << 3U)) +/* Use ULL to clean up cl6x compilation alerts */ +#define SECUREC_MAX_LONG_POS_VALUE ((unsigned long)(1ULL << (SECUREC_LONG_BIT_NUM - 1)) - 1) +#define SECUREC_MIN_LONG_NEG_VALUE ((unsigned long)(1ULL << (SECUREC_LONG_BIT_NUM - 1))) + +/* Covert to long long to clean up cl6x compilation alerts */ +#define SECUREC_LONG_HEX_BEYOND_MAX(number) (((unsigned long long)(number) >> (SECUREC_LONG_BIT_NUM - 4U)) > 0) +#define SECUREC_LONG_OCTAL_BEYOND_MAX(number) (((unsigned long long)(number) >> (SECUREC_LONG_BIT_NUM - 3U)) > 0) + +#define SECUREC_QWORD_HEX_BEYOND_MAX(number) (((number) >> (64U - 4U)) > 0) +#define SECUREC_QWORD_OCTAL_BEYOND_MAX(number) (((number) >> (64U - 3U)) > 0) + +#define SECUREC_LP64_BIT_WIDTH 64 +#define SECUREC_LP32_BIT_WIDTH 32 + +#define SECUREC_CONVERT_IS_SIGNED(conv) ((conv) == 'd' || (conv) == 'i') +#endif + +#define SECUREC_BRACE '{' /* [ to { */ +#define SECUREC_FILED_WIDTH_ENOUGH(spec) ((spec)->widthSet == 0 || (spec)->width > 0) +#define SECUREC_FILED_WIDTH_DEC(spec) do { \ + if ((spec)->widthSet != 0) { \ + --(spec)->width; \ + } \ +} SECUREC_WHILE_ZERO + +#ifdef SECUREC_FOR_WCHAR +/* Bits for all wchar, size is 65536/8, only supports wide characters with a maximum length of two bytes */ +#define SECUREC_BRACKET_TABLE_SIZE 8192 +#define SECUREC_EOF WEOF +#define SECUREC_MB_LEN 16 /* Max. # bytes in multibyte char ,see MB_LEN_MAX */ +#else +/* Bits for all char, size is 256/8 */ +#define SECUREC_BRACKET_TABLE_SIZE 32 +#define SECUREC_EOF EOF +#endif + +#if SECUREC_HAVE_WCHART +#define SECUREC_ARRAY_WIDTH_IS_WRONG(spec) ((spec).arrayWidth == 0 || \ + ((spec).isWCharOrLong <= 0 && (spec).arrayWidth > SECUREC_STRING_MAX_LEN) || \ + ((spec).isWCharOrLong > 0 && (spec).arrayWidth > SECUREC_WCHAR_STRING_MAX_LEN)) +#else +#define SECUREC_ARRAY_WIDTH_IS_WRONG(spec) ((spec).arrayWidth == 0 || (spec).arrayWidth > SECUREC_STRING_MAX_LEN) +#endif + +#ifdef SECUREC_ON_64BITS +/* Use 0xffffffffUL mask to pass integer as array length */ +#define SECUREC_GET_ARRAYWIDTH(argList) (((size_t)va_arg((argList), size_t)) & 0xffffffffUL) +#else /* !SECUREC_ON_64BITS */ +#define SECUREC_GET_ARRAYWIDTH(argList) ((size_t)va_arg((argList), size_t)) +#endif + +typedef struct { +#ifdef SECUREC_FOR_WCHAR + unsigned char *table; /* Default NULL */ +#else + unsigned char table[SECUREC_BRACKET_TABLE_SIZE]; /* Array length is large enough in application scenarios */ +#endif + unsigned char mask; /* Default 0 */ +} SecBracketTable; + +#ifdef SECUREC_FOR_WCHAR +#define SECUREC_INIT_BRACKET_TABLE { NULL, 0 } +#else +#define SECUREC_INIT_BRACKET_TABLE { {0}, 0 } +#endif + +#if SECUREC_ENABLE_SCANF_FLOAT +typedef struct { + size_t floatStrTotalLen; /* Initialization must be length of buffer in charater */ + size_t floatStrUsedLen; /* Store float string len */ + SecChar *floatStr; /* Initialization must point to buffer */ + SecChar *allocatedFloatStr; /* Initialization must be NULL to store alloced point */ + SecChar buffer[SECUREC_FLOAT_BUFSIZE + 1]; +} SecFloatSpec; +#endif + +#define SECUREC_NUMBER_STATE_DEFAULT 0U +#define SECUREC_NUMBER_STATE_STARTED 1U + +typedef struct { + SecInt ch; /* Char read from input */ + int charCount; /* Number of characters processed */ + void *argPtr; /* Variable parameter pointer, point to the end of the string */ + size_t arrayWidth; /* Length of pointer Variable parameter, in charaters */ + SecUnsignedInt64 number64; /* Store input number64 value */ + unsigned long number; /* Store input number32 value */ + int numberWidth; /* 0 = SHORT, 1 = int, > 1 long or L_DOUBLE */ + int numberArgType; /* 1 for 64-bit integer, 0 otherwise. use it as decode function index */ + unsigned int negative; /* 0 is positive */ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + unsigned int beyondMax; /* Non-zero means beyond */ +#endif + unsigned int numberState; /* Identifies whether to start processing numbers, 1 is can input number */ + int width; /* Width number in format */ + int widthSet; /* 0 is not set width in format */ + int convChr; /* Lowercase format conversion characters */ + int oriConvChr; /* Store original format conversion, convChr may change when parsing integers */ + signed char isWCharOrLong; /* -1/0 not wchar or long, 1 for wchar or long */ + unsigned char suppress; /* 0 is not have %* in format */ +} SecScanSpec; + +#ifdef SECUREC_FOR_WCHAR +#define SECUREC_GETC fgetwc +#define SECUREC_UN_GETC ungetwc +/* Only supports wide characters with a maximum length of two bytes in format string */ +#define SECUREC_BRACKET_CHAR_MASK 0xffffU +#else +#define SECUREC_GETC fgetc +#define SECUREC_UN_GETC ungetc +#define SECUREC_BRACKET_CHAR_MASK 0xffU +#endif + +#define SECUREC_CHAR_SIZE ((unsigned int)(sizeof(SecChar))) +/* To avoid 648, mask high bit: 0x00ffffff 0x0000ffff or 0x00000000 */ +#define SECUREC_CHAR_MASK_HIGH (((((((((unsigned int)(-1) >> SECUREC_CHAR_SIZE) >> SECUREC_CHAR_SIZE) >> \ + SECUREC_CHAR_SIZE) >> SECUREC_CHAR_SIZE) >> \ + SECUREC_CHAR_SIZE) >> SECUREC_CHAR_SIZE) >> \ + SECUREC_CHAR_SIZE) >> SECUREC_CHAR_SIZE) + +/* For char is 0xff, wcahr_t is 0xffff or 0xffffffff. */ +#define SECUREC_CHAR_MASK (~((((((((((unsigned int)(-1) & SECUREC_CHAR_MASK_HIGH) << \ + SECUREC_CHAR_SIZE) << SECUREC_CHAR_SIZE) << \ + SECUREC_CHAR_SIZE) << SECUREC_CHAR_SIZE) << \ + SECUREC_CHAR_SIZE) << SECUREC_CHAR_SIZE) << \ + SECUREC_CHAR_SIZE) << SECUREC_CHAR_SIZE)) + +/* According wchar_t has multiple bytes, so use sizeof */ +#define SECUREC_GET_CHAR(stream, outCh) do { \ + if ((stream)->count >= sizeof(SecChar)) { \ + *(outCh) = (SecInt)(SECUREC_CHAR_MASK & \ + (unsigned int)(int)(*((const SecChar *)(const void *)(stream)->cur))); \ + (stream)->cur += sizeof(SecChar); \ + (stream)->count -= sizeof(SecChar); \ + } else { \ + *(outCh) = SECUREC_EOF; \ + } \ +} SECUREC_WHILE_ZERO + +#define SECUREC_UN_GET_CHAR(stream) do { \ + if ((stream)->cur > (stream)->base) { \ + (stream)->cur -= sizeof(SecChar); \ + (stream)->count += sizeof(SecChar); \ + } \ +} SECUREC_WHILE_ZERO + +/* Convert wchar_t to int and then to unsigned int to keep data clearing warning */ +#define SECUREC_TO_LOWERCASE(chr) ((int)((unsigned int)(int)(chr) | (unsigned int)('a' - 'A'))) + +/* Record a flag for each bit */ +#define SECUREC_BRACKET_INDEX(x) ((unsigned int)(x) >> 3U) +#define SECUREC_BRACKET_VALUE(x) ((unsigned char)(1U << ((unsigned int)(x) & 7U))) +#if SECUREC_IN_KERNEL +#define SECUREC_CONVERT_IS_UNSIGNED(conv) ((conv) == 'x' || (conv) == 'o' || (conv) == 'u') +#endif + +/* + * Set char in %[xxx] into table, only supports wide characters with a maximum length of two bytes + */ +SECUREC_INLINE void SecBracketSetBit(unsigned char *table, SecUnsignedChar ch) +{ + unsigned int tableIndex = SECUREC_BRACKET_INDEX(((unsigned int)(int)ch & SECUREC_BRACKET_CHAR_MASK)); + unsigned int tableValue = SECUREC_BRACKET_VALUE(((unsigned int)(int)ch & SECUREC_BRACKET_CHAR_MASK)); + /* Do not use |= optimize this code, it will cause compiling warning */ + table[tableIndex] = (unsigned char)(table[tableIndex] | tableValue); +} + +SECUREC_INLINE void SecBracketSetBitRange(unsigned char *table, SecUnsignedChar startCh, SecUnsignedChar endCh) +{ + SecUnsignedChar expCh; + /* %[a-z] %[a-a] Format %[a-\xff] end is 0xFF, condition (expCh <= endChar) cause dead loop */ + for (expCh = startCh; expCh < endCh; ++expCh) { + SecBracketSetBit(table, expCh); + } + SecBracketSetBit(table, endCh); +} +/* + * Determine whether the expression can be satisfied + */ +SECUREC_INLINE int SecCanInputForBracket(int convChr, SecInt ch, const SecBracketTable *bracketTable) +{ + unsigned int tableIndex = SECUREC_BRACKET_INDEX(((unsigned int)(int)ch & SECUREC_BRACKET_CHAR_MASK)); + unsigned int tableValue = SECUREC_BRACKET_VALUE(((unsigned int)(int)ch & SECUREC_BRACKET_CHAR_MASK)); +#ifdef SECUREC_FOR_WCHAR + if (((unsigned int)(int)ch & (~(SECUREC_BRACKET_CHAR_MASK))) != 0) { + /* The value of the wide character exceeds the size of two bytes */ + return 0; + } + return (int)(convChr == SECUREC_BRACE && + (((unsigned int)bracketTable->table[tableIndex] ^ (unsigned int)bracketTable->mask) & tableValue) != 0); +#else + return (int)(convChr == SECUREC_BRACE && + (((unsigned int)bracketTable->table[tableIndex] ^ (unsigned int)bracketTable->mask) & tableValue) != 0); +#endif +} + +/* + * String input ends when blank character is encountered + */ +SECUREC_INLINE int SecCanInputString(int convChr, SecInt ch) +{ + return (int)(convChr == 's' && + (!(ch >= SECUREC_CHAR('\t') && ch <= SECUREC_CHAR('\r')) && ch != SECUREC_CHAR(' '))); +} + +/* + * Can input a character when format is %c + */ +SECUREC_INLINE int SecCanInputCharacter(int convChr) +{ + return (int)(convChr == 'c'); +} + +/* + * Determine if it is a 64-bit pointer function + * Return 0 is not ,1 is 64bit pointer + */ +SECUREC_INLINE int SecNumberArgType(size_t sizeOfVoidStar) +{ + /* Point size is 4 or 8 , Under the 64 bit system, the value not 0 */ + /* To clear e778 */ + if ((sizeOfVoidStar & sizeof(SecInt64)) != 0) { + return 1; + } + return 0; +} +SECUREC_INLINE int SecIsDigit(SecInt ch); +SECUREC_INLINE int SecIsXdigit(SecInt ch); +SECUREC_INLINE int SecIsSpace(SecInt ch); +SECUREC_INLINE SecInt SecSkipSpaceChar(SecFileStream *stream, int *counter); +SECUREC_INLINE SecInt SecGetChar(SecFileStream *stream, int *counter); +SECUREC_INLINE void SecUnGetChar(SecInt ch, SecFileStream *stream, int *counter); + +#if SECUREC_ENABLE_SCANF_FLOAT + +/* + * Convert a floating point string to a floating point number + */ +SECUREC_INLINE int SecAssignNarrowFloat(const char *floatStr, const SecScanSpec *spec) +{ + char *endPtr = NULL; + double d; +#if SECUREC_SUPPORT_STRTOLD + if (spec->numberWidth == SECUREC_NUM_WIDTH_LONG_LONG) { + long double d2 = strtold(floatStr, &endPtr); + if (endPtr == floatStr) { + return -1; + } + *(long double UNALIGNED *)(spec->argPtr) = d2; + return 0; + } +#endif + d = strtod(floatStr, &endPtr); + /* cannot detect if endPtr points to the end of floatStr,because strtod handles only two characters for 1.E */ + if (endPtr == floatStr) { + return -1; + } + if (spec->numberWidth > SECUREC_NUM_WIDTH_INT) { + *(double UNALIGNED *)(spec->argPtr) = (double)d; + } else { + *(float UNALIGNED *)(spec->argPtr) = (float)d; + } + return 0; +} + +#ifdef SECUREC_FOR_WCHAR +/* + * Convert a floating point wchar string to a floating point number + * Success ret 0 + */ +SECUREC_INLINE int SecAssignWideFloat(const SecFloatSpec *floatSpec, const SecScanSpec *spec) +{ + int retVal; + /* Convert float string */ + size_t mbsLen; + size_t tempFloatStrLen = (size_t)(floatSpec->floatStrUsedLen + 1) * sizeof(wchar_t); + char *tempFloatStr = (char *)SECUREC_MALLOC(tempFloatStrLen); + if (tempFloatStr == NULL) { + return -1; + } + tempFloatStr[0] = '\0'; + SECUREC_MASK_MSVC_CRT_WARNING + mbsLen = wcstombs(tempFloatStr, floatSpec->floatStr, tempFloatStrLen - 1); + SECUREC_END_MASK_MSVC_CRT_WARNING + /* This condition must satisfy mbsLen is not -1 */ + if (mbsLen >= tempFloatStrLen) { + SECUREC_FREE(tempFloatStr); + return -1; + } + tempFloatStr[mbsLen] = '\0'; + retVal = SecAssignNarrowFloat(tempFloatStr, spec); + SECUREC_FREE(tempFloatStr); + return retVal; +} +#endif + +SECUREC_INLINE int SecAssignFloat(const SecFloatSpec *floatSpec, const SecScanSpec *spec) +{ +#ifdef SECUREC_FOR_WCHAR + return SecAssignWideFloat(floatSpec, spec); +#else + return SecAssignNarrowFloat(floatSpec->floatStr, spec); +#endif +} + +/* + * Init SecFloatSpec before parse format + */ +SECUREC_INLINE void SecInitFloatSpec(SecFloatSpec *floatSpec) +{ + floatSpec->floatStr = floatSpec->buffer; + floatSpec->allocatedFloatStr = NULL; + floatSpec->floatStrTotalLen = sizeof(floatSpec->buffer) / sizeof(floatSpec->buffer[0]); + floatSpec->floatStrUsedLen = 0; +} + +SECUREC_INLINE void SecFreeFloatSpec(SecFloatSpec *floatSpec, int *doneCount) +{ + /* 2014.3.6 add, clear the stack data */ + if (memset_s(floatSpec->buffer, sizeof(floatSpec->buffer), 0, sizeof(floatSpec->buffer)) != EOK) { + *doneCount = 0; /* This code just to meet the coding requirements */ + } + /* The pFloatStr can be alloced in SecExtendFloatLen function, clear and free it */ + if (floatSpec->allocatedFloatStr != NULL) { + size_t bufferSize = floatSpec->floatStrTotalLen * sizeof(SecChar); + if (memset_s(floatSpec->allocatedFloatStr, bufferSize, 0, bufferSize) != EOK) { + *doneCount = 0; /* This code just to meet the coding requirements */ + } + SECUREC_FREE(floatSpec->allocatedFloatStr); + floatSpec->allocatedFloatStr = NULL; + floatSpec->floatStr = NULL; + } +} + +/* + * Splice floating point string + * Return 0 OK + */ +SECUREC_INLINE int SecExtendFloatLen(SecFloatSpec *floatSpec) +{ + if (floatSpec->floatStrUsedLen >= floatSpec->floatStrTotalLen) { + /* Buffer size is len x sizeof(SecChar) */ + size_t oriSize = floatSpec->floatStrTotalLen * sizeof(SecChar); + /* Add one character to clear tool warning */ + size_t nextSize = (oriSize * 2) + sizeof(SecChar); /* Multiply 2 to extend buffer size */ + + /* Prevents integer overflow, the maximum length of SECUREC_MAX_WIDTH_LEN is enough */ + if (nextSize <= (size_t)SECUREC_MAX_WIDTH_LEN) { + void *nextBuffer = (void *)SECUREC_MALLOC(nextSize); + if (nextBuffer == NULL) { + return -1; + } + if (memcpy_s(nextBuffer, nextSize, floatSpec->floatStr, oriSize) != EOK) { + SECUREC_FREE(nextBuffer); /* This is a dead code, just to meet the coding requirements */ + return -1; + } + /* Clear old buffer memory */ + if (memset_s(floatSpec->floatStr, oriSize, 0, oriSize) != EOK) { + SECUREC_FREE(nextBuffer); /* This is a dead code, just to meet the coding requirements */ + return -1; + } + /* Free old allocated buffer */ + if (floatSpec->allocatedFloatStr != NULL) { + SECUREC_FREE(floatSpec->allocatedFloatStr); + } + floatSpec->allocatedFloatStr = (SecChar *)(nextBuffer); /* Use to clear free on stack warning */ + floatSpec->floatStr = (SecChar *)(nextBuffer); + floatSpec->floatStrTotalLen = nextSize / sizeof(SecChar); /* Get buffer total len in character */ + return 0; + } + return -1; /* Next size is beyond max */ + } + return 0; +} + +/* Do not use localeconv()->decimal_pointif only support '.' */ +SECUREC_INLINE int SecIsFloatDecimal(SecChar ch) +{ + return (int)(ch == SECUREC_CHAR('.')); +} + +SECUREC_INLINE int SecInputFloatSign(SecFileStream *stream, SecScanSpec *spec, SecFloatSpec *floatSpec) +{ + if (!SECUREC_FILED_WIDTH_ENOUGH(spec)) { + return 0; + } + spec->ch = SecGetChar(stream, &(spec->charCount)); + if (spec->ch == SECUREC_CHAR('+') || spec->ch == SECUREC_CHAR('-')) { + SECUREC_FILED_WIDTH_DEC(spec); /* Make sure the count after un get char is correct */ + if (spec->ch == SECUREC_CHAR('-')) { + floatSpec->floatStr[floatSpec->floatStrUsedLen] = SECUREC_CHAR('-'); + ++floatSpec->floatStrUsedLen; + if (SecExtendFloatLen(floatSpec) != 0) { + return -1; + } + } + } else { + SecUnGetChar(spec->ch, stream, &(spec->charCount)); + } + return 0; +} + +SECUREC_INLINE int SecInputFloatDigit(SecFileStream *stream, SecScanSpec *spec, SecFloatSpec *floatSpec) +{ + /* Now get integral part */ + while (SECUREC_FILED_WIDTH_ENOUGH(spec)) { + spec->ch = SecGetChar(stream, &(spec->charCount)); + if (SecIsDigit(spec->ch) == 0) { + SecUnGetChar(spec->ch, stream, &(spec->charCount)); + return 0; + } + SECUREC_FILED_WIDTH_DEC(spec); /* Must be behind un get char, otherwise the logic is incorrect */ + spec->numberState = SECUREC_NUMBER_STATE_STARTED; + floatSpec->floatStr[floatSpec->floatStrUsedLen] = (SecChar)spec->ch; + ++floatSpec->floatStrUsedLen; + if (SecExtendFloatLen(floatSpec) != 0) { + return -1; + } + } + return 0; +} + +/* +* Scan value of exponent. +* Return 0 OK +*/ +SECUREC_INLINE int SecInputFloatE(SecFileStream *stream, SecScanSpec *spec, SecFloatSpec *floatSpec) +{ + if (SecInputFloatSign(stream, spec, floatSpec) == -1) { + return -1; + } + if (SecInputFloatDigit(stream, spec, floatSpec) != 0) { + return -1; + } + return 0; +} + +SECUREC_INLINE int SecInputFloatFractional(SecFileStream *stream, SecScanSpec *spec, SecFloatSpec *floatSpec) +{ + if (SECUREC_FILED_WIDTH_ENOUGH(spec)) { + spec->ch = SecGetChar(stream, &(spec->charCount)); + if (SecIsFloatDecimal((SecChar)spec->ch) == 0) { + SecUnGetChar(spec->ch, stream, &(spec->charCount)); + return 0; + } + SECUREC_FILED_WIDTH_DEC(spec); /* Must be behind un get char, otherwise the logic is incorrect */ + /* Now check for decimal */ + floatSpec->floatStr[floatSpec->floatStrUsedLen] = (SecChar)spec->ch; + ++floatSpec->floatStrUsedLen; + if (SecExtendFloatLen(floatSpec) != 0) { + return -1; + } + if (SecInputFloatDigit(stream, spec, floatSpec) != 0) { + return -1; + } + } + return 0; +} + +SECUREC_INLINE int SecInputFloatExponent(SecFileStream *stream, SecScanSpec *spec, SecFloatSpec *floatSpec) +{ + /* Now get exponent part */ + if (spec->numberState == SECUREC_NUMBER_STATE_STARTED && SECUREC_FILED_WIDTH_ENOUGH(spec)) { + spec->ch = SecGetChar(stream, &(spec->charCount)); + if (spec->ch != SECUREC_CHAR('e') && spec->ch != SECUREC_CHAR('E')) { + SecUnGetChar(spec->ch, stream, &(spec->charCount)); + return 0; + } + SECUREC_FILED_WIDTH_DEC(spec); /* Must be behind un get char, otherwise the logic is incorrect */ + floatSpec->floatStr[floatSpec->floatStrUsedLen] = SECUREC_CHAR('e'); + ++floatSpec->floatStrUsedLen; + if (SecExtendFloatLen(floatSpec) != 0) { + return -1; + } + if (SecInputFloatE(stream, spec, floatSpec) != 0) { + return -1; + } + } + return 0; +} + +/* +* Scan %f. +* Return 0 OK +*/ +SECUREC_INLINE int SecInputFloat(SecFileStream *stream, SecScanSpec *spec, SecFloatSpec *floatSpec) +{ + floatSpec->floatStrUsedLen = 0; + + /* The following code sequence is strict */ + if (SecInputFloatSign(stream, spec, floatSpec) != 0) { + return -1; + } + if (SecInputFloatDigit(stream, spec, floatSpec) != 0) { + return -1; + } + if (SecInputFloatFractional(stream, spec, floatSpec) != 0) { + return -1; + } + if (SecInputFloatExponent(stream, spec, floatSpec) != 0) { + return -1; + } + + /* Make sure have a string terminator, buffer is large enough */ + floatSpec->floatStr[floatSpec->floatStrUsedLen] = SECUREC_CHAR('\0'); + if (spec->numberState == SECUREC_NUMBER_STATE_STARTED) { + return 0; + } + return -1; +} +#endif + +#if (!defined(SECUREC_FOR_WCHAR) && SECUREC_HAVE_WCHART && SECUREC_HAVE_MBTOWC) || \ + (!defined(SECUREC_FOR_WCHAR) && defined(SECUREC_COMPATIBLE_VERSION)) +/* only multi-bytes string need isleadbyte() function */ +SECUREC_INLINE int SecIsLeadByte(SecInt ch) +{ + unsigned int c = (unsigned int)ch; +#if !(defined(_MSC_VER) || defined(_INC_WCTYPE)) + return (int)(c & 0x80U); /* Use bitwise operation to check if the most significant bit is 1 */ +#else + return (int)isleadbyte((int)(c & 0xffU)); /* Use bitwise operations to limit character values to valid ranges */ +#endif +} +#endif + +/* + * Parsing whether it is a wide character + */ +SECUREC_INLINE void SecUpdateWcharFlagByType(SecUnsignedChar ch, SecScanSpec *spec) +{ + if (spec->isWCharOrLong != 0) { + /* Wide character identifiers have been explicitly set by l or h flag */ + return; + } + + /* Set default flag */ +#if defined(SECUREC_FOR_WCHAR) && defined(SECUREC_COMPATIBLE_WIN_FORMAT) + spec->isWCharOrLong = 1; /* On windows wide char version %c %s %[ is wide char */ +#else + spec->isWCharOrLong = -1; /* On linux all version %c %s %[ is multi char */ +#endif + + if (ch == SECUREC_CHAR('C') || ch == SECUREC_CHAR('S')) { +#if defined(SECUREC_FOR_WCHAR) && defined(SECUREC_COMPATIBLE_WIN_FORMAT) + spec->isWCharOrLong = -1; /* On windows wide char version %C %S is multi char */ +#else + spec->isWCharOrLong = 1; /* On linux all version %C %S is wide char */ +#endif + } + + return; +} +/* + * Decode %l %ll + */ +SECUREC_INLINE void SecDecodeScanQualifierL(const SecUnsignedChar **format, SecScanSpec *spec) +{ + const SecUnsignedChar *fmt = *format; + if (*(fmt + 1) == SECUREC_CHAR('l')) { + spec->numberArgType = 1; + spec->numberWidth = SECUREC_NUM_WIDTH_LONG_LONG; + ++fmt; + } else { + spec->numberWidth = SECUREC_NUM_WIDTH_LONG; +#if defined(SECUREC_ON_64BITS) && !(defined(SECUREC_COMPATIBLE_WIN_FORMAT)) + /* On window 64 system sizeof long is 32bit */ + spec->numberArgType = 1; +#endif + spec->isWCharOrLong = 1; + } + *format = fmt; +} + +/* + * Decode %I %I43 %I64 %Id %Ii %Io ... + * Set finishFlag to 1 finish Flag + */ +SECUREC_INLINE void SecDecodeScanQualifierI(const SecUnsignedChar **format, SecScanSpec *spec, int *finishFlag) +{ + const SecUnsignedChar *fmt = *format; + if ((*(fmt + 1) == SECUREC_CHAR('6')) && + (*(fmt + 2) == SECUREC_CHAR('4'))) { /* Offset 2 for I64 */ + spec->numberArgType = 1; + *format = *format + 2; /* Add 2 to skip I64 point to '4' next loop will inc */ + } else if ((*(fmt + 1) == SECUREC_CHAR('3')) && + (*(fmt + 2) == SECUREC_CHAR('2'))) { /* Offset 2 for I32 */ + *format = *format + 2; /* Add 2 to skip I32 point to '2' next loop will inc */ + } else if ((*(fmt + 1) == SECUREC_CHAR('d')) || + (*(fmt + 1) == SECUREC_CHAR('i')) || + (*(fmt + 1) == SECUREC_CHAR('o')) || + (*(fmt + 1) == SECUREC_CHAR('x')) || + (*(fmt + 1) == SECUREC_CHAR('X'))) { + spec->numberArgType = SecNumberArgType(sizeof(void *)); + } else { + /* For %I */ + spec->numberArgType = SecNumberArgType(sizeof(void *)); + *finishFlag = 1; + } +} + +SECUREC_INLINE int SecDecodeScanWidth(const SecUnsignedChar **format, SecScanSpec *spec) +{ + const SecUnsignedChar *fmt = *format; + while (SecIsDigit((SecInt)(int)(*fmt)) != 0) { + spec->widthSet = 1; + if (SECUREC_MUL_TEN_ADD_BEYOND_MAX(spec->width)) { + return -1; + } + spec->width = (int)SECUREC_MUL_TEN((unsigned int)spec->width) + (unsigned char)(*fmt - SECUREC_CHAR('0')); + ++fmt; + } + *format = fmt; + return 0; +} + +/* + * Init default flags for each format. do not init ch this variable is context-dependent + */ +SECUREC_INLINE void SecSetDefaultScanSpec(SecScanSpec *spec) +{ + /* The ch and charCount member variables cannot be initialized here */ + spec->argPtr = NULL; + spec->arrayWidth = 0; + spec->number64 = 0; + spec->number = 0; + spec->numberWidth = SECUREC_NUM_WIDTH_INT; /* 0 = SHORT, 1 = int, > 1 long or L_DOUBLE */ + spec->numberArgType = 0; /* 1 for 64-bit integer, 0 otherwise */ + spec->width = 0; + spec->widthSet = 0; + spec->convChr = 0; + spec->oriConvChr = 0; + spec->isWCharOrLong = 0; + spec->suppress = 0; +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + spec->beyondMax = 0; +#endif + spec->negative = 0; + spec->numberState = SECUREC_NUMBER_STATE_DEFAULT; +} + +/* + * Decode qualifier %I %L %h ... + * Set finishFlag to 1 finish Flag + */ +SECUREC_INLINE void SecDecodeScanQualifier(const SecUnsignedChar **format, SecScanSpec *spec, int *finishFlag) +{ + switch (**format) { + case SECUREC_CHAR('F'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('N'): + break; + case SECUREC_CHAR('h'): + --spec->numberWidth; /* The h for SHORT , hh for CHAR */ + spec->isWCharOrLong = -1; + break; +#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT + case SECUREC_CHAR('j'): + spec->numberWidth = SECUREC_NUM_WIDTH_LONG_LONG; /* For intmax_t or uintmax_t */ + spec->numberArgType = 1; + break; + case SECUREC_CHAR('t'): /* fall-through */ /* FALLTHRU */ +#endif +#if SECUREC_IN_KERNEL + case SECUREC_CHAR('Z'): /* fall-through */ /* FALLTHRU */ +#endif + case SECUREC_CHAR('z'): +#ifdef SECUREC_ON_64BITS + spec->numberWidth = SECUREC_NUM_WIDTH_LONG_LONG; + spec->numberArgType = 1; +#else + spec->numberWidth = SECUREC_NUM_WIDTH_LONG; +#endif + break; + case SECUREC_CHAR('L'): /* For long double */ /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('q'): + spec->numberWidth = SECUREC_NUM_WIDTH_LONG_LONG; + spec->numberArgType = 1; + break; + case SECUREC_CHAR('l'): + SecDecodeScanQualifierL(format, spec); + break; + case SECUREC_CHAR('w'): + spec->isWCharOrLong = 1; + break; + case SECUREC_CHAR('*'): + spec->suppress = 1; + break; + case SECUREC_CHAR('I'): + SecDecodeScanQualifierI(format, spec, finishFlag); + break; + default: + *finishFlag = 1; + break; + } +} +/* + * Decode width and qualifier in format + */ +SECUREC_INLINE int SecDecodeScanFlag(const SecUnsignedChar **format, SecScanSpec *spec) +{ + const SecUnsignedChar *fmt = *format; + int finishFlag = 0; + + do { + ++fmt; /* First skip % , next seek fmt */ + /* May %*6d , so put it inside the loop */ + if (SecDecodeScanWidth(&fmt, spec) != 0) { + return -1; + } + SecDecodeScanQualifier(&fmt, spec, &finishFlag); + } while (finishFlag == 0); + *format = fmt; + return 0; +} + +/* + * Judging whether a zeroing buffer is needed according to different formats + */ +SECUREC_INLINE int SecDecodeClearFormat(const SecUnsignedChar *format, int *convChr) +{ + const SecUnsignedChar *fmt = format; + /* To lowercase */ + int ch = SECUREC_TO_LOWERCASE(*fmt); + if (!(ch == 'c' || ch == 's' || ch == SECUREC_BRACE)) { + return -1; /* First argument is not a string type */ + } + if (ch == SECUREC_BRACE) { +#if !(defined(SECUREC_COMPATIBLE_WIN_FORMAT)) + if (*fmt == SECUREC_CHAR('{')) { + return -1; + } +#endif + ++fmt; + if (*fmt == SECUREC_CHAR('^')) { + ++fmt; + } + if (*fmt == SECUREC_CHAR(']')) { + ++fmt; + } + while (*fmt != SECUREC_CHAR('\0') && *fmt != SECUREC_CHAR(']')) { + ++fmt; + } + if (*fmt == SECUREC_CHAR('\0')) { + return -1; /* Trunc'd format string */ + } + } + *convChr = ch; + return 0; +} + +/* + * Add L'\0' for wchar string , add '\0' for char string + */ +SECUREC_INLINE void SecAddEndingZero(void *ptr, const SecScanSpec *spec) +{ + if (spec->suppress == 0) { + *(char *)ptr = '\0'; +#if SECUREC_HAVE_WCHART + if (spec->isWCharOrLong > 0) { + *(wchar_t UNALIGNED *)ptr = L'\0'; + } +#endif + } +} + +SECUREC_INLINE void SecDecodeClearArg(SecScanSpec *spec, va_list argList) +{ + va_list argListSave; /* Backup for argList value, this variable don't need initialized */ + (void)SECUREC_MEMSET_FUNC_OPT(&argListSave, 0, sizeof(va_list)); /* To clear e530 argListSave not initialized */ +#if defined(va_copy) + va_copy(argListSave, argList); +#elif defined(__va_copy) /* For vxworks */ + __va_copy(argListSave, argList); +#else + argListSave = argList; +#endif + spec->argPtr = (void *)va_arg(argListSave, void *); + /* Get the next argument, size of the array in characters */ + /* Use 0xffffffffUL mask to Support pass integer as array length */ + spec->arrayWidth = ((size_t)(va_arg(argListSave, size_t))) & 0xffffffffUL; + va_end(argListSave); + /* To clear e438 last value assigned not used , the compiler will optimize this code */ + (void)argListSave; +} + +#ifdef SECUREC_FOR_WCHAR +/* + * Clean up the first %s %c buffer to zero for wchar version + */ +void SecClearDestBufW(const wchar_t *buffer, const wchar_t *format, va_list argList) +#else +/* + * Clean up the first %s %c buffer to zero for char version + */ +void SecClearDestBuf(const char *buffer, const char *format, va_list argList) +#endif +{ + SecScanSpec spec; + int convChr = 0; + const SecUnsignedChar *fmt = (const SecUnsignedChar *)format; + + /* Find first % */ + while (*fmt != SECUREC_CHAR('\0') && *fmt != SECUREC_CHAR('%')) { + ++fmt; + } + if (*fmt == SECUREC_CHAR('\0')) { + return; + } + + SecSetDefaultScanSpec(&spec); + if (SecDecodeScanFlag(&fmt, &spec) != 0) { + return; + } + + /* Update wchar flag for %S %C */ + SecUpdateWcharFlagByType(*fmt, &spec); + if (spec.suppress != 0) { + return; + } + + if (SecDecodeClearFormat(fmt, &convChr) != 0) { + return; + } + + if (*buffer != SECUREC_CHAR('\0') && convChr != 's') { + /* + * When buffer not empty just clear %s. + * Example call sscanf by argment of (" \n", "%s", s, sizeof(s)) + */ + return; + } + + SecDecodeClearArg(&spec, argList); + /* There is no need to judge the upper limit */ + if (spec.arrayWidth == 0 || spec.argPtr == NULL) { + return; + } + /* Clear one char */ + SecAddEndingZero(spec.argPtr, &spec); + return; +} + +/* + * Assign number to output buffer + */ +SECUREC_INLINE void SecAssignNumber(const SecScanSpec *spec) +{ + void *argPtr = spec->argPtr; + if (spec->numberArgType != 0) { +#if defined(SECUREC_VXWORKS_PLATFORM) +#if defined(SECUREC_VXWORKS_PLATFORM_COMP) + *(SecInt64 UNALIGNED *)argPtr = (SecInt64)(spec->number64); +#else + /* Take number64 as unsigned number unsigned to int clear Compile warning */ + *(SecInt64 UNALIGNED *)argPtr = *(SecUnsignedInt64 *)(&(spec->number64)); +#endif +#else + /* Take number64 as unsigned number */ + *(SecInt64 UNALIGNED *)argPtr = (SecInt64)(spec->number64); +#endif + return; + } + if (spec->numberWidth > SECUREC_NUM_WIDTH_INT) { + /* Take number as unsigned number */ + *(long UNALIGNED *)argPtr = (long)(spec->number); + } else if (spec->numberWidth == SECUREC_NUM_WIDTH_INT) { + *(int UNALIGNED *)argPtr = (int)(spec->number); + } else if (spec->numberWidth == SECUREC_NUM_WIDTH_SHORT) { + /* Take number as unsigned number */ + *(short UNALIGNED *)argPtr = (short)(spec->number); + } else { /* < 0 for hh format modifier */ + /* Take number as unsigned number */ + *(char UNALIGNED *)argPtr = (char)(spec->number); + } +} + +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) +/* + * Judge the long bit width + */ +SECUREC_INLINE int SecIsLongBitEqual(int bitNum) +{ + return (int)((unsigned int)bitNum == SECUREC_LONG_BIT_NUM); +} +#endif + +/* + * Convert hexadecimal characters to decimal value + */ +SECUREC_INLINE int SecHexValueOfChar(SecInt ch) +{ + /* Use isdigit Causing tool false alarms */ + return (int)((ch >= '0' && ch <= '9') ? ((unsigned char)ch - '0') : + ((((unsigned char)ch | (unsigned char)('a' - 'A')) - ('a')) + 10)); /* Adding 10 is to hex value */ +} + +/* + * Parse decimal character to integer for 32bit . + */ +static void SecDecodeNumberDecimal(SecScanSpec *spec) +{ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + unsigned long decimalEdge = SECUREC_MAX_32BITS_VALUE_DIV_TEN; +#ifdef SECUREC_ON_64BITS + if (SecIsLongBitEqual(SECUREC_LP64_BIT_WIDTH) != 0) { + decimalEdge = (unsigned long)SECUREC_MAX_64BITS_VALUE_DIV_TEN; + } +#endif + if (spec->number > decimalEdge) { + spec->beyondMax = 1; + } +#endif + spec->number = SECUREC_MUL_TEN(spec->number); +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + if (spec->number == SECUREC_MUL_TEN(decimalEdge)) { + /* This code is specially converted to unsigned long type for compatibility */ + SecUnsignedInt64 number64As = (unsigned long)SECUREC_MAX_64BITS_VALUE - spec->number; + if (number64As < (SecUnsignedInt64)(SecUnsignedInt)spec->ch - (SecUnsignedInt)SECUREC_CHAR('0')) { + spec->beyondMax = 1; + } + } +#endif + spec->number += ((unsigned long)(SecUnsignedInt)spec->ch - (SecUnsignedInt)SECUREC_CHAR('0')); +} + +/* + * Parse Hex character to integer for 32bit . + */ +static void SecDecodeNumberHex(SecScanSpec *spec) +{ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + if (SECUREC_LONG_HEX_BEYOND_MAX(spec->number)) { + spec->beyondMax = 1; + } +#endif + spec->number = SECUREC_MUL_SIXTEEN(spec->number); + spec->number += (unsigned long)(unsigned int)SecHexValueOfChar(spec->ch); +} + +/* + * Parse Octal character to integer for 32bit . + */ +static void SecDecodeNumberOctal(SecScanSpec *spec) +{ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + if (SECUREC_LONG_OCTAL_BEYOND_MAX(spec->number)) { + spec->beyondMax = 1; + } +#endif + spec->number = SECUREC_MUL_EIGHT(spec->number); + spec->number += ((unsigned long)(SecUnsignedInt)spec->ch - (SecUnsignedInt)SECUREC_CHAR('0')); +} + +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) +/* Compatible with integer negative values other than int */ +SECUREC_INLINE void SecFinishNumberNegativeOther(SecScanSpec *spec) +{ + if (SECUREC_CONVERT_IS_SIGNED(spec->oriConvChr)) { + if (spec->number > SECUREC_MIN_LONG_NEG_VALUE) { + spec->number = SECUREC_MIN_LONG_NEG_VALUE; + } else { + spec->number = (unsigned long)(0U - spec->number); /* Wrap with unsigned long numbers */ + } + if (spec->beyondMax != 0) { + if (spec->numberWidth < SECUREC_NUM_WIDTH_INT) { + spec->number = 0; + } + if (spec->numberWidth == SECUREC_NUM_WIDTH_LONG) { + spec->number = SECUREC_MIN_LONG_NEG_VALUE; + } + } + } else { /* For o, u, x, X, p */ + spec->number = (unsigned long)(0U - spec->number); /* Wrap with unsigned long numbers */ + if (spec->beyondMax != 0) { + spec->number = (unsigned long)SECUREC_MAX_64BITS_VALUE; + } + } +} +/* Compatible processing of integer negative numbers */ +SECUREC_INLINE void SecFinishNumberNegativeInt(SecScanSpec *spec) +{ + if (SECUREC_CONVERT_IS_SIGNED(spec->oriConvChr)) { +#ifdef SECUREC_ON_64BITS + if (SecIsLongBitEqual(SECUREC_LP64_BIT_WIDTH) != 0) { + if ((spec->number > SECUREC_MIN_64BITS_NEG_VALUE)) { + spec->number = 0; + } else { + spec->number = (unsigned int)(0U - (unsigned int)spec->number); /* Wrap with unsigned int numbers */ + } + } +#else + if (SecIsLongBitEqual(SECUREC_LP32_BIT_WIDTH) != 0) { + if ((spec->number > SECUREC_MIN_32BITS_NEG_VALUE)) { + spec->number = SECUREC_MIN_32BITS_NEG_VALUE; + } else { + spec->number = (unsigned int)(0U - (unsigned int)spec->number); /* Wrap with unsigned int numbers */ + } + } +#endif + if (spec->beyondMax != 0) { +#ifdef SECUREC_ON_64BITS + if (SecIsLongBitEqual(SECUREC_LP64_BIT_WIDTH) != 0) { + spec->number = 0; + } +#else + if (SecIsLongBitEqual(SECUREC_LP32_BIT_WIDTH) != 0) { + spec->number = SECUREC_MIN_32BITS_NEG_VALUE; + } +#endif + } + } else { /* For o, u, x, X ,p */ +#ifdef SECUREC_ON_64BITS + if (spec->number > SECUREC_MAX_32BITS_VALUE_INC) { + spec->number = SECUREC_MAX_32BITS_VALUE; + } else { + spec->number = (unsigned int)(0U - (unsigned int)spec->number); /* Wrap with unsigned int numbers */ + } +#else + spec->number = (unsigned int)(0U - (unsigned int)spec->number); /* Wrap with unsigned int numbers */ +#endif + if (spec->beyondMax != 0) { + spec->number = (unsigned long)SECUREC_MAX_64BITS_VALUE; + } + } +} + +/* Compatible with integer positive values other than int */ +SECUREC_INLINE void SecFinishNumberPositiveOther(SecScanSpec *spec) +{ + if (SECUREC_CONVERT_IS_SIGNED(spec->oriConvChr)) { + if (spec->number > SECUREC_MAX_LONG_POS_VALUE) { + spec->number = SECUREC_MAX_LONG_POS_VALUE; + } + if ((spec->beyondMax != 0 && spec->numberWidth < SECUREC_NUM_WIDTH_INT)) { + spec->number = (unsigned long)SECUREC_MAX_64BITS_VALUE; + } + if (spec->beyondMax != 0 && spec->numberWidth == SECUREC_NUM_WIDTH_LONG) { + spec->number = SECUREC_MAX_LONG_POS_VALUE; + } + } else { + if (spec->beyondMax != 0) { + spec->number = (unsigned long)SECUREC_MAX_64BITS_VALUE; + } + } +} + +/* Compatible processing of integer positive numbers */ +SECUREC_INLINE void SecFinishNumberPositiveInt(SecScanSpec *spec) +{ + if (SECUREC_CONVERT_IS_SIGNED(spec->oriConvChr)) { +#ifdef SECUREC_ON_64BITS + if (SecIsLongBitEqual(SECUREC_LP64_BIT_WIDTH) != 0) { + if (spec->number > SECUREC_MAX_64BITS_POS_VALUE) { + spec->number = (unsigned long)SECUREC_MAX_64BITS_VALUE; + } + } + if (spec->beyondMax != 0 && SecIsLongBitEqual(SECUREC_LP64_BIT_WIDTH) != 0) { + spec->number = (unsigned long)SECUREC_MAX_64BITS_VALUE; + } +#else + if (SecIsLongBitEqual(SECUREC_LP32_BIT_WIDTH) != 0) { + if (spec->number > SECUREC_MAX_32BITS_POS_VALUE) { + spec->number = SECUREC_MAX_32BITS_POS_VALUE; + } + } + if (spec->beyondMax != 0 && SecIsLongBitEqual(SECUREC_LP32_BIT_WIDTH) != 0) { + spec->number = SECUREC_MAX_32BITS_POS_VALUE; + } +#endif + } else { /* For o,u,x,X,p */ + if (spec->beyondMax != 0) { + spec->number = SECUREC_MAX_32BITS_VALUE; + } + } +} + +#endif + +/* + * Parse decimal character to integer for 64bit . + */ +static void SecDecodeNumber64Decimal(SecScanSpec *spec) +{ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + if (spec->number64 > SECUREC_MAX_64BITS_VALUE_DIV_TEN) { + spec->beyondMax = 1; + } +#endif + spec->number64 = SECUREC_MUL_TEN(spec->number64); +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + if (spec->number64 == SECUREC_MAX_64BITS_VALUE_CUT_LAST_DIGIT) { + SecUnsignedInt64 number64As = (SecUnsignedInt64)SECUREC_MAX_64BITS_VALUE - spec->number64; + if (number64As < (SecUnsignedInt64)(SecUnsignedInt)spec->ch - (SecUnsignedInt)SECUREC_CHAR('0')) { + spec->beyondMax = 1; + } + } +#endif + spec->number64 += ((SecUnsignedInt64)(SecUnsignedInt)spec->ch - (SecUnsignedInt)SECUREC_CHAR('0')); +} + +/* + * Parse Hex character to integer for 64bit . + */ +static void SecDecodeNumber64Hex(SecScanSpec *spec) +{ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + if (SECUREC_QWORD_HEX_BEYOND_MAX(spec->number64)) { + spec->beyondMax = 1; + } +#endif + spec->number64 = SECUREC_MUL_SIXTEEN(spec->number64); + spec->number64 += (SecUnsignedInt64)(unsigned int)SecHexValueOfChar(spec->ch); +} + +/* + * Parse Octal character to integer for 64bit . + */ +static void SecDecodeNumber64Octal(SecScanSpec *spec) +{ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + if (SECUREC_QWORD_OCTAL_BEYOND_MAX(spec->number64)) { + spec->beyondMax = 1; + } +#endif + spec->number64 = SECUREC_MUL_EIGHT(spec->number64); + spec->number64 += ((SecUnsignedInt64)(SecUnsignedInt)spec->ch - (SecUnsignedInt)SECUREC_CHAR('0')); +} + +#define SECUREC_DECODE_NUMBER_FUNC_NUM 2 + +/* + * Parse 64-bit integer formatted input, return 0 when ch is a number. + */ +SECUREC_INLINE int SecDecodeNumber(SecScanSpec *spec) +{ + /* Function name cannot add address symbol, causing 546 alarm */ + static void (* const secDecodeNumberHex[SECUREC_DECODE_NUMBER_FUNC_NUM])(SecScanSpec *spec) = { + SecDecodeNumberHex, SecDecodeNumber64Hex + }; + static void (* const secDecodeNumberOctal[SECUREC_DECODE_NUMBER_FUNC_NUM])(SecScanSpec *spec) = { + SecDecodeNumberOctal, SecDecodeNumber64Octal + }; + static void (* const secDecodeNumberDecimal[SECUREC_DECODE_NUMBER_FUNC_NUM])(SecScanSpec *spec) = { + SecDecodeNumberDecimal, SecDecodeNumber64Decimal + }; + if (spec->convChr == 'x' || spec->convChr == 'p') { + if (SecIsXdigit(spec->ch) != 0) { + (*secDecodeNumberHex[spec->numberArgType])(spec); + } else { + return -1; + } + return 0; + } + if (SecIsDigit(spec->ch) == 0) { + return -1; + } + if (spec->convChr == 'o') { + if (spec->ch < SECUREC_CHAR('8')) { /* Octal maximum limit '8' */ + (*secDecodeNumberOctal[spec->numberArgType])(spec); + } else { + return -1; + } + } else { /* The convChr is 'd' */ + (*secDecodeNumberDecimal[spec->numberArgType])(spec); + } + return 0; +} + +/* + * Complete the final 32-bit integer formatted input + */ +static void SecFinishNumber(SecScanSpec *spec) +{ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + if (spec->negative != 0) { + if (spec->numberWidth == SECUREC_NUM_WIDTH_INT) { + SecFinishNumberNegativeInt(spec); + } else { + SecFinishNumberNegativeOther(spec); + } + } else { + if (spec->numberWidth == SECUREC_NUM_WIDTH_INT) { + SecFinishNumberPositiveInt(spec); + } else { + SecFinishNumberPositiveOther(spec); + } + } +#else + if (spec->negative != 0) { +#if defined(__hpux) + if (spec->oriConvChr != 'p') { + spec->number = (unsigned long)(0U - spec->number); /* Wrap with unsigned long numbers */ + } +#else + spec->number = (unsigned long)(0U - spec->number); /* Wrap with unsigned long numbers */ +#endif + } +#endif + return; +} + +/* + * Complete the final 64-bit integer formatted input + */ +static void SecFinishNumber64(SecScanSpec *spec) +{ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + if (spec->negative != 0) { + if (SECUREC_CONVERT_IS_SIGNED(spec->oriConvChr)) { + if (spec->number64 > SECUREC_MIN_64BITS_NEG_VALUE) { + spec->number64 = SECUREC_MIN_64BITS_NEG_VALUE; + } else { + spec->number64 = (SecUnsignedInt64)(0U - spec->number64); /* Wrap with unsigned int64 numbers */ + } + if (spec->beyondMax != 0) { + spec->number64 = SECUREC_MIN_64BITS_NEG_VALUE; + } + } else { /* For o, u, x, X, p */ + spec->number64 = (SecUnsignedInt64)(0U - spec->number64); /* Wrap with unsigned int64 numbers */ + if (spec->beyondMax != 0) { + spec->number64 = SECUREC_MAX_64BITS_VALUE; + } + } + } else { + if (SECUREC_CONVERT_IS_SIGNED(spec->oriConvChr)) { + if (spec->number64 > SECUREC_MAX_64BITS_POS_VALUE) { + spec->number64 = SECUREC_MAX_64BITS_POS_VALUE; + } + if (spec->beyondMax != 0) { + spec->number64 = SECUREC_MAX_64BITS_POS_VALUE; + } + } else { + if (spec->beyondMax != 0) { + spec->number64 = SECUREC_MAX_64BITS_VALUE; + } + } + } +#else + if (spec->negative != 0) { +#if defined(__hpux) + if (spec->oriConvChr != 'p') { + spec->number64 = (SecUnsignedInt64)(0U - spec->number64); /* Wrap with unsigned int64 numbers */ + } +#else + spec->number64 = (SecUnsignedInt64)(0U - spec->number64); /* Wrap with unsigned int64 numbers */ +#endif + } +#endif + return; +} + +#if SECUREC_ENABLE_SCANF_FILE + +/* + * Adjust the pointer position of the file stream + */ +SECUREC_INLINE void SecSeekStream(SecFileStream *stream) +{ + if (stream->count == 0) { + if (feof(stream->pf) != 0) { + /* File pointer at the end of file, don't need to seek back */ + stream->base[0] = '\0'; + return; + } + } + /* Seek to original position, for file read, but nothing to input */ + if (fseek(stream->pf, stream->oriFilePos, SEEK_SET) != 0) { + /* Seek failed, ignore it */ + stream->oriFilePos = 0; + return; + } + + if (stream->fileRealRead > 0) { /* Do not seek without input data */ +#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) + size_t residue = stream->fileRealRead % SECUREC_BUFFERED_BLOK_SIZE; + size_t loops; + for (loops = 0; loops < (stream->fileRealRead / SECUREC_BUFFERED_BLOK_SIZE); ++loops) { + if (fread(stream->base, (size_t)SECUREC_BUFFERED_BLOK_SIZE, (size_t)1, stream->pf) != (size_t)1) { + break; + } + } + if (residue != 0) { + long curFilePos; + if (fread(stream->base, residue, (size_t)1, stream->pf) != (size_t)1) { + return; + } + curFilePos = ftell(stream->pf); + if (curFilePos < stream->oriFilePos || + (size_t)(unsigned long)(curFilePos - stream->oriFilePos) < stream->fileRealRead) { + /* Try to remedy the problem */ + long adjustNum = (long)(stream->fileRealRead - (size_t)(unsigned long)(curFilePos - stream->oriFilePos)); + (void)fseek(stream->pf, adjustNum, SEEK_CUR); + } + } +#else + /* Seek from oriFilePos. Regardless of the integer sign problem, call scanf will not read very large data */ + if (fseek(stream->pf, (long)stream->fileRealRead, SEEK_CUR) != 0) { + /* Seek failed, ignore it */ + stream->oriFilePos = 0; + return; + } +#endif + } + return; +} + +/* + * Adjust the pointer position of the file stream and free memory + */ +SECUREC_INLINE void SecAdjustStream(SecFileStream *stream) +{ + if ((stream->flag & SECUREC_FILE_STREAM_FLAG) != 0 && stream->base != NULL) { + SecSeekStream(stream); + SECUREC_FREE(stream->base); + stream->base = NULL; + } + return; +} +#endif + +SECUREC_INLINE void SecSkipSpaceFormat(const SecUnsignedChar **format) +{ + const SecUnsignedChar *fmt = *format; + while (SecIsSpace((SecInt)(int)(*fmt)) != 0) { + ++fmt; + } + *format = fmt; +} + +#if !defined(SECUREC_FOR_WCHAR) && defined(SECUREC_COMPATIBLE_VERSION) +/* + * Handling multi-character characters + */ +SECUREC_INLINE int SecDecodeLeadByte(SecScanSpec *spec, const SecUnsignedChar **format, SecFileStream *stream) +{ +#if SECUREC_HAVE_MBTOWC + const SecUnsignedChar *fmt = *format; + int ch1 = (int)spec->ch; + int ch2 = SecGetChar(stream, &(spec->charCount)); + spec->ch = (SecInt)ch2; + if (*fmt == SECUREC_CHAR('\0') || (int)(*fmt) != ch2) { + /* in console mode, ungetc twice may cause problem */ + SecUnGetChar(ch2, stream, &(spec->charCount)); + SecUnGetChar(ch1, stream, &(spec->charCount)); + return -1; + } + ++fmt; + if ((unsigned int)MB_CUR_MAX >= SECUREC_UTF8_BOM_HEADER_SIZE && + (((unsigned char)ch1 & SECUREC_UTF8_LEAD_1ST) == SECUREC_UTF8_LEAD_1ST) && + (((unsigned char)ch2 & SECUREC_UTF8_LEAD_2ND) == SECUREC_UTF8_LEAD_2ND)) { + /* This char is very likely to be a UTF-8 char */ + wchar_t tempWChar; + char temp[SECUREC_MULTI_BYTE_MAX_LEN]; + int ch3 = (int)SecGetChar(stream, &(spec->charCount)); + spec->ch = (SecInt)ch3; + if (*fmt == SECUREC_CHAR('\0') || (int)(*fmt) != ch3) { + SecUnGetChar(ch3, stream, &(spec->charCount)); + return -1; + } + temp[0] = (char)ch1; + temp[1] = (char)ch2; /* 1 index of second character */ + temp[2] = (char)ch3; /* 2 index of third character */ + temp[3] = '\0'; /* 3 of string terminator position */ + if (mbtowc(&tempWChar, temp, sizeof(temp)) > 0) { + /* Succeed */ + ++fmt; + --spec->charCount; + } else { + SecUnGetChar(ch3, stream, &(spec->charCount)); + } + } + --spec->charCount; /* Only count as one character read */ + *format = fmt; + return 0; +#else + SecUnGetChar(spec->ch, stream, &(spec->charCount)); + (void)format; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + return -1; +#endif +} + +SECUREC_INLINE int SecFilterWcharInFormat(SecScanSpec *spec, const SecUnsignedChar **format, SecFileStream *stream) +{ + if (SecIsLeadByte(spec->ch) != 0) { + if (SecDecodeLeadByte(spec, format, stream) != 0) { + return -1; + } + } + return 0; +} +#endif + +/* + * Resolving sequence of characters from %[ format, format wile point to ']' + */ +SECUREC_INLINE int SecSetupBracketTable(const SecUnsignedChar **format, SecBracketTable *bracketTable) +{ + const SecUnsignedChar *fmt = *format; + SecUnsignedChar prevChar = 0; +#if !(defined(SECUREC_COMPATIBLE_WIN_FORMAT)) + if (*fmt == SECUREC_CHAR('{')) { + return -1; + } +#endif + /* For building "table" data */ + ++fmt; /* Skip [ */ + bracketTable->mask = 0; /* Set all bits to 0 */ + if (*fmt == SECUREC_CHAR('^')) { + ++fmt; + bracketTable->mask = (unsigned char)0xffU; /* Use 0xffU to set all bits to 1 */ + } + if (*fmt == SECUREC_CHAR(']')) { + prevChar = SECUREC_CHAR(']'); + ++fmt; + SecBracketSetBit(bracketTable->table, SECUREC_CHAR(']')); + } + while (*fmt != SECUREC_CHAR('\0') && *fmt != SECUREC_CHAR(']')) { + SecUnsignedChar expCh = *fmt; + ++fmt; + if (expCh != SECUREC_CHAR('-') || prevChar == 0 || *fmt == SECUREC_CHAR(']')) { + /* Normal character */ + prevChar = expCh; + SecBracketSetBit(bracketTable->table, expCh); + } else { + /* For %[a-z] */ + expCh = *fmt; /* Get end of range */ + ++fmt; + if (prevChar <= expCh) { /* %[a-z] %[a-a] */ + SecBracketSetBitRange(bracketTable->table, prevChar, expCh); + } else { + /* For %[z-a] */ +#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) + /* Swap start and end characters */ + SecBracketSetBitRange(bracketTable->table, expCh, prevChar); +#else + SecBracketSetBit(bracketTable->table, SECUREC_CHAR('-')); + SecBracketSetBit(bracketTable->table, expCh); +#endif + } + prevChar = 0; + } + } + *format = fmt; + return 0; +} + +#ifdef SECUREC_FOR_WCHAR +SECUREC_INLINE int SecInputForWchar(SecScanSpec *spec) +{ + void *endPtr = spec->argPtr; + if (spec->isWCharOrLong > 0) { + *(wchar_t UNALIGNED *)endPtr = (wchar_t)spec->ch; + endPtr = (wchar_t *)endPtr + 1; + --spec->arrayWidth; + } else { +#if SECUREC_HAVE_WCTOMB + int temp; + char tmpBuf[SECUREC_MB_LEN + 1]; + SECUREC_MASK_MSVC_CRT_WARNING temp = wctomb(tmpBuf, (wchar_t)spec->ch); + SECUREC_END_MASK_MSVC_CRT_WARNING + if (temp <= 0 || (size_t)(unsigned int)temp > sizeof(tmpBuf)) { + /* If wctomb error, then ignore character */ + return 0; + } + if (((size_t)(unsigned int)temp) > spec->arrayWidth) { + return -1; + } + if (memcpy_s(endPtr, spec->arrayWidth, tmpBuf, (size_t)(unsigned int)temp) != EOK) { + return -1; + } + endPtr = (char *)endPtr + temp; + spec->arrayWidth -= (size_t)(unsigned int)temp; +#else + return -1; +#endif + } + spec->argPtr = endPtr; + return 0; +} +#endif + +#ifndef SECUREC_FOR_WCHAR +#if SECUREC_HAVE_WCHART +SECUREC_INLINE wchar_t SecConvertInputCharToWchar(SecScanSpec *spec, SecFileStream *stream) +{ + wchar_t tempWChar = L'?'; /* Set default char is ? */ +#if SECUREC_HAVE_MBTOWC + char temp[SECUREC_MULTI_BYTE_MAX_LEN + 1]; + temp[0] = (char)spec->ch; + temp[1] = '\0'; +#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) + if (SecIsLeadByte(spec->ch) != 0) { + spec->ch = SecGetChar(stream, &(spec->charCount)); + temp[1] = (char)spec->ch; + temp[2] = '\0'; /* 2 of string terminator position */ + } + if (mbtowc(&tempWChar, temp, sizeof(temp)) <= 0) { + /* No string termination error for tool */ + tempWChar = L'?'; + } +#else + if (SecIsLeadByte(spec->ch) != 0) { + int convRes = 0; + int di = 1; + /* On Linux like system, the string is encoded in UTF-8 */ + while (convRes <= 0 && di < (int)MB_CUR_MAX && di < SECUREC_MULTI_BYTE_MAX_LEN) { + spec->ch = SecGetChar(stream, &(spec->charCount)); + temp[di] = (char)spec->ch; + ++di; + temp[di] = '\0'; + convRes = mbtowc(&tempWChar, temp, sizeof(temp)); + } + if (convRes <= 0) { + tempWChar = L'?'; + } + } else { + if (mbtowc(&tempWChar, temp, sizeof(temp)) <= 0) { + tempWChar = L'?'; + } + } +#endif +#else + (void)spec; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + (void)stream; /* To clear e438 last value assigned not used , the compiler will optimize this code */ +#endif /* SECUREC_HAVE_MBTOWC */ + + return tempWChar; +} +#endif /* SECUREC_HAVE_WCHART */ + +SECUREC_INLINE int SecInputForChar(SecScanSpec *spec, SecFileStream *stream) +{ + void *endPtr = spec->argPtr; + if (spec->isWCharOrLong > 0) { +#if SECUREC_HAVE_WCHART + *(wchar_t UNALIGNED *)endPtr = SecConvertInputCharToWchar(spec, stream); + endPtr = (wchar_t *)endPtr + 1; + --spec->arrayWidth; +#else + (void)stream; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + return -1; +#endif + } else { + *(char *)endPtr = (char)spec->ch; + endPtr = (char *)endPtr + 1; + --spec->arrayWidth; + } + spec->argPtr = endPtr; + return 0; +} +#endif + +/* + * Scan digital part of %d %i %o %u %x %p. + * Return 0 OK + */ +SECUREC_INLINE int SecInputNumberDigital(SecFileStream *stream, SecScanSpec *spec) +{ + static void (* const secFinishNumber[SECUREC_DECODE_NUMBER_FUNC_NUM])(SecScanSpec *spec) = { + SecFinishNumber, SecFinishNumber64 + }; + while (SECUREC_FILED_WIDTH_ENOUGH(spec)) { + spec->ch = SecGetChar(stream, &(spec->charCount)); + /* Decode ch to number */ + if (SecDecodeNumber(spec) != 0) { + SecUnGetChar(spec->ch, stream, &(spec->charCount)); + break; + } + SECUREC_FILED_WIDTH_DEC(spec); /* Must be behind un get char, otherwise the logic is incorrect */ + spec->numberState = SECUREC_NUMBER_STATE_STARTED; + } + /* Handling integer negative numbers and beyond max */ + (*secFinishNumber[spec->numberArgType])(spec); + if (spec->numberState == SECUREC_NUMBER_STATE_STARTED) { + return 0; + } + return -1; +} + +/* + * Scan %d %i %o %u %x %p. + * Return 0 OK + */ +SECUREC_INLINE int SecInputNumber(SecFileStream *stream, SecScanSpec *spec) +{ + /* Character already read */ + if (spec->ch == SECUREC_CHAR('+') || spec->ch == SECUREC_CHAR('-')) { + if (spec->ch == SECUREC_CHAR('-')) { + spec->negative = 1; +#if SECUREC_IN_KERNEL + /* In kernel Refuse to enter negative number */ + if (SECUREC_CONVERT_IS_UNSIGNED(spec->oriConvChr)) { + return -1; + } +#endif + } + SECUREC_FILED_WIDTH_DEC(spec); /* Do not need to check width here, must be greater than 0 */ + spec->ch = SecGetChar(stream, &(spec->charCount)); /* Eat + or - */ + spec->ch = SecGetChar(stream, &(spec->charCount)); /* Get next character, used for the '0' judgments */ + SecUnGetChar(spec->ch, stream, &(spec->charCount)); /* Not sure if it was actually read, so push back */ + } + + if (spec->oriConvChr == 'i') { + spec->convChr = 'd'; /* The i could be d, o, or x, use d as default */ + } + + if (spec->ch == SECUREC_CHAR('0') && (spec->oriConvChr == 'x' || spec->oriConvChr == 'i') && + SECUREC_FILED_WIDTH_ENOUGH(spec)) { + /* Input string begin with 0, may be 0x123 0X123 0123 0x 01 0yy 09 0 0ab 00 */ + SECUREC_FILED_WIDTH_DEC(spec); + spec->ch = SecGetChar(stream, &(spec->charCount)); /* ch is '0' */ + + /* Read only '0' due to width limitation */ + if (!SECUREC_FILED_WIDTH_ENOUGH(spec)) { + /* The number or number64 in spec has been set 0 */ + return 0; + } + + spec->ch = SecGetChar(stream, &(spec->charCount)); /* Get next char to check x or X, do not dec width */ + if ((SecChar)spec->ch == SECUREC_CHAR('x') || (SecChar)spec->ch == SECUREC_CHAR('X')) { + spec->convChr = 'x'; + SECUREC_FILED_WIDTH_DEC(spec); /* Make incorrect width for x or X */ + } else { + if (spec->oriConvChr == 'i') { + spec->convChr = 'o'; + } + /* For "0y" "08" "01" "0a" ... ,push the 'y' '8' '1' 'a' back */ + SecUnGetChar(spec->ch, stream, &(spec->charCount)); + /* Since 0 has been read, it indicates that a valid character has been read */ + spec->numberState = SECUREC_NUMBER_STATE_STARTED; + } + } + return SecInputNumberDigital(stream, spec); +} + +/* + * Scan %c %s %[ + * Return 0 OK + */ +SECUREC_INLINE int SecInputString(SecFileStream *stream, SecScanSpec *spec, + const SecBracketTable *bracketTable, int *doneCount) +{ + void *startPtr = spec->argPtr; + int suppressed = 0; + int errNoMem = 0; + + while (SECUREC_FILED_WIDTH_ENOUGH(spec)) { + SECUREC_FILED_WIDTH_DEC(spec); + spec->ch = SecGetChar(stream, &(spec->charCount)); + /* + * The char condition or string condition and bracket condition. + * Only supports wide characters with a maximum length of two bytes + */ + if (spec->ch != SECUREC_EOF && (SecCanInputCharacter(spec->convChr) != 0 || + SecCanInputString(spec->convChr, spec->ch) != 0 || + SecCanInputForBracket(spec->convChr, spec->ch, bracketTable) != 0)) { + if (spec->suppress != 0) { + /* Used to identify processed data for %*, use argPtr to identify will cause 613, so use suppressed */ + suppressed = 1; + continue; + } + /* Now suppress is not set */ + if (spec->arrayWidth == 0) { + errNoMem = 1; /* We have exhausted the user's buffer */ + break; + } +#ifdef SECUREC_FOR_WCHAR + errNoMem = SecInputForWchar(spec); +#else + errNoMem = SecInputForChar(spec, stream); +#endif + if (errNoMem != 0) { + break; + } + } else { + SecUnGetChar(spec->ch, stream, &(spec->charCount)); + break; + } + } + + if (errNoMem != 0) { + /* In case of error, blank out the input buffer */ + SecAddEndingZero(startPtr, spec); + return -1; + } + if ((spec->suppress != 0 && suppressed == 0) || + (spec->suppress == 0 && startPtr == spec->argPtr)) { + /* No input was scanned */ + return -1; + } + if (spec->convChr != 'c') { + /* Add null-terminate for strings */ + SecAddEndingZero(spec->argPtr, spec); + } + if (spec->suppress == 0) { + *doneCount = *doneCount + 1; + } + return 0; +} + +#ifdef SECUREC_FOR_WCHAR +/* + * Allocate buffer for wchar version of %[. + * Return 0 OK + */ +SECUREC_INLINE int SecAllocBracketTable(SecBracketTable *bracketTable) +{ + if (bracketTable->table == NULL) { + /* Table should be freed after use */ + bracketTable->table = (unsigned char *)SECUREC_MALLOC(SECUREC_BRACKET_TABLE_SIZE); + if (bracketTable->table == NULL) { + return -1; + } + } + return 0; +} + +/* + * Free buffer for wchar version of %[ + */ +SECUREC_INLINE void SecFreeBracketTable(SecBracketTable *bracketTable) +{ + if (bracketTable->table != NULL) { + SECUREC_FREE(bracketTable->table); + bracketTable->table = NULL; + } +} +#endif + +#ifdef SECUREC_FOR_WCHAR +/* + * Formatting input core functions for wchar version.Called by a function such as vswscanf_s + */ +int SecInputSW(SecFileStream *stream, const wchar_t *cFormat, va_list argList) +#else +/* + * Formatting input core functions for char version.Called by a function such as vsscanf_s + */ +int SecInputS(SecFileStream *stream, const char *cFormat, va_list argList) +#endif +{ + const SecUnsignedChar *format = (const SecUnsignedChar *)cFormat; + SecBracketTable bracketTable = SECUREC_INIT_BRACKET_TABLE; + SecScanSpec spec; + int doneCount = 0; + int formatError = 0; + int paraIsNull = 0; + int match = 0; /* When % is found , inc this value */ + int errRet = 0; +#if SECUREC_ENABLE_SCANF_FLOAT + SecFloatSpec floatSpec; + SecInitFloatSpec(&floatSpec); +#endif + spec.ch = 0; /* Need to initialize to 0 */ + spec.charCount = 0; /* Need to initialize to 0 */ + + /* Format must not NULL, use err < 1 to clear 845 */ + while (errRet < 1 && *format != SECUREC_CHAR('\0')) { + /* Skip space in format and space in input */ + if (SecIsSpace((SecInt)(int)(*format)) != 0) { + /* Read first no space char */ + spec.ch = SecSkipSpaceChar(stream, &(spec.charCount)); + /* Read the EOF cannot be returned directly here, because the case of " %n" needs to be handled */ + /* Put fist no space char backup. put EOF back is also OK, and to modify the character count */ + SecUnGetChar(spec.ch, stream, &(spec.charCount)); + SecSkipSpaceFormat(&format); + continue; + } + + if (*format != SECUREC_CHAR('%')) { + spec.ch = SecGetChar(stream, &(spec.charCount)); + if ((int)(*format) != (int)(spec.ch)) { + SecUnGetChar(spec.ch, stream, &(spec.charCount)); + break; + } + ++format; +#if !defined(SECUREC_FOR_WCHAR) && defined(SECUREC_COMPATIBLE_VERSION) + if (SecFilterWcharInFormat(&spec, &format, stream) != 0) { + break; + } +#endif + continue; + } + + /* Now *format is % */ + /* Set default value for each % */ + SecSetDefaultScanSpec(&spec); + if (SecDecodeScanFlag(&format, &spec) != 0) { + formatError = 1; + ++errRet; + continue; + } + if (!SECUREC_FILED_WIDTH_ENOUGH(&spec)) { + /* 0 width in format */ + ++errRet; + continue; + } + + /* Update wchar flag for %S %C */ + SecUpdateWcharFlagByType(*format, &spec); + + spec.convChr = SECUREC_TO_LOWERCASE(*format); + spec.oriConvChr = spec.convChr; /* convChr may be modified to handle integer logic */ + if (spec.convChr != 'n') { + if (spec.convChr != 'c' && spec.convChr != SECUREC_BRACE) { + spec.ch = SecSkipSpaceChar(stream, &(spec.charCount)); + } else { + spec.ch = SecGetChar(stream, &(spec.charCount)); + } + if (spec.ch == SECUREC_EOF) { + ++errRet; + continue; + } + } + + /* Now no 0 width in format and get one char from input */ + switch (spec.oriConvChr) { + case 'c': /* Also 'C' */ + if (spec.widthSet == 0) { + spec.widthSet = 1; + spec.width = 1; + } + /* fall-through */ /* FALLTHRU */ + case 's': /* Also 'S': */ + /* fall-through */ /* FALLTHRU */ + case SECUREC_BRACE: + /* Unset last char to stream */ + SecUnGetChar(spec.ch, stream, &(spec.charCount)); + /* Check dest buffer and size */ + if (spec.suppress == 0) { + spec.argPtr = (void *)va_arg(argList, void *); + if (spec.argPtr == NULL) { + paraIsNull = 1; + ++errRet; + continue; + } + /* Get the next argument, size of the array in characters */ + spec.arrayWidth = SECUREC_GET_ARRAYWIDTH(argList); + if (SECUREC_ARRAY_WIDTH_IS_WRONG(spec)) { + /* Do not clear buffer just go error */ + ++errRet; + continue; + } + /* One element is needed for '\0' for %s and %[ */ + if (spec.convChr != 'c') { + --spec.arrayWidth; + } + } else { + /* Set argPtr to NULL is necessary, in suppress mode we don't use argPtr to store data */ + spec.argPtr = NULL; + } + + if (spec.convChr == SECUREC_BRACE) { + /* Malloc when first %[ is meet for wchar version */ +#ifdef SECUREC_FOR_WCHAR + if (SecAllocBracketTable(&bracketTable) != 0) { + ++errRet; + continue; + } +#endif + (void)SECUREC_MEMSET_FUNC_OPT(bracketTable.table, 0, (size_t)SECUREC_BRACKET_TABLE_SIZE); + if (SecSetupBracketTable(&format, &bracketTable) != 0) { + ++errRet; + continue; + } + + if (*format == SECUREC_CHAR('\0')) { + /* Default add string terminator */ + SecAddEndingZero(spec.argPtr, &spec); + ++errRet; + /* Truncated format */ + continue; + } + } + + /* Set completed. Now read string or character */ + if (SecInputString(stream, &spec, &bracketTable, &doneCount) != 0) { + ++errRet; + continue; + } + break; + case 'p': + /* Make %hp same as %p */ + spec.numberWidth = SECUREC_NUM_WIDTH_INT; +#ifdef SECUREC_ON_64BITS + spec.numberArgType = 1; +#endif + /* fall-through */ /* FALLTHRU */ + case 'o': /* fall-through */ /* FALLTHRU */ + case 'u': /* fall-through */ /* FALLTHRU */ + case 'd': /* fall-through */ /* FALLTHRU */ + case 'i': /* fall-through */ /* FALLTHRU */ + case 'x': + /* Unset last char to stream */ + SecUnGetChar(spec.ch, stream, &(spec.charCount)); + if (SecInputNumber(stream, &spec) != 0) { + ++errRet; + continue; + } + if (spec.suppress == 0) { + spec.argPtr = (void *)va_arg(argList, void *); + if (spec.argPtr == NULL) { + paraIsNull = 1; + ++errRet; + continue; + } + SecAssignNumber(&spec); + ++doneCount; + } + break; + case 'n': /* Char count */ + if (spec.suppress == 0) { + spec.argPtr = (void *)va_arg(argList, void *); + if (spec.argPtr == NULL) { + paraIsNull = 1; + ++errRet; + continue; + } + spec.number = (unsigned long)(unsigned int)(spec.charCount); + spec.numberArgType = 0; + SecAssignNumber(&spec); + } + break; + case 'e': /* fall-through */ /* FALLTHRU */ + case 'f': /* fall-through */ /* FALLTHRU */ + case 'g': /* Scan a float */ + /* Unset last char to stream */ + SecUnGetChar(spec.ch, stream, &(spec.charCount)); +#if SECUREC_ENABLE_SCANF_FLOAT + if (SecInputFloat(stream, &spec, &floatSpec) != 0) { + ++errRet; + continue; + } + if (spec.suppress == 0) { + spec.argPtr = (void *)va_arg(argList, void *); + if (spec.argPtr == NULL) { + ++errRet; + paraIsNull = 1; + continue; + } + if (SecAssignFloat(&floatSpec, &spec) != 0) { + ++errRet; + continue; + } + ++doneCount; + } + break; +#else /* SECUREC_ENABLE_SCANF_FLOAT */ + ++errRet; + continue; +#endif + default: + if ((int)(*format) != (int)spec.ch) { + SecUnGetChar(spec.ch, stream, &(spec.charCount)); + formatError = 1; + ++errRet; + continue; + } else { + --match; /* Compensate for the self-increment of the following code */ + } + break; + } + ++match; + ++format; + } + +#ifdef SECUREC_FOR_WCHAR + SecFreeBracketTable(&bracketTable); +#endif + +#if SECUREC_ENABLE_SCANF_FLOAT + SecFreeFloatSpec(&floatSpec, &doneCount); +#endif + +#if SECUREC_ENABLE_SCANF_FILE + SecAdjustStream(stream); +#endif + + if (spec.ch == SECUREC_EOF) { + return ((doneCount != 0 || match != 0) ? doneCount : SECUREC_SCANF_EINVAL); + } + if (formatError != 0 || paraIsNull != 0) { + /* Invalid Input Format or parameter, but not meet EOF */ + return SECUREC_SCANF_ERROR_PARA; + } + return doneCount; +} + +#if SECUREC_ENABLE_SCANF_FILE +/* + * Get char from stream use std function + */ +SECUREC_INLINE SecInt SecGetCharFromStream(const SecFileStream *stream) +{ + SecInt ch; + ch = SECUREC_GETC(stream->pf); + return ch; +} + +/* + * Try to read the BOM header, when meet a BOM head, discard it, then data is Aligned to base + */ +SECUREC_INLINE void SecReadAndSkipBomHeader(SecFileStream *stream) +{ + /* Use size_t type conversion to clean e747 */ + stream->count = fread(stream->base, (size_t)1, (size_t)SECUREC_BOM_HEADER_SIZE, stream->pf); + if (stream->count > SECUREC_BOM_HEADER_SIZE) { + stream->count = 0; + } + if (SECUREC_BEGIN_WITH_BOM(stream->base, stream->count)) { + /* It's BOM header, discard it */ + stream->count = 0; + } +} + +/* + * Get char from file stream or buffer + */ +SECUREC_INLINE SecInt SecGetCharFromFile(SecFileStream *stream) +{ + SecInt ch; + if (stream->count < sizeof(SecChar)) { + /* Load file to buffer */ + size_t len; + if (stream->base != NULL) { + /* Put the last unread data in the buffer head */ + for (len = 0; len < stream->count; ++len) { + stream->base[len] = stream->cur[len]; + } + } else { + stream->oriFilePos = ftell(stream->pf); /* Save original file read position */ + if (stream->oriFilePos == -1) { + /* It may be a pipe stream */ + stream->flag = SECUREC_PIPE_STREAM_FLAG; + return SecGetCharFromStream(stream); + } + /* Reserve the length of BOM head */ + stream->base = (char *)SECUREC_MALLOC(SECUREC_BUFFERED_BLOK_SIZE + + SECUREC_BOM_HEADER_SIZE + sizeof(SecChar)); /* To store '\0' and aligned to wide char */ + if (stream->base == NULL) { + return SECUREC_EOF; + } + /* First read file */ + if (stream->oriFilePos == 0) { + /* Make sure the data is aligned to base */ + SecReadAndSkipBomHeader(stream); + } + } + + /* Skip existing data and read data */ + len = fread(stream->base + stream->count, (size_t)1, (size_t)SECUREC_BUFFERED_BLOK_SIZE, stream->pf); + if (len > SECUREC_BUFFERED_BLOK_SIZE) { /* It won't happen, */ + len = 0; + } + stream->count += len; + stream->cur = stream->base; + stream->flag |= SECUREC_LOAD_FILE_TO_MEM_FLAG; + stream->base[stream->count] = '\0'; /* For tool Warning string null */ + } + + SECUREC_GET_CHAR(stream, &ch); + if (ch != SECUREC_EOF) { + stream->fileRealRead += sizeof(SecChar); + } + return ch; +} +#endif + +/* + * Get char for wchar version + */ +SECUREC_INLINE SecInt SecGetChar(SecFileStream *stream, int *counter) +{ + *counter = *counter + 1; /* Always plus 1 */ + /* The main scenario is scanf str */ + if ((stream->flag & SECUREC_MEM_STR_FLAG) != 0) { + SecInt ch; + SECUREC_GET_CHAR(stream, &ch); + return ch; + } +#if SECUREC_ENABLE_SCANF_FILE + if ((stream->flag & SECUREC_FILE_STREAM_FLAG) != 0) { + return SecGetCharFromFile(stream); + } + if ((stream->flag & SECUREC_PIPE_STREAM_FLAG) != 0) { + return SecGetCharFromStream(stream); + } +#endif + return SECUREC_EOF; +} + +/* + * Unget Public realization char for wchar and char version + */ +SECUREC_INLINE void SecUnGetCharImpl(SecInt ch, SecFileStream *stream) +{ + if ((stream->flag & SECUREC_MEM_STR_FLAG) != 0) { + SECUREC_UN_GET_CHAR(stream); + return; + } +#if SECUREC_ENABLE_SCANF_FILE + if ((stream->flag & SECUREC_LOAD_FILE_TO_MEM_FLAG) != 0) { + SECUREC_UN_GET_CHAR(stream); + if (stream->fileRealRead > 0) { + stream->fileRealRead -= sizeof(SecChar); + } + return; + } + if ((stream->flag & SECUREC_PIPE_STREAM_FLAG) != 0) { + (void)SECUREC_UN_GETC(ch, stream->pf); + return; + } +#else + (void)ch; /* To clear e438 last value assigned not used , the compiler will optimize this code */ +#endif +} + +/* + * Unget char for char version + */ +SECUREC_INLINE void SecUnGetChar(SecInt ch, SecFileStream *stream, int *counter) +{ + *counter = *counter - 1; /* Always minus 1 */ + if (ch != SECUREC_EOF) { + SecUnGetCharImpl(ch, stream); + } +} + +/* + * Skip space char by isspace + */ +SECUREC_INLINE SecInt SecSkipSpaceChar(SecFileStream *stream, int *counter) +{ + SecInt ch; + do { + ch = SecGetChar(stream, counter); + if (ch == SECUREC_EOF) { + break; + } + } while (SecIsSpace(ch) != 0); + return ch; +} +#endif /* INPUT_INL_5D13A042_DC3F_4ED9_A8D1_882811274C27 */ + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/memcpy_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/memcpy_s.c new file mode 100644 index 0000000000000000000000000000000000000000..a7fd48748e50a7180c2afd8a1def9b05180eb8bc --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/memcpy_s.c @@ -0,0 +1,555 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: memcpy_s function + * Create: 2014-02-25 + */ +/* + * [Standardize-exceptions] Use unsafe function: Portability + * [reason] Use unsafe function to implement security function to maintain platform compatibility. + * And sufficient input validation is performed before calling + */ + +#include "securecutil.h" + +#if SECUREC_WITH_PERFORMANCE_ADDONS +#ifndef SECUREC_MEMCOPY_THRESHOLD_SIZE +#define SECUREC_MEMCOPY_THRESHOLD_SIZE 64UL +#endif + +#define SECUREC_SMALL_MEM_COPY(dest, src, count) do { \ + if (SECUREC_ADDR_ALIGNED_8(dest) && SECUREC_ADDR_ALIGNED_8(src)) { \ + /* Use struct assignment */ \ + switch (count) { \ + case 1: \ + *(unsigned char *)(dest) = *(const unsigned char *)(src); \ + break; \ + case 2: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 2); \ + break; \ + case 3: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 3); \ + break; \ + case 4: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 4); \ + break; \ + case 5: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 5); \ + break; \ + case 6: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 6); \ + break; \ + case 7: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 7); \ + break; \ + case 8: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 8); \ + break; \ + case 9: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 9); \ + break; \ + case 10: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 10); \ + break; \ + case 11: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 11); \ + break; \ + case 12: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 12); \ + break; \ + case 13: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 13); \ + break; \ + case 14: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 14); \ + break; \ + case 15: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 15); \ + break; \ + case 16: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 16); \ + break; \ + case 17: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 17); \ + break; \ + case 18: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 18); \ + break; \ + case 19: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 19); \ + break; \ + case 20: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 20); \ + break; \ + case 21: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 21); \ + break; \ + case 22: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 22); \ + break; \ + case 23: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 23); \ + break; \ + case 24: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 24); \ + break; \ + case 25: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 25); \ + break; \ + case 26: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 26); \ + break; \ + case 27: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 27); \ + break; \ + case 28: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 28); \ + break; \ + case 29: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 29); \ + break; \ + case 30: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 30); \ + break; \ + case 31: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 31); \ + break; \ + case 32: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 32); \ + break; \ + case 33: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 33); \ + break; \ + case 34: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 34); \ + break; \ + case 35: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 35); \ + break; \ + case 36: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 36); \ + break; \ + case 37: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 37); \ + break; \ + case 38: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 38); \ + break; \ + case 39: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 39); \ + break; \ + case 40: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 40); \ + break; \ + case 41: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 41); \ + break; \ + case 42: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 42); \ + break; \ + case 43: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 43); \ + break; \ + case 44: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 44); \ + break; \ + case 45: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 45); \ + break; \ + case 46: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 46); \ + break; \ + case 47: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 47); \ + break; \ + case 48: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 48); \ + break; \ + case 49: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 49); \ + break; \ + case 50: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 50); \ + break; \ + case 51: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 51); \ + break; \ + case 52: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 52); \ + break; \ + case 53: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 53); \ + break; \ + case 54: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 54); \ + break; \ + case 55: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 55); \ + break; \ + case 56: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 56); \ + break; \ + case 57: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 57); \ + break; \ + case 58: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 58); \ + break; \ + case 59: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 59); \ + break; \ + case 60: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 60); \ + break; \ + case 61: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 61); \ + break; \ + case 62: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 62); \ + break; \ + case 63: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 63); \ + break; \ + case 64: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 64); \ + break; \ + default: \ + /* Do nothing */ \ + break; \ + } /* END switch */ \ + } else { \ + unsigned char *tmpDest_ = (unsigned char *)(dest); \ + const unsigned char *tmpSrc_ = (const unsigned char *)(src); \ + switch (count) { \ + case 64: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 63: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 62: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 61: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 60: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 59: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 58: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 57: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 56: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 55: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 54: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 53: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 52: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 51: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 50: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 49: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 48: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 47: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 46: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 45: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 44: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 43: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 42: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 41: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 40: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 39: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 38: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 37: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 36: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 35: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 34: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 33: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 32: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 31: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 30: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 29: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 28: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 27: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 26: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 25: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 24: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 23: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 22: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 21: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 20: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 19: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 18: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 17: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 16: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 15: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 14: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 13: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 12: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 11: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 10: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 9: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 8: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 7: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 6: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 5: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 4: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 3: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 2: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 1: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + default: \ + /* Do nothing */ \ + break; \ + } \ + } \ +} SECUREC_WHILE_ZERO + +/* + * Performance optimization + */ +#define SECUREC_MEMCPY_OPT(dest, src, count) do { \ + if ((count) > SECUREC_MEMCOPY_THRESHOLD_SIZE) { \ + SECUREC_MEMCPY_WARP_OPT((dest), (src), (count)); \ + } else { \ + SECUREC_SMALL_MEM_COPY((dest), (src), (count)); \ + } \ +} SECUREC_WHILE_ZERO +#endif + +/* + * Handling errors + */ +SECUREC_INLINE errno_t SecMemcpyError(void *dest, size_t destMax, const void *src, size_t count) +{ + if (destMax == 0 || destMax > SECUREC_MEM_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("memcpy_s"); + return ERANGE; + } + if (dest == NULL || src == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("memcpy_s"); + if (dest != NULL) { + (void)SECUREC_MEMSET_FUNC_OPT(dest, 0, destMax); + return EINVAL_AND_RESET; + } + return EINVAL; + } + if (count > destMax) { + (void)SECUREC_MEMSET_FUNC_OPT(dest, 0, destMax); + SECUREC_ERROR_INVALID_RANGE("memcpy_s"); + return ERANGE_AND_RESET; + } + if (SECUREC_MEMORY_IS_OVERLAP(dest, src, count)) { + (void)SECUREC_MEMSET_FUNC_OPT(dest, 0, destMax); + SECUREC_ERROR_BUFFER_OVERLAP("memcpy_s"); + return EOVERLAP_AND_RESET; + } + /* Count is 0 or dest equal src also ret EOK */ + return EOK; +} + +#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) + /* + * The fread API in windows will call memcpy_s and pass 0xffffffff to destMax. + * To avoid the failure of fread, we don't check desMax limit. + */ +#define SECUREC_MEMCPY_PARAM_OK(dest, destMax, src, count) (SECUREC_LIKELY((count) <= (destMax) && \ + (dest) != NULL && (src) != NULL && \ + (count) > 0 && SECUREC_MEMORY_NO_OVERLAP((dest), (src), (count)))) +#else +#define SECUREC_MEMCPY_PARAM_OK(dest, destMax, src, count) (SECUREC_LIKELY((count) <= (destMax) && \ + (dest) != NULL && (src) != NULL && (destMax) <= SECUREC_MEM_MAX_LEN && \ + (count) > 0 && SECUREC_MEMORY_NO_OVERLAP((dest), (src), (count)))) +#endif + +/* + * + * The memcpy_s function copies n characters from the object pointed to by src into the object pointed to by dest + * + * + * dest Destination buffer. + * destMax Size of the destination buffer. + * src Buffer to copy from. + * count Number of characters to copy + * + * + * dest buffer is updated. + * + * + * EOK Success + * EINVAL dest is NULL and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN + * EINVAL_AND_RESET dest != NULL and src is NULL and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN + * ERANGE destMax > SECUREC_MEM_MAX_LEN or destMax is 0 + * ERANGE_AND_RESET count > destMax and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN + * and dest != NULL and src != NULL + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and + * count <= destMax destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN and dest != NULL + * and src != NULL and dest != src + * + * if an error occurred, dest will be filled with 0. + * If the source and destination overlap, the behavior of memcpy_s is undefined. + * Use memmove_s to handle overlapping regions. + */ +errno_t memcpy_s(void *dest, size_t destMax, const void *src, size_t count) +{ + if (SECUREC_MEMCPY_PARAM_OK(dest, destMax, src, count)) { + SECUREC_MEMCPY_WARP_OPT(dest, src, count); + return EOK; + } + /* Meet some runtime violation, return error code */ + return SecMemcpyError(dest, destMax, src, count); +} + +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(memcpy_s); +#endif + +#if SECUREC_WITH_PERFORMANCE_ADDONS +/* + * Performance optimization + */ +errno_t memcpy_sOptAsm(void *dest, size_t destMax, const void *src, size_t count) +{ + if (SECUREC_MEMCPY_PARAM_OK(dest, destMax, src, count)) { + SECUREC_MEMCPY_OPT(dest, src, count); + return EOK; + } + /* Meet some runtime violation, return error code */ + return SecMemcpyError(dest, destMax, src, count); +} + +/* Trim judgement on "destMax <= SECUREC_MEM_MAX_LEN" */ +errno_t memcpy_sOptTc(void *dest, size_t destMax, const void *src, size_t count) +{ + if (SECUREC_LIKELY(count <= destMax && dest != NULL && src != NULL && \ + count > 0 && SECUREC_MEMORY_NO_OVERLAP((dest), (src), (count)))) { + SECUREC_MEMCPY_OPT(dest, src, count); + return EOK; + } + /* Meet some runtime violation, return error code */ + return SecMemcpyError(dest, destMax, src, count); +} +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/memmove_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/memmove_s.c new file mode 100644 index 0000000000000000000000000000000000000000..f231f05da96682f16609c8eb62fef36567c03988 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/memmove_s.c @@ -0,0 +1,123 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: memmove_s function + * Create: 2014-02-25 + */ +/* + * [Standardize-exceptions] Use unsafe function: Portability + * [reason] Use unsafe function to implement security function to maintain platform compatibility. + * And sufficient input validation is performed before calling + */ + +#include "securecutil.h" + +#ifdef SECUREC_NOT_CALL_LIBC_CORE_API +/* + * Implementing memory data movement + */ +SECUREC_INLINE void SecUtilMemmove(void *dst, const void *src, size_t count) +{ + unsigned char *pDest = (unsigned char *)dst; + const unsigned char *pSrc = (const unsigned char *)src; + size_t maxCount = count; + + if (dst <= src || pDest >= (pSrc + maxCount)) { + /* + * Non-Overlapping Buffers + * Copy from lower addresses to higher addresses + */ + while (maxCount > 0) { + --maxCount; + *pDest = *pSrc; + ++pDest; + ++pSrc; + } + } else { + /* + * Overlapping Buffers + * Copy from higher addresses to lower addresses + */ + pDest = pDest + maxCount - 1; + pSrc = pSrc + maxCount - 1; + while (maxCount > 0) { + --maxCount; + *pDest = *pSrc; + --pDest; + --pSrc; + } + } +} +#endif + +/* + * + * The memmove_s function copies count bytes of characters from src to dest. + * This function can be assigned correctly when memory overlaps. + * + * dest Destination object. + * destMax Size of the destination buffer. + * src Source object. + * count Number of characters to copy. + * + * + * dest buffer is updated. + * + * + * EOK Success + * EINVAL dest is NULL and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN + * EINVAL_AND_RESET dest != NULL and src is NULL and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN + * ERANGE destMax > SECUREC_MEM_MAX_LEN or destMax is 0 + * ERANGE_AND_RESET count > destMax and dest != NULL and src != NULL and destMax != 0 + * and destMax <= SECUREC_MEM_MAX_LEN + * + * If an error occurred, dest will be filled with 0 when dest and destMax valid. + * If some regions of the source area and the destination overlap, memmove_s + * ensures that the original source bytes in the overlapping region are copied + * before being overwritten. + */ +errno_t memmove_s(void *dest, size_t destMax, const void *src, size_t count) +{ + if (destMax == 0 || destMax > SECUREC_MEM_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("memmove_s"); + return ERANGE; + } + if (dest == NULL || src == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("memmove_s"); + if (dest != NULL) { + (void)SECUREC_MEMSET_FUNC_OPT(dest, 0, destMax); + return EINVAL_AND_RESET; + } + return EINVAL; + } + if (count > destMax) { + (void)SECUREC_MEMSET_FUNC_OPT(dest, 0, destMax); + SECUREC_ERROR_INVALID_RANGE("memmove_s"); + return ERANGE_AND_RESET; + } + if (dest == src) { + return EOK; + } + + if (count > 0) { +#ifdef SECUREC_NOT_CALL_LIBC_CORE_API + SecUtilMemmove(dest, src, count); +#else + /* Use underlying memmove for performance consideration */ + (void)memmove(dest, src, count); +#endif + } + return EOK; +} + +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(memmove_s); +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/memset_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/memset_s.c new file mode 100644 index 0000000000000000000000000000000000000000..d9a657fd326af60ec1195b226aa762855042299b --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/memset_s.c @@ -0,0 +1,510 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: memset_s function + * Create: 2014-02-25 + */ +/* + * [Standardize-exceptions] Use unsafe function: Portability + * [reason] Use unsafe function to implement security function to maintain platform compatibility. + * And sufficient input validation is performed before calling + */ + +#include "securecutil.h" + +#define SECUREC_MEMSET_PARAM_OK(dest, destMax, count) (SECUREC_LIKELY((destMax) <= SECUREC_MEM_MAX_LEN && \ + (dest) != NULL && (count) <= (destMax))) + +#if SECUREC_WITH_PERFORMANCE_ADDONS + +/* Use union to clear strict-aliasing warning */ +typedef union { + SecStrBuf32 buf32; + SecStrBuf31 buf31; + SecStrBuf30 buf30; + SecStrBuf29 buf29; + SecStrBuf28 buf28; + SecStrBuf27 buf27; + SecStrBuf26 buf26; + SecStrBuf25 buf25; + SecStrBuf24 buf24; + SecStrBuf23 buf23; + SecStrBuf22 buf22; + SecStrBuf21 buf21; + SecStrBuf20 buf20; + SecStrBuf19 buf19; + SecStrBuf18 buf18; + SecStrBuf17 buf17; + SecStrBuf16 buf16; + SecStrBuf15 buf15; + SecStrBuf14 buf14; + SecStrBuf13 buf13; + SecStrBuf12 buf12; + SecStrBuf11 buf11; + SecStrBuf10 buf10; + SecStrBuf9 buf9; + SecStrBuf8 buf8; + SecStrBuf7 buf7; + SecStrBuf6 buf6; + SecStrBuf5 buf5; + SecStrBuf4 buf4; + SecStrBuf3 buf3; + SecStrBuf2 buf2; +} SecStrBuf32Union; +/* C standard initializes the first member of the consortium. */ +static const SecStrBuf32 g_allZero = {{ + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U +}}; +static const SecStrBuf32 g_allFF = {{ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF +}}; + +/* Clear conversion warning strict aliasing" */ +SECUREC_INLINE const SecStrBuf32Union *SecStrictAliasingCast(const SecStrBuf32 *buf) +{ + return (const SecStrBuf32Union *)buf; +} + +#ifndef SECUREC_MEMSET_THRESHOLD_SIZE +#define SECUREC_MEMSET_THRESHOLD_SIZE 32UL +#endif + +#define SECUREC_UNALIGNED_SET(dest, c, count) do { \ + unsigned char *pDest_ = (unsigned char *)(dest); \ + switch (count) { \ + case 32: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 31: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 30: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 29: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 28: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 27: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 26: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 25: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 24: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 23: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 22: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 21: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 20: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 19: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 18: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 17: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 16: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 15: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 14: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 13: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 12: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 11: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 10: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 9: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 8: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 7: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 6: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 5: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 4: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 3: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 2: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 1: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + default: \ + /* Do nothing */ \ + break; \ + } \ +} SECUREC_WHILE_ZERO + +#define SECUREC_SET_VALUE_BY_STRUCT(dest, dataName, n) do { \ + *(SecStrBuf##n *)(dest) = *(const SecStrBuf##n *)(&((SecStrictAliasingCast(&(dataName)))->buf##n)); \ +} SECUREC_WHILE_ZERO + +#define SECUREC_ALIGNED_SET_OPT_ZERO_FF(dest, c, count) do { \ + switch (c) { \ + case 0: \ + switch (count) { \ + case 1: \ + *(unsigned char *)(dest) = (unsigned char)0; \ + break; \ + case 2: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 2); \ + break; \ + case 3: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 3); \ + break; \ + case 4: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 4); \ + break; \ + case 5: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 5); \ + break; \ + case 6: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 6); \ + break; \ + case 7: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 7); \ + break; \ + case 8: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 8); \ + break; \ + case 9: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 9); \ + break; \ + case 10: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 10); \ + break; \ + case 11: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 11); \ + break; \ + case 12: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 12); \ + break; \ + case 13: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 13); \ + break; \ + case 14: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 14); \ + break; \ + case 15: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 15); \ + break; \ + case 16: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 16); \ + break; \ + case 17: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 17); \ + break; \ + case 18: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 18); \ + break; \ + case 19: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 19); \ + break; \ + case 20: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 20); \ + break; \ + case 21: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 21); \ + break; \ + case 22: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 22); \ + break; \ + case 23: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 23); \ + break; \ + case 24: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 24); \ + break; \ + case 25: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 25); \ + break; \ + case 26: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 26); \ + break; \ + case 27: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 27); \ + break; \ + case 28: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 28); \ + break; \ + case 29: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 29); \ + break; \ + case 30: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 30); \ + break; \ + case 31: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 31); \ + break; \ + case 32: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 32); \ + break; \ + default: \ + /* Do nothing */ \ + break; \ + } \ + break; \ + case 0xFF: \ + switch (count) { \ + case 1: \ + *(unsigned char *)(dest) = (unsigned char)0xffU; \ + break; \ + case 2: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 2); \ + break; \ + case 3: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 3); \ + break; \ + case 4: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 4); \ + break; \ + case 5: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 5); \ + break; \ + case 6: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 6); \ + break; \ + case 7: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 7); \ + break; \ + case 8: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 8); \ + break; \ + case 9: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 9); \ + break; \ + case 10: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 10); \ + break; \ + case 11: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 11); \ + break; \ + case 12: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 12); \ + break; \ + case 13: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 13); \ + break; \ + case 14: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 14); \ + break; \ + case 15: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 15); \ + break; \ + case 16: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 16); \ + break; \ + case 17: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 17); \ + break; \ + case 18: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 18); \ + break; \ + case 19: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 19); \ + break; \ + case 20: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 20); \ + break; \ + case 21: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 21); \ + break; \ + case 22: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 22); \ + break; \ + case 23: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 23); \ + break; \ + case 24: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 24); \ + break; \ + case 25: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 25); \ + break; \ + case 26: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 26); \ + break; \ + case 27: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 27); \ + break; \ + case 28: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 28); \ + break; \ + case 29: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 29); \ + break; \ + case 30: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 30); \ + break; \ + case 31: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 31); \ + break; \ + case 32: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 32); \ + break; \ + default: \ + /* Do nothing */ \ + break; \ + } \ + break; \ + default: \ + SECUREC_UNALIGNED_SET((dest), (c), (count)); \ + break; \ + } /* END switch */ \ +} SECUREC_WHILE_ZERO + +#define SECUREC_SMALL_MEM_SET(dest, c, count) do { \ + if (SECUREC_ADDR_ALIGNED_8((dest))) { \ + SECUREC_ALIGNED_SET_OPT_ZERO_FF((dest), (c), (count)); \ + } else { \ + SECUREC_UNALIGNED_SET((dest), (c), (count)); \ + } \ +} SECUREC_WHILE_ZERO + +/* + * Performance optimization + */ +#define SECUREC_MEMSET_OPT(dest, c, count) do { \ + if ((count) > SECUREC_MEMSET_THRESHOLD_SIZE) { \ + SECUREC_MEMSET_PREVENT_DSE((dest), (c), (count)); \ + } else { \ + SECUREC_SMALL_MEM_SET((dest), (c), (count)); \ + } \ +} SECUREC_WHILE_ZERO +#endif + +/* + * Handling errors + */ +SECUREC_INLINE errno_t SecMemsetError(void *dest, size_t destMax, int c) +{ + /* Check destMax is 0 compatible with _sp macro */ + if (destMax == 0 || destMax > SECUREC_MEM_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("memset_s"); + return ERANGE; + } + if (dest == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("memset_s"); + return EINVAL; + } + SECUREC_MEMSET_PREVENT_DSE(dest, c, destMax); /* Set entire buffer to value c */ + SECUREC_ERROR_INVALID_RANGE("memset_s"); + return ERANGE_AND_RESET; +} + +/* + * + * The memset_s function copies the value of c (converted to an unsigned char) + * into each of the first count characters of the object pointed to by dest. + * + * + * dest Pointer to destination. + * destMax The size of the buffer. + * c Character to set. + * count Number of characters. + * + * + * dest buffer is updated. + * + * + * EOK Success + * EINVAL dest == NULL and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN + * ERANGE destMax > SECUREC_MEM_MAX_LEN or (destMax is 0 and count > destMax) + * ERANGE_AND_RESET count > destMax and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN and dest != NULL + * + * if return ERANGE_AND_RESET then fill dest to c ,fill length is destMax + */ +errno_t memset_s(void *dest, size_t destMax, int c, size_t count) +{ + if (SECUREC_MEMSET_PARAM_OK(dest, destMax, count)) { + SECUREC_MEMSET_PREVENT_DSE(dest, c, count); + return EOK; + } + /* Meet some runtime violation, return error code */ + return SecMemsetError(dest, destMax, c); +} + +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(memset_s); +#endif + +#if SECUREC_WITH_PERFORMANCE_ADDONS +/* + * Performance optimization + */ +errno_t memset_sOptAsm(void *dest, size_t destMax, int c, size_t count) +{ + if (SECUREC_MEMSET_PARAM_OK(dest, destMax, count)) { + SECUREC_MEMSET_OPT(dest, c, count); + return EOK; + } + /* Meet some runtime violation, return error code */ + return SecMemsetError(dest, destMax, c); +} + +/* + * Performance optimization, trim judgement on "destMax <= SECUREC_MEM_MAX_LEN" + */ +errno_t memset_sOptTc(void *dest, size_t destMax, int c, size_t count) +{ + if (SECUREC_LIKELY(count <= destMax && dest != NULL)) { + SECUREC_MEMSET_OPT(dest, c, count); + return EOK; + } + /* Meet some runtime violation, return error code */ + return SecMemsetError(dest, destMax, c); +} +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/output.inl b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/output.inl new file mode 100644 index 0000000000000000000000000000000000000000..9392efaaff1f4a2ccb18152d3b049cc0eb5b87a2 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/output.inl @@ -0,0 +1,1720 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: Used by secureprintoutput_a.c and secureprintoutput_w.c to include. + * This file provides a template function for ANSI and UNICODE compiling + * by different type definition. The functions of SecOutputS or + * SecOutputSW provides internal implementation for printf family API, such as sprintf, swprintf_s. + * Create: 2014-02-25 + * Notes: see www.cplusplus.com/reference/cstdio/printf/ + */ +/* + * [Standardize-exceptions] Use unsafe function: Portability + * [reason] Use unsafe function to implement security function to maintain platform compatibility. + * And sufficient input validation is performed before calling + */ +#ifndef OUTPUT_INL_2B263E9C_43D8_44BB_B17A_6D2033DECEE5 +#define OUTPUT_INL_2B263E9C_43D8_44BB_B17A_6D2033DECEE5 + +#ifndef SECUREC_ENABLE_SPRINTF_LONG_DOUBLE +/* Some compilers do not support long double */ +#define SECUREC_ENABLE_SPRINTF_LONG_DOUBLE 1 +#endif + +#define SECUREC_NULL_STRING_SIZE 8 +#define SECUREC_STATE_TABLE_SIZE 337 + +#if defined(SECUREC_VXWORKS_VERSION_5_4) && !defined(SECUREC_ON_64BITS) +#define SECUREC_DIV_QUOTIENT_OCTAL(val64) ((val64) >> 3ULL) +#define SECUREC_DIV_RESIDUE_OCTAL(val64) ((val64) & 7ULL) + +#define SECUREC_DIV_QUOTIENT_HEX(val64) ((val64) >> 4ULL) +#define SECUREC_DIV_RESIDUE_HEX(val64) ((val64) & 0xfULL) +#endif + +#define SECUREC_RADIX_OCTAL 8U +#define SECUREC_RADIX_DECIMAL 10U +#define SECUREC_RADIX_HEX 16U +#define SECUREC_PREFIX_LEN 2 +/* Size include '+' and '\0' */ +#define SECUREC_FLOAT_BUF_EXT 2 + +/* Sign extend or Zero-extend */ +#define SECUREC_GET_LONG_FROM_ARG(attr) ((((attr).flags & SECUREC_FLAG_SIGNED) != 0) ? \ + (SecInt64)(long)va_arg(argList, long) : \ + (SecInt64)(unsigned long)va_arg(argList, long)) + +/* Sign extend or Zero-extend */ +#define SECUREC_GET_CHAR_FROM_ARG(attr) ((((attr).flags & SECUREC_FLAG_SIGNED) != 0) ? \ + SecUpdateNegativeChar(&(attr), ((char)va_arg(argList, int))) : \ + (SecInt64)(unsigned char)va_arg(argList, int)) + +/* Sign extend or Zero-extend */ +#define SECUREC_GET_SHORT_FROM_ARG(attr) ((((attr).flags & SECUREC_FLAG_SIGNED) != 0) ? \ + (SecInt64)(short)va_arg(argList, int) : \ + (SecInt64)(unsigned short)va_arg(argList, int)) + +/* Sign extend or Zero-extend */ +#define SECUREC_GET_INT_FROM_ARG(attr) ((((attr).flags & SECUREC_FLAG_SIGNED) != 0) ? \ + (SecInt64)(int)va_arg(argList, int) : \ + (SecInt64)(unsigned int)va_arg(argList, int)) + +#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT +/* Sign extend or Zero-extend. No suitable macros were found to handle the branch */ +#define SECUREC_GET_SIZE_FROM_ARG(attr) ((((attr).flags & SECUREC_FLAG_SIGNED) != 0) ? \ + ((SecIsSameSize(sizeof(size_t), sizeof(long)) != 0) ? (SecInt64)(long)va_arg(argList, long) : \ + ((SecIsSameSize(sizeof(size_t), sizeof(long long)) != 0) ? (SecInt64)(long long)va_arg(argList, long long) : \ + (SecInt64)(int)va_arg(argList, int))) : \ + (SecInt64)(size_t)va_arg(argList, size_t)) +#endif + +/* Format output buffer pointer and available size */ +typedef struct { + int count; + SecChar *cur; +} SecPrintfStream; + +typedef union { + /* Integer formatting refers to the end of the buffer, plus 1 to prevent tool alarms */ + char str[SECUREC_BUFFER_SIZE + 1]; +#if SECUREC_HAVE_WCHART + wchar_t wStr[SECUREC_WCHAR_BUFFER_SIZE]; /* Just for %lc */ +#endif +} SecBuffer; + +typedef union { + char *str; /* Not a null terminated string */ +#if SECUREC_HAVE_WCHART + wchar_t *wStr; +#endif +} SecFormatBuf; + +typedef struct { + const char *digits; /* Point to the hexadecimal subset */ + SecFormatBuf text; /* Point to formatted string */ + int textLen; /* Length of the text */ + int textIsWide; /* Flag for text is wide chars ; 0 is not wide char */ + unsigned int radix; /* Use for output number , default set to 10 */ + unsigned int flags; + int fldWidth; + int precision; + int dynWidth; /* %* 1 width from variable parameter ;0 not */ + int dynPrecision; /* %.* 1 precision from variable parameter ;0 not */ + int padding; /* Padding len */ + int prefixLen; /* Length of prefix, 0 or 1 or 2 */ + SecChar prefix[SECUREC_PREFIX_LEN]; /* Prefix is 0 or 0x */ + SecBuffer buffer; +} SecFormatAttr; + +#if SECUREC_ENABLE_SPRINTF_FLOAT +#ifdef SECUREC_STACK_SIZE_LESS_THAN_1K +#define SECUREC_FMT_STR_LEN 8 +#else +#define SECUREC_FMT_STR_LEN 16 +#endif +typedef struct { + char buffer[SECUREC_FMT_STR_LEN]; + char *fmtStr; /* Initialization must point to buffer */ + char *allocatedFmtStr; /* Initialization must be NULL to store allocated point */ + char *floatBuffer; /* Use heap memory if the SecFormatAttr.buffer is not enough */ + int bufferSize; /* The size of floatBuffer */ +} SecFloatAdapt; +#endif + +/* Use 20 to Align the data */ +#define SECUREC_DIGITS_BUF_SIZE 20 +/* The serial number of 'x' or 'X' is 16 */ +#define SECUREC_NUMBER_OF_X 16 +/* Some systems can not use pointers to point to string literals, but can use string arrays. */ +/* For example, when handling code under uboot, there is a problem with the pointer */ +static const char g_itoaUpperDigits[SECUREC_DIGITS_BUF_SIZE] = "0123456789ABCDEFX"; +static const char g_itoaLowerDigits[SECUREC_DIGITS_BUF_SIZE] = "0123456789abcdefx"; + +#if SECUREC_ENABLE_SPRINTF_FLOAT +/* Call system sprintf to format float value */ +SECUREC_INLINE int SecFormatFloat(char *strDest, const char *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + SECUREC_MASK_VSPRINTF_WARNING + ret = vsprintf(strDest, format, argList); + SECUREC_END_MASK_VSPRINTF_WARNING + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} + +#if defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && SECUREC_ENABLE_SPRINTF_LONG_DOUBLE +/* Out put long double value to dest */ +SECUREC_INLINE void SecFormatLongDouble(SecFormatAttr *attr, const SecFloatAdapt *floatAdapt, long double ldValue) +{ + int fldWidth = (((attr->flags & SECUREC_FLAG_LEFT) != 0) ? (-attr->fldWidth) : attr->fldWidth); + if (attr->dynWidth != 0 && attr->dynPrecision != 0) { + attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, fldWidth, attr->precision, ldValue); + } else if (attr->dynWidth != 0) { + attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, fldWidth, ldValue); + } else if (attr->dynPrecision != 0) { + attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, attr->precision, ldValue); + } else { + attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, ldValue); + } + if (attr->textLen < 0 || attr->textLen >= floatAdapt->bufferSize) { + attr->textLen = 0; + } +} +#endif + +/* Out put double value to dest */ +SECUREC_INLINE void SecFormatDouble(SecFormatAttr *attr, const SecFloatAdapt *floatAdapt, double dValue) +{ + int fldWidth = (((attr->flags & SECUREC_FLAG_LEFT) != 0) ? (-attr->fldWidth) : attr->fldWidth); + if (attr->dynWidth != 0 && attr->dynPrecision != 0) { + attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, fldWidth, attr->precision, dValue); + } else if (attr->dynWidth != 0) { + attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, fldWidth, dValue); + } else if (attr->dynPrecision != 0) { + attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, attr->precision, dValue); + } else { + attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, dValue); + } + if (attr->textLen < 0 || attr->textLen >= floatAdapt->bufferSize) { + attr->textLen = 0; + } +} +#endif + +#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT +/* To clear e506 warning */ +SECUREC_INLINE int SecIsSameSize(size_t sizeA, size_t sizeB) +{ + return (int)(sizeA == sizeB); +} +#endif + +#ifndef SECUREC_ON_64BITS +/* + * Compiler Optimized Division 8. + * The text.str point to buffer end, must be Large enough + */ +SECUREC_INLINE void SecNumber32ToOctalString(SecUnsignedInt32 number, SecFormatAttr *attr) +{ + SecUnsignedInt32 val32 = number; + do { + --attr->text.str; + /* Just use lowerDigits for 0 - 9 */ + *(attr->text.str) = g_itoaLowerDigits[val32 % SECUREC_RADIX_OCTAL]; + val32 /= SECUREC_RADIX_OCTAL; + } while (val32 != 0); +} + +#ifdef _AIX +/* + * Compiler Optimized Division 10. + * The text.str point to buffer end, must be Large enough + */ +SECUREC_INLINE void SecNumber32ToDecString(SecUnsignedInt32 number, SecFormatAttr *attr) +{ + SecUnsignedInt32 val32 = number; + do { + --attr->text.str; + /* Just use lowerDigits for 0 - 9 */ + *(attr->text.str) = g_itoaLowerDigits[val32 % SECUREC_RADIX_DECIMAL]; + val32 /= SECUREC_RADIX_DECIMAL; + } while (val32 != 0); +} +#endif +/* + * Compiler Optimized Division 16. + * The text.str point to buffer end, must be Large enough + */ +SECUREC_INLINE void SecNumber32ToHexString(SecUnsignedInt32 number, SecFormatAttr *attr) +{ + SecUnsignedInt32 val32 = number; + do { + --attr->text.str; + *(attr->text.str) = attr->digits[val32 % SECUREC_RADIX_HEX]; + val32 /= SECUREC_RADIX_HEX; + } while (val32 != 0); +} + +#ifndef _AIX +/* Use fast div 10 */ +SECUREC_INLINE void SecNumber32ToDecStringFast(SecUnsignedInt32 number, SecFormatAttr *attr) +{ + SecUnsignedInt32 val32 = number; + do { + SecUnsignedInt32 quotient; + SecUnsignedInt32 remain; + --attr->text.str; + *(attr->text.str) = g_itoaLowerDigits[val32 % SECUREC_RADIX_DECIMAL]; + quotient = (val32 >> 1U) + (val32 >> 2U); /* Fast div magic 2 */ + quotient = quotient + (quotient >> 4U); /* Fast div magic 4 */ + quotient = quotient + (quotient >> 8U); /* Fast div magic 8 */ + quotient = quotient + (quotient >> 16U); /* Fast div magic 16 */ + quotient = quotient >> 3U; /* Fast div magic 3 */ + remain = val32 - SECUREC_MUL_TEN(quotient); + val32 = (remain > 9U) ? (quotient + 1U) : quotient; /* Fast div magic 9 */ + } while (val32 != 0); +} +#endif + +SECUREC_INLINE void SecNumber32ToString(SecUnsignedInt32 number, SecFormatAttr *attr) +{ + switch (attr->radix) { + case SECUREC_RADIX_HEX: + SecNumber32ToHexString(number, attr); + break; + case SECUREC_RADIX_OCTAL: + SecNumber32ToOctalString(number, attr); + break; + case SECUREC_RADIX_DECIMAL: +#ifdef _AIX + /* The compiler will optimize div 10 */ + SecNumber32ToDecString(number, attr); +#else + SecNumber32ToDecStringFast(number, attr); +#endif + break; + default: + /* Do nothing */ + break; + } +} +#endif + +#if defined(SECUREC_USE_SPECIAL_DIV64) || (defined(SECUREC_VXWORKS_VERSION_5_4) && !defined(SECUREC_ON_64BITS)) +/* + * This function just to clear warning, on sume vxworks compiler shift 32 bit make warnings + */ +SECUREC_INLINE SecUnsignedInt64 SecU64Shr32(SecUnsignedInt64 number) +{ + return (((number) >> 16U) >> 16U); /* Two shifts of 16 bits to realize shifts of 32 bits */ +} +/* + * Fast divide by 10 algorithm. + * Calculation divisor multiply 0xcccccccccccccccdULL, resultHi64 >> 3 as quotient + */ +SECUREC_INLINE void SecU64Div10(SecUnsignedInt64 divisor, SecUnsignedInt64 *quotient, SecUnsignedInt32 *residue) +{ + SecUnsignedInt64 mask = 0xffffffffULL; /* Use 0xffffffffULL as 32 bit mask */ + SecUnsignedInt64 magicHi = 0xccccccccULL; /* Fast divide 10 magic numbers high 32bit 0xccccccccULL */ + SecUnsignedInt64 magicLow = 0xcccccccdULL; /* Fast divide 10 magic numbers low 32bit 0xcccccccdULL */ + SecUnsignedInt64 divisorHi = (SecUnsignedInt64)(SecU64Shr32(divisor)); /* High 32 bit use */ + SecUnsignedInt64 divisorLow = (SecUnsignedInt64)(divisor & mask); /* Low 32 bit mask */ + SecUnsignedInt64 factorHi = divisorHi * magicHi; + SecUnsignedInt64 factorLow1 = divisorHi * magicLow; + SecUnsignedInt64 factorLow2 = divisorLow * magicHi; + SecUnsignedInt64 factorLow3 = divisorLow * magicLow; + SecUnsignedInt64 carry = (factorLow1 & mask) + (factorLow2 & mask) + SecU64Shr32(factorLow3); + SecUnsignedInt64 resultHi64 = factorHi + SecU64Shr32(factorLow1) + SecU64Shr32(factorLow2) + SecU64Shr32(carry); + + *quotient = resultHi64 >> 3U; /* Fast divide 10 magic numbers 3 */ + *residue = (SecUnsignedInt32)(divisor - ((*quotient) * 10)); /* Quotient mul 10 */ + return; +} +#if defined(SECUREC_VXWORKS_VERSION_5_4) && !defined(SECUREC_ON_64BITS) +/* + * Divide function for VXWORKS + */ +SECUREC_INLINE int SecU64Div32(SecUnsignedInt64 divisor, SecUnsignedInt32 radix, + SecUnsignedInt64 *quotient, SecUnsignedInt32 *residue) +{ + switch (radix) { + case SECUREC_RADIX_DECIMAL: + SecU64Div10(divisor, quotient, residue); + break; + case SECUREC_RADIX_HEX: + *quotient = SECUREC_DIV_QUOTIENT_HEX(divisor); + *residue = (SecUnsignedInt32)SECUREC_DIV_RESIDUE_HEX(divisor); + break; + case SECUREC_RADIX_OCTAL: + *quotient = SECUREC_DIV_QUOTIENT_OCTAL(divisor); + *residue = (SecUnsignedInt32)SECUREC_DIV_RESIDUE_OCTAL(divisor); + break; + default: + return -1; /* This does not happen in the current file */ + } + return 0; +} +SECUREC_INLINE void SecNumber64ToStringSpecial(SecUnsignedInt64 number, SecFormatAttr *attr) +{ + SecUnsignedInt64 val64 = number; + do { + SecUnsignedInt32 digit = 0; /* Ascii value of digit */ + SecUnsignedInt64 quotient = 0; + if (SecU64Div32(val64, (SecUnsignedInt32)attr->radix, "ient, &digit) != 0) { + /* Just break, when enter this function, no error is returned */ + break; + } + --attr->text.str; + *(attr->text.str) = attr->digits[digit]; + val64 = quotient; + } while (val64 != 0); +} +#endif +#endif + +#if defined(SECUREC_ON_64BITS) || !defined(SECUREC_VXWORKS_VERSION_5_4) +#if defined(SECUREC_USE_SPECIAL_DIV64) +/* The compiler does not provide 64 bit division problems */ +SECUREC_INLINE void SecNumber64ToDecString(SecUnsignedInt64 number, SecFormatAttr *attr) +{ + SecUnsignedInt64 val64 = number; + do { + SecUnsignedInt64 quotient = 0; + SecUnsignedInt32 digit = 0; + SecU64Div10(val64, "ient, &digit); + --attr->text.str; + /* Just use lowerDigits for 0 - 9 */ + *(attr->text.str) = g_itoaLowerDigits[digit]; + val64 = quotient; + } while (val64 != 0); +} +#else +/* + * Compiler Optimized Division 10. + * The text.str point to buffer end, must be Large enough + */ +SECUREC_INLINE void SecNumber64ToDecString(SecUnsignedInt64 number, SecFormatAttr *attr) +{ + SecUnsignedInt64 val64 = number; + do { + --attr->text.str; + /* Just use lowerDigits for 0 - 9 */ + *(attr->text.str) = g_itoaLowerDigits[val64 % SECUREC_RADIX_DECIMAL]; + val64 /= SECUREC_RADIX_DECIMAL; + } while (val64 != 0); +} +#endif + +/* + * Compiler Optimized Division 8. + * The text.str point to buffer end, must be Large enough + */ +SECUREC_INLINE void SecNumber64ToOctalString(SecUnsignedInt64 number, SecFormatAttr *attr) +{ + SecUnsignedInt64 val64 = number; + do { + --attr->text.str; + /* Just use lowerDigits for 0 - 9 */ + *(attr->text.str) = g_itoaLowerDigits[val64 % SECUREC_RADIX_OCTAL]; + val64 /= SECUREC_RADIX_OCTAL; + } while (val64 != 0); +} +/* + * Compiler Optimized Division 16. + * The text.str point to buffer end, must be Large enough + */ +SECUREC_INLINE void SecNumber64ToHexString(SecUnsignedInt64 number, SecFormatAttr *attr) +{ + SecUnsignedInt64 val64 = number; + do { + --attr->text.str; + *(attr->text.str) = attr->digits[val64 % SECUREC_RADIX_HEX]; + val64 /= SECUREC_RADIX_HEX; + } while (val64 != 0); +} + +SECUREC_INLINE void SecNumber64ToString(SecUnsignedInt64 number, SecFormatAttr *attr) +{ + switch (attr->radix) { + /* The compiler will optimize div 10 */ + case SECUREC_RADIX_DECIMAL: + SecNumber64ToDecString(number, attr); + break; + case SECUREC_RADIX_OCTAL: + SecNumber64ToOctalString(number, attr); + break; + case SECUREC_RADIX_HEX: + SecNumber64ToHexString(number, attr); + break; + default: + /* Do nothing */ + break; + } +} +#endif + +/* + * Converting integers to string + */ +SECUREC_INLINE void SecNumberToString(SecUnsignedInt64 number, SecFormatAttr *attr) +{ +#ifdef SECUREC_ON_64BITS + SecNumber64ToString(number, attr); +#else /* For 32 bits system */ + if (number <= 0xffffffffUL) { /* Use 0xffffffffUL to check if the value is in the 32-bit range */ + /* In most case, the value to be converted is small value */ + SecUnsignedInt32 n32Tmp = (SecUnsignedInt32)number; + SecNumber32ToString(n32Tmp, attr); + } else { + /* The value to be converted is greater than 4G */ +#if defined(SECUREC_VXWORKS_VERSION_5_4) + SecNumber64ToStringSpecial(number, attr); +#else + SecNumber64ToString(number, attr); +#endif + } +#endif +} + +SECUREC_INLINE int SecIsNumberNeedTo32Bit(const SecFormatAttr *attr) +{ + return (int)(((attr->flags & SECUREC_FLAG_I64) == 0) && +#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT + ((attr->flags & SECUREC_FLAG_INTMAX) == 0) && +#endif +#ifdef SECUREC_ON_64BITS + ((attr->flags & SECUREC_FLAG_PTRDIFF) == 0) && + ((attr->flags & SECUREC_FLAG_SIZE) == 0) && +#if !defined(SECUREC_COMPATIBLE_WIN_FORMAT) /* on window 64 system sizeof long is 32bit */ + ((attr->flags & SECUREC_FLAG_LONG) == 0) && +#endif +#endif + ((attr->flags & SECUREC_FLAG_LONGLONG) == 0)); +} + +SECUREC_INLINE void SecNumberToBuffer(SecFormatAttr *attr, SecInt64 num64) +{ + SecUnsignedInt64 number; + /* Check for negative; copy into number */ + if ((attr->flags & SECUREC_FLAG_SIGNED) != 0 && num64 < 0) { + number = (SecUnsignedInt64)(0 - (SecUnsignedInt64)num64); /* Wrap with unsigned int64 numbers */ + attr->flags |= SECUREC_FLAG_NEGATIVE; + } else { + number = (SecUnsignedInt64)num64; + } + if (SecIsNumberNeedTo32Bit(attr) != 0) { + number = (number & (SecUnsignedInt64)0xffffffffUL); /* Use 0xffffffff as 32 bit mask */ + } + + /* The text.str must be point to buffer.str, this pointer is used outside the function */ + attr->text.str = &attr->buffer.str[SECUREC_BUFFER_SIZE]; + + if (number == 0) { + /* Turn off hex prefix default, and textLen is zero */ + attr->prefixLen = 0; + attr->textLen = 0; + return; + } + + /* Convert integer to string. It must be invoked when number > 0, otherwise the following logic is incorrect */ + SecNumberToString(number, attr); + /* Compute length of number, text.str must be in buffer.str */ + attr->textLen = (int)(size_t)((char *)&attr->buffer.str[SECUREC_BUFFER_SIZE] - attr->text.str); +} + +/* + * Write one character to dest buffer + */ +SECUREC_INLINE void SecWriteChar(SecPrintfStream *stream, SecChar ch, int *charsOut) +{ + /* Count must be reduced first, In order to identify insufficient length */ + --stream->count; + if (stream->count >= 0) { + *(stream->cur) = ch; + ++stream->cur; + *charsOut = *charsOut + 1; + return; + } + /* No enough length */ + *charsOut = -1; +} + +/* +* Write multiple identical characters. +*/ +SECUREC_INLINE void SecWriteMultiChar(SecPrintfStream *stream, SecChar ch, int num, int *charsOut) +{ + int count; + for (count = num; count > 0; --count) { + --stream->count; /* count may be negative,indicating insufficient space */ + if (stream->count < 0) { + *charsOut = -1; + return; + } + *(stream->cur) = ch; + ++stream->cur; + } + *charsOut = *charsOut + num; +} + +/* +* Write string function, where this function is called, make sure that len is greater than 0 +*/ +SECUREC_INLINE void SecWriteString(SecPrintfStream *stream, const SecChar *str, int len, int *charsOut) +{ + const SecChar *tmp = str; + int count; + for (count = len; count > 0; --count) { + --stream->count; /* count may be negative,indicating insufficient space */ + if (stream->count < 0) { + *charsOut = -1; + return; + } + *(stream->cur) = *tmp; + ++stream->cur; + ++tmp; + } + *charsOut = *charsOut + len; +} + +/* Use loop copy char or wchar_t string */ +SECUREC_INLINE void SecWriteStringByLoop(SecPrintfStream *stream, const SecChar *str, int len) +{ + int i; + const SecChar *tmp = str; + for (i = 0; i < len; ++i) { + *stream->cur = *tmp; + ++stream->cur; + ++tmp; + } + stream->count -= len; +} + +SECUREC_INLINE void SecWriteStringOpt(SecPrintfStream *stream, const SecChar *str, int len) +{ + if (len < 12) { /* Performance optimization for mobile number length 12 */ + SecWriteStringByLoop(stream, str, len); + } else { + size_t count = (size_t)(unsigned int)len * sizeof(SecChar); + SECUREC_MEMCPY_WARP_OPT(stream->cur, str, count); + stream->cur += len; + stream->count -= len; + } +} + +/* + * Return if buffer length is enough + * The count variable can be reduced to 0, and the external function complements the \0 terminator. + */ +SECUREC_INLINE int SecIsStreamBufEnough(const SecPrintfStream *stream, int needLen) +{ + return (int)(stream->count >= needLen); +} + +/* Write text string */ +SECUREC_INLINE void SecWriteTextOpt(SecPrintfStream *stream, const SecChar *str, int len, int *charsOut) +{ + if (SecIsStreamBufEnough(stream, len) != 0) { + SecWriteStringOpt(stream, str, len); + *charsOut += len; + } else { + SecWriteString(stream, str, len, charsOut); + } +} + +/* Write left padding */ +SECUREC_INLINE void SecWriteLeftPadding(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) +{ + if ((attr->flags & (SECUREC_FLAG_LEFT | SECUREC_FLAG_LEADZERO)) == 0 && attr->padding > 0) { + /* Pad on left with blanks */ + SecWriteMultiChar(stream, SECUREC_CHAR(' '), attr->padding, charsOut); + } +} + +/* Write prefix */ +SECUREC_INLINE void SecWritePrefix(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) +{ + if (attr->prefixLen > 0) { + SecWriteString(stream, attr->prefix, attr->prefixLen, charsOut); + } +} + +/* Write leading zeros */ +SECUREC_INLINE void SecWriteLeadingZero(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) +{ + if ((attr->flags & SECUREC_FLAG_LEADZERO) != 0 && (attr->flags & SECUREC_FLAG_LEFT) == 0 && + attr->padding > 0) { + SecWriteMultiChar(stream, SECUREC_CHAR('0'), attr->padding, charsOut); + } +} + +/* Write right padding */ +SECUREC_INLINE void SecWriteRightPadding(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) +{ + if (*charsOut >= 0 && (attr->flags & SECUREC_FLAG_LEFT) != 0 && attr->padding > 0) { + /* Pad on right with blanks */ + SecWriteMultiChar(stream, SECUREC_CHAR(' '), attr->padding, charsOut); + } +} + +#ifdef SECUREC_FOR_WCHAR +#define SECUREC_TEXT_CHAR_PTR(text) ((text).wStr) +#define SECUREC_NEED_CONVERT_TEXT(attr) ((attr)->textIsWide == 0) +#if SECUREC_HAVE_MBTOWC +#define SECUREC_WRITE_TEXT_AFTER_CONVERT(stream, attr, charsOut) SecWriteTextAfterMbtowc((stream), (attr), (charsOut)) +#else +#define SECUREC_WRITE_TEXT_AFTER_CONVERT(stream, attr, charsOut) (*(charsOut) = -1) +#endif +#else +#define SECUREC_TEXT_CHAR_PTR(text) ((text).str) +#define SECUREC_NEED_CONVERT_TEXT(attr) ((attr)->textIsWide != 0) +#if SECUREC_HAVE_WCTOMB +#define SECUREC_WRITE_TEXT_AFTER_CONVERT(stream, attr, charsOut) SecWriteTextAfterWctomb((stream), (attr), (charsOut)) +#else +#define SECUREC_WRITE_TEXT_AFTER_CONVERT(stream, attr, charsOut) (*(charsOut) = -1) +#endif +#endif + +#ifdef SECUREC_FOR_WCHAR +#if SECUREC_HAVE_MBTOWC +SECUREC_INLINE void SecWriteTextAfterMbtowc(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) +{ + const char *p = attr->text.str; + int count = attr->textLen; + while (count > 0) { + wchar_t wChar = L'\0'; + int retVal = mbtowc(&wChar, p, (size_t)MB_CUR_MAX); + if (retVal <= 0) { + *charsOut = -1; + break; + } + SecWriteChar(stream, wChar, charsOut); + if (*charsOut == -1) { + break; + } + p += retVal; + count -= retVal; + } +} +#endif +#else /* Not SECUREC_FOR_WCHAR */ +#if SECUREC_HAVE_WCTOMB +SECUREC_INLINE void SecWriteTextAfterWctomb(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) +{ + const wchar_t *p = attr->text.wStr; + int count = attr->textLen; + while (count > 0) { + char tmpBuf[SECUREC_MB_LEN + 1]; + SECUREC_MASK_MSVC_CRT_WARNING + int retVal = wctomb(tmpBuf, *p); + SECUREC_END_MASK_MSVC_CRT_WARNING + if (retVal <= 0) { + *charsOut = -1; + break; + } + SecWriteString(stream, tmpBuf, retVal, charsOut); + if (*charsOut == -1) { + break; + } + --count; + ++p; + } +} +#endif +#endif + +#if SECUREC_ENABLE_SPRINTF_FLOAT +/* + * Write text of float + * Using independent functions to optimize the expansion of inline functions by the compiler + */ +SECUREC_INLINE void SecWriteFloatText(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) +{ +#ifdef SECUREC_FOR_WCHAR +#if SECUREC_HAVE_MBTOWC + SecWriteTextAfterMbtowc(stream, attr, charsOut); +#else + *charsOut = -1; + (void)stream; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + (void)attr; /* To clear e438 last value assigned not used , the compiler will optimize this code */ +#endif +#else /* Not SECUREC_FOR_WCHAR */ + SecWriteString(stream, attr->text.str, attr->textLen, charsOut); +#endif +} +#endif + +/* Write text of integer or string ... */ +SECUREC_INLINE void SecWriteText(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) +{ + if (SECUREC_NEED_CONVERT_TEXT(attr)) { + SECUREC_WRITE_TEXT_AFTER_CONVERT(stream, attr, charsOut); + } else { + SecWriteTextOpt(stream, SECUREC_TEXT_CHAR_PTR(attr->text), attr->textLen, charsOut); + } +} + +#define SECUREC_FMT_STATE_OFFSET 256 + +SECUREC_INLINE SecFmtState SecDecodeState(SecChar ch, SecFmtState lastState) +{ + static const unsigned char stateTable[SECUREC_STATE_TABLE_SIZE] = { + /* + * Type + * 0: nospecial meaning; + * 1: '%' + * 2: '.' + * 3: '*' + * 4: '0' + * 5: '1' ... '9' + * 6: ' ', '+', '-', '#' + * 7: 'h', 'l', 'L', 'w' , 'N', 'z', 'q', 't', 'j' + * 8: 'd', 'o', 'u', 'i', 'x', 'X', 'e', 'f', 'g', 'E', 'F', 'G', 's', 'c', '[', 'p' + */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x06, 0x00, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x03, 0x06, 0x00, 0x06, 0x02, 0x00, + 0x04, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x08, 0x08, 0x00, 0x07, 0x00, 0x00, 0x07, 0x00, 0x07, 0x00, + 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x07, 0x08, 0x07, 0x00, 0x07, 0x00, 0x00, 0x08, + 0x08, 0x07, 0x00, 0x08, 0x07, 0x08, 0x00, 0x07, 0x08, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, + /* Fill zero for normal char 128 byte for 0x80 - 0xff */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* + * State + * 0: normal + * 1: percent + * 2: flag + * 3: width + * 4: dot + * 5: precis + * 6: size + * 7: type + * 8: invalid + */ + 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x01, 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, + 0x01, 0x00, 0x00, 0x04, 0x04, 0x04, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x03, 0x03, 0x08, 0x05, + 0x08, 0x08, 0x00, 0x00, 0x00, 0x02, 0x02, 0x03, 0x05, 0x05, 0x08, 0x00, 0x00, 0x00, 0x03, 0x03, + 0x03, 0x05, 0x05, 0x08, 0x00, 0x00, 0x00, 0x02, 0x02, 0x02, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, + 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x00, + 0x00 + }; + +#ifdef SECUREC_FOR_WCHAR + /* Convert to unsigned char to clear gcc 4.3.4 warning */ + unsigned char fmtType = (unsigned char)((((unsigned int)(int)(ch)) <= (unsigned int)(int)(L'~')) ? \ + (stateTable[(unsigned char)(ch)]) : 0); + return (SecFmtState)(stateTable[fmtType * ((unsigned char)STAT_INVALID + 1) + + (unsigned char)(lastState) + SECUREC_FMT_STATE_OFFSET]); +#else + unsigned char fmtType = stateTable[(unsigned char)(ch)]; + return (SecFmtState)(stateTable[fmtType * ((unsigned char)STAT_INVALID + 1) + + (unsigned char)(lastState) + SECUREC_FMT_STATE_OFFSET]); +#endif +} + +SECUREC_INLINE void SecDecodeFlags(SecChar ch, SecFormatAttr *attr) +{ + switch (ch) { + case SECUREC_CHAR(' '): + attr->flags |= SECUREC_FLAG_SIGN_SPACE; + break; + case SECUREC_CHAR('+'): + attr->flags |= SECUREC_FLAG_SIGN; + break; + case SECUREC_CHAR('-'): + attr->flags |= SECUREC_FLAG_LEFT; + break; + case SECUREC_CHAR('0'): + attr->flags |= SECUREC_FLAG_LEADZERO; /* Add zero th the front */ + break; + case SECUREC_CHAR('#'): + attr->flags |= SECUREC_FLAG_ALTERNATE; /* Output %x with 0x */ + break; + default: + /* Do nothing */ + break; + } + return; +} + +/* + * Decoded size identifier in format string to Reduce the number of lines of function code + */ +SECUREC_INLINE int SecDecodeSizeI(SecFormatAttr *attr, const SecChar **format) +{ +#ifdef SECUREC_ON_64BITS + attr->flags |= SECUREC_FLAG_I64; /* %I to INT64 */ +#endif + if ((**format == SECUREC_CHAR('6')) && (*((*format) + 1) == SECUREC_CHAR('4'))) { + (*format) += 2; /* Add 2 to skip I64 */ + attr->flags |= SECUREC_FLAG_I64; /* %I64 to INT64 */ + } else if ((**format == SECUREC_CHAR('3')) && (*((*format) + 1) == SECUREC_CHAR('2'))) { + (*format) += 2; /* Add 2 to skip I32 */ + attr->flags &= ~SECUREC_FLAG_I64; /* %I64 to INT32 */ + } else if ((**format == SECUREC_CHAR('d')) || (**format == SECUREC_CHAR('i')) || + (**format == SECUREC_CHAR('o')) || (**format == SECUREC_CHAR('u')) || + (**format == SECUREC_CHAR('x')) || (**format == SECUREC_CHAR('X'))) { + /* Do nothing */ + } else { + /* Compatibility code for "%I" just print I */ + return -1; + } + return 0; +} + +/* + * Decoded size identifier in format string, and skip format to next charater + */ +SECUREC_INLINE int SecDecodeSize(SecChar ch, SecFormatAttr *attr, const SecChar **format) +{ + switch (ch) { + case SECUREC_CHAR('l'): + if (**format == SECUREC_CHAR('l')) { + *format = *format + 1; + attr->flags |= SECUREC_FLAG_LONGLONG; /* For long long */ + } else { + attr->flags |= SECUREC_FLAG_LONG; /* For long int or wchar_t */ + } + break; +#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT + case SECUREC_CHAR('z'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('Z'): + attr->flags |= SECUREC_FLAG_SIZE; + break; + case SECUREC_CHAR('j'): + attr->flags |= SECUREC_FLAG_INTMAX; + break; +#endif + case SECUREC_CHAR('t'): + attr->flags |= SECUREC_FLAG_PTRDIFF; + break; + case SECUREC_CHAR('q'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('L'): + attr->flags |= (SECUREC_FLAG_LONGLONG | SECUREC_FLAG_LONG_DOUBLE); + break; + case SECUREC_CHAR('I'): + if (SecDecodeSizeI(attr, format) != 0) { + /* Compatibility code for "%I" just print I */ + return -1; + } + break; + case SECUREC_CHAR('h'): + if (**format == SECUREC_CHAR('h')) { + *format = *format + 1; + attr->flags |= SECUREC_FLAG_CHAR; /* For char */ + } else { + attr->flags |= SECUREC_FLAG_SHORT; /* For short int */ + } + break; + case SECUREC_CHAR('w'): + attr->flags |= SECUREC_FLAG_WIDECHAR; /* For wide char */ + break; + default: + /* Do nothing */ + break; + } + return 0; +} + +/* + * Decoded char type identifier + */ +SECUREC_INLINE void SecDecodeTypeC(SecFormatAttr *attr, unsigned int c) +{ + attr->textLen = 1; /* Only 1 wide character */ + +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT)) && !(defined(__hpux)) && !(defined(SECUREC_ON_SOLARIS)) + attr->flags &= ~SECUREC_FLAG_LEADZERO; +#endif + +#ifdef SECUREC_FOR_WCHAR + if ((attr->flags & SECUREC_FLAG_SHORT) != 0) { + /* Get multibyte character from argument */ + attr->buffer.str[0] = (char)c; + attr->text.str = attr->buffer.str; + attr->textIsWide = 0; + } else { + attr->buffer.wStr[0] = (wchar_t)c; + attr->text.wStr = attr->buffer.wStr; + attr->textIsWide = 1; + } +#else /* Not SECUREC_FOR_WCHAR */ + if ((attr->flags & (SECUREC_FLAG_LONG | SECUREC_FLAG_WIDECHAR)) != 0) { +#if SECUREC_HAVE_WCHART + attr->buffer.wStr[0] = (wchar_t)c; + attr->text.wStr = attr->buffer.wStr; + attr->textIsWide = 1; +#else + attr->textLen = 0; /* Ignore unsupported characters */ + attr->fldWidth = 0; /* No paddings */ +#endif + } else { + /* Get multibyte character from argument */ + attr->buffer.str[0] = (char)c; + attr->text.str = attr->buffer.str; + attr->textIsWide = 0; + } +#endif +} + +#ifdef SECUREC_FOR_WCHAR +#define SECUREC_IS_NARROW_STRING(attr) (((attr)->flags & SECUREC_FLAG_SHORT) != 0) +#else +#define SECUREC_IS_NARROW_STRING(attr) (((attr)->flags & (SECUREC_FLAG_LONG | SECUREC_FLAG_WIDECHAR)) == 0) +#endif + +SECUREC_INLINE void SecDecodeTypeSchar(SecFormatAttr *attr) +{ + size_t textLen; + if (attr->text.str == NULL) { + /* + * Literal string to print null ptr, define it as array rather than const text area + * To avoid gcc warning with pointing const text with variable + */ + static char strNullString[SECUREC_NULL_STRING_SIZE] = "(null)"; + attr->text.str = strNullString; + } + if (attr->precision == -1) { + /* Precision NOT assigned */ + /* The strlen performance is high when the string length is greater than 32 */ + textLen = strlen(attr->text.str); + if (textLen > SECUREC_STRING_MAX_LEN) { + textLen = 0; + } + } else { + /* Precision assigned */ + SECUREC_CALC_STR_LEN(attr->text.str, (size_t)(unsigned int)attr->precision, &textLen); + } + attr->textLen = (int)textLen; +} + +SECUREC_INLINE void SecDecodeTypeSwchar(SecFormatAttr *attr) +{ +#if SECUREC_HAVE_WCHART + size_t textLen; + attr->textIsWide = 1; + if (attr->text.wStr == NULL) { + /* + * Literal string to print null ptr, define it as array rather than const text area + * To avoid gcc warning with pointing const text with variable + */ + static wchar_t wStrNullString[SECUREC_NULL_STRING_SIZE] = { L'(', L'n', L'u', L'l', L'l', L')', L'\0', L'\0' }; + attr->text.wStr = wStrNullString; + } + /* The textLen in wchar_t,when precision is -1, it is unlimited */ + SECUREC_CALC_WSTR_LEN(attr->text.wStr, (size_t)(unsigned int)attr->precision, &textLen); + if (textLen > SECUREC_WCHAR_STRING_MAX_LEN) { + textLen = 0; + } + attr->textLen = (int)textLen; +#else + attr->textLen = 0; +#endif +} + +/* + * Decoded string identifier + */ +SECUREC_INLINE void SecDecodeTypeS(SecFormatAttr *attr, char *argPtr) +{ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT)) +#if (!defined(SECUREC_ON_UNIX)) + attr->flags &= ~SECUREC_FLAG_LEADZERO; +#endif +#if (defined(SECUREC_FOR_WCHAR)) + if ((attr->flags & SECUREC_FLAG_LONG) == 0) { + attr->flags |= SECUREC_FLAG_SHORT; + } +#endif +#endif + attr->text.str = argPtr; + if (SECUREC_IS_NARROW_STRING(attr)) { + /* The textLen now contains length in multibyte chars */ + SecDecodeTypeSchar(attr); + } else { + /* The textLen now contains length in wide chars */ + SecDecodeTypeSwchar(attr); + } +} + +/* + * Check precision in format + */ +SECUREC_INLINE int SecDecodePrecision(SecChar ch, SecFormatAttr *attr) +{ + if (attr->dynPrecision == 0) { + /* Add digit to current precision */ + if (SECUREC_MUL_TEN_ADD_BEYOND_MAX(attr->precision)) { + return -1; + } + attr->precision = (int)SECUREC_MUL_TEN((unsigned int)attr->precision) + + (unsigned char)(ch - SECUREC_CHAR('0')); + } else { + if (attr->precision < 0) { + attr->precision = -1; + } + if (attr->precision > SECUREC_MAX_WIDTH_LEN) { + return -1; + } + } + return 0; +} + +/* + * Check width in format + */ +SECUREC_INLINE int SecDecodeWidth(SecChar ch, SecFormatAttr *attr, SecFmtState lastState) +{ + if (attr->dynWidth == 0) { + if (lastState != STAT_WIDTH) { + attr->fldWidth = 0; + } + if (SECUREC_MUL_TEN_ADD_BEYOND_MAX(attr->fldWidth)) { + return -1; + } + attr->fldWidth = (int)SECUREC_MUL_TEN((unsigned int)attr->fldWidth) + + (unsigned char)(ch - SECUREC_CHAR('0')); + } else { + if (attr->fldWidth < 0) { + attr->flags |= SECUREC_FLAG_LEFT; + attr->fldWidth = (-attr->fldWidth); + } + if (attr->fldWidth > SECUREC_MAX_WIDTH_LEN) { + return -1; + } + } + return 0; +} + +/* + * The sprintf_s function processes the wide character as a parameter for %C + * The swprintf_s function processes the multiple character as a parameter for %C + */ +SECUREC_INLINE void SecUpdateWcharFlags(SecFormatAttr *attr) +{ + if ((attr->flags & (SECUREC_FLAG_SHORT | SECUREC_FLAG_LONG | SECUREC_FLAG_WIDECHAR)) == 0) { +#ifdef SECUREC_FOR_WCHAR + attr->flags |= SECUREC_FLAG_SHORT; +#else + attr->flags |= SECUREC_FLAG_WIDECHAR; +#endif + } +} +/* + * When encountering %S, current just same as %C + */ +SECUREC_INLINE void SecUpdateWstringFlags(SecFormatAttr *attr) +{ + SecUpdateWcharFlags(attr); +} + +#if SECUREC_IN_KERNEL +SECUREC_INLINE void SecUpdatePointFlagsForKernel(SecFormatAttr *attr) +{ + /* Width is not set */ + if (attr->fldWidth <= 0) { + attr->flags |= SECUREC_FLAG_LEADZERO; + attr->fldWidth = 2 * sizeof(void *); /* 2 x byte number is the length of hex */ + } + if ((attr->flags & SECUREC_FLAG_ALTERNATE) != 0) { + /* Alternate form means '0x' prefix */ + attr->prefix[0] = SECUREC_CHAR('0'); + attr->prefix[1] = SECUREC_CHAR('x'); + attr->prefixLen = SECUREC_PREFIX_LEN; + } + attr->flags |= SECUREC_FLAG_LONG; /* Converting a long */ +} +#endif + +SECUREC_INLINE void SecUpdatePointFlags(SecFormatAttr *attr) +{ + attr->flags |= SECUREC_FLAG_POINTER; +#if SECUREC_IN_KERNEL + SecUpdatePointFlagsForKernel(attr); +#else +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) || defined(SECUREC_VXWORKS_PLATFORM)) && (!defined(SECUREC_ON_UNIX)) +#if defined(SECUREC_VXWORKS_PLATFORM) + attr->precision = 1; +#else + attr->precision = 0; +#endif + attr->flags |= SECUREC_FLAG_ALTERNATE; /* "0x" is not default prefix in UNIX */ + attr->digits = g_itoaLowerDigits; +#else /* On unix or win */ +#if defined(_AIX) || defined(SECUREC_ON_SOLARIS) + attr->precision = 1; +#else + attr->precision = 2 * sizeof(void *); /* 2 x byte number is the length of hex */ +#endif +#if defined(SECUREC_ON_UNIX) + attr->digits = g_itoaLowerDigits; +#else + attr->digits = g_itoaUpperDigits; +#endif +#endif + +#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) + attr->flags &= ~SECUREC_FLAG_LEADZERO; +#endif + +#ifdef SECUREC_ON_64BITS + attr->flags |= SECUREC_FLAG_I64; /* Converting an int64 */ +#else + attr->flags |= SECUREC_FLAG_LONG; /* Converting a long */ +#endif + /* Set up for %#p on different system */ + if ((attr->flags & SECUREC_FLAG_ALTERNATE) != 0) { + /* Alternate form means '0x' prefix */ + attr->prefix[0] = SECUREC_CHAR('0'); +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) || defined(SECUREC_VXWORKS_PLATFORM)) + attr->prefix[1] = SECUREC_CHAR('x'); +#else + attr->prefix[1] = (SecChar)(attr->digits[SECUREC_NUMBER_OF_X]); +#endif +#if defined(_AIX) || defined(SECUREC_ON_SOLARIS) + attr->prefixLen = 0; +#else + attr->prefixLen = SECUREC_PREFIX_LEN; +#endif + } +#endif +} + +SECUREC_INLINE void SecUpdateXpxFlags(SecFormatAttr *attr, SecChar ch) +{ + /* Use unsigned lower hex output for 'x' */ + attr->digits = g_itoaLowerDigits; + attr->radix = SECUREC_RADIX_HEX; + switch (ch) { + case SECUREC_CHAR('p'): + /* Print a pointer */ + SecUpdatePointFlags(attr); + break; + case SECUREC_CHAR('X'): /* fall-through */ /* FALLTHRU */ + /* Unsigned upper hex output */ + attr->digits = g_itoaUpperDigits; + /* fall-through */ /* FALLTHRU */ + default: + /* For %#x or %#X */ + if ((attr->flags & SECUREC_FLAG_ALTERNATE) != 0) { + /* Alternate form means '0x' prefix */ + attr->prefix[0] = SECUREC_CHAR('0'); + attr->prefix[1] = (SecChar)(attr->digits[SECUREC_NUMBER_OF_X]); + attr->prefixLen = SECUREC_PREFIX_LEN; + } + break; + } +} + +SECUREC_INLINE void SecUpdateOudiFlags(SecFormatAttr *attr, SecChar ch) +{ + /* Do not set digits here */ + switch (ch) { + case SECUREC_CHAR('i'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('d'): /* fall-through */ /* FALLTHRU */ + /* For signed decimal output */ + attr->flags |= SECUREC_FLAG_SIGNED; + /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('u'): + attr->radix = SECUREC_RADIX_DECIMAL; + attr->digits = g_itoaLowerDigits; + break; + case SECUREC_CHAR('o'): + /* For unsigned octal output */ + attr->radix = SECUREC_RADIX_OCTAL; + attr->digits = g_itoaLowerDigits; + if ((attr->flags & SECUREC_FLAG_ALTERNATE) != 0) { + /* Alternate form means force a leading 0 */ + attr->flags |= SECUREC_FLAG_FORCE_OCTAL; + } + break; + default: + /* Do nothing */ + break; + } +} + +#if SECUREC_ENABLE_SPRINTF_FLOAT +SECUREC_INLINE void SecFreeFloatBuffer(SecFloatAdapt *floatAdapt) +{ + if (floatAdapt->floatBuffer != NULL) { + SECUREC_FREE(floatAdapt->floatBuffer); + } + if (floatAdapt->allocatedFmtStr != NULL) { + SECUREC_FREE(floatAdapt->allocatedFmtStr); + } + floatAdapt->floatBuffer = NULL; + floatAdapt->allocatedFmtStr = NULL; + floatAdapt->fmtStr = NULL; + floatAdapt->bufferSize = 0; +} + +SECUREC_INLINE void SecSeekToFrontPercent(const SecChar **format) +{ + const SecChar *fmt = *format; + while (*fmt != SECUREC_CHAR('%')) { /* Must meet '%' */ + --fmt; + } + *format = fmt; +} + +/* Init float format, return 0 is OK */ +SECUREC_INLINE int SecInitFloatFmt(SecFloatAdapt *floatFmt, const SecChar *format) +{ + const SecChar *fmt = format - 2; /* Sub 2 to the position before 'f' or 'g' */ + int fmtStrLen; + int i; + + SecSeekToFrontPercent(&fmt); + /* Now fmt point to '%' */ + fmtStrLen = (int)(size_t)(format - fmt) + 1; /* With ending terminator */ + if (fmtStrLen > (int)sizeof(floatFmt->buffer)) { + /* When buffer is NOT enough, alloc a new buffer */ + floatFmt->allocatedFmtStr = (char *)SECUREC_MALLOC((size_t)((unsigned int)fmtStrLen)); + if (floatFmt->allocatedFmtStr == NULL) { + return -1; + } + floatFmt->fmtStr = floatFmt->allocatedFmtStr; + } else { + floatFmt->fmtStr = floatFmt->buffer; + floatFmt->allocatedFmtStr = NULL; /* Must set to NULL, later code free memory based on this identity */ + } + + for (i = 0; i < fmtStrLen - 1; ++i) { + /* Convert wchar to char */ + floatFmt->fmtStr[i] = (char)(fmt[i]); /* Copy the format string */ + } + floatFmt->fmtStr[fmtStrLen - 1] = '\0'; + + return 0; +} + +/* Init float buffer and format, return 0 is OK */ +SECUREC_INLINE int SecInitFloatBuffer(SecFloatAdapt *floatAdapt, const SecChar *format, SecFormatAttr *attr) +{ + floatAdapt->allocatedFmtStr = NULL; + floatAdapt->fmtStr = NULL; + floatAdapt->floatBuffer = NULL; + /* Compute the precision value */ + if (attr->precision < 0) { + attr->precision = SECUREC_FLOAT_DEFAULT_PRECISION; + } + /* + * Calc buffer size to store double value + * The maximum length of SECUREC_MAX_WIDTH_LEN is enough + */ + if ((attr->flags & SECUREC_FLAG_LONG_DOUBLE) != 0) { + if (attr->precision > (SECUREC_MAX_WIDTH_LEN - SECUREC_FLOAT_BUFSIZE_LB)) { + return -1; + } + /* Long double needs to meet the basic print length */ + floatAdapt->bufferSize = SECUREC_FLOAT_BUFSIZE_LB + attr->precision + SECUREC_FLOAT_BUF_EXT; + } else { + if (attr->precision > (SECUREC_MAX_WIDTH_LEN - SECUREC_FLOAT_BUFSIZE)) { + return -1; + } + /* Double needs to meet the basic print length */ + floatAdapt->bufferSize = SECUREC_FLOAT_BUFSIZE + attr->precision + SECUREC_FLOAT_BUF_EXT; + } + if (attr->fldWidth > floatAdapt->bufferSize) { + floatAdapt->bufferSize = attr->fldWidth + SECUREC_FLOAT_BUF_EXT; + } + + if (floatAdapt->bufferSize > SECUREC_BUFFER_SIZE) { + /* The current value of SECUREC_BUFFER_SIZE could not store the formatted float string */ + floatAdapt->floatBuffer = (char *)SECUREC_MALLOC(((size_t)(unsigned int)floatAdapt->bufferSize)); + if (floatAdapt->floatBuffer == NULL) { + return -1; + } + attr->text.str = floatAdapt->floatBuffer; + } else { + attr->text.str = attr->buffer.str; /* Output buffer for float string with default size */ + } + + if (SecInitFloatFmt(floatAdapt, format) != 0) { + if (floatAdapt->floatBuffer != NULL) { + SECUREC_FREE(floatAdapt->floatBuffer); + floatAdapt->floatBuffer = NULL; + } + return -1; + } + return 0; +} +#endif + +SECUREC_INLINE SecInt64 SecUpdateNegativeChar(SecFormatAttr *attr, char ch) +{ + SecInt64 num64 = ch; /* Sign extend */ + if (num64 >= 128) { /* 128 on some platform, char is always unsigned */ + unsigned char tmp = (unsigned char)(~((unsigned char)ch)); + num64 = tmp + 1; + attr->flags |= SECUREC_FLAG_NEGATIVE; + } + return num64; +} + +/* + * If the precision is not satisfied, zero is added before the string + */ +SECUREC_INLINE void SecNumberSatisfyPrecision(SecFormatAttr *attr) +{ + int precision; + if (attr->precision < 0) { + precision = 1; /* Default precision 1 */ + } else { +#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) + attr->flags &= ~SECUREC_FLAG_LEADZERO; +#else + if ((attr->flags & SECUREC_FLAG_POINTER) == 0) { + attr->flags &= ~SECUREC_FLAG_LEADZERO; + } +#endif + if (attr->precision > SECUREC_MAX_PRECISION) { + attr->precision = SECUREC_MAX_PRECISION; + } + precision = attr->precision; + } + while (attr->textLen < precision) { + --attr->text.str; + *(attr->text.str) = '0'; + ++attr->textLen; + } +} + +/* + * Add leading zero for %#o + */ +SECUREC_INLINE void SecNumberForceOctal(SecFormatAttr *attr) +{ + /* Force a leading zero if FORCEOCTAL flag set */ + if ((attr->flags & SECUREC_FLAG_FORCE_OCTAL) != 0 && + (attr->textLen == 0 || attr->text.str[0] != '0')) { + --attr->text.str; + *(attr->text.str) = '0'; + ++attr->textLen; + } +} + +SECUREC_INLINE void SecUpdateSignedNumberPrefix(SecFormatAttr *attr) +{ + if ((attr->flags & SECUREC_FLAG_SIGNED) == 0) { + return; + } + if ((attr->flags & SECUREC_FLAG_NEGATIVE) != 0) { + /* Prefix is '-' */ + attr->prefix[0] = SECUREC_CHAR('-'); + attr->prefixLen = 1; + return; + } + if ((attr->flags & SECUREC_FLAG_SIGN) != 0) { + /* Prefix is '+' */ + attr->prefix[0] = SECUREC_CHAR('+'); + attr->prefixLen = 1; + return; + } + if ((attr->flags & SECUREC_FLAG_SIGN_SPACE) != 0) { + /* Prefix is ' ' */ + attr->prefix[0] = SECUREC_CHAR(' '); + attr->prefixLen = 1; + return; + } + return; +} + +SECUREC_INLINE void SecNumberCompatZero(SecFormatAttr *attr) +{ +#if SECUREC_IN_KERNEL + if ((attr->flags & SECUREC_FLAG_POINTER) != 0) { + static char strNullPointer[SECUREC_NULL_STRING_SIZE] = "(null)"; + attr->text.str = strNullPointer; + attr->textLen = 6; /* Length of (null) is 6 */ + attr->flags &= ~SECUREC_FLAG_LEADZERO; + attr->prefixLen = 0; + if (attr->precision >= 0 && attr->precision < attr->textLen) { + attr->textLen = attr->precision; + } + } + if ((attr->flags & SECUREC_FLAG_POINTER) == 0 && attr->radix == SECUREC_RADIX_HEX && + (attr->flags & SECUREC_FLAG_ALTERNATE) != 0) { + /* Add 0x prefix for %x or %X, the prefix string has been set before */ + attr->prefixLen = SECUREC_PREFIX_LEN; + } +#elif defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && (!defined(SECUREC_ON_UNIX)) + if ((attr->flags & SECUREC_FLAG_POINTER) != 0) { + static char strNullPointer[SECUREC_NULL_STRING_SIZE] = "(nil)"; + attr->text.str = strNullPointer; + attr->textLen = 5; /* Length of (nil) is 5 */ + attr->flags &= ~SECUREC_FLAG_LEADZERO; + } +#elif defined(SECUREC_VXWORKS_PLATFORM) || defined(__hpux) + if ((attr->flags & SECUREC_FLAG_POINTER) != 0 && (attr->flags & SECUREC_FLAG_ALTERNATE) != 0) { + /* Add 0x prefix for %p, the prefix string has been set before */ + attr->prefixLen = SECUREC_PREFIX_LEN; + } +#endif + (void)attr; /* To clear e438 last value assigned not used , the compiler will optimize this code */ +} + +/* + * Formatting output core function + */ +SECUREC_INLINE int SecOutput(SecPrintfStream *stream, const SecChar *cFormat, va_list argList) +{ + const SecChar *format = cFormat; + int charsOut; /* Characters written */ + int noOutput = 0; /* Must be initialized or compiler alerts */ + SecFmtState state; + SecFormatAttr formatAttr; + + formatAttr.flags = 0; + formatAttr.textIsWide = 0; /* Flag for buffer contains wide chars */ + formatAttr.fldWidth = 0; + formatAttr.precision = 0; + formatAttr.dynWidth = 0; + formatAttr.dynPrecision = 0; + formatAttr.digits = g_itoaUpperDigits; + formatAttr.radix = SECUREC_RADIX_DECIMAL; + formatAttr.padding = 0; + formatAttr.textLen = 0; + formatAttr.text.str = NULL; + formatAttr.prefixLen = 0; + formatAttr.prefix[0] = SECUREC_CHAR('\0'); + formatAttr.prefix[1] = SECUREC_CHAR('\0'); + charsOut = 0; + state = STAT_NORMAL; /* Starting state */ + + /* Loop each format character */ + while (*format != SECUREC_CHAR('\0') && charsOut >= 0) { + SecFmtState lastState = state; + SecChar ch = *format; /* Currently read character */ + ++format; + state = SecDecodeState(ch, lastState); + switch (state) { + case STAT_NORMAL: + SecWriteChar(stream, ch, &charsOut); + continue; + case STAT_PERCENT: + /* Set default values */ + noOutput = 0; + formatAttr.prefixLen = 0; + formatAttr.textLen = 0; + formatAttr.flags = 0; + formatAttr.fldWidth = 0; + formatAttr.precision = -1; + formatAttr.textIsWide = 0; + formatAttr.dynWidth = 0; + formatAttr.dynPrecision = 0; + break; + case STAT_FLAG: + /* Set flag based on which flag character */ + SecDecodeFlags(ch, &formatAttr); + break; + case STAT_WIDTH: + /* Update width value */ + if (ch == SECUREC_CHAR('*')) { + /* get width from arg list */ + formatAttr.fldWidth = (int)va_arg(argList, int); + formatAttr.dynWidth = 1; + } + if (SecDecodeWidth(ch, &formatAttr, lastState) != 0) { + return -1; + } + break; + case STAT_DOT: + formatAttr.precision = 0; + break; + case STAT_PRECIS: + /* Update precision value */ + if (ch == SECUREC_CHAR('*')) { + /* Get precision from arg list */ + formatAttr.precision = (int)va_arg(argList, int); + formatAttr.dynPrecision = 1; + } + if (SecDecodePrecision(ch, &formatAttr) != 0) { + return -1; + } + break; + case STAT_SIZE: + /* Read a size specifier, set the formatAttr.flags based on it, and skip format to next character */ + if (SecDecodeSize(ch, &formatAttr, &format) != 0) { + /* Compatibility code for "%I" just print I */ + SecWriteChar(stream, ch, &charsOut); + state = STAT_NORMAL; + continue; + } + break; + case STAT_TYPE: + switch (ch) { + case SECUREC_CHAR('C'): /* Wide char */ + SecUpdateWcharFlags(&formatAttr); + /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('c'): { + unsigned int cValue = (unsigned int)va_arg(argList, int); + SecDecodeTypeC(&formatAttr, cValue); + break; + } + case SECUREC_CHAR('S'): /* Wide char string */ + SecUpdateWstringFlags(&formatAttr); + /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('s'): { + char *argPtr = (char *)va_arg(argList, char *); + SecDecodeTypeS(&formatAttr, argPtr); + break; + } + case SECUREC_CHAR('G'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('g'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('E'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('F'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('e'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('f'): { +#if SECUREC_ENABLE_SPRINTF_FLOAT + /* Add following code to call system sprintf API for float number */ + SecFloatAdapt floatAdapt; + noOutput = 1; /* It's no more data needs to be written */ + + /* Now format is pointer to the next character of 'f' */ + if (SecInitFloatBuffer(&floatAdapt, format, &formatAttr) != 0) { + break; + } + + if ((formatAttr.flags & SECUREC_FLAG_LONG_DOUBLE) != 0) { +#if defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && SECUREC_ENABLE_SPRINTF_LONG_DOUBLE + long double tmp = (long double)va_arg(argList, long double); + SecFormatLongDouble(&formatAttr, &floatAdapt, tmp); +#else + double tmp = (double)va_arg(argList, double); + SecFormatDouble(&formatAttr, &floatAdapt, tmp); +#endif + } else { + double tmp = (double)va_arg(argList, double); + SecFormatDouble(&formatAttr, &floatAdapt, tmp); + } + + /* Only need write formatted float string */ + SecWriteFloatText(stream, &formatAttr, &charsOut); + SecFreeFloatBuffer(&floatAdapt); + break; +#else + return -1; +#endif + } + case SECUREC_CHAR('X'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('p'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('x'): /* fall-through */ /* FALLTHRU */ + SecUpdateXpxFlags(&formatAttr, ch); + /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('i'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('d'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('u'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('o'): { + SecInt64 num64; + SecUpdateOudiFlags(&formatAttr, ch); + /* Read argument into variable num64. Be careful, depend on the order of judgment */ + if ((formatAttr.flags & SECUREC_FLAG_I64) != 0 || + (formatAttr.flags & SECUREC_FLAG_LONGLONG) != 0) { + num64 = (SecInt64)va_arg(argList, SecInt64); /* Maximum Bit Width sign bit unchanged */ + } else if ((formatAttr.flags & SECUREC_FLAG_LONG) != 0) { + num64 = SECUREC_GET_LONG_FROM_ARG(formatAttr); + } else if ((formatAttr.flags & SECUREC_FLAG_CHAR) != 0) { + num64 = SECUREC_GET_CHAR_FROM_ARG(formatAttr); + } else if ((formatAttr.flags & SECUREC_FLAG_SHORT) != 0) { + num64 = SECUREC_GET_SHORT_FROM_ARG(formatAttr); +#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT + } else if ((formatAttr.flags & SECUREC_FLAG_PTRDIFF) != 0) { + num64 = (ptrdiff_t)va_arg(argList, ptrdiff_t); /* Sign extend */ + } else if ((formatAttr.flags & SECUREC_FLAG_SIZE) != 0) { + num64 = SECUREC_GET_SIZE_FROM_ARG(formatAttr); + } else if ((formatAttr.flags & SECUREC_FLAG_INTMAX) != 0) { + num64 = (SecInt64)va_arg(argList, SecInt64); +#endif + } else { + num64 = SECUREC_GET_INT_FROM_ARG(formatAttr); + } + + /* The order of the following calls must be correct */ + SecNumberToBuffer(&formatAttr, num64); + SecNumberSatisfyPrecision(&formatAttr); + SecNumberForceOctal(&formatAttr); + SecUpdateSignedNumberPrefix(&formatAttr); + if (num64 == 0) { + SecNumberCompatZero(&formatAttr); + } + break; + } + default: + /* Do nothing */ + break; + } + + if (noOutput == 0) { + /* Calculate amount of padding */ + formatAttr.padding = (formatAttr.fldWidth - formatAttr.textLen) - formatAttr.prefixLen; + + /* Put out the padding, prefix, and text, in the correct order */ + SecWriteLeftPadding(stream, &formatAttr, &charsOut); + SecWritePrefix(stream, &formatAttr, &charsOut); + SecWriteLeadingZero(stream, &formatAttr, &charsOut); + SecWriteText(stream, &formatAttr, &charsOut); + SecWriteRightPadding(stream, &formatAttr, &charsOut); + } + break; + case STAT_INVALID: /* fall-through */ /* FALLTHRU */ + default: + return -1; /* Input format is wrong(STAT_INVALID), directly return */ + } + } + + if (state != STAT_NORMAL && state != STAT_TYPE) { + return -1; + } + + return charsOut; /* The number of characters written */ +} + +/* + * Output one zero character zero into the SecPrintfStream structure + * If there is not enough space, make sure f->count is less than 0 + */ +SECUREC_INLINE int SecPutZeroChar(SecPrintfStream *stream) +{ + --stream->count; + if (stream->count >= 0) { + *(stream->cur) = SECUREC_CHAR('\0'); + ++stream->cur; + return 0; + } + return -1; +} + +/* + * Multi character formatted output implementation + */ +#ifdef SECUREC_FOR_WCHAR +int SecVswprintfImpl(wchar_t *string, size_t count, const wchar_t *format, va_list argList) +#else +int SecVsnprintfImpl(char *string, size_t count, const char *format, va_list argList) +#endif +{ + SecPrintfStream stream; + int retVal; + + stream.count = (int)count; /* The count include \0 character, must be greater than zero */ + stream.cur = string; + + retVal = SecOutput(&stream, format, argList); + if (retVal >= 0) { + if (SecPutZeroChar(&stream) == 0) { + return retVal; + } + } + if (stream.count < 0) { + /* The buffer was too small, then truncate */ + string[count - 1] = SECUREC_CHAR('\0'); + return SECUREC_PRINTF_TRUNCATE; + } + string[0] = SECUREC_CHAR('\0'); /* Empty the dest string */ + return -1; +} +#endif /* OUTPUT_INL_2B263E9C_43D8_44BB_B17A_6D2033DECEE5 */ + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/scanf_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/scanf_s.c new file mode 100644 index 0000000000000000000000000000000000000000..fa5470b8504ca83056952a33078d3151b27d9ae9 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/scanf_s.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: scanf_s function + * Create: 2014-02-25 + */ + +#include "securec.h" + +/* + * + * The scanf_s function is equivalent to fscanf_s with the argument stdin interposed before the arguments to scanf_s + * The scanf_s function reads data from the standard input stream stdin and + * writes the data into the location that's given by argument. Each argument + * must be a pointer to a variable of a type that corresponds to a type specifier + * in format. If copying occurs between strings that overlap, the behavior is + * undefined. + * + * + * format Format control string. + * ... Optional arguments. + * + * + * ... The converted value stored in user assigned address + * + * + * Returns the number of fields successfully converted and assigned; + * the return value does not include fields that were read but not assigned. + * A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int scanf_s(const char *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vscanf_s(format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/secinput.h b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/secinput.h new file mode 100644 index 0000000000000000000000000000000000000000..176ee05d96d42aff0aa5968686d4584e5c6a2d8c --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/secinput.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: Define macro, data struct, and declare function prototype, + * which is used by input.inl, secureinput_a.c and secureinput_w.c. + * Create: 2014-02-25 + */ + +#ifndef SEC_INPUT_H_E950DA2C_902F_4B15_BECD_948E99090D9C +#define SEC_INPUT_H_E950DA2C_902F_4B15_BECD_948E99090D9C +#include "securecutil.h" + +#define SECUREC_SCANF_EINVAL (-1) +#define SECUREC_SCANF_ERROR_PARA (-2) + +/* For internal stream flag */ +#define SECUREC_MEM_STR_FLAG 0x01U +#define SECUREC_FILE_STREAM_FLAG 0x02U +#define SECUREC_PIPE_STREAM_FLAG 0x04U +#define SECUREC_LOAD_FILE_TO_MEM_FLAG 0x08U + +#define SECUREC_UCS_BOM_HEADER_SIZE 2U +#define SECUREC_UCS_BOM_HEADER_BE_1ST 0xfeU +#define SECUREC_UCS_BOM_HEADER_BE_2ST 0xffU +#define SECUREC_UCS_BOM_HEADER_LE_1ST 0xffU +#define SECUREC_UCS_BOM_HEADER_LE_2ST 0xfeU +#define SECUREC_UTF8_BOM_HEADER_SIZE 3U +#define SECUREC_UTF8_BOM_HEADER_1ST 0xefU +#define SECUREC_UTF8_BOM_HEADER_2ND 0xbbU +#define SECUREC_UTF8_BOM_HEADER_3RD 0xbfU +#define SECUREC_UTF8_LEAD_1ST 0xe0U +#define SECUREC_UTF8_LEAD_2ND 0x80U + +#define SECUREC_BEGIN_WITH_UCS_BOM(s, len) ((len) == SECUREC_UCS_BOM_HEADER_SIZE && \ + (((unsigned char)((s)[0]) == SECUREC_UCS_BOM_HEADER_LE_1ST && \ + (unsigned char)((s)[1]) == SECUREC_UCS_BOM_HEADER_LE_2ST) || \ + ((unsigned char)((s)[0]) == SECUREC_UCS_BOM_HEADER_BE_1ST && \ + (unsigned char)((s)[1]) == SECUREC_UCS_BOM_HEADER_BE_2ST))) + +#define SECUREC_BEGIN_WITH_UTF8_BOM(s, len) ((len) == SECUREC_UTF8_BOM_HEADER_SIZE && \ + (unsigned char)((s)[0]) == SECUREC_UTF8_BOM_HEADER_1ST && \ + (unsigned char)((s)[1]) == SECUREC_UTF8_BOM_HEADER_2ND && \ + (unsigned char)((s)[2]) == SECUREC_UTF8_BOM_HEADER_3RD) + +#ifdef SECUREC_FOR_WCHAR +#define SECUREC_BOM_HEADER_SIZE SECUREC_UCS_BOM_HEADER_SIZE +#define SECUREC_BEGIN_WITH_BOM(s, len) SECUREC_BEGIN_WITH_UCS_BOM((s), (len)) +#else +#define SECUREC_BOM_HEADER_SIZE SECUREC_UTF8_BOM_HEADER_SIZE +#define SECUREC_BEGIN_WITH_BOM(s, len) SECUREC_BEGIN_WITH_UTF8_BOM((s), (len)) +#endif + +typedef struct { + unsigned int flag; /* Mark the properties of input stream */ + char *base; /* The pointer to the header of buffered string */ + const char *cur; /* The pointer to next read position */ + size_t count; /* The size of buffered string in bytes */ +#if SECUREC_ENABLE_SCANF_FILE + FILE *pf; /* The file pointer */ + size_t fileRealRead; + long oriFilePos; /* The original position of file offset when fscanf is called */ +#endif +} SecFileStream; + +#if SECUREC_ENABLE_SCANF_FILE +#define SECUREC_FILE_STREAM_INIT_FILE(stream, fp) do { \ + (stream)->pf = (fp); \ + (stream)->fileRealRead = 0; \ + (stream)->oriFilePos = 0; \ +} SECUREC_WHILE_ZERO +#else +/* Disable file */ +#define SECUREC_FILE_STREAM_INIT_FILE(stream, fp) +#endif + +/* This initialization for eliminating redundant initialization. */ +#define SECUREC_FILE_STREAM_FROM_STRING(stream, buf, cnt) do { \ + (stream)->flag = SECUREC_MEM_STR_FLAG; \ + (stream)->base = NULL; \ + (stream)->cur = (buf); \ + (stream)->count = (cnt); \ + SECUREC_FILE_STREAM_INIT_FILE((stream), NULL); \ +} SECUREC_WHILE_ZERO + +/* This initialization for eliminating redundant initialization. */ +#define SECUREC_FILE_STREAM_FROM_FILE(stream, fp) do { \ + (stream)->flag = SECUREC_FILE_STREAM_FLAG; \ + (stream)->base = NULL; \ + (stream)->cur = NULL; \ + (stream)->count = 0; \ + SECUREC_FILE_STREAM_INIT_FILE((stream), (fp)); \ +} SECUREC_WHILE_ZERO + +/* This initialization for eliminating redundant initialization. */ +#define SECUREC_FILE_STREAM_FROM_STDIN(stream) do { \ + (stream)->flag = SECUREC_PIPE_STREAM_FLAG; \ + (stream)->base = NULL; \ + (stream)->cur = NULL; \ + (stream)->count = 0; \ + SECUREC_FILE_STREAM_INIT_FILE((stream), SECUREC_STREAM_STDIN); \ +} SECUREC_WHILE_ZERO + +#ifdef __cplusplus +extern "C" { +#endif +int SecInputS(SecFileStream *stream, const char *cFormat, va_list argList); +void SecClearDestBuf(const char *buffer, const char *format, va_list argList); +#ifdef SECUREC_FOR_WCHAR +int SecInputSW(SecFileStream *stream, const wchar_t *cFormat, va_list argList); +void SecClearDestBufW(const wchar_t *buffer, const wchar_t *format, va_list argList); +#endif + +/* 20150105 For software and hardware decoupling,such as UMG */ +#ifdef SECUREC_SYSAPI4VXWORKS +#ifdef feof +#undef feof +#endif +extern int feof(FILE *stream); +#endif + +#if defined(SECUREC_SYSAPI4VXWORKS) || defined(SECUREC_CTYPE_MACRO_ADAPT) +#ifndef isspace +#define isspace(c) (((c) == ' ') || ((c) == '\t') || ((c) == '\r') || ((c) == '\n')) +#endif +#ifndef iswspace +#define iswspace(c) (((c) == L' ') || ((c) == L'\t') || ((c) == L'\r') || ((c) == L'\n')) +#endif +#ifndef isascii +#define isascii(c) (((unsigned char)(c)) <= 0x7f) +#endif +#ifndef isupper +#define isupper(c) ((c) >= 'A' && (c) <= 'Z') +#endif +#ifndef islower +#define islower(c) ((c) >= 'a' && (c) <= 'z') +#endif +#ifndef isalpha +#define isalpha(c) (isupper(c) || (islower(c))) +#endif +#ifndef isdigit +#define isdigit(c) ((c) >= '0' && (c) <= '9') +#endif +#ifndef isxupper +#define isxupper(c) ((c) >= 'A' && (c) <= 'F') +#endif +#ifndef isxlower +#define isxlower(c) ((c) >= 'a' && (c) <= 'f') +#endif +#ifndef isxdigit +#define isxdigit(c) (isdigit(c) || isxupper(c) || isxlower(c)) +#endif +#endif + +#ifdef __cplusplus +} +#endif +/* Reserved file operation macro interface, s is FILE *, i is fileno zero. */ +#ifndef SECUREC_LOCK_FILE +#define SECUREC_LOCK_FILE(s) +#endif + +#ifndef SECUREC_UNLOCK_FILE +#define SECUREC_UNLOCK_FILE(s) +#endif + +#ifndef SECUREC_LOCK_STDIN +#define SECUREC_LOCK_STDIN(i, s) +#endif + +#ifndef SECUREC_UNLOCK_STDIN +#define SECUREC_UNLOCK_STDIN(i, s) +#endif +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/securecutil.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/securecutil.c new file mode 100644 index 0000000000000000000000000000000000000000..0053a72cfab51526702fecc78d1cbe4616e68abb --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/securecutil.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: Provides internal functions used by this library, such as memory + * copy and memory move. Besides, include some helper function for + * printf family API, such as SecVsnprintfImpl + * Create: 2014-02-25 + */ + +/* Avoid duplicate header files,not include securecutil.h */ +#include "securecutil.h" + +#if defined(ANDROID) && !defined(SECUREC_CLOSE_ANDROID_HANDLE) && (SECUREC_HAVE_WCTOMB || SECUREC_HAVE_MBTOWC) +#include +#if SECUREC_HAVE_WCTOMB +/* + * Convert wide characters to narrow multi-bytes + */ +int wctomb(char *s, wchar_t wc) +{ + return (int)wcrtomb(s, wc, NULL); +} +#endif + +#if SECUREC_HAVE_MBTOWC +/* + * Converting narrow multi-byte characters to wide characters + * mbrtowc returns -1 or -2 upon failure, unlike mbtowc, which only returns -1 + * When the return value is less than zero, we treat it as a failure + */ +int mbtowc(wchar_t *pwc, const char *s, size_t n) +{ + return (int)mbrtowc(pwc, s, n, NULL); +} +#endif +#endif + +/* The V100R001C01 version num is 0x5 (High 8 bits) */ +#define SECUREC_C_VERSION 0x500U +#define SECUREC_SPC_VERSION 0x10U +#define SECUREC_VERSION_STR "1.1.16" + +/* + * Get version string and version number. + * The rules for version number are as follows: + * 1) SPC verNumber<->verStr like: + * 0x201<->C01 + * 0x202<->C01SPC001 Redefine numbers after this version + * 0x502<->C01SPC002 + * 0x503<->C01SPC003 + * ... + * 0X50a<->SPC010 + * 0X50b<->SPC011 + * ... + * 0x700<->C02 + * 0x701<->C01SPC001 + * 0x702<->C02SPC002 + * ... + * 2) CP verNumber<->verStr like: + * 0X601<->CP0001 + * 0X602<->CP0002 + * ... + */ +const char *GetHwSecureCVersion(unsigned short *verNumber) +{ + if (verNumber != NULL) { + *verNumber = (unsigned short)(SECUREC_C_VERSION | SECUREC_SPC_VERSION); + } + return SECUREC_VERSION_STR; +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(GetHwSecureCVersion); +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/securecutil.h b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/securecutil.h new file mode 100644 index 0000000000000000000000000000000000000000..7e3bd691f9ece9decd2fcb3c239697c806597246 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/securecutil.h @@ -0,0 +1,574 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: Define macro, data struct, and declare internal used function prototype, + * which is used by secure functions. + * Create: 2014-02-25 + */ + +#ifndef SECURECUTIL_H_46C86578_F8FF_4E49_8E64_9B175241761F +#define SECURECUTIL_H_46C86578_F8FF_4E49_8E64_9B175241761F +#include "securec.h" + +#if (defined(_MSC_VER)) && (_MSC_VER >= 1400) +/* Shield compilation alerts using discarded functions and Constant expression to maximize code compatibility */ +#define SECUREC_MASK_MSVC_CRT_WARNING __pragma(warning(push)) \ + __pragma(warning(disable : 4996 4127)) +#define SECUREC_END_MASK_MSVC_CRT_WARNING __pragma(warning(pop)) +#else +#define SECUREC_MASK_MSVC_CRT_WARNING +#define SECUREC_END_MASK_MSVC_CRT_WARNING +#endif +#define SECUREC_WHILE_ZERO SECUREC_MASK_MSVC_CRT_WARNING while (0) SECUREC_END_MASK_MSVC_CRT_WARNING + +/* Automatically identify the platform that supports strnlen function, and use this function to improve performance */ +#ifndef SECUREC_HAVE_STRNLEN +#if (defined(_XOPEN_SOURCE) && _XOPEN_SOURCE >= 700) || (defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE >= 200809L) +#if SECUREC_IN_KERNEL +#define SECUREC_HAVE_STRNLEN 0 +#else +#if defined(__GLIBC__) && __GLIBC__ >= 2 && defined(__GLIBC_MINOR__) && __GLIBC_MINOR__ >= 10 +#define SECUREC_HAVE_STRNLEN 1 +#else +#define SECUREC_HAVE_STRNLEN 0 +#endif +#endif +#else +#define SECUREC_HAVE_STRNLEN 0 +#endif +#endif + +#if SECUREC_IN_KERNEL +/* In kernel disable functions */ +#ifndef SECUREC_ENABLE_SCANF_FILE +#define SECUREC_ENABLE_SCANF_FILE 0 +#endif +#ifndef SECUREC_ENABLE_SCANF_FLOAT +#define SECUREC_ENABLE_SCANF_FLOAT 0 +#endif +#ifndef SECUREC_ENABLE_SPRINTF_FLOAT +#define SECUREC_ENABLE_SPRINTF_FLOAT 0 +#endif +#ifndef SECUREC_HAVE_MBTOWC +#define SECUREC_HAVE_MBTOWC 0 +#endif +#ifndef SECUREC_HAVE_WCTOMB +#define SECUREC_HAVE_WCTOMB 0 +#endif +#ifndef SECUREC_HAVE_WCHART +#define SECUREC_HAVE_WCHART 0 +#endif +#else /* Not in kernel */ +/* Systems that do not support file, can define this macro to 0. */ +#ifndef SECUREC_ENABLE_SCANF_FILE +#define SECUREC_ENABLE_SCANF_FILE 1 +#endif +#ifndef SECUREC_ENABLE_SCANF_FLOAT +#define SECUREC_ENABLE_SCANF_FLOAT 1 +#endif +/* Systems that do not support float, can define this macro to 0. */ +#ifndef SECUREC_ENABLE_SPRINTF_FLOAT +#define SECUREC_ENABLE_SPRINTF_FLOAT 1 +#endif +#ifndef SECUREC_HAVE_MBTOWC +#define SECUREC_HAVE_MBTOWC 1 +#endif +#ifndef SECUREC_HAVE_WCTOMB +#define SECUREC_HAVE_WCTOMB 1 +#endif +#ifndef SECUREC_HAVE_WCHART +#define SECUREC_HAVE_WCHART 1 +#endif +#endif + +#ifndef SECUREC_ENABLE_INLINE +#define SECUREC_ENABLE_INLINE 0 +#endif + +#ifndef SECUREC_INLINE +#if SECUREC_ENABLE_INLINE +#define SECUREC_INLINE static inline +#else +#define SECUREC_INLINE static +#endif +#endif + +#ifndef SECUREC_WARP_OUTPUT +#if SECUREC_IN_KERNEL +#define SECUREC_WARP_OUTPUT 1 +#else +#define SECUREC_WARP_OUTPUT 0 +#endif +#endif + +#ifndef SECUREC_STREAM_STDIN +#define SECUREC_STREAM_STDIN stdin +#endif + +#define SECUREC_MUL_SIXTEEN(x) ((x) << 4U) +#define SECUREC_MUL_EIGHT(x) ((x) << 3U) +#define SECUREC_MUL_TEN(x) ((((x) << 2U) + (x)) << 1U) +/* Limited format input and output width, use signed integer */ +#define SECUREC_MAX_WIDTH_LEN_DIV_TEN 21474836 +#define SECUREC_MAX_WIDTH_LEN (SECUREC_MAX_WIDTH_LEN_DIV_TEN * 10) +/* Is the x multiplied by 10 greater than */ +#define SECUREC_MUL_TEN_ADD_BEYOND_MAX(x) (((x) > SECUREC_MAX_WIDTH_LEN_DIV_TEN)) + +#define SECUREC_FLOAT_BUFSIZE (309 + 40) /* Max length of double value */ +#define SECUREC_FLOAT_BUFSIZE_LB (4932 + 40) /* Max length of long double value */ +#define SECUREC_FLOAT_DEFAULT_PRECISION 6 + +/* This macro does not handle pointer equality or integer overflow */ +#define SECUREC_MEMORY_NO_OVERLAP(dest, src, count) \ + (((src) < (dest) && ((const char *)(src) + (count)) <= (char *)(dest)) || \ + ((dest) < (src) && ((char *)(dest) + (count)) <= (const char *)(src))) + +#define SECUREC_MEMORY_IS_OVERLAP(dest, src, count) \ + (((src) < (dest) && ((const char *)(src) + (count)) > (char *)(dest)) || \ + ((dest) < (src) && ((char *)(dest) + (count)) > (const char *)(src))) + +/* + * Check whether the strings overlap, len is the length of the string not include terminator + * Length is related to data type char or wchar , do not force conversion of types + */ +#define SECUREC_STRING_NO_OVERLAP(dest, src, len) \ + (((src) < (dest) && ((src) + (len)) < (dest)) || \ + ((dest) < (src) && ((dest) + (len)) < (src))) + +/* + * Check whether the strings overlap for strcpy wcscpy function, dest len and src Len are not include terminator + * Length is related to data type char or wchar , do not force conversion of types + */ +#define SECUREC_STRING_IS_OVERLAP(dest, src, len) \ + (((src) < (dest) && ((src) + (len)) >= (dest)) || \ + ((dest) < (src) && ((dest) + (len)) >= (src))) + +/* + * Check whether the strings overlap for strcat wcscat function, dest len and src Len are not include terminator + * Length is related to data type char or wchar , do not force conversion of types + */ +#define SECUREC_CAT_STRING_IS_OVERLAP(dest, destLen, src, srcLen) \ + (((dest) < (src) && ((dest) + (destLen) + (srcLen)) >= (src)) || \ + ((src) < (dest) && ((src) + (srcLen)) >= (dest))) + +#if SECUREC_HAVE_STRNLEN +#define SECUREC_CALC_STR_LEN(str, maxLen, outLen) do { \ + *(outLen) = strnlen((str), (maxLen)); \ +} SECUREC_WHILE_ZERO +#define SECUREC_CALC_STR_LEN_OPT(str, maxLen, outLen) do { \ + if ((maxLen) > 8) { \ + /* Optimization or len less then 8 */ \ + if (*((str) + 0) == '\0') { \ + *(outLen) = 0; \ + } else if (*((str) + 1) == '\0') { \ + *(outLen) = 1; \ + } else if (*((str) + 2) == '\0') { \ + *(outLen) = 2; \ + } else if (*((str) + 3) == '\0') { \ + *(outLen) = 3; \ + } else if (*((str) + 4) == '\0') { \ + *(outLen) = 4; \ + } else if (*((str) + 5) == '\0') { \ + *(outLen) = 5; \ + } else if (*((str) + 6) == '\0') { \ + *(outLen) = 6; \ + } else if (*((str) + 7) == '\0') { \ + *(outLen) = 7; \ + } else if (*((str) + 8) == '\0') { \ + /* Optimization with a length of 8 */ \ + *(outLen) = 8; \ + } else { \ + /* The offset is 8 because the performance of 8 byte alignment is high */ \ + *(outLen) = 8 + strnlen((str) + 8, (maxLen) - 8); \ + } \ + } else { \ + SECUREC_CALC_STR_LEN((str), (maxLen), (outLen)); \ + } \ +} SECUREC_WHILE_ZERO +#else +#define SECUREC_CALC_STR_LEN(str, maxLen, outLen) do { \ + const char *strEnd_ = (const char *)(str); \ + size_t availableSize_ = (size_t)(maxLen); \ + while (availableSize_ > 0 && *strEnd_ != '\0') { \ + --availableSize_; \ + ++strEnd_; \ + } \ + *(outLen) = (size_t)(strEnd_ - (str)); \ +} SECUREC_WHILE_ZERO +#define SECUREC_CALC_STR_LEN_OPT SECUREC_CALC_STR_LEN +#endif + +#define SECUREC_CALC_WSTR_LEN(str, maxLen, outLen) do { \ + const wchar_t *strEnd_ = (const wchar_t *)(str); \ + size_t len_ = 0; \ + while (len_ < (maxLen) && *strEnd_ != L'\0') { \ + ++len_; \ + ++strEnd_; \ + } \ + *(outLen) = len_; \ +} SECUREC_WHILE_ZERO + +/* + * Performance optimization, product may disable inline function. + * Using function pointer for MEMSET to prevent compiler optimization when cleaning up memory. + */ +#ifdef SECUREC_USE_ASM +#define SECUREC_MEMSET_FUNC_OPT memset_opt +#define SECUREC_MEMCPY_FUNC_OPT memcpy_opt +#else +#define SECUREC_MEMSET_FUNC_OPT memset +#define SECUREC_MEMCPY_FUNC_OPT memcpy +#endif + +#define SECUREC_MEMCPY_WARP_OPT(dest, src, count) (void)SECUREC_MEMCPY_FUNC_OPT((dest), (src), (count)) + +#ifndef SECUREC_MEMSET_BARRIER +#if defined(__GNUC__) +/* Can be turned off for scenarios that do not use memory barrier */ +#define SECUREC_MEMSET_BARRIER 1 +#else +#define SECUREC_MEMSET_BARRIER 0 +#endif +#endif + +#ifndef SECUREC_MEMSET_INDIRECT_USE +/* Can be turned off for scenarios that do not allow pointer calls */ +#define SECUREC_MEMSET_INDIRECT_USE 1 +#endif + +#if SECUREC_MEMSET_BARRIER +#define SECUREC_MEMORY_BARRIER(dest) __asm__ __volatile__("": : "r"(dest) : "memory") +#else +#define SECUREC_MEMORY_BARRIER(dest) +#endif + +#if SECUREC_MEMSET_BARRIER +#define SECUREC_MEMSET_PREVENT_DSE(dest, value, count) do { \ + (void)SECUREC_MEMSET_FUNC_OPT(dest, value, count); \ + SECUREC_MEMORY_BARRIER(dest); \ +} SECUREC_WHILE_ZERO +#elif SECUREC_MEMSET_INDIRECT_USE +#define SECUREC_MEMSET_PREVENT_DSE(dest, value, count) do { \ + void *(* const volatile fn_)(void *s_, int c_, size_t n_) = SECUREC_MEMSET_FUNC_OPT; \ + (void)(*fn_)((dest), (value), (count)); \ +} SECUREC_WHILE_ZERO +#else +#define SECUREC_MEMSET_PREVENT_DSE(dest, value, count) (void)SECUREC_MEMSET_FUNC_OPT((dest), (value), (count)) +#endif + +#ifdef SECUREC_FORMAT_OUTPUT_INPUT +#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) || defined(__ARMCC_VERSION) +typedef __int64 SecInt64; +typedef unsigned __int64 SecUnsignedInt64; +#if defined(__ARMCC_VERSION) +typedef unsigned int SecUnsignedInt32; +#else +typedef unsigned __int32 SecUnsignedInt32; +#endif +#else +typedef unsigned int SecUnsignedInt32; +typedef long long SecInt64; +typedef unsigned long long SecUnsignedInt64; +#endif + +#ifdef SECUREC_FOR_WCHAR +#if defined(SECUREC_VXWORKS_PLATFORM) && !defined(__WINT_TYPE__) +typedef wchar_t wint_t; +#endif +#ifndef WEOF +#define WEOF ((wchar_t)(-1)) +#endif +#define SECUREC_CHAR(x) L ## x +typedef wchar_t SecChar; +typedef wchar_t SecUnsignedChar; +typedef wint_t SecInt; +typedef wint_t SecUnsignedInt; +#else /* no SECUREC_FOR_WCHAR */ +#define SECUREC_CHAR(x) (x) +typedef char SecChar; +typedef unsigned char SecUnsignedChar; +typedef int SecInt; +typedef unsigned int SecUnsignedInt; +#endif +#endif + +/* + * Determine whether the address is 8-byte aligned + * Some systems do not have uintptr_t type, so use NULL to clear tool alarm 507 + */ +#define SECUREC_ADDR_ALIGNED_8(addr) ((((size_t)(addr)) & 7U) == 0) /* Use 7 to check aligned 8 */ + +/* + * If you define the memory allocation function, you need to define the function prototype. + * You can define this macro as a header file. + */ +#if defined(SECUREC_MALLOC_PROTOTYPE) +SECUREC_MALLOC_PROTOTYPE +#endif + +#ifndef SECUREC_MALLOC +#define SECUREC_MALLOC(x) malloc((size_t)(x)) +#endif + +#ifndef SECUREC_FREE +#define SECUREC_FREE(x) free((void *)(x)) +#endif + +/* Improve performance with struct assignment, buf1 is not defined to avoid tool false positive */ +#define SECUREC_COPY_VALUE_BY_STRUCT(dest, src, n) do { \ + *(SecStrBuf##n *)(void *)(dest) = *(const SecStrBuf##n *)(const void *)(src); \ +} SECUREC_WHILE_ZERO + +typedef struct { + unsigned char buf[2]; /* Performance optimization code structure assignment length 2 bytes */ +} SecStrBuf2; +typedef struct { + unsigned char buf[3]; /* Performance optimization code structure assignment length 3 bytes */ +} SecStrBuf3; +typedef struct { + unsigned char buf[4]; /* Performance optimization code structure assignment length 4 bytes */ +} SecStrBuf4; +typedef struct { + unsigned char buf[5]; /* Performance optimization code structure assignment length 5 bytes */ +} SecStrBuf5; +typedef struct { + unsigned char buf[6]; /* Performance optimization code structure assignment length 6 bytes */ +} SecStrBuf6; +typedef struct { + unsigned char buf[7]; /* Performance optimization code structure assignment length 7 bytes */ +} SecStrBuf7; +typedef struct { + unsigned char buf[8]; /* Performance optimization code structure assignment length 8 bytes */ +} SecStrBuf8; +typedef struct { + unsigned char buf[9]; /* Performance optimization code structure assignment length 9 bytes */ +} SecStrBuf9; +typedef struct { + unsigned char buf[10]; /* Performance optimization code structure assignment length 10 bytes */ +} SecStrBuf10; +typedef struct { + unsigned char buf[11]; /* Performance optimization code structure assignment length 11 bytes */ +} SecStrBuf11; +typedef struct { + unsigned char buf[12]; /* Performance optimization code structure assignment length 12 bytes */ +} SecStrBuf12; +typedef struct { + unsigned char buf[13]; /* Performance optimization code structure assignment length 13 bytes */ +} SecStrBuf13; +typedef struct { + unsigned char buf[14]; /* Performance optimization code structure assignment length 14 bytes */ +} SecStrBuf14; +typedef struct { + unsigned char buf[15]; /* Performance optimization code structure assignment length 15 bytes */ +} SecStrBuf15; +typedef struct { + unsigned char buf[16]; /* Performance optimization code structure assignment length 16 bytes */ +} SecStrBuf16; +typedef struct { + unsigned char buf[17]; /* Performance optimization code structure assignment length 17 bytes */ +} SecStrBuf17; +typedef struct { + unsigned char buf[18]; /* Performance optimization code structure assignment length 18 bytes */ +} SecStrBuf18; +typedef struct { + unsigned char buf[19]; /* Performance optimization code structure assignment length 19 bytes */ +} SecStrBuf19; +typedef struct { + unsigned char buf[20]; /* Performance optimization code structure assignment length 20 bytes */ +} SecStrBuf20; +typedef struct { + unsigned char buf[21]; /* Performance optimization code structure assignment length 21 bytes */ +} SecStrBuf21; +typedef struct { + unsigned char buf[22]; /* Performance optimization code structure assignment length 22 bytes */ +} SecStrBuf22; +typedef struct { + unsigned char buf[23]; /* Performance optimization code structure assignment length 23 bytes */ +} SecStrBuf23; +typedef struct { + unsigned char buf[24]; /* Performance optimization code structure assignment length 24 bytes */ +} SecStrBuf24; +typedef struct { + unsigned char buf[25]; /* Performance optimization code structure assignment length 25 bytes */ +} SecStrBuf25; +typedef struct { + unsigned char buf[26]; /* Performance optimization code structure assignment length 26 bytes */ +} SecStrBuf26; +typedef struct { + unsigned char buf[27]; /* Performance optimization code structure assignment length 27 bytes */ +} SecStrBuf27; +typedef struct { + unsigned char buf[28]; /* Performance optimization code structure assignment length 28 bytes */ +} SecStrBuf28; +typedef struct { + unsigned char buf[29]; /* Performance optimization code structure assignment length 29 bytes */ +} SecStrBuf29; +typedef struct { + unsigned char buf[30]; /* Performance optimization code structure assignment length 30 bytes */ +} SecStrBuf30; +typedef struct { + unsigned char buf[31]; /* Performance optimization code structure assignment length 31 bytes */ +} SecStrBuf31; +typedef struct { + unsigned char buf[32]; /* Performance optimization code structure assignment length 32 bytes */ +} SecStrBuf32; +typedef struct { + unsigned char buf[33]; /* Performance optimization code structure assignment length 33 bytes */ +} SecStrBuf33; +typedef struct { + unsigned char buf[34]; /* Performance optimization code structure assignment length 34 bytes */ +} SecStrBuf34; +typedef struct { + unsigned char buf[35]; /* Performance optimization code structure assignment length 35 bytes */ +} SecStrBuf35; +typedef struct { + unsigned char buf[36]; /* Performance optimization code structure assignment length 36 bytes */ +} SecStrBuf36; +typedef struct { + unsigned char buf[37]; /* Performance optimization code structure assignment length 37 bytes */ +} SecStrBuf37; +typedef struct { + unsigned char buf[38]; /* Performance optimization code structure assignment length 38 bytes */ +} SecStrBuf38; +typedef struct { + unsigned char buf[39]; /* Performance optimization code structure assignment length 39 bytes */ +} SecStrBuf39; +typedef struct { + unsigned char buf[40]; /* Performance optimization code structure assignment length 40 bytes */ +} SecStrBuf40; +typedef struct { + unsigned char buf[41]; /* Performance optimization code structure assignment length 41 bytes */ +} SecStrBuf41; +typedef struct { + unsigned char buf[42]; /* Performance optimization code structure assignment length 42 bytes */ +} SecStrBuf42; +typedef struct { + unsigned char buf[43]; /* Performance optimization code structure assignment length 43 bytes */ +} SecStrBuf43; +typedef struct { + unsigned char buf[44]; /* Performance optimization code structure assignment length 44 bytes */ +} SecStrBuf44; +typedef struct { + unsigned char buf[45]; /* Performance optimization code structure assignment length 45 bytes */ +} SecStrBuf45; +typedef struct { + unsigned char buf[46]; /* Performance optimization code structure assignment length 46 bytes */ +} SecStrBuf46; +typedef struct { + unsigned char buf[47]; /* Performance optimization code structure assignment length 47 bytes */ +} SecStrBuf47; +typedef struct { + unsigned char buf[48]; /* Performance optimization code structure assignment length 48 bytes */ +} SecStrBuf48; +typedef struct { + unsigned char buf[49]; /* Performance optimization code structure assignment length 49 bytes */ +} SecStrBuf49; +typedef struct { + unsigned char buf[50]; /* Performance optimization code structure assignment length 50 bytes */ +} SecStrBuf50; +typedef struct { + unsigned char buf[51]; /* Performance optimization code structure assignment length 51 bytes */ +} SecStrBuf51; +typedef struct { + unsigned char buf[52]; /* Performance optimization code structure assignment length 52 bytes */ +} SecStrBuf52; +typedef struct { + unsigned char buf[53]; /* Performance optimization code structure assignment length 53 bytes */ +} SecStrBuf53; +typedef struct { + unsigned char buf[54]; /* Performance optimization code structure assignment length 54 bytes */ +} SecStrBuf54; +typedef struct { + unsigned char buf[55]; /* Performance optimization code structure assignment length 55 bytes */ +} SecStrBuf55; +typedef struct { + unsigned char buf[56]; /* Performance optimization code structure assignment length 56 bytes */ +} SecStrBuf56; +typedef struct { + unsigned char buf[57]; /* Performance optimization code structure assignment length 57 bytes */ +} SecStrBuf57; +typedef struct { + unsigned char buf[58]; /* Performance optimization code structure assignment length 58 bytes */ +} SecStrBuf58; +typedef struct { + unsigned char buf[59]; /* Performance optimization code structure assignment length 59 bytes */ +} SecStrBuf59; +typedef struct { + unsigned char buf[60]; /* Performance optimization code structure assignment length 60 bytes */ +} SecStrBuf60; +typedef struct { + unsigned char buf[61]; /* Performance optimization code structure assignment length 61 bytes */ +} SecStrBuf61; +typedef struct { + unsigned char buf[62]; /* Performance optimization code structure assignment length 62 bytes */ +} SecStrBuf62; +typedef struct { + unsigned char buf[63]; /* Performance optimization code structure assignment length 63 bytes */ +} SecStrBuf63; +typedef struct { + unsigned char buf[64]; /* Performance optimization code structure assignment length 64 bytes */ +} SecStrBuf64; + +/* + * User can change the error handler by modify the following definition, + * such as logging the detail error in file. + */ +#if defined(_DEBUG) || defined(DEBUG) +#if defined(SECUREC_ERROR_HANDLER_BY_ASSERT) +#define SECUREC_ERROR_INVALID_PARAMTER(msg) assert(msg "invalid argument" == NULL) +#define SECUREC_ERROR_INVALID_RANGE(msg) assert(msg "invalid dest buffer size" == NULL) +#define SECUREC_ERROR_BUFFER_OVERLAP(msg) assert(msg "buffer overlap" == NULL) +#elif defined(SECUREC_ERROR_HANDLER_BY_PRINTF) +#if SECUREC_IN_KERNEL +#define SECUREC_ERROR_INVALID_PARAMTER(msg) printk("%s invalid argument\n", msg) +#define SECUREC_ERROR_INVALID_RANGE(msg) printk("%s invalid dest buffer size\n", msg) +#define SECUREC_ERROR_BUFFER_OVERLAP(msg) printk("%s buffer overlap\n", msg) +#else +#define SECUREC_ERROR_INVALID_PARAMTER(msg) printf("%s invalid argument\n", msg) +#define SECUREC_ERROR_INVALID_RANGE(msg) printf("%s invalid dest buffer size\n", msg) +#define SECUREC_ERROR_BUFFER_OVERLAP(msg) printf("%s buffer overlap\n", msg) +#endif +#elif defined(SECUREC_ERROR_HANDLER_BY_FILE_LOG) +#define SECUREC_ERROR_INVALID_PARAMTER(msg) LogSecureCRuntimeError(msg " EINVAL\n") +#define SECUREC_ERROR_INVALID_RANGE(msg) LogSecureCRuntimeError(msg " ERANGE\n") +#define SECUREC_ERROR_BUFFER_OVERLAP(msg) LogSecureCRuntimeError(msg " EOVERLAP\n") +#endif +#endif + +/* Default handler is none */ +#ifndef SECUREC_ERROR_INVALID_PARAMTER +#define SECUREC_ERROR_INVALID_PARAMTER(msg) +#endif +#ifndef SECUREC_ERROR_INVALID_RANGE +#define SECUREC_ERROR_INVALID_RANGE(msg) +#endif +#ifndef SECUREC_ERROR_BUFFER_OVERLAP +#define SECUREC_ERROR_BUFFER_OVERLAP(msg) +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* Assembly language memory copy and memory set for X86 or MIPS ... */ +#ifdef SECUREC_USE_ASM +void *memcpy_opt(void *dest, const void *src, size_t n); +void *memset_opt(void *s, int c, size_t n); +#endif + +#if defined(SECUREC_ERROR_HANDLER_BY_FILE_LOG) +void LogSecureCRuntimeError(const char *errDetail); +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_a.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_a.c new file mode 100644 index 0000000000000000000000000000000000000000..e79868f45eff5a3800774c055b9003e4c00561b0 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_a.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: By defining data type for ANSI string and including "input.inl", + * this file generates real underlying function used by scanf family API. + * Create: 2014-02-25 + */ + +#define SECUREC_FORMAT_OUTPUT_INPUT 1 +#ifdef SECUREC_FOR_WCHAR +#undef SECUREC_FOR_WCHAR +#endif + +#include "secinput.h" + +#include "input.inl" + +SECUREC_INLINE int SecIsDigit(SecInt ch) +{ + /* SecInt to unsigned char clear 571, use bit mask to clear negative return of ch */ + return isdigit((int)((unsigned int)(unsigned char)(ch) & 0xffU)); +} +SECUREC_INLINE int SecIsXdigit(SecInt ch) +{ + return isxdigit((int)((unsigned int)(unsigned char)(ch) & 0xffU)); +} +SECUREC_INLINE int SecIsSpace(SecInt ch) +{ + return isspace((int)((unsigned int)(unsigned char)(ch) & 0xffU)); +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_w.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_w.c new file mode 100644 index 0000000000000000000000000000000000000000..12c9ef813ddb9fdd4d50d495714a37ab6915c781 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_w.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: By defining data type for UNICODE string and including "input.inl", + * this file generates real underlying function used by scanf family API. + * Create: 2014-02-25 + */ + +/* If some platforms don't have wchar.h, don't include it */ +#if !(defined(SECUREC_VXWORKS_PLATFORM)) +/* If there is no macro below, it will cause vs2010 compiling alarm */ +#if defined(_MSC_VER) && (_MSC_VER >= 1400) +#ifndef __STDC_WANT_SECURE_LIB__ +/* The order of adjustment is to eliminate alarm of Duplicate Block */ +#define __STDC_WANT_SECURE_LIB__ 0 +#endif +#ifndef _CRTIMP_ALTERNATIVE +#define _CRTIMP_ALTERNATIVE /* Comment microsoft *_s function */ +#endif +#endif +#include +#endif + +/* Disable wchar func to clear vs warning */ +#define SECUREC_ENABLE_WCHAR_FUNC 0 +#define SECUREC_FORMAT_OUTPUT_INPUT 1 + +#ifndef SECUREC_FOR_WCHAR +#define SECUREC_FOR_WCHAR +#endif + +#include "secinput.h" + +#include "input.inl" + +SECUREC_INLINE unsigned int SecWcharHighBits(SecInt ch) +{ + /* Convert int to unsigned int clear 571 */ + return ((unsigned int)(int)ch & (~0xffU)); +} + +SECUREC_INLINE unsigned char SecWcharLowByte(SecInt ch) +{ + /* Convert int to unsigned int clear 571 */ + return (unsigned char)((unsigned int)(int)ch & 0xffU); +} + +SECUREC_INLINE int SecIsDigit(SecInt ch) +{ + if (SecWcharHighBits(ch) != 0) { + return 0; /* Same as isdigit */ + } + return isdigit((int)SecWcharLowByte(ch)); +} + +SECUREC_INLINE int SecIsXdigit(SecInt ch) +{ + if (SecWcharHighBits(ch) != 0) { + return 0; /* Same as isxdigit */ + } + return isxdigit((int)SecWcharLowByte(ch)); +} + +SECUREC_INLINE int SecIsSpace(SecInt ch) +{ + return iswspace((wint_t)(int)(ch)); +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput.h b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput.h new file mode 100644 index 0000000000000000000000000000000000000000..dc483f58c10905cb94205b1a9bd6a3dccfb3b279 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput.h @@ -0,0 +1,153 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: Define macro, enum, data struct, and declare internal used function + * prototype, which is used by output.inl, secureprintoutput_w.c and + * secureprintoutput_a.c. + * Create: 2014-02-25 + */ + +#ifndef SECUREPRINTOUTPUT_H_E950DA2C_902F_4B15_BECD_948E99090D9C +#define SECUREPRINTOUTPUT_H_E950DA2C_902F_4B15_BECD_948E99090D9C +#include "securecutil.h" + +/* Shield compilation alerts about using sprintf without format attribute to format float value. */ +#ifndef SECUREC_HANDLE_WFORMAT +#define SECUREC_HANDLE_WFORMAT 1 +#endif + +#if defined(__clang__) +#if SECUREC_HANDLE_WFORMAT && defined(__GNUC__) && ((__GNUC__ >= 5) || \ + (defined(__GNUC_MINOR__) && (__GNUC__ == 4 && __GNUC_MINOR__ >= 2))) +#define SECUREC_MASK_WFORMAT_WARNING _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wformat-nonliteral\"") +#define SECUREC_END_MASK_WFORMAT_WARNING _Pragma("GCC diagnostic pop") +#else +#define SECUREC_MASK_WFORMAT_WARNING +#define SECUREC_END_MASK_WFORMAT_WARNING +#endif +#else +#if SECUREC_HANDLE_WFORMAT && defined(__GNUC__) && ((__GNUC__ >= 5 ) || \ + (defined(__GNUC_MINOR__) && (__GNUC__ == 4 && __GNUC_MINOR__ > 7))) +#define SECUREC_MASK_WFORMAT_WARNING _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wformat-nonliteral\"") \ + _Pragma("GCC diagnostic ignored \"-Wmissing-format-attribute\"") \ + _Pragma("GCC diagnostic ignored \"-Wsuggest-attribute=format\"") +#define SECUREC_END_MASK_WFORMAT_WARNING _Pragma("GCC diagnostic pop") +#else +#define SECUREC_MASK_WFORMAT_WARNING +#define SECUREC_END_MASK_WFORMAT_WARNING +#endif +#endif + +#define SECUREC_MASK_VSPRINTF_WARNING SECUREC_MASK_WFORMAT_WARNING \ + SECUREC_MASK_MSVC_CRT_WARNING + +#define SECUREC_END_MASK_VSPRINTF_WARNING SECUREC_END_MASK_WFORMAT_WARNING \ + SECUREC_END_MASK_MSVC_CRT_WARNING + +/* + * Flag definitions. + * Using macros instead of enumerations is because some of the enumerated types under the compiler are 16bit. + */ +#define SECUREC_FLAG_SIGN 0x00001U +#define SECUREC_FLAG_SIGN_SPACE 0x00002U +#define SECUREC_FLAG_LEFT 0x00004U +#define SECUREC_FLAG_LEADZERO 0x00008U +#define SECUREC_FLAG_LONG 0x00010U +#define SECUREC_FLAG_SHORT 0x00020U +#define SECUREC_FLAG_SIGNED 0x00040U +#define SECUREC_FLAG_ALTERNATE 0x00080U +#define SECUREC_FLAG_NEGATIVE 0x00100U +#define SECUREC_FLAG_FORCE_OCTAL 0x00200U +#define SECUREC_FLAG_LONG_DOUBLE 0x00400U +#define SECUREC_FLAG_WIDECHAR 0x00800U +#define SECUREC_FLAG_LONGLONG 0x01000U +#define SECUREC_FLAG_CHAR 0x02000U +#define SECUREC_FLAG_POINTER 0x04000U +#define SECUREC_FLAG_I64 0x08000U +#define SECUREC_FLAG_PTRDIFF 0x10000U +#define SECUREC_FLAG_SIZE 0x20000U +#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT +#define SECUREC_FLAG_INTMAX 0x40000U +#endif + +/* State definitions. Identify the status of the current format */ +typedef enum { + STAT_NORMAL, + STAT_PERCENT, + STAT_FLAG, + STAT_WIDTH, + STAT_DOT, + STAT_PRECIS, + STAT_SIZE, + STAT_TYPE, + STAT_INVALID +} SecFmtState; + +#ifndef SECUREC_BUFFER_SIZE +#if SECUREC_IN_KERNEL +#define SECUREC_BUFFER_SIZE 32 +#elif defined(SECUREC_STACK_SIZE_LESS_THAN_1K) +/* + * SECUREC BUFFER SIZE Can not be less than 23 + * The length of the octal representation of 64-bit integers with zero lead + */ +#define SECUREC_BUFFER_SIZE 256 +#else +#define SECUREC_BUFFER_SIZE 512 +#endif +#endif +#if SECUREC_BUFFER_SIZE < 23 +#error SECUREC_BUFFER_SIZE Can not be less than 23 +#endif +/* Buffer size for wchar, use 4 to make the compiler aligns as 8 bytes as possible */ +#define SECUREC_WCHAR_BUFFER_SIZE 4 + +#define SECUREC_MAX_PRECISION SECUREC_BUFFER_SIZE +/* Max. # bytes in multibyte char,see MB_LEN_MAX */ +#define SECUREC_MB_LEN 16 +/* The return value of the internal function, which is returned when truncated */ +#define SECUREC_PRINTF_TRUNCATE (-2) + +#define SECUREC_VSPRINTF_PARAM_ERROR(format, strDest, destMax, maxLimit) \ + ((format) == NULL || (strDest) == NULL || (destMax) == 0 || (destMax) > (maxLimit)) + +#define SECUREC_VSPRINTF_CLEAR_DEST(strDest, destMax, maxLimit) do { \ + if ((strDest) != NULL && (destMax) > 0 && (destMax) <= (maxLimit)) { \ + *(strDest) = '\0'; \ + } \ +} SECUREC_WHILE_ZERO + +#ifdef SECUREC_COMPATIBLE_WIN_FORMAT +#define SECUREC_VSNPRINTF_PARAM_ERROR(format, strDest, destMax, count, maxLimit) \ + (((format) == NULL || (strDest) == NULL || (destMax) == 0 || (destMax) > (maxLimit)) || \ + ((count) > (SECUREC_STRING_MAX_LEN - 1) && (count) != (size_t)(-1))) + +#else +#define SECUREC_VSNPRINTF_PARAM_ERROR(format, strDest, destMax, count, maxLimit) \ + (((format) == NULL || (strDest) == NULL || (destMax) == 0 || (destMax) > (maxLimit)) || \ + ((count) > (SECUREC_STRING_MAX_LEN - 1))) +#endif + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef SECUREC_FOR_WCHAR +int SecVswprintfImpl(wchar_t *string, size_t count, const wchar_t *format, va_list argList); +#else +int SecVsnprintfImpl(char *string, size_t count, const char *format, va_list argList); +#endif +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_a.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_a.c new file mode 100644 index 0000000000000000000000000000000000000000..b2b4b6a65cfa6416c643ad3dbf5e09ead8bc095a --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_a.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: By defining corresponding macro for ANSI string and including "output.inl", + * this file generates real underlying function used by printf family API. + * Create: 2014-02-25 + */ + +#define SECUREC_FORMAT_OUTPUT_INPUT 1 + +#ifdef SECUREC_FOR_WCHAR +#undef SECUREC_FOR_WCHAR +#endif + +#include "secureprintoutput.h" +#if SECUREC_WARP_OUTPUT +#define SECUREC_FORMAT_FLAG_TABLE_SIZE 128 +SECUREC_INLINE const char *SecSkipKnownFlags(const char *format) +{ + static const unsigned char flagTable[SECUREC_FORMAT_FLAG_TABLE_SIZE] = { + /* + * Known flag is "0123456789 +-#hlLwZzjqt*I$" + */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x01, 0x00, 0x00, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + const char *fmt = format; + while (*fmt != '\0') { + char fmtChar = *fmt; + if ((unsigned char)fmtChar > 0x7f) { /* 0x7f is upper limit of format char value */ + break; + } + if (flagTable[(unsigned char)fmtChar] == 0) { + break; + } + ++fmt; + } + return fmt; +} + +SECUREC_INLINE int SecFormatContainN(const char *format) +{ + const char *fmt = format; + while (*fmt != '\0') { + ++fmt; + /* Skip normal char */ + if (*(fmt - 1) != '%') { + continue; + } + /* Meet %% */ + if (*fmt == '%') { + ++fmt; /* Point to the character after the %. Correct handling %%xx */ + continue; + } + /* Now parse %..., fmt point to the character after the % */ + fmt = SecSkipKnownFlags(fmt); + if (*fmt == 'n') { + return 1; + } + } + return 0; +} +/* + * Multi character formatted output implementation, the count include \0 character, must be greater than zero + */ +int SecVsnprintfImpl(char *string, size_t count, const char *format, va_list argList) +{ + int retVal; + if (SecFormatContainN(format) != 0) { + string[0] = '\0'; + return -1; + } + SECUREC_MASK_VSPRINTF_WARNING + retVal = vsnprintf(string, count, format, argList); + SECUREC_END_MASK_VSPRINTF_WARNING + if (retVal >= (int)count) { /* The size_t to int is ok, count max is SECUREC_STRING_MAX_LEN */ + /* The buffer was too small; we return truncation */ + string[count - 1] = '\0'; + return SECUREC_PRINTF_TRUNCATE; + } + if (retVal < 0) { + string[0] = '\0'; /* Empty the dest strDest */ + return -1; + } + return retVal; +} +#else +#if SECUREC_IN_KERNEL +#include +#endif + +#ifndef EOF +#define EOF (-1) +#endif + +#include "output.inl" + +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_w.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_w.c new file mode 100644 index 0000000000000000000000000000000000000000..672c0184cc6de509957e3bc32bbd0afcd48c7e65 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_w.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: By defining corresponding macro for UNICODE string and including "output.inl", + * this file generates real underlying function used by printf family API. + * Create: 2014-02-25 + */ + +/* If some platforms don't have wchar.h, don't include it */ +#if !(defined(SECUREC_VXWORKS_PLATFORM)) +/* If there is no macro above, it will cause compiling alarm */ +#if defined(_MSC_VER) && (_MSC_VER >= 1400) +#ifndef _CRTIMP_ALTERNATIVE +#define _CRTIMP_ALTERNATIVE /* Comment microsoft *_s function */ +#endif +#ifndef __STDC_WANT_SECURE_LIB__ +#define __STDC_WANT_SECURE_LIB__ 0 +#endif +#endif +#include +#endif + +/* Disable wchar func to clear vs warning */ +#define SECUREC_ENABLE_WCHAR_FUNC 0 +#define SECUREC_FORMAT_OUTPUT_INPUT 1 + +#ifndef SECUREC_FOR_WCHAR +#define SECUREC_FOR_WCHAR +#endif + +#include "secureprintoutput.h" + +#include "output.inl" + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/snprintf_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/snprintf_s.c new file mode 100644 index 0000000000000000000000000000000000000000..e9b94f37248f5a3d0ddd954ce7918d3d6db253be --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/snprintf_s.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: snprintf_s function + * Create: 2014-02-25 + */ + +#include "securec.h" + +#if SECUREC_ENABLE_SNPRINTF +/* + * + * The snprintf_s function is equivalent to the snprintf function + * except for the parameter destMax/count and the explicit runtime-constraints violation + * The snprintf_s function formats and stores count or fewer characters in + * strDest and appends a terminating null. Each argument (if any) is converted + * and output according to the corresponding format specification in format. + * The formatting is consistent with the printf family of functions; If copying + * occurs between strings that overlap, the behavior is undefined. + * + * + * strDest Storage location for the output. + * destMax The size of the storage location for output. Size + * in bytes for snprintf_s or size in words for snwprintf_s. + * count Maximum number of character to store. + * format Format-control string. + * ... Optional arguments. + * + * + * strDest is updated + * + * + * return the number of characters written, not including the terminating null + * return -1 if an error occurs. + * return -1 if count < destMax and the output string has been truncated + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + * + */ +int snprintf_s(char *strDest, size_t destMax, size_t count, const char *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vsnprintf_s(strDest, destMax, count, format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(snprintf_s); +#endif +#endif + +#if SECUREC_SNPRINTF_TRUNCATED +/* + * + * The snprintf_truncated_s function is equivalent to the snprintf function + * except for the parameter destMax/count and the explicit runtime-constraints violation + * The snprintf_truncated_s function formats and stores count or fewer characters in + * strDest and appends a terminating null. Each argument (if any) is converted + * and output according to the corresponding format specification in format. + * The formatting is consistent with the printf family of functions; If copying + * occurs between strings that overlap, the behavior is undefined. + * + * + * strDest Storage location for the output. + * destMax The size of the storage location for output. Size + * in bytes for snprintf_truncated_s or size in words for snwprintf_s. + * format Format-control string. + * ... Optional arguments. + * + * + * strDest is updated + * + * + * return the number of characters written, not including the terminating null + * return -1 if an error occurs. + * return destMax-1 if output string has been truncated + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + * + */ +int snprintf_truncated_s(char *strDest, size_t destMax, const char *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vsnprintf_truncated_s(strDest, destMax, format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(snprintf_truncated_s); +#endif + +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/sprintf_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/sprintf_s.c new file mode 100644 index 0000000000000000000000000000000000000000..0cf3fca9013d9ec2d6fd211bcfc6c123d31c7753 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/sprintf_s.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: sprintf_s function + * Create: 2014-02-25 + */ + +#include "securec.h" + +/* + * + * The sprintf_s function is equivalent to the sprintf function + * except for the parameter destMax and the explicit runtime-constraints violation + * The sprintf_s function formats and stores a series of characters and values + * in strDest. Each argument (if any) is converted and output according to + * the corresponding format specification in format. The format consists of + * ordinary characters and has the same form and function as the format argument + * for printf. A null character is appended after the last character written. + * If copying occurs between strings that overlap, the behavior is undefined. + * + * + * strDest Storage location for output. + * destMax Maximum number of characters to store. + * format Format-control string. + * ... Optional arguments + * + * + * strDest is updated + * + * + * return the number of bytes stored in strDest, not counting the terminating null character. + * return -1 if an error occurred. + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +int sprintf_s(char *strDest, size_t destMax, const char *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vsprintf_s(strDest, destMax, format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(sprintf_s); +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/sscanf_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/sscanf_s.c new file mode 100644 index 0000000000000000000000000000000000000000..b441329e12e08818e63804f3e14615331404bb6a --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/sscanf_s.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: sscanf_s function + * Create: 2014-02-25 + */ + +#include "securec.h" + +/* + * + * The sscanf_s function is equivalent to fscanf_s, + * except that input is obtained from a string (specified by the argument buffer) rather than from a stream + * The sscanf function reads data from buffer into the location given by each + * argument. Every argument must be a pointer to a variable with a type that + * corresponds to a type specifier in format. The format argument controls the + * interpretation of the input fields and has the same form and function as + * the format argument for the scanf function. + * If copying takes place between strings that overlap, the behavior is undefined. + * + * + * buffer Stored data. + * format Format control string, see Format Specifications. + * ... Optional arguments. + * + * + * ... The converted value stored in user assigned address + * + * + * Each of these functions returns the number of fields successfully converted + * and assigned; the return value does not include fields that were read but + * not assigned. + * A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int sscanf_s(const char *buffer, const char *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vsscanf_s(buffer, format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(sscanf_s); +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/strcat_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/strcat_s.c new file mode 100644 index 0000000000000000000000000000000000000000..f835e7bc90a6a772fdd6532cbd2b23d20032a251 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/strcat_s.c @@ -0,0 +1,101 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: strcat_s function + * Create: 2014-02-25 + */ + +#include "securecutil.h" + +/* + * Befor this function, the basic parameter checking has been done + */ +SECUREC_INLINE errno_t SecDoCat(char *strDest, size_t destMax, const char *strSrc) +{ + size_t destLen; + size_t srcLen; + size_t maxSrcLen; + SECUREC_CALC_STR_LEN(strDest, destMax, &destLen); + /* Only optimize strSrc, do not apply this function to strDest */ + maxSrcLen = destMax - destLen; + SECUREC_CALC_STR_LEN_OPT(strSrc, maxSrcLen, &srcLen); + + if (SECUREC_CAT_STRING_IS_OVERLAP(strDest, destLen, strSrc, srcLen)) { + strDest[0] = '\0'; + if (strDest + destLen <= strSrc && destLen == destMax) { + SECUREC_ERROR_INVALID_PARAMTER("strcat_s"); + return EINVAL_AND_RESET; + } + SECUREC_ERROR_BUFFER_OVERLAP("strcat_s"); + return EOVERLAP_AND_RESET; + } + if (srcLen + destLen >= destMax || strDest == strSrc) { + strDest[0] = '\0'; + if (destLen == destMax) { + SECUREC_ERROR_INVALID_PARAMTER("strcat_s"); + return EINVAL_AND_RESET; + } + SECUREC_ERROR_INVALID_RANGE("strcat_s"); + return ERANGE_AND_RESET; + } + SECUREC_MEMCPY_WARP_OPT(strDest + destLen, strSrc, srcLen + 1); /* Single character length include \0 */ + return EOK; +} + +/* + * + * The strcat_s function appends a copy of the string pointed to by strSrc (including the terminating null character) + * to the end of the string pointed to by strDest. + * The initial character of strSrc overwrites the terminating null character of strDest. + * strcat_s will return EOVERLAP_AND_RESET if the source and destination strings overlap. + * + * Note that the second parameter is the total size of the buffer, not the + * remaining size. + * + * + * strDest Null-terminated destination string buffer. + * destMax Size of the destination string buffer. + * strSrc Null-terminated source string buffer. + * + * + * strDest is updated + * + * + * EOK Success + * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN + * EINVAL_AND_RESET (strDest unterminated and all other parameters are valid) or + * (strDest != NULL and strSrc is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN) + * ERANGE destMax is 0 and destMax > SECUREC_STRING_MAX_LEN + * ERANGE_AND_RESET strDest have not enough space and all other parameters are valid and not overlap + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and all parameters are valid + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +errno_t strcat_s(char *strDest, size_t destMax, const char *strSrc) +{ + if (destMax == 0 || destMax > SECUREC_STRING_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("strcat_s"); + return ERANGE; + } + if (strDest == NULL || strSrc == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("strcat_s"); + if (strDest != NULL) { + strDest[0] = '\0'; + return EINVAL_AND_RESET; + } + return EINVAL; + } + return SecDoCat(strDest, destMax, strSrc); +} + +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(strcat_s); +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/strcpy_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/strcpy_s.c new file mode 100644 index 0000000000000000000000000000000000000000..ca1b2ddb1f445a6e271463c1ee79866387a3e1fe --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/strcpy_s.c @@ -0,0 +1,353 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: strcpy_s function + * Create: 2014-02-25 + */ +/* + * [Standardize-exceptions] Use unsafe function: Performance-sensitive + * [reason] Always used in the performance critical path, + * and sufficient input validation is performed before calling + */ + +#include "securecutil.h" + +#ifndef SECUREC_STRCPY_WITH_PERFORMANCE +#define SECUREC_STRCPY_WITH_PERFORMANCE 1 +#endif + +#define SECUREC_STRCPY_PARAM_OK(strDest, destMax, strSrc) ((destMax) > 0 && \ + (destMax) <= SECUREC_STRING_MAX_LEN && (strDest) != NULL && (strSrc) != NULL && (strDest) != (strSrc)) + +#if (!SECUREC_IN_KERNEL) && SECUREC_STRCPY_WITH_PERFORMANCE +#ifndef SECUREC_STRCOPY_THRESHOLD_SIZE +#define SECUREC_STRCOPY_THRESHOLD_SIZE 32UL +#endif +/* The purpose of converting to void is to clean up the alarm */ +#define SECUREC_SMALL_STR_COPY(strDest, strSrc, lenWithTerm) do { \ + if (SECUREC_ADDR_ALIGNED_8(strDest) && SECUREC_ADDR_ALIGNED_8(strSrc)) { \ + /* Use struct assignment */ \ + switch (lenWithTerm) { \ + case 1: \ + *(strDest) = *(strSrc); \ + break; \ + case 2: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 2); \ + break; \ + case 3: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 3); \ + break; \ + case 4: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 4); \ + break; \ + case 5: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 5); \ + break; \ + case 6: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 6); \ + break; \ + case 7: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 7); \ + break; \ + case 8: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 8); \ + break; \ + case 9: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 9); \ + break; \ + case 10: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 10); \ + break; \ + case 11: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 11); \ + break; \ + case 12: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 12); \ + break; \ + case 13: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 13); \ + break; \ + case 14: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 14); \ + break; \ + case 15: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 15); \ + break; \ + case 16: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 16); \ + break; \ + case 17: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 17); \ + break; \ + case 18: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 18); \ + break; \ + case 19: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 19); \ + break; \ + case 20: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 20); \ + break; \ + case 21: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 21); \ + break; \ + case 22: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 22); \ + break; \ + case 23: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 23); \ + break; \ + case 24: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 24); \ + break; \ + case 25: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 25); \ + break; \ + case 26: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 26); \ + break; \ + case 27: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 27); \ + break; \ + case 28: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 28); \ + break; \ + case 29: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 29); \ + break; \ + case 30: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 30); \ + break; \ + case 31: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 31); \ + break; \ + case 32: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 32); \ + break; \ + default: \ + /* Do nothing */ \ + break; \ + } /* END switch */ \ + } else { \ + char *tmpStrDest_ = (char *)(strDest); \ + const char *tmpStrSrc_ = (const char *)(strSrc); \ + switch (lenWithTerm) { \ + case 32: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 31: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 30: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 29: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 28: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 27: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 26: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 25: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 24: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 23: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 22: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 21: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 20: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 19: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 18: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 17: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 16: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 15: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 14: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 13: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 12: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 11: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 10: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 9: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 8: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 7: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 6: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 5: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 4: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 3: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 2: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 1: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + default: \ + /* Do nothing */ \ + break; \ + } \ + } \ +} SECUREC_WHILE_ZERO +#endif + +#if SECUREC_IN_KERNEL || (!SECUREC_STRCPY_WITH_PERFORMANCE) +#define SECUREC_STRCPY_OPT(dest, src, lenWithTerm) SECUREC_MEMCPY_WARP_OPT((dest), (src), (lenWithTerm)) +#else +/* + * Performance optimization. lenWithTerm include '\0' + */ +#define SECUREC_STRCPY_OPT(dest, src, lenWithTerm) do { \ + if ((lenWithTerm) > SECUREC_STRCOPY_THRESHOLD_SIZE) { \ + SECUREC_MEMCPY_WARP_OPT((dest), (src), (lenWithTerm)); \ + } else { \ + SECUREC_SMALL_STR_COPY((dest), (src), (lenWithTerm)); \ + } \ +} SECUREC_WHILE_ZERO +#endif + +/* + * Check Src Range + */ +SECUREC_INLINE errno_t CheckSrcRange(char *strDest, size_t destMax, const char *strSrc) +{ + size_t tmpDestMax = destMax; + const char *tmpSrc = strSrc; + /* Use destMax as boundary checker and destMax must be greater than zero */ + while (*tmpSrc != '\0' && tmpDestMax > 0) { + ++tmpSrc; + --tmpDestMax; + } + if (tmpDestMax == 0) { + strDest[0] = '\0'; + SECUREC_ERROR_INVALID_RANGE("strcpy_s"); + return ERANGE_AND_RESET; + } + return EOK; +} + +/* + * Handling errors + */ +errno_t strcpy_error(char *strDest, size_t destMax, const char *strSrc) +{ + if (destMax == 0 || destMax > SECUREC_STRING_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("strcpy_s"); + return ERANGE; + } + if (strDest == NULL || strSrc == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("strcpy_s"); + if (strDest != NULL) { + strDest[0] = '\0'; + return EINVAL_AND_RESET; + } + return EINVAL; + } + return CheckSrcRange(strDest, destMax, strSrc); +} + +/* + * + * The strcpy_s function copies the string pointed to strSrc + * (including the terminating null character) into the array pointed to by strDest + * The destination string must be large enough to hold the source string, + * including the terminating null character. strcpy_s will return EOVERLAP_AND_RESET + * if the source and destination strings overlap. + * + * + * strDest Location of destination string buffer + * destMax Size of the destination string buffer. + * strSrc Null-terminated source string buffer. + * + * + * strDest is updated. + * + * + * EOK Success + * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN + * EINVAL_AND_RESET strDest != NULL and strSrc is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN + * ERANGE destMax is 0 and destMax > SECUREC_STRING_MAX_LEN + * ERANGE_AND_RESET strDest have not enough space and all other parameters are valid and not overlap + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and all parameters are valid + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +errno_t strcpy_s(char *strDest, size_t destMax, const char *strSrc) +{ + if (SECUREC_STRCPY_PARAM_OK(strDest, destMax, strSrc)) { + size_t srcStrLen; + SECUREC_CALC_STR_LEN(strSrc, destMax, &srcStrLen); + ++srcStrLen; /* The length include '\0' */ + + if (srcStrLen <= destMax) { + /* Use mem overlap check include '\0' */ + if (SECUREC_MEMORY_NO_OVERLAP(strDest, strSrc, srcStrLen)) { + /* Performance optimization srcStrLen include '\0' */ + SECUREC_STRCPY_OPT(strDest, strSrc, srcStrLen); + return EOK; + } else { + strDest[0] = '\0'; + SECUREC_ERROR_BUFFER_OVERLAP("strcpy_s"); + return EOVERLAP_AND_RESET; + } + } + } + return strcpy_error(strDest, destMax, strSrc); +} + +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(strcpy_s); +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/strncat_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/strncat_s.c new file mode 100644 index 0000000000000000000000000000000000000000..6686d2994a64733f7ae92572106c26243f87070b --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/strncat_s.c @@ -0,0 +1,119 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: strncat_s function + * Create: 2014-02-25 + */ + +#include "securecutil.h" + +/* + * Befor this function, the basic parameter checking has been done + */ +SECUREC_INLINE errno_t SecDoCatLimit(char *strDest, size_t destMax, const char *strSrc, size_t count) +{ + size_t destLen; + size_t srcLen; + SECUREC_CALC_STR_LEN(strDest, destMax, &destLen); + /* + * The strSrc is no longer optimized. The reason is that when count is small, + * the efficiency of strnlen is higher than that of self realization. + */ + SECUREC_CALC_STR_LEN(strSrc, count, &srcLen); + + if (SECUREC_CAT_STRING_IS_OVERLAP(strDest, destLen, strSrc, srcLen)) { + strDest[0] = '\0'; + if (strDest + destLen <= strSrc && destLen == destMax) { + SECUREC_ERROR_INVALID_PARAMTER("strncat_s"); + return EINVAL_AND_RESET; + } + SECUREC_ERROR_BUFFER_OVERLAP("strncat_s"); + return EOVERLAP_AND_RESET; + } + if (srcLen + destLen >= destMax || strDest == strSrc) { + strDest[0] = '\0'; + if (destLen == destMax) { + SECUREC_ERROR_INVALID_PARAMTER("strncat_s"); + return EINVAL_AND_RESET; + } + SECUREC_ERROR_INVALID_RANGE("strncat_s"); + return ERANGE_AND_RESET; + } + SECUREC_MEMCPY_WARP_OPT(strDest + destLen, strSrc, srcLen); /* No terminator */ + *(strDest + destLen + srcLen) = '\0'; + return EOK; +} + +/* + * + * The strncat_s function appends not more than n successive characters + * (not including the terminating null character) + * from the array pointed to by strSrc to the end of the string pointed to by strDest + * The strncat_s function try to append the first D characters of strSrc to + * the end of strDest, where D is the lesser of count and the length of strSrc. + * If appending those D characters will fit within strDest (whose size is given + * as destMax) and still leave room for a null terminator, then those characters + * are appended, starting at the original terminating null of strDest, and a + * new terminating null is appended; otherwise, strDest[0] is set to the null + * character. + * + * + * strDest Null-terminated destination string. + * destMax Size of the destination buffer. + * strSrc Null-terminated source string. + * count Number of character to append, or truncate. + * + * + * strDest is updated + * + * + * EOK Success + * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN + * EINVAL_AND_RESET (strDest unterminated and all other parameters are valid)or + * (strDest != NULL and strSrc is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN) + * ERANGE destMax is 0 and destMax > SECUREC_STRING_MAX_LEN + * ERANGE_AND_RESET strDest have not enough space and all other parameters are valid and not overlap + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and all parameters are valid + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +errno_t strncat_s(char *strDest, size_t destMax, const char *strSrc, size_t count) +{ + if (destMax == 0 || destMax > SECUREC_STRING_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("strncat_s"); + return ERANGE; + } + + if (strDest == NULL || strSrc == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("strncat_s"); + if (strDest != NULL) { + strDest[0] = '\0'; + return EINVAL_AND_RESET; + } + return EINVAL; + } + if (count > SECUREC_STRING_MAX_LEN) { +#ifdef SECUREC_COMPATIBLE_WIN_FORMAT + if (count == (size_t)(-1)) { + /* Windows internal functions may pass in -1 when calling this function */ + return SecDoCatLimit(strDest, destMax, strSrc, destMax); + } +#endif + strDest[0] = '\0'; + SECUREC_ERROR_INVALID_RANGE("strncat_s"); + return ERANGE_AND_RESET; + } + return SecDoCatLimit(strDest, destMax, strSrc, count); +} + +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(strncat_s); +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/strncpy_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/strncpy_s.c new file mode 100644 index 0000000000000000000000000000000000000000..5f4c5b709ff9612bb8f3f36e684db3210da10532 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/strncpy_s.c @@ -0,0 +1,145 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: strncpy_s function + * Create: 2014-02-25 + */ +/* + * [Standardize-exceptions] Use unsafe function: Performance-sensitive + * [reason] Always used in the performance critical path, + * and sufficient input validation is performed before calling + */ + +#include "securecutil.h" + +#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) +#define SECUREC_STRNCPY_PARAM_OK(strDest, destMax, strSrc, count) \ + (((destMax) > 0 && (destMax) <= SECUREC_STRING_MAX_LEN && (strDest) != NULL && (strSrc) != NULL && \ + ((count) <= SECUREC_STRING_MAX_LEN || (count) == ((size_t)(-1))) && (count) > 0)) +#else +#define SECUREC_STRNCPY_PARAM_OK(strDest, destMax, strSrc, count) \ + (((destMax) > 0 && (destMax) <= SECUREC_STRING_MAX_LEN && (strDest) != NULL && (strSrc) != NULL && \ + (count) <= SECUREC_STRING_MAX_LEN && (count) > 0)) +#endif + +/* + * Check Src Count Range + */ +SECUREC_INLINE errno_t CheckSrcCountRange(char *strDest, size_t destMax, const char *strSrc, size_t count) +{ + size_t tmpDestMax = destMax; + size_t tmpCount = count; + const char *endPos = strSrc; + + /* Use destMax and count as boundary checker and destMax must be greater than zero */ + while (*(endPos) != '\0' && tmpDestMax > 0 && tmpCount > 0) { + ++endPos; + --tmpCount; + --tmpDestMax; + } + if (tmpDestMax == 0) { + strDest[0] = '\0'; + SECUREC_ERROR_INVALID_RANGE("strncpy_s"); + return ERANGE_AND_RESET; + } + return EOK; +} + +/* + * Handling errors, when dest equal src return EOK + */ +errno_t strncpy_error(char *strDest, size_t destMax, const char *strSrc, size_t count) +{ + if (destMax == 0 || destMax > SECUREC_STRING_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("strncpy_s"); + return ERANGE; + } + if (strDest == NULL || strSrc == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("strncpy_s"); + if (strDest != NULL) { + strDest[0] = '\0'; + return EINVAL_AND_RESET; + } + return EINVAL; + } + if (count > SECUREC_STRING_MAX_LEN) { + strDest[0] = '\0'; /* Clear dest string */ + SECUREC_ERROR_INVALID_RANGE("strncpy_s"); + return ERANGE_AND_RESET; + } + if (count == 0) { + strDest[0] = '\0'; + return EOK; + } + return CheckSrcCountRange(strDest, destMax, strSrc, count); +} + +/* + * + * The strncpy_s function copies not more than n successive characters (not including the terminating null character) + * from the array pointed to by strSrc to the array pointed to by strDest. + * + * + * strDest Destination string. + * destMax The size of the destination string, in characters. + * strSrc Source string. + * count Number of characters to be copied. + * + * + * strDest is updated + * + * + * EOK Success + * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN + * EINVAL_AND_RESET strDest != NULL and strSrc is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN + * ERANGE destMax is 0 and destMax > SECUREC_STRING_MAX_LEN + * ERANGE_AND_RESET strDest have not enough space and all other parameters are valid and not overlap + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and all parameters are valid + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +errno_t strncpy_s(char *strDest, size_t destMax, const char *strSrc, size_t count) +{ + if (SECUREC_STRNCPY_PARAM_OK(strDest, destMax, strSrc, count)) { + size_t minCpLen; /* Use it to store the maxi length limit */ + if (count < destMax) { + SECUREC_CALC_STR_LEN(strSrc, count, &minCpLen); /* No ending terminator */ + } else { + size_t tmpCount = destMax; +#ifdef SECUREC_COMPATIBLE_WIN_FORMAT + if (count == ((size_t)(-1))) { + tmpCount = destMax - 1; + } +#endif + SECUREC_CALC_STR_LEN(strSrc, tmpCount, &minCpLen); /* No ending terminator */ + if (minCpLen == destMax) { + strDest[0] = '\0'; + SECUREC_ERROR_INVALID_RANGE("strncpy_s"); + return ERANGE_AND_RESET; + } + } + if (SECUREC_STRING_NO_OVERLAP(strDest, strSrc, minCpLen) || strDest == strSrc) { + /* Not overlap */ + SECUREC_MEMCPY_WARP_OPT(strDest, strSrc, minCpLen); /* Copy string without terminator */ + strDest[minCpLen] = '\0'; + return EOK; + } else { + strDest[0] = '\0'; + SECUREC_ERROR_BUFFER_OVERLAP("strncpy_s"); + return EOVERLAP_AND_RESET; + } + } + return strncpy_error(strDest, destMax, strSrc, count); +} + +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(strncpy_s); +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/strtok_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/strtok_s.c new file mode 100644 index 0000000000000000000000000000000000000000..cd5dcd2cdfa05b120d79032c134f733dbf09ca49 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/strtok_s.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: strtok_s function + * Create: 2014-02-25 + */ + +#include "securecutil.h" + +SECUREC_INLINE int SecIsInDelimit(char ch, const char *strDelimit) +{ + const char *ctl = strDelimit; + while (*ctl != '\0' && *ctl != ch) { + ++ctl; + } + return (int)(*ctl != '\0'); +} + +/* + * Find beginning of token (skip over leading delimiters). + * Note that there is no token if this loop sets string to point to the terminal null. + */ +SECUREC_INLINE char *SecFindBegin(char *strToken, const char *strDelimit) +{ + char *token = strToken; + while (*token != '\0') { + if (SecIsInDelimit(*token, strDelimit) != 0) { + ++token; + continue; + } + /* Don't find any delimiter in string header, break the loop */ + break; + } + return token; +} + +/* + * Find rest of token + */ +SECUREC_INLINE char *SecFindRest(char *strToken, const char *strDelimit) +{ + /* Find the rest of the token. If it is not the end of the string, put a null there */ + char *token = strToken; + while (*token != '\0') { + if (SecIsInDelimit(*token, strDelimit) != 0) { + /* Find a delimiter, set string terminator */ + *token = '\0'; + ++token; + break; + } + ++token; + } + return token; +} + +/* + * Find the final position pointer + */ +SECUREC_INLINE char *SecUpdateToken(char *strToken, const char *strDelimit, char **context) +{ + /* Point to updated position. Record string position for next search in the context */ + *context = SecFindRest(strToken, strDelimit); + /* Determine if a token has been found. */ + if (*context == strToken) { + return NULL; + } + return strToken; +} + +/* + * + * The strtok_s function parses a string into a sequence of strToken, + * replace all characters in strToken string that match to strDelimit set with 0. + * On the first call to strtok_s the string to be parsed should be specified in strToken. + * In each subsequent call that should parse the same string, strToken should be NULL + * + * strToken String containing token or tokens. + * strDelimit Set of delimiter characters. + * context Used to store position information between calls + * to strtok_s + * + * context is updated + * + * On the first call returns the address of the first non \0 character, otherwise NULL is returned. + * In subsequent calls, the strtoken is set to NULL, and the context set is the same as the previous call, + * return NULL if the *context string length is equal 0, otherwise return *context. + */ +char *strtok_s(char *strToken, const char *strDelimit, char **context) +{ + char *orgToken = strToken; + /* Validate delimiter and string context */ + if (context == NULL || strDelimit == NULL) { + return NULL; + } + /* Valid input string and string pointer from where to search */ + if (orgToken == NULL && *context == NULL) { + return NULL; + } + /* If string is null, continue searching from previous string position stored in context */ + if (orgToken == NULL) { + orgToken = *context; + } + orgToken = SecFindBegin(orgToken, strDelimit); + return SecUpdateToken(orgToken, strDelimit, context); +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(strtok_s); +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/swprintf_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/swprintf_s.c new file mode 100644 index 0000000000000000000000000000000000000000..09d77a2fc0e6b473535028749673c04727650a90 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/swprintf_s.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: swprintf_s function + * Create: 2014-02-25 + */ + +#include "securec.h" + +/* + * + * The swprintf_s function is the wide-character equivalent of the sprintf_s function + * + * + * strDest Storage location for the output. + * destMax Maximum number of characters to store. + * format Format-control string. + * ... Optional arguments + * + * + * strDest is updated + * + * + * return the number of wide characters stored in strDest, not counting the terminating null wide character. + * return -1 if an error occurred. + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +int swprintf_s(wchar_t *strDest, size_t destMax, const wchar_t *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vswprintf_s(strDest, destMax, format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/swscanf_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/swscanf_s.c new file mode 100644 index 0000000000000000000000000000000000000000..e5b8bbfc7f1024d817ab6f1b52df5500788f2dd1 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/swscanf_s.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: swscanf_s function + * Create: 2014-02-25 + */ + +#include "securec.h" + +/* + * + * The swscanf_s function is the wide-character equivalent of the sscanf_s function + * The swscanf_s function reads data from buffer into the location given by + * each argument. Every argument must be a pointer to a variable with a type + * that corresponds to a type specifier in format. The format argument controls + * the interpretation of the input fields and has the same form and function + * as the format argument for the scanf function. If copying takes place between + * strings that overlap, the behavior is undefined. + * + * + * buffer Stored data. + * format Format control string, see Format Specifications. + * ... Optional arguments. + * + * + * ... the converted value stored in user assigned address + * + * + * Each of these functions returns the number of fields successfully converted + * and assigned; The return value does not include fields that were read but not + * assigned. + * A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int swscanf_s(const wchar_t *buffer, const wchar_t *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vswscanf_s(buffer, format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vfscanf_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vfscanf_s.c new file mode 100644 index 0000000000000000000000000000000000000000..214ee6a21fbb8e84e9e6ecfb895e7facf10f9b49 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vfscanf_s.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: vfscanf_s function + * Create: 2014-02-25 + */ + +#include "secinput.h" + +/* + * + * The vfscanf_s function is equivalent to fscanf_s, with the variable argument list replaced by argList + * The vfscanf_s function reads data from the current position of stream into + * the locations given by argument (if any). Each argument must be a pointer + * to a variable of a type that corresponds to a type specifier in format. + * format controls the interpretation of the input fields and has the same + * form and function as the format argument for scanf. + * + * + * stream Pointer to FILE structure. + * format Format control string, see Format Specifications. + * argList pointer to list of arguments + * + * + * argList the converted value stored in user assigned address + * + * + * Each of these functions returns the number of fields successfully converted + * and assigned; the return value does not include fields that were read but + * not assigned. A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int vfscanf_s(FILE *stream, const char *format, va_list argList) +{ + int retVal; /* If initialization causes e838 */ + SecFileStream fStr; + + if (stream == NULL || format == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("vfscanf_s"); + return SECUREC_SCANF_EINVAL; + } + if (stream == SECUREC_STREAM_STDIN) { + return vscanf_s(format, argList); + } + + SECUREC_LOCK_FILE(stream); + SECUREC_FILE_STREAM_FROM_FILE(&fStr, stream); + retVal = SecInputS(&fStr, format, argList); + SECUREC_UNLOCK_FILE(stream); + if (retVal < 0) { + SECUREC_ERROR_INVALID_PARAMTER("vfscanf_s"); + return SECUREC_SCANF_EINVAL; + } + + return retVal; +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vfwscanf_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vfwscanf_s.c new file mode 100644 index 0000000000000000000000000000000000000000..1ab9c3cb5a0ed3cf1a3d4f03f5795dddd34c4422 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vfwscanf_s.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: vfwscanf_s function + * Create: 2014-02-25 + */ + +#ifndef SECUREC_FOR_WCHAR +#define SECUREC_FOR_WCHAR +#endif + +#include "secinput.h" + +/* + * + * The vfwscanf_s function is the wide-character equivalent of the vfscanf_s function + * The vfwscanf_s function reads data from the current position of stream into + * the locations given by argument (if any). Each argument must be a pointer + * to a variable of a type that corresponds to a type specifier in format. + * format controls the interpretation of the input fields and has the same form + * and function as the format argument for scanf. + * + * + * stream Pointer to FILE structure. + * format Format control string, see Format Specifications. + * argList pointer to list of arguments + * + * + * argList the converted value stored in user assigned address + * + * + * Each of these functions returns the number of fields successfully converted + * and assigned; the return value does not include fields that were read but + * not assigned. A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int vfwscanf_s(FILE *stream, const wchar_t *format, va_list argList) +{ + int retVal; /* If initialization causes e838 */ + SecFileStream fStr; + + if (stream == NULL || format == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("vfwscanf_s"); + return SECUREC_SCANF_EINVAL; + } + if (stream == SECUREC_STREAM_STDIN) { + return vwscanf_s(format, argList); + } + + SECUREC_LOCK_FILE(stream); + SECUREC_FILE_STREAM_FROM_FILE(&fStr, stream); + retVal = SecInputSW(&fStr, format, argList); + SECUREC_UNLOCK_FILE(stream); + if (retVal < 0) { + SECUREC_ERROR_INVALID_PARAMTER("vfwscanf_s"); + return SECUREC_SCANF_EINVAL; + } + return retVal; +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vscanf_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vscanf_s.c new file mode 100644 index 0000000000000000000000000000000000000000..61480a69722f24fc98784902cfa0eec1b3aa51e1 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vscanf_s.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: vscanf_s function + * Create: 2014-02-25 + */ + +#include "secinput.h" + +/* + * + * The vscanf_s function is equivalent to scanf_s, with the variable argument list replaced by argList, + * The vscanf_s function reads data from the standard input stream stdin and + * writes the data into the location that's given by argument. Each argument + * must be a pointer to a variable of a type that corresponds to a type specifier + * in format. If copying occurs between strings that overlap, the behavior is + * undefined. + * + * + * format Format control string. + * argList pointer to list of arguments + * + * + * argList the converted value stored in user assigned address + * + * + * Returns the number of fields successfully converted and assigned; + * the return value does not include fields that were read but not assigned. + * A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int vscanf_s(const char *format, va_list argList) +{ + int retVal; /* If initialization causes e838 */ + SecFileStream fStr; + SECUREC_FILE_STREAM_FROM_STDIN(&fStr); + /* + * The "va_list" has different definition on different platform, so we can't use argList == NULL + * To determine it's invalid. If you has fixed platform, you can check some fields to validate it, + * such as "argList == NULL" or argList.xxx != NULL or *(size_t *)&argList != 0. + */ + if (format == NULL || fStr.pf == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("vscanf_s"); + return SECUREC_SCANF_EINVAL; + } + + SECUREC_LOCK_STDIN(0, fStr.pf); + retVal = SecInputS(&fStr, format, argList); + SECUREC_UNLOCK_STDIN(0, fStr.pf); + if (retVal < 0) { + SECUREC_ERROR_INVALID_PARAMTER("vscanf_s"); + return SECUREC_SCANF_EINVAL; + } + return retVal; +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vsnprintf_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vsnprintf_s.c new file mode 100644 index 0000000000000000000000000000000000000000..35caaa2206a3d349502cdc2dbbd59f654f35c691 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vsnprintf_s.c @@ -0,0 +1,138 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: vsnprintf_s function + * Create: 2014-02-25 + */ + +#include "secureprintoutput.h" + +#if SECUREC_ENABLE_VSNPRINTF +/* + * + * The vsnprintf_s function is equivalent to the vsnprintf function + * except for the parameter destMax/count and the explicit runtime-constraints violation + * The vsnprintf_s function takes a pointer to an argument list, then formats + * and writes up to count characters of the given data to the memory pointed + * to by strDest and appends a terminating null. + * + * + * strDest Storage location for the output. + * destMax The size of the strDest for output. + * count Maximum number of character to write(not including + * the terminating NULL) + * format Format-control string. + * argList pointer to list of arguments. + * + * + * strDest is updated + * + * + * return the number of characters written, not including the terminating null + * return -1 if an error occurs. + * return -1 if count < destMax and the output string has been truncated + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +int vsnprintf_s(char *strDest, size_t destMax, size_t count, const char *format, va_list argList) +{ + int retVal; + + if (SECUREC_VSNPRINTF_PARAM_ERROR(format, strDest, destMax, count, SECUREC_STRING_MAX_LEN)) { + SECUREC_VSPRINTF_CLEAR_DEST(strDest, destMax, SECUREC_STRING_MAX_LEN); + SECUREC_ERROR_INVALID_PARAMTER("vsnprintf_s"); + return -1; + } + + if (destMax > count) { + retVal = SecVsnprintfImpl(strDest, count + 1, format, argList); + if (retVal == SECUREC_PRINTF_TRUNCATE) { /* To keep dest buffer not destroyed 2014.2.18 */ + /* The string has been truncated, return -1 */ + return -1; /* To skip error handler, return strlen(strDest) or -1 */ + } + } else { + retVal = SecVsnprintfImpl(strDest, destMax, format, argList); +#ifdef SECUREC_COMPATIBLE_WIN_FORMAT + if (retVal == SECUREC_PRINTF_TRUNCATE && count == (size_t)(-1)) { + return -1; + } +#endif + } + + if (retVal < 0) { + strDest[0] = '\0'; /* Empty the dest strDest */ + if (retVal == SECUREC_PRINTF_TRUNCATE) { + /* Buffer too small */ + SECUREC_ERROR_INVALID_RANGE("vsnprintf_s"); + } + SECUREC_ERROR_INVALID_PARAMTER("vsnprintf_s"); + return -1; + } + + return retVal; +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(vsnprintf_s); +#endif +#endif + +#if SECUREC_SNPRINTF_TRUNCATED +/* + * + * The vsnprintf_truncated_s function is equivalent to the vsnprintf function + * except for the parameter destMax/count and the explicit runtime-constraints violation + * The vsnprintf_truncated_s function takes a pointer to an argument list, then formats + * and writes up to count characters of the given data to the memory pointed + * to by strDest and appends a terminating null. + * + * + * strDest Storage location for the output. + * destMax The size of the strDest for output. + * the terminating NULL) + * format Format-control string. + * argList pointer to list of arguments. + * + * + * strDest is updated + * + * + * return the number of characters written, not including the terminating null + * return -1 if an error occurs. + * return destMax-1 if output string has been truncated + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +int vsnprintf_truncated_s(char *strDest, size_t destMax, const char *format, va_list argList) +{ + int retVal; + + if (SECUREC_VSPRINTF_PARAM_ERROR(format, strDest, destMax, SECUREC_STRING_MAX_LEN)) { + SECUREC_VSPRINTF_CLEAR_DEST(strDest, destMax, SECUREC_STRING_MAX_LEN); + SECUREC_ERROR_INVALID_PARAMTER("vsnprintf_truncated_s"); + return -1; + } + + retVal = SecVsnprintfImpl(strDest, destMax, format, argList); + if (retVal < 0) { + if (retVal == SECUREC_PRINTF_TRUNCATE) { + return (int)(destMax - 1); /* To skip error handler, return strlen(strDest) */ + } + strDest[0] = '\0'; /* Empty the dest strDest */ + SECUREC_ERROR_INVALID_PARAMTER("vsnprintf_truncated_s"); + return -1; + } + + return retVal; +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(vsnprintf_truncated_s); +#endif +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vsprintf_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vsprintf_s.c new file mode 100644 index 0000000000000000000000000000000000000000..f50fa4a9802fe335519faebcfea5520423e2b3d2 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vsprintf_s.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: vsprintf_s function + * Create: 2014-02-25 + */ + +#include "secureprintoutput.h" + +/* + * + * The vsprintf_s function is equivalent to the vsprintf function + * except for the parameter destMax and the explicit runtime-constraints violation + * The vsprintf_s function takes a pointer to an argument list, and then formats + * and writes the given data to the memory pointed to by strDest. + * The function differ from the non-secure versions only in that the secure + * versions support positional parameters. + * + * + * strDest Storage location for the output. + * destMax Size of strDest + * format Format specification. + * argList pointer to list of arguments + * + * + * strDest is updated + * + * + * return the number of characters written, not including the terminating null character, + * return -1 if an error occurs. + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +int vsprintf_s(char *strDest, size_t destMax, const char *format, va_list argList) +{ + int retVal; /* If initialization causes e838 */ + + if (SECUREC_VSPRINTF_PARAM_ERROR(format, strDest, destMax, SECUREC_STRING_MAX_LEN)) { + SECUREC_VSPRINTF_CLEAR_DEST(strDest, destMax, SECUREC_STRING_MAX_LEN); + SECUREC_ERROR_INVALID_PARAMTER("vsprintf_s"); + return -1; + } + + retVal = SecVsnprintfImpl(strDest, destMax, format, argList); + if (retVal < 0) { + strDest[0] = '\0'; + if (retVal == SECUREC_PRINTF_TRUNCATE) { + /* Buffer is too small */ + SECUREC_ERROR_INVALID_RANGE("vsprintf_s"); + } + SECUREC_ERROR_INVALID_PARAMTER("vsprintf_s"); + return -1; + } + + return retVal; +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(vsprintf_s); +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vsscanf_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vsscanf_s.c new file mode 100644 index 0000000000000000000000000000000000000000..a19abe2b93da0350fda1c595e5f9f2184b24056a --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vsscanf_s.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: vsscanf_s function + * Create: 2014-02-25 + */ + +#include "secinput.h" +#if defined(SECUREC_VXWORKS_PLATFORM) && !SECUREC_IN_KERNEL && \ + (!defined(SECUREC_SYSAPI4VXWORKS) && !defined(SECUREC_CTYPE_MACRO_ADAPT)) +#include +#endif + +/* + * + * vsscanf_s + * + * + * + * The vsscanf_s function is equivalent to sscanf_s, with the variable argument list replaced by argList + * The vsscanf_s function reads data from buffer into the location given by + * each argument. Every argument must be a pointer to a variable with a type + * that corresponds to a type specifier in format. The format argument controls + * the interpretation of the input fields and has the same form and function + * as the format argument for the scanf function. + * If copying takes place between strings that overlap, the behavior is undefined. + * + * + * buffer Stored data + * format Format control string, see Format Specifications. + * argList pointer to list of arguments + * + * + * argList the converted value stored in user assigned address + * + * + * Each of these functions returns the number of fields successfully converted + * and assigned; the return value does not include fields that were read but + * not assigned. A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int vsscanf_s(const char *buffer, const char *format, va_list argList) +{ + size_t count; /* If initialization causes e838 */ + int retVal; + SecFileStream fStr; + + /* Validation section */ + if (buffer == NULL || format == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("vsscanf_s"); + return SECUREC_SCANF_EINVAL; + } + count = strlen(buffer); + if (count == 0 || count > SECUREC_STRING_MAX_LEN) { + SecClearDestBuf(buffer, format, argList); + SECUREC_ERROR_INVALID_PARAMTER("vsscanf_s"); + return SECUREC_SCANF_EINVAL; + } +#if defined(SECUREC_VXWORKS_PLATFORM) && !SECUREC_IN_KERNEL + /* + * On vxworks platform when buffer is white string, will set first %s argument to zero.Like following usage: + * " \v\f\t\r\n", "%s", str, strSize + * Do not check all character, just first and last character then consider it is white string + */ + if (isspace((int)(unsigned char)buffer[0]) != 0 && isspace((int)(unsigned char)buffer[count - 1]) != 0) { + SecClearDestBuf(buffer, format, argList); + } +#endif + SECUREC_FILE_STREAM_FROM_STRING(&fStr, buffer, count); + retVal = SecInputS(&fStr, format, argList); + if (retVal < 0) { + SECUREC_ERROR_INVALID_PARAMTER("vsscanf_s"); + return SECUREC_SCANF_EINVAL; + } + return retVal; +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(vsscanf_s); +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vswprintf_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vswprintf_s.c new file mode 100644 index 0000000000000000000000000000000000000000..29715fc62e88448ed341c19091924e72a54ec213 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vswprintf_s.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: vswprintf_s function + * Create: 2014-02-25 + */ + +#ifndef SECUREC_FOR_WCHAR +#define SECUREC_FOR_WCHAR +#endif + +#include "secureprintoutput.h" + +/* + * + * The vswprintf_s function is the wide-character equivalent of the vsprintf_s function + * + * + * strDest Storage location for the output. + * destMax Maximum number of characters to store + * format Format specification. + * argList pointer to list of arguments + * + * + * strDest is updated + * + * + * return the number of wide characters stored in strDest, not counting the terminating null wide character. + * return -1 if an error occurred. + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +int vswprintf_s(wchar_t *strDest, size_t destMax, const wchar_t *format, va_list argList) +{ + int retVal; /* If initialization causes e838 */ + if (SECUREC_VSPRINTF_PARAM_ERROR(format, strDest, destMax, SECUREC_WCHAR_STRING_MAX_LEN)) { + SECUREC_VSPRINTF_CLEAR_DEST(strDest, destMax, SECUREC_WCHAR_STRING_MAX_LEN); + SECUREC_ERROR_INVALID_PARAMTER("vswprintf_s"); + return -1; + } + + retVal = SecVswprintfImpl(strDest, destMax, format, argList); + if (retVal < 0) { + strDest[0] = L'\0'; + if (retVal == SECUREC_PRINTF_TRUNCATE) { + /* Buffer too small */ + SECUREC_ERROR_INVALID_RANGE("vswprintf_s"); + } + SECUREC_ERROR_INVALID_PARAMTER("vswprintf_s"); + return -1; + } + + return retVal; +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vswscanf_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vswscanf_s.c new file mode 100644 index 0000000000000000000000000000000000000000..bab53a3e16298b90fff38d59393a1c0b3ff37083 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vswscanf_s.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: vswscanf_s function + * Create: 2014-02-25 + */ + +#ifndef SECUREC_FOR_WCHAR +#define SECUREC_FOR_WCHAR +#endif + +#include "secinput.h" + +SECUREC_INLINE size_t SecWcslen(const wchar_t *s) +{ + const wchar_t *end = s; + while (*end != L'\0') { + ++end; + } + return ((size_t)((end - s))); +} + +/* + * + * The vswscanf_s function is the wide-character equivalent of the vsscanf_s function + * The vsscanf_s function reads data from buffer into the location given by + * each argument. Every argument must be a pointer to a variable with a type + * that corresponds to a type specifier in format. + * The format argument controls the interpretation of the input fields and + * has the same form and function as the format argument for the scanf function. + * If copying takes place between strings that overlap, the behavior is undefined. + * + * + * buffer Stored data + * format Format control string, see Format Specifications. + * argList pointer to list of arguments + * + * + * argList the converted value stored in user assigned address + * + * + * Each of these functions returns the number of fields successfully converted + * and assigned; the return value does not include fields that were read but + * not assigned. A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int vswscanf_s(const wchar_t *buffer, const wchar_t *format, va_list argList) +{ + size_t count; /* If initialization causes e838 */ + SecFileStream fStr; + int retVal; + + /* Validation section */ + if (buffer == NULL || format == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("vswscanf_s"); + return SECUREC_SCANF_EINVAL; + } + count = SecWcslen(buffer); + if (count == 0 || count > SECUREC_WCHAR_STRING_MAX_LEN) { + SecClearDestBufW(buffer, format, argList); + SECUREC_ERROR_INVALID_PARAMTER("vswscanf_s"); + return SECUREC_SCANF_EINVAL; + } + SECUREC_FILE_STREAM_FROM_STRING(&fStr, (const char *)buffer, count * sizeof(wchar_t)); + retVal = SecInputSW(&fStr, format, argList); + if (retVal < 0) { + SECUREC_ERROR_INVALID_PARAMTER("vswscanf_s"); + return SECUREC_SCANF_EINVAL; + } + return retVal; +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vwscanf_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vwscanf_s.c new file mode 100644 index 0000000000000000000000000000000000000000..b39f9bc74fb2136bd7468f3cf7e698542f85086d --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/vwscanf_s.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: vwscanf_s function + * Create: 2014-02-25 + */ + +#ifndef SECUREC_FOR_WCHAR +#define SECUREC_FOR_WCHAR +#endif + +#include "secinput.h" + +/* + * + * The vwscanf_s function is the wide-character equivalent of the vscanf_s function + * The vwscanf_s function is the wide-character version of vscanf_s. The + * function reads data from the standard input stream stdin and writes the + * data into the location that's given by argument. Each argument must be a + * pointer to a variable of a type that corresponds to a type specifier in + * format. If copying occurs between strings that overlap, the behavior is + * undefined. + * + * + * format Format control string. + * argList pointer to list of arguments + * + * + * argList the converted value stored in user assigned address + * + * + * Returns the number of fields successfully converted and assigned; + * the return value does not include fields that were read but not assigned. + * A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int vwscanf_s(const wchar_t *format, va_list argList) +{ + int retVal; /* If initialization causes e838 */ + SecFileStream fStr; + SECUREC_FILE_STREAM_FROM_STDIN(&fStr); + if (format == NULL || fStr.pf == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("vwscanf_s"); + return SECUREC_SCANF_EINVAL; + } + + SECUREC_LOCK_STDIN(0, fStr.pf); + retVal = SecInputSW(&fStr, format, argList); + SECUREC_UNLOCK_STDIN(0, fStr.pf); + if (retVal < 0) { + SECUREC_ERROR_INVALID_PARAMTER("vwscanf_s"); + return SECUREC_SCANF_EINVAL; + } + + return retVal; +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wcscat_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wcscat_s.c new file mode 100644 index 0000000000000000000000000000000000000000..fa7d847c2fa5d723c5164728d09f5d0ade939c20 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wcscat_s.c @@ -0,0 +1,107 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: wcscat_s function + * Create: 2014-02-25 + */ + +#include "securecutil.h" + +/* + * Befor this function, the basic parameter checking has been done + */ +SECUREC_INLINE errno_t SecDoCatW(wchar_t *strDest, size_t destMax, const wchar_t *strSrc) +{ + size_t destLen; + size_t srcLen; + size_t maxCount; /* Store the maximum available count */ + + /* To calculate the length of a wide character, the parameter must be a wide character */ + SECUREC_CALC_WSTR_LEN(strDest, destMax, &destLen); + maxCount = destMax - destLen; + SECUREC_CALC_WSTR_LEN(strSrc, maxCount, &srcLen); + + if (SECUREC_CAT_STRING_IS_OVERLAP(strDest, destLen, strSrc, srcLen)) { + strDest[0] = L'\0'; + if (strDest + destLen <= strSrc && destLen == destMax) { + SECUREC_ERROR_INVALID_PARAMTER("wcscat_s"); + return EINVAL_AND_RESET; + } + SECUREC_ERROR_BUFFER_OVERLAP("wcscat_s"); + return EOVERLAP_AND_RESET; + } + if (srcLen + destLen >= destMax || strDest == strSrc) { + strDest[0] = L'\0'; + if (destLen == destMax) { + SECUREC_ERROR_INVALID_PARAMTER("wcscat_s"); + return EINVAL_AND_RESET; + } + SECUREC_ERROR_INVALID_RANGE("wcscat_s"); + return ERANGE_AND_RESET; + } + /* Copy single character length include \0 */ + SECUREC_MEMCPY_WARP_OPT(strDest + destLen, strSrc, (srcLen + 1) * sizeof(wchar_t)); + return EOK; +} + +/* + * + * The wcscat_s function appends a copy of the wide string pointed to by strSrc +* (including the terminating null wide character) + * to the end of the wide string pointed to by strDest. + * The arguments and return value of wcscat_s are wide-character strings. + * + * The wcscat_s function appends strSrc to strDest and terminates the resulting + * string with a null character. The initial character of strSrc overwrites the + * terminating null character of strDest. wcscat_s will return EOVERLAP_AND_RESET if the + * source and destination strings overlap. + * + * Note that the second parameter is the total size of the buffer, not the + * remaining size. + * + * + * strDest Null-terminated destination string buffer. + * destMax Size of the destination string buffer. + * strSrc Null-terminated source string buffer. + * + * + * strDest is updated + * + * + * EOK Success + * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_WCHAR_STRING_MAX_LEN + * EINVAL_AND_RESET (strDest unterminated and all other parameters are valid) or + * (strDest != NULL and strSrc is NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_STRING_MAX_LEN) + * ERANGE destMax > SECUREC_WCHAR_STRING_MAX_LEN or destMax is 0 + * ERANGE_AND_RESET strDest have not enough space and all other parameters are valid and not overlap + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and all parameters are valid + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +errno_t wcscat_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc) +{ + if (destMax == 0 || destMax > SECUREC_WCHAR_STRING_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("wcscat_s"); + return ERANGE; + } + + if (strDest == NULL || strSrc == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("wcscat_s"); + if (strDest != NULL) { + strDest[0] = L'\0'; + return EINVAL_AND_RESET; + } + return EINVAL; + } + + return SecDoCatW(strDest, destMax, strSrc); +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wcscpy_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wcscpy_s.c new file mode 100644 index 0000000000000000000000000000000000000000..8c4a4af8b7f6347a7148ac5cdefc64c231511a2c --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wcscpy_s.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: wcscpy_s function + * Create: 2014-02-25 + */ + +#include "securecutil.h" + +SECUREC_INLINE errno_t SecDoCpyW(wchar_t *strDest, size_t destMax, const wchar_t *strSrc) +{ + size_t srcStrLen; + SECUREC_CALC_WSTR_LEN(strSrc, destMax, &srcStrLen); + + if (srcStrLen == destMax) { + strDest[0] = L'\0'; + SECUREC_ERROR_INVALID_RANGE("wcscpy_s"); + return ERANGE_AND_RESET; + } + if (strDest == strSrc) { + return EOK; + } + + if (SECUREC_STRING_NO_OVERLAP(strDest, strSrc, srcStrLen)) { + /* Performance optimization, srcStrLen is single character length include '\0' */ + SECUREC_MEMCPY_WARP_OPT(strDest, strSrc, (srcStrLen + 1) * sizeof(wchar_t)); + return EOK; + } else { + strDest[0] = L'\0'; + SECUREC_ERROR_BUFFER_OVERLAP("wcscpy_s"); + return EOVERLAP_AND_RESET; + } +} + +/* + * + * The wcscpy_s function copies the wide string pointed to by strSrc + * (including the terminating null wide character) into the array pointed to by strDest + + * + * strDest Destination string buffer + * destMax Size of the destination string buffer. + * strSrc Null-terminated source string buffer. + * + * + * strDest is updated. + * + * + * EOK Success + * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_WCHAR_STRING_MAX_LEN + * EINVAL_AND_RESET strDest != NULL and strSrc is NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_STRING_MAX_LEN + * ERANGE destMax > SECUREC_WCHAR_STRING_MAX_LEN or destMax is 0 + * ERANGE_AND_RESET destMax <= length of strSrc and strDest != strSrc + * and strDest != NULL and strSrc != NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_STRING_MAX_LEN and not overlap + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and destMax != 0 + * and destMax <= SECUREC_WCHAR_STRING_MAX_LEN + * and strDest != NULL and strSrc !=NULL and strDest != strSrc + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +errno_t wcscpy_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc) +{ + if (destMax == 0 || destMax > SECUREC_WCHAR_STRING_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("wcscpy_s"); + return ERANGE; + } + if (strDest == NULL || strSrc == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("wcscpy_s"); + if (strDest != NULL) { + strDest[0] = L'\0'; + return EINVAL_AND_RESET; + } + return EINVAL; + } + return SecDoCpyW(strDest, destMax, strSrc); +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncat_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncat_s.c new file mode 100644 index 0000000000000000000000000000000000000000..33e53a32496fdc2a3a8b6650e473ae14b27cf176 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncat_s.c @@ -0,0 +1,113 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: wcsncat_s function + * Create: 2014-02-25 + */ + +#include "securecutil.h" + +/* + * Befor this function, the basic parameter checking has been done + */ +SECUREC_INLINE errno_t SecDoCatLimitW(wchar_t *strDest, size_t destMax, const wchar_t *strSrc, size_t count) +{ + /* To calculate the length of a wide character, the parameter must be a wide character */ + size_t destLen; + size_t srcLen; + SECUREC_CALC_WSTR_LEN(strDest, destMax, &destLen); + SECUREC_CALC_WSTR_LEN(strSrc, count, &srcLen); + + if (SECUREC_CAT_STRING_IS_OVERLAP(strDest, destLen, strSrc, srcLen)) { + strDest[0] = L'\0'; + if (strDest + destLen <= strSrc && destLen == destMax) { + SECUREC_ERROR_INVALID_PARAMTER("wcsncat_s"); + return EINVAL_AND_RESET; + } + SECUREC_ERROR_BUFFER_OVERLAP("wcsncat_s"); + return EOVERLAP_AND_RESET; + } + if (srcLen + destLen >= destMax || strDest == strSrc) { + strDest[0] = L'\0'; + if (destLen == destMax) { + SECUREC_ERROR_INVALID_PARAMTER("wcsncat_s"); + return EINVAL_AND_RESET; + } + SECUREC_ERROR_INVALID_RANGE("wcsncat_s"); + return ERANGE_AND_RESET; + } + SECUREC_MEMCPY_WARP_OPT(strDest + destLen, strSrc, srcLen * sizeof(wchar_t)); /* no terminator */ + *(strDest + destLen + srcLen) = L'\0'; + return EOK; +} + +/* + * + * The wcsncat_s function appends not more than n successive wide characters + * (not including the terminating null wide character) + * from the array pointed to by strSrc to the end of the wide string pointed to by strDest. + * + * The wcsncat_s function try to append the first D characters of strSrc to + * the end of strDest, where D is the lesser of count and the length of strSrc. + * If appending those D characters will fit within strDest (whose size is + * given as destMax) and still leave room for a null terminator, then those + * characters are appended, starting at the original terminating null of + * strDest, and a new terminating null is appended; otherwise, strDest[0] is + * set to the null character. + * + * + * strDest Null-terminated destination string. + * destMax Size of the destination buffer. + * strSrc Null-terminated source string. + * count Number of character to append, or truncate. + * + * + * strDest is updated + * + * + * EOK Success + * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_WCHAR_STRING_MAX_LEN + * EINVAL_AND_RESET (strDest unterminated and all other parameters are valid) or + * (strDest != NULL and strSrc is NULL and destMax != 0 and + * destMax <= SECUREC_WCHAR_STRING_MAX_LEN) + * ERANGE destMax > SECUREC_WCHAR_STRING_MAX_LEN or destMax is 0 + * ERANGE_AND_RESET strDest have not enough space and all other parameters are valid and not overlap + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and all parameters are valid + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +errno_t wcsncat_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc, size_t count) +{ + if (destMax == 0 || destMax > SECUREC_WCHAR_STRING_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("wcsncat_s"); + return ERANGE; + } + if (strDest == NULL || strSrc == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("wcsncat_s"); + if (strDest != NULL) { + strDest[0] = L'\0'; + return EINVAL_AND_RESET; + } + return EINVAL; + } + if (count > SECUREC_WCHAR_STRING_MAX_LEN) { +#ifdef SECUREC_COMPATIBLE_WIN_FORMAT + if (count == ((size_t)(-1))) { + /* Windows internal functions may pass in -1 when calling this function */ + return SecDoCatLimitW(strDest, destMax, strSrc, destMax); + } +#endif + strDest[0] = L'\0'; + SECUREC_ERROR_INVALID_RANGE("wcsncat_s"); + return ERANGE_AND_RESET; + } + return SecDoCatLimitW(strDest, destMax, strSrc, count); +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncpy_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncpy_s.c new file mode 100644 index 0000000000000000000000000000000000000000..463f90e167809545e0ea63d20dfccdfe353a3c07 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncpy_s.c @@ -0,0 +1,107 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: wcsncpy_s function + * Create: 2014-02-25 + */ + +#include "securecutil.h" + +SECUREC_INLINE errno_t SecDoCpyLimitW(wchar_t *strDest, size_t destMax, const wchar_t *strSrc, size_t count) +{ + size_t srcStrLen; + if (count < destMax) { + SECUREC_CALC_WSTR_LEN(strSrc, count, &srcStrLen); + } else { + SECUREC_CALC_WSTR_LEN(strSrc, destMax, &srcStrLen); + } + if (srcStrLen == destMax) { + strDest[0] = L'\0'; + SECUREC_ERROR_INVALID_RANGE("wcsncpy_s"); + return ERANGE_AND_RESET; + } + if (strDest == strSrc) { + return EOK; + } + if (SECUREC_STRING_NO_OVERLAP(strDest, strSrc, srcStrLen)) { + /* Performance optimization srcStrLen not include '\0' */ + SECUREC_MEMCPY_WARP_OPT(strDest, strSrc, srcStrLen * sizeof(wchar_t)); + *(strDest + srcStrLen) = L'\0'; + return EOK; + } else { + strDest[0] = L'\0'; + SECUREC_ERROR_BUFFER_OVERLAP("wcsncpy_s"); + return EOVERLAP_AND_RESET; + } +} + +/* + * + * The wcsncpy_s function copies not more than n successive wide characters + * (not including the terminating null wide character) + * from the array pointed to by strSrc to the array pointed to by strDest + * + * + * strDest Destination string. + * destMax The size of the destination string, in characters. + * strSrc Source string. + * count Number of characters to be copied. + * + * + * strDest is updated + * + * + * EOK Success + * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_WCHAR_STRING_MAX_LEN + * EINVAL_AND_RESET strDest != NULL and strSrc is NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_STRING_MAX_LEN + * ERANGE destMax > SECUREC_WCHAR_STRING_MAX_LEN or destMax is 0 + * ERANGE_AND_RESET count > SECUREC_WCHAR_STRING_MAX_LEN or + * (destMax <= length of strSrc and destMax <= count and strDest != strSrc + * and strDest != NULL and strSrc != NULL and destMax != 0 and + * destMax <= SECUREC_WCHAR_STRING_MAX_LEN and not overlap) + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and all parameters are valid + * + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +errno_t wcsncpy_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc, size_t count) +{ + if (destMax == 0 || destMax > SECUREC_WCHAR_STRING_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("wcsncpy_s"); + return ERANGE; + } + if (strDest == NULL || strSrc == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("wcsncpy_s"); + if (strDest != NULL) { + strDest[0] = L'\0'; + return EINVAL_AND_RESET; + } + return EINVAL; + } + if (count > SECUREC_WCHAR_STRING_MAX_LEN) { +#ifdef SECUREC_COMPATIBLE_WIN_FORMAT + if (count == (size_t)(-1)) { + return SecDoCpyLimitW(strDest, destMax, strSrc, destMax - 1); + } +#endif + strDest[0] = L'\0'; /* Clear dest string */ + SECUREC_ERROR_INVALID_RANGE("wcsncpy_s"); + return ERANGE_AND_RESET; + } + + if (count == 0) { + strDest[0] = L'\0'; + return EOK; + } + + return SecDoCpyLimitW(strDest, destMax, strSrc, count); +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wcstok_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wcstok_s.c new file mode 100644 index 0000000000000000000000000000000000000000..063ca6917a0d84d9acfe83ab2cc8c6d89dc5d9c4 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wcstok_s.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: wcstok_s function + * Create: 2014-02-25 + */ + +#include "securecutil.h" + +SECUREC_INLINE int SecIsInDelimitW(wchar_t ch, const wchar_t *strDelimit) +{ + const wchar_t *ctl = strDelimit; + while (*ctl != L'\0' && *ctl != ch) { + ++ctl; + } + return (int)(*ctl != L'\0'); +} + +/* + * Find beginning of token (skip over leading delimiters). + * Note that there is no token if this loop sets string to point to the terminal null. + */ +SECUREC_INLINE wchar_t *SecFindBeginW(wchar_t *strToken, const wchar_t *strDelimit) +{ + wchar_t *token = strToken; + while (*token != L'\0') { + if (SecIsInDelimitW(*token, strDelimit) != 0) { + ++token; + continue; + } + /* Don't find any delimiter in string header, break the loop */ + break; + } + return token; +} + +/* + * Find the end of the token. If it is not the end of the string, put a null there. + */ +SECUREC_INLINE wchar_t *SecFindRestW(wchar_t *strToken, const wchar_t *strDelimit) +{ + wchar_t *token = strToken; + while (*token != L'\0') { + if (SecIsInDelimitW(*token, strDelimit) != 0) { + /* Find a delimiter, set string terminator */ + *token = L'\0'; + ++token; + break; + } + ++token; + } + return token; +} + +/* + * Update Token wide character function + */ +SECUREC_INLINE wchar_t *SecUpdateTokenW(wchar_t *strToken, const wchar_t *strDelimit, wchar_t **context) +{ + /* Point to updated position. Record string position for next search in the context */ + *context = SecFindRestW(strToken, strDelimit); + /* Determine if a token has been found */ + if (*context == strToken) { + return NULL; + } + return strToken; +} + +/* + * + * wcstok_s + * + * + * + * The wcstok_s function is the wide-character equivalent of the strtok_s function + * + * + * strToken String containing token or tokens. + * strDelimit Set of delimiter characters. + * context Used to store position information between calls to + * wcstok_s. + * + * + * context is updated + * + * The wcstok_s function is the wide-character equivalent of the strtok_s function + */ +wchar_t *wcstok_s(wchar_t *strToken, const wchar_t *strDelimit, wchar_t **context) +{ + wchar_t *orgToken = strToken; + /* Validation section */ + if (context == NULL || strDelimit == NULL) { + return NULL; + } + if (orgToken == NULL && *context == NULL) { + return NULL; + } + /* If string==NULL, continue with previous string */ + if (orgToken == NULL) { + orgToken = *context; + } + orgToken = SecFindBeginW(orgToken, strDelimit); + return SecUpdateTokenW(orgToken, strDelimit, context); +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wmemcpy_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wmemcpy_s.c new file mode 100644 index 0000000000000000000000000000000000000000..2f2b4a33cecf12535c4cf75b0c0376b5e81ab7cf --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wmemcpy_s.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: wmemcpy_s function + * Create: 2014-02-25 + */ +/* + * [Standardize-exceptions] Use unsafe function: Portability + * [reason] Use unsafe function to implement security function to maintain platform compatibility. + * And sufficient input validation is performed before calling + */ + +#include "securecutil.h" + +/* + * + * The wmemcpy_s function copies n successive wide characters + * from the object pointed to by src into the object pointed to by dest.t. + * + * + * dest Destination buffer. + * destMax Size of the destination buffer. + * src Buffer to copy from. + * count Number of characters to copy. + * + * + * dest buffer is updated. + * + * + * EOK Success + * EINVAL dest is NULL and destMax != 0 and count <= destMax + * and destMax <= SECUREC_WCHAR_MEM_MAX_LEN + * EINVAL_AND_RESET dest != NULL and src is NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_MEM_MAX_LEN and count <= destMax + * ERANGE destMax > SECUREC_WCHAR_MEM_MAX_LEN or destMax is 0 or + * (count > destMax and dest is NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_MEM_MAX_LEN) + * ERANGE_AND_RESET count > destMax and dest != NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_MEM_MAX_LEN + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and + * count <= destMax destMax != 0 and destMax <= SECUREC_WCHAR_MEM_MAX_LEN + * and dest != NULL and src != NULL and dest != src + * + * if an error occurred, dest will be filled with 0 when dest and destMax valid . + * If the source and destination overlap, the behavior of wmemcpy_s is undefined. + * Use wmemmove_s to handle overlapping regions. + */ +errno_t wmemcpy_s(wchar_t *dest, size_t destMax, const wchar_t *src, size_t count) +{ + if (destMax == 0 || destMax > SECUREC_WCHAR_MEM_MAX_LEN) { + SECUREC_ERROR_INVALID_PARAMTER("wmemcpy_s"); + return ERANGE; + } + if (count > destMax) { + SECUREC_ERROR_INVALID_PARAMTER("wmemcpy_s"); + if (dest != NULL) { + (void)SECUREC_MEMSET_FUNC_OPT(dest, 0, destMax * sizeof(wchar_t)); + return ERANGE_AND_RESET; + } + return ERANGE; + } + return memcpy_s(dest, destMax * sizeof(wchar_t), src, count * sizeof(wchar_t)); +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wmemmove_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wmemmove_s.c new file mode 100644 index 0000000000000000000000000000000000000000..88bb97b90454940d3d4333e8253bbbe9d86a6322 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wmemmove_s.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: wmemmove_s function + * Create: 2014-02-25 + */ +/* + * [Standardize-exceptions] Use unsafe function: Portability + * [reason] Use unsafe function to implement security function to maintain platform compatibility. + * And sufficient input validation is performed before calling + */ + +#include "securecutil.h" + +/* + * + * The wmemmove_s function copies n successive wide characters from the object pointed + * to by src into the object pointed to by dest. + * + * + * dest Destination buffer. + * destMax Size of the destination buffer. + * src Source object. + * count Number of bytes or character to copy. + * + * + * dest is updated. + * + * + * EOK Success + * EINVAL dest is NULL and destMax != 0 and count <= destMax + * and destMax <= SECUREC_WCHAR_MEM_MAX_LEN + * EINVAL_AND_RESET dest != NULL and src is NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_MEM_MAX_LEN and count <= destMax + * ERANGE destMax > SECUREC_WCHAR_MEM_MAX_LEN or destMax is 0 or + * (count > destMax and dest is NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_MEM_MAX_LEN) + * ERANGE_AND_RESET count > destMax and dest != NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_MEM_MAX_LEN + * + * + * If an error occurred, dest will be filled with 0 when dest and destMax valid. + * If some regions of the source area and the destination overlap, wmemmove_s + * ensures that the original source bytes in the overlapping region are copied + * before being overwritten + */ +errno_t wmemmove_s(wchar_t *dest, size_t destMax, const wchar_t *src, size_t count) +{ + if (destMax == 0 || destMax > SECUREC_WCHAR_MEM_MAX_LEN) { + SECUREC_ERROR_INVALID_PARAMTER("wmemmove_s"); + return ERANGE; + } + if (count > destMax) { + SECUREC_ERROR_INVALID_PARAMTER("wmemmove_s"); + if (dest != NULL) { + (void)SECUREC_MEMSET_FUNC_OPT(dest, 0, destMax * sizeof(wchar_t)); + return ERANGE_AND_RESET; + } + return ERANGE; + } + return memmove_s(dest, destMax * sizeof(wchar_t), src, count * sizeof(wchar_t)); +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wscanf_s.c b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wscanf_s.c new file mode 100644 index 0000000000000000000000000000000000000000..badb04efa054533c176de58029e38abdbbdbf283 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/hisilicon/libboundscheck_v1.1.16/src/wscanf_s.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: wscanf_s function + * Create: 2014-02-25 + */ + +#include "securec.h" + +/* + * + * + * The wscanf_s function is the wide-character equivalent of the scanf_s function + * The wscanf_s function reads data from the standard input stream stdin and + * writes the data into the location that's given by argument. Each argument + * must be a pointer to a variable of a type that corresponds to a type specifier + * in format. If copying occurs between strings that overlap, the behavior is + * undefined. + * + * + * format Format control string. + * ... Optional arguments. + * + * + * ... the converted value stored in user assigned address + * + * + * Returns the number of fields successfully converted and assigned; + * the return value does not include fields that were read but not assigned. + * A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int wscanf_s(const wchar_t *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vwscanf_s(format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} + diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/thirdparty/sysroot/include/mcs_smo_4th.h b/vendor/xinlingyu_92_3061M/Project/middleware/thirdparty/sysroot/include/mcs_smo_4th.h new file mode 100644 index 0000000000000000000000000000000000000000..5fb9a507342867de955d0520bcf20139f572603d --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/thirdparty/sysroot/include/mcs_smo_4th.h @@ -0,0 +1,71 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_smo_4th.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of 4th order smo module. + */ +#ifndef McuMagicTag_MCS_SMO_4TH_H +#define McuMagicTag_MCS_SMO_4TH_H + +#include "mcs_typedef.h" +#include "mcs_pll.h" +#include "mcs_filter.h" +#include "mcs_mtr_param.h" + + +typedef struct { + /* Model parameters */ + float ld; + float lq; + float rs; + float ts; + float kd; + float kq; + float pllBdw; + float fcLpf; /**< The cut-off frequency of First-order LPF for speed (Hz). */ + float elecAngle; + float spdEst; + /* Internal variable */ + AlbeAxis ialbeEst; + AlbeAxis ealbeEst; + PLL_Handle pll; + FOFLT_Handle spdFilter; +} SMO4TH_Handle; + +/** + * @brief SMO4TH_Param + */ +typedef struct { + float kd; + float kq; + float pllBdw; + float fcLpf; +} SMO4TH_Param; + + +void SMO4TH_Init(SMO4TH_Handle *smo4th, const SMO4TH_Param smo4thParam, const MOTOR_Param mtrParam, float ts); + +void SMO4TH_Exec(SMO4TH_Handle *smo4th, const AlbeAxis *ialbeFbk, const AlbeAxis *valbeRef); + +void SMO4TH_ParamUpdate(SMO4TH_Handle *smo4th, float kd, float kq, float pllBdw, float fc); + +void SMO4TH_Clear(SMO4TH_Handle *smo4th); + +void SMO4TH_SetTs(SMO4TH_Handle *smo4th, float ts); + +#endif \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/thirdparty/sysroot/include/nos_task.h b/vendor/xinlingyu_92_3061M/Project/middleware/thirdparty/sysroot/include/nos_task.h new file mode 100644 index 0000000000000000000000000000000000000000..78ff812782b72318909c186f070b8b7a1696172a --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/middleware/thirdparty/sysroot/include/nos_task.h @@ -0,0 +1,84 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file nos_task.h + */ + +#ifndef NOS_TASK_H +#define NOS_TASK_H + +#define NOS_TASK_PRIORITY_LOWEST 4 + +typedef void (*NOS_TaskEntryFunc)(void* param); +typedef void (*NOS_TimerCallBack)(void* param); +typedef struct { + const char *name; + NOS_TaskEntryFunc taskEntry; + void* param; + unsigned int priority; /* scope:[0-NOS_TASK_PRIORITY_LOWEST] */ + unsigned int stackAddr; /* notice: addr must 16Bytes align && not zero */ + unsigned int stackSize; + unsigned int privateData; +} NOS_TaskInitParam; + +typedef struct { + const char *name; + unsigned int timeout; // us + NOS_TimerCallBack callback; + void *callbackParam; + unsigned int priority; /* scope:[0-NOS_TASK_PRIORITY_LOWEST] */ + unsigned int stackSize; + unsigned int stackAddr; +}NOS_TimerTaskInitParam; + +typedef struct { + unsigned int cyclePerUs; + unsigned int usecPerTick; + unsigned long long (*getTickFunc)(void); +}NOS_SysConfig; + +int NOS_TaskInit(NOS_SysConfig *config); + +int NOS_StartScheduler(void); + +int NOS_TaskCreateOnly(NOS_TaskInitParam *initParam, unsigned int *taskId); + +int NOS_TaskCreate(NOS_TaskInitParam *initParam, unsigned int *taskId); + +int NOS_TaskDelete(unsigned int taskId); + +int NOS_TaskSuspend(unsigned int taskId); + +int NOS_TaskResume(unsigned int taskId); + +int NOS_TaskDelay(unsigned int timeout); + +int NOS_TaskPrioritySet(unsigned int taskId, unsigned short priority); + +int NOS_TaskPriorityGet(unsigned int taskId, unsigned short *priority); + +/* **********************timer task********************* */ + +int NOS_CreateTimerTask(unsigned int *timerTaskId, NOS_TimerTaskInitParam *timerParam); + +/* 接口约束 必须systick启动后. taskId 必须是 NOS_CreateTimerTask 创建的 */ +int NOS_StartTimerTask(unsigned int taskId); + +/* 接口约束 必须systick启动后. taskId 必须是 NOS_CreateTimerTask 创建的 */ +int NOS_StopTimerTask(unsigned int taskId); + +#endif // NOS_TASK_H diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/thirdparty/sysroot/lib/libmcs_smo_4th.a b/vendor/xinlingyu_92_3061M/Project/middleware/thirdparty/sysroot/lib/libmcs_smo_4th.a new file mode 100644 index 0000000000000000000000000000000000000000..2852d63db2444ccc666bce64872c3e6db1d23d31 Binary files /dev/null and b/vendor/xinlingyu_92_3061M/Project/middleware/thirdparty/sysroot/lib/libmcs_smo_4th.a differ diff --git a/vendor/xinlingyu_92_3061M/Project/middleware/thirdparty/sysroot/lib/libnostask.a b/vendor/xinlingyu_92_3061M/Project/middleware/thirdparty/sysroot/lib/libnostask.a new file mode 100644 index 0000000000000000000000000000000000000000..2dd6fe666747eb1f9fcf764a7fa5b2c5130cdde3 Binary files /dev/null and b/vendor/xinlingyu_92_3061M/Project/middleware/thirdparty/sysroot/lib/libnostask.a differ diff --git a/vendor/xinlingyu_92_3061M/Project/out/.ninja_deps b/vendor/xinlingyu_92_3061M/Project/out/.ninja_deps new file mode 100644 index 0000000000000000000000000000000000000000..a9ab2850c609bdcd693ad2cbf904066d61892af2 Binary files /dev/null and b/vendor/xinlingyu_92_3061M/Project/out/.ninja_deps differ diff --git a/vendor/xinlingyu_92_3061M/Project/out/.ninja_log b/vendor/xinlingyu_92_3061M/Project/out/.ninja_log new file mode 100644 index 0000000000000000000000000000000000000000..fb4974389b9a52036d6c8765282e4e90adbe0768 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/out/.ninja_log @@ -0,0 +1,407 @@ +# ninja log v6 +12 197 7506805969361305 obj/chip/3061m/startup.o 6c2783528fafc246 +323 741 7506805972477870 obj/drivers/debug/log/src/cmd.o cb97a6fe44477932 +46 266 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file mode 100644 index 0000000000000000000000000000000000000000..10a8579bf8fc8d1a9bbcb53b8e475ac41ea16e92 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/out/bin/target.list @@ -0,0 +1,16351 @@ + +out/bin/target.elf: file format elf32-littleriscv + + +Disassembly of section .text.entry: + +03000004 <_start>: + + .section .text.entry + .global _start + .option norvc +_start: + j handle_reset + 3000004: 4fc0006f j 3000500 + +03000008 : +.endm + +/* The interrupt vector table must be aligned with 4 bytes */ +.align 2 +TrapHandler: + j TrapVector /* trap and INT 0 */ + 3000008: 4680006f j 3000470 + j TrapVector /* INT 1 */ + 300000c: 4640006f j 3000470 + j TrapVector /* INT 2 */ + 3000010: 4600006f j 3000470 + j TrapVector /* INT 3 */ + 3000014: 45c0006f j 3000470 + j TrapVector /* INT 4 */ + 3000018: 4580006f j 3000470 + j TrapVector /* INT 5 */ + 300001c: 4540006f j 3000470 + j TrapVector /* INT 6 */ + 3000020: 4500006f j 3000470 + j TrapVector /* INT 7 */ + 3000024: 44c0006f j 3000470 + j TrapVector /* INT 8 */ + 3000028: 4480006f j 3000470 + j TrapVector /* INT 9 */ + 300002c: 4440006f j 3000470 + j TrapVector /* INT 10 */ + 3000030: 4400006f j 3000470 + j TrapVector /* INT 11 */ + 3000034: 43c0006f j 3000470 + j TrapVector /* INT 12 */ + 3000038: 4380006f j 3000470 + j TrapVector /* INT 13 */ + 300003c: 4340006f j 3000470 + j TrapVector /* INT 14 */ + 3000040: 4300006f j 3000470 + j TrapVector /* INT 15 */ + 3000044: 42c0006f j 3000470 + j TrapVector /* INT 16 */ + 3000048: 4280006f j 3000470 + j TrapVector /* INT 17 */ + 300004c: 4240006f j 3000470 + j TrapVector /* INT 18 */ + 3000050: 4200006f j 3000470 + j TrapVector /* INT 19 */ + 3000054: 41c0006f j 3000470 + j TrapVector /* INT 20 */ + 3000058: 4180006f j 3000470 + j TrapVector /* INT 21 */ + 300005c: 4140006f j 3000470 + j TrapVector /* INT 22 */ + 3000060: 4100006f j 3000470 + j TrapVector /* INT 23 */ + 3000064: 40c0006f j 3000470 + j TrapVector /* INT 24 */ + 3000068: 4080006f j 3000470 + j TrapVector /* INT 25 */ + 300006c: 4040006f j 3000470 + + j IntHandler /* INT 26 */ + 3000070: 2640006f j 30002d4 + j IntHandler /* INT 27 */ + 3000074: 2600006f j 30002d4 + j IntHandler /* INT 28 */ + 3000078: 25c0006f j 30002d4 + j IntHandler /* INT 29 */ + 300007c: 2580006f j 30002d4 + j IntHandler /* INT 30 */ + 3000080: 2540006f j 30002d4 + j IntHandler /* INT 31 */ + 3000084: 2500006f j 30002d4 + j IntHandler /* INT 32 */ + 3000088: 24c0006f j 30002d4 + j IntHandler /* INT 33 */ + 300008c: 2480006f j 30002d4 + j IntHandler /* INT 34 */ + 3000090: 2440006f j 30002d4 + j IntHandler /* INT 35 */ + 3000094: 2400006f j 30002d4 + j IntHandler /* INT 36 */ + 3000098: 23c0006f j 30002d4 + j IntHandler /* INT 37 */ + 300009c: 2380006f j 30002d4 + j IntHandler /* INT 38 */ + 30000a0: 2340006f j 30002d4 + j IntHandler /* INT 39 */ + 30000a4: 2300006f j 30002d4 + j IntHandler /* INT 40 */ + 30000a8: 22c0006f j 30002d4 + j IntHandler /* INT 41 */ + 30000ac: 2280006f j 30002d4 + j IntHandler /* INT 42 */ + 30000b0: 2240006f j 30002d4 + j IntHandler /* INT 43 */ + 30000b4: 2200006f j 30002d4 + j IntHandler /* INT 44 */ + 30000b8: 21c0006f j 30002d4 + j IntHandler /* INT 45 */ + 30000bc: 2180006f j 30002d4 + j IntHandler /* INT 46 */ + 30000c0: 2140006f j 30002d4 + j IntHandler /* INT 47 */ + 30000c4: 2100006f j 30002d4 + j IntHandler /* INT 48 */ + 30000c8: 20c0006f j 30002d4 + j IntHandler /* INT 49 */ + 30000cc: 2080006f j 30002d4 + j IntHandler /* INT 50 */ + 30000d0: 2040006f j 30002d4 + j IntHandler /* INT 51 */ + 30000d4: 2000006f j 30002d4 + j IntHandler /* INT 52 */ + 30000d8: 1fc0006f j 30002d4 + j IntHandler /* INT 53 */ + 30000dc: 1f80006f j 30002d4 + j IntHandler /* INT 54 */ + 30000e0: 1f40006f j 30002d4 + j IntHandler /* INT 55 */ + 30000e4: 1f00006f j 30002d4 + j IntHandler /* INT 56 */ + 30000e8: 1ec0006f j 30002d4 + j IntHandler /* INT 57 */ + 30000ec: 1e80006f j 30002d4 + j IntHandler /* INT 58 */ + 30000f0: 1e40006f j 30002d4 + j IntHandler /* INT 59 */ + 30000f4: 1e00006f j 30002d4 + j IntHandler /* INT 60 */ + 30000f8: 1dc0006f j 30002d4 + j IntHandler /* INT 61 */ + 30000fc: 1d80006f j 30002d4 + j IntHandler /* INT 62 */ + 3000100: 1d40006f j 30002d4 + j IntHandler /* INT 63 */ + 3000104: 1d00006f j 30002d4 + j IntHandler /* INT 64 */ + 3000108: 1cc0006f j 30002d4 + j IntHandler /* INT 65 */ + 300010c: 1c80006f j 30002d4 + j IntHandler /* INT 66 */ + 3000110: 1c40006f j 30002d4 + j IntHandler /* INT 67 */ + 3000114: 1c00006f j 30002d4 + j IntHandler /* INT 68 */ + 3000118: 1bc0006f j 30002d4 + j IntHandler /* INT 69 */ + 300011c: 1b80006f j 30002d4 + j IntHandler /* INT 70 */ + 3000120: 1b40006f j 30002d4 + j IntHandler /* INT 71 */ + 3000124: 1b00006f j 30002d4 + j IntHandler /* INT 72 */ + 3000128: 1ac0006f j 30002d4 + j IntHandler /* INT 73 */ + 300012c: 1a80006f j 30002d4 + j IntHandler /* INT 74 */ + 3000130: 1a40006f j 30002d4 + j IntHandler /* INT 75 */ + 3000134: 1a00006f j 30002d4 + j IntHandler /* INT 76 */ + 3000138: 19c0006f j 30002d4 + j IntHandler /* INT 77 */ + 300013c: 1980006f j 30002d4 + j IntHandler /* INT 78 */ + 3000140: 1940006f j 30002d4 + j IntHandler /* INT 79 */ + 3000144: 1900006f j 30002d4 + j IntHandler /* INT 80 */ + 3000148: 18c0006f j 30002d4 + j IntHandler /* INT 81 */ + 300014c: 1880006f j 30002d4 + j IntHandler /* INT 82 */ + 3000150: 1840006f j 30002d4 + j IntHandler /* INT 83 */ + 3000154: 1800006f j 30002d4 + j IntHandler /* INT 84 */ + 3000158: 17c0006f j 30002d4 + j IntHandler /* INT 85 */ + 300015c: 1780006f j 30002d4 + j IntHandler /* INT 86 */ + 3000160: 1740006f j 30002d4 + j IntHandler /* INT 87 */ + 3000164: 1700006f j 30002d4 + j IntHandler /* INT 88 */ + 3000168: 16c0006f j 30002d4 + j IntHandler /* INT 89 */ + 300016c: 1680006f j 30002d4 + j IntHandler /* INT 90 */ + 3000170: 1640006f j 30002d4 + j IntHandler /* INT 91 */ + 3000174: 1600006f j 30002d4 + j IntHandler /* INT 92 */ + 3000178: 15c0006f j 30002d4 + j IntHandler /* INT 93 */ + 300017c: 1580006f j 30002d4 + j IntHandler /* INT 94 */ + 3000180: 1540006f j 30002d4 + j IntHandler /* INT 95 */ + 3000184: 1500006f j 30002d4 + j IntHandler /* INT 96 */ + 3000188: 14c0006f j 30002d4 + j IntHandler /* INT 97 */ + 300018c: 1480006f j 30002d4 + j IntHandler /* INT 98 */ + 3000190: 1440006f j 30002d4 + j IntHandler /* INT 99 */ + 3000194: 1400006f j 30002d4 + j IntHandler /* INT 100 */ + 3000198: 13c0006f j 30002d4 + j IntHandler /* INT 101 */ + 300019c: 1380006f j 30002d4 + j IntHandler /* INT 102 */ + 30001a0: 1340006f j 30002d4 + j IntHandler /* INT 103 */ + 30001a4: 1300006f j 30002d4 + j IntHandler /* INT 104 */ + 30001a8: 12c0006f j 30002d4 + j IntHandler /* INT 105 */ + 30001ac: 1280006f j 30002d4 + j IntHandler /* INT 106 */ + 30001b0: 1240006f j 30002d4 + j IntHandler /* INT 107 */ + 30001b4: 1200006f j 30002d4 + j IntHandler /* INT 108 */ + 30001b8: 11c0006f j 30002d4 + j IntHandler /* INT 109 */ + 30001bc: 1180006f j 30002d4 + j IntHandler /* INT 110 */ + 30001c0: 1140006f j 30002d4 + j IntHandler /* INT 111 */ + 30001c4: 1100006f j 30002d4 + j IntHandler /* INT 112 */ + 30001c8: 10c0006f j 30002d4 + j IntHandler /* INT 113 */ + 30001cc: 1080006f j 30002d4 + j IntHandler /* INT 114 */ + 30001d0: 1040006f j 30002d4 + j IntHandler /* INT 115 */ + 30001d4: 1000006f j 30002d4 + j IntHandler /* INT 116 */ + 30001d8: 0fc0006f j 30002d4 + j IntHandler /* INT 117 */ + 30001dc: 0f80006f j 30002d4 + j IntHandler /* INT 118 */ + 30001e0: 0f40006f j 30002d4 + j IntHandler /* INT 119 */ + 30001e4: 0f00006f j 30002d4 + j IntHandler /* INT 120 */ + 30001e8: 0ec0006f j 30002d4 + j IntHandler /* INT 121 */ + 30001ec: 0e80006f j 30002d4 + +030001f0 : + +.align 2 +NmiEntry: + SAVE_SYSERR_REGS + 30001f0: f9010113 addi sp,sp,-112 + 30001f4: 04812023 sw s0,64(sp) + 30001f8: 04912223 sw s1,68(sp) + 30001fc: 05212423 sw s2,72(sp) + 3000200: 05312623 sw s3,76(sp) + 3000204: 05412823 sw s4,80(sp) + 3000208: 05512a23 sw s5,84(sp) + 300020c: 05612c23 sw s6,88(sp) + 3000210: 05712e23 sw s7,92(sp) + 3000214: 07812023 sw s8,96(sp) + 3000218: 07912223 sw s9,100(sp) + 300021c: 07a12423 sw s10,104(sp) + 3000220: 07b12623 sw s11,108(sp) + 3000224: 11010593 addi a1,sp,272 + 3000228: 06b12823 sw a1,112(sp) + 300022c: 06312a23 sw gp,116(sp) + 3000230: 06412c23 sw tp,120(sp) + 3000234: 34102573 csrr a0,mepc + 3000238: 300025f3 csrr a1,mstatus + 300023c: 34302673 csrr a2,mtval + 3000240: 342026f3 csrr a3,mcause + 3000244: 06a12e23 sw a0,124(sp) + 3000248: 08b12023 sw a1,128(sp) + 300024c: 08c12223 sw a2,132(sp) + 3000250: 08d12423 sw a3,136(sp) + 3000254: 00010513 mv a0,sp + call SysErrNmiEntry + 3000258: 3a4010ef jal ra,30015fc + +0300025c : +deadLoop1: + tail deadLoop1 + 300025c: a001 j 300025c + nop + 300025e: 00000013 nop + +03000262 : + +.align 2 +TrapEntry: + SAVE_SYSERR_REGS + 3000262: f9010113 addi sp,sp,-112 + 3000266: 04812023 sw s0,64(sp) + 300026a: 04912223 sw s1,68(sp) + 300026e: 05212423 sw s2,72(sp) + 3000272: 05312623 sw s3,76(sp) + 3000276: 05412823 sw s4,80(sp) + 300027a: 05512a23 sw s5,84(sp) + 300027e: 05612c23 sw s6,88(sp) + 3000282: 05712e23 sw s7,92(sp) + 3000286: 07812023 sw s8,96(sp) + 300028a: 07912223 sw s9,100(sp) + 300028e: 07a12423 sw s10,104(sp) + 3000292: 07b12623 sw s11,108(sp) + 3000296: 11010593 addi a1,sp,272 + 300029a: 06b12823 sw a1,112(sp) + 300029e: 06312a23 sw gp,116(sp) + 30002a2: 06412c23 sw tp,120(sp) + 30002a6: 34102573 csrr a0,mepc + 30002aa: 300025f3 csrr a1,mstatus + 30002ae: 34302673 csrr a2,mtval + 30002b2: 342026f3 csrr a3,mcause + 30002b6: 06a12e23 sw a0,124(sp) + 30002ba: 08b12023 sw a1,128(sp) + 30002be: 08c12223 sw a2,132(sp) + 30002c2: 08d12423 sw a3,136(sp) + 30002c6: 00010513 mv a0,sp + /* Exception run with interrupts masked */ + csrc mstatus, MSTATUS_MIE + 30002ca: 30047073 csrci mstatus,8 + call SysErrExcEntry + 30002ce: 310010ef jal ra,30015de + +030002d2 : +deadLoop2: + tail deadLoop2 + 30002d2: a001 j 30002d2 + +030002d4 : + +.align 2 +IntHandler: + addi sp, sp, -(TOTAL_INT_SIZE_ON_STACK) + 30002d4: f6010113 addi sp,sp,-160 + + SREG a0, 3 * REGBYTES(sp) + 30002d8: 00a12623 sw a0,12(sp) + SREG a1, 4 * REGBYTES(sp) + 30002dc: 00b12823 sw a1,16(sp) +#endif + +#if defined(HARD_NESTED_IRQ_SUPPORT) && (HARD_NESTED_IRQ_SUPPORT == 1) + csrr a0, mcause +#else + csrr a0, cipri + 30002e0: 7ed02573 csrr a0,0x7ed + csrr a1, prithd + 30002e4: bfe025f3 csrr a1,0xbfe + csrw prithd, a0 /* read prithd */ + 30002e8: bfe51073 csrw 0xbfe,a0 + SREG a1, 6 * REGBYTES(sp) /* save prithd */ + 30002ec: 00b12c23 sw a1,24(sp) + csrr a1, mstatus /* read mstatus */ + 30002f0: 300025f3 csrr a1,mstatus + SREG a1, 7 * REGBYTES(sp) /* save mstatus */ + 30002f4: 00b12e23 sw a1,28(sp) + csrr a1, mepc /* read mepc */ + 30002f8: 341025f3 csrr a1,mepc + SREG a1, 8 * REGBYTES(sp) /* save mepc */ + 30002fc: 02b12023 sw a1,32(sp) + + csrr a0, mcause + 3000300: 34202573 csrr a0,mcause + + li a1, (3<<11) + 3000304: 000025b7 lui a1,0x2 + 3000308: 80058593 addi a1,a1,-2048 # 1800 + csrs mstatus, a1 + 300030c: 3005a073 csrs mstatus,a1 + la a1, custom_nested_irq_main_handler_entry + 3000310: 00000597 auipc a1,0x0 + 3000314: 01058593 addi a1,a1,16 # 3000320 + csrw mepc, a1 + 3000318: 34159073 csrw mepc,a1 + mret + 300031c: 30200073 mret + +03000320 : +#endif + +.align 2 +custom_nested_irq_main_handler_entry: + SREG t0, 0 * REGBYTES(sp) + 3000320: 00512023 sw t0,0(sp) + SREG t1, 1 * REGBYTES(sp) + 3000324: 00612223 sw t1,4(sp) + SREG t2, 2 * REGBYTES(sp) + 3000328: 00712423 sw t2,8(sp) + SREG a2, 5 * REGBYTES(sp) + 300032c: 00c12a23 sw a2,20(sp) + SREG ra, 9 * REGBYTES(sp) + 3000330: 02112223 sw ra,36(sp) + SREG a3, 10 * REGBYTES(sp) + 3000334: 02d12423 sw a3,40(sp) + SREG a4, 11 * REGBYTES(sp) + 3000338: 02e12623 sw a4,44(sp) + SREG a5, 12 * REGBYTES(sp) + 300033c: 02f12823 sw a5,48(sp) + SREG a6, 13 * REGBYTES(sp) + 3000340: 03012a23 sw a6,52(sp) + SREG a7, 14 * REGBYTES(sp) + 3000344: 03112c23 sw a7,56(sp) + SREG t3, 15 * REGBYTES(sp) + 3000348: 03c12e23 sw t3,60(sp) + SREG t4, 16 * REGBYTES(sp) + 300034c: 05d12023 sw t4,64(sp) + SREG t5, 17 * REGBYTES(sp) + 3000350: 05e12223 sw t5,68(sp) + SREG t6, 18 * REGBYTES(sp) + 3000354: 05f12423 sw t6,72(sp) + +#ifdef FLOAT_SUPPORT + FSREG f0, 19 * REGBYTES(sp) + 3000358: 04012627 fsw ft0,76(sp) + FSREG f1, 20 * REGBYTES(sp) + 300035c: 04112827 fsw ft1,80(sp) + FSREG f2, 21 * REGBYTES(sp) + 3000360: 04212a27 fsw ft2,84(sp) + FSREG f3, 22 * REGBYTES(sp) + 3000364: 04312c27 fsw ft3,88(sp) + FSREG f4, 23 * REGBYTES(sp) + 3000368: 04412e27 fsw ft4,92(sp) + FSREG f5, 24 * REGBYTES(sp) + 300036c: 06512027 fsw ft5,96(sp) + FSREG f6, 25 * REGBYTES(sp) + 3000370: 06612227 fsw ft6,100(sp) + FSREG f7, 26 * REGBYTES(sp) + 3000374: 06712427 fsw ft7,104(sp) + FSREG f10, 27 * REGBYTES(sp) + 3000378: 06a12627 fsw fa0,108(sp) + FSREG f11, 28 * REGBYTES(sp) + 300037c: 06b12827 fsw fa1,112(sp) + FSREG f12, 29 * REGBYTES(sp) + 3000380: 06c12a27 fsw fa2,116(sp) + FSREG f13, 30 * REGBYTES(sp) + 3000384: 06d12c27 fsw fa3,120(sp) + FSREG f14, 31 * REGBYTES(sp) + 3000388: 06e12e27 fsw fa4,124(sp) + FSREG f15, 32 * REGBYTES(sp) + 300038c: 08f12027 fsw fa5,128(sp) + FSREG f16, 33 * REGBYTES(sp) + 3000390: 09012227 fsw fa6,132(sp) + FSREG f17, 34 * REGBYTES(sp) + 3000394: 09112427 fsw fa7,136(sp) + FSREG f28, 35 * REGBYTES(sp) + 3000398: 09c12627 fsw ft8,140(sp) + FSREG f29, 36 * REGBYTES(sp) + 300039c: 09d12827 fsw ft9,144(sp) + FSREG f30, 37 * REGBYTES(sp) + 30003a0: 09e12a27 fsw ft10,148(sp) + FSREG f31, 38 * REGBYTES(sp) + 30003a4: 09f12c27 fsw ft11,152(sp) +#endif + + andi a0, a0, MCAUSE_MASK_INT_NUM + 30003a8: 0ff57513 andi a0,a0,255 + call InterruptEntry + 30003ac: 7c3000ef jal ra,300136e + + LREG t1, 1 * REGBYTES(sp) + 30003b0: 00412303 lw t1,4(sp) + LREG t2, 2 * REGBYTES(sp) + 30003b4: 00812383 lw t2,8(sp) + LREG a2, 5 * REGBYTES(sp) + 30003b8: 01412603 lw a2,20(sp) + LREG ra, 9 * REGBYTES(sp) + 30003bc: 02412083 lw ra,36(sp) + LREG a3, 10 * REGBYTES(sp) + 30003c0: 02812683 lw a3,40(sp) + LREG a4, 11 * REGBYTES(sp) + 30003c4: 02c12703 lw a4,44(sp) + LREG a5, 12 * REGBYTES(sp) + 30003c8: 03012783 lw a5,48(sp) + LREG a6, 13 * REGBYTES(sp) + 30003cc: 03412803 lw a6,52(sp) + LREG a7, 14 * REGBYTES(sp) + 30003d0: 03812883 lw a7,56(sp) + LREG t3, 15 * REGBYTES(sp) + 30003d4: 03c12e03 lw t3,60(sp) + LREG t4, 16 * REGBYTES(sp) + 30003d8: 04012e83 lw t4,64(sp) + LREG t5, 17 * REGBYTES(sp) + 30003dc: 04412f03 lw t5,68(sp) + LREG t6, 18 * REGBYTES(sp) + 30003e0: 04812f83 lw t6,72(sp) + +#ifdef FLOAT_SUPPORT + FLREG f0, 19 * REGBYTES(sp) + 30003e4: 04c12007 flw ft0,76(sp) + FLREG f1, 20 * REGBYTES(sp) + 30003e8: 05012087 flw ft1,80(sp) + FLREG f2, 21 * REGBYTES(sp) + 30003ec: 05412107 flw ft2,84(sp) + FLREG f3, 22 * REGBYTES(sp) + 30003f0: 05812187 flw ft3,88(sp) + FLREG f4, 23 * REGBYTES(sp) + 30003f4: 05c12207 flw ft4,92(sp) + FLREG f5, 24 * REGBYTES(sp) + 30003f8: 06012287 flw ft5,96(sp) + FLREG f6, 25 * REGBYTES(sp) + 30003fc: 06412307 flw ft6,100(sp) + FLREG f7, 26 * REGBYTES(sp) + 3000400: 06812387 flw ft7,104(sp) + FLREG f10, 27 * REGBYTES(sp) + 3000404: 06c12507 flw fa0,108(sp) + FLREG f11, 28 * REGBYTES(sp) + 3000408: 07012587 flw fa1,112(sp) + FLREG f12, 29 * REGBYTES(sp) + 300040c: 07412607 flw fa2,116(sp) + FLREG f13, 30 * REGBYTES(sp) + 3000410: 07812687 flw fa3,120(sp) + FLREG f14, 31 * REGBYTES(sp) + 3000414: 07c12707 flw fa4,124(sp) + FLREG f15, 32 * REGBYTES(sp) + 3000418: 08012787 flw fa5,128(sp) + FLREG f16, 33 * REGBYTES(sp) + 300041c: 08412807 flw fa6,132(sp) + FLREG f17, 34 * REGBYTES(sp) + 3000420: 08812887 flw fa7,136(sp) + FLREG f28, 35 * REGBYTES(sp) + 3000424: 08c12e07 flw ft8,140(sp) + FLREG f29, 36 * REGBYTES(sp) + 3000428: 09012e87 flw ft9,144(sp) + FLREG f30, 37 * REGBYTES(sp) + 300042c: 09412f07 flw ft10,148(sp) + FLREG f31, 38 * REGBYTES(sp) + 3000430: 09812f87 flw ft11,152(sp) + +03000434 : + */ + +#if defined(HARD_NESTED_IRQ_SUPPORT) && (HARD_NESTED_IRQ_SUPPORT == 1) + LREG t0, 0 * REGBYTES(sp) +#else + LREG a0, 7 * REGBYTES(sp) /* load mstatus */ + 3000434: 01c12503 lw a0,28(sp) + csrr t0, mstatus + 3000438: 300022f3 csrr t0,mstatus + LREG a1, 8 * REGBYTES(sp) /* load mepc */ + 300043c: 02012583 lw a1,32(sp) + andi t0, t0, MSTATUS_MIE + 3000440: 0082f293 andi t0,t0,8 + bnei t0, 0, restore_mstatus + 3000444: 0002923b bnei t0,0,300044c + andi a0, a0, ~(MSTATUS_MIE | MSTATUS_MPIE) + 3000448: f7757513 andi a0,a0,-137 + +0300044c : +restore_mstatus: + csrw mstatus, a0 + 300044c: 30051073 csrw mstatus,a0 + + LREG t0, 0 * REGBYTES(sp) + 3000450: 00012283 lw t0,0(sp) + csrw mepc, a1 + 3000454: 34159073 csrw mepc,a1 + LREG a0, 6 * REGBYTES(sp) /* load prithd */ + 3000458: 01812503 lw a0,24(sp) + csrw prithd, a0 + 300045c: bfe51073 csrw 0xbfe,a0 + lw a1, (a0) + addi a1, a1, -1 + sw a1, (a0) +#endif + + LREG a1, 4 * REGBYTES(sp) /* 2 consecutive csrw instructions will have a bubble */ + 3000460: 01012583 lw a1,16(sp) + + LREG a0, 3 * REGBYTES(sp) + 3000464: 00c12503 lw a0,12(sp) + + addi sp, sp, TOTAL_INT_SIZE_ON_STACK + 3000468: 0a010113 addi sp,sp,160 + + mret + 300046c: 30200073 mret + +03000470 : + +.align 2 +TrapVector: + push_reg + 3000470: f6010113 addi sp,sp,-160 + 3000474: fff11f8b stmia {ra,t0-t6,a0-a7},(sp) + 3000478: f6010113 addi sp,sp,-160 + csrr a0, mcause + 300047c: 34202573 csrr a0,mcause + li t1, MCAUSE_ECALL_FROM_MMODE + 3000480: 00b00313 li t1,11 +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + beq a0, t1, switch_to_umode +#else + beq a0, t1, switch_to_mmode + 3000484: 02650c63 beq a0,t1,30004bc +#endif + li t1, MCAUSE_ECALL_FROM_UMODE + 3000488: 00800313 li t1,8 + beq a0, t1, switch_to_mmode + 300048c: 02650863 beq a0,t1,30004bc + + li a1, MCAUSE_MASK_INT_BIT + 3000490: 800005b7 lui a1,0x80000 + li a2, MCAUSE_MASK_INT_NUM + 3000494: 0ff00613 li a2,255 + and a1, a0, a1 + 3000498: 00b575b3 and a1,a0,a1 + and a0, a0, a2 + 300049c: 00c57533 and a0,a0,a2 + + li a2, 0xc + 30004a0: 00c00613 li a2,12 + beq a0, a2, NmiEntry + 30004a4: d4c506e3 beq a0,a2,30001f0 + beqz a1, TrapEntry + 30004a8: da058de3 beqz a1,3000262 + pop_reg + 30004ac: 0a010113 addi sp,sp,160 + 30004b0: fff10f8b ldmia {ra,t0-t6,a0-a7},(sp) + 30004b4: 0a010113 addi sp,sp,160 + mret + 30004b8: 30200073 mret + +030004bc : + mret +#endif + +.align 2 +switch_to_mmode: + li t2, MSTATUS_MPP_MACHINE + 30004bc: 000023b7 lui t2,0x2 + 30004c0: 80038393 addi t2,t2,-2048 # 1800 + csrs mstatus, t2 + 30004c4: 3003a073 csrs mstatus,t2 + csrr t0, mepc + 30004c8: 341022f3 csrr t0,mepc + addi t0, t0, 4 + 30004cc: 00428293 addi t0,t0,4 + csrw mepc, t0 + 30004d0: 34129073 csrw mepc,t0 + pop_reg + 30004d4: 0a010113 addi sp,sp,160 + 30004d8: fff10f8b ldmia {ra,t0-t6,a0-a7},(sp) + 30004dc: 0a010113 addi sp,sp,160 + mret + 30004e0: 30200073 mret + +030004e4 : + +.align 2 +mem_cpy: + bge t0, t2, cpy_done + 30004e4: 0072dc63 bge t0,t2,30004fc + lw t3, (t1) + 30004e8: 00032e03 lw t3,0(t1) + sw t3, (t0) + 30004ec: 01c2a023 sw t3,0(t0) + addi t0, t0, 4 + 30004f0: 00428293 addi t0,t0,4 + addi t1, t1, 4 + 30004f4: 00430313 addi t1,t1,4 + j mem_cpy + 30004f8: fedff06f j 30004e4 + +030004fc : +cpy_done: + ret + 30004fc: 00008067 ret + +03000500 : + +.align 2 +handle_reset: + csrwi mstatus, 0 + 3000500: 30005073 csrwi mstatus,0 + csrwi mie, 0 + 3000504: 30405073 csrwi mie,0 + csrci mstatus, 0x08 + 3000508: 30047073 csrci mstatus,8 + la t0, TrapHandler + 300050c: 00000297 auipc t0,0x0 + 3000510: afc28293 addi t0,t0,-1284 # 3000008 + addi t0, t0, 1 + 3000514: 00128293 addi t0,t0,1 + csrw mtvec, t0 + 3000518: 30529073 csrw mtvec,t0 + csrwi 0x7EF, 0x1 /* lock mtvec */ + 300051c: 7ef0d073 csrwi 0x7ef,1 + +03000520 : + csrwi 0x7C8, 0x1 /* enable hardware nest interrupt support */ +#endif + +flash_init: +/* eflash prefetch enable */ + li t0, EFC_BASE_ADDR + 3000520: 147102b7 lui t0,0x14710 + lw t1, 0x120(t0) + 3000524: 1202a303 lw t1,288(t0) # 14710120 + ori t1, t1, 1 + 3000528: 00136313 ori t1,t1,1 + sw t1, 0x120(t0) + 300052c: 1262a023 sw t1,288(t0) + +/* eflash cache enable */ + lw t1, 0x124(t0) + 3000530: 1242a303 lw t1,292(t0) + ori t1, t1, 1 + 3000534: 00136313 ori t1,t1,1 + sw t1, 0x124(t0) + 3000538: 1262a223 sw t1,292(t0) + +/* enable flash cmd */ + li t0, EFC_MAGIC_NUMBER + 300053c: fedcc2b7 lui t0,0xfedcc + 3000540: a9828293 addi t0,t0,-1384 # fedcba98 + li t1, EFC_MAGIC_LOCK_RW + 3000544: 14710337 lui t1,0x14710 + 3000548: 20030313 addi t1,t1,512 # 14710200 + sw t0, (t1) + 300054c: 00532023 sw t0,0(t1) + +/* initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + 3000550: 01001197 auipc gp,0x1001 + 3000554: 2ce18193 addi gp,gp,718 # 400181e <__global_pointer$> + .option pop + +/* initialize stack pointer */ + la sp, __stack_top + 3000558: 01007117 auipc sp,0x1007 + 300055c: 6a810113 addi sp,sp,1704 # 4007c00 <__INTERRUPT_STACK_BEGIN__> + +/* timer0 interrupt enable */ + li t0, TIMER0_CONTROL + 3000560: 143002b7 lui t0,0x14300 + 3000564: 00828293 addi t0,t0,8 # 14300008 + lw t1, (t0) + 3000568: 0002a303 lw t1,0(t0) + andi t1, t1, TIMER0_INTENABLE + 300056c: 02037313 andi t1,t1,32 + sw t1, (t0) + 3000570: 0062a023 sw t1,0(t0) + +/* uart0 deinit */ + li t0, 0x14000000 + 3000574: 140002b7 lui t0,0x14000 + li t1, 0 + 3000578: 00000313 li t1,0 + sw t1, IBRD_OFFSET(t0) + 300057c: 0262a223 sw t1,36(t0) # 14000024 + sw t1, FBRD_OFFSET(t0) + 3000580: 0262a423 sw t1,40(t0) + sw t1, LCR_H_OFFSET(t0) + 3000584: 0262a623 sw t1,44(t0) + sw t1, CR_OFFSET(t0) + 3000588: 0262a823 sw t1,48(t0) + sw t1, DMACR_OFFSET(t0) + 300058c: 0462a423 sw t1,72(t0) + +03000590 : + +/* perform the rest of initialization in C */ +clear_sram: + /* clear sysram parity error */ + li t0, SYSRAM_ERROR + 3000590: 101082b7 lui t0,0x10108 + 3000594: 30028293 addi t0,t0,768 # 10108300 + lw t1, (t0) + 3000598: 0002a303 lw t1,0(t0) + ori t1, t1, 1 + 300059c: 00136313 ori t1,t1,1 + sw t1, (t0) + 30005a0: 0062a023 sw t1,0(t0) + + la t0, SRAM_START + 30005a4: 01000297 auipc t0,0x1000 + 30005a8: a5c28293 addi t0,t0,-1444 # 4000000 + la t1, SRAM_END + 30005ac: 01008317 auipc t1,0x1008 + 30005b0: a5430313 addi t1,t1,-1452 # 4008000 + li t2, 0 + 30005b4: 00000393 li t2,0 + +030005b8 : + +clear_sram_loop: + sw t2, (t0) /* clear all sram */ + 30005b8: 0072a023 sw t2,0(t0) + addi t0, t0, 4 /* increment clear index pointer */ + 30005bc: 00428293 addi t0,t0,4 + blt t0, t1, clear_sram_loop /* are we at the end yet, if not , contiue till the end */ + 30005c0: fe62cce3 blt t0,t1,30005b8 + +030005c4 : + +start_coderom_code_copy: + la t0, __sram_code_start_addr /* SRAM addr */ + 30005c4: ff000297 auipc t0,0xff000 + 30005c8: a3c28293 addi t0,t0,-1476 # 2000000 + la t1, __sram_code_load_addr /* ROM addr */ + 30005cc: 00000317 auipc t1,0x0 + 30005d0: 13830313 addi t1,t1,312 # 3000704 + la t2, __sram_code_end_addr + 30005d4: ff000397 auipc t2,0xff000 + 30005d8: a2c38393 addi t2,t2,-1492 # 2000000 + jal mem_cpy + 30005dc: f09ff0ef jal ra,30004e4 + +030005e0 : + +start_reserved_data_copy: + la t0, __reserved_code_start_addr /* SRAM addr */ + 30005e0: 01000297 auipc t0,0x1000 + 30005e4: a2028293 addi t0,t0,-1504 # 4000000 + la t1, __reserved_code_load_addr /* ROM addr */ + 30005e8: 00000317 auipc t1,0x0 + 30005ec: 11c30313 addi t1,t1,284 # 3000704 + la t2, __reserved_code_end_addr + 30005f0: 01000397 auipc t2,0x1000 + 30005f4: a1038393 addi t2,t2,-1520 # 4000000 + jal mem_cpy + 30005f8: eedff0ef jal ra,30004e4 + +030005fc : + +start_coderom_data_copy: + la t0, __data_start /* SRAM addr */ + 30005fc: 01000297 auipc t0,0x1000 + 3000600: a2428293 addi t0,t0,-1500 # 4000020 + la t1, __data_load /* ROM addr */ + 3000604: 00008317 auipc t1,0x8 + 3000608: 63c30313 addi t1,t1,1596 # 3008c40 <__data_load> + la t2, __data_end + 300060c: 01000397 auipc t2,0x1000 + 3000610: af038393 addi t2,t2,-1296 # 40000fc + jal mem_cpy + 3000614: ed1ff0ef jal ra,30004e4 + +03000618 : + +pmp_init: + li t0, 0xB00 + 3000618: 000012b7 lui t0,0x1 + 300061c: b0028293 addi t0,t0,-1280 # b00 + csrw pmpaddr0, t0 + 3000620: 3b029073 csrw pmpaddr0,t0 + li t0, 0x400400 /* 0x2C00~0x1000FFF, BOOTROM, enable R+X */ + 3000624: 004002b7 lui t0,0x400 + 3000628: 40028293 addi t0,t0,1024 # 400400 + csrw pmpaddr1, t0 + 300062c: 3b129073 csrw pmpaddr1,t0 + li t0, 0x800000 /* 0x1001000~0x1FFFFFF, Reserved: diable R+X+W */ + 3000630: 008002b7 lui t0,0x800 + csrw pmpaddr2, t0 + 3000634: 3b229073 csrw pmpaddr2,t0 + li t0, 0x802000 /* 0x2000000~0x2007FFF, SYSRAM_ITCM */ + 3000638: 008022b7 lui t0,0x802 + csrw pmpaddr3, t0 + 300063c: 3b329073 csrw pmpaddr3,t0 + li t0, 0xC00000 /* 0x2008000 ~ 0x2FFFFFF, Reserved: disable R+X+W */ + 3000640: 00c002b7 lui t0,0xc00 + csrw pmpaddr4, t0 + 3000644: 3b429073 csrw pmpaddr4,t0 + li t0, 0x1000000 /* 0x3000000 ~ 0x03FFFFFF: EFLASH: enable R+X */ + 3000648: 010002b7 lui t0,0x1000 + csrw pmpaddr5, t0 + 300064c: 3b529073 csrw pmpaddr5,t0 + li t0, 0x1002000 /* 0x4000000 ~ 0x04007FFF: SYSTEM_DTCM enable R+W */ + 3000650: 010022b7 lui t0,0x1002 + csrw pmpaddr6, t0 + 3000654: 3b629073 csrw pmpaddr6,t0 + li t0,0x7000400 /* 0x4008000 ~ 0x01C000FFF: REGISTER R+W */ + 3000658: 070002b7 lui t0,0x7000 + 300065c: 40028293 addi t0,t0,1024 # 7000400 + csrw pmpaddr7, t0 + 3000660: 3b729073 csrw pmpaddr7,t0 + + li t0,0xf3333333 /* register TOR-R-W */ + 3000664: f33332b7 lui t0,0xf3333 + 3000668: 33328293 addi t0,t0,819 # f3333333 + csrw 0x7d8,t0 + 300066c: 7d829073 csrw 0x7d8,t0 + li t0,0x0d080d8b /* 0x0d:TOR-R-X; 0x0b:TOR-R-W; 0x08:TOR; 0x0c:TOR-x; 0x09:TOR-R */ + csrw pmpcfg0,t0 + li t0,0x0b0b0d08 + csrw pmpcfg1,t0 +#else + li t0,0x8d888d8b /* 0x0d:TOR-R-X; 0x0b:TOR-R-W; 0x08:TOR; 0x0c:TOR-x; 0x09:TOR-R */ + 3000670: 8d8892b7 lui t0,0x8d889 + 3000674: d8b28293 addi t0,t0,-629 # 8d888d8b + csrw pmpcfg0,t0 + 3000678: 3a029073 csrw pmpcfg0,t0 + li t0,0x8b8b8d88 + 300067c: 8b8b92b7 lui t0,0x8b8b9 + 3000680: d8828293 addi t0,t0,-632 # 8b8b8d88 + csrw pmpcfg1,t0 + 3000684: 3a129073 csrw pmpcfg1,t0 +#endif + +/* disable Icache */ + csrwi 0x7C0, 0x0 /* disable ICACHE */ + 3000688: 7c005073 csrwi 0x7c0,0 + fence + 300068c: 0ff0000f fence + +/* disable Dcache */ + csrwi 0x7C1, 0x0 /* disable DCACHE */ + 3000690: 7c105073 csrwi 0x7c1,0 + fence + 3000694: 0ff0000f fence + +/* support float and mie */ + li t0,0x2008 + 3000698: 000022b7 lui t0,0x2 + 300069c: 00828293 addi t0,t0,8 # 2008 + csrs mstatus,t0 + 30006a0: 3002a073 csrs mstatus,t0 + li t0,0x20 + 30006a4: 02000293 li t0,32 + csrs misa,t0 + 30006a8: 3012a073 csrs misa,t0 + +/* Interrupt set default priority = 1*/ + li t0, 0x11111111 + 30006ac: 111112b7 lui t0,0x11111 + 30006b0: 11128293 addi t0,t0,273 # 11111111 + csrw locipri0, t0 + 30006b4: bc029073 csrw 0xbc0,t0 + csrw locipri1, t0 + 30006b8: bc129073 csrw 0xbc1,t0 + csrw locipri2, t0 + 30006bc: bc229073 csrw 0xbc2,t0 + csrw locipri3, t0 + 30006c0: bc329073 csrw 0xbc3,t0 + csrw locipri4, t0 + 30006c4: bc429073 csrw 0xbc4,t0 + csrw locipri5, t0 + 30006c8: bc529073 csrw 0xbc5,t0 + csrw locipri6, t0 + 30006cc: bc629073 csrw 0xbc6,t0 + csrw locipri7, t0 + 30006d0: bc729073 csrw 0xbc7,t0 + csrw locipri8, t0 + 30006d4: bc829073 csrw 0xbc8,t0 + csrw locipri9, t0 + 30006d8: bc929073 csrw 0xbc9,t0 + csrw locipri10, t0 + 30006dc: bca29073 csrw 0xbca,t0 + csrw locipri11, t0 + 30006e0: bcb29073 csrw 0xbcb,t0 + csrw locipri12, t0 + 30006e4: bcc29073 csrw 0xbcc,t0 + csrw locipri13, t0 + 30006e8: bcd29073 csrw 0xbcd,t0 + csrw locipri14, t0 + 30006ec: bce29073 csrw 0xbce,t0 + csrw locipri15, t0 + 30006f0: bcf29073 csrw 0xbcf,t0 + + ecall + 30006f4: 00000073 ecall + jal Chip_Init + 30006f8: 014000ef jal ra,300070c + +/* jump to C func. */ + jal main + 30006fc: 36d060ef jal ra,3007268
+ +03000700 : + +dead_loop: + j dead_loop + 3000700: 0000006f j 3000700 + +Disassembly of section .text: + +03000704 : + * @brief Chip Init Fail Process, deadloop if Chip Init fail + * @param None + * @retval None + */ +static inline void Chip_InitFail(void) +{ + 3000704: 1141 addi sp,sp,-16 + 3000706: c622 sw s0,12(sp) + 3000708: 0800 addi s0,sp,16 + while (1) { + 300070a: a001 j 300070a + +0300070c : + * @brief Chip Init + * @param None + * @retval None + */ +void Chip_Init(void) +{ + 300070c: 1101 addi sp,sp,-32 + 300070e: ce06 sw ra,28(sp) + 3000710: cc22 sw s0,24(sp) + 3000712: 1000 addi s0,sp,32 + CRG_CoreClkSelect coreClkSelect; + /* Config CRG */ + if (CRG_Config(&coreClkSelect) != BASE_STATUS_OK) { + 3000714: fec40793 addi a5,s0,-20 + 3000718: 853e mv a0,a5 + 300071a: 3e2070ef jal ra,3007afc + 300071e: 87aa mv a5,a0 + 3000720: c391 beqz a5,3000724 + Chip_InitFail(); + 3000722: 37cd jal ra,3000704 + } + + /* Config FLASH Clock */ + FLASH_ClockConfig(coreClkSelect); + 3000724: fec42783 lw a5,-20(s0) + 3000728: 853e mv a0,a5 + 300072a: 792000ef jal ra,3000ebc + SYSTICK_Init(); + 300072e: 053000ef jal ra,3000f80 + /* Set CoreClock Select after FLASH Config Done */ + CRG_SetCoreClockSelect(coreClkSelect); + 3000732: fec42783 lw a5,-20(s0) + 3000736: 853e mv a0,a5 + 3000738: 25b1 jal ra,3000d84 + + IRQ_Init(); + 300073a: 479000ef jal ra,30013b2 + ANAVREF_Init(); + 300073e: 23e5 jal ra,3000d26 + ANATRIM_Entry(); + 3000740: 2b51 jal ra,3000cd4 + /* User Add Code Here */ + 3000742: 0001 nop + 3000744: 40f2 lw ra,28(sp) + 3000746: 4462 lw s0,24(sp) + 3000748: 6105 addi sp,sp,32 + 300074a: 8082 ret + +0300074c : + * @brief Calculate the conversion gain of the tsensor. + * @param data, original data. + * @retval None + */ +static void CalculateGain(unsigned int data) +{ + 300074c: 1101 addi sp,sp,-32 + 300074e: ce22 sw s0,28(sp) + 3000750: 1000 addi s0,sp,32 + 3000752: fea42623 sw a0,-20(s0) + g_tsensorGain = ((float)(data) / 10000000.0f); + 3000756: fec42783 lw a5,-20(s0) + 300075a: d017f753 fcvt.s.wu fa4,a5 + 300075e: 030087b7 lui a5,0x3008 + 3000762: 6c47a787 flw fa5,1732(a5) # 30086c4 <__rodata_start> + 3000766: 18f777d3 fdiv.s fa5,fa4,fa5 + 300076a: 040007b7 lui a5,0x4000 + 300076e: 02f7a027 fsw fa5,32(a5) # 4000020 +} + 3000772: 0001 nop + 3000774: 4472 lw s0,28(sp) + 3000776: 6105 addi sp,sp,32 + 3000778: 8082 ret + +0300077a : + * @brief Obtains the chip ID. + * @param None + * @retval None + */ +static bool CHIP_GetInfo(void) +{ + 300077a: 7179 addi sp,sp,-48 + 300077c: d606 sw ra,44(sp) + 300077e: d422 sw s0,40(sp) + 3000780: 1800 addi s0,sp,48 + FOTP_INFO_RGN0_NUMBER_4 emptyData; + FOTP_INFO_RGN0_NUMBER_2 idData; + FOTP_InfoGet(FOTP_INFO_RNG0, 4U, (void *)&emptyData.comData); /* 4 is the number of fotp_empty_flag in otp */ + 3000782: fe040793 addi a5,s0,-32 + 3000786: 863e mv a2,a5 + 3000788: 4591 li a1,4 + 300078a: 4501 li a0,0 + 300078c: 2391 jal ra,3000cd0 + FOTP_InfoGet(FOTP_INFO_RNG0, 2U, (void *)&idData.comData); /* 2 is the number of idData in otp */ + 300078e: fd040793 addi a5,s0,-48 + 3000792: 863e mv a2,a5 + 3000794: 4589 li a1,2 + 3000796: 4501 li a0,0 + 3000798: 2b25 jal ra,3000cd0 + if (emptyData.REG.fotp_empty_flag != 0x5AA59669 || idData.REG.chip_id == 0xFFFFFFFF) { + 300079a: fe042703 lw a4,-32(s0) + 300079e: 5aa597b7 lui a5,0x5aa59 + 30007a2: 66978793 addi a5,a5,1641 # 5aa59669 + 30007a6: 00f71763 bne a4,a5,30007b4 + 30007aa: fd042703 lw a4,-48(s0) + 30007ae: 57fd li a5,-1 + 30007b0: 00f71463 bne a4,a5,30007b8 + return false; + 30007b4: 4781 li a5,0 + 30007b6: a011 j 30007ba + } + return true; + 30007b8: 4785 li a5,1 +} + 30007ba: 853e mv a0,a5 + 30007bc: 50b2 lw ra,44(sp) + 30007be: 5422 lw s0,40(sp) + 30007c0: 6145 addi sp,sp,48 + 30007c2: 8082 ret + +030007c4 : + * @brief Analog module trim. + * @param None + * @retval None + */ +static void CHIP_AnalogTrim(void) +{ + 30007c4: 711d addi sp,sp,-96 + 30007c6: ce86 sw ra,92(sp) + 30007c8: cca2 sw s0,88(sp) + 30007ca: 1080 addi s0,sp,96 + FOTP_INFO_RGN0_NUMBER_20 trimData20; + FOTP_InfoGet(FOTP_INFO_RNG0, 20U, (void *)&trimData20.comData); /* 20 is the number of trim data in otp */ + 30007cc: fdc40793 addi a5,s0,-36 + 30007d0: 863e mv a2,a5 + 30007d2: 45d1 li a1,20 + 30007d4: 4501 li a0,0 + 30007d6: 29ed jal ra,3000cd0 + /* VREF */ + VREF->VREF_TRIM0.BIT.da_iref_trim = trimData20.REG.data0.da_iref_trim; + 30007d8: 18100737 lui a4,0x18100 + 30007dc: fdc42783 lw a5,-36(s0) + 30007e0: 83c1 srli a5,a5,0x10 + 30007e2: 9bfd andi a5,a5,-1 + 30007e4: 0ff7f693 andi a3,a5,255 + 30007e8: 433c lw a5,64(a4) + 30007ea: 0ff6f693 andi a3,a3,255 + 30007ee: f007f793 andi a5,a5,-256 + 30007f2: 8fd5 or a5,a5,a3 + 30007f4: c33c sw a5,64(a4) + VREF->VREF_TRIM0.BIT.da_ref_vref_trim = trimData20.REG.data0.da_ref_vref_trim; + 30007f6: 18100737 lui a4,0x18100 + 30007fa: fdc42783 lw a5,-36(s0) + 30007fe: 83a1 srli a5,a5,0x8 + 3000800: 9bfd andi a5,a5,-1 + 3000802: 0ff7f693 andi a3,a5,255 + 3000806: 433c lw a5,64(a4) + 3000808: 0ff6f693 andi a3,a3,255 + 300080c: 06a2 slli a3,a3,0x8 + 300080e: 7641 lui a2,0xffff0 + 3000810: 0ff60613 addi a2,a2,255 # ffff00ff + 3000814: 8ff1 and a5,a5,a2 + 3000816: 8fd5 or a5,a5,a3 + 3000818: c33c sw a5,64(a4) + VREF->VREF_TRIM0.BIT.da_ref_vbg_trim = trimData20.REG.data0.da_ref_vbg_trim; + 300081a: 18100737 lui a4,0x18100 + 300081e: fdc42783 lw a5,-36(s0) + 3000822: 0ff7f693 andi a3,a5,255 + 3000826: 433c lw a5,64(a4) + 3000828: 0ff6f693 andi a3,a3,255 + 300082c: 06c2 slli a3,a3,0x10 + 300082e: ff010637 lui a2,0xff010 + 3000832: 167d addi a2,a2,-1 # ff00ffff + 3000834: 8ff1 and a5,a5,a2 + 3000836: 8fd5 or a5,a5,a3 + 3000838: c33c sw a5,64(a4) + unsigned int value = trimData20.REG.data1.da_ref_temp_trim3; + 300083a: fe042783 lw a5,-32(s0) + 300083e: 83c1 srli a5,a5,0x10 + 3000840: 9bfd andi a5,a5,-1 + 3000842: 9f81 uxtb a5 + 3000844: fef42623 sw a5,-20(s0) + value |= (trimData20.REG.data1.da_ref_temp_trim2 << 8U); /* Shift left by 8 bits */ + 3000848: fe042783 lw a5,-32(s0) + 300084c: 83a1 srli a5,a5,0x8 + 300084e: 9bfd andi a5,a5,-1 + 3000850: 9f81 uxtb a5 + 3000852: 07a2 slli a5,a5,0x8 + 3000854: 873e mv a4,a5 + 3000856: fec42783 lw a5,-20(s0) + 300085a: 8fd9 or a5,a5,a4 + 300085c: fef42623 sw a5,-20(s0) + value |= (trimData20.REG.data1.da_ref_temp_trim1 << 16U); /* Shift left by 16 bits */ + 3000860: fe042783 lw a5,-32(s0) + 3000864: 9f81 uxtb a5 + 3000866: 07c2 slli a5,a5,0x10 + 3000868: 873e mv a4,a5 + 300086a: fec42783 lw a5,-20(s0) + 300086e: 8fd9 or a5,a5,a4 + 3000870: fef42623 sw a5,-20(s0) + value |= (trimData20.REG.data0.da_ref_temp_trim0 << 24U); /* Shift left by 24 bits */ + 3000874: fdc42783 lw a5,-36(s0) + 3000878: 83e1 srli a5,a5,0x18 + 300087a: 9f81 uxtb a5 + 300087c: 07e2 slli a5,a5,0x18 + 300087e: 873e mv a4,a5 + 3000880: fec42783 lw a5,-20(s0) + 3000884: 8fd9 or a5,a5,a4 + 3000886: fef42623 sw a5,-20(s0) + VREF->VREF_TRIM1.reg = value; + 300088a: 181007b7 lui a5,0x18100 + 300088e: fec42703 lw a4,-20(s0) + 3000892: c3f8 sw a4,68(a5) + + FOTP_INFO_RGN0_NUMBER_21 trimData21; + FOTP_InfoGet(FOTP_INFO_RNG0, 21U, (void *)&trimData21.comData); /* 21 is the number of trim data in otp */ + 3000894: fcc40793 addi a5,s0,-52 + 3000898: 863e mv a2,a5 + 300089a: 45d5 li a1,21 + 300089c: 4501 li a0,0 + 300089e: 290d jal ra,3000cd0 + /* ADC */ + ADC0->ADC_OEGE_TRIM.BIT.cfg_gain_cali_trim = trimData21.REG.data1.saradc_gain; + 30008a0: 18000737 lui a4,0x18000 + 30008a4: fd042783 lw a5,-48(s0) + 30008a8: 86be mv a3,a5 + 30008aa: 6789 lui a5,0x2 + 30008ac: 17fd addi a5,a5,-1 # 1fff + 30008ae: 8ff5 and a5,a5,a3 + 30008b0: 01079613 slli a2,a5,0x10 + 30008b4: 8241 srli a2,a2,0x10 + 30008b6: 6785 lui a5,0x1 + 30008b8: 973e add a4,a4,a5 + 30008ba: 80872783 lw a5,-2040(a4) # 17fff808 + 30008be: 6689 lui a3,0x2 + 30008c0: 16fd addi a3,a3,-1 # 1fff + 30008c2: 8ef1 and a3,a3,a2 + 30008c4: 06c2 slli a3,a3,0x10 + 30008c6: e0010637 lui a2,0xe0010 + 30008ca: 167d addi a2,a2,-1 # e000ffff + 30008cc: 8ff1 and a5,a5,a2 + 30008ce: 8fd5 or a5,a5,a3 + 30008d0: 80f72423 sw a5,-2040(a4) + ADC0->ADC_OEGE_TRIM.BIT.cfg_ofst_cali_trim = trimData21.REG.data1.saradc_offset; + 30008d4: 18000737 lui a4,0x18000 + 30008d8: fd042783 lw a5,-48(s0) + 30008dc: 83c1 srli a5,a5,0x10 + 30008de: 86be mv a3,a5 + 30008e0: 6785 lui a5,0x1 + 30008e2: 17fd addi a5,a5,-1 # fff + 30008e4: 8ff5 and a5,a5,a3 + 30008e6: 01079613 slli a2,a5,0x10 + 30008ea: 8241 srli a2,a2,0x10 + 30008ec: 6785 lui a5,0x1 + 30008ee: 973e add a4,a4,a5 + 30008f0: 80872783 lw a5,-2040(a4) # 17fff808 + 30008f4: 6685 lui a3,0x1 + 30008f6: 16fd addi a3,a3,-1 # fff + 30008f8: 8ef1 and a3,a3,a2 + 30008fa: 767d lui a2,0xfffff + 30008fc: 8ff1 and a5,a5,a2 + 30008fe: 8fd5 or a5,a5,a3 + 3000900: 80f72423 sw a5,-2040(a4) + + /* TSENSOR */ + TSENSOR->TSENSOR_TRIM.reg = trimData20.REG.data1.da_ref_vptat_trim; + 3000904: fe042783 lw a5,-32(s0) + 3000908: 83e1 srli a5,a5,0x18 + 300090a: 0ff7f713 andi a4,a5,255 + 300090e: 185007b7 lui a5,0x18500 + 3000912: cb98 sw a4,16(a5) + ADC0->ADC_TSENSOR_TRIM.BIT.cfg_tsensor_ofst_trim = trimData21.REG.data2.ts_offset; + 3000914: 18000737 lui a4,0x18000 + 3000918: fd442783 lw a5,-44(s0) + 300091c: 86be mv a3,a5 + 300091e: 6785 lui a5,0x1 + 3000920: 17fd addi a5,a5,-1 # fff + 3000922: 8ff5 and a5,a5,a3 + 3000924: 01079613 slli a2,a5,0x10 + 3000928: 8241 srli a2,a2,0x10 + 300092a: 6785 lui a5,0x1 + 300092c: 973e add a4,a4,a5 + 300092e: 80472783 lw a5,-2044(a4) # 17fff804 + 3000932: 6685 lui a3,0x1 + 3000934: 16fd addi a3,a3,-1 # fff + 3000936: 8ef1 and a3,a3,a2 + 3000938: 767d lui a2,0xfffff + 300093a: 8ff1 and a5,a5,a2 + 300093c: 8fd5 or a5,a5,a3 + 300093e: 80f72223 sw a5,-2044(a4) + CalculateGain(trimData21.REG.data3.ts_gain); + 3000942: fd842783 lw a5,-40(s0) + 3000946: 83a5 srli a5,a5,0x9 + 3000948: 853e mv a0,a5 + 300094a: 3509 jal ra,300074c + + /* PGA */ + PGA0->PGA_TRIM.BIT.da_pga_vos_trim = trimData21.REG.data0.da_pga0_vos_trim; + 300094c: 18200737 lui a4,0x18200 + 3000950: fcc42783 lw a5,-52(s0) + 3000954: 1ff7f793 andi a5,a5,511 + 3000958: 01079693 slli a3,a5,0x10 + 300095c: 82c1 srli a3,a3,0x10 + 300095e: 531c lw a5,32(a4) + 3000960: 1ff6f693 andi a3,a3,511 + 3000964: e007f793 andi a5,a5,-512 + 3000968: 8fd5 or a5,a5,a3 + 300096a: d31c sw a5,32(a4) + PGA1->PGA_TRIM.BIT.da_pga_vos_trim = trimData21.REG.data0.da_pga1_vos_trim; + 300096c: 18201737 lui a4,0x18201 + 3000970: fcc42783 lw a5,-52(s0) + 3000974: 83c1 srli a5,a5,0x10 + 3000976: 1ff7f793 andi a5,a5,511 + 300097a: 01079693 slli a3,a5,0x10 + 300097e: 82c1 srli a3,a3,0x10 + 3000980: 531c lw a5,32(a4) + 3000982: 1ff6f693 andi a3,a3,511 + 3000986: e007f793 andi a5,a5,-512 + 300098a: 8fd5 or a5,a5,a3 + 300098c: d31c sw a5,32(a4) + + FOTP_INFO_RGN0_NUMBER_22 trimData22; + FOTP_InfoGet(FOTP_INFO_RNG0, 22U, (void *)&trimData22.comData); /* 22 is the number of trim data in otp */ + 300098e: fbc40793 addi a5,s0,-68 + 3000992: 863e mv a2,a5 + 3000994: 45d9 li a1,22 + 3000996: 4501 li a0,0 + 3000998: 256d jal ra,3001042 + ADC0->ADC_PGA0_OEGE_TRIM0.BIT.cfg_pga0_gain_trim2 = trimData22.REG.data0.pga0_gain2; + 300099a: 18000737 lui a4,0x18000 + 300099e: fbc42783 lw a5,-68(s0) + 30009a2: 86be mv a3,a5 + 30009a4: 6789 lui a5,0x2 + 30009a6: 17fd addi a5,a5,-1 # 1fff + 30009a8: 8ff5 and a5,a5,a3 + 30009aa: 01079613 slli a2,a5,0x10 + 30009ae: 8241 srli a2,a2,0x10 + 30009b0: 6785 lui a5,0x1 + 30009b2: 973e add a4,a4,a5 + 30009b4: 81472783 lw a5,-2028(a4) # 17fff814 + 30009b8: 6689 lui a3,0x2 + 30009ba: 16fd addi a3,a3,-1 # 1fff + 30009bc: 8ef1 and a3,a3,a2 + 30009be: 06c2 slli a3,a3,0x10 + 30009c0: e0010637 lui a2,0xe0010 + 30009c4: 167d addi a2,a2,-1 # e000ffff + 30009c6: 8ff1 and a5,a5,a2 + 30009c8: 8fd5 or a5,a5,a3 + 30009ca: 80f72a23 sw a5,-2028(a4) + ADC0->ADC_PGA0_OEGE_TRIM0.BIT.cfg_pga0_ofst_trim2 = trimData22.REG.data0.pga0_offset2; + 30009ce: 18000737 lui a4,0x18000 + 30009d2: fbc42783 lw a5,-68(s0) + 30009d6: 83c1 srli a5,a5,0x10 + 30009d8: 86be mv a3,a5 + 30009da: 6785 lui a5,0x1 + 30009dc: 17fd addi a5,a5,-1 # fff + 30009de: 8ff5 and a5,a5,a3 + 30009e0: 01079613 slli a2,a5,0x10 + 30009e4: 8241 srli a2,a2,0x10 + 30009e6: 6785 lui a5,0x1 + 30009e8: 973e add a4,a4,a5 + 30009ea: 81472783 lw a5,-2028(a4) # 17fff814 + 30009ee: 6685 lui a3,0x1 + 30009f0: 16fd addi a3,a3,-1 # fff + 30009f2: 8ef1 and a3,a3,a2 + 30009f4: 767d lui a2,0xfffff + 30009f6: 8ff1 and a5,a5,a2 + 30009f8: 8fd5 or a5,a5,a3 + 30009fa: 80f72a23 sw a5,-2028(a4) + ADC0->ADC_PGA0_OEGE_TRIM1.BIT.cfg_pga0_gain_trim4 = trimData22.REG.data1.pga0_gain4; + 30009fe: 18000737 lui a4,0x18000 + 3000a02: fc042783 lw a5,-64(s0) + 3000a06: 86be mv a3,a5 + 3000a08: 6789 lui a5,0x2 + 3000a0a: 17fd addi a5,a5,-1 # 1fff + 3000a0c: 8ff5 and a5,a5,a3 + 3000a0e: 01079613 slli a2,a5,0x10 + 3000a12: 8241 srli a2,a2,0x10 + 3000a14: 6785 lui a5,0x1 + 3000a16: 973e add a4,a4,a5 + 3000a18: 81872783 lw a5,-2024(a4) # 17fff818 + 3000a1c: 6689 lui a3,0x2 + 3000a1e: 16fd addi a3,a3,-1 # 1fff + 3000a20: 8ef1 and a3,a3,a2 + 3000a22: 06c2 slli a3,a3,0x10 + 3000a24: e0010637 lui a2,0xe0010 + 3000a28: 167d addi a2,a2,-1 # e000ffff + 3000a2a: 8ff1 and a5,a5,a2 + 3000a2c: 8fd5 or a5,a5,a3 + 3000a2e: 80f72c23 sw a5,-2024(a4) + ADC0->ADC_PGA0_OEGE_TRIM1.BIT.cfg_pga0_ofst_trim4 = trimData22.REG.data1.pga0_offset4; + 3000a32: 18000737 lui a4,0x18000 + 3000a36: fc042783 lw a5,-64(s0) + 3000a3a: 83c1 srli a5,a5,0x10 + 3000a3c: 86be mv a3,a5 + 3000a3e: 6785 lui a5,0x1 + 3000a40: 17fd addi a5,a5,-1 # fff + 3000a42: 8ff5 and a5,a5,a3 + 3000a44: 01079613 slli a2,a5,0x10 + 3000a48: 8241 srli a2,a2,0x10 + 3000a4a: 6785 lui a5,0x1 + 3000a4c: 973e add a4,a4,a5 + 3000a4e: 81872783 lw a5,-2024(a4) # 17fff818 + 3000a52: 6685 lui a3,0x1 + 3000a54: 16fd addi a3,a3,-1 # fff + 3000a56: 8ef1 and a3,a3,a2 + 3000a58: 767d lui a2,0xfffff + 3000a5a: 8ff1 and a5,a5,a2 + 3000a5c: 8fd5 or a5,a5,a3 + 3000a5e: 80f72c23 sw a5,-2024(a4) + ADC0->ADC_PGA0_OEGE_TRIM2.BIT.cfg_pga0_gain_trim8 = trimData22.REG.data2.pga0_gain8; + 3000a62: 18000737 lui a4,0x18000 + 3000a66: fc442783 lw a5,-60(s0) + 3000a6a: 86be mv a3,a5 + 3000a6c: 6789 lui a5,0x2 + 3000a6e: 17fd addi a5,a5,-1 # 1fff + 3000a70: 8ff5 and a5,a5,a3 + 3000a72: 01079613 slli a2,a5,0x10 + 3000a76: 8241 srli a2,a2,0x10 + 3000a78: 6785 lui a5,0x1 + 3000a7a: 973e add a4,a4,a5 + 3000a7c: 81c72783 lw a5,-2020(a4) # 17fff81c + 3000a80: 6689 lui a3,0x2 + 3000a82: 16fd addi a3,a3,-1 # 1fff + 3000a84: 8ef1 and a3,a3,a2 + 3000a86: 06c2 slli a3,a3,0x10 + 3000a88: e0010637 lui a2,0xe0010 + 3000a8c: 167d addi a2,a2,-1 # e000ffff + 3000a8e: 8ff1 and a5,a5,a2 + 3000a90: 8fd5 or a5,a5,a3 + 3000a92: 80f72e23 sw a5,-2020(a4) + ADC0->ADC_PGA0_OEGE_TRIM2.BIT.cfg_pga0_ofst_trim8 = trimData22.REG.data2.pga0_offset8; + 3000a96: 18000737 lui a4,0x18000 + 3000a9a: fc442783 lw a5,-60(s0) + 3000a9e: 83c1 srli a5,a5,0x10 + 3000aa0: 86be mv a3,a5 + 3000aa2: 6785 lui a5,0x1 + 3000aa4: 17fd addi a5,a5,-1 # fff + 3000aa6: 8ff5 and a5,a5,a3 + 3000aa8: 01079613 slli a2,a5,0x10 + 3000aac: 8241 srli a2,a2,0x10 + 3000aae: 6785 lui a5,0x1 + 3000ab0: 973e add a4,a4,a5 + 3000ab2: 81c72783 lw a5,-2020(a4) # 17fff81c + 3000ab6: 6685 lui a3,0x1 + 3000ab8: 16fd addi a3,a3,-1 # fff + 3000aba: 8ef1 and a3,a3,a2 + 3000abc: 767d lui a2,0xfffff + 3000abe: 8ff1 and a5,a5,a2 + 3000ac0: 8fd5 or a5,a5,a3 + 3000ac2: 80f72e23 sw a5,-2020(a4) + ADC0->ADC_PGA0_OEGE_TRIM3.BIT.cfg_pga0_gain_trim16 = trimData22.REG.data3.pga0_gain16; + 3000ac6: 18000737 lui a4,0x18000 + 3000aca: fc842783 lw a5,-56(s0) + 3000ace: 86be mv a3,a5 + 3000ad0: 6789 lui a5,0x2 + 3000ad2: 17fd addi a5,a5,-1 # 1fff + 3000ad4: 8ff5 and a5,a5,a3 + 3000ad6: 01079613 slli a2,a5,0x10 + 3000ada: 8241 srli a2,a2,0x10 + 3000adc: 6785 lui a5,0x1 + 3000ade: 973e add a4,a4,a5 + 3000ae0: 82072783 lw a5,-2016(a4) # 17fff820 + 3000ae4: 6689 lui a3,0x2 + 3000ae6: 16fd addi a3,a3,-1 # 1fff + 3000ae8: 8ef1 and a3,a3,a2 + 3000aea: 06c2 slli a3,a3,0x10 + 3000aec: e0010637 lui a2,0xe0010 + 3000af0: 167d addi a2,a2,-1 # e000ffff + 3000af2: 8ff1 and a5,a5,a2 + 3000af4: 8fd5 or a5,a5,a3 + 3000af6: 82f72023 sw a5,-2016(a4) + ADC0->ADC_PGA0_OEGE_TRIM3.BIT.cfg_pga0_ofst_trim16 = trimData22.REG.data3.pga0_offset16; + 3000afa: 18000737 lui a4,0x18000 + 3000afe: fc842783 lw a5,-56(s0) + 3000b02: 83c1 srli a5,a5,0x10 + 3000b04: 86be mv a3,a5 + 3000b06: 6785 lui a5,0x1 + 3000b08: 17fd addi a5,a5,-1 # fff + 3000b0a: 8ff5 and a5,a5,a3 + 3000b0c: 01079613 slli a2,a5,0x10 + 3000b10: 8241 srli a2,a2,0x10 + 3000b12: 6785 lui a5,0x1 + 3000b14: 973e add a4,a4,a5 + 3000b16: 82072783 lw a5,-2016(a4) # 17fff820 + 3000b1a: 6685 lui a3,0x1 + 3000b1c: 16fd addi a3,a3,-1 # fff + 3000b1e: 8ef1 and a3,a3,a2 + 3000b20: 767d lui a2,0xfffff + 3000b22: 8ff1 and a5,a5,a2 + 3000b24: 8fd5 or a5,a5,a3 + 3000b26: 82f72023 sw a5,-2016(a4) + + FOTP_INFO_RGN0_NUMBER_23 trimData23; + FOTP_InfoGet(FOTP_INFO_RNG0, 23U, (void *)&trimData23.comData); /* 23 is the number of trim data in otp */ + 3000b2a: fac40793 addi a5,s0,-84 + 3000b2e: 863e mv a2,a5 + 3000b30: 45dd li a1,23 + 3000b32: 4501 li a0,0 + 3000b34: 2339 jal ra,3001042 + ADC0->ADC_PGA1_OEGE_TRIM0.BIT.cfg_pga1_gain_trim2 = trimData23.REG.data0.pga1_gain2; + 3000b36: 18000737 lui a4,0x18000 + 3000b3a: fac42783 lw a5,-84(s0) + 3000b3e: 86be mv a3,a5 + 3000b40: 6789 lui a5,0x2 + 3000b42: 17fd addi a5,a5,-1 # 1fff + 3000b44: 8ff5 and a5,a5,a3 + 3000b46: 01079613 slli a2,a5,0x10 + 3000b4a: 8241 srli a2,a2,0x10 + 3000b4c: 6785 lui a5,0x1 + 3000b4e: 973e add a4,a4,a5 + 3000b50: 82472783 lw a5,-2012(a4) # 17fff824 + 3000b54: 6689 lui a3,0x2 + 3000b56: 16fd addi a3,a3,-1 # 1fff + 3000b58: 8ef1 and a3,a3,a2 + 3000b5a: 06c2 slli a3,a3,0x10 + 3000b5c: e0010637 lui a2,0xe0010 + 3000b60: 167d addi a2,a2,-1 # e000ffff + 3000b62: 8ff1 and a5,a5,a2 + 3000b64: 8fd5 or a5,a5,a3 + 3000b66: 82f72223 sw a5,-2012(a4) + ADC0->ADC_PGA1_OEGE_TRIM0.BIT.cfg_pga1_ofst_trim2 = trimData23.REG.data0.pga1_offset2; + 3000b6a: 18000737 lui a4,0x18000 + 3000b6e: fac42783 lw a5,-84(s0) + 3000b72: 83c1 srli a5,a5,0x10 + 3000b74: 86be mv a3,a5 + 3000b76: 6785 lui a5,0x1 + 3000b78: 17fd addi a5,a5,-1 # fff + 3000b7a: 8ff5 and a5,a5,a3 + 3000b7c: 01079613 slli a2,a5,0x10 + 3000b80: 8241 srli a2,a2,0x10 + 3000b82: 6785 lui a5,0x1 + 3000b84: 973e add a4,a4,a5 + 3000b86: 82472783 lw a5,-2012(a4) # 17fff824 + 3000b8a: 6685 lui a3,0x1 + 3000b8c: 16fd addi a3,a3,-1 # fff + 3000b8e: 8ef1 and a3,a3,a2 + 3000b90: 767d lui a2,0xfffff + 3000b92: 8ff1 and a5,a5,a2 + 3000b94: 8fd5 or a5,a5,a3 + 3000b96: 82f72223 sw a5,-2012(a4) + ADC0->ADC_PGA1_OEGE_TRIM1.BIT.cfg_pga1_gain_trim4 = trimData23.REG.data1.pga1_gain4; + 3000b9a: 18000737 lui a4,0x18000 + 3000b9e: fb042783 lw a5,-80(s0) + 3000ba2: 86be mv a3,a5 + 3000ba4: 6789 lui a5,0x2 + 3000ba6: 17fd addi a5,a5,-1 # 1fff + 3000ba8: 8ff5 and a5,a5,a3 + 3000baa: 01079613 slli a2,a5,0x10 + 3000bae: 8241 srli a2,a2,0x10 + 3000bb0: 6785 lui a5,0x1 + 3000bb2: 973e add a4,a4,a5 + 3000bb4: 82872783 lw a5,-2008(a4) # 17fff828 + 3000bb8: 6689 lui a3,0x2 + 3000bba: 16fd addi a3,a3,-1 # 1fff + 3000bbc: 8ef1 and a3,a3,a2 + 3000bbe: 06c2 slli a3,a3,0x10 + 3000bc0: e0010637 lui a2,0xe0010 + 3000bc4: 167d addi a2,a2,-1 # e000ffff + 3000bc6: 8ff1 and a5,a5,a2 + 3000bc8: 8fd5 or a5,a5,a3 + 3000bca: 82f72423 sw a5,-2008(a4) + ADC0->ADC_PGA1_OEGE_TRIM1.BIT.cfg_pga1_ofst_trim4 = trimData23.REG.data1.pga1_offset4; + 3000bce: 18000737 lui a4,0x18000 + 3000bd2: fb042783 lw a5,-80(s0) + 3000bd6: 83c1 srli a5,a5,0x10 + 3000bd8: 86be mv a3,a5 + 3000bda: 6785 lui a5,0x1 + 3000bdc: 17fd addi a5,a5,-1 # fff + 3000bde: 8ff5 and a5,a5,a3 + 3000be0: 01079613 slli a2,a5,0x10 + 3000be4: 8241 srli a2,a2,0x10 + 3000be6: 6785 lui a5,0x1 + 3000be8: 973e add a4,a4,a5 + 3000bea: 82872783 lw a5,-2008(a4) # 17fff828 + 3000bee: 6685 lui a3,0x1 + 3000bf0: 16fd addi a3,a3,-1 # fff + 3000bf2: 8ef1 and a3,a3,a2 + 3000bf4: 767d lui a2,0xfffff + 3000bf6: 8ff1 and a5,a5,a2 + 3000bf8: 8fd5 or a5,a5,a3 + 3000bfa: 82f72423 sw a5,-2008(a4) + ADC0->ADC_PGA1_OEGE_TRIM2.BIT.cfg_pga1_gain_trim8 = trimData23.REG.data2.pga1_gain8; + 3000bfe: 18000737 lui a4,0x18000 + 3000c02: fb442783 lw a5,-76(s0) + 3000c06: 86be mv a3,a5 + 3000c08: 6789 lui a5,0x2 + 3000c0a: 17fd addi a5,a5,-1 # 1fff + 3000c0c: 8ff5 and a5,a5,a3 + 3000c0e: 01079613 slli a2,a5,0x10 + 3000c12: 8241 srli a2,a2,0x10 + 3000c14: 6785 lui a5,0x1 + 3000c16: 973e add a4,a4,a5 + 3000c18: 82c72783 lw a5,-2004(a4) # 17fff82c + 3000c1c: 6689 lui a3,0x2 + 3000c1e: 16fd addi a3,a3,-1 # 1fff + 3000c20: 8ef1 and a3,a3,a2 + 3000c22: 06c2 slli a3,a3,0x10 + 3000c24: e0010637 lui a2,0xe0010 + 3000c28: 167d addi a2,a2,-1 # e000ffff + 3000c2a: 8ff1 and a5,a5,a2 + 3000c2c: 8fd5 or a5,a5,a3 + 3000c2e: 82f72623 sw a5,-2004(a4) + ADC0->ADC_PGA1_OEGE_TRIM2.BIT.cfg_pga1_ofst_trim8 = trimData23.REG.data2.pga1_offset8; + 3000c32: 18000737 lui a4,0x18000 + 3000c36: fb442783 lw a5,-76(s0) + 3000c3a: 83c1 srli a5,a5,0x10 + 3000c3c: 86be mv a3,a5 + 3000c3e: 6785 lui a5,0x1 + 3000c40: 17fd addi a5,a5,-1 # fff + 3000c42: 8ff5 and a5,a5,a3 + 3000c44: 01079613 slli a2,a5,0x10 + 3000c48: 8241 srli a2,a2,0x10 + 3000c4a: 6785 lui a5,0x1 + 3000c4c: 973e add a4,a4,a5 + 3000c4e: 82c72783 lw a5,-2004(a4) # 17fff82c + 3000c52: 6685 lui a3,0x1 + 3000c54: 16fd addi a3,a3,-1 # fff + 3000c56: 8ef1 and a3,a3,a2 + 3000c58: 767d lui a2,0xfffff + 3000c5a: 8ff1 and a5,a5,a2 + 3000c5c: 8fd5 or a5,a5,a3 + 3000c5e: 82f72623 sw a5,-2004(a4) + ADC0->ADC_PGA1_OEGE_TRIM3.BIT.cfg_pga1_gain_trim16 = trimData23.REG.data3.pga1_gain16; + 3000c62: 18000737 lui a4,0x18000 + 3000c66: fb842783 lw a5,-72(s0) + 3000c6a: 86be mv a3,a5 + 3000c6c: 6789 lui a5,0x2 + 3000c6e: 17fd addi a5,a5,-1 # 1fff + 3000c70: 8ff5 and a5,a5,a3 + 3000c72: 01079613 slli a2,a5,0x10 + 3000c76: 8241 srli a2,a2,0x10 + 3000c78: 6785 lui a5,0x1 + 3000c7a: 973e add a4,a4,a5 + 3000c7c: 83072783 lw a5,-2000(a4) # 17fff830 + 3000c80: 6689 lui a3,0x2 + 3000c82: 16fd addi a3,a3,-1 # 1fff + 3000c84: 8ef1 and a3,a3,a2 + 3000c86: 06c2 slli a3,a3,0x10 + 3000c88: e0010637 lui a2,0xe0010 + 3000c8c: 167d addi a2,a2,-1 # e000ffff + 3000c8e: 8ff1 and a5,a5,a2 + 3000c90: 8fd5 or a5,a5,a3 + 3000c92: 82f72823 sw a5,-2000(a4) + ADC0->ADC_PGA1_OEGE_TRIM3.BIT.cfg_pga1_ofst_trim16 = trimData23.REG.data3.pga1_offset16; + 3000c96: 18000737 lui a4,0x18000 + 3000c9a: fb842783 lw a5,-72(s0) + 3000c9e: 83c1 srli a5,a5,0x10 + 3000ca0: 86be mv a3,a5 + 3000ca2: 6785 lui a5,0x1 + 3000ca4: 17fd addi a5,a5,-1 # fff + 3000ca6: 8ff5 and a5,a5,a3 + 3000ca8: 01079613 slli a2,a5,0x10 + 3000cac: 8241 srli a2,a2,0x10 + 3000cae: 6785 lui a5,0x1 + 3000cb0: 973e add a4,a4,a5 + 3000cb2: 83072783 lw a5,-2000(a4) # 17fff830 + 3000cb6: 6685 lui a3,0x1 + 3000cb8: 16fd addi a3,a3,-1 # fff + 3000cba: 8ef1 and a3,a3,a2 + 3000cbc: 767d lui a2,0xfffff + 3000cbe: 8ff1 and a5,a5,a2 + 3000cc0: 8fd5 or a5,a5,a3 + 3000cc2: 82f72823 sw a5,-2000(a4) +} + 3000cc6: 0001 nop + 3000cc8: 40f6 lw ra,92(sp) + 3000cca: 4466 lw s0,88(sp) + 3000ccc: 6125 addi sp,sp,96 + 3000cce: 8082 ret + +03000cd0 : + 3000cd0: 3720006f j 3001042 + +03000cd4 : + * @brief Parameter calibration entry of the analog module. + * @param None + * @retval None + */ +void ANATRIM_Entry(void) +{ + 3000cd4: 1141 addi sp,sp,-16 + 3000cd6: c606 sw ra,12(sp) + 3000cd8: c422 sw s0,8(sp) + 3000cda: 0800 addi s0,sp,16 + if (CHIP_GetInfo() == false) { /* If the chip information is incorrect, calibration is not performed */ + 3000cdc: 3c79 jal ra,300077a + 3000cde: 87aa mv a5,a0 + 3000ce0: 0017c793 xori a5,a5,1 + 3000ce4: 9f81 uxtb a5 + 3000ce6: eb9d bnez a5,3000d1c + return; + } + HAL_CRG_IpEnableSet((void *)ADC0, IP_CLK_ENABLE); /* Enable the clock for calibration */ + 3000ce8: 4585 li a1,1 + 3000cea: 18000537 lui a0,0x18000 + 3000cee: 2849 jal ra,3000d80 + HAL_CRG_IpEnableSet((void *)PGA0, IP_CLK_ENABLE); + 3000cf0: 4585 li a1,1 + 3000cf2: 18200537 lui a0,0x18200 + 3000cf6: 2069 jal ra,3000d80 + HAL_CRG_IpEnableSet((void *)PGA1, IP_CLK_ENABLE); + 3000cf8: 4585 li a1,1 + 3000cfa: 18201537 lui a0,0x18201 + 3000cfe: 2049 jal ra,3000d80 + CHIP_AnalogTrim(); + 3000d00: 34d1 jal ra,30007c4 + HAL_CRG_IpEnableSet((void *)ADC0, IP_CLK_DISABLE); /* The clock is disabled after calibration */ + 3000d02: 4581 li a1,0 + 3000d04: 18000537 lui a0,0x18000 + 3000d08: 28a5 jal ra,3000d80 + HAL_CRG_IpEnableSet((void *)PGA0, IP_CLK_DISABLE); + 3000d0a: 4581 li a1,0 + 3000d0c: 18200537 lui a0,0x18200 + 3000d10: 2885 jal ra,3000d80 + HAL_CRG_IpEnableSet((void *)PGA1, IP_CLK_DISABLE); + 3000d12: 4581 li a1,0 + 3000d14: 18201537 lui a0,0x18201 + 3000d18: 20a5 jal ra,3000d80 + 3000d1a: a011 j 3000d1e + return; + 3000d1c: 0001 nop + 3000d1e: 40b2 lw ra,12(sp) + 3000d20: 4422 lw s0,8(sp) + 3000d22: 0141 addi sp,sp,16 + 3000d24: 8082 ret + +03000d26 : + * @brief Set Crg Core clock select + * @param None + * @retval None + */ +void ANAVREF_Init(void) +{ + 3000d26: 1141 addi sp,sp,-16 + 3000d28: c606 sw ra,12(sp) + 3000d2a: c422 sw s0,8(sp) + 3000d2c: 0800 addi s0,sp,16 + HAL_CRG_IpEnableSet(VREF_BASE, IP_CLK_ENABLE); + 3000d2e: 4585 li a1,1 + 3000d30: 18100537 lui a0,0x18100 + 3000d34: 20b1 jal ra,3000d80 + VREF->VREF_CTRL1.BIT.da_ref_temp_trim_enh = 0x1; + 3000d36: 18100737 lui a4,0x18100 + 3000d3a: 531c lw a5,32(a4) + 3000d3c: 66c1 lui a3,0x10 + 3000d3e: 8fd5 or a5,a5,a3 + 3000d40: d31c sw a5,32(a4) + VREF->VREF_CTRL0.BIT.da_ref_enh = BASE_CFG_ENABLE; + 3000d42: 18100737 lui a4,0x18100 + 3000d46: 431c lw a5,0(a4) + 3000d48: 0017e793 ori a5,a5,1 + 3000d4c: c31c sw a5,0(a4) + BASE_FUNC_DELAY_US(200); /* delay 200us */ + 3000d4e: 000f47b7 lui a5,0xf4 + 3000d52: 24078593 addi a1,a5,576 # f4240 + 3000d56: 0c800513 li a0,200 + 3000d5a: 234d jal ra,30012fc + VREF->VREF_CTRL1.BIT.da_ref_chop_enh = BASE_CFG_ENABLE; + 3000d5c: 18100737 lui a4,0x18100 + 3000d60: 531c lw a5,32(a4) + 3000d62: 0017e793 ori a5,a5,1 + 3000d66: d31c sw a5,32(a4) + BASE_FUNC_DELAY_US(40); /* delay 40us */ + 3000d68: 000f47b7 lui a5,0xf4 + 3000d6c: 24078593 addi a1,a5,576 # f4240 + 3000d70: 02800513 li a0,40 + 3000d74: 2361 jal ra,30012fc + 3000d76: 0001 nop + 3000d78: 40b2 lw ra,12(sp) + 3000d7a: 4422 lw s0,8(sp) + 3000d7c: 0141 addi sp,sp,16 + 3000d7e: 8082 ret + +03000d80 : + 3000d80: 0d10106f j 3002650 + +03000d84 : + * @brief Set Crg Core clock select + * @param coreClkSelect Input core clock select value + * @retval None + */ +void CRG_SetCoreClockSelect(CRG_CoreClkSelect coreClkSelect) +{ + 3000d84: 715d addi sp,sp,-80 + 3000d86: c686 sw ra,76(sp) + 3000d88: c4a2 sw s0,72(sp) + 3000d8a: 0880 addi s0,sp,80 + 3000d8c: faa42e23 sw a0,-68(s0) + CRG_Handle crg; + crg.baseAddress = CRG; + 3000d90: 100007b7 lui a5,0x10000 + 3000d94: fcf42423 sw a5,-56(s0) + crg.coreClkSelect = coreClkSelect; + 3000d98: fbc42783 lw a5,-68(s0) + 3000d9c: fef42023 sw a5,-32(s0) + if (crg.coreClkSelect == CRG_CORE_CLK_SELECT_TCXO) { /* If an external crystal oscillator is selected. */ + 3000da0: fe042703 lw a4,-32(s0) + 3000da4: 4785 li a5,1 + 3000da6: 00f71663 bne a4,a5,3000db2 + BASE_FUNC_DELAY_MS(10); /* 10: delay 10ms, wait clokc stable. */ + 3000daa: 3e800593 li a1,1000 + 3000dae: 4529 li a0,10 + 3000db0: 23b1 jal ra,30012fc + } + HAL_CRG_SetCoreClockSelect(&crg); + 3000db2: fc840793 addi a5,s0,-56 + 3000db6: 853e mv a0,a5 + 3000db8: 58e010ef jal ra,3002346 + 3000dbc: 0001 nop + 3000dbe: 40b6 lw ra,76(sp) + 3000dc0: 4426 lw s0,72(sp) + 3000dc2: 6161 addi sp,sp,80 + 3000dc4: 8082 ret + +03000dc6 : + * @param frequence frequnce + * @param div Output Divison + * @retval None + */ +static void SetFlashDiv(unsigned int frequency, unsigned int *nreadDiv) +{ + 3000dc6: 7179 addi sp,sp,-48 + 3000dc8: d622 sw s0,44(sp) + 3000dca: 1800 addi s0,sp,48 + 3000dcc: fca42e23 sw a0,-36(s0) + 3000dd0: fcb42c23 sw a1,-40(s0) + unsigned int div; + unsigned int freq = frequency; + 3000dd4: fdc42783 lw a5,-36(s0) + 3000dd8: fef42423 sw a5,-24(s0) + /* Get frequency divider of flash. */ + if (freq < FLASH_BASE_FREQ) { + 3000ddc: fe842703 lw a4,-24(s0) + 3000de0: 023c37b7 lui a5,0x23c3 + 3000de4: 45f78793 addi a5,a5,1119 # 23c345f + 3000de8: 00e7e863 bltu a5,a4,3000df8 + freq = FLASH_BASE_FREQ; + 3000dec: 023c37b7 lui a5,0x23c3 + 3000df0: 46078793 addi a5,a5,1120 # 23c3460 + 3000df4: fef42423 sw a5,-24(s0) + } + /* Get the flash frequency division based on the frequency. */ + if ((freq % FLASH_BASE_FREQ) == 0) { + 3000df8: fe842703 lw a4,-24(s0) + 3000dfc: 023c37b7 lui a5,0x23c3 + 3000e00: 46078793 addi a5,a5,1120 # 23c3460 + 3000e04: 02f777b3 remu a5,a4,a5 + 3000e08: ef81 bnez a5,3000e20 + div = freq / FLASH_BASE_FREQ; + 3000e0a: fe842703 lw a4,-24(s0) + 3000e0e: 023c37b7 lui a5,0x23c3 + 3000e12: 46078793 addi a5,a5,1120 # 23c3460 + 3000e16: 02f757b3 divu a5,a4,a5 + 3000e1a: fef42623 sw a5,-20(s0) + 3000e1e: a821 j 3000e36 + } else { + div = (freq / FLASH_BASE_FREQ) + 1; + 3000e20: fe842703 lw a4,-24(s0) + 3000e24: 023c37b7 lui a5,0x23c3 + 3000e28: 46078793 addi a5,a5,1120 # 23c3460 + 3000e2c: 02f757b3 divu a5,a4,a5 + 3000e30: 0785 addi a5,a5,1 + 3000e32: fef42623 sw a5,-20(s0) + } + /* Ensure the flash frequency division is valid. */ + if (div > FLASH_MAX_DIV) { + 3000e36: fec42703 lw a4,-20(s0) + 3000e3a: 4791 li a5,4 + 3000e3c: 00e7f563 bgeu a5,a4,3000e46 + div = FLASH_MAX_DIV; + 3000e40: 4791 li a5,4 + 3000e42: fef42623 sw a5,-20(s0) + } + *nreadDiv = div; + 3000e46: fd842783 lw a5,-40(s0) + 3000e4a: fec42703 lw a4,-20(s0) + 3000e4e: c398 sw a4,0(a5) +} + 3000e50: 0001 nop + 3000e52: 5432 lw s0,44(sp) + 3000e54: 6145 addi sp,sp,48 + 3000e56: 8082 ret + +03000e58 : + * @brief Get the Rounding up value + * @param coreClkSelect Core Clock select + * @retval Frequency of Flash + */ +static unsigned int GetFlashFreq(CRG_CoreClkSelect coreClkSelect) +{ + 3000e58: 7179 addi sp,sp,-48 + 3000e5a: d606 sw ra,44(sp) + 3000e5c: d422 sw s0,40(sp) + 3000e5e: 1800 addi s0,sp,48 + 3000e60: fca42e23 sw a0,-36(s0) + unsigned int hclk; + /* Get frequency of flash. */ + switch (coreClkSelect) { + 3000e64: fdc42783 lw a5,-36(s0) + 3000e68: 4705 li a4,1 + 3000e6a: 02e78063 beq a5,a4,3000e8a + 3000e6e: 4705 li a4,1 + 3000e70: 00e7e663 bltu a5,a4,3000e7c + 3000e74: 4709 li a4,2 + 3000e76: 02e78163 beq a5,a4,3000e98 + 3000e7a: a025 j 3000ea2 + case CRG_CORE_CLK_SELECT_HOSC: + hclk = HOSC_FREQ; + 3000e7c: 017d87b7 lui a5,0x17d8 + 3000e80: 84078793 addi a5,a5,-1984 # 17d7840 + 3000e84: fef42623 sw a5,-20(s0) + break; + 3000e88: a01d j 3000eae + case CRG_CORE_CLK_SELECT_TCXO: + hclk = XTRAIL_FREQ; + 3000e8a: 01c9c7b7 lui a5,0x1c9c + 3000e8e: 38078793 addi a5,a5,896 # 1c9c380 + 3000e92: fef42623 sw a5,-20(s0) + break; + 3000e96: a821 j 3000eae + case CRG_CORE_CLK_SELECT_PLL: + hclk = HAL_CRG_GetPllFreq(); + 3000e98: 5d0010ef jal ra,3002468 + 3000e9c: fea42623 sw a0,-20(s0) + break; + 3000ea0: a039 j 3000eae + default: + hclk = LOSC_FREQ; + 3000ea2: 67a1 lui a5,0x8 + 3000ea4: d0078793 addi a5,a5,-768 # 7d00 + 3000ea8: fef42623 sw a5,-20(s0) + break; + 3000eac: 0001 nop + } + return hclk; + 3000eae: fec42783 lw a5,-20(s0) +} + 3000eb2: 853e mv a0,a5 + 3000eb4: 50b2 lw ra,44(sp) + 3000eb6: 5422 lw s0,40(sp) + 3000eb8: 6145 addi sp,sp,48 + 3000eba: 8082 ret + +03000ebc : + * @brief Set flash clock frequence base on hclk + * @param coreClkSelect core clock select + * @retval None + */ +void FLASH_ClockConfig(CRG_CoreClkSelect coreClkSelect) +{ + 3000ebc: 7179 addi sp,sp,-48 + 3000ebe: d606 sw ra,44(sp) + 3000ec0: d422 sw s0,40(sp) + 3000ec2: 1800 addi s0,sp,48 + 3000ec4: fca42e23 sw a0,-36(s0) + EFC_RegStruct *efc = EFC; + 3000ec8: 147107b7 lui a5,0x14710 + 3000ecc: fef42623 sw a5,-20(s0) + EFLASH_CLK_CFG_REG cfg; + unsigned int hclk; + unsigned int nreadDiv; + + /* Step 1: Set nread_div */ + hclk = GetFlashFreq(coreClkSelect); + 3000ed0: fdc42503 lw a0,-36(s0) + 3000ed4: 3751 jal ra,3000e58 + 3000ed6: fea42423 sw a0,-24(s0) + cfg.reg = efc->EFLASH_CLK_CFG.reg; + 3000eda: fec42703 lw a4,-20(s0) + 3000ede: 6785 lui a5,0x1 + 3000ee0: 97ba add a5,a5,a4 + 3000ee2: 9407a783 lw a5,-1728(a5) # 940 + 3000ee6: fef42223 sw a5,-28(s0) + SetFlashDiv(hclk, &nreadDiv); + 3000eea: fe040793 addi a5,s0,-32 + 3000eee: 85be mv a1,a5 + 3000ef0: fe842503 lw a0,-24(s0) + 3000ef4: 3dc9 jal ra,3000dc6 + cfg.BIT.nread_div = nreadDiv; + 3000ef6: fe042783 lw a5,-32(s0) + 3000efa: 8bbd andi a5,a5,15 + 3000efc: 0ff7f713 andi a4,a5,255 + 3000f00: fe442783 lw a5,-28(s0) + 3000f04: 8b3d andi a4,a4,15 + 3000f06: 0712 slli a4,a4,0x4 + 3000f08: f0f7f793 andi a5,a5,-241 + 3000f0c: 8fd9 or a5,a5,a4 + 3000f0e: fef42223 sw a5,-28(s0) + cfg.BIT.busclk_sw_req = BASE_CFG_SET; + 3000f12: fe442783 lw a5,-28(s0) + 3000f16: 00100737 lui a4,0x100 + 3000f1a: 8fd9 or a5,a5,a4 + 3000f1c: fef42223 sw a5,-28(s0) + cfg.BIT.cur_read_vref_cal = BASE_CFG_SET; + 3000f20: fe442783 lw a5,-28(s0) + 3000f24: 00400737 lui a4,0x400 + 3000f28: 8fd9 or a5,a5,a4 + 3000f2a: fef42223 sw a5,-28(s0) + + /* Step 2: Wait Busclk_sw_req */ + cfg.BIT.cur_read_vref_cal = BASE_CFG_SET; + 3000f2e: fe442783 lw a5,-28(s0) + 3000f32: 00400737 lui a4,0x400 + 3000f36: 8fd9 or a5,a5,a4 + 3000f38: fef42223 sw a5,-28(s0) + cfg.BIT.busclk_sw_req = BASE_CFG_SET; + 3000f3c: fe442783 lw a5,-28(s0) + 3000f40: 00100737 lui a4,0x100 + 3000f44: 8fd9 or a5,a5,a4 + 3000f46: fef42223 sw a5,-28(s0) + efc->EFLASH_CLK_CFG.reg = cfg.reg; + 3000f4a: fe442703 lw a4,-28(s0) + 3000f4e: fec42683 lw a3,-20(s0) + 3000f52: 6785 lui a5,0x1 + 3000f54: 97b6 add a5,a5,a3 + 3000f56: 94e7a023 sw a4,-1728(a5) # 940 + while (efc->EFLASH_CLK_CFG.BIT.busclk_sw_req == BASE_CFG_SET) { + 3000f5a: 0001 nop + 3000f5c: fec42703 lw a4,-20(s0) + 3000f60: 6785 lui a5,0x1 + 3000f62: 97ba add a5,a5,a4 + 3000f64: 9407a783 lw a5,-1728(a5) # 940 + 3000f68: 83d1 srli a5,a5,0x14 + 3000f6a: 8b85 andi a5,a5,1 + 3000f6c: 0ff7f713 andi a4,a5,255 + 3000f70: 4785 li a5,1 + 3000f72: fef705e3 beq a4,a5,3000f5c + ; + } + 3000f76: 0001 nop + 3000f78: 50b2 lw ra,44(sp) + 3000f7a: 5422 lw s0,40(sp) + 3000f7c: 6145 addi sp,sp,48 + 3000f7e: 8082 ret + +03000f80 : + * @brief Init the systick + * @param None + * @retval None + */ +void SYSTICK_Init(void) +{ + 3000f80: 1141 addi sp,sp,-16 + 3000f82: c622 sw s0,12(sp) + 3000f84: 0800 addi s0,sp,16 + SYSTICK->TIMER_CTRL.reg = 0; + 3000f86: 143807b7 lui a5,0x14380 + 3000f8a: 0007a023 sw zero,0(a5) # 14380000 + SYSTICK->TIMER_CTRL.BIT.enable = 1; + 3000f8e: 14380737 lui a4,0x14380 + 3000f92: 431c lw a5,0(a4) + 3000f94: 0017e793 ori a5,a5,1 + 3000f98: c31c sw a5,0(a4) +} + 3000f9a: 0001 nop + 3000f9c: 4432 lw s0,12(sp) + 3000f9e: 0141 addi sp,sp,16 + 3000fa0: 8082 ret + +03000fa2 : + * @brief Get the Systick frep(Hz) + * @param None + * @retval Clock frep of systick(Hz) + */ +unsigned int SYSTICK_GetCRGHZ(void) +{ + 3000fa2: 1141 addi sp,sp,-16 + 3000fa4: c606 sw ra,12(sp) + 3000fa6: c422 sw s0,8(sp) + 3000fa8: 0800 addi s0,sp,16 + /* Get the Systick IP */ + return HAL_CRG_GetIpFreq(SYSTICK_BASE); + 3000faa: 14380537 lui a0,0x14380 + 3000fae: 5bc010ef jal ra,300256a + 3000fb2: 87aa mv a5,a0 + 3000fb4: 853e mv a0,a5 + 3000fb6: 40b2 lw ra,12(sp) + 3000fb8: 4422 lw s0,8(sp) + 3000fba: 0141 addi sp,sp,16 + 3000fbc: 8082 ret + +03000fbe : + * @param efc Flash control register base address + * @retval BASE_STATUS_ERROR fail. + * @retval BASE_STATUS_OK success. + */ +static unsigned int FOTP_CheckReadStatus(EFC_RegStruct *efc) +{ + 3000fbe: 1101 addi sp,sp,-32 + 3000fc0: ce22 sw s0,28(sp) + 3000fc2: 1000 addi s0,sp,32 + 3000fc4: fea42623 sw a0,-20(s0) + /* Check for errors in the flash reading process. */ + if (efc->INT_RAW_STATUS.BIT.int_raw_err_illegal || + 3000fc8: fec42783 lw a5,-20(s0) + 3000fcc: 1007a783 lw a5,256(a5) + 3000fd0: 83c1 srli a5,a5,0x10 + 3000fd2: 8b85 andi a5,a5,1 + 3000fd4: 9f81 uxtb a5 + 3000fd6: e38d bnez a5,3000ff8 + efc->INT_RAW_STATUS.BIT.int_raw_err_ecc_corr || + 3000fd8: fec42783 lw a5,-20(s0) + 3000fdc: 1007a783 lw a5,256(a5) + 3000fe0: 83cd srli a5,a5,0x13 + 3000fe2: 8b85 andi a5,a5,1 + 3000fe4: 9f81 uxtb a5 + if (efc->INT_RAW_STATUS.BIT.int_raw_err_illegal || + 3000fe6: eb89 bnez a5,3000ff8 + efc->INT_RAW_STATUS.BIT.int_raw_err_ecc_chk) { + 3000fe8: fec42783 lw a5,-20(s0) + 3000fec: 1007a783 lw a5,256(a5) + 3000ff0: 83d1 srli a5,a5,0x14 + 3000ff2: 8b85 andi a5,a5,1 + 3000ff4: 9f81 uxtb a5 + efc->INT_RAW_STATUS.BIT.int_raw_err_ecc_corr || + 3000ff6: c3a9 beqz a5,3001038 + efc->INT_CLEAR.BIT.int_clr_err_ecc_corr = BASE_CFG_SET; + 3000ff8: fec42703 lw a4,-20(s0) + 3000ffc: 10c72783 lw a5,268(a4) # 1438010c + 3001000: 000806b7 lui a3,0x80 + 3001004: 8fd5 or a5,a5,a3 + 3001006: 10f72623 sw a5,268(a4) + efc->INT_CLEAR.BIT.int_clr_err_illegal = BASE_CFG_SET; + 300100a: fec42703 lw a4,-20(s0) + 300100e: 10c72783 lw a5,268(a4) + 3001012: 66c1 lui a3,0x10 + 3001014: 8fd5 or a5,a5,a3 + 3001016: 10f72623 sw a5,268(a4) + efc->INT_CLEAR.BIT.int_clr_err_ecc_chk = BASE_CFG_SET; + 300101a: fec42703 lw a4,-20(s0) + 300101e: 10c72783 lw a5,268(a4) + 3001022: 001006b7 lui a3,0x100 + 3001026: 8fd5 or a5,a5,a3 + 3001028: 10f72623 sw a5,268(a4) + efc->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; + 300102c: fec42783 lw a5,-20(s0) + 3001030: 2007a023 sw zero,512(a5) + return BASE_STATUS_ERROR; + 3001034: 4785 li a5,1 + 3001036: a011 j 300103a + } + return BASE_STATUS_OK; + 3001038: 4781 li a5,0 +} + 300103a: 853e mv a0,a5 + 300103c: 4472 lw s0,28(sp) + 300103e: 6105 addi sp,sp,32 + 3001040: 8082 ret + +03001042 : + * @param buf Buffer of read data + * @retval BASE_STATUS_ERROR fail. + * @retval BASE_STATUS_OK success. + */ +unsigned int FOTP_InfoGet(FOTP_InfoRngType type, unsigned int index, FOTP_CommonData *buf) +{ + 3001042: 7179 addi sp,sp,-48 + 3001044: d606 sw ra,44(sp) + 3001046: d422 sw s0,40(sp) + 3001048: 1800 addi s0,sp,48 + 300104a: fca42e23 sw a0,-36(s0) + 300104e: fcb42c23 sw a1,-40(s0) + 3001052: fcc42a23 sw a2,-44(s0) + EFC_RegStruct *p = EFC; + 3001056: 147107b7 lui a5,0x14710 + 300105a: fef42423 sw a5,-24(s0) + unsigned int addr; + + if (buf == NULL) { + 300105e: fd442783 lw a5,-44(s0) + 3001062: e399 bnez a5,3001068 + return BASE_STATUS_ERROR; + 3001064: 4785 li a5,1 + 3001066: aa15 j 300119a + } + + if ((type >= FOTP_INFO_MAXTYPE) || (index > FOTP_INFO_REG_MAX_ID)) { + 3001068: fdc42703 lw a4,-36(s0) + 300106c: 4785 li a5,1 + 300106e: 00e7e763 bltu a5,a4,300107c + 3001072: fd842703 lw a4,-40(s0) + 3001076: 47e5 li a5,25 + 3001078: 00e7f463 bgeu a5,a4,3001080 + return BASE_STATUS_ERROR; + 300107c: 4785 li a5,1 + 300107e: aa31 j 300119a + } + + /* If there is a read command, return */ + if (p->EFLASH_CMD.BIT.cmd_start) { + 3001080: fe842783 lw a5,-24(s0) + 3001084: 439c lw a5,0(a5) + 3001086: 8b85 andi a5,a5,1 + 3001088: 9f81 uxtb a5 + 300108a: c399 beqz a5,3001090 + return BASE_STATUS_ERROR; + 300108c: 4785 li a5,1 + 300108e: a231 j 300119a + } + + p->MAGIC_LOCK = FLASH_KEY_REGISTER_UNLOCK_VALUE; + 3001090: fe842783 lw a5,-24(s0) + 3001094: fedcc737 lui a4,0xfedcc + 3001098: a9870713 addi a4,a4,-1384 # fedcba98 + 300109c: 20e7a023 sw a4,512(a5) # 14710200 + + /* Configure the read command parameters and start the read command */ + addr = (type == FOTP_INFO_RNG0) ? FOTP_INFO_RNG0_BASEADDR : FOTP_INFO_RNG1_BASEADDR; + 30010a0: fdc42783 lw a5,-36(s0) + 30010a4: e781 bnez a5,30010ac + 30010a6: 008007b7 lui a5,0x800 + 30010aa: a019 j 30010b0 + 30010ac: 008017b7 lui a5,0x801 + 30010b0: fef42223 sw a5,-28(s0) + addr += index * REG_WORDS_NUM; + 30010b4: fd842783 lw a5,-40(s0) + 30010b8: 0792 slli a5,a5,0x4 + 30010ba: fe442703 lw a4,-28(s0) + 30010be: 97ba add a5,a5,a4 + 30010c0: fef42223 sw a5,-28(s0) + p->EFLASH_ADDR.BIT.cmd_addr = addr >> 2; /* Right shift 2 bit change to word */ + 30010c4: fe442783 lw a5,-28(s0) + 30010c8: 0027d713 srli a4,a5,0x2 + 30010cc: 004007b7 lui a5,0x400 + 30010d0: 17fd addi a5,a5,-1 # 3fffff + 30010d2: 00f77633 and a2,a4,a5 + 30010d6: fe842703 lw a4,-24(s0) + 30010da: 435c lw a5,4(a4) + 30010dc: 004006b7 lui a3,0x400 + 30010e0: 16fd addi a3,a3,-1 # 3fffff + 30010e2: 8ef1 and a3,a3,a2 + 30010e4: 068a slli a3,a3,0x2 + 30010e6: ff000637 lui a2,0xff000 + 30010ea: 060d addi a2,a2,3 # ff000003 + 30010ec: 8ff1 and a5,a5,a2 + 30010ee: 8fd5 or a5,a5,a3 + 30010f0: c35c sw a5,4(a4) + p->EFLASH_CMD.BIT.cmd_code = FLASH_OPERATION_READ; + 30010f2: fe842703 lw a4,-24(s0) + 30010f6: 431c lw a5,0(a4) + 30010f8: 8ff7f793 andi a5,a5,-1793 + 30010fc: 1007e793 ori a5,a5,256 + 3001100: c31c sw a5,0(a4) + p->EFLASH_CMD.BIT.cmd_read_size = FLASH_READ_128BIT; + 3001102: fe842703 lw a4,-24(s0) + 3001106: 431c lw a5,0(a4) + 3001108: d00006b7 lui a3,0xd0000 + 300110c: 16fd addi a3,a3,-1 # cfffffff + 300110e: 8efd and a3,a3,a5 + 3001110: 100007b7 lui a5,0x10000 + 3001114: 8fd5 or a5,a5,a3 + 3001116: c31c sw a5,0(a4) + p->EFLASH_CMD.BIT.cmd_start = BASE_CFG_SET; + 3001118: fe842703 lw a4,-24(s0) + 300111c: 431c lw a5,0(a4) + 300111e: 0017e793 ori a5,a5,1 + 3001122: c31c sw a5,0(a4) + + while (p->EFLASH_CMD.BIT.cmd_start) { + 3001124: 0001 nop + 3001126: fe842783 lw a5,-24(s0) + 300112a: 439c lw a5,0(a5) + 300112c: 8b85 andi a5,a5,1 + 300112e: 9f81 uxtb a5 + 3001130: fbfd bnez a5,3001126 + ; + } + while (p->EFLASH_CMD.BIT.exec_state) { + 3001132: 0001 nop + 3001134: fe842783 lw a5,-24(s0) + 3001138: 439c lw a5,0(a5) + 300113a: 8399 srli a5,a5,0x6 + 300113c: 8b8d andi a5,a5,3 + 300113e: 9f81 uxtb a5 + 3001140: fbf5 bnez a5,3001134 + ; + } + /* read error, clear interrupt and return */ + if (FOTP_CheckReadStatus(p) != BASE_STATUS_OK) { + 3001142: fe842503 lw a0,-24(s0) + 3001146: 3da5 jal ra,3000fbe + 3001148: 87aa mv a5,a0 + 300114a: c399 beqz a5,3001150 + return BASE_STATUS_ERROR; + 300114c: 4785 li a5,1 + 300114e: a0b1 j 300119a + } + /* Read data from FIFO to buffer */ + for (unsigned int i = 0; i < sizeof(buf->data) / sizeof(buf->data[0]); ++i) { + 3001150: fe042623 sw zero,-20(s0) + 3001154: a00d j 3001176 + buf->data[i] = p->FLASH_RDATA; + 3001156: fe842783 lw a5,-24(s0) + 300115a: 6007a703 lw a4,1536(a5) # 10000600 + 300115e: fd442683 lw a3,-44(s0) + 3001162: fec42783 lw a5,-20(s0) + 3001166: 078a slli a5,a5,0x2 + 3001168: 97b6 add a5,a5,a3 + 300116a: c398 sw a4,0(a5) + for (unsigned int i = 0; i < sizeof(buf->data) / sizeof(buf->data[0]); ++i) { + 300116c: fec42783 lw a5,-20(s0) + 3001170: 0785 addi a5,a5,1 + 3001172: fef42623 sw a5,-20(s0) + 3001176: fec42703 lw a4,-20(s0) + 300117a: 478d li a5,3 + 300117c: fce7fde3 bgeu a5,a4,3001156 + } + p->INT_CLEAR.BIT.int_clr_finish = BASE_CFG_SET; + 3001180: fe842703 lw a4,-24(s0) + 3001184: 10c72783 lw a5,268(a4) + 3001188: 0107e793 ori a5,a5,16 + 300118c: 10f72623 sw a5,268(a4) + p->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; + 3001190: fe842783 lw a5,-24(s0) + 3001194: 2007a023 sw zero,512(a5) + return BASE_STATUS_OK; + 3001198: 4781 li a5,0 + 300119a: 853e mv a0,a5 + 300119c: 50b2 lw ra,44(sp) + 300119e: 5422 lw s0,40(sp) + 30011a0: 6145 addi sp,sp,48 + 30011a2: 8082 ret + +030011a4 : + * @param baseAddr The ip base address + * @retval The Address(offset) in g_crgIpMatch if match success + * @retval 0 if match fail + */ +CHIP_CrgIpMatchInfo *GetCrgIpMatchInfo(const void *baseAddr) +{ + 30011a4: 7179 addi sp,sp,-48 + 30011a6: d622 sw s0,44(sp) + 30011a8: 1800 addi s0,sp,48 + 30011aa: fca42e23 sw a0,-36(s0) + unsigned int i; + for (i = 0; i < sizeof(g_crgIpMatch) / sizeof(g_crgIpMatch[0]); ++i) { + 30011ae: fe042623 sw zero,-20(s0) + 30011b2: a081 j 30011f2 + if (baseAddr == g_crgIpMatch[i].ipBaseAddr) { + 30011b4: 030087b7 lui a5,0x3008 + 30011b8: 6c878713 addi a4,a5,1736 # 30086c8 + 30011bc: fec42683 lw a3,-20(s0) + 30011c0: 47b1 li a5,12 + 30011c2: 02f687b3 mul a5,a3,a5 + 30011c6: 97ba add a5,a5,a4 + 30011c8: 439c lw a5,0(a5) + 30011ca: fdc42703 lw a4,-36(s0) + 30011ce: 00f71d63 bne a4,a5,30011e8 + return (CHIP_CrgIpMatchInfo *)&g_crgIpMatch[i]; + 30011d2: fec42703 lw a4,-20(s0) + 30011d6: 47b1 li a5,12 + 30011d8: 02f70733 mul a4,a4,a5 + 30011dc: 030087b7 lui a5,0x3008 + 30011e0: 6c878793 addi a5,a5,1736 # 30086c8 + 30011e4: 97ba add a5,a5,a4 + 30011e6: a829 j 3001200 + for (i = 0; i < sizeof(g_crgIpMatch) / sizeof(g_crgIpMatch[0]); ++i) { + 30011e8: fec42783 lw a5,-20(s0) + 30011ec: 0785 addi a5,a5,1 + 30011ee: fef42623 sw a5,-20(s0) + 30011f2: fec42703 lw a4,-20(s0) + 30011f6: 02d00793 li a5,45 + 30011fa: fae7fde3 bgeu a5,a4,30011b4 + } + } + return (CHIP_CrgIpMatchInfo *)0; /* The base address does not match, return 0. */ + 30011fe: 4781 li a5,0 +} + 3001200: 853e mv a0,a5 + 3001202: 5432 lw s0,44(sp) + 3001204: 6145 addi sp,sp,48 + 3001206: 8082 ret + +03001208 : + * @param file Pointer to the name of the file where the error occurs. + * @param line Number of the line where the error occurs. + * @retval None. + */ +__weak void AssertErrorLog(char *file, unsigned int line) +{ + 3001208: 1101 addi sp,sp,-32 + 300120a: ce22 sw s0,28(sp) + 300120c: 1000 addi s0,sp,32 + 300120e: fea42623 sw a0,-20(s0) + 3001212: feb42423 sw a1,-24(s0) + /* Use only if the user apllication is not defined. */ + BASE_FUNC_UNUSED(file); + BASE_FUNC_UNUSED(line); + 3001216: 0001 nop + 3001218: 4472 lw s0,28(sp) + 300121a: 6105 addi sp,sp,32 + 300121c: 8082 ret + +0300121e : + * @brief Get the systick + * @param None + * @retval The SysTick Value + */ +static inline unsigned int DCL_SYSTICK_GetTick(void) +{ + 300121e: 1141 addi sp,sp,-16 + 3001220: c622 sw s0,12(sp) + 3001222: 0800 addi s0,sp,16 + return SYSTICK->MTIME; /* Systick value(Lower 32bit register) */ + 3001224: 143807b7 lui a5,0x14380 + 3001228: 479c lw a5,8(a5) +} + 300122a: 853e mv a0,a5 + 300122c: 4432 lw s0,12(sp) + 300122e: 0141 addi sp,sp,16 + 3001230: 8082 ret + +03001232 : + * @brief Delay number of us. + * @param us The number of us to delay. + * @retval None. + */ +void BASE_FUNC_DelayUs(unsigned int us) +{ + 3001232: 7179 addi sp,sp,-48 + 3001234: d606 sw ra,44(sp) + 3001236: d422 sw s0,40(sp) + 3001238: 1800 addi s0,sp,48 + 300123a: fca42e23 sw a0,-36(s0) + unsigned int preTick = DCL_SYSTICK_GetTick(); + 300123e: 37c5 jal ra,300121e + 3001240: fea42623 sw a0,-20(s0) + unsigned int tickInUs = (SYSTICK_GetCRGHZ() / CRG_FREQ_1MHz) * us; + 3001244: 3bb9 jal ra,3000fa2 + 3001246: 872a mv a4,a0 + 3001248: 000f47b7 lui a5,0xf4 + 300124c: 24078793 addi a5,a5,576 # f4240 + 3001250: 02f757b3 divu a5,a4,a5 + 3001254: fdc42703 lw a4,-36(s0) + 3001258: 02f707b3 mul a5,a4,a5 + 300125c: fef42423 sw a5,-24(s0) + unsigned int curTick; + unsigned int delta; + + /* Wait until the delta is greater than tickInUs */ + do { + curTick = DCL_SYSTICK_GetTick(); + 3001260: 3f7d jal ra,300121e + 3001262: fea42223 sw a0,-28(s0) + delta = (curTick >= preTick) ? curTick - preTick : SYSTICK_MAX_VALUE - preTick + curTick + 1; + 3001266: fe442703 lw a4,-28(s0) + 300126a: fec42783 lw a5,-20(s0) + 300126e: 40f707b3 sub a5,a4,a5 + 3001272: fef42023 sw a5,-32(s0) + } while (delta < tickInUs); + 3001276: fe042703 lw a4,-32(s0) + 300127a: fe842783 lw a5,-24(s0) + 300127e: fef761e3 bltu a4,a5,3001260 +} + 3001282: 0001 nop + 3001284: 50b2 lw ra,44(sp) + 3001286: 5422 lw s0,40(sp) + 3001288: 6145 addi sp,sp,48 + 300128a: 8082 ret + +0300128c : + * @brief Delay number of ms. + * @param ms The number of ms to delay. + * @retval None. + */ +void BASE_FUNC_DelayMs(unsigned int ms) +{ + 300128c: 7179 addi sp,sp,-48 + 300128e: d606 sw ra,44(sp) + 3001290: d422 sw s0,40(sp) + 3001292: 1800 addi s0,sp,48 + 3001294: fca42e23 sw a0,-36(s0) + for (unsigned int i = 0; i < ms; ++i) { + 3001298: fe042623 sw zero,-20(s0) + 300129c: a809 j 30012ae + BASE_FUNC_DelayUs(BASE_DEFINE_DELAY_US_IN_MS); + 300129e: 3e800513 li a0,1000 + 30012a2: 3f41 jal ra,3001232 + for (unsigned int i = 0; i < ms; ++i) { + 30012a4: fec42783 lw a5,-20(s0) + 30012a8: 0785 addi a5,a5,1 + 30012aa: fef42623 sw a5,-20(s0) + 30012ae: fec42703 lw a4,-20(s0) + 30012b2: fdc42783 lw a5,-36(s0) + 30012b6: fef764e3 bltu a4,a5,300129e + } +} + 30012ba: 0001 nop + 30012bc: 50b2 lw ra,44(sp) + 30012be: 5422 lw s0,40(sp) + 30012c0: 6145 addi sp,sp,48 + 30012c2: 8082 ret + +030012c4 : + * @brief Delay number of seconds. + * @param seconds The number of seconds to delay. + * @retval None. + */ +void BASE_FUNC_DelaySeconds(unsigned int seconds) +{ + 30012c4: 7179 addi sp,sp,-48 + 30012c6: d606 sw ra,44(sp) + 30012c8: d422 sw s0,40(sp) + 30012ca: 1800 addi s0,sp,48 + 30012cc: fca42e23 sw a0,-36(s0) + for (unsigned int i = 0; i < seconds; ++i) { + 30012d0: fe042623 sw zero,-20(s0) + 30012d4: a809 j 30012e6 + BASE_FUNC_DelayMs(BASE_DEFINE_DELAY_MS_IN_SEC); + 30012d6: 3e800513 li a0,1000 + 30012da: 3f4d jal ra,300128c + for (unsigned int i = 0; i < seconds; ++i) { + 30012dc: fec42783 lw a5,-20(s0) + 30012e0: 0785 addi a5,a5,1 + 30012e2: fef42623 sw a5,-20(s0) + 30012e6: fec42703 lw a4,-20(s0) + 30012ea: fdc42783 lw a5,-36(s0) + 30012ee: fef764e3 bltu a4,a5,30012d6 + } +} + 30012f2: 0001 nop + 30012f4: 50b2 lw ra,44(sp) + 30012f6: 5422 lw s0,40(sp) + 30012f8: 6145 addi sp,sp,48 + 30012fa: 8082 ret + +030012fc : + * @param delay The number of 'units' to delay. + * @param units Specifies the delay unit. + * @retval None. + */ +void BASE_FUNC_Delay(unsigned int delay, BASE_DelayUnit units) +{ + 30012fc: 1101 addi sp,sp,-32 + 30012fe: ce06 sw ra,28(sp) + 3001300: cc22 sw s0,24(sp) + 3001302: 1000 addi s0,sp,32 + 3001304: fea42623 sw a0,-20(s0) + 3001308: feb42423 sw a1,-24(s0) + switch (units) { + 300130c: fe842783 lw a5,-24(s0) + 3001310: 3e800713 li a4,1000 + 3001314: 02e78063 beq a5,a4,3001334 + 3001318: 000f4737 lui a4,0xf4 + 300131c: 24070713 addi a4,a4,576 # f4240 + 3001320: 00e78e63 beq a5,a4,300133c + 3001324: 4705 li a4,1 + 3001326: 00e78363 beq a5,a4,300132c + break; + case BASE_DEFINE_DELAY_MICROSECS: + BASE_FUNC_DelayUs(delay); + break; + default: + break; + 300132a: a829 j 3001344 + BASE_FUNC_DelaySeconds(delay); + 300132c: fec42503 lw a0,-20(s0) + 3001330: 3f51 jal ra,30012c4 + break; + 3001332: a809 j 3001344 + BASE_FUNC_DelayMs(delay); + 3001334: fec42503 lw a0,-20(s0) + 3001338: 3f91 jal ra,300128c + break; + 300133a: a029 j 3001344 + BASE_FUNC_DelayUs(delay); + 300133c: fec42503 lw a0,-20(s0) + 3001340: 3dcd jal ra,3001232 + break; + 3001342: 0001 nop + } + return; + 3001344: 0001 nop + 3001346: 40f2 lw ra,28(sp) + 3001348: 4462 lw s0,24(sp) + 300134a: 6105 addi sp,sp,32 + 300134c: 8082 ret + +0300134e : + * @brief Clear external interrupt + * @param irqNum external interrupt number + * @retval BASE_STATUS_OK or IRQ_ERRNO_NUM_INVALID or IRQ_ERRNO_NOT_CREATED + */ +static inline void IRQ_ClearN(unsigned int irqNum) +{ + 300134e: 1101 addi sp,sp,-32 + 3001350: ce22 sw s0,28(sp) + 3001352: 1000 addi s0,sp,32 + 3001354: fea42623 sw a0,-20(s0) + asm volatile("fence"); + 3001358: 0ff0000f fence + WRITE_CUSTOM_CSR_VAL(LOCIPCLR, irqNum); + 300135c: fec42783 lw a5,-20(s0) + 3001360: 82be mv t0,a5 + 3001362: bf029073 csrw 0xbf0,t0 +} + 3001366: 0001 nop + 3001368: 4472 lw s0,28(sp) + 300136a: 6105 addi sp,sp,32 + 300136c: 8082 ret + +0300136e : + * @brief Exception/Interrupt Handler Entry. + * @param irqNum external interrupt number. + * @retval None + */ +void InterruptEntry(unsigned int irqNum) +{ + 300136e: 1101 addi sp,sp,-32 + 3001370: ce06 sw ra,28(sp) + 3001372: cc22 sw s0,24(sp) + 3001374: 1000 addi s0,sp,32 + 3001376: fea42623 sw a0,-20(s0) + g_irqCallbackFunc[irqNum].pfnHandler(g_irqCallbackFunc[irqNum].param); + 300137a: 040007b7 lui a5,0x4000 + 300137e: 0fc78713 addi a4,a5,252 # 40000fc + 3001382: fec42783 lw a5,-20(s0) + 3001386: 078e slli a5,a5,0x3 + 3001388: 97ba add a5,a5,a4 + 300138a: 4394 lw a3,0(a5) + 300138c: 040007b7 lui a5,0x4000 + 3001390: 0fc78713 addi a4,a5,252 # 40000fc + 3001394: fec42783 lw a5,-20(s0) + 3001398: 078e slli a5,a5,0x3 + 300139a: 97ba add a5,a5,a4 + 300139c: 43dc lw a5,4(a5) + 300139e: 853e mv a0,a5 + 30013a0: 9682 jalr a3 + IRQ_ClearN(irqNum); + 30013a2: fec42503 lw a0,-20(s0) + 30013a6: 3765 jal ra,300134e +} + 30013a8: 0001 nop + 30013aa: 40f2 lw ra,28(sp) + 30013ac: 4462 lw s0,24(sp) + 30013ae: 6105 addi sp,sp,32 + 30013b0: 8082 ret + +030013b2 : + * @brief Irq initialization. + * @param none. + * @retval None + */ +void IRQ_Init(void) +{ + 30013b2: 1101 addi sp,sp,-32 + 30013b4: ce22 sw s0,28(sp) + 30013b6: 1000 addi s0,sp,32 + unsigned int index; + + for (index = 0; index < IRQ_MAX; index++) { + 30013b8: fe042623 sw zero,-20(s0) + 30013bc: a82d j 30013f6 + g_irqCallbackFunc[index].pfnHandler = IRQ_DummyHandler; + 30013be: 040007b7 lui a5,0x4000 + 30013c2: 0fc78713 addi a4,a5,252 # 40000fc + 30013c6: fec42783 lw a5,-20(s0) + 30013ca: 078e slli a5,a5,0x3 + 30013cc: 97ba add a5,a5,a4 + 30013ce: 03002737 lui a4,0x3002 + 30013d2: c5270713 addi a4,a4,-942 # 3001c52 + 30013d6: c398 sw a4,0(a5) + g_irqCallbackFunc[index].param = NULL; + 30013d8: 040007b7 lui a5,0x4000 + 30013dc: 0fc78713 addi a4,a5,252 # 40000fc + 30013e0: fec42783 lw a5,-20(s0) + 30013e4: 078e slli a5,a5,0x3 + 30013e6: 97ba add a5,a5,a4 + 30013e8: 0007a223 sw zero,4(a5) + for (index = 0; index < IRQ_MAX; index++) { + 30013ec: fec42783 lw a5,-20(s0) + 30013f0: 0785 addi a5,a5,1 + 30013f2: fef42623 sw a5,-20(s0) + 30013f6: fec42703 lw a4,-20(s0) + 30013fa: 07200793 li a5,114 + 30013fe: fce7f0e3 bgeu a5,a4,30013be + } +} + 3001402: 0001 nop + 3001404: 4472 lw s0,28(sp) + 3001406: 6105 addi sp,sp,32 + 3001408: 8082 ret + +0300140a : + * @note In the corresponding interrupt handler, manually clear the interrupt source and the corresponding interrupt + * flag bit (call the IRQ_ClearN function to clear the interrupt), otherwise the interrupt will always be + * triggered. + */ +unsigned int IRQ_Register(unsigned int irqNum, IRQ_PROC_FUNC func, void *arg) +{ + 300140a: 1101 addi sp,sp,-32 + 300140c: ce06 sw ra,28(sp) + 300140e: cc22 sw s0,24(sp) + 3001410: 1000 addi s0,sp,32 + 3001412: fea42623 sw a0,-20(s0) + 3001416: feb42423 sw a1,-24(s0) + 300141a: fec42223 sw a2,-28(s0) + INTERRUPT_ASSERT_PARAM(func != NULL); + 300141e: fe842783 lw a5,-24(s0) + 3001422: eb89 bnez a5,3001434 + 3001424: 06300593 li a1,99 + 3001428: 030097b7 lui a5,0x3009 + 300142c: 8f078513 addi a0,a5,-1808 # 30088f0 + 3001430: 3be1 jal ra,3001208 + 3001432: a001 j 3001432 + INTERRUPT_PARAM_CHECK_WITH_RET(irqNum < IRQ_MAX, IRQ_ERRNO_NUM_INVALID); + 3001434: fec42703 lw a4,-20(s0) + 3001438: 07200793 li a5,114 + 300143c: 00e7fb63 bgeu a5,a4,3001452 + 3001440: 06400593 li a1,100 + 3001444: 030097b7 lui a5,0x3009 + 3001448: 8f078513 addi a0,a5,-1808 # 30088f0 + 300144c: 3b75 jal ra,3001208 + 300144e: 4789 li a5,2 + 3001450: a81d j 3001486 + + if (g_irqCallbackFunc[irqNum].pfnHandler != IRQ_DummyHandler) { + 3001452: 040007b7 lui a5,0x4000 + 3001456: 0fc78713 addi a4,a5,252 # 40000fc + 300145a: fec42783 lw a5,-20(s0) + 300145e: 078e slli a5,a5,0x3 + 3001460: 97ba add a5,a5,a4 + 3001462: 4398 lw a4,0(a5) + 3001464: 030027b7 lui a5,0x3002 + 3001468: c5278793 addi a5,a5,-942 # 3001c52 + 300146c: 00f70463 beq a4,a5,3001474 + return IRQ_ERRNO_ALREADY_CREATED; + 3001470: 478d li a5,3 + 3001472: a811 j 3001486 + } + IRQ_SetCallBack(irqNum, func, arg); + 3001474: fe442603 lw a2,-28(s0) + 3001478: fe842583 lw a1,-24(s0) + 300147c: fec42503 lw a0,-20(s0) + 3001480: 7e4000ef jal ra,3001c64 + return BASE_STATUS_OK; + 3001484: 4781 li a5,0 +} + 3001486: 853e mv a0,a5 + 3001488: 40f2 lw ra,28(sp) + 300148a: 4462 lw s0,24(sp) + 300148c: 6105 addi sp,sp,32 + 300148e: 8082 ret + +03001490 : + * @brief Enable the specified interrupt. + * @param irqNum External interrupt number. + * @retval BASE_STATUS_OK or IRQ_ERRNO_NUM_INVALID. + */ +unsigned int IRQ_EnableN(unsigned int irqNum) +{ + 3001490: 7139 addi sp,sp,-64 + 3001492: de06 sw ra,60(sp) + 3001494: dc22 sw s0,56(sp) + 3001496: 0080 addi s0,sp,64 + 3001498: fca42623 sw a0,-52(s0) + unsigned int locienVal; +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + unsigned int priv = IRQ_GetCpuPrivilege(); +#endif + + INTERRUPT_PARAM_CHECK_WITH_RET((irqNum >= IRQ_VECTOR_CNT && irqNum < IRQ_MAX), IRQ_ERRNO_NUM_INVALID); + 300149c: fcc42703 lw a4,-52(s0) + 30014a0: 47e5 li a5,25 + 30014a2: 00e7f863 bgeu a5,a4,30014b2 + 30014a6: fcc42703 lw a4,-52(s0) + 30014aa: 07200793 li a5,114 + 30014ae: 00e7fb63 bgeu a5,a4,30014c4 + 30014b2: 0c300593 li a1,195 + 30014b6: 030097b7 lui a5,0x3009 + 30014ba: 8f078513 addi a0,a5,-1808 # 30088f0 + 30014be: 33a9 jal ra,3001208 + 30014c0: 4789 li a5,2 + 30014c2: a8cd j 30015b4 + /* The interrupt enable bits that can be controlled in the mie register (32 bits), up to 32 + can be controlled, and each bit corresponds to an interrupt enable */ + + RISCV_PRIV_MODE_SWITCH(priv); + + if (irqNum < IRQ_MIE_TOTAL_CNT) { + 30014c4: fcc42703 lw a4,-52(s0) + 30014c8: 47fd li a5,31 + 30014ca: 02e7e063 bltu a5,a4,30014ea + irqOrder = 1U << irqNum; + 30014ce: 4705 li a4,1 + 30014d0: fcc42783 lw a5,-52(s0) + 30014d4: 00f717b3 sll a5,a4,a5 + 30014d8: fef42623 sw a5,-20(s0) + SET_CSR(mie, irqOrder); + 30014dc: fec42783 lw a5,-20(s0) + 30014e0: 3047a7f3 csrrs a5,mie,a5 + 30014e4: fcf42c23 sw a5,-40(s0) + 30014e8: a0e9 j 30015b2 + } else if (irqNum < IRQ_LOCIEN1_OFFSET) { + 30014ea: fcc42703 lw a4,-52(s0) + 30014ee: 03f00793 li a5,63 + 30014f2: 02e7ef63 bltu a5,a4,3001530 + irqOrder = irqNum - IRQ_MIE_TOTAL_CNT; + 30014f6: fcc42783 lw a5,-52(s0) + 30014fa: 1781 addi a5,a5,-32 + 30014fc: fef42623 sw a5,-20(s0) + locienVal = READ_CUSTOM_CSR(LOCIEN0); + 3001500: be0027f3 csrr a5,0xbe0 + 3001504: fcf42e23 sw a5,-36(s0) + 3001508: fdc42783 lw a5,-36(s0) + 300150c: fef42223 sw a5,-28(s0) + locienVal |= (1U << irqOrder); + 3001510: 4705 li a4,1 + 3001512: fec42783 lw a5,-20(s0) + 3001516: 00f717b3 sll a5,a4,a5 + 300151a: fe442703 lw a4,-28(s0) + 300151e: 8fd9 or a5,a5,a4 + 3001520: fef42223 sw a5,-28(s0) + WRITE_CUSTOM_CSR_VAL(LOCIEN0, locienVal); + 3001524: fe442783 lw a5,-28(s0) + 3001528: 82be mv t0,a5 + 300152a: be029073 csrw 0xbe0,t0 + 300152e: a051 j 30015b2 + } else if (irqNum < IRQ_LOCIEN2_OFFSET) { + 3001530: fcc42703 lw a4,-52(s0) + 3001534: 05f00793 li a5,95 + 3001538: 04e7e063 bltu a5,a4,3001578 + irqOrder = irqNum - IRQ_LOCIEN1_OFFSET; + 300153c: fcc42783 lw a5,-52(s0) + 3001540: fc078793 addi a5,a5,-64 + 3001544: fef42623 sw a5,-20(s0) + locienVal = READ_CUSTOM_CSR(LOCIEN1); + 3001548: be1027f3 csrr a5,0xbe1 + 300154c: fef42023 sw a5,-32(s0) + 3001550: fe042783 lw a5,-32(s0) + 3001554: fef42223 sw a5,-28(s0) + locienVal |= (1U << irqOrder); + 3001558: 4705 li a4,1 + 300155a: fec42783 lw a5,-20(s0) + 300155e: 00f717b3 sll a5,a4,a5 + 3001562: fe442703 lw a4,-28(s0) + 3001566: 8fd9 or a5,a5,a4 + 3001568: fef42223 sw a5,-28(s0) + WRITE_CUSTOM_CSR_VAL(LOCIEN1, locienVal); + 300156c: fe442783 lw a5,-28(s0) + 3001570: 82be mv t0,a5 + 3001572: be129073 csrw 0xbe1,t0 + 3001576: a835 j 30015b2 + } else { + irqOrder = irqNum - IRQ_LOCIEN2_OFFSET; + 3001578: fcc42783 lw a5,-52(s0) + 300157c: fa078793 addi a5,a5,-96 + 3001580: fef42623 sw a5,-20(s0) + locienVal = READ_CUSTOM_CSR(LOCIEN2); + 3001584: be2027f3 csrr a5,0xbe2 + 3001588: fef42423 sw a5,-24(s0) + 300158c: fe842783 lw a5,-24(s0) + 3001590: fef42223 sw a5,-28(s0) + locienVal |= (1U << irqOrder); + 3001594: 4705 li a4,1 + 3001596: fec42783 lw a5,-20(s0) + 300159a: 00f717b3 sll a5,a4,a5 + 300159e: fe442703 lw a4,-28(s0) + 30015a2: 8fd9 or a5,a5,a4 + 30015a4: fef42223 sw a5,-28(s0) + WRITE_CUSTOM_CSR_VAL(LOCIEN2, locienVal); + 30015a8: fe442783 lw a5,-28(s0) + 30015ac: 82be mv t0,a5 + 30015ae: be229073 csrw 0xbe2,t0 + } + + RISCV_PRIV_MODE_SWITCH(priv); + + return BASE_STATUS_OK; + 30015b2: 4781 li a5,0 +} + 30015b4: 853e mv a0,a5 + 30015b6: 50f2 lw ra,60(sp) + 30015b8: 5462 lw s0,56(sp) + 30015ba: 6121 addi sp,sp,64 + 30015bc: 8082 ret + +030015be : + * @param context. + * @note The actual code is generated by IDE + * @retval None. + */ +__weak void SysErrPrint(const SyserrContext *context) +{ + 30015be: 1101 addi sp,sp,-32 + 30015c0: ce22 sw s0,28(sp) + 30015c2: 1000 addi s0,sp,32 + 30015c4: fea42623 sw a0,-20(s0) + BASE_FUNC_UNUSED(context); +} + 30015c8: 0001 nop + 30015ca: 4472 lw s0,28(sp) + 30015cc: 6105 addi sp,sp,32 + 30015ce: 8082 ret + +030015d0 : + * @brief System error completion processing + * @param None. + * @retval None. + */ +static void SysErrFinish(void) +{ + 30015d0: 1141 addi sp,sp,-16 + 30015d2: c622 sw s0,12(sp) + 30015d4: 0800 addi s0,sp,16 +} + 30015d6: 0001 nop + 30015d8: 4432 lw s0,12(sp) + 30015da: 0141 addi sp,sp,16 + 30015dc: 8082 ret + +030015de : + * @brief Exception Handler Entry. + * @param context error context. + * @retval None. + */ +void SysErrExcEntry(const SyserrContext *context) +{ + 30015de: 1101 addi sp,sp,-32 + 30015e0: ce06 sw ra,28(sp) + 30015e2: cc22 sw s0,24(sp) + 30015e4: 1000 addi s0,sp,32 + 30015e6: fea42623 sw a0,-20(s0) + SysErrPrint(context); + 30015ea: fec42503 lw a0,-20(s0) + 30015ee: 3fc1 jal ra,30015be + SysErrFinish(); + 30015f0: 37c5 jal ra,30015d0 +} + 30015f2: 0001 nop + 30015f4: 40f2 lw ra,28(sp) + 30015f6: 4462 lw s0,24(sp) + 30015f8: 6105 addi sp,sp,32 + 30015fa: 8082 ret + +030015fc : + * @brief NMI Interrupt Handler Entry. + * @param context error context. + * @retval None. + */ +void SysErrNmiEntry(const SyserrContext *context) +{ + 30015fc: 1101 addi sp,sp,-32 + 30015fe: ce06 sw ra,28(sp) + 3001600: cc22 sw s0,24(sp) + 3001602: 1000 addi s0,sp,32 + 3001604: fea42623 sw a0,-20(s0) + INTERRUPT_ASSERT_PARAM(context != NULL); + 3001608: fec42783 lw a5,-20(s0) + 300160c: eb89 bnez a5,300161e + 300160e: 12d00593 li a1,301 + 3001612: 030097b7 lui a5,0x3009 + 3001616: 8f078513 addi a0,a5,-1808 # 30088f0 + 300161a: 36fd jal ra,3001208 + 300161c: a001 j 300161c + SysErrPrint(context); + 300161e: fec42503 lw a0,-20(s0) + 3001622: 3f71 jal ra,30015be + SysErrFinish(); + 3001624: 3775 jal ra,30015d0 +} + 3001626: 0001 nop + 3001628: 40f2 lw ra,28(sp) + 300162a: 4462 lw s0,24(sp) + 300162c: 6105 addi sp,sp,32 + 300162e: 8082 ret + +03001630 : + * @param interPriNum Local interrupt number, which equals external interrupt number - IRQ_VECTOR_CN. + * @param prior local int prioroty. + * @retval None + */ +static void SetLocalIntNumPri(unsigned int intNum, unsigned int interPriNum, unsigned int prior) +{ + 3001630: 711d addi sp,sp,-96 + 3001632: cea2 sw s0,92(sp) + 3001634: 1080 addi s0,sp,96 + 3001636: faa42623 sw a0,-84(s0) + 300163a: fab42423 sw a1,-88(s0) + 300163e: fac42223 sw a2,-92(s0) + switch (intNum) { + 3001642: fac42783 lw a5,-84(s0) + 3001646: 17e1 addi a5,a5,-8 + 3001648: 471d li a4,7 + 300164a: 2af76363 bltu a4,a5,30018f0 + 300164e: 00279713 slli a4,a5,0x2 + 3001652: 030097b7 lui a5,0x3009 + 3001656: 91078793 addi a5,a5,-1776 # 3008910 + 300165a: 97ba add a5,a5,a4 + 300165c: 439c lw a5,0(a5) + 300165e: 8782 jr a5 + case 8: /* GROUP8 */ + SET_LOCAL_INTER_NUM_PRI(8, interPriNum, prior); + 3001660: bc8027f3 csrr a5,0xbc8 + 3001664: faf42a23 sw a5,-76(s0) + 3001668: fb442783 lw a5,-76(s0) + 300166c: faf42823 sw a5,-80(s0) + 3001670: fa842783 lw a5,-88(s0) + 3001674: 078a slli a5,a5,0x2 + 3001676: 8bf1 andi a5,a5,28 + 3001678: 473d li a4,15 + 300167a: 00f717b3 sll a5,a4,a5 + 300167e: fff7c793 not a5,a5 + 3001682: fb042703 lw a4,-80(s0) + 3001686: 8ff9 and a5,a5,a4 + 3001688: faf42823 sw a5,-80(s0) + 300168c: fa842783 lw a5,-88(s0) + 3001690: 078a slli a5,a5,0x2 + 3001692: 8bf1 andi a5,a5,28 + 3001694: fa442703 lw a4,-92(s0) + 3001698: 00f717b3 sll a5,a4,a5 + 300169c: fb042703 lw a4,-80(s0) + 30016a0: 8fd9 or a5,a5,a4 + 30016a2: faf42823 sw a5,-80(s0) + 30016a6: fb042783 lw a5,-80(s0) + 30016aa: 82be mv t0,a5 + 30016ac: bc829073 csrw 0xbc8,t0 + break; + 30016b0: a489 j 30018f2 + case 9: /* GROUP9 */ + SET_LOCAL_INTER_NUM_PRI(9, interPriNum, prior); + 30016b2: bc9027f3 csrr a5,0xbc9 + 30016b6: faf42e23 sw a5,-68(s0) + 30016ba: fbc42783 lw a5,-68(s0) + 30016be: faf42c23 sw a5,-72(s0) + 30016c2: fa842783 lw a5,-88(s0) + 30016c6: 078a slli a5,a5,0x2 + 30016c8: 8bf1 andi a5,a5,28 + 30016ca: 473d li a4,15 + 30016cc: 00f717b3 sll a5,a4,a5 + 30016d0: fff7c793 not a5,a5 + 30016d4: fb842703 lw a4,-72(s0) + 30016d8: 8ff9 and a5,a5,a4 + 30016da: faf42c23 sw a5,-72(s0) + 30016de: fa842783 lw a5,-88(s0) + 30016e2: 078a slli a5,a5,0x2 + 30016e4: 8bf1 andi a5,a5,28 + 30016e6: fa442703 lw a4,-92(s0) + 30016ea: 00f717b3 sll a5,a4,a5 + 30016ee: fb842703 lw a4,-72(s0) + 30016f2: 8fd9 or a5,a5,a4 + 30016f4: faf42c23 sw a5,-72(s0) + 30016f8: fb842783 lw a5,-72(s0) + 30016fc: 82be mv t0,a5 + 30016fe: bc929073 csrw 0xbc9,t0 + break; + 3001702: aac5 j 30018f2 + case 10: /* GROUP10 */ + SET_LOCAL_INTER_NUM_PRI(10, interPriNum, prior); + 3001704: bca027f3 csrr a5,0xbca + 3001708: fcf42223 sw a5,-60(s0) + 300170c: fc442783 lw a5,-60(s0) + 3001710: fcf42023 sw a5,-64(s0) + 3001714: fa842783 lw a5,-88(s0) + 3001718: 078a slli a5,a5,0x2 + 300171a: 8bf1 andi a5,a5,28 + 300171c: 473d li a4,15 + 300171e: 00f717b3 sll a5,a4,a5 + 3001722: fff7c793 not a5,a5 + 3001726: fc042703 lw a4,-64(s0) + 300172a: 8ff9 and a5,a5,a4 + 300172c: fcf42023 sw a5,-64(s0) + 3001730: fa842783 lw a5,-88(s0) + 3001734: 078a slli a5,a5,0x2 + 3001736: 8bf1 andi a5,a5,28 + 3001738: fa442703 lw a4,-92(s0) + 300173c: 00f717b3 sll a5,a4,a5 + 3001740: fc042703 lw a4,-64(s0) + 3001744: 8fd9 or a5,a5,a4 + 3001746: fcf42023 sw a5,-64(s0) + 300174a: fc042783 lw a5,-64(s0) + 300174e: 82be mv t0,a5 + 3001750: bca29073 csrw 0xbca,t0 + break; + 3001754: aa79 j 30018f2 + case 11: /* GROUP11 */ + SET_LOCAL_INTER_NUM_PRI(11, interPriNum, prior); + 3001756: bcb027f3 csrr a5,0xbcb + 300175a: fcf42623 sw a5,-52(s0) + 300175e: fcc42783 lw a5,-52(s0) + 3001762: fcf42423 sw a5,-56(s0) + 3001766: fa842783 lw a5,-88(s0) + 300176a: 078a slli a5,a5,0x2 + 300176c: 8bf1 andi a5,a5,28 + 300176e: 473d li a4,15 + 3001770: 00f717b3 sll a5,a4,a5 + 3001774: fff7c793 not a5,a5 + 3001778: fc842703 lw a4,-56(s0) + 300177c: 8ff9 and a5,a5,a4 + 300177e: fcf42423 sw a5,-56(s0) + 3001782: fa842783 lw a5,-88(s0) + 3001786: 078a slli a5,a5,0x2 + 3001788: 8bf1 andi a5,a5,28 + 300178a: fa442703 lw a4,-92(s0) + 300178e: 00f717b3 sll a5,a4,a5 + 3001792: fc842703 lw a4,-56(s0) + 3001796: 8fd9 or a5,a5,a4 + 3001798: fcf42423 sw a5,-56(s0) + 300179c: fc842783 lw a5,-56(s0) + 30017a0: 82be mv t0,a5 + 30017a2: bcb29073 csrw 0xbcb,t0 + break; + 30017a6: a2b1 j 30018f2 + case 12: /* GROUP12 */ + SET_LOCAL_INTER_NUM_PRI(12, interPriNum, prior); + 30017a8: bcc027f3 csrr a5,0xbcc + 30017ac: fcf42a23 sw a5,-44(s0) + 30017b0: fd442783 lw a5,-44(s0) + 30017b4: fcf42823 sw a5,-48(s0) + 30017b8: fa842783 lw a5,-88(s0) + 30017bc: 078a slli a5,a5,0x2 + 30017be: 8bf1 andi a5,a5,28 + 30017c0: 473d li a4,15 + 30017c2: 00f717b3 sll a5,a4,a5 + 30017c6: fff7c793 not a5,a5 + 30017ca: fd042703 lw a4,-48(s0) + 30017ce: 8ff9 and a5,a5,a4 + 30017d0: fcf42823 sw a5,-48(s0) + 30017d4: fa842783 lw a5,-88(s0) + 30017d8: 078a slli a5,a5,0x2 + 30017da: 8bf1 andi a5,a5,28 + 30017dc: fa442703 lw a4,-92(s0) + 30017e0: 00f717b3 sll a5,a4,a5 + 30017e4: fd042703 lw a4,-48(s0) + 30017e8: 8fd9 or a5,a5,a4 + 30017ea: fcf42823 sw a5,-48(s0) + 30017ee: fd042783 lw a5,-48(s0) + 30017f2: 82be mv t0,a5 + 30017f4: bcc29073 csrw 0xbcc,t0 + break; + 30017f8: a8ed j 30018f2 + case 13: /* GROUP13 */ + SET_LOCAL_INTER_NUM_PRI(13, interPriNum, prior); + 30017fa: bcd027f3 csrr a5,0xbcd + 30017fe: fcf42e23 sw a5,-36(s0) + 3001802: fdc42783 lw a5,-36(s0) + 3001806: fcf42c23 sw a5,-40(s0) + 300180a: fa842783 lw a5,-88(s0) + 300180e: 078a slli a5,a5,0x2 + 3001810: 8bf1 andi a5,a5,28 + 3001812: 473d li a4,15 + 3001814: 00f717b3 sll a5,a4,a5 + 3001818: fff7c793 not a5,a5 + 300181c: fd842703 lw a4,-40(s0) + 3001820: 8ff9 and a5,a5,a4 + 3001822: fcf42c23 sw a5,-40(s0) + 3001826: fa842783 lw a5,-88(s0) + 300182a: 078a slli a5,a5,0x2 + 300182c: 8bf1 andi a5,a5,28 + 300182e: fa442703 lw a4,-92(s0) + 3001832: 00f717b3 sll a5,a4,a5 + 3001836: fd842703 lw a4,-40(s0) + 300183a: 8fd9 or a5,a5,a4 + 300183c: fcf42c23 sw a5,-40(s0) + 3001840: fd842783 lw a5,-40(s0) + 3001844: 82be mv t0,a5 + 3001846: bcd29073 csrw 0xbcd,t0 + break; + 300184a: a065 j 30018f2 + case 14: /* GROUP14 */ + SET_LOCAL_INTER_NUM_PRI(14, interPriNum, prior); + 300184c: bce027f3 csrr a5,0xbce + 3001850: fef42223 sw a5,-28(s0) + 3001854: fe442783 lw a5,-28(s0) + 3001858: fef42023 sw a5,-32(s0) + 300185c: fa842783 lw a5,-88(s0) + 3001860: 078a slli a5,a5,0x2 + 3001862: 8bf1 andi a5,a5,28 + 3001864: 473d li a4,15 + 3001866: 00f717b3 sll a5,a4,a5 + 300186a: fff7c793 not a5,a5 + 300186e: fe042703 lw a4,-32(s0) + 3001872: 8ff9 and a5,a5,a4 + 3001874: fef42023 sw a5,-32(s0) + 3001878: fa842783 lw a5,-88(s0) + 300187c: 078a slli a5,a5,0x2 + 300187e: 8bf1 andi a5,a5,28 + 3001880: fa442703 lw a4,-92(s0) + 3001884: 00f717b3 sll a5,a4,a5 + 3001888: fe042703 lw a4,-32(s0) + 300188c: 8fd9 or a5,a5,a4 + 300188e: fef42023 sw a5,-32(s0) + 3001892: fe042783 lw a5,-32(s0) + 3001896: 82be mv t0,a5 + 3001898: bce29073 csrw 0xbce,t0 + break; + 300189c: a899 j 30018f2 + case 15: /* GROUP15 */ + SET_LOCAL_INTER_NUM_PRI(15, interPriNum, prior); + 300189e: bcf027f3 csrr a5,0xbcf + 30018a2: fef42623 sw a5,-20(s0) + 30018a6: fec42783 lw a5,-20(s0) + 30018aa: fef42423 sw a5,-24(s0) + 30018ae: fa842783 lw a5,-88(s0) + 30018b2: 078a slli a5,a5,0x2 + 30018b4: 8bf1 andi a5,a5,28 + 30018b6: 473d li a4,15 + 30018b8: 00f717b3 sll a5,a4,a5 + 30018bc: fff7c793 not a5,a5 + 30018c0: fe842703 lw a4,-24(s0) + 30018c4: 8ff9 and a5,a5,a4 + 30018c6: fef42423 sw a5,-24(s0) + 30018ca: fa842783 lw a5,-88(s0) + 30018ce: 078a slli a5,a5,0x2 + 30018d0: 8bf1 andi a5,a5,28 + 30018d2: fa442703 lw a4,-92(s0) + 30018d6: 00f717b3 sll a5,a4,a5 + 30018da: fe842703 lw a4,-24(s0) + 30018de: 8fd9 or a5,a5,a4 + 30018e0: fef42423 sw a5,-24(s0) + 30018e4: fe842783 lw a5,-24(s0) + 30018e8: 82be mv t0,a5 + 30018ea: bcf29073 csrw 0xbcf,t0 + break; + 30018ee: a011 j 30018f2 + default: + break; + 30018f0: 0001 nop + } +} + 30018f2: 0001 nop + 30018f4: 4476 lw s0,92(sp) + 30018f6: 6125 addi sp,sp,96 + 30018f8: 8082 ret + +030018fa : + * @param interPriNum Local interrupt number, which equals external interrupt number - IRQ_VECTOR_CN. + * @param prior Priority of this local interrupt to be set. + * @retval None. + */ +static void IRQ_SetLocalPriority(unsigned int interPriNum, unsigned int prior) +{ + 30018fa: 7159 addi sp,sp,-112 + 30018fc: d686 sw ra,108(sp) + 30018fe: d4a2 sw s0,104(sp) + 3001900: 1880 addi s0,sp,112 + 3001902: f8a42e23 sw a0,-100(s0) + 3001906: f8b42c23 sw a1,-104(s0) +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + unsigned int priv = IRQ_GetCpuPrivilege(); +#endif + RISCV_PRIV_MODE_SWITCH(priv); + unsigned int intNum = GET_LOCAL_INTER_CONFIGREG_NUM(interPriNum); + 300190a: f9c42783 lw a5,-100(s0) + 300190e: 838d srli a5,a5,0x3 + 3001910: fef42623 sw a5,-20(s0) + switch (intNum) { + 3001914: fec42703 lw a4,-20(s0) + 3001918: 479d li a5,7 + 300191a: 2ae7e563 bltu a5,a4,3001bc4 + 300191e: fec42783 lw a5,-20(s0) + 3001922: 00279713 slli a4,a5,0x2 + 3001926: 030097b7 lui a5,0x3009 + 300192a: 93078793 addi a5,a5,-1744 # 3008930 + 300192e: 97ba add a5,a5,a4 + 3001930: 439c lw a5,0(a5) + 3001932: 8782 jr a5 + case 0: /* GROUP0 */ + SET_LOCAL_INTER_NUM_PRI(0, interPriNum, prior); + 3001934: bc0027f3 csrr a5,0xbc0 + 3001938: faf42823 sw a5,-80(s0) + 300193c: fb042783 lw a5,-80(s0) + 3001940: faf42623 sw a5,-84(s0) + 3001944: f9c42783 lw a5,-100(s0) + 3001948: 078a slli a5,a5,0x2 + 300194a: 8bf1 andi a5,a5,28 + 300194c: 473d li a4,15 + 300194e: 00f717b3 sll a5,a4,a5 + 3001952: fff7c793 not a5,a5 + 3001956: fac42703 lw a4,-84(s0) + 300195a: 8ff9 and a5,a5,a4 + 300195c: faf42623 sw a5,-84(s0) + 3001960: f9c42783 lw a5,-100(s0) + 3001964: 078a slli a5,a5,0x2 + 3001966: 8bf1 andi a5,a5,28 + 3001968: f9842703 lw a4,-104(s0) + 300196c: 00f717b3 sll a5,a4,a5 + 3001970: fac42703 lw a4,-84(s0) + 3001974: 8fd9 or a5,a5,a4 + 3001976: faf42623 sw a5,-84(s0) + 300197a: fac42783 lw a5,-84(s0) + 300197e: 82be mv t0,a5 + 3001980: bc029073 csrw 0xbc0,t0 + break; + 3001984: ac81 j 3001bd4 + case 1: /* GROUP1 */ + SET_LOCAL_INTER_NUM_PRI(1, interPriNum, prior); + 3001986: bc1027f3 csrr a5,0xbc1 + 300198a: faf42c23 sw a5,-72(s0) + 300198e: fb842783 lw a5,-72(s0) + 3001992: faf42a23 sw a5,-76(s0) + 3001996: f9c42783 lw a5,-100(s0) + 300199a: 078a slli a5,a5,0x2 + 300199c: 8bf1 andi a5,a5,28 + 300199e: 473d li a4,15 + 30019a0: 00f717b3 sll a5,a4,a5 + 30019a4: fff7c793 not a5,a5 + 30019a8: fb442703 lw a4,-76(s0) + 30019ac: 8ff9 and a5,a5,a4 + 30019ae: faf42a23 sw a5,-76(s0) + 30019b2: f9c42783 lw a5,-100(s0) + 30019b6: 078a slli a5,a5,0x2 + 30019b8: 8bf1 andi a5,a5,28 + 30019ba: f9842703 lw a4,-104(s0) + 30019be: 00f717b3 sll a5,a4,a5 + 30019c2: fb442703 lw a4,-76(s0) + 30019c6: 8fd9 or a5,a5,a4 + 30019c8: faf42a23 sw a5,-76(s0) + 30019cc: fb442783 lw a5,-76(s0) + 30019d0: 82be mv t0,a5 + 30019d2: bc129073 csrw 0xbc1,t0 + break; + 30019d6: aafd j 3001bd4 + case 2: /* GROUP2 */ + SET_LOCAL_INTER_NUM_PRI(2, interPriNum, prior); + 30019d8: bc2027f3 csrr a5,0xbc2 + 30019dc: fcf42023 sw a5,-64(s0) + 30019e0: fc042783 lw a5,-64(s0) + 30019e4: faf42e23 sw a5,-68(s0) + 30019e8: f9c42783 lw a5,-100(s0) + 30019ec: 078a slli a5,a5,0x2 + 30019ee: 8bf1 andi a5,a5,28 + 30019f0: 473d li a4,15 + 30019f2: 00f717b3 sll a5,a4,a5 + 30019f6: fff7c793 not a5,a5 + 30019fa: fbc42703 lw a4,-68(s0) + 30019fe: 8ff9 and a5,a5,a4 + 3001a00: faf42e23 sw a5,-68(s0) + 3001a04: f9c42783 lw a5,-100(s0) + 3001a08: 078a slli a5,a5,0x2 + 3001a0a: 8bf1 andi a5,a5,28 + 3001a0c: f9842703 lw a4,-104(s0) + 3001a10: 00f717b3 sll a5,a4,a5 + 3001a14: fbc42703 lw a4,-68(s0) + 3001a18: 8fd9 or a5,a5,a4 + 3001a1a: faf42e23 sw a5,-68(s0) + 3001a1e: fbc42783 lw a5,-68(s0) + 3001a22: 82be mv t0,a5 + 3001a24: bc229073 csrw 0xbc2,t0 + break; + 3001a28: a275 j 3001bd4 + case 3: /* GROUP3 */ + SET_LOCAL_INTER_NUM_PRI(3, interPriNum, prior); + 3001a2a: bc3027f3 csrr a5,0xbc3 + 3001a2e: fcf42423 sw a5,-56(s0) + 3001a32: fc842783 lw a5,-56(s0) + 3001a36: fcf42223 sw a5,-60(s0) + 3001a3a: f9c42783 lw a5,-100(s0) + 3001a3e: 078a slli a5,a5,0x2 + 3001a40: 8bf1 andi a5,a5,28 + 3001a42: 473d li a4,15 + 3001a44: 00f717b3 sll a5,a4,a5 + 3001a48: fff7c793 not a5,a5 + 3001a4c: fc442703 lw a4,-60(s0) + 3001a50: 8ff9 and a5,a5,a4 + 3001a52: fcf42223 sw a5,-60(s0) + 3001a56: f9c42783 lw a5,-100(s0) + 3001a5a: 078a slli a5,a5,0x2 + 3001a5c: 8bf1 andi a5,a5,28 + 3001a5e: f9842703 lw a4,-104(s0) + 3001a62: 00f717b3 sll a5,a4,a5 + 3001a66: fc442703 lw a4,-60(s0) + 3001a6a: 8fd9 or a5,a5,a4 + 3001a6c: fcf42223 sw a5,-60(s0) + 3001a70: fc442783 lw a5,-60(s0) + 3001a74: 82be mv t0,a5 + 3001a76: bc329073 csrw 0xbc3,t0 + break; + 3001a7a: aaa9 j 3001bd4 + case 4: /* GROUP4 */ + SET_LOCAL_INTER_NUM_PRI(4, interPriNum, prior); + 3001a7c: bc4027f3 csrr a5,0xbc4 + 3001a80: fcf42823 sw a5,-48(s0) + 3001a84: fd042783 lw a5,-48(s0) + 3001a88: fcf42623 sw a5,-52(s0) + 3001a8c: f9c42783 lw a5,-100(s0) + 3001a90: 078a slli a5,a5,0x2 + 3001a92: 8bf1 andi a5,a5,28 + 3001a94: 473d li a4,15 + 3001a96: 00f717b3 sll a5,a4,a5 + 3001a9a: fff7c793 not a5,a5 + 3001a9e: fcc42703 lw a4,-52(s0) + 3001aa2: 8ff9 and a5,a5,a4 + 3001aa4: fcf42623 sw a5,-52(s0) + 3001aa8: f9c42783 lw a5,-100(s0) + 3001aac: 078a slli a5,a5,0x2 + 3001aae: 8bf1 andi a5,a5,28 + 3001ab0: f9842703 lw a4,-104(s0) + 3001ab4: 00f717b3 sll a5,a4,a5 + 3001ab8: fcc42703 lw a4,-52(s0) + 3001abc: 8fd9 or a5,a5,a4 + 3001abe: fcf42623 sw a5,-52(s0) + 3001ac2: fcc42783 lw a5,-52(s0) + 3001ac6: 82be mv t0,a5 + 3001ac8: bc429073 csrw 0xbc4,t0 + break; + 3001acc: a221 j 3001bd4 + case 5: /* GROUP5 */ + SET_LOCAL_INTER_NUM_PRI(5, interPriNum, prior); + 3001ace: bc5027f3 csrr a5,0xbc5 + 3001ad2: fcf42c23 sw a5,-40(s0) + 3001ad6: fd842783 lw a5,-40(s0) + 3001ada: fcf42a23 sw a5,-44(s0) + 3001ade: f9c42783 lw a5,-100(s0) + 3001ae2: 078a slli a5,a5,0x2 + 3001ae4: 8bf1 andi a5,a5,28 + 3001ae6: 473d li a4,15 + 3001ae8: 00f717b3 sll a5,a4,a5 + 3001aec: fff7c793 not a5,a5 + 3001af0: fd442703 lw a4,-44(s0) + 3001af4: 8ff9 and a5,a5,a4 + 3001af6: fcf42a23 sw a5,-44(s0) + 3001afa: f9c42783 lw a5,-100(s0) + 3001afe: 078a slli a5,a5,0x2 + 3001b00: 8bf1 andi a5,a5,28 + 3001b02: f9842703 lw a4,-104(s0) + 3001b06: 00f717b3 sll a5,a4,a5 + 3001b0a: fd442703 lw a4,-44(s0) + 3001b0e: 8fd9 or a5,a5,a4 + 3001b10: fcf42a23 sw a5,-44(s0) + 3001b14: fd442783 lw a5,-44(s0) + 3001b18: 82be mv t0,a5 + 3001b1a: bc529073 csrw 0xbc5,t0 + break; + 3001b1e: a85d j 3001bd4 + case 6: /* GROUP6 */ + SET_LOCAL_INTER_NUM_PRI(6, interPriNum, prior); + 3001b20: bc6027f3 csrr a5,0xbc6 + 3001b24: fef42023 sw a5,-32(s0) + 3001b28: fe042783 lw a5,-32(s0) + 3001b2c: fcf42e23 sw a5,-36(s0) + 3001b30: f9c42783 lw a5,-100(s0) + 3001b34: 078a slli a5,a5,0x2 + 3001b36: 8bf1 andi a5,a5,28 + 3001b38: 473d li a4,15 + 3001b3a: 00f717b3 sll a5,a4,a5 + 3001b3e: fff7c793 not a5,a5 + 3001b42: fdc42703 lw a4,-36(s0) + 3001b46: 8ff9 and a5,a5,a4 + 3001b48: fcf42e23 sw a5,-36(s0) + 3001b4c: f9c42783 lw a5,-100(s0) + 3001b50: 078a slli a5,a5,0x2 + 3001b52: 8bf1 andi a5,a5,28 + 3001b54: f9842703 lw a4,-104(s0) + 3001b58: 00f717b3 sll a5,a4,a5 + 3001b5c: fdc42703 lw a4,-36(s0) + 3001b60: 8fd9 or a5,a5,a4 + 3001b62: fcf42e23 sw a5,-36(s0) + 3001b66: fdc42783 lw a5,-36(s0) + 3001b6a: 82be mv t0,a5 + 3001b6c: bc629073 csrw 0xbc6,t0 + break; + 3001b70: a095 j 3001bd4 + case 7: /* GROUP7 */ + SET_LOCAL_INTER_NUM_PRI(7, interPriNum, prior); + 3001b72: bc7027f3 csrr a5,0xbc7 + 3001b76: fef42423 sw a5,-24(s0) + 3001b7a: fe842783 lw a5,-24(s0) + 3001b7e: fef42223 sw a5,-28(s0) + 3001b82: f9c42783 lw a5,-100(s0) + 3001b86: 078a slli a5,a5,0x2 + 3001b88: 8bf1 andi a5,a5,28 + 3001b8a: 473d li a4,15 + 3001b8c: 00f717b3 sll a5,a4,a5 + 3001b90: fff7c793 not a5,a5 + 3001b94: fe442703 lw a4,-28(s0) + 3001b98: 8ff9 and a5,a5,a4 + 3001b9a: fef42223 sw a5,-28(s0) + 3001b9e: f9c42783 lw a5,-100(s0) + 3001ba2: 078a slli a5,a5,0x2 + 3001ba4: 8bf1 andi a5,a5,28 + 3001ba6: f9842703 lw a4,-104(s0) + 3001baa: 00f717b3 sll a5,a4,a5 + 3001bae: fe442703 lw a4,-28(s0) + 3001bb2: 8fd9 or a5,a5,a4 + 3001bb4: fef42223 sw a5,-28(s0) + 3001bb8: fe442783 lw a5,-28(s0) + 3001bbc: 82be mv t0,a5 + 3001bbe: bc729073 csrw 0xbc7,t0 + break; + 3001bc2: a809 j 3001bd4 + default: + SetLocalIntNumPri(intNum, interPriNum, prior); + 3001bc4: f9842603 lw a2,-104(s0) + 3001bc8: f9c42583 lw a1,-100(s0) + 3001bcc: fec42503 lw a0,-20(s0) + 3001bd0: 3485 jal ra,3001630 + break; + 3001bd2: 0001 nop + } + RISCV_PRIV_MODE_SWITCH(priv); +} + 3001bd4: 0001 nop + 3001bd6: 50b6 lw ra,108(sp) + 3001bd8: 5426 lw s0,104(sp) + 3001bda: 6165 addi sp,sp,112 + 3001bdc: 8082 ret + +03001bde : + * @param irqNum External interrupt number. + * @param priority. + * @retval IRQ_ERRNO_NUM_INVALID or IRQ_ERRNO_PRIORITY_INVALID or BASE_STATUS_OK. + */ +unsigned int IRQ_SetPriority(unsigned int irqNum, unsigned int priority) +{ + 3001bde: 1101 addi sp,sp,-32 + 3001be0: ce06 sw ra,28(sp) + 3001be2: cc22 sw s0,24(sp) + 3001be4: 1000 addi s0,sp,32 + 3001be6: fea42623 sw a0,-20(s0) + 3001bea: feb42423 sw a1,-24(s0) + INTERRUPT_PARAM_CHECK_WITH_RET((irqNum >= IRQ_VECTOR_CNT && irqNum < IRQ_MAX), IRQ_ERRNO_NUM_INVALID); + 3001bee: fec42703 lw a4,-20(s0) + 3001bf2: 47e5 li a5,25 + 3001bf4: 00e7f863 bgeu a5,a4,3001c04 + 3001bf8: fec42703 lw a4,-20(s0) + 3001bfc: 07200793 li a5,114 + 3001c00: 00e7fb63 bgeu a5,a4,3001c16 + 3001c04: 18c00593 li a1,396 + 3001c08: 030097b7 lui a5,0x3009 + 3001c0c: 8f078513 addi a0,a5,-1808 # 30088f0 + 3001c10: 21bd jal ra,300207e + 3001c12: 4789 li a5,2 + 3001c14: a815 j 3001c48 + INTERRUPT_PARAM_CHECK_WITH_RET((priority >= IRQ_PRIO_LOWEST && priority <= IRQ_PRIO_HIGHEST), \ + 3001c16: fe842783 lw a5,-24(s0) + 3001c1a: c791 beqz a5,3001c26 + 3001c1c: fe842703 lw a4,-24(s0) + 3001c20: 47bd li a5,15 + 3001c22: 00e7fb63 bgeu a5,a4,3001c38 + 3001c26: 18d00593 li a1,397 + 3001c2a: 030097b7 lui a5,0x3009 + 3001c2e: 8f078513 addi a0,a5,-1808 # 30088f0 + 3001c32: 21b1 jal ra,300207e + 3001c34: 4795 li a5,5 + 3001c36: a809 j 3001c48 + IRQ_ERRNO_PRIORITY_INVALID); + + /* The locipri register is specifically used to configure the priority of the + external non-standard interrupts of the CPU, so the number of internal + standard interrupts should be subtracted */ + IRQ_SetLocalPriority(irqNum - IRQ_VECTOR_CNT, priority); + 3001c38: fec42783 lw a5,-20(s0) + 3001c3c: 1799 addi a5,a5,-26 + 3001c3e: fe842583 lw a1,-24(s0) + 3001c42: 853e mv a0,a5 + 3001c44: 395d jal ra,30018fa + + return BASE_STATUS_OK; + 3001c46: 4781 li a5,0 +} + 3001c48: 853e mv a0,a5 + 3001c4a: 40f2 lw ra,28(sp) + 3001c4c: 4462 lw s0,24(sp) + 3001c4e: 6105 addi sp,sp,32 + 3001c50: 8082 ret + +03001c52 : + * @brief Interrupt dummy handler + * @param arg Not used + * @retval None. + */ +static void IRQ_DummyHandler(void *arg) +{ + 3001c52: 1101 addi sp,sp,-32 + 3001c54: ce22 sw s0,28(sp) + 3001c56: 1000 addi s0,sp,32 + 3001c58: fea42623 sw a0,-20(s0) + BASE_FUNC_UNUSED(arg); +} + 3001c5c: 0001 nop + 3001c5e: 4472 lw s0,28(sp) + 3001c60: 6105 addi sp,sp,32 + 3001c62: 8082 ret + +03001c64 : + * @param func callback function + * @param arg callback arg + * @retval None. + */ +static inline void IRQ_SetCallBack(unsigned int irqNum, IRQ_PROC_FUNC func, void *arg) +{ + 3001c64: 1101 addi sp,sp,-32 + 3001c66: ce22 sw s0,28(sp) + 3001c68: 1000 addi s0,sp,32 + 3001c6a: fea42623 sw a0,-20(s0) + 3001c6e: feb42423 sw a1,-24(s0) + 3001c72: fec42223 sw a2,-28(s0) + g_irqCallbackFunc[irqNum].param = arg; + 3001c76: 040007b7 lui a5,0x4000 + 3001c7a: 0fc78713 addi a4,a5,252 # 40000fc + 3001c7e: fec42783 lw a5,-20(s0) + 3001c82: 078e slli a5,a5,0x3 + 3001c84: 97ba add a5,a5,a4 + 3001c86: fe442703 lw a4,-28(s0) + 3001c8a: c3d8 sw a4,4(a5) + g_irqCallbackFunc[irqNum].pfnHandler = func; + 3001c8c: 040007b7 lui a5,0x4000 + 3001c90: 0fc78713 addi a4,a5,252 # 40000fc + 3001c94: fec42783 lw a5,-20(s0) + 3001c98: 078e slli a5,a5,0x3 + 3001c9a: 97ba add a5,a5,a4 + 3001c9c: fe842703 lw a4,-24(s0) + 3001ca0: c398 sw a4,0(a5) +} + 3001ca2: 0001 nop + 3001ca4: 4472 lw s0,28(sp) + 3001ca6: 6105 addi sp,sp,32 + 3001ca8: 8082 ret + +03001caa : + * @brief Set the write protection for CRG-related registers disable. + * @param None + * @retval None. + */ +static inline void DCL_SYSCTRL_CrgWriteProtectionDisable(void) +{ + 3001caa: 1141 addi sp,sp,-16 + 3001cac: c622 sw s0,12(sp) + 3001cae: 0800 addi s0,sp,16 + /* Set the corresponding bit without affecting the other bits and set the high 16 bits to EA51 to write to. */ + SYSCTRL0->SC_LOCKEN.reg = (SYSCTRL0->SC_LOCKEN.reg & SC_LOCKEN_CRG_DISABLE_MASK) + SC_LOCKEN_VALID_HIGH_BIT; + 3001cb0: 101007b7 lui a5,0x10100 + 3001cb4: 43f8 lw a4,68(a5) + 3001cb6: 67c1 lui a5,0x10 + 3001cb8: 17f9 addi a5,a5,-2 # fffe + 3001cba: 00f776b3 and a3,a4,a5 + 3001cbe: 101007b7 lui a5,0x10100 + 3001cc2: ea510737 lui a4,0xea510 + 3001cc6: 9736 add a4,a4,a3 + 3001cc8: c3f8 sw a4,68(a5) +} + 3001cca: 0001 nop + 3001ccc: 4432 lw s0,12(sp) + 3001cce: 0141 addi sp,sp,16 + 3001cd0: 8082 ret + +03001cd2 : + * @brief Set the Set the write protection for CRG-related registers enable. + * @param None + * @retval None. + */ +static inline void DCL_SYSCTRL_CrgWriteProtectionEnable(void) +{ + 3001cd2: 1141 addi sp,sp,-16 + 3001cd4: c622 sw s0,12(sp) + 3001cd6: 0800 addi s0,sp,16 + /* Set the corresponding bit without affecting the other bits and set the high 16 bits to EA51 to write to. */ + SYSCTRL0->SC_LOCKEN.reg = ((SYSCTRL0->SC_LOCKEN.reg & SC_LOW_BIT_MASK) | SC_LOCKEN_CRG_ENABLE_MASK) + + 3001cd8: 101007b7 lui a5,0x10100 + 3001cdc: 43f8 lw a4,68(a5) + 3001cde: 67c1 lui a5,0x10 + 3001ce0: 17fd addi a5,a5,-1 # ffff + 3001ce2: 8ff9 and a5,a5,a4 + 3001ce4: 0017e693 ori a3,a5,1 + 3001ce8: 101007b7 lui a5,0x10100 + 3001cec: ea510737 lui a4,0xea510 + 3001cf0: 9736 add a4,a4,a3 + 3001cf2: c3f8 sw a4,68(a5) + SC_LOCKEN_VALID_HIGH_BIT; +} + 3001cf4: 0001 nop + 3001cf6: 4432 lw s0,12(sp) + 3001cf8: 0141 addi sp,sp,16 + 3001cfa: 8082 ret + +03001cfc : + * @param clkSelect pll_ref_cksel + * @retval true + * @retval false + */ +static inline bool IsCrgPllRefClkSelect(CRG_PllRefClkSelect clkSelect) +{ + 3001cfc: 1101 addi sp,sp,-32 + 3001cfe: ce22 sw s0,28(sp) + 3001d00: 1000 addi s0,sp,32 + 3001d02: fea42623 sw a0,-20(s0) + return ((clkSelect == CRG_PLL_REF_CLK_SELECT_HOSC) || + 3001d06: fec42783 lw a5,-20(s0) + 3001d0a: c791 beqz a5,3001d16 + 3001d0c: fec42703 lw a4,-20(s0) + 3001d10: 4785 li a5,1 + 3001d12: 00f71463 bne a4,a5,3001d1a + 3001d16: 4785 li a5,1 + 3001d18: a011 j 3001d1c + 3001d1a: 4781 li a5,0 + 3001d1c: 8b85 andi a5,a5,1 + 3001d1e: 9f81 uxtb a5 + (clkSelect == CRG_PLL_REF_CLK_SELECT_XTAL)); +} + 3001d20: 853e mv a0,a5 + 3001d22: 4472 lw s0,28(sp) + 3001d24: 6105 addi sp,sp,32 + 3001d26: 8082 ret + +03001d28 : + * @param preDiv pll prediv value + * @retval true + * @retval false + */ +static inline bool IsCrgPllPreDiv(CRG_PllPreDiv preDiv) +{ + 3001d28: 1101 addi sp,sp,-32 + 3001d2a: ce22 sw s0,28(sp) + 3001d2c: 1000 addi s0,sp,32 + 3001d2e: fea42623 sw a0,-20(s0) + return ((preDiv >= CRG_PLL_PREDIV_1) && + 3001d32: fec42783 lw a5,-20(s0) + 3001d36: 0087b793 sltiu a5,a5,8 + 3001d3a: 9f81 uxtb a5 + (preDiv <= CRG_PLL_PREDIV_8)); +} + 3001d3c: 853e mv a0,a5 + 3001d3e: 4472 lw s0,28(sp) + 3001d40: 6105 addi sp,sp,32 + 3001d42: 8082 ret + +03001d44 : + * @param postDiv pll_postdiv value + * @retval true + * @retval false + */ +static inline bool IsCrgPllPostDiv(CRG_PllPostDiv postDiv) +{ + 3001d44: 1101 addi sp,sp,-32 + 3001d46: ce22 sw s0,28(sp) + 3001d48: 1000 addi s0,sp,32 + 3001d4a: fea42623 sw a0,-20(s0) + return ((postDiv >= CRG_PLL_POSTDIV_1) && + 3001d4e: fec42783 lw a5,-20(s0) + 3001d52: 0087b793 sltiu a5,a5,8 + 3001d56: 9f81 uxtb a5 + (postDiv <= CRG_PLL_POSTDIV_8)); +} + 3001d58: 853e mv a0,a5 + 3001d5a: 4472 lw s0,28(sp) + 3001d5c: 6105 addi sp,sp,32 + 3001d5e: 8082 ret + +03001d60 : + * @param postDiv pll_postdiv2 value + * @retval true + * @retval false + */ +static inline bool IsCrgPllPostDiv2(CRG_PllPostDiv2 postDiv) +{ + 3001d60: 1101 addi sp,sp,-32 + 3001d62: ce22 sw s0,28(sp) + 3001d64: 1000 addi s0,sp,32 + 3001d66: fea42623 sw a0,-20(s0) + return ((postDiv >= CRG_PLL_POSTDIV2_1) && + 3001d6a: fec42783 lw a5,-20(s0) + 3001d6e: 0087b793 sltiu a5,a5,8 + 3001d72: 9f81 uxtb a5 + (postDiv <= CRG_PLL_POSTDIV2_8_MAX)); +} + 3001d74: 853e mv a0,a5 + 3001d76: 4472 lw s0,28(sp) + 3001d78: 6105 addi sp,sp,32 + 3001d7a: 8082 ret + +03001d7c : + * @param fbDiv pll fbdiv value + * @retval true + * @retval false + */ +static inline bool IsCrgPllFbDiv(unsigned int fbDiv) +{ + 3001d7c: 1101 addi sp,sp,-32 + 3001d7e: ce22 sw s0,28(sp) + 3001d80: 1000 addi s0,sp,32 + 3001d82: fea42623 sw a0,-20(s0) + return (fbDiv <= CRG_PLL_FBDIV_MAX); + 3001d86: fec42783 lw a5,-20(s0) + 3001d8a: 0807b793 sltiu a5,a5,128 + 3001d8e: 9f81 uxtb a5 +} + 3001d90: 853e mv a0,a5 + 3001d92: 4472 lw s0,28(sp) + 3001d94: 6105 addi sp,sp,32 + 3001d96: 8082 ret + +03001d98 : + * @param select core_cksel value + * @retval true + * @retval false + */ +static inline bool IsCrgCoreCkSel(CRG_CoreClkSelect select) +{ + 3001d98: 1101 addi sp,sp,-32 + 3001d9a: ce22 sw s0,28(sp) + 3001d9c: 1000 addi s0,sp,32 + 3001d9e: fea42623 sw a0,-20(s0) + return ((select == CRG_CORE_CLK_SELECT_HOSC) || + (select == CRG_CORE_CLK_SELECT_TCXO) || + 3001da2: fec42783 lw a5,-20(s0) + 3001da6: cb99 beqz a5,3001dbc + return ((select == CRG_CORE_CLK_SELECT_HOSC) || + 3001da8: fec42703 lw a4,-20(s0) + 3001dac: 4785 li a5,1 + 3001dae: 00f70763 beq a4,a5,3001dbc + (select == CRG_CORE_CLK_SELECT_TCXO) || + 3001db2: fec42703 lw a4,-20(s0) + 3001db6: 4789 li a5,2 + 3001db8: 00f71463 bne a4,a5,3001dc0 + 3001dbc: 4785 li a5,1 + 3001dbe: a011 j 3001dc2 + 3001dc0: 4781 li a5,0 + 3001dc2: 8b85 andi a5,a5,1 + 3001dc4: 9f81 uxtb a5 + (select == CRG_CORE_CLK_SELECT_PLL)); +} + 3001dc6: 853e mv a0,a5 + 3001dc8: 4472 lw s0,28(sp) + 3001dca: 6105 addi sp,sp,32 + 3001dcc: 8082 ret + +03001dce : + * @param select 1M clock selection + * @retval true + * @retval false + */ +static inline bool IsCrg1MCkSel(CRG_1MClkSelect select) +{ + 3001dce: 1101 addi sp,sp,-32 + 3001dd0: ce22 sw s0,28(sp) + 3001dd2: 1000 addi s0,sp,32 + 3001dd4: fea42623 sw a0,-20(s0) + return ((select == CRG_1M_CLK_SELECT_HOSC) || + 3001dd8: fec42783 lw a5,-20(s0) + 3001ddc: c791 beqz a5,3001de8 + 3001dde: fec42703 lw a4,-20(s0) + 3001de2: 4785 li a5,1 + 3001de4: 00f71463 bne a4,a5,3001dec + 3001de8: 4785 li a5,1 + 3001dea: a011 j 3001dee + 3001dec: 4781 li a5,0 + 3001dee: 8b85 andi a5,a5,1 + 3001df0: 9f81 uxtb a5 + (select == CRG_1M_CLK_SELECT_TCXO)); +} + 3001df2: 853e mv a0,a5 + 3001df4: 4472 lw s0,28(sp) + 3001df6: 6105 addi sp,sp,32 + 3001df8: 8082 ret + +03001dfa : + * @param div 1M clock ratio + * @retval true + * @retval false + */ +static inline bool IsCrg1MCkDiv(unsigned int div) +{ + 3001dfa: 1101 addi sp,sp,-32 + 3001dfc: ce22 sw s0,28(sp) + 3001dfe: 1000 addi s0,sp,32 + 3001e00: fea42623 sw a0,-20(s0) + return (div <= CRG_1MHZ_CLK_MAX_DIV); + 3001e04: fec42783 lw a5,-20(s0) + 3001e08: 0407b793 sltiu a5,a5,64 + 3001e0c: 9f81 uxtb a5 +} + 3001e0e: 853e mv a0,a5 + 3001e10: 4472 lw s0,28(sp) + 3001e12: 6105 addi sp,sp,32 + 3001e14: 8082 ret + +03001e16 : + * @param preDiv PLL Previous Divsion + * @retval true + * @retval false + */ +static inline bool IsCrgValidPreDiv(unsigned int pllRefFreq, unsigned int preDiv) +{ + 3001e16: 7179 addi sp,sp,-48 + 3001e18: d622 sw s0,44(sp) + 3001e1a: 1800 addi s0,sp,48 + 3001e1c: fca42e23 sw a0,-36(s0) + 3001e20: fcb42c23 sw a1,-40(s0) + unsigned int freq = pllRefFreq; + 3001e24: fdc42783 lw a5,-36(s0) + 3001e28: fef42623 sw a5,-20(s0) + if (preDiv != 0) { + 3001e2c: fd842783 lw a5,-40(s0) + 3001e30: cb89 beqz a5,3001e42 + freq /= preDiv; + 3001e32: fec42703 lw a4,-20(s0) + 3001e36: fd842783 lw a5,-40(s0) + 3001e3a: 02f757b3 divu a5,a4,a5 + 3001e3e: fef42623 sw a5,-20(s0) + } + return (freq >= CRG_CLK_PFD_MIN_FREQ) && (freq <= CRG_CLK_PFD_MAX_FREQ); + 3001e42: fec42703 lw a4,-20(s0) + 3001e46: 003d17b7 lui a5,0x3d1 + 3001e4a: 8ff78793 addi a5,a5,-1793 # 3d08ff + 3001e4e: 00e7fc63 bgeu a5,a4,3001e66 + 3001e52: fec42703 lw a4,-20(s0) + 3001e56: 007277b7 lui a5,0x727 + 3001e5a: 0e078793 addi a5,a5,224 # 7270e0 + 3001e5e: 00e7e463 bltu a5,a4,3001e66 + 3001e62: 4785 li a5,1 + 3001e64: a011 j 3001e68 + 3001e66: 4781 li a5,0 + 3001e68: 8b85 andi a5,a5,1 + 3001e6a: 9f81 uxtb a5 +} + 3001e6c: 853e mv a0,a5 + 3001e6e: 5432 lw s0,44(sp) + 3001e70: 6145 addi sp,sp,48 + 3001e72: 8082 ret + +03001e74 : + * @param fdDiv PLL FD Divsion + * @retval true + * @retval false + */ +static inline bool IsCrgValidFdDiv(unsigned int clkPfdFreq, unsigned int fdDiv) +{ + 3001e74: 7179 addi sp,sp,-48 + 3001e76: d622 sw s0,44(sp) + 3001e78: 1800 addi s0,sp,48 + 3001e7a: fca42e23 sw a0,-36(s0) + 3001e7e: fcb42c23 sw a1,-40(s0) + if (clkPfdFreq > 30000000U) { /* The maximum speed of the external clock source is 30000000U. */ + 3001e82: fdc42703 lw a4,-36(s0) + 3001e86: 01c9c7b7 lui a5,0x1c9c + 3001e8a: 38078793 addi a5,a5,896 # 1c9c380 + 3001e8e: 00e7f463 bgeu a5,a4,3001e96 + return false; + 3001e92: 4781 li a5,0 + 3001e94: a08d j 3001ef6 + } else if (fdDiv > CRG_PLL_FBDIV_MAX) { + 3001e96: fd842703 lw a4,-40(s0) + 3001e9a: 07f00793 li a5,127 + 3001e9e: 00e7f463 bgeu a5,a4,3001ea6 + return false; + 3001ea2: 4781 li a5,0 + 3001ea4: a889 j 3001ef6 + } + + unsigned int freq = (fdDiv > 0x6) ? (clkPfdFreq * fdDiv) : (clkPfdFreq * 0x6); /* 0x0-0x6: divided by 0x6 */ + 3001ea6: fd842703 lw a4,-40(s0) + 3001eaa: 4799 li a5,6 + 3001eac: 00e7f963 bgeu a5,a4,3001ebe + 3001eb0: fdc42703 lw a4,-36(s0) + 3001eb4: fd842783 lw a5,-40(s0) + 3001eb8: 02f707b3 mul a5,a4,a5 + 3001ebc: a031 j 3001ec8 + 3001ebe: fdc42703 lw a4,-36(s0) + 3001ec2: 4799 li a5,6 + 3001ec4: 02f707b3 mul a5,a4,a5 + 3001ec8: fef42623 sw a5,-20(s0) + return (freq >= CRG_CLK_VCO_MIN_FREQ) && (freq <= CRG_CLK_VCO_MAX_FREQ); + 3001ecc: fec42703 lw a4,-20(s0) + 3001ed0: 05f5e7b7 lui a5,0x5f5e + 3001ed4: 0ff78793 addi a5,a5,255 # 5f5e0ff + 3001ed8: 00e7fc63 bgeu a5,a4,3001ef0 + 3001edc: fec42703 lw a4,-20(s0) + 3001ee0: 11e1a7b7 lui a5,0x11e1a + 3001ee4: 30078793 addi a5,a5,768 # 11e1a300 + 3001ee8: 00e7e463 bltu a5,a4,3001ef0 + 3001eec: 4785 li a5,1 + 3001eee: a011 j 3001ef2 + 3001ef0: 4781 li a5,0 + 3001ef2: 8b85 andi a5,a5,1 + 3001ef4: 9f81 uxtb a5 +} + 3001ef6: 853e mv a0,a5 + 3001ef8: 5432 lw s0,44(sp) + 3001efa: 6145 addi sp,sp,48 + 3001efc: 8082 ret + +03001efe : + * @param postDiv PLL Post Divsion + * @retval true + * @retval false + */ +static inline bool IsCrgValidPostDiv(unsigned int clkVcoFreq, unsigned int postDiv) +{ + 3001efe: 7179 addi sp,sp,-48 + 3001f00: d622 sw s0,44(sp) + 3001f02: 1800 addi s0,sp,48 + 3001f04: fca42e23 sw a0,-36(s0) + 3001f08: fcb42c23 sw a1,-40(s0) + unsigned int freq = clkVcoFreq; + 3001f0c: fdc42783 lw a5,-36(s0) + 3001f10: fef42623 sw a5,-20(s0) + if (postDiv != 0) { + 3001f14: fd842783 lw a5,-40(s0) + 3001f18: cb91 beqz a5,3001f2c + freq /= (postDiv + 1); + 3001f1a: fd842783 lw a5,-40(s0) + 3001f1e: 0785 addi a5,a5,1 + 3001f20: fec42703 lw a4,-20(s0) + 3001f24: 02f757b3 divu a5,a4,a5 + 3001f28: fef42623 sw a5,-20(s0) + } + return (freq <= CRG_CLK_TARGET_MAX_FREQ); + 3001f2c: fec42703 lw a4,-20(s0) + 3001f30: 08f0d7b7 lui a5,0x8f0d + 3001f34: 18178793 addi a5,a5,385 # 8f0d181 + 3001f38: 00f737b3 sltu a5,a4,a5 + 3001f3c: 9f81 uxtb a5 +} + 3001f3e: 853e mv a0,a5 + 3001f40: 5432 lw s0,44(sp) + 3001f42: 6145 addi sp,sp,48 + 3001f44: 8082 ret + +03001f46 : + * @param postDiv2 PLL Post Divsion2 + * @retval true + * @retval false + */ +static inline bool IsCrgValidPostDiv2(unsigned int clkVcoFreq, unsigned int postDiv2) +{ + 3001f46: 7179 addi sp,sp,-48 + 3001f48: d622 sw s0,44(sp) + 3001f4a: 1800 addi s0,sp,48 + 3001f4c: fca42e23 sw a0,-36(s0) + 3001f50: fcb42c23 sw a1,-40(s0) + unsigned int freq = clkVcoFreq; + 3001f54: fdc42783 lw a5,-36(s0) + 3001f58: fef42623 sw a5,-20(s0) + if (postDiv2 != 0) { + 3001f5c: fd842783 lw a5,-40(s0) + 3001f60: cb91 beqz a5,3001f74 + freq /= (postDiv2 + 1); + 3001f62: fd842783 lw a5,-40(s0) + 3001f66: 0785 addi a5,a5,1 + 3001f68: fec42703 lw a4,-20(s0) + 3001f6c: 02f757b3 divu a5,a4,a5 + 3001f70: fef42623 sw a5,-20(s0) + } + return (freq <= CRG_CLK_PST2_MAX_FREQ); + 3001f74: fec42703 lw a4,-20(s0) + 3001f78: 05f5e7b7 lui a5,0x5f5e + 3001f7c: 10178793 addi a5,a5,257 # 5f5e101 + 3001f80: 00f737b3 sltu a5,a4,a5 + 3001f84: 9f81 uxtb a5 +} + 3001f86: 853e mv a0,a5 + 3001f88: 5432 lw s0,44(sp) + 3001f8a: 6145 addi sp,sp,48 + 3001f8c: 8082 ret + +03001f8e : + * @param adcClkSelect the value of adc clock select + * @retval true + * @retval false + */ +static inline bool IsCrgAdcClkModeSelect(CRG_AdcClkSelect adcClkSelect) +{ + 3001f8e: 1101 addi sp,sp,-32 + 3001f90: ce22 sw s0,28(sp) + 3001f92: 1000 addi s0,sp,32 + 3001f94: fea42623 sw a0,-20(s0) + return (adcClkSelect == CRG_ADC_CLK_ASYN_HOSC || \ + adcClkSelect == CRG_ADC_CLK_ASYN_TCXO || \ + adcClkSelect == CRG_ADC_CLK_ASYN_PLL_DIV || \ + 3001f98: fec42783 lw a5,-20(s0) + 3001f9c: c385 beqz a5,3001fbc + return (adcClkSelect == CRG_ADC_CLK_ASYN_HOSC || \ + 3001f9e: fec42703 lw a4,-20(s0) + 3001fa2: 4785 li a5,1 + 3001fa4: 00f70c63 beq a4,a5,3001fbc + adcClkSelect == CRG_ADC_CLK_ASYN_TCXO || \ + 3001fa8: fec42703 lw a4,-20(s0) + 3001fac: 4789 li a5,2 + 3001fae: 00f70763 beq a4,a5,3001fbc + adcClkSelect == CRG_ADC_CLK_ASYN_PLL_DIV || \ + 3001fb2: fec42703 lw a4,-20(s0) + 3001fb6: 478d li a5,3 + 3001fb8: 00f71463 bne a4,a5,3001fc0 + 3001fbc: 4785 li a5,1 + 3001fbe: a011 j 3001fc2 + 3001fc0: 4781 li a5,0 + 3001fc2: 8b85 andi a5,a5,1 + 3001fc4: 9f81 uxtb a5 + adcClkSelect == CRG_ADC_CLK_SYN_CORE); +} + 3001fc6: 853e mv a0,a5 + 3001fc8: 4472 lw s0,28(sp) + 3001fca: 6105 addi sp,sp,32 + 3001fcc: 8082 ret + +03001fce : + * @param div the value of adc clock div + * @retval true + * @retval false + */ +static inline bool IsCrgAdcClkDiv(CRG_AdcDiv div) +{ + 3001fce: 1101 addi sp,sp,-32 + 3001fd0: ce22 sw s0,28(sp) + 3001fd2: 1000 addi s0,sp,32 + 3001fd4: fea42623 sw a0,-20(s0) + return (div == CRG_ADC_DIV_1 || \ + div == CRG_ADC_DIV_2 || \ + div == CRG_ADC_DIV_3 || \ + 3001fd8: fec42783 lw a5,-20(s0) + 3001fdc: c385 beqz a5,3001ffc + return (div == CRG_ADC_DIV_1 || \ + 3001fde: fec42703 lw a4,-20(s0) + 3001fe2: 4785 li a5,1 + 3001fe4: 00f70c63 beq a4,a5,3001ffc + div == CRG_ADC_DIV_2 || \ + 3001fe8: fec42703 lw a4,-20(s0) + 3001fec: 4789 li a5,2 + 3001fee: 00f70763 beq a4,a5,3001ffc + div == CRG_ADC_DIV_3 || \ + 3001ff2: fec42703 lw a4,-20(s0) + 3001ff6: 478d li a5,3 + 3001ff8: 00f71463 bne a4,a5,3002000 + 3001ffc: 4785 li a5,1 + 3001ffe: a011 j 3002002 + 3002000: 4781 li a5,0 + 3002002: 8b85 andi a5,a5,1 + 3002004: 9f81 uxtb a5 + div == CRG_ADC_DIV_4); +} + 3002006: 853e mv a0,a5 + 3002008: 4472 lw s0,28(sp) + 300200a: 6105 addi sp,sp,32 + 300200c: 8082 ret + +0300200e : + * @param clk Clock register base address + * @param select Core clock selection + * @retval None + */ +static inline void DCL_CRG_SetCoreClkSel(CRG_RegStruct *clk, CRG_CoreClkSelect select) +{ + 300200e: 1101 addi sp,sp,-32 + 3002010: ce06 sw ra,28(sp) + 3002012: cc22 sw s0,24(sp) + 3002014: 1000 addi s0,sp,32 + 3002016: fea42623 sw a0,-20(s0) + 300201a: feb42423 sw a1,-24(s0) + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + 300201e: fec42703 lw a4,-20(s0) + 3002022: 100007b7 lui a5,0x10000 + 3002026: 00f70a63 beq a4,a5,300203a + 300202a: 64b00593 li a1,1611 + 300202e: 030097b7 lui a5,0x3009 + 3002032: 95078513 addi a0,a5,-1712 # 3008950 + 3002036: 20a1 jal ra,300207e + 3002038: a001 j 3002038 + CRG_PARAM_CHECK_NO_RET(IsCrgCoreCkSel(select)); + 300203a: fe842503 lw a0,-24(s0) + 300203e: 3ba9 jal ra,3001d98 + 3002040: 87aa mv a5,a0 + 3002042: 0017c793 xori a5,a5,1 + 3002046: 9f81 uxtb a5 + 3002048: cb89 beqz a5,300205a + 300204a: 64c00593 li a1,1612 + 300204e: 030097b7 lui a5,0x3009 + 3002052: 95078513 addi a0,a5,-1712 # 3008950 + 3002056: 2025 jal ra,300207e + 3002058: a839 j 3002076 + clk->PERI_CRG64.BIT.clk_pst1_sw_sel = select; + 300205a: fe842783 lw a5,-24(s0) + 300205e: 8b8d andi a5,a5,3 + 3002060: 0ff7f693 andi a3,a5,255 + 3002064: fec42703 lw a4,-20(s0) + 3002068: 10072783 lw a5,256(a4) # ea510100 + 300206c: 8a8d andi a3,a3,3 + 300206e: 9bf1 andi a5,a5,-4 + 3002070: 8fd5 or a5,a5,a3 + 3002072: 10f72023 sw a5,256(a4) +} + 3002076: 40f2 lw ra,28(sp) + 3002078: 4462 lw s0,24(sp) + 300207a: 6105 addi sp,sp,32 + 300207c: 8082 ret + +0300207e : + 300207e: 98aff06f j 3001208 + +03002082 : + * @param handle CRG Handle + * @retval BASE_STATUS_ERROR Parameter Check fail + * @retval BASE_STATUS_OK Success + */ +BASE_StatusType HAL_CRG_Init(const CRG_Handle *handle) +{ + 3002082: 7179 addi sp,sp,-48 + 3002084: d606 sw ra,44(sp) + 3002086: d422 sw s0,40(sp) + 3002088: 1800 addi s0,sp,48 + 300208a: fca42e23 sw a0,-36(s0) + CRG_ASSERT_PARAM(handle != NULL); + 300208e: fdc42783 lw a5,-36(s0) + 3002092: eb89 bnez a5,30020a4 + 3002094: 07100593 li a1,113 + 3002098: 030097b7 lui a5,0x3009 + 300209c: 96c78513 addi a0,a5,-1684 # 300896c + 30020a0: 3ff9 jal ra,300207e + 30020a2: a001 j 30020a2 + CRG_ASSERT_PARAM(IsCRGInstance(handle->baseAddress)); + 30020a4: fdc42783 lw a5,-36(s0) + 30020a8: 4398 lw a4,0(a5) + 30020aa: 100007b7 lui a5,0x10000 + 30020ae: 00f70a63 beq a4,a5,30020c2 + 30020b2: 07200593 li a1,114 + 30020b6: 030097b7 lui a5,0x3009 + 30020ba: 96c78513 addi a0,a5,-1684 # 300896c + 30020be: 37c1 jal ra,300207e + 30020c0: a001 j 30020c0 + /* Check the validity of PLL-related parameters. */ + CRG_PARAM_CHECK_WITH_RET(IsCrgPllRefClkSelect(handle->pllRefClkSelect), BASE_STATUS_ERROR); + 30020c2: fdc42783 lw a5,-36(s0) + 30020c6: 43dc lw a5,4(a5) + 30020c8: 853e mv a0,a5 + 30020ca: 390d jal ra,3001cfc + 30020cc: 87aa mv a5,a0 + 30020ce: 0017c793 xori a5,a5,1 + 30020d2: 9f81 uxtb a5 + 30020d4: cb91 beqz a5,30020e8 + 30020d6: 07400593 li a1,116 + 30020da: 030097b7 lui a5,0x3009 + 30020de: 96c78513 addi a0,a5,-1684 # 300896c + 30020e2: 3f71 jal ra,300207e + 30020e4: 4785 li a5,1 + 30020e6: ac99 j 300233c + CRG_PARAM_CHECK_WITH_RET(IsCrgPllPreDiv(handle->pllPreDiv), BASE_STATUS_ERROR); + 30020e8: fdc42783 lw a5,-36(s0) + 30020ec: 479c lw a5,8(a5) + 30020ee: 853e mv a0,a5 + 30020f0: 3925 jal ra,3001d28 + 30020f2: 87aa mv a5,a0 + 30020f4: 0017c793 xori a5,a5,1 + 30020f8: 9f81 uxtb a5 + 30020fa: cb91 beqz a5,300210e + 30020fc: 07500593 li a1,117 + 3002100: 030097b7 lui a5,0x3009 + 3002104: 96c78513 addi a0,a5,-1684 # 300896c + 3002108: 3f9d jal ra,300207e + 300210a: 4785 li a5,1 + 300210c: ac05 j 300233c + CRG_PARAM_CHECK_WITH_RET(IsCrgPllFbDiv(handle->pllFbDiv), BASE_STATUS_ERROR); + 300210e: fdc42783 lw a5,-36(s0) + 3002112: 47dc lw a5,12(a5) + 3002114: 853e mv a0,a5 + 3002116: 319d jal ra,3001d7c + 3002118: 87aa mv a5,a0 + 300211a: 0017c793 xori a5,a5,1 + 300211e: 9f81 uxtb a5 + 3002120: cb91 beqz a5,3002134 + 3002122: 07600593 li a1,118 + 3002126: 030097b7 lui a5,0x3009 + 300212a: 96c78513 addi a0,a5,-1684 # 300896c + 300212e: 3f81 jal ra,300207e + 3002130: 4785 li a5,1 + 3002132: a429 j 300233c + CRG_PARAM_CHECK_WITH_RET(IsCrgPllPostDiv(handle->pllPostDiv), BASE_STATUS_ERROR); + 3002134: fdc42783 lw a5,-36(s0) + 3002138: 4b9c lw a5,16(a5) + 300213a: 853e mv a0,a5 + 300213c: 3121 jal ra,3001d44 + 300213e: 87aa mv a5,a0 + 3002140: 0017c793 xori a5,a5,1 + 3002144: 9f81 uxtb a5 + 3002146: cb91 beqz a5,300215a + 3002148: 07700593 li a1,119 + 300214c: 030097b7 lui a5,0x3009 + 3002150: 96c78513 addi a0,a5,-1684 # 300896c + 3002154: 372d jal ra,300207e + 3002156: 4785 li a5,1 + 3002158: a2d5 j 300233c + CRG_PARAM_CHECK_WITH_RET(IsCrgPllPostDiv2(handle->handleEx.pllPostDiv2), BASE_STATUS_ERROR); + 300215a: fdc42783 lw a5,-36(s0) + 300215e: 4fdc lw a5,28(a5) + 3002160: 853e mv a0,a5 + 3002162: 3efd jal ra,3001d60 + 3002164: 87aa mv a5,a0 + 3002166: 0017c793 xori a5,a5,1 + 300216a: 9f81 uxtb a5 + 300216c: cb91 beqz a5,3002180 + 300216e: 07800593 li a1,120 + 3002172: 030097b7 lui a5,0x3009 + 3002176: 96c78513 addi a0,a5,-1684 # 300896c + 300217a: 3711 jal ra,300207e + 300217c: 4785 li a5,1 + 300217e: aa7d j 300233c + /* Check the Clock Source and Frequency Divider of the 1 MHz Clock. */ + CRG_PARAM_CHECK_WITH_RET(IsCrg1MCkSel(handle->handleEx.clk1MSelect), BASE_STATUS_ERROR); + 3002180: fdc42783 lw a5,-36(s0) + 3002184: 539c lw a5,32(a5) + 3002186: 853e mv a0,a5 + 3002188: 3199 jal ra,3001dce + 300218a: 87aa mv a5,a0 + 300218c: 0017c793 xori a5,a5,1 + 3002190: 9f81 uxtb a5 + 3002192: cb91 beqz a5,30021a6 + 3002194: 07a00593 li a1,122 + 3002198: 030097b7 lui a5,0x3009 + 300219c: 96c78513 addi a0,a5,-1684 # 300896c + 30021a0: 3df9 jal ra,300207e + 30021a2: 4785 li a5,1 + 30021a4: aa61 j 300233c + CRG_PARAM_CHECK_WITH_RET(IsCrg1MCkDiv(handle->handleEx.clk1MDiv), BASE_STATUS_ERROR); + 30021a6: fdc42783 lw a5,-36(s0) + 30021aa: 53dc lw a5,36(a5) + 30021ac: 853e mv a0,a5 + 30021ae: 31b1 jal ra,3001dfa + 30021b0: 87aa mv a5,a0 + 30021b2: 0017c793 xori a5,a5,1 + 30021b6: 9f81 uxtb a5 + 30021b8: cb91 beqz a5,30021cc + 30021ba: 07b00593 li a1,123 + 30021be: 030097b7 lui a5,0x3009 + 30021c2: 96c78513 addi a0,a5,-1684 # 300896c + 30021c6: 3d65 jal ra,300207e + 30021c8: 4785 li a5,1 + 30021ca: aa8d j 300233c + CRG_PARAM_CHECK_WITH_RET(IsCrgCoreCkSel(handle->coreClkSelect), BASE_STATUS_ERROR); + 30021cc: fdc42783 lw a5,-36(s0) + 30021d0: 4f9c lw a5,24(a5) + 30021d2: 853e mv a0,a5 + 30021d4: 36d1 jal ra,3001d98 + 30021d6: 87aa mv a5,a0 + 30021d8: 0017c793 xori a5,a5,1 + 30021dc: 9f81 uxtb a5 + 30021de: cb91 beqz a5,30021f2 + 30021e0: 07c00593 li a1,124 + 30021e4: 030097b7 lui a5,0x3009 + 30021e8: 96c78513 addi a0,a5,-1684 # 300896c + 30021ec: 3d49 jal ra,300207e + 30021ee: 4785 li a5,1 + 30021f0: a2b1 j 300233c + + *(unsigned int *)CRG_HOSC_CTRL2_ADDR = 0x306E; /* Optimized HOSC temperature drift performance parameter. */ + 30021f2: 100017b7 lui a5,0x10001 + 30021f6: f0478793 addi a5,a5,-252 # 10000f04 + 30021fa: 670d lui a4,0x3 + 30021fc: 06e70713 addi a4,a4,110 # 306e <__bss_size__+0x14e> + 3002200: c398 sw a4,0(a5) + + CRG_RegStruct *reg = handle->baseAddress; + 3002202: fdc42783 lw a5,-36(s0) + 3002206: 439c lw a5,0(a5) + 3002208: fef42623 sw a5,-20(s0) + g_crgBaseAddr = (void *)reg; + 300220c: 040007b7 lui a5,0x4000 + 3002210: fec42703 lw a4,-20(s0) + 3002214: 48e7aa23 sw a4,1172(a5) # 4000494 + /* Check the validity of the PLL parameter configuration. */ + if (CRG_IsValidPllConfig(handle) != BASE_STATUS_OK) { + 3002218: fdc42503 lw a0,-36(s0) + 300221c: 2d15 jal ra,3002850 + 300221e: 87aa mv a5,a0 + 3002220: c399 beqz a5,3002226 + return BASE_STATUS_ERROR; + 3002222: 4785 li a5,1 + 3002224: aa21 j 300233c + } + /* Disable the write protection function of the CRG register. */ + DCL_SYSCTRL_CrgWriteProtectionDisable(); + 3002226: 3451 jal ra,3001caa + + reg->PERI_CRG0.BIT.pll_ref_cksel = handle->pllRefClkSelect; + 3002228: fdc42783 lw a5,-36(s0) + 300222c: 43dc lw a5,4(a5) + 300222e: 8b85 andi a5,a5,1 + 3002230: 0ff7f693 andi a3,a5,255 + 3002234: fec42703 lw a4,-20(s0) + 3002238: 431c lw a5,0(a4) + 300223a: 8a85 andi a3,a3,1 + 300223c: 9bf9 andi a5,a5,-2 + 300223e: 8fd5 or a5,a5,a3 + 3002240: c31c sw a5,0(a4) + reg->PERI_CRG1.BIT.pll_prediv = handle->pllPreDiv; + 3002242: fdc42783 lw a5,-36(s0) + 3002246: 479c lw a5,8(a5) + 3002248: 8bbd andi a5,a5,15 + 300224a: 0ff7f693 andi a3,a5,255 + 300224e: fec42703 lw a4,-20(s0) + 3002252: 435c lw a5,4(a4) + 3002254: 8abd andi a3,a3,15 + 3002256: 9bc1 andi a5,a5,-16 + 3002258: 8fd5 or a5,a5,a3 + 300225a: c35c sw a5,4(a4) + reg->PERI_CRG2.BIT.pll_fbdiv = handle->pllFbDiv; + 300225c: fdc42783 lw a5,-36(s0) + 3002260: 47dc lw a5,12(a5) + 3002262: 0ff7f693 andi a3,a5,255 + 3002266: fec42703 lw a4,-20(s0) + 300226a: 471c lw a5,8(a4) + 300226c: 0ff6f693 andi a3,a3,255 + 3002270: f007f793 andi a5,a5,-256 + 3002274: 8fd5 or a5,a5,a3 + 3002276: c71c sw a5,8(a4) + reg->PERI_CRG3.BIT.pll_postdiv1 = handle->pllPostDiv; + 3002278: fdc42783 lw a5,-36(s0) + 300227c: 4b9c lw a5,16(a5) + 300227e: 8bbd andi a5,a5,15 + 3002280: 0ff7f693 andi a3,a5,255 + 3002284: fec42703 lw a4,-20(s0) + 3002288: 475c lw a5,12(a4) + 300228a: 8abd andi a3,a3,15 + 300228c: 9bc1 andi a5,a5,-16 + 300228e: 8fd5 or a5,a5,a3 + 3002290: c75c sw a5,12(a4) + reg->PERI_CRG3.BIT.pll_postdiv2 = handle->handleEx.pllPostDiv2; + 3002292: fdc42783 lw a5,-36(s0) + 3002296: 4fdc lw a5,28(a5) + 3002298: 8bbd andi a5,a5,15 + 300229a: 0ff7f693 andi a3,a5,255 + 300229e: fec42703 lw a4,-20(s0) + 30022a2: 475c lw a5,12(a4) + 30022a4: 8abd andi a3,a3,15 + 30022a6: 0692 slli a3,a3,0x4 + 30022a8: f0f7f793 andi a5,a5,-241 + 30022ac: 8fd5 or a5,a5,a3 + 30022ae: c75c sw a5,12(a4) + reg->PERI_CRG4.BIT.pll_pd = BASE_CFG_UNSET; + 30022b0: fec42703 lw a4,-20(s0) + 30022b4: 4b1c lw a5,16(a4) + 30022b6: 9bf9 andi a5,a5,-2 + 30022b8: cb1c sw a5,16(a4) + + while (reg->PERI_CRG7.BIT.pll_lock != BASE_CFG_SET) { + 30022ba: 0001 nop + 30022bc: fec42783 lw a5,-20(s0) + 30022c0: 4fdc lw a5,28(a5) + 30022c2: 8b85 andi a5,a5,1 + 30022c4: 0ff7f713 andi a4,a5,255 + 30022c8: 4785 li a5,1 + 30022ca: fef719e3 bne a4,a5,30022bc + ; /* Wait for PLL to lock */ + } + + DCL_SYSCTRL_CrgWriteProtectionEnable(); + 30022ce: 3411 jal ra,3001cd2 + /* Check the 1MHz clock parameter configuration. */ + if (CRG_IsValid1MHzConfig(handle) != BASE_STATUS_OK) { + 30022d0: fdc42503 lw a0,-36(s0) + 30022d4: 2d3d jal ra,3002912 + 30022d6: 87aa mv a5,a0 + 30022d8: c399 beqz a5,30022de + return BASE_STATUS_ERROR; + 30022da: 4785 li a5,1 + 30022dc: a085 j 300233c + } + while (reg->HOSC_LOCK.BIT.hosc_lock != BASE_CFG_SET) { + 30022de: 0001 nop + 30022e0: fec42703 lw a4,-20(s0) + 30022e4: 6785 lui a5,0x1 + 30022e6: 97ba add a5,a5,a4 + 30022e8: f107a783 lw a5,-240(a5) # f10 + 30022ec: 8b85 andi a5,a5,1 + 30022ee: 0ff7f713 andi a4,a5,255 + 30022f2: 4785 li a5,1 + 30022f4: fef716e3 bne a4,a5,30022e0 + ; /* Wait for HOSC to lock */ + } + /* Set the Clock Source and Frequency Divider of the 1 MHz Clock. */ + reg->PERI_CRG67.BIT.clk_1m_div = handle->handleEx.clk1MDiv; + 30022f8: fdc42783 lw a5,-36(s0) + 30022fc: 53dc lw a5,36(a5) + 30022fe: 03f7f793 andi a5,a5,63 + 3002302: 0ff7f693 andi a3,a5,255 + 3002306: fec42703 lw a4,-20(s0) + 300230a: 10c72783 lw a5,268(a4) + 300230e: 03f6f693 andi a3,a3,63 + 3002312: fc07f793 andi a5,a5,-64 + 3002316: 8fd5 or a5,a5,a3 + 3002318: 10f72623 sw a5,268(a4) + reg->PERI_CRG66.BIT.clk_1m_ini_cksel = handle->handleEx.clk1MSelect; + 300231c: fdc42783 lw a5,-36(s0) + 3002320: 539c lw a5,32(a5) + 3002322: 8b85 andi a5,a5,1 + 3002324: 0ff7f693 andi a3,a5,255 + 3002328: fec42703 lw a4,-20(s0) + 300232c: 10872783 lw a5,264(a4) + 3002330: 8a85 andi a3,a3,1 + 3002332: 9bf9 andi a5,a5,-2 + 3002334: 8fd5 or a5,a5,a3 + 3002336: 10f72423 sw a5,264(a4) + return BASE_STATUS_OK; + 300233a: 4781 li a5,0 +} + 300233c: 853e mv a0,a5 + 300233e: 50b2 lw ra,44(sp) + 3002340: 5422 lw s0,40(sp) + 3002342: 6145 addi sp,sp,48 + 3002344: 8082 ret + +03002346 : + * @param handle CRG Handle + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Paramter check fail + */ +BASE_StatusType HAL_CRG_SetCoreClockSelect(CRG_Handle *handle) +{ + 3002346: 7179 addi sp,sp,-48 + 3002348: d606 sw ra,44(sp) + 300234a: d422 sw s0,40(sp) + 300234c: 1800 addi s0,sp,48 + 300234e: fca42e23 sw a0,-36(s0) + CRG_ASSERT_PARAM(handle != 0); + 3002352: fdc42783 lw a5,-36(s0) + 3002356: eb89 bnez a5,3002368 + 3002358: 10a00593 li a1,266 + 300235c: 030097b7 lui a5,0x3009 + 3002360: 96c78513 addi a0,a5,-1684 # 300896c + 3002364: 3b29 jal ra,300207e + 3002366: a001 j 3002366 + CRG_ASSERT_PARAM(IsCRGInstance(handle->baseAddress)); + 3002368: fdc42783 lw a5,-36(s0) + 300236c: 4398 lw a4,0(a5) + 300236e: 100007b7 lui a5,0x10000 + 3002372: 00f70a63 beq a4,a5,3002386 + 3002376: 10b00593 li a1,267 + 300237a: 030097b7 lui a5,0x3009 + 300237e: 96c78513 addi a0,a5,-1684 # 300896c + 3002382: 39f5 jal ra,300207e + 3002384: a001 j 3002384 + CRG_PARAM_CHECK_WITH_RET(IsCrgCoreCkSel(handle->coreClkSelect), BASE_STATUS_ERROR); + 3002386: fdc42783 lw a5,-36(s0) + 300238a: 4f9c lw a5,24(a5) + 300238c: 853e mv a0,a5 + 300238e: 3429 jal ra,3001d98 + 3002390: 87aa mv a5,a0 + 3002392: 0017c793 xori a5,a5,1 + 3002396: 9f81 uxtb a5 + 3002398: cb91 beqz a5,30023ac + 300239a: 10c00593 li a1,268 + 300239e: 030097b7 lui a5,0x3009 + 30023a2: 96c78513 addi a0,a5,-1684 # 300896c + 30023a6: 39e1 jal ra,300207e + 30023a8: 4785 li a5,1 + 30023aa: a005 j 30023ca + + CRG_RegStruct *reg = handle->baseAddress; + 30023ac: fdc42783 lw a5,-36(s0) + 30023b0: 439c lw a5,0(a5) + 30023b2: fef42623 sw a5,-20(s0) + /* The write protection of the CRG register needs to be disabled. */ + DCL_SYSCTRL_CrgWriteProtectionDisable(); + 30023b6: 38d5 jal ra,3001caa + DCL_CRG_SetCoreClkSel(reg, handle->coreClkSelect); + 30023b8: fdc42783 lw a5,-36(s0) + 30023bc: 4f9c lw a5,24(a5) + 30023be: 85be mv a1,a5 + 30023c0: fec42503 lw a0,-20(s0) + 30023c4: 31a9 jal ra,300200e + DCL_SYSCTRL_CrgWriteProtectionEnable(); + 30023c6: 3231 jal ra,3001cd2 + + return BASE_STATUS_OK; + 30023c8: 4781 li a5,0 +} + 30023ca: 853e mv a0,a5 + 30023cc: 50b2 lw ra,44(sp) + 30023ce: 5422 lw s0,40(sp) + 30023d0: 6145 addi sp,sp,48 + 30023d2: 8082 ret + +030023d4 : + * @brief Get PLL Clock Frequence + * @param None + * @retval unsigned int PLL clock frequency + */ +static inline unsigned int CRG_GetVcoFreq(void) +{ + 30023d4: 1101 addi sp,sp,-32 + 30023d6: ce06 sw ra,28(sp) + 30023d8: cc22 sw s0,24(sp) + 30023da: 1000 addi s0,sp,32 + unsigned int freq; + unsigned int regFbdiv; + CRG_RegStruct *crg = g_crgBaseAddr; + 30023dc: 040007b7 lui a5,0x4000 + 30023e0: 4947a783 lw a5,1172(a5) # 4000494 + 30023e4: fef42623 sw a5,-20(s0) + + CRG_ASSERT_PARAM(IsCRGInstance(crg)); + 30023e8: fec42703 lw a4,-20(s0) + 30023ec: 100007b7 lui a5,0x10000 + 30023f0: 00f70a63 beq a4,a5,3002404 + 30023f4: 12200593 li a1,290 + 30023f8: 030097b7 lui a5,0x3009 + 30023fc: 96c78513 addi a0,a5,-1684 # 300896c + 3002400: 39bd jal ra,300207e + 3002402: a001 j 3002402 + CRG_ASSERT_PARAM((XTRAIL_FREQ <= 30000000U)); /* The maximum of the external clock source is 30000000U. */ + + freq = CRG_GetPllRefIni(crg->PERI_CRG0.BIT.pll_ref_cksel); + 3002404: fec42783 lw a5,-20(s0) + 3002408: 439c lw a5,0(a5) + 300240a: 8b85 andi a5,a5,1 + 300240c: 9f81 uxtb a5 + 300240e: 853e mv a0,a5 + 3002410: 2b91 jal ra,3002964 + 3002412: fea42423 sw a0,-24(s0) + freq /= CRG_GetPreDivValue(crg->PERI_CRG1.BIT.pll_prediv); + 3002416: fec42783 lw a5,-20(s0) + 300241a: 43dc lw a5,4(a5) + 300241c: 8bbd andi a5,a5,15 + 300241e: 9f81 uxtb a5 + 3002420: 853e mv a0,a5 + 3002422: 23b5 jal ra,300298e + 3002424: 872a mv a4,a0 + 3002426: fe842783 lw a5,-24(s0) + 300242a: 02e7d7b3 divu a5,a5,a4 + 300242e: fef42423 sw a5,-24(s0) + regFbdiv = CRG_GetPllFbDivValue(crg->PERI_CRG2.BIT.pll_fbdiv); /* Get the value of the fbdiv register. */ + 3002432: fec42783 lw a5,-20(s0) + 3002436: 479c lw a5,8(a5) + 3002438: 9f81 uxtb a5 + 300243a: 853e mv a0,a5 + 300243c: 2341 jal ra,30029bc + 300243e: fea42223 sw a0,-28(s0) + freq *= (regFbdiv >= 0x06) ? regFbdiv : 0x06; /* 0x0-0x6: divided by 0x6 */ + 3002442: fe442783 lw a5,-28(s0) + 3002446: 4719 li a4,6 + 3002448: 00e7f363 bgeu a5,a4,300244e + 300244c: 4799 li a5,6 + 300244e: fe842703 lw a4,-24(s0) + 3002452: 02f707b3 mul a5,a4,a5 + 3002456: fef42423 sw a5,-24(s0) + return freq; + 300245a: fe842783 lw a5,-24(s0) +} + 300245e: 853e mv a0,a5 + 3002460: 40f2 lw ra,28(sp) + 3002462: 4462 lw s0,24(sp) + 3002464: 6105 addi sp,sp,32 + 3002466: 8082 ret + +03002468 : + * @brief Get PLL Clock Frequence + * @param None + * @retval unsigned int PLL clock frequency + */ +unsigned int HAL_CRG_GetPllFreq(void) +{ + 3002468: 1101 addi sp,sp,-32 + 300246a: ce06 sw ra,28(sp) + 300246c: cc22 sw s0,24(sp) + 300246e: 1000 addi s0,sp,32 + unsigned int freq; + unsigned int pllPostDivValue; + CRG_RegStruct *crg = g_crgBaseAddr; + 3002470: 040007b7 lui a5,0x4000 + 3002474: 4947a783 lw a5,1172(a5) # 4000494 + 3002478: fef42423 sw a5,-24(s0) + + CRG_ASSERT_PARAM(IsCRGInstance(crg)); + 300247c: fe842703 lw a4,-24(s0) + 3002480: 100007b7 lui a5,0x10000 + 3002484: 00f70a63 beq a4,a5,3002498 + 3002488: 13700593 li a1,311 + 300248c: 030097b7 lui a5,0x3009 + 3002490: 96c78513 addi a0,a5,-1684 # 300896c + 3002494: 36ed jal ra,300207e + 3002496: a001 j 3002496 + freq = CRG_GetVcoFreq(); + 3002498: 3f35 jal ra,30023d4 + 300249a: fea42623 sw a0,-20(s0) + pllPostDivValue = CRG_GetPllPostDivValue((CRG_PllPostDiv)crg->PERI_CRG3.BIT.pll_postdiv1); + 300249e: fe842783 lw a5,-24(s0) + 30024a2: 47dc lw a5,12(a5) + 30024a4: 8bbd andi a5,a5,15 + 30024a6: 9f81 uxtb a5 + 30024a8: 853e mv a0,a5 + 30024aa: 2b91 jal ra,30029fe + 30024ac: fea42223 sw a0,-28(s0) + /* Calculate the PLL output clock frequency based on the VCO clock frequency and post-division coefficient. */ + if (pllPostDivValue != 0) { + 30024b0: fe442783 lw a5,-28(s0) + 30024b4: cb89 beqz a5,30024c6 + freq /= pllPostDivValue; + 30024b6: fec42703 lw a4,-20(s0) + 30024ba: fe442783 lw a5,-28(s0) + 30024be: 02f757b3 divu a5,a4,a5 + 30024c2: fef42623 sw a5,-20(s0) + } + return freq; + 30024c6: fec42783 lw a5,-20(s0) +} + 30024ca: 853e mv a0,a5 + 30024cc: 40f2 lw ra,28(sp) + 30024ce: 4462 lw s0,24(sp) + 30024d0: 6105 addi sp,sp,32 + 30024d2: 8082 ret + +030024d4 : + * @brief Get Core Clock Frequence + * @param None + * @retval unsigned int Core clock frequency + */ +unsigned int HAL_CRG_GetCoreClkFreq(void) +{ + 30024d4: 1101 addi sp,sp,-32 + 30024d6: ce06 sw ra,28(sp) + 30024d8: cc22 sw s0,24(sp) + 30024da: 1000 addi s0,sp,32 + unsigned int freq; + unsigned int coreClkSelect; + CRG_RegStruct *crg = g_crgBaseAddr; + 30024dc: 040007b7 lui a5,0x4000 + 30024e0: 4947a783 lw a5,1172(a5) # 4000494 + 30024e4: fef42423 sw a5,-24(s0) + + CRG_ASSERT_PARAM(IsCRGInstance(crg)); + 30024e8: fe842703 lw a4,-24(s0) + 30024ec: 100007b7 lui a5,0x10000 + 30024f0: 00f70a63 beq a4,a5,3002504 + 30024f4: 14c00593 li a1,332 + 30024f8: 030097b7 lui a5,0x3009 + 30024fc: 96c78513 addi a0,a5,-1684 # 300896c + 3002500: 3ebd jal ra,300207e + 3002502: a001 j 3002502 + coreClkSelect = crg->PERI_CRG64.BIT.clk_pst1_sw_sel; + 3002504: fe842783 lw a5,-24(s0) + 3002508: 1007a783 lw a5,256(a5) + 300250c: 8b8d andi a5,a5,3 + 300250e: 9f81 uxtb a5 + 3002510: fef42223 sw a5,-28(s0) + switch (coreClkSelect) { + 3002514: fe442783 lw a5,-28(s0) + 3002518: 4705 li a4,1 + 300251a: 02e78063 beq a5,a4,300253a + 300251e: 4705 li a4,1 + 3002520: 00e7e663 bltu a5,a4,300252c + 3002524: 4709 li a4,2 + 3002526: 02e78163 beq a5,a4,3002548 + 300252a: a01d j 3002550 + case CRG_CORE_CLK_SELECT_HOSC: /* The clock source is an internal high-speed clock. */ + freq = HOSC_FREQ; + 300252c: 017d87b7 lui a5,0x17d8 + 3002530: 84078793 addi a5,a5,-1984 # 17d7840 + 3002534: fef42623 sw a5,-20(s0) + break; + 3002538: a015 j 300255c + + case CRG_CORE_CLK_SELECT_TCXO: /* The clock source is the external crystal oscillator clock. */ + freq = XTRAIL_FREQ; + 300253a: 01c9c7b7 lui a5,0x1c9c + 300253e: 38078793 addi a5,a5,896 # 1c9c380 + 3002542: fef42623 sw a5,-20(s0) + break; + 3002546: a819 j 300255c + + case CRG_CORE_CLK_SELECT_PLL: /* The clock source is the PLL. */ + freq = HAL_CRG_GetPllFreq(); + 3002548: 3705 jal ra,3002468 + 300254a: fea42623 sw a0,-20(s0) + break; + 300254e: a039 j 300255c + + default: + freq = LOSC_FREQ; + 3002550: 67a1 lui a5,0x8 + 3002552: d0078793 addi a5,a5,-768 # 7d00 + 3002556: fef42623 sw a5,-20(s0) + break; + 300255a: 0001 nop + } + return freq; + 300255c: fec42783 lw a5,-20(s0) +} + 3002560: 853e mv a0,a5 + 3002562: 40f2 lw ra,28(sp) + 3002564: 4462 lw s0,24(sp) + 3002566: 6105 addi sp,sp,32 + 3002568: 8082 ret + +0300256a : + * @brief Get Clock Frequence + * @param handle CRG Handle + * @retval Frequece of IP + */ +unsigned int HAL_CRG_GetIpFreq(const void *baseAddress) +{ + 300256a: 7179 addi sp,sp,-48 + 300256c: d606 sw ra,44(sp) + 300256e: d422 sw s0,40(sp) + 3002570: 1800 addi s0,sp,48 + 3002572: fca42e23 sw a0,-36(s0) + CRG_ASSERT_PARAM(baseAddress != NULL); + 3002576: fdc42783 lw a5,-36(s0) + 300257a: eb89 bnez a5,300258c + 300257c: 16900593 li a1,361 + 3002580: 030097b7 lui a5,0x3009 + 3002584: 96c78513 addi a0,a5,-1684 # 300896c + 3002588: 3cdd jal ra,300207e + 300258a: a001 j 300258a + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + 300258c: 040007b7 lui a5,0x4000 + 3002590: 4947a703 lw a4,1172(a5) # 4000494 + 3002594: 100007b7 lui a5,0x10000 + 3002598: 00f70a63 beq a4,a5,30025ac + 300259c: 16a00593 li a1,362 + 30025a0: 030097b7 lui a5,0x3009 + 30025a4: 96c78513 addi a0,a5,-1684 # 300896c + 30025a8: 3cd9 jal ra,300207e + 30025aa: a001 j 30025aa +#ifdef FPGA + /* Use this function to obtain the clock frequency during the FPGA phase. */ + return CHIP_GetIpFreqHz(baseAddress); +#else + unsigned int hclk = HAL_CRG_GetCoreClkFreq(); + 30025ac: 3725 jal ra,30024d4 + 30025ae: fea42423 sw a0,-24(s0) + unsigned int freq = LOSC_FREQ; + 30025b2: 67a1 lui a5,0x8 + 30025b4: d0078793 addi a5,a5,-768 # 7d00 + 30025b8: fef42623 sw a5,-20(s0) + unsigned int coreClkFreq; + /* Get the CRG type of the target IP. */ + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + 30025bc: fdc42503 lw a0,-36(s0) + 30025c0: be5fe0ef jal ra,30011a4 + 30025c4: fea42223 sw a0,-28(s0) + if (p == NULL) { + 30025c8: fe442783 lw a5,-28(s0) + 30025cc: e781 bnez a5,30025d4 + return freq; + 30025ce: fec42783 lw a5,-20(s0) + 30025d2: a895 j 3002646 + } + switch (p->type) { + 30025d4: fe442783 lw a5,-28(s0) + 30025d8: 43dc lw a5,4(a5) + 30025da: 4715 li a4,5 + 30025dc: 04f76a63 bltu a4,a5,3002630 + 30025e0: 00279713 slli a4,a5,0x2 + 30025e4: 030097b7 lui a5,0x3009 + 30025e8: 9a878793 addi a5,a5,-1624 # 30089a8 + 30025ec: 97ba add a5,a5,a4 + 30025ee: 439c lw a5,0(a5) + 30025f0: 8782 jr a5 + case CRG_IP_NONE_CLK_SEL: + case CRG_IP_EFC: + case CRG_IP_ANA: + freq = hclk; /* Returns the internal high speed clock frequency. */ + 30025f2: fe842783 lw a5,-24(s0) + 30025f6: fef42623 sw a5,-20(s0) + break; + 30025fa: a825 j 3002632 + + case CRG_IP_CAN: + freq = CRG_GetPllRefIni(g_crgBaseAddr->PERI_CRG0.BIT.pll_ref_cksel); + 30025fc: 040007b7 lui a5,0x4000 + 3002600: 4947a783 lw a5,1172(a5) # 4000494 + 3002604: 439c lw a5,0(a5) + 3002606: 8b85 andi a5,a5,1 + 3002608: 9f81 uxtb a5 + 300260a: 853e mv a0,a5 + 300260c: 2ea1 jal ra,3002964 + 300260e: fea42623 sw a0,-20(s0) + break; + 3002612: a005 j 3002632 + + case CRG_IP_ADC: + /* Get core clock frequence for calculating the ADC clock frequency. */ + coreClkFreq = HAL_CRG_GetCoreClkFreq(); + 3002614: 35c1 jal ra,30024d4 + 3002616: fea42023 sw a0,-32(s0) + freq = CRG_GetAdcIpFreq(p, CRG_GetVcoFreq(), coreClkFreq); + 300261a: 3b6d jal ra,30023d4 + 300261c: 87aa mv a5,a0 + 300261e: fe042603 lw a2,-32(s0) + 3002622: 85be mv a1,a5 + 3002624: fe442503 lw a0,-28(s0) + 3002628: 2209 jal ra,300272a + 300262a: fea42623 sw a0,-20(s0) + break; + 300262e: a011 j 3002632 + + case CRG_IP_IWDG: /* The IWDG clock frequency is an internal low-speed clock. */ + default: + break; + 3002630: 0001 nop + } + if (freq == 0) { + 3002632: fec42783 lw a5,-20(s0) + 3002636: e791 bnez a5,3002642 + freq = LOSC_FREQ; + 3002638: 67a1 lui a5,0x8 + 300263a: d0078793 addi a5,a5,-768 # 7d00 + 300263e: fef42623 sw a5,-20(s0) + } + return freq; + 3002642: fec42783 lw a5,-20(s0) +#endif +} + 3002646: 853e mv a0,a5 + 3002648: 50b2 lw ra,44(sp) + 300264a: 5422 lw s0,40(sp) + 300264c: 6145 addi sp,sp,48 + 300264e: 8082 ret + +03002650 : + * @param enable enable mask + * @retval BASE_STATUS_ERROR Can't find the Match or operation is not support + * @retval BASE_STATUS_OK Operation Success + */ +BASE_StatusType HAL_CRG_IpEnableSet(const void *baseAddress, unsigned int enable) +{ + 3002650: 7179 addi sp,sp,-48 + 3002652: d606 sw ra,44(sp) + 3002654: d422 sw s0,40(sp) + 3002656: 1800 addi s0,sp,48 + 3002658: fca42e23 sw a0,-36(s0) + 300265c: fcb42c23 sw a1,-40(s0) + CRG_ASSERT_PARAM(baseAddress != NULL); + 3002660: fdc42783 lw a5,-36(s0) + 3002664: eb89 bnez a5,3002676 + 3002666: 19c00593 li a1,412 + 300266a: 030097b7 lui a5,0x3009 + 300266e: 96c78513 addi a0,a5,-1684 # 300896c + 3002672: 3431 jal ra,300207e + 3002674: a001 j 3002674 + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + 3002676: 040007b7 lui a5,0x4000 + 300267a: 4947a703 lw a4,1172(a5) # 4000494 + 300267e: 100007b7 lui a5,0x10000 + 3002682: 00f70a63 beq a4,a5,3002696 + 3002686: 19d00593 li a1,413 + 300268a: 030097b7 lui a5,0x3009 + 300268e: 96c78513 addi a0,a5,-1684 # 300896c + 3002692: 32f5 jal ra,300207e + 3002694: a001 j 3002694 + /* Check the validity of the input parameters. */ + CRG_PARAM_CHECK_WITH_RET((enable == IP_CLK_ENABLE || enable == IP_CLK_DISABLE), BASE_STATUS_ERROR); + 3002696: fd842703 lw a4,-40(s0) + 300269a: 4785 li a5,1 + 300269c: 00f70e63 beq a4,a5,30026b8 + 30026a0: fd842783 lw a5,-40(s0) + 30026a4: cb91 beqz a5,30026b8 + 30026a6: 19f00593 li a1,415 + 30026aa: 030097b7 lui a5,0x3009 + 30026ae: 96c78513 addi a0,a5,-1684 # 300896c + 30026b2: 32f1 jal ra,300207e + 30026b4: 4785 li a5,1 + 30026b6: a0ad j 3002720 + /* Get the CRG type of the target IP. */ + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + 30026b8: fdc42503 lw a0,-36(s0) + 30026bc: ae9fe0ef jal ra,30011a4 + 30026c0: fea42623 sw a0,-20(s0) + if ((p == NULL) || (p->type >= CRG_IP_MAX_TYPE)) { + 30026c4: fec42783 lw a5,-20(s0) + 30026c8: c799 beqz a5,30026d6 + 30026ca: fec42783 lw a5,-20(s0) + 30026ce: 43d8 lw a4,4(a5) + 30026d0: 4795 li a5,5 + 30026d2: 00e7f463 bgeu a5,a4,30026da + return BASE_STATUS_ERROR; + 30026d6: 4785 li a5,1 + 30026d8: a0a1 j 3002720 + } + if (g_ipClkProc[p->type].enableSet == NULL) { + 30026da: fec42783 lw a5,-20(s0) + 30026de: 43d4 lw a3,4(a5) + 30026e0: 040007b7 lui a5,0x4000 + 30026e4: 02478713 addi a4,a5,36 # 4000024 + 30026e8: 02400793 li a5,36 + 30026ec: 02f687b3 mul a5,a3,a5 + 30026f0: 97ba add a5,a5,a4 + 30026f2: 479c lw a5,8(a5) + 30026f4: e399 bnez a5,30026fa + return BASE_STATUS_ERROR; + 30026f6: 4785 li a5,1 + 30026f8: a025 j 3002720 + } + g_ipClkProc[p->type].enableSet(p, enable); + 30026fa: fec42783 lw a5,-20(s0) + 30026fe: 43d4 lw a3,4(a5) + 3002700: 040007b7 lui a5,0x4000 + 3002704: 02478713 addi a4,a5,36 # 4000024 + 3002708: 02400793 li a5,36 + 300270c: 02f687b3 mul a5,a3,a5 + 3002710: 97ba add a5,a5,a4 + 3002712: 479c lw a5,8(a5) + 3002714: fd842583 lw a1,-40(s0) + 3002718: fec42503 lw a0,-20(s0) + 300271c: 9782 jalr a5 + return BASE_STATUS_OK; + 300271e: 4781 li a5,0 +} + 3002720: 853e mv a0,a5 + 3002722: 50b2 lw ra,44(sp) + 3002724: 5422 lw s0,40(sp) + 3002726: 6145 addi sp,sp,48 + 3002728: 8082 ret + +0300272a : + * @param coreClkFreq core clock rate + * @retval Ip Frequence + */ +static unsigned int CRG_GetAdcIpFreq(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int baseClkRate, + unsigned int coreClkFreq) +{ + 300272a: 7139 addi sp,sp,-64 + 300272c: de06 sw ra,60(sp) + 300272e: dc22 sw s0,56(sp) + 3002730: 0080 addi s0,sp,64 + 3002732: fca42623 sw a0,-52(s0) + 3002736: fcb42423 sw a1,-56(s0) + 300273a: fcc42223 sw a2,-60(s0) + CRG_ASSERT_PARAM(matchInfo != NULL); + 300273e: fcc42783 lw a5,-52(s0) + 3002742: eb89 bnez a5,3002754 + 3002744: 2af00593 li a1,687 + 3002748: 030097b7 lui a5,0x3009 + 300274c: 96c78513 addi a0,a5,-1684 # 300896c + 3002750: 27a1 jal ra,3002e98 + 3002752: a001 j 3002752 + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + 3002754: 040007b7 lui a5,0x4000 + 3002758: 4947a783 lw a5,1172(a5) # 4000494 + 300275c: eb89 bnez a5,300276e + 300275e: 2b000593 li a1,688 + 3002762: 030097b7 lui a5,0x3009 + 3002766: 96c78513 addi a0,a5,-1684 # 300896c + 300276a: 273d jal ra,3002e98 + 300276c: a001 j 300276c + + unsigned int clkSel; + unsigned int clkDiv; + unsigned int pst2Div; + unsigned int freq = 0; + 300276e: fe042623 sw zero,-20(s0) + + /* Obtains the clock source selection of the ADC. */ + const CRG_IpProc *proc = &g_ipClkProc[matchInfo->type]; + 3002772: fcc42783 lw a5,-52(s0) + 3002776: 43d8 lw a4,4(a5) + 3002778: 02400793 li a5,36 + 300277c: 02f70733 mul a4,a4,a5 + 3002780: 040007b7 lui a5,0x4000 + 3002784: 02478793 addi a5,a5,36 # 4000024 + 3002788: 97ba add a5,a5,a4 + 300278a: fef42423 sw a5,-24(s0) + if (proc->clkSelGet == NULL) { + 300278e: fe842783 lw a5,-24(s0) + 3002792: 4fdc lw a5,28(a5) + 3002794: e399 bnez a5,300279a + return 0; + 3002796: 4781 li a5,0 + 3002798: a07d j 3002846 + } + clkSel = proc->clkSelGet(matchInfo); + 300279a: fe842783 lw a5,-24(s0) + 300279e: 4fdc lw a5,28(a5) + 30027a0: fcc42503 lw a0,-52(s0) + 30027a4: 9782 jalr a5 + 30027a6: fea42223 sw a0,-28(s0) + /* Calculate the frequency from the ADC's clock source. */ + if (clkSel == CRG_ADC_CLK_SYN_CORE) { + 30027aa: fe442703 lw a4,-28(s0) + 30027ae: 478d li a5,3 + 30027b0: 00f71763 bne a4,a5,30027be + freq = coreClkFreq; + 30027b4: fc442783 lw a5,-60(s0) + 30027b8: fef42623 sw a5,-20(s0) + 30027bc: a085 j 300281c + } else if (clkSel == CRG_ADC_CLK_ASYN_HOSC) { + 30027be: fe442783 lw a5,-28(s0) + 30027c2: eb81 bnez a5,30027d2 + freq = HOSC_FREQ; + 30027c4: 017d87b7 lui a5,0x17d8 + 30027c8: 84078793 addi a5,a5,-1984 # 17d7840 + 30027cc: fef42623 sw a5,-20(s0) + 30027d0: a0b1 j 300281c + } else if (clkSel == CRG_ADC_CLK_ASYN_TCXO) { + 30027d2: fe442703 lw a4,-28(s0) + 30027d6: 4785 li a5,1 + 30027d8: 00f71963 bne a4,a5,30027ea + /* The maximum speed of the external clock source is 30000000U. */ + freq = (XTRAIL_FREQ > 30000000U) ? 0 : XTRAIL_FREQ; + 30027dc: 01c9c7b7 lui a5,0x1c9c + 30027e0: 38078793 addi a5,a5,896 # 1c9c380 + 30027e4: fef42623 sw a5,-20(s0) + 30027e8: a815 j 300281c + } else if (clkSel == CRG_ADC_CLK_ASYN_PLL_DIV) { + 30027ea: fe442703 lw a4,-28(s0) + 30027ee: 4789 li a5,2 + 30027f0: 02f71663 bne a4,a5,300281c + pst2Div = CRG_GetPllPostDivValue((CRG_PllPostDiv)g_crgBaseAddr->PERI_CRG3.BIT.pll_postdiv2); + 30027f4: 040007b7 lui a5,0x4000 + 30027f8: 4947a783 lw a5,1172(a5) # 4000494 + 30027fc: 47dc lw a5,12(a5) + 30027fe: 8391 srli a5,a5,0x4 + 3002800: 8bbd andi a5,a5,15 + 3002802: 9f81 uxtb a5 + 3002804: 853e mv a0,a5 + 3002806: 2ae5 jal ra,30029fe + 3002808: fea42023 sw a0,-32(s0) + freq = baseClkRate / pst2Div; + 300280c: fc842703 lw a4,-56(s0) + 3002810: fe042783 lw a5,-32(s0) + 3002814: 02f757b3 divu a5,a4,a5 + 3002818: fef42623 sw a5,-20(s0) + } + + /* Obtain the frequency divider based on the ADC clock source. */ + if (proc->clkDivGet == NULL) { + 300281c: fe842783 lw a5,-24(s0) + 3002820: 539c lw a5,32(a5) + 3002822: e399 bnez a5,3002828 + return 0; + 3002824: 4781 li a5,0 + 3002826: a005 j 3002846 + } + clkDiv = proc->clkDivGet(matchInfo); + 3002828: fe842783 lw a5,-24(s0) + 300282c: 539c lw a5,32(a5) + 300282e: fcc42503 lw a0,-52(s0) + 3002832: 9782 jalr a5 + 3002834: fca42e23 sw a0,-36(s0) + /* Calculate the clock frequency of the ADC. */ + return (freq / (clkDiv + 1)); + 3002838: fdc42783 lw a5,-36(s0) + 300283c: 0785 addi a5,a5,1 + 300283e: fec42703 lw a4,-20(s0) + 3002842: 02f757b3 divu a5,a4,a5 +} + 3002846: 853e mv a0,a5 + 3002848: 50f2 lw ra,60(sp) + 300284a: 5462 lw s0,56(sp) + 300284c: 6121 addi sp,sp,64 + 300284e: 8082 ret + +03002850 : + * @param CRG_Handle CRG handle + * @retval BASE_STATUS_OK Check Success + * @retval BASE_STATUS_ERROR Check Fail + */ +static BASE_StatusType CRG_IsValidPllConfig(const CRG_Handle *handle) +{ + 3002850: 7179 addi sp,sp,-48 + 3002852: d606 sw ra,44(sp) + 3002854: d422 sw s0,40(sp) + 3002856: 1800 addi s0,sp,48 + 3002858: fca42e23 sw a0,-36(s0) + unsigned int preDiv; + unsigned int freq; + + freq = CRG_GetPllRefIni(handle->pllRefClkSelect); + 300285c: fdc42783 lw a5,-36(s0) + 3002860: 43dc lw a5,4(a5) + 3002862: 853e mv a0,a5 + 3002864: 2201 jal ra,3002964 + 3002866: fea42623 sw a0,-20(s0) + preDiv = CRG_GetPreDivValue(handle->pllPreDiv); + 300286a: fdc42783 lw a5,-36(s0) + 300286e: 479c lw a5,8(a5) + 3002870: 853e mv a0,a5 + 3002872: 2a31 jal ra,300298e + 3002874: fea42423 sw a0,-24(s0) + /* Check the validity of the prescaled clock frequency. */ + if (!IsCrgValidPreDiv(freq, preDiv)) { + 3002878: fe842583 lw a1,-24(s0) + 300287c: fec42503 lw a0,-20(s0) + 3002880: d96ff0ef jal ra,3001e16 + 3002884: 87aa mv a5,a0 + 3002886: 0017c793 xori a5,a5,1 + 300288a: 9f81 uxtb a5 + 300288c: c399 beqz a5,3002892 + return BASE_STATUS_ERROR; + 300288e: 4785 li a5,1 + 3002890: a8a5 j 3002908 + } + freq /= preDiv; + 3002892: fec42703 lw a4,-20(s0) + 3002896: fe842783 lw a5,-24(s0) + 300289a: 02f757b3 divu a5,a4,a5 + 300289e: fef42623 sw a5,-20(s0) + /* Check the validity of the clock frequency after frequency multiplication. */ + if (!IsCrgValidFdDiv(freq, handle->pllFbDiv)) { + 30028a2: fdc42783 lw a5,-36(s0) + 30028a6: 47dc lw a5,12(a5) + 30028a8: 85be mv a1,a5 + 30028aa: fec42503 lw a0,-20(s0) + 30028ae: dc6ff0ef jal ra,3001e74 + 30028b2: 87aa mv a5,a0 + 30028b4: 0017c793 xori a5,a5,1 + 30028b8: 9f81 uxtb a5 + 30028ba: c399 beqz a5,30028c0 + return BASE_STATUS_ERROR; + 30028bc: 4785 li a5,1 + 30028be: a0a9 j 3002908 + } + freq *= (handle->pllFbDiv > 0x06) ? handle->pllFbDiv : 0x06; /* 0x0-0x6: divided by 0x6 */ + 30028c0: fdc42783 lw a5,-36(s0) + 30028c4: 47dc lw a5,12(a5) + 30028c6: 4719 li a4,6 + 30028c8: 00e7f363 bgeu a5,a4,30028ce + 30028cc: 4799 li a5,6 + 30028ce: fec42703 lw a4,-20(s0) + 30028d2: 02f707b3 mul a5,a4,a5 + 30028d6: fef42623 sw a5,-20(s0) + /* Check whether the PLL output frequency is valid. */ + if (IsCrgValidPostDiv(freq, handle->pllPostDiv) && IsCrgValidPostDiv2(freq, handle->handleEx.pllPostDiv2)) { + 30028da: fdc42783 lw a5,-36(s0) + 30028de: 4b9c lw a5,16(a5) + 30028e0: 85be mv a1,a5 + 30028e2: fec42503 lw a0,-20(s0) + 30028e6: e18ff0ef jal ra,3001efe + 30028ea: 87aa mv a5,a0 + 30028ec: cf89 beqz a5,3002906 + 30028ee: fdc42783 lw a5,-36(s0) + 30028f2: 4fdc lw a5,28(a5) + 30028f4: 85be mv a1,a5 + 30028f6: fec42503 lw a0,-20(s0) + 30028fa: e4cff0ef jal ra,3001f46 + 30028fe: 87aa mv a5,a0 + 3002900: c399 beqz a5,3002906 + return BASE_STATUS_OK; + 3002902: 4781 li a5,0 + 3002904: a011 j 3002908 + } + return BASE_STATUS_ERROR; + 3002906: 4785 li a5,1 +} + 3002908: 853e mv a0,a5 + 300290a: 50b2 lw ra,44(sp) + 300290c: 5422 lw s0,40(sp) + 300290e: 6145 addi sp,sp,48 + 3002910: 8082 ret + +03002912 : + * @param CRG_Handle CRG handle + * @retval BASE_STATUS_OK Check Success + * @retval BASE_STATUS_ERROR Check Fail + */ +static BASE_StatusType CRG_IsValid1MHzConfig(const CRG_Handle *handle) +{ + 3002912: 7179 addi sp,sp,-48 + 3002914: d622 sw s0,44(sp) + 3002916: 1800 addi s0,sp,48 + 3002918: fca42e23 sw a0,-36(s0) + unsigned int freq; + /* Get the ref frequency of the 1 MHz clock. */ + freq = (handle->handleEx.clk1MSelect == CRG_1M_CLK_SELECT_HOSC) ? HOSC_FREQ : XTRAIL_FREQ; + 300291c: fdc42783 lw a5,-36(s0) + 3002920: 539c lw a5,32(a5) + 3002922: e791 bnez a5,300292e + 3002924: 017d87b7 lui a5,0x17d8 + 3002928: 84078793 addi a5,a5,-1984 # 17d7840 + 300292c: a029 j 3002936 + 300292e: 01c9c7b7 lui a5,0x1c9c + 3002932: 38078793 addi a5,a5,896 # 1c9c380 + 3002936: fef42623 sw a5,-20(s0) + /* Check whether the 1MHz output frequency is valid. */ + if ((freq / (handle->handleEx.clk1MDiv + 1)) == CRG_FREQ_1MHz) { + 300293a: fdc42783 lw a5,-36(s0) + 300293e: 53dc lw a5,36(a5) + 3002940: 0785 addi a5,a5,1 + 3002942: fec42703 lw a4,-20(s0) + 3002946: 02f75733 divu a4,a4,a5 + 300294a: 000f47b7 lui a5,0xf4 + 300294e: 24078793 addi a5,a5,576 # f4240 + 3002952: 00f71463 bne a4,a5,300295a + return BASE_STATUS_OK; + 3002956: 4781 li a5,0 + 3002958: a011 j 300295c + } + return BASE_STATUS_ERROR; + 300295a: 4785 li a5,1 +} + 300295c: 853e mv a0,a5 + 300295e: 5432 lw s0,44(sp) + 3002960: 6145 addi sp,sp,48 + 3002962: 8082 ret + +03002964 : + * @brief Get clock frequence + * @param crg CRG_RegStruct + * @retval The frequence fo clock + */ +static inline unsigned int CRG_GetPllRefIni(CRG_PllRefClkSelect pllRefClkSelect) +{ + 3002964: 1101 addi sp,sp,-32 + 3002966: ce22 sw s0,28(sp) + 3002968: 1000 addi s0,sp,32 + 300296a: fea42623 sw a0,-20(s0) + /* The maximum speed of the external clock source is 30000000U. */ + if (pllRefClkSelect == CRG_PLL_REF_CLK_SELECT_XTAL && XTRAIL_FREQ > 30000000U) { + return 0; + } + return (pllRefClkSelect == (unsigned int)CRG_PLL_REF_CLK_SELECT_HOSC) ? HOSC_FREQ : XTRAIL_FREQ; + 300296e: fec42783 lw a5,-20(s0) + 3002972: e791 bnez a5,300297e + 3002974: 017d87b7 lui a5,0x17d8 + 3002978: 84078793 addi a5,a5,-1984 # 17d7840 + 300297c: a029 j 3002986 + 300297e: 01c9c7b7 lui a5,0x1c9c + 3002982: 38078793 addi a5,a5,896 # 1c9c380 +} + 3002986: 853e mv a0,a5 + 3002988: 4472 lw s0,28(sp) + 300298a: 6105 addi sp,sp,32 + 300298c: 8082 ret + +0300298e : + * @brief Get previous division Value before PLL + * @param crg CRG_RegStruct + * @retval Previous Div value + */ +static inline unsigned int CRG_GetPreDivValue(CRG_PllPreDiv pllPredDiv) +{ + 300298e: 7179 addi sp,sp,-48 + 3002990: d622 sw s0,44(sp) + 3002992: 1800 addi s0,sp,48 + 3002994: fca42e23 sw a0,-36(s0) + unsigned int preDiv; + if (pllPredDiv <= CRG_PLL_PREDIV_1) { /* 0 or 1 returns PLL_PREDIV_OUT_1. */ + 3002998: fdc42783 lw a5,-36(s0) + 300299c: e789 bnez a5,30029a6 + preDiv = PLL_PREDIV_OUT_1; + 300299e: 4785 li a5,1 + 30029a0: fef42623 sw a5,-20(s0) + 30029a4: a031 j 30029b0 + } else { + preDiv = pllPredDiv + 1; + 30029a6: fdc42783 lw a5,-36(s0) + 30029aa: 0785 addi a5,a5,1 + 30029ac: fef42623 sw a5,-20(s0) + } + return preDiv; + 30029b0: fec42783 lw a5,-20(s0) +} + 30029b4: 853e mv a0,a5 + 30029b6: 5432 lw s0,44(sp) + 30029b8: 6145 addi sp,sp,48 + 30029ba: 8082 ret + +030029bc : + * @brief Get PLL loop divider ratio + * @param crg CRG_RegStruct + * @retval PLL loop divider ratio + */ +static inline unsigned int CRG_GetPllFbDivValue(unsigned int pllFbDiv) +{ + 30029bc: 7179 addi sp,sp,-48 + 30029be: d622 sw s0,44(sp) + 30029c0: 1800 addi s0,sp,48 + 30029c2: fca42e23 sw a0,-36(s0) + unsigned int div = pllFbDiv; + 30029c6: fdc42783 lw a5,-36(s0) + 30029ca: fef42623 sw a5,-20(s0) + /* Check the validity of the minimum frequency multiplication parameter. */ + if (div < CRG_PLL_FBDIV_MIN) { + 30029ce: fec42703 lw a4,-20(s0) + 30029d2: 4795 li a5,5 + 30029d4: 00e7e563 bltu a5,a4,30029de + div = CRG_PLL_FBDIV_MIN; + 30029d8: 4799 li a5,6 + 30029da: fef42623 sw a5,-20(s0) + } + /* Check the validity of the maximum frequency multiplication parameter. */ + if (div > CRG_PLL_FBDIV_MAX) { + 30029de: fec42703 lw a4,-20(s0) + 30029e2: 07f00793 li a5,127 + 30029e6: 00e7f663 bgeu a5,a4,30029f2 + div = CRG_PLL_FBDIV_MAX; + 30029ea: 07f00793 li a5,127 + 30029ee: fef42623 sw a5,-20(s0) + } + return div; + 30029f2: fec42783 lw a5,-20(s0) +} + 30029f6: 853e mv a0,a5 + 30029f8: 5432 lw s0,44(sp) + 30029fa: 6145 addi sp,sp,48 + 30029fc: 8082 ret + +030029fe : + * @brief Get post division Value after PLL + * @param crg CRG_RegStruct + * @retval Previous Div value + */ +static inline unsigned int CRG_GetPllPostDivValue(unsigned int pllPostDiv) +{ + 30029fe: 7179 addi sp,sp,-48 + 3002a00: d622 sw s0,44(sp) + 3002a02: 1800 addi s0,sp,48 + 3002a04: fca42e23 sw a0,-36(s0) + unsigned int div = pllPostDiv; + 3002a08: fdc42783 lw a5,-36(s0) + 3002a0c: fef42623 sw a5,-20(s0) + if (div > CRG_PLL_POSTDIV_8) { + 3002a10: fec42703 lw a4,-20(s0) + 3002a14: 479d li a5,7 + 3002a16: 00e7f663 bgeu a5,a4,3002a22 + div = (CRG_PLL_POSTDIV_8 + 1); /* If the postdiv is greater than 8, set this postdiv to 8. */ + 3002a1a: 47a1 li a5,8 + 3002a1c: fef42623 sw a5,-20(s0) + 3002a20: a031 j 3002a2c + } else { + div += 1; + 3002a22: fec42783 lw a5,-20(s0) + 3002a26: 0785 addi a5,a5,1 + 3002a28: fef42623 sw a5,-20(s0) + } + return div; + 3002a2c: fec42783 lw a5,-20(s0) +} + 3002a30: 853e mv a0,a5 + 3002a32: 5432 lw s0,44(sp) + 3002a34: 6145 addi sp,sp,48 + 3002a36: 8082 ret + +03002a38 : + * @param matchInfo IP without Clock select match info + * @param enable BASE_CFG_SET or BASE_CFG_UNSET + * @retval None + */ +static void CRG_IpWoClkSelEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable) +{ + 3002a38: 7179 addi sp,sp,-48 + 3002a3a: d606 sw ra,44(sp) + 3002a3c: d422 sw s0,40(sp) + 3002a3e: 1800 addi s0,sp,48 + 3002a40: fca42e23 sw a0,-36(s0) + 3002a44: fcb42c23 sw a1,-40(s0) + CRG_ASSERT_PARAM(matchInfo != NULL); + 3002a48: fdc42783 lw a5,-36(s0) + 3002a4c: eb89 bnez a5,3002a5e + 3002a4e: 34d00593 li a1,845 + 3002a52: 030097b7 lui a5,0x3009 + 3002a56: 96c78513 addi a0,a5,-1684 # 300896c + 3002a5a: 293d jal ra,3002e98 + 3002a5c: a001 j 3002a5c + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + 3002a5e: 040007b7 lui a5,0x4000 + 3002a62: 4947a783 lw a5,1172(a5) # 4000494 + 3002a66: eb89 bnez a5,3002a78 + 3002a68: 34e00593 li a1,846 + 3002a6c: 030097b7 lui a5,0x3009 + 3002a70: 96c78513 addi a0,a5,-1684 # 300896c + 3002a74: 2115 jal ra,3002e98 + 3002a76: a001 j 3002a76 + + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + 3002a78: 040007b7 lui a5,0x4000 + 3002a7c: 4947a783 lw a5,1172(a5) # 4000494 + 3002a80: fef42623 sw a5,-20(s0) + CRG_IpWoClkSelectCfg *p = (CRG_IpWoClkSelectCfg *)(void *)(base + matchInfo->regOffset); + 3002a84: fdc42783 lw a5,-36(s0) + 3002a88: 279e lhu a5,8(a5) + 3002a8a: 873e mv a4,a5 + 3002a8c: fec42783 lw a5,-20(s0) + 3002a90: 97ba add a5,a5,a4 + 3002a92: fef42423 sw a5,-24(s0) + CRG_IpWoClkSelectCfg cfg; + cfg.value = p->value; + 3002a96: fe842783 lw a5,-24(s0) + 3002a9a: 439c lw a5,0(a5) + 3002a9c: fef42223 sw a5,-28(s0) + if (enable & IP_CLK_ENABLE) { /* Set enable of target ip. */ + 3002aa0: fd842783 lw a5,-40(s0) + 3002aa4: 8b85 andi a5,a5,1 + 3002aa6: c7c1 beqz a5,3002b2e + cfg.BIT.clkEnMask |= 1 << matchInfo->bitOffset; + 3002aa8: fe442783 lw a5,-28(s0) + 3002aac: 9fa1 uxth a5 + 3002aae: 01079713 slli a4,a5,0x10 + 3002ab2: 8741 srai a4,a4,0x10 + 3002ab4: fdc42783 lw a5,-36(s0) + 3002ab8: 27bc lbu a5,10(a5) + 3002aba: 86be mv a3,a5 + 3002abc: 4785 li a5,1 + 3002abe: 00d797b3 sll a5,a5,a3 + 3002ac2: 07c2 slli a5,a5,0x10 + 3002ac4: 87c1 srai a5,a5,0x10 + 3002ac6: 8fd9 or a5,a5,a4 + 3002ac8: 07c2 slli a5,a5,0x10 + 3002aca: 87c1 srai a5,a5,0x10 + 3002acc: 01079693 slli a3,a5,0x10 + 3002ad0: 82c1 srli a3,a3,0x10 + 3002ad2: fe442783 lw a5,-28(s0) + 3002ad6: 6741 lui a4,0x10 + 3002ad8: 177d addi a4,a4,-1 # ffff + 3002ada: 8f75 and a4,a4,a3 + 3002adc: 76c1 lui a3,0xffff0 + 3002ade: 8ff5 and a5,a5,a3 + 3002ae0: 8fd9 or a5,a5,a4 + 3002ae2: fef42223 sw a5,-28(s0) + cfg.BIT.softResetReq &= ~(1 << matchInfo->bitOffset); + 3002ae6: fe442783 lw a5,-28(s0) + 3002aea: 83c1 srli a5,a5,0x10 + 3002aec: 9fa1 uxth a5 + 3002aee: 01079713 slli a4,a5,0x10 + 3002af2: 8741 srai a4,a4,0x10 + 3002af4: fdc42783 lw a5,-36(s0) + 3002af8: 27bc lbu a5,10(a5) + 3002afa: 86be mv a3,a5 + 3002afc: 4785 li a5,1 + 3002afe: 00d797b3 sll a5,a5,a3 + 3002b02: 07c2 slli a5,a5,0x10 + 3002b04: 87c1 srai a5,a5,0x10 + 3002b06: fff7c793 not a5,a5 + 3002b0a: 07c2 slli a5,a5,0x10 + 3002b0c: 87c1 srai a5,a5,0x10 + 3002b0e: 8ff9 and a5,a5,a4 + 3002b10: 07c2 slli a5,a5,0x10 + 3002b12: 87c1 srai a5,a5,0x10 + 3002b14: 01079713 slli a4,a5,0x10 + 3002b18: 8341 srli a4,a4,0x10 + 3002b1a: fe442783 lw a5,-28(s0) + 3002b1e: 0742 slli a4,a4,0x10 + 3002b20: 66c1 lui a3,0x10 + 3002b22: 16fd addi a3,a3,-1 # ffff + 3002b24: 8ff5 and a5,a5,a3 + 3002b26: 8fd9 or a5,a5,a4 + 3002b28: fef42223 sw a5,-28(s0) + 3002b2c: a059 j 3002bb2 + } else { + cfg.BIT.clkEnMask &= ~(1 << matchInfo->bitOffset); /* Disable of target ip. */ + 3002b2e: fe442783 lw a5,-28(s0) + 3002b32: 9fa1 uxth a5 + 3002b34: 01079713 slli a4,a5,0x10 + 3002b38: 8741 srai a4,a4,0x10 + 3002b3a: fdc42783 lw a5,-36(s0) + 3002b3e: 27bc lbu a5,10(a5) + 3002b40: 86be mv a3,a5 + 3002b42: 4785 li a5,1 + 3002b44: 00d797b3 sll a5,a5,a3 + 3002b48: 07c2 slli a5,a5,0x10 + 3002b4a: 87c1 srai a5,a5,0x10 + 3002b4c: fff7c793 not a5,a5 + 3002b50: 07c2 slli a5,a5,0x10 + 3002b52: 87c1 srai a5,a5,0x10 + 3002b54: 8ff9 and a5,a5,a4 + 3002b56: 07c2 slli a5,a5,0x10 + 3002b58: 87c1 srai a5,a5,0x10 + 3002b5a: 01079693 slli a3,a5,0x10 + 3002b5e: 82c1 srli a3,a3,0x10 + 3002b60: fe442783 lw a5,-28(s0) + 3002b64: 6741 lui a4,0x10 + 3002b66: 177d addi a4,a4,-1 # ffff + 3002b68: 8f75 and a4,a4,a3 + 3002b6a: 76c1 lui a3,0xffff0 + 3002b6c: 8ff5 and a5,a5,a3 + 3002b6e: 8fd9 or a5,a5,a4 + 3002b70: fef42223 sw a5,-28(s0) + cfg.BIT.softResetReq |= (1 << matchInfo->bitOffset); + 3002b74: fe442783 lw a5,-28(s0) + 3002b78: 83c1 srli a5,a5,0x10 + 3002b7a: 9fa1 uxth a5 + 3002b7c: 01079713 slli a4,a5,0x10 + 3002b80: 8741 srai a4,a4,0x10 + 3002b82: fdc42783 lw a5,-36(s0) + 3002b86: 27bc lbu a5,10(a5) + 3002b88: 86be mv a3,a5 + 3002b8a: 4785 li a5,1 + 3002b8c: 00d797b3 sll a5,a5,a3 + 3002b90: 07c2 slli a5,a5,0x10 + 3002b92: 87c1 srai a5,a5,0x10 + 3002b94: 8fd9 or a5,a5,a4 + 3002b96: 07c2 slli a5,a5,0x10 + 3002b98: 87c1 srai a5,a5,0x10 + 3002b9a: 01079713 slli a4,a5,0x10 + 3002b9e: 8341 srli a4,a4,0x10 + 3002ba0: fe442783 lw a5,-28(s0) + 3002ba4: 0742 slli a4,a4,0x10 + 3002ba6: 66c1 lui a3,0x10 + 3002ba8: 16fd addi a3,a3,-1 # ffff + 3002baa: 8ff5 and a5,a5,a3 + 3002bac: 8fd9 or a5,a5,a4 + 3002bae: fef42223 sw a5,-28(s0) + } + p->value = cfg.value; + 3002bb2: fe442703 lw a4,-28(s0) + 3002bb6: fe842783 lw a5,-24(s0) + 3002bba: c398 sw a4,0(a5) +} + 3002bbc: 0001 nop + 3002bbe: 50b2 lw ra,44(sp) + 3002bc0: 5422 lw s0,40(sp) + 3002bc2: 6145 addi sp,sp,48 + 3002bc4: 8082 ret + +03002bc6 : + * @brief Get Enable status of IP in APB_HS_SUBSYS + * @param matchInfo IP without Clock select match info + * @retval Clock Enable status + */ +static unsigned int CRG_IpWoClkSelEnableGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + 3002bc6: 7179 addi sp,sp,-48 + 3002bc8: d606 sw ra,44(sp) + 3002bca: d422 sw s0,40(sp) + 3002bcc: 1800 addi s0,sp,48 + 3002bce: fca42e23 sw a0,-36(s0) + CRG_ASSERT_PARAM(matchInfo != NULL); + 3002bd2: fdc42783 lw a5,-36(s0) + 3002bd6: eb89 bnez a5,3002be8 + 3002bd8: 36500593 li a1,869 + 3002bdc: 030097b7 lui a5,0x3009 + 3002be0: 96c78513 addi a0,a5,-1684 # 300896c + 3002be4: 2c55 jal ra,3002e98 + 3002be6: a001 j 3002be6 + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + 3002be8: 040007b7 lui a5,0x4000 + 3002bec: 4947a783 lw a5,1172(a5) # 4000494 + 3002bf0: eb89 bnez a5,3002c02 + 3002bf2: 36600593 li a1,870 + 3002bf6: 030097b7 lui a5,0x3009 + 3002bfa: 96c78513 addi a0,a5,-1684 # 300896c + 3002bfe: 2c69 jal ra,3002e98 + 3002c00: a001 j 3002c00 + + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + 3002c02: 040007b7 lui a5,0x4000 + 3002c06: 4947a783 lw a5,1172(a5) # 4000494 + 3002c0a: fef42623 sw a5,-20(s0) + /* Get enable status of target ip. */ + CRG_IpWoClkSelectCfg *p = (CRG_IpWoClkSelectCfg *)(void *)(base + matchInfo->regOffset); + 3002c0e: fdc42783 lw a5,-36(s0) + 3002c12: 279e lhu a5,8(a5) + 3002c14: 873e mv a4,a5 + 3002c16: fec42783 lw a5,-20(s0) + 3002c1a: 97ba add a5,a5,a4 + 3002c1c: fef42423 sw a5,-24(s0) + CRG_IpWoClkSelectCfg cfg; + + cfg.value = p->value; + 3002c20: fe842783 lw a5,-24(s0) + 3002c24: 439c lw a5,0(a5) + 3002c26: fef42223 sw a5,-28(s0) + return (cfg.BIT.clkEnMask & (1 << matchInfo->bitOffset)) == 0 ? false : true; + 3002c2a: fe442783 lw a5,-28(s0) + 3002c2e: 9fa1 uxth a5 + 3002c30: 873e mv a4,a5 + 3002c32: fdc42783 lw a5,-36(s0) + 3002c36: 27bc lbu a5,10(a5) + 3002c38: 40f757b3 sra a5,a4,a5 + 3002c3c: 8b85 andi a5,a5,1 + 3002c3e: 00f037b3 snez a5,a5 + 3002c42: 9f81 uxtb a5 +} + 3002c44: 853e mv a0,a5 + 3002c46: 50b2 lw ra,44(sp) + 3002c48: 5422 lw s0,40(sp) + 3002c4a: 6145 addi sp,sp,48 + 3002c4c: 8082 ret + +03002c4e : + * @param matchInfo IP without Clock select match info + * @param reset BASE_CFG_SET or BASE_CFG_UNSET + * @retval None + */ +static void CRG_IpWoClkSelResetSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int reset) +{ + 3002c4e: 7179 addi sp,sp,-48 + 3002c50: d606 sw ra,44(sp) + 3002c52: d422 sw s0,40(sp) + 3002c54: 1800 addi s0,sp,48 + 3002c56: fca42e23 sw a0,-36(s0) + 3002c5a: fcb42c23 sw a1,-40(s0) + CRG_ASSERT_PARAM(matchInfo != NULL); + 3002c5e: fdc42783 lw a5,-36(s0) + 3002c62: eb89 bnez a5,3002c74 + 3002c64: 37900593 li a1,889 + 3002c68: 030097b7 lui a5,0x3009 + 3002c6c: 96c78513 addi a0,a5,-1684 # 300896c + 3002c70: 2425 jal ra,3002e98 + 3002c72: a001 j 3002c72 + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + 3002c74: 040007b7 lui a5,0x4000 + 3002c78: 4947a783 lw a5,1172(a5) # 4000494 + 3002c7c: eb89 bnez a5,3002c8e + 3002c7e: 37a00593 li a1,890 + 3002c82: 030097b7 lui a5,0x3009 + 3002c86: 96c78513 addi a0,a5,-1684 # 300896c + 3002c8a: 2439 jal ra,3002e98 + 3002c8c: a001 j 3002c8c + + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + 3002c8e: 040007b7 lui a5,0x4000 + 3002c92: 4947a783 lw a5,1172(a5) # 4000494 + 3002c96: fef42623 sw a5,-20(s0) + CRG_IpWoClkSelectCfg *p = (CRG_IpWoClkSelectCfg *)(void *)(base + matchInfo->regOffset); + 3002c9a: fdc42783 lw a5,-36(s0) + 3002c9e: 279e lhu a5,8(a5) + 3002ca0: 873e mv a4,a5 + 3002ca2: fec42783 lw a5,-20(s0) + 3002ca6: 97ba add a5,a5,a4 + 3002ca8: fef42423 sw a5,-24(s0) + CRG_IpWoClkSelectCfg cfg; + cfg.value = p->value; + 3002cac: fe842783 lw a5,-24(s0) + 3002cb0: 439c lw a5,0(a5) + 3002cb2: fef42223 sw a5,-28(s0) + if (reset & BASE_CFG_SET) { + 3002cb6: fd842783 lw a5,-40(s0) + 3002cba: 8b85 andi a5,a5,1 + 3002cbc: c3a9 beqz a5,3002cfe + cfg.BIT.softResetReq |= 1 << matchInfo->bitOffset; /* reset of target ip. */ + 3002cbe: fe442783 lw a5,-28(s0) + 3002cc2: 83c1 srli a5,a5,0x10 + 3002cc4: 9fa1 uxth a5 + 3002cc6: 01079713 slli a4,a5,0x10 + 3002cca: 8741 srai a4,a4,0x10 + 3002ccc: fdc42783 lw a5,-36(s0) + 3002cd0: 27bc lbu a5,10(a5) + 3002cd2: 86be mv a3,a5 + 3002cd4: 4785 li a5,1 + 3002cd6: 00d797b3 sll a5,a5,a3 + 3002cda: 07c2 slli a5,a5,0x10 + 3002cdc: 87c1 srai a5,a5,0x10 + 3002cde: 8fd9 or a5,a5,a4 + 3002ce0: 07c2 slli a5,a5,0x10 + 3002ce2: 87c1 srai a5,a5,0x10 + 3002ce4: 01079713 slli a4,a5,0x10 + 3002ce8: 8341 srli a4,a4,0x10 + 3002cea: fe442783 lw a5,-28(s0) + 3002cee: 0742 slli a4,a4,0x10 + 3002cf0: 66c1 lui a3,0x10 + 3002cf2: 16fd addi a3,a3,-1 # ffff + 3002cf4: 8ff5 and a5,a5,a3 + 3002cf6: 8fd9 or a5,a5,a4 + 3002cf8: fef42223 sw a5,-28(s0) + 3002cfc: a0a1 j 3002d44 + } else { + cfg.BIT.softResetReq &= ~(1 << matchInfo->bitOffset); /* Undo reset of target ip. */ + 3002cfe: fe442783 lw a5,-28(s0) + 3002d02: 83c1 srli a5,a5,0x10 + 3002d04: 9fa1 uxth a5 + 3002d06: 01079713 slli a4,a5,0x10 + 3002d0a: 8741 srai a4,a4,0x10 + 3002d0c: fdc42783 lw a5,-36(s0) + 3002d10: 27bc lbu a5,10(a5) + 3002d12: 86be mv a3,a5 + 3002d14: 4785 li a5,1 + 3002d16: 00d797b3 sll a5,a5,a3 + 3002d1a: 07c2 slli a5,a5,0x10 + 3002d1c: 87c1 srai a5,a5,0x10 + 3002d1e: fff7c793 not a5,a5 + 3002d22: 07c2 slli a5,a5,0x10 + 3002d24: 87c1 srai a5,a5,0x10 + 3002d26: 8ff9 and a5,a5,a4 + 3002d28: 07c2 slli a5,a5,0x10 + 3002d2a: 87c1 srai a5,a5,0x10 + 3002d2c: 01079713 slli a4,a5,0x10 + 3002d30: 8341 srli a4,a4,0x10 + 3002d32: fe442783 lw a5,-28(s0) + 3002d36: 0742 slli a4,a4,0x10 + 3002d38: 66c1 lui a3,0x10 + 3002d3a: 16fd addi a3,a3,-1 # ffff + 3002d3c: 8ff5 and a5,a5,a3 + 3002d3e: 8fd9 or a5,a5,a4 + 3002d40: fef42223 sw a5,-28(s0) + } + p->value = cfg.value; + 3002d44: fe442703 lw a4,-28(s0) + 3002d48: fe842783 lw a5,-24(s0) + 3002d4c: c398 sw a4,0(a5) +} + 3002d4e: 0001 nop + 3002d50: 50b2 lw ra,44(sp) + 3002d52: 5422 lw s0,40(sp) + 3002d54: 6145 addi sp,sp,48 + 3002d56: 8082 ret + +03002d58 : + * @brief Get Reset status of IP in APB_HS_SUBSYS + * @param matchInfo IP without Clock select match info + * @retval Clock select reset status + */ +static unsigned int CRG_IpWoClkSelResetGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + 3002d58: 7179 addi sp,sp,-48 + 3002d5a: d606 sw ra,44(sp) + 3002d5c: d422 sw s0,40(sp) + 3002d5e: 1800 addi s0,sp,48 + 3002d60: fca42e23 sw a0,-36(s0) + CRG_ASSERT_PARAM(matchInfo != NULL); + 3002d64: fdc42783 lw a5,-36(s0) + 3002d68: eb89 bnez a5,3002d7a + 3002d6a: 38f00593 li a1,911 + 3002d6e: 030097b7 lui a5,0x3009 + 3002d72: 96c78513 addi a0,a5,-1684 # 300896c + 3002d76: 220d jal ra,3002e98 + 3002d78: a001 j 3002d78 + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + 3002d7a: 040007b7 lui a5,0x4000 + 3002d7e: 4947a783 lw a5,1172(a5) # 4000494 + 3002d82: eb89 bnez a5,3002d94 + 3002d84: 39000593 li a1,912 + 3002d88: 030097b7 lui a5,0x3009 + 3002d8c: 96c78513 addi a0,a5,-1684 # 300896c + 3002d90: 2221 jal ra,3002e98 + 3002d92: a001 j 3002d92 + + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + 3002d94: 040007b7 lui a5,0x4000 + 3002d98: 4947a783 lw a5,1172(a5) # 4000494 + 3002d9c: fef42623 sw a5,-20(s0) + /* Get the reset status of target ip. */ + CRG_IpWoClkSelectCfg *p = (CRG_IpWoClkSelectCfg *)(void *)(base + matchInfo->regOffset); + 3002da0: fdc42783 lw a5,-36(s0) + 3002da4: 279e lhu a5,8(a5) + 3002da6: 873e mv a4,a5 + 3002da8: fec42783 lw a5,-20(s0) + 3002dac: 97ba add a5,a5,a4 + 3002dae: fef42423 sw a5,-24(s0) + CRG_IpWoClkSelectCfg cfg; + cfg.value = p->value; + 3002db2: fe842783 lw a5,-24(s0) + 3002db6: 439c lw a5,0(a5) + 3002db8: fef42223 sw a5,-28(s0) + return (cfg.BIT.softResetReq & (1 << matchInfo->bitOffset)) ? BASE_CFG_SET : BASE_CFG_UNSET; + 3002dbc: fe442783 lw a5,-28(s0) + 3002dc0: 83c1 srli a5,a5,0x10 + 3002dc2: 9fa1 uxth a5 + 3002dc4: 873e mv a4,a5 + 3002dc6: fdc42783 lw a5,-36(s0) + 3002dca: 27bc lbu a5,10(a5) + 3002dcc: 40f757b3 sra a5,a4,a5 + 3002dd0: 8b85 andi a5,a5,1 + 3002dd2: 00f037b3 snez a5,a5 + 3002dd6: 9f81 uxtb a5 +} + 3002dd8: 853e mv a0,a5 + 3002dda: 50b2 lw ra,44(sp) + 3002ddc: 5422 lw s0,40(sp) + 3002dde: 6145 addi sp,sp,48 + 3002de0: 8082 ret + +03002de2 : + * @param matchInfo ADC match info + * @param enable IP_CLK_ENABLE + * @retval None + */ +static void CRG_AdcEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable) +{ + 3002de2: 7179 addi sp,sp,-48 + 3002de4: d606 sw ra,44(sp) + 3002de6: d422 sw s0,40(sp) + 3002de8: 1800 addi s0,sp,48 + 3002dea: fca42e23 sw a0,-36(s0) + 3002dee: fcb42c23 sw a1,-40(s0) + CRG_ASSERT_PARAM(matchInfo != NULL); + 3002df2: fdc42783 lw a5,-36(s0) + 3002df6: eb89 bnez a5,3002e08 + 3002df8: 3a200593 li a1,930 + 3002dfc: 030097b7 lui a5,0x3009 + 3002e00: 96c78513 addi a0,a5,-1684 # 300896c + 3002e04: 2851 jal ra,3002e98 + 3002e06: a001 j 3002e06 + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + 3002e08: 040007b7 lui a5,0x4000 + 3002e0c: 4947a783 lw a5,1172(a5) # 4000494 + 3002e10: eb89 bnez a5,3002e22 + 3002e12: 3a300593 li a1,931 + 3002e16: 030097b7 lui a5,0x3009 + 3002e1a: 96c78513 addi a0,a5,-1684 # 300896c + 3002e1e: 28ad jal ra,3002e98 + 3002e20: a001 j 3002e20 + + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + 3002e22: 040007b7 lui a5,0x4000 + 3002e26: 4947a783 lw a5,1172(a5) # 4000494 + 3002e2a: fef42623 sw a5,-20(s0) + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + 3002e2e: fdc42783 lw a5,-36(s0) + 3002e32: 279e lhu a5,8(a5) + 3002e34: 873e mv a4,a5 + 3002e36: fec42783 lw a5,-20(s0) + 3002e3a: 97ba add a5,a5,a4 + 3002e3c: fef42423 sw a5,-24(s0) + CRG_AdcIpCfg cfg; + cfg.value[1] = p->value[1]; + 3002e40: fe842783 lw a5,-24(s0) + 3002e44: 43dc lw a5,4(a5) + 3002e46: fef42223 sw a5,-28(s0) + if (enable) { /* Enables and Deassert reset the ADC clock. */ + 3002e4a: fd842783 lw a5,-40(s0) + 3002e4e: cf99 beqz a5,3002e6c + cfg.BIT.clk_adc_cken = BASE_CFG_SET; + 3002e50: fe442783 lw a5,-28(s0) + 3002e54: 0017e793 ori a5,a5,1 + 3002e58: fef42223 sw a5,-28(s0) + cfg.BIT.adc_srst_req = BASE_CFG_UNSET; + 3002e5c: fe442783 lw a5,-28(s0) + 3002e60: 7741 lui a4,0xffff0 + 3002e62: 177d addi a4,a4,-1 # fffeffff + 3002e64: 8ff9 and a5,a5,a4 + 3002e66: fef42223 sw a5,-28(s0) + 3002e6a: a829 j 3002e84 + } else { /* Disable and reset the ADC clock. */ + cfg.BIT.clk_adc_cken = BASE_CFG_UNSET; + 3002e6c: fe442783 lw a5,-28(s0) + 3002e70: 9bf9 andi a5,a5,-2 + 3002e72: fef42223 sw a5,-28(s0) + cfg.BIT.adc_srst_req = BASE_CFG_UNSET; + 3002e76: fe442783 lw a5,-28(s0) + 3002e7a: 7741 lui a4,0xffff0 + 3002e7c: 177d addi a4,a4,-1 # fffeffff + 3002e7e: 8ff9 and a5,a5,a4 + 3002e80: fef42223 sw a5,-28(s0) + } + p->value[1] = cfg.value[1]; + 3002e84: fe442703 lw a4,-28(s0) + 3002e88: fe842783 lw a5,-24(s0) + 3002e8c: c3d8 sw a4,4(a5) +} + 3002e8e: 0001 nop + 3002e90: 50b2 lw ra,44(sp) + 3002e92: 5422 lw s0,40(sp) + 3002e94: 6145 addi sp,sp,48 + 3002e96: 8082 ret + +03002e98 : + 3002e98: b70fe06f j 3001208 + +03002e9c : + * @brief Get Enable status of ADC + * @param matchInfo ADC match info + * @retval Cken of ADC + */ +static unsigned int CRG_AdcEnableGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + 3002e9c: 7179 addi sp,sp,-48 + 3002e9e: d606 sw ra,44(sp) + 3002ea0: d422 sw s0,40(sp) + 3002ea2: 1800 addi s0,sp,48 + 3002ea4: fca42e23 sw a0,-36(s0) + CRG_ASSERT_PARAM(matchInfo != NULL); + 3002ea8: fdc42783 lw a5,-36(s0) + 3002eac: eb89 bnez a5,3002ebe + 3002eae: 3ba00593 li a1,954 + 3002eb2: 030097b7 lui a5,0x3009 + 3002eb6: 96c78513 addi a0,a5,-1684 # 300896c + 3002eba: 3ff9 jal ra,3002e98 + 3002ebc: a001 j 3002ebc + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + 3002ebe: 040007b7 lui a5,0x4000 + 3002ec2: 4947a783 lw a5,1172(a5) # 4000494 + 3002ec6: eb89 bnez a5,3002ed8 + 3002ec8: 3bb00593 li a1,955 + 3002ecc: 030097b7 lui a5,0x3009 + 3002ed0: 96c78513 addi a0,a5,-1684 # 300896c + 3002ed4: 37d1 jal ra,3002e98 + 3002ed6: a001 j 3002ed6 + unsigned int enable; + /* Get the enable status of the ADC clock gating. */ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + 3002ed8: 040007b7 lui a5,0x4000 + 3002edc: 4947a783 lw a5,1172(a5) # 4000494 + 3002ee0: fef42623 sw a5,-20(s0) + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + 3002ee4: fdc42783 lw a5,-36(s0) + 3002ee8: 279e lhu a5,8(a5) + 3002eea: 873e mv a4,a5 + 3002eec: fec42783 lw a5,-20(s0) + 3002ef0: 97ba add a5,a5,a4 + 3002ef2: fef42423 sw a5,-24(s0) + enable = ((p->BIT.clk_adc_cken != 0)) ? IP_CLK_ENABLE : IP_CLK_DISABLE; + 3002ef6: fe842783 lw a5,-24(s0) + 3002efa: 43dc lw a5,4(a5) + 3002efc: 8b85 andi a5,a5,1 + 3002efe: 9f81 uxtb a5 + 3002f00: c399 beqz a5,3002f06 + 3002f02: 4785 li a5,1 + 3002f04: a011 j 3002f08 + 3002f06: 4781 li a5,0 + 3002f08: fef42223 sw a5,-28(s0) + return enable; + 3002f0c: fe442783 lw a5,-28(s0) +} + 3002f10: 853e mv a0,a5 + 3002f12: 50b2 lw ra,44(sp) + 3002f14: 5422 lw s0,40(sp) + 3002f16: 6145 addi sp,sp,48 + 3002f18: 8082 ret + +03002f1a : + * @param matchInfo ADC match info + * @param clkSelect @see CRG_AdcClkSelect + * @retval None + */ +static void CRG_AdcClkSelectSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int clkSelect) +{ + 3002f1a: 7179 addi sp,sp,-48 + 3002f1c: d606 sw ra,44(sp) + 3002f1e: d422 sw s0,40(sp) + 3002f20: 1800 addi s0,sp,48 + 3002f22: fca42e23 sw a0,-36(s0) + 3002f26: fcb42c23 sw a1,-40(s0) + CRG_ASSERT_PARAM(matchInfo != NULL); + 3002f2a: fdc42783 lw a5,-36(s0) + 3002f2e: eb89 bnez a5,3002f40 + 3002f30: 3cc00593 li a1,972 + 3002f34: 030097b7 lui a5,0x3009 + 3002f38: 96c78513 addi a0,a5,-1684 # 300896c + 3002f3c: 3fb1 jal ra,3002e98 + 3002f3e: a001 j 3002f3e + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + 3002f40: 040007b7 lui a5,0x4000 + 3002f44: 4947a783 lw a5,1172(a5) # 4000494 + 3002f48: eb89 bnez a5,3002f5a + 3002f4a: 3cd00593 li a1,973 + 3002f4e: 030097b7 lui a5,0x3009 + 3002f52: 96c78513 addi a0,a5,-1684 # 300896c + 3002f56: 3789 jal ra,3002e98 + 3002f58: a001 j 3002f58 + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + 3002f5a: 040007b7 lui a5,0x4000 + 3002f5e: 4947a703 lw a4,1172(a5) # 4000494 + 3002f62: 100007b7 lui a5,0x10000 + 3002f66: 00f70a63 beq a4,a5,3002f7a + 3002f6a: 3ce00593 li a1,974 + 3002f6e: 030097b7 lui a5,0x3009 + 3002f72: 96c78513 addi a0,a5,-1684 # 300896c + 3002f76: 370d jal ra,3002e98 + 3002f78: a001 j 3002f78 + CRG_PARAM_CHECK_NO_RET(IsCrgAdcClkModeSelect(clkSelect)); + 3002f7a: fd842503 lw a0,-40(s0) + 3002f7e: 810ff0ef jal ra,3001f8e + 3002f82: 87aa mv a5,a0 + 3002f84: 0017c793 xori a5,a5,1 + 3002f88: 9f81 uxtb a5 + 3002f8a: cb89 beqz a5,3002f9c + 3002f8c: 3cf00593 li a1,975 + 3002f90: 030097b7 lui a5,0x3009 + 3002f94: 96c78513 addi a0,a5,-1684 # 300896c + 3002f98: 3701 jal ra,3002e98 + 3002f9a: a89d j 3003010 + + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + 3002f9c: 040007b7 lui a5,0x4000 + 3002fa0: 4947a783 lw a5,1172(a5) # 4000494 + 3002fa4: fef42623 sw a5,-20(s0) + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + 3002fa8: fdc42783 lw a5,-36(s0) + 3002fac: 279e lhu a5,8(a5) + 3002fae: 873e mv a4,a5 + 3002fb0: fec42783 lw a5,-20(s0) + 3002fb4: 97ba add a5,a5,a4 + 3002fb6: fef42423 sw a5,-24(s0) + if (clkSelect == CRG_ADC_CLK_SYN_CORE) { + 3002fba: fd842703 lw a4,-40(s0) + 3002fbe: 478d li a5,3 + 3002fc0: 00f71a63 bne a4,a5,3002fd4 + p->BIT.cfg_adc_ckmode_sel = BASE_CFG_SET; /* use sync clock */ + 3002fc4: fe842703 lw a4,-24(s0) + 3002fc8: 435c lw a5,4(a4) + 3002fca: 010006b7 lui a3,0x1000 + 3002fce: 8fd5 or a5,a5,a3 + 3002fd0: c35c sw a5,4(a4) + 3002fd2: a83d j 3003010 + } else { + DCL_SYSCTRL_CrgWriteProtectionDisable(); + 3002fd4: cd7fe0ef jal ra,3001caa + g_crgBaseAddr->PERI_CRG64.BIT.clk_pst2_sw_sel = clkSelect; /* write clock selection */ + 3002fd8: 040007b7 lui a5,0x4000 + 3002fdc: 4947a703 lw a4,1172(a5) # 4000494 + 3002fe0: fd842783 lw a5,-40(s0) + 3002fe4: 8b8d andi a5,a5,3 + 3002fe6: 0ff7f693 andi a3,a5,255 + 3002fea: 10072783 lw a5,256(a4) + 3002fee: 8a8d andi a3,a3,3 + 3002ff0: 0692 slli a3,a3,0x4 + 3002ff2: fcf7f793 andi a5,a5,-49 + 3002ff6: 8fd5 or a5,a5,a3 + 3002ff8: 10f72023 sw a5,256(a4) + DCL_SYSCTRL_CrgWriteProtectionEnable(); + 3002ffc: cd7fe0ef jal ra,3001cd2 + p->BIT.cfg_adc_ckmode_sel = BASE_CFG_UNSET; + 3003000: fe842703 lw a4,-24(s0) + 3003004: 435c lw a5,4(a4) + 3003006: ff0006b7 lui a3,0xff000 + 300300a: 16fd addi a3,a3,-1 # feffffff + 300300c: 8ff5 and a5,a5,a3 + 300300e: c35c sw a5,4(a4) + } +} + 3003010: 50b2 lw ra,44(sp) + 3003012: 5422 lw s0,40(sp) + 3003014: 6145 addi sp,sp,48 + 3003016: 8082 ret + +03003018 : + * @brief Get ADC Clock Select + * @param matchInfo ADC match info + * @retval Adc Clock select @see CRG_AdcClkSelect + */ +static unsigned int CRG_AdcClkSelectGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + 3003018: 7179 addi sp,sp,-48 + 300301a: d606 sw ra,44(sp) + 300301c: d422 sw s0,40(sp) + 300301e: 1800 addi s0,sp,48 + 3003020: fca42e23 sw a0,-36(s0) + CRG_ASSERT_PARAM(matchInfo != NULL); + 3003024: fdc42783 lw a5,-36(s0) + 3003028: eb89 bnez a5,300303a + 300302a: 3e400593 li a1,996 + 300302e: 030097b7 lui a5,0x3009 + 3003032: 96c78513 addi a0,a5,-1684 # 300896c + 3003036: 358d jal ra,3002e98 + 3003038: a001 j 3003038 + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + 300303a: 040007b7 lui a5,0x4000 + 300303e: 4947a783 lw a5,1172(a5) # 4000494 + 3003042: eb89 bnez a5,3003054 + 3003044: 3e500593 li a1,997 + 3003048: 030097b7 lui a5,0x3009 + 300304c: 96c78513 addi a0,a5,-1684 # 300896c + 3003050: 35a1 jal ra,3002e98 + 3003052: a001 j 3003052 + + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + 3003054: 040007b7 lui a5,0x4000 + 3003058: 4947a783 lw a5,1172(a5) # 4000494 + 300305c: fef42623 sw a5,-20(s0) + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + 3003060: fdc42783 lw a5,-36(s0) + 3003064: 279e lhu a5,8(a5) + 3003066: 873e mv a4,a5 + 3003068: fec42783 lw a5,-20(s0) + 300306c: 97ba add a5,a5,a4 + 300306e: fef42423 sw a5,-24(s0) + if (p->BIT.cfg_adc_ckmode_sel == BASE_CFG_SET) { + 3003072: fe842783 lw a5,-24(s0) + 3003076: 43dc lw a5,4(a5) + 3003078: 83e1 srli a5,a5,0x18 + 300307a: 8b85 andi a5,a5,1 + 300307c: 0ff7f713 andi a4,a5,255 + 3003080: 4785 li a5,1 + 3003082: 00f71463 bne a4,a5,300308a + return CRG_ADC_CLK_SYN_CORE; /* Synchronous clock signal */ + 3003086: 478d li a5,3 + 3003088: a811 j 300309c + } + return g_crgBaseAddr->PERI_CRG64.BIT.clk_pst2_sw_sel; /* asynchronous clock signal */ + 300308a: 040007b7 lui a5,0x4000 + 300308e: 4947a783 lw a5,1172(a5) # 4000494 + 3003092: 1007a783 lw a5,256(a5) + 3003096: 8391 srli a5,a5,0x4 + 3003098: 8b8d andi a5,a5,3 + 300309a: 9f81 uxtb a5 +} + 300309c: 853e mv a0,a5 + 300309e: 50b2 lw ra,44(sp) + 30030a0: 5422 lw s0,40(sp) + 30030a2: 6145 addi sp,sp,48 + 30030a4: 8082 ret + +030030a6 : + * @param matchInfo ADC match info + * @param div Adc clock division + * @retval None + */ +static void CRG_AdcDivSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int div) +{ + 30030a6: 7179 addi sp,sp,-48 + 30030a8: d606 sw ra,44(sp) + 30030aa: d422 sw s0,40(sp) + 30030ac: 1800 addi s0,sp,48 + 30030ae: fca42e23 sw a0,-36(s0) + 30030b2: fcb42c23 sw a1,-40(s0) + CRG_ASSERT_PARAM(matchInfo != NULL); + 30030b6: fdc42783 lw a5,-36(s0) + 30030ba: eb89 bnez a5,30030cc + 30030bc: 3f700593 li a1,1015 + 30030c0: 030097b7 lui a5,0x3009 + 30030c4: 96c78513 addi a0,a5,-1684 # 300896c + 30030c8: 3bc1 jal ra,3002e98 + 30030ca: a001 j 30030ca + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + 30030cc: 040007b7 lui a5,0x4000 + 30030d0: 4947a783 lw a5,1172(a5) # 4000494 + 30030d4: eb89 bnez a5,30030e6 + 30030d6: 3f800593 li a1,1016 + 30030da: 030097b7 lui a5,0x3009 + 30030de: 96c78513 addi a0,a5,-1684 # 300896c + 30030e2: 3b5d jal ra,3002e98 + 30030e4: a001 j 30030e4 + CRG_PARAM_CHECK_NO_RET(IsCrgAdcClkDiv(div)); + 30030e6: fd842503 lw a0,-40(s0) + 30030ea: ee5fe0ef jal ra,3001fce + 30030ee: 87aa mv a5,a0 + 30030f0: 0017c793 xori a5,a5,1 + 30030f4: 9f81 uxtb a5 + 30030f6: cb89 beqz a5,3003108 + 30030f8: 3f900593 li a1,1017 + 30030fc: 030097b7 lui a5,0x3009 + 3003100: 96c78513 addi a0,a5,-1684 # 300896c + 3003104: 3b51 jal ra,3002e98 + 3003106: a885 j 3003176 + + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + 3003108: 040007b7 lui a5,0x4000 + 300310c: 4947a783 lw a5,1172(a5) # 4000494 + 3003110: fef42623 sw a5,-20(s0) + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + 3003114: fdc42783 lw a5,-36(s0) + 3003118: 279e lhu a5,8(a5) + 300311a: 873e mv a4,a5 + 300311c: fec42783 lw a5,-20(s0) + 3003120: 97ba add a5,a5,a4 + 3003122: fef42423 sw a5,-24(s0) + unsigned int clkMode = p->BIT.cfg_adc_ckmode_sel; + 3003126: fe842783 lw a5,-24(s0) + 300312a: 43dc lw a5,4(a5) + 300312c: 83e1 srli a5,a5,0x18 + 300312e: 8b85 andi a5,a5,1 + 3003130: 9f81 uxtb a5 + 3003132: fef42223 sw a5,-28(s0) + if (clkMode == CRG_ADC_CLK_SYNCHRONOUS) { + 3003136: fe442703 lw a4,-28(s0) + 300313a: 4785 li a5,1 + 300313c: 02f71163 bne a4,a5,300315e + p->BIT.clk_adc_div1 = div; /* write div to I1 */ + 3003140: fd842783 lw a5,-40(s0) + 3003144: 8b8d andi a5,a5,3 + 3003146: 0ff7f693 andi a3,a5,255 + 300314a: fe842703 lw a4,-24(s0) + 300314e: 431c lw a5,0(a4) + 3003150: 8a8d andi a3,a3,3 + 3003152: 06a2 slli a3,a3,0x8 + 3003154: cff7f793 andi a5,a5,-769 + 3003158: 8fd5 or a5,a5,a3 + 300315a: c31c sw a5,0(a4) + 300315c: a829 j 3003176 + } else { + p->BIT.clk_adc_div0 = div; /* write div to I0 */ + 300315e: fd842783 lw a5,-40(s0) + 3003162: 8b8d andi a5,a5,3 + 3003164: 0ff7f693 andi a3,a5,255 + 3003168: fe842703 lw a4,-24(s0) + 300316c: 431c lw a5,0(a4) + 300316e: 8a8d andi a3,a3,3 + 3003170: 9bf1 andi a5,a5,-4 + 3003172: 8fd5 or a5,a5,a3 + 3003174: c31c sw a5,0(a4) + } +} + 3003176: 50b2 lw ra,44(sp) + 3003178: 5422 lw s0,40(sp) + 300317a: 6145 addi sp,sp,48 + 300317c: 8082 ret + +0300317e : + * @brief Get ADC clock division + * @param matchInfo ADC match info + * @retval Adc clock division + */ +static unsigned int CRG_AdcDivGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + 300317e: 7179 addi sp,sp,-48 + 3003180: d606 sw ra,44(sp) + 3003182: d422 sw s0,40(sp) + 3003184: 1800 addi s0,sp,48 + 3003186: fca42e23 sw a0,-36(s0) + CRG_ASSERT_PARAM(matchInfo != NULL); + 300318a: fdc42783 lw a5,-36(s0) + 300318e: eb89 bnez a5,30031a0 + 3003190: 40c00593 li a1,1036 + 3003194: 030097b7 lui a5,0x3009 + 3003198: 96c78513 addi a0,a5,-1684 # 300896c + 300319c: 39f5 jal ra,3002e98 + 300319e: a001 j 300319e + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + 30031a0: 040007b7 lui a5,0x4000 + 30031a4: 4947a783 lw a5,1172(a5) # 4000494 + 30031a8: eb89 bnez a5,30031ba + 30031aa: 40d00593 li a1,1037 + 30031ae: 030097b7 lui a5,0x3009 + 30031b2: 96c78513 addi a0,a5,-1684 # 300896c + 30031b6: 31cd jal ra,3002e98 + 30031b8: a001 j 30031b8 + + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + 30031ba: 040007b7 lui a5,0x4000 + 30031be: 4947a783 lw a5,1172(a5) # 4000494 + 30031c2: fef42623 sw a5,-20(s0) + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + 30031c6: fdc42783 lw a5,-36(s0) + 30031ca: 279e lhu a5,8(a5) + 30031cc: 873e mv a4,a5 + 30031ce: fec42783 lw a5,-20(s0) + 30031d2: 97ba add a5,a5,a4 + 30031d4: fef42423 sw a5,-24(s0) + + unsigned int clkMode = p->BIT.cfg_adc_ckmode_sel; + 30031d8: fe842783 lw a5,-24(s0) + 30031dc: 43dc lw a5,4(a5) + 30031de: 83e1 srli a5,a5,0x18 + 30031e0: 8b85 andi a5,a5,1 + 30031e2: 9f81 uxtb a5 + 30031e4: fef42223 sw a5,-28(s0) + + if (clkMode == CRG_ADC_CLK_SYNCHRONOUS) { + 30031e8: fe442703 lw a4,-28(s0) + 30031ec: 4785 li a5,1 + 30031ee: 00f71963 bne a4,a5,3003200 + return p->BIT.clk_adc_div1; /* return div value I1 */ + 30031f2: fe842783 lw a5,-24(s0) + 30031f6: 439c lw a5,0(a5) + 30031f8: 83a1 srli a5,a5,0x8 + 30031fa: 8b8d andi a5,a5,3 + 30031fc: 9f81 uxtb a5 + 30031fe: a031 j 300320a + } + return p->BIT.clk_adc_div0; /* return div valye I0 */ + 3003200: fe842783 lw a5,-24(s0) + 3003204: 439c lw a5,0(a5) + 3003206: 8b8d andi a5,a5,3 + 3003208: 9f81 uxtb a5 +} + 300320a: 853e mv a0,a5 + 300320c: 50b2 lw ra,44(sp) + 300320e: 5422 lw s0,40(sp) + 3003210: 6145 addi sp,sp,48 + 3003212: 8082 ret + +03003214 : + * @brief Enable Clock of EFC + * @param matchInfo EFC match Info + * @param enable IP_CLK_ENABLE or IP_CRG_DISABLE + */ +static void CRG_EfcEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable) +{ + 3003214: 7179 addi sp,sp,-48 + 3003216: d606 sw ra,44(sp) + 3003218: d422 sw s0,40(sp) + 300321a: 1800 addi s0,sp,48 + 300321c: fca42e23 sw a0,-36(s0) + 3003220: fcb42c23 sw a1,-40(s0) + CRG_ASSERT_PARAM(matchInfo != NULL); + 3003224: fdc42783 lw a5,-36(s0) + 3003228: eb89 bnez a5,300323a + 300322a: 42100593 li a1,1057 + 300322e: 030097b7 lui a5,0x3009 + 3003232: 96c78513 addi a0,a5,-1684 # 300896c + 3003236: 318d jal ra,3002e98 + 3003238: a001 j 3003238 + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + 300323a: 040007b7 lui a5,0x4000 + 300323e: 4947a783 lw a5,1172(a5) # 4000494 + 3003242: eb89 bnez a5,3003254 + 3003244: 42200593 li a1,1058 + 3003248: 030097b7 lui a5,0x3009 + 300324c: 96c78513 addi a0,a5,-1684 # 300896c + 3003250: 31a1 jal ra,3002e98 + 3003252: a001 j 3003252 + /* Enables or disables EFC clock gating. */ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + 3003254: 040007b7 lui a5,0x4000 + 3003258: 4947a783 lw a5,1172(a5) # 4000494 + 300325c: fef42623 sw a5,-20(s0) + CRG_EfcIpCfg *p = (CRG_EfcIpCfg *)(void *)(base + matchInfo->regOffset); + 3003260: fdc42783 lw a5,-36(s0) + 3003264: 279e lhu a5,8(a5) + 3003266: 873e mv a4,a5 + 3003268: fec42783 lw a5,-20(s0) + 300326c: 97ba add a5,a5,a4 + 300326e: fef42423 sw a5,-24(s0) + p->BIT.eflash_cken = (enable & IP_CLK_ENABLE) ? BASE_CFG_SET : BASE_CFG_UNSET; + 3003272: fd842783 lw a5,-40(s0) + 3003276: 8b85 andi a5,a5,1 + 3003278: 0ff7f693 andi a3,a5,255 + 300327c: fe842703 lw a4,-24(s0) + 3003280: 431c lw a5,0(a4) + 3003282: 8a85 andi a3,a3,1 + 3003284: 9bf9 andi a5,a5,-2 + 3003286: 8fd5 or a5,a5,a3 + 3003288: c31c sw a5,0(a4) +} + 300328a: 0001 nop + 300328c: 50b2 lw ra,44(sp) + 300328e: 5422 lw s0,40(sp) + 3003290: 6145 addi sp,sp,48 + 3003292: 8082 ret + +03003294 : + * @brief Disable Clock of EFC + * @param matchInfo EFC match Info + * @return unsigned int IP_CLK_ENABLE or IP_CRG_DISABLE + */ +static unsigned int CRG_EfcEnableGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + 3003294: 7179 addi sp,sp,-48 + 3003296: d606 sw ra,44(sp) + 3003298: d422 sw s0,40(sp) + 300329a: 1800 addi s0,sp,48 + 300329c: fca42e23 sw a0,-36(s0) + CRG_ASSERT_PARAM(matchInfo != NULL); + 30032a0: fdc42783 lw a5,-36(s0) + 30032a4: eb89 bnez a5,30032b6 + 30032a6: 43000593 li a1,1072 + 30032aa: 030097b7 lui a5,0x3009 + 30032ae: 96c78513 addi a0,a5,-1684 # 300896c + 30032b2: 36dd jal ra,3002e98 + 30032b4: a001 j 30032b4 + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + 30032b6: 040007b7 lui a5,0x4000 + 30032ba: 4947a783 lw a5,1172(a5) # 4000494 + 30032be: eb89 bnez a5,30032d0 + 30032c0: 43100593 li a1,1073 + 30032c4: 030097b7 lui a5,0x3009 + 30032c8: 96c78513 addi a0,a5,-1684 # 300896c + 30032cc: 36f1 jal ra,3002e98 + 30032ce: a001 j 30032ce + /* Get the value of the EFC register in the CRG. */ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + 30032d0: 040007b7 lui a5,0x4000 + 30032d4: 4947a783 lw a5,1172(a5) # 4000494 + 30032d8: fef42623 sw a5,-20(s0) + CRG_EfcIpCfg *p = (CRG_EfcIpCfg *)(void *)(base + matchInfo->regOffset); + 30032dc: fdc42783 lw a5,-36(s0) + 30032e0: 279e lhu a5,8(a5) + 30032e2: 873e mv a4,a5 + 30032e4: fec42783 lw a5,-20(s0) + 30032e8: 97ba add a5,a5,a4 + 30032ea: fef42423 sw a5,-24(s0) + return p->BIT.eflash_cken; + 30032ee: fe842783 lw a5,-24(s0) + 30032f2: 439c lw a5,0(a5) + 30032f4: 8b85 andi a5,a5,1 + 30032f6: 9f81 uxtb a5 +} + 30032f8: 853e mv a0,a5 + 30032fa: 50b2 lw ra,44(sp) + 30032fc: 5422 lw s0,40(sp) + 30032fe: 6145 addi sp,sp,48 + 3003300: 8082 ret + +03003302 : + * @brief Enable Clock of ANA + * @param matchInfo ANA match Info + * @param enable IP_CLK_ENABLE or IP_CRG_DISABLE + */ +static void CRG_AnaEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable) +{ + 3003302: 7179 addi sp,sp,-48 + 3003304: d606 sw ra,44(sp) + 3003306: d422 sw s0,40(sp) + 3003308: 1800 addi s0,sp,48 + 300330a: fca42e23 sw a0,-36(s0) + 300330e: fcb42c23 sw a1,-40(s0) + CRG_ASSERT_PARAM(matchInfo != NULL); + 3003312: fdc42783 lw a5,-36(s0) + 3003316: eb89 bnez a5,3003328 + 3003318: 44000593 li a1,1088 + 300331c: 030097b7 lui a5,0x3009 + 3003320: 96c78513 addi a0,a5,-1684 # 300896c + 3003324: 3e95 jal ra,3002e98 + 3003326: a001 j 3003326 + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + 3003328: 040007b7 lui a5,0x4000 + 300332c: 4947a783 lw a5,1172(a5) # 4000494 + 3003330: eb89 bnez a5,3003342 + 3003332: 44100593 li a1,1089 + 3003336: 030097b7 lui a5,0x3009 + 300333a: 96c78513 addi a0,a5,-1684 # 300896c + 300333e: 3ea9 jal ra,3002e98 + 3003340: a001 j 3003340 + CRG_PARAM_CHECK_NO_RET(enable == IP_CLK_ENABLE || enable == IP_CLK_DISABLE); + 3003342: fd842703 lw a4,-40(s0) + 3003346: 4785 li a5,1 + 3003348: 00f70d63 beq a4,a5,3003362 + 300334c: fd842783 lw a5,-40(s0) + 3003350: cb89 beqz a5,3003362 + 3003352: 44200593 li a1,1090 + 3003356: 030097b7 lui a5,0x3009 + 300335a: 96c78513 addi a0,a5,-1684 # 300896c + 300335e: 3e2d jal ra,3002e98 + 3003360: a20d j 3003482 + + /* Get the value of the ANA IP register in the CRG. */ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + 3003362: 040007b7 lui a5,0x4000 + 3003366: 4947a783 lw a5,1172(a5) # 4000494 + 300336a: fef42623 sw a5,-20(s0) + CRG_AnaIpCfg *p = (CRG_AnaIpCfg *)(void *)(base + matchInfo->regOffset + matchInfo->bitOffset); + 300336e: fdc42783 lw a5,-36(s0) + 3003372: 279e lhu a5,8(a5) + 3003374: 873e mv a4,a5 + 3003376: fec42783 lw a5,-20(s0) + 300337a: 97ba add a5,a5,a4 + 300337c: fdc42703 lw a4,-36(s0) + 3003380: 2738 lbu a4,10(a4) + 3003382: 97ba add a5,a5,a4 + 3003384: fef42423 sw a5,-24(s0) + + if ((enable == IP_CLK_ENABLE) && (p->BIT.ip_srst_req == BASE_CFG_SET)) { + 3003388: fd842703 lw a4,-40(s0) + 300338c: 4785 li a5,1 + 300338e: 02f71f63 bne a4,a5,30033cc + 3003392: fe842783 lw a5,-24(s0) + 3003396: 439c lw a5,0(a5) + 3003398: 83c1 srli a5,a5,0x10 + 300339a: 8b85 andi a5,a5,1 + 300339c: 0ff7f713 andi a4,a5,255 + 30033a0: 4785 li a5,1 + 30033a2: 02f71563 bne a4,a5,30033cc + p->BIT.ip_srst_req = BASE_CFG_UNSET; + 30033a6: fe842703 lw a4,-24(s0) + 30033aa: 431c lw a5,0(a4) + 30033ac: 76c1 lui a3,0xffff0 + 30033ae: 16fd addi a3,a3,-1 # fffeffff + 30033b0: 8ff5 and a5,a5,a3 + 30033b2: c31c sw a5,0(a4) + g_anaEnableFlag++; /* count enable analog IP number */ + 30033b4: 040007b7 lui a5,0x4000 + 30033b8: 4987c783 lbu a5,1176(a5) # 4000498 + 30033bc: 0785 addi a5,a5,1 + 30033be: 0ff7f713 andi a4,a5,255 + 30033c2: 040007b7 lui a5,0x4000 + 30033c6: 48e78c23 sb a4,1176(a5) # 4000498 + 30033ca: a089 j 300340c + } else if ((enable == IP_CLK_DISABLE) && (p->BIT.ip_srst_req == BASE_CFG_UNSET)) { + 30033cc: fd842783 lw a5,-40(s0) + 30033d0: ef95 bnez a5,300340c + 30033d2: fe842783 lw a5,-24(s0) + 30033d6: 439c lw a5,0(a5) + 30033d8: 83c1 srli a5,a5,0x10 + 30033da: 8b85 andi a5,a5,1 + 30033dc: 9f81 uxtb a5 + 30033de: e79d bnez a5,300340c + p->BIT.ip_srst_req = BASE_CFG_SET; + 30033e0: fe842703 lw a4,-24(s0) + 30033e4: 431c lw a5,0(a4) + 30033e6: 66c1 lui a3,0x10 + 30033e8: 8fd5 or a5,a5,a3 + 30033ea: c31c sw a5,0(a4) + if (g_anaEnableFlag > 0) { + 30033ec: 040007b7 lui a5,0x4000 + 30033f0: 4987c783 lbu a5,1176(a5) # 4000498 + 30033f4: cf81 beqz a5,300340c + g_anaEnableFlag--; /* Decreasing the count to enable the analog IP number. */ + 30033f6: 040007b7 lui a5,0x4000 + 30033fa: 4987c783 lbu a5,1176(a5) # 4000498 + 30033fe: 17fd addi a5,a5,-1 + 3003400: 0ff7f713 andi a4,a5,255 + 3003404: 040007b7 lui a5,0x4000 + 3003408: 48e78c23 sb a4,1176(a5) # 4000498 + } + } + + if ((g_anaEnableFlag == 0) && (enable == IP_CLK_DISABLE)) { /* all analog clock disable */ + 300340c: 040007b7 lui a5,0x4000 + 3003410: 4987c783 lbu a5,1176(a5) # 4000498 + 3003414: eb85 bnez a5,3003444 + 3003416: fd842783 lw a5,-40(s0) + 300341a: e78d bnez a5,3003444 + CRG->PERI_CRG660.BIT.clk_ana_cken = BASE_CFG_UNSET; + 300341c: 10000737 lui a4,0x10000 + 3003420: 6785 lui a5,0x1 + 3003422: 973e add a4,a4,a5 + 3003424: a5072783 lw a5,-1456(a4) # ffffa50 + 3003428: 9bf9 andi a5,a5,-2 + 300342a: a4f72823 sw a5,-1456(a4) + CRG->PERI_CRG660.BIT.ana_srst_req = BASE_CFG_SET; + 300342e: 10000737 lui a4,0x10000 + 3003432: 6785 lui a5,0x1 + 3003434: 973e add a4,a4,a5 + 3003436: a5072783 lw a5,-1456(a4) # ffffa50 + 300343a: 66c1 lui a3,0x10 + 300343c: 8fd5 or a5,a5,a3 + 300343e: a4f72823 sw a5,-1456(a4) + 3003442: a081 j 3003482 + } else if ((g_anaEnableFlag > 0) && (enable == IP_CLK_ENABLE)) { /* all analog clock enable */ + 3003444: 040007b7 lui a5,0x4000 + 3003448: 4987c783 lbu a5,1176(a5) # 4000498 + 300344c: cb9d beqz a5,3003482 + 300344e: fd842703 lw a4,-40(s0) + 3003452: 4785 li a5,1 + 3003454: 02f71763 bne a4,a5,3003482 + CRG->PERI_CRG660.BIT.ana_srst_req = BASE_CFG_UNSET; + 3003458: 10000737 lui a4,0x10000 + 300345c: 6785 lui a5,0x1 + 300345e: 973e add a4,a4,a5 + 3003460: a5072783 lw a5,-1456(a4) # ffffa50 + 3003464: 76c1 lui a3,0xffff0 + 3003466: 16fd addi a3,a3,-1 # fffeffff + 3003468: 8ff5 and a5,a5,a3 + 300346a: a4f72823 sw a5,-1456(a4) + CRG->PERI_CRG660.BIT.clk_ana_cken = BASE_CFG_SET; + 300346e: 10000737 lui a4,0x10000 + 3003472: 6785 lui a5,0x1 + 3003474: 973e add a4,a4,a5 + 3003476: a5072783 lw a5,-1456(a4) # ffffa50 + 300347a: 0017e793 ori a5,a5,1 + 300347e: a4f72823 sw a5,-1456(a4) + } +} + 3003482: 50b2 lw ra,44(sp) + 3003484: 5422 lw s0,40(sp) + 3003486: 6145 addi sp,sp,48 + 3003488: 8082 ret + +0300348a : + * @brief Get Clock of ANA + * @param matchInfo ANA match Info + * @return unsigned int IP_CLK_ENABLE or IP_CRG_DISABLE + */ +static unsigned int CRG_AnaEnableGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + 300348a: 7179 addi sp,sp,-48 + 300348c: d606 sw ra,44(sp) + 300348e: d422 sw s0,40(sp) + 3003490: 1800 addi s0,sp,48 + 3003492: fca42e23 sw a0,-36(s0) + CRG_ASSERT_PARAM(matchInfo != NULL); + 3003496: fdc42783 lw a5,-36(s0) + 300349a: eb89 bnez a5,30034ac + 300349c: 46200593 li a1,1122 + 30034a0: 030097b7 lui a5,0x3009 + 30034a4: 96c78513 addi a0,a5,-1684 # 300896c + 30034a8: 3ac5 jal ra,3002e98 + 30034aa: a001 j 30034aa + CRG_ASSERT_PARAM(g_crgBaseAddr != NULL); + 30034ac: 040007b7 lui a5,0x4000 + 30034b0: 4947a783 lw a5,1172(a5) # 4000494 + 30034b4: eb89 bnez a5,30034c6 + 30034b6: 46300593 li a1,1123 + 30034ba: 030097b7 lui a5,0x3009 + 30034be: 96c78513 addi a0,a5,-1684 # 300896c + 30034c2: 3ad9 jal ra,3002e98 + 30034c4: a001 j 30034c4 + + /* Get the value of the ANA IP register in the CRG. */ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + 30034c6: 040007b7 lui a5,0x4000 + 30034ca: 4947a783 lw a5,1172(a5) # 4000494 + 30034ce: fef42623 sw a5,-20(s0) + CRG_AnaIpCfg *p = (CRG_AnaIpCfg *)(void *)(base + matchInfo->regOffset + matchInfo->bitOffset); + 30034d2: fdc42783 lw a5,-36(s0) + 30034d6: 279e lhu a5,8(a5) + 30034d8: 873e mv a4,a5 + 30034da: fec42783 lw a5,-20(s0) + 30034de: 97ba add a5,a5,a4 + 30034e0: fdc42703 lw a4,-36(s0) + 30034e4: 2738 lbu a4,10(a4) + 30034e6: 97ba add a5,a5,a4 + 30034e8: fef42423 sw a5,-24(s0) + /* The clock is enabled based on the IP reset status. */ + return (p->BIT.ip_srst_req) ? BASE_CFG_UNSET : BASE_CFG_SET; + 30034ec: fe842783 lw a5,-24(s0) + 30034f0: 439c lw a5,0(a5) + 30034f2: 83c1 srli a5,a5,0x10 + 30034f4: 8b85 andi a5,a5,1 + 30034f6: 9f81 uxtb a5 + 30034f8: 0017c793 xori a5,a5,1 + 30034fc: 9f81 uxtb a5 +} + 30034fe: 853e mv a0,a5 + 3003500: 50b2 lw ra,44(sp) + 3003502: 5422 lw s0,40(sp) + 3003504: 6145 addi sp,sp,48 + 3003506: 8082 ret + +03003508 : + * @brief Check gpio value parameter. + * @param value Value of @ref GPIO_Value + * @retval Bool. + */ +static inline bool IsGpioValue(GPIO_Value value) +{ + 3003508: 1101 addi sp,sp,-32 + 300350a: ce22 sw s0,28(sp) + 300350c: 1000 addi s0,sp,32 + 300350e: fea42623 sw a0,-20(s0) + return (value == GPIO_LOW_LEVEL || value == GPIO_HIGH_LEVEL); + 3003512: fec42783 lw a5,-20(s0) + 3003516: c791 beqz a5,3003522 + 3003518: fec42703 lw a4,-20(s0) + 300351c: 4785 li a5,1 + 300351e: 00f71463 bne a4,a5,3003526 + 3003522: 4785 li a5,1 + 3003524: a011 j 3003528 + 3003526: 4781 li a5,0 + 3003528: 8b85 andi a5,a5,1 + 300352a: 9f81 uxtb a5 +} + 300352c: 853e mv a0,a5 + 300352e: 4472 lw s0,28(sp) + 3003530: 6105 addi sp,sp,32 + 3003532: 8082 ret + +03003534 : + * @brief Check gpio direction parameter. + * @param dir Value of @ref GPIO_Direction. + * @retval Bool. + */ +static inline bool IsGpioDirection(GPIO_Direction dir) +{ + 3003534: 1101 addi sp,sp,-32 + 3003536: ce22 sw s0,28(sp) + 3003538: 1000 addi s0,sp,32 + 300353a: fea42623 sw a0,-20(s0) + return (dir == GPIO_INPUT_MODE || dir == GPIO_OUTPUT_MODE); + 300353e: fec42783 lw a5,-20(s0) + 3003542: c791 beqz a5,300354e + 3003544: fec42703 lw a4,-20(s0) + 3003548: 4785 li a5,1 + 300354a: 00f71463 bne a4,a5,3003552 + 300354e: 4785 li a5,1 + 3003550: a011 j 3003554 + 3003552: 4781 li a5,0 + 3003554: 8b85 andi a5,a5,1 + 3003556: 9f81 uxtb a5 +} + 3003558: 853e mv a0,a5 + 300355a: 4472 lw s0,28(sp) + 300355c: 6105 addi sp,sp,32 + 300355e: 8082 ret + +03003560 : + * @brief Check gpio pins parameter. + * @param pins OR logical combination of pin. + * @retval Bool. + */ +static inline bool IsGpioPins(unsigned int pins) +{ + 3003560: 1101 addi sp,sp,-32 + 3003562: ce22 sw s0,28(sp) + 3003564: 1000 addi s0,sp,32 + 3003566: fea42623 sw a0,-20(s0) + return ((pins & GPIO_PIN_MASK) != BASE_CFG_UNSET) && ((pins & ~GPIO_PIN_MASK) == BASE_CFG_UNSET); + 300356a: fec42783 lw a5,-20(s0) + 300356e: 0ff7f793 andi a5,a5,255 + 3003572: cb81 beqz a5,3003582 + 3003574: fec42783 lw a5,-20(s0) + 3003578: f007f793 andi a5,a5,-256 + 300357c: e399 bnez a5,3003582 + 300357e: 4785 li a5,1 + 3003580: a011 j 3003584 + 3003582: 4781 li a5,0 + 3003584: 8b85 andi a5,a5,1 + 3003586: 9f81 uxtb a5 +} + 3003588: 853e mv a0,a5 + 300358a: 4472 lw s0,28(sp) + 300358c: 6105 addi sp,sp,32 + 300358e: 8082 ret + +03003590 : + * @brief Check gpio pin parameter. + * @param pin Value of @ref GPIO_PIN. + * @retval Bool. + */ +static inline bool IsGpioPin(GPIO_PIN pin) +{ + 3003590: 1101 addi sp,sp,-32 + 3003592: ce22 sw s0,28(sp) + 3003594: 1000 addi s0,sp,32 + 3003596: fea42623 sw a0,-20(s0) + /* Check whether gpio pin */ + return (pin == GPIO_PIN_0 || pin == GPIO_PIN_1 || \ + pin == GPIO_PIN_2 || pin == GPIO_PIN_3 || \ + pin == GPIO_PIN_4 || pin == GPIO_PIN_5 || \ + pin == GPIO_PIN_6 || pin == GPIO_PIN_7 || \ + 300359a: fec42703 lw a4,-20(s0) + 300359e: 4785 li a5,1 + 30035a0: 04f70e63 beq a4,a5,30035fc + return (pin == GPIO_PIN_0 || pin == GPIO_PIN_1 || \ + 30035a4: fec42703 lw a4,-20(s0) + 30035a8: 4789 li a5,2 + 30035aa: 04f70963 beq a4,a5,30035fc + 30035ae: fec42703 lw a4,-20(s0) + 30035b2: 4791 li a5,4 + 30035b4: 04f70463 beq a4,a5,30035fc + pin == GPIO_PIN_2 || pin == GPIO_PIN_3 || \ + 30035b8: fec42703 lw a4,-20(s0) + 30035bc: 47a1 li a5,8 + 30035be: 02f70f63 beq a4,a5,30035fc + 30035c2: fec42703 lw a4,-20(s0) + 30035c6: 47c1 li a5,16 + 30035c8: 02f70a63 beq a4,a5,30035fc + pin == GPIO_PIN_4 || pin == GPIO_PIN_5 || \ + 30035cc: fec42703 lw a4,-20(s0) + 30035d0: 02000793 li a5,32 + 30035d4: 02f70463 beq a4,a5,30035fc + 30035d8: fec42703 lw a4,-20(s0) + 30035dc: 04000793 li a5,64 + 30035e0: 00f70e63 beq a4,a5,30035fc + pin == GPIO_PIN_6 || pin == GPIO_PIN_7 || \ + 30035e4: fec42703 lw a4,-20(s0) + 30035e8: 08000793 li a5,128 + 30035ec: 00f70863 beq a4,a5,30035fc + 30035f0: fec42703 lw a4,-20(s0) + 30035f4: 0ff00793 li a5,255 + 30035f8: 00f71463 bne a4,a5,3003600 + 30035fc: 4785 li a5,1 + 30035fe: a011 j 3003602 + 3003600: 4781 li a5,0 + 3003602: 8b85 andi a5,a5,1 + 3003604: 9f81 uxtb a5 + pin == GPIO_PIN_ALL); +} + 3003606: 853e mv a0,a5 + 3003608: 4472 lw s0,28(sp) + 300360a: 6105 addi sp,sp,32 + 300360c: 8082 ret + +0300360e : + * @brief Check gpio interrupt mode parameter. + * @param mode Value of @ref GPIO_InterruptMode. + * @retval Bool. + */ +static inline bool IsGpioITMode(GPIO_InterruptMode mode) +{ + 300360e: 1101 addi sp,sp,-32 + 3003610: ce22 sw s0,28(sp) + 3003612: 1000 addi s0,sp,32 + 3003614: fea42623 sw a0,-20(s0) + /* Check whether gpio interrupt mode */ + return (mode == GPIO_INT_TYPE_HIGH_LEVEL || \ + mode == GPIO_INT_TYPE_LOW_LEVEL || \ + mode == GPIO_INT_TYPE_RISE_EDGE || \ + mode == GPIO_INT_TYPE_FALL_EDGE || \ + mode == GPIO_INT_TYPE_BOTH_EDGE || \ + 3003618: fec42703 lw a4,-20(s0) + 300361c: 478d li a5,3 + 300361e: 02f70963 beq a4,a5,3003650 + return (mode == GPIO_INT_TYPE_HIGH_LEVEL || \ + 3003622: fec42703 lw a4,-20(s0) + 3003626: 4789 li a5,2 + 3003628: 02f70463 beq a4,a5,3003650 + mode == GPIO_INT_TYPE_LOW_LEVEL || \ + 300362c: fec42703 lw a4,-20(s0) + 3003630: 4785 li a5,1 + 3003632: 00f70f63 beq a4,a5,3003650 + mode == GPIO_INT_TYPE_RISE_EDGE || \ + 3003636: fec42783 lw a5,-20(s0) + 300363a: cb99 beqz a5,3003650 + mode == GPIO_INT_TYPE_FALL_EDGE || \ + 300363c: fec42703 lw a4,-20(s0) + 3003640: 4791 li a5,4 + 3003642: 00f70763 beq a4,a5,3003650 + mode == GPIO_INT_TYPE_BOTH_EDGE || \ + 3003646: fec42703 lw a4,-20(s0) + 300364a: 4795 li a5,5 + 300364c: 00f71463 bne a4,a5,3003654 + 3003650: 4785 li a5,1 + 3003652: a011 j 3003656 + 3003654: 4781 li a5,0 + 3003656: 8b85 andi a5,a5,1 + 3003658: 9f81 uxtb a5 + mode == GPIO_INT_TYPE_NONE); +} + 300365a: 853e mv a0,a5 + 300365c: 4472 lw s0,28(sp) + 300365e: 6105 addi sp,sp,32 + 3003660: 8082 ret + +03003662 : + * @param pins OR logical combination of pin. + * @param value Value of @ref GPIO_Value. + * @retval None. + */ +static inline void DCL_GPIO_SetValue(GPIO_RegStruct *gpiox, unsigned int pins, GPIO_Value value) +{ + 3003662: 1101 addi sp,sp,-32 + 3003664: ce06 sw ra,28(sp) + 3003666: cc22 sw s0,24(sp) + 3003668: 1000 addi s0,sp,32 + 300366a: fea42623 sw a0,-20(s0) + 300366e: feb42423 sw a1,-24(s0) + 3003672: fec42223 sw a2,-28(s0) + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + 3003676: fec42703 lw a4,-20(s0) + 300367a: 145007b7 lui a5,0x14500 + 300367e: 04f70863 beq a4,a5,30036ce + 3003682: fec42703 lw a4,-20(s0) + 3003686: 145017b7 lui a5,0x14501 + 300368a: 04f70263 beq a4,a5,30036ce + 300368e: fec42703 lw a4,-20(s0) + 3003692: 145027b7 lui a5,0x14502 + 3003696: 02f70c63 beq a4,a5,30036ce + 300369a: fec42703 lw a4,-20(s0) + 300369e: 145037b7 lui a5,0x14503 + 30036a2: 02f70663 beq a4,a5,30036ce + 30036a6: fec42703 lw a4,-20(s0) + 30036aa: 145047b7 lui a5,0x14504 + 30036ae: 02f70063 beq a4,a5,30036ce + 30036b2: fec42703 lw a4,-20(s0) + 30036b6: 145057b7 lui a5,0x14505 + 30036ba: 00f70a63 beq a4,a5,30036ce + 30036be: 18e00593 li a1,398 + 30036c2: 030097b7 lui a5,0x3009 + 30036c6: 9c078513 addi a0,a5,-1600 # 30089c0 + 30036ca: 2d51 jal ra,3003d5e + 30036cc: a001 j 30036cc + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + 30036ce: fe842503 lw a0,-24(s0) + 30036d2: 3579 jal ra,3003560 + 30036d4: 87aa mv a5,a0 + 30036d6: 0017c793 xori a5,a5,1 + 30036da: 9f81 uxtb a5 + 30036dc: cb89 beqz a5,30036ee + 30036de: 18f00593 li a1,399 + 30036e2: 030097b7 lui a5,0x3009 + 30036e6: 9c078513 addi a0,a5,-1600 # 30089c0 + 30036ea: 2d95 jal ra,3003d5e + 30036ec: a089 j 300372e + GPIO_PARAM_CHECK_NO_RET(IsGpioValue(value)); + 30036ee: fe442503 lw a0,-28(s0) + 30036f2: 3d19 jal ra,3003508 + 30036f4: 87aa mv a5,a0 + 30036f6: 0017c793 xori a5,a5,1 + 30036fa: 9f81 uxtb a5 + 30036fc: cb89 beqz a5,300370e + 30036fe: 19000593 li a1,400 + 3003702: 030097b7 lui a5,0x3009 + 3003706: 9c078513 addi a0,a5,-1600 # 30089c0 + 300370a: 2d91 jal ra,3003d5e + 300370c: a00d j 300372e + gpiox->GPIO_DATA[pins].reg = (value == GPIO_HIGH_LEVEL ? pins : BASE_CFG_UNSET); /* Set GPIO pin level */ + 300370e: fe442703 lw a4,-28(s0) + 3003712: 4785 li a5,1 + 3003714: 00f71563 bne a4,a5,300371e + 3003718: fe842783 lw a5,-24(s0) + 300371c: a011 j 3003720 + 300371e: 4781 li a5,0 + 3003720: fec42683 lw a3,-20(s0) + 3003724: fe842703 lw a4,-24(s0) + 3003728: 070a slli a4,a4,0x2 + 300372a: 9736 add a4,a4,a3 + 300372c: c31c sw a5,0(a4) +} + 300372e: 40f2 lw ra,28(sp) + 3003730: 4462 lw s0,24(sp) + 3003732: 6105 addi sp,sp,32 + 3003734: 8082 ret + +03003736 : + * @param pins OR logical combination of pin. + * @param dir Value of @ref GPIO_Direction. + * @retval None. + */ +static inline void DCL_GPIO_SetDirection(GPIO_RegStruct *gpiox, unsigned int pins, GPIO_Direction dir) +{ + 3003736: 1101 addi sp,sp,-32 + 3003738: ce06 sw ra,28(sp) + 300373a: cc22 sw s0,24(sp) + 300373c: 1000 addi s0,sp,32 + 300373e: fea42623 sw a0,-20(s0) + 3003742: feb42423 sw a1,-24(s0) + 3003746: fec42223 sw a2,-28(s0) + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + 300374a: fec42703 lw a4,-20(s0) + 300374e: 145007b7 lui a5,0x14500 + 3003752: 04f70863 beq a4,a5,30037a2 + 3003756: fec42703 lw a4,-20(s0) + 300375a: 145017b7 lui a5,0x14501 + 300375e: 04f70263 beq a4,a5,30037a2 + 3003762: fec42703 lw a4,-20(s0) + 3003766: 145027b7 lui a5,0x14502 + 300376a: 02f70c63 beq a4,a5,30037a2 + 300376e: fec42703 lw a4,-20(s0) + 3003772: 145037b7 lui a5,0x14503 + 3003776: 02f70663 beq a4,a5,30037a2 + 300377a: fec42703 lw a4,-20(s0) + 300377e: 145047b7 lui a5,0x14504 + 3003782: 02f70063 beq a4,a5,30037a2 + 3003786: fec42703 lw a4,-20(s0) + 300378a: 145057b7 lui a5,0x14505 + 300378e: 00f70a63 beq a4,a5,30037a2 + 3003792: 1b700593 li a1,439 + 3003796: 030097b7 lui a5,0x3009 + 300379a: 9c078513 addi a0,a5,-1600 # 30089c0 + 300379e: 23c1 jal ra,3003d5e + 30037a0: a001 j 30037a0 + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + 30037a2: fe842503 lw a0,-24(s0) + 30037a6: 3b6d jal ra,3003560 + 30037a8: 87aa mv a5,a0 + 30037aa: 0017c793 xori a5,a5,1 + 30037ae: 9f81 uxtb a5 + 30037b0: cb89 beqz a5,30037c2 + 30037b2: 1b800593 li a1,440 + 30037b6: 030097b7 lui a5,0x3009 + 30037ba: 9c078513 addi a0,a5,-1600 # 30089c0 + 30037be: 2345 jal ra,3003d5e + 30037c0: a095 j 3003824 + GPIO_PARAM_CHECK_NO_RET(IsGpioDirection(dir)); + 30037c2: fe442503 lw a0,-28(s0) + 30037c6: 33bd jal ra,3003534 + 30037c8: 87aa mv a5,a0 + 30037ca: 0017c793 xori a5,a5,1 + 30037ce: 9f81 uxtb a5 + 30037d0: cb89 beqz a5,30037e2 + 30037d2: 1b900593 li a1,441 + 30037d6: 030097b7 lui a5,0x3009 + 30037da: 9c078513 addi a0,a5,-1600 # 30089c0 + 30037de: 2341 jal ra,3003d5e + 30037e0: a091 j 3003824 + if (dir == GPIO_INPUT_MODE) { /* Set GPIO pin direction */ + 30037e2: fe442783 lw a5,-28(s0) + 30037e6: ef99 bnez a5,3003804 + gpiox->GPIO_DIR.reg &= ~pins; + 30037e8: fec42783 lw a5,-20(s0) + 30037ec: 4007a703 lw a4,1024(a5) + 30037f0: fe842783 lw a5,-24(s0) + 30037f4: fff7c793 not a5,a5 + 30037f8: 8f7d and a4,a4,a5 + 30037fa: fec42783 lw a5,-20(s0) + 30037fe: 40e7a023 sw a4,1024(a5) + 3003802: a00d j 3003824 + } else if (dir == GPIO_OUTPUT_MODE) { + 3003804: fe442703 lw a4,-28(s0) + 3003808: 4785 li a5,1 + 300380a: 00f71d63 bne a4,a5,3003824 + gpiox->GPIO_DIR.reg |= pins; + 300380e: fec42783 lw a5,-20(s0) + 3003812: 4007a703 lw a4,1024(a5) + 3003816: fe842783 lw a5,-24(s0) + 300381a: 8f5d or a4,a4,a5 + 300381c: fec42783 lw a5,-20(s0) + 3003820: 40e7a023 sw a4,1024(a5) + } +} + 3003824: 40f2 lw ra,28(sp) + 3003826: 4462 lw s0,24(sp) + 3003828: 6105 addi sp,sp,32 + 300382a: 8082 ret + +0300382c : + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @retval None. + */ +static inline void DCL_GPIO_ClearIrq(GPIO_RegStruct *gpiox, unsigned int pins) +{ + 300382c: 1101 addi sp,sp,-32 + 300382e: ce06 sw ra,28(sp) + 3003830: cc22 sw s0,24(sp) + 3003832: 1000 addi s0,sp,32 + 3003834: fea42623 sw a0,-20(s0) + 3003838: feb42423 sw a1,-24(s0) + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + 300383c: fec42703 lw a4,-20(s0) + 3003840: 145007b7 lui a5,0x14500 + 3003844: 04f70863 beq a4,a5,3003894 + 3003848: fec42703 lw a4,-20(s0) + 300384c: 145017b7 lui a5,0x14501 + 3003850: 04f70263 beq a4,a5,3003894 + 3003854: fec42703 lw a4,-20(s0) + 3003858: 145027b7 lui a5,0x14502 + 300385c: 02f70c63 beq a4,a5,3003894 + 3003860: fec42703 lw a4,-20(s0) + 3003864: 145037b7 lui a5,0x14503 + 3003868: 02f70663 beq a4,a5,3003894 + 300386c: fec42703 lw a4,-20(s0) + 3003870: 145047b7 lui a5,0x14504 + 3003874: 02f70063 beq a4,a5,3003894 + 3003878: fec42703 lw a4,-20(s0) + 300387c: 145057b7 lui a5,0x14505 + 3003880: 00f70a63 beq a4,a5,3003894 + 3003884: 25c00593 li a1,604 + 3003888: 030097b7 lui a5,0x3009 + 300388c: 9c078513 addi a0,a5,-1600 # 30089c0 + 3003890: 21f9 jal ra,3003d5e + 3003892: a001 j 3003892 + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + 3003894: fe842503 lw a0,-24(s0) + 3003898: 31e1 jal ra,3003560 + 300389a: 87aa mv a5,a0 + 300389c: 0017c793 xori a5,a5,1 + 30038a0: 9f81 uxtb a5 + 30038a2: cb89 beqz a5,30038b4 + 30038a4: 25d00593 li a1,605 + 30038a8: 030097b7 lui a5,0x3009 + 30038ac: 9c078513 addi a0,a5,-1600 # 30089c0 + 30038b0: 217d jal ra,3003d5e + 30038b2: a821 j 30038ca + gpiox->GPIO_IC.reg |= pins; + 30038b4: fec42783 lw a5,-20(s0) + 30038b8: 41c7a703 lw a4,1052(a5) + 30038bc: fe842783 lw a5,-24(s0) + 30038c0: 8f5d or a4,a4,a5 + 30038c2: fec42783 lw a5,-20(s0) + 30038c6: 40e7ae23 sw a4,1052(a5) +} + 30038ca: 40f2 lw ra,28(sp) + 30038cc: 4462 lw s0,24(sp) + 30038ce: 6105 addi sp,sp,32 + 30038d0: 8082 ret + +030038d2 : + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pins. + * @retval None. + */ +static inline void DCL_GPIO_EnableIrq(GPIO_RegStruct *gpiox, unsigned int pins) +{ + 30038d2: 1101 addi sp,sp,-32 + 30038d4: ce06 sw ra,28(sp) + 30038d6: cc22 sw s0,24(sp) + 30038d8: 1000 addi s0,sp,32 + 30038da: fea42623 sw a0,-20(s0) + 30038de: feb42423 sw a1,-24(s0) + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + 30038e2: fec42703 lw a4,-20(s0) + 30038e6: 145007b7 lui a5,0x14500 + 30038ea: 04f70863 beq a4,a5,300393a + 30038ee: fec42703 lw a4,-20(s0) + 30038f2: 145017b7 lui a5,0x14501 + 30038f6: 04f70263 beq a4,a5,300393a + 30038fa: fec42703 lw a4,-20(s0) + 30038fe: 145027b7 lui a5,0x14502 + 3003902: 02f70c63 beq a4,a5,300393a + 3003906: fec42703 lw a4,-20(s0) + 300390a: 145037b7 lui a5,0x14503 + 300390e: 02f70663 beq a4,a5,300393a + 3003912: fec42703 lw a4,-20(s0) + 3003916: 145047b7 lui a5,0x14504 + 300391a: 02f70063 beq a4,a5,300393a + 300391e: fec42703 lw a4,-20(s0) + 3003922: 145057b7 lui a5,0x14505 + 3003926: 00f70a63 beq a4,a5,300393a + 300392a: 26900593 li a1,617 + 300392e: 030097b7 lui a5,0x3009 + 3003932: 9c078513 addi a0,a5,-1600 # 30089c0 + 3003936: 2125 jal ra,3003d5e + 3003938: a001 j 3003938 + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + 300393a: fe842503 lw a0,-24(s0) + 300393e: 310d jal ra,3003560 + 3003940: 87aa mv a5,a0 + 3003942: 0017c793 xori a5,a5,1 + 3003946: 9f81 uxtb a5 + 3003948: cb89 beqz a5,300395a + 300394a: 26a00593 li a1,618 + 300394e: 030097b7 lui a5,0x3009 + 3003952: 9c078513 addi a0,a5,-1600 # 30089c0 + 3003956: 2121 jal ra,3003d5e + 3003958: a00d j 300397a + /* must clear interrupt first, prevents interrupts triggered by previous output mode. */ + DCL_GPIO_ClearIrq(gpiox, pins); + 300395a: fe842583 lw a1,-24(s0) + 300395e: fec42503 lw a0,-20(s0) + 3003962: 35e9 jal ra,300382c + gpiox->GPIO_IE.reg |= pins; + 3003964: fec42783 lw a5,-20(s0) + 3003968: 4107a703 lw a4,1040(a5) + 300396c: fe842783 lw a5,-24(s0) + 3003970: 8f5d or a4,a4,a5 + 3003972: fec42783 lw a5,-20(s0) + 3003976: 40e7a823 sw a4,1040(a5) +} + 300397a: 40f2 lw ra,28(sp) + 300397c: 4462 lw s0,24(sp) + 300397e: 6105 addi sp,sp,32 + 3003980: 8082 ret + +03003982 : + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @retval None. + */ +static inline void DCL_GPIO_DisableIrq(GPIO_RegStruct *gpiox, unsigned int pins) +{ + 3003982: 1101 addi sp,sp,-32 + 3003984: ce06 sw ra,28(sp) + 3003986: cc22 sw s0,24(sp) + 3003988: 1000 addi s0,sp,32 + 300398a: fea42623 sw a0,-20(s0) + 300398e: feb42423 sw a1,-24(s0) + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + 3003992: fec42703 lw a4,-20(s0) + 3003996: 145007b7 lui a5,0x14500 + 300399a: 04f70863 beq a4,a5,30039ea + 300399e: fec42703 lw a4,-20(s0) + 30039a2: 145017b7 lui a5,0x14501 + 30039a6: 04f70263 beq a4,a5,30039ea + 30039aa: fec42703 lw a4,-20(s0) + 30039ae: 145027b7 lui a5,0x14502 + 30039b2: 02f70c63 beq a4,a5,30039ea + 30039b6: fec42703 lw a4,-20(s0) + 30039ba: 145037b7 lui a5,0x14503 + 30039be: 02f70663 beq a4,a5,30039ea + 30039c2: fec42703 lw a4,-20(s0) + 30039c6: 145047b7 lui a5,0x14504 + 30039ca: 02f70063 beq a4,a5,30039ea + 30039ce: fec42703 lw a4,-20(s0) + 30039d2: 145057b7 lui a5,0x14505 + 30039d6: 00f70a63 beq a4,a5,30039ea + 30039da: 27800593 li a1,632 + 30039de: 030097b7 lui a5,0x3009 + 30039e2: 9c078513 addi a0,a5,-1600 # 30089c0 + 30039e6: 2ea5 jal ra,3003d5e + 30039e8: a001 j 30039e8 + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + 30039ea: fe842503 lw a0,-24(s0) + 30039ee: 3e8d jal ra,3003560 + 30039f0: 87aa mv a5,a0 + 30039f2: 0017c793 xori a5,a5,1 + 30039f6: 9f81 uxtb a5 + 30039f8: cb89 beqz a5,3003a0a + 30039fa: 27900593 li a1,633 + 30039fe: 030097b7 lui a5,0x3009 + 3003a02: 9c078513 addi a0,a5,-1600 # 30089c0 + 3003a06: 2ea1 jal ra,3003d5e + 3003a08: a831 j 3003a24 + gpiox->GPIO_IE.reg &= ~pins; + 3003a0a: fec42783 lw a5,-20(s0) + 3003a0e: 4107a703 lw a4,1040(a5) + 3003a12: fe842783 lw a5,-24(s0) + 3003a16: fff7c793 not a5,a5 + 3003a1a: 8f7d and a4,a4,a5 + 3003a1c: fec42783 lw a5,-20(s0) + 3003a20: 40e7a823 sw a4,1040(a5) +} + 3003a24: 40f2 lw ra,28(sp) + 3003a26: 4462 lw s0,24(sp) + 3003a28: 6105 addi sp,sp,32 + 3003a2a: 8082 ret + +03003a2c : + * @brief Getting all values of GPIO MIS register. + * @param gpiox Value of @ref GPIO_RegStruct. + * @retval unsigned int All values of GPIO MIS register. + */ +static inline unsigned int DCL_GPIO_GetMIS(const GPIO_RegStruct *gpiox) +{ + 3003a2c: 1101 addi sp,sp,-32 + 3003a2e: ce06 sw ra,28(sp) + 3003a30: cc22 sw s0,24(sp) + 3003a32: 1000 addi s0,sp,32 + 3003a34: fea42623 sw a0,-20(s0) + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + 3003a38: fec42703 lw a4,-20(s0) + 3003a3c: 145007b7 lui a5,0x14500 + 3003a40: 04f70863 beq a4,a5,3003a90 + 3003a44: fec42703 lw a4,-20(s0) + 3003a48: 145017b7 lui a5,0x14501 + 3003a4c: 04f70263 beq a4,a5,3003a90 + 3003a50: fec42703 lw a4,-20(s0) + 3003a54: 145027b7 lui a5,0x14502 + 3003a58: 02f70c63 beq a4,a5,3003a90 + 3003a5c: fec42703 lw a4,-20(s0) + 3003a60: 145037b7 lui a5,0x14503 + 3003a64: 02f70663 beq a4,a5,3003a90 + 3003a68: fec42703 lw a4,-20(s0) + 3003a6c: 145047b7 lui a5,0x14504 + 3003a70: 02f70063 beq a4,a5,3003a90 + 3003a74: fec42703 lw a4,-20(s0) + 3003a78: 145057b7 lui a5,0x14505 + 3003a7c: 00f70a63 beq a4,a5,3003a90 + 3003a80: 29a00593 li a1,666 + 3003a84: 030097b7 lui a5,0x3009 + 3003a88: 9c078513 addi a0,a5,-1600 # 30089c0 + 3003a8c: 2cc9 jal ra,3003d5e + 3003a8e: a001 j 3003a8e + return gpiox->GPIO_MIS.reg & GPIO_PIN_MASK; + 3003a90: fec42783 lw a5,-20(s0) + 3003a94: 4187a783 lw a5,1048(a5) + 3003a98: 0ff7f793 andi a5,a5,255 +} + 3003a9c: 853e mv a0,a5 + 3003a9e: 40f2 lw ra,28(sp) + 3003aa0: 4462 lw s0,24(sp) + 3003aa2: 6105 addi sp,sp,32 + 3003aa4: 8082 ret + +03003aa6 : + * @brief Initializing GPIO register values. + * @param handle Value of @ref GPIO_Handle. + * @retval None. + */ +void HAL_GPIO_Init(GPIO_Handle *handle) +{ + 3003aa6: 7179 addi sp,sp,-48 + 3003aa8: d606 sw ra,44(sp) + 3003aaa: d422 sw s0,40(sp) + 3003aac: 1800 addi s0,sp,48 + 3003aae: fca42e23 sw a0,-36(s0) + GPIO_ASSERT_PARAM(handle != NULL); + 3003ab2: fdc42783 lw a5,-36(s0) + 3003ab6: eb89 bnez a5,3003ac8 + 3003ab8: 02b00593 li a1,43 + 3003abc: 030097b7 lui a5,0x3009 + 3003ac0: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003ac4: 2c69 jal ra,3003d5e + 3003ac6: a001 j 3003ac6 + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + 3003ac8: fdc42783 lw a5,-36(s0) + 3003acc: 4398 lw a4,0(a5) + 3003ace: 145007b7 lui a5,0x14500 + 3003ad2: 04f70d63 beq a4,a5,3003b2c + 3003ad6: fdc42783 lw a5,-36(s0) + 3003ada: 4398 lw a4,0(a5) + 3003adc: 145017b7 lui a5,0x14501 + 3003ae0: 04f70663 beq a4,a5,3003b2c + 3003ae4: fdc42783 lw a5,-36(s0) + 3003ae8: 4398 lw a4,0(a5) + 3003aea: 145027b7 lui a5,0x14502 + 3003aee: 02f70f63 beq a4,a5,3003b2c + 3003af2: fdc42783 lw a5,-36(s0) + 3003af6: 4398 lw a4,0(a5) + 3003af8: 145037b7 lui a5,0x14503 + 3003afc: 02f70863 beq a4,a5,3003b2c + 3003b00: fdc42783 lw a5,-36(s0) + 3003b04: 4398 lw a4,0(a5) + 3003b06: 145047b7 lui a5,0x14504 + 3003b0a: 02f70163 beq a4,a5,3003b2c + 3003b0e: fdc42783 lw a5,-36(s0) + 3003b12: 4398 lw a4,0(a5) + 3003b14: 145057b7 lui a5,0x14505 + 3003b18: 00f70a63 beq a4,a5,3003b2c + 3003b1c: 02c00593 li a1,44 + 3003b20: 030097b7 lui a5,0x3009 + 3003b24: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003b28: 2c1d jal ra,3003d5e + 3003b2a: a001 j 3003b2a + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(handle->pins)); + 3003b2c: fdc42783 lw a5,-36(s0) + 3003b30: 43dc lw a5,4(a5) + 3003b32: 853e mv a0,a5 + 3003b34: 3435 jal ra,3003560 + 3003b36: 87aa mv a5,a0 + 3003b38: 0017c793 xori a5,a5,1 + 3003b3c: 9f81 uxtb a5 + 3003b3e: cb89 beqz a5,3003b50 + 3003b40: 02d00593 li a1,45 + 3003b44: 030097b7 lui a5,0x3009 + 3003b48: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003b4c: 2c09 jal ra,3003d5e + 3003b4e: a81d j 3003b84 + + /* Register GPIO callback ID */ + for (unsigned int i = 0; i < GPIO_PIN_NUM; i++) { + 3003b50: fe042623 sw zero,-20(s0) + 3003b54: a01d j 3003b7a + handle->userCallBack.GPIO_CallbackFuncs[i].pin = (1 << i); + 3003b56: 4705 li a4,1 + 3003b58: fec42783 lw a5,-20(s0) + 3003b5c: 00f717b3 sll a5,a4,a5 + 3003b60: 86be mv a3,a5 + 3003b62: fdc42703 lw a4,-36(s0) + 3003b66: fec42783 lw a5,-20(s0) + 3003b6a: 078e slli a5,a5,0x3 + 3003b6c: 97ba add a5,a5,a4 + 3003b6e: c794 sw a3,8(a5) + for (unsigned int i = 0; i < GPIO_PIN_NUM; i++) { + 3003b70: fec42783 lw a5,-20(s0) + 3003b74: 0785 addi a5,a5,1 + 3003b76: fef42623 sw a5,-20(s0) + 3003b7a: fec42703 lw a4,-20(s0) + 3003b7e: 479d li a5,7 + 3003b80: fce7fbe3 bgeu a5,a4,3003b56 + } +} + 3003b84: 50b2 lw ra,44(sp) + 3003b86: 5422 lw s0,40(sp) + 3003b88: 6145 addi sp,sp,48 + 3003b8a: 8082 ret + +03003b8c : + * @param pins OR logical combination of pin. + * @param dir GPIO pin direction. + * @retval None. + */ +void HAL_GPIO_SetDirection(GPIO_Handle *handle, unsigned int pins, GPIO_Direction dir) +{ + 3003b8c: 1101 addi sp,sp,-32 + 3003b8e: ce06 sw ra,28(sp) + 3003b90: cc22 sw s0,24(sp) + 3003b92: 1000 addi s0,sp,32 + 3003b94: fea42623 sw a0,-20(s0) + 3003b98: feb42423 sw a1,-24(s0) + 3003b9c: fec42223 sw a2,-28(s0) + GPIO_ASSERT_PARAM(handle != NULL); + 3003ba0: fec42783 lw a5,-20(s0) + 3003ba4: eb89 bnez a5,3003bb6 + 3003ba6: 04f00593 li a1,79 + 3003baa: 030097b7 lui a5,0x3009 + 3003bae: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003bb2: 2275 jal ra,3003d5e + 3003bb4: a001 j 3003bb4 + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + 3003bb6: fec42783 lw a5,-20(s0) + 3003bba: 4398 lw a4,0(a5) + 3003bbc: 145007b7 lui a5,0x14500 + 3003bc0: 04f70d63 beq a4,a5,3003c1a + 3003bc4: fec42783 lw a5,-20(s0) + 3003bc8: 4398 lw a4,0(a5) + 3003bca: 145017b7 lui a5,0x14501 + 3003bce: 04f70663 beq a4,a5,3003c1a + 3003bd2: fec42783 lw a5,-20(s0) + 3003bd6: 4398 lw a4,0(a5) + 3003bd8: 145027b7 lui a5,0x14502 + 3003bdc: 02f70f63 beq a4,a5,3003c1a + 3003be0: fec42783 lw a5,-20(s0) + 3003be4: 4398 lw a4,0(a5) + 3003be6: 145037b7 lui a5,0x14503 + 3003bea: 02f70863 beq a4,a5,3003c1a + 3003bee: fec42783 lw a5,-20(s0) + 3003bf2: 4398 lw a4,0(a5) + 3003bf4: 145047b7 lui a5,0x14504 + 3003bf8: 02f70163 beq a4,a5,3003c1a + 3003bfc: fec42783 lw a5,-20(s0) + 3003c00: 4398 lw a4,0(a5) + 3003c02: 145057b7 lui a5,0x14505 + 3003c06: 00f70a63 beq a4,a5,3003c1a + 3003c0a: 05000593 li a1,80 + 3003c0e: 030097b7 lui a5,0x3009 + 3003c12: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003c16: 22a1 jal ra,3003d5e + 3003c18: a001 j 3003c18 + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + 3003c1a: fe842503 lw a0,-24(s0) + 3003c1e: 3289 jal ra,3003560 + 3003c20: 87aa mv a5,a0 + 3003c22: 0017c793 xori a5,a5,1 + 3003c26: 9f81 uxtb a5 + 3003c28: cb89 beqz a5,3003c3a + 3003c2a: 05100593 li a1,81 + 3003c2e: 030097b7 lui a5,0x3009 + 3003c32: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003c36: 2225 jal ra,3003d5e + 3003c38: a815 j 3003c6c + GPIO_PARAM_CHECK_NO_RET(IsGpioDirection(dir)); + 3003c3a: fe442503 lw a0,-28(s0) + 3003c3e: 38dd jal ra,3003534 + 3003c40: 87aa mv a5,a0 + 3003c42: 0017c793 xori a5,a5,1 + 3003c46: 9f81 uxtb a5 + 3003c48: cb89 beqz a5,3003c5a + 3003c4a: 05200593 li a1,82 + 3003c4e: 030097b7 lui a5,0x3009 + 3003c52: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003c56: 2221 jal ra,3003d5e + 3003c58: a811 j 3003c6c + DCL_GPIO_SetDirection(handle->baseAddress, pins, dir); + 3003c5a: fec42783 lw a5,-20(s0) + 3003c5e: 439c lw a5,0(a5) + 3003c60: fe442603 lw a2,-28(s0) + 3003c64: fe842583 lw a1,-24(s0) + 3003c68: 853e mv a0,a5 + 3003c6a: 34f1 jal ra,3003736 +} + 3003c6c: 40f2 lw ra,28(sp) + 3003c6e: 4462 lw s0,24(sp) + 3003c70: 6105 addi sp,sp,32 + 3003c72: 8082 ret + +03003c74 : + * @param pins OR logical combination of pin. + * @param value Value of @ref GPIO_Value. + * @retval None. + */ +void HAL_GPIO_SetValue(GPIO_Handle *handle, unsigned int pins, GPIO_Value value) +{ + 3003c74: 1101 addi sp,sp,-32 + 3003c76: ce06 sw ra,28(sp) + 3003c78: cc22 sw s0,24(sp) + 3003c7a: 1000 addi s0,sp,32 + 3003c7c: fea42623 sw a0,-20(s0) + 3003c80: feb42423 sw a1,-24(s0) + 3003c84: fec42223 sw a2,-28(s0) + GPIO_ASSERT_PARAM(handle != NULL); + 3003c88: fec42783 lw a5,-20(s0) + 3003c8c: eb89 bnez a5,3003c9e + 3003c8e: 05f00593 li a1,95 + 3003c92: 030097b7 lui a5,0x3009 + 3003c96: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003c9a: 20d1 jal ra,3003d5e + 3003c9c: a001 j 3003c9c + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + 3003c9e: fec42783 lw a5,-20(s0) + 3003ca2: 4398 lw a4,0(a5) + 3003ca4: 145007b7 lui a5,0x14500 + 3003ca8: 04f70d63 beq a4,a5,3003d02 + 3003cac: fec42783 lw a5,-20(s0) + 3003cb0: 4398 lw a4,0(a5) + 3003cb2: 145017b7 lui a5,0x14501 + 3003cb6: 04f70663 beq a4,a5,3003d02 + 3003cba: fec42783 lw a5,-20(s0) + 3003cbe: 4398 lw a4,0(a5) + 3003cc0: 145027b7 lui a5,0x14502 + 3003cc4: 02f70f63 beq a4,a5,3003d02 + 3003cc8: fec42783 lw a5,-20(s0) + 3003ccc: 4398 lw a4,0(a5) + 3003cce: 145037b7 lui a5,0x14503 + 3003cd2: 02f70863 beq a4,a5,3003d02 + 3003cd6: fec42783 lw a5,-20(s0) + 3003cda: 4398 lw a4,0(a5) + 3003cdc: 145047b7 lui a5,0x14504 + 3003ce0: 02f70163 beq a4,a5,3003d02 + 3003ce4: fec42783 lw a5,-20(s0) + 3003ce8: 4398 lw a4,0(a5) + 3003cea: 145057b7 lui a5,0x14505 + 3003cee: 00f70a63 beq a4,a5,3003d02 + 3003cf2: 06000593 li a1,96 + 3003cf6: 030097b7 lui a5,0x3009 + 3003cfa: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003cfe: 2085 jal ra,3003d5e + 3003d00: a001 j 3003d00 + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + 3003d02: fe842503 lw a0,-24(s0) + 3003d06: 38a9 jal ra,3003560 + 3003d08: 87aa mv a5,a0 + 3003d0a: 0017c793 xori a5,a5,1 + 3003d0e: 9f81 uxtb a5 + 3003d10: cb89 beqz a5,3003d22 + 3003d12: 06100593 li a1,97 + 3003d16: 030097b7 lui a5,0x3009 + 3003d1a: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003d1e: 2081 jal ra,3003d5e + 3003d20: a81d j 3003d56 + GPIO_PARAM_CHECK_NO_RET(IsGpioValue(value)); + 3003d22: fe442503 lw a0,-28(s0) + 3003d26: fe2ff0ef jal ra,3003508 + 3003d2a: 87aa mv a5,a0 + 3003d2c: 0017c793 xori a5,a5,1 + 3003d30: 9f81 uxtb a5 + 3003d32: cb89 beqz a5,3003d44 + 3003d34: 06200593 li a1,98 + 3003d38: 030097b7 lui a5,0x3009 + 3003d3c: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003d40: 2839 jal ra,3003d5e + 3003d42: a811 j 3003d56 + DCL_GPIO_SetValue(handle->baseAddress, pins, value); + 3003d44: fec42783 lw a5,-20(s0) + 3003d48: 439c lw a5,0(a5) + 3003d4a: fe442603 lw a2,-28(s0) + 3003d4e: fe842583 lw a1,-24(s0) + 3003d52: 853e mv a0,a5 + 3003d54: 3239 jal ra,3003662 +} + 3003d56: 40f2 lw ra,28(sp) + 3003d58: 4462 lw s0,24(sp) + 3003d5a: 6105 addi sp,sp,32 + 3003d5c: 8082 ret + +03003d5e : + 3003d5e: caafd06f j 3001208 + +03003d62 : + * @param handle Value of @ref GPIO_Handle. + * @param pins GPIO pins. + * @retval None. + */ +void HAL_GPIO_TogglePin(GPIO_Handle *handle, unsigned int pins) +{ + 3003d62: 1101 addi sp,sp,-32 + 3003d64: ce06 sw ra,28(sp) + 3003d66: cc22 sw s0,24(sp) + 3003d68: 1000 addi s0,sp,32 + 3003d6a: fea42623 sw a0,-20(s0) + 3003d6e: feb42423 sw a1,-24(s0) + GPIO_ASSERT_PARAM(handle != NULL); + 3003d72: fec42783 lw a5,-20(s0) + 3003d76: eb89 bnez a5,3003d88 + 3003d78: 0a300593 li a1,163 + 3003d7c: 030097b7 lui a5,0x3009 + 3003d80: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003d84: 3fe9 jal ra,3003d5e + 3003d86: a001 j 3003d86 + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + 3003d88: fec42783 lw a5,-20(s0) + 3003d8c: 4398 lw a4,0(a5) + 3003d8e: 145007b7 lui a5,0x14500 + 3003d92: 04f70d63 beq a4,a5,3003dec + 3003d96: fec42783 lw a5,-20(s0) + 3003d9a: 4398 lw a4,0(a5) + 3003d9c: 145017b7 lui a5,0x14501 + 3003da0: 04f70663 beq a4,a5,3003dec + 3003da4: fec42783 lw a5,-20(s0) + 3003da8: 4398 lw a4,0(a5) + 3003daa: 145027b7 lui a5,0x14502 + 3003dae: 02f70f63 beq a4,a5,3003dec + 3003db2: fec42783 lw a5,-20(s0) + 3003db6: 4398 lw a4,0(a5) + 3003db8: 145037b7 lui a5,0x14503 + 3003dbc: 02f70863 beq a4,a5,3003dec + 3003dc0: fec42783 lw a5,-20(s0) + 3003dc4: 4398 lw a4,0(a5) + 3003dc6: 145047b7 lui a5,0x14504 + 3003dca: 02f70163 beq a4,a5,3003dec + 3003dce: fec42783 lw a5,-20(s0) + 3003dd2: 4398 lw a4,0(a5) + 3003dd4: 145057b7 lui a5,0x14505 + 3003dd8: 00f70a63 beq a4,a5,3003dec + 3003ddc: 0a400593 li a1,164 + 3003de0: 030097b7 lui a5,0x3009 + 3003de4: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003de8: 3f9d jal ra,3003d5e + 3003dea: a001 j 3003dea + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + 3003dec: fe842503 lw a0,-24(s0) + 3003df0: f70ff0ef jal ra,3003560 + 3003df4: 87aa mv a5,a0 + 3003df6: 0017c793 xori a5,a5,1 + 3003dfa: 9f81 uxtb a5 + 3003dfc: cb89 beqz a5,3003e0e + 3003dfe: 0a500593 li a1,165 + 3003e02: 030097b7 lui a5,0x3009 + 3003e06: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003e0a: 3f91 jal ra,3003d5e + 3003e0c: a025 j 3003e34 + handle->baseAddress->GPIO_DATA[pins].reg ^= pins; + 3003e0e: fec42783 lw a5,-20(s0) + 3003e12: 4398 lw a4,0(a5) + 3003e14: fe842783 lw a5,-24(s0) + 3003e18: 078a slli a5,a5,0x2 + 3003e1a: 97ba add a5,a5,a4 + 3003e1c: 4398 lw a4,0(a5) + 3003e1e: fec42783 lw a5,-20(s0) + 3003e22: 4394 lw a3,0(a5) + 3003e24: fe842783 lw a5,-24(s0) + 3003e28: 8f3d xor a4,a4,a5 + 3003e2a: fe842783 lw a5,-24(s0) + 3003e2e: 078a slli a5,a5,0x2 + 3003e30: 97b6 add a5,a5,a3 + 3003e32: c398 sw a4,0(a5) +} + 3003e34: 40f2 lw ra,28(sp) + 3003e36: 4462 lw s0,24(sp) + 3003e38: 6105 addi sp,sp,32 + 3003e3a: 8082 ret + +03003e3c : + * @param pins OR logical combination of pin. + * @param mode Value of @ref GPIO_InterruptMode. + * @retval None. + */ +static void GPIO_SetLevelIrqType(GPIO_Handle *handle, unsigned int pins, GPIO_InterruptMode mode) +{ + 3003e3c: 1101 addi sp,sp,-32 + 3003e3e: ce22 sw s0,28(sp) + 3003e40: 1000 addi s0,sp,32 + 3003e42: fea42623 sw a0,-20(s0) + 3003e46: feb42423 sw a1,-24(s0) + 3003e4a: fec42223 sw a2,-28(s0) + handle->baseAddress->GPIO_IBE.reg &= ~pins; /* Disable edge detection */ + 3003e4e: fec42783 lw a5,-20(s0) + 3003e52: 439c lw a5,0(a5) + 3003e54: 4087a683 lw a3,1032(a5) + 3003e58: fe842783 lw a5,-24(s0) + 3003e5c: fff7c713 not a4,a5 + 3003e60: fec42783 lw a5,-20(s0) + 3003e64: 439c lw a5,0(a5) + 3003e66: 8f75 and a4,a4,a3 + 3003e68: 40e7a423 sw a4,1032(a5) + handle->baseAddress->GPIO_IS.reg |= pins; /* Enable level detection */ + 3003e6c: fec42783 lw a5,-20(s0) + 3003e70: 439c lw a5,0(a5) + 3003e72: 4047a683 lw a3,1028(a5) + 3003e76: fec42783 lw a5,-20(s0) + 3003e7a: 439c lw a5,0(a5) + 3003e7c: fe842703 lw a4,-24(s0) + 3003e80: 8f55 or a4,a4,a3 + 3003e82: 40e7a223 sw a4,1028(a5) + if (mode == GPIO_INT_TYPE_HIGH_LEVEL) { + 3003e86: fe442703 lw a4,-28(s0) + 3003e8a: 478d li a5,3 + 3003e8c: 02f71063 bne a4,a5,3003eac + handle->baseAddress->GPIO_IEV.reg |= pins; + 3003e90: fec42783 lw a5,-20(s0) + 3003e94: 439c lw a5,0(a5) + 3003e96: 40c7a683 lw a3,1036(a5) + 3003e9a: fec42783 lw a5,-20(s0) + 3003e9e: 439c lw a5,0(a5) + 3003ea0: fe842703 lw a4,-24(s0) + 3003ea4: 8f55 or a4,a4,a3 + 3003ea6: 40e7a623 sw a4,1036(a5) + } else { + handle->baseAddress->GPIO_IEV.reg &= ~pins; + } +} + 3003eaa: a005 j 3003eca + handle->baseAddress->GPIO_IEV.reg &= ~pins; + 3003eac: fec42783 lw a5,-20(s0) + 3003eb0: 439c lw a5,0(a5) + 3003eb2: 40c7a683 lw a3,1036(a5) + 3003eb6: fe842783 lw a5,-24(s0) + 3003eba: fff7c713 not a4,a5 + 3003ebe: fec42783 lw a5,-20(s0) + 3003ec2: 439c lw a5,0(a5) + 3003ec4: 8f75 and a4,a4,a3 + 3003ec6: 40e7a623 sw a4,1036(a5) +} + 3003eca: 0001 nop + 3003ecc: 4472 lw s0,28(sp) + 3003ece: 6105 addi sp,sp,32 + 3003ed0: 8082 ret + +03003ed2 : + * @param pins OR logical combination of pin. + * @param mode Value of @ref GPIO_InterruptMode. + * @retval None. + */ +static void GPIO_SetEdgeIrqType(GPIO_Handle *handle, unsigned int pins, GPIO_InterruptMode mode) +{ + 3003ed2: 1101 addi sp,sp,-32 + 3003ed4: ce22 sw s0,28(sp) + 3003ed6: 1000 addi s0,sp,32 + 3003ed8: fea42623 sw a0,-20(s0) + 3003edc: feb42423 sw a1,-24(s0) + 3003ee0: fec42223 sw a2,-28(s0) + handle->baseAddress->GPIO_IS.reg &= ~pins; /* Disable level detection. */ + 3003ee4: fec42783 lw a5,-20(s0) + 3003ee8: 439c lw a5,0(a5) + 3003eea: 4047a683 lw a3,1028(a5) + 3003eee: fe842783 lw a5,-24(s0) + 3003ef2: fff7c713 not a4,a5 + 3003ef6: fec42783 lw a5,-20(s0) + 3003efa: 439c lw a5,0(a5) + 3003efc: 8f75 and a4,a4,a3 + 3003efe: 40e7a223 sw a4,1028(a5) + handle->baseAddress->GPIO_IBE.reg &= ~pins; /* Clear detection on both edges. */ + 3003f02: fec42783 lw a5,-20(s0) + 3003f06: 439c lw a5,0(a5) + 3003f08: 4087a683 lw a3,1032(a5) + 3003f0c: fe842783 lw a5,-24(s0) + 3003f10: fff7c713 not a4,a5 + 3003f14: fec42783 lw a5,-20(s0) + 3003f18: 439c lw a5,0(a5) + 3003f1a: 8f75 and a4,a4,a3 + 3003f1c: 40e7a423 sw a4,1032(a5) + if (mode == GPIO_INT_TYPE_RISE_EDGE) { + 3003f20: fe442703 lw a4,-28(s0) + 3003f24: 4785 li a5,1 + 3003f26: 02f71063 bne a4,a5,3003f46 + handle->baseAddress->GPIO_IEV.reg |= pins; + 3003f2a: fec42783 lw a5,-20(s0) + 3003f2e: 439c lw a5,0(a5) + 3003f30: 40c7a683 lw a3,1036(a5) + 3003f34: fec42783 lw a5,-20(s0) + 3003f38: 439c lw a5,0(a5) + 3003f3a: fe842703 lw a4,-24(s0) + 3003f3e: 8f55 or a4,a4,a3 + 3003f40: 40e7a623 sw a4,1036(a5) + } else { + handle->baseAddress->GPIO_IEV.reg &= ~pins; + } +} + 3003f44: a005 j 3003f64 + handle->baseAddress->GPIO_IEV.reg &= ~pins; + 3003f46: fec42783 lw a5,-20(s0) + 3003f4a: 439c lw a5,0(a5) + 3003f4c: 40c7a683 lw a3,1036(a5) + 3003f50: fe842783 lw a5,-24(s0) + 3003f54: fff7c713 not a4,a5 + 3003f58: fec42783 lw a5,-20(s0) + 3003f5c: 439c lw a5,0(a5) + 3003f5e: 8f75 and a4,a4,a3 + 3003f60: 40e7a623 sw a4,1036(a5) +} + 3003f64: 0001 nop + 3003f66: 4472 lw s0,28(sp) + 3003f68: 6105 addi sp,sp,32 + 3003f6a: 8082 ret + +03003f6c : + * @param pins OR logical combination of pin. + * @param mode Value of @ref GPIO_InterruptMode. + * @retval Value of @ref BASE_StatusType. + */ +BASE_StatusType HAL_GPIO_SetIrqType(GPIO_Handle *handle, unsigned int pins, GPIO_InterruptMode mode) +{ + 3003f6c: 1101 addi sp,sp,-32 + 3003f6e: ce06 sw ra,28(sp) + 3003f70: cc22 sw s0,24(sp) + 3003f72: 1000 addi s0,sp,32 + 3003f74: fea42623 sw a0,-20(s0) + 3003f78: feb42423 sw a1,-24(s0) + 3003f7c: fec42223 sw a2,-28(s0) + GPIO_ASSERT_PARAM(handle != NULL); + 3003f80: fec42783 lw a5,-20(s0) + 3003f84: eb89 bnez a5,3003f96 + 3003f86: 0ef00593 li a1,239 + 3003f8a: 030097b7 lui a5,0x3009 + 3003f8e: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003f92: 33f1 jal ra,3003d5e + 3003f94: a001 j 3003f94 + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + 3003f96: fec42783 lw a5,-20(s0) + 3003f9a: 4398 lw a4,0(a5) + 3003f9c: 145007b7 lui a5,0x14500 + 3003fa0: 04f70d63 beq a4,a5,3003ffa + 3003fa4: fec42783 lw a5,-20(s0) + 3003fa8: 4398 lw a4,0(a5) + 3003faa: 145017b7 lui a5,0x14501 + 3003fae: 04f70663 beq a4,a5,3003ffa + 3003fb2: fec42783 lw a5,-20(s0) + 3003fb6: 4398 lw a4,0(a5) + 3003fb8: 145027b7 lui a5,0x14502 + 3003fbc: 02f70f63 beq a4,a5,3003ffa + 3003fc0: fec42783 lw a5,-20(s0) + 3003fc4: 4398 lw a4,0(a5) + 3003fc6: 145037b7 lui a5,0x14503 + 3003fca: 02f70863 beq a4,a5,3003ffa + 3003fce: fec42783 lw a5,-20(s0) + 3003fd2: 4398 lw a4,0(a5) + 3003fd4: 145047b7 lui a5,0x14504 + 3003fd8: 02f70163 beq a4,a5,3003ffa + 3003fdc: fec42783 lw a5,-20(s0) + 3003fe0: 4398 lw a4,0(a5) + 3003fe2: 145057b7 lui a5,0x14505 + 3003fe6: 00f70a63 beq a4,a5,3003ffa + 3003fea: 0f000593 li a1,240 + 3003fee: 030097b7 lui a5,0x3009 + 3003ff2: 9e078513 addi a0,a5,-1568 # 30089e0 + 3003ff6: 33a5 jal ra,3003d5e + 3003ff8: a001 j 3003ff8 + GPIO_PARAM_CHECK_WITH_RET(IsGpioPins(pins), BASE_STATUS_ERROR); + 3003ffa: fe842503 lw a0,-24(s0) + 3003ffe: d62ff0ef jal ra,3003560 + 3004002: 87aa mv a5,a0 + 3004004: 0017c793 xori a5,a5,1 + 3004008: 9f81 uxtb a5 + 300400a: cb91 beqz a5,300401e + 300400c: 0f100593 li a1,241 + 3004010: 030097b7 lui a5,0x3009 + 3004014: 9e078513 addi a0,a5,-1568 # 30089e0 + 3004018: 3399 jal ra,3003d5e + 300401a: 4785 li a5,1 + 300401c: aa91 j 3004170 + GPIO_PARAM_CHECK_WITH_RET(IsGpioITMode(mode), BASE_STATUS_ERROR); + 300401e: fe442503 lw a0,-28(s0) + 3004022: decff0ef jal ra,300360e + 3004026: 87aa mv a5,a0 + 3004028: 0017c793 xori a5,a5,1 + 300402c: 9f81 uxtb a5 + 300402e: cb91 beqz a5,3004042 + 3004030: 0f200593 li a1,242 + 3004034: 030097b7 lui a5,0x3009 + 3004038: 9e078513 addi a0,a5,-1568 # 30089e0 + 300403c: 330d jal ra,3003d5e + 300403e: 4785 li a5,1 + 3004040: aa05 j 3004170 + + /* It must be disabled to avoid triggering interrupts during configuration. */ + DCL_GPIO_DisableIrq(handle->baseAddress, pins); + 3004042: fec42783 lw a5,-20(s0) + 3004046: 439c lw a5,0(a5) + 3004048: fe842583 lw a1,-24(s0) + 300404c: 853e mv a0,a5 + 300404e: 3a15 jal ra,3003982 + + if ((mode == GPIO_INT_TYPE_HIGH_LEVEL) || (mode == GPIO_INT_TYPE_LOW_LEVEL)) { + 3004050: fe442703 lw a4,-28(s0) + 3004054: 478d li a5,3 + 3004056: 00f70763 beq a4,a5,3004064 + 300405a: fe442703 lw a4,-28(s0) + 300405e: 4789 li a5,2 + 3004060: 00f71a63 bne a4,a5,3004074 + GPIO_SetLevelIrqType(handle, pins, mode); + 3004064: fe442603 lw a2,-28(s0) + 3004068: fe842583 lw a1,-24(s0) + 300406c: fec42503 lw a0,-20(s0) + 3004070: 33f1 jal ra,3003e3c + 3004072: a0f5 j 300415e + } else if (mode == GPIO_INT_TYPE_BOTH_EDGE) { + 3004074: fe442703 lw a4,-28(s0) + 3004078: 4791 li a5,4 + 300407a: 04f71e63 bne a4,a5,30040d6 + handle->baseAddress->GPIO_IEV.reg &= ~pins; + 300407e: fec42783 lw a5,-20(s0) + 3004082: 439c lw a5,0(a5) + 3004084: 40c7a683 lw a3,1036(a5) + 3004088: fe842783 lw a5,-24(s0) + 300408c: fff7c713 not a4,a5 + 3004090: fec42783 lw a5,-20(s0) + 3004094: 439c lw a5,0(a5) + 3004096: 8f75 and a4,a4,a3 + 3004098: 40e7a623 sw a4,1036(a5) + handle->baseAddress->GPIO_IS.reg &= ~pins; + 300409c: fec42783 lw a5,-20(s0) + 30040a0: 439c lw a5,0(a5) + 30040a2: 4047a683 lw a3,1028(a5) + 30040a6: fe842783 lw a5,-24(s0) + 30040aa: fff7c713 not a4,a5 + 30040ae: fec42783 lw a5,-20(s0) + 30040b2: 439c lw a5,0(a5) + 30040b4: 8f75 and a4,a4,a3 + 30040b6: 40e7a223 sw a4,1028(a5) + handle->baseAddress->GPIO_IBE.reg |= pins; + 30040ba: fec42783 lw a5,-20(s0) + 30040be: 439c lw a5,0(a5) + 30040c0: 4087a683 lw a3,1032(a5) + 30040c4: fec42783 lw a5,-20(s0) + 30040c8: 439c lw a5,0(a5) + 30040ca: fe842703 lw a4,-24(s0) + 30040ce: 8f55 or a4,a4,a3 + 30040d0: 40e7a423 sw a4,1032(a5) + 30040d4: a069 j 300415e + } else if ((mode == GPIO_INT_TYPE_RISE_EDGE) || (mode == GPIO_INT_TYPE_FALL_EDGE)) { + 30040d6: fe442703 lw a4,-28(s0) + 30040da: 4785 li a5,1 + 30040dc: 00f70563 beq a4,a5,30040e6 + 30040e0: fe442783 lw a5,-28(s0) + 30040e4: eb89 bnez a5,30040f6 + GPIO_SetEdgeIrqType(handle, pins, mode); + 30040e6: fe442603 lw a2,-28(s0) + 30040ea: fe842583 lw a1,-24(s0) + 30040ee: fec42503 lw a0,-20(s0) + 30040f2: 33c5 jal ra,3003ed2 + 30040f4: a0ad j 300415e + } else if (mode == GPIO_INT_TYPE_NONE) { + 30040f6: fe442703 lw a4,-28(s0) + 30040fa: 4795 li a5,5 + 30040fc: 06f71163 bne a4,a5,300415e + /* No interruptMode: disable everything. */ + handle->baseAddress->GPIO_IEV.reg &= ~pins; + 3004100: fec42783 lw a5,-20(s0) + 3004104: 439c lw a5,0(a5) + 3004106: 40c7a683 lw a3,1036(a5) + 300410a: fe842783 lw a5,-24(s0) + 300410e: fff7c713 not a4,a5 + 3004112: fec42783 lw a5,-20(s0) + 3004116: 439c lw a5,0(a5) + 3004118: 8f75 and a4,a4,a3 + 300411a: 40e7a623 sw a4,1036(a5) + handle->baseAddress->GPIO_IS.reg &= ~pins; + 300411e: fec42783 lw a5,-20(s0) + 3004122: 439c lw a5,0(a5) + 3004124: 4047a683 lw a3,1028(a5) + 3004128: fe842783 lw a5,-24(s0) + 300412c: fff7c713 not a4,a5 + 3004130: fec42783 lw a5,-20(s0) + 3004134: 439c lw a5,0(a5) + 3004136: 8f75 and a4,a4,a3 + 3004138: 40e7a223 sw a4,1028(a5) + handle->baseAddress->GPIO_IBE.reg &= ~pins; + 300413c: fec42783 lw a5,-20(s0) + 3004140: 439c lw a5,0(a5) + 3004142: 4087a683 lw a3,1032(a5) + 3004146: fe842783 lw a5,-24(s0) + 300414a: fff7c713 not a4,a5 + 300414e: fec42783 lw a5,-20(s0) + 3004152: 439c lw a5,0(a5) + 3004154: 8f75 and a4,a4,a3 + 3004156: 40e7a423 sw a4,1032(a5) + return BASE_STATUS_ERROR; + 300415a: 4785 li a5,1 + 300415c: a811 j 3004170 + } + + DCL_GPIO_EnableIrq(handle->baseAddress, pins); + 300415e: fec42783 lw a5,-20(s0) + 3004162: 439c lw a5,0(a5) + 3004164: fe842583 lw a1,-24(s0) + 3004168: 853e mv a0,a5 + 300416a: f68ff0ef jal ra,30038d2 + return BASE_STATUS_OK; + 300416e: 4781 li a5,0 +} + 3004170: 853e mv a0,a5 + 3004172: 40f2 lw ra,28(sp) + 3004174: 4462 lw s0,24(sp) + 3004176: 6105 addi sp,sp,32 + 3004178: 8082 ret + +0300417a : + * @param handle Value of @ref GPIO_Handle. + * @param pin Value of @ref GPIO_PIN. + * @retval None. + */ +static void GPIO_ExcuteCallBack(GPIO_Handle *handle, GPIO_PIN pin) +{ + 300417a: 7179 addi sp,sp,-48 + 300417c: d606 sw ra,44(sp) + 300417e: d422 sw s0,40(sp) + 3004180: 1800 addi s0,sp,48 + 3004182: fca42e23 sw a0,-36(s0) + 3004186: fcb42c23 sw a1,-40(s0) + GPIO_ASSERT_PARAM(handle != NULL); + 300418a: fdc42783 lw a5,-36(s0) + 300418e: eb89 bnez a5,30041a0 + 3004190: 11300593 li a1,275 + 3004194: 030097b7 lui a5,0x3009 + 3004198: 9e078513 addi a0,a5,-1568 # 30089e0 + 300419c: 36c9 jal ra,3003d5e + 300419e: a001 j 300419e + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + 30041a0: fdc42783 lw a5,-36(s0) + 30041a4: 4398 lw a4,0(a5) + 30041a6: 145007b7 lui a5,0x14500 + 30041aa: 04f70d63 beq a4,a5,3004204 + 30041ae: fdc42783 lw a5,-36(s0) + 30041b2: 4398 lw a4,0(a5) + 30041b4: 145017b7 lui a5,0x14501 + 30041b8: 04f70663 beq a4,a5,3004204 + 30041bc: fdc42783 lw a5,-36(s0) + 30041c0: 4398 lw a4,0(a5) + 30041c2: 145027b7 lui a5,0x14502 + 30041c6: 02f70f63 beq a4,a5,3004204 + 30041ca: fdc42783 lw a5,-36(s0) + 30041ce: 4398 lw a4,0(a5) + 30041d0: 145037b7 lui a5,0x14503 + 30041d4: 02f70863 beq a4,a5,3004204 + 30041d8: fdc42783 lw a5,-36(s0) + 30041dc: 4398 lw a4,0(a5) + 30041de: 145047b7 lui a5,0x14504 + 30041e2: 02f70163 beq a4,a5,3004204 + 30041e6: fdc42783 lw a5,-36(s0) + 30041ea: 4398 lw a4,0(a5) + 30041ec: 145057b7 lui a5,0x14505 + 30041f0: 00f70a63 beq a4,a5,3004204 + 30041f4: 11400593 li a1,276 + 30041f8: 030097b7 lui a5,0x3009 + 30041fc: 9e078513 addi a0,a5,-1568 # 30089e0 + 3004200: 3eb9 jal ra,3003d5e + 3004202: a001 j 3004202 + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pin)); + 3004204: fd842503 lw a0,-40(s0) + 3004208: b58ff0ef jal ra,3003560 + 300420c: 87aa mv a5,a0 + 300420e: 0017c793 xori a5,a5,1 + 3004212: 9f81 uxtb a5 + 3004214: cb89 beqz a5,3004226 + 3004216: 11500593 li a1,277 + 300421a: 030097b7 lui a5,0x3009 + 300421e: 9e078513 addi a0,a5,-1568 # 30089e0 + 3004222: 3e35 jal ra,3003d5e + 3004224: a899 j 300427a + for (unsigned int i = 0; i < GPIO_PIN_NUM; i++) { + 3004226: fe042623 sw zero,-20(s0) + 300422a: a099 j 3004270 + if (handle->userCallBack.GPIO_CallbackFuncs[i].pin == pin) { + 300422c: fdc42703 lw a4,-36(s0) + 3004230: fec42783 lw a5,-20(s0) + 3004234: 078e slli a5,a5,0x3 + 3004236: 97ba add a5,a5,a4 + 3004238: 479c lw a5,8(a5) + 300423a: fd842703 lw a4,-40(s0) + 300423e: 02f71463 bne a4,a5,3004266 + if (handle->userCallBack.GPIO_CallbackFuncs[i].callbackFunc != NULL) { + 3004242: fdc42703 lw a4,-36(s0) + 3004246: fec42783 lw a5,-20(s0) + 300424a: 078e slli a5,a5,0x3 + 300424c: 97ba add a5,a5,a4 + 300424e: 47dc lw a5,12(a5) + 3004250: cb99 beqz a5,3004266 + handle->userCallBack.GPIO_CallbackFuncs[i].callbackFunc(handle); + 3004252: fdc42703 lw a4,-36(s0) + 3004256: fec42783 lw a5,-20(s0) + 300425a: 078e slli a5,a5,0x3 + 300425c: 97ba add a5,a5,a4 + 300425e: 47dc lw a5,12(a5) + 3004260: fdc42503 lw a0,-36(s0) + 3004264: 9782 jalr a5 + for (unsigned int i = 0; i < GPIO_PIN_NUM; i++) { + 3004266: fec42783 lw a5,-20(s0) + 300426a: 0785 addi a5,a5,1 + 300426c: fef42623 sw a5,-20(s0) + 3004270: fec42703 lw a4,-20(s0) + 3004274: 479d li a5,7 + 3004276: fae7fbe3 bgeu a5,a4,300422c + } + } + } +} + 300427a: 50b2 lw ra,44(sp) + 300427c: 5422 lw s0,40(sp) + 300427e: 6145 addi sp,sp,48 + 3004280: 8082 ret + +03004282 : + * @brief Handle GPIO interrupt request. + * @param handle Interrupt parameter. + * @retval None. + */ +void HAL_GPIO_IrqHandler(void *handle) +{ + 3004282: 7179 addi sp,sp,-48 + 3004284: d606 sw ra,44(sp) + 3004286: d422 sw s0,40(sp) + 3004288: 1800 addi s0,sp,48 + 300428a: fca42e23 sw a0,-36(s0) + GPIO_Handle *gpioHandle = (GPIO_Handle *)handle; + 300428e: fdc42783 lw a5,-36(s0) + 3004292: fef42423 sw a5,-24(s0) + GPIO_ASSERT_PARAM(gpioHandle != NULL); + 3004296: fe842783 lw a5,-24(s0) + 300429a: eb89 bnez a5,30042ac + 300429c: 12700593 li a1,295 + 30042a0: 030097b7 lui a5,0x3009 + 30042a4: 9e078513 addi a0,a5,-1568 # 30089e0 + 30042a8: 3c5d jal ra,3003d5e + 30042aa: a001 j 30042aa + GPIO_ASSERT_PARAM(IsGPIOInstance(gpioHandle->baseAddress)); + 30042ac: fe842783 lw a5,-24(s0) + 30042b0: 4398 lw a4,0(a5) + 30042b2: 145007b7 lui a5,0x14500 + 30042b6: 04f70d63 beq a4,a5,3004310 + 30042ba: fe842783 lw a5,-24(s0) + 30042be: 4398 lw a4,0(a5) + 30042c0: 145017b7 lui a5,0x14501 + 30042c4: 04f70663 beq a4,a5,3004310 + 30042c8: fe842783 lw a5,-24(s0) + 30042cc: 4398 lw a4,0(a5) + 30042ce: 145027b7 lui a5,0x14502 + 30042d2: 02f70f63 beq a4,a5,3004310 + 30042d6: fe842783 lw a5,-24(s0) + 30042da: 4398 lw a4,0(a5) + 30042dc: 145037b7 lui a5,0x14503 + 30042e0: 02f70863 beq a4,a5,3004310 + 30042e4: fe842783 lw a5,-24(s0) + 30042e8: 4398 lw a4,0(a5) + 30042ea: 145047b7 lui a5,0x14504 + 30042ee: 02f70163 beq a4,a5,3004310 + 30042f2: fe842783 lw a5,-24(s0) + 30042f6: 4398 lw a4,0(a5) + 30042f8: 145057b7 lui a5,0x14505 + 30042fc: 00f70a63 beq a4,a5,3004310 + 3004300: 12800593 li a1,296 + 3004304: 030097b7 lui a5,0x3009 + 3004308: 9e078513 addi a0,a5,-1568 # 30089e0 + 300430c: 3c89 jal ra,3003d5e + 300430e: a001 j 300430e + unsigned int position = 0x00000000U; + 3004310: fe042623 sw zero,-20(s0) + unsigned int pinCurrent = 0x00000000U; + 3004314: fe042223 sw zero,-28(s0) + unsigned int mis = DCL_GPIO_GetMIS(gpioHandle->baseAddress); /* Queries the masked GPIO interrupt status. */ + 3004318: fe842783 lw a5,-24(s0) + 300431c: 439c lw a5,0(a5) + 300431e: 853e mv a0,a5 + 3004320: f0cff0ef jal ra,3003a2c + 3004324: fea42023 sw a0,-32(s0) + + /* Determine which pin sets the callback function. */ + while ((mis >> position) != BASE_CFG_UNSET) { + 3004328: a0b1 j 3004374 + pinCurrent = mis & (1 << position); + 300432a: 4705 li a4,1 + 300432c: fec42783 lw a5,-20(s0) + 3004330: 00f717b3 sll a5,a4,a5 + 3004334: 873e mv a4,a5 + 3004336: fe042783 lw a5,-32(s0) + 300433a: 8ff9 and a5,a5,a4 + 300433c: fef42223 sw a5,-28(s0) + if (pinCurrent) { + 3004340: fe442783 lw a5,-28(s0) + 3004344: c39d beqz a5,300436a + gpioHandle->pins = pinCurrent; + 3004346: fe842783 lw a5,-24(s0) + 300434a: fe442703 lw a4,-28(s0) + 300434e: c3d8 sw a4,4(a5) + DCL_GPIO_ClearIrq(gpioHandle->baseAddress, pinCurrent); + 3004350: fe842783 lw a5,-24(s0) + 3004354: 439c lw a5,0(a5) + 3004356: fe442583 lw a1,-28(s0) + 300435a: 853e mv a0,a5 + 300435c: cd0ff0ef jal ra,300382c + GPIO_ExcuteCallBack(gpioHandle, pinCurrent); + 3004360: fe442583 lw a1,-28(s0) + 3004364: fe842503 lw a0,-24(s0) + 3004368: 3d09 jal ra,300417a + } + position++; + 300436a: fec42783 lw a5,-20(s0) + 300436e: 0785 addi a5,a5,1 + 3004370: fef42623 sw a5,-20(s0) + while ((mis >> position) != BASE_CFG_UNSET) { + 3004374: fe042703 lw a4,-32(s0) + 3004378: fec42783 lw a5,-20(s0) + 300437c: 00f757b3 srl a5,a4,a5 + 3004380: f7cd bnez a5,300432a + } +} + 3004382: 0001 nop + 3004384: 50b2 lw ra,44(sp) + 3004386: 5422 lw s0,40(sp) + 3004388: 6145 addi sp,sp,48 + 300438a: 8082 ret + +0300438c : + * @param pin Value of @ref GPIO_PIN. + * @param pCallback Value of @ref GPIO_CallbackType. + * @retval None. + */ +void HAL_GPIO_RegisterCallBack(GPIO_Handle *handle, GPIO_PIN pin, GPIO_CallbackType pCallback) +{ + 300438c: 7179 addi sp,sp,-48 + 300438e: d606 sw ra,44(sp) + 3004390: d422 sw s0,40(sp) + 3004392: 1800 addi s0,sp,48 + 3004394: fca42e23 sw a0,-36(s0) + 3004398: fcb42c23 sw a1,-40(s0) + 300439c: fcc42a23 sw a2,-44(s0) + GPIO_ASSERT_PARAM(handle != NULL); + 30043a0: fdc42783 lw a5,-36(s0) + 30043a4: eb89 bnez a5,30043b6 + 30043a6: 14200593 li a1,322 + 30043aa: 030097b7 lui a5,0x3009 + 30043ae: 9e078513 addi a0,a5,-1568 # 30089e0 + 30043b2: 3275 jal ra,3003d5e + 30043b4: a001 j 30043b4 + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + 30043b6: fdc42783 lw a5,-36(s0) + 30043ba: 4398 lw a4,0(a5) + 30043bc: 145007b7 lui a5,0x14500 + 30043c0: 04f70d63 beq a4,a5,300441a + 30043c4: fdc42783 lw a5,-36(s0) + 30043c8: 4398 lw a4,0(a5) + 30043ca: 145017b7 lui a5,0x14501 + 30043ce: 04f70663 beq a4,a5,300441a + 30043d2: fdc42783 lw a5,-36(s0) + 30043d6: 4398 lw a4,0(a5) + 30043d8: 145027b7 lui a5,0x14502 + 30043dc: 02f70f63 beq a4,a5,300441a + 30043e0: fdc42783 lw a5,-36(s0) + 30043e4: 4398 lw a4,0(a5) + 30043e6: 145037b7 lui a5,0x14503 + 30043ea: 02f70863 beq a4,a5,300441a + 30043ee: fdc42783 lw a5,-36(s0) + 30043f2: 4398 lw a4,0(a5) + 30043f4: 145047b7 lui a5,0x14504 + 30043f8: 02f70163 beq a4,a5,300441a + 30043fc: fdc42783 lw a5,-36(s0) + 3004400: 4398 lw a4,0(a5) + 3004402: 145057b7 lui a5,0x14505 + 3004406: 00f70a63 beq a4,a5,300441a + 300440a: 14300593 li a1,323 + 300440e: 030097b7 lui a5,0x3009 + 3004412: 9e078513 addi a0,a5,-1568 # 30089e0 + 3004416: 32a1 jal ra,3003d5e + 3004418: a001 j 3004418 + GPIO_PARAM_CHECK_NO_RET(IsGpioPin(pin)); + 300441a: fd842503 lw a0,-40(s0) + 300441e: 972ff0ef jal ra,3003590 + 3004422: 87aa mv a5,a0 + 3004424: 0017c793 xori a5,a5,1 + 3004428: 9f81 uxtb a5 + 300442a: cb89 beqz a5,300443c + 300442c: 14400593 li a1,324 + 3004430: 030097b7 lui a5,0x3009 + 3004434: 9e078513 addi a0,a5,-1568 # 30089e0 + 3004438: 321d jal ra,3003d5e + 300443a: a091 j 300447e + for (unsigned int i = 0; i < GPIO_PIN_NUM; i++) { + 300443c: fe042623 sw zero,-20(s0) + 3004440: a815 j 3004474 + if (handle->userCallBack.GPIO_CallbackFuncs[i].pin == pin) { + 3004442: fdc42703 lw a4,-36(s0) + 3004446: fec42783 lw a5,-20(s0) + 300444a: 078e slli a5,a5,0x3 + 300444c: 97ba add a5,a5,a4 + 300444e: 479c lw a5,8(a5) + 3004450: fd842703 lw a4,-40(s0) + 3004454: 00f71b63 bne a4,a5,300446a + handle->userCallBack.GPIO_CallbackFuncs[i].callbackFunc = pCallback; + 3004458: fdc42703 lw a4,-36(s0) + 300445c: fec42783 lw a5,-20(s0) + 3004460: 078e slli a5,a5,0x3 + 3004462: 97ba add a5,a5,a4 + 3004464: fd442703 lw a4,-44(s0) + 3004468: c7d8 sw a4,12(a5) + for (unsigned int i = 0; i < GPIO_PIN_NUM; i++) { + 300446a: fec42783 lw a5,-20(s0) + 300446e: 0785 addi a5,a5,1 + 3004470: fef42623 sw a5,-20(s0) + 3004474: fec42703 lw a4,-20(s0) + 3004478: 479d li a5,7 + 300447a: fce7f4e3 bgeu a5,a4,3004442 + } + } + 300447e: 50b2 lw ra,44(sp) + 3004480: 5422 lw s0,40(sp) + 3004482: 6145 addi sp,sp,48 + 3004484: 8082 ret + +03004486 : + * @param functionMode I2C function mode type. + * @retval true + * @retval false + */ +static inline bool IsI2cFunctionMode(I2C_ModeSelectType functionMode) +{ + 3004486: 1101 addi sp,sp,-32 + 3004488: ce22 sw s0,28(sp) + 300448a: 1000 addi s0,sp,32 + 300448c: fea42623 sw a0,-20(s0) + return (functionMode == I2C_MODE_SELECT_NONE || + functionMode == I2C_MODE_SELECT_MASTER_ONLY || + functionMode == I2C_MODE_SELECT_SLAVE_ONLY || + 3004490: fec42783 lw a5,-20(s0) + 3004494: c385 beqz a5,30044b4 + return (functionMode == I2C_MODE_SELECT_NONE || + 3004496: fec42703 lw a4,-20(s0) + 300449a: 4785 li a5,1 + 300449c: 00f70c63 beq a4,a5,30044b4 + functionMode == I2C_MODE_SELECT_MASTER_ONLY || + 30044a0: fec42703 lw a4,-20(s0) + 30044a4: 4789 li a5,2 + 30044a6: 00f70763 beq a4,a5,30044b4 + functionMode == I2C_MODE_SELECT_SLAVE_ONLY || + 30044aa: fec42703 lw a4,-20(s0) + 30044ae: 478d li a5,3 + 30044b0: 00f71463 bne a4,a5,30044b8 + 30044b4: 4785 li a5,1 + 30044b6: a011 j 30044ba + 30044b8: 4781 li a5,0 + 30044ba: 8b85 andi a5,a5,1 + 30044bc: 9f81 uxtb a5 + functionMode == I2C_MODE_SELECT_MASTER_SLAVE); +} + 30044be: 853e mv a0,a5 + 30044c0: 4472 lw s0,28(sp) + 30044c2: 6105 addi sp,sp,32 + 30044c4: 8082 ret + +030044c6 : + * @param addrMode I2C instance + * @retval true + * @retval false + */ +static inline bool IsI2cAddressMode(I2C_AddressMode addrMode) +{ + 30044c6: 1101 addi sp,sp,-32 + 30044c8: ce22 sw s0,28(sp) + 30044ca: 1000 addi s0,sp,32 + 30044cc: fea42623 sw a0,-20(s0) + return (addrMode == I2C_7_BITS || + 30044d0: fec42783 lw a5,-20(s0) + 30044d4: c791 beqz a5,30044e0 + 30044d6: fec42703 lw a4,-20(s0) + 30044da: 4785 li a5,1 + 30044dc: 00f71463 bne a4,a5,30044e4 + 30044e0: 4785 li a5,1 + 30044e2: a011 j 30044e6 + 30044e4: 4781 li a5,0 + 30044e6: 8b85 andi a5,a5,1 + 30044e8: 9f81 uxtb a5 + addrMode == I2C_10_BITS); +} + 30044ea: 853e mv a0,a5 + 30044ec: 4472 lw s0,28(sp) + 30044ee: 6105 addi sp,sp,32 + 30044f0: 8082 ret + +030044f2 : + * @param sdaHoldTime I2C instance + * @retval true + * @retval false + */ +static inline bool IsI2cSdaHoldTime(unsigned int sdaHoldTime) +{ + 30044f2: 1101 addi sp,sp,-32 + 30044f4: ce22 sw s0,28(sp) + 30044f6: 1000 addi s0,sp,32 + 30044f8: fea42623 sw a0,-20(s0) + return (sdaHoldTime <= 0xFFFF); /* SdaHoldTime value is 0 to 0xFFFF */ + 30044fc: fec42703 lw a4,-20(s0) + 3004500: 67c1 lui a5,0x10 + 3004502: 00f737b3 sltu a5,a4,a5 + 3004506: 9f81 uxtb a5 +} + 3004508: 853e mv a0,a5 + 300450a: 4472 lw s0,28(sp) + 300450c: 6105 addi sp,sp,32 + 300450e: 8082 ret + +03004510 : + * @param generalCallMode I2C general call mode. + * @retval true + * @retval false + */ +static inline bool IsI2cGeneralCallMode(unsigned int generalCallMode) +{ + 3004510: 1101 addi sp,sp,-32 + 3004512: ce22 sw s0,28(sp) + 3004514: 1000 addi s0,sp,32 + 3004516: fea42623 sw a0,-20(s0) + return (generalCallMode == BASE_CFG_ENABLE || + 300451a: fec42703 lw a4,-20(s0) + 300451e: 4785 li a5,1 + 3004520: 00f70563 beq a4,a5,300452a + 3004524: fec42783 lw a5,-20(s0) + 3004528: e399 bnez a5,300452e + 300452a: 4785 li a5,1 + 300452c: a011 j 3004530 + 300452e: 4781 li a5,0 + 3004530: 8b85 andi a5,a5,1 + 3004532: 9f81 uxtb a5 + generalCallMode == BASE_CFG_DISABLE); +} + 3004534: 853e mv a0,a5 + 3004536: 4472 lw s0,28(sp) + 3004538: 6105 addi sp,sp,32 + 300453a: 8082 ret + +0300453c : + * @param ownAddress I2C own address. + * @retval true + * @retval false + */ +static inline bool IsI2cOwnAddressOrMask(unsigned int ownAddress) +{ + 300453c: 1101 addi sp,sp,-32 + 300453e: ce22 sw s0,28(sp) + 3004540: 1000 addi s0,sp,32 + 3004542: fea42623 sw a0,-20(s0) + return (ownAddress <= XMBUS_OWN_ADDRESS_MASK); /* Own address value is 0 to 0x3FF */ + 3004546: fec42783 lw a5,-20(s0) + 300454a: 4007b793 sltiu a5,a5,1024 + 300454e: 9f81 uxtb a5 +} + 3004550: 853e mv a0,a5 + 3004552: 4472 lw s0,28(sp) + 3004554: 6105 addi sp,sp,32 + 3004556: 8082 ret + +03004558 : + * @param xmbusAddress XMBus address. + * @retval true + * @retval false + */ +static inline bool IsXMBusAddressOrMask(unsigned int xmbusAddress) +{ + 3004558: 1101 addi sp,sp,-32 + 300455a: ce22 sw s0,28(sp) + 300455c: 1000 addi s0,sp,32 + 300455e: fea42623 sw a0,-20(s0) + return (xmbusAddress <= XMBUS_OWN_ADDRESS_MASK); /* XMBus address value is 0 to 0x3FF */ + 3004562: fec42783 lw a5,-20(s0) + 3004566: 4007b793 sltiu a5,a5,1024 + 300456a: 9f81 uxtb a5 +} + 300456c: 853e mv a0,a5 + 300456e: 4472 lw s0,28(sp) + 3004570: 6105 addi sp,sp,32 + 3004572: 8082 ret + +03004574 : + * @param xmbusAddress XMBus address. + * @retval true + * @retval false + */ +static inline bool IsXMBusAddressEnable(unsigned int slaveOwnXmbAddressEnable) +{ + 3004574: 1101 addi sp,sp,-32 + 3004576: ce22 sw s0,28(sp) + 3004578: 1000 addi s0,sp,32 + 300457a: fea42623 sw a0,-20(s0) + return (slaveOwnXmbAddressEnable == BASE_CFG_ENABLE || slaveOwnXmbAddressEnable == BASE_CFG_DISABLE); + 300457e: fec42703 lw a4,-20(s0) + 3004582: 4785 li a5,1 + 3004584: 00f70563 beq a4,a5,300458e + 3004588: fec42783 lw a5,-20(s0) + 300458c: e399 bnez a5,3004592 + 300458e: 4785 li a5,1 + 3004590: a011 j 3004594 + 3004592: 4781 li a5,0 + 3004594: 8b85 andi a5,a5,1 + 3004596: 9f81 uxtb a5 +} + 3004598: 853e mv a0,a5 + 300459a: 4472 lw s0,28(sp) + 300459c: 6105 addi sp,sp,32 + 300459e: 8082 ret + +030045a0 : + * @param spikeFilterTime I2C SDA and SCL Glitch Filtering Time. + * @retval true + * @retval false + */ +static inline bool IsI2cSpikeFilterTime(unsigned int spikeFilterTime) +{ + 30045a0: 1101 addi sp,sp,-32 + 30045a2: ce22 sw s0,28(sp) + 30045a4: 1000 addi s0,sp,32 + 30045a6: fea42623 sw a0,-20(s0) + return (spikeFilterTime <= 0xF); /* The spikeFilterTime value is 0 to 0xF */ + 30045aa: fec42783 lw a5,-20(s0) + 30045ae: 0107b793 sltiu a5,a5,16 + 30045b2: 9f81 uxtb a5 +} + 30045b4: 853e mv a0,a5 + 30045b6: 4472 lw s0,28(sp) + 30045b8: 6105 addi sp,sp,32 + 30045ba: 8082 ret + +030045bc : + * @param freq I2C freq + * @retval true + * @retval false + */ +static inline bool IsI2cFreq(unsigned int freq) +{ + 30045bc: 1101 addi sp,sp,-32 + 30045be: ce22 sw s0,28(sp) + 30045c0: 1000 addi s0,sp,32 + 30045c2: fea42623 sw a0,-20(s0) + return (freq > 0); + 30045c6: fec42783 lw a5,-20(s0) + 30045ca: 00f037b3 snez a5,a5 + 30045ce: 9f81 uxtb a5 +} + 30045d0: 853e mv a0,a5 + 30045d2: 4472 lw s0,28(sp) + 30045d4: 6105 addi sp,sp,32 + 30045d6: 8082 ret + +030045d8 : + * @param ignoreAckFlag I2C ignore ack flag. + * @retval true + * @retval false + */ +static inline bool IsI2cIgnoreAckFlag(unsigned int ignoreAckFlag) +{ + 30045d8: 1101 addi sp,sp,-32 + 30045da: ce22 sw s0,28(sp) + 30045dc: 1000 addi s0,sp,32 + 30045de: fea42623 sw a0,-20(s0) + return (ignoreAckFlag == I2C_IGNORE_NAK_ENABLE || + 30045e2: fec42703 lw a4,-20(s0) + 30045e6: 4785 li a5,1 + 30045e8: 00f70563 beq a4,a5,30045f2 + 30045ec: fec42783 lw a5,-20(s0) + 30045f0: e399 bnez a5,30045f6 + 30045f2: 4785 li a5,1 + 30045f4: a011 j 30045f8 + 30045f6: 4781 li a5,0 + 30045f8: 8b85 andi a5,a5,1 + 30045fa: 9f81 uxtb a5 + ignoreAckFlag == I2C_IGNORE_NAK_DISABLE); +} + 30045fc: 853e mv a0,a5 + 30045fe: 4472 lw s0,28(sp) + 3004600: 6105 addi sp,sp,32 + 3004602: 8082 ret + +03004604 : + * @param txWaterMark I2C tx water mark. + * @retval true + * @retval false + */ +static inline bool IsI2cTxWaterMark(unsigned int txWaterMark) +{ + 3004604: 1101 addi sp,sp,-32 + 3004606: ce22 sw s0,28(sp) + 3004608: 1000 addi s0,sp,32 + 300460a: fea42623 sw a0,-20(s0) + return (txWaterMark <= 0xF); /* The txWaterMark value is 0 to 0xF */ + 300460e: fec42783 lw a5,-20(s0) + 3004612: 0107b793 sltiu a5,a5,16 + 3004616: 9f81 uxtb a5 +} + 3004618: 853e mv a0,a5 + 300461a: 4472 lw s0,28(sp) + 300461c: 6105 addi sp,sp,32 + 300461e: 8082 ret + +03004620 : + * @param rxWaterMark I2C rx water mark. + * @retval true + * @retval false + */ +static inline bool IsI2cRxWaterMark(unsigned int rxWaterMark) +{ + 3004620: 1101 addi sp,sp,-32 + 3004622: ce22 sw s0,28(sp) + 3004624: 1000 addi s0,sp,32 + 3004626: fea42623 sw a0,-20(s0) + return (rxWaterMark <= 0xF); /* The rxWaterMark value is 0 to 0xF */ + 300462a: fec42783 lw a5,-20(s0) + 300462e: 0107b793 sltiu a5,a5,16 + 3004632: 9f81 uxtb a5 +} + 3004634: 853e mv a0,a5 + 3004636: 4472 lw s0,28(sp) + 3004638: 6105 addi sp,sp,32 + 300463a: 8082 ret + +0300463c : + * @param sdaDelayTime The value of SDA delay time. + * @retval true + * @retval false + */ +static inline bool IsI2cSdaDelayTime(unsigned int sdaDelayTime) +{ + 300463c: 1101 addi sp,sp,-32 + 300463e: ce22 sw s0,28(sp) + 3004640: 1000 addi s0,sp,32 + 3004642: fea42623 sw a0,-20(s0) + return (sdaDelayTime <= 0x0F); /* The SDA delay time upper limit is 0x0F. */ + 3004646: fec42783 lw a5,-20(s0) + 300464a: 0107b793 sltiu a5,a5,16 + 300464e: 9f81 uxtb a5 +} + 3004650: 853e mv a0,a5 + 3004652: 4472 lw s0,28(sp) + 3004654: 6105 addi sp,sp,32 + 3004656: 8082 ret + +03004658 : + * @param handle I2C handle. + * @param clockFreq I2C work clock freq; + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType CheckAllInitParameters(I2C_Handle *handle, unsigned int clockFreq) +{ + 3004658: 1101 addi sp,sp,-32 + 300465a: ce06 sw ra,28(sp) + 300465c: cc22 sw s0,24(sp) + 300465e: 1000 addi s0,sp,32 + 3004660: fea42623 sw a0,-20(s0) + 3004664: feb42423 sw a1,-24(s0) + /* Check the configuration of basic function parameters. */ + I2C_PARAM_CHECK_WITH_RET(IsI2cFunctionMode(handle->functionMode), BASE_STATUS_ERROR); + 3004668: fec42783 lw a5,-20(s0) + 300466c: 43dc lw a5,4(a5) + 300466e: 853e mv a0,a5 + 3004670: 3d19 jal ra,3004486 + 3004672: 87aa mv a5,a0 + 3004674: 0017c793 xori a5,a5,1 + 3004678: 9f81 uxtb a5 + 300467a: cb91 beqz a5,300468e + 300467c: 09000593 li a1,144 + 3004680: 030097b7 lui a5,0x3009 + 3004684: 9fc78513 addi a0,a5,-1540 # 30089fc + 3004688: 2c31 jal ra,30048a4 + 300468a: 4785 li a5,1 + 300468c: a439 j 300489a + I2C_PARAM_CHECK_WITH_RET(IsI2cAddressMode(handle->addrMode), BASE_STATUS_ERROR); + 300468e: fec42783 lw a5,-20(s0) + 3004692: 479c lw a5,8(a5) + 3004694: 853e mv a0,a5 + 3004696: 3d05 jal ra,30044c6 + 3004698: 87aa mv a5,a0 + 300469a: 0017c793 xori a5,a5,1 + 300469e: 9f81 uxtb a5 + 30046a0: cb91 beqz a5,30046b4 + 30046a2: 09100593 li a1,145 + 30046a6: 030097b7 lui a5,0x3009 + 30046aa: 9fc78513 addi a0,a5,-1540 # 30089fc + 30046ae: 2add jal ra,30048a4 + 30046b0: 4785 li a5,1 + 30046b2: a2e5 j 300489a + I2C_PARAM_CHECK_WITH_RET(IsI2cSdaHoldTime(handle->sdaHoldTime), BASE_STATUS_ERROR); + 30046b4: fec42783 lw a5,-20(s0) + 30046b8: 4b9c lw a5,16(a5) + 30046ba: 853e mv a0,a5 + 30046bc: 3d1d jal ra,30044f2 + 30046be: 87aa mv a5,a0 + 30046c0: 0017c793 xori a5,a5,1 + 30046c4: 9f81 uxtb a5 + 30046c6: cb91 beqz a5,30046da + 30046c8: 09200593 li a1,146 + 30046cc: 030097b7 lui a5,0x3009 + 30046d0: 9fc78513 addi a0,a5,-1540 # 30089fc + 30046d4: 2ac1 jal ra,30048a4 + 30046d6: 4785 li a5,1 + 30046d8: a2c9 j 300489a + /* Check whether the I2C freq is valid. */ + I2C_PARAM_CHECK_WITH_RET(IsI2cFreq(handle->freq), BASE_STATUS_ERROR); + 30046da: fec42783 lw a5,-20(s0) + 30046de: 4bdc lw a5,20(a5) + 30046e0: 853e mv a0,a5 + 30046e2: 3de9 jal ra,30045bc + 30046e4: 87aa mv a5,a0 + 30046e6: 0017c793 xori a5,a5,1 + 30046ea: 9f81 uxtb a5 + 30046ec: cb91 beqz a5,3004700 + 30046ee: 09400593 li a1,148 + 30046f2: 030097b7 lui a5,0x3009 + 30046f6: 9fc78513 addi a0,a5,-1540 # 30089fc + 30046fa: 226d jal ra,30048a4 + 30046fc: 4785 li a5,1 + 30046fe: aa71 j 300489a + I2C_PARAM_CHECK_WITH_RET((clockFreq > 0), BASE_STATUS_ERROR); + 3004700: fe842783 lw a5,-24(s0) + 3004704: eb91 bnez a5,3004718 + 3004706: 09500593 li a1,149 + 300470a: 030097b7 lui a5,0x3009 + 300470e: 9fc78513 addi a0,a5,-1540 # 30089fc + 3004712: 2a49 jal ra,30048a4 + 3004714: 4785 li a5,1 + 3004716: a251 j 300489a + + if (handle->freq > clockFreq) { + 3004718: fec42783 lw a5,-20(s0) + 300471c: 4bdc lw a5,20(a5) + 300471e: fe842703 lw a4,-24(s0) + 3004722: 00f77463 bgeu a4,a5,300472a + return BASE_STATUS_ERROR; + 3004726: 4785 li a5,1 + 3004728: aa8d j 300489a + } + /* Check the configuration of basic function parameters. */ + I2C_PARAM_CHECK_WITH_RET(IsI2cIgnoreAckFlag(handle->ignoreAckFlag), BASE_STATUS_ERROR); + 300472a: fec42783 lw a5,-20(s0) + 300472e: 4f9c lw a5,24(a5) + 3004730: 853e mv a0,a5 + 3004732: 355d jal ra,30045d8 + 3004734: 87aa mv a5,a0 + 3004736: 0017c793 xori a5,a5,1 + 300473a: 9f81 uxtb a5 + 300473c: cb91 beqz a5,3004750 + 300473e: 09b00593 li a1,155 + 3004742: 030097b7 lui a5,0x3009 + 3004746: 9fc78513 addi a0,a5,-1540 # 30089fc + 300474a: 2aa9 jal ra,30048a4 + 300474c: 4785 li a5,1 + 300474e: a2b1 j 300489a + I2C_PARAM_CHECK_WITH_RET(IsI2cTxWaterMark(handle->txWaterMark), BASE_STATUS_ERROR); + 3004750: fec42783 lw a5,-20(s0) + 3004754: 5bdc lw a5,52(a5) + 3004756: 853e mv a0,a5 + 3004758: 3575 jal ra,3004604 + 300475a: 87aa mv a5,a0 + 300475c: 0017c793 xori a5,a5,1 + 3004760: 9f81 uxtb a5 + 3004762: cb91 beqz a5,3004776 + 3004764: 09c00593 li a1,156 + 3004768: 030097b7 lui a5,0x3009 + 300476c: 9fc78513 addi a0,a5,-1540 # 30089fc + 3004770: 2a15 jal ra,30048a4 + 3004772: 4785 li a5,1 + 3004774: a21d j 300489a + I2C_PARAM_CHECK_WITH_RET(IsI2cRxWaterMark(handle->rxWaterMark), BASE_STATUS_ERROR); + 3004776: fec42783 lw a5,-20(s0) + 300477a: 5b9c lw a5,48(a5) + 300477c: 853e mv a0,a5 + 300477e: 354d jal ra,3004620 + 3004780: 87aa mv a5,a0 + 3004782: 0017c793 xori a5,a5,1 + 3004786: 9f81 uxtb a5 + 3004788: cb91 beqz a5,300479c + 300478a: 09d00593 li a1,157 + 300478e: 030097b7 lui a5,0x3009 + 3004792: 9fc78513 addi a0,a5,-1540 # 30089fc + 3004796: 2239 jal ra,30048a4 + 3004798: 4785 li a5,1 + 300479a: a201 j 300489a + I2C_PARAM_CHECK_WITH_RET(IsI2cSpikeFilterTime(handle->handleEx.spikeFilterTime), BASE_STATUS_ERROR); + 300479c: fec42783 lw a5,-20(s0) + 30047a0: 4fbc lw a5,88(a5) + 30047a2: 853e mv a0,a5 + 30047a4: 3bf5 jal ra,30045a0 + 30047a6: 87aa mv a5,a0 + 30047a8: 0017c793 xori a5,a5,1 + 30047ac: 9f81 uxtb a5 + 30047ae: cb91 beqz a5,30047c2 + 30047b0: 09e00593 li a1,158 + 30047b4: 030097b7 lui a5,0x3009 + 30047b8: 9fc78513 addi a0,a5,-1540 # 30089fc + 30047bc: 20e5 jal ra,30048a4 + 30047be: 4785 li a5,1 + 30047c0: a8e9 j 300489a + I2C_PARAM_CHECK_WITH_RET(IsI2cSdaDelayTime(handle->handleEx.sdaDelayTime), BASE_STATUS_ERROR); + 30047c2: fec42783 lw a5,-20(s0) + 30047c6: 4ffc lw a5,92(a5) + 30047c8: 853e mv a0,a5 + 30047ca: 3d8d jal ra,300463c + 30047cc: 87aa mv a5,a0 + 30047ce: 0017c793 xori a5,a5,1 + 30047d2: 9f81 uxtb a5 + 30047d4: cb91 beqz a5,30047e8 + 30047d6: 09f00593 li a1,159 + 30047da: 030097b7 lui a5,0x3009 + 30047de: 9fc78513 addi a0,a5,-1540 # 30089fc + 30047e2: 20c9 jal ra,30048a4 + 30047e4: 4785 li a5,1 + 30047e6: a855 j 300489a + + /* Checking the own address and generalCall parameter enable when is used as slave. */ + if (handle->functionMode == I2C_MODE_SELECT_SLAVE_ONLY || handle->functionMode == I2C_MODE_SELECT_MASTER_SLAVE) { + 30047e8: fec42783 lw a5,-20(s0) + 30047ec: 43d8 lw a4,4(a5) + 30047ee: 4789 li a5,2 + 30047f0: 00f70863 beq a4,a5,3004800 + 30047f4: fec42783 lw a5,-20(s0) + 30047f8: 43d8 lw a4,4(a5) + 30047fa: 478d li a5,3 + 30047fc: 08f71e63 bne a4,a5,3004898 + I2C_PARAM_CHECK_WITH_RET(IsI2cOwnAddressOrMask(handle->slaveOwnAddress), BASE_STATUS_ERROR); + 3004800: fec42783 lw a5,-20(s0) + 3004804: 47dc lw a5,12(a5) + 3004806: 853e mv a0,a5 + 3004808: 3b15 jal ra,300453c + 300480a: 87aa mv a5,a0 + 300480c: 0017c793 xori a5,a5,1 + 3004810: 9f81 uxtb a5 + 3004812: cb91 beqz a5,3004826 + 3004814: 0a300593 li a1,163 + 3004818: 030097b7 lui a5,0x3009 + 300481c: 9fc78513 addi a0,a5,-1540 # 30089fc + 3004820: 2051 jal ra,30048a4 + 3004822: 4785 li a5,1 + 3004824: a89d j 300489a + I2C_PARAM_CHECK_WITH_RET(IsI2cGeneralCallMode(handle->generalCallMode), BASE_STATUS_ERROR); + 3004826: fec42783 lw a5,-20(s0) + 300482a: 4fdc lw a5,28(a5) + 300482c: 853e mv a0,a5 + 300482e: 31cd jal ra,3004510 + 3004830: 87aa mv a5,a0 + 3004832: 0017c793 xori a5,a5,1 + 3004836: 9f81 uxtb a5 + 3004838: cb91 beqz a5,300484c + 300483a: 0a400593 li a1,164 + 300483e: 030097b7 lui a5,0x3009 + 3004842: 9fc78513 addi a0,a5,-1540 # 30089fc + 3004846: 28b9 jal ra,30048a4 + 3004848: 4785 li a5,1 + 300484a: a881 j 300489a + I2C_PARAM_CHECK_WITH_RET(IsXMBusAddressEnable(handle->handleEx.slaveOwnXmbAddressEnable), BASE_STATUS_ERROR); + 300484c: fec42783 lw a5,-20(s0) + 3004850: 53bc lw a5,96(a5) + 3004852: 853e mv a0,a5 + 3004854: 3305 jal ra,3004574 + 3004856: 87aa mv a5,a0 + 3004858: 0017c793 xori a5,a5,1 + 300485c: 9f81 uxtb a5 + 300485e: cb91 beqz a5,3004872 + 3004860: 0a500593 li a1,165 + 3004864: 030097b7 lui a5,0x3009 + 3004868: 9fc78513 addi a0,a5,-1540 # 30089fc + 300486c: 2825 jal ra,30048a4 + 300486e: 4785 li a5,1 + 3004870: a02d j 300489a + I2C_PARAM_CHECK_WITH_RET(IsXMBusAddressOrMask(handle->handleEx.slaveOwnXmbAddress), BASE_STATUS_ERROR); + 3004872: fec42783 lw a5,-20(s0) + 3004876: 53fc lw a5,100(a5) + 3004878: 853e mv a0,a5 + 300487a: 39f9 jal ra,3004558 + 300487c: 87aa mv a5,a0 + 300487e: 0017c793 xori a5,a5,1 + 3004882: 9f81 uxtb a5 + 3004884: cb91 beqz a5,3004898 + 3004886: 0a600593 li a1,166 + 300488a: 030097b7 lui a5,0x3009 + 300488e: 9fc78513 addi a0,a5,-1540 # 30089fc + 3004892: 2809 jal ra,30048a4 + 3004894: 4785 li a5,1 + 3004896: a011 j 300489a + } + return BASE_STATUS_OK; + 3004898: 4781 li a5,0 +} + 300489a: 853e mv a0,a5 + 300489c: 40f2 lw ra,28(sp) + 300489e: 4462 lw s0,24(sp) + 30048a0: 6105 addi sp,sp,32 + 30048a2: 8082 ret + +030048a4 : + 30048a4: 965fc06f j 3001208 + +030048a8 : + * @param handle I2C handle. + * @param devAddr Slave device address + * @retval None. + */ +static void SetSlaveDevAddr(I2C_Handle *handle, const unsigned int devAddr) +{ + 30048a8: 7179 addi sp,sp,-48 + 30048aa: d622 sw s0,44(sp) + 30048ac: 1800 addi s0,sp,48 + 30048ae: fca42e23 sw a0,-36(s0) + 30048b2: fcb42c23 sw a1,-40(s0) + unsigned int addr; + + if (handle->addrMode == I2C_10_BITS) { + 30048b6: fdc42783 lw a5,-36(s0) + 30048ba: 4798 lw a4,8(a5) + 30048bc: 4785 li a5,1 + 30048be: 02f71663 bne a4,a5,30048ea + /* The upper 16 bits are the read operation address, and the lower 16 bits are the write operation address. */ + addr = (((devAddr << 16) & I2C_10BIT_SLAVE_READ_ADDR_MASK) | I2C_10BIT_SLAVE_READ_OPT_MASK) | + 30048c2: fd842783 lw a5,-40(s0) + 30048c6: 01079713 slli a4,a5,0x10 + 30048ca: feff07b7 lui a5,0xfeff0 + 30048ce: 8f7d and a4,a4,a5 + (devAddr & I2C_10BIT_SLAVE_WRITE_ADDR_MASK); + 30048d0: fd842683 lw a3,-40(s0) + 30048d4: 67c1 lui a5,0x10 + 30048d6: eff78793 addi a5,a5,-257 # feff + 30048da: 8ff5 and a5,a5,a3 + addr = (((devAddr << 16) & I2C_10BIT_SLAVE_READ_ADDR_MASK) | I2C_10BIT_SLAVE_READ_OPT_MASK) | + 30048dc: 8f5d or a4,a4,a5 + 30048de: 010007b7 lui a5,0x1000 + 30048e2: 8fd9 or a5,a5,a4 + 30048e4: fef42623 sw a5,-20(s0) + 30048e8: a00d j 300490a + } else { + /* The upper 16 bits are the read operation address, and the lower 16 bits are the write operation address. */ + addr = (((devAddr << 16) & I2C_7BIT_SLAVE_READ_ADDR_MASK) | I2C_7BIT_SLAVE_READ_OPT_MASK) | + 30048ea: fd842783 lw a5,-40(s0) + 30048ee: 01079713 slli a4,a5,0x10 + 30048f2: 00fe07b7 lui a5,0xfe0 + 30048f6: 8f7d and a4,a4,a5 + (devAddr & I2C_7BIT_SLAVE_WRITE_ADDR_MASK); + 30048f8: fd842783 lw a5,-40(s0) + 30048fc: 0fe7f793 andi a5,a5,254 + addr = (((devAddr << 16) & I2C_7BIT_SLAVE_READ_ADDR_MASK) | I2C_7BIT_SLAVE_READ_OPT_MASK) | + 3004900: 8f5d or a4,a4,a5 + 3004902: 67c1 lui a5,0x10 + 3004904: 8fd9 or a5,a5,a4 + 3004906: fef42623 sw a5,-20(s0) + } + + if (handle->baseAddress == I2C0) { + 300490a: fdc42783 lw a5,-36(s0) + 300490e: 4398 lw a4,0(a5) + 3004910: 141007b7 lui a5,0x14100 + 3004914: 00f71a63 bne a4,a5,3004928 + g_internalConfigParam[I2C_INTERFACE_INDEX_0].slaveAddress = addr; + 3004918: 040007b7 lui a5,0x4000 + 300491c: 49c78793 addi a5,a5,1180 # 400049c + 3004920: fec42703 lw a4,-20(s0) + 3004924: c3d8 sw a4,4(a5) + } else if (handle->baseAddress == I2C1) { + g_internalConfigParam[I2C_INTERFACE_INDEX_1].slaveAddress = addr; + } +} + 3004926: a839 j 3004944 + } else if (handle->baseAddress == I2C1) { + 3004928: fdc42783 lw a5,-36(s0) + 300492c: 4398 lw a4,0(a5) + 300492e: 141017b7 lui a5,0x14101 + 3004932: 00f71963 bne a4,a5,3004944 + g_internalConfigParam[I2C_INTERFACE_INDEX_1].slaveAddress = addr; + 3004936: 040007b7 lui a5,0x4000 + 300493a: 49c78793 addi a5,a5,1180 # 400049c + 300493e: fec42703 lw a4,-20(s0) + 3004942: cb98 sw a4,16(a5) +} + 3004944: 0001 nop + 3004946: 5432 lw s0,44(sp) + 3004948: 6145 addi sp,sp,48 + 300494a: 8082 ret + +0300494c : + * @brief I2C Bus clear. + * @param handle I2C handle. + * @retval None. + */ +static void I2cBusClear(I2C_Handle *handle) +{ + 300494c: 7179 addi sp,sp,-48 + 300494e: d606 sw ra,44(sp) + 3004950: d422 sw s0,40(sp) + 3004952: 1800 addi s0,sp,48 + 3004954: fca42e23 sw a0,-36(s0) + handle->state = I2C_STATE_READY; + 3004958: fdc42783 lw a5,-36(s0) + 300495c: 4705 li a4,1 + 300495e: c3f8 sw a4,68(a5) + handle->baseAddress->I2C_MODE.BIT.mst_slv_function = I2C_STATE_RESET; + 3004960: fdc42783 lw a5,-36(s0) + 3004964: 4398 lw a4,0(a5) + 3004966: 431c lw a5,0(a4) + 3004968: 9bf1 andi a5,a5,-4 + 300496a: c31c sw a5,0(a4) + /* Clears interrupts and disables interrupt reporting to + facilitate switching between different working modes. */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + 300496c: fdc42783 lw a5,-36(s0) + 3004970: 439c lw a5,0(a5) + 3004972: 0e07a223 sw zero,228(a5) + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + 3004976: fdc42783 lw a5,-36(s0) + 300497a: 439c lw a5,0(a5) + 300497c: 01000737 lui a4,0x1000 + 3004980: 177d addi a4,a4,-1 # ffffff + 3004982: 0ee7a023 sw a4,224(a5) + + /* Set the SCL and SDA pins of the I2C to GPIO mode. */ + handle->baseAddress->I2C_CTRL2.BIT.gpio_mode = BASE_CFG_ENABLE; + 3004986: fdc42783 lw a5,-36(s0) + 300498a: 4398 lw a4,0(a5) + 300498c: 0d472783 lw a5,212(a4) + 3004990: 1007e793 ori a5,a5,256 + 3004994: 0cf72a23 sw a5,212(a4) + handle->baseAddress->I2C_CTRL2.BIT.force_scl = BASE_CFG_ENABLE; + 3004998: fdc42783 lw a5,-36(s0) + 300499c: 4398 lw a4,0(a5) + 300499e: 0d472783 lw a5,212(a4) + 30049a2: 0107e793 ori a5,a5,16 + 30049a6: 0cf72a23 sw a5,212(a4) + handle->baseAddress->I2C_CTRL2.BIT.force_sda = BASE_CFG_ENABLE; + 30049aa: fdc42783 lw a5,-36(s0) + 30049ae: 4398 lw a4,0(a5) + 30049b0: 0d472783 lw a5,212(a4) + 30049b4: 0017e793 ori a5,a5,1 + 30049b8: 0cf72a23 sw a5,212(a4) + /* The device that controls the bus to be pulled down needs to release the bus within the 9 clocks. */ + for (unsigned int index = 0; index < 9; index++) { + 30049bc: fe042623 sw zero,-20(s0) + 30049c0: a099 j 3004a06 + handle->baseAddress->I2C_CTRL2.BIT.force_scl = BASE_CFG_UNSET; + 30049c2: fdc42783 lw a5,-36(s0) + 30049c6: 4398 lw a4,0(a5) + 30049c8: 0d472783 lw a5,212(a4) + 30049cc: 9bbd andi a5,a5,-17 + 30049ce: 0cf72a23 sw a5,212(a4) + BASE_FUNC_DELAY_US(5); /* The I2C timing is required. The delay is about 5 μs. */ + 30049d2: 000f47b7 lui a5,0xf4 + 30049d6: 24078593 addi a1,a5,576 # f4240 + 30049da: 4515 li a0,5 + 30049dc: 204d jal ra,3004a7e + handle->baseAddress->I2C_CTRL2.BIT.force_scl = BASE_CFG_SET; + 30049de: fdc42783 lw a5,-36(s0) + 30049e2: 4398 lw a4,0(a5) + 30049e4: 0d472783 lw a5,212(a4) + 30049e8: 0107e793 ori a5,a5,16 + 30049ec: 0cf72a23 sw a5,212(a4) + BASE_FUNC_DELAY_US(5); /* The I2C timing is required. The delay is about 5 μs. */ + 30049f0: 000f47b7 lui a5,0xf4 + 30049f4: 24078593 addi a1,a5,576 # f4240 + 30049f8: 4515 li a0,5 + 30049fa: 2051 jal ra,3004a7e + for (unsigned int index = 0; index < 9; index++) { + 30049fc: fec42783 lw a5,-20(s0) + 3004a00: 0785 addi a5,a5,1 + 3004a02: fef42623 sw a5,-20(s0) + 3004a06: fec42703 lw a4,-20(s0) + 3004a0a: 47a1 li a5,8 + 3004a0c: fae7fbe3 bgeu a5,a4,30049c2 + } + handle->baseAddress->I2C_CTRL2.BIT.force_scl = BASE_CFG_ENABLE; + 3004a10: fdc42783 lw a5,-36(s0) + 3004a14: 4398 lw a4,0(a5) + 3004a16: 0d472783 lw a5,212(a4) + 3004a1a: 0107e793 ori a5,a5,16 + 3004a1e: 0cf72a23 sw a5,212(a4) + handle->baseAddress->I2C_CTRL2.BIT.force_sda = BASE_CFG_ENABLE; + 3004a22: fdc42783 lw a5,-36(s0) + 3004a26: 4398 lw a4,0(a5) + 3004a28: 0d472783 lw a5,212(a4) + 3004a2c: 0017e793 ori a5,a5,1 + 3004a30: 0cf72a23 sw a5,212(a4) + /* I2C start */ + handle->baseAddress->I2C_CTRL2.BIT.force_sda = BASE_CFG_UNSET; + 3004a34: fdc42783 lw a5,-36(s0) + 3004a38: 4398 lw a4,0(a5) + 3004a3a: 0d472783 lw a5,212(a4) + 3004a3e: 9bf9 andi a5,a5,-2 + 3004a40: 0cf72a23 sw a5,212(a4) + BASE_FUNC_DELAY_US(10); /* The I2C timing is required. The delay is about 10 μs. */ + 3004a44: 000f47b7 lui a5,0xf4 + 3004a48: 24078593 addi a1,a5,576 # f4240 + 3004a4c: 4529 li a0,10 + 3004a4e: 2805 jal ra,3004a7e + /* I2C stop */ + handle->baseAddress->I2C_CTRL2.BIT.force_sda = BASE_CFG_SET; + 3004a50: fdc42783 lw a5,-36(s0) + 3004a54: 4398 lw a4,0(a5) + 3004a56: 0d472783 lw a5,212(a4) + 3004a5a: 0017e793 ori a5,a5,1 + 3004a5e: 0cf72a23 sw a5,212(a4) + handle->baseAddress->I2C_CTRL2.BIT.gpio_mode = BASE_CFG_DISABLE; /* Exit the I2C GPIO mode. */ + 3004a62: fdc42783 lw a5,-36(s0) + 3004a66: 4398 lw a4,0(a5) + 3004a68: 0d472783 lw a5,212(a4) + 3004a6c: eff7f793 andi a5,a5,-257 + 3004a70: 0cf72a23 sw a5,212(a4) +} + 3004a74: 0001 nop + 3004a76: 50b2 lw ra,44(sp) + 3004a78: 5422 lw s0,40(sp) + 3004a7a: 6145 addi sp,sp,48 + 3004a7c: 8082 ret + +03004a7e : + 3004a7e: 87ffc06f j 30012fc + +03004a82 : + * @brief Setting Error Handling. + * @param handle I2C handle. + * @retval None. + */ +static void SetErrorHandling(I2C_Handle *handle) +{ + 3004a82: 1101 addi sp,sp,-32 + 3004a84: ce06 sw ra,28(sp) + 3004a86: cc22 sw s0,24(sp) + 3004a88: 1000 addi s0,sp,32 + 3004a8a: fea42623 sw a0,-20(s0) + /* If the low level times out, the I2C bus is cleared and the bus is expected to be released. */ + if (handle->baseAddress->I2C_INTR_RAW.BIT.scl_low_timeout_raw == BASE_CFG_ENABLE) { + 3004a8e: fec42783 lw a5,-20(s0) + 3004a92: 439c lw a5,0(a5) + 3004a94: 0e07a783 lw a5,224(a5) + 3004a98: 83b5 srli a5,a5,0xd + 3004a9a: 8b85 andi a5,a5,1 + 3004a9c: 0ff7f713 andi a4,a5,255 + 3004aa0: 4785 li a5,1 + 3004aa2: 00f71e63 bne a4,a5,3004abe + I2cBusClear(handle); + 3004aa6: fec42503 lw a0,-20(s0) + 3004aaa: 354d jal ra,300494c + handle->baseAddress->I2C_INTR_RAW.BIT.scl_low_timeout_raw = BASE_CFG_ENABLE; + 3004aac: fec42783 lw a5,-20(s0) + 3004ab0: 4398 lw a4,0(a5) + 3004ab2: 0e072783 lw a5,224(a4) + 3004ab6: 6689 lui a3,0x2 + 3004ab8: 8fd5 or a5,a5,a3 + 3004aba: 0ef72023 sw a5,224(a4) + } + + if (handle->errorCode != BASE_STATUS_OK && handle->userCallBack.ErrorCallback != NULL) { + 3004abe: fec42783 lw a5,-20(s0) + 3004ac2: 47bc lw a5,72(a5) + 3004ac4: cb99 beqz a5,3004ada + 3004ac6: fec42783 lw a5,-20(s0) + 3004aca: 4bfc lw a5,84(a5) + 3004acc: c799 beqz a5,3004ada + handle->userCallBack.ErrorCallback(handle); + 3004ace: fec42783 lw a5,-20(s0) + 3004ad2: 4bfc lw a5,84(a5) + 3004ad4: fec42503 lw a0,-20(s0) + 3004ad8: 9782 jalr a5 + } + /* Clears interrupts and disables interrupt reporting to + facilitate switching between different working modes. */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + 3004ada: fec42783 lw a5,-20(s0) + 3004ade: 439c lw a5,0(a5) + 3004ae0: 0e07a223 sw zero,228(a5) + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + 3004ae4: fec42783 lw a5,-20(s0) + 3004ae8: 439c lw a5,0(a5) + 3004aea: 01000737 lui a4,0x1000 + 3004aee: 177d addi a4,a4,-1 # ffffff + 3004af0: 0ee7a023 sw a4,224(a5) + + handle->state = I2C_STATE_READY; + 3004af4: fec42783 lw a5,-20(s0) + 3004af8: 4705 li a4,1 + 3004afa: c3f8 sw a4,68(a5) +} + 3004afc: 0001 nop + 3004afe: 40f2 lw ra,28(sp) + 3004b00: 4462 lw s0,24(sp) + 3004b02: 6105 addi sp,sp,32 + 3004b04: 8082 ret + +03004b06 : + * @param checkItem The item to be checked. + * @param opt Read or write flag. + * @retval false, item is not ready. true, item is ready. + */ +static unsigned int CheckItemStatus(I2C_Handle *handle, unsigned int checkItem, unsigned int opt) +{ + 3004b06: 7179 addi sp,sp,-48 + 3004b08: d622 sw s0,44(sp) + 3004b0a: 1800 addi s0,sp,48 + 3004b0c: fca42e23 sw a0,-36(s0) + 3004b10: fcb42c23 sw a1,-40(s0) + 3004b14: fcc42a23 sw a2,-44(s0) + unsigned int ret = 0; + 3004b18: fe042623 sw zero,-20(s0) + unsigned int tempStatusValue = 0; + 3004b1c: fe042423 sw zero,-24(s0) + switch (checkItem) { + 3004b20: fd842703 lw a4,-40(s0) + 3004b24: 4791 li a5,4 + 3004b26: 0ce7e263 bltu a5,a4,3004bea + 3004b2a: fd842783 lw a5,-40(s0) + 3004b2e: 00279713 slli a4,a5,0x2 + 3004b32: 030097b7 lui a5,0x3009 + 3004b36: a1878793 addi a5,a5,-1512 # 3008a18 + 3004b3a: 97ba add a5,a5,a4 + 3004b3c: 439c lw a5,0(a5) + 3004b3e: 8782 jr a5 + case COMMAND_ALL_DONE: + /* The 0x1200 is the bit of mst_cmd_done_raw and stop_det_raw. */ + tempStatusValue = (handle->baseAddress->I2C_INTR_RAW.reg & 0x1200); /* Check the I2C is all command done. */ + 3004b40: fdc42783 lw a5,-36(s0) + 3004b44: 439c lw a5,0(a5) + 3004b46: 0e07a703 lw a4,224(a5) + 3004b4a: 6785 lui a5,0x1 + 3004b4c: 20078793 addi a5,a5,512 # 1200 + 3004b50: 8ff9 and a5,a5,a4 + 3004b52: fef42423 sw a5,-24(s0) + ret = tempStatusValue; + 3004b56: fe842783 lw a5,-24(s0) + 3004b5a: fef42623 sw a5,-20(s0) + break; + 3004b5e: a079 j 3004bec + case I2C_BUS_IS_FREE: + /* The I2C bus is free. */ + ret = handle->baseAddress->I2C_FSM_STAT.BIT.i2c_bus_free; + 3004b60: fdc42783 lw a5,-36(s0) + 3004b64: 439c lw a5,0(a5) + 3004b66: 0dc7a783 lw a5,220(a5) + 3004b6a: 83f9 srli a5,a5,0x1e + 3004b6c: 8b85 andi a5,a5,1 + 3004b6e: 9f81 uxtb a5 + 3004b70: fef42623 sw a5,-20(s0) + break; + 3004b74: a8a5 j 3004bec + case SLAVE_ADDRESS_MATCH: + /* Slave servers are matched */ + tempStatusValue = (handle->baseAddress->I2C_RX_ADDR.BIT.rx_rw == opt) ? 1 : 0; + 3004b76: fdc42783 lw a5,-36(s0) + 3004b7a: 439c lw a5,0(a5) + 3004b7c: 4f9c lw a5,24(a5) + 3004b7e: 8b85 andi a5,a5,1 + 3004b80: 9f81 uxtb a5 + 3004b82: 873e mv a4,a5 + 3004b84: fd442783 lw a5,-44(s0) + 3004b88: 8f99 sub a5,a5,a4 + 3004b8a: 0017b793 seqz a5,a5 + 3004b8e: 9f81 uxtb a5 + 3004b90: fef42423 sw a5,-24(s0) + tempStatusValue |= handle->baseAddress->I2C_INTR_RAW.BIT.slv_addr_match_raw; + 3004b94: fdc42783 lw a5,-36(s0) + 3004b98: 439c lw a5,0(a5) + 3004b9a: 0e07a783 lw a5,224(a5) + 3004b9e: 83d5 srli a5,a5,0x15 + 3004ba0: 8b85 andi a5,a5,1 + 3004ba2: 9f81 uxtb a5 + 3004ba4: 873e mv a4,a5 + 3004ba6: fe842783 lw a5,-24(s0) + 3004baa: 8fd9 or a5,a5,a4 + 3004bac: fef42423 sw a5,-24(s0) + ret = tempStatusValue; + 3004bb0: fe842783 lw a5,-24(s0) + 3004bb4: fef42623 sw a5,-20(s0) + break; + 3004bb8: a815 j 3004bec + case TX_FIFO_NOT_FULL: + /* Tx fifo is not full. */ + ret = ((handle->baseAddress->I2C_FIFO_STAT.BIT.tx_fifo_vld_num < I2C_MAX_FIFO_SIZE)) ? 1 : 0; + 3004bba: fdc42783 lw a5,-36(s0) + 3004bbe: 439c lw a5,0(a5) + 3004bc0: 0d87a783 lw a5,216(a5) + 3004bc4: 83a1 srli a5,a5,0x8 + 3004bc6: 8bfd andi a5,a5,31 + 3004bc8: 9f81 uxtb a5 + 3004bca: 0107b793 sltiu a5,a5,16 + 3004bce: 9f81 uxtb a5 + 3004bd0: fef42623 sw a5,-20(s0) + break; + 3004bd4: a821 j 3004bec + case RX_FIFO_NOT_EMPTY: + /* Rx fifo is not empty. */ + ret = handle->baseAddress->I2C_FIFO_STAT.BIT.rx_fifo_vld_num; + 3004bd6: fdc42783 lw a5,-36(s0) + 3004bda: 439c lw a5,0(a5) + 3004bdc: 0d87a783 lw a5,216(a5) + 3004be0: 8bfd andi a5,a5,31 + 3004be2: 9f81 uxtb a5 + 3004be4: fef42623 sw a5,-20(s0) + break; + 3004be8: a011 j 3004bec + default: + break; + 3004bea: 0001 nop + } + return ret; + 3004bec: fec42783 lw a5,-20(s0) +} + 3004bf0: 853e mv a0,a5 + 3004bf2: 5432 lw s0,44(sp) + 3004bf4: 6145 addi sp,sp,48 + 3004bf6: 8082 ret + +03004bf8 : + * @param checkItem The item to be checked. + * @param opt Read or write flag. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType WaitStatusReady(I2C_Handle *handle, unsigned int checkItem, unsigned int opt) +{ + 3004bf8: 7139 addi sp,sp,-64 + 3004bfa: 03010293 addi t0,sp,48 + 3004bfe: 0062928b stmia {ra,s0,s2-s3},(t0) + 3004c02: 0080 addi s0,sp,64 + 3004c04: fca42623 sw a0,-52(s0) + 3004c08: fcb42423 sw a1,-56(s0) + 3004c0c: fcc42223 sw a2,-60(s0) + unsigned int preTick = DCL_SYSTICK_GetTick(); + 3004c10: e0efc0ef jal ra,300121e + 3004c14: fea42623 sw a0,-20(s0) + unsigned int curTick; + unsigned long long delta = 0; + 3004c18: 4781 li a5,0 + 3004c1a: 4801 li a6,0 + 3004c1c: fef42023 sw a5,-32(s0) + 3004c20: ff042223 sw a6,-28(s0) + unsigned long long targetDelta = HAL_CRG_GetIpFreq(SYSTICK_BASE) / I2C_TICK_MS_DIV * handle->timeout; + 3004c24: 14380537 lui a0,0x14380 + 3004c28: 943fd0ef jal ra,300256a + 3004c2c: 872a mv a4,a0 + 3004c2e: 3e800793 li a5,1000 + 3004c32: 02f75733 divu a4,a4,a5 + 3004c36: fcc42783 lw a5,-52(s0) + 3004c3a: 57dc lw a5,44(a5) + 3004c3c: 02f707b3 mul a5,a4,a5 + 3004c40: fcf42c23 sw a5,-40(s0) + 3004c44: fc042e23 sw zero,-36(s0) + + while (true) { + if (handle->baseAddress->I2C_INTR_RAW.reg & I2C_ERROR_BIT_MASK) { + 3004c48: fcc42783 lw a5,-52(s0) + 3004c4c: 439c lw a5,0(a5) + 3004c4e: 0e07a703 lw a4,224(a5) + 3004c52: 001017b7 lui a5,0x101 + 3004c56: 80178793 addi a5,a5,-2047 # 100801 + 3004c5a: 8ff9 and a5,a5,a4 + 3004c5c: c791 beqz a5,3004c68 + SetErrorHandling(handle); + 3004c5e: fcc42503 lw a0,-52(s0) + 3004c62: 3505 jal ra,3004a82 + return BASE_STATUS_ERROR; + 3004c64: 4785 li a5,1 + 3004c66: a0d1 j 3004d2a + } + + /* Check the status of the item is ready. */ + if (CheckItemStatus(handle, checkItem, opt)) { + 3004c68: fc442603 lw a2,-60(s0) + 3004c6c: fc842583 lw a1,-56(s0) + 3004c70: fcc42503 lw a0,-52(s0) + 3004c74: 3d49 jal ra,3004b06 + 3004c76: 87aa mv a5,a0 + 3004c78: c395 beqz a5,3004c9c + if (checkItem == SLAVE_ADDRESS_MATCH) { + 3004c7a: fc842703 lw a4,-56(s0) + 3004c7e: 4789 li a5,2 + 3004c80: 00f71c63 bne a4,a5,3004c98 + /* Clear slave address match raw interrupt */ + handle->baseAddress->I2C_INTR_RAW.BIT.slv_addr_match_raw = BASE_CFG_SET; + 3004c84: fcc42783 lw a5,-52(s0) + 3004c88: 4398 lw a4,0(a5) + 3004c8a: 0e072783 lw a5,224(a4) + 3004c8e: 002006b7 lui a3,0x200 + 3004c92: 8fd5 or a5,a5,a3 + 3004c94: 0ef72023 sw a5,224(a4) + } + return BASE_STATUS_OK; + 3004c98: 4781 li a5,0 + 3004c9a: a841 j 3004d2a + } + + curTick = DCL_SYSTICK_GetTick(); + 3004c9c: d82fc0ef jal ra,300121e + 3004ca0: fca42a23 sw a0,-44(s0) + delta += curTick > preTick ? curTick - preTick : SYSTICK_MAX_VALUE - preTick + curTick; + 3004ca4: fd442703 lw a4,-44(s0) + 3004ca8: fec42783 lw a5,-20(s0) + 3004cac: 00e7fb63 bgeu a5,a4,3004cc2 + 3004cb0: fd442703 lw a4,-44(s0) + 3004cb4: fec42783 lw a5,-20(s0) + 3004cb8: 40f707b3 sub a5,a4,a5 + 3004cbc: 893e mv s2,a5 + 3004cbe: 4981 li s3,0 + 3004cc0: a811 j 3004cd4 + 3004cc2: fd442703 lw a4,-44(s0) + 3004cc6: fec42783 lw a5,-20(s0) + 3004cca: 40f707b3 sub a5,a4,a5 + 3004cce: 17fd addi a5,a5,-1 + 3004cd0: 893e mv s2,a5 + 3004cd2: 4981 li s3,0 + 3004cd4: fe042683 lw a3,-32(s0) + 3004cd8: fe442703 lw a4,-28(s0) + 3004cdc: 012687b3 add a5,a3,s2 + 3004ce0: 863e mv a2,a5 + 3004ce2: 00d63633 sltu a2,a2,a3 + 3004ce6: 01370833 add a6,a4,s3 + 3004cea: 01060733 add a4,a2,a6 + 3004cee: 883a mv a6,a4 + 3004cf0: fef42023 sw a5,-32(s0) + 3004cf4: ff042223 sw a6,-28(s0) + if (delta >= targetDelta) { /* Check timeout. */ + 3004cf8: fdc42703 lw a4,-36(s0) + 3004cfc: fe442783 lw a5,-28(s0) + 3004d00: 00e7ee63 bltu a5,a4,3004d1c + 3004d04: fdc42703 lw a4,-36(s0) + 3004d08: fe442783 lw a5,-28(s0) + 3004d0c: 00f71d63 bne a4,a5,3004d26 + 3004d10: fd842703 lw a4,-40(s0) + 3004d14: fe042783 lw a5,-32(s0) + 3004d18: 00e7f763 bgeu a5,a4,3004d26 + break; + } + preTick = curTick; + 3004d1c: fd442783 lw a5,-44(s0) + 3004d20: fef42623 sw a5,-20(s0) + if (handle->baseAddress->I2C_INTR_RAW.reg & I2C_ERROR_BIT_MASK) { + 3004d24: b715 j 3004c48 + break; + 3004d26: 0001 nop + } + return BASE_STATUS_TIMEOUT; + 3004d28: 478d li a5,3 +} + 3004d2a: 853e mv a0,a5 + 3004d2c: 03010293 addi t0,sp,48 + 3004d30: 0062828b ldmia {ra,s0,s2-s3},(t0) + 3004d34: 6121 addi sp,sp,64 + 3004d36: 8082 ret + +03004d38 : + * @param cmd Operation commands. + * @param data Sending data. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType SetTxFIFODataAndCmd(I2C_Handle *handle, I2C_CmdType cmd, unsigned char data) +{ + 3004d38: 7179 addi sp,sp,-48 + 3004d3a: d606 sw ra,44(sp) + 3004d3c: d422 sw s0,40(sp) + 3004d3e: 1800 addi s0,sp,48 + 3004d40: fca42e23 sw a0,-36(s0) + 3004d44: fcb42c23 sw a1,-40(s0) + 3004d48: 87b2 mv a5,a2 + 3004d4a: fcf40ba3 sb a5,-41(s0) + BASE_StatusType ret; + unsigned int temp; + + ret = WaitStatusReady(handle, TX_FIFO_NOT_FULL, I2C_OPERATION_WRITE); + 3004d4e: 4601 li a2,0 + 3004d50: 458d li a1,3 + 3004d52: fdc42503 lw a0,-36(s0) + 3004d56: 354d jal ra,3004bf8 + 3004d58: fea42623 sw a0,-20(s0) + if (ret != BASE_STATUS_OK) { + 3004d5c: fec42783 lw a5,-20(s0) + 3004d60: c781 beqz a5,3004d68 + return ret; + 3004d62: fec42783 lw a5,-20(s0) + 3004d66: a80d j 3004d98 + } + /* The 8 to 11 bits are the Timing Commands, and the 0 to 7 bits are the write data. */ + temp = (((unsigned int)cmd << I2C_TXFIFO_CMD_POS) & I2C_TXFIFO_CMD_MASK); + 3004d68: fd842783 lw a5,-40(s0) + 3004d6c: 00879713 slli a4,a5,0x8 + 3004d70: 6785 lui a5,0x1 + 3004d72: f0078793 addi a5,a5,-256 # f00 + 3004d76: 8ff9 and a5,a5,a4 + 3004d78: fef42423 sw a5,-24(s0) + temp |= (((unsigned int)data << I2C_TXFIFO_WDATA_POS) & I2C_TXFIFO_WDATA_MASK); + 3004d7c: fd744783 lbu a5,-41(s0) + 3004d80: fe842703 lw a4,-24(s0) + 3004d84: 8fd9 or a5,a5,a4 + 3004d86: fef42423 sw a5,-24(s0) + handle->baseAddress->I2C_TX_FIFO.reg = temp; /* Sets the data and commands to be sent. */ + 3004d8a: fdc42783 lw a5,-36(s0) + 3004d8e: 439c lw a5,0(a5) + 3004d90: fe842703 lw a4,-24(s0) + 3004d94: d398 sw a4,32(a5) + return BASE_STATUS_OK; + 3004d96: 4781 li a5,0 +} + 3004d98: 853e mv a0,a5 + 3004d9a: 50b2 lw ra,44(sp) + 3004d9c: 5422 lw s0,40(sp) + 3004d9e: 6145 addi sp,sp,48 + 3004da0: 8082 ret + +03004da2 : + * @param handle I2C handle. + * @param index The number of I2C. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType SendSlaveAddressWriteCmd(I2C_Handle *handle, unsigned int index) +{ + 3004da2: 7179 addi sp,sp,-48 + 3004da4: d606 sw ra,44(sp) + 3004da6: d422 sw s0,40(sp) + 3004da8: 1800 addi s0,sp,48 + 3004daa: fca42e23 sw a0,-36(s0) + 3004dae: fcb42c23 sw a1,-40(s0) + BASE_StatusType ret; + unsigned char addr; + /* Write slave address */ + if (handle->addrMode == I2C_10_BITS) { /* 10bit address Configuration */ + 3004db2: fdc42783 lw a5,-36(s0) + 3004db6: 4798 lw a4,8(a5) + 3004db8: 4785 li a5,1 + 3004dba: 0af71c63 bne a4,a5,3004e72 + if (handle->transferCount == 0) { + 3004dbe: fdc42783 lw a5,-36(s0) + 3004dc2: 579c lw a5,40(a5) + 3004dc4: ebb5 bnez a5,3004e38 + /* The first address of a 10-bit address configuration */ + addr = (unsigned char)((g_internalConfigParam[index].slaveAddress >> I2C_SLAVE_WRITE_ADDR_POS) & + 3004dc6: 040007b7 lui a5,0x4000 + 3004dca: 49c78713 addi a4,a5,1180 # 400049c + 3004dce: fd842683 lw a3,-40(s0) + 3004dd2: 47b1 li a5,12 + 3004dd4: 02f687b3 mul a5,a3,a5 + 3004dd8: 97ba add a5,a5,a4 + 3004dda: 43dc lw a5,4(a5) + 3004ddc: 83a1 srli a5,a5,0x8 + 3004dde: fef407a3 sb a5,-17(s0) + I2C_SLAVE_ADDR_MASK); + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_TD_RACK_S_RD_TACK, addr); + 3004de2: fef44783 lbu a5,-17(s0) + 3004de6: 863e mv a2,a5 + 3004de8: 4589 li a1,2 + 3004dea: fdc42503 lw a0,-36(s0) + 3004dee: 37a9 jal ra,3004d38 + 3004df0: fea42423 sw a0,-24(s0) + if (ret != BASE_STATUS_OK) { + 3004df4: fe842783 lw a5,-24(s0) + 3004df8: c781 beqz a5,3004e00 + return ret; + 3004dfa: fe842783 lw a5,-24(s0) + 3004dfe: a07d j 3004eac + } + /* The second address of the 10-bit address configuration */ + addr = (unsigned char)(g_internalConfigParam[index].slaveAddress & I2C_SLAVE_ADDR_MASK); + 3004e00: 040007b7 lui a5,0x4000 + 3004e04: 49c78713 addi a4,a5,1180 # 400049c + 3004e08: fd842683 lw a3,-40(s0) + 3004e0c: 47b1 li a5,12 + 3004e0e: 02f687b3 mul a5,a3,a5 + 3004e12: 97ba add a5,a5,a4 + 3004e14: 43dc lw a5,4(a5) + 3004e16: fef407a3 sb a5,-17(s0) + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_TD_RACK_S_RD_TACK, addr); + 3004e1a: fef44783 lbu a5,-17(s0) + 3004e1e: 863e mv a2,a5 + 3004e20: 4589 li a1,2 + 3004e22: fdc42503 lw a0,-36(s0) + 3004e26: 3f09 jal ra,3004d38 + 3004e28: fea42423 sw a0,-24(s0) + if (ret != BASE_STATUS_OK) { + 3004e2c: fe842783 lw a5,-24(s0) + 3004e30: cfad beqz a5,3004eaa + return ret; + 3004e32: fe842783 lw a5,-24(s0) + 3004e36: a89d j 3004eac + } + } else { + addr = (unsigned char)((g_internalConfigParam[index].slaveAddress >> I2C_SLAVE_WRITE_ADDR_POS) & + 3004e38: 040007b7 lui a5,0x4000 + 3004e3c: 49c78713 addi a4,a5,1180 # 400049c + 3004e40: fd842683 lw a3,-40(s0) + 3004e44: 47b1 li a5,12 + 3004e46: 02f687b3 mul a5,a3,a5 + 3004e4a: 97ba add a5,a5,a4 + 3004e4c: 43dc lw a5,4(a5) + 3004e4e: 83a1 srli a5,a5,0x8 + 3004e50: fef407a3 sb a5,-17(s0) + I2C_SLAVE_ADDR_MASK); + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_TD_RACK_S_RD_TACK, addr); + 3004e54: fef44783 lbu a5,-17(s0) + 3004e58: 863e mv a2,a5 + 3004e5a: 4589 li a1,2 + 3004e5c: fdc42503 lw a0,-36(s0) + 3004e60: 3de1 jal ra,3004d38 + 3004e62: fea42423 sw a0,-24(s0) + if (ret != BASE_STATUS_OK) { + 3004e66: fe842783 lw a5,-24(s0) + 3004e6a: c3a1 beqz a5,3004eaa + return ret; + 3004e6c: fe842783 lw a5,-24(s0) + 3004e70: a835 j 3004eac + } + } + } else { /* 7bit address Configuration */ + addr = (unsigned char)(g_internalConfigParam[index].slaveAddress & I2C_SLAVE_ADDR_MASK); + 3004e72: 040007b7 lui a5,0x4000 + 3004e76: 49c78713 addi a4,a5,1180 # 400049c + 3004e7a: fd842683 lw a3,-40(s0) + 3004e7e: 47b1 li a5,12 + 3004e80: 02f687b3 mul a5,a3,a5 + 3004e84: 97ba add a5,a5,a4 + 3004e86: 43dc lw a5,4(a5) + 3004e88: fef407a3 sb a5,-17(s0) + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_TD_RACK_S_RD_TACK, addr); + 3004e8c: fef44783 lbu a5,-17(s0) + 3004e90: 863e mv a2,a5 + 3004e92: 4589 li a1,2 + 3004e94: fdc42503 lw a0,-36(s0) + 3004e98: 3545 jal ra,3004d38 + 3004e9a: fea42423 sw a0,-24(s0) + if (ret != BASE_STATUS_OK) { + 3004e9e: fe842783 lw a5,-24(s0) + 3004ea2: c781 beqz a5,3004eaa + return ret; + 3004ea4: fe842783 lw a5,-24(s0) + 3004ea8: a011 j 3004eac + } + } + return BASE_STATUS_OK; + 3004eaa: 4781 li a5,0 +} + 3004eac: 853e mv a0,a5 + 3004eae: 50b2 lw ra,44(sp) + 3004eb0: 5422 lw s0,40(sp) + 3004eb2: 6145 addi sp,sp,48 + 3004eb4: 8082 ret + +03004eb6 : + * @param handle I2C handle. + * @param index The number of I2C. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType SendSlaveAddressReadCmd(I2C_Handle *handle, unsigned int index) +{ + 3004eb6: 7179 addi sp,sp,-48 + 3004eb8: d606 sw ra,44(sp) + 3004eba: d422 sw s0,40(sp) + 3004ebc: 1800 addi s0,sp,48 + 3004ebe: fca42e23 sw a0,-36(s0) + 3004ec2: fcb42c23 sw a1,-40(s0) + BASE_StatusType ret; + unsigned char addr; + /* Write slave address */ + if (handle->addrMode == I2C_10_BITS) { /* 10bit address Configuration */ + 3004ec6: fdc42783 lw a5,-36(s0) + 3004eca: 4798 lw a4,8(a5) + 3004ecc: 4785 li a5,1 + 3004ece: 0af71d63 bne a4,a5,3004f88 + if (handle->transferCount == 0) { + 3004ed2: fdc42783 lw a5,-36(s0) + 3004ed6: 579c lw a5,40(a5) + 3004ed8: ebbd bnez a5,3004f4e + /* The first address of a 10-bit address configuration */ + addr = (unsigned char)((g_internalConfigParam[index].slaveAddress >> I2C_SLAVE_READ_FIX_ADDR_POS) & + 3004eda: 040007b7 lui a5,0x4000 + 3004ede: 49c78713 addi a4,a5,1180 # 400049c + 3004ee2: fd842683 lw a3,-40(s0) + 3004ee6: 47b1 li a5,12 + 3004ee8: 02f687b3 mul a5,a3,a5 + 3004eec: 97ba add a5,a5,a4 + 3004eee: 43dc lw a5,4(a5) + 3004ef0: 83e1 srli a5,a5,0x18 + 3004ef2: fef407a3 sb a5,-17(s0) + I2C_SLAVE_ADDR_MASK); + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_TD_RACK_S_RD_TACK, addr); + 3004ef6: fef44783 lbu a5,-17(s0) + 3004efa: 863e mv a2,a5 + 3004efc: 4589 li a1,2 + 3004efe: fdc42503 lw a0,-36(s0) + 3004f02: 3d1d jal ra,3004d38 + 3004f04: fea42423 sw a0,-24(s0) + if (ret != BASE_STATUS_OK) { + 3004f08: fe842783 lw a5,-24(s0) + 3004f0c: c781 beqz a5,3004f14 + return ret; + 3004f0e: fe842783 lw a5,-24(s0) + 3004f12: a84d j 3004fc4 + } + /* The second address of the 10-bit address configuration */ + addr = (unsigned char)((g_internalConfigParam[index].slaveAddress >> I2C_SLAVE_READ_DEV_ADDR_POS) & + 3004f14: 040007b7 lui a5,0x4000 + 3004f18: 49c78713 addi a4,a5,1180 # 400049c + 3004f1c: fd842683 lw a3,-40(s0) + 3004f20: 47b1 li a5,12 + 3004f22: 02f687b3 mul a5,a3,a5 + 3004f26: 97ba add a5,a5,a4 + 3004f28: 43dc lw a5,4(a5) + 3004f2a: 83c1 srli a5,a5,0x10 + 3004f2c: fef407a3 sb a5,-17(s0) + I2C_SLAVE_ADDR_MASK); + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_TD_RACK_S_RD_TACK, addr); + 3004f30: fef44783 lbu a5,-17(s0) + 3004f34: 863e mv a2,a5 + 3004f36: 4589 li a1,2 + 3004f38: fdc42503 lw a0,-36(s0) + 3004f3c: 3bf5 jal ra,3004d38 + 3004f3e: fea42423 sw a0,-24(s0) + if (ret != BASE_STATUS_OK) { + 3004f42: fe842783 lw a5,-24(s0) + 3004f46: cfb5 beqz a5,3004fc2 + return ret; + 3004f48: fe842783 lw a5,-24(s0) + 3004f4c: a8a5 j 3004fc4 + } + } else { + addr = (unsigned char)((g_internalConfigParam[index].slaveAddress >> I2C_SLAVE_READ_FIX_ADDR_POS) & + 3004f4e: 040007b7 lui a5,0x4000 + 3004f52: 49c78713 addi a4,a5,1180 # 400049c + 3004f56: fd842683 lw a3,-40(s0) + 3004f5a: 47b1 li a5,12 + 3004f5c: 02f687b3 mul a5,a3,a5 + 3004f60: 97ba add a5,a5,a4 + 3004f62: 43dc lw a5,4(a5) + 3004f64: 83e1 srli a5,a5,0x18 + 3004f66: fef407a3 sb a5,-17(s0) + I2C_SLAVE_ADDR_MASK); + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_TD_RACK_S_RD_TACK, addr); + 3004f6a: fef44783 lbu a5,-17(s0) + 3004f6e: 863e mv a2,a5 + 3004f70: 4589 li a1,2 + 3004f72: fdc42503 lw a0,-36(s0) + 3004f76: 33c9 jal ra,3004d38 + 3004f78: fea42423 sw a0,-24(s0) + if (ret != BASE_STATUS_OK) { + 3004f7c: fe842783 lw a5,-24(s0) + 3004f80: c3a9 beqz a5,3004fc2 + return ret; + 3004f82: fe842783 lw a5,-24(s0) + 3004f86: a83d j 3004fc4 + } + } + } else { /* 7bit address Configuration */ + addr = (unsigned char)((g_internalConfigParam[index].slaveAddress >> I2C_SLAVE_READ_DEV_ADDR_POS) & + 3004f88: 040007b7 lui a5,0x4000 + 3004f8c: 49c78713 addi a4,a5,1180 # 400049c + 3004f90: fd842683 lw a3,-40(s0) + 3004f94: 47b1 li a5,12 + 3004f96: 02f687b3 mul a5,a3,a5 + 3004f9a: 97ba add a5,a5,a4 + 3004f9c: 43dc lw a5,4(a5) + 3004f9e: 83c1 srli a5,a5,0x10 + 3004fa0: fef407a3 sb a5,-17(s0) + I2C_SLAVE_ADDR_MASK); + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_TD_RACK_S_RD_TACK, addr); + 3004fa4: fef44783 lbu a5,-17(s0) + 3004fa8: 863e mv a2,a5 + 3004faa: 4589 li a1,2 + 3004fac: fdc42503 lw a0,-36(s0) + 3004fb0: 3361 jal ra,3004d38 + 3004fb2: fea42423 sw a0,-24(s0) + if (ret != BASE_STATUS_OK) { + 3004fb6: fe842783 lw a5,-24(s0) + 3004fba: c781 beqz a5,3004fc2 + return ret; + 3004fbc: fe842783 lw a5,-24(s0) + 3004fc0: a011 j 3004fc4 + } + } + return BASE_STATUS_OK; + 3004fc2: 4781 li a5,0 +} + 3004fc4: 853e mv a0,a5 + 3004fc6: 50b2 lw ra,44(sp) + 3004fc8: 5422 lw s0,40(sp) + 3004fca: 6145 addi sp,sp,48 + 3004fcc: 8082 ret + +03004fce : + * @param handle I2C handle. + * @param transferStatus The status is used to indicate read or write. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType I2C_ConfigParametersAndStartBlocking(I2C_Handle *handle, unsigned int transferStatus) +{ + 3004fce: 7179 addi sp,sp,-48 + 3004fd0: d606 sw ra,44(sp) + 3004fd2: d422 sw s0,40(sp) + 3004fd4: 1800 addi s0,sp,48 + 3004fd6: fca42e23 sw a0,-36(s0) + 3004fda: fcb42c23 sw a1,-40(s0) + BASE_StatusType ret; + /* Startup Control */ + handle->baseAddress->I2C_CTRL1.BIT.dma_operation = I2C_DMA_OP_NONE; + 3004fde: fdc42783 lw a5,-36(s0) + 3004fe2: 4398 lw a4,0(a5) + 3004fe4: 0d072783 lw a5,208(a4) + 3004fe8: cff7f793 andi a5,a5,-769 + 3004fec: 0cf72823 sw a5,208(a4) + handle->baseAddress->I2C_CTRL1.BIT.rst_rx_fifo = BASE_CFG_SET; + 3004ff0: fdc42783 lw a5,-36(s0) + 3004ff4: 4398 lw a4,0(a5) + 3004ff6: 0d072783 lw a5,208(a4) + 3004ffa: 0047e793 ori a5,a5,4 + 3004ffe: 0cf72823 sw a5,208(a4) + handle->baseAddress->I2C_CTRL1.BIT.rst_tx_fifo = BASE_CFG_SET; + 3005002: fdc42783 lw a5,-36(s0) + 3005006: 4398 lw a4,0(a5) + 3005008: 0d072783 lw a5,208(a4) + 300500c: 0087e793 ori a5,a5,8 + 3005010: 0cf72823 sw a5,208(a4) + + handle->baseAddress->I2C_CTRL1.BIT.mst_start = (transferStatus == I2C_MASTER_STATUS) ? BASE_CFG_SET : + 3005014: fdc42783 lw a5,-36(s0) + 3005018: 4398 lw a4,0(a5) + 300501a: fd842783 lw a5,-40(s0) + 300501e: 0017b793 seqz a5,a5 + 3005022: 0ff7f693 andi a3,a5,255 + 3005026: 0d072783 lw a5,208(a4) + 300502a: 8a85 andi a3,a3,1 + 300502c: 9bf9 andi a5,a5,-2 + 300502e: 8fd5 or a5,a5,a3 + 3005030: 0cf72823 sw a5,208(a4) + BASE_CFG_UNSET; + if (transferStatus == I2C_SLAVE_STATUS) { + 3005034: fd842703 lw a4,-40(s0) + 3005038: 4785 li a5,1 + 300503a: 00f71463 bne a4,a5,3005042 + return BASE_STATUS_OK; + 300503e: 4781 li a5,0 + 3005040: a01d j 3005066 + } + /* Send I2C start */ + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_S, 0); /* Sets the start command to be sent. */ + 3005042: 4601 li a2,0 + 3005044: 4585 li a1,1 + 3005046: fdc42503 lw a0,-36(s0) + 300504a: 31fd jal ra,3004d38 + 300504c: fea42623 sw a0,-20(s0) + if (ret != BASE_STATUS_OK) { + 3005050: fec42783 lw a5,-20(s0) + 3005054: c799 beqz a5,3005062 + SetErrorHandling(handle); + 3005056: fdc42503 lw a0,-36(s0) + 300505a: 3425 jal ra,3004a82 + return ret; + 300505c: fec42783 lw a5,-20(s0) + 3005060: a019 j 3005066 + } + return ret; + 3005062: fec42783 lw a5,-20(s0) +} + 3005066: 853e mv a0,a5 + 3005068: 50b2 lw ra,44(sp) + 300506a: 5422 lw s0,40(sp) + 300506c: 6145 addi sp,sp,48 + 300506e: 8082 ret + +03005070 : + * @brief Master send stop command in blocking. + * @param handle I2C handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType BlockingSendStopCommand(I2C_Handle *handle) +{ + 3005070: 7179 addi sp,sp,-48 + 3005072: d606 sw ra,44(sp) + 3005074: d422 sw s0,40(sp) + 3005076: 1800 addi s0,sp,48 + 3005078: fca42e23 sw a0,-36(s0) + BASE_StatusType ret; + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_P, 0); + 300507c: 4601 li a2,0 + 300507e: 45bd li a1,15 + 3005080: fdc42503 lw a0,-36(s0) + 3005084: 3955 jal ra,3004d38 + 3005086: fea42623 sw a0,-20(s0) + if (ret != BASE_STATUS_OK) { + 300508a: fec42783 lw a5,-20(s0) + 300508e: c799 beqz a5,300509c + SetErrorHandling(handle); + 3005090: fdc42503 lw a0,-36(s0) + 3005094: 32fd jal ra,3004a82 + return ret; + 3005096: fec42783 lw a5,-20(s0) + 300509a: a015 j 30050be + } + /* Wait until all commands are executed. */ + ret = WaitStatusReady(handle, COMMAND_ALL_DONE, I2C_OPERATION_WRITE); + 300509c: 4601 li a2,0 + 300509e: 4581 li a1,0 + 30050a0: fdc42503 lw a0,-36(s0) + 30050a4: 3e91 jal ra,3004bf8 + 30050a6: fea42623 sw a0,-20(s0) + handle->errorCode = ret; + 30050aa: fdc42783 lw a5,-36(s0) + 30050ae: fec42703 lw a4,-20(s0) + 30050b2: c7b8 sw a4,72(a5) + SetErrorHandling(handle); + 30050b4: fdc42503 lw a0,-36(s0) + 30050b8: 32e9 jal ra,3004a82 + return ret; + 30050ba: fec42783 lw a5,-20(s0) +} + 30050be: 853e mv a0,a5 + 30050c0: 50b2 lw ra,44(sp) + 30050c2: 5422 lw s0,40(sp) + 30050c4: 6145 addi sp,sp,48 + 30050c6: 8082 ret + +030050c8 : + * @brief The step of receive normal data in blocking as master. + * @param handle I2C handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType BlockingMasterRxDataOptStepNormal(I2C_Handle *handle) +{ + 30050c8: 7179 addi sp,sp,-48 + 30050ca: d606 sw ra,44(sp) + 30050cc: d422 sw s0,40(sp) + 30050ce: 1800 addi s0,sp,48 + 30050d0: fca42e23 sw a0,-36(s0) + BASE_StatusType ret = BASE_STATUS_OK; + 30050d4: fe042623 sw zero,-20(s0) + while (handle->transferCount < handle->transferSize) { + 30050d8: a859 j 300516e + if (handle->transferCount == handle->transferSize - 1) { + 30050da: fdc42783 lw a5,-36(s0) + 30050de: 5798 lw a4,40(a5) + 30050e0: fdc42783 lw a5,-36(s0) + 30050e4: 53dc lw a5,36(a5) + 30050e6: 17fd addi a5,a5,-1 + 30050e8: 00f71a63 bne a4,a5,30050fc + /* Reads the last frame of data without ack. */ + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_RD_TNACK_S_TD_RNACK, 0); + 30050ec: 4601 li a2,0 + 30050ee: 4599 li a1,6 + 30050f0: fdc42503 lw a0,-36(s0) + 30050f4: 3191 jal ra,3004d38 + 30050f6: fea42623 sw a0,-20(s0) + 30050fa: a801 j 300510a + } else { + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_RD_TACK_S_TD_RACK, 0); + 30050fc: 4601 li a2,0 + 30050fe: 4595 li a1,5 + 3005100: fdc42503 lw a0,-36(s0) + 3005104: 3915 jal ra,3004d38 + 3005106: fea42623 sw a0,-20(s0) + } + if (ret != BASE_STATUS_OK) { + 300510a: fec42783 lw a5,-20(s0) + 300510e: c799 beqz a5,300511c + SetErrorHandling(handle); + 3005110: fdc42503 lw a0,-36(s0) + 3005114: 32bd jal ra,3004a82 + return ret; + 3005116: fec42783 lw a5,-20(s0) + 300511a: a0a5 j 3005182 + } + /* Wait the RX FIFO is not empty. */ + ret = WaitStatusReady(handle, RX_FIFO_NOT_EMPTY, I2C_OPERATION_READ); + 300511c: 4605 li a2,1 + 300511e: 4591 li a1,4 + 3005120: fdc42503 lw a0,-36(s0) + 3005124: 3cd1 jal ra,3004bf8 + 3005126: fea42623 sw a0,-20(s0) + if (ret != BASE_STATUS_OK) { + 300512a: fec42783 lw a5,-20(s0) + 300512e: c799 beqz a5,300513c + SetErrorHandling(handle); + 3005130: fdc42503 lw a0,-36(s0) + 3005134: 32b9 jal ra,3004a82 + return ret; + 3005136: fec42783 lw a5,-20(s0) + 300513a: a0a1 j 3005182 + } + /* Obtains the data received from the RX FIFO. */ + *handle->transferBuff = handle->baseAddress->I2C_RX_FIFO.BIT.rx_fifo_rdata; + 300513c: fdc42783 lw a5,-36(s0) + 3005140: 4398 lw a4,0(a5) + 3005142: fdc42783 lw a5,-36(s0) + 3005146: 539c lw a5,32(a5) + 3005148: 5358 lw a4,36(a4) + 300514a: 9f01 uxtb a4 + 300514c: a398 sb a4,0(a5) + handle->transferBuff++; + 300514e: fdc42783 lw a5,-36(s0) + 3005152: 539c lw a5,32(a5) + 3005154: 00178713 addi a4,a5,1 + 3005158: fdc42783 lw a5,-36(s0) + 300515c: d398 sw a4,32(a5) + handle->transferCount++; + 300515e: fdc42783 lw a5,-36(s0) + 3005162: 579c lw a5,40(a5) + 3005164: 00178713 addi a4,a5,1 + 3005168: fdc42783 lw a5,-36(s0) + 300516c: d798 sw a4,40(a5) + while (handle->transferCount < handle->transferSize) { + 300516e: fdc42783 lw a5,-36(s0) + 3005172: 5798 lw a4,40(a5) + 3005174: fdc42783 lw a5,-36(s0) + 3005178: 53dc lw a5,36(a5) + 300517a: f6f760e3 bltu a4,a5,30050da + } + return ret; + 300517e: fec42783 lw a5,-20(s0) +} + 3005182: 853e mv a0,a5 + 3005184: 50b2 lw ra,44(sp) + 3005186: 5422 lw s0,40(sp) + 3005188: 6145 addi sp,sp,48 + 300518a: 8082 ret + +0300518c : + * @brief The step of transmit normal data in blocking as master. + * @param handle I2C handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType BlockingMasterTxDataOptStepNormal(I2C_Handle *handle) +{ + 300518c: 7179 addi sp,sp,-48 + 300518e: d606 sw ra,44(sp) + 3005190: d422 sw s0,40(sp) + 3005192: 1800 addi s0,sp,48 + 3005194: fca42e23 sw a0,-36(s0) + BASE_StatusType ret; + /* Sets data to be sent cyclically. */ + while (handle->transferCount < handle->transferSize) { + 3005198: a0b1 j 30051e4 + ret = SetTxFIFODataAndCmd(handle, I2C_CMD_M_TD_RACK_S_RD_TACK, *handle->transferBuff); + 300519a: fdc42783 lw a5,-36(s0) + 300519e: 539c lw a5,32(a5) + 30051a0: 239c lbu a5,0(a5) + 30051a2: 9f81 uxtb a5 + 30051a4: 863e mv a2,a5 + 30051a6: 4589 li a1,2 + 30051a8: fdc42503 lw a0,-36(s0) + 30051ac: 3671 jal ra,3004d38 + 30051ae: fea42623 sw a0,-20(s0) + if (ret != BASE_STATUS_OK) { + 30051b2: fec42783 lw a5,-20(s0) + 30051b6: c799 beqz a5,30051c4 + SetErrorHandling(handle); + 30051b8: fdc42503 lw a0,-36(s0) + 30051bc: 30d9 jal ra,3004a82 + return ret; + 30051be: fec42783 lw a5,-20(s0) + 30051c2: a815 j 30051f6 + } + handle->transferBuff++; + 30051c4: fdc42783 lw a5,-36(s0) + 30051c8: 539c lw a5,32(a5) + 30051ca: 00178713 addi a4,a5,1 + 30051ce: fdc42783 lw a5,-36(s0) + 30051d2: d398 sw a4,32(a5) + handle->transferCount++; + 30051d4: fdc42783 lw a5,-36(s0) + 30051d8: 579c lw a5,40(a5) + 30051da: 00178713 addi a4,a5,1 + 30051de: fdc42783 lw a5,-36(s0) + 30051e2: d798 sw a4,40(a5) + while (handle->transferCount < handle->transferSize) { + 30051e4: fdc42783 lw a5,-36(s0) + 30051e8: 5798 lw a4,40(a5) + 30051ea: fdc42783 lw a5,-36(s0) + 30051ee: 53dc lw a5,36(a5) + 30051f0: faf765e3 bltu a4,a5,300519a + } + return BASE_STATUS_OK; + 30051f4: 4781 li a5,0 +} + 30051f6: 853e mv a0,a5 + 30051f8: 50b2 lw ra,44(sp) + 30051fa: 5422 lw s0,40(sp) + 30051fc: 6145 addi sp,sp,48 + 30051fe: 8082 ret + +03005200 : + * @brief Initializing the I2C Module. + * @param handle I2C handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_Init(I2C_Handle *handle) +{ + 3005200: 7139 addi sp,sp,-64 + 3005202: de06 sw ra,60(sp) + 3005204: dc22 sw s0,56(sp) + 3005206: 0080 addi s0,sp,64 + 3005208: fca42623 sw a0,-52(s0) + unsigned int tempReg; + unsigned int temp; + unsigned int tempSclLowTime; + unsigned int tempSclHighTime; + + I2C_ASSERT_PARAM(handle != NULL); + 300520c: fcc42783 lw a5,-52(s0) + 3005210: eb89 bnez a5,3005222 + 3005212: 4f400593 li a1,1268 + 3005216: 030097b7 lui a5,0x3009 + 300521a: 9fc78513 addi a0,a5,-1540 # 30089fc + 300521e: 2de1 jal ra,30058f6 + 3005220: a001 j 3005220 + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + 3005222: fcc42783 lw a5,-52(s0) + 3005226: 4398 lw a4,0(a5) + 3005228: 141007b7 lui a5,0x14100 + 300522c: 02f70163 beq a4,a5,300524e + 3005230: fcc42783 lw a5,-52(s0) + 3005234: 4398 lw a4,0(a5) + 3005236: 141017b7 lui a5,0x14101 + 300523a: 00f70a63 beq a4,a5,300524e + 300523e: 4f500593 li a1,1269 + 3005242: 030097b7 lui a5,0x3009 + 3005246: 9fc78513 addi a0,a5,-1540 # 30089fc + 300524a: 2575 jal ra,30058f6 + 300524c: a001 j 300524c + + clockFreq = HAL_CRG_GetIpFreq((void *)handle->baseAddress); + 300524e: fcc42783 lw a5,-52(s0) + 3005252: 439c lw a5,0(a5) + 3005254: 853e mv a0,a5 + 3005256: b14fd0ef jal ra,300256a + 300525a: fea42423 sw a0,-24(s0) + if (CheckAllInitParameters(handle, clockFreq) != BASE_STATUS_OK) { + 300525e: fe842583 lw a1,-24(s0) + 3005262: fcc42503 lw a0,-52(s0) + 3005266: bf2ff0ef jal ra,3004658 + 300526a: 87aa mv a5,a0 + 300526c: c399 beqz a5,3005272 + return BASE_STATUS_ERROR; + 300526e: 4785 li a5,1 + 3005270: a4ad j 30054da + } + + handle->state = I2C_STATE_BUSY; + 3005272: fcc42783 lw a5,-52(s0) + 3005276: 4709 li a4,2 + 3005278: c3f8 sw a4,68(a5) + /* Clears interrupts and disables interrupt reporting to facilitate switching between different working modes. */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + 300527a: fcc42783 lw a5,-52(s0) + 300527e: 439c lw a5,0(a5) + 3005280: 0e07a223 sw zero,228(a5) + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + 3005284: fcc42783 lw a5,-52(s0) + 3005288: 439c lw a5,0(a5) + 300528a: 01000737 lui a4,0x1000 + 300528e: 177d addi a4,a4,-1 # ffffff + 3005290: 0ee7a023 sw a4,224(a5) + + /* Set SDA and SCL glitch filtering time. */ + handle->baseAddress->I2C_FILTER.BIT.spike_filter_time = handle->handleEx.spikeFilterTime; + 3005294: fcc42783 lw a5,-52(s0) + 3005298: 4fb4 lw a3,88(a5) + 300529a: fcc42783 lw a5,-52(s0) + 300529e: 4398 lw a4,0(a5) + 30052a0: 87b6 mv a5,a3 + 30052a2: 8bbd andi a5,a5,15 + 30052a4: 0ff7f693 andi a3,a5,255 + 30052a8: 10c72783 lw a5,268(a4) + 30052ac: 8abd andi a3,a3,15 + 30052ae: 9bc1 andi a5,a5,-16 + 30052b0: 8fd5 or a5,a5,a3 + 30052b2: 10f72623 sw a5,268(a4) + /* Set SCL high and low duratiom time */ + tempSclLowTime = I2C_FREQ_LOW_PARAMTER + handle->handleEx.spikeFilterTime; + 30052b6: fcc42783 lw a5,-52(s0) + 30052ba: 4fbc lw a5,88(a5) + 30052bc: 07a5 addi a5,a5,9 + 30052be: fef42223 sw a5,-28(s0) + tempSclHighTime = I2C_FREQ_HIGH_PARAMTER + handle->handleEx.spikeFilterTime; + 30052c2: fcc42783 lw a5,-52(s0) + 30052c6: 4fbc lw a5,88(a5) + 30052c8: 07a1 addi a5,a5,8 + 30052ca: fef42023 sw a5,-32(s0) + if (handle->freq <= I2C_STANDARD_FREQ_TH) { + 30052ce: fcc42783 lw a5,-52(s0) + 30052d2: 4bd8 lw a4,20(a5) + 30052d4: 67e1 lui a5,0x18 + 30052d6: 6a078793 addi a5,a5,1696 # 186a0 + 30052da: 02e7ee63 bltu a5,a4,3005316 + /* scl_high_time = (fclk_i2c/fSCL) x 0.5 - 8 - spike_filter_time. */ + val = clockFreq / (handle->freq * 2) - tempSclHighTime; /* The clockFreq / (freq * 2) = cloclFreq/0.5/freq. */ + 30052de: fcc42783 lw a5,-52(s0) + 30052e2: 4bdc lw a5,20(a5) + 30052e4: 0786 slli a5,a5,0x1 + 30052e6: fe842703 lw a4,-24(s0) + 30052ea: 02f75733 divu a4,a4,a5 + 30052ee: fe042783 lw a5,-32(s0) + 30052f2: 40f707b3 sub a5,a4,a5 + 30052f6: fef42623 sw a5,-20(s0) + /* scl_low_time = (fclk_i2c/fSCL) x 0.5 - 9 - spike_filter_time. */ + val = ((val - 1) & LOW_HOLD_TIME_MASK) | ((val << HIGH_HOLD_TIME_POS) & HIGH_HOLD_TIME_MASK); + 30052fa: fec42783 lw a5,-20(s0) + 30052fe: fff78713 addi a4,a5,-1 + 3005302: 67c1 lui a5,0x10 + 3005304: 17fd addi a5,a5,-1 # ffff + 3005306: 8f7d and a4,a4,a5 + 3005308: fec42783 lw a5,-20(s0) + 300530c: 07c2 slli a5,a5,0x10 + 300530e: 8fd9 or a5,a5,a4 + 3005310: fef42623 sw a5,-20(s0) + 3005314: a8b9 j 3005372 + } else { + /* scl_high_time = (fclk_i2c/fSCL) x 0.36 - 8 - spike_filter_time. (n/100*36)=0.36n. */ + val = ((((clockFreq / 100) * 36) / handle->freq) - tempSclHighTime) << HIGH_HOLD_TIME_POS; + 3005316: fe842703 lw a4,-24(s0) + 300531a: 06400793 li a5,100 + 300531e: 02f75733 divu a4,a4,a5 + 3005322: 02400793 li a5,36 + 3005326: 02f70733 mul a4,a4,a5 + 300532a: fcc42783 lw a5,-52(s0) + 300532e: 4bdc lw a5,20(a5) + 3005330: 02f75733 divu a4,a4,a5 + 3005334: fe042783 lw a5,-32(s0) + 3005338: 40f707b3 sub a5,a4,a5 + 300533c: 07c2 slli a5,a5,0x10 + 300533e: fef42623 sw a5,-20(s0) + /* scl_low_time = (fclk_i2c/fSCL) x 0.64 - 9 - spike_filter_time. (n/100*64)=0.64n. */ + val |= (((((clockFreq / 100) * 64) / handle->freq) - tempSclLowTime) & LOW_HOLD_TIME_MASK); + 3005342: fe842703 lw a4,-24(s0) + 3005346: 06400793 li a5,100 + 300534a: 02f757b3 divu a5,a4,a5 + 300534e: 00679713 slli a4,a5,0x6 + 3005352: fcc42783 lw a5,-52(s0) + 3005356: 4bdc lw a5,20(a5) + 3005358: 02f75733 divu a4,a4,a5 + 300535c: fe442783 lw a5,-28(s0) + 3005360: 8f1d sub a4,a4,a5 + 3005362: 67c1 lui a5,0x10 + 3005364: 17fd addi a5,a5,-1 # ffff + 3005366: 8ff9 and a5,a5,a4 + 3005368: fec42703 lw a4,-20(s0) + 300536c: 8fd9 or a5,a5,a4 + 300536e: fef42623 sw a5,-20(s0) + } + handle->baseAddress->I2C_SCL_CFG.reg = val; + 3005372: fcc42783 lw a5,-52(s0) + 3005376: 439c lw a5,0(a5) + 3005378: fec42703 lw a4,-20(s0) + 300537c: c3d8 sw a4,4(a5) + + /* Set sda hold duration.The value is fixed to 0xa */ + temp = ((handle->sdaHoldTime & 0x0000FFFF) << I2C_SDA_HOLD_DURATION_POS); + 300537e: fcc42783 lw a5,-52(s0) + 3005382: 4b9c lw a5,16(a5) + 3005384: 07c2 slli a5,a5,0x10 + 3005386: fcf42e23 sw a5,-36(s0) + tempReg = (handle->handleEx.sdaDelayTime & 0x0000000F) | temp; + 300538a: fcc42783 lw a5,-52(s0) + 300538e: 4ffc lw a5,92(a5) + 3005390: 8bbd andi a5,a5,15 + 3005392: fdc42703 lw a4,-36(s0) + 3005396: 8fd9 or a5,a5,a4 + 3005398: fcf42c23 sw a5,-40(s0) + handle->baseAddress->I2C_SDA_CFG.reg = tempReg; + 300539c: fcc42783 lw a5,-52(s0) + 30053a0: 439c lw a5,0(a5) + 30053a2: fd842703 lw a4,-40(s0) + 30053a6: c798 sw a4,8(a5) + + /* Set I2C TX FIFO watermark */ + handle->baseAddress->I2C_TX_WATERMARK.BIT.tx_watermark = handle->txWaterMark; + 30053a8: fcc42783 lw a5,-52(s0) + 30053ac: 5bd4 lw a3,52(a5) + 30053ae: fcc42783 lw a5,-52(s0) + 30053b2: 4398 lw a4,0(a5) + 30053b4: 87b6 mv a5,a3 + 30053b6: 8bbd andi a5,a5,15 + 30053b8: 0ff7f693 andi a3,a5,255 + 30053bc: 0c872783 lw a5,200(a4) + 30053c0: 8abd andi a3,a3,15 + 30053c2: 9bc1 andi a5,a5,-16 + 30053c4: 8fd5 or a5,a5,a3 + 30053c6: 0cf72423 sw a5,200(a4) + /* Set I2C RX FIFO watermark */ + handle->baseAddress->I2C_RX_WATERMARK.BIT.rx_watermark = handle->rxWaterMark; + 30053ca: fcc42783 lw a5,-52(s0) + 30053ce: 5b94 lw a3,48(a5) + 30053d0: fcc42783 lw a5,-52(s0) + 30053d4: 4398 lw a4,0(a5) + 30053d6: 87b6 mv a5,a3 + 30053d8: 8bbd andi a5,a5,15 + 30053da: 0ff7f693 andi a3,a5,255 + 30053de: 0cc72783 lw a5,204(a4) + 30053e2: 8abd andi a3,a3,15 + 30053e4: 9bc1 andi a5,a5,-16 + 30053e6: 8fd5 or a5,a5,a3 + 30053e8: 0cf72623 sw a5,204(a4) + handle->baseAddress->I2C_MODE.BIT.mst_slv_function = handle->functionMode; + 30053ec: fcc42783 lw a5,-52(s0) + 30053f0: 43d4 lw a3,4(a5) + 30053f2: fcc42783 lw a5,-52(s0) + 30053f6: 4398 lw a4,0(a5) + 30053f8: 87b6 mv a5,a3 + 30053fa: 8b8d andi a5,a5,3 + 30053fc: 0ff7f693 andi a3,a5,255 + 3005400: 431c lw a5,0(a4) + 3005402: 8a8d andi a3,a3,3 + 3005404: 9bf1 andi a5,a5,-4 + 3005406: 8fd5 or a5,a5,a3 + 3005408: c31c sw a5,0(a4) + handle->baseAddress->I2C_MODE.BIT.rack_mode = handle->ignoreAckFlag; + 300540a: fcc42783 lw a5,-52(s0) + 300540e: 4f94 lw a3,24(a5) + 3005410: fcc42783 lw a5,-52(s0) + 3005414: 4398 lw a4,0(a5) + 3005416: 87b6 mv a5,a3 + 3005418: 8b85 andi a5,a5,1 + 300541a: 0ff7f693 andi a3,a5,255 + 300541e: 431c lw a5,0(a4) + 3005420: 8a85 andi a3,a3,1 + 3005422: 0692 slli a3,a3,0x4 + 3005424: 9bbd andi a5,a5,-17 + 3005426: 8fd5 or a5,a5,a3 + 3005428: c31c sw a5,0(a4) + + if (handle->functionMode == I2C_MODE_SELECT_SLAVE_ONLY || handle->functionMode == I2C_MODE_SELECT_MASTER_SLAVE) { + 300542a: fcc42783 lw a5,-52(s0) + 300542e: 43d8 lw a4,4(a5) + 3005430: 4789 li a5,2 + 3005432: 00f70863 beq a4,a5,3005442 + 3005436: fcc42783 lw a5,-52(s0) + 300543a: 43d8 lw a4,4(a5) + 300543c: 478d li a5,3 + 300543e: 08f71963 bne a4,a5,30054d0 + /* Sets the first own address of the slave. */ + handle->baseAddress->I2C_OWN_ADDR.BIT.own_address = handle->slaveOwnAddress; + 3005442: fcc42783 lw a5,-52(s0) + 3005446: 47d4 lw a3,12(a5) + 3005448: fcc42783 lw a5,-52(s0) + 300544c: 4398 lw a4,0(a5) + 300544e: 87b6 mv a5,a3 + 3005450: 3ff7f793 andi a5,a5,1023 + 3005454: 01079693 slli a3,a5,0x10 + 3005458: 82c1 srli a3,a3,0x10 + 300545a: 475c lw a5,12(a4) + 300545c: 3ff6f693 andi a3,a3,1023 + 3005460: c007f793 andi a5,a5,-1024 + 3005464: 8fd5 or a5,a5,a3 + 3005466: c75c sw a5,12(a4) + handle->baseAddress->I2C_OWN_ADDR.BIT.i2c_general_call_en = handle->generalCallMode; + 3005468: fcc42783 lw a5,-52(s0) + 300546c: 4fd4 lw a3,28(a5) + 300546e: fcc42783 lw a5,-52(s0) + 3005472: 4398 lw a4,0(a5) + 3005474: 87b6 mv a5,a3 + 3005476: 8b85 andi a5,a5,1 + 3005478: 0ff7f693 andi a3,a5,255 + 300547c: 475c lw a5,12(a4) + 300547e: 8a85 andi a3,a3,1 + 3005480: 06e2 slli a3,a3,0x18 + 3005482: ff000637 lui a2,0xff000 + 3005486: 167d addi a2,a2,-1 # feffffff + 3005488: 8ff1 and a5,a5,a2 + 300548a: 8fd5 or a5,a5,a3 + 300548c: c75c sw a5,12(a4) + /* Sets the second own address of the slave. */ + if (handle->handleEx.slaveOwnXmbAddressEnable == BASE_CFG_ENABLE) { + 300548e: fcc42783 lw a5,-52(s0) + 3005492: 53b8 lw a4,96(a5) + 3005494: 4785 li a5,1 + 3005496: 02f71d63 bne a4,a5,30054d0 + handle->baseAddress->XMB_DEV_ADDR.BIT.xmb_address_en = BASE_CFG_ENABLE; + 300549a: fcc42783 lw a5,-52(s0) + 300549e: 4398 lw a4,0(a5) + 30054a0: 4b1c lw a5,16(a4) + 30054a2: 004006b7 lui a3,0x400 + 30054a6: 8fd5 or a5,a5,a3 + 30054a8: cb1c sw a5,16(a4) + handle->baseAddress->XMB_DEV_ADDR.BIT.xmb_address = handle->handleEx.slaveOwnXmbAddress; + 30054aa: fcc42783 lw a5,-52(s0) + 30054ae: 53f4 lw a3,100(a5) + 30054b0: fcc42783 lw a5,-52(s0) + 30054b4: 4398 lw a4,0(a5) + 30054b6: 87b6 mv a5,a3 + 30054b8: 3ff7f793 andi a5,a5,1023 + 30054bc: 01079693 slli a3,a5,0x10 + 30054c0: 82c1 srli a3,a3,0x10 + 30054c2: 4b1c lw a5,16(a4) + 30054c4: 3ff6f693 andi a3,a3,1023 + 30054c8: c007f793 andi a5,a5,-1024 + 30054cc: 8fd5 or a5,a5,a3 + 30054ce: cb1c sw a5,16(a4) + } + } + handle->state = I2C_STATE_READY; + 30054d0: fcc42783 lw a5,-52(s0) + 30054d4: 4705 li a4,1 + 30054d6: c3f8 sw a4,68(a5) + return BASE_STATUS_OK; + 30054d8: 4781 li a5,0 +} + 30054da: 853e mv a0,a5 + 30054dc: 50f2 lw ra,60(sp) + 30054de: 5462 lw s0,56(sp) + 30054e0: 6121 addi sp,sp,64 + 30054e2: 8082 ret + +030054e4 : + * @param timeout Timeout period,unit: ms. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_MasterReadBlocking(I2C_Handle *handle, unsigned short devAddr, unsigned char *rData, + unsigned int dataSize, unsigned int timeout) +{ + 30054e4: 7139 addi sp,sp,-64 + 30054e6: de06 sw ra,60(sp) + 30054e8: dc22 sw s0,56(sp) + 30054ea: 0080 addi s0,sp,64 + 30054ec: fca42e23 sw a0,-36(s0) + 30054f0: 87ae mv a5,a1 + 30054f2: fcc42a23 sw a2,-44(s0) + 30054f6: fcd42823 sw a3,-48(s0) + 30054fa: fce42623 sw a4,-52(s0) + 30054fe: fcf41d23 sh a5,-38(s0) + I2C_ASSERT_PARAM(handle != NULL && rData != NULL); + 3005502: fdc42783 lw a5,-36(s0) + 3005506: c781 beqz a5,300550e + 3005508: fd442783 lw a5,-44(s0) + 300550c: eb89 bnez a5,300551e + 300550e: 57b00593 li a1,1403 + 3005512: 030097b7 lui a5,0x3009 + 3005516: 9fc78513 addi a0,a5,-1540 # 30089fc + 300551a: 2ef1 jal ra,30058f6 + 300551c: a001 j 300551c + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + 300551e: fdc42783 lw a5,-36(s0) + 3005522: 4398 lw a4,0(a5) + 3005524: 141007b7 lui a5,0x14100 + 3005528: 02f70163 beq a4,a5,300554a + 300552c: fdc42783 lw a5,-36(s0) + 3005530: 4398 lw a4,0(a5) + 3005532: 141017b7 lui a5,0x14101 + 3005536: 00f70a63 beq a4,a5,300554a + 300553a: 57c00593 li a1,1404 + 300553e: 030097b7 lui a5,0x3009 + 3005542: 9fc78513 addi a0,a5,-1540 # 30089fc + 3005546: 2e45 jal ra,30058f6 + 3005548: a001 j 3005548 + I2C_PARAM_CHECK_WITH_RET(devAddr <= I2C_MAX_DEV_ADDR, BASE_STATUS_ERROR); + 300554a: fda45703 lhu a4,-38(s0) + 300554e: 3ff00793 li a5,1023 + 3005552: 00e7fb63 bgeu a5,a4,3005568 + 3005556: 57d00593 li a1,1405 + 300555a: 030097b7 lui a5,0x3009 + 300555e: 9fc78513 addi a0,a5,-1540 # 30089fc + 3005562: 2e51 jal ra,30058f6 + 3005564: 4785 li a5,1 + 3005566: aaad j 30056e0 + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + 3005568: fd042783 lw a5,-48(s0) + 300556c: eb91 bnez a5,3005580 + 300556e: 57e00593 li a1,1406 + 3005572: 030097b7 lui a5,0x3009 + 3005576: 9fc78513 addi a0,a5,-1540 # 30089fc + 300557a: 2eb5 jal ra,30058f6 + 300557c: 4785 li a5,1 + 300557e: a28d j 30056e0 + I2C_PARAM_CHECK_WITH_RET(timeout > 0, BASE_STATUS_ERROR); + 3005580: fcc42783 lw a5,-52(s0) + 3005584: eb91 bnez a5,3005598 + 3005586: 57f00593 li a1,1407 + 300558a: 030097b7 lui a5,0x3009 + 300558e: 9fc78513 addi a0,a5,-1540 # 30089fc + 3005592: 2695 jal ra,30058f6 + 3005594: 4785 li a5,1 + 3005596: a2a9 j 30056e0 + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + 3005598: fdc42783 lw a5,-36(s0) + 300559c: 43f8 lw a4,68(a5) + 300559e: 4785 li a5,1 + 30055a0: 00f70b63 beq a4,a5,30055b6 + 30055a4: 58000593 li a1,1408 + 30055a8: 030097b7 lui a5,0x3009 + 30055ac: 9fc78513 addi a0,a5,-1540 # 30089fc + 30055b0: 2699 jal ra,30058f6 + 30055b2: 4785 li a5,1 + 30055b4: a235 j 30056e0 + + BASE_StatusType ret; + unsigned int index = 0; + 30055b6: fe042623 sw zero,-20(s0) + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + 30055ba: fdc42783 lw a5,-36(s0) + 30055be: 439c lw a5,0(a5) + 30055c0: 0e07a223 sw zero,228(a5) + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + 30055c4: fdc42783 lw a5,-36(s0) + 30055c8: 439c lw a5,0(a5) + 30055ca: 01000737 lui a4,0x1000 + 30055ce: 177d addi a4,a4,-1 # ffffff + 30055d0: 0ee7a023 sw a4,224(a5) + + /* Determine which I2C is used. */ + index = (handle->baseAddress == I2C0) ? I2C_INTERFACE_INDEX_0 : I2C_INTERFACE_INDEX_1; + 30055d4: fdc42783 lw a5,-36(s0) + 30055d8: 4398 lw a4,0(a5) + 30055da: ebf007b7 lui a5,0xebf00 + 30055de: 97ba add a5,a5,a4 + 30055e0: 00f037b3 snez a5,a5 + 30055e4: 9f81 uxtb a5 + 30055e6: fef42623 sw a5,-20(s0) + /* Waiting for the i2c bus to be idle. */ + ret = WaitStatusReady(handle, I2C_BUS_IS_FREE, I2C_SEND_ADDR_STATUS_WRITE); + 30055ea: 4605 li a2,1 + 30055ec: 4585 li a1,1 + 30055ee: fdc42503 lw a0,-36(s0) + 30055f2: e06ff0ef jal ra,3004bf8 + 30055f6: fea42423 sw a0,-24(s0) + if (ret != BASE_STATUS_OK) { + 30055fa: fe842783 lw a5,-24(s0) + 30055fe: cf89 beqz a5,3005618 + handle->errorCode = ret; + 3005600: fdc42783 lw a5,-36(s0) + 3005604: fe842703 lw a4,-24(s0) + 3005608: c7b8 sw a4,72(a5) + SetErrorHandling(handle); + 300560a: fdc42503 lw a0,-36(s0) + 300560e: c74ff0ef jal ra,3004a82 + return ret; + 3005612: fe842783 lw a5,-24(s0) + 3005616: a0e9 j 30056e0 + } + /* Configuring I2C Parameters. */ + handle->state = I2C_STATE_BUSY_MASTER_RX; + 3005618: fdc42783 lw a5,-36(s0) + 300561c: 4711 li a4,4 + 300561e: c3f8 sw a4,68(a5) + handle->transferBuff = rData; + 3005620: fdc42783 lw a5,-36(s0) + 3005624: fd442703 lw a4,-44(s0) + 3005628: d398 sw a4,32(a5) + handle->transferSize = dataSize; + 300562a: fdc42783 lw a5,-36(s0) + 300562e: fd042703 lw a4,-48(s0) + 3005632: d3d8 sw a4,36(a5) + handle->transferCount = 0; + 3005634: fdc42783 lw a5,-36(s0) + 3005638: 0207a423 sw zero,40(a5) # ebf00028 + handle->timeout = timeout; + 300563c: fdc42783 lw a5,-36(s0) + 3005640: fcc42703 lw a4,-52(s0) + 3005644: d7d8 sw a4,44(a5) + SetSlaveDevAddr(handle, devAddr); + 3005646: fda45783 lhu a5,-38(s0) + 300564a: 85be mv a1,a5 + 300564c: fdc42503 lw a0,-36(s0) + 3005650: a58ff0ef jal ra,30048a8 + + /* step1 : Parameter Settings and startup Control. */ + ret = I2C_ConfigParametersAndStartBlocking(handle, I2C_MASTER_STATUS); + 3005654: 4581 li a1,0 + 3005656: fdc42503 lw a0,-36(s0) + 300565a: 3a95 jal ra,3004fce + 300565c: fea42423 sw a0,-24(s0) + if (ret != BASE_STATUS_OK) { + 3005660: fe842783 lw a5,-24(s0) + 3005664: cf89 beqz a5,300567e + handle->errorCode = ret; + 3005666: fdc42783 lw a5,-36(s0) + 300566a: fe842703 lw a4,-24(s0) + 300566e: c7b8 sw a4,72(a5) + SetErrorHandling(handle); + 3005670: fdc42503 lw a0,-36(s0) + 3005674: c0eff0ef jal ra,3004a82 + return ret; + 3005678: fe842783 lw a5,-24(s0) + 300567c: a095 j 30056e0 + } + /* step2 : Send slave address and read command. */ + ret = SendSlaveAddressReadCmd(handle, index); + 300567e: fec42583 lw a1,-20(s0) + 3005682: fdc42503 lw a0,-36(s0) + 3005686: 3805 jal ra,3004eb6 + 3005688: fea42423 sw a0,-24(s0) + if (ret != BASE_STATUS_OK) { + 300568c: fe842783 lw a5,-24(s0) + 3005690: cf89 beqz a5,30056aa + handle->errorCode = ret; + 3005692: fdc42783 lw a5,-36(s0) + 3005696: fe842703 lw a4,-24(s0) + 300569a: c7b8 sw a4,72(a5) + SetErrorHandling(handle); + 300569c: fdc42503 lw a0,-36(s0) + 30056a0: be2ff0ef jal ra,3004a82 + return ret; + 30056a4: fe842783 lw a5,-24(s0) + 30056a8: a825 j 30056e0 + } + /* step3 : start receive data. */ + ret = BlockingMasterRxDataOptStepNormal(handle); + 30056aa: fdc42503 lw a0,-36(s0) + 30056ae: 3c29 jal ra,30050c8 + 30056b0: fea42423 sw a0,-24(s0) + if (ret != BASE_STATUS_OK) { + 30056b4: fe842783 lw a5,-24(s0) + 30056b8: cf89 beqz a5,30056d2 + handle->errorCode = ret; + 30056ba: fdc42783 lw a5,-36(s0) + 30056be: fe842703 lw a4,-24(s0) + 30056c2: c7b8 sw a4,72(a5) + SetErrorHandling(handle); + 30056c4: fdc42503 lw a0,-36(s0) + 30056c8: bbaff0ef jal ra,3004a82 + return ret; + 30056cc: fe842783 lw a5,-24(s0) + 30056d0: a801 j 30056e0 + } + /* step4 ：send stop CMD. */ + ret = BlockingSendStopCommand(handle); + 30056d2: fdc42503 lw a0,-36(s0) + 30056d6: 3a69 jal ra,3005070 + 30056d8: fea42423 sw a0,-24(s0) + + return ret; + 30056dc: fe842783 lw a5,-24(s0) +} + 30056e0: 853e mv a0,a5 + 30056e2: 50f2 lw ra,60(sp) + 30056e4: 5462 lw s0,56(sp) + 30056e6: 6121 addi sp,sp,64 + 30056e8: 8082 ret + +030056ea : + * @param timeout Timeout period,unit: ms. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_MasterWriteBlocking(I2C_Handle *handle, unsigned short devAddr, unsigned char *wData, + unsigned int dataSize, unsigned int timeout) +{ + 30056ea: 7139 addi sp,sp,-64 + 30056ec: de06 sw ra,60(sp) + 30056ee: dc22 sw s0,56(sp) + 30056f0: 0080 addi s0,sp,64 + 30056f2: fca42e23 sw a0,-36(s0) + 30056f6: 87ae mv a5,a1 + 30056f8: fcc42a23 sw a2,-44(s0) + 30056fc: fcd42823 sw a3,-48(s0) + 3005700: fce42623 sw a4,-52(s0) + 3005704: fcf41d23 sh a5,-38(s0) + I2C_ASSERT_PARAM(handle != NULL && wData != NULL); + 3005708: fdc42783 lw a5,-36(s0) + 300570c: c781 beqz a5,3005714 + 300570e: fd442783 lw a5,-44(s0) + 3005712: eb89 bnez a5,3005724 + 3005714: 5bf00593 li a1,1471 + 3005718: 030097b7 lui a5,0x3009 + 300571c: 9fc78513 addi a0,a5,-1540 # 30089fc + 3005720: 2ad9 jal ra,30058f6 + 3005722: a001 j 3005722 + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + 3005724: fdc42783 lw a5,-36(s0) + 3005728: 4398 lw a4,0(a5) + 300572a: 141007b7 lui a5,0x14100 + 300572e: 02f70163 beq a4,a5,3005750 + 3005732: fdc42783 lw a5,-36(s0) + 3005736: 4398 lw a4,0(a5) + 3005738: 141017b7 lui a5,0x14101 + 300573c: 00f70a63 beq a4,a5,3005750 + 3005740: 5c000593 li a1,1472 + 3005744: 030097b7 lui a5,0x3009 + 3005748: 9fc78513 addi a0,a5,-1540 # 30089fc + 300574c: 226d jal ra,30058f6 + 300574e: a001 j 300574e + I2C_PARAM_CHECK_WITH_RET(devAddr <= I2C_MAX_DEV_ADDR, BASE_STATUS_ERROR); + 3005750: fda45703 lhu a4,-38(s0) + 3005754: 3ff00793 li a5,1023 + 3005758: 00e7fb63 bgeu a5,a4,300576e + 300575c: 5c100593 li a1,1473 + 3005760: 030097b7 lui a5,0x3009 + 3005764: 9fc78513 addi a0,a5,-1540 # 30089fc + 3005768: 2279 jal ra,30058f6 + 300576a: 4785 li a5,1 + 300576c: a241 j 30058ec + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + 300576e: fd042783 lw a5,-48(s0) + 3005772: eb91 bnez a5,3005786 + 3005774: 5c200593 li a1,1474 + 3005778: 030097b7 lui a5,0x3009 + 300577c: 9fc78513 addi a0,a5,-1540 # 30089fc + 3005780: 2a9d jal ra,30058f6 + 3005782: 4785 li a5,1 + 3005784: a2a5 j 30058ec + I2C_PARAM_CHECK_WITH_RET(timeout > 0, BASE_STATUS_ERROR); + 3005786: fcc42783 lw a5,-52(s0) + 300578a: eb91 bnez a5,300579e + 300578c: 5c300593 li a1,1475 + 3005790: 030097b7 lui a5,0x3009 + 3005794: 9fc78513 addi a0,a5,-1540 # 30089fc + 3005798: 2ab9 jal ra,30058f6 + 300579a: 4785 li a5,1 + 300579c: aa81 j 30058ec + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + 300579e: fdc42783 lw a5,-36(s0) + 30057a2: 43f8 lw a4,68(a5) + 30057a4: 4785 li a5,1 + 30057a6: 00f70b63 beq a4,a5,30057bc + 30057aa: 5c400593 li a1,1476 + 30057ae: 030097b7 lui a5,0x3009 + 30057b2: 9fc78513 addi a0,a5,-1540 # 30089fc + 30057b6: 2281 jal ra,30058f6 + 30057b8: 4785 li a5,1 + 30057ba: aa0d j 30058ec + + BASE_StatusType ret = BASE_STATUS_OK; + 30057bc: fe042623 sw zero,-20(s0) + unsigned int index; + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + 30057c0: fdc42783 lw a5,-36(s0) + 30057c4: 439c lw a5,0(a5) + 30057c6: 0e07a223 sw zero,228(a5) + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + 30057ca: fdc42783 lw a5,-36(s0) + 30057ce: 439c lw a5,0(a5) + 30057d0: 01000737 lui a4,0x1000 + 30057d4: 177d addi a4,a4,-1 # ffffff + 30057d6: 0ee7a023 sw a4,224(a5) + + /* Determine which I2C is used. */ + index = (handle->baseAddress == I2C0) ? I2C_INTERFACE_INDEX_0 : I2C_INTERFACE_INDEX_1; + 30057da: fdc42783 lw a5,-36(s0) + 30057de: 4398 lw a4,0(a5) + 30057e0: ebf007b7 lui a5,0xebf00 + 30057e4: 97ba add a5,a5,a4 + 30057e6: 00f037b3 snez a5,a5 + 30057ea: 9f81 uxtb a5 + 30057ec: fef42423 sw a5,-24(s0) + + /* Configuring I2C Parameters. */ + handle->state = I2C_STATE_BUSY_MASTER_TX; + 30057f0: fdc42783 lw a5,-36(s0) + 30057f4: 470d li a4,3 + 30057f6: c3f8 sw a4,68(a5) + handle->transferBuff = wData; + 30057f8: fdc42783 lw a5,-36(s0) + 30057fc: fd442703 lw a4,-44(s0) + 3005800: d398 sw a4,32(a5) + handle->transferSize = dataSize; + 3005802: fdc42783 lw a5,-36(s0) + 3005806: fd042703 lw a4,-48(s0) + 300580a: d3d8 sw a4,36(a5) + handle->transferCount = 0; + 300580c: fdc42783 lw a5,-36(s0) + 3005810: 0207a423 sw zero,40(a5) # ebf00028 + handle->timeout = timeout; + 3005814: fdc42783 lw a5,-36(s0) + 3005818: fcc42703 lw a4,-52(s0) + 300581c: d7d8 sw a4,44(a5) + SetSlaveDevAddr(handle, devAddr); + 300581e: fda45783 lhu a5,-38(s0) + 3005822: 85be mv a1,a5 + 3005824: fdc42503 lw a0,-36(s0) + 3005828: 880ff0ef jal ra,30048a8 + + /* Waiting for the i2c bus to be idle. */ + ret = WaitStatusReady(handle, I2C_BUS_IS_FREE, I2C_SEND_ADDR_STATUS_READ); + 300582c: 4609 li a2,2 + 300582e: 4585 li a1,1 + 3005830: fdc42503 lw a0,-36(s0) + 3005834: bc4ff0ef jal ra,3004bf8 + 3005838: fea42623 sw a0,-20(s0) + if (ret != BASE_STATUS_OK) { + 300583c: fec42783 lw a5,-20(s0) + 3005840: cf89 beqz a5,300585a + handle->errorCode = ret; + 3005842: fdc42783 lw a5,-36(s0) + 3005846: fec42703 lw a4,-20(s0) + 300584a: c7b8 sw a4,72(a5) + SetErrorHandling(handle); + 300584c: fdc42503 lw a0,-36(s0) + 3005850: a32ff0ef jal ra,3004a82 + return ret; + 3005854: fec42783 lw a5,-20(s0) + 3005858: a851 j 30058ec + } + + /* step1 : Parameter Settings and startup Control. */ + ret = I2C_ConfigParametersAndStartBlocking(handle, I2C_MASTER_STATUS); + 300585a: 4581 li a1,0 + 300585c: fdc42503 lw a0,-36(s0) + 3005860: f6eff0ef jal ra,3004fce + 3005864: fea42623 sw a0,-20(s0) + if (ret != BASE_STATUS_OK) { + 3005868: fec42783 lw a5,-20(s0) + 300586c: cf89 beqz a5,3005886 + handle->errorCode = ret; + 300586e: fdc42783 lw a5,-36(s0) + 3005872: fec42703 lw a4,-20(s0) + 3005876: c7b8 sw a4,72(a5) + SetErrorHandling(handle); + 3005878: fdc42503 lw a0,-36(s0) + 300587c: a06ff0ef jal ra,3004a82 + return ret; + 3005880: fec42783 lw a5,-20(s0) + 3005884: a0a5 j 30058ec + } + /* step2 : send slave addr */ + ret = SendSlaveAddressWriteCmd(handle, index); + 3005886: fe842583 lw a1,-24(s0) + 300588a: fdc42503 lw a0,-36(s0) + 300588e: d14ff0ef jal ra,3004da2 + 3005892: fea42623 sw a0,-20(s0) + if (ret != BASE_STATUS_OK) { + 3005896: fec42783 lw a5,-20(s0) + 300589a: cf89 beqz a5,30058b4 + handle->errorCode = ret; + 300589c: fdc42783 lw a5,-36(s0) + 30058a0: fec42703 lw a4,-20(s0) + 30058a4: c7b8 sw a4,72(a5) + SetErrorHandling(handle); + 30058a6: fdc42503 lw a0,-36(s0) + 30058aa: 9d8ff0ef jal ra,3004a82 + return ret; + 30058ae: fec42783 lw a5,-20(s0) + 30058b2: a82d j 30058ec + } + /* step3 : Send to slave data */ + ret = BlockingMasterTxDataOptStepNormal(handle); + 30058b4: fdc42503 lw a0,-36(s0) + 30058b8: 38d1 jal ra,300518c + 30058ba: fea42623 sw a0,-20(s0) + if (ret != BASE_STATUS_OK) { + 30058be: fec42783 lw a5,-20(s0) + 30058c2: cf89 beqz a5,30058dc + handle->errorCode = ret; + 30058c4: fdc42783 lw a5,-36(s0) + 30058c8: fec42703 lw a4,-20(s0) + 30058cc: c7b8 sw a4,72(a5) + SetErrorHandling(handle); + 30058ce: fdc42503 lw a0,-36(s0) + 30058d2: 9b0ff0ef jal ra,3004a82 + return ret; + 30058d6: fec42783 lw a5,-20(s0) + 30058da: a809 j 30058ec + } + /* step4 : send stop CMD */ + ret = BlockingSendStopCommand(handle); + 30058dc: fdc42503 lw a0,-36(s0) + 30058e0: f90ff0ef jal ra,3005070 + 30058e4: fea42623 sw a0,-20(s0) + + return ret; + 30058e8: fec42783 lw a5,-20(s0) +} + 30058ec: 853e mv a0,a5 + 30058ee: 50f2 lw ra,60(sp) + 30058f0: 5462 lw s0,56(sp) + 30058f2: 6121 addi sp,sp,64 + 30058f4: 8082 ret + +030058f6 : + 30058f6: 913fb06f j 3001208 + +030058fa : + * @param iocmgRegx Value of @ref IOCMG_REG. + * @param regValue value of @ref IOCMG_REG. + * @retval None. + */ +static inline void DCL_IOCMG_SetRegValue(IOCMG_REG *iocmgRegx, unsigned int regValue) +{ + 30058fa: 1101 addi sp,sp,-32 + 30058fc: ce06 sw ra,28(sp) + 30058fe: cc22 sw s0,24(sp) + 3005900: 1000 addi s0,sp,32 + 3005902: fea42623 sw a0,-20(s0) + 3005906: feb42423 sw a1,-24(s0) + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + 300590a: fec42703 lw a4,-20(s0) + 300590e: 77c1 lui a5,0xffff0 + 3005910: 8f7d and a4,a4,a5 + 3005912: 147f07b7 lui a5,0x147f0 + 3005916: 00f70a63 beq a4,a5,300592a + 300591a: 08b00593 li a1,139 + 300591e: 030097b7 lui a5,0x3009 + 3005922: a2c78513 addi a0,a5,-1492 # 3008a2c + 3005926: 3fc1 jal ra,30058f6 + 3005928: a001 j 3005928 + iocmgRegx->reg = regValue; + 300592a: fec42783 lw a5,-20(s0) + 300592e: fe842703 lw a4,-24(s0) + 3005932: c398 sw a4,0(a5) +} + 3005934: 0001 nop + 3005936: 40f2 lw ra,28(sp) + 3005938: 4462 lw s0,24(sp) + 300593a: 6105 addi sp,sp,32 + 300593c: 8082 ret + +0300593e : + * @param iocmgRegx Value of @ref IOCMG_REG. + * @param driveRate value of @ref IOCMG_DriveRate. + * @retval None. + */ +static inline void DCL_IOCMG_SetDriveRate(IOCMG_REG *iocmgRegx, IOCMG_DriveRate driveRate) +{ + 300593e: 1101 addi sp,sp,-32 + 3005940: ce06 sw ra,28(sp) + 3005942: cc22 sw s0,24(sp) + 3005944: 1000 addi s0,sp,32 + 3005946: fea42623 sw a0,-20(s0) + 300594a: feb42423 sw a1,-24(s0) + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + 300594e: fec42703 lw a4,-20(s0) + 3005952: 77c1 lui a5,0xffff0 + 3005954: 8f7d and a4,a4,a5 + 3005956: 147f07b7 lui a5,0x147f0 + 300595a: 00f70a63 beq a4,a5,300596e + 300595e: 0ba00593 li a1,186 + 3005962: 030097b7 lui a5,0x3009 + 3005966: a2c78513 addi a0,a5,-1492 # 3008a2c + 300596a: 3771 jal ra,30058f6 + 300596c: a001 j 300596c + IOCMG_PARAM_CHECK_NO_RET(driveRate < DRIVER_RATE_MAX && driveRate >= DRIVER_RATE_4); + 300596e: fe842703 lw a4,-24(s0) + 3005972: 478d li a5,3 + 3005974: 00e7fa63 bgeu a5,a4,3005988 + 3005978: 0bb00593 li a1,187 + 300597c: 030097b7 lui a5,0x3009 + 3005980: a2c78513 addi a0,a5,-1492 # 3008a2c + 3005984: 3f8d jal ra,30058f6 + 3005986: a839 j 30059a4 + iocmgRegx->BIT.ds = driveRate; + 3005988: fe842783 lw a5,-24(s0) + 300598c: 8b8d andi a5,a5,3 + 300598e: 0ff7f693 andi a3,a5,255 + 3005992: fec42703 lw a4,-20(s0) + 3005996: 431c lw a5,0(a4) + 3005998: 8a8d andi a3,a3,3 + 300599a: 0692 slli a3,a3,0x4 + 300599c: fcf7f793 andi a5,a5,-49 + 30059a0: 8fd5 or a5,a5,a3 + 30059a2: c31c sw a5,0(a4) +} + 30059a4: 40f2 lw ra,28(sp) + 30059a6: 4462 lw s0,24(sp) + 30059a8: 6105 addi sp,sp,32 + 30059aa: 8082 ret + +030059ac : + * @param iocmgRegx Value of @ref IOCMG_REG. + * @param pullMode value of @ref IOCMG_PullMode. + * @retval None. + */ +static inline void DCL_IOCMG_SetPullMode(IOCMG_REG *iocmgRegx, IOCMG_PullMode pullMode) +{ + 30059ac: 1101 addi sp,sp,-32 + 30059ae: ce06 sw ra,28(sp) + 30059b0: cc22 sw s0,24(sp) + 30059b2: 1000 addi s0,sp,32 + 30059b4: fea42623 sw a0,-20(s0) + 30059b8: feb42423 sw a1,-24(s0) + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + 30059bc: fec42703 lw a4,-20(s0) + 30059c0: 77c1 lui a5,0xffff0 + 30059c2: 8f7d and a4,a4,a5 + 30059c4: 147f07b7 lui a5,0x147f0 + 30059c8: 00f70a63 beq a4,a5,30059dc + 30059cc: 0d200593 li a1,210 + 30059d0: 030097b7 lui a5,0x3009 + 30059d4: a2c78513 addi a0,a5,-1492 # 3008a2c + 30059d8: 3f39 jal ra,30058f6 + 30059da: a001 j 30059da + IOCMG_PARAM_CHECK_NO_RET(pullMode < PULL_MODE_MAX && pullMode >= PULL_NONE); + 30059dc: fe842703 lw a4,-24(s0) + 30059e0: 478d li a5,3 + 30059e2: 00e7fa63 bgeu a5,a4,30059f6 + 30059e6: 0d300593 li a1,211 + 30059ea: 030097b7 lui a5,0x3009 + 30059ee: a2c78513 addi a0,a5,-1492 # 3008a2c + 30059f2: 3711 jal ra,30058f6 + 30059f4: a835 j 3005a30 + iocmgRegx->BIT.pu = (pullMode & 0x02) >> 1; /* 10b: pull up mode */ + 30059f6: fe842783 lw a5,-24(s0) + 30059fa: 8385 srli a5,a5,0x1 + 30059fc: 8b85 andi a5,a5,1 + 30059fe: 0ff7f693 andi a3,a5,255 + 3005a02: fec42703 lw a4,-20(s0) + 3005a06: 431c lw a5,0(a4) + 3005a08: 8a85 andi a3,a3,1 + 3005a0a: 06a2 slli a3,a3,0x8 + 3005a0c: eff7f793 andi a5,a5,-257 + 3005a10: 8fd5 or a5,a5,a3 + 3005a12: c31c sw a5,0(a4) + iocmgRegx->BIT.pd = pullMode & 0x01; /* 01b: pull down mode */ + 3005a14: fe842783 lw a5,-24(s0) + 3005a18: 8b85 andi a5,a5,1 + 3005a1a: 0ff7f693 andi a3,a5,255 + 3005a1e: fec42703 lw a4,-20(s0) + 3005a22: 431c lw a5,0(a4) + 3005a24: 8a85 andi a3,a3,1 + 3005a26: 069e slli a3,a3,0x7 + 3005a28: f7f7f793 andi a5,a5,-129 + 3005a2c: 8fd5 or a5,a5,a3 + 3005a2e: c31c sw a5,0(a4) +} + 3005a30: 40f2 lw ra,28(sp) + 3005a32: 4462 lw s0,24(sp) + 3005a34: 6105 addi sp,sp,32 + 3005a36: 8082 ret + +03005a38 : + * @param iocmgRegx Value of @ref IOCMG_REG. + * @param levelShiftRate value of @ref IOCMG_LevelShiftRate. + * @retval None. + */ +static inline void DCL_IOCMG_SetLevelShiftRate(IOCMG_REG *iocmgRegx, IOCMG_LevelShiftRate levelShiftRate) +{ + 3005a38: 1101 addi sp,sp,-32 + 3005a3a: ce06 sw ra,28(sp) + 3005a3c: cc22 sw s0,24(sp) + 3005a3e: 1000 addi s0,sp,32 + 3005a40: fea42623 sw a0,-20(s0) + 3005a44: feb42423 sw a1,-24(s0) + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + 3005a48: fec42703 lw a4,-20(s0) + 3005a4c: 77c1 lui a5,0xffff0 + 3005a4e: 8f7d and a4,a4,a5 + 3005a50: 147f07b7 lui a5,0x147f0 + 3005a54: 00f70a63 beq a4,a5,3005a68 + 3005a58: 0ed00593 li a1,237 + 3005a5c: 030097b7 lui a5,0x3009 + 3005a60: a2c78513 addi a0,a5,-1492 # 3008a2c + 3005a64: 3d49 jal ra,30058f6 + 3005a66: a001 j 3005a66 + IOCMG_PARAM_CHECK_NO_RET(levelShiftRate < LEVEL_SHIFT_RATE_MAX && levelShiftRate >= LEVEL_SHIFT_RATE_FAST); + 3005a68: fe842703 lw a4,-24(s0) + 3005a6c: 4785 li a5,1 + 3005a6e: 00e7fa63 bgeu a5,a4,3005a82 + 3005a72: 0ee00593 li a1,238 + 3005a76: 030097b7 lui a5,0x3009 + 3005a7a: a2c78513 addi a0,a5,-1492 # 3008a2c + 3005a7e: 3da5 jal ra,30058f6 + 3005a80: a839 j 3005a9e + iocmgRegx->BIT.sr = levelShiftRate; + 3005a82: fe842783 lw a5,-24(s0) + 3005a86: 8b85 andi a5,a5,1 + 3005a88: 0ff7f693 andi a3,a5,255 + 3005a8c: fec42703 lw a4,-20(s0) + 3005a90: 431c lw a5,0(a4) + 3005a92: 8a85 andi a3,a3,1 + 3005a94: 06a6 slli a3,a3,0x9 + 3005a96: dff7f793 andi a5,a5,-513 + 3005a9a: 8fd5 or a5,a5,a3 + 3005a9c: c31c sw a5,0(a4) +} + 3005a9e: 40f2 lw ra,28(sp) + 3005aa0: 4462 lw s0,24(sp) + 3005aa2: 6105 addi sp,sp,32 + 3005aa4: 8082 ret + +03005aa6 : + * @param iocmgRegx Value of @ref IOCMG_REG. + * @param schmidtMode value of @ref IOCMG_SchmidtMode. + * @retval None. + */ +static inline void DCL_IOCMG_SetSchmidtMode(IOCMG_REG *iocmgRegx, IOCMG_SchmidtMode schmidtMode) +{ + 3005aa6: 1101 addi sp,sp,-32 + 3005aa8: ce06 sw ra,28(sp) + 3005aaa: cc22 sw s0,24(sp) + 3005aac: 1000 addi s0,sp,32 + 3005aae: fea42623 sw a0,-20(s0) + 3005ab2: feb42423 sw a1,-24(s0) + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + 3005ab6: fec42703 lw a4,-20(s0) + 3005aba: 77c1 lui a5,0xffff0 + 3005abc: 8f7d and a4,a4,a5 + 3005abe: 147f07b7 lui a5,0x147f0 + 3005ac2: 00f70a63 beq a4,a5,3005ad6 + 3005ac6: 10500593 li a1,261 + 3005aca: 030097b7 lui a5,0x3009 + 3005ace: a2c78513 addi a0,a5,-1492 # 3008a2c + 3005ad2: 3515 jal ra,30058f6 + 3005ad4: a001 j 3005ad4 + IOCMG_PARAM_CHECK_NO_RET(schmidtMode <= SCHMIDT_ENABLE && schmidtMode >= SCHMIDT_DISABLE); + 3005ad6: fe842703 lw a4,-24(s0) + 3005ada: 4785 li a5,1 + 3005adc: 00e7fa63 bgeu a5,a4,3005af0 + 3005ae0: 10600593 li a1,262 + 3005ae4: 030097b7 lui a5,0x3009 + 3005ae8: a2c78513 addi a0,a5,-1492 # 3008a2c + 3005aec: 3529 jal ra,30058f6 + 3005aee: a839 j 3005b0c + iocmgRegx->BIT.se = schmidtMode; + 3005af0: fe842783 lw a5,-24(s0) + 3005af4: 8b85 andi a5,a5,1 + 3005af6: 0ff7f693 andi a3,a5,255 + 3005afa: fec42703 lw a4,-20(s0) + 3005afe: 431c lw a5,0(a4) + 3005b00: 8a85 andi a3,a3,1 + 3005b02: 06aa slli a3,a3,0xa + 3005b04: bff7f793 andi a5,a5,-1025 + 3005b08: 8fd5 or a5,a5,a3 + 3005b0a: c31c sw a5,0(a4) +} + 3005b0c: 40f2 lw ra,28(sp) + 3005b0e: 4462 lw s0,24(sp) + 3005b10: 6105 addi sp,sp,32 + 3005b12: 8082 ret + +03005b14 : + * @brief Get pins iocmg reg address + * @param pinTypedef the pin type defined in iomap.h + * @retval IOCMG_REG iocmg reg address. + */ +static IOCMG_REG* IOCMG_GetRegAddr(unsigned int pinTypedef) +{ + 3005b14: 7179 addi sp,sp,-48 + 3005b16: d622 sw s0,44(sp) + 3005b18: 1800 addi s0,sp,48 + 3005b1a: fca42e23 sw a0,-36(s0) + /* decode pin's iocmg reg offset address in base address, and conver value to point address */ + unsigned int iocmgBaseAddrValue = (uintptr_t)IOCMG_BASE; + 3005b1e: 147f07b7 lui a5,0x147f0 + 3005b22: fef42623 sw a5,-20(s0) + unsigned int iocmgRegOffsetAddrValue = (pinTypedef >> 16) & 0x00000FFF; /* 16 : shift 16 bit */ + 3005b26: fdc42783 lw a5,-36(s0) + 3005b2a: 0107d713 srli a4,a5,0x10 + 3005b2e: 6785 lui a5,0x1 + 3005b30: 17fd addi a5,a5,-1 # fff + 3005b32: 8ff9 and a5,a5,a4 + 3005b34: fef42423 sw a5,-24(s0) + IOCMG_REG* iocmgRegxAddr = (IOCMG_REG*)(void*)(iocmgBaseAddrValue + iocmgRegOffsetAddrValue); + 3005b38: fec42703 lw a4,-20(s0) + 3005b3c: fe842783 lw a5,-24(s0) + 3005b40: 97ba add a5,a5,a4 + 3005b42: fef42223 sw a5,-28(s0) + if (!IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegxAddr & IOCMG_BASE_ADDR_MASK))) { + 3005b46: fe442703 lw a4,-28(s0) + 3005b4a: 77c1 lui a5,0xffff0 + 3005b4c: 8f7d and a4,a4,a5 + 3005b4e: 147f07b7 lui a5,0x147f0 + 3005b52: 00f70463 beq a4,a5,3005b5a + return NULL; + 3005b56: 4781 li a5,0 + 3005b58: a019 j 3005b5e + } + return iocmgRegxAddr; + 3005b5a: fe442783 lw a5,-28(s0) +} + 3005b5e: 853e mv a0,a5 + 3005b60: 5432 lw s0,44(sp) + 3005b62: 6145 addi sp,sp,48 + 3005b64: 8082 ret + +03005b66 : + * @brief Set pins as function mode + * @param pinTypedef the pin type defined in iomap.h + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetPinAltFuncMode(unsigned int pinTypedef) +{ + 3005b66: 7179 addi sp,sp,-48 + 3005b68: d606 sw ra,44(sp) + 3005b6a: d422 sw s0,40(sp) + 3005b6c: 1800 addi s0,sp,48 + 3005b6e: fca42e23 sw a0,-36(s0) + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + 3005b72: fdc42503 lw a0,-36(s0) + 3005b76: 3f79 jal ra,3005b14 + 3005b78: fea42623 sw a0,-20(s0) + /* get iocmg reg default value */ + unsigned int regValue = pinTypedef & IOCMG_REG_VALUE_MASK; + 3005b7c: fdc42703 lw a4,-36(s0) + 3005b80: 67c1 lui a5,0x10 + 3005b82: 17fd addi a5,a5,-1 # ffff + 3005b84: 8ff9 and a5,a5,a4 + 3005b86: fef42423 sw a5,-24(s0) + DCL_IOCMG_SetRegValue(iocmgRegx, regValue); + 3005b8a: fe842583 lw a1,-24(s0) + 3005b8e: fec42503 lw a0,-20(s0) + 3005b92: 33a5 jal ra,30058fa + return IOCMG_STATUS_OK; + 3005b94: 4781 li a5,0 +} + 3005b96: 853e mv a0,a5 + 3005b98: 50b2 lw ra,44(sp) + 3005b9a: 5422 lw s0,40(sp) + 3005b9c: 6145 addi sp,sp,48 + 3005b9e: 8082 ret + +03005ba0 : + * @param pinTypedef the pin type defined in iomap.h + * @param pullMode function define as @ref IOCMG_PullMode + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetPinPullMode(unsigned int pinTypedef, IOCMG_PullMode pullMode) +{ + 3005ba0: 7179 addi sp,sp,-48 + 3005ba2: d606 sw ra,44(sp) + 3005ba4: d422 sw s0,40(sp) + 3005ba6: 1800 addi s0,sp,48 + 3005ba8: fca42e23 sw a0,-36(s0) + 3005bac: fcb42c23 sw a1,-40(s0) + IOCMG_PARAM_CHECK_WITH_RET(pullMode < PULL_MODE_MAX && pullMode >= PULL_NONE, IOCMG_PARAM_ERROR); + 3005bb0: fd842703 lw a4,-40(s0) + 3005bb4: 478d li a5,3 + 3005bb6: 00e7fb63 bgeu a5,a4,3005bcc + 3005bba: 07800593 li a1,120 + 3005bbe: 030097b7 lui a5,0x3009 + 3005bc2: a4c78513 addi a0,a5,-1460 # 3008a4c + 3005bc6: 3b05 jal ra,30058f6 + 3005bc8: 4791 li a5,4 + 3005bca: a821 j 3005be2 + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + 3005bcc: fdc42503 lw a0,-36(s0) + 3005bd0: 3791 jal ra,3005b14 + 3005bd2: fea42623 sw a0,-20(s0) + DCL_IOCMG_SetPullMode(iocmgRegx, pullMode); + 3005bd6: fd842583 lw a1,-40(s0) + 3005bda: fec42503 lw a0,-20(s0) + 3005bde: 33f9 jal ra,30059ac + return IOCMG_STATUS_OK; + 3005be0: 4781 li a5,0 +} + 3005be2: 853e mv a0,a5 + 3005be4: 50b2 lw ra,44(sp) + 3005be6: 5422 lw s0,40(sp) + 3005be8: 6145 addi sp,sp,48 + 3005bea: 8082 ret + +03005bec : + * @param pinTypedef the pin type defined in iomap.h + * @param schmidtMode function define as @ref IOCMG_SchmidtMode + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetPinSchmidtMode(unsigned int pinTypedef, IOCMG_SchmidtMode schmidtMode) +{ + 3005bec: 7179 addi sp,sp,-48 + 3005bee: d606 sw ra,44(sp) + 3005bf0: d422 sw s0,40(sp) + 3005bf2: 1800 addi s0,sp,48 + 3005bf4: fca42e23 sw a0,-36(s0) + 3005bf8: fcb42c23 sw a1,-40(s0) + IOCMG_PARAM_CHECK_WITH_RET(schmidtMode <= SCHMIDT_ENABLE && schmidtMode >= SCHMIDT_DISABLE, IOCMG_PARAM_ERROR); + 3005bfc: fd842703 lw a4,-40(s0) + 3005c00: 4785 li a5,1 + 3005c02: 00e7fb63 bgeu a5,a4,3005c18 + 3005c06: 09300593 li a1,147 + 3005c0a: 030097b7 lui a5,0x3009 + 3005c0e: a4c78513 addi a0,a5,-1460 # 3008a4c + 3005c12: 31d5 jal ra,30058f6 + 3005c14: 4791 li a5,4 + 3005c16: a821 j 3005c2e + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + 3005c18: fdc42503 lw a0,-36(s0) + 3005c1c: 3de5 jal ra,3005b14 + 3005c1e: fea42623 sw a0,-20(s0) + DCL_IOCMG_SetSchmidtMode(iocmgRegx, schmidtMode); + 3005c22: fd842583 lw a1,-40(s0) + 3005c26: fec42503 lw a0,-20(s0) + 3005c2a: 3db5 jal ra,3005aa6 + return IOCMG_STATUS_OK; + 3005c2c: 4781 li a5,0 +} + 3005c2e: 853e mv a0,a5 + 3005c30: 50b2 lw ra,44(sp) + 3005c32: 5422 lw s0,40(sp) + 3005c34: 6145 addi sp,sp,48 + 3005c36: 8082 ret + +03005c38 : + * @param pinTypedef the pin type defined in iomap.h + * @param schmidtMode function define as @ref IOCMG_SchmidtMode + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetPinLevelShiftRate(unsigned int pinTypedef, IOCMG_LevelShiftRate levelShiftRate) +{ + 3005c38: 7179 addi sp,sp,-48 + 3005c3a: d606 sw ra,44(sp) + 3005c3c: d422 sw s0,40(sp) + 3005c3e: 1800 addi s0,sp,48 + 3005c40: fca42e23 sw a0,-36(s0) + 3005c44: fcb42c23 sw a1,-40(s0) + IOCMG_PARAM_CHECK_WITH_RET(levelShiftRate < LEVEL_SHIFT_RATE_MAX, IOCMG_PARAM_ERROR); + 3005c48: fd842703 lw a4,-40(s0) + 3005c4c: 4785 li a5,1 + 3005c4e: 00e7fb63 bgeu a5,a4,3005c64 + 3005c52: 0ae00593 li a1,174 + 3005c56: 030097b7 lui a5,0x3009 + 3005c5a: a4c78513 addi a0,a5,-1460 # 3008a4c + 3005c5e: 3961 jal ra,30058f6 + 3005c60: 4791 li a5,4 + 3005c62: a821 j 3005c7a + IOCMG_PARAM_CHECK_WITH_RET(levelShiftRate >= LEVEL_SHIFT_RATE_FAST, IOCMG_PARAM_ERROR); + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + 3005c64: fdc42503 lw a0,-36(s0) + 3005c68: 3575 jal ra,3005b14 + 3005c6a: fea42623 sw a0,-20(s0) + DCL_IOCMG_SetLevelShiftRate(iocmgRegx, levelShiftRate); + 3005c6e: fd842583 lw a1,-40(s0) + 3005c72: fec42503 lw a0,-20(s0) + 3005c76: 33c9 jal ra,3005a38 + return IOCMG_STATUS_OK; + 3005c78: 4781 li a5,0 +} + 3005c7a: 853e mv a0,a5 + 3005c7c: 50b2 lw ra,44(sp) + 3005c7e: 5422 lw s0,40(sp) + 3005c80: 6145 addi sp,sp,48 + 3005c82: 8082 ret + +03005c84 : + * @param pinTypedef the pin type defined in iomap.h + * @param driveRate function define as @ref IOCMG_DriveRate + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetPinDriveRate(unsigned int pinTypedef, IOCMG_DriveRate driveRate) +{ + 3005c84: 7179 addi sp,sp,-48 + 3005c86: d606 sw ra,44(sp) + 3005c88: d422 sw s0,40(sp) + 3005c8a: 1800 addi s0,sp,48 + 3005c8c: fca42e23 sw a0,-36(s0) + 3005c90: fcb42c23 sw a1,-40(s0) + /* get iocmg reg address */ + IOCMG_PARAM_CHECK_WITH_RET(driveRate < DRIVER_RATE_MAX && driveRate >= DRIVER_RATE_4, IOCMG_PARAM_ERROR); + 3005c94: fd842703 lw a4,-40(s0) + 3005c98: 478d li a5,3 + 3005c9a: 00e7fb63 bgeu a5,a4,3005cb0 + 3005c9e: 0cb00593 li a1,203 + 3005ca2: 030097b7 lui a5,0x3009 + 3005ca6: a4c78513 addi a0,a5,-1460 # 3008a4c + 3005caa: 31b1 jal ra,30058f6 + 3005cac: 4791 li a5,4 + 3005cae: a821 j 3005cc6 + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + 3005cb0: fdc42503 lw a0,-36(s0) + 3005cb4: 3585 jal ra,3005b14 + 3005cb6: fea42623 sw a0,-20(s0) + DCL_IOCMG_SetDriveRate(iocmgRegx, driveRate); + 3005cba: fd842583 lw a1,-40(s0) + 3005cbe: fec42503 lw a0,-20(s0) + 3005cc2: 39b5 jal ra,300593e + return IOCMG_STATUS_OK; + 3005cc4: 4781 li a5,0 +} + 3005cc6: 853e mv a0,a5 + 3005cc8: 50b2 lw ra,44(sp) + 3005cca: 5422 lw s0,40(sp) + 3005ccc: 6145 addi sp,sp,48 + 3005cce: 8082 ret + +03005cd0 : + * @param mode Timer Mode, @ref TIMER_Mode + * @retval true + * @retval false + */ +static inline bool IsTimerMode(TIMER_Mode mode) +{ + 3005cd0: 1101 addi sp,sp,-32 + 3005cd2: ce22 sw s0,28(sp) + 3005cd4: 1000 addi s0,sp,32 + 3005cd6: fea42623 sw a0,-20(s0) + return (((mode) == TIMER_MODE_RUN_FREE) || + ((mode) == TIMER_MODE_RUN_PERIODIC) || + 3005cda: fec42783 lw a5,-20(s0) + 3005cde: cb99 beqz a5,3005cf4 + return (((mode) == TIMER_MODE_RUN_FREE) || + 3005ce0: fec42703 lw a4,-20(s0) + 3005ce4: 4785 li a5,1 + 3005ce6: 00f70763 beq a4,a5,3005cf4 + ((mode) == TIMER_MODE_RUN_PERIODIC) || + 3005cea: fec42703 lw a4,-20(s0) + 3005cee: 4789 li a5,2 + 3005cf0: 00f71463 bne a4,a5,3005cf8 + 3005cf4: 4785 li a5,1 + 3005cf6: a011 j 3005cfa + 3005cf8: 4781 li a5,0 + 3005cfa: 8b85 andi a5,a5,1 + 3005cfc: 9f81 uxtb a5 + ((mode) == TIMER_MODE_RUN_ONTSHOT)); +} + 3005cfe: 853e mv a0,a5 + 3005d00: 4472 lw s0,28(sp) + 3005d02: 6105 addi sp,sp,32 + 3005d04: 8082 ret + +03005d06 : + * @param mode Timer Interrupt Type, @ref TIMER_InterruptType + * @retval true + * @retval false + */ +static inline bool IsTimerInterruptType(TIMER_InterruptType interruptType) +{ + 3005d06: 1101 addi sp,sp,-32 + 3005d08: ce22 sw s0,28(sp) + 3005d0a: 1000 addi s0,sp,32 + 3005d0c: fea42623 sw a0,-20(s0) + return (((interruptType) == TIMER_PERIOD_FIN) || + 3005d10: fec42783 lw a5,-20(s0) + 3005d14: c791 beqz a5,3005d20 + 3005d16: fec42703 lw a4,-20(s0) + 3005d1a: 4785 li a5,1 + 3005d1c: 00f71463 bne a4,a5,3005d24 + 3005d20: 4785 li a5,1 + 3005d22: a011 j 3005d26 + 3005d24: 4781 li a5,0 + 3005d26: 8b85 andi a5,a5,1 + 3005d28: 9f81 uxtb a5 + ((interruptType) == TIMER_OVER_FLOW)); +} + 3005d2a: 853e mv a0,a5 + 3005d2c: 4472 lw s0,28(sp) + 3005d2e: 6105 addi sp,sp,32 + 3005d30: 8082 ret + +03005d32 : + * @param size Timer Size, @ref TIMER_Size + * @retval true + * @retval false + */ +static inline bool IsTimerSize(TIMER_Size size) +{ + 3005d32: 1101 addi sp,sp,-32 + 3005d34: ce22 sw s0,28(sp) + 3005d36: 1000 addi s0,sp,32 + 3005d38: fea42623 sw a0,-20(s0) + return (((size) == TIMER_SIZE_16BIT) || + 3005d3c: fec42783 lw a5,-20(s0) + 3005d40: c791 beqz a5,3005d4c + 3005d42: fec42703 lw a4,-20(s0) + 3005d46: 4785 li a5,1 + 3005d48: 00f71463 bne a4,a5,3005d50 + 3005d4c: 4785 li a5,1 + 3005d4e: a011 j 3005d52 + 3005d50: 4781 li a5,0 + 3005d52: 8b85 andi a5,a5,1 + 3005d54: 9f81 uxtb a5 + ((size) == TIMER_SIZE_32BIT)); +} + 3005d56: 853e mv a0,a5 + 3005d58: 4472 lw s0,28(sp) + 3005d5a: 6105 addi sp,sp,32 + 3005d5c: 8082 ret + +03005d5e : + * @param period + * @retval true + * @retval false + */ +static inline bool IsTimerPeriod(unsigned int period) +{ + 3005d5e: 1101 addi sp,sp,-32 + 3005d60: ce22 sw s0,28(sp) + 3005d62: 1000 addi s0,sp,32 + 3005d64: fea42623 sw a0,-20(s0) + return ((period) >= PERIOD_MIN_VALUE); + 3005d68: fec42783 lw a5,-20(s0) + 3005d6c: 00f037b3 snez a5,a5 + 3005d70: 9f81 uxtb a5 +} + 3005d72: 853e mv a0,a5 + 3005d74: 4472 lw s0,28(sp) + 3005d76: 6105 addi sp,sp,32 + 3005d78: 8082 ret + +03005d7a : + * @param div @see TIMER_PrescalerFactor + * @retval true + * @retval false + */ +static inline bool IsTimerDiv(TIMER_PrescalerFactor div) +{ + 3005d7a: 1101 addi sp,sp,-32 + 3005d7c: ce22 sw s0,28(sp) + 3005d7e: 1000 addi s0,sp,32 + 3005d80: fea42623 sw a0,-20(s0) + return (((div) == TIMERPRESCALER_NO_DIV) || + ((div) == TIMERPRESCALER_DIV_16) || + 3005d84: fec42783 lw a5,-20(s0) + 3005d88: cb99 beqz a5,3005d9e + return (((div) == TIMERPRESCALER_NO_DIV) || + 3005d8a: fec42703 lw a4,-20(s0) + 3005d8e: 4785 li a5,1 + 3005d90: 00f70763 beq a4,a5,3005d9e + ((div) == TIMERPRESCALER_DIV_16) || + 3005d94: fec42703 lw a4,-20(s0) + 3005d98: 4789 li a5,2 + 3005d9a: 00f71463 bne a4,a5,3005da2 + 3005d9e: 4785 li a5,1 + 3005da0: a011 j 3005da4 + 3005da2: 4781 li a5,0 + 3005da4: 8b85 andi a5,a5,1 + 3005da6: 9f81 uxtb a5 + ((div) == TIMERPRESCALER_DIV_256)); +} + 3005da8: 853e mv a0,a5 + 3005daa: 4472 lw s0,28(sp) + 3005dac: 6105 addi sp,sp,32 + 3005dae: 8082 ret + +03005db0 : + * @param handle Timer Handle + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR parameter check fail + */ +BASE_StatusType HAL_TIMER_Init(TIMER_Handle *handle) +{ + 3005db0: 1101 addi sp,sp,-32 + 3005db2: ce06 sw ra,28(sp) + 3005db4: cc22 sw s0,24(sp) + 3005db6: 1000 addi s0,sp,32 + 3005db8: fea42623 sw a0,-20(s0) + TIMER_ASSERT_PARAM(handle != NULL); + 3005dbc: fec42783 lw a5,-20(s0) + 3005dc0: eb89 bnez a5,3005dd2 + 3005dc2: 02800593 li a1,40 + 3005dc6: 030097b7 lui a5,0x3009 + 3005dca: a8c78513 addi a0,a5,-1396 # 3008a8c + 3005dce: 3625 jal ra,30058f6 + 3005dd0: a001 j 3005dd0 + TIMER_ASSERT_PARAM(IsTIMERInstance(handle->baseAddress)); + 3005dd2: fec42783 lw a5,-20(s0) + 3005dd6: 4398 lw a4,0(a5) + 3005dd8: 143007b7 lui a5,0x14300 + 3005ddc: 02f70f63 beq a4,a5,3005e1a + 3005de0: fec42783 lw a5,-20(s0) + 3005de4: 4398 lw a4,0(a5) + 3005de6: 143017b7 lui a5,0x14301 + 3005dea: 02f70863 beq a4,a5,3005e1a + 3005dee: fec42783 lw a5,-20(s0) + 3005df2: 4398 lw a4,0(a5) + 3005df4: 143027b7 lui a5,0x14302 + 3005df8: 02f70163 beq a4,a5,3005e1a + 3005dfc: fec42783 lw a5,-20(s0) + 3005e00: 4398 lw a4,0(a5) + 3005e02: 143037b7 lui a5,0x14303 + 3005e06: 00f70a63 beq a4,a5,3005e1a + 3005e0a: 02900593 li a1,41 + 3005e0e: 030097b7 lui a5,0x3009 + 3005e12: a8c78513 addi a0,a5,-1396 # 3008a8c + 3005e16: 34c5 jal ra,30058f6 + 3005e18: a001 j 3005e18 + + TIMER_PARAM_CHECK_WITH_RET(IsTimerPeriod(handle->load), BASE_STATUS_ERROR); + 3005e1a: fec42783 lw a5,-20(s0) + 3005e1e: 4bdc lw a5,20(a5) + 3005e20: 853e mv a0,a5 + 3005e22: 3f35 jal ra,3005d5e + 3005e24: 87aa mv a5,a0 + 3005e26: 0017c793 xori a5,a5,1 + 3005e2a: 9f81 uxtb a5 + 3005e2c: cb91 beqz a5,3005e40 + 3005e2e: 02b00593 li a1,43 + 3005e32: 030097b7 lui a5,0x3009 + 3005e36: a8c78513 addi a0,a5,-1396 # 3008a8c + 3005e3a: 3c75 jal ra,30058f6 + 3005e3c: 4785 li a5,1 + 3005e3e: aa6d j 3005ff8 + TIMER_PARAM_CHECK_WITH_RET(IsTimerPeriod(handle->bgLoad), BASE_STATUS_ERROR); + 3005e40: fec42783 lw a5,-20(s0) + 3005e44: 4f9c lw a5,24(a5) + 3005e46: 853e mv a0,a5 + 3005e48: 3f19 jal ra,3005d5e + 3005e4a: 87aa mv a5,a0 + 3005e4c: 0017c793 xori a5,a5,1 + 3005e50: 9f81 uxtb a5 + 3005e52: cb91 beqz a5,3005e66 + 3005e54: 02c00593 li a1,44 + 3005e58: 030097b7 lui a5,0x3009 + 3005e5c: a8c78513 addi a0,a5,-1396 # 3008a8c + 3005e60: 3c59 jal ra,30058f6 + 3005e62: 4785 li a5,1 + 3005e64: aa51 j 3005ff8 + TIMER_PARAM_CHECK_WITH_RET(IsTimerMode(handle->mode), BASE_STATUS_ERROR); + 3005e66: fec42783 lw a5,-20(s0) + 3005e6a: 479c lw a5,8(a5) + 3005e6c: 853e mv a0,a5 + 3005e6e: 358d jal ra,3005cd0 + 3005e70: 87aa mv a5,a0 + 3005e72: 0017c793 xori a5,a5,1 + 3005e76: 9f81 uxtb a5 + 3005e78: cb91 beqz a5,3005e8c + 3005e7a: 02d00593 li a1,45 + 3005e7e: 030097b7 lui a5,0x3009 + 3005e82: a8c78513 addi a0,a5,-1396 # 3008a8c + 3005e86: 3c85 jal ra,30058f6 + 3005e88: 4785 li a5,1 + 3005e8a: a2bd j 3005ff8 + TIMER_PARAM_CHECK_WITH_RET(IsTimerSize(handle->size), BASE_STATUS_ERROR); + 3005e8c: fec42783 lw a5,-20(s0) + 3005e90: 4b9c lw a5,16(a5) + 3005e92: 853e mv a0,a5 + 3005e94: 3d79 jal ra,3005d32 + 3005e96: 87aa mv a5,a0 + 3005e98: 0017c793 xori a5,a5,1 + 3005e9c: 9f81 uxtb a5 + 3005e9e: cb91 beqz a5,3005eb2 + 3005ea0: 02e00593 li a1,46 + 3005ea4: 030097b7 lui a5,0x3009 + 3005ea8: a8c78513 addi a0,a5,-1396 # 3008a8c + 3005eac: 34a9 jal ra,30058f6 + 3005eae: 4785 li a5,1 + 3005eb0: a2a1 j 3005ff8 + TIMER_PARAM_CHECK_WITH_RET(IsTimerDiv(handle->prescaler), BASE_STATUS_ERROR); + 3005eb2: fec42783 lw a5,-20(s0) + 3005eb6: 47dc lw a5,12(a5) + 3005eb8: 853e mv a0,a5 + 3005eba: 35c1 jal ra,3005d7a + 3005ebc: 87aa mv a5,a0 + 3005ebe: 0017c793 xori a5,a5,1 + 3005ec2: 9f81 uxtb a5 + 3005ec4: cb91 beqz a5,3005ed8 + 3005ec6: 02f00593 li a1,47 + 3005eca: 030097b7 lui a5,0x3009 + 3005ece: a8c78513 addi a0,a5,-1396 # 3008a8c + 3005ed2: 3415 jal ra,30058f6 + 3005ed4: 4785 li a5,1 + 3005ed6: a20d j 3005ff8 + + /* Initialize the configuration parameters of the timer */ + handle->baseAddress->timer_intclr = BASE_CFG_SET; /* Writing to this register clears interrupt output of timer */ + 3005ed8: fec42783 lw a5,-20(s0) + 3005edc: 439c lw a5,0(a5) + 3005ede: 4705 li a4,1 + 3005ee0: c7d8 sw a4,12(a5) + handle->baseAddress->timer_load = handle->load; + 3005ee2: fec42783 lw a5,-20(s0) + 3005ee6: 439c lw a5,0(a5) + 3005ee8: fec42703 lw a4,-20(s0) + 3005eec: 4b58 lw a4,20(a4) + 3005eee: c398 sw a4,0(a5) + handle->baseAddress->timerbgload = handle->bgLoad; + 3005ef0: fec42783 lw a5,-20(s0) + 3005ef4: 439c lw a5,0(a5) + 3005ef6: fec42703 lw a4,-20(s0) + 3005efa: 4f18 lw a4,24(a4) + 3005efc: cf98 sw a4,24(a5) + handle->baseAddress->TIMERx_CONTROL.BIT.timeren = BASE_CFG_DISABLE; + 3005efe: fec42783 lw a5,-20(s0) + 3005f02: 4398 lw a4,0(a5) + 3005f04: 471c lw a5,8(a4) + 3005f06: f7f7f793 andi a5,a5,-129 + 3005f0a: c71c sw a5,8(a4) + handle->baseAddress->TIMERx_CONTROL.BIT.timerintenable = handle->interruptEn; + 3005f0c: fec42783 lw a5,-20(s0) + 3005f10: 4398 lw a4,0(a5) + 3005f12: fec42783 lw a5,-20(s0) + 3005f16: 2fd4 lbu a3,28(a5) + 3005f18: 471c lw a5,8(a4) + 3005f1a: 8a85 andi a3,a3,1 + 3005f1c: 0696 slli a3,a3,0x5 + 3005f1e: fdf7f793 andi a5,a5,-33 + 3005f22: 8fd5 or a5,a5,a3 + 3005f24: c71c sw a5,8(a4) + + /* Sets the frequency divider and size of the timer module. */ + handle->baseAddress->TIMERx_CONTROL.BIT.timerpre = handle->prescaler; + 3005f26: fec42783 lw a5,-20(s0) + 3005f2a: 47d4 lw a3,12(a5) + 3005f2c: fec42783 lw a5,-20(s0) + 3005f30: 4398 lw a4,0(a5) + 3005f32: 87b6 mv a5,a3 + 3005f34: 8b8d andi a5,a5,3 + 3005f36: 0ff7f693 andi a3,a5,255 + 3005f3a: 471c lw a5,8(a4) + 3005f3c: 8a8d andi a3,a3,3 + 3005f3e: 068a slli a3,a3,0x2 + 3005f40: 9bcd andi a5,a5,-13 + 3005f42: 8fd5 or a5,a5,a3 + 3005f44: c71c sw a5,8(a4) + handle->baseAddress->TIMERx_CONTROL.BIT.timersize = handle->size; + 3005f46: fec42783 lw a5,-20(s0) + 3005f4a: 4b94 lw a3,16(a5) + 3005f4c: fec42783 lw a5,-20(s0) + 3005f50: 4398 lw a4,0(a5) + 3005f52: 87b6 mv a5,a3 + 3005f54: 8b85 andi a5,a5,1 + 3005f56: 0ff7f693 andi a3,a5,255 + 3005f5a: 471c lw a5,8(a4) + 3005f5c: 8a85 andi a3,a3,1 + 3005f5e: 0686 slli a3,a3,0x1 + 3005f60: 9bf5 andi a5,a5,-3 + 3005f62: 8fd5 or a5,a5,a3 + 3005f64: c71c sw a5,8(a4) + + /* Sets the running mode of the timer. */ + if (handle->mode == TIMER_MODE_RUN_ONTSHOT) { + 3005f66: fec42783 lw a5,-20(s0) + 3005f6a: 4798 lw a4,8(a5) + 3005f6c: 4789 li a5,2 + 3005f6e: 00f71a63 bne a4,a5,3005f82 + handle->baseAddress->TIMERx_CONTROL.BIT.oneshot = BASE_CFG_SET; + 3005f72: fec42783 lw a5,-20(s0) + 3005f76: 4398 lw a4,0(a5) + 3005f78: 471c lw a5,8(a4) + 3005f7a: 0017e793 ori a5,a5,1 + 3005f7e: c71c sw a5,8(a4) + 3005f80: a805 j 3005fb0 + } else { + handle->baseAddress->TIMERx_CONTROL.BIT.oneshot = BASE_CFG_UNSET; + 3005f82: fec42783 lw a5,-20(s0) + 3005f86: 4398 lw a4,0(a5) + 3005f88: 471c lw a5,8(a4) + 3005f8a: 9bf9 andi a5,a5,-2 + 3005f8c: c71c sw a5,8(a4) + handle->baseAddress->TIMERx_CONTROL.BIT.timermode = + (handle->mode == TIMER_MODE_RUN_FREE) ? BASE_CFG_UNSET : BASE_CFG_SET; + 3005f8e: fec42783 lw a5,-20(s0) + 3005f92: 479c lw a5,8(a5) + handle->baseAddress->TIMERx_CONTROL.BIT.timermode = + 3005f94: fec42703 lw a4,-20(s0) + 3005f98: 4318 lw a4,0(a4) + (handle->mode == TIMER_MODE_RUN_FREE) ? BASE_CFG_UNSET : BASE_CFG_SET; + 3005f9a: 00f037b3 snez a5,a5 + 3005f9e: 0ff7f693 andi a3,a5,255 + handle->baseAddress->TIMERx_CONTROL.BIT.timermode = + 3005fa2: 471c lw a5,8(a4) + 3005fa4: 8a85 andi a3,a3,1 + 3005fa6: 069a slli a3,a3,0x6 + 3005fa8: fbf7f793 andi a5,a5,-65 + 3005fac: 8fd5 or a5,a5,a3 + 3005fae: c71c sw a5,8(a4) + } + + /* Request for setting the DMA and ADC. */ + handle->baseAddress->TIMERx_CONTROLB.BIT.dmasreqen = handle->dmaReqEnable; + 3005fb0: fec42783 lw a5,-20(s0) + 3005fb4: 4398 lw a4,0(a5) + 3005fb6: fec42783 lw a5,-20(s0) + 3005fba: 2ff4 lbu a3,30(a5) + 3005fbc: 4f5c lw a5,28(a4) + 3005fbe: 8a85 andi a3,a3,1 + 3005fc0: 0686 slli a3,a3,0x1 + 3005fc2: 9bf5 andi a5,a5,-3 + 3005fc4: 8fd5 or a5,a5,a3 + 3005fc6: cf5c sw a5,28(a4) + handle->baseAddress->TIMERx_CONTROLB.BIT.dmabreqen = handle->dmaReqEnable; + 3005fc8: fec42783 lw a5,-20(s0) + 3005fcc: 4398 lw a4,0(a5) + 3005fce: fec42783 lw a5,-20(s0) + 3005fd2: 2ff4 lbu a3,30(a5) + 3005fd4: 4f5c lw a5,28(a4) + 3005fd6: 8a85 andi a3,a3,1 + 3005fd8: 9bf9 andi a5,a5,-2 + 3005fda: 8fd5 or a5,a5,a3 + 3005fdc: cf5c sw a5,28(a4) + handle->baseAddress->TIMERx_CONTROLB.BIT.socen = handle->adcSocReqEnable; + 3005fde: fec42783 lw a5,-20(s0) + 3005fe2: 4398 lw a4,0(a5) + 3005fe4: fec42783 lw a5,-20(s0) + 3005fe8: 3fd4 lbu a3,29(a5) + 3005fea: 4f5c lw a5,28(a4) + 3005fec: 8a85 andi a3,a3,1 + 3005fee: 068a slli a3,a3,0x2 + 3005ff0: 9bed andi a5,a5,-5 + 3005ff2: 8fd5 or a5,a5,a3 + 3005ff4: cf5c sw a5,28(a4) + return BASE_STATUS_OK; + 3005ff6: 4781 li a5,0 +} + 3005ff8: 853e mv a0,a5 + 3005ffa: 40f2 lw ra,28(sp) + 3005ffc: 4462 lw s0,24(sp) + 3005ffe: 6105 addi sp,sp,32 + 3006000: 8082 ret + +03006002 : + * @brief Start timer. + * @param handle Timer Handle + * @retval None + */ +void HAL_TIMER_Start(TIMER_Handle *handle) +{ + 3006002: 1101 addi sp,sp,-32 + 3006004: ce06 sw ra,28(sp) + 3006006: cc22 sw s0,24(sp) + 3006008: 1000 addi s0,sp,32 + 300600a: fea42623 sw a0,-20(s0) + TIMER_ASSERT_PARAM(handle != NULL); + 300600e: fec42783 lw a5,-20(s0) + 3006012: eb89 bnez a5,3006024 + 3006014: 0bc00593 li a1,188 + 3006018: 030097b7 lui a5,0x3009 + 300601c: a8c78513 addi a0,a5,-1396 # 3008a8c + 3006020: 22c5 jal ra,3006200 + 3006022: a001 j 3006022 + TIMER_ASSERT_PARAM(IsTIMERInstance(handle->baseAddress)); + 3006024: fec42783 lw a5,-20(s0) + 3006028: 4398 lw a4,0(a5) + 300602a: 143007b7 lui a5,0x14300 + 300602e: 02f70f63 beq a4,a5,300606c + 3006032: fec42783 lw a5,-20(s0) + 3006036: 4398 lw a4,0(a5) + 3006038: 143017b7 lui a5,0x14301 + 300603c: 02f70863 beq a4,a5,300606c + 3006040: fec42783 lw a5,-20(s0) + 3006044: 4398 lw a4,0(a5) + 3006046: 143027b7 lui a5,0x14302 + 300604a: 02f70163 beq a4,a5,300606c + 300604e: fec42783 lw a5,-20(s0) + 3006052: 4398 lw a4,0(a5) + 3006054: 143037b7 lui a5,0x14303 + 3006058: 00f70a63 beq a4,a5,300606c + 300605c: 0bd00593 li a1,189 + 3006060: 030097b7 lui a5,0x3009 + 3006064: a8c78513 addi a0,a5,-1396 # 3008a8c + 3006068: 2a61 jal ra,3006200 + 300606a: a001 j 300606a + /* Enable timer */ + handle->baseAddress->TIMERx_CONTROL.BIT.timeren = BASE_CFG_SET; + 300606c: fec42783 lw a5,-20(s0) + 3006070: 4398 lw a4,0(a5) + 3006072: 471c lw a5,8(a4) + 3006074: 0807e793 ori a5,a5,128 + 3006078: c71c sw a5,8(a4) +} + 300607a: 0001 nop + 300607c: 40f2 lw ra,28(sp) + 300607e: 4462 lw s0,24(sp) + 3006080: 6105 addi sp,sp,32 + 3006082: 8082 ret + +03006084 : + * @brief GPT Interrupt service processing function. + * @param handle TIMER Handle + * @retval None + */ +void HAL_TIMER_IrqHandler(void *handle) +{ + 3006084: 7179 addi sp,sp,-48 + 3006086: d606 sw ra,44(sp) + 3006088: d422 sw s0,40(sp) + 300608a: 1800 addi s0,sp,48 + 300608c: fca42e23 sw a0,-36(s0) + TIMER_ASSERT_PARAM(handle != NULL); + 3006090: fdc42783 lw a5,-36(s0) + 3006094: eb89 bnez a5,30060a6 + 3006096: 0d800593 li a1,216 + 300609a: 030097b7 lui a5,0x3009 + 300609e: a8c78513 addi a0,a5,-1396 # 3008a8c + 30060a2: 2ab9 jal ra,3006200 + 30060a4: a001 j 30060a4 + TIMER_Handle *timerHandle = (TIMER_Handle *)handle; + 30060a6: fdc42783 lw a5,-36(s0) + 30060aa: fef42623 sw a5,-20(s0) + TIMER_ASSERT_PARAM(IsTIMERInstance(timerHandle->baseAddress)); + 30060ae: fec42783 lw a5,-20(s0) + 30060b2: 4398 lw a4,0(a5) + 30060b4: 143007b7 lui a5,0x14300 + 30060b8: 02f70f63 beq a4,a5,30060f6 + 30060bc: fec42783 lw a5,-20(s0) + 30060c0: 4398 lw a4,0(a5) + 30060c2: 143017b7 lui a5,0x14301 + 30060c6: 02f70863 beq a4,a5,30060f6 + 30060ca: fec42783 lw a5,-20(s0) + 30060ce: 4398 lw a4,0(a5) + 30060d0: 143027b7 lui a5,0x14302 + 30060d4: 02f70163 beq a4,a5,30060f6 + 30060d8: fec42783 lw a5,-20(s0) + 30060dc: 4398 lw a4,0(a5) + 30060de: 143037b7 lui a5,0x14303 + 30060e2: 00f70a63 beq a4,a5,30060f6 + 30060e6: 0da00593 li a1,218 + 30060ea: 030097b7 lui a5,0x3009 + 30060ee: a8c78513 addi a0,a5,-1396 # 3008a8c + 30060f2: 2239 jal ra,3006200 + 30060f4: a001 j 30060f4 + /* Check interrupt type */ + if (timerHandle->baseAddress->TIMERx_MIS.dmaovmis == BASE_CFG_ENABLE) { + 30060f6: fec42783 lw a5,-20(s0) + 30060fa: 439c lw a5,0(a5) + 30060fc: 4bdc lw a5,20(a5) + 30060fe: 8385 srli a5,a5,0x1 + 3006100: 8b85 andi a5,a5,1 + 3006102: 0ff7f713 andi a4,a5,255 + 3006106: 4785 li a5,1 + 3006108: 02f71363 bne a4,a5,300612e + /* DMA overflow interrupt */ + timerHandle->baseAddress->DMAOV_INTCLR.BIT.dmaov_intclr = BASE_CFG_ENABLE; + 300610c: fec42783 lw a5,-20(s0) + 3006110: 4398 lw a4,0(a5) + 3006112: 531c lw a5,32(a4) + 3006114: 0017e793 ori a5,a5,1 + 3006118: d31c sw a5,32(a4) + /* Call the timer DMA request overflow callback function of the user. */ + if (timerHandle->userCallBack.TimerOverFlowCallBack != NULL) { + 300611a: fec42783 lw a5,-20(s0) + 300611e: 53dc lw a5,36(a5) + 3006120: c799 beqz a5,300612e + timerHandle->userCallBack.TimerOverFlowCallBack(timerHandle); + 3006122: fec42783 lw a5,-20(s0) + 3006126: 53dc lw a5,36(a5) + 3006128: fec42503 lw a0,-20(s0) + 300612c: 9782 jalr a5 + } + } + if (timerHandle->baseAddress->TIMERx_MIS.timermis == BASE_CFG_ENABLE) { + 300612e: fec42783 lw a5,-20(s0) + 3006132: 439c lw a5,0(a5) + 3006134: 4bdc lw a5,20(a5) + 3006136: 8b85 andi a5,a5,1 + 3006138: 0ff7f713 andi a4,a5,255 + 300613c: 4785 li a5,1 + 300613e: 02f71263 bne a4,a5,3006162 + /* TIMER Interrupt */ + timerHandle->baseAddress->timer_intclr = BASE_CFG_ENABLE; + 3006142: fec42783 lw a5,-20(s0) + 3006146: 439c lw a5,0(a5) + 3006148: 4705 li a4,1 + 300614a: c7d8 sw a4,12(a5) + /* Call the period finish callback function of the user. */ + if (timerHandle->userCallBack.TimerPeriodFinCallBack != NULL) { + 300614c: fec42783 lw a5,-20(s0) + 3006150: 539c lw a5,32(a5) + 3006152: cb81 beqz a5,3006162 + timerHandle->userCallBack.TimerPeriodFinCallBack(timerHandle); + 3006154: fec42783 lw a5,-20(s0) + 3006158: 539c lw a5,32(a5) + 300615a: fec42503 lw a0,-20(s0) + 300615e: 9782 jalr a5 + } + } + return; + 3006160: 0001 nop + 3006162: 0001 nop +} + 3006164: 50b2 lw ra,44(sp) + 3006166: 5422 lw s0,40(sp) + 3006168: 6145 addi sp,sp,48 + 300616a: 8082 ret + +0300616c : + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Parameter check fail + */ +BASE_StatusType HAL_TIMER_RegisterCallback(TIMER_Handle *handle, TIMER_InterruptType typeID, + TIMER_CallBackFunc callBackFunc) +{ + 300616c: 1101 addi sp,sp,-32 + 300616e: ce06 sw ra,28(sp) + 3006170: cc22 sw s0,24(sp) + 3006172: 1000 addi s0,sp,32 + 3006174: fea42623 sw a0,-20(s0) + 3006178: feb42423 sw a1,-24(s0) + 300617c: fec42223 sw a2,-28(s0) + TIMER_ASSERT_PARAM(handle != NULL); + 3006180: fec42783 lw a5,-20(s0) + 3006184: eb89 bnez a5,3006196 + 3006186: 0fa00593 li a1,250 + 300618a: 030097b7 lui a5,0x3009 + 300618e: a8c78513 addi a0,a5,-1396 # 3008a8c + 3006192: 20bd jal ra,3006200 + 3006194: a001 j 3006194 + TIMER_ASSERT_PARAM(callBackFunc != NULL); + 3006196: fe442783 lw a5,-28(s0) + 300619a: eb89 bnez a5,30061ac + 300619c: 0fb00593 li a1,251 + 30061a0: 030097b7 lui a5,0x3009 + 30061a4: a8c78513 addi a0,a5,-1396 # 3008a8c + 30061a8: 28a1 jal ra,3006200 + 30061aa: a001 j 30061aa + TIMER_ASSERT_PARAM(IsTimerInterruptType(typeID)); + 30061ac: fe842503 lw a0,-24(s0) + 30061b0: 3e99 jal ra,3005d06 + 30061b2: 87aa mv a5,a0 + 30061b4: 0017c793 xori a5,a5,1 + 30061b8: 9f81 uxtb a5 + 30061ba: cb89 beqz a5,30061cc + 30061bc: 0fc00593 li a1,252 + 30061c0: 030097b7 lui a5,0x3009 + 30061c4: a8c78513 addi a0,a5,-1396 # 3008a8c + 30061c8: 2825 jal ra,3006200 + 30061ca: a001 j 30061ca + + /* Registers the user callback function. */ + switch (typeID) { + 30061cc: fe842783 lw a5,-24(s0) + 30061d0: cb91 beqz a5,30061e4 + 30061d2: 4705 li a4,1 + 30061d4: 00e79e63 bne a5,a4,30061f0 + case TIMER_OVER_FLOW: + handle->userCallBack.TimerOverFlowCallBack = callBackFunc; /* User DMA request overflow function */ + 30061d8: fec42783 lw a5,-20(s0) + 30061dc: fe442703 lw a4,-28(s0) + 30061e0: d3d8 sw a4,36(a5) + break; + 30061e2: a809 j 30061f4 + case TIMER_PERIOD_FIN: + handle->userCallBack.TimerPeriodFinCallBack = callBackFunc; /* User timer period finish call back. */ + 30061e4: fec42783 lw a5,-20(s0) + 30061e8: fe442703 lw a4,-28(s0) + 30061ec: d398 sw a4,32(a5) + break; + 30061ee: a019 j 30061f4 + default: + return BASE_STATUS_ERROR; + 30061f0: 4785 li a5,1 + 30061f2: a011 j 30061f6 + } + return BASE_STATUS_OK; + 30061f4: 4781 li a5,0 +} + 30061f6: 853e mv a0,a5 + 30061f8: 40f2 lw ra,28(sp) + 30061fa: 4462 lw s0,24(sp) + 30061fc: 6105 addi sp,sp,32 + 30061fe: 8082 ret + +03006200 : + 3006200: 808fb06f j 3001208 + +03006204 : + * @brief Check UART datalength parameter. + * @param datalength The number of data bits in a frame, @ref UART_DataLength + * @retval bool + */ +static inline bool IsUartDatalength(UART_DataLength datalength) +{ + 3006204: 1101 addi sp,sp,-32 + 3006206: ce22 sw s0,28(sp) + 3006208: 1000 addi s0,sp,32 + 300620a: fea42623 sw a0,-20(s0) + return (datalength >= UART_DATALENGTH_5BIT) && (datalength <= UART_DATALENGTH_8BIT); + 300620e: fec42783 lw a5,-20(s0) + 3006212: 0047b793 sltiu a5,a5,4 + 3006216: 9f81 uxtb a5 +} + 3006218: 853e mv a0,a5 + 300621a: 4472 lw s0,28(sp) + 300621c: 6105 addi sp,sp,32 + 300621e: 8082 ret + +03006220 : + * @brief Check UART stopbits parameter. + * @param stopbits The number of stop bits in a frame, @ref UART_StopBits + * @retval bool + */ +static inline bool IsUartStopbits(UART_StopBits stopbits) +{ + 3006220: 1101 addi sp,sp,-32 + 3006222: ce22 sw s0,28(sp) + 3006224: 1000 addi s0,sp,32 + 3006226: fea42623 sw a0,-20(s0) + return (stopbits == UART_STOPBITS_ONE) || (stopbits == UART_STOPBITS_TWO); + 300622a: fec42783 lw a5,-20(s0) + 300622e: c791 beqz a5,300623a + 3006230: fec42703 lw a4,-20(s0) + 3006234: 4785 li a5,1 + 3006236: 00f71463 bne a4,a5,300623e + 300623a: 4785 li a5,1 + 300623c: a011 j 3006240 + 300623e: 4781 li a5,0 + 3006240: 8b85 andi a5,a5,1 + 3006242: 9f81 uxtb a5 +} + 3006244: 853e mv a0,a5 + 3006246: 4472 lw s0,28(sp) + 3006248: 6105 addi sp,sp,32 + 300624a: 8082 ret + +0300624c : + * @brief Check UART paritymode parameter. + * @param paritymode UART parity check mode, @ref UART_Parity_Mode + * @retval bool + */ +static inline bool IsUartParitymode(UART_Parity_Mode paritymode) +{ + 300624c: 1101 addi sp,sp,-32 + 300624e: ce22 sw s0,28(sp) + 3006250: 1000 addi s0,sp,32 + 3006252: fea42623 sw a0,-20(s0) + if ((paritymode >= UART_PARITY_ODD) && (paritymode <= UART_PARITY_NONE)) { + 3006256: fec42703 lw a4,-20(s0) + 300625a: 4791 li a5,4 + 300625c: 00e7e463 bltu a5,a4,3006264 + return true; + 3006260: 4785 li a5,1 + 3006262: a011 j 3006266 + } + return false; + 3006264: 4781 li a5,0 +} + 3006266: 853e mv a0,a5 + 3006268: 4472 lw s0,28(sp) + 300626a: 6105 addi sp,sp,32 + 300626c: 8082 ret + +0300626e : + * @brief Check UART transmode parameter. + * @param transmode Transmit mode, @ref UART_Transmit_Mode + * @retval bool + */ +static inline bool IsUartTransmode(UART_Transmit_Mode transmode) +{ + 300626e: 1101 addi sp,sp,-32 + 3006270: ce22 sw s0,28(sp) + 3006272: 1000 addi s0,sp,32 + 3006274: fea42623 sw a0,-20(s0) + if ((transmode == UART_MODE_BLOCKING) || + 3006278: fec42783 lw a5,-20(s0) + 300627c: c385 beqz a5,300629c + 300627e: fec42703 lw a4,-20(s0) + 3006282: 4785 li a5,1 + 3006284: 00f70c63 beq a4,a5,300629c + (transmode == UART_MODE_INTERRUPT) || + 3006288: fec42703 lw a4,-20(s0) + 300628c: 4789 li a5,2 + 300628e: 00f70763 beq a4,a5,300629c + (transmode == UART_MODE_DMA) || + 3006292: fec42703 lw a4,-20(s0) + 3006296: 478d li a5,3 + 3006298: 00f71463 bne a4,a5,30062a0 + (transmode == UART_MODE_DISABLE)) { + return true; + 300629c: 4785 li a5,1 + 300629e: a011 j 30062a2 + } + return false; + 30062a0: 4781 li a5,0 +} + 30062a2: 853e mv a0,a5 + 30062a4: 4472 lw s0,28(sp) + 30062a6: 6105 addi sp,sp,32 + 30062a8: 8082 ret + +030062aa : + * @brief Check UART fifoThreshold parameter. + * @param fifoThreshold UART TX/RX FIFO line interrupt threshold, @ref UART_FIFO_Threshold + * @retval bool + */ +static inline bool IsUartFIFOThreshold(UART_FIFO_Threshold fifoThreshold) +{ + 30062aa: 1101 addi sp,sp,-32 + 30062ac: ce22 sw s0,28(sp) + 30062ae: 1000 addi s0,sp,32 + 30062b0: fea42623 sw a0,-20(s0) + return (fifoThreshold >= UART_FIFODEPTH_SIZE0) && (fifoThreshold <= UART_FIFODEPTH_SIZE15); + 30062b4: fec42783 lw a5,-20(s0) + 30062b8: 0107b793 sltiu a5,a5,16 + 30062bc: 9f81 uxtb a5 +} + 30062be: 853e mv a0,a5 + 30062c0: 4472 lw s0,28(sp) + 30062c2: 6105 addi sp,sp,32 + 30062c4: 8082 ret + +030062c6 : + * @brief Check UART Oversampling multiple. + * @param multiple Oversampling multiple, @ref UART_OversampleMultiple + * @retval bool + */ +static inline bool IsUartOversampleMultiple(UART_OversampleMultiple multiple) +{ + 30062c6: 1101 addi sp,sp,-32 + 30062c8: ce22 sw s0,28(sp) + 30062ca: 1000 addi s0,sp,32 + 30062cc: fea42623 sw a0,-20(s0) + return (multiple >= UART_OVERSAMPLING_16X) && (multiple <= UART_OVERSAMPLING_12X); + 30062d0: fec42783 lw a5,-20(s0) + 30062d4: 0057b793 sltiu a5,a5,5 + 30062d8: 9f81 uxtb a5 +} + 30062da: 853e mv a0,a5 + 30062dc: 4472 lw s0,28(sp) + 30062de: 6105 addi sp,sp,32 + 30062e0: 8082 ret + +030062e2 : +#define PARITY_EVEN 0x6 +#define PARITY_MARK 0x82 +#define PARITY_SPACE 0x86 + +static unsigned int DivClosest(unsigned int x, unsigned int divisor) +{ + 30062e2: 7179 addi sp,sp,-48 + 30062e4: d622 sw s0,44(sp) + 30062e6: 1800 addi s0,sp,48 + 30062e8: fca42e23 sw a0,-36(s0) + 30062ec: fcb42c23 sw a1,-40(s0) + unsigned int ret; + if (divisor == 0) { + 30062f0: fd842783 lw a5,-40(s0) + 30062f4: e399 bnez a5,30062fa + return 0; + 30062f6: 4781 li a5,0 + 30062f8: a005 j 3006318 + } + ret = (((x) + ((divisor) / 2)) / (divisor)); /* Round up the result, add 1/2 */ + 30062fa: fd842783 lw a5,-40(s0) + 30062fe: 0017d713 srli a4,a5,0x1 + 3006302: fdc42783 lw a5,-36(s0) + 3006306: 973e add a4,a4,a5 + 3006308: fd842783 lw a5,-40(s0) + 300630c: 02f757b3 divu a5,a4,a5 + 3006310: fef42623 sw a5,-20(s0) + return ret; + 3006314: fec42783 lw a5,-20(s0) +} + 3006318: 853e mv a0,a5 + 300631a: 5432 lw s0,44(sp) + 300631c: 6145 addi sp,sp,48 + 300631e: 8082 ret + +03006320 : + * @brief Baud rate detection interrupt callback function. + * @param uartHandle UART handle. + * @retval None. + */ +static void BaudDetectCallBack(UART_Handle *uartHandle) +{ + 3006320: 1101 addi sp,sp,-32 + 3006322: ce06 sw ra,28(sp) + 3006324: cc22 sw s0,24(sp) + 3006326: 1000 addi s0,sp,32 + 3006328: fea42623 sw a0,-20(s0) + if (uartHandle->baseAddress->UART_MIS.BIT.abdcis == 0x01) { + 300632c: fec42783 lw a5,-20(s0) + 3006330: 439c lw a5,0(a5) + 3006332: 43bc lw a5,64(a5) + 3006334: 83cd srli a5,a5,0x13 + 3006336: 8b85 andi a5,a5,1 + 3006338: 0ff7f713 andi a4,a5,255 + 300633c: 4785 li a5,1 + 300633e: 06f71b63 bne a4,a5,30063b4 + uartHandle->baseAddress->UART_ABDEN.BIT.abden = BASE_CFG_DISABLE; + 3006342: fec42783 lw a5,-20(s0) + 3006346: 4398 lw a4,0(a5) + 3006348: 4f7c lw a5,92(a4) + 300634a: 9bf9 andi a5,a5,-2 + 300634c: cf7c sw a5,92(a4) + uartHandle->baseAddress->UART_IMSC.BIT.abdeim = BASE_CFG_DISABLE; + 300634e: fec42783 lw a5,-20(s0) + 3006352: 4398 lw a4,0(a5) + 3006354: 5f1c lw a5,56(a4) + 3006356: fff006b7 lui a3,0xfff00 + 300635a: 16fd addi a3,a3,-1 # ffefffff + 300635c: 8ff5 and a5,a5,a3 + 300635e: df1c sw a5,56(a4) + uartHandle->baseAddress->UART_IMSC.BIT.abdcim = BASE_CFG_DISABLE; + 3006360: fec42783 lw a5,-20(s0) + 3006364: 4398 lw a4,0(a5) + 3006366: 5f1c lw a5,56(a4) + 3006368: fff806b7 lui a3,0xfff80 + 300636c: 16fd addi a3,a3,-1 # fff7ffff + 300636e: 8ff5 and a5,a5,a3 + 3006370: df1c sw a5,56(a4) + uartHandle->baseAddress->UART_ICR.BIT.abdcic = BASE_CFG_ENABLE; + 3006372: fec42783 lw a5,-20(s0) + 3006376: 4398 lw a4,0(a5) + 3006378: 437c lw a5,68(a4) + 300637a: 000806b7 lui a3,0x80 + 300637e: 8fd5 or a5,a5,a3 + 3006380: c37c sw a5,68(a4) + /* After the baud rate automatic detection function is configured, enable UART. */ + uartHandle->baseAddress->UART_CR.BIT.txe = BASE_CFG_ENABLE; + 3006382: fec42783 lw a5,-20(s0) + 3006386: 4398 lw a4,0(a5) + 3006388: 5b1c lw a5,48(a4) + 300638a: 1007e793 ori a5,a5,256 + 300638e: db1c sw a5,48(a4) + uartHandle->baseAddress->UART_CR.BIT.rxe = BASE_CFG_ENABLE; + 3006390: fec42783 lw a5,-20(s0) + 3006394: 4398 lw a4,0(a5) + 3006396: 5b1c lw a5,48(a4) + 3006398: 2007e793 ori a5,a5,512 + 300639c: db1c sw a5,48(a4) + /* Call back user detect success function. */ + if (uartHandle->userCallBack.BaudDetectSuccessCallBack != NULL) { + 300639e: fec42783 lw a5,-20(s0) + 30063a2: 57fc lw a5,108(a5) + 30063a4: c7b9 beqz a5,30063f2 + uartHandle->userCallBack.BaudDetectSuccessCallBack(uartHandle); + 30063a6: fec42783 lw a5,-20(s0) + 30063aa: 57fc lw a5,108(a5) + 30063ac: fec42503 lw a0,-20(s0) + 30063b0: 9782 jalr a5 + /* Call back user baud detect error function. */ + if (uartHandle->userCallBack.BaudDetectErrorCallBack != NULL) { + uartHandle->userCallBack.BaudDetectErrorCallBack(uartHandle); + } + } + return; + 30063b2: a081 j 30063f2 + while (uartHandle->baseAddress->UART_ABDEN.BIT.abdbusy == 0x01) { + 30063b4: 0001 nop + 30063b6: fec42783 lw a5,-20(s0) + 30063ba: 439c lw a5,0(a5) + 30063bc: 4ffc lw a5,92(a5) + 30063be: 8391 srli a5,a5,0x4 + 30063c0: 8b85 andi a5,a5,1 + 30063c2: 0ff7f713 andi a4,a5,255 + 30063c6: 4785 li a5,1 + 30063c8: fef707e3 beq a4,a5,30063b6 + uartHandle->baseAddress->UART_ICR.BIT.abdeic = BASE_CFG_ENABLE; + 30063cc: fec42783 lw a5,-20(s0) + 30063d0: 4398 lw a4,0(a5) + 30063d2: 437c lw a5,68(a4) + 30063d4: 001006b7 lui a3,0x100 + 30063d8: 8fd5 or a5,a5,a3 + 30063da: c37c sw a5,68(a4) + if (uartHandle->userCallBack.BaudDetectErrorCallBack != NULL) { + 30063dc: fec42783 lw a5,-20(s0) + 30063e0: 5bbc lw a5,112(a5) + 30063e2: cb81 beqz a5,30063f2 + uartHandle->userCallBack.BaudDetectErrorCallBack(uartHandle); + 30063e4: fec42783 lw a5,-20(s0) + 30063e8: 5bbc lw a5,112(a5) + 30063ea: fec42503 lw a0,-20(s0) + 30063ee: 9782 jalr a5 + return; + 30063f0: 0001 nop + 30063f2: 0001 nop +} + 30063f4: 40f2 lw ra,28(sp) + 30063f6: 4462 lw s0,24(sp) + 30063f8: 6105 addi sp,sp,32 + 30063fa: 8082 ret + +030063fc : + * @brief Character detection interrupt callback function. + * @param uartHandle UART handle. + * @retval None. + */ +static void CharterMatchCallBack(UART_Handle *uartHandle) +{ + 30063fc: 1101 addi sp,sp,-32 + 30063fe: ce06 sw ra,28(sp) + 3006400: cc22 sw s0,24(sp) + 3006402: 1000 addi s0,sp,32 + 3006404: fea42623 sw a0,-20(s0) + uartHandle->baseAddress->UART_IMSC.BIT.cmim = BASE_CFG_DISABLE; + 3006408: fec42783 lw a5,-20(s0) + 300640c: 4398 lw a4,0(a5) + 300640e: 5f1c lw a5,56(a4) + 3006410: ffe006b7 lui a3,0xffe00 + 3006414: 16fd addi a3,a3,-1 # ffdfffff + 3006416: 8ff5 and a5,a5,a3 + 3006418: df1c sw a5,56(a4) + uartHandle->baseAddress->UART_ICR.BIT.cmic = BASE_CFG_ENABLE; + 300641a: fec42783 lw a5,-20(s0) + 300641e: 4398 lw a4,0(a5) + 3006420: 437c lw a5,68(a4) + 3006422: 002006b7 lui a3,0x200 + 3006426: 8fd5 or a5,a5,a3 + 3006428: c37c sw a5,68(a4) + if (uartHandle->userCallBack.CharacterMatchCallBack != NULL) { + 300642a: fec42783 lw a5,-20(s0) + 300642e: 5bfc lw a5,116(a5) + 3006430: c799 beqz a5,300643e + uartHandle->userCallBack.CharacterMatchCallBack(uartHandle); + 3006432: fec42783 lw a5,-20(s0) + 3006436: 5bfc lw a5,116(a5) + 3006438: fec42503 lw a0,-20(s0) + 300643c: 9782 jalr a5 + } +} + 300643e: 0001 nop + 3006440: 40f2 lw ra,28(sp) + 3006442: 4462 lw s0,24(sp) + 3006444: 6105 addi sp,sp,32 + 3006446: 8082 ret + +03006448 : + * @brief Sets the parity bit of the UART. + * @param uartHandle UART handle. + * @retval None. + */ +static void UART_SetParityBit(UART_Handle *uartHandle) +{ + 3006448: 1101 addi sp,sp,-32 + 300644a: ce22 sw s0,28(sp) + 300644c: 1000 addi s0,sp,32 + 300644e: fea42623 sw a0,-20(s0) + /* Sets the UART check mode. */ + switch (uartHandle->parity) { + 3006452: fec42783 lw a5,-20(s0) + 3006456: 4b9c lw a5,16(a5) + 3006458: 4711 li a4,4 + 300645a: 06f76e63 bltu a4,a5,30064d6 + 300645e: 00279713 slli a4,a5,0x2 + 3006462: 030097b7 lui a5,0x3009 + 3006466: aac78793 addi a5,a5,-1364 # 3008aac + 300646a: 97ba add a5,a5,a4 + 300646c: 439c lw a5,0(a5) + 300646e: 8782 jr a5 + case UART_PARITY_ODD: + uartHandle->baseAddress->UART_LCR_H.reg |= PARITY_ODD; /* Odd parity. */ + 3006470: fec42783 lw a5,-20(s0) + 3006474: 439c lw a5,0(a5) + 3006476: 57d8 lw a4,44(a5) + 3006478: fec42783 lw a5,-20(s0) + 300647c: 439c lw a5,0(a5) + 300647e: 00276713 ori a4,a4,2 + 3006482: d7d8 sw a4,44(a5) + break; + 3006484: a891 j 30064d8 + case UART_PARITY_EVEN: + uartHandle->baseAddress->UART_LCR_H.reg |= PARITY_EVEN; /* Even parity. */ + 3006486: fec42783 lw a5,-20(s0) + 300648a: 439c lw a5,0(a5) + 300648c: 57d8 lw a4,44(a5) + 300648e: fec42783 lw a5,-20(s0) + 3006492: 439c lw a5,0(a5) + 3006494: 00676713 ori a4,a4,6 + 3006498: d7d8 sw a4,44(a5) + break; + 300649a: a83d j 30064d8 + case UART_PARITY_MARK: + uartHandle->baseAddress->UART_LCR_H.reg |= PARITY_MARK; /* Marking parity */ + 300649c: fec42783 lw a5,-20(s0) + 30064a0: 439c lw a5,0(a5) + 30064a2: 57d8 lw a4,44(a5) + 30064a4: fec42783 lw a5,-20(s0) + 30064a8: 439c lw a5,0(a5) + 30064aa: 08276713 ori a4,a4,130 + 30064ae: d7d8 sw a4,44(a5) + break; + 30064b0: a025 j 30064d8 + case UART_PARITY_SPACE: + uartHandle->baseAddress->UART_LCR_H.reg |= PARITY_SPACE; /* space parity */ + 30064b2: fec42783 lw a5,-20(s0) + 30064b6: 439c lw a5,0(a5) + 30064b8: 57d8 lw a4,44(a5) + 30064ba: fec42783 lw a5,-20(s0) + 30064be: 439c lw a5,0(a5) + 30064c0: 08676713 ori a4,a4,134 + 30064c4: d7d8 sw a4,44(a5) + break; + 30064c6: a809 j 30064d8 + case UART_PARITY_NONE: + uartHandle->baseAddress->UART_LCR_H.BIT.pen = BASE_CFG_DISABLE; /* No parity */ + 30064c8: fec42783 lw a5,-20(s0) + 30064cc: 4398 lw a4,0(a5) + 30064ce: 575c lw a5,44(a4) + 30064d0: 9bf5 andi a5,a5,-3 + 30064d2: d75c sw a5,44(a4) + break; + 30064d4: a011 j 30064d8 + default: + return; + 30064d6: 0001 nop + } +} + 30064d8: 4472 lw s0,28(sp) + 30064da: 6105 addi sp,sp,32 + 30064dc: 8082 ret + +030064de : + * @brief Initialize the UART hardware configuration and configure parameters based on the specified handle. + * @param uartHandle UART handle. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_UART_Init(UART_Handle *uartHandle) +{ + 30064de: 7179 addi sp,sp,-48 + 30064e0: d606 sw ra,44(sp) + 30064e2: d422 sw s0,40(sp) + 30064e4: 1800 addi s0,sp,48 + 30064e6: fca42e23 sw a0,-36(s0) + UART_ASSERT_PARAM(uartHandle != NULL); + 30064ea: fdc42783 lw a5,-36(s0) + 30064ee: eb89 bnez a5,3006500 + 30064f0: 09700593 li a1,151 + 30064f4: 030097b7 lui a5,0x3009 + 30064f8: ac078513 addi a0,a5,-1344 # 3008ac0 + 30064fc: 3311 jal ra,3006200 + 30064fe: a001 j 30064fe + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + 3006500: fdc42783 lw a5,-36(s0) + 3006504: 4398 lw a4,0(a5) + 3006506: 140007b7 lui a5,0x14000 + 300650a: 02f70f63 beq a4,a5,3006548 + 300650e: fdc42783 lw a5,-36(s0) + 3006512: 4398 lw a4,0(a5) + 3006514: 140017b7 lui a5,0x14001 + 3006518: 02f70863 beq a4,a5,3006548 + 300651c: fdc42783 lw a5,-36(s0) + 3006520: 4398 lw a4,0(a5) + 3006522: 140027b7 lui a5,0x14002 + 3006526: 02f70163 beq a4,a5,3006548 + 300652a: fdc42783 lw a5,-36(s0) + 300652e: 4398 lw a4,0(a5) + 3006530: 140037b7 lui a5,0x14003 + 3006534: 00f70a63 beq a4,a5,3006548 + 3006538: 09800593 li a1,152 + 300653c: 030097b7 lui a5,0x3009 + 3006540: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006544: 3975 jal ra,3006200 + 3006546: a001 j 3006546 + UART_PARAM_CHECK_WITH_RET(uartHandle->txState == UART_STATE_NONE_INIT, BASE_STATUS_ERROR); + 3006548: fdc42783 lw a5,-36(s0) + 300654c: 47bc lw a5,72(a5) + 300654e: cb91 beqz a5,3006562 + 3006550: 09900593 li a1,153 + 3006554: 030097b7 lui a5,0x3009 + 3006558: ac078513 addi a0,a5,-1344 # 3008ac0 + 300655c: 3155 jal ra,3006200 + 300655e: 4785 li a5,1 + 3006560: ae0d j 3006892 + UART_PARAM_CHECK_WITH_RET(uartHandle->rxState == UART_STATE_NONE_INIT, BASE_STATUS_ERROR); + 3006562: fdc42783 lw a5,-36(s0) + 3006566: 47fc lw a5,76(a5) + 3006568: cb91 beqz a5,300657c + 300656a: 09a00593 li a1,154 + 300656e: 030097b7 lui a5,0x3009 + 3006572: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006576: 3169 jal ra,3006200 + 3006578: 4785 li a5,1 + 300657a: ae21 j 3006892 + unsigned int uartClock, quot; + UART_PARAM_CHECK_WITH_RET(IsUartDatalength(uartHandle->dataLength), BASE_STATUS_ERROR); + 300657c: fdc42783 lw a5,-36(s0) + 3006580: 479c lw a5,8(a5) + 3006582: 853e mv a0,a5 + 3006584: 3141 jal ra,3006204 + 3006586: 87aa mv a5,a0 + 3006588: 0017c793 xori a5,a5,1 + 300658c: 9f81 uxtb a5 + 300658e: cb91 beqz a5,30065a2 + 3006590: 09c00593 li a1,156 + 3006594: 030097b7 lui a5,0x3009 + 3006598: ac078513 addi a0,a5,-1344 # 3008ac0 + 300659c: 3195 jal ra,3006200 + 300659e: 4785 li a5,1 + 30065a0: accd j 3006892 + UART_PARAM_CHECK_WITH_RET(IsUartStopbits(uartHandle->stopBits), BASE_STATUS_ERROR); + 30065a2: fdc42783 lw a5,-36(s0) + 30065a6: 47dc lw a5,12(a5) + 30065a8: 853e mv a0,a5 + 30065aa: 399d jal ra,3006220 + 30065ac: 87aa mv a5,a0 + 30065ae: 0017c793 xori a5,a5,1 + 30065b2: 9f81 uxtb a5 + 30065b4: cb91 beqz a5,30065c8 + 30065b6: 09d00593 li a1,157 + 30065ba: 030097b7 lui a5,0x3009 + 30065be: ac078513 addi a0,a5,-1344 # 3008ac0 + 30065c2: 393d jal ra,3006200 + 30065c4: 4785 li a5,1 + 30065c6: a4f1 j 3006892 + UART_PARAM_CHECK_WITH_RET(IsUartParitymode(uartHandle->parity), BASE_STATUS_ERROR); + 30065c8: fdc42783 lw a5,-36(s0) + 30065cc: 4b9c lw a5,16(a5) + 30065ce: 853e mv a0,a5 + 30065d0: 39b5 jal ra,300624c + 30065d2: 87aa mv a5,a0 + 30065d4: 0017c793 xori a5,a5,1 + 30065d8: 9f81 uxtb a5 + 30065da: cb91 beqz a5,30065ee + 30065dc: 09e00593 li a1,158 + 30065e0: 030097b7 lui a5,0x3009 + 30065e4: ac078513 addi a0,a5,-1344 # 3008ac0 + 30065e8: 3921 jal ra,3006200 + 30065ea: 4785 li a5,1 + 30065ec: a45d j 3006892 + UART_PARAM_CHECK_WITH_RET(IsUartTransmode(uartHandle->txMode), BASE_STATUS_ERROR); + 30065ee: fdc42783 lw a5,-36(s0) + 30065f2: 4bdc lw a5,20(a5) + 30065f4: 853e mv a0,a5 + 30065f6: 39a5 jal ra,300626e + 30065f8: 87aa mv a5,a0 + 30065fa: 0017c793 xori a5,a5,1 + 30065fe: 9f81 uxtb a5 + 3006600: cb91 beqz a5,3006614 + 3006602: 09f00593 li a1,159 + 3006606: 030097b7 lui a5,0x3009 + 300660a: ac078513 addi a0,a5,-1344 # 3008ac0 + 300660e: 3ecd jal ra,3006200 + 3006610: 4785 li a5,1 + 3006612: a441 j 3006892 + UART_PARAM_CHECK_WITH_RET(IsUartTransmode(uartHandle->rxMode), BASE_STATUS_ERROR); + 3006614: fdc42783 lw a5,-36(s0) + 3006618: 4f9c lw a5,24(a5) + 300661a: 853e mv a0,a5 + 300661c: 3989 jal ra,300626e + 300661e: 87aa mv a5,a0 + 3006620: 0017c793 xori a5,a5,1 + 3006624: 9f81 uxtb a5 + 3006626: cb91 beqz a5,300663a + 3006628: 0a000593 li a1,160 + 300662c: 030097b7 lui a5,0x3009 + 3006630: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006634: 36f1 jal ra,3006200 + 3006636: 4785 li a5,1 + 3006638: aca9 j 3006892 + UART_PARAM_CHECK_WITH_RET(IsUartFIFOThreshold(uartHandle->fifoTxThr), BASE_STATUS_ERROR); + 300663a: fdc42783 lw a5,-36(s0) + 300663e: 5b9c lw a5,48(a5) + 3006640: 853e mv a0,a5 + 3006642: 31a5 jal ra,30062aa + 3006644: 87aa mv a5,a0 + 3006646: 0017c793 xori a5,a5,1 + 300664a: 9f81 uxtb a5 + 300664c: cb91 beqz a5,3006660 + 300664e: 0a100593 li a1,161 + 3006652: 030097b7 lui a5,0x3009 + 3006656: ac078513 addi a0,a5,-1344 # 3008ac0 + 300665a: 365d jal ra,3006200 + 300665c: 4785 li a5,1 + 300665e: ac15 j 3006892 + UART_PARAM_CHECK_WITH_RET(IsUartFIFOThreshold(uartHandle->fifoRxThr), BASE_STATUS_ERROR); + 3006660: fdc42783 lw a5,-36(s0) + 3006664: 5bdc lw a5,52(a5) + 3006666: 853e mv a0,a5 + 3006668: 3189 jal ra,30062aa + 300666a: 87aa mv a5,a0 + 300666c: 0017c793 xori a5,a5,1 + 3006670: 9f81 uxtb a5 + 3006672: cb91 beqz a5,3006686 + 3006674: 0a200593 li a1,162 + 3006678: 030097b7 lui a5,0x3009 + 300667c: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006680: 3641 jal ra,3006200 + 3006682: 4785 li a5,1 + 3006684: a439 j 3006892 + UART_PARAM_CHECK_WITH_RET(IsUartOversampleMultiple(uartHandle->handleEx.overSampleMultiple), BASE_STATUS_ERROR); + 3006686: fdc42783 lw a5,-36(s0) + 300668a: 5fbc lw a5,120(a5) + 300668c: 853e mv a0,a5 + 300668e: 3925 jal ra,30062c6 + 3006690: 87aa mv a5,a0 + 3006692: 0017c793 xori a5,a5,1 + 3006696: 9f81 uxtb a5 + 3006698: cb91 beqz a5,30066ac + 300669a: 0a300593 li a1,163 + 300669e: 030097b7 lui a5,0x3009 + 30066a2: ac078513 addi a0,a5,-1344 # 3008ac0 + 30066a6: 3ea9 jal ra,3006200 + 30066a8: 4785 li a5,1 + 30066aa: a2e5 j 3006892 + + uartHandle->baseAddress->UART_CR.BIT.uarten = BASE_CFG_DISABLE; + 30066ac: fdc42783 lw a5,-36(s0) + 30066b0: 4398 lw a4,0(a5) + 30066b2: 5b1c lw a5,48(a4) + 30066b4: 9bf9 andi a5,a5,-2 + 30066b6: db1c sw a5,48(a4) + while (uartHandle->baseAddress->UART_FR.BIT.busy == 0x01) { + 30066b8: 0001 nop + 30066ba: fdc42783 lw a5,-36(s0) + 30066be: 439c lw a5,0(a5) + 30066c0: 4f9c lw a5,24(a5) + 30066c2: 838d srli a5,a5,0x3 + 30066c4: 8b85 andi a5,a5,1 + 30066c6: 0ff7f713 andi a4,a5,255 + 30066ca: 4785 li a5,1 + 30066cc: fef707e3 beq a4,a5,30066ba + ; + } + + uartClock = HAL_CRG_GetIpFreq((void *)uartHandle->baseAddress); + 30066d0: fdc42783 lw a5,-36(s0) + 30066d4: 439c lw a5,0(a5) + 30066d6: 853e mv a0,a5 + 30066d8: e93fb0ef jal ra,300256a + 30066dc: fea42623 sw a0,-20(s0) + + /* DCL OverSample Multiple check */ + uartHandle->baseAddress->UART_SPCFG.BIT.spcfg = uartHandle->handleEx.overSampleMultiple; + 30066e0: fdc42783 lw a5,-36(s0) + 30066e4: 5fb4 lw a3,120(a5) + 30066e6: fdc42783 lw a5,-36(s0) + 30066ea: 4398 lw a4,0(a5) + 30066ec: 87b6 mv a5,a3 + 30066ee: 8bbd andi a5,a5,15 + 30066f0: 0ff7f693 andi a3,a5,255 + 30066f4: 4f3c lw a5,88(a4) + 30066f6: 8abd andi a3,a3,15 + 30066f8: 9bc1 andi a5,a5,-16 + 30066fa: 8fd5 or a5,a5,a3 + 30066fc: cf3c sw a5,88(a4) + + /* DCL sequences setting */ + uartHandle->baseAddress->UART_DS.BIT.msbfirst = uartHandle->handleEx.msbFirst; + 30066fe: fdc42783 lw a5,-36(s0) + 3006702: 4398 lw a4,0(a5) + 3006704: fdc42783 lw a5,-36(s0) + 3006708: 07c7c683 lbu a3,124(a5) + 300670c: 4b3c lw a5,80(a4) + 300670e: 8a85 andi a3,a3,1 + 3006710: 9bf9 andi a5,a5,-2 + 3006712: 8fd5 or a5,a5,a3 + 3006714: cb3c sw a5,80(a4) + + /* The baud rate divider(BRD) based on the baud rate and clock frequency, calculation formula */ + unsigned int oversample = uartHandle->baseAddress->UART_SPCFG.reg; + 3006716: fdc42783 lw a5,-36(s0) + 300671a: 439c lw a5,0(a5) + 300671c: 4fbc lw a5,88(a5) + 300671e: fef42423 sw a5,-24(s0) + if (uartHandle->baudRate > (uartClock / (OVERSAMPLING_PARAM - oversample))) { + 3006722: fdc42783 lw a5,-36(s0) + 3006726: 43d8 lw a4,4(a5) + 3006728: 46c1 li a3,16 + 300672a: fe842783 lw a5,-24(s0) + 300672e: 40f687b3 sub a5,a3,a5 + 3006732: fec42683 lw a3,-20(s0) + 3006736: 02f6d7b3 divu a5,a3,a5 + 300673a: 00e7f463 bgeu a5,a4,3006742 + return BASE_STATUS_ERROR; + 300673e: 4785 li a5,1 + 3006740: aa89 j 3006892 + } else { + unsigned int tmpClock = uartClock / (OVERSAMPLING_PARAM - oversample) * 64; /* 64 is for decimal parts */ + 3006742: 4741 li a4,16 + 3006744: fe842783 lw a5,-24(s0) + 3006748: 40f707b3 sub a5,a4,a5 + 300674c: fec42703 lw a4,-20(s0) + 3006750: 02f757b3 divu a5,a4,a5 + 3006754: 079a slli a5,a5,0x6 + 3006756: fef42223 sw a5,-28(s0) + quot = DivClosest(tmpClock, uartHandle->baudRate); + 300675a: fdc42783 lw a5,-36(s0) + 300675e: 43dc lw a5,4(a5) + 3006760: 85be mv a1,a5 + 3006762: fe442503 lw a0,-28(s0) + 3006766: 3eb5 jal ra,30062e2 + 3006768: fea42023 sw a0,-32(s0) + } + /* Clear the baud rate divider register */ + uartHandle->baseAddress->UART_FBRD.reg = 0; + 300676c: fdc42783 lw a5,-36(s0) + 3006770: 439c lw a5,0(a5) + 3006772: 0207a423 sw zero,40(a5) + uartHandle->baseAddress->UART_IBRD.reg = 0; + 3006776: fdc42783 lw a5,-36(s0) + 300677a: 439c lw a5,0(a5) + 300677c: 0207a223 sw zero,36(a5) + /* The fractional baud rate divider value is stored to the lower 6 bits of the FBRD */ + uartHandle->baseAddress->UART_FBRD.reg = (quot & 0x3F); + 3006780: fdc42783 lw a5,-36(s0) + 3006784: 439c lw a5,0(a5) + 3006786: fe042703 lw a4,-32(s0) + 300678a: 03f77713 andi a4,a4,63 + 300678e: d798 sw a4,40(a5) + /* Right shift 6 bits is the integer baud rate divider value, is stored to IBRD */ + uartHandle->baseAddress->UART_IBRD.reg = (quot >> 6); + 3006790: fdc42783 lw a5,-36(s0) + 3006794: 439c lw a5,0(a5) + 3006796: fe042703 lw a4,-32(s0) + 300679a: 8319 srli a4,a4,0x6 + 300679c: d3d8 sw a4,36(a5) + uartHandle->baseAddress->UART_LCR_H.reg = 0; + 300679e: fdc42783 lw a5,-36(s0) + 30067a2: 439c lw a5,0(a5) + 30067a4: 0207a623 sw zero,44(a5) + uartHandle->baseAddress->UART_LCR_H.BIT.wlen = uartHandle->dataLength; /* Frame length seting */ + 30067a8: fdc42783 lw a5,-36(s0) + 30067ac: 4794 lw a3,8(a5) + 30067ae: fdc42783 lw a5,-36(s0) + 30067b2: 4398 lw a4,0(a5) + 30067b4: 87b6 mv a5,a3 + 30067b6: 8b8d andi a5,a5,3 + 30067b8: 0ff7f693 andi a3,a5,255 + 30067bc: 575c lw a5,44(a4) + 30067be: 8a8d andi a3,a3,3 + 30067c0: 0696 slli a3,a3,0x5 + 30067c2: f9f7f793 andi a5,a5,-97 + 30067c6: 8fd5 or a5,a5,a3 + 30067c8: d75c sw a5,44(a4) + uartHandle->baseAddress->UART_LCR_H.BIT.stp2 = uartHandle->stopBits; /* Stop bit seting */ + 30067ca: fdc42783 lw a5,-36(s0) + 30067ce: 47d4 lw a3,12(a5) + 30067d0: fdc42783 lw a5,-36(s0) + 30067d4: 4398 lw a4,0(a5) + 30067d6: 87b6 mv a5,a3 + 30067d8: 8b85 andi a5,a5,1 + 30067da: 0ff7f693 andi a3,a5,255 + 30067de: 575c lw a5,44(a4) + 30067e0: 8a85 andi a3,a3,1 + 30067e2: 068e slli a3,a3,0x3 + 30067e4: 9bdd andi a5,a5,-9 + 30067e6: 8fd5 or a5,a5,a3 + 30067e8: d75c sw a5,44(a4) + UART_SetParityBit(uartHandle); + 30067ea: fdc42503 lw a0,-36(s0) + 30067ee: 39a9 jal ra,3006448 + if (uartHandle->fifoMode == true) { /* FIFO threshold setting */ + 30067f0: fdc42783 lw a5,-36(s0) + 30067f4: 02c7c783 lbu a5,44(a5) + 30067f8: cbb1 beqz a5,300684c + uartHandle->baseAddress->UART_LCR_H.BIT.fen = BASE_CFG_ENABLE; + 30067fa: fdc42783 lw a5,-36(s0) + 30067fe: 4398 lw a4,0(a5) + 3006800: 575c lw a5,44(a4) + 3006802: 0107e793 ori a5,a5,16 + 3006806: d75c sw a5,44(a4) + uartHandle->baseAddress->UART_IFLS.BIT.rxiflsel = uartHandle->fifoRxThr; + 3006808: fdc42783 lw a5,-36(s0) + 300680c: 5bd4 lw a3,52(a5) + 300680e: fdc42783 lw a5,-36(s0) + 3006812: 4398 lw a4,0(a5) + 3006814: 87b6 mv a5,a3 + 3006816: 8bbd andi a5,a5,15 + 3006818: 0ff7f693 andi a3,a5,255 + 300681c: 5b5c lw a5,52(a4) + 300681e: 8abd andi a3,a3,15 + 3006820: 06a2 slli a3,a3,0x8 + 3006822: 767d lui a2,0xfffff + 3006824: 0ff60613 addi a2,a2,255 # fffff0ff + 3006828: 8ff1 and a5,a5,a2 + 300682a: 8fd5 or a5,a5,a3 + 300682c: db5c sw a5,52(a4) + uartHandle->baseAddress->UART_IFLS.BIT.txiflsel = uartHandle->fifoTxThr; + 300682e: fdc42783 lw a5,-36(s0) + 3006832: 5b94 lw a3,48(a5) + 3006834: fdc42783 lw a5,-36(s0) + 3006838: 4398 lw a4,0(a5) + 300683a: 87b6 mv a5,a3 + 300683c: 8bbd andi a5,a5,15 + 300683e: 0ff7f693 andi a3,a5,255 + 3006842: 5b5c lw a5,52(a4) + 3006844: 8abd andi a3,a3,15 + 3006846: 9bc1 andi a5,a5,-16 + 3006848: 8fd5 or a5,a5,a3 + 300684a: db5c sw a5,52(a4) + } + if (uartHandle->hwFlowCtr == UART_HW_FLOWCTR_ENABLE) { /* Hardwarer flow control setting */ + 300684c: fdc42783 lw a5,-36(s0) + 3006850: 5f98 lw a4,56(a5) + 3006852: 4785 li a5,1 + 3006854: 00f71c63 bne a4,a5,300686c + uartHandle->baseAddress->UART_CR.reg |= 0xC000; + 3006858: fdc42783 lw a5,-36(s0) + 300685c: 439c lw a5,0(a5) + 300685e: 5b94 lw a3,48(a5) + 3006860: fdc42783 lw a5,-36(s0) + 3006864: 439c lw a5,0(a5) + 3006866: 6731 lui a4,0xc + 3006868: 8f55 or a4,a4,a3 + 300686a: db98 sw a4,48(a5) + } + uartHandle->baseAddress->UART_CR.reg |= 0x301; /* Enable bit use 0x301 is to set txe/rxe/uarten */ + 300686c: fdc42783 lw a5,-36(s0) + 3006870: 439c lw a5,0(a5) + 3006872: 5b98 lw a4,48(a5) + 3006874: fdc42783 lw a5,-36(s0) + 3006878: 439c lw a5,0(a5) + 300687a: 30176713 ori a4,a4,769 + 300687e: db98 sw a4,48(a5) + uartHandle->txState = UART_STATE_READY; + 3006880: fdc42783 lw a5,-36(s0) + 3006884: 4705 li a4,1 + 3006886: c7b8 sw a4,72(a5) + uartHandle->rxState = UART_STATE_READY; + 3006888: fdc42783 lw a5,-36(s0) + 300688c: 4705 li a4,1 + 300688e: c7f8 sw a4,76(a5) + return BASE_STATUS_OK; + 3006890: 4781 li a5,0 +} + 3006892: 853e mv a0,a5 + 3006894: 50b2 lw ra,44(sp) + 3006896: 5422 lw s0,40(sp) + 3006898: 6145 addi sp,sp,48 + 300689a: 8082 ret + +0300689c : + * @param blockingTime Blocking time, unit: milliseconds. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_WriteBlocking(UART_Handle *uartHandle, unsigned char *srcData, + unsigned int dataLength, unsigned int blockingTime) +{ + 300689c: 7139 addi sp,sp,-64 + 300689e: 03010293 addi t0,sp,48 + 30068a2: 0062928b stmia {ra,s0,s2-s3},(t0) + 30068a6: 0080 addi s0,sp,64 + 30068a8: fca42623 sw a0,-52(s0) + 30068ac: fcb42423 sw a1,-56(s0) + 30068b0: fcc42223 sw a2,-60(s0) + 30068b4: fcd42023 sw a3,-64(s0) + UART_ASSERT_PARAM(uartHandle != NULL); + 30068b8: fcc42783 lw a5,-52(s0) + 30068bc: eb89 bnez a5,30068ce + 30068be: 11500593 li a1,277 + 30068c2: 030097b7 lui a5,0x3009 + 30068c6: ac078513 addi a0,a5,-1344 # 3008ac0 + 30068ca: 3a1d jal ra,3006200 + 30068cc: a001 j 30068cc + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + 30068ce: fcc42783 lw a5,-52(s0) + 30068d2: 4398 lw a4,0(a5) + 30068d4: 140007b7 lui a5,0x14000 + 30068d8: 02f70f63 beq a4,a5,3006916 + 30068dc: fcc42783 lw a5,-52(s0) + 30068e0: 4398 lw a4,0(a5) + 30068e2: 140017b7 lui a5,0x14001 + 30068e6: 02f70863 beq a4,a5,3006916 + 30068ea: fcc42783 lw a5,-52(s0) + 30068ee: 4398 lw a4,0(a5) + 30068f0: 140027b7 lui a5,0x14002 + 30068f4: 02f70163 beq a4,a5,3006916 + 30068f8: fcc42783 lw a5,-52(s0) + 30068fc: 4398 lw a4,0(a5) + 30068fe: 140037b7 lui a5,0x14003 + 3006902: 00f70a63 beq a4,a5,3006916 + 3006906: 11600593 li a1,278 + 300690a: 030097b7 lui a5,0x3009 + 300690e: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006912: 30fd jal ra,3006200 + 3006914: a001 j 3006914 + UART_ASSERT_PARAM(srcData != NULL); + 3006916: fc842783 lw a5,-56(s0) + 300691a: eb89 bnez a5,300692c + 300691c: 11700593 li a1,279 + 3006920: 030097b7 lui a5,0x3009 + 3006924: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006928: 38e1 jal ra,3006200 + 300692a: a001 j 300692a + UART_PARAM_CHECK_WITH_RET(uartHandle->txMode == UART_MODE_BLOCKING, BASE_STATUS_ERROR); + 300692c: fcc42783 lw a5,-52(s0) + 3006930: 4bdc lw a5,20(a5) + 3006932: cb91 beqz a5,3006946 + 3006934: 11800593 li a1,280 + 3006938: 030097b7 lui a5,0x3009 + 300693c: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006940: 23bd jal ra,3006eae + 3006942: 4785 li a5,1 + 3006944: a249 j 3006ac6 + UART_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + 3006946: fc442783 lw a5,-60(s0) + 300694a: eb91 bnez a5,300695e + 300694c: 11900593 li a1,281 + 3006950: 030097b7 lui a5,0x3009 + 3006954: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006958: 2b99 jal ra,3006eae + 300695a: 4785 li a5,1 + 300695c: a2ad j 3006ac6 + unsigned long long setTick = HAL_CRG_GetIpFreq(SYSTICK_BASE) / SYSTICK_MS_DIV * blockingTime; + 300695e: 14380537 lui a0,0x14380 + 3006962: c09fb0ef jal ra,300256a + 3006966: 872a mv a4,a0 + 3006968: 3e800793 li a5,1000 + 300696c: 02f75733 divu a4,a4,a5 + 3006970: fc042783 lw a5,-64(s0) + 3006974: 02f707b3 mul a5,a4,a5 + 3006978: fef42023 sw a5,-32(s0) + 300697c: fe042223 sw zero,-28(s0) + UART_PARAM_CHECK_WITH_RET(setTick < SYSTICK_MAX_VALUE, BASE_STATUS_ERROR); + 3006980: fe442783 lw a5,-28(s0) + 3006984: eb89 bnez a5,3006996 + 3006986: fe442783 lw a5,-28(s0) + 300698a: ef99 bnez a5,30069a8 + 300698c: fe042703 lw a4,-32(s0) + 3006990: 57f9 li a5,-2 + 3006992: 00e7fb63 bgeu a5,a4,30069a8 + 3006996: 11b00593 li a1,283 + 300699a: 030097b7 lui a5,0x3009 + 300699e: ac078513 addi a0,a5,-1344 # 3008ac0 + 30069a2: 2331 jal ra,3006eae + 30069a4: 4785 li a5,1 + 30069a6: a205 j 3006ac6 + if (uartHandle->txState == UART_STATE_READY) { + 30069a8: fcc42783 lw a5,-52(s0) + 30069ac: 47b8 lw a4,72(a5) + 30069ae: 4785 li a5,1 + 30069b0: 10f71463 bne a4,a5,3006ab8 + uartHandle->txState = UART_STATE_BUSY_TX; + 30069b4: fcc42783 lw a5,-52(s0) + 30069b8: 470d li a4,3 + 30069ba: c7b8 sw a4,72(a5) + unsigned int txCount = dataLength; + 30069bc: fc442783 lw a5,-60(s0) + 30069c0: fef42623 sw a5,-20(s0) + unsigned char *src = srcData; + 30069c4: fc842783 lw a5,-56(s0) + 30069c8: fef42423 sw a5,-24(s0) + uartHandle->baseAddress->UART_IMSC.BIT.txim = BASE_CFG_DISABLE; /* Disable TX interrupt bit */ + 30069cc: fcc42783 lw a5,-52(s0) + 30069d0: 4398 lw a4,0(a5) + 30069d2: 5f1c lw a5,56(a4) + 30069d4: fdf7f793 andi a5,a5,-33 + 30069d8: df1c sw a5,56(a4) + uartHandle->baseAddress->UART_CR.BIT.txe = BASE_CFG_ENABLE; + 30069da: fcc42783 lw a5,-52(s0) + 30069de: 4398 lw a4,0(a5) + 30069e0: 5b1c lw a5,48(a4) + 30069e2: 1007e793 ori a5,a5,256 + 30069e6: db1c sw a5,48(a4) + unsigned long long deltaTick; + unsigned int preTick = DCL_SYSTICK_GetTick(); + 30069e8: 837fa0ef jal ra,300121e + 30069ec: fca42e23 sw a0,-36(s0) + unsigned int curTick = preTick; + 30069f0: fdc42783 lw a5,-36(s0) + 30069f4: fcf42c23 sw a5,-40(s0) + while (txCount > 0x00) { + 30069f8: a865 j 3006ab0 + curTick = DCL_SYSTICK_GetTick(); + 30069fa: 825fa0ef jal ra,300121e + 30069fe: fca42c23 sw a0,-40(s0) + deltaTick = (curTick > preTick) ? (curTick - preTick) : (SYSTICK_MAX_VALUE - preTick + curTick); + 3006a02: fd842703 lw a4,-40(s0) + 3006a06: fdc42783 lw a5,-36(s0) + 3006a0a: 00e7fb63 bgeu a5,a4,3006a20 + 3006a0e: fd842703 lw a4,-40(s0) + 3006a12: fdc42783 lw a5,-36(s0) + 3006a16: 40f707b3 sub a5,a4,a5 + 3006a1a: 893e mv s2,a5 + 3006a1c: 4981 li s3,0 + 3006a1e: a811 j 3006a32 + 3006a20: fd842703 lw a4,-40(s0) + 3006a24: fdc42783 lw a5,-36(s0) + 3006a28: 40f707b3 sub a5,a4,a5 + 3006a2c: 17fd addi a5,a5,-1 + 3006a2e: 893e mv s2,a5 + 3006a30: 4981 li s3,0 + 3006a32: fd242823 sw s2,-48(s0) + 3006a36: fd342a23 sw s3,-44(s0) + if (deltaTick >= setTick) { + 3006a3a: fe442703 lw a4,-28(s0) + 3006a3e: fd442783 lw a5,-44(s0) + 3006a42: 02e7e463 bltu a5,a4,3006a6a + 3006a46: fe442703 lw a4,-28(s0) + 3006a4a: fd442783 lw a5,-44(s0) + 3006a4e: 00f71863 bne a4,a5,3006a5e + 3006a52: fe042703 lw a4,-32(s0) + 3006a56: fd042783 lw a5,-48(s0) + 3006a5a: 00e7e863 bltu a5,a4,3006a6a + uartHandle->txState = UART_STATE_READY; + 3006a5e: fcc42783 lw a5,-52(s0) + 3006a62: 4705 li a4,1 + 3006a64: c7b8 sw a4,72(a5) + return BASE_STATUS_TIMEOUT; + 3006a66: 478d li a5,3 + 3006a68: a8b9 j 3006ac6 + } + if (uartHandle->baseAddress->UART_FR.BIT.txff == 0x01) { /* True when the TX FIFO is full */ + 3006a6a: fcc42783 lw a5,-52(s0) + 3006a6e: 439c lw a5,0(a5) + 3006a70: 4f9c lw a5,24(a5) + 3006a72: 8395 srli a5,a5,0x5 + 3006a74: 8b85 andi a5,a5,1 + 3006a76: 0ff7f713 andi a4,a5,255 + 3006a7a: 4785 li a5,1 + 3006a7c: 00f71363 bne a4,a5,3006a82 + continue; + 3006a80: a805 j 3006ab0 + } + /* Blocking write to DR when register is empty */ + uartHandle->baseAddress->UART_DR.BIT.data = *(src); + 3006a82: fcc42783 lw a5,-52(s0) + 3006a86: 4398 lw a4,0(a5) + 3006a88: fe842783 lw a5,-24(s0) + 3006a8c: 2394 lbu a3,0(a5) + 3006a8e: 431c lw a5,0(a4) + 3006a90: 0ff6f693 andi a3,a3,255 + 3006a94: f007f793 andi a5,a5,-256 + 3006a98: 8fd5 or a5,a5,a3 + 3006a9a: c31c sw a5,0(a4) + src++; + 3006a9c: fe842783 lw a5,-24(s0) + 3006aa0: 0785 addi a5,a5,1 + 3006aa2: fef42423 sw a5,-24(s0) + txCount--; + 3006aa6: fec42783 lw a5,-20(s0) + 3006aaa: 17fd addi a5,a5,-1 + 3006aac: fef42623 sw a5,-20(s0) + while (txCount > 0x00) { + 3006ab0: fec42783 lw a5,-20(s0) + 3006ab4: f3b9 bnez a5,30069fa + 3006ab6: a019 j 3006abc + } + } else { + return BASE_STATUS_BUSY; + 3006ab8: 4789 li a5,2 + 3006aba: a031 j 3006ac6 + } + uartHandle->txState = UART_STATE_READY; + 3006abc: fcc42783 lw a5,-52(s0) + 3006ac0: 4705 li a4,1 + 3006ac2: c7b8 sw a4,72(a5) + return BASE_STATUS_OK; + 3006ac4: 4781 li a5,0 +} + 3006ac6: 853e mv a0,a5 + 3006ac8: 03010293 addi t0,sp,48 + 3006acc: 0062828b ldmia {ra,s0,s2-s3},(t0) + 3006ad0: 6121 addi sp,sp,64 + 3006ad2: 8082 ret + +03006ad4 : + * The hanler function is called when Tx interruption occurs. + * @param uartHandle UART handle. + * @retval None. + */ +static void WriteITCallBack(UART_Handle *uartHandle) +{ + 3006ad4: 1101 addi sp,sp,-32 + 3006ad6: ce06 sw ra,28(sp) + 3006ad8: cc22 sw s0,24(sp) + 3006ada: 1000 addi s0,sp,32 + 3006adc: fea42623 sw a0,-20(s0) + UART_ASSERT_PARAM(uartHandle != NULL); + 3006ae0: fec42783 lw a5,-20(s0) + 3006ae4: eb89 bnez a5,3006af6 + 3006ae6: 16200593 li a1,354 + 3006aea: 030097b7 lui a5,0x3009 + 3006aee: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006af2: 2e75 jal ra,3006eae + 3006af4: a001 j 3006af4 + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + 3006af6: fec42783 lw a5,-20(s0) + 3006afa: 4398 lw a4,0(a5) + 3006afc: 140007b7 lui a5,0x14000 + 3006b00: 02f70f63 beq a4,a5,3006b3e + 3006b04: fec42783 lw a5,-20(s0) + 3006b08: 4398 lw a4,0(a5) + 3006b0a: 140017b7 lui a5,0x14001 + 3006b0e: 02f70863 beq a4,a5,3006b3e + 3006b12: fec42783 lw a5,-20(s0) + 3006b16: 4398 lw a4,0(a5) + 3006b18: 140027b7 lui a5,0x14002 + 3006b1c: 02f70163 beq a4,a5,3006b3e + 3006b20: fec42783 lw a5,-20(s0) + 3006b24: 4398 lw a4,0(a5) + 3006b26: 140037b7 lui a5,0x14003 + 3006b2a: 00f70a63 beq a4,a5,3006b3e + 3006b2e: 16300593 li a1,355 + 3006b32: 030097b7 lui a5,0x3009 + 3006b36: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006b3a: 2e95 jal ra,3006eae + 3006b3c: a001 j 3006b3c + UART_ASSERT_PARAM(uartHandle->txbuff != NULL); + 3006b3e: fec42783 lw a5,-20(s0) + 3006b42: 4fdc lw a5,28(a5) + 3006b44: eb89 bnez a5,3006b56 + 3006b46: 16400593 li a1,356 + 3006b4a: 030097b7 lui a5,0x3009 + 3006b4e: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006b52: 2eb1 jal ra,3006eae + 3006b54: a001 j 3006b54 + if (uartHandle->txState == UART_STATE_BUSY_TX) { + 3006b56: fec42783 lw a5,-20(s0) + 3006b5a: 47b8 lw a4,72(a5) + 3006b5c: 478d li a5,3 + 3006b5e: 0af71f63 bne a4,a5,3006c1c + while (uartHandle->txBuffSize > 0) { + 3006b62: a8a1 j 3006bba + if (uartHandle->baseAddress->UART_FR.BIT.txff == 1) { /* True when the TX FIFO is full */ + 3006b64: fec42783 lw a5,-20(s0) + 3006b68: 439c lw a5,0(a5) + 3006b6a: 4f9c lw a5,24(a5) + 3006b6c: 8395 srli a5,a5,0x5 + 3006b6e: 8b85 andi a5,a5,1 + 3006b70: 0ff7f713 andi a4,a5,255 + 3006b74: 4785 li a5,1 + 3006b76: 04f70763 beq a4,a5,3006bc4 + break; + } + uartHandle->baseAddress->UART_DR.BIT.data = *(uartHandle->txbuff); + 3006b7a: fec42783 lw a5,-20(s0) + 3006b7e: 4fdc lw a5,28(a5) + 3006b80: fec42703 lw a4,-20(s0) + 3006b84: 4318 lw a4,0(a4) + 3006b86: 239c lbu a5,0(a5) + 3006b88: 0ff7f693 andi a3,a5,255 + 3006b8c: 431c lw a5,0(a4) + 3006b8e: 0ff6f693 andi a3,a3,255 + 3006b92: f007f793 andi a5,a5,-256 + 3006b96: 8fd5 or a5,a5,a3 + 3006b98: c31c sw a5,0(a4) + (uartHandle->txbuff)++; + 3006b9a: fec42783 lw a5,-20(s0) + 3006b9e: 4fdc lw a5,28(a5) + 3006ba0: 00178713 addi a4,a5,1 + 3006ba4: fec42783 lw a5,-20(s0) + 3006ba8: cfd8 sw a4,28(a5) + uartHandle->txBuffSize -= 1; + 3006baa: fec42783 lw a5,-20(s0) + 3006bae: 53dc lw a5,36(a5) + 3006bb0: fff78713 addi a4,a5,-1 + 3006bb4: fec42783 lw a5,-20(s0) + 3006bb8: d3d8 sw a4,36(a5) + while (uartHandle->txBuffSize > 0) { + 3006bba: fec42783 lw a5,-20(s0) + 3006bbe: 53dc lw a5,36(a5) + 3006bc0: f3d5 bnez a5,3006b64 + 3006bc2: a011 j 3006bc6 + break; + 3006bc4: 0001 nop + } + if (uartHandle->txBuffSize == 0) { + 3006bc6: fec42783 lw a5,-20(s0) + 3006bca: 53dc lw a5,36(a5) + 3006bcc: eba1 bnez a5,3006c1c + uartHandle->baseAddress->UART_IMSC.reg &= 0xFFFFEFDF; /* Disable txim and txfeim */ + 3006bce: fec42783 lw a5,-20(s0) + 3006bd2: 439c lw a5,0(a5) + 3006bd4: 5f94 lw a3,56(a5) + 3006bd6: fec42783 lw a5,-20(s0) + 3006bda: 439c lw a5,0(a5) + 3006bdc: 777d lui a4,0xfffff + 3006bde: fdf70713 addi a4,a4,-33 # ffffefdf + 3006be2: 8f75 and a4,a4,a3 + 3006be4: df98 sw a4,56(a5) + uartHandle->baseAddress->UART_ICR.reg |= 0x1020; /* Clear txic and txfeic */ + 3006be6: fec42783 lw a5,-20(s0) + 3006bea: 439c lw a5,0(a5) + 3006bec: 43f4 lw a3,68(a5) + 3006bee: fec42783 lw a5,-20(s0) + 3006bf2: 439c lw a5,0(a5) + 3006bf4: 6705 lui a4,0x1 + 3006bf6: 02070713 addi a4,a4,32 # 1020 + 3006bfa: 8f55 or a4,a4,a3 + 3006bfc: c3f8 sw a4,68(a5) + uartHandle->txState = UART_STATE_READY; + 3006bfe: fec42783 lw a5,-20(s0) + 3006c02: 4705 li a4,1 + 3006c04: c7b8 sw a4,72(a5) + /* Call user call back function */ + if (uartHandle->userCallBack.WriteItFinishCallBack != NULL) { + 3006c06: fec42783 lw a5,-20(s0) + 3006c0a: 4bfc lw a5,84(a5) + 3006c0c: cb81 beqz a5,3006c1c + uartHandle->userCallBack.WriteItFinishCallBack(uartHandle); + 3006c0e: fec42783 lw a5,-20(s0) + 3006c12: 4bfc lw a5,84(a5) + 3006c14: fec42503 lw a0,-20(s0) + 3006c18: 9782 jalr a5 + } + } + } + return; + 3006c1a: 0001 nop + 3006c1c: 0001 nop +} + 3006c1e: 40f2 lw ra,28(sp) + 3006c20: 4462 lw s0,24(sp) + 3006c22: 6105 addi sp,sp,32 + 3006c24: 8082 ret + +03006c26 : + * @param saveData Address of the data buff to be saved. + * @param dataLength length of the data int the storage buffer. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_ReadIT(UART_Handle *uartHandle, unsigned char *saveData, unsigned int dataLength) +{ + 3006c26: 1101 addi sp,sp,-32 + 3006c28: ce06 sw ra,28(sp) + 3006c2a: cc22 sw s0,24(sp) + 3006c2c: 1000 addi s0,sp,32 + 3006c2e: fea42623 sw a0,-20(s0) + 3006c32: feb42423 sw a1,-24(s0) + 3006c36: fec42223 sw a2,-28(s0) + UART_ASSERT_PARAM(uartHandle != NULL); + 3006c3a: fec42783 lw a5,-20(s0) + 3006c3e: eb89 bnez a5,3006c50 + 3006c40: 1e100593 li a1,481 + 3006c44: 030097b7 lui a5,0x3009 + 3006c48: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006c4c: 248d jal ra,3006eae + 3006c4e: a001 j 3006c4e + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + 3006c50: fec42783 lw a5,-20(s0) + 3006c54: 4398 lw a4,0(a5) + 3006c56: 140007b7 lui a5,0x14000 + 3006c5a: 02f70f63 beq a4,a5,3006c98 + 3006c5e: fec42783 lw a5,-20(s0) + 3006c62: 4398 lw a4,0(a5) + 3006c64: 140017b7 lui a5,0x14001 + 3006c68: 02f70863 beq a4,a5,3006c98 + 3006c6c: fec42783 lw a5,-20(s0) + 3006c70: 4398 lw a4,0(a5) + 3006c72: 140027b7 lui a5,0x14002 + 3006c76: 02f70163 beq a4,a5,3006c98 + 3006c7a: fec42783 lw a5,-20(s0) + 3006c7e: 4398 lw a4,0(a5) + 3006c80: 140037b7 lui a5,0x14003 + 3006c84: 00f70a63 beq a4,a5,3006c98 + 3006c88: 1e200593 li a1,482 + 3006c8c: 030097b7 lui a5,0x3009 + 3006c90: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006c94: 2c29 jal ra,3006eae + 3006c96: a001 j 3006c96 + UART_ASSERT_PARAM(saveData != NULL); + 3006c98: fe842783 lw a5,-24(s0) + 3006c9c: eb89 bnez a5,3006cae + 3006c9e: 1e300593 li a1,483 + 3006ca2: 030097b7 lui a5,0x3009 + 3006ca6: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006caa: 2411 jal ra,3006eae + 3006cac: a001 j 3006cac + UART_PARAM_CHECK_WITH_RET(uartHandle->rxMode == UART_MODE_INTERRUPT, BASE_STATUS_ERROR); + 3006cae: fec42783 lw a5,-20(s0) + 3006cb2: 4f98 lw a4,24(a5) + 3006cb4: 4785 li a5,1 + 3006cb6: 00f70b63 beq a4,a5,3006ccc + 3006cba: 1e400593 li a1,484 + 3006cbe: 030097b7 lui a5,0x3009 + 3006cc2: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006cc6: 22e5 jal ra,3006eae + 3006cc8: 4785 li a5,1 + 3006cca: a051 j 3006d4e + UART_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + 3006ccc: fe442783 lw a5,-28(s0) + 3006cd0: eb91 bnez a5,3006ce4 + 3006cd2: 1e500593 li a1,485 + 3006cd6: 030097b7 lui a5,0x3009 + 3006cda: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006cde: 2ac1 jal ra,3006eae + 3006ce0: 4785 li a5,1 + 3006ce2: a0b5 j 3006d4e + if (uartHandle->rxState == UART_STATE_READY) { + 3006ce4: fec42783 lw a5,-20(s0) + 3006ce8: 47f8 lw a4,76(a5) + 3006cea: 4785 li a5,1 + 3006cec: 04f71e63 bne a4,a5,3006d48 + uartHandle->rxState = UART_STATE_BUSY_RX; + 3006cf0: fec42783 lw a5,-20(s0) + 3006cf4: 4711 li a4,4 + 3006cf6: c7f8 sw a4,76(a5) + uartHandle->rxbuff = saveData; + 3006cf8: fec42783 lw a5,-20(s0) + 3006cfc: fe842703 lw a4,-24(s0) + 3006d00: d398 sw a4,32(a5) + uartHandle->rxBuffSize = dataLength; + 3006d02: fec42783 lw a5,-20(s0) + 3006d06: fe442703 lw a4,-28(s0) + 3006d0a: d798 sw a4,40(a5) + if (uartHandle->fifoMode == true) { + 3006d0c: fec42783 lw a5,-20(s0) + 3006d10: 02c7c783 lbu a5,44(a5) + 3006d14: cf81 beqz a5,3006d2c + uartHandle->baseAddress->UART_IMSC.reg |= 0x7D0; /* Enable rx interrupt and rx timeout interrupt */ + 3006d16: fec42783 lw a5,-20(s0) + 3006d1a: 439c lw a5,0(a5) + 3006d1c: 5f98 lw a4,56(a5) + 3006d1e: fec42783 lw a5,-20(s0) + 3006d22: 439c lw a5,0(a5) + 3006d24: 7d076713 ori a4,a4,2000 + 3006d28: df98 sw a4,56(a5) + 3006d2a: a00d j 3006d4c + } else { + uartHandle->baseAddress->UART_IMSC.reg |= 0x20780; /* Enable rx not empty interrupt */ + 3006d2c: fec42783 lw a5,-20(s0) + 3006d30: 439c lw a5,0(a5) + 3006d32: 5f94 lw a3,56(a5) + 3006d34: fec42783 lw a5,-20(s0) + 3006d38: 439c lw a5,0(a5) + 3006d3a: 00020737 lui a4,0x20 + 3006d3e: 78070713 addi a4,a4,1920 # 20780 + 3006d42: 8f55 or a4,a4,a3 + 3006d44: df98 sw a4,56(a5) + 3006d46: a019 j 3006d4c + } + } else { + return BASE_STATUS_BUSY; + 3006d48: 4789 li a5,2 + 3006d4a: a011 j 3006d4e + } + return BASE_STATUS_OK; + 3006d4c: 4781 li a5,0 +} + 3006d4e: 853e mv a0,a5 + 3006d50: 40f2 lw ra,28(sp) + 3006d52: 4462 lw s0,24(sp) + 3006d54: 6105 addi sp,sp,32 + 3006d56: 8082 ret + +03006d58 : + * The hanler function is called when Rx interruption occurs. + * @param uartHandle UART handle. + * @retval None. + */ +static void ReadITCallBack(UART_Handle *uartHandle) +{ + 3006d58: 7179 addi sp,sp,-48 + 3006d5a: d606 sw ra,44(sp) + 3006d5c: d422 sw s0,40(sp) + 3006d5e: 1800 addi s0,sp,48 + 3006d60: fca42e23 sw a0,-36(s0) + UART_ASSERT_PARAM(uartHandle != NULL); + 3006d64: fdc42783 lw a5,-36(s0) + 3006d68: eb89 bnez a5,3006d7a + 3006d6a: 1fd00593 li a1,509 + 3006d6e: 030097b7 lui a5,0x3009 + 3006d72: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006d76: 2a25 jal ra,3006eae + 3006d78: a001 j 3006d78 + UART_ASSERT_PARAM(uartHandle->rxbuff != NULL); + 3006d7a: fdc42783 lw a5,-36(s0) + 3006d7e: 539c lw a5,32(a5) + 3006d80: eb89 bnez a5,3006d92 + 3006d82: 1fe00593 li a1,510 + 3006d86: 030097b7 lui a5,0x3009 + 3006d8a: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006d8e: 2205 jal ra,3006eae + 3006d90: a001 j 3006d90 + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + 3006d92: fdc42783 lw a5,-36(s0) + 3006d96: 4398 lw a4,0(a5) + 3006d98: 140007b7 lui a5,0x14000 + 3006d9c: 02f70f63 beq a4,a5,3006dda + 3006da0: fdc42783 lw a5,-36(s0) + 3006da4: 4398 lw a4,0(a5) + 3006da6: 140017b7 lui a5,0x14001 + 3006daa: 02f70863 beq a4,a5,3006dda + 3006dae: fdc42783 lw a5,-36(s0) + 3006db2: 4398 lw a4,0(a5) + 3006db4: 140027b7 lui a5,0x14002 + 3006db8: 02f70163 beq a4,a5,3006dda + 3006dbc: fdc42783 lw a5,-36(s0) + 3006dc0: 4398 lw a4,0(a5) + 3006dc2: 140037b7 lui a5,0x14003 + 3006dc6: 00f70a63 beq a4,a5,3006dda + 3006dca: 1ff00593 li a1,511 + 3006dce: 030097b7 lui a5,0x3009 + 3006dd2: ac078513 addi a0,a5,-1344 # 3008ac0 + 3006dd6: 28e1 jal ra,3006eae + 3006dd8: a001 j 3006dd8 + if (uartHandle->rxState == UART_STATE_BUSY_RX) { + 3006dda: fdc42783 lw a5,-36(s0) + 3006dde: 47f8 lw a4,76(a5) + 3006de0: 4791 li a5,4 + 3006de2: 0cf71163 bne a4,a5,3006ea4 + unsigned int tmp; + while (uartHandle->rxBuffSize > 0) { + 3006de6: a889 j 3006e38 + if (uartHandle->baseAddress->UART_FR.BIT.rxfe == 0x01) { /* True when the RX FIFO is empty */ + 3006de8: fdc42783 lw a5,-36(s0) + 3006dec: 439c lw a5,0(a5) + 3006dee: 4f9c lw a5,24(a5) + 3006df0: 8391 srli a5,a5,0x4 + 3006df2: 8b85 andi a5,a5,1 + 3006df4: 0ff7f713 andi a4,a5,255 + 3006df8: 4785 li a5,1 + 3006dfa: 04f70463 beq a4,a5,3006e42 + break; + } + tmp = uartHandle->baseAddress->UART_DR.reg; + 3006dfe: fdc42783 lw a5,-36(s0) + 3006e02: 439c lw a5,0(a5) + 3006e04: 439c lw a5,0(a5) + 3006e06: fef42623 sw a5,-20(s0) + *(uartHandle->rxbuff) = (tmp & 0xFF); /* Read from DR when holding register/FIFO is not empty */ + 3006e0a: fdc42783 lw a5,-36(s0) + 3006e0e: 539c lw a5,32(a5) + 3006e10: fec42703 lw a4,-20(s0) + 3006e14: 9f01 uxtb a4 + 3006e16: a398 sb a4,0(a5) + uartHandle->rxbuff++; + 3006e18: fdc42783 lw a5,-36(s0) + 3006e1c: 539c lw a5,32(a5) + 3006e1e: 00178713 addi a4,a5,1 + 3006e22: fdc42783 lw a5,-36(s0) + 3006e26: d398 sw a4,32(a5) + uartHandle->rxBuffSize -= 1; + 3006e28: fdc42783 lw a5,-36(s0) + 3006e2c: 579c lw a5,40(a5) + 3006e2e: fff78713 addi a4,a5,-1 + 3006e32: fdc42783 lw a5,-36(s0) + 3006e36: d798 sw a4,40(a5) + while (uartHandle->rxBuffSize > 0) { + 3006e38: fdc42783 lw a5,-36(s0) + 3006e3c: 579c lw a5,40(a5) + 3006e3e: f7cd bnez a5,3006de8 + 3006e40: a011 j 3006e44 + break; + 3006e42: 0001 nop + } + if (uartHandle->rxBuffSize == 0) { + 3006e44: fdc42783 lw a5,-36(s0) + 3006e48: 579c lw a5,40(a5) + 3006e4a: e38d bnez a5,3006e6c + uartHandle->baseAddress->UART_IMSC.reg &= 0xFFFDFFAF; /* Disable rxim ,rtim and rxfneim */ + 3006e4c: fdc42783 lw a5,-36(s0) + 3006e50: 439c lw a5,0(a5) + 3006e52: 5f94 lw a3,56(a5) + 3006e54: fdc42783 lw a5,-36(s0) + 3006e58: 439c lw a5,0(a5) + 3006e5a: 7701 lui a4,0xfffe0 + 3006e5c: faf70713 addi a4,a4,-81 # fffdffaf + 3006e60: 8f75 and a4,a4,a3 + 3006e62: df98 sw a4,56(a5) + uartHandle->rxState = UART_STATE_READY; + 3006e64: fdc42783 lw a5,-36(s0) + 3006e68: 4705 li a4,1 + 3006e6a: c7f8 sw a4,76(a5) + } + uartHandle->baseAddress->UART_ICR.reg |= 0x20050; /* Clear rxic, rtic and rxfneic */ + 3006e6c: fdc42783 lw a5,-36(s0) + 3006e70: 439c lw a5,0(a5) + 3006e72: 43f4 lw a3,68(a5) + 3006e74: fdc42783 lw a5,-36(s0) + 3006e78: 439c lw a5,0(a5) + 3006e7a: 00020737 lui a4,0x20 + 3006e7e: 05070713 addi a4,a4,80 # 20050 + 3006e82: 8f55 or a4,a4,a3 + 3006e84: c3f8 sw a4,68(a5) + if (uartHandle->userCallBack.ReadItFinishCallBack != NULL && uartHandle->rxBuffSize == 0) { + 3006e86: fdc42783 lw a5,-36(s0) + 3006e8a: 4fbc lw a5,88(a5) + 3006e8c: cf81 beqz a5,3006ea4 + 3006e8e: fdc42783 lw a5,-36(s0) + 3006e92: 579c lw a5,40(a5) + 3006e94: eb81 bnez a5,3006ea4 + uartHandle->userCallBack.ReadItFinishCallBack(uartHandle); + 3006e96: fdc42783 lw a5,-36(s0) + 3006e9a: 4fbc lw a5,88(a5) + 3006e9c: fdc42503 lw a0,-36(s0) + 3006ea0: 9782 jalr a5 + } + } + return; + 3006ea2: 0001 nop + 3006ea4: 0001 nop +} + 3006ea6: 50b2 lw ra,44(sp) + 3006ea8: 5422 lw s0,40(sp) + 3006eaa: 6145 addi sp,sp,48 + 3006eac: 8082 ret + +03006eae : + 3006eae: b5afa06f j 3001208 + +03006eb2 : + * @brief Error handler function of receiving. + * @param uartHandle UART handle. + * @retval None. + */ +static void ErrorServiceCallback(UART_Handle *uartHandle) +{ + 3006eb2: 7179 addi sp,sp,-48 + 3006eb4: d606 sw ra,44(sp) + 3006eb6: d422 sw s0,40(sp) + 3006eb8: 1800 addi s0,sp,48 + 3006eba: fca42e23 sw a0,-36(s0) + unsigned int error = 0x00; + 3006ebe: fe042623 sw zero,-20(s0) + if (uartHandle->baseAddress->UART_MIS.BIT.oemis == BASE_CFG_ENABLE) { /* Overflow error interrupt */ + 3006ec2: fdc42783 lw a5,-36(s0) + 3006ec6: 439c lw a5,0(a5) + 3006ec8: 43bc lw a5,64(a5) + 3006eca: 83a9 srli a5,a5,0xa + 3006ecc: 8b85 andi a5,a5,1 + 3006ece: 0ff7f713 andi a4,a5,255 + 3006ed2: 4785 li a5,1 + 3006ed4: 02f71763 bne a4,a5,3006f02 + error |= uartHandle->baseAddress->UART_MIS.BIT.oemis; + 3006ed8: fdc42783 lw a5,-36(s0) + 3006edc: 439c lw a5,0(a5) + 3006ede: 43bc lw a5,64(a5) + 3006ee0: 83a9 srli a5,a5,0xa + 3006ee2: 8b85 andi a5,a5,1 + 3006ee4: 9f81 uxtb a5 + 3006ee6: 873e mv a4,a5 + 3006ee8: fec42783 lw a5,-20(s0) + 3006eec: 8fd9 or a5,a5,a4 + 3006eee: fef42623 sw a5,-20(s0) + uartHandle->baseAddress->UART_ICR.BIT.oeic = BASE_CFG_ENABLE; + 3006ef2: fdc42783 lw a5,-36(s0) + 3006ef6: 4398 lw a4,0(a5) + 3006ef8: 437c lw a5,68(a4) + 3006efa: 4007e793 ori a5,a5,1024 + 3006efe: c37c sw a5,68(a4) + 3006f00: a0c1 j 3006fc0 + } else if (uartHandle->baseAddress->UART_MIS.BIT.bemis == BASE_CFG_ENABLE) { /* Break error interrupt */ + 3006f02: fdc42783 lw a5,-36(s0) + 3006f06: 439c lw a5,0(a5) + 3006f08: 43bc lw a5,64(a5) + 3006f0a: 83a5 srli a5,a5,0x9 + 3006f0c: 8b85 andi a5,a5,1 + 3006f0e: 0ff7f713 andi a4,a5,255 + 3006f12: 4785 li a5,1 + 3006f14: 02f71763 bne a4,a5,3006f42 + error |= uartHandle->baseAddress->UART_MIS.BIT.bemis; + 3006f18: fdc42783 lw a5,-36(s0) + 3006f1c: 439c lw a5,0(a5) + 3006f1e: 43bc lw a5,64(a5) + 3006f20: 83a5 srli a5,a5,0x9 + 3006f22: 8b85 andi a5,a5,1 + 3006f24: 9f81 uxtb a5 + 3006f26: 873e mv a4,a5 + 3006f28: fec42783 lw a5,-20(s0) + 3006f2c: 8fd9 or a5,a5,a4 + 3006f2e: fef42623 sw a5,-20(s0) + uartHandle->baseAddress->UART_ICR.BIT.beic = BASE_CFG_ENABLE; + 3006f32: fdc42783 lw a5,-36(s0) + 3006f36: 4398 lw a4,0(a5) + 3006f38: 437c lw a5,68(a4) + 3006f3a: 2007e793 ori a5,a5,512 + 3006f3e: c37c sw a5,68(a4) + 3006f40: a041 j 3006fc0 + } else if (uartHandle->baseAddress->UART_MIS.BIT.pemis == BASE_CFG_ENABLE) { /* Check error interrupt */ + 3006f42: fdc42783 lw a5,-36(s0) + 3006f46: 439c lw a5,0(a5) + 3006f48: 43bc lw a5,64(a5) + 3006f4a: 83a1 srli a5,a5,0x8 + 3006f4c: 8b85 andi a5,a5,1 + 3006f4e: 0ff7f713 andi a4,a5,255 + 3006f52: 4785 li a5,1 + 3006f54: 02f71763 bne a4,a5,3006f82 + error |= uartHandle->baseAddress->UART_MIS.BIT.pemis; + 3006f58: fdc42783 lw a5,-36(s0) + 3006f5c: 439c lw a5,0(a5) + 3006f5e: 43bc lw a5,64(a5) + 3006f60: 83a1 srli a5,a5,0x8 + 3006f62: 8b85 andi a5,a5,1 + 3006f64: 9f81 uxtb a5 + 3006f66: 873e mv a4,a5 + 3006f68: fec42783 lw a5,-20(s0) + 3006f6c: 8fd9 or a5,a5,a4 + 3006f6e: fef42623 sw a5,-20(s0) + uartHandle->baseAddress->UART_ICR.BIT.peic = BASE_CFG_ENABLE; + 3006f72: fdc42783 lw a5,-36(s0) + 3006f76: 4398 lw a4,0(a5) + 3006f78: 437c lw a5,68(a4) + 3006f7a: 1007e793 ori a5,a5,256 + 3006f7e: c37c sw a5,68(a4) + 3006f80: a081 j 3006fc0 + } else if (uartHandle->baseAddress->UART_MIS.BIT.femis == BASE_CFG_ENABLE) { /* Frame error interrupt */ + 3006f82: fdc42783 lw a5,-36(s0) + 3006f86: 439c lw a5,0(a5) + 3006f88: 43bc lw a5,64(a5) + 3006f8a: 839d srli a5,a5,0x7 + 3006f8c: 8b85 andi a5,a5,1 + 3006f8e: 0ff7f713 andi a4,a5,255 + 3006f92: 4785 li a5,1 + 3006f94: 02f71663 bne a4,a5,3006fc0 + error |= uartHandle->baseAddress->UART_MIS.BIT.femis; + 3006f98: fdc42783 lw a5,-36(s0) + 3006f9c: 439c lw a5,0(a5) + 3006f9e: 43bc lw a5,64(a5) + 3006fa0: 839d srli a5,a5,0x7 + 3006fa2: 8b85 andi a5,a5,1 + 3006fa4: 9f81 uxtb a5 + 3006fa6: 873e mv a4,a5 + 3006fa8: fec42783 lw a5,-20(s0) + 3006fac: 8fd9 or a5,a5,a4 + 3006fae: fef42623 sw a5,-20(s0) + uartHandle->baseAddress->UART_ICR.BIT.feic = BASE_CFG_ENABLE; + 3006fb2: fdc42783 lw a5,-36(s0) + 3006fb6: 4398 lw a4,0(a5) + 3006fb8: 437c lw a5,68(a4) + 3006fba: 0807e793 ori a5,a5,128 + 3006fbe: c37c sw a5,68(a4) + } + if (error != 0x00) { + 3006fc0: fec42783 lw a5,-20(s0) + 3006fc4: c79d beqz a5,3006ff2 + uartHandle->errorType = error; + 3006fc6: fdc42783 lw a5,-36(s0) + 3006fca: fec42703 lw a4,-20(s0) + 3006fce: cbb8 sw a4,80(a5) + if (uartHandle->rxMode == UART_MODE_INTERRUPT && uartHandle->userCallBack.TransmitItErrorCallBack != NULL) { + 3006fd0: fdc42783 lw a5,-36(s0) + 3006fd4: 4f98 lw a4,24(a5) + 3006fd6: 4785 li a5,1 + 3006fd8: 00f71d63 bne a4,a5,3006ff2 + 3006fdc: fdc42783 lw a5,-36(s0) + 3006fe0: 53fc lw a5,100(a5) + 3006fe2: cb81 beqz a5,3006ff2 + uartHandle->userCallBack.TransmitItErrorCallBack(uartHandle); + 3006fe4: fdc42783 lw a5,-36(s0) + 3006fe8: 53fc lw a5,100(a5) + 3006fea: fdc42503 lw a0,-36(s0) + 3006fee: 9782 jalr a5 + } + } + return; + 3006ff0: 0001 nop + 3006ff2: 0001 nop +} + 3006ff4: 50b2 lw ra,44(sp) + 3006ff6: 5422 lw s0,40(sp) + 3006ff8: 6145 addi sp,sp,48 + 3006ffa: 8082 ret + +03006ffc : + * @brief UART Interrupt service processing function. + * @param handle UART handle. + * @retval None. + */ +void HAL_UART_IrqHandler(void *handle) +{ + 3006ffc: 7179 addi sp,sp,-48 + 3006ffe: d606 sw ra,44(sp) + 3007000: d422 sw s0,40(sp) + 3007002: 1800 addi s0,sp,48 + 3007004: fca42e23 sw a0,-36(s0) + UART_ASSERT_PARAM(handle != NULL); + 3007008: fdc42783 lw a5,-36(s0) + 300700c: eb89 bnez a5,300701e + 300700e: 2d200593 li a1,722 + 3007012: 030097b7 lui a5,0x3009 + 3007016: ac078513 addi a0,a5,-1344 # 3008ac0 + 300701a: 3d51 jal ra,3006eae + 300701c: a001 j 300701c + UART_Handle *uartHandle = (UART_Handle *)handle; + 300701e: fdc42783 lw a5,-36(s0) + 3007022: fef42623 sw a5,-20(s0) + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + 3007026: fec42783 lw a5,-20(s0) + 300702a: 4398 lw a4,0(a5) + 300702c: 140007b7 lui a5,0x14000 + 3007030: 02f70f63 beq a4,a5,300706e + 3007034: fec42783 lw a5,-20(s0) + 3007038: 4398 lw a4,0(a5) + 300703a: 140017b7 lui a5,0x14001 + 300703e: 02f70863 beq a4,a5,300706e + 3007042: fec42783 lw a5,-20(s0) + 3007046: 4398 lw a4,0(a5) + 3007048: 140027b7 lui a5,0x14002 + 300704c: 02f70163 beq a4,a5,300706e + 3007050: fec42783 lw a5,-20(s0) + 3007054: 4398 lw a4,0(a5) + 3007056: 140037b7 lui a5,0x14003 + 300705a: 00f70a63 beq a4,a5,300706e + 300705e: 2d400593 li a1,724 + 3007062: 030097b7 lui a5,0x3009 + 3007066: ac078513 addi a0,a5,-1344 # 3008ac0 + 300706a: 3591 jal ra,3006eae + 300706c: a001 j 300706c + /* when tx interrupt is generated */ + if ((uartHandle->baseAddress->UART_MIS.BIT.txmis == 0x01) || + 300706e: fec42783 lw a5,-20(s0) + 3007072: 439c lw a5,0(a5) + 3007074: 43bc lw a5,64(a5) + 3007076: 8395 srli a5,a5,0x5 + 3007078: 8b85 andi a5,a5,1 + 300707a: 0ff7f713 andi a4,a5,255 + 300707e: 4785 li a5,1 + 3007080: 00f70d63 beq a4,a5,300709a + (uartHandle->baseAddress->UART_MIS.BIT.txfeis == 0x01)) { + 3007084: fec42783 lw a5,-20(s0) + 3007088: 439c lw a5,0(a5) + 300708a: 43bc lw a5,64(a5) + 300708c: 83b1 srli a5,a5,0xc + 300708e: 8b85 andi a5,a5,1 + 3007090: 0ff7f713 andi a4,a5,255 + if ((uartHandle->baseAddress->UART_MIS.BIT.txmis == 0x01) || + 3007094: 4785 li a5,1 + 3007096: 00f71563 bne a4,a5,30070a0 + WriteITCallBack(uartHandle); + 300709a: fec42503 lw a0,-20(s0) + 300709e: 3c1d jal ra,3006ad4 + } + /* when rx interrupt is generated */ + if ((uartHandle->baseAddress->UART_MIS.BIT.rxmis == 0x01 || uartHandle->baseAddress->UART_MIS.BIT.rtmis == 0x01) || + 30070a0: fec42783 lw a5,-20(s0) + 30070a4: 439c lw a5,0(a5) + 30070a6: 43bc lw a5,64(a5) + 30070a8: 8391 srli a5,a5,0x4 + 30070aa: 8b85 andi a5,a5,1 + 30070ac: 0ff7f713 andi a4,a5,255 + 30070b0: 4785 li a5,1 + 30070b2: 02f70863 beq a4,a5,30070e2 + 30070b6: fec42783 lw a5,-20(s0) + 30070ba: 439c lw a5,0(a5) + 30070bc: 43bc lw a5,64(a5) + 30070be: 8399 srli a5,a5,0x6 + 30070c0: 8b85 andi a5,a5,1 + 30070c2: 0ff7f713 andi a4,a5,255 + 30070c6: 4785 li a5,1 + 30070c8: 00f70d63 beq a4,a5,30070e2 + (uartHandle->baseAddress->UART_MIS.BIT.rxfneis == 0x1)) { + 30070cc: fec42783 lw a5,-20(s0) + 30070d0: 439c lw a5,0(a5) + 30070d2: 43bc lw a5,64(a5) + 30070d4: 83c5 srli a5,a5,0x11 + 30070d6: 8b85 andi a5,a5,1 + 30070d8: 0ff7f713 andi a4,a5,255 + if ((uartHandle->baseAddress->UART_MIS.BIT.rxmis == 0x01 || uartHandle->baseAddress->UART_MIS.BIT.rtmis == 0x01) || + 30070dc: 4785 li a5,1 + 30070de: 00f71563 bne a4,a5,30070e8 + ReadITCallBack(uartHandle); + 30070e2: fec42503 lw a0,-20(s0) + 30070e6: 398d jal ra,3006d58 + } + /* when charter match interrupt is generated */ + if (uartHandle->baseAddress->UART_MIS.BIT.cmis == 0x01) { + 30070e8: fec42783 lw a5,-20(s0) + 30070ec: 439c lw a5,0(a5) + 30070ee: 43bc lw a5,64(a5) + 30070f0: 83d5 srli a5,a5,0x15 + 30070f2: 8b85 andi a5,a5,1 + 30070f4: 0ff7f713 andi a4,a5,255 + 30070f8: 4785 li a5,1 + 30070fa: 00f71663 bne a4,a5,3007106 + CharterMatchCallBack(uartHandle); + 30070fe: fec42503 lw a0,-20(s0) + 3007102: afaff0ef jal ra,30063fc + } + /* when baud detect interrupt is generated */ + if (uartHandle->baseAddress->UART_MIS.BIT.abdcis == 0x01 || uartHandle->baseAddress->UART_MIS.BIT.abdeis == 0x01) { + 3007106: fec42783 lw a5,-20(s0) + 300710a: 439c lw a5,0(a5) + 300710c: 43bc lw a5,64(a5) + 300710e: 83cd srli a5,a5,0x13 + 3007110: 8b85 andi a5,a5,1 + 3007112: 0ff7f713 andi a4,a5,255 + 3007116: 4785 li a5,1 + 3007118: 00f70d63 beq a4,a5,3007132 + 300711c: fec42783 lw a5,-20(s0) + 3007120: 439c lw a5,0(a5) + 3007122: 43bc lw a5,64(a5) + 3007124: 83d1 srli a5,a5,0x14 + 3007126: 8b85 andi a5,a5,1 + 3007128: 0ff7f713 andi a4,a5,255 + 300712c: 4785 li a5,1 + 300712e: 00f71663 bne a4,a5,300713a + BaudDetectCallBack(uartHandle); + 3007132: fec42503 lw a0,-20(s0) + 3007136: 9eaff0ef jal ra,3006320 + } + /* when error interrupt is generated */ + if ((uartHandle->baseAddress->UART_MIS.reg & 0x780) != 0) { + 300713a: fec42783 lw a5,-20(s0) + 300713e: 439c lw a5,0(a5) + 3007140: 43bc lw a5,64(a5) + 3007142: 7807f793 andi a5,a5,1920 + 3007146: c789 beqz a5,3007150 + ErrorServiceCallback(uartHandle); + 3007148: fec42503 lw a0,-20(s0) + 300714c: 339d jal ra,3006eb2 + } + return; + 300714e: 0001 nop + 3007150: 0001 nop +} + 3007152: 50b2 lw ra,44(sp) + 3007154: 5422 lw s0,40(sp) + 3007156: 6145 addi sp,sp,48 + 3007158: 8082 ret + +0300715a : + * @param pCallback pointer of the specified callbcak function, @ref UART_CallbackType + * @retval BASE_StatusType: OK, ERROR. + */ +BASE_StatusType HAL_UART_RegisterCallBack(UART_Handle *uartHandle, UART_CallbackFun_Type typeID, + UART_CallbackType pCallback) +{ + 300715a: 1101 addi sp,sp,-32 + 300715c: ce06 sw ra,28(sp) + 300715e: cc22 sw s0,24(sp) + 3007160: 1000 addi s0,sp,32 + 3007162: fea42623 sw a0,-20(s0) + 3007166: feb42423 sw a1,-24(s0) + 300716a: fec42223 sw a2,-28(s0) + UART_ASSERT_PARAM(uartHandle != NULL); + 300716e: fec42783 lw a5,-20(s0) + 3007172: eb89 bnez a5,3007184 + 3007174: 2f800593 li a1,760 + 3007178: 030097b7 lui a5,0x3009 + 300717c: ac078513 addi a0,a5,-1344 # 3008ac0 + 3007180: 333d jal ra,3006eae + 3007182: a001 j 3007182 + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + 3007184: fec42783 lw a5,-20(s0) + 3007188: 4398 lw a4,0(a5) + 300718a: 140007b7 lui a5,0x14000 + 300718e: 02f70f63 beq a4,a5,30071cc + 3007192: fec42783 lw a5,-20(s0) + 3007196: 4398 lw a4,0(a5) + 3007198: 140017b7 lui a5,0x14001 + 300719c: 02f70863 beq a4,a5,30071cc + 30071a0: fec42783 lw a5,-20(s0) + 30071a4: 4398 lw a4,0(a5) + 30071a6: 140027b7 lui a5,0x14002 + 30071aa: 02f70163 beq a4,a5,30071cc + 30071ae: fec42783 lw a5,-20(s0) + 30071b2: 4398 lw a4,0(a5) + 30071b4: 140037b7 lui a5,0x14003 + 30071b8: 00f70a63 beq a4,a5,30071cc + 30071bc: 2f900593 li a1,761 + 30071c0: 030097b7 lui a5,0x3009 + 30071c4: ac078513 addi a0,a5,-1344 # 3008ac0 + 30071c8: 31dd jal ra,3006eae + 30071ca: a001 j 30071ca + switch (typeID) { + 30071cc: fe842703 lw a4,-24(s0) + 30071d0: 47a1 li a5,8 + 30071d2: 08e7e363 bltu a5,a4,3007258 + 30071d6: fe842783 lw a5,-24(s0) + 30071da: 00279713 slli a4,a5,0x2 + 30071de: 030097b7 lui a5,0x3009 + 30071e2: adc78793 addi a5,a5,-1316 # 3008adc + 30071e6: 97ba add a5,a5,a4 + 30071e8: 439c lw a5,0(a5) + 30071ea: 8782 jr a5 + case UART_WRITE_IT_FINISH: + uartHandle->userCallBack.WriteItFinishCallBack = pCallback; /* Write INT finish callback register */ + 30071ec: fec42783 lw a5,-20(s0) + 30071f0: fe442703 lw a4,-28(s0) + 30071f4: cbf8 sw a4,84(a5) + break; + 30071f6: a09d j 300725c + case UART_READ_IT_FINISH: + uartHandle->userCallBack.ReadItFinishCallBack = pCallback; /* Read INT finish callback register */ + 30071f8: fec42783 lw a5,-20(s0) + 30071fc: fe442703 lw a4,-28(s0) + 3007200: cfb8 sw a4,88(a5) + break; + 3007202: a8a9 j 300725c + case UART_WRITE_DMA_FINISH: + uartHandle->userCallBack.WriteDmaFinishCallBack = pCallback; /* DMA write finish callback register */ + 3007204: fec42783 lw a5,-20(s0) + 3007208: fe442703 lw a4,-28(s0) + 300720c: cff8 sw a4,92(a5) + break; + 300720e: a0b9 j 300725c + case UART_READ_DMA_FINISH: + uartHandle->userCallBack.ReadDmaFinishCallBack = pCallback; /* DMA read finish callback register */ + 3007210: fec42783 lw a5,-20(s0) + 3007214: fe442703 lw a4,-28(s0) + 3007218: d3b8 sw a4,96(a5) + break; + 300721a: a089 j 300725c + case UART_TRNS_IT_ERROR: + uartHandle->userCallBack.TransmitItErrorCallBack = pCallback; /* INT Trans error callback register */ + 300721c: fec42783 lw a5,-20(s0) + 3007220: fe442703 lw a4,-28(s0) + 3007224: d3f8 sw a4,100(a5) + break; + 3007226: a81d j 300725c + case UART_TRNS_DMA_ERROR: + uartHandle->userCallBack.TransmitDmaErrorCallBack = pCallback; /* DMA Trans error callback register */ + 3007228: fec42783 lw a5,-20(s0) + 300722c: fe442703 lw a4,-28(s0) + 3007230: d7b8 sw a4,104(a5) + break; + 3007232: a02d j 300725c + case UART_BAUD_DETECT_FINISH: + uartHandle->userCallBack.BaudDetectSuccessCallBack = pCallback; /* Baud detect finish callback register */ + 3007234: fec42783 lw a5,-20(s0) + 3007238: fe442703 lw a4,-28(s0) + 300723c: d7f8 sw a4,108(a5) + break; + 300723e: a839 j 300725c + case UART_BAUD_DETECT_ERROR: + uartHandle->userCallBack.BaudDetectErrorCallBack = pCallback; /* Baud detect error callback register */ + 3007240: fec42783 lw a5,-20(s0) + 3007244: fe442703 lw a4,-28(s0) + 3007248: dbb8 sw a4,112(a5) + break; + 300724a: a809 j 300725c + case UART_CHARACTER_MATCH: + uartHandle->userCallBack.CharacterMatchCallBack = pCallback; /* character match callback register */ + 300724c: fec42783 lw a5,-20(s0) + 3007250: fe442703 lw a4,-28(s0) + 3007254: dbf8 sw a4,116(a5) + break; + 3007256: a019 j 300725c + default: + return BASE_STATUS_ERROR; + 3007258: 4785 li a5,1 + 300725a: a011 j 300725e + } + return BASE_STATUS_OK; + 300725c: 4781 li a5,0 +} + 300725e: 853e mv a0,a5 + 3007260: 40f2 lw ra,28(sp) + 3007262: 4462 lw s0,24(sp) + 3007264: 6105 addi sp,sp,32 + 3007266: 8082 ret + +03007268
: +unsigned long g_timer0_count = 0; +unsigned long g_timer1_count = 0; +/* USER CODE END 1 */ + +int main(void) +{ + 3007268: 1141 addi sp,sp,-16 + 300726a: c606 sw ra,12(sp) + 300726c: c422 sw s0,8(sp) + 300726e: 0800 addi s0,sp,16 + /* USER CODE BEGIN 2 */ + /* 建议用户放置初始化代码或启动代码等 */ + /* USER CODE END 2 */ + SystemInit(); + 3007270: 42e010ef jal ra,300869e + /* USER CODE BEGIN 3 */ + /* 建议用户放置初始配置代码 */ + HAL_UART_ReadIT(&g_uart0, &g_uart0_rxdata, 1); + 3007274: 4605 li a2,1 + 3007276: 040007b7 lui a5,0x4000 + 300727a: 78c78593 addi a1,a5,1932 # 400078c + 300727e: 040007b7 lui a5,0x4000 + 3007282: 50478513 addi a0,a5,1284 # 4000504 + 3007286: 3245 jal ra,3006c26 + HAL_UART_ReadIT(&g_uart2, &g_uart2_rxdata, 1); + 3007288: 4605 li a2,1 + 300728a: 040007b7 lui a5,0x4000 + 300728e: 7fc78593 addi a1,a5,2044 # 40007fc + 3007292: 040007b7 lui a5,0x4000 + 3007296: 58478513 addi a0,a5,1412 # 4000584 + 300729a: 3271 jal ra,3006c26 + HAL_TIMER_Start(&g_timer0); + 300729c: 040007b7 lui a5,0x4000 + 30072a0: 4b478513 addi a0,a5,1204 # 40004b4 + 30072a4: d5ffe0ef jal ra,3006002 + HAL_TIMER_Start(&g_timer1); + 30072a8: 040007b7 lui a5,0x4000 + 30072ac: 4dc78513 addi a0,a5,1244 # 40004dc + 30072b0: d53fe0ef jal ra,3006002 + PAJ7620U2_Init(); + 30072b4: 2bd5 jal ra,30078a8 + /* USER CODE END 3 */ + while (1) { + /* USER CODE BEGIN 4 */ + /* 建议用户放置周期性执行代码 */ + if (g_uart0_rxin != g_uart0_rxout) + 30072b6: 040007b7 lui a5,0x4000 + 30072ba: 7f47a703 lw a4,2036(a5) # 40007f4 + 30072be: 040007b7 lui a5,0x4000 + 30072c2: 7f87a783 lw a5,2040(a5) # 40007f8 + 30072c6: 04f70663 beq a4,a5,3007312 + { + HAL_UART_WriteBlocking(&g_uart0, &g_uart0_rxbuff[g_uart0_rxout++], 1, 1000); + 30072ca: 040007b7 lui a5,0x4000 + 30072ce: 7f87a783 lw a5,2040(a5) # 40007f8 + 30072d2: 00178693 addi a3,a5,1 + 30072d6: 04000737 lui a4,0x4000 + 30072da: 7ed72c23 sw a3,2040(a4) # 40007f8 + 30072de: 04000737 lui a4,0x4000 + 30072e2: 79070713 addi a4,a4,1936 # 4000790 + 30072e6: 97ba add a5,a5,a4 + 30072e8: 3e800693 li a3,1000 + 30072ec: 4605 li a2,1 + 30072ee: 85be mv a1,a5 + 30072f0: 040007b7 lui a5,0x4000 + 30072f4: 50478513 addi a0,a5,1284 # 4000504 + 30072f8: 2579 jal ra,3007986 + g_uart0_rxout %= 100; + 30072fa: 040007b7 lui a5,0x4000 + 30072fe: 7f87a703 lw a4,2040(a5) # 40007f8 + 3007302: 06400793 li a5,100 + 3007306: 02f77733 remu a4,a4,a5 + 300730a: 040007b7 lui a5,0x4000 + 300730e: 7ee7ac23 sw a4,2040(a5) # 40007f8 + } + + if (g_uart2_rxin != g_uart2_rxout) + 3007312: 040037b7 lui a5,0x4003 + 3007316: 0007a703 lw a4,0(a5) # 4003000 + 300731a: 040037b7 lui a5,0x4003 + 300731e: 0047a783 lw a5,4(a5) # 4003004 + 3007322: 10f70963 beq a4,a5,3007434 + { + g_asr_cmd_id[0] = g_asr_cmd_id[1]; + 3007326: 040037b7 lui a5,0x4003 + 300732a: 00878793 addi a5,a5,8 # 4003008 + 300732e: 3398 lbu a4,1(a5) + 3007330: 040037b7 lui a5,0x4003 + 3007334: 00e78423 sb a4,8(a5) # 4003008 + g_asr_cmd_id[1] = g_asr_cmd_id[2]; + 3007338: 040037b7 lui a5,0x4003 + 300733c: 00878793 addi a5,a5,8 # 4003008 + 3007340: 23b8 lbu a4,2(a5) + 3007342: 040037b7 lui a5,0x4003 + 3007346: 00878793 addi a5,a5,8 # 4003008 + 300734a: b398 sb a4,1(a5) + g_asr_cmd_id[2] = g_asr_cmd_id[3]; + 300734c: 040037b7 lui a5,0x4003 + 3007350: 00878793 addi a5,a5,8 # 4003008 + 3007354: 33b8 lbu a4,3(a5) + 3007356: 040037b7 lui a5,0x4003 + 300735a: 00878793 addi a5,a5,8 # 4003008 + 300735e: a3b8 sb a4,2(a5) + g_asr_cmd_id[3] = g_uart2_rxbuff[g_uart2_rxout]; + 3007360: 040037b7 lui a5,0x4003 + 3007364: 0047a783 lw a5,4(a5) # 4003004 + 3007368: 04001737 lui a4,0x4001 + 300736c: 80070713 addi a4,a4,-2048 # 4000800 + 3007370: 97ba add a5,a5,a4 + 3007372: 2398 lbu a4,0(a5) + 3007374: 040037b7 lui a5,0x4003 + 3007378: 00878793 addi a5,a5,8 # 4003008 + 300737c: b3b8 sb a4,3(a5) + + HAL_UART_WriteBlocking(&g_uart0, &g_uart2_rxbuff[g_uart2_rxout++], 1, 1000); + 300737e: 040037b7 lui a5,0x4003 + 3007382: 0047a783 lw a5,4(a5) # 4003004 + 3007386: 00178693 addi a3,a5,1 + 300738a: 04003737 lui a4,0x4003 + 300738e: 00d72223 sw a3,4(a4) # 4003004 + 3007392: 04001737 lui a4,0x4001 + 3007396: 80070713 addi a4,a4,-2048 # 4000800 + 300739a: 97ba add a5,a5,a4 + 300739c: 3e800693 li a3,1000 + 30073a0: 4605 li a2,1 + 30073a2: 85be mv a1,a5 + 30073a4: 040007b7 lui a5,0x4000 + 30073a8: 50478513 addi a0,a5,1284 # 4000504 + 30073ac: 2be9 jal ra,3007986 + g_uart2_rxout %= (10 * 1024); + 30073ae: 040037b7 lui a5,0x4003 + 30073b2: 0047a703 lw a4,4(a5) # 4003004 + 30073b6: 678d lui a5,0x3 + 30073b8: 80078793 addi a5,a5,-2048 # 2800 + 30073bc: 02f77733 remu a4,a4,a5 + 30073c0: 040037b7 lui a5,0x4003 + 30073c4: 00e7a223 sw a4,4(a5) # 4003004 + + if ( + (g_asr_cmd_id[0] == '1') && (g_asr_cmd_id[1] == '0') && (g_asr_cmd_id[2] == '0') + 30073c8: 040037b7 lui a5,0x4003 + 30073cc: 0087c703 lbu a4,8(a5) # 4003008 + if ( + 30073d0: 03100793 li a5,49 + 30073d4: 06f71063 bne a4,a5,3007434 + (g_asr_cmd_id[0] == '1') && (g_asr_cmd_id[1] == '0') && (g_asr_cmd_id[2] == '0') + 30073d8: 040037b7 lui a5,0x4003 + 30073dc: 00878793 addi a5,a5,8 # 4003008 + 30073e0: 3398 lbu a4,1(a5) + 30073e2: 03000793 li a5,48 + 30073e6: 04f71763 bne a4,a5,3007434 + 30073ea: 040037b7 lui a5,0x4003 + 30073ee: 00878793 addi a5,a5,8 # 4003008 + 30073f2: 23b8 lbu a4,2(a5) + 30073f4: 03000793 li a5,48 + 30073f8: 02f71e63 bne a4,a5,3007434 + ) + { + if (g_asr_cmd_id[3] == '1') + 30073fc: 040037b7 lui a5,0x4003 + 3007400: 00878793 addi a5,a5,8 # 4003008 + 3007404: 33b8 lbu a4,3(a5) + 3007406: 03100793 li a5,49 + 300740a: 00f71763 bne a4,a5,3007418 + { + g_step_motor_flag = 0; + 300740e: 040037b7 lui a5,0x4003 + 3007412: 000786a3 sb zero,13(a5) # 400300d + 3007416: a839 j 3007434 + } + else if (g_asr_cmd_id[3] == '2') + 3007418: 040037b7 lui a5,0x4003 + 300741c: 00878793 addi a5,a5,8 # 4003008 + 3007420: 33b8 lbu a4,3(a5) + 3007422: 03200793 li a5,50 + 3007426: 00f71763 bne a4,a5,3007434 + { + g_step_motor_flag = 1; + 300742a: 040037b7 lui a5,0x4003 + 300742e: 4705 li a4,1 + 3007430: 00e786a3 sb a4,13(a5) # 400300d + // + } + } + } + + PAJ7620U2_Handler(); + 3007434: 2b99 jal ra,300798a + if (g_uart0_rxin != g_uart0_rxout) + 3007436: b541 j 30072b6 + +03007438 : +} + +/* USER CODE BEGIN 6 */ +/* 建议用户放置自定义函数 */ +void GPIO2_4_CallbackFunc(void *param) +{ + 3007438: 7179 addi sp,sp,-48 + 300743a: d606 sw ra,44(sp) + 300743c: d422 sw s0,40(sp) + 300743e: 1800 addi s0,sp,48 + 3007440: fca42e23 sw a0,-36(s0) + GPIO_Handle *handle = (GPIO_Handle *)param; + 3007444: fdc42783 lw a5,-36(s0) + 3007448: fef42623 sw a5,-20(s0) + BASE_FUNC_UNUSED(handle); + + if (g_step_motor_flag == 0) + 300744c: 040037b7 lui a5,0x4003 + 3007450: 00d7c783 lbu a5,13(a5) # 400300d + 3007454: ef91 bnez a5,3007470 + { + g_step_motor_flag = 1; + 3007456: 040037b7 lui a5,0x4003 + 300745a: 4705 li a4,1 + 300745c: 00e786a3 sb a4,13(a5) # 400300d + HAL_GPIO_SetValue(&g_gpio2, GPIO_PIN_3, GPIO_LOW_LEVEL); + 3007460: 4601 li a2,0 + 3007462: 45a1 li a1,8 + 3007464: 040007b7 lui a5,0x4000 + 3007468: 66c78513 addi a0,a5,1644 # 400066c + 300746c: 260d jal ra,300778e + else + { + g_step_motor_flag = 0; + HAL_GPIO_SetValue(&g_gpio2, GPIO_PIN_3, GPIO_HIGH_LEVEL); + } +} + 300746e: a821 j 3007486 + g_step_motor_flag = 0; + 3007470: 040037b7 lui a5,0x4003 + 3007474: 000786a3 sb zero,13(a5) # 400300d + HAL_GPIO_SetValue(&g_gpio2, GPIO_PIN_3, GPIO_HIGH_LEVEL); + 3007478: 4605 li a2,1 + 300747a: 45a1 li a1,8 + 300747c: 040007b7 lui a5,0x4000 + 3007480: 66c78513 addi a0,a5,1644 # 400066c + 3007484: 2629 jal ra,300778e +} + 3007486: 0001 nop + 3007488: 50b2 lw ra,44(sp) + 300748a: 5422 lw s0,40(sp) + 300748c: 6145 addi sp,sp,48 + 300748e: 8082 ret + +03007490 : + +void UART0ReadInterruptCallback(void *handle) +{ + 3007490: 1101 addi sp,sp,-32 + 3007492: ce06 sw ra,28(sp) + 3007494: cc22 sw s0,24(sp) + 3007496: 1000 addi s0,sp,32 + 3007498: fea42623 sw a0,-20(s0) + BASE_FUNC_UNUSED(handle); + /* USER CODE BEGIN UART0_READ_IT_FINISH */ + HAL_UART_ReadIT(&g_uart0, &g_uart0_rxdata, 1); + 300749c: 4605 li a2,1 + 300749e: 040007b7 lui a5,0x4000 + 30074a2: 78c78593 addi a1,a5,1932 # 400078c + 30074a6: 040007b7 lui a5,0x4000 + 30074aa: 50478513 addi a0,a5,1284 # 4000504 + 30074ae: f78ff0ef jal ra,3006c26 + + g_uart0_rxbuff[g_uart0_rxin++] = g_uart0_rxdata; + 30074b2: 040007b7 lui a5,0x4000 + 30074b6: 7f47a783 lw a5,2036(a5) # 40007f4 + 30074ba: 00178693 addi a3,a5,1 + 30074be: 04000737 lui a4,0x4000 + 30074c2: 7ed72a23 sw a3,2036(a4) # 40007f4 + 30074c6: 04000737 lui a4,0x4000 + 30074ca: 78c74703 lbu a4,1932(a4) # 400078c + 30074ce: 040006b7 lui a3,0x4000 + 30074d2: 79068693 addi a3,a3,1936 # 4000790 + 30074d6: 97b6 add a5,a5,a3 + 30074d8: a398 sb a4,0(a5) + g_uart0_rxin %= 100; + 30074da: 040007b7 lui a5,0x4000 + 30074de: 7f47a703 lw a4,2036(a5) # 40007f4 + 30074e2: 06400793 li a5,100 + 30074e6: 02f77733 remu a4,a4,a5 + 30074ea: 040007b7 lui a5,0x4000 + 30074ee: 7ee7aa23 sw a4,2036(a5) # 40007f4 + /* USER CODE END UART0_READ_IT_FINISH */ +} + 30074f2: 0001 nop + 30074f4: 40f2 lw ra,28(sp) + 30074f6: 4462 lw s0,24(sp) + 30074f8: 6105 addi sp,sp,32 + 30074fa: 8082 ret + +030074fc : + +void UART2ReadInterruptCallback(void *handle) +{ + 30074fc: 1101 addi sp,sp,-32 + 30074fe: ce06 sw ra,28(sp) + 3007500: cc22 sw s0,24(sp) + 3007502: 1000 addi s0,sp,32 + 3007504: fea42623 sw a0,-20(s0) + BASE_FUNC_UNUSED(handle); + /* USER CODE BEGIN UART2_READ_IT_FINISH */ + HAL_UART_ReadIT(&g_uart2, &g_uart2_rxdata, 1); + 3007508: 4605 li a2,1 + 300750a: 040007b7 lui a5,0x4000 + 300750e: 7fc78593 addi a1,a5,2044 # 40007fc + 3007512: 040007b7 lui a5,0x4000 + 3007516: 58478513 addi a0,a5,1412 # 4000584 + 300751a: f0cff0ef jal ra,3006c26 + + g_uart2_rxbuff[g_uart2_rxin++] = g_uart2_rxdata; + 300751e: 040037b7 lui a5,0x4003 + 3007522: 0007a783 lw a5,0(a5) # 4003000 + 3007526: 00178693 addi a3,a5,1 + 300752a: 04003737 lui a4,0x4003 + 300752e: 00d72023 sw a3,0(a4) # 4003000 + 3007532: 04000737 lui a4,0x4000 + 3007536: 7fc74703 lbu a4,2044(a4) # 40007fc + 300753a: 040016b7 lui a3,0x4001 + 300753e: 80068693 addi a3,a3,-2048 # 4000800 + 3007542: 97b6 add a5,a5,a3 + 3007544: a398 sb a4,0(a5) + g_uart2_rxin %= (10 * 1024); + 3007546: 040037b7 lui a5,0x4003 + 300754a: 0007a703 lw a4,0(a5) # 4003000 + 300754e: 678d lui a5,0x3 + 3007550: 80078793 addi a5,a5,-2048 # 2800 + 3007554: 02f77733 remu a4,a4,a5 + 3007558: 040037b7 lui a5,0x4003 + 300755c: 00e7a023 sw a4,0(a5) # 4003000 + /* USER CODE END UART2_READ_IT_FINISH */ +} + 3007560: 0001 nop + 3007562: 40f2 lw ra,28(sp) + 3007564: 4462 lw s0,24(sp) + 3007566: 6105 addi sp,sp,32 + 3007568: 8082 ret + +0300756a : + +void TIMER0_InterruptProcess(void *handle) +{ + 300756a: 1101 addi sp,sp,-32 + 300756c: ce06 sw ra,28(sp) + 300756e: cc22 sw s0,24(sp) + 3007570: 1000 addi s0,sp,32 + 3007572: fea42623 sw a0,-20(s0) + BASE_FUNC_UNUSED(handle); + /* USER CODE BEGIN TIMER0_InterruptProcess */ + + if (g_step_motor_flag == 1) + 3007576: 040037b7 lui a5,0x4003 + 300757a: 00d7c703 lbu a4,13(a5) # 400300d + 300757e: 4785 li a5,1 + 3007580: 00f71d63 bne a4,a5,300759a + { + g_timer0_count++; + 3007584: 040037b7 lui a5,0x4003 + 3007588: 0107a783 lw a5,16(a5) # 4003010 + 300758c: 00178713 addi a4,a5,1 + 3007590: 040037b7 lui a5,0x4003 + 3007594: 00e7a823 sw a4,16(a5) # 4003010 + 3007598: a0b1 j 30075e4 + } + else + { + g_step_motor = 0; + 300759a: 040037b7 lui a5,0x4003 + 300759e: 00078623 sb zero,12(a5) # 400300c + g_timer0_count = 0; + 30075a2: 040037b7 lui a5,0x4003 + 30075a6: 0007a823 sw zero,16(a5) # 4003010 + + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_2, GPIO_LOW_LEVEL); + 30075aa: 4601 li a2,0 + 30075ac: 4591 li a1,4 + 30075ae: 040007b7 lui a5,0x4000 + 30075b2: 6fc78513 addi a0,a5,1788 # 40006fc + 30075b6: 2ae1 jal ra,300778e + HAL_GPIO_SetValue(&g_gpio3, GPIO_PIN_6, GPIO_LOW_LEVEL); + 30075b8: 4601 li a2,0 + 30075ba: 04000593 li a1,64 + 30075be: 040007b7 lui a5,0x4000 + 30075c2: 74478513 addi a0,a5,1860 # 4000744 + 30075c6: 22e1 jal ra,300778e + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_3, GPIO_LOW_LEVEL); + 30075c8: 4601 li a2,0 + 30075ca: 45a1 li a1,8 + 30075cc: 040007b7 lui a5,0x4000 + 30075d0: 6fc78513 addi a0,a5,1788 # 40006fc + 30075d4: 2a6d jal ra,300778e + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_1, GPIO_LOW_LEVEL); + 30075d6: 4601 li a2,0 + 30075d8: 4589 li a1,2 + 30075da: 040007b7 lui a5,0x4000 + 30075de: 6fc78513 addi a0,a5,1788 # 40006fc + 30075e2: 2275 jal ra,300778e + } + + if (g_timer0_count > 2 * 5) + 30075e4: 040037b7 lui a5,0x4003 + 30075e8: 0107a703 lw a4,16(a5) # 4003010 + 30075ec: 47a9 li a5,10 + 30075ee: 18e7fa63 bgeu a5,a4,3007782 + { + g_timer0_count = 0; + 30075f2: 040037b7 lui a5,0x4003 + 30075f6: 0007a823 sw zero,16(a5) # 4003010 + + switch (g_step_motor) + 30075fa: 040037b7 lui a5,0x4003 + 30075fe: 00c7c783 lbu a5,12(a5) # 400300c + 3007602: 4711 li a4,4 + 3007604: 16f76a63 bltu a4,a5,3007778 + 3007608: 00279713 slli a4,a5,0x2 + 300760c: 030097b7 lui a5,0x3009 + 3007610: b0078793 addi a5,a5,-1280 # 3008b00 + 3007614: 97ba add a5,a5,a4 + 3007616: 439c lw a5,0(a5) + 3007618: 8782 jr a5 + { + case 0: + g_step_motor = 1; + 300761a: 040037b7 lui a5,0x4003 + 300761e: 4705 li a4,1 + 3007620: 00e78623 sb a4,12(a5) # 400300c + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_2, GPIO_LOW_LEVEL); + 3007624: 4601 li a2,0 + 3007626: 4591 li a1,4 + 3007628: 040007b7 lui a5,0x4000 + 300762c: 6fc78513 addi a0,a5,1788 # 40006fc + 3007630: 2ab9 jal ra,300778e + HAL_GPIO_SetValue(&g_gpio3, GPIO_PIN_6, GPIO_LOW_LEVEL); + 3007632: 4601 li a2,0 + 3007634: 04000593 li a1,64 + 3007638: 040007b7 lui a5,0x4000 + 300763c: 74478513 addi a0,a5,1860 # 4000744 + 3007640: 22b9 jal ra,300778e + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_3, GPIO_LOW_LEVEL); + 3007642: 4601 li a2,0 + 3007644: 45a1 li a1,8 + 3007646: 040007b7 lui a5,0x4000 + 300764a: 6fc78513 addi a0,a5,1788 # 40006fc + 300764e: 2281 jal ra,300778e + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_1, GPIO_LOW_LEVEL); + 3007650: 4601 li a2,0 + 3007652: 4589 li a1,2 + 3007654: 040007b7 lui a5,0x4000 + 3007658: 6fc78513 addi a0,a5,1788 # 40006fc + 300765c: 2a0d jal ra,300778e + break; + 300765e: a21d j 3007784 + case 1: + g_step_motor = 2; + 3007660: 040037b7 lui a5,0x4003 + 3007664: 4709 li a4,2 + 3007666: 00e78623 sb a4,12(a5) # 400300c + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_2, GPIO_HIGH_LEVEL); + 300766a: 4605 li a2,1 + 300766c: 4591 li a1,4 + 300766e: 040007b7 lui a5,0x4000 + 3007672: 6fc78513 addi a0,a5,1788 # 40006fc + 3007676: 2a21 jal ra,300778e + HAL_GPIO_SetValue(&g_gpio3, GPIO_PIN_6, GPIO_LOW_LEVEL); + 3007678: 4601 li a2,0 + 300767a: 04000593 li a1,64 + 300767e: 040007b7 lui a5,0x4000 + 3007682: 74478513 addi a0,a5,1860 # 4000744 + 3007686: 2221 jal ra,300778e + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_3, GPIO_LOW_LEVEL); + 3007688: 4601 li a2,0 + 300768a: 45a1 li a1,8 + 300768c: 040007b7 lui a5,0x4000 + 3007690: 6fc78513 addi a0,a5,1788 # 40006fc + 3007694: 28ed jal ra,300778e + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_1, GPIO_LOW_LEVEL); + 3007696: 4601 li a2,0 + 3007698: 4589 li a1,2 + 300769a: 040007b7 lui a5,0x4000 + 300769e: 6fc78513 addi a0,a5,1788 # 40006fc + 30076a2: 20f5 jal ra,300778e + break; + 30076a4: a0c5 j 3007784 + case 2: + g_step_motor = 3; + 30076a6: 040037b7 lui a5,0x4003 + 30076aa: 470d li a4,3 + 30076ac: 00e78623 sb a4,12(a5) # 400300c + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_2, GPIO_LOW_LEVEL); + 30076b0: 4601 li a2,0 + 30076b2: 4591 li a1,4 + 30076b4: 040007b7 lui a5,0x4000 + 30076b8: 6fc78513 addi a0,a5,1788 # 40006fc + 30076bc: 28c9 jal ra,300778e + HAL_GPIO_SetValue(&g_gpio3, GPIO_PIN_6, GPIO_HIGH_LEVEL); + 30076be: 4605 li a2,1 + 30076c0: 04000593 li a1,64 + 30076c4: 040007b7 lui a5,0x4000 + 30076c8: 74478513 addi a0,a5,1860 # 4000744 + 30076cc: 20c9 jal ra,300778e + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_3, GPIO_LOW_LEVEL); + 30076ce: 4601 li a2,0 + 30076d0: 45a1 li a1,8 + 30076d2: 040007b7 lui a5,0x4000 + 30076d6: 6fc78513 addi a0,a5,1788 # 40006fc + 30076da: 2855 jal ra,300778e + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_1, GPIO_LOW_LEVEL); + 30076dc: 4601 li a2,0 + 30076de: 4589 li a1,2 + 30076e0: 040007b7 lui a5,0x4000 + 30076e4: 6fc78513 addi a0,a5,1788 # 40006fc + 30076e8: 205d jal ra,300778e + break; + 30076ea: a869 j 3007784 + case 3: + g_step_motor = 4; + 30076ec: 040037b7 lui a5,0x4003 + 30076f0: 4711 li a4,4 + 30076f2: 00e78623 sb a4,12(a5) # 400300c + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_2, GPIO_LOW_LEVEL); + 30076f6: 4601 li a2,0 + 30076f8: 4591 li a1,4 + 30076fa: 040007b7 lui a5,0x4000 + 30076fe: 6fc78513 addi a0,a5,1788 # 40006fc + 3007702: 2071 jal ra,300778e + HAL_GPIO_SetValue(&g_gpio3, GPIO_PIN_6, GPIO_LOW_LEVEL); + 3007704: 4601 li a2,0 + 3007706: 04000593 li a1,64 + 300770a: 040007b7 lui a5,0x4000 + 300770e: 74478513 addi a0,a5,1860 # 4000744 + 3007712: 28b5 jal ra,300778e + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_3, GPIO_HIGH_LEVEL); + 3007714: 4605 li a2,1 + 3007716: 45a1 li a1,8 + 3007718: 040007b7 lui a5,0x4000 + 300771c: 6fc78513 addi a0,a5,1788 # 40006fc + 3007720: 20bd jal ra,300778e + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_1, GPIO_LOW_LEVEL); + 3007722: 4601 li a2,0 + 3007724: 4589 li a1,2 + 3007726: 040007b7 lui a5,0x4000 + 300772a: 6fc78513 addi a0,a5,1788 # 40006fc + 300772e: 2085 jal ra,300778e + break; + 3007730: a891 j 3007784 + case 4: + g_step_motor = 1; + 3007732: 040037b7 lui a5,0x4003 + 3007736: 4705 li a4,1 + 3007738: 00e78623 sb a4,12(a5) # 400300c + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_2, GPIO_LOW_LEVEL); + 300773c: 4601 li a2,0 + 300773e: 4591 li a1,4 + 3007740: 040007b7 lui a5,0x4000 + 3007744: 6fc78513 addi a0,a5,1788 # 40006fc + 3007748: 2099 jal ra,300778e + HAL_GPIO_SetValue(&g_gpio3, GPIO_PIN_6, GPIO_LOW_LEVEL); + 300774a: 4601 li a2,0 + 300774c: 04000593 li a1,64 + 3007750: 040007b7 lui a5,0x4000 + 3007754: 74478513 addi a0,a5,1860 # 4000744 + 3007758: 281d jal ra,300778e + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_3, GPIO_LOW_LEVEL); + 300775a: 4601 li a2,0 + 300775c: 45a1 li a1,8 + 300775e: 040007b7 lui a5,0x4000 + 3007762: 6fc78513 addi a0,a5,1788 # 40006fc + 3007766: 2025 jal ra,300778e + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_1, GPIO_HIGH_LEVEL); + 3007768: 4605 li a2,1 + 300776a: 4589 li a1,2 + 300776c: 040007b7 lui a5,0x4000 + 3007770: 6fc78513 addi a0,a5,1788 # 40006fc + 3007774: 2829 jal ra,300778e + break; + 3007776: a039 j 3007784 + default: + g_step_motor = 0; + 3007778: 040037b7 lui a5,0x4003 + 300777c: 00078623 sb zero,12(a5) # 400300c + break; + 3007780: a011 j 3007784 + } + } + 3007782: 0001 nop + /* USER CODE END TIMER0_InterruptProcess */ +} + 3007784: 0001 nop + 3007786: 40f2 lw ra,28(sp) + 3007788: 4462 lw s0,24(sp) + 300778a: 6105 addi sp,sp,32 + 300778c: 8082 ret + +0300778e : + 300778e: ce6fc06f j 3003c74 + +03007792 : + +void TIMER1_InterruptProcess(void *handle) +{ + 3007792: 1101 addi sp,sp,-32 + 3007794: ce06 sw ra,28(sp) + 3007796: cc22 sw s0,24(sp) + 3007798: 1000 addi s0,sp,32 + 300779a: fea42623 sw a0,-20(s0) + BASE_FUNC_UNUSED(handle); + /* USER CODE BEGIN TIMER1_InterruptProcess */ + /* USER CODE END TIMER1_InterruptProcess */ + g_timer1_count++; + 300779e: 040037b7 lui a5,0x4003 + 30077a2: 0147a783 lw a5,20(a5) # 4003014 + 30077a6: 00178713 addi a4,a5,1 + 30077aa: 040037b7 lui a5,0x4003 + 30077ae: 00e7aa23 sw a4,20(a5) # 4003014 + + if (g_timer1_count > 2 * 500) + 30077b2: 040037b7 lui a5,0x4003 + 30077b6: 0147a703 lw a4,20(a5) # 4003014 + 30077ba: 3e800793 li a5,1000 + 30077be: 00e7fd63 bgeu a5,a4,30077d8 + { + g_timer1_count = 0; + 30077c2: 040037b7 lui a5,0x4003 + 30077c6: 0007aa23 sw zero,20(a5) # 4003014 + + HAL_GPIO_TogglePin(&g_gpio1, GPIO_PIN_0); + 30077ca: 4585 li a1,1 + 30077cc: 040007b7 lui a5,0x4000 + 30077d0: 6b478513 addi a0,a5,1716 # 40006b4 + 30077d4: d8efc0ef jal ra,3003d62 + } +} + 30077d8: 0001 nop + 30077da: 40f2 lw ra,28(sp) + 30077dc: 4462 lw s0,24(sp) + 30077de: 6105 addi sp,sp,32 + 30077e0: 8082 ret + +030077e2 : +}; + +unsigned char g_i2c0_buff[2]; + +void PAJ7620U2_I2C_WriteData(unsigned char Address, unsigned char Data) +{ + 30077e2: 1101 addi sp,sp,-32 + 30077e4: ce06 sw ra,28(sp) + 30077e6: cc22 sw s0,24(sp) + 30077e8: 1000 addi s0,sp,32 + 30077ea: 87aa mv a5,a0 + 30077ec: 872e mv a4,a1 + 30077ee: fef407a3 sb a5,-17(s0) + 30077f2: 87ba mv a5,a4 + 30077f4: fef40723 sb a5,-18(s0) + g_i2c0_buff[0] = Address; + 30077f8: 040037b7 lui a5,0x4003 + 30077fc: fef44703 lbu a4,-17(s0) + 3007800: 00e78c23 sb a4,24(a5) # 4003018 + g_i2c0_buff[1] = Data; + 3007804: 040037b7 lui a5,0x4003 + 3007808: 01878793 addi a5,a5,24 # 4003018 + 300780c: fee44703 lbu a4,-18(s0) + 3007810: b398 sb a4,1(a5) + + HAL_I2C_MasterWriteBlocking(&g_i2c0, 0xE6, g_i2c0_buff, 2, 10000); + 3007812: 6789 lui a5,0x2 + 3007814: 71078713 addi a4,a5,1808 # 2710 + 3007818: 4689 li a3,2 + 300781a: 040037b7 lui a5,0x4003 + 300781e: 01878613 addi a2,a5,24 # 4003018 + 3007822: 0e600593 li a1,230 + 3007826: 040007b7 lui a5,0x4000 + 300782a: 60478513 addi a0,a5,1540 # 4000604 + 300782e: ebdfd0ef jal ra,30056ea +} + 3007832: 0001 nop + 3007834: 40f2 lw ra,28(sp) + 3007836: 4462 lw s0,24(sp) + 3007838: 6105 addi sp,sp,32 + 300783a: 8082 ret + +0300783c : + +unsigned char PAJ7620U2_I2C_ReadData(unsigned char Address) +{ + 300783c: 1101 addi sp,sp,-32 + 300783e: ce06 sw ra,28(sp) + 3007840: cc22 sw s0,24(sp) + 3007842: 1000 addi s0,sp,32 + 3007844: 87aa mv a5,a0 + 3007846: fef407a3 sb a5,-17(s0) + g_i2c0_buff[0] = Address; + 300784a: 040037b7 lui a5,0x4003 + 300784e: fef44703 lbu a4,-17(s0) + 3007852: 00e78c23 sb a4,24(a5) # 4003018 + + HAL_I2C_MasterWriteBlocking(&g_i2c0, 0xE6, &g_i2c0_buff, 1, 10000); + 3007856: 6789 lui a5,0x2 + 3007858: 71078713 addi a4,a5,1808 # 2710 + 300785c: 4685 li a3,1 + 300785e: 040037b7 lui a5,0x4003 + 3007862: 01878613 addi a2,a5,24 # 4003018 + 3007866: 0e600593 li a1,230 + 300786a: 040007b7 lui a5,0x4000 + 300786e: 60478513 addi a0,a5,1540 # 4000604 + 3007872: e79fd0ef jal ra,30056ea + HAL_I2C_MasterReadBlocking(&g_i2c0, 0xE7, &g_i2c0_buff, 1, 10000); + 3007876: 6789 lui a5,0x2 + 3007878: 71078713 addi a4,a5,1808 # 2710 + 300787c: 4685 li a3,1 + 300787e: 040037b7 lui a5,0x4003 + 3007882: 01878613 addi a2,a5,24 # 4003018 + 3007886: 0e700593 li a1,231 + 300788a: 040007b7 lui a5,0x4000 + 300788e: 60478513 addi a0,a5,1540 # 4000604 + 3007892: c53fd0ef jal ra,30054e4 + + return (g_i2c0_buff[0]); + 3007896: 040037b7 lui a5,0x4003 + 300789a: 0187c783 lbu a5,24(a5) # 4003018 +} + 300789e: 853e mv a0,a5 + 30078a0: 40f2 lw ra,28(sp) + 30078a2: 4462 lw s0,24(sp) + 30078a4: 6105 addi sp,sp,32 + 30078a6: 8082 ret + +030078a8 : + +void PAJ7620U2_Init(void) +{ + 30078a8: 1101 addi sp,sp,-32 + 30078aa: ce06 sw ra,28(sp) + 30078ac: cc22 sw s0,24(sp) + 30078ae: 1000 addi s0,sp,32 + if (PAJ7620U2_I2C_ReadData(0x00) == 0x20) + 30078b0: 4501 li a0,0 + 30078b2: 3769 jal ra,300783c + 30078b4: 87aa mv a5,a0 + 30078b6: 873e mv a4,a5 + 30078b8: 02000793 li a5,32 + 30078bc: 0af71463 bne a4,a5,3007964 + { + for (unsigned char i = 0; i < 51; i++) + 30078c0: fe0407a3 sb zero,-17(s0) + 30078c4: a81d j 30078fa + { + PAJ7620U2_I2C_WriteData(Init_REG_Table[i][0], Init_REG_Table[i][1]); + 30078c6: fef44783 lbu a5,-17(s0) + 30078ca: 03009737 lui a4,0x3009 + 30078ce: b1470713 addi a4,a4,-1260 # 3008b14 + 30078d2: 0786 slli a5,a5,0x1 + 30078d4: 97ba add a5,a5,a4 + 30078d6: 2394 lbu a3,0(a5) + 30078d8: fef44783 lbu a5,-17(s0) + 30078dc: 03009737 lui a4,0x3009 + 30078e0: b1470713 addi a4,a4,-1260 # 3008b14 + 30078e4: 0786 slli a5,a5,0x1 + 30078e6: 97ba add a5,a5,a4 + 30078e8: 339c lbu a5,1(a5) + 30078ea: 85be mv a1,a5 + 30078ec: 8536 mv a0,a3 + 30078ee: 3dd5 jal ra,30077e2 + for (unsigned char i = 0; i < 51; i++) + 30078f0: fef44783 lbu a5,-17(s0) + 30078f4: 0785 addi a5,a5,1 + 30078f6: fef407a3 sb a5,-17(s0) + 30078fa: fef44703 lbu a4,-17(s0) + 30078fe: 03200793 li a5,50 + 3007902: fce7f2e3 bgeu a5,a4,30078c6 + } + + for (unsigned char i = 0; i < 30; i++) + 3007906: fe040723 sb zero,-18(s0) + 300790a: a81d j 3007940 + { + PAJ7620U2_I2C_WriteData(Init_Gesture_Table[i][0], Init_Gesture_Table[i][1]); + 300790c: fee44783 lbu a5,-18(s0) + 3007910: 03009737 lui a4,0x3009 + 3007914: b7c70713 addi a4,a4,-1156 # 3008b7c + 3007918: 0786 slli a5,a5,0x1 + 300791a: 97ba add a5,a5,a4 + 300791c: 2394 lbu a3,0(a5) + 300791e: fee44783 lbu a5,-18(s0) + 3007922: 03009737 lui a4,0x3009 + 3007926: b7c70713 addi a4,a4,-1156 # 3008b7c + 300792a: 0786 slli a5,a5,0x1 + 300792c: 97ba add a5,a5,a4 + 300792e: 339c lbu a5,1(a5) + 3007930: 85be mv a1,a5 + 3007932: 8536 mv a0,a3 + 3007934: 357d jal ra,30077e2 + for (unsigned char i = 0; i < 30; i++) + 3007936: fee44783 lbu a5,-18(s0) + 300793a: 0785 addi a5,a5,1 + 300793c: fef40723 sb a5,-18(s0) + 3007940: fee44703 lbu a4,-18(s0) + 3007944: 47f5 li a5,29 + 3007946: fce7f3e3 bgeu a5,a4,300790c + } + + HAL_UART_WriteBlocking(&g_uart0, "\r\nPAJ7620U2_Init OK!", 20, 1000); + 300794a: 3e800693 li a3,1000 + 300794e: 4651 li a2,20 + 3007950: 030097b7 lui a5,0x3009 + 3007954: bb878593 addi a1,a5,-1096 # 3008bb8 + 3007958: 040007b7 lui a5,0x4000 + 300795c: 50478513 addi a0,a5,1284 # 4000504 + 3007960: 201d jal ra,3007986 + } + else + { + HAL_UART_WriteBlocking(&g_uart0, "\r\nPAJ7620U2_Init Failed!", 24, 1000); + } +} + 3007962: a829 j 300797c + HAL_UART_WriteBlocking(&g_uart0, "\r\nPAJ7620U2_Init Failed!", 24, 1000); + 3007964: 3e800693 li a3,1000 + 3007968: 4661 li a2,24 + 300796a: 030097b7 lui a5,0x3009 + 300796e: bd078593 addi a1,a5,-1072 # 3008bd0 + 3007972: 040007b7 lui a5,0x4000 + 3007976: 50478513 addi a0,a5,1284 # 4000504 + 300797a: 2031 jal ra,3007986 +} + 300797c: 0001 nop + 300797e: 40f2 lw ra,28(sp) + 3007980: 4462 lw s0,24(sp) + 3007982: 6105 addi sp,sp,32 + 3007984: 8082 ret + +03007986 : + 3007986: f17fe06f j 300689c + +0300798a : + +void PAJ7620U2_Handler(void) +{ + 300798a: 1101 addi sp,sp,-32 + 300798c: ce06 sw ra,28(sp) + 300798e: cc22 sw s0,24(sp) + 3007990: 1000 addi s0,sp,32 + unsigned char Data = PAJ7620U2_I2C_ReadData(0x43); + 3007992: 04300513 li a0,67 + 3007996: 355d jal ra,300783c + 3007998: 87aa mv a5,a0 + 300799a: fef407a3 sb a5,-17(s0) + + switch (Data) + 300799e: fef44783 lbu a5,-17(s0) + 30079a2: 4721 li a4,8 + 30079a4: 0ae78963 beq a5,a4,3007a56 + 30079a8: 4721 li a4,8 + 30079aa: 00f74c63 blt a4,a5,30079c2 + 30079ae: 4709 li a4,2 + 30079b0: 06e78063 beq a5,a4,3007a10 + 30079b4: 4711 li a4,4 + 30079b6: 06e78e63 beq a5,a4,3007a32 + 30079ba: 4705 li a4,1 + 30079bc: 02e78863 beq a5,a4,30079ec + case 0x10: HAL_UART_WriteBlocking(&g_uart0, "\r\nForward", 9, 1000); g_step_motor_flag = 1; break; + case 0x20: HAL_UART_WriteBlocking(&g_uart0, "\r\nBackward", 10, 1000); g_step_motor_flag = 0; break; + case 0x40: HAL_UART_WriteBlocking(&g_uart0, "\r\nClockwise", 11, 1000); break; + case 0x80: HAL_UART_WriteBlocking(&g_uart0, "\r\nAntiClockwise", 15, 1000); break; + default: + break; + 30079c0: aa0d j 3007af2 + switch (Data) + 30079c2: 02000713 li a4,32 + 30079c6: 0ce78b63 beq a5,a4,3007a9c + 30079ca: 02000713 li a4,32 + 30079ce: 00f74663 blt a4,a5,30079da + 30079d2: 4741 li a4,16 + 30079d4: 0ae78263 beq a5,a4,3007a78 + break; + 30079d8: aa29 j 3007af2 + switch (Data) + 30079da: 04000713 li a4,64 + 30079de: 0ee78063 beq a5,a4,3007abe + 30079e2: 08000713 li a4,128 + 30079e6: 0ee78963 beq a5,a4,3007ad8 + break; + 30079ea: a221 j 3007af2 + case 0x01: HAL_UART_WriteBlocking(&g_uart0, "\r\nUp", 4, 1000); g_step_motor_flag = 1; break; + 30079ec: 3e800693 li a3,1000 + 30079f0: 4611 li a2,4 + 30079f2: 030097b7 lui a5,0x3009 + 30079f6: bec78593 addi a1,a5,-1044 # 3008bec + 30079fa: 040007b7 lui a5,0x4000 + 30079fe: 50478513 addi a0,a5,1284 # 4000504 + 3007a02: 3751 jal ra,3007986 + 3007a04: 040037b7 lui a5,0x4003 + 3007a08: 4705 li a4,1 + 3007a0a: 00e786a3 sb a4,13(a5) # 400300d + 3007a0e: a0d5 j 3007af2 + case 0x02: HAL_UART_WriteBlocking(&g_uart0, "\r\nDown", 6, 1000); g_step_motor_flag = 0; break; + 3007a10: 3e800693 li a3,1000 + 3007a14: 4619 li a2,6 + 3007a16: 030097b7 lui a5,0x3009 + 3007a1a: bf478593 addi a1,a5,-1036 # 3008bf4 + 3007a1e: 040007b7 lui a5,0x4000 + 3007a22: 50478513 addi a0,a5,1284 # 4000504 + 3007a26: 3785 jal ra,3007986 + 3007a28: 040037b7 lui a5,0x4003 + 3007a2c: 000786a3 sb zero,13(a5) # 400300d + 3007a30: a0c9 j 3007af2 + case 0x04: HAL_UART_WriteBlocking(&g_uart0, "\r\nLeft", 6, 1000); g_step_motor_flag = 1; break; + 3007a32: 3e800693 li a3,1000 + 3007a36: 4619 li a2,6 + 3007a38: 030097b7 lui a5,0x3009 + 3007a3c: bfc78593 addi a1,a5,-1028 # 3008bfc + 3007a40: 040007b7 lui a5,0x4000 + 3007a44: 50478513 addi a0,a5,1284 # 4000504 + 3007a48: 3f3d jal ra,3007986 + 3007a4a: 040037b7 lui a5,0x4003 + 3007a4e: 4705 li a4,1 + 3007a50: 00e786a3 sb a4,13(a5) # 400300d + 3007a54: a879 j 3007af2 + case 0x08: HAL_UART_WriteBlocking(&g_uart0, "\r\nRight", 7, 1000); g_step_motor_flag = 0; break; + 3007a56: 3e800693 li a3,1000 + 3007a5a: 461d li a2,7 + 3007a5c: 030097b7 lui a5,0x3009 + 3007a60: c0478593 addi a1,a5,-1020 # 3008c04 + 3007a64: 040007b7 lui a5,0x4000 + 3007a68: 50478513 addi a0,a5,1284 # 4000504 + 3007a6c: 3f29 jal ra,3007986 + 3007a6e: 040037b7 lui a5,0x4003 + 3007a72: 000786a3 sb zero,13(a5) # 400300d + 3007a76: a8b5 j 3007af2 + case 0x10: HAL_UART_WriteBlocking(&g_uart0, "\r\nForward", 9, 1000); g_step_motor_flag = 1; break; + 3007a78: 3e800693 li a3,1000 + 3007a7c: 4625 li a2,9 + 3007a7e: 030097b7 lui a5,0x3009 + 3007a82: c0c78593 addi a1,a5,-1012 # 3008c0c + 3007a86: 040007b7 lui a5,0x4000 + 3007a8a: 50478513 addi a0,a5,1284 # 4000504 + 3007a8e: 3de5 jal ra,3007986 + 3007a90: 040037b7 lui a5,0x4003 + 3007a94: 4705 li a4,1 + 3007a96: 00e786a3 sb a4,13(a5) # 400300d + 3007a9a: a8a1 j 3007af2 + case 0x20: HAL_UART_WriteBlocking(&g_uart0, "\r\nBackward", 10, 1000); g_step_motor_flag = 0; break; + 3007a9c: 3e800693 li a3,1000 + 3007aa0: 4629 li a2,10 + 3007aa2: 030097b7 lui a5,0x3009 + 3007aa6: c1878593 addi a1,a5,-1000 # 3008c18 + 3007aaa: 040007b7 lui a5,0x4000 + 3007aae: 50478513 addi a0,a5,1284 # 4000504 + 3007ab2: 3dd1 jal ra,3007986 + 3007ab4: 040037b7 lui a5,0x4003 + 3007ab8: 000786a3 sb zero,13(a5) # 400300d + 3007abc: a81d j 3007af2 + case 0x40: HAL_UART_WriteBlocking(&g_uart0, "\r\nClockwise", 11, 1000); break; + 3007abe: 3e800693 li a3,1000 + 3007ac2: 462d li a2,11 + 3007ac4: 030097b7 lui a5,0x3009 + 3007ac8: c2478593 addi a1,a5,-988 # 3008c24 + 3007acc: 040007b7 lui a5,0x4000 + 3007ad0: 50478513 addi a0,a5,1284 # 4000504 + 3007ad4: 3d4d jal ra,3007986 + 3007ad6: a831 j 3007af2 + case 0x80: HAL_UART_WriteBlocking(&g_uart0, "\r\nAntiClockwise", 15, 1000); break; + 3007ad8: 3e800693 li a3,1000 + 3007adc: 463d li a2,15 + 3007ade: 030097b7 lui a5,0x3009 + 3007ae2: c3078593 addi a1,a5,-976 # 3008c30 + 3007ae6: 040007b7 lui a5,0x4000 + 3007aea: 50478513 addi a0,a5,1284 # 4000504 + 3007aee: 3d61 jal ra,3007986 + 3007af0: 0001 nop + } +} + 3007af2: 0001 nop + 3007af4: 40f2 lw ra,28(sp) + 3007af6: 4462 lw s0,24(sp) + 3007af8: 6105 addi sp,sp,32 + 3007afa: 8082 ret + +03007afc : + +#define UART0_BAND_RATE 115200 +#define UART2_BAND_RATE 921600 + +BASE_StatusType CRG_Config(CRG_CoreClkSelect *coreClkSelect) +{ + 3007afc: 715d addi sp,sp,-80 + 3007afe: c686 sw ra,76(sp) + 3007b00: c4a2 sw s0,72(sp) + 3007b02: 0880 addi s0,sp,80 + 3007b04: faa42e23 sw a0,-68(s0) + CRG_Handle crg; + crg.baseAddress = CRG; + 3007b08: 100007b7 lui a5,0x10000 + 3007b0c: fcf42423 sw a5,-56(s0) + crg.pllRefClkSelect = CRG_PLL_REF_CLK_SELECT_HOSC; + 3007b10: fc042623 sw zero,-52(s0) + crg.pllPreDiv = CRG_PLL_PREDIV_4; + 3007b14: 478d li a5,3 + 3007b16: fcf42823 sw a5,-48(s0) + crg.pllFbDiv = 48; /* PLL Multiplier 48 */ + 3007b1a: 03000793 li a5,48 + 3007b1e: fcf42a23 sw a5,-44(s0) + crg.pllPostDiv = CRG_PLL_POSTDIV_2; + 3007b22: 4785 li a5,1 + 3007b24: fcf42c23 sw a5,-40(s0) + crg.coreClkSelect = CRG_CORE_CLK_SELECT_PLL; + 3007b28: 4789 li a5,2 + 3007b2a: fef42023 sw a5,-32(s0) + crg.handleEx.pllPostDiv2 = CRG_PLL_POSTDIV2_3; + 3007b2e: 4789 li a5,2 + 3007b30: fef42223 sw a5,-28(s0) + crg.handleEx.clk1MSelect = CRG_1M_CLK_SELECT_HOSC; + 3007b34: fe042423 sw zero,-24(s0) + crg.handleEx.clk1MDiv = (25 - 1); /* The 1 MHz freq is equal to the input clock frequency / (clk_1m_div + 1). 25 is the div of the clk_1m in CLOCK. */ + 3007b38: 47e1 li a5,24 + 3007b3a: fef42623 sw a5,-20(s0) + + if (HAL_CRG_Init(&crg) != BASE_STATUS_OK) { + 3007b3e: fc840793 addi a5,s0,-56 + 3007b42: 853e mv a0,a5 + 3007b44: d3efa0ef jal ra,3002082 + 3007b48: 87aa mv a5,a0 + 3007b4a: c399 beqz a5,3007b50 + return BASE_STATUS_ERROR; + 3007b4c: 4785 li a5,1 + 3007b4e: a039 j 3007b5c + } + *coreClkSelect = crg.coreClkSelect; + 3007b50: fe042703 lw a4,-32(s0) + 3007b54: fbc42783 lw a5,-68(s0) + 3007b58: c398 sw a4,0(a5) + return BASE_STATUS_OK; + 3007b5a: 4781 li a5,0 +} + 3007b5c: 853e mv a0,a5 + 3007b5e: 40b6 lw ra,76(sp) + 3007b60: 4426 lw s0,72(sp) + 3007b62: 6161 addi sp,sp,80 + 3007b64: 8082 ret + +03007b66 : + GPIO_Handle *handle = (GPIO_Handle *)param; + BASE_FUNC_UNUSED(handle); +} + +static void GPIO_Init(void) +{ + 3007b66: 1141 addi sp,sp,-16 + 3007b68: c606 sw ra,12(sp) + 3007b6a: c422 sw s0,8(sp) + 3007b6c: 0800 addi s0,sp,16 + HAL_CRG_IpEnableSet(GPIO2_BASE, IP_CLK_ENABLE); + 3007b6e: 4585 li a1,1 + 3007b70: 14502537 lui a0,0x14502 + 3007b74: 2599 jal ra,30081ba + g_gpio2.baseAddress = GPIO2; + 3007b76: 040007b7 lui a5,0x4000 + 3007b7a: 66c78793 addi a5,a5,1644 # 400066c + 3007b7e: 14502737 lui a4,0x14502 + 3007b82: c398 sw a4,0(a5) + + g_gpio2.pins = GPIO_PIN_3; + 3007b84: 040007b7 lui a5,0x4000 + 3007b88: 66c78793 addi a5,a5,1644 # 400066c + 3007b8c: 4721 li a4,8 + 3007b8e: c3d8 sw a4,4(a5) + HAL_GPIO_Init(&g_gpio2); + 3007b90: 040007b7 lui a5,0x4000 + 3007b94: 66c78513 addi a0,a5,1644 # 400066c + 3007b98: 2c89 jal ra,3007dea + HAL_GPIO_SetDirection(&g_gpio2, g_gpio2.pins, GPIO_OUTPUT_MODE); + 3007b9a: 040007b7 lui a5,0x4000 + 3007b9e: 66c78793 addi a5,a5,1644 # 400066c + 3007ba2: 43dc lw a5,4(a5) + 3007ba4: 4605 li a2,1 + 3007ba6: 85be mv a1,a5 + 3007ba8: 040007b7 lui a5,0x4000 + 3007bac: 66c78513 addi a0,a5,1644 # 400066c + 3007bb0: 2c1d jal ra,3007de6 + HAL_GPIO_SetValue(&g_gpio2, g_gpio2.pins, GPIO_HIGH_LEVEL); + 3007bb2: 040007b7 lui a5,0x4000 + 3007bb6: 66c78793 addi a5,a5,1644 # 400066c + 3007bba: 43dc lw a5,4(a5) + 3007bbc: 4605 li a2,1 + 3007bbe: 85be mv a1,a5 + 3007bc0: 040007b7 lui a5,0x4000 + 3007bc4: 66c78513 addi a0,a5,1644 # 400066c + 3007bc8: 36d9 jal ra,300778e + HAL_GPIO_SetIrqType(&g_gpio2, g_gpio2.pins, GPIO_INT_TYPE_NONE); + 3007bca: 040007b7 lui a5,0x4000 + 3007bce: 66c78793 addi a5,a5,1644 # 400066c + 3007bd2: 43dc lw a5,4(a5) + 3007bd4: 4615 li a2,5 + 3007bd6: 85be mv a1,a5 + 3007bd8: 040007b7 lui a5,0x4000 + 3007bdc: 66c78513 addi a0,a5,1644 # 400066c + 3007be0: 2409 jal ra,3007de2 + + g_gpio2.pins = GPIO_PIN_4; + 3007be2: 040007b7 lui a5,0x4000 + 3007be6: 66c78793 addi a5,a5,1644 # 400066c + 3007bea: 4741 li a4,16 + 3007bec: c3d8 sw a4,4(a5) + HAL_GPIO_Init(&g_gpio2); + 3007bee: 040007b7 lui a5,0x4000 + 3007bf2: 66c78513 addi a0,a5,1644 # 400066c + 3007bf6: 2ad5 jal ra,3007dea + HAL_GPIO_SetDirection(&g_gpio2, g_gpio2.pins, GPIO_INPUT_MODE); + 3007bf8: 040007b7 lui a5,0x4000 + 3007bfc: 66c78793 addi a5,a5,1644 # 400066c + 3007c00: 43dc lw a5,4(a5) + 3007c02: 4601 li a2,0 + 3007c04: 85be mv a1,a5 + 3007c06: 040007b7 lui a5,0x4000 + 3007c0a: 66c78513 addi a0,a5,1644 # 400066c + 3007c0e: 2ae1 jal ra,3007de6 + HAL_GPIO_SetValue(&g_gpio2, g_gpio2.pins, GPIO_LOW_LEVEL); + 3007c10: 040007b7 lui a5,0x4000 + 3007c14: 66c78793 addi a5,a5,1644 # 400066c + 3007c18: 43dc lw a5,4(a5) + 3007c1a: 4601 li a2,0 + 3007c1c: 85be mv a1,a5 + 3007c1e: 040007b7 lui a5,0x4000 + 3007c22: 66c78513 addi a0,a5,1644 # 400066c + 3007c26: 36a5 jal ra,300778e + HAL_GPIO_SetIrqType(&g_gpio2, g_gpio2.pins, GPIO_INT_TYPE_FALL_EDGE); + 3007c28: 040007b7 lui a5,0x4000 + 3007c2c: 66c78793 addi a5,a5,1644 # 400066c + 3007c30: 43dc lw a5,4(a5) + 3007c32: 4601 li a2,0 + 3007c34: 85be mv a1,a5 + 3007c36: 040007b7 lui a5,0x4000 + 3007c3a: 66c78513 addi a0,a5,1644 # 400066c + 3007c3e: 2255 jal ra,3007de2 + + HAL_CRG_IpEnableSet(GPIO1_BASE, IP_CLK_ENABLE); + 3007c40: 4585 li a1,1 + 3007c42: 14501537 lui a0,0x14501 + 3007c46: 2b95 jal ra,30081ba + g_gpio1.baseAddress = GPIO1; + 3007c48: 040007b7 lui a5,0x4000 + 3007c4c: 6b478793 addi a5,a5,1716 # 40006b4 + 3007c50: 14501737 lui a4,0x14501 + 3007c54: c398 sw a4,0(a5) + + g_gpio1.pins = GPIO_PIN_0; + 3007c56: 040007b7 lui a5,0x4000 + 3007c5a: 6b478793 addi a5,a5,1716 # 40006b4 + 3007c5e: 4705 li a4,1 + 3007c60: c3d8 sw a4,4(a5) + HAL_GPIO_Init(&g_gpio1); + 3007c62: 040007b7 lui a5,0x4000 + 3007c66: 6b478513 addi a0,a5,1716 # 40006b4 + 3007c6a: 2241 jal ra,3007dea + HAL_GPIO_SetDirection(&g_gpio1, g_gpio1.pins, GPIO_OUTPUT_MODE); + 3007c6c: 040007b7 lui a5,0x4000 + 3007c70: 6b478793 addi a5,a5,1716 # 40006b4 + 3007c74: 43dc lw a5,4(a5) + 3007c76: 4605 li a2,1 + 3007c78: 85be mv a1,a5 + 3007c7a: 040007b7 lui a5,0x4000 + 3007c7e: 6b478513 addi a0,a5,1716 # 40006b4 + 3007c82: 2295 jal ra,3007de6 + HAL_GPIO_SetValue(&g_gpio1, g_gpio1.pins, GPIO_HIGH_LEVEL); + 3007c84: 040007b7 lui a5,0x4000 + 3007c88: 6b478793 addi a5,a5,1716 # 40006b4 + 3007c8c: 43dc lw a5,4(a5) + 3007c8e: 4605 li a2,1 + 3007c90: 85be mv a1,a5 + 3007c92: 040007b7 lui a5,0x4000 + 3007c96: 6b478513 addi a0,a5,1716 # 40006b4 + 3007c9a: 3cd5 jal ra,300778e + HAL_GPIO_SetIrqType(&g_gpio1, g_gpio1.pins, GPIO_INT_TYPE_NONE); + 3007c9c: 040007b7 lui a5,0x4000 + 3007ca0: 6b478793 addi a5,a5,1716 # 40006b4 + 3007ca4: 43dc lw a5,4(a5) + 3007ca6: 4615 li a2,5 + 3007ca8: 85be mv a1,a5 + 3007caa: 040007b7 lui a5,0x4000 + 3007cae: 6b478513 addi a0,a5,1716 # 40006b4 + 3007cb2: 2a05 jal ra,3007de2 + + HAL_CRG_IpEnableSet(GPIO5_BASE, IP_CLK_ENABLE); + 3007cb4: 4585 li a1,1 + 3007cb6: 14505537 lui a0,0x14505 + 3007cba: 2301 jal ra,30081ba + g_gpio5.baseAddress = GPIO5; + 3007cbc: 040007b7 lui a5,0x4000 + 3007cc0: 6fc78793 addi a5,a5,1788 # 40006fc + 3007cc4: 14505737 lui a4,0x14505 + 3007cc8: c398 sw a4,0(a5) + + g_gpio5.pins = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_1; + 3007cca: 040007b7 lui a5,0x4000 + 3007cce: 6fc78793 addi a5,a5,1788 # 40006fc + 3007cd2: 4739 li a4,14 + 3007cd4: c3d8 sw a4,4(a5) + HAL_GPIO_Init(&g_gpio5); + 3007cd6: 040007b7 lui a5,0x4000 + 3007cda: 6fc78513 addi a0,a5,1788 # 40006fc + 3007cde: 2231 jal ra,3007dea + HAL_GPIO_SetDirection(&g_gpio5, g_gpio5.pins, GPIO_OUTPUT_MODE); + 3007ce0: 040007b7 lui a5,0x4000 + 3007ce4: 6fc78793 addi a5,a5,1788 # 40006fc + 3007ce8: 43dc lw a5,4(a5) + 3007cea: 4605 li a2,1 + 3007cec: 85be mv a1,a5 + 3007cee: 040007b7 lui a5,0x4000 + 3007cf2: 6fc78513 addi a0,a5,1788 # 40006fc + 3007cf6: 28c5 jal ra,3007de6 + HAL_GPIO_SetValue(&g_gpio5, g_gpio5.pins, GPIO_HIGH_LEVEL); + 3007cf8: 040007b7 lui a5,0x4000 + 3007cfc: 6fc78793 addi a5,a5,1788 # 40006fc + 3007d00: 43dc lw a5,4(a5) + 3007d02: 4605 li a2,1 + 3007d04: 85be mv a1,a5 + 3007d06: 040007b7 lui a5,0x4000 + 3007d0a: 6fc78513 addi a0,a5,1788 # 40006fc + 3007d0e: 3441 jal ra,300778e + HAL_GPIO_SetIrqType(&g_gpio5, g_gpio5.pins, GPIO_INT_TYPE_NONE); + 3007d10: 040007b7 lui a5,0x4000 + 3007d14: 6fc78793 addi a5,a5,1788 # 40006fc + 3007d18: 43dc lw a5,4(a5) + 3007d1a: 4615 li a2,5 + 3007d1c: 85be mv a1,a5 + 3007d1e: 040007b7 lui a5,0x4000 + 3007d22: 6fc78513 addi a0,a5,1788 # 40006fc + 3007d26: 2875 jal ra,3007de2 + + HAL_CRG_IpEnableSet(GPIO3_BASE, IP_CLK_ENABLE); + 3007d28: 4585 li a1,1 + 3007d2a: 14503537 lui a0,0x14503 + 3007d2e: 2171 jal ra,30081ba + g_gpio3.baseAddress = GPIO3; + 3007d30: 040007b7 lui a5,0x4000 + 3007d34: 74478793 addi a5,a5,1860 # 4000744 + 3007d38: 14503737 lui a4,0x14503 + 3007d3c: c398 sw a4,0(a5) + + g_gpio3.pins = GPIO_PIN_6; + 3007d3e: 040007b7 lui a5,0x4000 + 3007d42: 74478793 addi a5,a5,1860 # 4000744 + 3007d46: 04000713 li a4,64 + 3007d4a: c3d8 sw a4,4(a5) + HAL_GPIO_Init(&g_gpio3); + 3007d4c: 040007b7 lui a5,0x4000 + 3007d50: 74478513 addi a0,a5,1860 # 4000744 + 3007d54: 2859 jal ra,3007dea + HAL_GPIO_SetDirection(&g_gpio3, g_gpio3.pins, GPIO_OUTPUT_MODE); + 3007d56: 040007b7 lui a5,0x4000 + 3007d5a: 74478793 addi a5,a5,1860 # 4000744 + 3007d5e: 43dc lw a5,4(a5) + 3007d60: 4605 li a2,1 + 3007d62: 85be mv a1,a5 + 3007d64: 040007b7 lui a5,0x4000 + 3007d68: 74478513 addi a0,a5,1860 # 4000744 + 3007d6c: 28ad jal ra,3007de6 + HAL_GPIO_SetValue(&g_gpio3, g_gpio3.pins, GPIO_HIGH_LEVEL); + 3007d6e: 040007b7 lui a5,0x4000 + 3007d72: 74478793 addi a5,a5,1860 # 4000744 + 3007d76: 43dc lw a5,4(a5) + 3007d78: 4605 li a2,1 + 3007d7a: 85be mv a1,a5 + 3007d7c: 040007b7 lui a5,0x4000 + 3007d80: 74478513 addi a0,a5,1860 # 4000744 + 3007d84: 3429 jal ra,300778e + HAL_GPIO_SetIrqType(&g_gpio3, g_gpio3.pins, GPIO_INT_TYPE_NONE); + 3007d86: 040007b7 lui a5,0x4000 + 3007d8a: 74478793 addi a5,a5,1860 # 4000744 + 3007d8e: 43dc lw a5,4(a5) + 3007d90: 4615 li a2,5 + 3007d92: 85be mv a1,a5 + 3007d94: 040007b7 lui a5,0x4000 + 3007d98: 74478513 addi a0,a5,1860 # 4000744 + 3007d9c: 2099 jal ra,3007de2 + + HAL_GPIO_RegisterCallBack(&g_gpio2, GPIO_PIN_4, GPIO2_4_CallbackFunc); + 3007d9e: 030077b7 lui a5,0x3007 + 3007da2: 43878613 addi a2,a5,1080 # 3007438 + 3007da6: 45c1 li a1,16 + 3007da8: 040007b7 lui a5,0x4000 + 3007dac: 66c78513 addi a0,a5,1644 # 400066c + 3007db0: ddcfc0ef jal ra,300438c + IRQ_Register(IRQ_GPIO2, HAL_GPIO_IrqHandler, &g_gpio2); + 3007db4: 040007b7 lui a5,0x4000 + 3007db8: 66c78613 addi a2,a5,1644 # 400066c + 3007dbc: 030047b7 lui a5,0x3004 + 3007dc0: 28278593 addi a1,a5,642 # 3004282 + 3007dc4: 06f00513 li a0,111 + 3007dc8: 2305 jal ra,30082e8 + IRQ_SetPriority(IRQ_GPIO2, 1); /* set gpio1 interrupt priority to 1, 1~15. 1 is priority value */ + 3007dca: 4585 li a1,1 + 3007dcc: 06f00513 li a0,111 + 3007dd0: 2b11 jal ra,30082e4 + IRQ_EnableN(IRQ_GPIO2); /* gpio interrupt enable */ + 3007dd2: 06f00513 li a0,111 + 3007dd6: 2329 jal ra,30082e0 + + return; + 3007dd8: 0001 nop +} + 3007dda: 40b2 lw ra,12(sp) + 3007ddc: 4422 lw s0,8(sp) + 3007dde: 0141 addi sp,sp,16 + 3007de0: 8082 ret + +03007de2 : + 3007de2: 98afc06f j 3003f6c + +03007de6 : + 3007de6: da7fb06f j 3003b8c + +03007dea : + 3007dea: cbdfb06f j 3003aa6 + +03007dee : + +static void I2C0_Init(void) +{ + 3007dee: 1141 addi sp,sp,-16 + 3007df0: c606 sw ra,12(sp) + 3007df2: c422 sw s0,8(sp) + 3007df4: 0800 addi s0,sp,16 + HAL_CRG_IpEnableSet(I2C0_BASE, IP_CLK_ENABLE); /* I2C0 clock enable. */ + 3007df6: 4585 li a1,1 + 3007df8: 14100537 lui a0,0x14100 + 3007dfc: 2e7d jal ra,30081ba + g_i2c0.baseAddress = I2C0; + 3007dfe: 040007b7 lui a5,0x4000 + 3007e02: 60478793 addi a5,a5,1540 # 4000604 + 3007e06: 14100737 lui a4,0x14100 + 3007e0a: c398 sw a4,0(a5) + + g_i2c0.functionMode = I2C_MODE_SELECT_MASTER_ONLY; + 3007e0c: 040007b7 lui a5,0x4000 + 3007e10: 60478793 addi a5,a5,1540 # 4000604 + 3007e14: 4705 li a4,1 + 3007e16: c3d8 sw a4,4(a5) + g_i2c0.addrMode = I2C_7_BITS; + 3007e18: 040007b7 lui a5,0x4000 + 3007e1c: 60478793 addi a5,a5,1540 # 4000604 + 3007e20: 0007a423 sw zero,8(a5) + g_i2c0.sdaHoldTime = 10; /* 10 is sda Hold Time */ + 3007e24: 040007b7 lui a5,0x4000 + 3007e28: 60478793 addi a5,a5,1540 # 4000604 + 3007e2c: 4729 li a4,10 + 3007e2e: cb98 sw a4,16(a5) + g_i2c0.freq = 100000; /* freqence is 100000 */ + 3007e30: 040007b7 lui a5,0x4000 + 3007e34: 60478793 addi a5,a5,1540 # 4000604 + 3007e38: 6761 lui a4,0x18 + 3007e3a: 6a070713 addi a4,a4,1696 # 186a0 + 3007e3e: cbd8 sw a4,20(a5) + g_i2c0.transferBuff = NULL; + 3007e40: 040007b7 lui a5,0x4000 + 3007e44: 60478793 addi a5,a5,1540 # 4000604 + 3007e48: 0207a023 sw zero,32(a5) + g_i2c0.ignoreAckFlag = BASE_CFG_DISABLE; + 3007e4c: 040007b7 lui a5,0x4000 + 3007e50: 60478793 addi a5,a5,1540 # 4000604 + 3007e54: 0007ac23 sw zero,24(a5) + g_i2c0.handleEx.spikeFilterTime = 0; + 3007e58: 040007b7 lui a5,0x4000 + 3007e5c: 60478793 addi a5,a5,1540 # 4000604 + 3007e60: 0407ac23 sw zero,88(a5) + g_i2c0.handleEx.sdaDelayTime = 0; + 3007e64: 040007b7 lui a5,0x4000 + 3007e68: 60478793 addi a5,a5,1540 # 4000604 + 3007e6c: 0407ae23 sw zero,92(a5) + g_i2c0.timeout = 10000; /* 10000 is time out */ + 3007e70: 040007b7 lui a5,0x4000 + 3007e74: 60478793 addi a5,a5,1540 # 4000604 + 3007e78: 6709 lui a4,0x2 + 3007e7a: 71070713 addi a4,a4,1808 # 2710 + 3007e7e: d7d8 sw a4,44(a5) + g_i2c0.state = I2C_STATE_RESET; + 3007e80: 040007b7 lui a5,0x4000 + 3007e84: 60478793 addi a5,a5,1540 # 4000604 + 3007e88: 0407a223 sw zero,68(a5) + HAL_I2C_Init(&g_i2c0); + 3007e8c: 040007b7 lui a5,0x4000 + 3007e90: 60478513 addi a0,a5,1540 # 4000604 + 3007e94: b6cfd0ef jal ra,3005200 +} + 3007e98: 0001 nop + 3007e9a: 40b2 lw ra,12(sp) + 3007e9c: 4422 lw s0,8(sp) + 3007e9e: 0141 addi sp,sp,16 + 3007ea0: 8082 ret + +03007ea2 : + /* USER CODE BEGIN TIMER0_InterruptProcess */ + /* USER CODE END TIMER0_InterruptProcess */ +} + +static void TIMER0_Init(void) +{ + 3007ea2: 1101 addi sp,sp,-32 + 3007ea4: ce06 sw ra,28(sp) + 3007ea6: cc22 sw s0,24(sp) + 3007ea8: 1000 addi s0,sp,32 + HAL_CRG_IpEnableSet(TIMER0_BASE, IP_CLK_ENABLE); /* TIMER0 clock enable. */ + 3007eaa: 4585 li a1,1 + 3007eac: 14300537 lui a0,0x14300 + 3007eb0: 2629 jal ra,30081ba + unsigned int load = (HAL_CRG_GetIpFreq((void *)TIMER0) / (1u << (TIMERPRESCALER_NO_DIV * 4)) / 1000000u) * 500; + 3007eb2: 14300537 lui a0,0x14300 + 3007eb6: eb4fa0ef jal ra,300256a + 3007eba: 872a mv a4,a0 + 3007ebc: 000f47b7 lui a5,0xf4 + 3007ec0: 24078793 addi a5,a5,576 # f4240 + 3007ec4: 02f75733 divu a4,a4,a5 + 3007ec8: 1f400793 li a5,500 + 3007ecc: 02f707b3 mul a5,a4,a5 + 3007ed0: fef42623 sw a5,-20(s0) + + g_timer0.baseAddress = TIMER0; + 3007ed4: 040007b7 lui a5,0x4000 + 3007ed8: 4b478793 addi a5,a5,1204 # 40004b4 + 3007edc: 14300737 lui a4,0x14300 + 3007ee0: c398 sw a4,0(a5) + g_timer0.load = load - 1; /* Set timer value immediately */ + 3007ee2: fec42783 lw a5,-20(s0) + 3007ee6: fff78713 addi a4,a5,-1 + 3007eea: 040007b7 lui a5,0x4000 + 3007eee: 4b478793 addi a5,a5,1204 # 40004b4 + 3007ef2: cbd8 sw a4,20(a5) + g_timer0.bgLoad = load - 1; /* Set timer value */ + 3007ef4: fec42783 lw a5,-20(s0) + 3007ef8: fff78713 addi a4,a5,-1 + 3007efc: 040007b7 lui a5,0x4000 + 3007f00: 4b478793 addi a5,a5,1204 # 40004b4 + 3007f04: cf98 sw a4,24(a5) + g_timer0.mode = TIMER_MODE_RUN_PERIODIC; /* Run in period mode */ + 3007f06: 040007b7 lui a5,0x4000 + 3007f0a: 4b478793 addi a5,a5,1204 # 40004b4 + 3007f0e: 4705 li a4,1 + 3007f10: c798 sw a4,8(a5) + g_timer0.prescaler = TIMERPRESCALER_NO_DIV; /* Don't frequency division */ + 3007f12: 040007b7 lui a5,0x4000 + 3007f16: 4b478793 addi a5,a5,1204 # 40004b4 + 3007f1a: 0007a623 sw zero,12(a5) + g_timer0.size = TIMER_SIZE_32BIT; /* 1 for 32bit, 0 for 16bit */ + 3007f1e: 040007b7 lui a5,0x4000 + 3007f22: 4b478793 addi a5,a5,1204 # 40004b4 + 3007f26: 4705 li a4,1 + 3007f28: cb98 sw a4,16(a5) + g_timer0.interruptEn = BASE_CFG_ENABLE; + 3007f2a: 040007b7 lui a5,0x4000 + 3007f2e: 4b478793 addi a5,a5,1204 # 40004b4 + 3007f32: 4705 li a4,1 + 3007f34: afd8 sb a4,28(a5) + g_timer0.adcSocReqEnable = BASE_CFG_DISABLE; + 3007f36: 040007b7 lui a5,0x4000 + 3007f3a: 4b478793 addi a5,a5,1204 # 40004b4 + 3007f3e: 00078ea3 sb zero,29(a5) + g_timer0.dmaReqEnable = BASE_CFG_DISABLE; + 3007f42: 040007b7 lui a5,0x4000 + 3007f46: 4b478793 addi a5,a5,1204 # 40004b4 + 3007f4a: 00078f23 sb zero,30(a5) + HAL_TIMER_Init(&g_timer0); + 3007f4e: 040007b7 lui a5,0x4000 + 3007f52: 4b478513 addi a0,a5,1204 # 40004b4 + 3007f56: e5bfd0ef jal ra,3005db0 + IRQ_Register(IRQ_TIMER0, HAL_TIMER_IrqHandler, &g_timer0); + 3007f5a: 040007b7 lui a5,0x4000 + 3007f5e: 4b478613 addi a2,a5,1204 # 40004b4 + 3007f62: 030067b7 lui a5,0x3006 + 3007f66: 08478593 addi a1,a5,132 # 3006084 + 3007f6a: 02000513 li a0,32 + 3007f6e: 2ead jal ra,30082e8 + + HAL_TIMER_RegisterCallback(&g_timer0, TIMER_PERIOD_FIN, TIMER0_InterruptProcess); + 3007f70: 030077b7 lui a5,0x3007 + 3007f74: 56a78613 addi a2,a5,1386 # 300756a + 3007f78: 4581 li a1,0 + 3007f7a: 040007b7 lui a5,0x4000 + 3007f7e: 4b478513 addi a0,a5,1204 # 40004b4 + 3007f82: 9eafe0ef jal ra,300616c + IRQ_SetPriority(IRQ_TIMER0, 1); /* 1 is priority value */ + 3007f86: 4585 li a1,1 + 3007f88: 02000513 li a0,32 + 3007f8c: 2ea1 jal ra,30082e4 + IRQ_EnableN(IRQ_TIMER0); + 3007f8e: 02000513 li a0,32 + 3007f92: 26b9 jal ra,30082e0 +} + 3007f94: 0001 nop + 3007f96: 40f2 lw ra,28(sp) + 3007f98: 4462 lw s0,24(sp) + 3007f9a: 6105 addi sp,sp,32 + 3007f9c: 8082 ret + +03007f9e : + /* USER CODE BEGIN TIMER1_InterruptProcess */ + /* USER CODE END TIMER1_InterruptProcess */ +} + +static void TIMER1_Init(void) +{ + 3007f9e: 1101 addi sp,sp,-32 + 3007fa0: ce06 sw ra,28(sp) + 3007fa2: cc22 sw s0,24(sp) + 3007fa4: 1000 addi s0,sp,32 + HAL_CRG_IpEnableSet(TIMER1_BASE, IP_CLK_ENABLE); /* TIMER1 clock enable. */ + 3007fa6: 4585 li a1,1 + 3007fa8: 14301537 lui a0,0x14301 + 3007fac: 2439 jal ra,30081ba + unsigned int load = (HAL_CRG_GetIpFreq((void *)TIMER1) / (1u << (TIMERPRESCALER_NO_DIV * 4)) / 1000000u) * 500; + 3007fae: 14301537 lui a0,0x14301 + 3007fb2: db8fa0ef jal ra,300256a + 3007fb6: 872a mv a4,a0 + 3007fb8: 000f47b7 lui a5,0xf4 + 3007fbc: 24078793 addi a5,a5,576 # f4240 + 3007fc0: 02f75733 divu a4,a4,a5 + 3007fc4: 1f400793 li a5,500 + 3007fc8: 02f707b3 mul a5,a4,a5 + 3007fcc: fef42623 sw a5,-20(s0) + + g_timer1.baseAddress = TIMER1; + 3007fd0: 040007b7 lui a5,0x4000 + 3007fd4: 4dc78793 addi a5,a5,1244 # 40004dc + 3007fd8: 14301737 lui a4,0x14301 + 3007fdc: c398 sw a4,0(a5) + g_timer1.load = load - 1; /* Set timer value immediately */ + 3007fde: fec42783 lw a5,-20(s0) + 3007fe2: fff78713 addi a4,a5,-1 + 3007fe6: 040007b7 lui a5,0x4000 + 3007fea: 4dc78793 addi a5,a5,1244 # 40004dc + 3007fee: cbd8 sw a4,20(a5) + g_timer1.bgLoad = load - 1; /* Set timer value */ + 3007ff0: fec42783 lw a5,-20(s0) + 3007ff4: fff78713 addi a4,a5,-1 + 3007ff8: 040007b7 lui a5,0x4000 + 3007ffc: 4dc78793 addi a5,a5,1244 # 40004dc + 3008000: cf98 sw a4,24(a5) + g_timer1.mode = TIMER_MODE_RUN_PERIODIC; /* Run in period mode */ + 3008002: 040007b7 lui a5,0x4000 + 3008006: 4dc78793 addi a5,a5,1244 # 40004dc + 300800a: 4705 li a4,1 + 300800c: c798 sw a4,8(a5) + g_timer1.prescaler = TIMERPRESCALER_NO_DIV; /* Don't frequency division */ + 300800e: 040007b7 lui a5,0x4000 + 3008012: 4dc78793 addi a5,a5,1244 # 40004dc + 3008016: 0007a623 sw zero,12(a5) + g_timer1.size = TIMER_SIZE_32BIT; /* 1 for 32bit, 0 for 16bit */ + 300801a: 040007b7 lui a5,0x4000 + 300801e: 4dc78793 addi a5,a5,1244 # 40004dc + 3008022: 4705 li a4,1 + 3008024: cb98 sw a4,16(a5) + g_timer1.interruptEn = BASE_CFG_ENABLE; + 3008026: 040007b7 lui a5,0x4000 + 300802a: 4dc78793 addi a5,a5,1244 # 40004dc + 300802e: 4705 li a4,1 + 3008030: afd8 sb a4,28(a5) + g_timer1.adcSocReqEnable = BASE_CFG_DISABLE; + 3008032: 040007b7 lui a5,0x4000 + 3008036: 4dc78793 addi a5,a5,1244 # 40004dc + 300803a: 00078ea3 sb zero,29(a5) + g_timer1.dmaReqEnable = BASE_CFG_DISABLE; + 300803e: 040007b7 lui a5,0x4000 + 3008042: 4dc78793 addi a5,a5,1244 # 40004dc + 3008046: 00078f23 sb zero,30(a5) + HAL_TIMER_Init(&g_timer1); + 300804a: 040007b7 lui a5,0x4000 + 300804e: 4dc78513 addi a0,a5,1244 # 40004dc + 3008052: d5ffd0ef jal ra,3005db0 + IRQ_Register(IRQ_TIMER1, HAL_TIMER_IrqHandler, &g_timer1); + 3008056: 040007b7 lui a5,0x4000 + 300805a: 4dc78613 addi a2,a5,1244 # 40004dc + 300805e: 030067b7 lui a5,0x3006 + 3008062: 08478593 addi a1,a5,132 # 3006084 + 3008066: 02100513 li a0,33 + 300806a: 2cbd jal ra,30082e8 + + HAL_TIMER_RegisterCallback(&g_timer1, TIMER_PERIOD_FIN, TIMER1_InterruptProcess); + 300806c: 030077b7 lui a5,0x3007 + 3008070: 79278613 addi a2,a5,1938 # 3007792 + 3008074: 4581 li a1,0 + 3008076: 040007b7 lui a5,0x4000 + 300807a: 4dc78513 addi a0,a5,1244 # 40004dc + 300807e: 8eefe0ef jal ra,300616c + IRQ_SetPriority(IRQ_TIMER1, 1); /* 1 is priority value */ + 3008082: 4585 li a1,1 + 3008084: 02100513 li a0,33 + 3008088: 2cb1 jal ra,30082e4 + IRQ_EnableN(IRQ_TIMER1); + 300808a: 02100513 li a0,33 + 300808e: 2c89 jal ra,30082e0 +} + 3008090: 0001 nop + 3008092: 40f2 lw ra,28(sp) + 3008094: 4462 lw s0,24(sp) + 3008096: 6105 addi sp,sp,32 + 3008098: 8082 ret + +0300809a : + +__weak void UART0InterruptErrorCallback(void *handle) +{ + 300809a: 1101 addi sp,sp,-32 + 300809c: ce22 sw s0,28(sp) + 300809e: 1000 addi s0,sp,32 + 30080a0: fea42623 sw a0,-20(s0) + BASE_FUNC_UNUSED(handle); + /* USER CODE BEGIN UART0_TRNS_IT_ERROR */ + /* USER CODE END UART0_TRNS_IT_ERROR */ +} + 30080a4: 0001 nop + 30080a6: 4472 lw s0,28(sp) + 30080a8: 6105 addi sp,sp,32 + 30080aa: 8082 ret + +030080ac : + /* USER CODE BEGIN UART0_READ_IT_FINISH */ + /* USER CODE END UART0_READ_IT_FINISH */ +} + +static void UART0_Init(void) +{ + 30080ac: 1141 addi sp,sp,-16 + 30080ae: c606 sw ra,12(sp) + 30080b0: c422 sw s0,8(sp) + 30080b2: 0800 addi s0,sp,16 + HAL_CRG_IpEnableSet(UART0_BASE, IP_CLK_ENABLE); /* UART0 clock enable. */ + 30080b4: 4585 li a1,1 + 30080b6: 14000537 lui a0,0x14000 + 30080ba: 2201 jal ra,30081ba + g_uart0.baseAddress = UART0; + 30080bc: 040007b7 lui a5,0x4000 + 30080c0: 50478793 addi a5,a5,1284 # 4000504 + 30080c4: 14000737 lui a4,0x14000 + 30080c8: c398 sw a4,0(a5) + + g_uart0.baudRate = UART0_BAND_RATE; + 30080ca: 040007b7 lui a5,0x4000 + 30080ce: 50478793 addi a5,a5,1284 # 4000504 + 30080d2: 6771 lui a4,0x1c + 30080d4: 20070713 addi a4,a4,512 # 1c200 + 30080d8: c3d8 sw a4,4(a5) + g_uart0.dataLength = UART_DATALENGTH_8BIT; + 30080da: 040007b7 lui a5,0x4000 + 30080de: 50478793 addi a5,a5,1284 # 4000504 + 30080e2: 470d li a4,3 + 30080e4: c798 sw a4,8(a5) + g_uart0.stopBits = UART_STOPBITS_ONE; + 30080e6: 040007b7 lui a5,0x4000 + 30080ea: 50478793 addi a5,a5,1284 # 4000504 + 30080ee: 0007a623 sw zero,12(a5) + g_uart0.parity = UART_PARITY_NONE; + 30080f2: 040007b7 lui a5,0x4000 + 30080f6: 50478793 addi a5,a5,1284 # 4000504 + 30080fa: 4711 li a4,4 + 30080fc: cb98 sw a4,16(a5) + g_uart0.txMode = UART_MODE_BLOCKING; + 30080fe: 040007b7 lui a5,0x4000 + 3008102: 50478793 addi a5,a5,1284 # 4000504 + 3008106: 0007aa23 sw zero,20(a5) + g_uart0.rxMode = UART_MODE_INTERRUPT; + 300810a: 040007b7 lui a5,0x4000 + 300810e: 50478793 addi a5,a5,1284 # 4000504 + 3008112: 4705 li a4,1 + 3008114: cf98 sw a4,24(a5) + g_uart0.fifoMode = BASE_CFG_DISABLE; + 3008116: 040007b7 lui a5,0x4000 + 300811a: 50478793 addi a5,a5,1284 # 4000504 + 300811e: 02078623 sb zero,44(a5) + g_uart0.fifoTxThr = UART_FIFODEPTH_SIZE8; + 3008122: 040007b7 lui a5,0x4000 + 3008126: 50478793 addi a5,a5,1284 # 4000504 + 300812a: 4721 li a4,8 + 300812c: db98 sw a4,48(a5) + g_uart0.fifoRxThr = UART_FIFODEPTH_SIZE8; + 300812e: 040007b7 lui a5,0x4000 + 3008132: 50478793 addi a5,a5,1284 # 4000504 + 3008136: 4721 li a4,8 + 3008138: dbd8 sw a4,52(a5) + g_uart0.hwFlowCtr = BASE_CFG_DISABLE; + 300813a: 040007b7 lui a5,0x4000 + 300813e: 50478793 addi a5,a5,1284 # 4000504 + 3008142: 0207ac23 sw zero,56(a5) + g_uart0.handleEx.overSampleMultiple = UART_OVERSAMPLING_16X; + 3008146: 040007b7 lui a5,0x4000 + 300814a: 50478793 addi a5,a5,1284 # 4000504 + 300814e: 0607ac23 sw zero,120(a5) + g_uart0.handleEx.msbFirst = BASE_CFG_DISABLE; + 3008152: 040007b7 lui a5,0x4000 + 3008156: 50478793 addi a5,a5,1284 # 4000504 + 300815a: 06078e23 sb zero,124(a5) + HAL_UART_Init(&g_uart0); + 300815e: 040007b7 lui a5,0x4000 + 3008162: 50478513 addi a0,a5,1284 # 4000504 + 3008166: b78fe0ef jal ra,30064de + HAL_UART_RegisterCallBack(&g_uart0, UART_TRNS_IT_ERROR, (UART_CallbackType)UART0InterruptErrorCallback); + 300816a: 030087b7 lui a5,0x3008 + 300816e: 09a78613 addi a2,a5,154 # 300809a + 3008172: 4591 li a1,4 + 3008174: 040007b7 lui a5,0x4000 + 3008178: 50478513 addi a0,a5,1284 # 4000504 + 300817c: 2285 jal ra,30082dc + HAL_UART_RegisterCallBack(&g_uart0, UART_READ_IT_FINISH, (UART_CallbackType)UART0ReadInterruptCallback); + 300817e: 030077b7 lui a5,0x3007 + 3008182: 49078613 addi a2,a5,1168 # 3007490 + 3008186: 4585 li a1,1 + 3008188: 040007b7 lui a5,0x4000 + 300818c: 50478513 addi a0,a5,1284 # 4000504 + 3008190: 22b1 jal ra,30082dc + IRQ_Register(IRQ_UART0, HAL_UART_IrqHandler, &g_uart0); + 3008192: 040007b7 lui a5,0x4000 + 3008196: 50478613 addi a2,a5,1284 # 4000504 + 300819a: 030077b7 lui a5,0x3007 + 300819e: ffc78593 addi a1,a5,-4 # 3006ffc + 30081a2: 4571 li a0,28 + 30081a4: 2291 jal ra,30082e8 + IRQ_SetPriority(IRQ_UART0, 1); /* 1 is priority value */ + 30081a6: 4585 li a1,1 + 30081a8: 4571 li a0,28 + 30081aa: 2a2d jal ra,30082e4 + IRQ_EnableN(IRQ_UART0); + 30081ac: 4571 li a0,28 + 30081ae: 2a0d jal ra,30082e0 +} + 30081b0: 0001 nop + 30081b2: 40b2 lw ra,12(sp) + 30081b4: 4422 lw s0,8(sp) + 30081b6: 0141 addi sp,sp,16 + 30081b8: 8082 ret + +030081ba : + 30081ba: c96fa06f j 3002650 + +030081be : + +__weak void UART2InterruptErrorCallback(void *handle) +{ + 30081be: 1101 addi sp,sp,-32 + 30081c0: ce22 sw s0,28(sp) + 30081c2: 1000 addi s0,sp,32 + 30081c4: fea42623 sw a0,-20(s0) + BASE_FUNC_UNUSED(handle); + /* USER CODE BEGIN UART2_TRNS_IT_ERROR */ + /* USER CODE END UART2_TRNS_IT_ERROR */ +} + 30081c8: 0001 nop + 30081ca: 4472 lw s0,28(sp) + 30081cc: 6105 addi sp,sp,32 + 30081ce: 8082 ret + +030081d0 : + /* USER CODE BEGIN UART2_READ_IT_FINISH */ + /* USER CODE END UART2_READ_IT_FINISH */ +} + +static void UART2_Init(void) +{ + 30081d0: 1141 addi sp,sp,-16 + 30081d2: c606 sw ra,12(sp) + 30081d4: c422 sw s0,8(sp) + 30081d6: 0800 addi s0,sp,16 + HAL_CRG_IpEnableSet(UART2_BASE, IP_CLK_ENABLE); /* UART2 clock enable. */ + 30081d8: 4585 li a1,1 + 30081da: 14002537 lui a0,0x14002 + 30081de: 3ff1 jal ra,30081ba + g_uart2.baseAddress = UART2; + 30081e0: 040007b7 lui a5,0x4000 + 30081e4: 58478793 addi a5,a5,1412 # 4000584 + 30081e8: 14002737 lui a4,0x14002 + 30081ec: c398 sw a4,0(a5) + + g_uart2.baudRate = UART2_BAND_RATE; + 30081ee: 040007b7 lui a5,0x4000 + 30081f2: 58478793 addi a5,a5,1412 # 4000584 + 30081f6: 000e1737 lui a4,0xe1 + 30081fa: c3d8 sw a4,4(a5) + g_uart2.dataLength = UART_DATALENGTH_8BIT; + 30081fc: 040007b7 lui a5,0x4000 + 3008200: 58478793 addi a5,a5,1412 # 4000584 + 3008204: 470d li a4,3 + 3008206: c798 sw a4,8(a5) + g_uart2.stopBits = UART_STOPBITS_ONE; + 3008208: 040007b7 lui a5,0x4000 + 300820c: 58478793 addi a5,a5,1412 # 4000584 + 3008210: 0007a623 sw zero,12(a5) + g_uart2.parity = UART_PARITY_NONE; + 3008214: 040007b7 lui a5,0x4000 + 3008218: 58478793 addi a5,a5,1412 # 4000584 + 300821c: 4711 li a4,4 + 300821e: cb98 sw a4,16(a5) + g_uart2.txMode = UART_MODE_BLOCKING; + 3008220: 040007b7 lui a5,0x4000 + 3008224: 58478793 addi a5,a5,1412 # 4000584 + 3008228: 0007aa23 sw zero,20(a5) + g_uart2.rxMode = UART_MODE_INTERRUPT; + 300822c: 040007b7 lui a5,0x4000 + 3008230: 58478793 addi a5,a5,1412 # 4000584 + 3008234: 4705 li a4,1 + 3008236: cf98 sw a4,24(a5) + g_uart2.fifoMode = BASE_CFG_DISABLE; + 3008238: 040007b7 lui a5,0x4000 + 300823c: 58478793 addi a5,a5,1412 # 4000584 + 3008240: 02078623 sb zero,44(a5) + g_uart2.fifoTxThr = UART_FIFODEPTH_SIZE8; + 3008244: 040007b7 lui a5,0x4000 + 3008248: 58478793 addi a5,a5,1412 # 4000584 + 300824c: 4721 li a4,8 + 300824e: db98 sw a4,48(a5) + g_uart2.fifoRxThr = UART_FIFODEPTH_SIZE8; + 3008250: 040007b7 lui a5,0x4000 + 3008254: 58478793 addi a5,a5,1412 # 4000584 + 3008258: 4721 li a4,8 + 300825a: dbd8 sw a4,52(a5) + g_uart2.hwFlowCtr = BASE_CFG_DISABLE; + 300825c: 040007b7 lui a5,0x4000 + 3008260: 58478793 addi a5,a5,1412 # 4000584 + 3008264: 0207ac23 sw zero,56(a5) + g_uart2.handleEx.overSampleMultiple = UART_OVERSAMPLING_16X; + 3008268: 040007b7 lui a5,0x4000 + 300826c: 58478793 addi a5,a5,1412 # 4000584 + 3008270: 0607ac23 sw zero,120(a5) + g_uart2.handleEx.msbFirst = BASE_CFG_DISABLE; + 3008274: 040007b7 lui a5,0x4000 + 3008278: 58478793 addi a5,a5,1412 # 4000584 + 300827c: 06078e23 sb zero,124(a5) + HAL_UART_Init(&g_uart2); + 3008280: 040007b7 lui a5,0x4000 + 3008284: 58478513 addi a0,a5,1412 # 4000584 + 3008288: a56fe0ef jal ra,30064de + HAL_UART_RegisterCallBack(&g_uart2, UART_TRNS_IT_ERROR, (UART_CallbackType)UART2InterruptErrorCallback); + 300828c: 030087b7 lui a5,0x3008 + 3008290: 1be78613 addi a2,a5,446 # 30081be + 3008294: 4591 li a1,4 + 3008296: 040007b7 lui a5,0x4000 + 300829a: 58478513 addi a0,a5,1412 # 4000584 + 300829e: 283d jal ra,30082dc + HAL_UART_RegisterCallBack(&g_uart2, UART_READ_IT_FINISH, (UART_CallbackType)UART2ReadInterruptCallback); + 30082a0: 030077b7 lui a5,0x3007 + 30082a4: 4fc78613 addi a2,a5,1276 # 30074fc + 30082a8: 4585 li a1,1 + 30082aa: 040007b7 lui a5,0x4000 + 30082ae: 58478513 addi a0,a5,1412 # 4000584 + 30082b2: 202d jal ra,30082dc + IRQ_Register(IRQ_UART2, HAL_UART_IrqHandler, &g_uart2); + 30082b4: 040007b7 lui a5,0x4000 + 30082b8: 58478613 addi a2,a5,1412 # 4000584 + 30082bc: 030077b7 lui a5,0x3007 + 30082c0: ffc78593 addi a1,a5,-4 # 3006ffc + 30082c4: 4579 li a0,30 + 30082c6: 200d jal ra,30082e8 + IRQ_SetPriority(IRQ_UART2, 1); /* 1 is priority value */ + 30082c8: 4585 li a1,1 + 30082ca: 4579 li a0,30 + 30082cc: 2821 jal ra,30082e4 + IRQ_EnableN(IRQ_UART2); + 30082ce: 4579 li a0,30 + 30082d0: 2801 jal ra,30082e0 +} + 30082d2: 0001 nop + 30082d4: 40b2 lw ra,12(sp) + 30082d6: 4422 lw s0,8(sp) + 30082d8: 0141 addi sp,sp,16 + 30082da: 8082 ret + +030082dc : + 30082dc: e7ffe06f j 300715a + +030082e0 : + 30082e0: 9b0f906f j 3001490 + +030082e4 : + 30082e4: 8fbf906f j 3001bde + +030082e8 : + 30082e8: 922f906f j 300140a + +030082ec : + +static void IOConfig(void) +{ + 30082ec: 1141 addi sp,sp,-16 + 30082ee: c606 sw ra,12(sp) + 30082f0: c422 sw s0,8(sp) + 30082f2: 0800 addi s0,sp,16 + /* Config PIN36 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO0_0_AS_JTAG_TCK); /* Check function selection */ + 30082f4: 018807b7 lui a5,0x1880 + 30082f8: 2b178513 addi a0,a5,689 # 18802b1 + 30082fc: 2e79 jal ra,300869a + HAL_IOCMG_SetPinPullMode(GPIO0_0_AS_JTAG_TCK, PULL_NONE); /* Pull-up and Pull-down */ + 30082fe: 4581 li a1,0 + 3008300: 018807b7 lui a5,0x1880 + 3008304: 2b178513 addi a0,a5,689 # 18802b1 + 3008308: 2679 jal ra,3008696 + HAL_IOCMG_SetPinSchmidtMode(GPIO0_0_AS_JTAG_TCK, SCHMIDT_DISABLE); /* Schmitt input on/off */ + 300830a: 4581 li a1,0 + 300830c: 018807b7 lui a5,0x1880 + 3008310: 2b178513 addi a0,a5,689 # 18802b1 + 3008314: 2ebd jal ra,3008692 + HAL_IOCMG_SetPinLevelShiftRate(GPIO0_0_AS_JTAG_TCK, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + 3008316: 4585 li a1,1 + 3008318: 018807b7 lui a5,0x1880 + 300831c: 2b178513 addi a0,a5,689 # 18802b1 + 3008320: 26bd jal ra,300868e + HAL_IOCMG_SetPinDriveRate(GPIO0_0_AS_JTAG_TCK, DRIVER_RATE_2); /* Output signal edge fast/slow */ + 3008322: 4589 li a1,2 + 3008324: 018807b7 lui a5,0x1880 + 3008328: 2b178513 addi a0,a5,689 # 18802b1 + 300832c: 2eb9 jal ra,300868a + /* Config PIN37 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO0_1_AS_JTAG_TMS); /* Check function selection */ + 300832e: 018c07b7 lui a5,0x18c0 + 3008332: 31178513 addi a0,a5,785 # 18c0311 + 3008336: 2695 jal ra,300869a + HAL_IOCMG_SetPinPullMode(GPIO0_1_AS_JTAG_TMS, PULL_NONE); /* Pull-up and Pull-down */ + 3008338: 4581 li a1,0 + 300833a: 018c07b7 lui a5,0x18c0 + 300833e: 31178513 addi a0,a5,785 # 18c0311 + 3008342: 2e91 jal ra,3008696 + HAL_IOCMG_SetPinSchmidtMode(GPIO0_1_AS_JTAG_TMS, SCHMIDT_DISABLE); /* Schmitt input on/off */ + 3008344: 4581 li a1,0 + 3008346: 018c07b7 lui a5,0x18c0 + 300834a: 31178513 addi a0,a5,785 # 18c0311 + 300834e: 2691 jal ra,3008692 + HAL_IOCMG_SetPinLevelShiftRate(GPIO0_1_AS_JTAG_TMS, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + 3008350: 4585 li a1,1 + 3008352: 018c07b7 lui a5,0x18c0 + 3008356: 31178513 addi a0,a5,785 # 18c0311 + 300835a: 2e15 jal ra,300868e + HAL_IOCMG_SetPinDriveRate(GPIO0_1_AS_JTAG_TMS, DRIVER_RATE_2); /* Output signal edge fast/slow */ + 300835c: 4589 li a1,2 + 300835e: 018c07b7 lui a5,0x18c0 + 3008362: 31178513 addi a0,a5,785 # 18c0311 + 3008366: 2615 jal ra,300868a + /* Config PIN35 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO2_3_AS_GPIO2_3); /* Check function selection */ + 3008368: 018407b7 lui a5,0x1840 + 300836c: 23078513 addi a0,a5,560 # 1840230 + 3008370: 262d jal ra,300869a + HAL_IOCMG_SetPinPullMode(GPIO2_3_AS_GPIO2_3, PULL_NONE); /* Pull-up and Pull-down */ + 3008372: 4581 li a1,0 + 3008374: 018407b7 lui a5,0x1840 + 3008378: 23078513 addi a0,a5,560 # 1840230 + 300837c: 2e29 jal ra,3008696 + HAL_IOCMG_SetPinSchmidtMode(GPIO2_3_AS_GPIO2_3, SCHMIDT_DISABLE); /* Schmitt input on/off */ + 300837e: 4581 li a1,0 + 3008380: 018407b7 lui a5,0x1840 + 3008384: 23078513 addi a0,a5,560 # 1840230 + 3008388: 2629 jal ra,3008692 + HAL_IOCMG_SetPinLevelShiftRate(GPIO2_3_AS_GPIO2_3, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + 300838a: 4585 li a1,1 + 300838c: 018407b7 lui a5,0x1840 + 3008390: 23078513 addi a0,a5,560 # 1840230 + 3008394: 2ced jal ra,300868e + HAL_IOCMG_SetPinDriveRate(GPIO2_3_AS_GPIO2_3, DRIVER_RATE_2); /* Output signal edge fast/slow */ + 3008396: 4589 li a1,2 + 3008398: 018407b7 lui a5,0x1840 + 300839c: 23078513 addi a0,a5,560 # 1840230 + 30083a0: 24ed jal ra,300868a + /* Config PIN27 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO1_0_AS_GPIO1_0); /* Check function selection */ + 30083a2: 016807b7 lui a5,0x1680 + 30083a6: 23078513 addi a0,a5,560 # 1680230 + 30083aa: 2cc5 jal ra,300869a + HAL_IOCMG_SetPinPullMode(GPIO1_0_AS_GPIO1_0, PULL_NONE); /* Pull-up and Pull-down */ + 30083ac: 4581 li a1,0 + 30083ae: 016807b7 lui a5,0x1680 + 30083b2: 23078513 addi a0,a5,560 # 1680230 + 30083b6: 24c5 jal ra,3008696 + HAL_IOCMG_SetPinSchmidtMode(GPIO1_0_AS_GPIO1_0, SCHMIDT_DISABLE); /* Schmitt input on/off */ + 30083b8: 4581 li a1,0 + 30083ba: 016807b7 lui a5,0x1680 + 30083be: 23078513 addi a0,a5,560 # 1680230 + 30083c2: 2cc1 jal ra,3008692 + HAL_IOCMG_SetPinLevelShiftRate(GPIO1_0_AS_GPIO1_0, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + 30083c4: 4585 li a1,1 + 30083c6: 016807b7 lui a5,0x1680 + 30083ca: 23078513 addi a0,a5,560 # 1680230 + 30083ce: 24c1 jal ra,300868e + HAL_IOCMG_SetPinDriveRate(GPIO1_0_AS_GPIO1_0, DRIVER_RATE_2); /* Output signal edge fast/slow */ + 30083d0: 4589 li a1,2 + 30083d2: 016807b7 lui a5,0x1680 + 30083d6: 23078513 addi a0,a5,560 # 1680230 + 30083da: 2c45 jal ra,300868a + /* Config PIN41 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO2_4_AS_GPIO2_4); /* Check function selection */ + 30083dc: 001c07b7 lui a5,0x1c0 + 30083e0: 23078513 addi a0,a5,560 # 1c0230 + 30083e4: 2c5d jal ra,300869a + HAL_IOCMG_SetPinPullMode(GPIO2_4_AS_GPIO2_4, PULL_NONE); /* Pull-up and Pull-down */ + 30083e6: 4581 li a1,0 + 30083e8: 001c07b7 lui a5,0x1c0 + 30083ec: 23078513 addi a0,a5,560 # 1c0230 + 30083f0: 245d jal ra,3008696 + HAL_IOCMG_SetPinSchmidtMode(GPIO2_4_AS_GPIO2_4, SCHMIDT_DISABLE); /* Schmitt input on/off */ + 30083f2: 4581 li a1,0 + 30083f4: 001c07b7 lui a5,0x1c0 + 30083f8: 23078513 addi a0,a5,560 # 1c0230 + 30083fc: 2c59 jal ra,3008692 + HAL_IOCMG_SetPinLevelShiftRate(GPIO2_4_AS_GPIO2_4, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + 30083fe: 4585 li a1,1 + 3008400: 001c07b7 lui a5,0x1c0 + 3008404: 23078513 addi a0,a5,560 # 1c0230 + 3008408: 2459 jal ra,300868e + HAL_IOCMG_SetPinDriveRate(GPIO2_4_AS_GPIO2_4, DRIVER_RATE_2); /* Output signal edge fast/slow */ + 300840a: 4589 li a1,2 + 300840c: 001c07b7 lui a5,0x1c0 + 3008410: 23078513 addi a0,a5,560 # 1c0230 + 3008414: 2c9d jal ra,300868a + /* Config PIN6 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO5_2_AS_GPIO5_2); /* Check function selection */ + 3008416: 011407b7 lui a5,0x1140 + 300841a: 23078513 addi a0,a5,560 # 1140230 + 300841e: 2cb5 jal ra,300869a + HAL_IOCMG_SetPinPullMode(GPIO5_2_AS_GPIO5_2, PULL_NONE); /* Pull-up and Pull-down */ + 3008420: 4581 li a1,0 + 3008422: 011407b7 lui a5,0x1140 + 3008426: 23078513 addi a0,a5,560 # 1140230 + 300842a: 24b5 jal ra,3008696 + HAL_IOCMG_SetPinSchmidtMode(GPIO5_2_AS_GPIO5_2, SCHMIDT_DISABLE); /* Schmitt input on/off */ + 300842c: 4581 li a1,0 + 300842e: 011407b7 lui a5,0x1140 + 3008432: 23078513 addi a0,a5,560 # 1140230 + 3008436: 2cb1 jal ra,3008692 + HAL_IOCMG_SetPinLevelShiftRate(GPIO5_2_AS_GPIO5_2, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + 3008438: 4585 li a1,1 + 300843a: 011407b7 lui a5,0x1140 + 300843e: 23078513 addi a0,a5,560 # 1140230 + 3008442: 24b1 jal ra,300868e + HAL_IOCMG_SetPinDriveRate(GPIO5_2_AS_GPIO5_2, DRIVER_RATE_2); /* Output signal edge fast/slow */ + 3008444: 4589 li a1,2 + 3008446: 011407b7 lui a5,0x1140 + 300844a: 23078513 addi a0,a5,560 # 1140230 + 300844e: 2c35 jal ra,300868a + /* Config PIN8 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO3_6_AS_GPIO3_6); /* Check function selection */ + 3008450: 011c07b7 lui a5,0x11c0 + 3008454: 23078513 addi a0,a5,560 # 11c0230 + 3008458: 2489 jal ra,300869a + HAL_IOCMG_SetPinPullMode(GPIO3_6_AS_GPIO3_6, PULL_NONE); /* Pull-up and Pull-down */ + 300845a: 4581 li a1,0 + 300845c: 011c07b7 lui a5,0x11c0 + 3008460: 23078513 addi a0,a5,560 # 11c0230 + 3008464: 2c0d jal ra,3008696 + HAL_IOCMG_SetPinSchmidtMode(GPIO3_6_AS_GPIO3_6, SCHMIDT_DISABLE); /* Schmitt input on/off */ + 3008466: 4581 li a1,0 + 3008468: 011c07b7 lui a5,0x11c0 + 300846c: 23078513 addi a0,a5,560 # 11c0230 + 3008470: 240d jal ra,3008692 + HAL_IOCMG_SetPinLevelShiftRate(GPIO3_6_AS_GPIO3_6, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + 3008472: 4585 li a1,1 + 3008474: 011c07b7 lui a5,0x11c0 + 3008478: 23078513 addi a0,a5,560 # 11c0230 + 300847c: 2c09 jal ra,300868e + HAL_IOCMG_SetPinDriveRate(GPIO3_6_AS_GPIO3_6, DRIVER_RATE_2); /* Output signal edge fast/slow */ + 300847e: 4589 li a1,2 + 3008480: 011c07b7 lui a5,0x11c0 + 3008484: 23078513 addi a0,a5,560 # 11c0230 + 3008488: 2409 jal ra,300868a + /* Config PIN10 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO5_3_AS_GPIO5_3); /* Check function selection */ + 300848a: 012407b7 lui a5,0x1240 + 300848e: 23078513 addi a0,a5,560 # 1240230 + 3008492: 2421 jal ra,300869a + HAL_IOCMG_SetPinPullMode(GPIO5_3_AS_GPIO5_3, PULL_NONE); /* Pull-up and Pull-down */ + 3008494: 4581 li a1,0 + 3008496: 012407b7 lui a5,0x1240 + 300849a: 23078513 addi a0,a5,560 # 1240230 + 300849e: 2ae5 jal ra,3008696 + HAL_IOCMG_SetPinSchmidtMode(GPIO5_3_AS_GPIO5_3, SCHMIDT_DISABLE); /* Schmitt input on/off */ + 30084a0: 4581 li a1,0 + 30084a2: 012407b7 lui a5,0x1240 + 30084a6: 23078513 addi a0,a5,560 # 1240230 + 30084aa: 22e5 jal ra,3008692 + HAL_IOCMG_SetPinLevelShiftRate(GPIO5_3_AS_GPIO5_3, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + 30084ac: 4585 li a1,1 + 30084ae: 012407b7 lui a5,0x1240 + 30084b2: 23078513 addi a0,a5,560 # 1240230 + 30084b6: 2ae1 jal ra,300868e + HAL_IOCMG_SetPinDriveRate(GPIO5_3_AS_GPIO5_3, DRIVER_RATE_2); /* Output signal edge fast/slow */ + 30084b8: 4589 li a1,2 + 30084ba: 012407b7 lui a5,0x1240 + 30084be: 23078513 addi a0,a5,560 # 1240230 + 30084c2: 22e1 jal ra,300868a + /* Config PIN2 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO5_1_AS_GPIO5_1); /* Check function selection */ + 30084c4: 010407b7 lui a5,0x1040 + 30084c8: 23078513 addi a0,a5,560 # 1040230 + 30084cc: 22f9 jal ra,300869a + HAL_IOCMG_SetPinPullMode(GPIO5_1_AS_GPIO5_1, PULL_NONE); /* Pull-up and Pull-down */ + 30084ce: 4581 li a1,0 + 30084d0: 010407b7 lui a5,0x1040 + 30084d4: 23078513 addi a0,a5,560 # 1040230 + 30084d8: 2a7d jal ra,3008696 + HAL_IOCMG_SetPinSchmidtMode(GPIO5_1_AS_GPIO5_1, SCHMIDT_DISABLE); /* Schmitt input on/off */ + 30084da: 4581 li a1,0 + 30084dc: 010407b7 lui a5,0x1040 + 30084e0: 23078513 addi a0,a5,560 # 1040230 + 30084e4: 227d jal ra,3008692 + HAL_IOCMG_SetPinLevelShiftRate(GPIO5_1_AS_GPIO5_1, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + 30084e6: 4585 li a1,1 + 30084e8: 010407b7 lui a5,0x1040 + 30084ec: 23078513 addi a0,a5,560 # 1040230 + 30084f0: 2a79 jal ra,300868e + HAL_IOCMG_SetPinDriveRate(GPIO5_1_AS_GPIO5_1, DRIVER_RATE_2); /* Output signal edge fast/slow */ + 30084f2: 4589 li a1,2 + 30084f4: 010407b7 lui a5,0x1040 + 30084f8: 23078513 addi a0,a5,560 # 1040230 + 30084fc: 2279 jal ra,300868a + /* Config PIN38 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO0_2_AS_RESETN); /* Check function selection */ + 30084fe: 73100513 li a0,1841 + 3008502: 2a61 jal ra,300869a + HAL_IOCMG_SetPinPullMode(GPIO0_2_AS_RESETN, PULL_NONE); /* Pull-up and Pull-down */ + 3008504: 4581 li a1,0 + 3008506: 73100513 li a0,1841 + 300850a: 2271 jal ra,3008696 + HAL_IOCMG_SetPinSchmidtMode(GPIO0_2_AS_RESETN, SCHMIDT_DISABLE); /* Schmitt input on/off */ + 300850c: 4581 li a1,0 + 300850e: 73100513 li a0,1841 + 3008512: 2241 jal ra,3008692 + HAL_IOCMG_SetPinLevelShiftRate(GPIO0_2_AS_RESETN, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + 3008514: 4585 li a1,1 + 3008516: 73100513 li a0,1841 + 300851a: 2a95 jal ra,300868e + HAL_IOCMG_SetPinDriveRate(GPIO0_2_AS_RESETN, DRIVER_RATE_2); /* Output signal edge fast/slow */ + 300851c: 4589 li a1,2 + 300851e: 73100513 li a0,1841 + 3008522: 22a5 jal ra,300868a + /* Config PIN39 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO0_3_AS_UART0_TXD); /* Check function selection */ + 3008524: 019007b7 lui a5,0x1900 + 3008528: 23378513 addi a0,a5,563 # 1900233 + 300852c: 22bd jal ra,300869a + HAL_IOCMG_SetPinPullMode(GPIO0_3_AS_UART0_TXD, PULL_NONE); /* Pull-up and Pull-down */ + 300852e: 4581 li a1,0 + 3008530: 019007b7 lui a5,0x1900 + 3008534: 23378513 addi a0,a5,563 # 1900233 + 3008538: 2ab9 jal ra,3008696 + HAL_IOCMG_SetPinSchmidtMode(GPIO0_3_AS_UART0_TXD, SCHMIDT_DISABLE); /* Schmitt input on/off */ + 300853a: 4581 li a1,0 + 300853c: 019007b7 lui a5,0x1900 + 3008540: 23378513 addi a0,a5,563 # 1900233 + 3008544: 22b9 jal ra,3008692 + HAL_IOCMG_SetPinLevelShiftRate(GPIO0_3_AS_UART0_TXD, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + 3008546: 4585 li a1,1 + 3008548: 019007b7 lui a5,0x1900 + 300854c: 23378513 addi a0,a5,563 # 1900233 + 3008550: 2a3d jal ra,300868e + HAL_IOCMG_SetPinDriveRate(GPIO0_3_AS_UART0_TXD, DRIVER_RATE_2); /* Output signal edge fast/slow */ + 3008552: 4589 li a1,2 + 3008554: 019007b7 lui a5,0x1900 + 3008558: 23378513 addi a0,a5,563 # 1900233 + 300855c: 223d jal ra,300868a + /* Config PIN40 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO0_4_AS_UART0_RXD); /* Check function selection */ + 300855e: 019407b7 lui a5,0x1940 + 3008562: 23378513 addi a0,a5,563 # 1940233 + 3008566: 2a15 jal ra,300869a + HAL_IOCMG_SetPinPullMode(GPIO0_4_AS_UART0_RXD, PULL_UP); /* Pull-up and Pull-down, UART RX recommend PULL_UP */ + 3008568: 4589 li a1,2 + 300856a: 019407b7 lui a5,0x1940 + 300856e: 23378513 addi a0,a5,563 # 1940233 + 3008572: 2215 jal ra,3008696 + HAL_IOCMG_SetPinSchmidtMode(GPIO0_4_AS_UART0_RXD, SCHMIDT_DISABLE); /* Schmitt input on/off */ + 3008574: 4581 li a1,0 + 3008576: 019407b7 lui a5,0x1940 + 300857a: 23378513 addi a0,a5,563 # 1940233 + 300857e: 2a11 jal ra,3008692 + HAL_IOCMG_SetPinLevelShiftRate(GPIO0_4_AS_UART0_RXD, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + 3008580: 4585 li a1,1 + 3008582: 019407b7 lui a5,0x1940 + 3008586: 23378513 addi a0,a5,563 # 1940233 + 300858a: 2211 jal ra,300868e + HAL_IOCMG_SetPinDriveRate(GPIO0_4_AS_UART0_RXD, DRIVER_RATE_2); /* Output signal edge fast/slow */ + 300858c: 4589 li a1,2 + 300858e: 019407b7 lui a5,0x1940 + 3008592: 23378513 addi a0,a5,563 # 1940233 + 3008596: 28d5 jal ra,300868a + /* Config PIN11 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO1_5_AS_UART2_TXD); /* Check function selection */ + 3008598: 012807b7 lui a5,0x1280 + 300859c: 23378513 addi a0,a5,563 # 1280233 + 30085a0: 28ed jal ra,300869a + HAL_IOCMG_SetPinPullMode(GPIO1_5_AS_UART2_TXD, PULL_NONE); /* Pull-up and Pull-down */ + 30085a2: 4581 li a1,0 + 30085a4: 012807b7 lui a5,0x1280 + 30085a8: 23378513 addi a0,a5,563 # 1280233 + 30085ac: 20ed jal ra,3008696 + HAL_IOCMG_SetPinSchmidtMode(GPIO1_5_AS_UART2_TXD, SCHMIDT_DISABLE); /* Schmitt input on/off */ + 30085ae: 4581 li a1,0 + 30085b0: 012807b7 lui a5,0x1280 + 30085b4: 23378513 addi a0,a5,563 # 1280233 + 30085b8: 28e9 jal ra,3008692 + HAL_IOCMG_SetPinLevelShiftRate(GPIO1_5_AS_UART2_TXD, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + 30085ba: 4585 li a1,1 + 30085bc: 012807b7 lui a5,0x1280 + 30085c0: 23378513 addi a0,a5,563 # 1280233 + 30085c4: 20e9 jal ra,300868e + HAL_IOCMG_SetPinDriveRate(GPIO1_5_AS_UART2_TXD, DRIVER_RATE_2); /* Output signal edge fast/slow */ + 30085c6: 4589 li a1,2 + 30085c8: 012807b7 lui a5,0x1280 + 30085cc: 23378513 addi a0,a5,563 # 1280233 + 30085d0: 286d jal ra,300868a + /* Config PIN12 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO1_6_AS_UART2_RXD); /* Check function selection */ + 30085d2: 012c07b7 lui a5,0x12c0 + 30085d6: 23378513 addi a0,a5,563 # 12c0233 + 30085da: 20c1 jal ra,300869a + HAL_IOCMG_SetPinPullMode(GPIO1_6_AS_UART2_RXD, PULL_UP); /* Pull-up and Pull-down, UART RX recommend PULL_UP */ + 30085dc: 4589 li a1,2 + 30085de: 012c07b7 lui a5,0x12c0 + 30085e2: 23378513 addi a0,a5,563 # 12c0233 + 30085e6: 2845 jal ra,3008696 + HAL_IOCMG_SetPinSchmidtMode(GPIO1_6_AS_UART2_RXD, SCHMIDT_DISABLE); /* Schmitt input on/off */ + 30085e8: 4581 li a1,0 + 30085ea: 012c07b7 lui a5,0x12c0 + 30085ee: 23378513 addi a0,a5,563 # 12c0233 + 30085f2: 2045 jal ra,3008692 + HAL_IOCMG_SetPinLevelShiftRate(GPIO1_6_AS_UART2_RXD, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + 30085f4: 4585 li a1,1 + 30085f6: 012c07b7 lui a5,0x12c0 + 30085fa: 23378513 addi a0,a5,563 # 12c0233 + 30085fe: 2841 jal ra,300868e + HAL_IOCMG_SetPinDriveRate(GPIO1_6_AS_UART2_RXD, DRIVER_RATE_2); /* Output signal edge fast/slow */ + 3008600: 4589 li a1,2 + 3008602: 012c07b7 lui a5,0x12c0 + 3008606: 23378513 addi a0,a5,563 # 12c0233 + 300860a: 2041 jal ra,300868a + /* Config PIN31 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO2_0_AS_I2C0_SCL); /* Check function selection */ + 300860c: 017807b7 lui a5,0x1780 + 3008610: 23178513 addi a0,a5,561 # 1780231 + 3008614: 2059 jal ra,300869a + HAL_IOCMG_SetPinPullMode(GPIO2_0_AS_I2C0_SCL, PULL_NONE); /* Pull-up and Pull-down */ + 3008616: 4581 li a1,0 + 3008618: 017807b7 lui a5,0x1780 + 300861c: 23178513 addi a0,a5,561 # 1780231 + 3008620: 289d jal ra,3008696 + HAL_IOCMG_SetPinSchmidtMode(GPIO2_0_AS_I2C0_SCL, SCHMIDT_DISABLE); /* Schmitt input on/off */ + 3008622: 4581 li a1,0 + 3008624: 017807b7 lui a5,0x1780 + 3008628: 23178513 addi a0,a5,561 # 1780231 + 300862c: 209d jal ra,3008692 + HAL_IOCMG_SetPinLevelShiftRate(GPIO2_0_AS_I2C0_SCL, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + 300862e: 4585 li a1,1 + 3008630: 017807b7 lui a5,0x1780 + 3008634: 23178513 addi a0,a5,561 # 1780231 + 3008638: 2899 jal ra,300868e + HAL_IOCMG_SetPinDriveRate(GPIO2_0_AS_I2C0_SCL, DRIVER_RATE_2); /* Output signal edge fast/slow */ + 300863a: 4589 li a1,2 + 300863c: 017807b7 lui a5,0x1780 + 3008640: 23178513 addi a0,a5,561 # 1780231 + 3008644: 2099 jal ra,300868a + /* Config PIN32 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO2_1_AS_I2C0_SDA); /* Check function selection */ + 3008646: 017c07b7 lui a5,0x17c0 + 300864a: 23178513 addi a0,a5,561 # 17c0231 + 300864e: 20b1 jal ra,300869a + HAL_IOCMG_SetPinPullMode(GPIO2_1_AS_I2C0_SDA, PULL_NONE); /* Pull-up and Pull-down */ + 3008650: 4581 li a1,0 + 3008652: 017c07b7 lui a5,0x17c0 + 3008656: 23178513 addi a0,a5,561 # 17c0231 + 300865a: 2835 jal ra,3008696 + HAL_IOCMG_SetPinSchmidtMode(GPIO2_1_AS_I2C0_SDA, SCHMIDT_DISABLE); /* Schmitt input on/off */ + 300865c: 4581 li a1,0 + 300865e: 017c07b7 lui a5,0x17c0 + 3008662: 23178513 addi a0,a5,561 # 17c0231 + 3008666: 2035 jal ra,3008692 + HAL_IOCMG_SetPinLevelShiftRate(GPIO2_1_AS_I2C0_SDA, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + 3008668: 4585 li a1,1 + 300866a: 017c07b7 lui a5,0x17c0 + 300866e: 23178513 addi a0,a5,561 # 17c0231 + 3008672: 2831 jal ra,300868e + HAL_IOCMG_SetPinDriveRate(GPIO2_1_AS_I2C0_SDA, DRIVER_RATE_2); /* Output signal edge fast/slow */ + 3008674: 4589 li a1,2 + 3008676: 017c07b7 lui a5,0x17c0 + 300867a: 23178513 addi a0,a5,561 # 17c0231 + 300867e: 2031 jal ra,300868a +} + 3008680: 0001 nop + 3008682: 40b2 lw ra,12(sp) + 3008684: 4422 lw s0,8(sp) + 3008686: 0141 addi sp,sp,16 + 3008688: 8082 ret + +0300868a : + 300868a: dfafd06f j 3005c84 + +0300868e : + 300868e: daafd06f j 3005c38 + +03008692 : + 3008692: d5afd06f j 3005bec + +03008696 : + 3008696: d0afd06f j 3005ba0 + +0300869a : + 300869a: cccfd06f j 3005b66 + +0300869e : + +void SystemInit(void) +{ + 300869e: 1141 addi sp,sp,-16 + 30086a0: c606 sw ra,12(sp) + 30086a2: c422 sw s0,8(sp) + 30086a4: 0800 addi s0,sp,16 + IOConfig(); + 30086a6: 3199 jal ra,30082ec + UART0_Init(); + 30086a8: 3411 jal ra,30080ac + UART2_Init(); + 30086aa: 361d jal ra,30081d0 + TIMER0_Init(); + 30086ac: ff6ff0ef jal ra,3007ea2 + TIMER1_Init(); + 30086b0: 30fd jal ra,3007f9e + I2C0_Init(); + 30086b2: f3cff0ef jal ra,3007dee + GPIO_Init(); + 30086b6: cb0ff0ef jal ra,3007b66 + + /* USER CODE BEGIN system_init */ + /* USER CODE END system_init */ + 30086ba: 0001 nop + 30086bc: 40b2 lw ra,12(sp) + 30086be: 4422 lw s0,8(sp) + 30086c0: 0141 addi sp,sp,16 + 30086c2: 8082 ret + +030086c4 <__rodata_start>: + 30086c4: 9680 pop {ra,s0-s6},384 + 30086c6: 4b18 lw a4,16(a4) + +030086c8 : + 30086c8: 0000 1400 0000 0000 0140 0000 1000 1400 ........@....... + 30086d8: 0000 0000 0144 0000 2000 1400 0000 0000 ....D.... ...... + 30086e8: 0148 0000 3000 1400 0000 0000 014c 0000 H....0......L... + 30086f8: 0000 1430 0000 0000 0240 0000 1000 1430 ..0.....@.....0. + 3008708: 0000 0000 0244 0000 2000 1430 0000 0000 ....D.... 0..... + 3008718: 0248 0000 3000 1430 0000 0000 024c 0000 H....00.....L... + 3008728: 0000 1438 0000 0000 0040 0000 0000 1420 ..8.....@..... . + 3008738: 0000 0000 0180 0000 1000 1420 0000 0000 .......... ..... + 3008748: 0184 0000 0000 1410 0000 0000 01c0 0000 ................ + 3008758: 1000 1410 0000 0000 01c4 0000 0000 1460 ..............`. + 3008768: 0001 0000 02c0 0000 0000 1470 0000 0000 ..........p..... + 3008778: 0440 0000 1000 1470 0000 0000 0444 0000 @.....p.....D... + 3008788: 2000 1470 0000 0000 0448 0000 3000 1470 . p.....H....0p. + 3008798: 0000 0000 044c 0000 0000 1440 0000 0000 ....L.....@..... + 30087a8: 0200 0000 0000 14b0 0000 0000 0280 0000 ................ + 30087b8: 1000 14b0 0000 0000 0284 0000 2000 14b0 ............. .. + 30087c8: 0000 0000 0288 0000 0000 1c00 0000 0000 ................ + 30087d8: 0300 0000 0000 1450 0000 0000 0480 0000 ......P......... + 30087e8: 1000 1450 0000 0000 0484 0000 2000 1450 ..P.......... P. + 30087f8: 0000 0000 0488 0000 3000 1450 0000 0000 .........0P..... + 3008808: 048c 0000 4000 1450 0000 0000 0490 0000 .....@P......... + 3008818: 5000 1450 0000 0000 0494 0000 1000 1440 .PP...........@. + 3008828: 0004 0000 03c0 0000 0000 14c0 0000 0000 ................ + 3008838: 04c0 0000 1000 14c0 0000 0000 04c4 0000 ................ + 3008848: 0000 147d 0000 0000 0b00 0000 0000 1480 ..}............. + 3008858: 0000 0000 0380 0000 0000 14a0 0000 0000 ................ + 3008868: 0400 0000 1000 14a0 0000 0000 0404 0000 ................ + 3008878: 2000 14a0 0000 0000 0408 0000 3000 14a0 . ...........0.. + 3008888: 0000 0000 040c 0000 0000 1001 0000 0000 ................ + 3008898: 0340 0000 0000 1810 0005 0000 0a60 0000 @...........`... + 30088a8: 0000 1830 0005 0000 0a70 0000 0000 1840 ..0.....p.....@. + 30088b8: 0005 0000 0a80 0000 0000 1820 0005 0000 .......... ..... + 30088c8: 0a90 0000 1000 1820 0005 0000 0a90 0004 ...... ......... + 30088d8: 0000 1800 0002 0000 0a00 0000 0000 1471 ..............q. + 30088e8: 0003 0000 0500 0000 2e2e 642f 6972 6576 ........../drive + 30088f8: 7372 622f 7361 2f65 7273 2f63 6e69 6574 rs/base/src/inte + 3008908: 7272 7075 2e74 0063 1660 0300 16b2 0300 rrupt.c.`....... + 3008918: 1704 0300 1756 0300 17a8 0300 17fa 0300 ....V........... + 3008928: 184c 0300 189e 0300 1934 0300 1986 0300 L.......4....... + 3008938: 19d8 0300 1a2a 0300 1a7c 0300 1ace 0300 ....*...|....... + 3008948: 1b20 0300 1b72 0300 2e2e 642f 6972 6576 ...r...../drive + 3008958: 7372 632f 6772 692f 636e 632f 6772 695f rs/crg/inc/crg_i + 3008968: 2e70 0068 2e2e 642f 6972 6576 7372 632f p.h.../drivers/c + 3008978: 6772 732f 6372 632f 6772 632e 0000 0000 rg/src/crg.c.... + 3008988: 0000 0000 0001 0000 0002 0000 0003 0000 ................ + 3008998: 0004 0000 0005 0000 0006 0000 0007 0000 ................ + 30089a8: 25f2 0300 25fc 0300 2614 0300 25f2 0300 .%...%...&...%.. + 30089b8: 2630 0300 25f2 0300 2e2e 642f 6972 6576 0&...%..../drive + 30089c8: 7372 672f 6970 2f6f 6e69 2f63 7067 6f69 rs/gpio/inc/gpio + 30089d8: 695f 2e70 0068 0000 2e2e 642f 6972 6576 _ip.h...../drive + 30089e8: 7372 672f 6970 2f6f 7273 2f63 7067 6f69 rs/gpio/src/gpio + 30089f8: 632e 0000 2e2e 642f 6972 6576 7372 692f .c..../drivers/i + 3008a08: 6332 732f 6372 692f 6332 632e 0000 0000 2c/src/i2c.c.... + 3008a18: 4b40 0300 4b60 0300 4b76 0300 4bba 0300 @K..`K..vK...K.. + 3008a28: 4bd6 0300 2e2e 642f 6972 6576 7372 692f .K..../drivers/i + 3008a38: 636f 676d 692f 636e 692f 636f 676d 695f ocmg/inc/iocmg_i + 3008a48: 2e70 0068 2e2e 642f 6972 6576 7372 692f p.h.../drivers/i + 3008a58: 636f 676d 732f 6372 692f 636f 676d 632e ocmg/src/iocmg.c + 3008a68: 0000 0000 2e2e 642f 6972 6576 7372 742f ....../drivers/t + 3008a78: 6d69 7265 692f 636e 742f 6d69 7265 695f imer/inc/timer_i + 3008a88: 2e70 0068 2e2e 642f 6972 6576 7372 742f p.h.../drivers/t + 3008a98: 6d69 7265 732f 6372 742f 6d69 7265 632e imer/src/timer.c + 3008aa8: 0000 0000 6470 0300 6486 0300 649c 0300 ....pd...d...d.. + 3008ab8: 64b2 0300 64c8 0300 2e2e 642f 6972 6576 .d...d..../drive + 3008ac8: 7372 752f 7261 2f74 7273 2f63 6175 7472 rs/uart/src/uart + 3008ad8: 632e 0000 71ec 0300 71f8 0300 7204 0300 .c...q...q...r.. + 3008ae8: 7210 0300 721c 0300 7228 0300 7234 0300 .r...r..(r..4r.. + 3008af8: 7240 0300 724c 0300 761a 0300 7660 0300 @r..Lr...v..`v.. + 3008b08: 76a6 0300 76ec 0300 7732 0300 .v...v..2w.. + +03008b14 : + 3008b14: 00ef 0737 1738 0639 0041 0042 2d46 0f47 ..7.8.9.A.B.F-G. + 3008b24: 3c48 0049 1e4a 204c 1051 105e 2760 4280 H. + 3008b64: 3d5e 9665 9767 cd69 016a 2c6d 016e 0172 ^=e.g.i.j.m,n.r. + 3008b74: 3573 0074 0177 0000 s5t.w... + +03008b7c : + 3008b7c: 00ef 0041 0042 00ef 3c48 0049 1051 2083 ..A.B...H + + + + + + + diff --git a/vendor/xinlingyu_92_3061M/Project/out/obj/build/target.elf.ninja b/vendor/xinlingyu_92_3061M/Project/out/obj/build/target.elf.ninja new file mode 100644 index 0000000000000000000000000000000000000000..a5057bf7fc910183aa5f28d36e7eb3d7fda6aace --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/out/obj/build/target.elf.ninja @@ -0,0 +1,404 @@ +defines = -DFLOAT_SUPPORT +include_dirs = -I../chip/3061m -I../chip/3061m/chipinit -I../chip/3061m/chipinit/anatrim -I../chip/3061m/chipinit/anavrefinit -I../chip/3061m/chipinit/crginit -I../chip/3061m/chipinit/flashinit -I../chip/3061m/chipinit/systickinit -I../chip/3061m/fotp -I../chip/3061m/iomap -I../chip/3061m/ip_crg -I../drivers/acmp/common/inc -I../drivers/acmp/inc -I../drivers/adc/common/inc -I../drivers/adc/inc -I../drivers/apt/common/inc -I../drivers/apt/inc -I../drivers/base/common/inc -I../drivers/base/inc -I../drivers/can/common/inc -I../drivers/can/inc -I../drivers/capm/common/inc -I../drivers/capm/inc -I../drivers/cfd/common/inc -I../drivers/cfd/inc -I../drivers/cmm/common/inc -I../drivers/cmm/inc -I../drivers/crc/common/inc -I../drivers/crc/inc -I../drivers/crg/common/inc -I../drivers/crg/inc -I../drivers/dac/common/inc -I../drivers/dac/inc -I../drivers/debug/inc -I../drivers/debug/log/inc -I../drivers/dma/common/inc -I../drivers/dma/inc -I../drivers/flash/common/inc -I../drivers/flash/inc -I../drivers/gpio/common/inc -I../drivers/gpio/inc -I../drivers/gpt/common/inc -I../drivers/gpt/inc -I../drivers/i2c/common/inc -I../drivers/i2c/inc -I../drivers/iocmg/common -I../drivers/iocmg/inc -I../drivers/iwdg/common/inc -I../drivers/iwdg/inc -I../drivers/pga/common/inc -I../drivers/pga/inc -I../drivers/pmc/common/inc -I../drivers/pmc/inc -I../drivers/qdm/common/inc -I../drivers/qdm/inc -I../drivers/spi/common/inc -I../drivers/spi/inc -I../drivers/timer/common/inc -I../drivers/timer/inc -I../drivers/tsensor/common/inc -I../drivers/tsensor/inc -I../drivers/uart/common/inc -I../drivers/uart/inc -I../drivers/wwdg/common/inc -I../drivers/wwdg/inc -I../middleware/control_library/adc_calibra -I../middleware/control_library/brake -I../middleware/control_library/filter -I../middleware/control_library/foc_loop_ctrl -I../middleware/control_library/math -I../middleware/control_library/modulation -I../middleware/control_library/observer -I../middleware/control_library/pfc -I../middleware/control_library/pid_controller -I../middleware/control_library/power -I../middleware/control_library/protection -I../middleware/control_library/ramp -I../middleware/control_library/utilities -I../middleware/control_library/vf -I../middleware/hisilicon/libboundscheck_v1.1.16/include -I../middleware/hisilicon/libboundscheck_v1.1.16/src -I../middleware/thirdparty/sysroot/include -I../user -I../user/generatecode +asmflags = +cflags = -O0 -pipe -Wall -Wextra -Winit-self -Wmissing-include-dirs -Wtrampolines -Werror=undef -Wpointer-arith -Wlogical-op -Wstrict-prototypes -Wmissing-prototypes -Wjump-misses-init -Wformat=2 -Wfloat-equal -Wdate-time -Wswitch-default -Wimplicit-fallthrough=2 -Wno-missing-declarations -std=gnu11 -fsigned-char -fno-builtin -ffreestanding -nostdlib -fno-exceptions -fno-unwind-tables -fno-short-enums -fno-common -freg-struct-return -mabi=ilp32f -march=rv32imfc -fno-strict-aliasing -fdata-sections -ffunction-sections -falign-functions=2 -fno-schedule-insns -fno-optimize-strlen -fno-aggressive-loop-optimizations -Wa,-enable-c-lbu-sb -Wa,-enable-c-lhu-sh -msmall-data-limit=0 -fimm-compare -femit-muliadd -fmerge-immshf -femit-uxtb-uxth -femit-lli -fldm-stm-optimize -fno-inline-small-functions -mtune=size -mpush-pop -femit-clz -madjust-regorder -madjust-const-cost -freorder-commu-args -fimm-compare-expand -frmv-str-zero -mfp-const-opt -mswitch-jump-table -frtl-sequence-abstract -frtl-hoist-sink -fsafe-alias-multipointer -finline-optimize-size -fmuliadd-expand -mlli-expand -Wa,-mcjal-expand -foptimize-reg-alloc -fsplit-multi-zero-assignments -floop-optimize-size -mpattern-abstract -foptimize-pro-and-epilogue -fstrict-volatile-bitfields -Wcast-align -fstrong-eval-order -Wunused -Wvla -Wshadow -fvisibility=hidden -fsingle-precision-constant -g +target_output_name = target.elf + +build obj/chip/3061m/startup.o: asm ../chip/3061m/startup.S + source_file_part = startup.S + source_name_part = startup +build obj/chip/3061m/chipinit/chipinit.o: cc ../chip/3061m/chipinit/chipinit.c + source_file_part = chipinit.c + source_name_part = chipinit +build obj/chip/3061m/chipinit/anatrim/anatrim.o: cc ../chip/3061m/chipinit/anatrim/anatrim.c + source_file_part = anatrim.c + source_name_part = anatrim +build obj/chip/3061m/chipinit/anavrefinit/anavrefinit.o: cc ../chip/3061m/chipinit/anavrefinit/anavrefinit.c + source_file_part = anavrefinit.c + source_name_part = anavrefinit +build obj/chip/3061m/chipinit/crginit/crginit.o: cc ../chip/3061m/chipinit/crginit/crginit.c + source_file_part = crginit.c + source_name_part = crginit +build obj/chip/3061m/chipinit/flashinit/flashinit.o: cc ../chip/3061m/chipinit/flashinit/flashinit.c + source_file_part = flashinit.c + source_name_part = flashinit +build obj/chip/3061m/chipinit/systickinit/systickinit.o: cc ../chip/3061m/chipinit/systickinit/systickinit.c + source_file_part = systickinit.c + source_name_part = systickinit +build obj/chip/3061m/fotp/fotp_info_read.o: cc ../chip/3061m/fotp/fotp_info_read.c + source_file_part = fotp_info_read.c + source_name_part = fotp_info_read +build obj/chip/3061m/ip_crg/ip_crg_common.o: cc ../chip/3061m/ip_crg/ip_crg_common.c + source_file_part = ip_crg_common.c + source_name_part = ip_crg_common +build obj/drivers/acmp/src/acmp.o: cc ../drivers/acmp/src/acmp.c + source_file_part = acmp.c + source_name_part = acmp +build obj/drivers/acmp/src/acmp_ex.o: cc ../drivers/acmp/src/acmp_ex.c + source_file_part = acmp_ex.c + source_name_part = acmp_ex +build obj/drivers/adc/src/adc.o: cc ../drivers/adc/src/adc.c + source_file_part = adc.c + source_name_part = adc +build obj/drivers/adc/src/adc_ex.o: cc ../drivers/adc/src/adc_ex.c + source_file_part = adc_ex.c + source_name_part = adc_ex +build obj/drivers/apt/src/apt.o: cc ../drivers/apt/src/apt.c + source_file_part = apt.c + source_name_part = apt +build obj/drivers/base/src/assert.o: cc ../drivers/base/src/assert.c + source_file_part = assert.c + source_name_part = assert +build obj/drivers/base/src/base_math.o: cc ../drivers/base/src/base_math.c + source_file_part = base_math.c + source_name_part = base_math +build obj/drivers/base/src/clock.o: cc ../drivers/base/src/clock.c + source_file_part = clock.c + source_name_part = clock +build obj/drivers/base/src/generalfunc.o: cc ../drivers/base/src/generalfunc.c + source_file_part = generalfunc.c + source_name_part = generalfunc +build obj/drivers/base/src/interrupt.o: cc ../drivers/base/src/interrupt.c + source_file_part = interrupt.c + source_name_part = interrupt +build obj/drivers/base/src/lock.o: cc ../drivers/base/src/lock.c + source_file_part = lock.c + source_name_part = lock +build obj/drivers/base/src/reset.o: cc ../drivers/base/src/reset.c + source_file_part = reset.c + source_name_part = reset +build obj/drivers/can/src/can.o: cc ../drivers/can/src/can.c + source_file_part = can.c + source_name_part = can +build obj/drivers/capm/src/capm.o: cc ../drivers/capm/src/capm.c + source_file_part = capm.c + source_name_part = capm +build obj/drivers/cfd/src/cfd.o: cc ../drivers/cfd/src/cfd.c + source_file_part = cfd.c + source_name_part = cfd +build obj/drivers/cmm/src/cmm.o: cc ../drivers/cmm/src/cmm.c + source_file_part = cmm.c + source_name_part = cmm +build obj/drivers/crc/src/crc.o: cc ../drivers/crc/src/crc.c + source_file_part = crc.c + source_name_part = crc +build obj/drivers/crg/src/crg.o: cc ../drivers/crg/src/crg.c + source_file_part = crg.c + source_name_part = crg +build obj/drivers/dac/src/dac.o: cc ../drivers/dac/src/dac.c + source_file_part = dac.c + source_name_part = dac +build obj/drivers/debug/log/src/app_command.o: cc ../drivers/debug/log/src/app_command.c + source_file_part = app_command.c + source_name_part = app_command +build obj/drivers/debug/log/src/cmd.o: cc ../drivers/debug/log/src/cmd.c + source_file_part = cmd.c + source_name_part = cmd +build obj/drivers/debug/log/src/cmd_common.o: cc ../drivers/debug/log/src/cmd_common.c + source_file_part = cmd_common.c + source_name_part = cmd_common +build obj/drivers/debug/log/src/config.o: cc ../drivers/debug/log/src/config.c + source_file_part = config.c + source_name_part = config +build obj/drivers/debug/log/src/console.o: cc ../drivers/debug/log/src/console.c + source_file_part = console.c + source_name_part = console +build obj/drivers/debug/log/src/dfx_debug.o: cc ../drivers/debug/log/src/dfx_debug.c + source_file_part = dfx_debug.c + source_name_part = dfx_debug +build obj/drivers/debug/log/src/dfx_log.o: cc ../drivers/debug/log/src/dfx_log.c + source_file_part = dfx_log.c + source_name_part = dfx_log +build obj/drivers/debug/log/src/dfx_log_proc.o: cc ../drivers/debug/log/src/dfx_log_proc.c + source_file_part = dfx_log_proc.c + source_name_part = dfx_log_proc +build obj/drivers/debug/log/src/event.o: cc ../drivers/debug/log/src/event.c + source_file_part = event.c + source_name_part = event +build obj/drivers/debug/log/src/ext_command.o: cc ../drivers/debug/log/src/ext_command.c + source_file_part = ext_command.c + source_name_part = ext_command +build obj/drivers/debug/src/debug.o: cc ../drivers/debug/src/debug.c + source_file_part = debug.c + source_name_part = debug +build obj/drivers/dma/src/dma.o: cc ../drivers/dma/src/dma.c + source_file_part = dma.c + source_name_part = dma +build obj/drivers/dma/src/dma_ex.o: cc ../drivers/dma/src/dma_ex.c + source_file_part = dma_ex.c + source_name_part = dma_ex +build obj/drivers/flash/src/flash.o: cc ../drivers/flash/src/flash.c + source_file_part = flash.c + source_name_part = flash +build obj/drivers/gpio/src/gpio.o: cc ../drivers/gpio/src/gpio.c + source_file_part = gpio.c + source_name_part = gpio +build obj/drivers/gpt/src/gpt.o: cc ../drivers/gpt/src/gpt.c + source_file_part = gpt.c + source_name_part = gpt +build obj/drivers/gpt/src/gpt_ex.o: cc ../drivers/gpt/src/gpt_ex.c + source_file_part = gpt_ex.c + source_name_part = gpt_ex +build obj/drivers/i2c/src/i2c.o: cc ../drivers/i2c/src/i2c.c + source_file_part = i2c.c + source_name_part = i2c +build obj/drivers/i2c/src/i2c_ex.o: cc ../drivers/i2c/src/i2c_ex.c + source_file_part = i2c_ex.c + source_name_part = i2c_ex +build obj/drivers/iocmg/src/iocmg.o: cc ../drivers/iocmg/src/iocmg.c + source_file_part = iocmg.c + source_name_part = iocmg +build obj/drivers/iwdg/src/iwdg.o: cc ../drivers/iwdg/src/iwdg.c + source_file_part = iwdg.c + source_name_part = iwdg +build obj/drivers/iwdg/src/iwdg_ex.o: cc ../drivers/iwdg/src/iwdg_ex.c + source_file_part = iwdg_ex.c + source_name_part = iwdg_ex +build obj/drivers/pga/src/pga.o: cc ../drivers/pga/src/pga.c + source_file_part = pga.c + source_name_part = pga +build obj/drivers/pmc/src/pmc.o: cc ../drivers/pmc/src/pmc.c + source_file_part = pmc.c + source_name_part = pmc +build obj/drivers/qdm/src/qdm.o: cc ../drivers/qdm/src/qdm.c + source_file_part = qdm.c + source_name_part = qdm +build obj/drivers/spi/src/spi.o: cc ../drivers/spi/src/spi.c + source_file_part = spi.c + source_name_part = spi +build obj/drivers/spi/src/spi_ex.o: cc ../drivers/spi/src/spi_ex.c + source_file_part = spi_ex.c + source_name_part = spi_ex +build obj/drivers/timer/src/timer.o: cc ../drivers/timer/src/timer.c + source_file_part = timer.c + source_name_part = timer +build obj/drivers/timer/src/timer_ex.o: cc ../drivers/timer/src/timer_ex.c + source_file_part = timer_ex.c + source_name_part = timer_ex +build obj/drivers/tsensor/src/tsensor.o: cc ../drivers/tsensor/src/tsensor.c + source_file_part = tsensor.c + source_name_part = tsensor +build obj/drivers/uart/src/uart.o: cc ../drivers/uart/src/uart.c + source_file_part = uart.c + source_name_part = uart +build obj/drivers/uart/src/uart_ex.o: cc ../drivers/uart/src/uart_ex.c + source_file_part = uart_ex.c + source_name_part = uart_ex +build obj/drivers/wwdg/src/wwdg.o: cc ../drivers/wwdg/src/wwdg.c + source_file_part = wwdg.c + source_name_part = wwdg +build obj/drivers/wwdg/src/wwdg_ex.o: cc ../drivers/wwdg/src/wwdg_ex.c + source_file_part = wwdg_ex.c + source_name_part = wwdg_ex +build obj/middleware/control_library/adc_calibra/mcs_adcCalibr.o: cc ../middleware/control_library/adc_calibra/mcs_adcCalibr.c + source_file_part = mcs_adcCalibr.c + source_name_part = mcs_adcCalibr +build obj/middleware/control_library/brake/mcs_brake.o: cc ../middleware/control_library/brake/mcs_brake.c + source_file_part = mcs_brake.c + source_name_part = mcs_brake +build obj/middleware/control_library/filter/mcs_filter.o: cc ../middleware/control_library/filter/mcs_filter.c + source_file_part = mcs_filter.c + source_name_part = mcs_filter +build obj/middleware/control_library/filter/mcs_lpfRk4.o: cc ../middleware/control_library/filter/mcs_lpfRk4.c + source_file_part = mcs_lpfRk4.c + source_name_part = mcs_lpfRk4 +build obj/middleware/control_library/filter/mcs_pll.o: cc ../middleware/control_library/filter/mcs_pll.c + source_file_part = mcs_pll.c + source_name_part = mcs_pll +build obj/middleware/control_library/foc_loop_ctrl/mcs_curr_ctrl.o: cc ../middleware/control_library/foc_loop_ctrl/mcs_curr_ctrl.c + source_file_part = mcs_curr_ctrl.c + source_name_part = mcs_curr_ctrl +build obj/middleware/control_library/foc_loop_ctrl/mcs_curr_ff.o: cc ../middleware/control_library/foc_loop_ctrl/mcs_curr_ff.c + source_file_part = mcs_curr_ff.c + source_name_part = mcs_curr_ff +build obj/middleware/control_library/foc_loop_ctrl/mcs_fw_ctrl.o: cc ../middleware/control_library/foc_loop_ctrl/mcs_fw_ctrl.c + source_file_part = mcs_fw_ctrl.c + source_name_part = mcs_fw_ctrl +build obj/middleware/control_library/foc_loop_ctrl/mcs_if_ctrl.o: cc ../middleware/control_library/foc_loop_ctrl/mcs_if_ctrl.c + source_file_part = mcs_if_ctrl.c + source_name_part = mcs_if_ctrl +build obj/middleware/control_library/foc_loop_ctrl/mcs_pos_ctrl.o: cc ../middleware/control_library/foc_loop_ctrl/mcs_pos_ctrl.c + source_file_part = mcs_pos_ctrl.c + source_name_part = mcs_pos_ctrl +build obj/middleware/control_library/foc_loop_ctrl/mcs_spd_ctrl.o: cc ../middleware/control_library/foc_loop_ctrl/mcs_spd_ctrl.c + source_file_part = mcs_spd_ctrl.c + source_name_part = mcs_spd_ctrl +build obj/middleware/control_library/foc_loop_ctrl/mcs_startup.o: cc ../middleware/control_library/foc_loop_ctrl/mcs_startup.c + source_file_part = mcs_startup.c + source_name_part = mcs_startup +build obj/middleware/control_library/math/mcs_math.o: cc ../middleware/control_library/math/mcs_math.c + source_file_part = mcs_math.c + source_name_part = mcs_math +build obj/middleware/control_library/modulation/mcs_r1_svpwm.o: cc ../middleware/control_library/modulation/mcs_r1_svpwm.c + source_file_part = mcs_r1_svpwm.c + source_name_part = mcs_r1_svpwm +build obj/middleware/control_library/modulation/mcs_svpwm.o: cc ../middleware/control_library/modulation/mcs_svpwm.c + source_file_part = mcs_svpwm.c + source_name_part = mcs_svpwm +build obj/middleware/control_library/observer/mcs_fosmo.o: cc ../middleware/control_library/observer/mcs_fosmo.c + source_file_part = mcs_fosmo.c + source_name_part = mcs_fosmo +build obj/middleware/control_library/pfc/pfc_curr_ctrl.o: cc ../middleware/control_library/pfc/pfc_curr_ctrl.c + source_file_part = pfc_curr_ctrl.c + source_name_part = pfc_curr_ctrl +build obj/middleware/control_library/pfc/pfc_volt_ctrl.o: cc ../middleware/control_library/pfc/pfc_volt_ctrl.c + source_file_part = pfc_volt_ctrl.c + source_name_part = pfc_volt_ctrl +build obj/middleware/control_library/pid_controller/mcs_pid_ctrl.o: cc ../middleware/control_library/pid_controller/mcs_pid_ctrl.c + source_file_part = mcs_pid_ctrl.c + source_name_part = mcs_pid_ctrl +build obj/middleware/control_library/power/mcs_power_mgmt.o: cc ../middleware/control_library/power/mcs_power_mgmt.c + source_file_part = mcs_power_mgmt.c + source_name_part = mcs_power_mgmt +build obj/middleware/control_library/protection/mcs_openphs_det.o: cc ../middleware/control_library/protection/mcs_openphs_det.c + source_file_part = mcs_openphs_det.c + source_name_part = mcs_openphs_det +build obj/middleware/control_library/protection/mcs_stall_det.o: cc ../middleware/control_library/protection/mcs_stall_det.c + source_file_part = mcs_stall_det.c + source_name_part = mcs_stall_det +build obj/middleware/control_library/protection/mcs_unbalance_det.o: cc ../middleware/control_library/protection/mcs_unbalance_det.c + source_file_part = mcs_unbalance_det.c + source_name_part = mcs_unbalance_det +build obj/middleware/control_library/ramp/mcs_ramp_mgmt.o: cc ../middleware/control_library/ramp/mcs_ramp_mgmt.c + source_file_part = mcs_ramp_mgmt.c + source_name_part = mcs_ramp_mgmt +build obj/middleware/control_library/utilities/mcs_mtr_param.o: cc ../middleware/control_library/utilities/mcs_mtr_param.c + source_file_part = mcs_mtr_param.c + source_name_part = mcs_mtr_param +build obj/middleware/control_library/vf/mcs_vf_ctrl.o: cc ../middleware/control_library/vf/mcs_vf_ctrl.c + source_file_part = mcs_vf_ctrl.c + source_name_part = mcs_vf_ctrl +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/fscanf_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/fscanf_s.c + source_file_part = fscanf_s.c + source_name_part = fscanf_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/fwscanf_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/fwscanf_s.c + source_file_part = fwscanf_s.c + source_name_part = fwscanf_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/gets_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/gets_s.c + source_file_part = gets_s.c + source_name_part = gets_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/memcpy_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/memcpy_s.c + source_file_part = memcpy_s.c + source_name_part = memcpy_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/memmove_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/memmove_s.c + source_file_part = memmove_s.c + source_name_part = memmove_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/memset_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/memset_s.c + source_file_part = memset_s.c + source_name_part = memset_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/scanf_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/scanf_s.c + source_file_part = scanf_s.c + source_name_part = scanf_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/securecutil.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/securecutil.c + source_file_part = securecutil.c + source_name_part = securecutil +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_a.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_a.c + source_file_part = secureinput_a.c + source_name_part = secureinput_a +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_w.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_w.c + source_file_part = secureinput_w.c + source_name_part = secureinput_w +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_a.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_a.c + source_file_part = secureprintoutput_a.c + source_name_part = secureprintoutput_a +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_w.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_w.c + source_file_part = secureprintoutput_w.c + source_name_part = secureprintoutput_w +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/snprintf_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/snprintf_s.c + source_file_part = snprintf_s.c + source_name_part = snprintf_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/sprintf_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/sprintf_s.c + source_file_part = sprintf_s.c + source_name_part = sprintf_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/sscanf_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/sscanf_s.c + source_file_part = sscanf_s.c + source_name_part = sscanf_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/strcat_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/strcat_s.c + source_file_part = strcat_s.c + source_name_part = strcat_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/strcpy_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/strcpy_s.c + source_file_part = strcpy_s.c + source_name_part = strcpy_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/strncat_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/strncat_s.c + source_file_part = strncat_s.c + source_name_part = strncat_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/strncpy_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/strncpy_s.c + source_file_part = strncpy_s.c + source_name_part = strncpy_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/strtok_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/strtok_s.c + source_file_part = strtok_s.c + source_name_part = strtok_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/swprintf_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/swprintf_s.c + source_file_part = swprintf_s.c + source_name_part = swprintf_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/swscanf_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/swscanf_s.c + source_file_part = swscanf_s.c + source_name_part = swscanf_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vfscanf_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/vfscanf_s.c + source_file_part = vfscanf_s.c + source_name_part = vfscanf_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vfwscanf_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/vfwscanf_s.c + source_file_part = vfwscanf_s.c + source_name_part = vfwscanf_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vscanf_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/vscanf_s.c + source_file_part = vscanf_s.c + source_name_part = vscanf_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vsnprintf_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/vsnprintf_s.c + source_file_part = vsnprintf_s.c + source_name_part = vsnprintf_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vsprintf_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/vsprintf_s.c + source_file_part = vsprintf_s.c + source_name_part = vsprintf_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vsscanf_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/vsscanf_s.c + source_file_part = vsscanf_s.c + source_name_part = vsscanf_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vswprintf_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/vswprintf_s.c + source_file_part = vswprintf_s.c + source_name_part = vswprintf_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vswscanf_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/vswscanf_s.c + source_file_part = vswscanf_s.c + source_name_part = vswscanf_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vwscanf_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/vwscanf_s.c + source_file_part = vwscanf_s.c + source_name_part = vwscanf_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wcscat_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/wcscat_s.c + source_file_part = wcscat_s.c + source_name_part = wcscat_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wcscpy_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/wcscpy_s.c + source_file_part = wcscpy_s.c + source_name_part = wcscpy_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncat_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncat_s.c + source_file_part = wcsncat_s.c + source_name_part = wcsncat_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncpy_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncpy_s.c + source_file_part = wcsncpy_s.c + source_name_part = wcsncpy_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wcstok_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/wcstok_s.c + source_file_part = wcstok_s.c + source_name_part = wcstok_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wmemcpy_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/wmemcpy_s.c + source_file_part = wmemcpy_s.c + source_name_part = wmemcpy_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wmemmove_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/wmemmove_s.c + source_file_part = wmemmove_s.c + source_name_part = wmemmove_s +build obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wscanf_s.o: cc ../middleware/hisilicon/libboundscheck_v1.1.16/src/wscanf_s.c + source_file_part = wscanf_s.c + source_name_part = wscanf_s +build obj/user/main.o: cc ../user/main.c + source_file_part = main.c + source_name_part = main +build obj/user/PAJ7620U2.o: cc ../user/PAJ7620U2.c + source_file_part = PAJ7620U2.c + source_name_part = PAJ7620U2 +build obj/user/generatecode/system_init.o: cc ../user/generatecode/system_init.c + source_file_part = system_init.c + source_name_part = system_init + +build ./bin/target.elf: link obj/chip/3061m/startup.o obj/chip/3061m/chipinit/chipinit.o obj/chip/3061m/chipinit/anatrim/anatrim.o obj/chip/3061m/chipinit/anavrefinit/anavrefinit.o obj/chip/3061m/chipinit/crginit/crginit.o obj/chip/3061m/chipinit/flashinit/flashinit.o obj/chip/3061m/chipinit/systickinit/systickinit.o obj/chip/3061m/fotp/fotp_info_read.o obj/chip/3061m/ip_crg/ip_crg_common.o obj/drivers/acmp/src/acmp.o obj/drivers/acmp/src/acmp_ex.o obj/drivers/adc/src/adc.o obj/drivers/adc/src/adc_ex.o obj/drivers/apt/src/apt.o obj/drivers/base/src/assert.o obj/drivers/base/src/base_math.o obj/drivers/base/src/clock.o obj/drivers/base/src/generalfunc.o obj/drivers/base/src/interrupt.o obj/drivers/base/src/lock.o obj/drivers/base/src/reset.o obj/drivers/can/src/can.o obj/drivers/capm/src/capm.o obj/drivers/cfd/src/cfd.o obj/drivers/cmm/src/cmm.o obj/drivers/crc/src/crc.o obj/drivers/crg/src/crg.o obj/drivers/dac/src/dac.o obj/drivers/debug/log/src/app_command.o obj/drivers/debug/log/src/cmd.o obj/drivers/debug/log/src/cmd_common.o obj/drivers/debug/log/src/config.o obj/drivers/debug/log/src/console.o obj/drivers/debug/log/src/dfx_debug.o obj/drivers/debug/log/src/dfx_log.o obj/drivers/debug/log/src/dfx_log_proc.o obj/drivers/debug/log/src/event.o obj/drivers/debug/log/src/ext_command.o obj/drivers/debug/src/debug.o obj/drivers/dma/src/dma.o obj/drivers/dma/src/dma_ex.o obj/drivers/flash/src/flash.o obj/drivers/gpio/src/gpio.o obj/drivers/gpt/src/gpt.o obj/drivers/gpt/src/gpt_ex.o obj/drivers/i2c/src/i2c.o obj/drivers/i2c/src/i2c_ex.o obj/drivers/iocmg/src/iocmg.o obj/drivers/iwdg/src/iwdg.o obj/drivers/iwdg/src/iwdg_ex.o obj/drivers/pga/src/pga.o obj/drivers/pmc/src/pmc.o obj/drivers/qdm/src/qdm.o obj/drivers/spi/src/spi.o obj/drivers/spi/src/spi_ex.o obj/drivers/timer/src/timer.o obj/drivers/timer/src/timer_ex.o obj/drivers/tsensor/src/tsensor.o obj/drivers/uart/src/uart.o obj/drivers/uart/src/uart_ex.o obj/drivers/wwdg/src/wwdg.o obj/drivers/wwdg/src/wwdg_ex.o obj/middleware/control_library/adc_calibra/mcs_adcCalibr.o obj/middleware/control_library/brake/mcs_brake.o obj/middleware/control_library/filter/mcs_filter.o obj/middleware/control_library/filter/mcs_lpfRk4.o obj/middleware/control_library/filter/mcs_pll.o obj/middleware/control_library/foc_loop_ctrl/mcs_curr_ctrl.o obj/middleware/control_library/foc_loop_ctrl/mcs_curr_ff.o obj/middleware/control_library/foc_loop_ctrl/mcs_fw_ctrl.o obj/middleware/control_library/foc_loop_ctrl/mcs_if_ctrl.o obj/middleware/control_library/foc_loop_ctrl/mcs_pos_ctrl.o obj/middleware/control_library/foc_loop_ctrl/mcs_spd_ctrl.o obj/middleware/control_library/foc_loop_ctrl/mcs_startup.o obj/middleware/control_library/math/mcs_math.o obj/middleware/control_library/modulation/mcs_r1_svpwm.o obj/middleware/control_library/modulation/mcs_svpwm.o obj/middleware/control_library/observer/mcs_fosmo.o obj/middleware/control_library/pfc/pfc_curr_ctrl.o obj/middleware/control_library/pfc/pfc_volt_ctrl.o obj/middleware/control_library/pid_controller/mcs_pid_ctrl.o obj/middleware/control_library/power/mcs_power_mgmt.o obj/middleware/control_library/protection/mcs_openphs_det.o obj/middleware/control_library/protection/mcs_stall_det.o obj/middleware/control_library/protection/mcs_unbalance_det.o obj/middleware/control_library/ramp/mcs_ramp_mgmt.o obj/middleware/control_library/utilities/mcs_mtr_param.o obj/middleware/control_library/vf/mcs_vf_ctrl.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/fscanf_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/fwscanf_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/gets_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/memcpy_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/memmove_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/memset_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/scanf_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/securecutil.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_a.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_w.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_a.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_w.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/snprintf_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/sprintf_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/sscanf_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/strcat_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/strcpy_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/strncat_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/strncpy_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/strtok_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/swprintf_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/swscanf_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vfscanf_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vfwscanf_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vscanf_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vsnprintf_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vsprintf_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vsscanf_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vswprintf_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vswscanf_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vwscanf_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wcscat_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wcscpy_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncat_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncpy_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wcstok_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wmemcpy_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wmemmove_s.o obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wscanf_s.o obj/user/main.o obj/user/PAJ7620U2.o obj/user/generatecode/system_init.o + ldflags = -Wl,-Map,bin/target.map -Wl,--enjal16 -Wl,--gc-section -Wl,--cjal-relax -Wl,--dslf -Wl,--jal-transfer -nostdlib -static -lgcc -lc -Wl,-Bsymbolic -rdynamic -Wl,--no-undefined -T..\chip\3061m\flash.lds -Wl,--whole-archive -L..\middleware\thirdparty\sysroot\lib -lmcs_smo_4th -lnostask -Wl,--no-whole-archive + libs = + frameworks = + swiftmodules = + output_extension = + output_dir = . diff --git a/vendor/xinlingyu_92_3061M/Project/out/obj/chip/3061m/chipinit/anatrim/anatrim.o b/vendor/xinlingyu_92_3061M/Project/out/obj/chip/3061m/chipinit/anatrim/anatrim.o new file mode 100644 index 0000000000000000000000000000000000000000..bf4609dc3d9d3a6de9c54c71a421d68b1467906e Binary files /dev/null and b/vendor/xinlingyu_92_3061M/Project/out/obj/chip/3061m/chipinit/anatrim/anatrim.o differ diff --git a/vendor/xinlingyu_92_3061M/Project/out/obj/chip/3061m/chipinit/anavrefinit/anavrefinit.o b/vendor/xinlingyu_92_3061M/Project/out/obj/chip/3061m/chipinit/anavrefinit/anavrefinit.o new file mode 100644 index 0000000000000000000000000000000000000000..6f7e38dfc8456b65f4d4b44cf9505208dcc96d78 Binary files /dev/null and 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a/vendor/xinlingyu_92_3061M/Project/out/obj/user/main.o b/vendor/xinlingyu_92_3061M/Project/out/obj/user/main.o new file mode 100644 index 0000000000000000000000000000000000000000..44ee61b5d1b4692a30334aceae78c7c0ec340d10 Binary files /dev/null and b/vendor/xinlingyu_92_3061M/Project/out/obj/user/main.o differ diff --git a/vendor/xinlingyu_92_3061M/Project/out/toolchain.ninja b/vendor/xinlingyu_92_3061M/Project/out/toolchain.ninja new file mode 100644 index 0000000000000000000000000000000000000000..048af6ce174e0d8ff44d96230eaca7290bdc606a --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/out/toolchain.ninja @@ -0,0 +1,38 @@ +rule copy + command = cp -afd ${in} ${out} + description = COPY ${in} ${out} +rule stamp + command = cmd /c type nul > "${out}" + description = STAMP ${out} +rule cxx + command = riscv32-linux-musl-g++ -MMD -MF ${out}.d ${defines} ${include_dirs} ${cflags} -c ${in} -o ${out} + description = CXX ${out} + depfile = ${out}.d + deps = gcc +rule cc + command = riscv32-linux-musl-gcc -MMD -MF ${out}.d ${defines} ${include_dirs} ${cflags} -c ${in} -o ${out} + description = cross compiler ${out} + depfile = ${out}.d + deps = gcc +rule link + command = riscv32-linux-musl-gcc -Wl,--start-group ${ldflags} -Wl,--whole-archive @${output_dir}/bin/${target_output_name}${output_extension}.rsp -Wl,--no-whole-archive ${libs} -Wl,--end-group -o ${output_dir}/bin/${target_output_name}${output_extension} + description = LINK ${output_dir}/bin/${target_output_name}${output_extension} + rspfile = ${output_dir}/bin/${target_output_name}${output_extension}.rsp + rspfile_content = ${in} +rule solink + command = riscv32-linux-musl-gcc -shared -Wl,--start-group ${ldflags} ${in} ${libs} -Wl,--end-group -o ${output_dir}/${target_output_name}${output_extension} + description = SOLINK ${output_dir}/${target_output_name}${output_extension} + rspfile = ${out}.rsp + rspfile_content = ${in} +rule alink + command = riscv32-linux-musl-ar cr ${out} @"${out}.rsp" + description = AR ${out} + rspfile = ${out}.rsp + rspfile_content = ${in} +rule asm + command = riscv32-linux-musl-gcc -MMD -MF ${out}.d ${defines} ${include_dirs} ${cflags} ${asmflags} -c ${in} -o ${out} + description = cross compiler ${out} + depfile = ${out}.d + deps = gcc + +subninja obj/build/target.elf.ninja diff --git a/vendor/xinlingyu_92_3061M/Project/user/PAJ7620U2.c b/vendor/xinlingyu_92_3061M/Project/user/PAJ7620U2.c new file mode 100644 index 0000000000000000000000000000000000000000..e34325862f47a417b860b4a07318776f9c12eec3 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/user/PAJ7620U2.c @@ -0,0 +1,157 @@ +#include "PAJ7620U2.h" +#include "main.h" +#include "ioconfig.h" +#include "iocmg_ip.h" + +extern unsigned char g_step_motor_flag; + +const unsigned char Init_REG_Table[51][2] = +{ + { 0xEF, 0x00 }, + { 0x37, 0x07 }, + { 0x38, 0x17 }, + { 0x39, 0x06 }, + { 0x41, 0x00 }, + { 0x42, 0x00 }, + { 0x46, 0x2D }, + { 0x47, 0x0F }, + { 0x48, 0x3C }, + { 0x49, 0x00 }, + { 0x4A, 0x1E }, + { 0x4C, 0x20 }, + { 0x51, 0x10 }, + { 0x5E, 0x10 }, + { 0x60, 0x27 }, + { 0x80, 0x42 }, + { 0x81, 0x44 }, + { 0x82, 0x04 }, + { 0x8B, 0x01 }, + { 0x90, 0x06 }, + { 0x95, 0x0A }, + { 0x96, 0x0C }, + { 0x97, 0x05 }, + { 0x9A, 0x14 }, + { 0x9C, 0x3F }, + { 0xA5, 0x19 }, + { 0xCC, 0x19 }, + { 0xCD, 0x0B }, + { 0xCE, 0x13 }, + { 0xCF, 0x64 }, + { 0xD0, 0x21 }, + { 0xEF, 0x01 }, + { 0x02, 0x0F }, + { 0x03, 0x10 }, + { 0x04, 0x02 }, + { 0x25, 0x01 }, + { 0x27, 0x39 }, + { 0x28, 0x7F }, + { 0x29, 0x08 }, + { 0x3E, 0xFF }, + { 0x5E, 0x3D }, + { 0x65, 0x96 }, + { 0x67, 0x97 }, + { 0x69, 0xCD }, + { 0x6A, 0x01 }, + { 0x6D, 0x2C }, + { 0x6E, 0x01 }, + { 0x72, 0x01 }, + { 0x73, 0x35 }, + { 0x74, 0x00 }, + { 0x77, 0x01 }, +}; + +const unsigned char Init_Gesture_Table[30][2] = +{ + { 0xEF, 0x00 }, + { 0x41, 0x00 }, + { 0x42, 0x00 }, + { 0xEF, 0x00 }, + { 0x48, 0x3C }, + { 0x49, 0x00 }, + { 0x51, 0x10 }, + { 0x83, 0x20 }, + { 0x9F, 0xF9 }, + { 0xEF, 0x01 }, + { 0x01, 0x1E }, + { 0x02, 0x0F }, + { 0x03, 0x10 }, + { 0x04, 0x02 }, + { 0x41, 0x40 }, + { 0x43, 0x30 }, + { 0x65, 0x96 }, + { 0x66, 0x00 }, + { 0x67, 0x97 }, + { 0x68, 0x01 }, + { 0x69, 0xCD }, + { 0x6A, 0x01 }, + { 0x6B, 0xB0 }, + { 0x6C, 0x04 }, + { 0x6D, 0x2C }, + { 0x6E, 0x01 }, + { 0x74, 0x00 }, + { 0xEF, 0x00 }, + { 0x41, 0xFF }, + { 0x42, 0x01 }, +}; + +unsigned char g_i2c0_buff[2]; + +void PAJ7620U2_I2C_WriteData(unsigned char Address, unsigned char Data) +{ + g_i2c0_buff[0] = Address; + g_i2c0_buff[1] = Data; + + HAL_I2C_MasterWriteBlocking(&g_i2c0, 0xE6, g_i2c0_buff, 2, 10000); +} + +unsigned char PAJ7620U2_I2C_ReadData(unsigned char Address) +{ + g_i2c0_buff[0] = Address; + + HAL_I2C_MasterWriteBlocking(&g_i2c0, 0xE6, &g_i2c0_buff, 1, 10000); + HAL_I2C_MasterReadBlocking(&g_i2c0, 0xE7, &g_i2c0_buff, 1, 10000); + + return (g_i2c0_buff[0]); +} + +void PAJ7620U2_Init(void) +{ + if (PAJ7620U2_I2C_ReadData(0x00) == 0x20) + { + for (unsigned char i = 0; i < 51; i++) + { + PAJ7620U2_I2C_WriteData(Init_REG_Table[i][0], Init_REG_Table[i][1]); + } + + for (unsigned char i = 0; i < 30; i++) + { + PAJ7620U2_I2C_WriteData(Init_Gesture_Table[i][0], Init_Gesture_Table[i][1]); + } + + HAL_UART_WriteBlocking(&g_uart0, "\r\nPAJ7620U2_Init OK!", 20, 1000); + } + else + { + HAL_UART_WriteBlocking(&g_uart0, "\r\nPAJ7620U2_Init Failed!", 24, 1000); + } +} + +void PAJ7620U2_Handler(void) +{ + unsigned char Data = PAJ7620U2_I2C_ReadData(0x43); + + switch (Data) + { + case 0x01: HAL_UART_WriteBlocking(&g_uart0, "\r\nUp", 4, 1000); g_step_motor_flag = 1; break; + case 0x02: HAL_UART_WriteBlocking(&g_uart0, "\r\nDown", 6, 1000); g_step_motor_flag = 0; break; + case 0x04: HAL_UART_WriteBlocking(&g_uart0, "\r\nLeft", 6, 1000); g_step_motor_flag = 1; break; + case 0x08: HAL_UART_WriteBlocking(&g_uart0, "\r\nRight", 7, 1000); g_step_motor_flag = 0; break; + case 0x10: HAL_UART_WriteBlocking(&g_uart0, "\r\nForward", 9, 1000); g_step_motor_flag = 1; break; + case 0x20: HAL_UART_WriteBlocking(&g_uart0, "\r\nBackward", 10, 1000); g_step_motor_flag = 0; break; + case 0x40: HAL_UART_WriteBlocking(&g_uart0, "\r\nClockwise", 11, 1000); break; + case 0x80: HAL_UART_WriteBlocking(&g_uart0, "\r\nAntiClockwise", 15, 1000); break; + default: + break; + } +} + diff --git a/vendor/xinlingyu_92_3061M/Project/user/PAJ7620U2.h b/vendor/xinlingyu_92_3061M/Project/user/PAJ7620U2.h new file mode 100644 index 0000000000000000000000000000000000000000..0a7f638fe153bf9f894a7f0b4f3c9d25c6de5020 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/user/PAJ7620U2.h @@ -0,0 +1,15 @@ +#ifndef __PAJ7620U2_H +#define __PAJ7620U2_H + +#ifdef __cplusplus +extern "C" { +#endif + +void PAJ7620U2_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/vendor/xinlingyu_92_3061M/Project/user/generatecode/feature.h b/vendor/xinlingyu_92_3061M/Project/user/generatecode/feature.h new file mode 100644 index 0000000000000000000000000000000000000000..1e8331dc3060e84d7aeff4e361c01c89a64f344f --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/user/generatecode/feature.h @@ -0,0 +1,119 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file feature.h + * @author MCU Driver Team + * @brief This file contains macro configurations related to the project. This file is generated by the IDE tool. + */ + +#ifndef McuMagicTag_FEATURE_H +#define McuMagicTag_FEATURE_H + +/* Macro definitions --------------------------------------------------------- */ +#define CHIP_3061MNPICA MACRO_ENABLE + +#define MACRO_ENABLE 1 +#define MACRO_DISABLE 0 + +/* Macro switch */ +#define BASE_DEFINE_USE_ASSERT MACRO_ENABLE +#ifndef FLASH_CRC_CONFIG +#define FLASH_CRC_CONFIG +#endif /* #ifndef FLASH_CRC_CONFIG */ +#define BASE_MATH_SINCOS_MIDDLE_TABLE MACRO_ENABLE /**< This macro is used to control the table type when the + BASE_MATH_GetSinCos() queries the table. When the value of + this macro is MACRO_ENABLE, the error value obtained by the + BASE_MATH_GetSinCos() is relatively small, and the return + value of the function may be greater than or less than the + actual value. When the value of this macro is MACRO_DISABLE, + the error value obtained by the BASE_MATH_GetSinCos() is + relatively large. However, in the range [0°, 180°) and + [180°, 360°), the return value of the function is either + greater than or less than the actual value. */ + +#define MCS_PARAM_CHECK MACRO_ENABLE +#define APT_PARAM_CHECK MACRO_ENABLE +#define ADC_PARAM_CHECK MACRO_ENABLE +#define CAPM_PARAM_CHECK MACRO_ENABLE +#define CRG_PARAM_CHECK MACRO_ENABLE +#define I2C_PARAM_CHECK MACRO_ENABLE +#define UART_PARAM_CHECK MACRO_ENABLE +#define SPI_PARAM_CHECK MACRO_ENABLE +#define TIMER_PARAM_CHECK MACRO_ENABLE +#define IWDG_PARAM_CHECK MACRO_ENABLE +#define WWDG_PARAM_CHECK MACRO_ENABLE +#define GPIO_PARAM_CHECK MACRO_ENABLE +#define GPT_PARAM_CHECK MACRO_ENABLE +#define DMA_PARAM_CHECK MACRO_ENABLE +#define CRC_PARAM_CHECK MACRO_ENABLE +#define CFD_PARAM_CHECK MACRO_ENABLE +#define CMM_PARAM_CHECK MACRO_ENABLE +#define CAN_PARAM_CHECK MACRO_ENABLE +#define FLASH_PARAM_CHECK MACRO_ENABLE +#define PMC_PARAM_CHECK MACRO_ENABLE +#define ACMP_PARAM_CHECK MACRO_ENABLE +#define DAC_PARAM_CHECK MACRO_ENABLE +#define PGA_PARAM_CHECK MACRO_ENABLE +#define IOCMG_PARAM_CHECK MACRO_ENABLE +#define QDM_PARAM_CHECK MACRO_ENABLE + +/* Peripheral module macro switch--------------------------------------------- */ +#define BOARD_DIM_NUM 1 /**< Number of dimming handle arrays. */ + +#define BOARD_KEY_NUM 10 /**< Number of key handle arrays. */ +#define BOARD_KEY_PRESS_ON GPIO_HIGH_LEVEL /**< GPIO status corresponding to long press valid. */ +#define BOARD_KEY_PRESS_OFF GPIO_LOW_LEVEL /**< GPIO status corresponding to short press valid. */ + +#define BOARD_LED_SEG_NUM 4 /**< Number of segments. */ +#define BOARD_LED_SEGMENT_ON GPIO_HIGH_LEVEL /**< GPIO level status corresponding to valid segments. */ +#define BOARD_LED_SEGMENT_OFF GPIO_LOW_LEVEL /**< GPIO level status corresponding to invalid segments. */ + +#define BOARD_MKEY_SCHEME_NUMBER BOARD_MKEY_SCHEME_NUMBER_ONE /**< Define the scheme to be adopted. */ +#define BOARD_MKEY_OUT_NUM 4 /**< Number of GPIO pins used as output during scanning. */ +#define BOARD_MKEY_IN_NUM 4 /**< Number of GPIO pins used as input during scanning. */ +#define BOARD_MKEY_OUT_PIN_VALID GPIO_LOW_LEVEL /**< GPIO level status corresponding to the valid \ + status of the output GPIO in the key matrix. */ +#define BOARD_MKEY_OUT_PIN_INVALID GPIO_HIGH_LEVEL /**< GPIO level status corresponding to the \ + invalid status of the output GPIO in the key matrix. */ +#define BOARD_MKEY_IN_PIN_VALID GPIO_LOW_LEVEL /**< Indicates the GPIO level corresponding to the \ + valid status of the input GPIO in the key matrix. */ +#define BOARD_MKEY_IN_PIN_INVALID GPIO_HIGH_LEVEL /**< Indicates the GPIO level corresponding to the \ + invalid status of the input GPIO in the key matrix. */ + +#define BOARD_PULSES_NUM 2 /**< Number of pulse handles. */ + +#define BASE_DEFINE_SLIPAVERAGE_NUM 2 /**< Sliding average array length. */ + +#define LISTNODE_MAX 20 + +#define BASE_DEFINE_DMA_QUICKSTART + +#define XTRAIL_FREQ 30000000U + +#define DBG_USE_NO_PRINTF 0U +#define DBG_USE_UART_PRINTF 1U + +#define DBG_PRINTF_USE DBG_USE_UART_PRINTF +#if (DBG_PRINTF_USE == DBG_USE_UART_PRINTF) +#define DBG_PRINTF_UART_PORT UART0 +#endif + +/* USER CODE BEGIN 0 */ +/* USER CODE 区域内代码不会被覆盖，区域外会被生成的默认代码覆盖（其余USER CODE 区域同理） */ +/* USER CODE END 0 */ + +#endif /* McuMagicTag_FEATURE_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/user/generatecode/main.h b/vendor/xinlingyu_92_3061M/Project/user/generatecode/main.h new file mode 100644 index 0000000000000000000000000000000000000000..d593542b6a7fd92778d08f64f6970f4b721b247b --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/user/generatecode/main.h @@ -0,0 +1,80 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file main.h + * @author MCU Driver Team + * @brief This file contains driver init functions. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_SYSTEM_INIT_H +#define McuMagicTag_SYSTEM_INIT_H + +#include "uart.h" +#include "uart_ex.h" +#include "i2c.h" +#include "i2c_ex.h" +#include "gpio.h" +#include "timer.h" +#include "timer_ex.h" +#include "crg.h" +#include "iocmg.h" + +#define IO_SPEED_FAST 0x00U +#define IO_SPEED_SLOW 0x01U + +#define IO_DRV_LEVEL4 0x00U +#define IO_DRV_LEVEL3 0x01U +#define IO_DRV_LEVEL2 0x02U +#define IO_DRV_LEVEL1 0x03U + +#define XTAL_DRV_LEVEL4 0x03U +#define XTAL_DRV_LEVEL3 0x02U +#define XTAL_DRV_LEVEL2 0x01U +#define XTAL_DRV_LEVEL1 0x00U + +extern TIMER_Handle g_timer0; +extern TIMER_Handle g_timer1; +extern UART_Handle g_uart0; +extern UART_Handle g_uart2; +extern I2C_Handle g_i2c0; + +extern GPIO_Handle g_gpio2; +extern GPIO_Handle g_gpio1; +extern GPIO_Handle g_gpio5; +extern GPIO_Handle g_gpio3; + +BASE_StatusType CRG_Config(CRG_CoreClkSelect *coreClkSelect); +void SystemInit(void); + +void UART0ReadInterruptCallback(void *handle); +void UART2ReadInterruptCallback(void *handle); + +void UART0InterruptErrorCallback(void *handle); +void UART2InterruptErrorCallback(void *handle); +void TIMER0_InterruptProcess(void *handle); +void TIMER0_DMAOverFlow_InterruptProcess(void *handle); +void TIMER1_InterruptProcess(void *handle); +void TIMER1_DMAOverFlow_InterruptProcess(void *handle); + +void GPIO2_4_CallbackFunc(void *param); + +/* USER CODE BEGIN 0 */ +/* USER CODE 区域内代码不会被覆盖，区域外会被生成的默认代码覆盖（其余USER CODE 区域同理） */ +/* USER CODE END 0 */ + +#endif /* McuMagicTag_SYSTEM_INIT_H */ \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/user/generatecode/system_init.c b/vendor/xinlingyu_92_3061M/Project/user/generatecode/system_init.c new file mode 100644 index 0000000000000000000000000000000000000000..83b112469a4fbb00c388479b15664351f7c8979d --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/user/generatecode/system_init.c @@ -0,0 +1,374 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file system_init.c + * @author MCU Driver Team + * @brief This file contains driver init functions. + */ + +#include "main.h" +#include "ioconfig.h" +#include "iocmg_ip.h" + +#define UART0_BAND_RATE 115200 +#define UART2_BAND_RATE 921600 + +BASE_StatusType CRG_Config(CRG_CoreClkSelect *coreClkSelect) +{ + CRG_Handle crg; + crg.baseAddress = CRG; + crg.pllRefClkSelect = CRG_PLL_REF_CLK_SELECT_HOSC; + crg.pllPreDiv = CRG_PLL_PREDIV_4; + crg.pllFbDiv = 48; /* PLL Multiplier 48 */ + crg.pllPostDiv = CRG_PLL_POSTDIV_2; + crg.coreClkSelect = CRG_CORE_CLK_SELECT_PLL; + crg.handleEx.pllPostDiv2 = CRG_PLL_POSTDIV2_3; + crg.handleEx.clk1MSelect = CRG_1M_CLK_SELECT_HOSC; + crg.handleEx.clk1MDiv = (25 - 1); /* The 1 MHz freq is equal to the input clock frequency / (clk_1m_div + 1). 25 is the div of the clk_1m in CLOCK. */ + + if (HAL_CRG_Init(&crg) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + *coreClkSelect = crg.coreClkSelect; + return BASE_STATUS_OK; +} + +__weak void GPIO2_4_CallbackFunc(void *param) +{ + GPIO_Handle *handle = (GPIO_Handle *)param; + BASE_FUNC_UNUSED(handle); +} + +static void GPIO_Init(void) +{ + HAL_CRG_IpEnableSet(GPIO2_BASE, IP_CLK_ENABLE); + g_gpio2.baseAddress = GPIO2; + + g_gpio2.pins = GPIO_PIN_3; + HAL_GPIO_Init(&g_gpio2); + HAL_GPIO_SetDirection(&g_gpio2, g_gpio2.pins, GPIO_OUTPUT_MODE); + HAL_GPIO_SetValue(&g_gpio2, g_gpio2.pins, GPIO_HIGH_LEVEL); + HAL_GPIO_SetIrqType(&g_gpio2, g_gpio2.pins, GPIO_INT_TYPE_NONE); + + g_gpio2.pins = GPIO_PIN_4; + HAL_GPIO_Init(&g_gpio2); + HAL_GPIO_SetDirection(&g_gpio2, g_gpio2.pins, GPIO_INPUT_MODE); + HAL_GPIO_SetValue(&g_gpio2, g_gpio2.pins, GPIO_LOW_LEVEL); + HAL_GPIO_SetIrqType(&g_gpio2, g_gpio2.pins, GPIO_INT_TYPE_FALL_EDGE); + + HAL_CRG_IpEnableSet(GPIO1_BASE, IP_CLK_ENABLE); + g_gpio1.baseAddress = GPIO1; + + g_gpio1.pins = GPIO_PIN_0; + HAL_GPIO_Init(&g_gpio1); + HAL_GPIO_SetDirection(&g_gpio1, g_gpio1.pins, GPIO_OUTPUT_MODE); + HAL_GPIO_SetValue(&g_gpio1, g_gpio1.pins, GPIO_HIGH_LEVEL); + HAL_GPIO_SetIrqType(&g_gpio1, g_gpio1.pins, GPIO_INT_TYPE_NONE); + + HAL_CRG_IpEnableSet(GPIO5_BASE, IP_CLK_ENABLE); + g_gpio5.baseAddress = GPIO5; + + g_gpio5.pins = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_1; + HAL_GPIO_Init(&g_gpio5); + HAL_GPIO_SetDirection(&g_gpio5, g_gpio5.pins, GPIO_OUTPUT_MODE); + HAL_GPIO_SetValue(&g_gpio5, g_gpio5.pins, GPIO_HIGH_LEVEL); + HAL_GPIO_SetIrqType(&g_gpio5, g_gpio5.pins, GPIO_INT_TYPE_NONE); + + HAL_CRG_IpEnableSet(GPIO3_BASE, IP_CLK_ENABLE); + g_gpio3.baseAddress = GPIO3; + + g_gpio3.pins = GPIO_PIN_6; + HAL_GPIO_Init(&g_gpio3); + HAL_GPIO_SetDirection(&g_gpio3, g_gpio3.pins, GPIO_OUTPUT_MODE); + HAL_GPIO_SetValue(&g_gpio3, g_gpio3.pins, GPIO_HIGH_LEVEL); + HAL_GPIO_SetIrqType(&g_gpio3, g_gpio3.pins, GPIO_INT_TYPE_NONE); + + HAL_GPIO_RegisterCallBack(&g_gpio2, GPIO_PIN_4, GPIO2_4_CallbackFunc); + IRQ_Register(IRQ_GPIO2, HAL_GPIO_IrqHandler, &g_gpio2); + IRQ_SetPriority(IRQ_GPIO2, 1); /* set gpio1 interrupt priority to 1, 1~15. 1 is priority value */ + IRQ_EnableN(IRQ_GPIO2); /* gpio interrupt enable */ + + return; +} + +static void I2C0_Init(void) +{ + HAL_CRG_IpEnableSet(I2C0_BASE, IP_CLK_ENABLE); /* I2C0 clock enable. */ + g_i2c0.baseAddress = I2C0; + + g_i2c0.functionMode = I2C_MODE_SELECT_MASTER_ONLY; + g_i2c0.addrMode = I2C_7_BITS; + g_i2c0.sdaHoldTime = 10; /* 10 is sda Hold Time */ + g_i2c0.freq = 100000; /* freqence is 100000 */ + g_i2c0.transferBuff = NULL; + g_i2c0.ignoreAckFlag = BASE_CFG_DISABLE; + g_i2c0.handleEx.spikeFilterTime = 0; + g_i2c0.handleEx.sdaDelayTime = 0; + g_i2c0.timeout = 10000; /* 10000 is time out */ + g_i2c0.state = I2C_STATE_RESET; + HAL_I2C_Init(&g_i2c0); +} + +__weak void TIMER0_InterruptProcess(void *handle) +{ + BASE_FUNC_UNUSED(handle); + /* USER CODE BEGIN TIMER0_InterruptProcess */ + /* USER CODE END TIMER0_InterruptProcess */ +} + +static void TIMER0_Init(void) +{ + HAL_CRG_IpEnableSet(TIMER0_BASE, IP_CLK_ENABLE); /* TIMER0 clock enable. */ + unsigned int load = (HAL_CRG_GetIpFreq((void *)TIMER0) / (1u << (TIMERPRESCALER_NO_DIV * 4)) / 1000000u) * 500; + + g_timer0.baseAddress = TIMER0; + g_timer0.load = load - 1; /* Set timer value immediately */ + g_timer0.bgLoad = load - 1; /* Set timer value */ + g_timer0.mode = TIMER_MODE_RUN_PERIODIC; /* Run in period mode */ + g_timer0.prescaler = TIMERPRESCALER_NO_DIV; /* Don't frequency division */ + g_timer0.size = TIMER_SIZE_32BIT; /* 1 for 32bit, 0 for 16bit */ + g_timer0.interruptEn = BASE_CFG_ENABLE; + g_timer0.adcSocReqEnable = BASE_CFG_DISABLE; + g_timer0.dmaReqEnable = BASE_CFG_DISABLE; + HAL_TIMER_Init(&g_timer0); + IRQ_Register(IRQ_TIMER0, HAL_TIMER_IrqHandler, &g_timer0); + + HAL_TIMER_RegisterCallback(&g_timer0, TIMER_PERIOD_FIN, TIMER0_InterruptProcess); + IRQ_SetPriority(IRQ_TIMER0, 1); /* 1 is priority value */ + IRQ_EnableN(IRQ_TIMER0); +} + +__weak void TIMER1_InterruptProcess(void *handle) +{ + BASE_FUNC_UNUSED(handle); + /* USER CODE BEGIN TIMER1_InterruptProcess */ + /* USER CODE END TIMER1_InterruptProcess */ +} + +static void TIMER1_Init(void) +{ + HAL_CRG_IpEnableSet(TIMER1_BASE, IP_CLK_ENABLE); /* TIMER1 clock enable. */ + unsigned int load = (HAL_CRG_GetIpFreq((void *)TIMER1) / (1u << (TIMERPRESCALER_NO_DIV * 4)) / 1000000u) * 500; + + g_timer1.baseAddress = TIMER1; + g_timer1.load = load - 1; /* Set timer value immediately */ + g_timer1.bgLoad = load - 1; /* Set timer value */ + g_timer1.mode = TIMER_MODE_RUN_PERIODIC; /* Run in period mode */ + g_timer1.prescaler = TIMERPRESCALER_NO_DIV; /* Don't frequency division */ + g_timer1.size = TIMER_SIZE_32BIT; /* 1 for 32bit, 0 for 16bit */ + g_timer1.interruptEn = BASE_CFG_ENABLE; + g_timer1.adcSocReqEnable = BASE_CFG_DISABLE; + g_timer1.dmaReqEnable = BASE_CFG_DISABLE; + HAL_TIMER_Init(&g_timer1); + IRQ_Register(IRQ_TIMER1, HAL_TIMER_IrqHandler, &g_timer1); + + HAL_TIMER_RegisterCallback(&g_timer1, TIMER_PERIOD_FIN, TIMER1_InterruptProcess); + IRQ_SetPriority(IRQ_TIMER1, 1); /* 1 is priority value */ + IRQ_EnableN(IRQ_TIMER1); +} + +__weak void UART0InterruptErrorCallback(void *handle) +{ + BASE_FUNC_UNUSED(handle); + /* USER CODE BEGIN UART0_TRNS_IT_ERROR */ + /* USER CODE END UART0_TRNS_IT_ERROR */ +} + +__weak void UART0ReadInterruptCallback(void *handle) +{ + BASE_FUNC_UNUSED(handle); + /* USER CODE BEGIN UART0_READ_IT_FINISH */ + /* USER CODE END UART0_READ_IT_FINISH */ +} + +static void UART0_Init(void) +{ + HAL_CRG_IpEnableSet(UART0_BASE, IP_CLK_ENABLE); /* UART0 clock enable. */ + g_uart0.baseAddress = UART0; + + g_uart0.baudRate = UART0_BAND_RATE; + g_uart0.dataLength = UART_DATALENGTH_8BIT; + g_uart0.stopBits = UART_STOPBITS_ONE; + g_uart0.parity = UART_PARITY_NONE; + g_uart0.txMode = UART_MODE_BLOCKING; + g_uart0.rxMode = UART_MODE_INTERRUPT; + g_uart0.fifoMode = BASE_CFG_DISABLE; + g_uart0.fifoTxThr = UART_FIFODEPTH_SIZE8; + g_uart0.fifoRxThr = UART_FIFODEPTH_SIZE8; + g_uart0.hwFlowCtr = BASE_CFG_DISABLE; + g_uart0.handleEx.overSampleMultiple = UART_OVERSAMPLING_16X; + g_uart0.handleEx.msbFirst = BASE_CFG_DISABLE; + HAL_UART_Init(&g_uart0); + HAL_UART_RegisterCallBack(&g_uart0, UART_TRNS_IT_ERROR, (UART_CallbackType)UART0InterruptErrorCallback); + HAL_UART_RegisterCallBack(&g_uart0, UART_READ_IT_FINISH, (UART_CallbackType)UART0ReadInterruptCallback); + IRQ_Register(IRQ_UART0, HAL_UART_IrqHandler, &g_uart0); + IRQ_SetPriority(IRQ_UART0, 1); /* 1 is priority value */ + IRQ_EnableN(IRQ_UART0); +} + +__weak void UART2InterruptErrorCallback(void *handle) +{ + BASE_FUNC_UNUSED(handle); + /* USER CODE BEGIN UART2_TRNS_IT_ERROR */ + /* USER CODE END UART2_TRNS_IT_ERROR */ +} + +__weak void UART2ReadInterruptCallback(void *handle) +{ + BASE_FUNC_UNUSED(handle); + /* USER CODE BEGIN UART2_READ_IT_FINISH */ + /* USER CODE END UART2_READ_IT_FINISH */ +} + +static void UART2_Init(void) +{ + HAL_CRG_IpEnableSet(UART2_BASE, IP_CLK_ENABLE); /* UART2 clock enable. */ + g_uart2.baseAddress = UART2; + + g_uart2.baudRate = UART2_BAND_RATE; + g_uart2.dataLength = UART_DATALENGTH_8BIT; + g_uart2.stopBits = UART_STOPBITS_ONE; + g_uart2.parity = UART_PARITY_NONE; + g_uart2.txMode = UART_MODE_BLOCKING; + g_uart2.rxMode = UART_MODE_INTERRUPT; + g_uart2.fifoMode = BASE_CFG_DISABLE; + g_uart2.fifoTxThr = UART_FIFODEPTH_SIZE8; + g_uart2.fifoRxThr = UART_FIFODEPTH_SIZE8; + g_uart2.hwFlowCtr = BASE_CFG_DISABLE; + g_uart2.handleEx.overSampleMultiple = UART_OVERSAMPLING_16X; + g_uart2.handleEx.msbFirst = BASE_CFG_DISABLE; + HAL_UART_Init(&g_uart2); + HAL_UART_RegisterCallBack(&g_uart2, UART_TRNS_IT_ERROR, (UART_CallbackType)UART2InterruptErrorCallback); + HAL_UART_RegisterCallBack(&g_uart2, UART_READ_IT_FINISH, (UART_CallbackType)UART2ReadInterruptCallback); + IRQ_Register(IRQ_UART2, HAL_UART_IrqHandler, &g_uart2); + IRQ_SetPriority(IRQ_UART2, 1); /* 1 is priority value */ + IRQ_EnableN(IRQ_UART2); +} + +static void IOConfig(void) +{ + /* Config PIN36 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO0_0_AS_JTAG_TCK); /* Check function selection */ + HAL_IOCMG_SetPinPullMode(GPIO0_0_AS_JTAG_TCK, PULL_NONE); /* Pull-up and Pull-down */ + HAL_IOCMG_SetPinSchmidtMode(GPIO0_0_AS_JTAG_TCK, SCHMIDT_DISABLE); /* Schmitt input on/off */ + HAL_IOCMG_SetPinLevelShiftRate(GPIO0_0_AS_JTAG_TCK, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + HAL_IOCMG_SetPinDriveRate(GPIO0_0_AS_JTAG_TCK, DRIVER_RATE_2); /* Output signal edge fast/slow */ + /* Config PIN37 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO0_1_AS_JTAG_TMS); /* Check function selection */ + HAL_IOCMG_SetPinPullMode(GPIO0_1_AS_JTAG_TMS, PULL_NONE); /* Pull-up and Pull-down */ + HAL_IOCMG_SetPinSchmidtMode(GPIO0_1_AS_JTAG_TMS, SCHMIDT_DISABLE); /* Schmitt input on/off */ + HAL_IOCMG_SetPinLevelShiftRate(GPIO0_1_AS_JTAG_TMS, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + HAL_IOCMG_SetPinDriveRate(GPIO0_1_AS_JTAG_TMS, DRIVER_RATE_2); /* Output signal edge fast/slow */ + /* Config PIN35 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO2_3_AS_GPIO2_3); /* Check function selection */ + HAL_IOCMG_SetPinPullMode(GPIO2_3_AS_GPIO2_3, PULL_NONE); /* Pull-up and Pull-down */ + HAL_IOCMG_SetPinSchmidtMode(GPIO2_3_AS_GPIO2_3, SCHMIDT_DISABLE); /* Schmitt input on/off */ + HAL_IOCMG_SetPinLevelShiftRate(GPIO2_3_AS_GPIO2_3, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + HAL_IOCMG_SetPinDriveRate(GPIO2_3_AS_GPIO2_3, DRIVER_RATE_2); /* Output signal edge fast/slow */ + /* Config PIN27 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO1_0_AS_GPIO1_0); /* Check function selection */ + HAL_IOCMG_SetPinPullMode(GPIO1_0_AS_GPIO1_0, PULL_NONE); /* Pull-up and Pull-down */ + HAL_IOCMG_SetPinSchmidtMode(GPIO1_0_AS_GPIO1_0, SCHMIDT_DISABLE); /* Schmitt input on/off */ + HAL_IOCMG_SetPinLevelShiftRate(GPIO1_0_AS_GPIO1_0, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + HAL_IOCMG_SetPinDriveRate(GPIO1_0_AS_GPIO1_0, DRIVER_RATE_2); /* Output signal edge fast/slow */ + /* Config PIN41 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO2_4_AS_GPIO2_4); /* Check function selection */ + HAL_IOCMG_SetPinPullMode(GPIO2_4_AS_GPIO2_4, PULL_NONE); /* Pull-up and Pull-down */ + HAL_IOCMG_SetPinSchmidtMode(GPIO2_4_AS_GPIO2_4, SCHMIDT_DISABLE); /* Schmitt input on/off */ + HAL_IOCMG_SetPinLevelShiftRate(GPIO2_4_AS_GPIO2_4, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + HAL_IOCMG_SetPinDriveRate(GPIO2_4_AS_GPIO2_4, DRIVER_RATE_2); /* Output signal edge fast/slow */ + /* Config PIN6 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO5_2_AS_GPIO5_2); /* Check function selection */ + HAL_IOCMG_SetPinPullMode(GPIO5_2_AS_GPIO5_2, PULL_NONE); /* Pull-up and Pull-down */ + HAL_IOCMG_SetPinSchmidtMode(GPIO5_2_AS_GPIO5_2, SCHMIDT_DISABLE); /* Schmitt input on/off */ + HAL_IOCMG_SetPinLevelShiftRate(GPIO5_2_AS_GPIO5_2, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + HAL_IOCMG_SetPinDriveRate(GPIO5_2_AS_GPIO5_2, DRIVER_RATE_2); /* Output signal edge fast/slow */ + /* Config PIN8 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO3_6_AS_GPIO3_6); /* Check function selection */ + HAL_IOCMG_SetPinPullMode(GPIO3_6_AS_GPIO3_6, PULL_NONE); /* Pull-up and Pull-down */ + HAL_IOCMG_SetPinSchmidtMode(GPIO3_6_AS_GPIO3_6, SCHMIDT_DISABLE); /* Schmitt input on/off */ + HAL_IOCMG_SetPinLevelShiftRate(GPIO3_6_AS_GPIO3_6, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + HAL_IOCMG_SetPinDriveRate(GPIO3_6_AS_GPIO3_6, DRIVER_RATE_2); /* Output signal edge fast/slow */ + /* Config PIN10 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO5_3_AS_GPIO5_3); /* Check function selection */ + HAL_IOCMG_SetPinPullMode(GPIO5_3_AS_GPIO5_3, PULL_NONE); /* Pull-up and Pull-down */ + HAL_IOCMG_SetPinSchmidtMode(GPIO5_3_AS_GPIO5_3, SCHMIDT_DISABLE); /* Schmitt input on/off */ + HAL_IOCMG_SetPinLevelShiftRate(GPIO5_3_AS_GPIO5_3, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + HAL_IOCMG_SetPinDriveRate(GPIO5_3_AS_GPIO5_3, DRIVER_RATE_2); /* Output signal edge fast/slow */ + /* Config PIN2 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO5_1_AS_GPIO5_1); /* Check function selection */ + HAL_IOCMG_SetPinPullMode(GPIO5_1_AS_GPIO5_1, PULL_NONE); /* Pull-up and Pull-down */ + HAL_IOCMG_SetPinSchmidtMode(GPIO5_1_AS_GPIO5_1, SCHMIDT_DISABLE); /* Schmitt input on/off */ + HAL_IOCMG_SetPinLevelShiftRate(GPIO5_1_AS_GPIO5_1, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + HAL_IOCMG_SetPinDriveRate(GPIO5_1_AS_GPIO5_1, DRIVER_RATE_2); /* Output signal edge fast/slow */ + /* Config PIN38 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO0_2_AS_RESETN); /* Check function selection */ + HAL_IOCMG_SetPinPullMode(GPIO0_2_AS_RESETN, PULL_NONE); /* Pull-up and Pull-down */ + HAL_IOCMG_SetPinSchmidtMode(GPIO0_2_AS_RESETN, SCHMIDT_DISABLE); /* Schmitt input on/off */ + HAL_IOCMG_SetPinLevelShiftRate(GPIO0_2_AS_RESETN, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + HAL_IOCMG_SetPinDriveRate(GPIO0_2_AS_RESETN, DRIVER_RATE_2); /* Output signal edge fast/slow */ + /* Config PIN39 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO0_3_AS_UART0_TXD); /* Check function selection */ + HAL_IOCMG_SetPinPullMode(GPIO0_3_AS_UART0_TXD, PULL_NONE); /* Pull-up and Pull-down */ + HAL_IOCMG_SetPinSchmidtMode(GPIO0_3_AS_UART0_TXD, SCHMIDT_DISABLE); /* Schmitt input on/off */ + HAL_IOCMG_SetPinLevelShiftRate(GPIO0_3_AS_UART0_TXD, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + HAL_IOCMG_SetPinDriveRate(GPIO0_3_AS_UART0_TXD, DRIVER_RATE_2); /* Output signal edge fast/slow */ + /* Config PIN40 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO0_4_AS_UART0_RXD); /* Check function selection */ + HAL_IOCMG_SetPinPullMode(GPIO0_4_AS_UART0_RXD, PULL_UP); /* Pull-up and Pull-down, UART RX recommend PULL_UP */ + HAL_IOCMG_SetPinSchmidtMode(GPIO0_4_AS_UART0_RXD, SCHMIDT_DISABLE); /* Schmitt input on/off */ + HAL_IOCMG_SetPinLevelShiftRate(GPIO0_4_AS_UART0_RXD, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + HAL_IOCMG_SetPinDriveRate(GPIO0_4_AS_UART0_RXD, DRIVER_RATE_2); /* Output signal edge fast/slow */ + /* Config PIN11 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO1_5_AS_UART2_TXD); /* Check function selection */ + HAL_IOCMG_SetPinPullMode(GPIO1_5_AS_UART2_TXD, PULL_NONE); /* Pull-up and Pull-down */ + HAL_IOCMG_SetPinSchmidtMode(GPIO1_5_AS_UART2_TXD, SCHMIDT_DISABLE); /* Schmitt input on/off */ + HAL_IOCMG_SetPinLevelShiftRate(GPIO1_5_AS_UART2_TXD, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + HAL_IOCMG_SetPinDriveRate(GPIO1_5_AS_UART2_TXD, DRIVER_RATE_2); /* Output signal edge fast/slow */ + /* Config PIN12 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO1_6_AS_UART2_RXD); /* Check function selection */ + HAL_IOCMG_SetPinPullMode(GPIO1_6_AS_UART2_RXD, PULL_UP); /* Pull-up and Pull-down, UART RX recommend PULL_UP */ + HAL_IOCMG_SetPinSchmidtMode(GPIO1_6_AS_UART2_RXD, SCHMIDT_DISABLE); /* Schmitt input on/off */ + HAL_IOCMG_SetPinLevelShiftRate(GPIO1_6_AS_UART2_RXD, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + HAL_IOCMG_SetPinDriveRate(GPIO1_6_AS_UART2_RXD, DRIVER_RATE_2); /* Output signal edge fast/slow */ + /* Config PIN31 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO2_0_AS_I2C0_SCL); /* Check function selection */ + HAL_IOCMG_SetPinPullMode(GPIO2_0_AS_I2C0_SCL, PULL_NONE); /* Pull-up and Pull-down */ + HAL_IOCMG_SetPinSchmidtMode(GPIO2_0_AS_I2C0_SCL, SCHMIDT_DISABLE); /* Schmitt input on/off */ + HAL_IOCMG_SetPinLevelShiftRate(GPIO2_0_AS_I2C0_SCL, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + HAL_IOCMG_SetPinDriveRate(GPIO2_0_AS_I2C0_SCL, DRIVER_RATE_2); /* Output signal edge fast/slow */ + /* Config PIN32 */ + HAL_IOCMG_SetPinAltFuncMode(GPIO2_1_AS_I2C0_SDA); /* Check function selection */ + HAL_IOCMG_SetPinPullMode(GPIO2_1_AS_I2C0_SDA, PULL_NONE); /* Pull-up and Pull-down */ + HAL_IOCMG_SetPinSchmidtMode(GPIO2_1_AS_I2C0_SDA, SCHMIDT_DISABLE); /* Schmitt input on/off */ + HAL_IOCMG_SetPinLevelShiftRate(GPIO2_1_AS_I2C0_SDA, LEVEL_SHIFT_RATE_SLOW); /* Output drive capability */ + HAL_IOCMG_SetPinDriveRate(GPIO2_1_AS_I2C0_SDA, DRIVER_RATE_2); /* Output signal edge fast/slow */ +} + +void SystemInit(void) +{ + IOConfig(); + UART0_Init(); + UART2_Init(); + TIMER0_Init(); + TIMER1_Init(); + I2C0_Init(); + GPIO_Init(); + + /* USER CODE BEGIN system_init */ + /* USER CODE END system_init */ +} \ No newline at end of file diff --git a/vendor/xinlingyu_92_3061M/Project/user/main.c b/vendor/xinlingyu_92_3061M/Project/user/main.c new file mode 100644 index 0000000000000000000000000000000000000000..b07407620a53cfa9d8aafc26041635ff4ea4d092 --- /dev/null +++ b/vendor/xinlingyu_92_3061M/Project/user/main.c @@ -0,0 +1,247 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file main.c + * @author MCU Driver Team + * @brief Main program body. + */ + +#include "typedefs.h" +#include "feature.h" +#include "main.h" +/* USER CODE BEGIN 0 */ +/* USER CODE 区域内代码不会被覆盖，区域外会被生成的默认代码覆盖（其余USER CODE 区域同理） */ +/* 建议用户放置头文件 */ +#include "PAJ7620U2.h" +/* USER CODE END 0 */ +TIMER_Handle g_timer0; +TIMER_Handle g_timer1; +UART_Handle g_uart0; +UART_Handle g_uart2; +I2C_Handle g_i2c0; +GPIO_Handle g_gpio2; +GPIO_Handle g_gpio1; +GPIO_Handle g_gpio5; +GPIO_Handle g_gpio3; +/* USER CODE BEGIN 1 */ +/* 建议用户定义全局变量、结构体、宏定义或函数声明等 */ +unsigned char g_uart0_rxdata; +unsigned char g_uart0_rxbuff[100]; +unsigned int g_uart0_rxin = 0; +unsigned int g_uart0_rxout = 0; +void UART0ReadInterruptCallback(void *handle); + +unsigned char g_uart2_rxdata; +unsigned char g_uart2_rxbuff[10 * 1024]; +unsigned int g_uart2_rxin = 0; +unsigned int g_uart2_rxout = 0; +void UART2ReadInterruptCallback(void *handle); + +unsigned char g_asr_cmd_id[4]; + +unsigned char g_step_motor = 0; +unsigned char g_step_motor_flag = 0; +unsigned long g_timer0_count = 0; +unsigned long g_timer1_count = 0; +/* USER CODE END 1 */ + +int main(void) +{ + /* USER CODE BEGIN 2 */ + /* 建议用户放置初始化代码或启动代码等 */ + /* USER CODE END 2 */ + SystemInit(); + /* USER CODE BEGIN 3 */ + /* 建议用户放置初始配置代码 */ + HAL_UART_ReadIT(&g_uart0, &g_uart0_rxdata, 1); + HAL_UART_ReadIT(&g_uart2, &g_uart2_rxdata, 1); + HAL_TIMER_Start(&g_timer0); + HAL_TIMER_Start(&g_timer1); + PAJ7620U2_Init(); + /* USER CODE END 3 */ + while (1) { + /* USER CODE BEGIN 4 */ + /* 建议用户放置周期性执行代码 */ + if (g_uart0_rxin != g_uart0_rxout) + { + HAL_UART_WriteBlocking(&g_uart0, &g_uart0_rxbuff[g_uart0_rxout++], 1, 1000); + g_uart0_rxout %= 100; + } + + if (g_uart2_rxin != g_uart2_rxout) + { + g_asr_cmd_id[0] = g_asr_cmd_id[1]; + g_asr_cmd_id[1] = g_asr_cmd_id[2]; + g_asr_cmd_id[2] = g_asr_cmd_id[3]; + g_asr_cmd_id[3] = g_uart2_rxbuff[g_uart2_rxout]; + + HAL_UART_WriteBlocking(&g_uart0, &g_uart2_rxbuff[g_uart2_rxout++], 1, 1000); + g_uart2_rxout %= (10 * 1024); + + if ( + (g_asr_cmd_id[0] == '1') && (g_asr_cmd_id[1] == '0') && (g_asr_cmd_id[2] == '0') + ) + { + if (g_asr_cmd_id[3] == '1') + { + g_step_motor_flag = 0; + } + else if (g_asr_cmd_id[3] == '2') + { + g_step_motor_flag = 1; + } + else + { + // + } + } + } + + PAJ7620U2_Handler(); + /* USER CODE END 4 */ + } + /* USER CODE BEGIN 5 */ + /* 建议用户放置代码流程 */ + /* USER CODE END 5 */ + return BASE_STATUS_OK; +} + +/* USER CODE BEGIN 6 */ +/* 建议用户放置自定义函数 */ +void GPIO2_4_CallbackFunc(void *param) +{ + GPIO_Handle *handle = (GPIO_Handle *)param; + BASE_FUNC_UNUSED(handle); + + if (g_step_motor_flag == 0) + { + g_step_motor_flag = 1; + HAL_GPIO_SetValue(&g_gpio2, GPIO_PIN_3, GPIO_LOW_LEVEL); + } + else + { + g_step_motor_flag = 0; + HAL_GPIO_SetValue(&g_gpio2, GPIO_PIN_3, GPIO_HIGH_LEVEL); + } +} + +void UART0ReadInterruptCallback(void *handle) +{ + BASE_FUNC_UNUSED(handle); + /* USER CODE BEGIN UART0_READ_IT_FINISH */ + HAL_UART_ReadIT(&g_uart0, &g_uart0_rxdata, 1); + + g_uart0_rxbuff[g_uart0_rxin++] = g_uart0_rxdata; + g_uart0_rxin %= 100; + /* USER CODE END UART0_READ_IT_FINISH */ +} + +void UART2ReadInterruptCallback(void *handle) +{ + BASE_FUNC_UNUSED(handle); + /* USER CODE BEGIN UART2_READ_IT_FINISH */ + HAL_UART_ReadIT(&g_uart2, &g_uart2_rxdata, 1); + + g_uart2_rxbuff[g_uart2_rxin++] = g_uart2_rxdata; + g_uart2_rxin %= (10 * 1024); + /* USER CODE END UART2_READ_IT_FINISH */ +} + +void TIMER0_InterruptProcess(void *handle) +{ + BASE_FUNC_UNUSED(handle); + /* USER CODE BEGIN TIMER0_InterruptProcess */ + + if (g_step_motor_flag == 1) + { + g_timer0_count++; + } + else + { + g_step_motor = 0; + g_timer0_count = 0; + + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_2, GPIO_LOW_LEVEL); + HAL_GPIO_SetValue(&g_gpio3, GPIO_PIN_6, GPIO_LOW_LEVEL); + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_3, GPIO_LOW_LEVEL); + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_1, GPIO_LOW_LEVEL); + } + + if (g_timer0_count > 2 * 5) + { + g_timer0_count = 0; + + switch (g_step_motor) + { + case 0: + g_step_motor = 1; + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_2, GPIO_LOW_LEVEL); + HAL_GPIO_SetValue(&g_gpio3, GPIO_PIN_6, GPIO_LOW_LEVEL); + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_3, GPIO_LOW_LEVEL); + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_1, GPIO_LOW_LEVEL); + break; + case 1: + g_step_motor = 2; + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_2, GPIO_HIGH_LEVEL); + HAL_GPIO_SetValue(&g_gpio3, GPIO_PIN_6, GPIO_LOW_LEVEL); + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_3, GPIO_LOW_LEVEL); + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_1, GPIO_LOW_LEVEL); + break; + case 2: + g_step_motor = 3; + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_2, GPIO_LOW_LEVEL); + HAL_GPIO_SetValue(&g_gpio3, GPIO_PIN_6, GPIO_HIGH_LEVEL); + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_3, GPIO_LOW_LEVEL); + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_1, GPIO_LOW_LEVEL); + break; + case 3: + g_step_motor = 4; + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_2, GPIO_LOW_LEVEL); + HAL_GPIO_SetValue(&g_gpio3, GPIO_PIN_6, GPIO_LOW_LEVEL); + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_3, GPIO_HIGH_LEVEL); + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_1, GPIO_LOW_LEVEL); + break; + case 4: + g_step_motor = 1; + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_2, GPIO_LOW_LEVEL); + HAL_GPIO_SetValue(&g_gpio3, GPIO_PIN_6, GPIO_LOW_LEVEL); + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_3, GPIO_LOW_LEVEL); + HAL_GPIO_SetValue(&g_gpio5, GPIO_PIN_1, GPIO_HIGH_LEVEL); + break; + default: + g_step_motor = 0; + break; + } + } + /* USER CODE END TIMER0_InterruptProcess */ +} + +void TIMER1_InterruptProcess(void *handle) +{ + BASE_FUNC_UNUSED(handle); + /* USER CODE BEGIN TIMER1_InterruptProcess */ + /* USER CODE END TIMER1_InterruptProcess */ + g_timer1_count++; + + if (g_timer1_count > 2 * 500) + { + g_timer1_count = 0; + + HAL_GPIO_TogglePin(&g_gpio1, GPIO_PIN_0); + } +} +/* USER CODE END 6 */ \ No newline at end of file