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create mode 100644 vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/user/main.c create mode 100644 vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/user/sample_gpio_led/inc/gpio_led_sample.h create mode 100644 vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/user/sample_gpio_led/readme.md create mode 100644 vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/user/sample_gpio_led/src/gpio_led_sample.c diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/.vscode/.attachinit b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/.vscode/.attachinit new file mode 100644 index 00000000..15f40d61 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/.vscode/.attachinit @@ -0,0 +1,16 @@ +echo debug_tool = openocd(HiSpark-Link)\n +echo Initializing remote target...\n +define pio_reset_halt_target +monitor reset halt +set var $pc=0x03000004 +end +define pio_reset_run_target +monitor reset +end +target extended-remote :3333 +monitor init +monitor halt +tbreak main +define pio_restart_target +pio_reset_halt_target +echo Initialization completed\n \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/.vscode/.launchinit b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/.vscode/.launchinit new file mode 100644 index 00000000..f514a5d8 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/.vscode/.launchinit @@ -0,0 +1,17 @@ +echo debug_tool = openocd(HiSpark-Link)\n +echo Initializing remote target...\n +define pio_reset_halt_target +monitor reset halt +set var $pc=0x03000004 +end +define pio_reset_run_target +monitor reset +end +target extended-remote :3333 +monitor init +load +pio_reset_halt_target +tbreak main +define pio_restart_target +pio_reset_halt_target +echo Initialization completed\n \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/.vscode/c_cpp_properties.json b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/.vscode/c_cpp_properties.json new file mode 100644 index 00000000..1e47f94f --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/.vscode/c_cpp_properties.json @@ -0,0 +1,21 @@ +{ + "configurations": [ + { + "name": "c/cpp plugin configurations", + "compilerPath": "d:\\Program Files\\HiSpark Studio\\tools\\Windows\\cc_riscv32_musl_fp_win\\bin\\riscv32-linux-musl-gcc.exe", + "includePath": [ + "${workspaceFolder}/**" + ], + "browse": { + "limitSymbolsToIncludedHeaders": true, + "path": [ + "${workspaceFolder}/**" + ] + }, + "defines": [ + "FLOAT_SUPPORT" + ] + } + ], + "version": 4 +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/.vscode/launch.json b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/.vscode/launch.json new file mode 100644 index 00000000..ceb9760c --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/.vscode/launch.json @@ -0,0 +1,52 @@ +{ + "configurations": [ + { + "type": "deveco-device-tool-debug", + "request": "launch", + "name": "GDB Launch (Download and Reset Program)", + "debugInitPath": "${workspaceFolder}/.vscode", + "servertype": "openocd(HiSpark-Link)", + "executable": "./out/bin/target.elf", + "toolchainBinDir": "${command:toolsPath}\\Windows\\cc_riscv32_musl_fp_win\\bin", + "internalConsoleOptions": "openOnSessionStart", + "serverpath": "${command:toolsPath}\\hw_openocd\\bin\\openocd.exe", + "serverArgs": [ + "-c", + "adapter speed 5000", + "-c", + "gdb_port 3333", + "-s", + "${command:toolsPath}\\hw_openocd", + "-f", + "interface\\ft2232h-ftdi-swd.cfg", + "-f", + "target\\3065HRPIRZ-swd.cfg" + ], + "svdFile": "${command:projectWizardExtensionPath}\\resources\\debug\\svd\\3065HRPIRZ.svd" + }, + { + "type": "deveco-device-tool-debug", + "request": "attach", + "name": "GDB Attach (Attach to Running Program)", + "debugInitPath": "${workspaceFolder}/.vscode", + "servertype": "openocd(HiSpark-Link)", + "executable": "./out/bin/target.elf", + "toolchainBinDir": "${command:toolsPath}\\Windows\\cc_riscv32_musl_fp_win\\bin", + "internalConsoleOptions": "openOnSessionStart", + "serverpath": "${command:toolsPath}\\hw_openocd\\bin\\openocd.exe", + "serverArgs": [ + "-c", + "adapter speed 5000", + "-c", + "gdb_port 3333", + "-s", + "${command:toolsPath}\\hw_openocd", + "-f", + "interface\\ft2232h-ftdi-swd.cfg", + "-f", + "target\\3065HRPIRZ-swd.cfg" + ], + "svdFile": "${command:projectWizardExtensionPath}\\resources\\debug\\svd\\3065HRPIRZ.svd" + } + ] +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/.vscode/problems.json b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/.vscode/problems.json new file mode 100644 index 00000000..0637a088 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/.vscode/problems.json @@ -0,0 +1 @@ +[] \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/.vscode/settings.json b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/.vscode/settings.json new file mode 100644 index 00000000..54efb092 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/.vscode/settings.json @@ -0,0 +1,7 @@ +{ + "files.associations": { + "ec200.h": "c", + "gpio_led_sample.h": "c", + "wdg.h": "c" + } +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/T1.hiproj b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/T1.hiproj new file mode 100644 index 00000000..4aca4801 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/T1.hiproj @@ -0,0 +1,80 @@ +[information] +series_name=3065h +board=3065HRPIRZ +sdk_path=d:\AhaisiMCU\open_solarec-master +flash=155648 +board_build.mcu=3065HRPIRZ +platform=vendorhm +json_path=3065HRPIRZ.json +project_type=MCU + +[chipconfig] +chipconfig=true + +[variabletrace] +variabletrace=true + +[compile] +tool_chain=cc_riscv32_musl_fp_win +link_c_library_in_toolchain=yes +link_c_library_in_compilationchain=yes +custom_build_command=undefined -d FLOAT_SUPPORT +custom_clean_command=undefined +map_path=./out/bin/target.map +compile_type=debug +constant_type=float +optimization=O0 +warning=yes +werror=no +wno_unused_function=no +wno_unused_label=no +wno_unused_parameter=no +wno_unused_variable=no +wno_missing_prototypes=no +static_library_enable=no +static_library_name= +static_library_dependency_header_file= +static_library_source_file= +fstack_protector_strong=no +extern_staticlib_path= +extern_staticlib_include= +global_macro_definition={"FLOAT_SUPPORT":""} +generate_crc=no +generate_checksum=no +generate_allinone_bin=yes +generate_target_hex=yes +parse_elf_for_livewatch=no +parse_analysis_json=yes +padding=no + +[debug] +elf_path=./out/bin/target.elf +breakpoints_limitation=7 +client=gdb +tool=HiSpark-Link +interface=swd +speed=5000 +openocd_interface_file= +openocd_target_file= +timeout=60000 +port=3333 + +[upload] +bin_path=./out/bin/target.bin +protocol=serial +reset=1 +burn_verification=0 +debug_board=HiSpark-Trace +frequency=5000 +address=0x3000000 +partition_length=0x26000 +stop_bit=0 +parity=N +baud=115200 +port=COM11 + +[console] +port=COM10 +baud=115200 +stop_bit=0 +parity=N diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/analyzerJson/assembleFile.asm b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/analyzerJson/assembleFile.asm new file mode 100644 index 00000000..86674777 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/analyzerJson/assembleFile.asm @@ -0,0 +1,6520 @@ + +d:\workspace\T1\out\bin\target.elf: file format elf32-littleriscv + + +Disassembly of section .text.entry: + +03000004 <_start>: + 3000004: 50c0006f j 3000510 + +03000008 : + 3000008: 4780006f j 3000480 + 300000c: 4740006f j 3000480 + 3000010: 4700006f j 3000480 + 3000014: 46c0006f j 3000480 + 3000018: 4680006f j 3000480 + 300001c: 4640006f j 3000480 + 3000020: 4600006f j 3000480 + 3000024: 45c0006f j 3000480 + 3000028: 4580006f j 3000480 + 300002c: 4540006f j 3000480 + 3000030: 4500006f j 3000480 + 3000034: 44c0006f j 3000480 + 3000038: 4480006f j 3000480 + 300003c: 4440006f j 3000480 + 3000040: 4400006f j 3000480 + 3000044: 43c0006f j 3000480 + 3000048: 4380006f j 3000480 + 300004c: 4340006f j 3000480 + 3000050: 4300006f j 3000480 + 3000054: 42c0006f j 3000480 + 3000058: 4280006f j 3000480 + 300005c: 4240006f j 3000480 + 3000060: 4200006f j 3000480 + 3000064: 41c0006f j 3000480 + 3000068: 4180006f j 3000480 + 300006c: 4140006f j 3000480 + 3000070: 2640006f j 30002d4 + 3000074: 2600006f j 30002d4 + 3000078: 25c0006f j 30002d4 + 300007c: 2580006f j 30002d4 + 3000080: 2540006f j 30002d4 + 3000084: 2500006f j 30002d4 + 3000088: 24c0006f j 30002d4 + 300008c: 2480006f j 30002d4 + 3000090: 2440006f j 30002d4 + 3000094: 2400006f j 30002d4 + 3000098: 23c0006f j 30002d4 + 300009c: 2380006f j 30002d4 + 30000a0: 2340006f j 30002d4 + 30000a4: 2300006f j 30002d4 + 30000a8: 22c0006f j 30002d4 + 30000ac: 2280006f j 30002d4 + 30000b0: 2240006f j 30002d4 + 30000b4: 2200006f j 30002d4 + 30000b8: 21c0006f j 30002d4 + 30000bc: 2180006f j 30002d4 + 30000c0: 2140006f j 30002d4 + 30000c4: 2100006f j 30002d4 + 30000c8: 20c0006f j 30002d4 + 30000cc: 2080006f j 30002d4 + 30000d0: 2040006f j 30002d4 + 30000d4: 2000006f j 30002d4 + 30000d8: 1fc0006f j 30002d4 + 30000dc: 1f80006f j 30002d4 + 30000e0: 1f40006f j 30002d4 + 30000e4: 1f00006f j 30002d4 + 30000e8: 1ec0006f j 30002d4 + 30000ec: 1e80006f j 30002d4 + 30000f0: 1e40006f j 30002d4 + 30000f4: 1e00006f j 30002d4 + 30000f8: 1dc0006f j 30002d4 + 30000fc: 1d80006f j 30002d4 + 3000100: 1d40006f j 30002d4 + 3000104: 1d00006f j 30002d4 + 3000108: 1cc0006f j 30002d4 + 300010c: 1c80006f j 30002d4 + 3000110: 1c40006f j 30002d4 + 3000114: 1c00006f j 30002d4 + 3000118: 1bc0006f j 30002d4 + 300011c: 1b80006f j 30002d4 + 3000120: 1b40006f j 30002d4 + 3000124: 1b00006f j 30002d4 + 3000128: 1ac0006f j 30002d4 + 300012c: 1a80006f j 30002d4 + 3000130: 1a40006f j 30002d4 + 3000134: 1a00006f j 30002d4 + 3000138: 19c0006f j 30002d4 + 300013c: 1980006f j 30002d4 + 3000140: 1940006f j 30002d4 + 3000144: 1900006f j 30002d4 + 3000148: 18c0006f j 30002d4 + 300014c: 1880006f j 30002d4 + 3000150: 1840006f j 30002d4 + 3000154: 1800006f j 30002d4 + 3000158: 17c0006f j 30002d4 + 300015c: 1780006f j 30002d4 + 3000160: 1740006f j 30002d4 + 3000164: 1700006f j 30002d4 + 3000168: 16c0006f j 30002d4 + 300016c: 1680006f j 30002d4 + 3000170: 1640006f j 30002d4 + 3000174: 1600006f j 30002d4 + 3000178: 15c0006f j 30002d4 + 300017c: 1580006f j 30002d4 + 3000180: 1540006f j 30002d4 + 3000184: 1500006f j 30002d4 + 3000188: 14c0006f j 30002d4 + 300018c: 1480006f j 30002d4 + 3000190: 1440006f j 30002d4 + 3000194: 1400006f j 30002d4 + 3000198: 13c0006f j 30002d4 + 300019c: 1380006f j 30002d4 + 30001a0: 1340006f j 30002d4 + 30001a4: 1300006f j 30002d4 + 30001a8: 12c0006f j 30002d4 + 30001ac: 1280006f j 30002d4 + 30001b0: 1240006f j 30002d4 + 30001b4: 1200006f j 30002d4 + 30001b8: 11c0006f j 30002d4 + 30001bc: 1180006f j 30002d4 + 30001c0: 1140006f j 30002d4 + 30001c4: 1100006f j 30002d4 + 30001c8: 10c0006f j 30002d4 + 30001cc: 1080006f j 30002d4 + 30001d0: 1040006f j 30002d4 + 30001d4: 1000006f j 30002d4 + 30001d8: 0fc0006f j 30002d4 + 30001dc: 0f80006f j 30002d4 + 30001e0: 0f40006f j 30002d4 + 30001e4: 0f00006f j 30002d4 + 30001e8: 0ec0006f j 30002d4 + 30001ec: 0e80006f j 30002d4 + +030001f0 : + 30001f0: f9010113 addi sp,sp,-112 + 30001f4: 04812023 sw s0,64(sp) + 30001f8: 04912223 sw s1,68(sp) + 30001fc: 05212423 sw s2,72(sp) + 3000200: 05312623 sw s3,76(sp) + 3000204: 05412823 sw s4,80(sp) + 3000208: 05512a23 sw s5,84(sp) + 300020c: 05612c23 sw s6,88(sp) + 3000210: 05712e23 sw s7,92(sp) + 3000214: 07812023 sw s8,96(sp) + 3000218: 07912223 sw s9,100(sp) + 300021c: 07a12423 sw s10,104(sp) + 3000220: 07b12623 sw s11,108(sp) + 3000224: 11010593 addi a1,sp,272 + 3000228: 06b12823 sw a1,112(sp) + 300022c: 06312a23 sw gp,116(sp) + 3000230: 06412c23 sw tp,120(sp) + 3000234: 34102573 csrr a0,mepc + 3000238: 300025f3 csrr a1,mstatus + 300023c: 34302673 csrr a2,mtval + 3000240: 342026f3 csrr a3,mcause + 3000244: 06a12e23 sw a0,124(sp) + 3000248: 08b12023 sw a1,128(sp) + 300024c: 08c12223 sw a2,132(sp) + 3000250: 08d12423 sw a3,136(sp) + 3000254: 00010513 mv a0,sp + 3000258: 5aa010ef jal ra,3001802 + +0300025c : + 300025c: a001 j 300025c + 300025e: 00000013 nop + +03000262 : + 3000262: f9010113 addi sp,sp,-112 + 3000266: 04812023 sw s0,64(sp) + 300026a: 04912223 sw s1,68(sp) + 300026e: 05212423 sw s2,72(sp) + 3000272: 05312623 sw s3,76(sp) + 3000276: 05412823 sw s4,80(sp) + 300027a: 05512a23 sw s5,84(sp) + 300027e: 05612c23 sw s6,88(sp) + 3000282: 05712e23 sw s7,92(sp) + 3000286: 07812023 sw s8,96(sp) + 300028a: 07912223 sw s9,100(sp) + 300028e: 07a12423 sw s10,104(sp) + 3000292: 07b12623 sw s11,108(sp) + 3000296: 11010593 addi a1,sp,272 + 300029a: 06b12823 sw a1,112(sp) + 300029e: 06312a23 sw gp,116(sp) + 30002a2: 06412c23 sw tp,120(sp) + 30002a6: 34102573 csrr a0,mepc + 30002aa: 300025f3 csrr a1,mstatus + 30002ae: 34302673 csrr a2,mtval + 30002b2: 342026f3 csrr a3,mcause + 30002b6: 06a12e23 sw a0,124(sp) + 30002ba: 08b12023 sw a1,128(sp) + 30002be: 08c12223 sw a2,132(sp) + 30002c2: 08d12423 sw a3,136(sp) + 30002c6: 00010513 mv a0,sp + 30002ca: 30047073 csrci mstatus,8 + 30002ce: 516010ef jal ra,30017e4 + +030002d2 : + 30002d2: a001 j 30002d2 + +030002d4 : + 30002d4: f6010113 addi sp,sp,-160 + 30002d8: 00a12623 sw a0,12(sp) + 30002dc: 00b12823 sw a1,16(sp) + 30002e0: 7ed02573 csrr a0,0x7ed + 30002e4: bfe025f3 csrr a1,0xbfe + 30002e8: bfe51073 csrw 0xbfe,a0 + 30002ec: 00b12c23 sw a1,24(sp) + 30002f0: 300025f3 csrr a1,mstatus + 30002f4: 00b12e23 sw a1,28(sp) + 30002f8: 341025f3 csrr a1,mepc + 30002fc: 02b12023 sw a1,32(sp) + 3000300: 34202573 csrr a0,mcause + 3000304: 000025b7 lui a1,0x2 + 3000308: 80058593 addi a1,a1,-2048 # 1800 + 300030c: 3005a073 csrs mstatus,a1 + 3000310: 00000597 auipc a1,0x0 + 3000314: 01058593 addi a1,a1,16 # 3000320 + 3000318: 34159073 csrw mepc,a1 + 300031c: 30200073 mret + +03000320 : + 3000320: 00512023 sw t0,0(sp) + 3000324: 00612223 sw t1,4(sp) + 3000328: 00712423 sw t2,8(sp) + 300032c: 00c12a23 sw a2,20(sp) + 3000330: 02112223 sw ra,36(sp) + 3000334: 02d12423 sw a3,40(sp) + 3000338: 02e12623 sw a4,44(sp) + 300033c: 02f12823 sw a5,48(sp) + 3000340: 03012a23 sw a6,52(sp) + 3000344: 03112c23 sw a7,56(sp) + 3000348: 03c12e23 sw t3,60(sp) + 300034c: 05d12023 sw t4,64(sp) + 3000350: 05e12223 sw t5,68(sp) + 3000354: 05f12423 sw t6,72(sp) + 3000358: 04012627 fsw ft0,76(sp) + 300035c: 04112827 fsw ft1,80(sp) + 3000360: 04212a27 fsw ft2,84(sp) + 3000364: 04312c27 fsw ft3,88(sp) + 3000368: 04412e27 fsw ft4,92(sp) + 300036c: 06512027 fsw ft5,96(sp) + 3000370: 06612227 fsw ft6,100(sp) + 3000374: 06712427 fsw ft7,104(sp) + 3000378: 06a12627 fsw fa0,108(sp) + 300037c: 06b12827 fsw fa1,112(sp) + 3000380: 06c12a27 fsw fa2,116(sp) + 3000384: 06d12c27 fsw fa3,120(sp) + 3000388: 06e12e27 fsw fa4,124(sp) + 300038c: 08f12027 fsw fa5,128(sp) + 3000390: 09012227 fsw fa6,132(sp) + 3000394: 09112427 fsw fa7,136(sp) + 3000398: 09c12627 fsw ft8,140(sp) + 300039c: 09d12827 fsw ft9,144(sp) + 30003a0: 09e12a27 fsw ft10,148(sp) + 30003a4: 09f12c27 fsw ft11,152(sp) + 30003a8: 003022f3 frcsr t0 + 30003ac: 08512e23 sw t0,156(sp) + 30003b0: 0ff57513 andi a0,a0,255 + 30003b4: 384010ef jal ra,3001738 + +030003b8 : + 30003b8: 00412303 lw t1,4(sp) + 30003bc: 00812383 lw t2,8(sp) + 30003c0: 01412603 lw a2,20(sp) + 30003c4: 02412083 lw ra,36(sp) + 30003c8: 02812683 lw a3,40(sp) + 30003cc: 02c12703 lw a4,44(sp) + 30003d0: 03012783 lw a5,48(sp) + 30003d4: 03412803 lw a6,52(sp) + 30003d8: 03812883 lw a7,56(sp) + 30003dc: 03c12e03 lw t3,60(sp) + 30003e0: 04012e83 lw t4,64(sp) + 30003e4: 04412f03 lw t5,68(sp) + 30003e8: 04812f83 lw t6,72(sp) + 30003ec: 04c12007 flw ft0,76(sp) + 30003f0: 05012087 flw ft1,80(sp) + 30003f4: 05412107 flw ft2,84(sp) + 30003f8: 05812187 flw ft3,88(sp) + 30003fc: 05c12207 flw ft4,92(sp) + 3000400: 06012287 flw ft5,96(sp) + 3000404: 06412307 flw ft6,100(sp) + 3000408: 06812387 flw ft7,104(sp) + 300040c: 06c12507 flw fa0,108(sp) + 3000410: 07012587 flw fa1,112(sp) + 3000414: 07412607 flw fa2,116(sp) + 3000418: 07812687 flw fa3,120(sp) + 300041c: 07c12707 flw fa4,124(sp) + 3000420: 08012787 flw fa5,128(sp) + 3000424: 08412807 flw fa6,132(sp) + 3000428: 08812887 flw fa7,136(sp) + 300042c: 08c12e07 flw ft8,140(sp) + 3000430: 09012e87 flw ft9,144(sp) + 3000434: 09412f07 flw ft10,148(sp) + 3000438: 09812f87 flw ft11,152(sp) + 300043c: 09c12283 lw t0,156(sp) + 3000440: 00329073 fscsr t0 + +03000444 : + 3000444: 01c12503 lw a0,28(sp) + 3000448: 02012583 lw a1,32(sp) + 300044c: 300022f3 csrr t0,mstatus + 3000450: 0082f293 andi t0,t0,8 + 3000454: 0002923b bnei t0,0,300045c + 3000458: f7757513 andi a0,a0,-137 + +0300045c : + 300045c: 30051073 csrw mstatus,a0 + 3000460: 00012283 lw t0,0(sp) + 3000464: 34159073 csrw mepc,a1 + 3000468: 01812503 lw a0,24(sp) + 300046c: bfe51073 csrw 0xbfe,a0 + 3000470: 01012583 lw a1,16(sp) + 3000474: 00c12503 lw a0,12(sp) + 3000478: 0a010113 addi sp,sp,160 + 300047c: 30200073 mret + +03000480 : + 3000480: f6010113 addi sp,sp,-160 + 3000484: fff11f8b stmia {ra,t0-t6,a0-a7},(sp) + 3000488: f6010113 addi sp,sp,-160 + 300048c: 34202573 csrr a0,mcause + 3000490: 00b00313 li t1,11 + 3000494: 02650c63 beq a0,t1,30004cc + 3000498: 00800313 li t1,8 + 300049c: 02650863 beq a0,t1,30004cc + 30004a0: 800005b7 lui a1,0x80000 + 30004a4: 0ff00613 li a2,255 + 30004a8: 00b575b3 and a1,a0,a1 + 30004ac: 00c57533 and a0,a0,a2 + 30004b0: 00c00613 li a2,12 + 30004b4: d2c50ee3 beq a0,a2,30001f0 + 30004b8: da0585e3 beqz a1,3000262 + 30004bc: 0a010113 addi sp,sp,160 + 30004c0: fff10f8b ldmia {ra,t0-t6,a0-a7},(sp) + 30004c4: 0a010113 addi sp,sp,160 + 30004c8: 30200073 mret + +030004cc : + 30004cc: 000023b7 lui t2,0x2 + 30004d0: 80038393 addi t2,t2,-2048 # 1800 + 30004d4: 3003a073 csrs mstatus,t2 + 30004d8: 341022f3 csrr t0,mepc + 30004dc: 00428293 addi t0,t0,4 + 30004e0: 34129073 csrw mepc,t0 + 30004e4: 0a010113 addi sp,sp,160 + 30004e8: fff10f8b ldmia {ra,t0-t6,a0-a7},(sp) + 30004ec: 0a010113 addi sp,sp,160 + 30004f0: 30200073 mret + +030004f4 : + 30004f4: 0072dc63 bge t0,t2,300050c + 30004f8: 00032e03 lw t3,0(t1) + 30004fc: 01c2a023 sw t3,0(t0) + 3000500: 00428293 addi t0,t0,4 + 3000504: 00430313 addi t1,t1,4 + 3000508: fedff06f j 30004f4 + +0300050c : + 300050c: 00008067 ret + +03000510 : + 3000510: 30005073 csrwi mstatus,0 + 3000514: 30405073 csrwi mie,0 + 3000518: 30047073 csrci mstatus,8 + 300051c: 00000297 auipc t0,0x0 + 3000520: aec28293 addi t0,t0,-1300 # 3000008 + 3000524: 00128293 addi t0,t0,1 + 3000528: 30529073 csrw mtvec,t0 + 300052c: 7ef0d073 csrwi 0x7ef,1 + +03000530 : + 3000530: 147102b7 lui t0,0x14710 + 3000534: 1202a303 lw t1,288(t0) # 14710120 + 3000538: 00136313 ori t1,t1,1 + 300053c: 1262a023 sw t1,288(t0) + 3000540: 1242a303 lw t1,292(t0) + 3000544: 00136313 ori t1,t1,1 + 3000548: 1262a223 sw t1,292(t0) + 300054c: fedcc2b7 lui t0,0xfedcc + 3000550: a9828293 addi t0,t0,-1384 # fedcba98 + 3000554: 14710337 lui t1,0x14710 + 3000558: 20030313 addi t1,t1,512 # 14710200 + 300055c: 00532023 sw t0,0(t1) + 3000560: 01000197 auipc gp,0x1000 + 3000564: d8618193 addi gp,gp,-634 # 40002e6 <__global_pointer$> + 3000568: 01003117 auipc sp,0x1003 + 300056c: 69810113 addi sp,sp,1688 # 4003c00 <__INTERRUPT_STACK_BEGIN__> + 3000570: 143002b7 lui t0,0x14300 + 3000574: 00828293 addi t0,t0,8 # 14300008 + 3000578: 0002a303 lw t1,0(t0) + 300057c: 02037313 andi t1,t1,32 + 3000580: 0062a023 sw t1,0(t0) + 3000584: 140002b7 lui t0,0x14000 + 3000588: 00000313 li t1,0 + 300058c: 0262a223 sw t1,36(t0) # 14000024 + 3000590: 0262a423 sw t1,40(t0) + 3000594: 0262a623 sw t1,44(t0) + 3000598: 0262a823 sw t1,48(t0) + 300059c: 0462a423 sw t1,72(t0) + +030005a0 : + 30005a0: 101082b7 lui t0,0x10108 + 30005a4: 30028293 addi t0,t0,768 # 10108300 + 30005a8: 0002a303 lw t1,0(t0) + 30005ac: 00136313 ori t1,t1,1 + 30005b0: 0062a023 sw t1,0(t0) + 30005b4: d1a18293 addi t0,gp,-742 # 4000000 + 30005b8: 01004317 auipc t1,0x1004 + 30005bc: a4830313 addi t1,t1,-1464 # 4004000 + 30005c0: 00000393 li t2,0 + +030005c4 : + 30005c4: 0072a023 sw t2,0(t0) + 30005c8: 00428293 addi t0,t0,4 + 30005cc: fe62cce3 blt t0,t1,30005c4 + +030005d0 : + 30005d0: ff000297 auipc t0,0xff000 + 30005d4: a3028293 addi t0,t0,-1488 # 2000000 + 30005d8: 00000317 auipc t1,0x0 + 30005dc: 0d430313 addi t1,t1,212 # 30006ac + 30005e0: ff000397 auipc t2,0xff000 + 30005e4: a2038393 addi t2,t2,-1504 # 2000000 + 30005e8: f0dff0ef jal ra,30004f4 + +030005ec : + 30005ec: d1a18293 addi t0,gp,-742 # 4000000 + 30005f0: 00000317 auipc t1,0x0 + 30005f4: 0bc30313 addi t1,t1,188 # 30006ac + 30005f8: d1a18393 addi t2,gp,-742 # 4000000 + 30005fc: ef9ff0ef jal ra,30004f4 + +03000600 : + 3000600: d3a18293 addi t0,gp,-710 # 4000020 + 3000604: 00004317 auipc t1,0x4 + 3000608: 3fc30313 addi t1,t1,1020 # 3004a00 <__data_load> + 300060c: d4218393 addi t2,gp,-702 # 4000028 + 3000610: ee5ff0ef jal ra,30004f4 + +03000614 : + 3000614: 01002297 auipc t0,0x1002 + 3000618: 1dc28293 addi t0,t0,476 # 40027f0 + 300061c: 00004317 auipc t1,0x4 + 3000620: 3ec30313 addi t1,t1,1004 # 3004a08 <__checksum_addr> + 3000624: 01002397 auipc t2,0x1002 + 3000628: 1cc38393 addi t2,t2,460 # 40027f0 + 300062c: ec9ff0ef jal ra,30004f4 + +03000630 : + 3000630: 7c005073 csrwi 0x7c0,0 + 3000634: 0ff0000f fence + 3000638: 7c105073 csrwi 0x7c1,0 + 300063c: 0ff0000f fence + 3000640: 000022b7 lui t0,0x2 + 3000644: 00828293 addi t0,t0,8 # 2008 + 3000648: 3002a073 csrs mstatus,t0 + 300064c: 02000293 li t0,32 + 3000650: 3012a073 csrs misa,t0 + 3000654: 111112b7 lui t0,0x11111 + 3000658: 11128293 addi t0,t0,273 # 11111111 + 300065c: bc029073 csrw 0xbc0,t0 + 3000660: bc129073 csrw 0xbc1,t0 + 3000664: bc229073 csrw 0xbc2,t0 + 3000668: bc329073 csrw 0xbc3,t0 + 300066c: bc429073 csrw 0xbc4,t0 + 3000670: bc529073 csrw 0xbc5,t0 + 3000674: bc629073 csrw 0xbc6,t0 + 3000678: bc729073 csrw 0xbc7,t0 + 300067c: bc829073 csrw 0xbc8,t0 + 3000680: bc929073 csrw 0xbc9,t0 + 3000684: bca29073 csrw 0xbca,t0 + 3000688: bcb29073 csrw 0xbcb,t0 + 300068c: bcc29073 csrw 0xbcc,t0 + 3000690: bcd29073 csrw 0xbcd,t0 + 3000694: bce29073 csrw 0xbce,t0 + 3000698: bcf29073 csrw 0xbcf,t0 + 300069c: 00000073 ecall + 30006a0: 014000ef jal ra,30006b4 + 30006a4: 29b030ef jal ra,300413e
+ +030006a8 : + 30006a8: 0000006f j 30006a8 + +Disassembly of section .text: + +030006ac : + 30006ac: 1141 addi sp,sp,-16 + 30006ae: c622 sw s0,12(sp) + 30006b0: 0800 addi s0,sp,16 + 30006b2: a001 j 30006b2 + +030006b4 : + 30006b4: 1101 addi sp,sp,-32 + 30006b6: ce06 sw ra,28(sp) + 30006b8: cc22 sw s0,24(sp) + 30006ba: 1000 addi s0,sp,32 + 30006bc: fec40793 addi a5,s0,-20 + 30006c0: 853e mv a0,a5 + 30006c2: 289030ef jal ra,300414a + 30006c6: 87aa mv a5,a0 + 30006c8: c391 beqz a5,30006cc + 30006ca: 37cd jal ra,30006ac + 30006cc: fec42783 lw a5,-20(s0) + 30006d0: 853e mv a0,a5 + 30006d2: 1c3000ef jal ra,3001094 + 30006d6: 465000ef jal ra,300133a + 30006da: fec42783 lw a5,-20(s0) + 30006de: 853e mv a0,a5 + 30006e0: 0e3000ef jal ra,3000fc2 + 30006e4: 4a8010ef jal ra,3001b8c + 30006e8: 872a mv a4,a0 + 30006ea: 017d87b7 lui a5,0x17d8 + 30006ee: 84078793 addi a5,a5,-1984 # 17d7840 + 30006f2: 00f70463 beq a4,a5,30006fa + 30006f6: 319000ef jal ra,300120e + 30006fa: 07a010ef jal ra,3001774 + 30006fe: 2821 jal ra,3000716 + 3000700: 00d000ef jal ra,3000f0c + 3000704: 33d000ef jal ra,3001240 + 3000708: 3a9000ef jal ra,30012b0 + 300070c: 0001 nop + 300070e: 40f2 lw ra,28(sp) + 3000710: 4462 lw s0,24(sp) + 3000712: 6105 addi sp,sp,32 + 3000714: 8082 ret + +03000716 : + 3000716: 715d addi sp,sp,-80 + 3000718: c686 sw ra,76(sp) + 300071a: c4a2 sw s0,72(sp) + 300071c: 0880 addi s0,sp,80 + 300071e: fdc40793 addi a5,s0,-36 + 3000722: 863e mv a2,a5 + 3000724: 4591 li a1,4 + 3000726: 4501 li a0,0 + 3000728: 2505 jal ra,3000d48 + 300072a: fdc42703 lw a4,-36(s0) + 300072e: 5aa597b7 lui a5,0x5aa59 + 3000732: 66978793 addi a5,a5,1641 # 5aa59669 + 3000736: 00f71563 bne a4,a5,3000740 + 300073a: 4705 li a4,1 + 300073c: e2e18923 sb a4,-462(gp) # 4000118 + 3000740: fcc40793 addi a5,s0,-52 + 3000744: 863e mv a2,a5 + 3000746: 4589 li a1,2 + 3000748: 4501 li a0,0 + 300074a: 2bfd jal ra,3000d48 + 300074c: fd444783 lbu a5,-44(s0) + 3000750: 873e mv a4,a5 + 3000752: d2e1ad23 sw a4,-710(gp) # 4000020 + 3000756: e321c783 lbu a5,-462(gp) # 4000118 + 300075a: cb81 beqz a5,300076a + 300075c: fbc40793 addi a5,s0,-68 + 3000760: 863e mv a2,a5 + 3000762: 45d5 li a1,21 + 3000764: 4501 li a0,0 + 3000766: 23cd jal ra,3000d48 + 3000768: a051 j 30007ec + 300076a: fc042783 lw a5,-64(s0) + 300076e: 9b81 andi a5,a5,-32 + 3000770: 0107e793 ori a5,a5,16 + 3000774: fcf42023 sw a5,-64(s0) + 3000778: fc042783 lw a5,-64(s0) + 300077c: c1f7f793 andi a5,a5,-993 + 3000780: 2007e793 ori a5,a5,512 + 3000784: fcf42023 sw a5,-64(s0) + 3000788: fc442783 lw a5,-60(s0) + 300078c: 9b81 andi a5,a5,-32 + 300078e: 0107e793 ori a5,a5,16 + 3000792: fcf42223 sw a5,-60(s0) + 3000796: fc842783 lw a5,-56(s0) + 300079a: 9b81 andi a5,a5,-32 + 300079c: 0107e793 ori a5,a5,16 + 30007a0: fcf42423 sw a5,-56(s0) + 30007a4: fc442783 lw a5,-60(s0) + 30007a8: c1f7f793 andi a5,a5,-993 + 30007ac: 2007e793 ori a5,a5,512 + 30007b0: fcf42223 sw a5,-60(s0) + 30007b4: fc842783 lw a5,-56(s0) + 30007b8: c1f7f793 andi a5,a5,-993 + 30007bc: 2007e793 ori a5,a5,512 + 30007c0: fcf42423 sw a5,-56(s0) + 30007c4: fc442703 lw a4,-60(s0) + 30007c8: 77e1 lui a5,0xffff8 + 30007ca: 3ff78793 addi a5,a5,1023 # ffff83ff + 30007ce: 8f7d and a4,a4,a5 + 30007d0: 6791 lui a5,0x4 + 30007d2: 8fd9 or a5,a5,a4 + 30007d4: fcf42223 sw a5,-60(s0) + 30007d8: fc842703 lw a4,-56(s0) + 30007dc: 77e1 lui a5,0xffff8 + 30007de: 3ff78793 addi a5,a5,1023 # ffff83ff + 30007e2: 8f7d and a4,a4,a5 + 30007e4: 6791 lui a5,0x4 + 30007e6: 8fd9 or a5,a5,a4 + 30007e8: fcf42423 sw a5,-56(s0) + 30007ec: 10100737 lui a4,0x10100 + 30007f0: fc042783 lw a5,-64(s0) + 30007f4: 8bfd andi a5,a5,31 + 30007f6: 0ff7f693 andi a3,a5,255 + 30007fa: 67ad lui a5,0xb + 30007fc: 973e add a4,a4,a5 + 30007fe: 431c lw a5,0(a4) + 3000800: 8afd andi a3,a3,31 + 3000802: 06c2 slli a3,a3,0x10 + 3000804: ffe10637 lui a2,0xffe10 + 3000808: 167d addi a2,a2,-1 # ffe0ffff + 300080a: 8ff1 and a5,a5,a2 + 300080c: 8fd5 or a5,a5,a3 + 300080e: c31c sw a5,0(a4) + 3000810: 10100737 lui a4,0x10100 + 3000814: 67ad lui a5,0xb + 3000816: 973e add a4,a4,a5 + 3000818: 431c lw a5,0(a4) + 300081a: 0017e793 ori a5,a5,1 + 300081e: c31c sw a5,0(a4) + 3000820: 10100737 lui a4,0x10100 + 3000824: fc042783 lw a5,-64(s0) + 3000828: 8395 srli a5,a5,0x5 + 300082a: 8bfd andi a5,a5,31 + 300082c: 0ff7f693 andi a3,a5,255 + 3000830: 67ad lui a5,0xb + 3000832: 973e add a4,a4,a5 + 3000834: 435c lw a5,4(a4) + 3000836: 8afd andi a3,a3,31 + 3000838: 06c2 slli a3,a3,0x10 + 300083a: ffe10637 lui a2,0xffe10 + 300083e: 167d addi a2,a2,-1 # ffe0ffff + 3000840: 8ff1 and a5,a5,a2 + 3000842: 8fd5 or a5,a5,a3 + 3000844: c35c sw a5,4(a4) + 3000846: 10100737 lui a4,0x10100 + 300084a: 67ad lui a5,0xb + 300084c: 973e add a4,a4,a5 + 300084e: 435c lw a5,4(a4) + 3000850: 0017e793 ori a5,a5,1 + 3000854: c35c sw a5,4(a4) + 3000856: 10100737 lui a4,0x10100 + 300085a: fc442783 lw a5,-60(s0) + 300085e: 8bfd andi a5,a5,31 + 3000860: 0ff7f693 andi a3,a5,255 + 3000864: 67ad lui a5,0xb + 3000866: 973e add a4,a4,a5 + 3000868: 471c lw a5,8(a4) + 300086a: 8afd andi a3,a3,31 + 300086c: 06c2 slli a3,a3,0x10 + 300086e: ffe10637 lui a2,0xffe10 + 3000872: 167d addi a2,a2,-1 # ffe0ffff + 3000874: 8ff1 and a5,a5,a2 + 3000876: 8fd5 or a5,a5,a3 + 3000878: c71c sw a5,8(a4) + 300087a: 10100737 lui a4,0x10100 + 300087e: fc842783 lw a5,-56(s0) + 3000882: 8bfd andi a5,a5,31 + 3000884: 0ff7f693 andi a3,a5,255 + 3000888: 67ad lui a5,0xb + 300088a: 973e add a4,a4,a5 + 300088c: 471c lw a5,8(a4) + 300088e: 8afd andi a3,a3,31 + 3000890: 06e2 slli a3,a3,0x18 + 3000892: e1000637 lui a2,0xe1000 + 3000896: 167d addi a2,a2,-1 # e0ffffff + 3000898: 8ff1 and a5,a5,a2 + 300089a: 8fd5 or a5,a5,a3 + 300089c: c71c sw a5,8(a4) + 300089e: 10100737 lui a4,0x10100 + 30008a2: fc442783 lw a5,-60(s0) + 30008a6: 8395 srli a5,a5,0x5 + 30008a8: 8bfd andi a5,a5,31 + 30008aa: 0ff7f693 andi a3,a5,255 + 30008ae: 67ad lui a5,0xb + 30008b0: 973e add a4,a4,a5 + 30008b2: 475c lw a5,12(a4) + 30008b4: 8afd andi a3,a3,31 + 30008b6: 06c2 slli a3,a3,0x10 + 30008b8: ffe10637 lui a2,0xffe10 + 30008bc: 167d addi a2,a2,-1 # ffe0ffff + 30008be: 8ff1 and a5,a5,a2 + 30008c0: 8fd5 or a5,a5,a3 + 30008c2: c75c sw a5,12(a4) + 30008c4: 10100737 lui a4,0x10100 + 30008c8: fc842783 lw a5,-56(s0) + 30008cc: 8395 srli a5,a5,0x5 + 30008ce: 8bfd andi a5,a5,31 + 30008d0: 0ff7f693 andi a3,a5,255 + 30008d4: 67ad lui a5,0xb + 30008d6: 973e add a4,a4,a5 + 30008d8: 475c lw a5,12(a4) + 30008da: 8afd andi a3,a3,31 + 30008dc: 06e2 slli a3,a3,0x18 + 30008de: e1000637 lui a2,0xe1000 + 30008e2: 167d addi a2,a2,-1 # e0ffffff + 30008e4: 8ff1 and a5,a5,a2 + 30008e6: 8fd5 or a5,a5,a3 + 30008e8: c75c sw a5,12(a4) + 30008ea: 10100737 lui a4,0x10100 + 30008ee: fc442783 lw a5,-60(s0) + 30008f2: 83a9 srli a5,a5,0xa + 30008f4: 8bfd andi a5,a5,31 + 30008f6: 0ff7f693 andi a3,a5,255 + 30008fa: 67ad lui a5,0xb + 30008fc: 973e add a4,a4,a5 + 30008fe: 4b1c lw a5,16(a4) + 3000900: 8afd andi a3,a3,31 + 3000902: 06c2 slli a3,a3,0x10 + 3000904: ffe10637 lui a2,0xffe10 + 3000908: 167d addi a2,a2,-1 # ffe0ffff + 300090a: 8ff1 and a5,a5,a2 + 300090c: 8fd5 or a5,a5,a3 + 300090e: cb1c sw a5,16(a4) + 3000910: 10100737 lui a4,0x10100 + 3000914: fc842783 lw a5,-56(s0) + 3000918: 83a9 srli a5,a5,0xa + 300091a: 8bfd andi a5,a5,31 + 300091c: 0ff7f693 andi a3,a5,255 + 3000920: 67ad lui a5,0xb + 3000922: 973e add a4,a4,a5 + 3000924: 4b1c lw a5,16(a4) + 3000926: 8afd andi a3,a3,31 + 3000928: 06e2 slli a3,a3,0x18 + 300092a: e1000637 lui a2,0xe1000 + 300092e: 167d addi a2,a2,-1 # e0ffffff + 3000930: 8ff1 and a5,a5,a2 + 3000932: 8fd5 or a5,a5,a3 + 3000934: cb1c sw a5,16(a4) + 3000936: 3e800593 li a1,1000 + 300093a: 4529 li a0,10 + 300093c: 58b000ef jal ra,30016c6 + 3000940: 10100737 lui a4,0x10100 + 3000944: 67ad lui a5,0xb + 3000946: 97ba add a5,a5,a4 + 3000948: 43dc lw a5,4(a5) + 300094a: 83fd srli a5,a5,0x1f + 300094c: 9f81 uxtb a5 + 300094e: fef42623 sw a5,-20(s0) + 3000952: fec42703 lw a4,-20(s0) + 3000956: 4785 li a5,1 + 3000958: 00f71f63 bne a4,a5,3000976 + 300095c: 10100737 lui a4,0x10100 + 3000960: 67ad lui a5,0xb + 3000962: 97ba add a5,a5,a4 + 3000964: 4f98 lw a4,24(a5) + 3000966: 101006b7 lui a3,0x10100 + 300096a: 008007b7 lui a5,0x800 + 300096e: 8f5d or a4,a4,a5 + 3000970: 67ad lui a5,0xb + 3000972: 97b6 add a5,a5,a3 + 3000974: cf98 sw a4,24(a5) + 3000976: e321c783 lbu a5,-462(gp) # 4000118 + 300097a: c399 beqz a5,3000980 + 300097c: 2039 jal ra,300098a + 300097e: 2145 jal ra,3000e1e + 3000980: 0001 nop + 3000982: 40b6 lw ra,76(sp) + 3000984: 4426 lw s0,72(sp) + 3000986: 6161 addi sp,sp,80 + 3000988: 8082 ret + +0300098a : + 300098a: 7119 addi sp,sp,-128 + 300098c: de86 sw ra,124(sp) + 300098e: dca2 sw s0,120(sp) + 3000990: 0100 addi s0,sp,128 + 3000992: fe042623 sw zero,-20(s0) + 3000996: fdc40793 addi a5,s0,-36 + 300099a: 863e mv a2,a5 + 300099c: 45d9 li a1,22 + 300099e: 4501 li a0,0 + 30009a0: 2665 jal ra,3000d48 + 30009a2: fcc40793 addi a5,s0,-52 + 30009a6: 863e mv a2,a5 + 30009a8: 45dd li a1,23 + 30009aa: 4501 li a0,0 + 30009ac: 2e71 jal ra,3000d48 + 30009ae: fdc42783 lw a5,-36(s0) + 30009b2: 873e mv a4,a5 + 30009b4: 6789 lui a5,0x2 + 30009b6: 17fd addi a5,a5,-1 # 1fff + 30009b8: 8ff9 and a5,a5,a4 + 30009ba: 9fa1 uxth a5 + 30009bc: 86be mv a3,a5 + 30009be: d4218713 addi a4,gp,-702 # 4000028 + 30009c2: fec42783 lw a5,-20(s0) + 30009c6: 078a slli a5,a5,0x2 + 30009c8: 97ba add a5,a5,a4 + 30009ca: a396 sh a3,0(a5) + 30009cc: fdc42783 lw a5,-36(s0) + 30009d0: 83b5 srli a5,a5,0xd + 30009d2: 873e mv a4,a5 + 30009d4: 6791 lui a5,0x4 + 30009d6: 17fd addi a5,a5,-1 # 3fff + 30009d8: 8ff9 and a5,a5,a4 + 30009da: 01079693 slli a3,a5,0x10 + 30009de: 82c1 srli a3,a3,0x10 + 30009e0: fec42783 lw a5,-20(s0) + 30009e4: 00178713 addi a4,a5,1 + 30009e8: fee42623 sw a4,-20(s0) + 30009ec: d4218713 addi a4,gp,-702 # 4000028 + 30009f0: 078a slli a5,a5,0x2 + 30009f2: 97ba add a5,a5,a4 + 30009f4: a3b6 sh a3,2(a5) + 30009f6: fcc42783 lw a5,-52(s0) + 30009fa: 873e mv a4,a5 + 30009fc: 6789 lui a5,0x2 + 30009fe: 17fd addi a5,a5,-1 # 1fff + 3000a00: 8ff9 and a5,a5,a4 + 3000a02: 9fa1 uxth a5 + 3000a04: 86be mv a3,a5 + 3000a06: d4218713 addi a4,gp,-702 # 4000028 + 3000a0a: fec42783 lw a5,-20(s0) + 3000a0e: 078a slli a5,a5,0x2 + 3000a10: 97ba add a5,a5,a4 + 3000a12: a396 sh a3,0(a5) + 3000a14: fcc42783 lw a5,-52(s0) + 3000a18: 83b5 srli a5,a5,0xd + 3000a1a: 873e mv a4,a5 + 3000a1c: 6791 lui a5,0x4 + 3000a1e: 17fd addi a5,a5,-1 # 3fff + 3000a20: 8ff9 and a5,a5,a4 + 3000a22: 01079693 slli a3,a5,0x10 + 3000a26: 82c1 srli a3,a3,0x10 + 3000a28: fec42783 lw a5,-20(s0) + 3000a2c: 00178713 addi a4,a5,1 + 3000a30: fee42623 sw a4,-20(s0) + 3000a34: d4218713 addi a4,gp,-702 # 4000028 + 3000a38: 078a slli a5,a5,0x2 + 3000a3a: 97ba add a5,a5,a4 + 3000a3c: a3b6 sh a3,2(a5) + 3000a3e: fe442783 lw a5,-28(s0) + 3000a42: 873e mv a4,a5 + 3000a44: 6789 lui a5,0x2 + 3000a46: 17fd addi a5,a5,-1 # 1fff + 3000a48: 8ff9 and a5,a5,a4 + 3000a4a: 9fa1 uxth a5 + 3000a4c: 86be mv a3,a5 + 3000a4e: d4218713 addi a4,gp,-702 # 4000028 + 3000a52: fec42783 lw a5,-20(s0) + 3000a56: 078a slli a5,a5,0x2 + 3000a58: 97ba add a5,a5,a4 + 3000a5a: a396 sh a3,0(a5) + 3000a5c: fe442783 lw a5,-28(s0) + 3000a60: 83b5 srli a5,a5,0xd + 3000a62: 873e mv a4,a5 + 3000a64: 6791 lui a5,0x4 + 3000a66: 17fd addi a5,a5,-1 # 3fff + 3000a68: 8ff9 and a5,a5,a4 + 3000a6a: 01079693 slli a3,a5,0x10 + 3000a6e: 82c1 srli a3,a3,0x10 + 3000a70: fec42783 lw a5,-20(s0) + 3000a74: 00178713 addi a4,a5,1 + 3000a78: fee42623 sw a4,-20(s0) + 3000a7c: d4218713 addi a4,gp,-702 # 4000028 + 3000a80: 078a slli a5,a5,0x2 + 3000a82: 97ba add a5,a5,a4 + 3000a84: a3b6 sh a3,2(a5) + 3000a86: fd442783 lw a5,-44(s0) + 3000a8a: 873e mv a4,a5 + 3000a8c: 6789 lui a5,0x2 + 3000a8e: 17fd addi a5,a5,-1 # 1fff + 3000a90: 8ff9 and a5,a5,a4 + 3000a92: 9fa1 uxth a5 + 3000a94: 86be mv a3,a5 + 3000a96: d4218713 addi a4,gp,-702 # 4000028 + 3000a9a: fec42783 lw a5,-20(s0) + 3000a9e: 078a slli a5,a5,0x2 + 3000aa0: 97ba add a5,a5,a4 + 3000aa2: a396 sh a3,0(a5) + 3000aa4: fd442783 lw a5,-44(s0) + 3000aa8: 83b5 srli a5,a5,0xd + 3000aaa: 873e mv a4,a5 + 3000aac: 6791 lui a5,0x4 + 3000aae: 17fd addi a5,a5,-1 # 3fff + 3000ab0: 8ff9 and a5,a5,a4 + 3000ab2: 01079693 slli a3,a5,0x10 + 3000ab6: 82c1 srli a3,a3,0x10 + 3000ab8: fec42783 lw a5,-20(s0) + 3000abc: 00178713 addi a4,a5,1 + 3000ac0: fee42623 sw a4,-20(s0) + 3000ac4: d4218713 addi a4,gp,-702 # 4000028 + 3000ac8: 078a slli a5,a5,0x2 + 3000aca: 97ba add a5,a5,a4 + 3000acc: a3b6 sh a3,2(a5) + 3000ace: fbc40793 addi a5,s0,-68 + 3000ad2: 863e mv a2,a5 + 3000ad4: 45e1 li a1,24 + 3000ad6: 4501 li a0,0 + 3000ad8: 2c85 jal ra,3000d48 + 3000ada: fac40793 addi a5,s0,-84 + 3000ade: 863e mv a2,a5 + 3000ae0: 45e5 li a1,25 + 3000ae2: 4501 li a0,0 + 3000ae4: 2495 jal ra,3000d48 + 3000ae6: fbc42783 lw a5,-68(s0) + 3000aea: 873e mv a4,a5 + 3000aec: 6789 lui a5,0x2 + 3000aee: 17fd addi a5,a5,-1 # 1fff + 3000af0: 8ff9 and a5,a5,a4 + 3000af2: 9fa1 uxth a5 + 3000af4: 86be mv a3,a5 + 3000af6: d4218713 addi a4,gp,-702 # 4000028 + 3000afa: fec42783 lw a5,-20(s0) + 3000afe: 078a slli a5,a5,0x2 + 3000b00: 97ba add a5,a5,a4 + 3000b02: a396 sh a3,0(a5) + 3000b04: fbc42783 lw a5,-68(s0) + 3000b08: 83b5 srli a5,a5,0xd + 3000b0a: 873e mv a4,a5 + 3000b0c: 6791 lui a5,0x4 + 3000b0e: 17fd addi a5,a5,-1 # 3fff + 3000b10: 8ff9 and a5,a5,a4 + 3000b12: 01079693 slli a3,a5,0x10 + 3000b16: 82c1 srli a3,a3,0x10 + 3000b18: fec42783 lw a5,-20(s0) + 3000b1c: 00178713 addi a4,a5,1 + 3000b20: fee42623 sw a4,-20(s0) + 3000b24: d4218713 addi a4,gp,-702 # 4000028 + 3000b28: 078a slli a5,a5,0x2 + 3000b2a: 97ba add a5,a5,a4 + 3000b2c: a3b6 sh a3,2(a5) + 3000b2e: fac42783 lw a5,-84(s0) + 3000b32: 873e mv a4,a5 + 3000b34: 6789 lui a5,0x2 + 3000b36: 17fd addi a5,a5,-1 # 1fff + 3000b38: 8ff9 and a5,a5,a4 + 3000b3a: 9fa1 uxth a5 + 3000b3c: 86be mv a3,a5 + 3000b3e: d4218713 addi a4,gp,-702 # 4000028 + 3000b42: fec42783 lw a5,-20(s0) + 3000b46: 078a slli a5,a5,0x2 + 3000b48: 97ba add a5,a5,a4 + 3000b4a: a396 sh a3,0(a5) + 3000b4c: fac42783 lw a5,-84(s0) + 3000b50: 83b5 srli a5,a5,0xd + 3000b52: 873e mv a4,a5 + 3000b54: 6791 lui a5,0x4 + 3000b56: 17fd addi a5,a5,-1 # 3fff + 3000b58: 8ff9 and a5,a5,a4 + 3000b5a: 01079693 slli a3,a5,0x10 + 3000b5e: 82c1 srli a3,a3,0x10 + 3000b60: fec42783 lw a5,-20(s0) + 3000b64: 00178713 addi a4,a5,1 + 3000b68: fee42623 sw a4,-20(s0) + 3000b6c: d4218713 addi a4,gp,-702 # 4000028 + 3000b70: 078a slli a5,a5,0x2 + 3000b72: 97ba add a5,a5,a4 + 3000b74: a3b6 sh a3,2(a5) + 3000b76: fc442783 lw a5,-60(s0) + 3000b7a: 873e mv a4,a5 + 3000b7c: 6789 lui a5,0x2 + 3000b7e: 17fd addi a5,a5,-1 # 1fff + 3000b80: 8ff9 and a5,a5,a4 + 3000b82: 9fa1 uxth a5 + 3000b84: 86be mv a3,a5 + 3000b86: d4218713 addi a4,gp,-702 # 4000028 + 3000b8a: fec42783 lw a5,-20(s0) + 3000b8e: 078a slli a5,a5,0x2 + 3000b90: 97ba add a5,a5,a4 + 3000b92: a396 sh a3,0(a5) + 3000b94: fc442783 lw a5,-60(s0) + 3000b98: 83b5 srli a5,a5,0xd + 3000b9a: 873e mv a4,a5 + 3000b9c: 6791 lui a5,0x4 + 3000b9e: 17fd addi a5,a5,-1 # 3fff + 3000ba0: 8ff9 and a5,a5,a4 + 3000ba2: 01079693 slli a3,a5,0x10 + 3000ba6: 82c1 srli a3,a3,0x10 + 3000ba8: fec42783 lw a5,-20(s0) + 3000bac: 00178713 addi a4,a5,1 + 3000bb0: fee42623 sw a4,-20(s0) + 3000bb4: d4218713 addi a4,gp,-702 # 4000028 + 3000bb8: 078a slli a5,a5,0x2 + 3000bba: 97ba add a5,a5,a4 + 3000bbc: a3b6 sh a3,2(a5) + 3000bbe: fb442783 lw a5,-76(s0) + 3000bc2: 873e mv a4,a5 + 3000bc4: 6789 lui a5,0x2 + 3000bc6: 17fd addi a5,a5,-1 # 1fff + 3000bc8: 8ff9 and a5,a5,a4 + 3000bca: 9fa1 uxth a5 + 3000bcc: 86be mv a3,a5 + 3000bce: d4218713 addi a4,gp,-702 # 4000028 + 3000bd2: fec42783 lw a5,-20(s0) + 3000bd6: 078a slli a5,a5,0x2 + 3000bd8: 97ba add a5,a5,a4 + 3000bda: a396 sh a3,0(a5) + 3000bdc: fb442783 lw a5,-76(s0) + 3000be0: 83b5 srli a5,a5,0xd + 3000be2: 873e mv a4,a5 + 3000be4: 6791 lui a5,0x4 + 3000be6: 17fd addi a5,a5,-1 # 3fff + 3000be8: 8ff9 and a5,a5,a4 + 3000bea: 01079693 slli a3,a5,0x10 + 3000bee: 82c1 srli a3,a3,0x10 + 3000bf0: fec42783 lw a5,-20(s0) + 3000bf4: 00178713 addi a4,a5,1 + 3000bf8: fee42623 sw a4,-20(s0) + 3000bfc: d4218713 addi a4,gp,-702 # 4000028 + 3000c00: 078a slli a5,a5,0x2 + 3000c02: 97ba add a5,a5,a4 + 3000c04: a3b6 sh a3,2(a5) + 3000c06: f9c40793 addi a5,s0,-100 + 3000c0a: 863e mv a2,a5 + 3000c0c: 45e9 li a1,26 + 3000c0e: 4501 li a0,0 + 3000c10: 2a25 jal ra,3000d48 + 3000c12: f8c40793 addi a5,s0,-116 + 3000c16: 863e mv a2,a5 + 3000c18: 45ed li a1,27 + 3000c1a: 4501 li a0,0 + 3000c1c: 2235 jal ra,3000d48 + 3000c1e: f9c42783 lw a5,-100(s0) + 3000c22: 873e mv a4,a5 + 3000c24: 6789 lui a5,0x2 + 3000c26: 17fd addi a5,a5,-1 # 1fff + 3000c28: 8ff9 and a5,a5,a4 + 3000c2a: 9fa1 uxth a5 + 3000c2c: 86be mv a3,a5 + 3000c2e: d4218713 addi a4,gp,-702 # 4000028 + 3000c32: fec42783 lw a5,-20(s0) + 3000c36: 078a slli a5,a5,0x2 + 3000c38: 97ba add a5,a5,a4 + 3000c3a: a396 sh a3,0(a5) + 3000c3c: f9c42783 lw a5,-100(s0) + 3000c40: 83b5 srli a5,a5,0xd + 3000c42: 873e mv a4,a5 + 3000c44: 6791 lui a5,0x4 + 3000c46: 17fd addi a5,a5,-1 # 3fff + 3000c48: 8ff9 and a5,a5,a4 + 3000c4a: 01079693 slli a3,a5,0x10 + 3000c4e: 82c1 srli a3,a3,0x10 + 3000c50: fec42783 lw a5,-20(s0) + 3000c54: 00178713 addi a4,a5,1 + 3000c58: fee42623 sw a4,-20(s0) + 3000c5c: d4218713 addi a4,gp,-702 # 4000028 + 3000c60: 078a slli a5,a5,0x2 + 3000c62: 97ba add a5,a5,a4 + 3000c64: a3b6 sh a3,2(a5) + 3000c66: f8c42783 lw a5,-116(s0) + 3000c6a: 873e mv a4,a5 + 3000c6c: 6789 lui a5,0x2 + 3000c6e: 17fd addi a5,a5,-1 # 1fff + 3000c70: 8ff9 and a5,a5,a4 + 3000c72: 9fa1 uxth a5 + 3000c74: 86be mv a3,a5 + 3000c76: d4218713 addi a4,gp,-702 # 4000028 + 3000c7a: fec42783 lw a5,-20(s0) + 3000c7e: 078a slli a5,a5,0x2 + 3000c80: 97ba add a5,a5,a4 + 3000c82: a396 sh a3,0(a5) + 3000c84: f8c42783 lw a5,-116(s0) + 3000c88: 83b5 srli a5,a5,0xd + 3000c8a: 873e mv a4,a5 + 3000c8c: 6791 lui a5,0x4 + 3000c8e: 17fd addi a5,a5,-1 # 3fff + 3000c90: 8ff9 and a5,a5,a4 + 3000c92: 01079693 slli a3,a5,0x10 + 3000c96: 82c1 srli a3,a3,0x10 + 3000c98: fec42783 lw a5,-20(s0) + 3000c9c: 00178713 addi a4,a5,1 + 3000ca0: fee42623 sw a4,-20(s0) + 3000ca4: d4218713 addi a4,gp,-702 # 4000028 + 3000ca8: 078a slli a5,a5,0x2 + 3000caa: 97ba add a5,a5,a4 + 3000cac: a3b6 sh a3,2(a5) + 3000cae: fa442783 lw a5,-92(s0) + 3000cb2: 873e mv a4,a5 + 3000cb4: 6789 lui a5,0x2 + 3000cb6: 17fd addi a5,a5,-1 # 1fff + 3000cb8: 8ff9 and a5,a5,a4 + 3000cba: 9fa1 uxth a5 + 3000cbc: 86be mv a3,a5 + 3000cbe: d4218713 addi a4,gp,-702 # 4000028 + 3000cc2: fec42783 lw a5,-20(s0) + 3000cc6: 078a slli a5,a5,0x2 + 3000cc8: 97ba add a5,a5,a4 + 3000cca: a396 sh a3,0(a5) + 3000ccc: fa442783 lw a5,-92(s0) + 3000cd0: 83b5 srli a5,a5,0xd + 3000cd2: 873e mv a4,a5 + 3000cd4: 6791 lui a5,0x4 + 3000cd6: 17fd addi a5,a5,-1 # 3fff + 3000cd8: 8ff9 and a5,a5,a4 + 3000cda: 01079693 slli a3,a5,0x10 + 3000cde: 82c1 srli a3,a3,0x10 + 3000ce0: fec42783 lw a5,-20(s0) + 3000ce4: 00178713 addi a4,a5,1 + 3000ce8: fee42623 sw a4,-20(s0) + 3000cec: d4218713 addi a4,gp,-702 # 4000028 + 3000cf0: 078a slli a5,a5,0x2 + 3000cf2: 97ba add a5,a5,a4 + 3000cf4: a3b6 sh a3,2(a5) + 3000cf6: f9442783 lw a5,-108(s0) + 3000cfa: 873e mv a4,a5 + 3000cfc: 6789 lui a5,0x2 + 3000cfe: 17fd addi a5,a5,-1 # 1fff + 3000d00: 8ff9 and a5,a5,a4 + 3000d02: 9fa1 uxth a5 + 3000d04: 86be mv a3,a5 + 3000d06: d4218713 addi a4,gp,-702 # 4000028 + 3000d0a: fec42783 lw a5,-20(s0) + 3000d0e: 078a slli a5,a5,0x2 + 3000d10: 97ba add a5,a5,a4 + 3000d12: a396 sh a3,0(a5) + 3000d14: f9442783 lw a5,-108(s0) + 3000d18: 83b5 srli a5,a5,0xd + 3000d1a: 873e mv a4,a5 + 3000d1c: 6791 lui a5,0x4 + 3000d1e: 17fd addi a5,a5,-1 # 3fff + 3000d20: 8ff9 and a5,a5,a4 + 3000d22: 01079693 slli a3,a5,0x10 + 3000d26: 82c1 srli a3,a3,0x10 + 3000d28: fec42783 lw a5,-20(s0) + 3000d2c: 00178713 addi a4,a5,1 + 3000d30: fee42623 sw a4,-20(s0) + 3000d34: d4218713 addi a4,gp,-702 # 4000028 + 3000d38: 078a slli a5,a5,0x2 + 3000d3a: 97ba add a5,a5,a4 + 3000d3c: a3b6 sh a3,2(a5) + 3000d3e: 0001 nop + 3000d40: 50f6 lw ra,124(sp) + 3000d42: 5466 lw s0,120(sp) + 3000d44: 6109 addi sp,sp,128 + 3000d46: 8082 ret + +03000d48 : + 3000d48: 6d60006f j 300141e + +03000d4c : + 3000d4c: 7179 addi sp,sp,-48 + 3000d4e: d622 sw s0,44(sp) + 3000d50: 1800 addi s0,sp,48 + 3000d52: fca42e23 sw a0,-36(s0) + 3000d56: d4218713 addi a4,gp,-702 # 4000028 + 3000d5a: fdc42783 lw a5,-36(s0) + 3000d5e: 078a slli a5,a5,0x2 + 3000d60: 97ba add a5,a5,a4 + 3000d62: 239e lhu a5,0(a5) + 3000d64: fef42623 sw a5,-20(s0) + 3000d68: fec42783 lw a5,-20(s0) + 3000d6c: d017f753 fcvt.s.wu fa4,a5 + 3000d70: 030047b7 lui a5,0x3004 + 3000d74: 5b87a787 flw fa5,1464(a5) # 30045b8 <__rodata_start> + 3000d78: 18f777d3 fdiv.s fa5,fa4,fa5 + 3000d7c: fef42427 fsw fa5,-24(s0) + 3000d80: fe842787 flw fa5,-24(s0) + 3000d84: 20f78553 fmv.s fa0,fa5 + 3000d88: 5432 lw s0,44(sp) + 3000d8a: 6145 addi sp,sp,48 + 3000d8c: 8082 ret + +03000d8e : + 3000d8e: 7179 addi sp,sp,-48 + 3000d90: d622 sw s0,44(sp) + 3000d92: 1800 addi s0,sp,48 + 3000d94: fca42e23 sw a0,-36(s0) + 3000d98: d4218713 addi a4,gp,-702 # 4000028 + 3000d9c: fdc42783 lw a5,-36(s0) + 3000da0: 078a slli a5,a5,0x2 + 3000da2: 97ba add a5,a5,a4 + 3000da4: 23be lhu a5,2(a5) + 3000da6: fef42423 sw a5,-24(s0) + 3000daa: fe842703 lw a4,-24(s0) + 3000dae: 6789 lui a5,0x2 + 3000db0: 8ff9 and a5,a5,a4 + 3000db2: cf85 beqz a5,3000dea + 3000db4: fe842703 lw a4,-24(s0) + 3000db8: 77f1 lui a5,0xffffc + 3000dba: 8fd9 or a5,a5,a4 + 3000dbc: fef42423 sw a5,-24(s0) + 3000dc0: fe842783 lw a5,-24(s0) + 3000dc4: 40f007b3 neg a5,a5 + 3000dc8: fef42223 sw a5,-28(s0) + 3000dcc: fe442783 lw a5,-28(s0) + 3000dd0: 40f007b3 neg a5,a5 + 3000dd4: d007f753 fcvt.s.w fa4,a5 + 3000dd8: 030047b7 lui a5,0x3004 + 3000ddc: 5bc7a787 flw fa5,1468(a5) # 30045bc <__rodata_start+0x4> + 3000de0: 18f777d3 fdiv.s fa5,fa4,fa5 + 3000de4: fef42627 fsw fa5,-20(s0) + 3000de8: a025 j 3000e10 + 3000dea: fe842703 lw a4,-24(s0) + 3000dee: 6789 lui a5,0x2 + 3000df0: 17fd addi a5,a5,-1 # 1fff + 3000df2: 8ff9 and a5,a5,a4 + 3000df4: fef42423 sw a5,-24(s0) + 3000df8: fe842783 lw a5,-24(s0) + 3000dfc: d017f753 fcvt.s.wu fa4,a5 + 3000e00: 030047b7 lui a5,0x3004 + 3000e04: 5bc7a787 flw fa5,1468(a5) # 30045bc <__rodata_start+0x4> + 3000e08: 18f777d3 fdiv.s fa5,fa4,fa5 + 3000e0c: fef42627 fsw fa5,-20(s0) + 3000e10: fec42787 flw fa5,-20(s0) + 3000e14: 20f78553 fmv.s fa0,fa5 + 3000e18: 5432 lw s0,44(sp) + 3000e1a: 6145 addi sp,sp,48 + 3000e1c: 8082 ret + +03000e1e : + 3000e1e: 7179 addi sp,sp,-48 + 3000e20: d606 sw ra,44(sp) + 3000e22: d422 sw s0,40(sp) + 3000e24: 1800 addi s0,sp,48 + 3000e26: fe042623 sw zero,-20(s0) + 3000e2a: a0f9 j 3000ef8 + 3000e2c: fec42783 lw a5,-20(s0) + 3000e30: 8389 srli a5,a5,0x2 + 3000e32: fef42423 sw a5,-24(s0) + 3000e36: fec42783 lw a5,-20(s0) + 3000e3a: 8b8d andi a5,a5,3 + 3000e3c: fef42223 sw a5,-28(s0) + 3000e40: fe442783 lw a5,-28(s0) + 3000e44: ffe78713 addi a4,a5,-2 + 3000e48: 4785 li a5,1 + 3000e4a: 00e7e463 bltu a5,a4,3000e52 + 3000e4e: 4785 li a5,1 + 3000e50: a011 j 3000e54 + 3000e52: 4789 li a5,2 + 3000e54: fef42023 sw a5,-32(s0) + 3000e58: fec42783 lw a5,-20(s0) + 3000e5c: 8b85 andi a5,a5,1 + 3000e5e: fcf42e23 sw a5,-36(s0) + 3000e62: fec42503 lw a0,-20(s0) + 3000e66: 35dd jal ra,3000d4c + 3000e68: fca42c27 fsw fa0,-40(s0) + 3000e6c: fec42503 lw a0,-20(s0) + 3000e70: 3f39 jal ra,3000d8e + 3000e72: fca42a27 fsw fa0,-44(s0) + 3000e76: 030047b7 lui a5,0x3004 + 3000e7a: 5c07a707 flw fa4,1472(a5) # 30045c0 <__rodata_start+0x8> + 3000e7e: fd442787 flw fa5,-44(s0) + 3000e82: 08f77753 fsub.s fa4,fa4,fa5 + 3000e86: fd842787 flw fa5,-40(s0) + 3000e8a: 10f777d3 fmul.s fa5,fa4,fa5 + 3000e8e: 030047b7 lui a5,0x3004 + 3000e92: 5c07a707 flw fa4,1472(a5) # 30045c0 <__rodata_start+0x8> + 3000e96: 08f777d3 fsub.s fa5,fa4,fa5 + 3000e9a: fcf42827 fsw fa5,-48(s0) + 3000e9e: d7218713 addi a4,gp,-654 # 4000058 + 3000ea2: fe842683 lw a3,-24(s0) + 3000ea6: 478d li a5,3 + 3000ea8: 02f686b3 mul a3,a3,a5 + 3000eac: fe042783 lw a5,-32(s0) + 3000eb0: 97b6 add a5,a5,a3 + 3000eb2: 00179693 slli a3,a5,0x1 + 3000eb6: fdc42783 lw a5,-36(s0) + 3000eba: 97b6 add a5,a5,a3 + 3000ebc: 078e slli a5,a5,0x3 + 3000ebe: 97ba add a5,a5,a4 + 3000ec0: fd842787 flw fa5,-40(s0) + 3000ec4: e39c fsw fa5,0(a5) + 3000ec6: d7218713 addi a4,gp,-654 # 4000058 + 3000eca: fe842683 lw a3,-24(s0) + 3000ece: 478d li a5,3 + 3000ed0: 02f686b3 mul a3,a3,a5 + 3000ed4: fe042783 lw a5,-32(s0) + 3000ed8: 97b6 add a5,a5,a3 + 3000eda: 00179693 slli a3,a5,0x1 + 3000ede: fdc42783 lw a5,-36(s0) + 3000ee2: 97b6 add a5,a5,a3 + 3000ee4: 078e slli a5,a5,0x3 + 3000ee6: 97ba add a5,a5,a4 + 3000ee8: fd042787 flw fa5,-48(s0) + 3000eec: e3dc fsw fa5,4(a5) + 3000eee: fec42783 lw a5,-20(s0) + 3000ef2: 0785 addi a5,a5,1 + 3000ef4: fef42623 sw a5,-20(s0) + 3000ef8: fec42703 lw a4,-20(s0) + 3000efc: 47ad li a5,11 + 3000efe: f2e7f7e3 bgeu a5,a4,3000e2c + 3000f02: 0001 nop + 3000f04: 50b2 lw ra,44(sp) + 3000f06: 5422 lw s0,40(sp) + 3000f08: 6145 addi sp,sp,48 + 3000f0a: 8082 ret + +03000f0c : + 3000f0c: 7139 addi sp,sp,-64 + 3000f0e: de06 sw ra,60(sp) + 3000f10: dc22 sw s0,56(sp) + 3000f12: 0080 addi s0,sp,64 + 3000f14: fd440793 addi a5,s0,-44 + 3000f18: 863e mv a2,a5 + 3000f1a: 4585 li a1,1 + 3000f1c: 4501 li a0,0 + 3000f1e: 2301 jal ra,300141e + 3000f20: fe042783 lw a5,-32(s0) + 3000f24: 7ff7f793 andi a5,a5,2047 + 3000f28: 9fa1 uxth a5 + 3000f2a: fc778793 addi a5,a5,-57 + 3000f2e: fef42623 sw a5,-20(s0) + 3000f32: fe042783 lw a5,-32(s0) + 3000f36: 83ad srli a5,a5,0xb + 3000f38: 7ff7f793 andi a5,a5,2047 + 3000f3c: 9fa1 uxth a5 + 3000f3e: d007f753 fcvt.s.w fa4,a5 + 3000f42: 030047b7 lui a5,0x3004 + 3000f46: 5c47a787 flw fa5,1476(a5) # 30045c4 <__rodata_start+0xc> + 3000f4a: 10f77753 fmul.s fa4,fa4,fa5 + 3000f4e: 030047b7 lui a5,0x3004 + 3000f52: 5c87a787 flw fa5,1480(a5) # 30045c8 <__rodata_start+0x10> + 3000f56: 00f777d3 fadd.s fa5,fa4,fa5 + 3000f5a: fef42427 fsw fa5,-24(s0) + 3000f5e: fec42783 lw a5,-20(s0) + 3000f62: 11178793 addi a5,a5,273 + 3000f66: d017f7d3 fcvt.s.wu fa5,a5 + 3000f6a: fe842707 flw fa4,-24(s0) + 3000f6e: 18f777d3 fdiv.s fa5,fa4,fa5 + 3000f72: fef42227 fsw fa5,-28(s0) + 3000f76: fec42783 lw a5,-20(s0) + 3000f7a: 01079713 slli a4,a5,0x10 + 3000f7e: 8341 srli a4,a4,0x10 + 3000f80: e3618793 addi a5,gp,-458 # 400011c + 3000f84: a79a sh a4,8(a5) + 3000f86: e3618793 addi a5,gp,-458 # 400011c + 3000f8a: fe842787 flw fa5,-24(s0) + 3000f8e: e39c fsw fa5,0(a5) + 3000f90: e3618793 addi a5,gp,-458 # 400011c + 3000f94: fe442787 flw fa5,-28(s0) + 3000f98: e3dc fsw fa5,4(a5) + 3000f9a: fc440793 addi a5,s0,-60 + 3000f9e: 863e mv a2,a5 + 3000fa0: 4585 li a1,1 + 3000fa2: 4501 li a0,0 + 3000fa4: 29ad jal ra,300141e + 3000fa6: fcc42783 lw a5,-52(s0) + 3000faa: 83c9 srli a5,a5,0x12 + 3000fac: 1ff7f793 andi a5,a5,511 + 3000fb0: 9fa1 uxth a5 + 3000fb2: 873e mv a4,a5 + 3000fb4: d2e1af23 sw a4,-706(gp) # 4000024 + 3000fb8: 0001 nop + 3000fba: 50f2 lw ra,60(sp) + 3000fbc: 5462 lw s0,56(sp) + 3000fbe: 6121 addi sp,sp,64 + 3000fc0: 8082 ret + +03000fc2 : + 3000fc2: 7139 addi sp,sp,-64 + 3000fc4: de06 sw ra,60(sp) + 3000fc6: dc22 sw s0,56(sp) + 3000fc8: 0080 addi s0,sp,64 + 3000fca: fca42623 sw a0,-52(s0) + 3000fce: 100007b7 lui a5,0x10000 + 3000fd2: fcf42823 sw a5,-48(s0) + 3000fd6: fcc42783 lw a5,-52(s0) + 3000fda: fef42423 sw a5,-24(s0) + 3000fde: fe842703 lw a4,-24(s0) + 3000fe2: 4785 li a5,1 + 3000fe4: 00f71663 bne a4,a5,3000ff0 + 3000fe8: 3e800593 li a1,1000 + 3000fec: 4529 li a0,10 + 3000fee: 2de1 jal ra,30016c6 + 3000ff0: fd040793 addi a5,s0,-48 + 3000ff4: 853e mv a0,a5 + 3000ff6: 2bd000ef jal ra,3001ab2 + 3000ffa: 0001 nop + 3000ffc: 50f2 lw ra,60(sp) + 3000ffe: 5462 lw s0,56(sp) + 3001000: 6121 addi sp,sp,64 + 3001002: 8082 ret + +03001004 : + 3001004: 1101 addi sp,sp,-32 + 3001006: ce22 sw s0,28(sp) + 3001008: 1000 addi s0,sp,32 + 300100a: fea42623 sw a0,-20(s0) + 300100e: feb42423 sw a1,-24(s0) + 3001012: fec42703 lw a4,-20(s0) + 3001016: fe842783 lw a5,-24(s0) + 300101a: 97ba add a5,a5,a4 + 300101c: fff78713 addi a4,a5,-1 # fffffff + 3001020: fe842783 lw a5,-24(s0) + 3001024: 02f757b3 divu a5,a4,a5 + 3001028: 853e mv a0,a5 + 300102a: 4472 lw s0,28(sp) + 300102c: 6105 addi sp,sp,32 + 300102e: 8082 ret + +03001030 : + 3001030: 7179 addi sp,sp,-48 + 3001032: d606 sw ra,44(sp) + 3001034: d422 sw s0,40(sp) + 3001036: 1800 addi s0,sp,48 + 3001038: fca42e23 sw a0,-36(s0) + 300103c: fdc42783 lw a5,-36(s0) + 3001040: 4705 li a4,1 + 3001042: 02e78063 beq a5,a4,3001062 + 3001046: 4705 li a4,1 + 3001048: 00e7e663 bltu a5,a4,3001054 + 300104c: 4709 li a4,2 + 300104e: 02e78163 beq a5,a4,3001070 + 3001052: a025 j 300107a + 3001054: 017d87b7 lui a5,0x17d8 + 3001058: 84078793 addi a5,a5,-1984 # 17d7840 + 300105c: fef42623 sw a5,-20(s0) + 3001060: a01d j 3001086 + 3001062: 01c9c7b7 lui a5,0x1c9c + 3001066: 38078793 addi a5,a5,896 # 1c9c380 + 300106a: fef42623 sw a5,-20(s0) + 300106e: a821 j 3001086 + 3001070: 2dd000ef jal ra,3001b4c + 3001074: fea42623 sw a0,-20(s0) + 3001078: a039 j 3001086 + 300107a: 67a1 lui a5,0x8 + 300107c: d0078793 addi a5,a5,-768 # 7d00 + 3001080: fef42623 sw a5,-20(s0) + 3001084: 0001 nop + 3001086: fec42783 lw a5,-20(s0) + 300108a: 853e mv a0,a5 + 300108c: 50b2 lw ra,44(sp) + 300108e: 5422 lw s0,40(sp) + 3001090: 6145 addi sp,sp,48 + 3001092: 8082 ret + +03001094 : + 3001094: 7139 addi sp,sp,-64 + 3001096: de06 sw ra,60(sp) + 3001098: dc22 sw s0,56(sp) + 300109a: 0080 addi s0,sp,64 + 300109c: fca42623 sw a0,-52(s0) + 30010a0: 147107b7 lui a5,0x14710 + 30010a4: fef42023 sw a5,-32(s0) + 30010a8: fcc42503 lw a0,-52(s0) + 30010ac: 3751 jal ra,3001030 + 30010ae: fca42e23 sw a0,-36(s0) + 30010b2: fdc42783 lw a5,-36(s0) + 30010b6: 8385 srli a5,a5,0x1 + 30010b8: fcf42c23 sw a5,-40(s0) + 30010bc: fe042703 lw a4,-32(s0) + 30010c0: 6785 lui a5,0x1 + 30010c2: 97ba add a5,a5,a4 + 30010c4: 9407a783 lw a5,-1728(a5) # 940 + 30010c8: fcf42a23 sw a5,-44(s0) + 30010cc: fd442783 lw a5,-44(s0) + 30010d0: 00200737 lui a4,0x200 + 30010d4: 8fd9 or a5,a5,a4 + 30010d6: fcf42a23 sw a5,-44(s0) + 30010da: fd442783 lw a5,-44(s0) + 30010de: 00100737 lui a4,0x100 + 30010e2: 8fd9 or a5,a5,a4 + 30010e4: fcf42a23 sw a5,-44(s0) + 30010e8: 000f47b7 lui a5,0xf4 + 30010ec: 24078593 addi a1,a5,576 # f4240 + 30010f0: fd842503 lw a0,-40(s0) + 30010f4: 3f01 jal ra,3001004 + 30010f6: 87aa mv a5,a0 + 30010f8: 0ff7f713 andi a4,a5,255 + 30010fc: fd442783 lw a5,-44(s0) + 3001100: 0ff77713 andi a4,a4,255 + 3001104: 0732 slli a4,a4,0xc + 3001106: fff016b7 lui a3,0xfff01 + 300110a: 16fd addi a3,a3,-1 # fff00fff + 300110c: 8ff5 and a5,a5,a3 + 300110e: 8fd9 or a5,a5,a4 + 3001110: fcf42a23 sw a5,-44(s0) + 3001114: fdc42783 lw a5,-36(s0) + 3001118: fef42623 sw a5,-20(s0) + 300111c: fe042423 sw zero,-24(s0) + 3001120: a819 j 3001136 + 3001122: fe842783 lw a5,-24(s0) + 3001126: 0785 addi a5,a5,1 + 3001128: fef42423 sw a5,-24(s0) + 300112c: fec42783 lw a5,-20(s0) + 3001130: 8385 srli a5,a5,0x1 + 3001132: fef42623 sw a5,-20(s0) + 3001136: fec42703 lw a4,-20(s0) + 300113a: 004c57b7 lui a5,0x4c5 + 300113e: b4078793 addi a5,a5,-1216 # 4c4b40 + 3001142: fee7e0e3 bltu a5,a4,3001122 + 3001146: fe842783 lw a5,-24(s0) + 300114a: 8b9d andi a5,a5,7 + 300114c: 0ff7f713 andi a4,a5,255 + 3001150: fd442783 lw a5,-44(s0) + 3001154: 8b1d andi a4,a4,7 + 3001156: 0722 slli a4,a4,0x8 + 3001158: 8ff7f793 andi a5,a5,-1793 + 300115c: 8fd9 or a5,a5,a4 + 300115e: fcf42a23 sw a5,-44(s0) + 3001162: 02faf7b7 lui a5,0x2faf + 3001166: 08078593 addi a1,a5,128 # 2faf080 + 300116a: fdc42503 lw a0,-36(s0) + 300116e: 3d59 jal ra,3001004 + 3001170: 87aa mv a5,a0 + 3001172: 9f81 uxtb a5 + 3001174: 17fd addi a5,a5,-1 + 3001176: 9f81 uxtb a5 + 3001178: 8bbd andi a5,a5,15 + 300117a: 0ff7f713 andi a4,a5,255 + 300117e: fd442783 lw a5,-44(s0) + 3001182: 8b3d andi a4,a4,15 + 3001184: 0712 slli a4,a4,0x4 + 3001186: f0f7f793 andi a5,a5,-241 + 300118a: 8fd9 or a5,a5,a4 + 300118c: fcf42a23 sw a5,-44(s0) + 3001190: fd442783 lw a5,-44(s0) + 3001194: 8391 srli a5,a5,0x4 + 3001196: 8bbd andi a5,a5,15 + 3001198: 0ff7f713 andi a4,a5,255 + 300119c: fd442783 lw a5,-44(s0) + 30011a0: 8b3d andi a4,a4,15 + 30011a2: 9bc1 andi a5,a5,-16 + 30011a4: 8fd9 or a5,a5,a4 + 30011a6: fcf42a23 sw a5,-44(s0) + 30011aa: fd442703 lw a4,-44(s0) + 30011ae: fe042683 lw a3,-32(s0) + 30011b2: 6785 lui a5,0x1 + 30011b4: 97b6 add a5,a5,a3 + 30011b6: 94e7a023 sw a4,-1728(a5) # 940 + 30011ba: 009897b7 lui a5,0x989 + 30011be: 68078593 addi a1,a5,1664 # 989680 + 30011c2: fd842503 lw a0,-40(s0) + 30011c6: 3d3d jal ra,3001004 + 30011c8: fea42223 sw a0,-28(s0) + 30011cc: fe442703 lw a4,-28(s0) + 30011d0: 4785 li a5,1 + 30011d2: 00e7e563 bltu a5,a4,30011dc + 30011d6: 4789 li a5,2 + 30011d8: fef42223 sw a5,-28(s0) + 30011dc: fe442783 lw a5,-28(s0) + 30011e0: 8bfd andi a5,a5,31 + 30011e2: 0ff7f693 andi a3,a5,255 + 30011e6: fe042703 lw a4,-32(s0) + 30011ea: 6785 lui a5,0x1 + 30011ec: 973e add a4,a4,a5 + 30011ee: e1072783 lw a5,-496(a4) # ffe10 + 30011f2: 8afd andi a3,a3,31 + 30011f4: 06a2 slli a3,a3,0x8 + 30011f6: 7679 lui a2,0xffffe + 30011f8: 0ff60613 addi a2,a2,255 # ffffe0ff + 30011fc: 8ff1 and a5,a5,a2 + 30011fe: 8fd5 or a5,a5,a3 + 3001200: e0f72823 sw a5,-496(a4) + 3001204: 0001 nop + 3001206: 50f2 lw ra,60(sp) + 3001208: 5462 lw s0,56(sp) + 300120a: 6121 addi sp,sp,64 + 300120c: 8082 ret + +0300120e : + 300120e: 1101 addi sp,sp,-32 + 3001210: ce22 sw s0,28(sp) + 3001212: 1000 addi s0,sp,32 + 3001214: 147107b7 lui a5,0x14710 + 3001218: fef42623 sw a5,-20(s0) + 300121c: 0001 nop + 300121e: fec42703 lw a4,-20(s0) + 3001222: 6785 lui a5,0x1 + 3001224: 97ba add a5,a5,a4 + 3001226: 9407a783 lw a5,-1728(a5) # 940 + 300122a: 83d1 srli a5,a5,0x14 + 300122c: 8b85 andi a5,a5,1 + 300122e: 0ff7f713 andi a4,a5,255 + 3001232: 4785 li a5,1 + 3001234: fef705e3 beq a4,a5,300121e + 3001238: 0001 nop + 300123a: 4472 lw s0,28(sp) + 300123c: 6105 addi sp,sp,32 + 300123e: 8082 ret + +03001240 : + 3001240: 1101 addi sp,sp,-32 + 3001242: ce06 sw ra,28(sp) + 3001244: cc22 sw s0,24(sp) + 3001246: 1000 addi s0,sp,32 + 3001248: fe040793 addi a5,s0,-32 + 300124c: 863e mv a2,a5 + 300124e: 45fd li a1,31 + 3001250: 4501 li a0,0 + 3001252: 22f1 jal ra,300141e + 3001254: e321c783 lbu a5,-462(gp) # 4000118 + 3001258: c7b9 beqz a5,30012a6 + 300125a: 18200737 lui a4,0x18200 + 300125e: fe042783 lw a5,-32(s0) + 3001262: 8bfd andi a5,a5,31 + 3001264: 0ff7f693 andi a3,a5,255 + 3001268: 435c lw a5,4(a4) + 300126a: 8afd andi a3,a3,31 + 300126c: 9b81 andi a5,a5,-32 + 300126e: 8fd5 or a5,a5,a3 + 3001270: c35c sw a5,4(a4) + 3001272: 18201737 lui a4,0x18201 + 3001276: fe042783 lw a5,-32(s0) + 300127a: 83a9 srli a5,a5,0xa + 300127c: 8bfd andi a5,a5,31 + 300127e: 0ff7f693 andi a3,a5,255 + 3001282: 435c lw a5,4(a4) + 3001284: 8afd andi a3,a3,31 + 3001286: 9b81 andi a5,a5,-32 + 3001288: 8fd5 or a5,a5,a3 + 300128a: c35c sw a5,4(a4) + 300128c: 18202737 lui a4,0x18202 + 3001290: fe042783 lw a5,-32(s0) + 3001294: 83d1 srli a5,a5,0x14 + 3001296: 8bfd andi a5,a5,31 + 3001298: 0ff7f693 andi a3,a5,255 + 300129c: 435c lw a5,4(a4) + 300129e: 8afd andi a3,a3,31 + 30012a0: 9b81 andi a5,a5,-32 + 30012a2: 8fd5 or a5,a5,a3 + 30012a4: c35c sw a5,4(a4) + 30012a6: 0001 nop + 30012a8: 40f2 lw ra,28(sp) + 30012aa: 4462 lw s0,24(sp) + 30012ac: 6105 addi sp,sp,32 + 30012ae: 8082 ret + +030012b0 : + 30012b0: 1101 addi sp,sp,-32 + 30012b2: ce06 sw ra,28(sp) + 30012b4: cc22 sw s0,24(sp) + 30012b6: 1000 addi s0,sp,32 + 30012b8: e321c783 lbu a5,-462(gp) # 4000118 + 30012bc: cf85 beqz a5,30012f4 + 30012be: fe040793 addi a5,s0,-32 + 30012c2: 863e mv a2,a5 + 30012c4: 45d5 li a1,21 + 30012c6: 4501 li a0,0 + 30012c8: 2a99 jal ra,300141e + 30012ca: 147e0737 lui a4,0x147e0 + 30012ce: fe042783 lw a5,-32(s0) + 30012d2: 83a9 srli a5,a5,0xa + 30012d4: 8bbd andi a5,a5,15 + 30012d6: 0ff7f693 andi a3,a5,255 + 30012da: 6785 lui a5,0x1 + 30012dc: 973e add a4,a4,a5 + 30012de: a0c72783 lw a5,-1524(a4) # 147dfa0c + 30012e2: 8abd andi a3,a3,15 + 30012e4: 06c2 slli a3,a3,0x10 + 30012e6: fff10637 lui a2,0xfff10 + 30012ea: 167d addi a2,a2,-1 # fff0ffff + 30012ec: 8ff1 and a5,a5,a2 + 30012ee: 8fd5 or a5,a5,a3 + 30012f0: a0f72623 sw a5,-1524(a4) + 30012f4: 0001 nop + 30012f6: 40f2 lw ra,28(sp) + 30012f8: 4462 lw s0,24(sp) + 30012fa: 6105 addi sp,sp,32 + 30012fc: 8082 ret + +030012fe : + 30012fe: 1141 addi sp,sp,-16 + 3001300: c606 sw ra,12(sp) + 3001302: c422 sw s0,8(sp) + 3001304: 0800 addi s0,sp,16 + 3001306: 143017b7 lui a5,0x14301 + 300130a: 02078513 addi a0,a5,32 # 14301020 + 300130e: 0f3000ef jal ra,3001c00 + 3001312: 87aa mv a5,a0 + 3001314: 853e mv a0,a5 + 3001316: 40b2 lw ra,12(sp) + 3001318: 4422 lw s0,8(sp) + 300131a: 0141 addi sp,sp,16 + 300131c: 8082 ret + +0300131e : + 300131e: 1141 addi sp,sp,-16 + 3001320: c622 sw s0,12(sp) + 3001322: 0800 addi s0,sp,16 + 3001324: 143017b7 lui a5,0x14301 + 3001328: 02078793 addi a5,a5,32 # 14301020 + 300132c: 43dc lw a5,4(a5) + 300132e: fff7c793 not a5,a5 + 3001332: 853e mv a0,a5 + 3001334: 4432 lw s0,12(sp) + 3001336: 0141 addi sp,sp,16 + 3001338: 8082 ret + +0300133a : + 300133a: 1141 addi sp,sp,-16 + 300133c: c606 sw ra,12(sp) + 300133e: c422 sw s0,8(sp) + 3001340: 0800 addi s0,sp,16 + 3001342: e4218793 addi a5,gp,-446 # 4000128 + 3001346: 14301737 lui a4,0x14301 + 300134a: 02070713 addi a4,a4,32 # 14301020 + 300134e: c398 sw a4,0(a5) + 3001350: e4218793 addi a5,gp,-446 # 4000128 + 3001354: 577d li a4,-1 + 3001356: cbd8 sw a4,20(a5) + 3001358: e4218793 addi a5,gp,-446 # 4000128 + 300135c: 577d li a4,-1 + 300135e: cf98 sw a4,24(a5) + 3001360: e4218793 addi a5,gp,-446 # 4000128 + 3001364: 4705 li a4,1 + 3001366: c798 sw a4,8(a5) + 3001368: e4218793 addi a5,gp,-446 # 4000128 + 300136c: 0007a623 sw zero,12(a5) + 3001370: e4218793 addi a5,gp,-446 # 4000128 + 3001374: 4705 li a4,1 + 3001376: cb98 sw a4,16(a5) + 3001378: e4218793 addi a5,gp,-446 # 4000128 + 300137c: 00078e23 sb zero,28(a5) + 3001380: e4218513 addi a0,gp,-446 # 4000128 + 3001384: 217020ef jal ra,3003d9a + 3001388: e4218513 addi a0,gp,-446 # 4000128 + 300138c: 33f020ef jal ra,3003eca + 3001390: 0001 nop + 3001392: 40b2 lw ra,12(sp) + 3001394: 4422 lw s0,8(sp) + 3001396: 0141 addi sp,sp,16 + 3001398: 8082 ret + +0300139a : + 300139a: 1101 addi sp,sp,-32 + 300139c: ce22 sw s0,28(sp) + 300139e: 1000 addi s0,sp,32 + 30013a0: fea42623 sw a0,-20(s0) + 30013a4: fec42783 lw a5,-20(s0) + 30013a8: 1007a783 lw a5,256(a5) + 30013ac: 83c1 srli a5,a5,0x10 + 30013ae: 8b85 andi a5,a5,1 + 30013b0: 9f81 uxtb a5 + 30013b2: e38d bnez a5,30013d4 + 30013b4: fec42783 lw a5,-20(s0) + 30013b8: 1007a783 lw a5,256(a5) + 30013bc: 83cd srli a5,a5,0x13 + 30013be: 8b85 andi a5,a5,1 + 30013c0: 9f81 uxtb a5 + 30013c2: eb89 bnez a5,30013d4 + 30013c4: fec42783 lw a5,-20(s0) + 30013c8: 1007a783 lw a5,256(a5) + 30013cc: 83d1 srli a5,a5,0x14 + 30013ce: 8b85 andi a5,a5,1 + 30013d0: 9f81 uxtb a5 + 30013d2: c3a9 beqz a5,3001414 + 30013d4: fec42703 lw a4,-20(s0) + 30013d8: 10c72783 lw a5,268(a4) + 30013dc: 000806b7 lui a3,0x80 + 30013e0: 8fd5 or a5,a5,a3 + 30013e2: 10f72623 sw a5,268(a4) + 30013e6: fec42703 lw a4,-20(s0) + 30013ea: 10c72783 lw a5,268(a4) + 30013ee: 66c1 lui a3,0x10 + 30013f0: 8fd5 or a5,a5,a3 + 30013f2: 10f72623 sw a5,268(a4) + 30013f6: fec42703 lw a4,-20(s0) + 30013fa: 10c72783 lw a5,268(a4) + 30013fe: 001006b7 lui a3,0x100 + 3001402: 8fd5 or a5,a5,a3 + 3001404: 10f72623 sw a5,268(a4) + 3001408: fec42783 lw a5,-20(s0) + 300140c: 2007a023 sw zero,512(a5) + 3001410: 4785 li a5,1 + 3001412: a011 j 3001416 + 3001414: 4781 li a5,0 + 3001416: 853e mv a0,a5 + 3001418: 4472 lw s0,28(sp) + 300141a: 6105 addi sp,sp,32 + 300141c: 8082 ret + +0300141e : + 300141e: 7179 addi sp,sp,-48 + 3001420: d606 sw ra,44(sp) + 3001422: d422 sw s0,40(sp) + 3001424: 1800 addi s0,sp,48 + 3001426: fca42e23 sw a0,-36(s0) + 300142a: fcb42c23 sw a1,-40(s0) + 300142e: fcc42a23 sw a2,-44(s0) + 3001432: 147107b7 lui a5,0x14710 + 3001436: fef42423 sw a5,-24(s0) + 300143a: fd442783 lw a5,-44(s0) + 300143e: e399 bnez a5,3001444 + 3001440: 4785 li a5,1 + 3001442: aa1d j 3001578 + 3001444: fdc42703 lw a4,-36(s0) + 3001448: 4785 li a5,1 + 300144a: 00e7e863 bltu a5,a4,300145a + 300144e: fd842703 lw a4,-40(s0) + 3001452: 1ff00793 li a5,511 + 3001456: 00e7f463 bgeu a5,a4,300145e + 300145a: 4785 li a5,1 + 300145c: aa31 j 3001578 + 300145e: fe842783 lw a5,-24(s0) + 3001462: 439c lw a5,0(a5) + 3001464: 8b85 andi a5,a5,1 + 3001466: 9f81 uxtb a5 + 3001468: c399 beqz a5,300146e + 300146a: 4785 li a5,1 + 300146c: a231 j 3001578 + 300146e: fe842783 lw a5,-24(s0) + 3001472: fedcc737 lui a4,0xfedcc + 3001476: a9870713 addi a4,a4,-1384 # fedcba98 + 300147a: 20e7a023 sw a4,512(a5) # 14710200 + 300147e: fdc42783 lw a5,-36(s0) + 3001482: e781 bnez a5,300148a + 3001484: 008007b7 lui a5,0x800 + 3001488: a019 j 300148e + 300148a: 008027b7 lui a5,0x802 + 300148e: fef42223 sw a5,-28(s0) + 3001492: fd842783 lw a5,-40(s0) + 3001496: 0792 slli a5,a5,0x4 + 3001498: fe442703 lw a4,-28(s0) + 300149c: 97ba add a5,a5,a4 + 300149e: fef42223 sw a5,-28(s0) + 30014a2: fe442783 lw a5,-28(s0) + 30014a6: 0027d713 srli a4,a5,0x2 + 30014aa: 004007b7 lui a5,0x400 + 30014ae: 17fd addi a5,a5,-1 # 3fffff + 30014b0: 00f77633 and a2,a4,a5 + 30014b4: fe842703 lw a4,-24(s0) + 30014b8: 435c lw a5,4(a4) + 30014ba: 004006b7 lui a3,0x400 + 30014be: 16fd addi a3,a3,-1 # 3fffff + 30014c0: 8ef1 and a3,a3,a2 + 30014c2: 068a slli a3,a3,0x2 + 30014c4: ff000637 lui a2,0xff000 + 30014c8: 060d addi a2,a2,3 # ff000003 + 30014ca: 8ff1 and a5,a5,a2 + 30014cc: 8fd5 or a5,a5,a3 + 30014ce: c35c sw a5,4(a4) + 30014d0: fe842703 lw a4,-24(s0) + 30014d4: 431c lw a5,0(a4) + 30014d6: 8ff7f793 andi a5,a5,-1793 + 30014da: 1007e793 ori a5,a5,256 + 30014de: c31c sw a5,0(a4) + 30014e0: fe842703 lw a4,-24(s0) + 30014e4: 431c lw a5,0(a4) + 30014e6: d00006b7 lui a3,0xd0000 + 30014ea: 16fd addi a3,a3,-1 # cfffffff + 30014ec: 8efd and a3,a3,a5 + 30014ee: 100007b7 lui a5,0x10000 + 30014f2: 8fd5 or a5,a5,a3 + 30014f4: c31c sw a5,0(a4) + 30014f6: fe842703 lw a4,-24(s0) + 30014fa: 431c lw a5,0(a4) + 30014fc: 0017e793 ori a5,a5,1 + 3001500: c31c sw a5,0(a4) + 3001502: 0001 nop + 3001504: fe842783 lw a5,-24(s0) + 3001508: 439c lw a5,0(a5) + 300150a: 8b85 andi a5,a5,1 + 300150c: 9f81 uxtb a5 + 300150e: fbfd bnez a5,3001504 + 3001510: 0001 nop + 3001512: fe842783 lw a5,-24(s0) + 3001516: 439c lw a5,0(a5) + 3001518: 8399 srli a5,a5,0x6 + 300151a: 8b8d andi a5,a5,3 + 300151c: 9f81 uxtb a5 + 300151e: fbf5 bnez a5,3001512 + 3001520: fe842503 lw a0,-24(s0) + 3001524: 3d9d jal ra,300139a + 3001526: 87aa mv a5,a0 + 3001528: c399 beqz a5,300152e + 300152a: 4785 li a5,1 + 300152c: a0b1 j 3001578 + 300152e: fe042623 sw zero,-20(s0) + 3001532: a00d j 3001554 + 3001534: fe842783 lw a5,-24(s0) + 3001538: 6007a703 lw a4,1536(a5) # 10000600 + 300153c: fd442683 lw a3,-44(s0) + 3001540: fec42783 lw a5,-20(s0) + 3001544: 078a slli a5,a5,0x2 + 3001546: 97b6 add a5,a5,a3 + 3001548: c398 sw a4,0(a5) + 300154a: fec42783 lw a5,-20(s0) + 300154e: 0785 addi a5,a5,1 + 3001550: fef42623 sw a5,-20(s0) + 3001554: fec42703 lw a4,-20(s0) + 3001558: 478d li a5,3 + 300155a: fce7fde3 bgeu a5,a4,3001534 + 300155e: fe842703 lw a4,-24(s0) + 3001562: 10c72783 lw a5,268(a4) + 3001566: 0107e793 ori a5,a5,16 + 300156a: 10f72623 sw a5,268(a4) + 300156e: fe842783 lw a5,-24(s0) + 3001572: 2007a023 sw zero,512(a5) + 3001576: 4781 li a5,0 + 3001578: 853e mv a0,a5 + 300157a: 50b2 lw ra,44(sp) + 300157c: 5422 lw s0,40(sp) + 300157e: 6145 addi sp,sp,48 + 3001580: 8082 ret + +03001582 : + 3001582: 7179 addi sp,sp,-48 + 3001584: d622 sw s0,44(sp) + 3001586: 1800 addi s0,sp,48 + 3001588: fca42e23 sw a0,-36(s0) + 300158c: fe042623 sw zero,-20(s0) + 3001590: a081 j 30015d0 + 3001592: 030047b7 lui a5,0x3004 + 3001596: 5cc78713 addi a4,a5,1484 # 30045cc + 300159a: fec42683 lw a3,-20(s0) + 300159e: 47b1 li a5,12 + 30015a0: 02f687b3 mul a5,a3,a5 + 30015a4: 97ba add a5,a5,a4 + 30015a6: 439c lw a5,0(a5) + 30015a8: fdc42703 lw a4,-36(s0) + 30015ac: 00f71d63 bne a4,a5,30015c6 + 30015b0: fec42703 lw a4,-20(s0) + 30015b4: 47b1 li a5,12 + 30015b6: 02f70733 mul a4,a4,a5 + 30015ba: 030047b7 lui a5,0x3004 + 30015be: 5cc78793 addi a5,a5,1484 # 30045cc + 30015c2: 97ba add a5,a5,a4 + 30015c4: a829 j 30015de + 30015c6: fec42783 lw a5,-20(s0) + 30015ca: 0785 addi a5,a5,1 + 30015cc: fef42623 sw a5,-20(s0) + 30015d0: fec42703 lw a4,-20(s0) + 30015d4: 03200793 li a5,50 + 30015d8: fae7fde3 bgeu a5,a4,3001592 + 30015dc: 4781 li a5,0 + 30015de: 853e mv a0,a5 + 30015e0: 5432 lw s0,44(sp) + 30015e2: 6145 addi sp,sp,48 + 30015e4: 8082 ret + +030015e6 : + 30015e6: 1101 addi sp,sp,-32 + 30015e8: ce22 sw s0,28(sp) + 30015ea: 1000 addi s0,sp,32 + 30015ec: fea42623 sw a0,-20(s0) + 30015f0: feb42423 sw a1,-24(s0) + 30015f4: 0001 nop + 30015f6: 4472 lw s0,28(sp) + 30015f8: 6105 addi sp,sp,32 + 30015fa: 8082 ret + +030015fc : + 30015fc: 7179 addi sp,sp,-48 + 30015fe: d606 sw ra,44(sp) + 3001600: d422 sw s0,40(sp) + 3001602: 1800 addi s0,sp,48 + 3001604: fca42e23 sw a0,-36(s0) + 3001608: 3b19 jal ra,300131e + 300160a: fea42623 sw a0,-20(s0) + 300160e: 39c5 jal ra,30012fe + 3001610: 872a mv a4,a0 + 3001612: 000f47b7 lui a5,0xf4 + 3001616: 24078793 addi a5,a5,576 # f4240 + 300161a: 02f757b3 divu a5,a4,a5 + 300161e: fdc42703 lw a4,-36(s0) + 3001622: 02f707b3 mul a5,a4,a5 + 3001626: fef42423 sw a5,-24(s0) + 300162a: 39d5 jal ra,300131e + 300162c: fea42223 sw a0,-28(s0) + 3001630: fe442703 lw a4,-28(s0) + 3001634: fec42783 lw a5,-20(s0) + 3001638: 40f707b3 sub a5,a4,a5 + 300163c: fef42023 sw a5,-32(s0) + 3001640: fe042703 lw a4,-32(s0) + 3001644: fe842783 lw a5,-24(s0) + 3001648: fef761e3 bltu a4,a5,300162a + 300164c: 0001 nop + 300164e: 50b2 lw ra,44(sp) + 3001650: 5422 lw s0,40(sp) + 3001652: 6145 addi sp,sp,48 + 3001654: 8082 ret + +03001656 : + 3001656: 7179 addi sp,sp,-48 + 3001658: d606 sw ra,44(sp) + 300165a: d422 sw s0,40(sp) + 300165c: 1800 addi s0,sp,48 + 300165e: fca42e23 sw a0,-36(s0) + 3001662: fe042623 sw zero,-20(s0) + 3001666: a809 j 3001678 + 3001668: 3e800513 li a0,1000 + 300166c: 3f41 jal ra,30015fc + 300166e: fec42783 lw a5,-20(s0) + 3001672: 0785 addi a5,a5,1 + 3001674: fef42623 sw a5,-20(s0) + 3001678: fec42703 lw a4,-20(s0) + 300167c: fdc42783 lw a5,-36(s0) + 3001680: fef764e3 bltu a4,a5,3001668 + 3001684: 0001 nop + 3001686: 50b2 lw ra,44(sp) + 3001688: 5422 lw s0,40(sp) + 300168a: 6145 addi sp,sp,48 + 300168c: 8082 ret + +0300168e : + 300168e: 7179 addi sp,sp,-48 + 3001690: d606 sw ra,44(sp) + 3001692: d422 sw s0,40(sp) + 3001694: 1800 addi s0,sp,48 + 3001696: fca42e23 sw a0,-36(s0) + 300169a: fe042623 sw zero,-20(s0) + 300169e: a809 j 30016b0 + 30016a0: 3e800513 li a0,1000 + 30016a4: 3f4d jal ra,3001656 + 30016a6: fec42783 lw a5,-20(s0) + 30016aa: 0785 addi a5,a5,1 + 30016ac: fef42623 sw a5,-20(s0) + 30016b0: fec42703 lw a4,-20(s0) + 30016b4: fdc42783 lw a5,-36(s0) + 30016b8: fef764e3 bltu a4,a5,30016a0 + 30016bc: 0001 nop + 30016be: 50b2 lw ra,44(sp) + 30016c0: 5422 lw s0,40(sp) + 30016c2: 6145 addi sp,sp,48 + 30016c4: 8082 ret + +030016c6 : + 30016c6: 1101 addi sp,sp,-32 + 30016c8: ce06 sw ra,28(sp) + 30016ca: cc22 sw s0,24(sp) + 30016cc: 1000 addi s0,sp,32 + 30016ce: fea42623 sw a0,-20(s0) + 30016d2: feb42423 sw a1,-24(s0) + 30016d6: fe842783 lw a5,-24(s0) + 30016da: 3e800713 li a4,1000 + 30016de: 02e78063 beq a5,a4,30016fe + 30016e2: 000f4737 lui a4,0xf4 + 30016e6: 24070713 addi a4,a4,576 # f4240 + 30016ea: 00e78e63 beq a5,a4,3001706 + 30016ee: 4705 li a4,1 + 30016f0: 00e78363 beq a5,a4,30016f6 + 30016f4: a829 j 300170e + 30016f6: fec42503 lw a0,-20(s0) + 30016fa: 3f51 jal ra,300168e + 30016fc: a809 j 300170e + 30016fe: fec42503 lw a0,-20(s0) + 3001702: 3f91 jal ra,3001656 + 3001704: a029 j 300170e + 3001706: fec42503 lw a0,-20(s0) + 300170a: 3dcd jal ra,30015fc + 300170c: 0001 nop + 300170e: 0001 nop + 3001710: 40f2 lw ra,28(sp) + 3001712: 4462 lw s0,24(sp) + 3001714: 6105 addi sp,sp,32 + 3001716: 8082 ret + +03001718 : + 3001718: 1101 addi sp,sp,-32 + 300171a: ce22 sw s0,28(sp) + 300171c: 1000 addi s0,sp,32 + 300171e: fea42623 sw a0,-20(s0) + 3001722: 0ff0000f fence + 3001726: fec42783 lw a5,-20(s0) + 300172a: 82be mv t0,a5 + 300172c: bf029073 csrw 0xbf0,t0 + 3001730: 0001 nop + 3001732: 4472 lw s0,28(sp) + 3001734: 6105 addi sp,sp,32 + 3001736: 8082 ret + +03001738 : + 3001738: 1101 addi sp,sp,-32 + 300173a: ce06 sw ra,28(sp) + 300173c: cc22 sw s0,24(sp) + 300173e: 1000 addi s0,sp,32 + 3001740: fea42623 sw a0,-20(s0) + 3001744: e6618713 addi a4,gp,-410 # 400014c + 3001748: fec42783 lw a5,-20(s0) + 300174c: 078e slli a5,a5,0x3 + 300174e: 97ba add a5,a5,a4 + 3001750: 4394 lw a3,0(a5) + 3001752: e6618713 addi a4,gp,-410 # 400014c + 3001756: fec42783 lw a5,-20(s0) + 300175a: 078e slli a5,a5,0x3 + 300175c: 97ba add a5,a5,a4 + 300175e: 43dc lw a5,4(a5) + 3001760: 853e mv a0,a5 + 3001762: 9682 jalr a3 + 3001764: fec42503 lw a0,-20(s0) + 3001768: 3f45 jal ra,3001718 + 300176a: 0001 nop + 300176c: 40f2 lw ra,28(sp) + 300176e: 4462 lw s0,24(sp) + 3001770: 6105 addi sp,sp,32 + 3001772: 8082 ret + +03001774 : + 3001774: 1101 addi sp,sp,-32 + 3001776: ce22 sw s0,28(sp) + 3001778: 1000 addi s0,sp,32 + 300177a: fe042623 sw zero,-20(s0) + 300177e: a80d j 30017b0 + 3001780: e6618713 addi a4,gp,-410 # 400014c + 3001784: fec42783 lw a5,-20(s0) + 3001788: 078e slli a5,a5,0x3 + 300178a: 97ba add a5,a5,a4 + 300178c: 03002737 lui a4,0x3002 + 3001790: 83670713 addi a4,a4,-1994 # 3001836 + 3001794: c398 sw a4,0(a5) + 3001796: e6618713 addi a4,gp,-410 # 400014c + 300179a: fec42783 lw a5,-20(s0) + 300179e: 078e slli a5,a5,0x3 + 30017a0: 97ba add a5,a5,a4 + 30017a2: 0007a223 sw zero,4(a5) + 30017a6: fec42783 lw a5,-20(s0) + 30017aa: 0785 addi a5,a5,1 + 30017ac: fef42623 sw a5,-20(s0) + 30017b0: fec42703 lw a4,-20(s0) + 30017b4: 07400793 li a5,116 + 30017b8: fce7f4e3 bgeu a5,a4,3001780 + 30017bc: 0001 nop + 30017be: 4472 lw s0,28(sp) + 30017c0: 6105 addi sp,sp,32 + 30017c2: 8082 ret + +030017c4 : + 30017c4: 1101 addi sp,sp,-32 + 30017c6: ce22 sw s0,28(sp) + 30017c8: 1000 addi s0,sp,32 + 30017ca: fea42623 sw a0,-20(s0) + 30017ce: 0001 nop + 30017d0: 4472 lw s0,28(sp) + 30017d2: 6105 addi sp,sp,32 + 30017d4: 8082 ret + +030017d6 : + 30017d6: 1141 addi sp,sp,-16 + 30017d8: c622 sw s0,12(sp) + 30017da: 0800 addi s0,sp,16 + 30017dc: 0001 nop + 30017de: 4432 lw s0,12(sp) + 30017e0: 0141 addi sp,sp,16 + 30017e2: 8082 ret + +030017e4 : + 30017e4: 1101 addi sp,sp,-32 + 30017e6: ce06 sw ra,28(sp) + 30017e8: cc22 sw s0,24(sp) + 30017ea: 1000 addi s0,sp,32 + 30017ec: fea42623 sw a0,-20(s0) + 30017f0: fec42503 lw a0,-20(s0) + 30017f4: 3fc1 jal ra,30017c4 + 30017f6: 37c5 jal ra,30017d6 + 30017f8: 0001 nop + 30017fa: 40f2 lw ra,28(sp) + 30017fc: 4462 lw s0,24(sp) + 30017fe: 6105 addi sp,sp,32 + 3001800: 8082 ret + +03001802 : + 3001802: 1101 addi sp,sp,-32 + 3001804: ce06 sw ra,28(sp) + 3001806: cc22 sw s0,24(sp) + 3001808: 1000 addi s0,sp,32 + 300180a: fea42623 sw a0,-20(s0) + 300180e: fec42783 lw a5,-20(s0) + 3001812: eb89 bnez a5,3001824 + 3001814: 12d00593 li a1,301 + 3001818: 030057b7 lui a5,0x3005 + 300181c: 83078513 addi a0,a5,-2000 # 3004830 + 3001820: 33d9 jal ra,30015e6 + 3001822: a001 j 3001822 + 3001824: fec42503 lw a0,-20(s0) + 3001828: 3f71 jal ra,30017c4 + 300182a: 3775 jal ra,30017d6 + 300182c: 0001 nop + 300182e: 40f2 lw ra,28(sp) + 3001830: 4462 lw s0,24(sp) + 3001832: 6105 addi sp,sp,32 + 3001834: 8082 ret + +03001836 : + 3001836: 1101 addi sp,sp,-32 + 3001838: ce22 sw s0,28(sp) + 300183a: 1000 addi s0,sp,32 + 300183c: fea42623 sw a0,-20(s0) + 3001840: 0001 nop + 3001842: 4472 lw s0,28(sp) + 3001844: 6105 addi sp,sp,32 + 3001846: 8082 ret + +03001848 : + 3001848: 1141 addi sp,sp,-16 + 300184a: c622 sw s0,12(sp) + 300184c: 0800 addi s0,sp,16 + 300184e: 101007b7 lui a5,0x10100 + 3001852: 43f8 lw a4,68(a5) + 3001854: 67c1 lui a5,0x10 + 3001856: 17f9 addi a5,a5,-2 # fffe + 3001858: 00f776b3 and a3,a4,a5 + 300185c: 101007b7 lui a5,0x10100 + 3001860: ea510737 lui a4,0xea510 + 3001864: 9736 add a4,a4,a3 + 3001866: c3f8 sw a4,68(a5) + 3001868: 0001 nop + 300186a: 4432 lw s0,12(sp) + 300186c: 0141 addi sp,sp,16 + 300186e: 8082 ret + +03001870 : + 3001870: 1141 addi sp,sp,-16 + 3001872: c622 sw s0,12(sp) + 3001874: 0800 addi s0,sp,16 + 3001876: 101007b7 lui a5,0x10100 + 300187a: 43f8 lw a4,68(a5) + 300187c: 67c1 lui a5,0x10 + 300187e: 17fd addi a5,a5,-1 # ffff + 3001880: 8ff9 and a5,a5,a4 + 3001882: 0017e693 ori a3,a5,1 + 3001886: 101007b7 lui a5,0x10100 + 300188a: ea510737 lui a4,0xea510 + 300188e: 9736 add a4,a4,a3 + 3001890: c3f8 sw a4,68(a5) + 3001892: 0001 nop + 3001894: 4432 lw s0,12(sp) + 3001896: 0141 addi sp,sp,16 + 3001898: 8082 ret + +0300189a : + 300189a: 7179 addi sp,sp,-48 + 300189c: d622 sw s0,44(sp) + 300189e: 1800 addi s0,sp,48 + 30018a0: fca42e23 sw a0,-36(s0) + 30018a4: fcb42c23 sw a1,-40(s0) + 30018a8: fdc42783 lw a5,-36(s0) + 30018ac: fef42623 sw a5,-20(s0) + 30018b0: fd842783 lw a5,-40(s0) + 30018b4: cb89 beqz a5,30018c6 + 30018b6: fec42703 lw a4,-20(s0) + 30018ba: fd842783 lw a5,-40(s0) + 30018be: 02f757b3 divu a5,a4,a5 + 30018c2: fef42623 sw a5,-20(s0) + 30018c6: fec42703 lw a4,-20(s0) + 30018ca: 003d17b7 lui a5,0x3d1 + 30018ce: 8ff78793 addi a5,a5,-1793 # 3d08ff + 30018d2: 00e7fc63 bgeu a5,a4,30018ea + 30018d6: fec42703 lw a4,-20(s0) + 30018da: 007277b7 lui a5,0x727 + 30018de: 0e078793 addi a5,a5,224 # 7270e0 + 30018e2: 00e7e463 bltu a5,a4,30018ea + 30018e6: 4785 li a5,1 + 30018e8: a011 j 30018ec + 30018ea: 4781 li a5,0 + 30018ec: 8b85 andi a5,a5,1 + 30018ee: 9f81 uxtb a5 + 30018f0: 853e mv a0,a5 + 30018f2: 5432 lw s0,44(sp) + 30018f4: 6145 addi sp,sp,48 + 30018f6: 8082 ret + +030018f8 : + 30018f8: 7179 addi sp,sp,-48 + 30018fa: d622 sw s0,44(sp) + 30018fc: 1800 addi s0,sp,48 + 30018fe: fca42e23 sw a0,-36(s0) + 3001902: fcb42c23 sw a1,-40(s0) + 3001906: fdc42703 lw a4,-36(s0) + 300190a: fd842783 lw a5,-40(s0) + 300190e: 02f707b3 mul a5,a4,a5 + 3001912: fef42623 sw a5,-20(s0) + 3001916: fec42703 lw a4,-20(s0) + 300191a: 05f5e7b7 lui a5,0x5f5e + 300191e: 0ff78793 addi a5,a5,255 # 5f5e0ff + 3001922: 00e7fc63 bgeu a5,a4,300193a + 3001926: fec42703 lw a4,-20(s0) + 300192a: 0bebc7b7 lui a5,0xbebc + 300192e: 20078793 addi a5,a5,512 # bebc200 + 3001932: 00e7e463 bltu a5,a4,300193a + 3001936: 4785 li a5,1 + 3001938: a011 j 300193c + 300193a: 4781 li a5,0 + 300193c: 8b85 andi a5,a5,1 + 300193e: 9f81 uxtb a5 + 3001940: 853e mv a0,a5 + 3001942: 5432 lw s0,44(sp) + 3001944: 6145 addi sp,sp,48 + 3001946: 8082 ret + +03001948 : + 3001948: 7179 addi sp,sp,-48 + 300194a: d622 sw s0,44(sp) + 300194c: 1800 addi s0,sp,48 + 300194e: fca42e23 sw a0,-36(s0) + 3001952: fcb42c23 sw a1,-40(s0) + 3001956: fdc42783 lw a5,-36(s0) + 300195a: fef42623 sw a5,-20(s0) + 300195e: fd842783 lw a5,-40(s0) + 3001962: cb89 beqz a5,3001974 + 3001964: fec42703 lw a4,-20(s0) + 3001968: fd842783 lw a5,-40(s0) + 300196c: 02f757b3 divu a5,a4,a5 + 3001970: fef42623 sw a5,-20(s0) + 3001974: fec42703 lw a4,-20(s0) + 3001978: 002fb7b7 lui a5,0x2fb + 300197c: f0778793 addi a5,a5,-249 # 2faf07 + 3001980: 00e7fc63 bgeu a5,a4,3001998 + 3001984: fec42703 lw a4,-20(s0) + 3001988: 0bebc7b7 lui a5,0xbebc + 300198c: 20078793 addi a5,a5,512 # bebc200 + 3001990: 00e7e463 bltu a5,a4,3001998 + 3001994: 4785 li a5,1 + 3001996: a011 j 300199a + 3001998: 4781 li a5,0 + 300199a: 8b85 andi a5,a5,1 + 300199c: 9f81 uxtb a5 + 300199e: 853e mv a0,a5 + 30019a0: 5432 lw s0,44(sp) + 30019a2: 6145 addi sp,sp,48 + 30019a4: 8082 ret + +030019a6 : + 30019a6: 1101 addi sp,sp,-32 + 30019a8: ce22 sw s0,28(sp) + 30019aa: 1000 addi s0,sp,32 + 30019ac: fea42623 sw a0,-20(s0) + 30019b0: feb42423 sw a1,-24(s0) + 30019b4: fe842783 lw a5,-24(s0) + 30019b8: 8b8d andi a5,a5,3 + 30019ba: 0ff7f693 andi a3,a5,255 + 30019be: fec42703 lw a4,-20(s0) + 30019c2: 4f5c lw a5,28(a4) + 30019c4: 8a8d andi a3,a3,3 + 30019c6: 9bf1 andi a5,a5,-4 + 30019c8: 8fd5 or a5,a5,a3 + 30019ca: cf5c sw a5,28(a4) + 30019cc: 0001 nop + 30019ce: 4472 lw s0,28(sp) + 30019d0: 6105 addi sp,sp,32 + 30019d2: 8082 ret + +030019d4 : + 30019d4: 7179 addi sp,sp,-48 + 30019d6: d606 sw ra,44(sp) + 30019d8: d422 sw s0,40(sp) + 30019da: 1800 addi s0,sp,48 + 30019dc: fca42e23 sw a0,-36(s0) + 30019e0: fdc42783 lw a5,-36(s0) + 30019e4: 439c lw a5,0(a5) + 30019e6: fef42623 sw a5,-20(s0) + 30019ea: fec42703 lw a4,-20(s0) + 30019ee: 20e1a723 sw a4,526(gp) # 40004f4 + 30019f2: fdc42503 lw a0,-36(s0) + 30019f6: 23f5 jal ra,3001fe2 + 30019f8: 87aa mv a5,a0 + 30019fa: c399 beqz a5,3001a00 + 30019fc: 4785 li a5,1 + 30019fe: a06d j 3001aa8 + 3001a00: 35a1 jal ra,3001848 + 3001a02: fdc42783 lw a5,-36(s0) + 3001a06: 43dc lw a5,4(a5) + 3001a08: 8b85 andi a5,a5,1 + 3001a0a: 0ff7f693 andi a3,a5,255 + 3001a0e: fec42703 lw a4,-20(s0) + 3001a12: 431c lw a5,0(a4) + 3001a14: 8a85 andi a3,a3,1 + 3001a16: 9bf9 andi a5,a5,-2 + 3001a18: 8fd5 or a5,a5,a3 + 3001a1a: c31c sw a5,0(a4) + 3001a1c: fdc42783 lw a5,-36(s0) + 3001a20: 479c lw a5,8(a5) + 3001a22: 8bbd andi a5,a5,15 + 3001a24: 0ff7f693 andi a3,a5,255 + 3001a28: fec42703 lw a4,-20(s0) + 3001a2c: 435c lw a5,4(a4) + 3001a2e: 8abd andi a3,a3,15 + 3001a30: 9bc1 andi a5,a5,-16 + 3001a32: 8fd5 or a5,a5,a3 + 3001a34: c35c sw a5,4(a4) + 3001a36: fdc42783 lw a5,-36(s0) + 3001a3a: 47dc lw a5,12(a5) + 3001a3c: 0ff7f693 andi a3,a5,255 + 3001a40: fec42703 lw a4,-20(s0) + 3001a44: 471c lw a5,8(a4) + 3001a46: 0ff6f693 andi a3,a3,255 + 3001a4a: f007f793 andi a5,a5,-256 + 3001a4e: 8fd5 or a5,a5,a3 + 3001a50: c71c sw a5,8(a4) + 3001a52: fdc42783 lw a5,-36(s0) + 3001a56: 4b9c lw a5,16(a5) + 3001a58: 8bbd andi a5,a5,15 + 3001a5a: 0ff7f693 andi a3,a5,255 + 3001a5e: fec42703 lw a4,-20(s0) + 3001a62: 475c lw a5,12(a4) + 3001a64: 8abd andi a3,a3,15 + 3001a66: 9bc1 andi a5,a5,-16 + 3001a68: 8fd5 or a5,a5,a3 + 3001a6a: c75c sw a5,12(a4) + 3001a6c: fec42703 lw a4,-20(s0) + 3001a70: 4b1c lw a5,16(a4) + 3001a72: 9bf9 andi a5,a5,-2 + 3001a74: cb1c sw a5,16(a4) + 3001a76: fec42703 lw a4,-20(s0) + 3001a7a: 4b5c lw a5,20(a4) + 3001a7c: 76f9 lui a3,0xffffe + 3001a7e: 16fd addi a3,a3,-1 # ffffdfff + 3001a80: 8ff5 and a5,a5,a3 + 3001a82: cb5c sw a5,20(a4) + 3001a84: 0001 nop + 3001a86: fec42783 lw a5,-20(s0) + 3001a8a: 539c lw a5,32(a5) + 3001a8c: 8b85 andi a5,a5,1 + 3001a8e: 0ff7f713 andi a4,a5,255 + 3001a92: 4785 li a5,1 + 3001a94: fef719e3 bne a4,a5,3001a86 + 3001a98: fec42703 lw a4,-20(s0) + 3001a9c: 4f5c lw a5,28(a4) + 3001a9e: 0087e793 ori a5,a5,8 + 3001aa2: cf5c sw a5,28(a4) + 3001aa4: 33f1 jal ra,3001870 + 3001aa6: 4781 li a5,0 + 3001aa8: 853e mv a0,a5 + 3001aaa: 50b2 lw ra,44(sp) + 3001aac: 5422 lw s0,40(sp) + 3001aae: 6145 addi sp,sp,48 + 3001ab0: 8082 ret + +03001ab2 : + 3001ab2: 7179 addi sp,sp,-48 + 3001ab4: d606 sw ra,44(sp) + 3001ab6: d422 sw s0,40(sp) + 3001ab8: 1800 addi s0,sp,48 + 3001aba: fca42e23 sw a0,-36(s0) + 3001abe: fdc42783 lw a5,-36(s0) + 3001ac2: 439c lw a5,0(a5) + 3001ac4: fef42623 sw a5,-20(s0) + 3001ac8: 3341 jal ra,3001848 + 3001aca: fdc42783 lw a5,-36(s0) + 3001ace: 4f9c lw a5,24(a5) + 3001ad0: 85be mv a1,a5 + 3001ad2: fec42503 lw a0,-20(s0) + 3001ad6: 3dc1 jal ra,30019a6 + 3001ad8: 3b61 jal ra,3001870 + 3001ada: 4781 li a5,0 + 3001adc: 853e mv a0,a5 + 3001ade: 50b2 lw ra,44(sp) + 3001ae0: 5422 lw s0,40(sp) + 3001ae2: 6145 addi sp,sp,48 + 3001ae4: 8082 ret + +03001ae6 : + 3001ae6: 1101 addi sp,sp,-32 + 3001ae8: ce06 sw ra,28(sp) + 3001aea: cc22 sw s0,24(sp) + 3001aec: 1000 addi s0,sp,32 + 3001aee: 20e1a783 lw a5,526(gp) # 40004f4 + 3001af2: fef42623 sw a5,-20(s0) + 3001af6: fec42783 lw a5,-20(s0) + 3001afa: 439c lw a5,0(a5) + 3001afc: 8b85 andi a5,a5,1 + 3001afe: 9f81 uxtb a5 + 3001b00: 853e mv a0,a5 + 3001b02: 2bbd jal ra,3002080 + 3001b04: fea42423 sw a0,-24(s0) + 3001b08: fec42783 lw a5,-20(s0) + 3001b0c: 43dc lw a5,4(a5) + 3001b0e: 8bbd andi a5,a5,15 + 3001b10: 9f81 uxtb a5 + 3001b12: 853e mv a0,a5 + 3001b14: 2b59 jal ra,30020aa + 3001b16: 872a mv a4,a0 + 3001b18: fe842783 lw a5,-24(s0) + 3001b1c: 02e7d7b3 divu a5,a5,a4 + 3001b20: fef42423 sw a5,-24(s0) + 3001b24: fec42783 lw a5,-20(s0) + 3001b28: 479c lw a5,8(a5) + 3001b2a: 9f81 uxtb a5 + 3001b2c: 853e mv a0,a5 + 3001b2e: 2375 jal ra,30020da + 3001b30: 872a mv a4,a0 + 3001b32: fe842783 lw a5,-24(s0) + 3001b36: 02e787b3 mul a5,a5,a4 + 3001b3a: fef42423 sw a5,-24(s0) + 3001b3e: fe842783 lw a5,-24(s0) + 3001b42: 853e mv a0,a5 + 3001b44: 40f2 lw ra,28(sp) + 3001b46: 4462 lw s0,24(sp) + 3001b48: 6105 addi sp,sp,32 + 3001b4a: 8082 ret + +03001b4c : + 3001b4c: 1101 addi sp,sp,-32 + 3001b4e: ce06 sw ra,28(sp) + 3001b50: cc22 sw s0,24(sp) + 3001b52: 1000 addi s0,sp,32 + 3001b54: 20e1a783 lw a5,526(gp) # 40004f4 + 3001b58: fef42623 sw a5,-20(s0) + 3001b5c: 3769 jal ra,3001ae6 + 3001b5e: fea42423 sw a0,-24(s0) + 3001b62: fec42783 lw a5,-20(s0) + 3001b66: 47dc lw a5,12(a5) + 3001b68: 8bbd andi a5,a5,15 + 3001b6a: 9f81 uxtb a5 + 3001b6c: 853e mv a0,a5 + 3001b6e: 237d jal ra,300211c + 3001b70: 872a mv a4,a0 + 3001b72: fe842783 lw a5,-24(s0) + 3001b76: 02e7d7b3 divu a5,a5,a4 + 3001b7a: fef42423 sw a5,-24(s0) + 3001b7e: fe842783 lw a5,-24(s0) + 3001b82: 853e mv a0,a5 + 3001b84: 40f2 lw ra,28(sp) + 3001b86: 4462 lw s0,24(sp) + 3001b88: 6105 addi sp,sp,32 + 3001b8a: 8082 ret + +03001b8c : + 3001b8c: 1101 addi sp,sp,-32 + 3001b8e: ce06 sw ra,28(sp) + 3001b90: cc22 sw s0,24(sp) + 3001b92: 1000 addi s0,sp,32 + 3001b94: 20e1a783 lw a5,526(gp) # 40004f4 + 3001b98: fef42423 sw a5,-24(s0) + 3001b9c: fe842783 lw a5,-24(s0) + 3001ba0: 4fdc lw a5,28(a5) + 3001ba2: 8b8d andi a5,a5,3 + 3001ba4: 9f81 uxtb a5 + 3001ba6: fef42223 sw a5,-28(s0) + 3001baa: fe442783 lw a5,-28(s0) + 3001bae: 4705 li a4,1 + 3001bb0: 02e78063 beq a5,a4,3001bd0 + 3001bb4: 4705 li a4,1 + 3001bb6: 00e7e663 bltu a5,a4,3001bc2 + 3001bba: 4709 li a4,2 + 3001bbc: 02e78163 beq a5,a4,3001bde + 3001bc0: a01d j 3001be6 + 3001bc2: 017d87b7 lui a5,0x17d8 + 3001bc6: 84078793 addi a5,a5,-1984 # 17d7840 + 3001bca: fef42623 sw a5,-20(s0) + 3001bce: a015 j 3001bf2 + 3001bd0: 01c9c7b7 lui a5,0x1c9c + 3001bd4: 38078793 addi a5,a5,896 # 1c9c380 + 3001bd8: fef42623 sw a5,-20(s0) + 3001bdc: a819 j 3001bf2 + 3001bde: 37bd jal ra,3001b4c + 3001be0: fea42623 sw a0,-20(s0) + 3001be4: a039 j 3001bf2 + 3001be6: 67a1 lui a5,0x8 + 3001be8: d0078793 addi a5,a5,-768 # 7d00 + 3001bec: fef42623 sw a5,-20(s0) + 3001bf0: 0001 nop + 3001bf2: fec42783 lw a5,-20(s0) + 3001bf6: 853e mv a0,a5 + 3001bf8: 40f2 lw ra,28(sp) + 3001bfa: 4462 lw s0,24(sp) + 3001bfc: 6105 addi sp,sp,32 + 3001bfe: 8082 ret + +03001c00 : + 3001c00: 7179 addi sp,sp,-48 + 3001c02: d606 sw ra,44(sp) + 3001c04: d422 sw s0,40(sp) + 3001c06: 1800 addi s0,sp,48 + 3001c08: fca42e23 sw a0,-36(s0) + 3001c0c: 3741 jal ra,3001b8c + 3001c0e: fea42423 sw a0,-24(s0) + 3001c12: 67a1 lui a5,0x8 + 3001c14: d0078793 addi a5,a5,-768 # 7d00 + 3001c18: fef42623 sw a5,-20(s0) + 3001c1c: fdc42503 lw a0,-36(s0) + 3001c20: 328d jal ra,3001582 + 3001c22: fea42223 sw a0,-28(s0) + 3001c26: fe442783 lw a5,-28(s0) + 3001c2a: e781 bnez a5,3001c32 + 3001c2c: fec42783 lw a5,-20(s0) + 3001c30: a871 j 3001ccc + 3001c32: fe442783 lw a5,-28(s0) + 3001c36: 43dc lw a5,4(a5) + 3001c38: 4715 li a4,5 + 3001c3a: 06f76e63 bltu a4,a5,3001cb6 + 3001c3e: 00279713 slli a4,a5,0x2 + 3001c42: 030057b7 lui a5,0x3005 + 3001c46: 94c78793 addi a5,a5,-1716 # 300494c + 3001c4a: 97ba add a5,a5,a4 + 3001c4c: 439c lw a5,0(a5) + 3001c4e: 8782 jr a5 + 3001c50: fe842783 lw a5,-24(s0) + 3001c54: 8385 srli a5,a5,0x1 + 3001c56: 85be mv a1,a5 + 3001c58: fe442503 lw a0,-28(s0) + 3001c5c: 2c01 jal ra,3001e6c + 3001c5e: fea42623 sw a0,-20(s0) + 3001c62: a899 j 3001cb8 + 3001c64: fe842783 lw a5,-24(s0) + 3001c68: fef42623 sw a5,-20(s0) + 3001c6c: a0b1 j 3001cb8 + 3001c6e: 20e1a783 lw a5,526(gp) # 40004f4 + 3001c72: 439c lw a5,0(a5) + 3001c74: 8b85 andi a5,a5,1 + 3001c76: 9f81 uxtb a5 + 3001c78: 853e mv a0,a5 + 3001c7a: 2119 jal ra,3002080 + 3001c7c: fea42623 sw a0,-20(s0) + 3001c80: a825 j 3001cb8 + 3001c82: 20e1a783 lw a5,526(gp) # 40004f4 + 3001c86: 439c lw a5,0(a5) + 3001c88: 8b85 andi a5,a5,1 + 3001c8a: 9f81 uxtb a5 + 3001c8c: 853e mv a0,a5 + 3001c8e: 2ecd jal ra,3002080 + 3001c90: fea42623 sw a0,-20(s0) + 3001c94: fec42583 lw a1,-20(s0) + 3001c98: fe442503 lw a0,-28(s0) + 3001c9c: 24dd jal ra,3001f82 + 3001c9e: fea42623 sw a0,-20(s0) + 3001ca2: a819 j 3001cb8 + 3001ca4: 3589 jal ra,3001ae6 + 3001ca6: 87aa mv a5,a0 + 3001ca8: 85be mv a1,a5 + 3001caa: fe442503 lw a0,-28(s0) + 3001cae: 2c05 jal ra,3001ede + 3001cb0: fea42623 sw a0,-20(s0) + 3001cb4: a011 j 3001cb8 + 3001cb6: 0001 nop + 3001cb8: fec42783 lw a5,-20(s0) + 3001cbc: e791 bnez a5,3001cc8 + 3001cbe: 67a1 lui a5,0x8 + 3001cc0: d0078793 addi a5,a5,-768 # 7d00 + 3001cc4: fef42623 sw a5,-20(s0) + 3001cc8: fec42783 lw a5,-20(s0) + 3001ccc: 853e mv a0,a5 + 3001cce: 50b2 lw ra,44(sp) + 3001cd0: 5422 lw s0,40(sp) + 3001cd2: 6145 addi sp,sp,48 + 3001cd4: 8082 ret + +03001cd6 : + 3001cd6: 7179 addi sp,sp,-48 + 3001cd8: d606 sw ra,44(sp) + 3001cda: d422 sw s0,40(sp) + 3001cdc: 1800 addi s0,sp,48 + 3001cde: fca42e23 sw a0,-36(s0) + 3001ce2: fcb42c23 sw a1,-40(s0) + 3001ce6: fdc42503 lw a0,-36(s0) + 3001cea: 3861 jal ra,3001582 + 3001cec: fea42623 sw a0,-20(s0) + 3001cf0: fec42783 lw a5,-20(s0) + 3001cf4: c799 beqz a5,3001d02 + 3001cf6: fec42783 lw a5,-20(s0) + 3001cfa: 43d8 lw a4,4(a5) + 3001cfc: 4799 li a5,6 + 3001cfe: 00e7f463 bgeu a5,a4,3001d06 + 3001d02: 4785 li a5,1 + 3001d04: a0a1 j 3001d4c + 3001d06: fec42783 lw a5,-20(s0) + 3001d0a: 43d4 lw a3,4(a5) + 3001d0c: 030057b7 lui a5,0x3005 + 3001d10: 85078713 addi a4,a5,-1968 # 3004850 + 3001d14: 02400793 li a5,36 + 3001d18: 02f687b3 mul a5,a3,a5 + 3001d1c: 97ba add a5,a5,a4 + 3001d1e: 479c lw a5,8(a5) + 3001d20: e399 bnez a5,3001d26 + 3001d22: 4785 li a5,1 + 3001d24: a025 j 3001d4c + 3001d26: fec42783 lw a5,-20(s0) + 3001d2a: 43d4 lw a3,4(a5) + 3001d2c: 030057b7 lui a5,0x3005 + 3001d30: 85078713 addi a4,a5,-1968 # 3004850 + 3001d34: 02400793 li a5,36 + 3001d38: 02f687b3 mul a5,a3,a5 + 3001d3c: 97ba add a5,a5,a4 + 3001d3e: 479c lw a5,8(a5) + 3001d40: fd842583 lw a1,-40(s0) + 3001d44: fec42503 lw a0,-20(s0) + 3001d48: 9782 jalr a5 + 3001d4a: 4781 li a5,0 + 3001d4c: 853e mv a0,a5 + 3001d4e: 50b2 lw ra,44(sp) + 3001d50: 5422 lw s0,40(sp) + 3001d52: 6145 addi sp,sp,48 + 3001d54: 8082 ret + +03001d56 : + 3001d56: 7179 addi sp,sp,-48 + 3001d58: d606 sw ra,44(sp) + 3001d5a: d422 sw s0,40(sp) + 3001d5c: 1800 addi s0,sp,48 + 3001d5e: fca42e23 sw a0,-36(s0) + 3001d62: fcb42c23 sw a1,-40(s0) + 3001d66: fdc42503 lw a0,-36(s0) + 3001d6a: 3821 jal ra,3001582 + 3001d6c: fea42623 sw a0,-20(s0) + 3001d70: fec42783 lw a5,-20(s0) + 3001d74: c799 beqz a5,3001d82 + 3001d76: fec42783 lw a5,-20(s0) + 3001d7a: 43d8 lw a4,4(a5) + 3001d7c: 4799 li a5,6 + 3001d7e: 00e7f463 bgeu a5,a4,3001d86 + 3001d82: 4785 li a5,1 + 3001d84: a899 j 3001dda + 3001d86: fdc42503 lw a0,-36(s0) + 3001d8a: 28a9 jal ra,3001de4 + 3001d8c: 87aa mv a5,a0 + 3001d8e: c399 beqz a5,3001d94 + 3001d90: 4785 li a5,1 + 3001d92: a0a1 j 3001dda + 3001d94: fec42783 lw a5,-20(s0) + 3001d98: 43d4 lw a3,4(a5) + 3001d9a: 030057b7 lui a5,0x3005 + 3001d9e: 85078713 addi a4,a5,-1968 # 3004850 + 3001da2: 02400793 li a5,36 + 3001da6: 02f687b3 mul a5,a3,a5 + 3001daa: 97ba add a5,a5,a4 + 3001dac: 47dc lw a5,12(a5) + 3001dae: e399 bnez a5,3001db4 + 3001db0: 4785 li a5,1 + 3001db2: a025 j 3001dda + 3001db4: fec42783 lw a5,-20(s0) + 3001db8: 43d4 lw a3,4(a5) + 3001dba: 030057b7 lui a5,0x3005 + 3001dbe: 85078713 addi a4,a5,-1968 # 3004850 + 3001dc2: 02400793 li a5,36 + 3001dc6: 02f687b3 mul a5,a3,a5 + 3001dca: 97ba add a5,a5,a4 + 3001dcc: 47dc lw a5,12(a5) + 3001dce: fd842583 lw a1,-40(s0) + 3001dd2: fec42503 lw a0,-20(s0) + 3001dd6: 9782 jalr a5 + 3001dd8: 4781 li a5,0 + 3001dda: 853e mv a0,a5 + 3001ddc: 50b2 lw ra,44(sp) + 3001dde: 5422 lw s0,40(sp) + 3001de0: 6145 addi sp,sp,48 + 3001de2: 8082 ret + +03001de4 : + 3001de4: 1101 addi sp,sp,-32 + 3001de6: ce22 sw s0,28(sp) + 3001de8: 1000 addi s0,sp,32 + 3001dea: fea42623 sw a0,-20(s0) + 3001dee: fec42703 lw a4,-20(s0) + 3001df2: 145007b7 lui a5,0x14500 + 3001df6: 06f70263 beq a4,a5,3001e5a + 3001dfa: fec42703 lw a4,-20(s0) + 3001dfe: 145017b7 lui a5,0x14501 + 3001e02: 04f70c63 beq a4,a5,3001e5a + 3001e06: fec42703 lw a4,-20(s0) + 3001e0a: 145027b7 lui a5,0x14502 + 3001e0e: 04f70663 beq a4,a5,3001e5a + 3001e12: fec42703 lw a4,-20(s0) + 3001e16: 145037b7 lui a5,0x14503 + 3001e1a: 04f70063 beq a4,a5,3001e5a + 3001e1e: fec42703 lw a4,-20(s0) + 3001e22: 145047b7 lui a5,0x14504 + 3001e26: 02f70a63 beq a4,a5,3001e5a + 3001e2a: fec42703 lw a4,-20(s0) + 3001e2e: 145057b7 lui a5,0x14505 + 3001e32: 02f70463 beq a4,a5,3001e5a + 3001e36: fec42703 lw a4,-20(s0) + 3001e3a: 145067b7 lui a5,0x14506 + 3001e3e: 00f70e63 beq a4,a5,3001e5a + 3001e42: fec42703 lw a4,-20(s0) + 3001e46: 145077b7 lui a5,0x14507 + 3001e4a: 00f70863 beq a4,a5,3001e5a + 3001e4e: fec42703 lw a4,-20(s0) + 3001e52: 141007b7 lui a5,0x14100 + 3001e56: 00f71463 bne a4,a5,3001e5e + 3001e5a: 4785 li a5,1 + 3001e5c: a011 j 3001e60 + 3001e5e: 4781 li a5,0 + 3001e60: 8b85 andi a5,a5,1 + 3001e62: 9f81 uxtb a5 + 3001e64: 853e mv a0,a5 + 3001e66: 4472 lw s0,28(sp) + 3001e68: 6105 addi sp,sp,32 + 3001e6a: 8082 ret + +03001e6c : + 3001e6c: 7179 addi sp,sp,-48 + 3001e6e: d606 sw ra,44(sp) + 3001e70: d422 sw s0,40(sp) + 3001e72: 1800 addi s0,sp,48 + 3001e74: fca42e23 sw a0,-36(s0) + 3001e78: fcb42c23 sw a1,-40(s0) + 3001e7c: fdc42783 lw a5,-36(s0) + 3001e80: 43d8 lw a4,4(a5) + 3001e82: 02400793 li a5,36 + 3001e86: 02f70733 mul a4,a4,a5 + 3001e8a: 030057b7 lui a5,0x3005 + 3001e8e: 85078793 addi a5,a5,-1968 # 3004850 + 3001e92: 97ba add a5,a5,a4 + 3001e94: fef42623 sw a5,-20(s0) + 3001e98: fdc42783 lw a5,-36(s0) + 3001e9c: 439c lw a5,0(a5) + 3001e9e: 853e mv a0,a5 + 3001ea0: 3791 jal ra,3001de4 + 3001ea2: 87aa mv a5,a0 + 3001ea4: c781 beqz a5,3001eac + 3001ea6: fd842783 lw a5,-40(s0) + 3001eaa: a02d j 3001ed4 + 3001eac: fec42783 lw a5,-20(s0) + 3001eb0: 4fdc lw a5,28(a5) + 3001eb2: e399 bnez a5,3001eb8 + 3001eb4: 4781 li a5,0 + 3001eb6: a839 j 3001ed4 + 3001eb8: fec42783 lw a5,-20(s0) + 3001ebc: 4fdc lw a5,28(a5) + 3001ebe: fdc42503 lw a0,-36(s0) + 3001ec2: 9782 jalr a5 + 3001ec4: fea42423 sw a0,-24(s0) + 3001ec8: fd842703 lw a4,-40(s0) + 3001ecc: fe842783 lw a5,-24(s0) + 3001ed0: 00f757b3 srl a5,a4,a5 + 3001ed4: 853e mv a0,a5 + 3001ed6: 50b2 lw ra,44(sp) + 3001ed8: 5422 lw s0,40(sp) + 3001eda: 6145 addi sp,sp,48 + 3001edc: 8082 ret + +03001ede : + 3001ede: 7179 addi sp,sp,-48 + 3001ee0: d606 sw ra,44(sp) + 3001ee2: d422 sw s0,40(sp) + 3001ee4: 1800 addi s0,sp,48 + 3001ee6: fca42e23 sw a0,-36(s0) + 3001eea: fcb42c23 sw a1,-40(s0) + 3001eee: fdc42783 lw a5,-36(s0) + 3001ef2: 43d8 lw a4,4(a5) + 3001ef4: 02400793 li a5,36 + 3001ef8: 02f70733 mul a4,a4,a5 + 3001efc: 030057b7 lui a5,0x3005 + 3001f00: 85078793 addi a5,a5,-1968 # 3004850 + 3001f04: 97ba add a5,a5,a4 + 3001f06: fef42623 sw a5,-20(s0) + 3001f0a: fec42783 lw a5,-20(s0) + 3001f0e: 4fdc lw a5,28(a5) + 3001f10: e399 bnez a5,3001f16 + 3001f12: 4781 li a5,0 + 3001f14: a095 j 3001f78 + 3001f16: fec42783 lw a5,-20(s0) + 3001f1a: 4fdc lw a5,28(a5) + 3001f1c: fdc42503 lw a0,-36(s0) + 3001f20: 9782 jalr a5 + 3001f22: fea42423 sw a0,-24(s0) + 3001f26: fe842783 lw a5,-24(s0) + 3001f2a: e791 bnez a5,3001f36 + 3001f2c: 017d87b7 lui a5,0x17d8 + 3001f30: 84078793 addi a5,a5,-1984 # 17d7840 + 3001f34: a091 j 3001f78 + 3001f36: fe842703 lw a4,-24(s0) + 3001f3a: 4785 li a5,1 + 3001f3c: 00f71763 bne a4,a5,3001f4a + 3001f40: 01c9c7b7 lui a5,0x1c9c + 3001f44: 38078793 addi a5,a5,896 # 1c9c380 + 3001f48: a805 j 3001f78 + 3001f4a: fec42783 lw a5,-20(s0) + 3001f4e: 539c lw a5,32(a5) + 3001f50: e399 bnez a5,3001f56 + 3001f52: 4781 li a5,0 + 3001f54: a015 j 3001f78 + 3001f56: fec42783 lw a5,-20(s0) + 3001f5a: 539c lw a5,32(a5) + 3001f5c: fdc42503 lw a0,-36(s0) + 3001f60: 9782 jalr a5 + 3001f62: fea42223 sw a0,-28(s0) + 3001f66: fd842783 lw a5,-40(s0) + 3001f6a: 00179713 slli a4,a5,0x1 + 3001f6e: fe442783 lw a5,-28(s0) + 3001f72: 0789 addi a5,a5,2 + 3001f74: 02f757b3 divu a5,a4,a5 + 3001f78: 853e mv a0,a5 + 3001f7a: 50b2 lw ra,44(sp) + 3001f7c: 5422 lw s0,40(sp) + 3001f7e: 6145 addi sp,sp,48 + 3001f80: 8082 ret + +03001f82 : + 3001f82: 7179 addi sp,sp,-48 + 3001f84: d606 sw ra,44(sp) + 3001f86: d422 sw s0,40(sp) + 3001f88: 1800 addi s0,sp,48 + 3001f8a: fca42e23 sw a0,-36(s0) + 3001f8e: fcb42c23 sw a1,-40(s0) + 3001f92: fdc42783 lw a5,-36(s0) + 3001f96: 43d8 lw a4,4(a5) + 3001f98: 02400793 li a5,36 + 3001f9c: 02f70733 mul a4,a4,a5 + 3001fa0: 030057b7 lui a5,0x3005 + 3001fa4: 85078793 addi a5,a5,-1968 # 3004850 + 3001fa8: 97ba add a5,a5,a4 + 3001faa: fef42623 sw a5,-20(s0) + 3001fae: fec42783 lw a5,-20(s0) + 3001fb2: 539c lw a5,32(a5) + 3001fb4: e399 bnez a5,3001fba + 3001fb6: 4781 li a5,0 + 3001fb8: a005 j 3001fd8 + 3001fba: fec42783 lw a5,-20(s0) + 3001fbe: 539c lw a5,32(a5) + 3001fc0: fdc42503 lw a0,-36(s0) + 3001fc4: 9782 jalr a5 + 3001fc6: fea42423 sw a0,-24(s0) + 3001fca: fe842783 lw a5,-24(s0) + 3001fce: 0785 addi a5,a5,1 + 3001fd0: fd842703 lw a4,-40(s0) + 3001fd4: 02f757b3 divu a5,a4,a5 + 3001fd8: 853e mv a0,a5 + 3001fda: 50b2 lw ra,44(sp) + 3001fdc: 5422 lw s0,40(sp) + 3001fde: 6145 addi sp,sp,48 + 3001fe0: 8082 ret + +03001fe2 : + 3001fe2: 7179 addi sp,sp,-48 + 3001fe4: d606 sw ra,44(sp) + 3001fe6: d422 sw s0,40(sp) + 3001fe8: 1800 addi s0,sp,48 + 3001fea: fca42e23 sw a0,-36(s0) + 3001fee: fdc42783 lw a5,-36(s0) + 3001ff2: 43dc lw a5,4(a5) + 3001ff4: 853e mv a0,a5 + 3001ff6: 2069 jal ra,3002080 + 3001ff8: fea42623 sw a0,-20(s0) + 3001ffc: fdc42783 lw a5,-36(s0) + 3002000: 479c lw a5,8(a5) + 3002002: 853e mv a0,a5 + 3002004: 205d jal ra,30020aa + 3002006: fea42423 sw a0,-24(s0) + 300200a: fe842583 lw a1,-24(s0) + 300200e: fec42503 lw a0,-20(s0) + 3002012: 3061 jal ra,300189a + 3002014: 87aa mv a5,a0 + 3002016: 0017c793 xori a5,a5,1 + 300201a: 9f81 uxtb a5 + 300201c: c399 beqz a5,3002022 + 300201e: 4785 li a5,1 + 3002020: a899 j 3002076 + 3002022: fec42703 lw a4,-20(s0) + 3002026: fe842783 lw a5,-24(s0) + 300202a: 02f757b3 divu a5,a4,a5 + 300202e: fef42623 sw a5,-20(s0) + 3002032: fdc42783 lw a5,-36(s0) + 3002036: 47dc lw a5,12(a5) + 3002038: 85be mv a1,a5 + 300203a: fec42503 lw a0,-20(s0) + 300203e: 386d jal ra,30018f8 + 3002040: 87aa mv a5,a0 + 3002042: 0017c793 xori a5,a5,1 + 3002046: 9f81 uxtb a5 + 3002048: c399 beqz a5,300204e + 300204a: 4785 li a5,1 + 300204c: a02d j 3002076 + 300204e: fdc42783 lw a5,-36(s0) + 3002052: 47dc lw a5,12(a5) + 3002054: fec42703 lw a4,-20(s0) + 3002058: 02f707b3 mul a5,a4,a5 + 300205c: fef42623 sw a5,-20(s0) + 3002060: fdc42783 lw a5,-36(s0) + 3002064: 4b9c lw a5,16(a5) + 3002066: 85be mv a1,a5 + 3002068: fec42503 lw a0,-20(s0) + 300206c: 38f1 jal ra,3001948 + 300206e: 87aa mv a5,a0 + 3002070: 0017c793 xori a5,a5,1 + 3002074: 9f81 uxtb a5 + 3002076: 853e mv a0,a5 + 3002078: 50b2 lw ra,44(sp) + 300207a: 5422 lw s0,40(sp) + 300207c: 6145 addi sp,sp,48 + 300207e: 8082 ret + +03002080 : + 3002080: 1101 addi sp,sp,-32 + 3002082: ce22 sw s0,28(sp) + 3002084: 1000 addi s0,sp,32 + 3002086: fea42623 sw a0,-20(s0) + 300208a: fec42783 lw a5,-20(s0) + 300208e: e791 bnez a5,300209a + 3002090: 017d87b7 lui a5,0x17d8 + 3002094: 84078793 addi a5,a5,-1984 # 17d7840 + 3002098: a029 j 30020a2 + 300209a: 01c9c7b7 lui a5,0x1c9c + 300209e: 38078793 addi a5,a5,896 # 1c9c380 + 30020a2: 853e mv a0,a5 + 30020a4: 4472 lw s0,28(sp) + 30020a6: 6105 addi sp,sp,32 + 30020a8: 8082 ret + +030020aa : + 30020aa: 1101 addi sp,sp,-32 + 30020ac: ce22 sw s0,28(sp) + 30020ae: 1000 addi s0,sp,32 + 30020b0: fea42623 sw a0,-20(s0) + 30020b4: fec42703 lw a4,-20(s0) + 30020b8: 4785 li a5,1 + 30020ba: 00e7e463 bltu a5,a4,30020c2 + 30020be: 4785 li a5,1 + 30020c0: a809 j 30020d2 + 30020c2: fec42703 lw a4,-20(s0) + 30020c6: 4789 li a5,2 + 30020c8: 00f71463 bne a4,a5,30020d0 + 30020cc: 4789 li a5,2 + 30020ce: a011 j 30020d2 + 30020d0: 4791 li a5,4 + 30020d2: 853e mv a0,a5 + 30020d4: 4472 lw s0,28(sp) + 30020d6: 6105 addi sp,sp,32 + 30020d8: 8082 ret + +030020da : + 30020da: 7179 addi sp,sp,-48 + 30020dc: d622 sw s0,44(sp) + 30020de: 1800 addi s0,sp,48 + 30020e0: fca42e23 sw a0,-36(s0) + 30020e4: fdc42783 lw a5,-36(s0) + 30020e8: fef42623 sw a5,-20(s0) + 30020ec: fec42703 lw a4,-20(s0) + 30020f0: 4795 li a5,5 + 30020f2: 00e7e563 bltu a5,a4,30020fc + 30020f6: 4799 li a5,6 + 30020f8: fef42623 sw a5,-20(s0) + 30020fc: fec42703 lw a4,-20(s0) + 3002100: 03f00793 li a5,63 + 3002104: 00e7f663 bgeu a5,a4,3002110 + 3002108: 03f00793 li a5,63 + 300210c: fef42623 sw a5,-20(s0) + 3002110: fec42783 lw a5,-20(s0) + 3002114: 853e mv a0,a5 + 3002116: 5432 lw s0,44(sp) + 3002118: 6145 addi sp,sp,48 + 300211a: 8082 ret + +0300211c : + 300211c: 7179 addi sp,sp,-48 + 300211e: d622 sw s0,44(sp) + 3002120: 1800 addi s0,sp,48 + 3002122: fca42e23 sw a0,-36(s0) + 3002126: fdc42783 lw a5,-36(s0) + 300212a: fef42623 sw a5,-20(s0) + 300212e: fec42703 lw a4,-20(s0) + 3002132: 4795 li a5,5 + 3002134: 00e7f563 bgeu a5,a4,300213e + 3002138: 4795 li a5,5 + 300213a: fef42623 sw a5,-20(s0) + 300213e: 4705 li a4,1 + 3002140: fec42783 lw a5,-20(s0) + 3002144: 00f717b3 sll a5,a4,a5 + 3002148: 853e mv a0,a5 + 300214a: 5432 lw s0,44(sp) + 300214c: 6145 addi sp,sp,48 + 300214e: 8082 ret + +03002150 : + 3002150: 7179 addi sp,sp,-48 + 3002152: d622 sw s0,44(sp) + 3002154: 1800 addi s0,sp,48 + 3002156: fca42e23 sw a0,-36(s0) + 300215a: fcb42c23 sw a1,-40(s0) + 300215e: 20e1a783 lw a5,526(gp) # 40004f4 + 3002162: fef42623 sw a5,-20(s0) + 3002166: fdc42783 lw a5,-36(s0) + 300216a: 279e lhu a5,8(a5) + 300216c: 873e mv a4,a5 + 300216e: fec42783 lw a5,-20(s0) + 3002172: 97ba add a5,a5,a4 + 3002174: fef42423 sw a5,-24(s0) + 3002178: fd842783 lw a5,-40(s0) + 300217c: 8b85 andi a5,a5,1 + 300217e: cf99 beqz a5,300219c + 3002180: fe842703 lw a4,-24(s0) + 3002184: 431c lw a5,0(a4) + 3002186: 0017e793 ori a5,a5,1 + 300218a: c31c sw a5,0(a4) + 300218c: fe842703 lw a4,-24(s0) + 3002190: 431c lw a5,0(a4) + 3002192: 76c1 lui a3,0xffff0 + 3002194: 16fd addi a3,a3,-1 # fffeffff + 3002196: 8ff5 and a5,a5,a3 + 3002198: c31c sw a5,0(a4) + 300219a: a031 j 30021a6 + 300219c: fe842703 lw a4,-24(s0) + 30021a0: 431c lw a5,0(a4) + 30021a2: 9bf9 andi a5,a5,-2 + 30021a4: c31c sw a5,0(a4) + 30021a6: 0001 nop + 30021a8: 5432 lw s0,44(sp) + 30021aa: 6145 addi sp,sp,48 + 30021ac: 8082 ret + +030021ae : + 30021ae: 7179 addi sp,sp,-48 + 30021b0: d622 sw s0,44(sp) + 30021b2: 1800 addi s0,sp,48 + 30021b4: fca42e23 sw a0,-36(s0) + 30021b8: 20e1a783 lw a5,526(gp) # 40004f4 + 30021bc: fef42623 sw a5,-20(s0) + 30021c0: fdc42783 lw a5,-36(s0) + 30021c4: 279e lhu a5,8(a5) + 30021c6: 873e mv a4,a5 + 30021c8: fec42783 lw a5,-20(s0) + 30021cc: 97ba add a5,a5,a4 + 30021ce: fef42423 sw a5,-24(s0) + 30021d2: fe842783 lw a5,-24(s0) + 30021d6: 439c lw a5,0(a5) + 30021d8: 8b85 andi a5,a5,1 + 30021da: 9f81 uxtb a5 + 30021dc: 853e mv a0,a5 + 30021de: 5432 lw s0,44(sp) + 30021e0: 6145 addi sp,sp,48 + 30021e2: 8082 ret + +030021e4 : + 30021e4: 7179 addi sp,sp,-48 + 30021e6: d622 sw s0,44(sp) + 30021e8: 1800 addi s0,sp,48 + 30021ea: fca42e23 sw a0,-36(s0) + 30021ee: fcb42c23 sw a1,-40(s0) + 30021f2: 20e1a783 lw a5,526(gp) # 40004f4 + 30021f6: fef42623 sw a5,-20(s0) + 30021fa: fdc42783 lw a5,-36(s0) + 30021fe: 279e lhu a5,8(a5) + 3002200: 873e mv a4,a5 + 3002202: fec42783 lw a5,-20(s0) + 3002206: 97ba add a5,a5,a4 + 3002208: fef42423 sw a5,-24(s0) + 300220c: fd842783 lw a5,-40(s0) + 3002210: 8b85 andi a5,a5,1 + 3002212: 0ff7f693 andi a3,a5,255 + 3002216: fe842703 lw a4,-24(s0) + 300221a: 431c lw a5,0(a4) + 300221c: 8a85 andi a3,a3,1 + 300221e: 06c2 slli a3,a3,0x10 + 3002220: 7641 lui a2,0xffff0 + 3002222: 167d addi a2,a2,-1 # fffeffff + 3002224: 8ff1 and a5,a5,a2 + 3002226: 8fd5 or a5,a5,a3 + 3002228: c31c sw a5,0(a4) + 300222a: 0001 nop + 300222c: 5432 lw s0,44(sp) + 300222e: 6145 addi sp,sp,48 + 3002230: 8082 ret + +03002232 : + 3002232: 7179 addi sp,sp,-48 + 3002234: d622 sw s0,44(sp) + 3002236: 1800 addi s0,sp,48 + 3002238: fca42e23 sw a0,-36(s0) + 300223c: 20e1a783 lw a5,526(gp) # 40004f4 + 3002240: fef42623 sw a5,-20(s0) + 3002244: fdc42783 lw a5,-36(s0) + 3002248: 279e lhu a5,8(a5) + 300224a: 873e mv a4,a5 + 300224c: fec42783 lw a5,-20(s0) + 3002250: 97ba add a5,a5,a4 + 3002252: fef42423 sw a5,-24(s0) + 3002256: fe842783 lw a5,-24(s0) + 300225a: 439c lw a5,0(a5) + 300225c: 83c1 srli a5,a5,0x10 + 300225e: 8b85 andi a5,a5,1 + 3002260: 9f81 uxtb a5 + 3002262: 853e mv a0,a5 + 3002264: 5432 lw s0,44(sp) + 3002266: 6145 addi sp,sp,48 + 3002268: 8082 ret + +0300226a : + 300226a: 7179 addi sp,sp,-48 + 300226c: d622 sw s0,44(sp) + 300226e: 1800 addi s0,sp,48 + 3002270: fca42e23 sw a0,-36(s0) + 3002274: fcb42c23 sw a1,-40(s0) + 3002278: 20e1a783 lw a5,526(gp) # 40004f4 + 300227c: fef42623 sw a5,-20(s0) + 3002280: fdc42783 lw a5,-36(s0) + 3002284: 279e lhu a5,8(a5) + 3002286: 873e mv a4,a5 + 3002288: fec42783 lw a5,-20(s0) + 300228c: 97ba add a5,a5,a4 + 300228e: fef42423 sw a5,-24(s0) + 3002292: fd842783 lw a5,-40(s0) + 3002296: 8b8d andi a5,a5,3 + 3002298: 0ff7f693 andi a3,a5,255 + 300229c: fe842703 lw a4,-24(s0) + 30022a0: 431c lw a5,0(a4) + 30022a2: 8a8d andi a3,a3,3 + 30022a4: 06a2 slli a3,a3,0x8 + 30022a6: cff7f793 andi a5,a5,-769 + 30022aa: 8fd5 or a5,a5,a3 + 30022ac: c31c sw a5,0(a4) + 30022ae: 0001 nop + 30022b0: 5432 lw s0,44(sp) + 30022b2: 6145 addi sp,sp,48 + 30022b4: 8082 ret + +030022b6 : + 30022b6: 7179 addi sp,sp,-48 + 30022b8: d622 sw s0,44(sp) + 30022ba: 1800 addi s0,sp,48 + 30022bc: fca42e23 sw a0,-36(s0) + 30022c0: 20e1a783 lw a5,526(gp) # 40004f4 + 30022c4: fef42623 sw a5,-20(s0) + 30022c8: fdc42783 lw a5,-36(s0) + 30022cc: 279e lhu a5,8(a5) + 30022ce: 873e mv a4,a5 + 30022d0: fec42783 lw a5,-20(s0) + 30022d4: 97ba add a5,a5,a4 + 30022d6: fef42423 sw a5,-24(s0) + 30022da: fe842783 lw a5,-24(s0) + 30022de: 439c lw a5,0(a5) + 30022e0: 83a1 srli a5,a5,0x8 + 30022e2: 8b8d andi a5,a5,3 + 30022e4: 9f81 uxtb a5 + 30022e6: 853e mv a0,a5 + 30022e8: 5432 lw s0,44(sp) + 30022ea: 6145 addi sp,sp,48 + 30022ec: 8082 ret + +030022ee : + 30022ee: 7179 addi sp,sp,-48 + 30022f0: d622 sw s0,44(sp) + 30022f2: 1800 addi s0,sp,48 + 30022f4: fca42e23 sw a0,-36(s0) + 30022f8: fcb42c23 sw a1,-40(s0) + 30022fc: 20e1a783 lw a5,526(gp) # 40004f4 + 3002300: fef42623 sw a5,-20(s0) + 3002304: fdc42783 lw a5,-36(s0) + 3002308: 279e lhu a5,8(a5) + 300230a: 873e mv a4,a5 + 300230c: fec42783 lw a5,-20(s0) + 3002310: 97ba add a5,a5,a4 + 3002312: fef42423 sw a5,-24(s0) + 3002316: fe842783 lw a5,-24(s0) + 300231a: 439c lw a5,0(a5) + 300231c: fef42223 sw a5,-28(s0) + 3002320: fd842783 lw a5,-40(s0) + 3002324: 8b85 andi a5,a5,1 + 3002326: c7c1 beqz a5,30023ae + 3002328: fe442783 lw a5,-28(s0) + 300232c: 9fa1 uxth a5 + 300232e: 01079713 slli a4,a5,0x10 + 3002332: 8741 srai a4,a4,0x10 + 3002334: fdc42783 lw a5,-36(s0) + 3002338: 27bc lbu a5,10(a5) + 300233a: 86be mv a3,a5 + 300233c: 4785 li a5,1 + 300233e: 00d797b3 sll a5,a5,a3 + 3002342: 07c2 slli a5,a5,0x10 + 3002344: 87c1 srai a5,a5,0x10 + 3002346: 8fd9 or a5,a5,a4 + 3002348: 07c2 slli a5,a5,0x10 + 300234a: 87c1 srai a5,a5,0x10 + 300234c: 01079693 slli a3,a5,0x10 + 3002350: 82c1 srli a3,a3,0x10 + 3002352: fe442783 lw a5,-28(s0) + 3002356: 6741 lui a4,0x10 + 3002358: 177d addi a4,a4,-1 # ffff + 300235a: 8f75 and a4,a4,a3 + 300235c: 76c1 lui a3,0xffff0 + 300235e: 8ff5 and a5,a5,a3 + 3002360: 8fd9 or a5,a5,a4 + 3002362: fef42223 sw a5,-28(s0) + 3002366: fe442783 lw a5,-28(s0) + 300236a: 83c1 srli a5,a5,0x10 + 300236c: 9fa1 uxth a5 + 300236e: 01079713 slli a4,a5,0x10 + 3002372: 8741 srai a4,a4,0x10 + 3002374: fdc42783 lw a5,-36(s0) + 3002378: 27bc lbu a5,10(a5) + 300237a: 86be mv a3,a5 + 300237c: 4785 li a5,1 + 300237e: 00d797b3 sll a5,a5,a3 + 3002382: 07c2 slli a5,a5,0x10 + 3002384: 87c1 srai a5,a5,0x10 + 3002386: fff7c793 not a5,a5 + 300238a: 07c2 slli a5,a5,0x10 + 300238c: 87c1 srai a5,a5,0x10 + 300238e: 8ff9 and a5,a5,a4 + 3002390: 07c2 slli a5,a5,0x10 + 3002392: 87c1 srai a5,a5,0x10 + 3002394: 01079713 slli a4,a5,0x10 + 3002398: 8341 srli a4,a4,0x10 + 300239a: fe442783 lw a5,-28(s0) + 300239e: 0742 slli a4,a4,0x10 + 30023a0: 66c1 lui a3,0x10 + 30023a2: 16fd addi a3,a3,-1 # ffff + 30023a4: 8ff5 and a5,a5,a3 + 30023a6: 8fd9 or a5,a5,a4 + 30023a8: fef42223 sw a5,-28(s0) + 30023ac: a0a1 j 30023f4 + 30023ae: fe442783 lw a5,-28(s0) + 30023b2: 9fa1 uxth a5 + 30023b4: 01079713 slli a4,a5,0x10 + 30023b8: 8741 srai a4,a4,0x10 + 30023ba: fdc42783 lw a5,-36(s0) + 30023be: 27bc lbu a5,10(a5) + 30023c0: 86be mv a3,a5 + 30023c2: 4785 li a5,1 + 30023c4: 00d797b3 sll a5,a5,a3 + 30023c8: 07c2 slli a5,a5,0x10 + 30023ca: 87c1 srai a5,a5,0x10 + 30023cc: fff7c793 not a5,a5 + 30023d0: 07c2 slli a5,a5,0x10 + 30023d2: 87c1 srai a5,a5,0x10 + 30023d4: 8ff9 and a5,a5,a4 + 30023d6: 07c2 slli a5,a5,0x10 + 30023d8: 87c1 srai a5,a5,0x10 + 30023da: 01079693 slli a3,a5,0x10 + 30023de: 82c1 srli a3,a3,0x10 + 30023e0: fe442783 lw a5,-28(s0) + 30023e4: 6741 lui a4,0x10 + 30023e6: 177d addi a4,a4,-1 # ffff + 30023e8: 8f75 and a4,a4,a3 + 30023ea: 76c1 lui a3,0xffff0 + 30023ec: 8ff5 and a5,a5,a3 + 30023ee: 8fd9 or a5,a5,a4 + 30023f0: fef42223 sw a5,-28(s0) + 30023f4: fe442703 lw a4,-28(s0) + 30023f8: fe842783 lw a5,-24(s0) + 30023fc: c398 sw a4,0(a5) + 30023fe: 0001 nop + 3002400: 5432 lw s0,44(sp) + 3002402: 6145 addi sp,sp,48 + 3002404: 8082 ret + +03002406 : + 3002406: 7179 addi sp,sp,-48 + 3002408: d622 sw s0,44(sp) + 300240a: 1800 addi s0,sp,48 + 300240c: fca42e23 sw a0,-36(s0) + 3002410: 20e1a783 lw a5,526(gp) # 40004f4 + 3002414: fef42623 sw a5,-20(s0) + 3002418: fdc42783 lw a5,-36(s0) + 300241c: 279e lhu a5,8(a5) + 300241e: 873e mv a4,a5 + 3002420: fec42783 lw a5,-20(s0) + 3002424: 97ba add a5,a5,a4 + 3002426: fef42423 sw a5,-24(s0) + 300242a: fe842783 lw a5,-24(s0) + 300242e: 439c lw a5,0(a5) + 3002430: fef42223 sw a5,-28(s0) + 3002434: fe442783 lw a5,-28(s0) + 3002438: 9fa1 uxth a5 + 300243a: 873e mv a4,a5 + 300243c: fdc42783 lw a5,-36(s0) + 3002440: 27bc lbu a5,10(a5) + 3002442: 40f757b3 sra a5,a4,a5 + 3002446: 8b85 andi a5,a5,1 + 3002448: 00f037b3 snez a5,a5 + 300244c: 9f81 uxtb a5 + 300244e: 853e mv a0,a5 + 3002450: 5432 lw s0,44(sp) + 3002452: 6145 addi sp,sp,48 + 3002454: 8082 ret + +03002456 : + 3002456: 7179 addi sp,sp,-48 + 3002458: d622 sw s0,44(sp) + 300245a: 1800 addi s0,sp,48 + 300245c: fca42e23 sw a0,-36(s0) + 3002460: fcb42c23 sw a1,-40(s0) + 3002464: 20e1a783 lw a5,526(gp) # 40004f4 + 3002468: fef42623 sw a5,-20(s0) + 300246c: fdc42783 lw a5,-36(s0) + 3002470: 279e lhu a5,8(a5) + 3002472: 873e mv a4,a5 + 3002474: fec42783 lw a5,-20(s0) + 3002478: 97ba add a5,a5,a4 + 300247a: fef42423 sw a5,-24(s0) + 300247e: fe842783 lw a5,-24(s0) + 3002482: 439c lw a5,0(a5) + 3002484: fef42223 sw a5,-28(s0) + 3002488: fd842783 lw a5,-40(s0) + 300248c: 8b85 andi a5,a5,1 + 300248e: c3a9 beqz a5,30024d0 + 3002490: fe442783 lw a5,-28(s0) + 3002494: 83c1 srli a5,a5,0x10 + 3002496: 9fa1 uxth a5 + 3002498: 01079713 slli a4,a5,0x10 + 300249c: 8741 srai a4,a4,0x10 + 300249e: fdc42783 lw a5,-36(s0) + 30024a2: 27bc lbu a5,10(a5) + 30024a4: 86be mv a3,a5 + 30024a6: 4785 li a5,1 + 30024a8: 00d797b3 sll a5,a5,a3 + 30024ac: 07c2 slli a5,a5,0x10 + 30024ae: 87c1 srai a5,a5,0x10 + 30024b0: 8fd9 or a5,a5,a4 + 30024b2: 07c2 slli a5,a5,0x10 + 30024b4: 87c1 srai a5,a5,0x10 + 30024b6: 01079713 slli a4,a5,0x10 + 30024ba: 8341 srli a4,a4,0x10 + 30024bc: fe442783 lw a5,-28(s0) + 30024c0: 0742 slli a4,a4,0x10 + 30024c2: 66c1 lui a3,0x10 + 30024c4: 16fd addi a3,a3,-1 # ffff + 30024c6: 8ff5 and a5,a5,a3 + 30024c8: 8fd9 or a5,a5,a4 + 30024ca: fef42223 sw a5,-28(s0) + 30024ce: a0a1 j 3002516 + 30024d0: fe442783 lw a5,-28(s0) + 30024d4: 83c1 srli a5,a5,0x10 + 30024d6: 9fa1 uxth a5 + 30024d8: 01079713 slli a4,a5,0x10 + 30024dc: 8741 srai a4,a4,0x10 + 30024de: fdc42783 lw a5,-36(s0) + 30024e2: 27bc lbu a5,10(a5) + 30024e4: 86be mv a3,a5 + 30024e6: 4785 li a5,1 + 30024e8: 00d797b3 sll a5,a5,a3 + 30024ec: 07c2 slli a5,a5,0x10 + 30024ee: 87c1 srai a5,a5,0x10 + 30024f0: fff7c793 not a5,a5 + 30024f4: 07c2 slli a5,a5,0x10 + 30024f6: 87c1 srai a5,a5,0x10 + 30024f8: 8ff9 and a5,a5,a4 + 30024fa: 07c2 slli a5,a5,0x10 + 30024fc: 87c1 srai a5,a5,0x10 + 30024fe: 01079713 slli a4,a5,0x10 + 3002502: 8341 srli a4,a4,0x10 + 3002504: fe442783 lw a5,-28(s0) + 3002508: 0742 slli a4,a4,0x10 + 300250a: 66c1 lui a3,0x10 + 300250c: 16fd addi a3,a3,-1 # ffff + 300250e: 8ff5 and a5,a5,a3 + 3002510: 8fd9 or a5,a5,a4 + 3002512: fef42223 sw a5,-28(s0) + 3002516: fe442703 lw a4,-28(s0) + 300251a: fe842783 lw a5,-24(s0) + 300251e: c398 sw a4,0(a5) + 3002520: 0001 nop + 3002522: 5432 lw s0,44(sp) + 3002524: 6145 addi sp,sp,48 + 3002526: 8082 ret + +03002528 : + 3002528: 7179 addi sp,sp,-48 + 300252a: d622 sw s0,44(sp) + 300252c: 1800 addi s0,sp,48 + 300252e: fca42e23 sw a0,-36(s0) + 3002532: 20e1a783 lw a5,526(gp) # 40004f4 + 3002536: fef42623 sw a5,-20(s0) + 300253a: fdc42783 lw a5,-36(s0) + 300253e: 279e lhu a5,8(a5) + 3002540: 873e mv a4,a5 + 3002542: fec42783 lw a5,-20(s0) + 3002546: 97ba add a5,a5,a4 + 3002548: fef42423 sw a5,-24(s0) + 300254c: fe842783 lw a5,-24(s0) + 3002550: 439c lw a5,0(a5) + 3002552: fef42223 sw a5,-28(s0) + 3002556: fe442783 lw a5,-28(s0) + 300255a: 83c1 srli a5,a5,0x10 + 300255c: 9fa1 uxth a5 + 300255e: 873e mv a4,a5 + 3002560: fdc42783 lw a5,-36(s0) + 3002564: 27bc lbu a5,10(a5) + 3002566: 40f757b3 sra a5,a4,a5 + 300256a: 8b85 andi a5,a5,1 + 300256c: 00f037b3 snez a5,a5 + 3002570: 9f81 uxtb a5 + 3002572: 853e mv a0,a5 + 3002574: 5432 lw s0,44(sp) + 3002576: 6145 addi sp,sp,48 + 3002578: 8082 ret + +0300257a : + 300257a: 7179 addi sp,sp,-48 + 300257c: d622 sw s0,44(sp) + 300257e: 1800 addi s0,sp,48 + 3002580: fca42e23 sw a0,-36(s0) + 3002584: fcb42c23 sw a1,-40(s0) + 3002588: 20e1a783 lw a5,526(gp) # 40004f4 + 300258c: fef42623 sw a5,-20(s0) + 3002590: fdc42783 lw a5,-36(s0) + 3002594: 279e lhu a5,8(a5) + 3002596: 873e mv a4,a5 + 3002598: fec42783 lw a5,-20(s0) + 300259c: 97ba add a5,a5,a4 + 300259e: fef42423 sw a5,-24(s0) + 30025a2: fe842783 lw a5,-24(s0) + 30025a6: 439c lw a5,0(a5) + 30025a8: fef42223 sw a5,-28(s0) + 30025ac: fd842783 lw a5,-40(s0) + 30025b0: c7a1 beqz a5,30025f8 + 30025b2: fe442783 lw a5,-28(s0) + 30025b6: 0017e793 ori a5,a5,1 + 30025ba: fef42223 sw a5,-28(s0) + 30025be: fe442783 lw a5,-28(s0) + 30025c2: 0027e793 ori a5,a5,2 + 30025c6: fef42223 sw a5,-28(s0) + 30025ca: fe442783 lw a5,-28(s0) + 30025ce: 7741 lui a4,0xffff0 + 30025d0: 177d addi a4,a4,-1 # fffeffff + 30025d2: 8ff9 and a5,a5,a4 + 30025d4: fef42223 sw a5,-28(s0) + 30025d8: fe442783 lw a5,-28(s0) + 30025dc: 7701 lui a4,0xfffe0 + 30025de: 177d addi a4,a4,-1 # fffdffff + 30025e0: 8ff9 and a5,a5,a4 + 30025e2: fef42223 sw a5,-28(s0) + 30025e6: fe442783 lw a5,-28(s0) + 30025ea: fffc0737 lui a4,0xfffc0 + 30025ee: 177d addi a4,a4,-1 # fffbffff + 30025f0: 8ff9 and a5,a5,a4 + 30025f2: fef42223 sw a5,-28(s0) + 30025f6: a819 j 300260c + 30025f8: fe442783 lw a5,-28(s0) + 30025fc: 9bf9 andi a5,a5,-2 + 30025fe: fef42223 sw a5,-28(s0) + 3002602: fe442783 lw a5,-28(s0) + 3002606: 9bf5 andi a5,a5,-3 + 3002608: fef42223 sw a5,-28(s0) + 300260c: fe442703 lw a4,-28(s0) + 3002610: fe842783 lw a5,-24(s0) + 3002614: c398 sw a4,0(a5) + 3002616: 0001 nop + 3002618: 5432 lw s0,44(sp) + 300261a: 6145 addi sp,sp,48 + 300261c: 8082 ret + +0300261e : + 300261e: 7179 addi sp,sp,-48 + 3002620: d622 sw s0,44(sp) + 3002622: 1800 addi s0,sp,48 + 3002624: fca42e23 sw a0,-36(s0) + 3002628: 20e1a783 lw a5,526(gp) # 40004f4 + 300262c: fef42623 sw a5,-20(s0) + 3002630: fdc42783 lw a5,-36(s0) + 3002634: 279e lhu a5,8(a5) + 3002636: 873e mv a4,a5 + 3002638: fec42783 lw a5,-20(s0) + 300263c: 97ba add a5,a5,a4 + 300263e: fef42423 sw a5,-24(s0) + 3002642: fe842783 lw a5,-24(s0) + 3002646: 439c lw a5,0(a5) + 3002648: 8b85 andi a5,a5,1 + 300264a: 9f81 uxtb a5 + 300264c: cb91 beqz a5,3002660 + 300264e: fe842783 lw a5,-24(s0) + 3002652: 439c lw a5,0(a5) + 3002654: 8385 srli a5,a5,0x1 + 3002656: 8b85 andi a5,a5,1 + 3002658: 9f81 uxtb a5 + 300265a: c399 beqz a5,3002660 + 300265c: 4785 li a5,1 + 300265e: a011 j 3002662 + 3002660: 4781 li a5,0 + 3002662: fef42223 sw a5,-28(s0) + 3002666: fe442783 lw a5,-28(s0) + 300266a: 853e mv a0,a5 + 300266c: 5432 lw s0,44(sp) + 300266e: 6145 addi sp,sp,48 + 3002670: 8082 ret + +03002672 : + 3002672: 7179 addi sp,sp,-48 + 3002674: d622 sw s0,44(sp) + 3002676: 1800 addi s0,sp,48 + 3002678: fca42e23 sw a0,-36(s0) + 300267c: fcb42c23 sw a1,-40(s0) + 3002680: 20e1a783 lw a5,526(gp) # 40004f4 + 3002684: fef42623 sw a5,-20(s0) + 3002688: fdc42783 lw a5,-36(s0) + 300268c: 279e lhu a5,8(a5) + 300268e: 873e mv a4,a5 + 3002690: fec42783 lw a5,-20(s0) + 3002694: 97ba add a5,a5,a4 + 3002696: fef42423 sw a5,-24(s0) + 300269a: fd842783 lw a5,-40(s0) + 300269e: 8b8d andi a5,a5,3 + 30026a0: 0ff7f693 andi a3,a5,255 + 30026a4: fe842703 lw a4,-24(s0) + 30026a8: 431c lw a5,0(a4) + 30026aa: 8a8d andi a3,a3,3 + 30026ac: 06b2 slli a3,a3,0xc + 30026ae: 7675 lui a2,0xffffd + 30026b0: 167d addi a2,a2,-1 # ffffcfff + 30026b2: 8ff1 and a5,a5,a2 + 30026b4: 8fd5 or a5,a5,a3 + 30026b6: c31c sw a5,0(a4) + 30026b8: 0001 nop + 30026ba: 5432 lw s0,44(sp) + 30026bc: 6145 addi sp,sp,48 + 30026be: 8082 ret + +030026c0 : + 30026c0: 7179 addi sp,sp,-48 + 30026c2: d622 sw s0,44(sp) + 30026c4: 1800 addi s0,sp,48 + 30026c6: fca42e23 sw a0,-36(s0) + 30026ca: 20e1a783 lw a5,526(gp) # 40004f4 + 30026ce: fef42623 sw a5,-20(s0) + 30026d2: fdc42783 lw a5,-36(s0) + 30026d6: 279e lhu a5,8(a5) + 30026d8: 873e mv a4,a5 + 30026da: fec42783 lw a5,-20(s0) + 30026de: 97ba add a5,a5,a4 + 30026e0: fef42423 sw a5,-24(s0) + 30026e4: fe842783 lw a5,-24(s0) + 30026e8: 439c lw a5,0(a5) + 30026ea: 83b1 srli a5,a5,0xc + 30026ec: 8b8d andi a5,a5,3 + 30026ee: 9f81 uxtb a5 + 30026f0: 853e mv a0,a5 + 30026f2: 5432 lw s0,44(sp) + 30026f4: 6145 addi sp,sp,48 + 30026f6: 8082 ret + +030026f8 : + 30026f8: 7179 addi sp,sp,-48 + 30026fa: d622 sw s0,44(sp) + 30026fc: 1800 addi s0,sp,48 + 30026fe: fca42e23 sw a0,-36(s0) + 3002702: fcb42c23 sw a1,-40(s0) + 3002706: 20e1a783 lw a5,526(gp) # 40004f4 + 300270a: fef42623 sw a5,-20(s0) + 300270e: fdc42783 lw a5,-36(s0) + 3002712: 279e lhu a5,8(a5) + 3002714: 873e mv a4,a5 + 3002716: fec42783 lw a5,-20(s0) + 300271a: 97ba add a5,a5,a4 + 300271c: fef42423 sw a5,-24(s0) + 3002720: fd842783 lw a5,-40(s0) + 3002724: 8bfd andi a5,a5,31 + 3002726: 0ff7f693 andi a3,a5,255 + 300272a: fe842703 lw a4,-24(s0) + 300272e: 431c lw a5,0(a4) + 3002730: 8afd andi a3,a3,31 + 3002732: 0692 slli a3,a3,0x4 + 3002734: e0f7f793 andi a5,a5,-497 + 3002738: 8fd5 or a5,a5,a3 + 300273a: c31c sw a5,0(a4) + 300273c: 0001 nop + 300273e: 5432 lw s0,44(sp) + 3002740: 6145 addi sp,sp,48 + 3002742: 8082 ret + +03002744 : + 3002744: 7179 addi sp,sp,-48 + 3002746: d622 sw s0,44(sp) + 3002748: 1800 addi s0,sp,48 + 300274a: fca42e23 sw a0,-36(s0) + 300274e: 20e1a783 lw a5,526(gp) # 40004f4 + 3002752: fef42623 sw a5,-20(s0) + 3002756: fdc42783 lw a5,-36(s0) + 300275a: 279e lhu a5,8(a5) + 300275c: 873e mv a4,a5 + 300275e: fec42783 lw a5,-20(s0) + 3002762: 97ba add a5,a5,a4 + 3002764: fef42423 sw a5,-24(s0) + 3002768: fe842783 lw a5,-24(s0) + 300276c: 439c lw a5,0(a5) + 300276e: 8391 srli a5,a5,0x4 + 3002770: 8bfd andi a5,a5,31 + 3002772: 9f81 uxtb a5 + 3002774: 853e mv a0,a5 + 3002776: 5432 lw s0,44(sp) + 3002778: 6145 addi sp,sp,48 + 300277a: 8082 ret + +0300277c : + 300277c: 7179 addi sp,sp,-48 + 300277e: d622 sw s0,44(sp) + 3002780: 1800 addi s0,sp,48 + 3002782: fca42e23 sw a0,-36(s0) + 3002786: fcb42c23 sw a1,-40(s0) + 300278a: 20e1a783 lw a5,526(gp) # 40004f4 + 300278e: fef42623 sw a5,-20(s0) + 3002792: fdc42783 lw a5,-36(s0) + 3002796: 279e lhu a5,8(a5) + 3002798: 873e mv a4,a5 + 300279a: fec42783 lw a5,-20(s0) + 300279e: 97ba add a5,a5,a4 + 30027a0: fef42423 sw a5,-24(s0) + 30027a4: fe842783 lw a5,-24(s0) + 30027a8: 439c lw a5,0(a5) + 30027aa: fef42223 sw a5,-28(s0) + 30027ae: fd842783 lw a5,-40(s0) + 30027b2: c795 beqz a5,30027de + 30027b4: fe442783 lw a5,-28(s0) + 30027b8: 6741 lui a4,0x10 + 30027ba: 8fd9 or a5,a5,a4 + 30027bc: fef42223 sw a5,-28(s0) + 30027c0: fe442783 lw a5,-28(s0) + 30027c4: 00020737 lui a4,0x20 + 30027c8: 8fd9 or a5,a5,a4 + 30027ca: fef42223 sw a5,-28(s0) + 30027ce: fe442783 lw a5,-28(s0) + 30027d2: 00040737 lui a4,0x40 + 30027d6: 8fd9 or a5,a5,a4 + 30027d8: fef42223 sw a5,-28(s0) + 30027dc: a03d j 300280a + 30027de: fe442783 lw a5,-28(s0) + 30027e2: 7741 lui a4,0xffff0 + 30027e4: 177d addi a4,a4,-1 # fffeffff + 30027e6: 8ff9 and a5,a5,a4 + 30027e8: fef42223 sw a5,-28(s0) + 30027ec: fe442783 lw a5,-28(s0) + 30027f0: 7701 lui a4,0xfffe0 + 30027f2: 177d addi a4,a4,-1 # fffdffff + 30027f4: 8ff9 and a5,a5,a4 + 30027f6: fef42223 sw a5,-28(s0) + 30027fa: fe442783 lw a5,-28(s0) + 30027fe: fffc0737 lui a4,0xfffc0 + 3002802: 177d addi a4,a4,-1 # fffbffff + 3002804: 8ff9 and a5,a5,a4 + 3002806: fef42223 sw a5,-28(s0) + 300280a: fe442703 lw a4,-28(s0) + 300280e: fe842783 lw a5,-24(s0) + 3002812: c398 sw a4,0(a5) + 3002814: 0001 nop + 3002816: 5432 lw s0,44(sp) + 3002818: 6145 addi sp,sp,48 + 300281a: 8082 ret + +0300281c : + 300281c: 7179 addi sp,sp,-48 + 300281e: d622 sw s0,44(sp) + 3002820: 1800 addi s0,sp,48 + 3002822: fca42e23 sw a0,-36(s0) + 3002826: 20e1a783 lw a5,526(gp) # 40004f4 + 300282a: fef42623 sw a5,-20(s0) + 300282e: fdc42783 lw a5,-36(s0) + 3002832: 279e lhu a5,8(a5) + 3002834: 873e mv a4,a5 + 3002836: fec42783 lw a5,-20(s0) + 300283a: 97ba add a5,a5,a4 + 300283c: fef42423 sw a5,-24(s0) + 3002840: fe842783 lw a5,-24(s0) + 3002844: 439c lw a5,0(a5) + 3002846: 83c1 srli a5,a5,0x10 + 3002848: 8b85 andi a5,a5,1 + 300284a: 9f81 uxtb a5 + 300284c: fef42223 sw a5,-28(s0) + 3002850: fe842783 lw a5,-24(s0) + 3002854: 439c lw a5,0(a5) + 3002856: 83c5 srli a5,a5,0x11 + 3002858: 8b85 andi a5,a5,1 + 300285a: 9f81 uxtb a5 + 300285c: 873e mv a4,a5 + 300285e: fe442783 lw a5,-28(s0) + 3002862: 8fd9 or a5,a5,a4 + 3002864: fef42223 sw a5,-28(s0) + 3002868: fe842783 lw a5,-24(s0) + 300286c: 439c lw a5,0(a5) + 300286e: 83c9 srli a5,a5,0x12 + 3002870: 8b85 andi a5,a5,1 + 3002872: 9f81 uxtb a5 + 3002874: 873e mv a4,a5 + 3002876: fe442783 lw a5,-28(s0) + 300287a: 8fd9 or a5,a5,a4 + 300287c: fef42223 sw a5,-28(s0) + 3002880: fe442783 lw a5,-28(s0) + 3002884: 853e mv a0,a5 + 3002886: 5432 lw s0,44(sp) + 3002888: 6145 addi sp,sp,48 + 300288a: 8082 ret + +0300288c : + 300288c: 7179 addi sp,sp,-48 + 300288e: d622 sw s0,44(sp) + 3002890: 1800 addi s0,sp,48 + 3002892: fca42e23 sw a0,-36(s0) + 3002896: fcb42c23 sw a1,-40(s0) + 300289a: 20e1a783 lw a5,526(gp) # 40004f4 + 300289e: fef42623 sw a5,-20(s0) + 30028a2: fdc42783 lw a5,-36(s0) + 30028a6: 279e lhu a5,8(a5) + 30028a8: 873e mv a4,a5 + 30028aa: fec42783 lw a5,-20(s0) + 30028ae: 97ba add a5,a5,a4 + 30028b0: fef42423 sw a5,-24(s0) + 30028b4: fe842783 lw a5,-24(s0) + 30028b8: 439c lw a5,0(a5) + 30028ba: fef42223 sw a5,-28(s0) + 30028be: fd842783 lw a5,-40(s0) + 30028c2: c7c9 beqz a5,300294c + 30028c4: fe442783 lw a5,-28(s0) + 30028c8: 83c1 srli a5,a5,0x10 + 30028ca: 8b9d andi a5,a5,7 + 30028cc: 9f81 uxtb a5 + 30028ce: 01879713 slli a4,a5,0x18 + 30028d2: 8761 srai a4,a4,0x18 + 30028d4: fdc42783 lw a5,-36(s0) + 30028d8: 27bc lbu a5,10(a5) + 30028da: 86be mv a3,a5 + 30028dc: 4785 li a5,1 + 30028de: 00d797b3 sll a5,a5,a3 + 30028e2: 07e2 slli a5,a5,0x18 + 30028e4: 87e1 srai a5,a5,0x18 + 30028e6: fff7c793 not a5,a5 + 30028ea: 07e2 slli a5,a5,0x18 + 30028ec: 87e1 srai a5,a5,0x18 + 30028ee: 8ff9 and a5,a5,a4 + 30028f0: 07e2 slli a5,a5,0x18 + 30028f2: 87e1 srai a5,a5,0x18 + 30028f4: 8b9d andi a5,a5,7 + 30028f6: 0ff7f713 andi a4,a5,255 + 30028fa: fe442783 lw a5,-28(s0) + 30028fe: 8b1d andi a4,a4,7 + 3002900: 0742 slli a4,a4,0x10 + 3002902: fff906b7 lui a3,0xfff90 + 3002906: 16fd addi a3,a3,-1 # fff8ffff + 3002908: 8ff5 and a5,a5,a3 + 300290a: 8fd9 or a5,a5,a4 + 300290c: fef42223 sw a5,-28(s0) + 3002910: fe442783 lw a5,-28(s0) + 3002914: 8b9d andi a5,a5,7 + 3002916: 9f81 uxtb a5 + 3002918: 01879713 slli a4,a5,0x18 + 300291c: 8761 srai a4,a4,0x18 + 300291e: fdc42783 lw a5,-36(s0) + 3002922: 27bc lbu a5,10(a5) + 3002924: 86be mv a3,a5 + 3002926: 4785 li a5,1 + 3002928: 00d797b3 sll a5,a5,a3 + 300292c: 07e2 slli a5,a5,0x18 + 300292e: 87e1 srai a5,a5,0x18 + 3002930: 8fd9 or a5,a5,a4 + 3002932: 07e2 slli a5,a5,0x18 + 3002934: 87e1 srai a5,a5,0x18 + 3002936: 8b9d andi a5,a5,7 + 3002938: 0ff7f713 andi a4,a5,255 + 300293c: fe442783 lw a5,-28(s0) + 3002940: 8b1d andi a4,a4,7 + 3002942: 9be1 andi a5,a5,-8 + 3002944: 8fd9 or a5,a5,a4 + 3002946: fef42223 sw a5,-28(s0) + 300294a: a091 j 300298e + 300294c: fe442783 lw a5,-28(s0) + 3002950: 8b9d andi a5,a5,7 + 3002952: 9f81 uxtb a5 + 3002954: 01879713 slli a4,a5,0x18 + 3002958: 8761 srai a4,a4,0x18 + 300295a: fdc42783 lw a5,-36(s0) + 300295e: 27bc lbu a5,10(a5) + 3002960: 86be mv a3,a5 + 3002962: 4785 li a5,1 + 3002964: 00d797b3 sll a5,a5,a3 + 3002968: 07e2 slli a5,a5,0x18 + 300296a: 87e1 srai a5,a5,0x18 + 300296c: fff7c793 not a5,a5 + 3002970: 07e2 slli a5,a5,0x18 + 3002972: 87e1 srai a5,a5,0x18 + 3002974: 8ff9 and a5,a5,a4 + 3002976: 07e2 slli a5,a5,0x18 + 3002978: 87e1 srai a5,a5,0x18 + 300297a: 8b9d andi a5,a5,7 + 300297c: 0ff7f713 andi a4,a5,255 + 3002980: fe442783 lw a5,-28(s0) + 3002984: 8b1d andi a4,a4,7 + 3002986: 9be1 andi a5,a5,-8 + 3002988: 8fd9 or a5,a5,a4 + 300298a: fef42223 sw a5,-28(s0) + 300298e: fe442703 lw a4,-28(s0) + 3002992: fe842783 lw a5,-24(s0) + 3002996: c398 sw a4,0(a5) + 3002998: 0001 nop + 300299a: 5432 lw s0,44(sp) + 300299c: 6145 addi sp,sp,48 + 300299e: 8082 ret + +030029a0 : + 30029a0: 7179 addi sp,sp,-48 + 30029a2: d622 sw s0,44(sp) + 30029a4: 1800 addi s0,sp,48 + 30029a6: fca42e23 sw a0,-36(s0) + 30029aa: 20e1a783 lw a5,526(gp) # 40004f4 + 30029ae: fef42423 sw a5,-24(s0) + 30029b2: fdc42783 lw a5,-36(s0) + 30029b6: 279e lhu a5,8(a5) + 30029b8: 873e mv a4,a5 + 30029ba: fe842783 lw a5,-24(s0) + 30029be: 97ba add a5,a5,a4 + 30029c0: fef42223 sw a5,-28(s0) + 30029c4: fe442783 lw a5,-28(s0) + 30029c8: 439c lw a5,0(a5) + 30029ca: 8b9d andi a5,a5,7 + 30029cc: 9f81 uxtb a5 + 30029ce: 873e mv a4,a5 + 30029d0: fdc42783 lw a5,-36(s0) + 30029d4: 27bc lbu a5,10(a5) + 30029d6: 40f757b3 sra a5,a4,a5 + 30029da: 8b85 andi a5,a5,1 + 30029dc: c789 beqz a5,30029e6 + 30029de: 4785 li a5,1 + 30029e0: fef42623 sw a5,-20(s0) + 30029e4: a019 j 30029ea + 30029e6: fe042623 sw zero,-20(s0) + 30029ea: fec42783 lw a5,-20(s0) + 30029ee: 853e mv a0,a5 + 30029f0: 5432 lw s0,44(sp) + 30029f2: 6145 addi sp,sp,48 + 30029f4: 8082 ret + +030029f6 : + 30029f6: 7179 addi sp,sp,-48 + 30029f8: d622 sw s0,44(sp) + 30029fa: 1800 addi s0,sp,48 + 30029fc: fca42e23 sw a0,-36(s0) + 3002a00: fcb42c23 sw a1,-40(s0) + 3002a04: 20e1a783 lw a5,526(gp) # 40004f4 + 3002a08: fef42623 sw a5,-20(s0) + 3002a0c: fdc42783 lw a5,-36(s0) + 3002a10: 279e lhu a5,8(a5) + 3002a12: 873e mv a4,a5 + 3002a14: fec42783 lw a5,-20(s0) + 3002a18: 97ba add a5,a5,a4 + 3002a1a: fef42423 sw a5,-24(s0) + 3002a1e: fe842783 lw a5,-24(s0) + 3002a22: 439c lw a5,0(a5) + 3002a24: fef42223 sw a5,-28(s0) + 3002a28: fe442783 lw a5,-28(s0) + 3002a2c: 8391 srli a5,a5,0x4 + 3002a2e: 873e mv a4,a5 + 3002a30: 6785 lui a5,0x1 + 3002a32: 17fd addi a5,a5,-1 # fff + 3002a34: 8ff9 and a5,a5,a4 + 3002a36: 9fa1 uxth a5 + 3002a38: 01079713 slli a4,a5,0x10 + 3002a3c: 8741 srai a4,a4,0x10 + 3002a3e: fdc42783 lw a5,-36(s0) + 3002a42: 27bc lbu a5,10(a5) + 3002a44: 078a slli a5,a5,0x2 + 3002a46: 46bd li a3,15 + 3002a48: 00f697b3 sll a5,a3,a5 + 3002a4c: 07c2 slli a5,a5,0x10 + 3002a4e: 87c1 srai a5,a5,0x10 + 3002a50: fff7c793 not a5,a5 + 3002a54: 07c2 slli a5,a5,0x10 + 3002a56: 87c1 srai a5,a5,0x10 + 3002a58: 8ff9 and a5,a5,a4 + 3002a5a: 07c2 slli a5,a5,0x10 + 3002a5c: 87c1 srai a5,a5,0x10 + 3002a5e: 873e mv a4,a5 + 3002a60: 6785 lui a5,0x1 + 3002a62: 17fd addi a5,a5,-1 # fff + 3002a64: 8ff9 and a5,a5,a4 + 3002a66: 01079693 slli a3,a5,0x10 + 3002a6a: 82c1 srli a3,a3,0x10 + 3002a6c: fe442783 lw a5,-28(s0) + 3002a70: 6705 lui a4,0x1 + 3002a72: 177d addi a4,a4,-1 # fff + 3002a74: 8f75 and a4,a4,a3 + 3002a76: 0712 slli a4,a4,0x4 + 3002a78: 76c1 lui a3,0xffff0 + 3002a7a: 06bd addi a3,a3,15 # ffff000f + 3002a7c: 8ff5 and a5,a5,a3 + 3002a7e: 8fd9 or a5,a5,a4 + 3002a80: fef42223 sw a5,-28(s0) + 3002a84: fe442783 lw a5,-28(s0) + 3002a88: 8391 srli a5,a5,0x4 + 3002a8a: 873e mv a4,a5 + 3002a8c: 6785 lui a5,0x1 + 3002a8e: 17fd addi a5,a5,-1 # fff + 3002a90: 8ff9 and a5,a5,a4 + 3002a92: 9fa1 uxth a5 + 3002a94: 86be mv a3,a5 + 3002a96: fd842783 lw a5,-40(s0) + 3002a9a: 00f7f713 andi a4,a5,15 + 3002a9e: fdc42783 lw a5,-36(s0) + 3002aa2: 27bc lbu a5,10(a5) + 3002aa4: 078a slli a5,a5,0x2 + 3002aa6: 00f717b3 sll a5,a4,a5 + 3002aaa: 9fa1 uxth a5 + 3002aac: 8fd5 or a5,a5,a3 + 3002aae: 9fa1 uxth a5 + 3002ab0: 873e mv a4,a5 + 3002ab2: 6785 lui a5,0x1 + 3002ab4: 17fd addi a5,a5,-1 # fff + 3002ab6: 8ff9 and a5,a5,a4 + 3002ab8: 01079693 slli a3,a5,0x10 + 3002abc: 82c1 srli a3,a3,0x10 + 3002abe: fe442783 lw a5,-28(s0) + 3002ac2: 6705 lui a4,0x1 + 3002ac4: 177d addi a4,a4,-1 # fff + 3002ac6: 8f75 and a4,a4,a3 + 3002ac8: 0712 slli a4,a4,0x4 + 3002aca: 76c1 lui a3,0xffff0 + 3002acc: 06bd addi a3,a3,15 # ffff000f + 3002ace: 8ff5 and a5,a5,a3 + 3002ad0: 8fd9 or a5,a5,a4 + 3002ad2: fef42223 sw a5,-28(s0) + 3002ad6: fe442703 lw a4,-28(s0) + 3002ada: fe842783 lw a5,-24(s0) + 3002ade: c398 sw a4,0(a5) + 3002ae0: 0001 nop + 3002ae2: 5432 lw s0,44(sp) + 3002ae4: 6145 addi sp,sp,48 + 3002ae6: 8082 ret + +03002ae8 : + 3002ae8: 7179 addi sp,sp,-48 + 3002aea: d622 sw s0,44(sp) + 3002aec: 1800 addi s0,sp,48 + 3002aee: fca42e23 sw a0,-36(s0) + 3002af2: 20e1a783 lw a5,526(gp) # 40004f4 + 3002af6: fef42623 sw a5,-20(s0) + 3002afa: fdc42783 lw a5,-36(s0) + 3002afe: 279e lhu a5,8(a5) + 3002b00: 873e mv a4,a5 + 3002b02: fec42783 lw a5,-20(s0) + 3002b06: 97ba add a5,a5,a4 + 3002b08: fef42423 sw a5,-24(s0) + 3002b0c: fe842783 lw a5,-24(s0) + 3002b10: 439c lw a5,0(a5) + 3002b12: 8391 srli a5,a5,0x4 + 3002b14: 873e mv a4,a5 + 3002b16: 6785 lui a5,0x1 + 3002b18: 17fd addi a5,a5,-1 # fff + 3002b1a: 8ff9 and a5,a5,a4 + 3002b1c: 9fa1 uxth a5 + 3002b1e: fef42223 sw a5,-28(s0) + 3002b22: fdc42783 lw a5,-36(s0) + 3002b26: 27bc lbu a5,10(a5) + 3002b28: 078a slli a5,a5,0x2 + 3002b2a: fe442703 lw a4,-28(s0) + 3002b2e: 00f757b3 srl a5,a4,a5 + 3002b32: fef42223 sw a5,-28(s0) + 3002b36: fe442783 lw a5,-28(s0) + 3002b3a: 8bbd andi a5,a5,15 + 3002b3c: 853e mv a0,a5 + 3002b3e: 5432 lw s0,44(sp) + 3002b40: 6145 addi sp,sp,48 + 3002b42: 8082 ret + +03002b44 : + 3002b44: 7179 addi sp,sp,-48 + 3002b46: d622 sw s0,44(sp) + 3002b48: 1800 addi s0,sp,48 + 3002b4a: fca42e23 sw a0,-36(s0) + 3002b4e: fcb42c23 sw a1,-40(s0) + 3002b52: 20e1a783 lw a5,526(gp) # 40004f4 + 3002b56: fef42623 sw a5,-20(s0) + 3002b5a: fdc42783 lw a5,-36(s0) + 3002b5e: 279e lhu a5,8(a5) + 3002b60: 873e mv a4,a5 + 3002b62: fec42783 lw a5,-20(s0) + 3002b66: 97ba add a5,a5,a4 + 3002b68: fef42423 sw a5,-24(s0) + 3002b6c: fe842783 lw a5,-24(s0) + 3002b70: 439c lw a5,0(a5) + 3002b72: fef42223 sw a5,-28(s0) + 3002b76: fd842783 lw a5,-40(s0) + 3002b7a: c7a1 beqz a5,3002bc2 + 3002b7c: fe442783 lw a5,-28(s0) + 3002b80: 83c1 srli a5,a5,0x10 + 3002b82: 8b9d andi a5,a5,7 + 3002b84: 9f81 uxtb a5 + 3002b86: 01879713 slli a4,a5,0x18 + 3002b8a: 8761 srai a4,a4,0x18 + 3002b8c: fdc42783 lw a5,-36(s0) + 3002b90: 27bc lbu a5,10(a5) + 3002b92: 86be mv a3,a5 + 3002b94: 4785 li a5,1 + 3002b96: 00d797b3 sll a5,a5,a3 + 3002b9a: 07e2 slli a5,a5,0x18 + 3002b9c: 87e1 srai a5,a5,0x18 + 3002b9e: 8fd9 or a5,a5,a4 + 3002ba0: 07e2 slli a5,a5,0x18 + 3002ba2: 87e1 srai a5,a5,0x18 + 3002ba4: 8b9d andi a5,a5,7 + 3002ba6: 0ff7f713 andi a4,a5,255 + 3002baa: fe442783 lw a5,-28(s0) + 3002bae: 8b1d andi a4,a4,7 + 3002bb0: 0742 slli a4,a4,0x10 + 3002bb2: fff906b7 lui a3,0xfff90 + 3002bb6: 16fd addi a3,a3,-1 # fff8ffff + 3002bb8: 8ff5 and a5,a5,a3 + 3002bba: 8fd9 or a5,a5,a4 + 3002bbc: fef42223 sw a5,-28(s0) + 3002bc0: a0b9 j 3002c0e + 3002bc2: fe442783 lw a5,-28(s0) + 3002bc6: 83c1 srli a5,a5,0x10 + 3002bc8: 8b9d andi a5,a5,7 + 3002bca: 9f81 uxtb a5 + 3002bcc: 01879713 slli a4,a5,0x18 + 3002bd0: 8761 srai a4,a4,0x18 + 3002bd2: fdc42783 lw a5,-36(s0) + 3002bd6: 27bc lbu a5,10(a5) + 3002bd8: 86be mv a3,a5 + 3002bda: 4785 li a5,1 + 3002bdc: 00d797b3 sll a5,a5,a3 + 3002be0: 07e2 slli a5,a5,0x18 + 3002be2: 87e1 srai a5,a5,0x18 + 3002be4: fff7c793 not a5,a5 + 3002be8: 07e2 slli a5,a5,0x18 + 3002bea: 87e1 srai a5,a5,0x18 + 3002bec: 8ff9 and a5,a5,a4 + 3002bee: 07e2 slli a5,a5,0x18 + 3002bf0: 87e1 srai a5,a5,0x18 + 3002bf2: 8b9d andi a5,a5,7 + 3002bf4: 0ff7f713 andi a4,a5,255 + 3002bf8: fe442783 lw a5,-28(s0) + 3002bfc: 8b1d andi a4,a4,7 + 3002bfe: 0742 slli a4,a4,0x10 + 3002c00: fff906b7 lui a3,0xfff90 + 3002c04: 16fd addi a3,a3,-1 # fff8ffff + 3002c06: 8ff5 and a5,a5,a3 + 3002c08: 8fd9 or a5,a5,a4 + 3002c0a: fef42223 sw a5,-28(s0) + 3002c0e: fe442703 lw a4,-28(s0) + 3002c12: fe842783 lw a5,-24(s0) + 3002c16: c398 sw a4,0(a5) + 3002c18: 0001 nop + 3002c1a: 5432 lw s0,44(sp) + 3002c1c: 6145 addi sp,sp,48 + 3002c1e: 8082 ret + +03002c20 : + 3002c20: 7179 addi sp,sp,-48 + 3002c22: d622 sw s0,44(sp) + 3002c24: 1800 addi s0,sp,48 + 3002c26: fca42e23 sw a0,-36(s0) + 3002c2a: 20e1a783 lw a5,526(gp) # 40004f4 + 3002c2e: fef42623 sw a5,-20(s0) + 3002c32: fdc42783 lw a5,-36(s0) + 3002c36: 279e lhu a5,8(a5) + 3002c38: 873e mv a4,a5 + 3002c3a: fec42783 lw a5,-20(s0) + 3002c3e: 97ba add a5,a5,a4 + 3002c40: fef42423 sw a5,-24(s0) + 3002c44: fe842783 lw a5,-24(s0) + 3002c48: 439c lw a5,0(a5) + 3002c4a: 83c1 srli a5,a5,0x10 + 3002c4c: 8b9d andi a5,a5,7 + 3002c4e: 9f81 uxtb a5 + 3002c50: 873e mv a4,a5 + 3002c52: fdc42783 lw a5,-36(s0) + 3002c56: 27bc lbu a5,10(a5) + 3002c58: 40f757b3 sra a5,a4,a5 + 3002c5c: 8b85 andi a5,a5,1 + 3002c5e: 853e mv a0,a5 + 3002c60: 5432 lw s0,44(sp) + 3002c62: 6145 addi sp,sp,48 + 3002c64: 8082 ret + +03002c66 : + 3002c66: 7179 addi sp,sp,-48 + 3002c68: d622 sw s0,44(sp) + 3002c6a: 1800 addi s0,sp,48 + 3002c6c: fca42e23 sw a0,-36(s0) + 3002c70: fcb42c23 sw a1,-40(s0) + 3002c74: 20e1a783 lw a5,526(gp) # 40004f4 + 3002c78: fef42623 sw a5,-20(s0) + 3002c7c: fdc42783 lw a5,-36(s0) + 3002c80: 279e lhu a5,8(a5) + 3002c82: 873e mv a4,a5 + 3002c84: fec42783 lw a5,-20(s0) + 3002c88: 97ba add a5,a5,a4 + 3002c8a: fef42423 sw a5,-24(s0) + 3002c8e: fd842783 lw a5,-40(s0) + 3002c92: 8b85 andi a5,a5,1 + 3002c94: 0ff7f693 andi a3,a5,255 + 3002c98: fe842703 lw a4,-24(s0) + 3002c9c: 431c lw a5,0(a4) + 3002c9e: 8a85 andi a3,a3,1 + 3002ca0: 9bf9 andi a5,a5,-2 + 3002ca2: 8fd5 or a5,a5,a3 + 3002ca4: c31c sw a5,0(a4) + 3002ca6: 0001 nop + 3002ca8: 5432 lw s0,44(sp) + 3002caa: 6145 addi sp,sp,48 + 3002cac: 8082 ret + +03002cae : + 3002cae: 7179 addi sp,sp,-48 + 3002cb0: d622 sw s0,44(sp) + 3002cb2: 1800 addi s0,sp,48 + 3002cb4: fca42e23 sw a0,-36(s0) + 3002cb8: 20e1a783 lw a5,526(gp) # 40004f4 + 3002cbc: fef42623 sw a5,-20(s0) + 3002cc0: fdc42783 lw a5,-36(s0) + 3002cc4: 279e lhu a5,8(a5) + 3002cc6: 873e mv a4,a5 + 3002cc8: fec42783 lw a5,-20(s0) + 3002ccc: 97ba add a5,a5,a4 + 3002cce: fef42423 sw a5,-24(s0) + 3002cd2: fe842783 lw a5,-24(s0) + 3002cd6: 439c lw a5,0(a5) + 3002cd8: 8b85 andi a5,a5,1 + 3002cda: 9f81 uxtb a5 + 3002cdc: 853e mv a0,a5 + 3002cde: 5432 lw s0,44(sp) + 3002ce0: 6145 addi sp,sp,48 + 3002ce2: 8082 ret + +03002ce4 : + 3002ce4: 1101 addi sp,sp,-32 + 3002ce6: ce22 sw s0,28(sp) + 3002ce8: 1000 addi s0,sp,32 + 3002cea: fea42623 sw a0,-20(s0) + 3002cee: 0001 nop + 3002cf0: 140007b7 lui a5,0x14000 + 3002cf4: 4f9c lw a5,24(a5) + 3002cf6: 8395 srli a5,a5,0x5 + 3002cf8: 8b85 andi a5,a5,1 + 3002cfa: 0ff7f713 andi a4,a5,255 + 3002cfe: 4785 li a5,1 + 3002d00: fef708e3 beq a4,a5,3002cf0 + 3002d04: 14000737 lui a4,0x14000 + 3002d08: fec42783 lw a5,-20(s0) + 3002d0c: 0ff7f693 andi a3,a5,255 + 3002d10: 431c lw a5,0(a4) + 3002d12: 0ff6f693 andi a3,a3,255 + 3002d16: f007f793 andi a5,a5,-256 + 3002d1a: 8fd5 or a5,a5,a3 + 3002d1c: c31c sw a5,0(a4) + 3002d1e: 0001 nop + 3002d20: 4472 lw s0,28(sp) + 3002d22: 6105 addi sp,sp,32 + 3002d24: 8082 ret + +03002d26 : + 3002d26: 7179 addi sp,sp,-48 + 3002d28: d606 sw ra,44(sp) + 3002d2a: d422 sw s0,40(sp) + 3002d2c: 1800 addi s0,sp,48 + 3002d2e: fca42e23 sw a0,-36(s0) + 3002d32: fe042623 sw zero,-20(s0) + 3002d36: a00d j 3002d58 + 3002d38: fdc42783 lw a5,-36(s0) + 3002d3c: 00078783 lb a5,0(a5) # 14000000 + 3002d40: 853e mv a0,a5 + 3002d42: 374d jal ra,3002ce4 + 3002d44: fdc42783 lw a5,-36(s0) + 3002d48: 0785 addi a5,a5,1 + 3002d4a: fcf42e23 sw a5,-36(s0) + 3002d4e: fec42783 lw a5,-20(s0) + 3002d52: 0785 addi a5,a5,1 + 3002d54: fef42623 sw a5,-20(s0) + 3002d58: fdc42783 lw a5,-36(s0) + 3002d5c: 00078783 lb a5,0(a5) + 3002d60: ffe1 bnez a5,3002d38 + 3002d62: fec42783 lw a5,-20(s0) + 3002d66: 853e mv a0,a5 + 3002d68: 50b2 lw ra,44(sp) + 3002d6a: 5422 lw s0,40(sp) + 3002d6c: 6145 addi sp,sp,48 + 3002d6e: 8082 ret + +03002d70 : + 3002d70: 7179 addi sp,sp,-48 + 3002d72: d622 sw s0,44(sp) + 3002d74: 1800 addi s0,sp,48 + 3002d76: fca42e23 sw a0,-36(s0) + 3002d7a: fcb42c23 sw a1,-40(s0) + 3002d7e: 4785 li a5,1 + 3002d80: fef42623 sw a5,-20(s0) + 3002d84: a809 j 3002d96 + 3002d86: fec42703 lw a4,-20(s0) + 3002d8a: fdc42783 lw a5,-36(s0) + 3002d8e: 02f707b3 mul a5,a4,a5 + 3002d92: fef42623 sw a5,-20(s0) + 3002d96: fd842783 lw a5,-40(s0) + 3002d9a: fff78713 addi a4,a5,-1 + 3002d9e: fce42c23 sw a4,-40(s0) + 3002da2: f3f5 bnez a5,3002d86 + 3002da4: fec42783 lw a5,-20(s0) + 3002da8: 853e mv a0,a5 + 3002daa: 5432 lw s0,44(sp) + 3002dac: 6145 addi sp,sp,48 + 3002dae: 8082 ret + +03002db0 : + 3002db0: 7179 addi sp,sp,-48 + 3002db2: d622 sw s0,44(sp) + 3002db4: 1800 addi s0,sp,48 + 3002db6: fca42e23 sw a0,-36(s0) + 3002dba: fcb42c23 sw a1,-40(s0) + 3002dbe: fe042623 sw zero,-20(s0) + 3002dc2: fd842783 lw a5,-40(s0) + 3002dc6: e78d bnez a5,3002df0 + 3002dc8: 4781 li a5,0 + 3002dca: a099 j 3002e10 + 3002dcc: fec42783 lw a5,-20(s0) + 3002dd0: 0785 addi a5,a5,1 + 3002dd2: fef42623 sw a5,-20(s0) + 3002dd6: fec42703 lw a4,-20(s0) + 3002dda: 47fd li a5,31 + 3002ddc: 00e7ee63 bltu a5,a4,3002df8 + 3002de0: fdc42703 lw a4,-36(s0) + 3002de4: fd842783 lw a5,-40(s0) + 3002de8: 02f757b3 divu a5,a4,a5 + 3002dec: fcf42e23 sw a5,-36(s0) + 3002df0: fdc42783 lw a5,-36(s0) + 3002df4: ffe1 bnez a5,3002dcc + 3002df6: a011 j 3002dfa + 3002df8: 0001 nop + 3002dfa: fec42783 lw a5,-20(s0) + 3002dfe: c781 beqz a5,3002e06 + 3002e00: fec42783 lw a5,-20(s0) + 3002e04: a011 j 3002e08 + 3002e06: 4785 li a5,1 + 3002e08: fef42623 sw a5,-20(s0) + 3002e0c: fec42783 lw a5,-20(s0) + 3002e10: 853e mv a0,a5 + 3002e12: 5432 lw s0,44(sp) + 3002e14: 6145 addi sp,sp,48 + 3002e16: 8082 ret + +03002e18 : + 3002e18: 7179 addi sp,sp,-48 + 3002e1a: d606 sw ra,44(sp) + 3002e1c: d422 sw s0,40(sp) + 3002e1e: 1800 addi s0,sp,48 + 3002e20: fca42e23 sw a0,-36(s0) + 3002e24: fcb42c23 sw a1,-40(s0) + 3002e28: fcc42a23 sw a2,-44(s0) + 3002e2c: a069 j 3002eb6 + 3002e2e: fd442783 lw a5,-44(s0) + 3002e32: 17fd addi a5,a5,-1 + 3002e34: 85be mv a1,a5 + 3002e36: fd842503 lw a0,-40(s0) + 3002e3a: 3f1d jal ra,3002d70 + 3002e3c: 872a mv a4,a0 + 3002e3e: fdc42783 lw a5,-36(s0) + 3002e42: 02e7d7b3 divu a5,a5,a4 + 3002e46: fef407a3 sb a5,-17(s0) + 3002e4a: fd442783 lw a5,-44(s0) + 3002e4e: 17fd addi a5,a5,-1 + 3002e50: 85be mv a1,a5 + 3002e52: fd842503 lw a0,-40(s0) + 3002e56: 3f29 jal ra,3002d70 + 3002e58: 872a mv a4,a0 + 3002e5a: fdc42783 lw a5,-36(s0) + 3002e5e: 02e7f7b3 remu a5,a5,a4 + 3002e62: fcf42e23 sw a5,-36(s0) + 3002e66: fd842703 lw a4,-40(s0) + 3002e6a: 47a9 li a5,10 + 3002e6c: 00f71963 bne a4,a5,3002e7e + 3002e70: fef44783 lbu a5,-17(s0) + 3002e74: 03078793 addi a5,a5,48 + 3002e78: 853e mv a0,a5 + 3002e7a: 35ad jal ra,3002ce4 + 3002e7c: a805 j 3002eac + 3002e7e: fd842703 lw a4,-40(s0) + 3002e82: 47c1 li a5,16 + 3002e84: 02f71d63 bne a4,a5,3002ebe + 3002e88: fef44703 lbu a4,-17(s0) + 3002e8c: 47a5 li a5,9 + 3002e8e: 00e7e963 bltu a5,a4,3002ea0 + 3002e92: fef44783 lbu a5,-17(s0) + 3002e96: 03078793 addi a5,a5,48 + 3002e9a: 853e mv a0,a5 + 3002e9c: 35a1 jal ra,3002ce4 + 3002e9e: a039 j 3002eac + 3002ea0: fef44783 lbu a5,-17(s0) + 3002ea4: 03778793 addi a5,a5,55 + 3002ea8: 853e mv a0,a5 + 3002eaa: 3d2d jal ra,3002ce4 + 3002eac: fd442783 lw a5,-44(s0) + 3002eb0: 17fd addi a5,a5,-1 + 3002eb2: fcf42a23 sw a5,-44(s0) + 3002eb6: fd442783 lw a5,-44(s0) + 3002eba: fbb5 bnez a5,3002e2e + 3002ebc: a011 j 3002ec0 + 3002ebe: 0001 nop + 3002ec0: 0001 nop + 3002ec2: 50b2 lw ra,44(sp) + 3002ec4: 5422 lw s0,40(sp) + 3002ec6: 6145 addi sp,sp,48 + 3002ec8: 8082 ret + +03002eca : + 3002eca: 7179 addi sp,sp,-48 + 3002ecc: d606 sw ra,44(sp) + 3002ece: d422 sw s0,40(sp) + 3002ed0: 1800 addi s0,sp,48 + 3002ed2: fca42e23 sw a0,-36(s0) + 3002ed6: fdc42783 lw a5,-36(s0) + 3002eda: e791 bnez a5,3002ee6 + 3002edc: 03000513 li a0,48 + 3002ee0: 3511 jal ra,3002ce4 + 3002ee2: 4785 li a5,1 + 3002ee4: a82d j 3002f1e + 3002ee6: fdc42783 lw a5,-36(s0) + 3002eea: 0007db63 bgez a5,3002f00 + 3002eee: 02d00513 li a0,45 + 3002ef2: 3bcd jal ra,3002ce4 + 3002ef4: fdc42783 lw a5,-36(s0) + 3002ef8: 40f007b3 neg a5,a5 + 3002efc: fcf42e23 sw a5,-36(s0) + 3002f00: 45a9 li a1,10 + 3002f02: fdc42503 lw a0,-36(s0) + 3002f06: 356d jal ra,3002db0 + 3002f08: fea42623 sw a0,-20(s0) + 3002f0c: fdc42783 lw a5,-36(s0) + 3002f10: fec42603 lw a2,-20(s0) + 3002f14: 45a9 li a1,10 + 3002f16: 853e mv a0,a5 + 3002f18: 3701 jal ra,3002e18 + 3002f1a: fec42783 lw a5,-20(s0) + 3002f1e: 853e mv a0,a5 + 3002f20: 50b2 lw ra,44(sp) + 3002f22: 5422 lw s0,40(sp) + 3002f24: 6145 addi sp,sp,48 + 3002f26: 8082 ret + +03002f28 : + 3002f28: 7179 addi sp,sp,-48 + 3002f2a: d606 sw ra,44(sp) + 3002f2c: d422 sw s0,40(sp) + 3002f2e: 1800 addi s0,sp,48 + 3002f30: fca42e23 sw a0,-36(s0) + 3002f34: fdc42783 lw a5,-36(s0) + 3002f38: e791 bnez a5,3002f44 + 3002f3a: 03000513 li a0,48 + 3002f3e: 335d jal ra,3002ce4 + 3002f40: 4785 li a5,1 + 3002f42: a005 j 3002f62 + 3002f44: fdc42783 lw a5,-36(s0) + 3002f48: 45c1 li a1,16 + 3002f4a: 853e mv a0,a5 + 3002f4c: 3595 jal ra,3002db0 + 3002f4e: fea42623 sw a0,-20(s0) + 3002f52: fec42603 lw a2,-20(s0) + 3002f56: 45c1 li a1,16 + 3002f58: fdc42503 lw a0,-36(s0) + 3002f5c: 3d75 jal ra,3002e18 + 3002f5e: fec42783 lw a5,-20(s0) + 3002f62: 853e mv a0,a5 + 3002f64: 50b2 lw ra,44(sp) + 3002f66: 5422 lw s0,40(sp) + 3002f68: 6145 addi sp,sp,48 + 3002f6a: 8082 ret + +03002f6c : + 3002f6c: 7139 addi sp,sp,-64 + 3002f6e: de06 sw ra,60(sp) + 3002f70: dc22 sw s0,56(sp) + 3002f72: 0080 addi s0,sp,64 + 3002f74: fca42627 fsw fa0,-52(s0) + 3002f78: fca42423 sw a0,-56(s0) + 3002f7c: fe042623 sw zero,-20(s0) + 3002f80: fcc42787 flw fa5,-52(s0) + 3002f84: f0000753 fmv.w.x fa4,zero + 3002f88: a0e797d3 flt.s a5,fa5,fa4 + 3002f8c: cf99 beqz a5,3002faa + 3002f8e: 02d00513 li a0,45 + 3002f92: 3b89 jal ra,3002ce4 + 3002f94: fec42783 lw a5,-20(s0) + 3002f98: 0785 addi a5,a5,1 + 3002f9a: fef42623 sw a5,-20(s0) + 3002f9e: fcc42787 flw fa5,-52(s0) + 3002fa2: 20f797d3 fneg.s fa5,fa5 + 3002fa6: fcf42627 fsw fa5,-52(s0) + 3002faa: fcc42787 flw fa5,-52(s0) + 3002fae: c00797d3 fcvt.w.s a5,fa5,rtz + 3002fb2: fef42023 sw a5,-32(s0) + 3002fb6: fc842783 lw a5,-56(s0) + 3002fba: 0785 addi a5,a5,1 + 3002fbc: 85be mv a1,a5 + 3002fbe: 4529 li a0,10 + 3002fc0: 3b45 jal ra,3002d70 + 3002fc2: fca42e23 sw a0,-36(s0) + 3002fc6: fdc42783 lw a5,-36(s0) + 3002fca: d017f753 fcvt.s.wu fa4,a5 + 3002fce: fe042783 lw a5,-32(s0) + 3002fd2: d007f7d3 fcvt.s.w fa5,a5 + 3002fd6: fcc42687 flw fa3,-52(s0) + 3002fda: 08f6f7d3 fsub.s fa5,fa3,fa5 + 3002fde: 10f777d3 fmul.s fa5,fa4,fa5 + 3002fe2: c00797d3 fcvt.w.s a5,fa5,rtz + 3002fe6: fef42423 sw a5,-24(s0) + 3002fea: fe842703 lw a4,-24(s0) + 3002fee: 47a9 li a5,10 + 3002ff0: 02f77733 remu a4,a4,a5 + 3002ff4: 4791 li a5,4 + 3002ff6: 00e7fb63 bgeu a5,a4,300300c + 3002ffa: fe842703 lw a4,-24(s0) + 3002ffe: 47a9 li a5,10 + 3003000: 02f757b3 divu a5,a4,a5 + 3003004: 0785 addi a5,a5,1 + 3003006: fef42423 sw a5,-24(s0) + 300300a: a801 j 300301a + 300300c: fe842703 lw a4,-24(s0) + 3003010: 47a9 li a5,10 + 3003012: 02f757b3 divu a5,a4,a5 + 3003016: fef42423 sw a5,-24(s0) + 300301a: fe042503 lw a0,-32(s0) + 300301e: 3575 jal ra,3002eca + 3003020: 872a mv a4,a0 + 3003022: fec42783 lw a5,-20(s0) + 3003026: 97ba add a5,a5,a4 + 3003028: fef42623 sw a5,-20(s0) + 300302c: 02e00513 li a0,46 + 3003030: 3955 jal ra,3002ce4 + 3003032: fec42783 lw a5,-20(s0) + 3003036: 0785 addi a5,a5,1 + 3003038: fef42623 sw a5,-20(s0) + 300303c: 45a9 li a1,10 + 300303e: fe842503 lw a0,-24(s0) + 3003042: 33bd jal ra,3002db0 + 3003044: fca42c23 sw a0,-40(s0) + 3003048: fc842703 lw a4,-56(s0) + 300304c: fd842783 lw a5,-40(s0) + 3003050: 02e7f763 bgeu a5,a4,300307e + 3003054: fe042223 sw zero,-28(s0) + 3003058: a809 j 300306a + 300305a: 03000513 li a0,48 + 300305e: 3159 jal ra,3002ce4 + 3003060: fe442783 lw a5,-28(s0) + 3003064: 0785 addi a5,a5,1 + 3003066: fef42223 sw a5,-28(s0) + 300306a: fc842703 lw a4,-56(s0) + 300306e: fd842783 lw a5,-40(s0) + 3003072: 40f707b3 sub a5,a4,a5 + 3003076: fe442703 lw a4,-28(s0) + 300307a: fef760e3 bltu a4,a5,300305a + 300307e: fe842783 lw a5,-24(s0) + 3003082: fd842603 lw a2,-40(s0) + 3003086: 45a9 li a1,10 + 3003088: 853e mv a0,a5 + 300308a: 3379 jal ra,3002e18 + 300308c: fec42703 lw a4,-20(s0) + 3003090: fc842783 lw a5,-56(s0) + 3003094: 97ba add a5,a5,a4 + 3003096: fef42623 sw a5,-20(s0) + 300309a: fec42783 lw a5,-20(s0) + 300309e: 853e mv a0,a5 + 30030a0: 50f2 lw ra,60(sp) + 30030a2: 5462 lw s0,56(sp) + 30030a4: 6121 addi sp,sp,64 + 30030a6: 8082 ret + +030030a8 : + 30030a8: 7139 addi sp,sp,-64 + 30030aa: de06 sw ra,60(sp) + 30030ac: dc22 sw s0,56(sp) + 30030ae: 0080 addi s0,sp,64 + 30030b0: 87aa mv a5,a0 + 30030b2: fcb42423 sw a1,-56(s0) + 30030b6: fcf407a3 sb a5,-49(s0) + 30030ba: fe042623 sw zero,-20(s0) + 30030be: fe0405a3 sb zero,-21(s0) + 30030c2: fe042223 sw zero,-28(s0) + 30030c6: fe042023 sw zero,-32(s0) + 30030ca: fc042e23 sw zero,-36(s0) + 30030ce: fc042c23 sw zero,-40(s0) + 30030d2: fc042a23 sw zero,-44(s0) + 30030d6: fcf40783 lb a5,-49(s0) + 30030da: fa878793 addi a5,a5,-88 + 30030de: 02000713 li a4,32 + 30030e2: 14f76063 bltu a4,a5,3003222 + 30030e6: 00279713 slli a4,a5,0x2 + 30030ea: 030057b7 lui a5,0x3005 + 30030ee: 96478793 addi a5,a5,-1692 # 3004964 + 30030f2: 97ba add a5,a5,a4 + 30030f4: 439c lw a5,0(a5) + 30030f6: 8782 jr a5 + 30030f8: fc842783 lw a5,-56(s0) + 30030fc: 439c lw a5,0(a5) + 30030fe: 00478693 addi a3,a5,4 + 3003102: fc842703 lw a4,-56(s0) + 3003106: c314 sw a3,0(a4) + 3003108: 439c lw a5,0(a5) + 300310a: fef405a3 sb a5,-21(s0) + 300310e: feb40783 lb a5,-21(s0) + 3003112: 853e mv a0,a5 + 3003114: 3ec1 jal ra,3002ce4 + 3003116: fec42783 lw a5,-20(s0) + 300311a: 0785 addi a5,a5,1 + 300311c: fef42623 sw a5,-20(s0) + 3003120: aa19 j 3003236 + 3003122: fc842783 lw a5,-56(s0) + 3003126: 439c lw a5,0(a5) + 3003128: 00478693 addi a3,a5,4 + 300312c: fc842703 lw a4,-56(s0) + 3003130: c314 sw a3,0(a4) + 3003132: 439c lw a5,0(a5) + 3003134: fef42223 sw a5,-28(s0) + 3003138: fe442503 lw a0,-28(s0) + 300313c: 36ed jal ra,3002d26 + 300313e: 87aa mv a5,a0 + 3003140: 873e mv a4,a5 + 3003142: fec42783 lw a5,-20(s0) + 3003146: 97ba add a5,a5,a4 + 3003148: fef42623 sw a5,-20(s0) + 300314c: a0ed j 3003236 + 300314e: fc842783 lw a5,-56(s0) + 3003152: 439c lw a5,0(a5) + 3003154: 00478693 addi a3,a5,4 + 3003158: fc842703 lw a4,-56(s0) + 300315c: c314 sw a3,0(a4) + 300315e: 439c lw a5,0(a5) + 3003160: fef42023 sw a5,-32(s0) + 3003164: fe042503 lw a0,-32(s0) + 3003168: 338d jal ra,3002eca + 300316a: 872a mv a4,a0 + 300316c: fec42783 lw a5,-20(s0) + 3003170: 97ba add a5,a5,a4 + 3003172: fef42623 sw a5,-20(s0) + 3003176: a0c1 j 3003236 + 3003178: fc842783 lw a5,-56(s0) + 300317c: 439c lw a5,0(a5) + 300317e: 00478693 addi a3,a5,4 + 3003182: fc842703 lw a4,-56(s0) + 3003186: c314 sw a3,0(a4) + 3003188: 439c lw a5,0(a5) + 300318a: fcf42e23 sw a5,-36(s0) + 300318e: fdc42783 lw a5,-36(s0) + 3003192: 45a9 li a1,10 + 3003194: 853e mv a0,a5 + 3003196: 3929 jal ra,3002db0 + 3003198: fca42823 sw a0,-48(s0) + 300319c: fd042603 lw a2,-48(s0) + 30031a0: 45a9 li a1,10 + 30031a2: fdc42503 lw a0,-36(s0) + 30031a6: 398d jal ra,3002e18 + 30031a8: fec42703 lw a4,-20(s0) + 30031ac: fd042783 lw a5,-48(s0) + 30031b0: 97ba add a5,a5,a4 + 30031b2: fef42623 sw a5,-20(s0) + 30031b6: a041 j 3003236 + 30031b8: fc842783 lw a5,-56(s0) + 30031bc: 439c lw a5,0(a5) + 30031be: 00478693 addi a3,a5,4 + 30031c2: fc842703 lw a4,-56(s0) + 30031c6: c314 sw a3,0(a4) + 30031c8: 439c lw a5,0(a5) + 30031ca: fcf42c23 sw a5,-40(s0) + 30031ce: fd842503 lw a0,-40(s0) + 30031d2: 3b99 jal ra,3002f28 + 30031d4: 872a mv a4,a0 + 30031d6: fec42783 lw a5,-20(s0) + 30031da: 97ba add a5,a5,a4 + 30031dc: fef42623 sw a5,-20(s0) + 30031e0: a899 j 3003236 + 30031e2: fc842783 lw a5,-56(s0) + 30031e6: 439c lw a5,0(a5) + 30031e8: 079d addi a5,a5,7 + 30031ea: 9be1 andi a5,a5,-8 + 30031ec: 00878693 addi a3,a5,8 + 30031f0: fc842703 lw a4,-56(s0) + 30031f4: c314 sw a3,0(a4) + 30031f6: 0047a803 lw a6,4(a5) + 30031fa: 439c lw a5,0(a5) + 30031fc: 853e mv a0,a5 + 30031fe: 85c2 mv a1,a6 + 3003200: 194010ef jal ra,3004394 <__truncdfsf2> + 3003204: 20a507d3 fmv.s fa5,fa0 + 3003208: fcf42a27 fsw fa5,-44(s0) + 300320c: 4515 li a0,5 + 300320e: fd442507 flw fa0,-44(s0) + 3003212: 3ba9 jal ra,3002f6c + 3003214: 872a mv a4,a0 + 3003216: fec42783 lw a5,-20(s0) + 300321a: 97ba add a5,a5,a4 + 300321c: fef42623 sw a5,-20(s0) + 3003220: a819 j 3003236 + 3003222: fcf40783 lb a5,-49(s0) + 3003226: 853e mv a0,a5 + 3003228: 3c75 jal ra,3002ce4 + 300322a: fec42783 lw a5,-20(s0) + 300322e: 0785 addi a5,a5,1 + 3003230: fef42623 sw a5,-20(s0) + 3003234: 0001 nop + 3003236: fec42783 lw a5,-20(s0) + 300323a: 853e mv a0,a5 + 300323c: 50f2 lw ra,60(sp) + 300323e: 5462 lw s0,56(sp) + 3003240: 6121 addi sp,sp,64 + 3003242: 8082 ret + +03003244 : + 3003244: 7139 addi sp,sp,-64 + 3003246: de06 sw ra,60(sp) + 3003248: dc22 sw s0,56(sp) + 300324a: 0080 addi s0,sp,64 + 300324c: fca42623 sw a0,-52(s0) + 3003250: fcb42423 sw a1,-56(s0) + 3003254: fc042e23 sw zero,-36(s0) + 3003258: fe042623 sw zero,-20(s0) + 300325c: fe042423 sw zero,-24(s0) + 3003260: fcc42783 lw a5,-52(s0) + 3003264: e791 bnez a5,3003270 + 3003266: 03000513 li a0,48 + 300326a: 3cad jal ra,3002ce4 + 300326c: 4785 li a5,1 + 300326e: a0dd j 3003354 + 3003270: fcc42783 lw a5,-52(s0) + 3003274: 0607dd63 bgez a5,30032ee + 3003278: 02d00513 li a0,45 + 300327c: 34a5 jal ra,3002ce4 + 300327e: fe842783 lw a5,-24(s0) + 3003282: 0785 addi a5,a5,1 + 3003284: fef42423 sw a5,-24(s0) + 3003288: fcc42783 lw a5,-52(s0) + 300328c: 40f007b3 neg a5,a5 + 3003290: fcf42623 sw a5,-52(s0) + 3003294: 45a9 li a1,10 + 3003296: fcc42503 lw a0,-52(s0) + 300329a: 3e19 jal ra,3002db0 + 300329c: 87aa mv a5,a0 + 300329e: fef42623 sw a5,-20(s0) + 30032a2: fc842703 lw a4,-56(s0) + 30032a6: fec42783 lw a5,-20(s0) + 30032aa: 40f707b3 sub a5,a4,a5 + 30032ae: fcf42e23 sw a5,-36(s0) + 30032b2: fe042223 sw zero,-28(s0) + 30032b6: a831 j 30032d2 + 30032b8: 03000513 li a0,48 + 30032bc: 3425 jal ra,3002ce4 + 30032be: fe842783 lw a5,-24(s0) + 30032c2: 0785 addi a5,a5,1 + 30032c4: fef42423 sw a5,-24(s0) + 30032c8: fe442783 lw a5,-28(s0) + 30032cc: 0785 addi a5,a5,1 + 30032ce: fef42223 sw a5,-28(s0) + 30032d2: fe442703 lw a4,-28(s0) + 30032d6: fdc42783 lw a5,-36(s0) + 30032da: fcf74fe3 blt a4,a5,30032b8 + 30032de: fec42783 lw a5,-20(s0) + 30032e2: fe842703 lw a4,-24(s0) + 30032e6: 97ba add a5,a5,a4 + 30032e8: fef42423 sw a5,-24(s0) + 30032ec: a891 j 3003340 + 30032ee: 45a9 li a1,10 + 30032f0: fcc42503 lw a0,-52(s0) + 30032f4: 3c75 jal ra,3002db0 + 30032f6: 87aa mv a5,a0 + 30032f8: fef42623 sw a5,-20(s0) + 30032fc: fec42783 lw a5,-20(s0) + 3003300: fef42423 sw a5,-24(s0) + 3003304: fc842703 lw a4,-56(s0) + 3003308: fec42783 lw a5,-20(s0) + 300330c: 40f707b3 sub a5,a4,a5 + 3003310: fcf42e23 sw a5,-36(s0) + 3003314: fe042023 sw zero,-32(s0) + 3003318: a831 j 3003334 + 300331a: 03000513 li a0,48 + 300331e: 32d9 jal ra,3002ce4 + 3003320: fe842783 lw a5,-24(s0) + 3003324: 0785 addi a5,a5,1 + 3003326: fef42423 sw a5,-24(s0) + 300332a: fe042783 lw a5,-32(s0) + 300332e: 0785 addi a5,a5,1 + 3003330: fef42023 sw a5,-32(s0) + 3003334: fe042703 lw a4,-32(s0) + 3003338: fdc42783 lw a5,-36(s0) + 300333c: fcf74fe3 blt a4,a5,300331a + 3003340: fcc42783 lw a5,-52(s0) + 3003344: fec42703 lw a4,-20(s0) + 3003348: 863a mv a2,a4 + 300334a: 45a9 li a1,10 + 300334c: 853e mv a0,a5 + 300334e: 34e9 jal ra,3002e18 + 3003350: fe842783 lw a5,-24(s0) + 3003354: 853e mv a0,a5 + 3003356: 50f2 lw ra,60(sp) + 3003358: 5462 lw s0,56(sp) + 300335a: 6121 addi sp,sp,64 + 300335c: 8082 ret + +0300335e : + 300335e: 7179 addi sp,sp,-48 + 3003360: d622 sw s0,44(sp) + 3003362: 1800 addi s0,sp,48 + 3003364: fca42e23 sw a0,-36(s0) + 3003368: fe042623 sw zero,-20(s0) + 300336c: a02d j 3003396 + 300336e: fec42703 lw a4,-20(s0) + 3003372: 47a9 li a5,10 + 3003374: 02f70733 mul a4,a4,a5 + 3003378: fe842783 lw a5,-24(s0) + 300337c: 97ba add a5,a5,a4 + 300337e: fd078793 addi a5,a5,-48 + 3003382: fef42623 sw a5,-20(s0) + 3003386: fdc42783 lw a5,-36(s0) + 300338a: 439c lw a5,0(a5) + 300338c: 00178713 addi a4,a5,1 + 3003390: fdc42783 lw a5,-36(s0) + 3003394: c398 sw a4,0(a5) + 3003396: fdc42783 lw a5,-36(s0) + 300339a: 439c lw a5,0(a5) + 300339c: 00078783 lb a5,0(a5) + 30033a0: fef42423 sw a5,-24(s0) + 30033a4: fe842703 lw a4,-24(s0) + 30033a8: 02f00793 li a5,47 + 30033ac: 00e7d863 bge a5,a4,30033bc + 30033b0: fe842703 lw a4,-24(s0) + 30033b4: 03900793 li a5,57 + 30033b8: fae7dbe3 bge a5,a4,300336e + 30033bc: fec42783 lw a5,-20(s0) + 30033c0: 853e mv a0,a5 + 30033c2: 5432 lw s0,44(sp) + 30033c4: 6145 addi sp,sp,48 + 30033c6: 8082 ret + +030033c8 : + 30033c8: 711d addi sp,sp,-96 + 30033ca: de06 sw ra,60(sp) + 30033cc: dc22 sw s0,56(sp) + 30033ce: 0080 addi s0,sp,64 + 30033d0: fca42623 sw a0,-52(s0) + 30033d4: c04c sw a1,4(s0) + 30033d6: c410 sw a2,8(s0) + 30033d8: c454 sw a3,12(s0) + 30033da: c818 sw a4,16(s0) + 30033dc: c85c sw a5,20(s0) + 30033de: 01042c23 sw a6,24(s0) + 30033e2: 01142e23 sw a7,28(s0) + 30033e6: fe042623 sw zero,-20(s0) + 30033ea: fe042423 sw zero,-24(s0) + 30033ee: fe042223 sw zero,-28(s0) + 30033f2: fe042023 sw zero,-32(s0) + 30033f6: fc042e23 sw zero,-36(s0) + 30033fa: 02040793 addi a5,s0,32 + 30033fe: 1791 addi a5,a5,-28 + 3003400: fcf42c23 sw a5,-40(s0) + 3003404: aa09 j 3003516 + 3003406: fcc42783 lw a5,-52(s0) + 300340a: 00078703 lb a4,0(a5) + 300340e: 02500793 li a5,37 + 3003412: 00f70e63 beq a4,a5,300342e + 3003416: fcc42783 lw a5,-52(s0) + 300341a: 00078783 lb a5,0(a5) + 300341e: 853e mv a0,a5 + 3003420: 30d1 jal ra,3002ce4 + 3003422: fec42783 lw a5,-20(s0) + 3003426: 0785 addi a5,a5,1 + 3003428: fef42623 sw a5,-20(s0) + 300342c: a0c5 j 300350c + 300342e: fcc42783 lw a5,-52(s0) + 3003432: 0785 addi a5,a5,1 + 3003434: fcf42623 sw a5,-52(s0) + 3003438: fcc42783 lw a5,-52(s0) + 300343c: 00078703 lb a4,0(a5) + 3003440: 03000793 li a5,48 + 3003444: 04f71263 bne a4,a5,3003488 + 3003448: fcc42783 lw a5,-52(s0) + 300344c: 0785 addi a5,a5,1 + 300344e: fcf42623 sw a5,-52(s0) + 3003452: fcc40793 addi a5,s0,-52 + 3003456: 853e mv a0,a5 + 3003458: 3719 jal ra,300335e + 300345a: fea42423 sw a0,-24(s0) + 300345e: fd842783 lw a5,-40(s0) + 3003462: 00478713 addi a4,a5,4 + 3003466: fce42c23 sw a4,-40(s0) + 300346a: 439c lw a5,0(a5) + 300346c: fcf42e23 sw a5,-36(s0) + 3003470: fe842583 lw a1,-24(s0) + 3003474: fdc42503 lw a0,-36(s0) + 3003478: 33f1 jal ra,3003244 + 300347a: 872a mv a4,a0 + 300347c: fec42783 lw a5,-20(s0) + 3003480: 97ba add a5,a5,a4 + 3003482: fef42623 sw a5,-20(s0) + 3003486: a059 j 300350c + 3003488: fcc42783 lw a5,-52(s0) + 300348c: 00078703 lb a4,0(a5) + 3003490: 02e00793 li a5,46 + 3003494: 04f71d63 bne a4,a5,30034ee + 3003498: fcc42783 lw a5,-52(s0) + 300349c: 0785 addi a5,a5,1 + 300349e: fcf42623 sw a5,-52(s0) + 30034a2: fcc40793 addi a5,s0,-52 + 30034a6: 853e mv a0,a5 + 30034a8: 3d5d jal ra,300335e + 30034aa: fea42223 sw a0,-28(s0) + 30034ae: fd842783 lw a5,-40(s0) + 30034b2: 079d addi a5,a5,7 + 30034b4: 9be1 andi a5,a5,-8 + 30034b6: 00878713 addi a4,a5,8 + 30034ba: fce42c23 sw a4,-40(s0) + 30034be: 0047a803 lw a6,4(a5) + 30034c2: 439c lw a5,0(a5) + 30034c4: 853e mv a0,a5 + 30034c6: 85c2 mv a1,a6 + 30034c8: 6cd000ef jal ra,3004394 <__truncdfsf2> + 30034cc: 20a507d3 fmv.s fa5,fa0 + 30034d0: fef42027 fsw fa5,-32(s0) + 30034d4: fe442783 lw a5,-28(s0) + 30034d8: 853e mv a0,a5 + 30034da: fe042507 flw fa0,-32(s0) + 30034de: 3479 jal ra,3002f6c + 30034e0: 872a mv a4,a0 + 30034e2: fec42783 lw a5,-20(s0) + 30034e6: 97ba add a5,a5,a4 + 30034e8: fef42623 sw a5,-20(s0) + 30034ec: a005 j 300350c + 30034ee: fcc42783 lw a5,-52(s0) + 30034f2: 00078783 lb a5,0(a5) + 30034f6: fd840713 addi a4,s0,-40 + 30034fa: 85ba mv a1,a4 + 30034fc: 853e mv a0,a5 + 30034fe: 366d jal ra,30030a8 + 3003500: 872a mv a4,a0 + 3003502: fec42783 lw a5,-20(s0) + 3003506: 97ba add a5,a5,a4 + 3003508: fef42623 sw a5,-20(s0) + 300350c: fcc42783 lw a5,-52(s0) + 3003510: 0785 addi a5,a5,1 + 3003512: fcf42623 sw a5,-52(s0) + 3003516: fcc42783 lw a5,-52(s0) + 300351a: 00078783 lb a5,0(a5) + 300351e: ee0794e3 bnez a5,3003406 + 3003522: fec42783 lw a5,-20(s0) + 3003526: 853e mv a0,a5 + 3003528: 50f2 lw ra,60(sp) + 300352a: 5462 lw s0,56(sp) + 300352c: 6125 addi sp,sp,96 + 300352e: 8082 ret + +03003530 : + 3003530: 1101 addi sp,sp,-32 + 3003532: ce22 sw s0,28(sp) + 3003534: 1000 addi s0,sp,32 + 3003536: fea42623 sw a0,-20(s0) + 300353a: feb42423 sw a1,-24(s0) + 300353e: fec42223 sw a2,-28(s0) + 3003542: fe442703 lw a4,-28(s0) + 3003546: 4785 li a5,1 + 3003548: 00f71563 bne a4,a5,3003552 + 300354c: fe842783 lw a5,-24(s0) + 3003550: a011 j 3003554 + 3003552: 4781 li a5,0 + 3003554: fec42683 lw a3,-20(s0) + 3003558: fe842703 lw a4,-24(s0) + 300355c: 070a slli a4,a4,0x2 + 300355e: 9736 add a4,a4,a3 + 3003560: c31c sw a5,0(a4) + 3003562: 0001 nop + 3003564: 4472 lw s0,28(sp) + 3003566: 6105 addi sp,sp,32 + 3003568: 8082 ret + +0300356a : + 300356a: 1101 addi sp,sp,-32 + 300356c: ce22 sw s0,28(sp) + 300356e: 1000 addi s0,sp,32 + 3003570: fea42623 sw a0,-20(s0) + 3003574: feb42423 sw a1,-24(s0) + 3003578: fec42223 sw a2,-28(s0) + 300357c: fe442783 lw a5,-28(s0) + 3003580: ef99 bnez a5,300359e + 3003582: fec42783 lw a5,-20(s0) + 3003586: 4007a703 lw a4,1024(a5) + 300358a: fe842783 lw a5,-24(s0) + 300358e: fff7c793 not a5,a5 + 3003592: 8f7d and a4,a4,a5 + 3003594: fec42783 lw a5,-20(s0) + 3003598: 40e7a023 sw a4,1024(a5) + 300359c: a00d j 30035be + 300359e: fe442703 lw a4,-28(s0) + 30035a2: 4785 li a5,1 + 30035a4: 00f71d63 bne a4,a5,30035be + 30035a8: fec42783 lw a5,-20(s0) + 30035ac: 4007a703 lw a4,1024(a5) + 30035b0: fe842783 lw a5,-24(s0) + 30035b4: 8f5d or a4,a4,a5 + 30035b6: fec42783 lw a5,-20(s0) + 30035ba: 40e7a023 sw a4,1024(a5) + 30035be: 0001 nop + 30035c0: 4472 lw s0,28(sp) + 30035c2: 6105 addi sp,sp,32 + 30035c4: 8082 ret + +030035c6 : + 30035c6: 1101 addi sp,sp,-32 + 30035c8: ce22 sw s0,28(sp) + 30035ca: 1000 addi s0,sp,32 + 30035cc: fea42623 sw a0,-20(s0) + 30035d0: feb42423 sw a1,-24(s0) + 30035d4: fec42783 lw a5,-20(s0) + 30035d8: 41c7a703 lw a4,1052(a5) + 30035dc: fe842783 lw a5,-24(s0) + 30035e0: 8f5d or a4,a4,a5 + 30035e2: fec42783 lw a5,-20(s0) + 30035e6: 40e7ae23 sw a4,1052(a5) + 30035ea: 0001 nop + 30035ec: 4472 lw s0,28(sp) + 30035ee: 6105 addi sp,sp,32 + 30035f0: 8082 ret + +030035f2 : + 30035f2: 1101 addi sp,sp,-32 + 30035f4: ce06 sw ra,28(sp) + 30035f6: cc22 sw s0,24(sp) + 30035f8: 1000 addi s0,sp,32 + 30035fa: fea42623 sw a0,-20(s0) + 30035fe: feb42423 sw a1,-24(s0) + 3003602: fe842583 lw a1,-24(s0) + 3003606: fec42503 lw a0,-20(s0) + 300360a: 3f75 jal ra,30035c6 + 300360c: fec42783 lw a5,-20(s0) + 3003610: 4107a703 lw a4,1040(a5) + 3003614: fe842783 lw a5,-24(s0) + 3003618: 8f5d or a4,a4,a5 + 300361a: fec42783 lw a5,-20(s0) + 300361e: 40e7a823 sw a4,1040(a5) + 3003622: 0001 nop + 3003624: 40f2 lw ra,28(sp) + 3003626: 4462 lw s0,24(sp) + 3003628: 6105 addi sp,sp,32 + 300362a: 8082 ret + +0300362c : + 300362c: 1101 addi sp,sp,-32 + 300362e: ce22 sw s0,28(sp) + 3003630: 1000 addi s0,sp,32 + 3003632: fea42623 sw a0,-20(s0) + 3003636: feb42423 sw a1,-24(s0) + 300363a: fec42783 lw a5,-20(s0) + 300363e: 4107a703 lw a4,1040(a5) + 3003642: fe842783 lw a5,-24(s0) + 3003646: fff7c793 not a5,a5 + 300364a: 8f7d and a4,a4,a5 + 300364c: fec42783 lw a5,-20(s0) + 3003650: 40e7a823 sw a4,1040(a5) + 3003654: 0001 nop + 3003656: 4472 lw s0,28(sp) + 3003658: 6105 addi sp,sp,32 + 300365a: 8082 ret + +0300365c : + 300365c: 7179 addi sp,sp,-48 + 300365e: d622 sw s0,44(sp) + 3003660: 1800 addi s0,sp,48 + 3003662: fca42e23 sw a0,-36(s0) + 3003666: fe042623 sw zero,-20(s0) + 300366a: a01d j 3003690 + 300366c: 4705 li a4,1 + 300366e: fec42783 lw a5,-20(s0) + 3003672: 00f717b3 sll a5,a4,a5 + 3003676: 86be mv a3,a5 + 3003678: fdc42703 lw a4,-36(s0) + 300367c: fec42783 lw a5,-20(s0) + 3003680: 078e slli a5,a5,0x3 + 3003682: 97ba add a5,a5,a4 + 3003684: c794 sw a3,8(a5) + 3003686: fec42783 lw a5,-20(s0) + 300368a: 0785 addi a5,a5,1 + 300368c: fef42623 sw a5,-20(s0) + 3003690: fec42703 lw a4,-20(s0) + 3003694: 479d li a5,7 + 3003696: fce7fbe3 bgeu a5,a4,300366c + 300369a: 0001 nop + 300369c: 5432 lw s0,44(sp) + 300369e: 6145 addi sp,sp,48 + 30036a0: 8082 ret + +030036a2 : + 30036a2: 1101 addi sp,sp,-32 + 30036a4: ce06 sw ra,28(sp) + 30036a6: cc22 sw s0,24(sp) + 30036a8: 1000 addi s0,sp,32 + 30036aa: fea42623 sw a0,-20(s0) + 30036ae: feb42423 sw a1,-24(s0) + 30036b2: fec42223 sw a2,-28(s0) + 30036b6: fec42783 lw a5,-20(s0) + 30036ba: 439c lw a5,0(a5) + 30036bc: fe442603 lw a2,-28(s0) + 30036c0: fe842583 lw a1,-24(s0) + 30036c4: 853e mv a0,a5 + 30036c6: 3555 jal ra,300356a + 30036c8: 0001 nop + 30036ca: 40f2 lw ra,28(sp) + 30036cc: 4462 lw s0,24(sp) + 30036ce: 6105 addi sp,sp,32 + 30036d0: 8082 ret + +030036d2 : + 30036d2: 1101 addi sp,sp,-32 + 30036d4: ce06 sw ra,28(sp) + 30036d6: cc22 sw s0,24(sp) + 30036d8: 1000 addi s0,sp,32 + 30036da: fea42623 sw a0,-20(s0) + 30036de: feb42423 sw a1,-24(s0) + 30036e2: fec42223 sw a2,-28(s0) + 30036e6: fec42783 lw a5,-20(s0) + 30036ea: 439c lw a5,0(a5) + 30036ec: fe442603 lw a2,-28(s0) + 30036f0: fe842583 lw a1,-24(s0) + 30036f4: 853e mv a0,a5 + 30036f6: 3d2d jal ra,3003530 + 30036f8: 0001 nop + 30036fa: 40f2 lw ra,28(sp) + 30036fc: 4462 lw s0,24(sp) + 30036fe: 6105 addi sp,sp,32 + 3003700: 8082 ret + +03003702 : + 3003702: 1101 addi sp,sp,-32 + 3003704: ce22 sw s0,28(sp) + 3003706: 1000 addi s0,sp,32 + 3003708: fea42623 sw a0,-20(s0) + 300370c: feb42423 sw a1,-24(s0) + 3003710: fec42783 lw a5,-20(s0) + 3003714: 4398 lw a4,0(a5) + 3003716: fe842783 lw a5,-24(s0) + 300371a: 078a slli a5,a5,0x2 + 300371c: 97ba add a5,a5,a4 + 300371e: 4398 lw a4,0(a5) + 3003720: fec42783 lw a5,-20(s0) + 3003724: 4394 lw a3,0(a5) + 3003726: fe842783 lw a5,-24(s0) + 300372a: 8f3d xor a4,a4,a5 + 300372c: fe842783 lw a5,-24(s0) + 3003730: 078a slli a5,a5,0x2 + 3003732: 97b6 add a5,a5,a3 + 3003734: c398 sw a4,0(a5) + 3003736: 0001 nop + 3003738: 4472 lw s0,28(sp) + 300373a: 6105 addi sp,sp,32 + 300373c: 8082 ret + +0300373e : + 300373e: 1101 addi sp,sp,-32 + 3003740: ce22 sw s0,28(sp) + 3003742: 1000 addi s0,sp,32 + 3003744: fea42623 sw a0,-20(s0) + 3003748: feb42423 sw a1,-24(s0) + 300374c: fec42223 sw a2,-28(s0) + 3003750: fec42783 lw a5,-20(s0) + 3003754: 439c lw a5,0(a5) + 3003756: 4087a683 lw a3,1032(a5) + 300375a: fe842783 lw a5,-24(s0) + 300375e: fff7c713 not a4,a5 + 3003762: fec42783 lw a5,-20(s0) + 3003766: 439c lw a5,0(a5) + 3003768: 8f75 and a4,a4,a3 + 300376a: 40e7a423 sw a4,1032(a5) + 300376e: fec42783 lw a5,-20(s0) + 3003772: 439c lw a5,0(a5) + 3003774: 4047a683 lw a3,1028(a5) + 3003778: fec42783 lw a5,-20(s0) + 300377c: 439c lw a5,0(a5) + 300377e: fe842703 lw a4,-24(s0) + 3003782: 8f55 or a4,a4,a3 + 3003784: 40e7a223 sw a4,1028(a5) + 3003788: fe442703 lw a4,-28(s0) + 300378c: 478d li a5,3 + 300378e: 02f71063 bne a4,a5,30037ae + 3003792: fec42783 lw a5,-20(s0) + 3003796: 439c lw a5,0(a5) + 3003798: 40c7a683 lw a3,1036(a5) + 300379c: fec42783 lw a5,-20(s0) + 30037a0: 439c lw a5,0(a5) + 30037a2: fe842703 lw a4,-24(s0) + 30037a6: 8f55 or a4,a4,a3 + 30037a8: 40e7a623 sw a4,1036(a5) + 30037ac: a005 j 30037cc + 30037ae: fec42783 lw a5,-20(s0) + 30037b2: 439c lw a5,0(a5) + 30037b4: 40c7a683 lw a3,1036(a5) + 30037b8: fe842783 lw a5,-24(s0) + 30037bc: fff7c713 not a4,a5 + 30037c0: fec42783 lw a5,-20(s0) + 30037c4: 439c lw a5,0(a5) + 30037c6: 8f75 and a4,a4,a3 + 30037c8: 40e7a623 sw a4,1036(a5) + 30037cc: 0001 nop + 30037ce: 4472 lw s0,28(sp) + 30037d0: 6105 addi sp,sp,32 + 30037d2: 8082 ret + +030037d4 : + 30037d4: 1101 addi sp,sp,-32 + 30037d6: ce22 sw s0,28(sp) + 30037d8: 1000 addi s0,sp,32 + 30037da: fea42623 sw a0,-20(s0) + 30037de: feb42423 sw a1,-24(s0) + 30037e2: fec42223 sw a2,-28(s0) + 30037e6: fec42783 lw a5,-20(s0) + 30037ea: 439c lw a5,0(a5) + 30037ec: 4047a683 lw a3,1028(a5) + 30037f0: fe842783 lw a5,-24(s0) + 30037f4: fff7c713 not a4,a5 + 30037f8: fec42783 lw a5,-20(s0) + 30037fc: 439c lw a5,0(a5) + 30037fe: 8f75 and a4,a4,a3 + 3003800: 40e7a223 sw a4,1028(a5) + 3003804: fec42783 lw a5,-20(s0) + 3003808: 439c lw a5,0(a5) + 300380a: 4087a683 lw a3,1032(a5) + 300380e: fe842783 lw a5,-24(s0) + 3003812: fff7c713 not a4,a5 + 3003816: fec42783 lw a5,-20(s0) + 300381a: 439c lw a5,0(a5) + 300381c: 8f75 and a4,a4,a3 + 300381e: 40e7a423 sw a4,1032(a5) + 3003822: fe442703 lw a4,-28(s0) + 3003826: 4785 li a5,1 + 3003828: 02f71063 bne a4,a5,3003848 + 300382c: fec42783 lw a5,-20(s0) + 3003830: 439c lw a5,0(a5) + 3003832: 40c7a683 lw a3,1036(a5) + 3003836: fec42783 lw a5,-20(s0) + 300383a: 439c lw a5,0(a5) + 300383c: fe842703 lw a4,-24(s0) + 3003840: 8f55 or a4,a4,a3 + 3003842: 40e7a623 sw a4,1036(a5) + 3003846: a005 j 3003866 + 3003848: fec42783 lw a5,-20(s0) + 300384c: 439c lw a5,0(a5) + 300384e: 40c7a683 lw a3,1036(a5) + 3003852: fe842783 lw a5,-24(s0) + 3003856: fff7c713 not a4,a5 + 300385a: fec42783 lw a5,-20(s0) + 300385e: 439c lw a5,0(a5) + 3003860: 8f75 and a4,a4,a3 + 3003862: 40e7a623 sw a4,1036(a5) + 3003866: 0001 nop + 3003868: 4472 lw s0,28(sp) + 300386a: 6105 addi sp,sp,32 + 300386c: 8082 ret + +0300386e : + 300386e: 1101 addi sp,sp,-32 + 3003870: ce06 sw ra,28(sp) + 3003872: cc22 sw s0,24(sp) + 3003874: 1000 addi s0,sp,32 + 3003876: fea42623 sw a0,-20(s0) + 300387a: feb42423 sw a1,-24(s0) + 300387e: fec42223 sw a2,-28(s0) + 3003882: fec42783 lw a5,-20(s0) + 3003886: 439c lw a5,0(a5) + 3003888: fe842583 lw a1,-24(s0) + 300388c: 853e mv a0,a5 + 300388e: 3b79 jal ra,300362c + 3003890: fe442703 lw a4,-28(s0) + 3003894: 478d li a5,3 + 3003896: 00f70763 beq a4,a5,30038a4 + 300389a: fe442703 lw a4,-28(s0) + 300389e: 4789 li a5,2 + 30038a0: 00f71a63 bne a4,a5,30038b4 + 30038a4: fe442603 lw a2,-28(s0) + 30038a8: fe842583 lw a1,-24(s0) + 30038ac: fec42503 lw a0,-20(s0) + 30038b0: 3579 jal ra,300373e + 30038b2: a0f5 j 300399e + 30038b4: fe442703 lw a4,-28(s0) + 30038b8: 4791 li a5,4 + 30038ba: 04f71e63 bne a4,a5,3003916 + 30038be: fec42783 lw a5,-20(s0) + 30038c2: 439c lw a5,0(a5) + 30038c4: 40c7a683 lw a3,1036(a5) + 30038c8: fe842783 lw a5,-24(s0) + 30038cc: fff7c713 not a4,a5 + 30038d0: fec42783 lw a5,-20(s0) + 30038d4: 439c lw a5,0(a5) + 30038d6: 8f75 and a4,a4,a3 + 30038d8: 40e7a623 sw a4,1036(a5) + 30038dc: fec42783 lw a5,-20(s0) + 30038e0: 439c lw a5,0(a5) + 30038e2: 4047a683 lw a3,1028(a5) + 30038e6: fe842783 lw a5,-24(s0) + 30038ea: fff7c713 not a4,a5 + 30038ee: fec42783 lw a5,-20(s0) + 30038f2: 439c lw a5,0(a5) + 30038f4: 8f75 and a4,a4,a3 + 30038f6: 40e7a223 sw a4,1028(a5) + 30038fa: fec42783 lw a5,-20(s0) + 30038fe: 439c lw a5,0(a5) + 3003900: 4087a683 lw a3,1032(a5) + 3003904: fec42783 lw a5,-20(s0) + 3003908: 439c lw a5,0(a5) + 300390a: fe842703 lw a4,-24(s0) + 300390e: 8f55 or a4,a4,a3 + 3003910: 40e7a423 sw a4,1032(a5) + 3003914: a069 j 300399e + 3003916: fe442703 lw a4,-28(s0) + 300391a: 4785 li a5,1 + 300391c: 00f70563 beq a4,a5,3003926 + 3003920: fe442783 lw a5,-28(s0) + 3003924: eb89 bnez a5,3003936 + 3003926: fe442603 lw a2,-28(s0) + 300392a: fe842583 lw a1,-24(s0) + 300392e: fec42503 lw a0,-20(s0) + 3003932: 354d jal ra,30037d4 + 3003934: a0ad j 300399e + 3003936: fe442703 lw a4,-28(s0) + 300393a: 4795 li a5,5 + 300393c: 06f71163 bne a4,a5,300399e + 3003940: fec42783 lw a5,-20(s0) + 3003944: 439c lw a5,0(a5) + 3003946: 40c7a683 lw a3,1036(a5) + 300394a: fe842783 lw a5,-24(s0) + 300394e: fff7c713 not a4,a5 + 3003952: fec42783 lw a5,-20(s0) + 3003956: 439c lw a5,0(a5) + 3003958: 8f75 and a4,a4,a3 + 300395a: 40e7a623 sw a4,1036(a5) + 300395e: fec42783 lw a5,-20(s0) + 3003962: 439c lw a5,0(a5) + 3003964: 4047a683 lw a3,1028(a5) + 3003968: fe842783 lw a5,-24(s0) + 300396c: fff7c713 not a4,a5 + 3003970: fec42783 lw a5,-20(s0) + 3003974: 439c lw a5,0(a5) + 3003976: 8f75 and a4,a4,a3 + 3003978: 40e7a223 sw a4,1028(a5) + 300397c: fec42783 lw a5,-20(s0) + 3003980: 439c lw a5,0(a5) + 3003982: 4087a683 lw a3,1032(a5) + 3003986: fe842783 lw a5,-24(s0) + 300398a: fff7c713 not a4,a5 + 300398e: fec42783 lw a5,-20(s0) + 3003992: 439c lw a5,0(a5) + 3003994: 8f75 and a4,a4,a3 + 3003996: 40e7a423 sw a4,1032(a5) + 300399a: 4785 li a5,1 + 300399c: a809 j 30039ae + 300399e: fec42783 lw a5,-20(s0) + 30039a2: 439c lw a5,0(a5) + 30039a4: fe842583 lw a1,-24(s0) + 30039a8: 853e mv a0,a5 + 30039aa: 31a1 jal ra,30035f2 + 30039ac: 4781 li a5,0 + 30039ae: 853e mv a0,a5 + 30039b0: 40f2 lw ra,28(sp) + 30039b2: 4462 lw s0,24(sp) + 30039b4: 6105 addi sp,sp,32 + 30039b6: 8082 ret + +030039b8 : + 30039b8: 1101 addi sp,sp,-32 + 30039ba: ce22 sw s0,28(sp) + 30039bc: 1000 addi s0,sp,32 + 30039be: fea42623 sw a0,-20(s0) + 30039c2: feb42423 sw a1,-24(s0) + 30039c6: fec42783 lw a5,-20(s0) + 30039ca: fe842703 lw a4,-24(s0) + 30039ce: c398 sw a4,0(a5) + 30039d0: 0001 nop + 30039d2: 4472 lw s0,28(sp) + 30039d4: 6105 addi sp,sp,32 + 30039d6: 8082 ret + +030039d8 : + 30039d8: 1101 addi sp,sp,-32 + 30039da: ce22 sw s0,28(sp) + 30039dc: 1000 addi s0,sp,32 + 30039de: fea42623 sw a0,-20(s0) + 30039e2: feb42423 sw a1,-24(s0) + 30039e6: fe842783 lw a5,-24(s0) + 30039ea: 8b8d andi a5,a5,3 + 30039ec: 0ff7f693 andi a3,a5,255 + 30039f0: fec42703 lw a4,-20(s0) + 30039f4: 431c lw a5,0(a4) + 30039f6: 8a8d andi a3,a3,3 + 30039f8: 0692 slli a3,a3,0x4 + 30039fa: fcf7f793 andi a5,a5,-49 + 30039fe: 8fd5 or a5,a5,a3 + 3003a00: c31c sw a5,0(a4) + 3003a02: 0001 nop + 3003a04: 4472 lw s0,28(sp) + 3003a06: 6105 addi sp,sp,32 + 3003a08: 8082 ret + +03003a0a : + 3003a0a: 1101 addi sp,sp,-32 + 3003a0c: ce22 sw s0,28(sp) + 3003a0e: 1000 addi s0,sp,32 + 3003a10: fea42623 sw a0,-20(s0) + 3003a14: feb42423 sw a1,-24(s0) + 3003a18: fe842783 lw a5,-24(s0) + 3003a1c: 8385 srli a5,a5,0x1 + 3003a1e: 8b85 andi a5,a5,1 + 3003a20: 0ff7f693 andi a3,a5,255 + 3003a24: fec42703 lw a4,-20(s0) + 3003a28: 431c lw a5,0(a4) + 3003a2a: 8a85 andi a3,a3,1 + 3003a2c: 06a2 slli a3,a3,0x8 + 3003a2e: eff7f793 andi a5,a5,-257 + 3003a32: 8fd5 or a5,a5,a3 + 3003a34: c31c sw a5,0(a4) + 3003a36: fe842783 lw a5,-24(s0) + 3003a3a: 8b85 andi a5,a5,1 + 3003a3c: 0ff7f693 andi a3,a5,255 + 3003a40: fec42703 lw a4,-20(s0) + 3003a44: 431c lw a5,0(a4) + 3003a46: 8a85 andi a3,a3,1 + 3003a48: 069e slli a3,a3,0x7 + 3003a4a: f7f7f793 andi a5,a5,-129 + 3003a4e: 8fd5 or a5,a5,a3 + 3003a50: c31c sw a5,0(a4) + 3003a52: 0001 nop + 3003a54: 4472 lw s0,28(sp) + 3003a56: 6105 addi sp,sp,32 + 3003a58: 8082 ret + +03003a5a : + 3003a5a: 1101 addi sp,sp,-32 + 3003a5c: ce22 sw s0,28(sp) + 3003a5e: 1000 addi s0,sp,32 + 3003a60: fea42623 sw a0,-20(s0) + 3003a64: feb42423 sw a1,-24(s0) + 3003a68: fe842783 lw a5,-24(s0) + 3003a6c: 8b85 andi a5,a5,1 + 3003a6e: 0ff7f693 andi a3,a5,255 + 3003a72: fec42703 lw a4,-20(s0) + 3003a76: 431c lw a5,0(a4) + 3003a78: 8a85 andi a3,a3,1 + 3003a7a: 06a6 slli a3,a3,0x9 + 3003a7c: dff7f793 andi a5,a5,-513 + 3003a80: 8fd5 or a5,a5,a3 + 3003a82: c31c sw a5,0(a4) + 3003a84: 0001 nop + 3003a86: 4472 lw s0,28(sp) + 3003a88: 6105 addi sp,sp,32 + 3003a8a: 8082 ret + +03003a8c : + 3003a8c: 1101 addi sp,sp,-32 + 3003a8e: ce22 sw s0,28(sp) + 3003a90: 1000 addi s0,sp,32 + 3003a92: fea42623 sw a0,-20(s0) + 3003a96: feb42423 sw a1,-24(s0) + 3003a9a: fe842783 lw a5,-24(s0) + 3003a9e: 8b85 andi a5,a5,1 + 3003aa0: 0ff7f693 andi a3,a5,255 + 3003aa4: fec42703 lw a4,-20(s0) + 3003aa8: 431c lw a5,0(a4) + 3003aaa: 8a85 andi a3,a3,1 + 3003aac: 06aa slli a3,a3,0xa + 3003aae: bff7f793 andi a5,a5,-1025 + 3003ab2: 8fd5 or a5,a5,a3 + 3003ab4: c31c sw a5,0(a4) + 3003ab6: 0001 nop + 3003ab8: 4472 lw s0,28(sp) + 3003aba: 6105 addi sp,sp,32 + 3003abc: 8082 ret + +03003abe : + 3003abe: 7179 addi sp,sp,-48 + 3003ac0: d622 sw s0,44(sp) + 3003ac2: 1800 addi s0,sp,48 + 3003ac4: fca42e23 sw a0,-36(s0) + 3003ac8: fdc42783 lw a5,-36(s0) + 3003acc: 0087d713 srli a4,a5,0x8 + 3003ad0: 00ff07b7 lui a5,0xff0 + 3003ad4: 8f7d and a4,a4,a5 + 3003ad6: 147e07b7 lui a5,0x147e0 + 3003ada: 97ba add a5,a5,a4 + 3003adc: fef42623 sw a5,-20(s0) + 3003ae0: fdc42783 lw a5,-36(s0) + 3003ae4: 83c1 srli a5,a5,0x10 + 3003ae6: 0ff7f793 andi a5,a5,255 + 3003aea: fef42423 sw a5,-24(s0) + 3003aee: fec42703 lw a4,-20(s0) + 3003af2: fe842783 lw a5,-24(s0) + 3003af6: 97ba add a5,a5,a4 + 3003af8: fef42223 sw a5,-28(s0) + 3003afc: fe442703 lw a4,-28(s0) + 3003b00: 77c1 lui a5,0xffff0 + 3003b02: 8f7d and a4,a4,a5 + 3003b04: 147e07b7 lui a5,0x147e0 + 3003b08: 02f70c63 beq a4,a5,3003b40 + 3003b0c: fe442703 lw a4,-28(s0) + 3003b10: 77c1 lui a5,0xffff0 + 3003b12: 8f7d and a4,a4,a5 + 3003b14: 147e07b7 lui a5,0x147e0 + 3003b18: 02f70463 beq a4,a5,3003b40 + 3003b1c: fe442703 lw a4,-28(s0) + 3003b20: 77c1 lui a5,0xffff0 + 3003b22: 8f7d and a4,a4,a5 + 3003b24: 147f07b7 lui a5,0x147f0 + 3003b28: 00f70c63 beq a4,a5,3003b40 + 3003b2c: fe442703 lw a4,-28(s0) + 3003b30: 77c1 lui a5,0xffff0 + 3003b32: 8f7d and a4,a4,a5 + 3003b34: 149f07b7 lui a5,0x149f0 + 3003b38: 00f70463 beq a4,a5,3003b40 + 3003b3c: 4781 li a5,0 + 3003b3e: a019 j 3003b44 + 3003b40: fe442783 lw a5,-28(s0) + 3003b44: 853e mv a0,a5 + 3003b46: 5432 lw s0,44(sp) + 3003b48: 6145 addi sp,sp,48 + 3003b4a: 8082 ret + +03003b4c : + 3003b4c: 7179 addi sp,sp,-48 + 3003b4e: d606 sw ra,44(sp) + 3003b50: d422 sw s0,40(sp) + 3003b52: 1800 addi s0,sp,48 + 3003b54: fca42e23 sw a0,-36(s0) + 3003b58: fdc42503 lw a0,-36(s0) + 3003b5c: 378d jal ra,3003abe + 3003b5e: fea42623 sw a0,-20(s0) + 3003b62: fec42703 lw a4,-20(s0) + 3003b66: 77c1 lui a5,0xffff0 + 3003b68: 8f7d and a4,a4,a5 + 3003b6a: 147e07b7 lui a5,0x147e0 + 3003b6e: 02f70c63 beq a4,a5,3003ba6 + 3003b72: fec42703 lw a4,-20(s0) + 3003b76: 77c1 lui a5,0xffff0 + 3003b78: 8f7d and a4,a4,a5 + 3003b7a: 147e07b7 lui a5,0x147e0 + 3003b7e: 02f70463 beq a4,a5,3003ba6 + 3003b82: fec42703 lw a4,-20(s0) + 3003b86: 77c1 lui a5,0xffff0 + 3003b88: 8f7d and a4,a4,a5 + 3003b8a: 147f07b7 lui a5,0x147f0 + 3003b8e: 00f70c63 beq a4,a5,3003ba6 + 3003b92: fec42703 lw a4,-20(s0) + 3003b96: 77c1 lui a5,0xffff0 + 3003b98: 8f7d and a4,a4,a5 + 3003b9a: 149f07b7 lui a5,0x149f0 + 3003b9e: 00f70463 beq a4,a5,3003ba6 + 3003ba2: 4789 li a5,2 + 3003ba4: a831 j 3003bc0 + 3003ba6: fdc42703 lw a4,-36(s0) + 3003baa: 67c1 lui a5,0x10 + 3003bac: 17fd addi a5,a5,-1 # ffff + 3003bae: 8ff9 and a5,a5,a4 + 3003bb0: fef42423 sw a5,-24(s0) + 3003bb4: fe842583 lw a1,-24(s0) + 3003bb8: fec42503 lw a0,-20(s0) + 3003bbc: 3bf5 jal ra,30039b8 + 3003bbe: 4781 li a5,0 + 3003bc0: 853e mv a0,a5 + 3003bc2: 50b2 lw ra,44(sp) + 3003bc4: 5422 lw s0,40(sp) + 3003bc6: 6145 addi sp,sp,48 + 3003bc8: 8082 ret + +03003bca : + 3003bca: 7179 addi sp,sp,-48 + 3003bcc: d606 sw ra,44(sp) + 3003bce: d422 sw s0,40(sp) + 3003bd0: 1800 addi s0,sp,48 + 3003bd2: fca42e23 sw a0,-36(s0) + 3003bd6: fcb42c23 sw a1,-40(s0) + 3003bda: fdc42503 lw a0,-36(s0) + 3003bde: 35c5 jal ra,3003abe + 3003be0: fea42623 sw a0,-20(s0) + 3003be4: fec42703 lw a4,-20(s0) + 3003be8: 77c1 lui a5,0xffff0 + 3003bea: 8f7d and a4,a4,a5 + 3003bec: 147e07b7 lui a5,0x147e0 + 3003bf0: 02f70c63 beq a4,a5,3003c28 + 3003bf4: fec42703 lw a4,-20(s0) + 3003bf8: 77c1 lui a5,0xffff0 + 3003bfa: 8f7d and a4,a4,a5 + 3003bfc: 147e07b7 lui a5,0x147e0 + 3003c00: 02f70463 beq a4,a5,3003c28 + 3003c04: fec42703 lw a4,-20(s0) + 3003c08: 77c1 lui a5,0xffff0 + 3003c0a: 8f7d and a4,a4,a5 + 3003c0c: 147f07b7 lui a5,0x147f0 + 3003c10: 00f70c63 beq a4,a5,3003c28 + 3003c14: fec42703 lw a4,-20(s0) + 3003c18: 77c1 lui a5,0xffff0 + 3003c1a: 8f7d and a4,a4,a5 + 3003c1c: 149f07b7 lui a5,0x149f0 + 3003c20: 00f70463 beq a4,a5,3003c28 + 3003c24: 4789 li a5,2 + 3003c26: a039 j 3003c34 + 3003c28: fd842583 lw a1,-40(s0) + 3003c2c: fec42503 lw a0,-20(s0) + 3003c30: 3be9 jal ra,3003a0a + 3003c32: 4781 li a5,0 + 3003c34: 853e mv a0,a5 + 3003c36: 50b2 lw ra,44(sp) + 3003c38: 5422 lw s0,40(sp) + 3003c3a: 6145 addi sp,sp,48 + 3003c3c: 8082 ret + +03003c3e : + 3003c3e: 7179 addi sp,sp,-48 + 3003c40: d606 sw ra,44(sp) + 3003c42: d422 sw s0,40(sp) + 3003c44: 1800 addi s0,sp,48 + 3003c46: fca42e23 sw a0,-36(s0) + 3003c4a: fcb42c23 sw a1,-40(s0) + 3003c4e: fdc42503 lw a0,-36(s0) + 3003c52: 35b5 jal ra,3003abe + 3003c54: fea42623 sw a0,-20(s0) + 3003c58: fec42703 lw a4,-20(s0) + 3003c5c: 77c1 lui a5,0xffff0 + 3003c5e: 8f7d and a4,a4,a5 + 3003c60: 147e07b7 lui a5,0x147e0 + 3003c64: 02f70c63 beq a4,a5,3003c9c + 3003c68: fec42703 lw a4,-20(s0) + 3003c6c: 77c1 lui a5,0xffff0 + 3003c6e: 8f7d and a4,a4,a5 + 3003c70: 147e07b7 lui a5,0x147e0 + 3003c74: 02f70463 beq a4,a5,3003c9c + 3003c78: fec42703 lw a4,-20(s0) + 3003c7c: 77c1 lui a5,0xffff0 + 3003c7e: 8f7d and a4,a4,a5 + 3003c80: 147f07b7 lui a5,0x147f0 + 3003c84: 00f70c63 beq a4,a5,3003c9c + 3003c88: fec42703 lw a4,-20(s0) + 3003c8c: 77c1 lui a5,0xffff0 + 3003c8e: 8f7d and a4,a4,a5 + 3003c90: 149f07b7 lui a5,0x149f0 + 3003c94: 00f70463 beq a4,a5,3003c9c + 3003c98: 4789 li a5,2 + 3003c9a: a039 j 3003ca8 + 3003c9c: fd842583 lw a1,-40(s0) + 3003ca0: fec42503 lw a0,-20(s0) + 3003ca4: 33e5 jal ra,3003a8c + 3003ca6: 4781 li a5,0 + 3003ca8: 853e mv a0,a5 + 3003caa: 50b2 lw ra,44(sp) + 3003cac: 5422 lw s0,40(sp) + 3003cae: 6145 addi sp,sp,48 + 3003cb0: 8082 ret + +03003cb2 : + 3003cb2: 7179 addi sp,sp,-48 + 3003cb4: d606 sw ra,44(sp) + 3003cb6: d422 sw s0,40(sp) + 3003cb8: 1800 addi s0,sp,48 + 3003cba: fca42e23 sw a0,-36(s0) + 3003cbe: fcb42c23 sw a1,-40(s0) + 3003cc2: fdc42503 lw a0,-36(s0) + 3003cc6: 3be5 jal ra,3003abe + 3003cc8: fea42623 sw a0,-20(s0) + 3003ccc: fec42703 lw a4,-20(s0) + 3003cd0: 77c1 lui a5,0xffff0 + 3003cd2: 8f7d and a4,a4,a5 + 3003cd4: 147e07b7 lui a5,0x147e0 + 3003cd8: 02f70c63 beq a4,a5,3003d10 + 3003cdc: fec42703 lw a4,-20(s0) + 3003ce0: 77c1 lui a5,0xffff0 + 3003ce2: 8f7d and a4,a4,a5 + 3003ce4: 147e07b7 lui a5,0x147e0 + 3003ce8: 02f70463 beq a4,a5,3003d10 + 3003cec: fec42703 lw a4,-20(s0) + 3003cf0: 77c1 lui a5,0xffff0 + 3003cf2: 8f7d and a4,a4,a5 + 3003cf4: 147f07b7 lui a5,0x147f0 + 3003cf8: 00f70c63 beq a4,a5,3003d10 + 3003cfc: fec42703 lw a4,-20(s0) + 3003d00: 77c1 lui a5,0xffff0 + 3003d02: 8f7d and a4,a4,a5 + 3003d04: 149f07b7 lui a5,0x149f0 + 3003d08: 00f70463 beq a4,a5,3003d10 + 3003d0c: 4789 li a5,2 + 3003d0e: a039 j 3003d1c + 3003d10: fd842583 lw a1,-40(s0) + 3003d14: fec42503 lw a0,-20(s0) + 3003d18: 3389 jal ra,3003a5a + 3003d1a: 4781 li a5,0 + 3003d1c: 853e mv a0,a5 + 3003d1e: 50b2 lw ra,44(sp) + 3003d20: 5422 lw s0,40(sp) + 3003d22: 6145 addi sp,sp,48 + 3003d24: 8082 ret + +03003d26 : + 3003d26: 7179 addi sp,sp,-48 + 3003d28: d606 sw ra,44(sp) + 3003d2a: d422 sw s0,40(sp) + 3003d2c: 1800 addi s0,sp,48 + 3003d2e: fca42e23 sw a0,-36(s0) + 3003d32: fcb42c23 sw a1,-40(s0) + 3003d36: fdc42503 lw a0,-36(s0) + 3003d3a: 3351 jal ra,3003abe + 3003d3c: fea42623 sw a0,-20(s0) + 3003d40: fec42703 lw a4,-20(s0) + 3003d44: 77c1 lui a5,0xffff0 + 3003d46: 8f7d and a4,a4,a5 + 3003d48: 147e07b7 lui a5,0x147e0 + 3003d4c: 02f70c63 beq a4,a5,3003d84 + 3003d50: fec42703 lw a4,-20(s0) + 3003d54: 77c1 lui a5,0xffff0 + 3003d56: 8f7d and a4,a4,a5 + 3003d58: 147e07b7 lui a5,0x147e0 + 3003d5c: 02f70463 beq a4,a5,3003d84 + 3003d60: fec42703 lw a4,-20(s0) + 3003d64: 77c1 lui a5,0xffff0 + 3003d66: 8f7d and a4,a4,a5 + 3003d68: 147f07b7 lui a5,0x147f0 + 3003d6c: 00f70c63 beq a4,a5,3003d84 + 3003d70: fec42703 lw a4,-20(s0) + 3003d74: 77c1 lui a5,0xffff0 + 3003d76: 8f7d and a4,a4,a5 + 3003d78: 149f07b7 lui a5,0x149f0 + 3003d7c: 00f70463 beq a4,a5,3003d84 + 3003d80: 4789 li a5,2 + 3003d82: a039 j 3003d90 + 3003d84: fd842583 lw a1,-40(s0) + 3003d88: fec42503 lw a0,-20(s0) + 3003d8c: 31b1 jal ra,30039d8 + 3003d8e: 4781 li a5,0 + 3003d90: 853e mv a0,a5 + 3003d92: 50b2 lw ra,44(sp) + 3003d94: 5422 lw s0,40(sp) + 3003d96: 6145 addi sp,sp,48 + 3003d98: 8082 ret + +03003d9a : + 3003d9a: 1101 addi sp,sp,-32 + 3003d9c: ce22 sw s0,28(sp) + 3003d9e: 1000 addi s0,sp,32 + 3003da0: fea42623 sw a0,-20(s0) + 3003da4: fec42783 lw a5,-20(s0) + 3003da8: 439c lw a5,0(a5) + 3003daa: 4705 li a4,1 + 3003dac: c7d8 sw a4,12(a5) + 3003dae: fec42783 lw a5,-20(s0) + 3003db2: 439c lw a5,0(a5) + 3003db4: fec42703 lw a4,-20(s0) + 3003db8: 4b58 lw a4,20(a4) + 3003dba: c398 sw a4,0(a5) + 3003dbc: fec42783 lw a5,-20(s0) + 3003dc0: 439c lw a5,0(a5) + 3003dc2: fec42703 lw a4,-20(s0) + 3003dc6: 4f18 lw a4,24(a4) + 3003dc8: cf98 sw a4,24(a5) + 3003dca: fec42783 lw a5,-20(s0) + 3003dce: 4398 lw a4,0(a5) + 3003dd0: 471c lw a5,8(a4) + 3003dd2: f7f7f793 andi a5,a5,-129 + 3003dd6: c71c sw a5,8(a4) + 3003dd8: fec42783 lw a5,-20(s0) + 3003ddc: 4398 lw a4,0(a5) + 3003dde: fec42783 lw a5,-20(s0) + 3003de2: 2fd4 lbu a3,28(a5) + 3003de4: 471c lw a5,8(a4) + 3003de6: 8a85 andi a3,a3,1 + 3003de8: 0696 slli a3,a3,0x5 + 3003dea: fdf7f793 andi a5,a5,-33 + 3003dee: 8fd5 or a5,a5,a3 + 3003df0: c71c sw a5,8(a4) + 3003df2: fec42783 lw a5,-20(s0) + 3003df6: 47d4 lw a3,12(a5) + 3003df8: fec42783 lw a5,-20(s0) + 3003dfc: 4398 lw a4,0(a5) + 3003dfe: 87b6 mv a5,a3 + 3003e00: 8b8d andi a5,a5,3 + 3003e02: 0ff7f693 andi a3,a5,255 + 3003e06: 471c lw a5,8(a4) + 3003e08: 8a8d andi a3,a3,3 + 3003e0a: 068a slli a3,a3,0x2 + 3003e0c: 9bcd andi a5,a5,-13 + 3003e0e: 8fd5 or a5,a5,a3 + 3003e10: c71c sw a5,8(a4) + 3003e12: fec42783 lw a5,-20(s0) + 3003e16: 4b94 lw a3,16(a5) + 3003e18: fec42783 lw a5,-20(s0) + 3003e1c: 4398 lw a4,0(a5) + 3003e1e: 87b6 mv a5,a3 + 3003e20: 8b85 andi a5,a5,1 + 3003e22: 0ff7f693 andi a3,a5,255 + 3003e26: 471c lw a5,8(a4) + 3003e28: 8a85 andi a3,a3,1 + 3003e2a: 0686 slli a3,a3,0x1 + 3003e2c: 9bf5 andi a5,a5,-3 + 3003e2e: 8fd5 or a5,a5,a3 + 3003e30: c71c sw a5,8(a4) + 3003e32: fec42783 lw a5,-20(s0) + 3003e36: 4798 lw a4,8(a5) + 3003e38: 4789 li a5,2 + 3003e3a: 00f71a63 bne a4,a5,3003e4e + 3003e3e: fec42783 lw a5,-20(s0) + 3003e42: 4398 lw a4,0(a5) + 3003e44: 471c lw a5,8(a4) + 3003e46: 0017e793 ori a5,a5,1 + 3003e4a: c71c sw a5,8(a4) + 3003e4c: a805 j 3003e7c + 3003e4e: fec42783 lw a5,-20(s0) + 3003e52: 4398 lw a4,0(a5) + 3003e54: 471c lw a5,8(a4) + 3003e56: 9bf9 andi a5,a5,-2 + 3003e58: c71c sw a5,8(a4) + 3003e5a: fec42783 lw a5,-20(s0) + 3003e5e: 479c lw a5,8(a5) + 3003e60: fec42703 lw a4,-20(s0) + 3003e64: 4318 lw a4,0(a4) + 3003e66: 00f037b3 snez a5,a5 + 3003e6a: 0ff7f693 andi a3,a5,255 + 3003e6e: 471c lw a5,8(a4) + 3003e70: 8a85 andi a3,a3,1 + 3003e72: 069a slli a3,a3,0x6 + 3003e74: fbf7f793 andi a5,a5,-65 + 3003e78: 8fd5 or a5,a5,a3 + 3003e7a: c71c sw a5,8(a4) + 3003e7c: fec42783 lw a5,-20(s0) + 3003e80: 3fdc lbu a5,29(a5) + 3003e82: e789 bnez a5,3003e8c + 3003e84: fec42783 lw a5,-20(s0) + 3003e88: 2ffc lbu a5,30(a5) + 3003e8a: c399 beqz a5,3003e90 + 3003e8c: 4785 li a5,1 + 3003e8e: a011 j 3003e92 + 3003e90: 4781 li a5,0 + 3003e92: fec42703 lw a4,-20(s0) + 3003e96: 4318 lw a4,0(a4) + 3003e98: 8b85 andi a5,a5,1 + 3003e9a: 0ff7f693 andi a3,a5,255 + 3003e9e: 4f5c lw a5,28(a4) + 3003ea0: 8a85 andi a3,a3,1 + 3003ea2: 0686 slli a3,a3,0x1 + 3003ea4: 9bf5 andi a5,a5,-3 + 3003ea6: 8fd5 or a5,a5,a3 + 3003ea8: cf5c sw a5,28(a4) + 3003eaa: fec42783 lw a5,-20(s0) + 3003eae: 4398 lw a4,0(a5) + 3003eb0: fec42783 lw a5,-20(s0) + 3003eb4: 2ff4 lbu a3,30(a5) + 3003eb6: 4f5c lw a5,28(a4) + 3003eb8: 8a85 andi a3,a3,1 + 3003eba: 9bf9 andi a5,a5,-2 + 3003ebc: 8fd5 or a5,a5,a3 + 3003ebe: cf5c sw a5,28(a4) + 3003ec0: 4781 li a5,0 + 3003ec2: 853e mv a0,a5 + 3003ec4: 4472 lw s0,28(sp) + 3003ec6: 6105 addi sp,sp,32 + 3003ec8: 8082 ret + +03003eca : + 3003eca: 1101 addi sp,sp,-32 + 3003ecc: ce22 sw s0,28(sp) + 3003ece: 1000 addi s0,sp,32 + 3003ed0: fea42623 sw a0,-20(s0) + 3003ed4: fec42783 lw a5,-20(s0) + 3003ed8: 4398 lw a4,0(a5) + 3003eda: 471c lw a5,8(a4) + 3003edc: 0807e793 ori a5,a5,128 + 3003ee0: c71c sw a5,8(a4) + 3003ee2: 0001 nop + 3003ee4: 4472 lw s0,28(sp) + 3003ee6: 6105 addi sp,sp,32 + 3003ee8: 8082 ret + +03003eea : + 3003eea: 1101 addi sp,sp,-32 + 3003eec: ce22 sw s0,28(sp) + 3003eee: 1000 addi s0,sp,32 + 3003ef0: fea42623 sw a0,-20(s0) + 3003ef4: fec42783 lw a5,-20(s0) + 3003ef8: 078e slli a5,a5,0x3 + 3003efa: 853e mv a0,a5 + 3003efc: 4472 lw s0,28(sp) + 3003efe: 6105 addi sp,sp,32 + 3003f00: 8082 ret + +03003f02 : + 3003f02: 1101 addi sp,sp,-32 + 3003f04: ce22 sw s0,28(sp) + 3003f06: 1000 addi s0,sp,32 + 3003f08: fea42623 sw a0,-20(s0) + 3003f0c: fec42783 lw a5,-20(s0) + 3003f10: 078a slli a5,a5,0x2 + 3003f12: 853e mv a0,a5 + 3003f14: 4472 lw s0,28(sp) + 3003f16: 6105 addi sp,sp,32 + 3003f18: 8082 ret + +03003f1a : + 3003f1a: 7179 addi sp,sp,-48 + 3003f1c: d622 sw s0,44(sp) + 3003f1e: 1800 addi s0,sp,48 + 3003f20: fca42e23 sw a0,-36(s0) + 3003f24: fcb42c23 sw a1,-40(s0) + 3003f28: fd842783 lw a5,-40(s0) + 3003f2c: e399 bnez a5,3003f32 + 3003f2e: 4781 li a5,0 + 3003f30: a005 j 3003f50 + 3003f32: fd842783 lw a5,-40(s0) + 3003f36: 0017d713 srli a4,a5,0x1 + 3003f3a: fdc42783 lw a5,-36(s0) + 3003f3e: 973e add a4,a4,a5 + 3003f40: fd842783 lw a5,-40(s0) + 3003f44: 02f757b3 divu a5,a4,a5 + 3003f48: fef42623 sw a5,-20(s0) + 3003f4c: fec42783 lw a5,-20(s0) + 3003f50: 853e mv a0,a5 + 3003f52: 5432 lw s0,44(sp) + 3003f54: 6145 addi sp,sp,48 + 3003f56: 8082 ret + +03003f58 : + 3003f58: 7179 addi sp,sp,-48 + 3003f5a: d606 sw ra,44(sp) + 3003f5c: d422 sw s0,40(sp) + 3003f5e: 1800 addi s0,sp,48 + 3003f60: fca42e23 sw a0,-36(s0) + 3003f64: 0001 nop + 3003f66: fdc42783 lw a5,-36(s0) + 3003f6a: 439c lw a5,0(a5) + 3003f6c: 4f9c lw a5,24(a5) + 3003f6e: 838d srli a5,a5,0x3 + 3003f70: 8b85 andi a5,a5,1 + 3003f72: 0ff7f713 andi a4,a5,255 + 3003f76: 4785 li a5,1 + 3003f78: fef707e3 beq a4,a5,3003f66 + 3003f7c: fdc42783 lw a5,-36(s0) + 3003f80: 4398 lw a4,0(a5) + 3003f82: 5b1c lw a5,48(a4) + 3003f84: 9bf9 andi a5,a5,-2 + 3003f86: db1c sw a5,48(a4) + 3003f88: fdc42783 lw a5,-36(s0) + 3003f8c: 439c lw a5,0(a5) + 3003f8e: 853e mv a0,a5 + 3003f90: c71fd0ef jal ra,3001c00 + 3003f94: fea42423 sw a0,-24(s0) + 3003f98: fdc42783 lw a5,-36(s0) + 3003f9c: 43d8 lw a4,4(a5) + 3003f9e: fe842783 lw a5,-24(s0) + 3003fa2: 8391 srli a5,a5,0x4 + 3003fa4: 00e7ff63 bgeu a5,a4,3003fc2 + 3003fa8: fe842503 lw a0,-24(s0) + 3003fac: 3f3d jal ra,3003eea + 3003fae: 872a mv a4,a0 + 3003fb0: fdc42783 lw a5,-36(s0) + 3003fb4: 43dc lw a5,4(a5) + 3003fb6: 85be mv a1,a5 + 3003fb8: 853a mv a0,a4 + 3003fba: 3785 jal ra,3003f1a + 3003fbc: fea42623 sw a0,-20(s0) + 3003fc0: a829 j 3003fda + 3003fc2: fe842503 lw a0,-24(s0) + 3003fc6: 3f35 jal ra,3003f02 + 3003fc8: 872a mv a4,a0 + 3003fca: fdc42783 lw a5,-36(s0) + 3003fce: 43dc lw a5,4(a5) + 3003fd0: 85be mv a1,a5 + 3003fd2: 853a mv a0,a4 + 3003fd4: 3799 jal ra,3003f1a + 3003fd6: fea42623 sw a0,-20(s0) + 3003fda: fdc42783 lw a5,-36(s0) + 3003fde: 439c lw a5,0(a5) + 3003fe0: 0207a423 sw zero,40(a5) # 149f0028 + 3003fe4: fdc42783 lw a5,-36(s0) + 3003fe8: 439c lw a5,0(a5) + 3003fea: 0207a223 sw zero,36(a5) + 3003fee: fdc42783 lw a5,-36(s0) + 3003ff2: 439c lw a5,0(a5) + 3003ff4: fec42703 lw a4,-20(s0) + 3003ff8: 03f77713 andi a4,a4,63 + 3003ffc: d798 sw a4,40(a5) + 3003ffe: fdc42783 lw a5,-36(s0) + 3004002: 439c lw a5,0(a5) + 3004004: fec42703 lw a4,-20(s0) + 3004008: 8319 srli a4,a4,0x6 + 300400a: d3d8 sw a4,36(a5) + 300400c: fdc42783 lw a5,-36(s0) + 3004010: 4794 lw a3,8(a5) + 3004012: fdc42783 lw a5,-36(s0) + 3004016: 4398 lw a4,0(a5) + 3004018: 87b6 mv a5,a3 + 300401a: 8b8d andi a5,a5,3 + 300401c: 0ff7f693 andi a3,a5,255 + 3004020: 575c lw a5,44(a4) + 3004022: 8a8d andi a3,a3,3 + 3004024: 0696 slli a3,a3,0x5 + 3004026: f9f7f793 andi a5,a5,-97 + 300402a: 8fd5 or a5,a5,a3 + 300402c: d75c sw a5,44(a4) + 300402e: fdc42783 lw a5,-36(s0) + 3004032: 47d4 lw a3,12(a5) + 3004034: fdc42783 lw a5,-36(s0) + 3004038: 4398 lw a4,0(a5) + 300403a: 87b6 mv a5,a3 + 300403c: 8b85 andi a5,a5,1 + 300403e: 0ff7f693 andi a3,a5,255 + 3004042: 575c lw a5,44(a4) + 3004044: 8a85 andi a3,a3,1 + 3004046: 068e slli a3,a3,0x3 + 3004048: 9bdd andi a5,a5,-9 + 300404a: 8fd5 or a5,a5,a3 + 300404c: d75c sw a5,44(a4) + 300404e: fdc42783 lw a5,-36(s0) + 3004052: 4b98 lw a4,16(a5) + 3004054: 4789 li a5,2 + 3004056: 00f71963 bne a4,a5,3004068 + 300405a: fdc42783 lw a5,-36(s0) + 300405e: 4398 lw a4,0(a5) + 3004060: 575c lw a5,44(a4) + 3004062: 9bf5 andi a5,a5,-3 + 3004064: d75c sw a5,44(a4) + 3004066: a805 j 3004096 + 3004068: 4789 li a5,2 + 300406a: fef42223 sw a5,-28(s0) + 300406e: fdc42783 lw a5,-36(s0) + 3004072: 4b9c lw a5,16(a5) + 3004074: 078a slli a5,a5,0x2 + 3004076: fe442703 lw a4,-28(s0) + 300407a: 8fd9 or a5,a5,a4 + 300407c: fef42223 sw a5,-28(s0) + 3004080: fdc42783 lw a5,-36(s0) + 3004084: 439c lw a5,0(a5) + 3004086: 57d4 lw a3,44(a5) + 3004088: fdc42783 lw a5,-36(s0) + 300408c: 439c lw a5,0(a5) + 300408e: fe442703 lw a4,-28(s0) + 3004092: 8f55 or a4,a4,a3 + 3004094: d7d8 sw a4,44(a5) + 3004096: fdc42783 lw a5,-36(s0) + 300409a: 02c7c783 lbu a5,44(a5) + 300409e: cba1 beqz a5,30040ee + 30040a0: fdc42783 lw a5,-36(s0) + 30040a4: 4398 lw a4,0(a5) + 30040a6: 575c lw a5,44(a4) + 30040a8: 0107e793 ori a5,a5,16 + 30040ac: d75c sw a5,44(a4) + 30040ae: fdc42783 lw a5,-36(s0) + 30040b2: 5bd4 lw a3,52(a5) + 30040b4: fdc42783 lw a5,-36(s0) + 30040b8: 4398 lw a4,0(a5) + 30040ba: 87b6 mv a5,a3 + 30040bc: 8b9d andi a5,a5,7 + 30040be: 0ff7f693 andi a3,a5,255 + 30040c2: 5b5c lw a5,52(a4) + 30040c4: 8a9d andi a3,a3,7 + 30040c6: 068e slli a3,a3,0x3 + 30040c8: fc77f793 andi a5,a5,-57 + 30040cc: 8fd5 or a5,a5,a3 + 30040ce: db5c sw a5,52(a4) + 30040d0: fdc42783 lw a5,-36(s0) + 30040d4: 5b94 lw a3,48(a5) + 30040d6: fdc42783 lw a5,-36(s0) + 30040da: 4398 lw a4,0(a5) + 30040dc: 87b6 mv a5,a3 + 30040de: 8b9d andi a5,a5,7 + 30040e0: 0ff7f693 andi a3,a5,255 + 30040e4: 5b5c lw a5,52(a4) + 30040e6: 8a9d andi a3,a3,7 + 30040e8: 9be1 andi a5,a5,-8 + 30040ea: 8fd5 or a5,a5,a3 + 30040ec: db5c sw a5,52(a4) + 30040ee: fdc42783 lw a5,-36(s0) + 30040f2: 5f98 lw a4,56(a5) + 30040f4: 4785 li a5,1 + 30040f6: 00f71c63 bne a4,a5,300410e + 30040fa: fdc42783 lw a5,-36(s0) + 30040fe: 439c lw a5,0(a5) + 3004100: 5b94 lw a3,48(a5) + 3004102: fdc42783 lw a5,-36(s0) + 3004106: 439c lw a5,0(a5) + 3004108: 6731 lui a4,0xc + 300410a: 8f55 or a4,a4,a3 + 300410c: db98 sw a4,48(a5) + 300410e: fdc42783 lw a5,-36(s0) + 3004112: 439c lw a5,0(a5) + 3004114: 5b98 lw a4,48(a5) + 3004116: fdc42783 lw a5,-36(s0) + 300411a: 439c lw a5,0(a5) + 300411c: 30176713 ori a4,a4,769 + 3004120: db98 sw a4,48(a5) + 3004122: fdc42783 lw a5,-36(s0) + 3004126: 4705 li a4,1 + 3004128: c7b8 sw a4,72(a5) + 300412a: fdc42783 lw a5,-36(s0) + 300412e: 4705 li a4,1 + 3004130: c7f8 sw a4,76(a5) + 3004132: 4781 li a5,0 + 3004134: 853e mv a0,a5 + 3004136: 50b2 lw ra,44(sp) + 3004138: 5422 lw s0,40(sp) + 300413a: 6145 addi sp,sp,48 + 300413c: 8082 ret + +0300413e
: + 300413e: 1141 addi sp,sp,-16 + 3004140: c606 sw ra,12(sp) + 3004142: c422 sw s0,8(sp) + 3004144: 0800 addi s0,sp,16 + 3004146: 2c39 jal ra,3004364 + 3004148: a001 j 3004148 + +0300414a : + 300414a: 7139 addi sp,sp,-64 + 300414c: de06 sw ra,60(sp) + 300414e: dc22 sw s0,56(sp) + 3004150: 0080 addi s0,sp,64 + 3004152: fca42623 sw a0,-52(s0) + 3004156: 100007b7 lui a5,0x10000 + 300415a: fcf42823 sw a5,-48(s0) + 300415e: fc042a23 sw zero,-44(s0) + 3004162: 478d li a5,3 + 3004164: fcf42c23 sw a5,-40(s0) + 3004168: 02000793 li a5,32 + 300416c: fcf42e23 sw a5,-36(s0) + 3004170: fe042023 sw zero,-32(s0) + 3004174: 4789 li a5,2 + 3004176: fef42423 sw a5,-24(s0) + 300417a: fd040793 addi a5,s0,-48 + 300417e: 853e mv a0,a5 + 3004180: 855fd0ef jal ra,30019d4 + 3004184: 87aa mv a5,a0 + 3004186: c399 beqz a5,300418c + 3004188: 4785 li a5,1 + 300418a: a039 j 3004198 + 300418c: fe842703 lw a4,-24(s0) + 3004190: fcc42783 lw a5,-52(s0) + 3004194: c398 sw a4,0(a5) + 3004196: 4781 li a5,0 + 3004198: 853e mv a0,a5 + 300419a: 50f2 lw ra,60(sp) + 300419c: 5462 lw s0,56(sp) + 300419e: 6121 addi sp,sp,64 + 30041a0: 8082 ret + +030041a2 : + 30041a2: 1141 addi sp,sp,-16 + 30041a4: c606 sw ra,12(sp) + 30041a6: c422 sw s0,8(sp) + 30041a8: 0800 addi s0,sp,16 + 30041aa: 4585 li a1,1 + 30041ac: 14505537 lui a0,0x14505 + 30041b0: b27fd0ef jal ra,3001cd6 + 30041b4: 27e18793 addi a5,gp,638 # 4000564 + 30041b8: 14505737 lui a4,0x14505 + 30041bc: c398 sw a4,0(a5) + 30041be: 27e18793 addi a5,gp,638 # 4000564 + 30041c2: 04000713 li a4,64 + 30041c6: c3d8 sw a4,4(a5) + 30041c8: 27e18513 addi a0,gp,638 # 4000564 + 30041cc: c90ff0ef jal ra,300365c + 30041d0: 27e18793 addi a5,gp,638 # 4000564 + 30041d4: 43dc lw a5,4(a5) + 30041d6: 4605 li a2,1 + 30041d8: 85be mv a1,a5 + 30041da: 27e18513 addi a0,gp,638 # 4000564 + 30041de: cc4ff0ef jal ra,30036a2 + 30041e2: 27e18793 addi a5,gp,638 # 4000564 + 30041e6: 43dc lw a5,4(a5) + 30041e8: 4601 li a2,0 + 30041ea: 85be mv a1,a5 + 30041ec: 27e18513 addi a0,gp,638 # 4000564 + 30041f0: ce2ff0ef jal ra,30036d2 + 30041f4: 27e18793 addi a5,gp,638 # 4000564 + 30041f8: 43dc lw a5,4(a5) + 30041fa: 4615 li a2,5 + 30041fc: 85be mv a1,a5 + 30041fe: 27e18513 addi a0,gp,638 # 4000564 + 3004202: e6cff0ef jal ra,300386e + 3004206: 0001 nop + 3004208: 40b2 lw ra,12(sp) + 300420a: 4422 lw s0,8(sp) + 300420c: 0141 addi sp,sp,16 + 300420e: 8082 ret + +03004210 : + 3004210: 1141 addi sp,sp,-16 + 3004212: c606 sw ra,12(sp) + 3004214: c422 sw s0,8(sp) + 3004216: 0800 addi s0,sp,16 + 3004218: 4585 li a1,1 + 300421a: 14000537 lui a0,0x14000 + 300421e: ab9fd0ef jal ra,3001cd6 + 3004222: 4581 li a1,0 + 3004224: 14000537 lui a0,0x14000 + 3004228: b2ffd0ef jal ra,3001d56 + 300422c: 21218793 addi a5,gp,530 # 40004f8 + 3004230: 14000737 lui a4,0x14000 + 3004234: c398 sw a4,0(a5) + 3004236: 21218793 addi a5,gp,530 # 40004f8 + 300423a: 6771 lui a4,0x1c + 300423c: 20070713 addi a4,a4,512 # 1c200 + 3004240: c3d8 sw a4,4(a5) + 3004242: 21218793 addi a5,gp,530 # 40004f8 + 3004246: 470d li a4,3 + 3004248: c798 sw a4,8(a5) + 300424a: 21218793 addi a5,gp,530 # 40004f8 + 300424e: 0007a623 sw zero,12(a5) # 1000000c + 3004252: 21218793 addi a5,gp,530 # 40004f8 + 3004256: 4709 li a4,2 + 3004258: cb98 sw a4,16(a5) + 300425a: 21218793 addi a5,gp,530 # 40004f8 + 300425e: 0007aa23 sw zero,20(a5) + 3004262: 21218793 addi a5,gp,530 # 40004f8 + 3004266: 0007ac23 sw zero,24(a5) + 300426a: 21218793 addi a5,gp,530 # 40004f8 + 300426e: 4705 li a4,1 + 3004270: 02e78623 sb a4,44(a5) + 3004274: 21218793 addi a5,gp,530 # 40004f8 + 3004278: 4709 li a4,2 + 300427a: db98 sw a4,48(a5) + 300427c: 21218793 addi a5,gp,530 # 40004f8 + 3004280: 4709 li a4,2 + 3004282: dbd8 sw a4,52(a5) + 3004284: 21218793 addi a5,gp,530 # 40004f8 + 3004288: 0207ac23 sw zero,56(a5) + 300428c: 21218513 addi a0,gp,530 # 40004f8 + 3004290: 31e1 jal ra,3003f58 + 3004292: 0001 nop + 3004294: 40b2 lw ra,12(sp) + 3004296: 4422 lw s0,8(sp) + 3004298: 0141 addi sp,sp,16 + 300429a: 8082 ret + +0300429c : + 300429c: 1141 addi sp,sp,-16 + 300429e: c606 sw ra,12(sp) + 30042a0: c422 sw s0,8(sp) + 30042a2: 0800 addi s0,sp,16 + 30042a4: 21800537 lui a0,0x21800 + 30042a8: 2045 jal ra,3004348 + 30042aa: 4581 li a1,0 + 30042ac: 21800537 lui a0,0x21800 + 30042b0: 3a29 jal ra,3003bca + 30042b2: 4581 li a1,0 + 30042b4: 21800537 lui a0,0x21800 + 30042b8: 3259 jal ra,3003c3e + 30042ba: 4585 li a1,1 + 30042bc: 21800537 lui a0,0x21800 + 30042c0: 3acd jal ra,3003cb2 + 30042c2: 4589 li a1,2 + 30042c4: 21800537 lui a0,0x21800 + 30042c8: 3cb9 jal ra,3003d26 + 30042ca: 010407b7 lui a5,0x1040 + 30042ce: 00478513 addi a0,a5,4 # 1040004 + 30042d2: 289d jal ra,3004348 + 30042d4: 4581 li a1,0 + 30042d6: 010407b7 lui a5,0x1040 + 30042da: 00478513 addi a0,a5,4 # 1040004 + 30042de: 30f5 jal ra,3003bca + 30042e0: 4581 li a1,0 + 30042e2: 010407b7 lui a5,0x1040 + 30042e6: 00478513 addi a0,a5,4 # 1040004 + 30042ea: 3a91 jal ra,3003c3e + 30042ec: 4585 li a1,1 + 30042ee: 010407b7 lui a5,0x1040 + 30042f2: 00478513 addi a0,a5,4 # 1040004 + 30042f6: 3a75 jal ra,3003cb2 + 30042f8: 4589 li a1,2 + 30042fa: 010407b7 lui a5,0x1040 + 30042fe: 00478513 addi a0,a5,4 # 1040004 + 3004302: 3415 jal ra,3003d26 + 3004304: 010807b7 lui a5,0x1080 + 3004308: 00478513 addi a0,a5,4 # 1080004 + 300430c: 2835 jal ra,3004348 + 300430e: 4589 li a1,2 + 3004310: 010807b7 lui a5,0x1080 + 3004314: 00478513 addi a0,a5,4 # 1080004 + 3004318: 384d jal ra,3003bca + 300431a: 4581 li a1,0 + 300431c: 010807b7 lui a5,0x1080 + 3004320: 00478513 addi a0,a5,4 # 1080004 + 3004324: 3a29 jal ra,3003c3e + 3004326: 4585 li a1,1 + 3004328: 010807b7 lui a5,0x1080 + 300432c: 00478513 addi a0,a5,4 # 1080004 + 3004330: 3249 jal ra,3003cb2 + 3004332: 4589 li a1,2 + 3004334: 010807b7 lui a5,0x1080 + 3004338: 00478513 addi a0,a5,4 # 1080004 + 300433c: 32ed jal ra,3003d26 + 300433e: 0001 nop + 3004340: 40b2 lw ra,12(sp) + 3004342: 4422 lw s0,8(sp) + 3004344: 0141 addi sp,sp,16 + 3004346: 8082 ret + +03004348 : + 3004348: 805ff06f j 3003b4c + +0300434c : + 300434c: 1141 addi sp,sp,-16 + 300434e: c606 sw ra,12(sp) + 3004350: c422 sw s0,8(sp) + 3004352: 0800 addi s0,sp,16 + 3004354: 37a1 jal ra,300429c + 3004356: 3d6d jal ra,3004210 + 3004358: 35a9 jal ra,30041a2 + 300435a: 0001 nop + 300435c: 40b2 lw ra,12(sp) + 300435e: 4422 lw s0,8(sp) + 3004360: 0141 addi sp,sp,16 + 3004362: 8082 ret + +03004364 : + 3004364: 1141 addi sp,sp,-16 + 3004366: c606 sw ra,12(sp) + 3004368: c422 sw s0,8(sp) + 300436a: 0800 addi s0,sp,16 + 300436c: 37c5 jal ra,300434c + 300436e: 3e800593 li a1,1000 + 3004372: 1f400513 li a0,500 + 3004376: b50fd0ef jal ra,30016c6 + 300437a: 04000593 li a1,64 + 300437e: 27e18513 addi a0,gp,638 # 4000564 + 3004382: b80ff0ef jal ra,3003702 + 3004386: 030057b7 lui a5,0x3005 + 300438a: 9e878513 addi a0,a5,-1560 # 30049e8 + 300438e: 83aff0ef jal ra,30033c8 + 3004392: bff1 j 300436e + +03004394 <__truncdfsf2>: + 3004394: 00202873 frrm a6 + 3004398: 001006b7 lui a3,0x100 + 300439c: 16fd addi a3,a3,-1 # fffff + 300439e: 8eed and a3,a3,a1 + 30043a0: 0145d893 srli a7,a1,0x14 + 30043a4: 00369793 slli a5,a3,0x3 + 30043a8: 7ff8f893 andi a7,a7,2047 + 30043ac: 01d55693 srli a3,a0,0x1d + 30043b0: 8edd or a3,a3,a5 + 30043b2: 00188793 addi a5,a7,1 + 30043b6: 7ff7f793 andi a5,a5,2047 + 30043ba: 4705 li a4,1 + 30043bc: 81fd srli a1,a1,0x1f + 30043be: 00351613 slli a2,a0,0x3 + 30043c2: 16f75b63 bge a4,a5,3004538 <__truncdfsf2+0x1a4> + 30043c6: c8088713 addi a4,a7,-896 + 30043ca: 0fe00793 li a5,254 + 30043ce: 0ae7d063 bge a5,a4,300446e <__truncdfsf2+0xda> + 30043d2: 04080063 beqz a6,3004412 <__truncdfsf2+0x7e> + 30043d6: 478d li a5,3 + 30043d8: 02f81963 bne a6,a5,300440a <__truncdfsf2+0x76> + 30043dc: c99d beqz a1,3004412 <__truncdfsf2+0x7e> + 30043de: 57fd li a5,-1 + 30043e0: 0fe00713 li a4,254 + 30043e4: 4681 li a3,0 + 30043e6: 4615 li a2,5 + 30043e8: 4509 li a0,2 + 30043ea: 00166613 ori a2,a2,1 + 30043ee: 1aa80063 beq a6,a0,300458e <__truncdfsf2+0x1fa> + 30043f2: 450d li a0,3 + 30043f4: 18a80a63 beq a6,a0,3004588 <__truncdfsf2+0x1f4> + 30043f8: 12081763 bnez a6,3004526 <__truncdfsf2+0x192> + 30043fc: 00f7f513 andi a0,a5,15 + 3004400: 4891 li a7,4 + 3004402: 13150263 beq a0,a7,3004526 <__truncdfsf2+0x192> + 3004406: 0791 addi a5,a5,4 + 3004408: aa39 j 3004526 <__truncdfsf2+0x192> + 300440a: 4789 li a5,2 + 300440c: fcf819e3 bne a6,a5,30043de <__truncdfsf2+0x4a> + 3004410: d5f9 beqz a1,30043de <__truncdfsf2+0x4a> + 3004412: 4781 li a5,0 + 3004414: 0ff00713 li a4,255 + 3004418: 4615 li a2,5 + 300441a: 00579693 slli a3,a5,0x5 + 300441e: 0006db63 bgez a3,3004434 <__truncdfsf2+0xa0> + 3004422: 0705 addi a4,a4,1 + 3004424: 0ff00693 li a3,255 + 3004428: 16d70563 beq a4,a3,3004592 <__truncdfsf2+0x1fe> + 300442c: fc0006b7 lui a3,0xfc000 + 3004430: 16fd addi a3,a3,-1 # fbffffff + 3004432: 8ff5 and a5,a5,a3 + 3004434: 0ff00693 li a3,255 + 3004438: 838d srli a5,a5,0x3 + 300443a: 00d71663 bne a4,a3,3004446 <__truncdfsf2+0xb2> + 300443e: c781 beqz a5,3004446 <__truncdfsf2+0xb2> + 3004440: 004007b7 lui a5,0x400 + 3004444: 4581 li a1,0 + 3004446: 008006b7 lui a3,0x800 + 300444a: 16fd addi a3,a3,-1 # 7fffff + 300444c: 8ff5 and a5,a5,a3 + 300444e: 808006b7 lui a3,0x80800 + 3004452: 0ff77713 andi a4,a4,255 + 3004456: 16fd addi a3,a3,-1 # 807fffff + 3004458: 075e slli a4,a4,0x17 + 300445a: 8ff5 and a5,a5,a3 + 300445c: 05fe slli a1,a1,0x1f + 300445e: 8fd9 or a5,a5,a4 + 3004460: 8fcd or a5,a5,a1 + 3004462: c219 beqz a2,3004468 <__truncdfsf2+0xd4> + 3004464: 00162073 csrs fflags,a2 + 3004468: f0078553 fmv.w.x fa0,a5 + 300446c: 8082 ret + 300446e: 08e04e63 bgtz a4,300450a <__truncdfsf2+0x176> + 3004472: 57a5 li a5,-23 + 3004474: 0ef74d63 blt a4,a5,300456e <__truncdfsf2+0x1da> + 3004478: 008007b7 lui a5,0x800 + 300447c: 4379 li t1,30 + 300447e: 8edd or a3,a3,a5 + 3004480: 40e30333 sub t1,t1,a4 + 3004484: 47fd li a5,31 + 3004486: 0467ce63 blt a5,t1,30044e2 <__truncdfsf2+0x14e> + 300448a: c8288893 addi a7,a7,-894 + 300448e: 011617b3 sll a5,a2,a7 + 3004492: 00f037b3 snez a5,a5 + 3004496: 011696b3 sll a3,a3,a7 + 300449a: 00665333 srl t1,a2,t1 + 300449e: 8edd or a3,a3,a5 + 30044a0: 00d367b3 or a5,t1,a3 + 30044a4: 4701 li a4,0 + 30044a6: cff9 beqz a5,3004584 <__truncdfsf2+0x1f0> + 30044a8: 00179713 slli a4,a5,0x1 + 30044ac: 00777693 andi a3,a4,7 + 30044b0: 4601 li a2,0 + 30044b2: c28d beqz a3,30044d4 <__truncdfsf2+0x140> + 30044b4: 4689 li a3,2 + 30044b6: 0cd80263 beq a6,a3,300457a <__truncdfsf2+0x1e6> + 30044ba: 468d li a3,3 + 30044bc: 0ad80b63 beq a6,a3,3004572 <__truncdfsf2+0x1de> + 30044c0: 4605 li a2,1 + 30044c2: 00081963 bnez a6,30044d4 <__truncdfsf2+0x140> + 30044c6: 00f77693 andi a3,a4,15 + 30044ca: 4511 li a0,4 + 30044cc: 4605 li a2,1 + 30044ce: 00a68363 beq a3,a0,30044d4 <__truncdfsf2+0x140> + 30044d2: 0711 addi a4,a4,4 + 30044d4: 01b75693 srli a3,a4,0x1b + 30044d8: 0016c693 xori a3,a3,1 + 30044dc: 8a85 andi a3,a3,1 + 30044de: 4701 li a4,0 + 30044e0: a83d j 300451e <__truncdfsf2+0x18a> + 30044e2: 57f9 li a5,-2 + 30044e4: 40e78733 sub a4,a5,a4 + 30044e8: 02000793 li a5,32 + 30044ec: 00e6d733 srl a4,a3,a4 + 30044f0: 4501 li a0,0 + 30044f2: 00f30663 beq t1,a5,30044fe <__truncdfsf2+0x16a> + 30044f6: ca288893 addi a7,a7,-862 + 30044fa: 01169533 sll a0,a3,a7 + 30044fe: 00c567b3 or a5,a0,a2 + 3004502: 00f037b3 snez a5,a5 + 3004506: 8fd9 or a5,a5,a4 + 3004508: bf71 j 30044a4 <__truncdfsf2+0x110> + 300450a: 051a slli a0,a0,0x6 + 300450c: 00a037b3 snez a5,a0 + 3004510: 068e slli a3,a3,0x3 + 3004512: 8275 srli a2,a2,0x1d + 3004514: 8edd or a3,a3,a5 + 3004516: 00c6e7b3 or a5,a3,a2 + 300451a: 4681 li a3,0 + 300451c: 4601 li a2,0 + 300451e: 0077f513 andi a0,a5,7 + 3004522: ec0513e3 bnez a0,30043e8 <__truncdfsf2+0x54> + 3004526: ee068ae3 beqz a3,300441a <__truncdfsf2+0x86> + 300452a: 00167693 andi a3,a2,1 + 300452e: ee0686e3 beqz a3,300441a <__truncdfsf2+0x86> + 3004532: 00266613 ori a2,a2,2 + 3004536: b5d5 j 300441a <__truncdfsf2+0x86> + 3004538: 00c6e7b3 or a5,a3,a2 + 300453c: 00089563 bnez a7,3004546 <__truncdfsf2+0x1b2> + 3004540: 00f037b3 snez a5,a5 + 3004544: b785 j 30044a4 <__truncdfsf2+0x110> + 3004546: cf8d beqz a5,3004580 <__truncdfsf2+0x1ec> + 3004548: 7ff00793 li a5,2047 + 300454c: 4601 li a2,0 + 300454e: 00f89863 bne a7,a5,300455e <__truncdfsf2+0x1ca> + 3004552: 00400637 lui a2,0x400 + 3004556: 8e75 and a2,a2,a3 + 3004558: 00163613 seqz a2,a2 + 300455c: 0612 slli a2,a2,0x4 + 300455e: 068e slli a3,a3,0x3 + 3004560: 020007b7 lui a5,0x2000 + 3004564: 8fd5 or a5,a5,a3 + 3004566: 0ff00713 li a4,255 + 300456a: 4681 li a3,0 + 300456c: bf4d j 300451e <__truncdfsf2+0x18a> + 300456e: 4785 li a5,1 + 3004570: bf25 j 30044a8 <__truncdfsf2+0x114> + 3004572: 4605 li a2,1 + 3004574: f1a5 bnez a1,30044d4 <__truncdfsf2+0x140> + 3004576: 0721 addi a4,a4,8 + 3004578: bfb1 j 30044d4 <__truncdfsf2+0x140> + 300457a: 4605 li a2,1 + 300457c: dda1 beqz a1,30044d4 <__truncdfsf2+0x140> + 300457e: bfe5 j 3004576 <__truncdfsf2+0x1e2> + 3004580: 0ff00713 li a4,255 + 3004584: 4601 li a2,0 + 3004586: bd51 j 300441a <__truncdfsf2+0x86> + 3004588: fdd9 bnez a1,3004526 <__truncdfsf2+0x192> + 300458a: 07a1 addi a5,a5,8 # 2000008 + 300458c: bf69 j 3004526 <__truncdfsf2+0x192> + 300458e: ddc1 beqz a1,3004526 <__truncdfsf2+0x192> + 3004590: bfed j 300458a <__truncdfsf2+0x1f6> + 3004592: 4781 li a5,0 + 3004594: 00080e63 beqz a6,30045b0 <__truncdfsf2+0x21c> + 3004598: 468d li a3,3 + 300459a: 00d81763 bne a6,a3,30045a8 <__truncdfsf2+0x214> + 300459e: c989 beqz a1,30045b0 <__truncdfsf2+0x21c> + 30045a0: 57fd li a5,-1 + 30045a2: 0fe00713 li a4,254 + 30045a6: a029 j 30045b0 <__truncdfsf2+0x21c> + 30045a8: 4689 li a3,2 + 30045aa: fed81be3 bne a6,a3,30045a0 <__truncdfsf2+0x20c> + 30045ae: d9ed beqz a1,30045a0 <__truncdfsf2+0x20c> + 30045b0: 00566613 ori a2,a2,5 + 30045b4: b541 j 3004434 <__truncdfsf2+0xa0> + ... + +030045b8 <__rodata_start>: + 30045b8: 0000 unimp + 30045ba: 4580 lw s0,8(a1) + 30045bc: 0000 unimp + 30045be: 4000 lw s0,0(s0) + 30045c0: 0000 unimp + 30045c2: 4500 lw s0,8(a0) + 30045c4: 6666 3b4b 295f .byte 0x5f, 0x29, 0x4b, 0x3b, 0x66, 0x66 + 30045ca: 3f26 lhu s1,58(a4) + +030045cc : + 30045cc: 0000 1400 0000 0000 0030 0000 1000 1400 ........0....... + 30045dc: 0000 0000 0034 0000 2000 1400 0000 0000 ....4.... ...... + 30045ec: 0038 0000 0000 1430 0000 0000 003c 0000 8.....0.....<... + 30045fc: 0020 1430 0000 0000 003c 0000 1000 1430 .0.....<.....0. + 300460c: 0000 0000 0040 0000 1020 1430 0000 0000 ....@... .0..... + 300461c: 0040 0000 0000 1470 0000 0000 0044 0000 @.....p.....D... + 300462c: 1000 1470 0000 0000 0048 0000 0000 1440 ..p.....H.....@. + 300463c: 0000 0000 004c 0000 0000 1420 0000 0000 ....L..... ..... + 300464c: 0050 0000 0000 1460 0002 0000 0054 0000 P.....`.....T... + 300465c: 0000 14b0 0001 0000 0058 0000 1000 14b0 ........X....... + 300466c: 0001 0000 0058 0001 2000 14b0 0001 0000 ....X.... ...... + 300467c: 0058 0002 0000 1c00 0001 0000 005c 0000 X...........\... + 300468c: 0000 1450 0000 0000 0064 0000 1000 1450 ..P.....d.....P. + 300469c: 0000 0000 0064 0001 2000 1450 0000 0000 ....d.... P..... + 30046ac: 0064 0002 3000 1450 0000 0000 0064 0003 d....0P.....d... + 30046bc: 4000 1450 0000 0000 0064 0004 5000 1450 .@P.....d....PP. + 30046cc: 0000 0000 0064 0005 6000 1450 0000 0000 ....d....`P..... + 30046dc: 0064 0006 7000 1450 0000 0000 0064 0007 d....pP.....d... + 30046ec: 0000 1410 0000 0000 0068 0000 1000 1440 ........h.....@. + 30046fc: 0006 0000 006c 0000 0000 14c0 0001 0000 ....l........... + 300470c: 0070 0000 0000 147d 0001 0000 0074 0000 p.....}.....t... + 300471c: 0000 1480 0001 0000 007c 0000 0000 14a0 ........|....... + 300472c: 0001 0000 0080 0000 1000 14a0 0001 0000 ................ + 300473c: 0080 0001 2000 14a0 0001 0000 0080 0002 ..... .......... + 300474c: 3000 14a0 0001 0000 0080 0003 4000 14a0 .0...........@.. + 300475c: 0001 0000 0080 0004 5000 14a0 0001 0000 .........P...... + 300476c: 0080 0005 6000 14a0 0001 0000 0080 0006 .....`.......... + 300477c: 7000 14a0 0001 0000 0080 0007 8000 14a0 .p.............. + 300478c: 0001 0000 0080 0008 0008 1830 0001 0000 ..........0..... + 300479c: 0090 0000 1008 1830 0001 0000 0090 0001 ......0......... + 30047ac: 2008 1830 0001 0000 0090 0002 0000 1820 . 0........... . + 30047bc: 0001 0000 0098 0000 1000 1820 0001 0000 .......... ..... + 30047cc: 0098 0001 2000 1820 0001 0000 0098 0002 ..... ......... + 30047dc: 0000 1800 0003 0000 0084 0000 1000 1800 ................ + 30047ec: 0003 0000 0088 0000 2000 1800 0003 0000 ......... ...... + 30047fc: 008c 0000 0000 1830 0004 0000 0094 0000 ......0......... + 300480c: 1000 1830 0004 0000 0094 0001 2000 1830 ..0.......... 0. + 300481c: 0004 0000 0094 0002 0000 1471 0005 0000 ..........q..... + 300482c: 0060 0000 2e2e 642f 6972 6576 7372 622f `...../drivers/b + 300483c: 7361 2f65 7273 2f63 6e69 6574 7272 7075 ase/src/interrup + 300484c: 2e74 0063 t.c. + +03004850 : + 3004850: 0000 0000 21e4 0300 2150 0300 226a 0300 .....!..P!..j".. + 3004860: 0000 0000 2232 0300 21ae 0300 22b6 0300 ....2"...!...".. + 3004870: 0000 0000 0001 0000 2456 0300 22ee 0300 ........V$...".. + ... + 3004888: 2528 0300 2406 0300 0000 0000 0000 0000 (%...$.......... + 3004898: 0002 0000 2456 0300 22ee 0300 0000 0000 ....V$..."...... + 30048a8: 0000 0000 2528 0300 2406 0300 0000 0000 ....(%...$...... + 30048b8: 0000 0000 0003 0000 277c 0300 257a 0300 ........|'..z%.. + 30048c8: 2672 0300 26f8 0300 281c 0300 261e 0300 r&...&...(...&.. + 30048d8: 26c0 0300 2744 0300 0004 0000 2b44 0300 .&..D'......D+.. + 30048e8: 288c 0300 0000 0000 29f6 0300 2c20 0300 .(.......).. ,.. + 30048f8: 29a0 0300 0000 0000 2ae8 0300 0005 0000 .).......*...... + 3004908: 0000 0000 2c66 0300 0000 0000 0000 0000 ....f,.......... + 3004918: 0000 0000 2cae 0300 0000 0000 0000 0000 .....,.......... + 3004928: 0006 0000 2456 0300 22ee 0300 0000 0000 ....V$..."...... + 3004938: 0000 0000 2528 0300 2406 0300 0000 0000 ....(%...$...... + 3004948: 0000 0000 1c50 0300 1c64 0300 1c6e 0300 ....P...d...n... + 3004958: 1ca4 0300 1c82 0300 1c64 0300 31b8 0300 ........d....1.. + 3004968: 3222 0300 3222 0300 3222 0300 3222 0300 "2.."2.."2.."2.. + 3004978: 3222 0300 3222 0300 3222 0300 3222 0300 "2.."2.."2.."2.. + 3004988: 3222 0300 3222 0300 30f8 0300 314e 0300 "2.."2...0..N1.. + 3004998: 3222 0300 31e2 0300 3222 0300 3222 0300 "2...1.."2.."2.. + 30049a8: 3222 0300 3222 0300 3222 0300 3222 0300 "2.."2.."2.."2.. + 30049b8: 3222 0300 3222 0300 3222 0300 31b8 0300 "2.."2.."2...1.. + 30049c8: 3222 0300 3222 0300 3122 0300 3222 0300 "2.."2.."1.."2.. + 30049d8: 3178 0300 3222 0300 3222 0300 31b8 0300 x1.."2.."2...1.. + 30049e8: 454c 2044 7453 7461 2061 6572 6576 7372 LED Stata revers + 30049f8: 2165 0d20 000a 0000 e! ..... diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/analyzerJson/cfg/funcptr.txt b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/analyzerJson/cfg/funcptr.txt new file mode 100644 index 00000000..33e6a951 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/analyzerJson/cfg/funcptr.txt @@ -0,0 +1,27 @@ + +Miss_funcptr: InterruptEntry ... +Remarks_here: 0x3001738 InterruptEntry + +Miss_funcptr: HAL_CRG_GetIpFreq ... +Remarks_here: 0x3001c00 HAL_CRG_GetIpFreq + +Miss_funcptr: CRG_GetLsIpFreq ... +Remarks_here: 0x3001e6c CRG_GetLsIpFreq + +Miss_funcptr: CRG_GetDacIpFreq ... +Remarks_here: 0x3001f82 CRG_GetDacIpFreq + +Miss_funcptr: CRG_GetAdcIpFreq ... +Remarks_here: 0x3001ede CRG_GetAdcIpFreq + +Miss_funcptr: CRG_GetAdcIpFreq ... +Remarks_here: 0x3001ede CRG_GetAdcIpFreq + +Miss_funcptr: HAL_CRG_IpEnableSet ... +Remarks_here: 0x3001cd6 HAL_CRG_IpEnableSet + +Miss_funcptr: HAL_CRG_IpClkSelectSet ... +Remarks_here: 0x3001d56 HAL_CRG_IpClkSelectSet + +Miss_funcptr: ParseSpecifier ... +Remarks_here: 0x30030a8 ParseSpecifier diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/analyzerJson/funcstack.json b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/analyzerJson/funcstack.json new file mode 100644 index 00000000..b59efb36 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/analyzerJson/funcstack.json @@ -0,0 +1,3115 @@ +{ + "stackData": { + "0x3000004": { + "funcname": "_start", + "funcaddr": "0x3000004", + "LocalCost": 0, + "MaxCost": 0, + "called": [ + "0x3000510" + ], + "Location": "", + "IsCalled": 0, + "IsRec": 0, + "depth": 1, + "ptrVarName": [] + }, + "0x3000008": { + "funcname": "TrapHandler", + "funcaddr": "0x3000008", + "LocalCost": 0, + "MaxCost": 640, + "called": [ + "0x3000480", + "0x30002d4" + ], + "Location": "startup.S:221", + "IsCalled": 0, + "IsRec": 0, + "depth": 1, + "ptrVarName": [] + }, + "0x30001f0": { + "funcname": "NmiEntry", + "funcaddr": "0x30001f0", + "LocalCost": 112, + "MaxCost": 352, + "called": [ + "0x3001802" + ], + "Location": "startup.S:347", + "IsCalled": 0, + "IsRec": 0, + "depth": 2, + "ptrVarName": [] + }, + "0x300025c": { + "funcname": "deadLoop1", + "funcaddr": "0x300025c", + "LocalCost": 0, + "MaxCost": 0, + "called": [ + "0x300025c" + ], + "Location": "", + "IsCalled": 1, + "IsRec": 1, + "depth": 0, + "ptrVarName": [] + }, + "0x3000262": { + "funcname": "TrapEntry", + "funcaddr": "0x3000262", + "LocalCost": 112, + "MaxCost": 352, + "called": [ + "0x30017e4" + ], + "Location": "startup.S:355", + "IsCalled": 0, + "IsRec": 0, + "depth": 2, + "ptrVarName": [] + }, + "0x30002d2": { + "funcname": "deadLoop2", + "funcaddr": "0x30002d2", + "LocalCost": 0, + "MaxCost": 0, + "called": [ + "0x30002d2" + ], + "Location": "", + "IsCalled": 1, + "IsRec": 1, + "depth": 0, + "ptrVarName": [] + }, + "0x30002d4": { + "funcname": "IntHandler", + "funcaddr": "0x30002d4", + "LocalCost": 160, + "MaxCost": 320, + "called": [], + "Location": "", + "IsCalled": 1, + "IsRec": 0, + "depth": 0, + "ptrVarName": [] + }, + "0x3000320": { + "funcname": "custom_nested_irq_main_handler_entry", + "funcaddr": "0x3000320", + "LocalCost": 0, + "MaxCost": 128, + "called": [ + "0x3001738" + ], + "Location": "startup.S:397", + "IsCalled": 0, + "IsRec": 0, + "depth": 2, + "ptrVarName": [] + }, + "0x30003b8": { + "funcname": "BacktoIrq", + "funcaddr": "0x30003b8", + "LocalCost": 0, + "MaxCost": 0, + "called": [], + "Location": "", + "IsCalled": 0, + "IsRec": 0, + "depth": 0, + "ptrVarName": [] + }, + "0x3000444": { + "funcname": "quit_int", + "funcaddr": "0x3000444", + "LocalCost": 0, + "MaxCost": 0, + "called": [], + "Location": "", + "IsCalled": 0, + "IsRec": 0, + "depth": 0, + "ptrVarName": [] + }, + "0x300045c": { + "funcname": "restore_mstatus", + "funcaddr": "0x300045c", + "LocalCost": 0, + "MaxCost": 0, + "called": [], + "Location": "", + "IsCalled": 0, + "IsRec": 0, + "depth": 0, + "ptrVarName": [] + }, + "0x3000480": { + "funcname": "TrapVector", + "funcaddr": "0x3000480", + "LocalCost": 320, + "MaxCost": 640, + "called": [], + "Location": "", + "IsCalled": 1, + "IsRec": 0, + "depth": 0, + "ptrVarName": [] + }, + "0x30004cc": { + "funcname": "switch_to_mmode", + "funcaddr": "0x30004cc", + "LocalCost": 0, + "MaxCost": 0, + "called": [], + "Location": "", + "IsCalled": 0, + "IsRec": 0, + "depth": 0, + "ptrVarName": [] + }, + "0x30004f4": { + "funcname": "mem_cpy", + "funcaddr": "0x30004f4", + "LocalCost": 0, + "MaxCost": 0, + "called": [ + "0x30004f4" + ], + "Location": "", + "IsCalled": 1, + "IsRec": 1, + "depth": 3, + "ptrVarName": [] + }, + "0x300050c": { + "funcname": "cpy_done", + "funcaddr": "0x300050c", + "LocalCost": 0, + "MaxCost": 0, + "called": [], + "Location": "", + "IsCalled": 0, + "IsRec": 0, + "depth": 0, + "ptrVarName": [] + }, + "0x3000510": { + "funcname": "handle_reset", + "funcaddr": "0x3000510", + "LocalCost": 0, + "MaxCost": 0, + "called": [], + "Location": "", + "IsCalled": 1, + "IsRec": 0, + "depth": 0, + "ptrVarName": [] + }, + "0x3000530": { + "funcname": "flash_init", + "funcaddr": "0x3000530", + "LocalCost": 0, + "MaxCost": 0, + "called": [], + "Location": "", + "IsCalled": 0, + "IsRec": 0, + "depth": 0, + "ptrVarName": [] + }, + "0x30005a0": { + "funcname": "clear_sram", + "funcaddr": "0x30005a0", + "LocalCost": 0, + "MaxCost": 0, + "called": [], + "Location": "", + "IsCalled": 0, + "IsRec": 0, + "depth": 0, + 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b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/board.bak @@ -0,0 +1 @@ +{"all":{"CLOCKSettings":{"HOSC":"25","LOSC":"32","adc0_cksel":"adc0_cksel_value","adc0_cksel_value":"40","adc0_div":"/5","adc1_cksel":"adc1_cksel_value","adc1_cksel_value":"40","adc1_div":"/5","adc2_cksel":"adc2_cksel_value","adc2_cksel_value":"40","adc2_div":"/5","clk_adc0":"40","clk_adc1":"40","clk_adc2":"40","clk_cs":"/2","clk_dac0_in":"5","clk_dac1_in":"5","clk_dac2_in":"5","dac0_div":"/5","dac1_div":"/5","dac2_div":"/5","clk_gpt0_in":"100","clk_gpt1_in":"100","clk_hs":"200","clk_iwdog":"32","clk_ls":"100","clk_pll":"200","clk_pll_adc":"200","clk_spi_in":"100","clk_tcxo":"30","clk_timer01_in":"100","clk_timer23_in":"100","clk_uart0_in":"100","clk_uart1_in":"100","clk_uart2_in":"100","clk_wdog_in":"100","core_cksel":"clk_pll","gpt0_cksel":"/1","gpt1_cksel":"/1","pll_div":"X32","pll_postdiv":"/1","pll_prediv":"/4","pll_ref_cksel":"HOSC","spi_cksel":"/1","timer01_cksel":"/1","timer23_cksel":"/1","uart0_cksel":"/1","uart1_cksel":"/1","uart2_cksel":"/1","wdog_cksel":"/1"},"SAMPLE Settings":{"Gpio Led":{"Name":"Gpio Led","Type":"Driver","SampleDir":"application/drivers_sample/gpio/sample_gpio_led","SampleDirName":"sample_gpio_led","SampleFunction":"GPIO_LedSample()","SampleHead":"#include \"gpio_led_sample.h\"","Enable":"enable","key":25},"Blank Main":{"Name":"Blank Main","Type":"Default","Extend Board":"Default","Extend Module":"Default","SampleDir":"","SampleDirName":"blank_main","SampleFunction":"SystemInit()","Enable":"disable","key":0},"Motorcontrolsystem":{"Name":"Motorcontrolsystem","Type":"Motor","SampleDir":"application/middleware_sample/mcs_65demo","SampleDirName":"mcs_65demo","SampleFunction":"MotorMain()","SampleHead":"#include \"mcs_motor_process.h\"","Enable":"disable","key":1},"Pmsm Sensorless 1shunt Foc":{"Name":"Pmsm Sensorless 1shunt Foc","Type":"Motor","Extend Board":"ECBMOTORA","Extend Module":"Motor : GBM2804H-100T","SampleDir":"application/middleware_sample/pmsm_sensorless_1shunt_foc","SampleDirName":"pmsm_sensorless_1shunt_foc","SampleFunction":"MotorMainProcess()","SampleHead":"#include \"mcs_motor_process.h\"","Enable":"disable","key":2},"Pmsm Sensorless 2shunt Foc":{"Name":"Pmsm Sensorless 2shunt Foc","Type":"Motor","Extend Board":"ECBMOTORA","Extend Module":"Motor : GBM2804H-100T","SampleDir":"application/middleware_sample/pmsm_sensorless_2shunt_foc","SampleDirName":"pmsm_sensorless_2shunt_foc","SampleFunction":"MotorMainProcess()","SampleHead":"#include \"mcs_motor_process.h\"","Enable":"disable","key":3},"Pmsm Encode Qdm 2shunt Foc":{"Name":"Pmsm Encode Qdm 2shunt Foc","Type":"Motor","Extend Board":"ECBMOTORA","Extend Module":"Motor : JMK-42JSF630AS-1000","SampleDir":"application/middleware_sample/pmsm_encode_qdm_2shunt_foc","SampleDirName":"pmsm_encode_qdm_2shunt_foc","SampleFunction":"MotorMainProcess()","SampleHead":"#include \"mcs_motor_process.h\"","Enable":"disable","key":4},"Adc Associativetrigger Of Apt":{"Name":"Adc Associativetrigger Of Apt","Type":"Driver","SampleDir":"application/drivers_sample/adc/sample_adc_associative_trigger_of_apt","SampleDirName":"sample_adc_associative_trigger_of_apt","SampleFunction":"ADC_AptTrigger()","SampleHead":"#include \"sample_adc_associative_trigger_apt.h\"","Enable":"disable","key":5},"Adc Continuetrigger":{"Name":"Adc Continuetrigger","Type":"Driver","SampleDir":"application/drivers_sample/adc/sample_adc_continue_trigger","SampleDirName":"sample_adc_continue_trigger","SampleFunction":"ADC_ContinueSample()","SampleHead":"#include \"sample_adc_continue_trigger.h\"","Enable":"disable","key":6},"Adc Oversample":{"Name":"Adc Oversample","Type":"Driver","SampleDir":"application/drivers_sample/adc/sample_adc_over_sample","SampleDirName":"sample_adc_over_sample","SampleFunction":"ADC_OverSample()","SampleHead":"#include \"sample_adc_over_sample.h\"","Enable":"disable","key":7},"Adc Singletrigger":{"Name":"Adc Singletrigger","Type":"Driver","SampleDir":"application/drivers_sample/adc/sample_adc_single_trigger","SampleDirName":"sample_adc_single_trigger","SampleFunction":"ADC_SingleTrigger()","SampleHead":"#include \"sample_adc_single_trigger.h\"","Enable":"disable","key":8},"Adc Singletrigger Dma":{"Name":"Adc Singletrigger Dma","Type":"Driver","SampleDir":"application/drivers_sample/adc/sample_adc_single_trigger_dma","SampleDirName":"sample_adc_single_trigger_dma","SampleFunction":"ADC_SingleTriggerDma()","SampleHead":"#include \"sample_adc_single_trigger_dma.h\"","Enable":"disable","key":9},"Adc Singletrigger It":{"Name":"Adc Singletrigger It","Type":"Driver","SampleDir":"application/drivers_sample/adc/sample_adc_single_trigger_it","SampleDirName":"sample_adc_single_trigger_it","SampleFunction":"ADC_SingleTriggerIT()","SampleHead":"#include \"sample_adc_single_trigger_it.h\"","Enable":"disable","key":10},"Adc Sync Dma":{"Name":"Adc Sync Dma","Type":"Driver","SampleDir":"application/drivers_sample/adc/sample_adc_sync_sample_dma","SampleDirName":"sample_adc_sync_sample_dma","SampleFunction":"ADC_SyncSampleWithDma()","SampleHead":"#include \"sample_adc_sync_sample_dma.h\"","Enable":"disable","key":11},"Adc Sync It":{"Name":"Adc Sync It","Type":"Driver","SampleDir":"application/drivers_sample/adc/sample_adc_sync_sample_it","SampleDirName":"sample_adc_sync_sample_it","SampleFunction":"ADC_SyncSampleWithIt()","SampleHead":"#include \"sample_adc_sync_sample_it.h\"","Enable":"disable","key":12},"Adc Syncsample":{"Name":"Adc Syncsample","Type":"Driver","SampleDir":"application/drivers_sample/adc/sample_adc_sync_sample","SampleDirName":"sample_adc_sync_sample","SampleFunction":"ADC_SyncSample()","SampleHead":"#include \"sample_adc_sync_sample.h\"","Enable":"disable","key":13},"Cfd Check Error":{"Name":"Cfd Check Error","Type":"Driver","SampleDir":"application/drivers_sample/cfd/sample_cfd_check_error","SampleDirName":"sample_cfd_check_error","SampleFunction":"CFD_SampleMain()","SampleHead":"#include \"cfd_check_error_sample.h\"","Enable":"disable","key":14},"Cmm Check Error":{"Name":"Cmm Check Error","Type":"Driver","SampleDir":"application/drivers_sample/cmm/sample_cmm_check_error","SampleDirName":"sample_cmm_check_error","SampleFunction":"CMM_SampleMain()","SampleHead":"#include \"cmm_check_error_sample.h\"","Enable":"disable","key":15},"Crc Check":{"Name":"Crc Check","Type":"Driver","SampleDir":"application/drivers_sample/crc/sample_crc_check","SampleDirName":"sample_crc_check","SampleFunction":"CRC_CheckSample()","SampleHead":"#include \"crc_check_sample.h\"","Enable":"disable","key":16},"Crc Gen":{"Name":"Crc Gen","Type":"Driver","SampleDir":"application/drivers_sample/crc/sample_crc_gen","SampleDirName":"sample_crc_gen","SampleFunction":"CRC_GenerateSample()","SampleHead":"#include \"crc_gen_sample.h\"","Enable":"disable","key":17},"Crc Load":{"Name":"Crc Load","Type":"Driver","SampleDir":"application/drivers_sample/crc/sample_crc_load","SampleDirName":"sample_crc_load","SampleFunction":"CRC_LoadSample()","SampleHead":"#include \"crc_load_sample.h\"","Enable":"disable","key":18},"Dma Memtomem":{"Name":"Dma Memtomem","Type":"Driver","SampleDir":"application/drivers_sample/dma/sample_dma_mem_to_mem","SampleDirName":"sample_dma_mem_to_mem","SampleFunction":"DMA_MemoryToMemory()","SampleHead":"#include \"sample_dma_mem_to_mem.h\"","Enable":"disable","key":19},"Flash Blocking":{"Name":"Flash Blocking","Type":"Driver","SampleDir":"application/drivers_sample/flash/sample_flash_blocking","SampleDirName":"sample_flash_blocking","SampleFunction":"FlashBlockingProcessing()","SampleHead":"#include \"sample_flash_blocking.h\"","Enable":"disable","key":20},"Flash Interrupt":{"Name":"Flash Interrupt","Type":"Driver","SampleDir":"application/drivers_sample/flash/sample_flash_interrupt","SampleDirName":"sample_flash_interrupt","SampleFunction":"FlashInterruptProcessing()","SampleHead":"#include \"sample_flash_interrupt.h\"","Enable":"disable","key":21},"Gpio Circle":{"Name":"Gpio Circle","Type":"Driver","SampleDir":"application/drivers_sample/gpio/sample_gpio_circle","SampleDirName":"sample_gpio_circle","SampleFunction":"GPIO_CircleSample()","SampleHead":"#include \"gpio_circle_sample.h\"","Enable":"disable","key":22},"Gpio Interrupt":{"Name":"Gpio Interrupt","Type":"Driver","SampleDir":"application/drivers_sample/gpio/sample_gpio_interrupt","SampleDirName":"sample_gpio_interrupt","SampleFunction":"GPIO_InterruptSample()","SampleHead":"#include \"gpio_interrupt_sample.h\"","Enable":"disable","key":23},"Gpio Key":{"Name":"Gpio Key","Type":"Driver","SampleDir":"application/drivers_sample/gpio/sample_gpio_key","SampleDirName":"sample_gpio_key","SampleFunction":"GPIO_KeySample()","SampleHead":"#include \"gpio_key_sample.h\"","Enable":"disable","key":24},"Gpt Simplerun":{"Name":"Gpt Simplerun","Type":"Driver","SampleDir":"application/drivers_sample/gpt/sample_gpt_simplerun","SampleDirName":"sample_gpt_simplerun","SampleFunction":"GPT_SampleMain()","SampleHead":"#include \"sample_gpt_simplerun.h\"","Enable":"disable","key":26},"Spi Microwire Master":{"Name":"Spi Microwire Master","Type":"Driver","SampleDir":"application/drivers_sample/spi/sample_spi_microwire_master","SampleDirName":"sample_spi_microwire_master","SampleFunction":"MicroWireMasterTestSampleProcessing()","SampleHead":"#include \"sample_spi_microwire_master.h\"","Enable":"disable","key":27},"Spi Microwire Slave":{"Name":"Spi Microwire Slave","Type":"Driver","SampleDir":"application/drivers_sample/spi/sample_spi_microwire_slave","SampleDirName":"sample_spi_microwire_slave","SampleFunction":"MicroWireSlaveTestSampleProcessing()","SampleHead":"#include \"sample_spi_microwire_slave.h\"","Enable":"disable","key":28},"Spi Slave":{"Name":"Spi Slave","Type":"Driver","SampleDir":"application/drivers_sample/spi/sample_spi_slave","SampleDirName":"sample_spi_slave","SampleFunction":"SlaveTestSampleProcessing()","SampleHead":"#include \"sample_spi_slave.h\"","Enable":"disable","key":29},"Spi Master":{"Name":"Spi Master","Type":"Driver","SampleDir":"application/drivers_sample/spi/sample_spi_master","SampleDirName":"sample_spi_master","SampleFunction":"MasterTestSampleProcessing()","SampleHead":"#include \"sample_spi_master.h\"","Enable":"disable","key":30},"Spi Blocking W25Q32 Internal":{"Name":"Spi Blocking W25Q32 Internal","Type":"Driver","SampleDir":"application/drivers_sample/spi/sample_spi_blocking_w25q32_internal","SampleDirName":"sample_spi_blocking_w25q32_internal","SampleFunction":"W25Q32BlockingSampleProcessing()","SampleHead":"#include \"sample_spi_blocking_w25q32_internal.h\"","Enable":"disable","key":31},"Spi Dma W25Q32 Internal":{"Name":"Spi Dma W25Q32 Internal","Type":"Driver","SampleDir":"application/drivers_sample/spi/sample_spi_dma_w25q32_internal","SampleDirName":"sample_spi_dma_w25q32_internal","SampleFunction":"W25Q32DmaSampleProcessing()","SampleHead":"#include \"sample_spi_dma_w25q32_internal.h\"","Enable":"disable","key":32},"Spi Interrupt W25Q32 Internal":{"Name":"Spi Interrupt W25Q32 Internal","Type":"Driver","SampleDir":"application/drivers_sample/spi/sample_spi_interrupt_w25q32_internal","SampleDirName":"sample_spi_interrupt_w25q32_internal","SampleFunction":"W25Q32InterruptSampleProcessing()","SampleHead":"#include \"sample_spi_interrupt_w25q32_internal.h\"","Enable":"disable","key":33},"Timer Interrupt":{"Name":"Timer Interrupt","Type":"Driver","SampleDir":"application/drivers_sample/timer/sample_timer_interrupt","SampleDirName":"sample_timer_interrupt","SampleFunction":"TIMER_SampleMain()","SampleHead":"#include \"sample_timer_interrupt.h\"","Enable":"disable","key":34},"Uart Blocking Rx":{"Name":"Uart Blocking Rx","Type":"Driver","SampleDir":"application/drivers_sample/uart/sample_uart_blocking_rx","SampleDirName":"sample_uart_blocking_rx","SampleFunction":"UART_BlcokingRX()","SampleHead":"#include \"sample_uart_blocking_rx.h\"","Enable":"disable","key":35},"Uart Blocking Tx":{"Name":"Uart Blocking Tx","Type":"Driver","SampleDir":"application/drivers_sample/uart/sample_uart_blocking_tx","SampleDirName":"sample_uart_blocking_tx","SampleFunction":"UART_BlcokingTX()","SampleHead":"#include \"sample_uart_blocking_tx.h\"","Enable":"disable","key":36},"Uart Dma Rx":{"Name":"Uart Dma Rx","Type":"Driver","SampleDir":"application/drivers_sample/uart/sample_uart_dma_rx","SampleDirName":"sample_uart_dma_rx","SampleFunction":"UART_DMA_RX()","SampleHead":"#include \"sample_uart_dma_rx.h\"","Enable":"disable","key":37},"Uart Dma Tx":{"Name":"Uart Dma Tx","Type":"Driver","SampleDir":"application/drivers_sample/uart/sample_uart_dma_tx","SampleDirName":"sample_uart_dma_tx","SampleFunction":"UART_DMA_TX()","SampleHead":"#include \"sample_uart_dma_tx.h\"","Enable":"disable","key":38},"Uart Interrupt Tx after Rx":{"Name":"Uart Interrupt Tx after Rx","Type":"Driver","SampleDir":"application/drivers_sample/uart/sample_uart_interrupt_tx_after_rx","SampleDirName":"sample_uart_interrupt_tx_after_rx","SampleFunction":"UART_InterruptTxAfterRx()","SampleHead":"#include \"sample_uart_interrupt_tx_after_rx.h\"","Enable":"disable","key":39},"Uart Interrupt Rx":{"Name":"Uart Interrupt Rx","Type":"Driver","SampleDir":"application/drivers_sample/uart/sample_uart_interrupt_rx","SampleDirName":"sample_uart_interrupt_rx","SampleFunction":"UART_InterruptRX()","SampleHead":"#include \"sample_uart_interrupt_rx.h\"","Enable":"disable","key":40},"Uart Interrupt Tx":{"Name":"Uart Interrupt Tx","Type":"Driver","SampleDir":"application/drivers_sample/uart/sample_uart_interrupt_tx","SampleDirName":"sample_uart_interrupt_tx","SampleFunction":"UART_InterruptTX()","SampleHead":"#include \"sample_uart_interrupt_tx.h\"","Enable":"disable","key":41},"Uart DMA_Tx&DMA_Rx Simultaneously":{"Name":"Uart DMA_Tx&DMA_Rx Simultaneously","Type":"Driver","SampleDir":"application/drivers_sample/uart/sample_uart_dma_tx_dma_rx_simultaneously","SampleDirName":"sample_uart_dma_tx_dma_rx_simultaneously","SampleFunction":"UART_DMATxAndRxSimultaneously()","SampleHead":"#include \"sample_uart_dma_tx_dma_rx_simultaneously.h\"","Enable":"disable","key":42},"Uart DMA_Tx&Int_Rx Simultaneously":{"Name":"Uart DMA_Tx&Int_Rx Simultaneously","Type":"Driver","SampleDir":"application/drivers_sample/uart/sample_uart_dma_tx_int_rx_simultaneously","SampleDirName":"sample_uart_dma_tx_int_rx_simultaneously","SampleFunction":"UART_DMATxAndINTRxSimultaneously()","SampleHead":"#include \"sample_uart_dma_tx_int_rx_simultaneously.h\"","Enable":"disable","key":43},"Uart Int_Tx&DMA_Rx Simultaneously":{"Name":"Uart Int_Tx&DMA_Rx Simultaneously","Type":"Driver","SampleDir":"application/drivers_sample/uart/sample_uart_int_tx_dma_rx_simultaneously","SampleDirName":"sample_uart_int_tx_dma_rx_simultaneously","SampleFunction":"UART_INTTxAndDMARxSimultaneously()","SampleHead":"#include \"sample_uart_int_tx_dma_rx_simultaneously.h\"","Enable":"disable","key":44},"Uart Int_Tx&Int_Rx Simultaneously":{"Name":"Uart Int_Tx&Int_Rx Simultaneously","Type":"Driver","SampleDir":"application/drivers_sample/uart/sample_uart_int_tx_int_rx_simultaneously","SampleDirName":"sample_uart_int_tx_int_rx_simultaneously","SampleFunction":"UART_INTTxAndINTRxSimultaneously()","SampleHead":"#include \"sample_uart_int_tx_int_rx_simultaneously.h\"","Enable":"disable","key":45},"Uart DMA Rx and Cyclically Stored":{"Name":"Uart DMA Rx and Cyclically Stored","Type":"Driver","SampleDir":"application/drivers_sample/uart/sample_uart_dma_rx_cyclically_stored","SampleDirName":"sample_uart_dma_rx_cyclically_stored","SampleFunction":"UART_DMA_RxCyclicallyStored()","SampleHead":"#include \"sample_uart_dma_rx_cyclically_stored.h\"","Enable":"disable","key":46},"Uart Single Wire Communication":{"Name":"Uart Single Wire Communication","Type":"Driver","SampleDir":"application/drivers_sample/uart/sample_uart_single_wire_communication","SampleDirName":"sample_uart_single_wire_communication","SampleFunction":"UART_SingleWireCommunication()","SampleHead":"#include \"sample_uart_single_wire_communication.h\"","Enable":"disable","key":47},"Wdg Reset":{"Name":"Wdg Reset","Type":"Driver","SampleDir":"application/drivers_sample/wdg/sample_wdg_reset","SampleDirName":"sample_wdg_reset","SampleFunction":"WDG_ResetSample()","SampleHead":"#include \"wdg_reset_sample.h\"","Enable":"disable","key":48},"Acmp Sample":{"Name":"Acmp Sample","Type":"Driver","SampleDir":"application/drivers_sample/acmp/sample_acmp","SampleDirName":"sample_acmp","SampleFunction":"SystemInit()","Enable":"disable","key":49},"Apt Single Resistor Sampling":{"Name":"Apt Single Resistor Sampling","Type":"Driver","SampleDir":"application/drivers_sample/apt/sample_apt_single_resistor","SampleDirName":"sample_apt_single_resistor","SampleFunction":"APT_PWMInitHALSample()","SampleHead":"#include \"sample_apt_single_resistor.h\"","Enable":"disable","key":50},"Apt Three Resistor Sampling":{"Name":"Apt Three Resistor Sampling","Type":"Driver","SampleDir":"application/drivers_sample/apt/sample_apt_three_resistor","SampleDirName":"sample_apt_three_resistor","SampleFunction":"APT_PWMInitHALSample()","SampleHead":"#include \"sample_apt_three_resistor.h\"","Enable":"disable","key":51},"Capm Sample":{"Name":"Capm Sample","Type":"Driver","SampleDir":"application/drivers_sample/capm/capm_hall_sample","SampleDirName":"sample_capm","SampleFunction":"CAPM_HallSample()","SampleHead":"#include \"capm_hall_sample.h\"","Enable":"disable","key":52},"Dac Sample":{"Name":"Dac Sample","Type":"Driver","SampleDir":"application/drivers_sample/dac/sample_dac","SampleDirName":"sample_dac","SampleFunction":"SystemInit()","Enable":"disable","key":53},"Pga Sample":{"Name":"Pga Sample","Type":"Driver","SampleDir":"application/drivers_sample/pga/sample_pga","SampleDirName":"sample_pga","SampleFunction":"SystemInit()","Enable":"disable","key":54},"PGA Extra Resistor Sample":{"Name":"PGA Extra Resistor Sample","Type":"Driver","SampleDir":"application/drivers_sample/pga/sample_pga_extra_resistor","SampleDirName":"sample_pga_extra_resistor","SampleFunction":"SystemInit()","Enable":"disable","key":55},"Qdm M method":{"Name":"Qdm M method","Type":"Driver","SampleDir":"application/drivers_sample/qdm/sample_qdm_m","SampleDirName":"sample_qdm_m","SampleFunction":"QDM_SampleM()","SampleHead":"#include \"sample_qdm_m.h\"","Enable":"disable","key":56},"Qdm MT method":{"Name":"Qdm MT method","Type":"Driver","SampleDir":"application/drivers_sample/qdm/sample_qdm_mt","SampleDirName":"sample_qdm_mt","SampleFunction":"QDM_SampleMT()","SampleHead":"#include \"sample_qdm_mt.h\"","Enable":"disable","key":57},"Pmc pvd sample":{"Name":"Pmc pvd sample","Type":"Driver","SampleDir":"application/drivers_sample/pmc/sample_pmc_pvd","SampleDirName":"sample_pmc_pvd","SampleFunction":"PmcPvdSample()","SampleHead":"#include \"sample_pmc_pvd.h\"","Enable":"disable","key":58},"Pmc wakeup sample":{"Name":"Pmc wakeup sample","Type":"Driver","SampleDir":"application/drivers_sample/pmc/sample_pmc_wakeup","SampleDirName":"sample_pmc_wakeup","SampleFunction":"PmcWakeupSample()","SampleHead":"#include \"sample_pmc_wakeup.h\"","Enable":"disable","key":59},"CAN Sample":{"Name":"CAN Sample","Type":"Driver","SampleDir":"application/drivers_sample/can/sample_can_send_receive","SampleDirName":"sample_can_send_receive","SampleFunction":"CAN_ReceiveFilter()","SampleHead":"#include \"sample_can_send_receive.h\"","Enable":"disable","key":60},"IWdg Reset":{"Name":"IWdg Reset","Type":"Driver","SampleDir":"application/drivers_sample/wdg/sample_iwdg_reset","SampleDirName":"sample_iwdg_reset","SampleFunction":"IWDG_ResetSample()","SampleHead":"#include \"iwdg_reset_sample.h\"","Enable":"disable","key":61},"IOCMG IOlist init":{"Name":"IOCMG IOlist init","Type":"Driver","SampleDir":"application/drivers_sample/iocmg/iolist_sample","SampleDirName":"iolist_sample","SampleFunction":"IOCMG_IOListInitSample()","SampleHead":"#include \"iolist_sample.h\"","Enable":"disable","key":62},"I2C Master Blocking AT24C64":{"Name":"I2C Master Blocking AT24C64","Type":"Driver","SampleDir":"application/drivers_sample/i2c/sample_i2c_master_blocking_at24c64","SampleDirName":"sample_i2c_master_blocking_at24c64","SampleFunction":"I2cBlocking24c64Processing()","SampleHead":"#include \"sample_i2c_master_blocking_at24c64.h\"","Enable":"disable","key":63},"I2C Master Interrupt AT24C64":{"Name":"I2C Master Interrupt AT24C64","Type":"Driver","SampleDir":"application/drivers_sample/i2c/sample_i2c_master_interrupt_at24c64","SampleDirName":"sample_i2c_master_interrupt_at24c64","SampleFunction":"I2cInterrupt24c64Processing()","SampleHead":"#include \"sample_i2c_master_interrupt_at24c64.h\"","Enable":"disable","key":64},"I2C Master DMA AT24C64":{"Name":"I2C Master DMA AT24C64","Type":"Driver","SampleDir":"application/drivers_sample/i2c/sample_i2c_master_dma_at24c64","SampleDirName":"sample_i2c_master_dma_at24c64","SampleFunction":"I2cDma24c64Processing()","SampleHead":"#include \"sample_i2c_master_dma_at24c64.h\"","Enable":"disable","key":65},"Bldc Hall Six Step Wave":{"Name":"Bldc Hall Six Step Wave","Type":"Motor","SampleDir":"application/middleware_sample/mcs_hall_bldc_1shunt","SampleDirName":"mcs_hall_bldc_1shunt","SampleFunction":"MotorMain()","SampleHead":"#include \"mcs_motor_process.h\"","Enable":"disable","key":66},"Pmsm Hall 2shunt Foc":{"Name":"Pmsm Hall 2shunt Foc","Type":"Motor","SampleDir":"application/middleware_sample/pmsm_hall_2shunt_foc","SampleDirName":"pmsm_hall_2shunt_foc","SampleFunction":"MotorMainProcess()","SampleHead":"#include \"mcs_motor_process.h\"","Enable":"disable","key":67}},"GPIO Settings":{"GPIO5_6":{"Name":"GPIO5_6","PinName":"PIN32","GpioName":"GPIO_PIN_6","register":"GPIO5","Level":"low","Direction":"output","InterruptMode":"none","InterruptCallback":"","CustomPinName":"LED","Enable":"enable","key":37}},"gpio":{"GPIO":{"GPIO5_6":{"Pin Name":"PIN32"}},"UART0":{"UART0_TXD":{"Pin Name":"PIN52"},"UART0_RXD":{"Pin Name":"PIN53"}}},"pinName":["PIN32","PIN52","PIN53"],"PLIC Settings":{}},"enabled":["GPIO","UART0"],"info":{"board":"","chipName":"3065HRPIRZ","clockName":"clock4","seriesName":"3065h","package":"LQFP64","package path":"d:\\AhaisiMCU\\open_solarec-master","package version":"SolarA2_1.0.1.2","part":"","needSDK":true},"part":{"UART0":{"UART0 Configuration":{"Send Mode":"BLOCKING","Receive Mode":"BLOCKING","Enable Interrupt":"Disable","AS DEBUG UART":true,"UART0_TXD":"PIN52","UART0_RXD":"PIN53","Baud Rate":115200,"Word Length":"8Bits","Parity":"None","Stop Bits":"1Bit","Hardware Flow Control":"Disable","FIFO Mode":"Enable","Send FIFO Threshold":"1/2Full","Receive FIFO Threshold":"1/2Full","Handle Name":"g_uart0","Write Interrupt Callback":"UART0WriteInterruptCallback","Read Interrupt Callback":"UART0ReadInterruptCallback","Interrupt Error Callback":"UART0InterruptErrorCallback","Write DMA Callback":"UART0_TXDMACallback","Read DMA Callback":"UART0_RXDMACallback"},"advancedSetting":{"PLIC Settings":{"IRQ_UART0":{"Name":"IRQ_UART0","dependence":"","Module":"UART0","Priority":"1","Enable":"disable","key":"0"}},"DMA Settings":{"UART0_RX":{"SrcPeriph":"UART0_RX","dependence":"","DestPeriph":"None","Direction":"None","key":"0","Channel":"None","Priority":"None","SrcAddrInc":"UNALTERED","DestAddrInc":"UNALTERED","SrcBurst":"1","DestBurst":"1","SrcWidth":"BYTE","DestWidth":"BYTE","Enable":"disable","Module":"UART0"},"UART0_TX":{"SrcPeriph":"UART0_TX","dependence":"","DestPeriph":"None","Direction":"None","key":"0","Channel":"None","Priority":"None","SrcAddrInc":"UNALTERED","DestAddrInc":"UNALTERED","SrcBurst":"1","DestBurst":"1","SrcWidth":"BYTE","DestWidth":"BYTE","Enable":"disable","Module":"UART0"}}},"pins":{"UART0_TXD":{"Pin Name":"PIN52","dependence":true},"UART0_RXD":{"Pin Name":"PIN53","dependence":true}}}},"globalCheckResult":{"UART0":{"status":"STATUS_OK","tips":""}},"globalCheckItem":{"UART0":[{"check":"all:gpio:UART0:UART0_TXD","tips":[]},{"check":"all:gpio:UART0:UART0_RXD","tips":[]}]},"selectPinName":{},"configType":"menu"} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/board.json b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/board.json new file mode 100644 index 00000000..f74cf64a --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/board.json @@ -0,0 +1 @@ +{"all":{"CLOCKSettings":{"HOSC":"25","LOSC":"32","adc0_cksel":"adc0_cksel_value","adc0_cksel_value":"40","adc0_div":"/5","adc1_cksel":"adc1_cksel_value","adc1_cksel_value":"40","adc1_div":"/5","adc2_cksel":"adc2_cksel_value","adc2_cksel_value":"40","adc2_div":"/5","clk_adc0":"40","clk_adc1":"40","clk_adc2":"40","clk_cs":"/2","clk_dac0_in":"5","clk_dac1_in":"5","clk_dac2_in":"5","dac0_div":"/5","dac1_div":"/5","dac2_div":"/5","clk_gpt0_in":"100","clk_gpt1_in":"100","clk_hs":"200","clk_iwdog":"32","clk_ls":"100","clk_pll":"200","clk_pll_adc":"200","clk_spi_in":"100","clk_tcxo":"30","clk_timer01_in":"100","clk_timer23_in":"100","clk_uart0_in":"100","clk_uart1_in":"100","clk_uart2_in":"100","clk_wdog_in":"100","core_cksel":"clk_pll","gpt0_cksel":"/1","gpt1_cksel":"/1","pll_div":"X32","pll_postdiv":"/1","pll_prediv":"/4","pll_ref_cksel":"HOSC","spi_cksel":"/1","timer01_cksel":"/1","timer23_cksel":"/1","uart0_cksel":"/1","uart1_cksel":"/1","uart2_cksel":"/1","wdog_cksel":"/1"},"SAMPLE Settings":{"Gpio Led":{"Name":"Gpio Led","Type":"Driver","SampleDir":"application/drivers_sample/gpio/sample_gpio_led","SampleDirName":"sample_gpio_led","SampleFunction":"GPIO_LedSample()","SampleHead":"#include \"gpio_led_sample.h\"","Enable":"enable","key":25}},"GPIO Settings":{"GPIO5_6":{"Name":"GPIO5_6","PinName":"PIN32","GpioName":"GPIO_PIN_6","register":"GPIO5","Level":"low","Direction":"output","InterruptMode":"none","InterruptCallback":"","CustomPinName":"LED","Enable":"enable","key":37}},"gpio":{"GPIO":{"GPIO5_6":{"Pin Name":"PIN32"}},"UART0":{"UART0_TXD":{"Pin Name":"PIN52"},"UART0_RXD":{"Pin Name":"PIN53"}},"CAN":{"CAN_RX":{"Pin Name":"PIN39"},"CAN_TX":{"Pin Name":"PIN40"}},"I2C":{"I2C0_SCL":{"Pin Name":"PIN60"},"I2C0_SDA":{"Pin Name":"PIN61"}},"UART2":{"UART2_TXD":{"Pin Name":"PIN36"},"UART2_RXD":{"Pin Name":"PIN37"}}},"pinName":["PIN32","PIN52","PIN53","PIN39","PIN40","PIN60","PIN61","PIN36","PIN37"],"PLIC Settings":{},"DMA Settings":{"UART2_TX":{"SrcPeriph":"UART2_TX","dependence":"","DestPeriph":"Memory","Direction":"Memory_To_Periph","key":0,"Channel":"0","Priority":"Very High","SrcAddrInc":"UNALTERED","DestAddrInc":"UNALTERED","SrcBurst":"1","DestBurst":"1","SrcWidth":"BYTE","DestWidth":"BYTE","Enable":"enable","Module":"UART2","DMARequest":"UART2_TX","dataListDependence":{"ADC0":{"checkItem":[{"check":"part:ADC0:ADC0 Configuration:Sampling Result Output Mode:DMA","tips":["DMA:ADC0","ADC0:Sampling Result Output Mode"]}]},"ADC1":{"checkItem":[{"check":"part:ADC1:ADC1 Configuration:Sampling Result Output Mode:DMA","tips":["DMA:ADC1","ADC1:Sampling Result Output Mode"]}]},"ADC2":{"checkItem":[{"check":"part:ADC2:ADC2 Configuration:Sampling Result Output Mode:DMA","tips":["DMA:ADC2","ADC2:Sampling Result Output Mode"]}]},"I2C_RX":{"checkItem":[{"check":"part:I2C:I2C Configuration:Operating Mode Selection:Dma","tips":["DMA:I2C_RX","I2C:Operating Mode Selection"]}]},"I2C_TX":{"checkItem":[{"check":"part:I2C:I2C Configuration:Operating Mode Selection:Dma","tips":["DMA:I2C_TX","I2C:Operating Mode Selection"]}]},"SPI_TX":{"checkItem":[{"check":"part:SPI:SPI Configuration:Operating Mode Selection:{TX}","tips":["DMA:SPI_TX","SPI:Operating Mode Selection"]}]},"SPI_RX":{"checkItem":[{"check":"part:SPI:SPI Configuration:Operating Mode Selection:{RX}","tips":["DMA:SPI_RX","SPI:Operating Mode Selection"]}]},"CAPM0":{"checkItem":[{"check":"part:CAPM0:CAPM0 Configuration:Enable DMA:Enable","tips":["DMA:CAPM0","CAPM0:Enable DMA"]}]},"CAPM1":{"checkItem":[{"check":"part:CAPM1:CAPM1 Configuration:Enable DMA:Enable","tips":["DMA:CAPM1","CAPM1:Enable DMA"]}]},"CAPM2":{"checkItem":[{"check":"part:CAPM2:CAPM2 Configuration:Enable DMA:Enable","tips":["DMA:CAPM2","CAPM2:Enable DMA"]}]},"UART0_RX":{"checkItem":[{"check":"part:UART0:UART0 Configuration:Receive Mode:DMA","tips":["DMA:UART0","UART0:Receive Mode"]}]},"UART0_TX":{"checkItem":[{"check":"part:UART0:UART0 Configuration:Send Mode:DMA","tips":["DMA:UART0","UART0:Send Mode"]}]},"UART1_RX":{"checkItem":[{"check":"part:UART1:UART1 Configuration:Receive Mode:DMA","tips":["DMA:UART1","UART1:Receive Mode"]}]},"UART1_TX":{"checkItem":[{"check":"part:UART1:UART1 Configuration:Send Mode:DMA","tips":["DMA:UART1","UART1:Send Mode"]}]},"UART2_RX":{"checkItem":[{"check":"part:UART2:UART2 Configuration:Receive Mode:DMA","tips":["DMA:UART2","UART2:Receive Mode"]}]},"UART2_TX":{"checkItem":[{"check":"part:UART2:UART2 Configuration:Send Mode:DMA","tips":["DMA:UART2","UART2:Send Mode"]}]}}},"UART0_TX":{"SrcPeriph":"UART0_TX","dependence":"","DestPeriph":"Memory","Direction":"Memory_To_Periph","key":1,"Channel":"1","Priority":"High","SrcAddrInc":"UNALTERED","DestAddrInc":"UNALTERED","SrcBurst":"1","DestBurst":"1","SrcWidth":"BYTE","DestWidth":"BYTE","Enable":"enable","Module":"UART0","DMARequest":"UART0_TX","dataListDependence":{"ADC0":{"checkItem":[{"check":"part:ADC0:ADC0 Configuration:Sampling Result Output Mode:DMA","tips":["DMA:ADC0","ADC0:Sampling Result Output Mode"]}]},"ADC1":{"checkItem":[{"check":"part:ADC1:ADC1 Configuration:Sampling Result Output Mode:DMA","tips":["DMA:ADC1","ADC1:Sampling Result Output Mode"]}]},"ADC2":{"checkItem":[{"check":"part:ADC2:ADC2 Configuration:Sampling Result Output Mode:DMA","tips":["DMA:ADC2","ADC2:Sampling Result Output Mode"]}]},"I2C_RX":{"checkItem":[{"check":"part:I2C:I2C Configuration:Operating Mode Selection:Dma","tips":["DMA:I2C_RX","I2C:Operating Mode Selection"]}]},"I2C_TX":{"checkItem":[{"check":"part:I2C:I2C Configuration:Operating Mode Selection:Dma","tips":["DMA:I2C_TX","I2C:Operating Mode Selection"]}]},"SPI_TX":{"checkItem":[{"check":"part:SPI:SPI Configuration:Operating Mode Selection:{TX}","tips":["DMA:SPI_TX","SPI:Operating Mode Selection"]}]},"SPI_RX":{"checkItem":[{"check":"part:SPI:SPI Configuration:Operating Mode Selection:{RX}","tips":["DMA:SPI_RX","SPI:Operating Mode Selection"]}]},"CAPM0":{"checkItem":[{"check":"part:CAPM0:CAPM0 Configuration:Enable DMA:Enable","tips":["DMA:CAPM0","CAPM0:Enable DMA"]}]},"CAPM1":{"checkItem":[{"check":"part:CAPM1:CAPM1 Configuration:Enable DMA:Enable","tips":["DMA:CAPM1","CAPM1:Enable DMA"]}]},"CAPM2":{"checkItem":[{"check":"part:CAPM2:CAPM2 Configuration:Enable DMA:Enable","tips":["DMA:CAPM2","CAPM2:Enable DMA"]}]},"UART0_RX":{"checkItem":[{"check":"part:UART0:UART0 Configuration:Receive Mode:DMA","tips":["DMA:UART0","UART0:Receive Mode"]}]},"UART0_TX":{"checkItem":[{"check":"part:UART0:UART0 Configuration:Send Mode:DMA","tips":["DMA:UART0","UART0:Send Mode"]}]},"UART1_RX":{"checkItem":[{"check":"part:UART1:UART1 Configuration:Receive Mode:DMA","tips":["DMA:UART1","UART1:Receive Mode"]}]},"UART1_TX":{"checkItem":[{"check":"part:UART1:UART1 Configuration:Send Mode:DMA","tips":["DMA:UART1","UART1:Send Mode"]}]},"UART2_RX":{"checkItem":[{"check":"part:UART2:UART2 Configuration:Receive Mode:DMA","tips":["DMA:UART2","UART2:Receive Mode"]}]},"UART2_TX":{"checkItem":[{"check":"part:UART2:UART2 Configuration:Send Mode:DMA","tips":["DMA:UART2","UART2:Send Mode"]}]}}}}},"enabled":["GPIO","UART0","CAN","I2C","UART1","UART2"],"info":{"board":"","chipName":"3065HRPIRZ","clockName":"clock4","seriesName":"3065h","package":"LQFP64","package path":"d:\\AhaisiMCU\\open_solarec-master","package version":"SolarA2_1.0.1.2","part":"","needSDK":true},"part":{"UART0":{"UART0 Configuration":{"Send Mode":"DMA","Receive Mode":"BLOCKING","Enable Interrupt":"Disable","AS DEBUG UART":true,"UART0_TXD":"PIN52","UART0_RXD":"PIN53","Baud Rate":115200,"Word Length":"8Bits","Parity":"None","Stop Bits":"1Bit","Hardware Flow Control":"Disable","FIFO Mode":"Enable","Send FIFO Threshold":"1/2Full","Receive FIFO Threshold":"1/2Full","Handle Name":"g_uart0","Write Interrupt Callback":"UART0WriteInterruptCallback","Read Interrupt Callback":"UART0ReadInterruptCallback","Interrupt Error Callback":"UART0InterruptErrorCallback","Write DMA Callback":"UART0_TXDMACallback","Read DMA Callback":"UART0_RXDMACallback"},"advancedSetting":{"PLIC Settings":{"IRQ_UART0":{"Name":"IRQ_UART0","dependence":"","Module":"UART0","Priority":"1","Enable":"disable","key":"0"}},"DMA Settings":{"UART0_RX":{"SrcPeriph":"UART0_RX","dependence":"","DestPeriph":"None","Direction":"None","key":"0","Channel":"None","Priority":"None","SrcAddrInc":"UNALTERED","DestAddrInc":"UNALTERED","SrcBurst":"1","DestBurst":"1","SrcWidth":"BYTE","DestWidth":"BYTE","Enable":"disable","Module":"UART0"},"UART0_TX":{"SrcPeriph":"UART0_TX","dependence":"","DestPeriph":"Memory","Direction":"Memory_To_Periph","key":"0","Channel":"1","Priority":"High","SrcAddrInc":"UNALTERED","DestAddrInc":"UNALTERED","SrcBurst":"1","DestBurst":"1","SrcWidth":"BYTE","DestWidth":"BYTE","Enable":"enable","Module":"UART0","DMARequest":"UART0_TX","dataListDependence":{"ADC0":{"checkItem":[{"check":"part:ADC0:ADC0 Configuration:Sampling Result Output Mode:DMA","tips":["DMA:ADC0","ADC0:Sampling Result Output Mode"]}]},"ADC1":{"checkItem":[{"check":"part:ADC1:ADC1 Configuration:Sampling Result Output Mode:DMA","tips":["DMA:ADC1","ADC1:Sampling Result Output Mode"]}]},"ADC2":{"checkItem":[{"check":"part:ADC2:ADC2 Configuration:Sampling Result Output Mode:DMA","tips":["DMA:ADC2","ADC2:Sampling Result Output Mode"]}]},"I2C_RX":{"checkItem":[{"check":"part:I2C:I2C Configuration:Operating Mode Selection:Dma","tips":["DMA:I2C_RX","I2C:Operating Mode Selection"]}]},"I2C_TX":{"checkItem":[{"check":"part:I2C:I2C Configuration:Operating Mode Selection:Dma","tips":["DMA:I2C_TX","I2C:Operating Mode Selection"]}]},"SPI_TX":{"checkItem":[{"check":"part:SPI:SPI Configuration:Operating Mode Selection:{TX}","tips":["DMA:SPI_TX","SPI:Operating Mode Selection"]}]},"SPI_RX":{"checkItem":[{"check":"part:SPI:SPI Configuration:Operating Mode Selection:{RX}","tips":["DMA:SPI_RX","SPI:Operating Mode Selection"]}]},"CAPM0":{"checkItem":[{"check":"part:CAPM0:CAPM0 Configuration:Enable DMA:Enable","tips":["DMA:CAPM0","CAPM0:Enable DMA"]}]},"CAPM1":{"checkItem":[{"check":"part:CAPM1:CAPM1 Configuration:Enable DMA:Enable","tips":["DMA:CAPM1","CAPM1:Enable DMA"]}]},"CAPM2":{"checkItem":[{"check":"part:CAPM2:CAPM2 Configuration:Enable DMA:Enable","tips":["DMA:CAPM2","CAPM2:Enable DMA"]}]},"UART0_RX":{"checkItem":[{"check":"part:UART0:UART0 Configuration:Receive Mode:DMA","tips":["DMA:UART0","UART0:Receive Mode"]}]},"UART0_TX":{"checkItem":[{"check":"part:UART0:UART0 Configuration:Send Mode:DMA","tips":["DMA:UART0","UART0:Send Mode"]}]},"UART1_RX":{"checkItem":[{"check":"part:UART1:UART1 Configuration:Receive Mode:DMA","tips":["DMA:UART1","UART1:Receive Mode"]}]},"UART1_TX":{"checkItem":[{"check":"part:UART1:UART1 Configuration:Send Mode:DMA","tips":["DMA:UART1","UART1:Send Mode"]}]},"UART2_RX":{"checkItem":[{"check":"part:UART2:UART2 Configuration:Receive Mode:DMA","tips":["DMA:UART2","UART2:Receive Mode"]}]},"UART2_TX":{"checkItem":[{"check":"part:UART2:UART2 Configuration:Send Mode:DMA","tips":["DMA:UART2","UART2:Send Mode"]}]}}}}},"pins":{"UART0_TXD":{"Pin Name":"PIN52","dependence":true},"UART0_RXD":{"Pin Name":"PIN53","dependence":true}}},"CAN":{"CAN Configuration":{"Prescalser":25,"Phase Seg 1(Time Quantum)":"6","Phase Seg 2(Time Quantum)":"3","Sync Jump Width(Time Quantum)":"2","Interrupt Enable":"Disable","FIFO Depth":4,"Operating Mode":"Normal","Auto Retransmission":true,"CAN_RX":"PIN55","CAN_TX":"PIN56","Handle Name":"g_can","Read Finish Callback":"CAN_ReadFinish","Write Finish Callback":"CAN_WriteFinish","Error Callback":"CAN_Transmit_Error"},"advancedSetting":{"PLIC Settings":{"IRQ_CAN":{"Name":"IRQ_CAN","dependence":"","Module":"CAN","Priority":"1","Enable":"disable","key":"0"}}},"pins":{"CAN_RX":{"Pin Name":"PIN39","dependence":true},"CAN_TX":{"Pin Name":"PIN40","dependence":true}}},"I2C":{"I2C Configuration":{"Operating Mode Selection":"Blocking","I2C TX INT FIFO Threshold":32,"I2C TX DMA FIFO Threshold":32,"I2C RX INT FIFO Threshold":32,"I2C RX DMA FIFO Threshold":32,"I2C0_SCL":"PIN60","I2C0_SDA":"PIN61","I2C Speed Frequency(Hz)":100000,"Sda Hold Time":10,"Sda Hold Time(ns)":"100 ns","I2C Address Mode Selection":"7-bit","I2C Ignore Ack Flag":"disable","Handle Name":"g_i2c","Master Tx Callback":"I2CMasterTxCallback","Master Rx Callback":"I2CMasterRxCallback","Error Callback":"I2CErrorCallback"},"advancedSetting":{"DMA Settings":{"I2C_RX":{"SrcPeriph":"I2C_RX","dependence":"","DestPeriph":"None","Direction":"None","key":"0","Channel":"None","Priority":"None","SrcAddrInc":"UNALTERED","DestAddrInc":"INCREASE","SrcBurst":"1","DestBurst":"1","SrcWidth":"BYTE","DestWidth":"BYTE","Enable":"disable","Module":"I2C"},"I2C_TX":{"SrcPeriph":"I2C_TX","dependence":"","DestPeriph":"None","Direction":"None","key":"0","Channel":"None","Priority":"None","SrcAddrInc":"INCREASE","DestAddrInc":"UNALTERED","SrcBurst":"1","DestBurst":"1","SrcWidth":"BYTE","DestWidth":"BYTE","Enable":"disable","Module":"I2C"}},"PLIC Settings":{"IRQ_I2C":{"Name":"IRQ_I2C","dependence":"","Module":"I2C","Priority":"1","Enable":"disable","key":"0"}}},"pins":{"I2C0_SCL":{"Pin Name":"PIN60","dependence":true},"I2C0_SDA":{"Pin Name":"PIN61","dependence":true}}},"UART1":{"UART1 Configuration":{"Send Mode":"BLOCKING","Receive Mode":"BLOCKING","Enable Interrupt":"Disable","AS DEBUG UART":false,"UART1_TXD":"Disable","UART1_RXD":"Disable","UART1_CTSN":"Disable","UART1_RTSN":"Disable","Baud Rate":115200,"Word Length":"8Bits","Parity":"None","Stop Bits":"1Bit","Hardware Flow Control":"Disable","FIFO Mode":"Enable","Send FIFO Threshold":"1/2Full","Receive FIFO Threshold":"1/2Full","Handle Name":"g_uart1","Write Interrupt Callback":"UART1WriteInterruptCallback","Read Interrupt Callback":"UART1ReadInterruptCallback","Interrupt Error Callback":"UART1InterruptErrorCallback","Write DMA Callback":"UART1_TXDMACallback","Read DMA Callback":"UART1_RXDMACallback"},"advancedSetting":{"PLIC Settings":{"IRQ_UART1":{"Name":"IRQ_UART1","dependence":"","Module":"UART1","Priority":"1","Enable":"disable","key":"0"}},"DMA Settings":{"UART1_RX":{"SrcPeriph":"UART1_RX","dependence":"","DestPeriph":"None","Direction":"None","key":"0","Channel":"None","Priority":"None","SrcAddrInc":"UNALTERED","DestAddrInc":"UNALTERED","SrcBurst":"1","DestBurst":"1","SrcWidth":"BYTE","DestWidth":"BYTE","Enable":"disable","Module":"UART1"},"UART1_TX":{"SrcPeriph":"UART1_TX","dependence":"","DestPeriph":"None","Direction":"None","key":"0","Channel":"None","Priority":"None","SrcAddrInc":"UNALTERED","DestAddrInc":"UNALTERED","SrcBurst":"1","DestBurst":"1","SrcWidth":"BYTE","DestWidth":"BYTE","Enable":"disable","Module":"UART1"}}},"pins":{"UART1_TXD":{},"UART1_RXD":{},"UART1_CTSN":{},"UART1_RTSN":{}}},"UART2":{"UART2 Configuration":{"Send Mode":"DMA","Receive Mode":"BLOCKING","Enable Interrupt":"Disable","AS DEBUG UART":false,"UART2_TXD":"PIN36","UART2_RXD":"PIN37","Baud Rate":115200,"Word Length":"8Bits","Parity":"None","Stop Bits":"1Bit","Hardware Flow Control":"Disable","FIFO Mode":"Enable","Send FIFO Threshold":"1/2Full","Receive FIFO Threshold":"1/2Full","Handle Name":"g_uart2","Write Interrupt Callback":"UART2WriteInterruptCallback","Read Interrupt Callback":"UART2ReadInterruptCallback","Interrupt Error Callback":"UART2InterruptErrorCallback","Write DMA Callback":"UART2_TXDMACallback","Read DMA Callback":"UART2_RXDMACallback"},"advancedSetting":{"PLIC Settings":{"IRQ_UART2":{"Name":"IRQ_UART2","dependence":"","Module":"UART2","Priority":"1","Enable":"disable","key":"0"}},"DMA Settings":{"UART2_RX":{"SrcPeriph":"UART2_RX","dependence":"","DestPeriph":"None","Direction":"None","key":"0","Channel":"None","Priority":"None","SrcAddrInc":"UNALTERED","DestAddrInc":"UNALTERED","SrcBurst":"1","DestBurst":"1","SrcWidth":"BYTE","DestWidth":"BYTE","Enable":"disable","Module":"UART2"},"UART2_TX":{"SrcPeriph":"UART2_TX","dependence":"","DestPeriph":"Memory","Direction":"Memory_To_Periph","key":"0","Channel":"0","Priority":"Very High","SrcAddrInc":"UNALTERED","DestAddrInc":"UNALTERED","SrcBurst":"1","DestBurst":"1","SrcWidth":"BYTE","DestWidth":"BYTE","Enable":"enable","Module":"UART2","DMARequest":"UART2_TX","dataListDependence":{"ADC0":{"checkItem":[{"check":"part:ADC0:ADC0 Configuration:Sampling Result Output Mode:DMA","tips":["DMA:ADC0","ADC0:Sampling Result Output Mode"]}]},"ADC1":{"checkItem":[{"check":"part:ADC1:ADC1 Configuration:Sampling Result Output Mode:DMA","tips":["DMA:ADC1","ADC1:Sampling Result Output Mode"]}]},"ADC2":{"checkItem":[{"check":"part:ADC2:ADC2 Configuration:Sampling Result Output Mode:DMA","tips":["DMA:ADC2","ADC2:Sampling Result Output Mode"]}]},"I2C_RX":{"checkItem":[{"check":"part:I2C:I2C Configuration:Operating Mode Selection:Dma","tips":["DMA:I2C_RX","I2C:Operating Mode Selection"]}]},"I2C_TX":{"checkItem":[{"check":"part:I2C:I2C Configuration:Operating Mode Selection:Dma","tips":["DMA:I2C_TX","I2C:Operating Mode Selection"]}]},"SPI_TX":{"checkItem":[{"check":"part:SPI:SPI Configuration:Operating Mode Selection:{TX}","tips":["DMA:SPI_TX","SPI:Operating Mode Selection"]}]},"SPI_RX":{"checkItem":[{"check":"part:SPI:SPI Configuration:Operating Mode Selection:{RX}","tips":["DMA:SPI_RX","SPI:Operating Mode Selection"]}]},"CAPM0":{"checkItem":[{"check":"part:CAPM0:CAPM0 Configuration:Enable DMA:Enable","tips":["DMA:CAPM0","CAPM0:Enable DMA"]}]},"CAPM1":{"checkItem":[{"check":"part:CAPM1:CAPM1 Configuration:Enable DMA:Enable","tips":["DMA:CAPM1","CAPM1:Enable DMA"]}]},"CAPM2":{"checkItem":[{"check":"part:CAPM2:CAPM2 Configuration:Enable DMA:Enable","tips":["DMA:CAPM2","CAPM2:Enable DMA"]}]},"UART0_RX":{"checkItem":[{"check":"part:UART0:UART0 Configuration:Receive Mode:DMA","tips":["DMA:UART0","UART0:Receive Mode"]}]},"UART0_TX":{"checkItem":[{"check":"part:UART0:UART0 Configuration:Send Mode:DMA","tips":["DMA:UART0","UART0:Send Mode"]}]},"UART1_RX":{"checkItem":[{"check":"part:UART1:UART1 Configuration:Receive Mode:DMA","tips":["DMA:UART1","UART1:Receive Mode"]}]},"UART1_TX":{"checkItem":[{"check":"part:UART1:UART1 Configuration:Send Mode:DMA","tips":["DMA:UART1","UART1:Send Mode"]}]},"UART2_RX":{"checkItem":[{"check":"part:UART2:UART2 Configuration:Receive Mode:DMA","tips":["DMA:UART2","UART2:Receive Mode"]}]},"UART2_TX":{"checkItem":[{"check":"part:UART2:UART2 Configuration:Send Mode:DMA","tips":["DMA:UART2","UART2:Send Mode"]}]}}}}},"pins":{"UART2_TXD":{"Pin Name":"PIN36","dependence":true},"UART2_RXD":{"Pin Name":"PIN37","dependence":true}}}},"globalCheckResult":{"UART0":{"status":"STATUS_OK","tips":""},"CAN":{"status":"STATUS_OK","tips":""},"I2C":{"status":"STATUS_OK","tips":""},"UART1":{"status":"STATUS_OK","tips":""},"UART2":{"status":"STATUS_OK","tips":""}},"globalCheckItem":{"UART0":[{"check":"all:gpio:UART0:UART0_TXD","tips":[]},{"check":"all:gpio:UART0:UART0_RXD","tips":[]},{"check":"all:DMA Settings:UART0_TX:Enable:enable","tips":["UART0:Send Mode","DMA:UART0_TX"]}],"CAN":[{"check":"all:gpio:CAN:CAN_RX","tips":[]},{"check":"all:gpio:CAN:CAN_TX","tips":[]}],"I2C":[{"check":"all:gpio:I2C:I2C0_SCL","tips":[]},{"check":"all:gpio:I2C:I2C0_SDA","tips":[]}],"UART1":[],"UART2":[{"check":"all:gpio:UART2:UART2_TXD","tips":[]},{"check":"all:gpio:UART2:UART2_RXD","tips":[]},{"check":"all:DMA Settings:UART2_TX:Enable:enable","tips":["UART2:Send Mode","DMA:UART2_TX"]}]},"selectPinName":{},"configType":"menu"} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/.gn b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/.gn new file mode 100644 index 00000000..823030a8 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/.gn @@ -0,0 +1,21 @@ +# @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +# following disclaimer in the documentation and/or other materials provided with the distribution. +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote +# products derived from this software without specific prior written permission. +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# The location of the build configuration file. + +buildconfig = "//build/config/BUILDCONFIG.gn" + +root = "//build" diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/BUILD.gn b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/BUILD.gn new file mode 100644 index 00000000..99fb0997 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/BUILD.gn @@ -0,0 +1,358 @@ +import("//build/toolchain/config.gni") +set_defaults("executable") { + cflags = [ + "-O0", + "-pipe", + "-Wall", + "-Wextra", + "-Winit-self", + "-Wmissing-include-dirs", + "-Wtrampolines", + "-Werror=undef", + "-Wpointer-arith", + "-Wlogical-op", + "-Wstrict-prototypes", + "-Wmissing-prototypes", + "-Wjump-misses-init", + "-Wformat=2", + "-Wfloat-equal", + "-Wdate-time", + "-Wswitch-default", + "-Wimplicit-fallthrough=2", + "-Wno-missing-declarations", + "-std=gnu11", + "-fsigned-char", + "-fno-builtin", + "-ffreestanding", + "-nostdlib", + "-fno-exceptions", + "-fno-unwind-tables", + "-fno-short-enums", + "-fno-common", + "-freg-struct-return", + "-mabi=ilp32f", + "-march=rv32imfc", + "-fno-strict-aliasing", + "-fdata-sections", + "-ffunction-sections", + "-falign-functions=2", + "-fno-schedule-insns", + "-fno-optimize-strlen", + "-fno-aggressive-loop-optimizations", + "-Wa,-enable-c-lbu-sb", + "-Wa,-enable-c-lhu-sh", + "-msmall-data-limit=0", + "-fimm-compare", + "-femit-muliadd", + "-fmerge-immshf", + "-femit-uxtb-uxth", + "-femit-lli", + "-fldm-stm-optimize", + "-fno-inline-small-functions", + "-mtune=size", + "-mpush-pop", + "-femit-clz", + "-madjust-regorder", + "-madjust-const-cost", + "-freorder-commu-args", + "-fimm-compare-expand", + "-frmv-str-zero", + "-mfp-const-opt", + "-mswitch-jump-table", + "-frtl-sequence-abstract", + "-frtl-hoist-sink", + "-fsafe-alias-multipointer", + "-finline-optimize-size", + "-fmuliadd-expand", + "-mlli-expand", + "-Wa,-mcjal-expand", + "-foptimize-reg-alloc", + "-fsplit-multi-zero-assignments", + "-floop-optimize-size", + "-mpattern-abstract", + "-foptimize-pro-and-epilogue", + "-fstrict-volatile-bitfields", + "-Wcast-align", + "-fstrong-eval-order", + "-Wunused", + "-Wvla", + "-Wshadow", + "-fvisibility=hidden", + "-fsingle-precision-constant", + ] + ldflags = [ + "-Wl,-Map,bin/target.map", + "-Wl,--enjal16", + "-Wl,--gc-section", + "-Wl,--cjal-relax", + "-Wl,--dslf", + "-Wl,--jal-transfer", + "-nostdlib", + "-static", + "-lgcc", + "-lc", + "-Wl,-Bsymbolic", + "-rdynamic", + "-Wl,--no-undefined", + "-T..\chip\3065h\flash.lds", + "-Wl,--whole-archive", + "-L..\middleware\thirdparty\sysroot\lib", + "-lmcs_smo_4th", + "-lnostask", + "-Wl,--no-whole-archive", + ] + defines = [ + "FLOAT_SUPPORT", + ] + if(build_type == "debug") { + cflags += [ + "-g" + ] + }else if(build_type == "release") { + cflags += [ + "-fomit-frame-pointer" + ] + defines += [ + "NDEBUG" + ] + } +} +executable("target.elf") { + sources = [ + "//chip\3065h\startup.S", + "//chip\3065h\chipinit\chipinit.c", + "//chip\3065h\chipinit\adcinit\adcinit.c", + "//chip\3065h\chipinit\adc_tsensor\adc_tsensor.c", + "//chip\3065h\chipinit\crginit\crginit.c", + "//chip\3065h\chipinit\flashinit\flashinit.c", + "//chip\3065h\chipinit\nosinit\nosinit.c", + "//chip\3065h\chipinit\pgainit\pgainit.c", + "//chip\3065h\chipinit\pmcinit\pmcinit.c", + "//chip\3065h\chipinit\systickinit\systickinit.c", + "//chip\3065h\fotp\fotp_info_read.c", + "//chip\3065h\ip_crg\ip_crg_common.c", + "//drivers\acmp\src\acmp.c", + "//drivers\adc\src\adc.c", + "//drivers\adc\src\adc_ex.c", + "//drivers\apt\src\apt.c", + "//drivers\base\src\assert.c", + "//drivers\base\src\base_math.c", + "//drivers\base\src\clock.c", + "//drivers\base\src\generalfunc.c", + "//drivers\base\src\interrupt.c", + "//drivers\base\src\lock.c", + "//drivers\base\src\reset.c", + "//drivers\can\src\can.c", + "//drivers\capm\src\capm.c", + "//drivers\cfd\src\cfd.c", + "//drivers\cmm\src\cmm.c", + "//drivers\crc\src\crc.c", + "//drivers\crg\src\crg.c", + "//drivers\dac\src\dac.c", + "//drivers\dac\src\dac_ex.c", + "//drivers\debug\log\src\app_command.c", + "//drivers\debug\log\src\cmd.c", + "//drivers\debug\log\src\cmd_common.c", + "//drivers\debug\log\src\config.c", + "//drivers\debug\log\src\console.c", + "//drivers\debug\log\src\dfx_debug.c", + "//drivers\debug\log\src\dfx_log.c", + "//drivers\debug\log\src\dfx_log_proc.c", + "//drivers\debug\log\src\event.c", + "//drivers\debug\log\src\ext_command.c", + "//drivers\debug\src\debug.c", + "//drivers\dma\src\dma.c", + "//drivers\EG25\EC200.c", + "//drivers\flash\src\flash.c", + "//drivers\gpio\src\gpio.c", + "//drivers\gpt\src\gpt.c", + "//drivers\i2c\src\i2c.c", + "//drivers\iocmg\src\iocmg.c", + "//drivers\iwdg\src\iwdg.c", + "//drivers\nav\bat.c", + "//drivers\nav\core.c", + "//drivers\nav\mot.c", + "//drivers\pga\src\pga.c", + "//drivers\pmc\src\pmc.c", + "//drivers\qdm\src\qdm.c", + "//drivers\spi\src\spi.c", + "//drivers\timer\src\timer.c", + "//drivers\tsensor\src\tsensor.c", + "//drivers\tsensor\src\tsensor_ex.c", + "//drivers\uart\src\uart.c", + "//drivers\wdg\src\wdg.c", + "//middleware\control_library\adc_calibra\mcs_adcCalibr.c", + "//middleware\control_library\brake\mcs_brake.c", + "//middleware\control_library\filter\mcs_filter.c", + "//middleware\control_library\filter\mcs_lpfRk4.c", + "//middleware\control_library\filter\mcs_pll.c", + "//middleware\control_library\foc_loop_ctrl\mcs_curr_ctrl.c", + "//middleware\control_library\foc_loop_ctrl\mcs_curr_ff.c", + "//middleware\control_library\foc_loop_ctrl\mcs_fw_ctrl.c", + "//middleware\control_library\foc_loop_ctrl\mcs_if_ctrl.c", + "//middleware\control_library\foc_loop_ctrl\mcs_pos_ctrl.c", + "//middleware\control_library\foc_loop_ctrl\mcs_spd_ctrl.c", + "//middleware\control_library\foc_loop_ctrl\mcs_startup.c", + "//middleware\control_library\math\mcs_math.c", + "//middleware\control_library\modulation\mcs_r1_svpwm.c", + "//middleware\control_library\modulation\mcs_svpwm.c", + "//middleware\control_library\observer\mcs_fosmo.c", + "//middleware\control_library\pfc\pfc_curr_ctrl.c", + "//middleware\control_library\pfc\pfc_volt_ctrl.c", + "//middleware\control_library\pid_controller\mcs_pid_ctrl.c", + "//middleware\control_library\power\mcs_power_mgmt.c", + "//middleware\control_library\protection\mcs_openphs_det.c", + "//middleware\control_library\protection\mcs_stall_det.c", + "//middleware\control_library\protection\mcs_unbalance_det.c", + "//middleware\control_library\ramp\mcs_ramp_mgmt.c", + "//middleware\control_library\utilities\mcs_mtr_param.c", + "//middleware\control_library\vf\mcs_vf_ctrl.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\fscanf_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\fwscanf_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\gets_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\memcpy_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\memmove_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\memset_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\scanf_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\securecutil.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\secureinput_a.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\secureinput_w.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\secureprintoutput_a.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\secureprintoutput_w.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\snprintf_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\sprintf_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\sscanf_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\strcat_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\strcpy_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\strncat_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\strncpy_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\strtok_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\swprintf_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\swscanf_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\vfscanf_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\vfwscanf_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\vscanf_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\vsnprintf_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\vsprintf_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\vsscanf_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\vswprintf_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\vswscanf_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\vwscanf_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\wcscat_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\wcscpy_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\wcsncat_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\wcsncpy_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\wcstok_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\wmemcpy_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\wmemmove_s.c", + "//middleware\hisilicon\libboundscheck_v1.1.16\src\wscanf_s.c", + "//middleware\thirdparty\FreeRTOS\Source\croutine.c", + "//middleware\thirdparty\FreeRTOS\Source\event_groups.c", + "//middleware\thirdparty\FreeRTOS\Source\list.c", + "//middleware\thirdparty\FreeRTOS\Source\queue.c", + "//middleware\thirdparty\FreeRTOS\Source\stream_buffer.c", + "//middleware\thirdparty\FreeRTOS\Source\tasks.c", + "//middleware\thirdparty\FreeRTOS\Source\timers.c", + "//middleware\thirdparty\FreeRTOS\Source\CMSIS_RTOS\cmsis_os.c", + "//middleware\thirdparty\FreeRTOS\Source\portable\MemMang\heap_4.c", + "//middleware\thirdparty\FreeRTOS\Source\portable\RVDS\ARM_CM3\port.c", + "//user\main.c", + "//user\generatecode\system_init.c", + "//user\sample_gpio_led\src\gpio_led_sample.c", + ] + include_dirs = [ + "//chip\3065h", + "//chip\3065h\chipinit", + "//chip\3065h\chipinit\adcinit", + "//chip\3065h\chipinit\adc_tsensor", + "//chip\3065h\chipinit\crginit", + "//chip\3065h\chipinit\flashinit", + "//chip\3065h\chipinit\nosinit", + "//chip\3065h\chipinit\pgainit", + "//chip\3065h\chipinit\pmcinit", + "//chip\3065h\chipinit\systickinit", + "//chip\3065h\fotp", + "//chip\3065h\iomap\3065hrpirz", + "//chip\3065h\ip_crg", + "//drivers\acmp\common\inc", + "//drivers\acmp\inc", + "//drivers\adc\common\inc", + "//drivers\adc\inc", + "//drivers\apt\common\inc", + "//drivers\apt\inc", + "//drivers\base\common\inc", + "//drivers\base\inc", + "//drivers\can\common\inc", + "//drivers\can\inc", + "//drivers\capm\common\inc", + "//drivers\capm\inc", + "//drivers\cfd\common\inc", + "//drivers\cfd\inc", + "//drivers\cmm\common\inc", + "//drivers\cmm\inc", + "//drivers\crc\common\inc", + "//drivers\crc\inc", + "//drivers\crg\common\inc", + "//drivers\crg\inc", + "//drivers\dac\common\inc", + "//drivers\dac\inc", + "//drivers\debug\inc", + "//drivers\debug\log\inc", + "//drivers\dma\common\inc", + "//drivers\dma\inc", + "//drivers\EG25", + "//drivers\flash\common\inc", + "//drivers\flash\inc", + "//drivers\gpio\common\inc", + "//drivers\gpio\inc", + "//drivers\gpt\common\inc", + "//drivers\gpt\inc", + "//drivers\i2c\common\inc", + "//drivers\i2c\inc", + "//drivers\iocmg\common", + "//drivers\iocmg\inc", + "//drivers\iwdg\common\inc", + "//drivers\iwdg\inc", + "//drivers\nav", + "//drivers\pga\common\inc", + "//drivers\pga\inc", + "//drivers\pmc\common\inc", + "//drivers\pmc\inc", + "//drivers\qdm\common\inc", + "//drivers\qdm\inc", + "//drivers\spi\common\inc", + "//drivers\spi\inc", + "//drivers\timer\common\inc", + "//drivers\timer\inc", + "//drivers\tsensor\common\inc", + "//drivers\tsensor\inc", + "//drivers\uart\common\inc", + "//drivers\uart\inc", + "//drivers\wdg\common\inc", + "//drivers\wdg\inc", + "//middleware\control_library\adc_calibra", + "//middleware\control_library\brake", + "//middleware\control_library\filter", + "//middleware\control_library\foc_loop_ctrl", + "//middleware\control_library\math", + "//middleware\control_library\modulation", + "//middleware\control_library\observer", + "//middleware\control_library\pfc", + "//middleware\control_library\pid_controller", + "//middleware\control_library\power", + "//middleware\control_library\protection", + "//middleware\control_library\ramp", + "//middleware\control_library\utilities", + "//middleware\control_library\vf", + "//middleware\hisilicon\libboundscheck_v1.1.16\include", + "//middleware\hisilicon\libboundscheck_v1.1.16\src", + "//middleware\thirdparty\FreeRTOS\Source\CMSIS_RTOS", + "//middleware\thirdparty\FreeRTOS\Source\include", + "//middleware\thirdparty\FreeRTOS\Source\portable\RVDS\ARM_CM3", + "//middleware\thirdparty\sysroot\include", + "//user\generatecode", + "//user\sample_gpio_led\inc", + ] + deps = [ + ] +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/build.py b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/build.py new file mode 100644 index 00000000..2bb80f16 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/build.py @@ -0,0 +1,586 @@ +# !/usr/bin/env python +# -*- coding: utf-8 -*- + +# @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +# following disclaimer in the documentation and/or other materials provided with the distribution. +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote +# products derived from this software without specific prior written permission. +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# build.py Function implementation: Build the compilation framework and +# compile the project. + +import sys +import os +import pathlib +import argparse +import collections +import shutil +import subprocess +import distutils.spawn +from configparser import ConfigParser +import platform +import logging +import stat +import shlex + +from build_gn import read_json_file, del_allgn, AutoCreate + + +def usage(): + ''' + Function description: Compiling Commands lists. + ''' + + msg = "\n python build/build.py\n"\ + " python build/build.py build\n"\ + " python build/build.py checkbuild\n"\ + " python build/build.py -t hcc_fpu\n"\ + " python build/build.py -b debug\n" + return msg + + +def copy_xml(): + ''' + Function description: Copy xml file to out. + ''' + build_tmp_path = pathlib.Path.cwd().joinpath('build', 'createxml', + 'mss_prim_db') + xml_path = build_tmp_path.joinpath('dfx_db', 'log.xml') + target_path = pathlib.Path.cwd().joinpath('out') + shutil.copy(xml_path, target_path) + if os.path.isdir(build_tmp_path): + shutil.rmtree(build_tmp_path) + + +def generatefile(file_path, config): + ''' + Function description: Signing Executable Files. + ''' + # Instantiation parameter check. + if not isinstance(file_path, str): + raise TypeError("file_path in para type error {}".format( + type(file_path))) + + file_abspath = pathlib.Path(file_path).resolve() + # Generate the bin file. + bin_abspath = file_abspath.parent.joinpath('{}.bin' + .format(file_abspath.stem)) + cmd = ['riscv32-linux-musl-objcopy', '-Obinary', str(file_abspath), str(bin_abspath)] + process = subprocess.Popen(cmd, shell=False) + process.wait() + ret_code = process.returncode + if ret_code != 0: + raise Exception("bin_file failed, return code is " + ret_code) + + # Generate the hex file. + hex_abspath = file_abspath.parent.joinpath('{}.hex' + .format(file_abspath.stem)) + cmd = ['riscv32-linux-musl-objcopy', '-Oihex', str(file_abspath), str(hex_abspath)] + process = subprocess.Popen(cmd, shell=False) + process.wait() + ret_code = process.returncode + if ret_code != 0: + raise Exception("hex_file failed, return code is " + ret_code) + + # Generate the list file. + if config.build_type == 'debug': + list_path = file_abspath.parent.joinpath('{}.list' + .format(file_abspath.stem)) + if list_path.exists(): + os.remove(list_path) + flags = os.O_WRONLY | os.O_CREAT | os.O_EXCL + modes = stat.S_IWUSR | stat.S_IRUSR + with os.fdopen(os.open(list_path, flags, modes), 'w+') as list_file: + cmd = ['riscv32-linux-musl-objdump', '-S', str(file_abspath)] + process = subprocess.Popen(cmd, stdout=list_file, shell=False) + process.wait() + ret_code = process.returncode + if ret_code != 0: + raise Exception("list_file failed, return code is " + ret_code) + else: + cmd = ['riscv32-linux-musl-strip', str(file_abspath)] + process = subprocess.Popen(cmd, shell=False) + process.wait() + ret_code = process.returncode + if ret_code != 0: + raise Exception("strip failed, return code is " + ret_code) + + +def run_build(**kwargs): + ''' + Function description: Start building. + ''' + + config = kwargs.get('config') + compile_var = Compile() + compile_var.compile(config) + file_path = str(pathlib.Path().joinpath('out', + 'bin', 'target.elf')) + generatefile(file_path, config) + + +def exec_command(cmd, log_path, **kwargs): + ''' + Function description: Run the build command. + ''' + flags = os.O_WRONLY | os.O_CREAT + modes = stat.S_IWUSR | stat.S_IRUSR + with os.fdopen(os.open(log_path, flags, modes), 'w') as log_file: + process = subprocess.Popen(cmd, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + universal_newlines=True, + errors='ignore', + **kwargs) + # Write the build process to the build.log. + for line in iter(process.stdout.readline, ''): + log_file.write(line) + + process.wait() + ret_code = process.returncode + + # An error code is returned when the command is executed. + if ret_code != 0: + with os.fdopen(os.open(log_path, flags, modes), 'at') as log_file: + for line in iter(process.stderr.readline, ''): + log_file.write(line) + raise Exception("{} failed, return code is {}".format(cmd, ret_code)) + + +def parsejson_startautocreat(config): + ''' + Function description: Parsing Chip Template Files. + ''' + + # Obtaining the gn and ninja Paths. + Compile.get_tool_path() + # Read the content of the compilation configuration file. + product_json = pathlib.Path.cwd().joinpath('chip', 'target', + 'userconfig.json') + json_content = read_json_file(product_json) + + if config.action == 'checkbuild': + del_output(config) + check_output(config) + check_extcomponent() + del_allgn() + AutoCreate(json_content) + return True + + +def makedirs(path, exist_ok=True): + ''' + Function description: Creating a directory. + ''' + + try: + os.makedirs(path) + except OSError: + if not pathlib.Path(path).is_dir(): + raise Exception("{} makedirs failed".format(path)) + if not exist_ok: + raise Exception("{} exists, makedirs failed".format(path)) + finally: + pass + + +def remove_readonly(func, path, _): + ''' + Function description: Change the read-only permission to write. + ''' + + os.chmod(path, stat.S_IWRITE) + func(path) + + +def del_output(config): + ''' + Function description: Delete output path. + ''' + + out_path = config.get_out_path() + bin_path = pathlib.Path(out_path).joinpath('bin') + libs_path = pathlib.Path(out_path).joinpath('libs') + obj_path = pathlib.Path(out_path).joinpath('obj') + product_json = pathlib.Path.cwd().joinpath('chip', 'target', + 'userconfig.json') + lib_name = "" + + json_content = read_json_file(product_json) + if json_content['system'][0]['subsystem'][0]['component'][0].get('name'): + lib_name = json_content['system'][0]['subsystem'][0]['component'][0]\ + .get('name') + lib_name = "lib{}.a".format(lib_name) + + for (dirpath, _, filenames) in os.walk(bin_path): + for file in filenames: + if "target" in file or "allinone" in file: + os.remove(pathlib.Path(dirpath).joinpath(file)) + + for (dirpath, _, filenames) in os.walk(libs_path): + for file in filenames: + if file == lib_name: + os.remove(pathlib.Path(dirpath).joinpath(file)) + + for (dirpath, _, filenames) in os.walk(obj_path): + for file in filenames: + if pathlib.Path(file).suffix == '.o': + os.remove(pathlib.Path(dirpath).joinpath(file)) + + +def check_output(config): + ''' + Function description: Recreate output path. + ''' + out_path = config.get_out_path() + if not pathlib.Path(out_path).exists(): + makedirs(out_path) + + +def check_extcomponent(): + ''' + Function description: Deletes output files generated by + external components. + ''' + + ext_inc_path = pathlib.Path('middleware').joinpath( + 'thirdparty', 'sysroot', 'include') + ext_lib_path = pathlib.Path('middleware').joinpath( + 'thirdparty', 'sysroot', 'lib') + if not ext_inc_path.exists(): + makedirs(ext_inc_path) + if not ext_lib_path.exists(): + makedirs(ext_lib_path) + + +def config_create(**kwargs): + ''' + Function description: Start to create configuration. + ''' + + config = kwargs.get('config') + parsejson_startautocreat(config) + return True + + +def exec_create(args): + ''' + Function description: Start creating the compilation process. + ''' + + callback_dict = CallbackDict() + + # parse action + if args.action[0] == 'build' or\ + args.action[0] == 'checkbuild': + config = Config(args) + callback_dict.register(config.action, config_create) + callback_dict.register(config.action, run_build) + callback_dict.execute(config.action, + config=config, + args=args) + elif args.action[0] == 'clean': + config = Config(args) + del_output(config) + del_allgn() + else: + raise Exception("Error: action not found.") + + +class Config(): + ''' + Function description: config config.ini. + ''' + + def __init__(self, args): + self.action = args.action[0] + self.build_type = args.build_type[0] + self.tool_chain = args.tool_chain[0] + self.__set_path() + self.config = pathlib.Path(self.get_build_path())\ + .joinpath('config.ini') + self.log_path = pathlib.Path(self.get_out_path()).joinpath('build.log') + self.cfg = ConfigParser() + self.cfg.read(self.config) + self.toolenv_check() + self.set_default_cmd() + self.set_env_path() + self.args_list = [] + + def get_root_path(self): + if self.__root_path is None: + raise Exception('Error: set root_path first.') + + return self.__root_path + + def get_build_path(self): + if self.__build_path is None: + raise Exception('Error: set build_path first.') + + return self.__build_path + + def get_out_path(self): + if self.__out_path is None: + raise Exception('Error: set out_path first.') + + return self.__out_path + + def toolenv_check(self): + ''' + Function description: Check whether the tool chain path is set. + ''' + + toolspath = self.cfg.get('gn_args', 'tools_path') + user_tool_path = os.path.join(os.path.expanduser("~"), + ".deveco-device-tool/compiler_tool_chain") + if not os.path.exists(user_tool_path): + # use default tool chain path + return + + if toolspath != user_tool_path: + self.cfg.set('gn_args', 'tools_path', user_tool_path) + flags = os.O_WRONLY | os.O_CREAT | os.O_TRUNC + modes = stat.S_IWUSR | stat.S_IRUSR + with os.fdopen(os.open(self.config, flags, modes), + 'w') as configini: + self.cfg.write(configini) + elif not toolspath: + raise Exception("Error: please set config.ini tools_path.") + + def set_default_cmd(self): + ''' + Function description: Write the toolchain and version information to + the config.ini file. + ''' + + section = 'gn_args' + userconfig_file_name = 'userconfig.json' + default_build_type = self.cfg.get(section, 'build_type') + default_tool_chain = self.cfg.get(section, 'toolchain_select') + target_path = pathlib.Path(self.get_root_path()).joinpath('chip', + 'target') + compileopt_path = pathlib.Path(self.get_build_path())\ + .joinpath('config') + + if self.build_type != default_build_type: + if self.build_type != 'debug' and\ + self.build_type != 'release': + raise Exception('Error: {} is not build_type, please check.'\ + .format(self.build_type)) + self.cfg.set(section, 'build_type', self.build_type) + if self.tool_chain != default_tool_chain: + if self.tool_chain != 'hcc' and\ + self.tool_chain != 'hcc_fpu': + raise Exception('Error: {} is not tool_chain, please check.'\ + .format(self.tool_chain)) + # Updating the userconfig.json File. + shutil.copy(pathlib.Path(compileopt_path)\ + .joinpath(self.tool_chain, userconfig_file_name), + target_path) + self.cfg.set(section, 'toolchain_select', self.tool_chain) + if not pathlib.Path(target_path).joinpath(userconfig_file_name).exists(): + # userconfig.json file corresponding to different tool chains. + shutil.copy(pathlib.Path(compileopt_path)\ + .joinpath(self.tool_chain, userconfig_file_name), + target_path) + if self.build_type != default_build_type or\ + self.tool_chain != default_tool_chain: + flags = os.O_WRONLY | os.O_CREAT | os.O_TRUNC + modes = stat.S_IWUSR | stat.S_IRUSR + with os.fdopen(os.open(self.config, flags, modes), + 'w') as configini: + self.cfg.write(configini) + + def set_env_path(self): + ''' + Function description: Write the toolchain and version information to + the config.ini file. + ''' + + compiler_path = None + tools_path = self.cfg.get('gn_args', 'tools_path') + + cur_sys = platform.system() + if cur_sys == "Linux": + gn_name = 'gn-linux' + ninja_name = 'ninja-linux' + hcc_name = 'cc_riscv32_musl' + hccfpu_name = 'cc_riscv32_musl_fp' + elif cur_sys == "Windows": + gn_name = 'gn-win' + ninja_name = 'ninja-win' + hcc_name = 'cc_riscv32_musl_win' + hccfpu_name = 'cc_riscv32_musl_fp_win' + # Setting GN and NINJA env. + gn_path = pathlib.Path(tools_path).joinpath(cur_sys, gn_name) + ninja_path = pathlib.Path(tools_path).joinpath(cur_sys, ninja_name) + # Setting Toolchain env. + if self.tool_chain == 'hcc': + # Check whether the env contains hcc. + compiler_path = distutils.spawn\ + .find_executable("riscv32-linux-musl-gcc") + if compiler_path is None: + # If no, set the hcc path to the env. + compiler_path = pathlib.Path(tools_path)\ + .joinpath(cur_sys, hcc_name, 'bin') + elif self.tool_chain == 'hcc_fpu': + # Check whether the env contains hcc_fpu. + compiler_path = distutils.spawn\ + .find_executable("riscv32-linux-musl-gcc") + if compiler_path is None: + # If no, set the hcc_fpu path to the env. + compiler_path = pathlib.Path(tools_path)\ + .joinpath(cur_sys, hccfpu_name, 'bin') + else: + raise Exception('Error: Unsupported compiler {}.'\ + .format(self.tool_chain)) + + str_path = 'PATH' + if cur_sys == "Linux": + # Setting Temporary Environment Variables + os.environ[str_path] = "{}:{}:{}:{}".format(os.environ[str_path], + gn_path, ninja_path, compiler_path) + elif cur_sys == "Windows": + # Setting Temporary Environment Variables + os.environ[str_path] = "{};{};{};{}".format(os.environ[str_path], + gn_path, ninja_path, compiler_path) + + # get compile cmd + def get_cmd(self, gn_path, ninja_path): + if not pathlib.Path(self.config).exists(): + raise Exception('Error: {} not exist, please check.'.format( + self.config)) + return self.__parse_compile_config(gn_path, ninja_path) + + def get_gn_args(self): + self.args_list.append(self.cfg.get('gn_args', 'build_type_args')) + self.args_list.append(self.cfg.get('gn_args', 'toolchain_args')) + return "".join(self.args_list).replace('\"', '\\"') + + def __set_path(self): + self.__root_path = pathlib.Path.cwd() + self.__build_path = pathlib.Path(self.__root_path).joinpath('build') + if not pathlib.Path(self.__build_path).exists(): + raise Exception('Error: {} not exist, please check.'.format( + self.__build_path)) + self.__out_path = pathlib.Path(self.__root_path)\ + .joinpath('out') + + def __parse_compile_config(self, gn_path, ninja_path): + section = 'env' + self.cfg.set(section, 'build_path', str(self.get_build_path())) + out_relpath = os.path.relpath(self.get_out_path()) + self.cfg.set(section, 'out_path', str(out_relpath)) + self.cfg.set(section, 'gn_path', gn_path) + self.cfg.set(section, 'ninja_path', ninja_path) + self.cfg.set(section, 'gn_args', self.get_gn_args()) + return [self.cfg.get(section, 'gn_cmd'), + self.cfg.get(section, 'ninja_cmd')] + + +class Compile(): + ''' + Function description: Obtain the path of the compilation tool and + start compilation. + ''' + + gn_path = None + ninja_path = None + + @classmethod + def get_tool_path(cls): + # Check whether the GN file exists. + cls.gn_path = distutils.spawn.find_executable('gn') + if cls.gn_path is None: + raise Exception('Error: Can\'t find gn, install it please.') + + # Check whether the NINJA file exists. + cls.ninja_path = distutils.spawn.find_executable('ninja') + if cls.ninja_path is None: + raise Exception('Error: Can\'t find ninja, install it please.') + + def compile(self, config): + cmd_list = config.get_cmd(self.gn_path, self.ninja_path) + for cmd in cmd_list: + # Strings can be directly used in the Windows environment. + if sys.platform == 'linux': + cmd = shlex.split(cmd) + # If shell is True, cmd is a string; if not, a sequence. + exec_command(cmd, log_path=config.log_path, shell=False) + + +class CallbackDict(object): + ''' + Function description: ??? + ''' + + handlers = None + + # write the default value. + def __init__(self): + self.handlers = collections.defaultdict(list) + + def register(self, event, callback): + self.handlers[event].append(callback) + + # ??? + def execute(self, event, **kwargs): + if event not in self.handlers: + raise Exception('{} not found in callback dict'.format(event)) + for handler in self.handlers.get(event, []): + handler(**kwargs) + + +def main(argv): + ''' + Function description: build and compile entry function. + ''' + + # Read the default command value + configini_path = pathlib.Path.cwd().joinpath('build', 'config.ini') + configini = ConfigParser() + configini.read(configini_path) + buildtype_default = configini.get('gn_args', 'build_type') + toolchain_default = configini.get('gn_args', 'toolchain_select') + + # Command parser. + parser = argparse.ArgumentParser(usage=usage(), + description='auto build system') + parser.add_argument('action', help='build or checkbuild or clean or info', + nargs='*', default=['info']) + parser.add_argument('-b', '--build_type', help='release or debug version.', + nargs=1, default=['{}'.format(buildtype_default)]) + parser.add_argument('-t', '--tool_chain', help='hcc or hcc_fpu.', + nargs=1, default=['{}'.format(toolchain_default)]) + parser.set_defaults(command=exec_create) + args = parser.parse_args() + + try: + status = args.command(args) + # Generally, press Ctrl+C to raise exception. + except KeyboardInterrupt: + logging.warning('interrupted') + status = -1 + # Catch Other Exceptions + except Exception as exce: + parser.print_help() + status = -1 + finally: + pass + + return status + + +if __name__ == "__main__": + sys.exit(main(sys.argv)) diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/build_gn.py b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/build_gn.py new file mode 100644 index 00000000..b3ac601d --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/build_gn.py @@ -0,0 +1,819 @@ +# !/usr/bin/env python +# -*- coding: utf-8 -*- + +# @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +# following disclaimer in the documentation and/or other materials provided with the distribution. +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote +# products derived from this software without specific prior written permission. +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# build_gn.py Function implementation: Automatically builds the compilation +# framework. + +import sys +import os +import stat +import subprocess +import pathlib +import json +import shlex +import shutil + +from createxml.mk_prim_xml_step1 import CreateCfg +from createxml.mk_prim_xml_step2 import CreateXml + + +def read_json_file(input_file): + ''' + Function description: Read the json file. + ''' + + if not pathlib.Path(input_file).exists(): + raise Exception('file [{}] no exist.'.format(input_file)) + data = None + with open(input_file, 'rb') as input_f: + data = json.load(input_f) + return data + + +def del_allgn(): + ''' + Function description: Delete all GN build scripts. + ''' + + for (dirpath, _, filenames) in os.walk(pathlib.Path()): + if "build" in dirpath or\ + ("middleware" in dirpath and "hisilicon" in dirpath): + continue + for file in filenames: + if str(pathlib.Path(file)) != 'BUILD.gn': + continue + os.remove(pathlib.Path(dirpath).joinpath(file)) + global_buildfile = pathlib.Path().joinpath('build', 'BUILD.gn') + if global_buildfile.exists(): + os.remove(global_buildfile) + + +class AutoCreate(): + ''' + Function description: Automatically builds the compilation framework. + ''' + + def __init__(self, json_content): + ''' + Function description: Initialization is invoked by default. + ''' + + if 'system' not in json_content: + raise Exception('Error: system not exist,please check.') + + # Stores information about the compile subsystem. + compile_dict = dict() + # Stores information about the transplant subsystem. + transplant_dict = dict() + # Save the path of third-party components so that + # they are not scanned during automatic construction. + self.ext_component_path = [] + + for subsystem in json_content['system']: + if subsystem['name'] == 'compile': + compile_dict = subsystem + elif subsystem['name'] == 'transplant': + transplant_dict = subsystem + + if transplant_dict: + self.subsystem_transplant(transplant_dict) + if compile_dict: + self.subsystem_compile(compile_dict) + else: + raise Exception('Error: compile subsystem not exist,please check.') + + @staticmethod + def check_extcomponentkeys_isexists(ext_component): + # Instantiation parameter check. + str_name = 'name' + str_ext_component = 'ext_component' + str_exec_path = 'exec_path' + if not isinstance(ext_component, dict): + raise TypeError("ext_component in para type error {}".format( + type(ext_component))) + is_exception = str_name not in ext_component or\ + str_ext_component not in ext_component or\ + not ext_component.get(str_name) or\ + not ext_component.get(str_ext_component) + if is_exception: + raise Exception('Error: ext_components are incomplete,' + 'Identification failed.') + + # Check whether the key exists. + if str_exec_path not in ext_component[str_ext_component]: + raise Exception('Error: {} key exec_path not exist, please' + 'check.'.format(ext_component.get(str_name))) + elif 'exec_cmd' not in ext_component[str_ext_component]: + raise Exception('Error: {} key exec_cmd not exist, please' + 'check.'.format(ext_component.get(str_name))) + elif 'includes' not in ext_component[str_ext_component]: + raise Exception('Error: {} key includes not exist, please' + 'check.'.format(ext_component.get(str_name))) + + # If the value is empty, an exception is thrown. + if not ext_component[str_ext_component][str_exec_path]: + raise Exception('Error: {} value exec_path not exist, please' + 'check.'.format(ext_component.get(str_name))) + if not ext_component[str_ext_component]['exec_cmd']: + raise Exception('Error: {} value exec_cmd not exist, please' + 'check.'.format(ext_component.get(str_name))) + # An exception is thrown when the sources fails to be searched. + if not pathlib.Path(ext_component[str_ext_component] + [str_exec_path]).is_dir(): + raise Exception('Error: {} dir not exist, please ' + 'check.'.format(ext_component.get(str_name))) + + @staticmethod + def copy_ext_component_includes(includes_list): + # Instantiation parameter check. + if not isinstance(includes_list, list): + raise TypeError("includes_list in para type error {}".format( + type(includes_list))) + + for include in includes_list: + if not pathlib.Path(include).is_dir(): + raise Exception('Error: {} is not a dir, please ' + 'check.'.format(include)) + for (dirpath, _, filenames) in os.walk(pathlib.Path( + include)): + for file in filenames: + if pathlib.Path(file).suffix != '.h': + continue + include_file = pathlib.Path(dirpath).joinpath(file) + copy_path = pathlib.Path('middleware').joinpath( + 'thirdparty', 'sysroot', 'include') + shutil.copy(include_file, copy_path) + + @staticmethod + def cmd_exec(command): + ''' + Function description: Run the compilation command. + ''' + + # Instantiation parameter check. + if not isinstance(command, str): + raise TypeError("command in para type error {}".format( + type(command))) + + cmd = shlex.split(command) + proc = subprocess.Popen(cmd, shell=False) + proc.wait() + ret_code = proc.returncode + if ret_code != 0: + raise Exception("{} failed, return code is {}".format(cmd, + ret_code)) + + @staticmethod + def check_modulekeys_isexists(module_content): + # Check whether the key exists. + str_sources = 'sources' + if 'name' not in module_content: + raise Exception('Error: {} key name not exist, please check.' + .format(module_content.get(str_sources))) + elif 'target_type' not in module_content: + raise Exception('Error: {} key target_type not exist, please' + 'check.'.format(module_content.get(str_sources))) + elif 'includes' not in module_content: + raise Exception('Error: {} key includes not exist, please check.' + .format(module_content.get(str_sources))) + elif 'define' not in module_content: + raise Exception('Error: {} key define not exist, please check.' + .format(module_content.get(str_sources))) + elif 'libs' not in module_content: + raise Exception('Error: {} key libs not exist, please check.' + .format(module_content.get(str_sources))) + elif 'lds_scripts' not in module_content: + raise Exception('Error: {} key lds_scripts not exist, please' + 'check.'.format(module_content.get(str_sources))) + elif 'cflags' not in module_content: + raise Exception('Error: {} key cflags not exist, please check.' + .format(module_content.get(str_sources))) + elif 'asmflags' not in module_content: + raise Exception('Error: {} key asmflags not exist, please check.' + .format(module_content.get(str_sources))) + elif 'ldflags' not in module_content: + raise Exception('Error: {} key ldflags not exist, please check.' + .format(module_content.get(str_sources))) + + @staticmethod + def nochecklist(path, nocheck_list): + ''' + Function description: If the path exists in the nocheck_list, + a false is returned,Otherwise, a true is returned. + ''' + + # Instantiation parameter check. + if not isinstance(path, str): + raise TypeError("path in para type error {}".format( + type(path))) + if not isinstance(nocheck_list, list): + raise TypeError("nocheck_list in para type error {}".format( + type(nocheck_list))) + + for nocheck in nocheck_list: + if nocheck in path: + return False + + return True + + def subsystem_transplant(self, subsystem): + ''' + Function description: transplant Subsystem + ''' + + # Instantiation parameter check. + if not isinstance(subsystem, dict): + raise TypeError("subsystem in para type error {}".format( + type(subsystem))) + + ext_component_key = 'ext_component' + for ext_component in subsystem['subsystem']: + if not ext_component: + continue + self.check_extcomponentkeys_isexists(ext_component) + + path = str(pathlib.Path( + ext_component[ext_component_key]['exec_path'])) + self.ext_component_path.append(path) + command = ext_component[ext_component_key]['exec_cmd'] + if ext_component[ext_component_key]['includes']: + self.copy_ext_component_includes(ext_component[ext_component_key] + ['includes']) + + curr_dir = os.getcwd() + os.chdir(path) + if '&&' in command: + command_list = command.split('&&') + for cmd in command_list: + self.cmd_exec(cmd) + else: + self.cmd_exec(command) + os.chdir(os.path.realpath(curr_dir)) + + def subsystem_compile(self, subsystem): + ''' + Function description: Compiling Subsystem + ''' + + # Instantiation parameter check. + if not isinstance(subsystem, dict): + raise TypeError("subsystem in para type error {}".format( + type(subsystem))) + + # Records the list of modules to be built in the JSON file. + self.json_module_name = [] + self.json_module_path = [] + # List of paths that are not checked. + self.nocheck = [] + # Save global build parameters in a dictionary. + globalbuild_dict = dict() + + # Read the JSON file to build the module compilation script. + for component in subsystem['subsystem']: + # Perform global build after module build is complete. + if component['name'] == 'compile_frame': + globalbuild_dict = component + continue + for module in component['component']: + # If the key exists and the key value also exists + if 'sources' in module and\ + module.get('sources'): + self.localgn_create(module) + + if not globalbuild_dict: + raise Exception('Error: Global Build Parameters not exist,' + 'please check.') + # Global compilation script building + self.globalgn_create(globalbuild_dict) + + def localgn_create(self, module_content): + ''' + Function description: Module partial construction. + notes: + (1)Create the Build.gn file in the first path of sources. + ''' + + # Instantiation parameter check. + if not isinstance(module_content, dict): + raise TypeError("module_content in para type error {}".format( + type(module_content))) + + self.check_modulekeys_isexists(module_content) + + # Reads the content of the JSON file. + # If the name value is empty, an exception is thrown. + if module_content.get('name'): + self.name = module_content['name'] + else: + raise Exception('Error: module name is None, please check.') + self.json_module_name.append(self.name) + + # If the target_type value is empty, an warning is thrown. + if module_content.get('target_type'): + self.target_type = module_content['target_type'] + else: + self.target_type = "obj" + + # Converting a Relative Path to an Absolute Path. + self.sources = [] + for source_path in module_content['sources']: + self.sources.append("{}".format( + os.path.relpath(pathlib.Path(source_path)))) + self.json_module_path.append(self.sources) + self.includes = [] + for include_path in module_content['includes']: + self.includes.append("{}".format( + os.path.relpath(pathlib.Path(include_path)))) + + self.define = module_content['define'] + self.libs = module_content['libs'] + self.lds_scripts = module_content['lds_scripts'] + self.cflags = module_content['cflags'] + self.asmflags = module_content['asmflags'] + self.ldflags = module_content['ldflags'] + + # Create the Build.gn file in the first path of sources. + self.gn_create(self.sources[0]) + + def globalgn_create(self, globalbuild_dict): + ''' + Function description: Global Build Generates Executable Files. + notes: + (1)Create the Build.gn file in the build directory. + (2)Executable file name:target. + ''' + + str_cflags = 'cflags' + str_ldflags = 'ldflags' + # Instantiation parameter check. + if not isinstance(globalbuild_dict, dict): + raise TypeError("globalbuild_dict in para type error {}".format( + type(globalbuild_dict))) + + # Check whether the key exists. + if 'define' not in globalbuild_dict: + raise Exception('Error: compile_frame key define not exist, please check.') + elif str_cflags not in globalbuild_dict: + raise Exception('Error: compile_frame key cflags not exist, please check.') + elif 'asmflags' not in globalbuild_dict: + raise Exception('Error: compile_frame key asmflags not exist, please check.') + elif str_ldflags not in globalbuild_dict: + raise Exception('Error: compile_frame key ldflags not exist, please check.') + elif 'nocheck' not in globalbuild_dict: + raise Exception('Error: compile_frame key nocheck not exist, please check.') + + # Check whether the value exists. + if not globalbuild_dict.get(str_cflags): + raise Exception('Error: global cflags is None, please check.') + elif not globalbuild_dict.get(str_ldflags): + raise Exception('Error: global ldflags is None, please check.') + + self.name = 'target.elf' + self.target_type = 'executable' + self.sources = [] + self.includes = [] + self.libs = [] + self.extlibspath = [] + self.extlibsname = [] + self.extlibsinclude = [] + for name, path in zip(self.json_module_name, self.json_module_path): + if pathlib.Path(path[0]).is_file(): + self.libs.append("{0}:{1}".format(pathlib.Path(path[0]).parent, name)) + else: + self.libs.append("{0}:{1}".format(path[0], name)) + self.define = globalbuild_dict['define'] + self.cflags = globalbuild_dict[str_cflags] + self.asmflags = globalbuild_dict['asmflags'] + self.ldflags = globalbuild_dict[str_ldflags] + for nocheck_path in globalbuild_dict['nocheck']: + self.nocheck.append("{}".format(pathlib.Path(nocheck_path))) + if 'extlibspath' in globalbuild_dict: + self.extlibspath = globalbuild_dict['extlibspath'] + if 'extlibsname' in globalbuild_dict: + self.extlibsname = globalbuild_dict['extlibsname'] + if 'extlibsinclude' in globalbuild_dict: + self.extlibsinclude = globalbuild_dict['extlibsinclude'] + + self._build_path = pathlib.Path.cwd().joinpath('build') + self.gn_create(self._build_path) + + def gn_create(self, path): + ''' + Function description: Creating a BUILD.gn File. + ''' + + # Module Building Content List + self.build_content = [] + if pathlib.Path(path).is_file(): + path = pathlib.Path(path).parent + buildgn_path = pathlib.Path(path).joinpath('BUILD.gn') + + flags = os.O_WRONLY | os.O_CREAT + modes = stat.S_IWUSR | stat.S_IRUSR + with os.fdopen(os.open(buildgn_path, flags, modes), + 'w') as build_file: + self.build_content.append("import(\"//build/toolchain/config.gni\"" + ")\n") + self.defaults_config() + self.target_config() + build_file.writelines(self.build_content) + + def defaults_config(self): + ''' + Function description: default configuration of the target_type. + ''' + + if self.target_type == "obj": + self.build_content.append("set_defaults(\"source_set\") {\n") + elif self.target_type == "static": + self.build_content.append("set_defaults(\"static_library\") {\n") + elif self.target_type == "share": + self.build_content.append("set_defaults(\"shared_library\") {\n") + elif self.target_type == "executable": + self.build_content.append("set_defaults(\"executable\") {\n") + else: + raise Exception('Error: {} is incorrect, please check.'.format( + self.target_type)) + + self.compileflag_config() + self.define_config() + + self.build_content.append(''' if(build_type == "debug") { + cflags += [ + "-g" + ] + }else if(build_type == "release") { + cflags += [ + "-fomit-frame-pointer" + ] + defines += [ + "NDEBUG" + ] + } +}''') + + def compileflag_config(self): + ''' + Function description: Setting Compilation Parameters. + ''' + + close_bracket = " ]\n" + prefix = " \"" + suffix = "\",\n" + # set cflags + if self.cflags: + self.build_content.append(" cflags = [\n") + for cflags in self.cflags: + self.build_content.append(prefix + cflags + suffix) + self.build_content.append(close_bracket) + + # set asmflags + if self.asmflags: + self.build_content.append(" asmflags = [\n") + for asmflags in self.asmflags: + self.build_content.append(prefix + asmflags + suffix) + self.build_content.append(close_bracket) + + # set ldflags + if self.ldflags: + self.build_content.append(" ldflags = [\n") + for ldflags in self.ldflags: + self.build_content.append(prefix + ldflags + suffix) + + self.lds_scripts_config() + self.library_link_config() + + self.build_content.append(close_bracket) + + def define_config(self): + ''' + Function description: Setting Precompiled Macros. + ''' + + # set define + self.build_content.append(" defines = [\n") + for define in self.define: + self.build_content.append(" \"{}\",\n".format(define)) + self.build_content.append(" ]\n") + + def target_config(self): + ''' + Function description: Required File Configuration for Target. + ''' + + if self.target_type == "obj": + self.build_content.append("source_set(\"%s\") {\n" + % (self.name)) + elif self.target_type == "static": + self.build_content.append("static_library(\"%s\") {\n" + % (self.name)) + elif self.target_type == "share": + self.build_content.append("shared_library(\"%s\") {\n" + % (self.name)) + elif self.target_type == "executable": + self.build_content.append("executable(\"%s\") {\n" + % (self.name)) + else: + raise Exception('Error: {} is incorrect, please check.'.format( + self.target_type)) + + self.sources_config() + self.include_dirs_config() + self.deps_config() + + self.build_content.append("}\n") + + def xml_create(self): + build_xml_para = {} + c_file = self.xmlfiles + module_name = "mcu_xml" + str_dfx_db = 'dfx_db' + build_tmp_path = pathlib.Path.cwd().joinpath('build', 'createxml', + 'mss_prim_db') + if not build_tmp_path: + os.makedirs(build_tmp_path) + prim_xml_cfg_dir = build_tmp_path.joinpath(str_dfx_db, 'xml_cfg') + prim_xml_cfg_file = build_tmp_path.joinpath(str_dfx_db, 'xml_cfg', + module_name + '.cfg') + in_path = pathlib.Path.cwd().joinpath('build', 'createxml', + 'mk_dfx_xml.json') + hdb_xml_temp_root_dir = build_tmp_path.joinpath('modules') + hdb_xml_file_id = pathlib.Path.cwd().joinpath('drivers', + 'debug', 'log', 'inc', 'file_id_defs.h') + prim_xml_key_word = module_name + i_file_dir = build_tmp_path.joinpath('modules', module_name) + prim_xml_dst_full_path = build_tmp_path.joinpath(str_dfx_db, 'log.xml') + sources = c_file + build_xml_para.update({"cflags": self.cflags}) + build_xml_para.update({"c_file": c_file}) + build_xml_para.update({"build_tmp_path": build_tmp_path}) + build_xml_para.update({"prim_xml_cfg_dir": prim_xml_cfg_dir}) + build_xml_para.update({"prim_xml_cfg_file": prim_xml_cfg_file}) + build_xml_para.update({"module_name": module_name}) + build_xml_para.update({"in_path": in_path}) + build_xml_para.update({"hdb_xml_temp_root_dir": hdb_xml_temp_root_dir}) + build_xml_para.update({"hdb_xml_file_id": hdb_xml_file_id}) + build_xml_para.update({"prim_xml_key_word": prim_xml_key_word}) + build_xml_para.update({"i_file_dir": i_file_dir}) + build_xml_para.update({"sources": sources}) + build_xml_para.update({"cc": "riscv32-linux-musl-gcc"}) + build_xml_para.update({"include": self.includes_path}) + build_xml_para.update({"prim_xml_dst_full_path": + prim_xml_dst_full_path}) + createcfg = CreateCfg() + createcfg.generate_params_dic(build_xml_para) + createcfg.get_necessary_information() + createxml = CreateXml() + createxml.get_cfg_files(build_xml_para) + createxml.init_tree() + createxml.parse_cfg_file() + createxml.tree_to_xml() + + def sources_config(self): + ''' + Function description: Source File Configuration. + ''' + + if self.target_type != "executable": + self.local_sources_scan() + return True + + self.global_sources_scan() + return True + + def global_sources_scan(self): + ''' + Function description: Global Source File Search. + ''' + + self.nocheck_lists = [] + self.nocheck_lists_file = [] + + self.build_content.append(" sources = [\n") + self.xmlfiles = [] + for module_list in self.json_module_path: + for sources_list in module_list: + if pathlib.Path(sources_list).is_file(): + self.nocheck_lists_file.append(sources_list) + else: + self.nocheck_lists.append(sources_list) + for nocheck_list in self.nocheck: + self.nocheck_lists.append(nocheck_list) + self.nocheck_lists.extend(self.ext_component_path) + + self._root_path = pathlib.Path() + for (dirpath, dirnames, filenames) in os.walk(self._root_path): + dirnames.sort() + filenames.sort() + # Find all module code except in the JSON file + if not self.nochecklist(dirpath, self.nocheck_lists): + continue + + for file_global in filenames: + if pathlib.Path(file_global).suffix != '.c' and\ + pathlib.Path(file_global).suffix != '.S': + continue + if not self.nochecklist(str(pathlib.Path(dirpath). + joinpath(file_global)), + self.nocheck_lists_file): + continue + if pathlib.Path(file_global).suffix == '.c': + self.xmlfiles.append("{}".format( + pathlib.Path(dirpath) + .joinpath(file_global))) + self.build_content.append(" \"//{}\",\n".format( + pathlib.Path(dirpath) + .joinpath(file_global))) + + self.build_content.append(" ]\n") + + def local_subdirectory_sources_scan(self, sources, cfile_list): + ''' + Function description: Search for source files in the subdirectory. + ''' + + for (dirpath, dirnames, filenames) in os.walk(sources): + dirnames.sort() + filenames.sort() + for file_local in filenames: + if (pathlib.Path(file_local).suffix != '.c' and\ + pathlib.Path(file_local).suffix != '.S') or\ + file_local in cfile_list: + continue + cfile_list.append(file_local) + self.build_content.append(" \"//{}\",\n" + .format(pathlib.Path(dirpath) + .joinpath(file_local))) + + def local_sources_scan(self): + ''' + Function description: module Source File Search. + ''' + + cfile_list = [] + + self.build_content.append(" sources = [\n") + for sources in self.sources: + # An exception is thrown when the sources fails to be searched. + if pathlib.Path(sources).is_file(): + if pathlib.Path(sources).suffix == '.c' or\ + pathlib.Path(sources).suffix == '.S': + self.build_content.append(" \"//{}\",\n" + .format(sources)) + else: + self.local_subdirectory_sources_scan(sources, cfile_list) + + self.build_content.append(" ]\n") + + def include_dirs_config(self): + ''' + Function description: Include Dirs Configuration. + ''' + + # set includes + if self.target_type != "executable": + if self.includes: + self.build_content.append(" include_dirs = [\n") + for include in self.includes: + self.includes_scan(include) + self.build_content.append(" ]\n") + return True + + self.build_content.append(" include_dirs = [\n") + self.includes_scan(pathlib.Path()) + for extlibsinclude in self.extlibsinclude: + self.build_content.append(" \"//{}\",\n" + .format(os.path.relpath(extlibsinclude))) + self.build_content.append(" ]\n") + return True + + def includes_scan(self, path): + self.includes_path = [] + for (dirpath, dirnames, filenames) in os.walk(path): + dirnames.sort() + filenames.sort() + if not self.nochecklist(dirpath, self.ext_component_path): + continue + if not self.nochecklist(dirpath, self.nocheck): + continue + for file in filenames: + if pathlib.Path(file).suffix != '.h': + continue + self.build_content.append(" \"//{}\",\n" + .format(pathlib.Path(dirpath))) + self.includes_path.append("-I" + str(pathlib.Path.cwd() + .joinpath(dirpath))) + break + + def deps_config(self): + ''' + Function description: Dependency Library File Configuration. + ''' + + if self.target_type == "executable": + if self.libs: + self.build_content.append(" deps = [\n") + + for libs in self.libs: + self.build_content.append(" \"//{}\",\n" + .format(libs)) + + self.build_content.append(" ]\n") + + def lds_scripts_config(self): + ''' + Function description: Lds File Configuration. + ''' + + if self.target_type == "executable": + for filename in os.listdir(pathlib.Path("chip")): + if filename == "target": + continue + break + self._lds_scripts_path = pathlib.Path("..").joinpath('chip', + filename, 'flash.lds') + self.build_content.append(" \"-T{}\",\n" + .format(self._lds_scripts_path)) + + def library_link_config(self): + ''' + Function description: Static Library Link Configuration. + ''' + + if self.target_type != "executable": + return + + libs_list = [] + out_path_name = 'out' + libs_path_name = 'libs' + spliter = '.' + libs_path = ["../{}".format(pathlib.Path(out_path_name).joinpath(libs_path_name))] + if pathlib.Path(out_path_name).joinpath(libs_path_name).exists(): + for libname in os.listdir(pathlib.Path(out_path_name).joinpath(libs_path_name)): + if libname.split(spliter)[-1] != 'a': + continue + libname = libname[3:-2] + if libname not in self.json_module_name: + libs_list.append(libname) + if not libs_list: + libs_path = [] + + for (dirpath, _, filenames) in os.walk(pathlib.Path(spliter)): + if out_path_name in dirpath and libs_path_name in dirpath: + continue + for file in filenames: + if file.split(spliter)[-1] == 'a': + libs_path.append(".{}".format(dirpath)) + libs_list.append(file[3:-2]) + + if libs_list or self.extlibsname: + self.build_content.append(" \"-Wl,--whole-archive\",\n") + # Deduplicate paths. + libs_path = list(set(libs_path)) + for libpath in libs_path: + self.build_content.append(" \"-L{}\",\n" + .format(libpath)) + for extlibspath in self.extlibspath: + self.build_content.append(" \"-L{}\",\n" + .format(extlibspath)) + for liblist in libs_list: + self.build_content.append(" \"-l{}\",\n" + .format(liblist)) + for extlibsname in self.extlibsname: + self.build_content.append(" \"-l{}\",\n" + .format(extlibsname[3:-2])) + self.build_content.append(" \"-Wl,--no-whole-archive\",\n") + + +def main(argv): + ''' + Function description: buildgn entry function. + ''' + + #clear gn + del_allgn() + #auto build + product_json = pathlib.Path.cwd().joinpath('chip', 'target', + 'userconfig.json') + json_content = read_json_file(product_json) + AutoCreate(json_content) + + +if __name__ == "__main__": + sys.exit(main(sys.argv)) \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/config.ini b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/config.ini new file mode 100644 index 00000000..01f98190 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/config.ini @@ -0,0 +1,16 @@ +[env] +build_path = +gn_path = +out_path = +gn_args = +gn_cmd = %(gn_path)s gen %(out_path)s --root=. --dotfile=build/.gn --args="%(gn_args)s" +ninja_path = +ninja_cmd = %(ninja_path)s -w dupbuild=warn -C %(out_path)s + +[gn_args] +tools_path = +build_type = release +build_type_args = build_type="%(build_type)s" +toolchain_select = hcc_fpu +toolchain_args = build_compiler_specified="%(toolchain_select)s" +gen_crc = yes diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/config/BUILDCONFIG.gn b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/config/BUILDCONFIG.gn new file mode 100644 index 00000000..db7374fe --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/config/BUILDCONFIG.gn @@ -0,0 +1,25 @@ +# @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +# following disclaimer in the documentation and/or other materials provided with the distribution. +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote +# products derived from this software without specific prior written permission. +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# BUILD.gn Function implementation: Selecting the default compilation toolchain + +import("//build/toolchain/config.gni") + +if (build_compiler_specified == "hcc") { + set_default_toolchain("//build/toolchain:riscv32_hcc") +}else if (build_compiler_specified == "hcc_fpu") { + set_default_toolchain("//build/toolchain:riscv32_hcc") +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/config/hcc/userconfig.json b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/config/hcc/userconfig.json new file mode 100644 index 00000000..ec926c9b --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/config/hcc/userconfig.json @@ -0,0 +1,127 @@ +{ + "system": [ + { + "name": "compile", + "subsystem": [ + { + "name": "static_lib", + "component": [ + { + "name": "", + "target_type": "static", + "sources": [], + "includes": [], + "define": [], + "libs": [], + "lds_scripts": [], + "cflags": [], + "asmflags": [], + "ldflags": [] + } + ] + }, + { + "name": "compile_frame", + "cflags": [ + "-Os", + "-pipe", + "-Wall", + "-Wextra", + "-Winit-self", + "-Wmissing-include-dirs", + "-Wtrampolines", + "-Werror=undef", + "-Wpointer-arith", + "-Wlogical-op", + "-Wstrict-prototypes", + "-Wmissing-prototypes", + "-Wjump-misses-init", + "-Wformat=2", + "-Wfloat-equal", + "-Wdate-time", + "-Wswitch-default", + "-Wimplicit-fallthrough=2", + "-Wno-missing-declarations", + "-std=gnu11", + "-fsigned-char", + "-fno-builtin", + "-ffreestanding", + "-nostdlib", + "-fno-exceptions", + "-fno-unwind-tables", + "-fno-short-enums", + "-fno-common", + "-freg-struct-return", + "-mabi=ilp32", + "-march=rv32imc", + "-fno-strict-aliasing", + "-fdata-sections", + "-ffunction-sections", + "-falign-functions=2", + "-fno-schedule-insns", + "-fno-optimize-strlen", + "-fno-aggressive-loop-optimizations", + "-Wa,-enable-c-lbu-sb", + "-Wa,-enable-c-lhu-sh", + "-msmall-data-limit=0", + "-fimm-compare", + "-femit-muliadd", + "-fmerge-immshf", + "-femit-uxtb-uxth", + "-femit-lli", + "-fldm-stm-optimize", + "-fno-inline-small-functions", + "-mtune=size", + "-mpush-pop", + "-femit-clz", + "-madjust-regorder", + "-madjust-const-cost", + "-freorder-commu-args", + "-fimm-compare-expand", + "-frmv-str-zero", + "-mfp-const-opt", + "-mswitch-jump-table", + "-frtl-sequence-abstract", + "-frtl-hoist-sink", + "-fsafe-alias-multipointer", + "-finline-optimize-size", + "-fmuliadd-expand", + "-mlli-expand", + "-Wa,-mcjal-expand", + "-foptimize-reg-alloc", + "-fsplit-multi-zero-assignments", + "-floop-optimize-size", + "-mpattern-abstract", + "-foptimize-pro-and-epilogue", + "-fstrict-volatile-bitfields", + "-Wcast-align", + "-fstrong-eval-order", + "-Wunused", + "-Wvla", + "-Wshadow", + "-fvisibility=hidden", + "-Werror" + ], + "asmflags": [], + "ldflags": [ + "-Wl,-Map,bin/target.map", + "-Wl,--enjal16", + "-Wl,--gc-section", + "-Wl,--cjal-relax", + "-Wl,--dslf", + "-Wl,--jal-transfer", + "-nostdlib", + "-static", + "-lgcc-nano", + "-lc", + "-Wl,-Bsymbolic", + "-rdynamic", + "-Wl,--no-undefined" + ], + "define": [], + "nocheck": [] + } + ] + } + ] +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/config/hcc_fpu/userconfig.json b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/config/hcc_fpu/userconfig.json new file mode 100644 index 00000000..c7feccf3 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/config/hcc_fpu/userconfig.json @@ -0,0 +1,129 @@ +{ + "system": [ + { + "name": "compile", + "subsystem": [ + { + "name": "static_lib", + "component": [ + { + "name": "", + "target_type": "static", + "sources": [], + "includes": [], + "define": [], + "libs": [], + "lds_scripts": [], + "cflags": [], + "asmflags": [], + "ldflags": [] + } + ] + }, + { + "name": "compile_frame", + "cflags": [ + "-Os", + "-pipe", + "-Wall", + "-Wextra", + "-Winit-self", + "-Wmissing-include-dirs", + "-Wtrampolines", + "-Werror=undef", + "-Wpointer-arith", + "-Wlogical-op", + "-Wstrict-prototypes", + "-Wmissing-prototypes", + "-Wjump-misses-init", + "-Wformat=2", + "-Wfloat-equal", + "-Wdate-time", + "-Wswitch-default", + "-Wimplicit-fallthrough=2", + "-Wno-missing-declarations", + "-std=gnu11", + "-fsigned-char", + "-fno-builtin", + "-ffreestanding", + "-nostdlib", + "-fno-exceptions", + "-fno-unwind-tables", + "-fno-short-enums", + "-fno-common", + "-freg-struct-return", + "-mabi=ilp32f", + "-march=rv32imfc", + "-fno-strict-aliasing", + "-fdata-sections", + "-ffunction-sections", + "-falign-functions=2", + "-fno-schedule-insns", + "-fno-optimize-strlen", + "-fno-aggressive-loop-optimizations", + "-Wa,-enable-c-lbu-sb", + "-Wa,-enable-c-lhu-sh", + "-msmall-data-limit=0", + "-fimm-compare", + "-femit-muliadd", + "-fmerge-immshf", + "-femit-uxtb-uxth", + "-femit-lli", + "-fldm-stm-optimize", + "-fno-inline-small-functions", + "-mtune=size", + "-mpush-pop", + "-femit-clz", + "-madjust-regorder", + "-madjust-const-cost", + "-freorder-commu-args", + "-fimm-compare-expand", + "-frmv-str-zero", + "-mfp-const-opt", + "-mswitch-jump-table", + "-frtl-sequence-abstract", + "-frtl-hoist-sink", + "-fsafe-alias-multipointer", + "-finline-optimize-size", + "-fmuliadd-expand", + "-mlli-expand", + "-Wa,-mcjal-expand", + "-foptimize-reg-alloc", + "-fsplit-multi-zero-assignments", + "-floop-optimize-size", + "-mpattern-abstract", + "-foptimize-pro-and-epilogue", + "-fstrict-volatile-bitfields", + "-Wcast-align", + "-fstrong-eval-order", + "-Wunused", + "-Wvla", + "-Wshadow", + "-fvisibility=hidden", + "-Werror" + ], + "asmflags": [], + "ldflags": [ + "-Wl,-Map,bin/target.map", + "-Wl,--enjal16", + "-Wl,--gc-section", + "-Wl,--cjal-relax", + "-Wl,--dslf", + "-Wl,--jal-transfer", + "-nostdlib", + "-static", + "-lgcc", + "-lc", + "-Wl,-Bsymbolic", + "-rdynamic", + "-Wl,--no-undefined" + ], + "define": [ + "FLOAT_SUPPORT" + ], + "nocheck": [] + } + ] + } + ] +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mk_dfx_xml.json b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mk_dfx_xml.json new file mode 100644 index 00000000..c1f941be --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mk_dfx_xml.json @@ -0,0 +1,10 @@ +{ + "HDB_XML_TEMP_ROOT_DIR":"build/createxml/build_tmp/modules/", + "HDB_XML_FILE_ID":"drivers/log/inc/file_id_defs.h", + + "HDB_PRIM_XML_SRC_FILE" : "build/createxml/mss_prim_db.xml", + + "HDB_PRIM_XML_FILE_ID_BIT" : "14", + "HDB_PRIM_XML_LINE_ID_BIT" : "14", + "HDB_PRIM_XML_PRINT_LEVEL_BIT" : "4" +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mk_prim_xml_step1.py b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mk_prim_xml_step1.py new file mode 100644 index 00000000..1e44025b --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mk_prim_xml_step1.py @@ -0,0 +1,171 @@ +#!/usr/bin/env python +# coding=utf-8 +# Purpose: +# Copyright Huawei Technologies Co.,Ltd. 2022-2022. All rights reserved +# Author: + +import json +import os +import re +import shutil +import sys +import subprocess +import time +import stat + + +class CreateCfg(): + ''' + Function description: create config file. + ''' + + def __init__(self): + self.params = {} + self.file_id_dic = {} + self.dst_full_file_name_list = [] + self.last_file_id_num = 0 + + + @staticmethod + def get_file_id_str(src_file_name): + if not os.path.isfile(src_file_name): + return -1 + with open(src_file_name, 'r', encoding='utf-8', + errors='replace') as file: + for line in file: + mod = re.search(\ + "^#define[\s]+THIS_FILE_ID[\s]+(FILE_ID_[\w]*)",\ + line.strip()) + if mod is None: + continue + return mod.groups()[0] + + + @staticmethod + def get_necessary_information_singleton(fp, file_name): + ''' + Function description: get necessary information for prim xml + ''' + flags = os.O_RDWR | os.O_CREAT + modes = stat.S_IWUSR | stat.S_IRUSR + with os.fdopen(os.open(file_name, flags, modes), 'r+') as src_fp: + line = src_fp.readline() + while line: + match = re.search('_PRIM_ST', line) + if match: + fp.write(line) + line = src_fp.readline() + + + def save_file_id_dict(self, line): + file_id_str = '' + file_id_num = 0 + + mod_1 = re.search("^(FILE_ID_[\w]*).+=\s+(\d*)", line.strip()) + mod_2 = re.search("^(FILE_ID_[\w]*)", line.strip()) + if mod_1 is not None: + file_id_str = mod_1.groups()[0] + file_id_num = mod_1.groups()[1] + self.file_id_dic[file_id_str] = int(file_id_num) + self.last_file_id_num = int(file_id_num) + elif mod_2 is not None: + file_id_str = mod_2.group() + self.last_file_id_num += 1 + self.file_id_dic[file_id_str] = self.last_file_id_num + else: + return -1 + return 0 + + + def create_file_id_dic(self): + file_name = self.params.get('hdb_xml_file_id', 'Not exist') + if not os.path.exists(file_name): + return + + file_d = open(file_name, 'r') + lines = file_d.readlines() + file_d.close() + fsm_status = 0 + for line in lines: + if 0 == fsm_status: + mod = re.search("^typedef enum {", line.strip()) + if mod is not None: + fsm_status = 1 + elif 1 == fsm_status: + mod_1 = re.search("^FILE_ID_[\w]*", line.strip()) + mod_2 = re.search("^}", line.strip()) + if mod_1 is not None: + CreateCfg.save_file_id_dict(self, line.strip()) + elif mod_2 is not None: + fsm_status = 2 + elif 2 == fsm_status: + break + + + def conver_c_2_i(self, full_file_name_list): + not_exist = 'Not exist' + temp_dir = self.params.get('i_file_dir', not_exist) + if os.path.isdir(temp_dir): + shutil.rmtree(temp_dir) + os.makedirs(temp_dir) + cflag = self.params.get('cflags', not_exist) + include = self.params.get('include', not_exist) + for src_full_file_name in full_file_name_list: + file_id_str = CreateCfg.get_file_id_str(src_full_file_name) + if file_id_str is None: + continue + src_file_name = src_full_file_name.rsplit(os.path.sep, 1)[-1] + dst_file_name = src_file_name + dst_file_name = dst_file_name.replace('.c', '.i') + dst_full_file_name = os.path.join(temp_dir, dst_file_name) + file_id_str = self.file_id_dic.get(file_id_str) + if file_id_str is None: + raise Exception(self.file_id_dic) + cmd_line = ['riscv32-linux-musl-gcc', '-E', src_full_file_name] + \ + cflag + include + ["-DMAKE_PRIM_XML_PROCESS_IN", + '-D__FILE_NAME__ = %s' % src_file_name, + '-D__FILE_IDX__ = %s' % file_id_str, + '-P', '-o', dst_full_file_name] + subprocess.run(cmd_line, check=True) + self.dst_full_file_name_list.append(dst_full_file_name) + return self.dst_full_file_name_list + + + def generate_params_dic(self, build_xml_para): + ''' + Function description: convert input to dictionary + ''' + self.params = build_xml_para + CreateCfg.create_file_id_dic(self) + full_file_name_list = self.params.get('sources') + self.dst_full_file_name_list = CreateCfg.conver_c_2_i(self, + full_file_name_list) + if self.dst_full_file_name_list is None: + return -1 + + + def get_necessary_information(self): + ''' + Function description: store necessary information to .cfg + ''' + + cfg_file = self.params.get('prim_xml_cfg_file') + flags = os.O_RDWR | os.O_CREAT + modes = stat.S_IWUSR | stat.S_IRUSR + if os.path.isfile(cfg_file): + os.remove(cfg_file) + if os.path.exists(os.path.dirname(cfg_file)) is False: + os.makedirs(os.path.dirname(cfg_file)) + with os.fdopen(os.open(cfg_file, flags, modes), 'w+') as cfg_fp: + for src_file in self.dst_full_file_name_list: + CreateCfg.get_necessary_information_singleton( + cfg_fp, src_file) + + +def main(): + createcfg = CreateCfg() + createcfg.generate_params_dic() + createcfg.get_necessary_information() + +if __name__ == '__main__': + main() \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mk_prim_xml_step2.py b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mk_prim_xml_step2.py new file mode 100644 index 00000000..21043567 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mk_prim_xml_step2.py @@ -0,0 +1,184 @@ +#!/usr/bin/env python +# coding=utf-8 +# Purpose: +# Copyright Huawei Technologies Co.,Ltd. 2022-2022. All rights reserved +# Author: + +import os +import time +import string +import re +import shutil +import time +import hashlib +import binascii +import sys +import xml.etree.ElementTree as ET +import xml.dom.minidom as XDM + + +class CreateXml(): + ''' + Function description: create xml file + ''' + + def __init__(self): + self.params = {} + + + @staticmethod + def get_loglevel(prim_pri): + prim_loglevel = 'UNKNOWN' + if int(prim_pri) == 0: + real_pri = int(prim_pri) + prim_loglevel = 'FATAL' + elif int(prim_pri) == 1: + real_pri = int(prim_pri) + prim_loglevel = 'ERROR' + elif int(prim_pri) == 2: + real_pri = int(prim_pri) + prim_loglevel = 'WARNING' + elif int(prim_pri) == 3: + real_pri = int(0) + prim_loglevel = 'INFO' + elif int(prim_pri) == 4: + real_pri = int(0) + prim_loglevel = 'DEBUG' + return prim_loglevel + + + @staticmethod + def add_msg_to_xml(file_hdlr, contents): + msg_hdlr = ET.Element('Msg') + attributes = {} + attributes['id'] = str(contents['prim_id']) + attributes['loglevel'] = contents['prim_loglevel'] + attributes['description'] = contents['prim_msg'] + msg_hdlr.attrib = attributes + file_hdlr.append(msg_hdlr) + + + def get_cfg_files(self, build_xml_para): + self.params = build_xml_para + cfg_dir = self.params.get('prim_xml_cfg_dir') + files = os.listdir(cfg_dir) + cfg_files = [] + for file_name in files: + if file_name[-4:] == '.cfg': + cfg_files.append(os.path.join(cfg_dir, file_name)) + self.params['CFG_FILES'] = cfg_files + + + def init_tree(self): + xml_string = '' + root = ET.fromstring(xml_string) + tree = ET.ElementTree(root) + self.params['XML_ROOT'] = root + + + def add_module_to_xml(self, root_hdlr, contents): + prim_mod_id = contents['prim_mod_id'] + + module_hdlr = ET.Element('Module') + attributes = {} + attributes['name'] = prim_mod_id + module_hdlr.attrib = attributes + root_hdlr.append(module_hdlr) + + self.params[prim_mod_id] = {} + self.params.get(prim_mod_id)['handler'] = module_hdlr + return module_hdlr + + + def add_file_to_xml(self, module_hdlr, contents): + prim_mod_id = contents['prim_mod_id'] + prim_file_id = contents['prim_file_id'] + + file_hdlr = ET.Element('File') + attributes = {} + attributes['id'] = str(prim_file_id) + file_hdlr.attrib = attributes + module_hdlr.append(file_hdlr) + + self.params.get(prim_mod_id)[prim_file_id] = {} + self.params.get(prim_mod_id).get(prim_file_id)['handler'] = file_hdlr + return file_hdlr + + + def add_contents_to_xml(self, contents): + prim_file_id = contents['prim_file_id'] + prim_mod_id = contents['prim_mod_id'] + if prim_mod_id not in self.params.keys(): + root_hdlr = self.params.get('XML_ROOT') + module_hdlr = CreateXml.add_module_to_xml(self, root_hdlr, contents) + file_hdlr = CreateXml.add_file_to_xml(self, module_hdlr, contents) + CreateXml.add_msg_to_xml(file_hdlr, contents) + elif prim_file_id not in self.params.get(prim_mod_id): + module_hdlr = self.params.get(prim_mod_id).get('handler') + file_hdlr = CreateXml.add_file_to_xml(self, module_hdlr, contents) + CreateXml.add_msg_to_xml(file_hdlr, contents) + else: + file_hdlr = self.params.get(prim_mod_id).get(prim_file_id).get( + 'handler') + CreateXml.add_msg_to_xml(file_hdlr, contents) + + + def parse_cfg_file_singleton(self, cfg_file): + with open(cfg_file, encoding='utf-8') as fp: + for line in fp: + contents = {} + match_pri = re.search('_PRIM_PRI_ = ', line) + match_msg = re.search(', _PRIM_MSG_ = ', line) + match_line = re.search(', _PRIM_LINE_ = ', line) + match_file_id = re.search(', _PRIM_FILE_ID_ = ', line) + match_mod_id = re.search(', _PRIM_MOD_ID_ = ', line) + match_end = re.search(', _PRIM_END_', line) + + prim_pri = line[match_pri.end():match_msg.start()] + prim_msg = line[match_msg.end():match_line.start()].strip(r'"') + prim_line = line[match_line.end():match_file_id.start()] + prim_file_id = line[match_file_id.end():match_mod_id.start()] + prim_mod_id = line[match_mod_id.end():match_end.start()] + contents['prim_id'] = (int(prim_line)) | (int(prim_file_id) << + 16) + contents['prim_loglevel'] = CreateXml.get_loglevel(prim_pri) + contents['prim_msg'] = prim_msg + contents['prim_file_id'] = prim_file_id + contents['prim_mod_id'] = prim_mod_id + + CreateXml.add_contents_to_xml(self, contents) + + + def parse_cfg_file(self): + for cfg_file in self.params.get('CFG_FILES'): + CreateXml.parse_cfg_file_singleton(self, cfg_file) + + + def tree_to_xml(self): + root = self.params.get('XML_ROOT') + xml_string = ET.tostring(root, encoding='utf-8') + flags = os.O_RDWR | os.O_CREAT + xdm = XDM.parseString(xml_string) + xml_path = self.params.get('prim_xml_dst_full_path') + with os.fdopen(os.open(xml_path, flags, 0o755), 'wb') as f: + f.write(xdm.toprettyxml(indent=' ', encoding='utf-8')) + + +def copy_dir(): + root_path = os.getcwd() + splicing_path = "drivers/debug/log/inc/ext_file_id_defs.h" + src_path = os.path.join(root_path, splicing_path) + target_path = os.path.dirname(self.params.get('PRIM_XML_DST_FULL_PATH')) + shutil.copy(src_path, target_path) + + +def main(): + createxml = CreateXml() + createxml.get_cfg_files() + createxml.init_tree() + createxml.parse_cfg_file() + createxml.tree_to_xml() + copy_dir() + +if __name__ == '__main__': + main() \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mss_prim_db.xml b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mss_prim_db.xml new file mode 100644 index 00000000..8bb3efcf --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mss_prim_db.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mss_prim_db/dfx_db/log.xml b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mss_prim_db/dfx_db/log.xml new file mode 100644 index 00000000..dc46a607 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mss_prim_db/dfx_db/log.xml @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mss_prim_db/dfx_db/xml_cfg/mcu_xml.cfg b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mss_prim_db/dfx_db/xml_cfg/mcu_xml.cfg new file mode 100644 index 00000000..aa5bffca --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mss_prim_db/dfx_db/xml_cfg/mcu_xml.cfg @@ -0,0 +1 @@ + { _PRIM_ST_, _PRIM_PRI_ = 1, _PRIM_MSG_ = "version info is : %x\n", _PRIM_LINE_ = 266, _PRIM_FILE_ID_ = 2001, _PRIM_MOD_ID_ = 12, _PRIM_END_ }; \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mss_prim_db/modules/mcu_xml/dfx_log.i b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mss_prim_db/modules/mcu_xml/dfx_log.i new file mode 100644 index 00000000..5e0e9a2b --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/createxml/mss_prim_db/modules/mcu_xml/dfx_log.i @@ -0,0 +1,2680 @@ +typedef unsigned int size_t; +typedef int ssize_t; +typedef long long off_t; +typedef struct _IO_FILE FILE; +typedef __builtin_va_list va_list; +typedef __builtin_va_list __isoc_va_list; +typedef union _G_fpos64_t { + char __opaque[16]; + long long __lldata; + double __align; +} fpos_t; +extern FILE *const stdin; +extern FILE *const stdout; +extern FILE *const stderr; +FILE *fopen(const char *restrict, const char *restrict); +FILE *freopen(const char *restrict, const char *restrict, FILE *restrict); +int fclose(FILE *); +int remove(const char *); +int rename(const char *, const char *); +int feof(FILE *); +int ferror(FILE *); +int fflush(FILE *); +void clearerr(FILE *); +int fseek(FILE *, long, int); +long ftell(FILE *); +void rewind(FILE *); +int fgetpos(FILE *restrict, fpos_t *restrict); +int fsetpos(FILE *, const fpos_t *); +size_t fread(void *restrict, size_t, size_t, FILE *restrict); +size_t fwrite(const void *restrict, size_t, size_t, FILE *restrict); +int fgetc(FILE *); +int getc(FILE *); +int getchar(void); +int ungetc(int, FILE *); +int fputc(int, FILE *); +int putc(int, FILE *); +int putchar(int); +char *fgets(char *restrict, int, FILE *restrict); +int fputs(const char *restrict, FILE *restrict); +int puts(const char *); +int printf(const char *restrict, ...); +int fprintf(FILE *restrict, const char *restrict, ...); +int sprintf(char *restrict, const char *restrict, ...); +int snprintf(char *restrict, size_t, const char *restrict, ...); +int vprintf(const char *restrict, __isoc_va_list); +int vfprintf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsprintf(char *restrict, const char *restrict, __isoc_va_list); +int vsnprintf(char *restrict, size_t, const char *restrict, __isoc_va_list); +int scanf(const char *restrict, ...); +int fscanf(FILE *restrict, const char *restrict, ...); +int sscanf(const char *restrict, const char *restrict, ...); +int vscanf(const char *restrict, __isoc_va_list); +int vfscanf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsscanf(const char *restrict, const char *restrict, __isoc_va_list); +void perror(const char *); +int setvbuf(FILE *restrict, char *restrict, int, size_t); +void setbuf(FILE *restrict, char *restrict); +char *tmpnam(char *); +FILE *tmpfile(void); +FILE *fmemopen(void *restrict, size_t, const char *restrict); +FILE *open_memstream(char **, size_t *); +FILE *fdopen(int, const char *); +FILE *popen(const char *, const char *); +int pclose(FILE *); +int fileno(FILE *); +int fseeko(FILE *, off_t, int); +off_t ftello(FILE *); +int dprintf(int, const char *restrict, ...); +int vdprintf(int, const char *restrict, __isoc_va_list); +void flockfile(FILE *); +int ftrylockfile(FILE *); +void funlockfile(FILE *); +int getc_unlocked(FILE *); +int getchar_unlocked(void); +int putc_unlocked(int, FILE *); +int putchar_unlocked(int); +ssize_t getdelim(char **restrict, size_t *restrict, int, FILE *restrict); +ssize_t getline(char **restrict, size_t *restrict, FILE *restrict); +int renameat(int, const char *, int, const char *); +char *ctermid(char *); +char *tempnam(const char *, const char *); +char *cuserid(char *); +void setlinebuf(FILE *); +void setbuffer(FILE *, char *, size_t); +int fgetc_unlocked(FILE *); +int fputc_unlocked(int, FILE *); +int fflush_unlocked(FILE *); +size_t fread_unlocked(void *, size_t, size_t, FILE *); +size_t fwrite_unlocked(const void *, size_t, size_t, FILE *); +void clearerr_unlocked(FILE *); +int feof_unlocked(FILE *); +int ferror_unlocked(FILE *); +int fileno_unlocked(FILE *); +int getw(FILE *); +int putw(int, FILE *); +char *fgetln(FILE *, size_t *); +int asprintf(char **, const char *, ...); +int vasprintf(char **, const char *, __isoc_va_list); +typedef struct __locale_struct * locale_t; +void *memcpy (void *restrict, const void *restrict, size_t); +void *memmove (void *, const void *, size_t); +void *memset (void *, int, size_t); +int memcmp (const void *, const void *, size_t); +void *memchr (const void *, int, size_t); +char *strcpy (char *restrict, const char *restrict); +char *strncpy (char *restrict, const char *restrict, size_t); +char *strcat (char *restrict, const char *restrict); +char *strncat (char *restrict, const char *restrict, size_t); +int strcmp (const char *, const char *); +int strncmp (const char *, const char *, size_t); +int strcoll (const char *, const char *); +size_t strxfrm (char *restrict, const char *restrict, size_t); +char *strchr (const char *, int); +char *strrchr (const char *, int); +size_t strcspn (const char *, const char *); +size_t strspn (const char *, const char *); +char *strpbrk (const char *, const char *); +char *strstr (const char *, const char *); +char *strtok (char *restrict, const char *restrict); +size_t strlen (const char *); +char *strerror (int); +int bcmp (const void *, const void *, size_t); +void bcopy (const void *, void *, size_t); +void bzero (void *, size_t); +char *index (const char *, int); +char *rindex (const char *, int); +int ffs (int); +int ffsl (long); +int ffsll (long long); +int strcasecmp (const char *, const char *); +int strncasecmp (const char *, const char *, size_t); +int strcasecmp_l (const char *, const char *, locale_t); +int strncasecmp_l (const char *, const char *, size_t, locale_t); +char *strtok_r (char *restrict, const char *restrict, char **restrict); +int strerror_r (int, char *, size_t); +char *stpcpy(char *restrict, const char *restrict); +char *stpncpy(char *restrict, const char *restrict, size_t); +size_t strnlen (const char *, size_t); +char *strdup (const char *); +char *strndup (const char *, size_t); +char *strsignal(int); +char *strerror_l (int, locale_t); +int strcoll_l (const char *, const char *, locale_t); +size_t strxfrm_l (char *restrict, const char *restrict, size_t, locale_t); +void *memccpy (void *restrict, const void *restrict, int, size_t); +char *strsep(char **, const char *); +size_t strlcat (char *, const char *, size_t); +size_t strlcpy (char *, const char *, size_t); +void explicit_bzero (void *, size_t); +typedef __builtin_va_list __gnuc_va_list; +typedef __gnuc_va_list va_list; +typedef enum { + EXT_SUCCESS = 0x0, + EXT_ERR_USER_BUSY = 0x01060002, + EXT_INVALID = 0xFFFFFFFE, + EXT_FAILURE = 0xFFFFFFFF, +} EXT_MCU_ERRNO; +enum ExtModule { + EXT_MODULE_APP_MAIN, + EXT_MODULE_APP_CONSOLE, + EXT_MODULE_APP_CHIP, + EXT_MODULE_DRV_BASE, + EXT_MODULE_DRV_CHIPS, + EXT_MODULE_DRV_CRG, + EXT_MODULE_DRV_GPIO, + EXT_MODULE_DRV_I2C, + EXT_MODULE_DRV_IRQ, + EXT_MODULE_DRV_PINCTRL, + EXT_MODULE_DRV_TIMER, + EXT_MODULE_DRV_UART, + EXT_MODULE_DFX, + EXT_MODULE_BUTT +}; +typedef enum { + CHIP_LOCK_GPIO0 = 0, + CHIP_LOCK_GPIO1 = 1, + CHIP_LOCK_GPIO2 = 2, + CHIP_LOCK_GPIO3 = 3, + CHIP_LOCK_GPIO4 = 4, + CHIP_LOCK_GPIO5 = 5, + CHIP_LOCK_GPIO6 = 6, + CHIP_LOCK_GPIO7 = 7, + CHIP_LOCK_TOTAL +} CHIP_LockType; +typedef enum { + IRQ_SOFTWARE = 26, + IRQ_UART0 = 28, + IRQ_UART1 = 29, + IRQ_UART2 = 30, + IRQ_TIMER0 = 32, + IRQ_TIMER1 = 33, + IRQ_TIMER2 = 34, + IRQ_TIMER3 = 35, + IRQ_WDG = 40, + IRQ_IWDG = 41, + IRQ_I2C = 42, + IRQ_SPI = 44, + IRQ_CAN = 46, + IRQ_CRC = 47, + IRQ_APT0_EVT = 48, + IRQ_APT0_TMR = 49, + IRQ_APT1_EVT = 50, + IRQ_APT1_TMR = 51, + IRQ_APT2_EVT = 52, + IRQ_APT2_TMR = 53, + IRQ_APT3_EVT = 54, + IRQ_APT3_TMR = 55, + IRQ_APT4_EVT = 56, + IRQ_APT4_TMR = 57, + IRQ_APT5_EVT = 58, + IRQ_APT5_TMR = 59, + IRQ_APT6_EVT = 60, + IRQ_APT6_TMR = 61, + IRQ_APT7_EVT = 62, + IRQ_APT7_TMR = 63, + IRQ_APT8_EVT = 64, + IRQ_APT8_TMR = 65, + IRQ_CMM = 68, + IRQ_CFD = 69, + IRQ_CAPM0 = 70, + IRQ_CAPM1 = 71, + IRQ_CAPM2 = 72, + IRQ_QDM0 = 73, + IRQ_DMA_TC = 77, + IRQ_DMA_ERR = 78, + IRQ_SYSRAM_PARITY_ERR = 79, + IRQ_EFC = 81, + IRQ_EFC_ERR = 82, + IRQ_PMU_CLDO_OCP = 84, + IRQ_PVD = 85, + IRQ_ADC0_OVINT = 92, + IRQ_ADC0_INT1 = 93, + IRQ_ADC0_INT2 = 94, + IRQ_ADC0_INT3 = 95, + IRQ_ADC0_INT4 = 96, + IRQ_ADC1_OVINT = 97, + IRQ_ADC1_INT1 = 98, + IRQ_ADC1_INT2 = 99, + IRQ_ADC1_INT3 = 100, + IRQ_ADC1_INT4 = 101, + IRQ_ADC2_OVINT = 102, + IRQ_ADC2_INT1 = 103, + IRQ_ADC2_INT2 = 104, + IRQ_ADC2_INT3 = 105, + IRQ_ADC2_INT4 = 106, + IRQ_GPIO0 = 109, + IRQ_GPIO1 = 110, + IRQ_GPIO2 = 111, + IRQ_GPIO3 = 112, + IRQ_GPIO4 = 113, + IRQ_GPIO5 = 114, + IRQ_GPIO6 = 115, + IRQ_GPIO7 = 116, + IRQ_MAX, +} IRQ_ID; +typedef int intptr_t; +typedef unsigned int uintptr_t; +typedef enum { + BASE_STATUS_OK = 0x00000000U, + BASE_STATUS_ERROR = 0x00000001U, + BASE_STATUS_BUSY = 0x00000002U, + BASE_STATUS_TIMEOUT = 0x00000003U, + BASE_STATUS_NOT_SUPPORT = 0x00000004U, +} BASE_StatusType; +typedef enum { + BASE_FSM_START, + BASE_DEFINE_FSM_END +} BASE_FSM_Status; +typedef enum { + SYSCTRL_NMI_BIT = 0x00000000U, + SYSCTRL_LOCKUP_BIT = 0x00000002U, + SYSCTRL_HARD_FAULT_BIT = 0x00000003U, + SYSCTRL_DEBUG_BIT = 0x00000004U, + SYSCTRL_SLEEP_BIT = 0x00000005U, + SYSCTRL_PC_VALID_BIT = 0x0000001FU +} SYSCTRL_CPU_Status; +typedef enum { + SYSCTRL_FUNC_JTAG_CORESIGHT = 0x00000000U, + SYSCTRL_FUNC_JYAG_EFLASH = 0x00000001U +} SYSCTRL_FUNC_JTAG_Status; +typedef union { + unsigned int reg; + struct { + unsigned int softresreq : 1; + unsigned int reserved : 31; + } BIT; +} volatile SC_SYS_RES_REG; +typedef union { + unsigned int reg; + struct { + unsigned int soft_rst_cnt : 16; + unsigned int ext_rst_cnt : 16; + } BIT; +} volatile SC_RST_CNT0_REG; +typedef union { + unsigned int reg; + struct { + unsigned int wdg_rst_cnt : 16; + unsigned int iwdg_rst_cnt : 16; + } BIT; +} volatile SC_RST_CNT1_REG; +typedef union { + unsigned int reg; + struct { + unsigned int update_mode_clear : 1; + unsigned int reserved0 : 3; + unsigned int update_mode : 1; + unsigned int reserved1 : 27; + } BIT; +} volatile SC_SYS_STAT_REG; +typedef union { + unsigned int reg; + struct { + unsigned int software_int : 1; + unsigned int reserved : 31; + } BIT; +} volatile SC_SOFT_INT_REG; +typedef union { + unsigned int reg; + struct { + unsigned int swint_evt_id : 32; + } BIT; +} volatile SC_SOFT_EVT_ID_REG; +typedef union { + unsigned int reg; + struct { + unsigned int crg_cfg_lock : 1; + unsigned int sc_cfg_lock : 1; + unsigned int reserved : 30; + } BIT; +} volatile SC_LOCKEN_REG; +typedef union { + unsigned int reg; + struct { + unsigned int sc_hrst_reg0 : 32; + } BIT; +} volatile SC_HRST_REG0_REG; +typedef union { + unsigned int reg; + struct { + unsigned int user_hrst_reg0 : 32; + } BIT; +} volatile USER_HRST_REG0_REG; +typedef union { + unsigned int reg; + struct { + unsigned int user_hrst_reg1 : 32; + } BIT; +} volatile USER_HRST_REG1_REG; +typedef union { + unsigned int reg; + struct { + unsigned int user_por_reg0 : 32; + } BIT; +} volatile USER_POR_REG0_REG; +typedef union { + unsigned int reg; + struct { + unsigned int user_por_reg1 : 32; + } BIT; +} volatile USER_POR_REG1_REG; +typedef union { + unsigned int reg; + struct { + unsigned int user_reg0 : 32; + } BIT; +} volatile USER_REG0_REG; +typedef union { + unsigned int reg; + struct { + unsigned int user_reg1 : 32; + } BIT; +} volatile USER_REG1_REG; +typedef struct _SYSCTRL0_Regstruct { + char space0[4]; + SC_SYS_RES_REG SC_SYS_RES; + SC_RST_CNT0_REG SC_RST_CNT0; + SC_RST_CNT1_REG SC_RST_CNT1; + char space1[8]; + SC_SYS_STAT_REG SC_SYS_STAT; + char space2[4]; + SC_SOFT_INT_REG SC_SOFT_INT; + SC_SOFT_EVT_ID_REG SC_SOFT_EVT_ID; + char space3[28]; + SC_LOCKEN_REG SC_LOCKEN; + char space4[440]; + SC_HRST_REG0_REG SC_HRST_REG0; + char space5[3068]; + USER_POR_REG0_REG USER_POR_REG0; + USER_POR_REG1_REG USER_POR_REG1; + char space6[56]; + USER_HRST_REG0_REG USER_HRST_REG0; + USER_HRST_REG1_REG USER_HRST_REG1; + char space7[56]; + USER_REG0_REG USER_REG0; + USER_REG1_REG USER_REG1; +} volatile SYSCTRL0_RegStruct; +typedef union { + unsigned int reg; + struct { + unsigned int apt0_run : 1; + unsigned int apt1_run : 1; + unsigned int apt2_run : 1; + unsigned int apt3_run : 1; + unsigned int apt4_run : 1; + unsigned int apt5_run : 1; + unsigned int apt6_run : 1; + unsigned int apt7_run : 1; + unsigned int apt8_run : 1; + unsigned int reserved : 23; + } BIT; +} volatile APT_RUN_REG; +typedef union { + unsigned int reg; + struct { + unsigned int poe0_filter_level : 8; + unsigned int poe1_filter_level : 8; + unsigned int poe2_filter_level : 8; + unsigned int poe0_filter_en : 1; + unsigned int poe1_filter_en : 1; + unsigned int poe2_filter_en : 1; + unsigned int reserved : 5; + } BIT; +} volatile APT_POE_FILTER_REG; +typedef union { + unsigned int reg; + struct { + unsigned int apt_evtio4_filter_level : 8; + unsigned int apt_evtio5_filter_level : 8; + unsigned int reserved0 : 8; + unsigned int apt_evtio4_filter_en : 1; + unsigned int apt_evtio5_filter_en : 1; + unsigned int reserved1 : 6; + } BIT; +} volatile APT_EVTIO_FILTER_REG; +typedef union { + unsigned int reg; + struct { + unsigned int apt_evtmp4_filter_level : 8; + unsigned int apt_evtmp5_filter_level : 8; + unsigned int apt_evtmp6_filter_level : 8; + unsigned int apt_evtmp4_filter_en : 1; + unsigned int apt_evtmp5_filter_en : 1; + unsigned int apt_evtmp6_filter_en : 1; + unsigned int reserved : 5; + } BIT; +} volatile APT_EVTMP_FILTER_REG; +typedef union { + unsigned int reg; + struct { + unsigned int capm0_sync_sel : 2; + unsigned int reserved0 : 2; + unsigned int capm1_sync_sel : 2; + unsigned int reserved1 : 2; + unsigned int capm2_sync_sel : 2; + unsigned int reserved2 : 22; + } BIT; +} volatile CAPM_SYNC_SEL_REG; +typedef union { + unsigned int reg; + struct { + unsigned int dma_req0_sel : 1; + unsigned int dma_req1_sel : 1; + unsigned int reserved0 : 3; + unsigned int dma_req5_sel : 1; + unsigned int dma_req6_sel : 1; + unsigned int dma_req7_sel : 1; + unsigned int dma_req8_sel : 1; + unsigned int dma_req9_sel : 1; + unsigned int dma_req10_sel : 1; + unsigned int dma_req11_sel : 1; + unsigned int dma_req12_sel : 1; + unsigned int dma_req13_sel : 1; + unsigned int dma_req14_sel : 1; + unsigned int dma_req15_sel : 1; + unsigned int reserved1 : 16; + } BIT; +} volatile DMA_REQ_SEL_REG; +typedef union { + unsigned int reg; + struct { + unsigned int sysram_parity_err_clr : 1; + unsigned int sysram_parity_err : 1; + unsigned int reserved : 30; + } BIT; +} volatile SYSRAM_ERR_REG; +typedef union { + unsigned int reg; + struct { + unsigned int cpu_in_nmi_hdlr : 1; + unsigned int cpu_ra_wr_en : 1; + unsigned int cpu_lockup_mode : 1; + unsigned int cpu_hard_fault_mode : 1; + unsigned int cpu_debug_mode : 1; + unsigned int cpu_sleep_mode : 1; + unsigned int reserved : 25; + unsigned int cpu_pc_valid : 1; + } BIT; +} volatile CPU_STATUS_REG; +typedef union { + unsigned int reg; + struct { + unsigned int cpu_irf_x1 : 32; + } BIT; +} volatile CPU_IRF_X1_REG; +typedef union { + unsigned int reg; + struct { + unsigned int cpu_irf_x2 : 32; + } BIT; +} volatile CPU_IRF_X2_REG; +typedef union { + unsigned int reg; + struct { + unsigned int tsensor_en : 1; + unsigned int reserved : 31; + } BIT; +} volatile TSENSOR_EN_REG; +typedef union { + unsigned int reg; + struct { + unsigned int adcvref_bg_en : 1; + unsigned int reserved0 : 15; + unsigned int adcvref_bg_trim : 5; + unsigned int reserved1 : 11; + } BIT; +} volatile ADCVREF_CTRL0_REG; +typedef union { + unsigned int reg; + struct { + unsigned int adcvref_adcldo_en : 1; + unsigned int adcvref_adcldo_bypss : 1; + unsigned int reserved0 : 2; + unsigned int adcvref_adcldo_s : 4; + unsigned int reserved1 : 8; + unsigned int adcvref_adcldo_trim : 5; + unsigned int reserved2 : 3; + unsigned int adcvref_adcldo_ib_sel : 1; + unsigned int reserved3 : 6; + unsigned int adcvref_adcldo_ok : 1; + } BIT; +} volatile ADCVREF_CTRL1_REG; +typedef union { + unsigned int reg; + struct { + unsigned int adcvref_refbuf_en0 : 1; + unsigned int reserved0 : 3; + unsigned int adcvref_refbuf_s0 : 1; + unsigned int reserved1 : 3; + unsigned int adcvref_refbuf_sel0 : 1; + unsigned int reserved2 : 7; + unsigned int adcvref_refbuf_trim0_2p0v : 5; + unsigned int reserved3 : 3; + unsigned int adcvref_refbuf_trim0_2p5v : 5; + unsigned int reserved4 : 3; + } BIT; +} volatile ADC0_VREF_CTRL_REG; +typedef union { + unsigned int reg; + struct { + unsigned int adcvref_refbuf_en1 : 1; + unsigned int reserved0 : 3; + unsigned int adcvref_refbuf_s1 : 1; + unsigned int reserved1 : 3; + unsigned int adcvref_refbuf_sel1 : 1; + unsigned int reserved2 : 7; + unsigned int adcvref_refbuf_trim1_2p0v : 5; + unsigned int reserved3 : 3; + unsigned int adcvref_refbuf_trim1_2p5v : 5; + unsigned int reserved4 : 3; + } BIT; +} volatile ADC1_VREF_CTRL_REG; +typedef union { + unsigned int reg; + struct { + unsigned int adcvref_refbuf_en2 : 1; + unsigned int reserved0 : 3; + unsigned int adcvref_refbuf_s2 : 1; + unsigned int reserved1 : 3; + unsigned int adcvref_refbuf_sel2 : 1; + unsigned int reserved2 : 7; + unsigned int adcvref_refbuf_trim2_2p0v : 5; + unsigned int reserved3 : 3; + unsigned int adcvref_refbuf_trim2_2p5v : 5; + unsigned int reserved4 : 3; + } BIT; +} volatile ADC2_VREF_CTRL_REG; +typedef union { + unsigned int reg; + struct { + unsigned int adcvref_test_en : 1; + unsigned int reserved0 : 3; + unsigned int adcvref_test_sel : 4; + unsigned int reserved1 : 8; + unsigned int adcvref_rsv : 8; + unsigned int reserved2 : 8; + } BIT; +} volatile ADCVREF_CTRL6_REG; +typedef union { + unsigned int reg; + struct { + unsigned int adc2core_iso : 1; + unsigned int reserved : 31; + } BIT; +} volatile ADC2CORE_ISO_REG; +typedef union { + unsigned int reg; + struct { + unsigned int adc_ob_sel : 2; + unsigned int reserved : 30; + } BIT; +} volatile ADC_OB_SEL_REG; +typedef struct _SYSCTRL1_RegStruct { + char space0[0x8000]; + APT_RUN_REG APT_RUN; + char space1[12]; + APT_POE_FILTER_REG APT_POE_FILTER; + APT_EVTIO_FILTER_REG APT_EVTIO_FILTER; + APT_EVTMP_FILTER_REG APT_EVTMP_FILTER; + char space2[484]; + DMA_REQ_SEL_REG DMA_REQ_SEL; + char space3[252]; + SYSRAM_ERR_REG SYSRAM_ERR; + char space4[3324]; + CPU_STATUS_REG CPU_STATUS; + char space5[4092]; + TSENSOR_EN_REG TSENSOR_EN; + char space6[4092]; + ADCVREF_CTRL0_REG ADCVREF_CTRL0; + ADCVREF_CTRL1_REG ADCVREF_CTRL1; + ADC0_VREF_CTRL_REG ADC0_VREF_CTRL; + ADC1_VREF_CTRL_REG ADC1_VREF_CTRL; + ADC2_VREF_CTRL_REG ADC2_VREF_CTRL; + char space7[4]; + ADCVREF_CTRL6_REG ADCVREF_CTRL6; + char space8[20444]; + ADC_OB_SEL_REG ADC_OB_SEL; +} volatile SYSCTRL1_RegStruct; +static inline void DCL_SYSCTRL_SoftReset(void) +{ + ((SYSCTRL0_RegStruct *)(void *)0x10100000)->SC_SYS_RES.BIT.softresreq = 1; +} +static inline unsigned short DCL_SYSCTRL_GetSoftResetConut(void) +{ + return ((SYSCTRL0_RegStruct *)(void *)0x10100000)->SC_RST_CNT0.BIT.soft_rst_cnt; +} +static inline unsigned short DCL_SYSCTRL_GetPinResetConut(void) +{ + return ((SYSCTRL0_RegStruct *)(void *)0x10100000)->SC_RST_CNT0.BIT.ext_rst_cnt; +} +static inline unsigned short DCL_SYSCTRL_GetWdgResetConut(void) +{ + return ((SYSCTRL0_RegStruct *)(void *)0x10100000)->SC_RST_CNT1.BIT.wdg_rst_cnt; +} +static inline unsigned short DCL_SYSCTRL_GetIWdgResetConut(void) +{ + return ((SYSCTRL0_RegStruct *)(void *)0x10100000)->SC_RST_CNT1.BIT.iwdg_rst_cnt; +} +static inline void DCL_SYSCTRL_ScWriteProtectionDisable(void) +{ + ((SYSCTRL0_RegStruct *)(void *)0x10100000)->SC_LOCKEN.reg = (((SYSCTRL0_RegStruct *)(void *)0x10100000)->SC_LOCKEN.reg & 0x0000FFFDU) + 0xEA510000U; +} +static inline void DCL_SYSCTRL_ScWriteProtectionEnable(void) +{ + ((SYSCTRL0_RegStruct *)(void *)0x10100000)->SC_LOCKEN.reg = ((((SYSCTRL0_RegStruct *)(void *)0x10100000)->SC_LOCKEN.reg & 0x0000FFFFU) | 0x00000002U) + + 0xEA510000U; +} +static inline void DCL_SYSCTRL_CrgWriteProtectionDisable(void) +{ + ((SYSCTRL0_RegStruct *)(void *)0x10100000)->SC_LOCKEN.reg = (((SYSCTRL0_RegStruct *)(void *)0x10100000)->SC_LOCKEN.reg & 0x0000FFFEU) + 0xEA510000U; +} +static inline void DCL_SYSCTRL_CrgWriteProtectionEnable(void) +{ + ((SYSCTRL0_RegStruct *)(void *)0x10100000)->SC_LOCKEN.reg = ((((SYSCTRL0_RegStruct *)(void *)0x10100000)->SC_LOCKEN.reg & 0x0000FFFFU) | 0x00000001U) + + 0xEA510000U; +} +static inline void DCL_SYSCTRL_GenerateSoftInterrupt(void) +{ + ((SYSCTRL0_RegStruct *)(void *)0x10100000)->SC_SOFT_INT.BIT.software_int = 1; +} +static inline void DCL_SYSCTRL_ClearSoftInterrupt(void) +{ + ((SYSCTRL0_RegStruct *)(void *)0x10100000)->SC_SOFT_INT.BIT.software_int = 0; +} +static inline void DCL_SYSCTRL_SetSoftInterruptEventId(unsigned int id) +{ + ((SYSCTRL0_RegStruct *)(void *)0x10100000)->SC_SOFT_EVT_ID.BIT.swint_evt_id = id; +} +static inline unsigned int DCL_SYSCTRL_GetSoftInterruptEventId(void) +{ + return ((SYSCTRL0_RegStruct *)(void *)0x10100000)->SC_SOFT_EVT_ID.BIT.swint_evt_id; +} +static inline unsigned int DCL_SYSCTRL_GetSysramParityErrorStatus(void) +{ + return ((SYSCTRL1_RegStruct *)(void *)0x10100000)->SYSRAM_ERR.BIT.sysram_parity_err; +} +static inline void DCL_SYSCTRL_ClearSysramParityError(void) +{ + ((SYSCTRL1_RegStruct *)(void *)0x10100000)->SYSRAM_ERR.BIT.sysram_parity_err_clr = 1; +} +static inline _Bool DCL_SYSCTRL_CheckCpuStatus(SYSCTRL_CPU_Status offset) +{ + return ((((SYSCTRL1_RegStruct *)(void *)0x10100000)->CPU_STATUS.reg) & (1 << offset)) == 0 ? 0 : 1; +} +static inline void DCL_SYSCTRL_EnableTsensor(void) +{ + ((SYSCTRL1_RegStruct *)(void *)0x10100000)->TSENSOR_EN.BIT.tsensor_en = 0x01; +} +static inline void DCL_SYSCTRL_DisableTsensor(void) +{ + ((SYSCTRL1_RegStruct *)(void *)0x10100000)->TSENSOR_EN.BIT.tsensor_en = 0x00; +} +unsigned int SYSTICK_GetCRGHZ(void); +unsigned int DCL_SYSTICK_GetTick(void); +unsigned int SYSTICK_GetTimeStampUs(void); +typedef enum { + CHIP_IP_CLK_LOSC = 32000U, + CHIP_IP_CLK_CAN = 25000000U, + CHIP_IP_CLK_LS = 12500000U, + CHIP_IP_CLK_HS = 25000000U, +} CHIP_IpRate; +typedef enum { + CRG_IP_WITH_LS = 0x00, + CRG_IP_WITH_HS = 0x01, + CRG_IP_CAN = 0x02, + CRG_IP_ADC = 0x03, + CRG_IP_DAC = 0x04, + CRG_IP_EFC = 0x05, + CRG_IP_IWDG = 0x06, + CRG_IP_MAX_TYPE = 0x07, +} CHIP_CrgIpType; +typedef struct { + void *ipBaseAddr; + CHIP_CrgIpType type; + unsigned short regOffset; + unsigned char bitOffset; +} CHIP_CrgIpMatchInfo; +unsigned int CHIP_GetIpFreqHz(const void *ipBaseAddr); +CHIP_CrgIpMatchInfo *GetCrgIpMatchInfo(const void *baseAddr); +extern unsigned int HAL_CRG_GetIpFreq(const void *baseAddress); +void AssertErrorLog(char *file, unsigned int line); +typedef enum { + BASE_DEFINE_DELAY_SECS = 1, + BASE_DEFINE_DELAY_MILLISECS = 1000, + BASE_DEFINE_DELAY_MICROSECS = 1000000 +} BASE_DelayUnit; +unsigned int BASE_FUNC_GetCpuFreqHz(void); +void BASE_FUNC_Delay(unsigned int delay, BASE_DelayUnit units); +void BASE_FUNC_DelayUs(unsigned int us); +void BASE_FUNC_DelayMs(unsigned int ms); +void BASE_FUNC_DelaySeconds(unsigned int seconds); +typedef enum { + BASE_STATUS_UNLOCKED = 0, + BASE_STATUS_LOCKED = 1 +} BASE_LockStatus; +_Bool BASE_FUNC_SoftwareLock(unsigned int * const addr); +void BASE_FUNC_SoftwareUnLock(unsigned int * const addr); +_Bool BASE_FUNC_HardwareLock(CHIP_LockType const hwIndex); +void BASE_FUNC_HardwareUnLock(CHIP_LockType const hwIndex); +typedef struct { + unsigned int cnt; + float *buf; + unsigned int size; + unsigned int at; + unsigned int calNum; + float total; +} BASE_AverageHandle; +typedef BASE_FSM_Status (*FunType)(void); +typedef struct { + FunType funList[BASE_DEFINE_FSM_END + 1]; + BASE_FSM_Status nextFun; +} BASE_FSM_Handle; +unsigned int BASE_FUNC_GetTick(void); +unsigned int BASE_FUNC_FindArrayValue(const unsigned short *nums, unsigned int leng, unsigned int value); +unsigned char BASE_FUNC_CalcSumByte(const unsigned char *pt, unsigned int len); +unsigned short BASE_FUNC_CalcSumShort(unsigned char const * pt, unsigned int len); +BASE_StatusType BASE_FUNC_AverageInit(unsigned int index, float *buf, unsigned int size, unsigned int calNum); +float BASE_FUNC_GetSlipAverageVal(unsigned int index, float val); +void BASE_FUNC_AverageDeInit(unsigned int index); +void BASE_FSM_FunRegister(BASE_FSM_Status index, FunType funAddress); +void BASE_FSM_Run(unsigned int delayTime, BASE_DelayUnit delayUnit); +typedef struct { + int sin : 16; + int cos : 16; +} BASE_MathTypeSinCos; +typedef struct { + int q : 16; + int d : 16; +} BASE_MathTypeQD; +typedef struct { + int a : 16; + int b : 16; +} BASE_MathTypeAB; +typedef struct { + int alpha : 16; + int beta : 16; +} BASE_MathTypeAlphaBeta; +BASE_MathTypeSinCos BASE_MATH_GetSinCos(short angle); +float BASE_MATH_GetSin(float angle); +float BASE_MATH_GetCos(float angle); +float BASE_MATH_Sqrt(const float x); +float BASE_MATH_Pow(float x, int n); +BASE_MathTypeAlphaBeta BASE_MATH_Clarke(BASE_MathTypeAB input); +BASE_MathTypeQD BASE_MATH_Park(BASE_MathTypeAlphaBeta input, short theta); +BASE_MathTypeAlphaBeta BASE_MATH_RevPark(BASE_MathTypeQD input, short theta); +void BASE_FUNC_SoftReset(void); +static inline void IRQ_ClearN(unsigned int irqNum) +{ + asm volatile("fence"); + do { if (__builtin_constant_p(irqNum)) { asm volatile("li t0," "%0" : : "i"(irqNum)); } else { asm volatile("mv t0," "%0" : : "r"(irqNum)); } asm volatile("csrw %0, t0" :: "i"(0xBF0)); } while (0); +} +typedef void (* IRQ_PROC_FUNC)(void *arg); +typedef struct { + IRQ_PROC_FUNC pfnHandler; + void *param; +} IRQ_ARG_FUNC; +typedef struct { + unsigned int ra; + unsigned int t0; + unsigned int t1; + unsigned int t2; + unsigned int a0; + unsigned int a1; + unsigned int a2; + unsigned int a3; + unsigned int a4; + unsigned int a5; + unsigned int a6; + unsigned int a7; + unsigned int t3; + unsigned int t4; + unsigned int t5; + unsigned int t6; + unsigned int s0; + unsigned int s1; + unsigned int s2; + unsigned int s3; + unsigned int s4; + unsigned int s5; + unsigned int s6; + unsigned int s7; + unsigned int s8; + unsigned int s9; + unsigned int s10; + unsigned int s11; + unsigned int sp; + unsigned int gp; + unsigned int tp; + unsigned int mepc; + unsigned int mstatus; + unsigned int mtval; + unsigned int mcause; + unsigned int ccause; +} SyserrContext; +unsigned int IRQ_SetPriority(unsigned int irqNum, unsigned int priority); +unsigned int IRQ_GetPriority(unsigned int irqNum, unsigned int *priority); +void IRQ_Enable(void); +void IRQ_Disable(void); +unsigned int IRQ_EnableN(unsigned int irqNum); +unsigned int IRQ_DisableN(unsigned int irqNum); +void IRQ_Init(void); +unsigned int IRQ_Register(unsigned int irqNum, IRQ_PROC_FUNC func, void *arg); +unsigned int IRQ_Unregister(unsigned int irqNum); +unsigned int IRQ_ClearAll(void); +void SysErrNmiEntry(const SyserrContext *context); +void SysErrExcEntry(const SyserrContext *context); +void InterruptEntry(unsigned int irqNum); +void SysErrPrint(const SyserrContext *context); +typedef struct { +} UART_ExtendHandle; +typedef enum { + UART_WRITE_IT_FINISH = 0x00000000U, + UART_READ_IT_FINISH = 0x00000001U, + UART_WRITE_DMA_FINISH = 0x00000002U, + UART_READ_DMA_FINISH = 0x00000003U, + UART_TRNS_IT_ERROR = 0x00000004U, + UART_TRNS_DMA_ERROR = 0x00000005U +} UART_CallbackFun_Type; +typedef struct { + void (* WriteItFinishCallBack)(void *handle); + void (* ReadItFinishCallBack)(void *handle); + void (* WriteDmaFinishCallBack)(void *handle); + void (* ReadDmaFinishCallBack)(void *handle); + void (* TransmitItErrorCallBack)(void *handle); + void (* TransmitDmaErrorCallBack)(void *handle); +}UART_UserCallBack; +typedef enum { + UART_ERROR_FRAME = 0x00000080U, + UART_ERROR_PARITY = 0x00000100U, + UART_ERROR_BREAK = 0x00000200U, + UART_ERROR_OVERFLOW = 0x00000400U +} UART_Error_Type; +typedef enum { + UART_DATALENGTH_5BIT = 0x00000000U, + UART_DATALENGTH_6BIT = 0x00000001U, + UART_DATALENGTH_7BIT = 0x00000002U, + UART_DATALENGTH_8BIT = 0x00000003U +} UART_DataLength; +typedef enum { + UART_PARITY_ODD = 0x00000000U, + UART_PARITY_EVEN = 0x00000001U, + UART_PARITY_NONE = 0x00000002U +} UART_Parity_Mode; +typedef enum { + UART_STOPBITS_ONE = 0x00000000U, + UART_STOPBITS_TWO = 0x00000001U +} UART_StopBits; +typedef enum { + UART_MODE_BLOCKING = 0x00000000U, + UART_MODE_INTERRUPT = 0x00000001U, + UART_MODE_DMA = 0x00000002U, + UART_MODE_DISABLE = 0x00000003U +} UART_Transmit_Mode; +typedef enum { + UART_HW_FLOWCTR_DISABLE = 0x00000000U, + UART_HW_FLOWCTR_ENABLE = 0x00000001U +} UART_HW_FlowCtr; +typedef enum { + UART_STATE_NONE_INIT = 0x00000000U, + UART_STATE_READY = 0x00000001U, + UART_STATE_BUSY = 0x00000002U, + UART_STATE_BUSY_TX = 0x00000003U, + UART_STATE_BUSY_RX = 0x00000004U, +} UART_State_Type; +typedef enum { + UART_FIFOFULL_ONE_EIGHT = 0x00000000U, + UART_FIFOFULL_ONE_FOUR = 0x00000001U, + UART_FIFOFULL_ONE_TWO = 0x00000002U, + UART_FIFOFULL_THREE_FOUR = 0x00000003U, + UART_FIFOFULL_SEVEN_EIGHT = 0x00000004U, + UART_FIFOFULL_ONE_SIXTEEN = 0x00000005U, + UART_FIFOFULL_ONE_THIRTYTWO = 0x00000006U, + UART_FIFOFULL_FIVETEEN_SIXTEEN = 0x00000005U, + UART_FIFOFULL_THIRTYONE_THIRTYTWO = 0x00000006U +} UART_FIFO_Threshold; +typedef union { + unsigned int reg; + struct { + unsigned int data : 8; + unsigned int fe : 1; + unsigned int pe : 1; + unsigned int be : 1; + unsigned int oe : 1; + unsigned int reserved0 : 20; + } BIT; +} volatile UART_DR_REG; +typedef union { + unsigned int reg; + struct { + unsigned int fe : 1; + unsigned int pe : 1; + unsigned int be : 1; + unsigned int oe : 1; + unsigned int reserved0 : 28; + } BIT; +} volatile UART_RSR_REG; +typedef union { + unsigned int reg; + struct { + unsigned int cts : 1; + unsigned int reserved0 : 2; + unsigned int busy : 1; + unsigned int rxfe : 1; + unsigned int txff : 1; + unsigned int rxff : 1; + unsigned int txfe : 1; + unsigned int reserved1 : 24; + } BIT; +} volatile UART_FR_REG; +typedef union { + unsigned int reg; + struct { + unsigned int bauddivint : 16; + unsigned int reserved0 : 16; + } BIT; +} volatile UART_IBRD_REG; +typedef union { + unsigned int reg; + struct { + unsigned int bauddivfrac : 6; + unsigned int reserved0 : 26; + } BIT; +} volatile UART_FBRD_REG; +typedef union { + unsigned int reg; + struct { + unsigned int brk : 1; + unsigned int pen : 1; + unsigned int eps : 1; + unsigned int stp2 : 1; + unsigned int fen : 1; + unsigned int wlen : 2; + unsigned int sps : 1; + unsigned int reserved0 : 24; + } BIT; +} volatile UART_LCR_H_REG; +typedef union { + unsigned int reg; + struct { + unsigned int uarten : 1; + unsigned int reserved0 : 6; + unsigned int lbe : 1; + unsigned int txe : 1; + unsigned int rxe : 1; + unsigned int reserved1 : 1; + unsigned int rts : 1; + unsigned int reserved2 : 2; + unsigned int rtsen : 1; + unsigned int ctsen : 1; + unsigned int reserved3 : 16; + } BIT; +} volatile UART_CR_REG; +typedef union { + unsigned int reg; + struct { + unsigned int txiflsel : 3; + unsigned int rxiflsel : 3; + unsigned int reserved0 : 26; + } BIT; +} volatile UART_IFLS_REG; +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int ctsmim : 1; + unsigned int reserved1 : 2; + unsigned int rxim : 1; + unsigned int txim : 1; + unsigned int rtim : 1; + unsigned int feim : 1; + unsigned int peim : 1; + unsigned int beim : 1; + unsigned int oeim : 1; + unsigned int reserved2 : 21; + } BIT; +} volatile UART_IMSC_REG; +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int ctsmis : 1; + unsigned int reserved1 : 2; + unsigned int rxris : 1; + unsigned int txris : 1; + unsigned int rtris : 1; + unsigned int feris : 1; + unsigned int peris : 1; + unsigned int beris : 1; + unsigned int oeris : 1; + unsigned int reserved2 : 21; + } BIT; +} volatile UART_RIS_REG; +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int ctsmmis : 1; + unsigned int reserved1 : 2; + unsigned int rxmis : 1; + unsigned int txmis : 1; + unsigned int rtmis : 1; + unsigned int femis : 1; + unsigned int pemis : 1; + unsigned int bemis : 1; + unsigned int oemis : 1; + unsigned int reserved2 : 21; + } BIT; +} volatile UART_MIS_REG; +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int ctsmic : 1; + unsigned int reserved1 : 2; + unsigned int rxic : 1; + unsigned int txic : 1; + unsigned int rtic : 1; + unsigned int feic : 1; + unsigned int peic : 1; + unsigned int beic : 1; + unsigned int oeic : 1; + unsigned int reserved2 : 21; + } BIT; +} volatile UART_ICR_REG; +typedef union { + unsigned int reg; + struct { + unsigned int rxdmae : 1; + unsigned int txdmae : 1; + unsigned int dmaonerr : 1; + unsigned int rxlastsreq_en : 1; + unsigned int reserved0 : 28; + } BIT; +} volatile UART_DMACR_REG; +typedef struct { + UART_DR_REG UART_DR; + UART_RSR_REG UART_RSR; + unsigned char space0[16]; + UART_FR_REG UART_FR; + unsigned char space1[8]; + UART_IBRD_REG UART_IBRD; + UART_FBRD_REG UART_FBRD; + UART_LCR_H_REG UART_LCR_H; + UART_CR_REG UART_CR; + UART_IFLS_REG UART_IFLS; + UART_IMSC_REG UART_IMSC; + UART_RIS_REG UART_RIS; + UART_MIS_REG UART_MIS; + UART_ICR_REG UART_ICR; + UART_DMACR_REG UART_DMACR; +} volatile UART_RegStruct; +static inline _Bool IsUartDatalength(UART_DataLength datalength) +{ + return (datalength >= UART_DATALENGTH_5BIT) && (datalength <= UART_DATALENGTH_8BIT); +} +static inline _Bool IsUartStopbits(UART_StopBits stopbits) +{ + return (stopbits == UART_STOPBITS_ONE) || (stopbits == UART_STOPBITS_TWO); +} +static inline _Bool IsUartParitymode(UART_Parity_Mode paritymode) +{ + if ((paritymode == UART_PARITY_ODD) || + (paritymode == UART_PARITY_EVEN) || + (paritymode == UART_PARITY_NONE)) { + return 1; + } + return 0; +} +static inline _Bool IsUartTransmode(UART_Transmit_Mode transmode) +{ + if ((transmode == UART_MODE_BLOCKING) || + (transmode == UART_MODE_INTERRUPT) || + (transmode == UART_MODE_DMA) || + (transmode == UART_MODE_DISABLE)) { + return 1; + } + return 0; +} +static inline _Bool IsUartFIFOThreshold(UART_FIFO_Threshold fifoThreshold) +{ + return (fifoThreshold >= UART_FIFOFULL_ONE_EIGHT) && (fifoThreshold <= UART_FIFOFULL_ONE_THIRTYTWO); +} +static inline void DCL_UART_WriteData(UART_RegStruct * const uartx, unsigned char data) +{ + ((void)0U); + uartx->UART_DR.BIT.data = data; +} +static inline unsigned char DCL_UART_ReadData(const UART_RegStruct *uartx) +{ + ((void)0U); + return uartx->UART_DR.BIT.data; +} +static inline unsigned int DCL_UART_ReceiveStatus(const UART_RegStruct *uartx) +{ + ((void)0U); + return uartx->UART_DR.reg; +} +static inline void DCL_UART_WriteEnable(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_CR.BIT.txe = 0x01; +} +static inline void DCL_UART_WriteDisable(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_CR.BIT.txe = 0x00; +} +static inline void DCL_UART_ReadEnable(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_CR.BIT.rxe = 0x01; +} +static inline void DCL_UART_ReadDisable(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_CR.BIT.rxe = 0x00; +} +static inline void DCL_UART_EnableRequestTxSend(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_CR.BIT.rts = 0x01; +} +static inline void DCL_UART_DisableRequestTxSend(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_CR.BIT.rts = 0x00; +} +static inline void DCL_UART_Enable_HwFlowCtr(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_CR.BIT.ctsen = 0x01; + uartx->UART_CR.BIT.rtsen = 0x01; +} +static inline void DCL_UART_Disable_HwFlowCtr(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_CR.BIT.ctsen = 0x00; + uartx->UART_CR.BIT.rtsen = 0x00; +} +static inline void DCL_UART_EnableUart(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_CR.BIT.uarten = 0x01; +} +static inline void DCL_UART_DisableUart(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_CR.BIT.uarten = 0x00; +} +static inline void DCL_UART_EnableLoopBack(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_CR.BIT.lbe = 0x01; +} +static inline void DCL_UART_DisableLoopBack(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_CR.BIT.lbe = 0x00; +} +static inline void DCL_UART_DMA_WriteEnable(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_DMACR.BIT.txdmae = 0x01; +} +static inline void DCL_UART_DMA_WriteDisable(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_DMACR.BIT.txdmae = 0x00; +} +static inline void DCL_UART_DMA_ReadEnable(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_DMACR.BIT.rxdmae = 0x01; +} +static inline void DCL_UART_DMA_ReadDisable(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_DMACR.BIT.rxdmae = 0x00; +} +static inline void DCL_UART_SetDataLength(UART_RegStruct * const uartx, UART_DataLength dataLength) +{ + ((void)0U); + ((void)0U); + uartx->UART_LCR_H.BIT.wlen = dataLength; +} +static inline unsigned int DCL_UART_GetDataLength(const UART_RegStruct * uartx) +{ + ((void)0U); + return uartx->UART_LCR_H.BIT.wlen; +} +static inline void DCL_UART_SetParityOdd(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_LCR_H.BIT.eps = 0x00; + uartx->UART_LCR_H.BIT.pen = 0x01; +} +static inline void DCL_UART_SetParityEven(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_LCR_H.BIT.eps = 0x01; + uartx->UART_LCR_H.BIT.pen = 0x01; +} +static inline void DCL_UART_SetParityNone(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_LCR_H.BIT.pen = 0x00; +} +static inline unsigned int DCL_UART_GetParityCheck(const UART_RegStruct * uartx) +{ + ((void)0U); + unsigned int eps = uartx->UART_LCR_H.BIT.eps; + unsigned int pen = uartx->UART_LCR_H.BIT.pen; + if (eps == 0) { + return UART_PARITY_NONE; + } else if (pen == 0) { + return UART_PARITY_ODD; + } else { + return UART_PARITY_EVEN; + } +} +static inline void DCL_UART_SetStopBits(UART_RegStruct * const uartx, UART_StopBits bit) +{ + ((void)0U); + ((void)0U); + uartx->UART_LCR_H.BIT.stp2 = bit; +} +static inline _Bool DCL_UART_GetStopBits(const UART_RegStruct *uartx) +{ + ((void)0U); + return uartx->UART_LCR_H.BIT.stp2; +} +static inline void DCL_UART_DisableStickParity(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_LCR_H.BIT.sps = 0x00; +} +static inline void DCL_UART_EnableStickParity_Zero(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_LCR_H.BIT.pen = 0x01; + uartx->UART_LCR_H.BIT.eps = 0x01; + uartx->UART_LCR_H.BIT.sps = 0x01; +} +static inline void DCL_UART_EnableStickParity_One(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_LCR_H.BIT.pen = 0x01; + uartx->UART_LCR_H.BIT.eps = 0x00; + uartx->UART_LCR_H.BIT.sps = 0x01; +} +static inline void DCL_UART_EnableCTSInt(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_IMSC.BIT.ctsmim = 0x01; +} +static inline void DCL_UART_DisableCTSInt(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_IMSC.BIT.ctsmim = 0x00; +} +static inline void DCL_UART_SetLineControl(UART_RegStruct * const uartx, unsigned int controlValue) +{ + ((void)0U); + uartx->UART_LCR_H.reg = controlValue; +} +static inline void DCL_UART_EnableFIFO(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_LCR_H.BIT.fen = 0x01; +} +static inline void DCL_UART_DisableFIFO(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_LCR_H.BIT.fen = 0x00; +} +static inline void DCL_UART_EnableTxBreak(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_LCR_H.BIT.brk = 0x01; +} +static inline void DCL_UART_DisableTxBreak(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_LCR_H.BIT.brk = 0x00; +} +static inline void DCL_UART_ClearCTSInt(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_ICR.BIT.ctsmic = 0x01; + uartx->UART_IMSC.BIT.ctsmim = 0x00; +} +static inline void DCL_UART_ClearInterrupts(UART_RegStruct * const uartx, unsigned int clearInterruptBits) +{ + ((void)0U); + uartx->UART_ICR.reg = clearInterruptBits; +} +static inline void DCL_UART_ClearTxInt(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_ICR.BIT.txic = 0x01; +} +static inline void DCL_UART_ClearOverflowINT(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_ICR.BIT.oeic = 0x01; +} +static inline void DCL_UART_ClearBreakErrorINT(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_ICR.BIT.beic = 0x01; +} +static inline void DCL_UART_ClearParityINT(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_ICR.BIT.peic = 0x01; +} +static inline void DCL_UART_ClearFrameErrorINT(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_ICR.BIT.feic = 0x01; +} +static inline unsigned int DCL_UART_GetMISCTSIntStatus(const UART_RegStruct *uartx) +{ + ((void)0U); + return uartx->UART_MIS.BIT.ctsmmis; +} +static inline _Bool DCL_UART_GetMISErrorINTStatus(const UART_RegStruct * uartx) +{ + ((void)0U); + return uartx->UART_MIS.BIT.oemis; +} +static inline _Bool DCL_UART_GetMISBreakINTStatus(const UART_RegStruct * uartx) +{ + ((void)0U); + return uartx->UART_MIS.BIT.bemis; +} +static inline _Bool DCL_UART_GetMISParityINTStatus(const UART_RegStruct * uartx) +{ + ((void)0U); + return uartx->UART_MIS.BIT.pemis; +} +static inline _Bool DCL_UART_GetMISFrameErrorINTStatus(const UART_RegStruct * uartx) +{ + ((void)0U); + return uartx->UART_MIS.BIT.femis; +} +static inline _Bool DCL_UART_GetMISSendINTStatus(const UART_RegStruct * uartx) +{ + ((void)0U); + return uartx->UART_MIS.BIT.txmis; +} +static inline _Bool DCL_UART_GetMISReceiveINTStatus(const UART_RegStruct * uartx) +{ + ((void)0U); + return uartx->UART_MIS.BIT.rxmis; +} +static inline _Bool DCL_UART_GetMISReceiveTimeOutINTStatus(const UART_RegStruct * uartx) +{ + ((void)0U); + return uartx->UART_MIS.BIT.rtmis; +} +static inline _Bool DCL_UART_GetBusyIdleStatus(const UART_RegStruct * uartx) +{ + ((void)0U); + return uartx->UART_FR.BIT.busy; +} +static inline _Bool DCL_UART_GetTxFIFOFullStatus(const UART_RegStruct *uartx) +{ + ((void)0U); + return uartx->UART_FR.BIT.txff; +} +static inline _Bool DCL_UART_GetTxFIFOEmptyStatus(const UART_RegStruct *uartx) +{ + ((void)0U); + return uartx->UART_FR.BIT.txfe; +} +static inline _Bool DCL_UART_GetRxFIFOFullStatus(const UART_RegStruct *uartx) +{ + ((void)0U); + return uartx->UART_FR.BIT.rxff; +} +static inline _Bool DCL_UART_GetRxFIFOEmptyStatus(const UART_RegStruct *uartx) +{ + ((void)0U); + return uartx->UART_FR.BIT.rxfe; +} +static inline void DCL_UART_SetfractiondBaud(UART_RegStruct * const uartx, unsigned int fractionBaud) +{ + ((void)0U); + uartx->UART_FBRD.reg = fractionBaud; +} +static inline void DCL_UART_SetIntegerBaud(UART_RegStruct * const uartx, unsigned int IntegerBaud) +{ + ((void)0U); + uartx->UART_IBRD.reg = IntegerBaud; +} +static inline void DCL_UART_SetRxFIFOThreshold(UART_RegStruct * const uartx, UART_FIFO_Threshold thresholdValue) +{ + ((void)0U); + ((void)0U); + uartx->UART_IFLS.BIT.rxiflsel = thresholdValue; +} +static inline void DCL_UART_SetTxFIFOThreshold(UART_RegStruct * const uartx, UART_FIFO_Threshold thresholdValue) +{ + ((void)0U); + ((void)0U); + uartx->UART_IFLS.BIT.txiflsel = thresholdValue; +} +static inline void DCL_UART_MaskingInterrupts(UART_RegStruct * const uartx, unsigned int maskingInterruptBits) +{ + ((void)0U); + uartx->UART_IMSC.reg = maskingInterruptBits; +} +static inline void DCL_UART_EnableMSCTxInterrupt(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_IMSC.BIT.txim = 0x01; +} +static inline void DCL_UART_DisableMSCTxInterrupt(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_IMSC.BIT.txim = 0x00; +} +static inline void DCL_UART_DisableRxInt(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_IMSC.BIT.rxim = 0x00; +} +static inline void DCL_UART_EnableRxInt(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_IMSC.BIT.rxim = 0x01; +} +static inline void DCL_UART_EnableDMARxLastReq(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_DMACR.BIT.rxlastsreq_en = 0x01; +} +static inline void DCL_UART_DisableDMARxLastReq(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_DMACR.BIT.rxlastsreq_en = 0x00; +} +static inline void DCL_UART_EnableDMANoErrorINT(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_DMACR.BIT.dmaonerr = 0x01; +} +static inline void DCL_UART_DisableDMANoErrorINT(UART_RegStruct * const uartx) +{ + ((void)0U); + uartx->UART_DMACR.BIT.dmaonerr = 0x00; +} +typedef enum { + DMA_BURST_LENGTH_1 = 0x00000000U, + DMA_BURST_LENGTH_4 = 0x00000001U, + DMA_BURST_LENGTH_8 = 0x00000002U, + DMA_BURST_LENGTH_16 = 0x00000003U, + DMA_BURST_LENGTH_32 = 0x00000004U, + DMA_BURST_LENGTH_64 = 0x00000005U, + DMA_BURST_LENGTH_128 = 0x00000006U, + DMA_BURST_LENGTH_256 = 0x00000007U +} DMA_BurstLength; +typedef enum { + DMA_TRANSWIDTH_BYTE = 0x00000000U, + DMA_TRANSWIDTH_HALFWORD = 0x00000001U, + DMA_TRANSWIDTH_WORD = 0x00000002U +} DMA_TransmisWidth; +typedef enum { + DMA_CHANNEL_ZERO = 0x00000000U, + DMA_CHANNEL_ONE = 0x00000001U, + DMA_CHANNEL_TWO = 0x00000002U, + DMA_CHANNEL_THREE = 0x00000003U +} DMA_ChannelNum; +typedef enum { + DMA_CHANNEL_FINISH = 0x00000000U, + DMA_CHANNEL_ERROR = 0x00000001U +} DMA_CallbackFun_Type; +typedef enum { + DMA_MASTER1 = 0x00000000U, + DMA_MASTER2 = 0x00000001U +} DMA_Master; +typedef enum { + DMA_REQUEST_I2C_RX = 0x00000000U, + DMA_REQUEST_I2C_TX = 0x00000001U, + DMA_REQUEST_UART0_RX = 0x00000002U, + DMA_REQUEST_UART0_TX = 0x00000003U, + DMA_REQUEST_UART1_RX = 0x00000004U, + DMA_REQUEST_UART1_TX = 0x00000005U, + DMA_REQUEST_SPI_RX = 0x00000006U, + DMA_REQUEST_SPI_TX = 0x00000007U, + DMA_REQUEST_CAPM0 = 0x00000008U, + DMA_REQUEST_CAPM1 = 0x00000009U, + DMA_REQUEST_CAPM2 = 0x0000000AU, + DMA_REQUEST_ADC0 = 0x0000000BU, + DMA_REQUEST_ADC1 = 0x0000000CU, + DMA_REQUEST_ADC2 = 0x0000000DU, + DMA_REQUEST_TIMER0 = 0x0000000EU, + DMA_REQUEST_TIMER1 = 0x0000000FU, + DMA_REQUEST_UART2_RX = 0x00000010U, + DMA_REQUEST_UART2_TX = 0x00000011U, + DMA_REQUEST_APT8 = 0x00000012U, + DMA_REQUEST_APT0 = 0x00000013U, + DMA_REQUEST_APT1 = 0x00000014U, + DMA_REQUEST_APT2 = 0x00000015U, + DMA_REQUEST_APT3 = 0x00000016U, + DMA_REQUEST_APT4 = 0x00000017U, + DMA_REQUEST_APT5 = 0x00000018U, + DMA_REQUEST_APT6 = 0x00000019U, + DMA_REQUEST_APT7 = 0x0000001AU, + DMA_REQUEST_TIMER2 = 0x0000001BU, + DMA_REQUEST_TIMER3 = 0x0000001CU, + DMA_REQUEST_MEM = 0x0000001DU +} DMA_RequestLineNum; +typedef enum { + DMA_REQLINEVAL_0 = 0x00000000U, + DMA_REQLINEVAL_1 = 0x00000001U, + DMA_REQLINEVAL_2 = 0x00000002U, + DMA_REQLINEVAL_3 = 0x00000003U, + DMA_REQLINEVAL_4 = 0x00000004U, + DMA_REQLINEVAL_5 = 0x00000005U, + DMA_REQLINEVAL_6 = 0x00000006U, + DMA_REQLINEVAL_7 = 0x00000007U, + DMA_REQLINEVAL_8 = 0x00000008U, + DMA_REQLINEVAL_9 = 0x00000009U, + DMA_REQLINEVAL_10 = 0x0000000AU, + DMA_REQLINEVAL_11 = 0x0000000BU, + DMA_REQLINEVAL_12 = 0x0000000CU, + DMA_REQLINEVAL_13 = 0x0000000DU, + DMA_REQLINEVAL_14 = 0x0000000EU, + DMA_REQLINEVAL_15 = 0x0000000FU +} DMA_ReqLineVal; +typedef enum { + DMA_SYSCTRLSET_0 = 0x00000000U, + DMA_SYSCTRLSET_1 = 0x00000001U, + DMA_SYSCTRLSET_2 = 0x00000002U +} DMA_SysctrlSet; +typedef enum { + DMA_BYTEORDER_SMALLENDIAN = 0x00000000U, + DMA_BYTEORDER_BIGENDIAN = 0x00000001U +} DMA_ByteOrder; +typedef enum { + DMA_MEMORY_TO_MEMORY_BY_DMAC = 0x00000000U, + DMA_MEMORY_TO_PERIPH_BY_DMAC = 0x00000001U, + DMA_PERIPH_TO_MEMORY_BY_DMAC = 0x00000002U, + DMA_PERIPH_TO_PERIPH_BY_DMAC = 0x00000003U, + DMA_PERIPH_TO_PERIPH_BY_DES = 0x00000004U, + DMA_MEMORY_TO_PERIPH_BY_DES = 0x00000005U, + DMA_PERIPH_TO_MEMORY_BY_SRC = 0x00000006U, + DMA_PERIPH_TO_PERIPH_BY_SRC = 0x00000007U +} DMA_TransDirection; +typedef enum { + DMA_ADDR_UNALTERED = 0x00000000U, + DMA_ADDR_INCREASE = 0x00000001U +} DMA_AddrIncMode; +typedef struct _DMA_ExtendHandle { + DMA_ByteOrder srcByteOrder; + DMA_ByteOrder destByteOrder; +} DMA_ExtendHandle; +typedef struct { + struct { + void (* ChannelFinishCallBack)(void *handle); + void (* ChannelErrorCallBack)(void *handle); + } DMA_CallbackFuns[4]; +} DMA_UserCallBack; +typedef union { + unsigned int reg; + struct { + unsigned int ch0_int_stat : 1; + unsigned int ch1_int_stat : 1; + unsigned int ch2_int_stat : 1; + unsigned int ch3_int_stat : 1; + unsigned int reserved0 : 28; + } BIT; +} volatile DMAC_INT_STAT_REG; +typedef union { + unsigned int reg; + struct { + unsigned int ch0_int_tc_stat : 1; + unsigned int ch1_int_tc_stat : 1; + unsigned int ch2_int_tc_stat : 1; + unsigned int ch3_int_tc_stat : 1; + unsigned int reserved0 : 28; + } BIT; +} volatile DMAC_INT_TC_STAT_REG; +typedef union { + unsigned int reg; + struct { + unsigned int ch0_int_tc_clr : 1; + unsigned int ch1_int_tc_clr : 1; + unsigned int ch2_int_tc_clr : 1; + unsigned int ch3_int_tc_clr : 1; + unsigned int reserved1 : 28; + } BIT; +} volatile DMAC_INT_TC_CLR_REG; +typedef union { + unsigned int reg; + struct { + unsigned int ch0_int_err_stat : 1; + unsigned int ch1_int_err_stat : 1; + unsigned int ch2_int_err_stat : 1; + unsigned int ch3_int_err_stat : 1; + unsigned int reserved0 : 28; + } BIT; +} volatile DMAC_INT_ERR_STAT_REG; +typedef union { + unsigned int reg; + struct { + unsigned int ch0_int_err_clr : 1; + unsigned int ch1_int_err_clr : 1; + unsigned int ch2_int_err_clr : 1; + unsigned int ch3_int_err_clr : 1; + unsigned int reserved0 : 28; + } BIT; +} volatile DMAC_INT_ERR_CLR_REG; +typedef union { + unsigned int reg; + struct { + unsigned int ch0_raw_int_tc : 1; + unsigned int ch1_raw_int_tc : 1; + unsigned int ch2_raw_int_tc : 1; + unsigned int ch3_raw_int_tc : 1; + unsigned int reserved0 : 28; + } BIT; +} volatile DMAC_RAW_INT_TC_STAT_REG; +typedef union { + unsigned int reg; + struct { + unsigned int ch0_raw_int_err : 1; + unsigned int ch1_raw_int_err : 1; + unsigned int ch2_raw_int_err : 1; + unsigned int ch3_raw_int_err : 1; + unsigned int reserved0 : 28; + } BIT; +} volatile DMAC_RAW_INT_ERR_STAT_REG; +typedef union { + unsigned int reg; + struct { + unsigned int ch0_enabled : 1; + unsigned int ch1_enabled : 1; + unsigned int ch2_enabled : 1; + unsigned int ch3_enabled : 1; + unsigned int reserved0 : 28; + } BIT; +} volatile DMAC_ENABLED_CHNS_REG; +typedef union { + unsigned int reg; + struct { + unsigned int soft_breq : 16; + unsigned int reserved0 : 16; + } BIT; +} volatile DMAC_SOFT_BREQ_REG; +typedef union { + unsigned int reg; + struct { + unsigned int soft_sreq : 16; + unsigned int reserved0 : 16; + } BIT; +} volatile DMAC_SOFT_SREQ_REG; +typedef union { + unsigned int reg; + struct { + unsigned int soft_lbreq : 16; + unsigned int reserved0 : 16; + } BIT; +} volatile DMAC_SOFT_LBREQ_REG; +typedef union { + unsigned int reg; + struct { + unsigned int soft_lsreq : 16; + unsigned int reserved0 : 16; + } BIT; +} volatile DMAC_SOFT_LSREQ_REG; +typedef union { + unsigned int reg; + struct { + unsigned int dmac_enable : 1; + unsigned int m1_endianness : 1; + unsigned int m2_endianness : 1; + unsigned int reserved0 : 29; + } BIT; +} volatile DMAC_CONFIG_REG; +typedef union { + unsigned int reg; + struct { + unsigned int dmac_sync : 16; + unsigned int reserved0 : 16; + } BIT; +} volatile DMAC_SYNC_REG; +typedef union { + unsigned int reg; + struct { + unsigned int src_addr : 32; + } BIT; +} volatile DMAC_Cn_SRC_ADDR_REG; +typedef union { + unsigned int reg; + struct { + unsigned int dest_addr : 32; + } BIT; +} volatile DMAC_Cn_DEST_ADDR_REG; +typedef union { + unsigned int reg; + struct { + unsigned int ll_master : 1; + unsigned int reserved0 : 1; + unsigned int ll_item : 30; + } BIT; +} volatile DMAC_Cn_LLI_REG; +typedef union { + unsigned int reg; + struct { + unsigned int trans_size : 12; + unsigned int sbsize : 3; + unsigned int dbsize : 3; + unsigned int swidth : 3; + unsigned int dwidth : 3; + unsigned int src_select : 1; + unsigned int dest_select : 1; + unsigned int src_incr : 1; + unsigned int dest_incr : 1; + unsigned int reserved0 : 3; + unsigned int int_tc_enable : 1; + } BIT; +} volatile DMAC_Cn_CONTROL_REG; +typedef union { + unsigned int reg; + struct { + unsigned int ch_en : 1; + unsigned int src_periph : 4; + unsigned int reserved0 : 1; + unsigned int dest_periph : 4; + unsigned int reserved1 : 1; + unsigned int flow_ctrl : 3; + unsigned int err_int_msk : 1; + unsigned int tc_int_msk : 1; + unsigned int ch_lock : 1; + unsigned int ch_active : 1; + unsigned int ch_halt : 1; + unsigned int reserved2 : 13; + } BIT; +} volatile DMAC_Cn_CONFIG_REG; +typedef struct { + DMAC_INT_STAT_REG DMAC_INT_STAT; + DMAC_INT_TC_STAT_REG DMAC_INT_TC_STAT; + DMAC_INT_TC_CLR_REG DMAC_INT_TC_CLR; + DMAC_INT_ERR_STAT_REG DMAC_INT_ERR_STAT; + DMAC_INT_ERR_CLR_REG DMAC_INT_ERR_CLR; + DMAC_RAW_INT_TC_STAT_REG DMAC_RAW_INT_TC_STAT; + DMAC_RAW_INT_ERR_STAT_REG DMAC_RAW_INT_ERR_STAT; + DMAC_ENABLED_CHNS_REG DMAC_ENABLED_CHNS; + DMAC_SOFT_BREQ_REG DMAC_SOFT_BREQ; + DMAC_SOFT_SREQ_REG DMAC_SOFT_SREQ; + DMAC_SOFT_LBREQ_REG DMAC_SOFT_LBREQ; + DMAC_SOFT_LSREQ_REG DMAC_SOFT_LSREQ; + DMAC_CONFIG_REG DMAC_CONFIG; + DMAC_SYNC_REG DMAC_SYNC; + char space0[200]; + DMAC_Cn_SRC_ADDR_REG DMAC_C0_SRC_ADDR; + DMAC_Cn_DEST_ADDR_REG DMAC_C0_DEST_ADDR; + DMAC_Cn_LLI_REG DMAC_C0_LLI; + DMAC_Cn_CONTROL_REG DMAC_C0_CONTROL; + DMAC_Cn_CONFIG_REG DMAC_C0_CONFIG; + char space1[12]; + DMAC_Cn_SRC_ADDR_REG DMAC_C1_SRC_ADDR; + DMAC_Cn_DEST_ADDR_REG DMAC_C1_DEST_ADDR; + DMAC_Cn_LLI_REG DMAC_C1_LLI; + DMAC_Cn_CONTROL_REG DMAC_C1_CONTROL; + DMAC_Cn_CONFIG_REG DMAC_C1_CONFIG; + char space2[12]; + DMAC_Cn_SRC_ADDR_REG DMAC_C2_SRC_ADDR; + DMAC_Cn_DEST_ADDR_REG DMAC_C2_DEST_ADDR; + DMAC_Cn_LLI_REG DMAC_C2_LLI; + DMAC_Cn_CONTROL_REG DMAC_C2_CONTROL; + DMAC_Cn_CONFIG_REG DMAC_C2_CONFIG; + char space3[12]; + DMAC_Cn_SRC_ADDR_REG DMAC_C3_SRC_ADDR; + DMAC_Cn_DEST_ADDR_REG DMAC_C3_DEST_ADDR; + DMAC_Cn_LLI_REG DMAC_C3_LLI; + DMAC_Cn_CONTROL_REG DMAC_C3_CONTROL; + DMAC_Cn_CONFIG_REG DMAC_C3_CONFIG; +} volatile DMA_RegStruct; +typedef struct { + DMAC_Cn_SRC_ADDR_REG DMAC_Cn_SRC_ADDR; + DMAC_Cn_DEST_ADDR_REG DMAC_Cn_DEST_ADDR; + DMAC_Cn_LLI_REG DMAC_Cn_LLI; + DMAC_Cn_CONTROL_REG DMAC_Cn_CONTROL; + DMAC_Cn_CONFIG_REG DMAC_Cn_CONFIG; +} volatile DMA_ChannelRegStruct; +typedef struct _DMA_LinkList { + unsigned int srcAddr; + unsigned int destAddr; + struct _DMA_LinkList *lliNext; + DMAC_Cn_CONTROL_REG control; +} DMA_LinkList; +typedef struct { + unsigned int srcAddr; + unsigned int destAddr; + unsigned int srcIn; + unsigned int destIn; + unsigned int chnParam; + unsigned int totalSize; +} DMA_SplitParam; +typedef struct { + DMA_ReqLineVal reqLineVal; + DMA_SysctrlSet sysctrVal; + unsigned int shiftLeft; +} DMA_PeriphReq; +static inline _Bool IsDmaChannelNum(DMA_ChannelNum channel) +{ + if ((channel == DMA_CHANNEL_ZERO) || (channel == DMA_CHANNEL_ONE) || + (channel == DMA_CHANNEL_TWO) || (channel == DMA_CHANNEL_THREE)) { + return 1; + } + return 0; +} +static inline _Bool IsDmaWidth(DMA_TransmisWidth width) +{ + if ((width == DMA_TRANSWIDTH_BYTE) || + (width == DMA_TRANSWIDTH_HALFWORD) || + (width == DMA_TRANSWIDTH_WORD)) { + return 1; + } + return 0; +} +static inline _Bool IsDmaBurstLength(DMA_BurstLength burstLength) +{ + if ((burstLength == DMA_BURST_LENGTH_1) || (burstLength == DMA_BURST_LENGTH_4) || + (burstLength == DMA_BURST_LENGTH_8) || (burstLength == DMA_BURST_LENGTH_16) || + (burstLength == DMA_BURST_LENGTH_32) || (burstLength == DMA_BURST_LENGTH_64) || + (burstLength == DMA_BURST_LENGTH_128) || (burstLength == DMA_BURST_LENGTH_256)) { + return 1; + } + return 0; +} +static inline _Bool IsDmaByteOrder(DMA_ByteOrder byteOrder) +{ + return (byteOrder == DMA_BYTEORDER_SMALLENDIAN) || (byteOrder == DMA_BYTEORDER_BIGENDIAN); +} +static inline _Bool IsDmaAddrMode(DMA_AddrIncMode addrMode) +{ + return (addrMode == DMA_ADDR_UNALTERED) || (addrMode == DMA_ADDR_INCREASE); +} +static inline _Bool IsDmaDirection(DMA_TransDirection direction) +{ + if ((direction == DMA_MEMORY_TO_MEMORY_BY_DMAC) || (direction == DMA_MEMORY_TO_PERIPH_BY_DMAC) || + (direction == DMA_PERIPH_TO_MEMORY_BY_DMAC) || (direction == DMA_PERIPH_TO_PERIPH_BY_DMAC) || + (direction == DMA_PERIPH_TO_PERIPH_BY_DES) || (direction == DMA_MEMORY_TO_PERIPH_BY_DES) || + (direction == DMA_PERIPH_TO_MEMORY_BY_SRC) || (direction == DMA_PERIPH_TO_PERIPH_BY_SRC)) { + return 1; + } + return 0; +} +static inline _Bool IsDmaReqPeriph(DMA_RequestLineNum reqPeriph) +{ + return (reqPeriph >= DMA_REQUEST_I2C_RX) && (reqPeriph <= DMA_REQUEST_MEM); +} +static inline _Bool IsDmaValidAddress(unsigned long long address) +{ + return (address >= 0x4000000 && address <= 0x4003FFF) || (address >= 0x10000000 && address <= 0x1FFFFFFF); +} +static inline _Bool IsDmaMaster(DMA_Master master) +{ + return (master == DMA_MASTER1) || (master == DMA_MASTER2); +} +static inline void DCL_DMA_SetMast1ByteOrder(DMA_RegStruct * const dmax, DMA_ByteOrder byteOrder) +{ + ((void)0U); + ((void)0U); + dmax->DMAC_CONFIG.BIT.m1_endianness = byteOrder; +} +static inline void DCL_DMA_SetMast2ByteOrder(DMA_RegStruct * const dmax, DMA_ByteOrder byteOrder) +{ + ((void)0U); + ((void)0U); + dmax->DMAC_CONFIG.BIT.m2_endianness = byteOrder; +} +static inline void DCL_DMA_SetDirection(DMA_ChannelRegStruct * const dmaChannelx, DMA_TransDirection direction) +{ + ((void)0U); + ((void)0U); + dmaChannelx->DMAC_Cn_CONFIG.BIT.flow_ctrl = direction; +} +static inline void DCL_DMA_SetSrcAddr(DMA_ChannelRegStruct * const dmaChannelx, unsigned int srcAddr) +{ + ((void)0U); + ((void)0U); + dmaChannelx->DMAC_Cn_SRC_ADDR.BIT.src_addr = srcAddr; +} +static inline void DCL_DMA_SetDestAddr(DMA_ChannelRegStruct * const dmaChannelx, unsigned int destAddr) +{ + ((void)0U); + ((void)0U); + dmaChannelx->DMAC_Cn_DEST_ADDR.BIT.dest_addr = destAddr; +} +static inline void DCL_DMA_SetSrcAddrMode(DMA_ChannelRegStruct * const dmaChannelx, DMA_AddrIncMode srcAddrInc) +{ + ((void)0U); + ((void)0U); + dmaChannelx->DMAC_Cn_CONTROL.BIT.src_incr = srcAddrInc; +} +static inline void DCL_DMA_SetDestAddrMode(DMA_ChannelRegStruct * const dmaChannelx, DMA_AddrIncMode destAddrInc) +{ + ((void)0U); + ((void)0U); + dmaChannelx->DMAC_Cn_CONTROL.BIT.dest_incr = destAddrInc; +} +static inline void DCL_DMA_SetSrcWidth(DMA_ChannelRegStruct * const dmaChannelx, DMA_TransmisWidth srcWidth) +{ + ((void)0U); + ((void)0U); + dmaChannelx->DMAC_Cn_CONTROL.BIT.swidth = srcWidth; +} +static inline void DCL_DMA_SetDestWidth(DMA_ChannelRegStruct * const dmaChannelx, DMA_TransmisWidth destWidth) +{ + ((void)0U); + ((void)0U); + dmaChannelx->DMAC_Cn_CONTROL.BIT.dwidth = destWidth; +} +static inline void DCL_DMA_SetSrcBurst(DMA_ChannelRegStruct * const dmaChannelx, DMA_BurstLength srcBurst) +{ + ((void)0U); + ((void)0U); + dmaChannelx->DMAC_Cn_CONTROL.BIT.sbsize = srcBurst; +} +static inline void DCL_DMA_SetDestBurst(DMA_ChannelRegStruct * const dmaChannelx, DMA_BurstLength destBurst) +{ + ((void)0U); + ((void)0U); + dmaChannelx->DMAC_Cn_CONTROL.BIT.dbsize = destBurst; +} +static inline void DCL_DMA_SetTransferSize(DMA_ChannelRegStruct * const dmaChannelx, unsigned int dataLength) +{ + ((void)0U); + ((void)0U); + dmaChannelx->DMAC_Cn_CONTROL.BIT.trans_size = dataLength; +} +static inline void DCL_DMA_EnableIT(DMA_ChannelRegStruct * const dmaChannelx) +{ + ((void)0U); + dmaChannelx->DMAC_Cn_CONFIG.BIT.err_int_msk = 0x01; + dmaChannelx->DMAC_Cn_CONFIG.BIT.tc_int_msk = 0x01; +} +static inline void DCL_DMA_DisableIT(DMA_ChannelRegStruct * const dmaChannelx) +{ + ((void)0U); + dmaChannelx->DMAC_Cn_CONFIG.BIT.err_int_msk = 0x00; + dmaChannelx->DMAC_Cn_CONFIG.BIT.tc_int_msk = 0x00; +} +static inline void DCL_DMA_EnableChannel(DMA_ChannelRegStruct * const dmaChannelx) +{ + ((void)0U); + dmaChannelx->DMAC_Cn_CONFIG.BIT.ch_en = 0x01; +} +static inline void DCL_DMA_DisableChannel(DMA_ChannelRegStruct * const dmaChannelx) +{ + ((void)0U); + dmaChannelx->DMAC_Cn_CONFIG.BIT.ch_en = 0x00; +} +static inline void DCL_DMA_EnableDMAController(DMA_RegStruct * const dmax) +{ + ((void)0U); + dmax->DMAC_CONFIG.BIT.dmac_enable = 0x01; +} +static inline void DCL_DMA_DisableDMAController(DMA_RegStruct * const dmax) +{ + ((void)0U); + dmax->DMAC_CONFIG.BIT.dmac_enable = 0x00; +} +static inline void DCL_DMA_ClearTransferCompleteInt(DMA_RegStruct * const dmax, DMA_ChannelNum channel) +{ + ((void)0U); + ((void)0U); + dmax->DMAC_INT_TC_CLR.reg |= (1U << (unsigned int)channel); +} +static inline void DCL_DMA_ClearTransferErrorInt(DMA_RegStruct * const dmax, DMA_ChannelNum channel) +{ + ((void)0U); + ((void)0U); + dmax->DMAC_INT_ERR_CLR.reg |= (1U << (unsigned int)channel); +} +static inline void DCL_DMA_EnableRequestSync(DMA_RegStruct * const dmax) +{ + ((void)0U); + dmax->DMAC_SYNC.reg = 0x00; +} +static inline void DCL_DMA_DisableRequestSync(DMA_RegStruct * const dmax) +{ + ((void)0U); + dmax->DMAC_SYNC.reg = 0xFF; +} +static inline void DCL_DMA_ClearChannalParam(DMA_ChannelRegStruct * const dmaChannelx) +{ + ((void)0U); + dmaChannelx->DMAC_Cn_CONFIG.reg = 0x00; +} +static inline void DCL_DMA_SetSrcMasterChannal(DMA_ChannelRegStruct * const dmaChannelx, DMA_Master master) +{ + ((void)0U); + ((void)0U); + dmaChannelx->DMAC_Cn_CONTROL.BIT.src_select = master; +} +static inline void DCL_DMA_SetDestMasterChannal(DMA_ChannelRegStruct * const dmaChannelx, DMA_Master master) +{ + ((void)0U); + ((void)0U); + dmaChannelx->DMAC_Cn_CONTROL.BIT.dest_select = master; +} +static inline void DCL_DMA_ChannalEnableInt(DMA_ChannelRegStruct * const dmaChannelx) +{ + ((void)0U); + dmaChannelx->DMAC_Cn_CONTROL.BIT.int_tc_enable = 0x01; +} +static inline void DCL_DMA_ChannalDisableInt(DMA_ChannelRegStruct * const dmaChannelx) +{ + ((void)0U); + dmaChannelx->DMAC_Cn_CONTROL.BIT.int_tc_enable = 0x00; +} +static inline unsigned int DCL_DMA_GetChannelState(DMA_RegStruct * const dmax, DMA_ChannelNum channel) +{ + ((void)0U); + ((void)0U); + unsigned int val = dmax->DMAC_ENABLED_CHNS.reg; + unsigned int ret = (val & (1U << channel)); + return ret; +} +static inline unsigned int DCL_DMA_GetIntState(DMA_RegStruct * const dmax, DMA_ChannelNum channel) +{ + ((void)0U); + ((void)0U); + unsigned int val = dmax->DMAC_INT_STAT.reg; + unsigned int ret = (val & (1U << channel)); + return ret; +} +static inline unsigned int DCL_DMA_GetIntFinsihState(DMA_RegStruct * const dmax) +{ + ((void)0U); + return dmax->DMAC_INT_TC_STAT.reg; +} +static inline unsigned int DCL_DMA_GetIntErrorState(DMA_RegStruct * const dmax) +{ + ((void)0U); + return dmax->DMAC_INT_ERR_STAT.reg; +} +static inline void DCL_DMA_SetListNextNode(DMA_ChannelRegStruct * const dmaChannelx, unsigned int value) +{ + ((void)0U); + ((void)0U); + dmaChannelx->DMAC_Cn_LLI.reg = value; +} +static inline void DCL_DMA_HaltChannelRequest(DMA_ChannelRegStruct * const dmaChannelx) +{ + ((void)0U); + dmaChannelx->DMAC_Cn_CONFIG.BIT.ch_halt = 0x01; +} +static inline void DCL_DMA_AllowChannelRequest(DMA_ChannelRegStruct * const dmaChannelx) +{ + ((void)0U); + dmaChannelx->DMAC_Cn_CONFIG.BIT.ch_halt = 0x00; +} +static inline unsigned int DCL_DMA_GetFifoState(DMA_ChannelRegStruct * const dmaChannelx) +{ + ((void)0U); + return dmaChannelx->DMAC_Cn_CONFIG.BIT.ch_active; +} +typedef struct _DMA_Handle { + DMA_RegStruct *baseAddress; + struct { + DMA_ChannelRegStruct *channelAddr; + DMA_TransDirection direction; + DMA_RequestLineNum srcPeriph; + DMA_RequestLineNum destPeriph; + DMA_AddrIncMode srcAddrInc; + DMA_AddrIncMode destAddrInc; + DMA_BurstLength srcBurst; + DMA_BurstLength destBurst; + DMA_TransmisWidth srcWidth; + DMA_TransmisWidth destWidth; + void *pHandle; + unsigned int srcAddr; + unsigned int destAddr; + unsigned int controlVal; + unsigned int configVal; + } DMA_Channels[4]; + DMA_UserCallBack userCallBack; + DMA_ExtendHandle handleEx; +} DMA_Handle; +typedef struct { + DMA_RequestLineNum srcPeriph; + DMA_RequestLineNum destPeriph; + DMA_TransDirection direction; + DMA_AddrIncMode srcAddrInc; + DMA_AddrIncMode destAddrInc; + DMA_BurstLength srcBurst; + DMA_BurstLength destBurst; + DMA_TransmisWidth srcWidth; + DMA_TransmisWidth destWidth; + void *pHandle; +} DMA_ChannelParam; +typedef void (* DMA_CallbackType)(void *handle); +BASE_StatusType HAL_DMA_Init(DMA_Handle *dmaHandle); +BASE_StatusType HAL_DMA_Deinit(DMA_Handle *dmaHandle); +BASE_StatusType HAL_DMA_Start(DMA_Handle *dmaHandle, unsigned int srcAddr, + unsigned int destAddr, unsigned int dataLength, unsigned int channel); +BASE_StatusType HAL_DMA_StartIT(DMA_Handle *dmaHandle, unsigned int srcAddr, + unsigned int destAddr, unsigned int dataLength, unsigned int channel); +BASE_StatusType HAL_DMA_StopChannel(DMA_Handle *dmaHandle, unsigned int channel); +BASE_StatusType HAL_DMA_GetChannelState(DMA_Handle *dmaHandle, unsigned int channel); +BASE_StatusType HAL_DMA_InitChannel(DMA_Handle *dmaHandle, DMA_ChannelParam *channelParam, unsigned int channel); +void HAL_DMA_IrqHandlerTc(void *handle); +void HAL_DMA_IrqHandlerError(void *handle); +void HAL_DMA_RegisterCallback(DMA_Handle *dmaHandle, DMA_CallbackFun_Type typeID, + DMA_ChannelNum channel, DMA_CallbackType pCallback); +BASE_StatusType HAL_DMA_ListAddNode(DMA_LinkList *head, DMA_LinkList *newNode); +BASE_StatusType HAL_DMA_InitNewNode(DMA_LinkList *node, const DMA_ChannelParam *param, + unsigned int srcAddr, unsigned int destAddr, unsigned int tranSize); +BASE_StatusType HAL_DMA_StartListTransfer(DMA_Handle *dmaHandle, DMA_LinkList *head, unsigned int channel); +void HAL_DMA_QuickStart(DMA_Handle *dmaHandle, unsigned int channel); +typedef struct _UART_Handle { + UART_RegStruct *baseAddress; + unsigned int baudRate; + UART_DataLength dataLength; + UART_StopBits stopBits; + UART_Parity_Mode parity; + UART_Transmit_Mode txMode; + UART_Transmit_Mode rxMode; + volatile unsigned char *txbuff; + volatile unsigned char *rxbuff; + volatile unsigned int txBuffSize; + volatile unsigned int rxBuffSize; + _Bool fifoMode; + UART_FIFO_Threshold fifoTxThr; + UART_FIFO_Threshold fifoRxThr; + UART_HW_FlowCtr hwFlowCtr; + DMA_Handle *dmaHandle; + unsigned int uartDmaTxChn; + unsigned int uartDmaRxChn; + volatile UART_State_Type txState; + volatile UART_State_Type rxState; + UART_Error_Type errorType; + UART_UserCallBack userCallBack; + UART_ExtendHandle handleEx; +} UART_Handle; +typedef void (* UART_CallbackType)(void *handle); +BASE_StatusType HAL_UART_Init(UART_Handle *uartHandle); +BASE_StatusType HAL_UART_DeInit(UART_Handle *uartHandle); +UART_State_Type HAL_UART_GetState(UART_Handle *uartHandle); +BASE_StatusType HAL_UART_WriteBlocking(UART_Handle *uartHandle, unsigned char *srcData, + unsigned int dataLength, unsigned int blockingTime); +BASE_StatusType HAL_UART_WriteIT(UART_Handle *uartHandle, unsigned char *srcData, unsigned int dataLength); +BASE_StatusType HAL_UART_WriteDMA(UART_Handle *uartHandle, unsigned char *srcData, + unsigned int dataLength); +BASE_StatusType HAL_UART_ReadBlocking(UART_Handle *uartHandle, unsigned char *saveData, + unsigned int dataLength, unsigned int blockingTime); +BASE_StatusType HAL_UART_ReadIT(UART_Handle *uartHandle, unsigned char *saveData, unsigned int dataLength); +BASE_StatusType HAL_UART_ReadDMA(UART_Handle *uartHandle, unsigned char *saveData, + unsigned int dataLength); +BASE_StatusType HAL_UART_StopRead(UART_Handle *uartHandle); +BASE_StatusType HAL_UART_StopWrite(UART_Handle *uartHandle); +void HAL_UART_IrqHandler(void *handle); +BASE_StatusType HAL_UART_RegisterCallBack(UART_Handle *uartHandle, UART_CallbackFun_Type typeID, + UART_CallbackType pCallback); +BASE_StatusType HAL_UART_ReadDMAAndCyclicallyStored(UART_Handle *uartHandle, unsigned char *saveData, + DMA_LinkList *tempNode, unsigned int dataLength); +unsigned int HAL_UART_ReadDMAGetPos(UART_Handle *uartHandle); +int ConsoleGetQuery(void); +int ConsoleGetc(void); +int ConsolePuts(const char *str); +void ConsolePutc(const char c); +int UartPrintf(const char *format, ...); +void ConsoleInit(UART_Handle uart); +typedef enum { + FILE_ID_LOG_C = 2001, +} file_id_enum; +enum ExtLogLevel { + EXT_LOG_LEVEL_FATAL, + EXT_LOG_LEVEL_ERROR, + EXT_LOG_LEVEL_WARNING, + EXT_LOG_LEVEL_INFO, + EXT_LOG_LEVEL_DBG, + EXT_LOG_LEVEL_BUTT, +}; +enum ExtLogLevelToken { + FATAL, + ERR, + WARN, + INFO, + DBG, +}; +int ExtDrvLogOutBuf(enum ExtLogLevel level, enum ExtModule modId, unsigned int xmlId, + const unsigned int* logBuf, unsigned short logBufLen); +int ExtDrvLogOut0(enum ExtLogLevel level, enum ExtModule modId, unsigned int xmlId); +int ExtDrvLogOut1(enum ExtLogLevel level, enum ExtModule modId, unsigned int xmlId, unsigned int d0); +int ExtDrvLogOut2(enum ExtLogLevel level, enum ExtModule modId, unsigned int xmlId, unsigned int d0, unsigned int d1); +int ExtDrvLogOut3(enum ExtLogLevel level, enum ExtModule modId, unsigned int xmlId, unsigned int d0, unsigned int d1, + unsigned int d2); +int ExtDrvLogSetLogLevel(enum ExtModule modId, enum ExtLogLevel level); +int ExtDrvLogOutFmt(enum ExtLogLevel level, enum ExtModule id, const char *fmt, ...); +struct MemoryLog { + unsigned char enable; + unsigned char mmzBuf[1024]; + unsigned int writePos; + unsigned int logLen; +}; +struct SysLogCtx { + unsigned char init; + char **modStr; + enum ExtLogLevel logLevel[EXT_MODULE_BUTT]; + struct MemoryLog memLog; +}; +struct SysDebugSwitch { + unsigned char enable; + struct SysLogCtx logCtx; +}; +struct SysLogCtx *GetLogCtx(void); +void LogCtxInit(struct SysLogCtx *ctx); +void InitMemoryData(struct MemoryLog *memData); +struct SysDebugSwitch *GetDebugSwitch(void); +struct MemoryLog *GetMemoryData(void); +void DfxCmdRegister(void); +int CmdGetVersionInfo(void); +int ExtSetLogLevel(enum ExtModule id, enum ExtLogLevel logLevel); +typedef int wchar_t; +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); +int rand (void); +void srand (unsigned); +void *malloc (size_t); +void *calloc (size_t, size_t); +void *realloc (void *, size_t); +void free (void *); +void *aligned_alloc(size_t, size_t); +_Noreturn void abort (void); +int atexit (void (*) (void)); +_Noreturn void exit (int); +_Noreturn void _Exit (int); +int at_quick_exit (void (*) (void)); +_Noreturn void quick_exit (int); +char *getenv (const char *); +int system (const char *); +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); +void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); +int abs (int); +long labs (long); +long long llabs (long long); +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); +int mblen (const char *, size_t); +int mbtowc (wchar_t *restrict, const char *restrict, size_t); +int wctomb (char *, wchar_t); +size_t mbstowcs (wchar_t *restrict, const char *restrict, size_t); +size_t wcstombs (char *restrict, const wchar_t *restrict, size_t); +size_t __ctype_get_mb_cur_max(void); +int posix_memalign (void **, size_t, size_t); +int setenv (const char *, const char *, int); +int unsetenv (const char *); +int mkstemp (char *); +int mkostemp (char *, int); +char *mkdtemp (char *); +int getsubopt (char **, char *const *, char **); +int rand_r (unsigned *); +char *realpath (const char *restrict, char *restrict); +long int random (void); +void srandom (unsigned int); +char *initstate (unsigned int, char *, size_t); +char *setstate (char *); +int putenv (char *); +int posix_openpt (int); +int grantpt (int); +int unlockpt (int); +char *ptsname (int); +char *l64a (long); +long a64l (const char *); +void setkey (const char *); +double drand48 (void); +double erand48 (unsigned short [3]); +long int lrand48 (void); +long int nrand48 (unsigned short [3]); +long mrand48 (void); +long jrand48 (unsigned short [3]); +void srand48 (long); +unsigned short *seed48 (unsigned short [3]); +void lcong48 (unsigned short [7]); +void *alloca(size_t); +char *mktemp (char *); +int mkstemps (char *, int); +int mkostemps (char *, int, int); +void *valloc (size_t); +void *memalign(size_t, size_t); +int getloadavg(double *, int); +int clearenv(void); +void *reallocarray (void *, size_t, size_t); +void qsort_r (void *, size_t, size_t, int (*)(const void *, const void *, void *), void *); +typedef int ptrdiff_t; +typedef unsigned int size_t; +typedef int wchar_t; +typedef struct { + long long __max_align_ll __attribute__((__aligned__(__alignof__(long long)))); + long double __max_align_ld __attribute__((__aligned__(__alignof__(long double)))); +} max_align_t; +typedef int errno_t; +extern const char *GetHwSecureCVersion(unsigned short *verNumber); +extern errno_t memset_s(void *dest, size_t destMax, int c, size_t count); +extern errno_t memmove_s(void *dest, size_t destMax, const void *src, size_t count); +extern errno_t memcpy_s(void *dest, size_t destMax, const void *src, size_t count); +extern errno_t strcpy_s(char *strDest, size_t destMax, const char *strSrc); +extern errno_t strncpy_s(char *strDest, size_t destMax, const char *strSrc, size_t count); +extern errno_t strcat_s(char *strDest, size_t destMax, const char *strSrc); +extern errno_t strncat_s(char *strDest, size_t destMax, const char *strSrc, size_t count); +extern int vsprintf_s(char *strDest, size_t destMax, const char *format, + va_list argList) ; +extern int sprintf_s(char *strDest, size_t destMax, const char *format, ...) ; +extern int vsnprintf_s(char *strDest, size_t destMax, size_t count, const char *format, + va_list argList) ; +extern int snprintf_s(char *strDest, size_t destMax, size_t count, const char *format, + ...) ; +extern int vsnprintf_truncated_s(char *strDest, size_t destMax, const char *format, + va_list argList) ; +extern int snprintf_truncated_s(char *strDest, size_t destMax, + const char *format, ...) ; +extern int scanf_s(const char *format, ...); +extern int vscanf_s(const char *format, va_list argList); +extern int sscanf_s(const char *buffer, const char *format, ...); +extern int vsscanf_s(const char *buffer, const char *format, va_list argList); +extern int fscanf_s(FILE *stream, const char *format, ...); +extern int vfscanf_s(FILE *stream, const char *format, va_list argList); +extern char *strtok_s(char *strToken, const char *strDelimit, char **context); +extern char *gets_s(char *buffer, size_t destMax); +extern errno_t wmemcpy_s(wchar_t *dest, size_t destMax, const wchar_t *src, size_t count); +extern errno_t wmemmove_s(wchar_t *dest, size_t destMax, const wchar_t *src, size_t count); +extern errno_t wcscpy_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc); +extern errno_t wcsncpy_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc, size_t count); +extern errno_t wcscat_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc); +extern errno_t wcsncat_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc, size_t count); +extern wchar_t *wcstok_s(wchar_t *strToken, const wchar_t *strDelimit, wchar_t **context); +extern int vswprintf_s(wchar_t *strDest, size_t destMax, const wchar_t *format, va_list argList); +extern int swprintf_s(wchar_t *strDest, size_t destMax, const wchar_t *format, ...); +extern int fwscanf_s(FILE *stream, const wchar_t *format, ...); +extern int vfwscanf_s(FILE *stream, const wchar_t *format, va_list argList); +extern int wscanf_s(const wchar_t *format, ...); +extern int vwscanf_s(const wchar_t *format, va_list argList); +extern int swscanf_s(const wchar_t *buffer, const wchar_t *format, ...); +extern int vswscanf_s(const wchar_t *buffer, const wchar_t *format, va_list argList); +extern errno_t strncpy_error(char *strDest, size_t destMax, const char *strSrc, size_t count); +extern errno_t strcpy_error(char *strDest, size_t destMax, const char *strSrc); +extern errno_t memset_sOptAsm(void *dest, size_t destMax, int c, size_t count); +extern errno_t memset_sOptTc(void *dest, size_t destMax, int c, size_t count); +extern errno_t memcpy_sOptAsm(void *dest, size_t destMax, const void *src, size_t count); +extern errno_t memcpy_sOptTc(void *dest, size_t destMax, const void *src, size_t count); +static struct MemoryLog g_memoryLog = {0}; +char *moduleStr[EXT_MODULE_BUTT] = { + "app_main", + "app_console", + "app_chip", + "drv_base", + "drv_chips", + "drv_crg", + "drv_gpio", + "drv_i2c", + "drv_irq", + "drv_pinctrl", + "drv_timer", + "drv_uart", + "dfx", +}; +char *ExtLogLevel1[6] = { + "EXT_LOG_LEVEL_FATAL", + "EXT_LOG_LEVEL_ERROR", + "EXT_LOG_LEVEL_WARNING", + "EXT_LOG_LEVEL_INFO", + "EXT_LOG_LEVEL_DBG", + "EXT_LOG_LEVEL_BUTT", +}; +struct SysLogCtx g_logCtx = { 0 }; +struct SysLogCtx *GetLogCtx(void) +{ + return &g_logCtx; +} +static struct SysDebugSwitch g_debugSwitch = {.enable = 1}; +struct SysDebugSwitch *GetDebugSwitch(void) +{ + return &g_debugSwitch; +} +void InitMemoryData(struct MemoryLog *memData) +{ + memData->enable = 1; + memData->logLen = 0; + memData->writePos = 0; +} +struct MemoryLog *GetMemoryData(void) +{ + return &g_memoryLog; +} +void LogCtxInit(struct SysLogCtx *ctx) +{ + ctx->modStr = moduleStr; + for (unsigned char i = 0; i < EXT_MODULE_BUTT; i++) { + ctx->logLevel[i] = EXT_LOG_LEVEL_ERROR; + } + ctx->init = 1; +} +static void PutLogToMem(struct MemoryLog *memLog, const char *src, unsigned char cnt) +{ + unsigned char len = cnt; + if (cnt > 1024 - memLog->writePos) { + len = 1024 - memLog->writePos; + if (memcpy_s(memLog->mmzBuf + memLog->writePos, 1024 - memLog->writePos, src, len) != + EXT_SUCCESS) { + UartPrintf("put log to memory memcpy err\n"); + return; + } + memLog->writePos = 0; + src += len; + len = cnt - len; + } + if (memcpy_s(memLog->mmzBuf + memLog->writePos, 1024 - memLog->writePos, src, len) != EXT_SUCCESS) { + UartPrintf("put log to memory memcpy err\n"); + return; + } + memLog->writePos += len; + memLog->logLen += cnt; + if (memLog->logLen > 1024) { + memLog->logLen = 1024; + } +} +static int CountNumberLen(unsigned int num) +{ + int count = 0; + do { + count += 1; + num = num/10; + } while (num != 0); + return count; +} +static unsigned int IsLogOutBufLegal(enum ExtLogLevel level, struct SysDebugSwitch *debugSwitch, + enum ExtModule modId, struct SysLogCtx *ctx) +{ + if (level > EXT_LOG_LEVEL_BUTT || modId > EXT_MODULE_BUTT) + return EXT_FAILURE; + if (((!debugSwitch->enable) && (level != EXT_LOG_LEVEL_ERROR)) || (level > ctx->logLevel[modId])) { + return EXT_SUCCESS; + } + return EXT_FAILURE; +} +int ExtDrvLogOutBuf(enum ExtLogLevel level, enum ExtModule modId, unsigned int id, const unsigned int* logBuf, + unsigned short logBufLen) +{ + if (logBuf == ((void *)0)) + return EXT_FAILURE; + char buf[512] = { 0 }; + int cnt = 0; + int len = 0; + int count = 0; + struct SysLogCtx *ctx = GetLogCtx(); + struct SysDebugSwitch *debugSwitch = GetDebugSwitch(); + if (!ctx->init) { LogCtxInit(ctx); } + if (!(IsLogOutBufLegal(level, debugSwitch, modId, ctx))) { return EXT_SUCCESS; } + cnt = sprintf_s(buf, 512, "%u", id); + if (cnt < 0) { + UartPrintf("sprintf err\n"); + return EXT_FAILURE; + } + len += cnt; + unsigned short i = 0; + for (; i < logBufLen; ++i) { + count = CountNumberLen(logBuf[i]); + if ((count + len + 1) >= 512) { return EXT_FAILURE; } + cnt = sprintf_s(buf + len, 512 - len, " %u", logBuf[i]); + if (cnt < 0) { + UartPrintf("sprintf err\n"); + return EXT_FAILURE; + } + len += cnt; + } + cnt = sprintf_s(buf + len, 512 - len, "\n"); + len += cnt; + if (cnt < 0) { + UartPrintf("sprintf err\n"); + return EXT_FAILURE; + } else if (!ctx->memLog.enable) { + UartPrintf("%s", buf); + return EXT_SUCCESS; + } + PutLogToMem(&ctx->memLog, buf, len); + return EXT_SUCCESS; +} +int CmdGetVersionInfo(void) +{ + int versionInfo; + versionInfo = (*(volatile unsigned int *)(0x4000000)); + { _PRIM_ST_, _PRIM_PRI_ = 1, _PRIM_MSG_ = "version info is : %x\n", _PRIM_LINE_ = 266, _PRIM_FILE_ID_ = 2001, _PRIM_MOD_ID_ = 12, _PRIM_END_ }; + return EXT_SUCCESS; +} +static int DealLogBuf(int len, enum ExtLogLevel level, enum ExtModule modId, const char buf[]) +{ + struct SysLogCtx *ctx = GetLogCtx(); + struct SysDebugSwitch *debugSwitch = GetDebugSwitch(); + if (!debugSwitch->enable) { + if (level != EXT_LOG_LEVEL_ERROR) { + return EXT_SUCCESS; + } + } + if (!ctx->init) { LogCtxInit(ctx); } + if (level > ctx->logLevel[modId]) { return EXT_SUCCESS; } + if (len < 0) { + UartPrintf("sprintf err\n"); + return EXT_FAILURE; + } + if (!ctx->memLog.enable) { + UartPrintf("%s", buf); + return EXT_SUCCESS; + } + PutLogToMem(&ctx->memLog, buf, len); + return EXT_SUCCESS; +} +int ExtDrvLogOut0(enum ExtLogLevel level, enum ExtModule modId, unsigned int id) +{ + if (level > EXT_LOG_LEVEL_BUTT || modId > EXT_MODULE_BUTT) + return EXT_FAILURE; + char buf[512] = { 0 }; + int len = 0; + len = sprintf_s(buf, 512, "%u\n", id); + if (len < 0) { + UartPrintf("sprintf err\n"); + return EXT_FAILURE; + } + return (DealLogBuf(len, level, modId, buf)); +} +int ExtDrvLogOut1(enum ExtLogLevel level, enum ExtModule modId, unsigned int id, unsigned int d0) +{ + if (level > EXT_LOG_LEVEL_BUTT || modId > EXT_MODULE_BUTT) + return EXT_FAILURE; + char buf[512] = { 0 }; + int len = 0; + len = sprintf_s(buf, 512, "%u %u\n", id, d0); + if (len < 0) { + UartPrintf("sprintf err\n"); + return EXT_FAILURE; + } + return (DealLogBuf(len, level, modId, buf)); +} +int ExtDrvLogOut2(enum ExtLogLevel level, enum ExtModule modId, unsigned int id, unsigned int d0, unsigned int d1) +{ + if (level > EXT_LOG_LEVEL_BUTT || modId > EXT_MODULE_BUTT) + return EXT_FAILURE; + char buf[512] = { 0 }; + int len = 0; + len = sprintf_s(buf, 512, "%u %u %u\n", id, d0, d1); + if (len < 0) { + UartPrintf("sprintf err\n"); + return EXT_FAILURE; + } + return (DealLogBuf(len, level, modId, buf)); +} +int ExtDrvLogOut3(enum ExtLogLevel level, enum ExtModule modId, unsigned int id, unsigned int d0, unsigned int d1, + unsigned int d2) +{ + if (level > EXT_LOG_LEVEL_BUTT || modId > EXT_MODULE_BUTT) + return EXT_FAILURE; + char buf[512] = { 0 }; + int len = 0; + len = sprintf_s(buf, 512, "%u %u %u %u\n", id, d0, d1, d2); + if (len < 0) { + UartPrintf("sprintf err\n"); + return EXT_FAILURE; + } + return (DealLogBuf(len, level, modId, buf)); +} +int ExtDrvLogSetLogLevel(enum ExtModule id, enum ExtLogLevel level) +{ + if (level >= EXT_LOG_LEVEL_BUTT || id >= EXT_MODULE_BUTT) { + UartPrintf("module or level unsupport\n"); + return EXT_FAILURE; + } + struct SysLogCtx *ctx = GetLogCtx(); + if (!ctx->init) { + LogCtxInit(ctx); + } + ctx->logLevel[id] = level; + return EXT_SUCCESS; +} +int ExtDrvLogOutFmt(enum ExtLogLevel level, enum ExtModule id, const char *fmt, ...) +{ + va_list args; + struct SysDebugSwitch *debugSwitch = GetDebugSwitch(); + if ((!debugSwitch->enable) && (level != EXT_LOG_LEVEL_ERROR)) { + return EXT_SUCCESS; + } + if (level >= EXT_LOG_LEVEL_BUTT || id >= EXT_MODULE_BUTT) { + UartPrintf("level %d or module %d err\n", level, id); + return EXT_FAILURE; + } + char *tag = "FEWIDB"; + struct SysLogCtx *ctx = GetLogCtx(); + if (!ctx->init) { + LogCtxInit(ctx); + } + if (level > ctx->logLevel[id]) { + return EXT_SUCCESS; + } + UartPrintf("%c-%s:", *(tag + level), ctx->modStr[id]); + __builtin_va_start(args,fmt); + UartPrintf(fmt, args); + __builtin_va_end(args); + UartPrintf("\r\n"); + return EXT_SUCCESS; +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/ide_entry.py b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/ide_entry.py new file mode 100644 index 00000000..163938d9 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/ide_entry.py @@ -0,0 +1,204 @@ +# !/usr/bin/env python +# -*- coding: utf-8 -*- + +# @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +# following disclaimer in the documentation and/or other materials provided with the distribution. +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote +# products derived from this software without specific prior written permission. +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# ide_entry.py Function implementation: ide build entry file, which is used to +# copy code and invoke build compilation scripts. + +import os +import sys +import stat +import pathlib +import glob +import tarfile +import zipfile +import platform +import shutil +from configparser import ConfigParser +import shlex +import subprocess +from build import remove_readonly + +from build_gn import read_json_file + + +def copy_code(product, copy_path): + ''' + Function description: Code copy phase for CI build work. + ''' + + # Instantiation parameter check. + if not isinstance(copy_path, str): + raise TypeError("copy_path in para type error {}".format( + type(copy_path))) + if not isinstance(product, str): + raise TypeError("product in para type error {}".format( + type(product))) + + if pathlib.Path(copy_path).exists(): + shutil.rmtree(os.path.realpath(copy_path), onerror=remove_readonly) + + copy_abspath = pathlib.Path(copy_path).resolve() + copyjson_path = pathlib.Path.cwd()\ + .joinpath('chip', "{}".format(product), 'codecopy.json') + copyjson_content = read_json_file(copyjson_path) + for module_path in copyjson_content['modules']: + if pathlib.Path(module_path).is_dir(): + traversal_path(copy_abspath, module_path) + elif pathlib.Path(module_path).is_file(): + parent_path = pathlib.Path(module_path).parent + copy_parent_path = pathlib.Path(copy_abspath).joinpath(parent_path) + if not copy_parent_path.exists(): + os.makedirs(copy_parent_path) + shutil.copy(module_path, copy_parent_path) + + +def traversal_path(copy_path, module_path): + ''' + Function description: Traverse the path and then perform the create + and copy work. + ''' + + ipbefore_list = [] + ipafter_list = [] + cur_sys = platform.system() + + for (dirpath, _, filenames) in os.walk(module_path): + if cur_sys == 'Windows': + ipbefore_list = dirpath.split('\\') + elif cur_sys == 'Linux': + ipbefore_list = dirpath.split('/') + ipafter_list = [] + for ipdir in ipbefore_list: + if ipdir.startswith('v') and '.' in ipdir: + continue + ipafter_list.append(ipdir) + dirprocesspath = '/'.join(ipafter_list) + dest_path = pathlib.Path(copy_path).joinpath(dirprocesspath) + if not dest_path.exists(): + os.makedirs(dest_path) + for file in filenames: + if 'entry.py' in file or 'trustlist.json' in file: + continue + source_file = pathlib.Path(dirpath).joinpath(file) + shutil.copy(source_file, dest_path) + + +def untar(filename): + ''' + Function description: Decompress the tar or tar.gz file. + ''' + + tar = tarfile.open(filename) + tar.extractall(pathlib.Path()) + tar.close() + + +def unzip(filename): + ''' + Function description: Decompress the zip file. + ''' + + max_size = 1 * 1024 * 1024 * 500 + cur_size = 0 + + zip_file = zipfile.ZipFile(filename) + filename = filename.split('.')[0] + if not os.path.isdir(filename): + os.mkdir(filename) + for names in zip_file.infolist(): + cur_size += names.file_size + if cur_size > max_size: + break + zip_file.extract(names.filename, filename) + zip_file.close() + + +def del_decfile(tools_path): + ''' + Function description: Delete the decompressed files. + ''' + + file_lst = glob.glob(tools_path + '/*') + filename_lst = [os.path.basename(i) for i in file_lst if '.' not in os.path.basename(i)] + for filename in filename_lst: + shutil.rmtree(filename, onerror=remove_readonly) + + +def un_alltools(tools_path): + ''' + Function description: Decompress all compilation tools. + ''' + + # Judgment system. + cur_sys = platform.system() + path = str(pathlib.Path(tools_path).joinpath(cur_sys)) + cur_path = os.getcwd() + + os.chdir(path) + del_decfile(path) + + # Decompress all compressed files. + file_lst = glob.glob(path + '/*') + filename_lst = [os.path.basename(i) for i in file_lst] + for filename in filename_lst: + if '.' in filename: + suffix = filename.split('.')[-1] + if suffix == 'gz' or suffix == 'tar': + untar(filename) + if suffix == 'zip': + unzip(filename) + os.chdir(os.path.realpath(cur_path)) + + +def ide_entry(argv): + ''' + Function description: ci entry function. + ''' + + # Save the path of the full package tool. + tools_path = str(pathlib.Path().cwd().joinpath('tools', 'toolchain')) + if len(argv) == 3: + copy_chip = argv[1] + copy_path = argv[2] + else: + copy_chip = '3065h' + copy_path = '../mcu_pro' + + # Decompress all compilation tools. + un_alltools(tools_path) + + # Detach the chip package. + copy_code(copy_chip, copy_path) + + os.chdir(pathlib.Path(copy_path).resolve()) + # Write the path of the full package tool to the config.ini file. + config_path = pathlib.Path().cwd().joinpath('build', 'config.ini') + config = ConfigParser() + config.read(config_path) + config.set('gn_args', 'tools_path', tools_path) + flags = os.O_WRONLY | os.O_CREAT | os.O_TRUNC + modes = stat.S_IWUSR | stat.S_IRUSR + with os.fdopen(os.open(config_path, flags, modes), 'w+') as configini: + config.write(configini) + + os.makedirs("ohos_bundles") + + +if __name__ == "__main__": + sys.exit(ide_entry(sys.argv)) diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/packet_create.py b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/packet_create.py new file mode 100644 index 00000000..73add298 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/packet_create.py @@ -0,0 +1,460 @@ +#!/usr/bin/env python3 +# coding=utf-8 + +''' +# @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +# following disclaimer in the documentation and/or other materials provided with the distribution. +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote +# products derived from this software without specific prior written permission. +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# ide_entry.py Function implementation: ide build entry file, which is used to +# copy code and invoke build compilation scripts. +''' +import struct +import sys +import os +import stat +import pathlib +import zlib +import copy +import socket +import collections +from configparser import ConfigParser + + +class Crc16: + POLYNOMIAL = 0x1021 + PRESET = 0x0000 + _tab = [] + + def __init__(self): + self._tab = [self._initial(i) for i in range(256)] + + def crc(self, string): + crc = self.PRESET + for c in string: + crc = self._update_crc(crc, ord(c)) + return crc + + def crcb(self, i): + crc = self.PRESET + for c in i: + crc = self._update_crc(crc, c) + return crc + + def _initial(self, c): + crc = 0 + c = c << 8 + for _i in range(8): + if (crc ^ c) & 0x8000: + crc = (crc << 1) ^ self.POLYNOMIAL + else: + crc = crc << 1 + c = c << 1 + return crc + + def _update_crc(self, crc, c): + cc = 0xff & int(c) + + tmp = (crc >> 8) ^ cc + crc = (crc << 8) ^ self._tab[tmp & 0xff] + crc = crc & 0xffff + return crc + + +def get_config(name): + deveco_path = './.deveco/deveco.ini' + env = "env:" + name + config = ConfigParser() + config.read(deveco_path) + init_value = 'no' + config_dict = dict(generate_crc=init_value, generate_checksum=init_value, padding=init_value) + if name == init_value: + return config_dict + key = 'generate_crc' + if key in config[env]: + config_dict[key] = config[env].get(key) + key = 'generate_checksum' + if key in config[env]: + config_dict[key] = config[env].get(key) + key = 'padding' + if key in config[env]: + config_dict[key] = config[env].get(key) + return config_dict + + +def packet_bin(output_path, input_list): + t = Crc16() + path_list = [] + burn_addr_list = [] + burn_size_list = [] + image_size_list = [] + type_list = [] + for item in input_list: + path, burn_addr, burn_size, burn_type = item.split("|") + image_size = os.path.getsize(path) + path_list.append(path) + burn_addr_list.append(int(burn_addr)) + burn_size_list.append(int(burn_size)) + image_size_list.append(image_size) + type_list.append(int(burn_type)) + + flag = 0xefbeaddf + crc = 0 + image_num = len(path_list) + head_len = image_num * 52 + 12 + total_file_size = sum(image_size_list) + head_len + + flags = os.O_RDWR | os.O_CREAT + modes = stat.S_IWUSR | stat.S_IRUSR + with os.fdopen(os.open(output_path, flags, modes), 'wb+') as file: + file.write(struct.pack('IHHI', flag, crc, image_num, total_file_size)) + start_index = head_len + times = 0 + for path in path_list: + path_name = os.path.basename(path) + file.write( + struct.pack('32sIIIII', bytes(path_name, 'ascii'), start_index, + image_size_list[times], burn_addr_list[times], + burn_size_list[times], type_list[times])) + start_index = start_index + image_size_list[times] + 16 + times += 1 + + for path in path_list: + with os.fdopen(os.open(path, flags, modes), 'rb+') as subfile: + data = subfile.read() + file.write(data) + file.write(struct.pack('IIII', 0, 0, 0, 0)) + + file.flush() + file.seek(6) + newdata = file.read(head_len - 6) + crc16 = t.crcb(newdata) + file.seek(4) + file.write(struct.pack('H', crc16)) + + +def get_len_addr_type(line): + data = int(line[1:9], 16) + length = data >> 24 + addr = (data >> 8) & 0xffff + data_type = data & 0xff + ext_data = int(line[10:13], 16) + Information = collections.namedtuple('Information', ['length', 'addr', 'data_type', 'ext_data']) + return Information(length, addr, data_type, ext_data) + + +def is_start_linear_addr_rec_line(data_type): + return True if data_type == 5 else False + + +def is_ext_linear_addr_rec_line(data_type): + return True if data_type == 4 else False + + +def add_ext_linear_addr_record(fp, addr): + checksum = 0 + data = [] + data.append(':02000004') + checksum += 6 + checksum += (addr & 0xff) + checksum += ((addr >> 8) & 0xff) + data.append("%04x".upper() % (addr)) + checksum = (0x100 - checksum % 0x100) & 0xFF + data.append("%02x".upper() % (checksum)) + data.append('\n') + fp.writelines(data) + + +def add_data_of_crc(fp, addr, crc_val): + checksum = 0 + data = [] + data.append(':04') + checksum += 4 + data.append("%04x".upper() % (addr)) + checksum += (addr & 0xff) + checksum += ((addr >> 8) & 0xff) + data.append('00') + data.append("%08x".upper() % (socket.htonl(crc_val))) + checksum += (crc_val & 0xff) + checksum += ((crc_val >> 8) & 0xff) + checksum += ((crc_val >> 16) & 0xff) + checksum += ((crc_val >> 24) & 0xff) + checksum = (0x100 - checksum % 0x100) & 0xFF + data.append("%02x".upper() % (checksum)) + data.append('\n') + fp.writelines(data) + + +def add_crc(fp, ext_addr, address, crc_val): + addr = address + if addr > 0xFFFF: + add_ext_linear_addr_record(fp, ext_addr + 1) + addr = 0 + add_data_of_crc(fp, addr, crc_val) + + +def gen_crc_padding(fp, lines, crc_val): + is_start_linear_addr_rec = False + ext_linear_addr = 0 + next_addr = 0 + + for line in lines: + length, addr, data_type, ext_data = get_len_addr_type(line) + if is_ext_linear_addr_rec_line(data_type): + ext_linear_addr = ext_data + if not is_start_linear_addr_rec_line(data_type): + next_addr = addr + length + else: + if not is_start_linear_addr_rec: + is_start_linear_addr_rec = True + add_crc(fp, ext_linear_addr, next_addr, crc_val) + fp.writelines(line) + + +def gen_crc_for_hex(filename, crc_val): + flags = os.O_RDWR + modes = stat.S_IWUSR | stat.S_IRUSR + + lines = [] + with os.fdopen(os.open(filename, flags, modes), 'r') as file: + lines = file.readlines() + + flag = os.O_RDWR | os.O_CREAT + with os.fdopen(os.open(filename, flag, modes), 'w+') as file: + gen_crc_padding(file, lines, crc_val) + + +def gen_crc(filename, filename_hex): + flags = os.O_RDWR + modes = stat.S_IWUSR | stat.S_IRUSR + with os.fdopen(os.open(filename, flags, modes), 'rb') as f: + data = f.read() + crc_val = zlib.crc32(data) & 0xFFFFFFFF + with os.fdopen(os.open(filename, flags, modes), 'rb+') as file: + file.seek(0, 2) + crc_val = socket.htonl(crc_val) + file.write(struct.pack('I', crc_val)) + gen_crc_for_hex(filename_hex, crc_val) + + +def findfiles(path, types): + file_list = [] + files = os.listdir(path) + for f in files: + npath = "{}/{}".format(path, f) + if os.path.isfile(npath): + if os.path.splitext(npath)[-1] in types: + file_list.append(npath) + return file_list + + +def packet_bin_with_padding(file, length, val): + while length >= 32: + file.write(struct.pack('IIIIIIII', + val, val, val, val, val, val, val, val)) + length = length - 32 + while length >= 4: + file.write(struct.pack('I', val)) + length = length - 4 + while length > 0: + file.write(struct.pack('B', val & 0xFF)) + length = length - 1 + + +def gen_padding_for_bin(filename, max_len, pad_bit): + flags = os.O_RDWR | os.O_CREAT + modes = stat.S_IWUSR | stat.S_IRUSR + with os.fdopen(os.open(filename, flags, modes), 'ab+') as file: + pad_val = 0xFFFFFFFF + if pad_bit == '0': + pad_val = 0 + image_size = os.path.getsize(filename) + pad_len = max_len - image_size + packet_bin_with_padding(file, pad_len, pad_val) + return pad_len + + +def get_hex_addr(lines): + ext_addr = 0 + next_addr = 0 + for line in lines: + length, addr, data_type, ext_data = get_len_addr_type(line) + if data_type == 4: + ext_addr = ext_data + if data_type == 0: + next_addr = addr + length + return ext_addr, next_addr + + +def get_line_pad_len(addr, max_pad_len): + line_space_size = 0xFFFF - addr + 1 + pad_len = 16 if max_pad_len >= 16 else max_pad_len + if pad_len > line_space_size: + pad_len = line_space_size + return pad_len + + +def gen_ext_addr_rec(ext_addr): + checksum = 0 + data = '' + data += ':02000004' + checksum += 6 + checksum += (ext_addr & 0xff) + checksum += ((ext_addr >> 8) & 0xff) + data += "%04x".upper() % ext_addr + checksum = (0x100 - (checksum & 0xFF)) & 0xFF + data += "%02x\n".upper() % (checksum) + return data + + +def gen_padding_line_rec(addr, length, pad_bit): + checksum = 0 + data = '' + data += ":%02x".upper() % length + checksum += length & 0xff + checksum += (addr & 0xff) + checksum += ((addr >> 8) & 0xff) + data += "%04x00".upper() % addr + pad_val = 0xFF if pad_bit == '1' else 0 + for _i in range(length): + data += "%02x".upper() % pad_val + checksum += pad_val + checksum = (0x100 - (checksum & 0xFF)) & 0xFF + data += "%02x\n".upper() % (checksum) + return data + + +def gen_padding_lines_for_hex(ext_addr, addr, length, pad_bit): + lines = [] + + while length > 0: + pad_len = get_line_pad_len(addr, length) + lines.append(gen_padding_line_rec(addr, pad_len, pad_bit)) + length -= pad_len + addr += pad_len + if addr == 0x10000 and length > 0: + ext_addr += 1 + lines.append(gen_ext_addr_rec(ext_addr)) + addr = 0 + return lines + + +def gen_padding_for_hex(filename, pad_len, pad_bit): + ''' + Generate padding for target.hex + ''' + flags = os.O_RDWR + modes = stat.S_IWUSR | stat.S_IRUSR + lines = [] + ext_addr = int(0) + next_addr = int(0) + with os.fdopen(os.open(filename, flags, modes), 'r') as file: + lines = file.readlines() + ext_addr, next_addr = get_hex_addr(lines) + + start_linear_addr_rec = lines[-2] + end_of_file_rec = lines[-1] + lines.pop() + lines.pop() + + lines += gen_padding_lines_for_hex(ext_addr, next_addr, pad_len, pad_bit) + lines += start_linear_addr_rec + lines += end_of_file_rec + + flag = os.O_RDWR | os.O_CREAT + with os.fdopen(os.open(filename, flag, modes), 'w+') as file: + file.writelines(lines) + + +def gen_checksum_list(filename): + ''' + Generate Checksum list + ''' + path = "./out/bin" + type_list = ['.bin', '.hex'] + file_list = findfiles(path, type_list) + checksum_list = [] + + flags = os.O_RDWR | os.O_CREAT + modes = stat.S_IWUSR | stat.S_IRUSR + for item in file_list: + with os.fdopen(os.open(item, flags, modes), 'rb') as f: + data = f.read() + crc_val = zlib.crc32(data) & 0xFFFFFFFF + file_crc_dict = {} + file_crc_dict['file'] = os.path.split(item)[1] + file_crc_dict['crc'] = hex(crc_val) + checksum_list.append(file_crc_dict) + + with os.fdopen(os.open(filename, flags, modes), 'w') as f: + for info in checksum_list: + file_name = "{}\n".format(info['file']) + f.write(file_name) + crc_str = "CRC:{}\n\n".format(info['crc']) + f.write(crc_str) + + +def main(argv): + ''' + Function description: + 1. add crc for target.bin and hex.bin if generate_crc = yes + 2. add padding for target.bin if padding enable + 3. generate checksum_list.txt and print in IDE TERMINAL windows + 4. Combine loader.bin with image.bin into allinone.bin. + ''' + chipname = 'no' + flashsize = 0 + if len(argv) == 3: + chipname = argv[1] + flashsize = argv[2] + cfg_dict = get_config(chipname) + cfg_dict['max_len'] = flashsize + + loaderbin_path = "./middleware/hisilicon/loaderboot/loader.bin" + targetbin_path = "./out/bin/target.bin" + targethex_path = "./out/bin/target.hex" + allinonebin_path = "./out/bin/allinone.bin" + chksumlisttxt_path = "./out/bin/checksum_list.txt" + str_padding = "padding" + + curpath = pathlib.Path().cwd() + bootloaderpath = curpath.joinpath(loaderbin_path) + eflashpath = curpath.joinpath(targetbin_path) + output_path = curpath.joinpath(allinonebin_path) + + if cfg_dict.get('generate_crc') == 'yes': + gen_crc(targetbin_path, targethex_path) + + if cfg_dict.get(str_padding) != 'no': + pad_len = gen_padding_for_bin(targetbin_path, + int(cfg_dict.get('max_len')), + cfg_dict.get(str_padding)) + gen_padding_for_hex(targethex_path, pad_len, cfg_dict.get(str_padding)) + + input_list = [ + "{}|{}|{}|0".format( + bootloaderpath, 0x2000000, 0x2000000 + 0x3FFF), + "{}|{}|{}|1".format( + eflashpath, 0x3000000, 0x3000000 + 0x27FFF) + ] + + packet_bin(output_path, input_list) + + if cfg_dict.get('generate_checksum') == 'yes': + gen_checksum_list(chksumlisttxt_path) + + +if __name__ == "__main__": + sys.exit(main(sys.argv)) diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/toolchain/BUILD.gn b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/toolchain/BUILD.gn new file mode 100644 index 00000000..282da139 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/toolchain/BUILD.gn @@ -0,0 +1,28 @@ +# @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +# following disclaimer in the documentation and/or other materials provided with the distribution. +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote +# products derived from this software without specific prior written permission. +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# BUILD.gn Function implementation: Pre-configuration of the Compilation Toolchain + +import("//build/toolchain/config.gni") + +hcc_toolchain("riscv32_hcc") { + build_compiler_prefix = "riscv32-linux-musl" + cc = "${build_compiler_prefix}-gcc" + cxx = "${build_compiler_prefix}-g++" + ar = "${build_compiler_prefix}-ar" + ld = cc +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/toolchain/config.gni b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/toolchain/config.gni new file mode 100644 index 00000000..2fb29c75 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/build/toolchain/config.gni @@ -0,0 +1,131 @@ +# @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +# following disclaimer in the documentation and/or other materials provided with the distribution. +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote +# products derived from this software without specific prior written permission. +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# config.gni Function implementation: Global parameter definition and template configuration + +declare_args() { + build_type = "" + build_compiler_specified = "" +} + +template("hcc_toolchain") { + toolchain(target_name) { + assert(defined(invoker.ar), "gcc toolchain must specify a \"ar\" value") + assert(defined(invoker.cc), "gcc toolchain must specify a \"cc\" value") + assert(defined(invoker.cxx), "gcc toolchain must specify a \"cxx\" value") + assert(defined(invoker.ld), "gcc toolchain must specify a \"ld\" value") + + cc = invoker.cc + cxx = invoker.cxx + ar = invoker.ar + ld = invoker.ld + + need_strip = false + if(defined(invoker.strip)) { + strip = invoker.strip + need_strip = true + } + + tool("cc") { + depfile = "{{output}}.d" + command = "$cc -MMD -MF $depfile {{defines}} {{include_dirs}} {{cflags}} -c {{source}} -o {{output}}" + depsformat = "gcc" + description = "cross compiler {{output}}" + outputs = [ + "{{source_out_dir}}/{{source_name_part}}.o", + ] + } + tool("cxx") { + depfile = "{{output}}.d" + command = "$cxx -MMD -MF $depfile {{defines}} {{include_dirs}} {{cflags}} -c {{source}} -o {{output}}" + depsformat = "gcc" + description = "CXX {{output}}" + outputs = [ + "{{source_out_dir}}/{{target_output_name}}.{{source_name_part}}.o", + ] + } + tool("asm") { + depfile = "{{output}}.d" + command = "$cc -MMD -MF $depfile {{defines}} {{include_dirs}} {{cflags}} {{asmflags}} -c {{source}} -o {{output}}" + depsformat = "gcc" + description = "cross compiler {{output}}" + outputs = [ + "{{source_out_dir}}/{{source_name_part}}.o" + ] + } + tool("alink") { + outfile = "{{output_dir}}/{{target_output_name}}{{output_extension}}" + rspfile = "{{output}}.rsp" + rspfile_content = "{{inputs}}" + command = "$ar cr {{output}} @\"$rspfile\"" + + description = "AR {{output}}" + outputs = [ + outfile + ] + + default_output_dir = "{{root_out_dir}}/libs" + default_output_extension = ".a" + output_prefix = "lib" + } + tool("solink") { + outfile = "{{output_dir}}/{{target_output_name}}{{output_extension}}" + rspfile = "{{output}}.rsp" + rspfile_content = "{{inputs}}" + command = "$ld -shared -Wl,--start-group {{ldflags}} " + + "{{inputs}} {{libs}} -Wl,--end-group -o $outfile" + if(need_strip) { + command += "&& $strip $outfile" + } + description = "SOLINK $outfile" + outputs = [ + outfile + ] + + default_output_dir = "{{root_out_dir}}" + default_output_extension = ".so" + output_prefix = "lib" + } + tool("link") { + outfile = "{{output_dir}}/bin/{{target_output_name}}{{output_extension}}" + rspfile = "$outfile.rsp" + command = "$ld -Wl,--start-group {{ldflags}} " + + "-Wl,--whole-archive @$rspfile -Wl,--no-whole-archive {{libs}} -Wl,--end-group -o $outfile" + if(need_strip) { + command += "&& $strip $outfile" + } + + description = "LINK $outfile" + default_output_dir = "{{root_out_dir}}" + rspfile_content = "{{inputs}}" + outputs = [ + outfile + ] + } + tool("stamp") { + if (host_os == "win") { + command = "cmd /c type nul > \"{{output}}\"" + } else { + command = "/usr/bin/touch {{output}}" + } + description = "STAMP {{output}}" + } + tool("copy") { + command = "cp -afd {{source}} {{output}}" + description = "COPY {{source}} {{output}}" + } + } +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/baseaddr.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/baseaddr.h new file mode 100644 index 00000000..a572d1f9 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/baseaddr.h @@ -0,0 +1,214 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file baseaddr.h + * @author MCU Driver Team + * @brief Definition of MCU register baseaddress + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_BASEADDR_H +#define McuMagicTag_BASEADDR_H + +#define CRG_BASE (void *)0x10000000 +#define CMM_BASE (void *)0x10010000 +#define CFD_BASE (void *)0x10020000 +#define SYSCTRL0_BASE (void *)0x10100000 +#define SYSCTRL1_BASE (void *)0x10100000 +#define UART0_BASE (void *)0x14000000 +#define UART1_BASE (void *)0x14001000 +#define UART2_BASE (void *)0x14002000 +#define I2C_BASE (void *)0x14100000 +#define SPI_BASE (void *)0x14200000 +#define TIMER0_BASE (void *)0x14300000 +#define TIMER1_BASE (void *)0x14300020 +#define TIMER2_BASE (void *)0x14301000 +#define SYSTICK_BASE (void *)0x14301020 +#define WDG_BASE (void *)0x14400000 +#define IWDG_BASE (void *)0x14401000 +#define GPIO0_BASE (void *)0x14500000 +#define GPIO1_BASE (void *)0x14501000 +#define GPIO2_BASE (void *)0x14502000 +#define GPIO3_BASE (void *)0x14503000 +#define GPIO4_BASE (void *)0x14504000 +#define GPIO5_BASE (void *)0x14505000 +#define GPIO6_BASE (void *)0x14506000 +#define GPIO7_BASE (void *)0x14507000 +#define CAN_BASE (void *)0x14600000 +#define GPT0_BASE (void *)0x14700000 +#define GPT1_BASE (void *)0x14701000 +#define EFC_BASE (void *)0x14710000 +#define FOTP_BASE (void *)0x14720000 +#define HPM_BASE (void *)0x147D0000 +#define PMC_BASE (void *)0x147E0000 +#define LS_IOCFG_BASE (void *)0x147F0000 +#define CRC_BASE (void *)0x14800000 +#define HS_IOCFG_BASE (void *)0x149F0000 +#define APT0_BASE (void *)0x14A00000 +#define APT1_BASE (void *)0x14A01000 +#define APT2_BASE (void *)0x14A02000 +#define APT3_BASE (void *)0x14A03000 +#define APT4_BASE (void *)0x14A04000 +#define APT5_BASE (void *)0x14A05000 +#define APT6_BASE (void *)0x14A06000 +#define APT7_BASE (void *)0x14A07000 +#define APT8_BASE (void *)0x14A08000 +#define CAPM0_BASE (void *)0x14B00000 +#define CAPM1_BASE (void *)0x14B01000 +#define CAPM2_BASE (void *)0x14B02000 +#define CAPM_COMM_BASE (void *)0x14B03000 +#define QDM0_BASE (void *)0x14C00000 +#define ADC0_BASE (void *)0x18000000 +#define ADC1_BASE (void *)0x18001000 +#define ADC2_BASE (void *)0x18002000 +#define PGA0_BASE (void *)0x18200000 +#define PGA1_BASE (void *)0x18201000 +#define PGA2_BASE (void *)0x18202000 +#define DAC0_BASE (void *)0x18300000 +#define ACMP0_BASE (void *)0x18300008 +#define DAC1_BASE (void *)0x18301000 +#define ACMP1_BASE (void *)0x18301008 +#define DAC2_BASE (void *)0x18302000 +#define ACMP2_BASE (void *)0x18302008 +#define DMA_BASE (void *)0x1C000000 +#define DMA_CHANNEL0_BASE (void *)0x1C000100 +#define DMA_CHANNEL1_BASE (void *)0x1C000120 +#define DMA_CHANNEL2_BASE (void *)0x1C000140 +#define DMA_CHANNEL3_BASE (void *)0x1C000160 +#define IOCONFIG_BASE (void *)0x147e0000 +#define IOCMG_BASE (void *)0x147e0000 +#define IOCMG_AON_BASE (void *)0x147e0000 +#define IOCMG_CORE_BASE (void *)0x147f0000 +#define IOCMG_ANA_BASE (void *)0x149f0000 +#define TSENSOR_BASE (void *)0x1010A000 + +#define CRG ((CRG_RegStruct *)CRG_BASE) +#define CMM ((CMM_RegStruct *)CMM_BASE) +#define CFD ((CFD_RegStruct *)CFD_BASE) +#define SYSCTRL0 ((SYSCTRL0_RegStruct *)SYSCTRL0_BASE) +#define SYSCTRL1 ((SYSCTRL1_RegStruct *)SYSCTRL1_BASE) +#define UART0 ((UART_RegStruct *)UART0_BASE) +#define UART1 ((UART_RegStruct *)UART1_BASE) +#define UART2 ((UART_RegStruct *)UART2_BASE) +#define I2C ((I2C_RegStruct *)I2C_BASE) +#define SPI ((SPI_RegStruct *)SPI_BASE) +#define TIMER0 ((TIMER_RegStruct *)TIMER0_BASE) +#define TIMER1 ((TIMER_RegStruct *)TIMER1_BASE) +#define TIMER2 ((TIMER_RegStruct *)TIMER2_BASE) +#define SYSTICK ((TIMER_RegStruct *)SYSTICK_BASE) +#define WDG ((WDG_RegStruct *)WDG_BASE) +#define IWDG ((IWDG_RegStruct *)IWDG_BASE) +#define GPIO0 ((GPIO_RegStruct *)GPIO0_BASE) +#define GPIO1 ((GPIO_RegStruct *)GPIO1_BASE) +#define GPIO2 ((GPIO_RegStruct *)GPIO2_BASE) +#define GPIO3 ((GPIO_RegStruct *)GPIO3_BASE) +#define GPIO4 ((GPIO_RegStruct *)GPIO4_BASE) +#define GPIO5 ((GPIO_RegStruct *)GPIO5_BASE) +#define GPIO6 ((GPIO_RegStruct *)GPIO6_BASE) +#define GPIO7 ((GPIO_RegStruct *)GPIO7_BASE) +#define CAN ((CAN_RegStruct *)CAN_BASE) +#define GPT0 ((GPT_RegStruct *)GPT0_BASE) +#define GPT1 ((GPT_RegStruct *)GPT1_BASE) +#define EFC ((EFC_RegStruct *)EFC_BASE) +#define FOTP ((FOTP_RegStruct *)FOTP_BASE) +#define HPM ((HPM_RegStruct *)HPM_BASE) +#define PMC ((PMC_RegStruct *)PMC_BASE) +#define LS_IOCFG ((LS_IOCFG_RegStruct *)LS_IOCFG_BASE) +#define CRC ((CRC_RegStruct *)CRC_BASE) +#define HS_IOCFG ((HS_IOCFG_RegStruct *)HS_IOCFG_BASE) +#define APT0 ((APT_RegStruct *)APT0_BASE) +#define APT1 ((APT_RegStruct *)APT1_BASE) +#define APT2 ((APT_RegStruct *)APT2_BASE) +#define APT3 ((APT_RegStruct *)APT3_BASE) +#define APT4 ((APT_RegStruct *)APT4_BASE) +#define APT5 ((APT_RegStruct *)APT5_BASE) +#define APT6 ((APT_RegStruct *)APT6_BASE) +#define APT7 ((APT_RegStruct *)APT7_BASE) +#define APT8 ((APT_RegStruct *)APT8_BASE) +#define CAPM0 ((CAPM_RegStruct *)CAPM0_BASE) +#define CAPM1 ((CAPM_RegStruct *)CAPM1_BASE) +#define CAPM2 ((CAPM_RegStruct *)CAPM2_BASE) +#define CAPM_COMM ((CAPM_COMM_RegStruct *)CAPM_COMM_BASE) +#define QDM0 ((QDM_RegStruct *)QDM0_BASE) +#define ADC0 ((ADC_RegStruct *)ADC0_BASE) +#define ADC1 ((ADC_RegStruct *)ADC1_BASE) +#define ADC2 ((ADC_RegStruct *)ADC2_BASE) +#define PGA0 ((PGA_RegStruct *)PGA0_BASE) +#define PGA1 ((PGA_RegStruct *)PGA1_BASE) +#define PGA2 ((PGA_RegStruct *)PGA2_BASE) +#define DAC0 ((DAC_RegStruct *)DAC0_BASE) +#define DAC1 ((DAC_RegStruct *)DAC1_BASE) +#define DAC2 ((DAC_RegStruct *)DAC2_BASE) +#define ACMP0 ((ACMP_RegStruct *)ACMP0_BASE) +#define ACMP1 ((ACMP_RegStruct *)ACMP1_BASE) +#define ACMP2 ((ACMP_RegStruct *)ACMP2_BASE) +#define DMA ((DMA_RegStruct *)DMA_BASE) +#define DMA_CHANNEL0 ((DMA_ChannelRegStruct *)DMA_CHANNEL0_BASE) +#define DMA_CHANNEL1 ((DMA_ChannelRegStruct *)DMA_CHANNEL1_BASE) +#define DMA_CHANNEL2 ((DMA_ChannelRegStruct *)DMA_CHANNEL2_BASE) +#define DMA_CHANNEL3 ((DMA_ChannelRegStruct *)DMA_CHANNEL3_BASE) +#define IOCONFIG ((IOConfig_RegStruct *)IOCONFIG_BASE) +#define IOCMG ((IOConfig_RegStruct*)IOCMG_BASE) +#define TSENSOR ((TSENSOR_RegStruct *)TSENSOR_BASE) + +#define IsCRGInstance(instance) ((instance) == CRG) +#define IsCMMInstance(instance) ((instance) == CMM) +#define IsCFDInstance(instance) ((instance) == CFD) +#define IsSYSCTRLInstance(instance) (((instance) == SYSCTRL0) || ((instance) == SYSCTRL1)) +#define IsUARTInstance(instance) (((instance) == UART0) || ((instance) == UART1) || ((instance) == UART2)) +#define IsI2CInstance(instance) ((instance) == I2C) +#define IsSPIInstance(instance) ((instance) == SPI) +#define IsTIMERInstance(instance) (((instance) == TIMER0) || ((instance) == TIMER1) || \ + ((instance) == TIMER2) || ((instance) == SYSTICK)) +#define IsSYSTICKInstance(instance) ((instance) == SYSTICK) +#define IsWDGInstance(instance) ((instance) == WDG) +#define IsIWDGInstance(instance) ((instance) == IWDG) +#define IsGPIOInstance(instance) (((instance) == GPIO0) || ((instance) == GPIO1) || \ + ((instance) == GPIO2) || ((instance) == GPIO3) || \ + ((instance) == GPIO4) || ((instance) == GPIO5) || \ + ((instance) == GPIO6) || ((instance) == GPIO7)) +#define IsCANInstance(instance) ((instance) == CAN) +#define IsGPTInstance(instance) (((instance) == GPT0) || ((instance) == GPT1)) +#define IsEFCInstance(instance) ((instance) == EFC) +#define IsFOTPInstance(instance) ((instance) == FOTP) +#define IsHPMInstance(instance) ((instance) == HPM) +#define IsPMCInstance(instance) ((instance) == PMC) +#define IsLSIOCFGInstance(instance) ((instance) == LS_IOCFG) +#define IsCRCInstance(instance) ((instance) == CRC) +#define IsHSIOCFGInstance(instance) ((instance) == HS_IOCFG) +#define IsAPTInstance(instance) (((instance) == APT0) || ((instance) == APT1) || \ + ((instance) == APT2) || ((instance) == APT3) || \ + ((instance) == APT4) || ((instance) == APT5) || \ + ((instance) == APT6) || ((instance) == APT7) || ((instance) == APT8)) +#define IsCAPMInstance(instance) (((instance) == CAPM0) || ((instance) == CAPM1) || ((instance) == CAPM2)) +#define IsCAPMCOMMInstance(instance) ((instance) == CAPM_COMM) +#define IsQDMInstance(instance) ((instance) == QDM0) +#define IsADCInstance(instance) (((instance) == ADC0) || ((instance) == ADC1) || ((instance) == ADC2)) +#define IsPGAInstance(instance) (((instance) == PGA0) || ((instance) == PGA1) || ((instance) == PGA2)) +#define IsDACInstance(instance) (((instance) == DAC0) || ((instance) == DAC1) || ((instance) == DAC2)) +#define IsACMPInstance(instance) (((instance) == ACMP0) || ((instance) == ACMP1) || ((instance) == ACMP2)) +#define IsDMAInstance(instance) ((instance) == DMA) +#define IsDMACHXInstance(instance) (((instance) == DMA_CHANNEL0) || ((instance) == DMA_CHANNEL1) || \ + ((instance) == DMA_CHANNEL2) || ((instance) == DMA_CHANNEL3)) +#define IsIOCMGInstance(instance) ((instance) == IOCMG || (instance) == IOCMG_AON_BASE || \ + (instance) == IOCMG_CORE_BASE || (instance) == IOCMG_ANA_BASE) + +#define SRAM_START 0x4000000 +#define SRAM_END 0x4003FFF +#define REGISTER_START 0x10000000 +#define REGISTER_END 0x1FFFFFFF +#endif /* McuMagicTag_BASEADDR_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinc.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinc.h new file mode 100644 index 00000000..3994c661 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinc.h @@ -0,0 +1,37 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file chipinc.h + * @author MCU Driver Team + * @brief Contains chip-related header files. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_CHIPINC_H +#define McuMagicTag_CHIPINC_H + +/* Includes ------------------------------------------------------------------ */ +#include "feature.h" +#include "info.h" +#include "baseaddr.h" +#include "locktype.h" +#include "interrupt_ip.h" +#include "sysctrl.h" +#include "systick.h" +#include "ip_crg_common.h" + +#endif /* McuMagicTag_CHIPINC_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/adc_tsensor/adc_tsensor.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/adc_tsensor/adc_tsensor.c new file mode 100644 index 00000000..03f37007 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/adc_tsensor/adc_tsensor.c @@ -0,0 +1,49 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file adc_tsensor.c + * @author MCU Driver Team + * @brief tsensor init module. + * @details tsensor initialization verification parameter table during startup + */ + +#include "fotp_info_read.h" +#include "adc_tsensor.h" + +TSENSOR_VrefList g_tsensor[1] = {0}; +unsigned int g_hosc_ctrim = 0x1FF; + +/** + * @brief ADC initialize vref power. + * @param None. + * @retval None. + */ +void TSENSOR_InitVrefList(void) +{ + FOTP_INFO_RGN0_NUMBER_1 tsensorRef; + FOTP_InfoGet(FOTP_INFO_RNG0, 1, &tsensorRef.comData); /* 1 is the index of tsensorRef in otp */ + unsigned int t = tsensorRef.REG.data3.ts_ref_t0_ft_rt - 57; /* offset temperature is -57 */ + float v = tsensorRef.REG.data3.ts_ref_v0_ft_rt * 0.0031f + 0.65f; /* offset Voltage is 0.65, degree is 0.0031 */ + float slope = (v) / (float)(t + 273); /* reference temperature is -273 */ + g_tsensor->vrefTemp = t; + g_tsensor->vrefVoltage = v; + g_tsensor->slope = slope; + FOTP_INFO_RGN0_NUMBER_1 trimDate; + FOTP_InfoGet(FOTP_INFO_RNG0, 1, &trimDate.comData); /* 1 is the number of adc_vref in otp */ + g_hosc_ctrim = trimDate.REG.data2.hosc_ctrim_ft_rt; + return; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/adc_tsensor/adc_tsensor.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/adc_tsensor/adc_tsensor.h new file mode 100644 index 00000000..50964a4a --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/adc_tsensor/adc_tsensor.h @@ -0,0 +1,40 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file adc_tsensor.c + * @author MCU Driver Team + * @brief tsensor init module. + * @details tsensor initialization verification parameter table during startup + */ + +#ifndef McuMagicTag_ADC_TSENSOR_H +#define McuMagicTag_ADC_TSENSOR_H + +#define ADCX_TSENSOR ADC1 +#define ADCX_TSENSOR_BASE ADC1_BASE +#define TSENSOR_SAMPLE_CH ADC_CH_ADCINB6 + +typedef struct { + float vrefVoltage; + float slope; + unsigned int vrefTemp : 16; +} TSENSOR_VrefList; + +extern TSENSOR_VrefList g_tsensor[1]; +extern unsigned int g_hosc_ctrim; +void TSENSOR_InitVrefList(void); +#endif /* McuMagicTag_ADC_TSENSOR_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/adcinit/adcinit.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/adcinit/adcinit.c new file mode 100644 index 00000000..66ea6e38 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/adcinit/adcinit.c @@ -0,0 +1,191 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file adcinit.c + * @author MCU Driver Team + * @brief adc init module. + * @details adc initialization function during startup + */ + +#include "fotp_info_read.h" +#include "adc_ip.h" +#include "dac_ip.h" +#include "adcinit.h" + +ADC_TrimValue g_adcTrimList[LIST_NUM] = {0}; +ADC_ParameterList g_adcParmList[4][3][2] = {0}; +bool g_trimEnable = false; +unsigned int g_versionId = 0xFF; +static void ADC_CreateTrimList(void); +static void ADC_CreateParmList(void); + +/** + * @brief ADC initialize vref power. + * @param None. + * @retval None. + */ +void ADC_InitVref(void) +{ + FOTP_INFO_RGN0_NUMBER_4 trimDate; + FOTP_InfoGet(FOTP_INFO_RNG0, 4, &trimDate.comData); /* 4 is the number of fotp_empty_flag in otp */ + if (trimDate.REG.fotp_empty_flag == 0x5AA59669) { /* fotp_empty_flag is 0x5AA59669 */ + g_trimEnable = true; + } + FOTP_INFO_RGN0_NUMBER_2 idInfo; + FOTP_InfoGet(FOTP_INFO_RNG0, 2, &idInfo.comData); /* 2 is the number of in otp */ + g_versionId = idInfo.REG.data2.version_id; + FOTP_INFO_RGN0_NUMBER_21 adcVrefTrim; + if (g_trimEnable == true) { + FOTP_InfoGet(FOTP_INFO_RNG0, 21, &adcVrefTrim.comData); /* 21 is the number of adc_vref in otp */ + } else { + adcVrefTrim.REG.data1.adcvref_bg_trim = 0x10; /* Use the default value 0x10 */ + adcVrefTrim.REG.data1.adcvref_adcldo_trim = 0x10; + adcVrefTrim.REG.data2.adcvref_refbuf0_trim_2p0v = 0x10; + adcVrefTrim.REG.data3.adcvref_refbuf0_trim_2p5v = 0x10; + adcVrefTrim.REG.data2.adcvref_refbuf1_trim_2p0v = 0x10; + adcVrefTrim.REG.data3.adcvref_refbuf1_trim_2p5v = 0x10; + adcVrefTrim.REG.data2.adcvref_refbuf2_trim_2p0v = 0x10; + adcVrefTrim.REG.data3.adcvref_refbuf2_trim_2p5v = 0x10; + } + SYSCTRL1->ADCVREF_CTRL0.BIT.adcvref_bg_trim = adcVrefTrim.REG.data1.adcvref_bg_trim; + SYSCTRL1->ADCVREF_CTRL0.BIT.adcvref_bg_en = BASE_CFG_ENABLE; + SYSCTRL1->ADCVREF_CTRL1.BIT.adcvref_adcldo_trim = adcVrefTrim.REG.data1.adcvref_adcldo_trim; + SYSCTRL1->ADCVREF_CTRL1.BIT.adcvref_adcldo_en = BASE_CFG_ENABLE; + SYSCTRL1->ADC0_VREF_CTRL.BIT.adcvref_refbuf_trim0_2p0v = adcVrefTrim.REG.data2.adcvref_refbuf0_trim_2p0v; + SYSCTRL1->ADC0_VREF_CTRL.BIT.adcvref_refbuf_trim0_2p5v = adcVrefTrim.REG.data3.adcvref_refbuf0_trim_2p5v; + SYSCTRL1->ADC1_VREF_CTRL.BIT.adcvref_refbuf_trim1_2p0v = adcVrefTrim.REG.data2.adcvref_refbuf1_trim_2p0v; + SYSCTRL1->ADC1_VREF_CTRL.BIT.adcvref_refbuf_trim1_2p5v = adcVrefTrim.REG.data3.adcvref_refbuf1_trim_2p5v; + SYSCTRL1->ADC2_VREF_CTRL.BIT.adcvref_refbuf_trim2_2p0v = adcVrefTrim.REG.data2.adcvref_refbuf2_trim_2p0v; + SYSCTRL1->ADC2_VREF_CTRL.BIT.adcvref_refbuf_trim2_2p5v = adcVrefTrim.REG.data3.adcvref_refbuf2_trim_2p5v; + BASE_FUNC_DELAY_MS(10); /* Wait for 10 ms until the LDO becomes stable */ + unsigned int ldoStatu = SYSCTRL1->ADCVREF_CTRL1.BIT.adcvref_adcldo_ok; + if (ldoStatu == BASE_CFG_ENABLE) { + SYSCTRL1->ADCVREF_CTRL6.reg |= 0x800000; + } + if (g_trimEnable == true) { + ADC_CreateTrimList(); + ADC_CreateParmList(); + } +} + +/** + * @brief Establish ADC calibration parameter list. + * @param None. + * @retval None. + */ +static void ADC_CreateTrimList(void) +{ + unsigned int index = 0; + FOTP_INFO_RGN0_NUMBER_22 adc0Sh0; + FOTP_InfoGet(FOTP_INFO_RNG0, 22, &adc0Sh0.comData); /* 22 is the number of adc calibration trim in otp */ + FOTP_INFO_RGN0_NUMBER_23 adc0Sh1; + FOTP_InfoGet(FOTP_INFO_RNG0, 23, &adc0Sh1.comData); /* 23 is the number of adc calibration trim in otp */ + /* ADC0 vref2.0 SH0 and SH1 */ + g_adcTrimList[index].gain = adc0Sh0.REG.data0.adc0_sh0_g0p6_ge_trim; + g_adcTrimList[index++].offset = adc0Sh0.REG.data0.adc0_sh0_g0p6_oe_trim; + g_adcTrimList[index].gain = adc0Sh1.REG.data0.adc0_sh1_g0p6_ge_trim; + g_adcTrimList[index++].offset = adc0Sh1.REG.data0.adc0_sh1_g0p6_oe_trim; + /* ADC0 vref2.5 SH0 and SH1 */ + g_adcTrimList[index].gain = adc0Sh0.REG.data2.adc0_sh0_g0p75_ge_trim; + g_adcTrimList[index++].offset = adc0Sh0.REG.data2.adc0_sh0_g0p75_oe_trim; + g_adcTrimList[index].gain = adc0Sh1.REG.data2.adc0_sh1_g0p75_ge_trim ; + g_adcTrimList[index++].offset = adc0Sh1.REG.data2.adc0_sh1_g0p75_oe_trim; + + FOTP_INFO_RGN0_NUMBER_24 adc1Sh0; + FOTP_InfoGet(FOTP_INFO_RNG0, 24, &adc1Sh0.comData); /* 24 is the number of adc calibration trim in otp */ + FOTP_INFO_RGN0_NUMBER_25 adc1Sh1; + FOTP_InfoGet(FOTP_INFO_RNG0, 25, &adc1Sh1.comData); /* 25 is the number of adc calibration trim in otp */ + /* ADC1 vref2.0 SH0 and SH1 */ + g_adcTrimList[index].gain = adc1Sh0.REG.data0.adc1_sh0_g0p6_ge_trim; + g_adcTrimList[index++].offset = adc1Sh0.REG.data0.adc1_sh0_g0p6_oe_trim; + g_adcTrimList[index].gain = adc1Sh1.REG.data0.adc1_sh1_g0p6_ge_trim; + g_adcTrimList[index++].offset = adc1Sh1.REG.data0.adc1_sh1_g0p6_oe_trim; + /* ADC1 vref2.5 SH0 and SH1 */ + g_adcTrimList[index].gain = adc1Sh0.REG.data2.adc1_sh0_g0p75_ge_trim ; + g_adcTrimList[index++].offset = adc1Sh0.REG.data2.adc1_sh0_g0p75_oe_trim; + g_adcTrimList[index].gain = adc1Sh1.REG.data2.adc1_sh1_g0p75_ge_trim ; + g_adcTrimList[index++].offset = adc1Sh1.REG.data2.adc1_sh1_g0p75_oe_trim; + + FOTP_INFO_RGN0_NUMBER_26 adc2Sh0; + FOTP_InfoGet(FOTP_INFO_RNG0, 26, &adc2Sh0.comData); /* 26 is the number of adc calibration trim in otp */ + FOTP_INFO_RGN0_NUMBER_27 adc2Sh1; + FOTP_InfoGet(FOTP_INFO_RNG0, 27, &adc2Sh1.comData); /* 27 is the number of adc calibration trim in otp */ + /* ADC2 vref2.0 SH0 and SH1 */ + g_adcTrimList[index].gain = adc2Sh0.REG.data0.adc2_sh0_g0p6_ge_trim; + g_adcTrimList[index++].offset = adc2Sh0.REG.data0.adc2_sh0_g0p6_oe_trim; + g_adcTrimList[index].gain = adc2Sh1.REG.data0.adc2_sh1_g0p6_ge_trim; + g_adcTrimList[index++].offset = adc2Sh1.REG.data0.adc2_sh1_g0p6_oe_trim; + /* ADC2 vref2.5 SH0 and SH1 */ + g_adcTrimList[index].gain = adc2Sh0.REG.data2.adc2_sh0_g0p75_ge_trim ; + g_adcTrimList[index++].offset = adc2Sh0.REG.data2.adc2_sh0_g0p75_oe_trim; + g_adcTrimList[index].gain = adc2Sh1.REG.data2.adc2_sh1_g0p75_ge_trim ; + g_adcTrimList[index++].offset = adc2Sh1.REG.data2.adc2_sh1_g0p75_oe_trim; +} + +/** + * @brief Obtains the adc gain value. + * @param None. + * @retval gain value. + */ +float ADC_GetGainTrim(unsigned int index) +{ + unsigned int temp = g_adcTrimList[index].gain; + float ret = (float)temp / (float)4096; /* 4096 for decimal conversion */ + return ret; +} + +/** + * @brief Obtains the adc offset value. + * @param None. + * @retval offset value. + */ +float ADC_GetOffsetTrim(unsigned int index) +{ + unsigned temp = g_adcTrimList[index].offset; + float ret; + if ((temp & 0x2000) == 0x2000) { /* determine the sign bit[13] */ + temp |= 0xFFFFC000; + unsigned int tmp = ~(temp - 1); + ret = (0 - (int)tmp) / (float)2; /* 2 for decimal conversion */ + } else { + temp &= 0x1FFF; + ret = (float)temp / (float)2; /* 2 for decimal conversion */ + } + return ret; +} + +/** + * @brief Establish ADC calibration parameter list. + * @param None. + * @retval None. + */ +static void ADC_CreateParmList(void) +{ + float gain, offset, tmpk2; + unsigned int addrIndex, vrefIndex, shIndex, tmpIndex; + for (unsigned int index = 0; index < LIST_NUM; ++index) { + addrIndex = index / 4; /* 4 used to create list */ + tmpIndex = index % 4; /* 4 used to create list */ + vrefIndex = ((tmpIndex / 2) == 1) ? 1 : 2; /* index of vref2.0 is 2, index of vref2.0 is 1 */ + shIndex = index % 2; /* 2 used to create list */ + gain = ADC_GetGainTrim(index); + offset = ADC_GetOffsetTrim(index); + tmpk2 = (float)(2048 - (2048 - offset) * gain); /* 2048 is formula parameters */ + g_adcParmList[addrIndex][vrefIndex][shIndex].k1 = gain; + g_adcParmList[addrIndex][vrefIndex][shIndex].k2 = tmpk2; + } +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/adcinit/adcinit.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/adcinit/adcinit.h new file mode 100644 index 00000000..809f2c43 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/adcinit/adcinit.h @@ -0,0 +1,46 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file adcinit.h + * @author MCU Driver Team + * @brief adc init module. + * @details adc initialization function during startup + */ + +#ifndef McuMagicTag_ADCINIT_H +#define McuMagicTag_ADCINIT_H + +#include "baseinc.h" +#define LIST_NUM 12 + +typedef struct { + unsigned int gain : 16; + unsigned int offset : 16; +} ADC_TrimValue; + +typedef struct { + float k1; + float k2; +} ADC_ParameterList; + +extern ADC_TrimValue g_adcTrimList[LIST_NUM]; +extern ADC_ParameterList g_adcParmList[4][3][2]; + +void ADC_InitVref(void); +float ADC_GetGainTrim(unsigned int index); +float ADC_GetOffsetTrim(unsigned int index); +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/chipinit.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/chipinit.c new file mode 100644 index 00000000..5247dd10 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/chipinit.c @@ -0,0 +1,85 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file chipint.c + * @author MCU Driver Team + * @brief Chip Init module. + * @details Declare a function that needs to be executed as soon as the C + * runtime environment is ready + */ +#include "chipinc.h" +#include "adcinit.h" +#include "adc_tsensor.h" +#include "pgainit.h" +#include "pmcinit.h" +#include "crginit.h" +#include "systickinit.h" +#include "flashinit.h" +#include "crg.h" +#include "interrupt.h" +#include "chipinit.h" +#ifdef NOS_TASK_SUPPORT +#include "nosinit.h" +#endif + +/** + * @brief Chip Init Fail Process, deadloop if Chip Init fail + * @param None + * @retval None + */ +static inline void Chip_InitFail(void) +{ + while (1) { + ; + } +} + +/** + * @brief Chip Init + * @param None + * @retval None + */ +void Chip_Init(void) +{ + CRG_CoreClkSelect coreClkSelect; + /* Config CRG */ + if (CRG_Config(&coreClkSelect) != BASE_STATUS_OK) { + Chip_InitFail(); + } + + /* Config FLASH Clock */ + FLASH_ClockConfig(coreClkSelect); + SYSTICK_Init(); + /* Set CoreClock Select after FLASH Config Done */ + CRG_SetCoreClockSelect(coreClkSelect); + + /* Waiting CRG Config Done */ + if (HAL_CRG_GetCoreClkFreq() != HOSC_FREQ) { + FLASH_WaitClockConfigDone(); + } + + IRQ_Init(); + ADC_InitVref(); + TSENSOR_InitVrefList(); + PGA_InitVref(); + PMC_InitVref(); + /* User Add Code Here */ + +#ifdef NOS_TASK_SUPPORT + NOS_Init(); +#endif +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/chipinit.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/chipinit.h new file mode 100644 index 00000000..9df3359c --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/chipinit.h @@ -0,0 +1,31 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file chipinit.h + * @author MCU Driver Team + * @brief Chip Init module. + * @details Declare a function that needs to be executed as soon as the C + * runtime environment is ready + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_CHIPINIT_H +#define McuMagicTag_CHIPINIT_H + +void Chip_Init(void); + +#endif /* McuMagicTag_CHIPINIT_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/crginit/crginit.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/crginit/crginit.c new file mode 100644 index 00000000..7b1ba9e8 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/crginit/crginit.c @@ -0,0 +1,62 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file crginit.c + * @author MCU Driver Team + * @brief crg init module. + * @details crg initialization function during startup + */ +#include "crginit.h" + +/** + * @brief CRG Config + * @param coreClkSelect OutPut core clock select value + * @retval None + */ +__weak BASE_StatusType CRG_Config(CRG_CoreClkSelect *coreClkSelect) +{ + BASE_FUNC_ASSERT_PARAM(coreClkSelect != NULL); + + CRG_Handle crg; + crg.baseAddress = CRG; + crg.pllRefClkSelect = CRG_PLL_REF_CLK_SELECT_HOSC; + crg.pllFbDiv = 0x20; /* PLL loop divider ratio = 0x20 */ + crg.pllPreDiv = CRG_PLL_PREDIV_4; + crg.pllPostDiv = CRG_PLL_POSTDIV_1; + crg.coreClkSelect = CRG_CORE_CLK_SELECT_PLL; + if (HAL_CRG_Init(&crg) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + *coreClkSelect = crg.coreClkSelect; + return BASE_STATUS_OK; +} + +/** + * @brief Set Crg Core clock select + * @param coreClkSelect Input core clock select value + * @retval None + */ +void CRG_SetCoreClockSelect(CRG_CoreClkSelect coreClkSelect) +{ + CRG_Handle crg; + crg.baseAddress = CRG; + crg.coreClkSelect = coreClkSelect; + if (crg.coreClkSelect == CRG_CORE_CLK_SELECT_TCXO) { /* If an external crystal oscillator is selected. */ + BASE_FUNC_DELAY_MS(10); /* 10: delay 10ms, wait clokc stable. */ + } + HAL_CRG_SetCoreClockSelect(&crg); +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/crginit/crginit.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/crginit/crginit.h new file mode 100644 index 00000000..7a7ce607 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/crginit/crginit.h @@ -0,0 +1,33 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file crginit.h + * @author MCU Driver Team + * @brief crg init module. + * @details crg initialization function during startup + */ + +#ifndef McuMagicTag_CRGINIT_H +#define McuMagicTag_CRGINIT_H + +#include "baseinc.h" +#include "crg.h" + +BASE_StatusType CRG_Config(CRG_CoreClkSelect *coreClkSelect); +void CRG_SetCoreClockSelect(CRG_CoreClkSelect coreClkSelect); + +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/flashinit/flashinit.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/flashinit/flashinit.c new file mode 100644 index 00000000..ae3fe6c2 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/flashinit/flashinit.c @@ -0,0 +1,125 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file flashinit.c + * @author MCU Driver Team + * @brief flash init module. + * @details flash initialization function during startup + */ +#include "chipinit.h" +#include "crg.h" +#include "flash_ip.h" +#include "flashinit.h" + +#define FREQ_1MHz (1000 * 1000) +#define SREAD_DIV_STEP (5 * FREQ_1MHz) +#define NREAD_DIV_STEP (50 * FREQ_1MHz) +#define SWMTIMER_OPTVAL_STEP (10 * FREQ_1MHz) +#define SMWTIMER_OPTVAL_MIN_VAL 2 + +/** + * @brief Get the Rounding up value + * @param val input value + * @param modulo modeulo value + * @retval value after rounding up process + */ +static inline unsigned int RoundingUp(unsigned int val, unsigned int modulo) +{ + return (val + modulo - 1) / modulo; +} + +/** + * @brief Get the Rounding up value + * @param coreClkSelect Core Clock select + * @retval Frequency of Flash + */ +static unsigned int GetFlashFreq(CRG_CoreClkSelect coreClkSelect) +{ + unsigned int hclk; + + switch (coreClkSelect) { + case CRG_CORE_CLK_SELECT_HOSC: + hclk = HOSC_FREQ; + break; + + case CRG_CORE_CLK_SELECT_TCXO: + hclk = XTRAIL_FREQ; + break; + + case CRG_CORE_CLK_SELECT_PLL: + hclk = HAL_CRG_GetPllFreq(); + break; + + default: + hclk = LOSC_FREQ; + break; + } + return hclk; +} + +/** + * @brief Set flash clock frequence base on hclk + * @param coreClkSelect core clock select + * @retval None + */ +void FLASH_ClockConfig(CRG_CoreClkSelect coreClkSelect) +{ + EFC_RegStruct *efc = EFC; + EFLASH_CLK_CFG_REG cfg; + unsigned int hclk; + unsigned int pclk; + unsigned int freq; + unsigned int sreadDiv; + unsigned int smwTimerOptVal; + + hclk = GetFlashFreq(coreClkSelect); + pclk = hclk >> 1; + + cfg.reg = efc->EFLASH_CLK_CFG.reg; + cfg.BIT.busclk_switch_protect_enable = BASE_CFG_SET; + cfg.BIT.busclk_sw_req = BASE_CFG_SET; + + cfg.BIT.ef_timer_option_unit = RoundingUp(pclk, FREQ_1MHz); + freq = hclk; + sreadDiv = 0; + while (freq > SREAD_DIV_STEP) { + sreadDiv++; + freq >>= 1; + } + cfg.BIT.sread_div = sreadDiv; + cfg.BIT.nread_div = RoundingUp(hclk, NREAD_DIV_STEP) - 1; + cfg.BIT.m20ns_div = cfg.BIT.nread_div; + efc->EFLASH_CLK_CFG.reg = cfg.reg; + smwTimerOptVal = RoundingUp(pclk, SWMTIMER_OPTVAL_STEP); + if (smwTimerOptVal < SMWTIMER_OPTVAL_MIN_VAL) { + smwTimerOptVal = SMWTIMER_OPTVAL_MIN_VAL; + } + efc->SMW_TIMER_OPTION.BIT.smw_timer_option_value = smwTimerOptVal; +} + +/** + * @brief Wait flash clock config done + * @param None + * @retval None + */ +void FLASH_WaitClockConfigDone(void) +{ + EFC_RegStruct *efc = EFC; + while (efc->EFLASH_CLK_CFG.BIT.busclk_sw_req == BASE_CFG_SET) { + ; /* Wait Eflash frequency switching completes configuration query */ + } +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/flashinit/flashinit.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/flashinit/flashinit.h new file mode 100644 index 00000000..8c11df72 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/flashinit/flashinit.h @@ -0,0 +1,33 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file flashinit.h + * @author MCU Driver Team + * @brief flash init module. + * @details flash initialization function during startup + */ + +#ifndef McuMagicTag_FLASHINIT_H +#define McuMagicTag_FLASHINIT_H + +#include "baseinc.h" +#include "crg.h" + +void FLASH_ClockConfig(CRG_CoreClkSelect coreClkSelect); +void FLASH_WaitClockConfigDone(void); + +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/nosinit/nosinit.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/nosinit/nosinit.c new file mode 100644 index 00000000..38dcd197 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/nosinit/nosinit.c @@ -0,0 +1,74 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file nosinit.c + * @author MCU Driver Team + * @brief nos init module. + * @details nos initialization function during startup + */ + +#ifdef NOS_TASK_SUPPORT +#include "nos_task.h" +#include "nosinit.h" +#include "systick.h" +#include "crg.h" + +#ifndef CFG_NOS_MAINTASK_STACKSIZE +#define CFG_NOS_MAINTASK_STACKSIZE 0x500 +#endif +#define CYCCLE_PERUS 200 +// User define the stack size of main task by CFG_NOS_MAINTASK_STACKSIZE +unsigned char __attribute__((aligned(16))) g_taskMainStackSpace[CFG_NOS_MAINTASK_STACKSIZE]; + +static unsigned int g_nosSysFreq; +// Get tick in real time +static unsigned long long NOS_GetTick() +{ + unsigned int cycle, cycleh; + asm volatile("csrr %0, cycle" : "=r"(cycle)); + asm volatile("csrr %0, cycleh" : "=r"(cycleh)); + unsigned long long longCycle = (unsigned long long)cycle + (unsigned long long)cycleh * 0xFFFFFFFF; + // tick = cycle/freq + return longCycle / g_nosSysFreq; +} + +/** + * @brief Init the Nos Task Schedule + * @param None + * @retval None + */ +void NOS_Init(void) +{ + unsigned int taskId; + NOS_SysConfig config = {}; + g_nosSysFreq = SYSTICK_GetCRGHZ() / CRG_FREQ_1MHz * CFG_SYSTICK_TICKINTERVAL_US; + config.usecPerTick = SYSTICK_GetTickInterval(); /* Set the tick size of Nos task schedule */ + config.getTickFunc = NOS_GetTick; + config.cyclePerUs = CYCCLE_PERUS; + NOS_TaskInit(&config); + NOS_TaskInitParam param = {}; + param.name = "mainTask"; + param.taskEntry = (NOS_TaskEntryFunc)main; /* Set the entry function by user define */ + param.param = 0; + param.priority = NOS_TASK_PRIORITY_LOWEST; + param.stackAddr = g_taskMainStackSpace; + param.stackSize = sizeof(g_taskMainStackSpace); + param.privateData = 0; + (void)NOS_TaskCreate(¶m, &taskId); + (void)NOS_StartScheduler(); /* Nos task schedule start */ +} +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/nosinit/nosinit.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/nosinit/nosinit.h new file mode 100644 index 00000000..81c83b43 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/nosinit/nosinit.h @@ -0,0 +1,26 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file nosinit.h + * @author MCU Driver Team + * @brief nos init module. + * @details nos initialization function during startup + */ + +#ifdef NOS_TASK_SUPPORT +int main(void); +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/pgainit/pgainit.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/pgainit/pgainit.c new file mode 100644 index 00000000..9bf1367a --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/pgainit/pgainit.c @@ -0,0 +1,37 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pgainit.c + * @author MCU Driver Team + * @brief pga init module. + * @details pga initialization function during startup + */ +#include "fotp_info_read.h" +#include "pga_ip.h" +#include "pgainit.h" + +void PGA_InitVref(void) +{ + FOTP_INFO_RGN0_NUMBER_31 trimPga; + + FOTP_InfoGet(FOTP_INFO_RNG0, 31, &trimPga.comData); /* 31 is the number of pga_vref in otp */ + if (g_trimEnable == true) { /* if trim enable */ + PGA0->PGA_CTRL1.BIT.pga_trim_ofstp = trimPga.REG.data0.pga0_poffset_trim; + PGA1->PGA_CTRL1.BIT.pga_trim_ofstp = trimPga.REG.data0.pga1_poffset_trim; + PGA2->PGA_CTRL1.BIT.pga_trim_ofstp = trimPga.REG.data0.pga2_poffset_trim; + } +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/pgainit/pgainit.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/pgainit/pgainit.h new file mode 100644 index 00000000..23a075c1 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/pgainit/pgainit.h @@ -0,0 +1,30 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pgainit.h + * @author MCU Driver Team + * @brief pga init module. + * @details pga initialization function during startup + */ + +#ifndef McuMagicTag_PGAINIT_H +#define McuMagicTag_PGAINIT_H + +extern bool g_trimEnable; + +void PGA_InitVref(void); +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/pmcinit/pmcinit.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/pmcinit/pmcinit.c new file mode 100644 index 00000000..48c2e4a2 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/pmcinit/pmcinit.c @@ -0,0 +1,35 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pmcinit.c + * @author MCU Driver Team + * @brief pmc init module. + * @details pmc initialization function during startup + */ +#include "fotp_info_read.h" +#include "pmc_ip.h" +#include "pmcinit.h" + +void PMC_InitVref(void) +{ + FOTP_INFO_RGN0_NUMBER_21 trimPmc; + + if (g_trimEnable == true) { /* if trim enable */ + FOTP_InfoGet(FOTP_INFO_RNG0, 21, &trimPmc.comData); /* 21 is the number of pmc_vref in otp */ + PMC->PMU_CLDO.BIT.pmu_cldo_trim = trimPmc.REG.data0.pmu_cldo_trim; + } +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/pmcinit/pmcinit.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/pmcinit/pmcinit.h new file mode 100644 index 00000000..ff972c42 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/pmcinit/pmcinit.h @@ -0,0 +1,29 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pmcinit.h + * @author MCU Driver Team + * @brief pmc init module. + * @details pmc initialization function during startup + */ +#ifndef McuMagicTag_PMC_INIT_H +#define McuMagicTag_PMC_INIT_H + +extern bool g_trimEnable; +void PMC_InitVref(void); + +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/systickinit/systickinit.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/systickinit/systickinit.c new file mode 100644 index 00000000..7f641067 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/systickinit/systickinit.c @@ -0,0 +1,125 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file systickinit.c + * @author MCU Driver Team + * @brief systick init module. + * @details systick initialization function during startup + */ +#include "baseaddr.h" +#include "timer.h" +#include "systick.h" +#include "systickinit.h" +#include "crg.h" + +TIMER_Handle g_systickHandle; + +#ifdef NOS_TASK_SUPPORT +#include "interrupt.h" +#include "systick.h" +#define NOS_TickPostDispatch OsHwiDispatchTick + +void SYSTICK_Default_Callback(void) +{ + /* The default systick callback when using th nos task */ + HAL_TIMER_IrqClear(&g_systickHandle); + NOS_TickPostDispatch(); +} + +void SYSTICK_IRQ_Enable(void) +{ + /* When Support NOS Task, Need to open the TickIRQ, us per tick will to update the load */ + g_systickHandle.irqNum = IRQ_TIMER3; + g_systickHandle.interruptEn = BASE_CFG_ENABLE; + HAL_TIMER_RegisterCallback(&g_systickHandle, SYSTICK_Default_Callback); + HAL_TIMER_Config(&g_systickHandle, TIMER_CFG_INTERRUPT); // enable the systickIRQ + IRQ_SetPriority(g_systickHandle.irqNum, 1); + IRQ_EnableN(IRQ_TIMER3); +} + +unsigned int SYSTICK_GetTickInterval(void) +{ + /* Get the tick interval(the number of usecond per tick) */ + return CFG_SYSTICK_TICKINTERVAL_US; +} + +static inline unsigned int DCL_GetCpuCycle() +{ + /* Get the Cpu Cycle Register(CSR) */ + unsigned int cycle; + asm volatile("csrr %0, cycle" : "=r"(cycle)); + + return cycle; +} +#endif + +unsigned int SYSTICK_GetCRGHZ(void) +{ + /* Get the Systick IP */ +#ifdef NOS_TASK_SUPPORT + return HAL_CRG_GetCoreClkFreq(); +#else + return HAL_CRG_GetIpFreq(SYSTICK_BASE); +#endif +} + +unsigned int DCL_SYSTICK_GetTick(void) +{ +#ifdef NOS_TASK_SUPPORT + /* Return the load value(period) and the counter value, make the returned counter in count up mode */ + return DCL_GetCpuCycle(); +#else + /* Invert the counter value, make the returned counter in count up mode */ + return ~SYSTICK->timer_value; +#endif +} + +unsigned int SYSTICK_GetTimeStampUs(void) +{ + /* Get the systick timestamp(convert from the systick value) */ + return DCL_SYSTICK_GetTick() / (SYSTICK_GetCRGHZ() / CRG_FREQ_1MHz); +} + +/** + * @brief Init the systick + * @param None + * @retval None + */ +void SYSTICK_Init() +{ + /* Choose the config to support GetTick and Delay */ + g_systickHandle.baseAddress = SYSTICK; +#ifdef NOS_TASK_SUPPORT + /* Change the period load to the user defined usecond */ + g_systickHandle.load = (HAL_CRG_GetIpFreq(SYSTICK_BASE) / CRG_FREQ_1MHz) * CFG_SYSTICK_TICKINTERVAL_US; + g_systickHandle.bgLoad = (HAL_CRG_GetIpFreq(SYSTICK_BASE) / CRG_FREQ_1MHz) * CFG_SYSTICK_TICKINTERVAL_US; +#else + g_systickHandle.load = SYSTICK_MAX_VALUE; + g_systickHandle.bgLoad = SYSTICK_MAX_VALUE; +#endif + g_systickHandle.mode = TIMER_MODE_RUN_PERIODIC; + g_systickHandle.prescaler = TIMERPRESCALER_NO_DIV; + g_systickHandle.size = TIMER_SIZE_32BIT; + /* Don't Support IRQ because only needs to read the value of systick */ + g_systickHandle.interruptEn = BASE_CFG_DISABLE; + HAL_TIMER_Init(&g_systickHandle); +#ifdef NOS_TASK_SUPPORT + /* Support IRQ to upload the totalCycle and detect the timeout lists */ + SYSTICK_IRQ_Enable(); +#endif + HAL_TIMER_Start(&g_systickHandle); +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/systickinit/systickinit.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/systickinit/systickinit.h new file mode 100644 index 00000000..7b7b1e0e --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/chipinit/systickinit/systickinit.h @@ -0,0 +1,29 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file systickinit.h + * @author MCU Driver Team + * @brief systick init module. + * @details systick initialization function during startup + */ + +#ifndef McuMagicTag_SYSTICKINIT_H +#define McuMagicTag_SYSTICKINIT_H + +void SYSTICK_Init(void); + +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/flash.lds b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/flash.lds new file mode 100644 index 00000000..ba463972 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/flash.lds @@ -0,0 +1,201 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file flash.lds + * @author MCU Application Driver Team + * @brief RISCV flash link script + */ + +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +SRAM_START = 0x4000000; +SRAM_END = 0x4000000 + 16K; + +/* USER CODE BEGIN 0 */ +/* USER CODE 区域内代码不会被覆盖，区域外会被生成的默认代码覆盖（其余USER CODE 区域同理） */ +/* USER CODE END 0 */ + +RAM_CODE_START = 0x2000000; +RAM_CODE_SIZE = 0; + +RAM_RESERVE_DATA_START = SRAM_START + RAM_CODE_SIZE; +RAM_RESERVE_DATA_SIZE = 0; + +RAM_DIAGNOSE_BUF_START = RAM_RESERVE_DATA_START + RAM_RESERVE_DATA_SIZE; +RAM_DIAGNOSE_BUF_SIZE = 0x20; + +STACK_SRAM_BOUND_SIZE = 0x10; + +RAM_START = RAM_RESERVE_DATA_START + RAM_RESERVE_DATA_SIZE + RAM_DIAGNOSE_BUF_SIZE; +RAM_SIZE = 10K - RAM_CODE_SIZE - RAM_RESERVE_DATA_SIZE - RAM_DIAGNOSE_BUF_SIZE - STACK_SRAM_BOUND_SIZE; +RAM_END = SRAM_END; + +STACK_SRAM_BOUND_START = RAM_START + RAM_SIZE; +STACK_START = STACK_SRAM_BOUND_START + STACK_SRAM_BOUND_SIZE; + +NMI_STACK_SIZE = 1024; +STACK_SIZE = 6144 - NMI_STACK_SIZE; +INIT_STACK_SIZE = 1024; + +FLASH_START = 0x3000000; +FLASH_SIZE = 152K - 4; + +MEMORY +{ + /* ram for code */ + RAM_CODE(xr) : ORIGIN = RAM_CODE_START, LENGTH = RAM_CODE_SIZE + + /* ram for reserved data */ + RAM_RESERVE_DATA(rw) : ORIGIN = RAM_RESERVE_DATA_START, LENGTH = RAM_RESERVE_DATA_SIZE + + /* ram for diagnose buf */ + RAM_DIAGNOSE_BUF(rw) : ORIGIN = RAM_DIAGNOSE_BUF_START, LENGTH = RAM_DIAGNOSE_BUF_SIZE + + /* ram for common bss and data */ + RAM_DATA(xrw) : ORIGIN = RAM_START, LENGTH = RAM_SIZE + + /* ram for common bss and data */ + STACK_SRAM_BOUND(xrw) : ORIGIN = STACK_SRAM_BOUND_START, LENGTH = STACK_SRAM_BOUND_SIZE + + /* ram for stack */ + RAM_STACK(xrw) : ORIGIN = STACK_START, LENGTH = STACK_SIZE + NMI_STACK_SIZE + + /*magic number */ + FLASH_MAGIC(rw) : ORIGIN = FLASH_START, LENGTH = 4 + + /* ram for target */ + FLASH_CODE(rx) : ORIGIN = FLASH_START + 4, LENGTH = FLASH_SIZE + +/* USER CODE BEGIN 1 */ +/* USER CODE 区域内代码不会被覆盖，区域外会被生成的默认代码覆盖（其余USER CODE 区域同理） */ +/* USER CODE END 1 */ +} + +SECTIONS +{ + /* The startup code goes first into FLASH */ + .data.magic : ALIGN(4) + { + KEEP(*(.data.magic)) + } > FLASH_MAGIC + + /* The startup code goes first into FLASH_CODE */ + .text.entry : ALIGN(4) + { + KEEP(*(.text.entry)) + } > FLASH_CODE + + /* Stack in SRAM at Highest addresses */ + .stacks (NOLOAD) : + { + . = ALIGN(4); + __SYSTEM_STACK_BEGIN__ = ORIGIN(RAM_STACK); + KEEP(*(.stacks)) + __SYSTEM_STACK_END__ = ORIGIN(RAM_STACK) + STACK_SIZE; + . = ALIGN(0x20); + __INTERRUPT_STACK_BEGIN__ = __SYSTEM_STACK_END__; + . = ALIGN(0x20); + __NMI_STACK_BEGIN__ = __SYSTEM_STACK_END__; + __nmi_stack_bottom = .; + . += NMI_STACK_SIZE; + __nmi_stack_top = .; + } > RAM_STACK + __stack_top = __SYSTEM_STACK_END__; + __init_stack_top = __SYSTEM_STACK_BEGIN__ + INIT_STACK_SIZE; + __irq_stack_top = __SYSTEM_STACK_END__; + + .text.sram : ALIGN(4) + { + __sram_code_load = LOADADDR(.text.sram); + __sram_code_start = .; + *(.text.sram) + . = ALIGN(4); + __sram_code_end = .; + } > RAM_CODE AT > FLASH_CODE + + .reserved.data : ALIGN(4) + { + __reserved_code_load_addr = LOADADDR(.reserved.data); + __reserved_code_start_addr = .; + *(.reserved.data*) + . = ALIGN(4); + __reserved_code_end_addr = .; + } > RAM_RESERVE_DATA AT > FLASH_CODE + + .text : ALIGN(4) + { + __start_addr = .; + *(.text*) + *(.ram.text*) + . = ALIGN(4); + __rodata_start = .; + *(.rodata*) + . = ALIGN(4); + __rodata_end = .; + *(.got*) + __text_end = .; + } > FLASH_CODE + + /* data section */ + .data : ALIGN(4) + { + __data_load = LOADADDR(.data); + __data_start = .; + *(.data*) + . = ALIGN(4); + __data_end = .; + } > RAM_DATA AT> FLASH_CODE + __data_size = __data_end - __data_start; + + .stackBound : ALIGN(4) + { + __stack_sram_bound_data_load = LOADADDR(.stackBound); + __stack_sram_bound_data_start = .; + *(STACK_SRAM_BOUND) + . = ALIGN(4); + __stack_sram_bound_data_end = .; + } > STACK_SRAM_BOUND AT> FLASH_CODE + + .checkSum (NOLOAD) : ALIGN(4) + { + __checksum_addr = .; + *(CHECKSUM) + __checksum_end = .; + } > FLASH_CODE + + /* bss section */ + .bss (NOLOAD) : ALIGN(4) + { + __bss_begin__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM_DATA + __bss_size__ = __bss_end__ - __bss_begin__; + __global_pointer$ = __data_start + ((__data_size + __bss_size__) / 2); + + .ramBuf (NOLOAD) : ALIGN(4) + { + *(RAM_DIAGNOSE_BUF) + } > RAM_DIAGNOSE_BUF + +/* USER CODE BEGIN 2 */ +/* USER CODE 区域内代码不会被覆盖，区域外会被生成的默认代码覆盖（其余USER CODE 区域同理） */ +/* USER CODE END 2 */ +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/fotp/fotp.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/fotp/fotp.h new file mode 100644 index 00000000..59b693fe --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/fotp/fotp.h @@ -0,0 +1,792 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file fotp.h + * @author MCU Driver Team + * @brief This file provides firmware functions to manage the following + * functionalities of the system control register. + * + Register Struct of FOTP RNG0 and FOTP RNG1 + */ +#ifndef McuMagicTag_FOTP_H +#define McuMagicTag_FOTP_H + +#define FOTP_INFO_REG_MAX_ID 511 /* Max index of fotp info rng 0 and rng 1 */ + +typedef enum { + FOTP_INFO_RNG0, + FOTP_INFO_RNG1, + FOTP_INFO_MAXTYPE, +} FOTP_InfoRngType; + +typedef struct { + unsigned int data[4]; +} FOTP_CommonData; + +/* + * FOTP INFO RNG0 + */ +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int DIEID_STD_VER : 3; + unsigned int LOTID0 : 6; + unsigned int LOTID1 : 6; + unsigned int LOTID2 : 6; + unsigned int LOTID3 : 6; + unsigned int LOTID4 : 5; + } data0; + struct { + unsigned int LOTID4 : 1; + unsigned int LOTID5 : 6; + unsigned int WAFERID : 5; + unsigned int DIEX : 8; + unsigned int DIEY : 8; + unsigned int reserved : 4; + } data1; + unsigned int reserved; + struct { + unsigned int ts_ref_t0_cp_rt : 11; + unsigned int ts_ref_v0_cp_rt : 11; + unsigned int reserved : 2; + unsigned int CRC8_CP_RT : 8; + } data3; + } REG; +} FOTP_INFO_RGN0_NUMBER_0; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int YEAR : 6; + unsigned int MON : 4; + unsigned int DAY : 5; + unsigned int HOUR : 5; + unsigned int MIN : 6; + unsigned int SEC : 6; + } data0; + unsigned int reserved; + struct { + unsigned int reserved : 10; + unsigned int losc_ctrim_ft_rt : 8; + unsigned int hosc_ctrim_ft_rt : 9; + unsigned int SITE_NUM_FT : 5; + } data2; + struct { + unsigned int ts_ref_t0_ft_rt : 11; + unsigned int ts_ref_v0_ft_rt : 11; + unsigned int reserved : 10; + } data3; + } REG; +} FOTP_INFO_RGN0_NUMBER_1; + +typedef union { + FOTP_CommonData comData; + struct { + unsigned int chip_id; + unsigned int reserved; + struct { + unsigned int version_id : 8; + unsigned int reserved : 24; + } data2; + unsigned int customer_id; + } REG; +} FOTP_INFO_RGN0_NUMBER_2; + +typedef union { + FOTP_CommonData comData; + struct { + unsigned int fotp_empty_flag; + unsigned int reserved[3]; + } REG; +} FOTP_INFO_RGN0_NUMBER_4; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int info_rgn0_unlock : 1; + unsigned int reserved : 31; + } data0; + unsigned int reserved[3]; + } REG; +} FOTP_INFO_RGN0_NUMBER_5; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int bootrom_debug_enable : 1; + unsigned int reserved : 31; + } data0; + struct { + unsigned int bootrom_hide_disable : 1; + unsigned int reserved : 31; + } data1; + struct { + unsigned int ef_bist_jtag_enable : 1; + unsigned int reserved : 31; + } data2; + unsigned int reserved; + } REG; +} FOTP_INFO_RGN0_NUMBER_6; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int cpu_fpu_enable : 1; + unsigned int sysram_size_cfg : 1; + unsigned int eflash_size_cfg : 1; + unsigned int cpu_maxfreq_cfg : 1; + unsigned int reserved : 28; + } data0; + unsigned int reserved[3]; + } REG; +} FOTP_INFO_RGN0_NUMBER_7; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int adc0_enable : 1; + unsigned int adc1_enable : 1; + unsigned int adc2_enable : 1; + unsigned int reserved : 29; + } data0; + struct { + unsigned int pga0_enable : 1; + unsigned int pga1_enable : 1; + unsigned int pga2_enable : 1; + unsigned int reserved : 29; + } data1; + struct { + unsigned int dac0_enable : 1; + unsigned int dac1_enable : 1; + unsigned int dac2_enable : 1; + unsigned int reserved : 29; + } data2; + struct { + unsigned int acmp0_enable : 1; + unsigned int acmp1_enable : 1; + unsigned int acmp2_enable : 1; + unsigned int reserved : 29; + } data3; + } REG; +} FOTP_INFO_RGN0_NUMBER_8; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int apt0_enable : 1; + unsigned int apt1_enable : 1; + unsigned int apt2_enable : 1; + unsigned int apt3_enable : 1; + unsigned int apt4_enable : 1; + unsigned int apt5_enable : 1; + unsigned int apt6_enable : 1; + unsigned int apt7_enable : 1; + unsigned int apt8_enable : 1; + unsigned int reserved : 23; + } data0; + unsigned int reserved[3]; + } REG; +} FOTP_INFO_RGN0_NUMBER_9; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int IDDQ_DVDD : 8; + unsigned int IDDQ_AVDD : 8; + unsigned int reserved : 16; + } data0; + unsigned int reserved[3]; + } REG; +} FOTP_INFO_RGN0_NUMBER_10; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int hpm_core : 16; + unsigned int reserved : 16; + } data0; + unsigned int reserved[3]; + } REG; +} FOTP_INFO_RGN0_NUMBER_11; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int PASSFLAG_CP_RT : 1; + unsigned int reserved : 31; + } data0; + unsigned int reserved[3]; + } REG; +} FOTP_INFO_RGN0_NUMBER_13; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int ts_ref_t0_ft_ht : 11; + unsigned int ts_ref_v0_ft_ht : 11; + unsigned int reserved : 10; + } data0; + struct { + unsigned int pmu_bg_vo_h00_ht : 12; + unsigned int pmu_bg_vo_h1f_ht : 12; + unsigned int adcvref_bg_vo_h00_ht : 8; + } data1; + struct { + unsigned int adcvref_bg_vo_h00_ht : 4; + unsigned int adcvref_bg_vo_h08_ht : 12; + unsigned int adcvref_bg_vo_h10_ht : 12; + unsigned int adcvref_bg_vo_h18_ht : 4; + } data2; + struct { + unsigned int adcvref_bg_vo_h18_ht : 8; + unsigned int adcvref_bg_vo_h1f_ht : 12; + unsigned int reserved : 4; + unsigned int CRC8_FT_RT : 8; + } data3; + } REG; +} FOTP_INFO_RGN0_NUMBER_15; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int PASSFLAG_FT_HT : 1; + unsigned int reserved : 31; + } data0; + unsigned int reserved[3]; + } REG; +} FOTP_INFO_RGN0_NUMBER_16; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int DVS_FLOW_FLAG : 1; + unsigned int DVS_PASS_FLAG : 1; + unsigned int reserved : 30; + } data0; + unsigned int reserved[3]; + } REG; +} FOTP_INFO_RGN0_NUMBER_17; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int FAILFLAG_ALL : 2; + unsigned int reserved : 30; + } data0; + unsigned int reserved[3]; + } REG; +} FOTP_INFO_RGN0_NUMBER_18; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int PASSFLAG_FT_RT : 1; + unsigned int reserved : 31; + } data0; + unsigned int reserved[3]; + } REG; +} FOTP_INFO_RGN0_NUMBER_19; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int pmu_bg_vo_h00_rt : 12; + unsigned int pmu_bg_vo_h1f_rt : 12; + unsigned int adcvref_bg_vo_h00_rt : 8; + } data0; + struct { + unsigned int adcvref_bg_vo_h00_rt : 4; + unsigned int adcvref_bg_vo_h08_rt : 12; + unsigned int adcvref_bg_vo_h10_rt : 12; + unsigned int adcvref_bg_vo_h18_rt : 4; + } data1; + struct { + unsigned int adcvref_bg_vo_h18_rt : 8; + unsigned int adcvref_bg_vo_h1f_rt : 12; + unsigned int reserved : 12; + } data2; + unsigned int reserved; + } REG; +} FOTP_INFO_RGN0_NUMBER_20; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int pmu_bg_trim : 5; + unsigned int pmu_aoldo_trim : 5; + unsigned int pmu_cldo_trim : 4; + unsigned int reserved : 18; + } data0; + struct { + unsigned int adcvref_bg_trim : 5; + unsigned int adcvref_adcldo_trim : 5; + unsigned int reserved : 22; + } data1; + struct { + unsigned int adcvref_refbuf0_trim_2p0v : 5; + unsigned int adcvref_refbuf1_trim_2p0v : 5; + unsigned int adcvref_refbuf2_trim_2p0v : 5; + unsigned int reserved : 17; + } data2; + struct { + unsigned int adcvref_refbuf0_trim_2p5v : 5; + unsigned int adcvref_refbuf1_trim_2p5v : 5; + unsigned int adcvref_refbuf2_trim_2p5v : 5; + unsigned int reserved : 17; + } data3; + } REG; +} FOTP_INFO_RGN0_NUMBER_21; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int adc0_sh0_g0p6_ge_trim : 13; + unsigned int adc0_sh0_g0p6_oe_trim : 14; + unsigned int adc0_sh0_g0p6_trim_1d8 : 5; + } data0; + struct { + unsigned int adc0_sh0_g0p6_trim_1d8 : 2; + unsigned int adc0_sh0_g0p6_trim_7d8 : 7; + unsigned int adc0_sh0_g0p6_trim_3d8 : 7; + unsigned int adc0_sh0_g0p6_trim_4d8 : 7; + unsigned int adc0_sh0_g0p6_trim_5d8 : 7; + unsigned int reserved : 2; + } data1; + struct { + unsigned int adc0_sh0_g0p75_ge_trim : 13; + unsigned int adc0_sh0_g0p75_oe_trim : 14; + unsigned int adc0_sh0_g0p75_trim_1d8 : 5; + } data2; + struct { + unsigned int adc0_sh0_g0p75_trim_1d8 : 2; + unsigned int adc0_sh0_g0p75_trim_7d8 : 7; + unsigned int adc0_sh0_g0p75_trim_3d8 : 7; + unsigned int adc0_sh0_g0p75_trim_4d8 : 7; + unsigned int adc0_sh0_g0p75_trim_5d8 : 7; + unsigned int reserved : 2; + } data3; + } REG; +} FOTP_INFO_RGN0_NUMBER_22; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int adc0_sh1_g0p6_ge_trim : 13; + unsigned int adc0_sh1_g0p6_oe_trim : 14; + unsigned int adc0_sh1_g0p6_trim_1d8 : 5; + } data0; + struct { + unsigned int adc0_sh1_g0p6_trim_1d8 : 2; + unsigned int adc0_sh1_g0p6_trim_7d8 : 7; + unsigned int adc0_sh1_g0p6_trim_3d8 : 7; + unsigned int adc0_sh1_g0p6_trim_4d8 : 7; + unsigned int adc0_sh1_g0p6_trim_5d8 : 7; + unsigned int reserved : 2; + } data1; + struct { + unsigned int adc0_sh1_g0p75_ge_trim : 13; + unsigned int adc0_sh1_g0p75_oe_trim : 14; + unsigned int adc0_sh1_g0p75_trim_1d8 : 5; + } data2; + struct { + unsigned int adc0_sh1_g0p75_trim_1d8 : 2; + unsigned int adc0_sh1_g0p75_trim_7d8 : 7; + unsigned int adc0_sh1_g0p75_trim_3d8 : 7; + unsigned int adc0_sh1_g0p75_trim_4d8 : 7; + unsigned int adc0_sh1_g0p75_trim_5d8 : 7; + unsigned int reserved : 2; + } data3; + } REG; +} FOTP_INFO_RGN0_NUMBER_23; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int adc1_sh0_g0p6_ge_trim : 13; + unsigned int adc1_sh0_g0p6_oe_trim : 14; + unsigned int adc1_sh0_g0p6_trim_1d8 : 5; + } data0; + struct { + unsigned int adc1_sh0_g0p6_trim_1d8 : 2; + unsigned int adc1_sh0_g0p6_trim_7d8 : 7; + unsigned int adc1_sh0_g0p6_trim_3d8 : 7; + unsigned int adc1_sh0_g0p6_trim_4d8 : 7; + unsigned int adc1_sh0_g0p6_trim_5d8 : 7; + unsigned int reserved : 2; + } data1; + struct { + unsigned int adc1_sh0_g0p75_ge_trim : 13; + unsigned int adc1_sh0_g0p75_oe_trim : 14; + unsigned int adc1_sh0_g0p75_trim_1d8 : 5; + } data2; + struct { + unsigned int adc1_sh0_g0p75_trim_1d8 : 2; + unsigned int adc1_sh0_g0p75_trim_7d8 : 7; + unsigned int adc1_sh0_g0p75_trim_3d8 : 7; + unsigned int adc1_sh0_g0p75_trim_4d8 : 7; + unsigned int adc1_sh0_g0p75_trim_5d8 : 7; + unsigned int reserved : 2; + } data3; + } REG; +} FOTP_INFO_RGN0_NUMBER_24; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int adc1_sh1_g0p6_ge_trim : 13; + unsigned int adc1_sh1_g0p6_oe_trim : 14; + unsigned int adc1_sh1_g0p6_trim_1d8 : 5; + } data0; + struct { + unsigned int adc1_sh1_g0p6_trim_1d8 : 2; + unsigned int adc1_sh1_g0p6_trim_7d8 : 7; + unsigned int adc1_sh1_g0p6_trim_3d8 : 7; + unsigned int adc1_sh1_g0p6_trim_4d8 : 7; + unsigned int adc1_sh1_g0p6_trim_5d8 : 7; + unsigned int reserved : 2; + } data1; + struct { + unsigned int adc1_sh1_g0p75_ge_trim : 13; + unsigned int adc1_sh1_g0p75_oe_trim : 14; + unsigned int adc1_sh1_g0p75_trim_1d8 : 5; + } data2; + struct { + unsigned int adc1_sh1_g0p75_trim_1d8 : 2; + unsigned int adc1_sh1_g0p75_trim_7d8 : 7; + unsigned int adc1_sh1_g0p75_trim_3d8 : 7; + unsigned int adc1_sh1_g0p75_trim_4d8 : 7; + unsigned int adc1_sh1_g0p75_trim_5d8 : 7; + unsigned int reserved : 2; + } data3; + } REG; +} FOTP_INFO_RGN0_NUMBER_25; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int adc2_sh0_g0p6_ge_trim : 13; + unsigned int adc2_sh0_g0p6_oe_trim : 14; + unsigned int adc2_sh0_g0p6_trim_1d8 : 5; + } data0; + struct { + unsigned int adc2_sh0_g0p6_trim_1d8 : 2; + unsigned int adc2_sh0_g0p6_trim_7d8 : 7; + unsigned int adc2_sh0_g0p6_trim_3d8 : 7; + unsigned int adc2_sh0_g0p6_trim_4d8 : 7; + unsigned int adc2_sh0_g0p6_trim_5d8 : 7; + unsigned int reserved : 2; + } data1; + struct { + unsigned int adc2_sh0_g0p75_ge_trim : 13; + unsigned int adc2_sh0_g0p75_oe_trim : 14; + unsigned int adc2_sh0_g0p75_trim_1d8 : 5; + } data2; + struct { + unsigned int adc2_sh0_g0p75_trim_1d8 : 2; + unsigned int adc2_sh0_g0p75_trim_7d8 : 7; + unsigned int adc2_sh0_g0p75_trim_3d8 : 7; + unsigned int adc2_sh0_g0p75_trim_4d8 : 7; + unsigned int adc2_sh0_g0p75_trim_5d8 : 7; + unsigned int reserved : 2; + } data3; + } REG; +} FOTP_INFO_RGN0_NUMBER_26; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int adc2_sh1_g0p6_ge_trim : 13; + unsigned int adc2_sh1_g0p6_oe_trim : 14; + unsigned int adc2_sh1_g0p6_trim_1d8 : 5; + } data0; + struct { + unsigned int adc2_sh1_g0p6_trim_1d8 : 2; + unsigned int adc2_sh1_g0p6_trim_7d8 : 7; + unsigned int adc2_sh1_g0p6_trim_3d8 : 7; + unsigned int adc2_sh1_g0p6_trim_4d8 : 7; + unsigned int adc2_sh1_g0p6_trim_5d8 : 7; + unsigned int reserved : 2; + } data1; + struct { + unsigned int adc2_sh1_g0p75_ge_trim : 13; + unsigned int adc2_sh1_g0p75_oe_trim : 14; + unsigned int adc2_sh1_g0p75_trim_1d8 : 5; + } data2; + struct { + unsigned int adc2_sh1_g0p75_trim_1d8 : 2; + unsigned int adc2_sh1_g0p75_trim_7d8 : 7; + unsigned int adc2_sh1_g0p75_trim_3d8 : 7; + unsigned int adc2_sh1_g0p75_trim_4d8 : 7; + unsigned int adc2_sh1_g0p75_trim_5d8 : 7; + unsigned int reserved : 2; + } data3; + } REG; +} FOTP_INFO_RGN0_NUMBER_27; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int pga0_g1_error_trim_v0 : 8; + unsigned int pga0_g1_error_trim_v1 : 8; + unsigned int pga0_g1_error_trim_v2 : 8; + unsigned int pga0_g2_error_trim_v0 : 8; + } data0; + struct { + unsigned int pga0_g2_error_trim_v1 : 8; + unsigned int pga0_g2_error_trim_v2 : 8; + unsigned int pga0_g4_error_trim_v0 : 8; + unsigned int pga0_g4_error_trim_v1 : 8; + } data1; + struct { + unsigned int pga0_g4_error_trim_v2 : 8; + unsigned int pga0_g8_error_trim_v0 : 8; + unsigned int pga0_g8_error_trim_v1 : 8; + unsigned int pga0_g8_error_trim_v2 : 8; + } data2; + struct { + unsigned int pga0_g16_error_trim_v0 : 8; + unsigned int pga0_g16_error_trim_v1 : 8; + unsigned int pga0_g16_error_trim_v2 : 8; + unsigned int reserved : 8; + } data3; + } REG; +} FOTP_INFO_RGN0_NUMBER_28; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int pga1_g1_error_trim_v0 : 8; + unsigned int pga1_g1_error_trim_v1 : 8; + unsigned int pga1_g1_error_trim_v2 : 8; + unsigned int pga1_g2_error_trim_v0 : 8; + } data0; + struct { + unsigned int pga1_g2_error_trim_v1 : 8; + unsigned int pga1_g2_error_trim_v2 : 8; + unsigned int pga1_g4_error_trim_v0 : 8; + unsigned int pga1_g4_error_trim_v1 : 8; + } data1; + struct { + unsigned int pga1_g4_error_trim_v2 : 8; + unsigned int pga1_g8_error_trim_v0 : 8; + unsigned int pga1_g8_error_trim_v1 : 8; + unsigned int pga1_g8_error_trim_v2 : 8; + } data2; + struct { + unsigned int pga1_g16_error_trim_v0 : 8; + unsigned int pga1_g16_error_trim_v1 : 8; + unsigned int pga1_g16_error_trim_v2 : 8; + unsigned int reserved : 8; + } data3; + } REG; +} FOTP_INFO_RGN0_NUMBER_29; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int pga2_g1_error_trim_v0 : 8; + unsigned int pga2_g1_error_trim_v1 : 8; + unsigned int pga2_g1_error_trim_v2 : 8; + unsigned int pga2_g2_error_trim_v0 : 8; + } data0; + struct { + unsigned int pga2_g2_error_trim_v1 : 8; + unsigned int pga2_g2_error_trim_v2 : 8; + unsigned int pga2_g4_error_trim_v0 : 8; + unsigned int pga2_g4_error_trim_v1 : 8; + } data1; + struct { + unsigned int pga2_g4_error_trim_v2 : 8; + unsigned int pga2_g8_error_trim_v0 : 8; + unsigned int pga2_g8_error_trim_v1 : 8; + unsigned int pga2_g8_error_trim_v2 : 8; + } data2; + struct { + unsigned int pga2_g16_error_trim_v0 : 8; + unsigned int pga2_g16_error_trim_v1 : 8; + unsigned int pga2_g16_error_trim_v2 : 8; + unsigned int reserved : 8; + } data3; + } REG; +} FOTP_INFO_RGN0_NUMBER_30; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int pga0_poffset_trim : 5; + unsigned int pga0_noffset_trim : 5; + unsigned int pga1_poffset_trim : 5; + unsigned int pga1_noffset_trim : 5; + unsigned int pga2_poffset_trim : 5; + unsigned int pga2_noffset_trim : 5; + unsigned int reserved : 2; + } data0; + struct { + unsigned int reserved : 15; + unsigned int CRC8_P1_RT_FT : 8; + unsigned int CRC8_P2_RT_FT : 8; + unsigned int reserved1 : 1; + } data1; + unsigned int reserved[2]; + } REG; +} FOTP_INFO_RGN0_NUMBER_31; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int DIEX : 8; + unsigned int DIEY : 8; + unsigned int WAFERID : 8; + unsigned int LOTID0 : 8; + } data0; + struct { + unsigned int LOTID1 : 8; + unsigned int LOTID2 : 8; + unsigned int LOTID3 : 8; + unsigned int LOTID4 : 8; + } data1; + struct { + unsigned int LOTID5 : 8; + unsigned int PASSFLAG_RT_CPB : 1; + unsigned int PASSFLAG_RT_FTC : 1; + unsigned int reserved : 22; + } data2; + unsigned int reserved; + } REG; +} FOTP_INFO_RGN0_NUMBER_507; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int ef_cp1_stress_flag : 16; + unsigned int reserved : 16; + } data0; + unsigned int reserved[3]; + } REG; +} FOTP_INFO_RGN0_NUMBER_508; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int ef_cp2_dr_flag : 16; + unsigned int reserved : 16; + } data0; + unsigned int reserved[3]; + } REG; +} FOTP_INFO_RGN0_NUMBER_509; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int ef_cp2_gdr : 16; + unsigned int reserved : 16; + } data0; + unsigned int reserved[3]; + } REG; +} FOTP_INFO_RGN0_NUMBER_510; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int ef_cp1_gdr : 16; + unsigned int reserved : 16; + } data0; + unsigned int reserved[3]; + } REG; +} FOTP_INFO_RGN0_NUMBER_511; + +/* + * FOTP INFO RNG1 + */ +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int lifecycle_status : 1; + unsigned int reserved : 31; + } data0; + unsigned int reserved[3]; + } REG; +} FOTP_INFO_RGN1_NUMBER_0; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int uart0_enable : 1; + unsigned int uart1_enable : 1; + unsigned int uart2_enable : 1; + unsigned int reserved : 29; + } data0; + struct { + unsigned int func_jtag_enable : 1; + unsigned int reserved : 31; + } data1; + struct { + unsigned int uart0_boot_enable : 1; + unsigned int reserved : 31; + } data2; + struct { + unsigned int func_jtag_boot_enable : 1; + unsigned int reserved : 31; + } data3; + } REG; +} FOTP_INFO_RGN1_NUMBER_1; + +typedef union { + FOTP_CommonData comData; + struct { + struct { + unsigned int info_rgn1_unlock : 1; + unsigned int reserved : 31; + } data0; + unsigned int reserved[3]; + } REG; +} FOTP_INFO_RGN1_NUMBER_2; + +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/fotp/fotp_info_read.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/fotp/fotp_info_read.c new file mode 100644 index 00000000..bda1fcd2 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/fotp/fotp_info_read.c @@ -0,0 +1,106 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file fotp_info_read.c + * @author MCU Driver Team + * @brief This file provides firmware functions to manage the following + * functionalities of the fotp control register. + * + FOTP INFO Read API + */ +#include "chipinc.h" +#include "flash.h" +#include "fotp_info_read.h" +#include "debug.h" +#define FOTP_INFO_RNG0_BASEADDR 0x800000 +#define FOTP_INFO_RNG1_BASEADDR 0x802000 +#define REG_WORDS_NUM 16 +#define FLASH_READ_128BIT 1 + +/** + * @brief Read Four words of FOTP. + * @param efc Flash control register base address + * @retval BASE_STATUS_ERROR fail. + * @retval BASE_STATUS_OK success. + */ +static unsigned int FOTP_CheckReadStatus(EFC_RegStruct *efc) +{ + if (efc->INT_RAW_STATUS.BIT.int_raw_err_illegal || + efc->INT_RAW_STATUS.BIT.int_raw_err_ecc_corr || + efc->INT_RAW_STATUS.BIT.int_raw_err_ecc_chk) { + efc->INT_CLEAR.BIT.int_clr_err_ecc_corr = BASE_CFG_SET; + efc->INT_CLEAR.BIT.int_clr_err_illegal = BASE_CFG_SET; + efc->INT_CLEAR.BIT.int_clr_err_ecc_chk = BASE_CFG_SET; + efc->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief Read Four words of FOTP. + * @param type FOTP Range Type + * @param index FOTP register index + * @param buf Buffer of read data + * @retval BASE_STATUS_ERROR fail. + * @retval BASE_STATUS_OK success. + */ +unsigned int FOTP_InfoGet(FOTP_InfoRngType type, unsigned int index, FOTP_CommonData *buf) +{ + EFC_RegStruct *p = EFC; + unsigned int addr; + + if (buf == NULL) { + return BASE_STATUS_ERROR; + } + + if ((type >= FOTP_INFO_MAXTYPE) || (index > FOTP_INFO_REG_MAX_ID)) { + return BASE_STATUS_ERROR; + } + + /* If there is a read command, return */ + if (p->EFLASH_CMD.BIT.cmd_start) { + return BASE_STATUS_ERROR; + } + + p->MAGIC_LOCK = FLASH_KEY_REGISTER_UNLOCK_VALUE; + + /* Configure the read command parameters and start the read command */ + addr = (type == FOTP_INFO_RNG0) ? FOTP_INFO_RNG0_BASEADDR : FOTP_INFO_RNG1_BASEADDR; + addr += index * REG_WORDS_NUM; + p->EFLASH_ADDR.BIT.cmd_addr = addr >> 2; /* Right shift 2 bit change to word */ + p->EFLASH_CMD.BIT.cmd_code = FLASH_OPERATION_READ; + p->EFLASH_CMD.BIT.cmd_read_size = FLASH_READ_128BIT; + p->EFLASH_CMD.BIT.cmd_start = BASE_CFG_SET; + + while (p->EFLASH_CMD.BIT.cmd_start) { + ; + } + while (p->EFLASH_CMD.BIT.exec_state) { + ; + } + /* read error, clear interrupt and return */ + if (FOTP_CheckReadStatus(p) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + /* Read data from FIFO to buffer */ + for (unsigned int i = 0; i < sizeof(buf->data) / sizeof(buf->data[0]); ++i) { + buf->data[i] = p->FLASH_RDATA; + } + p->INT_CLEAR.BIT.int_clr_finish = BASE_CFG_SET; + p->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; + return BASE_STATUS_OK; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/fotp/fotp_info_read.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/fotp/fotp_info_read.h new file mode 100644 index 00000000..2a78077f --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/fotp/fotp_info_read.h @@ -0,0 +1,31 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file fotp_info_read.h + * @author MCU Driver Team + * @brief This file provides firmware functions to manage the following + * functionalities of the system control register. + * + FOTP Register Read API + */ +#ifndef McuMagicTag_FOTP_INFO_READ_H +#define McuMagicTag_FOTP_INFO_READ_H + +#include "fotp.h" + +unsigned int FOTP_InfoGet(FOTP_InfoRngType type, unsigned int index, FOTP_CommonData *buf); + +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/info.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/info.h new file mode 100644 index 00000000..fde26d30 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/info.h @@ -0,0 +1,30 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file info.h + * @author MCU Driver Team + * @brief Defines chip attributes. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_INFO_H +#define McuMagicTag_INFO_H + +#define CHIP_DELAY_CYCLES_PER_LOOP (4) /**< CPU cycles. Known number of this CPU cycles required to execute the \ + BASE_FUNC_delay() loop. */ + +#endif /* McuMagicTag_INFO_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/interrupt_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/interrupt_ip.h new file mode 100644 index 00000000..a6408250 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/interrupt_ip.h @@ -0,0 +1,198 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file interrupt_ip.h + * @author MCU Driver Team + * @brief interrupt module driver. + * This file define the interrupt number + */ + +#ifndef MCUMagicTag_INTERRUPT_IP_H +#define MCUMagicTag_INTERRUPT_IP_H + +/* Typedef definitions -------------------------------------------------------*/ +#define MSTATUS_MIE 0x00000008U /**< mie in mstatus */ +#define MSTATUS_MPIE 0x00000080U /**< mpie in mstatus */ +#define UINT32_CUT_MASK 0xFFFFFFFFU + +#define IRQ_PRIO_HIGHEST 7 /**< Highest priority of a hardware interrupt. */ +#define IRQ_PRIO_LOWEST 1 /**< Lowest priority of a hardware interrupt. */ + +/** + * @brief Count of system interrupt vector. + * The number of standard interrupts inside the CPU. The interrupt number + * is 0~25. The software interrupt nesting scheme cannot use standard + * interrupts, which means that external system integration will ensure + * that no standard interrupts will be triggered. + */ +#define IRQ_VECTOR_CNT 26 + +/** + * @brief Count of local interrupt vector 0 - 5, enabled by CSR mie 26 -31 bit. + */ +#define IRQ_MIE_VECTOR_CNT 6 + +/** + * @brief Count of IRQ controlled by CSR mie + */ +#define IRQ_MIE_TOTAL_CNT (IRQ_VECTOR_CNT + IRQ_MIE_VECTOR_CNT) +#define IRQ_LOCIEN1_OFFSET 64 +#define IRQ_LOCIEN2_OFFSET 96 +#define IRQ_LOCIEN3_OFFSET 128 + +/** + * @brief rv_custom_csr + * locipri0~15 are registers that control the priority of interrupts, + * and every 4 bits control the priority of an interrupt + */ +#define LOCIPRI0 0xBC0 +#define LOCIPRI1 0xBC1 +#define LOCIPRI2 0xBC2 +#define LOCIPRI3 0xBC3 +#define LOCIPRI4 0xBC4 +#define LOCIPRI5 0xBC5 +#define LOCIPRI6 0xBC6 +#define LOCIPRI7 0xBC7 +#define LOCIPRI8 0xBC8 +#define LOCIPRI9 0xBC9 +#define LOCIPRI10 0xBCA +#define LOCIPRI11 0xBCB +#define LOCIPRI12 0xBCC +#define LOCIPRI13 0xBCD +#define LOCIPRI14 0xBCE +#define LOCIPRI15 0xBCF + +#define LOCIPRI(x) LOCIPRI##x + +/** + * @brief locien0~3 are registers that control interrupt enable + */ +#define LOCIEN0 0xBE0 +#define LOCIEN1 0xBE1 +#define LOCIEN2 0xBE2 +#define LOCIEN3 0xBE3 + +/** + * @brief locipd0~3 are registers that control the interrupt flag bit. Each bit + * controls an interrupt. If the corresponding bit bit is 1, it means the + * corresponding interrupt is triggered. + */ +#define LOCIPD0 0xBE8 +#define LOCIPD1 0xBE9 +#define LOCIPD2 0xBEA +#define LOCIPD3 0xBEB + +/** + * @brief Locipclr is the register that clears the interrupt flag bit, and the + * corresponding interrupt number is assigned to the locipclr register, + * and the hardware will clear the corresponding interrupt flag bit, that + * is, the corresponding locipd bit is set + */ +#define LOCIPCLR 0xBF0 + +/** + * @brief The maximum number of interrupts supported, excluding 26 internal standard + * interrupts, up to 230 external non-standard interrupts can be supported + */ +#define IRQ_NUM 256 + +/* ---------- Interrupt Number Definition ----------------------------------- */ +typedef enum { + IRQ_SOFTWARE = 26, /* The first 0~25 interrupts are the internal standard interrupts of the CPU, + and the customizable external non-standard interrupts start from 26 */ + IRQ_UART0 = 28, + IRQ_UART1 = 29, + IRQ_UART2 = 30, + + IRQ_TIMER0 = 32, + IRQ_TIMER1 = 33, + IRQ_TIMER2 = 34, + IRQ_TIMER3 = 35, + + IRQ_WDG = 40, + IRQ_IWDG = 41, + IRQ_I2C = 42, + + IRQ_SPI = 44, + + IRQ_CAN = 46, + IRQ_CRC = 47, + IRQ_APT0_EVT = 48, + IRQ_APT0_TMR = 49, + IRQ_APT1_EVT = 50, + IRQ_APT1_TMR = 51, + IRQ_APT2_EVT = 52, + IRQ_APT2_TMR = 53, + IRQ_APT3_EVT = 54, + IRQ_APT3_TMR = 55, + IRQ_APT4_EVT = 56, + IRQ_APT4_TMR = 57, + IRQ_APT5_EVT = 58, + IRQ_APT5_TMR = 59, + IRQ_APT6_EVT = 60, + IRQ_APT6_TMR = 61, + IRQ_APT7_EVT = 62, + IRQ_APT7_TMR = 63, + IRQ_APT8_EVT = 64, + IRQ_APT8_TMR = 65, + + IRQ_CMM = 68, + IRQ_CFD = 69, + IRQ_CAPM0 = 70, + IRQ_CAPM1 = 71, + IRQ_CAPM2 = 72, + IRQ_QDM0 = 73, + + IRQ_DMA_TC = 77, + IRQ_DMA_ERR = 78, + IRQ_SYSRAM_PARITY_ERR = 79, + + IRQ_EFC = 81, + IRQ_EFC_ERR = 82, + + IRQ_PMU_CLDO_OCP = 84, + IRQ_PVD = 85, + + IRQ_ADC0_OVINT = 92, + IRQ_ADC0_INT1 = 93, + IRQ_ADC0_INT2 = 94, + IRQ_ADC0_INT3 = 95, + IRQ_ADC0_INT4 = 96, + IRQ_ADC1_OVINT = 97, + IRQ_ADC1_INT1 = 98, + IRQ_ADC1_INT2 = 99, + IRQ_ADC1_INT3 = 100, + IRQ_ADC1_INT4 = 101, + IRQ_ADC2_OVINT = 102, + IRQ_ADC2_INT1 = 103, + IRQ_ADC2_INT2 = 104, + IRQ_ADC2_INT3 = 105, + IRQ_ADC2_INT4 = 106, + + IRQ_GPIO0 = 109, + IRQ_GPIO1 = 110, + IRQ_GPIO2 = 111, + IRQ_GPIO3 = 112, + IRQ_GPIO4 = 113, + IRQ_GPIO5 = 114, + IRQ_GPIO6 = 115, + IRQ_GPIO7 = 116, + + IRQ_MAX, /**< The maximum number of interrupts currently supported */ +} IRQ_ID; + +#endif /* MCUMagicTag_INTERRUPT_IP_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/ioconfig.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/ioconfig.h new file mode 100644 index 00000000..a5ea8a69 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/ioconfig.h @@ -0,0 +1,158 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file ioconfig.h + * @author MCU Driver Team + * @brief ioconfig module driver + * @details This file provides IOConfig register mapping structure. + */ + +/* Macro definitions */ +#ifndef McuMagicTag_IOCONFIG_H +#define McuMagicTag_IOCONFIG_H +typedef union { + unsigned int reg; + struct { + unsigned int func : 4; /**< IO function selection. */ + unsigned int ds : 2; /**< Pin drive capability selection. */ + unsigned int reserved0 : 1; + unsigned int pd : 1; /**< Pin pull down control. */ + unsigned int pu : 1; /**< Pin pull up control. */ + unsigned int sr : 1; /**< Electrical level shift speed control. */ + unsigned int se : 1; /**< Schmidt input control. */ + unsigned int osc_e : 1; /**< XOUT/XIN pin crystal oscillator function enable. */ + unsigned int osc_ds : 2; /**< XOUT/XIN pin crystal oscillator function drive capability selection. */ + unsigned int osc_ie : 1; /**< XOUT/XIN pin crystal oscillator function clock output enable. */ + unsigned int reserved1 : 17; + } BIT; +} volatile IOCMG_OSC_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int func : 4; /**< IO function selection. */ + unsigned int ds : 2; /**< Pin drive capability selection. */ + unsigned int reserved0 : 1; + unsigned int pd : 1; /**< Pin pull down control. */ + unsigned int pu : 1; /**< Pin pull up control. */ + unsigned int sr : 1; /**< Electrical level shift speed control. */ + unsigned int se : 1; /**< Schmidt input control. */ + unsigned int reserved1 : 21; + } BIT; +} volatile IOCMG_REG; + +typedef struct { + IOCMG_REG iocmg_0; /**< Pin TCK/SWDCK IO Config Register, offset address:0x0U */ + IOCMG_REG iocmg_1; /**< Pin TMS/SWDIO IO Config Register, offset address:0x4U */ + IOCMG_REG iocmg_66; /**< Pin I2C0_SCL/UART2_TX IO Config Register, offset address:0x8U */ + IOCMG_REG iocmg_67; /**< Pin I2C0_SDA/UART2_RX IO Config Register, offset address:0xCU */ + unsigned char space0[65524]; + IOCMG_OSC_REG iocmg_6; /**< Pin XTAL_OUT IO Config Register, offset address:0x10004U */ + IOCMG_REG iocmg_7; /**< Pin XTAL_IN IO Config Register, offset address:0x10008U */ +#if defined (CHIP_3061HRPIKZ) + unsigned char space1[4]; +#else + IOCMG_REG iocmg_8; /**< Pin GPT0 IO Config Register, offset address:0x1000CU */ +#endif +#if defined (CHIP_3065HRPICZ) || defined (CHIP_3061HRPIKZ) + unsigned char space2[16]; +#else + IOCMG_REG iocmg_9; /**< Pin CAN_RX IO Config Register, offset address:0x10010U */ + IOCMG_REG iocmg_10; /**< Pin CAN_TX IO Config Register, offset address:0x10014U */ + IOCMG_REG iocmg_11; /**< Pin QDM_A IO Config Register, offset address:0x10018U */ + IOCMG_REG iocmg_12; /**< Pin QDM_B IO Config Register, offset address:0x1001CU */ +#endif + IOCMG_REG iocmg_13; /**< Pin BOOT/GPIO1_2 IO Config Register, offset address:0x10020U */ + IOCMG_REG iocmg_14; /**< Pin TDO/GPT1/UART1_RX IO Config Register, offset address:0x10024U */ + IOCMG_REG iocmg_15; /**< Pin TDI/CAPM0/UART1_TX IO Config Register, offset address:0x10028U */ + unsigned char space3[2097108]; +#if defined (CHIP_3065HRPICZ) || defined (CHIP_3061HRPIKZ) + unsigned char space4[4]; +#else + IOCMG_REG iocmg_17; /**< Pin QDM_INDEX/POE1 IO Config Register, offset address:0x210000U */ +#endif + IOCMG_REG iocmg_18; /**< Pin TRSTN/ADC1_B3/CAPM1 IO Config Register, offset address:0x210004U */ +#if defined (CHIP_3061HRPIKZ) + unsigned char space5[8]; +#else + IOCMG_REG iocmg_19; /**< Pin ADC1_B4/CAPM2 IO Config Register, offset address:0x210008U */ + IOCMG_REG iocmg_20; /**< Pin ADC1_B5 IO Config Register, offset address:0x21000CU */ +#endif + IOCMG_REG iocmg_21; /**< Pin ADC1_A1 IO Config Register, offset address:0x210010U */ + IOCMG_REG iocmg_22; /**< Pin ADC1_A2/PGA1IN_P0 IO Config Register, offset address:0x210014U */ + IOCMG_REG iocmg_23; /**< Pin ADC1_B2/PGA1IN_N0/APT6_A IO Config Register, offset address:0x210018U */ + IOCMG_REG iocmg_24; /**< Pin PGA1OUT0 IO Config Register, offset address:0x21001CU */ + IOCMG_REG iocmg_25; /**< Pin ADC1_A3 IO Config Register, offset address:0x210020U */ + IOCMG_REG iocmg_26; /**< Pin ADC1_A4/APT6_B IO Config Register, offset address:0x210024U */ +#if defined (CHIP_3061HRPIKZ) + unsigned char space6[20]; +#else + IOCMG_REG iocmg_27; /**< Pin ADC1_A5/APT7_B IO Config Register, offset address:0x210028U */ + IOCMG_REG iocmg_28; /**< Pin ADC1_A6/APT8_B IO Config Register, offset address:0x21002CU */ + unsigned char space6[12]; +#endif + IOCMG_REG iocmg_32; /**< Pin APT0_A IO Config Register, offset address:0x21003CU */ + IOCMG_REG iocmg_33; /**< Pin APT1_A IO Config Register, offset address:0x210040U */ + IOCMG_REG iocmg_34; /**< Pin APT2_A IO Config Register, offset address:0x210044U */ + IOCMG_REG iocmg_35; /**< Pin APT0_B IO Config Register, offset address:0x210048U */ + IOCMG_REG iocmg_36; /**< Pin APT1_B IO Config Register, offset address:0x21004CU */ + IOCMG_REG iocmg_37; /**< Pin APT2_B IO Config Register, offset address:0x210050U */ +#if defined (CHIP_3061HRPIKZ) + unsigned char space7[12]; +#else + IOCMG_REG iocmg_38; /**< Pin PGA0IN_P0 IO Config Register, offset address:0x210054U */ + IOCMG_REG iocmg_39; /**< Pin PGA0IN_N0 IO Config Register, offset address:0x210058U */ + IOCMG_REG iocmg_40; /**< Pin PGA0OUT IO Config Register, offset address:0x21005CU */ +#endif +#if defined (CHIP_3065HRPICZ) || defined (CHIP_3061HRPIKZ) + unsigned char space8[4]; +#else + IOCMG_REG iocmg_41; /**< Pin GPIO4_6 IO Config Register, offset address:0x210060U */ +#endif +#if defined (CHIP_3061HRPIKZ) + unsigned char space9[4]; +#else + IOCMG_REG iocmg_42; /**< Pin GPIO4_7 IO Config Register, offset address:0x210064U */ +#endif + IOCMG_REG iocmg_43; /**< Pin GPIO5_0/POE0 IO Config Register, offset address:0x210068U */ + unsigned char space10[16]; + IOCMG_REG iocmg_48; /**< Pin GPIO5_5 IO Config Register, offset address:0x21007CU */ + IOCMG_REG iocmg_49; /**< Pin GPIO5_6 IO Config Register, offset address:0x210080U */ + IOCMG_REG iocmg_50; /**< Pin GPIO5_7 IO Config Register, offset address:0x210084U */ +#if defined (CHIP_3061HRPIKZ) + unsigned char space11[20]; +#else + IOCMG_REG iocmg_51; /**< Pin ADC2_A7 IO Config Register, offset address:0x210088U */ + IOCMG_REG iocmg_52; /**< Pin ADC2_B0 IO Config Register, offset address:0x21008CU */ + IOCMG_REG iocmg_53; /**< Pin ADC2_A1 IO Config Register, offset address:0x210090U */ + IOCMG_REG iocmg_54; /**< Pin ADC2_A2/POE2 IO Config Register, offset address:0x210094U */ + IOCMG_REG iocmg_55; /**< Pin ADC2_B2 IO Config Register, offset address:0x210098U */ +#endif +#if defined (CHIP_3065HRPICZ) || defined (CHIP_3061HRPIKZ) + unsigned char space12[32]; +#else + unsigned char space12[8]; + IOCMG_REG iocmg_58; /**< Pin APT3_A IO Config Register, offset address:0x2100A4U */ + IOCMG_REG iocmg_59; /**< Pin APT4_A IO Config Register, offset address:0x2100A8U */ + IOCMG_REG iocmg_60; /**< Pin APT5_A IO Config Register, offset address:0x2100ACU */ + IOCMG_REG iocmg_61; /**< Pin APT3_B IO Config Register, offset address:0x2100B0U */ + IOCMG_REG iocmg_62; /**< Pin APT4_B IO Config Register, offset address:0x2100B4U */ + IOCMG_REG iocmg_63; /**< Pin APT5_B IO Config Register, offset address:0x2100B8U */ +#endif +} volatile IOConfig_RegStruct; + +#endif /* McuMagicTag_IOCONFIG_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/iomap/3065hrpirz/iomap.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/iomap/3065hrpirz/iomap.h new file mode 100644 index 00000000..a37fbc25 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/iomap/3065hrpirz/iomap.h @@ -0,0 +1,275 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file iomap.h + * @author MCU Driver Team + * @brief Defines chip pin map and function mode. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_IOMAP_H +#define McuMagicTag_IOMAP_H + +/* get offset value of member in type struct */ +#define OFFSET_OF(type, member) (unsigned int)(&(((type *)0)->member)) + +#define IOCMG_PIN_MUX(regx, funcNum, regValueDefault) \ + (unsigned int)(((OFFSET_OF(IOConfig_RegStruct, regx) & 0x00FF0000) << 8) | \ + ((OFFSET_OF(IOConfig_RegStruct, regx) & 0x000000FF) << 16) | \ + ((regValueDefault & 0xFFFFFFF0) | funcNum)) +/* pin function mode info ---------------------------------------------------- */ +#define IO1_AS_GPIO1_6 IOCMG_PIN_MUX(iocmg_17, FUNC_MODE_0, 0x0000) +#define IO1_AS_QDM_INDEX IOCMG_PIN_MUX(iocmg_17, FUNC_MODE_1, 0x0000) +#define IO1_AS_POE1 IOCMG_PIN_MUX(iocmg_17, FUNC_MODE_2, 0x0000) +#define IO1_AS_QDM_SYNC IOCMG_PIN_MUX(iocmg_17, FUNC_MODE_3, 0x0000) + +#define IO2_AS_GPIO1_7 IOCMG_PIN_MUX(iocmg_18, FUNC_MODE_0, 0x0081) +#define IO2_AS_JTAG_TRSTN IOCMG_PIN_MUX(iocmg_18, FUNC_MODE_1, 0x0081) +#define IO2_AS_CAPM1_SRC1 IOCMG_PIN_MUX(iocmg_18, FUNC_MODE_3, 0x0081) +#define IO2_AS_UART1_CTSN IOCMG_PIN_MUX(iocmg_18, FUNC_MODE_4, 0x0081) +#define IO2_AS_SSP0_CSN0 IOCMG_PIN_MUX(iocmg_18, FUNC_MODE_5, 0x0081) +#define IO2_AS_ADTRG1 IOCMG_PIN_MUX(iocmg_18, FUNC_MODE_6, 0x0081) +#define IO2_AS_ADC1_ANA IOCMG_PIN_MUX(iocmg_18, FUNC_MODE_8, 0x0081) +#define IO2_AS_ACMP1_ANA_N2 IOCMG_PIN_MUX(iocmg_18, FUNC_MODE_9, 0x0081) + +#define IO3_AS_GPIO2_0 IOCMG_PIN_MUX(iocmg_19, FUNC_MODE_0, 0x0000) +#define IO3_AS_CAPM2_SRC1 IOCMG_PIN_MUX(iocmg_19, FUNC_MODE_3, 0x0000) +#define IO3_AS_SSP0_TXD IOCMG_PIN_MUX(iocmg_19, FUNC_MODE_5, 0x0000) +#define IO3_AS_ADC1_ANA_B4 IOCMG_PIN_MUX(iocmg_19, FUNC_MODE_8, 0x0000) + +#define IO4_AS_GPIO2_1 IOCMG_PIN_MUX(iocmg_20, FUNC_MODE_0, 0x0000) +#define IO4_AS_CAPM0_SRC1 IOCMG_PIN_MUX(iocmg_20, FUNC_MODE_3, 0x0000) +#define IO4_AS_SSP0_RXD IOCMG_PIN_MUX(iocmg_20, FUNC_MODE_5, 0x0000) +#define IO4_AS_ADC1_ANA_B5 IOCMG_PIN_MUX(iocmg_20, FUNC_MODE_8, 0x0000) + +#define IO5_AS_GPIO2_2 IOCMG_PIN_MUX(iocmg_21, FUNC_MODE_0, 0x0000) +#define IO5_AS_APT_EVTMP4 IOCMG_PIN_MUX(iocmg_21, FUNC_MODE_2, 0x0000) +#define IO5_AS_UART1_RTSN IOCMG_PIN_MUX(iocmg_21, FUNC_MODE_4, 0x0000) +#define IO5_AS_SSP0_CSN1 IOCMG_PIN_MUX(iocmg_21, FUNC_MODE_5, 0x0000) +#define IO5_AS_ADST1 IOCMG_PIN_MUX(iocmg_21, FUNC_MODE_6, 0x0000) +#define IO5_AS_ADC1_ANA_A1 IOCMG_PIN_MUX(iocmg_21, FUNC_MODE_8, 0x0000) +#define IO5_AS_ACMP1_ANA_P2 IOCMG_PIN_MUX(iocmg_21, FUNC_MODE_9, 0x0000) + +#define IO6_AS_GPIO2_3 IOCMG_PIN_MUX(iocmg_22, FUNC_MODE_0, 0x0000) +#define IO6_AS_SSP0_CLK IOCMG_PIN_MUX(iocmg_22, FUNC_MODE_5, 0x0000) +#define IO6_AS_ADC1_ANA_A2 IOCMG_PIN_MUX(iocmg_22, FUNC_MODE_8, 0x0000) +#define IO6_AS_PGA1_ANA_P0 IOCMG_PIN_MUX(iocmg_22, FUNC_MODE_9, 0x0000) + +#define IO7_AS_GPIO2_4 IOCMG_PIN_MUX(iocmg_23, FUNC_MODE_0, 0x0000) +#define IO7_AS_APT6_PWMA IOCMG_PIN_MUX(iocmg_23, FUNC_MODE_3, 0x0000) +#define IO7_AS_ADC1_ANA_B2 IOCMG_PIN_MUX(iocmg_23, FUNC_MODE_8, 0x0000) +#define IO7_AS_PGA1_ANA_N0 IOCMG_PIN_MUX(iocmg_23, FUNC_MODE_9, 0x0000) + +#define IO8_AS_GPIO2_5 IOCMG_PIN_MUX(iocmg_24, FUNC_MODE_0, 0x0000) +#define IO8_AS_APT7_PWMA IOCMG_PIN_MUX(iocmg_24, FUNC_MODE_3, 0x0000) +#define IO8_AS_PGA1_ANA_EXT0 IOCMG_PIN_MUX(iocmg_24, FUNC_MODE_8, 0x0000) + +#define IO9_AS_GPIO2_6 IOCMG_PIN_MUX(iocmg_25, FUNC_MODE_0, 0x0000) +#define IO9_AS_APT8_PWMA IOCMG_PIN_MUX(iocmg_25, FUNC_MODE_3, 0x0000) +#define IO9_AS_POE0 IOCMG_PIN_MUX(iocmg_25, FUNC_MODE_4, 0x0000) +#define IO9_AS_ADST0 IOCMG_PIN_MUX(iocmg_25, FUNC_MODE_6, 0x0000) +#define IO9_AS_ADC1_ANA_A3 IOCMG_PIN_MUX(iocmg_25, FUNC_MODE_8, 0x0000) + +#define IO10_AS_GPIO2_7 IOCMG_PIN_MUX(iocmg_26, FUNC_MODE_0, 0x0000) +#define IO10_AS_ACMP1_OUT IOCMG_PIN_MUX(iocmg_26, FUNC_MODE_2, 0x0000) +#define IO10_AS_APT6_PWMB IOCMG_PIN_MUX(iocmg_26, FUNC_MODE_3, 0x0000) +#define IO10_AS_ADC1_ANA_A4 IOCMG_PIN_MUX(iocmg_26, FUNC_MODE_8, 0x0000) + +#define IO11_AS_GPIO3_0 IOCMG_PIN_MUX(iocmg_27, FUNC_MODE_0, 0x0000) +#define IO11_AS_APT7_PWMB IOCMG_PIN_MUX(iocmg_27, FUNC_MODE_3, 0x0000) +#define IO11_AS_ADC1_ANA_A5 IOCMG_PIN_MUX(iocmg_27, FUNC_MODE_8, 0x0000) +#define IO11_AS_ACMP1_ANA_N3 IOCMG_PIN_MUX(iocmg_27, FUNC_MODE_9, 0x0000) + +#define IO12_AS_GPIO3_1 IOCMG_PIN_MUX(iocmg_28, FUNC_MODE_0, 0x0000) +#define IO12_AS_APT8_PWMB IOCMG_PIN_MUX(iocmg_28, FUNC_MODE_3, 0x0000) +#define IO12_AS_ADC1_ANA_A6 IOCMG_PIN_MUX(iocmg_28, FUNC_MODE_8, 0x0000) +#define IO12_AS_ACMP1_ANA_P3 IOCMG_PIN_MUX(iocmg_28, FUNC_MODE_9, 0x0000) + +#define IO15_AS_GPIO3_5 IOCMG_PIN_MUX(iocmg_32, FUNC_MODE_0, 0x0000) +#define IO15_AS_APT0_PWMA IOCMG_PIN_MUX(iocmg_32, FUNC_MODE_3, 0x0000) + +#define IO16_AS_GPIO3_6 IOCMG_PIN_MUX(iocmg_33, FUNC_MODE_0, 0x0000) +#define IO16_AS_APT1_PWMA IOCMG_PIN_MUX(iocmg_33, FUNC_MODE_3, 0x0000) +#define IO16_AS_DAC0_ANA_OUT IOCMG_PIN_MUX(iocmg_33, FUNC_MODE_8, 0x0000) + +#define IO17_AS_GPIO3_7 IOCMG_PIN_MUX(iocmg_34, FUNC_MODE_0, 0x0000) +#define IO17_AS_APT2_PWMA IOCMG_PIN_MUX(iocmg_34, FUNC_MODE_3, 0x0000) +#define IO17_AS_DAC1_ANA_OUT IOCMG_PIN_MUX(iocmg_34, FUNC_MODE_8, 0x0000) + +#define IO18_AS_GPIO4_0 IOCMG_PIN_MUX(iocmg_35, FUNC_MODE_0, 0x0000) +#define IO18_AS_APT0_PWMB IOCMG_PIN_MUX(iocmg_35, FUNC_MODE_3, 0x0000) +#define IO18_AS_DAC2_ANA_OUT IOCMG_PIN_MUX(iocmg_35, FUNC_MODE_8, 0x0000) + +#define IO19_AS_GPIO4_1 IOCMG_PIN_MUX(iocmg_36, FUNC_MODE_0, 0x0000) +#define IO19_AS_APT1_PWMB IOCMG_PIN_MUX(iocmg_36, FUNC_MODE_3, 0x0000) +#define IO19_AS_ADC_OB_CLK IOCMG_PIN_MUX(iocmg_36, FUNC_MODE_4, 0x0000) + +#define IO20_AS_GPIO4_2 IOCMG_PIN_MUX(iocmg_37, FUNC_MODE_0, 0x0000) +#define IO20_AS_APT2_PWMB IOCMG_PIN_MUX(iocmg_37, FUNC_MODE_3, 0x0000) +#define IO20_AS_ADC_OB_DATA IOCMG_PIN_MUX(iocmg_37, FUNC_MODE_4, 0x0000) + +#define IO21_AS_GPIO4_3 IOCMG_PIN_MUX(iocmg_38, FUNC_MODE_0, 0x0000) +#define IO21_AS_ADC0_ANA_A7 IOCMG_PIN_MUX(iocmg_38, FUNC_MODE_8, 0x0000) +#define IO21_AS_PGA0_ANA_P0 IOCMG_PIN_MUX(iocmg_38, FUNC_MODE_9, 0x0000) + +#define IO22_AS_GPIO4_4 IOCMG_PIN_MUX(iocmg_39, FUNC_MODE_0, 0x0000) +#define IO22_AS_ADC0_ANA_B0 IOCMG_PIN_MUX(iocmg_39, FUNC_MODE_8, 0x0000) +#define IO22_AS_PGA0_ANA_N0 IOCMG_PIN_MUX(iocmg_39, FUNC_MODE_9, 0x0000) + +#define IO23_AS_GPIO4_5 IOCMG_PIN_MUX(iocmg_40, FUNC_MODE_0, 0x0000) +#define IO23_AS_PGA0_ANA_EXT0 IOCMG_PIN_MUX(iocmg_40, FUNC_MODE_8, 0x0000) + +#define IO28_AS_GPIO4_6 IOCMG_PIN_MUX(iocmg_41, FUNC_MODE_0, 0x0000) +#define IO28_AS_ADTRG0 IOCMG_PIN_MUX(iocmg_41, FUNC_MODE_6, 0x0000) +#define IO28_AS_ADC0_ANA_A3 IOCMG_PIN_MUX(iocmg_41, FUNC_MODE_8, 0x0000) +#define IO28_AS_PGA1_ANA_P3 IOCMG_PIN_MUX(iocmg_41, FUNC_MODE_9, 0x0000) + +#define IO29_AS_GPIO4_7 IOCMG_PIN_MUX(iocmg_42, FUNC_MODE_0, 0x0000) +#define IO29_AS_ADC0_ANA_A4 IOCMG_PIN_MUX(iocmg_42, FUNC_MODE_8, 0x0000) +#define IO29_AS_PGA1_ANA_N3 IOCMG_PIN_MUX(iocmg_42, FUNC_MODE_9, 0x0000) +#define IO29_AS_ACMP0_ANA_N1 IOCMG_PIN_MUX(iocmg_42, FUNC_MODE_10, 0x0000) + +#define IO30_AS_GPIO5_0 IOCMG_PIN_MUX(iocmg_43, FUNC_MODE_0, 0x0000) +#define IO30_AS_ACMP0_OUT IOCMG_PIN_MUX(iocmg_43, FUNC_MODE_2, 0x0000) +#define IO30_AS_APT_EVTMP4 IOCMG_PIN_MUX(iocmg_43, FUNC_MODE_3, 0x0000) +#define IO30_AS_POE0 IOCMG_PIN_MUX(iocmg_43, FUNC_MODE_4, 0x0000) +#define IO30_AS_ADST0 IOCMG_PIN_MUX(iocmg_43, FUNC_MODE_6, 0x0000) +#define IO30_AS_PGA1_ANA_EXT0 IOCMG_PIN_MUX(iocmg_43, FUNC_MODE_9, 0x0000) + +#define IO31_AS_GPIO5_5 IOCMG_PIN_MUX(iocmg_48, FUNC_MODE_0, 0x0000) +#define IO31_AS_SYS_RSTN_OUT IOCMG_PIN_MUX(iocmg_48, FUNC_MODE_1, 0x0000) +#define IO31_AS_ADC2_ANA_B1 IOCMG_PIN_MUX(iocmg_48, FUNC_MODE_8, 0x0000) +#define IO31_AS_GA2_ANA_P0 IOCMG_PIN_MUX(iocmg_48, FUNC_MODE_9, 0x0000) + +#define IO32_AS_GPIO5_6 IOCMG_PIN_MUX(iocmg_49, FUNC_MODE_0, 0x0000) +#define IO32_AS_ADC2_ANA_A6 IOCMG_PIN_MUX(iocmg_49, FUNC_MODE_8, 0x0000) +#define IO32_AS_PGA2_ANA_N0 IOCMG_PIN_MUX(iocmg_49, FUNC_MODE_9, 0x0000) + +#define IO33_AS_GPIO5_7 IOCMG_PIN_MUX(iocmg_50, FUNC_MODE_0, 0x0000) +#define IO33_AS_PGA2_ANA_EXT0 IOCMG_PIN_MUX(iocmg_50, FUNC_MODE_9, 0x0000) + +#define IO36_AS_GPIO6_0 IOCMG_PIN_MUX(iocmg_51, FUNC_MODE_0, 0x0000) +#define IO36_AS_UART2_TXD IOCMG_PIN_MUX(iocmg_51, FUNC_MODE_3, 0x0000) +#define IO36_AS_ADC2_ANA_A7 IOCMG_PIN_MUX(iocmg_51, FUNC_MODE_8, 0x0000) +#define IO36_AS_ACMP2_ANA_N1 IOCMG_PIN_MUX(iocmg_51, FUNC_MODE_9, 0x0000) + +#define IO37_AS_GPIO6_1 IOCMG_PIN_MUX(iocmg_52, FUNC_MODE_0, 0x0000) +#define IO37_AS_UART2_RXD IOCMG_PIN_MUX(iocmg_52, FUNC_MODE_3, 0x0000) +#define IO37_AS_ADC2_ANA_B0 IOCMG_PIN_MUX(iocmg_52, FUNC_MODE_8, 0x0000) +#define IO37_AS_ACMP2_ANA_P1 IOCMG_PIN_MUX(iocmg_52, FUNC_MODE_9, 0x0000) + +#define IO38_AS_GPIO6_2 IOCMG_PIN_MUX(iocmg_53, FUNC_MODE_0, 0x0000) +#define IO38_AS_ACMP2_OUT IOCMG_PIN_MUX(iocmg_53, FUNC_MODE_2, 0x0000) +#define IO38_AS_ADST2 IOCMG_PIN_MUX(iocmg_53, FUNC_MODE_6, 0x0000) +#define IO38_AS_ADC2_ANA_A1 IOCMG_PIN_MUX(iocmg_53, FUNC_MODE_8, 0x0000) + +#define IO39_AS_GPIO6_3 IOCMG_PIN_MUX(iocmg_54, FUNC_MODE_0, 0x0000) +#define IO39_AS_POE2 IOCMG_PIN_MUX(iocmg_54, FUNC_MODE_2, 0x0000) +#define IO39_AS_CAN_RX IOCMG_PIN_MUX(iocmg_54, FUNC_MODE_3, 0x0000) +#define IO39_AS_ADTRG2 IOCMG_PIN_MUX(iocmg_54, FUNC_MODE_6, 0x0000) +#define IO39_AS_ADC2_ANA_A2 IOCMG_PIN_MUX(iocmg_54, FUNC_MODE_8, 0x0000) + +#define IO40_AS_GPIO6_4 IOCMG_PIN_MUX(iocmg_55, FUNC_MODE_0, 0x0000) +#define IO40_AS_APT_EVTMP6 IOCMG_PIN_MUX(iocmg_55, FUNC_MODE_2, 0x0000) +#define IO40_AS_CAN_TX IOCMG_PIN_MUX(iocmg_55, FUNC_MODE_3, 0x0000) +#define IO40_AS_ADC2_ANA_B2 IOCMG_PIN_MUX(iocmg_55, FUNC_MODE_8, 0x0000) + +#define IO41_AS_GPIO6_7 IOCMG_PIN_MUX(iocmg_58, FUNC_MODE_0, 0x0000) +#define IO41_AS_APT3_PWMA IOCMG_PIN_MUX(iocmg_58, FUNC_MODE_1, 0x0000) + +#define IO42_AS_GPIO7_0 IOCMG_PIN_MUX(iocmg_59, FUNC_MODE_0, 0x0000) +#define IO42_AS_APT4_PWMA IOCMG_PIN_MUX(iocmg_59, FUNC_MODE_1, 0x0000) + +#define IO43_AS_GPIO7_1 IOCMG_PIN_MUX(iocmg_60, FUNC_MODE_0, 0x0000) +#define IO43_AS_APT5_PWMA IOCMG_PIN_MUX(iocmg_60, FUNC_MODE_1, 0x0000) + +#define IO44_AS_GPIO7_2 IOCMG_PIN_MUX(iocmg_61, FUNC_MODE_0, 0x0000) +#define IO44_AS_APT3_PWMB IOCMG_PIN_MUX(iocmg_61, FUNC_MODE_1, 0x0000) + +#define IO45_AS_GPIO7_3 IOCMG_PIN_MUX(iocmg_62, FUNC_MODE_0, 0x0000) +#define IO45_AS_APT4_PWMB IOCMG_PIN_MUX(iocmg_62, FUNC_MODE_1, 0x0000) + +#define IO46_AS_GPIO7_4 IOCMG_PIN_MUX(iocmg_63, FUNC_MODE_0, 0x0000) +#define IO46_AS_APT5_PWMB IOCMG_PIN_MUX(iocmg_63, FUNC_MODE_1, 0x0000) + +#define IO47_AS_GPIO7_6 IOCMG_PIN_MUX(iocmg_66, FUNC_MODE_0, 0x0000) +#define IO47_AS_UART2_TXD IOCMG_PIN_MUX(iocmg_66, FUNC_MODE_1, 0x0000) +#define IO47_AS_I2C0_SCL IOCMG_PIN_MUX(iocmg_66, FUNC_MODE_2, 0x0000) +#define IO47_AS_DS_WAKEUP2 IOCMG_PIN_MUX(iocmg_66, FUNC_MODE_3, 0x0000) +#define IO47_AS_APT_EVTIO4 IOCMG_PIN_MUX(iocmg_66, FUNC_MODE_4, 0x0000) +#define IO47_AS_ADC2_ANA_A3 IOCMG_PIN_MUX(iocmg_66, FUNC_MODE_8, 0x0000) + +#define IO48_AS_GPIO7_7 IOCMG_PIN_MUX(iocmg_67, FUNC_MODE_0, 0x0000) +#define IO48_AS_UART2_RXD IOCMG_PIN_MUX(iocmg_67, FUNC_MODE_1, 0x0000) +#define IO48_AS_I2C0_SDA IOCMG_PIN_MUX(iocmg_67, FUNC_MODE_2, 0x0000) +#define IO48_AS_DS_WAKEUP3 IOCMG_PIN_MUX(iocmg_67, FUNC_MODE_3, 0x0000) +#define IO48_AS_ADC2_ANA_A4 IOCMG_PIN_MUX(iocmg_67, FUNC_MODE_8, 0x0000) + +#define IO49_AS_GPIO0_0 IOCMG_PIN_MUX(iocmg_0, FUNC_MODE_0, 0x0081) +#define IO49_AS_JTAG_TCK IOCMG_PIN_MUX(iocmg_0, FUNC_MODE_1, 0x0081) +#define IO49_AS_DS_WAKEUP0 IOCMG_PIN_MUX(iocmg_0, FUNC_MODE_3, 0x0081) + +#define IO50_AS_GPIO0_1 IOCMG_PIN_MUX(iocmg_1, FUNC_MODE_0, 0x0331) +#define IO50_AS_JTAG_TMS IOCMG_PIN_MUX(iocmg_1, FUNC_MODE_1, 0x0331) +#define IO50_AS_DS_WAKEUP1 IOCMG_PIN_MUX(iocmg_1, FUNC_MODE_3, 0x0331) + +#define IO52_AS_GPIO0_3 IOCMG_PIN_MUX(iocmg_6, FUNC_MODE_0, 0x0000) +#define IO52_AS_GPT0_PWM IOCMG_PIN_MUX(iocmg_6, FUNC_MODE_2, 0x0000) +#define IO52_AS_UART0_TXD IOCMG_PIN_MUX(iocmg_6, FUNC_MODE_4, 0x0000) +#define IO52_AS_XTAL_OUT IOCMG_PIN_MUX(iocmg_6, FUNC_MODE_8, 0x0000) + +#define IO53_AS_GPIO0_4 IOCMG_PIN_MUX(iocmg_7, FUNC_MODE_0, 0x0000) +#define IO53_AS_UART0_RXD IOCMG_PIN_MUX(iocmg_7, FUNC_MODE_4, 0x0000) +#define IO53_AS_XTAL_IN IOCMG_PIN_MUX(iocmg_7, FUNC_MODE_8, 0x0000) + +#define IO54_AS_GPIO0_5 IOCMG_PIN_MUX(iocmg_8, FUNC_MODE_0, 0x0000) +#define IO54_AS_GPT0_PWM IOCMG_PIN_MUX(iocmg_8, FUNC_MODE_1, 0x0000) +#define IO54_AS_APT_EVTMP5 IOCMG_PIN_MUX(iocmg_8, FUNC_MODE_2, 0x0000) +#define IO54_AS_CAPM1_SRC0 IOCMG_PIN_MUX(iocmg_8, FUNC_MODE_3, 0x0000) + +#define IO55_AS_GPIO0_6 IOCMG_PIN_MUX(iocmg_9, FUNC_MODE_0, 0x0000) +#define IO55_AS_CAN_RX IOCMG_PIN_MUX(iocmg_9, FUNC_MODE_1, 0x0000) +#define IO55_AS_APT_EVTIO5 IOCMG_PIN_MUX(iocmg_9, FUNC_MODE_2, 0x0000) + +#define IO56_AS_GPIO0_7 IOCMG_PIN_MUX(iocmg_10, FUNC_MODE_0, 0x0000) +#define IO56_AS_CAN_TX IOCMG_PIN_MUX(iocmg_10, FUNC_MODE_1, 0x0000) + +#define IO57_AS_GPIO1_0 IOCMG_PIN_MUX(iocmg_11, FUNC_MODE_0, 0x0000) +#define IO57_AS_QDM_A IOCMG_PIN_MUX(iocmg_11, FUNC_MODE_1, 0x0000) + +#define IO58_AS_GPIO1_1 IOCMG_PIN_MUX(iocmg_12, FUNC_MODE_0, 0x0000) +#define IO58_AS_QDM_B IOCMG_PIN_MUX(iocmg_12, FUNC_MODE_1, 0x0000) + +#define IO59_AS_GPIO1_2 IOCMG_PIN_MUX(iocmg_13, FUNC_MODE_0, 0x0080) +#define IO59_AS_UPDATE_MODE IOCMG_PIN_MUX(iocmg_13, FUNC_MODE_1, 0x0080) +#define IO59_AS_TEST_CLK IOCMG_PIN_MUX(iocmg_13, FUNC_MODE_2, 0x0080) +#define IO59_AS_UART1_RTSN IOCMG_PIN_MUX(iocmg_13, FUNC_MODE_4, 0x0080) + +#define IO60_AS_GPIO1_3 IOCMG_PIN_MUX(iocmg_14, FUNC_MODE_0, 0x0211) +#define IO60_AS_JTAG_TDO IOCMG_PIN_MUX(iocmg_14, FUNC_MODE_1, 0x0211) +#define IO60_AS_GPT1_PWM IOCMG_PIN_MUX(iocmg_14, FUNC_MODE_2, 0x0211) +#define IO60_AS_CAPM2_SRC0 IOCMG_PIN_MUX(iocmg_14, FUNC_MODE_3, 0x0211) +#define IO60_AS_UART1_RXD IOCMG_PIN_MUX(iocmg_14, FUNC_MODE_4, 0x0211) +#define IO60_AS_I2C0_SCL IOCMG_PIN_MUX(iocmg_14, FUNC_MODE_5, 0x0211) + +#define IO61_AS_GPIO1_4 IOCMG_PIN_MUX(iocmg_15, FUNC_MODE_0, 0x0001) +#define IO61_AS_JTAG_TDI IOCMG_PIN_MUX(iocmg_15, FUNC_MODE_1, 0x0001) +#define IO61_AS_CAPM0_SRC0 IOCMG_PIN_MUX(iocmg_15, FUNC_MODE_3, 0x0001) +#define IO61_AS_UART1_TXD IOCMG_PIN_MUX(iocmg_15, FUNC_MODE_4, 0x0001) +#define IO61_AS_I2C0_SDA IOCMG_PIN_MUX(iocmg_15, FUNC_MODE_5, 0x0001) + +#endif /* McuMagicTag_IOMAP_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/ip_crg/ip_crg_common.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/ip_crg/ip_crg_common.c new file mode 100644 index 00000000..bb8a0f19 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/ip_crg/ip_crg_common.c @@ -0,0 +1,133 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file ip_crg_common.c + * @author MCU Driver Team + * @brief Contains ip crg common header files. + */ + +/* Includes ----------------------------------------------------------------- */ +#include "baseaddr.h" +#include "ip_crg_common.h" + +/** + * @brief Get IP frequency by ip register base address + * @param ipBaseAddr The ip base address + * @retval The bus frequency where the IP is located + */ +#ifdef FPGA +unsigned int CHIP_GetIpFreqHz(const void *ipBaseAddr) +{ + void *highRateIp[] = { + SYSCTRL1_BASE, + CRC_BASE, + APT0_BASE, APT1_BASE, APT2_BASE, APT3_BASE, APT4_BASE, APT5_BASE, APT6_BASE, APT7_BASE, APT8_BASE, + CAPM0_BASE, CAPM1_BASE, CAPM2_BASE, CAPM_COMM_BASE, + QDM0_BASE, + ADC0_BASE, ADC1_BASE, ADC2_BASE, + PGA0_BASE, PGA1_BASE, PGA2_BASE, + ACMP0_BASE, ACMP1_BASE, ACMP2_BASE, + }; + + if (ipBaseAddr == IWDG_BASE) { + return CHIP_IP_CLK_LOSC; + } else if (ipBaseAddr == CAN_BASE) { + return CHIP_IP_CLK_CAN; + } else { + for (unsigned int i = 0; i < sizeof(highRateIp) / sizeof(highRateIp[0]); ++i) { + if (ipBaseAddr == highRateIp[i]) { + return CHIP_IP_CLK_HS; + } + } + return CHIP_IP_CLK_LS; + } +} +#endif + +static const CHIP_CrgIpMatchInfo g_crgIpMatch[] = { + {UART0_BASE, CRG_IP_WITH_LS, 0x30, 0}, + {UART1_BASE, CRG_IP_WITH_LS, 0x34, 0}, + {UART2_BASE, CRG_IP_WITH_LS, 0x38, 0}, + {TIMER0_BASE, CRG_IP_WITH_LS, 0x3C, 0}, + {TIMER1_BASE, CRG_IP_WITH_LS, 0x3C, 0}, + {TIMER2_BASE, CRG_IP_WITH_LS, 0x40, 0}, + {SYSTICK_BASE, CRG_IP_WITH_LS, 0x40, 0}, + {GPT0_BASE, CRG_IP_WITH_LS, 0x44, 0}, + {GPT1_BASE, CRG_IP_WITH_LS, 0x48, 0}, + {WDG_BASE, CRG_IP_WITH_LS, 0x4C, 0}, + {SPI_BASE, CRG_IP_WITH_LS, 0x50, 0}, + {CAN_BASE, CRG_IP_CAN, 0x54, 0}, + {CAPM0_BASE, CRG_IP_WITH_HS, 0x58, 0}, + {CAPM1_BASE, CRG_IP_WITH_HS, 0x58, 1}, + {CAPM2_BASE, CRG_IP_WITH_HS, 0x58, 2}, + {DMA_BASE, CRG_IP_WITH_HS, 0x5C, 0}, + {GPIO0_BASE, CRG_IP_WITH_LS, 0x64, 0}, + {GPIO1_BASE, CRG_IP_WITH_LS, 0x64, 1}, + {GPIO2_BASE, CRG_IP_WITH_LS, 0x64, 2}, + {GPIO3_BASE, CRG_IP_WITH_LS, 0x64, 3}, + {GPIO4_BASE, CRG_IP_WITH_LS, 0x64, 4}, + {GPIO5_BASE, CRG_IP_WITH_LS, 0x64, 5}, + {GPIO6_BASE, CRG_IP_WITH_LS, 0x64, 6}, + {GPIO7_BASE, CRG_IP_WITH_LS, 0x64, 7}, + {I2C_BASE, CRG_IP_WITH_LS, 0x68, 0}, + {IWDG_BASE, CRG_IP_IWDG, 0x6C, 0}, + {QDM0_BASE, CRG_IP_WITH_HS, 0x70, 0}, + {HPM_BASE, CRG_IP_WITH_HS, 0x74, 0}, + {CRC_BASE, CRG_IP_WITH_HS, 0x7C, 0}, + {APT0_BASE, CRG_IP_WITH_HS, 0x80, 0}, + {APT1_BASE, CRG_IP_WITH_HS, 0x80, 1}, + {APT2_BASE, CRG_IP_WITH_HS, 0x80, 2}, + {APT3_BASE, CRG_IP_WITH_HS, 0x80, 3}, + {APT4_BASE, CRG_IP_WITH_HS, 0x80, 4}, + {APT5_BASE, CRG_IP_WITH_HS, 0x80, 5}, + {APT6_BASE, CRG_IP_WITH_HS, 0x80, 6}, + {APT7_BASE, CRG_IP_WITH_HS, 0x80, 7}, + {APT8_BASE, CRG_IP_WITH_HS, 0x80, 8}, + {ACMP0_BASE, CRG_IP_WITH_HS, 0x90, 0}, + {ACMP1_BASE, CRG_IP_WITH_HS, 0x90, 1}, + {ACMP2_BASE, CRG_IP_WITH_HS, 0x90, 2}, + {PGA0_BASE, CRG_IP_WITH_HS, 0x98, 0}, + {PGA1_BASE, CRG_IP_WITH_HS, 0x98, 1}, + {PGA2_BASE, CRG_IP_WITH_HS, 0x98, 2}, + + {ADC0_BASE, CRG_IP_ADC, 0x84, 0}, + {ADC1_BASE, CRG_IP_ADC, 0x88, 0}, + {ADC2_BASE, CRG_IP_ADC, 0x8C, 0}, + + {DAC0_BASE, CRG_IP_DAC, 0x94, 0}, + {DAC1_BASE, CRG_IP_DAC, 0x94, 1}, + {DAC2_BASE, CRG_IP_DAC, 0x94, 2}, + + {EFC_BASE, CRG_IP_EFC, 0x60, 0}, +}; + +/** + * @brief Get IP Match Info, @see g_crgIpMatch + * @param baseAddr The ip base address + * @retval The Address(offset) in g_crgIpMatch if match success + * @retval 0 if match fail + */ +CHIP_CrgIpMatchInfo *GetCrgIpMatchInfo(const void *baseAddr) +{ + unsigned int i; + for (i = 0; i < sizeof(g_crgIpMatch) / sizeof(g_crgIpMatch[0]); ++i) { + if (baseAddr == g_crgIpMatch[i].ipBaseAddr) { + return (CHIP_CrgIpMatchInfo *)&g_crgIpMatch[i]; + } + } + return (CHIP_CrgIpMatchInfo *)0; +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/ip_crg/ip_crg_common.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/ip_crg/ip_crg_common.h new file mode 100644 index 00000000..fb5fd706 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/ip_crg/ip_crg_common.h @@ -0,0 +1,83 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file ip_crg_common.h + * @author MCU Driver Team + * @brief Contains crg ip common header files. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_IP_CRG_COMMON_H +#define McuMagicTag_IP_CRG_COMMON_H + +/** + * @brief define the frequence of hosc, losc and xtrail + */ +#define HOSC_FREQ 25000000U +#define LOSC_FREQ 32000U + +#ifdef FPGA +#define FLASH_SUPPORT +typedef enum { + CHIP_IP_CLK_LOSC = 32000U, + CHIP_IP_CLK_CAN = 25000000U, +#ifdef FLASH_SUPPORT + CHIP_IP_CLK_LS = 20000000U, + CHIP_IP_CLK_HS = 40000000U, +#else + CHIP_IP_CLK_LS = 30000000U, + CHIP_IP_CLK_HS = 60000000U, +#endif +} CHIP_IpRate; +#else +typedef enum { + CHIP_IP_CLK_LOSC = 32000U, + CHIP_IP_CLK_CAN = 25000000U, + CHIP_IP_CLK_LS = 12500000U, + CHIP_IP_CLK_HS = 25000000U, +} CHIP_IpRate; +#endif + +/** + * @brief CRG Ip Type, Sorting based on operable registers + */ +typedef enum { + CRG_IP_WITH_LS = 0x00, + CRG_IP_WITH_HS = 0x01, + CRG_IP_CAN = 0x02, + CRG_IP_ADC = 0x03, + CRG_IP_DAC = 0x04, + CRG_IP_EFC = 0x05, + CRG_IP_IWDG = 0x06, + CRG_IP_MAX_TYPE = 0x07, +} CHIP_CrgIpType; + +/** + * @brief CRG register and IP address matching relationship table + */ +typedef struct { + void *ipBaseAddr; /**< Ip base address */ + CHIP_CrgIpType type; /**< Ip type, @see CHIP_CrgIpType */ + unsigned short regOffset; /**< Offset in CRG registers */ + unsigned char bitOffset; /**< Bit Offset in CRG register */ +} CHIP_CrgIpMatchInfo; + +unsigned int CHIP_GetIpFreqHz(const void *ipBaseAddr); +CHIP_CrgIpMatchInfo *GetCrgIpMatchInfo(const void *baseAddr); +extern unsigned int HAL_CRG_GetIpFreq(const void *baseAddress); + +#endif /* McuMagicTag_IP_CRG_COMMON_H */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/locktype.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/locktype.h new file mode 100644 index 00000000..08b87ff3 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/locktype.h @@ -0,0 +1,43 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file locktype.h + * @author MCU Driver Team + * @brief This file lists all types that need to be locked on the chip. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_LOCKTYPE_H +#define McuMagicTag_LOCKTYPE_H + +/* Typedef definitions ------------------------------------------------------- */ +/** + * @brief This enum defines all hardware locks integrated by this MCU. + */ +typedef enum { + CHIP_LOCK_GPIO0 = 0, + CHIP_LOCK_GPIO1 = 1, + CHIP_LOCK_GPIO2 = 2, + CHIP_LOCK_GPIO3 = 3, + CHIP_LOCK_GPIO4 = 4, + CHIP_LOCK_GPIO5 = 5, + CHIP_LOCK_GPIO6 = 6, + CHIP_LOCK_GPIO7 = 7, + CHIP_LOCK_TOTAL +} CHIP_LockType; + +#endif /* McuMagicTag_LOCKTYPE_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/startup.S b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/startup.S new file mode 100644 index 00000000..4e2a2922 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/startup.S @@ -0,0 +1,851 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file startup.S + * @author MCU Application Driver Team + * @brief RISC-V trap handling and startup code + */ + +#ifndef ENTRY_S +#define ENTRY_S + +#include "feature.h" +#ifdef NOS_TASK_SUPPORT +.extern OsHwiPostHandle +.extern OsTaskTrueSwitch +#define NOS_HwiPostDispatch OsHwiPostHandle +#define NOS_TaskDispatch OsTaskTrueSwitch +#define NOS_TASK_SWITCH_MAGIC_NUM 0xACBCCCDC +#define TICK_IRQ_EN_BASE 0xBE0 +#define TICK_IRQ_EN_NUM 0x8 +#endif + +.extern __stack_top +.extern __init_stack_top +.extern __irq_stack_top +.extern SysErrNmiEntry +.extern SysErrExcEntry +.extern trap_entry +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) +.extern g_RiscvPrivMode +#endif + +#ifdef __riscv64 +#define LREG ld +#define SREG sd +#define FLREG fld +#define FSREG fsd +#define REGBYTES 8 +#else +#define LREG lw +#define SREG sw +#define FLREG flw +#define FSREG fsw +#define REGBYTES 4 +#endif + +#define NESTED_IRQ_SUPPORT +#define COMPILE_LDM /**< Support stmia and ldmia instruction */ + +#ifdef NOS_TASK_SUPPORT /* Support Multi-task needs more stack to restore TickIRQEnable */ +#ifdef FLOAT_SUPPORT +#define TOTAL_INT_SIZE_ON_STACK (44 * REGBYTES) +#else +#define TOTAL_INT_SIZE_ON_STACK (24 * REGBYTES) +#endif +#else +#ifdef FLOAT_SUPPORT +#define TOTAL_INT_SIZE_ON_STACK (40 * REGBYTES) +#else +#define TOTAL_INT_SIZE_ON_STACK (20 * REGBYTES) +#endif +#endif + +#define SYSERR_INT_SIZE_ON_STACK (28 * REGBYTES) + +#define MSTATUS_MPP_MACHINE 0x00001800 +#define MCAUSE_ECALL_FROM_MMODE 11 +#define MCAUSE_ECALL_FROM_UMODE 8 +#define EXC_SIZE_ON_STACK (160) + +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_MPIE 0x00000080 +#define MCAUSE_MASK_INT_BIT 0x80000000 +#define MCAUSE_MASK_INT_NUM 0x000000FF + +#define locipri0 0xBC0 +#define locipri1 0xBC1 +#define locipri2 0xBC2 +#define locipri3 0xBC3 +#define locipri4 0xBC4 +#define locipri5 0xBC5 +#define locipri6 0xBC6 +#define locipri7 0xBC7 +#define locipri8 0xBC8 +#define locipri9 0xBC9 +#define locipri10 0xBCA +#define locipri11 0xBCB +#define locipri12 0xBCC +#define locipri13 0xBCD +#define locipri14 0xBCE +#define locipri15 0xBCF + +#define EFC_BASE_ADDR 0x14710000 /* efc base address */ +#define EFC_MAGIC_LOCK_RW 0x14710200 /* cmd operation magic word protection register */ +#define EFC_MAGIC_NUMBER 0xFEDCBA98 /* magic number */ +#define SYSRAM_ERROR 0x10108300 +#define SC_SYS_STAT_ADDR 0x10100018 /**< System state register address */ +#define TIMER0_CONTROL 0x14300008 +#define TIMER0_INTENABLE (1 << 5) +#define UART0_BASE_ADDR 0x14000000 +#define IBRD_OFFSET 0x24 +#define FBRD_OFFSET 0x28 +#define LCR_H_OFFSET 0x2C +#define CR_OFFSET 0x30 +#define DMACR_OFFSET 0x48 + +.equ cipri, 0x7ED +.equ prithd, 0xBFE + + .section .data.magic + .word 0xA37E95BD /* eflash magic number, bootrom will check it */ + + .section .text.entry + .global _start + .option norvc +_start: + j handle_reset + +.macro push_reg + addi sp, sp, -(TOTAL_INT_SIZE_ON_STACK) +#ifdef COMPILE_LDM + stmia {ra, t0-t2, a0-a7, t3-t6}, (sp) +#else + SREG ra, 0 * REGBYTES(sp) + SREG t0, 1 * REGBYTES(sp) + SREG t1, 2 * REGBYTES(sp) + SREG t2, 3 * REGBYTES(sp) + SREG a0, 4 * REGBYTES(sp) + SREG a1, 5 * REGBYTES(sp) + SREG a2, 6 * REGBYTES(sp) + SREG a3, 7 * REGBYTES(sp) + SREG a4, 8 * REGBYTES(sp) + SREG a5, 9 * REGBYTES(sp) + SREG a6, 10 * REGBYTES(sp) + SREG a7, 11 * REGBYTES(sp) + SREG t3, 12 * REGBYTES(sp) + SREG t4, 13 * REGBYTES(sp) + SREG t5, 14 * REGBYTES(sp) + SREG t6, 15 * REGBYTES(sp) +#endif + addi sp, sp, -(TOTAL_INT_SIZE_ON_STACK) +.endm + +.macro pop_reg + addi sp, sp, TOTAL_INT_SIZE_ON_STACK +#ifdef COMPILE_LDM + ldmia {ra, t0-t2, a0-a7, t3-t6},(sp) +#else + LREG ra, 0 * REGBYTES(sp) + LREG t0, 1 * REGBYTES(sp) + LREG t1, 2 * REGBYTES(sp) + LREG t2, 3 * REGBYTES(sp) + LREG a0, 4 * REGBYTES(sp) + LREG a1, 5 * REGBYTES(sp) + LREG a2, 6 * REGBYTES(sp) + LREG a3, 7 * REGBYTES(sp) + LREG a4, 8 * REGBYTES(sp) + LREG a5, 9 * REGBYTES(sp) + LREG a6, 10 * REGBYTES(sp) + LREG a7, 11 * REGBYTES(sp) + LREG t3, 12 * REGBYTES(sp) + LREG t4, 13 * REGBYTES(sp) + LREG t5, 14 * REGBYTES(sp) + LREG t6, 15 * REGBYTES(sp) +#endif + addi sp, sp, TOTAL_INT_SIZE_ON_STACK +.endm + +.macro SAVE_SYSERR_REGS + addi sp,sp,-(SYSERR_INT_SIZE_ON_STACK) + SREG s0, 16 * REGBYTES(sp) + SREG s1, 17 * REGBYTES(sp) + SREG s2, 18 * REGBYTES(sp) + SREG s3, 19 * REGBYTES(sp) + SREG s4, 20 * REGBYTES(sp) + SREG s5, 21 * REGBYTES(sp) + SREG s6, 22 * REGBYTES(sp) + SREG s7, 23 * REGBYTES(sp) + SREG s8, 24 * REGBYTES(sp) + SREG s9, 25 * REGBYTES(sp) + SREG s10, 26 * REGBYTES(sp) + SREG s11, 27 * REGBYTES(sp) + + addi a1, sp, (TOTAL_INT_SIZE_ON_STACK + SYSERR_INT_SIZE_ON_STACK) + SREG a1, 28 * REGBYTES(sp) /* save original sp */ + + SREG gp, 29 * REGBYTES(sp) + SREG tp, 30 * REGBYTES(sp) + + csrr a0, mepc + csrr a1, mstatus + csrr a2, mtval + csrr a3, mcause + # csrr a4, ccause + + SREG a0, 31 * REGBYTES(sp) /* mepc */ + SREG a1, 32 * REGBYTES(sp) /* mstatus */ + SREG a2, 33 * REGBYTES(sp) /* mtval */ + SREG a3, 34 * REGBYTES(sp) /* mcause */ + # SREG a4, 35 * REGBYTES(sp) /* ccause */ + mv a0,sp +.endm + +/* The interrupt vector table must be aligned with 4 bytes */ +.align 2 +TrapHandler: + j TrapVector /* trap and INT 0 */ + j TrapVector /* INT 1 */ + j TrapVector /* INT 2 */ + j TrapVector /* INT 3 */ + j TrapVector /* INT 4 */ + j TrapVector /* INT 5 */ + j TrapVector /* INT 6 */ + j TrapVector /* INT 7 */ + j TrapVector /* INT 8 */ + j TrapVector /* INT 9 */ + j TrapVector /* INT 10 */ + j TrapVector /* INT 11 */ + j TrapVector /* INT 12 */ + j TrapVector /* INT 13 */ + j TrapVector /* INT 14 */ + j TrapVector /* INT 15 */ + j TrapVector /* INT 16 */ + j TrapVector /* INT 17 */ + j TrapVector /* INT 18 */ + j TrapVector /* INT 19 */ + j TrapVector /* INT 20 */ + j TrapVector /* INT 21 */ + j TrapVector /* INT 22 */ + j TrapVector /* INT 23 */ + j TrapVector /* INT 24 */ + j TrapVector /* INT 25 */ + + j IntHandler /* INT 26 */ + j IntHandler /* INT 27 */ + j IntHandler /* INT 28 */ + j IntHandler /* INT 29 */ + j IntHandler /* INT 30 */ + j IntHandler /* INT 31 */ + j IntHandler /* INT 32 */ + j IntHandler /* INT 33 */ + j IntHandler /* INT 34 */ + j IntHandler /* INT 35 */ + j IntHandler /* INT 36 */ + j IntHandler /* INT 37 */ + j IntHandler /* INT 38 */ + j IntHandler /* INT 39 */ + j IntHandler /* INT 40 */ + j IntHandler /* INT 41 */ + j IntHandler /* INT 42 */ + j IntHandler /* INT 43 */ + j IntHandler /* INT 44 */ + j IntHandler /* INT 45 */ + j IntHandler /* INT 46 */ + j IntHandler /* INT 47 */ + j IntHandler /* INT 48 */ + j IntHandler /* INT 49 */ + j IntHandler /* INT 50 */ + j IntHandler /* INT 51 */ + j IntHandler /* INT 52 */ + j IntHandler /* INT 53 */ + j IntHandler /* INT 54 */ + j IntHandler /* INT 55 */ + j IntHandler /* INT 56 */ + j IntHandler /* INT 57 */ + j IntHandler /* INT 58 */ + j IntHandler /* INT 59 */ + j IntHandler /* INT 60 */ + j IntHandler /* INT 61 */ + j IntHandler /* INT 62 */ + j IntHandler /* INT 63 */ + j IntHandler /* INT 64 */ + j IntHandler /* INT 65 */ + j IntHandler /* INT 66 */ + j IntHandler /* INT 67 */ + j IntHandler /* INT 68 */ + j IntHandler /* INT 69 */ + j IntHandler /* INT 70 */ + j IntHandler /* INT 71 */ + j IntHandler /* INT 72 */ + j IntHandler /* INT 73 */ + j IntHandler /* INT 74 */ + j IntHandler /* INT 75 */ + j IntHandler /* INT 76 */ + j IntHandler /* INT 77 */ + j IntHandler /* INT 78 */ + j IntHandler /* INT 79 */ + j IntHandler /* INT 80 */ + j IntHandler /* INT 81 */ + j IntHandler /* INT 82 */ + j IntHandler /* INT 83 */ + j IntHandler /* INT 84 */ + j IntHandler /* INT 85 */ + j IntHandler /* INT 86 */ + j IntHandler /* INT 87 */ + j IntHandler /* INT 88 */ + j IntHandler /* INT 89 */ + j IntHandler /* INT 90 */ + j IntHandler /* INT 91 */ + j IntHandler /* INT 92 */ + j IntHandler /* INT 93 */ + j IntHandler /* INT 94 */ + j IntHandler /* INT 95 */ + j IntHandler /* INT 96 */ + j IntHandler /* INT 97 */ + j IntHandler /* INT 98 */ + j IntHandler /* INT 99 */ + j IntHandler /* INT 100 */ + j IntHandler /* INT 101 */ + j IntHandler /* INT 102 */ + j IntHandler /* INT 103 */ + j IntHandler /* INT 104 */ + j IntHandler /* INT 105 */ + j IntHandler /* INT 106 */ + j IntHandler /* INT 107 */ + j IntHandler /* INT 108 */ + j IntHandler /* INT 109 */ + j IntHandler /* INT 110 */ + j IntHandler /* INT 111 */ + j IntHandler /* INT 112 */ + j IntHandler /* INT 113 */ + j IntHandler /* INT 114 */ + j IntHandler /* INT 115 */ + j IntHandler /* INT 116 */ + j IntHandler /* INT 117 */ + j IntHandler /* INT 118 */ + j IntHandler /* INT 119 */ + j IntHandler /* INT 120 */ + j IntHandler /* INT 121 */ + +.align 2 +NmiEntry: + SAVE_SYSERR_REGS + call SysErrNmiEntry +deadLoop1: + tail deadLoop1 + nop + +.align 2 +TrapEntry: + SAVE_SYSERR_REGS + /* Exception run with interrupts masked */ + csrc mstatus, MSTATUS_MIE + call SysErrExcEntry +deadLoop2: + tail deadLoop2 + +.align 2 +IntHandler: + addi sp, sp, -(TOTAL_INT_SIZE_ON_STACK) + + SREG a0, 3 * REGBYTES(sp) + SREG a1, 4 * REGBYTES(sp) + +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + la a0, g_RiscvPrivMode + lw a1, (a0) + addi a1, a1, 1 + sw a1, (a0) +#endif + + csrr a0, cipri + csrr a1, prithd + csrw prithd, a0 /* read prithd */ + SREG a1, 6 * REGBYTES(sp) /* save prithd */ + csrr a1, mstatus /* read mstatus */ + SREG a1, 7 * REGBYTES(sp) /* save mstatus */ + csrr a1, mepc /* read mepc */ + SREG a1, 8 * REGBYTES(sp) /* save mepc */ + + csrr a0, mcause + + li a1, (3<<11) + csrs mstatus, a1 + #ifndef NOS_TASK_SUPPORT /* When using NOS_TASK_SUPPORT, enable gloal irq after change to irq stack */ + la a1, custom_nested_irq_main_handler_entry + csrw mepc, a1 + mret + #endif + +.align 2 +custom_nested_irq_main_handler_entry: + SREG t0, 0 * REGBYTES(sp) + SREG t1, 1 * REGBYTES(sp) + SREG t2, 2 * REGBYTES(sp) + SREG a2, 5 * REGBYTES(sp) + SREG ra, 9 * REGBYTES(sp) + SREG a3, 10 * REGBYTES(sp) + SREG a4, 11 * REGBYTES(sp) + SREG a5, 12 * REGBYTES(sp) + SREG a6, 13 * REGBYTES(sp) + SREG a7, 14 * REGBYTES(sp) + SREG t3, 15 * REGBYTES(sp) + SREG t4, 16 * REGBYTES(sp) + SREG t5, 17 * REGBYTES(sp) + SREG t6, 18 * REGBYTES(sp) +#ifdef NOS_TASK_SUPPORT /* Support Multi-task needs to save TickIRQEnable */ + csrr t0, TICK_IRQ_EN_BASE + andi t0, t0, TICK_IRQ_EN_NUM + SREG t0, 19 * REGBYTES(sp) +#endif + +#ifdef FLOAT_SUPPORT +#ifdef NOS_TASK_SUPPORT /* Support Multi-task needs to save TickIRQEnable */ + FSREG f0, 23 * REGBYTES(sp) + FSREG f1, 24 * REGBYTES(sp) + FSREG f2, 25 * REGBYTES(sp) + FSREG f3, 26 * REGBYTES(sp) + FSREG f4, 27 * REGBYTES(sp) + FSREG f5, 28 * REGBYTES(sp) + FSREG f6, 29 * REGBYTES(sp) + FSREG f7, 30 * REGBYTES(sp) + FSREG f10, 31 * REGBYTES(sp) + FSREG f11, 32 * REGBYTES(sp) + FSREG f12, 33 * REGBYTES(sp) + FSREG f13, 34 * REGBYTES(sp) + FSREG f14, 35 * REGBYTES(sp) + FSREG f15, 36 * REGBYTES(sp) + FSREG f16, 37 * REGBYTES(sp) + FSREG f17, 38 * REGBYTES(sp) + FSREG f28, 39 * REGBYTES(sp) + FSREG f29, 40 * REGBYTES(sp) + FSREG f30, 41 * REGBYTES(sp) + FSREG f31, 42 * REGBYTES(sp) + frcsr t0 + SREG t0, 43 * REGBYTES(sp) +#else + FSREG f0, 19 * REGBYTES(sp) + FSREG f1, 20 * REGBYTES(sp) + FSREG f2, 21 * REGBYTES(sp) + FSREG f3, 22 * REGBYTES(sp) + FSREG f4, 23 * REGBYTES(sp) + FSREG f5, 24 * REGBYTES(sp) + FSREG f6, 25 * REGBYTES(sp) + FSREG f7, 26 * REGBYTES(sp) + FSREG f10, 27 * REGBYTES(sp) + FSREG f11, 28 * REGBYTES(sp) + FSREG f12, 29 * REGBYTES(sp) + FSREG f13, 30 * REGBYTES(sp) + FSREG f14, 31 * REGBYTES(sp) + FSREG f15, 32 * REGBYTES(sp) + FSREG f16, 33 * REGBYTES(sp) + FSREG f17, 34 * REGBYTES(sp) + FSREG f28, 35 * REGBYTES(sp) + FSREG f29, 36 * REGBYTES(sp) + FSREG f30, 37 * REGBYTES(sp) + FSREG f31, 38 * REGBYTES(sp) + frcsr t0 + SREG t0, 39 * REGBYTES(sp) /* save fcsr */ +#endif +#endif + +#ifdef NOS_TASK_SUPPORT + LREG a2, 6 * REGBYTES(sp) + bnez a2, IrqCallback /* Should determine whether need to switch stack */ + csrw mscratch, sp + la sp, __irq_stack_top - 16 + +IrqCallback: + addi sp, sp, -4 * REGBYTES + SREG a2, 0 * REGBYTES(sp) /* save prithd in irq stack */ + andi a0, a0, MCAUSE_MASK_INT_NUM + la a1, IrqCallbackNew /* When using NOS_TASK_SUPPORT, enable gloal irq after change to irq stack */ + csrw mepc, a1 + mret + +IrqCallbackNew: + call InterruptEntry + li a2, 0x8 + csrrc zero, mstatus, a2 /* When using NOS_TASK_SUPPORT, disable gloal irq before any stack operation */ + LREG a2, 0 * REGBYTES(sp) /* restore prithd in irq stack */ + addi sp, sp, 4 * REGBYTES + + bnez a2, BacktoIrq + csrr sp, mscratch + tail NOS_HwiPostDispatch /* Should determine whether need to reschedule */ +#else + andi a0, a0, MCAUSE_MASK_INT_NUM + call InterruptEntry +#endif + +BacktoIrq: + LREG t1, 1 * REGBYTES(sp) + LREG t2, 2 * REGBYTES(sp) + LREG a2, 5 * REGBYTES(sp) + LREG ra, 9 * REGBYTES(sp) + LREG a3, 10 * REGBYTES(sp) + LREG a4, 11 * REGBYTES(sp) + LREG a5, 12 * REGBYTES(sp) + LREG a6, 13 * REGBYTES(sp) + LREG a7, 14 * REGBYTES(sp) + LREG t3, 15 * REGBYTES(sp) + LREG t4, 16 * REGBYTES(sp) + LREG t5, 17 * REGBYTES(sp) + LREG t6, 18 * REGBYTES(sp) +#ifdef NOS_TASK_SUPPORT /* Support Multi-task needs to restore TickIRQEnable */ + LREG t0, 19 * REGBYTES(sp) + andi t0, t0, TICK_IRQ_EN_NUM + csrs TICK_IRQ_EN_BASE, t0 +#endif + +#ifdef FLOAT_SUPPORT +#ifdef NOS_TASK_SUPPORT /* Support Multi-task needs to save TickIRQEnable */ + FLREG f0, 23 * REGBYTES(sp) + FLREG f1, 24 * REGBYTES(sp) + FLREG f2, 25 * REGBYTES(sp) + FLREG f3, 26 * REGBYTES(sp) + FLREG f4, 27 * REGBYTES(sp) + FLREG f5, 28 * REGBYTES(sp) + FLREG f6, 29 * REGBYTES(sp) + FLREG f7, 30 * REGBYTES(sp) + FLREG f10, 31 * REGBYTES(sp) + FLREG f11, 32 * REGBYTES(sp) + FLREG f12, 33 * REGBYTES(sp) + FLREG f13, 34 * REGBYTES(sp) + FLREG f14, 35 * REGBYTES(sp) + FLREG f15, 36 * REGBYTES(sp) + FLREG f16, 37 * REGBYTES(sp) + FLREG f17, 38 * REGBYTES(sp) + FLREG f28, 39 * REGBYTES(sp) + FLREG f29, 40 * REGBYTES(sp) + FLREG f30, 41 * REGBYTES(sp) + FLREG f31, 42 * REGBYTES(sp) + LREG t0, 43 * REGBYTES(sp) + fscsr t0 +#else + FLREG f0, 19 * REGBYTES(sp) + FLREG f1, 20 * REGBYTES(sp) + FLREG f2, 21 * REGBYTES(sp) + FLREG f3, 22 * REGBYTES(sp) + FLREG f4, 23 * REGBYTES(sp) + FLREG f5, 24 * REGBYTES(sp) + FLREG f6, 25 * REGBYTES(sp) + FLREG f7, 26 * REGBYTES(sp) + FLREG f10, 27 * REGBYTES(sp) + FLREG f11, 28 * REGBYTES(sp) + FLREG f12, 29 * REGBYTES(sp) + FLREG f13, 30 * REGBYTES(sp) + FLREG f14, 31 * REGBYTES(sp) + FLREG f15, 32 * REGBYTES(sp) + FLREG f16, 33 * REGBYTES(sp) + FLREG f17, 34 * REGBYTES(sp) + FLREG f28, 35 * REGBYTES(sp) + FLREG f29, 36 * REGBYTES(sp) + FLREG f30, 37 * REGBYTES(sp) + FLREG f31, 38 * REGBYTES(sp) + LREG t0, 39 * REGBYTES(sp) /* restore fcsr */ + fscsr t0 +#endif +#endif + +quit_int: + /* + * Since the interrupt is already turned off when loading mstatus (after entering the interrupt, + * the hardware will turn off the interrupt, so when saving mstatus, the interrupt is already turned off), + * so there is no need to turn off the interrupt separately. + */ + LREG a0, 7 * REGBYTES(sp) /* load mstatus */ + LREG a1, 8 * REGBYTES(sp) /* load mepc */ + #ifndef NOS_TASK_SUPPORT /* When using NOS_TASK_SUPPORT, don't check mstatus */ + csrr t0, mstatus + andi t0, t0, MSTATUS_MIE + bnei t0, 0, restore_mstatus + andi a0, a0, ~(MSTATUS_MIE | MSTATUS_MPIE) + #endif +restore_mstatus: + csrw mstatus, a0 + + LREG t0, 0 * REGBYTES(sp) + csrw mepc, a1 + LREG a0, 6 * REGBYTES(sp) /* load prithd */ + csrw prithd, a0 +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + la a0, g_RiscvPrivMode + lw a1, (a0) + addi a1, a1, -1 + sw a1, (a0) +#endif + + LREG a1, 4 * REGBYTES(sp) /* 2 consecutive csrw instructions will have a bubble */ + + LREG a0, 3 * REGBYTES(sp) + + addi sp, sp, TOTAL_INT_SIZE_ON_STACK + + mret + +.align 2 +TrapVector: + +#ifdef NOS_TASK_SUPPORT /* Support Multi-task needs to check mcause == ecall and a0 = magic word for taskSwitch */ + addi sp, sp, -8 + SREG a1, 0(sp) + SREG a2, 4(sp) + csrr a1, mcause + li a2, MCAUSE_ECALL_FROM_MMODE + bne a1, a2, IsTrap + li a2, NOS_TASK_SWITCH_MAGIC_NUM + bne a0, a2, IsTrap + LREG a2, 4(sp) + LREG a1, 0(sp) + addi sp, sp, 8 + tail NOS_TaskDispatch + +IsTrap: + LREG a2, 4(sp) + LREG a1, 0(sp) + addi sp, sp, 8 +#endif + + push_reg + csrr a0, mcause + li t1, MCAUSE_ECALL_FROM_MMODE +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + beq a0, t1, switch_to_umode +#else + beq a0, t1, switch_to_mmode +#endif + li t1, MCAUSE_ECALL_FROM_UMODE + beq a0, t1, switch_to_mmode + + li a1, MCAUSE_MASK_INT_BIT + li a2, MCAUSE_MASK_INT_NUM + and a1, a0, a1 + and a0, a0, a2 + + li a2, 0xc + beq a0, a2, NmiEntry + beqz a1, TrapEntry + pop_reg + mret + +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) +.align 2 +switch_to_umode: + li t2, MSTATUS_MPP_MACHINE + csrc mstatus, t2 + csrr t0, mepc + addi t0, t0, 4 + csrw mepc, t0 + pop_reg + mret +#endif + +.align 2 +switch_to_mmode: + li t2, MSTATUS_MPP_MACHINE + csrs mstatus, t2 + csrr t0, mepc + addi t0, t0, 4 + csrw mepc, t0 + pop_reg + mret + +.align 2 +mem_cpy: + bge t0, t2, cpy_done + lw t3, (t1) + sw t3, (t0) + addi t0, t0, 4 + addi t1, t1, 4 + j mem_cpy +cpy_done: + ret + +.align 2 +handle_reset: + csrwi mstatus, 0 + csrwi mie, 0 + csrci mstatus, 0x08 + la t0, TrapHandler + addi t0, t0, 1 + csrw mtvec, t0 + csrwi 0x7EF, 0x1 /* lock mtvec */ + +flash_init: +/* eflash prefetch enable */ + li t0, EFC_BASE_ADDR + lw t1, 0x120(t0) + ori t1, t1, 1 + sw t1, 0x120(t0) + +/* eflash cache enable */ + lw t1, 0x124(t0) + ori t1, t1, 1 + sw t1, 0x124(t0) + +/* enable flash cmd */ + li t0, EFC_MAGIC_NUMBER + li t1, EFC_MAGIC_LOCK_RW + sw t0, (t1) + +/* initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + .option pop + +/* initialize stack pointer */ +#ifdef NOS_TASK_SUPPORT /* Support Multi-task needs to use irq stack */ + la sp, __init_stack_top +#else + la sp, __stack_top +#endif + +/* timer0 interrupt enable */ + li t0, TIMER0_CONTROL + lw t1, (t0) + andi t1, t1, TIMER0_INTENABLE + sw t1, (t0) + +/* uart0 deinit */ + li t0, 0x14000000 + li t1, 0 + sw t1, IBRD_OFFSET(t0) + sw t1, FBRD_OFFSET(t0) + sw t1, LCR_H_OFFSET(t0) + sw t1, CR_OFFSET(t0) + sw t1, DMACR_OFFSET(t0) + +/* perform the rest of initialization in C */ +clear_sram: + /* clear sysram parity error */ + li t0, SYSRAM_ERROR + lw t1, (t0) + ori t1, t1, 1 + sw t1, (t0) + + la t0, SRAM_START + la t1, SRAM_END + li t2, 0 + +clear_sram_loop: + sw t2, (t0) /* clear all sram */ + addi t0, t0, 4 /* increment clear index pointer */ + blt t0, t1, clear_sram_loop /* are we at the end yet, if not , continue till the end */ + +ramdcode_copy: + la t0, __sram_code_start /* SRAM addr */ + la t1, __sram_code_load /* ROM addr */ + la t2, __sram_code_end + jal mem_cpy + +reserved_data_copy: + la t0, __reserved_code_start_addr /* SRAM addr */ + la t1, __reserved_code_load_addr /* ROM addr */ + la t2, __reserved_code_end_addr + jal mem_cpy + +coderom_data_copy: + la t0, __data_start /* SRAM addr */ + la t1, __data_load /* ROM addr */ + la t2, __data_end + jal mem_cpy + +stack_sram_bound_data_copy: + la t0, __stack_sram_bound_data_start /* SRAM addr */ + la t1, __stack_sram_bound_data_load /* ROM addr */ + la t2, __stack_sram_bound_data_end + jal mem_cpy + +pmp_init: +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + li t0, 0xB00 + csrw pmpaddr0, t0 + li t0,0x400400 /* 2C00?~0x1000FFF, BOOTROM, enable R+X */ + csrw pmpaddr1, t0 + li t0,0x800000 /* 0x1001000~0x1FFFFFF, Reserved: disable R+X+W */ + csrw pmpaddr2, t0 + li t0,0x801000 /* 0x2000000~0x2003FFF, SYSRAM_ITCM? */ + csrw pmpaddr3, t0 + li t0, 0xC00000 /* 0x2004000 ~ 0x2FFFFFF, Reserved: disable R+X+W */ + csrw pmpaddr4, t0 + li t0, 0x1000000 /* 0x3000000 ~ 0x03FFFFFF: EFLASH: enable R+X */ + csrw pmpaddr5, t0 + li t0,0x1001000 /* 0x4000000 ~ 0x0x04003FFF: SYSTEM_DTCM enable R+W */ + csrw pmpaddr6, t0 + li t0,0x7080000 /* 0x0d:TOR-R-X; 0x0b:TOR-R-W; 0x08:TOR; 0x0c:TOR-x; 0x09:TOR-R */ + csrw pmpaddr7, t0 + + li t0,0xf3333333 /* register TOR-R-W */ + csrw 0x7d8,t0 + + li t0,0x0d080d8b /* 0x0d:TOR-R-X; 0x0b:TOR-R-W; 0x08:TOR; 0x0c:TOR-x; 0x09:TOR-R */ + csrw pmpcfg0,t0 + li t0,0x0b0b0d08 + csrw pmpcfg1,t0 +#endif + +/* disable Icache */ + csrwi 0x7C0, 0x0 /* disable ICACHE */ + fence + +/* disable Dcache */ + csrwi 0x7C1, 0x0 /* disable DCACHE */ + fence + +/* support float and mie */ + li t0,0x2008 + csrs mstatus,t0 + li t0,0x20 + csrs misa,t0 + +/* Interrupt set default priority = 1*/ + li t0, 0x11111111 + csrw locipri0, t0 + csrw locipri1, t0 + csrw locipri2, t0 + csrw locipri3, t0 + csrw locipri4, t0 + csrw locipri5, t0 + csrw locipri6, t0 + csrw locipri7, t0 + csrw locipri8, t0 + csrw locipri9, t0 + csrw locipri10, t0 + csrw locipri11, t0 + csrw locipri12, t0 + csrw locipri13, t0 + csrw locipri14, t0 + csrw locipri15, t0 + + ecall + +#ifdef NOS_TASK_SUPPORT + jal Chip_Init +#else + jal Chip_Init + +/* jump to C func. */ + jal main +#endif + +dead_loop: + j dead_loop + +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/sysctrl.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/sysctrl.h new file mode 100644 index 00000000..112e4efc --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/sysctrl.h @@ -0,0 +1,745 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file sysctrl.h + * @author MCU Driver Team + * @brief This file provides firmware functions to manage the following + * functionalities of the system control register. + * + Register Struct of SYSCTRL + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_SYSCTRL_H +#define McuMagicTag_SYSCTRL_H + +/* Includes ------------------------------------------------------------------ */ +#include "baseaddr.h" +#include "typedefs.h" + +/* Macro definitions ---------------------------------------------------------*/ +#define SC_LOCKEN_VALID_HIGH_BIT 0xEA510000U /**< Upper 16 active bits of the SC_LOCKEN register */ +#define SC_LOW_BIT_MASK 0x0000FFFFU /**< Obtains the mask of the lower 16 bits. */ +#define SC_LOCKEN_CRG_DISABLE_MASK 0x0000FFFEU /**< CRG write protection disable mask in SC_LOCKEN */ +#define SC_LOCKEN_CRG_ENABLE_MASK 0x00000001U /**< CRG write protection enable mask in SC_LOCKEN */ +#define SC_LOCKEN_SC_DISABLE_MASK 0x0000FFFDU /**< SC write protection disable mask in SC_LOCKEN */ +#define SC_LOCKEN_SC_ENABLE_MASK 0x00000002U /**< SC write protection enable mask in SC_LOCKEN */ + + +/** + * @brief Records the offsets of various states in the CPU status register. + */ +typedef enum { + SYSCTRL_NMI_BIT = 0x00000000U, + SYSCTRL_LOCKUP_BIT = 0x00000002U, + SYSCTRL_HARD_FAULT_BIT = 0x00000003U, + SYSCTRL_DEBUG_BIT = 0x00000004U, + SYSCTRL_SLEEP_BIT = 0x00000005U, + SYSCTRL_PC_VALID_BIT = 0x0000001FU +} SYSCTRL_CPU_Status; + +/** + * @brief FUNC_JTAG_SEL_REG register function item. + */ +typedef enum { + SYSCTRL_FUNC_JTAG_CORESIGHT = 0x00000000U, + SYSCTRL_FUNC_JYAG_EFLASH = 0x00000001U +} SYSCTRL_FUNC_JTAG_Status; + +/** + * @brief System soft reset register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int softresreq : 1; /**< Soft reset of the system. */ + unsigned int reserved : 31; + } BIT; +} volatile SC_SYS_RES_REG; + +/** + * @brief Record the number of resets(soft reset, pin reset). + */ +typedef union { + unsigned int reg; + struct { + unsigned int soft_rst_cnt : 16; /**< Number of soft reset. */ + unsigned int ext_rst_cnt : 16; /**< Number of the RESETN pin reset. */ + } BIT; +} volatile SC_RST_CNT0_REG; + +/** + * @brief Record the number of resets(wdg reset, iwdg reset). + */ +typedef union { + unsigned int reg; + struct { + unsigned int wdg_rst_cnt : 16; /**< Number of wdg reset. */ + unsigned int iwdg_rst_cnt : 16; /**< Number of iwdg reset. */ + } BIT; +} volatile SC_RST_CNT1_REG; + +/** + * @brief System status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int update_mode_clear : 1; /**< System update mark clear register. */ + unsigned int reserved0 : 3; + unsigned int update_mode : 1; /**< System update mark. */ + unsigned int reserved1 : 27; + } BIT; +} volatile SC_SYS_STAT_REG; + +/** + * @brief Software interrupt register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int software_int : 1; /**< Software interrupt register. */ + unsigned int reserved : 31; + } BIT; +} volatile SC_SOFT_INT_REG; + +/** + * @brief Software interrupt event ID register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int swint_evt_id : 32; /**< Software interrupt event ID. */ + } BIT; +} volatile SC_SOFT_EVT_ID_REG; + +/** + * @brief Lock register of key registers. + */ +typedef union { + unsigned int reg; + struct { + unsigned int crg_cfg_lock : 1; /**< CRG register write-protection. */ + unsigned int sc_cfg_lock : 1; /**< SYSCTRL register write-protection. */ + unsigned int reserved : 30; + } BIT; +} volatile SC_LOCKEN_REG; + +/** + * @brief SC dedicated hard reset register 0. (CH) This register is not reset by a system soft reset. + */ +typedef union { + unsigned int reg; + struct { + unsigned int sc_hrst_reg0 : 32; /**< JTAG/SWD interface debug or write system. */ + } BIT; +} volatile SC_HRST_REG0_REG; + +/** + * @brief User dedicated hard reset register 0. (CH) This register is not reset by a system soft reset. + */ +typedef union { + unsigned int reg; + struct { + unsigned int user_hrst_reg0 : 32; /**< User dedicated hard reset register 0. */ + } BIT; +} volatile USER_HRST_REG0_REG; + +/** + * @brief User dedicated hard reset register 1. (CH) This register is not reset by a system soft reset. + */ +typedef union { + unsigned int reg; + struct { + unsigned int user_hrst_reg1 : 32; /**< User dedicated hard reset register 1. */ + } BIT; +} volatile USER_HRST_REG1_REG; + +/** + * @brief User dedicated POR reset register 0. (CH) This register is reset only by a POR reset. + */ +typedef union { + unsigned int reg; + struct { + unsigned int user_por_reg0 : 32; /**< User dedicated POR reset register 0. */ + } BIT; +} volatile USER_POR_REG0_REG; + +/** + * @brief User dedicated POR reset register 1. (CH) This register is reset only by a POR reset. + */ +typedef union { + unsigned int reg; + struct { + unsigned int user_por_reg1 : 32; /**< User dedicated POR reset register 1. */ + } BIT; +} volatile USER_POR_REG1_REG; + +/** + * @brief User dedicated register 0. + */ +typedef union { + unsigned int reg; + struct { + unsigned int user_reg0 : 32; /**< User dedicated register 0. */ + } BIT; +} volatile USER_REG0_REG; + +/** + * @brief User dedicated register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int user_reg1 : 32; /**< User dedicated register 1. */ + } BIT; +} volatile USER_REG1_REG; + +/** + * @brief SYSCTRL0 register. + */ +typedef struct _SYSCTRL0_Regstruct { + char space0[4]; + SC_SYS_RES_REG SC_SYS_RES; /**< System soft reset register. */ + SC_RST_CNT0_REG SC_RST_CNT0; /**< Record the number of resets(soft reset, pin reset). */ + SC_RST_CNT1_REG SC_RST_CNT1; /**< Record the number of resets(wdg reset, iwdg reset). */ + char space1[8]; + SC_SYS_STAT_REG SC_SYS_STAT; /**< System status register. */ + char space2[4]; + SC_SOFT_INT_REG SC_SOFT_INT; /**< Software interrupt register. */ + SC_SOFT_EVT_ID_REG SC_SOFT_EVT_ID; /**< Software interrupt event ID register. */ + char space3[28]; + SC_LOCKEN_REG SC_LOCKEN; /**< Lock register of key registers. */ + char space4[440]; + SC_HRST_REG0_REG SC_HRST_REG0; /**< SC dedicated hard reset register 0. */ + char space5[3068]; + USER_POR_REG0_REG USER_POR_REG0; /**< User dedicated POR reset register 0, offset address: 0x0E00. */ + USER_POR_REG1_REG USER_POR_REG1; /**< User dedicated POR reset register 1, offset address: 0x0E04. */ + char space6[56]; + USER_HRST_REG0_REG USER_HRST_REG0; /**< User dedicated hard reset register 0, offset address: 0x0E40. */ + USER_HRST_REG1_REG USER_HRST_REG1; /**< User dedicated hard reset register 1, offset address: 0x0E44. */ + char space7[56]; + USER_REG0_REG USER_REG0; /**< User dedicated register 0. */ + USER_REG1_REG USER_REG1; /**< User dedicated register 1. */ +} volatile SYSCTRL0_RegStruct; + +/** + * @brief APT enable control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int apt0_run : 1; /**< APT0 enable. */ + unsigned int apt1_run : 1; /**< APT1 enable. */ + unsigned int apt2_run : 1; /**< APT2 enable. */ + unsigned int apt3_run : 1; /**< APT3 enable. */ + unsigned int apt4_run : 1; /**< APT4 enable. */ + unsigned int apt5_run : 1; /**< APT5 enable. */ + unsigned int apt6_run : 1; /**< APT6 enable. */ + unsigned int apt7_run : 1; /**< APT7 enable. */ + unsigned int apt8_run : 1; /**< APT8 enable. */ + unsigned int reserved : 23; + } BIT; +} volatile APT_RUN_REG; + +/** + * @brief APT POE filter control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int poe0_filter_level : 8; /**< Number of POE0 filter period. */ + unsigned int poe1_filter_level : 8; /**< Number of POE1 filter period. */ + unsigned int poe2_filter_level : 8; /**< Number of POE2 filter period. */ + unsigned int poe0_filter_en : 1; /**< POE0 filter enable. */ + unsigned int poe1_filter_en : 1; /**< POE1 filter enable. */ + unsigned int poe2_filter_en : 1; /**< POE2 filter enable. */ + unsigned int reserved : 5; + } BIT; +} volatile APT_POE_FILTER_REG; + +/** + * @brief APT_EVTIO filter control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int apt_evtio4_filter_level : 8; /**< Number of APT EVTIO4 filter period. */ + unsigned int apt_evtio5_filter_level : 8; /**< Number of APT EVTIO5 filter period. */ + unsigned int reserved0 : 8; + unsigned int apt_evtio4_filter_en : 1; /**< APT EVTIO4 filter enable. */ + unsigned int apt_evtio5_filter_en : 1; /**< APT EVTIO5 filter enable. */ + unsigned int reserved1 : 6; + } BIT; +} volatile APT_EVTIO_FILTER_REG; + +/** + * @brief APT_EVTMP filter control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int apt_evtmp4_filter_level : 8; /**< Number of APT EVTMP4 filter period. */ + unsigned int apt_evtmp5_filter_level : 8; /**< Number of APT EVTMP5 filter period. */ + unsigned int apt_evtmp6_filter_level : 8; /**< Number of APT EVTMP6 filter period. */ + unsigned int apt_evtmp4_filter_en : 1; /**< APT EVTMP4 filter enable. */ + unsigned int apt_evtmp5_filter_en : 1; /**< APT EVTMP5 filter enable. */ + unsigned int apt_evtmp6_filter_en : 1; /**< APT EVTMP6 filter enable. */ + unsigned int reserved : 5; + } BIT; +} volatile APT_EVTMP_FILTER_REG; + +/** + * @brief CAPM synchronization source select register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int capm0_sync_sel : 2; + unsigned int reserved0 : 2; + unsigned int capm1_sync_sel : 2; + unsigned int reserved1 : 2; + unsigned int capm2_sync_sel : 2; + unsigned int reserved2 : 22; + } BIT; +} volatile CAPM_SYNC_SEL_REG; + +/** + * @brief DMA request source select register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int dma_req0_sel : 1; /**< DMA request line0 source selection. */ + unsigned int dma_req1_sel : 1; /**< DMA request line1 source selection. */ + unsigned int reserved0 : 3; + unsigned int dma_req5_sel : 1; /**< DMA request line5 source selection. */ + unsigned int dma_req6_sel : 1; /**< DMA request line6 source selection. */ + unsigned int dma_req7_sel : 1; /**< DMA request line7 source selection. */ + unsigned int dma_req8_sel : 1; /**< DMA request line8 source selection. */ + unsigned int dma_req9_sel : 1; /**< DMA request line9 source selection. */ + unsigned int dma_req10_sel : 1; /**< DMA request line10 source selection. */ + unsigned int dma_req11_sel : 1; /**< DMA request line11 source selection. */ + unsigned int dma_req12_sel : 1; /**< DMA request line12 source selection. */ + unsigned int dma_req13_sel : 1; /**< DMA request line13 source selection. */ + unsigned int dma_req14_sel : 1; /**< DMA request line14 source selection. */ + unsigned int dma_req15_sel : 1; /**< DMA request line15 source selection. */ + unsigned int reserved1 : 16; + } BIT; +} volatile DMA_REQ_SEL_REG; + +/** + * @brief Sysram odd-even check status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int sysram_parity_err_clr : 1; /**< SYSRAM odd-even check error status clear. */ + unsigned int sysram_parity_err : 1; /**< SYSRAM odd-even check error status. */ + unsigned int reserved : 30; + } BIT; +} volatile SYSRAM_ERR_REG; + +/** + * @brief CPU status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cpu_in_nmi_hdlr : 1; + unsigned int cpu_ra_wr_en : 1; + unsigned int cpu_lockup_mode : 1; /**< CPU lockup status. */ + unsigned int cpu_hard_fault_mode : 1; /**< CPU hard fault status.*/ + unsigned int cpu_debug_mode : 1; /**< CPU debug status.*/ + unsigned int cpu_sleep_mode : 1; /**< CPU sleep status. */ + unsigned int reserved : 25; + unsigned int cpu_pc_valid : 1; /**< CPU PC value effective status. */ + } BIT; +} volatile CPU_STATUS_REG; + +/** + * @brief CPU IRF_X1 value register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cpu_irf_x1 : 32; /**< CPU IRF_X1 value.*/ + } BIT; +} volatile CPU_IRF_X1_REG; + +/** + * @brief CPU IRF_X2 value register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cpu_irf_x2 : 32; /**< CPU IRF_X2 value.*/ + } BIT; +} volatile CPU_IRF_X2_REG; + +/** + * @brief Tsensor enable control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int tsensor_en : 1; /**< Tsensor enable.*/ + unsigned int reserved : 31; + } BIT; +} volatile TSENSOR_EN_REG; + +/** + * @brief ADCVREF bandgap control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int adcvref_bg_en : 1; /**< ADC0 VREF enable. */ + unsigned int reserved0 : 15; + unsigned int adcvref_bg_trim : 5; /**< ADC0 VREF voltage selection. */ + unsigned int reserved1 : 11; + } BIT; +} volatile ADCVREF_CTRL0_REG; + +/** + * @brief ADCLDO control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int adcvref_adcldo_en : 1; /**< ADCLDO enable. */ + unsigned int adcvref_adcldo_bypss : 1; /**< Reserved. */ + unsigned int reserved0 : 2; + unsigned int adcvref_adcldo_s : 4; /**< ADCLDO output voltage tap adjustment. */ + unsigned int reserved1 : 8; + unsigned int adcvref_adcldo_trim : 5; /**< ADCLDO calibration value. */ + unsigned int reserved2 : 3; + unsigned int adcvref_adcldo_ib_sel : 1; /**< ADCLDO low power comsumption mode enable. */ + unsigned int reserved3 : 6; + unsigned int adcvref_adcldo_ok : 1; /**< ADCLDO voltage stability mark. */ + } BIT; +} volatile ADCVREF_CTRL1_REG; + +/** + * @brief ADC0 control registe. + */ +typedef union { + unsigned int reg; + struct { + unsigned int adcvref_refbuf_en0 : 1; /**< ADC0 VREF enable. */ + unsigned int reserved0 : 3; + unsigned int adcvref_refbuf_s0 : 1; /**< ADC0 VREF voltage selection. */ + unsigned int reserved1 : 3; + unsigned int adcvref_refbuf_sel0 : 1; /**< ADC0 VREF source selection. */ + unsigned int reserved2 : 7; + unsigned int adcvref_refbuf_trim0_2p0v : 5; /**< Trim value when ADC0 VREF is 2.0v. */ + unsigned int reserved3 : 3; + unsigned int adcvref_refbuf_trim0_2p5v : 5; /**< Trim value when ADC0 VREF is 2.5v. */ + unsigned int reserved4 : 3; + } BIT; +} volatile ADC0_VREF_CTRL_REG; + +/** + * @brief ADC1 control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int adcvref_refbuf_en1 : 1; /**< ADC1 VREF enable. */ + unsigned int reserved0 : 3; + unsigned int adcvref_refbuf_s1 : 1; /**< ADC1 VREF voltage selection. */ + unsigned int reserved1 : 3; + unsigned int adcvref_refbuf_sel1 : 1; /**< ADC1 VREF source selection. */ + unsigned int reserved2 : 7; + unsigned int adcvref_refbuf_trim1_2p0v : 5; /**< Trim value when ADC1 VREF is 2.0v. */ + unsigned int reserved3 : 3; + unsigned int adcvref_refbuf_trim1_2p5v : 5; /**< Trim value when ADC1 VREF is 2.5v. */ + unsigned int reserved4 : 3; + } BIT; +} volatile ADC1_VREF_CTRL_REG; + +/** + * @brief ADC2 control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int adcvref_refbuf_en2 : 1; /**< ADC2 VREF enable. */ + unsigned int reserved0 : 3; + unsigned int adcvref_refbuf_s2 : 1; /**< ADC2 VREF voltage selection. */ + unsigned int reserved1 : 3; + unsigned int adcvref_refbuf_sel2 : 1; /**< ADC2 VREF source selection. */ + unsigned int reserved2 : 7; + unsigned int adcvref_refbuf_trim2_2p0v : 5; /**< Trim value when ADC2 VREF is 2.0v. */ + unsigned int reserved3 : 3; + unsigned int adcvref_refbuf_trim2_2p5v : 5; /**< Trim value when ADC2 VREF is 2.5v. */ + unsigned int reserved4 : 3; + } BIT; +} volatile ADC2_VREF_CTRL_REG; + +/** + * @brief ADC2CORE control register 6. + */ +typedef union { + unsigned int reg; + struct { + unsigned int adcvref_test_en : 1; /**< ADC VREF test function enable. */ + unsigned int reserved0 : 3; + unsigned int adcvref_test_sel : 4; /**< ADC VREF test function selection. */ + unsigned int reserved1 : 8; + unsigned int adcvref_rsv : 8; /**< ADC VREF reserved. */ + unsigned int reserved2 : 8; + } BIT; +} volatile ADCVREF_CTRL6_REG; + +/** + * @brief ADC2CORE_ISO register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc2core_iso : 1; /**< ADC power feild and CORE power feild isolation control. */ + unsigned int reserved : 31; + } BIT; +} volatile ADC2CORE_ISO_REG; + +/** + * @brief ADC serial observation selection register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_ob_sel : 2; /**< ADC serial output side selection. */ + unsigned int reserved : 30; + } BIT; +} volatile ADC_OB_SEL_REG; + +/** + * @brief SYSCTRL1 register. + */ +typedef struct _SYSCTRL1_RegStruct { + char space0[0x8000]; + APT_RUN_REG APT_RUN; /**< APT enable control register, offset address: 0x8000. */ + char space1[12]; + APT_POE_FILTER_REG APT_POE_FILTER; /**< APT POE filter control register, offset address: 0x8010. */ + APT_EVTIO_FILTER_REG APT_EVTIO_FILTER; /**< APT_EVTIO filter control register, offset address: 0x8014. */ + APT_EVTMP_FILTER_REG APT_EVTMP_FILTER; /**< APT_EVTMP filter control register, offset address: 0x8018. */ + char space2[484]; + DMA_REQ_SEL_REG DMA_REQ_SEL; /**< DMA request source select register, offset address: 0x8200. */ + char space3[252]; + SYSRAM_ERR_REG SYSRAM_ERR; /**< Sysram odd-even check status register, offset address: 0x8300. */ + char space4[3324]; + CPU_STATUS_REG CPU_STATUS; /**< CPU status register, offset address: 0x9000. */ + char space5[4092]; + TSENSOR_EN_REG TSENSOR_EN; /**< Tsensor enable control register, offset address: 0xA000. */ + char space6[4092]; + ADCVREF_CTRL0_REG ADCVREF_CTRL0; /**< ADCVREF bandgap control register, offset address: 0xB000. */ + ADCVREF_CTRL1_REG ADCVREF_CTRL1; /**< ADCLD0 control register, offset address: 0xB004. */ + ADC0_VREF_CTRL_REG ADC0_VREF_CTRL; /**< ADC0 control register, offset address: 0xB008. */ + ADC1_VREF_CTRL_REG ADC1_VREF_CTRL; /**< ADC1 control register, offset address: 0xB00C. */ + ADC2_VREF_CTRL_REG ADC2_VREF_CTRL; /**< ADC2 control register, offset address: 0xB010. */ + char space7[4]; + ADCVREF_CTRL6_REG ADCVREF_CTRL6; /**< ADC2CORE control register 6, offset address: 0xB018. */ + char space8[20444]; + ADC_OB_SEL_REG ADC_OB_SEL; /**< ADC observation selection register, offset address: 0xFFF8. */ +} volatile SYSCTRL1_RegStruct; + +/** + * @brief Make system soft reset. + * @param None. + * @retval None. + */ +static inline void DCL_SYSCTRL_SoftReset(void) +{ + SYSCTRL0->SC_SYS_RES.BIT.softresreq = 1; +} + +/** + * @brief Get number of soft resets. + * @param None. + * @retval Number of soft resets. + */ +static inline unsigned short DCL_SYSCTRL_GetSoftResetConut(void) +{ + return SYSCTRL0->SC_RST_CNT0.BIT.soft_rst_cnt; +} + +/** + * @brief Get number of reset times of the RESETN pin. + * @param None. + * @retval Number of reset times of the RESETN pin. + */ +static inline unsigned short DCL_SYSCTRL_GetPinResetConut(void) +{ + return SYSCTRL0->SC_RST_CNT0.BIT.ext_rst_cnt; +} + +/** + * @brief Get number of WDG resets. + * @param None. + * @retval Number of WDG resets. + */ +static inline unsigned short DCL_SYSCTRL_GetWdgResetConut(void) +{ + return SYSCTRL0->SC_RST_CNT1.BIT.wdg_rst_cnt; +} + +/** + * @brief Get number of IWDG resets. + * @param None. + * @retval Number of IWDG resets. + */ +static inline unsigned short DCL_SYSCTRL_GetIWdgResetConut(void) +{ + return SYSCTRL0->SC_RST_CNT1.BIT.iwdg_rst_cnt; +} + +/** + * @brief Set the write protection for SYSCTRL registers disable. + * @param None. + * @retval None. + */ +static inline void DCL_SYSCTRL_ScWriteProtectionDisable(void) +{ + /* Set the corresponding bit without affecting the other bits and set the high 16 bits to EA51 to write to */ + SYSCTRL0->SC_LOCKEN.reg = (SYSCTRL0->SC_LOCKEN.reg & SC_LOCKEN_SC_DISABLE_MASK) + SC_LOCKEN_VALID_HIGH_BIT; +} + +/** + * @brief Set the write protection for SYSCTRL registers enable. + * @param None. + * @retval None. + */ +static inline void DCL_SYSCTRL_ScWriteProtectionEnable(void) +{ + /* Set the corresponding bit without affecting the other bits and set the high 16 bits to EA51 to write to */ + SYSCTRL0->SC_LOCKEN.reg = ((SYSCTRL0->SC_LOCKEN.reg & SC_LOW_BIT_MASK) | SC_LOCKEN_SC_ENABLE_MASK) + + SC_LOCKEN_VALID_HIGH_BIT; +} + +/** + * @brief Set the write protection for CRG-related registers disable. + * @param None. + * @retval None. + */ +static inline void DCL_SYSCTRL_CrgWriteProtectionDisable(void) +{ + /* Set the corresponding bit without affecting the other bits and set the high 16 bits to EA51 to write to */ + SYSCTRL0->SC_LOCKEN.reg = (SYSCTRL0->SC_LOCKEN.reg & SC_LOCKEN_CRG_DISABLE_MASK) + SC_LOCKEN_VALID_HIGH_BIT; +} + +/** + * @brief Set the Set the write protection for CRG-related registers enable. + * @param None. + * @retval None. + */ +static inline void DCL_SYSCTRL_CrgWriteProtectionEnable(void) +{ + /* Set the corresponding bit without affecting the other bits and set the high 16 bits to EA51 to write to */ + SYSCTRL0->SC_LOCKEN.reg = ((SYSCTRL0->SC_LOCKEN.reg & SC_LOW_BIT_MASK) | SC_LOCKEN_CRG_ENABLE_MASK) + + SC_LOCKEN_VALID_HIGH_BIT; +} + +/** + * @brief Set software interrupt register, writing 1 generates a software interrupt. + * @param None. + * @retval None. + */ +static inline void DCL_SYSCTRL_GenerateSoftInterrupt(void) +{ + SYSCTRL0->SC_SOFT_INT.BIT.software_int = 1; +} +/** + * @brief Clear software interrupt register, writing 0 clear software interrupt. + * @param None. + * @retval None. + */ +static inline void DCL_SYSCTRL_ClearSoftInterrupt(void) +{ + SYSCTRL0->SC_SOFT_INT.BIT.software_int = 0; +} + +/** + * @brief Set Software interrupt event ID. + * @param id the software interrupt event ID. + * @retval None. + */ +static inline void DCL_SYSCTRL_SetSoftInterruptEventId(unsigned int id) +{ + SYSCTRL0->SC_SOFT_EVT_ID.BIT.swint_evt_id = id; +} + +/** + * @brief Get Software interrupt event ID. + * @param None. + * @retval The value of software interrupt event ID. + */ +static inline unsigned int DCL_SYSCTRL_GetSoftInterruptEventId(void) +{ + return SYSCTRL0->SC_SOFT_EVT_ID.BIT.swint_evt_id; +} + +/** + * @brief Get SYSRAM Parity Error Status. + * @param None. + * @retval 0:no error, 1:error. + */ +static inline unsigned int DCL_SYSCTRL_GetSysramParityErrorStatus(void) +{ + return SYSCTRL1->SYSRAM_ERR.BIT.sysram_parity_err; +} + +/** + * @brief Set SYSRAM parity error status clear. + * @param None. + * @retval None. + */ +static inline void DCL_SYSCTRL_ClearSysramParityError(void) +{ + SYSCTRL1->SYSRAM_ERR.BIT.sysram_parity_err_clr = 1; /* Write any value to clear. */ +} + +/** + * @brief Get CPU status. + * @param offset Bit offset of CPU status. + * @retval true or false + */ +static inline bool DCL_SYSCTRL_CheckCpuStatus(SYSCTRL_CPU_Status offset) +{ + return ((SYSCTRL1->CPU_STATUS.reg) & (1 << offset)) == 0 ? false : true; +} + +/** + * @brief Set the tsensor function enable. + * @param None. + * @retval None + */ +static inline void DCL_SYSCTRL_EnableTsensor(void) +{ + SYSCTRL1->TSENSOR_EN.BIT.tsensor_en = BASE_CFG_ENABLE; +} + +/** + * @brief Set the tsensor function disable. + * @param None. + * @retval None + */ +static inline void DCL_SYSCTRL_DisableTsensor(void) +{ + SYSCTRL1->TSENSOR_EN.BIT.tsensor_en = BASE_CFG_DISABLE; +} + +#endif /* McuMagicTag_SYSCTRL_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/systick.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/systick.h new file mode 100644 index 00000000..1a72e8d4 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/3065h/systick.h @@ -0,0 +1,66 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file systick.h + * @author MCU Driver Team + * @brief SYSTICK module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the SYSTICK. + * + SYSTICK register mapping structure + * + Get SysTick counter + */ + + +#ifndef McuMagicTag_SYSTICK_H +#define McuMagicTag_SYSTICK_H + +/* Includes ------------------------------------------------------------------*/ + +/** + * @addtogroup SYSTICK + * @{ + */ + +/** + * @defgroup SYSTICK_IP SYSTICK_IP + * @brief SYSTICK_IP: systick + * @{ + */ + +/** + * @defgroup SYSTICK_Param_Def SYSTICK Parameters Definition + * @brief Definition of SYSTICK configuration parameters. + * @{ + */ + +#ifdef NOS_TASK_SUPPORT +#ifndef CFG_SYSTICK_TICKINTERVAL_US +#define CFG_SYSTICK_TICKINTERVAL_US 100 +#endif +unsigned int SYSTICK_GetTickInterval(void); +#endif + +#define SYSTICK_MAX_VALUE 0xFFFFFFFFUL + +unsigned int SYSTICK_GetCRGHZ(void); +unsigned int DCL_SYSTICK_GetTick(void); +unsigned int SYSTICK_GetTimeStampUs(void); + +/** + * @} + */ +#endif /* McuMagicTag_SYSTICK_H */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/target/userconfig.json b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/target/userconfig.json new file mode 100644 index 00000000..855b1d10 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/chip/target/userconfig.json @@ -0,0 +1,132 @@ +{ + "system": [ + { + "name": "compile", + "subsystem": [ + { + "name": "static_lib", + "component": [ + { + "name": "", + "target_type": "static", + "sources": [], + "includes": [], + "define": [], + "libs": [], + "lds_scripts": [], + "cflags": [], + "asmflags": [], + "ldflags": [] + } + ] + }, + { + "name": "compile_frame", + "cflags": [ + "-O0", + "-pipe", + "-Wall", + "-Wextra", + "-Winit-self", + "-Wmissing-include-dirs", + "-Wtrampolines", + "-Werror=undef", + "-Wpointer-arith", + "-Wlogical-op", + "-Wstrict-prototypes", + "-Wmissing-prototypes", + "-Wjump-misses-init", + "-Wformat=2", + "-Wfloat-equal", + "-Wdate-time", + "-Wswitch-default", + "-Wimplicit-fallthrough=2", + "-Wno-missing-declarations", + "-std=gnu11", + "-fsigned-char", + "-fno-builtin", + "-ffreestanding", + "-nostdlib", + "-fno-exceptions", + "-fno-unwind-tables", + "-fno-short-enums", + "-fno-common", + "-freg-struct-return", + "-mabi=ilp32f", + "-march=rv32imfc", + "-fno-strict-aliasing", + "-fdata-sections", + "-ffunction-sections", + "-falign-functions=2", + "-fno-schedule-insns", + "-fno-optimize-strlen", + "-fno-aggressive-loop-optimizations", + "-Wa,-enable-c-lbu-sb", + "-Wa,-enable-c-lhu-sh", + "-msmall-data-limit=0", + "-fimm-compare", + "-femit-muliadd", + "-fmerge-immshf", + "-femit-uxtb-uxth", + "-femit-lli", + "-fldm-stm-optimize", + "-fno-inline-small-functions", + "-mtune=size", + "-mpush-pop", + "-femit-clz", + "-madjust-regorder", + "-madjust-const-cost", + "-freorder-commu-args", + "-fimm-compare-expand", + "-frmv-str-zero", + "-mfp-const-opt", + "-mswitch-jump-table", + "-frtl-sequence-abstract", + "-frtl-hoist-sink", + "-fsafe-alias-multipointer", + "-finline-optimize-size", + "-fmuliadd-expand", + "-mlli-expand", + "-Wa,-mcjal-expand", + "-foptimize-reg-alloc", + "-fsplit-multi-zero-assignments", + "-floop-optimize-size", + "-mpattern-abstract", + "-foptimize-pro-and-epilogue", + "-fstrict-volatile-bitfields", + "-Wcast-align", + "-fstrong-eval-order", + "-Wunused", + "-Wvla", + "-Wshadow", + "-fvisibility=hidden", + "-fsingle-precision-constant" + ], + "asmflags": [], + "ldflags": [ + "-Wl,-Map,bin/target.map", + "-Wl,--enjal16", + "-Wl,--gc-section", + "-Wl,--cjal-relax", + "-Wl,--dslf", + "-Wl,--jal-transfer", + "-nostdlib", + "-static", + "-lgcc", + "-lc", + "-Wl,-Bsymbolic", + "-rdynamic", + "-Wl,--no-undefined" + ], + "define": [ + "FLOAT_SUPPORT" + ], + "nocheck": [], + "extlibspath": [], + "extlibsname": [], + "extlibsinclude": [] + } + ] + } + ] +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/EG25/EC200.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/EG25/EC200.c new file mode 100644 index 00000000..cb94787e --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/EG25/EC200.c @@ -0,0 +1,232 @@ +#include "EC200.h" +#include "usart.h" +#include "stdlib.h" +#include "string.h" +#include "wdg.h" +#include "delay.h" +char *strx=0,*extstrx,*Readystrx,*Errstrx; //ֵָж + +extern u8 RxBuffer[200],RxCounter; +//GPSģľγֵ +struct +{ +char Latitude[10];//ԭ +char longitude[9];//γԴ +char Latitudess[3];// +char longitudess[2]; +char Latitudedd[7];//С㲿 +char longitudedd[7]; +float TrueLatitude;//ת +float Truelongitude;//ת +char buffer[200];//洢תľγ +char data_len[10]; +}LongLatidata; +void Uart1_SendStr(char*SendBuf)//2ӡ +{ + while(*SendBuf) + { + while((USART1->SR&0X40)==0) + {}//ȴ + USART1->DR = (u8) *SendBuf; + SendBuf++; + } +} +void Clear_Buffer(void)//ջ +{ + u8 i; + Uart1_SendStr(RxBuffer); + for(i=0;i= ACMP_SW_VIN0); + ACMP_PARAM_CHECK_NO_RET(inputP <= ACMP_SW_VIN3); + ACMP_PARAM_CHECK_NO_RET(inputN >= ACMP_SW_VIN0); + ACMP_PARAM_CHECK_NO_RET(inputN <= ACMP_SW_VIN3); + acmpx->CMP_SW.BIT.cmp_sw_enlv_p = inputP; /* switch P input */ + acmpx->CMP_SW.BIT.cmp_sw_enlv_n = inputN; /* switch N input */ +} + +/** + * @brief Set comparator blking active level + * @param acmpx: ACMP register base address. + * @param actLevel: Active level. @ref ACMP_BlkingActLevel + * @retval None. + */ +static inline void DCL_ACMP_SetCmpBlkingActiveLevel(ACMP_RegStruct *acmpx, ACMP_BlkingActLevel actLevel) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + ACMP_PARAM_CHECK_NO_RET(actLevel >= ACMP_BLKING_LOW_ACTIVE); + ACMP_PARAM_CHECK_NO_RET(actLevel <= ACMP_BLKING_HIGH_ACTIVE); + acmpx->CMP_CTRL.BIT.cmp_blking_inv_sel = actLevel; +} + +/** + * @brief ACMP output(deshark and synchronize) source. + * @param acmp: ACMP register base address. + * @param value: config value. @ref ACMP_OutputSrcSel + * @retval None. + */ +static inline void DCL_ACMP_SetCmpOutputSrc(ACMP_RegStruct *acmpx, ACMP_OutputSrcSel value) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + ACMP_PARAM_CHECK_NO_RET(value >= ACMP_ORIGINAL_TO_PORT); + ACMP_PARAM_CHECK_NO_RET(value <= ACMP_SYNC_TO_PORT); + acmpx->CMP_CTRL.BIT.cmp_qual_en = value & 0x01; /* result select bit0 */ + acmpx->CMP_CTRL.BIT.cmp_sync_sel = (value >> 1) & 0x01; /* result select bit1 */ +} + +/** + * @brief Comparator enable blking function + * @param acmpx: ACMP register base address. + * @retval None. + */ +static inline void DCL_ACMP_EnableCmpBlking(ACMP_RegStruct *acmpx) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + acmpx->CMP_CTRL.BIT.cmp_blking_en = BASE_CFG_ENABLE; +} + +/** + * @brief Comparator disable blking function + * @param acmpx: ACMP register base address. + * @retval None. + */ +static inline void DCL_ACMP_DisableCmpBlking(ACMP_RegStruct *acmpx) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + acmpx->CMP_CTRL.BIT.cmp_blking_en = BASE_CFG_DISABLE; +} + +/** + * @brief Set blking from which apt number + * @param acmpx: ACMP register base address. + * @param aptNum: APT number. + * @retval None. + */ +static inline void DCL_ACMP_SetCmpBlkingAptSelect(ACMP_RegStruct *acmpx, unsigned char aptNum) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + ACMP_PARAM_CHECK_NO_RET(aptNum <= ACMP_MAX_APT_NUM); + acmpx->CMP_CTRL.BIT.cmp_apt_sel = aptNum; +} + +/** + * @brief Set blking source. + * @param acmpx: ACMP register base address. + * @param source: Source of blking. @ref ACMP_BlkingSrcType + * @retval None. + */ +static inline void DCL_ACMP_SetCmpBlkingSource(ACMP_RegStruct *acmpx, ACMP_BlkingSrcType source) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + ACMP_PARAM_CHECK_NO_RET(source >= ACMP_BLKING_SRC_APT); + ACMP_PARAM_CHECK_NO_RET(source <= ACMP_BLKING_SRC_SOFT); + acmpx->CMP_CTRL.BIT.cmp_blking_sel = source; +} + +/** + * @brief Set software blking valid. + * @param acmpx: ACMP register base address. + * @retval None. + */ +static inline void DCL_ACMP_CmpBlkingSoftValid(ACMP_RegStruct *acmpx) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + acmpx->CMP_CTRL.BIT.cmp_blking_cfg = BASE_CFG_DISABLE; /* 0, valid; 1, invalid */ +} + +/** + * @brief Set software blking invalid. + * @param acmpx: ACMP register base address. + * @retval None. + */ +static inline void DCL_ACMP_CmpBlkingSoftInValid(ACMP_RegStruct *acmpx) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + acmpx->CMP_CTRL.BIT.cmp_blking_cfg = BASE_CFG_ENABLE; /* 0, valid; 1, invalid */ +} + +/** + * @brief Enable comparator's digital part. + * @param acmpx: ACMP register base address. + * @retval None. + */ +static inline void DCL_ACMP_EnableCmpDigital(ACMP_RegStruct *acmpx) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + acmpx->CMP_CTRL.BIT.cmp_dig_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable comparator's digital part. + * @param acmpx: ACMP register base address. + * @retval None. + */ +static inline void DCL_ACMP_DisableCmpDigital(ACMP_RegStruct *acmpx) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + acmpx->CMP_CTRL.BIT.cmp_dig_en = BASE_CFG_DISABLE; +} + +/** + * @brief Set comparator hysteresis voltage. + * @param acmpx: ACMP register base address. + * @param volSelect: Hysteresis voltage selection. @ref ACMP_HystVol + * @retval None. + */ +static inline void DCL_ACMP_SetCmpHysteresisVoltage(ACMP_RegStruct *acmpx, ACMP_HystVol volSelect) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + ACMP_PARAM_CHECK_NO_RET(volSelect >= ACMP_HYS_VOL_ZERO); + ACMP_PARAM_CHECK_NO_RET(volSelect <= ACMP_HYS_VOL_30MV); + acmpx->CMP_CTRL.BIT.cmp_hy_vol_sel = volSelect; +} + +/** + * @brief Set comparator's output polarity + * @param acmpx: ACMP register base address. + * @param polarity: output polarity. @ref ACMP_OutputPolarity + * @retval None. + */ +static inline void DCL_ACMP_SetCmpOutputPolarity(ACMP_RegStruct *acmpx, ACMP_OutputPolarity polarity) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + ACMP_PARAM_CHECK_NO_RET(polarity >= ACMP_OUT_NOT_INVERT); + ACMP_PARAM_CHECK_NO_RET(polarity <= ACMP_OUT_INVERT); + acmpx->CMP_CTRL.BIT.cmp_rslt_inv = polarity; +} + +/** + * @brief enable comparator's analog part. + * @param acmpx: ACMP register base address. + * @retval None. + */ +static inline void DCL_ACMP_EnableCmpAnalog(ACMP_RegStruct *acmpx) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + acmpx->CMP_CTRL.BIT.cmp_ana_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable comparator's analog part. + * @param acmpx: ACMP register base address. + * @retval None. + */ +static inline void DCL_ACMP_DisableCmpAnalog(ACMP_RegStruct *acmpx) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + acmpx->CMP_CTRL.BIT.cmp_ana_en = BASE_CFG_DISABLE; +} + +/** + * @brief Set comparator input muxtex P + * @param acmpx: ACMP register base address. + * @param muxValue: input P select value. @ref ACMP_VinMux + * @retval None. + */ +static inline void DCL_ACMP_SetMuxP(ACMP_RegStruct *acmpx, ACMP_VinMux muxValue) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + ACMP_PARAM_CHECK_NO_RET(muxValue >= ACMP_VIN_MUX0); + ACMP_PARAM_CHECK_NO_RET(muxValue <= ACMP_VIN_MUX3); + acmpx->CMP_CTRL1.BIT.cmp_mux_p = muxValue; +} + +/** + * @brief Set comparator input muxtex N + * @param acmpx: ACMP register base address. + * @param muxValue: input N value. @ref ACMP_VinMux + * @retval None. + */ +static inline void DCL_ACMP_SetMuxN(ACMP_RegStruct *acmpx, ACMP_VinMux muxValue) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + ACMP_PARAM_CHECK_NO_RET(muxValue >= ACMP_VIN_MUX0); + ACMP_PARAM_CHECK_NO_RET(muxValue <= ACMP_VIN_MUX3); + acmpx->CMP_CTRL1.BIT.cmp_mux_n = muxValue; +} + +/** + * @brief Reading compare result after blking. + * @param acmpx: ACMP register base address. + * @retval Blking result. + */ +static inline unsigned int DCL_ACMP_GetCmpOutValueAfterBlking(ACMP_RegStruct *acmpx) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + return acmpx->CMP_CTRL2.BIT.cmp_blking_rslt; +} + +/** + * @brief Reading compare result after deshark. + * @param acmpx: ACMP register base address. + * @retval deshark result. + */ +static inline unsigned int DCL_ACMP_GetCmpOutValueAfterDeshark(ACMP_RegStruct *acmpx) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + return acmpx->CMP_CTRL2.BIT.cmp_qual_rslt; +} + +/** + * @brief Reading original compare result + * @param acmpx: ACMP register base address. + * @retval original result. + */ +static inline unsigned int DCL_ACMP_GetCmpOutValueOriginal(ACMP_RegStruct *acmpx) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + return acmpx->CMP_CTRL2.BIT.cmp_ana_rslt; +} + +/** + * @brief Set deshark step by clock. + * @param acmpx: ACMP register base address. + * @param clkTimes: Times of clock. + * @retval None. + */ +static inline void DCL_ACMP_SetDesharkStepByClock(ACMP_RegStruct *acmpx, unsigned short clkTimes) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + ACMP_PARAM_CHECK_NO_RET(clkTimes <= ACMP_DESHARK_BY_CLK_MAX); + acmpx->CMP_QUALI2.BIT.cmp_qual_step = clkTimes; +} + +/** + * @brief Set deshark step by compare times + * @param acmpx: ACMP register base address. + * @param cmpTimes: Times of compare. + * @retval None. + */ +static inline void DCL_ACMP_SetDesharkStepByCmpTimes(ACMP_RegStruct *acmpx, unsigned short cmpTimes) +{ + ACMP_ASSERT_PARAM(IsACMPInstance(acmpx)); + ACMP_PARAM_CHECK_NO_RET(cmpTimes <= ACMP_DESHARK_BY_CMP_MAX); + acmpx->CMP_QUALI2.BIT.cmp_qual_sel = cmpTimes; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/acmp/src/acmp.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/acmp/src/acmp.c new file mode 100644 index 00000000..736e5f36 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/acmp/src/acmp.c @@ -0,0 +1,265 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file acmp.c + * @author MCU Driver Team. + * @brief ACMP HAL level module driver. + * This file provides firmware functions to manage the following + * functionalities of ACMP. + * + Comparator's Initialization and de-initialization functions + * + Set Comparator's hysteresis voltage function + * + Set blocking function. + */ +#include "acmp.h" +#include "assert.h" + +/** + * @brief Input and output initialization of comparator + * @param acmpHandle: ACMP handle. + * @retval None. + */ +static void ACMP_InputOutputInit(ACMP_Handle *acmpHandle) +{ + ACMP_ASSERT_PARAM(acmpHandle != NULL); + ACMP_ASSERT_PARAM(IsACMPInstance(acmpHandle->baseAddress)); + ACMP_PARAM_CHECK_NO_RET(IsACMPOutputPolarity(acmpHandle->inOutConfig.polarity)); + /* Check input multiplexing selection and input switch selection */ + ACMP_PARAM_CHECK_NO_RET(IsACMPSwitchVinNumber(acmpHandle->inOutConfig.swVinNNum)); + ACMP_PARAM_CHECK_NO_RET(IsACMPSwitchVinNumber(acmpHandle->inOutConfig.swVinPNum)); + ACMP_PARAM_CHECK_NO_RET(IsACMPVinNumber(acmpHandle->inOutConfig.vinNNum)); + ACMP_PARAM_CHECK_NO_RET(IsACMPVinNumber(acmpHandle->inOutConfig.vinPNum)); + /* input mux selection */ + acmpHandle->baseAddress->CMP_CTRL1.BIT.cmp_mux_p = acmpHandle->inOutConfig.vinPNum; + acmpHandle->baseAddress->CMP_CTRL1.BIT.cmp_mux_n = acmpHandle->inOutConfig.vinNNum; + /* input switch selection */ + acmpHandle->baseAddress->CMP_SW.BIT.cmp_sw_enlv_p = acmpHandle->inOutConfig.swVinPNum; + acmpHandle->baseAddress->CMP_SW.BIT.cmp_sw_enlv_n = acmpHandle->inOutConfig.swVinNNum; + /* output polarity selection */ + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_rslt_inv = acmpHandle->inOutConfig.polarity; +} + +/** + * @brief Filter initialization of comparator + * @param acmpHandle: ACMP handle. + * @retval None. + */ +static void ACMP_FilterInit(ACMP_Handle *acmpHandle) +{ + ACMP_ASSERT_PARAM(acmpHandle != NULL); + ACMP_ASSERT_PARAM(IsACMPInstance(acmpHandle->baseAddress)); + /* Check input parameters: Blking source, Deshark, Blking, Blking source */ + ACMP_PARAM_CHECK_NO_RET(IsACMPBlkingSrcType(acmpHandle->filterCtrl.blkingSrcSelect)); + ACMP_PARAM_CHECK_NO_RET(IsACMPAptMaskWindow(acmpHandle->filterCtrl.blkingFromAptNum)); + unsigned short blkingSrc; + switch (acmpHandle->filterCtrl.filterMode) { + case ACMP_FILTER_NONE: /* Use the analog comparison mode. */ + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_blking_en = BASE_CFG_DISABLE; /* Disable Blking */ + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_qual_en = BASE_CFG_DISABLE; /* Disable Deshark */ + break; + case ACMP_FILTER_BLKING: /* Use masking to compare results. */ + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_blking_en = BASE_CFG_ENABLE; /* Enable Blking */ + + blkingSrc = acmpHandle->filterCtrl.blkingSrcSelect; + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_blking_sel = blkingSrc; /* Setting Blking source */ + if (blkingSrc == ACMP_BLKING_SRC_APT) { + /* Setting Blking source apt number */ + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_apt_sel = acmpHandle->filterCtrl.blkingFromAptNum; + } else { + /* Blocking source from software. Blanking polarity. */ + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_blking_inv_sel = acmpHandle->filterCtrl.blkingPorty; + } + break; + case ACMP_FILTER_DESHARK: /* Use the filter deshark function. */ + /* Enable Deshark */ + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_qual_en = BASE_CFG_ENABLE; + /* Setting deshark by step */ + acmpHandle->baseAddress->CMP_QUALI2.BIT.cmp_qual_step = acmpHandle->filterCtrl.desharkByStep; + /* Setting deshark by times */ + acmpHandle->baseAddress->CMP_QUALI2.BIT.cmp_qual_sel = acmpHandle->filterCtrl.desharkByTimes; + break; + case ACMP_FILTER_BOTH: /* The masking and debounce functions are enabled at the same time. */ + /* Deshark setting */ + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_qual_en = BASE_CFG_ENABLE; + /* Setting deshark by step */ + acmpHandle->baseAddress->CMP_QUALI2.BIT.cmp_qual_step = acmpHandle->filterCtrl.desharkByStep; + /* Setting deshark by times */ + acmpHandle->baseAddress->CMP_QUALI2.BIT.cmp_qual_sel = acmpHandle->filterCtrl.desharkByTimes; + + /* Blocking setting */ + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_blking_en = BASE_CFG_ENABLE; /* Enable Blking */ + blkingSrc = acmpHandle->filterCtrl.blkingSrcSelect; + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_blking_sel = blkingSrc; /* Setting Blking source */ + if (blkingSrc == ACMP_BLKING_SRC_APT) { + /* Setting Blking source apt window */ + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_apt_sel = acmpHandle->filterCtrl.blkingFromAptNum; + } else { + /* Effective blanking signal configured by the software. */ + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_blking_inv_sel = acmpHandle->filterCtrl.blkingPorty; + } + break; + default: + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_blking_en = BASE_CFG_DISABLE; /* Disable Blking */ + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_qual_en = BASE_CFG_DISABLE; /* Disable Deshark */ + break; + } +} + +/** + * @brief Comparator HAL Init + * @param acmpHandle: ACMP handle. + * @retval BASE_StatusType: OK, ERROR + */ +BASE_StatusType HAL_ACMP_Init(ACMP_Handle *acmpHandle) +{ + ACMP_ASSERT_PARAM(acmpHandle != NULL); + ACMP_ASSERT_PARAM(IsACMPInstance(acmpHandle->baseAddress)); + ACMP_PARAM_CHECK_WITH_RET(acmpHandle->hysteresisVol >= ACMP_HYS_VOL_ZERO, BASE_STATUS_ERROR); + ACMP_PARAM_CHECK_WITH_RET(acmpHandle->hysteresisVol <= ACMP_HYS_VOL_30MV, BASE_STATUS_ERROR); + /* Check deshark parameters. */ + ACMP_PARAM_CHECK_WITH_RET(acmpHandle->filterCtrl.desharkByStep >= 0, BASE_STATUS_ERROR); + ACMP_PARAM_CHECK_WITH_RET(acmpHandle->filterCtrl.desharkByStep <= ACMP_DESHARK_BY_CLK_MAX, BASE_STATUS_ERROR); + ACMP_PARAM_CHECK_WITH_RET(acmpHandle->filterCtrl.desharkByTimes >= 0, BASE_STATUS_ERROR); + ACMP_PARAM_CHECK_WITH_RET(acmpHandle->filterCtrl.desharkByTimes <= ACMP_DESHARK_BY_CMP_MAX, BASE_STATUS_ERROR); + + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_ana_en = BASE_CFG_ENABLE; /* ACMP Enable. */ + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_dig_en = BASE_CFG_ENABLE; /* ACMP digital part enable. */ + + /* ACMP input and output settings. */ + ACMP_InputOutputInit(acmpHandle); + /* Set the ACMP digital filter. */ + ACMP_FilterInit(acmpHandle); + /* set hysteresis voltage */ + HAL_ACMP_SetHystVol(acmpHandle, acmpHandle->hysteresisVol); + + return BASE_STATUS_OK; +} + +/** + * @brief Comparator HAL DeInit + * @param acmpHandle: ACMP handle. + * @retval BASE_StatusType: OK, ERROR. + */ +BASE_StatusType HAL_ACMP_DeInit(ACMP_Handle *acmpHandle) +{ + ACMP_ASSERT_PARAM(acmpHandle != NULL); + ACMP_ASSERT_PARAM(IsACMPInstance(acmpHandle->baseAddress)); + acmpHandle->baseAddress->CMP_CTRL.reg = BASE_CFG_DISABLE; /* Disable ACMP. */ + acmpHandle->baseAddress->CMP_CTRL1.reg = BASE_CFG_DISABLE; /* Deinitializes the comparison input setting. */ + acmpHandle->baseAddress->CMP_SW.reg = BASE_CFG_DISABLE; /* Deinitializes the SW control. */ + return BASE_STATUS_OK; +} + +/** + * @brief Set hysteresis Voltage + * @param acmpHandle: ACMP handle. + * @param voltage: hysteresis voltage to be set, @ref ACMP_HystVol + * @retval None. + */ +void HAL_ACMP_SetHystVol(ACMP_Handle *acmpHandle, ACMP_HystVol voltage) +{ + ACMP_ASSERT_PARAM(acmpHandle != NULL); + ACMP_ASSERT_PARAM(IsACMPInstance(acmpHandle->baseAddress)); + ACMP_PARAM_CHECK_NO_RET(voltage >= ACMP_HYS_VOL_ZERO); + ACMP_PARAM_CHECK_NO_RET(voltage <= ACMP_HYS_VOL_30MV); + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_hy_vol_sel = voltage; /* Hysteresis voltage setting. */ +} + +/** + * @brief Set Blking Valid + * @param acmpHandle: ACMP handle. + * @retval None. + */ +void HAL_ACMP_BlkingValid(ACMP_Handle *acmpHandle) +{ + ACMP_ASSERT_PARAM(acmpHandle != NULL); + ACMP_ASSERT_PARAM(IsACMPInstance(acmpHandle->baseAddress)); + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_blking_en = BASE_CFG_ENABLE; +} + +/** + * @brief Set Blking Invalid + * @param acmpHandle: ACMP handle. + * @retval None. + */ +void HAL_ACMP_BlkingInvalid(ACMP_Handle *acmpHandle) +{ + ACMP_ASSERT_PARAM(acmpHandle != NULL); + ACMP_ASSERT_PARAM(IsACMPInstance(acmpHandle->baseAddress)); + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_blking_en = BASE_CFG_DISABLE; +} + +/** + * @brief Sets the output of ACMP. + * @param acmpHandle: ACMP handle. + * @param resultSelect: ACMP result output options, @ref ACMP_ResultSelect. + * @retval None. + */ +BASE_StatusType HAL_ACMP_ResultSelect(ACMP_Handle *acmpHandle, ACMP_ResultSelect resultSelect) +{ + ACMP_ASSERT_PARAM(acmpHandle != NULL); + ACMP_ASSERT_PARAM(IsACMPInstance(acmpHandle->baseAddress)); + ACMP_PARAM_CHECK_WITH_RET(IsACMPResultSeletion(resultSelect), BASE_STATUS_ERROR); + /* Output result selection of the comparator. */ + switch (resultSelect) { + case ACMP_RESULT_SIMULATION: /* Simulate the original comparison results. */ + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_sync_sel = BASE_CFG_DISABLE; + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_qual_en = BASE_CFG_DISABLE; + break; + case ACMP_RESULT_DESHAKE: /* Compare the results after deshake. */ + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_sync_sel = BASE_CFG_DISABLE; + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_qual_en = BASE_CFG_ENABLE; + break; + case ACMP_RESULT_DELAY: /* The original result is delayed by 1 cycle. */ + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_sync_sel = BASE_CFG_ENABLE; + acmpHandle->baseAddress->CMP_CTRL.BIT.cmp_qual_en = BASE_CFG_DISABLE; + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief ACMP Interrupt service processing function. + * @param handle ACMP handle. + * @note No interruption occurs on the 3065 interface, and no action is required. + * @retval None. + */ +void HAL_ACMP_IrqHandler(void *handle) +{ + BASE_FUNC_UNUSED(handle); + return; +} + +/** + * @brief Register the callback function of ACMP handle. + * @param handle Acmp Handle + * @param typeID CallBack function type of user, @ref ACMP_CallBackFun_Type + * @param callBackFunc CallBack function of user, @ref ACMP_CallBackType + * @note Hi3065H has no interrupt and does not need to register the user callback function. + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Parameter check fail + */ +BASE_StatusType HAL_ACMP_RegisterCallBack(ACMP_Handle *acmpHandle, ACMP_CallBackFun_Type typeID, + ACMP_CallBackType callBackFunc) +{ + /* Hi3065H has no interrupt and does not need to process the interrupt callback function. */ + BASE_FUNC_UNUSED(acmpHandle); + BASE_FUNC_UNUSED(typeID); + BASE_FUNC_UNUSED(callBackFunc); + return BASE_STATUS_OK; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/adc/common/inc/adc.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/adc/common/inc/adc.h new file mode 100644 index 00000000..c32b8cae --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/adc/common/inc/adc.h @@ -0,0 +1,128 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file adc.h + * @author MCU Driver Team + * @brief ADC module driver + * @details This file provides functions declaration of the ADC, + * + ADC initialization function. + * + Start ADC sample and conversion. + * + Start ADC sample and conversion with interrupt. + * + Start ADC sample and conversion with DMA. + * + Start ADC sample and conversion synchronously. + * + Query the ADC conversion result. + * + Single channel and multichannel software trigger functions. + * + Interrupt callback function and user registration function. + * This file also provides the definition of the ADC handle structure. + */ + +/* Macro definitions */ +#ifndef McuMagicTag_ADC_H +#define McuMagicTag_ADC_H + +#include "adc_ip.h" +#include "dma.h" +#include "dac.h" +#include "interrupt.h" + +/** + * @defgroup ADC ADC + * @brief ADC module. + * @{ + */ + +/** + * @defgroup ADC_Common ADC Common + * @brief ADC common external module. + * @{ + */ + +/** + * @defgroup ADC_Handle_Definition ADC Handle Definition + * @{ + */ + +/** + * @brief The definition of the ADC handle structure. + */ +typedef struct _ADC_Handle { + ADC_RegStruct *baseAddress; /**< ADC registers base address */ + ADC_PriorityMode socPriority; /**< ADC clock divider */ + DMA_Handle *dmaHandle; /**< ADC_DMA control */ + unsigned int adcDmaChn; /**< ADC_DMA channel */ + ADC_OverState overState; /**< ADC overflow state */ + struct { + unsigned short finishMode; /**< sample finish mode, defined in ADC_SOCFinishMode */ + } ADC_SOCxParam[SOC_MAX_NUM]; + struct { + unsigned short socxFinish; /**< After each SOC is completed, the corresponding bit is set as 1 */ + } ADC_IntxParam[INT_MAX_NUM]; + ADC_UserCallBack userCallBack; /**< ADC User Callback Function */ + ADC_ExtendHandle handleEx; /**< ADC extend handle */ +} ADC_Handle; + +/** + * @brief The definition of the ADC callback function. + */ +typedef void (* ADC_CallbackType)(void *handle); + +/** + * @} + */ + +/** + * @defgroup ADC_API_Declaration ADC HAL API + * @{ + */ +BASE_StatusType HAL_ADC_Init(ADC_Handle *adcHandle); +BASE_StatusType HAL_ADC_Deinit(ADC_Handle *adcHandle); +BASE_StatusType HAL_ADC_ConfigureSoc(ADC_Handle *adcHandle, ADC_SOCNumber soc, SOC_Param *socParam); +BASE_StatusType HAL_ADC_StartDma(ADC_Handle *adcHandle, unsigned int startSoc, + unsigned int endSoc, unsigned int *saveData); +BASE_StatusType HAL_ADC_StartIt(ADC_Handle *adcHandle); +BASE_StatusType HAL_ADC_SoftTrigMultiSample(ADC_Handle *adcHandle, ADC_SoftMultiTrig syncTrig); +BASE_StatusType HAL_ADC_SoftTrigSample(ADC_Handle *adcHandle, unsigned int soc); +unsigned int HAL_ADC_GetConvResult(ADC_Handle *adcHandle, unsigned int soc); +BASE_StatusType HAL_ADC_CheckSocFinish(ADC_Handle *adcHandle, unsigned int soc); +void HAL_ADC_RegisterCallBack(ADC_Handle *adcHandle, ADC_CallbackFunType typeID, ADC_CallbackType pCallback); +BASE_StatusType HAL_ADC_InitForVdda(ADC_RegStruct *adcx, ADC_SOCNumber soc, DAC_RegStruct *dacx, bool useDac); +float HAL_ADC_GetVddaByDac(ADC_RegStruct *adcx, ADC_SOCNumber soc, DAC_RegStruct *dacx, bool useDac); +unsigned int HAL_ADC_GetTransResultByVdda(ADC_RegStruct *adcx, ADC_SOCNumber soc, float vdda); +#if defined (CHIP_3061MNPICA) || defined (CHIP_3061MNPIKA) || defined (CHIP_3061MNPIC8) || defined (CHIP_3061MNPIK8) +void HAL_ADC_IrqHandlerInt0(void *handle); +#endif +void HAL_ADC_IrqHandlerInt1(void *handle); +void HAL_ADC_IrqHandlerInt2(void *handle); +void HAL_ADC_IrqHandlerInt3(void *handle); +#if defined (CHIP_3065HRPIRZ) || defined (CHIP_3065HRPICZ) || defined (CHIP_3061HRPIKZ) || \ + defined (AU302PDF51) || defined (AU302NDF51) || defined (AU301LDF51) || defined (CHIP_3065ARPIRZ) +void HAL_ADC_IrqHandlerInt4(void *handle); +#endif +void HAL_ADC_IrqHandlerOver(void *handle); +void HAL_ADC_IrqHandlerAllEvent(void *handle); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/adc/inc/adc_ex.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/adc/inc/adc_ex.h new file mode 100644 index 00000000..a96ccede --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/adc/inc/adc_ex.h @@ -0,0 +1,47 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file adc_ex.h + * @author MCU Driver Team + * @brief ADC module driver + * @details This file provides DCL functions to manage ADC and Definition of + * specific parameters. + * + ADC Synchronous Sampling. + * + ADC Software Calibration. + */ +#ifndef McuMagicTag_ADC_EX_H +#define McuMagicTag_ADC_EX_H +#include "adc.h" +/** + * @addtogroup ADC_IP + * @{ + */ + +/** + * @defgroup ADC_EX_API_Declaration ADC HAL API EX + * @{ + */ + BASE_StatusType HAL_ADC_StartSyncSampleEx(ADC_Handle *adcHandle, SOC_SyncParam *syncParam); + unsigned int HAL_ADC_ActiveCalibrateRetEx(ADC_RegStruct * const adcx, unsigned int soc, unsigned int originalRet); + /** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/adc/inc/adc_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/adc/inc/adc_ip.h new file mode 100644 index 00000000..c3354517 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/adc/inc/adc_ip.h @@ -0,0 +1,2495 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file adc_ip.h + * @author MCU Driver Team + * @brief ADC module driver + * @details This file provides DCL functions to manage ADC and Definition of + * specific parameters. + * + Definition of ADC configuration parameters. + * + ADC register mapping structure. + * + Parameters check functions. + * + Direct configuration layer interface. + */ + +/* Macro definitions */ +#ifndef McuMagicTag_ADC_IP_H +#define McuMagicTag_ADC_IP_H + +#include "baseinc.h" +#include "dma.h" + +extern bool g_trimEnable; +extern unsigned int g_versionId; +#define SOC_MAX_NUM 16 +#define INT_MAX_NUM 4 +#define HOLDTIME_MIN 2 +#define HOLDTIME_MAX 28 +#define ACQPSTIME_MIN 3 +#define ACQPSTIME_MAX 127 +#define SYNCGROUP_NUM 8 +#define DMA_OVER_MASK 0x00000010 +#define INT_OVER_MASK 0x0000000F +#define ADC_MIN_FREQ 2350000 +#define ADC_MAX_FREQ 40000000 +#ifdef ADC_PARAM_CHECK +#define ADC_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define ADC_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define ADC_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define ADC_ASSERT_PARAM(para) ((void)0U) +#define ADC_PARAM_CHECK_NO_RET(para) ((void)0U) +#define ADC_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +/** + * @addtogroup ADC + * @{ + */ + +/** + * @defgroup ADC_IP ADC_IP + * @brief ADC_IP: adc_v0. + * @{ + */ + +/** + * @defgroup ADC_REG_Definition ADC Register Structure. + * @brief ADC Register Structure Definition. + * @{ + */ + +/** + * @brief Define the union ADC_RESULT0_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result0 : 12; /**< SOC0 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT0_REG; + +/** + * @brief Define the union ADC_RESULT1_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result1 : 12; /**< SOC1 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT1_REG; + +/** + * @brief Define the union ADC_RESULT2_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result2 : 12; /**< SOC2 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT2_REG; + +/** + * @brief Define the union ADC_RESULT3_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result3 : 12; /**< SOC3 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT3_REG; + +/** + * @brief Define the union ADC_RESULT4_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result4 : 12; /**< SOC4 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT4_REG; + +/** + * @brief Define the union ADC_RESULT5_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result5 : 12; /**< SOC5 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT5_REG; + +/** + * @brief Define the union ADC_RESULT6_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result6 : 12; /**< SOC6 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT6_REG; + +/** + * @brief Define the union ADC_RESULT7_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result7 : 12; /**< SOC7 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT7_REG; + +/** + * @brief Define the union ADC_RESULT8_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result8 : 12; /**< SOC8 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT8_REG; + +/** + * @brief Define the union ADC_RESULT9_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result9 : 12; /**< SOC9 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT9_REG; + +/** + * @brief Define the union ADC_RESULT10_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result10 : 12; /**< SOC10 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT10_REG; + +/** + * @brief Define the union ADC_RESULT11_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result11 : 12; /**< SOC11 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT11_REG; + +/** + * @brief Define the union ADC_RESULT12_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result12 : 12; /**< SOC12 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT12_REG; + +/** + * @brief Define the union ADC_RESULT13_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result13 : 12; /**< SOC13 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT13_REG; + +/** + * @brief Define the union ADC_RESULT14_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result14 : 12; /**< SOC14 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT14_REG; + +/** + * @brief Define the union ADC_RESULT15_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_result15 : 12; /**< SOC15 Results */ + unsigned int reserved0 : 20; + } BIT; +} volatile ADC_RESULT15_REG; + +/** + * @brief Define the union ADC_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int one_shot : 1; /**< Block round robin mode enable */ + unsigned int reserved1 : 1; + unsigned int adc_cal_mode : 2; /**< Calibration mode selection */ + unsigned int adc_cal_en : 1; /**< ADC calibration enable */ + unsigned int reserved2 : 3; + unsigned int rstn_ana_num : 8; /**< Delay count value for analog reset */ + unsigned int reserved3 : 3; + unsigned int saen_ini_num : 8; /**< Duration when the simulated SAEN signal is high */ + unsigned int reserved4 : 4; + } BIT; +} volatile ADC_CTRL_REG; + +/** + * @brief Define the union ADC_STATUS_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_bsy_chn : 4; /**< ADC busy channel */ + unsigned int adc_bsy : 1; /**< Calibration mode selection */ + unsigned int reserved0 : 3; + unsigned int rr_pointer : 5; /**< Calibration mode selection */ + unsigned int reserved1 : 19; + } BIT; +} volatile ADC_STATUS_REG; + +/** + * @brief Define the union ADC_SOC_PRICTL_SET_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int rr_set : 1; /**< Polling pointer reset. Set to 1 to reset */ + unsigned int reserved0 : 31; + } BIT; +} volatile ADC_SOC_PRICTL_SET_REG; + +/** + * @brief Define the union ADC_SAMPLE_MODE_REG. If this bit is set to 0, two SOC perform independent sampling. + * 1: Two SOC perform synchronous sampling. + */ +typedef union { + unsigned int reg; + struct { + unsigned int simul_en0 : 1; /**< Sampling mode selection for SOC0 and SOC1 */ + unsigned int simul_en1 : 1; /**< Sampling mode selection for SOC2 and SOC3 */ + unsigned int simul_en2 : 1; /**< Sampling mode selection for SOC4 and SOC5 */ + unsigned int simul_en3 : 1; /**< Sampling mode selection for SOC6 and SOC7 */ + unsigned int simul_en4 : 1; /**< Sampling mode selection for SOC8 and SOC9 */ + unsigned int simul_en5 : 1; /**< Sampling mode selection for SOC10 and SOC11 */ + unsigned int simul_en6 : 1; /**< Sampling mode selection for SOC12 and SOC13 */ + unsigned int simul_en7 : 1; /**< Sampling mode selection for SOC14 and SOC15 */ + unsigned int reserved0 : 24; + } BIT; +} volatile ADC_SAMPLE_MODE_REG; + +/** + * @brief Define the union ADC_INT_FLAG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int int1_flag : 1; /**< Interrupt 1 status. Value 0: No interrupt. Value 1: Interrupt is generated */ + unsigned int int2_flag : 1; /**< Interrupt 2 status. Value 0: No interrupt. Value 1: Interrupt is generated */ + unsigned int int3_flag : 1; /**< Interrupt 3 status. Value 0: No interrupt. Value 1: Interrupt is generated */ + unsigned int int4_flag : 1; /**< Interrupt 4 status. Value 0: No interrupt. Value 1: Interrupt is generated */ + unsigned int reserved0 : 28; + } BIT; +} volatile ADC_INT_FLAG_REG; + +/** + * @brief Define the union ADC_EOC_FLAG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int eoc0_flag : 1; /**< Status of eoc0. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc1_flag : 1; /**< Status of eoc1. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc2_flag : 1; /**< Status of eoc2. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc3_flag : 1; /**< Status of eoc3. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc4_flag : 1; /**< Status of eoc4. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc5_flag : 1; /**< Status of eoc5. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc6_flag : 1; /**< Status of eoc6. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc7_flag : 1; /**< Status of eoc7. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc8_flag : 1; /**< Status of eoc8. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc9_flag : 1; /**< Status of eoc9. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc10_flag : 1; /**< Status of eoc10. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc11_flag : 1; /**< Status of eoc11. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc12_flag : 1; /**< Status of eoc12. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc13_flag : 1; /**< Status of eoc13. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc14_flag : 1; /**< Status of eoc14. 0: conversion is not complete. 1: conversion is complete */ + unsigned int eoc15_flag : 1; /**< Status of eoc15. 0: conversion is not complete. 1: conversion is complete */ + unsigned int reserved0 : 16; + } BIT; +} volatile ADC_EOC_FLAG_REG; + +/** + * @brief Define the union ADC_INT_OVFL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int int1_ovflg : 1; /**< Interrupt 1 overflow flag */ + unsigned int int2_ovflg : 1; /**< Interrupt 2 overflow flag */ + unsigned int int3_ovflg : 1; /**< Interrupt 3 overflow flag */ + unsigned int int4_ovflg : 1; /**< Interrupt 4 overflow flag */ + unsigned int dma_req_ovflg : 1; /**< DMA request overflow flag */ + unsigned int reserved0 : 27; + } BIT; +} volatile ADC_INT_OVFL_REG; + +/** + * @brief Define the union ADC_EOC_OVFL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int eoc0_ovflg : 1; /**< Overflow status of eoc0 */ + unsigned int eoc1_ovflg : 1; /**< Overflow status of eoc1 */ + unsigned int eoc2_ovflg : 1; /**< Overflow status of eoc2 */ + unsigned int eoc3_ovflg : 1; /**< Overflow status of eoc3 */ + unsigned int eoc4_ovflg : 1; /**< Overflow status of eoc4 */ + unsigned int eoc5_ovflg : 1; /**< Overflow status of eoc5 */ + unsigned int eoc6_ovflg : 1; /**< Overflow status of eoc6 */ + unsigned int eoc7_ovflg : 1; /**< Overflow status of eoc7 */ + unsigned int eoc8_ovflg : 1; /**< Overflow status of eoc8 */ + unsigned int eoc9_ovflg : 1; /**< Overflow status of eoc9 */ + unsigned int eoc10_ovflg : 1; /**< Overflow status of eoc10 */ + unsigned int eoc11_ovflg : 1; /**< Overflow status of eoc11 */ + unsigned int eoc12_ovflg : 1; /**< Overflow status of eoc12 */ + unsigned int eoc13_ovflg : 1; /**< Overflow status of eoc13 */ + unsigned int eoc14_ovflg : 1; /**< Overflow status of eoc14 */ + unsigned int eoc15_ovflg : 1; /**< Overflow status of eoc15 */ + unsigned int reserved0 : 16; + } BIT; +} volatile ADC_EOC_OVFL_REG; + +/** + * @brief Define the union ADC_INT1_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int int1_en : 1; /**< Interrupt 1 enable */ + unsigned int int1_cont : 1; /**< Interrupt 1 pulse enable */ + unsigned int int1_pos : 1; /**< Early interrupt mode */ + unsigned int int1_oven : 1; /**< Interrupt 1 overflow flag enable */ + unsigned int int1_offset : 12; /**< Interrupt 1 offset enable */ + unsigned int int1_eoc_en : 16; /**< Enables the eoc that can trigger interrupt 1 */ + } BIT; +} volatile ADC_INT1_CTRL_REG; + +/** + * @brief Define the union ADC_INT2_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int int2_en : 1; /**< Interrupt 2 enable */ + unsigned int int2_cont : 1; /**< Interrupt 2 pulse enable */ + unsigned int int2_pos : 1; /**< Early interrupt mode */ + unsigned int int2_oven : 1; /**< Interrupt 2 overflow flag enable */ + unsigned int int2_offset : 12; /**< Interrupt 2 offset enable */ + unsigned int int2_eoc_en : 16; /**< Enables the eoc that can trigger interrupt 2 */ + } BIT; +} volatile ADC_INT2_CTRL_REG; + +/** + * @brief Define the union ADC_INT3_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int int3_en : 1; /**< Interrupt 3 enable */ + unsigned int int3_cont : 1; /**< Interrupt 3 pulse enable */ + unsigned int int3_pos : 1; /**< Early interrupt mode */ + unsigned int int3_oven : 1; /**< Interrupt 3 overflow flag enable */ + unsigned int int3_offset : 12; /**< Interrupt 3 offset enable */ + unsigned int int3_eoc_en : 16; /**< Enables the eoc that can trigger interrupt 3 */ + } BIT; +} volatile ADC_INT3_CTRL_REG; + +/** + * @brief Define the union ADC_INT4_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int int4_en : 1; /**< Interrupt 4 enable */ + unsigned int int4_cont : 1; /**< Interrupt 4 pulse enable */ + unsigned int int4_pos : 1; /**< Early interrupt mode */ + unsigned int int4_oven : 1; /**< Interrupt 4 overflow flag enable */ + unsigned int int4_offset : 12; /**< Interrupt 4 offset enable */ + unsigned int int4_eoc_en : 16; /**< Enables the eoc that can trigger interrupt 4 */ + } BIT; +} volatile ADC_INT4_CTRL_REG; + +/** + * @brief Define the union ADC_INT_OFFSET_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int dma_sing_req_sel : 1; /**< DMA single request enable */ + unsigned int dma_brst_req_sel : 1; /**< DMA burst request enable */ + unsigned int dma_int_sel : 4; /**< Selecting the DMA interrupt source */ + unsigned int reserved0 : 26; + } BIT; +} volatile ADC_INT_OFFSET_REG; + +/** + * @brief Define the union ADC_SOC_PRICTL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int soc_priority : 16; /**< High-priority configuration */ + unsigned int reserved0 : 16; + } BIT; +} volatile ADC_SOC_PRICTL_REG; + +/** + * @brief Define the union ADC_SOFT_TRIG_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int soc0_soft_trig : 1; /**< SOC0 triggered by software */ + unsigned int soc1_soft_trig : 1; /**< SOC1 triggered by software */ + unsigned int soc2_soft_trig : 1; /**< SOC2 triggered by software */ + unsigned int soc3_soft_trig : 1; /**< SOC3 triggered by software */ + unsigned int soc4_soft_trig : 1; /**< SOC4 triggered by software */ + unsigned int soc5_soft_trig : 1; /**< SOC5 triggered by software */ + unsigned int soc6_soft_trig : 1; /**< SOC6 triggered by software */ + unsigned int soc7_soft_trig : 1; /**< SOC7 triggered by software */ + unsigned int soc8_soft_trig : 1; /**< SOC8 triggered by software */ + unsigned int soc9_soft_trig : 1; /**< SOC9 triggered by software */ + unsigned int soc10_soft_trig : 1; /**< SOC10 triggered by software */ + unsigned int soc11_soft_trig : 1; /**< SOC11 triggered by software */ + unsigned int soc12_soft_trig : 1; /**< SOC12 triggered by software */ + unsigned int soc13_soft_trig : 1; /**< SOC13 triggered by software */ + unsigned int soc14_soft_trig : 1; /**< SOC14 triggered by software */ + unsigned int soc15_soft_trig : 1; /**< SOC15 triggered by software */ + unsigned int reserved0 : 16; + } BIT; +} volatile ADC_SOFT_TRIG_REG; + +/** + * @brief Define the union ADC_TRIG_OVFL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int soc0_trig_ovflg : 1; /**< Trigger overflow flag of SOC0 */ + unsigned int soc1_trig_ovflg : 1; /**< Trigger overflow flag of SOC1 */ + unsigned int soc2_trig_ovflg : 1; /**< Trigger overflow flag of SOC2 */ + unsigned int soc3_trig_ovflg : 1; /**< Trigger overflow flag of SOC3 */ + unsigned int soc4_trig_ovflg : 1; /**< Trigger overflow flag of SOC4 */ + unsigned int soc5_trig_ovflg : 1; /**< Trigger overflow flag of SOC5 */ + unsigned int soc6_trig_ovflg : 1; /**< Trigger overflow flag of SOC6 */ + unsigned int soc7_trig_ovflg : 1; /**< Trigger overflow flag of SOC7 */ + unsigned int soc8_trig_ovflg : 1; /**< Trigger overflow flag of SOC8 */ + unsigned int soc9_trig_ovflg : 1; /**< Trigger overflow flag of SOC9 */ + unsigned int soc10_trig_ovflg : 1; /**< Trigger overflow flag of SOC10 */ + unsigned int soc11_trig_ovflg : 1; /**< Trigger overflow flag of SOC11 */ + unsigned int soc12_trig_ovflg : 1; /**< Trigger overflow flag of SOC12 */ + unsigned int soc13_trig_ovflg : 1; /**< Trigger overflow flag of SOC13 */ + unsigned int soc14_trig_ovflg : 1; /**< Trigger overflow flag of SOC14 */ + unsigned int soc15_trig_ovflg : 1; /**< Trigger overflow flag of SOC15 */ + unsigned int reserved0 : 16; + } BIT; +} volatile ADC_TRIG_OVFL_REG; + +/** + * @brief Define the union ADC_SOC0_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int soc0_chsel : 4; /**< Channel selection */ + unsigned int soc0_trig_sel : 5; /**< Trigger source selection */ + unsigned int soc0_int_trig_sel : 2; /**< Feedback interrupt trigger configuration */ + unsigned int soc0_acqps : 7; /**< Capacitor charging time */ + unsigned int soc0_rslt_rclr : 1; /**< Read-clear enable */ + unsigned int reserved0 : 1; + unsigned int soc0_sh_hold : 6; /**< Sample and Hold Circuit Hold Time */ + unsigned int reserved1 : 6; + } BIT; +} volatile ADC_SOC0_CTRL_REG; + +/** + * @brief Define the union ADC_SOC1_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int soc1_chsel : 4; /**< Channel selection */ + unsigned int soc1_trig_sel : 5; /**< Trigger source selection */ + unsigned int soc1_int_trig_sel : 2; /**< Feedback interrupt trigger configuration */ + unsigned int soc1_acqps : 7; /**< Capacitor charging time */ + unsigned int soc1_rslt_rclr : 1; /**< Read-clear enable */ + unsigned int reserved0 : 1; + unsigned int soc1_sh_hold : 6; /**< Sample and Hold Circuit Hold Time */ + unsigned int reserved1 : 6; + } BIT; +} volatile ADC_SOC1_CTRL_REG; + +/** + * @brief Define the union ADC_SOC2_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int soc2_chsel : 4; /**< Channel selection */ + unsigned int soc2_trig_sel : 5; /**< Trigger source selection */ + unsigned int soc2_int_trig_sel : 2; /**< Feedback interrupt trigger configuration */ + unsigned int soc2_acqps : 7; /**< Capacitor charging time */ + unsigned int soc2_rslt_rclr : 1; /**< Read-clear enable */ + unsigned int reserved0 : 1; + unsigned int soc2_sh_hold : 6; /**< Sample and Hold Circuit Hold Time */ + unsigned int reserved1 : 6; + } BIT; +} volatile ADC_SOC2_CTRL_REG; + +/** + * @brief Define the union ADC_SOC3_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int soc3_chsel : 4; /**< Channel selection */ + unsigned int soc3_trig_sel : 5; /**< Trigger source selection */ + unsigned int soc3_int_trig_sel : 2; /**< Feedback interrupt trigger configuration */ + unsigned int soc3_acqps : 7; /**< Capacitor charging time */ + unsigned int soc3_rslt_rclr : 1; /**< Read-clear enable */ + unsigned int reserved0 : 1; + unsigned int soc3_sh_hold : 6; /**< Sample and Hold Circuit Hold Time */ + unsigned int reserved1 : 6; + } BIT; +} volatile ADC_SOC3_CTRL_REG; + +/** + * @brief Define the union ADC_SOC4_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int soc4_chsel : 4; /**< Channel selection */ + unsigned int soc4_trig_sel : 5; /**< Trigger source selection */ + unsigned int soc4_int_trig_sel : 2; /**< Feedback interrupt trigger configuration */ + unsigned int soc4_acqps : 7; /**< Capacitor charging time */ + unsigned int soc4_rslt_rclr : 1; /**< Read-clear enable */ + unsigned int reserved0 : 1; + unsigned int soc4_sh_hold : 6; /**< Sample and Hold Circuit Hold Time */ + unsigned int reserved1 : 6; + } BIT; +} volatile ADC_SOC4_CTRL_REG; + +/** + * @brief Define the union ADC_SOC5_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int soc5_chsel : 4; /**< Channel selection */ + unsigned int soc5_trig_sel : 5; /**< Trigger source selection */ + unsigned int soc5_int_trig_sel : 2; /**< Feedback interrupt trigger configuration */ + unsigned int soc5_acqps : 7; /**< Capacitor charging time */ + unsigned int soc5_rslt_rclr : 1; /**< Read-clear enable */ + unsigned int reserved0 : 1; + unsigned int soc5_sh_hold : 6; /**< Sample and Hold Circuit Hold Time */ + unsigned int reserved1 : 6; + } BIT; +} volatile ADC_SOC5_CTRL_REG; + +/** + * @brief Define the union ADC_SOC6_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int soc6_chsel : 4; /**< Channel selection */ + unsigned int soc6_trig_sel : 5; /**< Trigger source selection */ + unsigned int soc6_int_trig_sel : 2; /**< Feedback interrupt trigger configuration */ + unsigned int soc6_acqps : 7; /**< Capacitor charging time */ + unsigned int soc6_rslt_rclr : 1; /**< Read-clear enable */ + unsigned int reserved0 : 1; + unsigned int soc6_sh_hold : 6; /**< Sample and Hold Circuit Hold Time */ + unsigned int reserved1 : 6; + } BIT; +} volatile ADC_SOC6_CTRL_REG; + +/** + * @brief Define the union ADC_SOC7_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int soc7_chsel : 4; /**< Channel selection */ + unsigned int soc7_trig_sel : 5; /**< Trigger source selection */ + unsigned int soc7_int_trig_sel : 2; /**< Feedback interrupt trigger configuration */ + unsigned int soc7_acqps : 7; /**< Capacitor charging time */ + unsigned int soc7_rslt_rclr : 1; /**< Read-clear enable */ + unsigned int reserved0 : 1; + unsigned int soc7_sh_hold : 6; /**< Sample and Hold Circuit Hold Time */ + unsigned int reserved1 : 6; + } BIT; +} volatile ADC_SOC7_CTRL_REG; + +/** + * @brief Define the union ADC_SOC8_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int soc8_chsel : 4; /**< Channel selection */ + unsigned int soc8_trig_sel : 5; /**< Trigger source selection */ + unsigned int soc8_int_trig_sel : 2; /**< Feedback interrupt trigger configuration */ + unsigned int soc8_acqps : 7; /**< Capacitor charging time */ + unsigned int soc8_rslt_rclr : 1; /**< Read-clear enable */ + unsigned int reserved0 : 1; + unsigned int soc8_sh_hold : 6; /**< Sample and Hold Circuit Hold Time */ + unsigned int reserved1 : 6; + } BIT; +} volatile ADC_SOC8_CTRL_REG; + +/** + * @brief Define the union ADC_SOC9_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int soc9_chsel : 4; /**< Channel selection */ + unsigned int soc9_trig_sel : 5; /**< Trigger source selection */ + unsigned int soc9_int_trig_sel : 2; /**< Feedback interrupt trigger configuration */ + unsigned int soc9_acqps : 7; /**< Capacitor charging time */ + unsigned int soc9_rslt_rclr : 1; /**< Read-clear enable */ + unsigned int reserved0 : 1; + unsigned int soc9_sh_hold : 6; /**< Sample and Hold Circuit Hold Time */ + unsigned int reserved1 : 6; + } BIT; +} volatile ADC_SOC9_CTRL_REG; + +/** + * @brief Define the union ADC_SOC10_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int soc10_chsel : 4; /**< Channel selection */ + unsigned int soc10_trig_sel : 5; /**< Trigger source selection */ + unsigned int soc10_int_trig_sel : 2; /**< Feedback interrupt trigger configuration */ + unsigned int soc10_acqps : 7; /**< Capacitor charging time */ + unsigned int soc10_rslt_rclr : 1; /**< Read-clear enable */ + unsigned int reserved0 : 1; + unsigned int soc10_sh_hold : 6; /**< Sample and Hold Circuit Hold Time */ + unsigned int reserved1 : 6; + } BIT; +} volatile ADC_SOC10_CTRL_REG; + +/** + * @brief Define the union ADC_SOC11_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int soc11_chsel : 4; /**< Channel selection */ + unsigned int soc11_trig_sel : 5; /**< Trigger source selection */ + unsigned int soc11_int_trig_sel : 2; /**< Feedback interrupt trigger configuration */ + unsigned int soc11_acqps : 7; /**< Capacitor charging time */ + unsigned int soc11_rslt_rclr : 1; /**< Read-clear enable */ + unsigned int reserved0 : 1; + unsigned int soc11_sh_hold : 6; /**< Sample and Hold Circuit Hold Time */ + unsigned int reserved1 : 6; + } BIT; +} volatile ADC_SOC11_CTRL_REG; + +/** + * @brief Define the union ADC_SOC12_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int soc12_chsel : 4; /**< Channel selection */ + unsigned int soc12_trig_sel : 5; /**< Trigger source selection */ + unsigned int soc12_int_trig_sel : 2; /**< Feedback interrupt trigger configuration */ + unsigned int soc12_acqps : 7; /**< Capacitor charging time */ + unsigned int soc12_rslt_rclr : 1; /**< Read-clear enable */ + unsigned int reserved0 : 1; + unsigned int soc12_sh_hold : 6; /**< Sample and Hold Circuit Hold Time */ + unsigned int reserved1 : 6; + } BIT; +} volatile ADC_SOC12_CTRL_REG; + +/** + * @brief Define the union ADC_SOC13_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int soc13_chsel : 4; /**< Channel selection */ + unsigned int soc13_trig_sel : 5; /**< Trigger source selection */ + unsigned int soc13_int_trig_sel : 2; /**< Feedback interrupt trigger configuration */ + unsigned int soc13_acqps : 7; /**< Capacitor charging time */ + unsigned int soc13_rslt_rclr : 1; /**< Read-clear enable */ + unsigned int reserved0 : 1; + unsigned int soc13_sh_hold : 6; /**< Sample and Hold Circuit Hold Time */ + unsigned int reserved1 : 6; + } BIT; +} volatile ADC_SOC13_CTRL_REG; + +/** + * @brief Define the union ADC_SOC14_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int soc14_chsel : 4; /**< Channel selection */ + unsigned int soc14_trig_sel : 5; /**< Trigger source selection */ + unsigned int soc14_int_trig_sel : 2; /**< Feedback interrupt trigger configuration */ + unsigned int soc14_acqps : 7; /**< Capacitor charging time */ + unsigned int soc14_rslt_rclr : 1; /**< Read-clear enable */ + unsigned int reserved0 : 1; + unsigned int soc14_sh_hold : 6; /**< Sample and Hold Circuit Hold Time */ + unsigned int reserved1 : 6; + } BIT; +} volatile ADC_SOC14_CTRL_REG; + +/** + * @brief Define the union ADC_SOC15_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int soc15_chsel : 4; /**< Channel selection */ + unsigned int soc15_trig_sel : 5; /**< Trigger source selection */ + unsigned int soc15_int_trig_sel : 2; /**< Feedback interrupt trigger configuration */ + unsigned int soc15_acqps : 7; /**< Capacitor charging time */ + unsigned int soc15_rslt_rclr : 1; /**< Read-clear enable */ + unsigned int reserved0 : 1; + unsigned int soc15_sh_hold : 6; /**< Sample and Hold Circuit Hold Time */ + unsigned int reserved1 : 6; + } BIT; +} volatile ADC_SOC15_CTRL_REG; + +/** + * @brief Define the union ADC_PPB0_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int ppb0_ch_sel : 4; /**< PPB channel selection */ + unsigned int ppb0_en : 1; /**< PPB Enable */ + unsigned int reserved0 : 27; + } BIT; +} volatile ADC_PPB0_CTRL_REG; + +/** + * @brief Define the union ADC_PPB1_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int ppb1_ch_sel : 4; /**< PPB channel selection */ + unsigned int ppb1_en : 1; /**< PPB Enable */ + unsigned int reserved0 : 27; + } BIT; +} volatile ADC_PPB1_CTRL_REG; + +/** + * @brief Define the union ADC_PPB2_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int ppb2_ch_sel : 4; /**< PPB channel selection */ + unsigned int ppb2_en : 1; /**< PPB Enable */ + unsigned int reserved0 : 27; + } BIT; +} volatile ADC_PPB2_CTRL_REG; + +/** + * @brief Define the union ADC_PPB3_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int ppb3_ch_sel : 4; /**< PPB channel selection */ + unsigned int ppb3_en : 1; /**< PPB Enable */ + unsigned int reserved0 : 27; + } BIT; +} volatile ADC_PPB3_CTRL_REG; + +/** + * @brief Define the union ADC_PPB0_PPB1_DLY_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int ppb0_dly_stamp : 16; /**< Sampling delay of PPB1 */ + unsigned int ppb1_dly_stamp : 16; /**< Sampling delay of PPB0 */ + } BIT; +} volatile ADC_PPB0_PPB1_DLY_REG; + +/** + * @brief Define the union ADC_PPB2_PPB3_DLY_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int ppb2_dly_stamp : 16; /**< Sampling delay of PPB2 */ + unsigned int ppb3_dly_stamp : 16; /**< Sampling delay of PPB3 */ + } BIT; +} volatile ADC_PPB2_PPB3_DLY_REG; + +/** + * @brief Define the union ADC_ANA_CTRL_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int ana_logic_mode : 1; /**< ADC Analog Operating Modes */ + unsigned int reserved1 : 1; + unsigned int adc_ana_gsh0 : 2; /**< S/H0 Attenuation Configuration */ + unsigned int adc_ana_gsh1 : 2; /**< S/H1 Attenuation Configuration */ + unsigned int adc_ana_dish : 2; /**< OFFSET Calibration Control */ + unsigned int reserved2 : 23; + } BIT; +} volatile ADC_ANA_CTRL_REG; + +/** + * @brief Define the union ADC_SAR_CTRL0_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 3; + unsigned int cap_start_index : 4; /**< Selecte Calibration Capacitor */ + unsigned int reserved1 : 25; + } BIT; +} volatile ADC_SAR_CTRL0_REG; + +/** + * @brief Define the union ADC_SAR_CTRL3_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int cap_start : 1; /**< Capacitive Calibration Trigger */ + unsigned int reserved0 : 31; + } BIT; +} volatile ADC_SAR_CTRL3_REG; + +/** + * @brief Define the union ADC_OFF_CALI1_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int ofst_calana_cfg : 6; /**< Analog offset configured by software */ + unsigned int reserved0 : 1; + unsigned int ofst_ana_sel : 1; /**< Select analog offset input source */ + unsigned int ofst_digcal_cfg : 14; /**< Software configuration digital offset */ + unsigned int ofst_digcal_sel : 1; /**< Select digital offset input source */ + unsigned int reserved1 : 9; + } BIT; +} volatile ADC_OFF_CALI1_REG; + +/** + * @brief Define the union ADC_OFF_CALI2_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_avg_start : 1; /**< Starts to calculate the average offset value */ + unsigned int reserved0 : 31; + } BIT; +} volatile ADC_OFF_CALI2_REG; + +/** + * @brief Define the union ADC_OFF_CALI4_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int ofst_caliana : 6; /**< Analog offset value */ + unsigned int reserved0 : 1; + unsigned int ofst_calidig : 14; /**< Digital offset */ + unsigned int adc_ofst_calib_done : 1; /**< Offset calibration end flag */ + unsigned int adc_ofst_calib_error : 1; /**< Offset calibration error flag */ + unsigned int reserved1 : 9; + } BIT; +} volatile ADC_OFF_CALI4_REG; + +/** + * @brief Define the union ADC_CAP_CALI0_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 21; + unsigned int adc_weight_ini_sel : 1; /**< Weight selection */ + unsigned int cap_cal1_finish : 1; /**< Capacitor calibration completion flag */ + unsigned int reserved1 : 9; + } BIT; +} volatile ADC_CAP_CALI0_REG; + +/** + * @brief Define the union ADC_DATA_PROCS0_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int gain_digcal_cfg : 13; /**< Calibration gain value configured by software */ + unsigned int reserved1 : 18; + } BIT; +} volatile ADC_DATA_PROCS0_REG; + +/** + * @brief Define the union ADC_ANA_PD_REG + */ +typedef union { + unsigned int reg; + struct { + unsigned int adc_pwdnz : 1; /**< ADC analog power supply */ + unsigned int reserved0 : 31; + } BIT; +} volatile ADC_ANA_PD_REG; + +/** + * @brief Define the ADC resistor struct. + */ +typedef struct { + ADC_RESULT0_REG ADC_RESULT0; /**< Offset address: 0x00000000U */ + ADC_RESULT1_REG ADC_RESULT1; /**< Offset address: 0x00000004U */ + ADC_RESULT2_REG ADC_RESULT2; /**< Offset address: 0x00000008U */ + ADC_RESULT3_REG ADC_RESULT3; /**< Offset address: 0x0000000CU */ + ADC_RESULT4_REG ADC_RESULT4; /**< Offset address: 0x00000010U */ + ADC_RESULT5_REG ADC_RESULT5; /**< Offset address: 0x00000014U */ + ADC_RESULT6_REG ADC_RESULT6; /**< Offset address: 0x00000018U */ + ADC_RESULT7_REG ADC_RESULT7; /**< Offset address: 0x0000001CU */ + ADC_RESULT8_REG ADC_RESULT8; /**< Offset address: 0x00000020U */ + ADC_RESULT9_REG ADC_RESULT9; /**< Offset address: 0x00000024U */ + ADC_RESULT10_REG ADC_RESULT10; /**< Offset address: 0x00000028U */ + ADC_RESULT11_REG ADC_RESULT11; /**< Offset address: 0x0000002CU */ + ADC_RESULT12_REG ADC_RESULT12; /**< Offset address: 0x00000030U */ + ADC_RESULT13_REG ADC_RESULT13; /**< Offset address: 0x00000034U */ + ADC_RESULT14_REG ADC_RESULT14; /**< Offset address: 0x00000038U */ + ADC_RESULT15_REG ADC_RESULT15; /**< Offset address: 0x0000003CU */ + ADC_CTRL_REG ADC_CTRL; /**< Offset address: 0x00000040U */ + ADC_STATUS_REG ADC_STATUS; /**< Offset address: 0x00000044U */ + ADC_SOC_PRICTL_SET_REG ADC_SOC_PRICTL_SET; /**< Offset address: 0x00000048U */ + ADC_SAMPLE_MODE_REG ADC_SAMPLE_MODE; /**< Offset address: 0x0000004CU */ + ADC_INT_FLAG_REG ADC_INT_FLAG; /**< Offset address: 0x00000050U */ + ADC_EOC_FLAG_REG ADC_EOC_FLAG; /**< Offset address: 0x00000054U */ + ADC_INT_OVFL_REG ADC_INT_OVFL; /**< Offset address: 0x00000058U */ + ADC_EOC_OVFL_REG ADC_EOC_OVFL; /**< Offset address: 0x0000005CU */ + ADC_INT1_CTRL_REG ADC_INT1_CTRL; /**< Offset address: 0x00000060U */ + ADC_INT2_CTRL_REG ADC_INT2_CTRL; /**< Offset address: 0x00000064U */ + ADC_INT3_CTRL_REG ADC_INT3_CTRL; /**< Offset address: 0x00000068U */ + ADC_INT4_CTRL_REG ADC_INT4_CTRL; /**< Offset address: 0x0000006CU */ + ADC_INT_OFFSET_REG ADC_INT_OFFSET; /**< Offset address: 0x00000070U */ + ADC_SOC_PRICTL_REG ADC_SOC_PRICTL; /**< Offset address: 0x00000074U */ + ADC_SOFT_TRIG_REG ADC_SOFT_TRIG; /**< Offset address: 0x00000078U */ + ADC_TRIG_OVFL_REG ADC_TRIG_OVFL; /**< Offset address: 0x0000007CU */ + ADC_SOC0_CTRL_REG ADC_SOC0_CTRL; /**< Offset address: 0x00000080U */ + ADC_SOC1_CTRL_REG ADC_SOC1_CTRL; /**< Offset address: 0x00000084U */ + ADC_SOC2_CTRL_REG ADC_SOC2_CTRL; /**< Offset address: 0x00000088U */ + ADC_SOC3_CTRL_REG ADC_SOC3_CTRL; /**< Offset address: 0x0000008CU */ + ADC_SOC4_CTRL_REG ADC_SOC4_CTRL; /**< Offset address: 0x00000090U */ + ADC_SOC5_CTRL_REG ADC_SOC5_CTRL; /**< Offset address: 0x00000094U */ + ADC_SOC6_CTRL_REG ADC_SOC6_CTRL; /**< Offset address: 0x00000098U */ + ADC_SOC7_CTRL_REG ADC_SOC7_CTRL; /**< Offset address: 0x0000009CU */ + ADC_SOC8_CTRL_REG ADC_SOC8_CTRL; /**< Offset address: 0x000000A0U */ + ADC_SOC9_CTRL_REG ADC_SOC9_CTRL; /**< Offset address: 0x000000A4U */ + ADC_SOC10_CTRL_REG ADC_SOC10_CTRL; /**< Offset address: 0x000000A8U */ + ADC_SOC11_CTRL_REG ADC_SOC11_CTRL; /**< Offset address: 0x000000ACU */ + ADC_SOC12_CTRL_REG ADC_SOC12_CTRL; /**< Offset address: 0x000000B0U */ + ADC_SOC13_CTRL_REG ADC_SOC13_CTRL; /**< Offset address: 0x000000B4U */ + ADC_SOC14_CTRL_REG ADC_SOC14_CTRL; /**< Offset address: 0x000000B8U */ + unsigned char space0[4]; + ADC_SOC15_CTRL_REG ADC_SOC15_CTRL; /**< Offset address: 0x000000C0U */ + ADC_PPB0_CTRL_REG ADC_PPB0_CTRL; /**< Offset address: 0x000000C4U */ + ADC_PPB1_CTRL_REG ADC_PPB1_CTRL; /**< Offset address: 0x000000C8U */ + unsigned char space1[4]; + ADC_PPB2_CTRL_REG ADC_PPB2_CTRL; /**< Offset address: 0x000000D0U */ + ADC_PPB3_CTRL_REG ADC_PPB3_CTRL; /**< Offset address: 0x000000D4U */ + ADC_PPB0_PPB1_DLY_REG ADC_PPB0_PPB1_DLY; /**< Offset address: 0x000000D8U */ + ADC_PPB2_PPB3_DLY_REG ADC_PPB2_PPB3_DLY; /**< Offset address: 0x000000DCU */ + ADC_ANA_CTRL_REG ADC_ANA_CTRL; /**< Offset address: 0x000000E0U */ + ADC_SAR_CTRL0_REG ADC_SAR_CTRL0; /**< Offset address: 0x000000E4U */ + unsigned char space2[8]; + ADC_SAR_CTRL3_REG ADC_SAR_CTRL3; /**< Offset address: 0x000000F0U */ + unsigned char space3[8]; + ADC_OFF_CALI1_REG ADC_OFF_CALI1; /**< Offset address: 0x000000FCU */ + ADC_OFF_CALI2_REG ADC_OFF_CALI2; /**< Offset address: 0x00000100U */ + unsigned char space4[4]; + ADC_OFF_CALI4_REG ADC_OFF_CALI4; /**< Offset address: 0x00000108U */ + ADC_CAP_CALI0_REG ADC_CAP_CALI0; /**< Offset address: 0x0000010CU */ + unsigned char space5[188]; + ADC_DATA_PROCS0_REG ADC_DATA_PROCS0; /**< Offset address: 0x000001CCU */ + unsigned char space6[4]; + ADC_ANA_PD_REG ADC_ANA_PD; /**< Offset address: 0x000001D4U */ +} volatile ADC_RegStruct; +/** + * @} + */ + + +/** + * @defgroup ADC_Param_Def ADC Parameters Definition + * @brief Description of ADC configuration parameters. + * @{ + */ +/** + * @brief Synchronous sample group classification. + * @details Syncsample group type: + * + Group1 -- Synchronous sample group: SOC0 and SOC1 + * + Group2 -- Synchronous sample group: SOC2 and SOC3 + * + Group3 -- Synchronous sample group: SOC4 and SOC5 + * + Group4 -- Synchronous sample group: SOC6 and SOC7 + * + Group5 -- Synchronous sample group: SOC8 and SOC9 + * + Group6 -- Synchronous sample group: SOC10 and SOC11 + * + Group7 -- Synchronous sample group: SOC12 and SOC13 + * + Group8 -- Synchronous sample group: SOC14 and SOC15 + */ +typedef enum { + ADC_SYNCSAMPLE_GROUP_1 = 0x00000001U, + ADC_SYNCSAMPLE_GROUP_2 = 0x00000002U, + ADC_SYNCSAMPLE_GROUP_3 = 0x00000004U, + ADC_SYNCSAMPLE_GROUP_4 = 0x00000008U, + ADC_SYNCSAMPLE_GROUP_5 = 0x00000010U, + ADC_SYNCSAMPLE_GROUP_6 = 0x00000020U, + ADC_SYNCSAMPLE_GROUP_7 = 0x00000040U, + ADC_SYNCSAMPLE_GROUP_8 = 0x00000080U +} ADC_SyncSampleGroup; + +/** + * @brief ADC sample input. + * @details Input type: + * + ADC_CH_ADCINA0 -- ADCINA0 is converted, number 0 + * + ADC_CH_ADCINA1 -- ADCINA1 is converted, number 1 + * + ADC_CH_ADCINA2 -- ADCINA2 is converted, number 2 + * + ADC_CH_ADCINA3 -- ADCINA3 is converted, number 3 + * + ADC_CH_ADCINA4 -- ADCINA4 is converted, number 4 + * + ADC_CH_ADCINA5 -- ADCINA5 is converted, number 5 + * + ADC_CH_ADCINA6 -- ADCINA6 is converted, number 6 + * + ADC_CH_ADCINA7 -- ADCINA7 is converted, number 7 + * + ADC_CH_ADCINB0 -- ADCINB0 is converted, number 8 + * + ADC_CH_ADCINB1 -- ADCINB1 is converted, number 9 + * + ADC_CH_ADCINB2 -- ADCINB2 is converted, number 10 + * + ADC_CH_ADCINB3 -- ADCINB3 is converted, number 11 + * + ADC_CH_ADCINB4 -- ADCINB4 is converted, number 12 + * + ADC_CH_ADCINB5 -- ADCINB5 is converted, number 13 + * + ADC_CH_ADCINB6 -- ADCINB6 is converted, number 14 + * + ADC_CH_ADCINB7 -- ADCINB7 is converted, number 15 + */ +typedef enum { + ADC_CH_ADCINA0 = 0x00000000U, + ADC_CH_ADCINA1 = 0x00000001U, + ADC_CH_ADCINA2 = 0x00000002U, + ADC_CH_ADCINA3 = 0x00000003U, + ADC_CH_ADCINA4 = 0x00000004U, + ADC_CH_ADCINA5 = 0x00000005U, + ADC_CH_ADCINA6 = 0x00000006U, + ADC_CH_ADCINA7 = 0x00000007U, + ADC_CH_ADCINB0 = 0x00000008U, + ADC_CH_ADCINB1 = 0x00000009U, + ADC_CH_ADCINB2 = 0x0000000AU, + ADC_CH_ADCINB3 = 0x0000000BU, + ADC_CH_ADCINB4 = 0x0000000CU, + ADC_CH_ADCINB5 = 0x0000000DU, + ADC_CH_ADCINB6 = 0x0000000EU, + ADC_CH_ADCINB7 = 0x0000000FU +} ADC_Input; + +/** + * @brief ADC SOC(start of conversion) classification. + */ +typedef enum { + ADC_SOC_NUM0 = 0x00000000U, + ADC_SOC_NUM1 = 0x00000001U, + ADC_SOC_NUM2 = 0x00000002U, + ADC_SOC_NUM3 = 0x00000003U, + ADC_SOC_NUM4 = 0x00000004U, + ADC_SOC_NUM5 = 0x00000005U, + ADC_SOC_NUM6 = 0x00000006U, + ADC_SOC_NUM7 = 0x00000007U, + ADC_SOC_NUM8 = 0x00000008U, + ADC_SOC_NUM9 = 0x00000009U, + ADC_SOC_NUM10 = 0x0000000AU, + ADC_SOC_NUM11 = 0x0000000BU, + ADC_SOC_NUM12 = 0x0000000CU, + ADC_SOC_NUM13 = 0x0000000DU, + ADC_SOC_NUM14 = 0x0000000EU, + ADC_SOC_NUM15 = 0x0000000FU +} ADC_SOCNumber; + +/** + * @brief ADC four interrupt classification. + * @details Interrupt type: + * + ADC_INT_NUMBER1 -- ADCINT1 interrupt + * + ADC_INT_NUMBER2 -- ADCINT2 interrupt + * + ADC_INT_NUMBER3 -- ADCINT3 interrupt + * + ADC_INT_NUMBER4 -- ADCINT4 interrupt + */ +typedef enum { + ADC_INT_NUMBER1 = 0x00000000U, + ADC_INT_NUMBER2 = 0x00000001U, + ADC_INT_NUMBER3 = 0x00000002U, + ADC_INT_NUMBER4 = 0x00000003U +} ADC_IntNumber; + +/** + * @brief ADC supports three internal interrupt feedback trigger soc sample. + * @details Interrupt trigger source type: + * + ADC_TRIGSOC_NONEINT -- NONE + * + ADC_TRIGSOC_INT1 -- ADCINT1 interrupt trigger soc + * + ADC_TRIGSOC_INT2 -- ADCINT2 interrupt trigger soc + * + ADC_TRIGSOC_INT3 -- ADCINT3 interrupt trigger soc + */ +typedef enum { + ADC_TRIGSOC_NONEINT = 0x00000000U, + ADC_TRIGSOC_INT1 = 0x00000001U, + ADC_TRIGSOC_INT2 = 0x00000002U, + ADC_TRIGSOC_INT3 = 0x00000003U +} ADC_IntTrigSoc; + +/** + * @brief ADC supports peripherals trigger source. + */ +typedef enum { + ADC_TRIGSOC_NONEPERIPH = 0x00000000U, + ADC_TRIGSOC_APT0_SOCA = 0x00000001U, + ADC_TRIGSOC_APT0_SOCB = 0x00000002U, + ADC_TRIGSOC_APT1_SOCA = 0x00000003U, + ADC_TRIGSOC_APT1_SOCB = 0x00000004U, + ADC_TRIGSOC_APT2_SOCA = 0x00000005U, + ADC_TRIGSOC_APT2_SOCB = 0x00000006U, + ADC_TRIGSOC_APT3_SOCA = 0x00000007U, + ADC_TRIGSOC_APT3_SOCB = 0x00000008U, + ADC_TRIGSOC_APT4_SOCA = 0x00000009U, + ADC_TRIGSOC_APT4_SOCB = 0x0000000AU, + ADC_TRIGSOC_APT5_SOCA = 0x0000000BU, + ADC_TRIGSOC_APT5_SOCB = 0x0000000CU, + ADC_TRIGSOC_APT6_SOCA = 0x0000000DU, + ADC_TRIGSOC_APT6_SOCB = 0x0000000EU, + ADC_TRIGSOC_APT7_SOCA = 0x0000000FU, + ADC_TRIGSOC_APT7_SOCB = 0x00000010U, + ADC_TRIGSOC_APT8_SOCA = 0x00000011U, + ADC_TRIGSOC_APT8_SOCB = 0x00000012U, + ADC_TRIGSOC_TIMER0 = 0x00000013U, + ADC_TRIGSOC_TIMER1 = 0x00000014U, + ADC_TRIGSOC_TIMER2 = 0x00000015U, + ADC_TRIGSOC_TIMER3 = 0x00000016U, + ADC_TRIGSOC_GPIO = 0x00000017U, +} ADC_PeriphTrigSoc; + +/** + * @brief The type of software trigger source. + */ +typedef enum { + ADC_TRIGSOC_NONESOFT = 0x00000000U, + ADC_TRIGSOC_SOFT = 0x00000001U, +} ADC_SoftTrigSoc; + +/** + * @brief The type of interrupt. + * @details Interrupt type: + * + ADC_INTMODE_NORMAL -- ADCINT normal interrupt + * + ADC_INTMODE_EARLYINT -- ADCINT early interrupt + */ +typedef enum { + ADC_INTMODE_NORMAL = 0x00000000U, + ADC_INTMODE_EARLYINT = 0x00000001U +} ADC_IntMode; + +/** + * @brief The type of DMA request. + * @details DMA request type: + * + ADC_DMA_SINGLEREQ -- single request + * + ADC_DMA_BURSTREQ -- burst request + */ +typedef enum { + ADC_DMA_SINGLEREQ = 0x00000000U, + ADC_DMA_BURSTREQ = 0x00000001U +} ADC_DMARequestType; + +/** + * @brief The type of DMA vref power. + * @details Internal referencevoltage power type: + * + ADC_VREF_2P0V -- 2.0v, select when VDDA < 2.9v + * + ADC_VREF_2P5V -- 2.5v, select when VDDA >= 2.9v + */ +typedef enum { + ADC_VREF_2P0V = 0x00000000U, + ADC_VREF_2P5V = 0x00000001U +} ADC_VrefType; + +/** + * @brief The priority mode of SOCs sample simultaneously. + * @details Priority mode: + * + ADC_PRIMODE_ALL_ROUND -- Round robin mode is used for all + * + ADC_PRIMODE_SOC0 -- SOC0 higher priority, others in round + * + ADC_PRIMODE_TO_SOC1 -- SOC 0-1 higher priority, others in round + * + ADC_PRIMODE_TO_SOC2 -- SOC 0-2 higher priority, others in round + * + ADC_PRIMODE_TO_SOC3 -- SOC 0-3 higher priority, others in round + * + ADC_PRIMODE_TO_SOC4 -- SOC 0-4 higher priority, others in round + * + ADC_PRIMODE_TO_SOC5 -- SOC 0-5 higher priority, others in round + * + ADC_PRIMODE_TO_SOC6 -- SOC 0-6 higher priority, others in round + * + ADC_PRIMODE_TO_SOC7 -- SOC 0-7 higher priority, others in round + * + ADC_PRIMODE_TO_SOC8 -- SOC 0-8 higher priority, others in round + * + ADC_PRIMODE_TO_SOC9 -- SOC 0-9 higher priority, others in round + * + ADC_PRIMODE_TO_SOC10 -- SOC 0-10 higher priority, others in round + * + ADC_PRIMODE_TO_SOC11 -- SOC 0-11 higher priority, others in round + * + ADC_PRIMODE_TO_SOC12 -- SOC 0-12 higher priority, others in round + * + ADC_PRIMODE_TO_SOC13 -- SOC 0-13 higher priority, others in round + * + ADC_PRIMODE_TO_SOC14 -- SOC 0-14 higher priority, others in round + * + ADC_PRIMODE_ALL_PRIORITY -- SOC 0-15 higher priority, others in round + */ +typedef enum { + ADC_PRIMODE_ALL_ROUND = 0x00000000U, + ADC_PRIMODE_SOC0 = 0x00000001U, + ADC_PRIMODE_TO_SOC1 = 0x00000003U, + ADC_PRIMODE_TO_SOC2 = 0x00000007U, + ADC_PRIMODE_TO_SOC3 = 0x0000000FU, + ADC_PRIMODE_TO_SOC4 = 0x0000001FU, + ADC_PRIMODE_TO_SOC5 = 0x0000003FU, + ADC_PRIMODE_TO_SOC6 = 0x0000007FU, + ADC_PRIMODE_TO_SOC7 = 0x000000FFU, + ADC_PRIMODE_TO_SOC8 = 0x000001FFU, + ADC_PRIMODE_TO_SOC9 = 0x000003FFU, + ADC_PRIMODE_TO_SOC10 = 0x000007FFU, + ADC_PRIMODE_TO_SOC11 = 0x00000FFFU, + ADC_PRIMODE_TO_SOC12 = 0x00001FFFU, + ADC_PRIMODE_TO_SOC13 = 0x00003FFFU, + ADC_PRIMODE_TO_SOC14 = 0x00007FFFU, + ADC_PRIMODE_ALL_PRIORITY = 0x0000FFFFU +} ADC_PriorityMode; + +/** + * @brief The number of PPB(post processing block). + */ +typedef enum { + ADC_PPB_NUM0 = 0x00000000U, + ADC_PPB_NUM1 = 0x00000001U, + ADC_PPB_NUM2 = 0x00000002U, + ADC_PPB_NUM3 = 0x00000003U +} ADC_PPBNumber; + +/** + * @brief The mode of SOCs finish sample and conversion. + * @details Priority mode: + * + ADC_SOCFINISH_NONE -- Interruption and DMA are not reported when sampling is complete + * + ADC_SOCFINISH_DMA -- DMA is reported when sampling is complete + * + ADC_SOCFINISH_INT1 -- Interruption 1 is reported when sampling is complete + * + ADC_SOCFINISH_INT2 -- Interruption 2 is reported when sampling is complete + * + ADC_SOCFINISH_INT3 -- Interruption 3 is reported when sampling is complete + * + ADC_SOCFINISH_INT4 -- Interruption 4 is reported when sampling is complete + */ +typedef enum { + ADC_SOCFINISH_NONE = 0x00000001U, + ADC_SOCFINISH_DMA = 0x00000002U, + ADC_SOCFINISH_INT1 = 0x00000003U, + ADC_SOCFINISH_INT2 = 0x00000004U, + ADC_SOCFINISH_INT3 = 0x00000005U, + ADC_SOCFINISH_INT4 = 0x00000006U +}ADC_SOCFinishMode; + +/** + * @brief The type of interrupt call back functions. + */ +typedef enum { + ADC_CALLBACK_INT1 = 0x00000000U, + ADC_CALLBACK_INT2 = 0x00000001U, + ADC_CALLBACK_INT3 = 0x00000002U, + ADC_CALLBACK_INT4 = 0x00000003U, + ADC_CALLBACK_DMA = 0x000000004U, + ADC_CALLBACK_INTOVER = 0x00000005U, + ADC_CALLBACK_DMAOVER = 0x00000006U, + ADC_CALLBACK_TRIGOVER = 0x00000007U, + ADC_CALLBACK_EOCOVER = 0x00000008U, + ADC_CALLBACK_DMAERROR = 0x00000009U, +} ADC_CallbackFunType; + +/** + * @brief The type of gain. + */ +typedef enum { + ADC_GAIN_1 = 0x00000000U, + ADC_GAIN_0P75 = 0x00000001U, + ADC_GAIN_0P6 = 0x00000002U, +} ADC_GainType; + +/* + * Each bit indicates the software triggering status of the SOC. The value 1 indicates enable + * and the value 0 indicates disable. + */ +typedef union { + unsigned int softTrigVal; + struct { + unsigned int trigSoc0 : 1; + unsigned int trigSoc1 : 1; + unsigned int trigSoc2 : 1; + unsigned int trigSoc3 : 1; + unsigned int trigSoc4 : 1; + unsigned int trigSoc5 : 1; + unsigned int trigSoc6 : 1; + unsigned int trigSoc7 : 1; + unsigned int trigSoc8 : 1; + unsigned int trigSoc9 : 1; + unsigned int trigSoc10 : 1; + unsigned int trigSoc11 : 1; + unsigned int trigSoc12 : 1; + unsigned int trigSoc13 : 1; + unsigned int trigSoc14 : 1; + unsigned int trigSoc15 : 1; + unsigned int reserved : 16; + } BIT; +} ADC_SoftMultiTrig; + +/** + * @brief The definition of ADC overflow status. + */ +typedef union { + unsigned int eocOver : 16; + unsigned int trigOver : 16; + unsigned int intOver : 16; +} ADC_OverState; + +extern unsigned int HAL_ADC_ActiveCalibrateRetEx(ADC_RegStruct * const adcx, unsigned int soc, + unsigned int originalRet); + +/** + * @brief The definition of SOC parameter structure. + * Note: + * (1) sampleTotalTime: Sum of hold time and sampling time, unit: adc_clk. sampleTotalTime affects the sampling rate. + * (2) sampleHoldTime: hold time, unit: adc_clk. Generally, the default value 2 is used. + * (3) The sampling time is related to the input circuit model. Sampling time need meet input circuit design. + * The model and formula of sampling time are as follows. Please refer to the Analog-to-Digital Converter (ADC) Section + * of the Chip Data Sheet for details. + * sampling time = (ln(2^n / setting_error) - ln(Cin / Csh_s)) * ((Rs + Ron_s) * Csh_s + Rs * Cin) + * +-----^^^^^^-------+--*----^^^^^---- +----------+ + * | Rs | Ron_s | | + * VIN Cin === Csh_s === ADC_CONVERT + * | | | | + * +------------------+--*-------------------------+ + */ +typedef struct { + ADC_Input adcInput; /**< SOC specified input */ + unsigned int sampleTotalTime; /**< SOC specified input sample total time */ + unsigned int sampleHoldTime; /**< SOC specified input hold time */ + ADC_SoftTrigSoc softTrigSource; /**< SOC specified input software trigger mode */ + ADC_PeriphTrigSoc periphTrigSource; /**< SOC specified input periph trigger source */ + ADC_IntTrigSoc intTrigSource; /**< SOC specified input interrupt trigger source */ + ADC_SOCFinishMode finishMode; /**< SOC specified input mode of finishing sample and conversion */ +} SOC_Param; + +/** + * @brief The definition of synchronous sampling parameter structure. + * Note: + * (1) sampleTotalTime: Sum of hold time and sampling time, unit: adc_clk. sampleTotalTime affects the sampling rate. + * (2) sampleHoldTime: hold time, unit: adc_clk. Generally, the default value 2 is used. + * (3) The sampling time is related to the input circuit model. Sampling time need meet input circuit design. + * The model and formula of sampling time are as follows. Please refer to the Analog-to-Digital Converter (ADC) Section + * of the Chip Data Sheet for details. + * sampling time = (ln(2^n / setting_error) - ln(Cin / Csh_s)) * ((Rs + Ron_s) * Csh_s + Rs * Cin) + * +-----^^^^^^-------+--*----^^^^^---- +----------+ + * | Rs | Ron_s | | + * VIN Cin === Csh_s === ADC_CONVERT + * | | | | + * +------------------+--*-------------------------+ + */ +typedef struct { + ADC_Input ChannelA; /**< The selection range is ADC_CH_ADCINA0 to ADC_CH_ADCINA7 */ + ADC_Input ChannelB; /**< The selection range is ADC_CH_ADCINB0 to ADC_CH_ADCINB7 */ + ADC_SyncSampleGroup group; /**< Syncsample group param */ + unsigned int sampleTotalTime; /**< Generally, the default value 3 is selected */ + unsigned int sampleHoldTime; /**< Generally, the default value 2 is selected */ + ADC_SoftTrigSoc softTrigSource; /**< Software trigger mode */ + ADC_PeriphTrigSoc periphTrigSource; /**< Peripheral trigger source selection */ + ADC_IntTrigSoc intTrigSource; /**< Internal interrupt trigger source select */ + ADC_SOCFinishMode finishMode; /**< Sample finish mode */ + unsigned int *dmaSaveAddr; /**< When DMA is used, configure destination address for data transfer */ + DMA_ChannelParam *dmaParam; /**< When DMA is used, configure DMA transmission parameters */ +} SOC_SyncParam; + +/** + * @brief The definition of extend handle structure. + */ +typedef struct _ADC_ExtendHandle { + ADC_VrefType vrefBuf; /**< ADC vrefBuf type, configuration options affected by VDDA */ +} ADC_ExtendHandle; + +/** + * @brief The definition of callback. + */ +typedef struct { + void (* Int1FinishCallBack)(void *handle); /**< ADC interrupt one complete callback function for users */ + void (* Int2FinishCallBack)(void *handle); /**< ADC interrupt two complete callback function for users */ + void (* Int3FinishCallBack)(void *handle); /**< ADC interrupt three complete callback function for users */ + void (* Int4FinishCallBack)(void *handle); /**< ADC interrupt four complete callback function for users */ + void (* DmaFinishCallBack)(void *handle); /**< ADC DMA finish callback function for users */ + void (* IntxOverCallBack)(void *handle); /**< ADC interrupt overflow callback function for users */ + void (* DmaOverCallBack)(void *handle); /**< ADC DMA overflow callback function for users */ + void (* TrigOverCallBack)(void *handle); /**< ADC trigger overflow callback function for users */ + void (* EocOverCallBack)(void *handle); /**< ADC eoc overflow callback function for users */ + void (* DmaErrorCallBack)(void *handle); /**< ADC DMA transmission error callback function for users */ +} ADC_UserCallBack; +/** + * @} + */ + +/* ADC DCL Functions */ +/** + * @brief Check ADC Operating Frequency. + * @param freq Configured frequency. + * @retval bool + */ +static inline bool IsADCWorkFreq(unsigned int freq) +{ + return (freq >= ADC_MIN_FREQ) && (freq <= ADC_MAX_FREQ); +} + +/** + * @brief Check ADC synchronous sample group parameter. + * @param group Group id of SOC. + * @retval bool + */ +static inline bool IsADCSyncGroup(ADC_SyncSampleGroup group) +{ + return (group >= ADC_SYNCSAMPLE_GROUP_1) && (group <= ADC_SYNCSAMPLE_GROUP_8); +} + +/** + * @brief Check ADC sample input. Input are classified into group A inputs and group B inputs. + * @param input Number of input. + * @retval bool + */ +static inline bool IsADCSampleChannel(ADC_Input input) +{ + return (input >= ADC_CH_ADCINA0) && (input <= ADC_CH_ADCINB7); +} + +/** + * @brief Check sample input in group A. + * @param input Number of input. + * @retval bool + */ +static inline bool IsADCGroupAChannel(ADC_Input input) +{ + return (input >= ADC_CH_ADCINA0) && (input <= ADC_CH_ADCINA7); +} + +/** + * @brief Check sample input in group B. + * @param input Number of input. + * @retval bool + */ +static inline bool IsADCGroupBChannel(ADC_Input input) +{ + return (input >= ADC_CH_ADCINB0) && (input <= ADC_CH_ADCINB7); +} + +/** + * @brief Check ADC SOC(start of conversion). Each SOC selects a unique input for sampling. The sample parameters + * are configured through the SOC. + * @param soc Number of SOC. + * @retval bool + */ +static inline bool IsADCSOCx(ADC_SOCNumber soc) +{ + return (soc >= ADC_SOC_NUM0) && (soc <= ADC_SOC_NUM15); +} + +/** + * @brief Check ADC interrupt parameter. + * @param intx Number of interrupt. + * @retval bool + */ +static inline bool IsADCIntx(ADC_IntNumber intx) +{ + return (intx >= ADC_INT_NUMBER1) && (intx <= ADC_INT_NUMBER4); +} + +/** + * @brief Check SOC interrupt trigger source. + * @param intTrig Type of interrupt trigger source. + * @retval bool + */ +static inline bool IsADCIntTrig(ADC_IntTrigSoc intTrig) +{ + return (intTrig >= ADC_TRIGSOC_NONEINT) && (intTrig <= ADC_TRIGSOC_INT3); +} + +/** + * @brief Check SOC interrupt trigger mode. + * @param intMode Type of interrupt mode. + * @retval bool + */ +static inline bool IsADCIntMode(ADC_IntMode intMode) +{ + return (intMode == ADC_INTMODE_NORMAL) || (intMode == ADC_INTMODE_EARLYINT); +} + +/** + * @brief Check SOC peripherals trigger source. + * @param periphTrig Type of peripherals trigger source. + * @retval bool + */ +static inline bool IsADCPeriphTrig(ADC_PeriphTrigSoc periphTrig) +{ + return (periphTrig >= ADC_TRIGSOC_NONEPERIPH) && (periphTrig <= ADC_TRIGSOC_GPIO); +} + +/** + * @brief Check SOC software trigger source. + * @param softTrig Type of software trigger source. + * @retval bool + */ +static inline bool IsADCSoftTrig(ADC_SoftTrigSoc softTrig) +{ + return (softTrig == ADC_TRIGSOC_NONESOFT) || (softTrig == ADC_TRIGSOC_SOFT); +} + +/** + * @brief Check SOC software trigger source. + * @param dmaType Type of software trigger source. + * @retval bool + */ +static inline bool IsADCReqDMAType(ADC_DMARequestType dmaType) +{ + return (dmaType == ADC_DMA_SINGLEREQ) || (dmaType == ADC_DMA_BURSTREQ); +} + +/** + * @brief Check mode of completion of SOC sample + * @param mode Type of completion. + * @retval bool + */ +static inline bool IsADCFinishMode(ADC_SOCFinishMode mode) +{ + return (mode >= ADC_SOCFINISH_NONE) && (mode <= ADC_SOCFINISH_INT4); +} + +/** + * @brief Check ADC sample priority parameter. + * @param mode Priority mode of SOC. + * @retval bool + */ +static inline bool IsADCPriorityMode(ADC_PriorityMode mode) +{ + return (mode >= ADC_PRIMODE_ALL_ROUND) && (mode <= ADC_PRIMODE_ALL_PRIORITY); +} + +/** + * @brief Check time of capacitor hold time after charging. + * @param shHold Priority mode of SOC. + * @retval bool + */ +static inline bool IsADCHodeTime(unsigned int shHold) +{ + return (shHold >= HOLDTIME_MIN) && (shHold <= HOLDTIME_MAX); +} + +/** + * @brief Check time of capacitor charging. + * @param acqps Time of capacitor charging. + * @retval bool + */ +static inline bool IsADCChargeTime(unsigned int acqps) +{ + return (acqps >= ACQPSTIME_MIN) && (acqps <= ACQPSTIME_MAX); +} + +/** + * @brief Check adc vrefbuf. + * @param vrefBuf Type of vrefbuf. + * @retval bool + */ +static inline bool IsADCVrefBufType(ADC_VrefType vrefBuf) +{ + return (vrefBuf == ADC_VREF_2P0V) || (vrefBuf == ADC_VREF_2P5V); +} + +/** + * @brief Check adc gain of SH0, SH1. + * @param gain Type of gain of SH0, SH1. + * @retval bool + */ +static inline bool IsADCGainType(ADC_GainType gain) +{ + return (gain >= ADC_GAIN_1) || (gain <= ADC_GAIN_0P6); +} + +/** + * @brief ADC Configuration Synchronous Sample Group. + * @param adcx ADC register base address. + * @param group Number of Synchronous sample group. + * @retval None. + */ +static inline void DCL_ADC_SetSyncSample(ADC_RegStruct * const adcx, ADC_SyncSampleGroup group) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSyncGroup(group)); + adcx->ADC_SAMPLE_MODE.reg |= (unsigned int)group; +} + +/** + * @brief ADC uses ONE-SHOT sampling mode. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_EnableOneShot(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_CTRL.BIT.one_shot = BASE_CFG_ENABLE; +} + +/** + * @brief ADC can not use ONE-SHOT sampling mode. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_DisableOneShot(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_CTRL.BIT.one_shot = BASE_CFG_DISABLE; +} + +/** + * @brief Configuring the ADC eraly interrupt offset. + * @param adcx ADC register base address. + * @param intx Number of ADC interrupt controller, @ref ADC_IntNumber. + * @param offset Offset of eraly interrupt. + * @retval None. + */ +static inline void DCL_ADC_SetIntxOffset(ADC_RegStruct * const adcx, ADC_IntNumber intx, unsigned int offset) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCIntx(intx) && (offset < 4096)); /* The upper limit of offset is 4096 */ + uintptr_t addr = (uintptr_t)(void *)adcx; + addr = (addr + 0x60 + (unsigned int)intx * 4); /* Register base address difference 4, 0x60 CTRL_REG addr */ + ADC_INT1_CTRL_REG *intReg; + intReg = (ADC_INT1_CTRL_REG *)(void *)addr; + intReg->BIT.int1_offset = offset; + intReg->BIT.int1_en = BASE_CFG_ENABLE; +} + +/** + * @brief Configure the interrupt mode: normal interrupt and early interrupt. + * @param adcx ADC register base address. + * @param intx Number of ADC interrupt controller, @ref ADC_IntNumber. + * @param mode ADC interrupt Mode. + * @retval None. + */ +static inline void DCL_ADC_SetIntxMode(ADC_RegStruct * const adcx, ADC_IntNumber intx, ADC_IntMode mode) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCIntx(intx) && IsADCIntMode(mode)); + uintptr_t addr = (uintptr_t)(void *)adcx; + addr = (addr + 0x60 + (unsigned int)intx * 4); /* Register base address difference 4, 0x60 CTRL_REG addr */ + ADC_INT1_CTRL_REG *intReg; + intReg = (ADC_INT1_CTRL_REG *)(void *)addr; + intReg->BIT.int1_pos = mode; +} + +/** + * @brief Configuring the interrupt source used by the SOC. + * @param adcx ADC register base address. + * @param intx Number of ADC interrupt controller, @ref ADC_IntNumber. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_SetSOCxBlindIntx(ADC_RegStruct * const adcx, ADC_IntNumber intx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCIntx(intx) && IsADCSOCx(socx)); + unsigned int shiftBit = (unsigned int)socx + 16; /* Offset 16 bits configuration */ + uintptr_t addr = (uintptr_t)(void *)adcx; + addr = (addr + 0x60 + (unsigned int)intx * 4); /* Register base address difference 4, 0x60 CTRL_REG addr */ + ADC_INT1_CTRL_REG *intReg; + intReg = (ADC_INT1_CTRL_REG *)(void *)addr; + intReg->reg |= (1U << shiftBit); +} + +/** + * @brief Enable ADC interrupt. + * @param adcx ADC register base address. + * @param intx Number of ADC interrupt controller, @ref ADC_IntNumber. + * @retval None. + */ +static inline void DCL_ADC_EnableIntx(ADC_RegStruct * const adcx, ADC_IntNumber intx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCIntx(intx)); + uintptr_t addr = (uintptr_t)(void *)adcx; + addr = (addr + 0x60 + (unsigned int)intx * 4); /* Register base address difference 4, 0x60 CTRL_REG addr */ + ADC_INT1_CTRL_REG *intReg; + intReg = (ADC_INT1_CTRL_REG *)(void *)addr; + intReg->BIT.int1_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable ADC interrupt. + * @param adcx ADC register base address. + * @param intx Number of ADC interrupt controller, @ref ADC_IntNumber. + * @retval None. + */ +static inline void DCL_ADC_DisableIntx(ADC_RegStruct * const adcx, ADC_IntNumber intx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCIntx(intx)); + uintptr_t addr = (uintptr_t)(void *)adcx; + addr = (addr + 0x60 + (unsigned int)intx * 4); /* Register base address difference 4, 0x60 CTRL_REG addr */ + ADC_INT1_CTRL_REG *intReg; + intReg = (ADC_INT1_CTRL_REG *)(void *)addr; + intReg->BIT.int1_en = BASE_CFG_DISABLE; +} + +/** + * @brief Obtains the interrupt state. + * @param adcx ADC register base address. + * @retval unsigned int. + */ +static inline unsigned int DCL_ADC_GetStateOfIntx(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + return adcx->ADC_INT_FLAG.reg; +} + +/** + * @brief ADC clear interruption. + * @param adcx ADC register base address. + * @param intx Number of ADC interrupt controller, @ref ADC_IntNumber. + * @retval None. + */ +static inline void DCL_ADC_ClearIntx(ADC_RegStruct * const adcx, ADC_IntNumber intx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCIntx(intx)); + adcx->ADC_INT_FLAG.reg = (1U << (unsigned int)intx); +} + +/** + * @brief Enable ADC interrupt pulse. + * @param adcx ADC register base address. + * @param intx Number of ADC interrupt controller, @ref ADC_IntNumber. + * @retval None. + */ +static inline void DCL_ADC_EnableIntxPulse(ADC_RegStruct * const adcx, ADC_IntNumber intx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCIntx(intx)); + uintptr_t addr = (uintptr_t)(void *)adcx; + addr = (addr + 0x60 + (unsigned int)intx * 4); /* Register base address difference 4, 0x60 CTRL_REG addr */ + ADC_INT1_CTRL_REG *intReg; + intReg = (ADC_INT1_CTRL_REG *)(void *)addr; + intReg->BIT.int1_cont = BASE_CFG_ENABLE; +} + +/** + * @brief Disable ADC interrupt pulse. + * @param adcx ADC register base address. + * @param intx Number of ADC interrupt controller, @ref ADC_IntNumber. + * @retval None. + */ +static inline void DCL_ADC_DisableIntxPulse(ADC_RegStruct * const adcx, ADC_IntNumber intx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCIntx(intx)); + uintptr_t addr = (uintptr_t)(void *)adcx; + addr = (addr + 0x60 + (unsigned int)intx * 4); /* Register base address difference 4, 0x60 CTRL_REG addr */ + ADC_INT1_CTRL_REG *intReg; + intReg = (ADC_INT1_CTRL_REG *)(void *)addr; + intReg->BIT.int1_cont = BASE_CFG_DISABLE; +} +/** + * @brief Calculate the base address of the SOC registers with different numbers.This interface is invoked by the DCL, + * and parameter verification has been completed at the DCL functions. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval addr, the base address of the SOC registers. + */ +static unsigned int ADC_GetCTRLAddr(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + unsigned int addr; + if (socx == ADC_SOC_NUM15) { + addr = (uintptr_t)(void *)&(adcx->ADC_SOC15_CTRL); + } else { + addr = (uintptr_t)(void *)&(adcx->ADC_SOC0_CTRL); + addr += ((unsigned int)socx * 4); /* Register base address difference 4 */ + } + return addr; +} + +/** + * @brief Configure the corresponding input for the SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @param input ADC input, @ref ADC_Input. + * @retval None. + */ +static inline void DCL_ADC_SOCxSelectChannel(ADC_RegStruct * const adcx, ADC_SOCNumber socx, ADC_Input input) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx) && IsADCSampleChannel(input)); + ADC_SOC0_CTRL_REG *soc = NULL; + unsigned int addr = ADC_GetCTRLAddr(adcx, socx); /* get the Address After Translation */ + soc = (ADC_SOC0_CTRL_REG *)(void *)(uintptr_t)addr; + soc->reg &= 0xFFFFFFF0; + soc->reg |= (unsigned int)input; +} + +/** + * @brief Configure the trigger source for the SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @param trig Source of trigger, @ref ADC_PeriphTrigSoc. + * @retval None. + */ +static inline void DCL_ADC_SOCxSelcetTrigSource(ADC_RegStruct * const adcx, ADC_SOCNumber socx, ADC_PeriphTrigSoc trig) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx) && IsADCPeriphTrig(trig)); + unsigned int addr = ADC_GetCTRLAddr(adcx, socx); + ADC_SOC0_CTRL_REG *soc = NULL; + soc = (ADC_SOC0_CTRL_REG *)(void *)(uintptr_t)addr; + soc->reg &= 0xFFFFFE0F; + soc->reg |= ((unsigned int)trig << 4); /* Registers 4 through 8 bit to configure the SOC trigger source */ +} + +/** + * @brief Configure the feedback interrupt for the SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @param Intxtrig Source of trigger, @ref ADC_IntTrigSoc. + * @retval None. + */ +static inline void DCL_ADC_SOCxSelcetIntxTrig(ADC_RegStruct * const adcx, ADC_SOCNumber socx, ADC_IntTrigSoc Intxtrig) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx) && IsADCIntTrig(Intxtrig)); + unsigned int addr = ADC_GetCTRLAddr(adcx, socx); + ADC_SOC0_CTRL_REG *soc = NULL; + soc = (ADC_SOC0_CTRL_REG *)(void *)(uintptr_t)addr; + soc->reg &= 0xFFFFF9FF; + soc->reg |= ((unsigned int)Intxtrig << 9); /* Shift left 9 bit to configure the SOC interrupt trigger source */ +} + +/** + * @brief Configure the capacitor charging time for the SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @param acqps Capacitor charging time. + * @retval None. + */ +static inline void DCL_ADC_SOCxSetAcqps(ADC_RegStruct * const adcx, ADC_SOCNumber socx, unsigned int acqps) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + ADC_PARAM_CHECK_NO_RET(acqps >= 3 && acqps <= 127); /* The value of acqps ranges from 3 to 127 */ + unsigned int addr = ADC_GetCTRLAddr(adcx, socx); + ADC_SOC0_CTRL_REG *soc = NULL; + soc = (ADC_SOC0_CTRL_REG *)(void *)(uintptr_t)addr; + soc->reg &= 0xFFFC07FF; + soc->reg |= (acqps << 11); /* Registers 11 bit to configure the capacitor charging time */ +} + +/** + * @brief Configure the capacitor hold time for the SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @param shHold Charge hold time. + * @retval None. + */ +static inline void DCL_ADC_SOCxSetShHold(ADC_RegStruct * const adcx, ADC_SOCNumber socx, unsigned int shHold) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + ADC_PARAM_CHECK_NO_RET(shHold >= 2 && shHold <= 28); /* The value of shHold ranges from 2 to 28 */ + unsigned int addr = ADC_GetCTRLAddr(adcx, socx); + ADC_SOC0_CTRL_REG *soc = NULL; + soc = (ADC_SOC0_CTRL_REG *)(void *)(uintptr_t)addr; + soc->reg &= 0xFC0FFFFF; + soc->reg |= (shHold << 20); /* Registers 20 bit to configure the capacitor charge hold time */ +} + +/** + * @brief Enables the read-clear function of the result register for SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_SOCxEnableRC(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + ADC_SOC0_CTRL_REG *soc = NULL; + unsigned int addr = ADC_GetCTRLAddr(adcx, socx); /* get the Address After Translation */ + soc = (ADC_SOC0_CTRL_REG *)(void *)(uintptr_t)addr; + soc->BIT.soc0_rslt_rclr = BASE_CFG_ENABLE; +} + +/** + * @brief Disable the read-clear function of the result register for SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_SOCxDisableRC(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + unsigned int addr = ADC_GetCTRLAddr(adcx, socx); /* get the Address After Translation */ + ADC_SOC0_CTRL_REG *soc = NULL; + soc = (ADC_SOC0_CTRL_REG *)(void *)(uintptr_t)addr; + soc->BIT.soc0_rslt_rclr = BASE_CFG_DISABLE; +} + +/** + * @brief ADC uses software-triggered sampling. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_SOCxSoftTrigger(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + adcx->ADC_SOFT_TRIG.reg |= (1U << (unsigned int)socx); +} + +/** + * @brief Multiple inputs trigger software sampling. + * @param adcx ADC register base address. + * @param val The val bits range from 0 to 0xFFFF. Writing 1 indicates triggering. + * @retval None. + */ +static inline void DCL_ADC_SOCxMultiSoftTrigger(ADC_RegStruct * const adcx, unsigned int val) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(val <= 0xFFFF); /* The value of val ranges from 0 to 0xFFFF */ + adcx->ADC_SOFT_TRIG.reg = val; +} + +/** + * @brief Configuring the SOC Priority. + * @param adcx ADC register base address. + * @param priorityMode Mode of SOC priority, @ref ADC_PriorityMode. + * @retval None. + */ +static inline void DCL_ADC_SOCxSetPriority(ADC_RegStruct * const adcx, ADC_PriorityMode priorityMode) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCPriorityMode(priorityMode)); + adcx->ADC_SOC_PRICTL.reg = priorityMode; +} + +/** + * @brief Get current poll pointer. This pointer holds the last converted poll SOC. + * @param adcx ADC register base address. + * @retval None. + */ +static inline unsigned int DCL_ADC_QueryPollPoint(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + return adcx->ADC_STATUS.BIT.rr_pointer; +} + +/** + * @brief The poll pointer is reset by software. After the software is set to 1, the rr_pointer is set to 16. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_ResetPollPoint(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_SOC_PRICTL_SET.BIT.rr_set = BASE_CFG_SET; +} + + +/** + * @brief Set the specified SOC as the DAM request trigger source. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_DMARequestSource(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + adcx->ADC_INT_OFFSET.BIT.dma_int_sel = socx; +} + +/** + * @brief ADC enable DMA burst request. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_EnableDMABurstReq(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_INT_OFFSET.BIT.dma_brst_req_sel = BASE_CFG_ENABLE; +} + +/** + * @brief ADC disable DMA burst request. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_DisableDMABurstReq(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_INT_OFFSET.BIT.dma_brst_req_sel = BASE_CFG_DISABLE; +} + +/** + * @brief ADC enable DMA single request. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_EnableDMASingleReq(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_INT_OFFSET.BIT.dma_sing_req_sel = BASE_CFG_ENABLE; +} + +/** + * @brief ADC disable DMA single request. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_DisableDMASingleReq(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_INT_OFFSET.BIT.dma_sing_req_sel = BASE_CFG_DISABLE; +} + +/** + * @brief Configure post processing module(PPB) for the SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_SOCxSelectPPB0(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + adcx->ADC_PPB0_CTRL.reg |= (unsigned int)socx; +} + +/** + * @brief Configure post processing module(PPB) for the SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_SOCxSelectPPB1(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + adcx->ADC_PPB1_CTRL.reg |= (unsigned int)socx; +} + +/** + * @brief Configure post processing module(PPB) for the SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_SOCxSelectPPB2(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + adcx->ADC_PPB2_CTRL.reg |= (unsigned int)socx; +} + +/** + * @brief Configure post processing module(PPB) for the SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_SOCxSelectPPB3(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_NO_RET(IsADCSOCx(socx)); + adcx->ADC_PPB3_CTRL.reg |= (unsigned int)socx; +} + +/** + * @brief Enable specified PPB. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_EnablePPB0(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_PPB0_CTRL.BIT.ppb0_en = BASE_CFG_ENABLE; +} + +/** + * @brief Enable specified PPB. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_EnablePPB1(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_PPB1_CTRL.BIT.ppb1_en = BASE_CFG_ENABLE; +} + +/** + * @brief Enable specified PPB. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_EnablePPB2(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_PPB2_CTRL.BIT.ppb2_en = BASE_CFG_ENABLE; +} + +/** + * @brief Enable specified PPB. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_EnablePPB3(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_PPB3_CTRL.BIT.ppb3_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable specified PPB. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_DisablePPB0(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_PPB0_CTRL.BIT.ppb0_en = BASE_CFG_DISABLE; +} + +/** + * @brief Disable specified PPB. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_DisablePPB1(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_PPB1_CTRL.BIT.ppb1_en = BASE_CFG_DISABLE; +} + +/** + * @brief Disable specified PPB. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_DisablePPB2(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_PPB2_CTRL.BIT.ppb2_en = BASE_CFG_DISABLE; +} + +/** + * @brief Disable specified PPB. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_DisablePPB3(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_PPB3_CTRL.BIT.ppb3_en = BASE_CFG_DISABLE; +} + +/** + * @brief Read ADC conversion result. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline unsigned int DCL_ADC_ReadSOCxResult(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_ASSERT_PARAM(IsADCSOCx(socx) == true); + ADC_RESULT0_REG *result; + uintptr_t addr = (uintptr_t)(void *)adcx; + /* The address interval of the result register is 4 */ + result = (ADC_RESULT0_REG *)(void *)(addr + 4 * (unsigned int)socx); + if (g_trimEnable == false) { + return result->reg; + } + return HAL_ADC_ActiveCalibrateRetEx(adcx, socx, result->reg); +} + +/** + * @brief Setting vrefbuf Parameters. + * @param vrefBuf Type of verfbuf, @ref ADC_VrefType. + * @retval None. + */ +static inline void DCL_ADC0_SetVrefBuf(ADC_VrefType vrefBuf) +{ + ADC_ASSERT_PARAM(IsADCVrefBufType(vrefBuf)); + unsigned int val = BASE_CFG_ENABLE; + val |= ((unsigned int)vrefBuf << 4); /* Shift left 4 bit to configurate the type of vrefbuf */ + SYSCTRL1->ADC0_VREF_CTRL.reg |= val; +} + +/** + * @brief Setting vrefbuf Parameters. + * @param vrefBuf Type of verfbuf, @ref ADC_VrefType. + * @retval None. + */ +static inline void DCL_ADC1_SetVrefBuf(ADC_VrefType vrefBuf) +{ + ADC_ASSERT_PARAM(IsADCVrefBufType(vrefBuf)); + unsigned int val = BASE_CFG_ENABLE; + val |= ((unsigned int)vrefBuf << 4); /* Shift left 4 bit to configurate the type of vrefbuf */ + SYSCTRL1->ADC1_VREF_CTRL.reg |= val; +} + +/** + * @brief Setting vrefbuf Parameters. + * @param vrefBuf Type of verfbuf, @ref ADC_VrefType. + * @retval None. + */ +static inline void DCL_ADC2_SetVrefBuf(ADC_VrefType vrefBuf) +{ + ADC_ASSERT_PARAM(IsADCVrefBufType(vrefBuf)); + unsigned int val = BASE_CFG_ENABLE; + val |= ((unsigned int)vrefBuf << 4); /* Shift left 4 bit to configurate the type of vrefbuf */ + SYSCTRL1->ADC2_VREF_CTRL.reg |= val; +} + +/** + * @brief Analog Power Enable. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_PowerEnable(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_ANA_PD.BIT.adc_pwdnz = BASE_CFG_ENABLE; +} + +/** + * @brief Analog Power Disable. + * @param adcx ADC register base address. + * @retval None. + */ +static inline void DCL_ADC_PowerDisable(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_ANA_PD.BIT.adc_pwdnz = BASE_CFG_DISABLE; +} + +/** + * @brief Obtain the SOC conversion status. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval unsigned int, Not 0: Finish, 0: Not finish. + */ +static inline unsigned int DCL_ADC_GetConvState(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_ASSERT_PARAM(IsADCSOCx(socx) == true); + unsigned int ret = adcx->ADC_EOC_FLAG.reg; + return (ret & ((1U << (unsigned int)socx))); +} + +/** + * @brief Clears the SOC completion flag. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval None. + */ +static inline void DCL_ADC_ResetConvState(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_ASSERT_PARAM(IsADCSOCx(socx) == true); + unsigned int ret = (1U << (unsigned int)socx); + adcx->ADC_EOC_FLAG.reg = ret; +} + +/** + * @brief Obtains the input ID currently configured for the SOC. + * @param adcx ADC register base address. + * @param socx Number of SOC, @ref ADC_SOCNumber. + * @retval unisgned int, input number of soc. + */ +static inline unsigned int DCL_ADC_GetSOCxInputChannel(ADC_RegStruct * const adcx, ADC_SOCNumber socx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_ASSERT_PARAM(IsADCSOCx(socx) == true); + unsigned int addr = ADC_GetCTRLAddr(adcx, socx); /* Obtains the SOC base address */ + ADC_SOC0_CTRL_REG *soc = NULL; + soc = (ADC_SOC0_CTRL_REG *)(void *)(uintptr_t)addr; + return soc->BIT.soc0_chsel; +} + +/** + * @brief Setting the gain of SH0. + * @param adcx ADC register base address. + * @param gain Type of gain, @ref ADC_GainType. + * @retval None. + */ +static inline void DCL_ADC_SetGainOfSampleHold0(ADC_RegStruct * const adcx, ADC_GainType gain) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_ASSERT_PARAM(IsADCGainType(gain) == true); + adcx->ADC_ANA_CTRL.BIT.adc_ana_gsh0 = gain; +} + +/** + * @brief Setting the gain of SH1. + * @param adcx ADC register base address. + * @param gain Type of gain, @ref ADC_GainType. + * @retval None. + */ +static inline void DCL_ADC_SetGainOfSampleHold1(ADC_RegStruct * const adcx, ADC_GainType gain) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_ASSERT_PARAM(IsADCGainType(gain) == true); + adcx->ADC_ANA_CTRL.BIT.adc_ana_gsh1 = gain; +} + +/** + * @brief Obtains the gain of SH0. + * @param adcx ADC register base address. + * @retval unsigned int, gain of SH0. + */ +static inline unsigned int DCL_ADC_GetGainOfSampleHold0(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + return adcx->ADC_ANA_CTRL.BIT.adc_ana_gsh0; +} + +/** + * @brief Obtains the gain of SH1. + * @param adcx ADC register base address. + * @retval unsigned int, gain of SH1. + */ +static inline unsigned int DCL_ADC_GetGainOfSampleHold1(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + return adcx->ADC_ANA_CTRL.BIT.adc_ana_gsh1; +} + +/** + * @brief Enter ADC Calibration Mode. + * @param adcx ADC register base address. + * @retval void. + */ +static inline void DCL_ADC_EnterCalibrationMode(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_CTRL.BIT.adc_cal_en = 0x01; + adcx->ADC_CTRL.BIT.adc_cal_mode = 0x01; + adcx->ADC_ANA_CTRL.BIT.ana_logic_mode = 0x01; +} + +/** + * @brief Enter ADC Work Mode. + * @param adcx ADC register base address. + * @retval void. + */ +static inline void DCL_ADC_EnterWorkMode(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_CTRL.BIT.adc_cal_en = 0x00; + adcx->ADC_CTRL.BIT.adc_cal_mode = 0x00; + adcx->ADC_ANA_CTRL.BIT.ana_logic_mode = 0x00; +} + +/** + * @brief Configure the calibration capacitor and weight and enable calibration. + * @param adcx ADC register base address. + * @retval void. + */ +static inline void DCL_ADC_StartCalibrationMode(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + adcx->ADC_CAP_CALI0.BIT.adc_weight_ini_sel = 0x01; /* Select AutoCalibration Weight Value */ + adcx->ADC_SAR_CTRL0.BIT.cap_start_index = 0xF; /* Select Calibration Capacitor */ + adcx->ADC_SAR_CTRL3.BIT.cap_start = 0x01; /* Select Calibration Capacitor */ +} + +/** + * @brief Clear the interrupt overflow flag. + * @param adcx ADC register base address. + * @retval void. + */ +static inline void DCL_ADC_ClearIntOver(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + unsigned int intOver = adcx->ADC_INT_OVFL.reg; + adcx->ADC_INT_OVFL.reg = intOver; +} + +/** + * @brief Clear the EOC overflow flag. + * @param adcx ADC register base address. + * @retval void. + */ +static inline void DCL_ADC_ClearEocOver(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + unsigned int eocOver = adcx->ADC_EOC_OVFL.reg; + adcx->ADC_EOC_OVFL.reg = eocOver; +} + +/** + * @brief Clear the trigger overflow flag. + * @param adcx ADC register base address. + * @retval void. + */ +static inline void DCL_ADC_ClearTrigOver(ADC_RegStruct * const adcx) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + unsigned int trigOver = adcx->ADC_TRIG_OVFL.reg; + adcx->ADC_TRIG_OVFL.reg = trigOver; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_ADC_IP_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/adc/src/adc.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/adc/src/adc.c new file mode 100644 index 00000000..17f27024 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/adc/src/adc.c @@ -0,0 +1,669 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file adc.c + * @author MCU Driver Team + * @brief ADC module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the ADC. + * + ADC initialization function. + * + Start ADC sample and conversion. + * + Start ADC sample and conversion with interrupt. + * + Start ADC sample and conversion with DMA. + * + Start ADC sample and conversion synchronously. + * + Query the ADC conversion result. + * + Single and multichannel software trigger functions. + * + Interrupt callback function and user registration function. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "crg.h" +#include "adcinit.h" +#include "adc.h" + +static void ADC_CapCalibrationMode(ADC_Handle *adcHandle); +void HAL_ADC_IrqHandlerInt4(void *handle); +/** + * @brief Configuring ADC vref parameters. + * @param adcHandle ADC handle. + * @param vrefBuf type of adc vrefBuf. + * @retval None. + */ +static void ADC_SetVrefBuf(ADC_Handle *adcHandle, unsigned int vrefBuf) +{ + unsigned int val; + if (vrefBuf == ADC_VREF_2P0V) { + val = 0x1; /* vrefbuf is 2.0v */ + } else { + val = 0x11; /* vrefbuf is 2.5v */ + } + if (adcHandle->baseAddress == ADC0) { + SYSCTRL1->ADC0_VREF_CTRL.reg |= val; + } else if (adcHandle->baseAddress == ADC1) { + SYSCTRL1->ADC1_VREF_CTRL.reg |= val; + } else if (adcHandle->baseAddress == ADC2) { + SYSCTRL1->ADC2_VREF_CTRL.reg |= val; + } +} + +/** + * @brief ADC Capacitor Calibration Mode1. + * @param None. + * @retval None. + */ +static void ADC_CapCalibrationMode(ADC_Handle *adcHandle) +{ + adcHandle->baseAddress->ADC_CTRL.BIT.adc_cal_en = 0x01; + adcHandle->baseAddress->ADC_CTRL.BIT.adc_cal_mode = 0x01; /* Enter Capacitance Calibration Mode 1 */ + adcHandle->baseAddress->ADC_ANA_CTRL.BIT.ana_logic_mode = 0x01; + adcHandle->baseAddress->ADC_CAP_CALI0.BIT.adc_weight_ini_sel = 0x01; + adcHandle->baseAddress->ADC_SAR_CTRL0.BIT.cap_start_index = 0xF; + adcHandle->baseAddress->ADC_SAR_CTRL3.BIT.cap_start = 0x01; + BASE_FUNC_DELAY_US(270); /* wait 270us */ + adcHandle->baseAddress->ADC_CTRL.BIT.adc_cal_en = 0x0; + adcHandle->baseAddress->ADC_CTRL.BIT.adc_cal_mode = 0x0; /* Enter the working mode */ + adcHandle->baseAddress->ADC_ANA_CTRL.BIT.ana_logic_mode = 0x0; +} + +/** + * @brief Set User vref Configuration. + * @param adcHandle ADC handle. + * @retval None. + */ +static void ADC_SetUserVref(ADC_Handle *adcHandle) +{ + ADC_SetVrefBuf(adcHandle, (unsigned int)adcHandle->handleEx.vrefBuf); + unsigned int val = 0x00; + if (adcHandle->handleEx.vrefBuf == ADC_VREF_2P0V) { + val = 0x02; /* 0x02: gian = 0.6 */ + } else if (adcHandle->handleEx.vrefBuf == ADC_VREF_2P5V) { + val = 0x01; /* 0x01: gian = 0.75 */ + } + adcHandle->baseAddress->ADC_ANA_CTRL.BIT.adc_ana_gsh0 = val; + adcHandle->baseAddress->ADC_ANA_CTRL.BIT.adc_ana_gsh1 = val; +} + +/** + * @brief Initialize the ADC hardware controller. + * @param adcHandle ADC handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_ADC_Init(ADC_Handle *adcHandle) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_ASSERT_PARAM(IsADCWorkFreq(HAL_CRG_GetIpFreq((const void *)adcHandle->baseAddress))); + ADC_PARAM_CHECK_WITH_RET(IsADCPriorityMode(adcHandle->socPriority) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCVrefBufType(adcHandle->handleEx.vrefBuf) == true, BASE_STATUS_ERROR); + adcHandle->baseAddress->ADC_ANA_PD.BIT.adc_pwdnz = BASE_CFG_ENABLE; + BASE_FUNC_DELAY_US(10); /* wait 10us */ + ADC_SetUserVref(adcHandle); + /* ADC Calibration */ + if (g_versionId != 0xFF && g_versionId != 0) { + ADC_CapCalibrationMode(adcHandle); + } + DCL_ADC_SOCxSetPriority(adcHandle->baseAddress, adcHandle->socPriority); + return BASE_STATUS_OK; +} + +/** + * @brief DeInitialize the ADC hardware controller. + * @param adcHandle ADC handle. + * @retval BASE status type: OK. + */ +BASE_StatusType HAL_ADC_Deinit(ADC_Handle *adcHandle) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + adcHandle->baseAddress->ADC_ANA_PD.BIT.adc_pwdnz = BASE_CFG_DISABLE; + return BASE_STATUS_OK; +} + +/** + * @brief configurating the specified SOC parameters. + * @param adcHandle ADC handle. + * @param soc ID of SOC(start of conversion), managing the specific sample inputs. + * @param socParam Param struct of SOC. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_ADC_ConfigureSoc(ADC_Handle *adcHandle, ADC_SOCNumber soc, SOC_Param *socParam) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + ADC_ASSERT_PARAM(socParam != NULL); + ADC_PARAM_CHECK_WITH_RET(IsADCSampleChannel(socParam->adcInput) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCChargeTime(socParam->sampleTotalTime) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCHodeTime(socParam->sampleHoldTime) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCSoftTrig(socParam->softTrigSource) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCPeriphTrig(socParam->periphTrigSource) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCIntTrig(socParam->intTrigSource) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCFinishMode(socParam->finishMode) == true, BASE_STATUS_ERROR); + DCL_ADC_SOCxSelectChannel(adcHandle->baseAddress, soc, socParam->adcInput); + DCL_ADC_SOCxSetAcqps(adcHandle->baseAddress, soc, socParam->sampleTotalTime); + DCL_ADC_SOCxSetShHold(adcHandle->baseAddress, soc, socParam->sampleHoldTime); + DCL_ADC_SOCxSelcetIntxTrig(adcHandle->baseAddress, soc, socParam->intTrigSource); + DCL_ADC_SOCxSelcetTrigSource(adcHandle->baseAddress, soc, socParam->periphTrigSource); + adcHandle->ADC_SOCxParam[soc].finishMode = socParam->finishMode; + return BASE_STATUS_OK; +} + +/** + * @brief Callback function that ADC completes the sample conversion and uses the DMA to complete the transmission. + * @param handle ADC handle. + * @retval None. + */ +static void ADC_DMATransFinish(void *handle) +{ + ADC_ASSERT_PARAM(handle != NULL); + ADC_Handle *adcHandle = (ADC_Handle *)(handle); + if (adcHandle->userCallBack.DmaFinishCallBack != NULL) { + adcHandle->userCallBack.DmaFinishCallBack(adcHandle); + } + return; +} + +/** + * @brief Callback function that ADC falis to use DMA. + * @param handle ADC handle. + * @retval None. + */ +static void ADC_DMATransError(void *handle) +{ + ADC_ASSERT_PARAM(handle != NULL); + ADC_Handle *adcHandle = (ADC_Handle *)(handle); + if (adcHandle->userCallBack.DmaErrorCallBack != NULL) { + adcHandle->userCallBack.DmaErrorCallBack(adcHandle); + } + return; +} + +/** + * @brief Start the ADC conversion and enable ADC DMA. After the SOC conversion using the DMA is complete, use the DMA + * to transfer data The DMA can transfer the sampling results of consecutive SOCs. The start and end of DMA transfer + * are determined by startSoc and endSoc. + * @param adcHandle ADC handle. + * @param startSoc First SOC result for DMA transfer. + * @param endSoc Last SOC result for DMA transfer. + * @param saveData Address where the converted result is saved. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_ADC_StartDma(ADC_Handle *adcHandle, unsigned int startSoc, + unsigned int endSoc, unsigned int *saveData) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(startSoc) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(endSoc) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(startSoc <= endSoc, BASE_STATUS_ERROR); + ADC_ASSERT_PARAM(saveData != NULL); + ADC_ASSERT_PARAM(adcHandle->dmaHandle != NULL); + ADC_PARAM_CHECK_WITH_RET(IsDmaChannelNum(adcHandle->adcDmaChn) == true, BASE_STATUS_ERROR); + unsigned int dmaSOCx = 0; + unsigned int dataLength = endSoc - startSoc + 1; + for (int i = 0; i < SOC_MAX_NUM; i++) { + if (adcHandle->ADC_SOCxParam[i].finishMode == ADC_SOCFINISH_DMA) { + dmaSOCx = i; + } + } + + DCL_ADC_DMARequestSource(adcHandle->baseAddress, dmaSOCx); + DCL_ADC_EnableDMABurstReq(adcHandle->baseAddress); + DCL_ADC_EnableDMASingleReq(adcHandle->baseAddress); + uintptr_t srcAddr = (uintptr_t)(void *)(adcHandle->baseAddress); + srcAddr = srcAddr + 4 * startSoc; /* The base address difference of adjacent SOC result registers is 4 */ + adcHandle->dmaHandle->userCallBack.DMA_CallbackFuns[adcHandle->adcDmaChn].ChannelFinishCallBack = + ADC_DMATransFinish; + adcHandle->dmaHandle->userCallBack.DMA_CallbackFuns[adcHandle->adcDmaChn].ChannelErrorCallBack = ADC_DMATransError; + HAL_DMA_StartIT(adcHandle->dmaHandle, srcAddr, (uintptr_t)(void *)(saveData), dataLength, adcHandle->adcDmaChn); + return BASE_STATUS_OK; +} + +/** + * @brief Start the ADC conversion and enable ADC interrupt. After the SOC completes sample conversion, the ADC + * interrupt is reported. + * @param adcHandle ADC handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_ADC_StartIt(ADC_Handle *adcHandle) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + unsigned int intVal = 0; + for (int i = 0; i < SOC_MAX_NUM; i++) { + intVal = adcHandle->ADC_SOCxParam[i].finishMode; + switch (intVal) { + case ADC_SOCFINISH_INT1: + DCL_ADC_SetSOCxBlindIntx(adcHandle->baseAddress, ADC_INT_NUMBER1, i); + break; + case ADC_SOCFINISH_INT2: + DCL_ADC_SetSOCxBlindIntx(adcHandle->baseAddress, ADC_INT_NUMBER2, i); + break; + case ADC_SOCFINISH_INT3: + DCL_ADC_SetSOCxBlindIntx(adcHandle->baseAddress, ADC_INT_NUMBER3, i); + break; + case ADC_SOCFINISH_INT4: + DCL_ADC_SetSOCxBlindIntx(adcHandle->baseAddress, ADC_INT_NUMBER4, i); + break; + default: + break; + } + } + DCL_ADC_EnableIntx(adcHandle->baseAddress, ADC_INT_NUMBER1); + DCL_ADC_EnableIntx(adcHandle->baseAddress, ADC_INT_NUMBER2); + DCL_ADC_EnableIntx(adcHandle->baseAddress, ADC_INT_NUMBER3); + DCL_ADC_EnableIntx(adcHandle->baseAddress, ADC_INT_NUMBER4); + return BASE_STATUS_OK; +} + +/** + * @brief The software triggers multiple SCOs for sampling at the same time. + * @param adcHandle ADC handle. + * @param syncTrig Triggering Parameters. The lower 16 bits correspond to one SOC. If this bit is set to 1, the + * software triggers the SOC. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_ADC_SoftTrigMultiSample(ADC_Handle *adcHandle, ADC_SoftMultiTrig syncTrig) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + unsigned int val = syncTrig.softTrigVal; + ADC_PARAM_CHECK_WITH_RET(val <= 0xFFFF, BASE_STATUS_ERROR); + DCL_ADC_SOCxMultiSoftTrigger(adcHandle->baseAddress, val); + return BASE_STATUS_OK; +} + +/** + * @brief The software triggers only one soc. + * @param adcHandle ADC handle. + * @param soc ID of SOC. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_ADC_SoftTrigSample(ADC_Handle *adcHandle, unsigned int soc) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + DCL_ADC_SOCxSoftTrigger(adcHandle->baseAddress, soc); + return BASE_STATUS_OK; +} + +/** + * @brief Obtains the sample result after SOC conversion. + * @param adcHandle ADC handle. + * @param soc ID of SOC. + * @retval unsigned int value of ADC convert result. + */ +unsigned int HAL_ADC_GetConvResult(ADC_Handle *adcHandle, unsigned int soc) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + return DCL_ADC_ReadSOCxResult(adcHandle->baseAddress, soc); +} + + +/** + * @brief Check the SOC completion flag. + * @param adcHandle ADC handle. + * @param soc ID of SOC. + * @retval BASE_STATUS_ERROR: The SOC does not complete the data sampling conversion. + * @retval BASE_STATUS_OK: The SOC has completed data sampling conversion. + */ +BASE_StatusType HAL_ADC_CheckSocFinish(ADC_Handle *adcHandle, unsigned int soc) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + if (DCL_ADC_GetConvState(adcHandle->baseAddress, soc) == 0) { + return BASE_STATUS_ERROR; /* The SOC does not complete the conversion */ + } + DCL_ADC_ResetConvState(adcHandle->baseAddress, soc); /* Clear flag bit */ + return BASE_STATUS_OK; +} + +/** + * @brief The ADC completes the interrupt processing. + * @param adcHandle ADC handle. + * @param intx ADC interrupt type number @ref ADC_IntNumber. + * @retval None. + */ +static void ADC_IntxClearEoc(ADC_Handle *adcHandle, unsigned int intx) +{ + unsigned int eocFlag = adcHandle->baseAddress->ADC_EOC_FLAG.reg; + ADC_INT1_CTRL_REG int1Ctrl; + ADC_INT2_CTRL_REG int2Ctrl; + ADC_INT3_CTRL_REG int3Ctrl; + ADC_INT4_CTRL_REG int4Ctrl; + unsigned int eocMask = 0; + switch (intx) { + case ADC_INT_NUMBER1: /* Read the configuration of interrupt 1 */ + int1Ctrl.reg = adcHandle->baseAddress->ADC_INT1_CTRL.reg; + eocMask = int1Ctrl.BIT.int1_eoc_en; + break; + case ADC_INT_NUMBER2: /* Read the configuration of interrupt 2 */ + int2Ctrl.reg = adcHandle->baseAddress->ADC_INT2_CTRL.reg; + eocMask = int2Ctrl.BIT.int2_eoc_en; + break; + case ADC_INT_NUMBER3: /* Read the configuration of interrupt 3 */ + int3Ctrl.reg = adcHandle->baseAddress->ADC_INT3_CTRL.reg; + eocMask = int3Ctrl.BIT.int3_eoc_en; + break; + case ADC_INT_NUMBER4: /* Read the configuration of interrupt 4 */ + int4Ctrl.reg = adcHandle->baseAddress->ADC_INT4_CTRL.reg; + eocMask = int4Ctrl.BIT.int4_eoc_en; + break; + default: + break; + } + unsigned int eoc = eocFlag & eocMask; /* Record the interrupt status */ + adcHandle->ADC_IntxParam[intx].socxFinish = eoc; + for (int i = 0; i < SOC_MAX_NUM; i++) { + unsigned int val = (1 << i); + if (eoc & val) { + adcHandle->baseAddress->ADC_EOC_FLAG.reg = val; /* Clear the EOC flag */ + } + } +} + +/** + * @brief Processing the overflow callback function. + * @param adcHandle ADC handle. + * @param eocOver ADC eoc overflow status. + * @param intOver ADC trigger overflow status. + * @param trigOver ADC interrupt overflow status. + * @retval None. + */ +static void ADC_OverflowCallBack(ADC_Handle *adcHandle, unsigned int eocOver, unsigned int intOver, + unsigned int trigOver) +{ + if ((eocOver) != 0 && adcHandle->userCallBack.EocOverCallBack != NULL) { + adcHandle->userCallBack.EocOverCallBack(adcHandle); /* eoc overflow callback */ + } + if ((intOver & INT_OVER_MASK) != 0 && adcHandle->userCallBack.IntxOverCallBack != NULL) { + adcHandle->userCallBack.IntxOverCallBack(adcHandle); /* interrupt overflow callback */ + } + if ((intOver & DMA_OVER_MASK) != 0 && adcHandle->userCallBack.DmaOverCallBack != NULL) { + adcHandle->userCallBack.DmaOverCallBack(adcHandle); /* dma overflow callback */ + } + if ((trigOver) != 0 && adcHandle->userCallBack.TrigOverCallBack != NULL) { + adcHandle->userCallBack.TrigOverCallBack(adcHandle); /* trigger overflow callback */ + } +} + +/** + * @brief The ADC overflow interrupt processing + * @param handle ADC handle. + * @retval None. + */ +void HAL_ADC_IrqHandlerOver(void *handle) +{ + ADC_ASSERT_PARAM(handle != NULL); + ADC_Handle *adcHandle = (ADC_Handle *)handle; + unsigned int eocOver = adcHandle->baseAddress->ADC_EOC_OVFL.reg; + unsigned int intOver = adcHandle->baseAddress->ADC_INT_OVFL.reg; + unsigned int trigOver = adcHandle->baseAddress->ADC_TRIG_OVFL.reg; + adcHandle->overState.eocOver = eocOver; /* Save the eoc overflow status */ + adcHandle->overState.trigOver = trigOver; /* Save the trigger overflow status */ + adcHandle->overState.intOver = intOver; /* Save the interrupt overflow status */ + DCL_ADC_ClearEocOver(adcHandle->baseAddress); + DCL_ADC_ClearIntOver(adcHandle->baseAddress); + DCL_ADC_ClearTrigOver(adcHandle->baseAddress); + /* overflow callback function */ + ADC_OverflowCallBack(adcHandle, eocOver, intOver, trigOver); +} + +/** + * @brief ADC Interrupt1 service processing function. + * @param handle ADC handle. + * @retval None. + */ +void HAL_ADC_IrqHandlerInt1(void *handle) +{ + ADC_ASSERT_PARAM(handle != NULL); + ADC_Handle *adcHandle = (ADC_Handle *)handle; + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_IntxClearEoc(adcHandle, ADC_INT_NUMBER1); + DCL_ADC_ClearIntx(adcHandle->baseAddress, ADC_INT_NUMBER1); + if (adcHandle->userCallBack.Int1FinishCallBack != NULL) { /* Invoke the callback function to the user */ + adcHandle->userCallBack.Int1FinishCallBack(handle); + } +} + +/** + * @brief ADC Interrupt2 service processing function. + * @param handle ADC handle. + * @retval None. + */ +void HAL_ADC_IrqHandlerInt2(void *handle) +{ + ADC_ASSERT_PARAM(handle != NULL); + ADC_Handle *adcHandle = (ADC_Handle *)handle; + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_IntxClearEoc(adcHandle, ADC_INT_NUMBER2); + DCL_ADC_ClearIntx(adcHandle->baseAddress, ADC_INT_NUMBER2); + if (adcHandle->userCallBack.Int2FinishCallBack != NULL) { /* Invoke the callback function to the user */ + adcHandle->userCallBack.Int2FinishCallBack(handle); + } +} + +/** + * @brief ADC Interrupt3 service processing function. + * @param handle ADC handle. + * @retval None. + */ +void HAL_ADC_IrqHandlerInt3(void *handle) +{ + ADC_ASSERT_PARAM(handle != NULL); + ADC_Handle *adcHandle = (ADC_Handle *)handle; + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_IntxClearEoc(adcHandle, ADC_INT_NUMBER3); + DCL_ADC_ClearIntx(adcHandle->baseAddress, ADC_INT_NUMBER3); + if (adcHandle->userCallBack.Int3FinishCallBack != NULL) { /* Invoke the callback function to the user */ + adcHandle->userCallBack.Int3FinishCallBack(handle); + } +} + +/** + * @brief ADC Interrupt4 service processing function. + * @param handle ADC handle. + * @retval None. + */ +void HAL_ADC_IrqHandlerInt4(void *handle) +{ + ADC_ASSERT_PARAM(handle != NULL); + ADC_Handle *adcHandle = (ADC_Handle *)handle; + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_IntxClearEoc(adcHandle, ADC_INT_NUMBER4); + DCL_ADC_ClearIntx(adcHandle->baseAddress, ADC_INT_NUMBER4); + if (adcHandle->userCallBack.Int4FinishCallBack != NULL) { /* Invoke the callback function to the user */ + adcHandle->userCallBack.Int4FinishCallBack(handle); + } +} + +/** + * @brief ADC Event Interrupt service processing function. + * @param handle ADC handle. + * @retval None. + */ +void HAL_ADC_IrqHandlerAllEvent(void *handle) +{ + BASE_FUNC_UNUSED(handle); +} + +/** + * @brief User callback function registration interface. + * @param adcHandle ADC handle. + * @param typeID Id of callback function type. + * @param pCallback Pointer of the specified callbcak function. + * @retval None. + */ +void HAL_ADC_RegisterCallBack(ADC_Handle *adcHandle, ADC_CallbackFunType typeID, ADC_CallbackType pCallback) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + switch (typeID) { + case ADC_CALLBACK_INT1: + adcHandle->userCallBack.Int1FinishCallBack = pCallback; + break; + case ADC_CALLBACK_INT2: + adcHandle->userCallBack.Int2FinishCallBack = pCallback; + break; + case ADC_CALLBACK_INT3: + adcHandle->userCallBack.Int3FinishCallBack = pCallback; + break; + case ADC_CALLBACK_INT4: + adcHandle->userCallBack.Int4FinishCallBack = pCallback; + break; + case ADC_CALLBACK_DMA: + adcHandle->userCallBack.DmaFinishCallBack = pCallback; + break; + case ADC_CALLBACK_INTOVER: + adcHandle->userCallBack.IntxOverCallBack = pCallback; + break; + case ADC_CALLBACK_DMAOVER: + adcHandle->userCallBack.DmaOverCallBack = pCallback; + break; + case ADC_CALLBACK_TRIGOVER: + adcHandle->userCallBack.TrigOverCallBack = pCallback; + break; + case ADC_CALLBACK_EOCOVER: + adcHandle->userCallBack.EocOverCallBack = pCallback; + break; + case ADC_CALLBACK_DMAERROR: + adcHandle->userCallBack.DmaErrorCallBack = pCallback; + break; + default: + return; + } +} + +#if defined (CHIP_3065HRPIRZ) || defined (CHIP_3065HRPICZ) || defined (CHIP_3061HRPIKZ) || \ + defined (AU302PDF51) || defined (AU302NDF51) || defined (AU301LDF51) || defined (CHIP_3065ARPIRZ) +/** + * @brief Initialize the ADC and DAC for VDDA. + * Note: + * (1) Ensure that the ADC clock is turned on and the ADC has been initialized using before use. + * (2) The mapping between the ADC and DAC must be configured as follows: + * ADC0 -- DAC0, ADC1 -- DAC1, ADC2 -- DAC0, ADC2 -- DAC2. + * (3) The soc parameter must be set to an SOC that is not occupied in the ADC. + * (4) The user-configured DAC output value need >= 128. + * @param dacx DAC register base address. + * @param adcx ADC register base address. + * @param soc ID of SOC(start of conversion), managing the specific sample inputs. + * @param dacx DAC register base address. + * @param useDac ture: dacx has been used, false: dacx has not been used. + * @retval BASE_StatusType. + */ +BASE_StatusType HAL_ADC_InitForVdda(ADC_RegStruct *adcx, ADC_SOCNumber soc, DAC_RegStruct *dacx, bool useDac) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_ASSERT_PARAM(IsDACInstance(dacx)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + DAC_Handle dac = {0}; + dac.baseAddress = dacx; + unsigned int valueOfDac = 223; /* 223 is the recommended value for the DAC */ + if (useDac == false) { /* Check whether the DAC is used */ + dac.dacValue = valueOfDac; + HAL_DAC_Init(&dac); + } else { + valueOfDac = dac.baseAddress->DAC_VALUE.reg; + } + if (valueOfDac < 128) { /* The user-configured DAC output value need >= 128 */ + return BASE_STATUS_ERROR; + } + ADC_Handle adc = {0}; + unsigned int input = ADC_CH_ADCINB7; + if (adcx == ADC2 && dacx == DAC0) { + input = ADC_CH_ADCINB6; + } + adc.baseAddress = adcx; + SOC_Param socParam = {0}; + socParam.adcInput = input; /* DAC input */ + socParam.sampleHoldTime = 2; /* adc sample holed time set as 2 */ + socParam.sampleTotalTime = 32; /* adc sample total time set as 32 */ + socParam.softTrigSource = ADC_TRIGSOC_SOFT; + socParam.intTrigSource = ADC_TRIGSOC_NONEINT; + socParam.periphTrigSource = ADC_TRIGSOC_NONEPERIPH; + socParam.finishMode = ADC_SOCFINISH_NONE; + HAL_ADC_ConfigureSoc(&adc, soc, &socParam); + return BASE_STATUS_OK; +} + +/** + * @brief The DAC is sampled by using the ADC and converted to the VDDA voltage of the DAC. + * @param adcx ADC register base address. + * @param soc ID of SOC(start of conversion), managing the specific sample inputs. + * @param dacx DAC register base address. + * @param useDac ture: dacx has been used, false: dacx has not been used. + * @retval float, The reference voltage. + */ +float HAL_ADC_GetVddaByDac(ADC_RegStruct *adcx, ADC_SOCNumber soc, DAC_RegStruct *dacx, bool useDac) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_ASSERT_PARAM(IsDACInstance(dacx)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + unsigned int valueOfDac = 223; /* 223 is the recommended value for the DAC */ + if (useDac == true) { /* Check whether the DAC is used */ + valueOfDac = dacx->DAC_VALUE.reg; + } + if (valueOfDac < 128) { /* The user-configured DAC output value need >= 128 */ + return 0.0f; + } + unsigned ret = 0; + unsigned int count = 0; + ADC_Handle adc = {0}; + adc.baseAddress = adcx; + for (unsigned int i = 0; i < 10; ++i) { /* Average of 10 times */ + HAL_ADC_SoftTrigSample(&adc, soc); + BASE_FUNC_DELAY_US(4); /* delay 4 us */ + if (HAL_ADC_CheckSocFinish(&adc, soc) == BASE_STATUS_ERROR) { + continue; + } + count++; + unsigned int tmp = HAL_ADC_GetConvResult(&adc, soc); + ret += tmp; + } + if (count == 0) { + return 0.0f; + } + float ori = (float)ret / (float)count; + /* 256.0, 3.33333 and 4096.0 are used to convert the voltage */ + float voltage = 256.0f / (float)valueOfDac * 3.33333f * ori / 4096.0f; + return voltage; +} + +/** + * @brief set an external reference source to convert the original sampling results of the ADC. + * @param adcx ADC register base address. + * @param soc ID of SOC(start of conversion), managing the specific sample inputs. + * @param vdda Voltage Drain Drain. + * @retval unsigned int, Sampled results after using the reference voltage. + */ +unsigned int HAL_ADC_GetTransResultByVdda(ADC_RegStruct *adcx, ADC_SOCNumber soc, float vdda) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + if (vdda < 2.6f || vdda > 3.63f) { /* 2.6v ~ 3.63v is reasonable value range of VDDA */ + return 0; + } + unsigned int oriAdcResult = DCL_ADC_ReadSOCxResult(adcx, soc); + float tmp = 3.33333f / vdda * (float)oriAdcResult; /* ADC full scale from 3.33333v to VDDA */ + /* If the actual VDDA value is greater than the standard voltage value, the actual result is greater than 0xFFF */ + unsigned int ret = (unsigned int)tmp; + return ret; +} +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/adc/src/adc_ex.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/adc/src/adc_ex.c new file mode 100644 index 00000000..e1f7a55e --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/adc/src/adc_ex.c @@ -0,0 +1,111 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file adc_ex.c + * @author MCU Driver Team + * @brief ADC module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the ADC. + * + ADC Synchronous Sampling. + * + ADC Software Calibration. + */ + +/* Includes ------------------------------------------------------------------*/ + +#include "adcinit.h" +#include "adc_ex.h" + +/** + * @brief Enable ADC synchronous sample.Use one ADC with two different SOCs, configure the same trigger source, and + * sample both inputs simultaneously. When used, the inputs in group A need to be configured with one SOC, and + * the inputs in group B need to be configured with another SOC. + * @param adcHandle ADC handle. + * @param syncParam Param struct of synchronous sample. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_ADC_StartSyncSampleEx(ADC_Handle *adcHandle, SOC_SyncParam *syncParam) +{ + ADC_ASSERT_PARAM(adcHandle != NULL); + ADC_ASSERT_PARAM(IsADCInstance(adcHandle->baseAddress)); + ADC_ASSERT_PARAM(syncParam != NULL); + ADC_PARAM_CHECK_WITH_RET(IsADCGroupAChannel(syncParam->ChannelA) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCGroupBChannel(syncParam->ChannelB) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCChargeTime(syncParam->sampleTotalTime) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCHodeTime(syncParam->sampleHoldTime) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCSoftTrig(syncParam->softTrigSource) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCPeriphTrig(syncParam->periphTrigSource) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCIntTrig(syncParam->intTrigSource) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCFinishMode(syncParam->finishMode) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(IsADCSyncGroup(syncParam->group) == true, BASE_STATUS_ERROR); + unsigned int socA = 0; + unsigned int socB = 0; + unsigned int tmp; + SOC_Param param; /* Configuring SOC Parameters */ + param.adcInput = syncParam->ChannelA; + param.sampleHoldTime = syncParam->sampleHoldTime; + param.sampleTotalTime = syncParam->sampleTotalTime; + param.finishMode = ADC_SOCFINISH_NONE; + param.softTrigSource = syncParam->softTrigSource; + param.intTrigSource = syncParam->intTrigSource; + param.periphTrigSource = syncParam->periphTrigSource; + for (unsigned int i = 0; i < SYNCGROUP_NUM; i++) { + tmp = (1 << i); + if (tmp & syncParam->group) { + socA = 2 * i; /* 2 for converting from group number to SOC number */ + socB = 2 * i + 1; /* 2 for converting from group number to SOC number */ + break; + } + } + DCL_ADC_SetSyncSample(adcHandle->baseAddress, syncParam->group); + /* Group A does not report DMA and interrupts by default. Group B reports DMA and interrupts after sampling */ + HAL_ADC_ConfigureSoc(adcHandle, socA, ¶m); /* Configuring group A input */ + param.finishMode = syncParam->finishMode; + param.adcInput = syncParam->ChannelB; + HAL_ADC_ConfigureSoc(adcHandle, socB, ¶m); /* Configuring group B input */ + if (syncParam->finishMode >= ADC_SOCFINISH_INT1) { + HAL_ADC_StartIt(adcHandle); /* Configuring Interrupts During Synchronous Sampling */ + } + return BASE_STATUS_OK; +} + +/** + * @brief Obtains the sample result after SOC conversion. + * @param adcx ADC Base Pointer. + * @param soc ID of SOC. + * @param originalRet Sampling original data. + * @retval unsigned int, Calibrated data. + */ +unsigned int HAL_ADC_ActiveCalibrateRetEx(ADC_RegStruct * const adcx, unsigned int soc, unsigned int originalRet) +{ + ADC_ASSERT_PARAM(IsADCInstance(adcx)); + ADC_PARAM_CHECK_WITH_RET(IsADCSOCx(soc) == true, BASE_STATUS_ERROR); + ADC_PARAM_CHECK_WITH_RET(originalRet <= 0x1000, BASE_STATUS_ERROR); + uintptr_t adcAddr = (uintptr_t)(void *)adcx; + unsigned int addrIndex = (adcAddr & 0x3000) >> 12; /* 0x3000 and 12 are used to convert addresses to index */ + unsigned int socNum = DCL_ADC_GetSOCxInputChannel(adcx, soc); + unsigned int vrefIndex = adcx->ADC_ANA_CTRL.BIT.adc_ana_gsh0; + unsigned int shIndex = ((socNum & 0x18) == 0) ? 0 : 1; /* 0x18 is used to convert sh0 or sh1 to index */ + float k1 = g_adcParmList[addrIndex][vrefIndex][shIndex].k1; + float k2 = g_adcParmList[addrIndex][vrefIndex][shIndex].k2; + int result = (int)((float)originalRet * k1 + k2); + if (result < 0) { + return 0; /* Limit the range of results after calibration */ + } else if ((unsigned int)result > 0xFFF) { + return 0xFFF; /* Limit the range of results after calibration */ + } + return (unsigned int)result; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/apt/common/inc/apt.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/apt/common/inc/apt.h new file mode 100644 index 00000000..331709f5 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/apt/common/inc/apt.h @@ -0,0 +1,357 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file apt.h + * @author MCU Driver Team + * @brief APT module driver. + * @details This file provides functions declaration of the APT module. + * + APT handle structure definition. + * + Initialization and de-initialization functions. + * + APT Service Functions. + */ + +#ifndef McuMagicTag_APT_H +#define McuMagicTag_APT_H + +#include "apt_ip.h" + +#define EM_OUT_EVT_FILTER_EN 0x0f +#define EM_CMB_MODE_OFFSET 16 +#define EM_CMB_MODE_INTERVAL 4 +#define EM_CMB_SRC_SEL_INTERVAL 4 +#define EM_OR_INTERVAL 16 +#define EM_CMB_EVT_NUM 4 +#define EM_COMBINE_A1_SRC_ENABLE_ALL 0xF +/** + * @defgroup APT APT + * @brief APT module. + * @{ + */ + + +/** + * @defgroup APT_Common APT Common + * @brief APT common external module. + * @{ + */ + +/** + * @defgroup APT_Handle_Definition APT Handle Definition + * @{ + */ + +/* + Basic type AHBL ALBH AHBH ALBL + ___ __ __ ___ __ __ + ChannelA __| |__ |___| __| |__ |___| + __ __ ___ ___ __ __ + ChannelB |___| __| |__ __| |__ |___| +*/ +/** + * @brief Basic PWM waveform type. + * @details waveform type: + * + APT_PWM_BASIC_A_HIGH_B_LOW -- Basic PWM waveform type 1. + * + APT_PWM_BASIC_A_LOW_B_HIGH -- Basic PWM waveform type 2. + * + APT_PWM_BASIC_A_HIGH_B_HIGH -- Basic PWM waveform type 3. + * + APT_PWM_BASIC_A_LOW_B_LOW -- Basic PWM waveform type 4. + */ +typedef enum { + APT_PWM_BASIC_A_HIGH_B_LOW = 0x00000000U, + APT_PWM_BASIC_A_LOW_B_HIGH = 0x00000001U, + APT_PWM_BASIC_A_HIGH_B_HIGH = 0x00000002U, + APT_PWM_BASIC_A_LOW_B_LOW = 0x00000003U, +} APT_PWMBasicType; + +/** + * @brief The actual outputs of PWM channelA and channelB. + * @details Output: + * + APT_PWM_OUT_BASIC_TYPE = 0x00000000U -- PWM channel output the waveform according to basic PWM type. + * + APT_PWM_OUT_ALWAYS_LOW = 0x00000001U -- PWM channel output low level. + * + APT_PWM_OUT_ALWAYS_HIGH = 0x00000002U -- PWM channel output high level. + */ +typedef enum { + APT_PWM_OUT_BASIC_TYPE = 0x00000000U, + APT_PWM_OUT_ALWAYS_LOW = 0x00000001U, + APT_PWM_OUT_ALWAYS_HIGH = 0x00000002U, +} APT_PWMChannelOutType; + +/** + * @brief PWM waveform configuration handle of APT module. + */ +typedef struct { + APT_PWMBasicType basicType; /**< Basic PWM waveform type. */ + APT_PWMChannelOutType chAOutType; /**< Actual output of PWM channelA. */ + APT_PWMChannelOutType chBOutType; /**< Actual output of PWM channelB. */ + APT_CountMode cntMode; /**< Count mode of APT time-base counter. */ + unsigned short dividerFactor; /**< Divider factor. The range is 0~4095. */ + unsigned short timerPeriod; /**< Count period of APT time-base timer. */ + unsigned short divInitVal; /**< Initial value of divider. */ + unsigned short cntInitVal; /**< Initial value of time-base counter */ + unsigned short cntCmpLeftEdge; /**< Count compare point of the left edge of PWM waveform. */ + unsigned short cntCmpRightEdge; /**< Count compare point of the right edge of PWM waveform. */ + APT_BufferLoadMode cntCmpLoadMode; /**< Buffer load mode of PWM waveform count compare value. */ + unsigned int cntCmpLoadEvt; /**< Buffer load event of PWM waveform count compare value. */ + unsigned short deadBandCnt; /**< Count value of dead-band counter. In units of APT clock. */ +} APT_PWMWaveForm; + +/** + * @brief ADC trigger configuration handle of APT module. + */ +typedef struct { + bool trgEnSOCA; /**< Enable of ADC trigger source SOCA. */ + APT_ADCTriggerSource trgSrcSOCA; /**< Source of ADC trigger source SOCA. */ + unsigned short trgScaleSOCA; /**< Scale of ADC trigger source SOCA. */ + unsigned short cntCmpSOCA; /**< Count compare point of ADC trigger source SOCA when using CMPA */ + bool trgEnSOCB; /**< Enable of ADC trigger source SOCB. */ + APT_ADCTriggerSource trgSrcSOCB; /**< Source of ADC trigger source SOCB. */ + unsigned short trgScaleSOCB; /**< Scale of ADC trigger source SOCB. */ + unsigned short cntCmpSOCB; /**< Count compare point of ADC trigger source SOCB when using CMPB */ + APT_BufferLoadMode cntCmpLoadMode; /**< Buffer load mode of ADC trigger count compare value. */ + unsigned int cntCmpLoadEvt; /**< Buffer load event of ADC trigger count compare value. */ +} APT_ADCTrigger; + +/** + * @brief Timer interrupt configuration handle of APT module. + */ +typedef struct { + bool tmrInterruptEn; /**< Enable of APT module timer interrupt. */ + APT_TimerInterruptSrc tmrInterruptSrc; /**< Source of APT module timer interrupt. */ + unsigned short tmrInterruptScale; /**< Scale of APT module timer interrupt. */ +} APT_TimerInterrupt; + +/** + * @brief Output control protection configuration handle of APT module. + */ +typedef struct { + bool ocEventEn; /**< Enable of output control event. */ + APT_OutCtrlEvent ocEvent; /**< Output control event. Limited to IO events or system events. */ + APT_OutCtrlMode ocEventMode; /**< Output control protection mode. */ + APT_CBCClearMode cbcClrMode; /**< Event clear mode when using cycle-by-cycle mode. */ + APT_EMEventPolarity evtPolarity; /**< Event effective polarity. */ + APT_OutCtrlAction ocAction; /**< Output control protection action. */ + APT_EmulationMode emMode; /**< emulation mode */ + bool ocEvtInterruptEn; /**< Enable of output control event interrupt. */ +} APT_OutCtrlProtect; + +/** + * @brief Source event of event magnagement. + */ +typedef enum { + APT_EM_ORIGINAL_SRC_POE0 = 0x00000001U, + APT_EM_ORIGINAL_SRC_POE1 = 0x00000002U, + APT_EM_ORIGINAL_SRC_POE2 = 0x00000004U, + APT_EM_ORIGINAL_SRC_ACMP0 = 0x00000008U, + APT_EM_ORIGINAL_SRC_ACMP1 = 0x00000010U, + APT_EM_ORIGINAL_SRC_ACMP2 = 0x00000020U, + APT_EM_ORIGINAL_SRC_EVTMP4 = 0x00000040U, + APT_EM_ORIGINAL_SRC_EVTMP5 = 0x00000080U, + APT_EM_ORIGINAL_SRC_EVTMP6 = 0x00000100U, +} APT_EMOriginalEvtSrc; + +/** + * @brief Filter mask bit. + */ +typedef enum { + APT_EM_POE0_INVERT_BIT = 0x00000001U, + APT_EM_POE1_INVERT_BIT = 0x00000002U, + APT_EM_POE2_INVERT_BIT = 0x00000004U, + APT_EM_ACMP0_INVERT_BIT = 0x00000008U, + APT_EM_ACMP1_INVERT_BIT = 0x00000010U, + APT_EM_ACMP2_INVERT_BIT = 0x00000020U, + APT_EM_EVTMP4_INVERT_BIT = 0x00000040U, + APT_EM_EVTMP5_INVERT_BIT = 0x00000080U, + APT_EM_EVTMP6_INVERT_BIT = 0x00000100U, +} APT_EMPolarityMskBit; + +/** + * @brief System protect event; + */ +typedef enum { + APT_SYS_EVT_DEBUG = 0x00000010U, + APT_SYS_EVT_CLK = 0x00000020U, + APT_SYS_EVT_MEM = 0x00000040U, +} APT_SysOcEvent; + +/** + * @brief Output control protection configuration handle of APT module. + */ +typedef struct { + bool ocEventEnEx; /**< oc event enable */ + APT_OutCtrlMode ocEventModeEx; /**< Output control protection mode. */ + APT_CBCClearMode cbcClrModeEx; /**< Event clear mode when using cycle-by-cycle mode. */ + APT_OutCtrlAction ocActionEx; /**< Output control protection channel A action. */ + APT_OutCtrlAction ocActionBEx; /**< Output control protection channel B action. */ + bool ocEvtInterruptEnEx; /**< Enable of output control event interrupt. */ + APT_SysOcEvent ocSysEvent; /**< System protect event */ + APT_EMOriginalEvtSrc originalEvtEx; /**< Event management's event source */ + APT_EMPolarityMskBit evtPolarityMaskEx; /**< Event effective polarity. */ + unsigned char filterCycleNumEx; /**< input source event filter */ +} APT_OutCtrlProtectEx; + +/** + * @brief struct of EM conbine event + */ +typedef struct { + APT_EMCombineEvtSrc emEvtSrc; /**< combine event selection */ + APT_EMCombineEvtMode emEvtCombineMode; /**< event combine mode */ + APT_EMEventPolarity emEvtPolar; /**< event source polarity */ + unsigned int emEvtOrEnBits; /**< event logic or enable bits */ +} APT_CombineEvt; + +/** + * @brief Shield window and capture configurations + */ +typedef struct { + bool wdEnable; /**< Shield windows enable bit */ + bool emCapEnable; /**< Enable EM captrue functions */ + APT_EMCombineEvent eventSel; /**< Window source event selection */ + APT_MaskWinResetMode wdStartAndCapClr; /**< Window's offset start count and EM capture clear condition */ + unsigned short wdOffset; /**< Window's offset value */ + unsigned short wdWidth; /**< Window's width value */ + APT_MaskWinPolarity wdPolar; /**< Window's polarity */ +} APT_WdAndCap; + + +/** + * @brief Valley switch configurations + */ +typedef struct { + bool vsEnable; /**< Valley switch enable */ + APT_EMEdgeFilterMode vsFilerEdgeSel; /**< Filter edge selection */ + unsigned char vsFilterCnt; /**< Filter edge count */ + APT_ValleyCapRstType vsClrType; /**< Clear type */ + APT_ValleyCountEdge vsCapEdgeSel; /**< Capture edge selection */ + unsigned char vsCapStartEdge; /**< Capture start edge */ + unsigned char vsCapEndEdge; /**< Capture end edge */ + APT_ValleyDelayMode vsCapDelayMode; /**< Capture delay mode */ + unsigned short vsCapSoftDelay; /**< Capture software calibrate value */ +} APT_ValleySw; + +/** + * @brief Event management handle of APT module + */ +typedef struct { + bool emEnable; /**< Enable bit of event management */ + APT_CombineEvt emEvt[EM_CMB_EVT_NUM]; /**< Combine events configuration */ + APT_WdAndCap emWdAndCap; /**< Shield windows and capture configuration */ + APT_ValleySw emValleySw; /**< Valley switch configuration */ +} APT_EventManage; + +/** + * @brief Synchronization handle of slave APT module. + */ +typedef struct { + unsigned short divPhase; /**< Divider phase when receiving APT synchronization pulse. */ + unsigned short cntPhase; /**< Counter phase when receiving APT synchronization pulse. */ + APT_SyncCountMode syncCntMode; /**< Count mode when receiving APT synchronization pulse. */ + APT_SyncInSrc syncInSrc; /**< Sync-in source of APT module */ + unsigned short cntrSyncSrc; + /**< Sync-in source of time-base counter synchronization + A logical OR of valid values can be passed as the cntrSyncSrc parameter. + Valid values for cntrSyncSrc are: + APT_CNTR_SYNC_SRC_COMBINE_EVENT_A1 - Enable combine event A1 as the counter synchronization source. + APT_CNTR_SYNC_SRC_COMBINE_EVENT_B1 - Enable combine event B1 as the counter synchronization source. + APT_CNTR_SYNC_SRC_SYNCIN - Enable Sync-In source as the counter synchronization source. */ +} APT_SlaveSyncIn; + +/** + * @brief Definition of callback function type. + */ +typedef void (* APT_CallbackType)(void *aptHandle); + +/** + * @brief Definition of callback function type. + */ +typedef struct { + void (* EvtInterruptCallBack)(void *handle); + void (* TmrInterruptCallBack)(void *handle); +} APT_UserCallBack; + +/** + * @brief The definition of the APT handle structure. + */ +typedef struct _APT_Handle { + APT_RegStruct *baseAddress; /**< Register base address. */ + APT_PWMWaveForm waveform; /**< PWM waveform configuration handle. */ + APT_ADCTrigger adcTrg; /**< ADC trigger configuration handle. */ + APT_TimerInterrupt tmrInterrupt; /**< Timer interrupt configuration handle. */ + APT_UserCallBack userCallBack; /**< Interrupt callback function when APT event happens. */ + APT_ExtendHandle handleEx; /**< extra handle */ +} APT_Handle; +/** + * @} + */ + +/** + * @defgroup APT_API_Declaration APT HAL API + * @{ + */ + +/** + * @brief Definition of callback function ID. + */ +typedef enum { + APT_TIMER_INTERRUPT = 0x00000000U, + APT_EVENT_INTERRUPT = 0x00000001U, +} APT_InterruputType; + +BASE_StatusType HAL_APT_PWMInit(APT_Handle *aptHandle); +BASE_StatusType HAL_APT_PWMDeInit(APT_Handle *aptHandle); +BASE_StatusType HAL_APT_ProtectInit(APT_Handle *aptHandle, APT_OutCtrlProtect *protect); +BASE_StatusType HAL_APT_ProtectDeInit(APT_Handle *aptHandle, APT_OutCtrlProtect *protect); +BASE_StatusType HAL_APT_ProtectInitEx(APT_Handle *aptHandle, APT_OutCtrlProtectEx *protect); +BASE_StatusType HAL_APT_ProtectDeInitEx(APT_Handle *aptHandle, APT_OutCtrlProtectEx *protect); +void HAL_APT_ForcePWMOutputLow(APT_Handle *aptHandle); +BASE_StatusType HAL_APT_MasterSyncInit(APT_Handle *aptHandle, unsigned short syncOutSrc); +BASE_StatusType HAL_APT_SlaveSyncInit(APT_Handle *aptHandle, APT_SlaveSyncIn *slaveSyncIn); +void HAL_APT_StartModule(unsigned int aptRunMask); +void HAL_APT_StopModule(unsigned int aptRunMask); +BASE_StatusType HAL_APT_SetPWMDuty(APT_Handle *aptHandle, unsigned short cntCmpLeftEdge, \ + unsigned short cntCmpRightEdge); +BASE_StatusType HAL_APT_SetPWMDutyByNumber(APT_Handle *aptHandle, unsigned int duty); +BASE_StatusType HAL_APT_SetADCTriggerTime(APT_Handle *aptHandle, unsigned short cntCmpSOCA, unsigned short cntCmpSOCB); +void HAL_APT_EventIrqHandler(void *handle); +void HAL_APT_TimerIrqHandler(void *handle); +void HAL_APT_RegisterCallBack(APT_Handle *aptHandle, APT_InterruputType typeID, APT_CallbackType pCallback); +BASE_StatusType HAL_APT_EMInit(APT_Handle *aptHandle, APT_EventManage *eventManage); +unsigned short HAL_APT_EMGetCapValue(APT_Handle *aptHandle); +void HAL_APT_EMSetWdOffsetAndWidth(APT_Handle *aptHandle, unsigned short offset, unsigned short width); +void HAL_APT_EMSetValleySwithSoftDelay(APT_Handle *aptHandle, unsigned short calibrate); +BASE_StatusType HAL_APT_ChangeOutputType(APT_Handle *aptHandle, + APT_PWMChannel channel, + APT_PWMChannelOutType aptAction); + +/* Attribute configuration of each reference point. */ +BASE_StatusType APT_ConfigRefA(APT_Handle *aptHandle, APT_RefDotParameters *refDotParameters); +BASE_StatusType APT_ConfigRefB(APT_Handle *aptHandle, APT_RefDotParameters *refDotParameters); +BASE_StatusType APT_ConfigRefC(APT_Handle *aptHandle, APT_RefDotParameters *refDotParameters); +BASE_StatusType APT_ConfigRefD(APT_Handle *aptHandle, APT_RefDotParameters *refDotParameters); +/* Combination configuration of reference point attributes. */ +BASE_StatusType HAL_APT_ConfigRefDot(APT_Handle *aptHandle, APT_RefDotSelect refDotSelect, + APT_RefDotParameters *refDotParameters); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_APT_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/apt/inc/apt_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/apt/inc/apt_ip.h new file mode 100644 index 00000000..47d31618 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/apt/inc/apt_ip.h @@ -0,0 +1,3918 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file apt_ip.h + * @author MCU Driver Team + * @brief Header file containing APT module DCL driver functions. + * This file provides functions to manage the following functionalities of APT module. + * + Definition of APT configuration parameters. + * + APT registers mapping structure. + * + Direct Configuration Layer driver functions. + */ + +#ifndef McuMagicTag_APT_IP_H +#define McuMagicTag_APT_IP_H + +#include "baseinc.h" + +#ifdef APT_PARAM_CHECK + #define APT_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM + #define APT_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET + #define APT_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else + #define APT_ASSERT_PARAM(para) ((void)0U) + #define APT_PARAM_CHECK_NO_RET(para) ((void)0U) + #define APT_PARAM_CHECK_WITH_RET(param, ret) ((void)0U) +#endif + +/** + * @addtogroup APT + * @{ + */ + +/** + * @defgroup APT_IP APT_IP + * @brief APT_IP: apt_v0. + * @{ + */ + +/** + * @defgroup APT_Param_Def APT Parameters Definition + * @brief Definition of APT configuration parameters + * @{ + */ + +/* Bitmask of the aptx_run bits in SYSCTRL1 register. */ +#define RUN_APT0 0x00000001U +#define RUN_APT1 0x00000002U +#define RUN_APT2 0x00000004U +#define RUN_APT3 0x00000008U +#define RUN_APT4 0x00000010U +#define RUN_APT5 0x00000020U +#define RUN_APT6 0x00000040U +#define RUN_APT7 0x00000080U +#define RUN_APT8 0x00000100U + +/* Limited values for some configuration items of APT module. */ +#define DIVIDER_FACTOR_MAX 0x00000FFFU +#define TIMEBASE_COUNTER_MAX 0x0000FFFFU +#define TIMER_INTERRUPT_CNT_MAX 0x0000000FU +#define ADC_CONVERSION_START_CNT_MAX 0x0000000FU +#define VCAP_STARY_STOP_EDGE_CNT_MAX 0x0000000FU +#define EDGE_FILTER_EDGE_CNT_MAX 0x0000000FU +#define CNTR_SYNC_SOURCE_MAX 0x00000007U +#define SYNC_OUT_SOURCE_MAX 0x000000FFU +#define GLOBAL_LOAD_CNT_MAX 0x0000000FU + +/* Values that can be passed to DCL_APT_SetPeriodLoadEvent() as the loadEvent parameter. */ +#define APT_PERIOD_LOAD_EVENT_ZERO 0x00000001U +#define APT_PERIOD_LOAD_EVENT_A1 0x00000004U +#define APT_PERIOD_LOAD_EVENT_B1 0x00000008U +#define APT_PERIOD_LOAD_EVENT_SYNC 0x00000010U + +/* Values that can be passed to DCL_APT_SetCompareLoadEvent() as the loadEvent parameter. */ +#define APT_COMPARE_LOAD_EVENT_ZERO 0x00000001U +#define APT_COMPARE_LOAD_EVENT_PERIOD 0x00000002U +#define APT_COMPARE_LOAD_EVENT_A1 0x00000004U +#define APT_COMPARE_LOAD_EVENT_B1 0x00000008U +#define APT_COMPARE_LOAD_EVENT_SYNC 0x00000010U + +/* Values that can be returned by DCL_APT_GetCounterDirection(). */ +#define APT_COUNTER_STATUS_COUNT_DOWN 0x00000000U +#define APT_COUNTER_STATUS_COUNT_UP 0x00000001U + +/* Values that can be passed to DCL_APT_SetPWMActionLoadEvent() and + * DCL_APT_SetSwContActionLoadEvent() as the loadEvent parameter. */ +#define APT_ACTION_LOAD_EVENT_ZERO 0x00000001U +#define APT_ACTION_LOAD_EVENT_PERIOD 0x00000002U +#define APT_ACTION_LOAD_EVENT_A1 0x00000004U +#define APT_ACTION_LOAD_EVENT_B1 0x00000008U +#define APT_ACTION_LOAD_EVENT_SYNC 0x00000010U + + +/* Values that can be passed to DCL_APT_SetDGConfigLoadEvent(), DCL_APT_SetREDCounterLoadEvent() and + * DCL_APT_SetFEDCounterLoadEvent() as the loadEvent parameter. */ + +#define APT_DEAD_BAND_LOAD_EVENT_ZERO 0x00000001U +#define APT_DEAD_BAND_LOAD_EVENT_PERIOD 0x00000002U + +/* Values that can be passed to DCL_APT_SetEMEventOR() as the event1OREn and event1OREn parameter. */ +#define APT_EM_OR_EN_GPIO_EVENT_1 0x00000001U +#define APT_EM_OR_EN_GPIO_EVENT_2 0x00000002U +#define APT_EM_OR_EN_GPIO_EVENT_3 0x00000004U +#define APT_EM_OR_EN_MXU_EVENT_1 0x00000008U +#define APT_EM_OR_EN_MXU_EVENT_2 0x00000010U +#define APT_EM_OR_EN_MXU_EVENT_3 0x00000020U +#define APT_EM_OR_EN_MXU_EVENT_4 0x00000040U +#define APT_EM_OR_EN_MXU_EVENT_5 0x00000080U +#define APT_EM_OR_EN_MXU_EVENT_6 0x00000100U +#define APT_EM_OR_EN_MXU_EVENT_7 0x00000200U +#define APT_EM_OR_EN_MXU_EVENT_8 0x00000400U +#define APT_EM_OR_EN_MXU_EVENT_9 0x00000800U +#define APT_EM_OR_EN_MXU_EVENT_10 0x00001000U +#define APT_EM_OR_EN_MXU_EVENT_11 0x00002000U +#define APT_EM_OR_EN_MXU_EVENT_12 0x00004000U + +/* Values that can be passed to DCL_APT_SetTimeBaseCounterSyncSrc() as the cntrSyncSrc parameter. */ +#define APT_CNTR_SYNC_SRC_COMBINE_EVENT_A1 0x00000001U +#define APT_CNTR_SYNC_SRC_COMBINE_EVENT_B1 0x00000002U +#define APT_CNTR_SYNC_SRC_SYNCIN 0x00000004U + +/* Values that can be passed to DCL_APT_SetSyncOutPulseSrc() as the syncOutSrc parameter. */ +#define APT_SYNC_OUT_ON_CNTR_ZERO 0x00000001U +#define APT_SYNC_OUT_ON_CNTR_PERIOD 0x00000002U +#define APT_SYNC_OUT_ON_COMBINE_EVENT_A1 0x00000004U +#define APT_SYNC_OUT_ON_COMBINE_EVENT_B1 0x00000008U +#define APT_SYNC_OUT_ON_CNTR_CMPB 0x00000020U +#define APT_SYNC_OUT_ON_CNTR_CMPC 0x00000040U +#define APT_SYNC_OUT_ON_CNTR_CMPD 0x00000080U + +/* Values that can be passed to DCL_APT_SetGlobalLoadPrescale() as the glbLoadEvt parameter. */ +#define APT_GLB_LOAD_ON_CNTR_ZERO 0x00000001U +#define APT_GLB_LOAD_ON_CNTR_PERIOD 0x00000002U +#define APT_GLB_LOAD_ON_CNTR_SYNC 0x00000004U + +/** + * @brief APT Extra Handle. + */ +typedef struct { + ; +} APT_ExtendHandle; + +/** + * @brief Emulation stop mode of APT module. + */ +typedef enum { + APT_EMULATION_NO_STOP = 0x00000001U, + APT_EMULATION_STOP_COUNTER = 0x00000002U, + APT_EMULATION_STOP_APT = 0x00000003U, +} APT_EmulationMode; + +/** + * @brief Count mode of time-base counter. + */ +typedef enum { + APT_COUNT_MODE_UP = 0x00000000U, + APT_COUNT_MODE_DOWN = 0x00000001U, + APT_COUNT_MODE_UP_DOWN = 0x00000002U, + APT_COUNT_MODE_FREEZE = 0x00000003U, +} APT_CountMode; + +/** + * @brief Count mode after synchronization for slave APT module. + */ +typedef enum { + APT_COUNT_MODE_AFTER_SYNC_DOWN = 0x00000000U, + APT_COUNT_MODE_AFTER_SYNC_UP = 0x00000001U, +} APT_SyncCountMode; + +/** + * @brief Count compare reference of time-base counter. + */ +typedef enum { + APT_COMPARE_REFERENCE_A = 0x00000000U, + APT_COMPARE_REFERENCE_B = 0x00000001U, + APT_COMPARE_REFERENCE_C = 0x00000002U, + APT_COMPARE_REFERENCE_D = 0x00000003U, +} APT_CompareRef; + +/** + * @brief Buffer load mode of the registers that support buffer register. + * @details Load mode: + * + APT_BUFFER_DISABLE -- Disable register buffer + * + APT_BUFFER_INDEPENDENT_LOAD -- Enable register buffer and load independently + * + APT_BUFFER_GLOBAL_LOAD -- enable register buffer and load globally + */ +typedef enum { + APT_BUFFER_DISABLE = 0x00000000U, + APT_BUFFER_INDEPENDENT_LOAD = 0x00000001U, + APT_BUFFER_GLOBAL_LOAD = 0x00000003U, +} APT_BufferLoadMode; + +/** + * @brief PWM waveform output channel. + */ +typedef enum { + APT_PWM_CHANNEL_A = 0x00000000U, + APT_PWM_CHANNEL_B = 0x00000001U, +} APT_PWMChannel; + +/** + * @brief PWM waveform action on PWM action events. + */ +typedef enum { + APT_PWM_ACTION_HOLD = 0x00000000U, + APT_PWM_ACTION_LOW = 0x00000001U, + APT_PWM_ACTION_HIGH = 0x00000002U, + APT_PWM_ACTION_TOGGLE = 0x00000003U, +} APT_PWMAction; + +/** + * @brief Count compare event for generating PWM waveform actions. + * The enumeration values are the register bit field offset of the corresponding action events. + */ +typedef enum { + APT_PWM_ACTION_ON_TIMEBASE_ZERO = 0U, + APT_PWM_ACTION_ON_TIMEBASE_PERIOD = 2U, + APT_PWM_ACTION_ON_CMPA_COUNT_UP = 4U, + APT_PWM_ACTION_ON_CMPA_COUNT_DOWN = 6U, + APT_PWM_ACTION_ON_CMPB_COUNT_UP = 8U, + APT_PWM_ACTION_ON_CMPB_COUNT_DOWN = 10U, + APT_PWM_ACTION_ON_CMPC_COUNT_UP = 12U, + APT_PWM_ACTION_ON_CMPC_COUNT_DOWN = 14U, + APT_PWM_ACTION_ON_CMPD_COUNT_UP = 16U, + APT_PWM_ACTION_ON_CMPD_COUNT_DOWN = 18U, + APT_PWM_ACTION_ON_C1_COUNT_UP = 20U, + APT_PWM_ACTION_ON_C1_COUNT_DOWN = 22U, + APT_PWM_ACTION_ON_C2_COUNT_UP = 24U, + APT_PWM_ACTION_ON_C2_COUNT_DOWN = 26U, +} APT_PWMActionEvent; + +/** + * @brief PWM action when using software continuous action. + */ +typedef enum { + APT_PWM_CONTINUOUS_ACTION_HOLD = 0x00000000U, + APT_PWM_CONTINUOUS_ACTION_LOW = 0x00000001U, + APT_PWM_CONTINUOUS_ACTION_HIGH = 0x00000002U, +} APT_PWMContAction; + +/** + * @brief PWM Generation event C1 and C2. + */ +typedef enum { + APT_PWM_GENERATION_EVENT_C1 = 0x00000000U, + APT_PWM_GENERATION_EVENT_C2 = 0x00000001U, +} APT_PGEventCx; + +/** + * @brief Source of PWM Generation event C1 and C2. + */ +typedef enum { + APT_PG_EVT_C_FORBIDDEN = 0x00000000U, + APT_PG_EVT_C_COMBINE_EVENT_A1 = 0x00000001U, + APT_PG_EVT_C_COMBINE_EVENT_A2 = 0x00000002U, + APT_PG_EVT_C_COMBINE_EVENT_B1 = 0x00000003U, + APT_PG_EVT_C_COMBINE_EVENT_B2 = 0x00000004U, + APT_PG_EVT_C_COMBINE_EVENT_FILT = 0x00000005U, + APT_PG_EVT_C_IO_EVENT1 = 0x00000006U, + APT_PG_EVT_C_IO_EVENT2 = 0x00000007U, + APT_PG_EVT_C_IO_EVENT3 = 0x00000008U, + APT_PG_EVT_C_SYNC_IN = 0x00000009U, +} APT_PGEventCxSrc; + +/** + * @brief Input source of Dead-Band rising edge delay counter. + * @details Input source: + * + APT_DB_RED_INPUT_PWM_A -- Dead-Band rising edge delay input is PWM channel A + * + APT_DB_RED_INPUT_PWM_B -- Dead-Band rising edge delay input is PWM channel B + */ +typedef enum { + APT_DB_RED_INPUT_PWM_A = 0x00000000U, + APT_DB_RED_INPUT_PWM_B = 0x00000001U, +} APT_REDInput; + +/** + * @brief Output mode of Dead-Band rising edge delay counter. + * @details Output mode: + * + APT_DB_RED_OUTPUT_NOT_INVERT -- Dead-Band rising edge delay output is not inverted + * + APT_DB_RED_OUTPUT_INVERT -- Dead-Band rising edge delay output is inverted + * + APT_DB_RED_OUTPUT_PWM_A -- Dead-Band rising edge delay is bypassed + */ +typedef enum { + APT_DB_RED_OUTPUT_NOT_INVERT = 0x00000000U, + APT_DB_RED_OUTPUT_INVERT = 0x00000002U, + APT_DB_RED_OUTPUT_PWM_A = 0x00000003U, +} APT_REDOutMode; + +/** + * @brief Input source of Dead-Band falling edge delay counter. + * @details Input source: + * + APT_DB_FED_INPUT_PWM_B -- Dead-Band falling edge delay input is PWM channel B + * + APT_DB_FED_INPUT_PWM_A -- Dead-Band falling edge delay input is PWM channel A + * + APT_DB_FED_INPUT_RED_OUT -- Falling edge delay input is rising edge delay output + * + APT_DB_FED_INPUT_ZERO -- Dead-Band falling edge delay input is 0 + */ +typedef enum { + APT_DB_FED_INPUT_PWM_B = 0x00000000U, + APT_DB_FED_INPUT_PWM_A = 0x00000001U, + APT_DB_FED_INPUT_RED_OUT = 0x00000002U, + APT_DB_FED_INPUT_ZERO = 0x00000003U, +} APT_FEDInput; + +/** + * @brief Output mode of Dead-Band falling edge delay counter. + * @details Output mode: + * + APT_DB_FED_OUTPUT_NOT_INVERT -- Dead-Band falling edge delay output is not inverted + * + APT_DB_FED_OUTPUT_INVERT -- Dead-Band falling edge delay output is inverted + * + APT_DB_FED_OUTPUT_PWM_B -- Dead-Band falling edge delay is bypassed + */ +typedef enum { + APT_DB_FED_OUTPUT_NOT_INVERT = 0x00000000U, /**< Dead-Band falling edge delay output is not inverted */ + APT_DB_FED_OUTPUT_INVERT = 0x00000002U, /**< Dead-Band falling edge delay output is inverted */ + APT_DB_FED_OUTPUT_PWM_B = 0x00000003U, /**< Dead-Band falling edge delay is bypassed */ +} APT_FEDOutMode; + +/** + * @brief Output control events. + */ +typedef enum { + APT_OC_NO_EVENT = 0x00000000U, + APT_OC_GPIO_EVENT_1 = 0x00000001U, + APT_OC_GPIO_EVENT_2 = 0x00000002U, + APT_OC_GPIO_EVENT_3 = 0x00000004U, + APT_OC_SYSTEM_EVENT_1 = 0x00000010U, + APT_OC_SYSTEM_EVENT_2 = 0x00000020U, + APT_OC_SYSTEM_EVENT_3 = 0x00000040U, + APT_OC_COMBINE_EVENT_A1 = 0x00000100U, + APT_OC_COMBINE_EVENT_A2 = 0x00000200U, + APT_OC_COMBINE_EVENT_B1 = 0x00000400U, + APT_OC_COMBINE_EVENT_B2 = 0x00000800U, +} APT_OutCtrlEvent; + +/** + * @brief Output control event mode. + */ +typedef enum { + APT_OUT_CTRL_ONE_SHOT = 0x00000000U, + APT_OUT_CTRL_CYCLE_BY_CYBLE = 0x00000001U, +} APT_OutCtrlMode; + +/** + * @brief Advanced output control events take into consideration of the direction of time-base counter. + * The enumeration values are the register bit field offset of the corresponding output control events. + */ +typedef enum { + APT_OC_EVT_GPIO_OR_SYSTEM_UP = 0U, + APT_OC_EVT_COMBINE_EVENT_A1_UP = 3U, + APT_OC_EVT_COMBINE_EVENT_A2_UP = 6U, + APT_OC_EVT_COMBINE_EVENT_B1_UP = 9U, + APT_OC_EVT_COMBINE_EVENT_B2_UP = 12U, + APT_OC_EVT_GPIO_OR_SYSTEM_DOWN = 16U, + APT_OC_EVT_COMBINE_EVENT_A1_DOWN = 19U, + APT_OC_EVT_COMBINE_EVENT_A2_DOWN = 22U, + APT_OC_EVT_COMBINE_EVENT_B1_DOWN = 25U, + APT_OC_EVT_COMBINE_EVENT_B2_DOWN = 28U, +} APT_OutCtrlEventDir; + +/** + * @brief Output control action. + * @details Control action: + * + APT_OUT_CTRL_ACTION_DISABLE -- Disable output protect control. Output PWM directly + * + APT_OUT_CTRL_ACTION_LOW -- Output low level + * + APT_OUT_CTRL_ACTION_HIGH -- Output high level + * + APT_OUT_CTRL_ACTION_HOLD -- Hold the current output state + * + APT_OUT_CTRL_ACTION_TOGGLE -- Toggle the current output state + * + APT_OUT_CTRL_ACTION_HIGH_Z -- High-impedance output + */ +typedef enum { + APT_OUT_CTRL_ACTION_DISABLE = 0x00000000U, + APT_OUT_CTRL_ACTION_LOW = 0x00000001U, + APT_OUT_CTRL_ACTION_HIGH = 0x00000002U, + APT_OUT_CTRL_ACTION_HOLD = 0x00000003U, + APT_OUT_CTRL_ACTION_TOGGLE = 0x00000004U, + APT_OUT_CTRL_ACTION_HIGH_Z = 0x00000005U, +} APT_OutCtrlAction; + +/** + * @brief Event latch clear mode of cycle-by-cycle output control mode. + */ +typedef enum { + APT_CLEAR_CBC_ON_CNTR_ZERO = 0x00000001U, + APT_CLEAR_CBC_ON_CNTR_PERIOD = 0x00000002U, + APT_CLEAR_CBC_ON_CNTR_ZERO_PERIOD = 0x00000003U, +} APT_CBCClearMode; + +/** + * @brief Source of timer interrupt. + */ +typedef enum { + APT_INT_SRC_CNTR_DISABLE = 0x00000000U, + APT_INT_SRC_CNTR_ZERO = 0x00000001U, + APT_INT_SRC_CNTR_PERIOD = 0x00000002U, + APT_INT_SRC_CNTR_ZERO_PERIOD = 0x00000003U, + APT_INT_SRC_CNTR_CMPA_UP = 0x00000004U, + APT_INT_SRC_CNTR_CMPA_DOWN = 0x00000005U, + APT_INT_SRC_CNTR_CMPB_UP = 0x00000006U, + APT_INT_SRC_CNTR_CMPB_DOWN = 0x00000007U, + APT_INT_SRC_CNTR_CMPC_UP = 0x00000008U, + APT_INT_SRC_CNTR_CMPC_DOWN = 0x00000009U, + APT_INT_SRC_CNTR_CMPD_UP = 0x0000000AU, + APT_INT_SRC_CNTR_CMPD_DOWN = 0x0000000BU, +} APT_TimerInterruptSrc; + +/** + * @brief ADC trigger channels. + */ +typedef enum { + APT_ADC_CONVERSION_START_A = 0x00000001U, + APT_ADC_CONVERSION_START_B = 0x00000002U, +} APT_ADCTriggerChannel; + +/** + * @brief Source of ADC trigger channels. + */ +typedef enum { + APT_CS_SRC_COMBINE_EVENT_A1 = 0x00000000U, + APT_CS_SRC_CNTR_ZERO = 0x00000001U, + APT_CS_SRC_CNTR_PERIOD = 0x00000002U, + APT_CS_SRC_CNTR_ZERO_PERIOD = 0x00000003U, + APT_CS_SRC_CNTR_CMPA_UP = 0x00000004U, + APT_CS_SRC_CNTR_CMPA_DOWN = 0x00000005U, + APT_CS_SRC_CNTR_CMPB_UP = 0x00000006U, + APT_CS_SRC_CNTR_CMPB_DOWN = 0x00000007U, + APT_CS_SRC_CNTR_CMPC_UP = 0x00000008U, + APT_CS_SRC_CNTR_CMPC_DOWN = 0x00000009U, + APT_CS_SRC_CNTR_CMPD_UP = 0x0000000AU, + APT_CS_SRC_CNTR_CMPD_DOWN = 0x0000000BU, +} APT_ADCTriggerSource; + +/** + * @brief DMA request source of ADC Converter Start submodule. + */ +typedef enum { + APT_CS_DMA_REQ_SRC_DISABLE = 0x00000000U, + APT_CS_DMA_REQ_SRC_CHANNEL_A = 0x00000001U, + APT_CS_DMA_REQ_SRC_CHANNEL_B = 0x00000002U, +} APT_ADCTrgDMAReqSrc; + +/** + * @brief DMA request type of ADC Converter Start submodule. + */ +typedef enum { + APT_CS_DMA_SINGLE_REQUEST = 0x00000000U, + APT_CS_DMA_BURST_REQUEST = 0x00000002U, +} APT_ADCTrgDMAReqType; + +/** + * @brief Polarity of the events of Event Management submodule. + * @details Polarity: + * + APT_EM_EVENT_POLARITY_NOT_INVERT -- High active. + * + APT_EM_EVENT_POLARITY_INVERT -- Low active. + * + APT_EM_EVENT_POLARITY_FORCE_LOW -- Force event to low level. + * + APT_EM_EVENT_POLARITY_FORCE_HIGH -- Force event to high level. + */ +typedef enum { + APT_EM_EVENT_POLARITY_NOT_INVERT = 0x00000000U, + APT_EM_EVENT_POLARITY_INVERT = 0x00000001U, + APT_EM_EVENT_POLARITY_FORCE_LOW = 0x00000002U, + APT_EM_EVENT_POLARITY_FORCE_HIGH = 0x00000003U, +} APT_EMEventPolarity; + +/** + * @brief GPIO events and system events of Event Management submodule. + * The enumeration values are the register bit field offset of the corresponding GPIO/system events. + */ +typedef enum { + APT_EM_GPIO_EVENT_1 = 0U, + APT_EM_GPIO_EVENT_2 = 2U, + APT_EM_GPIO_EVENT_3 = 4U, + APT_EM_GPIO_EVENT_4 = 6U, + APT_EM_GPIO_EVENT_5 = 8U, + APT_EM_SYSTEM_EVENT_1 = 16U, + APT_EM_SYSTEM_EVENT_2 = 18U, + APT_EM_SYSTEM_EVENT_3 = 20U, +} APT_EMIOSysEvent; + +/** + * @brief Multiplexing events of Event Management submodule. + * The enumeration values are the register bit field offset of the corresponding multiplexing events. + */ +typedef enum { + APT_EM_MP_EVENT_1 = 0U, + APT_EM_MP_EVENT_2 = 2U, + APT_EM_MP_EVENT_3 = 4U, + APT_EM_MP_EVENT_4 = 6U, + APT_EM_MP_EVENT_5 = 8U, + APT_EM_MP_EVENT_6 = 10U, +} APT_EMMuxEvent; + +/** + * @brief Event Module of Event Management submodule. + */ +typedef enum { + APT_EM_MODULE_A = 0x00000000U, + APT_EM_MODULE_B = 0x00000001U, +} APT_EMGroup; + +/** + * @brief Group of combine event source input. + */ +typedef enum { + APT_EM_COMBINE_SRC_GRP_A1 = 0x00000000U, + APT_EM_COMBINE_SRC_GRP_A2 = 0x00000001U, + APT_EM_COMBINE_SRC_GRP_B1 = 0x00000002U, + APT_EM_COMBINE_SRC_GRP_B2 = 0x00000003U, +} APT_EMCombineEvtSrcGrp; + +/** + * @brief Source of combine events A1, A2, B1, B2. + */ +typedef enum { + APT_EM_COMBINE_SRC_EVT_1 = 0x00000000U, + APT_EM_COMBINE_SRC_EVT_2 = 0x00000001U, + APT_EM_COMBINE_SRC_EVT_3 = 0x00000002U, + APT_EM_COMBINE_SRC_EVT_MP_1 = 0x00000003U, + APT_EM_COMBINE_SRC_EVT_MP_2 = 0x00000004U, + APT_EM_COMBINE_SRC_EVT_MP_3 = 0x00000005U, + APT_EM_COMBINE_SRC_EVT_MP_4 = 0x00000006U, + APT_EM_COMBINE_SRC_EVT_MP_5 = 0x00000007U, + APT_EM_COMBINE_SRC_EVT_MP_6 = 0x00000008U, + APT_EM_COMBINE_SRC_ALL_EVENT_OR = 0x0000000FU, /* based on EM_AOR_EN/EM_BOR_EN */ +} APT_EMCombineEvtSrc; + +/** + * @brief Combine events of Event Management submodule. + */ +typedef enum { + APT_EM_COMBINE_EVENT_A1 = 0x00000000U, + APT_EM_COMBINE_EVENT_A2 = 0x00000001U, + APT_EM_COMBINE_EVENT_B1 = 0x00000002U, + APT_EM_COMBINE_EVENT_B2 = 0x00000003U, +} APT_EMCombineEvent; + +/** + * @brief Combine Mode of combine events A1, A2, B1, B2. + * @details combine mode: + * + The combine result is set output to low level + * + The combine result is qual to event 1 + * + The combine result is the logical AND of group event 1 high level and group event 2 low level + * + The combine result is the logical AND of group event 1 high level and group event 2 low level + * + The combine result is the logical AND of group event 1 high level and group event 2 high level + * + The combine result is the logical AND of group event 1 low level and group event 2 low level + */ +typedef enum { + APT_EM_COMBINE_LOW_LEVEL = 0x00000000U, + APT_EM_COMBINE_EVT1 = 0x00000001U, + APT_EM_COMBINE_EVT1_H_AND_EVT2_L = 0x00000002U, + APT_EM_COMBINE_EVT1_H_AND_EVT2_H = 0x00000003U, + APT_EM_COMBINE_EVT1_L_AND_EVT2_H = 0x00000004U, + APT_EM_COMBINE_EVT2 = 0x00000005U, +} APT_EMCombineEvtMode; + +/** + * @brief Output type of combine events. + * @details Output type: + * +APT_EM_COMBINE_EVENT_OUT_ORIG_SIGNAL -- The source of combine event is unfiltered + * +APT_EM_COMBINE_EVENT_OUT_FILT_SIGNAL -- The source of combine event is filtered + */ +typedef enum { + APT_EM_COMBINE_EVENT_OUT_ORIG_SIGNAL = 0x00000000U, + APT_EM_COMBINE_EVENT_OUT_FILT_SIGNAL = 0x00000001U, +} APT_EMCombineEventOut; + +/** + * @brief Polarity of mask window. + */ +typedef enum { + APT_BLANK_EVENT_INSIDE_MASK_WIN = 0x00000000U, + APT_BLANK_EVENT_OUTSIDE_MASK_WIN = 0x00000001U, +} APT_MaskWinPolarity; + +/** + * @brief Reset mode of mask window and count capture. + */ +typedef enum { + APT_RESET_MASK_WIN_DISABLE = 0x00000000U, + APT_RESET_MASK_WIN_CNTR_ZERO = 0x00000001U, + APT_RESET_MASK_WIN_CNTR_PERIOD = 0x00000002U, + APT_RESET_MASK_WIN_CNTR_ZERO_PERIOD = 0x00000003U, +} APT_MaskWinResetMode; + +/** + * @brief Clock source of valley capture. + */ +typedef enum { + APT_VALLY_CAP_USE_MAIN_CLOCK = 0x00000000U, + APT_VALLEY_CAP_USE_DIVIDER_CLOCK = 0x00000001U, +} APT_ValleyCapClkMode; + +/** + * @brief Trigger source of valley capture. + */ +typedef enum { + APT_VALLEY_CAP_SRC_DISABLE = 0x00000000U, + APT_VALLEY_CAP_SRC_CNTR_ZERO = 0x00000001U, + APT_VALLEY_CAP_SRC_CNTR_PERIOD = 0x00000002U, + APT_VALLEY_CAP_SRC_CNTR_ZERO_PERIOD = 0x00000003U, + APT_VALLEY_CAP_SRC_COMBINE_EVENT_A1 = 0x00000004U, + APT_VALLEY_CAP_SRC_COMBINE_EVENT_A2 = 0x00000005U, + APT_VALLEY_CAP_SRC_COMBINE_EVENT_B1 = 0x00000006U, + APT_VALLEY_CAP_SRC_COMBINE_EVENT_B2 = 0x00000007U, +} APT_ValleyCapRstType; + +/** + * @brief Edge type of valley capture. + */ +typedef enum { + APT_VALLEY_CAP_RISING_EDGE = 0x00000000U, + APT_VALLEY_CAP_FALLING_EDGE = 0x00000001U, +} APT_ValleyCapEdgeType; + +/** + * @brief Delay calibration of valley capture. + * @details Delay calibration: + * + APT_VCAP_SW_DELAY -- Delay value = software delay value + * + APT_VCAP_VCNT_DELAY_DIVIDE_1_SW_DELAY -- Delay value = capture count value + software delay value + * + APT_VCAP_VCNT_DELAY_DIVIDE_2_SW_DELAY -- Delay value = capture count value / 2 + software delay value + * + APT_VCAP_VCNT_DELAY_DIVIDE_4_SW_DELAY -- Delay value = capture count value / 4 + software delay value + * + APT_VCAP_VCNT_DELAY_DIVIDE_8_SW_DELAY -- Delay value = capture count value / 8 + software delay value + * + APT_VCAP_VCNT_DELAY_DIVIDE_16_SW_DELAY -- Delay value = capture count value / 16 + software delay value + * + APT_VCAP_VCNT_DELAY_DIVIDE_32_SW_DELAY -- Delay value = capture count value / 32 + software delay value + */ +typedef enum { + APT_VCAP_SW_DELAY = 0x00000000U, + APT_VCAP_VCNT_DELAY_DIVIDE_1_SW_DELAY = 0x00000001U, + APT_VCAP_VCNT_DELAY_DIVIDE_2_SW_DELAY = 0x00000002U, + APT_VCAP_VCNT_DELAY_DIVIDE_4_SW_DELAY = 0x00000003U, + APT_VCAP_VCNT_DELAY_DIVIDE_8_SW_DELAY = 0x00000004U, + APT_VCAP_VCNT_DELAY_DIVIDE_16_SW_DELAY = 0x00000005U, + APT_VCAP_VCNT_DELAY_DIVIDE_32_SW_DELAY = 0x00000006U, +} APT_ValleyDelayMode; + +/** + * @brief Start and stop edge of valley capture. + */ +typedef enum { + APT_VALLEY_COUNT_START_EDGE = 0x00000000U, + APT_VALLEY_COUNT_STOP_EDGE = 0x00000001U, +} APT_ValleyCountEdge; + +/** + * @brief Edge filter mode of Event Management submodule. + */ +typedef enum { + APT_EM_EDGEFILTER_MODE_RISING = 0x00000000U, + APT_EM_EDGEFILTER_MODE_FALLING = 0x00000002U, + APT_EM_EDGEFILTER_MODE_BOTH = 0x00000003U, +} APT_EMEdgeFilterMode; + +/** + * @brief Sync-in source of slave APT module. + */ +typedef enum { + APT_SYNCIN_SRC_APT0_SYNCOUT = 0x00000000U, + APT_SYNCIN_SRC_APT1_SYNCOUT = 0x00000001U, + APT_SYNCIN_SRC_APT2_SYNCOUT = 0x00000002U, + APT_SYNCIN_SRC_APT3_SYNCOUT = 0x00000003U, + APT_SYNCIN_SRC_APT4_SYNCOUT = 0x00000004U, + APT_SYNCIN_SRC_APT5_SYNCOUT = 0x00000005U, + APT_SYNCIN_SRC_APT6_SYNCOUT = 0x00000006U, + APT_SYNCIN_SRC_APT7_SYNCOUT = 0x00000007U, + APT_SYNCIN_SRC_APT8_SYNCOUT = 0x00000008U, + APT_SYNCIN_SRC_CAPM0_SYNCOUT = 0x00000009U, + APT_SYNCIN_SRC_CAPM1_SYNCOUT = 0x0000000AU, + APT_SYNCIN_SRC_CAPM2_SYNCOUT = 0x0000000BU, + APT_SYNCIN_SRC_GPIO_EVENT_4 = 0x0000000CU, + APT_SYNCIN_SRC_GPIO_EVENT_5 = 0x0000000DU, + APT_SYNCIN_SRC_DISABLE = 0x0000000EU, +} APT_SyncInSrc; + +/** + * @brief Sync-out mode of master APT module. + * @details Sync-out mode: + * + APT_SYNCOUT_ONE_SHOT_MODE -- One-Shot synchronization mode + * + APT_SYNCOUT_MULTIPLE_MODE -- Multiple synchronization mode + */ +typedef enum { + APT_SYNCOUT_ONE_SHOT_MODE = 0x00000000U, + APT_SYNCOUT_MULTIPLE_MODE = 0x00000001U, +} APT_SyncOutMode; + +/** + * @brief Selection of sync-out latch when using one-shot sync-out mode. + * @details Sync-out latch: + * + APT_SYNCOUT_LATCH_SET_ON_SW_FORCE -- Select rg_latset_otsyn as the latch set condition + * + APT_SYNCOUT_LATCH_SET_ON_GLB_LOAD -- Select rg_latset_otgld as the latch set condition + */ +typedef enum { + APT_SYNCOUT_LATCH_SET_ON_SW_FORCE = 0x00000000U, + APT_SYNCOUT_LATCH_SET_ON_GLB_LOAD = 0x00000001U, +} APT_SyncOutLatSetSel; + +/** + * @brief Source of peripheral synchronization. + */ +typedef enum { + APT_PER_SYNCOUT_SRC_DISABLE = 0x00000000U, + APT_PER_SYNCOUT_SRC_CNTR_ZERO = 0x00000001U, + APT_PER_SYNCOUT_SRC_CNTR_PERIOD = 0x00000002U, + APT_PER_SYNCOUT_SRC_CNTR_ZERO_PERIOD = 0x00000003U, + APT_PER_SYNCOUT_SRC_CNTR_CMPC_UP = 0x00000004U, + APT_PER_SYNCOUT_SRC_CNTR_CMPC_DOWN = 0x00000005U, + APT_PER_SYNCOUT_SRC_CNTR_CMPD_UP = 0x00000006U, + APT_PER_SYNCOUT_SRC_CNTR_CMPD_DOWN = 0x00000007U, +} APT_PeriphSyncOutSrc; + +/** + * @brief Global buffer load mode. + */ +typedef enum { + APT_GLB_LOAD_ONE_SHOT_MODE = 0x00000000U, + APT_GLB_LOAD_MULTIPLE_MODE = 0x00000001U, +} APT_GlobalLoadMode; + +/** + * @brief The buffer of the registers that support buffer register. + */ +typedef enum { + APT_REG_BUFFER_TC_PRD = 0x00000001U, + APT_REG_BUFFER_TC_REFA = 0x00000002U, + APT_REG_BUFFER_TC_REFB = 0x00000004U, + APT_REG_BUFFER_TC_REFC = 0x00000008U, + APT_REG_BUFFER_TC_REFD = 0x00000010U, + APT_REG_BUFFER_PG_ACT_A = 0x00000040U, + APT_REG_BUFFER_PG_ACT_B = 0x00000080U, + APT_REG_BUFFER_PG_OUT_FRC = 0x00000100U, + APT_REG_BUFFER_DG_RED = 0x00000400U, + APT_REG_BUFFER_DG_FED = 0x00000800U, + APT_REG_BUFFER_DG_CFG = 0x00001000U, +} APT_RegBuffer; + +/** + * @brief Software force events. + */ +typedef enum { + APT_FORCE_EVENT_COUNTER_SYNC = 0x00000001U, + APT_FORCE_EVENT_SYNCOUT = 0x00000010U, + APT_FORCE_EVENT_SYNC_PERIPH = 0x00000100U, + APT_FORCE_EVENT_GLOBAL_LOAD = 0x00001000U, + APT_FORCE_EVENT_VALLEY_CAP_RST = 0x00010000U, + APT_FORCE_EVENT_ADC_START_A = 0x00100000U, + APT_FORCE_EVENT_ADC_START_B = 0x00200000U, + APT_FORCE_EVENT_TIMER_INTERRUPT = 0x01000000U, + APT_FORCE_EVENT_PWM_ACTION_BUF_LOAD = 0x10000000U, +} APT_ForceEvtType; + +/** + * @brief Software force events. + * @details Reference point selection. + * + APT_REFERENCE_DOTA -- Select referece dot A as action trigger point. + * + APT_REFERENCE_DOTB -- Select referece dot B as action trigger point. + * + APT_REFERENCE_DOTC -- Select referece dot C as action trigger point. + * + APT_REFERENCE_DOTD -- Select referece dot D as action trigger point. + */ +typedef enum { + APT_REFERENCE_DOTA = 0x00000000U, + APT_REFERENCE_DOTB = 0x00000001U, + APT_REFERENCE_DOTC = 0x00000002U, + APT_REFERENCE_DOTD = 0x00000003U, +} APT_RefDotSelect; + +/** + * @brief Configure action point parameters. + * @details Property of the action point. + * + refDotValue -- the action point value. + * + refDotDivValue -- frequency division value of the action point. + * + pwmChannel -- number of channels for which the action point needs to be changed. @ref APT_PWMChannel + * + actionEvent -- action event configure of reference point. @ref APT_PWMActionEvent + * + action -- triggle action of reference point. @ref APT_PWMAction + * @note: the value of Reference Point must be less than or equal to the value of period. + */ +typedef struct { + unsigned int refDotValue; + unsigned int refDotDivValue; + APT_PWMChannel pwmChannel; /* PWM channel selection. */ + APT_PWMActionEvent actionEvent; /* Point triggle action event. */ + APT_PWMAction action; /* Point action. */ +} APT_RefDotParameters; + +/** + * @} + */ + +/** + * @defgroup APT_REG_Definition APT Register Structure. + * @brief APT Register Structure Definition. + * @{ + */ +typedef union { + unsigned int reg; + struct { + unsigned int sub_version : 4; /**< ip subversion */ + unsigned int main_version : 4; /**< ip main verison */ + unsigned int reserved0 : 24; + } BIT; +} volatile VER_INFO_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_cnt_mode : 2; /**< timer work mode */ + unsigned int reserved0 : 14; + unsigned int rg_div_fac : 12; /**< divider factor */ + unsigned int rg_emu_stop : 2; /**< emulation stop mode */ + unsigned int reserved1 : 2; + } BIT; +} volatile TC_MODE_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_cnt_phs : 16; /**< timer's phase */ + unsigned int rg_div_phs : 12; /**< divider's phase */ + unsigned int reserved0 : 3; + unsigned int rg_cnt_dir : 1; /**< timer count direction */ + } BIT; +} volatile TC_PHS_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_cnt_ovrid : 16; /**< timer count init value */ + unsigned int rg_div_ovrid : 12; /**< divider init value */ + unsigned int reserved0 : 3; + unsigned int rg_cnt_ovrid_en : 1; /**< timer and divider init enable */ + } BIT; +} volatile TC_OVRID_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_cnt_prd : 16; /* count period */ + unsigned int reserved0 : 16; + } BIT; +} volatile TC_PRD_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_cnt_refah : 16; /* reference A counter value */ + unsigned int rg_cnt_refal : 12; /* reference A divider value */ + unsigned int reserved0 : 4; + } BIT; +} volatile TC_REFA_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_cnt_refbh : 16; /* reference B counter value */ + unsigned int rg_cnt_refbl : 12; /* reference B divider value */ + unsigned int reserved0 : 4; + } BIT; +} volatile TC_REFB_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_cnt_refch : 16; /* reference C counter value */ + unsigned int rg_cnt_refcl : 12; /* reference C divider value */ + unsigned int reserved0 : 4; + } BIT; +} volatile TC_REFC_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_cnt_refdh : 16; /* reference D counter value */ + unsigned int rg_cnt_refdl : 12; /* reference D divider value */ + unsigned int reserved0 : 4; + } BIT; +} volatile TC_REFD_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_prd_buf_en : 1; /**< period buffer enable */ + unsigned int rg_prd_gld_en : 1; /**< period global buffer enable */ + unsigned int reserved0 : 2; + unsigned int rg_refa_buf_en : 1; /**< reference A buffer enable */ + unsigned int rg_refa_gld_en : 1; /**< reference A global buffer enable */ + unsigned int rg_refb_buf_en : 1; /**< reference B buffer enable */ + unsigned int rg_refb_gld_en : 1; /**< reference B global buffer enable */ + unsigned int rg_refc_buf_en : 1; /**< reference C buffer enable */ + unsigned int rg_refc_gld_en : 1; /**< reference C global buffer enable */ + unsigned int rg_refd_buf_en : 1; /**< reference D buffer enable */ + unsigned int rg_refd_gld_en : 1; /**< reference D global buffer enable */ + unsigned int reserved1 : 20; + } BIT; +} volatile TC_BUF_EN_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_prd_ld_zroen : 1; /**< period value register load at zero */ + unsigned int reserved0 : 1; + unsigned int rg_prd_ld_a1en : 1; /**< period value load at evt_a1 */ + unsigned int rg_prd_ld_b1en : 1; /**< period value load at evt_b1 */ + unsigned int rg_prd_ld_synen : 1; /**< period value load at sync signal input */ + unsigned int reserved1 : 27; + } BIT; +} volatile TC_PRD_LOAD_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_refa_ld_zroen : 1; /**< reference A value load at zero */ + unsigned int rg_refa_ld_prden : 1; /**< reference A value load at period */ + unsigned int rg_refa_ld_a1en : 1; /**< reference A value load at evt_a1 */ + unsigned int rg_refa_ld_b1en : 1; /**< reference A value load at evt_b1 */ + unsigned int rg_refa_ld_synen : 1; /**< reference A value load at sync signal input */ + unsigned int reserved0 : 3; + unsigned int rg_refb_ld_zroen : 1; /**< reference B value load at zero */ + unsigned int rg_refb_ld_prden : 1; /**< reference B value load at period */ + unsigned int rg_refb_ld_a1en : 1; /**< reference B value load at evt_a1 */ + unsigned int rg_refb_ld_b1en : 1; /**< reference B value load at evt_b1 */ + unsigned int rg_refb_ld_synen : 1; /**< reference B value load at sync signal input */ + unsigned int reserved1 : 3; + unsigned int rg_refc_ld_zroen : 1; /**< reference C value load at zero */ + unsigned int rg_refc_ld_prden : 1; /**< reference C value load at period */ + unsigned int rg_refc_ld_a1en : 1; /**< reference C value load at evt_a1 */ + unsigned int rg_refc_ld_b1en : 1; /**< reference C value load at evt_b1 */ + unsigned int rg_refc_ld_synen : 1; /**< reference C value load at sync signal input */ + unsigned int reserved2 : 3; + unsigned int rg_refd_ld_zroen : 1; /**< reference D value load at zero */ + unsigned int rg_refd_ld_prden : 1; /**< reference D value load at period */ + unsigned int rg_refd_ld_a1en : 1; /**< reference D value load at evt_a1 */ + unsigned int rg_refd_ld_b1en : 1; /**< reference D value load at evt_b1 */ + unsigned int rg_refd_ld_synen : 1; /**< reference D value load at sync signal input */ + unsigned int reserved3 : 3; + } BIT; +} volatile TC_REF_LOAD_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int ro_cnt_val : 16; /**< counter value */ + unsigned int ro_div_cnt : 12; /**< divider value */ + unsigned int reserved0 : 3; + unsigned int ro_cnt_dir : 1; /**< count direction */ + } BIT; +} volatile TC_STS_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_pga_act_zro : 2; /**< PG channel A action at zero */ + unsigned int rg_pga_act_prd : 2; /**< PG channel A action at period */ + unsigned int rg_pga_act_refa_inc : 2; /**< PG channel A action at reference A increase */ + unsigned int rg_pga_act_refa_dec : 2; /**< PG channel A action at reference A decrease */ + unsigned int rg_pga_act_refb_inc : 2; /**< PG channel A action at reference B increase */ + unsigned int rg_pga_act_refb_dec : 2; /**< PG channel A action at reference B decrease */ + unsigned int rg_pga_act_refc_inc : 2; /**< PG channel A action at reference C increase */ + unsigned int rg_pga_act_refc_dec : 2; /**< PG channel A action at reference C decrease */ + unsigned int rg_pga_act_refd_inc : 2; /**< PG channel A action at reference D increase */ + unsigned int rg_pga_act_refd_dec : 2; /**< PG channel A action at reference D decrease */ + unsigned int rg_pga_act_evtc1_inc : 2; /**< PG channel A action at evt_c1 increase */ + unsigned int rg_pga_act_evtc1_dec : 2; /**< PG channel A action at evt_c1 decrease */ + unsigned int rg_pga_act_evtc2_inc : 2; /**< PG channel A action at evt_c2 increase */ + unsigned int rg_pga_act_evtc2_dec : 2; /**< PG channel A action at evt_c2 decrease */ + unsigned int reserved0 : 4; + } BIT; +} volatile PG_ACT_A_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_pgb_act_zro : 2; /**< PG channel A action at zero */ + unsigned int rg_pgb_act_prd : 2; /**< PG channel A action at period */ + unsigned int rg_pgb_act_refa_inc : 2; /**< PG channel A action at reference A increase */ + unsigned int rg_pgb_act_refa_dec : 2; /**< PG channel A action at reference A decrease */ + unsigned int rg_pgb_act_refb_inc : 2; /**< PG channel A action at reference B increase */ + unsigned int rg_pgb_act_refb_dec : 2; /**< PG channel A action at reference B decrease */ + unsigned int rg_pgb_act_refc_inc : 2; /**< PG channel A action at reference C increase */ + unsigned int rg_pgb_act_refc_dec : 2; /**< PG channel A action at reference C decrease */ + unsigned int rg_pgb_act_refd_inc : 2; /**< PG channel A action at reference D increase */ + unsigned int rg_pgb_act_refd_dec : 2; /**< PG channel A action at reference D decrease */ + unsigned int rg_pgb_act_evtc1_inc : 2; /**< PG channel A action at evt_c1 increase */ + unsigned int rg_pgb_act_evtc1_dec : 2; /**< PG channel A action at evt_c1 decrease */ + unsigned int rg_pgb_act_evtc2_inc : 2; /**< PG channel A action at evt_c2 increase */ + unsigned int rg_pgb_act_evtc2_dec : 2; /**< PG channel A action at evt_c2 decrease */ + unsigned int reserved0 : 4; + } BIT; +} volatile PG_ACT_B_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_pga_act_evt_frc : 2; /**< channel A force action select */ + unsigned int rg_pga_evt_frc : 1; /**< enable a force action at channel A */ + unsigned int reserved0 : 1; + unsigned int rg_pgb_act_evt_frc : 2; /**< channel A force action select */ + unsigned int rg_pgb_evt_frc : 1; /**< enable a force action at channel A */ + unsigned int reserved1 : 25; + } BIT; +} volatile PG_ACT_FRC_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_pga_frc_act : 2; /**< channel A force output action select */ + unsigned int rg_pga_frc_en : 1; /**< channel A force output action enable */ + unsigned int reserved0 : 1; + unsigned int rg_pgb_frc_act : 2; /**< channel A force output action select */ + unsigned int rg_pgb_frc_en : 1; /**< channel A force output action enable */ + unsigned int reserved1 : 25; + } BIT; +} volatile PG_OUT_FRC_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_acta_buf_en : 1; /**< channel A action value buffer enable */ + unsigned int rg_acta_gld_en : 1; /**< channel A action value global buffer enable */ + unsigned int rg_actb_buf_en : 1; /**< channel B action value buffer enable */ + unsigned int rg_actb_gld_en : 1; /**< channel B action value global buffer enable */ + unsigned int rg_frc_buf_en : 1; /**< force output config buffer enable */ + unsigned int rg_frc_gld_en : 1; /**< force output config global buffer enable */ + unsigned int reserved0 : 26; + } BIT; +} volatile PG_BUF_EN_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_pga_actld_zroen : 1; /**< enable PG channel A action value independent load at zero */ + unsigned int rg_pga_actld_prden : 1; /**< enable PG channel A action value independent load at period */ + unsigned int rg_pga_actld_a1en : 1; /**< enable PG channel A action value independent load at evt_a1 */ + unsigned int rg_pga_actld_b1en : 1; /**< enable PG channel A action value independent load at evt_b1 */ + unsigned int rg_pga_actld_synen : 1; /**< enable PG channel A action value independent load at sync signal */ + unsigned int reserved0 : 3; + unsigned int rg_pgb_actld_zroen : 1; /**< enable PG channel B action value independent load at zero */ + unsigned int rg_pgb_actld_prden : 1; /**< enable PG channel B action value independent load at period */ + unsigned int rg_pgb_actld_a1en : 1; /**< enable PG channel B action value independent load at evt_a1 */ + unsigned int rg_pgb_actld_b1en : 1; /**< enable PG channel B action value independent load at evt_b1 */ + unsigned int rg_pgb_actld_synen : 1; /**< enable PG channel B action value independent load at sync signal */ + unsigned int reserved1 : 3; + unsigned int rg_pg_frcld_zroen : 1; /**< enable force action config value independent load at zero */ + unsigned int rg_pg_frcld_prden : 1; /**< enable force action config value independent load at period */ + unsigned int reserved2 : 2; + unsigned int rg_pg_frcld_synen : 1; /**< enable force action config value independent load at sync signal */ + unsigned int reserved3 : 3; + unsigned int reserved4 : 8; + } BIT; +} volatile PG_ACT_LD_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_pga_evtc1_sel : 4; /**< pga_evtc1 source select */ + unsigned int rg_pga_evtc2_sel : 4; /**< pga_evtc2 source select */ + unsigned int rg_pgb_evtc1_sel : 4; /**< pgb_evtc1 source select */ + unsigned int rg_pgb_evtc2_sel : 4; /**< pgb_evtc2 source select */ + unsigned int reserved0 : 16; + } BIT; +} volatile PG_EVTC_SEL_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_dg_red : 16; /**< deadband time at rising edge */ + unsigned int reserved0 : 16; + } BIT; +} volatile DG_RED_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_dg_fed : 16; /**< deadband timer at falling edge */ + unsigned int reserved0 : 16; + } BIT; +} volatile DG_FED_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_dg_red_isel : 2; /**< rising edge delay source input select */ + unsigned int rg_dg_fed_isel : 2; /**< falling edge delay source input select */ + unsigned int rg_dg_red_osel : 2; /**< rising edge delay polarity select */ + unsigned int rg_dg_fed_osel : 2; /**< falling edge delay polarity select */ + unsigned int rg_dga_osel : 1; /**< dga output waveform swap select */ + unsigned int rg_dgb_osel : 1; /**< dgb output waveform swap select */ + unsigned int reserved0 : 22; + } BIT; +} volatile DG_CFG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_red_buf_en : 1; /**< rising edge delay value buffer enable */ + unsigned int rg_red_gld_en : 1; /**< rising edge delay value global buffer enable */ + unsigned int rg_fed_buf_en : 1; /**< falling edge delay value buffer enable */ + unsigned int rg_fed_gld_en : 1; /**< falling edge delay value global buffer enable */ + unsigned int rg_cfg_buf_en : 1; /**< deadband config buffer enable */ + unsigned int rg_cfg_gld_en : 1; /**< deadband config global enable */ + unsigned int reserved0 : 26; + } BIT; +} volatile DG_BUF_EN_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_red_ld_zroen : 1; /**< rising edge delay value load independent at zero */ + unsigned int rg_red_ld_prden : 1; /**< rising edge delay value load independent at period */ + unsigned int reserved0 : 6; + unsigned int rg_fed_ld_zroen : 1; /**< falling edge delay value load independent at zero */ + unsigned int rg_fed_ld_prden : 1; /**< falling edge delay value load independent at period */ + unsigned int reserved1 : 6; + unsigned int rg_cfg_ld_zroen : 1; /**< deadband config register value load independent at zero */ + unsigned int rg_cfg_ld_prden : 1; /**< deadband config register value load independent at period */ + unsigned int reserved2 : 14; + } BIT; +} volatile DG_BUF_LOAD_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_oc_en_evt1 : 1; /**< evtio1 output control enable */ + unsigned int rg_oc_en_evt2 : 1; /**< evtio2 output control enable */ + unsigned int rg_oc_en_evt3 : 1; /**< evtio3 output control enable */ + unsigned int reserved0 : 1; + unsigned int rg_oc_en_evts1 : 1; /**< evts1 output control enable */ + unsigned int rg_oc_en_evts2 : 1; /**< evts2 output control enable */ + unsigned int rg_oc_en_evts3 : 1; /**< evts3 output control enable */ + unsigned int reserved1 : 1; + unsigned int rg_oc_en_evta1 : 1; /**< evta1 output control enable */ + unsigned int rg_oc_en_evta2 : 1; /**< evta2 output control enable */ + unsigned int rg_oc_en_evtb1 : 1; /**< evtb1 output control enable */ + unsigned int rg_oc_en_evtb2 : 1; /**< evtb2 output control enable */ + unsigned int reserved2 : 4; + unsigned int rg_oc_mode_evt1 : 1; /**< evtio1 output mode select */ + unsigned int rg_oc_mode_evt2 : 1; /**< evtio2 output mode select */ + unsigned int rg_oc_mode_evt3 : 1; /**< evtio3 output mode select */ + unsigned int reserved3 : 1; + unsigned int rg_oc_mode_evts1 : 1; /**< evts1 output mode select */ + unsigned int rg_oc_mode_evts2 : 1; /**< evts2 output mode select */ + unsigned int rg_oc_mode_evts3 : 1; /**< evts3 output mode select */ + unsigned int reserved4 : 1; + unsigned int rg_oc_mode_evta1 : 1; /**< evta1 output mode select */ + unsigned int rg_oc_mode_evta2 : 1; /**< evta2 output mode select */ + unsigned int rg_oc_mode_evtb1 : 1; /**< evtb1 output mode select */ + unsigned int rg_oc_mode_evtb2 : 1; /**< evtb2 output mode select */ + unsigned int reserved5 : 4; + } BIT; +} volatile OC_MODE_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_oc_laten_evt1 : 1; /**< output control evtio1 latch event enable */ + unsigned int rg_oc_laten_evt2 : 1; /**< output control evtio2 latch event enable */ + unsigned int rg_oc_laten_evt3 : 1; /**< output control evtio3 latch event enable */ + unsigned int reserved0 : 1; + unsigned int rg_oc_laten_evts1 : 1; /**< output control evtis1 latch event enable */ + unsigned int rg_oc_laten_evts2 : 1; /**< output control evtis2 latch event enable */ + unsigned int rg_oc_laten_evts3 : 1; /**< output control evtis3 latch event enable */ + unsigned int reserved1 : 1; + unsigned int rg_oc_laten_evta1 : 1; /**< output control evtia1 latch event enable */ + unsigned int rg_oc_laten_evta2 : 1; /**< output control evtia2 latch event enable */ + unsigned int rg_oc_laten_evtb1 : 1; /**< output control evtib1 latch event enable */ + unsigned int rg_oc_laten_evtb2 : 1; /**< output control evtib2 latch event enable */ + unsigned int reserved2 : 20; + } BIT; +} volatile OC_LAT_EN_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_oca_evtio_inc : 3; /**< channel A output control action at evtio increase */ + unsigned int rg_oca_evta1_inc : 3; /**< channel A output control action at evta1 increase */ + unsigned int rg_oca_evta2_inc : 3; /**< channel A output control action at evta2 increase */ + unsigned int rg_oca_evtb1_inc : 3; /**< channel A output control action at evtb1 increase */ + unsigned int rg_oca_evtb2_inc : 3; /**< channel A output control action at evtb2 increase */ + unsigned int reserved0 : 1; + unsigned int rg_oca_evtio_dec : 3; /**< channel A output control action at evtio decrease */ + unsigned int rg_oca_evta1_dec : 3; /**< channel A output control action at evta1 decrease */ + unsigned int rg_oca_evta2_dec : 3; /**< channel A output control action at evta2 decrease */ + unsigned int rg_oca_evtb1_dec : 3; /**< channel A output control action at evtb1 decrease */ + unsigned int rg_oca_evtb2_dec : 3; /**< channel A output control action at evtb2 decrease */ + unsigned int reserved1 : 1; + } BIT; +} volatile OC_ACT_A_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_ocb_evtio_inc : 3; /**< channel B output control action at evtio increase */ + unsigned int rg_ocb_evta1_inc : 3; /**< channel B output control action at evta1 increase */ + unsigned int rg_ocb_evta2_inc : 3; /**< channel B output control action at evta2 increase */ + unsigned int rg_ocb_evtb1_inc : 3; /**< channel B output control action at evtb1 increase */ + unsigned int rg_ocb_evtb2_inc : 3; /**< channel B output control action at evtb2 increase */ + unsigned int reserved0 : 1; + unsigned int rg_ocb_evtio_dec : 3; /**< channel B output control action at evtio decrease */ + unsigned int rg_ocb_evta1_dec : 3; /**< channel B output control action at evta1 decrease */ + unsigned int rg_ocb_evta2_dec : 3; /**< channel B output control action at evta2 decrease */ + unsigned int rg_ocb_evtb1_dec : 3; /**< channel B output control action at evtb1 decrease */ + unsigned int rg_ocb_evtb2_dec : 3; /**< channel B output control action at evtb2 decrease */ + unsigned int reserved1 : 1; + } BIT; +} volatile OC_ACT_B_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int ro_oc_flag_evt1 : 1; /**< output control evtio1 flag */ + unsigned int ro_oc_flag_evt2 : 1; /**< output control evtio2 flag */ + unsigned int ro_oc_flag_evt3 : 1; /**< output control evtio3 flag */ + unsigned int reserved0 : 1; + unsigned int ro_oc_flag_evts1 : 1; /**< output control evts1 flag */ + unsigned int ro_oc_flag_evts2 : 1; /**< output control evts2 flag */ + unsigned int ro_oc_flag_evts3 : 1; /**< output control evts3 flag */ + unsigned int reserved1 : 1; + unsigned int ro_oc_flag_evta1 : 1; /**< output control evta1 flag */ + unsigned int ro_oc_flag_evta2 : 1; /**< output control evta2 flag */ + unsigned int ro_oc_flag_evtb1 : 1; /**< output control evtb1 flag */ + unsigned int ro_oc_flag_evtb2 : 1; /**< output control evtb2 flag */ + unsigned int reserved2 : 3; + unsigned int ro_int_flag_evt : 1; /**< output control event interrupt flag */ + unsigned int rg_oc_clr_evt1 : 1; /**< output control evtio1 clear bit */ + unsigned int rg_oc_clr_evt2 : 1; /**< output control evtio2 clear bit */ + unsigned int rg_oc_clr_evt3 : 1; /**< output control evtio3 clear bit */ + unsigned int reserved3 : 1; + unsigned int rg_oc_clr_evts1 : 1; /**< output control evts1 clear bit */ + unsigned int rg_oc_clr_evts2 : 1; /**< output control evts2 clear bit */ + unsigned int rg_oc_clr_evts3 : 1; /**< output control evts3 clear bit */ + unsigned int reserved4 : 1; + unsigned int rg_oc_clr_evta1 : 1; /**< output control evta1 clear bit */ + unsigned int rg_oc_clr_evta2 : 1; /**< output control evta2 clear bit */ + unsigned int rg_oc_clr_evtb1 : 1; /**< output control evtb1 clear bit */ + unsigned int rg_oc_clr_evtb2 : 1; /**< output control evtb2 clear bit */ + unsigned int reserved5 : 3; + unsigned int rg_int_clr_evt : 1; /**< output control event interrupt clear bit */ + } BIT; +} volatile OC_EVT_FLAG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_oc_clr_zroen_evt1 : 1; /**< enable clear evtio1 at zero */ + unsigned int rg_oc_clr_zroen_evt2 : 1; /**< enable clear evtio2 at zero */ + unsigned int rg_oc_clr_zroen_evt3 : 1; /**< enable clear evtio3 at zero */ + unsigned int reserved0 : 1; + unsigned int rg_oc_clr_zroen_evts1 : 1; /**< enable clear evts1 at zero */ + unsigned int rg_oc_clr_zroen_evts2 : 1; /**< enable clear evts2 at zero */ + unsigned int rg_oc_clr_zroen_evts3 : 1; /**< enable clear evts3 at zero */ + unsigned int reserved1 : 1; + unsigned int rg_oc_clr_zroen_evta1 : 1; /**< enable clear evta1 at zero */ + unsigned int rg_oc_clr_zroen_evta2 : 1; /**< enable clear evta2 at zero */ + unsigned int rg_oc_clr_zroen_evtb1 : 1; /**< enable clear evtb1 at zero */ + unsigned int rg_oc_clr_zroen_evtb2 : 1; /**< enable clear evtb2 at zero */ + unsigned int reserved2 : 4; + unsigned int rg_oc_clr_prden_evt1 : 1; /**< enable clear evtio1 at period */ + unsigned int rg_oc_clr_prden_evt2 : 1; /**< enable clear evtio2 at period */ + unsigned int rg_oc_clr_prden_evt3 : 1; /**< enable clear evtio3 at period */ + unsigned int reserved3 : 1; + unsigned int rg_oc_clr_prden_evts1 : 1; /**< enable clear evts1 at period */ + unsigned int rg_oc_clr_prden_evts2 : 1; /**< enable clear evts2 at period */ + unsigned int rg_oc_clr_prden_evts3 : 1; /**< enable clear evts3 at period */ + unsigned int reserved4 : 1; + unsigned int rg_oc_clr_prden_evta1 : 1; /**< enable clear evta1 at period */ + unsigned int rg_oc_clr_prden_evta2 : 1; /**< enable clear evta2 at period */ + unsigned int rg_oc_clr_prden_evtb1 : 1; /**< enable clear evtb1 at period */ + unsigned int rg_oc_clr_prden_evtb2 : 1; /**< enable clear evtb2 at period */ + unsigned int reserved5 : 4; + } BIT; +} volatile OC_PRD_CLR_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_oc_frc_evt1 : 1; /**< force enable evtio1 event */ + unsigned int rg_oc_frc_evt2 : 1; /**< force enable evtio2 event */ + unsigned int rg_oc_frc_evt3 : 1; /**< force enable evtio3 event */ + unsigned int reserved0 : 1; + unsigned int rg_oc_frc_evts1 : 1; /**< force enable evts1 event */ + unsigned int rg_oc_frc_evts2 : 1; /**< force enable evts2 event */ + unsigned int rg_oc_frc_evts3 : 1; /**< force enable evts3 event */ + unsigned int reserved1 : 1; + unsigned int rg_oc_frc_evta1 : 1; /**< force enable evta1 event */ + unsigned int rg_oc_frc_evta2 : 1; /**< force enable evta2 event */ + unsigned int rg_oc_frc_evtb1 : 1; /**< force enable evtb1 event */ + unsigned int rg_oc_frc_evtb2 : 1; /**< force enable evtb2 event */ + unsigned int reserved2 : 20; + } BIT; +} volatile OC_FRC_EVT_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_int_en_evt1 : 1; /**< enable evtio1 intterrupt */ + unsigned int rg_int_en_evt2 : 1; /**< enable evtio2 intterrupt */ + unsigned int rg_int_en_evt3 : 1; /**< enable evtio3 intterrupt */ + unsigned int reserved0 : 1; + unsigned int rg_int_en_evts1 : 1; /**< enable evts1 intterrupt */ + unsigned int rg_int_en_evts2 : 1; /**< enable evts2 intterrupt */ + unsigned int rg_int_en_evts3 : 1; /**< enable evts3 intterrupt */ + unsigned int reserved1 : 1; + unsigned int rg_int_en_evta1 : 1; /**< enable evta1 intterrupt */ + unsigned int rg_int_en_evta2 : 1; /**< enable evta2 intterrupt */ + unsigned int rg_int_en_evtb1 : 1; /**< enable evtb1 intterrupt */ + unsigned int rg_int_en_evtb2 : 1; /**< enable evtb2 intterrupt */ + unsigned int reserved2 : 20; + } BIT; +} volatile INT_EVT_EN_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_int_en_tmr : 1; /**< enable timer interrupt */ + unsigned int reserved0 : 31; + } BIT; +} volatile INT_TMR_EN_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int ro_int_flag_tmr : 1; /**< timer interrupt clear bit */ + unsigned int reserved0 : 15; + unsigned int rg_int_clr_tmr : 1; /**< timer interrupt flag */ + unsigned int reserved1 : 15; + } BIT; +} volatile INT_TMR_FLAG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_int_tmr_sel : 4; /**< timer interrupt source select */ + unsigned int reserved0 : 28; + } BIT; +} volatile INT_TMR_SEL_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_int_prsc_prd : 4; /**< timer interrupt scale ratio */ + unsigned int reserved0 : 4; + unsigned int ro_int_prsc_cnt : 4; /**< timer interrupt scale ratio value read register */ + unsigned int reserved1 : 4; + unsigned int rg_int_prsc_phs : 4; /**< timer interrupt scale ratio phase value */ + unsigned int reserved2 : 4; + unsigned int rg_int_prsc_synen : 1; /**< timer interrupt scale ratio phase value */ + unsigned int rg_int_prsc_frc : 1; + unsigned int reserved3 : 6; + } BIT; +} volatile INT_PRSC_CFG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_csa_tmr_sel : 4; /**< timer condition to trigger adc sample through SOCA */ + unsigned int reserved0 : 12; + unsigned int rg_csa_en_cs : 1; /**< timer trigger adc sample through SOCA enable */ + unsigned int reserved1 : 15; + } BIT; +} volatile CS_TMR_SELA_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_csb_tmr_sel : 4; /**< timer condition to trigger adc sample through SOCB */ + unsigned int reserved0 : 12; + unsigned int rg_csb_en_cs : 1; /**< timer trigger adc sample through SOCB enable */ + unsigned int reserved1 : 15; + } BIT; +} volatile CS_TMR_SELB_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_csa_prsc_prd : 4; /**< trigger adc scale ratio through SOCB */ + unsigned int reserved0 : 12; + unsigned int rg_csa_prsc_phs : 4; /**< trigger adc scale ratio phase value through SOCB */ + unsigned int reserved1 : 4; + unsigned int rg_csa_prsc_synen : 1; /**< trigger adc scale ratio phase value sync enable through SOCB */ + unsigned int rg_csa_prsc_frc : 1; /**< trigger adc scale ratio phase value force enable through SOCB */ + unsigned int reserved2 : 6; + } BIT; +} volatile CS_PRSCA_CFG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_csb_prsc_prd : 4; /**< trigger adc scale ratio through SOCB */ + unsigned int reserved0 : 12; + unsigned int rg_csb_prsc_phs : 4; /**< trigger adc scale ratio phase value through SOCB */ + unsigned int reserved1 : 4; + unsigned int rg_csb_prsc_synen : 1; /**< trigger adc scale ratio phase value sync enable through SOCB */ + unsigned int rg_csb_prsc_frc : 1; /**< trigger adc scale ratio phase value force enable through SOCB */ + unsigned int reserved2 : 6; + } BIT; +} volatile CS_PRSCB_CFG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int ro_csa_flag : 1; /**< SOCA adc start sample flag */ + unsigned int ro_csb_flag : 1; /**< SOCB adc start sample flag */ + unsigned int reserved0 : 14; + unsigned int rg_csa_clr_flag : 1; /**< SOCA adc start sample flag clear bit */ + unsigned int rg_csb_clr_flag : 1; /**< SOCB adc start sample flag clear bit */ + unsigned int reserved1 : 14; + } BIT; +} volatile CS_FLAG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_dma_breq_sel : 2; /**< DMA Burst request source select */ + unsigned int rg_dma_sreq_sel : 2; /**< DMA single request source select */ + unsigned int reserved0 : 28; + } BIT; +} volatile CS_DMA_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_evtio1_psel : 2; /**< evtio1's polarity */ + unsigned int rg_evtio2_psel : 2; /**< evtio2's polarity */ + unsigned int rg_evtio3_psel : 2; /**< evtio3's polarity */ + unsigned int rg_evtio4_psel : 2; /**< evtio4's polarity */ + unsigned int rg_evtio5_psel : 2; /**< evtio5's polarity */ + unsigned int reserved0 : 6; + unsigned int rg_evtsys1_psel : 2; /**< evts1's polarity */ + unsigned int rg_evtsys2_psel : 2; /**< evts2's polarity */ + unsigned int rg_evtsys3_psel : 2; /**< evts3's polarity */ + unsigned int reserved1 : 10; + } BIT; +} volatile EM_EVTIO_PSEL_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_evtmp1_psel : 2; /**< evtmp1's polarity */ + unsigned int rg_evtmp2_psel : 2; /**< evtmp2's polarity */ + unsigned int rg_evtmp3_psel : 2; /**< evtmp3's polarity */ + unsigned int rg_evtmp4_psel : 2; /**< evtmp4's polarity */ + unsigned int rg_evtmp5_psel : 2; /**< evtmp5's polarity */ + unsigned int rg_evtmp6_psel : 2; /**< evtmp6's polarity */ + unsigned int reserved0 : 20; + } BIT; +} volatile EM_EVTMP_PSEL_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_em_a1_oren : 15; /**< group A event 1 logic OR source enable */ + unsigned int reserved0 : 1; + unsigned int rg_em_a2_oren : 15; /**< group A event 2 logic OR source enable */ + unsigned int reserved1 : 1; + } BIT; +} volatile EM_AOR_EN_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_em_b1_oren : 15; /**< group B event 1 logic OR source enable */ + unsigned int reserved0 : 1; + unsigned int rg_em_b2_oren : 15; /**< group B event 2 logic OR source enable */ + unsigned int reserved1 : 1; + } BIT; +} volatile EM_BOR_EN_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_em_a1_sel : 4; /**< group A event 1 source select */ + unsigned int rg_em_a2_sel : 4; /**< group A event 2 source select */ + unsigned int rg_em_b1_sel : 4; /**< group B event 1 source select */ + unsigned int rg_em_b2_sel : 4; /**< group B event 2 source select */ + unsigned int rg_evta1t_sel : 3; /**< evta1t source select */ + unsigned int reserved0 : 1; + unsigned int rg_evta2t_sel : 3; /**< evta2t source select */ + unsigned int reserved1 : 1; + unsigned int rg_evtb1t_sel : 3; /**< evtb1t source select */ + unsigned int reserved2 : 1; + unsigned int rg_evtb2t_sel : 3; /**< evtb2t source select */ + unsigned int reserved3 : 1; + } BIT; +} volatile EM_MRG_SEL_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_evta1_sel : 1; /**< em_evta1 event source select */ + unsigned int rg_evta2_sel : 1; /**< em_evta2 event source select */ + unsigned int rg_evtb1_sel : 1; /**< em_evtb1 event source select */ + unsigned int rg_evtb2_sel : 1; /**< em_evtb2 event source select */ + unsigned int rg_evtfilt_sel : 2; /**< em_evfilt event source select */ + unsigned int reserved0 : 26; + } BIT; +} volatile EM_OUT_SEL_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_mskwd_alg_zroen : 1; /**< enable clear and restart mask window when couter zero */ + unsigned int rg_mskwd_alg_prden : 1; /**< enable clear and restart mask window when couter period */ + unsigned int reserved0 : 2; + unsigned int rg_mskwd_psel : 1; /**< mask window polarity */ + unsigned int reserved1 : 26; + unsigned int rg_mskwd_en : 1; /**< mask window enable */ + } BIT; +} volatile EM_WD_EN_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_mskwd_offset : 16; /**< mask window's offset */ + unsigned int rg_mskwd_width : 16; /**< mask window's width */ + } BIT; +} volatile EM_WD_CNT_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int ro_offset_cnt : 16; /**< mask window's offset read register */ + unsigned int ro_width_cnt : 16; /**< mask window's width read register */ + } BIT; +} volatile EM_WD_STS_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_vcap_sta_edg : 4; /**< valley capture start edge */ + unsigned int reserved0 : 4; + unsigned int rg_vcap_stp_edg : 4; /**< valley capture stop edge */ + unsigned int reserved1 : 4; + unsigned int rg_vcap_edg_sel : 1; /**< valley capture edge select */ + unsigned int reserved2 : 3; + unsigned int rg_vcap_trig_sel : 3; /**< valley capture trigger select */ + unsigned int reserved3 : 7; + unsigned int rg_vcap_div_mode : 1; /**< valley capture count mode */ + unsigned int rg_vcap_en : 1; /**< valley delay capture enable */ + } BIT; +} volatile EM_VCAP_CFG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_vcap_swdly : 16; /**< softeware delay value */ + unsigned int rg_vcap_dly_mode : 3; /**< em_evtfilt delay select */ + unsigned int reserved0 : 13; + } BIT; +} volatile EM_VCAP_DLY_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int ro_vcap_cnt : 16; /**< software calibration value */ + unsigned int ro_vcap_dly : 16; /**< delay value between start edge and stop edge */ + } BIT; +} volatile EM_VCAP_STS1_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int ro_vcap_sta_edgsts : 1; /**< flag of capture start edge */ + unsigned int ro_vcap_stp_edgsts : 1; /**< flag of capture stop edge */ + unsigned int reserved0 : 30; + } BIT; +} volatile EM_VCAP_STS2_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_filt_edg_cnt : 4; /**< edge mask count value */ + unsigned int reserved0 : 4; + unsigned int rg_filt_edg_sel : 2; /**< filter active edge select */ + unsigned int reserved1 : 21; + unsigned int rg_filt_dly_en : 1; /**< enable add delay after filter */ + } BIT; +} volatile EM_FILT_CFG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int ro_tcap_sts : 1; /**< TC count value capure success */ + unsigned int reserved0 : 3; + unsigned int rg_tcap_clr : 1; /**< TC count value capure success flag */ + unsigned int reserved1 : 26; + unsigned int rg_tcap_en : 1; /**< TC count capture enable */ + } BIT; +} volatile EM_TCAP_CFG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int ro_tcap_cnt_rt : 16; /**< TC count value */ + unsigned int ro_tcap_cnt_buf : 16; /**< TC count buffer value */ + } BIT; +} volatile EM_TCAP_VAL_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_syni_sel : 4; /**< em_evt_syni source select */ + unsigned int reserved0 : 12; + unsigned int ro_syni_flag : 1; /**< em_evt_syni event active flag */ + unsigned int reserved1 : 3; + unsigned int rg_syni_clr : 1; /**< em_evt_syni event active flag clear bit */ + unsigned int reserved2 : 11; + } BIT; +} volatile SYNI_CFG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_syncnt_a1en : 1; /**< TC value sync at em_evta1_pulse */ + unsigned int rg_syncnt_b1en : 1; /**< TC value sync at em_evtb1_pulse */ + unsigned int rg_syncnt_synien : 1; /**< TC value sync at em_synci_pulse */ + unsigned int reserved0 : 29; + } BIT; +} volatile SYNCNT_CFG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_syno_zroen : 1; /**< sync out at zero enable */ + unsigned int rg_syno_prden : 1; /**< sync out at period enable */ + unsigned int rg_syno_a1en : 1; /**< sync out at a1 enable */ + unsigned int rg_syno_b1en : 1; /**< sync out at b1 enable */ + unsigned int reserved0 : 1; + unsigned int rg_syno_refben : 1; /**< sync out at reference B match enable */ + unsigned int rg_syno_refcen : 1; /**< sync out at reference C match enable */ + unsigned int rg_syno_refden : 1; /**< sync out at reference D match enable */ + unsigned int rg_mode_syno : 1; /**< sync out mode select */ + unsigned int rg_latset_sel : 1; /**< latch condition */ + unsigned int rg_latset_otsyn : 1; /**< control a sync out latch bit enable */ + unsigned int reserved1 : 21; + } BIT; +} volatile SYNO_CFG_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_gld_zroen : 1; /**< enable global load when count zero */ + unsigned int rg_gld_prden : 1; /**< enable global load when count period */ + unsigned int rg_gld_cntsynen : 1; /**< enable global load when em_cnt_syn enable */ + unsigned int reserved0 : 5; + unsigned int rg_gld_prsc_prd : 4; /**< global load scale ratio */ + unsigned int rg_mode_gld : 1; /**< buffer global load mode select */ + unsigned int reserved1 : 3; + unsigned int rg_latset_otgld : 1; /**< control a global latch bit enable */ + unsigned int reserved2 : 15; + } BIT; +} volatile GLB_LOAD_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int tc_prd_ld_sts : 1; /**< count period buffer status */ + unsigned int tc_refa_ld_sts : 1; /**< reference A buffer status */ + unsigned int tc_refb_ld_sts : 1; /**< reference B buffer status */ + unsigned int tc_refc_ld_sts : 1; /**< reference C buffer status */ + unsigned int tc_refd_ld_sts : 1; /**< reference D buffer status */ + unsigned int reserved0 : 3; + unsigned int pg_act_a_ld_sts : 1; /**< channel A action buffer status */ + unsigned int pg_act_b_ld_sts : 1; /**< channel B buffer status */ + unsigned int pg_out_frc_ld_sts : 1; /**< PG putput force buffer status */ + unsigned int reserved1 : 1; + unsigned int dg_red_ld_sts : 1; /**< DG rising edge buffer status */ + unsigned int dg_fed_ld_sts : 1; /**< DG falling edge buffer status */ + unsigned int dg_cfg_ld_sts : 1; /**< DG config buffer status */ + unsigned int reserved2 : 17; + } BIT; +} volatile LOAD_STS_REG; + +typedef union { + unsigned int reg; + struct { + unsigned int rg_syncnt_frc : 1; /**< force an em_cnt_syn event */ + unsigned int reserved0 : 3; + unsigned int rg_syno_frc : 1; /**< force an apt_syno event */ + unsigned int reserved1 : 3; + unsigned int rg_synp_frc : 1; + unsigned int reserved2 : 3; + unsigned int rg_gld_frc : 1; /**< force an em_glb_ld event*/ + unsigned int reserved3 : 3; + unsigned int rg_vcap_frc : 1; /**< force a valley capture restart trigger event */ + unsigned int reserved4 : 3; + unsigned int rg_csa_syn_frc : 1; /**< force a SOCA trigger */ + unsigned int rg_csb_syn_frc : 1; /**< force a SOCB trigger */ + unsigned int reserved5 : 2; + unsigned int rg_int_syn_frc : 1; /**< force timer interrupt scale load sync init value */ + unsigned int reserved6 : 3; + unsigned int rg_synpg_frc : 1; /**< force create waveform buffer indepent load trigger event */ + unsigned int reserved7 : 3; + } BIT; +} volatile SYN_FRC_REG; + +/** + * @brief APT registers definition structure. + */ +typedef struct _APT_RegStrcut { + VER_INFO_REG VER_INFO; /**< VER_INFO_REG. Offset address 0x00000000U. */ + unsigned int reserved0[3]; + TC_MODE_REG TC_MODE; /**< TC_MODE_REG. Offset address 0x00000010U. */ + TC_PHS_REG TC_PHS; /**< TC_PHS_REG. Offset address 0x00000014U. */ + TC_OVRID_REG TC_OVRID; /**< TC_OVRID_REG. Offset address 0x00000018U. */ + unsigned int reserved1; + TC_PRD_REG TC_PRD; /**< TC_PRD_REG. Offset address 0x00000020U. */ + unsigned int reserved2[3]; + TC_REFA_REG TC_REFA; /**< TC_REFA_REG. Offset address 0x00000030U. */ + TC_REFB_REG TC_REFB; /**< TC_REFB_REG. Offset address 0x00000034U. */ + TC_REFC_REG TC_REFC; /**< TC_REFC_REG. Offset address 0x00000038U. */ + TC_REFD_REG TC_REFD; /**< TC_REFD_REG. Offset address 0x0000003CU. */ + TC_BUF_EN_REG TC_BUF_EN; /**< TC_BUF_EN_REG. Offset address 0x00000040U. */ + unsigned int reserved3[3]; + TC_PRD_LOAD_REG TC_PRD_LOAD; /**< TC_PRD_LOAD_REG. Offset address 0x00000050U. */ + TC_REF_LOAD_REG TC_REF_LOAD; /**< TC_REF_LOAD_REG. Offset address 0x00000054U. */ + unsigned int reserved4[2]; + TC_STS_REG TC_STS; /**< TC_STS_REG. Offset address 0x00000060U. */ + unsigned int reserved5[39]; + PG_ACT_A_REG PG_ACT_A; /**< PG_ACT_A_REG. Offset address 0x00000100U. */ + PG_ACT_B_REG PG_ACT_B; /**< PG_ACT_B_REG. Offset address 0x00000104U. */ + unsigned int reserved6[2]; + PG_ACT_FRC_REG PG_ACT_FRC; /**< PG_ACT_FRC_REG. Offset address 0x00000110U. */ + PG_OUT_FRC_REG PG_OUT_FRC; /**< PG_OUT_FRC_REG. Offset address 0x00000114U. */ + unsigned int reserved7[2]; + PG_BUF_EN_REG PG_BUF_EN; /**< PG_BUF_EN_REG. Offset address 0x00000120U. */ + unsigned int reserved8[3]; + PG_ACT_LD_REG PG_ACT_LD; /**< PG_ACT_LD_REG. Offset address 0x00000130U. */ + unsigned int reserved9[3]; + PG_EVTC_SEL_REG PG_EVTC_SEL; /**< PG_EVTC_SEL_REG. Offset address 0x00000140U. */ + unsigned int reserved10[47]; + DG_RED_REG DG_RED; /**< DG_RED_REG. Offset address 0x00000200U. */ + DG_FED_REG DG_FED; /**< DG_FED_REG. Offset address 0x00000204U. */ + DG_CFG_REG DG_CFG; /**< DG_CFG_REG. Offset address 0x00000208U. */ + unsigned int reserved11; + DG_BUF_EN_REG DG_BUF_EN; /**< DG_BUF_EN_REG. Offset address 0x00000210U. */ + DG_BUF_LOAD_REG DG_BUF_LOAD; /**< DG_BUF_LOAD_REG. Offset address 0x00000214U. */ + unsigned int reserved12[58]; + OC_MODE_REG OC_MODE; /**< OC_MODE_REG. Offset address 0x00000300U. */ + OC_LAT_EN_REG OC_LAT_EN; /**< OC_LAT_EN_REG. Offset address 0x00000304U. */ + unsigned int reserved13[2]; + OC_ACT_A_REG OC_ACT_A; /**< OC_ACT_A_REG. Offset address 0x00000310U. */ + OC_ACT_B_REG OC_ACT_B; /**< OC_ACT_B_REG. Offset address 0x00000314U. */ + unsigned int reserved14[2]; + OC_EVT_FLAG_REG OC_EVT_FLAG; /**< OC_EVT_FLAG_REG. Offset address 0x00000320U. */ + OC_PRD_CLR_REG OC_PRD_CLR; /**< OC_PRD_CLR_REG. Offset address 0x00000324U. */ + unsigned int reserved15[2]; + OC_FRC_EVT_REG OC_FRC_EVT; /**< OC_FRC_EVT_REG. Offset address 0x00000330U. */ + unsigned int reserved16[55]; + INT_EVT_EN_REG INT_EVT_EN; /**< INT_EVT_EN_REG. Offset address 0x00000410U. */ + INT_TMR_EN_REG INT_TMR_EN; /**< INT_TMR_EN_REG. Offset address 0x00000414U. */ + unsigned int reserved17[2]; + INT_TMR_FLAG_REG INT_TMR_FLAG; /**< INT_TMR_FLAG_REG. Offset address 0x00000420U. */ + INT_TMR_SEL_REG INT_TMR_SEL; /**< INT_TMR_SEL_REG. Offset address 0x00000424U. */ + INT_PRSC_CFG_REG INT_PRSC_CFG; /**< INT_PRSC_CFG_REG. Offset address 0x00000428U. */ + unsigned int reserved18[53]; + CS_TMR_SELA_REG CS_TMR_SELA; /**< CS_TMR_SELA_REG. Offset address 0x00000500U. */ + CS_TMR_SELB_REG CS_TMR_SELB; /**< CS_TMR_SELB_REG. Offset address 0x00000504U. */ + CS_PRSCA_CFG_REG CS_PRSCA_CFG; /**< CS_PRSCA_CFG_REG. Offset address 0x00000508U. */ + CS_PRSCB_CFG_REG CS_PRSCB_CFG; /**< CS_PRSCB_CFG_REG. Offset address 0x0000050CU. */ + CS_FLAG_REG CS_FLAG; /**< CS_FLAG_REG. Offset address 0x00000510U. */ + unsigned int reserved19[3]; + CS_DMA_REG CS_DMA; /**< CS_DMA_REG. Offset address 0x00000520U. */ + unsigned int reserved20[55]; + EM_EVTIO_PSEL_REG EM_EVTIO_PSEL; /**< EM_EVTIO_PSEL_REG. Offset address 0x00000600U. */ + EM_EVTMP_PSEL_REG EM_EVTMP_PSEL; /**< EM_EVTMP_PSEL_REG. Offset address 0x00000604U. */ + EM_AOR_EN_REG EM_AOR_EN; /**< EM_AOR_EN_REG. Offset address 0x00000608U. */ + EM_BOR_EN_REG EM_BOR_EN; /**< EM_BOR_EN_REG. Offset address 0x0000060CU. */ + EM_MRG_SEL_REG EM_MRG_SEL; /**< EM_MRG_SEL_REG. Offset address 0x00000610U. */ + EM_OUT_SEL_REG EM_OUT_SEL; /**< EM_OUT_SEL_REG. Offset address 0x00000614U. */ + unsigned int reserved21[2]; + EM_WD_EN_REG EM_WD_EN; /**< EM_WD_EN_REG. Offset address 0x00000620U. */ + EM_WD_CNT_REG EM_WD_CNT; /**< EM_WD_CNT_REG. Offset address 0x00000624U. */ + unsigned int reserved22; + EM_WD_STS_REG EM_WD_STS; /**< EM_WD_STS_REG. Offset address 0x0000062CU. */ + EM_VCAP_CFG_REG EM_VCAP_CFG; /**< EM_VCAP_CFG_REG. Offset address 0x00000630U. */ + EM_VCAP_DLY_REG EM_VCAP_DLY; /**< EM_VCAP_DLY_REG. Offset address 0x00000634U. */ + unsigned int reserved23[2]; + EM_VCAP_STS1_REG EM_VCAP_STS1; /**< EM_VCAP_STS1_REG. Offset address 0x00000640U. */ + EM_VCAP_STS2_REG EM_VCAP_STS2; /**< EM_VCAP_STS2_REG. Offset address 0x00000644U. */ + unsigned int reserved24[2]; + EM_FILT_CFG_REG EM_FILT_CFG; /**< EM_FILT_CFG_REG. Offset address 0x00000650U. */ + unsigned int reserved25[3]; + EM_TCAP_CFG_REG EM_TCAP_CFG; /**< EM_TCAP_CFG_REG. Offset address 0x00000660U. */ + unsigned int reserved26[3]; + EM_TCAP_VAL_REG EM_TCAP_VAL; /**< EM_TCAP_VAL_REG. Offset address 0x00000670U. */ + unsigned int reserved27[35]; + SYNI_CFG_REG SYNI_CFG; /**< SYNI_CFG_REG. Offset address 0x00000700U. */ + SYNCNT_CFG_REG SYNCNT_CFG; /**< SYNCNT_CFG_REG. Offset address 0x00000704U. */ + SYNO_CFG_REG SYNO_CFG; /**< SYNO_CFG_REG. Offset address 0x00000708U. */ + unsigned int reserved28; + GLB_LOAD_REG GLB_LOAD; /**< GLB_LOAD_REG. Offset address 0x000000710U. */ + unsigned int reserved29[3]; + LOAD_STS_REG LOAD_STS; /**< LOAD_STS_REG. Offset address 0x000000720U. */ + unsigned int reserved30[3]; + SYN_FRC_REG SYN_FRC; /**< SYN_FRC_REG. Offset address 0x00000730U. */ +} volatile APT_RegStruct; + +/** + * @brief Set the emulation stop mode of APT module. + * @param aptx APT register base address. + * @param emuMode Emulation stop mode. + * @retval None. + */ +static inline void DCL_APT_SetEmulationMode(APT_RegStruct *aptx, APT_EmulationMode emuMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(emuMode <= APT_EMULATION_STOP_APT); + aptx->TC_MODE.BIT.rg_emu_stop = emuMode; +} + +/** + * @brief Set the time-base divider factor. + * @param aptx APT register base address. + * @param divFactor Time-base divider factor. + * @retval None. + */ +static inline void DCL_APT_SetDividerFactor(APT_RegStruct *aptx, unsigned short divFactor) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(divFactor <= DIVIDER_FACTOR_MAX); + aptx->TC_MODE.BIT.rg_div_fac = divFactor; +} + +/** + * @brief Get the time-base divider factor. + * @param aptx APT register base address. + * @retval unsigned short: time-base divider factor. + */ +static inline unsigned short DCL_APT_GetDividerFactor(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->TC_MODE.BIT.rg_div_fac); +} + +/** + * @brief Set the count mode of time-base counter. + * @param aptx APT register base address. + * @param cntMode Count mode. + * @retval None. + */ +static inline void DCL_APT_SetTimeBaseCountMode(APT_RegStruct *aptx, APT_CountMode cntMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(cntMode <= APT_COUNT_MODE_FREEZE); + aptx->TC_MODE.BIT.rg_cnt_mode = cntMode; +} + +/** + * @brief Set the period of time-base counter. + * @param aptx APT register base address. + * @param periodCnt Time-base counter period. + * @retval None. + */ +static inline void DCL_APT_SetTimeBasePeriod(APT_RegStruct *aptx, unsigned short periodCnt) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->TC_PRD.BIT.rg_cnt_prd = periodCnt; +} + +/** + * @brief Get the period of time-base counter. + * @param aptx APT register base address. + * @retval unsigned short: time-base counter period + */ +static inline unsigned short DCL_APT_GetTimeBasePeriod(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->TC_PRD.BIT.rg_cnt_prd); +} + +/** + * @brief Set the count mode of slave APT module after synchronization. + * @param aptx APT register base address. + * @param syncCntMode Count mode after synchronization. + * @retval None. + */ +static inline void DCL_APT_SetCountModeAfterSync(APT_RegStruct *aptx, APT_SyncCountMode syncCntMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(syncCntMode >= APT_COUNT_MODE_AFTER_SYNC_DOWN); + APT_PARAM_CHECK_NO_RET(syncCntMode <= APT_COUNT_MODE_AFTER_SYNC_UP); + aptx->TC_PHS.BIT.rg_cnt_dir = syncCntMode; +} + +/** + * @brief Set the divider phase after synchronization. + * @param aptx APT register base address. + * @param divPhase Divider phase after synchronization + * @retval None. + */ +static inline void DCL_APT_SetDividerPhase(APT_RegStruct *aptx, unsigned short divPhase) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(divPhase <= DIVIDER_FACTOR_MAX); + aptx->TC_PHS.BIT.rg_div_phs = divPhase; +} + +/** + * @brief Set the counter phase after synchronization. + * @param aptx APT register base address. + * @param cntPhase Counter phase after synchronization. + * @retval None. + */ +static inline void DCL_APT_SetCounterPhase(APT_RegStruct *aptx, unsigned short cntPhase) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + TC_PHS_REG tmp = aptx->TC_PHS; + tmp.BIT.rg_cnt_phs = cntPhase; + aptx->TC_PHS = tmp; +} + +/** + * @brief Set the software override value of divider. + * @param aptx APT register base address. + * @param divOvrid Software override value of divider. + * @retval None. + */ +static inline void DCL_APT_SetDividerOverride(APT_RegStruct *aptx, unsigned short divOvrid) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(divOvrid <= DIVIDER_FACTOR_MAX); + aptx->TC_OVRID.BIT.rg_div_ovrid = divOvrid; +} + +/** + * @brief Set the software override value of time-base counter. + * @param aptx APT register base address. + * @param cntOvrid Software override value of time-base counter. + * @retval None. + */ +static inline void DCL_APT_SetCounterOverride(APT_RegStruct *aptx, unsigned short cntOvrid) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + TC_OVRID_REG tmp = aptx->TC_OVRID; + tmp.BIT.rg_cnt_ovrid = cntOvrid; + aptx->TC_OVRID = tmp; +} + +/** + * @brief Force software override on time-base divider and counter. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_ForceOverride(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->TC_OVRID.BIT.rg_cnt_ovrid_en = BASE_CFG_SET; +} + +/** + * @brief Set the count compare reference value of time-base divider. + * @param aptx APT register base address. + * @param ref Count compare reference. + * @param divCmp Count compare reference value of divider. + * @retval None. + */ +static inline void DCL_APT_SetDividerCompare(APT_RegStruct *aptx, APT_CompareRef ref, unsigned short divCmp) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ref <= APT_COMPARE_REFERENCE_D); + APT_PARAM_CHECK_NO_RET(divCmp <= DIVIDER_FACTOR_MAX); + switch (ref) { + case APT_COMPARE_REFERENCE_A: + aptx->TC_REFA.BIT.rg_cnt_refal = divCmp; + break; + case APT_COMPARE_REFERENCE_B: + aptx->TC_REFB.BIT.rg_cnt_refbl = divCmp; + break; + case APT_COMPARE_REFERENCE_C: + aptx->TC_REFC.BIT.rg_cnt_refcl = divCmp; + break; + case APT_COMPARE_REFERENCE_D: + aptx->TC_REFD.BIT.rg_cnt_refdl = divCmp; + break; + default: + break; + } +} + +/** + * @brief Get the count compare reference value of time-base divider. + * @param aptx APT register base address. + * @param ref Count compare reference. + * @retval unsigned short: Count compare reference value of divider. + */ +static inline unsigned short DCL_APT_GetDividerCompare(APT_RegStruct *aptx, APT_CompareRef ref) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_WITH_RET(ref >= APT_COMPARE_REFERENCE_A, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(ref <= APT_COMPARE_REFERENCE_D, BASE_STATUS_ERROR); + switch (ref) { + case APT_COMPARE_REFERENCE_A: + return (aptx->TC_REFA.BIT.rg_cnt_refal); + case APT_COMPARE_REFERENCE_B: + return (aptx->TC_REFB.BIT.rg_cnt_refbl); + case APT_COMPARE_REFERENCE_C: + return (aptx->TC_REFC.BIT.rg_cnt_refcl); + case APT_COMPARE_REFERENCE_D: + return (aptx->TC_REFD.BIT.rg_cnt_refdl); + default: + return 0; + } +} + +/** + * @brief Set the count compare reference value of time-base counter. + * @param aptx APT register base address. + * @param ref Count compare reference. + * @param cntCmp Count compare reference value of counter. + * @retval None. + */ +static inline void DCL_APT_SetCounterCompare(APT_RegStruct *aptx, APT_CompareRef ref, unsigned short cntCmp) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ref >= APT_COMPARE_REFERENCE_A); + APT_PARAM_CHECK_NO_RET(ref <= APT_COMPARE_REFERENCE_D); + TC_REFA_REG tmpA; + TC_REFB_REG tmpB; + TC_REFC_REG tmpC; + TC_REFD_REG tmpD; + switch (ref) { + case APT_COMPARE_REFERENCE_A: + tmpA = aptx->TC_REFA; + tmpA.BIT.rg_cnt_refah = cntCmp; + aptx->TC_REFA = tmpA; + break; + case APT_COMPARE_REFERENCE_B: + tmpB = aptx->TC_REFB; + tmpB.BIT.rg_cnt_refbh = cntCmp; + aptx->TC_REFB = tmpB; + break; + case APT_COMPARE_REFERENCE_C: + tmpC = aptx->TC_REFC; + tmpC.BIT.rg_cnt_refch = cntCmp; + aptx->TC_REFC = tmpC; + break; + case APT_COMPARE_REFERENCE_D: + tmpD = aptx->TC_REFD; + tmpD.BIT.rg_cnt_refdh = cntCmp; + aptx->TC_REFD = tmpD; + break; + default: + break; + } +} + +/** + * @brief Get the count compare reference value of time-base counter. + * @param aptx APT register base address. + * @param ref Count compare reference. + * @retval unsigned short: Count compare reference value of counter. + */ +static inline unsigned short DCL_APT_GetCounterCompare(APT_RegStruct *aptx, APT_CompareRef ref) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_WITH_RET(ref >= APT_COMPARE_REFERENCE_A, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(ref <= APT_COMPARE_REFERENCE_D, BASE_STATUS_ERROR); + switch (ref) { + case APT_COMPARE_REFERENCE_A: + return (aptx->TC_REFA.BIT.rg_cnt_refah); + case APT_COMPARE_REFERENCE_B: + return (aptx->TC_REFB.BIT.rg_cnt_refbh); + case APT_COMPARE_REFERENCE_C: + return (aptx->TC_REFC.BIT.rg_cnt_refch); + case APT_COMPARE_REFERENCE_D: + return (aptx->TC_REFD.BIT.rg_cnt_refdh); + default: + return 0; + } +} + +/** + * @brief Set the buffer load mode of time-base period register. + * @param aptx APT register base address. + * @param prdLoadMode Buffer load mode of time-base period register. + * @retval None. + */ +static inline void DCL_APT_SetPeriodLoadMode(APT_RegStruct *aptx, APT_BufferLoadMode prdLoadMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(prdLoadMode >= APT_BUFFER_DISABLE); + APT_PARAM_CHECK_NO_RET(prdLoadMode <= APT_BUFFER_GLOBAL_LOAD); + aptx->TC_BUF_EN.reg &= (~0b11); /* Clear rg_prd_buf_en and rg_prd_gld_en */ + aptx->TC_BUF_EN.reg |= prdLoadMode; /* Write rg_prd_buf_en and rg_prd_gld_en */ +} + +/** + * @brief Enable the buffer load events of TC_PRD register + * @param aptx APT register base address. + * @param loadEvent The buffer load events of TC_PRD register + * A logical OR of valid values that can be passed as the loadEvent parameter + * Valid values for loadEvent are: + * APT_PERIOD_LOAD_EVENT_ZERO - When counter value equal to zeor + * APT_PERIOD_LOAD_EVENT_A1 - When combined event A1 is valid + * APT_PERIOD_LOAD_EVENT_B1 - When combined event B1 is valid + * APT_PERIOD_LOAD_EVENT_SYNC - When synchronization event is valid + * @retval None. + */ +static inline void DCL_APT_SetPeriodLoadEvent(APT_RegStruct *aptx, unsigned int prdLoadEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->TC_PRD_LOAD.reg = prdLoadEvent; +} + +/** + * @brief Set the buffer load mode of count compare reference register. + * @param aptx APT register base address. + * @param ref Count compare reference. + * @param cmpLoadMode Buffer load mode of count compare reference register. + * @retval None. + */ +static inline void DCL_APT_SetCompareLoadMode(APT_RegStruct *aptx, + APT_CompareRef ref, + APT_BufferLoadMode cmpLoadMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ref >= APT_COMPARE_REFERENCE_A); + APT_PARAM_CHECK_NO_RET(ref <= APT_COMPARE_REFERENCE_D); + APT_PARAM_CHECK_NO_RET(cmpLoadMode >= APT_BUFFER_DISABLE); + APT_PARAM_CHECK_NO_RET(cmpLoadMode <= APT_BUFFER_GLOBAL_LOAD); + unsigned int offsetA = 4; /* Buffer mode control bits offset of reference A */ + unsigned int tcBufField = 2; /* Field width of buffer load mode setting */ + unsigned int offset = offsetA + ref * tcBufField; + aptx->TC_BUF_EN.reg &= (~(0b11 << offset)); /* Clear rg_refx_gld_en and rg_refx_buf_en */ + aptx->TC_BUF_EN.reg |= (cmpLoadMode << offset); /* Write rg_refx_gld_en and rg_refx_buf_en */ +} + +/** + * @brief Enable the buffer load events of TC_REFA, TC_REFB, TC_REFC, TC_REFD register + * @param aptx APT register base address. + * @param ref Count compare reference + * @param loadEvent The buffer load events of TC_REFA, TC_REFB, TC_REFC, TC_REFD register + * A logical OR of valid values can be passed as the loadEvent parameter + * Valid values for loadEvent are: + * APT_COMPARE_LOAD_EVENT_ZERO - When counter value equal to zero + * APT_COMPARE_LOAD_EVENT_PERIOD - When counter value equal to period + * APT_COMPARE_LOAD_EVENT_A1 - When combined event A1 is valid + * APT_COMPARE_LOAD_EVENT_B1 - When combined event B1 is valid + * APT_COMPARE_LOAD_EVENT_SYNC - When synchronization event is valid + * @retval None. + */ +static inline void DCL_APT_SetCompareLoadEvent(APT_RegStruct *aptx, APT_CompareRef ref, unsigned int cmpLoadEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ref >= APT_COMPARE_REFERENCE_A); + APT_PARAM_CHECK_NO_RET(ref <= APT_COMPARE_REFERENCE_D); + unsigned int refBufField = 8; /* Field width of compare reference load event setting */ + aptx->TC_REF_LOAD.reg &= (~(0x1F << (ref * refBufField))); /* Clear bit field for load event selection */ + aptx->TC_REF_LOAD.reg |= (cmpLoadEvent << (ref * refBufField)); +} + +/** + * @brief Get the value of time-base divider. + * @param aptx APT register base address. + * @retval unsigned short: The value of time-base divider value. + */ +static inline unsigned short DCL_APT_GetDividerValue(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->TC_STS.BIT.ro_div_cnt); +} + +/** + * @brief Get the value of time-base counter. + * @param aptx APT register base address. + * @retval unsigned short: The value of time-base counter. + */ +static inline unsigned short DCL_APT_GetCounterValue(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->TC_STS.BIT.ro_cnt_val); +} + +/** + * @brief Return time base counter direction + * @param aptx APT register base address. + * @retval unsigned short: The direction of time base counter + * Valid return values are: + * APT_COUNTER_STATUS_COUNT_DOWN - The counter is counting down + * APT_COUNTER_STATUS_COUNT_UP - The counter is counting up + */ +static inline unsigned short DCL_APT_GetCounterDirection(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->TC_STS.BIT.ro_cnt_dir); +} + +/* --------------------------------------------------------------------------------------------- */ +/* PWM Generation (PG) submodule Direct Configuration Layer functions -------------------------- */ +/* --------------------------------------------------------------------------------------------- */ +/** + * @brief Set PWM waveform action on corresponding event. + * @param aptx APT register base address. + * @param channel PWM output channel. + * @param actEvent PWM waveform action event. + * @param action PWM waveform action. + * @retval None. + */ +static inline void DCL_APT_SetPWMAction(APT_RegStruct *aptx, + APT_PWMChannel channel, + APT_PWMActionEvent actEvent, + APT_PWMAction action) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(channel >= APT_PWM_CHANNEL_A); + APT_PARAM_CHECK_NO_RET(channel <= APT_PWM_CHANNEL_B); + APT_PARAM_CHECK_NO_RET(actEvent >= APT_PWM_ACTION_ON_TIMEBASE_ZERO); + APT_PARAM_CHECK_NO_RET(actEvent <= APT_PWM_ACTION_ON_C2_COUNT_DOWN); + APT_PARAM_CHECK_NO_RET(action <= APT_PWM_ACTION_TOGGLE); + if (channel == APT_PWM_CHANNEL_A) { + aptx->PG_ACT_A.reg &= (~(0b11 << actEvent)); + aptx->PG_ACT_A.reg |= (action << actEvent); + } else if (channel == APT_PWM_CHANNEL_B) { + aptx->PG_ACT_B.reg &= (~(0b11 << actEvent)); + aptx->PG_ACT_B.reg |= (action << actEvent); + } +} + +/** + * @brief Select the event source of PWM Generation event C1 or C2. + * This function is only used when C1 or C2 event is selected as PWM action event. + * @param aptx APT register base address. + * @param channel PWM output channel. + * @param eventCx The PWM Generation event, should be C1 or C2. + * @param eventCxSrc The trigger source of PWM Generation event C1 or C2. + * @retval None. + */ +static inline void DCL_APT_SelectCxEventSource(APT_RegStruct *aptx, + APT_PWMChannel channel, + APT_PGEventCx eventCx, + APT_PGEventCxSrc eventCxSrc) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET((channel >= APT_PWM_CHANNEL_A) && (channel <= APT_PWM_CHANNEL_B)); + APT_PARAM_CHECK_NO_RET(eventCx >= APT_PWM_GENERATION_EVENT_C1); + APT_PARAM_CHECK_NO_RET(eventCx <= APT_PWM_GENERATION_EVENT_C2); + APT_PARAM_CHECK_NO_RET(eventCxSrc >= APT_PG_EVT_C_FORBIDDEN); + APT_PARAM_CHECK_NO_RET(eventCxSrc <= APT_PG_EVT_C_SYNC_IN); + unsigned int chOffset = 8; /* Bit field offset of PWM output channel */ + unsigned int cxOffset = 4; /* Bit field offset of event Cx */ + aptx->PG_EVTC_SEL.reg &= (~(0b1111 << (channel * chOffset + eventCx * cxOffset))); + aptx->PG_EVTC_SEL.reg |= eventCxSrc << (channel * chOffset + eventCx * cxOffset); +} + +/** + * @brief Set the buffer load mode of PWM action register. + * @param aptx APT register base address. + * @param channel PWM output channel. + * @param loadMode Buffer load mode. + * @retval None. + */ +static inline void DCL_APT_SetPWMActionLoadMode(APT_RegStruct *aptx, + APT_PWMChannel channel, + APT_BufferLoadMode loadMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(channel >= APT_PWM_CHANNEL_A); + APT_PARAM_CHECK_NO_RET(channel <= APT_PWM_CHANNEL_B); + APT_PARAM_CHECK_NO_RET(loadMode >= APT_BUFFER_DISABLE); + APT_PARAM_CHECK_NO_RET(loadMode <= APT_BUFFER_GLOBAL_LOAD); + unsigned int bufFieldWidth = 2; /* Bit field width of buffer load mode setting */ + aptx->PG_BUF_EN.reg &= (~(0b11 << (channel * bufFieldWidth))); /* Clear rg_actx_gld_en and rg_actx_buf_en */ + aptx->PG_BUF_EN.reg |= (loadMode << (channel * bufFieldWidth)); /* Write rg_actx_gld_en and rg_actx_buf_en */ +} + +/** + * @brief Enable the buffer load events of PG_ACT_A or PG_ACT_B register + * @param aptx APT register base address. + * @param channel PWM output channel. + * @param loadEvent The buffer load events of PG_ACT_A or PG_ACT_B register + * A logical OR of valid values can be passed as the loadEvent parameter + * Valid values for loadEvent are: + * APT_ACTION_LOAD_EVENT_ZERO - When counter value equal to zero + * APT_ACTION_LOAD_EVENT_PERIOD - When counter value equal to period + * APT_ACTION_LOAD_EVENT_A1 - When combined event A1 is valid + * APT_ACTION_LOAD_EVENT_B1 - When combined event B1 is valid + * APT_ACTION_LOAD_EVENT_SYNC - When synchronization event is valid + * @retval None. + */ +static inline void DCL_APT_SetPWMActionLoadEvent(APT_RegStruct *aptx, + APT_PWMChannel channel, + unsigned int loadEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(channel >= APT_PWM_CHANNEL_A); + APT_PARAM_CHECK_NO_RET(channel <= APT_PWM_CHANNEL_B); + unsigned int actBufField = 8; /* Field width of PWM action load event setting */ + aptx->PG_ACT_LD.reg &= (~(0x1F << (channel * actBufField))); + aptx->PG_ACT_LD.reg |= (loadEvent << (channel * actBufField)); +} + +/** + * @brief Set the PWM waveform action on one-shot action software event. + * @param aptx APT register base address. + * @param channel PWM output channel. + * @param action PWM waveform action. + * @retval None. + */ +static inline void DCL_APT_SetSwOneShotPWMAction(APT_RegStruct *aptx, APT_PWMChannel channel, APT_PWMAction action) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(channel >= APT_PWM_CHANNEL_A); + APT_PARAM_CHECK_NO_RET(channel <= APT_PWM_CHANNEL_B); + APT_PARAM_CHECK_NO_RET(action >= APT_PWM_ACTION_HOLD); + APT_PARAM_CHECK_NO_RET(action <= APT_PWM_ACTION_TOGGLE); + if (channel == APT_PWM_CHANNEL_A) { + aptx->PG_ACT_FRC.BIT.rg_pga_act_evt_frc = action; + } else if (channel == APT_PWM_CHANNEL_B) { + aptx->PG_ACT_FRC.BIT.rg_pgb_act_evt_frc = action; + } +} + +/** + * @brief Force one-shot software event. + * @param aptx APT register base address. + * @param channel PWM output channel. + * @retval None. + */ +static inline void DCL_APT_ForceSwOneShotPWMAction(APT_RegStruct *aptx, APT_PWMChannel channel) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(channel >= APT_PWM_CHANNEL_A); + APT_PARAM_CHECK_NO_RET(channel <= APT_PWM_CHANNEL_B); + if (channel == APT_PWM_CHANNEL_A) { + aptx->PG_ACT_FRC.BIT.rg_pga_evt_frc = BASE_CFG_SET; + } else if (channel == APT_PWM_CHANNEL_B) { + aptx->PG_ACT_FRC.BIT.rg_pgb_evt_frc = BASE_CFG_SET; + } +} + +/** + * @brief Set the PWM waveform action on continuous action software event. + * @param aptx APT register base address. + * @param channel PWM output channel. + * @param action PWM waveform action + * @retval None. + */ +static inline void DCL_APT_SetSwContPWMAction(APT_RegStruct *aptx, APT_PWMChannel channel, APT_PWMContAction action) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(channel >= APT_PWM_CHANNEL_A); + APT_PARAM_CHECK_NO_RET(channel <= APT_PWM_CHANNEL_B); + APT_PARAM_CHECK_NO_RET(action >= APT_PWM_CONTINUOUS_ACTION_HOLD); + APT_PARAM_CHECK_NO_RET(action <= APT_PWM_CONTINUOUS_ACTION_HIGH); + if (channel == APT_PWM_CHANNEL_A) { + aptx->PG_OUT_FRC.BIT.rg_pga_frc_act = action; + } else if (channel == APT_PWM_CHANNEL_B) { + aptx->PG_OUT_FRC.BIT.rg_pgb_frc_act = action; + } +} + +static void APT_ForcePWMAOutputLow(APT_RegStruct *aptx) +{ + unsigned int risingOutSelect = aptx->DG_CFG.BIT.rg_dg_red_osel; + unsigned int fallingOutSelect = aptx->DG_CFG.BIT.rg_dg_fed_osel; + unsigned int risingInSelect = aptx->DG_CFG.BIT.rg_dg_red_isel; + unsigned int fallingInSelect = aptx->DG_CFG.BIT.rg_dg_fed_isel; + /* Enable force output. */ + aptx->PG_OUT_FRC.BIT.rg_pga_frc_en = BASE_CFG_ENABLE; + /* if PWMA invert */ + if (((risingOutSelect == APT_DB_RED_OUTPUT_INVERT) && (risingInSelect == APT_DB_RED_INPUT_PWM_A)) || \ + ((fallingOutSelect == APT_DB_FED_OUTPUT_INVERT) && (fallingInSelect == APT_DB_FED_INPUT_PWM_A))) { + aptx->PG_OUT_FRC.BIT.rg_pga_frc_act = APT_PWM_CONTINUOUS_ACTION_HIGH; /* if invert, set high */ + } else { /* if PWMA not invert */ + aptx->PG_OUT_FRC.BIT.rg_pga_frc_act = APT_PWM_CONTINUOUS_ACTION_LOW; /* if not invert, set low */ + } + return; +} + +static void APT_ForcePWMBOutputLow(APT_RegStruct *aptx) +{ + unsigned int risingOutSelect = aptx->DG_CFG.BIT.rg_dg_red_osel; + unsigned int fallingOutSelect = aptx->DG_CFG.BIT.rg_dg_fed_osel; + unsigned int risingInSelect = aptx->DG_CFG.BIT.rg_dg_red_isel; + unsigned int fallingInSelect = aptx->DG_CFG.BIT.rg_dg_fed_isel; + /* Enable force output */ + aptx->PG_OUT_FRC.BIT.rg_pgb_frc_en = BASE_CFG_ENABLE; + /* if PWMB invert */ + if (((risingOutSelect == APT_DB_RED_OUTPUT_INVERT) && (risingInSelect == APT_DB_RED_INPUT_PWM_B)) || \ + ((fallingOutSelect == APT_DB_FED_OUTPUT_INVERT) && (fallingInSelect == APT_DB_FED_INPUT_PWM_B))) { + aptx->PG_OUT_FRC.BIT.rg_pgb_frc_act = APT_PWM_CONTINUOUS_ACTION_HIGH; /* if invert, set high */ + } else { /* if PWMB not invert */ + aptx->PG_OUT_FRC.BIT.rg_pgb_frc_act = APT_PWM_CONTINUOUS_ACTION_LOW; /* if not invert, set low */ + } + return; +} + +/** + * @brief Both PWMA and PWMB output low level. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_ForcePWMOutputLow(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + + APT_ForcePWMAOutputLow(aptx); + APT_ForcePWMBOutputLow(aptx); + + return; +} + +/** + * @brief Set the buffer load mode of continuous aciton software event register. + * @param aptx APT register base address. + * @param loadMode Buffer load mode. + * @retval None. + */ +static inline void DCL_APT_SetSwContActionLoadMode(APT_RegStruct *aptx, APT_BufferLoadMode loadMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(loadMode >= APT_BUFFER_DISABLE); + APT_PARAM_CHECK_NO_RET(loadMode <= APT_BUFFER_GLOBAL_LOAD); + unsigned int bufFieldWidth = 4; /* Bit field width of buffer load mode setting */ + aptx->PG_BUF_EN.reg &= (~(0b11 << bufFieldWidth)); /* Clear rg_frc_gld_en and rg_frc_buf_en */ + aptx->PG_BUF_EN.reg |= (loadMode << bufFieldWidth); /* Write rg_frc_gld_en and rg_frc_buf_en */ +} + +/** + * @brief Enable the buffer load events of PG_OUT_FRC register + * @param aptx APT register base address. + * @param channel PWM output channel + * @param loadEvent The buffer load events of PG_OUT_FRC register + * A logical OR of valid values can be passed as the loadEvent parameter + * Valid values for loadEvent are: + * APT_ACTION_LOAD_EVENT_ZERO - When counter value equal to zero + * APT_ACTION_LOAD_EVENT_PERIOD - When counter value equal to period + * APT_ACTION_LOAD_EVENT_SYNC - When synchronization event is valid + * @retval None. + */ +static inline void DCL_APT_SetSwContActionLoadEvent(APT_RegStruct *aptx, unsigned int loadEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + unsigned int actBufField = 16; /* Field width of continuous PWM action load event setting */ + aptx->PG_ACT_LD.reg &= (~(0x1F << actBufField)); + aptx->PG_ACT_LD.reg |= (loadEvent << actBufField); +} + +/** + * @brief Enable continuous action software event. + * @param aptx APT register base address. + * @param channel PWM output channel. + * @retval None. + */ +static inline void DCL_APT_EnableSwContPWMAction(APT_RegStruct *aptx, APT_PWMChannel channel) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(channel >= APT_PWM_CHANNEL_A); + APT_PARAM_CHECK_NO_RET(channel <= APT_PWM_CHANNEL_B); + if (channel == APT_PWM_CHANNEL_A) { + aptx->PG_OUT_FRC.BIT.rg_pga_frc_en = BASE_CFG_SET; + } else if (channel == APT_PWM_CHANNEL_B) { + aptx->PG_OUT_FRC.BIT.rg_pgb_frc_en = BASE_CFG_SET; + } +} + +/** + * @brief Disable continuous action software event. + * @param aptx APT register base address. + * @param channel PWM output channel. + * @retval None. + */ +static inline void DCL_APT_DisableSwContPWMAction(APT_RegStruct *aptx, APT_PWMChannel channel) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(channel >= APT_PWM_CHANNEL_A); + APT_PARAM_CHECK_NO_RET(channel <= APT_PWM_CHANNEL_B); + if (channel == APT_PWM_CHANNEL_A) { + aptx->PG_OUT_FRC.BIT.rg_pga_frc_en = BASE_CFG_UNSET; + } else if (channel == APT_PWM_CHANNEL_B) { + aptx->PG_OUT_FRC.BIT.rg_pgb_frc_en = BASE_CFG_UNSET; + } +} + +/* --------------------------------------------------------------------------------------------- */ +/* Dead-Band Generation (DG) submodule Direct Configuration Layer functions -------------------- */ +/* --------------------------------------------------------------------------------------------- */ +/** + * @brief Configure the rising edge delay (RED) of Dead-Band Generation. + * @param aptx APT register base address. + * @param redInput The input source of RED counter. + * @param redOutMode The output of RED counter. + * @param dgaOutSwap The swap mode of Dead-Band Generation output signal A. + * true - Select the output of FED counter. + * false - Select the output of RED counter. + * @param redCount The count value of RED counter, in units of APT clock. + * @retval None. + */ +static inline void DCL_APT_SetDeadBandRisingEdge(APT_RegStruct *aptx, + APT_REDInput redInput, + APT_REDOutMode redOutMode, + bool dgaOutSwap, + unsigned short redCount) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(redInput >= APT_DB_RED_INPUT_PWM_A); + APT_PARAM_CHECK_NO_RET(redInput <= APT_DB_RED_INPUT_PWM_B); + APT_PARAM_CHECK_NO_RET(redOutMode >= APT_DB_RED_OUTPUT_NOT_INVERT); + APT_PARAM_CHECK_NO_RET(redOutMode <= APT_DB_RED_OUTPUT_PWM_A); + aptx->DG_CFG.BIT.rg_dg_red_isel = redInput; + aptx->DG_CFG.BIT.rg_dg_red_osel = redOutMode; + aptx->DG_CFG.BIT.rg_dga_osel = dgaOutSwap; + aptx->DG_RED.BIT.rg_dg_red = redCount; +} + +/** + * @brief Configure the falling edge delay (FED) of Dead-Band Generation. + * @param aptx APT register base address. + * @param fedInput The input source of FED counter. + * @param fedOutMode The output of FED counter. + * @param dgbOutSwap The swap mode of Dead-Band Generation output signal B. + * true - Select the output of RED counter. + * false - Select the output of FED counter. + * @param fedCount The count value of FED counter, in units of APT clock. + * @retval None. + */ +static inline void DCL_APT_SetDeadBandFallingEdge(APT_RegStruct *aptx, + APT_FEDInput fedInput, + APT_FEDOutMode fedOutMode, + bool dgbOutSwap, + unsigned short fedCount) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(fedInput >= APT_DB_FED_INPUT_PWM_B); + APT_PARAM_CHECK_NO_RET(fedInput <= APT_DB_FED_INPUT_ZERO); + APT_PARAM_CHECK_NO_RET(fedOutMode >= APT_DB_FED_OUTPUT_NOT_INVERT); + APT_PARAM_CHECK_NO_RET(fedOutMode <= APT_DB_FED_OUTPUT_PWM_B); + aptx->DG_CFG.BIT.rg_dg_fed_isel = fedInput; + aptx->DG_CFG.BIT.rg_dg_fed_osel = fedOutMode; + aptx->DG_CFG.BIT.rg_dgb_osel = dgbOutSwap; + aptx->DG_FED.BIT.rg_dg_fed = fedCount; +} + +/** + * @brief Set buffer load mode of Dead-Band configuration register. + * @param aptx APT register base address. + * @param dgCfgLoadMode Buffer load mode. + * @retval None. + */ +static inline void DCL_APT_SetDGConfigLoadMode(APT_RegStruct *aptx, APT_BufferLoadMode dgCfgLoadMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(dgCfgLoadMode >= APT_BUFFER_DISABLE); + APT_PARAM_CHECK_NO_RET(dgCfgLoadMode <= APT_BUFFER_GLOBAL_LOAD); + unsigned int bufFieldWidth = 4; /* Bit field width of buffer load mode setting */ + aptx->DG_BUF_EN.reg &= (~(0b11 << bufFieldWidth)); /* Clear rg_cfg_gld_en and rg_cfg_buf_en */ + aptx->DG_BUF_EN.reg |= (dgCfgLoadMode << bufFieldWidth); /* Write rg_cfg_gld_en and rg_cfg_buf_en */ +} + +/** + * @brief Enable the buffer load events of DG_CFG register. + * @param aptx APT register base address. + * @param loadEvent The buffer load events of DG_CFG register. + * A logical OR of valid values can be passed as the loadEvent parameter. + * Valid values for loadEvent are: + * APT_DEAD_BAND_LOAD_EVENT_ZERO - When time base counter value equal to zero. + * APT_DEAD_BAND_LOAD_EVENT_PERIOD - When time base counter value equal to period. + * @retval None. + */ +static inline void DCL_APT_SetDGConfigLoadEvent(APT_RegStruct *aptx, unsigned int dgCfgLoadEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + unsigned int dgBufField = 16; /* Field width of continuous PWM action load event setting */ + aptx->DG_BUF_LOAD.reg &= (~(0b11 << dgBufField)); + aptx->DG_BUF_LOAD.reg |= (dgCfgLoadEvent << dgBufField); +} + +/** + * @brief Set buffer load mode of Dead-Band rising edge delay counter register. + * @param aptx APT register base address. + * @param redCntLoadMode Buffer load mode. + * @retval None. + */ +static inline void DCL_APT_SetREDCounterLoadMode(APT_RegStruct *aptx, APT_BufferLoadMode redCntLoadMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(redCntLoadMode >= APT_BUFFER_DISABLE); + APT_PARAM_CHECK_NO_RET(redCntLoadMode <= APT_BUFFER_GLOBAL_LOAD); + aptx->DG_BUF_EN.reg &= (~(0b11 << 0)); /* Clear rg_red_gld_en and rg_red_buf_en */ + aptx->DG_BUF_EN.reg |= (redCntLoadMode << 0); /* Write rg_red_gld_en and rg_red_buf_en */ +} + +/** + * @brief Enable the buffer load events of DG_RED register + * @param aptx APT register base address. + * @param loadEvent The buffer load events of DG_RED register. + * A logical OR of valid values can be passed as the loadEvent parameter. + * Valid values for loadEvent are: + * APT_DEAD_BAND_LOAD_EVENT_ZERO - When time base counter value equal to zero. + * APT_DEAD_BAND_LOAD_EVENT_PERIOD - When time base counter value equal to period. + * @retval None. + */ +static inline void DCL_APT_SetREDCounterLoadEvent(APT_RegStruct *aptx, unsigned int redCntLoadEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->DG_BUF_LOAD.reg &= (~(0b11 << 0)); + aptx->DG_BUF_LOAD.reg |= (redCntLoadEvent << 0); +} + +/** + * @brief Set buffer load mode of Dead-Band falling edge delay counter register. + * @param aptx APT register base address. + * @param fedCntLoadMode Buffer load mode. + * @retval None. + */ +static inline void DCL_APT_SetFEDCounterLoadMode(APT_RegStruct *aptx, APT_BufferLoadMode fedCntLoadMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(fedCntLoadMode >= APT_BUFFER_DISABLE); + APT_PARAM_CHECK_NO_RET(fedCntLoadMode <= APT_BUFFER_GLOBAL_LOAD); + unsigned int bufFieldWidth = 2; /* Bit field width of buffer load mode setting */ + aptx->DG_BUF_EN.reg &= (~(0b11 << bufFieldWidth)); /* Clear rg_fed_gld_en and rg_fed_buf_en */ + aptx->DG_BUF_EN.reg |= (fedCntLoadMode << bufFieldWidth); /* Write rg_fed_gld_en and rg_fed_buf_en */ +} + +/** + * @brief Enable the buffer load events of DG_FED register. + * @param aptx APT register base address. + * @param loadEvent The buffer load events of DG_FED register. + * A logical OR of valid values can be passed as the loadEvent parameter. + * Valid values for loadEvent are: + * APT_DEAD_BAND_LOAD_EVENT_ZERO - When time base counter value equal to zero. + * APT_DEAD_BAND_LOAD_EVENT_PERIOD - When time base counter value equal to period. + * @retval None. + */ +static inline void DCL_APT_SetFEDCounterLoadEvent(APT_RegStruct *aptx, unsigned int fedCntLoadEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + unsigned int dgBufField = 8; /* Field width of continuous PWM action load event setting */ + aptx->DG_BUF_LOAD.reg &= (~(0b11 << dgBufField)); + aptx->DG_BUF_LOAD.reg |= (fedCntLoadEvent << dgBufField); +} + +/* --------------------------------------------------------------------------------------------- */ +/* Output Control (OC) submodule Direct Configuration Layer functions -------------------------- */ +/* --------------------------------------------------------------------------------------------- */ +/** + * @brief Enable an output control event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval None. + */ +static inline void DCL_APT_EnableOutCtrlEvent(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + aptx->OC_MODE.reg |= ocEvent; +} + +/** + * @brief Disable an output control event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval None. + */ +static inline void DCL_APT_DisableOutCtrlEvent(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + aptx->OC_MODE.reg &= ~ocEvent; +} + +/** + * @brief Clear OC_MODE register. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_ClearOCEventReg(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->OC_MODE.reg = 0; +} + +/** + * @brief Set output control mode of an output control event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @param ocEventMode Output control mode. + * @retval None. + */ +static inline void DCL_APT_SetOutCtrlEventMode(APT_RegStruct *aptx, + APT_OutCtrlEvent ocEvent, + APT_OutCtrlMode ocEventMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET((ocEvent >= APT_OC_NO_EVENT) && (ocEvent <= APT_OC_COMBINE_EVENT_B2)); + APT_PARAM_CHECK_NO_RET(ocEventMode >= APT_OUT_CTRL_ONE_SHOT); + APT_PARAM_CHECK_NO_RET(ocEventMode <= APT_OUT_CTRL_CYCLE_BY_CYBLE); + unsigned ocModeOffset = 16; /* Offset of output control mode setting */ + if (ocEventMode == APT_OUT_CTRL_ONE_SHOT) { + aptx->OC_MODE.reg &= (~(ocEvent << ocModeOffset)); /* Set rg_oc_mode_evtx to 0 */ + } else if (ocEventMode == APT_OUT_CTRL_CYCLE_BY_CYBLE) { + aptx->OC_MODE.reg |= (ocEvent << ocModeOffset); /* Set rg_oc_mode_evtx to 1 */ + } +} + +/** + * @brief Set output control action of an output control event. + * @param aptx APT register base address. + * @param channel PWM output channel. + * @param ocEvtDir Output control event that takes into consideration of counter direction. + * @param ocAction Output control action. + * @retval None. + */ +static inline void DCL_APT_SetOutCtrlAction(APT_RegStruct *aptx, + APT_PWMChannel channel, + APT_OutCtrlEventDir ocEvtDir, + APT_OutCtrlAction ocAction) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(channel >= APT_PWM_CHANNEL_A); + APT_PARAM_CHECK_NO_RET(channel <= APT_PWM_CHANNEL_B); + APT_PARAM_CHECK_NO_RET(ocEvtDir >= APT_OC_EVT_GPIO_OR_SYSTEM_UP); + APT_PARAM_CHECK_NO_RET(ocEvtDir <= APT_OC_EVT_COMBINE_EVENT_B2_DOWN); + APT_PARAM_CHECK_NO_RET(ocAction >= APT_OUT_CTRL_ACTION_DISABLE); + APT_PARAM_CHECK_NO_RET(ocAction <= APT_OUT_CTRL_ACTION_HIGH_Z); + if (channel == APT_PWM_CHANNEL_A) { + aptx->OC_ACT_A.reg &= (~(0b111 << ocEvtDir)); + aptx->OC_ACT_A.reg |= (ocAction << ocEvtDir); + } else if (channel == APT_PWM_CHANNEL_B) { + aptx->OC_ACT_B.reg &= (~(0b111 << ocEvtDir)); + aptx->OC_ACT_B.reg |= (ocAction << ocEvtDir); + } +} + +/** + * @brief Get the flag of an output control event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval bool: true, false. + */ +static inline bool DCL_APT_GetOutCtrlEventFlag(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_WITH_RET(ocEvent >= APT_OC_NO_EVENT, false); + APT_PARAM_CHECK_WITH_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2, false); + return ((aptx->OC_EVT_FLAG.reg & ocEvent) == ocEvent); +} + +/** + * @brief Clear the flag of an output control event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval None. + */ +static inline void DCL_APT_ClearOutCtrlEventFlag(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + unsigned int ocFlgOffset = 16; /* Offset of output control flag clear */ + aptx->OC_EVT_FLAG.reg |= (ocEvent << ocFlgOffset); +} + +/** + * @brief Enable the event latch of an output control event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval None. + */ +static inline void DCL_APT_EnableOutCtrlEventLatch(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + aptx->OC_LAT_EN.reg |= ocEvent; +} + +/** + * @brief Disable the event latch of an output control event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval None. + */ +static inline void DCL_APT_DisableOutCtrlEventLatch(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + aptx->OC_LAT_EN.reg &= ~ocEvent; +} + +/** + * @brief Set cycle-by-cycle event latch clear event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @param clrMode Latche clear event of cycle-by-cycle event. + * @retval None. + */ +static inline void DCL_APT_SetCBCLatchClearEvent(APT_RegStruct *aptx, + APT_OutCtrlEvent ocEvent, + APT_CBCClearMode clrMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + APT_PARAM_CHECK_NO_RET(clrMode >= APT_CLEAR_CBC_ON_CNTR_ZERO); + APT_PARAM_CHECK_NO_RET(clrMode <= APT_CLEAR_CBC_ON_CNTR_ZERO_PERIOD); + unsigned int cbcClrOffsetZero = 0; /* Offset of CBC latch clear on counter equal to 0 */ + unsigned int cbcClrOffsetPrd = 16; /* Offset of CBC latch clear on counter euqal to period */ + unsigned int mask = (ocEvent << cbcClrOffsetPrd) | (ocEvent << cbcClrOffsetZero); + mask &= clrMode; + aptx->OC_PRD_CLR.reg |= mask; +} + +/** + * @brief Enable a software output control event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval None. + */ +static inline void DCL_APT_EnableSwOutCtrlEvent(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + aptx->OC_FRC_EVT.reg |= ocEvent; +} + +/** + * @brief Disable a software output control event. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval None. + */ +static inline void DCL_APT_DisableSwOutCtrlEvent(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + aptx->OC_FRC_EVT.reg &= (~ocEvent); +} + +/* --------------------------------------------------------------------------------------------- */ +/* Interrupt Generation (IG) submodule Direct Configuration Layer functions -------------------- */ +/* --------------------------------------------------------------------------------------------- */ +/** + * @brief Enable the output control event to generate an event interrupt. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval None. + */ +static inline void DCL_APT_EnableEventInterrupt(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + aptx->INT_EVT_EN.reg |= ocEvent; +} + +/** + * @brief Disable the output control event to generate an event interrupt.. + * @param aptx APT register base address. + * @param ocEvent Output control event. + * @retval None. + */ +static inline void DCL_APT_DisableEventInterrupt(APT_RegStruct *aptx, APT_OutCtrlEvent ocEvent) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ocEvent >= APT_OC_NO_EVENT); + APT_PARAM_CHECK_NO_RET(ocEvent <= APT_OC_COMBINE_EVENT_B2); + aptx->INT_EVT_EN.reg &= (~ocEvent); +} + +/** + * @brief Enable timer interrupt of APT module. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_EnableTimerInterrupt(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->INT_TMR_EN.BIT.rg_int_en_tmr = BASE_CFG_SET; +} + +/** + * @brief Disable timer interrupt of APT module. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_DisableTimerInterrupt(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->INT_TMR_EN.BIT.rg_int_en_tmr = BASE_CFG_UNSET; +} + +/** + * @brief Get the event interrupt flag. + * @param aptx APT register base address. + * @retval bool: true, false. + */ +static inline bool DCL_APT_GetEventInterruptFlag(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->OC_EVT_FLAG.BIT.ro_int_flag_evt); +} + +/** + * @brief Clear the event interrupt flag. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_ClearEventInterruptFlag(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->OC_EVT_FLAG.BIT.rg_int_clr_evt = BASE_CFG_SET; +} + +/** + * @brief Get the timer interrupt flag. + * @param aptx APT register base address. + * @retval bool: true, false. + */ +static inline bool DCL_APT_GetTimerInterruptFlag(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->INT_TMR_FLAG.BIT.ro_int_flag_tmr); +} + +/** + * @brief Clear the timer interrupt flag. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_ClearTimerInterruptFlag(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->INT_TMR_FLAG.BIT.rg_int_clr_tmr = BASE_CFG_SET; +} + +/** + * @brief Select the source of timer interrupt. + * @param aptx APT register base address. + * @param tmrIntSrc Source of timer interrupt. + * @retval None. + */ +static inline void DCL_APT_SetTimerInterruptSrc(APT_RegStruct *aptx, APT_TimerInterruptSrc tmrIntSrc) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(tmrIntSrc >= APT_INT_SRC_CNTR_DISABLE); + APT_PARAM_CHECK_NO_RET(tmrIntSrc <= APT_INT_SRC_CNTR_CMPD_DOWN); + aptx->INT_TMR_SEL.BIT.rg_int_tmr_sel = tmrIntSrc; +} + +/** + * @brief Enable the synchronization of timer interrupt scale initial count value. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_EnableTimerInterruptCountSyncInit(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->INT_PRSC_CFG.BIT.rg_int_prsc_synen = BASE_CFG_SET; +} + +/** + * @brief Disable the synchronization of timer interrupt scale initial count value. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_DisableTimerInterruptCountSyncInit(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->INT_PRSC_CFG.BIT.rg_int_prsc_synen = BASE_CFG_UNSET; +} + +/** + * @brief Set the initial count value of timer interrupt scale. + * @param aptx APT register base address. + * @param intCntInitVal Initial count value of timer interrupt scale. + * @retval None. + */ +static inline void DCL_APT_SetTimerInterruptCountSyncInitVal(APT_RegStruct *aptx, unsigned short intCntInitVal) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(intCntInitVal <= TIMER_INTERRUPT_CNT_MAX); + aptx->INT_PRSC_CFG.BIT.rg_int_prsc_phs = intCntInitVal; +} + +/** + * @brief Set the count period of timer interrupt scale. + * @param aptx APT register base address. + * @param intCntPeriod Count period of timer interrupt scale. + * @retval None. + */ +static inline void DCL_APT_SetTimerInterruptCountPeriod(APT_RegStruct *aptx, unsigned short intCntPeriod) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(intCntPeriod <= TIMER_INTERRUPT_CNT_MAX); + aptx->INT_PRSC_CFG.BIT.rg_int_prsc_prd = intCntPeriod; +} + +/** + * @brief Get the count value of timer interrupt scale. + * @param aptx APT register base address. + * @retval unsigned short: Count value of timer interrupt scale. + */ +static inline unsigned short DCL_APT_GetTimerInterruptCount(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->INT_PRSC_CFG.BIT.ro_int_prsc_cnt); +} + +/** + * @brief Force the count value of timer interrupt scale to increase. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_ForceTimerInterruptCountIncr(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->INT_PRSC_CFG.BIT.rg_int_prsc_frc = BASE_CFG_SET; +} + +/* --------------------------------------------------------------------------------------------- */ +/* ADC Converter Start (CS) submodule Direct Configuration Layer functions --------------------- */ +/* --------------------------------------------------------------------------------------------- */ +/** + * @brief Enable the ADC trigger channel. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @retval None. + */ +static inline void DCL_APT_EnableADCTrigger(APT_RegStruct *aptx, APT_ADCTriggerChannel csTrgCh) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csTrgCh >= APT_ADC_CONVERSION_START_A); + APT_PARAM_CHECK_NO_RET(csTrgCh <= APT_ADC_CONVERSION_START_B); + if (csTrgCh == APT_ADC_CONVERSION_START_A) { + aptx->CS_TMR_SELA.BIT.rg_csa_en_cs = BASE_CFG_SET; + } else if (csTrgCh == APT_ADC_CONVERSION_START_B) { + aptx->CS_TMR_SELB.BIT.rg_csb_en_cs = BASE_CFG_SET; + } +} + +/** + * @brief Disable the ADC trigger channel. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @retval None. + */ +static inline void DCL_APT_DisableADCTrigger(APT_RegStruct *aptx, APT_ADCTriggerChannel csTrgCh) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csTrgCh >= APT_ADC_CONVERSION_START_A); + APT_PARAM_CHECK_NO_RET(csTrgCh <= APT_ADC_CONVERSION_START_B); + if (csTrgCh == APT_ADC_CONVERSION_START_A) { + aptx->CS_TMR_SELA.BIT.rg_csa_en_cs = BASE_CFG_UNSET; + } else if (csTrgCh == APT_ADC_CONVERSION_START_B) { + aptx->CS_TMR_SELB.BIT.rg_csb_en_cs = BASE_CFG_UNSET; + } +} + +/** + * @brief Select the source of ADC trigger channel. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @param csTrgSrc Source of ADC trigger. + * @retval None. + */ +static inline void DCL_APT_SetADCTriggerSrc(APT_RegStruct *aptx, + APT_ADCTriggerChannel csTrgCh, + APT_ADCTriggerSource csTrgSrc) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csTrgCh >= APT_ADC_CONVERSION_START_A); + APT_PARAM_CHECK_NO_RET(csTrgCh <= APT_ADC_CONVERSION_START_B); + APT_PARAM_CHECK_NO_RET(csTrgSrc <= APT_CS_SRC_CNTR_CMPD_DOWN); + if (csTrgCh == APT_ADC_CONVERSION_START_A) { + aptx->CS_TMR_SELA.BIT.rg_csa_tmr_sel = csTrgSrc; + } else if (csTrgCh == APT_ADC_CONVERSION_START_B) { + aptx->CS_TMR_SELB.BIT.rg_csb_tmr_sel = csTrgSrc; + } +} + +/** + * @brief Enable synchronization of ADC trigger scale initial count value. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @retval None. + */ +static inline void DCL_APT_EnableADCTriggerCountSyncInit(APT_RegStruct *aptx, APT_ADCTriggerChannel csTrgCh) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csTrgCh >= APT_ADC_CONVERSION_START_A); + APT_PARAM_CHECK_NO_RET(csTrgCh <= APT_ADC_CONVERSION_START_B); + if (csTrgCh == APT_ADC_CONVERSION_START_A) { + aptx->CS_PRSCA_CFG.BIT.rg_csa_prsc_synen = BASE_CFG_SET; + } else if (csTrgCh == APT_ADC_CONVERSION_START_B) { + aptx->CS_PRSCB_CFG.BIT.rg_csb_prsc_synen = BASE_CFG_SET; + } +} + +/** + * @brief Disable synchronization of ADC trigger scale initial count value. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @retval None. + */ +static inline void DCL_APT_DisableADCTriggerCountSyncInit(APT_RegStruct *aptx, APT_ADCTriggerChannel csTrgCh) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csTrgCh >= APT_ADC_CONVERSION_START_A); + APT_PARAM_CHECK_NO_RET(csTrgCh <= APT_ADC_CONVERSION_START_B); + if (csTrgCh == APT_ADC_CONVERSION_START_A) { + aptx->CS_PRSCA_CFG.BIT.rg_csa_prsc_synen = BASE_CFG_UNSET; + } else if (csTrgCh == APT_ADC_CONVERSION_START_B) { + aptx->CS_PRSCB_CFG.BIT.rg_csb_prsc_synen = BASE_CFG_UNSET; + } +} + +/** + * @brief Set the initial count value of ADC trigger scale. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @param csCntInitVal Initial count value of ADC trigger scale. + * @retval None. + */ +static inline void DCL_APT_SetADCTriggerCountSyncInitVal(APT_RegStruct *aptx, + APT_ADCTriggerChannel csTrgCh, + unsigned short csCntInitVal) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csTrgCh >= APT_ADC_CONVERSION_START_A); + APT_PARAM_CHECK_NO_RET(csTrgCh <= APT_ADC_CONVERSION_START_B); + APT_PARAM_CHECK_NO_RET(csCntInitVal <= ADC_CONVERSION_START_CNT_MAX); + if (csTrgCh == APT_ADC_CONVERSION_START_A) { + aptx->CS_PRSCA_CFG.BIT.rg_csa_prsc_phs = csCntInitVal; + } else if (csTrgCh == APT_ADC_CONVERSION_START_B) { + aptx->CS_PRSCB_CFG.BIT.rg_csb_prsc_phs = csCntInitVal; + } +} + +/** + * @brief Set the count period of ADC trigger scale. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @param csCntPeriod Count period of ADC trigger scale. + * @retval None. + */ +static inline void DCL_APT_SetADCTriggerCountPeriod(APT_RegStruct *aptx, + APT_ADCTriggerChannel csTrgCh, + unsigned short csCntPeriod) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csTrgCh >= APT_ADC_CONVERSION_START_A); + APT_PARAM_CHECK_NO_RET(csTrgCh <= APT_ADC_CONVERSION_START_B); + APT_PARAM_CHECK_NO_RET(csCntPeriod <= ADC_CONVERSION_START_CNT_MAX); + if (csTrgCh == APT_ADC_CONVERSION_START_A) { + aptx->CS_PRSCA_CFG.BIT.rg_csa_prsc_prd = csCntPeriod; + } else if (csTrgCh == APT_ADC_CONVERSION_START_B) { + aptx->CS_PRSCB_CFG.BIT.rg_csb_prsc_prd = csCntPeriod; + } +} + +/** + * @brief Force the count value of ADC trigger scale to increase. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @retval None. + */ +static inline void DCL_APT_ForceADCTriggerCountIncr(APT_RegStruct *aptx, APT_ADCTriggerChannel csTrgCh) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csTrgCh >= APT_ADC_CONVERSION_START_A); + APT_PARAM_CHECK_NO_RET(csTrgCh <= APT_ADC_CONVERSION_START_B); + if (csTrgCh == APT_ADC_CONVERSION_START_A) { + aptx->CS_PRSCA_CFG.BIT.rg_csa_prsc_frc = BASE_CFG_SET; + } else if (csTrgCh == APT_ADC_CONVERSION_START_B) { + aptx->CS_PRSCB_CFG.BIT.rg_csb_prsc_frc = BASE_CFG_SET; + } +} + +/** + * @brief Get the flag of ADC trigger. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @retval bool: true, false. + */ +static inline bool DCL_APT_GetADCTriggerFlag(APT_RegStruct *aptx, APT_ADCTriggerChannel csTrgCh) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_WITH_RET(csTrgCh >= APT_ADC_CONVERSION_START_A, false); + APT_PARAM_CHECK_WITH_RET(csTrgCh <= APT_ADC_CONVERSION_START_B, false); + return ((aptx->CS_FLAG.reg & csTrgCh) == csTrgCh); +} + +/** + * @brief Clear the flag of ADC trigger. + * @param aptx APT register base address. + * @param csTrgCh ADC trigger channel. + * @retval None. + */ +static inline void DCL_APT_ClearADCTriggerFlag(APT_RegStruct *aptx, APT_ADCTriggerChannel csTrgCh) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csTrgCh >= APT_ADC_CONVERSION_START_A); + APT_PARAM_CHECK_NO_RET(csTrgCh <= APT_ADC_CONVERSION_START_B); + unsigned int trgFlgOffset = 16; /* Offset of ADC trigget flag clear */ + aptx->CS_FLAG.reg |= (csTrgCh << trgFlgOffset); +} + +/** + * @brief Configure the DMA request of ADC trigger. + * @param aptx APT register base address. + * @param csDMAReqSrc DMA request source of ADC Converter Start submodule. + * @param csDMAType DMA request type of ADC Converter Start submodule. + * @retval None. + */ +static inline void DCL_APT_SetADCTriggerDMAReq(APT_RegStruct *aptx, + APT_ADCTrgDMAReqSrc csDMAReqSrc, + APT_ADCTrgDMAReqType csDMAType) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(csDMAReqSrc >= APT_CS_DMA_REQ_SRC_DISABLE); + APT_PARAM_CHECK_NO_RET(csDMAReqSrc <= APT_CS_DMA_REQ_SRC_CHANNEL_B); + APT_PARAM_CHECK_NO_RET(csDMAType <= APT_CS_DMA_SINGLE_REQUEST); + APT_PARAM_CHECK_NO_RET(csDMAType <= APT_CS_DMA_BURST_REQUEST); + aptx->CS_DMA.reg &= (~(0b11 << csDMAType)); + aptx->CS_DMA.reg |= (csDMAReqSrc << csDMAType); +} + +/* --------------------------------------------------------------------------------------------- */ +/* Event Management (EM) submodule Direct Configuration Layer functions ------------------------ */ +/* --------------------------------------------------------------------------------------------- */ +/** + * @brief Set the polarity of GPIO/system event. + * @param aptx APT register base address. + * @param ioSysEvt GPIO or system event. + * @param ioSysEvtPolar Event polarity. + * @retval None. + */ +static inline void DCL_APT_SetIOSysEventPolarity(APT_RegStruct *aptx, + APT_EMIOSysEvent ioSysEvt, + APT_EMEventPolarity ioSysEvtPolar) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(ioSysEvt >= APT_EM_GPIO_EVENT_1); + APT_PARAM_CHECK_NO_RET(ioSysEvt <= APT_EM_SYSTEM_EVENT_3); + APT_PARAM_CHECK_NO_RET(ioSysEvtPolar >= APT_EM_EVENT_POLARITY_NOT_INVERT); + APT_PARAM_CHECK_NO_RET(ioSysEvtPolar <= APT_EM_EVENT_POLARITY_FORCE_HIGH); + aptx->EM_EVTIO_PSEL.reg &= (~(0b11 << ioSysEvt)); + aptx->EM_EVTIO_PSEL.reg |= (ioSysEvtPolar << ioSysEvt); +} + +/** + * @brief Set the polarity of multiplexing event. + * @param aptx APT register base address. + * @param mpEvt Multiplexing event. + * @param mpEvtPolar Event polarity. + * @retval None. + */ +static inline void DCL_APT_SetMpEventPolarity(APT_RegStruct *aptx, + APT_EMMuxEvent mpEvt, + APT_EMEventPolarity mpEvtPolar) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(mpEvt >= APT_EM_MP_EVENT_1); + APT_PARAM_CHECK_NO_RET(mpEvt <= APT_EM_MP_EVENT_6); + APT_PARAM_CHECK_NO_RET(mpEvtPolar >= APT_EM_EVENT_POLARITY_NOT_INVERT); + APT_PARAM_CHECK_NO_RET(mpEvtPolar <= APT_EM_EVENT_POLARITY_FORCE_HIGH); + aptx->EM_EVTMP_PSEL.reg &= (~(0b11 << mpEvt)); + aptx->EM_EVTMP_PSEL.reg |= (mpEvtPolar << mpEvt); +} + +/** + * @brief When the logicial OR result of GPIO events and MUX events is selected as the source of EM group event, + * this function is called to enable which events can participate in the logical OR operation. + * @param aptx APT register base address. + * @param emGroup The group of Event Management, which can be APT_EM_MODULE_A or APT_EM_MODULE_B. + * Each EM group has 2 events. All the 4 group events are enumerated in APT_EMGroupEvent. + * @param event1OREn The logical OR operation source of group event 1. + * @param event2OREn The logical OR operation source of group event 2. + * event1OREn and event2ORE are the logical OR of some valid values. + * Each valid values indicates that the corresponding event is enabled to participate in the + * logical OR operation of EM group event source. These valid values are: + * APT_EM_OR_EN_GPIO_EVENT_1 - GPIO event 1 is enabled + * APT_EM_OR_EN_GPIO_EVENT_2 - GPIO event 2 is enabled + * APT_EM_OR_EN_GPIO_EVENT_3 - GPIO event 3 is enabled + * APT_EM_OR_EN_MUX_EVENT_1 - MUX event 1 is enabled + * APT_EM_OR_EN_MUX_EVENT_2 - MUX event 2 is enabled + * APT_EM_OR_EN_MUX_EVENT_3 - MUX event 3 is enabled + * APT_EM_OR_EN_MUX_EVENT_4 - MUX event 4 is enabled + * APT_EM_OR_EN_MUX_EVENT_5 - MUX event 5 is enabled + * APT_EM_OR_EN_MUX_EVENT_6 - MUX event 6 is enabled + * @retval None. + */ +static inline void DCL_APT_SetEMEventOR(APT_RegStruct *aptx, + APT_EMGroup emGroup, + unsigned short event1OREn, + unsigned short event2OREn) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(emGroup >= APT_EM_MODULE_A); + APT_PARAM_CHECK_NO_RET(emGroup <= APT_EM_MODULE_B); + if (emGroup == APT_EM_MODULE_A) { + aptx->EM_AOR_EN.BIT.rg_em_a1_oren = event1OREn; + aptx->EM_AOR_EN.BIT.rg_em_a2_oren = event2OREn; + } else if (emGroup == APT_EM_MODULE_B) { + aptx->EM_BOR_EN.BIT.rg_em_b1_oren = event1OREn; + aptx->EM_BOR_EN.BIT.rg_em_b2_oren = event2OREn; + } +} + +/** + * @brief Select the combine event source of GRP_A1, GRP_A2, GRP_B1, GRP_B2. + * @param aptx APT register base address. + * @param evtGroup Combine event source group. + * @param combineEvtSrc Combine event source. + * @retval None. + */ +static inline void DCL_APT_SetCombineGroupSrc(APT_RegStruct *aptx, + APT_EMCombineEvtSrcGrp evtGroup, + APT_EMCombineEvtSrc combineEvtSrc) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(evtGroup >= APT_EM_COMBINE_SRC_GRP_A1); + APT_PARAM_CHECK_NO_RET(evtGroup <= APT_EM_COMBINE_SRC_GRP_B2); + APT_PARAM_CHECK_NO_RET(combineEvtSrc >= APT_EM_COMBINE_SRC_EVT_1); + APT_PARAM_CHECK_NO_RET(combineEvtSrc <= APT_EM_COMBINE_SRC_ALL_EVENT_OR); + unsigned int grpEvtFieldWidth = 4; /* Bit field width of combine event group input source setting */ + aptx->EM_MRG_SEL.reg &= (~(0b1111 << (evtGroup * grpEvtFieldWidth))); + aptx->EM_MRG_SEL.reg |= (combineEvtSrc << (evtGroup * grpEvtFieldWidth)); +} + +/** + * @brief Select Combine Mode + * @param aptx APT register base address. + * @param cmbEvt Combine event. + * @param cmbMode Combine mode. + * @retval None. + */ +static inline void DCL_APT_SetCombineEventSrc(APT_RegStruct *aptx, + APT_EMCombineEvent cmbEvt, + APT_EMCombineEvtMode cmbMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(cmbEvt >= APT_EM_COMBINE_EVENT_A1); + APT_PARAM_CHECK_NO_RET(cmbEvt <= APT_EM_COMBINE_EVENT_B2); + APT_PARAM_CHECK_NO_RET(cmbMode >= APT_EM_COMBINE_LOW_LEVEL); + APT_PARAM_CHECK_NO_RET(cmbMode <= APT_EM_COMBINE_EVT2); + unsigned int cmbModeOffset = 16; /* Offset of combine mode */ + unsigned int cmbModeFieldWidth = 4; /* Bit field width of combine mode */ + aptx->EM_MRG_SEL.reg &= (~(0b111 << (cmbModeOffset + cmbEvt * cmbModeFieldWidth))); + aptx->EM_MRG_SEL.reg |= (cmbMode << (cmbModeOffset + cmbEvt * cmbModeFieldWidth)); +} + +/** + * @brief Select the source of Event Management submodule filter event. + * @param aptx APT register base address. + * @param cmbEvt Combine event. + * @retval None. + */ +static inline void DCL_APT_SelectFilterEventInput(APT_RegStruct *aptx, APT_EMCombineEvent cmbEvt) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(cmbEvt >= APT_EM_COMBINE_EVENT_A1); + APT_PARAM_CHECK_NO_RET(cmbEvt <= APT_EM_COMBINE_EVENT_B2); + aptx->EM_OUT_SEL.BIT.rg_evtfilt_sel = cmbEvt; +} + +/** + * @brief Set the output type of combine event. + * @param aptx APT register base address. + * @param cmbEvt Combine event. + * @param filter Whether the output of combine event is filtered. + * @retval None. + */ +static inline void DCL_APT_SetCombineEventOut(APT_RegStruct *aptx, + APT_EMCombineEvent cmbEvt, + APT_EMCombineEventOut filter) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(cmbEvt >= APT_EM_COMBINE_EVENT_A1); + APT_PARAM_CHECK_NO_RET(cmbEvt <= APT_EM_COMBINE_EVENT_B2); + APT_PARAM_CHECK_NO_RET(filter >= APT_EM_COMBINE_EVENT_OUT_ORIG_SIGNAL); + APT_PARAM_CHECK_NO_RET(filter <= APT_EM_COMBINE_EVENT_OUT_FILT_SIGNAL); + aptx->EM_OUT_SEL.reg &= (~(0b1 << cmbEvt)); + aptx->EM_OUT_SEL.reg |= (filter << cmbEvt); +} + +/** + * @brief Enable mask window. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_EnableMaskWindow(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->EM_WD_EN.BIT.rg_mskwd_en = BASE_CFG_SET; +} + +/** + * @brief Disable mask window. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_DisableMaskWindow(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->EM_WD_EN.BIT.rg_mskwd_en = BASE_CFG_UNSET; +} + +/** + * @brief Configure the polarity and reset mode of mask window. + * @param aptx APT register base address. + * @param polar Polarity of mask window. + * @param rstMode Reset mode of mask window. + * @retval None. + */ +static inline void DCL_APT_SetMaskWindow(APT_RegStruct *aptx, APT_MaskWinPolarity polar, APT_MaskWinResetMode rstMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(polar >= APT_BLANK_EVENT_INSIDE_MASK_WIN); + APT_PARAM_CHECK_NO_RET(polar <= APT_BLANK_EVENT_OUTSIDE_MASK_WIN); + APT_PARAM_CHECK_NO_RET(rstMode >= APT_RESET_MASK_WIN_DISABLE); + APT_PARAM_CHECK_NO_RET(rstMode <= APT_RESET_MASK_WIN_CNTR_ZERO_PERIOD); + aptx->EM_WD_EN.BIT.rg_mskwd_psel = polar; + aptx->EM_WD_EN.reg &= (~(0b11 << 0)); + aptx->EM_WD_EN.reg |= rstMode; +} + +/** + * @brief Set the offset and width of mask window. + * @param aptx APT register base address. + * @param mskWinOffset Offset of mask window, in units of time-base clock frequency. + * @retval None. + */ +static inline void DCL_APT_SetMaskWindowOffsetAndWidth(APT_RegStruct *aptx, + unsigned short mskWinOffset, + unsigned short mskWinWidth) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + EM_WD_CNT_REG tmp = aptx->EM_WD_CNT; + tmp.BIT.rg_mskwd_offset = mskWinOffset; + tmp.BIT.rg_mskwd_width = mskWinWidth; + aptx->EM_WD_CNT = tmp; +} + +/** + * @brief Get the count value of mask window offset. + * @param aptx APT register base address. + * @retval unsigned short: Count value of mask window offset. + */ +static inline unsigned short DCL_APT_GetMaskWindowOffsetCount(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->EM_WD_STS.BIT.ro_offset_cnt); +} + +/** + * @brief Get the count value of mask window width. + * @param aptx APT register base address. + * @retval unsigned short: Count value of mask window width. + */ +static inline unsigned short DCL_APT_GetMaskWindowWidthCount(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->EM_WD_STS.BIT.ro_width_cnt); +} + +/** + * @brief Enable valley capture. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_EnableValleyCapture(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->EM_VCAP_CFG.BIT.rg_vcap_en = BASE_CFG_SET; +} + +/** + * @brief Disable valley capture. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_DisableValleyCapture(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->EM_VCAP_CFG.BIT.rg_vcap_en = BASE_CFG_UNSET; +} + +/** + * @brief Select the clock source of valley capture. + * @param aptx APT register base address. + * @param clkMode Clock source of valley capture. + * @retval None. + */ +static inline void DCL_APT_SetValleyCapClockMode(APT_RegStruct *aptx, APT_ValleyCapClkMode clkMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(clkMode >= APT_VALLY_CAP_USE_MAIN_CLOCK); + APT_PARAM_CHECK_NO_RET(clkMode <= APT_VALLEY_CAP_USE_DIVIDER_CLOCK); + aptx->EM_VCAP_CFG.BIT.rg_vcap_div_mode = clkMode; +} + +/** + * @brief Select the trigge source of valley capture. + * @param aptx APT register base address. + * @param vcapSrc Source of valley capture. + * @param edge Edge type of valley capture. + * @retval None. + */ +static inline void DCL_APT_SetValleyCapSrc(APT_RegStruct *aptx, + APT_ValleyCapRstType vcapSrc, + APT_ValleyCapEdgeType edge) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(vcapSrc >= APT_VALLEY_CAP_SRC_DISABLE); + APT_PARAM_CHECK_NO_RET(vcapSrc <= APT_VALLEY_CAP_SRC_COMBINE_EVENT_B2); + APT_PARAM_CHECK_NO_RET(edge >= APT_VALLEY_CAP_RISING_EDGE); + APT_PARAM_CHECK_NO_RET(edge <= APT_VALLEY_CAP_FALLING_EDGE); + aptx->EM_VCAP_CFG.BIT.rg_vcap_trig_sel = vcapSrc; + aptx->EM_VCAP_CFG.BIT.rg_vcap_edg_sel = edge; +} + +/** + * @brief Set the valley capture count value of start edge and stop edge. + * @param aptx APT register base address. + * @param startCount Count value of start edge. + * @param stopCount Count value of stop edge. + * @retval None. + */ +static inline void DCL_APT_SetValleyCapEdgeCount(APT_RegStruct *aptx, + unsigned short startCount, + unsigned short stopCount) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(startCount < stopCount); + aptx->EM_VCAP_CFG.BIT.rg_vcap_sta_edg = startCount; + aptx->EM_VCAP_CFG.BIT.rg_vcap_stp_edg = stopCount; +} + +/** + * @brief Set the delay calibration of valley capture. + * @param aptx APT register base address. + * @param delayMode Delay mode of valley capture. + * @param swDelay Software delay value. + * @retval None. + */ +static inline void DCL_APT_SetValleyCapDelay(APT_RegStruct *aptx, + APT_ValleyDelayMode delayMode, + unsigned short swDelay) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(delayMode >= APT_VCAP_SW_DELAY); + APT_PARAM_CHECK_NO_RET(delayMode <= APT_VCAP_VCNT_DELAY_DIVIDE_32_SW_DELAY); + EM_VCAP_DLY_REG tmp = aptx->EM_VCAP_DLY; + tmp.BIT.rg_vcap_dly_mode = delayMode; + tmp.BIT.rg_vcap_swdly = swDelay; + aptx->EM_VCAP_DLY = tmp; +} + +/** + * @brief Get the delay value of valley capture, including capture count value and software delay value. + * @param aptx APT register base address. + * @retval unsigned short: Value of valley capture. + */ +static inline unsigned short DCL_APT_GetValleyCapDelay(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->EM_VCAP_STS1.BIT.ro_vcap_dly); +} + +/** + * @brief Get the count value between start edge and stop edge. + * @param aptx APT register base address. + * @retval unsigned short: Count value between start edge and stop edge. + */ +static inline unsigned short DCL_APT_GetValleyCapCount(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->EM_VCAP_STS1.BIT.ro_vcap_cnt); +} + +/** + * @brief Get valley capture status of start edge of stop edge. + * @param aptx APT register base address. + * @param edge Start or stop edge of valley capture. + * @retval bool: true, false. + */ +static inline bool DCL_APT_GetValleyEdgeStatus(APT_RegStruct *aptx, APT_ValleyCountEdge edge) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_WITH_RET(edge >= APT_VALLEY_COUNT_START_EDGE, false); + APT_PARAM_CHECK_WITH_RET(edge <= APT_VALLEY_COUNT_STOP_EDGE, false); + if (edge == APT_VALLEY_COUNT_START_EDGE) { + return (aptx->EM_VCAP_STS2.BIT.ro_vcap_sta_edgsts); + } else if (edge == APT_VALLEY_COUNT_STOP_EDGE) { + return (aptx->EM_VCAP_STS2.BIT.ro_vcap_stp_edgsts); + } +} + +/** + * @brief Enable the Event Management submodule edge filter to generate events after configured number of edges. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_EnableFilterDelay(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->EM_FILT_CFG.BIT.rg_filt_dly_en = BASE_CFG_SET; +} + +/** + * @brief Disable the Event Management submodule edge filter. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_DisableEdgeFilter(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->EM_FILT_CFG.BIT.rg_filt_dly_en = BASE_CFG_UNSET; +} + +/** + * @brief Configure the edge filter of Event Management submodule. + * @param aptx APT register base address. + * @param edgeFiltMode Edge filter mode. + * @param edgeCnt Edge count threshold of edge filter. + * @retval None. + */ +static inline void DCL_APT_SetEdgeFilter(APT_RegStruct *aptx, + APT_EMEdgeFilterMode edgeFiltMode, + unsigned short edgeCnt) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(edgeFiltMode >= APT_EM_EDGEFILTER_MODE_RISING); + APT_PARAM_CHECK_NO_RET(edgeFiltMode <= APT_EM_EDGEFILTER_MODE_BOTH); + APT_PARAM_CHECK_NO_RET(edgeCnt <= EDGE_FILTER_EDGE_CNT_MAX); + aptx->EM_FILT_CFG.BIT.rg_filt_edg_sel = edgeFiltMode; + aptx->EM_FILT_CFG.BIT.rg_filt_edg_cnt = edgeCnt; +} + +/** + * @brief Enable time-base counter capture. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_EnableTimerCapture(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->EM_TCAP_CFG.BIT.rg_tcap_en = BASE_CFG_SET; +} + +/** + * @brief Disable time-base counter capture. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_DisableTimerCapture(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->EM_TCAP_CFG.BIT.rg_tcap_en = BASE_CFG_UNSET; +} + +/** + * @brief Get the capture status of time-base counter. + * @param aptx APT register base address. + * @retval bool: true, false + */ +static inline bool DCL_APT_GetTimerCapStatus(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->EM_TCAP_CFG.BIT.ro_tcap_sts); +} + +/** + * @brief Clear the capture status of time-base counter. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_ClearTimerCapStatus(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->EM_TCAP_CFG.BIT.rg_tcap_clr = BASE_CFG_SET; +} + +/** + * @brief Get the time-base counter capture value. + * @param aptx APT register base address. + * @retval unsigned short: Time-base counter capture value. + */ +static inline unsigned short DCL_APT_GetTimerCapValue(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->EM_TCAP_VAL.BIT.ro_tcap_cnt_buf); +} + +/** + * @brief Select the sync-in source of slave APT module. + * @param aptx APT register base address. + * @param syncInSrc Sync-in source of slave APT module. + * @retval None. + */ +static inline void DCL_APT_SelectSyncInPulseSrc(APT_RegStruct *aptx, APT_SyncInSrc syncInSrc) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(syncInSrc >= APT_SYNCIN_SRC_APT0_SYNCOUT); + APT_PARAM_CHECK_NO_RET(syncInSrc <= APT_SYNCIN_SRC_DISABLE); + aptx->SYNI_CFG.BIT.rg_syni_sel = syncInSrc; +} + +/** + * @brief Get the flag of sync-in pulse. + * @param aptx APT register base address. + * @retval bool: true, false. + */ +static inline bool DCL_APT_GetSyncInPulseFlag(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + return (aptx->SYNI_CFG.BIT.ro_syni_flag); +} + +/** + * @brief Clear the flag of sync-in pulse. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_ClearSyncInPulseFlag(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->SYNI_CFG.BIT.rg_syni_clr = BASE_CFG_SET; +} + +/** + * @brief Select the synchronization source of the time-base counter. + * @param aptx APT register base address. + * @param cntrSyncSrc The selection of synchronization source for the time-base counter. + * A logical OR of valid values can be passed as the cntrSyncSrc parameter. + * Valid values for cntrSyncSrc are: + * APT_CNTR_SYNC_SRC_COMBINE_EVENT_A1 - Enable combine event A1 as the counter synchronization source. + * APT_CNTR_SYNC_SRC_COMBINE_EVENT_B1 - Enable combine event B1 as the counter synchronization source. + * APT_CNTR_SYNC_SRC_SYNCIN - Enable Sync-In source as the counter synchronization source. + * @retval None. + */ +static inline void DCL_APT_SetTimeBaseCounterSyncSrc(APT_RegStruct *aptx, unsigned short cntrSyncSrc) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(cntrSyncSrc <= CNTR_SYNC_SOURCE_MAX); + aptx->SYNCNT_CFG.reg = cntrSyncSrc; +} + +/** + * @brief Select the source of synchronization out pulse. + * @param aptx APT register base address. + * @param syncOutSrc The source of synchronization out pulse. + * A logical OR of valid values can be passed as the syncOutSrc parameter. + * Valid values for syncOutSrc are: + * APT_SYNC_OUT_ON_CNTR_ZERO - Generate a sync out pulse when counter equals zero. + * APT_SYNC_OUT_ON_CNTR_PERIOD - Generate a sync out pulse when counter equals period. + * APT_SYNC_OUT_ON_COMBINE_EVENT_A1 - Generate a sync out pulse when combine event A1 happens. + * APT_SYNC_OUT_ON_COMBINE_EVENT_B1 - Generate a sync out pulse when combine event B1 happens. + * APT_SYNC_OUT_ON_CNTR_CMPB - Generate a sync out pulse when counter equals CMPB. + * APT_SYNC_OUT_ON_CNTR_CMPC - Generate a sync out pulse when counter equals CMPC. + * APT_SYNC_OUT_ON_CNTR_CMPD - Generate a sync out pulse when counter equals CMPD. + * @retval None. + */ +static inline void DCL_APT_SetSyncOutPulseSrc(APT_RegStruct *aptx, unsigned short syncOutSrc) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(syncOutSrc <= SYNC_OUT_SOURCE_MAX); + aptx->SYNO_CFG.reg &= (~(0xFF << 0)); + aptx->SYNO_CFG.reg |= (syncOutSrc << 0); +} + +/** + * @brief Set synchronization mode of master APT module. + * @param aptx APT register base address. + * @param syncOutMode Synchronization mode of master APT module. + * @retval None. + */ +static inline void DCL_APT_SetSyncOutMode(APT_RegStruct *aptx, APT_SyncOutMode syncOutMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(syncOutMode >= APT_SYNCOUT_ONE_SHOT_MODE); + APT_PARAM_CHECK_NO_RET(syncOutMode <= APT_SYNCOUT_MULTIPLE_MODE); + aptx->SYNO_CFG.BIT.rg_mode_syno = syncOutMode; +} + +/** + * @brief Select the latch source of one-shot sync-out mode. + * @param aptx APT register base address. + * @param latSetSel Latch source of one-shot sync-out mode. + * @retval None. + */ +static inline void DCL_APT_SelectSyncOutOneShotLatch(APT_RegStruct *aptx, APT_SyncOutLatSetSel latSetSel) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(latSetSel >= APT_SYNCOUT_LATCH_SET_ON_SW_FORCE); + APT_PARAM_CHECK_NO_RET(latSetSel <= APT_SYNCOUT_LATCH_SET_ON_GLB_LOAD); + aptx->SYNO_CFG.BIT.rg_latset_sel = latSetSel; +} + +/** + * @brief When in one-shot sync out mode and rg_latset_otsyn is selected as the latch set condition, + * this function is called to turn the one-shot latch condition ON. + * Upon occurrence of a chosen sync out source event, a sync out pulse is generated and the latch + * will be cleared. Hence writing 1 to rg_latset_otsyn will allow a sync out event to pass through + * and block other sync out source event. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_SetSyncOutOneShotLatch(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->SYNO_CFG.BIT.rg_latset_otsyn = BASE_CFG_SET; +} + +/** + * @brief Select the pulse that causes global buffer load. + * @param aptx APT register base address. + * @param glbLoadEvt The pulse that causes global buffer load. + * A logical OR of valid values can be passed as the syncOutSrc parameter. + * Valid values for gloLoadTrg are: + * APT_GLB_LOAD_ON_CNTR_ZERO - Global buffer load when counter equals zero. + * APT_GLB_LOAD_ON_CNTR_PERIOD - Global buffer load when counter equals period. + * APT_GLB_LOAD_ON_CNTR_SYNC - Global buffer load when counter sync is effective. + * @retval None. + */ +static inline void DCL_APT_SetGlobalLoadEvent(APT_RegStruct *aptx, unsigned short glbLoadEvt) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->GLB_LOAD.reg &= (~(0b111 << 0)); + aptx->GLB_LOAD.reg |= (glbLoadEvt << 0); +} + +/** + * @brief Set the prescale value of multiple global buffer load mode. + * @param aptx APT register base address. + * @param gldCntPeriod Prescale value of multiple global buffer load mode. + * @retval None. + */ +static inline void DCL_APT_SetGlobalLoadPrescale(APT_RegStruct *aptx, unsigned short gldCntPeriod) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(gldCntPeriod <= GLOBAL_LOAD_CNT_MAX); + aptx->GLB_LOAD.BIT.rg_gld_prsc_prd = gldCntPeriod; +} + +/** + * @brief Set the global buffer load mode. + * @param aptx APT register base address. + * @param glbLoadMode Global buffer load mode. + * @retval None. + */ +static inline void DCL_APT_SetGlobalLoadMode(APT_RegStruct *aptx, APT_GlobalLoadMode glbLoadMode) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(glbLoadMode >= APT_GLB_LOAD_ONE_SHOT_MODE); + APT_PARAM_CHECK_NO_RET(glbLoadMode <= APT_GLB_LOAD_MULTIPLE_MODE); + aptx->GLB_LOAD.BIT.rg_mode_gld = glbLoadMode; +} + +/** + * @brief When in one-shot global buffer load mode, this function is called to turn the one-shot latch condition ON. + * Upon occurrence of a chosen global buffer load event, the registers that is set to global buffer load mode + * will load the buffer, and the one-shot latch will be cleared. Hence writing 1 to rg_latset_otgld will + * allow a global buffer load event to pass through and block other global buffer load event. + * @param aptx APT register base address. + * @retval None. + */ +static inline void DCL_APT_SetGlobalLoadOneShotLatch(APT_RegStruct *aptx) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + aptx->GLB_LOAD.BIT.rg_latset_otgld = BASE_CFG_SET; +} + +/** + * @brief Get buffer status of the registers that enable buffer load. + * @param aptx The base address of APT module. + * @param regBuf The buffer of the registers that enable buffer load. + * @retval true: The register buffer is full. + * @retval false: The register buffer is not full. + */ +static inline bool DCL_APT_GetRegBufferStatus(APT_RegStruct *aptx, APT_RegBuffer regBuf) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_WITH_RET(regBuf <= APT_REG_BUFFER_DG_CFG, false); + return ((aptx->LOAD_STS.reg & regBuf) == regBuf); +} + +/** + * @brief Generate a synchronization force event. + * @param aptx The base address of APT module. + * @param frcEvt Synchronization force event. + * @retval None. + */ +static inline void DCL_APT_ForceEvent(APT_RegStruct *aptx, APT_ForceEvtType frcEvt) +{ + APT_ASSERT_PARAM(IsAPTInstance(aptx)); + APT_PARAM_CHECK_NO_RET(frcEvt <= APT_FORCE_EVENT_PWM_ACTION_BUF_LOAD); + aptx->SYN_FRC.reg |= frcEvt; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_APT_IP_H */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/apt/src/apt.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/apt/src/apt.c new file mode 100644 index 00000000..de47e2cd --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/apt/src/apt.c @@ -0,0 +1,1426 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file apt.c + * @author MCU Driver Team + * @brief APT module driver. + * @details This file provides firmware functions to manage the following functionalities of APT module. + * + Initialization and de-initialization functions + * + APT module synchronization functions. + * + PWM waveform configuration and ADC trigger time configuration functions. + * + Interrupt callback function and user registration function + */ + +#include "apt.h" +#include "crg.h" +#define MAX_DUTY 100 +#define ALL_EVT_INT_FLAGS 0xf770000U +#define RERF 4 +/** + * @brief The parameters of PWM waveform. + */ +typedef struct { + APT_PWMAction leftEdgeActA; /**< Action on the left edge of PWM channel A. */ + APT_PWMAction rightEdgeActA; /**< Action on the right edge of PWM channel A. */ + APT_PWMAction leftEdgeActB; /**< Action on the left edge of PWM channel B. */ + APT_PWMAction rightEdgeActB; /**< Action on the right edge of PWM channel B. */ + APT_REDInput redInput; /**< Input source of Dead-Band rising edge delay counter. */ + APT_REDOutMode redOutMode; /**< Output mode of Dead-Band rising edge delay counter. */ + APT_FEDInput fedInput; /**< Input source of Dead-Band falling edge delay counter. */ + APT_FEDOutMode fedOutMode; /**< Output mode of Dead-Band falling edge delay counter. */ +} APT_WaveformPara; + +/** + * @brief Initialize the time-base counter of APT module. + * @param aptHandle APT module handle. + * @retval None. + */ +static void APT_TimeBaseInit(APT_Handle *aptHandle) +{ + aptHandle->baseAddress->TC_MODE.BIT.rg_cnt_mode = aptHandle->waveform.cntMode; + aptHandle->baseAddress->TC_MODE.BIT.rg_div_fac = aptHandle->waveform.dividerFactor; + /* Disable buffer mode of TC_PRD */ + aptHandle->baseAddress->TC_BUF_EN.reg &= (~(0b11 << 0)); + aptHandle->baseAddress->TC_PRD.BIT.rg_cnt_prd = aptHandle->waveform.timerPeriod; + /* Set the override value of divier and timebase counter */ + aptHandle->baseAddress->TC_OVRID.BIT.rg_div_ovrid = aptHandle->waveform.divInitVal; + aptHandle->baseAddress->TC_OVRID.BIT.rg_cnt_ovrid = aptHandle->waveform.cntInitVal; + aptHandle->baseAddress->TC_OVRID.BIT.rg_cnt_ovrid_en = 1; +} + +/** + * @brief Initialize the count compare points for PWM waveform generation. + * @param aptHandle APT module handle. + * @retval None. + */ +static void APT_SetPWMCompareVal(APT_Handle *aptHandle) +{ + /* Do not use divider compare value for PWM wareform generation */ + aptHandle->baseAddress->TC_REFC.BIT.rg_cnt_refcl = aptHandle->waveform.dividerFactor; + aptHandle->baseAddress->TC_REFD.BIT.rg_cnt_refdl = aptHandle->waveform.dividerFactor; + /* Configure the compare point along the left and right edges of PWM waveform */ + TC_REFC_REG tmpC; + TC_REFD_REG tmpD; + /* Set the value of the active register of CMPC and CMPD */ + tmpC = aptHandle->baseAddress->TC_REFC; + tmpC.BIT.rg_cnt_refch = aptHandle->waveform.cntCmpLeftEdge; + aptHandle->baseAddress->TC_REFC = tmpC; + tmpD = aptHandle->baseAddress->TC_REFD; + tmpD.BIT.rg_cnt_refdh = aptHandle->waveform.cntCmpRightEdge; + aptHandle->baseAddress->TC_REFD = tmpD; + /* Set the buffer load mode of CMPC and CMPD */ + if (aptHandle->waveform.cntCmpLoadMode == APT_BUFFER_DISABLE) { + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refc_buf_en = 0; + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refd_buf_en = 0; + } else { + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refc_buf_en = 1; + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refd_buf_en = 1; + unsigned int gldLdEn = (aptHandle->waveform.cntCmpLoadMode == APT_BUFFER_GLOBAL_LOAD) ? 1 : 0; + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refc_gld_en = gldLdEn; + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refd_gld_en = gldLdEn; + /* Set buffer load event */ + unsigned int refBufField = 8; + aptHandle->baseAddress->TC_REF_LOAD.reg &= (~(0x1F << (APT_COMPARE_REFERENCE_C * refBufField))); + aptHandle->baseAddress->TC_REF_LOAD.reg &= (~(0x1F << (APT_COMPARE_REFERENCE_D * refBufField))); + aptHandle->baseAddress->TC_REF_LOAD.reg |= + (aptHandle->waveform.cntCmpLoadEvt << (APT_COMPARE_REFERENCE_C * refBufField)); + aptHandle->baseAddress->TC_REF_LOAD.reg |= + (aptHandle->waveform.cntCmpLoadEvt << (APT_COMPARE_REFERENCE_D * refBufField)); + /* Set the value of the buffer register of CMPC and CMPD */ + tmpC = aptHandle->baseAddress->TC_REFC; + tmpC.BIT.rg_cnt_refch = aptHandle->waveform.cntCmpLeftEdge; + aptHandle->baseAddress->TC_REFC = tmpC; + tmpD = aptHandle->baseAddress->TC_REFD; + tmpD.BIT.rg_cnt_refdh = aptHandle->waveform.cntCmpRightEdge; + aptHandle->baseAddress->TC_REFD = tmpD; + } +} + +/** + * @brief Configure the basic PWM A waveform output according to the waveform parameters. + * @param aptHandle APT module handle. + * @param wavePara PWM waveform parameter. + * @retval None. + */ +static void APT_SetOutputABasicType(APT_Handle *aptHandle, const APT_WaveformPara *wavePara) +{ + switch (aptHandle->waveform.cntMode) { + case APT_COUNT_MODE_UP: + aptHandle->baseAddress->PG_ACT_A.BIT.rg_pga_act_refc_inc = wavePara->leftEdgeActA; + aptHandle->baseAddress->PG_ACT_A.BIT.rg_pga_act_refd_inc = wavePara->rightEdgeActA; + break; + case APT_COUNT_MODE_DOWN: + aptHandle->baseAddress->PG_ACT_A.BIT.rg_pga_act_refc_dec = wavePara->rightEdgeActA; + aptHandle->baseAddress->PG_ACT_A.BIT.rg_pga_act_refd_dec = wavePara->leftEdgeActA; + break; + case APT_COUNT_MODE_UP_DOWN: + aptHandle->baseAddress->PG_ACT_A.BIT.rg_pga_act_refc_inc = wavePara->leftEdgeActA; + aptHandle->baseAddress->PG_ACT_A.BIT.rg_pga_act_refd_dec = wavePara->rightEdgeActA; + break; + default: + break; + } + return; +} + +/** + * @brief Configure the basic PWM B waveform output according to the waveform parameters. + * @param aptHandle APT module handle. + * @param wavePara PWM waveform parameter. + * @retval None. + */ +static void APT_SetOutputBBasicType(APT_Handle *aptHandle, const APT_WaveformPara *wavePara) +{ + switch (aptHandle->waveform.cntMode) { + case APT_COUNT_MODE_UP: + aptHandle->baseAddress->PG_ACT_B.BIT.rg_pgb_act_refc_inc = wavePara->leftEdgeActB; + aptHandle->baseAddress->PG_ACT_B.BIT.rg_pgb_act_refd_inc = wavePara->rightEdgeActB; + break; + case APT_COUNT_MODE_DOWN: + aptHandle->baseAddress->PG_ACT_B.BIT.rg_pgb_act_refc_dec = wavePara->rightEdgeActB; + aptHandle->baseAddress->PG_ACT_B.BIT.rg_pgb_act_refd_dec = wavePara->leftEdgeActB; + break; + case APT_COUNT_MODE_UP_DOWN: + aptHandle->baseAddress->PG_ACT_B.BIT.rg_pgb_act_refc_inc = wavePara->leftEdgeActB; + aptHandle->baseAddress->PG_ACT_B.BIT.rg_pgb_act_refd_dec = wavePara->rightEdgeActB; + break; + default: + break; + } + return; +} + +/** + * @brief Configure the basic PWM waveform output according to the waveform parameters. + * @param aptHandle APT module handle. + * @param wavePara PWM waveform parameter. + * @retval None. + */ +static void APT_SetPWMBasicType(APT_Handle *aptHandle, const APT_WaveformPara *wavePara) +{ + /* Configure PWM waveform of PWM channel A */ + if (aptHandle->waveform.chAOutType == APT_PWM_OUT_BASIC_TYPE) { + APT_SetOutputABasicType(aptHandle, wavePara); + } + /* Configure PWM waveform of PWM channel B */ + if (aptHandle->waveform.chBOutType == APT_PWM_OUT_BASIC_TYPE) { + APT_SetOutputBBasicType(aptHandle, wavePara); + } + /* Configure dead band of PWM channel A and channel B */ + if (aptHandle->waveform.chAOutType == APT_PWM_OUT_BASIC_TYPE && + aptHandle->waveform.chBOutType == APT_PWM_OUT_BASIC_TYPE) { + aptHandle->baseAddress->DG_CFG.BIT.rg_dg_red_isel = wavePara->redInput; + aptHandle->baseAddress->DG_CFG.BIT.rg_dg_red_osel = wavePara->redOutMode; + aptHandle->baseAddress->DG_RED.BIT.rg_dg_red = aptHandle->waveform.deadBandCnt; + aptHandle->baseAddress->DG_CFG.BIT.rg_dg_fed_isel = wavePara->fedInput; + aptHandle->baseAddress->DG_CFG.BIT.rg_dg_fed_osel = wavePara->fedOutMode; + aptHandle->baseAddress->DG_FED.BIT.rg_dg_fed = aptHandle->waveform.deadBandCnt; + } +} + +/** + * @brief Set the actual outputs of PWM channelA and channelB when basic PWM waveform type is not used. + * @param aptHandle APT module handle. + * @retval None. + */ +static void APT_SetContWaveform(APT_Handle *aptHandle) +{ + if (aptHandle->waveform.chAOutType != APT_PWM_OUT_BASIC_TYPE) { + unsigned int contActA = (aptHandle->waveform.chAOutType == APT_PWM_OUT_ALWAYS_LOW) ? 0b01 : 0b10; + aptHandle->baseAddress->PG_ACT_A.BIT.rg_pga_act_zro = contActA; + } + if (aptHandle->waveform.chBOutType != APT_PWM_OUT_BASIC_TYPE) { + unsigned int contActB = (aptHandle->waveform.chBOutType == APT_PWM_OUT_ALWAYS_LOW) ? 0b01 : 0b10; + aptHandle->baseAddress->PG_ACT_B.BIT.rg_pgb_act_zro = contActB; + } +} + +/** + * @brief Initialize the PWM waveform parameters according to the selected PWM basic type. + * @param aptHandle APT module handle. + * @retval None. + */ +static void APT_SetPWMWaveform(APT_Handle *aptHandle) +{ + APT_SetContWaveform(aptHandle); + /* Configure the basic type of PWM waveform */ + APT_WaveformPara wavePara = {0, 0, 0, 0, 0, 0, 0, 0}; + switch (aptHandle->waveform.basicType) { + case APT_PWM_BASIC_A_HIGH_B_LOW: + wavePara.leftEdgeActA = APT_PWM_ACTION_HIGH; + wavePara.rightEdgeActA = APT_PWM_ACTION_LOW; + wavePara.leftEdgeActB = APT_PWM_ACTION_HIGH; + wavePara.rightEdgeActB = APT_PWM_ACTION_LOW; + wavePara.redInput = APT_DB_RED_INPUT_PWM_A; + wavePara.redOutMode = APT_DB_RED_OUTPUT_NOT_INVERT; + wavePara.fedInput = APT_DB_FED_INPUT_PWM_B; + wavePara.fedOutMode = APT_DB_FED_OUTPUT_INVERT; + break; + case APT_PWM_BASIC_A_LOW_B_HIGH: + wavePara.leftEdgeActA = APT_PWM_ACTION_LOW; + wavePara.rightEdgeActA = APT_PWM_ACTION_HIGH; + wavePara.leftEdgeActB = APT_PWM_ACTION_LOW; + wavePara.rightEdgeActB = APT_PWM_ACTION_HIGH; + wavePara.fedInput = APT_DB_FED_INPUT_PWM_A; + wavePara.fedOutMode = APT_DB_FED_OUTPUT_INVERT; + wavePara.redInput = APT_DB_RED_INPUT_PWM_B; + wavePara.redOutMode = APT_DB_RED_OUTPUT_NOT_INVERT; + break; + case APT_PWM_BASIC_A_HIGH_B_HIGH: + wavePara.leftEdgeActA = APT_PWM_ACTION_HIGH; + wavePara.rightEdgeActA = APT_PWM_ACTION_LOW; + wavePara.leftEdgeActB = APT_PWM_ACTION_HIGH; + wavePara.rightEdgeActB = APT_PWM_ACTION_LOW; + wavePara.redInput = APT_DB_RED_INPUT_PWM_A; + wavePara.redOutMode = APT_DB_RED_OUTPUT_NOT_INVERT; + wavePara.fedInput = APT_DB_FED_INPUT_PWM_B; + wavePara.fedOutMode = APT_DB_FED_OUTPUT_NOT_INVERT; + break; + case APT_PWM_BASIC_A_LOW_B_LOW: + wavePara.leftEdgeActA = APT_PWM_ACTION_LOW; + wavePara.rightEdgeActA = APT_PWM_ACTION_HIGH; + wavePara.leftEdgeActB = APT_PWM_ACTION_LOW; + wavePara.rightEdgeActB = APT_PWM_ACTION_HIGH; + wavePara.fedInput = APT_DB_FED_INPUT_PWM_A; + wavePara.fedOutMode = APT_DB_FED_OUTPUT_NOT_INVERT; + wavePara.redInput = APT_DB_RED_INPUT_PWM_B; + wavePara.redOutMode = APT_DB_RED_OUTPUT_NOT_INVERT; + break; + default: + break; + } + APT_SetPWMBasicType(aptHandle, &wavePara); +} + +/** + * @brief Initialize the count compare points for triggering ADC sampling. + * @param aptHandle APT module handle. + * @retval None. + */ +static void APT_SetADCTrgCompareVal(APT_Handle *aptHandle) +{ + /* Do not use divider compare value for ADC trigger source SOCA and SOCB */ + aptHandle->baseAddress->TC_REFA.BIT.rg_cnt_refal = aptHandle->waveform.dividerFactor; + aptHandle->baseAddress->TC_REFB.BIT.rg_cnt_refbl = aptHandle->waveform.dividerFactor; + /* Configure the count compare point for triggering SOCA and SOCB */ + TC_REFA_REG tmpA; + TC_REFB_REG tmpB; + /* Set the value of active register for CMPA and CMPB */ + tmpA = aptHandle->baseAddress->TC_REFA; + tmpA.BIT.rg_cnt_refah = aptHandle->adcTrg.cntCmpSOCA; + aptHandle->baseAddress->TC_REFA = tmpA; + tmpB = aptHandle->baseAddress->TC_REFB; + tmpB.BIT.rg_cnt_refbh = aptHandle->adcTrg.cntCmpSOCB; + aptHandle->baseAddress->TC_REFB = tmpB; + /* Set the buffer load mode of CMPA and CMPB */ + if (aptHandle->adcTrg.cntCmpLoadMode == APT_BUFFER_DISABLE) { + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refa_buf_en = 0; + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refb_buf_en = 0; + } else { + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refa_buf_en = 1; + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refb_buf_en = 1; + unsigned int gldLdEn = (aptHandle->adcTrg.cntCmpLoadMode == APT_BUFFER_GLOBAL_LOAD) ? 1 : 0; + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refa_gld_en = gldLdEn; + aptHandle->baseAddress->TC_BUF_EN.BIT.rg_refb_gld_en = gldLdEn; + /* Set buffer load event */ + unsigned int refBufField = 8; + aptHandle->baseAddress->TC_REF_LOAD.reg &= (~(0x1F << (APT_COMPARE_REFERENCE_A * refBufField))); + aptHandle->baseAddress->TC_REF_LOAD.reg &= (~(0x1F << (APT_COMPARE_REFERENCE_B * refBufField))); + aptHandle->baseAddress->TC_REF_LOAD.reg |= + (aptHandle->adcTrg.cntCmpLoadEvt << (APT_COMPARE_REFERENCE_A * refBufField)); + aptHandle->baseAddress->TC_REF_LOAD.reg |= + (aptHandle->adcTrg.cntCmpLoadEvt << (APT_COMPARE_REFERENCE_B * refBufField)); + /* Set the value of buffer register for CMPA and CMPB */ + tmpA = aptHandle->baseAddress->TC_REFA; + tmpA.BIT.rg_cnt_refah = aptHandle->adcTrg.cntCmpSOCA; + aptHandle->baseAddress->TC_REFA = tmpA; + tmpB = aptHandle->baseAddress->TC_REFB; + tmpB.BIT.rg_cnt_refbh = aptHandle->adcTrg.cntCmpSOCB; + aptHandle->baseAddress->TC_REFB = tmpB; + } +} + +/** + * @brief Initialize the ADC trigger function of APT module. + * @param aptHandle APT module handle + * @retval None. + */ +static void APT_SetADCTrigger(APT_Handle *aptHandle) +{ + APT_PARAM_CHECK_NO_RET(aptHandle->adcTrg.trgScaleSOCA <= ADC_CONVERSION_START_CNT_MAX); + APT_PARAM_CHECK_NO_RET(aptHandle->adcTrg.trgScaleSOCB <= ADC_CONVERSION_START_CNT_MAX); + /* Configure ADC trigger source SOCA */ + aptHandle->baseAddress->CS_TMR_SELA.BIT.rg_csa_tmr_sel = aptHandle->adcTrg.trgSrcSOCA; + aptHandle->baseAddress->CS_PRSCA_CFG.BIT.rg_csa_prsc_prd = aptHandle->adcTrg.trgScaleSOCA; + aptHandle->baseAddress->CS_TMR_SELA.BIT.rg_csa_en_cs = aptHandle->adcTrg.trgEnSOCA; + /* Configure ADC trigger source SOCB */ + aptHandle->baseAddress->CS_TMR_SELB.BIT.rg_csb_tmr_sel = aptHandle->adcTrg.trgSrcSOCB; + aptHandle->baseAddress->CS_PRSCB_CFG.BIT.rg_csb_prsc_prd = aptHandle->adcTrg.trgScaleSOCB; + aptHandle->baseAddress->CS_TMR_SELB.BIT.rg_csb_en_cs = aptHandle->adcTrg.trgEnSOCB; +} + +/** + * @brief Initialize the timer interrupt of APT module. + * @param aptHandle APT module handle. + * @retval None. + */ +static void APT_SetTimerInterrupt(APT_Handle *aptHandle) +{ + APT_PARAM_CHECK_NO_RET(aptHandle->tmrInterrupt.tmrInterruptScale <= TIMER_INTERRUPT_CNT_MAX); + aptHandle->baseAddress->INT_TMR_SEL.BIT.rg_int_tmr_sel = aptHandle->tmrInterrupt.tmrInterruptSrc; + aptHandle->baseAddress->INT_PRSC_CFG.BIT.rg_int_prsc_prd = aptHandle->tmrInterrupt.tmrInterruptScale; + aptHandle->baseAddress->INT_TMR_EN.BIT.rg_int_en_tmr = aptHandle->tmrInterrupt.tmrInterruptEn; +} + +/** + * @brief Initialize the APT hardware configuration based on the APT module handle. + * @param aptHandle APT module handle. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_PWMInit(APT_Handle *aptHandle) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + APT_PARAM_CHECK_WITH_RET(aptHandle->waveform.dividerFactor <= DIVIDER_FACTOR_MAX, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->waveform.divInitVal <= aptHandle->waveform.dividerFactor, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->waveform.cntInitVal < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->waveform.cntCmpLeftEdge > 0, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->waveform.cntCmpLeftEdge < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->waveform.cntCmpRightEdge > 0, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->waveform.cntCmpRightEdge < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->adcTrg.cntCmpSOCA >= 0, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->adcTrg.cntCmpSOCA < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->adcTrg.cntCmpSOCB >= 0, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptHandle->adcTrg.cntCmpSOCB < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + APT_TimeBaseInit(aptHandle); + APT_SetPWMCompareVal(aptHandle); + APT_SetPWMWaveform(aptHandle); + APT_SetADCTrgCompareVal(aptHandle); + APT_SetADCTrigger(aptHandle); + APT_SetTimerInterrupt(aptHandle); + return BASE_STATUS_OK; +} + +/** + * @brief Deinitialize the APT hardware configuration. + * @param aptHandle APT module handle. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_PWMDeInit(APT_Handle *aptHandle) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + aptHandle->userCallBack.EvtInterruptCallBack = NULL; /* The callback function is left blank. */ + aptHandle->userCallBack.TmrInterruptCallBack = NULL; + aptHandle->baseAddress->INT_TMR_EN.BIT.rg_int_en_tmr = BASE_CFG_UNSET; /* Interrupt reset. */ + aptHandle->baseAddress->CS_TMR_SELA.BIT.rg_csa_en_cs = BASE_CFG_UNSET; + aptHandle->baseAddress->CS_TMR_SELB.BIT.rg_csb_en_cs = BASE_CFG_UNSET; + aptHandle->baseAddress->TC_BUF_EN.reg = 0x0; /* APT Buff register reset. */ + aptHandle->baseAddress->TC_REFA.reg = 0x0; /* APT reference dots reset. */ + aptHandle->baseAddress->TC_REFB.reg = 0x0; + aptHandle->baseAddress->TC_REFC.reg = 0x0; + aptHandle->baseAddress->TC_REFD.reg = 0x0; + aptHandle->baseAddress->TC_PRD.BIT.rg_cnt_prd = 0x2710; /* 0x2710: default value */ + aptHandle->baseAddress->PG_ACT_A.reg = 0x0; /* Clear action register. */ + aptHandle->baseAddress->PG_ACT_B.reg = 0x0; + + return BASE_STATUS_OK; +} + +/** + * @brief Configure output control protection mode. + * @param aptHandle APT module handle. + * @param protect Output control protection event handle. + * @retval None. + */ +static void APT_SetOutCtrlProtectMode(APT_Handle *aptHandle, APT_OutCtrlProtect *protect) +{ + /* Set output control protect mode */ + unsigned int ocModeOffset = 16; + unsigned int cbcClrOffsetPrd = 16; + if (protect->ocEventMode == APT_OUT_CTRL_ONE_SHOT) { + aptHandle->baseAddress->OC_MODE.reg &= (~(protect->ocEvent << ocModeOffset)); + } else if (protect->ocEventMode == APT_OUT_CTRL_CYCLE_BY_CYBLE) { + aptHandle->baseAddress->OC_MODE.reg |= (protect->ocEvent << ocModeOffset); + if ((protect->cbcClrMode & APT_CLEAR_CBC_ON_CNTR_ZERO) ==APT_CLEAR_CBC_ON_CNTR_ZERO) { + aptHandle->baseAddress->OC_PRD_CLR.reg |= protect->ocEvent; + } + if ((protect->cbcClrMode & APT_CLEAR_CBC_ON_CNTR_PERIOD) == APT_CLEAR_CBC_ON_CNTR_PERIOD) { + aptHandle->baseAddress->OC_PRD_CLR.reg |= (protect->ocEvent << cbcClrOffsetPrd); + } + } +} + +/** + * @brief Output control protection action selection. + * @param aptHandle APT module handle. + * @param ocAction Out control action. + * @param protect Output control protection event handle. + * @param outCtrlEvent output settings. + * @retval None. + */ +static void APT_SetOutCtrlAction(APT_Handle *aptHandle, APT_OutCtrlAction ocAction, APT_OutCtrlEventDir outCtrlEvent) +{ + /* Set output control action when counting up */ + aptHandle->baseAddress->OC_ACT_A.reg &= (~(0b111 << outCtrlEvent)); + aptHandle->baseAddress->OC_ACT_A.reg |= (ocAction << outCtrlEvent); + aptHandle->baseAddress->OC_ACT_B.reg &= (~(0b111 << outCtrlEvent)); + aptHandle->baseAddress->OC_ACT_B.reg |= (ocAction << outCtrlEvent); +} + +/** + * @brief Indicates the configuration of protection actions for different channels(PWMA and PWMB output action). + * @param aptHandle APT module handle. @ref APT_Handle + * @param ocActionA PWMA output action control. @ref APT_OutCtrlAction + * @param ocActionB PWMB output action control. @ref APT_OutCtrlAction + * @param outCtrlEvent Action configuration in different counting directions. @ref APT_OutCtrlEventDir + * @retval None. + */ +static void APT_SetOutCtrlActionEx(APT_Handle *aptHandle, APT_OutCtrlAction ocActionA, APT_OutCtrlAction ocActionB, + APT_OutCtrlEventDir outCtrlEvent) +{ + /* Set output control action when counting up */ + aptHandle->baseAddress->OC_ACT_A.reg &= (~(0b111 << outCtrlEvent)); + aptHandle->baseAddress->OC_ACT_A.reg |= (ocActionA << outCtrlEvent); + aptHandle->baseAddress->OC_ACT_B.reg &= (~(0b111 << outCtrlEvent)); + aptHandle->baseAddress->OC_ACT_B.reg |= (ocActionB << outCtrlEvent); +} + +/** + * @brief Change APT's OC Event to EM Event. + * @param ocEvent OC Event. + * @param emEvent EM Event. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +static BASE_StatusType APT_ChangeOcEventToEmEvent(APT_OutCtrlEvent ocEvent, APT_EMIOSysEvent *emEvent) +{ + APT_ASSERT_PARAM(emEvent != NULL); + switch (ocEvent) { + case APT_OC_GPIO_EVENT_1: + *emEvent = APT_EM_GPIO_EVENT_1; + break; + case APT_OC_GPIO_EVENT_2: + *emEvent = APT_EM_GPIO_EVENT_2; + break; + case APT_OC_GPIO_EVENT_3: + *emEvent = APT_EM_GPIO_EVENT_3; + break; + case APT_OC_SYSTEM_EVENT_1: + *emEvent = APT_EM_SYSTEM_EVENT_1; + break; + case APT_OC_SYSTEM_EVENT_2: + *emEvent = APT_EM_SYSTEM_EVENT_2; + break; + case APT_OC_SYSTEM_EVENT_3: + *emEvent = APT_EM_SYSTEM_EVENT_3; + break; + default: + return BASE_STATUS_ERROR; + } + + return BASE_STATUS_OK; +} + +/** + * @brief Set combine event out control action. + * @param aptHandle APT module handle. + * @param protect Output control protection event handle. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +static BASE_StatusType APT_SetCombieEvtOutCtrl(APT_Handle *aptHandle, APT_OutCtrlProtect *protect) +{ + switch (protect->ocEvent) { + case APT_OC_COMBINE_EVENT_A1: + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_COMBINE_EVENT_A1_UP); + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_COMBINE_EVENT_A1_DOWN); + break; + case APT_OC_COMBINE_EVENT_A2: + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_COMBINE_EVENT_A2_UP); + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_COMBINE_EVENT_A2_DOWN); + break; + case APT_OC_COMBINE_EVENT_B1: + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_COMBINE_EVENT_B1_UP); + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_COMBINE_EVENT_B1_DOWN); + break; + case APT_OC_COMBINE_EVENT_B2: + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_COMBINE_EVENT_B2_UP); + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_COMBINE_EVENT_B2_DOWN); + break; + default: + return BASE_STATUS_ERROR; + } + + return BASE_STATUS_OK; +} + +/** + * @brief Setting emulation mode of APT module. + * @param aptHandle APT module handle. + * @param protect Output control protection event handle. + * @retval None. + */ +static void APT_OcSetEmulation(APT_Handle *aptHandle, APT_OutCtrlProtect *protect) +{ + aptHandle->baseAddress->TC_MODE.BIT.rg_emu_stop = protect->emMode; + if (protect->emMode > APT_EMULATION_NO_STOP) { + aptHandle->baseAddress->OC_MODE.reg |= APT_OC_SYSTEM_EVENT_1; + } +} + +/** + * @brief Initialize the output control protection event of APT module. + * @param aptHandle APT module handle. + * @param protect Output control protection event handle. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_ProtectInit(APT_Handle *aptHandle, APT_OutCtrlProtect *protect) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(protect != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + APT_PARAM_CHECK_WITH_RET(protect->ocEvent >= APT_OC_GPIO_EVENT_1, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(protect->ocEvent <= APT_OC_COMBINE_EVENT_B2, BASE_STATUS_ERROR); + APT_SetOutCtrlProtectMode(aptHandle, protect); + /* Emultion settings */ + APT_OcSetEmulation(aptHandle, protect); + + if ((protect->ocEvent >= APT_OC_COMBINE_EVENT_A1) && (protect->ocEvent <= APT_OC_COMBINE_EVENT_B2)) { + if (APT_SetCombieEvtOutCtrl(aptHandle, protect) == BASE_STATUS_ERROR) { + return BASE_STATUS_ERROR; + } + } else { + /* Set IO event polarity */ + APT_EMIOSysEvent ioSysEvt; + if (APT_ChangeOcEventToEmEvent(protect->ocEvent, &ioSysEvt) == BASE_STATUS_OK) { + aptHandle->baseAddress->EM_EVTIO_PSEL.reg &= (~(0b11 << ioSysEvt)); + aptHandle->baseAddress->EM_EVTIO_PSEL.reg |= (protect->evtPolarity << ioSysEvt); + } + /* Set output control action when counting up */ + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_GPIO_OR_SYSTEM_UP); + /* Set output control action when counting down */ + APT_SetOutCtrlAction(aptHandle, protect->ocAction, APT_OC_EVT_GPIO_OR_SYSTEM_DOWN); + } + if (protect->ocEventEn == BASE_CFG_ENABLE) { + aptHandle->baseAddress->OC_MODE.reg |= (protect->ocEvent); + } else { + aptHandle->baseAddress->OC_MODE.reg &= (~(protect->ocEvent)); + } + if (protect->ocEvtInterruptEn == BASE_CFG_ENABLE) { + aptHandle->baseAddress->INT_EVT_EN.reg |= (protect->ocEvent); + } else { + aptHandle->baseAddress->INT_EVT_EN.reg &= (~(protect->ocEvent)); + } + return BASE_STATUS_OK; +} + +/** + * @brief Setting protect source event filter, only support the same filter value. + * @param filterNum filter cycle number. + * @retval None. + */ +static void APT_SetEMEventFilterEx(unsigned char filterNum) +{ + unsigned int srcEvent; + unsigned int enableOffset = 24; + unsigned int valueShift = 8; + unsigned int maxEventNum = 3; /* every register can config 3 event's filer */ + for (srcEvent = 0; srcEvent < maxEventNum; srcEvent++) { + SYSCTRL1->APT_POE_FILTER.reg |= 0x1 << (enableOffset + srcEvent); + SYSCTRL1->APT_POE_FILTER.reg |= (((unsigned int)filterNum & 0xff) << (valueShift * srcEvent)); + SYSCTRL1->APT_EVTMP_FILTER.reg |= 0x1 << (enableOffset + srcEvent); + SYSCTRL1->APT_EVTMP_FILTER.reg |= (((unsigned int)filterNum & 0xff) << (valueShift * srcEvent)); + } +} + +/** + * @brief Set protect source event polarity. + * @param aptHandle APT module handle. + * @param polarityMask polarity bit mask. + * @retval None. + */ +static void APT_SetProtectSrcEventPolarityEx(APT_Handle *aptHandle, unsigned int polarityMask) +{ + unsigned int curEvent; + unsigned int curPolarity; + unsigned int curMpEventNum; /* System Compare Event Sources */ + unsigned int curIoEventNum; /* I/O Event Source */ + /* Sets the polarity of the trigger source. */ + for (int i = 0; i <= APT_EM_COMBINE_SRC_EVT_MP_6; i++) { + curEvent = i; + curPolarity = (polarityMask >> curEvent) & 0x01; + if (curEvent >= APT_EM_COMBINE_SRC_EVT_MP_1) { + curMpEventNum = (curEvent - APT_EM_COMBINE_SRC_EVT_MP_1) << 1; + /* set ACMP0~2 and EVTMP4~6 event polarity */ + aptHandle->baseAddress->EM_EVTMP_PSEL.reg &= (~(0b11 << curMpEventNum)); + aptHandle->baseAddress->EM_EVTMP_PSEL.reg |= (curPolarity << curMpEventNum); + } else { + /* set IO event polarity */ + curIoEventNum = curEvent << 1; + aptHandle->baseAddress->EM_EVTIO_PSEL.reg &= (~(0b11 << curIoEventNum)); + aptHandle->baseAddress->EM_EVTIO_PSEL.reg |= (curPolarity << curIoEventNum); + } + } +} + +/** + * @brief Configure output control protection mode. + * @param aptHandle APT module handle. + * @param protect Output control protection event handle. + * @retval None. + */ +static void APT_SetSysEventProtectModeEx(APT_Handle *aptHandle, APT_OutCtrlProtectEx *protect) +{ + /* Set output control protect mode */ + unsigned int ocModeOffset = 16; + unsigned int cbcClrOffsetPrd = 16; + if (protect->ocEventModeEx == APT_OUT_CTRL_ONE_SHOT) { + aptHandle->baseAddress->OC_MODE.reg &= (~(protect->ocSysEvent << ocModeOffset)); + } else if (protect->ocEventModeEx == APT_OUT_CTRL_CYCLE_BY_CYBLE) { + aptHandle->baseAddress->OC_MODE.reg |= (protect->ocSysEvent << ocModeOffset); + if ((protect->cbcClrModeEx & APT_CLEAR_CBC_ON_CNTR_ZERO) ==APT_CLEAR_CBC_ON_CNTR_ZERO) { + aptHandle->baseAddress->OC_PRD_CLR.reg |= protect->ocSysEvent; + } + if ((protect->cbcClrModeEx & APT_CLEAR_CBC_ON_CNTR_PERIOD) == APT_CLEAR_CBC_ON_CNTR_PERIOD) { + aptHandle->baseAddress->OC_PRD_CLR.reg |= (protect->ocSysEvent << cbcClrOffsetPrd); + } + } +} + +/** + * @brief System event protect initialize. + * @param aptHandle APT module handle. + * @param protect Output control protection event data. + * @retval None. + */ +static void APT_SysProtectInitEx(APT_Handle *aptHandle, APT_OutCtrlProtectEx *protect) +{ + APT_SetSysEventProtectModeEx(aptHandle, protect); + if (protect->ocEventEnEx == BASE_CFG_ENABLE) { + aptHandle->baseAddress->OC_MODE.reg |= protect->ocSysEvent; + } else { + aptHandle->baseAddress->OC_MODE.reg &= (~(protect->ocSysEvent)); + } + if (protect->ocEvtInterruptEnEx == BASE_CFG_ENABLE) { + aptHandle->baseAddress->INT_EVT_EN.reg |= protect->ocSysEvent; + } else { + aptHandle->baseAddress->INT_EVT_EN.reg &= (~(protect->ocSysEvent)); + } +} + +/** + * @brief Initialize the output control protection event of APT module (Extended interface). + * @param aptHandle APT module handle. + * @param protect Output control protection event data. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_ProtectInitEx(APT_Handle *aptHandle, APT_OutCtrlProtectEx *protect) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(protect != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + APT_PARAM_CHECK_WITH_RET(protect->originalEvtEx >= 0, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(protect->originalEvtEx <= 0x1FF, BASE_STATUS_ERROR); /* 0x1FF : all event enable */ + unsigned int cbcClrOffsetPrd = 16; + aptHandle->baseAddress->OC_MODE.reg = 0x0; /* clear OC_MODE resgiter */ + aptHandle->baseAddress->TC_MODE.BIT.rg_emu_stop = 0x0; /* don't stop APT when emulation */ + aptHandle->baseAddress->OC_PRD_CLR.reg = 0x0; /* clear OC_PRD_CLR register */ + APT_SysProtectInitEx(aptHandle, protect); + /* event management configuration */ + aptHandle->baseAddress->EM_MRG_SEL.BIT.rg_em_a1_sel = EM_COMBINE_A1_SRC_ENABLE_ALL; /* open logic OR */ + aptHandle->baseAddress->EM_AOR_EN.BIT.rg_em_a1_oren = protect->originalEvtEx; /* open selected event */ + APT_SetProtectSrcEventPolarityEx(aptHandle, protect->evtPolarityMaskEx); + APT_SetEMEventFilterEx(protect->filterCycleNumEx); + aptHandle->baseAddress->EM_MRG_SEL.BIT.rg_evta1t_sel= APT_EM_COMBINE_EVT1; /* all event input to combine event A1 */ + /* out control configuration */ + APT_SetOutCtrlActionEx(aptHandle, protect->ocActionEx, protect->ocActionBEx, APT_OC_EVT_COMBINE_EVENT_A1_UP); + APT_SetOutCtrlActionEx(aptHandle, protect->ocActionEx, protect->ocActionBEx, APT_OC_EVT_COMBINE_EVENT_A1_DOWN); + /* system event protect setting. */ + APT_SetOutCtrlActionEx(aptHandle, protect->ocActionEx, protect->ocActionBEx, APT_OC_EVT_GPIO_OR_SYSTEM_UP); + APT_SetOutCtrlActionEx(aptHandle, protect->ocActionEx, protect->ocActionBEx, APT_OC_EVT_GPIO_OR_SYSTEM_DOWN); + aptHandle->baseAddress->OC_MODE.BIT.rg_oc_mode_evta1 = protect->ocEventModeEx; /* set protect mode */ + if ((protect->cbcClrModeEx & APT_CLEAR_CBC_ON_CNTR_ZERO) ==APT_CLEAR_CBC_ON_CNTR_ZERO) { + aptHandle->baseAddress->OC_PRD_CLR.reg |= APT_OC_COMBINE_EVENT_A1; /* set CBC clear mode */ + } + if ((protect->cbcClrModeEx & APT_CLEAR_CBC_ON_CNTR_PERIOD) == APT_CLEAR_CBC_ON_CNTR_PERIOD) { + aptHandle->baseAddress->OC_PRD_CLR.reg |= (APT_OC_COMBINE_EVENT_A1 << cbcClrOffsetPrd); + } + if (protect->ocEventEnEx == BASE_CFG_ENABLE) { + aptHandle->baseAddress->OC_MODE.reg |= APT_OC_COMBINE_EVENT_A1; /* OC input combine event A1 */ + } else { + aptHandle->baseAddress->OC_MODE.reg &= (~(APT_OC_COMBINE_EVENT_A1)); + } + if (protect->ocEvtInterruptEnEx == BASE_CFG_ENABLE) { + aptHandle->baseAddress->INT_EVT_EN.reg |= (APT_OC_COMBINE_EVENT_A1); + } else { + aptHandle->baseAddress->INT_EVT_EN.reg &= (~(APT_OC_COMBINE_EVENT_A1)); /* enable combine event A1 interrupt */ + } + return BASE_STATUS_OK; +} + +/** + * @brief De-initialize the output control protection event of APT module (Extended interface). + * @param aptHandle APT module handle. + * @param protect Output control protection event handle. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_ProtectDeInitEx(APT_Handle *aptHandle, APT_OutCtrlProtectEx *protect) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(protect != NULL); + protect->ocEventEnEx = BASE_CFG_DISABLE; + aptHandle->baseAddress->OC_MODE.reg = 0x700070; /* 0x7000070: default value */ + + return BASE_STATUS_OK; +} + +/** + * @brief De-initialize the output control protection event of APT module. + * @param aptHandle APT module handle. + * @param protect Output control protection event handle. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_ProtectDeInit(APT_Handle *aptHandle, APT_OutCtrlProtect *protect) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(protect != NULL); + protect->ocEventEn = BASE_CFG_DISABLE; + aptHandle->baseAddress->OC_MODE.reg = 0x700070; /* 0x7000070: default value */ + + return BASE_STATUS_OK; +} + +/** + * @brief Set event management's source events polarity. + * @param aptHandle APT module handle. + * @param emEvtSrc Source event selection. + * @param emEvtPolar Event polarity. + * @retval None. + */ +static void APT_SetEMInputEvtPolarity(APT_Handle *aptHandle, APT_EMCombineEvtSrc emEvtSrc, + APT_EMEventPolarity emEvtPolar) +{ + unsigned int eventPolarity; + if (emEvtSrc >= APT_EM_COMBINE_SRC_EVT_MP_1) { + /* set multiplex event polarity */ + eventPolarity = (emEvtSrc - APT_EM_COMBINE_SRC_EVT_MP_1) << 1; + aptHandle->baseAddress->EM_EVTMP_PSEL.reg &= (~(0b11 << eventPolarity)); + aptHandle->baseAddress->EM_EVTMP_PSEL.reg |= (emEvtPolar << eventPolarity); + } else { + /* set io event polarity */ + eventPolarity = (emEvtSrc) << 1; + aptHandle->baseAddress->EM_EVTIO_PSEL.reg &= (~(0b11 << eventPolarity)); + aptHandle->baseAddress->EM_EVTIO_PSEL.reg |= (emEvtPolar << eventPolarity); + } +} + + +/** + * @brief Set event management's source events input and event combine. + * (if enable logic or function, it do not support setting polarity, need use DCL to set polarity.) + * @param aptHandle APT module handle. + * @param emEvent EM event handle. + * @retval None. + */ +static void APT_EMCombineEventInit(APT_Handle *aptHandle, APT_CombineEvt *emEvent) +{ + unsigned int evtNum; + for (evtNum = 0; evtNum < EM_CMB_EVT_NUM; evtNum++) { + /* if select logical or */ + aptHandle->baseAddress->EM_MRG_SEL.reg |= emEvent[evtNum].emEvtSrc << (evtNum * EM_CMB_SRC_SEL_INTERVAL); + if (emEvent[evtNum].emEvtSrc == APT_EM_COMBINE_SRC_ALL_EVENT_OR) { + /* enable logical or events */ + if (evtNum < APT_EM_COMBINE_EVENT_B1) { + aptHandle->baseAddress->EM_AOR_EN.reg |= (emEvent[evtNum].emEvtOrEnBits << (evtNum * EM_OR_INTERVAL)); + } else { + aptHandle->baseAddress->EM_BOR_EN.reg |= (emEvent[evtNum].emEvtOrEnBits << \ + ((evtNum - APT_EM_COMBINE_EVENT_B1) * EM_OR_INTERVAL)); + } + } else { + /* set input event's polarity */ + APT_SetEMInputEvtPolarity(aptHandle, emEvent[evtNum].emEvtSrc, emEvent[evtNum].emEvtPolar); + } + aptHandle->baseAddress->EM_MRG_SEL.reg |= (emEvent[evtNum].emEvtCombineMode << \ + (evtNum * EM_CMB_MODE_INTERVAL)) << EM_CMB_MODE_OFFSET; + } +} + +/** + * @brief Initialize mask window and capture function of event management. + * @param aptHandle APT module handle. + * @param emWdAndCp Mask window and capture configuration handle. + * @retval None. + */ +static void APT_EMWdAndCapInit(APT_Handle *aptHandle, APT_WdAndCap *emWdAndCap) +{ + if (emWdAndCap->wdEnable == true) { + /* filter source select */ + aptHandle->baseAddress->EM_OUT_SEL.BIT.rg_evtfilt_sel = emWdAndCap->eventSel; + /* set window offset */ + aptHandle->baseAddress->EM_WD_CNT.BIT.rg_mskwd_offset = emWdAndCap->wdOffset; + /* set window width */ + aptHandle->baseAddress->EM_WD_CNT.BIT.rg_mskwd_width = emWdAndCap->wdWidth; + /* window polarit select */ + aptHandle->baseAddress->EM_WD_EN.BIT.rg_mskwd_psel = emWdAndCap->wdPolar; + /* capture clear mode */ + aptHandle->baseAddress->EM_WD_EN.BIT.rg_mskwd_alg_zroen = emWdAndCap->wdStartAndCapClr & 0x1; + aptHandle->baseAddress->EM_WD_EN.BIT.rg_mskwd_alg_prden = (emWdAndCap->wdStartAndCapClr >> 0x1) & 0x1; + /* enable capture function */ + if (emWdAndCap->emCapEnable == true) { + aptHandle->baseAddress->EM_TCAP_CFG.BIT.rg_tcap_en = BASE_CFG_SET; + } + } +} + +/** + * @brief Initialize vally switch function of event management. + * @param aptHandle APT module handle. + * @param emVallySw Valley switch configuration handle. + * @retval None. + */ +static void APT_EMVallySwInit(APT_Handle *aptHandle, APT_ValleySw *emValleySw) +{ + if (emValleySw->vsEnable == true) { + /* filter edge */ + aptHandle->baseAddress->EM_FILT_CFG.BIT.rg_filt_edg_sel = emValleySw->vsFilerEdgeSel; + /* filter count */ + aptHandle->baseAddress->EM_FILT_CFG.BIT.rg_filt_edg_cnt = emValleySw->vsFilterCnt; + /* clear setting */ + aptHandle->baseAddress->EM_VCAP_CFG.BIT.rg_vcap_trig_sel = emValleySw->vsClrType; + /* capture edge */ + aptHandle->baseAddress->EM_VCAP_CFG.BIT.rg_vcap_edg_sel = emValleySw->vsCapEdgeSel; + /* capture start edge */ + aptHandle->baseAddress->EM_VCAP_CFG.BIT.rg_vcap_sta_edg = emValleySw->vsCapStartEdge; + /* capture end edge */ + aptHandle->baseAddress->EM_VCAP_CFG.BIT.rg_vcap_sta_edg = emValleySw->vsCapStartEdge; + /* capture delay mode */ + aptHandle->baseAddress->EM_VCAP_DLY.BIT.rg_vcap_dly_mode = emValleySw->vsCapDelayMode; + /* Calibrate delay */ + aptHandle->baseAddress->EM_VCAP_DLY.BIT.rg_vcap_swdly = emValleySw->vsCapSoftDelay; + } +} + +/** + * @brief Event management initialization interface. + * @param aptHandle APT module handle. + * @param eventManage Event management handle. + * @retval None. + */ +BASE_StatusType HAL_APT_EMInit(APT_Handle *aptHandle, APT_EventManage *eventManage) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(eventManage != NULL); + if (eventManage->emEnable == true) { /* event manage enable */ + APT_EMCombineEventInit(aptHandle, eventManage->emEvt); /* init combine event */ + if ((eventManage->emValleySw.vsEnable == true) || (eventManage->emWdAndCap.wdEnable == true)) { + aptHandle->baseAddress->EM_OUT_SEL.reg |= EM_OUT_EVT_FILTER_EN; + APT_EMWdAndCapInit(aptHandle, &(eventManage->emWdAndCap)); /* init window and capture function */ + APT_EMVallySwInit(aptHandle, &(eventManage->emValleySw)); /* init valley switch */ + } + return BASE_STATUS_OK; + } + return BASE_STATUS_ERROR; +} + + +/** + * @brief Get capture value of Event management. + * @param aptHandle APT module handle. + * @retval unsignd short: Capture counting value. + */ +unsigned short HAL_APT_EMGetCapValue(APT_Handle *aptHandle) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + unsigned short capValue = 0; + /* if capture valid */ + if (aptHandle->baseAddress->EM_TCAP_CFG.BIT.rg_tcap_en == BASE_CFG_ENABLE) { + /* read capture value */ + capValue = aptHandle->baseAddress->EM_TCAP_VAL.BIT.ro_tcap_cnt_rt; + } + + return capValue; +} + +/** + * @brief Set window's offset and width of Event management. + * @param aptHandle APT module handle. + * @param offset Window's offset. + * @param width Window's width. + * @retval None. + */ +void HAL_APT_EMSetWdOffsetAndWidth(APT_Handle *aptHandle, unsigned short offset, unsigned short width) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + aptHandle->baseAddress->EM_WD_CNT.BIT.rg_mskwd_offset = offset; + aptHandle->baseAddress->EM_WD_CNT.BIT.rg_mskwd_width = width; +} + +/** + * @brief Set vallet switch's software calibrate of Event management. + * @param aptHandle APT module handle. + * @param calibrate Delay calibration. + * @retval None. + */ +void HAL_APT_EMSetValleySwithSoftDelay(APT_Handle *aptHandle, unsigned short calibrate) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + aptHandle->baseAddress->EM_VCAP_DLY.BIT.rg_vcap_swdly = calibrate; +} + +/** + * @brief Disable PWMA and PWMB output. PWMA and PWMB output low level. + * @param aptHandle APT module handle. + * @retval None. + */ +void HAL_APT_ForcePWMOutputLow(APT_Handle *aptHandle) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + DCL_APT_ForcePWMOutputLow(aptHandle->baseAddress); + + return; +} + +/** + * @brief Initialize the master APT module when using multiple sync-out mode. + * @param aptHandle APT module handle. + * @param syncOutSrc Master APT module synchronization source. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_MasterSyncInit(APT_Handle *aptHandle, unsigned short syncOutSrc) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + APT_PARAM_CHECK_WITH_RET(syncOutSrc <= SYNC_OUT_SOURCE_MAX, BASE_STATUS_ERROR); + /* Configure the sync-out pulse source of APT module synchronization */ + aptHandle->baseAddress->SYNO_CFG.reg &= (~(0xFF << 0)); + aptHandle->baseAddress->SYNO_CFG.reg |= (syncOutSrc << 0); + aptHandle->baseAddress->SYNO_CFG.BIT.rg_mode_syno = APT_SYNCOUT_MULTIPLE_MODE; + return BASE_STATUS_OK; +} + +/** + * @brief Initialize the slave APT module. + * @param aptHandle APT module handle. + * @param slaveSyncIn Slave APT module synchronization handle. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_SlaveSyncInit(APT_Handle *aptHandle, APT_SlaveSyncIn *slaveSyncIn) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(slaveSyncIn != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + APT_PARAM_CHECK_WITH_RET(slaveSyncIn->divPhase <= aptHandle->waveform.dividerFactor, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(slaveSyncIn->cntPhase < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(slaveSyncIn->cntrSyncSrc <= CNTR_SYNC_SOURCE_MAX, BASE_STATUS_ERROR); + + aptHandle->baseAddress->TC_PHS.BIT.rg_cnt_dir = slaveSyncIn->syncCntMode; + aptHandle->baseAddress->TC_PHS.BIT.rg_div_phs = slaveSyncIn->divPhase; + TC_PHS_REG tmp = aptHandle->baseAddress->TC_PHS; + tmp.BIT.rg_cnt_phs = slaveSyncIn->cntPhase; + aptHandle->baseAddress->TC_PHS = tmp; + + aptHandle->baseAddress->SYNI_CFG.BIT.rg_syni_sel = slaveSyncIn->syncInSrc; + aptHandle->baseAddress->SYNCNT_CFG.reg = slaveSyncIn->cntrSyncSrc; + return BASE_STATUS_OK; +} + +/** + * @brief Start all of the used APT modules simultaneously. + * @param aptRunMask A logical OR of valid values that can be passed as the aptRunMask. + * Valid values for aptRunMask are: + * RUN_APT0 - apt0_run bit in SYSCTRL1 register. + * RUN_APT1 - apt1_run bit in SYSCTRL1 register. + * RUN_APT2 - apt2_run bit in SYSCTRL1 register. + * RUN_APT3 - apt3_run bit in SYSCTRL1 register. + * RUN_APT4 - apt4_run bit in SYSCTRL1 register. + * RUN_APT5 - apt5_run bit in SYSCTRL1 register. + * RUN_APT6 - apt6_run bit in SYSCTRL1 register. + * RUN_APT7 - apt7_run bit in SYSCTRL1 register. + * RUN_APT8 - apt8_run bit in SYSCTRL1 register. + * @retval None. + */ +void HAL_APT_StartModule(unsigned int aptRunMask) +{ + SYSCTRL1->APT_RUN.reg |= aptRunMask; +} + +/** + * @brief Stop all of the used APT modules simultaneously. + * @param aptRunMask A logical OR of valid values that can be passed as the aptRunMask. + * Valid values for aptRunMask are: + * RUN_APT0 - apt0_run bit in SYSCTRL1 register. + * RUN_APT1 - apt1_run bit in SYSCTRL1 register. + * RUN_APT2 - apt2_run bit in SYSCTRL1 register. + * RUN_APT3 - apt3_run bit in SYSCTRL1 register. + * RUN_APT4 - apt4_run bit in SYSCTRL1 register. + * RUN_APT5 - apt5_run bit in SYSCTRL1 register. + * RUN_APT6 - apt6_run bit in SYSCTRL1 register. + * RUN_APT7 - apt7_run bit in SYSCTRL1 register. + * RUN_APT8 - apt8_run bit in SYSCTRL1 register. + * @retval None. + */ +void HAL_APT_StopModule(unsigned int aptRunMask) +{ + SYSCTRL1->APT_RUN.reg &= (~aptRunMask); +} + +/** + * @brief Set the count compare points along the left and right edges of PWM waveform. + * @param aptHandle APT module handle. + * @param cntCmpLeftEdge The count compare point of the left edge of PWM waveform. Pull High on left edge. + * @param cntCmpRightEdge The count compare point of the right edge of PWM waveform. Pull Low on right edge. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_SetPWMDuty(APT_Handle *aptHandle, unsigned short cntCmpLeftEdge, \ + unsigned short cntCmpRightEdge) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + APT_PARAM_CHECK_WITH_RET(cntCmpLeftEdge > 0, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(cntCmpLeftEdge < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(cntCmpRightEdge > 0, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(cntCmpRightEdge < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + TC_REFC_REG tmpC; + TC_REFD_REG tmpD; + tmpC = aptHandle->baseAddress->TC_REFC; + tmpC.BIT.rg_cnt_refch = cntCmpLeftEdge; + aptHandle->baseAddress->TC_REFC = tmpC; + tmpD = aptHandle->baseAddress->TC_REFD; + tmpD.BIT.rg_cnt_refdh = cntCmpRightEdge; + aptHandle->baseAddress->TC_REFD = tmpD; + return BASE_STATUS_OK; +} + +/** + * @brief Set the count compare points along the left and right edges of PWM waveform. + * @param aptHandle APT module handle. + * @param duty PWM duty. Range: 1 ~ 99. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_SetPWMDutyByNumber(APT_Handle *aptHandle, unsigned int duty) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + APT_PARAM_CHECK_WITH_RET(duty < MAX_DUTY, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(duty > 0, BASE_STATUS_ERROR); + + unsigned int cntCmpLeftEdge, cntCmpRightEdge; + TC_REFC_REG tmpC; + TC_REFD_REG tmpD; + + if (aptHandle->waveform.cntMode == APT_COUNT_MODE_UP_DOWN) { + cntCmpLeftEdge = aptHandle->waveform.timerPeriod - \ + (int)(((float)aptHandle->waveform.timerPeriod / MAX_DUTY) * duty); + cntCmpRightEdge = cntCmpLeftEdge; + } else { + cntCmpLeftEdge = 1; + cntCmpRightEdge = (int)(((float)aptHandle->waveform.timerPeriod / MAX_DUTY) * duty + cntCmpLeftEdge); + } + tmpC = aptHandle->baseAddress->TC_REFC; + tmpC.BIT.rg_cnt_refch = cntCmpLeftEdge; + aptHandle->baseAddress->TC_REFC = tmpC; + tmpD = aptHandle->baseAddress->TC_REFD; + tmpD.BIT.rg_cnt_refdh = cntCmpRightEdge; + aptHandle->baseAddress->TC_REFD = tmpD; + return BASE_STATUS_OK; +} + +/** + * @brief Set the count compare points to trigger the ADC sampling. + * @param aptHandle APT module handle. + * @param cntCmpSOCA The count compare point for triggering SOCA. + * @param cntCmpSOCB The count compare point for triggering SOCB. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_SetADCTriggerTime(APT_Handle *aptHandle, unsigned short cntCmpSOCA, unsigned short cntCmpSOCB) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + APT_PARAM_CHECK_WITH_RET(cntCmpSOCA > 0, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(cntCmpSOCA < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(cntCmpSOCB > 0, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(cntCmpSOCB < aptHandle->waveform.timerPeriod, BASE_STATUS_ERROR); + TC_REFA_REG tmpA; + TC_REFB_REG tmpB; + tmpA = aptHandle->baseAddress->TC_REFA; + tmpA.BIT.rg_cnt_refah = cntCmpSOCA; + aptHandle->baseAddress->TC_REFA = tmpA; + tmpB = aptHandle->baseAddress->TC_REFB; + tmpB.BIT.rg_cnt_refbh = cntCmpSOCB; + aptHandle->baseAddress->TC_REFB = tmpB; + return BASE_STATUS_OK; +} + +/** + * @brief set outputs of channelA when use APT_PWM_BASIC_A_HIGH_B_HIGH. + * @param aptHandle APT module handle. + * @param aptAction output action type. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +static BASE_StatusType APT_SetActionChannelA(APT_Handle *aptHandle, APT_PWMChannelOutType aptAction) +{ + switch (aptAction) { + case APT_PWM_OUT_BASIC_TYPE: + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pga_frc_en = BASE_CFG_UNSET; /* disable force action */ + break; + case APT_PWM_OUT_ALWAYS_LOW: + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pga_frc_act = APT_PWM_OUT_ALWAYS_LOW; /* force output low */ + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pga_frc_en = BASE_CFG_SET; + break; + case APT_PWM_OUT_ALWAYS_HIGH: + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pga_frc_act = APT_PWM_OUT_ALWAYS_HIGH; /* force output high */ + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pga_frc_en = BASE_CFG_SET; + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief set outputs of channelB when use APT_PWM_BASIC_A_HIGH_B_HIGH. + * @param aptHandle APT module handle. + * @param aptAction output action type. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +static BASE_StatusType APT_SetActionChannelB(APT_Handle *aptHandle, APT_PWMChannelOutType aptAction) +{ + switch (aptAction) { + case APT_PWM_OUT_BASIC_TYPE: + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pgb_frc_en = BASE_CFG_UNSET; /* disable force action */ + break; + case APT_PWM_OUT_ALWAYS_LOW: + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pgb_frc_act = APT_PWM_OUT_ALWAYS_LOW; /* force output low */ + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pgb_frc_en = BASE_CFG_SET; + break; + case APT_PWM_OUT_ALWAYS_HIGH: + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pgb_frc_act = APT_PWM_OUT_ALWAYS_HIGH; /* force output high */ + aptHandle->baseAddress->PG_OUT_FRC.BIT.rg_pgb_frc_en = BASE_CFG_SET; + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief Change outputs of channelA and channelB when use APT_PWM_BASIC_A_HIGH_B_HIGH. + * @param aptHandle APT module handle. + * @param channel channel number. + * @param aptAction output action type. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_APT_ChangeOutputType(APT_Handle *aptHandle, APT_PWMChannel channel, APT_PWMChannelOutType aptAction) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(aptHandle->baseAddress != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + APT_PARAM_CHECK_WITH_RET(channel >= APT_PWM_CHANNEL_A, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(channel <= APT_PWM_CHANNEL_B, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptAction >= APT_PWM_OUT_BASIC_TYPE, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(aptAction <= APT_PWM_OUT_ALWAYS_HIGH, BASE_STATUS_ERROR); + /* only use in APT_PWM_BASIC_A_HIGH_B_HIGH mode */ + if (aptHandle->waveform.basicType != APT_PWM_BASIC_A_HIGH_B_HIGH) { + return BASE_STATUS_ERROR; + } + if (channel == APT_PWM_CHANNEL_A) { + return APT_SetActionChannelA(aptHandle, aptAction); /* set channnelA's action */ + } else if (channel == APT_PWM_CHANNEL_B) { + return APT_SetActionChannelB(aptHandle, aptAction); /* set channelB's action */ + } else { + return BASE_STATUS_ERROR; /* error channnel number */ + } +} + +/** + * @brief APT event interrupt service processing function. + * @param handle APT module handle. + * @retval None. + */ +void HAL_APT_EventIrqHandler(void *handle) +{ + APT_ASSERT_PARAM(handle != NULL); + APT_Handle *aptHandle = (APT_Handle *)handle; + /* Continuous protection cannot clear the event flag. Clear the event flag by users. */ + if (aptHandle->baseAddress->OC_MODE.BIT.rg_oc_mode_evta1 == 0x1) { /* Protection by period. */ + /* Interrupt of the periodic protection clear event. */ + aptHandle->baseAddress->OC_EVT_FLAG.reg |= ALL_EVT_INT_FLAGS; + } + aptHandle->baseAddress->OC_EVT_FLAG.BIT.rg_int_clr_evt = 1; /* clear event flag */ + if (aptHandle->userCallBack.EvtInterruptCallBack != NULL) { + aptHandle->userCallBack.EvtInterruptCallBack(aptHandle); + } +} + +/** + * @brief APT timer interrupt service processing function. + * @param handle APT module handle. + * @retval None. + */ +void HAL_APT_TimerIrqHandler(void *handle) +{ + APT_ASSERT_PARAM(handle != NULL); + APT_Handle *aptHandle = (APT_Handle *)handle; + aptHandle->baseAddress->INT_TMR_FLAG.BIT.rg_int_clr_tmr = 1; /* clear timer interrupt flag */ + if (aptHandle->userCallBack.TmrInterruptCallBack != NULL) { + aptHandle->userCallBack.TmrInterruptCallBack(aptHandle); + } +} + +/** + * @brief Interrupt callback functions registration interface. + * @param aptHandle APT module handle. + * @param typeID ID of callback function type. + * @param pCallback Pointer for the user callback function. + * @retval None. + */ +void HAL_APT_RegisterCallBack(APT_Handle *aptHandle, APT_InterruputType typeID, APT_CallbackType pCallback) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + switch (typeID) { + case APT_TIMER_INTERRUPT: /* timer interrupt */ + aptHandle->userCallBack.TmrInterruptCallBack = pCallback; + break; + case APT_EVENT_INTERRUPT: /* event interrupt */ + aptHandle->userCallBack.EvtInterruptCallBack = pCallback; + break; + default: + break; + } +} + +/** + * @brief Attribute configuration of the reference point. + * @param aptHandle APT module handle. + * @param refDotParameters Attribute structure of a reference point. + * @retval BASE_StatusType: OK, ERROR. + */ +static BASE_StatusType APT_ConfigAction(APT_Handle *aptHandle, APT_RefDotParameters *refDotParameters) +{ + /* Action configuration of the reference point of channel B. */ + if (refDotParameters->pwmChannel == APT_PWM_CHANNEL_B) { + aptHandle->baseAddress->PG_ACT_B.reg &= (~(0b11 << refDotParameters->actionEvent)); /* Reset configuration */ + aptHandle->baseAddress->PG_ACT_B.reg |= (refDotParameters->action << refDotParameters->actionEvent); + return BASE_STATUS_OK; + } + /* Action configuration of the reference point of channel A. */ + if (refDotParameters->pwmChannel == APT_PWM_CHANNEL_A) { + aptHandle->baseAddress->PG_ACT_A.reg &= (~(0b11 << refDotParameters->actionEvent)); /* Reset configuration */ + aptHandle->baseAddress->PG_ACT_A.reg |= (refDotParameters->action << refDotParameters->actionEvent); + return BASE_STATUS_OK; + } + return BASE_STATUS_ERROR; +} + +/** + * @brief Configure the value and action of the reference point A. + * @param aptHandle APT module handle. + * @param refDotParameters Reference point A configuration property set. + * @retval BASE_StatusType: OK, ERROR. + */ +BASE_StatusType APT_ConfigRefA(APT_Handle *aptHandle, APT_RefDotParameters *refDotParameters) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(aptHandle->baseAddress != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + /* Check the attributes of the reference point A: PWM Channel. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel >= APT_PWM_CHANNEL_A, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel <= APT_PWM_CHANNEL_B, BASE_STATUS_ERROR); + /* Check the attributes of the reference point A: triggle action event. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent >= APT_PWM_ACTION_ON_TIMEBASE_ZERO, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent <= APT_PWM_ACTION_ON_C2_COUNT_DOWN, BASE_STATUS_ERROR); + /* Check the attributes of the reference point A: triggle action. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->action <= APT_PWM_ACTION_TOGGLE, BASE_STATUS_ERROR); + /* Change reference dot A value and division value. */ + aptHandle->baseAddress->TC_REFA.BIT.rg_cnt_refah = refDotParameters->refDotValue; + aptHandle->baseAddress->TC_REFA.BIT.rg_cnt_refal = refDotParameters->refDotDivValue; + /* Reference dot A triggle event and action */ + return APT_ConfigAction(aptHandle, refDotParameters); +} + +/** + * @brief Configure the value and action of the reference point B. + * @param aptHandle APT module handle. + * @param refDotParameters Reference point B configuration property set. + * @retval BASE_StatusType: OK, ERROR. + */ +BASE_StatusType APT_ConfigRefB(APT_Handle *aptHandle, APT_RefDotParameters *refDotParameters) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(aptHandle->baseAddress != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + /* Check the attributes of the reference point B: PWM Channel. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel >= APT_PWM_CHANNEL_A, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel <= APT_PWM_CHANNEL_B, BASE_STATUS_ERROR); + /* Check the attributes of the reference point B: triggle action event. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent >= APT_PWM_ACTION_ON_TIMEBASE_ZERO, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent <= APT_PWM_ACTION_ON_C2_COUNT_DOWN, BASE_STATUS_ERROR); + /* Check the attributes of the reference point B: triggle action. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->action <= APT_PWM_ACTION_TOGGLE, BASE_STATUS_ERROR); + /* Change reference dot B value and division value. */ + aptHandle->baseAddress->TC_REFB.BIT.rg_cnt_refbh = refDotParameters->refDotValue; + aptHandle->baseAddress->TC_REFB.BIT.rg_cnt_refbl = refDotParameters->refDotDivValue; + /* Reference dot B triggle event and action. */ + return APT_ConfigAction(aptHandle, refDotParameters); +} + +/** + * @brief Configure the value and action of the reference point C. + * @param aptHandle APT module handle. + * @param refDotParameters Reference point C configuration property set. + * @retval BASE_StatusType: OK, ERROR. + */ +BASE_StatusType APT_ConfigRefC(APT_Handle *aptHandle, APT_RefDotParameters *refDotParameters) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(aptHandle->baseAddress != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + /* Check the attributes of the reference point C: PWM Channel. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel >= APT_PWM_CHANNEL_A, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel <= APT_PWM_CHANNEL_B, BASE_STATUS_ERROR); + /* Check the attributes of the reference point C: triggle action event. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent >= APT_PWM_ACTION_ON_TIMEBASE_ZERO, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent <= APT_PWM_ACTION_ON_C2_COUNT_DOWN, BASE_STATUS_ERROR); + /* Check the attributes of the reference point C: triggle action. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->action <= APT_PWM_ACTION_TOGGLE, BASE_STATUS_ERROR); + /* Change reference dot C value and division value. */ + aptHandle->baseAddress->TC_REFC.BIT.rg_cnt_refch = refDotParameters->refDotValue; + aptHandle->baseAddress->TC_REFC.BIT.rg_cnt_refcl = refDotParameters->refDotDivValue; + /* Reference dot C triggle event and action. */ + return APT_ConfigAction(aptHandle, refDotParameters); +} + +/** + * @brief Configure the value and action of the reference point D. + * @param aptHandle APT module handle. + * @param refDotParameters Reference point D configuration property set. + * @retval BASE_StatusType: OK, ERROR. + */ +BASE_StatusType APT_ConfigRefD(APT_Handle *aptHandle, APT_RefDotParameters *refDotParameters) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(aptHandle->baseAddress != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + /* Check the attributes of the reference point D: PWM Channel. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel >= APT_PWM_CHANNEL_A, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel <= APT_PWM_CHANNEL_B, BASE_STATUS_ERROR); + /* Check the attributes of the reference point D: triggle action event. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent >= APT_PWM_ACTION_ON_TIMEBASE_ZERO, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent <= APT_PWM_ACTION_ON_C2_COUNT_DOWN, BASE_STATUS_ERROR); + /* Check the attributes of the reference point D: triggle action. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->action <= APT_PWM_ACTION_TOGGLE, BASE_STATUS_ERROR); + /* Change reference dot D value and division value. */ + aptHandle->baseAddress->TC_REFD.BIT.rg_cnt_refdh = refDotParameters->refDotValue; + aptHandle->baseAddress->TC_REFD.BIT.rg_cnt_refdl = refDotParameters->refDotDivValue; + /* Reference dot D triggle event and action. */ + return APT_ConfigAction(aptHandle, refDotParameters); +} + + +/** + * @brief Attribute configuration of any reference point. + * @param aptHandle APT module handle. + * @param refDotSelect Selection of reference points. + * @param refDotParameters The properties of the reference point. + * @retval BASE_StatusType: OK, ERROR. + */ +BASE_StatusType HAL_APT_ConfigRefDot(APT_Handle *aptHandle, APT_RefDotSelect refDotSelect, + APT_RefDotParameters *refDotParameters) +{ + APT_ASSERT_PARAM(aptHandle != NULL); + APT_ASSERT_PARAM(aptHandle->baseAddress != NULL); + APT_ASSERT_PARAM(IsAPTInstance(aptHandle->baseAddress)); + /* Reference point configuration, which must be point A, point B, point C, and point D. */ + APT_PARAM_CHECK_WITH_RET(refDotSelect >= APT_REFERENCE_DOTA, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotSelect <= APT_REFERENCE_DOTD, BASE_STATUS_ERROR); + /* Channels A and B are optional. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel >= APT_PWM_CHANNEL_A, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->pwmChannel <= APT_PWM_CHANNEL_B, BASE_STATUS_ERROR); + /* Trigger event type check. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent >= APT_PWM_ACTION_ON_TIMEBASE_ZERO, BASE_STATUS_ERROR); + APT_PARAM_CHECK_WITH_RET(refDotParameters->actionEvent <= APT_PWM_ACTION_ON_C2_COUNT_DOWN, BASE_STATUS_ERROR); + /* There are four types of trigger actions. */ + APT_PARAM_CHECK_WITH_RET(refDotParameters->action <= APT_PWM_ACTION_TOGGLE, BASE_STATUS_ERROR); + /* Transfer table for setting reference dot. */ + BASE_StatusType (* APT_RefDotConfigTable[RERF])(APT_Handle *, APT_RefDotParameters *) = {APT_ConfigRefA, + APT_ConfigRefB, + APT_ConfigRefC, + APT_ConfigRefD}; + return APT_RefDotConfigTable[refDotSelect](aptHandle, refDotParameters); /* Configure reference point. */ +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/common/inc/baseinc.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/common/inc/baseinc.h new file mode 100644 index 00000000..2f9c37a8 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/common/inc/baseinc.h @@ -0,0 +1,39 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file baseinc.h + * @author MCU Driver Team + * @brief BASE module driver + * @details Contains BASE-related header files. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_BASEINC_H +#define McuMagicTag_BASEINC_H + +/* Includes ------------------------------------------------------------------ */ +#include "chipinc.h" +#include "typedefs.h" +#include "assert.h" +#include "clock.h" +#include "lock.h" +#include "generalfunc.h" +#include "base_math.h" +#include "reset.h" +#include "interrupt.h" + +#endif /* McuMagicTag_BASEINC_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/assert.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/assert.h new file mode 100644 index 00000000..4d17a1c8 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/assert.h @@ -0,0 +1,96 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file assert.h + * @author MCU Driver Team + * @brief BASE module driver + * @details This file provides functions declaration of the assert, + * + BASE_FUNC_PARAMCHECK_NO_RET macro function definition. + * + BASE_FUNC_PARAMCHECK_WITH_RET macro function definition. + * + BASE_FUNC_ASSERT_PARAM macro function definition. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_ASSERT_H +#define McuMagicTag_ASSERT_H + +/* Includes ------------------------------------------------------------------ */ +#include "chipinc.h" +#include "typedefs.h" +/** + * @defgroup BASE BASE + * @brief BASE module. + * @{ + */ + +void AssertErrorLog(char *file, unsigned int line); + +/** + * @defgroup ASSERT Assert Definition + * @brief Definition of different assert. + * @{ + */ + +/** + * @defgroup ASSERT_Macro ASSERT Macro Function Definition + * @{ + */ +/* Macro definitions --------------------------------------------------------- */ +#if (BASE_DEFINE_USE_ASSERT == BASE_CFG_ENABLE) +#define BASE_FUNC_PARAMCHECK_NO_RET(param) \ + do { \ + if (!(param)) { \ + AssertErrorLog(__FILE__, __LINE__); \ + return; \ + } \ + } while (0) + +#define BASE_FUNC_PARAMCHECK_WITH_RET(param, ret) \ + do { \ + if (!(param)) { \ + AssertErrorLog(__FILE__, __LINE__); \ + return ret; \ + } \ + } while (0) + +#define BASE_FUNC_ASSERT_PARAM(param) \ + do { \ + if (!(param)) { \ + AssertErrorLog(__FILE__, __LINE__); \ + while (1) { \ + }; \ + } \ + } while (0) + +#else +#define BASE_FUNC_ASSERT_PARAM(param) ((void)0U) +#define BASE_FUNC_PARAMCHECK_NO_RET(param) ((void)0U) +#define BASE_FUNC_PARAMCHECK_WITH_RET(param, ret) ((void)0U) + +#endif /* BASE_DEFINE_USE_ASSERT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_ASSERT_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/base_math.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/base_math.h new file mode 100644 index 00000000..defe9cb0 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/base_math.h @@ -0,0 +1,116 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file base_math.h + * @author MCU Driver Team + * @brief BASE module driver + * @details This file provides functions declaration of math + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_BASE_MATH_H +#define McuMagicTag_BASE_MATH_H + +/* Includes ------------------------------------------------------------------ */ +#include "chipinc.h" +#include "typedefs.h" +#include "assert.h" + +/** + * @defgroup BASE BASE + * @brief BASE module. + * @{ + */ + +/** + * @defgroup MATH Math Definition + * @brief Definition of MATH Definition. + * @{ + */ + +/** + * @defgroup MATH_STRUCTURE_DEFINITION math structure Definition + * @brief Definition of math structure Definition. + * @{ + */ +/* Typedef definitions ------------------------------------------------------- */ +/** + * @brief sin, cos status definition. + */ +typedef struct { + int sin : 16; + int cos : 16; +} BASE_MathTypeSinCos; + +/** + * @brief q-axis d-axis status definition. + */ +typedef struct { + int q : 16; + int d : 16; +} BASE_MathTypeQD; + +/** + * @brief current component a,b status definition. + */ +typedef struct { + int a : 16; + int b : 16; +} BASE_MathTypeAB; + +/** + * @brief alpha-axis beta-axis status definition. + */ +typedef struct { + int alpha : 16; + int beta : 16; +} BASE_MathTypeAlphaBeta; +/** + * @} + */ +/** + * @defgroup MATH_API_DEFINITION Math API + * @brief Definition of math API Definition. + * @{ + */ +/* Macro definitions --------------------------------------------------------- */ +#define BASE_MATH_ABS(x) ((x) < 0 ? -(x) : (x)) + +/* Radian to angle. */ +#define BASE_MATH_RADIAN_TO_ANGLE(radian) ((radian) * 57.295779524) + +/* Exported global functions ------------------------------------------------- */ +BASE_MathTypeSinCos BASE_MATH_GetSinCos(short angle); +float BASE_MATH_GetSin(float angle); +float BASE_MATH_GetCos(float angle); +float BASE_MATH_Sqrt(const float x); +float BASE_MATH_Pow(float x, int n); +BASE_MathTypeAlphaBeta BASE_MATH_Clarke(BASE_MathTypeAB input); +BASE_MathTypeQD BASE_MATH_Park(BASE_MathTypeAlphaBeta input, short theta); +BASE_MathTypeAlphaBeta BASE_MATH_RevPark(BASE_MathTypeQD input, short theta); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_BASE_MATH_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/clock.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/clock.h new file mode 100644 index 00000000..0f5df18e --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/clock.h @@ -0,0 +1,105 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file clock.h + * @author MCU Driver Team + * @brief BASE module driver + * @brief Include the header file of the clock.c file. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_CLOCK_H +#define McuMagicTag_CLOCK_H + +/* Includes ------------------------------------------------------------------ */ +#include "chipinc.h" +#include "typedefs.h" + +/** + * @defgroup BASE BASE + * @brief BASE module. + * @{ + */ + +/** + * @defgroup CLOCK Clock Definition + * @brief Definition of Clock Definition. + * @{ + */ + +/** + * @defgroup CLOCK_ENUM_DEFINITION Delay Enum Definition + * @brief Definition of BASE_DelayUnit enum + * @{ + */ + +/* Typedef definitions ------------------------------------------------------- */ +/** + * @brief Multiples of the parameters of the delay function based on microseconds in different time units. + * @details BASE_DelayUnit: + * + BASE_DEFINE_DELAY_SECS -- Needed delay amount is in seconds + * + BASE_DEFINE_DELAY_MILLISECS -- Needed delay amount is in milliseconds + * + BASE_DEFINE_DELAY_MICROSECS -- Needed delay amount is in microseconds + */ +typedef enum { + BASE_DEFINE_DELAY_SECS = 1, + BASE_DEFINE_DELAY_MILLISECS = 1000, + BASE_DEFINE_DELAY_MICROSECS = 1000000 +} BASE_DelayUnit; +/** + * @} + */ + +/** + * @defgroup CLOCK_MACRO_DEFINITION Delay Macro Function Definition + * @brief Definition of BASE_DelayUnit macro. + * @{ + */ +/* Macro definitions --------------------------------------------------------- */ +#define BASE_DEFINE_DELAY_MS_IN_SEC 1000 +#define BASE_DEFINE_DELAY_US_IN_MS 1000 + +#define BASE_FUNC_DELAY_S(n) BASE_FUNC_Delay(n, BASE_DEFINE_DELAY_SECS) +#define BASE_FUNC_DELAY_MS(n) BASE_FUNC_Delay(n, BASE_DEFINE_DELAY_MILLISECS) +#define BASE_FUNC_DELAY_US(n) BASE_FUNC_Delay(n, BASE_DEFINE_DELAY_MICROSECS) +/** + * @} + */ + +/** + * @defgroup CLOCK_API_DEFINITION Clock Delay API + * @brief Definition of clcok API. + * @{ + */ +/* Exported global functions ------------------------------------------------------------------ */ +unsigned int BASE_FUNC_GetCpuFreqHz(void); +void BASE_FUNC_Delay(unsigned int delay, BASE_DelayUnit units); +void BASE_FUNC_DelayUs(unsigned int us); +void BASE_FUNC_DelayMs(unsigned int ms); +void BASE_FUNC_DelaySeconds(unsigned int seconds); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_CLOCK_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/generalfunc.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/generalfunc.h new file mode 100644 index 00000000..06ef81bb --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/generalfunc.h @@ -0,0 +1,109 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file generalfunc.h + * @author MCU Driver Team + * @brief BASE module driver + * @details This file provides functions declaration of the basic function + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_GENERAL_FUNC_H +#define McuMagicTag_GENERAL_FUNC_H + +/* Includes ------------------------------------------------------------------ */ +#include "chipinc.h" +#include "typedefs.h" +#include "assert.h" +#include "clock.h" + +/** + * @defgroup BASE BASE + * @brief BASE module. + * @{ + */ + +/** + * @defgroup GeneralFunc GeneralFunc Definition + * @brief Definition of GeneralFunc function. + * @{ + */ + +/* Typedef definitions ------------------------------------------------------- */ +/** + * @defgroup BASIC_Structure_Definition BASE_AverageHandle Definition + * @{ + */ + +/** + * @brief Structure for configuring and controlling averaging + */ +typedef struct { + unsigned int cnt; /**< Used to record the divisor of the average */ + float *buf; /**< Buffer pointer */ + unsigned int size; /**< Buffer size */ + unsigned int at; /**< Index value of the currently inserted value */ + unsigned int calNum; /**< Total number to be averaged */ + float total; /**< Current Cumulative Sum */ +} BASE_AverageHandle; +/** + * @} + */ + +/** + * @defgroup BASIC_Structure_Definition BASE_FSM_Handle Definition + * @{ + */ +typedef BASE_FSM_Status (*FunType)(void); +/** + * @brief General state machine handle + */ +typedef struct { + FunType funList[BASE_DEFINE_FSM_END + 1]; /**< function list */ + BASE_FSM_Status nextFun; /**< next function status */ +} BASE_FSM_Handle; +/** + * @} + */ + +/** + * @defgroup GENERAL_API_Definition GENERAL_API + * @{ + */ +/* Exported global functions ------------------------------------------------- */ +unsigned int BASE_FUNC_GetTick(void); +unsigned int BASE_FUNC_FindArrayValue(const unsigned short *nums, unsigned int leng, unsigned int value); +unsigned char BASE_FUNC_CalcSumByte(const unsigned char *pt, unsigned int len); +unsigned short BASE_FUNC_CalcSumShort(unsigned char const * pt, unsigned int len); +BASE_StatusType BASE_FUNC_AverageInit(unsigned int index, float *buf, unsigned int size, unsigned int calNum); +float BASE_FUNC_GetSlipAverageVal(unsigned int index, float val); +void BASE_FUNC_AverageDeInit(unsigned int index); +void BASE_FSM_FunRegister(BASE_FSM_Status index, FunType funAddress); +void BASE_FSM_Run(unsigned int delayTime, BASE_DelayUnit delayUnit); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_GENERAL_FUNC_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/interrupt.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/interrupt.h new file mode 100644 index 00000000..1fa09615 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/interrupt.h @@ -0,0 +1,318 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file interrupt.h + * @author MCU Driver Team + * @brief BASE module driver + * @brief Header file containing functions prototypes of Interrupt HAL library. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_INTERRUPT_H +#define McuMagicTag_INTERRUPT_H + +/* Includes ------------------------------------------------------------------*/ +#include "feature.h" +#include "interrupt_ip.h" + +/* Macro definitions ---------------------------------------------------------*/ +#define INTERRUPT_USE_ASSERT +#ifdef INTERRUPT_USE_ASSERT +#define INTERRUPT_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define INTERRUPT_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define INTERRUPT_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define INTERRUPT_ASSERT_PARAM(para) ((void)0U) +#define INTERRUPT_PARAM_CHECK_NO_RET ((void)0U) +#define INTERRUPT_PARAM_CHECK_WITH_RET ((void)0U) +#endif +/** + * @defgroup BASE BASE + * @brief BASE module. + * @{ + */ + +/** + * @defgroup INTERRUPT Interrupt Definition + * @brief Definition of Interrupt Definition. + * @{ + */ + +/** + * @defgroup INTERRUPT_MACRO Macro Definition + * @brief Definition of Interrupt Definition. + * @{ + */ + +/** + * @brief IRQ module error code + */ +#define IRQ_ERRNO_PROC_FUNC_NULL 1 /**< Non-interrupted callback function */ +#define IRQ_ERRNO_NUM_INVALID 2 /**< Interrupt Number invalid */ +#define IRQ_ERRNO_ALREADY_CREATED 3 /**< Interrupt function is created */ +#define IRQ_ERRNO_NOT_CREATED 4 /**< Interrupt function not create */ +#define IRQ_ERRNO_PRIORITY_INVALID 5 /**< Invalid priority */ + +#define RISCV_U_MODE 0x8 /**< The Value in mcause for umode */ +#define RISCV_M_MODE 0xB /**< The Value in mcause for mmode */ +/** + * @} + */ + +/** + * @defgroup ASM Interrupt ASM Function Definition + * @brief Definition of Interrupt ASM Function Definition. + * @{ + */ + +/** + * @brief Read standard csr registers + */ +#define READ_CSR(csrReg) ({ \ + unsigned int tmp_; \ + asm volatile ("csrr %0, " #csrReg : "=r"(tmp_)); \ + tmp_; \ +}) + + +/** + * @brief Write standard csr registers + */ +#define WRITE_CSR(csrReg, csrVal) do { \ + if (__builtin_constant_p(csrVal) && ((unsigned int)(csrVal) < 32)) { \ + asm volatile ("csrw " #csrReg ", %0" :: "i"(csrVal)); \ + } else { \ + asm volatile ("csrw " #csrReg ", %0" :: "r"(csrVal)); \ + } \ +} while (0) + +/** + * @brief Set standard csr registers + */ +#define SET_CSR(csrReg, csrBit) do { \ + unsigned int tmp_; \ + if (__builtin_constant_p(csrBit) && ((unsigned int)(csrBit) < 32)) { \ + asm volatile ("csrrs %0, " #csrReg ", %1" : "=r"(tmp_) : "i"(csrBit)); \ + } else { \ + asm volatile ("csrrs %0, " #csrReg ", %1" : "=r"(tmp_): "r"(csrBit)); \ + } \ + (void)tmp_; \ +} while (0) + +/** + * @brief Clear standard csr registers + */ +#define CLEAR_CSR(csrReg, csrBit) do { \ + unsigned int tmp_; \ + if (__builtin_constant_p(csrBit) && ((unsigned int)(csrBit) < 32)) { \ + asm volatile ("csrrc %0, " #csrReg ", %1" : "=r"(tmp_) : "i"(csrBit)); \ + } else { \ + asm volatile ("csrrc %0, " #csrReg ", %1" : "=r"(tmp_) : "r"(csrBit)); \ + } \ + (void)tmp_; \ +} while (0) + +/** + * @brief Read the custom defined registers of the chip + */ +#define READ_CUSTOM_CSR(csrReg) ({ \ + unsigned int tmp_; \ + asm volatile ("csrr %0, %1" : "=r"(tmp_) : "i"(csrReg)); \ + tmp_; \ +}) + +/** + * @brief Write the custom defined registers of the chip + */ +#define WRITE_CUSTOM_CSR_VAL(csrRegAddr, csrVal) do { \ + if (__builtin_constant_p(csrVal)) { \ + asm volatile("li t0," "%0" : : "i"(csrVal)); \ + } else { \ + asm volatile("mv t0," "%0" : : "r"(csrVal)); \ + } \ + asm volatile("csrw %0, t0" :: "i"(csrRegAddr)); \ +} while (0) + +/** + * @brief Set the custom defined registers of the chip + */ +#define SET_CUSTOM_CSR(csrRegAddr, csrBit) do { \ + if (__builtin_constant_p(csrBit) && ((unsigned int)(csrBit) < 32)) { \ + asm volatile("li t0," "%0" : : "i"(csrBit)); \ + } else { \ + asm volatile("mv t0," "%0" : : "r"(csrBit)); \ + } \ + asm volatile("csrs %0, t0" :: "i"(csrRegAddr)); \ +} while (0) + +/** + * @brief Clear the custom defined registers of the chip + */ +#define CLEAR_CUSTOM_CSR(csrRegAddr, csrBit) do { \ + if (__builtin_constant_p(csrBit) && ((unsigned int)(csrBit) < 32)) { \ + asm volatile("li t0," "%0" : : "i"(csrBit)); \ + } else { \ + asm volatile("mv t0," "%0" : : "r"(csrBit)); \ + } \ + asm volatile("csrc %0, t0" :: "i"(csrRegAddr)); \ +} while (0) + +/* Configure the locipri register, that is, configure the interrupt priority */ +/** + * @brief Get the local interrupt register number. + */ +#define GET_LOCAL_INTER_CONFIGREG_NUM(interIndex) ((unsigned int)(interIndex) >> 3) + +/** + * @brief Set local interrupt registers priority. + */ +#define SET_LOCAL_INTER_NUM_PRI(configNum, priNum, pri) do { \ + unsigned int interPriVal = READ_CUSTOM_CSR(LOCIPRI(configNum)); \ + /* clear the irqNum-th local interrupt priority */ \ + interPriVal &= (~((0xfU << (((unsigned int)(priNum) & 0x7U) << 2)) & UINT32_CUT_MASK)); \ + /* set the irqNum-th local interrupt priority */ \ + interPriVal |= ((unsigned int)(pri) << (((unsigned int)(priNum) & 0x7U) << 2)); \ + WRITE_CUSTOM_CSR_VAL(LOCIPRI(configNum), interPriVal); \ +} while (0) + +/** + * @brief Get local interrupt registers priority. + */ +#define GET_LOCAL_INTER_NUM_PRI(configNum, priNum, pri) do { \ + (pri) = READ_CUSTOM_CSR(LOCIPRI(configNum)); \ + /* Get the irqNum-th local interrupt priority */ \ + (pri) >>= (((unsigned int)(priNum) & 0x7U) << 2); \ + (pri) &= 0x7U; \ +} while (0) + +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) +/** + * @brief Riscv mode switch in user mode + */ +#define RISCV_PRIV_MODE_SWITCH(priv) do { \ + if ((priv) == RISCV_U_MODE) { \ + asm volatile ("ecall"); \ + } \ +} while (0) +#else +#define RISCV_PRIV_MODE_SWITCH(priv) (void)(0) +#endif +/** + * @} + */ + +/** + * @brief Clear external interrupt + * @param irqNum external interrupt number + * @retval BASE_STATUS_OK or IRQ_ERRNO_NUM_INVALID or IRQ_ERRNO_NOT_CREATED + */ +static inline void IRQ_ClearN(unsigned int irqNum) +{ + asm volatile("fence"); + WRITE_CUSTOM_CSR_VAL(LOCIPCLR, irqNum); +} +/** + * @defgroup INTERRUPT_STRUCTURE_DEFINITION Interrupt Structure Definition + * @brief Definition of interrupt STRUCTURE. + * @{ + */ +typedef void (* IRQ_PROC_FUNC)(void *arg); + +/** + * @brief Interrupt Handle Structure + */ +typedef struct { + IRQ_PROC_FUNC pfnHandler; + void *param; +} IRQ_ARG_FUNC; + +/** + * @brief System error context Structure + */ +typedef struct { + unsigned int ra; + unsigned int t0; + unsigned int t1; + unsigned int t2; + unsigned int a0; + unsigned int a1; + unsigned int a2; + unsigned int a3; + unsigned int a4; + unsigned int a5; + unsigned int a6; + unsigned int a7; + unsigned int t3; + unsigned int t4; + unsigned int t5; + unsigned int t6; + unsigned int s0; + unsigned int s1; + unsigned int s2; + unsigned int s3; + unsigned int s4; + unsigned int s5; + unsigned int s6; + unsigned int s7; + unsigned int s8; + unsigned int s9; + unsigned int s10; + unsigned int s11; + unsigned int sp; + unsigned int gp; + unsigned int tp; + unsigned int mepc; + unsigned int mstatus; + unsigned int mtval; + unsigned int mcause; + unsigned int ccause; +} SyserrContext; +/** + * @} + */ + +/** + * @defgroup INTERRUPT_API_DEFINITION Interrupt API + * @brief Definition of interrupt API. + * @{ + */ +unsigned int IRQ_SetPriority(unsigned int irqNum, unsigned int priority); +unsigned int IRQ_GetPriority(unsigned int irqNum, unsigned int *priority); +void IRQ_Enable(void); +void IRQ_Disable(void); +unsigned int IRQ_EnableN(unsigned int irqNum); +unsigned int IRQ_DisableN(unsigned int irqNum); +void IRQ_Init(void); +unsigned int IRQ_Register(unsigned int irqNum, IRQ_PROC_FUNC func, void *arg); +unsigned int IRQ_Unregister(unsigned int irqNum); +unsigned int IRQ_ClearAll(void); +void SysErrNmiEntry(const SyserrContext *context); +void SysErrExcEntry(const SyserrContext *context); +void InterruptEntry(unsigned int irqNum); +void SysErrPrint(const SyserrContext *context); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_INTERRUPT_H */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/lock.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/lock.h new file mode 100644 index 00000000..451ca83f --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/lock.h @@ -0,0 +1,83 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file lock.h + * @author MCU Driver Team + * @brief BASE module driver + * @details This file provides functions declaration of lock + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_LOCK_H +#define McuMagicTag_LOCK_H + +/* Includes ------------------------------------------------------------------ */ +#include "chipinc.h" +#include "typedefs.h" +#include "assert.h" + +/** + * @defgroup BASE BASE + * @brief BASE module. + * @{ + */ + +/** + * @defgroup LOCK Lock Definition + * @brief Definition of LOCK Definition. + * @{ + */ + +/** + * @defgroup LOCK_ENUM_DEFINITION BASE_LockStatus Definition + * @brief Definition of LOCK Definition. + * @{ + */ +/* Typedef definitions ------------------------------------------------------- */ +/** + * @brief Lock status definition + */ +typedef enum { + BASE_STATUS_UNLOCKED = 0, + BASE_STATUS_LOCKED = 1 +} BASE_LockStatus; +/** + * @} + */ + +/** + * @defgroup LOCK_API_DEFINITION Lock API + * @brief Definition of lock API Definition. + * @{ + */ +/* Exported global functions ------------------------------------------------- */ +bool BASE_FUNC_SoftwareLock(unsigned int * const addr); +void BASE_FUNC_SoftwareUnLock(unsigned int * const addr); +bool BASE_FUNC_HardwareLock(CHIP_LockType const hwIndex); +void BASE_FUNC_HardwareUnLock(CHIP_LockType const hwIndex); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_LOCK_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/reset.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/reset.h new file mode 100644 index 00000000..ffc14408 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/reset.h @@ -0,0 +1,60 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file reset.h + * @author MCU Driver Team + * @brief BASE module driver + * @details This file provides functions declaration of reset + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_RESET_H +#define McuMagicTag_RESET_H + +/* Includes ------------------------------------------------------------------ */ +#include "chipinc.h" +/** + * @defgroup BASE BASE + * @brief BASE module. + * @{ + */ + +/** + * @defgroup RESET Reset Definition + * @brief Definition of RESET Definition. + * @{ + */ + +/** + * @defgroup RESET_API_DEFINITION RESET API Definition + * @brief Definition of RESET API Definition. + * @{ + */ +/* Exported global functions ------------------------------------------------- */ +void BASE_FUNC_SoftReset(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_RESET_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/typedefs.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/typedefs.h new file mode 100644 index 00000000..2af04be5 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/inc/typedefs.h @@ -0,0 +1,137 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file typedefs.h + * @author MCU Driver Team + * @brief BASE module driver + * @brief This file contains generic definitions + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_TYPEDEFS_H +#define McuMagicTag_TYPEDEFS_H +/** + * @defgroup BASE BASE + * @brief BASE module. + * @{ + */ + +/** + * @defgroup TYPRDEF Typedef Definition + * @brief Definition of RESET Definition. + * @{ + */ + +/** + * @defgroup TYPEDEF_MACRO_DEFINITION TYPEDEF MACRO Definition + * @brief Definition of TYPEDEF MACRO Definition. + * @{ + */ +/* Macro definitions --------------------------------------------------------- */ +#ifndef bool +#define bool _Bool +#endif /* bool */ + +#ifndef false +#define false 0 +#endif /* false */ + +#ifndef true +#define true 1 +#endif /* true */ + +#ifndef NULL +#define NULL ((void *)0) +#endif /* NULL */ + +#ifndef FLT_EPSILON +#define FLT_EPSILON 0.000001 +#endif /* float min error definition */ + +#ifndef INT16_MAX +#define INT16_MAX 0x7FFF +#endif /* INT16_MAX */ + +#ifndef INT16_MIN +#define INT16_MIN (-0x8000) +#endif /* INT16_MIN */ + +#ifndef INT_MAX +#define INT_MAX 0x7FFFFFFF +#endif /* INT_MAX */ + +#ifndef UINT_MAX +#define UINT_MAX 0xFFFFFFFFU +#endif /* UINT_MAX */ + +#define BASE_FUNC_UNUSED(X) (void)(X) + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +#define BASE_CFG_UNSET 0x00 +#define BASE_CFG_SET 0x01 + +#define BASE_CFG_DISABLE 0x00 +#define BASE_CFG_ENABLE 0x01 + +#define RAM_CODE __attribute__((section(".text.sram"))) +#define RESERVED_DATA __attribute__((section(".reserved.data"))) + +typedef int intptr_t; +typedef unsigned int uintptr_t; +/** + * @} + */ + +/** + * @defgroup TYPEDEF_ENUM_DEFINITION TYPEDEF ENUM Definition + * @brief Definition of TYPEDEF ENUM Definition. + * @{ + */ +/** + * @brief BASE Status structures definition + */ +typedef enum { + BASE_STATUS_OK = 0x00000000U, + BASE_STATUS_ERROR = 0x00000001U, + BASE_STATUS_BUSY = 0x00000002U, + BASE_STATUS_TIMEOUT = 0x00000003U, + BASE_STATUS_NOT_SUPPORT = 0x00000004U, +} BASE_StatusType; + +/** + * @brief Indicates the status of the general state machine. The user should add the service status to this enum. + */ +typedef enum { + BASE_FSM_START, + BASE_DEFINE_FSM_END +} BASE_FSM_Status; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_TYPEDEFS_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/assert.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/assert.c new file mode 100644 index 00000000..b99ca6ca --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/assert.c @@ -0,0 +1,38 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file assert.c + * @author MCU Driver Team + * @brief Provides weak Error logger function. + */ + +/* Includes ------------------------------------------------------------------ */ +#include "assert.h" +#include "typedefs.h" + +/** + * @brief Error logger function. + * @param file Pointer to the name of the file where the error occurs. + * @param line Number of the line where the error occurs. + * @retval None. + */ +__weak void AssertErrorLog(char *file, unsigned int line) +{ + /* Use only if the user apllication is not defined. */ + BASE_FUNC_UNUSED(file); + BASE_FUNC_UNUSED(line); +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/base_math.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/base_math.c new file mode 100644 index 00000000..05a2063e --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/base_math.c @@ -0,0 +1,392 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file base_math.c + * @author MCU Driver Team + * @brief Provides functions about math. + */ + +/* Includes ------------------------------------------------------------------ */ +#include "base_math.h" + +/* Private macro ------------------------------------------------------------- */ +#if (BASE_MATH_SINCOS_MIDDLE_TABLE == BASE_CFG_ENABLE) +#define TRIGONOMETRIC_MAPPING_TABLE { \ + 0X0000, 0X012D, 0X01F6, 0X02BF, 0X0388, 0X0451, 0X051A, 0X05E3, \ + 0X06AC, 0X0775, 0X083D, 0X0906, 0X09CE, 0X0A97, 0X0B5F, 0X0C27, \ + 0X0CEF, 0X0DB7, 0X0E7F, 0X0F47, 0X100E, 0X10D6, 0X119D, 0X1264, \ + 0X132B, 0X13F2, 0X14B8, 0X157F, 0X1645, 0X170A, 0X17D0, 0X1896, \ + 0X195B, 0X1A20, 0X1AE4, 0X1BA9, 0X1C6D, 0X1D31, 0X1DF5, 0X1EB8, \ + 0X1F7B, 0X203E, 0X2100, 0X21C2, 0X2284, 0X2345, 0X2407, 0X24C7, \ + 0X2588, 0X2648, 0X2707, 0X27C7, 0X2886, 0X2944, 0X2A02, 0X2AC0, \ + 0X2B7D, 0X2C3A, 0X2CF7, 0X2DB3, 0X2E6E, 0X2F29, 0X2FE4, 0X309E, \ + 0X3158, 0X3211, 0X32CA, 0X3382, 0X343A, 0X34F2, 0X35A8, 0X365F, \ + 0X3714, 0X37CA, 0X387E, 0X3932, 0X39E6, 0X3A99, 0X3B4C, 0X3BFD, \ + 0X3CAF, 0X3D60, 0X3E10, 0X3EBF, 0X3F6E, 0X401D, 0X40CA, 0X4177, \ + 0X4224, 0X42D0, 0X437B, 0X4425, 0X44CF, 0X4578, 0X4621, 0X46C9, \ + 0X4770, 0X4816, 0X48BC, 0X4961, 0X4A06, 0X4AA9, 0X4B4C, 0X4BEF, \ + 0X4C90, 0X4D31, 0X4DD1, 0X4E70, 0X4F0F, 0X4FAC, 0X5049, 0X50E5, \ + 0X5181, 0X521C, 0X52B5, 0X534E, 0X53E7, 0X547E, 0X5515, 0X55AB, \ + 0X5640, 0X56D4, 0X5767, 0X57F9, 0X588B, 0X591C, 0X59AC, 0X5A3B, \ + 0X5AC9, 0X5B56, 0X5BE3, 0X5C6E, 0X5CF9, 0X5D83, 0X5E0B, 0X5E93, \ + 0X5F1A, 0X5FA0, 0X6026, 0X60AA, 0X612D, 0X61B0, 0X6231, 0X62B2, \ + 0X6331, 0X63B0, 0X642D, 0X64AA, 0X6526, 0X65A0, 0X661A, 0X6693, \ + 0X670B, 0X6782, 0X67F7, 0X686C, 0X68E0, 0X6953, 0X69C4, 0X6A35, \ + 0X6AA5, 0X6B13, 0X6B81, 0X6BEE, 0X6C59, 0X6CC4, 0X6D2D, 0X6D96, \ + 0X6DFD, 0X6E63, 0X6EC9, 0X6F2D, 0X6F90, 0X6FF2, 0X7053, 0X70B3, \ + 0X7112, 0X716F, 0X71CC, 0X7227, 0X7282, 0X72DB, 0X7333, 0X738A, \ + 0X73E0, 0X7435, 0X7489, 0X74DB, 0X752D, 0X757D, 0X75CC, 0X761B, \ + 0X7668, 0X76B3, 0X76FE, 0X7747, 0X7790, 0X77D7, 0X781D, 0X7862, \ + 0X78A6, 0X78E8, 0X792A, 0X796A, 0X79A9, 0X79E7, 0X7A24, 0X7A5F, \ + 0X7A9A, 0X7AD3, 0X7B0B, 0X7B42, 0X7B77, 0X7BAC, 0X7BDF, 0X7C11, \ + 0X7C42, 0X7C71, 0X7CA0, 0X7CCD, 0X7CF9, 0X7D24, 0X7D4E, 0X7D76, \ + 0X7D9D, 0X7DC3, 0X7DE8, 0X7E0C, 0X7E2E, 0X7E4F, 0X7E6F, 0X7E8E, \ + 0X7EAB, 0X7EC8, 0X7EE3, 0X7EFD, 0X7F15, 0X7F2D, 0X7F43, 0X7F58, \ + 0X7F6B, 0X7F7E, 0X7F8F, 0X7F9F, 0X7FAE, 0X7FBC, 0X7FC8, 0X7FD3, \ + 0X7FDD, 0X7FE5, 0X7FED, 0X7FF3, 0X7FF8, 0X7FFC, 0X7FFE, 0X7FFF } +#elif (BASE_MATH_SINCOS_MIDDLE_TABLE == BASE_CFG_DISABLE) +#define TRIGONOMETRIC_MAPPING_TABLE { \ + 0x0000, 0x00C9, 0x0192, 0x025B, 0x0324, 0x03ED, 0x04B6, 0x057F, \ + 0x0647, 0x0710, 0x07D9, 0x08A2, 0x096A, 0x0A33, 0x0AFB, 0x0BC3, \ + 0x0C8B, 0x0D53, 0x0E1B, 0x0EE3, 0x0FAB, 0x1072, 0x1139, 0x1201, \ + 0x12C8, 0x138E, 0x1455, 0x151B, 0x15E2, 0x16A8, 0x176D, 0x1833, \ + 0x18F8, 0x19BD, 0x1A82, 0x1B47, 0x1C0B, 0x1CCF, 0x1D93, 0x1E56, \ + 0x1F19, 0x1FDC, 0x209F, 0x2161, 0x2223, 0x22E5, 0x23A6, 0x2467, \ + 0x2528, 0x25E8, 0x26A8, 0x2767, 0x2826, 0x28E5, 0x29A3, 0x2A61, \ + 0x2B1F, 0x2BDC, 0x2C98, 0x2D55, 0x2E11, 0x2ECC, 0x2F87, 0x3041, \ + 0x30FB, 0x31B5, 0x326E, 0x3326, 0x33DE, 0x3496, 0x354D, 0x3604, \ + 0x36BA, 0x376F, 0x3824, 0x38D8, 0x398C, 0x3A40, 0x3AF2, 0x3BA5, \ + 0x3C56, 0x3D07, 0x3DB8, 0x3E68, 0x3F17, 0x3FC5, 0x4073, 0x4121, \ + 0x41CE, 0x427A, 0x4325, 0x43D0, 0x447A, 0x4524, 0x45CD, 0x4675, \ + 0x471C, 0x47C3, 0x4869, 0x490F, 0x49B4, 0x4A58, 0x4AFB, 0x4B9E, \ + 0x4C3F, 0x4CE1, 0x4D81, 0x4E21, 0x4EBF, 0x4F5E, 0x4FFB, 0x5097, \ + 0x5133, 0x51CE, 0x5269, 0x5302, 0x539B, 0x5433, 0x54CA, 0x5560, \ + 0x55F5, 0x568A, 0x571D, 0x57B0, 0x5842, 0x58D4, 0x5964, 0x59F3, \ + 0x5A82, 0x5B10, 0x5B9D, 0x5C29, 0x5CB4, 0x5D3E, 0x5DC7, 0x5E50, \ + 0x5ED7, 0x5F5E, 0x5FE3, 0x6068, 0x60EC, 0x616F, 0x61F1, 0x6271, \ + 0x62F2, 0x6371, 0x63EF, 0x646C, 0x64E8, 0x6563, 0x65DD, 0x6657, \ + 0x66CF, 0x6746, 0x67BD, 0x6832, 0x68A6, 0x6919, 0x698C, 0x69FD, \ + 0x6A6D, 0x6ADC, 0x6B4A, 0x6BB8, 0x6C24, 0x6C8F, 0x6CF9, 0x6D62, \ + 0x6DCA, 0x6E30, 0x6E96, 0x6EFB, 0x6F5F, 0x6FC1, 0x7023, 0x7083, \ + 0x70E2, 0x7141, 0x719E, 0x71FA, 0x7255, 0x72AF, 0x7307, 0x735F, \ + 0x73B5, 0x740B, 0x745F, 0x74B2, 0x7504, 0x7555, 0x75A5, 0x75F4, \ + 0x7641, 0x768E, 0x76D9, 0x7723, 0x776C, 0x77B4, 0x77FA, 0x7840, \ + 0x7884, 0x78C7, 0x7909, 0x794A, 0x798A, 0x79C8, 0x7A05, 0x7A42, \ + 0x7A7D, 0x7AB6, 0x7AEF, 0x7B26, 0x7B5D, 0x7B92, 0x7BC5, 0x7BF8, \ + 0x7C29, 0x7C5A, 0x7C89, 0x7CB7, 0x7CE3, 0x7D0F, 0x7D39, 0x7D62, \ + 0x7D8A, 0x7DB0, 0x7DD6, 0x7DFA, 0x7E1D, 0x7E3F, 0x7E5F, 0x7E7F, \ + 0x7E9D, 0x7EBA, 0x7ED5, 0x7EF0, 0x7F09, 0x7F21, 0x7F38, 0x7F4D, \ + 0x7F62, 0x7F75, 0x7F87, 0x7F97, 0x7FA7, 0x7FB5, 0x7FC2, 0x7FCE, \ + 0x7FD8, 0x7FE1, 0x7FE9, 0x7FF0, 0x7FF6, 0x7FFA, 0x7FFD, 0x7FFF } +#endif + +#define BASE_MATH_SIN_COS_MASK 0x0300u /**< All mask values of sincos */ +#define BASE_MATH_ANGLED0_90 0x0200u /**< Mask value of sincos ranging from 0 to 90 degrees */ +#define BASE_MATH_ANGLED90_180 0x0300u /**< Mask value of sincos ranging from 90 to 180 degrees */ +#define BASE_MATH_ANGLED180_270 0x0000u /**< Mask value of sincos ranging from 180 to 270 degrees */ +#define BASE_MATH_ANGLED270_360 0x0100u /**< Mask value of sincos ranging from 270 to 360 degrees */ +#define BASE_MATH_PAI 3.141592653 +#define BASE_MATH_FACTORIAL3_RECIPROCAL 0.166666667 /**< 1/6. */ +#define BASE_MATH_FACTORIAL5_RECIPROCAL 0.008333333 /**< 1/120. */ +#define BASE_MATH_FACTORIAL7_RECIPROCAL 0.000198413 /**< 1/5040. */ +#define BASE_MATH_ANGLE90 90 +#define BASE_MATH_ANGLE180 180 +#define BASE_MATH_ANGLE180_RECIPROCAL 0.005555556 /**< 1/180. */ +#define BASE_MATH_ANGLE270 270 +#define BASE_MATH_ANGLE360 360 + +#define BASE_DEFINE_MAPPING_TABLE_SIZE 255 +/** Value to be added to convert a signed 16-bit value to an unsigned 16-bit value. */ +#define BASE_DEFINE_INT16_ADDITIONS_VAL 32768 + +#define BASE_DEFINE_DIV_SQRT3 (int)0x49E6 /**< 1/sqrt(3) = 0.5773315 in q15 format. */ + +/* Private variables --------------------------------------------------------- */ +const short g_triFunMappingTable[] = TRIGONOMETRIC_MAPPING_TABLE; /**< trigonometric look-up table. */ + +/** + * @brief Calculate the value of the input angle by looking up the table. Data in Q15 format. + * @param angle: Angle value to be calculated. + * @retval Calculation result in BASE_MathTypeSinCos Structure. + */ +BASE_MathTypeSinCos BASE_MATH_GetSinCos(short angle) +{ + BASE_MathTypeSinCos ret = {0}; + unsigned short uhindex; + + /* Move the zero to ensure that the mapping result is positive. */ + uhindex = (unsigned short)((int)BASE_DEFINE_INT16_ADDITIONS_VAL + (int)angle); + + /* Shift right by 6 bits. */ + uhindex /= (unsigned short)64; /* 64:Reserved 10-bit precision. */ + + switch ((unsigned short)(uhindex) & BASE_MATH_SIN_COS_MASK) { + case BASE_MATH_ANGLED0_90: /* 0 ~ 90° */ + ret.sin = g_triFunMappingTable[(unsigned char)(uhindex)]; + ret.cos = g_triFunMappingTable[(unsigned char)(BASE_DEFINE_MAPPING_TABLE_SIZE - (unsigned char)(uhindex))]; + break; + + case BASE_MATH_ANGLED90_180: /* 90 ~ 180° */ + ret.sin = g_triFunMappingTable[(unsigned char)(BASE_DEFINE_MAPPING_TABLE_SIZE - (unsigned char)(uhindex))]; + ret.cos = -g_triFunMappingTable[(unsigned char)(uhindex)]; + break; + + case BASE_MATH_ANGLED180_270: /* 180 ~ 270° */ + ret.sin = -g_triFunMappingTable[(unsigned char)(uhindex)]; + ret.cos = -g_triFunMappingTable[(unsigned char)(BASE_DEFINE_MAPPING_TABLE_SIZE - (unsigned char)(uhindex))]; + break; + + case BASE_MATH_ANGLED270_360: /* 270 ~ 360° */ + ret.sin = -g_triFunMappingTable[(unsigned char)(BASE_DEFINE_MAPPING_TABLE_SIZE - (unsigned char)(uhindex))]; + ret.cos = g_triFunMappingTable[(unsigned char)(uhindex)]; + break; + + default: + break; + } + + return ret; +} + +/** + * @brief Using Taylor Expansion to Calculate Sin Values in 90 Degrees. + * @param angle Angle value to be calculated. Note: 0 <= angle <= 90. + * @retval float Calculated sin value. + */ +static float BASE_MATH_CalSinIn90(float angle) +{ + float radian = angle * BASE_MATH_PAI * BASE_MATH_ANGLE180_RECIPROCAL; + float radian3 = radian * radian * radian; /* power(3) */ + float radian5 = radian3 * radian * radian; + float radian7 = radian5 * radian * radian; /* power(7) */ + /* Using Taylor Expansion to Calculate Sin Values in 90 Degrees. */ + return (radian - radian3 * BASE_MATH_FACTORIAL3_RECIPROCAL + radian5 * BASE_MATH_FACTORIAL5_RECIPROCAL \ + - radian7 * BASE_MATH_FACTORIAL7_RECIPROCAL); +} + +/** + * @brief Using Taylor Expansion to Calculate Sin Values for Any Angle. + * @param angle Angle value to be calculated. + * @retval float Calculated sin value. + */ +float BASE_MATH_GetSin(float angle) +{ + float angleIn360; + angleIn360 = (int)angle % BASE_MATH_ANGLE360 + angle - (int)angle; + if (angleIn360 < 0) { + angleIn360 = angleIn360 + BASE_MATH_ANGLE360; + } + if (angleIn360 < BASE_MATH_ANGLE90) { /* 0 ~ 90° */ + return BASE_MATH_CalSinIn90(angleIn360); + } + if (angleIn360 < BASE_MATH_ANGLE180) { /* 90 ~ 180° */ + return BASE_MATH_CalSinIn90(BASE_MATH_ANGLE180 - angleIn360); + } + if (angleIn360 < BASE_MATH_ANGLE270) { /* 180 ~ 270° */ + return -BASE_MATH_CalSinIn90(angleIn360 - BASE_MATH_ANGLE180); + } + return -BASE_MATH_CalSinIn90(BASE_MATH_ANGLE360 - angleIn360); /* 270 ~ 360° */ +} + +/** + * @brief Using Taylor Expansion to Calculate Sin Values for Any Angle. + * @param angle Angle value to be calculated. + * @retval float Calculated sin value. + */ +float BASE_MATH_GetCos(float angle) +{ + float angleIn360; + angleIn360 = (int)angle % BASE_MATH_ANGLE360 + angle - (int)angle; + if (angleIn360 < 0) { + angleIn360 = angleIn360 + BASE_MATH_ANGLE360; + } + if (angleIn360 < BASE_MATH_ANGLE90) { /* 0 ~ 90° */ + return BASE_MATH_CalSinIn90(BASE_MATH_ANGLE90 - angleIn360); + } + if (angleIn360 < BASE_MATH_ANGLE180) { /* 90 ~ 180° */ + return -BASE_MATH_CalSinIn90(angleIn360 - BASE_MATH_ANGLE90); + } + if (angleIn360 < BASE_MATH_ANGLE270) { /* 180 ~ 270° */ + return -BASE_MATH_CalSinIn90(BASE_MATH_ANGLE270 - angleIn360); + } + return BASE_MATH_CalSinIn90(angleIn360 - BASE_MATH_ANGLE270); /* 270 ~ 360° */ +} + +/** + * @brief Using newton iteration method to realize sqrt. + * @param x Value to be squared. + * @retval float Value after square. + */ +float BASE_MATH_Sqrt(const float x) +{ + BASE_FUNC_ASSERT_PARAM(x >= FLT_EPSILON); + const float xHalf = 0.5f * x; /* 0.5f : coefficients. */ + + union { + float x; + unsigned int i; + } u; + u.x = x; + u.i = 0x5f3759df - (u.i >> 1); /* 0x5f3759df : Magic numbers for sqrt. */ + return x * u.x * (1.5f - xHalf * u.x * u.x); /* 1.5f : coefficients. */ +} + +/** + * @brief Compute x to the n power. + * @param x Cardinality to be calculated. + * @param n Power exponent to be calculated. + * @retval float Calculated value. + */ +float BASE_MATH_Pow(float x, int n) +{ + /* check x not equal zero */ + if (x > -FLT_EPSILON && x < FLT_EPSILON) { + return 0.0f; + } + float value = x; + int power = n; + float res = 1.0; + if (power < 0) { + value = 1 / value; + power = -power; + } + /* power multiplication */ + for (unsigned int i = 0; i < (unsigned int)power; ++i) { + res *= value; + } + return res; +} + +/** + * @brief This function performs Clarke conversion. Data in Q15 format. The conversion formula is as follows: + * alpha = a; + * beta = 1 / sqrt3 * a + 2 / sqrt3 *b. + * @param input Current values of a\b items. + * @retval BASE_MathTypeAlphaBeta Conversion result in BASE_MathTypeAlphaBeta Structure. + */ +BASE_MathTypeAlphaBeta BASE_MATH_Clarke(BASE_MathTypeAB input) +{ + BASE_MathTypeAlphaBeta ret; + int aDivSort3, bDivSort3, betaTmp32; + + /* qIalpha = qIas. */ + ret.alpha = input.a; + + aDivSort3 = BASE_DEFINE_DIV_SQRT3 * (int)input.a; + + bDivSort3 = BASE_DEFINE_DIV_SQRT3 * (int)input.b; + + /* qIbeta = (2*qIbs+qIas)/sqrt(3). */ + /* Because BASE_DEFINE_DIV_SQRT3 is in the Q15 format, divide it by 32768 to ensure that the result is correct. */ + betaTmp32 = (aDivSort3 + bDivSort3 + bDivSort3) >> 15; /* 15:Move 15 bits to the right, keep Q15 format. */ + + /* Check saturation of Ibeta */ + if (betaTmp32 > INT16_MAX) { + ret.beta = INT16_MAX; + } else if (betaTmp32 < INT16_MIN) { + ret.beta = INT16_MIN; + } else { + ret.beta = (short)(betaTmp32); + } + + return ret; +} + +/** + * @brief This function performs Park coordinate conversion. Data in Q15 format. The conversion formula is as follows: + * id = alpha * cos(theta) + beta * sin(theta); + * iq = -alpha * sin(theta) + beta * cos(theta). + * @param input stator values alpha and beta in BASE_MathTypeAlphaBeta format. + * @param theta rotating frame angular position. + * @retval BASE_MathTypeQD Conversion result in BASE_MathTypeQD Structure. + */ +BASE_MathTypeQD BASE_MATH_Park(BASE_MathTypeAlphaBeta input, short theta) +{ + BASE_MathTypeQD ret; + BASE_MathTypeSinCos thetaSinCos; + int d1, d2, q1, q2, tmp32; + + thetaSinCos = BASE_MATH_GetSinCos(theta); + + /* No overflow guaranteed. */ + d1 = input.alpha * (int)thetaSinCos.cos; + + /* No overflow guaranteed. */ + d2 = input.beta * (int)thetaSinCos.sin; + + /* Id component in Q1.15 Format. */ + tmp32 = (d1 + d2) >> 15; /* 15:Move 15 bits to the right, keep Q15 format. */ + + /* Check saturation of Id. */ + if (tmp32 > INT16_MAX) { + ret.d = INT16_MAX; + } else if (tmp32 < INT16_MIN) { + ret.d = INT16_MIN; + } else { + ret.d = (short)(tmp32); + } + + /* No overflow guaranteed. */ + q1 = input.alpha * (int)thetaSinCos.sin; + + /* No overflow guaranteed. */ + q2 = input.beta * (int)thetaSinCos.cos; + + /* Iq component in Q1.15 Format. */ + tmp32 = (q2 - q1) >> 15; /* 15:Move 15 bits to the right, keep Q15 format. */ + + /* Check saturation of Iq. */ + if (tmp32 > INT16_MAX) { + ret.q = INT16_MAX; + } else if (tmp32 < INT16_MIN) { + ret.q = INT16_MIN; + } else { + ret.q = (short)(tmp32); + } + + return ret; +} + +/** + * @brief This function performs Reverse Park coordinate conversion. Data in Q15 format. The conversion formula is as + * follows: alpha = d * cos(theta) - q * sin(theta); + * beta = d * sin(theta) + q * cos(theta). + * @param input stator voltage Vq and Vd in BASE_MathTypeQD format. + * @param theta rotating frame angular position. + * @retval BASE_MathTypeAlphaBeta Conversion result in BASE_MathTypeAlphaBeta Structure. + */ +BASE_MathTypeAlphaBeta BASE_MATH_RevPark(BASE_MathTypeQD input, short theta) +{ + int alpha1, alpha2, beta1, beta2; + BASE_MathTypeSinCos thetaSinCos; + BASE_MathTypeAlphaBeta ret; + + thetaSinCos = BASE_MATH_GetSinCos(theta); + + /* No overflow guaranteed. */ + alpha1 = input.q * (int)thetaSinCos.sin; + alpha2 = input.d * (int)thetaSinCos.cos; + + ret.alpha = (short)((alpha2 - alpha1) >> 15); /* 15:Move 15 bits to the right, keep Q15 format. */ + + beta1 = input.q * (int)thetaSinCos.cos; + beta2 = input.d * (int)thetaSinCos.sin; + + ret.beta = (short)((beta1 + beta2) >> 15); /* 15:Move 15 bits to the right, keep Q15 format. */ + + return ret; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/clock.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/clock.c new file mode 100644 index 00000000..5a364125 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/clock.c @@ -0,0 +1,103 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file clock.c + * @author MCU Driver Team + * @brief Provides functions related to the dominant frequency operation and delay. + */ + +/* Includes ------------------------------------------------------------------ */ +#include "ip_crg_common.h" +#include "crg.h" +#include "clock.h" + +/** + * @brief Get the current CPU frequency. + * @param None. + * @retval System clock frequency in Hz. + */ +unsigned int BASE_FUNC_GetCpuFreqHz(void) +{ + return HAL_CRG_GetCoreClkFreq(); +} + +/** + * @brief Delay number of us. + * @param us The number of us to delay. + * @retval None. + */ +void BASE_FUNC_DelayUs(unsigned int us) +{ + unsigned int preTick = DCL_SYSTICK_GetTick(); + unsigned int tickInUs = (SYSTICK_GetCRGHZ() / CRG_FREQ_1MHz) * us; + unsigned int curTick; + unsigned int delta; + + /* Wait until the delta is greater than tickInUs */ + do { + curTick = DCL_SYSTICK_GetTick(); + delta = (curTick >= preTick) ? curTick - preTick : SYSTICK_MAX_VALUE - preTick + curTick + 1; + } while (delta < tickInUs); +} + +/** + * @brief Delay number of ms. + * @param ms The number of ms to delay. + * @retval None. + */ +void BASE_FUNC_DelayMs(unsigned int ms) +{ + for (unsigned int i = 0; i < ms; ++i) { + BASE_FUNC_DelayUs(BASE_DEFINE_DELAY_US_IN_MS); + } +} + +/** + * @brief Delay number of seconds. + * @param seconds The number of seconds to delay. + * @retval None. + */ +void BASE_FUNC_DelaySeconds(unsigned int seconds) +{ + for (unsigned int i = 0; i < seconds; ++i) { + BASE_FUNC_DelayMs(BASE_DEFINE_DELAY_MS_IN_SEC); + } +} + +/** + * @brief Delay for a certain period of time based on parameters delay and units. + * @param delay The number of 'units' to delay. + * @param units Specifies the delay unit. + * @retval None. + */ +void BASE_FUNC_Delay(unsigned int delay, BASE_DelayUnit units) +{ + switch (units) { + case BASE_DEFINE_DELAY_SECS: + BASE_FUNC_DelaySeconds(delay); + break; + case BASE_DEFINE_DELAY_MILLISECS: + BASE_FUNC_DelayMs(delay); + break; + case BASE_DEFINE_DELAY_MICROSECS: + BASE_FUNC_DelayUs(delay); + break; + default: + break; + } + return; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/generalfunc.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/generalfunc.c new file mode 100644 index 00000000..91c2d2fc --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/generalfunc.c @@ -0,0 +1,223 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file basic.c + * @author MCU Driver Team + * @brief BASE module driver + * @details This file provides firmware functions to manage the following + * functionalities of the basic functions. + * + Verifying the timeout function + * + 8-bit, 16-bit checksum function + * + Sliding averaging function + * + General state machine + * @verbatim + * Sliding averaging interface usage: + * 1) Call the BASE_FUNC_AverageInit() function to initialize and configure the buffer, + * average the window size, and set the index value for identification. + * 2) Call the BASE_FUNC_GetSlipAverageVal() function based on the index value transferred + * in the initialization function to obtain the average value of the current window. + * 3) Call the BASE_FUNC_AverageDeInit() function to close the current index channel. + * + * General state machine usage: + * 1) Add your status to enum BASE_FSM_Status; + * 2) Write your code for each state. Note that the function prototype is BASE_FSM_Status xxx(void); + * 3) Use BASE_FSM_FunRegister() to register your functions and their status; + * 4) Start the state machine using BASE_FSM_Run(). + * @endverbatim + */ + +/* Includes ------------------------------------------------------------------ */ +#include "generalfunc.h" + +/* Private variables --------------------------------------------------------- */ +BASE_AverageHandle g_averageHandle[BASE_DEFINE_SLIPAVERAGE_NUM]; +BASE_FSM_Handle g_fsmHandle; + +/** + * @brief Obtains the current tick value. + * @retval unsigned int. Current tick value. + */ +unsigned int BASE_FUNC_GetTick(void) +{ + return DCL_SYSTICK_GetTick(); +} + +/** + * @brief Query an element in an array using dichotomous lookup. Note: Arrays are sorted in ascending order. + * Returns the left index when the array element does not exist. + * @param nums Array to be searched. + * @param leng Array Length. + * @param value Value to be searched for. + * @return unsigned int Index value corresponding to value. + */ +unsigned int BASE_FUNC_FindArrayValue(const unsigned short *nums, unsigned int leng, unsigned int value) +{ + BASE_FUNC_ASSERT_PARAM(nums != NULL); + BASE_FUNC_PARAMCHECK_WITH_RET(leng > 0, 0); + unsigned int left = 0; + unsigned int right = leng - 1; + while (left < right) { + unsigned int mid = (left + right) / 2; + if (value >= nums[mid] && value < nums[mid + 1]) { + return mid; + } else if (value < nums[mid]) { + right = mid - 1; + } else { + left = mid + 1; + } + } + return left; +} + +/** + * @brief 8-bit checksum. + * @param pt Pointer to the data to be computed. + * @param len Data length. + * @return unsigned char Calculation result. + */ +unsigned char BASE_FUNC_CalcSumByte(const unsigned char *pt, unsigned int len) +{ + BASE_FUNC_ASSERT_PARAM(pt != NULL); + BASE_FUNC_PARAMCHECK_WITH_RET((len > 0), 0); + + unsigned int sum = 0; + /* calculate sum value */ + while (len--) { + sum += *pt; + pt++; + } + /* Use 8 digits */ + return (unsigned char)sum; +} + +/** + * @brief 16-bit checksum. + * @param pt Pointer to the data to be computed. + * @param len Data length. + * @return unsigned char Calculation result. + */ +unsigned short BASE_FUNC_CalcSumShort(unsigned char const * pt, unsigned int len) +{ + BASE_FUNC_ASSERT_PARAM(pt != NULL); + BASE_FUNC_PARAMCHECK_WITH_RET((len > 0), 0); + unsigned int sum = 0; + /* calculate sum value */ + while (len--) { + sum += *pt; + pt++; + } + /* Use 16 digits */ + return (unsigned short)sum; +} + +/** + * @brief Sliding average initialization function. + * @param index User-entered index value used to identify the channel, in [0, BASE_DEFINE_SLIPAVERAGE_NUM). + * @param buf Pointer to the ring buffer, it stores historical data. + * @param size Ring buffer size. + * @param calNum Indicates the average window size, that is, the number of pieces of data to be averaged. + * @return BASE_StatusType @ref BASE_StatusType. + */ +BASE_StatusType BASE_FUNC_AverageInit(unsigned int index, float *buf, unsigned int size, unsigned int calNum) +{ + /* verify param */ + BASE_FUNC_ASSERT_PARAM(buf != NULL); + BASE_FUNC_PARAMCHECK_WITH_RET((calNum > 0), BASE_STATUS_ERROR); + BASE_FUNC_PARAMCHECK_WITH_RET((size >= calNum), BASE_STATUS_ERROR); + BASE_FUNC_PARAMCHECK_WITH_RET((index < BASE_DEFINE_SLIPAVERAGE_NUM), BASE_STATUS_ERROR); + /* init handle's member */ + g_averageHandle[index].buf = buf; + g_averageHandle[index].size = size; + g_averageHandle[index].at = 0; + g_averageHandle[index].calNum = calNum; + g_averageHandle[index].total = 0; + g_averageHandle[index].cnt = 0; + + return BASE_STATUS_OK; +} + +/** + * @brief Transfer new data and return the average value after the new data is inserted. + * @param index Index value of the handle array, which is set by the user in the initialization function. + * @param val Data value. + * @return float Calculated average. + */ +float BASE_FUNC_GetSlipAverageVal(unsigned int index, float val) +{ + /* verify param */ + BASE_FUNC_ASSERT_PARAM(index < BASE_DEFINE_SLIPAVERAGE_NUM); + /* The processing data volume does not reach the constant average amount. */ + if (g_averageHandle[index].cnt < g_averageHandle[index].calNum) { + (g_averageHandle[index].cnt)++; + g_averageHandle[index].total += val; + g_averageHandle[index].buf[g_averageHandle[index].at] = val; + (g_averageHandle[index].at)++; + return g_averageHandle[index].total / g_averageHandle[index].cnt; /* g_averageHandle[index].cnt > 0 */ + } + /* The processing data volume reach the constant average amount. */ + g_averageHandle[index].total += val - g_averageHandle[index].buf[(g_averageHandle[index].at + \ + g_averageHandle[index].size - g_averageHandle[index].calNum) % \ + g_averageHandle[index].size]; + g_averageHandle[index].buf[g_averageHandle[index].at] = val; + g_averageHandle[index].at = (g_averageHandle[index].at + 1) % g_averageHandle[index].size; + return g_averageHandle[index].total / g_averageHandle[index].calNum; /* g_averageHandle[index].calNum > 0 */ +} + +/** + * @brief Disables the channel specified by index. + * @param index Index value of the handle array, which is set by the user in the initialization function. + * @return None. + */ +void BASE_FUNC_AverageDeInit(unsigned int index) +{ + /* verify param */ + BASE_FUNC_ASSERT_PARAM(index < BASE_DEFINE_SLIPAVERAGE_NUM); + g_averageHandle[index].buf = NULL; +} + +/** + * @brief Registering functions to the state machine. Note that the function prototype is BASE_FSM_Status xxx(void). + * @param index Status of the function. + * @param funAddress Function Pointer. + * @return None. + */ +void BASE_FSM_FunRegister(BASE_FSM_Status index, FunType funAddress) +{ + BASE_FUNC_PARAMCHECK_NO_RET(index >= BASE_FSM_START && index <= BASE_DEFINE_FSM_END); + g_fsmHandle.funList[index] = funAddress; +} + +/** + * @brief Start the state machine. + * @param delayTime State switching delay time. + * @param delayUnit Indicates the unit of the state switch delay. + * @return None. + */ +void BASE_FSM_Run(unsigned int delayTime, BASE_DelayUnit delayUnit) +{ + g_fsmHandle.nextFun = BASE_FSM_START; + + FunType execFun; + while (1) { + execFun = g_fsmHandle.funList[g_fsmHandle.nextFun]; + g_fsmHandle.nextFun = execFun(); + if (g_fsmHandle.nextFun < BASE_FSM_START || g_fsmHandle.nextFun > BASE_DEFINE_FSM_END) { + break; + } + BASE_FUNC_Delay(delayTime, delayUnit); + } +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/interrupt.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/interrupt.c new file mode 100644 index 00000000..c85e5fc1 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/interrupt.c @@ -0,0 +1,555 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file interrupt.c + * @author MCU Driver Team + * @brief Provides the handle template functions for processing exceptions and interrupts supported by the current + * functionalities of the interrupt. + * + Initialization and de-initialization functions + * + Regester and de-regester interrupt + * + Enable and disable interrupt + * + Configure interrupt + */ + +/* Includes ------------------------------------------------------------------ */ +#include "interrupt.h" +#include "baseinc.h" + +/* Macro definitions ---------------------------------------------------------*/ + +/* Typedef definitions -------------------------------------------------------*/ +void IRQ_PriorityInit(void); +static void IRQ_DummyHandler(void *arg); +static void IRQ_SetCallBack(unsigned int irqNum, IRQ_PROC_FUNC func, void *arg); + +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) +static inline unsigned int IRQ_GetCpuPrivilege(void); + +static struct IRQ_Mask { + unsigned int irqMie; + unsigned int irqLocien0; + unsigned int irqLocien1; + unsigned int irqLocien2; + unsigned int irqLocien3; +} g_irqMask; + +volatile unsigned int g_RiscvPrivMode = 0; +#endif + +/** + * @brief Interrupt vector table, supports up to IRQ_MAX interrupts, except for IRQ_VECTOR_CNT internal + * standard interrupts, which can be configured according to actual conditions. + */ +IRQ_ARG_FUNC g_irqCallbackFunc[IRQ_MAX]; + +/* Initialization and de-initialization functions ----------------------------*/ +/** + * @brief Exception/Interrupt Handler Entry. + * @param irqNum external interrupt number. + * @retval None + */ +void InterruptEntry(unsigned int irqNum) +{ + g_irqCallbackFunc[irqNum].pfnHandler(g_irqCallbackFunc[irqNum].param); + IRQ_ClearN(irqNum); +} + +/** + * @brief Irq initialization. + * @param none. + * @retval None + */ +void IRQ_Init(void) +{ + unsigned int index; + + for (index = 0; index < IRQ_MAX; index++) { + g_irqCallbackFunc[index].pfnHandler = IRQ_DummyHandler; + g_irqCallbackFunc[index].param = NULL; + } +} + +/* Register and Unregister interrupt -----------------------------------------*/ +/** + * @brief Register IRQ Callback function and parameter. + * @param irqNum External interrupt number. + * @param func Callback function. + * @param arg Parameter of callback function. + * @retval BASE_STATUS_OK(success) or IRQ_ERRNO_ALREADY_CREATED(fail) or IRQ_ERRNO_NUM_INVALID. + * @note In the corresponding interrupt handler, manually clear the interrupt source and the corresponding interrupt + * flag bit (call the IRQ_ClearN function to clear the interrupt), otherwise the interrupt will always be + * triggered. + */ +unsigned int IRQ_Register(unsigned int irqNum, IRQ_PROC_FUNC func, void *arg) +{ + INTERRUPT_ASSERT_PARAM(func != NULL); + INTERRUPT_PARAM_CHECK_WITH_RET(irqNum < IRQ_MAX, IRQ_ERRNO_NUM_INVALID); + + if (g_irqCallbackFunc[irqNum].pfnHandler != IRQ_DummyHandler) { + return IRQ_ERRNO_ALREADY_CREATED; + } + IRQ_SetCallBack(irqNum, func, arg); + return BASE_STATUS_OK; +} + +/** + * @brief Unregister IRQ Callback. + * @param irqNum External interrupt number. + * @retval BASE_STATUS_OK or IRQ_ERRNO_NUM_INVALID. + */ +unsigned int IRQ_Unregister(unsigned int irqNum) +{ + INTERRUPT_PARAM_CHECK_WITH_RET(irqNum < IRQ_MAX, IRQ_ERRNO_NUM_INVALID); + g_irqCallbackFunc[irqNum].pfnHandler = IRQ_DummyHandler; + g_irqCallbackFunc[irqNum].param = NULL; + return BASE_STATUS_OK; +} + +/* Enable and disable interrupt ----------------------------------------------*/ +/** + * @brief Global Interrupt Enable. + * @retval None. + */ +void IRQ_Enable(void) +{ +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + unsigned int priv = IRQ_GetCpuPrivilege(); + + RISCV_PRIV_MODE_SWITCH(priv); + + g_irqMask.irqMie |= READ_CSR(mie); + g_irqMask.irqLocien0 |= READ_CUSTOM_CSR(LOCIEN0); + g_irqMask.irqLocien1 |= READ_CUSTOM_CSR(LOCIEN1); + g_irqMask.irqLocien2 |= READ_CUSTOM_CSR(LOCIEN2); + g_irqMask.irqLocien3 |= READ_CUSTOM_CSR(LOCIEN3); + + WRITE_CSR(mie, g_irqMask.irqMie); + WRITE_CUSTOM_CSR_VAL(LOCIEN0, g_irqMask.irqLocien0); + WRITE_CUSTOM_CSR_VAL(LOCIEN1, g_irqMask.irqLocien1); + WRITE_CUSTOM_CSR_VAL(LOCIEN2, g_irqMask.irqLocien2); + WRITE_CUSTOM_CSR_VAL(LOCIEN3, g_irqMask.irqLocien3); + + RISCV_PRIV_MODE_SWITCH(priv); +#else + SET_CSR(mstatus, MSTATUS_MIE); +#endif +} + +/** + * @brief Global Interrupt Disable. + * @retval BASE_STATUS_OK. + * @note Must be called in Interrupt(Machine mode) + */ +void IRQ_Disable(void) +{ +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + unsigned int priv = IRQ_GetCpuPrivilege(); + + RISCV_PRIV_MODE_SWITCH(priv); + + g_irqMask.irqMie = READ_CSR(mie); + g_irqMask.irqLocien0 = READ_CUSTOM_CSR(LOCIEN0); + g_irqMask.irqLocien1 = READ_CUSTOM_CSR(LOCIEN1); + g_irqMask.irqLocien2 = READ_CUSTOM_CSR(LOCIEN2); + g_irqMask.irqLocien3 = READ_CUSTOM_CSR(LOCIEN3); + + WRITE_CSR(mie, 0); + WRITE_CUSTOM_CSR_VAL(LOCIEN0, 0); + WRITE_CUSTOM_CSR_VAL(LOCIEN1, 0); + WRITE_CUSTOM_CSR_VAL(LOCIEN2, 0); + WRITE_CUSTOM_CSR_VAL(LOCIEN3, 0); + + RISCV_PRIV_MODE_SWITCH(priv); +#else + CLEAR_CSR(mstatus, MSTATUS_MIE | MSTATUS_MPIE); +#endif +} + +/** + * @brief Enable the specified interrupt. + * @param irqNum External interrupt number. + * @retval BASE_STATUS_OK or IRQ_ERRNO_NUM_INVALID. + */ +unsigned int IRQ_EnableN(unsigned int irqNum) +{ + unsigned int irqOrder; + unsigned int locienVal; +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + unsigned int priv = IRQ_GetCpuPrivilege(); +#endif + + INTERRUPT_PARAM_CHECK_WITH_RET((irqNum >= IRQ_VECTOR_CNT && irqNum < IRQ_MAX), IRQ_ERRNO_NUM_INVALID); + + /* The interrupt enable bits that can be controlled in the mie register (32 bits), up to 32 + can be controlled, and each bit corresponds to an interrupt enable */ + + RISCV_PRIV_MODE_SWITCH(priv); + + if (irqNum < IRQ_MIE_TOTAL_CNT) { + irqOrder = 1U << irqNum; + SET_CSR(mie, irqOrder); + } else if (irqNum < IRQ_LOCIEN1_OFFSET) { + irqOrder = irqNum - IRQ_MIE_TOTAL_CNT; + locienVal = READ_CUSTOM_CSR(LOCIEN0); + locienVal |= (1U << irqOrder); + WRITE_CUSTOM_CSR_VAL(LOCIEN0, locienVal); + } else if (irqNum < IRQ_LOCIEN2_OFFSET) { + irqOrder = irqNum - IRQ_LOCIEN1_OFFSET; + locienVal = READ_CUSTOM_CSR(LOCIEN1); + locienVal |= (1U << irqOrder); + WRITE_CUSTOM_CSR_VAL(LOCIEN1, locienVal); + } else { + irqOrder = irqNum - IRQ_LOCIEN2_OFFSET; + locienVal = READ_CUSTOM_CSR(LOCIEN2); + locienVal |= (1U << irqOrder); + WRITE_CUSTOM_CSR_VAL(LOCIEN2, locienVal); + } + + RISCV_PRIV_MODE_SWITCH(priv); + + return BASE_STATUS_OK; +} + +/** + * @brief Disable the specified interrupt. + * @param irqNum External interrupt number. + * @retval BASE_STATUS_OK or IRQ_ERRNO_NUM_INVALID or IRQ_ERRNO_NOT_CREATED. + */ +unsigned int IRQ_DisableN(unsigned int irqNum) +{ + unsigned int irqOrder; +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + unsigned int priv = IRQ_GetCpuPrivilege(); +#endif + + INTERRUPT_PARAM_CHECK_WITH_RET((irqNum >= IRQ_VECTOR_CNT && irqNum < IRQ_MAX), IRQ_ERRNO_NUM_INVALID); + INTERRUPT_PARAM_CHECK_WITH_RET((g_irqCallbackFunc[irqNum].pfnHandler != IRQ_DummyHandler), IRQ_ERRNO_NOT_CREATED); + + RISCV_PRIV_MODE_SWITCH(priv); + + if (irqNum < IRQ_MIE_TOTAL_CNT) { + irqOrder = 1U << irqNum; + CLEAR_CSR(mie, irqOrder); + } else if (irqNum < IRQ_LOCIEN1_OFFSET) { + irqOrder = 1U << (irqNum - IRQ_MIE_TOTAL_CNT); + CLEAR_CUSTOM_CSR(LOCIEN0, irqOrder); + } else if (irqNum < IRQ_LOCIEN2_OFFSET) { + irqOrder = 1U << (irqNum - IRQ_LOCIEN1_OFFSET); + CLEAR_CUSTOM_CSR(LOCIEN1, irqOrder); + } else { + irqOrder = 1U << (irqNum - IRQ_LOCIEN2_OFFSET); + CLEAR_CUSTOM_CSR(LOCIEN2, irqOrder); + } + + RISCV_PRIV_MODE_SWITCH(priv); + + return BASE_STATUS_OK; +} + +/** + * @brief Print RISCV register. + * @param context. + * @note The actual code is generated by IDE + * @retval None. + */ +__weak void SysErrPrint(const SyserrContext *context) +{ + BASE_FUNC_UNUSED(context); +} + +/** + * @brief System error completion processing + * @param None. + * @retval None. + */ +static void SysErrFinish(void) +{ +} + +/** + * @brief Exception Handler Entry. + * @param context error context. + * @retval None. + */ +void SysErrExcEntry(const SyserrContext *context) +{ + SysErrPrint(context); + SysErrFinish(); +} + +/** + * @brief NMI Interrupt Handler Entry. + * @param context error context. + * @retval None. + */ +void SysErrNmiEntry(const SyserrContext *context) +{ + INTERRUPT_ASSERT_PARAM(context != NULL); + SysErrPrint(context); + SysErrFinish(); +} +/** + * @brief Set the priority of local interrupt. + * @param intNum GROUP NUM. + * @param interPriNum Local interrupt number, which equals external interrupt number - IRQ_VECTOR_CN. + * @param prior local int prioroty. + * @retval None + */ +static void SetLocalIntNumPri(unsigned int intNum, unsigned int interPriNum, unsigned int prior) +{ + switch (intNum) { + case 8: /* GROUP8 */ + SET_LOCAL_INTER_NUM_PRI(8, interPriNum, prior); + break; + case 9: /* GROUP9 */ + SET_LOCAL_INTER_NUM_PRI(9, interPriNum, prior); + break; + case 10: /* GROUP10 */ + SET_LOCAL_INTER_NUM_PRI(10, interPriNum, prior); + break; + case 11: /* GROUP11 */ + SET_LOCAL_INTER_NUM_PRI(11, interPriNum, prior); + break; + case 12: /* GROUP12 */ + SET_LOCAL_INTER_NUM_PRI(12, interPriNum, prior); + break; + case 13: /* GROUP13 */ + SET_LOCAL_INTER_NUM_PRI(13, interPriNum, prior); + break; + case 14: /* GROUP14 */ + SET_LOCAL_INTER_NUM_PRI(14, interPriNum, prior); + break; + case 15: /* GROUP15 */ + SET_LOCAL_INTER_NUM_PRI(15, interPriNum, prior); + break; + default: + break; + } +} +/** + * @brief Set the priority of local interrupt. + * @param interPriNum Local interrupt number, which equals external interrupt number - IRQ_VECTOR_CN. + * @param prior Priority of this local interrupt to be set. + * @retval None. + */ +static void IRQ_SetLocalPriority(unsigned int interPriNum, unsigned int prior) +{ +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + unsigned int priv = IRQ_GetCpuPrivilege(); +#endif + RISCV_PRIV_MODE_SWITCH(priv); + unsigned int intNum = GET_LOCAL_INTER_CONFIGREG_NUM(interPriNum); + switch (intNum) { + case 0: /* GROUP0 */ + SET_LOCAL_INTER_NUM_PRI(0, interPriNum, prior); + break; + case 1: /* GROUP1 */ + SET_LOCAL_INTER_NUM_PRI(1, interPriNum, prior); + break; + case 2: /* GROUP2 */ + SET_LOCAL_INTER_NUM_PRI(2, interPriNum, prior); + break; + case 3: /* GROUP3 */ + SET_LOCAL_INTER_NUM_PRI(3, interPriNum, prior); + break; + case 4: /* GROUP4 */ + SET_LOCAL_INTER_NUM_PRI(4, interPriNum, prior); + break; + case 5: /* GROUP5 */ + SET_LOCAL_INTER_NUM_PRI(5, interPriNum, prior); + break; + case 6: /* GROUP6 */ + SET_LOCAL_INTER_NUM_PRI(6, interPriNum, prior); + break; + case 7: /* GROUP7 */ + SET_LOCAL_INTER_NUM_PRI(7, interPriNum, prior); + break; + default: + SetLocalIntNumPri(intNum, interPriNum, prior); + break; + } + RISCV_PRIV_MODE_SWITCH(priv); +} + +/** + * @brief Set the priority of external interrupt. + * @param irqNum External interrupt number. + * @param priority. + * @retval IRQ_ERRNO_NUM_INVALID or IRQ_ERRNO_PRIORITY_INVALID or BASE_STATUS_OK. + */ +unsigned int IRQ_SetPriority(unsigned int irqNum, unsigned int priority) +{ + INTERRUPT_PARAM_CHECK_WITH_RET((irqNum >= IRQ_VECTOR_CNT && irqNum < IRQ_MAX), IRQ_ERRNO_NUM_INVALID); + INTERRUPT_PARAM_CHECK_WITH_RET((priority >= IRQ_PRIO_LOWEST && priority <= IRQ_PRIO_HIGHEST), \ + IRQ_ERRNO_PRIORITY_INVALID); + + /* The locipri register is specifically used to configure the priority of the + external non-standard interrupts of the CPU, so the number of internal + standard interrupts should be subtracted */ + IRQ_SetLocalPriority(irqNum - IRQ_VECTOR_CNT, priority); + + return BASE_STATUS_OK; +} +/** + * @brief Get the priority of local interrupt. + * @param intNum GROUP NUM. + * @param interPriNum Local interrupt number, which equals external interrupt number - IRQ_VECTOR_CN. + * @param prior local int prioroty. + * @retval None + */ +static void GetLocaIntNumPri(unsigned int intNum, unsigned int interPriNum, unsigned int prior) +{ + switch (intNum) { + case 8: /* GROUP8 */ + GET_LOCAL_INTER_NUM_PRI(8, interPriNum, prior); + break; + case 9: /* GROUP9 */ + GET_LOCAL_INTER_NUM_PRI(9, interPriNum, prior); + break; + case 10: /* GROUP10 */ + GET_LOCAL_INTER_NUM_PRI(10, interPriNum, prior); + break; + case 11: /* GROUP11 */ + GET_LOCAL_INTER_NUM_PRI(11, interPriNum, prior); + break; + case 12: /* GROUP12 */ + GET_LOCAL_INTER_NUM_PRI(12, interPriNum, prior); + break; + case 13: /* GROUP13 */ + GET_LOCAL_INTER_NUM_PRI(13, interPriNum, prior); + break; + case 14: /* GROUP14 */ + GET_LOCAL_INTER_NUM_PRI(14, interPriNum, prior); + break; + case 15: /* GROUP15 */ + GET_LOCAL_INTER_NUM_PRI(15, interPriNum, prior); + break; + default: + break; + } +} + +/** + * @brief Get the priority of local interrupt. + * @param interPriNum Local interrupt number, which equals external interrupt number - IRQ_VECTOR_CN. + * @retval prior Priority of this local interrupt to be set. + */ +static unsigned int IRQ_GetLocalPriority(unsigned int interPriNum) +{ +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + unsigned int priv = IRQ_GetCpuPrivilege(); +#endif + unsigned int prior = 0; + RISCV_PRIV_MODE_SWITCH(priv); + unsigned int intNum = GET_LOCAL_INTER_CONFIGREG_NUM(interPriNum); + switch (intNum) { + case 0: /* GROUP0 */ + GET_LOCAL_INTER_NUM_PRI(0, interPriNum, prior); + break; + case 1: /* GROUP1 */ + GET_LOCAL_INTER_NUM_PRI(1, interPriNum, prior); + break; + case 2: /* GROUP2 */ + GET_LOCAL_INTER_NUM_PRI(2, interPriNum, prior); + break; + case 3: /* GROUP3 */ + GET_LOCAL_INTER_NUM_PRI(3, interPriNum, prior); + break; + case 4: /* GROUP4 */ + GET_LOCAL_INTER_NUM_PRI(4, interPriNum, prior); + break; + case 5: /* GROUP5 */ + GET_LOCAL_INTER_NUM_PRI(5, interPriNum, prior); + break; + case 6: /* GROUP6 */ + GET_LOCAL_INTER_NUM_PRI(6, interPriNum, prior); + break; + case 7: /* GROUP7 */ + GET_LOCAL_INTER_NUM_PRI(7, interPriNum, prior); + break; + default: + GetLocaIntNumPri(intNum, interPriNum, prior); + break; + } + RISCV_PRIV_MODE_SWITCH(priv); + return prior; +} +/** + * @brief Get the priority of external interrupt. + * @param irqNum External interrupt number. + * @output priority. + * @retval IRQ_ERRNO_NUM_INVALID or IRQ_ERRNO_PRIORITY_INVALID or BASE_STATUS_OK. + */ +unsigned int IRQ_GetPriority(unsigned int irqNum, unsigned int *priority) +{ + INTERRUPT_PARAM_CHECK_WITH_RET(irqNum < IRQ_MAX, IRQ_ERRNO_NUM_INVALID); + + /* The locipri register is specifically used to configure the priority of the + external non-standard interrupts of the CPU, so the number of internal + standard interrupts should be subtracted */ + *priority = IRQ_GetLocalPriority(irqNum - IRQ_VECTOR_CNT); + + return BASE_STATUS_OK; +} + +/** + * @brief Clear all external interrupts + * @retval BASE_STATUS_OK or IRQ_ERRNO_NOT_CREATED + */ +unsigned int IRQ_ClearAll(void) +{ + unsigned int index; + for (index = IRQ_VECTOR_CNT; index < IRQ_MAX; index++) { + IRQ_ClearN(index); + } + return BASE_STATUS_OK; +} + +/** + * @brief Interrupt dummy handler + * @param arg Not used + * @retval None. + */ +static void IRQ_DummyHandler(void *arg) +{ + BASE_FUNC_UNUSED(arg); +} + +/** + * @brief Construct a new irq setcallback object + * @param irqNum external interrupt number + * @param func callback function + * @param arg callback arg + * @retval None. + */ +static inline void IRQ_SetCallBack(unsigned int irqNum, IRQ_PROC_FUNC func, void *arg) +{ + g_irqCallbackFunc[irqNum].param = arg; + g_irqCallbackFunc[irqNum].pfnHandler = func; +} + +/** + * @brief Get CPU Privilege by ecall + * @param none + * @retval mcause value + */ +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) +static inline unsigned int IRQ_GetCpuPrivilege(void) +{ + return (g_RiscvPrivMode == 0) ? RISCV_U_MODE : RISCV_M_MODE; +} +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/lock.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/lock.c new file mode 100644 index 00000000..764a7cf2 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/lock.c @@ -0,0 +1,82 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file lock.c + * @author MCU Driver Team + * @brief Provides functions about locks. + */ + +/* Includes ------------------------------------------------------------------ */ +#include "lock.h" + +/* Global Variables----------------------------------------------------------- */ +unsigned int g_baseLock[CHIP_LOCK_TOTAL]; /**< Used to store the hardware lock status */ + +/** + * @brief Attempt to acquire a lock for the specified address. + * @param addr Point to the address where the lock is obtained. + * @retval true, Succeeded in obtaining the lock. + * @retval false, Failed to obtain the lock. The resource has been locked. + */ +bool BASE_FUNC_SoftwareLock(unsigned int * const addr) +{ + BASE_FUNC_PARAMCHECK_WITH_RET(addr, false); + + unsigned int tmpLocked = *addr; + *addr = BASE_STATUS_LOCKED; + /* Atomic exchange instructions are not supported. Lock determination and locking may be interrupted by */ + /* interrupts. To ensure atomicity, disable the corresponding interrupts. */ + if (tmpLocked == BASE_STATUS_UNLOCKED) { + return true; + } + return false; +} + +/** + * @brief Releases the lock of the specified address. + * @param addr Point to the address that releases the lock. + * @retval None. + */ +void BASE_FUNC_SoftwareUnLock(unsigned int * const addr) +{ + BASE_FUNC_PARAMCHECK_NO_RET(addr); + + *addr = BASE_STATUS_UNLOCKED; +} + +/** + * @brief Attempt to acquire a lock on the specified hardware resource by hwIndex. + * @param hwIndex Hardware Resource ID. + * @retval true, Succeeded in obtaining the Hardware Resource lock. + * @retval false, Failed to obtain the Hardware Resource lock. The resource has been locked. + */ +bool BASE_FUNC_HardwareLock(CHIP_LockType const hwIndex) +{ + BASE_FUNC_PARAMCHECK_WITH_RET((hwIndex >= 0 && hwIndex < CHIP_LOCK_TOTAL), false); + return BASE_FUNC_SoftwareLock(&g_baseLock[hwIndex]); +} + +/** + * @brief Releases the lock of a specified hardware resource. + * @param hwIndex Hardware Resource ID. + * @retval None. + */ +void BASE_FUNC_HardwareUnLock(CHIP_LockType const hwIndex) +{ + BASE_FUNC_PARAMCHECK_NO_RET(hwIndex >= 0 && hwIndex < CHIP_LOCK_TOTAL); + BASE_FUNC_SoftwareUnLock(&g_baseLock[hwIndex]); +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/reset.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/reset.c new file mode 100644 index 00000000..c7c4e085 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/base/src/reset.c @@ -0,0 +1,41 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file reset.c + * @author MCU Driver Team + * @brief Provides functions related to software reset. + */ + +/* Includes ------------------------------------------------------------------ */ +#include "reset.h" +#include "crg_ip.h" + +/** + * @brief Soft reset interface + * @retval None. + */ +void BASE_FUNC_SoftReset(void) +{ + DCL_SYSCTRL_ScWriteProtectionDisable(); + /* Set core clock as CRG_CORE_CLK_SELECT_HOSC. */ + DCL_CRG_SetCoreClkSel(CRG, CRG_CORE_CLK_SELECT_HOSC); + DCL_SYSCTRL_SoftReset(); + + while (1) { + __asm__ volatile ("nop"); + } +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/can/common/inc/can.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/can/common/inc/can.h new file mode 100644 index 00000000..b9f2e930 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/can/common/inc/can.h @@ -0,0 +1,110 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file can.h + * @author MCU Driver Team + * @brief CAN module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the CAN. + * + Definition of the CAN handle structure. + * + Initialization and de-initialization functions. + * + Sending and receiving CAN data frames functions. + * + Interrupt handler function and user registration callback function. + */ + +/* Includes ------------------------------------------------------------------*/ +#ifndef McuMagicTag_CAN_H +#define McuMagicTag_CAN_H + +#include "can_ip.h" + + +/** + * @defgroup CAN CAN + * @brief CAN module. + * @{ + */ + +/** + * @defgroup CAN_Common CAN Common + * @brief CAN common external module. + * @{ + */ + +/** + * @defgroup CAN_Handle_Definition ADC Handle Definition + * @{ + */ + +/** + * @brief Definition of the CAN handle structure. + */ +typedef struct _CAN_Handle { + CAN_RegStruct *baseAddress; /**< CAN registers base address */ + CAN_TypeMode typeMode; /**< Work mode */ + CAN_TestMode_Configure *testModeConfigure; /**< Test mode configure */ + CAN_Seg1_Phase seg1Phase; /**< Seg1Phase: Phase Buffer Section 1, propagation section */ + CAN_Seg2_Phase seg2Phase; /**< Seg2Phase: Phase Buffer Section 2 */ + unsigned int prescalser; /**< CAN frequency divider, range: 1 ~ 64 */ + CAN_Sync_Jump_Width sjw; /**< Sync jump width coefficient */ + volatile CAN_State_Type state; /**< Transmit status of the CAN. */ + volatile CANFrame *rxFrame; /**< Rx buff */ + CAN_FilterConfigure *rxFilter; /**< Received Frame Filtering Configuration */ + unsigned int rxFIFODepth; /**< Number of receive FIFO composed by packet objects */ + bool autoRetrans; /**< Automatic retransmission of interfered message */ + + CAN_UserCallBack userCallBack; /**< User call back function of CAN */ + CAN_ExtendHandle handleEx; /**< CAN extend handle */ +} CAN_Handle; + +typedef void (* CAN_CallbackType)(void *handle); +/** + * @} + */ + +/** + * @defgroup CAN_API_Declaration CAN HAL API + * @{ + */ +BASE_StatusType HAL_CAN_Init(CAN_Handle *canHandle); +BASE_StatusType HAL_CAN_DeInit(CAN_Handle *canHandle); +BASE_StatusType HAL_CAN_ReadIT(CAN_Handle *canHandle, CANFrame *data, CAN_FilterConfigure *filterConfigure); +BASE_StatusType HAL_CAN_Write(CAN_Handle *canHandle, CANFrame *data); + +/* CAN status */ +CAN_ErrorStatus HAL_CAN_GetErrorStatus(CAN_Handle *canHandle); +unsigned int HAL_CAN_GetErrorStatusCode(CAN_Handle *canHandle); +CAN_BusOffStatus HAL_CAN_GetBusOffStatus(CAN_Handle *canHandle); +CAN_MessageReceiveStatus HAL_CAN_MessageReceiveStatus(CAN_Handle *canHandle); +CAN_MessageSendStatus HAL_CAN_MessageSendStatus(CAN_Handle *canHandle); +/* CAN interrupt service funciton. */ +void HAL_CAN_IrqHandler(void *handle); +BASE_StatusType HAL_CAN_RegisterCallBack(CAN_Handle *canHandle, CAN_CallBackFunType typeID, + CAN_CallbackType pCallback); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_CAN_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/can/inc/can_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/can/inc/can_ip.h new file mode 100644 index 00000000..f25c3836 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/can/inc/can_ip.h @@ -0,0 +1,1738 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file can_ip.h + * @author MCU Driver Team + * @brief CAN module driver. + * @details This file provides DCL functions to manage CAN and Definition of + * specific parameters + * + Definition of CAN configuration parameters. + * + CAN register mapping structure. + * + Parameters check functions. + * + Direct configuration layer interface + */ + +/* Macro definitions */ +#ifndef McuMagicTag_CAN_IP_H +#define McuMagicTag_CAN_IP_H + +#define PRESCALSER_MIN 1 +#define PRESCALSER_MAX 64 + +#define MESSAGE_NUMBER_MIN 1 +#define MESSAGE_NUMBER_MAX 32 + +#ifdef CAN_PARAM_CHECK +#define CAN_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define CAN_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define CAN_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define CAN_ASSERT_PARAM(para) ((void)0U) +#define CAN_PARAM_CHECK_NO_RET(para) ((void)0U) +#define CAN_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +#include "baseinc.h" + +/** + * @addtogroup CAN + * @{ + */ + +/** + * @defgroup CAN_IP CAN_IP + * @brief CAN_IP: can_v0. + * @{ + */ + +/** + * @defgroup CAN_Param_Def CAN Parameters Definition + * @brief Definition of CAN configuration parameters. + * @{ + */ + +/** + * @brief Extent handle definition of CAN + */ +typedef struct { +} CAN_ExtendHandle; + +/** + * @brief Type ID of the callback function registered by the user. + */ +typedef enum { + CAN_WRITE_FINISH = 0x00000000U, + CAN_READ_FINISH = 0x00000001U, + CAN_TRNS_ERROR = 0x00000002U +} CAN_CallBackFunType; + +/** + * @brief Type define of user callback function + */ +typedef struct { + void (* WriteFinishCallBack)(void *handle); /**< CAN tx interrupt complete callback function for users */ + void (* ReadFinishCallBack)(void *handle); /**< CAN rx interrupt complete callback function for users */ + void (* TransmitErrorCallBack)(void *handle); /**< CAN mode error callback function for users */ +} CAN_UserCallBack; + +/** + * @brief CAN state type. + */ +typedef enum { + CAN_STATE_NONE_INIT = 0x00000000U, + CAN_STATE_READY = 0x00000001U, + CAN_STATE_BUSY_TX = 0x00000002U, + CAN_STATE_BUSY_RX = 0x00000003u, +} CAN_State_Type; + +/** + * @brief Error status code: the last error status on the CAN bus. + */ +typedef enum { + CAN_ERROR_NONE = 0x00000000U, + CAN_ERROR_PADDING = 0x00000001U, + CAN_ERROR_FORMAL = 0x00000002U, + CAN_ERROR_ANSWER = 0x00000003U, + CAN_ERROR_BIT1 = 0x00000004U, + CAN_ERROR_BIT0 = 0x00000005U, + CAN_ERROR_CRC = 0x00000006U +} CAN_ERROR_StatusCode; + +/** + * @brief Indicates the error status. + * @details CAN Error Status Code: + * +CAN_ACTIVE_ERROR: active error defined by the CAN protocol; + * +CAN_PASSIVE_ERROR: passive error defined by the CAN protocol. + */ +typedef enum { + CAN_ACTIVE_ERROR = 0x00000000U, + CAN_PASSIVE_ERROR = 0x00000001U +} CAN_ErrorStatus; + +/** + * @brief Bus-off status. + * @details CAN Bus-off Status: + * CAN_BUSSOFF_OFF: The CAN module is not in the bus-off state. + * CAN_BUSSOFF_ON: The CAN module is in the bus-off state. + */ +typedef enum { + CAN_BUSOFF_OFF = 0x00000000U, + CAN_BUSOFF_ON = 0x00000001U +} CAN_BusOffStatus; + +/** + * @brief Status of CAN message receive status. + * @details CAN message receive status: + * CAN_MESSAGE_RECEIVE_OK: receive message success. + * CAN_MESSAGE_RECEIVE_ERROR: receive message error. + */ +typedef enum { + CAN_MESSAGE_RECEIVE_OK = 0x00000000U, + CAN_MESSAGE_RECEIVE_ERROR = 0x00000001U +}CAN_MessageReceiveStatus; + +/** + * @brief Status of CAN message send status. + * @details CAN message receive status: + * CAN_MESSAGE_SEND_OK: send message success. + * CAN_MESSAGE_SEND_ERROR: send message error. + */ +typedef enum { + CAN_MESSAGE_SEND_OK = 0x00000000U, + CAN_MESSAGE_SEND_ERROR = 0x00000001U +}CAN_MessageSendStatus; + +/** + * @brief Work mode select. + */ +typedef enum { + CAN_MODE_NORMAL = 0x00000000U, + CAN_MODE_TEST = 0x00000001U +} CAN_TypeMode; + +/** + * @brief Test status select in test mode. + * @details Mode type: + * + loopBack mode, 1: enabele, rx can receive tx frame ; 0: disable + * + silent mode, 1: enabele, cannot send frame to others; 0: disable + * + basic mode, 1: enable, IF1 used for tx buffer, IF2 used for rx buffer; 0: disable + */ +typedef struct { + unsigned int loopBack; + unsigned int silent; + unsigned int basic; +} CAN_TestMode_Configure; + +/** + * @brief The type of CAN frame. + * @details CAN frame type: + * + CAN_TYPEFRAME_STD_DATA -- Standard data frame + * + CAN_TYPEFRAME_EXT_DATA -- Extended data Frame + * + CAN_TYPEFRAME_STD_REMOTE -- Standard remote frame + * + CAN_TYPEFRAME_EXT_REMOTE -- Extended remote Frame + */ +typedef enum { + CAN_TYPEFRAME_STD_DATA = 0x00000000U, + CAN_TYPEFRAME_EXT_DATA = 0x00000001U, + CAN_TYPEFRAME_STD_REMOTE = 0x00000002U, + CAN_TYPEFRAME_EXT_REMOTE = 0x00000003U +} CAN_TypeFrame; + +/** + * @brief Type of the received frame after filtering. + * @details Filtering receive frame type: + * + CAN_FILTERFRAME_STD_DATA -- Standard data frame + * + CAN_FILTERFRAME_EXT_DATA -- Extended data frame + * + CAN_FILTERFRAME_STD_EXT_DATA -- Standard remote frame + */ +typedef enum { + CAN_FILTERFRAME_STD_DATA = 0x00000000U, + CAN_FILTERFRAME_EXT_DATA = 0x00000001U, + CAN_FILTERFRAME_STD_EXT_DATA = 0x00000002U +} CAN_FilterFrame; + +/** + * @brief Time quanta of phase buffer section 1 and propagation section. + */ +typedef enum { + CAN_SEG1_2TQ = 0x00000002U, + CAN_SEG1_3TQ = 0x00000003U, + CAN_SEG1_4TQ = 0x00000004U, + CAN_SEG1_5TQ = 0x00000005U, + CAN_SEG1_6TQ = 0x00000006U, + CAN_SEG1_7TQ = 0x00000007U, + CAN_SEG1_8TQ = 0x00000008U, + CAN_SEG1_9TQ = 0x00000009U, + CAN_SEG1_10TQ = 0x0000000AU, + CAN_SEG1_11TQ = 0x0000000BU, + CAN_SEG1_12TQ = 0x0000000CU, + CAN_SEG1_13TQ = 0x0000000DU, + CAN_SEG1_14TQ = 0x0000000EU, + CAN_SEG1_15TQ = 0x0000000FU, + CAN_SEG1_16TQ = 0x00000010U +} CAN_Seg1_Phase; + +/** + * @brief Time quanta of phase buffer section 2. + */ +typedef enum { + CAN_SEG2_1TQ = 0x00000001U, + CAN_SEG2_2TQ = 0x00000002U, + CAN_SEG2_3TQ = 0x00000003U, + CAN_SEG2_4TQ = 0x00000004U, + CAN_SEG2_5TQ = 0x00000005U, + CAN_SEG2_6TQ = 0x00000006U, + CAN_SEG2_7TQ = 0x00000007U, + CAN_SEG2_8TQ = 0x00000008U +} CAN_Seg2_Phase; + +/** + * @brief Time quanta of Sync Jump Width. + */ +typedef enum { + CAN_SJW_1TQ = 0x00000001U, + CAN_SJW_2TQ = 0x00000002U, + CAN_SJW_3TQ = 0x00000003U, + CAN_SJW_4TQ = 0x00000004U +} CAN_Sync_Jump_Width; + +/** + * @brief Error status code: the last error status on the CAN bus. + */ +typedef enum { + CAN_WRITE_MASK = 0x00000008U, + CAN_READ_MASK = 0x00000010U, + CAN_EPASS_MASK = 0x00000020U, + CAN_EWARN_MASK = 0x00000040U, + CAN_BOFF_MASK = 0x00000080U, +} CAN_StatusMask; + +/** + * @brief CAN data frame format. + */ +typedef struct { + CAN_TypeFrame type; + unsigned int dataLength; + unsigned int CANId; + unsigned char frame[8]; +} CANFrame; + +/** + * @brief Received frame filtering configuration parameters. + */ +typedef struct { + CAN_FilterFrame receiveType; + unsigned int filterID; + unsigned int filterMask; +} CAN_FilterConfigure; + +/** + * @brief Bit timing parameters. + */ +typedef struct { + unsigned int Tseg2 : 3; + unsigned int Tseg1 : 4; + unsigned int SJW : 2; + unsigned int BRP : 1; +} Bit_Timing; +/** + * @} + */ + +/** + * @defgroup CAN_Reg_Def CAN Register Definition + * @brief CAN register mapping structure. + * @{ + */ + +/** + * @brief CAN control register, Control of basic functions. + */ +typedef union { + unsigned int reg; + struct { + unsigned int Init : 1; /**< Initialization enable. */ + unsigned int IE : 1; /**< Module interrupt enable. */ + unsigned int SIE : 1; /**< Status change interrupt enable. */ + unsigned int EIE : 1; /**< Error interrupt enable. */ + unsigned int reserved0 : 1; + unsigned int DAR : 1; /**< Automatic retransmission enable. */ + unsigned int CCE : 1; /**< Configuration change enable. */ + unsigned int Test : 1; /**< Test mode enable. */ + unsigned int reserved1 : 24; + } BIT; +} volatile CAN_CONTROL_REG; + +/** + * @brief CAN status register register.CAN error count register + */ +typedef union { + unsigned int reg; + struct { + unsigned int LEC : 3; /**< Error status code, used to indicate last error status on CAN bus. */ + unsigned int TxOk : 1; /**< Indicates the packet sending status. */ + unsigned int RxOk : 1; /**< Indicates the packet receiving status. */ + unsigned int Epass : 1; /**< Indicates the error status. */ + unsigned int Ewarn : 1; /**< Warning status. */ + unsigned int Boff : 1; /**< Bus-off status. */ + unsigned int reserved0 : 24; + } BIT; +} volatile CAN_STATUS_REG; + +/** + * @brief CAN error count register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int TEC : 8; /**< Indicates transmission error counter. */ + unsigned int REC : 7; /**< Receive error counter. */ + unsigned int RP : 1; /**< Indicates passive error reception status. */ + unsigned int reserved0 : 16; + } BIT; +} volatile CAN_ERROR_COUNTER_REG; + +/** + * @brief bit time register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int BRP : 6; /**< Baud rate coefficient. */ + unsigned int SJW : 2; /**< Resync jump width. */ + unsigned int TSeg1 : 4; /**< Phase buffer segment 1. */ + unsigned int TSeg2 : 3; /**< Phase buffer segment 2. */ + unsigned int reserved0 : 17; + } BIT; +} volatile BIT_TIMING_REG; + +/** + * @brief CAN interrupt register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int IntId : 16; /**< Interrupt packet object ID. */ + unsigned int reserved0 : 16; + } BIT; +} volatile CAN_INTERRUPT_REG; + +/** + * @brief CAN test register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int : 2; + unsigned int Basic : 1; /**< Basic mode enable. */ + unsigned int Silent : 1; /**< Silent mode enable. */ + unsigned int Lback : 1; /**< Loop back mode enable. */ + unsigned int Tx : 2; /**< CAN_TX pin control. */ + unsigned int Rx : 1; /**< Monitors the CAN_RX pin. */ + unsigned int reserved0 : 24; + } BIT; +} volatile CAN_TEST_REG; + +/** + * @brief Baud rate coefficient extension register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int BRPE : 4; /**< Baud rate coefficient expansion. */ + unsigned int reserved0 : 28; + } BIT; +} volatile BRP_EXTENSION_REG; + +/** + * @brief Request register for IF1 command. + */ +typedef union { + unsigned int reg; + struct { + unsigned int MessageNumber : 6; /**< Message object serial number. */ + unsigned int reserved0 : 9; + unsigned int BUSY : 1; /**< Busy signal. */ + unsigned int reserved1 : 16; + } BIT; +} volatile IF1_COMMAND_REQUEST_REG; + +/** + * @brief IF1 command mask register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DataB : 1; /**< Command mask, which controls the transmission of IF1_DATAB. */ + unsigned int DataA : 1; /**< Command mask, which controls the transmission of IF1_DATAA. */ + unsigned int TxRqstNewDat : 1; /**< Command mask, which controls the TxRqst bit or NewDat bit of + the packet object. */ + unsigned int ClrIntPnd : 1; /**< Command mask, which is used to clear the interrupts of the + packet object to be processed. */ + unsigned int Control : 1; /**< Command mask, which controls the transmission of IF1_MESSAGE_CONTROL. */ + unsigned int Arb : 1; /**< Command mask, which controls the transmission of IF1_ARBITRATION. */ + unsigned int Mask : 1; /**< Command mask, which controls the transmission of IF1_MASK.*/ + unsigned int WRRD : 1; /**< Read/Write command, which controls the transfer direction + of the IF1 packet buffer register and Message RAM. */ + unsigned int reserved0 : 24; + } BIT; +} volatile IF1_COMMAND_MASK_REG; + +/** + * @brief IF1 mask register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int Msk : 16; /**< Mask of the 15th to 0th bits of the packet object ID + which are used for packet receiving and filtering. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF1_MASK1_REG; + +/** + * @brief IF1 mask register 2. + */ +typedef union { + unsigned int reg; + struct { + unsigned int Msk : 13; /**< Mask of the 28th to 16th bits of the packet object ID + which are used to filter received packets. */ + unsigned int reserved0 : 1; + unsigned int MDir : 1; /**< Indicates the direction bit mask of the packet object + which is used for filtering received packets. */ + unsigned int MXtd : 1; /**< Indicates the extended ID (Xtd) mask of the packet object + which is used for filtering received packets. */ + unsigned int reserved1 : 16; + } BIT; +} volatile IF1_MASK2_REG; + +/** + * @brief IF1 arbitration register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ID : 16; /**< Bits 15 to 0 of the packet ID of the packet object. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF1_ARBITRATION1_REG; + +/** + * @brief IF1 arbitration register 2. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ID : 13; /**< Bits 28 to 16 of packet ID of packet object. */ + unsigned int Dir : 1; /**< Indicates direction of the packet object. */ + unsigned int Xtd : 1; /**< Indicates format of received and sent frames of packet object. */ + unsigned int MsgVal : 1; /**< Packet object validity enable. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF1_ARBITRATION2_REG; + +/** + * @brief IF1 packet control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DLC : 4; /**< Data length. */ + unsigned int reserved0 : 3; + unsigned int EoB : 1; /**< Indicates the multi-packet receiving mode. */ + unsigned int TxRqst : 1; /**< Transfer request. */ + unsigned int RmtEn : 1; /**< Remote frame enable. */ + unsigned int RxIE : 1; /**< RX interrupt enable. */ + unsigned int TxIE : 1; /**< TX interrupt enable. */ + unsigned int Umask : 1; /**< Indicates whether the packet object uses the packet mask + which is used for packet receiving and filtering. */ + unsigned int IntPnd : 1; /**< Indicates the interrupt to be processed of the packet object. */ + unsigned int MsgLst : 1; /**< Indicates the packet loss flag of the packet object + parameter is valid only when packet object is in the receive direction. */ + unsigned int NewDat : 1; /**< Write status of the new data of the message object. */ + unsigned int reserved1 : 16; + } BIT; +} volatile IF1_MESSAGE_CONTROL_REG; + +/** + * @brief IF1 data A1 register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DATA0 : 8; /**< CAN frame data byte 0. */ + unsigned int DATA1 : 8; /**< CAN frame data byte 1. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF1_DATAA1_REG; + +/** + * @brief IF1 data A2 register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DATA2 : 8; /**< CAN frame data byte 2. */ + unsigned int DATA3 : 8; /**< CAN frame data byte 3. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF1_DATAA2_REG; + +/** + * @brief IF1 data B1 register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DATA4 : 8; /**< CAN frame data byte 4. */ + unsigned int DATA5 : 8; /**< CAN frame data byte 5. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF1_DATAB1_REG; + +/** + * @brief IF1 data B2 register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DATA6 : 8; /**< CAN frame data byte 6. */ + unsigned int DATA7 : 8; /**< CAN frame data byte 7. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF1_DATAB2_REG; + +/** + * @brief IF2 command request register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int MessageNumber : 6; /**< Indicates the sequence number of a packet object. */ + unsigned int reserved0 : 9; + unsigned int BUSY : 1; /**< Busy sign. */ + unsigned int reserved1 : 16; + } BIT; +} volatile IF2_COMMAND_REQUEST_REG; + +/** + * @brief IF2 command mask register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DataB : 1; /**< Command mask, which controls the transmission of IF2_DATAB. */ + unsigned int DataA : 1; /**< Command mask, which controls the transmission of IF2_DATAA. */ + unsigned int TxRqstNewDat : 1;/**< Command mask, which controls TxRqst bit or NewDat bit of packet object. */ + unsigned int ClrIntPnd : 1; /**< Command mask, which is used to clear interrupts of packet + object to be processed. */ + unsigned int Control : 1; /**< Command mask, which controls the transmission of IF2_MESSAGE_CONTROL. */ + unsigned int Arb : 1; /**< Command mask, which controls the transmission of IF2_ARBITRATION. */ + unsigned int Mask : 1; /**< Command mask, which controls the transmission of IF2_MASK. */ + unsigned int WRRD : 1; /**< Read/Write command, which controls the transfer direction of + the IF2 packet buffer register and Message RAM. */ + unsigned int reserved0 : 24; + } BIT; +} volatile IF2_COMMAND_MASK_REG; + +/** + * @brief IF2 mask register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int Msk : 16; /**< Mask of the 15th to 0th bits of the packet object ID + which are used for packet receiving and filtering. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF2_MASK1_REG; + +/** + * @brief IF2 mask register 2. + */ +typedef union { + unsigned int reg; + struct { + unsigned int Msk : 13; /**< Mask of the 28th to 16th bits of the packet object ID + which are used for packet receiving and filtering. */ + unsigned int reserved0 : 1; + unsigned int MDir : 1; /**< Indicates the direction bit mask of the packet object + which is used for packet receiving and filtering. */ + unsigned int MXtd : 1; /**< Extended ID mask (Xtd) of a packet object + which is used for packet receiving and filtering. */ + unsigned int reserved1 : 16; + } BIT; +} volatile IF2_MASK2_REG; + +/** + * @brief IF2 arbitration register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ID : 16; /**< Bits 15 to 0 of the packet ID of the packet object. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF2_ARBITRATION1_REG; + +/** + * @brief IF2 arbitration register 2. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ID : 13; /**< Bits 28 to 16 of the packet ID of the packet object.*/ + unsigned int Dir : 1; /**< Indicates the direction of the packet object.*/ + unsigned int Xtd : 1; /**< Indicates format of received and sent frames of packet object.*/ + unsigned int MsgVal : 1; /**< Packet object validity enable.*/ + unsigned int reserved0 : 16; + } BIT; +} volatile IF2_ARBITRATION2_REG; + +/** + * @brief IF2 packet control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DLC : 4; /**< Data length */ + unsigned int reserved0 : 3; + unsigned int EoB : 1; /**< Indicates the multi-packet receiving mode. */ + unsigned int TxRqst : 1; /**< Transfer request. */ + unsigned int RmtEn : 1; /**< Remote frame enable. */ + unsigned int RxIE : 1; /**< RX interrupt enable. */ + unsigned int TxIE : 1; /**< TX interrupt enable. */ + unsigned int Umask : 1; /**< Indicates whether the packet object uses the packet mask + which is used for packet receiving and filtering. */ + unsigned int IntPnd : 1; /**< Indicates the interrupt to be processed of the packet object. */ + unsigned int MsgLst : 1; /**< Indicates the packet loss flag of the packet object + This parameter is valid only when packet object is in receive direction. */ + unsigned int NewDat : 1; /**< Indicates the frame data ID of the packet object. */ + unsigned int reserved1 : 16; + } BIT; +} volatile IF2_MESSAGE_CONTROL_REG; + +/** + * @brief IF2 data A1 register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DATA0 : 8; /**< CAN frame data byte 0. */ + unsigned int DATA1 : 8; /**< CAN frame data byte 1. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF2_DATAA1_REG; + +/** + * @brief IF2 data A2 register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DATA2 : 8; /**< CAN frame data byte 2. */ + unsigned int DATA3 : 8; /**< CAN frame data byte 3. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF2_DATAA2_REG; + +/** + * @brief IF2 data B1 register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DATA4 : 8; /**< CAN frame data byte 4. */ + unsigned int DATA5 : 8; /**< CAN frame data byte 5. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF2_DATAB1_REG; + +/** + * @brief IF2 data B2 register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int DATA6 : 8; /**< CAN frame data byte 6. */ + unsigned int DATA7 : 8; /**< CAN frame data byte 7. */ + unsigned int reserved0 : 16; + } BIT; +} volatile IF2_DATAB2_REG; + +/** + * @brief Transfer request status register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int TxRqst16_1 : 16; /**< Transfer request status. + Each bit of TxRqst16-1 corresponds to packet object 16-1. */ + unsigned int reserved0 : 16; + } BIT; +} volatile TRANSMISSION_REQUEST1_REG; + +/** + * @brief Transfer request status register 2. + */ +typedef union { + unsigned int reg; + struct { + unsigned int TxRqst32_17 : 16; /**< Transfer request status. + Each bit of TxRqst32-17 corresponds to packet objects 32-17. */ + unsigned int reserved0 : 16; + } BIT; +} volatile TRANSMISSION_REQUEST2_REG; + +/** + * @brief New data status register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int NewDat16_1 : 16; /**< New data write status. + NewDat16-1 Each bit corresponds to the packet object 16-1. */ + unsigned int reserved0 : 16; + } BIT; +} volatile NEW_DATA1_REG; + +/** + * @brief New data status register 2. + */ +typedef union { + unsigned int reg; + struct { + unsigned int NewDat32_17 : 16; /**< New data write status. + Each bit of NewDat32-17 corresponds to packet objects 32-17. */ + unsigned int reserved0 : 16; + } BIT; +} volatile NEW_DATA2_REG; + +/** + * @brief Interrupt pending status register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int IntPnd16_1 : 16; /**< Interrupt Pending Status. + Each bit of IntPnd16-1 corresponds to packet object 16-1. */ + unsigned int reserved0 : 16; + } BIT; +} volatile INTERRUPT_PENDING1_REG; + +/** + * @brief Interrupt pending status register 2. + */ +typedef union { + unsigned int reg; + struct { + unsigned int IntPnd32_17 : 16; /**< Interrupt Pending Status. + Each bit of IntPnd32-17 corresponds to packet objects 32-17. */ + unsigned int reserved0 : 16; + } BIT; +} volatile INTERRUPT_PENDING2_REG; + +/** + * @brief Packet validity status register 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int MsgVal16_1 : 16; /**< Indicates the validity status of the packet object + Each bit of MsgVal16-1 corresponds to packet object 16-1. */ + unsigned int reserved0 : 16; + } BIT; +} volatile MESSAGE_VALID1_REG; + +/** + * @brief Packet validity status register 2. + */ +typedef union { + unsigned int reg; + struct { + unsigned int MsgVal32_17 : 16; /**< Indicates the validity status of the packet object. + Each bit of MsgVal32-17 corresponds to packet objects 32-17. */ + unsigned int reserved0 : 16; + } BIT; +} volatile MESSAGE_VALID2_REG; + +/** + * @brief Register mapping structure. + */ +typedef struct _CAN_RegStruct { + CAN_CONTROL_REG CAN_CONTROL; /**< CAN control register, Offset address: 0x00000000U. */ + CAN_STATUS_REG CAN_STATUS; /**< CAN status register. Offset address: 0x00000004U.*/ + CAN_ERROR_COUNTER_REG CAN_ERROR_COUNTER; /**< CAN error count register. Offset address: 0x00000008U.*/ + BIT_TIMING_REG BIT_TIMING; /**< Bit time register. Offset address: 0x0000000CU. */ + CAN_INTERRUPT_REG CAN_INTERRUPT; /**< CAN interrupt register. Offset address: 0x00000010U. */ + CAN_TEST_REG CAN_TEST; /**< CAN debug register. Offset address: 0x00000014U. */ + BRP_EXTENSION_REG BRP_EXTENSION; /**< BRP extension register. Offset address: 0x00000018U. */ + char space0[4]; + IF1_COMMAND_REQUEST_REG IF1_COMMAND_REQUEST; /**< IF1 command request register. Offset address: 0x00000020U. */ + IF1_COMMAND_MASK_REG IF1_COMMAND_MASK; /**< IF1 command mask register. Offset address: 0x00000024U. */ + IF1_MASK1_REG IF1_MASK1; /**< IF1 mask register 1. Offset address: 0x00000028U. */ + IF1_MASK2_REG IF1_MASK2; /**< IF1 mask register 2. Offset address: 0x0000002CU. */ + IF1_ARBITRATION1_REG IF1_ARBITRATION1; /**< IF1 arbitration register 1. Offset address: 0x00000030U. */ + IF1_ARBITRATION2_REG IF1_ARBITRATION2; /**< IF1 arbitration register 2. Offset address: 0x00000034U. */ + IF1_MESSAGE_CONTROL_REG IF1_MESSAGE_CONTROL; /**< IF1 packet control register. Offset address: 0x00000038U. */ + IF1_DATAA1_REG IF1_DATAA1; /**< IF1 data A1 register. Offset address: 0x0000003CU. */ + IF1_DATAA2_REG IF1_DATAA2; /**< IF1 data A2 register. Offset address: 0x00000040U. */ + IF1_DATAB1_REG IF1_DATAB1; /**< IF1 data B1 register. Offset address: 0x00000044U. */ + IF1_DATAB2_REG IF1_DATAB2; /**< IF1 data B2 register. Offset address: 0x00000048U. */ + char space1[52]; + IF2_COMMAND_REQUEST_REG IF2_COMMAND_REQUEST; /**< IF2 command request register. Offset address: 0x00000080U. */ + IF2_COMMAND_MASK_REG IF2_COMMAND_MASK; /**< IF2 command mask register. Offset address: 0x00000084U. */ + IF2_MASK1_REG IF2_MASK1; /**< IF2 mask register 1. Offset address: 0x00000088U. */ + IF2_MASK2_REG IF2_MASK2; /**< IF2 mask register 2. Offset address: 0x0000008CU. */ + IF2_ARBITRATION1_REG IF2_ARBITRATION1; /**< IF2 arbitration register 1. Offset address: 0x00000090U. */ + IF2_ARBITRATION2_REG IF2_ARBITRATION2; /**< IF2 arbitration register 2. Offset address: 0x00000094U. */ + IF2_MESSAGE_CONTROL_REG IF2_MESSAGE_CONTROL; /**< IF2 packet control register. Offset address: 0x00000098U.*/ + IF2_DATAA1_REG IF2_DATAA1; /**< IF2 data A1 register. Offset address: 0x0000009CU. */ + IF2_DATAA2_REG IF2_DATAA2; /**< IF2 data A2 register. Offset address: 0x000000A0U. */ + IF2_DATAB1_REG IF2_DATAB1; /**< IF2 data B1 register. Offset address: 0x000000A4U. */ + IF2_DATAB2_REG IF2_DATAB2; /**< IF2 data B2 register. Offset address: 0x000000A8U. */ + char space2[84]; + TRANSMISSION_REQUEST1_REG TRANSMISSION_REQUEST1;/**< Trans_request status reg 1. Offset address: 0x00000100U. */ + TRANSMISSION_REQUEST2_REG TRANSMISSION_REQUEST2;/**< Trans_request status reg 2. Offset address: 0x00000104U. */ + char space3[24]; + NEW_DATA1_REG NEW_DATA1; /**< New data status register 1. Offset address: 0x00000120U. */ + NEW_DATA2_REG NEW_DATA2; /**< New data status register 2. Offset address: 0x00000124U. */ + char space4[24]; + INTERRUPT_PENDING1_REG INTERRUPT_PENDING1; /**< INT pending status reg 1. Offset address: 0x00000140U. */ + INTERRUPT_PENDING2_REG INTERRUPT_PENDING2; /**< INT pending status reg 2. Offset address: 0x00000144U. */ + char space5[24]; + MESSAGE_VALID1_REG MESSAGE_VALID1; /**< Packet validity status reg 1. Offset address: 0x00000160U. */ + MESSAGE_VALID2_REG MESSAGE_VALID2; /**< Packet validity status reg 2. Offset address: 0x00000164U.*/ +} volatile CAN_RegStruct; +/** + * @} + */ + + +/** + * @brief Check CAN typemode parameter. + * @param typemode Work mode, @ref CAN_TypeMode + * @retval bool + */ +static inline bool IsCanMode(CAN_TypeMode typemode) +{ + return (typemode == CAN_MODE_NORMAL) || (typemode == CAN_MODE_TEST); +} + +/** + * @brief Check CAN prescalser parameter. + * @param prescalser Bit timing prescalser. + * @retval bool + */ +static inline bool IsCanPrescalser(unsigned int prescalser) +{ + return prescalser >= PRESCALSER_MIN && prescalser <= PRESCALSER_MAX; +} + +/** + * @brief Check CAN seg1Phase parameter. + * @param seg1Phase Phase buffer section 1, @ref CAN_Seg1_Phase + * @retval bool + */ +static inline bool IsCanSeg1phase(CAN_Seg1_Phase seg1Phase) +{ + return (seg1Phase >= CAN_SEG1_2TQ) && (seg1Phase <= CAN_SEG1_16TQ); +} + +/** + * @brief Check CAN seg2Phase parameter. + * @param seg2Phase Phase buffer section 2, @ref CAN_Seg2_Phase + * @retval bool + */ +static inline bool IsCanSeg2phase(CAN_Seg2_Phase seg2Phase) +{ + return (seg2Phase >= CAN_SEG2_1TQ) && (seg2Phase <= CAN_SEG2_8TQ); +} + +/** + * @brief Check CAN syncJumpWidth parameter. + * @param syncJumpWidth Sync jump width, @ref CAN_Sync_Jump_Width + * @retval bool + */ +static inline bool IsCanSJW(CAN_Sync_Jump_Width syncJumpWidth) +{ + return (syncJumpWidth >= CAN_SJW_1TQ) && (syncJumpWidth <= CAN_SJW_4TQ); +} + +/* Direct configuration layer */ +/** + * @brief CAN bit timing setting. + * @param canx CAN register base address. + * @param bitSetting CAN bit timing parameter, @ref Bit_Timing + * @retval None. + */ +static inline void DCL_CAN_BitSetting(CAN_RegStruct * const canx, Bit_Timing bitSetting) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + CAN_PARAM_CHECK_NO_RET(bitSetting.Tseg1 > 0); + canx->CAN_CONTROL.reg |= 0x00000041U; /* Bit_Timing setting, [0] and [6] bit need are set, others clear */ + unsigned int val = bitSetting.BRP; /* The prescalser is set to the lower 6 bits, [5:0] */ + val |= (bitSetting.SJW) << 6; /* The sjw needs to be shifted leftwards by 6 bits, range : 0~3 */ + val |= (bitSetting.Tseg1) << 8; /* The seg1Phase needs to be shifted leftwards by 8 bits, range : 1~15 */ + val |= (bitSetting.Tseg2) << 12; /* The seg2Phase needs to be shifted leftwards by 12 bits, range : 0~63 */ + canx->BIT_TIMING.reg = val; +} + +/** + * @brief CAN interrupt enable. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_EnableInterrupt(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.IE = BASE_CFG_ENABLE; +} + +/** + * @brief CAN interrupt disable. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_DisableInterrupt(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.IE = BASE_CFG_DISABLE; +} + +/** + * @brief CAN status interrupt enable. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_EnableStatusInterrupt(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.SIE = BASE_CFG_ENABLE; +} + +/** + * @brief CAN status interrupt disable. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_DisableStatusInterrupt(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.SIE = BASE_CFG_DISABLE; +} + +/** + * @brief CAN error interrupt enable. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_EnableErrorInterrupt(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.EIE = BASE_CFG_ENABLE; +} + +/** + * @brief CAN error interrupt disable. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_DisableErrorInterrupt(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.EIE = BASE_CFG_DISABLE; +} + +/** + * @brief Enable Automatic Retransmission + * @param canx CAN register base address. + * @retval None + */ +static inline void DCL_CAN_EnableAutoRetrans(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.DAR = BASE_CFG_DISABLE; +} + +/** + * @brief Disable Automatic Retransmission + * @param canx CAN register base address. + * @retval None + */ +static inline void DCL_CAN_DisableAutoRetrans(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.DAR = BASE_CFG_ENABLE; +} + +/** + * @brief Enable CAN test mode + * @param canx CAN register base address. + * @retval None + */ +static inline void DCL_CAN_EnableTestMode(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.Test = BASE_CFG_ENABLE; +} + +/** + * @brief Disable CAN test mode + * @param canx CAN register base address. + * @retval None + */ +static inline void DCL_CAN_DisableTestMode(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.Test = BASE_CFG_DISABLE; +} + +/** + * @brief Enable CAN bit timing config + * @param canx CAN register base address. + * @retval None + */ +static inline void DCL_CAN_EnableBitTimingConfig(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.CCE = BASE_CFG_ENABLE; +} + +/** + * @brief Disable CAN bit timing config + * @param canx CAN register base address. + * @retval None + */ +static inline void DCL_CAN_DisableBitTimingConfig(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.CCE = BASE_CFG_DISABLE; +} + +/** + * @brief Enable CAN Init. + * @param canx CAN register base address. + * @retval None + */ +static inline void DCL_CAN_EnableInit(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.Init = BASE_CFG_ENABLE; +} + +/** + * @brief Disable CAN init. + * @param canx CAN register base address. + * @retval None + */ +static inline void DCL_CAN_DisableInit(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_CONTROL.BIT.Init = BASE_CFG_DISABLE; +} + +/** + * @brief Initializes a specified packet object. + * @param canx CAN register base address. + * @param objID ID of message object. + * @retval None. + */ +static inline void DCL_CAN_InitObj(CAN_RegStruct * const canx, unsigned int objID) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + CAN_PARAM_CHECK_NO_RET((objID >= MESSAGE_NUMBER_MIN) && (objID <= MESSAGE_NUMBER_MAX)); + unsigned int busy; + canx->IF1_COMMAND_REQUEST.reg = objID; + do { + busy = canx->IF1_COMMAND_REQUEST.BIT.BUSY; + } while (busy == 0x00000001U); + return; +} + +/** + * @brief Get IF1 CAN status + * @param canx CAN register base address. + * @retval bool: 0 command is being executed, 1 command has been completed. + */ +static inline bool DCL_CAN_GetIF1Status(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_COMMAND_REQUEST.BIT.BUSY; +} + +/** + * @brief Setting IF1 message number + * @param canx CAN register base address. + * @param objID message number + * @retval None + */ +static inline void DCL_CAN_SetIF1MessageNumber(CAN_RegStruct * const canx, unsigned int objID) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + CAN_PARAM_CHECK_NO_RET((objID >= MESSAGE_NUMBER_MIN) && (objID <= MESSAGE_NUMBER_MAX)); + canx->IF1_COMMAND_REQUEST.BIT.MessageNumber = objID; +} + +/** + * @brief Query the CAN interrupt generation source. + * @param canx CAN register base address. + * @retval IDs of the packet objects for which the interrupt is generated. + */ +static inline unsigned int DCL_CAN_GetInterruptID(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->CAN_INTERRUPT.reg; +} + +/** + * @brief Confrguration command mask + * @param canx CAN register base address. + * @param maskValue Mask value for command register. + * @retval None + */ +static inline void DCL_CAN_ConfigMaskValue(CAN_RegStruct * const canx, unsigned int maskValue) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_COMMAND_MASK.reg = maskValue; +} + +/** + * @brief Get IF2 CAN status. + * @param canx CAN register base address. + * @retval bool: 0 command is being executed, 1 command has been completed. + */ +static inline bool DCL_CAN_GetIF2Status(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_COMMAND_REQUEST.BIT.BUSY; +} + +/** + * @brief Setting IF2 message number. + * @param canx CAN register base address. + * @param objID message number. + * @retval None + */ +static inline void DCL_CAN_SetIF2MessageNumber(CAN_RegStruct * const canx, unsigned int objID) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + CAN_PARAM_CHECK_NO_RET((objID >= MESSAGE_NUMBER_MIN) && (objID <= MESSAGE_NUMBER_MAX)); + canx->IF2_COMMAND_REQUEST.BIT.MessageNumber = objID; +} + +/** + * @brief Enable CAN loop back mode. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_EnableLoopBack(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_TEST.BIT.Lback = BASE_CFG_ENABLE; +} + +/** + * @brief Disable CAN loop back mode. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_DisableLoopBack(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_TEST.BIT.Lback = BASE_CFG_DISABLE; +} + +/** + * @brief Enable CAN silent mode. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_EnableSilent(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_TEST.BIT.Silent = BASE_CFG_ENABLE; +} + +/** + * @brief Disable CAN silent mode. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_DisableSilent(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_TEST.BIT.Silent = BASE_CFG_DISABLE; +} + +/** + * @brief Enable CAN basic mode. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_EnableBasic(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_TEST.BIT.Basic = BASE_CFG_ENABLE; +} + +/** + * @brief Disable CAN basic mode. + * @param canx CAN register base address. + * @retval None. + */ +static inline void DCL_CAN_DisableBasic(CAN_RegStruct * const canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->CAN_TEST.BIT.Basic = BASE_CFG_DISABLE; +} + +/** + * @brief Config IF1_ARBITRATION1. + * @param canx CAN register base address. + * @param maskValue Mask value for arbitration 1 register. + * @retval None. + */ +static inline void DCL_CAN_ConfigIF1ARBITRATION1(CAN_RegStruct * const canx, unsigned int maskValue) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_ARBITRATION1.reg = maskValue; +} + +/** + * @brief Low bit(0-15) obj ID number using IF1. + * @param canx CAN register base address. + * @retval unsigned int: Low bit ID number. + */ +static inline unsigned int DCL_CAN_GetIF1LoWBitObjNumber(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_ARBITRATION1.BIT.ID; +} + +/** + * @brief Config IF1_ARBITRATION2. + * @param canx CAN register base address. + * @param maskValue Mask value for arbitration 2 register. + * @retval None. + */ +static inline void DCL_CAN_ConfigIF1ARBITRATION2(CAN_RegStruct * const canx, unsigned int maskValue) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_ARBITRATION2.reg = maskValue; +} + +/** + * @brief Config IF2_ARBITRATION1. + * @param canx CAN register base address. + * @param maskValue Mask value for arbitration 1 register. + * @retval None. + */ +static inline void DCL_CAN_ConfigIF2ARBITRATION1(CAN_RegStruct * const canx, unsigned int maskValue) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_ARBITRATION1.reg = maskValue; +} + +/** + * @brief Low bit(0-15) obj ID number using IF2. + * @param canx CAN register base address. + * @retval unsigned int: Low bit ID number. + */ +static inline unsigned int DCL_CAN_GetIF2LoWBitObjNumber(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_ARBITRATION1.BIT.ID; +} + +/** + * @brief Config IF2_ARBITRATION2. + * @param canx CAN register base address. + * @param maskValue Mask value for arbitration 2 register. + * @retval None + */ +static inline void DCL_CAN_ConfigIF2ARBITRATION2(CAN_RegStruct * const canx, unsigned int maskValue) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_ARBITRATION2.reg = maskValue; +} + +/** + * @brief Get objection format of transmitted and received frame of IF2. + * @param canx CAN register base address. + * @retval bool: 0: Message object receives and transmits frames in standard format. + * @retval 1: Message object receives and transmits frames in extended format. + */ +static inline bool DCL_CAN_GetIF2ObjFormat(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_ARBITRATION2.BIT.Xtd; +} + +/** + * @brief Get objection format of transmitted and received frame of IF1. + * @param canx CAN register base address. + * @retval bool: 0: Message object receives and transmits frames in standard format. + * @retval 1: Message object receives and transmits frames in extended format. + */ +static inline bool DCL_CAN_GetIF1ObjFormat(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_ARBITRATION2.BIT.Xtd; +} + +/** + * @brief Get direction of transmitted and received frame of IF1. + * @param canx CAN register base address. + * @retval bool: 0: Message object is received in receive direction. + * @retval 1: Message object is in transmit direction. + */ +static inline bool DCL_CAN_GetIF1ObjDirection(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_ARBITRATION2.BIT.Dir; +} + +/** + * @brief Get the status of whether objection is valid using IF1. + * @param canx CAN register base address. + * @retval bool: 1 message object valid, 0 message object invalid. + */ +static inline bool DCL_CAN_GetIF1ObjStatus(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_ARBITRATION2.BIT.MsgVal; +} + +/** + * @brief high bit(16-28) obj ID number using IF1. + * @param canx CAN register base address. + * @retval unsigned int: high bit ID number. + */ +static inline unsigned int DCL_CAN_GetIF1HighBitObjNumber(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_ARBITRATION2.BIT.ID; +} + +/** + * @brief Get direction of transmitted and received frame of IF2. + * @param canx CAN register base address. + * @retval bool: 0: Message object is received in receive direction. + * @retval 1: Message object is in transmit direction. + */ +static inline bool DCL_CAN_GetIF2ObjDirection(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_ARBITRATION2.BIT.Dir; +} + +/** + * @brief Get the status of whether objection is valid using IF2. + * @param canx CAN register base address. + * @retval bool: 1: message object valid. + * @retval 0: message object invalid. + */ +static inline bool DCL_CAN_GetIF2ObjStatus(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_ARBITRATION2.BIT.MsgVal; +} + +/** + * @brief high bit(16-28) obj ID number using IF2 + * @param canx CAN register base address. + * @retval unsigned int: high bit ID number + */ +static inline unsigned int DCL_CAN_GetIF2HighBitObjNumber(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_ARBITRATION2.BIT.ID; +} + +/** + * @brief Get obj data length using IF2. + * @param canx CAN register base address. + * @retval unsigned int: data length + */ +static inline unsigned int DCL_CAN_GetIF2ObjDataLength(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_MESSAGE_CONTROL.BIT.DLC; +} + +/** + * @brief config message control using IF2 + * @param canx CAN register base address. + * @param messageControlValue Message control command value. + * @retval None + */ +static inline void DCL_CAN_ConfigIF2MessageControl(CAN_RegStruct * const canx, unsigned int messageControlValue) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_MESSAGE_CONTROL.reg = messageControlValue; +} + +/** + * @brief Get obj data length using IF1 + * @param canx CAN register base address. + * @retval unsigned int: message object data length + */ +static inline unsigned int DCL_CAN_GetIF1ObjDataLength(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_MESSAGE_CONTROL.BIT.DLC; +} + +/** + * @brief config message control using IF1 + * @param canx CAN register base address. + * @param messageControlValue Message control command value. + * @retval None + */ +static inline void DCL_CAN_ConfigIF1MessageControl(CAN_RegStruct * const canx, unsigned int messageControlValue) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_MESSAGE_CONTROL.reg = messageControlValue; +} + +/** + * @brief Get A1 data using IF2 + * @param canx CAN register base address. + * @retval byte 1 and byte 2 of data + */ +static inline unsigned int DCL_CAN_GetIF2ObjDataA1(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_DATAA1.reg; +} + +/** + * @brief Set A1 data using IF2 + * @param canx CAN register base address. + * @param dataA1 Data of A1. + * @retval None. + */ +static inline void DCL_CAN_SetIF2ObjDataA1(CAN_RegStruct * const canx, unsigned int dataA1) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_DATAA1.reg = dataA1; +} + +/** + * @brief Get A2 data using IF2 + * @param canx CAN register base address. + * @retval byte 3 and byte 4 of data + */ +static inline unsigned int DCL_CAN_GetIF2ObjDataA2(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_DATAA2.reg; +} + +/** + * @brief Set A2 data using IF2 + * @param canx CAN register base address. + * @param dataA2 Data of A2. + * @retval None. + */ +static inline void DCL_CAN_SetIF2ObjDataA2(CAN_RegStruct * const canx, unsigned int dataA2) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_DATAA2.reg = dataA2; +} + +/** + * @brief Get B1 data using IF2 + * @param canx CAN register base address. + * @retval byte 5 and byte 6 of data + */ +static inline unsigned int DCL_CAN_GetIF2ObjDataB1(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_DATAB1.reg; +} + +/** + * @brief Set B1 data using IF2, set byte 5 and byte 6 of data. + * @param canx CAN register base address. + * @param dataB1 Data of B1. + * @retval None. + */ +static inline void DCL_CAN_SetIF2ObjDataB1(CAN_RegStruct * const canx, unsigned int dataB1) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_DATAB1.reg = dataB1; +} + +/** + * @brief Get B2 data using IF2 + * @param canx CAN register base address. + * @retval byte 7 and byte 8 of data + */ +static inline unsigned int DCL_CAN_GetIF2ObjDataB2(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF2_DATAB2.reg; +} + +/** + * @brief Set B2 data using IF2, set byte 7 and byte 8 of data + * @param canx CAN register base address. + * @param dataB2 Data of B2. + * @retval None. + */ +static inline void DCL_CAN_SetIF2ObjDataB2(CAN_RegStruct * const canx, unsigned int dataB2) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_DATAB2.reg = dataB2; +} + +/** + * @brief Get A1 data using IF1. + * @param canx CAN register base address. + * @retval byte 1 and byte 2 of data. + */ +static inline unsigned int DCL_CAN_GetIF1ObjDataA1(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_DATAA1.reg; +} + +/** + * @brief Set A1 data using IF1, Set byte 1 and byte 2 of data + * @param canx CAN register base address. + * @param dataA1 Data of A1. + * @retval None. + */ +static inline void DCL_CAN_SetIF1ObjDataA1(CAN_RegStruct * const canx, unsigned int dataA1) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_DATAA1.reg = dataA1; +} + +/** + * @brief Get A2 data using IF1 + * @param canx CAN register base address. + * @retval byte 3 and byte 4 of data + */ +static inline unsigned int DCL_CAN_GetIF1ObjDataA2(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_DATAA2.reg; +} + +/** + * @brief Set A2 data using IF1, Set byte 3 and byte 4 of data + * @param canx CAN register base address. + * @param dataA2 Data of A2. + * @retval None. + */ +static inline void DCL_CAN_SetIF1ObjDataA2(CAN_RegStruct * const canx, unsigned int dataA2) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_DATAA2.reg = dataA2; +} + +/** + * @brief Get B1 data using IF1 + * @param canx CAN register base address. + * @retval byte 5 and byte 6 of data + */ +static inline unsigned int DCL_CAN_GetIF1ObjDataB1(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_DATAB1.reg; +} + +/** + * @brief Set B1 data using IF1, Set byte 5 and byte 6 of data + * @param canx CAN register base address. + * @param dataB1 Data of B1. + * @retval None. + */ +static inline void DCL_CAN_SetIF1ObjDataB1(CAN_RegStruct * const canx, unsigned int dataB1) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_DATAB1.reg = dataB1; +} + +/** + * @brief Get B2 data using IF1 + * @param canx CAN register base address. + * @retval byte 7 and byte 8 of data + */ +static inline unsigned int DCL_CAN_GetIF1ObjDataB2(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->IF1_DATAB2.reg; +} + +/** + * @brief Set B2 data using IF1, Set byte 7 and byte 8 of data + * @param canx CAN register base address. + * @param dataB2 Data of B2. + * @retval None. + */ +static inline void DCL_CAN_SetIF1ObjDataB2(CAN_RegStruct * const canx, unsigned int dataB2) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_DATAB2.reg = dataB2; +} + +/** + * @brief Set IF2 mask + * @param canx CAN register base address. + * @param mask Mask value + * @retval None + */ +static inline void DCL_CAN_SetIF2Mask(CAN_RegStruct * const canx, unsigned int mask) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_MASK2.reg = mask; +} + +/** + * @brief Set objection mask using IF2 + * @param canx CAN register base address. + * @param maskChg Mask value. + * @retval None + */ +static inline void DCL_CAN_SetIF2ObjFilterMask(CAN_RegStruct * const canx, unsigned int maskChg) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_MASK1.reg = maskChg; +} + +/** + * @brief Set IF1 mask + * @param canx CAN register base address. + * @param mask Mask value. + * @retval None + */ +static inline void DCL_CAN_SetIF1Mask(CAN_RegStruct * const canx, unsigned int mask) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_MASK2.reg = mask; +} + +/** + * @brief Set objection mask using IF1 + * @param canx CAN register base address. + * @param maskChg Mask value. + * @retval None + */ +static inline void DCL_CAN_SetIF1ObjFilterMask(CAN_RegStruct * const canx, unsigned int maskChg) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF1_MASK1.reg = maskChg; +} + +/** + * @brief Set command mask using IF2.return + * @param canx CAN register base address. + * @param commandMask command mask value. + * @retval None + */ +static inline void DCL_CAN_SetIF2CommandMask(CAN_RegStruct * const canx, unsigned int commandMask) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + canx->IF2_COMMAND_MASK.reg = commandMask; +} + +/** + * @brief Get Can Status + * @param canx CAN register base address. + * @retval Overall status of the CAN. + */ +static inline unsigned int DCL_CAN_GetStatus(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->CAN_STATUS.reg; +} + +/** + * @brief Get object interrupt ID. + * @param canx CAN register base address. + * @retval Interrupt status of obj 1 to 16 + */ +static inline unsigned int DCL_CAN_GetInterruptPend1(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->INTERRUPT_PENDING1.reg; +} + +/** + * @brief Get objects interrupt ID. + * @param canx CAN register base address. + * @retval Interrupt status of obj 17 to 32 + */ +static inline unsigned int DCL_CAN_GetInterruptPend2(const CAN_RegStruct *canx) +{ + CAN_ASSERT_PARAM(IsCANInstance(canx)); + return canx->INTERRUPT_PENDING2.reg; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_CAN_IP_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/can/src/can.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/can/src/can.c new file mode 100644 index 00000000..13a403ce --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/can/src/can.c @@ -0,0 +1,663 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file can.c + * @author MCU Driver Team + * @brief CAN module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the CAN. + * + Initialization and de-initialization functions + * + Sending and receiving CAN data frames functions + * + Interrupt handling function and user registration callback function + * + CAN data frame filtering function + */ + +/* Includes ------------------------------------------------------------------*/ +#include "can.h" +#include "interrupt.h" + +/* Macro definitions ---------------------------------------------------------*/ + +#define BOUND_ID 24 /* ObjID 1 ~ 24 used for receive, 25 ~ 32 used for send */ +#define CAN_OBJ_MAXNUM 32 + +#define CAN_EFF_FLAG 0x80000000 /* EFF/SFF is set in the MSB */ +#define CAN_RTR_FLAG 0x40000000 /* Remote transmission request */ +#define CAN_ERR_FLAG 0x20000000 /* Error message frame */ + +/* Valid bits in CAN ID for frame formats */ +#define CAN_STD_MASK 0x000007FF /* Standard frame format (SFF) */ +#define CAN_EXT_MASK 0x1FFFFFFF /* Extended frame format (EFF) */ +#define CAN_ERR_MASK 0x1FFFFFFF /* Omit EFF, RTR, ERR flags */ +#define CAN_TIME_WAIT 11 /* CAN initialization wait time */ + +static unsigned int g_stdRecvMap = 0x00000FFF; +static unsigned int g_extRecvMap = 0x00FFF000; +static unsigned int g_allSendMap = 0xFF000000; +static unsigned int g_allRecvMap = 0x00FFFFFF; + +static unsigned int g_msgObj[CAN_OBJ_MAXNUM] = {0}; + +static BASE_StatusType CAN_ReadCallback(CAN_Handle *canHandle, unsigned int objId); +static BASE_StatusType CAN_ConfigReadReq(CAN_Handle *canHandle, unsigned int objId); +static BASE_StatusType WriteFinishClear(CAN_Handle *canHandle, unsigned int objId); +static void CAN_ReceiveFilter(CAN_Handle *canHandle, const CAN_FilterConfigure *filterConfigure, unsigned int objId); +static void CAN_WaitTime(CAN_Handle *canHandle); +static void CAN_AutoRetrans(CAN_Handle *canHandle); + +/* Initialization and de-initialization functions ----------------------------*/ +/** + * @brief Wait 11 CAN bit time. + * @param canHandle CAN handle. + * @retval void + */ +static void CAN_WaitTime(CAN_Handle *canHandle) +{ + /* CAN clock frequency */ + unsigned int canFrep = HAL_CRG_GetIpFreq((void *)canHandle->baseAddress) / (canHandle->prescalser); + unsigned int waitTime = canFrep / (1 + canHandle->seg1Phase + canHandle->seg2Phase); + /* 1000000 equals 1 us to wait for 11 time bits */ + unsigned int waitTimeCount = CAN_TIME_WAIT * ((1000000) / waitTime); + BASE_FUNC_DelayUs(waitTimeCount); +} + +/** + * @brief CAN Setting Automatic Retransmission. + * @param canHandle CAN handle. + * @retval void + */ +static void CAN_AutoRetrans(CAN_Handle *canHandle) +{ + if (canHandle->autoRetrans == BASE_CFG_DISABLE) { + /* Turn off auto retransmission */ + canHandle->baseAddress->CAN_CONTROL.BIT.DAR = BASE_CFG_ENABLE; + } else { + /* Turn on auto retransmission */ + canHandle->baseAddress->CAN_CONTROL.BIT.DAR = BASE_CFG_DISABLE; + } +} + +/** + * @brief Initialize the CAN hardware configuration and configure parameters based on the specified handle. + * @param canHandle CAN handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT + */ +BASE_StatusType HAL_CAN_Init(CAN_Handle *canHandle) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + CAN_PARAM_CHECK_WITH_RET(IsCanMode(canHandle->typeMode), BASE_STATUS_ERROR); /* Check initialization parameters */ + CAN_PARAM_CHECK_WITH_RET(IsCanPrescalser(canHandle->prescalser), BASE_STATUS_ERROR); + CAN_PARAM_CHECK_WITH_RET(IsCanSeg1phase(canHandle->seg1Phase), BASE_STATUS_ERROR); + CAN_PARAM_CHECK_WITH_RET(IsCanSeg2phase(canHandle->seg2Phase), BASE_STATUS_ERROR); + CAN_PARAM_CHECK_WITH_RET(IsCanSJW(canHandle->sjw), BASE_STATUS_ERROR); + unsigned int busy; + /* Step1: init enable */ + canHandle->baseAddress->CAN_CONTROL.BIT.Init = BASE_CFG_ENABLE; + /* Step2: configuration command mask register, set 0xF3 to write into packet objects */ + canHandle->baseAddress->IF1_COMMAND_MASK.reg = 0xF3; + /* Step3 ~ 4: init packet object 1 ~ 32 */ + for (int i = 1; i <= CAN_OBJ_MAXNUM; i++) { + canHandle->baseAddress->IF1_COMMAND_REQUEST.reg = i; + do { + busy = canHandle->baseAddress->IF1_COMMAND_REQUEST.BIT.BUSY; + } while (busy == BASE_CFG_ENABLE); + } + /* Step5: Bit_Timing setting enable, [0]bit and [6]bit need are set, others clear */ + canHandle->baseAddress->CAN_CONTROL.reg = 0x41; + /* Step6: Bit_Timing configuration */ + unsigned int val = canHandle->prescalser - 1; /* The prescalser is set to the lower 6 bits, [5:0] */ + val |= (canHandle->sjw - 1) << 6; /* The sjw needs to be shifted leftwards by 6 bits, [7:6] */ + val |= (canHandle->seg1Phase - 1) << 8; /* The seg1Phase needs to be shifted leftwards by 8 bits, [11:8] */ + val |= (canHandle->seg2Phase - 1) << 12; /* The seg2Phase needs to be shifted leftwards by 12 bits, [14:12] */ + canHandle->baseAddress->BIT_TIMING.reg = val; + /* Step7: setting interrupt configuration, error interrupt and module interrupt */ + canHandle->baseAddress->CAN_CONTROL.reg = 0x0B; + /* Step8: setting automatic retransmission */ + CAN_AutoRetrans(canHandle); + /* Step9: finish init */ + if (canHandle->typeMode == CAN_MODE_TEST && canHandle->testModeConfigure != NULL) { + canHandle->baseAddress->CAN_CONTROL.BIT.Test = BASE_CFG_ENABLE; + canHandle->baseAddress->CAN_TEST.BIT.Lback = canHandle->testModeConfigure->loopBack; + canHandle->baseAddress->CAN_TEST.BIT.Silent = canHandle->testModeConfigure->silent; + canHandle->baseAddress->CAN_TEST.BIT.Basic = canHandle->testModeConfigure->basic; + } + canHandle->baseAddress->CAN_CONTROL.BIT.Init = BASE_CFG_DISABLE; + /* Each packet object configuration before read CAN frame */ + for (int i = 1; i <= CAN_OBJ_MAXNUM; i++) { + if (i <= BOUND_ID) { + CAN_ConfigReadReq(canHandle, i); /* The default configuration is no filter receive */ + } + g_msgObj[i - 1] = 0; + } + CAN_WaitTime(canHandle); + canHandle->state = CAN_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief DeInitialize the CAN and restoring default parameters based on the specified handle. + * @param canHandle CAN handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT + */ +BASE_StatusType HAL_CAN_DeInit(CAN_Handle *canHandle) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + canHandle->baseAddress->CAN_CONTROL.reg = BASE_CFG_DISABLE; /* Disables the control register. */ + canHandle->baseAddress->CAN_STATUS.reg = BASE_CFG_DISABLE; /* Clear the status of the CAN. */ + canHandle->userCallBack.ReadFinishCallBack = NULL; /* Clear all user call back function. */ + canHandle->userCallBack.TransmitErrorCallBack = NULL; + canHandle->userCallBack.WriteFinishCallBack = NULL; + canHandle->state = CAN_STATE_NONE_INIT; /* Set the CAN to the uninitialized state. */ + return BASE_STATUS_OK; +} + +/** + * @brief CAN error status. + * @param canHandle CAN handle. + * @retval CAN_ErrorStatus: + * CAN_PASSIVE_ERROR: CAN is in passive error. + * CAN_ACTIVE_ERROR: CAN is in active error. + */ +CAN_ErrorStatus HAL_CAN_GetErrorStatus(CAN_Handle *canHandle) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + CAN_STATUS_REG canStatus; + /* CAN error status reg. */ + canStatus.reg = canHandle->baseAddress->CAN_STATUS.reg; + if (canStatus.BIT.Epass == BASE_CFG_ENABLE) { + return CAN_PASSIVE_ERROR; /* Passive error */ + } + return CAN_ACTIVE_ERROR; /* active error */ +} + +/** + * @brief Return the specified CAN error status code. + * @param canHandle CAN handle. + * @retval CAN bus error status. @ref CAN_ERROR_StatusCode + * @note CAN_ERROR_NONE -- No error normal. + * CAN_ERROR_PADDING -- Filling error. + * CAN_ERROR_FORMAL -- The format is incorrect. + * CAN_ERROR_ANSWER -- response error. + * CAN_ERROR_BIT1 -- Bit 1 error. + * CAN_ERROR_BIT0 -- bit 0 error. + * CAN_ERROR_CRC -- CRC error. + */ +unsigned int HAL_CAN_GetErrorStatusCode(CAN_Handle *canHandle) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + CAN_STATUS_REG canStatus; + canStatus.reg = canHandle->baseAddress->CAN_STATUS.reg; /* Obtains the full status of the CAN. */ + unsigned int errorStatus = canStatus.BIT.LEC; + return errorStatus; +} + +/** + * @brief CAN Bus-off status. + * @param canHandle CAN handle. + * @retval CAN Bus off status: + * CAN_BUSOFF_ON: In bus-off state. + * CAN_BUSOFF_OFF: Not in the bus-off state. + */ +CAN_BusOffStatus HAL_CAN_GetBusOffStatus(CAN_Handle *canHandle) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + CAN_STATUS_REG canStatus; /* CAN status reg. */ + canStatus.reg = canHandle->baseAddress->CAN_STATUS.reg; /* Obtains all status of the CAN. */ + if (canStatus.BIT.Boff == BASE_CFG_ENABLE) { + return CAN_BUSOFF_ON; + } + return CAN_BUSOFF_OFF; +} + +/** + * @brief CAN message receive status. + * @param canHandle CAN handle. + * @retval CAN message receive status: + * CAN_MESSAGE_RECEIVE_OK: message receive successful. + * CAN_MESSAGE_RECEIVE_ERROR: message receive failed. + */ +CAN_MessageReceiveStatus HAL_CAN_MessageReceiveStatus(CAN_Handle *canHandle) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + CAN_STATUS_REG canStatus; + /* Obtains the CAN RX status. */ + canStatus.reg = canHandle->baseAddress->CAN_STATUS.reg; + if (canStatus.BIT.RxOk == BASE_CFG_ENABLE) { + return CAN_MESSAGE_RECEIVE_OK; /* CAN receive succeeded. */ + } + return CAN_MESSAGE_RECEIVE_ERROR; +} + +/** + * @brief CAN message send status. + * @param canHandle CAN handle. + * @retval CAN message send status: + * CAN_MESSAGE_SEND_OK: message send successful. + * CAN_MESSAGE_SEND_ERROR: message send failed. + */ +CAN_MessageSendStatus HAL_CAN_MessageSendStatus(CAN_Handle *canHandle) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + CAN_STATUS_REG canStatus; + /* Obtains the CAN RX status. */ + canStatus.reg = canHandle->baseAddress->CAN_STATUS.reg; + if (canStatus.BIT.TxOk == BASE_CFG_ENABLE) { + return CAN_MESSAGE_SEND_OK; /* CAN send succeeded. */ + } + return CAN_MESSAGE_SEND_ERROR; +} + +/** + * @brief Padding can data frame 8-bit data. + * @param canHandle CAN handle. + * @param data Pointer address of the CAN data frame to be sent, @ref CANFrame + * @retval None. + */ +static void WriteData(CAN_Handle *canHandle, CANFrame *data) +{ + IF1_DATAA1_REG dataA1; + dataA1.BIT.DATA0 = data->frame[0]; /* Data of bit 0 */ + dataA1.BIT.DATA1 = data->frame[1]; /* Data of bit 0 */ + canHandle->baseAddress->IF1_DATAA1 = dataA1; + IF1_DATAA2_REG dataA2; + dataA2.BIT.DATA2 = data->frame[2]; /* Data of bit 2 */ + dataA2.BIT.DATA3 = data->frame[3]; /* Data of bit 3 */ + canHandle->baseAddress->IF1_DATAA2 = dataA2; + IF1_DATAB1_REG dataB1; + dataB1.BIT.DATA4 = data->frame[4]; /* Data of bit 4 */ + dataB1.BIT.DATA5 = data->frame[5]; /* Data of bit 5 */ + canHandle->baseAddress->IF1_DATAB1 = dataB1; + IF1_DATAB2_REG dataB2; + dataB2.BIT.DATA6 = data->frame[6]; /* Data of bit 6 */ + dataB2.BIT.DATA7 = data->frame[7]; /* Data of bit 7 */ + canHandle->baseAddress->IF1_DATAB2 = dataB2; +} + +/** + * @brief Send data immediately. + * @param canHandle CAN handle. + * @param data Pointer address of the CAN data frame to be sent, @ref CANFrame + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT + * @note: + * IF1 and IF2 have the same functions. To facilitate management, + * IF1 is used for sending and IF2 is used for receiving. + */ +BASE_StatusType HAL_CAN_Write(CAN_Handle *canHandle, CANFrame *data) +{ + CAN_ASSERT_PARAM(canHandle != NULL && data != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + CAN_PARAM_CHECK_WITH_RET(data->dataLength <= 8, BASE_STATUS_ERROR); /* CAN frame length: 1 ~ 8 */ + if (canHandle->state != CAN_STATE_READY) { + return BASE_STATUS_BUSY; + } + canHandle->state = CAN_STATE_BUSY_TX; + unsigned int objId = 0; + unsigned int id; + for (int i = BOUND_ID + 1; i <= CAN_OBJ_MAXNUM; i++) { + if (g_msgObj[i - 1] == 0) { + g_msgObj[i - 1] = 1; + objId = i; + break; + } + } + if (objId == 0) { + return BASE_STATUS_ERROR; + } + /* Step1: write id into register arbitration according frame type */ + switch (data->type) { + case CAN_TYPEFRAME_STD_DATA: /* Standard data frame */ + id = (data->CANId & CAN_STD_MASK) << 2; /* Bit[12:2] = CANId */ + id |= 0xA000; /* [15:13] = 0x05 */ + canHandle->baseAddress->IF1_ARBITRATION1.reg = 0x00; + break; + case CAN_TYPEFRAME_EXT_DATA: /* Extended data frame */ + id = (data->CANId & CAN_EXT_MASK) >> 16; /* Bit[12:0] = CANId(28bit~16bit) */ + id |= 0xE000; /* [15:13] = 0x07 */ + canHandle->baseAddress->IF1_ARBITRATION1.reg = (data->CANId & 0xFFFF); /* write lower 16bits CANId */ + break; + case CAN_TYPEFRAME_STD_REMOTE: /* Standard remote frame */ + id = (data->CANId & CAN_EXT_MASK) << 2; /* Bit[12:2] = CANId */ + id |= 0x8000; /* [15:13] = 0x04 */ + canHandle->baseAddress->IF1_ARBITRATION1.reg = 0x00; + break; + case CAN_TYPEFRAME_EXT_REMOTE: /* Extended remote frame */ + id = (data->CANId & CAN_EXT_MASK) >> 16; /* Bit[12:0] = CANId(28bit~16bit) */ + id |= 0xC000; /* [15:13] = 0x06 */ + canHandle->baseAddress->IF1_ARBITRATION1.reg = (data->CANId & 0xFFFF); /* write lower 16bits CANId */ + break; + default: + return BASE_STATUS_ERROR; + } + canHandle->baseAddress->IF1_ARBITRATION2.reg = id; + /* Step2: setting mask register 2 */ + canHandle->baseAddress->IF1_MASK2.reg = 0x8000; + /* Step3: setting mask register 1 */ + canHandle->baseAddress->IF1_MASK1.reg = 0x0000; + /* Step4: setting message control register */ + canHandle->baseAddress->IF1_MESSAGE_CONTROL.reg |= 0x8980; + canHandle->baseAddress->IF1_MESSAGE_CONTROL.BIT.DLC = data->dataLength; + /* Step5: write data to be sent */ + WriteData(canHandle, data); + /* Step6: send configuration to packet objects */ + canHandle->baseAddress->IF1_COMMAND_MASK.reg = 0xF3; + /* Step7: write IF1 request command */ + canHandle->baseAddress->IF1_COMMAND_REQUEST.BIT.MessageNumber = objId; + canHandle->state = CAN_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief Interrupt receiving callback function. + * @param canHandle CAN handle. + * @param objId Indicates the packet object ID. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +static BASE_StatusType CAN_ReadCallback(CAN_Handle *canHandle, unsigned int objId) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + CAN_PARAM_CHECK_WITH_RET(canHandle->rxFrame != NULL, BASE_STATUS_ERROR); + CAN_PARAM_CHECK_WITH_RET((objID >= MESSAGE_NUMBER_MIN) && (objID <= MESSAGE_NUMBER_MAX), BASE_STATUS_ERROR); + unsigned int busy, id, idLow, idHigh, extendedFrame, remoteFrame; + /* Step1: setting request transfer to packet object */ + canHandle->baseAddress->IF2_COMMAND_MASK.reg = 0x7F; /* 0x7F indicates reading data from the packet object */ + /* Step2: Request specififed packet object */ + canHandle->baseAddress->IF2_COMMAND_REQUEST.BIT.MessageNumber = objId; + do { + busy = canHandle->baseAddress->IF2_COMMAND_REQUEST.BIT.BUSY; + } while (busy != 0x00); + /* Step3: Obtains packet information */ + extendedFrame = canHandle->baseAddress->IF2_ARBITRATION2.BIT.Xtd; + remoteFrame = canHandle->baseAddress->IF2_ARBITRATION2.BIT.Dir; + if (extendedFrame == BASE_CFG_ENABLE) { + idLow = canHandle->baseAddress->IF2_ARBITRATION1.BIT.ID; + idHigh = canHandle->baseAddress->IF2_ARBITRATION2.BIT.ID; + id = idLow; + idHigh <<= 16; /* High 16 bits ID */ + id |= idHigh; + canHandle->rxFrame->CANId = id; + id |= CAN_EFF_FLAG; + if (remoteFrame == BASE_CFG_ENABLE) { + id |= CAN_RTR_FLAG; + canHandle->rxFrame->type = CAN_TYPEFRAME_EXT_REMOTE; + } else { + canHandle->rxFrame->type = CAN_TYPEFRAME_EXT_DATA; + } + } else { + id = canHandle->baseAddress->IF2_ARBITRATION2.BIT.ID; + id >>= 2; /* 2: Standard frame CAN id. */ + canHandle->rxFrame->CANId = id; + if (remoteFrame == BASE_CFG_ENABLE) { + id |= CAN_RTR_FLAG; + canHandle->rxFrame->type = CAN_TYPEFRAME_STD_REMOTE; + } else { + canHandle->rxFrame->type = CAN_TYPEFRAME_STD_DATA; + } + } + canHandle->rxFrame->dataLength = canHandle->baseAddress->IF2_MESSAGE_CONTROL.BIT.DLC; + canHandle->rxFrame->frame[0] = canHandle->baseAddress->IF2_DATAA1.BIT.DATA0; /* Data of bit 0 */ + canHandle->rxFrame->frame[1] = canHandle->baseAddress->IF2_DATAA1.BIT.DATA1; /* Data of bit 1 */ + canHandle->rxFrame->frame[2] = canHandle->baseAddress->IF2_DATAA2.BIT.DATA2; /* Data of bit 2 */ + canHandle->rxFrame->frame[3] = canHandle->baseAddress->IF2_DATAA2.BIT.DATA3; /* Data of bit 3 */ + canHandle->rxFrame->frame[4] = canHandle->baseAddress->IF2_DATAB1.BIT.DATA4; /* Data of bit 4 */ + canHandle->rxFrame->frame[5] = canHandle->baseAddress->IF2_DATAB1.BIT.DATA5; /* Data of bit 5 */ + canHandle->rxFrame->frame[6] = canHandle->baseAddress->IF2_DATAB2.BIT.DATA6; /* Data of bit 6 */ + canHandle->rxFrame->frame[7] = canHandle->baseAddress->IF2_DATAB2.BIT.DATA7; /* Data of bit 7 */ + return BASE_STATUS_OK; +} + +/** + * @brief CAN Bus receive filtering configuration. + * @param canHandle CAN handle. + * @param CAN_FilterConfigure handle of filtering configuration, @ref CAN_FilterConfigure + * @param objId Indicates the packet object ID. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +static void CAN_ReceiveFilter(CAN_Handle *canHandle, const CAN_FilterConfigure *filterConfigure, unsigned int objId) +{ + unsigned int id, idChg; + unsigned int mask, maskChg; + idChg = filterConfigure->filterID & 0xFFFF; + maskChg = filterConfigure->filterMask & 0xFFFF; + switch (filterConfigure->receiveType) { + case CAN_FILTERFRAME_STD_DATA: + id = (filterConfigure->filterID & CAN_STD_MASK) << 2; /* Bit[12:2] = CANId */ + id |= 0x8000; + idChg = 0x0000; + /* Shift left by 2 bits. The upper 11 bits of [12:0] are used */ + mask = (filterConfigure->filterMask & CAN_STD_MASK) << 2; + mask |= 0xC000; + maskChg = 0x0000; + break; + case CAN_FILTERFRAME_EXT_DATA: + id = (filterConfigure->filterID & CAN_EXT_MASK) >> 16; /* Bit[12:0] = CANId(28bit ~ 16bit) */ + id |= 0xC000; + /* write lower 16bits CANId */ + mask = (filterConfigure->filterMask & CAN_EXT_MASK) >> 16; /* Remove the lower 16 bits */ + mask |= 0xC000; + break; + case CAN_FILTERFRAME_STD_EXT_DATA: + id = (filterConfigure->filterID & CAN_EXT_MASK) >> 16; /* Remove the lower 16 bits */ + id |= 0xC000; + mask = (filterConfigure->filterMask & CAN_EXT_MASK) >> 16; /* Remove the lower 16 bits */ + mask |= 0x4000; /* [15]MXtd = 0 */ + break; + default: + return; + } + canHandle->baseAddress->IF2_ARBITRATION2.reg = id; + canHandle->baseAddress->IF2_ARBITRATION1.reg = idChg; + canHandle->baseAddress->IF2_MASK2.reg = mask; + canHandle->baseAddress->IF2_MASK1.reg = maskChg; + if (canHandle->rxFIFODepth > BOUND_ID) { + canHandle->rxFIFODepth = BOUND_ID; + } + if (objId < canHandle->rxFIFODepth) { /* packet objects form the receiving FIFO */ + canHandle->baseAddress->IF2_MESSAGE_CONTROL.reg = 0x1408; /* EOB is set 0 */ + } else { + canHandle->baseAddress->IF2_MESSAGE_CONTROL.reg = 0x1488; /* EOB is set 1 */ + } + /* Step5: send configuration to packet objects */ + canHandle->baseAddress->IF2_COMMAND_MASK.reg = 0x00F3; + /* Step6: write IF2 request command */ + canHandle->baseAddress->IF2_COMMAND_REQUEST.BIT.MessageNumber = objId; + canHandle->baseAddress->IF2_COMMAND_REQUEST.BIT.BUSY = 0x01; +} + +/** + * @brief Receive CAN data frames asynchronously. + * @param canHandle CAN handle. + * @param data Address for storing CAN data frames, @ref CANFrame + * @param filterConfigure handle of filtering configuration, @ref CAN_FilterConfigure + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_CAN_ReadIT(CAN_Handle *canHandle, CANFrame *data, CAN_FilterConfigure *filterConfigure) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + CAN_PARAM_CHECK_WITH_RET(data != NULL, BASE_STATUS_ERROR); + CAN_PARAM_CHECK_WITH_RET(filterConfigure != NULL, BASE_STATUS_ERROR); + if (canHandle->state != CAN_STATE_READY) { + return BASE_STATUS_BUSY; + } + canHandle->state = CAN_STATE_BUSY_RX; + canHandle->rxFrame = data; + canHandle->rxFilter = filterConfigure; + for (int i = 1; i <= BOUND_ID; i++) { + CAN_ReceiveFilter(canHandle, filterConfigure, i); + } + canHandle->state = CAN_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief Pre-configuration of Receive CAN Data Frames. + * @param canHandle CAN handle. + * @param objId Indicates the packet object ID. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +static BASE_StatusType CAN_ConfigReadReq(CAN_Handle *canHandle, unsigned int objId) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + unsigned int map = 1; + map <<= objId - 1; + /* Step1: write id into register arbitration according frame type */ + if ((map & g_stdRecvMap) != 0) { /* STD DATA FRAME */ + canHandle->baseAddress->IF2_ARBITRATION2.reg = 0x8000; + canHandle->baseAddress->IF2_ARBITRATION1.reg = 0x0000; + } else if ((map & g_extRecvMap) != 0) { /* EXTENDED DATA FRAME */ + canHandle->baseAddress->IF2_ARBITRATION2.reg = 0xC000; + canHandle->baseAddress->IF2_ARBITRATION1.reg = 0x0000; + } else { + return BASE_STATUS_ERROR; + } + /* Step2: setting mask register 2 */ + canHandle->baseAddress->IF2_MASK2.reg = 0xC000; + /* Step3: setting mask register 1 */ + canHandle->baseAddress->IF2_MASK1.reg = 0x0000; + /* Step4: setting message control register. By default, there is no RX FIFO and no filtering is performed */ + canHandle->baseAddress->IF2_MESSAGE_CONTROL.reg = 0x1488; + /* Step5: send configuration to packet objects */ + canHandle->baseAddress->IF2_COMMAND_MASK.reg = 0x00F3; + /* Step6: write IF2 request command */ + canHandle->baseAddress->IF2_COMMAND_REQUEST.BIT.MessageNumber = objId; + canHandle->baseAddress->IF2_COMMAND_REQUEST.BIT.BUSY = BASE_CFG_ENABLE; + return BASE_STATUS_OK; +} + +/** + * @brief The object of the sent packet is cleared. + * @param canHandle CAN handle. + * @param objId Indicates the packet object ID. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +static BASE_StatusType WriteFinishClear(CAN_Handle *canHandle, unsigned int objId) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + unsigned int busy; + canHandle->baseAddress->IF2_COMMAND_MASK.reg = 0x7F; + canHandle->baseAddress->IF2_COMMAND_REQUEST.BIT.MessageNumber = objId; + do { + busy = canHandle->baseAddress->IF2_COMMAND_REQUEST.BIT.BUSY; + } while (busy != 0x00); + return BASE_STATUS_OK; +} + +/** + * @brief Write interrupt service function. + * @param canHandle CAN handle. + * @param irqIndex Packet object interrupt ID. + * @retval None. + */ +static void WriteIrqService(CAN_Handle *canHandle, unsigned int irqIndex) +{ + WriteFinishClear(canHandle, irqIndex); + g_msgObj[irqIndex - 1] = 0; + if (canHandle->userCallBack.WriteFinishCallBack != NULL) { + canHandle->userCallBack.WriteFinishCallBack(canHandle); + } +} + +/** + * @brief Read interrupt service function. + * @param canHandle CAN handle. + * @param irqIndex Packet object interrupt ID. + * @retval None. + */ +static void ReadIrqService(CAN_Handle *canHandle, unsigned int irqIndex) +{ + CAN_ReadCallback(canHandle, irqIndex); + if (canHandle->userCallBack.ReadFinishCallBack != NULL) { + canHandle->userCallBack.ReadFinishCallBack(canHandle); + } +} + +/** + * @brief CAN interrupt service processing function. + * @param handle CAN handle. + * @retval None. + */ +void HAL_CAN_IrqHandler(void *handle) +{ + CAN_ASSERT_PARAM(handle != NULL); + CAN_Handle *canHandle = (CAN_Handle *)handle; + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + unsigned int irqIndex; + unsigned int idLow, idHigh, id; + irqIndex = canHandle->baseAddress->CAN_INTERRUPT.reg; + /* Status interrupt ID: 0x8000 */ + if (irqIndex == 0x8000) { + /* Offline status of the CAN bus. */ + unsigned int statusBusoff = canHandle->baseAddress->CAN_STATUS.BIT.Boff; + if (statusBusoff == BASE_CFG_ENABLE) { /* true when the bus-off state is displayed. */ + canHandle->baseAddress->CAN_CONTROL.BIT.Init = 0x01; + __asm__ volatile ("nop"); /* Hold-off time */ + canHandle->baseAddress->CAN_CONTROL.BIT.Init = 0x00; + } + if (canHandle->userCallBack.TransmitErrorCallBack != NULL) { + canHandle->userCallBack.TransmitErrorCallBack(canHandle); + } + } else if (irqIndex >= 0x01 && irqIndex <= 0x20) { /* Packet object interrupt ID from 0x01 to 0x20 */ + idLow = canHandle->baseAddress->INTERRUPT_PENDING1.BIT.IntPnd16_1; + idHigh = canHandle->baseAddress->INTERRUPT_PENDING2.BIT.IntPnd32_17; + id = idLow; + id |= idHigh << 16; /* High 16 bits ID */ + if (id & g_allSendMap) { /* Write complete */ + WriteIrqService(canHandle, irqIndex); + } + if (id & g_allRecvMap) { + ReadIrqService(canHandle, irqIndex); + } + } + return; +} + +/** + * @brief Handle CAN interrupt request. + * @param canHandle CAN handle. + * @param typeID Id of callback function type, @ref CAN_CallBackFunType + * @param pCallback Pointer of the specified callbcak function, @ref CAN_CallbackType + * @retval BASE_StatusType: BASE_STATUS_ERROR register error, BASE_STATUS_OK register success. + */ +BASE_StatusType HAL_CAN_RegisterCallBack(CAN_Handle *canHandle, CAN_CallBackFunType typeID, CAN_CallbackType pCallback) +{ + CAN_ASSERT_PARAM(canHandle != NULL); + CAN_ASSERT_PARAM(IsCANInstance(canHandle->baseAddress)); + switch (typeID) { + case CAN_WRITE_FINISH: /* CAN write finish call back. */ + canHandle->userCallBack.WriteFinishCallBack = pCallback; + break; + case CAN_READ_FINISH: /* CAN read finish call back. */ + canHandle->userCallBack.ReadFinishCallBack = pCallback; + break; + case CAN_TRNS_ERROR: /* CAN transmit finish call back. */ + canHandle->userCallBack.TransmitErrorCallBack = pCallback; + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/capm/common/inc/capm.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/capm/common/inc/capm.h new file mode 100644 index 00000000..eae8fb20 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/capm/common/inc/capm.h @@ -0,0 +1,186 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file capm.h + * @author MCU Driver Team + * @brief CAPM module driver + * @details This file provides firmware CAPM Handle Structure and functions + * prototypes to manage the following functionalities of the CAPM. + * + CAPM handle structure definition. + * + Initialization and de-initialization functions. + * + CAPM Service Functions. + */ +#ifndef McuMagicTag_CAPM_H +#define McuMagicTag_CAPM_H + +#include "typedefs.h" +#include "dma.h" +#include "capm_ip.h" + +/** + * @defgroup CAPM CAPM + * @brief CAPM module. + * @{ + */ + +/** + * @defgroup CAPM_Common CAPM Common + * @brief CAPM common external module. + * @{ + */ + + +/** + * @defgroup CAPM_Common_Param CAPM Common Parameters + * @{ + */ +#define CAPM_NUM_0 0 +#define CAPM_NUM_1 1 +#define CAPM_NUM_2 2 + +/** + * @brief Capture edge mode + */ +typedef enum { + CAPM_FALLING, + CAPM_RISING, +} CAPM_CapEvent; + +/** + * @brief Reset mode + */ +typedef enum { + CAPM_NOTRESET, + CAPM_RESET, +} CAPM_RegRestMode; + +/** + * @brief Signal level + */ +typedef enum { + CAPM_LOW_LEVEL, + CAPM_UP_EDGE, + CAPM_DOWN_EDGE, + CAPM_HIGHT_LEVEL, +} CAPM_CaptureLevel; + +/** + * @brief Numbers of ECR + */ +typedef enum { + CAPM_ECR_NUM1, + CAPM_ECR_NUM2, + CAPM_ECR_NUM3, + CAPM_ECR_NUM4 +} CAPM_ECRNum; + +/** + * @brief Used ECR of next load + */ +typedef enum { + CAPM_NEXT_LOAD_ECR1, + CAPM_NEXT_LOAD_ECR2, + CAPM_NEXT_LOAD_ECR3, + CAPM_NEXT_LOAD_ECR4, +} CAPM_NextLoadECR; + +/** + * @brief CAPM callback function type + */ +typedef enum { + CAPM_EVT_FINISH = 0x00000000U, + CAPM_DMA_ERROR = 0x00000001U, + CAPM_DMA_FINISH = 0x00000002U +} CAPM_CallbackFuncType; + +/** + * @} + */ + +/** + * @defgroup CAPM_Handle_Definition CAPM Handle Definition + * @{ + */ + +/** + * @brief Configurations of each capture register + */ +typedef struct CapmCapRegConfig { + CAPM_CapEvent capEvent; + CAPM_RegRestMode regReset; +} CAPM_CapRegConfig; + +/** + * @brief The definition of the CAPM handle structure + */ +typedef struct _CAPM_Handle { + CAPM_RegStruct *baseAddress; /**< base address */ + unsigned int tscntDiv; /**< TSR count division, value range: 0~65535 */ + DMA_Handle *dmaHandle; /**< DMA handle */ + unsigned int dmaChannel; /**< Used DMA channel */ + + unsigned int preScale; /**< preScale factor. value range: 0~127 */ + unsigned int deburrNum; /**< deburr level. value range:0~8192. 0: Disable deburr */ + unsigned int useCapNum; /**< number of cap to be use. + value range: 1~CAPM_MAX_CAP_REG_NUM */ + unsigned int triggleDmaReg; /**< which ECR to triggle DMA interrupt. + value range:1 ~ useCapNum */ + unsigned int syncPhs; /**< TSRֵ sync phase value */ + bool enableSync; /**< enable sync */ + CAPM_SyncSrc syncSrc; /**< CAPM synchronized input source */ + unsigned int enableIntFlags; /**< enable interrupt */ + CAPM_CapMode capMode; /**< capture mode. continue or one-shot */ + CAPM_InputSrc inputSrc; /**< capture input source */ + CAPM_CapRegConfig capRegConfig[CAPM_MAX_CAP_REG_NUM]; /**< each capture register configuration */ + CAPM_UserCallBack userCallBack; /**< CAPM Interrupt callback functions.*/ + CAPM_ExtendHandle handleEx; /**< CAPM extend parameter */ +} CAPM_Handle; + +typedef void (* CAPM_CallbackType)(void *handle); +/** + * @} + */ + +/** + * @defgroup CAPM_API_Declaration CAPM HAL API + * @{ + */ +BASE_StatusType HAL_CAPM_Init(CAPM_Handle *handle); +BASE_StatusType HAL_CAPM_DeInit(CAPM_Handle *handle); + +unsigned int HAL_CAPM_GetECRValue(CAPM_Handle *handle, CAPM_ECRNum ecrNum); +unsigned char HAL_CAPM_GetCrtEdge(CAPM_Handle *handle); +unsigned char HAL_CAPM_GetNextLoadECRNum(CAPM_Handle *handle); +BASE_StatusType HAL_CAPM_GetECRValueDMA(CAPM_Handle *handle, unsigned int *saveData, unsigned int dataLength); + +void HAL_CAPM_SetSyncPhs(CAPM_Handle *handle, unsigned int phase); +unsigned int HAL_CAPM_GetSyncPhs(CAPM_Handle *handle); + +void HAL_CAPM_IrqHandler(void *handle); +void HAL_CAPM_RegisterCallback(CAPM_Handle *capmHandle, CAPM_CallbackFuncType typeID, CAPM_CallbackType pCallback); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/capm/inc/capm_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/capm/inc/capm_ip.h new file mode 100644 index 00000000..e708e973 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/capm/inc/capm_ip.h @@ -0,0 +1,1865 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file capm_ip.h + * @author MCU Driver Team + * @brief CAPM DCL level module driver. + * @details This file provides DCL functions to manage CAPM and Definition of + * specific parameters. + * + Definition of CAPM configuration parameters. + * + CAPM register mapping structure. + * + Direct configuration layer interface. + */ +#ifndef McuMagicTag_CAPM_IP_H +#define McuMagicTag_CAPM_IP_H + +#include "baseinc.h" +#include "baseaddr.h" + +#ifdef CAPM_PARAM_CHECK +#define CAPM_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define CAPM_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define CAPM_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define CAPM_ASSERT_PARAM(para) ((void)0U) +#define CAPM_PARAM_CHECK_NO_RET(para) ((void)0U) +#define CAPM_PARAM_CHECK_WITH_RET(param, ret) ((void)0U) +#endif + +/** + * @addtogroup CAPM + * @{ + */ + +/** + * @defgroup CAPM_IP CAPM_IP + * @brief CAPM_IP: capm_v0. + * @{ + */ + +/** + * @defgroup CAPM_Param_Def CAPM Parameters Definition + * @brief Definition of CAPM configuration parameters + * @{ + */ + +#define CAPM_RELEASE_DATE_MASK 0x00FFFFFFU +#define CAPM_IP_VER_MASK 0x0F000000U +#define CAPM_NEXT_LOAD_REG_MASK 0x00000003U +#define CAPM_INTERRUPT_MASK 0x0000001FU +#define CAPM_MAX_FILTER_VALUE 16 +#define CAPM_MAX_PRESCALE 127 +#define CAPM_MAX_CAP_REG_NUM 4 +#define CAPM_MAX_FILTER_LEVEL 0x00001FFFU +#define CAPM_BIT_SHIFT_TWO 2 +#define CAPM_MAX_INTERRUPT_NUMBER 8 + +#define CAPM0_BASEADDR CAPM0 +#define CAPM1_BASEADDR CAPM1 +#define CAPM2_BASEADDR CAPM2 + +/** + * @brief EAR count types. + * @details Count type: + * + CAPM_COUNT_NONE -- EAR do not count + * + CAPM_COUNT_RISING_EDGE -- EAR counting at rising edge + * + CAPM_COUNT_FALLING_EDGE -- EAR counting at falling edge + * + CAPM_COUNT_DOUBLE_EDGE -- EAR counting at rising edge or edge + */ +typedef enum { + CAPM_COUNT_NONE = 0x00000000U, + CAPM_COUNT_RISING_EDGE = 0x00000001U, + CAPM_COUNT_FALLING_EDGE = 0x00000002U, + CAPM_COUNT_DOUBLE_EDGE = 0x00000003U, +} CAPM_CountType; + +/** + * @brief Interrupt types. + * @details Type: + * + CAPM_REG1CAP -- ECR1 interrupt + * + CAPM_REG2CAP -- ECR2 interrupt + * + CAPM_REG3CAP -- ECR3 interrupt + * + CAPM_REG4CAP -- ECR4 interrupt + * + CAPM_TSROVF -- TSR register overflow interrupt + * + CAPM_ECROVF -- ECR register overflow interrupt + * + CAPM_EARCMPMATCH -- EAR compare match interrupt + * + CAPM_EAROVF -- EAR register overflow interrupt + * + CAPM_DMAREQOVF -- DMA require overflow interrupt + */ +typedef enum { + CAPM_REG1CAP = 0x00000001U, + CAPM_REG2CAP = 0x00000002U, + CAPM_REG3CAP = 0x00000004U, + CAPM_REG4CAP = 0x00000008U, + CAPM_TSROVF = 0x00000010U, + CAPM_ECROVF = 0x00000020U, + CAPM_EARCMPMATCH = 0x00000040U, + CAPM_EAROVF = 0x00000080U, + CAPM_DMAREQOVF = 0x00000100U, +} CAPM_Interrupt; + +/** + * @brief ECR number to be used. + */ +typedef enum { + CAPM_EVT1 = 0x00000000U, + CAPM_EVT2 = 0x00000001U, + CAPM_EVT3 = 0x00000002U, + CAPM_EVT4 = 0x00000003U, +} CampConfigCapRegNum; + +/** + * @brief CAPM capture mode. + * @details Capture mode: + * + CAPM_CONTINUECAP -- continue cap + * + CAPM_ONESHOTCAP -- one-shot cap + */ +typedef enum { + CAPM_CONTINUECAP = 0x00000000U, /**< continue cap */ + CAPM_ONESHOTCAP = 0x00000001U, /**< one-shot cap */ +} CAPM_CapMode; + +/** + * @brief CAPM capture edge. + * @details Capture edge: + * + CAPM_FALLING_EDGE -- capture falling edge + * + CAPM_RISING_EDGE -- capture rising edge + */ +typedef enum { + CAPM_FALLING_EDGE = 0x00000000U, + CAPM_RISING_EDGE = 0x00000001U, +} CAPM_POLAR; + +/** + * @brief CAPM input source selection. + * @details Capture edge: + * + CAPM_INPUT_SRC0 -- source 0 + * + CAPM_INPUT_SRC1 -- source 1 + */ +typedef enum { + CAPM_INPUT_SRC0 = 0x00000000U, + CAPM_INPUT_SRC1 = 0x00000001U, +} CAPM_InputSrc; + +/** + * @brief CAPM sync input source selection. + * @details Capture edge: + * + CAPM_SYNC_SRC_NONE -- source none + * + CAPM_SYNC_SRC_APT0 -- source apt0 + * + CAPM_SYNC_SRC_APT1 -- source apt1 + * + CAPM_SYNC_SRC_APT2 -- source apt2 + * + CAPM_SYNC_SRC_APT3 -- source apt3 + * + CAPM_SYNC_SRC_APT4 -- source apt4 + * + CAPM_SYNC_SRC_APT5 -- source apt5 + * + CAPM_SYNC_SRC_APT6 -- source apt6 + * + CAPM_SYNC_SRC_APT7 -- source apt7 + * + CAPM_SYNC_SRC_APT8 -- source apt8 + */ +typedef enum { + CAPM_SYNC_SRC_NONE = 0x00000000U, + CAPM_SYNC_SRC_APT0 = 0x00000001U, + CAPM_SYNC_SRC_APT1 = 0x00000002U, + CAPM_SYNC_SRC_APT2 = 0x00000003U, + CAPM_SYNC_SRC_APT3 = 0x00000004U, + CAPM_SYNC_SRC_APT4 = 0x00000005U, + CAPM_SYNC_SRC_APT5 = 0x00000006U, + CAPM_SYNC_SRC_APT6 = 0x00000007U, + CAPM_SYNC_SRC_APT7 = 0x00000008U, + CAPM_SYNC_SRC_APT8 = 0x00000009U, +} CAPM_SyncSrc; + +/** + * @} + */ + +/** + * @defgroup CAPM_REG_Definition CAPM Register Structure. + * @brief CAPM Register Structure Definition. + * @{ + */ + +/** + * @brief CAPM revision information registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int y_m_d_info : 24; /**< Version date(year, month and day). */ + unsigned int revision : 4; /**< IP version number. */ + unsigned int reserved : 4; + } BIT; +} volatile REV_INFO_REG; + +/** + * @brief CAPM time-stamp divider registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int tscnt_div : 16; /**< Counter division. */ + unsigned int reserved : 16; + } BIT; +} volatile TSR_DIV_REG; + +/** + * @brief CAPM edge amount registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int ear : 16; /**< Edge count value. */ + unsigned int reserved : 16; + } BIT; +} volatile EAR_REG; + +/** + * @brief EAR compare value registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int earcmp : 16; /**< Edge count compare value. */ + unsigned int reserved : 16; + } BIT; +} volatile EAR_CMP_REG; + +/** + * @brief Event capture sequence registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int nxtldecr : 2; /**< Read next loaded ECR. */ + unsigned int crt_edge : 2; /**< Current input signal level. */ + unsigned int reserved : 28; + } BIT; +} volatile ECSEQR_REG; + +/** + * @brief Filter control registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int ft_en : 1; /**< Filter function enable. */ + unsigned int ft_lev : 13; /**< Filter level. */ + unsigned int reserved : 18; + } BIT; +} volatile FTCR_REG; + +/** + * @brief CCR1 registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int evt1pol : 1; /**< Event1 capture edge selection. */ + unsigned int evt1rst : 1; /**< Event1 reset TSR. */ + unsigned int evt2pol : 1; /**< Event2 capture edge selection. */ + unsigned int evt2rst : 1; /**< Event2 reset TSR. */ + unsigned int evt3pol : 1; /**< Event3 capture edge selection. */ + unsigned int evt3rst : 1; /**< Event3 reset TSR. */ + unsigned int evt4pol : 1; /**< Event4 capture edge selection. */ + unsigned int evt4rst : 1; /**< Event4 reset TSR. */ + unsigned int ecrlden : 1; /**< Capture enable. */ + unsigned int dmaevt_sel : 2; /**< DMA request event selection. */ + unsigned int psc : 8; /**< Pre-division coefficient of the input signal. */ + unsigned int cnt_edge_sel : 2; /**< Edge type selection of edge count.*/ + unsigned int reserved : 11; + } BIT; +} volatile CCR1_REG; + +/** + * @brief CCR2 registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 3; + unsigned int emu_stop_en : 1; /**< Emulation stop TSR enable. */ + unsigned int reserved1 : 28; + } BIT; +} volatile CCR2_REG; + +/** + * @brief CCR3 registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int cap_mode : 1; /**< Capture mode selection. */ + unsigned int seq_stop : 2; /**< End of capture sequence/Boundary of circulation. */ + unsigned int reserved : 29; + } BIT; +} volatile CCR3_REG; + +/** + * @brief CAPM interrupt enable registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int evt1_en : 1; /**< Event1 interrupt enable. */ + unsigned int evt2_en : 1; /**< Event2 interrupt enable. */ + unsigned int evt3_en : 1; /**< Event3 interrupt enable. */ + unsigned int evt4_en : 1; /**< Event4 interrupt enable. */ + unsigned int tsr_ovf_en : 1; /**< TSR overflow interrupt enable. */ + unsigned int ecr_ovf_en : 1; /**< Capture overflow interrupt enable. */ + unsigned int earcmp_match_en : 1; /**< Edge count compare match interrupt enable. */ + unsigned int ear_ovf_en : 1; /**< Edge count overflow interrupt enable. */ + unsigned int dmareq_ovf_en : 1; /**< DMA request overflow interrupt enable. */ + unsigned int reserved : 23; + } BIT; +} volatile INTENR_REG; + +/** + * @brief CAPM initial interrupt registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int evt1_raw : 1; /**< Event1 initial interrupt. */ + unsigned int evt2_raw : 1; /**< Event2 initial interrupt. */ + unsigned int evt3_raw : 1; /**< Event3 initial interrupt. */ + unsigned int evt4_raw : 1; /**< Event4 initial interrupt. */ + unsigned int tsr_ovf_raw : 1; /**< TSR overflow initial interrupt. */ + unsigned int ecr_ovf_raw : 1; /**< Capture overflow initial interrupt. */ + unsigned int earcmp_match_raw : 1; /**< Edge count compare match initial interrupt. */ + unsigned int ear_ovf_raw : 1; /**< Edge count overflow initial interrupt. */ + unsigned int dmareq_ovf_raw : 1; /**< DMA request overflow initial interrupt. */ + unsigned int reserved : 23; + } BIT; +} volatile INTRAWR_REG; + +/** + * @brief CAPM interrupt injection registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int evt1_inj : 1; /**< Event1 interrupt injection. */ + unsigned int evt2_inj : 1; /**< Event2 interrupt injection. */ + unsigned int evt3_inj : 1; /**< Event3 interrupt injection. */ + unsigned int evt4_inj : 1; /**< Event4 interrupt injection. */ + unsigned int tsr_ovf_inj : 1; /**< TSR overflow interrupt injection. */ + unsigned int ecr_ovf_inj : 1; /**< Capture overflow interrupt injection. */ + unsigned int earcmp_match_inj : 1; /**< Edge count compare match interrupt injection. */ + unsigned int ear_ovf_inj : 1; /**< Edge count overflow interrupt injection. */ + unsigned int dmareq_ovf_inj : 1; /**< DMA request overflow interrupt injection. */ + unsigned int reserved : 23; + } BIT; +} volatile INTINJR_REG; + +/** + * @brief CAPM interrupt status registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int evt1_int : 1; /**< Event1 interrupt status. */ + unsigned int evt2_int : 1; /**< Event2 interrupt status. */ + unsigned int evt3_int : 1; /**< Event3 interrupt status. */ + unsigned int evt4_int : 1; /**< Event4 interrupt status. */ + unsigned int tsr_ovf_int : 1; /**< TSR overflow interrupt status. */ + unsigned int ecr_ovf_int : 1; /**< Capture overflow interrupt status. */ + unsigned int earcmp_match_int : 1; /**< Edge count compare match interrupt status. */ + unsigned int ear_ovf_int : 1; /**< Edge count overflow interrupt status. */ + unsigned int dmareq_ovf_int : 1; /**< DMA request overflow interrupt status. */ + unsigned int reserved : 23; + } BIT; +} volatile INTFLGR_REG; + +/** + * @brief Event interrupt + */ +typedef enum { + CAPM_INTREG1CAP = 0x00000000U, + CAPM_INTREG2CAP = 0x00000001U, + CAPM_INTREG3CAP = 0x00000002U, + CAPM_INTREG4CAP = 0x00000003U, + CAPM_INTTSROVF = 0x00000004U, + CAPM_INTECROVF = 0x00000005U, + CAPM_INTEARCMPMATCH = 0x00000006U, + CAPM_INTEAROVF = 0x00000007U, + CAPM_INTDMAREQOVF = 0x00000008U, +} CAPM_IntEvent; + +/** + * @brief CAPM Interrupt callback functions. + * + */ +typedef void (*EvtCallbackType)(void *handle, CAPM_IntEvent intValue); +typedef struct { + EvtCallbackType EvtFinishCallback; /**< event finish callback function. */ + void (*DmaFinishCallback)(void *handle); /**< DMA finish callback function. */ + void (*DmaErrorCallback)(void *handle); /**< DMA error callback function. */ +} CAPM_UserCallBack; + +/** + * @brief CAPM extend handle. + */ +typedef struct _CAPM_ExtendeHandle { +} CAPM_ExtendHandle; + +/** + * @brief CAPM registers definition structure. + */ +typedef struct { + REV_INFO_REG REV_INFO; /**< CAPM revision information register, offset address: 0x0000. */ + unsigned int tsr; /**< CAPM time-stamp register, offset address: 0x0004. */ + TSR_DIV_REG TSR_DIV; /**< CAPM time-stamp divider register, offset address: 0x0008. */ + EAR_REG EAR; /**< CAPM edge amount register, offset address: 0x000C. */ + EAR_CMP_REG EAR_CMP; /**< EAR compare value register, offset address: 0x0010. */ + unsigned int SYNC_PHS; /**< Sync phase, offset address: 0x0014. */ + unsigned int ECR1; /**< Event1 capture register, offset address: 0x0018. */ + unsigned int ECR2; /**< Event2 capture register, offset address: 0x001C. */ + unsigned int ECR3; /**< Event3 capture register, offset address: 0x0020. */ + unsigned int ECR4; /**< Event4 capture register, offset address: 0x0024. */ + ECSEQR_REG ECSEQR; /**< Event capture sequence register, offset address: 0x0028. */ + FTCR_REG FTCR; /**< Filter control register, offset address: 0x002C. */ + CCR1_REG CCR1; /**< CCR1 register, offset address: 0x0030. */ + CCR2_REG CCR2; /**< CCR2 register, offset address: 0x0034. */ + CCR3_REG CCR3; /**< CCR3 register, offset address: 0x0038. */ + unsigned int reserve; + INTENR_REG INTENR; /**< CAPM interrupt enable register, offset address: 0x0040. */ + INTRAWR_REG INTRAWR; /**< CAPM initial interrupt register, offset address: 0x0044. */ + INTINJR_REG INTINJR; /**< CAPM interrupt injection register, offset address: 0x0048. */ + INTFLGR_REG INTFLGR; /**< CAPM interrupt status register, offset address: 0x004C. */ +} volatile CAPM_RegStruct; + +/** + * @brief Capture module general control registers structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int restart_capm0 : 1; /**< CAPM0 start a new single round capture. */ + unsigned int restart_capm1 : 1; /**< CAPM1 start a new single round capture. */ + unsigned int restart_capm2 : 1; /**< CAPM2 start a new single round capture. */ + unsigned int reserved1 : 5; + unsigned int tsr_stop_capm0 : 1; /**< CAPM0 TSR stop count enable. */ + unsigned int tsr_stop_capm1 : 1; /**< CAPM1 TSR stop count enable. */ + unsigned int tsr_stop_capm2 : 1; /**< CAPM2 TSR stop count enable. */ + unsigned int reserved2 : 5; + unsigned int stat_rst_capm0 : 1; /**< CAPM0 work state reset. */ + unsigned int stat_rst_capm1 : 1; /**< CAPM1 work state reset. */ + unsigned int stat_rst_capm2 : 1; /**< CAPM2 work state reset. */ + unsigned int reserve3 : 5; + unsigned int sync_sw_capm0 : 1; /**< Triggle CAPM0 sync, TSR reset, capture sequence reset. */ + unsigned int sync_sw_capm1 : 1; /**< Triggle CAPM1 sync, TSR reset, capture sequence reset. */ + unsigned int sync_sw_capm2 : 1; /**< Triggle CAPM2 sync, TSR reset, capture sequence reset. */ + unsigned int reserve4 : 5; + } BIT; +} volatile CAPM_GENE_CR_REG; + +/** + * @brief Sync selection register for CAPM0 structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int capm0_sync_sel : 4; /**< CAPM0 hardware sync source selection. */ + unsigned int capm0_synci_en : 1; /**< CAPM0 sync enable. */ + unsigned int reserved : 27; + } BIT; +} volatile SYNC_SELR0_REG; + +/** + * @brief Sync selection register for CAPM1 structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int capm1_sync_sel : 4; /**< CAPM1 hardware sync source selection. */ + unsigned int capm1_synci_en : 1; /**< CAPM1 sync enable. */ + unsigned int reserved : 27; + } BIT; +} volatile SYNC_SELR1_REG; + +/** + * @brief Sync selection register for CAPM2 structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int capm2_sync_sel : 4; /**< CAPM2 hardware sync source selection. */ + unsigned int capm2_synci_en : 1; /**< CAPM2 sync enable. */ + unsigned int reserved : 27; + } BIT; +} volatile SYNC_SELR2_REG; + +/** + * @brief Input source selection register for CAPM0 structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int capm0_in_sel : 1; /**< CAPM0 input source selection. */ + unsigned int reserved : 31; + } BIT; +} volatile INPUT_SELR0_REG; + +/** + * @brief Input source selection register for CAPM1 structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int capm1_in_sel : 1; /**< CAPM1 input source selection. */ + unsigned int reserved : 31; + } BIT; +} volatile INPUT_SELR1_REG; + +/** + * @brief Input source selection register for CAPM2 structure definition + */ +typedef union { + unsigned int reg; + struct { + unsigned int capm2_in_sel : 1; /**< CAPM2 input source selection. */ + unsigned int reserved : 31; + } BIT; +} volatile INPUT_SELR2_REG; + +/** + * @brief Define the CAPM common register struct. + */ +typedef struct { + REV_INFO_REG REV_INFO; /**< Revision information, offset address: 0x0000. */ + CAPM_GENE_CR_REG CAPM_GENE_CR; /**< Capture module general control register, offset address: 0x0004. */ + SYNC_SELR0_REG SYNC_SELR0; /**< Sync selection register for CAPM0, offset address: 0x0008. */ + SYNC_SELR1_REG SYNC_SELR1; /**< Sync selection register for CAPM1, offset address: 0x000C. */ + SYNC_SELR2_REG SYNC_SELR2; /**< Sync selection register for CAPM2, offset address: 0x0010. */ + unsigned char reserved[20]; + INPUT_SELR0_REG INPUT_SELR0; /**< Input source selection register for CAPM0, offset address: 0x0028. */ + INPUT_SELR1_REG INPUT_SELR1; /**< Input source selection register for CAPM1, offset address: 0x002C. */ + INPUT_SELR2_REG INPUT_SELR2; /**< Input source selection register for CAPM2, offset address: 0x0030. */ +} volatile CAPM_COMM_RegStruct; + +/** + * @brief Get CAPM IP's release date. + * @param capmx: CAPM register base address. + * @retval Release date. + */ +static inline unsigned int DCL_CAPM_GetReleaseDate(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return (capmx->REV_INFO.reg) & CAPM_RELEASE_DATE_MASK; +} + +/** + * @brief Get CAPM IP's version. + * @param capmx: CAPM register base address. + * @retval CAPM IP's version. + */ +static inline unsigned int DCL_CAPM_GetIPVer(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return (capmx->REV_INFO.reg) & CAPM_IP_VER_MASK; +} + +/** + * @brief Get TSR value. + * @param capmx: CAPM register base address. + * @retval TSR value. + */ +static inline unsigned int DCL_CAPM_GetTSR(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->tsr; +} +/** + * @brief Set TSR divide value. + * @param capmx: CAPM register base address. + * @param divValue: Divide value. Range: 0~65535 + * @retval None. + */ +static inline void DCL_CAPM_SetTSRDiv(CAPM_RegStruct * const capmx, unsigned short divValue) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->TSR_DIV.BIT.tscnt_div = divValue; + return; +} + +/** + * @brief Get EAR value. + * @param capmx: CAPM register base address. + * @retval EAR value. + */ +static inline unsigned int DCL_CAPM_GetEar(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->EAR.BIT.ear; +} + +/** + * @brief Get EAR_CMP value. + * @param capmx: CAPM register base address. + * @retval EAR_CMP value. + */ +static inline unsigned int DCL_CAPM_GetEarCmp(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->EAR_CMP.BIT.earcmp; +} + +/** + * @brief Set sync phase value. + * @param capmx: CAPM register base address. + * @param syncPhs: Phase value. Range: 0~0xFFFF FFFF. + * @retval None. + */ +static inline void DCL_CAPM_SetSyncPhase(CAPM_RegStruct * const capmx, unsigned int syncPhs) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->SYNC_PHS = syncPhs; + return; +} + +/** + * @brief Get sync phase value. + * @param capmx: CAPM register base address. + * @retval Phase value. + */ +static inline unsigned int DCL_CAPM_GetSyncPhase(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->SYNC_PHS; +} + +/** + * @brief Get ECR1 value. + * @param capmx: CAPM register base address. + * @retval ECR1 value. + */ +static inline unsigned int DCL_CAPM_GetECR1(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->ECR1; +} + +/** + * @brief Get ECR2 value. + * @param capmx: CAPM register base address. + * @retval ECR2 value. + */ +static inline unsigned int DCL_CAPM_GetECR2(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->ECR2; +} + +/** + * @brief Get ECR3 value. + * @param capmx: CAPM register base address. + * @retval ECR3 value. + */ +static inline unsigned int DCL_CAPM_GetECR3(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->ECR3; +} + +/** + * @brief Get ECR4 value. + * @param capmx: CAPM register base address. + * @retval ECR4 value. + */ +static inline unsigned int DCL_CAPM_GetECR4(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->ECR4; +} + +/** + * @brief Get current signal level. + * @param capmx: CAPM register base address. + * @retval Signal level. + */ +static inline unsigned char DCL_CAPM_GetCRTEdge(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return (capmx->ECSEQR.BIT.crt_edge); +} + +/** + * @brief Get next ECR number. + * @param capmx: CAPM register base address. + * @retval Next ECR number. + */ +static inline unsigned char DCL_CAPM_GetNextECRNum(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return (capmx->ECSEQR.BIT.nxtldecr); +} + +/** + * @brief Set capture rising edge register. + * @param capmx: CAPM register base address. + * @param capReg: Capture rising edge register. + * Input argument value: 0(CapReg 1),1(CapReg 2),2(CapReg 3),3(CapReg 4).Register set value:1,4,16,64. + * @retval None. + */ +static inline void DCL_CAPM_RisingCap(CAPM_RegStruct * const capmx, unsigned int capReg) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + if (capReg > CAPM_MAX_CAP_REG_NUM) { + return; + } + capmx->CCR1.reg |= (unsigned int)((1 << capReg) * (1 << capReg)); + return; +} + +/** + * @brief Set capture falling edge register. + * @param capmx: CAPM register base address. + * @param capReg: Capture falling edge register. + * Input argument value:0(CapReg 1),1(CapReg 2),2(CapReg 3),3(CapReg 4).Register set value:1,4,16,64. + * @retval None. + */ +static inline void DCL_CAPM_FallingCap(CAPM_RegStruct * const capmx, unsigned int capReg) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + if (capReg > CAPM_MAX_CAP_REG_NUM) { + return; + } + capmx->CCR1.reg &= (~(unsigned int)((1 << capReg) * (1 << capReg))); + return; +} + +/** + * @brief Enable capture register reset TSR function. + * @param capmx: CAPM register base address. + * @param capReg: Reset TSR's capture register. + * Input argument value:0(CapReg 1),1(CapReg 2),2(CapReg 3),3(CapReg 4).Register set value:2,8,32,128. + * @retval None. + */ +static inline void DCL_CAPM_EnableCapReset(CAPM_RegStruct * const capmx, unsigned int capReg) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + if (capReg > CAPM_MAX_CAP_REG_NUM) { + return; + } + capmx->CCR1.reg |= (unsigned int)((CAPM_BIT_SHIFT_TWO * (1 << capReg) * (1 << capReg))); + return; +} + +/** + * @brief Disable capture register reset TSR function. + * @param capmx: CAPM register base address. + * @param capReg: Non-reset TSR's capture register. + * Input argument value:0(CapReg 1),1(CapReg 2),2(CapReg 3),3(CapReg 4).Register set value:2,8,32,128. + * @retval None. + */ +static inline void DCL_CAPM_DisableCapReset(CAPM_RegStruct * const capmx, unsigned int capReg) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + if (capReg > CAPM_MAX_CAP_REG_NUM) { + return; + } + capmx->CCR1.reg &= ~(unsigned int)(CAPM_BIT_SHIFT_TWO * (1 << capReg) * (1 << capReg)); + return; +} + +/** + * @brief Set ECR1 capture falling edge. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ECR1FallingCap(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.evt1pol = CAPM_FALLING_EDGE; + return; +} + +/** + * @brief Set ECR1 capture rising edge. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ECR1RisingCap(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.evt1pol = CAPM_RISING_EDGE; + return; +} + +/** + * @brief Enable ECR1 reset after each capture action. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableECR1CapReset(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.evt1rst = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable ECR1 reset after each capture action. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableECR1CapReset(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.evt1rst = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Set ECR2 capture falling edge. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ECR2FallingCap(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.evt2pol = CAPM_FALLING_EDGE; + return; +} + +/** + * @brief Set ECR2 capture rising edge. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ECR2RisingCap(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.evt2pol = CAPM_RISING_EDGE; + return; +} + +/** + * @brief Enable ECR2 reset after each capture action. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableECR2CapReset(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.evt2rst = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable ECR2 reset after each capture action. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableECR2CapReset(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.evt2rst = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Set ECR3 capture falling edge. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ECR3FallingCap(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.evt3pol = CAPM_FALLING_EDGE; + return; +} + +/** + * @brief Set ECR3 capture rising edge. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ECR3RisingCap(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.evt3pol = CAPM_RISING_EDGE; + return; +} + +/** + * @brief Enable ECR3 reset after each capture action. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableECR3CapReset(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.evt3rst = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable ECR3 reset after each capture action. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableECR3CapReset(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.evt3rst = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Set ECR3 capture Falling edge. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ECR4FallingCap(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.evt4pol = CAPM_FALLING_EDGE; + return; +} + +/** + * @brief Set ECR3 capture Rising edge. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ECR4RisingCap(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.evt4pol = CAPM_RISING_EDGE; + return; +} + +/** + * @brief Enable ECR4 after each capture action. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableECR4CapReset(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.evt4rst = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable ECR4 after each capture action. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableECR4CapReset(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.evt4rst = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Enable capture register load. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableCapRegLoad(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.ecrlden = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable capture register load. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableCapRegLoad(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.ecrlden = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Set the capture register's number which trggle DMA interrupt. + * @param capmx: CAPM register base address. + * @param capNum: Capture register number. + * @retval None. + */ +static inline void DCL_CAPM_SetDMATriggleReg(CAPM_RegStruct * const capmx, CampConfigCapRegNum capNum) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + CAPM_PARAM_CHECK_NO_RET(capNum >= 0); + CAPM_PARAM_CHECK_NO_RET(capNum < CAPM_MAX_CAP_REG_NUM); + capmx->CCR1.BIT.dmaevt_sel = capNum; + return; +} + +/** + * @brief Set prescale value. + * @param base: CAPM register base address. + * @param preScale PreScale value. Range: 0, 1, 2, 3 ... 127. + * @retval None. + */ +static inline void DCL_CAPM_SetPreScale(CAPM_RegStruct * const capmx, unsigned short preScale) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + CAPM_PARAM_CHECK_NO_RET(preScale <= CAPM_MAX_PRESCALE); + capmx->CCR1.BIT.psc = preScale; + return; +} + +/** + * @brief Set count edge type. + * @param capmx: CAPM register base address. + * @param countType: Count edge type. + * @retval None. + */ +static inline void DCL_CAPM_SetCountType(CAPM_RegStruct * const capmx, CAPM_CountType countType) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR1.BIT.cnt_edge_sel = countType; + return; +} + +/** + * @brief Set filer value. + * @param capmx: CAPM register base address. + * @param filterValue: Filter value. Range: 0 ~ 8191. + * @retval None. + */ +static inline void DCL_CAPM_SetFilterLevel(CAPM_RegStruct * const capmx, unsigned short filterValue) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->FTCR.BIT.ft_lev = filterValue; + return; +} + +/** + * @brief Get filer value. + * @param capmx: CAPM register base address. + * @retval Filer value. + */ +static inline unsigned int DCL_CAPM_GetFilterLevel(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->FTCR.BIT.ft_lev; +} + +/** + * @brief Enable input filter. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableFilter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->FTCR.BIT.ft_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable input filter. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableFilter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->FTCR.BIT.ft_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Restart CAPM0 one-shot capture. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_RestartOneShotCap0(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.restart_capm0 = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Restart CAPM1 one-shot capture. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_RestartOneShotCap1(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.restart_capm1 = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Restart CAPM2 one-shot capture. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_RestartOneShotCap2(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.restart_capm2 = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Suspend capm0 TSR count. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_SuspendTSRCount0(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.tsr_stop_capm0 = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Resume capm0 TSR counter. + * @param capmx: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ResumeTSRCount0(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.tsr_stop_capm0 = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Suspend capm1 TSR count. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_SuspendTSRCount1(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.tsr_stop_capm1 = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Resume capm1 TSR counter. + * @param capmx: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ResumeTSRCount1(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.tsr_stop_capm1 = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Suspend capm2 TSR count. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_SuspendTSRCount2(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.tsr_stop_capm2 = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Resume capm0 TSR counter. + * @param capmx: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ResumeTSRCount2(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.tsr_stop_capm2 = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Reset capm0 TSR value. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ResetTSRCount0(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.stat_rst_capm0 = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Reset capm1 TSR value. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ResetTSRCount1(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.stat_rst_capm1 = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Reset capm2 TSR value. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ResetTSRCount2(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.stat_rst_capm2 = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Set capture mode. + * @param capmx: CAPM register base address. + * @param capMode: Capture mode. + * @retval None. + */ +static inline void DCL_CAPM_SetCapMode(CAPM_RegStruct * const capmx, CAPM_CapMode capMode) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + CAPM_PARAM_CHECK_NO_RET(capMode == CAPM_CONTINUECAP || capMode == CAPM_ONESHOTCAP); + capmx->CCR3.BIT.cap_mode = capMode; + return; +} + +/** + * @brief Set capture stop on which register's capture event. + * @param capmx: CAPM register base address. + * @param capNum: Stop capture register number. + * @retval None. + */ +static inline void DCL_CAPM_SetStopSeq(CAPM_RegStruct * const capmx, CampConfigCapRegNum capNum) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + CAPM_PARAM_CHECK_NO_RET(capNum >= 0); + CAPM_PARAM_CHECK_NO_RET(capNum < CAPM_MAX_CAP_REG_NUM); + capmx->CCR3.BIT.seq_stop = capNum; + return; +} + +/** + * @brief Enable capm0 sync input. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableSyncIn0(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->SYNC_SELR0.BIT.capm0_synci_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Enable capm1 sync input. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableSyncIn1(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->SYNC_SELR1.BIT.capm1_synci_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Enable capm2 sync input. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableSyncIn2(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->SYNC_SELR2.BIT.capm2_synci_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable capm0 sync input. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableSyncIn0(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->SYNC_SELR0.BIT.capm0_synci_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Disable capm1 sync input. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableSyncIn1(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->SYNC_SELR1.BIT.capm1_synci_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Disable capm2 sync input. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableSyncIn2(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->SYNC_SELR2.BIT.capm2_synci_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Triggle a software sync event for capm0. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_TriggleSoftSync0(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.sync_sw_capm0 = BASE_CFG_SET; + return; +} + +/** + * @brief Triggle a software sync event for capm1. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_TriggleSoftSync1(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.sync_sw_capm1 = BASE_CFG_SET; + return; +} + +/** + * @brief Triggle a software sync event for capm2. + * @param capmComm: CAPM COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_TriggleSoftSync2(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.sync_sw_capm2 = BASE_CFG_SET; + return; +} + +/** + * @brief Clear all CAPM interrupt flags. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_ClearAllInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTRAWR.reg = 0x1FF; + return; +} + +/** + * @brief Clear specific interrupt. + * @param capmx: CAPM register base address. + * @param eventNumber: Specific interrupt. + * @retval None. + */ +static inline void DCL_CAPM_ClearInter(CAPM_RegStruct * const capmx, CAPM_Interrupt eventNumber) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTRAWR.reg |= (unsigned int)eventNumber; + return; +} + +/** + * @brief Enable specific interrupt. + * @param capmx: CAPM register base address. + * @param eventNumber: Specific interrupt. + * @retval None. + */ +static inline void DCL_CAPM_EnableInter(CAPM_RegStruct * const capmx, CAPM_Interrupt eventNumber) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.reg |= (unsigned int)eventNumber; + return; +} + +/** + * @brief Disable specific interrupt. + * @param capmx: CAPM register base address. + * @param eventNumber: Specific interrupt. + * @retval None. + */ +static inline void DCL_CAPM_DisableInter(CAPM_RegStruct * const capmx, CAPM_Interrupt eventNumber) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.reg &= (~(unsigned int)eventNumber); + return; +} + +/** + * @brief Enable event1 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableEvt1Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.evt1_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable event1 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableEvt1Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.evt1_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Enable event2 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableEvt2Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.evt2_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable event2 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableEvt2Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.evt2_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Enable event3 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableEvt3Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.evt3_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable event3 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableEvt3Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.evt3_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Enable event4 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableEvt4Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.evt4_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable event4 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableEvt4Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.evt4_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Enable TSR overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableTsrovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.tsr_ovf_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable TSR overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableTsrovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.tsr_ovf_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Enable ECR overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableEcrovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.ecr_ovf_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable ECR overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableEcrovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.ecr_ovf_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Enable EAR compare match interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableEARCMPMatchInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.earcmp_match_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable EAR compare match interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableEARCMPMatchInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.earcmp_match_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Enable EAR overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableEarovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.ear_ovf_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable EAR overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableEarovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.ear_ovf_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Enable DMA overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableDmaovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.dmareq_ovf_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable DMA overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableDmaovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTENR.BIT.dmareq_ovf_en = BASE_CFG_DISABLE; + return; +} + +/** + * @brief Get all interrupt flags. + * @param capmx: CAPM register base address. + * @retval Interrupt flags. + */ +static inline unsigned int DCL_CAPM_GetInterFlag(const CAPM_RegStruct *capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + return capmx->INTFLGR.reg; +} + +/** + * @brief Inject interrupts by software. + * @param capmx: CAPM register base address. + * @param eventNumber: Inject interrupt. + * @retval None. + */ +static inline void DCL_CAPM_InjectInter(CAPM_RegStruct * const capmx, CAPM_Interrupt eventNumber) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTFLGR.reg |= (unsigned int)eventNumber; + return; +} + +/** + * @brief Inject event1 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_InjectEvt1Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTINJR.BIT.evt1_inj |= 0x01; + return; +} + +/** + * @brief Inject event2 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_InjectEvt2Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTINJR.BIT.evt2_inj |= 0x01; + return; +} + +/** + * @brief Inject event3 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_InjectEvt3Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTINJR.BIT.evt3_inj |= 0x01; + return; +} + +/** + * @brief Inject event4 interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_InjectEvt4Inter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTINJR.BIT.evt4_inj |= 0x01; + return; +} + +/** + * @brief Inject TSR overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_IngectTsrovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTINJR.BIT.tsr_ovf_inj |= 0x01; + return; +} + +/** + * @brief Inject ECR overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_InjectEcrovfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTINJR.BIT.ecr_ovf_inj |= 0x01; + return; +} + +/** + * @brief Inject EAR overflow interrupt. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_InjectEarOvfInter(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->INTINJR.BIT.ear_ovf_inj |= 0x01; + return; +} + +/** + * @brief Enable emulation stop TSR count. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_EnableEmuStopTSR(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR2.BIT.emu_stop_en = BASE_CFG_ENABLE; + return; +} + +/** + * @brief Disable emulation stop TSR count. + * @param capmx: CAPM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableEmuStopTSR(CAPM_RegStruct * const capmx) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmx)); + capmx->CCR2.BIT.emu_stop_en = BASE_CFG_DISABLE; +} + +/** + * @brief Disable TSR count stop control + * @param capmComm: CAPM_COMM register base address. + * @retval None. + */ +static inline void DCL_CAPM_DisableTSRStop(CAPM_COMM_RegStruct * const capmComm) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->CAPM_GENE_CR.BIT.tsr_stop_capm0 = BASE_CFG_DISABLE; + capmComm->CAPM_GENE_CR.BIT.tsr_stop_capm1 = BASE_CFG_DISABLE; + capmComm->CAPM_GENE_CR.BIT.tsr_stop_capm2 = BASE_CFG_DISABLE; +} + +/** + * @brief Set CAPM0 input source + * @param capmComm: CAPM_COMM register base address. + * @param src: source selection + * @retval None. + */ +static inline void DCL_CAPM_SetInputSEL0(CAPM_COMM_RegStruct * const capmComm, CAPM_InputSrc src) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->INPUT_SELR0.BIT.capm0_in_sel = src; +} + +/** + * @brief Set CAPM1 input source + * @param capmComm: CAPM_COMM register base address. + * @param src: source selection + * @retval None. + */ +static inline void DCL_CAPM_SetInputSEL1(CAPM_COMM_RegStruct * const capmComm, CAPM_InputSrc src) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->INPUT_SELR1.BIT.capm1_in_sel = src; +} + +/** + * @brief Set CAPM2 input source + * @param capmComm: CAPM_COMM register base address. + * @param src: source selection + * @retval None. + */ +static inline void DCL_CAPM_SetInputSEL2(CAPM_COMM_RegStruct * const capmComm, CAPM_InputSrc src) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + capmComm->INPUT_SELR2.BIT.capm2_in_sel = src; +} + +/** + * @brief Set CAPM0 sync input source + * @param capmComm: CAPM_COMM register base address. + * @param src: apt source selection + * @retval None. + */ +static inline void DCL_CAPM_SetSyncInput0(CAPM_COMM_RegStruct * const capmComm, CAPM_SyncSrc src) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + CAPM_PARAM_CHECK_NO_RET(src >= CAPM_SYNC_SRC_NONE); + CAPM_PARAM_CHECK_NO_RET(src <= CAPM_SYNC_SRC_APT8); + capmComm->SYNC_SELR0.BIT.capm0_sync_sel = src; +} + +/** + * @brief Set CAPM1 sync input source + * @param capmComm: CAPM_COMM register base address. + * @param src: apt source selection + * @retval None. + */ +static inline void DCL_CAPM_SetSyncInput1(CAPM_COMM_RegStruct * const capmComm, CAPM_SyncSrc src) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + CAPM_PARAM_CHECK_NO_RET(src >= CAPM_SYNC_SRC_NONE); + CAPM_PARAM_CHECK_NO_RET(src <= CAPM_SYNC_SRC_APT8); + capmComm->SYNC_SELR1.BIT.capm1_sync_sel = src; +} + +/** + * @brief Set CAPM2 sync input source + * @param capmComm: CAPM_COMM register base address. + * @param src: apt source selection + * @retval None. + */ +static inline void DCL_CAPM_SetSyncInput2(CAPM_COMM_RegStruct * const capmComm, CAPM_SyncSrc src) +{ + CAPM_ASSERT_PARAM(IsCAPMCOMMInstance(capmComm)); + CAPM_PARAM_CHECK_NO_RET(src >= CAPM_SYNC_SRC_NONE); + CAPM_PARAM_CHECK_NO_RET(src <= CAPM_SYNC_SRC_APT8); + capmComm->SYNC_SELR2.BIT.capm2_sync_sel = src; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/capm/src/capm.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/capm/src/capm.c new file mode 100644 index 00000000..578969a0 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/capm/src/capm.c @@ -0,0 +1,439 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file capm.c + * @author MCU Driver Team. + * @brief CAPM HAL level module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the CAPM. + * + Initialization and de-initialization functions. + * + Get CAPM ECR value and next load ECR number. + * + Get CAPM CRT edge. + * + Enable/Disable CAPM sync function. + * + Get/Set CAPM sync phase(TSR) value. + * + Config CAPM interrupt function. + */ +#include "capm.h" +#include "assert.h" +#include "interrupt.h" + +/** + * @brief Config whether the ECR capture event need reset TSR. + * @param handle: CAPM handle. + * @param number: ECR number. + * @retval None. + */ +static inline void CAPM_SetCapReset(CAPM_Handle *handle, unsigned int number) +{ + CAPM_ASSERT_PARAM(handle != NULL); + CAPM_ASSERT_PARAM(IsCAPMInstance(handle->baseAddress)); + CAPM_PARAM_CHECK_NO_RET(number <= CAPM_MAX_CAP_REG_NUM); + if (handle->capRegConfig[number].regReset == CAPM_RESET) { + /* Enable ECR capture event need reset TSR */ + DCL_CAPM_EnableCapReset(handle->baseAddress, number); + } else { + /* Disable ECR capture event need reset TSR */ + DCL_CAPM_DisableCapReset(handle->baseAddress, number); + } + return; +} + +/** + * @brief Config triggle ECR capture event source. + * @param handle: CAPM handle. + * @retval BASE status type: BASE_STATUS_OK, BASE_STATUS_ERROR. + */ +static BASE_StatusType CAPM_SetRegCaptureEvent(CAPM_Handle *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + CAPM_PARAM_CHECK_WITH_RET(handle->useCapNum <= CAPM_MAX_CAP_REG_NUM, BASE_STATUS_ERROR); + unsigned int i; + for (i = 0; i < handle->useCapNum; i++) { + if (handle->capRegConfig[i].capEvent == CAPM_RISING) { /* CAPM rising capture. */ + DCL_CAPM_RisingCap(handle->baseAddress, i); + CAPM_SetCapReset(handle, i); + } else if (handle->capRegConfig[i].capEvent == CAPM_FALLING) { /* CAPM falling capture. */ + DCL_CAPM_FallingCap(handle->baseAddress, i); + CAPM_SetCapReset(handle, i); + } else { + return BASE_STATUS_ERROR; + } + } + return BASE_STATUS_OK; +} + +/** + * @brief Set deburr number. + * @param handle: CAPM handle. + * @retval BASE status type: BASE_STATUS_OK, BASE_STATUS_ERROR. + */ +static BASE_StatusType CAPM_SetDeburrNum(CAPM_Handle *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + if ((handle->deburrNum > 0) && (handle->deburrNum <= CAPM_MAX_FILTER_LEVEL)) { + DCL_CAPM_EnableFilter(handle->baseAddress); + DCL_CAPM_SetFilterLevel(handle->baseAddress, handle->deburrNum - 1); + } else { + /* deburrNum = 0: Disable filter. */ + DCL_CAPM_DisableFilter(handle->baseAddress); + } + return BASE_STATUS_OK; +} + +/** + * @brief IRQ Handler + * @param handle: CAPM handle. + * @retval None + */ +void HAL_CAPM_IrqHandler(void *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + CAPM_Handle *useHandle = (CAPM_Handle *)handle; + CAPM_ASSERT_PARAM(IsCAPMInstance(useHandle->baseAddress)); + if (useHandle->userCallBack.EvtFinishCallback != NULL) { + /* Get interrupt flag. */ + unsigned int intMask = DCL_CAPM_GetInterFlag(useHandle->baseAddress); + unsigned int intBit; + for (unsigned int i = 0; i <= CAPM_INTDMAREQOVF; i++) { + if (((intMask >> i) & 0x1) == 0x1) { + intBit = (intMask & (0x1 << i)); + /* Clear interrupt. */ + DCL_CAPM_ClearInter(useHandle->baseAddress, intBit); + useHandle->userCallBack.EvtFinishCallback(useHandle, i); + } + } + } + return; +} + +/** + * @brief Register IRQ callback functions + * @param capmHandle: CAPM handle. + * @param typeID: callback function type ID. + * @param pCallback: pointer of callback function. + * @retval None + */ +void HAL_CAPM_RegisterCallback(CAPM_Handle *capmHandle, CAPM_CallbackFuncType typeID, CAPM_CallbackType pCallback) +{ + CAPM_ASSERT_PARAM(capmHandle != NULL); + CAPM_ASSERT_PARAM(IsCAPMInstance(capmHandle->baseAddress)); + CAPM_ASSERT_PARAM(pCallback != NULL); + + switch (typeID) { + case CAPM_EVT_FINISH: + capmHandle->userCallBack.EvtFinishCallback = (EvtCallbackType)pCallback; /**< Event finish callback. */ + break; + case CAPM_DMA_ERROR: + capmHandle->userCallBack.DmaErrorCallback = pCallback; /**< DMA error callback function. */ + break; + case CAPM_DMA_FINISH: + capmHandle->userCallBack.DmaFinishCallback = pCallback; /**< DMA finish callback function. */ + default: + return; + } +} + +/** + * @brief DMA error interrupt service routine. + * @param handle: CAPM handle. + * @retval None. + */ +static void CAPM_DmaErrorIRQService(void *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + + CAPM_Handle *useHandle = (CAPM_Handle *)handle; + if (useHandle->userCallBack.DmaErrorCallback != NULL) { /* if callback not equal to null */ + useHandle->userCallBack.DmaErrorCallback(useHandle); + } + return; +} + +/** + * @brief DMA finish interrupt service routine. + * @param handle: CAPM handle. + * @retval None. + */ +static void CAPM_DmaFinishIRQService(void *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + + CAPM_Handle *useHandle = (CAPM_Handle *)handle; + if (useHandle->userCallBack.DmaFinishCallback != NULL) { /* if callback not equal to null */ + useHandle->userCallBack.DmaFinishCallback(useHandle); + } + return; +} + +/** + * @brief Get camp number. + * @param handle: CAPM handle. + * @retval camp number. + */ +static unsigned char CAPM_GetCapmNumber(CAPM_Handle *capmHandle) +{ + CAPM_ASSERT_PARAM(IsCAPMInstance(capmHandle->baseAddress)); + if (capmHandle->baseAddress == CAPM0_BASE) { + return CAPM_NUM_0; /* capm0 */ + } else if (capmHandle->baseAddress == CAPM1_BASE) { + return CAPM_NUM_1; /* capm1 */ + } else if (capmHandle->baseAddress == CAPM2_BASE) { + return CAPM_NUM_2; /* capm2 */ + } else { + return CAPM_NUM_0; + } +} + +/** + * @brief Setting camp sync. + * @param capmHandle: CAPM handle. + * @param capmNum: capm number. + * @retval camp number. + */ +static void CAPM_SyncSetByNumber(CAPM_Handle *capmHandle, unsigned char capmNum) +{ + switch (capmNum) { + case CAPM_NUM_0: + DCL_CAPM_EnableSyncIn0(CAPM_COMM); /* enable capm0 sync */ + DCL_CAPM_SetSyncInput0(CAPM_COMM, capmHandle->syncSrc); + break; + case CAPM_NUM_1: + DCL_CAPM_EnableSyncIn1(CAPM_COMM); /* enable capm1 sync */ + DCL_CAPM_SetSyncInput1(CAPM_COMM, capmHandle->syncSrc); + break; + case CAPM_NUM_2: + DCL_CAPM_EnableSyncIn2(CAPM_COMM); /* enable capm2 sync */ + DCL_CAPM_SetSyncInput2(CAPM_COMM, capmHandle->syncSrc); + break; + default: + break; + } +} + +/** + * @brief Disable sync by capm number. + * @param capmNum: CAPM number. + * @retval None. + */ +static void CAPM_SyncDisableByNumber(unsigned char capmNum) +{ + switch (capmNum) { + case CAPM_NUM_0: + DCL_CAPM_DisableSyncIn0(CAPM_COMM); /* disable capm0 sync */ + break; + case CAPM_NUM_1: + DCL_CAPM_DisableSyncIn1(CAPM_COMM); /* disable camp1 sync */ + break; + case CAPM_NUM_2: + DCL_CAPM_DisableSyncIn2(CAPM_COMM); /* disable capm2 sync */ + break; + default: + break; + } +} + +/** + * @brief Capm sync initialize. + * @param capmHandle: CAPM handle. + * @retval None. + */ +static void CAPM_SyncInit(CAPM_Handle *capmHandle) +{ + unsigned char capmNum; + CAPM_ASSERT_PARAM(capmHandle != NULL); + capmNum = CAPM_GetCapmNumber(capmHandle); + if (capmHandle->enableSync == true) { /* if enable sync */ + CAPM_SyncSetByNumber(capmHandle, capmNum); + } else { /* if do not enable sync */ + CAPM_SyncDisableByNumber(capmNum); + } +} + +/** + * @brief Capm select input. + * @param capmHandle: CAPM handle. + * @retval None. + */ +static BASE_StatusType CAPM_InputSel(CAPM_Handle *capmHandle) +{ + CAPM_ASSERT_PARAM(capmHandle != NULL); + if (capmHandle->baseAddress == CAPM0_BASE) { + DCL_CAPM_SetInputSEL0(CAPM_COMM, capmHandle->inputSrc); /* set capm0 input selection */ + } else if (capmHandle->baseAddress == CAPM1_BASE) { + DCL_CAPM_SetInputSEL1(CAPM_COMM, capmHandle->inputSrc); /* set capm1 input selection */ + } else if (capmHandle->baseAddress == CAPM2_BASE) { + DCL_CAPM_SetInputSEL2(CAPM_COMM, capmHandle->inputSrc); /* set capm2 input selection */ + } else { /* error value */ + return BASE_STATUS_ERROR; + } + + return BASE_STATUS_OK; +} + +/** + * @brief CAPM initialize function. + * @param handle: CAPM handle. + * @retval BASE status type: BASE_STATUS_OK, BASE_STATUS_ERROR. + */ +BASE_StatusType HAL_CAPM_Init(CAPM_Handle *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + CAPM_ASSERT_PARAM(IsCAPMInstance(handle->baseAddress)); + CAPM_PARAM_CHECK_WITH_RET(handle->useCapNum <= CAPM_MAX_CAP_REG_NUM, BASE_STATUS_ERROR); + CAPM_PARAM_CHECK_WITH_RET(handle->preScale <= CAPM_MAX_PRESCALE, BASE_STATUS_ERROR); + /* Init CAPM TSR division. */ + DCL_CAPM_SetTSRDiv(handle->baseAddress, handle->tscntDiv); + /* Init CAPM capture mode. */ + DCL_CAPM_SetCapMode(handle->baseAddress, handle->capMode); + DCL_CAPM_SetStopSeq(handle->baseAddress, handle->useCapNum - 1); + CAPM_SetDeburrNum(handle); + /* Init CAPM prescale. */ + DCL_CAPM_SetPreScale(handle->baseAddress, handle->preScale); + DCL_CAPM_SetDMATriggleReg(handle->baseAddress, handle->useCapNum - 1); + CAPM_SetRegCaptureEvent(handle); + CAPM_SyncInit(handle); + if (CAPM_InputSel(handle) == BASE_STATUS_ERROR) { + return BASE_STATUS_ERROR; + } + DCL_CAPM_DisableTSRStop((CAPM_COMM_RegStruct *) CAPM_COMM); + /* Enable CAPM interrupt. */ + DCL_CAPM_EnableInter(handle->baseAddress, handle->enableIntFlags); + DCL_CAPM_EnableCapRegLoad(handle->baseAddress); + + return BASE_STATUS_OK; +} + +/** + * @brief CAPM deinitialize function. + * @param handle: CAPM handle. + * @retval BASE status type: BASE_STATUS_OK, BASE_STATUS_ERROR. + */ +BASE_StatusType HAL_CAPM_DeInit(CAPM_Handle *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + CAPM_ASSERT_PARAM(IsCAPMInstance(handle->baseAddress)); + /* Clear interrupt callback function. */ + handle->userCallBack.EvtFinishCallback = NULL; + handle->userCallBack.DmaErrorCallback = NULL; + handle->userCallBack.DmaFinishCallback = NULL; + + /* Clear enable operations. */ + DCL_CAPM_DisableInter(handle->baseAddress, handle->enableIntFlags); + DCL_CAPM_DisableCapRegLoad(handle->baseAddress); + return BASE_STATUS_OK; +} + +/** + * @brief Get ECR value. + * @param handle: CAPM handle. + * @param ecrNum: ECR number. + * @retval ECR value. + */ +unsigned int HAL_CAPM_GetECRValue(CAPM_Handle *handle, CAPM_ECRNum ecrNum) +{ + CAPM_ASSERT_PARAM(handle != NULL); + CAPM_PARAM_CHECK_WITH_RET(ecrNum > 0, BASE_STATUS_ERROR); + CAPM_PARAM_CHECK_WITH_RET(ecrNum < CAPM_MAX_CAP_REG_NUM, BASE_STATUS_ERROR); + switch (ecrNum) { + case CAPM_ECR_NUM1: + return DCL_CAPM_GetECR1(handle->baseAddress); /* Get ECR1 value. */ + case CAPM_ECR_NUM2: + return DCL_CAPM_GetECR2(handle->baseAddress); /* Get ECR2 value. */ + case CAPM_ECR_NUM3: + return DCL_CAPM_GetECR3(handle->baseAddress); /* Get ECR3 value. */ + case CAPM_ECR_NUM4: + return DCL_CAPM_GetECR4(handle->baseAddress); /* Get ECR4 value. */ + default: + return BASE_STATUS_OK; + } +} + +/** + * @brief Get current signal level. + * @param handle: CAPM handle. + * @retval Current signal level: CAPM_LOW_LEVEL, CAPM_UP_EDGE, CAPM_DOWN_EDGE, CAPM_HIGH_LEVEL. + */ +unsigned char HAL_CAPM_GetCrtEdge(CAPM_Handle *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + return DCL_CAPM_GetCRTEdge(handle->baseAddress); +} + +/** + * @brief Get the number of next ECR to be loaded. + * @param handle: CAPM handle. + * @retval Next ECR number:NEXT_LOAD_ECR1, NEXT_LOAD_ECR2, NEXT_LOAD_ECR3, NEXT_LOAD_ECR4. + */ +unsigned char HAL_CAPM_GetNextLoadECRNum(CAPM_Handle *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + return DCL_CAPM_GetNextECRNum(handle->baseAddress); +} + +/** + * @brief Set sync phase value. + * @param handle: CAPM handle. + * @param phase: Default sync phase value. + * @retval None. + */ +void HAL_CAPM_SetSyncPhs(CAPM_Handle *handle, unsigned int phase) +{ + CAPM_ASSERT_PARAM(handle != NULL); + DCL_CAPM_SetSyncPhase(handle->baseAddress, phase); + return; +} + +/** + * @brief Get sync phase value. + * @param handle: CAPM handle. + * @retval Sync phase value. + */ +unsigned int HAL_CAPM_GetSyncPhs(CAPM_Handle *handle) +{ + CAPM_ASSERT_PARAM(handle != NULL); + return DCL_CAPM_GetSyncPhase(handle->baseAddress); +} + +/** + * @brief Get ECR register value by DMA. + * @param handle: CAPM handle. + * @param distAddr: Distance address. + * @param dataLength: CAPM handle. + * @retval BASE status type: BASE_STATUS_OK, BASE_STATUS_ERROR. + */ +BASE_StatusType HAL_CAPM_GetECRValueDMA(CAPM_Handle *handle, unsigned int *distAddr, + unsigned int dataLength) +{ + CAPM_ASSERT_PARAM(handle != NULL); + CAPM_ASSERT_PARAM(handle->dmaHandle != NULL); + CAPM_ASSERT_PARAM(distAddr != NULL); + CAPM_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + unsigned int channel; + channel = handle->dmaChannel; + if (channel >= CHANNEL_MAX_NUM) { + return BASE_STATUS_ERROR; + } + /* Config DMA callback. */ + handle->dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelFinishCallBack = CAPM_DmaFinishIRQService; + handle->dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelErrorCallBack = CAPM_DmaErrorIRQService; + /* Get ECR value by DMA. */ + if (HAL_DMA_StartIT(handle->dmaHandle, (unsigned int)(uintptr_t)(void *)&(handle->baseAddress->ECR1), + (unsigned int)(uintptr_t)(void *)distAddr, dataLength, channel) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/cfd/common/inc/cfd.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/cfd/common/inc/cfd.h new file mode 100644 index 00000000..c697a72f --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/cfd/common/inc/cfd.h @@ -0,0 +1,111 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cfd.h + * @author MCU Driver Team + * @brief CFD module driver. + * @details This file provides firmware CFD Handle structure and Functions + * prototypes to manage the following functionalities of the CFD module. + * + Initialization and de-initialization functions + * + config the register of CFD module + */ + +#ifndef McuMagicTag_CFD_H +#define McuMagicTag_CFD_H + +/* Includes ------------------------------------------------------------------ */ +#include "cfd_ip.h" + +/* Macro definitions ---------------------------------------------------------*/ +/** + * @defgroup CFD CFD + * @brief CFD module. + * @{ + */ + +/** + * @defgroup CFD_Common CFD Common + * @brief CFD common external module. + * @{ + */ + +/** + * @defgroup CFD_Handle_Definition CFD Handle Definition + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ + +/** + * @brief CFD module configurable item. + */ +typedef enum { + CFD_CFG_UPPER_BOUND = 0x00000001U, + CFD_CFG_INT_TYPE = 0x00000002U, + CFD_CFG_MAX +} CFD_CFG_TYPE; + +/** + * @brief CFD handle. + */ +typedef struct _CFD_Handle { + CFD_RegStruct *baseAddress; /**< CFD registers base address. */ + unsigned char upperBound; /**< Upper boundary. */ + unsigned int interruptType; /**< Enabled interrupt type. */ + CFD_UserCallBack userCallBack; /**< CFD Interrupt callback functions.*/ + CFD_ExtendHandle handleEx; /**< CFD extend parameter */ +} CFD_Handle; + +/** + * @brief Typedef callback function of CFD + */ +typedef void (*CFD_CallBackFuncType)(void *handle); + +/** + * @} + */ + +/** + * @defgroup CFD_API_Declaration CFD HAL API + * @{ + */ + +/* Hardware abstraction layer functions -------------------------------------------------------- */ +BASE_StatusType HAL_CFD_Init(CFD_Handle *handle); +BASE_StatusType HAL_CFD_DeInit(CFD_Handle *handle); +BASE_StatusType CFD_RspInit(CFD_Handle *handle); +BASE_StatusType CFD_RspDeInit(CFD_Handle *handle); +BASE_StatusType HAL_CFD_Config(CFD_Handle *handle, CFD_CFG_TYPE cfgType); +void HAL_CFD_GetConfig(CFD_Handle *handle); +void HAL_CFD_Start(CFD_Handle *handle); +void HAL_CFD_Stop(CFD_Handle *handle); +BASE_StatusType HAL_CFD_RegisterCallback(CFD_Handle *handle, CFD_Interrupt_Type type, CFD_CallBackFuncType callback); +void HAL_CFD_IrqHandler(void *handle); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_UART_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/cfd/inc/cfd_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/cfd/inc/cfd_ip.h new file mode 100644 index 00000000..9ec8bb26 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/cfd/inc/cfd_ip.h @@ -0,0 +1,357 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cfd_ip.h + * @author MCU Driver Team + * @brief CFD module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the CFD. + * + Register Struct of CFD + * + CFD Register Map struct + * + Direct Configuration Layer functions of CFD + */ + +#ifndef McuMagicTag_CFD_IP_H +#define McuMagicTag_CFD_IP_H + +/* Includes ------------------------------------------------------------------ */ +#include "baseinc.h" +/* Macro definitions ---------------------------------------------------------*/ +#ifdef CFD_PARAM_CHECK + #define CFD_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM + #define CFD_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET + #define CFD_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else + #define CFD_ASSERT_PARAM(para) ((void)0U) + #define CFD_PARAM_CHECK_NO_RET(para) ((void)0U) + #define CFD_PARAM_CHECK_WITH_RET(param, ret) ((void)0U) +#endif +/** + * @addtogroup CFD + * @{ + */ + +/** + * @defgroup CFD_IP + * @{ + */ + +/** + * @defgroup CFD_Param_Def CFD Parameters Definition + * @brief Description of CFD configuration parameters. + * @{ + */ + +/* Typedef definitions ------------------------------------------------------- */ +/** + * @brief The CFD module interrupt type mask. + */ +typedef enum { + CFD_INT_CHECK_END_MASK = 0x00000001U, + CFD_INT_PLL_REF_CLOCK_STOP_MASK = 0x00000002U, + CFD_INT_MAX_MASK +} CFD_Interrupt_Type; + +/** + * @} + */ + +/** + * @defgroup CFD_Reg_Def CFD Register Definition + * @brief Description CFD register mapping structure. + * @{ + */ + +/** + * @brief CFD version registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int month_day : 16; /**< Month and day. */ + unsigned int year : 8; /**< Year. */ + unsigned int release_substep : 1; /**< Version information. */ + unsigned int release_step : 1; /**< Version information. */ + unsigned int release_ver : 1; /**< Version information. */ + unsigned int reserved0 : 5; + } BIT; +} volatile CFDVER_Reg; + +/** + * @brief CFD control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfden : 1; /**< CFD enable or disable. */ + unsigned int reserved0 : 31; + } BIT; +} volatile CFDCTRL_Reg; + +/** + * @brief CFD check window upper bound registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfdwdoh : 8; /**< CFD check window upper bound value. */ + unsigned int reserved0 : 24; + } BIT; +} volatile CFDWDOH_Reg; + +/** + * @brief CFD count locked value registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cfdcnt_lock : 8; /**< CFD count locked value */ + unsigned int reserved0 : 24; + } BIT; +} volatile CFDCNTLOCK_Reg; + +/** + * @brief CFD interrupt enable registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int chk_end_en : 1; /**< CFD check end interrupt enable. */ + unsigned int clk_fail_en : 1; /**< CFD clock failure interrupt enable. */ + unsigned int reserved0 : 30; + } BIT; +} volatile CFDINTENA_Reg; + +/** + * @brief CFD interrupt status registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int chk_end_int : 1; /**< CFD check end interrupt status. */ + unsigned int clk_fail_int : 1; /**< CFD clock failure interrupt status. */ + unsigned int reserved0 : 30; + } BIT; +} volatile CFDINTSTS_Reg; + +/** + * @brief CFD initial interrupt registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int chk_end_raw : 1; /**< CFD check end initial interrupt. */ + unsigned int clk_fail_raw : 1; /**< CFD clock failure initial interrupt. */ + unsigned int reserved0 : 30; + } BIT; +} volatile CFDINTRAW_Reg; + +/** + * @brief CFD interrupt injection registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int chk_end_inj : 1; /**< CFD check end interrupt injection. */ + unsigned int clk_fail_inj : 1; /**< CFD clock failure interrupt injection. */ + unsigned int reserved0 : 30; + } BIT; +} volatile CFDINTINJ_Reg; + +/** + * @brief CFD interrupt callback functions. + * + */ +typedef struct { + void (*PllClockStopCallback)(void *handle); /**< Pll clock stop callback function. */ + void (*CheckEndCallback)(void *handle); /**< End of each check callback function. */ +} CFD_UserCallBack; + +/** + * @brief CFD extend handle. + */ +typedef struct _CFD_ExtendeHandle { +} CFD_ExtendHandle; + + +/** + * @brief CFD register mapping structure. + */ +typedef struct { + CFDVER_Reg CFDVER; /**< CFD version register, offset address: 0x0000. */ + CFDCTRL_Reg CFDCTRL; /**< CFD control register, offset address: 0x0004. */ + CFDWDOH_Reg CFDWDOH; /**< CFD check window upper bound register, offset address: 0x0008. */ + CFDCNTLOCK_Reg CFDCNTLOCK; /**< CFD count locked value register, offset address: 0x000C. */ + CFDINTENA_Reg CFDINTENA; /**< CFD interrupt enable register, offset address: 0x0010. */ + CFDINTSTS_Reg CFDINTSTS; /**< CFD interrupt status register, offset address: 0x0014. */ + CFDINTRAW_Reg CFDINTRAW; /**< CFD initial interrupt register, offset address: 0x0018. */ + CFDINTINJ_Reg CFDINTINJ; /**< CFD interrupt injection register, offset address: 0x001C. */ +} volatile CFD_RegStruct; + +/** + * @} + */ + +/** + * @brief Enable CFD module. + * @param cfdx CFD register base address. + * @retval None. + */ +static inline void DCL_CFD_Enable(CFD_RegStruct *cfdx) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + cfdx->CFDCTRL.BIT.cfden = BASE_CFG_ENABLE; +} + +/** + * @brief Disable CFD module. + * @param cfdx CFD register base address. + * @retval None. + */ +static inline void DCL_CFD_Disable(CFD_RegStruct *cfdx) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + cfdx->CFDCTRL.BIT.cfden = BASE_CFG_DISABLE; +} + +/** + * @brief Sets the upper boundary of the detection window. + * @param cfdx CFD register base address. + * @param value The value of the upper bound. + * @retval None. + */ +static inline void DCL_CFD_SetWindowUpperBound(CFD_RegStruct *cfdx, unsigned char value) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + cfdx->CFDWDOH.BIT.cfdwdoh = value; +} + +/** + * @brief Gets the upper boundary of the detection window. + * @param cfdx CFD register base address. + * @retval The value of the upper bound. + */ +static inline unsigned char DCL_CFD_GetWindowUpperBound(CFD_RegStruct *cfdx) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + return cfdx->CFDWDOH.BIT.cfdwdoh; +} + +/** + * @brief Internal counter count latch value. + * @param cfdx CFD register base address. + * @retval unsigned char. latch value. + */ +static inline unsigned char DCL_CFD_GetCntValue(CFD_RegStruct *cfdx) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + return cfdx->CFDCNTLOCK.BIT.cfdcnt_lock; +} + +/** + * @brief Enables the specified type of interrupt. + * @param cfdx CFD register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CFD_EnableInterrupt(CFD_RegStruct *cfdx, CFD_Interrupt_Type type) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + CFD_PARAM_CHECK_NO_RET(type == CFD_INT_CHECK_END_MASK || \ + type == CFD_INT_PLL_REF_CLOCK_STOP_MASK); + cfdx->CFDINTENA.reg |= type; +} + +/** + * @brief Disables the specified type of interrupt. + * @param cfdx CFD register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CFD_DisableInterrupt(CFD_RegStruct *cfdx, CFD_Interrupt_Type type) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + CFD_PARAM_CHECK_NO_RET(type == CFD_INT_CHECK_END_MASK || \ + type == CFD_INT_PLL_REF_CLOCK_STOP_MASK); + cfdx->CFDINTENA.reg &= (~type); +} + +/** + * @brief Check whether the specified interrupt is triggered. + * @param cfdx CFD register base address. + * @param type Mask of the interrupt type. + * @retval bool. + */ +static inline bool DCL_CFD_GetInterruptStatus(CFD_RegStruct *cfdx, CFD_Interrupt_Type type) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + CFD_PARAM_CHECK_WITH_RET(type == CFD_INT_CHECK_END_MASK || \ + type == CFD_INT_PLL_REF_CLOCK_STOP_MASK, false); + return (cfdx->CFDINTSTS.reg & type) == 0 ? false : true; +} + +/** + * @brief Clears interrupts of the specified type. + * @param cfdx CFD register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CFD_ClearInterrupt(CFD_RegStruct *cfdx, CFD_Interrupt_Type type) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + CFD_PARAM_CHECK_NO_RET(type == CFD_INT_CHECK_END_MASK || \ + type == CFD_INT_PLL_REF_CLOCK_STOP_MASK); + cfdx->CFDINTRAW.reg |= type; +} + +/** + * @brief Injects interrupts of the specified type. + * @param cfdx CFD register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CFD_EnableInterruptInject(CFD_RegStruct *cfdx, CFD_Interrupt_Type type) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + CFD_PARAM_CHECK_NO_RET(type == CFD_INT_CHECK_END_MASK || \ + type == CFD_INT_PLL_REF_CLOCK_STOP_MASK); + cfdx->CFDINTINJ.reg |= type; +} + +/** + * @brief Stop injecting interrupts of a specified type. + * @param cfdx CFD register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CFD_DisableInterruptInject(CFD_RegStruct *cfdx, CFD_Interrupt_Type type) +{ + CFD_ASSERT_PARAM(IsCFDInstance(cfdx)); + CFD_PARAM_CHECK_NO_RET(type == CFD_INT_CHECK_END_MASK || \ + type == CFD_INT_PLL_REF_CLOCK_STOP_MASK); + cfdx->CFDINTINJ.reg &= (~type); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_CFD_IP_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/cfd/src/cfd.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/cfd/src/cfd.c new file mode 100644 index 00000000..a24298b1 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/cfd/src/cfd.c @@ -0,0 +1,182 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cfd.c + * @author MCU Driver Team + * @brief CFD module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the CFD. + * + Initialization and de-initialization functions. + * + Config the register of cfd. + * + Interrupt callback function and user registration function. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "cfd.h" + +/** + * @brief Perform initial configuration based on the handle. + * @param handle CFD handle. + * @retval @ref BASE_StatusType. + */ +BASE_StatusType HAL_CFD_Init(CFD_Handle *handle) +{ + CFD_ASSERT_PARAM(handle != NULL); + CFD_ASSERT_PARAM(IsCFDInstance(handle->baseAddress)); + /* Init CFD upperBound and interruptType. */ + handle->baseAddress->CFDWDOH.BIT.cfdwdoh = handle->upperBound; + handle->baseAddress->CFDINTENA.reg = handle->interruptType; + + return BASE_STATUS_OK; +} + +/** + * @brief Deinitialize configurations based on the handle. + * @param handle CFD handle. + * @retval @ref BASE_StatusType. + */ +BASE_StatusType HAL_CFD_DeInit(CFD_Handle *handle) +{ + CFD_ASSERT_PARAM(handle != NULL); + CFD_ASSERT_PARAM(IsCFDInstance(handle->baseAddress)); + /* Clear interrupt callback function. */ + handle->userCallBack.PllClockStopCallback = NULL; + handle->userCallBack.CheckEndCallback = NULL; + /* Clear register value. */ + handle->baseAddress->CFDINTENA.reg = BASE_CFG_DISABLE; + return BASE_STATUS_OK; +} + +/** + * @brief Set this parameter based on the configuration item parameters. + * @param handle CFD handle. + * @param cfgType Configurable item. @ref CFD_CFG_TYPE. + * @retval @ref BASE_StatusType. + */ +BASE_StatusType HAL_CFD_Config(CFD_Handle *handle, CFD_CFG_TYPE cfgType) +{ + CFD_ASSERT_PARAM(handle != NULL); + CFD_ASSERT_PARAM(IsCFDInstance(handle->baseAddress)); + /* CFD config type. */ + switch (cfgType) { + case CFD_CFG_UPPER_BOUND: /* Config upperbound. */ + handle->baseAddress->CFDWDOH.BIT.cfdwdoh = handle->upperBound; + break; + case CFD_CFG_INT_TYPE: /* Config interrupt type. */ + handle->baseAddress->CFDINTENA.reg = handle->interruptType; + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief Reads the register configuration value to the handle. + * @param handle CFD handle. + * @retval None. + */ +void HAL_CFD_GetConfig(CFD_Handle *handle) +{ + CFD_ASSERT_PARAM(handle != NULL); + CFD_ASSERT_PARAM(IsCFDInstance(handle->baseAddress)); + + handle->upperBound = handle->baseAddress->CFDWDOH.BIT.cfdwdoh; + handle->interruptType = handle->baseAddress->CFDINTENA.reg; +} + +/** + * @brief Start CFD Module. + * @param handle CFD handle. + * @retval None. + */ +void HAL_CFD_Start(CFD_Handle *handle) +{ + CFD_ASSERT_PARAM(handle != NULL); + CFD_ASSERT_PARAM(IsCFDInstance(handle->baseAddress)); + + handle->baseAddress->CFDCTRL.BIT.cfden = BASE_CFG_ENABLE; +} + +/** + * @brief Stop CFD Module. + * @param handle CFD handle. + * @retval None. + */ +void HAL_CFD_Stop(CFD_Handle *handle) +{ + CFD_ASSERT_PARAM(handle != NULL); + CFD_ASSERT_PARAM(IsCFDInstance(handle->baseAddress)); + + handle->baseAddress->CFDCTRL.BIT.cfden = BASE_CFG_DISABLE; +} + +/** + * @brief Registers the interrupt function to the specified interrupt type. + * @param handle CFD handle. + * @param type Specified interrupt type. + * @param callback Interrupt callback function. + * @retval @ref BASE_StatusType. + */ +BASE_StatusType HAL_CFD_RegisterCallback(CFD_Handle *handle, CFD_Interrupt_Type type, CFD_CallBackFuncType callback) +{ + CFD_ASSERT_PARAM(handle != NULL); + CFD_ASSERT_PARAM(callback != NULL); + CFD_ASSERT_PARAM(IsCFDInstance(handle->baseAddress)); + + switch (type) { + case CFD_INT_PLL_REF_CLOCK_STOP_MASK : /* Clock stop interrupt. */ + handle->userCallBack.PllClockStopCallback = callback; + break; + case CFD_INT_CHECK_END_MASK : /* Check end interrupt. */ + handle->userCallBack.CheckEndCallback = callback; + break; + default: + return BASE_STATUS_ERROR; + } + + return BASE_STATUS_OK; +} + +/** + * @brief Interrupt service processing function. + * @param handle CFD Handle. + * @retval None. + */ +void HAL_CFD_IrqHandler(void *handle) +{ + CFD_ASSERT_PARAM(handle != NULL); + CFD_Handle *cfdHandle = (CFD_Handle *)handle; + CFD_ASSERT_PARAM(IsCFDInstance(cfdHandle->baseAddress)); + + /* PLL clock stop interrupt. */ + if (cfdHandle->baseAddress->CFDINTSTS.BIT.clk_fail_int == 0x01) { + cfdHandle->baseAddress->CFDINTRAW.BIT.clk_fail_raw = BASE_CFG_SET; + if (cfdHandle->userCallBack.PllClockStopCallback) { + cfdHandle->userCallBack.PllClockStopCallback(cfdHandle); + } + } + + /* Check end interrupt. */ + if (cfdHandle->baseAddress->CFDINTSTS.BIT.chk_end_int == 0x01) { + cfdHandle->baseAddress->CFDINTRAW.BIT.chk_end_raw = BASE_CFG_SET; + if (cfdHandle->userCallBack.CheckEndCallback) { + cfdHandle->userCallBack.CheckEndCallback(cfdHandle); + } + } +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/cmm/common/inc/cmm.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/cmm/common/inc/cmm.h new file mode 100644 index 00000000..fedc5f36 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/cmm/common/inc/cmm.h @@ -0,0 +1,121 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cmm.h + * @author MCU Driver Team + * @brief CMM module driver. + * @details This file provides firmware CMM Handle structure and Functions + * prototypes to manage the following functionalities of the CMM module. + * + Initialization and de-initialization functions + * + config the register of CMM module + */ + +#ifndef McuMagicTag_CMM_H +#define McuMagicTag_CMM_H + +/* Includes ------------------------------------------------------------------ */ +#include "cmm_ip.h" + +/* Macro definitions ---------------------------------------------------------*/ +/** + * @defgroup CMM CMM + * @brief CMM module. + * @{ + */ + +/** + * @defgroup CMM_Common CMM Common + * @brief CMM common external module. + * @{ + */ + +/** + * @defgroup CMM_Handle_Definition CMM Handle Definition + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ + +/** + * @brief CMM module configurable item. + */ +typedef enum { + CMM_CFG_TRIGGER_MODE = 0x00000001U, + CMM_CFG_TARGET_SOURCE = 0x00000002U, + CMM_CFG_TARGET_FREQ_DIV = 0x00000003U, + CMM_CFG_REF_SOURCE = 0x00000004U, + CMM_CFG_REF_FREQ_DIV = 0x00000005U, + CMM_CFG_UPPER_BOUND = 0x00000006U, + CMM_CFG_LOWER_BOUND = 0x00000007U, + CMM_CFG_INT_TYPE = 0x00000008U, + CMM_CFG_MAX +} CMM_CFG_TYPE; + +/** + * @brief CMM handle. + */ +typedef struct _CMM_Handle { + CMM_RegStruct *baseAddress; /**< CMM registers base address. */ + CMM_Trigger_Mode mode; /**< Effective edge of the target clock. */ + CMM_Target_Freq_Div_Value targetFreqDivision; /**< Frequency divider of the working target clock. */ + CMM_Ref_Freq_Div_Value refFreqDivision; /**< Frequency divider of the working reference clock. */ + CMM_Target_Clock_Source targetClockSource; /**< Working target clock source selection. */ + CMM_Ref_Clock_Source refClockSource; /**< Working reference clock source selection. */ + unsigned short upperBound; /**< Upper bound of window. */ + unsigned short lowerBound; /**< Lower bound of window. */ + CMM_Interrupt_Type interruptType; /**< Enabled interrupt type. */ + CMM_UserCallBack userCallBack; /**< CMM Interrupt callback functions.*/ + CMM_ExtendHandle handleEx; /**< CMM extend parameter */ +} CMM_Handle; + +/** + * @brief Typedef callback function of CMM + */ +typedef void (*CMM_CallBackFuncType)(void *handle); + +/** + * @} + */ + +/** + * @defgroup CMM_API_Declaration CMM HAL API + * @{ + */ + +/* Hardware abstraction layer functions -------------------------------------------------------- */ +BASE_StatusType HAL_CMM_Init(CMM_Handle *handle); +BASE_StatusType HAL_CMM_DeInit(CMM_Handle *handle); +BASE_StatusType HAL_CMM_Config(CMM_Handle *handle, CMM_CFG_TYPE cfgType); +void HAL_CMM_GetConfig(CMM_Handle *handle); +void HAL_CMM_Start(CMM_Handle *handle); +void HAL_CMM_Stop(CMM_Handle *handle); +BASE_StatusType HAL_CMM_RegisterCallback(CMM_Handle *handle, CMM_Interrupt_Type type, CMM_CallBackFuncType callback); +void HAL_CMM_IrqHandler(void *handle); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_UART_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/cmm/inc/cmm_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/cmm/inc/cmm_ip.h new file mode 100644 index 00000000..a4984c90 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/cmm/inc/cmm_ip.h @@ -0,0 +1,601 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cmm_ip.h + * @author MCU Driver Team + * @brief CMM module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the CMM. + * + Register Struct of CMM + * + CMM Register Map struct + * + Direct Configuration Layer functions of CMM + */ + +#ifndef McuMagicTag_CMM_IP_H +#define McuMagicTag_CMM_IP_H + +/* Includes ------------------------------------------------------------------ */ +#include "baseinc.h" +/* Macro definitions ------------------------------------------------------- */ +#ifdef CMM_PARAM_CHECK + #define CMM_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM + #define CMM_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET + #define CMM_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else + #define CMM_ASSERT_PARAM(para) ((void)0U) + #define CMM_PARAM_CHECK_NO_RET(para) ((void)0U) + #define CMM_PARAM_CHECK_WITH_RET(param, ret) ((void)0U) +#endif +/** + * @addtogroup CMM + * @{ + */ + +/** + * @defgroup CMM_IP: cmm_v0 + * @{ + */ + +/** + * @defgroup CMM_Param_Def CMM Parameters Definition + * @brief Description of CMM configuration parameters. + * @{ + */ + +/* Typedef definitions ------------------------------------------------------- */ +typedef enum { + CMM_TRIGGER_RISE = 0x00000000U, + CMM_TRIGGER_FALL = 0x00000001U, + CMM_TRIGGER_BOTH = 0x00000002U, + CMM_TRIGGER_NONE = 0x00000003U, + CMM_TRIGGER_MAX +} CMM_Trigger_Mode; + +typedef enum { + CMM_TARGET_FREQ_DIV_0 = 0x00000000U, + CMM_TARGET_FREQ_DIV_32 = 0x00000001U, + CMM_TARGET_FREQ_DIV_128 = 0x00000002U, + CMM_TARGET_FREQ_DIV_1024 = 0x00000003U, + CMM_TARGET_FREQ_DIV_8192 = 0x00000004U, + CMM_TARGET_FREQ_DIV_MAX +} CMM_Target_Freq_Div_Value; + +typedef enum { + CMM_REF_FREQ_DIV_0 = 0x00000000U, + CMM_REF_FREQ_DIV_4 = 0x00000001U, + CMM_REF_FREQ_DIV_8 = 0x00000002U, + CMM_REF_FREQ_DIV_32 = 0x00000003U, + CMM_REF_FREQ_DIV_MAX +} CMM_Ref_Freq_Div_Value; + +typedef enum { + CMM_TARGET_CLK_LOSC = 0x00000000U, + CMM_TARGET_CLK_HOSC = 0x00000001U, + CMM_TARGET_CLK_TCXO = 0x00000002U, + CMM_TARGET_CLK_HS_SYS = 0x00000003U, + CMM_TARGET_CLK_LS_SYS = 0x00000004U, + CMM_TARGET_CLK_MAX +} CMM_Target_Clock_Source; + +typedef enum { + CMM_REF_CLK_LOSC = 0x00000000U, + CMM_REF_CLK_HOSC = 0x00000001U, + CMM_REF_CLK_TCXO = 0x00000002U, + CMM_REF_CLK_HS_SYS = 0x00000003U, + CMM_REF_CLK_MAX +} CMM_Ref_Clock_Source; + +typedef enum { + CMM_INT_COUNTER_OVERFLOW_MASK = 0x00000001U, + CMM_INT_CHECK_END_MASK = 0x00000002U, + CMM_INT_FREQ_ERR_MASK = 0x00000004U, + CMM_INT_MAX +} CMM_Interrupt_Type; + +/** + * @} + */ + +/** + * @defgroup CMM_Reg_Def CMM Register Definition + * @brief Description CMM register mapping structure. + * @{ + */ + +/** + * @brief CMM version registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int month_day : 16; /**< Month and day. */ + unsigned int year : 8; /**< Year. */ + unsigned int release_substep : 1; /**< Version information. */ + unsigned int release_step : 1; /**< Version information. */ + unsigned int release_ver : 1; /**< Version information. */ + unsigned int reserved0 : 5; + } BIT; +} volatile CMVER_Reg; + +/** + * @brief CMM control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cmen : 1; /**< CMM enable or disable. */ + unsigned int reserved0 : 31; + } BIT; +} volatile CMCTRL_Reg; + +/** + * @brief CMM target clock control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int tgtsel : 3; /**< CMM target clock source. */ + unsigned int reserved0 : 1; + unsigned int tgtscale : 3; /**< CMM target clock divide factor. */ + unsigned int reserved1 : 1; + unsigned int tgt_edgesel : 2; /**< CMM target clock effective edge selection. */ + unsigned int reserved2 : 22; + } BIT; +} volatile CMTGTCTRL_Reg; + +/** + * @brief CMM reference clock control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int refsel : 2; /**< CMM reference clock source. */ + unsigned int reserved0 : 2; + unsigned int refdiv : 2; /**< CMM reference clock divide factor. */ + unsigned int reserved1 : 26; + } BIT; +} volatile CMREFCTRL_Reg; + +/** + * @brief CMM check window upper bound registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cmwdoh : 16; /**< CMM check window upper bound value. */ + unsigned int reserved0 : 16; + } BIT; +} volatile CMWDOH_Reg; + +/** + * @brief CMM check window low bound registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cmwdol : 16; /**< CMM check window low bound value. */ + unsigned int reserved0 : 16; + } BIT; +} volatile CMWDOL_Reg; + +/** + * @brief CMM count locked value registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cmcnt_lock : 16; /**< CMM count locked value */ + unsigned int reserved0 : 16; + } BIT; +} volatile CMCNTLOCK_Reg; + +/** + * @brief CMM interrupt enable registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cnt_ovf_en : 1; /**< CMM count overflow interrupt enable. */ + unsigned int chk_end_en : 1; /**< CMM check end interrupt enable. */ + unsigned int freq_err_en : 1; /**< CMM frequence error interrupt enable. */ + unsigned int reserved0 : 29; + } BIT; +} volatile CMINTENA_Reg; + +/** + * @brief CMM interrupt status registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cnt_ovf_int : 1; /**< CMM count overflow interrupt status. */ + unsigned int chk_end_int : 1; /**< CMM check end interrupt status. */ + unsigned int freq_err_int : 1; /**< CMM frequence error interrupt status. */ + unsigned int reserved0 : 29; + } BIT; +} volatile CMINTSTS_Reg; + +/** + * @brief CMM initial interrupt registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cnt_ovf_raw : 1; /**< CMM count overflow initial interrupt. */ + unsigned int chk_end_raw : 1; /**< CMM check end initial interrupt. */ + unsigned int freq_err_raw : 1; /**< CMM frequence error initial interrupt. */ + unsigned int reserved0 : 29; + } BIT; +} volatile CMINTRAW_Reg; + +/** + * @brief CMM interrupt injection registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cnt_ovf_inj : 1; /**< CMM frequence error interrupt injection. */ + unsigned int chk_end_inj : 1; /**< CMM check end interrupt injection. */ + unsigned int freq_err_inj : 1; /**< CMM frequence error interrupt injection. */ + unsigned int reserved0 : 29; + } BIT; +} volatile CMINTINJ_Reg; + +/** + * @brief CMM Interrupt callback functions. + * + */ +typedef struct { + void (*FreqErrorCallback)(void *handle); + /**< Clock frequency error callback function */ + void (*CheckEndCallback)(void *handle); + /**< End of each check callback function */ + void (*CountOverflowCallback)(void *handle); + /**< Count Overflow callback function */ +} CMM_UserCallBack; + +/** + * @brief CMM extend handle. + */ +typedef struct _CMM_ExtendeHandle { +} CMM_ExtendHandle; + +/** + * @brief CMM register mapping structure. + */ +typedef struct { + CMVER_Reg CMVER; /**< CMM version register, offset address: 0x0000. */ + CMCTRL_Reg CMCTRL; /**< CMM control register, offset address: 0x0004. */ + CMTGTCTRL_Reg CMTGTCTRL; /**< CMM target clock control register, offset address: 0x0008. */ + CMREFCTRL_Reg CMREFCTRL; /**< CMM reference clock control register, offset address: 0x000C. */ + CMWDOH_Reg CMWDOH; /**< CMM check window upper bound register, offset address: 0x0010. */ + CMWDOL_Reg CMWDOL; /**< CMM check window low bound register, offset address: 0x0014. */ + CMCNTLOCK_Reg CMCNTLOCK; /**< CMM count locked value register, offset address: 0x0018. */ + CMINTENA_Reg CMINTENA; /**< CMM interrupt enable register, offset address: 0x001C. */ + CMINTSTS_Reg CMINTSTS; /**< CMM interrupt status register, offset address: 0x0020. */ + CMINTRAW_Reg CMINTRAW; /**< CMM initial interrupt register, offset address: 0x0024. */ + CMINTINJ_Reg CMINTINJ; /**< CMM interrupt injection register, offset address: 0x0028. */ +} volatile CMM_RegStruct; + +/** + * @} + */ + +/** + * @brief Enable CMM module. + * @param cmmx CMM register base address. + * @retval None. + */ +static inline void DCL_CMM_Enable(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + cmmx->CMCTRL.BIT.cmen = BASE_CFG_ENABLE; +} + +/** + * @brief Disable CMM module. + * @param cmmx CMM register base address. + * @retval None. + */ +static inline void DCL_CMM_Disable(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + cmmx->CMCTRL.BIT.cmen = BASE_CFG_DISABLE; +} + +/** + * @brief Sets the valid edge of the target clock. + * @param cmmx CMM register base address. + * @param mode Type of valid edge. + * @retval None. + */ +static inline void DCL_CMM_SetTargetClockTriggerMode(CMM_RegStruct *cmmx, CMM_Trigger_Mode mode) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_NO_RET(mode < CMM_TRIGGER_MAX); + cmmx->CMTGTCTRL.BIT.tgt_edgesel = mode; +} + +/** + * @brief Gets the valid edge of the target clock. + * @param cmmx CMM register base address. + * @retval unsigned int @ref CMM_Trigger_Mode. + */ +static inline unsigned int DCL_CMM_GetTargetClockTriggerMode(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + return cmmx->CMTGTCTRL.BIT.tgt_edgesel; +} + +/** + * @brief Sets the frequency divider of the target clock. + * @param cmmx CMM register base address. + * @param value Specified frequency divider. + * @retval None. + */ +static inline void DCL_CMM_SetTargetClockFreqDivision(CMM_RegStruct *cmmx, CMM_Target_Freq_Div_Value value) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_NO_RET(value < CMM_TARGET_FREQ_DIV_MAX); + cmmx->CMTGTCTRL.BIT.tgtscale = value; +} + +/** + * @brief Gets the frequency divider of the target clock. + * @param cmmx CMM register base address. + * @retval unsigned int @ref CMM_Target_Freq_Div_Value. + */ +static inline unsigned int DCL_CMM_GetTargetClockFreqDivision(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + return cmmx->CMTGTCTRL.BIT.tgtscale; +} + +/** + * @brief Sets the target clock source. + * @param cmmx CMM register base address. + * @param clockSource Specifies the type of the clock source. + * @retval None. + */ +static inline void DCL_CMM_SetTargetClockSource(CMM_RegStruct *cmmx, CMM_Target_Clock_Source clockSource) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_NO_RET(clockSource < CMM_TARGET_CLK_MAX); + cmmx->CMTGTCTRL.BIT.tgtsel = clockSource; +} + +/** + * @brief Gets the target clock source. + * @param cmmx CMM register base address. + * @retval unsigned int @ref CMM_Target_Clock_Source. + */ +static inline unsigned int DCL_CMM_GetTargetClockSource(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + return cmmx->CMTGTCTRL.BIT.tgtsel; +} + +/** + * @brief Sets the frequency divider of the reference clock. + * @param cmmx CMM register base address. + * @param value Specified frequency divider. + * @retval None. + */ +static inline void DCL_CMM_SetRefClockFreqDivision(CMM_RegStruct *cmmx, CMM_Ref_Freq_Div_Value value) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_NO_RET(value < CMM_REF_FREQ_DIV_MAX); + cmmx->CMREFCTRL.BIT.refdiv = value; +} + +/** + * @brief Gets the frequency divider of the reference clock. + * @param cmmx CMM register base address. + * @retval unsigned int @ref CMM_Ref_Freq_Div_Value. + */ +static inline unsigned int DCL_CMM_GetRefClockFreqDivision(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + return cmmx->CMREFCTRL.BIT.refdiv; +} + +/** + * @brief Sets the reference clock source. + * @param cmmx CMM register base address. + * @param clockSource Specified reference clock source. + * @retval None. + */ +static inline void DCL_CMM_SetRefClockSource(CMM_RegStruct *cmmx, CMM_Ref_Clock_Source clockSource) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_NO_RET(clockSource < CMM_REF_CLK_MAX); + cmmx->CMREFCTRL.BIT.refsel = clockSource; +} + +/** + * @brief Gets the reference clock source. + * @param cmmx CMM register base address. + * @retval unsigned int @ref CMM_Ref_Clock_Source. + */ +static inline unsigned int DCL_CMM_GetRefClockSource(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + return cmmx->CMREFCTRL.BIT.refsel; +} + +/** + * @brief Sets the upper boundary of the detection window. + * @param cmmx CMM register base address. + * @param value The value of the upper bound. + * @retval None. + */ +static inline void DCL_CMM_SetWindowUpperBound(CMM_RegStruct *cmmx, unsigned short value) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + cmmx->CMWDOH.BIT.cmwdoh = value; +} + +/** + * @brief Gets the upper boundary of the detection window. + * @param cmmx CMM register base address. + * @retval The value of the upper bound. + */ +static inline unsigned short DCL_CMM_GetWindowUpperBound(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + return cmmx->CMWDOH.BIT.cmwdoh; +} + +/** + * @brief Sets the lower boundary of the detection window. + * @param cmmx CMM register base address. + * @param value The value of the lower bound. + * @retval None. + */ +static inline void DCL_CMM_SetWindowLowerBound(CMM_RegStruct *cmmx, unsigned short value) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + cmmx->CMWDOL.BIT.cmwdol = value; +} + +/** + * @brief Gets the lower boundary of the detection window. + * @param cmmx CMM register base address. + * @retval The value of the lower bound. + */ +static inline unsigned short DCL_CMM_GetWindowLowerBound(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + return cmmx->CMWDOL.BIT.cmwdol; +} + +/** + * @brief Internal counter count latch value. + * @param cmmx CMM register base address. + * @retval unsigned short. latch value. + */ +static inline unsigned short DCL_CMM_GetCntValue(CMM_RegStruct *cmmx) +{ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + return cmmx->CMCNTLOCK.BIT.cmcnt_lock; +} + +/** + * @brief Enables the specified type of interrupt. + * @param cmmx CMM register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CMM_EnableInterrupt(CMM_RegStruct *cmmx, CMM_Interrupt_Type type) +{ + /* if define macro CMM_PARAM_CHECK, function of param check is valid */ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_NO_RET(type == CMM_INT_COUNTER_OVERFLOW_MASK || \ + type == CMM_INT_CHECK_END_MASK || \ + type == CMM_INT_FREQ_ERR_MASK); + cmmx->CMINTENA.reg |= type; +} + +/** + * @brief Disables the specified type of interrupt. + * @param cmmx CMM register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CMM_DisableInterrupt(CMM_RegStruct *cmmx, CMM_Interrupt_Type type) +{ + /* if define macro CMM_PARAM_CHECK, function of param check is valid */ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_NO_RET(type == CMM_INT_COUNTER_OVERFLOW_MASK || \ + type == CMM_INT_CHECK_END_MASK || \ + type == CMM_INT_FREQ_ERR_MASK); + cmmx->CMINTENA.reg &= (~type); +} + +/** + * @brief Check whether the specified interrupt is triggered. + * @param cmmx CMM register base address. + * @param type Mask of the interrupt type. + * @retval bool. + */ +static inline bool DCL_CMM_GetInterruptStatus(CMM_RegStruct *cmmx, CMM_Interrupt_Type type) +{ + /* if define macro CMM_PARAM_CHECK, function of param check is valid */ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_WITH_RET(type == CMM_INT_COUNTER_OVERFLOW_MASK || \ + type == CMM_INT_CHECK_END_MASK || \ + type == CMM_INT_FREQ_ERR_MASK, false); + return (cmmx->CMINTSTS.reg & type) == 0 ? false : true; +} + +/** + * @brief Clears interrupts of the specified type. + * @param cmmx CMM register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CMM_ClearInterrupt(CMM_RegStruct *cmmx, CMM_Interrupt_Type type) +{ + /* if define macro CMM_PARAM_CHECK, function of param check is valid */ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_NO_RET(type == CMM_INT_COUNTER_OVERFLOW_MASK || \ + type == CMM_INT_CHECK_END_MASK || \ + type == CMM_INT_FREQ_ERR_MASK); + cmmx->CMINTRAW.reg |= type; +} + +/** + * @brief Injects interrupts of the specified type. + * @param cmmx CMM register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CMM_EnableInterruptInject(CMM_RegStruct *cmmx, CMM_Interrupt_Type type) +{ + /* if define macro CMM_PARAM_CHECK, function of param check is valid */ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_NO_RET(type == CMM_INT_COUNTER_OVERFLOW_MASK || \ + type == CMM_INT_CHECK_END_MASK || \ + type == CMM_INT_FREQ_ERR_MASK); + cmmx->CMINTINJ.reg |= type; +} + +/** + * @brief Stop injecting interrupts of a specified type. + * @param cmmx CMM register base address. + * @param type Mask of the interrupt type. + * @retval None. + */ +static inline void DCL_CMM_DisableInterruptInject(CMM_RegStruct *cmmx, CMM_Interrupt_Type type) +{ + /* if define macro CMM_PARAM_CHECK, function of param check is valid */ + CMM_ASSERT_PARAM(IsCMMInstance(cmmx)); + CMM_PARAM_CHECK_NO_RET(type == CMM_INT_COUNTER_OVERFLOW_MASK || \ + type == CMM_INT_CHECK_END_MASK || \ + type == CMM_INT_FREQ_ERR_MASK); + cmmx->CMINTINJ.reg &= (~type); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_CMM_IP_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/cmm/src/cmm.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/cmm/src/cmm.c new file mode 100644 index 00000000..19c14914 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/cmm/src/cmm.c @@ -0,0 +1,246 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cmm.c + * @author MCU Driver Team + * @brief CMM module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the CMM. + * + Initialization and de-initialization functions. + * + Config the register of CMM. + * + Interrupt callback function and user registration function. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "cmm.h" + +/** + * @brief Perform initial configuration based on the handle. + * @param handle CMM handle. + * @retval @ref BASE_StatusType. + */ +BASE_StatusType HAL_CMM_Init(CMM_Handle *handle) +{ + /* param check */ + CMM_ASSERT_PARAM(handle != NULL); + CMM_ASSERT_PARAM(IsCMMInstance(handle->baseAddress)); + CMM_PARAM_CHECK_WITH_RET(handle->targetClockSource < CMM_TARGET_CLK_MAX, BASE_STATUS_ERROR); + CMM_PARAM_CHECK_WITH_RET(handle->mode < CMM_TRIGGER_MAX, BASE_STATUS_ERROR); + CMM_PARAM_CHECK_WITH_RET(handle->targetFreqDivision < CMM_TARGET_FREQ_DIV_MAX, BASE_STATUS_ERROR); + CMM_PARAM_CHECK_WITH_RET(handle->refClockSource < CMM_REF_CLK_MAX, BASE_STATUS_ERROR); + CMM_PARAM_CHECK_WITH_RET(handle->refFreqDivision < CMM_REF_FREQ_DIV_MAX, BASE_STATUS_ERROR); + CMM_PARAM_CHECK_WITH_RET(handle->interruptType < CMM_INT_MAX, BASE_STATUS_ERROR); + /* init handle value into register */ + handle->baseAddress->CMTGTCTRL.BIT.tgt_edgesel = handle->mode; + /* Init CMM target clock. */ + handle->baseAddress->CMTGTCTRL.BIT.tgtsel = handle->targetClockSource; + handle->baseAddress->CMTGTCTRL.BIT.tgtscale = handle->targetFreqDivision; + /* Init CMM reference clock. */ + handle->baseAddress->CMREFCTRL.BIT.refsel = handle->refClockSource; + handle->baseAddress->CMREFCTRL.BIT.refdiv = handle->refFreqDivision; + /* Init CMM UpperBound and LowerBound. */ + handle->baseAddress->CMWDOH.BIT.cmwdoh = handle->upperBound; + handle->baseAddress->CMWDOL.BIT.cmwdol = handle->lowerBound; + handle->baseAddress->CMINTENA.reg = handle->interruptType; + + return BASE_STATUS_OK; +} + +/** + * @brief Deinitialize configurations based on the handle. + * @param handle CMM handle. + * @retval @ref BASE_StatusType. + */ +BASE_StatusType HAL_CMM_DeInit(CMM_Handle *handle) +{ + CMM_ASSERT_PARAM(handle != NULL); + CMM_ASSERT_PARAM(IsCMMInstance(handle->baseAddress)); + /* Clear interrupt callback function. */ + handle->userCallBack.FreqErrorCallback = NULL; + handle->userCallBack.CheckEndCallback = NULL; + handle->userCallBack.CountOverflowCallback = NULL; + /* Clear register value. */ + handle->baseAddress->CMREFCTRL.reg = BASE_CFG_DISABLE; + handle->baseAddress->CMINTENA.reg = BASE_CFG_DISABLE; + return BASE_STATUS_OK; +} + + +/** + * @brief Set this parameter based on the configuration item parameters. + * @param handle CMM handle. + * @param cfgType Configurable item. @ref CMM_CFG_TYPE. + * @retval @ref BASE_StatusType. + */ +BASE_StatusType HAL_CMM_Config(CMM_Handle *handle, CMM_CFG_TYPE cfgType) +{ + /* param check */ + CMM_ASSERT_PARAM(handle != NULL); + CMM_ASSERT_PARAM(IsCMMInstance(handle->baseAddress)); + CMM_PARAM_CHECK_WITH_RET(handle->targetClockSource < CMM_TARGET_CLK_MAX, BASE_STATUS_ERROR); + CMM_PARAM_CHECK_WITH_RET(handle->mode < CMM_TRIGGER_MAX, BASE_STATUS_ERROR); + CMM_PARAM_CHECK_WITH_RET(handle->targetFreqDivision < CMM_TARGET_FREQ_DIV_MAX, BASE_STATUS_ERROR); + CMM_PARAM_CHECK_WITH_RET(handle->refClockSource < CMM_REF_CLK_MAX, BASE_STATUS_ERROR); + CMM_PARAM_CHECK_WITH_RET(handle->refFreqDivision < CMM_REF_FREQ_DIV_MAX, BASE_STATUS_ERROR); + CMM_PARAM_CHECK_WITH_RET(handle->interruptType < CMM_INT_MAX, BASE_STATUS_ERROR); + /* config register value with different type of cmm member */ + switch (cfgType) { + case CMM_CFG_UPPER_BOUND: + handle->baseAddress->CMWDOH.BIT.cmwdoh = handle->upperBound; /* upperBound value */ + break; + case CMM_CFG_LOWER_BOUND: + handle->baseAddress->CMWDOL.BIT.cmwdol = handle->lowerBound; /* lowerBound value */ + break; + case CMM_CFG_TARGET_SOURCE: + handle->baseAddress->CMTGTCTRL.BIT.tgtsel = handle->targetClockSource; /* target Clock Source */ + break; + case CMM_CFG_TRIGGER_MODE: + handle->baseAddress->CMTGTCTRL.BIT.tgt_edgesel = handle->mode; /* trigger mode */ + break; + case CMM_CFG_TARGET_FREQ_DIV: + handle->baseAddress->CMTGTCTRL.BIT.tgtscale = handle->targetFreqDivision; /* target Freq Division */ + break; + case CMM_CFG_REF_SOURCE: + handle->baseAddress->CMREFCTRL.BIT.refsel = handle->refClockSource; /* ref Clock Source */ + break; + case CMM_CFG_REF_FREQ_DIV: + handle->baseAddress->CMREFCTRL.BIT.refdiv = handle->refFreqDivision; /* ref Freq Division */ + break; + case CMM_CFG_INT_TYPE: + handle->baseAddress->CMINTENA.reg = handle->interruptType; /* interrupt Type */ + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief Reads the register configuration value to the handle. + * @param handle CMM handle. + * @retval None. + */ +void HAL_CMM_GetConfig(CMM_Handle *handle) +{ + /* param check */ + CMM_ASSERT_PARAM(handle != NULL); + CMM_ASSERT_PARAM(IsCMMInstance(handle->baseAddress)); + /* Get config of cmm member from register */ + handle->upperBound = handle->baseAddress->CMWDOH.BIT.cmwdoh; + handle->lowerBound = handle->baseAddress->CMWDOL.BIT.cmwdol; + handle->targetClockSource = handle->baseAddress->CMTGTCTRL.BIT.tgtsel; + handle->mode = handle->baseAddress->CMTGTCTRL.BIT.tgt_edgesel; + handle->targetFreqDivision = handle->baseAddress->CMTGTCTRL.BIT.tgtscale; + handle->refClockSource = handle->baseAddress->CMREFCTRL.BIT.refsel; + handle->refFreqDivision = handle->baseAddress->CMREFCTRL.BIT.refdiv; +} + +/** + * @brief Start CMM Module. + * @param handle CMM handle. + * @retval None. + */ +void HAL_CMM_Start(CMM_Handle *handle) +{ + CMM_ASSERT_PARAM(handle != NULL); + CMM_ASSERT_PARAM(IsCMMInstance(handle->baseAddress)); + + handle->baseAddress->CMCTRL.BIT.cmen = BASE_CFG_ENABLE; +} + +/** + * @brief Stop CMM Module. + * @param handle CMM handle. + * @retval None. + */ +void HAL_CMM_Stop(CMM_Handle *handle) +{ + CMM_ASSERT_PARAM(handle != NULL); + CMM_ASSERT_PARAM(IsCMMInstance(handle->baseAddress)); + + handle->baseAddress->CMCTRL.BIT.cmen = BASE_CFG_DISABLE; +} + +/** + * @brief Registers the interrupt function to the specified interrupt type. + * @param handle CMM handle. + * @param type Specified interrupt type. + * @param callback Interrupt callback function. + * @retval @ref BASE_StatusType. + */ +BASE_StatusType HAL_CMM_RegisterCallback(CMM_Handle *handle, CMM_Interrupt_Type type, CMM_CallBackFuncType callback) +{ + CMM_ASSERT_PARAM(handle != NULL); + CMM_ASSERT_PARAM(callback != NULL); + CMM_ASSERT_PARAM(IsCMMInstance(handle->baseAddress)); + + switch (type) { + case CMM_INT_FREQ_ERR_MASK: /* Frequence error interrupt. */ + handle->userCallBack.FreqErrorCallback = callback; + break; + case CMM_INT_CHECK_END_MASK: /* Check end interrupt. */ + handle->userCallBack.CheckEndCallback = callback; + break; + case CMM_INT_COUNTER_OVERFLOW_MASK: /* Counter overflow interrupt. */ + handle->userCallBack.CountOverflowCallback = callback; + break; + default: + return BASE_STATUS_ERROR; + } + + return BASE_STATUS_OK; +} + +/** + * @brief Interrupt service processing function. + * @param handle CMM Handle. + * @retval None. + */ +void HAL_CMM_IrqHandler(void *handle) +{ + CMM_ASSERT_PARAM(handle != NULL); + CMM_Handle *cmmHandle = (CMM_Handle *)handle; + CMM_ASSERT_PARAM(IsCMMInstance(cmmHandle->baseAddress)); + + /**< Frequence error interrupt. */ + if (cmmHandle->baseAddress->CMINTSTS.BIT.freq_err_int == 0x01) { + cmmHandle->baseAddress->CMINTRAW.BIT.freq_err_raw = BASE_CFG_SET; + /* Disable and then enable the CMM to ensure that the CMM can still work. */ + cmmHandle->baseAddress->CMCTRL.BIT.cmen = BASE_CFG_UNSET; + cmmHandle->baseAddress->CMCTRL.BIT.cmen = BASE_CFG_SET; + if (cmmHandle->userCallBack.FreqErrorCallback) { + cmmHandle->userCallBack.FreqErrorCallback(cmmHandle); + } + } + + /**< Check end interrupt. */ + if (cmmHandle->baseAddress->CMINTSTS.BIT.chk_end_int == 0x01) { + cmmHandle->baseAddress->CMINTRAW.BIT.chk_end_raw = BASE_CFG_SET; + if (cmmHandle->userCallBack.CheckEndCallback) { + cmmHandle->userCallBack.CheckEndCallback(cmmHandle); + } + } + + /**< Counter overflow interrupt. */ + if (cmmHandle->baseAddress->CMINTSTS.BIT.cnt_ovf_int == 0x01) { + cmmHandle->baseAddress->CMINTRAW.BIT.cnt_ovf_raw = BASE_CFG_SET; + if (cmmHandle->userCallBack.CountOverflowCallback) { + cmmHandle->userCallBack.CountOverflowCallback(cmmHandle); + } + } +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/crc/common/inc/crc.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/crc/common/inc/crc.h new file mode 100644 index 00000000..4e73620c --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/crc/common/inc/crc.h @@ -0,0 +1,100 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file crc.h + * @author MCU Driver Team + * @brief CRC module driver + * @details The header file contains the following declaration: + * + CRC handle structure definition. + * + Initialization functions. + * + CRC Set And Get Functions. + * + Interrupt Handler Functions. + */ + +#ifndef McuMagicTag_CRC_H +#define McuMagicTag_CRC_H +/* Includes ------------------------------------------------------------------*/ +#include "crc_ip.h" + +/* Macro definition */ +/** + * @defgroup CRC CRC + * @brief CRC module. + * @{ + */ + +/** + * @defgroup CRC_Common CRC Common + * @brief CRC common external module. + * @{ + */ + +/** + * @defgroup CRC_Handle_Definition CRC Handle Definition + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ +typedef void (* CRC_CallbackType)(void *handle); + +/** + * @brief CRC handle structure definition. + */ +typedef struct _CRC_Handle { + CRC_RegStruct *baseAddress; /**< CRC Registers */ + CRC_InputDataFormat inputDataFormat; /**< CRC byte mode */ + CRC_PolynomialMode polyMode; /**< CRC polynomial mode */ + CRC_InitValueType initValueType; /**< CRC init value type */ + CRC_ResultXorValueType resultXorValueType; /**< CRC result xor value type */ + CRC_ReverseEnableType reverseEnableType; /**< input and output reverse type */ + CRC_XorEndianEnableType xorEndianEnbaleType; /**< xor enable and endian enable type */ + CRC_UserCallBack userCallBack; /**< User callback */ + CRC_ExtendHandle handleEx; /**< CRC extend parameter */ +} CRC_Handle; + +/** + * @} + */ + +/** + * @defgroup CRC_API_Declaration CRC HAL API + * @{ + */ +BASE_StatusType HAL_CRC_Init(CRC_Handle *handle); +void HAL_CRC_DeInit(CRC_Handle *handle); +unsigned int HAL_CRC_SetInputDataGetCheck(CRC_Handle *handle, unsigned int data); +unsigned int HAL_CRC_Accumulate(CRC_Handle *handle, const void *pData, unsigned int length); +unsigned int HAL_CRC_Calculate(CRC_Handle *handle, const void *pData, unsigned int length); +bool HAL_CRC_CheckInputData(CRC_Handle *handle, const void *pData, unsigned int length, unsigned int crcValue); +void HAL_CRC_SetCheckInData(CRC_Handle *handle, unsigned int data); +unsigned int HAL_CRC_LoadCheckInData(CRC_Handle *handle); +void HAL_CRC_RegisterCallback(CRC_Handle *handle, CRC_CallbackType callBackFunc); +void HAL_CRC_IrqHandler(void *handle); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_CRC_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/crc/inc/crc_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/crc/inc/crc_ip.h new file mode 100644 index 00000000..a8f877da --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/crc/inc/crc_ip.h @@ -0,0 +1,557 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file crc_ip.h + * @author MCU Driver Team + * @brief CRC module driver + * @details The header file contains the following declaration: + * + CRC configuration enums. + * + CRC register structures. + * + CRC DCL Functions. + * + Parameters check functions. + */ + +#ifndef McuMagicTag_CRC_IP_H +#define McuMagicTag_CRC_IP_H +/* Includes ------------------------------------------------------------------*/ +#include "baseinc.h" +/* Macro definitions -------------------------------------------------------*/ +#ifdef CRC_PARAM_CHECK + #define CRC_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM + #define CRC_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET + #define CRC_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else + #define CRC_ASSERT_PARAM(para) ((void)0U) + #define CRC_PARAM_CHECK_NO_RET(para) ((void)0U) + #define CRC_PARAM_CHECK_WITH_RET(param, ret) ((void)0U) +#endif +/** + * @addtogroup CRC + * @{ + */ + +/** + * @defgroup CRC_IP CRC_IP + * @brief CRC_IP: crc_v0. + * @{ + */ + +/** + * @defgroup CRC_Param_Def CRC Parameters Definition + * @brief Description of CRC configuration parameters. + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ +/** + * @brief CRC algorithm type. + * @details CRC algorithm type: + * +CRC8_ROHC -- CRC-8/ROHC algorithm, CRC8_07, crc_mode reg value:b000 + * +CRC16_IBM -- CRC-16/IBM algorithm, CRC16_8005, crc_mode reg value:b010 + * +CRC16_MODBUS -- CRC-16/MODBUS algorithm, CRC16_8005, crc_mode reg value:b010 + * +CRC16_CCITT_FALSE -- CRC-16/CCITT-FALSE algorithm, CRC16_1021, crc_mode reg value:b011 + * +CRC16_XMODEM -- CRC-16/XMODEM algorithm, CRC16_1021, crc_mode reg value:b011 + * +CRC32 -- CRC32 algorithm, CRC32_04C11D87, crc_mode reg value:b10x + * +CRC_ALG_MODE_MAX -- CRC_mode bunder + */ +typedef enum { + CRC8_ROHC = 0x00000001U, + CRC16_IBM = 0x00000002U, + CRC16_MODBUS = 0x00000003U, + CRC16_CCITT_FALSE = 0x00000004U, + CRC16_XMODEM = 0x00000005U, + CRC32 = 0x00000006U, + CRC_ALG_MODE_MAX +} CRC_AlgorithmMode; + +/** + * @brief CRC polynomial mode register configuration. + */ +typedef enum { + CRC8_07_POLY_MODE = 0x00000000U, + CRC8_07_POLY_MODE_BK = 0x00000001U, + CRC16_8005_POLY_MODE = 0x00000002U, + CRC16_1021_POLY_MODE = 0x00000003U, + CRC32_04C11D87_POLY_MODE = 0x00000004U, + CRC32_04C11D87_POLY_MODE_BK = 0x00000005U, + CRC_POLY_MODE_MAX +} CRC_PolynomialMode; + +/** + * @brief CRC init value type. + */ +typedef enum { + TYPE_CRC_INIT_VALUE_FF = 0x00000200U, + TYPE_CRC_INIT_VALUE_0000 = 0x00000300U, + TYPE_CRC_INIT_VALUE_FFFF = 0x00000400U, + TYPE_CRC_INIT_VALUE_FFFFFFFF = 0x00000500U +} CRC_InitValueType; + +/** + * @brief CRC init value Enumeration. + */ +typedef enum { + CRC_INIT_VALUE_FF = 0x000000FFU, + CRC_INIT_VALUE_0000 = 0x00000000U, + CRC_INIT_VALUE_FFFF = 0x0000FFFFU, + CRC_INIT_VALUE_FFFFFFFF = 0xFFFFFFFFU +} CRC_InitValue; + +/** + * @brief CRC xor value type. + */ +typedef enum { + TYPE_CRC_XOR_VALUE_00 = 0x00000001U, + TYPE_CRC_XOR_VALUE_0000 = 0x00000002U, + TYPE_CRC_XOR_VALUE_FFFFFFFF = 0x00000003U +} CRC_ResultXorValueType; + +/** + * @brief CRC input data or output data in reverse order. + */ +typedef enum { + REVERSE_INPUT_FALSE_OUTPUT_FALSE = 0x00000001U, + REVERSE_INPUT_TURE_OUTPUT_TRUE = 0x00000002U +} CRC_ReverseEnableType; + +/** + * @brief CRC xor result value and endian mode type. + */ +typedef enum { + DISABLE_XOR_ENABLE_LSB = 0x00000000U, + DISABLE_XOR_ENABLE_MSB = 0x10000000U, + ENABLE_XOR_ENABLE_LSB = 0x20000000U, + ENABLE_XOR_ENABLE_MSB = 0x30000000U +} CRC_XorEndianEnableType; + +/** + * @brief CRC byte type register configuration. + */ +typedef enum { + CRC_MODE_BIT8 = 0x00000000U, + CRC_MODE_BIT16 = 0x00000001U, + CRC_MODE_BIT24 = 0x00000002U, + CRC_MODE_BIT32 = 0x00000003U +} CRC_InputDataFormat; + +/** + * @brief CRC FIFO status. + */ +typedef enum { + CRC_FIFO_FULL = 0x00000000U, + CRC_FIFO_EMPTY = 0x00000001U +} CRC_FIFOStatus; + +/** + * @brief CRC extend handle. + */ +typedef struct _CRC_ExtendHandle { + CRC_AlgorithmMode algoMode; /**< CRC calculate algorithm mode */ + bool enableIT; /**< Enable pready timeout interrupt */ + bool enableErrInject; /**< Enable error inject */ + unsigned int timeout; /**< APB pready max timeout value */ +} CRC_ExtendHandle; + +/** + * @brief CRC user callback. + */ +typedef struct { + void (* PreadyTimeoutCallback)(void *handle); /**< CRC pready Timeout Callback */ +} CRC_UserCallBack; +/** + * @} + */ + +/** + * @defgroup CRC_Reg_Def CRC Register Definition + * @brief Description CRC register mapping structure. + * @{ + */ + +/** + * @brief CRC control algorithm and valid bit register union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int crc_byte_mode : 2; /**< data valid byte mode. */ + unsigned int crc_mode : 3; /**< crc algorithm selection. */ + unsigned int reserved0 : 27; + } BIT; +} volatile CRC_CTRL_CFG0_REG; + +/** + * @brief CRC init register union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int crc_init : 1; /**< crc soft reset signal. */ + unsigned int reserved0 : 31; + } BIT; +} volatile CRC_CTRL_CFG1_REG; + +/** + * @brief CRC load data register union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int crc_ld : 1; /**< crc load value signal. */ + unsigned int reserved0 : 31; + } BIT; +} volatile CRC_CTRL_CFG2_REG; + +/** + * @brief CRC state register union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int crc_fifo_full : 1; /**< crc fifo full flag. */ + unsigned int crc_fifo_empty : 1; /**< crc fifo empty flag. */ + unsigned int reserved1 : 29; + } BIT; +} volatile CRC_CTRL_STATUS_REG; + +/** + * @brief CRC set pready timeout register union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pready_timeout : 1; /**< pready timeout interrupt. */ + unsigned int reserved0 : 31; + } BIT; +} volatile CRC_CTRL_INT_REG; + +/** + * @brief CRC timeout mask register union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pready_timeout_int_mask : 1; /**< pready timeout interrupt mask. */ + unsigned int reserved0 : 31; + } BIT; +} volatile CRC_CTRL_INTMASK_REG; + +/** + * @brief CRC timeout error inject register union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int time_out_err_inj : 1; /**< pready timeout error inject. */ + unsigned int reserved0 : 31; + } BIT; +} volatile CRC_CTRL_ERRINJ_REG; + +/** + * @brief CRC assemble registers structure definition + */ +typedef struct { + CRC_CTRL_CFG0_REG CRC_CTRL_CFG0; /**< crc control algorithm and valid bit register. */ + CRC_CTRL_CFG1_REG CRC_CTRL_CFG1; /**< crc init control register. */ + CRC_CTRL_CFG2_REG CRC_CTRL_CFG2; /**< crc load data register. */ + unsigned int cnt_max; /**< timeout max value. */ + unsigned int crc_check_in; /**< crc output check in value. */ + unsigned int crc_data_in; /**< crc calculate data. */ + unsigned int crc_out; /**< crc calculate output result. */ + CRC_CTRL_STATUS_REG CRC_CTRL_STATUS; /**< crc state register. */ + CRC_CTRL_INT_REG CRC_CTRL_INT; /**< crc set pready timeout register. */ + CRC_CTRL_INTMASK_REG CRC_CTRL_INTMASK; /**< crc timeout mask register. */ + CRC_CTRL_ERRINJ_REG CRC_CTRL_ERRINJ; /**< crc timeout error inject register. */ +} volatile CRC_RegStruct; + +/** + * @} + */ + +/** + * @brief Set CRC polynomial mode. + * @param crcx Value of @ref CRC_RegStruct. + * @param @ref polyMode of @ref CRC_PolynomialMode. + * @retval None. + */ +static inline void DCL_CRC_SetPolynomialMode(CRC_RegStruct *crcx, CRC_PolynomialMode polyMode) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + CRC_PARAM_CHECK_NO_RET(polyMode < CRC_POLY_MODE_MAX && polyMode >= CRC8_07_POLY_MODE); + crcx->CRC_CTRL_CFG0.BIT.crc_mode = polyMode; +} + +/** + * @brief Set CRC calculate input Data Format. + * @param crcx Value of @ref CRC_RegStruct. + * @param inputDataFormat Value of @ref CRC_InputDataFormat. + * @retval None. + */ +static inline void DCL_CRC_SetByteMode(CRC_RegStruct *crcx, CRC_InputDataFormat inputDataFormat) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + CRC_PARAM_CHECK_NO_RET(inputDataFormat <= CRC_MODE_BIT32 && inputDataFormat >= CRC_MODE_BIT8); + crcx->CRC_CTRL_CFG0.BIT.crc_byte_mode = inputDataFormat; +} + +/** + * @brief Set CRC timeout value. + * @param crcx Value of @ref CRC_RegStruct. + * @retval None. + */ +static inline void DCL_CRC_SetTimeOut(CRC_RegStruct *crcx, unsigned int timeout) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + crcx->cnt_max = timeout; +} + +/** + * @brief Set CRC soft reset function. + * @param crcx Value of @ref CRC_RegStruct. + * @retval None. + */ +static inline void DCL_CRC_SoftReset(CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + crcx->CRC_CTRL_CFG1.BIT.crc_init = BASE_CFG_SET; +} + +/** + * @brief Enable CRC init function. + * @param crcx Value of @ref CRC_RegStruct. + * @retval None. + */ +static inline void DCL_CRC_LoadInitValue(CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + crcx->CRC_CTRL_CFG2.BIT.crc_ld = BASE_CFG_SET; +} + +/** + * @brief Set CRC data in value function. + * @param crcx Value of @ref CRC_RegStruct. + * @param data value of CRC calulate data value. + * @retval None. + */ +static inline void DCL_CRC_SetInputData(CRC_RegStruct *crcx, unsigned int data) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + crcx->crc_data_in = data; +} + +/** + * @brief Get CRC input data. + * @param crcx Value of @ref CRC_RegStruct. + * @retval unsigned int CRC Input data. + */ +static inline unsigned int DCL_CRC_GetInputData(CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + return crcx->crc_data_in; +} + +/** + * @brief Get CRC output value. + * @param crcx Value of @ref CRC_RegStruct. + * @retval unsigned int CRC Output value. + */ +static inline unsigned int DCL_CRC_GetOutputData(CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + return crcx->crc_out; +} + +/** + * @brief Clear CRC interrupt signal. + * @param crcx Value of @ref CRC_RegStruct. + * @retval None. + */ +static inline void DCL_CRC_ClearIrq(CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + crcx->CRC_CTRL_INT.BIT.pready_timeout = BASE_CFG_SET; +} + +/** + * @brief Get pready interrrput flag. + * @param crcx Value of @ref CRC_RegStruct. + * @retval bool true is valid, false is invalid. + */ +static inline bool DCL_CRC_GetPreadyIrqFlag(CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + return crcx->CRC_CTRL_INT.BIT.pready_timeout; +} + +/** + * @brief Set pready timeout mask. + * @param crcx Value of @ref CRC_RegStruct. + * @param mask true means enable, false means disable. + * @retval None. + */ +static inline void DCL_CRC_SetPreadyTimeoutMask(CRC_RegStruct *crcx, bool mask) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + crcx->CRC_CTRL_INTMASK.BIT.pready_timeout_int_mask = mask; +} + +/** + * @brief Get pready timeout mask. + * @param crcx Value of @ref CRC_RegStruct. + * @retval bool pready timeout mask. + */ +static inline bool DCL_CRC_GetPreadyTimeoutMask(const CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + return crcx->CRC_CTRL_INTMASK.BIT.pready_timeout_int_mask; +} + +/** + * @brief Set timeout error inject. + * @param crcx Value of @ref CRC_RegStruct. + * @param errInject true means enable, false means disable . + * @retval None. + */ +static inline void DCL_CRC_SetTimeoutErrInj(CRC_RegStruct *crcx, bool errInject) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + crcx->CRC_CTRL_ERRINJ.BIT.time_out_err_inj = errInject; +} + +/** + * @brief Get timeout error inject. + * @param crcx Value of @ref CRC_RegStruct. + * @retval bool timeout error inject. + */ +static inline bool DCL_CRC_GetTimeoutErrInj(const CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + return crcx->CRC_CTRL_ERRINJ.BIT.time_out_err_inj; +} + +/** + * @brief Set CRC check in value function. + * @param crcx Value of @ref CRC_RegStruct. + * @param value value of CRC calulate check in value. + * @retval None. + */ +static inline void DCL_CRC_SetCheckInValue(CRC_RegStruct *crcx, unsigned int value) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + crcx->crc_check_in = value; +} + +/** + * @brief Get CRC check in value function. + * @param crcx Value of @ref CRC_RegStruct. + * @retval unsigned int crc check in value. + */ +static inline unsigned int DCL_CRC_GetCheckInValue(CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + return crcx->crc_check_in; +} + +/** + * @brief Get CRC FIFO status. + * @param crcx Value of @ref CRC_RegStruct. + * @retval None. + */ +static inline void DCL_CRC_WaitComplete(const CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + while (crcx->CRC_CTRL_STATUS.BIT.crc_fifo_empty != BASE_CFG_SET) { + } + while (crcx->CRC_CTRL_STATUS.BIT.crc_fifo_empty != BASE_CFG_SET) { + } +} + +/** + * @brief Get fifo empty flag. + * @param crcx Value of @ref CRC_RegStruct. + * @retval bool of fifo empty flag. + */ +static inline bool DCL_CRC_GetFifoEmptyFlag(const CRC_RegStruct *crcx) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + return crcx->CRC_CTRL_STATUS.BIT.crc_fifo_empty; +} + +/** + * @brief Check crc algorithm mode. + * @param mode Value of @ref CRC_AlgorithmMode. + * @retval Bool + */ +static inline bool IsCrcAlgorithm(CRC_AlgorithmMode mode) +{ + /* Check crc algorithm mode. */ + return (mode == CRC8_ROHC || \ + mode == CRC16_IBM || \ + mode == CRC16_MODBUS || \ + mode == CRC16_CCITT_FALSE || \ + mode == CRC16_XMODEM || \ + mode == CRC32); +} + +/** + * @brief Check crc valid byte mode. + * @param mode Value of @ref CRC_InputDataFormat. + * @retval Bool + */ +static inline bool IsCrcInputDataFormat(CRC_InputDataFormat mode) +{ + return (mode == CRC_MODE_BIT8 || + mode == CRC_MODE_BIT16 || + mode == CRC_MODE_BIT24 || + mode == CRC_MODE_BIT32); +} + +/** + * @brief Check crc init value type. + * @param mode Value of @ref CRC_InitValueType. + * @retval Bool + */ +static inline bool IsCrcInitValueType(CRC_InitValueType mode) +{ + /* Check crc init value. */ + return (mode == TYPE_CRC_INIT_VALUE_FF || mode == TYPE_CRC_INIT_VALUE_0000 || \ + mode == TYPE_CRC_INIT_VALUE_FFFF || mode == TYPE_CRC_INIT_VALUE_FFFFFFFF); +} + +/** + * @brief Check crc polynomial mode. + * @param mode Value of @ref CRC_PolynomialMode. + * @retval Bool + */ +static inline bool IsCrcPolynomial(CRC_PolynomialMode mode) +{ + /* Check crc polynomial mode. */ + return (mode == CRC8_07_POLY_MODE || mode == CRC8_07_POLY_MODE_BK || \ + mode == CRC16_8005_POLY_MODE || mode == CRC16_1021_POLY_MODE || \ + mode == CRC32_04C11D87_POLY_MODE || mode == CRC32_04C11D87_POLY_MODE_BK); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_CRC_IP_H */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/crc/src/crc.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/crc/src/crc.c new file mode 100644 index 00000000..6889954a --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/crc/src/crc.c @@ -0,0 +1,432 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file crc.c + * @author MCU Driver Team + * @brief CRC module driver + * @details This file provides firmware functions to manage the following functionalities of the GPIO. + * + Initialization functions. + * + CRC Set And Get Functions. + * + Interrupt Handler Functions. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "crc.h" + +#define WORD_DIV_BYTE_SIZE 4 +#define WORD_DIV_DOUBLE_SIZE 2 + +#define OFFSET_ONE_BYTE 1 +#define OFFSET_TWO_BYTE 2 +#define OFFSET_THREE_BYTE 3 + +#define BIT_SHIFT24 24 +#define BIT_SHIFT16 16 +#define BIT_SHIFT8 8 + +#define REMAINDER_SIZE_ONE 1 +#define REMAINDER_SIZE_TWO 2 +#define REMAINDER_SIZE_THREE 3 +#define REMAINDER_RANGE_THREE 3 +#define REMAINDER_RANGE_ONE 1 + +static void CRC_Handle_8(CRC_Handle *handle, const unsigned char *pData, unsigned int length); +static void CRC_Handle_16(CRC_Handle *handle, const unsigned short *pData, unsigned int length); +static void CRC_Handle_32(CRC_Handle *handle, const unsigned int *pData, unsigned int length); +static void CRC_SetPolynomialModeByAlgorithm(CRC_RegStruct *crcx, CRC_AlgorithmMode algorithmMode); +static void CRC_SetInitValueByAlgorithm(CRC_RegStruct *crcx, CRC_AlgorithmMode algorithmMode); +static void CRC_SetPolynomialMode(CRC_Handle *handle, CRC_PolynomialMode polynomialMode); +static void CRC_SetInitValue(CRC_Handle *handle, CRC_InitValueType type); + +/** + * @brief Initializing CRC register values. + * @param handle Value of @ref CRC_Handle. + * @retval BASE_StatusType: OK, ERROR. + */ +BASE_StatusType HAL_CRC_Init(CRC_Handle *handle) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + CRC_PARAM_CHECK_WITH_RET(IsCrcInputDataFormat(handle->inputDataFormat), BASE_STATUS_ERROR); + DCL_CRC_SoftReset(handle->baseAddress); + DCL_CRC_SetByteMode(handle->baseAddress, handle->inputDataFormat); + /* Set the polynomial and initial value by algorithm mode */ + if (IsCrcAlgorithm(handle->handleEx.algoMode)) { + CRC_SetInitValueByAlgorithm(handle->baseAddress, handle->handleEx.algoMode); + CRC_SetPolynomialModeByAlgorithm(handle->baseAddress, handle->handleEx.algoMode); + } else { /* Set the polynomial and initial value by algorithm attribute */ + CRC_SetPolynomialMode(handle, handle->polyMode); + CRC_SetInitValue(handle, handle->initValueType); + } + DCL_CRC_SetTimeOut(handle->baseAddress, handle->handleEx.timeout); + /* enable CRC interrupt */ + handle->baseAddress->CRC_CTRL_INTMASK.BIT.pready_timeout_int_mask = handle->handleEx.enableIT ? \ + BASE_CFG_UNSET : BASE_CFG_SET; + /* enable CRC error inject */ + handle->baseAddress->CRC_CTRL_ERRINJ.BIT.time_out_err_inj = handle->handleEx.enableErrInject ? \ + BASE_CFG_SET : BASE_CFG_UNSET; + return BASE_STATUS_OK; +} + +/** + * @brief DeInitializing CRC register values. + * @param handle Value of @ref CRC_Handle. + * @retval None. + */ +void HAL_CRC_DeInit(CRC_Handle *handle) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + /* Reset CRC calculation data */ + handle->baseAddress->crc_data_in = 0x00000000; + /* Reset CRC init value */ + handle->baseAddress->CRC_CTRL_CFG1.BIT.crc_init = BASE_CFG_SET; /* Reset CRC init value. */ + handle->baseAddress->CRC_CTRL_CFG2.BIT.crc_ld = BASE_CFG_SET; /* load CRC init value. */ + handle->userCallBack.PreadyTimeoutCallback = NULL; /* Clean callback */ +} + +/** + * @brief Set CRC input data and get CRC output. + * @param handle Value of @ref CRC_Handle. + * @param data CRC input data. + * @retval unsigned int CRC output data. + */ +unsigned int HAL_CRC_SetInputDataGetCheck(CRC_Handle *handle, unsigned int data) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + handle->baseAddress->crc_data_in = data; /* Set CRC input data */ + DCL_CRC_WaitComplete(handle->baseAddress); /* wait crc cpmplete */ + return handle->baseAddress->crc_out; +} + +/** + * @brief Compute the 8, 16 or 32-bit CRC value of an 8, 16 or + 32-bit data buffer starting with the previously computed CRC as initialization value. + * @param handle Value of @ref CRC_Handle. + * @param pData Pointer to the input data buffer. + * @param length pData array length. + * @retval unsigned int CRC output data. + */ +unsigned int HAL_CRC_Accumulate(CRC_Handle *handle, const void *pData, unsigned int length) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(pData != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + switch (handle->inputDataFormat) { + case CRC_MODE_BIT8: + CRC_Handle_8(handle, (unsigned char *)pData, length); /* Input register to compute 8-bit data value */ + break; + case CRC_MODE_BIT16: + CRC_Handle_16(handle, (unsigned short *)pData, length); /* Input register to compute 16-bit data value */ + break; + case CRC_MODE_BIT32: + CRC_Handle_32(handle, (unsigned int *)pData, length); /* Input register to compute 32-bit data value */ + break; + default: + break; + } + DCL_CRC_WaitComplete(handle->baseAddress); + return handle->baseAddress->crc_out; +} + +/** + * @brief Compute the 8, 16 or 32-bit CRC value of an 8, 16 or + 32-bit data buffer starting with default initialization value. + * @param handle Value of @ref CRC_Handle. + * @param pData Pointer to the input data buffer. + * @param length pData array length. + * @retval unsigned int CRC output data. + */ +unsigned int HAL_CRC_Calculate(CRC_Handle *handle, const void *pData, unsigned int length) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(pData != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + DCL_CRC_SoftReset(handle->baseAddress); /* Reset CRC init value. */ + DCL_CRC_LoadInitValue(handle->baseAddress); /* load CRC init value. */ + return HAL_CRC_Accumulate(handle, pData, length); +} + +/** + * @brief Compute the 8-bit input data to the CRC calculator. + * @param handle Value of @ref CRC_Handle. + * @param pData Pointer to the input data buffer. + * @param length pData array length. + * @retval unsigned int CRC output data. + */ +static void CRC_Handle_8(CRC_Handle *handle, const unsigned char *pData, unsigned int length) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(pData != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + unsigned int i = 0; + for (i = 0; i < (length / WORD_DIV_BYTE_SIZE); i++) { + DCL_CRC_SetByteMode(handle->baseAddress, CRC_MODE_BIT32); + /* Data concatenation */ + handle->baseAddress->crc_data_in = \ + ((unsigned int)pData[WORD_DIV_BYTE_SIZE * i] << BIT_SHIFT24) | \ + ((unsigned int)pData[WORD_DIV_BYTE_SIZE * i + OFFSET_ONE_BYTE] << BIT_SHIFT16) | \ + ((unsigned int)pData[WORD_DIV_BYTE_SIZE * i + OFFSET_TWO_BYTE] << BIT_SHIFT8) | \ + (unsigned int)pData[WORD_DIV_BYTE_SIZE * i + OFFSET_THREE_BYTE]; + } + if ((length & REMAINDER_RANGE_THREE) != 0) { + if ((length & REMAINDER_RANGE_THREE) == REMAINDER_SIZE_ONE) { /* remainder : 1 */ + DCL_CRC_SetByteMode(handle->baseAddress, CRC_MODE_BIT8); + handle->baseAddress->crc_data_in = pData[WORD_DIV_BYTE_SIZE * i]; + } + if ((length & REMAINDER_RANGE_THREE) == REMAINDER_SIZE_TWO) { /* remainder : 2 */ + DCL_CRC_SetByteMode(handle->baseAddress, CRC_MODE_BIT16); + /* Data concatenation */ + handle->baseAddress->crc_data_in = \ + ((unsigned int)pData[WORD_DIV_BYTE_SIZE * i] << BIT_SHIFT8) | \ + (unsigned int)pData[WORD_DIV_BYTE_SIZE * i + OFFSET_ONE_BYTE]; + } + if ((length & REMAINDER_RANGE_THREE) == REMAINDER_SIZE_THREE) { /* remainder : 3 */ + DCL_CRC_SetByteMode(handle->baseAddress, CRC_MODE_BIT24); + /* Data concatenation */ + handle->baseAddress->crc_data_in = \ + ((unsigned int)pData[WORD_DIV_BYTE_SIZE * i] << BIT_SHIFT16) | \ + ((unsigned int)pData[WORD_DIV_BYTE_SIZE * i + OFFSET_ONE_BYTE] << BIT_SHIFT8) | \ + (unsigned int)pData[WORD_DIV_BYTE_SIZE * i + OFFSET_TWO_BYTE]; + } + } + DCL_CRC_SetByteMode(handle->baseAddress, CRC_MODE_BIT8); +} + +/** + * @brief Compute the 16-bit input data to the CRC calculator. + * @param handle Value of @ref CRC_Handle. + * @param pData Pointer to the input data buffer. + * @param length pData array length. + * @retval unsigned int CRC output data. + */ +static void CRC_Handle_16(CRC_Handle *handle, const unsigned short *pData, unsigned int length) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(pData != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + unsigned int i = 0; + for (i = 0; i < (length / WORD_DIV_DOUBLE_SIZE); i++) { + DCL_CRC_SetByteMode(handle->baseAddress, CRC_MODE_BIT32); + /* Data concatenation */ + handle->baseAddress->crc_data_in = \ + ((unsigned int)pData[WORD_DIV_DOUBLE_SIZE * i] << BIT_SHIFT16) | \ + (unsigned int)pData[WORD_DIV_DOUBLE_SIZE * i + OFFSET_ONE_BYTE]; + } + if ((length & REMAINDER_RANGE_ONE) != 0) { /* remainder bot equal zero */ + DCL_CRC_SetByteMode(handle->baseAddress, CRC_MODE_BIT16); + handle->baseAddress->crc_data_in = (unsigned int)pData[WORD_DIV_DOUBLE_SIZE * i]; + } + DCL_CRC_SetByteMode(handle->baseAddress, CRC_MODE_BIT16); +} + +/** + * @brief Compute the 32-bit input data to the CRC calculator. + * @param handle Value of @ref CRC_Handle. + * @param pData Pointer to the input data buffer. + * @param length pData array length. + * @retval unsigned int CRC output data. + */ +static void CRC_Handle_32(CRC_Handle *handle, const unsigned int *pData, unsigned int length) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(pData != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + for (unsigned int i = 0; i < length; i++) { + handle->baseAddress->crc_data_in = pData[i]; /* input crc data */ + } +} + +/** + * @brief Check whether the received data CRC value is the same as the expected value. + * @param handle Value of @ref CRC_Handle. + * @param pData Pointer to the input data buffer, + exact input data byte mode is provided by handle->inputDataFormat. + * @param length pData array length. + * @param crcValue CRC check value. + * @retval unsigned int CRC check result + */ +bool HAL_CRC_CheckInputData(CRC_Handle *handle, const void *pData, unsigned int length, unsigned int crcValue) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(pData != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + return (HAL_CRC_Calculate(handle, pData, length) == crcValue); +} + +/** + * @brief Set CRC check_in data to register. + * @param handle Value of @ref CRC_Handle. + * @retval None. + */ +void HAL_CRC_SetCheckInData(CRC_Handle *handle, unsigned int data) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + handle->baseAddress->crc_check_in = data; +} + +/** + * @brief Load CRC check_in register data to crc_out register. + * @param handle Value of @ref CRC_Handle. + * @retval unsigned int Reversed check_in data. + */ +unsigned int HAL_CRC_LoadCheckInData(CRC_Handle *handle) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + handle->baseAddress->CRC_CTRL_CFG2.BIT.crc_ld = BASE_CFG_SET; + return handle->baseAddress->crc_out; +} + +/** + * @brief Register CRC interrupt callback. + * @param handle Value of @ref CRC_handle. + * @param callBackFunc Value of @ref CRC_CallbackType. + * @retval None + */ +void HAL_CRC_RegisterCallback(CRC_Handle *handle, CRC_CallbackType callBackFunc) +{ + CRC_ASSERT_PARAM(handle != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + handle->userCallBack.PreadyTimeoutCallback = callBackFunc; +} + +/** + * @brief Interrupt handler processing function. + * @param handle CRC_Handle. + * @retval None. + */ +void HAL_CRC_IrqHandler(void *handle) +{ + CRC_Handle *crcHandle = (CRC_Handle *)handle; + CRC_ASSERT_PARAM(crcHandle != NULL); + CRC_ASSERT_PARAM(IsCRCInstance(crcHandle->baseAddress)); + + if (crcHandle->baseAddress->CRC_CTRL_INT.BIT.pready_timeout == 0x01) { + crcHandle->baseAddress->CRC_CTRL_INT.BIT.pready_timeout = BASE_CFG_SET; /* Clear pready_timeout IRQ */ + if (crcHandle->userCallBack.PreadyTimeoutCallback) { + crcHandle->userCallBack.PreadyTimeoutCallback(crcHandle); + } + } +} + +/** + * @brief Set crc polynomial mode by algorithm. + * @param crcx Value of @ref CRC_Handle. + * @param algorithmMode CRC algorithm mode. + * @retval None. + */ +static void CRC_SetPolynomialModeByAlgorithm(CRC_RegStruct *crcx, CRC_AlgorithmMode algorithmMode) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + CRC_PARAM_CHECK_NO_RET(algorithmMode < CRC_ALG_MODE_MAX); + /* Matching enumerated values with register configuration values */ + unsigned int polyMode = CRC_POLY_MODE_MAX; + if (algorithmMode == CRC8_ROHC) { + polyMode = CRC8_07_POLY_MODE; + } else if (algorithmMode == CRC16_XMODEM || algorithmMode == CRC16_CCITT_FALSE) { + polyMode = CRC16_1021_POLY_MODE; + } else if (algorithmMode == CRC16_IBM || algorithmMode == CRC16_MODBUS) { + polyMode = CRC16_8005_POLY_MODE; + } else if (algorithmMode == CRC32) { + polyMode = CRC32_04C11D87_POLY_MODE; + } + /* config register */ + DCL_CRC_SetPolynomialMode(crcx, polyMode); +} + +/** + * @brief Set CRC init value by algorithmMode. + * @param crc Value of @ref CRC_RegStruct. + * @param algorithmMode value of CRC algorithm. + * @retval None. + */ +static void CRC_SetInitValueByAlgorithm(CRC_RegStruct *crcx, CRC_AlgorithmMode algorithmMode) +{ + CRC_ASSERT_PARAM(IsCRCInstance(crcx)); + CRC_PARAM_CHECK_NO_RET(algorithmMode < CRC_ALG_MODE_MAX && algorithmMode >= CRC8_ROHC); + switch (algorithmMode) { + case CRC8_ROHC: + /* CRC8_ROHC init value is FF */ + *(unsigned char *)(void *)(&crcx->crc_check_in) = CRC_INIT_VALUE_FF; + break; + case CRC16_IBM: + *(unsigned short *)(void *)(&crcx->crc_check_in) = CRC_INIT_VALUE_0000; + break; + case CRC16_MODBUS: + /* CRC16_MODBUS init value is FFFF */ + *(unsigned short *)(void *)(&crcx->crc_check_in) = CRC_INIT_VALUE_FFFF; + break; + case CRC16_CCITT_FALSE: + *(unsigned short *)(void *)(&crcx->crc_check_in) = CRC_INIT_VALUE_FFFF; + break; + case CRC16_XMODEM: + /* CRC16_XMODEM init value is 0000 */ + *(unsigned short *)(void *)(&crcx->crc_check_in) = CRC_INIT_VALUE_0000; + break; + case CRC32: + *(unsigned int *)(void *)(&crcx->crc_check_in) = CRC_INIT_VALUE_FFFFFFFF; + break; + default: + break; + } + DCL_CRC_LoadInitValue(crcx); /* load init value */ +} + +/** + * @brief Set CRC Polynomial Mode by algorithmMode. + * @param handle Value of @ref CRC_Handle. + * @param polynomialMode CRC_PolynomialMode. + * @retval None. + */ +static void CRC_SetPolynomialMode(CRC_Handle *handle, CRC_PolynomialMode polynomialMode) +{ + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + CRC_PARAM_CHECK_NO_RET(IsCrcPolynomial(polynomialMode)); + DCL_CRC_SetPolynomialMode(handle->baseAddress, polynomialMode); +} + +/** + * @brief Set CRC init value. + * @param handle Value of @ref CRC_Handle. + * @param type Value of @ref CRC_InitValueType. + * @retval None. + */ +static void CRC_SetInitValue(CRC_Handle *handle, CRC_InitValueType type) +{ + CRC_ASSERT_PARAM(IsCRCInstance(handle->baseAddress)); + CRC_PARAM_CHECK_NO_RET(IsCrcInitValueType(type)); + switch (type) { + case TYPE_CRC_INIT_VALUE_FF: /* init value type 00 */ + *(unsigned char *)(void *)(&handle->baseAddress->crc_check_in) = CRC_INIT_VALUE_FF; + break; + case TYPE_CRC_INIT_VALUE_0000: /* init value type 0000 */ + *(unsigned short *)(void *)(&handle->baseAddress->crc_check_in) = CRC_INIT_VALUE_0000; + break; + case TYPE_CRC_INIT_VALUE_FFFF: + *(unsigned short *)(void *)(&handle->baseAddress->crc_check_in) = CRC_INIT_VALUE_FFFF; + break; + case TYPE_CRC_INIT_VALUE_FFFFFFFF: /* init value type FFFFFFFF */ + *(unsigned int *)(void *)(&handle->baseAddress->crc_check_in) = CRC_INIT_VALUE_FFFFFFFF; + break; + default: + break; + } +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/crg/common/inc/crg.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/crg/common/inc/crg.h new file mode 100644 index 00000000..ed10ef58 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/crg/common/inc/crg.h @@ -0,0 +1,123 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file crg.h + * @author MCU Driver Team + * @brief CRG module driver + * @details This file provides firmware CRG Handle Structure and functions + * prototypes to manage the following functionalities of the CRG. + * + Config CRG + * + Config IP Clock + * + Get the Config of CRG + * + Get the frequency of cpu and IP + */ +#ifndef McuMagicTag_CRG_H +#define McuMagicTag_CRG_H + +/* Includes ------------------------------------------------------------------*/ +#include "crg_ip.h" + +/* Macro definitions ---------------------------------------------------------*/ + +/** + * @defgroup CRG CRG + * @brief CRG module. + * @{ + */ + +/** + * @defgroup CRG_Common CRG Common + * @brief CRG common external module. + * @{ + */ + +/** + * @defgroup CRG_Handle_Definition CRG Handle Definition + * @{ + */ +/** + * @brief Typedef callback function of CRG + */ +typedef void (*CRG_CallBackFunc)(void *param); + +/** + * @brief CRG Handle, include clock config and ip clock ip config + */ +typedef struct { + CRG_RegStruct *baseAddress; /**< Base address of CLOCK register */ + CRG_PllRefClkSelect pllRefClkSelect; /**< PLL Refer clock selection */ + CRG_PllPreDiv pllPreDiv; /**< PLL pre division */ + unsigned int pllFbDiv; /**< PLL loop divider ratio */ + CRG_PllPostDiv pllPostDiv; /**< PLL post ratio */ + bool pllPd; /**< Pll Power down or not */ + CRG_CoreClkSelect coreClkSelect; /**< Core clock selection */ + CRG_ExtendHandle handleEx; /**< CRG handle extra */ +} CRG_Handle; +/** + * @} + */ + +/** + * @defgroup CRG_API_Declaration CRG HAL API + * @{ + */ +BASE_StatusType HAL_CRG_Init(const CRG_Handle *handle); + +BASE_StatusType HAL_CRG_DeInit(const CRG_Handle *handle); + +BASE_StatusType HAL_CRG_GetConfig(CRG_Handle *handle); + +BASE_StatusType HAL_CRG_SetCoreClockSelect(CRG_Handle *handle); + +BASE_StatusType HAL_CRG_InitWithTargetFrequence(const CRG_Handle *handle, unsigned int targetFreq); + +BASE_StatusType HAL_CRG_IpEnableSet(const void *baseAddress, unsigned int enable); + +BASE_StatusType HAL_CRG_IpEnableGet(const void *baseAddress, unsigned int *enable); + +BASE_StatusType HAL_CRG_IpClkSelectSet(const void *baseAddress, unsigned int select); + +BASE_StatusType HAL_CRG_IpClkSelectGet(const void *baseAddress, unsigned int *select); + +BASE_StatusType HAL_CRG_IpClkResetSet(const void *baseAddress, unsigned int reset); + +BASE_StatusType HAL_CRG_IpClkResetGet(const void *baseAddress, unsigned int *reset); + +BASE_StatusType HAL_CRG_IpClkDivSet(const void *baseAddress, unsigned int div); + +BASE_StatusType HAL_CRG_IpClkDivGet(const void *baseAddress, unsigned int *div); + +void HAL_CRG_PvdResetEnable(bool enable); + +unsigned int HAL_CRG_GetPllFreq(void); + +unsigned int HAL_CRG_GetCoreClkFreq(void); + +unsigned int HAL_CRG_GetIpFreq(const void *ipBaseAddr); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_CRG_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/crg/inc/crg_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/crg/inc/crg_ip.h new file mode 100644 index 00000000..b53d0d19 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/crg/inc/crg_ip.h @@ -0,0 +1,1260 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file crg_ip.h + * @author MCU Driver Team + * @brief TIMER module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the TIMER. + * + CRG register mapping structure + * + Direct Configuration Layer functions of CRG + */ +#ifndef McuMagicTag_CRG_IP_H +#define McuMagicTag_CRG_IP_H + +/* Includes ------------------------------------------------------------------*/ +#include "baseinc.h" + +/** + * @addtogroup CRG + * @{ + */ + +/** + * @defgroup CRG_IP CRG_IP + * @brief CRG_IP: crg_v0 + * @{ + */ + +/** + * @defgroup CRG_Param_Def CRG Parameters Definition + * @brief Definition of CRG configuration parameters. + * @{ + */ +#ifdef CRG_PARAM_CHECK +#define CRG_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define CRG_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define CRG_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define CRG_ASSERT_PARAM(para) ((void)0U) +#define CRG_PARAM_CHECK_NO_RET(para) ((void)0U) +#define CRG_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +#define IP_CLK_DISABLE 0x00000000U /**< IP Clock disable bitmask */ +#define IP_CLK_ENABLE 0x00000001U /**< IP Clock disable bitmask */ +#define IP_SYSCLK_ENABLE 0x00000002U /**< IP SysClock disable bitmask, Only valid for ADC */ + +#define DAC_DIV_BITLEN 4U /**< DIV bit length */ +#define DAC_DIV_MASK ((1 << DAC_DIV_BITLEN) - 1) /**< DAC div mask, base on the bit length */ + +#define ADC_DIV_FACTOR (1 << 1) /**< ADC div min factor */ + +#define CRG_FREQ_1MHz (1000 * 1000) +#define CRG_CLK_PFD_MIN_FREQ (4 * CRG_FREQ_1MHz) +#define CRG_CLK_PFD_MAX_FREQ (75 * CRG_FREQ_1MHz / 10) +#define CRG_CLK_VCO_MIN_FREQ (100 * CRG_FREQ_1MHz) +#define CRG_CLK_VCO_MAX_FREQ (200 * CRG_FREQ_1MHz) +#define CRG_CLK_TARGET_MIN_FREQ (3125 * 1000) +#define CRG_CLK_TARGET_MAX_FREQ (200 * CRG_FREQ_1MHz) +#define CRG_CLK_XTAL_MIN_FREQ (2 * CRG_FREQ_1MHz) +#define CRG_CLK_XTAL_MAX_FREQ (30 * CRG_FREQ_1MHz) +/** + * @brief PLL refer clock Select + */ +typedef enum { + CRG_PLL_REF_CLK_SELECT_HOSC = 0, + CRG_PLL_REF_CLK_SELECT_XTAL = 1, +} CRG_PllRefClkSelect; + +/** + * @brief PLL previous division value in register + */ +typedef enum { + CRG_PLL_NO_PREDV = 0, + CRG_PLL_PREDIV_1 = 1, + CRG_PLL_PREDIV_2 = 2, + CRG_PLL_PREDIV_4 = 3, +} CRG_PllPreDiv; + +/** + * @brief PLL previous division value in Calc frequency + */ +typedef enum { + PLL_PREDIV_OUT_1 = 1, + PLL_PREDIV_OUT_2 = 2, + PLL_PREDIV_OUT_4 = 4, +} PLL_PreDivOut; + +/** + * @brief PLL post division value in register + */ +typedef enum { + CRG_PLL_POSTDIV_1 = 0, + CRG_PLL_POSTDIV_2 = 1, + CRG_PLL_POSTDIV_4 = 2, + CRG_PLL_POSTDIV_8 = 3, + CRG_PLL_POSTDIV_16 = 4, + CRG_PLL_POSTDIV_32 = 5, + CRG_PLL_POSTDIV_32_MAX = 7, +} CRG_PllPostDiv; + +/** + * @brief Core clock selection + * @note CRG_CORE_CLK_SELECT_LOSC will be selected under other invalid conditions + */ +typedef enum { + CRG_CORE_CLK_SELECT_HOSC = 0, + CRG_CORE_CLK_SELECT_TCXO = 1, + CRG_CORE_CLK_SELECT_PLL = 2, +} CRG_CoreClkSelect; + +/** + * @brief PLL frequency multiplication range + */ +typedef enum { + CRG_PLL_FBDIV_MIN = 6, + CRG_PLL_FBDIV_MAX = 63, +} CRG_PllFbDivRange; + +/** + * @brief PLL diagnose post div selection + */ +typedef enum { + CRG_PLL_DIG_POST_DIV_SELECT_FREF = 0, + CRG_PLL_DIG_POST_DIV_SELECT_PLL = 1, +} CRG_PllDigPostDivInSelect; + +/** + * @brief PLL diagnose loct detect lpsel + */ +typedef enum { + CRG_PLL_DIG_LOCKDET_LP_SELECT_2048 = 0, + CRG_PLL_DIG_LOCKDET_LP_SELECT_1024 = 1, + CRG_PLL_DIG_LOCKDET_LP_SELECT_512 = 2, + CRG_PLL_DIG_LOCKDET_LP_SELECT_256 = 3, +} CRG_PllDigLockDetLpSelect; + +/** + * @brief PLL Test selection + */ +typedef enum { + CRG_PLL_TEST_SELECT_PFD = 0, + CRG_PLL_TEST_SELECT_PLL_DIV_128 = 3, +} CRG_PllTestClkSelect; + +/** + * @brief Source clock selection of ip in APB_LS_SUBSYS + */ +typedef enum { + CRG_CLK_LS = 0, + CRG_CLK_LS_DIV_2 = 1, + CRG_CLK_LS_DIV_4 = 2, + CRG_CLK_LS_DIV_8 = 3, +} CRG_APBLsClkSelect; + +/** + * @brief ADC source clock select + */ +typedef enum { + CRG_ADC_CLK_SELECT_HOSC = 0, + CRG_ADC_CLK_SELECT_TCXO = 1, + CRG_ADC_CLK_SELECT_PLL_DIV = 2, +} CRG_AdcClkSelect; + +/** + * @brief ADC Div set Value + */ +typedef enum { + CRG_ADC_DIV_1 = 0, + CRG_ADC_DIV_1_P_5 = 1, + CRG_ADC_DIV_2 = 2, + CRG_ADC_DIV_2_P_5 = 3, + CRG_ADC_DIV_3 = 4, + CRG_ADC_DIV_3_P_5 = 5, + CRG_ADC_DIV_4 = 6, + CRG_ADC_DIV_4_P_5 = 7, + CRG_ADC_DIV_5 = 8, + CRG_ADC_DIV_5_P_5 = 9, + CRG_ADC_DIV_6 = 10, + CRG_ADC_DIV_6_P_5 = 11, + CRG_ADC_DIV_7 = 12, + CRG_ADC_DIV_7_P_5 = 13, + CRG_ADC_DIV_8 = 14, + CRG_ADC_DIV_8_P_5 = 15, + CRG_ADC_DIV_9 = 16, + CRG_ADC_DIV_9_P_5 = 17, + CRG_ADC_DIV_10 = 18, + CRG_ADC_DIV_10_P_5 = 19, + CRG_ADC_DIV_11 = 20, + CRG_ADC_DIV_11_P_5 = 21, + CRG_ADC_DIV_12 = 22, + CRG_ADC_DIV_12_P_5 = 23, + CRG_ADC_DIV_13 = 24, + CRG_ADC_DIV_13_P_5 = 25, + CRG_ADC_DIV_14 = 26, + CRG_ADC_DIV_14_P_5 = 27, + CRG_ADC_DIV_15 = 28, + CRG_ADC_DIV_15_P_5 = 29, + CRG_ADC_DIV_16 = 30, + CRG_ADC_DIV_16_P_5 = 31, +} CRG_AdcDiv; + +/** + * @brief DAC Div set Value + */ +typedef enum { + CRG_DAC_DIV_1 = 0, + CRG_DAC_DIV_2 = 1, + CRG_DAC_DIV_3 = 2, + CRG_DAC_DIV_4 = 3, + CRG_DAC_DIV_5 = 4, + CRG_DAC_DIV_6 = 5, + CRG_DAC_DIV_7 = 6, + CRG_DAC_DIV_8 = 7, + CRG_DAC_DIV_9 = 8, + CRG_DAC_DIV_10 = 9, + CRG_DAC_DIV_11 = 10, + CRG_DAC_DIV_12 = 11, + CRG_DAC_DIV_13 = 12, + CRG_DAC_DIV_14 = 13, + CRG_DAC_DIV_15 = 14, + CRG_DAC_DIV_16 = 15, +} CRG_DacDiv; + +/** + * @brief CRG Test Clock Select + */ +typedef enum { + CRG_TEST_CLK_PLL = 0x00000000U, + CRG_TEST_CLK_HOSC = 0x00000001U, + CRG_TEST_CLK_LOSC = 0x00000002U, + CRG_TEST_CLK_XTAL = 0x00000003U, + CRG_TEST_CLK_DAC0 = 0x00000004U, + CRG_TEST_CLK_DAC1 = 0x00000005U, + CRG_TEST_CLK_DAC2 = 0x00000006U, + CRG_TEST_CLK_ADC0 = 0x00000007U, + CRG_TEST_CLK_ADC1 = 0x00000008U, + CRG_TEST_CLK_ADC2 = 0x00000009U, +} CRG_TestClkSel; + +/** + * @brief CRG Extra Handle, include CRG's other config + */ +typedef struct { + bool ckSwitchEn; /**< Clock switch interactive function enable */ +} CRG_ExtendHandle; + +/** + * @brief PLL Division Config + */ +typedef struct { + unsigned int PreDiv; /**< prescale division */ + unsigned int fbDiv; /**< feedback division */ + unsigned int postDiv; /**< post division */ +} CRG_PllDivCfg; + +/** + * @brief APB_LS_SUBSYS IP config + */ +typedef union { + unsigned int value; + struct { + unsigned int cken : 1; + unsigned int reserved_0 : 7; + unsigned int cksel : 2; + unsigned int reserved_1 : 6; + unsigned int srst_req : 1; + unsigned int reserved_2 : 15; + } BIT; +} volatile CRG_IpWithClkSelectCfg; + +/** + * @brief APB_HS_SUBSYS IP config + */ +typedef union { + unsigned int value; + struct { + unsigned int clkEnMask : 16; + unsigned int softResetReq : 16; + } BIT; +} volatile CRG_IpWoClkSelectCfg; + +/** + * @brief ADC config + * @see PERI_CRG41_Reg and PERI_CRG42_Reg and PERI_CRG43_Reg + */ +typedef union { + unsigned int value; + struct { + unsigned int cken : 1; + unsigned int sys_cken : 1; + unsigned int reserved_0 : 2; + unsigned int div : 5; + unsigned int reserved_1 : 3; + unsigned int cksel : 2; + unsigned int reserved_2 : 2; + unsigned int srst_req : 1; + unsigned int sys_srst_req : 1; + unsigned int ana_srst_req : 1; + unsigned int reserved_3 : 13; + } BIT; +} volatile CRG_AdcIpCfg; + +/** + * @brief DAC config + * @see PERI_CRG45_Reg + */ +typedef union { + unsigned int value; + struct { + unsigned int clkEnMask : 3; + unsigned int reserved_0 : 1; + unsigned int div : 12; + unsigned int softResetReq : 3; + unsigned int reserved_1 : 13; + } BIT; +} volatile CRG_DacIpCfg; + +/** + * @brief IP match info for ip process + */ +typedef struct { + void *baseAddr; /**< Base address of ip */ + unsigned int offset; /**< The offset in CRG_RegStruct */ + unsigned int idx; /**< index in Reg, for example: 0 -capm0_cken 1 - capm1_cken in PERI_CRG30_Reg */ +} CRG_IpMatchInfo; + +/** + * @} + */ + +/** + * @defgroup CRG_Reg_Def CRG Register Definition + * @brief register mapping structure + * @{ + */ +typedef struct { + unsigned int pll_ref_cksel : 1; /**< pll reference select */ + unsigned int reserved_0 : 31; +} volatile PERI_CRG0_Reg; + +typedef struct { + unsigned int pll_prediv : 4; /**< predivider value */ + unsigned int reserved_0 : 28; +} volatile PERI_CRG1_Reg; + +typedef struct { + unsigned int pll_fbdiv : 8; /**< feedback divider value */ + unsigned int reserved_0 : 24; +} volatile PERI_CRG2_Reg; + +typedef struct { + unsigned int pll_postdiv : 4; /**< post divider value */ + unsigned int reserved_0 : 28; +} volatile PERI_CRG3_Reg; + +typedef struct { + unsigned int pll_pd : 1; /**< pll power down */ + unsigned int reserved_0 : 31; +} volatile PERI_CRG4_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int reserved0 : 13; + unsigned int pll_dig_eb_lockdet : 1; /**< lock detector window size */ + unsigned int reserved_0 : 18; + } BIT; +} volatile PERI_CRG5_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int reserved0 : 19; + unsigned int pll_test_clk : 3; /**< pll test clock */ + unsigned int reserved1 : 10; + } BIT; +} volatile PERI_CRG6_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int core_cksel : 2; /**< core clock select */ + unsigned int reserved0 : 1; + unsigned int ck_switchen : 1; /**< clock switch enable */ + unsigned int reserved : 28; + } BIT; +} volatile PERI_CRG7_Reg; + +typedef struct { + unsigned int pll_lock : 1; /**< pll clock */ + unsigned int reserved : 31; +} volatile PERI_CRG8_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int uart0_cken : 1; /**< uart0 clock enable */ + unsigned int reserved_0 : 7; + unsigned int uart0_cksel : 2; /**< uart0 clock select */ + unsigned int reserved_1 : 6; + unsigned int uart0_srst_req : 1; /**< uart0 reset request */ + unsigned int reserved_2 : 15; + } BIT; +} volatile PERI_CRG20_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int uart1_cken : 1; /**< uart1 clock enable */ + unsigned int reserved_0 : 7; + unsigned int uart1_cksel : 2; /**< uart1 clock select */ + unsigned int reserved_1 : 6; + unsigned int uart1_srst_req : 1; /**< uart1 reset request */ + unsigned int reserved_2 : 15; + } BIT; +} volatile PERI_CRG21_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int uart2_cken : 1; /**< uart2 clock enable */ + unsigned int reserved_0 : 7; + unsigned int uart2_cksel : 2; /**< uart2 clock select */ + unsigned int reserved_1 : 6; + unsigned int uart2_srst_req : 1; /**< uart2 reset request */ + unsigned int reserved_2 : 15; + } BIT; +} volatile PERI_CRG22_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int timer01_cken : 1; /**< timer0/1 clock enable */ + unsigned int reserved_2 : 7; + unsigned int timer01_cksel : 2; /**< timer0/1 clock select */ + unsigned int reserved_0 : 6; + unsigned int timer01_srst_req : 1; /**< timer0/1 reset request */ + unsigned int reserved_1 : 15; + } BIT; +} volatile PERI_CRG23_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int timer23_cken : 1; /**< timer2/3 clock enable */ + unsigned int reserved_0 : 7; + unsigned int timer23_cksel : 2; /**< timer2/3 clock select */ + unsigned int reserved_1 : 6; + unsigned int timer23_srst_req : 1; /**< timer2/3 reset request */ + unsigned int reserved_2 : 15; + } BIT; +} volatile PERI_CRG24_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int pwm0_cken : 1; /**< gpt0 clock enable */ + unsigned int reserved_0 : 7; + unsigned int pwm0_cksel : 2; /**< gpt0 clock select */ + unsigned int reserved_1 : 6; + unsigned int pwm0_srst_req : 1; /**< gpt0 reset request */ + unsigned int reserved_2 : 15; + } BIT; +} volatile PERI_CRG25_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int pwm1_cken : 1; /**< gpt1 clock enable */ + unsigned int reserved_0 : 7; + unsigned int pwm1_cksel : 2; /**< gpt1 clock select */ + unsigned int reserved_1 : 6; + unsigned int pwm1_srst_req : 1; /**< gpt1 reset request */ + unsigned int reserved_2 : 15; + } BIT; +} volatile PERI_CRG26_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int wdog_cken : 1; /**< watchdog clock enable */ + unsigned int reserved_0 : 7; + unsigned int wdog_cksel : 2; /**< watchdog clock select */ + unsigned int reserved_1 : 6; + unsigned int wdog_srst_req : 1; /**< watchdog reset request */ + unsigned int reserved_2 : 15; + } BIT; +} volatile PERI_CRG27_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int ssp_cken : 1; /**< spi clock enable */ + unsigned int reserved_0 : 7; + unsigned int ssp_cksel : 2; /**< spi clock select */ + unsigned int reserved_1 : 6; + unsigned int ssp_srst_req : 1; /**< spi reset request */ + unsigned int reserved_2 : 15; + } BIT; +} volatile PERI_CRG28_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int can_cken : 1; /**< can clock enable */ + unsigned int reserved_1 : 15; + unsigned int can_srst_req : 1; /**< can reset request */ + unsigned int reserved_0 : 15; + } BIT; +} volatile PERI_CRG29_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int capm0_cken : 1; /**< capm0 clock enable */ + unsigned int capm1_cken : 1; /**< capm1 clock enable */ + unsigned int capm2_cken : 1; /**< capm0 clock enable */ + unsigned int reserved_1 : 13; + unsigned int capm0_srst_req : 1; /**< capm0 reset request */ + unsigned int capm1_srst_req : 1; /**< capm1 reset request */ + unsigned int capm2_srst_req : 1; /**< capm2 reset request */ + unsigned int reserved_0 : 13; + } BIT; +} volatile PERI_CRG30_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int dma_cken : 1; /**< dma clock enable */ + unsigned int reserved_0 : 15; + unsigned int dma_srst_req : 1; /**< dma reset request */ + unsigned int reserved_1 : 15; + } BIT; +} volatile PERI_CRG31_Reg; + +typedef struct { + unsigned int eflash_cken : 1; /**< flash clock enable */ + unsigned int reserved : 31; +} volatile PERI_CRG32_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int gpio0_cken : 1; /**< gpio0 clock enable */ + unsigned int gpio1_cken : 1; /**< gpio1 clock enable */ + unsigned int gpio2_cken : 1; /**< gpio2 clock enable */ + unsigned int gpio3_cken : 1; /**< gpio3 clock enable */ + unsigned int gpio4_cken : 1; /**< gpio4 clock enable */ + unsigned int gpio5_cken : 1; /**< gpio5 clock enable */ + unsigned int gpio6_cken : 1; /**< gpio6 clock enable */ + unsigned int gpio7_cken : 1; /**< gpio7 clock enable */ + unsigned int reserved_0 : 8; + unsigned int gpio0_srst_req : 1; /**< gpio0 reset request */ + unsigned int gpio1_srst_req : 1; /**< gpio1 reset request */ + unsigned int gpio2_srst_req : 1; /**< gpio2 reset request */ + unsigned int gpio3_srst_req : 1; /**< gpio3 reset request */ + unsigned int gpio4_srst_req : 1; /**< gpio4 reset request */ + unsigned int gpio5_srst_req : 1; /**< gpio5 reset request */ + unsigned int gpio6_srst_req : 1; /**< gpio6 reset request */ + unsigned int gpio7_srst_req : 1; /**< gpio7 reset request */ + unsigned int reserved_1 : 8; /**< gpio8 reset request */ + } BIT; +} volatile PERI_CRG33_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int i2c_cken : 1; /**< i2c clock enable */ + unsigned int reserved_0 : 15; + unsigned int i2c_srst_req : 1; /**< i2c reset request */ + unsigned int reserved_1 : 15; + } BIT; +} volatile PERI_CRG34_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int iwdog_cken : 1; /**< iwdog clock enable */ + unsigned int reserved_1 : 15; + unsigned int iwdog_srst_req : 1; /**< iwdog reset request */ + unsigned int reserved_0 : 15; + } BIT; +} volatile PERI_CRG35_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int qdm0_cken : 1; /**< clock enable */ + unsigned int reserved_0 : 15; + unsigned int qdm0_srst_req : 1; /**< reset request */ + unsigned int reserved_1 : 14; + } BIT; +} volatile PERI_CRG36_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int cs_cken : 1; /**< clock enable */ + unsigned int reserved_0 : 31; + } BIT; +} volatile PERI_CRG38_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int crc_cken : 1; /**< clock enable */ + unsigned int reserved_0 : 15; + unsigned int crc_srst_req : 1; /**< reset request */ + unsigned int reserved_1 : 15; + } BIT; +} volatile PERI_CRG39_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int apt0_cken : 1; /**< apt0 clock enable */ + unsigned int apt1_cken : 1; /**< apt1 clock enable */ + unsigned int apt2_cken : 1; /**< apt2 clock enable */ + unsigned int apt3_cken : 1; /**< apt3 clock enable */ + unsigned int apt4_cken : 1; /**< apt4 clock enable */ + unsigned int apt5_cken : 1; /**< apt5 clock enable */ + unsigned int apt6_cken : 1; /**< apt6 clock enable */ + unsigned int apt7_cken : 1; /**< apt7 clock enable */ + unsigned int apt8_cken : 1; /**< apt8 clock enable */ + unsigned int reserved_0 : 7; + unsigned int apt0_srst_req : 1; /**< apt0 reset request */ + unsigned int apt1_srst_req : 1; /**< apt1 reset request */ + unsigned int apt2_srst_req : 1; /**< apt2 reset request */ + unsigned int apt3_srst_req : 1; /**< apt3 reset request */ + unsigned int apt4_srst_req : 1; /**< apt4 reset request */ + unsigned int apt5_srst_req : 1; /**< apt5 reset request */ + unsigned int apt6_srst_req : 1; /**< apt6 reset request */ + unsigned int apt7_srst_req : 1; /**< apt7 reset request */ + unsigned int apt8_srst_req : 1; /**< apt8 reset request */ + unsigned int reserved_1 : 7; /**< apt9 reset request */ + } BIT; +} volatile PERI_CRG40_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int adc0_cken : 1; /**< adc0 controller sampling clock enable */ + unsigned int adc0sys_cken : 1; /**< adc0 controller config clock enable */ + unsigned int reserved_0 : 2; + unsigned int adc0_div : 5; /**< adc0 divider value */ + unsigned int reserved_1 : 3; + unsigned int adc0_cksel : 2; /**< adc0 clock select */ + unsigned int reserved_2 : 2; + unsigned int adc0_srst_req : 1; /**< adc0 controller sampling clock reset request */ + unsigned int adc0sys_srst_req : 1; /**< adc0 controller config clock reset request */ + unsigned int adc0_ana_srst_req : 1; /**< adc0 controller analog clock reset request */ + unsigned int reserved_3 : 13; + } BIT; +} volatile PERI_CRG41_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int adc1_cken : 1; /**< adc1 controller sampling clock enable */ + unsigned int adc1sys_cken : 1; /**< adc1 controller config clock enable */ + unsigned int reserved_0 : 2; + unsigned int adc1_div : 5; /**< adc1 divider value */ + unsigned int reserved_1 : 3; + unsigned int adc1_cksel : 2; /**< adc1 clock select */ + unsigned int reserved_2 : 2; + unsigned int adc1_srst_req : 1; /**< adc1 controller sampling clock reset request */ + unsigned int adc1sys_srst_req : 1; /**< adc1 controller config clock reset request */ + unsigned int adc1_ana_srst_req : 1; /**< adc1 controller analog clock reset request */ + unsigned int reserved_3 : 13; + } BIT; +} volatile PERI_CRG42_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int adc2_cken : 1; /**< adc1 controller sampling clock enable */ + unsigned int adc2sys_cken : 1; /**< adc1 controller config clock enable */ + unsigned int reserved_0 : 2; + unsigned int adc2_div : 5; /**< adc1 divider value */ + unsigned int reserved_1 : 3; + unsigned int adc2_cksel : 2; /**< adc1 clock select */ + unsigned int reserved_2 : 2; + unsigned int adc2_srst_req : 1; /**< adc1 controller sampling clock reset request */ + unsigned int adc2sys_srst_req : 1; /**< adc1 controller config clock reset request */ + unsigned int adc2_ana_srst_req : 1; /**< adc1 controller analog clock reset request */ + unsigned int reserved_3 : 13; + } BIT; +} volatile PERI_CRG43_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int acmp0_cken : 1; /**< acmp0 clock enable */ + unsigned int acmp1_cken : 1; /**< acmp1 clock enable */ + unsigned int acmp2_cken : 1; /**< acmp2 clock enable */ + unsigned int reserved_0 : 13; + unsigned int acmp0_srst_req : 1; /**< acmp0 reset request */ + unsigned int acmp1_srst_req : 1; /**< acmp1 reset request */ + unsigned int acmp2_srst_req : 1; /**< acmp2 reset request */ + unsigned int reserved_1 : 13; + } BIT; +} volatile PERI_CRG44_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int dac0_cken : 1; /**< dac0 clock enable */ + unsigned int dac1_cken : 1; /**< dac1 clock enable */ + unsigned int dac2_cken : 1; /**< dac2 clock enable */ + unsigned int reserved_0 : 1; + unsigned int dac0_div : 4; /**< dac0 divider */ + unsigned int dac1_div : 4; /**< dac1 divider */ + unsigned int dac2_div : 4; /**< dac2 divider */ + unsigned int dac0_srst_req : 1; /**< dac0 reset request */ + unsigned int dac1_srst_req : 1; /**< dac1 reset request */ + unsigned int dac2_srst_req : 1; /**< dac2 reset request */ + unsigned int reserved_1 : 13; + } BIT; +} volatile PERI_CRG45_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int pga0_cken : 1; /**< pga0 clock enable */ + unsigned int pga1_cken : 1; /**< pga1 clock enable */ + unsigned int pga2_cken : 1; /**< pga2 clock enable */ + unsigned int reserved_1 : 13; + unsigned int pga0_srst_req : 1; /**< pga0 reset request */ + unsigned int pga1_srst_req : 1; /**< pga1 reset request */ + unsigned int pga2_srst_req : 1; /**< pga2 reset request */ + unsigned int reserved_0 : 13; + } BIT; +} volatile PERI_CRG46_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int test_clk_sel : 4; /**< test clock select */ + unsigned int test_clk_en : 1; /**< test clock enable */ + unsigned int reserved : 27; + } BIT; +} volatile PERI_CRG47_Reg; + +typedef union { + unsigned int value; + struct { + unsigned int pvd_rst_enable : 1; /**< pvd reset enable */ + unsigned int reserved_0 : 31 ; + } BIT; +} volatile PERI_CRG48_Reg; + +/** + * @brief CRG Register + */ +typedef struct { + PERI_CRG0_Reg PERI_CRG0; /**< CRG0 register. Offset address 0x00000000U. */ + PERI_CRG1_Reg PERI_CRG1; /**< CRG1 register. Offset address 0x00000004U. */ + PERI_CRG2_Reg PERI_CRG2; /**< CRG2 register. Offset address 0x00000008U. */ + PERI_CRG3_Reg PERI_CRG3; /**< CRG3 register. Offset address 0x0000000CU. */ + PERI_CRG4_Reg PERI_CRG4; /**< CRG4 register. Offset address 0x00000010U. */ + PERI_CRG5_Reg PERI_CRG5; /**< CRG5 register. Offset address 0x00000014U. */ + PERI_CRG6_Reg PERI_CRG6; /**< CRG6 register. Offset address 0x00000018U. */ + PERI_CRG7_Reg PERI_CRG7; /**< CRG7 register. Offset address 0x0000001CU. */ + PERI_CRG8_Reg PERI_CRG8; /**< CRG8 register. Offset address 0x00000020U. */ + unsigned int reserved_1[3]; + PERI_CRG20_Reg PERI_CRG20; /**< CRG20 register. Offset address 0x00000030U. */ + PERI_CRG21_Reg PERI_CRG21; /**< CRG21 register. Offset address 0x00000034U. */ + PERI_CRG22_Reg PERI_CRG22; /**< CRG22 register. Offset address 0x00000038U. */ + PERI_CRG23_Reg PERI_CRG23; /**< CRG23 register. Offset address 0x0000003CU. */ + PERI_CRG24_Reg PERI_CRG24; /**< CRG24 register. Offset address 0x00000040U. */ + PERI_CRG25_Reg PERI_CRG25; /**< CRG25 register. Offset address 0x00000044U. */ + PERI_CRG26_Reg PERI_CRG26; /**< CRG26 register. Offset address 0x00000048U. */ + PERI_CRG27_Reg PERI_CRG27; /**< CRG27 register. Offset address 0x0000004CU. */ + PERI_CRG28_Reg PERI_CRG28; /**< CRG28 register. Offset address 0x00000050U. */ + PERI_CRG29_Reg PERI_CRG29; /**< CRG29 register. Offset address 0x00000054U. */ + PERI_CRG30_Reg PERI_CRG30; /**< CRG30 register. Offset address 0x00000058U. */ + PERI_CRG31_Reg PERI_CRG31; /**< CRG31 register. Offset address 0x0000005CU. */ + PERI_CRG32_Reg PERI_CRG32; /**< CRG32 register. Offset address 0x00000060U. */ + PERI_CRG33_Reg PERI_CRG33; /**< CRG33 register. Offset address 0x00000064U. */ + PERI_CRG34_Reg PERI_CRG34; /**< CRG34 register. Offset address 0x00000068U. */ + PERI_CRG35_Reg PERI_CRG35; /**< CRG35 register. Offset address 0x0000006CU. */ + PERI_CRG36_Reg PERI_CRG36; /**< CRG36 register. Offset address 0x00000070U. */ + unsigned int reserved_3; + PERI_CRG38_Reg PERI_CRG38; /**< CRG38 register. Offset address 0x00000078U. */ + PERI_CRG39_Reg PERI_CRG39; /**< CRG39 register. Offset address 0x0000007CU. */ + PERI_CRG40_Reg PERI_CRG40; /**< CRG40 register. Offset address 0x00000080U. */ + PERI_CRG41_Reg PERI_CRG41; /**< CRG40 register. Offset address 0x00000084U. */ + PERI_CRG42_Reg PERI_CRG42; /**< CRG42 register. Offset address 0x00000088U. */ + PERI_CRG43_Reg PERI_CRG43; /**< CRG43 register. Offset address 0x0000008CU. */ + PERI_CRG44_Reg PERI_CRG44; /**< CRG44 register. Offset address 0x00000090U. */ + PERI_CRG45_Reg PERI_CRG45; /**< CRG45 register. Offset address 0x00000094U. */ + PERI_CRG46_Reg PERI_CRG46; /**< CRG46 register. Offset address 0x00000098U. */ + PERI_CRG47_Reg PERI_CRG47; /**< CRG47 register. Offset address 0x0000009CU. */ + PERI_CRG48_Reg PERI_CRG48; /**< CRG48 register. Offset address 0x000000A0U. */ +} volatile CRG_RegStruct; +/** + * @} + */ + +/* Parameter Check -----------------------------------------------------------*/ +/** + * @brief Verify XTAL Freq + * @param freq The freq of User-defined XTAL + * @retval true + * @retval false + */ +static inline bool IsCrgXtalFreq(unsigned int freq) +{ + return ((freq >= CRG_CLK_XTAL_MIN_FREQ) && + (freq <= CRG_CLK_XTAL_MAX_FREQ)); +} + +/** + * @brief Verify pll_ref_cksel configuration + * @param clkSelect pll_ref_cksel + * @retval true + * @retval false + */ +static inline bool IsCrgPllRefClkSelect(CRG_PllRefClkSelect clkSelect) +{ + return ((clkSelect == CRG_PLL_REF_CLK_SELECT_HOSC) || + (clkSelect == CRG_PLL_REF_CLK_SELECT_XTAL)); +} + +/** + * @brief Verify Crg pll_prediv configuration + * @param preDiv pll prediv value + * @retval true + * @retval false + */ +static inline bool IsCrgPllPreDiv(CRG_PllPreDiv preDiv) +{ + return ((preDiv >= CRG_PLL_NO_PREDV) && + (preDiv <= CRG_PLL_PREDIV_4)); +} + +/** + * @brief Verify Crg pll_postdiv configuration + * @param postDiv pll_postdiv value + * @retval true + * @retval false + */ +static inline bool IsCrgPllPostDiv(CRG_PllPostDiv postDiv) +{ + return ((postDiv >= CRG_PLL_POSTDIV_1) && + (postDiv <= CRG_PLL_POSTDIV_32_MAX)); +} + +/** + * @brief Verify Crg pll_fbdiv configuration + * @param fbDiv pll fbdiv value + * @retval true + * @retval false + */ +static inline bool IsCrgPllFbDiv(unsigned int fbDiv) +{ + return (fbDiv >= CRG_PLL_FBDIV_MIN) && (fbDiv <= CRG_PLL_FBDIV_MAX); +} + +/** + * @brief Verify Crg pll_test_clk select configuration + * @param select pll_test_clk value + * @retval true + * @retval false + */ +static inline bool IsCrgPllTestClkSelect(CRG_PllTestClkSelect select) +{ + return ((select == CRG_PLL_TEST_SELECT_PFD) || + (select == CRG_PLL_TEST_SELECT_PLL_DIV_128)); +} + +/** + * @brief Verify Crg pll_digpostdiv_in_sel configuration + * @param select pll_digpostdiv_in_sel value + * @retval true + * @retval false + */ +static inline bool IsCrgPllDigPostDivInSel(CRG_PllDigPostDivInSelect select) +{ + return ((select == CRG_PLL_DIG_POST_DIV_SELECT_FREF) || + (select == CRG_PLL_DIG_POST_DIV_SELECT_PLL)); +} + +/** + * @brief Verify Crg core_cksel configuration + * @param select core_cksel value + * @retval true + * @retval false + */ +static inline bool IsCrgCoreCkSel(CRG_CoreClkSelect select) +{ + return ((select == CRG_CORE_CLK_SELECT_HOSC) || + (select == CRG_CORE_CLK_SELECT_TCXO) || + (select == CRG_CORE_CLK_SELECT_PLL)); +} + +/** + * @brief Verify Crg Ls Ip clock select configuration + * @param select ls ip clock select value + * @retval true + * @retval false + */ +static inline bool IsCrgAPBLsCkSel(CRG_APBLsClkSelect select) +{ + return ((select == CRG_CLK_LS) || + (select == CRG_CLK_LS_DIV_2) || + (select == CRG_CLK_LS_DIV_4) || + (select == CRG_CLK_LS_DIV_8)); +} + +/** + * @brief Verify Crg Ip (exclude adc) clock enable configuration + * @param enable ip clock enable value + * @retval true + * @retval false + */ +static inline bool IsCrgIpClkEnable(unsigned int enable) +{ + return ((enable == IP_CLK_DISABLE) || + (enable == IP_CLK_ENABLE)); +} + +/** + * @brief Check the PLL PreDiv is valid or not + * @param clkPllRef PLL Refer clock + * @param preDiv PLL Previous Division + * @retval true + * @retval false + */ +static inline bool IsCrgValidPreDiv(unsigned int pllRefFreq, unsigned int preDiv) +{ + unsigned int freq = pllRefFreq; + if (preDiv != 0) { + freq /= preDiv; + } + return (freq >= CRG_CLK_PFD_MIN_FREQ) && (freq <= CRG_CLK_PFD_MAX_FREQ); +} + +/** + * @brief Check the PLL FbDiv is valid or not + * @param clkPfdFreq PLL PFD clock + * @param fdDiv PLL FD Division + * @retval true + * @retval false + */ +static inline bool IsCrgValidFdDiv(unsigned int clkPfdFreq, unsigned int fdDiv) +{ + unsigned int freq = clkPfdFreq * fdDiv; + return (freq >= CRG_CLK_VCO_MIN_FREQ) && (freq <= CRG_CLK_VCO_MAX_FREQ); +} + +/** + * @brief Check the PLL PostDiv is valid or not + * @param clkPllRef PLL Vco clock + * @param postDiv PLL Post Division + * @retval true + * @retval false + */ +static inline bool IsCrgValidPostDiv(unsigned int clkVcoFreq, unsigned int postDiv) +{ + unsigned int freq = clkVcoFreq; + if (postDiv != 0) { + freq /= postDiv; + } + return (freq >= CRG_CLK_TARGET_MIN_FREQ) && (freq <= CRG_CLK_TARGET_MAX_FREQ); +} + +/** + * @brief Set Pll Ref clock select + * @param clk Clock register base address + * @param clkSel clock source select + * @retval None + */ +static inline void DCL_CRG_SetPllRefClkSel(CRG_RegStruct *clk, CRG_PllRefClkSelect clkSel) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + CRG_PARAM_CHECK_NO_RET(IsCrgPllRefClkSelect(clkSel)); + clk->PERI_CRG0.pll_ref_cksel = (unsigned int)clkSel; +} + +/** + * @brief Get Pll Ref clock selection + * @param clk Clock register base address + * @retval pll_ref_cksel Ref clock selection + */ +static inline CRG_PllRefClkSelect DCL_CRG_GetPllRefClkSel(const CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + return (CRG_PllRefClkSelect)clk->PERI_CRG0.pll_ref_cksel; +} + +/** + * @brief Set previous division ratio + * @param clk Clock register base address + * @param preDiv previous division ratio + * @retval None + */ +static inline void DCL_CRG_SetPllPreDiv(CRG_RegStruct *clk, CRG_PllPreDiv preDiv) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + CRG_PARAM_CHECK_NO_RET(IsCrgPllPreDiv(preDiv)); + clk->PERI_CRG1.pll_prediv = (unsigned int)preDiv; +} + +/** + * @brief Get previous division ratio + * @param clk Clock register base address + * @retval prediv previous division ratio + */ +static inline CRG_PllPreDiv DCL_CRG_GetPllPreDiv(const CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + return (CRG_PllPreDiv)clk->PERI_CRG1.pll_prediv; +} + +/** + * @brief Set PLL frequency multiplication factor + * @param clk Clock register base address + * @param fbDiv Multiplication factor + * @retval None + */ +static inline void DCL_CRG_SetPllFbDiv(CRG_RegStruct *clk, unsigned int fbDiv) +{ + unsigned int div = fbDiv; + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + CRG_PARAM_CHECK_NO_RET(IsCrgPllFbDiv(fbDiv)); + clk->PERI_CRG2.pll_fbdiv = div; +} + +/** + * @brief Get PLL frequency multiplication factor + * @param clk Clock register base address + * @retval pll_fbdiv Multiplication factor + */ +static inline unsigned int DCL_CRG_GetPllFbDiv(const CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + return clk->PERI_CRG2.pll_fbdiv; +} + +/** + * @brief Set PLL post division ratio + * @param clk Clock register base address + * @param postDiv Post division ratio + * @retval None + */ +static inline void DCL_CRG_SetPllPostDiv(CRG_RegStruct *clk, CRG_PllPostDiv postDiv) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + CRG_PARAM_CHECK_NO_RET(IsCrgPllPostDiv(postDiv)); + clk->PERI_CRG3.pll_postdiv = (unsigned int)postDiv; +} + +/** + * @brief Get PLL post division ratio + * @param clk Clock register base address + * @retval pll_postdiv Post division ratio + */ +static inline CRG_PllPostDiv DCL_CRG_GetPllPostDiv(const CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + return (CRG_PllPostDiv)clk->PERI_CRG3.pll_postdiv; +} + +/** + * @brief Set PLL Power + * @param clk Clock register base address + * @param pd pll power down or not + * @retval None + */ +static inline void DCL_CRG_SetPllPd(CRG_RegStruct *clk, bool pd) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + clk->PERI_CRG4.pll_pd = (unsigned int)pd; +} + +/** + * @brief Get PLL power status + * @param clk Clock register base address + * @retval 0: power up, 1: power down + */ +static inline bool DCL_CRG_GetPllPd(const CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + return clk->PERI_CRG4.pll_pd; +} + +/** + * @brief Get pll diagnose test enable + * @param clk Clock register base address + * @retval bool lockdet enable + */ +static inline bool DCL_CRG_GetPllDigEbLockDet(const CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + return (bool)clk->PERI_CRG5.BIT.pll_dig_eb_lockdet; +} + +/** + * @brief Set core clock selection + * @param clk Clock register base address + * @param select Core clock selection + * @retval None + */ +static inline void DCL_CRG_SetCoreClkSel(CRG_RegStruct *clk, CRG_CoreClkSelect select) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + CRG_PARAM_CHECK_NO_RET(IsCrgCoreCkSel(select)); + clk->PERI_CRG7.BIT.core_cksel = select; +} + +/** + * @brief Get core clock selection + * @param clk Clock register base address + * @retval Core clock selection + */ +static inline unsigned int DCL_CRG_GetCoreClkSel(const CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + return clk->PERI_CRG7.BIT.core_cksel; +} + +/** + * @brief Set Pll test clock selection + * @param clk Clock register base address + * @param select PLL test clock selection + * @retval None + */ +static inline void DCL_CRG_SetPllTestClockSelect(CRG_RegStruct *clk, CRG_PllTestClkSelect select) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + CRG_PARAM_CHECK_NO_RET(IsCrgPllTestClkSelect(select)); + clk->PERI_CRG6.BIT.pll_test_clk = select; +} + +/** + * @brief Get Pll test clock selection + * @param clk Clock register base address + * @retval PLL test clock selection + */ +static inline unsigned int DCL_CRG_GetPllTestClockSelect(const CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + return clk->PERI_CRG6.BIT.pll_test_clk; +} + +/** + * @brief Set refer clock selection + * @param clk Clock register base address + * @param sel Refer clock selection + * @retval None + */ +static inline void DCL_CRG_SetRefClkSel(CRG_RegStruct *clk, bool switchEn) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + clk->PERI_CRG7.BIT.ck_switchen = switchEn; +} + +/** + * @brief Get refer clock selection + * @param clk Clock register base address + * @retval unsigned int + */ +static inline unsigned int DCL_CRG_GetRefClkSel(const CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + return clk->PERI_CRG7.BIT.ck_switchen; +} +/** + * @brief Enable PVD reset function + * @param clk Clock register base address + * @retval None + */ +static inline void DCL_CRG_PvdResetEnable(CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + clk->PERI_CRG48.BIT.pvd_rst_enable = BASE_CFG_ENABLE; +} + +/** + * @brief Disable PVD reset function + * @param clk Clock register base address + * @retval None + */ +static inline void DCL_CRG_PvdResetDisable(CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + clk->PERI_CRG48.BIT.pvd_rst_enable = BASE_CFG_DISABLE; +} + +/** + * @brief Coresight auto clock gate select. + * @param clk Clock register base address + * @param clkEn enable select. + * @retval None + */ +static inline void DCL_CRG_CoresightClkGateSel(CRG_RegStruct *clk, bool clkEn) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + clk->PERI_CRG38.BIT.cs_cken = clkEn; +} + +/** + * @brief Enable test clock function + * @param clk Clock register base address + * @retval None + */ +static inline void DCL_CRG_TestClkEnable(CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + clk->PERI_CRG47.BIT.test_clk_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable test clock function + * @param clk Clock register base address + * @retval None + */ +static inline void DCL_CRG_TestClkDisable(CRG_RegStruct *clk) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + clk->PERI_CRG47.BIT.test_clk_en = BASE_CFG_DISABLE; +} + +/** + * @brief CRG test clock select. + * @param clk Clock register base address + * @param clkSel Clock select. + * @retval None + */ +static inline void DCL_CRG_TestClkSel(CRG_RegStruct *clk, CRG_TestClkSel clkSel) +{ + CRG_ASSERT_PARAM(IsCRGInstance(clk)); + CRG_PARAM_CHECK_NO_RET(clkSel >= CRG_TEST_CLK_PLL); + CRG_PARAM_CHECK_NO_RET(clkSel <= CRG_TEST_CLK_ADC2); + clk->PERI_CRG47.BIT.test_clk_sel = clkSel; +} +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_CRG_IP_H */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/crg/src/crg.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/crg/src/crg.c new file mode 100644 index 00000000..a2f12b9d --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/crg/src/crg.c @@ -0,0 +1,1260 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file crg.c + * @author MCU Driver Team + * @brief CRG module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the CRG. + * + Initialization and de-initialization functions + * + Config the register of CRG + * + Config the register of IP,such as Uart,Timer and so on + */ + +/* Includes ------------------------------------------------------------------*/ +#include "crg.h" + +/* Macro definitions ---------------------------------------------------------*/ + +/* Private Function -----------------------------------------------------------*/ +static unsigned int CRG_GetPllRefIni(CRG_PllRefClkSelect pllRefClkSelect); +static unsigned int CRG_GetPreDivValue(CRG_PllPreDiv pllPredDiv); +static unsigned int CRG_GetPllFbDivValue(unsigned int pllFbDiv); +static unsigned int CRG_GetPllPostDivValue(unsigned int pllPostDiv); +static inline unsigned int CRG_GetVcoFreq(void); +static BASE_StatusType CRG_IsValidPllConfig(const CRG_Handle *handle); +static void CRG_GetPllOptConfig(unsigned int targetFreq, unsigned int pllRefFreq, CRG_PllDivCfg *div); + +static void CRG_IpWithClkSelEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable); +static void CRG_IpWithClkSelClkSelSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int clkSelect); +static void CRG_IpWithClkSelResetSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int reset); +static unsigned int CRG_IpWithClkSelEnableGet(const CHIP_CrgIpMatchInfo *matchInfo); +static unsigned int CRG_IpWithClkSelClkSelGet(const CHIP_CrgIpMatchInfo *matchInfo); +static unsigned int CRG_IpWithClkSelResetGet(const CHIP_CrgIpMatchInfo *matchInfo); + +static void CRG_IpWoClkSelEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable); +static void CRG_IpWoClkSelResetSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int reset); +static unsigned int CRG_IpWoClkSelEnableGet(const CHIP_CrgIpMatchInfo *matchInfo); +static unsigned int CRG_IpWoClkSelResetGet(const CHIP_CrgIpMatchInfo *matchInfo); + +static void CRG_AdcEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable); +static void CRG_AdcResetSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int reset); +static void CRG_AdcDivSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int div); +static void CRG_AdcClkSelectSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int clkSelect); +static unsigned int CRG_AdcEnableGet(const CHIP_CrgIpMatchInfo *matchInfo); +static unsigned int CRG_AdcResetGet(const CHIP_CrgIpMatchInfo *matchInfo); +static unsigned int CRG_AdcClkSelectGet(const CHIP_CrgIpMatchInfo *matchInfo); +static unsigned int CRG_AdcDivGet(const CHIP_CrgIpMatchInfo *matchInfo); + +static void CRG_DacEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable); +static unsigned int CRG_DacEnableGet(const CHIP_CrgIpMatchInfo *matchInfo); +static void CRG_DacDivSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int div); +static unsigned int CRG_DacDivGet(const CHIP_CrgIpMatchInfo *matchInfo); +static void CRG_DacResetSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int reset); +static unsigned int CRG_DacResetGet(const CHIP_CrgIpMatchInfo *matchInfo); + +static void CRG_EfcEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable); +static unsigned int CRG_EfcEnableGet(const CHIP_CrgIpMatchInfo *matchInfo); + +static bool CheckClkLsNoDivBaseAddr(const void *ipBaseAddr); + +#ifndef FPGA +static unsigned int CRG_GetLsIpFreq(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int baseClkRate); +static unsigned int CRG_GetAdcIpFreq(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int baseClkRate); +static unsigned int CRG_GetDacIpFreq(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int baseClkRate); +#endif + +typedef CHIP_CrgIpMatchInfo *(*FindFunc)(const void *baseAddress); +typedef void (*SetFunc)(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int value); +typedef unsigned int (*GetFunc)(const CHIP_CrgIpMatchInfo *matchInfo); + +typedef struct { + CHIP_CrgIpType type; + SetFunc resetSet; + SetFunc enableSet; + SetFunc clkSelSet; + SetFunc clkDivSet; + GetFunc resetGet; + GetFunc enableGet; + GetFunc clkSelGet; + GetFunc clkDivGet; +} CRG_IpProc; + +static const CRG_IpProc g_ipClkProc[CRG_IP_MAX_TYPE] = { + { + CRG_IP_WITH_LS, + CRG_IpWithClkSelResetSet, + CRG_IpWithClkSelEnableSet, + CRG_IpWithClkSelClkSelSet, + NULL, + CRG_IpWithClkSelResetGet, + CRG_IpWithClkSelEnableGet, + CRG_IpWithClkSelClkSelGet, + NULL, + }, + { + CRG_IP_WITH_HS, + CRG_IpWoClkSelResetSet, + CRG_IpWoClkSelEnableSet, + NULL, + NULL, + CRG_IpWoClkSelResetGet, + CRG_IpWoClkSelEnableGet, + NULL, + NULL, + }, + { + CRG_IP_CAN, + CRG_IpWoClkSelResetSet, + CRG_IpWoClkSelEnableSet, + NULL, + NULL, + CRG_IpWoClkSelResetGet, + CRG_IpWoClkSelEnableGet, + NULL, + NULL, + }, + { + CRG_IP_ADC, + CRG_AdcResetSet, + CRG_AdcEnableSet, + CRG_AdcClkSelectSet, + CRG_AdcDivSet, + CRG_AdcResetGet, + CRG_AdcEnableGet, + CRG_AdcClkSelectGet, + CRG_AdcDivGet, + }, + { + CRG_IP_DAC, + CRG_DacResetSet, + CRG_DacEnableSet, + NULL, + CRG_DacDivSet, + CRG_DacResetGet, + CRG_DacEnableGet, + NULL, + CRG_DacDivGet, + }, + { + CRG_IP_EFC, + NULL, + CRG_EfcEnableSet, + NULL, + NULL, + NULL, + CRG_EfcEnableGet, + NULL, + NULL, + }, + { + CRG_IP_IWDG, + CRG_IpWoClkSelResetSet, + CRG_IpWoClkSelEnableSet, + NULL, + NULL, + CRG_IpWoClkSelResetGet, + CRG_IpWoClkSelEnableGet, + NULL, + NULL, + }, +}; +static CRG_RegStruct *g_crgBaseAddr; + +/* Public Function -----------------------------------------------------------*/ +/** + * @brief Clock Init + * @param handle CRG Handle + * @retval BASE_STATUS_ERROR Parameter Check fail + * @retval BASE_STATUS_OK Success + */ +BASE_StatusType HAL_CRG_Init(const CRG_Handle *handle) +{ + CRG_ASSERT_PARAM(handle != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(handle->baseAddress)); + CRG_PARAM_CHECK_WITH_RET(IsCrgXtalFreq(XTRAIL_FREQ), BASE_STATUS_ERROR); /* Check the validity of XTRAIL_FREQ. */ + CRG_PARAM_CHECK_WITH_RET(IsCrgPllRefClkSelect(handle->pllRefClkSelect), BASE_STATUS_ERROR); + CRG_PARAM_CHECK_WITH_RET(IsCrgPllPreDiv(handle->pllPreDiv), BASE_STATUS_ERROR); + CRG_PARAM_CHECK_WITH_RET(IsCrgPllFbDiv(handle->pllFbDiv), BASE_STATUS_ERROR); + CRG_PARAM_CHECK_WITH_RET(IsCrgPllPostDiv(handle->pllPostDiv), BASE_STATUS_ERROR); + CRG_PARAM_CHECK_WITH_RET(IsCrgCoreCkSel(handle->coreClkSelect), BASE_STATUS_ERROR); + + CRG_RegStruct *reg = handle->baseAddress; + g_crgBaseAddr = (void *)reg; + /* Check the validity of PLL parameters. */ + if (CRG_IsValidPllConfig(handle) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + + DCL_SYSCTRL_CrgWriteProtectionDisable(); /* Disable register write protection. */ + + reg->PERI_CRG0.pll_ref_cksel = handle->pllRefClkSelect; + reg->PERI_CRG1.pll_prediv = handle->pllPreDiv; + reg->PERI_CRG2.pll_fbdiv = handle->pllFbDiv; + reg->PERI_CRG3.pll_postdiv = handle->pllPostDiv; + reg->PERI_CRG4.pll_pd = BASE_CFG_UNSET; + reg->PERI_CRG5.BIT.pll_dig_eb_lockdet = BASE_CFG_UNSET; /* PLL lock detection enable, 0 : enable, 1: disable */ + + while (reg->PERI_CRG8.pll_lock != BASE_CFG_SET) { + ; /* Wait for PLL to lock */ + } + reg->PERI_CRG7.BIT.ck_switchen = BASE_CFG_SET; + + DCL_SYSCTRL_CrgWriteProtectionEnable(); /* Enable register write protection. */ + return BASE_STATUS_OK; +} + +/** + * @brief Set Crg Core clock by target frequecy + * @param handle CRG handle + * @param targetFreq Target Frequency + * @retval BASE_STATUS_ERROR Parameter Check fail + * @retval BASE_STATUS_OK Success + */ +BASE_StatusType HAL_CRG_InitWithTargetFrequence(const CRG_Handle *handle, unsigned int targetFreq) +{ + CRG_ASSERT_PARAM(handle != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(handle->baseAddress)); + CRG_PARAM_CHECK_WITH_RET(IsCrgPllRefClkSelect(handle->pllRefClkSelect), BASE_STATUS_ERROR); + CRG_PARAM_CHECK_WITH_RET((targetFreq <= CRG_CLK_VCO_MAX_FREQ), BASE_STATUS_ERROR); + + CRG_Handle crgHandle; + CRG_PllDivCfg divCfg; + unsigned int pllRefFreq; + + pllRefFreq = (handle->pllRefClkSelect == CRG_PLL_REF_CLK_SELECT_HOSC) ? HOSC_FREQ : XTRAIL_FREQ; + CRG_GetPllOptConfig(targetFreq, pllRefFreq, &divCfg); + crgHandle = *handle; + crgHandle.pllPreDiv = divCfg.PreDiv; + crgHandle.pllFbDiv = divCfg.fbDiv; + crgHandle.pllPostDiv = divCfg.postDiv; + return HAL_CRG_Init(&crgHandle); +} + +/** + * @brief Clock Deinit + * @param handle CRG Handle + * @retval BASE_STATUS_OK + */ +BASE_StatusType HAL_CRG_DeInit(const CRG_Handle *handle) +{ + CRG_ASSERT_PARAM(handle != NULL); + CRG_RegStruct *reg = handle->baseAddress; + DCL_SYSCTRL_CrgWriteProtectionDisable(); + + reg->PERI_CRG0.pll_ref_cksel = 0x0; /* 0x0: default value */ + reg->PERI_CRG1.pll_prediv = 0x3; /* 0x3: default value */ + reg->PERI_CRG2.pll_fbdiv = 0x10; /* 0x10: default value */ + reg->PERI_CRG3.pll_postdiv = 0x0; /* 0x0: default value */ + reg->PERI_CRG4.pll_pd = 0x1; /* 0x1: default value */ + reg->PERI_CRG5.BIT.pll_dig_eb_lockdet = 0x1; /* 0x1: default value */ + reg->PERI_CRG7.BIT.ck_switchen = 0x1; /* 0x1: default value */ + + DCL_SYSCTRL_CrgWriteProtectionEnable(); + return BASE_STATUS_OK; +} + +/** + * @brief Get Clock Config + * @param handle CRG Handle + * @retval BASE_STATUS_OK Success + */ +BASE_StatusType HAL_CRG_GetConfig(CRG_Handle *handle) +{ + CRG_ASSERT_PARAM(handle != 0); + CRG_ASSERT_PARAM(IsCRGInstance(handle->baseAddress)); + + CRG_RegStruct *reg = handle->baseAddress; + handle->pllRefClkSelect = reg->PERI_CRG0.pll_ref_cksel; + handle->pllPreDiv = reg->PERI_CRG1.pll_prediv; + handle->pllFbDiv = reg->PERI_CRG2.pll_fbdiv; + handle->pllPostDiv = reg->PERI_CRG3.pll_postdiv; + handle->pllPd = reg->PERI_CRG4.pll_pd; + handle->handleEx.ckSwitchEn = reg->PERI_CRG7.BIT.ck_switchen; + handle->coreClkSelect = reg->PERI_CRG7.BIT.core_cksel; + + return BASE_STATUS_OK; +} + +/** + * @brief Set CRG Core Clock Select + * @param handle CRG Handle + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Parameter check fail + */ +BASE_StatusType HAL_CRG_SetCoreClockSelect(CRG_Handle *handle) +{ + CRG_ASSERT_PARAM(handle != 0); + CRG_ASSERT_PARAM(IsCRGInstance(handle->baseAddress)); + CRG_PARAM_CHECK_WITH_RET(IsCrgCoreCkSel(handle->coreClkSelect), BASE_STATUS_ERROR); + + CRG_RegStruct *reg = handle->baseAddress; + + DCL_SYSCTRL_CrgWriteProtectionDisable(); + DCL_CRG_SetCoreClkSel(reg, handle->coreClkSelect); + DCL_SYSCTRL_CrgWriteProtectionEnable(); + + return BASE_STATUS_OK; +} + +/** + * @brief Get PLL Clock Frequence + * @param None + * @retval unsigned int PLL clock frequency + */ +static inline unsigned int CRG_GetVcoFreq(void) +{ + unsigned int freq; + CRG_RegStruct *crg = g_crgBaseAddr; + + CRG_ASSERT_PARAM(IsCRGInstance(crg)); + freq = CRG_GetPllRefIni(crg->PERI_CRG0.pll_ref_cksel); + freq /= CRG_GetPreDivValue(crg->PERI_CRG1.pll_prediv); + freq *= CRG_GetPllFbDivValue(crg->PERI_CRG2.pll_fbdiv); + return freq; +} + +/** + * @brief Get PLL Clock Frequence + * @param None + * @retval unsigned int PLL clock frequency + */ +unsigned int HAL_CRG_GetPllFreq(void) +{ + unsigned int freq; + CRG_RegStruct *crg = g_crgBaseAddr; + + CRG_ASSERT_PARAM(IsCRGInstance(crg)); + freq = CRG_GetVcoFreq(); + freq /= CRG_GetPllPostDivValue((CRG_PllPostDiv)crg->PERI_CRG3.pll_postdiv); + return freq; +} + +/** + * @brief Get Core Clock Frequence + * @param None + * @retval unsigned int Core clock frequency + */ +unsigned int HAL_CRG_GetCoreClkFreq(void) +{ + unsigned int freq; + unsigned int coreClkSelect; + CRG_RegStruct *crg = g_crgBaseAddr; + + CRG_ASSERT_PARAM(IsCRGInstance(crg)); + coreClkSelect = crg->PERI_CRG7.BIT.core_cksel; + switch (coreClkSelect) { + case CRG_CORE_CLK_SELECT_HOSC: + freq = HOSC_FREQ; + break; + + case CRG_CORE_CLK_SELECT_TCXO: + freq = XTRAIL_FREQ; + break; + + case CRG_CORE_CLK_SELECT_PLL: + freq = HAL_CRG_GetPllFreq(); + break; + + default: + freq = LOSC_FREQ; + break; + } + return freq; +} + +/** + * @brief Get Clock Frequence + * @param handle CRG Handle + * @retval Frequece of IP + */ +unsigned int HAL_CRG_GetIpFreq(const void *baseAddress) +{ + CRG_ASSERT_PARAM(baseAddress != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); +#ifdef FPGA + return CHIP_GetIpFreqHz(baseAddress); +#else + unsigned int hclk = HAL_CRG_GetCoreClkFreq(); + unsigned int freq = LOSC_FREQ; + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + if (p == NULL) { + return freq; + } + switch (p->type) { + case CRG_IP_WITH_LS: + freq = CRG_GetLsIpFreq(p, hclk / 0x2); /* pclk is 1/2 of hclk */ + break; + + case CRG_IP_WITH_HS: + case CRG_IP_EFC: + freq = hclk; + break; + + case CRG_IP_CAN: + freq = CRG_GetPllRefIni(g_crgBaseAddr->PERI_CRG0.pll_ref_cksel); + break; + + case CRG_IP_DAC: + freq = CRG_GetPllRefIni(g_crgBaseAddr->PERI_CRG0.pll_ref_cksel); + freq = CRG_GetDacIpFreq(p, freq); + break; + + case CRG_IP_ADC: + freq = CRG_GetAdcIpFreq(p, CRG_GetVcoFreq()); + break; + + case CRG_IP_IWDG: + default: + break; + } + if (freq == 0) { + freq = LOSC_FREQ; + } + return freq; +#endif +} + +/** + * @brief Enable clock of ip + * @param baseAddress Ip base address + * @param enable enable mask + * @retval BASE_STATUS_ERROR Can't find the Match or operation is not support + * @retval BASE_STATUS_OK Operation Success + */ +BASE_StatusType HAL_CRG_IpEnableSet(const void *baseAddress, unsigned int enable) +{ + CRG_ASSERT_PARAM(baseAddress != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + if ((p == NULL) || (p->type >= CRG_IP_MAX_TYPE)) { + return BASE_STATUS_ERROR; + } + if (g_ipClkProc[p->type].enableSet == NULL) { + return BASE_STATUS_ERROR; + } + g_ipClkProc[p->type].enableSet(p, enable); + return BASE_STATUS_OK; +} + +/** + * @brief Get clock enable status of ip + * @param baseAddress Ip base address + * @param enable parameter out for ip enable status + * @retval BASE_STATUS_ERROR Can't find the Match or operation is not support + * @retval BASE_STATUS_OK Operation Success + */ +BASE_StatusType HAL_CRG_IpEnableGet(const void *baseAddress, unsigned int *enable) +{ + CRG_ASSERT_PARAM(baseAddress != NULL); + CRG_ASSERT_PARAM(enable != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + if ((p == NULL) || (p->type >= CRG_IP_MAX_TYPE)) { + return BASE_STATUS_ERROR; + } + if (g_ipClkProc[p->type].enableGet == NULL) { + return BASE_STATUS_ERROR; + } + *enable = g_ipClkProc[p->type].enableGet(p); + return BASE_STATUS_OK; +} + +/** + * @brief Set clock select ip + * @param baseAddress Ip base address + * @param select clock select, @see CRG_APBLsClkSelect for ip in apb_ls_subsys or CRG_AdcClkSelect for adc + * @retval BASE_STATUS_OK success + * @retval BASE_STATUS_ERROR fail + */ +BASE_StatusType HAL_CRG_IpClkSelectSet(const void *baseAddress, unsigned int select) +{ + CRG_ASSERT_PARAM(baseAddress != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + if ((p == NULL) || (p->type >= CRG_IP_MAX_TYPE)) { + return BASE_STATUS_ERROR; + } + /* Check the base address of the LS clock without division. */ + if (CheckClkLsNoDivBaseAddr(baseAddress)) { + return BASE_STATUS_ERROR; + } + if (g_ipClkProc[p->type].clkSelSet == NULL) { + return BASE_STATUS_ERROR; + } + g_ipClkProc[p->type].clkSelSet(p, select); + return BASE_STATUS_OK; +} + +/** + * @brief Get clock select of ip + * @param baseAddress Ip base address + * @param clkSel Get clkSet value + * @retval BASE_STATUS_OK + * @retval BASE_STATUS_ERROR Match Fail or Not support + */ +BASE_StatusType HAL_CRG_IpClkSelectGet(const void *baseAddress, unsigned int *clkSel) +{ + CRG_ASSERT_PARAM(baseAddress != NULL); + CRG_ASSERT_PARAM(clkSel != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + if ((p == NULL) || (p->type >= CRG_IP_MAX_TYPE)) { + return BASE_STATUS_ERROR; + } + /* Check the base address of the LS clock without division. */ + if (CheckClkLsNoDivBaseAddr(baseAddress)) { + return BASE_STATUS_ERROR; + } + if (g_ipClkProc[p->type].clkSelGet == NULL) { + return BASE_STATUS_ERROR; + } + *clkSel = g_ipClkProc[p->type].clkSelGet(p); + return BASE_STATUS_OK; +} + +/** + * @brief Reset/Set clock of ip + * @param baseAddress Ip base address + * @param reset Set reset value + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Match Fail or Not support + */ +BASE_StatusType HAL_CRG_IpClkResetSet(const void *baseAddress, unsigned int reset) +{ + CRG_ASSERT_PARAM(baseAddress != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + if ((p == NULL) || (p->type >= CRG_IP_MAX_TYPE)) { + return BASE_STATUS_ERROR; + } + if (g_ipClkProc[p->type].resetSet == NULL) { + return BASE_STATUS_ERROR; + } + g_ipClkProc[p->type].resetSet(p, reset); + return BASE_STATUS_OK; +} + +/** + * @brief Get clock select of ip + * @param baseAddress Ip base address + * @param reset Get reset value + * @retval BASE_STATUS_OK Success + * @retval BASE_CFG_UNSET Match Fail or Not support + */ +BASE_StatusType HAL_CRG_IpClkResetGet(const void *baseAddress, unsigned int *reset) +{ + CRG_ASSERT_PARAM(baseAddress != NULL); + CRG_ASSERT_PARAM(reset != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + if ((p == NULL) || (p->type >= CRG_IP_MAX_TYPE)) { + return BASE_STATUS_ERROR; + } + if (g_ipClkProc[p->type].resetGet == NULL) { + return BASE_STATUS_ERROR; + } + *reset = g_ipClkProc[p->type].resetGet(p); + return BASE_STATUS_OK; +} + +/** + * @brief Reset/Set clock of ip + * @param baseAddress Ip base address + * @param div set div value + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Match Fail or Not support + */ +BASE_StatusType HAL_CRG_IpClkDivSet(const void *baseAddress, unsigned int div) +{ + CRG_ASSERT_PARAM(baseAddress != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + if ((p == NULL) || (p->type >= CRG_IP_MAX_TYPE)) { + return BASE_STATUS_ERROR; + } + if (g_ipClkProc[p->type].clkDivSet == NULL) { + return BASE_STATUS_ERROR; + } + g_ipClkProc[p->type].clkDivSet(p, div); + return BASE_STATUS_OK; +} + +/** + * @brief Get clock select of ip + * @param baseAddress Ip base address + * @param div get div value + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Match Fail or Not support + */ +BASE_StatusType HAL_CRG_IpClkDivGet(const void *baseAddress, unsigned int *div) +{ + CRG_ASSERT_PARAM(baseAddress != NULL); + CRG_ASSERT_PARAM(div != NULL); + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + + CHIP_CrgIpMatchInfo *p = GetCrgIpMatchInfo(baseAddress); + if ((p == NULL) || (p->type >= CRG_IP_MAX_TYPE)) { + return BASE_STATUS_ERROR; + } + if (g_ipClkProc[p->type].clkDivGet == NULL) { + return BASE_STATUS_ERROR; + } + *div = g_ipClkProc[p->type].clkDivGet(p); + return BASE_STATUS_OK; +} + +/** + * @brief PVD reset function enable switch + * @param pvd reset enable select + * @retval None + */ +void HAL_CRG_PvdResetEnable(bool enable) +{ + CRG_ASSERT_PARAM(IsCRGInstance(g_crgBaseAddr)); + g_crgBaseAddr->PERI_CRG48.BIT.pvd_rst_enable = enable; +} + +/** + * @brief Based on the target frequency, obtain the optimal frequency division coefficient of the pll + * @param targetFreq Target frequency + * @param pllRefFreq Pll refer clock frequency + * @param divCfg Output Pll division config + * @retval None + */ +static void CRG_GetPllOptConfig(unsigned int targetFreq, unsigned int pllRefFreq, CRG_PllDivCfg *divCfg) +{ + unsigned int preDiv[] = {CRG_PLL_PREDIV_1, CRG_PLL_PREDIV_2, CRG_PLL_PREDIV_4}; + unsigned int freq; + unsigned int delta; + unsigned int minDelta = 0xFFFFFFFF; + + divCfg->PreDiv = CRG_PLL_NO_PREDV; + divCfg->fbDiv = CRG_PLL_FBDIV_MIN; + divCfg->postDiv = CRG_PLL_POSTDIV_1; + + for (unsigned int i = 0; i < sizeof(preDiv) / sizeof(preDiv[0]); ++i) { + unsigned int preDivOut = CRG_GetPreDivValue(preDiv[i]); + if (!IsCrgValidPreDiv(pllRefFreq, preDivOut)) { + continue; + } + unsigned int clkPfdFreq = pllRefFreq / preDivOut; + for (unsigned int j = CRG_PLL_FBDIV_MIN; j <= CRG_PLL_FBDIV_MAX; ++j) { + if (!IsCrgValidFdDiv(clkPfdFreq, j)) { + continue; + } + unsigned int clkVcoFreq = clkPfdFreq * j; + for (unsigned int k = CRG_PLL_POSTDIV_1; k <= CRG_PLL_POSTDIV_32; k++) { + unsigned int postDiv = 1 << k; + if (!IsCrgValidPostDiv(clkVcoFreq, postDiv)) { + continue; + } + freq = clkVcoFreq / postDiv; + delta = (targetFreq >= freq) ? targetFreq - freq : freq - targetFreq; + if (delta < minDelta) { + minDelta = delta; + divCfg->PreDiv = preDiv[i]; + divCfg->fbDiv = j; + divCfg->postDiv = k; + } + } + } + } +} + +/** + * @brief Check clk ls without div base address. + * @param ipBaseAddr the up base address + * @retval true or false + */ +static bool CheckClkLsNoDivBaseAddr(const void *ipBaseAddr) +{ + return (ipBaseAddr == GPIO0_BASE || ipBaseAddr == GPIO1_BASE || /* GPIO Baseaddress. */ + ipBaseAddr == GPIO2_BASE || ipBaseAddr == GPIO3_BASE || + ipBaseAddr == GPIO4_BASE || ipBaseAddr == GPIO5_BASE || + ipBaseAddr == GPIO6_BASE || ipBaseAddr == GPIO7_BASE || + ipBaseAddr == I2C_BASE); /* I2C Baseaddress. */ +} + +#ifndef FPGA +/** + * @brief Get Ls Ip Clock Frequence + * @param matchInfo match info + * @param baseClkRate clock rate + * @retval Ip Frequence + */ +static unsigned int CRG_GetLsIpFreq(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int baseClkRate) +{ + unsigned int clkSel; + const CRG_IpProc *proc = &g_ipClkProc[matchInfo->type]; + + /* Check the base address of the LS clock without division. */ + if (CheckClkLsNoDivBaseAddr(matchInfo->ipBaseAddr)) { + return baseClkRate; + } + + if (proc->clkSelGet == NULL) { + return 0; + } + clkSel = proc->clkSelGet(matchInfo); + return (baseClkRate >> clkSel); +} + +/** + * @brief Get ADC Clock Frequence + * @param matchInfo match info + * @param baseClkRate clock rate + * @retval Ip Frequence + */ +static unsigned int CRG_GetAdcIpFreq(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int baseClkRate) +{ + unsigned int clkSel; + unsigned int clkDiv; + const CRG_IpProc *proc = &g_ipClkProc[matchInfo->type]; + if (proc->clkSelGet == NULL) { + return 0; + } + clkSel = proc->clkSelGet(matchInfo); + if (clkSel == CRG_ADC_CLK_SELECT_HOSC) { + return HOSC_FREQ; + } + if (clkSel == CRG_ADC_CLK_SELECT_TCXO) { + return XTRAIL_FREQ; + } + if (proc->clkDivGet == NULL) { + return 0; + } + clkDiv = proc->clkDivGet(matchInfo); + return (baseClkRate * ADC_DIV_FACTOR) / (clkDiv + ADC_DIV_FACTOR); +} + +/** + * @brief Get DAC Clock Frequence + * @param matchInfo match info + * @param baseClkRate clock rate + * @retval Ip Frequence + */ +static unsigned int CRG_GetDacIpFreq(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int baseClkRate) +{ + unsigned int clkDiv; + const CRG_IpProc *proc = &g_ipClkProc[matchInfo->type]; + + if (proc->clkDivGet == NULL) { + return 0; + } + clkDiv = proc->clkDivGet(matchInfo); /* get clock division value */ + return baseClkRate / (clkDiv + 1); /* return frequency value */ +} +#endif + +/** + * @brief Check is Valid Pll Config + * @param CRG_Handle CRG handle + * @retval BASE_STATUS_OK Check Success + * @retval BASE_STATUS_ERROR Check Fail + */ +static BASE_StatusType CRG_IsValidPllConfig(const CRG_Handle *handle) +{ + unsigned int preDiv; + unsigned int freq; + + freq = CRG_GetPllRefIni(handle->pllRefClkSelect); + preDiv = CRG_GetPreDivValue(handle->pllPreDiv); + if (!IsCrgValidPreDiv(freq, preDiv)) { + return BASE_STATUS_ERROR; + } + freq /= preDiv; + if (!IsCrgValidFdDiv(freq, handle->pllFbDiv)) { + return BASE_STATUS_ERROR; + } + freq *= handle->pllFbDiv; + return IsCrgValidPostDiv(freq, handle->pllPostDiv) ? BASE_STATUS_OK : BASE_STATUS_ERROR; +} + +/** + * @brief Get clock frequence + * @param crg CRG_RegStruct + * @retval The frequence of clock + */ +static inline unsigned int CRG_GetPllRefIni(CRG_PllRefClkSelect pllRefClkSelect) +{ + return (pllRefClkSelect == (unsigned int)CRG_PLL_REF_CLK_SELECT_HOSC) ? HOSC_FREQ : XTRAIL_FREQ; +} + +/** + * @brief Get previous division Value before PLL + * @param crg CRG_RegStruct + * @retval Previous Div value + */ +static inline unsigned int CRG_GetPreDivValue(CRG_PllPreDiv pllPredDiv) +{ + if (pllPredDiv <= CRG_PLL_PREDIV_1) { + return PLL_PREDIV_OUT_1; + } else if (pllPredDiv == CRG_PLL_PREDIV_2) { + return PLL_PREDIV_OUT_2; + } else { + return PLL_PREDIV_OUT_4; + } +} + +/** + * @brief Get PLL loop divider ratio + * @param crg CRG_RegStruct + * @retval PLL loop divider ratio + */ +static inline unsigned int CRG_GetPllFbDivValue(unsigned int pllFbDiv) +{ + unsigned int div = pllFbDiv; + + if (div < CRG_PLL_FBDIV_MIN) { + div = CRG_PLL_FBDIV_MIN; + } + if (div > CRG_PLL_FBDIV_MAX) { + div = CRG_PLL_FBDIV_MAX; + } + return div; +} + +/** + * @brief Get post division Value after PLL + * @param crg CRG_RegStruct + * @retval Previous Div value + */ +static inline unsigned int CRG_GetPllPostDivValue(unsigned int pllPostDiv) +{ + unsigned int div = pllPostDiv; + if (div > CRG_PLL_POSTDIV_32) { + div = CRG_PLL_POSTDIV_32; + } + return (1 << div); +} + +/** + * @brief Enable Set for IP in APB_LS_SUBSYS + * @param matchInfo IP with Clock select match info + * @param enable BASE_CFG_SET or BASE_CFG_UNSET + * @retval None + */ +static void CRG_IpWithClkSelEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_IpWithClkSelectCfg *p = (CRG_IpWithClkSelectCfg *)(void *)(base + matchInfo->regOffset); + if ((enable & IP_CLK_ENABLE) == IP_CLK_ENABLE) { + p->BIT.cken = BASE_CFG_SET; + p->BIT.srst_req = BASE_CFG_UNSET; /* Enable with soft reset disable */ + } else { + p->BIT.cken = BASE_CFG_UNSET; + } +} + +/** + * @brief Get Enable status for IP in APB_LS_SUBSYS + * @param matchInfo IP with Clock select match info + * @param unsigned int 0: disable, 1: enable + * @retval Clock enable status + */ +static unsigned int CRG_IpWithClkSelEnableGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_IpWithClkSelectCfg *p = (CRG_IpWithClkSelectCfg *)(void *)(base + matchInfo->regOffset); + return p->BIT.cken; +} + +/** + * @brief Reset or undo Reset for IP in APB_LS_SUBSYS + * @param matchInfo IP with Clock select match info + * @param reset BASE_CFG_SET or BASE_CFG_UNSET + * @retval None + */ +static void CRG_IpWithClkSelResetSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int reset) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_IpWithClkSelectCfg *p = (CRG_IpWithClkSelectCfg *)(void *)(base + matchInfo->regOffset); + p->BIT.srst_req = (reset & BASE_CFG_SET) ? BASE_CFG_SET : BASE_CFG_UNSET; +} + +/** + * @brief Get Reset status for IP in APB_LS_SUBSYS + * @param matchInfo IP with Clock select match info + * @param unsigned int 0: disable, 1: enable + * @retval Clock reset status + */ +static unsigned int CRG_IpWithClkSelResetGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_IpWithClkSelectCfg *p = (CRG_IpWithClkSelectCfg *)(void *)(base + matchInfo->regOffset); + return p->BIT.srst_req; +} + +/** + * @brief Set Clock Select for IP in APB_LS_SUBSYS + * @param matchInfo IP with Clock select match info + * @param clkSelect @see CRG_APBLsClkSelect + * @param unsigned int BASE_CFG_SET or BASE_CFG_UNSET + * @retval None + */ +static void CRG_IpWithClkSelClkSelSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int clkSelect) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_IpWithClkSelectCfg *p = (CRG_IpWithClkSelectCfg *)(void *)(base + matchInfo->regOffset); + p->BIT.cksel = clkSelect; +} + +/** + * @brief Get Clock Select for IP in APB_LS_SUBSYS + * @param matchInfo IP with Clock select match info + * @retval Clock Select @see CRG_APBLsClkSelect + */ +static unsigned int CRG_IpWithClkSelClkSelGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_IpWithClkSelectCfg *p = (CRG_IpWithClkSelectCfg *)(void *)(base + matchInfo->regOffset); + return p->BIT.cksel; +} + +/** + * @brief Enable Set of IP in APB_HS_SUBSYS + * @param matchInfo IP without Clock select match info + * @param enable BASE_CFG_SET or BASE_CFG_UNSET + * @retval None + */ +static void CRG_IpWoClkSelEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_IpWoClkSelectCfg *p = (CRG_IpWoClkSelectCfg *)(void *)(base + matchInfo->regOffset); + CRG_IpWoClkSelectCfg cfg; + cfg.value = p->value; + if (enable & IP_CLK_ENABLE) { + cfg.BIT.clkEnMask |= 1 << matchInfo->bitOffset; + cfg.BIT.softResetReq &= ~(1 << matchInfo->bitOffset); + } else { + cfg.BIT.clkEnMask &= ~(1 << matchInfo->bitOffset); + } + p->value = cfg.value; +} + +/** + * @brief Get Enable status of IP in APB_HS_SUBSYS + * @param matchInfo IP without Clock select match info + * @retval Clock Enable status + */ +static unsigned int CRG_IpWoClkSelEnableGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_IpWoClkSelectCfg *p = (CRG_IpWoClkSelectCfg *)(void *)(base + matchInfo->regOffset); + CRG_IpWoClkSelectCfg cfg; + + cfg.value = p->value; + return (cfg.BIT.clkEnMask & (1 << matchInfo->bitOffset)) == 0 ? false : true; +} + +/** + * @brief Reset/undo reset of IP in APB_HS_SUBSYS + * @param matchInfo IP without Clock select match info + * @param reset BASE_CFG_SET or BASE_CFG_UNSET + * @retval None + */ +static void CRG_IpWoClkSelResetSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int reset) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_IpWoClkSelectCfg *p = (CRG_IpWoClkSelectCfg *)(void *)(base + matchInfo->regOffset); + CRG_IpWoClkSelectCfg cfg; + cfg.value = p->value; + if (reset & BASE_CFG_SET) { + cfg.BIT.softResetReq |= 1 << matchInfo->bitOffset; + } else { + cfg.BIT.softResetReq &= ~(1 << matchInfo->bitOffset); + } + p->value = cfg.value; +} + +/** + * @brief Get Reset status of IP in APB_HS_SUBSYS + * @param matchInfo IP without Clock select match info + * @retval Clock select reset status + */ +static unsigned int CRG_IpWoClkSelResetGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_IpWoClkSelectCfg *p = (CRG_IpWoClkSelectCfg *)(void *)(base + matchInfo->regOffset); + CRG_IpWoClkSelectCfg cfg; + cfg.value = p->value; + return (cfg.BIT.softResetReq & (1 << matchInfo->bitOffset)) ? BASE_CFG_SET : BASE_CFG_UNSET; +} + +/** + * @brief Enable/Disable ADC Clock + * @param matchInfo ADC match info + * @param enable IP_CLK_ENABLE + * @retval None + */ +static void CRG_AdcEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + CRG_AdcIpCfg cfg; + cfg.value = p->value; + if (enable) { + cfg.BIT.cken = BASE_CFG_SET; + cfg.BIT.sys_cken = BASE_CFG_SET; + cfg.BIT.srst_req = BASE_CFG_UNSET; + cfg.BIT.sys_srst_req = BASE_CFG_UNSET; + cfg.BIT.ana_srst_req = BASE_CFG_UNSET; + } else { + cfg.BIT.cken = BASE_CFG_UNSET; + cfg.BIT.sys_cken = BASE_CFG_UNSET; + } + p->value = cfg.value; +} + +/** + * @brief Get Enable status of ADC + * @param matchInfo ADC match info + * @retval Cken of ADC + */ +static unsigned int CRG_AdcEnableGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + unsigned int enable; + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + enable = ((p->BIT.cken != 0) && (p->BIT.sys_cken != 0)) ? IP_CLK_ENABLE : IP_CLK_DISABLE; + return enable; +} + +/** + * @brief Set ADC Clock Select + * @param matchInfo ADC match info + * @param clkSelect @see CRG_AdcClkSelect + * @retval None + */ +static void CRG_AdcClkSelectSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int clkSelect) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + p->BIT.cksel = (unsigned int)clkSelect; +} + +/** + * @brief Get ADC Clock Select + * @param matchInfo ADC match info + * @retval Adc Clock select @see CRG_AdcClkSelect + */ +static unsigned int CRG_AdcClkSelectGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + return p->BIT.cksel; +} + +/** + * @brief Set ADC Div + * @param matchInfo ADC match info + * @param div Adc clock division + * @retval None + */ +static void CRG_AdcDivSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int div) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + p->BIT.div = div; /* write div */ +} + +/** + * @brief Get ADC clock division + * @param matchInfo ADC match info + * @retval Adc clock division + */ +static unsigned int CRG_AdcDivGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + return p->BIT.div; /* return div value */ +} + +/** + * @brief Reset/undo reset ADC + * @param matchInfo ADC match Info + * @param reset BASE_CFG_SET or BASE_CFG_UNSET + * @retval None + */ +static void CRG_AdcResetSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int reset) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + CRG_AdcIpCfg cfg; + + cfg.value = p->value; + if (reset) { + cfg.BIT.srst_req = BASE_CFG_SET; + cfg.BIT.sys_srst_req = BASE_CFG_SET; + cfg.BIT.ana_srst_req = BASE_CFG_SET; + } else { + cfg.BIT.srst_req = BASE_CFG_UNSET; + cfg.BIT.sys_srst_req = BASE_CFG_UNSET; + cfg.BIT.ana_srst_req = BASE_CFG_UNSET; + } + p->value = cfg.value; +} + +/** + * @brief Get Reset Status of ADC + * @param matchInfo ADC match Info + * @retval reset BASE_CFG_SET or BASE_CFG_UNSET + */ +static unsigned int CRG_AdcResetGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + unsigned int reset; + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_AdcIpCfg *p = (CRG_AdcIpCfg *)(void *)(base + matchInfo->regOffset); + reset = p->BIT.srst_req; + reset |= p->BIT.sys_srst_req; + reset |= p->BIT.ana_srst_req; + return reset; +} + +/** + * @brief Enable/Disable DAC Clock + * @param matchInfo DAC match info + * @param enable IP_CLK_ENABLE + * @retval None + */ +static void CRG_DacEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_DacIpCfg *p = (CRG_DacIpCfg *)(void *)(base + matchInfo->regOffset); + CRG_DacIpCfg cfg; + cfg.value = p->value; + if (enable) { + cfg.BIT.softResetReq &= ~(BASE_CFG_SET << matchInfo->bitOffset); + cfg.BIT.clkEnMask |= BASE_CFG_SET << matchInfo->bitOffset; + } else { + cfg.BIT.clkEnMask &= ~(BASE_CFG_SET << matchInfo->bitOffset); + } + p->value = cfg.value; +} + +/** + * @brief Get Enable status of DAC + * @param matchInfo DAC Match info + * @retval Cken and Sys_cken of ADC + */ +static unsigned int CRG_DacEnableGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + unsigned int enable; + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_DacIpCfg *p = (CRG_DacIpCfg *)(void *)(base + matchInfo->regOffset); + if ((p->BIT.clkEnMask & (1 << matchInfo->bitOffset)) != 0) { + enable = BASE_CFG_SET; + } else { + enable = BASE_CFG_UNSET; + } + return enable; +} + +/** + * @brief Set DAC Div + * @param matchInfo DAC Match info + * @param div dac div parameter + */ +static void CRG_DacDivSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int div) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_DacIpCfg *p = (CRG_DacIpCfg *)(void *)(base + matchInfo->regOffset); + CRG_DacIpCfg cfg; + cfg.value = p->value; + cfg.BIT.div &= ~(DAC_DIV_MASK << (matchInfo->bitOffset * DAC_DIV_BITLEN)); + cfg.BIT.div |= (div & DAC_DIV_MASK) << (matchInfo->bitOffset * DAC_DIV_BITLEN); + p->value = cfg.value; +} + +/** + * @brief Get DAC Div + * @param matchInfo DAC Match info + * @return div dac div parameter + */ +static unsigned int CRG_DacDivGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + unsigned int div; + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_DacIpCfg *p = (CRG_DacIpCfg *)(void *)(base + matchInfo->regOffset); + div = p->BIT.div; + div >>= (matchInfo->bitOffset * DAC_DIV_BITLEN); + return (div & DAC_DIV_MASK); +} + +/** + * @brief Reset/undo reset DAC + * @param matchInfo DAC match Info + * @param reset DAC_SOFTRESET + */ +static void CRG_DacResetSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int reset) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_DacIpCfg *p = (CRG_DacIpCfg *)(void *)(base + matchInfo->regOffset); + CRG_DacIpCfg cfg; + + cfg.value = p->value; + if (reset != 0) { + cfg.BIT.softResetReq |= BASE_CFG_SET << matchInfo->bitOffset; + } else { + cfg.BIT.softResetReq &= ~(BASE_CFG_SET << matchInfo->bitOffset); + } + p->value = cfg.value; +} + +/** + * @brief Get Reset Status of DAC + * @param matchInfo DAC match Info + * @return unsigned int DAC_SOFTRESET + */ +static unsigned int CRG_DacResetGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + CRG_DacIpCfg *p = (CRG_DacIpCfg *)(void *)(base + matchInfo->regOffset); + return ((p->BIT.softResetReq >> matchInfo->bitOffset) & BASE_CFG_SET); +} + +/** + * @brief Enable Clock of EFC + * @param matchInfo EFC match Info + * @param enable IP_CLK_ENABLE or IP_CRG_DISABLE + */ +static void CRG_EfcEnableSet(const CHIP_CrgIpMatchInfo *matchInfo, unsigned int enable) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + PERI_CRG32_Reg *p = (PERI_CRG32_Reg *)(void *)(base + matchInfo->regOffset); + p->eflash_cken = (enable & IP_CLK_ENABLE) ? BASE_CFG_SET : BASE_CFG_UNSET; +} + +/** + * @brief Disable Clock of EFC + * @param matchInfo EFC match Info + * @return unsigned int IP_CLK_ENABLE or IP_CRG_DISABLE + */ +static unsigned int CRG_EfcEnableGet(const CHIP_CrgIpMatchInfo *matchInfo) +{ + uintptr_t base = (uintptr_t)(void *)g_crgBaseAddr; + PERI_CRG32_Reg *p = (PERI_CRG32_Reg *)(void *)(base + matchInfo->regOffset); + return p->eflash_cken; +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dac/common/inc/dac.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dac/common/inc/dac.h new file mode 100644 index 00000000..4849c092 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dac/common/inc/dac.h @@ -0,0 +1,81 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dac.h + * @author MCU Driver Team. + * @brief DAC module driver. + * This file provides functions declaration of the Comparator. + * + DAC's Initialization and de-initialization functions + * + Set DAC value function + */ +#ifndef McuMagicTag_DAC_H +#define McuMagicTag_DAC_H + +#include "dac_ip.h" + +/** + * @defgroup DAC DAC + * @brief DAC module. + * @{ + */ + +/** + * @defgroup DAC_Common DAC Common + * @brief DAC common external module. + * @{ + */ + +/** + * @defgroup DAC_Handle_Definition DAC Handle Definition + * @{ + */ + +/** + * @brief DAC Handle + */ +typedef struct _DAC_Handle { + DAC_RegStruct *baseAddress; /**< DAC registers base address. */ + volatile unsigned int dacValue; /**< DAC configuration value. */ + + DAC_ExtendHandle handleEx; /* DAC Handle Ex. */ +} DAC_Handle; + +/** + * @} + */ + +/** + * @defgroup DAC_API_Declaration DAC HAL API + * @{ + */ +/* DAC APIs */ +BASE_StatusType HAL_DAC_Init(DAC_Handle *dacHandle); +BASE_StatusType HAL_DAC_DeInit(DAC_Handle *dacHandle); +void HAL_DAC_SetValue(DAC_Handle *dacHandle, unsigned int value); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dac/inc/dac_ex.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dac/inc/dac_ex.h new file mode 100644 index 00000000..518941dd --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dac/inc/dac_ex.h @@ -0,0 +1,51 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dac_ex.h + * @author MCU Driver Team + * @brief DAC module driver + * @details This file provides DCL functions to manage DAC and Definition of + * specific parameters. + * + DAC sine wave mode. + */ +#ifndef McuMagicTag_DAC_EX_H +#define McuMagicTag_DAC_EX_H +#include "dac.h" +/** + * @addtogroup DAC_IP + * @{ + */ + +/** + * @defgroup DAC_EX_API_Declaration DAC HAL API EX + * @{ + */ + + /* DAC sine mode setting. */ + BASE_StatusType HAL_DAC_SetSineModeEx(DAC_Handle *dacHandle, unsigned short intervalValue); + + void HAL_DAC_DisableSineModeEx(DAC_Handle *dacHandle); + + + /** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dac/inc/dac_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dac/inc/dac_ip.h new file mode 100644 index 00000000..a780287b --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dac/inc/dac_ip.h @@ -0,0 +1,195 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dac_ip.h + * @author MCU Driver Team + * @brief DAC module driver. + * This file provides DCL functions to manage DAC and Definitions of specific parameters. + * + Definition of DAC configuration parameters. + * + DAC register mapping structure. + * + Parameters check functions. + * + Direct configuration layer interface. + */ +#ifndef McuMagicTag_DAC_IP_H +#define McuMagicTag_DAC_IP_H + +#include "baseinc.h" + +#ifdef DAC_PARAM_CHECK +#define DAC_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define DAC_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define DAC_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define DAC_ASSERT_PARAM(para) ((void)0U) +#define DAC_PARAM_CHECK_NO_RET(para) ((void)0U) +#define DAC_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +#define DAC_MAX_OUT_VALUE 0xFF +#define DAC_MAX_SINE_INTERVAL_VALUE 0xFF +/** + * @addtogroup DAC + * @{ + */ + +/** + * @defgroup DAC_IP DAC_IP + * @brief DAC_IP: dac_v0. + * @{ + */ + +/** + * @defgroup DAC_REG_Definition DAC Register Structure. + * @brief DAC Register Structure Definition. + * @{ + */ +typedef struct { + bool sineMode; /* DAC sine mode enable. */ + unsigned short sineCountValue; /* DAC output number in sine mode. */ +} DAC_ExtendHandle; + +/** + * @brief DAC control. + */ +typedef union { + unsigned int reg; + struct { + unsigned int dac_en : 1; /**< DAC Enable. */ + unsigned int reserved_0 : 1; + unsigned int dac_test_en : 1; /**< DAC sine wave mode enable. */ + unsigned int reserved_1 : 5; + unsigned int dac_test_num : 8; /**< DAC sine wave interval count value. */ + unsigned int reserved_2 : 16; + } BIT; +} volatile DAC_CTRL_REG; + +/** + * @brief DAC configuration value. + */ +typedef union { + unsigned int reg; + struct { + unsigned int dac_value : 8; /**< DAC digital signal, corresponding to the voltage */ + unsigned int reserved_0 : 24; + } BIT; +} volatile DAC_VALUE_REG; + +/** + * @brief DAC registers definition structure. + */ +typedef struct _DAC_RegStruct { + DAC_CTRL_REG DAC_CTRL; /**< DAC control register. Offset address: 0x00000000U */ + DAC_VALUE_REG DAC_VALUE; /**< DAC configuration value register. Offset address: 0x00000004U */ +} volatile DAC_RegStruct; + +/* Parameter Check -----------------------------------------------------------*/ + +/** + * @brief Verify count value of the DAC sine wave interval. + * @param intervalNum interval value. + * @retval true + * @retval false + */ +static inline bool IsDacSineIntervalNum(unsigned short intervalNum) +{ + return (intervalNum <= DAC_MAX_SINE_INTERVAL_VALUE); +} + +/** + * @brief Set DAC test value + * @param dacx: DAC register base address. + * @param value: DAC test value. + * @retval None. + */ +static inline void DCL_DAC_SetTstValue(DAC_RegStruct *dacx, unsigned short value) +{ + DAC_ASSERT_PARAM(IsDACInstance(dacx)); + DAC_PARAM_CHECK_NO_RET(IsDacSineIntervalNum(value)); + DAC_CTRL_REG dacCtrlReg; /* Set sine interval value. */ + dacCtrlReg.reg = dacx->DAC_CTRL.reg; + dacCtrlReg.BIT.dac_test_num = value; + dacx->DAC_CTRL.reg = dacCtrlReg.reg; +} + +/** + * @brief Enable DAC dynamic test + * @param dacx: DAC register base address. + * @retval None. + */ +static inline void DCL_DAC_EnableDynamicTst(DAC_RegStruct *dacx) +{ + DAC_ASSERT_PARAM(IsDACInstance(dacx)); + dacx->DAC_CTRL.BIT.dac_test_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable DAC dynamic test + * @param dacx: DAC register base address. + * @retval None. + */ +static inline void DCL_DAC_DisableDynamicTst(DAC_RegStruct *dacx) +{ + DAC_ASSERT_PARAM(IsDACInstance(dacx)); + dacx->DAC_CTRL.BIT.dac_test_en = BASE_CFG_DISABLE; +} + +/** + * @brief Enable DAC + * @param dacx: DAC register base address. + * @retval None. + */ +static inline void DCL_DAC_Enable(DAC_RegStruct *dacx) +{ + DAC_ASSERT_PARAM(IsDACInstance(dacx)); + dacx->DAC_CTRL.BIT.dac_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable DAC + * @param dacx: DAC register base address. + * @retval None. + */ +static inline void DCL_DAC_Disable(DAC_RegStruct *dacx) +{ + DAC_ASSERT_PARAM(IsDACInstance(dacx)); + dacx->DAC_CTRL.BIT.dac_en = BASE_CFG_DISABLE; +} + +/** + * @brief Set DAC value + * @param dacx: DAC register base address. + * @param value: DAC value. + */ +static inline void DCL_DAC_SetValue(DAC_RegStruct *dacx, unsigned int value) +{ + DAC_ASSERT_PARAM(IsDACInstance(dacx)); + DAC_PARAM_CHECK_NO_RET(value <= DAC_MAX_OUT_VALUE); + dacx->DAC_VALUE.BIT.dac_value = value; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dac/src/dac.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dac/src/dac.c new file mode 100644 index 00000000..2bcd63d7 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dac/src/dac.c @@ -0,0 +1,79 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dac.c + * @author MCU Driver Team. + * @brief DAC HAL level module driver. + * This file provides firmware functions to manage the following + * functionalities of the DAC and Comparator. + * + DAC's Initialization and de-initialization functions + * + Set DAC value function + */ +#include "dac.h" +#include "assert.h" + +/** + * @brief Set DAC value + * @param dacHandle: DAC handle. + * @param value: DAC value. + * @retval None. + */ +void HAL_DAC_SetValue(DAC_Handle *dacHandle, unsigned int value) +{ + DAC_ASSERT_PARAM(dacHandle != NULL); + DAC_ASSERT_PARAM(IsDACInstance(dacHandle->baseAddress)); + DAC_PARAM_CHECK_NO_RET(value <= DAC_MAX_OUT_VALUE); + /* Change the conversion value of the DAC. */ + dacHandle->baseAddress->DAC_VALUE.BIT.dac_value = value; +} + +/** + * @brief DAC HAL Init + * @param dacHandle: DAC handle. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_DAC_Init(DAC_Handle *dacHandle) +{ + DAC_ASSERT_PARAM(dacHandle != NULL); + DAC_ASSERT_PARAM(IsDACInstance(dacHandle->baseAddress)); + DAC_PARAM_CHECK_WITH_RET(IsDacSineIntervalNum(dacHandle->handleEx.sineCountValue), BASE_STATUS_ERROR); + /* Conversion value of the DAC. */ + dacHandle->baseAddress->DAC_VALUE.BIT.dac_value = dacHandle->dacValue; + /* DAC sine mode configuration and setting. */ + DAC_CTRL_REG dacCtrlReg; + dacCtrlReg.reg = dacHandle->baseAddress->DAC_CTRL.reg; + dacCtrlReg.BIT.dac_test_num = dacHandle->handleEx.sineCountValue; + dacHandle->baseAddress->DAC_CTRL.reg = dacCtrlReg.reg; + dacHandle->baseAddress->DAC_CTRL.BIT.dac_test_en = dacHandle->handleEx.sineMode; + /* Turn on the DAC. */ + dacHandle->baseAddress->DAC_CTRL.BIT.dac_en = BASE_CFG_ENABLE; + return BASE_STATUS_OK; +} + +/** + * @brief DAC HAL DeInit + * @param dacHandle: DAC handle. + * @retval BASE_StatusType: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_DAC_DeInit(DAC_Handle *dacHandle) +{ + DAC_ASSERT_PARAM(dacHandle != NULL); + DAC_ASSERT_PARAM(IsDACInstance(dacHandle->baseAddress)); + dacHandle->baseAddress->DAC_CTRL.reg = BASE_CFG_DISABLE; /* Disable DAC, clears the count value. */ + dacHandle->baseAddress->DAC_VALUE.reg = BASE_CFG_DISABLE; /* Clear DAC value. */ + return BASE_STATUS_OK; +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dac/src/dac_ex.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dac/src/dac_ex.c new file mode 100644 index 00000000..55c6be3d --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dac/src/dac_ex.c @@ -0,0 +1,59 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dac_ex.c + * @author MCU Driver Team + * @brief DAC module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the DAC. + * + DAC Sine mode setting. + */ +#include "dac_ex.h" + +/** + * @brief DAC sine wave mode configuration. The DAC automatically generates 8-bit sine wave digital signals, + and outputs a sine wave sampling point every intervalValue clk_dac cycles. A complete sine wave period with + 100 sampling points. + * @param dacHandle DAC handle. + * @param intervalValue A sine wave sampling point is output every intervalValue clk_dac cycles. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_DAC_SetSineModeEx(DAC_Handle *dacHandle, unsigned short intervalValue) +{ + DAC_ASSERT_PARAM(dacHandle != NULL); + DAC_ASSERT_PARAM(IsDACInstance(dacHandle->baseAddress)); + DAC_PARAM_CHECK_WITH_RET(IsDacSineIntervalNum(intervalValue), BASE_STATUS_ERROR); + /* DAC sine mode configuration and setting. */ + DAC_CTRL_REG dacCtrlReg; + dacCtrlReg.reg = dacHandle->baseAddress->DAC_CTRL.reg; /* Sine mode and number setting. */ + dacCtrlReg.BIT.dac_test_num = intervalValue; + dacCtrlReg.BIT.dac_test_en = BASE_CFG_ENABLE; + dacHandle->baseAddress->DAC_CTRL.reg = dacCtrlReg.reg; + return BASE_STATUS_OK; +} + +/** + * @brief Disable DAC sine mode. + * @param dacHandle DAC handle. + * @retval None. + */ +void HAL_DAC_DisableSineModeEx(DAC_Handle *dacHandle) +{ + DAC_ASSERT_PARAM(dacHandle != NULL); + DAC_ASSERT_PARAM(IsDACInstance(dacHandle->baseAddress)); + dacHandle->baseAddress->DAC_CTRL.BIT.dac_test_en = BASE_CFG_DISABLE; /* Disable DAC sine mode. */ +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/inc/debug.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/inc/debug.h new file mode 100644 index 00000000..ce2a1aa5 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/inc/debug.h @@ -0,0 +1,90 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file debug.h + * @author MCU Driver Team + * @brief Header file containing functions prototypes of DEBUG module. + * + Initialization and de-initialization functions + * + Format print function + */ + +#ifndef McuMagicTag_DEBUG_H +#define McuMagicTag_DEBUG_H + +#include "uart.h" + +#ifdef DEBUG_PARAM_CHECK +#define DEBUG_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define DEBUG_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define DEBUG_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define DEBUG_ASSERT_PARAM(para) ((void)0U) +#define DEBUG_PARAM_CHECK_NO_RET(para) ((void)0U) +#define DEBUG_PARAM_CHECK_WITH_RET(param, ret) ((void)0U) +#endif + +/** + * @defgroup DEBUG DEBUG + * @brief DEBUG module. + * @{ + */ + + +/** + * @defgroup DEBUG_Common DEBUG Common + * @brief DEBUG common external module. + * @{ + */ + +/* Macro definitions for enabling the function of DEBUG_PRINT submodule */ +#define BAUDRATE 115200 + +#if (DBG_PRINTF_USE == DBG_USE_NO_PRINTF) +static inline int DBG_dummy(const char *format, ...) +{ + BASE_FUNC_UNUSED(format); + return 0; +} /* dummy debug function */ +#define DBG_PRINTF DBG_dummy /* Delete all print statement */ +#endif + +#if (DBG_PRINTF_USE == DBG_USE_UART_PRINTF) +#define DBG_PRINTF DBG_UartPrintf /**< Select the customized printf function */ +#endif + +/** + * @defgroup DEBUG_API_Declaration DEBUG HAL API + * @{ + */ +BASE_StatusType DBG_UartPrintInit(unsigned int baudRate); +BASE_StatusType DBG_UartPrintDeInit(void); + +/* Format print function */ +int DBG_UartPrintf(const char *format, ...); /* Supported format: %c, %s, %d, %u, %x, %X, %p, %f */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_DEBUG_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/cmd.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/cmd.h new file mode 100644 index 00000000..ae00b8e9 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/cmd.h @@ -0,0 +1,89 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cmd.h + * @author MCU Driver Team + * @brief Header file containing functions prototypes of DEBUG module. + * + Initialization and de-initialization functions + * + Format cmd function + */ +#ifndef CMD_H +#define CMD_H + +#include "module.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C"{ +#endif +#endif /* __cplusplus */ + +#ifndef CMD_REGESTER_MAX_NUM +#define CMD_REGESTER_MAX_NUM 128 // The maximum length of the command +#endif + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup CMD_Def CMD_Def + * @brief Command line registration initialization. + * @{ + */ + +/* Defines a function pointer to command registered function */ +typedef int (*pfncmd)(unsigned int argc, const char *argv[]); +/* defines the structure required for registering a function */ +struct cmdRegisterTable { + char *name; + pfncmd func; +}; + +/** + * @brief cmd_regester + * @attention None + * + * @param cmdName [IN] registration name, which is a character string + * @param func [IN] register the function corresponding to the name + * @retval void None + */ +void ExtCmdRegister(char *cmdName, pfncmd func); + +/** + * @brief get regester address + * @attention None + * + * @retval struct cmdRegisterTable * + */ +struct cmdRegisterTable *GetRegisterAddr(void); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ +/** + * @} + */ + +/** + * @} + */ +#endif /* __EXT_DEBUG_H__ */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/cmd_common.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/cmd_common.h new file mode 100644 index 00000000..909206c8 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/cmd_common.h @@ -0,0 +1,109 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cmd_common.h + * @author MCU Driver Team + * @brief cmd module driver + * @details The header file contains the following declaration: + * + cmd configuration enums. + * + cmd register structures. + * + cmd DCL Functions. + * + Parameters check functions. + */ +#ifndef CMD_COMMON_H +#define CMD_COMMON_H + +/* Include Header Files */ +#include "type.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +/* Macro Definition */ +#define MATCH_CMD_BUF_CNT 8 + +#define ARGS_NUM_MAX 16 +#define CMD_BUF_MAX 128 + +#define CMD_NUM_MAX 5 + +#define DIR_KEY_HEAD (0x1b) +#define DEL ((char)255) +#define DEL7 ((char)127) + +#define CTL_CH(c) ((c) - 'a' + 1) +#define CTL_CH_C 3 /* define the ctl c key */ +#define CTL_CH_P 16 /* define the ctl p key */ +#define CTL_CH_N 14 /* define the ctl n key */ +#define CTL_BACKSPACE ('\b') +#define SPACE_KEY (' ') +#define TAB_KEY 9 /* define the tab key */ +#define ENTER_KEY1 13 /* define the '\r' */ +#define ENTER_KEY2 10 /* define the '\n' */ + +#define APP_CMD_ERR_PRINT(fmt...) EXT_ERR_PRINT(EXT_MODULE_APP_CMD, fmt) + +/** + * @addtogroup DEBUG + * @brief DEBUG module. + * @{ + */ + +/** + * @defgroup DEBUG_Log DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup CMD_COMMON_Def CMD_COMMON_Def + * @brief Common Command Line Interface. + * @{ + */ +/** + * @} + */ + +/** + * @brief Interprets the string of characters. + * @param cmdStr command string + * @argv At the command line, type a string of cosmonies + * @retval the following is the standard + */ +unsigned int CmdParserParam(char *cmdStr, const char *argv[]); +/** + * @brief Interprets the string of characters. + * @param None + * @retval None + */ +void ExtAppCmdProcess(void); +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ +/** + * @} + */ + +/** + * @} + */ +#endif /* __APP_COMMAND_H__ */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/command.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/command.h new file mode 100644 index 00000000..4732fafa --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/command.h @@ -0,0 +1,91 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file command.h + * @author MCU Driver Team + * @brief Header file containing functions prototypes of DEBUG module. + * + Initialization and de-initialization functions + * + Format command function + */ +#ifndef COMMAND_H +#define COMMAND_H + +#include "cmd.h" + +#define UART_SWITCH_CMD "soct_pq_tool" + +#define CMD_SECTION __attribute__((unused, section(".command"))) + +struct CmdTable { + const char *name; /* Command Name */ + int (*pfncmd)(unsigned int argc, const char *argv[]); +}; + +#define CMD_REGESTER(name, cmd) \ + struct CmdTable __cmd_##name CMD_SECTION = { #name, cmd } + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup COMMAND_Def COMMAND_Def + * @brief Command processing. + * @{ + */ + +/** + * @brief use cmd line to find cmd + * @attention None + * + * @param str [IN] command character string carried in the command line + * @retval struct cmdRegisterTable * + */ +struct cmdRegisterTable *ExtCmdFindCmd(const char *str); + +/** + * @brief use cmd line to match cmd read + * @attention None + * @param head [IN] enter a portion of the complete command you want at the command line + * @param res [out] the string array is used to store all matching strings + * @param len [IN] length of the string array + * @param findCnt [out] Number of matched strings + * @param tailId [out] Record the location of the last search + * @retval unsigned char Whether the matching is complete. + * If the matching is successful, true is returned. If the matching fails, false is returned + */ +unsigned char ExtCmdFindMatchCmd(const char *head, const char *res[], unsigned char resLen, unsigned char *findCnt, + unsigned int *tailId); +#define UESR_CMD_SECTION __attribute__((unused, section(".user_command"))) + +struct UserCmdTable { + unsigned short cmd; /* Command ID */ + int (*pfnUserMCUCmd)(unsigned char len, unsigned char* param); +}; + +#define USRER_CMD_REGESTER(pfn, cmd) \ + struct UserCmdTable __user_cmd_##pfn USER_CMD_SECTION = { cmd, pfn } +/** + * @} + */ + +/** + * @} + */ +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/common.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/common.h new file mode 100644 index 00000000..0e13687c --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/common.h @@ -0,0 +1,90 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file common.h + * @author MCU Driver Team + * @brief Header file containing functions prototypes of cmd module. + * + Initialization and de-initialization functions + * + Format common function + */ +#ifndef COMMON_H +#define COMMON_H + +#include "type.h" +#include "ext_log.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* __cplusplus */ + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup CONFIG_Def CONFIG_Def + * @brief Processing Special Characters. + * @{ + */ + +#define EXT_ARRAY_COUNT(x) (sizeof(x) / sizeof(x[0])) +#define EXT_ALIGN_4(x) ((unsigned int)(x + 0x3) & (~0x3)) +#define CHAR_CR '\r' /* 0x0D */ +#define CHAR_LF '\n' /* 0x0A */ + +#define EXT_REG_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) /* Write by register address */ +#define EXT_REG_READ(addr, val) ((val) = *(volatile unsigned int *)(addr)) /* Read by register address */ +#define EXT_REG_READ32(addr) (*(volatile unsigned int *)(addr)) +#define EXT_REG_WRITE32(addr, val) (*(volatile unsigned int *)(addr) = (val)) +#define EXT_REG_WRITE_MASK(addr, val, mask) (*(volatile unsigned int *)((addr) & 0xFFFFFFFC) = \ + ((*(volatile unsigned int *)((addr)& 0xFFFFFFFC)) & (~(mask))) | ((val) & (mask))) +#define EXT_REG_TOOLWRITE(addr, val) (*(volatile unsigned int *)((addr) & 0xFFFFFFFC) = (val)) +#define EXT_REG_TOOLREAD(addr, val) ((val) = *(volatile unsigned int *)((addr) & 0xFFFFFFFC)) + +#define ABS(x) (((x) >= 0) ? (x) : -(x)) +#define MAX(a, b) (((a) >= (b)) ? (a) : (b)) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define CLIP(a) (((a) >= 0) ? (a) : 0) +#define CLIP2(m, n, a) (((a) > (m)) ? (m) : ((a) < (n) ? (n) : (a))) +#define CLIP3(low, high, x) (MAX(MIN((x), high), low)) +#define RSHFT(x, n) ((x) >= 1 ? \ + (((x) + (1 << ((n)-1))) >> (n)) : (-(((-(x)) + (1 << ((n)-1))) >> (n)))) + +#define ROUND_UP(x, align) (((x) + (align)-1) & ~((align)-1)) +#define ROUND_DOWN(x, align) ((x) & (~((align) - 1))) + +#define EXT_FENCE(void) do { \ + __asm__("fence\n\r"); \ +} while (0) +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ +/** + * @} + */ + +/** + * @} + */ +#endif /* __EXT_COMMON_H__ */ + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/config.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/config.h new file mode 100644 index 00000000..573eaa74 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/config.h @@ -0,0 +1,114 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file config.h + * @author MCU Driver Team + * @brief Header file containing functions prototypes of config module. + * + Initialization and de-initialization functions + * + Format config function + */ +#ifndef CONFIG_H +#define CONFIG_H + + +#include "module.h" +#include "type.h" +#include "typedefs.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C"{ +#endif +#endif /* __cplusplus */ + + +#define DATA_ITEM_MAX_LEN 256 /* maximum length of data items */ + +enum DataItem { + DATA_ITEM_EVENT, + DATA_ITEM_NUM_MAX, +}; + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup CONFIG_Def CONFIG_Def + * @brief Content read/write. + * @{ + */ + +/** + * @brief load_read Reads the content in the configuration address based on the address + * @attention None + * + * @param add [IN] Indicates the address to be read + * @param value [OUT] read content + * @param len [OUT] Length of the read content + * @retval None + */ +void ExtLoadRead(uintptr_t add, char *value, int len); + +/** + * @extLoadWrite Write the content in the configuration address according to the address + * @attention None + * + * @param add [IN] Address to be written + * @param value [IN] What is written + * @param len [IN] Length of the content to be written + * @retval None + */ +void ExtLoadWrite(uintptr_t add, const char *value, int len); + +/** + * @extConfigRead Reads content based on data items + * @attention None + * + * @param item [IN] Read Data Items + * @param value [OUT] Read content + * @param len [OUT] Length of the read content + * @retval None + */ +void ExtConfigRead(enum DataItem item, char *value, int len); + +/** + * @brief load_write Write content based on data items + * @attention Nonw + * + * @param item [IN] Data Items Written + * @param value [IN] Contents of write + * @param len [IN] Length of the content to be written + * @retval None + */ +void ExtConfigWrite(enum DataItem item, const char *value, int len); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ +/** + * @} + */ + +/** + * @} + */ +#endif /* __EXT_DEBUG_H__ */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/console.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/console.h new file mode 100644 index 00000000..d870fd98 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/console.h @@ -0,0 +1,73 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file console.h + * @author MCU Driver Team + * @brief Header file containing functions prototypes of console module. + * + Initialization and de-initialization functions + * + Format console function + */ +#ifndef CONSOLE_H +#define CONSOLE_H + +#include "uart.h" + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup CONSOLE_Def CONSOLE_Def + * @brief Serial port printing initialization. + * @{ + */ + + /** + * @brief Read Status Query + * @{ + */ +int ConsoleGetQuery(void); + /** + * @brief Read a single character + * @{ + */ +int ConsoleGetc(void); + /** + * @brief Output String + * @{ + */ +int ConsolePuts(const char *str); + /** + * @brief Output Characters + * @{ + */ +void ConsolePutc(const char c); +/* Format print function */ +int UartPrintf(const char *format, ...); + +/* init console uart */ +void ConsoleInit(UART_Handle uart); +/** + * @} + */ + +/** + * @} + */ +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/dfx_debug.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/dfx_debug.h new file mode 100644 index 00000000..69d44fb9 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/dfx_debug.h @@ -0,0 +1,74 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dfx_debug.h + * @author MCU Driver Team + * @brief Header file containing functions prototypes of DFX_DEBUG module. + * + Initialization and de-initialization functions + * + Format DFX_DEBUG function + */ +#ifndef DFX_DEBUG_H +#define DFX_DEBUG_H + +#include "module.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* __cplusplus */ + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup DFX_DEBUG_Def DFX_DEBUG_Def + * @brief Setting the Debug Mode. + * @{ + */ + +enum ExtDebugMode { + DEBUG, + RUNNING +}; +/** + * @brief extSetDebugMode + * @attention None + * + * @param ExtDebugMode [IN] Operation mode + * @retval None + */ +void ExtSetDebugMode(enum ExtDebugMode mode); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DFX_DEBUG_H */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/dfx_log.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/dfx_log.h new file mode 100644 index 00000000..bbb51567 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/dfx_log.h @@ -0,0 +1,142 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dfx_log.h + * @author MCU Driver Team + * @brief dfx_log module driver + * @details The header file contains the following declaration: + * + Perhaps and print the log content. + */ +#ifndef DFX_LOG_H +#define DFX_LOG_H + +#include "ext_log.h" + +#ifdef __cplusplus__ +#if __cplusplus__ +extern "C" { +#endif +#endif + +#define LOG_UINT_MAX_LEN 512 +#define LOG_MEM_POOL_MAX_LEN 1024 +#define LOG_LAST_WORD_MAX_LEN 1024 + +#define LOG_STATEMENT_MAX_LEN 20 + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup DFX_LOG_Def DFX_LOG_Def + * @brief Initialization of Miniaturized Logs. + * @{ + */ + +struct MemoryLog { + unsigned char enable; + unsigned char mmzBuf[LOG_MEM_POOL_MAX_LEN]; + unsigned int writePos; + unsigned int logLen; +}; +struct SysLogCtx { + unsigned char init; + char **modStr; + enum ExtLogLevel logLevel[EXT_MODULE_BUTT]; + struct MemoryLog memLog; +}; +struct SysDebugSwitch { + unsigned char enable; + struct SysLogCtx logCtx; +}; + +/** + * @brief get log context. + * @attention None + * + * @retval struct SysLogCtx *. + */ +struct SysLogCtx *GetLogCtx(void); + +/** + * @brief init log context. + * @attention None + * + * @param ctx: Pointer to the SysLogCtx structure to be initialized. + * @retval None + */ +void LogCtxInit(struct SysLogCtx *ctx); + +/** + * @brief init struct MemoryLog. + * @attention None + * + * @param memData: Pointer to the MemoryLog structure to be initialized + * @retval None + */ +void InitMemoryData(struct MemoryLog *memData); + +/** + * @brief get debug switch. + * @attention None + * + * @retval struct SysDebugSwitch *. + */ +struct SysDebugSwitch *GetDebugSwitch(void); + +/** + * @brief get memory data. + * @attention None + * + * @retval struct MemoryLog *. + */ +struct MemoryLog *GetMemoryData(void); + +/** + * @brief Register the dfx cmd + * @attention None + * + * @retval None + */ +void DfxCmdRegister(void); + +/** + * @brief get version info cmd + * @attention None + * + * @param argc: Number of input parameters. + * @param argv: Array of pointers + * @retval Return the setting result, success or failure. + */ +int CmdGetVersionInfo(void); + +#ifdef __cplusplus__ +#if __cplusplus__ +} +#endif +#endif /* end of __cplusplus */ +/** + * @} + */ + +/** + * @} + */ +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/errno.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/errno.h new file mode 100644 index 00000000..df88fbf3 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/errno.h @@ -0,0 +1,65 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file errno.h + * @author MCU Driver Team + * @brief Header file containing functions prototypes of erron module. + * + Initialization and de-initialization functions + * + Format erron function + */ +#ifndef ERRNO_H +#define ERRNO_H + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* __cplusplus */ + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup ERRNO_Def ERRNO_Def + * @brief Define the success flag. + * @{ + */ + +/* Customize the required return value */ +typedef enum { + EXT_SUCCESS = 0x0, + EXT_ERR_USER_BUSY = 0x01060002, + EXT_INVALID = 0xFFFFFFFE, + EXT_FAILURE = 0xFFFFFFFF, +} EXT_MCU_ERRNO; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ +/** + * @} + */ + +/** + * @} + */ +#endif /* __EXT_ERRNO_H__ */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/event.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/event.h new file mode 100644 index 00000000..7d7482e4 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/event.h @@ -0,0 +1,143 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file event.h + * @author MCU Driver Team + * @brief Header file containing functions prototypes of erron module. + * + Defines the function of reporting initialization events. + */ +#ifndef EVENT_CODE_H +#define EVENT_CODE_H + +#include "module.h" +#include "type.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C"{ +#endif +#endif /* __cplusplus */ + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup EVENT_Def EVENT_Def + * @brief Definition of the Event Reporting Function. + * @{ + */ + +#define SYS_GPIO_GROUP_REPORT 0 +#define USER_CMD_MAX_LEN 8 +#define EVENT_MAX_LEN 5 + +#define REPORT_EVENT_DONE 0xFFFFFFFF + + +typedef enum { + REPORT_LAST_WORD_EVENT, +} REPORT_EVENT; + +typedef enum { + BUS_SLAVE_IRQ_INT_WRITE_START, + BUS_SLAVE_IRQ_INT_WRITE_END, + BUS_SLAVE_IRQ_INT_READ_START, + BUS_SLAVE_IRQ_INT_READ_END, + BUS_SLAVE_IRQ_PGM_WRITE_START, + BUS_SLAVE_IRQ_PGM_WRITE_END, + BUS_SLAVE_IRQ_PGM_READ_START, + BUS_SLAVE_IRQ_PGM_READ_END, + BUS_SLAVE_IRQ_INT_FIFO, + BUS_SLAVE_IRQ_EXCEPTION, + BUS_SLAVE_IRQ_BUTT +} BUSS_IRQ_Type; + +typedef struct { + unsigned short cmd; /* Commands delivered by the user */ + unsigned char ack; + unsigned char len; + unsigned char param[USER_CMD_MAX_LEN]; +} UserCmd; + +typedef void (*pfnCB)(unsigned int); + +typedef enum { + DATA_TYPE_NOISE, DATA_TYPE_SELF, DATA_TYPE_STYLUS, DATA_TYPE_MUTUAL +} DataType; + +typedef struct { + unsigned char eventType; + unsigned char ack; + unsigned char len; + unsigned char param[EVENT_MAX_LEN]; +} McuEvent; + +typedef struct { + unsigned int reportType; /* Report Type */ + McuEvent event; +} McuReport; + +typedef struct { + McuReport report; + pfnCB pfnevent; +} UserEventObj; + +typedef struct { + unsigned int reportLock; + int gpioHandle; + unsigned int reportAddr; + unsigned short cmdNotFoudCount; + unsigned short reportFailedCount; + UserEventObj eventObj; + UserCmd cmd; +} UserMgr; + +/** + * @brief report event + * @attention None + * + * @param report event struct + * @retval The return value indicates that the event is reported successfully or failed. + */ +int UserReportEvent(UserEventObj *eventObj); + +/** + * @brief init event + * @attention None + * + * @retval The return value indicates that the event is reported successfully or failed. + */ +int EventInit(void); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __EXT_DEBUG_H__ */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/ext_log.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/ext_log.h new file mode 100644 index 00000000..1a211d0d --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/ext_log.h @@ -0,0 +1,275 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file ext_loh.h + * @author MCU Driver Team + * @brief log module driver + * @details The header file contains the following declaration: + * + Definition of the Miniaturized Log Structure + * + Definition of Miniaturized Log Output Functions + */ +#ifndef EXT_LOG_H +#define EXT_LOG_H + +#include "module.h" +#include "console.h" +#include "file_id_defs.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C"{ +#endif +#endif /* __cplusplus */ + +/* Serial port print definition */ +#define EXT_PRINT UartPrintf +/** + * @brief Initializing the Log Output Level + */ +enum ExtLogLevel { + EXT_LOG_LEVEL_FATAL, + EXT_LOG_LEVEL_ERROR, + EXT_LOG_LEVEL_WARNING, + EXT_LOG_LEVEL_INFO, + EXT_LOG_LEVEL_DBG, + EXT_LOG_LEVEL_BUTT, +}; + +enum ExtLogLevelToken { + FATAL, + ERR, + WARN, + INFO, + DBG, +}; +#define MAKE_XML_ID_UINT32(a, b) ((unsigned int)(((unsigned short)(a)) | ((unsigned int)((unsigned short)(b))) << 16)) + +#define EXT_FATAL_PRINT(modId, fmt...) +#define EXT_ERR_PRINT(modId, fmt...) UartPrintf(fmt) +#define EXT_WARN_PRINT(modId, fmt...) +#define EXT_INFO_PRINT(modId, fmt...) UartPrintf(fmt) +#define EXT_DBG_PRINT(modId, fmt...) + +#ifndef CFG_DFX_MINILOG_SUPPORT +#define CFG_DFX_MINILOG_SUPPORT 1 +#endif + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup EXT_LOG_Def EXT_LOG_Def + * @brief Interface for Printing Miniaturized Logs. + * @{ + */ + +/** + * @defgroup Various types of miniaturized log output + * @brief log output external module. + * @{ + */ +int ExtDrvLogOutBuf(enum ExtLogLevel level, enum ExtModule modId, unsigned int xmlId, + const unsigned int* logBuf, unsigned short logBufLen); +int ExtDrvLogOut0(enum ExtLogLevel level, enum ExtModule modId, unsigned int xmlId); +int ExtDrvLogOut1(enum ExtLogLevel level, enum ExtModule modId, unsigned int xmlId, unsigned int d0); +int ExtDrvLogOut2(enum ExtLogLevel level, enum ExtModule modId, unsigned int xmlId, unsigned int d0, unsigned int d1); +int ExtDrvLogOut3(enum ExtLogLevel level, enum ExtModule modId, unsigned int xmlId, unsigned int d0, unsigned int d1, + unsigned int d2); + +/** + * @defgroup Printing and outputting miniaturized logs + * @brief log output external module. + * @{ + */ +int ExtDrvLogSetLogLevel(enum ExtModule modId, enum ExtLogLevel level); +int ExtDrvLogOutFmt(enum ExtLogLevel level, enum ExtModule id, const char *fmt, ...); + +#ifndef EXT_LOG_LEVEL +#define EXT_LOG_LEVEL EXT_LOG_LEVEL_DBG +#endif +#define EXT_LOG_0(level, modId, msg) LOG_##level##_0(modId, msg) +#define EXT_LOG_1(level, modId, msg, d0) LOG_##level##_1(modId, msg, d0) +#define EXT_LOG_2(level, modId, msg, d0, d1) LOG_##level##_2(modId, msg, d0, d1) +#define EXT_LOG_3(level, modId, msg, d0, d1, d2) LOG_##level##_3(modId, msg, d0, d1, d2) +#define EXT_LOG_BUF(level, modId, msg, logBuf, logBufLen) LOG_##level##_BUF(modId, msg, logBuf, logBufLen) + +#ifdef MAKE_PRIM_XML_PROCESS_IN + +#define LOG_FATAL_0(modId, msg) \ + { \ + _PRIM_ST_, _PRIM_PRI_ = 0, _PRIM_MSG_ = msg, _PRIM_LINE_ = __LINE__, \ + _PRIM_FILE_ID_ = __FILE_IDX__, _PRIM_MOD_ID_ = modId, _PRIM_END_ \ + } +#define LOG_FATAL_1(modId, msg, d0) LOG_FATAL_0(modId, msg) +#define LOG_FATAL_2(modId, msg, d0, d1) LOG_FATAL_0(modId, msg) +#define LOG_FATAL_3(modId, msg, d0, d1, d2) LOG_FATAL_0(modId, msg) +#define LOG_FATAL_BUF(modId, msg, logBuf, logBufLen) LOG_FATAL_0(modId, msg) +#define LOG_LAST_WORD_BUF(modId, msg, logBuf, logBufLen) LOG_FATAL_0(modId, msg) + + +#define LOG_ERR_0(modId, msg) \ + { \ + _PRIM_ST_, _PRIM_PRI_ = 1, _PRIM_MSG_ = msg, _PRIM_LINE_ = __LINE__, \ + _PRIM_FILE_ID_ = __FILE_IDX__, _PRIM_MOD_ID_ = modId, _PRIM_END_ \ + } +#define LOG_ERR_1(modId, msg, d0) LOG_ERR_0(modId, msg) +#define LOG_ERR_2(modId, msg, d0, d1) LOG_ERR_0(modId, msg) +#define LOG_ERR_3(modId, msg, d0, d1, d2) LOG_ERR_0(modId, msg) +#define LOG_ERR_BUF(modId, msg, logBuf, logBufLen) LOG_ERR_0(modId, msg) + +#define LOG_WARN_0(modId, msg) \ + { \ + _PRIM_ST_, _PRIM_PRI_ = 2, _PRIM_MSG_ = msg, _PRIM_LINE_ = __LINE__, \ + _PRIM_FILE_ID_ = __FILE_IDX__, _PRIM_MOD_ID_ = modId, _PRIM_END_ \ + } +#define LOG_WARN_1(modId, msg, d0) LOG_WARN_0(modId, msg) +#define LOG_WARN_2(modId, msg, d0, d1) LOG_WARN_0(modId, msg) +#define LOG_WARN_3(modId, msg, d0, d1, d2) LOG_WARN_0(modId, msg) +#define LOG_WARN_BUF(modId, msg, logBuf, logBufLen) LOG_WARN_0(modId, msg) + +#define LOG_INFO_0(modId, msg) \ + { \ + _PRIM_ST_, _PRIM_PRI_ = 3, _PRIM_MSG_ = msg, _PRIM_LINE_ = __LINE__, \ + _PRIM_FILE_ID_ = __FILE_IDX__, _PRIM_MOD_ID_ = modId, _PRIM_END_ \ + } +#define LOG_INFO_1(modId, msg, d0) LOG_INFO_0(modId, msg) +#define LOG_INFO_2(modId, msg, d0, d1) LOG_INFO_0(modId, msg) +#define LOG_INFO_3(modId, msg, d0, d1, d2) LOG_INFO_0(modId, msg) +#define LOG_INFO_BUF(modId, msg, logBuf, logBufLen) LOG_INFO_0(modId, msg) + +#define LOG_DBG_0(modId, msg) \ + { \ + _PRIM_ST_, _PRIM_PRI_ = 4, _PRIM_MSG_ = msg, _PRIM_LINE_ = __LINE__, \ + _PRIM_FILE_ID_ = __FILE_IDX__, _PRIM_MOD_ID_ = modId, _PRIM_END_ \ + } +#define LOG_DBG_1(modId, msg, d0) LOG_DBG_0(modId, msg) +#define LOG_DBG_2(modId, msg, d0, d1) LOG_DBG_0(modId, msg) +#define LOG_DBG_3(modId, msg, d0, d1, d2) LOG_DBG_0(modId, msg) +#define LOG_DBG_BUF(modId, msg, logBuf, logBufLen) LOG_DBG_0(modId, msg) + +#else + +#define MAKE_XML_ID_UINT32(a, b) ((unsigned int)(((unsigned short)(a)) | ((unsigned int)((unsigned short)(b))) << 16)) + +#define LOG_0(level, modId, msg) \ + ExtDrvLogOut0(level, modId, MAKE_XML_ID_UINT32(__LINE__, THIS_FILE_ID)) +#define LOG_1(level, modId, msg, d0) \ + ExtDrvLogOut1(level, modId, MAKE_XML_ID_UINT32(__LINE__, THIS_FILE_ID), d0) +#define LOG_2(level, modId, msg, d0, d1) \ + ExtDrvLogOut2(level, modId, MAKE_XML_ID_UINT32(__LINE__, THIS_FILE_ID), d0, d1) +#define LOG_3(level, modId, msg, d0, d1, d2) \ + ExtDrvLogOut3(level, modId, MAKE_XML_ID_UINT32(__LINE__, THIS_FILE_ID), d0, d1, d2) + +#if CFG_DFX_MINILOG_SUPPORT +#define LOG_FATAL_0(modId, msg) \ + LOG_0(EXT_LOG_LEVEL_FATAL, modId, msg) +#define LOG_FATAL_1(modId, msg, d0) \ + LOG_1(EXT_LOG_LEVEL_FATAL, modId, msg, d0) +#define LOG_FATAL_2(modId, msg, d0, d1) \ + LOG_2(EXT_LOG_LEVEL_FATAL, modId, msg, d0, d1) +#define LOG_FATAL_3(modId, msg, d0, d1, d2) \ + LOG_3(EXT_LOG_LEVEL_FATAL, modId, msg, d0, d1, d2) +#define LOG_ERR_0(modId, msg) \ + LOG_0(EXT_LOG_LEVEL_ERROR, modId, msg) +#define LOG_ERR_1(modId, msg, d0) \ + LOG_1(EXT_LOG_LEVEL_ERROR, modId, msg, d0) +#define LOG_ERR_2(modId, msg, d0, d1) \ + LOG_2(EXT_LOG_LEVEL_ERROR, modId, msg, d0, d1) +#define LOG_ERR_3(modId, msg, d0, d1, d2) \ + LOG_3(EXT_LOG_LEVEL_ERROR, modId, msg, d0, d1, d2) +#define LOG_WARN_0(modId, msg) \ + LOG_0(EXT_LOG_LEVEL_WARNING, modId, msg) +#define LOG_WARN_1(modId, msg, d0) \ + LOG_1(EXT_LOG_LEVEL_WARNING, modId, msg, d0) +#define LOG_WARN_2(modId, msg, d0, d1) \ + LOG_2(EXT_LOG_LEVEL_WARNING, modId, msg, d0, d1) +#define LOG_WARN_3(modId, msg, d0, d1, d2) \ + LOG_3(EXT_LOG_LEVEL_WARNING, modId, msg, d0, d1, d2) +#define LOG_INFO_0(modId, msg) \ + LOG_0(EXT_LOG_LEVEL_INFO, modId, msg) +#define LOG_INFO_1(modId, msg, d0) \ + LOG_1(EXT_LOG_LEVEL_INFO, modId, msg, d0) +#define LOG_INFO_2(modId, msg, d0, d1) \ + LOG_2(EXT_LOG_LEVEL_INFO, modId, msg, d0, d1) +#define LOG_INFO_3(modId, msg, d0, d1, d2) \ + LOG_3(EXT_LOG_LEVEL_INFO, modId, msg, d0, d1, d2) +#define LOG_DBG_0(modId, msg) \ + LOG_0(EXT_LOG_LEVEL_DBG, modId, msg) +#define LOG_DBG_1(modId, msg, d0) \ + LOG_1(EXT_LOG_LEVEL_DBG, modId, msg, d0) +#define LOG_DBG_2(modId, msg, d0, d1) \ + LOG_2(EXT_LOG_LEVEL_DBG, modId, msg, d0, d1) +#define LOG_DBG_3(modId, msg, d0, d1, d2) \ + LOG_3(EXT_LOG_LEVEL_DBG, modId, msg, d0, d1, d2) +#else +#define LOG_FATAL_0(modId, fmt...) ExtDrvLogOutFmt(EXT_LOG_LEVEL_FATAL, modId, fmt) +#define LOG_FATAL_1(modId, fmt...) LOG_FATAL_0(modId, fmt) +#define LOG_FATAL_2(modId, fmt...) LOG_FATAL_0(modId, fmt) +#define LOG_FATAL_3(modId, fmt...) LOG_FATAL_0(modId, fmt) +#define LOG_ERR_0(modId, fmt...) ExtDrvLogOutFmt(EXT_LOG_LEVEL_ERROR, modId, fmt) +#define LOG_ERR_1(modId, fmt...) LOG_ERR_0(modId, fmt) +#define LOG_ERR_2(modId, fmt...) LOG_ERR_0(modId, fmt) +#define LOG_ERR_3(modId, fmt...) LOG_ERR_0(modId, fmt) +#define LOG_WARN_0(modId, fmt...) ExtDrvLogOutFmt(EXT_LOG_LEVEL_WARNING, modId, fmt) +#define LOG_WARN_1(modId, fmt...) LOG_WARN_0(modId, fmt) +#define LOG_WARN_2(modId, fmt...) LOG_WARN_0(modId, fmt) +#define LOG_WARN_3(modId, fmt...) LOG_WARN_0(modId, fmt) +#define LOG_INFO_0(modId, fmt...) ExtDrvLogOutFmt(EXT_LOG_LEVEL_INFO, modId, fmt) +#define LOG_INFO_1(modId, fmt...) LOG_INFO_0(modId, fmt) +#define LOG_INFO_2(modId, fmt...) LOG_INFO_0(modId, fmt) +#define LOG_INFO_3(modId, fmt...) LOG_INFO_0(modId, fmt) +#define LOG_DBG_0(modId, fmt...) ExtDrvLogOutFmt(EXT_LOG_LEVEL_DBG, modId, fmt) +#define LOG_DBG_1(modId, fmt...) LOG_DBG_0(modId, fmt) +#define LOG_DBG_2(modId, fmt...) LOG_DBG_0(modId, fmt) +#define LOG_DBG_3(modId, fmt...) LOG_DBG_0(modId, fmt) +#endif + +#define LOG_BUF(level, modId, msg, logBuf, logBufLen) \ + ExtDrvLogOutBuf(level, modId, MAKE_XML_ID_UINT32(__LINE__, THIS_FILE_ID), logBuf, logBufLen) + + +#define LOG_FATAL_BUF(modId, msg, logBuf, logBufLen) \ + LOG_BUF(EXT_LOG_LEVEL_FATAL, modId, msg, logBuf, logBufLen) +#define LOG_ERR_BUF(modId, msg, logBuf, logBufLen) \ + LOG_BUF(EXT_LOG_LEVEL_ERROR, modId, msg, logBuf, logBufLen) +#define LOG_WARN_BUF(modId, msg, logBuf, logBufLen) \ + LOG_BUF(EXT_LOG_LEVEL_WARNING, modId, msg, logBuf, logBufLen) +#define LOG_INFO_BUF(modId, msg, logBuf, logBufLen) \ + LOG_BUF(EXT_LOG_LEVEL_INFO, modId, msg, logBuf, logBufLen) +#define LOG_DBG_BUF(modId, msg, logBuf, logBufLen) \ + LOG_BUF(EXT_LOG_LEVEL_DBG, modId, msg, logBuf, logBufLen) + +#endif + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __EXT_DEBUG_H__ */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/file_id_defs.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/file_id_defs.h new file mode 100644 index 00000000..b1005a51 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/file_id_defs.h @@ -0,0 +1,63 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file file_id_defs.h + * @author MCU Driver Team + * @brief file id module driver + * @details The header file contains the following declaration: + * +Definition of miniaturized log event IDs + */ +#ifndef FILE_ID_DEFS_H +#define FILE_ID_DEFS_H + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup FILE_ID_DEFS_Def FILE_ID_DEFS_Def + * @brief Define source files and ID. + * @{ + */ + +typedef enum { + FILE_ID_LOG_C = 2001, /* this is a test sample */ +} file_id_enum; + +#ifdef __cplusplus +#if __cplusplus + } +#endif +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* FILE_ID_DEFS_H */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/log.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/log.h new file mode 100644 index 00000000..70653a31 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/log.h @@ -0,0 +1,146 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file log.h + * @author MCU Driver Team + * @brief log module driver + * @details The header file contains the following declaration: + * + Definition of log level settings for miniaturization. + * + Output of miniaturized logs based on different conditions. + */ +#ifndef LOG_H +#define LOG_H + +#include "ext_log.h" +#include "module.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C"{ +#endif +#endif /* __cplusplus */ + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup LOG_Def LOG_Def + * @brief Printing miniaturized logs. + * @{ + */ + +/** + * @brief Set Log Level. + * @attention None + * + * @param id [IN] ID of the module whose log level is to be set, which is defined by ExtModule. + * @param logLevel [IN] Log level, which is defined by ExtLogLevel. + * @retval int Whether the setting is successful + */ +int ExtSetLogLevel(enum ExtModule id, enum ExtLogLevel logLevel); + +/** + * @brief Used to report the content of a specified buffer to the message interface of the PC tool. + * @attention None + * + * @param logLevel [IN] Log level, which is defined by ExtLogLevel. + * @param modId [IN] Module ID, which is planned in advance based on the service scenario. + * @param msg [IN] The value is a character string constant and does not support carriage returns. + * The current version does not support parameter formatting. Only the character string is displayed. + * @param log_buf[IN] Log buffer + * @param log_buf_len[IN] Length of the log buffer, in bytes + * + * @retval None + */ +#define ExtLogBuf(logLevel, modId, msg, logBuf, logBufLen) EXT_LOG_BUF(logLevel, modId, msg, logBuf, logBufLen) + +/** + * @brief extLog0,Output logs without variables + * @attention None + * + * @param logLevel [IN] Log level, which is defined by ExtLogLevel + * @param modId [IN] Module ID, which is planned in advance based on the service scenario. + * @param msg [IN] The value is a character string constant and does not support carriage returns. + * The current version does not support parameter formatting. Only the character string is displayed. + * + * @retval None + */ +#define ExtLog0(logLevel, modId, msg) EXT_LOG_0(logLevel, modId, msg) + +/** + * @brief Logs with one int value are output + * @attention None + * + * @param logLevel [IN] Log level, which is defined by ExtLogLevel + * @param modId [IN] Module ID, which is planned in advance based on the service scenario. + * @param msg [IN] The value is a character string constant and does not support carriage returns. + * The current version does not support parameter formatting. Only the character string is displayed. + * @param d0 [IN] Variable of the unsigned int type + * + * @retval None + */ +#define ExtLog1(logLevel, modId, msg, d0) EXT_LOG_1(logLevel, modId, msg, d0) + +/** + * @brief Logs with two int values are output. + * @attention None + * + * @param logLevel [IN] Log level, which is defined by ExtLogLevel + * @param modId [IN] Module ID, which is planned in advance based on the service scenario. + * @param msg [IN] The value is a character string constant and does not support carriage returns. + * The current version does not support parameter formatting. Only the character string is displayed. + * @param d0 [IN] Variable of the unsigned int type + * @param d1 [IN] Variable of the unsigned int type + * + * @retval None + */ +#define ExtLog2(logLevel, modId, msg, d0, d1) EXT_LOG_2(logLevel, modId, msg, d0, d1) + +/** + * @brief Logs with three int values are output + * @attention None + * + * @param logLevel [IN] Log level, which is defined by ExtLogLevel + * @param modId [IN] Module ID, which is planned in advance based on the service scenario. + * @param msg [IN] The value is a character string constant and does not support carriage returns. + * The current version does not support parameter formatting. Only the character string is displayed. + * @param d0 [IN] Variable of the unsigned int type + * @param d1 [IN] Variable of the unsigned int type + * @param d2 [IN] Variable of the unsigned int type + * + * @retval None + */ +#define ExtLog3(logLevel, modId, msg, d0, d1, d2) EXT_LOG_3(logLevel, modId, msg, d0, d1, d2) + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __EXT_DEBUG_H__ */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/module.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/module.h new file mode 100644 index 00000000..ca565e1f --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/module.h @@ -0,0 +1,96 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mpdule.h + * @author MCU Driver Team + * @brief Definition of the Miniaturized Log Module + * @details The header file contains the following declaration: + * + Definition of the ID of the miniaturized log module + */ +#ifndef MODULE_H +#define MODULE_H + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* __cplusplus */ + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup MODULE_Def MODULE_Def + * @brief define the device model. + * @{ + */ + +/* * Module ID flags */ +enum ExtModule { + EXT_MODULE_APP_MAIN, + EXT_MODULE_APP_CONSOLE, + EXT_MODULE_APP_CHIP, + EXT_MODULE_DRV_BASE, + EXT_MODULE_DRV_CHIPS, + EXT_MODULE_DRV_CRG, + EXT_MODULE_DRV_GPIO, + EXT_MODULE_DRV_I2C, + EXT_MODULE_DRV_IRQ, + EXT_MODULE_DRV_PINCTRL, + EXT_MODULE_DRV_TIMER, + EXT_MODULE_DRV_UART, + EXT_MODULE_DFX, + EXT_MODULE_BUTT +}; + +#define MODULE_ID_MASK 0xFF000000 +#define FEATURE_ID_MASK 0x00FF0000 +#define PARAM_USE_ID_MASK 0x0000FFFF + +#define MODULE_ID_OFFSET 0x18 +#define FEATURE_ID_OFFSET 0x10 +#define PARAM_USE_ID_OFFSET 0x8 + +#define SCENE_UINT_MAX_ID 0xFF + +#define SCENE_END_LABEL 0xABCDABCD + +#define STATE_CODE_MODULE_MASK 0x10 +#define STATE_CODE_MASK 0xFFFF0000 + +#define STATE_CODE(moduleId, stateCode) (moduleId << STATE_CODE_MODULE_MASK | (stateCode & STATE_CODE_MASK)) +#define STATE_CODE_ERR_CHECK(ret) ((ret & STATE_CODE_MASK) > EXT_RIGHT_UNKNOWN) +#define STATE_CODE_RIGHT_CHECK(ret) ((ret & STATE_CODE_MASK) <= EXT_RIGHT_UNKNOWN) + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __EXT__MODULE__ */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/type.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/type.h new file mode 100644 index 00000000..2e4fdbfd --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/inc/type.h @@ -0,0 +1,73 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file type.h + * @author MCU Driver Team + * @brief type module driver + * @details The header file contains the following declaration: + * + Basic Data Type Definition + */ +#ifndef TYPE_H +#define TYPE_H + +#include "errno.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* __cplusplus */ + +/** + * @addtogroup DEBUG_Log + * @brief DEBUG external module. + * @{ + */ + + /** + * @defgroup TYPE_Def TYPE_Def + * @brief define the return value type. + * @{ + */ + +/** + * @brief Basic Data Type Definition + */ +#ifndef NULL +#define NULL 0L +#endif +#define NULL_PTR ((void*)0) + +#define EXT_FALSE 0 +#define EXT_TRUE 1 + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __EXT_TYPE_H__ */ + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/app_command.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/app_command.c new file mode 100644 index 00000000..a512fcae --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/app_command.c @@ -0,0 +1,525 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file app_command.c + * @author MCU Driver Team + * @brief command module driver + * @details The header file contains the following declaration: + * + Receive and parse the command input through the serial port. + * + implementation of serial port output function + * + Key Character Detection + */ +#include +#include +#include "common.h" +#include "command.h" +#include "console.h" +#include "cmd_common.h" +#include "cmd.h" +#include "securec.h" + +typedef struct { + char ch; + char c; +} DirMapRes; + +/** + * @brief Command Input Keyword Initialization + */ +struct CmdInput { + char buf[CMD_BUF_MAX]; + size_t cursor; +}; + +/** + * @brief Initialize the command storage address. + */ +struct CmdRecord { + char cmdLogList[CMD_NUM_MAX][CMD_BUF_MAX]; + signed char max; + signed char addIdx; + signed char cur; +}; + +/** + * @brief Initialize the command sending variable. + */ +struct CmdCtx { + char cmdBuf[CMD_BUF_MAX]; + const char *argv[ARGS_NUM_MAX]; + unsigned char dirKeyLen; + char uartRxch; /* stores the characters */ + + struct CmdInput inputCmd; + struct CmdRecord cmdLog; +}; + +static struct CmdCtx g_cmdCtx = { 0 }; +static struct CmdCtx *AppCmdGetCtx(void) +{ + /* Initialize the structure value */ + return &g_cmdCtx; +} + +/** + * @brief Get Previous Command + * @param cmdLog: Commands from user + * @retval : Parse the subscript or error return value of a character string. + */ +static char *GetPreCmd(struct CmdRecord *cmdLog) +{ + if (cmdLog->max == 0) { /* Failed to initialize the maximum value */ + return NULL; + } + + if (cmdLog->max < CMD_NUM_MAX - 1) { + if (cmdLog->cur == 0) { + return NULL; + } + return cmdLog->cmdLogList[--cmdLog->cur]; + } + + if (cmdLog->cur == 0) { + if (cmdLog->addIdx == cmdLog->max) { + return NULL; + } + cmdLog->cur = cmdLog->max; + return cmdLog->cmdLogList[cmdLog->cur]; + } + + if (cmdLog->addIdx == cmdLog->cur - 1) { + return NULL; + } + return cmdLog->cmdLogList[--cmdLog->cur]; /* the pointer address is returned */ +} + +/** + * @brief Read the next command + * @param cmdLog: Commands from user + * @retval : Parse the subscript or error return value of a character string. + */ +static char *GetNextCmd(struct CmdRecord *cmdLog) +{ + if (cmdLog == NULL || cmdLog->max == 0) { /* Failed to initialize the maximum value */ + return NULL; + } + + if (cmdLog->max < CMD_NUM_MAX - 1) { + if (cmdLog->cur == cmdLog->max) { + return NULL; + } + return cmdLog->cmdLogList[++cmdLog->cur]; + } + + if (cmdLog->cur == cmdLog->max) { + if (cmdLog->addIdx == 0) { + return NULL; + } + cmdLog->cur = 0; + return cmdLog->cmdLogList[cmdLog->cur]; + } + + if (cmdLog->addIdx == cmdLog->cur + 1) { + return NULL; + } + return cmdLog->cmdLogList[++cmdLog->cur]; /* the pointer address is returned */ +} + +/** + * @brief Delete End Identifier + * @param inputcmd : Entered character string information. + * @retval None. + */ +static void CmdDeleteTailChar(struct CmdInput *inputCmd) +{ + if (inputCmd == NULL || inputCmd->cursor == 0) { + return; + } + /* Add a closing marker to a string */ + ConsolePutc(CTL_BACKSPACE); + ConsolePutc(SPACE_KEY); + ConsolePutc(CTL_BACKSPACE); + inputCmd->buf[--(inputCmd->cursor)] = '\0'; +} + +/** + * @brief Add a terminator at the end of a string + * @param inputcmd : Entered character string information. + * @retval None. + */ +static void CmdAddTailChar(struct CmdInput *inputCmd, char ch) +{ + if (inputCmd->cursor >= CMD_BUF_MAX - 1) { + return; + } + inputCmd->buf[(inputCmd->cursor)++] = ch; + /* Remove '\n' characters and add '\r\n' */ + ConsolePutc(ch); +} + +/** + * @brief Ignore the effects of key characters + * @param ch : Characters contained in the command + * @retval Indicates whether the implementation is successful. + */ +static unsigned char IgnoreCmdKey(char ch) +{ + /* end character and type character for the crt key */ + char ignoreKeys[] = {'\0', CTL_CH('a'), CTL_CH('b'), CTL_CH('e'), CTL_CH('f'), CTL_CH('x'), + CTL_CH('o'), CTL_CH('u')}; + + for (unsigned char i = 0; i < sizeof(ignoreKeys); i++) { + if (ch == ignoreKeys[i]) { + return EXT_TRUE; + } + } + return EXT_FALSE; +} + +/** + * @brief deleted Command Keys + * @param ch : Characters contained in the command + * @retval Indicates whether the implementation is successful. + */ +static unsigned char DeleteCmdKey(char ch) +{ + /* Backspace key delete key and other special key input */ + char deleteKeys[] = {DEL, DEL7, CTL_CH('h'), CTL_CH('d'), CTL_CH('k')}; + + for (unsigned char i = 0; i < sizeof(deleteKeys); i++) { + if (ch == deleteKeys[i]) { + return EXT_TRUE; + } + } + return EXT_FALSE; +} + +/** + * @brief Output Log Commands + * @param ch : Characters contained in the command + * @param cmdlog : Command log information + * @param input : Entering command information + * @retval None + */ +static void OutputLogCmd(struct CmdCtx *cmdCtx) +{ + char *cmd = NULL; + + cmd = (cmdCtx->uartRxch == CTL_CH('p')) ? GetPreCmd(&(cmdCtx->cmdLog)) : GetNextCmd(&(cmdCtx->cmdLog)); + /* If the value is empty, direct returned */ + if (cmd == NULL) { + return; + } + + /* Clears the array of characters */ + while (cmdCtx->inputCmd.cursor) { + CmdDeleteTailChar(&(cmdCtx->inputCmd)); + } + if (strncpy_s(cmdCtx->inputCmd.buf, CMD_BUF_MAX, cmd, strlen(cmd)) != EXT_SUCCESS) { + APP_CMD_ERR_PRINT("backup logcmd err\n"); + return; + } + /* Update pointer coordinates */ + cmdCtx->inputCmd.cursor = strlen(cmdCtx->inputCmd.buf); + EXT_PRINT("%s", cmdCtx->inputCmd.buf); +} + +/** + * @brief Output log commands + * @param cmd : Command string + * @param cmdlog : Command log information + * @retval Indicates whether the implementation is successful + */ +static int RecordCmd(const char *cmd, struct CmdRecord *cmdLog) +{ + /* not record uart switch cmd */ + if (strncmp(cmd, UART_SWITCH_CMD, strlen(UART_SWITCH_CMD)) == 0) { + return EXT_SUCCESS; + } + + /* clear buf and copy cmd to buf */ + memset_s(cmdLog->cmdLogList[cmdLog->addIdx], CMD_BUF_MAX, 0, CMD_BUF_MAX); + if (strncpy_s(cmdLog->cmdLogList[cmdLog->addIdx], CMD_BUF_MAX, cmd, strlen(cmd)) != EXT_SUCCESS) { + return EXT_FAILURE; + } + cmdLog->addIdx = (cmdLog->addIdx + 1) % CMD_NUM_MAX; + cmdLog->max = (cmdLog->addIdx > cmdLog->max) ? cmdLog->addIdx : cmdLog->max; + cmdLog->cur = cmdLog->addIdx; + return EXT_SUCCESS; +} + +/** + * @brief Clear the command and initialize the address + * @param inputCmd : Entering command information + * @retval None + */ +static void CleanInputCmd(struct CmdCtx *cmdCtx) +{ + /* the address pointer points to the start address */ + cmdCtx->inputCmd.buf[0] = '\0'; + cmdCtx->inputCmd.cursor = 0; + ConsolePuts("\n$ "); +} + +/** + * @brief Parse the arrow keys in the command. + * @param ch : Characters entered + * @param dirKeyLen : Arrow key flag + * @retval end character or non-direction character entered + */ +static char CmdDirectionKey(char ch, unsigned char *dirKeyLen) +{ + char c = '\0'; + DirMapRes dirMap[5] = { + /* Dir chd have 5 */ + {'D', CTL_CH('b')}, /* left key, convert to ctrl + b */ + {'C', CTL_CH('f')}, /* right key, convert to ctrl + c */ + {'H', CTL_CH('a')}, /* Home key, convert to ctrl + a */ + {'A', CTL_CH('p')}, /* up arrow, convert to ctrl + p */ + {'B', CTL_CH('n')} /* down arrow, convert to ctrl + n */ + }; + + if (*dirKeyLen == 0) { + if (ch == DIR_KEY_HEAD) { + *dirKeyLen = 1; + return c; + } + return ch; + } + + if (*dirKeyLen == 1) { + *dirKeyLen = (ch == '[') ? 2 : 0; /* 2 is directionKeyLen */ + return c; + } + + /* handle the third char sended by direction key */ + for (unsigned char i = 0; i < sizeof(dirMap) / sizeof(DirMapRes); i++) { + if (ch == dirMap[i].ch) { + c = dirMap[i].c; + break; + } + } + *dirKeyLen = 0; + return c; +} + +/** + * @brief tabkey alignment implementation + * @param res : Entered string + * @param inputCmd : Entering command information + * @retval None + */ +static void CompletesTabKey(const char *res, struct CmdInput *inputCmd) +{ + if (res == NULL || inputCmd == NULL) { + APP_CMD_ERR_PRINT("param err\n"); + return; + } + /* Obtains the array length */ + size_t len = strlen(res); + + while (len > inputCmd->cursor && inputCmd->cursor < CMD_BUF_MAX) { + /* Output Characters */ + ConsolePutc(res[inputCmd->cursor]); + + inputCmd->buf[inputCmd->cursor] = res[inputCmd->cursor]; + inputCmd->cursor++; + } +} + +/** + * @brief tabkey alignment implementation + * @param inputCmd : Entering command information + * @retval None + */ +static void CmdTabKey(struct CmdCtx *cmdCtx) +{ + const char* res[MATCH_CMD_BUF_CNT] = { NULL }; + /* Numeric element initialization */ + unsigned char findCnt = 0; + unsigned char cycle = 0; + unsigned int tailId = 0; + unsigned char searchFinish = EXT_TRUE; + + cmdCtx->inputCmd.buf[cmdCtx->inputCmd.cursor] = '\0'; + while (EXT_TRUE) { + /* The printing is performed cyclically until the tabkey detection is complete */ + searchFinish = ExtCmdFindMatchCmd(cmdCtx->inputCmd.buf, res, MATCH_CMD_BUF_CNT, &findCnt, &tailId); + cycle++; + if (searchFinish && cycle ==1) { + if (findCnt) { + CompletesTabKey(res[0], &(cmdCtx->inputCmd)); + } + break; + } + /* Print newline key after end */ + if (cycle == 1) { + EXT_PRINT("\n"); + } + /* cyclic print characters */ + for (unsigned char i = 0; i < findCnt; i++) { + EXT_PRINT("%s ", res[i]); + } + EXT_PRINT("\n"); + if (searchFinish) { + EXT_PRINT("$"); + EXT_PRINT("%s", cmdCtx->inputCmd.buf); + break; + } + /* Clear the count value */ + findCnt = 0; + } +} + +/** + * @brief tabkey alignment implementation + * @param inputCmd : Entering command information + * @param cmdBuf ；Command storage array + * @param cmdLog : Address for storing printed log information + * @retval None + */ +static void CmdEnterKey(struct CmdCtx *cmdCtx) +{ + if (cmdCtx->inputCmd.cursor == 0) { + ConsolePuts("\n$ "); + return; + } + + if (memcpy_s(cmdCtx->cmdBuf, CMD_BUF_MAX, cmdCtx->inputCmd.buf, cmdCtx->inputCmd.cursor) != EXT_SUCCESS) { + ConsolePuts("\n$ "); /* Add the end character */ + return; + } + cmdCtx->cmdBuf[cmdCtx->inputCmd.cursor] = '\0'; + + if (RecordCmd(cmdCtx->cmdBuf, &(cmdCtx->cmdLog)) != EXT_SUCCESS) { + ConsolePuts("\n$ "); /* Add the end character */ + return; + } + CleanInputCmd(cmdCtx); +} + +/** + * @brief Setting the log level + * @param None + * @retval Returns the value of the character's ASCII code + */ +static int CmdStrSetLevel(void) +{ + int ret; + for (unsigned char i = 0; i < EXT_MODULE_BUTT; i++) { + /* Setting the log level cyclically */ + ret = ExtDrvLogSetLogLevel(i, EXT_LOG_LEVEL_FATAL); + if (ret != EXT_SUCCESS) { + break; + } + } + return ret; +} + +typedef struct { + unsigned int ulEventBit; + void (*Func)(struct CmdCtx *cmdCtx); +} EventDoWithTable_t; +static const EventDoWithTable_t astDoWithTable[] = { + { CTL_CH_C, CleanInputCmd}, + { TAB_KEY, CmdTabKey}, /* detrct the tab key */ + { ENTER_KEY1, CmdEnterKey}, /* detected '\r' */ + { ENTER_KEY2, CmdEnterKey}, /* detected '\n' */ + { CTL_CH_P, OutputLogCmd}, + { CTL_CH_N, OutputLogCmd} +}; +/** + * @brief Parse characters one by one + * @param cmdCtx : string information + * @retval Returns the value of the character's ASCII code + */ +static int GetCmdStr(struct CmdCtx *cmdCtx) +{ + int ret = EXT_SUCCESS; + char c; + /* Query the status of the serial port register */ + while ((cmdCtx->uartRxch = ConsoleGetc()) != 0) { + if (cmdCtx->inputCmd.cursor >= CMD_BUF_MAX) { + APP_CMD_ERR_PRINT("\ncmd overflow\n"); + /* Clear Character Cache */ + CleanInputCmd(cmdCtx); + return EXT_FAILURE; + } + /* Get cmd direct key word */ + c = CmdDirectionKey(cmdCtx->uartRxch, &cmdCtx->dirKeyLen); + if (IgnoreCmdKey(c)) { + return ret; + } + /* Delete cmd key word */ + if (DeleteCmdKey(c)) { + CmdDeleteTailChar(&cmdCtx->inputCmd); + return ret; + } + /* Invoke the function drive table */ + for (unsigned int i = 0 ; i < (unsigned int)sizeof(astDoWithTable)/sizeof(astDoWithTable[0]); i ++) { + if ((unsigned int)c == astDoWithTable[i].ulEventBit) { + astDoWithTable[i].Func(cmdCtx); + return ret; + } + } + /* Setting the log level */ + if (c == CTL_CH('l')) { + ret = CmdStrSetLevel(); + return ret; + } + /* Add key word to tail */ + CmdAddTailChar(&cmdCtx->inputCmd, c); + } + return ret; +} + +/** + * @brief encapsulation of Serial Port Transmission + * @param None + * @retval None + */ +void ExtAppCmdProcess(void) +{ + int ret; + unsigned int argsNum; + struct cmdRegisterTable *cmd; + /* Initialize the structure */ + struct CmdCtx *cmdCtx = AppCmdGetCtx(); + ret = GetCmdStr(cmdCtx); + if ((ret != EXT_SUCCESS) || (cmdCtx->cmdBuf[0] == '\0')) { + return; + } + argsNum = CmdParserParam(cmdCtx->cmdBuf, cmdCtx->argv); + if (argsNum == 0) { + /* Clear the memory in the structure */ + (void)memset_s(&cmdCtx->inputCmd, sizeof(cmdCtx->inputCmd), 0, sizeof(cmdCtx->inputCmd)); + (void)memset_s(&cmdCtx->cmdBuf, sizeof(cmdCtx->cmdBuf), 0, sizeof(cmdCtx->cmdBuf)); + return; + } + cmd = ExtCmdFindCmd(cmdCtx->argv[0]); + if (cmd == NULL || cmd->func == NULL) { + /* Initialization Structure */ + (void)memset_s(&cmdCtx->inputCmd, sizeof(cmdCtx->inputCmd), 0, sizeof(cmdCtx->inputCmd)); + (void)memset_s(&cmdCtx->cmdBuf, sizeof(cmdCtx->cmdBuf), 0, sizeof(cmdCtx->cmdBuf)); + return; + } + cmd->func(argsNum, cmdCtx->argv); + EXT_PRINT("\n$ "); + /* Initialization Structure */ + (void)memset_s(&cmdCtx->inputCmd, sizeof(cmdCtx->inputCmd), 0, sizeof(cmdCtx->inputCmd)); + (void)memset_s(&cmdCtx->cmdBuf, sizeof(cmdCtx->cmdBuf), 0, sizeof(cmdCtx->cmdBuf)); +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/cmd.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/cmd.c new file mode 100644 index 00000000..06a08d9c --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/cmd.c @@ -0,0 +1,56 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cmd.c + * @author MCU Driver Team + * @brief cmd module driver + * @details The header file contains the following declaration: + * + basic register information assignment + */ +#include "cmd.h" +#include "console.h" +#include "ext_log.h" +struct cmdRegisterTable g_cmdRegister[CMD_REGESTER_MAX_NUM] = {0}; + +int g_cmdIndex = 0; + +/** + * @brief assign a value to the information in the RX register. + * @param None + * @retval the information in the RX register. + */ +struct cmdRegisterTable *GetRegisterAddr(void) +{ + return g_cmdRegister; +} + +/** + * @brief Registering a User-Defined Function + * @param cmdName : customize a name for the implemented function. + * @param func : pointer to the customized function. + * @retval None + */ +void ExtCmdRegister(char *cmdName, pfncmd func) +{ + if (g_cmdIndex >= CMD_REGESTER_MAX_NUM || g_cmdIndex < 0) { + EXT_PRINT("the number of registration commmamds has reached the maximum\n"); + return; + } + g_cmdRegister[g_cmdIndex].name = cmdName; /* enter the user-defined name */ + g_cmdRegister[g_cmdIndex].func = func; /* pointing a function pointer to a user-defined function */ + g_cmdIndex++; +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/cmd_common.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/cmd_common.c new file mode 100644 index 00000000..b20ef5e7 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/cmd_common.c @@ -0,0 +1,67 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file cmd_common.c + * @author MCU Driver Team + * @brief cmd module driver + * @details The header file contains the following declaration: + * + total invoking of entry parameter parsing + */ +#include "cmd_common.h" + +/** + * @brief invoking of entry parameter parsing + * @param cdmStr : single character from user + * @param argv[] : Character string directly entered through the serial port + * @retval pointer address of the string + */ +unsigned int CmdParserParam(char *cmdStr, const char *argv[]) +{ + unsigned int nargs = 0; + + while (nargs < ARGS_NUM_MAX) { + /* skip any white space */ + while ((*cmdStr == ' ') || (*cmdStr == '\t')) { + ++cmdStr; + } + + /* end of line, no more args */ + if (*cmdStr == '\0') { + argv[nargs] = NULL; + return (nargs); + } + + /* begin of argument string */ + argv[nargs++] = cmdStr; + + /* find end of string */ + while ((*cmdStr != '\0') && (*cmdStr != ' ') && (*cmdStr != '\t')) { + ++cmdStr; + } + + /* end of line, no more args */ + if (*cmdStr == '\0') { + argv[nargs] = NULL; + return (nargs); + } + + /* terminate current arg */ + *cmdStr++ = '\0'; + } + return nargs; +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/config.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/config.c new file mode 100644 index 00000000..2cdb30cd --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/config.c @@ -0,0 +1,143 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file config.c + * @author MCU Driver Team + * @brief config module driver + * @details The header file contains the following declaration: + * + Miniaturized logs are written based on addresses. + * + Abnormal event reporting + */ +#include +#include "config.h" +#include "common.h" +#include "console.h" +#include "type.h" +#include "string.h" +#include "securec.h" + +/** + * @brief read information by address + * @param add : register address of the information to be read + * @param value : storage array of read information + * @param len ： length of the information to be read + * @retval None. + */ +void ExtLoadRead(uintptr_t add, char *value, int len) +{ + /* Check whether the address is out of range */ + if (add > REGISTER_END || add < REGISTER_START) { + EXT_PRINT("The address is out of range"); + return; + } + /* check param vaild */ + if (value == NULL) { + EXT_PRINT("read data is null, please check value\n"); + return; + } + /* Read information cyclically */ + for (int i = 0; i < len; i++) { + *(value + i) = *(volatile char *)(add + i); + } +} + +/** + * @brief write information by address + * @param add : register address of the information to write + * @param value : storage array of write information + * @param len ： length of the information to write + * @retval None. + */ +void ExtLoadWrite(uintptr_t add, const char *value, int len) +{ + /* Check whether the address is out of range */ + if (add > REGISTER_END || add < REGISTER_START) { + EXT_PRINT("The address is out of range"); + return; + } + /* check param vaild */ + if (value == NULL) { + EXT_PRINT("write data is null, please check value\n"); + return; + } + /* Write information cyclically */ + for (int i = 0; i < len; i++) { + *(volatile char *)(add + i) = *(value + i); + } +} + +char g_dataItem[DATA_ITEM_NUM_MAX][DATA_ITEM_MAX_LEN]; + +/** + * @brief read information by config + * @param item : event that starts to read data + * @param value : storage array of read information + * @param len ： length of the information to be read + * @retval None. + */ +void ExtConfigRead(enum DataItem item, char *value, int len) +{ + /* Exceeded the maximum scenario value */ + if (item > DATA_ITEM_NUM_MAX) { + EXT_PRINT("The config has exceeded max vaule"); + return; + } + /* check param vaild */ + if (len >= DATA_ITEM_MAX_LEN) { + EXT_PRINT("The length of the read data exceeds 256\n"); + return; + } + if (value == NULL) { + EXT_PRINT("The read content is empty, read err"); + return; + } + /* Reads the data stored in the register */ + if (memcpy_s(value, len, &g_dataItem[item], len) != EXT_SUCCESS) { + EXT_PRINT("config read memcpy failed"); + } + return; +} + +/** + * @brief write information by config + * @param add : register address of the information to write + * @param value : storage array of write information + * @param len ： length of the information to write + * @retval None. + */ +void ExtConfigWrite(enum DataItem item, const char *value, int len) +{ + /* Exceeded the maximum scenario value */ + if (item > DATA_ITEM_NUM_MAX) { + EXT_PRINT("The config has exceeded max vaule"); + return; + } + /* check param vaild */ + if (len >= DATA_ITEM_MAX_LEN) { + EXT_PRINT("The length of the write data exceeds 256\n"); + return; + } + if (value == NULL) { + EXT_PRINT("The written content is empty, write err"); + return; + } + /* Writes data to a register for storage */ + if (memcpy_s(&g_dataItem[item], DATA_ITEM_MAX_LEN, value, len) != EXT_SUCCESS) { + EXT_PRINT("config write memcpy failed"); + } + return; +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/console.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/console.c new file mode 100644 index 00000000..2c31c248 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/console.c @@ -0,0 +1,442 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file console.c + * @author MCU Driver Team + * @brief console module driver + * @details The header file contains the following declaration: + * + GPIO configuration enums. + * + GPIO register structures. + * + GPIO DCL Functions. + * + Parameters check functions. + */ +#include "console.h" +#include "errno.h" +#include "ext_log.h" +#include "dfx_log.h" +#define UART_READ_TIME_MS 1000 + +#define VA_START(v, l) __builtin_va_start(v, l) +#define VA_ARG(v, l) __builtin_va_arg(v, l) +#define VA_END(v) __builtin_va_end(v) + +#define DECIMAL_BASE 10U /* Cardinality of decimal numbers */ +#define HALF_ADJUST_BOUNDARY 5U /* The boundary for rounding the floating number */ +#define MAX_DIV_TIMES 31U + +typedef __builtin_va_list va_list; + +/* defines the number of output numbers */ +typedef enum { + BINARY = 2U, + OCTAL = 8U, + DECIMAL = 10U, + HEXADECIMAL = 16U, +} NumBase; +UART_Handle g_console_uart; + +/** + * @brief query the status of a serial port reading register + * @param uartHandle: indicates the serial port information corresponding to the value assignment + * @param isEmpty: pointer to the array that stores status information + * @retval whether data is received + */ +static BASE_StatusType QueryUartRxStatus(UART_Handle *uartHandle, unsigned char *isEmpty) +{ + *isEmpty = uartHandle->baseAddress->UART_FR.BIT.rxfe; /* read register status address */ + return BASE_STATUS_OK; +} + +/** + * @brief Single Character Output + * @param c: single character to be output + * @retval None + */ +void ConsolePutc(const char c) +{ + unsigned int length = 1; + unsigned char p; + /* add newline characters for standby */ + p = (unsigned char)c; + if (c == '\n') { + p = '\r'; + HAL_UART_WriteBlocking(&g_console_uart, &p, length, UART_READ_TIME_MS); + p = '\n'; + } + HAL_UART_WriteBlocking(&g_console_uart, &p, length, UART_READ_TIME_MS); +} + +/** + * @brief output the entire string. + * @param str: string to be output. + * @retval None + */ +int ConsolePuts(const char *str) +{ + int cnt = 0; + /* decompose a string into a single character output */ + while (*str != '\0') { + ConsolePutc(*str); + str++; + cnt++; + } + return cnt; +} + +/** + * @brief Read a single character + * @param None + * @retval ASCII value of the read character + */ +int ConsoleGetc(void) +{ + unsigned char rxStr; + unsigned int length = 1; + int ret; + + /* reads a single character from the serial port */ + ret = HAL_UART_ReadBlocking(&g_console_uart, &rxStr, length, UART_READ_TIME_MS); + if (ret == EXT_SUCCESS) { + return (int)rxStr; + } else { + return -1; + } +} + +/** + * @brief reads the register reception status + * @param None + * @retval register Status + */ +int ConsoleGetQuery(void) +{ + unsigned char isEmpty; + + QueryUartRxStatus(&g_console_uart, &isEmpty); + return !(isEmpty); +} + +/** + * @brief reads the pointer coordinates of the register. + * @param base: pointer initial address value. + * @param exponent: number of times the pointer needs to be moved + * @retval pointer coordinate value + */ +static unsigned long DBG_Pow(unsigned int base, unsigned int exponent) +{ + unsigned long ret = 1; + while (exponent--) { + ret *= base; + } + return ret; /* ret = base ^ exponent */ +} + +/** + * @brief calculate the number of digits entered + * @param num: numbers to be calculated + * @param base: number of digits entered + * @retval number of digits of the calculated number + */ +static unsigned int DBG_CountDigits(int num, NumBase base) +{ + unsigned int cnt = 0; + if (base == 0) { + return 0; + } + /* Cyclic Conversion Count */ + while (num != 0) { + cnt++; + if (cnt > MAX_DIV_TIMES) { + break; + } + num /= base; + } + /* Returns the number of digits */ + return cnt; +} + +/** + * @brief Output unsigned digits + * @param num: numbers to be output + * @param base: number of digits entered + * @param digits: number of digits output + * @retval None + */ +static void DBG_PutUnsignedNum(unsigned int num, NumBase base, unsigned int digits) +{ + unsigned char ch; + while (digits != 0) { + ch = num / DBG_Pow(base, digits - 1); + num %= DBG_Pow(base, digits - 1); + if (base == DECIMAL) { + ConsolePutc(ch + '0'); /* characters that convert numbers to decimal numbers */ + } else if (base == HEXADECIMAL) { + if (ch < DECIMAL_BASE) { + ConsolePutc(ch + '0'); /* Character that converts a number to a hexadecimal number */ + } else { + ConsolePutc(ch - DECIMAL_BASE + 'A'); + } + } + digits--; + } +} + +/** + * @brief print Numbers + * @param intNum: numbers to be output + * @retval returns the number of digits of the output number + */ +static unsigned int DBG_PrintInt(int intNum) +{ + unsigned int cnt; + if (intNum == 0) { + ConsolePutc('0'); /* add '0' */ + return 1; + } + if (intNum < 0) { + ConsolePutc('-'); /* need to manually add a negative sign */ + intNum = -intNum; + } + /* Calculate the number of digits */ + cnt = DBG_CountDigits(intNum, DECIMAL); + DBG_PutUnsignedNum(intNum, DECIMAL, cnt); + return cnt; +} + +/** + * @brief print hexadecimal digits + * @param hexNum: numbers to be output + * @retval returns the number of digits of the output number + */ +static unsigned int DBG_PrintHex(unsigned int hexNum) +{ + unsigned int cnt; + if (hexNum == 0) { + ConsolePutc('0'); /* add '0' */ + return 1; + } + /* Calculate the number of hexadecimal digits */ + cnt = DBG_CountDigits(hexNum, HEXADECIMAL); + DBG_PutUnsignedNum(hexNum, HEXADECIMAL, cnt); + return cnt; +} + +/** + * @brief Print Single Precision Decimals + * @param fltNum: numbers to be output + * @param precision: number of decimal places to print + * @retval returns the number of digits of the output number + */ +static unsigned int DBG_PrintFlt(float fltNum, unsigned int precision) +{ + unsigned int cnt = 0; + unsigned int floatScale; + + if (fltNum < 0) { + ConsolePutc('-'); + cnt += 1; + fltNum = -fltNum; + } + int integerVal = (int)fltNum; + floatScale = DBG_Pow(10, (precision + 1)); /* 10: decimal */ + int floatVal = (long)(floatScale * (fltNum - integerVal)); + /* Half-adjust: round up or round down */ + if (floatVal % DECIMAL_BASE >= HALF_ADJUST_BOUNDARY) { + floatVal = floatVal / DECIMAL_BASE + 1; + } else { + floatVal = floatVal / DECIMAL_BASE; + } + cnt += DBG_PrintInt(integerVal); + ConsolePutc('.'); + cnt += 1; + /* Pad 0 in float part */ + unsigned int fltCnt = DBG_CountDigits(floatVal, DECIMAL); + if (precision > fltCnt) { + for (unsigned int i = 0; i < precision - fltCnt; i++) { + ConsolePutc('0'); /* add '0' */ + } + } + DBG_PutUnsignedNum(floatVal, DECIMAL, fltCnt); /* print unsigned number */ + cnt += precision; + return cnt; +} + +/** + * @brief Resolving Special Characters + * @param ch: single character to be parsed + * @param *paramList: elements that implement parsing + * @retval returns the number of digits of the output number + */ +static unsigned int ParseSpecifier(const char ch, va_list *paramList) +{ + /* Value Definition Initialization */ + unsigned int cnt = 0; + unsigned int tmpCnt; + char chVal = 0; + const char *strVal = 0; + int intVal = 0; + unsigned int unsignedVal = 0; + unsigned int hexVal = 0; + float fltVal = 0; + switch (ch) { + case 'c': + chVal = VA_ARG(*paramList, int); /* Use type int because of byte alignment */ + ConsolePutc(chVal); + cnt += 1; + break; + case 's': + /* received 's', print the string */ + strVal = VA_ARG(*paramList, const char *); + cnt += ConsolePuts(strVal); + break; + case 'd': + /* Received character'd', print initialization */ + intVal = VA_ARG(*paramList, int); + cnt += DBG_PrintInt(intVal); + break; + case 'u': + unsignedVal = VA_ARG(*paramList, unsigned int); + tmpCnt = DBG_CountDigits(unsignedVal, DECIMAL); + DBG_PutUnsignedNum(unsignedVal, DECIMAL, tmpCnt); + cnt += tmpCnt; + break; + case 'x': + case 'X': + case 'p': + /* Received'p' and returned hexadecimal number */ + hexVal = VA_ARG(*paramList, unsigned int); + cnt += DBG_PrintHex(hexVal); + break; + case 'f': + fltVal = VA_ARG(*paramList, double); + cnt += DBG_PrintFlt(fltVal, 5); /* default precision: 5 */ + break; + default: + ConsolePutc(ch); /* Output the original input characters */ + cnt += 1; + break; + } + /* returns the count value */ + return cnt; +} + +/** + * @brief Printed number with width + * @param intNum: Numbers to be printed + * @param *paramList: Number of digits to be printed + * @retval returns the number of digits of the output number + */ +static unsigned int DBG_PrintIntWithField(int intNum, int fieldWidth) +{ + int zeroCnt = 0; + int digitsCnt = 0; + unsigned int cnt = 0; + + if (intNum == 0) { + ConsolePutc('0'); + return 1; + } + if (intNum < 0) { + ConsolePutc('-'); /* add symbol */ + cnt++; + intNum = -intNum; + digitsCnt = DBG_CountDigits(intNum, DECIMAL); /* get int value's width */ + zeroCnt = fieldWidth - digitsCnt; + for (int i = 0; i < zeroCnt; i++) { + ConsolePutc('0'); /* add '0' */ + cnt++; + } + cnt += digitsCnt; + } else { + digitsCnt = DBG_CountDigits(intNum, DECIMAL); /* get int value's width */ + cnt = digitsCnt; + zeroCnt = fieldWidth - digitsCnt; + for (int i = 0; i < zeroCnt; i++) { + ConsolePutc('0'); /* add '0' */ + cnt++; + } + } + DBG_PutUnsignedNum(intNum, DECIMAL, digitsCnt); + return cnt; +} + +/** + * @brief Convert a numeric string to a number + * @param **s: Number string to be converted + * @retval Number after conversion + */ +static int DBG_Atoi(const char **s) +{ + int i, c; + + for (i = 0; '0' <= (c = **s) && c <= '9'; ++*s) { + i = i * 10 + c - '0'; /* 10: decimal */ + } + return i; +} + +/** + * @brief Print the entry parameters + * @param *format: thing need to print + * @retval returns the number of digits of the output number + */ +int UartPrintf(const char *format, ...) +{ + /* Define Value Initialization */ + int cnt = 0; + int fieldWidth = 0; + int floatPrecision = 0; + float fltVal = 0; + int intVal = 0; + va_list paramList; + VA_START(paramList, format); + + while (*format != '\0') { + if (*format != '%') { + /* received '%', print characters directly */ + ConsolePutc(*format); + cnt += 1; + } else { + format++; + /* Check whether the value is an integer */ + if (*format == '0') { + format++; + fieldWidth = DBG_Atoi(&format); + intVal = VA_ARG(paramList, int); + cnt += DBG_PrintIntWithField(intVal, fieldWidth); + } else if (*format == '.') { + format++; + floatPrecision = DBG_Atoi(&format); /* Convert to Integer */ + fltVal = VA_ARG(paramList, double); + cnt += DBG_PrintFlt(fltVal, floatPrecision); + } else { + cnt += ParseSpecifier(*format, ¶mList); + } + } + format++; + } + VA_END(paramList); + /* Returns the value of count */ + return cnt; +} + +/* init console uart */ +void ConsoleInit(UART_Handle uart) +{ + g_console_uart = uart; + DfxCmdRegister(); +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/dfx_debug.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/dfx_debug.c new file mode 100644 index 00000000..3084eb4c --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/dfx_debug.c @@ -0,0 +1,43 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dfx_debug.c + * @author MCU Driver Team + * @brief debug module driver + * @details The header file contains the following declaration: + * + Setting the Debug Mode + */ +#include "dfx_debug.h" +#include "cmd.h" +#include "console.h" +#include "dfx_log.h" + +/** + * @brief Enables or disables the debug mode. + * @param mode: Status to be set + * @retval None. + */ +void ExtSetDebugMode(enum ExtDebugMode mode) +{ + struct SysDebugSwitch *debugSwitch = GetDebugSwitch(); + if (mode == RUNNING) { + debugSwitch->enable = 0; /* 0 indicates that the debug mode is disabled */ + return; + } + debugSwitch->enable = 1; /* not 0 indicates that the debug mode is enabled */ + return; +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/dfx_log.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/dfx_log.c new file mode 100644 index 00000000..b0cba421 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/dfx_log.c @@ -0,0 +1,468 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dfx_log.c + * @author MCU Driver Team + * @brief dfx_log module driver + * @details The header file contains the following declaration: + * + Small-scale log output + * + Miniaturized log output with different numbers of int types + */ +#include +#include "string.h" +#include "stdarg.h" +#include "type.h" +#include "dfx_log.h" +#include "common.h" +#include "log.h" +#include "ext_log.h" +#include "securec.h" + +#define EXT_DEFAULT_LOG_LEVEL EXT_LOG_LEVEL_ERROR +#define THIS_FILE_ID FILE_ID_LOG_C +static struct MemoryLog g_memoryLog = {0}; +#define DIVISOR 10 +#define EXT_MODULE_DFX 12 /* Test Version Information Cases */ +/* Address of the test case for obtaining version information */ +#define VERSION_INFO_ADDR 0x4000000 +/* Device Name */ +char *moduleStr[EXT_MODULE_BUTT] = { + "app_main", + "app_console", + "app_chip", + "drv_base", + "drv_chips", + "drv_crg", + "drv_gpio", + "drv_i2c", + "drv_irq", + "drv_pinctrl", + "drv_timer", + "drv_uart", + "dfx", +}; +/* Levels that can be set */ +char *ExtLogLevel1[6] = { + "EXT_LOG_LEVEL_FATAL", + "EXT_LOG_LEVEL_ERROR", + "EXT_LOG_LEVEL_WARNING", + "EXT_LOG_LEVEL_INFO", + "EXT_LOG_LEVEL_DBG", + "EXT_LOG_LEVEL_BUTT", +}; +struct SysLogCtx g_logCtx = { 0 }; +/** + * @defgroup log Common + * @brief Initialize miniaturization log information. + * @{ + */ +struct SysLogCtx *GetLogCtx(void) +{ + return &g_logCtx; +} +static struct SysDebugSwitch g_debugSwitch = {.enable = 1}; +struct SysDebugSwitch *GetDebugSwitch(void) +{ + /* Return Enable Initialization */ + return &g_debugSwitch; +} +/** + * @brief Initialize register information. + * @param memData: Register structure variable + * @retval None. + */ +void InitMemoryData(struct MemoryLog *memData) +{ + memData->enable = EXT_TRUE; + memData->logLen = 0; + memData->writePos = 0; +} + +/** + * @brief Obtains the value of register information. + * @param None. + * @retval memory address + */ +struct MemoryLog *GetMemoryData(void) +{ + return &g_memoryLog; +} + +/** + * @brief Initialize the environment information for miniaturization logs. + * @param ctx: Environment information of miniaturized logs + * @retval None. + */ +void LogCtxInit(struct SysLogCtx *ctx) +{ + ctx->modStr = moduleStr; + for (unsigned char i = 0; i < EXT_MODULE_BUTT; i++) { + ctx->logLevel[i] = EXT_DEFAULT_LOG_LEVEL; + } + ctx->init = EXT_TRUE; +} + +/** + * @brief Write the log to the memory. + * @param *memlog: memory address + * @param src: Stored Information + * @param cnt: Length of the stored information + * @retval None. + */ +static void PutLogToMem(struct MemoryLog *memLog, const char *src, unsigned char cnt) +{ + unsigned char len = cnt; /* default mem write pos < LOG_MEM_POOL_MAX_LEN - cnt */ + + if (cnt > LOG_MEM_POOL_MAX_LEN - memLog->writePos) { + len = LOG_MEM_POOL_MAX_LEN - memLog->writePos; + /* put log data to buf */ + if (memcpy_s(memLog->mmzBuf + memLog->writePos, LOG_MEM_POOL_MAX_LEN - memLog->writePos, src, len) != + EXT_SUCCESS) { + EXT_PRINT("put log to memory memcpy err\n"); + return; + } + /* if the data is full, the position pointer returns to the origin. */ + memLog->writePos = 0; + src += len; + len = cnt - len; + } + /* if the data is full, cyclic write log data */ + if (memcpy_s(memLog->mmzBuf + memLog->writePos, LOG_MEM_POOL_MAX_LEN - memLog->writePos, src, len) != EXT_SUCCESS) { + EXT_PRINT("put log to memory memcpy err\n"); + return; + } + + /* The pointer position is increased by the write length */ + memLog->writePos += len; + memLog->logLen += cnt; + if (memLog->logLen > LOG_MEM_POOL_MAX_LEN) { + memLog->logLen = LOG_MEM_POOL_MAX_LEN; + } +} + +/** + * @brief Calculates the length of an int number converted to a character string. + * @param num: number to calculate. + * @retval Length after being converted to a character string. + */ +static int CountNumberLen(unsigned int num) +{ + int count = 0; + do { + count += 1; + num = num/DIVISOR; + } while (num != 0); /* divided by 10 to round */ + return count; +} + +/** + * @brief Check whether the log output is proper. + * @param level: Specifies the log level. + * @param debugSwitch: Pointer to the debug mode + * @param modId: Device ID + * @param ctx Pointer to storing log information + * @retval Indicates whether the printing is successful. + */ +static unsigned int IsLogOutBufLegal(enum ExtLogLevel level, struct SysDebugSwitch *debugSwitch, + enum ExtModule modId, struct SysLogCtx *ctx) +{ + /* Check whether the value is out of range */ + if (level > EXT_LOG_LEVEL_BUTT || modId > EXT_MODULE_BUTT) + return EXT_FAILURE; + /* Checking the Status of debug */ + if (((!debugSwitch->enable) && (level != EXT_LOG_LEVEL_ERROR)) || (level > ctx->logLevel[modId])) { + return EXT_SUCCESS; + } + return EXT_FAILURE; +} + +/** + * @brief Log output and printing + * @param level: Specifies the log level. + * @param modId: Device ID + * @param id: device name + * @param logBuf: Character string information to be printed + * @param logBuflen: Indicates the length of the printed information. + * @retval Indicates whether the printing is successful. + */ +int ExtDrvLogOutBuf(enum ExtLogLevel level, enum ExtModule modId, unsigned int id, const unsigned int* logBuf, + unsigned short logBufLen) +{ + /* Check whether the array is empty */ + if (logBuf == NULL) + return EXT_FAILURE; + /* Value Definition Initialization */ + char buf[LOG_UINT_MAX_LEN] = { 0 }; + int cnt = 0; + int len = 0; + int count = 0; + + struct SysLogCtx *ctx = GetLogCtx(); + + struct SysDebugSwitch *debugSwitch = GetDebugSwitch(); + if (!ctx->init) { LogCtxInit(ctx); } /* Initialize the structure */ + if (!(IsLogOutBufLegal(level, debugSwitch, modId, ctx))) { return EXT_SUCCESS; } + cnt = sprintf_s(buf, LOG_UINT_MAX_LEN, "%u", id); + /* an error message is displayed when the return value is a negative value */ + if (cnt < 0) { + EXT_PRINT("sprintf err\n"); + return EXT_FAILURE; + } + len += cnt; + + unsigned short i = 0; + /* Write characters cyclically */ + for (; i < logBufLen; ++i) { + count = CountNumberLen(logBuf[i]); + if ((count + len + 1) >= LOG_UINT_MAX_LEN) { return EXT_FAILURE; } + cnt = sprintf_s(buf + len, LOG_UINT_MAX_LEN - len, " %u", logBuf[i]); + /* an error message is displayed when the return value is a negative value */ + if (cnt < 0) { + EXT_PRINT("sprintf err\n"); + return EXT_FAILURE; + } + len += cnt; + } + cnt = sprintf_s(buf + len, LOG_UINT_MAX_LEN - len, "\n"); + len += cnt; + /* an error message is displayed when the return value is a negative value */ + if (cnt < 0) { + EXT_PRINT("sprintf err\n"); + return EXT_FAILURE; + } else if (!ctx->memLog.enable) { + EXT_PRINT("%s", buf); + return EXT_SUCCESS; + } + + PutLogToMem(&ctx->memLog, buf, len); /* Storing the log information into the memory */ + return EXT_SUCCESS; +} + + +/** + * @brief get version info cmd + * @param None + * @retval Return the setting result, success or failure. + */ +int CmdGetVersionInfo(void) +{ + int versionInfo; + versionInfo = EXT_REG_READ32(VERSION_INFO_ADDR); + /* Print version information */ + ExtLog1(ERR, EXT_MODULE_DFX, "version info is : %x\n", versionInfo); + return EXT_SUCCESS; +} +/** + * @brief Processing log buffer + * @param len: Length of the processed data. + * @param level: Specifies the log level. + * @param modId: Device ID + * @param buf: Log information to be processed. + * @retval Indicates whether the printing is successful. + */ +static int DealLogBuf(int len, enum ExtLogLevel level, enum ExtModule modId, const char buf[]) +{ + struct SysLogCtx *ctx = GetLogCtx(); + struct SysDebugSwitch *debugSwitch = GetDebugSwitch(); + /* Checking the Status of debug */ + if (!debugSwitch->enable) { + if (level != EXT_LOG_LEVEL_ERROR) { + return EXT_SUCCESS; + } + } + + if (!ctx->init) { LogCtxInit(ctx); } /* Initialize the structure */ + + if (level > ctx->logLevel[modId]) { return EXT_SUCCESS; } + /* If the length is negative, an error value is returned */ + if (len < 0) { + EXT_PRINT("sprintf err\n"); + return EXT_FAILURE; + } + + if (!ctx->memLog.enable) { + EXT_PRINT("%s", buf); + return EXT_SUCCESS; + } + + PutLogToMem(&ctx->memLog, buf, len); /* Storing the log information into the memory */ + return EXT_SUCCESS; +} + +/** + * @brief Print with no int number + * @param level: Specifies the log level. + * @param modId: Device ID + * @param id: custom string variable + * @retval Indicates whether the printing is successful. + */ +int ExtDrvLogOut0(enum ExtLogLevel level, enum ExtModule modId, unsigned int id) +{ + /* Check whether the value is out of range */ + if (level > EXT_LOG_LEVEL_BUTT || modId > EXT_MODULE_BUTT) + return EXT_FAILURE; + char buf[LOG_UINT_MAX_LEN] = { 0 }; + int len = 0; + len = sprintf_s(buf, LOG_UINT_MAX_LEN, "%u\n", id); + if (len < 0) { + EXT_PRINT("sprintf err\n"); + return EXT_FAILURE; + } + /* Process logs and determine whether to write to memory */ + return (DealLogBuf(len, level, modId, buf)); +} + +/** + * @brief Print with an int number + * @param level: Specifies the log level. + * @param modId: Device ID + * @param id: custom string variable + * @param d0: User-defined first variable of the int type + * @retval Indicates whether the printing is successful. + */ +int ExtDrvLogOut1(enum ExtLogLevel level, enum ExtModule modId, unsigned int id, unsigned int d0) +{ + /* Check whether the value is out of range */ + if (level > EXT_LOG_LEVEL_BUTT || modId > EXT_MODULE_BUTT) + return EXT_FAILURE; + char buf[LOG_UINT_MAX_LEN] = { 0 }; + int len = 0; + len = sprintf_s(buf, LOG_UINT_MAX_LEN, "%u %u\n", id, d0); + if (len < 0) { + EXT_PRINT("sprintf err\n"); + return EXT_FAILURE; + } + /* Process logs and determine whether to write to memory */ + return (DealLogBuf(len, level, modId, buf)); +} + +/** + * @brief Print with two int numbers + * @param level: Specifies the log level. + * @param modId: Device ID + * @param id: custom string variable + * @param d0: User-defined first variable of the int type + * @param d1: User-defined second variable of the int type + * @retval Indicates whether the printing is successful. + */ +int ExtDrvLogOut2(enum ExtLogLevel level, enum ExtModule modId, unsigned int id, unsigned int d0, unsigned int d1) +{ + /* Check whether the value is out of range */ + if (level > EXT_LOG_LEVEL_BUTT || modId > EXT_MODULE_BUTT) + return EXT_FAILURE; + char buf[LOG_UINT_MAX_LEN] = { 0 }; + int len = 0; + len = sprintf_s(buf, LOG_UINT_MAX_LEN, "%u %u %u\n", id, d0, d1); + if (len < 0) { + EXT_PRINT("sprintf err\n"); + return EXT_FAILURE; + } + /* Process logs and determine whether to write to memory */ + return (DealLogBuf(len, level, modId, buf)); +} + +/** + * @brief Print with three int numbers + * @param level: Specifies the log level. + * @param modId: Device ID + * @param id: custom string variable + * @param d0: User-defined first variable of the int type + * @param d1: User-defined second variable of the int type + * @param d2: User-defined third variable of the int type + * @retval Indicates whether the printing is successful. + */ +int ExtDrvLogOut3(enum ExtLogLevel level, enum ExtModule modId, unsigned int id, unsigned int d0, unsigned int d1, + unsigned int d2) +{ + /* Check whether the value is out of range */ + if (level > EXT_LOG_LEVEL_BUTT || modId > EXT_MODULE_BUTT) + return EXT_FAILURE; + char buf[LOG_UINT_MAX_LEN] = { 0 }; + int len = 0; + len = sprintf_s(buf, LOG_UINT_MAX_LEN, "%u %u %u %u\n", id, d0, d1, d2); + if (len < 0) { + EXT_PRINT("sprintf err\n"); + return EXT_FAILURE; + } + /* Process logs and determine whether to write to memory */ + return (DealLogBuf(len, level, modId, buf)); +} + +/** + * @brief Setting the log level + * @param id: Indicates the device ID of the specified level + * @param level: Level set for the device + * @retval Indicates whether the printing is successful + */ +int ExtDrvLogSetLogLevel(enum ExtModule id, enum ExtLogLevel level) +{ + /* Exceeded the maximum value of the storage array */ + if (level >= EXT_LOG_LEVEL_BUTT || id >= EXT_MODULE_BUTT) { + EXT_PRINT("module or level unsupport\n"); + return EXT_FAILURE; + } + + struct SysLogCtx *ctx = GetLogCtx(); + + if (!ctx->init) { + LogCtxInit(ctx); /* Initialize the structure */ + } + ctx->logLevel[id] = level; + return EXT_SUCCESS; +} + +/** + * @brief Logs are output based on different levels + * @param level: Pre-set level + * @param id: Indicates the device ID of the output log + * @param fmt: character string to be output + * @retval Indicates whether the printing is successful + */ +int ExtDrvLogOutFmt(enum ExtLogLevel level, enum ExtModule id, const char *fmt, ...) +{ + /* define value initialization */ + va_list args; + + struct SysDebugSwitch *debugSwitch = GetDebugSwitch(); + if ((!debugSwitch->enable) && (level != EXT_LOG_LEVEL_ERROR)) { + return EXT_SUCCESS; + } + + /* Outputs character strings by level and ID */ + if (level >= EXT_LOG_LEVEL_BUTT || id >= EXT_MODULE_BUTT) { + EXT_PRINT("level %d or module %d err\n", level, id); + return EXT_FAILURE; + } + + char *tag = "FEWIDB"; + struct SysLogCtx *ctx = GetLogCtx(); + + if (!ctx->init) { + LogCtxInit(ctx); /* Initialize the structure */ + } + + if (level > ctx->logLevel[id]) { + return EXT_SUCCESS; + } + EXT_PRINT("%c-%s:", *(tag + level), ctx->modStr[id]); /* Calculate the print length */ + + va_start(args, fmt); + EXT_PRINT(fmt, args); + va_end(args); + EXT_PRINT("\r\n"); + return EXT_SUCCESS; +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/dfx_log_proc.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/dfx_log_proc.c new file mode 100644 index 00000000..03e80edc --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/dfx_log_proc.c @@ -0,0 +1,195 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file gpio_ip.h + * @author MCU Driver Team + * @brief GPIO module driver + * @details The header file contains the following declaration: + * + GPIO configuration enums. + * + GPIO register structures. + * + GPIO DCL Functions. + * + Parameters check functions. + */ +#include +#include +#include "command.h" +#include "dfx_log.h" +#include "log.h" +#include "console.h" +#include "type.h" + +/** + * @brief show the log information. + * @param None + * @retval return whether the display is successful + */ +static int DrvLogShowLogLevel(void) +{ + struct SysLogCtx *ctx = GetLogCtx(); + + if (!ctx->init) { + LogCtxInit(ctx); /* Initialize the structure */ + } + + EXT_PRINT("\n"); + EXT_PRINT("\t ------- module log level -------\n"); /* Delimiter Display Title */ + struct SysDebugSwitch *debugSwitch = GetDebugSwitch(); + if (!debugSwitch->enable) { + EXT_PRINT("The debug mode is disabled, and only err-level information is output\n"); + } + EXT_PRINT("\n"); + EXT_PRINT("ModuleName ModuleId LogLevel\n"); + /* Displays log information line by line in sequence */ + for (unsigned char i = 0; i < EXT_MODULE_BUTT; i++) { + EXT_PRINT("%s\t", ctx->modStr[i]); + EXT_PRINT("%d\t", i); + EXT_PRINT("%d", ctx->logLevel[i]); + EXT_PRINT("\n"); + } + return EXT_SUCCESS; +} + +/** + * @brief write log to memory + * @param enable: Enables log writing to the memory + * @retval return whether the display is successful + */ +static int DrvLogPutLogToMem(unsigned char enable) +{ + if (enable != EXT_TRUE && enable != EXT_FALSE) { + EXT_PRINT("param err\n"); + return EXT_FAILURE; + } + + struct SysLogCtx *ctx = GetLogCtx(); + if (!ctx->init) { + LogCtxInit(ctx); /* Initialize the structure */ + } + /* Flag bit 1 to start writing */ + if (enable) { + ctx->memLog.enable = EXT_TRUE; + EXT_PRINT("log put memory:0x%x enable\n", ctx->memLog.mmzBuf); + } else { + ctx->memLog.enable = EXT_FALSE; + EXT_PRINT("log put memory disable\n"); + } + + /* Initialize Pointer */ + ctx->memLog.writePos = 0; + ctx->memLog.logLen = 0; + return EXT_SUCCESS; +} + +/** + * @brief print the logs stored in the memory + * @param None + * @retval None + */ +static void DrvLogPrintMemLog(void) +{ + struct SysLogCtx *ctx = GetLogCtx(); + if (!ctx->init) { + LogCtxInit(ctx); /* Initialize the structure */ + } + + if (!ctx->memLog.enable) { + EXT_PRINT("mem record log not enable\n"); + return; + } + + unsigned short i; + if (ctx->memLog.logLen == LOG_MEM_POOL_MAX_LEN) { + /* Logs are printed one by one */ + for (i = ctx->memLog.writePos; i < LOG_MEM_POOL_MAX_LEN; ++i) { + EXT_PRINT("%c", ctx->memLog.mmzBuf[i]); + } + } + + /* Cyclic Print Characters */ + for (i = 0; i < ctx->memLog.writePos; ++i) { + EXT_PRINT("%c", ctx->memLog.mmzBuf[i]); + } +} + +/** + * @brief Prints the help information about the log command + * @param None + * @retval None + */ +static void DrvLogCmdHelp(void) +{ + /* Print Command Prompt */ + EXT_PRINT("Usage:\n"); + EXT_PRINT("logcmd show show log info\n"); + EXT_PRINT("logcmd setlevel [moduleId][level] set log level(0:F,1:E,2:W,3:I,4:D)\n"); + EXT_PRINT("logcmd setmem [0/1] enable mem log(1: print to memory, 0: print to console)\n"); + EXT_PRINT("logcmd print print log from memory\n"); +} + +/** + * @brief Command Parsing of Driver Miniaturization Logs + * @param argc: Total number of input strings + * @param argv[]: Entered character string information. + * @retval return whether the display is successful + */ +static int DrvLogCmd(unsigned int argc, const char *argv[]) +{ + char *endp = NULL; + if (argc < 2) { /* 2 is agrc */ + DrvLogCmdHelp(); + return EXT_FAILURE; + } else if (strcmp(argv[1], "show") == 0) { + DrvLogShowLogLevel(); + } else if (strcmp(argv[1], "setlevel") == 0) { + if (argc < 4) { /* 4 is argc */ + DrvLogCmdHelp(); + return EXT_FAILURE; + } + unsigned int modId = strtoul(argv[2], &endp, 0); /* 2 is argv */ + unsigned int level = strtoul(argv[3], &endp, 0); /* 3 is argv */ + if (ExtDrvLogSetLogLevel(modId, level) != EXT_SUCCESS) { + EXT_PRINT("set log level err\n"); + return EXT_FAILURE; + } + EXT_PRINT("setlevel succsee!\r\n"); + } else if (strcmp(argv[1], "setmem") == 0) { + if (argc < 3) { /* 3 is argc */ + DrvLogCmdHelp(); + return EXT_FAILURE; + } + + unsigned char enable = (unsigned char)strtoul(argv[2], &endp, 0); /* 2 is argv */ + if (DrvLogPutLogToMem(enable) != EXT_SUCCESS) { + EXT_PRINT("set put mem err\n"); + return EXT_FAILURE; + } + } else if (strcmp(argv[1], "print") == 0) { + DrvLogPrintMemLog(); + } + + return EXT_SUCCESS; +} + +/** + * @brief init dfx + * @param None + * @retval None + */ +void DfxCmdRegister(void) +{ + ExtCmdRegister("logcmd", &DrvLogCmd); +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/event.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/event.c new file mode 100644 index 00000000..0f8eb7a6 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/event.c @@ -0,0 +1,91 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file event.c + * @author MCU Driver Team + * @brief Header file containing functions prototypes of erron module. + * + Defines the function of reporting initialization events. + */ +#include "event.h" +#include "console.h" +#include "command.h" +#include "common.h" +#include "typedefs.h" + +UserMgr g_userMgr; + +/** + * @brief Event report. + * @param eventObj : Unsolicitedly reported events + * @retval Indicates whether the upload is successful. + */ +static inline int UserReport(UserEventObj *eventObj) +{ + unsigned int *reportAddr = (unsigned int *)&g_userMgr.reportAddr; + + /* Obtain reported events */ + *reportAddr = (uintptr_t)(void *)&eventObj->report; + EXT_PRINT("event report type: %u event type: %u ", eventObj->report.event.eventType, eventObj->report.reportType); + g_userMgr.reportLock = 0; + return EXT_SUCCESS; +} + +/** + * @brief Obtains the address for reporting events. + * @param None + * @retval Address to which the event is reported. + */ +static UserEventObj *UserGetEventObj(void) +{ + /* The event is locked and cannot be reported */ + if (g_userMgr.reportLock == 1) { + g_userMgr.reportFailedCount++; + return NULL; + } + + g_userMgr.reportLock = 1; + return &g_userMgr.eventObj; +} + +/** + * @brief Reporting an event + * @param eventObj: Structure for storing reported events + * @retval Indicates whether the upload is successful. + */ +int UserReportEvent(UserEventObj *eventObj) +{ + UserEventObj *obj = (UserEventObj *)UserGetEventObj(); + /* If it is locked, it cannot be reported */ + if (obj == NULL) { + return EXT_FAILURE; + } + + *obj = *eventObj; + + return UserReport(&g_userMgr.eventObj); +} + +/** + * @brief RInitializing event reporting + * @param None + * @retval For user-defined + */ +int EventInit(void) +{ + /* Users can customize event reporting based on their requirements */ + return 0; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/ext_command.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/ext_command.c new file mode 100644 index 00000000..7bbf842c --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/log/src/ext_command.c @@ -0,0 +1,123 @@ +/** + * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file ext_command.c + * @author MCU Driver Team + * @brief command module driver + * @details The header file contains the following declaration: + * + Mainly including query commands. + * + Mainly including matching command. + */ +#include +#include +#include "command.h" +#include "cmd.h" +#include "common.h" +#define USER_COMMAND_START 0x50000 +#define USER_COMMAND_END 0x60000 + +/** + * @brief Commands contained in the query string. + * @param cmd: Contains command information. + * @retval Indicates whether the query is successful. + */ +struct cmdRegisterTable *ExtCmdFindCmd(const char *cmd) +{ + struct cmdRegisterTable *cmdtp = GetRegisterAddr(); + const char *p = NULL; + + unsigned int tblLen = CMD_REGESTER_MAX_NUM; + unsigned int cmdLen; + + if (tblLen == 0 || cmd == NULL) { + return NULL; + } + + /* compare command name only until first dot */ + p = strchr(cmd, '.'); + cmdLen = (p == NULL) ? (unsigned char)strlen(cmd) : (unsigned char)(p - cmd); + + for (int i = 0; i < CMD_REGESTER_MAX_NUM; i++, cmdtp++) { + if (cmdtp->name == NULL) { + return NULL; + } + + if ((p != NULL) && (cmdLen != 0)) { + if (strncmp(cmd, cmdtp->name, cmdLen) == 0) { + return cmdtp; /* only match part before dot */ + } + } + + if (strcmp(cmd, cmdtp->name) == 0) { + return cmdtp; /* full match */ + } + } + return NULL; /* not found */ +} + +/** + * @brief Matches valid commands based on included commands. + * @param head: Command to be queried. + * @param resLen: Length of the string to be found. + * @param finCnt: Set the number of times to be searched. + * @param tailId: End Flag Character + * @retval Indicates whether the query is successful. + */ +static unsigned char IsFindMatchCmdParamLegal(const char *head, unsigned char resLen, unsigned char *findCnt, + const char *res[]) +{ + if (head == NULL || resLen == 0 || findCnt == NULL || res == NULL) { return EXT_FALSE; } + return EXT_TRUE; +} + +/** + * @brief Matches valid commands based on included commands. + * @param head: Command to be queried. + * @param *res[]: An array that temporarily stores strings. + * @param resLen: Length of the string to be found. + * @param finCnt: Set the number of times to be searched. + * @param tailId: End Flag Character + * @retval Indicates whether the query is successful. + */ +unsigned char ExtCmdFindMatchCmd(const char *head, const char *res[], unsigned char resLen, unsigned char *findCnt, + unsigned int *tailId) +{ + /* Define Value Initialization */ + unsigned char ret = EXT_TRUE; + unsigned int cmdId = 0; + size_t headLen = 0; + /* initialization structure */ + struct cmdRegisterTable *cmdtp = GetRegisterAddr(); + + if (!IsFindMatchCmdParamLegal(head, resLen, findCnt, res)) { return EXT_FALSE; } + headLen = strlen(head); + for (int i = 0; i < CMD_REGESTER_MAX_NUM; cmdtp++, cmdId++, i++) { + if (cmdtp->name == NULL) { break; } /* search finish */ + if (*findCnt >= resLen) { /* search not finish */ + ret = EXT_FALSE; + break; + } + + /* detect registered name */ + if ((*tailId > 0 && (unsigned int)cmdId < *tailId) || strlen(cmdtp->name) < (unsigned int)headLen + || strcmp(cmdtp->name, UART_SWITCH_CMD) == 0) { continue; } + + if (strncmp(head, cmdtp->name, headLen) == 0) { res[(*findCnt)++] = cmdtp->name; } + } + *tailId = cmdId; + return ret; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/src/debug.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/src/debug.c new file mode 100644 index 00000000..d7cb26bc --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/debug/src/debug.c @@ -0,0 +1,416 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file debug.c + * @author MCU Driver Team + * @brief DEBUG module driver. + * This file provides functions to manage the following functionalities of the DEBUG module. + * + Initialization and de-initialization functions + * + Format string print function + */ + +#include "debug.h" + +#if (DBG_PRINTF_USE == DBG_USE_UART_PRINTF) +/* Macro definitions of stdarg.h to prevent using standard library */ +#define VA_START(v, l) __builtin_va_start(v, l) +#define VA_ARG(v, l) __builtin_va_arg(v, l) +#define VA_END(v) __builtin_va_end(v) + +#define DECIMAL_BASE 10U /* Cardinality of decimal numbers */ +#define HALF_ADJUST_BOUNDARY 5U /* The boundary for rounding the floating number */ +#define MAX_DIV_TIMES 31U +/* FLOAT_SCALE = DECIMAL_BASE ^ (FLOAT_PRECISION + 1) */ +#endif + +typedef __builtin_va_list va_list; + +#if (DBG_PRINTF_USE == DBG_USE_UART_PRINTF) +/** + * @brief Cardinality of binary, octal, decimal, and hexadecimal numbers. + */ +typedef enum { + BINARY = 2U, + OCTAL = 8U, + DECIMAL = 10U, + HEXADECIMAL = 16U, +} NumBase; +#endif + +#if (DBG_PRINTF_USE == DBG_USE_UART_PRINTF) +UART_Handle g_dbgUart; +/** + * @brief Initialize the UART port for DBG_UartPrintf(). + * @param baudRate The baud rate of UART port. + * @retval BASE_StatusType BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType DBG_UartPrintInit(unsigned int baudRate) +{ + g_dbgUart.baseAddress = DBG_PRINTF_UART_PORT; + g_dbgUart.baudRate = baudRate; + g_dbgUart.dataLength = UART_DATALENGTH_8BIT; + g_dbgUart.stopBits = UART_STOPBITS_ONE; + g_dbgUart.parity = UART_PARITY_NONE; + g_dbgUart.txMode = UART_MODE_BLOCKING; + g_dbgUart.rxMode = UART_MODE_BLOCKING; + g_dbgUart.fifoMode = true; + g_dbgUart.fifoTxThr = UART_FIFOFULL_ONE_EIGHT; + g_dbgUart.fifoRxThr = UART_FIFOFULL_ONE_EIGHT; + g_dbgUart.hwFlowCtr = UART_HW_FLOWCTR_DISABLE; + return HAL_UART_Init(&g_dbgUart); +} + +/** + * @brief De-initialize the UART port for DBG_UartPrintf(). + * @retval BASE_StatusType BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType DBG_UartPrintDeInit(void) +{ + return HAL_UART_DeInit(&g_dbgUart); +} +#endif + +/* Format string print function */ +#if (DBG_PRINTF_USE == DBG_USE_UART_PRINTF) +/** + * @brief Write a character to the UART port. + * @param ch The int promotion of the character to be written. + * @retval None. + */ +static void DBG_PrintCh(unsigned int ch) +{ + while (DBG_PRINTF_UART_PORT->UART_FR.BIT.txff == 1) { + ; + } + DBG_PRINTF_UART_PORT->UART_DR.BIT.data = (unsigned char)ch; +} + +/** + * @brief Print a string through the UART port. + * @param str The string to be printed. + * @retval int If succeeded, the total number of characters printed is returned. + * If the input parameter is wrong, a BASE_STATUS_ERROR is returned. + */ +static int DBG_PrintStr(const char *str) +{ + DEBUG_ASSERT_PARAM(str != NULL); + int cnt = 0; + while (*str != '\0') { + DBG_PrintCh(*str); + str++; + cnt++; + } + return cnt; +} + +/** + * @brief Raise base value to the power exponent value. + * @param base Base value. + * @param exponent Exponent value. + * @retval unsigned long The result of raising base to the power exponent. + */ +static unsigned long DBG_Pow(unsigned int base, unsigned int exponent) +{ + unsigned long ret = 1; + while (exponent--) { + ret *= base; + } + return ret; /* ret = base ^ exponent */ +} + +/** + * @brief Count the digits of the number. + * @param num The number to be counted. + * @param base The number base of num. + * @retval unsigned int The number of digits. + */ +static unsigned int DBG_CountDigits(int num, NumBase base) +{ + unsigned int cnt = 0; + if (base == 0) { + return 0; + } + while (num != 0) { + cnt++; + if (cnt > MAX_DIV_TIMES) { + break; + } + num /= base; + } + cnt = (cnt == 0) ? 1 : cnt; + return cnt; +} + +/** + * @brief Print unsigned number through UART port. + * @param num The unsigned number to be printed. + * @param base The number base of num. + * @param digits The digits of num. + */ +static void DBG_PutUnsignedNum(unsigned int num, NumBase base, unsigned int digits) +{ + unsigned char ch; + while (digits != 0) { + ch = num / DBG_Pow(base, digits - 1); + num %= DBG_Pow(base, digits - 1); + if (base == DECIMAL) { + DBG_PrintCh(ch + '0'); + } else if (base == HEXADECIMAL) { + if (ch < DECIMAL_BASE) { + DBG_PrintCh(ch + '0'); + } else { + DBG_PrintCh(ch - DECIMAL_BASE + 'A'); + } + } else { + break; + } + digits--; + } +} + +/** + * @brief Print decimal number through UART port. + * @param intNum The decimal number to be printed. + * @retval unsigned int The total number of characters printed. + */ +static unsigned int DBG_PrintInt(int intNum) +{ + unsigned int cnt; + if (intNum == 0) { + DBG_PrintCh('0'); + return 1; + } + if (intNum < 0) { + DBG_PrintCh('-'); + intNum = -intNum; + } + cnt = DBG_CountDigits(intNum, DECIMAL); + DBG_PutUnsignedNum(intNum, DECIMAL, cnt); + return cnt; +} + +/** + * @brief Print hexadecimal number through UART port. + * @param hexNum The hexadecimal number to be printed. + * @retval unsigned int The total number of characters printed. + */ +static unsigned int DBG_PrintHex(unsigned int hexNum) +{ + unsigned int cnt; + if (hexNum == 0) { + DBG_PrintCh('0'); + return 1; + } + cnt = DBG_CountDigits(hexNum, HEXADECIMAL); + DBG_PutUnsignedNum(hexNum, HEXADECIMAL, cnt); + return cnt; +} + +/** + * @brief Print floating-point number through UART port. + * @param fltNum The floating-point number to be printed. + * @retval unsigned int The total number of characters printed. + */ +static unsigned int DBG_PrintFlt(float fltNum, unsigned int precision) +{ + unsigned int cnt = 0; + unsigned int floatScale; + + if (fltNum < 0) { + DBG_PrintCh('-'); + cnt += 1; + fltNum = -fltNum; + } + int integerVal = (int)fltNum; + floatScale = DBG_Pow(10, (precision + 1)); /* 10: decimal */ + int floatVal = (long)(floatScale * (fltNum - integerVal)); + /* Half-adjust: round up or round down */ + if (floatVal % DECIMAL_BASE >= HALF_ADJUST_BOUNDARY) { + floatVal = floatVal / DECIMAL_BASE + 1; + } else { + floatVal = floatVal / DECIMAL_BASE; + } + cnt += DBG_PrintInt(integerVal); + DBG_PrintCh('.'); + cnt += 1; + /* Pad 0 in float part */ + unsigned int fltCnt = DBG_CountDigits(floatVal, DECIMAL); + if (precision > fltCnt) { + for (unsigned int i = 0; i < precision - fltCnt; i++) { + DBG_PrintCh('0'); /* add '0' */ + } + } + DBG_PutUnsignedNum(floatVal, DECIMAL, fltCnt); /* print unsigned number */ + cnt += precision; + return cnt; +} + +/** + * @brief Parse the format specifier and print the parameter by format. + * @param ch The format specifier. + * @param paramList The pointer of the variable parameter list. + * @retval unsigned int The total number of characters printed. + */ +static unsigned int ParseSpecifier(const char ch, va_list *paramList) +{ + unsigned int cnt = 0; + unsigned int tmpCnt; + char chVal = 0; + const char *strVal = NULL; + int intVal = 0; + unsigned int unsignedVal = 0; + unsigned int hexVal = 0; + float fltVal = 0; + switch (ch) { + case 'c': /* Character format data. */ + chVal = VA_ARG(*paramList, int); /* Use type int because of byte alignment */ + DBG_PrintCh(chVal); + cnt += 1; + break; + case 's': /* String format data. */ + strVal = VA_ARG(*paramList, const char *); + cnt += DBG_PrintStr(strVal); + break; + case 'd': /* Integer decimal data. */ + intVal = VA_ARG(*paramList, int); + cnt += DBG_PrintInt(intVal); + break; + case 'u': /* Unsigned decimal data. */ + unsignedVal = VA_ARG(*paramList, unsigned int); + tmpCnt = DBG_CountDigits(unsignedVal, DECIMAL); + DBG_PutUnsignedNum(unsignedVal, DECIMAL, tmpCnt); + cnt += tmpCnt; + break; + case 'x': /* Hexadecimal data. */ + case 'X': + case 'p': /* Address data. */ + hexVal = VA_ARG(*paramList, unsigned int); + cnt += DBG_PrintHex(hexVal); + break; + case 'f': /* Floating-point data. */ + fltVal = VA_ARG(*paramList, double); + cnt += DBG_PrintFlt(fltVal, 5); /* default precision: 5 */ + break; + default: + DBG_PrintCh(ch); + cnt += 1; + break; + } + return cnt; +} + +/** + * @brief Print decimal number with field width. + * @param intNum The decimal number to be printed. + * @param fieldWidth Field width. + * @retval unsigned int The total number of characters printed. + */ +static unsigned int DBG_PrintIntWithField(int intNum, int fieldWidth) +{ + int zeroCnt = 0; + int digitsCnt = 0; + unsigned int cnt = 0; + + if (intNum == 0) { + DBG_PrintCh('0'); + return 1; + } + if (intNum < 0) { + DBG_PrintCh('-'); /* add symbol */ + cnt++; + intNum = -intNum; + digitsCnt = DBG_CountDigits(intNum, DECIMAL); /* get int value's width */ + zeroCnt = fieldWidth - digitsCnt; + for (int i = 0; i < zeroCnt; i++) { + DBG_PrintCh('0'); /* add '0' */ + cnt++; + } + cnt += digitsCnt; + } else { + digitsCnt = DBG_CountDigits(intNum, DECIMAL); /* get int value's width */ + cnt = digitsCnt; + zeroCnt = fieldWidth - digitsCnt; + for (int i = 0; i < zeroCnt; i++) { + DBG_PrintCh('0'); /* add '0' */ + cnt++; + } + } + DBG_PutUnsignedNum(intNum, DECIMAL, digitsCnt); + return cnt; +} + +static int DBG_Atoi(const char **s) +{ + int i, c; + + for (i = 0; '0' <= (c = **s) && c <= '9'; ++*s) { + i = i * 10 + c - '0'; /* 10: decimal */ + } + return i; +} + +/** + * @brief Print format string through UART port, supporting %c, %s, %d, %u, %x, %X, %p, %f. + * %c To print a character. + * %s To print a string. + * %d To print a decimal value. + * %u To print an unsigned decimal value. + * %x, %X To print a hexadecimal value using upper case letters. + * %p To print a pointer as a hexadecimal value. + * %f To print a floating-point number with a fixed precision determined by FLOAT_PRECISION. + * @param format A string that contains the text to be printed and the format specifiers. + * @param ... Variable parameter list. + * @retval int If succeeded, the total number of characters printed is returned. + * If the input parameter is wrong, return BASE_STATUS_ERROR. + */ +int DBG_UartPrintf(const char *format, ...) +{ + DEBUG_ASSERT_PARAM(format != NULL); + int cnt = 0; + int fieldWidth = 0; + int floatPrecision = 0; + float fltVal = 0; + int intVal = 0; + va_list paramList; + VA_START(paramList, format); + + while (*format != '\0') { + if (*format != '%') { + DBG_PrintCh(*format); + cnt += 1; + } else { + format++; + if (*format == '0') { + format++; + fieldWidth = DBG_Atoi(&format); + intVal = VA_ARG(paramList, int); + cnt += DBG_PrintIntWithField(intVal, fieldWidth); + } else if (*format == '.') { + format++; + floatPrecision = DBG_Atoi(&format); + fltVal = VA_ARG(paramList, double); + cnt += DBG_PrintFlt(fltVal, floatPrecision); + } else { + cnt += ParseSpecifier(*format, ¶mList); + } + } + format++; + } + VA_END(paramList); + return cnt; +} +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dma/common/inc/dma.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dma/common/inc/dma.h new file mode 100644 index 00000000..acd7381b --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dma/common/inc/dma.h @@ -0,0 +1,134 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dma.h + * @author MCU Driver Team + * @brief DMA module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the DMA. + * + The definition of the DMA handle structure. + * + Initialization and de-initialization functions + * + Peripheral querying the transmission functions. + * + Peripheral interrupt handler and callback registration functions. + */ + +/* Includes ------------------------------------------------------------------*/ +#ifndef McuMagicTag_DMA_H +#define McuMagicTag_DMA_H +#include "dma_ip.h" + +/** + * @defgroup DMA DMA + * @brief DMA module. + * @{ + */ + +/** + * @defgroup DMA_Common DMA Common + * @brief DMA common external module. + * @{ + */ + +/** + * @defgroup DMA_Handle_Definition DMA Handle Definition + * @{ + */ + +/** + * @brief The definition of the DMA handle structure. + */ +typedef struct _DMA_Handle { + DMA_RegStruct *baseAddress; /**< DMA common registers base address */ + struct { + DMA_ChannelRegStruct *channelAddr; /**< DMA channel registers base address */ + DMA_TransDirection direction; /**< The transmission direction type */ + DMA_RequestLineNum srcPeriph; /**< Source device request line, memory ignore configuration */ + DMA_RequestLineNum destPeriph; /**< Destination device request line, memory ignore configuration */ + DMA_AddrIncMode srcAddrInc; /**< Address increase configuration of source device */ + DMA_AddrIncMode destAddrInc; /**< Address increase configuration of destination device */ + DMA_BurstLength srcBurst; /**< Burst length of source device */ + DMA_BurstLength destBurst; /**< Burst length of destination device */ + DMA_TransmisWidth srcWidth; /**< Transfer width of source device */ + DMA_TransmisWidth destWidth; /**< Transfer width of destination device */ + void *pHandle; /**< Handle of the modules that use the DMA */ + unsigned int srcAddr; /**< Readback value from the source address to the register */ + unsigned int destAddr; /**< Readback value from the destnation address to the register */ + unsigned int controlVal; /**< Readback value of the DMA control register */ + unsigned int configVal; /**< Readback value of the DMA configuration register */ + } DMA_Channels[CHANNEL_MAX_NUM]; + DMA_UserCallBack userCallBack; /**< User callback */ + DMA_ExtendHandle handleEx; /**< DMA extend parameter */ +} DMA_Handle; + +/** + * @brief The definition of the DMA channel param structure. + */ +typedef struct { + DMA_RequestLineNum srcPeriph; /**< Source device request line, memory ignore configuration */ + DMA_RequestLineNum destPeriph; /**< Destination device request line, memory ignore configuration */ + DMA_TransDirection direction; /**< The transmission direction type */ + DMA_AddrIncMode srcAddrInc; /**< Address increase configuration of source device */ + DMA_AddrIncMode destAddrInc; /**< Address increase configuration of destination device */ + DMA_BurstLength srcBurst; /**< Burst length of source device */ + DMA_BurstLength destBurst; /**< Burst length of destination device */ + DMA_TransmisWidth srcWidth; /**< Transfer width of source device */ + DMA_TransmisWidth destWidth; /**< Transfer width of destination device */ + void *pHandle; /**< Parameter handle of the users callback function */ +} DMA_ChannelParam; + +typedef void (* DMA_CallbackType)(void *handle); +/** + * @} + */ + +/** + * @defgroup DMA_API_Declaration DMA HAL API + * @{ + */ +/* Hardware abstraction layer */ +BASE_StatusType HAL_DMA_Init(DMA_Handle *dmaHandle); +BASE_StatusType HAL_DMA_Deinit(DMA_Handle *dmaHandle); +BASE_StatusType HAL_DMA_Start(DMA_Handle *dmaHandle, unsigned int srcAddr, + unsigned int destAddr, unsigned int dataLength, unsigned int channel); +BASE_StatusType HAL_DMA_StartIT(DMA_Handle *dmaHandle, unsigned int srcAddr, + unsigned int destAddr, unsigned int dataLength, unsigned int channel); +BASE_StatusType HAL_DMA_StopChannel(DMA_Handle *dmaHandle, unsigned int channel); +BASE_StatusType HAL_DMA_GetChannelState(DMA_Handle *dmaHandle, unsigned int channel); +BASE_StatusType HAL_DMA_InitChannel(DMA_Handle *dmaHandle, DMA_ChannelParam *channelParam, unsigned int channel); +void HAL_DMA_IrqHandlerTc(void *handle); +void HAL_DMA_IrqHandlerError(void *handle); +void HAL_DMA_RegisterCallback(DMA_Handle *dmaHandle, DMA_CallbackFun_Type typeID, + DMA_ChannelNum channel, DMA_CallbackType pCallback); +BASE_StatusType HAL_DMA_ListAddNode(DMA_LinkList *head, DMA_LinkList *newNode); +BASE_StatusType HAL_DMA_InitNewNode(DMA_LinkList *node, const DMA_ChannelParam *param, + unsigned int srcAddr, unsigned int destAddr, unsigned int tranSize); +BASE_StatusType HAL_DMA_StartListTransfer(DMA_Handle *dmaHandle, DMA_LinkList *head, unsigned int channel); +#ifdef BASE_DEFINE_DMA_QUICKSTART +void HAL_DMA_QuickStart(DMA_Handle *dmaHandle, unsigned int channel); +#endif +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_DMA_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dma/inc/dma_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dma/inc/dma_ip.h new file mode 100644 index 00000000..0a8895a7 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dma/inc/dma_ip.h @@ -0,0 +1,1205 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dma_ip.h + * @author MCU Driver Team + * @brief DMA module driver + * @details This file provides DCL functions to manage DMA and Definition of + * specific parameters. + * + Definition of DMA configuration parameters. + * + DMA register mapping structure. + * + Parameters check functions. + * + Direct configuration layer interface. + */ + +#ifndef McuMagicTag_DMA_IP_H +#define McuMagicTag_DMA_IP_H + +#include "baseinc.h" + +#define CHANNEL_MAX_NUM 4 +#define TRANSIZE_MAX 4095 +#define TRANS_BLOCK 4092 + +#ifdef DMA_PARAM_CHECK +#define DMA_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define DMA_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define DMA_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define DMA_ASSERT_PARAM(para) ((void)0U) +#define DMA_PARAM_CHECK_NO_RET(para) ((void)0U) +#define DMA_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +/** + * @addtogroup DMA + * @{ + */ + +/** + * @defgroup DMA_IP DMA_IP + * @brief DMA_IP: dma_v0. + * @{ + */ + +/** + * @defgroup DMA_Param_Def DMA Parameters Definition + * @brief Description of DMA configuration parameters. + * @{ + */ + +/** + * @brief Indicates the burst length of the destination device and the source device. + */ +typedef enum { + DMA_BURST_LENGTH_1 = 0x00000000U, + DMA_BURST_LENGTH_4 = 0x00000001U, + DMA_BURST_LENGTH_8 = 0x00000002U, + DMA_BURST_LENGTH_16 = 0x00000003U, + DMA_BURST_LENGTH_32 = 0x00000004U, + DMA_BURST_LENGTH_64 = 0x00000005U, + DMA_BURST_LENGTH_128 = 0x00000006U, + DMA_BURST_LENGTH_256 = 0x00000007U +} DMA_BurstLength; + +/** + * @brief DMA transfer width definition. + */ +typedef enum { + DMA_TRANSWIDTH_BYTE = 0x00000000U, + DMA_TRANSWIDTH_HALFWORD = 0x00000001U, + DMA_TRANSWIDTH_WORD = 0x00000002U +} DMA_TransmisWidth; + +/** + * @brief DMA channel ID, a smaller channel ID indicates a higher priority. + */ +typedef enum { + DMA_CHANNEL_ZERO = 0x00000000U, + DMA_CHANNEL_ONE = 0x00000001U, + DMA_CHANNEL_TWO = 0x00000002U, + DMA_CHANNEL_THREE = 0x00000003U +} DMA_ChannelNum; + +/** + * @brief DMA channel ID, a smaller channel ID indicates a higher priority. + */ +typedef enum { + DMA_CHANNEL_FINISH = 0x00000000U, + DMA_CHANNEL_ERROR = 0x00000001U +} DMA_CallbackFun_Type; + +/** + * @brief DMA Master type. + */ +typedef enum { + DMA_MASTER1 = 0x00000000U, + DMA_MASTER2 = 0x00000001U +} DMA_Master; + +/** + * @brief DMA request peripheral. The multiplexed transmitter requires additional + * configuration of the system register. + * @details DMA request line type: + * + DMA_REQUEST_I2C_RX -- I2C_RX and TIMER2 reuse the request line numbered 0 + * + DMA_REQUEST_I2C_TX -- I2C_TX and TIMER3 reuse the request line numbered 1 + * + DMA_REQUEST_UART0_RX -- UART0_RX use the request line numbered 2 + * + DMA_REQUEST_UART0_TX -- UART0_TX use the request line numbered 3 + * + DMA_REQUEST_UART1_RX -- UART1_RX use the request line numbered 4 + * + DMA_REQUEST_UART1_TX -- UART1_RX and APT8 reuse the request line numbered 5 + * + DMA_REQUEST_UART2_RX -- SPI_RX and UART2_RX reuse the request line numbered 6 + * + DMA_REQUEST_UART2_TX -- SPI_TX and UART2_TX reuse the request line numbered 7 + * + DMA_REQUEST_SPI_RX -- SPI_RX and UART2_RX reuse the request line numbered 6 + * + DMA_REQUEST_SPI_TX -- UART1_RX and APT8 reuse the request line numbered 5 + * + DMA_REQUEST_CAPM0 -- CAPM0 and APT0 reuse the request line numbered 8 + * + DMA_REQUEST_CAPM1 -- CAPM1 and APT1 reuse the request line numbered 9 + * + DMA_REQUEST_CAPM2 -- CAPM2 and APT2 reuse the request line numbered 10 + * + DMA_REQUEST_ADC0 -- ADC0 and APT3 reuse the request line numbered 11 + * + DMA_REQUEST_ADC1 -- ADC1 and APT4 reuse the request line numbered 12 + * + DMA_REQUEST_ADC2 -- ADC2 and APT5 reuse the request line numbered 13 + * + DMA_REQUEST_TIMER0 -- TIMER0 and APT6 reuse the request line numbered 14 + * + DMA_REQUEST_TIMER1 -- TIMER1 and APT7 reuse the request line numbered 15 + * + DMA_REQUEST_TIMER2 -- TIMER2 and I2C_RX reuse the request line numbered 0 + * + DMA_REQUEST_TIMER3 -- TIMER3 and I2C_TX reuse the request line numbered 1 + * + DMA_REQUEST_APT0 -- CAPM0 and APT0 reuse the request line numbered 8 + * + DMA_REQUEST_APT1 -- CAMP1 and APT1 reuse the request line numbered 9 + * + DMA_REQUEST_APT2 -- CAPM2 and APT2 reuse the request line numbered 10 + * + DMA_REQUEST_APT3 -- ADC0 and APT3 reuse the request line numbered 11 + * + DMA_REQUEST_APT4 -- ADC1 and APT4 reuse the request line numbered 12 + * + DMA_REQUEST_APT5 -- ADC2 and APT5 reuse the request line numbered 13 + * + DMA_REQUEST_APT6 -- TIMER0 and APT6 reuse the request line numbered 14 + * + DMA_REQUEST_APT7 -- TIMER1 and APT7 reuse the request line numbered 15 + * + DMA_REQUEST_APT8 -- APT8 and UART1_RX reuse the request line numbered 5 + * + DMA_REQUEST_MEM -- The source and destination devices are memory + */ +typedef enum { + DMA_REQUEST_I2C_RX = 0x00000000U, + DMA_REQUEST_I2C_TX = 0x00000001U, + DMA_REQUEST_UART0_RX = 0x00000002U, + DMA_REQUEST_UART0_TX = 0x00000003U, + DMA_REQUEST_UART1_RX = 0x00000004U, + DMA_REQUEST_UART1_TX = 0x00000005U, + DMA_REQUEST_SPI_RX = 0x00000006U, + DMA_REQUEST_SPI_TX = 0x00000007U, + DMA_REQUEST_CAPM0 = 0x00000008U, + DMA_REQUEST_CAPM1 = 0x00000009U, + DMA_REQUEST_CAPM2 = 0x0000000AU, + DMA_REQUEST_ADC0 = 0x0000000BU, + DMA_REQUEST_ADC1 = 0x0000000CU, + DMA_REQUEST_ADC2 = 0x0000000DU, + DMA_REQUEST_TIMER0 = 0x0000000EU, + DMA_REQUEST_TIMER1 = 0x0000000FU, + DMA_REQUEST_UART2_RX = 0x00000010U, + DMA_REQUEST_UART2_TX = 0x00000011U, + DMA_REQUEST_APT8 = 0x00000012U, + DMA_REQUEST_APT0 = 0x00000013U, + DMA_REQUEST_APT1 = 0x00000014U, + DMA_REQUEST_APT2 = 0x00000015U, + DMA_REQUEST_APT3 = 0x00000016U, + DMA_REQUEST_APT4 = 0x00000017U, + DMA_REQUEST_APT5 = 0x00000018U, + DMA_REQUEST_APT6 = 0x00000019U, + DMA_REQUEST_APT7 = 0x0000001AU, + DMA_REQUEST_TIMER2 = 0x0000001BU, + DMA_REQUEST_TIMER3 = 0x0000001CU, + DMA_REQUEST_MEM = 0x0000001DU +} DMA_RequestLineNum; + +/** + * @brief DMA peripheral request line. The multiplexed transmitter requires additional + * configuration of the system register. + */ +typedef enum { + DMA_REQLINEVAL_0 = 0x00000000U, + DMA_REQLINEVAL_1 = 0x00000001U, + DMA_REQLINEVAL_2 = 0x00000002U, + DMA_REQLINEVAL_3 = 0x00000003U, + DMA_REQLINEVAL_4 = 0x00000004U, + DMA_REQLINEVAL_5 = 0x00000005U, + DMA_REQLINEVAL_6 = 0x00000006U, + DMA_REQLINEVAL_7 = 0x00000007U, + DMA_REQLINEVAL_8 = 0x00000008U, + DMA_REQLINEVAL_9 = 0x00000009U, + DMA_REQLINEVAL_10 = 0x0000000AU, + DMA_REQLINEVAL_11 = 0x0000000BU, + DMA_REQLINEVAL_12 = 0x0000000CU, + DMA_REQLINEVAL_13 = 0x0000000DU, + DMA_REQLINEVAL_14 = 0x0000000EU, + DMA_REQLINEVAL_15 = 0x0000000FU +} DMA_ReqLineVal; + +/** + * @brief Configuration value definition of the peripheral multiplexing DMA request line. + */ +typedef enum { + DMA_SYSCTRLSET_0 = 0x00000000U, + DMA_SYSCTRLSET_1 = 0x00000001U, + DMA_SYSCTRLSET_2 = 0x00000002U +} DMA_SysctrlSet; + +/** + * @brief DMA Transfer Byte Order. + */ +typedef enum { + DMA_BYTEORDER_SMALLENDIAN = 0x00000000U, + DMA_BYTEORDER_BIGENDIAN = 0x00000001U +} DMA_ByteOrder; + +/** + * @brief Define the transmission direction type and data flow controller. + * @details Transmission direction type: + * + DMA_MEMORY_TO_MEMORY_BY_DMAC -- Direc: memory to memory, control: DMAC + * + DMA_MEMORY_TO_PERIPH_BY_DMAC -- Direc: memory to peripheral, control: DMAC + * + DMA_PERIPH_TO_MEMORY_BY_DMAC -- Direc: peripheral to memory, control: DMAC + * + DMA_PERIPH_TO_PERIPH_BY_DMAC -- Direc: peripheral to peripheral, control: DMAC + * + DMA_PERIPH_TO_PERIPH_BY_DES -- Direc: peripheral to peripheral, control: destination peripheral + * + DMA_MEMORY_TO_PERIPH_BY_DES -- Direc: memory to peripheral, control: destination peripheral + * + DMA_PERIPH_TO_MEMORY_BY_SRC -- Direc: peripheral to memory, control: source peripheral + * + DMA_PERIPH_TO_PERIPH_BY_SRC -- Direc: peripheral to peripheral, control: source peripheral + * + */ +typedef enum { + DMA_MEMORY_TO_MEMORY_BY_DMAC = 0x00000000U, + DMA_MEMORY_TO_PERIPH_BY_DMAC = 0x00000001U, + DMA_PERIPH_TO_MEMORY_BY_DMAC = 0x00000002U, + DMA_PERIPH_TO_PERIPH_BY_DMAC = 0x00000003U, + DMA_PERIPH_TO_PERIPH_BY_DES = 0x00000004U, + DMA_MEMORY_TO_PERIPH_BY_DES = 0x00000005U, + DMA_PERIPH_TO_MEMORY_BY_SRC = 0x00000006U, + DMA_PERIPH_TO_PERIPH_BY_SRC = 0x00000007U +} DMA_TransDirection; + +/** + * @brief Address increase configuration. Peripherals can only be set to unaltered, memory can be set to two mode. + */ +typedef enum { + DMA_ADDR_UNALTERED = 0x00000000U, + DMA_ADDR_INCREASE = 0x00000001U +} DMA_AddrIncMode; + +/** + * @brief DMA extend handle. + */ +typedef struct _DMA_ExtendHandle { + DMA_ByteOrder srcByteOrder; /**< Master1 is defined for source device, set byteOrder */ + DMA_ByteOrder destByteOrder; /**< Master2 is defined for destination device, set byteOrder */ +} DMA_ExtendHandle; + +/** + * @brief DMA user callback. + */ +typedef struct { + struct { + void (* ChannelFinishCallBack)(void *handle); + void (* ChannelErrorCallBack)(void *handle); + } DMA_CallbackFuns[CHANNEL_MAX_NUM]; +} DMA_UserCallBack; +/** + * @} + */ + +/** + * @defgroup DMA_Reg_Def DMA Register Definition + * @brief Description DMA register mapping structure. + * @{ + */ + +/** + * @brief DMAC interrupt status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ch0_int_stat : 1; /**< Masked interrupt status of channel 0. */ + unsigned int ch1_int_stat : 1; /**< Masked interrupt status of channel 1. */ + unsigned int ch2_int_stat : 1; /**< Masked interrupt status of channel 2. */ + unsigned int ch3_int_stat : 1; /**< Masked interrupt status of channel 3. */ + unsigned int reserved0 : 28; + } BIT; +} volatile DMAC_INT_STAT_REG; + +/** + * @brief DMAC transfer completion interrupt status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ch0_int_tc_stat : 1; /**< Masked transfer completion interrupt status of channel 0. */ + unsigned int ch1_int_tc_stat : 1; /**< Masked transfer completion interrupt status of channel 1. */ + unsigned int ch2_int_tc_stat : 1; /**< Masked transfer completion interrupt status of channel 2. */ + unsigned int ch3_int_tc_stat : 1; /**< Masked transfer completion interrupt status of channel 3. */ + unsigned int reserved0 : 28; + } BIT; +} volatile DMAC_INT_TC_STAT_REG; + +/** + * @brief DMAC transfer completion interrupt clear register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ch0_int_tc_clr : 1; /**< Clear the channel 0 transfer completion interrupt. */ + unsigned int ch1_int_tc_clr : 1; /**< Clear the channel 1 transfer completion interrupt. */ + unsigned int ch2_int_tc_clr : 1; /**< Clear the channel 2 transfer completion interrupt. */ + unsigned int ch3_int_tc_clr : 1; /**< Clear the channel 3 transfer completion interrupt. */ + unsigned int reserved1 : 28; + } BIT; +} volatile DMAC_INT_TC_CLR_REG; + +/** + * @brief DMAC error interrupt status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ch0_int_err_stat : 1; /**< Masked error interrupt status of channel 0. */ + unsigned int ch1_int_err_stat : 1; /**< Masked error interrupt status of channel 1. */ + unsigned int ch2_int_err_stat : 1; /**< Masked error interrupt status of channel 2. */ + unsigned int ch3_int_err_stat : 1; /**< Masked error interrupt status of channel 3. */ + unsigned int reserved0 : 28; + } BIT; +} volatile DMAC_INT_ERR_STAT_REG; + +/** + * @brief DMAC error interrupt clear register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ch0_int_err_clr : 1; /**< Clear channel 0 error interrupt. */ + unsigned int ch1_int_err_clr : 1; /**< Clear channel 1 error interrupt. */ + unsigned int ch2_int_err_clr : 1; /**< Clear channel 2 error interrupt. */ + unsigned int ch3_int_err_clr : 1; /**< Clear channel 3 error interrupt. */ + unsigned int reserved0 : 28; + } BIT; +} volatile DMAC_INT_ERR_CLR_REG; + +/** + * @brief DMAC raw transfer completion interrupt register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ch0_raw_int_tc : 1; /**< Raw transfer completion interrupt status of channel 0. */ + unsigned int ch1_raw_int_tc : 1; /**< Raw transfer completion interrupt status of channel 1. */ + unsigned int ch2_raw_int_tc : 1; /**< Raw transfer completion interrupt status of channel 2. */ + unsigned int ch3_raw_int_tc : 1; /**< Raw transfer completion interrupt status of channel 3. */ + unsigned int reserved0 : 28; + } BIT; +} volatile DMAC_RAW_INT_TC_STAT_REG; + +/** + * @brief DMAC raw error interrupt register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ch0_raw_int_err : 1; /**< Raw error interrupt status of channel 0. */ + unsigned int ch1_raw_int_err : 1; /**< Raw error interrupt status of channel 1. */ + unsigned int ch2_raw_int_err : 1; /**< Raw error interrupt status of channel 2. */ + unsigned int ch3_raw_int_err : 1; /**< Raw error interrupt status of channel 3. */ + unsigned int reserved0 : 28; + } BIT; +} volatile DMAC_RAW_INT_ERR_STAT_REG; + +/** + * @brief DMAC channel enable status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ch0_enabled : 1; /**< Channel 0 enable status. */ + unsigned int ch1_enabled : 1; /**< Channel 1 enable status. */ + unsigned int ch2_enabled : 1; /**< Channel 2 enable status. */ + unsigned int ch3_enabled : 1; /**< Channel 3 enable status. */ + unsigned int reserved0 : 28; + } BIT; +} volatile DMAC_ENABLED_CHNS_REG; + +/** + * @brief DMAC software burst transfer request register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int soft_breq : 16; /**< Software control the generation of DMA burst transfer request. */ + unsigned int reserved0 : 16; + } BIT; +} volatile DMAC_SOFT_BREQ_REG; + +/** + * @brief DMAC software single transfer request register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int soft_sreq : 16; /**< Software control the generation of DMA single transfer request. */ + unsigned int reserved0 : 16; + } BIT; +} volatile DMAC_SOFT_SREQ_REG; + +/** + * @brief DMAC software last burst request register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int soft_lbreq : 16; /**< Software initiate a last burst request. */ + unsigned int reserved0 : 16; + } BIT; +} volatile DMAC_SOFT_LBREQ_REG; + +/** + * @brief DMAC software last single request register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int soft_lsreq : 16; /**< Software initiate a last single request. */ + unsigned int reserved0 : 16; + } BIT; +} volatile DMAC_SOFT_LSREQ_REG; + +/** + * @brief DMAC parameter configuration register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int dmac_enable : 1; /**< DMA controller enable. */ + unsigned int m1_endianness : 1; /**< Master 1 byte sequence configuration. */ + unsigned int m2_endianness : 1; /**< Master 2 byte sequence configuration. */ + unsigned int reserved0 : 29; + } BIT; +} volatile DMAC_CONFIG_REG; + +/** + * @brief DMAC request line synchronization enable. + */ +typedef union { + unsigned int reg; + struct { + unsigned int dmac_sync : 16; /**< Control whether the request line needs to be synchronized.. */ + unsigned int reserved0 : 16; + } BIT; +} volatile DMAC_SYNC_REG; + +/** + * @brief Source address register of DMA channel n (n = 0, 1, 2, 3). + */ +typedef union { + unsigned int reg; + struct { + unsigned int src_addr : 32; /**< DMA source address. */ + } BIT; +} volatile DMAC_Cn_SRC_ADDR_REG; + +/** + * @brief Destination address register of DMA channel n (n = 0, 1, 2, 3). + */ +typedef union { + unsigned int reg; + struct { + unsigned int dest_addr : 32; /**< DMA destination address. */ + } BIT; +} volatile DMAC_Cn_DEST_ADDR_REG; + +/** + * @brief Linked list information register for DMA channel n (n = 0, 1, 2, 3). + */ +typedef union { + unsigned int reg; + struct { + unsigned int ll_master : 1; /**< Master of the next linked list node : Master1 or Master2. */ + unsigned int reserved0 : 1; + unsigned int ll_item : 30; /**< Address of the next linked list node. */ + } BIT; +} volatile DMAC_Cn_LLI_REG; + +/** + * @brief DMA channel n (n = 0, 1, 2, 3) control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int trans_size : 12; /**< Length of the DMA transfer, provided that the DMAC flow controller. */ + unsigned int sbsize : 3; /**< Burst length of the source device. */ + unsigned int dbsize : 3; /**< Burst length of the destination device. */ + unsigned int swidth : 3; /**< Transfer bit width of the source device, + which cannot be greater than Master bit width. */ + unsigned int dwidth : 3; /**< Transfer bit width of the destination device, + which cannot be greater than Master bit width. */ + unsigned int src_select : 1; /**< Set Master for accessing the source device : Master 1 or Master 2. */ + unsigned int dest_select : 1; /**< Set Master for accessing the destination device : Master 1 or Master 2. */ + unsigned int src_incr : 1; /**< Set the incremental mode of the source address. */ + unsigned int dest_incr : 1; /**< Set the incremental mode of the destination address. */ + unsigned int reserved0 : 3; + unsigned int int_tc_enable : 1; /**< Transfer completion interrupt enable. */ + } BIT; +} volatile DMAC_Cn_CONTROL_REG; + +/** + * @brief DMA channel n (n = 0, 1, 2, 3) configuration register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ch_en : 1; /**< Channel enable. */ + unsigned int src_periph : 4; /**< Source device, ignore this field if memory device. */ + unsigned int reserved0 : 1; + unsigned int dest_periph : 4; /**< Destination device, ignore this field if memory device. */ + unsigned int reserved1 : 1; + unsigned int flow_ctrl : 3; /**< Flow control and transmission Type. */ + unsigned int err_int_msk : 1; /**< Error interrupt mask flag. */ + unsigned int tc_int_msk : 1; /**< Transfer completion interrupt mask flag. */ + unsigned int ch_lock : 1; /**< Lock transmission enable on the bus. */ + unsigned int ch_active : 1; /**< Whether the data in the channel FIFO. */ + unsigned int ch_halt : 1; /**< Whether ignore DMA requests. */ + unsigned int reserved2 : 13; + } BIT; +} volatile DMAC_Cn_CONFIG_REG; + +/** + * @brief DMA register mapping structure. + */ +typedef struct { + DMAC_INT_STAT_REG DMAC_INT_STAT; /**< DMAC interrupt status register, + Offset address: 0x00000000U. */ + DMAC_INT_TC_STAT_REG DMAC_INT_TC_STAT; /**< DMAC transfer completion interrupt status register, + Offset address: 0x00000004U. */ + DMAC_INT_TC_CLR_REG DMAC_INT_TC_CLR; /**< DMAC transfer completion interrupt clear register, + Offset address: 0x00000008U. */ + DMAC_INT_ERR_STAT_REG DMAC_INT_ERR_STAT; /**< DMAC error interrupt status register, + Offset address: 0x0000000CU. */ + DMAC_INT_ERR_CLR_REG DMAC_INT_ERR_CLR; /**< DMAC error interrupt clear register, + Offset address: 0x00000010U. */ + DMAC_RAW_INT_TC_STAT_REG DMAC_RAW_INT_TC_STAT; /**< DMAC raw transfer completion interrupt register, + Offset address: 0x00000014U. */ + DMAC_RAW_INT_ERR_STAT_REG DMAC_RAW_INT_ERR_STAT; /**< DMAC raw error interrupt register, + Offset address: 0x00000018U. */ + DMAC_ENABLED_CHNS_REG DMAC_ENABLED_CHNS; /**< DMAC channel enable status register, + Offset address: 0x0000001CU. */ + DMAC_SOFT_BREQ_REG DMAC_SOFT_BREQ; /**< DMAC software burst transfer request register, + Offset address: 0x00000020U. */ + DMAC_SOFT_SREQ_REG DMAC_SOFT_SREQ; /**< DMAC software single transfer request register, + Offset address: 0x00000024U. */ + DMAC_SOFT_LBREQ_REG DMAC_SOFT_LBREQ; /**< DMAC software last burst request register, + Offset address: 0x00000028U. */ + DMAC_SOFT_LSREQ_REG DMAC_SOFT_LSREQ; /**< DMAC software last single request register, + Offset address: 0x0000002CU. */ + DMAC_CONFIG_REG DMAC_CONFIG; /**< DMAC parameter configuration register, + Offset address: 0x00000030U. */ + DMAC_SYNC_REG DMAC_SYNC; /**< DMAC request line synchronization enable, + Offset address: 0x00000034U. */ + char space0[200]; + DMAC_Cn_SRC_ADDR_REG DMAC_C0_SRC_ADDR; /**< Source address register of DMA channel 0, + Offset address: 0x00000100U. */ + DMAC_Cn_DEST_ADDR_REG DMAC_C0_DEST_ADDR; /**< Destination address register of DMA channel 0, + Offset address: 0x00000104U. */ + DMAC_Cn_LLI_REG DMAC_C0_LLI; /**< Linked list information register for DMA channel 0, + Offset address: 0x00000108U. */ + DMAC_Cn_CONTROL_REG DMAC_C0_CONTROL; /**< DMA channel 0 control register, + Offset address: 0x0000010CU. */ + DMAC_Cn_CONFIG_REG DMAC_C0_CONFIG; /**< DMA channel 0 configuration register, + Offset address: 0x00000110U. */ + char space1[12]; + DMAC_Cn_SRC_ADDR_REG DMAC_C1_SRC_ADDR; /**< Source address register of DMA channel 1, + Offset address: 0x00000120U. */ + DMAC_Cn_DEST_ADDR_REG DMAC_C1_DEST_ADDR; /**< Destination address register of DMA channel 1, + Offset address: 0x00000124U. */ + DMAC_Cn_LLI_REG DMAC_C1_LLI; /**< Linked list information register for DMA channel 1, + Offset address: 0x00000128U. */ + DMAC_Cn_CONTROL_REG DMAC_C1_CONTROL; /**< DMA channel 1 control register, + Offset address: 0x0000012CU. */ + DMAC_Cn_CONFIG_REG DMAC_C1_CONFIG; /**< DMA channel 1 configuration register, + Offset address: 0x00000130U. */ + char space2[12]; + DMAC_Cn_SRC_ADDR_REG DMAC_C2_SRC_ADDR; /**< Source address register of DMA channel 2, + Offset address: 0x00000140U. */ + DMAC_Cn_DEST_ADDR_REG DMAC_C2_DEST_ADDR; /**< Destination address register of DMA channel 2, + Offset address: 0x00000144U. */ + DMAC_Cn_LLI_REG DMAC_C2_LLI; /**< Linked list information register for DMA channel 2, + Offset address: 0x00000148U. */ + DMAC_Cn_CONTROL_REG DMAC_C2_CONTROL; /**< DMA channel 2 control register, + Offset address: 0x0000014CU. */ + DMAC_Cn_CONFIG_REG DMAC_C2_CONFIG; /**< DMA channel 2 configuration register, + Offset address: 0x00000150U. */ + char space3[12]; + DMAC_Cn_SRC_ADDR_REG DMAC_C3_SRC_ADDR; /**< Source address register of DMA channel 3, + Offset address: 0x00000160U. */ + DMAC_Cn_DEST_ADDR_REG DMAC_C3_DEST_ADDR; /**< Destination address register of DMA channel 3, + Offset address: 0x00000164U. */ + DMAC_Cn_LLI_REG DMAC_C3_LLI; /**< Linked list information register for DMA channel 3, + Offset address: 0x00000168U. */ + DMAC_Cn_CONTROL_REG DMAC_C3_CONTROL; /**< DMA channel 3 control register, + Offset address: 0x0000016CU. */ + DMAC_Cn_CONFIG_REG DMAC_C3_CONFIG; /**< DMA channel 3 configuration register, + Offset address: 0x00000170U. */ +} volatile DMA_RegStruct; + +/** + * @brief Channel register mapping structure. + */ +typedef struct { + DMAC_Cn_SRC_ADDR_REG DMAC_Cn_SRC_ADDR; /**< Source address register of DMA channel. */ + DMAC_Cn_DEST_ADDR_REG DMAC_Cn_DEST_ADDR; /**< Destination address register of DMA channel. */ + DMAC_Cn_LLI_REG DMAC_Cn_LLI; /**< Linked list information register for DMA channel. */ + DMAC_Cn_CONTROL_REG DMAC_Cn_CONTROL; /**< DMA channel control register. */ + DMAC_Cn_CONFIG_REG DMAC_Cn_CONFIG; /**< DMA channel configuration register. */ +} volatile DMA_ChannelRegStruct; + +/** + * @brief DMA linked list structure. + */ +typedef struct _DMA_LinkList { + unsigned int srcAddr; /**< Source device start address. */ + unsigned int destAddr; /**< Destination device start address. */ + struct _DMA_LinkList *lliNext; /**< Pointer to the next node. */ + DMAC_Cn_CONTROL_REG control; /**< Channel parameters configured for the node. */ +} DMA_LinkList; + +/** + * @brief A large amount of block data needs to be splited. Split functions need to transfer the following structure. + */ +typedef struct { + unsigned int srcAddr; /**< Source device start address. */ + unsigned int destAddr; /**< Destination device start address. */ + unsigned int srcIn; /**< Source address single increment size. */ + unsigned int destIn; /**< destnation address single increment size. */ + unsigned int chnParam; /**< Channel parameters configured for the splited node. */ + unsigned int totalSize; /**< Total amount of block data. */ +} DMA_SplitParam; + +/** + * @brief Struct of DMA peripheral request line and system register multiplexing. + */ +typedef struct { + DMA_ReqLineVal reqLineVal; /**< DMA peripheral request line. */ + DMA_SysctrlSet sysctrVal; /**< Configuration value definition of the peripheral multiplexing. */ + unsigned int shiftLeft; /**< Left shift of peripheral multiplexing configuration value. */ +} DMA_PeriphReq; +/** + * @} + */ + + +/** + * @brief Check DMA channel num parameter. + * @param channel The number of channel. + * @retval bool + */ +static inline bool IsDmaChannelNum(DMA_ChannelNum channel) +{ + if ((channel == DMA_CHANNEL_ZERO) || (channel == DMA_CHANNEL_ONE) || + (channel == DMA_CHANNEL_TWO) || (channel == DMA_CHANNEL_THREE)) { + return true; + } + return false; +} + +/** + * @brief Check DMA channel transfer width. + * @param width DMA transfer width. + * @retval bool + */ +static inline bool IsDmaWidth(DMA_TransmisWidth width) +{ + if ((width == DMA_TRANSWIDTH_BYTE) || + (width == DMA_TRANSWIDTH_HALFWORD) || + (width == DMA_TRANSWIDTH_WORD)) { + return true; + } + return false; +} + +/** + * @brief Check DMA channel burst length. + * @param burstLength DMA transfer burst length. + * @retval bool + */ +static inline bool IsDmaBurstLength(DMA_BurstLength burstLength) +{ + if ((burstLength == DMA_BURST_LENGTH_1) || (burstLength == DMA_BURST_LENGTH_4) || + (burstLength == DMA_BURST_LENGTH_8) || (burstLength == DMA_BURST_LENGTH_16) || + (burstLength == DMA_BURST_LENGTH_32) || (burstLength == DMA_BURST_LENGTH_64) || + (burstLength == DMA_BURST_LENGTH_128) || (burstLength == DMA_BURST_LENGTH_256)) { + return true; + } + return false; +} + +/** + * @brief Check DMA type of byte order. + * @param byteOrder DMA master1/master2 byte order. + * @retval bool + */ +static inline bool IsDmaByteOrder(DMA_ByteOrder byteOrder) +{ + return (byteOrder == DMA_BYTEORDER_SMALLENDIAN) || (byteOrder == DMA_BYTEORDER_BIGENDIAN); +} + +/** + * @brief Check DMA type of address change. + * @param byteOrder DMA source/destination address change type. + * @retval bool + */ +static inline bool IsDmaAddrMode(DMA_AddrIncMode addrMode) +{ + return (addrMode == DMA_ADDR_UNALTERED) || (addrMode == DMA_ADDR_INCREASE); +} + +/** + * @brief Check DMA type of direction. + * @param direction DMA transmfer direction. + * @retval bool + */ +static inline bool IsDmaDirection(DMA_TransDirection direction) +{ + if ((direction == DMA_MEMORY_TO_MEMORY_BY_DMAC) || (direction == DMA_MEMORY_TO_PERIPH_BY_DMAC) || + (direction == DMA_PERIPH_TO_MEMORY_BY_DMAC) || (direction == DMA_PERIPH_TO_PERIPH_BY_DMAC) || + (direction == DMA_PERIPH_TO_PERIPH_BY_DES) || (direction == DMA_MEMORY_TO_PERIPH_BY_DES) || + (direction == DMA_PERIPH_TO_MEMORY_BY_SRC) || (direction == DMA_PERIPH_TO_PERIPH_BY_SRC)) { + return true; + } + return false; +} +/** + * @brief Check DMA num of request peripheral. + * @param reqPeriph peripherals supported by the DMA. + * @retval bool + */ +static inline bool IsDmaReqPeriph(DMA_RequestLineNum reqPeriph) +{ + return (reqPeriph >= DMA_REQUEST_I2C_RX) && (reqPeriph <= DMA_REQUEST_MEM); +} + +/** + * @brief Check whether the address is valid. + * @param address Address for the DMA to transfer data. + * @retval bool + */ +static inline bool IsDmaValidAddress(unsigned long long address) +{ + return (address >= SRAM_START && address <= SRAM_END) || (address >= REGISTER_START && address <= REGISTER_END); +} + +/** + * @brief Check whether the master is valid. + * @param master Master of DMA. + * @retval bool + */ +static inline bool IsDmaMaster(DMA_Master master) +{ + return (master == DMA_MASTER1) || (master == DMA_MASTER2); +} + +/** + * @brief DMA configurate the byte order of master1. + * @param dmax DMA register base address. + * @param byteOrder DMA byte order. + * @retval None. + */ +static inline void DCL_DMA_SetMast1ByteOrder(DMA_RegStruct * const dmax, DMA_ByteOrder byteOrder) +{ + DMA_ASSERT_PARAM(IsDMAInstance(dmax)); + DMA_PARAM_CHECK_NO_RET(IsDmaByteOrder(byteOrder)); + dmax->DMAC_CONFIG.BIT.m1_endianness = byteOrder; +} + +/** + * @brief DMA configurate the byte order of master2. + * @param dmax DMA register base address. + * @param byteOrder DMA byte order. + * @retval None. + */ +static inline void DCL_DMA_SetMast2ByteOrder(DMA_RegStruct * const dmax, DMA_ByteOrder byteOrder) +{ + DMA_ASSERT_PARAM(IsDMAInstance(dmax)); + DMA_PARAM_CHECK_NO_RET(IsDmaByteOrder(byteOrder)); + dmax->DMAC_CONFIG.BIT.m2_endianness = byteOrder; +} + +/** + * @brief DMA configurate the direction. + * @param dmaChannelx DMA channel register base address. + * @param direction Direction of channel. + * @retval None. + */ +static inline void DCL_DMA_SetDirection(DMA_ChannelRegStruct * const dmaChannelx, DMA_TransDirection direction) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(IsDmaDirection(direction)); + dmaChannelx->DMAC_Cn_CONFIG.BIT.flow_ctrl = direction; +} + +/** + * @brief DMA configurate the address of source. + * @param dmaChannelx DMA channel register base address. + * @param srcAddr Address of source. + * @retval None. + */ +static inline void DCL_DMA_SetSrcAddr(DMA_ChannelRegStruct * const dmaChannelx, unsigned int srcAddr) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(IsDmaValidAddress(srcAddr)); + dmaChannelx->DMAC_Cn_SRC_ADDR.BIT.src_addr = srcAddr; +} + +/** + * @brief DMA configurate the address of destnation. + * @param dmaChannelx DMA channel register base address. + * @param destAddr Address of destnation. + * @retval None. + */ +static inline void DCL_DMA_SetDestAddr(DMA_ChannelRegStruct * const dmaChannelx, unsigned int destAddr) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(IsDmaValidAddress(destAddr)); + dmaChannelx->DMAC_Cn_DEST_ADDR.BIT.dest_addr = destAddr; +} + +/** + * @brief DMA configurate the address mode of source. + * @param dmaChannelx DMA channel register base address. + * @param srcAddrInc The address mode of source. + * @retval None. + */ +static inline void DCL_DMA_SetSrcAddrMode(DMA_ChannelRegStruct * const dmaChannelx, DMA_AddrIncMode srcAddrInc) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(IsDmaAddrMode(srcAddrInc)); + dmaChannelx->DMAC_Cn_CONTROL.BIT.src_incr = srcAddrInc; +} + +/** + * @brief DMA configurate the address mode of destnation. + * @param dmaChannelx DMA channel register base address. + * @param destAddrInc The address mode of destnation. + * @retval None. + */ +static inline void DCL_DMA_SetDestAddrMode(DMA_ChannelRegStruct * const dmaChannelx, DMA_AddrIncMode destAddrInc) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(IsDmaAddrMode(destAddrInc)); + dmaChannelx->DMAC_Cn_CONTROL.BIT.dest_incr = destAddrInc; +} + +/** + * @brief DMA configurate the bit width of source. + * @param dmaChannelx DMA channel register base address. + * @param srcWidth The bit width of source. + * @retval None. + */ +static inline void DCL_DMA_SetSrcWidth(DMA_ChannelRegStruct * const dmaChannelx, DMA_TransmisWidth srcWidth) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(IsDmaWidth(srcWidth)); + dmaChannelx->DMAC_Cn_CONTROL.BIT.swidth = srcWidth; +} + +/** + * @brief DMA configurate the bit width of destnation. + * @param dmaChannelx DMA channel register base address. + * @param destWidth The bit width of destnation. + * @retval None. + */ +static inline void DCL_DMA_SetDestWidth(DMA_ChannelRegStruct * const dmaChannelx, DMA_TransmisWidth destWidth) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(IsDmaWidth(destWidth)); + dmaChannelx->DMAC_Cn_CONTROL.BIT.dwidth = destWidth; +} + +/** + * @brief DMA configurate the burst size of source. + * @param dmaChannelx DMA channel register base address. + * @param srcBurst The burst size of source. + * @retval None. + */ +static inline void DCL_DMA_SetSrcBurst(DMA_ChannelRegStruct * const dmaChannelx, DMA_BurstLength srcBurst) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(IsDmaBurstLength(srcBurst)); + dmaChannelx->DMAC_Cn_CONTROL.BIT.sbsize = srcBurst; +} + +/** + * @brief DMA configurate the burst size of destnation. + * @param dmaChannelx DMA channel register base address. + * @param destBurst The burst size of destnation. + * @retval None. + */ +static inline void DCL_DMA_SetDestBurst(DMA_ChannelRegStruct * const dmaChannelx, DMA_BurstLength destBurst) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(IsDmaBurstLength(destBurst)); + dmaChannelx->DMAC_Cn_CONTROL.BIT.dbsize = destBurst; +} + +/** + * @brief DMA configurate the transfer size. + * @param dmaChannelx DMA channel register base address. + * @param dataLength The transfer size. + * @retval None. + */ +static inline void DCL_DMA_SetTransferSize(DMA_ChannelRegStruct * const dmaChannelx, unsigned int dataLength) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(dataLength <= 0xFFF); + dmaChannelx->DMAC_Cn_CONTROL.BIT.trans_size = dataLength; +} + +/** + * @brief Enable channel completion interrupt. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_EnableIT(DMA_ChannelRegStruct * const dmaChannelx) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + dmaChannelx->DMAC_Cn_CONFIG.BIT.err_int_msk = BASE_CFG_ENABLE; + dmaChannelx->DMAC_Cn_CONFIG.BIT.tc_int_msk = BASE_CFG_ENABLE; +} + +/** + * @brief Disable channel completion interrupt. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_DisableIT(DMA_ChannelRegStruct * const dmaChannelx) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + dmaChannelx->DMAC_Cn_CONFIG.BIT.err_int_msk = BASE_CFG_DISABLE; + dmaChannelx->DMAC_Cn_CONFIG.BIT.tc_int_msk = BASE_CFG_DISABLE; +} + +/** + * @brief Enables the channel to start transmission. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_EnableChannel(DMA_ChannelRegStruct * const dmaChannelx) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + dmaChannelx->DMAC_Cn_CONFIG.BIT.ch_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable the channel to start transmission. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_DisableChannel(DMA_ChannelRegStruct * const dmaChannelx) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + dmaChannelx->DMAC_Cn_CONFIG.BIT.ch_en = BASE_CFG_DISABLE; +} + +/** + * @brief Enable the DMA controller. + * @param dmax DMA register base address. + * @retval None. + */ +static inline void DCL_DMA_EnableDMAController(DMA_RegStruct * const dmax) +{ + DMA_ASSERT_PARAM(IsDMAInstance(dmax)); + dmax->DMAC_CONFIG.BIT.dmac_enable = BASE_CFG_ENABLE; +} + +/** + * @brief Disable the DMA controller. + * @param dmax DMA register base address. + * @retval None. + */ +static inline void DCL_DMA_DisableDMAController(DMA_RegStruct * const dmax) +{ + DMA_ASSERT_PARAM(IsDMAInstance(dmax)); + dmax->DMAC_CONFIG.BIT.dmac_enable = BASE_CFG_DISABLE; +} + +/** + * @brief Clear the transfer completion interrupt. + * @param dmax DMA register base address. + * @param channel channel of DMA. + * @retval None. + */ +static inline void DCL_DMA_ClearTransferCompleteInt(DMA_RegStruct * const dmax, DMA_ChannelNum channel) +{ + DMA_ASSERT_PARAM(IsDMAInstance(dmax)); + DMA_PARAM_CHECK_NO_RET(IsDmaChannelNum(channel)); + dmax->DMAC_INT_TC_CLR.reg |= (1U << (unsigned int)channel); +} + +/** + * @brief Clear the transfer error interrupt. + * @param dmax DMA register base address. + * @param channel channel of DMA. + * @retval None. + */ +static inline void DCL_DMA_ClearTransferErrorInt(DMA_RegStruct * const dmax, DMA_ChannelNum channel) +{ + DMA_ASSERT_PARAM(IsDMAInstance(dmax)); + DMA_PARAM_CHECK_NO_RET(IsDmaChannelNum(channel)); + dmax->DMAC_INT_ERR_CLR.reg |= (1U << (unsigned int)channel); +} + +/** + * @brief Enable request line synchronization. + * @param dmax DMA register base address. + * @retval None. + */ +static inline void DCL_DMA_EnableRequestSync(DMA_RegStruct * const dmax) +{ + DMA_ASSERT_PARAM(IsDMAInstance(dmax)); + dmax->DMAC_SYNC.reg = 0x00; +} + +/** + * @brief Disable request line synchronization. + * @param dmax DMA register base address. + * @retval None. + */ +static inline void DCL_DMA_DisableRequestSync(DMA_RegStruct * const dmax) +{ + DMA_ASSERT_PARAM(IsDMAInstance(dmax)); + dmax->DMAC_SYNC.reg = 0xFF; +} + +/** + * @brief Clearing Channel Configuration Parameters. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_ClearChannalParam(DMA_ChannelRegStruct * const dmaChannelx) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + dmaChannelx->DMAC_Cn_CONFIG.reg = 0x00; +} + +/** + * @brief Configure the source master interface of the channel. + * @param dmaChannelx DMA channel register base address. + * @param master Master interface type of DMA. + * @retval None. + */ +static inline void DCL_DMA_SetSrcMasterChannal(DMA_ChannelRegStruct * const dmaChannelx, DMA_Master master) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(IsDmaMaster(master)); + dmaChannelx->DMAC_Cn_CONTROL.BIT.src_select = master; +} + +/** + * @brief Configure the destination master interface of the channel. + * @param dmaChannelx DMA channel register base address. + * @param master Master interface type of DMA. + * @retval None. + */ +static inline void DCL_DMA_SetDestMasterChannal(DMA_ChannelRegStruct * const dmaChannelx, DMA_Master master) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(IsDmaMaster(master)); + dmaChannelx->DMAC_Cn_CONTROL.BIT.dest_select = master; +} + +/** + * @brief Interrupt generated when channel transfer. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_ChannalEnableInt(DMA_ChannelRegStruct * const dmaChannelx) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + dmaChannelx->DMAC_Cn_CONTROL.BIT.int_tc_enable = BASE_CFG_ENABLE; +} + +/** + * @brief No interrupt is generated after the channel transfer. + * @param dmaChannelx DMA channel register base address. + * @retval None. + */ +static inline void DCL_DMA_ChannalDisableInt(DMA_ChannelRegStruct * const dmaChannelx) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + dmaChannelx->DMAC_Cn_CONTROL.BIT.int_tc_enable = BASE_CFG_DISABLE; +} + +/** + * @brief Obtaining the DMA channel state. + * @param dmax DMA register base address. + * @param channel channel of DMA. + * @retval unsigned int. + */ +static inline unsigned int DCL_DMA_GetChannelState(DMA_RegStruct * const dmax, DMA_ChannelNum channel) +{ + DMA_ASSERT_PARAM(IsDMAInstance(dmax)); + DMA_PARAM_CHECK_WITH_RET(IsDmaChannelNum(channel), BASE_STATUS_ERROR); + unsigned int val = dmax->DMAC_ENABLED_CHNS.reg; + unsigned int ret = (val & (1U << channel)); /* Select the state of the specified channel */ + return ret; +} + +/** + * @brief Obtaining the DMA interrupt state. + * @param dmax DMA register base address. + * @param channel channel of DMA. + * @retval unsigned int. + */ +static inline unsigned int DCL_DMA_GetIntState(DMA_RegStruct * const dmax, DMA_ChannelNum channel) +{ + DMA_ASSERT_PARAM(IsDMAInstance(dmax)); + DMA_PARAM_CHECK_WITH_RET(IsDmaChannelNum(channel), BASE_STATUS_ERROR); + unsigned int val = dmax->DMAC_INT_STAT.reg; + unsigned int ret = (val & (1U << channel)); /* Select the state of the specified interrupt */ + return ret; +} + +/** + * @brief Obtaining the DMA interrupt transfer complete state. + * @param dmax DMA register base address. + * @retval unsigned int. + */ +static inline unsigned int DCL_DMA_GetIntFinsihState(DMA_RegStruct * const dmax) +{ + DMA_ASSERT_PARAM(IsDMAInstance(dmax)); + return dmax->DMAC_INT_TC_STAT.reg; +} + +/** + * @brief Obtaining the DMA interrupt error state. + * @param dmax DMA register base address. + * @retval unsigned int. + */ +static inline unsigned int DCL_DMA_GetIntErrorState(DMA_RegStruct * const dmax) +{ + DMA_ASSERT_PARAM(IsDMAInstance(dmax)); + return dmax->DMAC_INT_ERR_STAT.reg; +} + +/** + * @brief Set the next node information. + * @param dmaChannelx DMA channel register base address. + * @param value Linked list field. + * @retval None. + */ +static inline void DCL_DMA_SetListNextNode(DMA_ChannelRegStruct * const dmaChannelx, unsigned int value) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + DMA_PARAM_CHECK_NO_RET(value < 0xFFFFFFF0); + dmaChannelx->DMAC_Cn_LLI.reg = value; +} + +/** + * @brief Halt DMA channel request. + * @param dmaChannelx DMA channel register base address. + * @retval void. + */ +static inline void DCL_DMA_HaltChannelRequest(DMA_ChannelRegStruct * const dmaChannelx) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + dmaChannelx->DMAC_Cn_CONFIG.BIT.ch_halt = BASE_CFG_ENABLE; +} + +/** + * @brief Allow DMA channel request. + * @param dmaChannelx DMA channel register base address. + * @retval void. + */ +static inline void DCL_DMA_AllowChannelRequest(DMA_ChannelRegStruct * const dmaChannelx) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + dmaChannelx->DMAC_Cn_CONFIG.BIT.ch_halt = BASE_CFG_DISABLE; +} + +/** + * @brief Allow DMA channel request. + * @param dmaChannelx DMA channel register base address. + * @retval unsigned int, 1: FIFO has data, 0: FIFO has not data. + */ +static inline unsigned int DCL_DMA_GetFifoState(DMA_ChannelRegStruct * const dmaChannelx) +{ + DMA_ASSERT_PARAM(IsDMACHXInstance(dmaChannelx)); + return dmaChannelx->DMAC_Cn_CONFIG.BIT.ch_active; +} +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_DMA_IP_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dma/src/dma.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dma/src/dma.c new file mode 100644 index 00000000..54f79763 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/dma/src/dma.c @@ -0,0 +1,769 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file dma.c + * @author MCU Driver Team + * @brief DMA module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the DMA. + * + Initialization and de-initialization functions. + * + Start DMA transfer with interrupt mode. + * + Start DMA transfer without interrupt mode. + * + Stop DMA transfer and query the state of DMA. + * + Interrupt callback function and user registration function. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "dma.h" + +static DMA_LinkList g_listTable[LISTNODE_MAX] = {0}; +static unsigned int g_listIndex = 0; + +static DMA_PeriphReq g_periphReqTable[] = { + {DMA_REQLINEVAL_0, DMA_SYSCTRLSET_0, 0}, /* DMA_REQUEST_I2C_RX, system registers shift left 0 bit set */ + {DMA_REQLINEVAL_1, DMA_SYSCTRLSET_0, 1}, /* DMA_REQUEST_I2C_TX, system registers shift left 1 bit set */ + {DMA_REQLINEVAL_2, DMA_SYSCTRLSET_0, 0}, /* DMA_REQUEST_UART0_RX, system registers no use */ + {DMA_REQLINEVAL_3, DMA_SYSCTRLSET_0, 0}, /* DMA_REQUEST_UART0_TX, system registers no use */ + {DMA_REQLINEVAL_4, DMA_SYSCTRLSET_0, 0}, /* DMA_REQUEST_UART1_RX, system registers no use */ + {DMA_REQLINEVAL_5, DMA_SYSCTRLSET_0, 5}, /* DMA_REQUEST_UART1_TX, system registers shift left 5 bit set */ + {DMA_REQLINEVAL_6, DMA_SYSCTRLSET_1, 6}, /* DMA_REQUEST_SPI_RX, system registers shift left 6 bits set */ + {DMA_REQLINEVAL_7, DMA_SYSCTRLSET_1, 7}, /* DMA_REQUEST_SPI_TX, system registers shift left 7 bits set */ + {DMA_REQLINEVAL_8, DMA_SYSCTRLSET_0, 8}, /* DMA_REQUEST_CAPM0, system registers shift left 8 bits set */ + {DMA_REQLINEVAL_9, DMA_SYSCTRLSET_0, 9}, /* DMA_REQUEST_CAPM1, system registers shift left 9 bits set */ + {DMA_REQLINEVAL_10, DMA_SYSCTRLSET_0, 10}, /* DMA_REQUEST_CAPM2, system registers shift left 10 bits set */ + {DMA_REQLINEVAL_11, DMA_SYSCTRLSET_0, 11}, /* DMA_REQUEST_ADC0, system registers shift left 11 bits set */ + {DMA_REQLINEVAL_12, DMA_SYSCTRLSET_0, 12}, /* DMA_REQUEST_ADC1, system registers shift left 12 bits set */ + {DMA_REQLINEVAL_13, DMA_SYSCTRLSET_0, 13}, /* DMA_REQUEST_ADC2, system registers shift left 13 bits set */ + {DMA_REQLINEVAL_14, DMA_SYSCTRLSET_0, 14}, /* DMA_REQUEST_TIMER0, system registers shift left 14 bits set */ + {DMA_REQLINEVAL_15, DMA_SYSCTRLSET_0, 15}, /* DMA_REQUEST_TIMER1, system registers shift left 15 bits set */ + {DMA_REQLINEVAL_6, DMA_SYSCTRLSET_0, 6}, /* DMA_REQUEST_UART2_RX, system registers shift left 6 bits set */ + {DMA_REQLINEVAL_7, DMA_SYSCTRLSET_0, 7}, /* DMA_REQUEST_UART2_TX, system registers shift left 7 bits set */ + {DMA_REQLINEVAL_5, DMA_SYSCTRLSET_1, 5}, /* DMA_REQUEST_APT8, system registers shift left 5 bits set */ + {DMA_REQLINEVAL_8, DMA_SYSCTRLSET_1, 8}, /* DMA_REQUEST_APT0, system registers shift left 8 bits set */ + {DMA_REQLINEVAL_9, DMA_SYSCTRLSET_1, 9}, /* DMA_REQUEST_APT1, system registers shift left 9 bits set */ + {DMA_REQLINEVAL_10, DMA_SYSCTRLSET_1, 10}, /* DMA_REQUEST_APT2, system registers shift left 10 bits set */ + {DMA_REQLINEVAL_11, DMA_SYSCTRLSET_1, 11}, /* DMA_REQUEST_APT3, system registers shift left 11 bits set */ + {DMA_REQLINEVAL_12, DMA_SYSCTRLSET_1, 12}, /* DMA_REQUEST_APT4, system registers shift left 12 bits set */ + {DMA_REQLINEVAL_13, DMA_SYSCTRLSET_1, 13}, /* DMA_REQUEST_APT5, system registers shift left 13 bits set */ + {DMA_REQLINEVAL_14, DMA_SYSCTRLSET_1, 14}, /* DMA_REQUEST_APT6, system registers shift left 14 bits set */ + {DMA_REQLINEVAL_15, DMA_SYSCTRLSET_1, 15}, /* DMA_REQUEST_APT7, system registers shift left 15 bits set */ + {DMA_REQLINEVAL_0, DMA_SYSCTRLSET_1, 0}, /* DMA_REQUEST_TIMER2, system registers shift left 0 bit set */ + {DMA_REQLINEVAL_1, DMA_SYSCTRLSET_1, 1} /* DMA_REQUEST_TIMER3, system registers shift left 1 bit set */ +}; +static BASE_StatusType DMA_SetChannelAndDirection(DMA_Handle *dmaHandle, unsigned int srcAddr, unsigned int destAddr, + unsigned int dataLength, unsigned int channel); +static BASE_StatusType DMA_SetDirection(DMA_Handle *dmaHandle, unsigned int channel); +static BASE_StatusType DMA_SetChannel(DMA_Handle *dmaHandle, unsigned int srcAddr, unsigned int destAddr, + unsigned int dataLength, unsigned int channel); + +static void DMA_SplitToBlock(DMA_LinkList *node, DMA_SplitParam *split); +/** + * @brief Initialize the DMA hardware controller configuration. + * @param dmaHandle DMA handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_DMA_Init(DMA_Handle *dmaHandle) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + DMA_PARAM_CHECK_WITH_RET(IsDmaByteOrder(dmaHandle->handleEx.srcByteOrder) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaByteOrder(dmaHandle->handleEx.destByteOrder) == true, BASE_STATUS_ERROR); + /* Sets the byte sequence of master1 and master2 */ + dmaHandle->baseAddress->DMAC_CONFIG.BIT.m1_endianness = dmaHandle->handleEx.srcByteOrder; + dmaHandle->baseAddress->DMAC_CONFIG.BIT.m2_endianness = dmaHandle->handleEx.destByteOrder; + dmaHandle->baseAddress->DMAC_CONFIG.BIT.dmac_enable = BASE_CFG_ENABLE; /* Enable the DMAC controller */ + dmaHandle->baseAddress->DMAC_INT_ERR_CLR.reg |= 0x0F; + dmaHandle->baseAddress->DMAC_INT_TC_CLR.reg |= 0x0F; + dmaHandle->baseAddress->DMAC_SYNC.reg = 0x00; + dmaHandle->baseAddress->DMAC_C0_CONFIG.reg = 0x00; + dmaHandle->baseAddress->DMAC_C1_CONFIG.reg = 0x00; + dmaHandle->baseAddress->DMAC_C2_CONFIG.reg = 0x00; + dmaHandle->baseAddress->DMAC_C3_CONFIG.reg = 0x00; + dmaHandle->DMA_Channels[0].channelAddr = DMA_CHANNEL0; /* Setting the base Address of channel 0 registers */ + dmaHandle->DMA_Channels[1].channelAddr = DMA_CHANNEL1; /* Setting the base Address of channel 1 registers */ + dmaHandle->DMA_Channels[2].channelAddr = DMA_CHANNEL2; /* Setting the base Address of channel 2 registers */ + dmaHandle->DMA_Channels[3].channelAddr = DMA_CHANNEL3; /* Setting the base Address of channel 3 registers */ + return BASE_STATUS_OK; +} + +/** + * @brief DeInitialize the DMA, close all channels. + * @param dmaHandle DMA handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_DMA_Deinit(DMA_Handle *dmaHandle) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + dmaHandle->baseAddress->DMAC_INT_ERR_CLR.reg |= 0x0F; + dmaHandle->baseAddress->DMAC_INT_TC_CLR.reg |= 0x0F; + dmaHandle->baseAddress->DMAC_C0_CONFIG.reg = 0x00; + dmaHandle->baseAddress->DMAC_C1_CONFIG.reg = 0x00; + dmaHandle->baseAddress->DMAC_C2_CONFIG.reg = 0x00; + dmaHandle->baseAddress->DMAC_C3_CONFIG.reg = 0x00; + dmaHandle->baseAddress->DMAC_CONFIG.BIT.dmac_enable = BASE_CFG_DISABLE; + /* Clean callback */ + for (unsigned int i = 0; i < CHANNEL_MAX_NUM; i++) { + dmaHandle->userCallBack.DMA_CallbackFuns[i].ChannelFinishCallBack = NULL; + dmaHandle->userCallBack.DMA_CallbackFuns[i].ChannelErrorCallBack = NULL; + } + return BASE_STATUS_OK; +} + +/** + * @brief Return the specified DMA channel state. + * @param dmaHandle DMA handle. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval Channel state: BASE_STATUS_BUSY, BASE_STATUS_OK. + */ +BASE_StatusType HAL_DMA_GetChannelState(DMA_Handle *dmaHandle, unsigned int channel) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + DMA_PARAM_CHECK_WITH_RET(IsDmaChannelNum(channel) == true, BASE_STATUS_ERROR); + unsigned int chns = dmaHandle->baseAddress->DMAC_ENABLED_CHNS.reg; /* Obtains the channel enabling status */ + unsigned int channelStatus = chns & (1 << channel); + if (channelStatus == (uintptr_t)(1 << channel)) { + return BASE_STATUS_BUSY; + } + return BASE_STATUS_OK; +} + +/** + * @brief Modifying DMA channel parameters. + * @param dmaHandle DMA handle. + * @param channelParam DMA specific channel handle. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_DMA_InitChannel(DMA_Handle *dmaHandle, DMA_ChannelParam *channelParam, unsigned int channel) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(channelParam != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + DMA_PARAM_CHECK_WITH_RET(IsDmaDirection(channelParam->direction) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaReqPeriph(channelParam->srcPeriph) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaReqPeriph(channelParam->destPeriph) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaWidth(channelParam->srcWidth) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaWidth(channelParam->destWidth) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaBurstLength(channelParam->srcBurst) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaBurstLength(channelParam->destBurst) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaAddrMode(channelParam->srcAddrInc) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaAddrMode(channelParam->destAddrInc) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaChannelNum(channel) == true, BASE_STATUS_ERROR); + dmaHandle->DMA_Channels[channel].direction = channelParam->direction; + dmaHandle->DMA_Channels[channel].srcPeriph = channelParam->srcPeriph; + dmaHandle->DMA_Channels[channel].destPeriph = channelParam->destPeriph; + dmaHandle->DMA_Channels[channel].srcWidth = channelParam->srcWidth; + dmaHandle->DMA_Channels[channel].destWidth = channelParam->destWidth; + dmaHandle->DMA_Channels[channel].srcBurst = channelParam->srcBurst; + dmaHandle->DMA_Channels[channel].destBurst = channelParam->destBurst; + dmaHandle->DMA_Channels[channel].srcAddrInc = channelParam->srcAddrInc; + dmaHandle->DMA_Channels[channel].destAddrInc = channelParam->destAddrInc; + dmaHandle->DMA_Channels[channel].pHandle = channelParam->pHandle; + return BASE_STATUS_OK; +} + +/** + * @brief Configuring the DMA source device. + * @param dmaHandle DMA handle. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval None. + */ +static void DMA_SetSrcPeriph(DMA_Handle *dmaHandle, unsigned int channel) +{ + unsigned int periphNum = dmaHandle->DMA_Channels[channel].srcPeriph; + if (periphNum >= DMA_REQUEST_MEM) { + return; + } + /* Set the source device channel request line */ + unsigned int reqVal = g_periphReqTable[periphNum].reqLineVal; + unsigned int sysVal = g_periphReqTable[periphNum].sysctrVal; + unsigned int bitNum = g_periphReqTable[periphNum].shiftLeft; + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONFIG.BIT.src_periph = reqVal; + if (periphNum > DMA_REQUEST_UART1_TX) { + SYSCTRL1->DMA_REQ_SEL.reg |= (sysVal << bitNum); + } +} + +/** + * @brief Configuring the DMA destination device. + * @param dmaHandle DMA handle. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval None. + */ +static void DMA_SetDestPeriph(DMA_Handle *dmaHandle, unsigned int channel) +{ + unsigned int periphNum = dmaHandle->DMA_Channels[channel].destPeriph; + if (periphNum >= DMA_REQUEST_MEM) { + return; + } + /* Set the channel request line of the destination device */ + unsigned int reqVal = g_periphReqTable[periphNum].reqLineVal; + unsigned int sysVal = g_periphReqTable[periphNum].sysctrVal; + unsigned int bitNum = g_periphReqTable[periphNum].shiftLeft; + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONFIG.BIT.dest_periph = reqVal; + if (periphNum > DMA_REQUEST_UART1_TX) { + SYSCTRL1->DMA_REQ_SEL.reg |= (sysVal << bitNum); + } +} + +/** + * @brief Configuring the transmission direction of the DMA channel. + * @param dmaHandle DMA handle. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +static BASE_StatusType DMA_SetDirection(DMA_Handle *dmaHandle, unsigned int channel) +{ + unsigned int direction = dmaHandle->DMA_Channels[channel].direction; + DMA_PARAM_CHECK_WITH_RET(IsDmaDirection(direction) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaReqPeriph(dmaHandle->DMA_Channels[channel].srcPeriph) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaReqPeriph(dmaHandle->DMA_Channels[channel].destPeriph) == true, BASE_STATUS_ERROR); + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONFIG.reg = 0x0000; + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONFIG.BIT.flow_ctrl = direction; + switch (direction) { + case DMA_MEMORY_TO_PERIPH_BY_DMAC: + DMA_SetDestPeriph(dmaHandle, channel); + break; + /* The transfer type is peripheral to memory, flow control is controlled by DMAC */ + case DMA_PERIPH_TO_MEMORY_BY_DMAC: + DMA_SetSrcPeriph(dmaHandle, channel); + break; + case DMA_PERIPH_TO_PERIPH_BY_DMAC: + DMA_SetSrcPeriph(dmaHandle, channel); + DMA_SetDestPeriph(dmaHandle, channel); + break; + /* The transfer type is peripheral to peripheral, flow control is controlled by destination periphera */ + case DMA_PERIPH_TO_PERIPH_BY_DES: + DMA_SetSrcPeriph(dmaHandle, channel); + DMA_SetDestPeriph(dmaHandle, channel); + break; + case DMA_MEMORY_TO_PERIPH_BY_DES: + DMA_SetDestPeriph(dmaHandle, channel); + break; + /* The transfer type is peripheral to memory, flow control is controlled by source periphera */ + case DMA_PERIPH_TO_MEMORY_BY_SRC: + DMA_SetSrcPeriph(dmaHandle, channel); + break; + case DMA_PERIPH_TO_PERIPH_BY_SRC: + DMA_SetSrcPeriph(dmaHandle, channel); + DMA_SetDestPeriph(dmaHandle, channel); + break; + default: + break; + } + return BASE_STATUS_OK; +} + +/** + * @brief Calculate the configured value based on the channel configuration parameters. + * @param dmaHandle DMA handle. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval val Calculation result. + */ +static unsigned int DMA_CalControlval(DMA_Handle *dmaHandle, unsigned int channel) +{ + unsigned int val = 0x82000000; /* 0x82000000 indicates src use master1, dest use master2, int_tc_enable is set */ + val |= (dmaHandle->DMA_Channels[channel].srcBurst) << 12; /* Shift left by 12 bits for source burst */ + val |= (dmaHandle->DMA_Channels[channel].destBurst) << 15; /* Shift left by 15 bits for destination burst */ + val |= (dmaHandle->DMA_Channels[channel].srcWidth) << 18; /* Shift left by 18 bits for source width */ + val |= (dmaHandle->DMA_Channels[channel].destWidth) << 21; /* Shift left by 21 bits for destination width */ + val |= (dmaHandle->DMA_Channels[channel].srcAddrInc) << 26; /* Shift left by 26 bits for source address */ + val |= (dmaHandle->DMA_Channels[channel].destAddrInc) << 27; /* Shift left by 27 bits for destination address */ + return val; +} + +/** + * @brief Configuring Segmentation Parameters. + * @param dmaHandle DMA handle. + * @param srcAddr Data source address. + * @param destAddr Data destination address + * @param dataLength Length of data to be transferred. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval None. + */ +static void DMA_ConfigureSplit(DMA_Handle *dmaHandle, unsigned int srcAddr, + unsigned int destAddr, unsigned int dataLength, unsigned int channel) +{ + unsigned int val = DMA_CalControlval(dmaHandle, channel); + DMA_SplitParam split; + split.chnParam = val; /* Setting channel parameters by val */ + split.srcAddr = srcAddr; + split.destAddr = destAddr; + split.srcIn = dmaHandle->DMA_Channels[channel].srcAddrInc * (1 << dmaHandle->DMA_Channels[channel].srcWidth); + split.destIn = dmaHandle->DMA_Channels[channel].destAddrInc * (1 << dmaHandle->DMA_Channels[channel].destWidth); + split.totalSize = dataLength; + DMA_LinkList *head = &(g_listTable[g_listIndex]); + g_listIndex++; + head->lliNext = NULL; + val |= TRANS_BLOCK; /* Set the size of the data to be transferred, TRANS_BLOCK is 4092 */ + head->control.reg = val; + DMA_SplitToBlock(head, &split); + /* After DMA_SplitToBlock return, head->control.reg[31] int_tc_enable is set 0 */ + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONTROL.reg = head->control.reg; + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_LLI.reg = (uintptr_t)(void *)head->lliNext; +} + +/** + * @brief Configuring DMA channel and direction. + * @param dmaHandle DMA handle. + * @param srcAddr Data source address. + * @param destAddr Data destination address + * @param dataLength Length of data to be transferred. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +static BASE_StatusType DMA_SetChannelAndDirection(DMA_Handle *dmaHandle, unsigned int srcAddr, unsigned int destAddr, + unsigned int dataLength, unsigned int channel) +{ + DMA_PARAM_CHECK_WITH_RET(IsDmaValidAddress(srcAddr), BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaValidAddress(destAddr), BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaValidAddress((unsigned long long)srcAddr + (unsigned long long)dataLength), + BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaValidAddress((unsigned long long)destAddr + (unsigned long long)dataLength), + BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaChannelNum(channel) == true, BASE_STATUS_ERROR); + if (HAL_DMA_GetChannelState(dmaHandle, channel) != BASE_STATUS_OK) { + return BASE_STATUS_BUSY; + } + /* Indicates whether to clear the corresponding channel interrupt */ + dmaHandle->baseAddress->DMAC_INT_ERR_CLR.reg |= (1 << channel); + dmaHandle->baseAddress->DMAC_INT_TC_CLR.reg |= (1 << channel); + if (DMA_SetChannel(dmaHandle, srcAddr, destAddr, dataLength, channel) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + /* Setting channel direction */ + if (DMA_SetDirection(dmaHandle, channel) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief Configuring DMA channel transmission parameters. + * @param dmaHandle DMA handle. + * @param srcAddr Data source address. + * @param destAddr Data destination address + * @param dataLength Length of data to be transferred. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +static BASE_StatusType DMA_SetChannel(DMA_Handle *dmaHandle, unsigned int srcAddr, unsigned int destAddr, + unsigned int dataLength, unsigned int channel) +{ + DMA_PARAM_CHECK_WITH_RET(IsDmaWidth(dmaHandle->DMA_Channels[channel].srcWidth) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaWidth(dmaHandle->DMA_Channels[channel].destWidth) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaBurstLength(dmaHandle->DMA_Channels[channel].srcBurst) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaBurstLength(dmaHandle->DMA_Channels[channel].destBurst) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaAddrMode(dmaHandle->DMA_Channels[channel].srcAddrInc) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaAddrMode(dmaHandle->DMA_Channels[channel].destAddrInc) == true, BASE_STATUS_ERROR); + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_SRC_ADDR.reg = srcAddr; + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_DEST_ADDR.reg = destAddr; + /* If the data size is greater than 4095, data needs to be transferred in blocks */ + if (dataLength > TRANSIZE_MAX) { + if (g_listIndex >= LISTNODE_MAX) { + return BASE_STATUS_ERROR; + } + DMA_ConfigureSplit(dmaHandle, srcAddr, destAddr, dataLength, channel); + } else { + unsigned int val = DMA_CalControlval(dmaHandle, channel); + val |= dataLength; + /* Configure the corresponding channel control parameters based on the value */ + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONTROL.reg = val; + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_LLI.reg = 0x00; + } + return BASE_STATUS_OK; +} + +/** + * @brief DMA start data transfer without interrupt enable. + * @param dmaHandle DMA handle. + * @param srcAddr Data source address. + * @param destAddr Data destination address + * @param dataLength Length of data to be transferred + * @param channel DMA channel num @ref DMA_ChannelNum. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_DMA_Start(DMA_Handle *dmaHandle, unsigned int srcAddr, + unsigned int destAddr, unsigned int dataLength, unsigned int channel) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + BASE_StatusType status; + /* Setting channel parameter */ + status = DMA_SetChannelAndDirection(dmaHandle, srcAddr, destAddr, dataLength, channel); + if (status != BASE_STATUS_OK) { + return status; + } + /* Mask completion interrupts and error interrupts, enable channels */ + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONFIG.reg &= ~(0x0000C000); + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONFIG.BIT.ch_en = BASE_CFG_ENABLE; +#ifdef BASE_DEFINE_DMA_QUICKSTART + dmaHandle->DMA_Channels[channel].srcAddr = dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_SRC_ADDR.reg; + dmaHandle->DMA_Channels[channel].destAddr = dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_DEST_ADDR.reg; + dmaHandle->DMA_Channels[channel].controlVal = dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONTROL.reg; + dmaHandle->DMA_Channels[channel].configVal = dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONFIG.reg; +#endif + return BASE_STATUS_OK; +} + +/** + * @brief DMA start data transfer with interrupt enable. + * @param dmaHandle DMA handle. + * @param srcAddr Data source address. + * @param destAddr Data destination address + * @param dataLength Length of data to be transferred + * @param channel DMA channel num @ref DMA_ChannelNum. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_DMA_StartIT(DMA_Handle *dmaHandle, unsigned int srcAddr, + unsigned int destAddr, unsigned int dataLength, unsigned int channel) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + BASE_StatusType status; + /* Setting channel parameter */ + status = DMA_SetChannelAndDirection(dmaHandle, srcAddr, destAddr, dataLength, channel); + if (status != BASE_STATUS_OK) { + return status; + } + /* Set tc_int_msk, err_int_msk, ch_en */ + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONFIG.reg |= 0xC001; +#ifdef BASE_DEFINE_DMA_QUICKSTART + dmaHandle->DMA_Channels[channel].srcAddr = dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_SRC_ADDR.reg; + dmaHandle->DMA_Channels[channel].destAddr = dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_DEST_ADDR.reg; + dmaHandle->DMA_Channels[channel].controlVal = dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONTROL.reg; + dmaHandle->DMA_Channels[channel].configVal = dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONFIG.reg; +#endif + return BASE_STATUS_OK; +} + +/** + * @brief DMA specified channel stops transporting. + * @param dmaHandle DMA handle. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_DMA_StopChannel(DMA_Handle *dmaHandle, unsigned int channel) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + DMA_PARAM_CHECK_WITH_RET(IsDmaChannelNum(channel) == true, BASE_STATUS_ERROR); + /* Ignore subsequent DMA requests */ + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONFIG.BIT.ch_halt = BASE_CFG_ENABLE; + unsigned int active; + /* Processes the remaining data in the channel FIFO */ + do { + active = dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONFIG.BIT.ch_active; + } while (active != 0); + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONFIG.BIT.ch_en = BASE_CFG_DISABLE; + return BASE_STATUS_OK; +} + +/** + * @brief DMA specified channel transfer complete interrupt service processing function. + * @param dmaHandle DMA handle. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval None. + */ +static void DMA_ChannelIrqHandlerTc(DMA_Handle *dmaHandle, unsigned int channel) +{ + unsigned int finishStatus = dmaHandle->baseAddress->DMAC_INT_TC_STAT.reg; + if ((finishStatus & (1 << channel)) != 0) { + dmaHandle->baseAddress->DMAC_INT_TC_CLR.reg |= (1 << channel); /* Clear channel tc interrupt */ + if (dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelFinishCallBack != NULL) { + dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelFinishCallBack( + dmaHandle->DMA_Channels[channel].pHandle); + } + } + return; +} + +/** + * @brief DMA specified channel error interrupt service processing function. + * @param dmaHandle DMA handle. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @retval None. + */ +static void DMA_ChannelIrqHandlerError(DMA_Handle *dmaHandle, unsigned int channel) +{ + unsigned int errorStatus = dmaHandle->baseAddress->DMAC_INT_ERR_STAT.reg; + if ((errorStatus & (1 << channel)) != 0) { + dmaHandle->baseAddress->DMAC_INT_ERR_CLR.reg |= (1 << channel); /* Clear channel err interrupt */ + if (dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelErrorCallBack != NULL) { + dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelErrorCallBack( + dmaHandle->DMA_Channels[channel].pHandle); + } + } + return; +} + +/** + * @brief DMA transfer complete interrupt service processing function. + * @param handle DMA handle. + * @retval None. + */ +void HAL_DMA_IrqHandlerTc(void *handle) +{ + DMA_ASSERT_PARAM(handle != NULL); + DMA_Handle *dmaHandle = (DMA_Handle *)handle; + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + unsigned int intStatus = dmaHandle->baseAddress->DMAC_INT_STAT.reg; + for (int i = 0; i < CHANNEL_MAX_NUM; i++) { + if (intStatus & (1 << i)) { /* DMAC channel status */ + DMA_ChannelIrqHandlerTc(dmaHandle, i); + } + } + return; +} + +/** + * @brief DMA error interrupt service processing function. + * @param handle DMA handle. + * @retval None. + */ +void HAL_DMA_IrqHandlerError(void *handle) +{ + DMA_ASSERT_PARAM(handle != NULL); + DMA_Handle *dmaHandle = (DMA_Handle *)handle; + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + unsigned int intStatus = dmaHandle->baseAddress->DMAC_INT_STAT.reg; + for (int i = 0; i < CHANNEL_MAX_NUM; i++) { + if (intStatus & (1 << i)) { /* DMAC channel status */ + DMA_ChannelIrqHandlerError(dmaHandle, i); + } + } + return; +} + +/** + * @brief User callback function registration interface. + * @param dmaHandle DMA handle. + * @param typeID Id of callback function type. + * @param channel ID of the selected DMA channel @ref DMA_ChannelNum. + * @param pCallback pointer of the specified callbcak function. + * @retval None. + */ +void HAL_DMA_RegisterCallback(DMA_Handle *dmaHandle, DMA_CallbackFun_Type typeID, + DMA_ChannelNum channel, DMA_CallbackType pCallback) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + DMA_PARAM_CHECK_NO_RET(IsDmaChannelNum(channel) == true); + switch (typeID) { + case DMA_CHANNEL_FINISH: + dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelFinishCallBack = pCallback; + break; + case DMA_CHANNEL_ERROR: + dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelErrorCallBack = pCallback; + break; + default: + return; + } +} + +/** + * @brief Find the last node in the linked list. + * @param head Pointer to the transfer header of the linked list. + * @retval retNode End node of the linked list. + */ +static DMA_LinkList* DMA_FindListEndNode(DMA_LinkList *head) +{ + DMA_LinkList* retNode = head; + while (retNode->lliNext != NULL) { + retNode = retNode->lliNext; + } + return retNode; +} + +/** + * @brief Add a new node to the end of the linked list. + * @param head Pointer to the transfer header of the linked list. + * @param newNode Node to be added. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_DMA_ListAddNode(DMA_LinkList *head, DMA_LinkList *newNode) +{ + DMA_ASSERT_PARAM(head != NULL); + DMA_ASSERT_PARAM(newNode != NULL); + DMA_LinkList *node = NULL; + node = DMA_FindListEndNode(head); + if (node != NULL) { + node->lliNext = newNode; + node->control.BIT.int_tc_enable = 0x0; /* current node does not trigger the transfer completion interrupt */ + newNode->control.BIT.int_tc_enable = 0x01; /* current node trigger the transfer completion interrupt */ + } + return BASE_STATUS_OK; +} + +/** + * @brief Create a new node and add it to the end of the linked list. + * @param head Linked blocked head node. + * @param split Argument handle that splits into small blocks. + * @param index Sequence number of the new node in the linked list. + * @param controlVal Channel control parameters for the new node. + * @retval None. + */ +static void DMA_CreateNode(DMA_LinkList *head, DMA_SplitParam *split, unsigned int index, unsigned int controlVal) +{ + if (g_listIndex >= LISTNODE_MAX) { + return; + } + DMA_LinkList *newNode = &(g_listTable[g_listIndex]); + g_listIndex++; + newNode->srcAddr = split->srcAddr + (index * TRANS_BLOCK * split->srcIn); + newNode->destAddr = split->destAddr + (index * TRANS_BLOCK * split->destIn); + newNode->lliNext = NULL; + newNode->control.reg = controlVal; /* Channel parameters configured for the node */ + HAL_DMA_ListAddNode(head, newNode); +} + +/** + * @brief The upper limit of a DMA transfer is TRANSIZE_MAX. If the upper limit is greater than this value, + * the DMA needs to be divided into small blocks, and each small block is linked for transmission. + * @param head Linked blocked head node. + * @param split Argument handle that splits into small blocks. + * @retval None. + */ +static void DMA_SplitToBlock(DMA_LinkList *head, DMA_SplitParam *split) +{ + unsigned int totalSize = split->totalSize; + unsigned remainSize = totalSize % TRANS_BLOCK; + unsigned int index, controlVal; + for (index = 1; index < totalSize / TRANS_BLOCK; index++) { /* Block transfer based on the 4092 size */ + controlVal = split->chnParam; + controlVal |= TRANS_BLOCK; + DMA_CreateNode(head, split, index, controlVal); + } + if (remainSize != 0) { /* The remaining data size is less than 4092 */ + controlVal = split->chnParam; + controlVal |= remainSize; + DMA_CreateNode(head, split, index, controlVal); + } +} + +/** + * @brief In DMA chain transmission, initialize each node. + * @param node Node to be initialized. + * @param param Channel transmission parameters. + * @param srcAddr Transport source address of this node. + * @param destAddr Transport destnation address of this node. + * @param tranSize Data transmitted by this node. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_DMA_InitNewNode(DMA_LinkList *node, const DMA_ChannelParam *param, + unsigned int srcAddr, unsigned int destAddr, unsigned int tranSize) +{ + DMA_ASSERT_PARAM(node != NULL); + DMA_ASSERT_PARAM(param != NULL); + DMA_PARAM_CHECK_WITH_RET(IsDmaValidAddress(srcAddr), BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaValidAddress(destAddr), BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(tranSize > 0, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaValidAddress((unsigned long long)srcAddr + (unsigned long long)tranSize), + BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaValidAddress((unsigned long long)destAddr + (unsigned long long)tranSize), + BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaBurstLength(param->srcBurst) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaBurstLength(param->destBurst) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaWidth(param->srcWidth) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaWidth(param->destWidth) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaAddrMode(param->srcAddrInc) == true, BASE_STATUS_ERROR); + DMA_PARAM_CHECK_WITH_RET(IsDmaAddrMode(param->destAddrInc) == true, BASE_STATUS_ERROR); + node->srcAddr = srcAddr; + node->destAddr = destAddr; + node->lliNext = NULL; + unsigned int val = 0x82000000; /* 0x82000000 indicates src use master1, dest use master2, int_tc_enable */ + val |= (param->srcBurst) << 12; /* Shift left by 12 bits for source burst */ + val |= (param->destBurst) << 15; /* Shift left by 15 bits for destination burst */ + val |= (param->srcWidth) << 18; /* Shift left by 18 bits for source width */ + val |= (param->destWidth) << 21; /* Shift left by 21 bits for destination width */ + val |= (param->srcAddrInc) << 26; /* Shift left by 26 bits for source address */ + val |= (param->destAddrInc) << 27; /* Shift left by 27 bits for destination address */ + if (tranSize > TRANSIZE_MAX) { + DMA_SplitParam split; + split.chnParam = val; + split.srcAddr = srcAddr; + split.destAddr = destAddr; + /* Source and destnation address single increment size */ + split.srcIn = param->srcAddrInc * (1 << param->srcWidth); + split.destIn = param->destAddrInc * (1 << param->destWidth); + split.totalSize = tranSize; + val |= TRANS_BLOCK; + node->control.reg = val; + DMA_SplitToBlock(node, &split); /* Shift left by 27 bits for destination address */ + } else { + val |= tranSize; + node->control.reg = val; + } + return BASE_STATUS_OK; +} + +/** + * @brief Start DMA chain transmission. Chain transfer, which is used to transfer data to discontinuous + * address spaces in memory. After the transmission task of the last node is complete, an interrupt is reported. + * @param dmaHandle DMA handle. + * @param head Pointer to the transfer header of the linked list. + * @param channel DMA channel num @ref DMA_ChannelNum. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_DMA_StartListTransfer(DMA_Handle *dmaHandle, DMA_LinkList *head, unsigned int channel) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(head != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + DMA_PARAM_CHECK_WITH_RET(IsDmaChannelNum(channel) == true, BASE_STATUS_ERROR); + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_SRC_ADDR.reg = head->srcAddr; + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_DEST_ADDR.reg = head->destAddr; + if (head->lliNext != NULL) { + /* Configure the next node address of the linked list */ + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_LLI.reg = (uintptr_t)(void *)head->lliNext; + } else { + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_LLI.reg = 0x00; + } + if (head->lliNext == head) { + head->control.BIT.int_tc_enable = 0; /* current node does not trigger the transfer completion interrupt */ + } + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONTROL.reg = head->control.reg; + /* Set tc_int_msk, ch_en */ + DMA_SetDirection(dmaHandle, channel); + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONFIG.BIT.tc_int_msk = BASE_CFG_ENABLE; + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONFIG.BIT.ch_en = BASE_CFG_ENABLE; + return BASE_STATUS_OK; +} + +#ifdef BASE_DEFINE_DMA_QUICKSTART +/** + * @brief DMA start data transfer without parameter verification Use the parameters of the last DMA configuration. + * @param dmaHandle DMA handle. + * @param channel DMA channel num @ref DMA_ChannelNum. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +void HAL_DMA_QuickStart(DMA_Handle *dmaHandle, unsigned int channel) +{ + DMA_ASSERT_PARAM(dmaHandle != NULL); + DMA_ASSERT_PARAM(IsDMAInstance(dmaHandle->baseAddress)); + DMA_PARAM_CHECK_NO_RET(IsDmaChannelNum(channel)); + /* Readback value configuration channel parameters */ + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_SRC_ADDR.reg = dmaHandle->DMA_Channels[channel].srcAddr; + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_DEST_ADDR.reg = dmaHandle->DMA_Channels[channel].destAddr; + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONTROL.reg = dmaHandle->DMA_Channels[channel].controlVal; + dmaHandle->DMA_Channels[channel].channelAddr->DMAC_Cn_CONFIG.reg = dmaHandle->DMA_Channels[channel].configVal; +} +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/flash/common/inc/flash.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/flash/common/inc/flash.h new file mode 100644 index 00000000..ede119d3 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/flash/common/inc/flash.h @@ -0,0 +1,124 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file flash.h + * @author MCU Driver Team + * @brief FLASH module driver. + * @details This file provides firmware functions to manage the following functionalities of the FLASH. + * + Basic parameter configuration macro. + * + FLASH parameter handle definition. + * + Initialization and de-initialization functions. + * + Definition of flash read/write erase functions. + */ +#ifndef McuMagicTag_FLASH_H +#define McuMagicTag_FLASH_H + +/* Includes ---------------------------------------------------------------------*/ +#include "flash_ip.h" + +/** + * @defgroup FLASH FLASH + * @brief FLASH module. + * @{ + */ + +/** + * @defgroup FLASH_Common FLASH Common + * @brief FLASH common external module. + * @{ + */ + +/* Macro definitions -----------------------------------------------------------*/ + +/** + * @defgroup FLASH_Handle_Definition FLASH Handle Definition + * @{ + */ + +/** + * @brief Module Status Enumeration Definition + */ +typedef enum { + FLASH_STATE_RESET = 0x00000000U, + FLASH_STATE_READY = 0x00000001U, + FLASH_STATE_PGM = 0x00000002U, + FLASH_STATE_ERASE = 0x00000003U, + FLASH_STATE_ERROR = 0x00000004U +} FLASH_StateType; + +/** + * @brief Module handle structure definition + */ +typedef struct _FLASH_Handle { + EFC_RegStruct *baseAddress; /**< Register base address. */ + FLASH_PE_OpMode peMode; /**< PE operation type. For details, see FLASH_PE_OpMode. */ + volatile unsigned int destAddr; /**< Destination address for storing interrupt operations. */ + volatile unsigned int srcAddr; /**< Used to store the source address in interrupt mode. */ + volatile unsigned int writeLen; /**< Indicates the length of the data to be written in interrupt mode. */ + volatile unsigned int eraseNum; /**< Used to store the number of erase blocks in interrupt mode. */ + FLASH_StateType state; /**< Running status of the flash module. For details, see FLASH_StateType. */ + FLASH_UserCallBcak userCallBack; /**< User-defined callback function. */ + FLASH_ExtendHandle handleEx; /**< Extend handle, configuring some special parameters. */ +} FLASH_Handle; + +/** + * @brief Callback Function Type Definition. + */ +typedef void (*FLASH_CallbackFunType)(void *handle, FLASH_CallBackEvent event, unsigned int opAddr); +/** + * @} + */ + +/** + * @defgroup FLASH_API_Declaration FLASH HAL API + * @{ + */ +BASE_StatusType HAL_FLASH_Init(FLASH_Handle *handle); +BASE_StatusType HAL_FLASH_DeInit(FLASH_Handle *handle); +BASE_StatusType HAL_FLASH_RegisterCallback(FLASH_Handle *handle, FLASH_CallbackFunType pcallback); +BASE_StatusType HAL_FLASH_WriteBlocking(FLASH_Handle *handle, unsigned int srcAddr, + unsigned int destAddr, unsigned int srcLen); +BASE_StatusType HAL_FLASH_EraseBlocking(FLASH_Handle *handle, + FLASH_EraseMode eraseMode, + FLASH_SectorAddr startAddr, + unsigned int eraseNum); +BASE_StatusType HAL_FLASH_WriteIT(FLASH_Handle *handle, unsigned int srcAddr, + unsigned int destAddr, unsigned int srcLen); +BASE_StatusType HAL_FLASH_EraseIT(FLASH_Handle *handle, + FLASH_EraseMode eraseMode, + FLASH_SectorAddr startAddr, + unsigned int eraseNum); +BASE_StatusType HAL_FLASH_Read(FLASH_Handle *handle, + unsigned int srcAddr, + unsigned int readLen, + unsigned char *dataBuff, + unsigned int buffLen); +void HAL_FLASH_IrqHandler(void *handle); +void HAL_FLASH_IrqHandlerError(void *handle); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* #ifndef McuMagicTag_FLASH_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/flash/inc/flash_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/flash/inc/flash_ip.h new file mode 100644 index 00000000..bbdae91f --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/flash/inc/flash_ip.h @@ -0,0 +1,955 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file flash_ip.h + * @author MCU Driver Team + * @brief FLASH module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the FLASH. + * + Register definition structure + * + Basic parameter configuration macro + */ + +/* Define to prevent recursive inclusion ----------------------------------------*/ +#ifndef McuMagicTag_FLASH_IP_H +#define McuMagicTag_FLASH_IP_H + +/* Includes ---------------------------------------------------------------------*/ +#include "baseinc.h" + +/* Macro definitions -----------------------------------------------------------*/ +#ifdef FLASH_PARAM_CHECK +#define FLASH_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define FLASH_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define FLASH_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define FLASH_ASSERT_PARAM(para) ((void)0U) +#define FLASH_PARAM_CHECK_NO_RET(para) ((void)0U) +#define FLASH_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +/** + * @addtogroup FLASH + * @{ + */ + +/** + * @defgroup FLASH_IP FLASH_IP + * @brief FLASH_IP: flash_v0 + * @{ + */ + +#define FLASH_BASE 0x0U /* Flash PE operation base address. */ +#define FLASH_READ_BASE 0x3000000U /* Base address for the flash read operation. */ +#define FLASH_ONE_PAGE_SIZE 0x2000U /* Size of a page,unit: bytes. 8K. */ +#define FLASH_MAX_SIZE 0x28000U /* Flash space size 160k bytes. */ + +#define FLASH_KEY_REGISTER_UNLOCK_VALUE 0xFEDCBA98 +#define FLASH_KEY_REGISTER_LOCK_VALUE 0x0 + +#define FLASH_MAX_PGM_WORD_SIZE 0x80 +#define FLASH_MIN_PGM_BYTES_SIZE 0x10 +#define FLASH_MIN_PGM_WORDS_SIZE 4 +#define FLASH_ONE_WORD_BYTES_SIZE 4 +#define FLASH_MAX_PAGE_NUM 20 + +#define FLASH_INFORMATUON_CAPACITY_POS 16 +#define FLASH_INFORMATUON_CAPACITY_MASK (0xFFFF << FLASH_INFORMATUON_CAPACITY_POS) + +#define FLASH_PGM_WBUF_CNT_POS 8 +#define FLASH_PGM_WBUF_CNT_MASK (0xFF << FLASH_PGM_WBUF_CNT_POS) + +#define FLASH_MAX_CMD_READ_SIZE 0x3 +#define FLASH_MAX_CMD_PROGRAM_SIZE 0x20 + +#define FLASH_SRAM_START_ADDRESS 0x04000000 +#define FLASH_SRAM_END_ADDRESS 0x04003FFF +#define FLASH_MAIN_RNG_START_ADDRESS 0x03000000 +#define FLASH_MAIN_RNG_END_ADDRESS 0x03027FFF + +/** + * @defgroup FLASH_Param_Def FLASH Parameters Definition + * @brief Definition of FLASH configuration parameters. + * @{ + */ +/* Typedef definitions --------------------------------------------------------*/ +/** + * @brief PE Operation Mode Enumeration Definition. + */ +typedef enum { + FLASH_PE_OP_BLOCK = 0x00000000U, + FLASH_PE_OP_IT = 0x00000001U +} FLASH_PE_OpMode; + +/** + * @brief Erase operation type enumeration definition. + */ +typedef enum { + FLASH_ERASE_MODE_PAGE = 0x00000004U, + FLASH_ERASE_MODE_CHIP = 0x00000006U +} FLASH_EraseMode; + +/** + * @brief Flash page address enumeration. + */ +typedef enum { + FLASH_PAGE_0 = FLASH_BASE, + FLASH_PAGE_1 = FLASH_BASE + FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_2 = FLASH_BASE + 2 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_3 = FLASH_BASE + 3 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_4 = FLASH_BASE + 4 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_5 = FLASH_BASE + 5 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_6 = FLASH_BASE + 6 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_7 = FLASH_BASE + 7 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_8 = FLASH_BASE + 8 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_9 = FLASH_BASE + 9 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_10 = FLASH_BASE + 10 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_11 = FLASH_BASE + 11 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_12 = FLASH_BASE + 12 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_13 = FLASH_BASE + 13 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_14 = FLASH_BASE + 14 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_15 = FLASH_BASE + 15 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_16 = FLASH_BASE + 16 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_17 = FLASH_BASE + 17 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_18 = FLASH_BASE + 18 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_19 = FLASH_BASE + 19 * FLASH_ONE_PAGE_SIZE, + FLASH_PAGE_MAX = FLASH_PAGE_19 +} FLASH_SectorAddr; + +/** + * @brief Flash operation word enumeration definition. + */ +typedef enum { + FLASH_OPERATION_READ = 0x00000001U, + FLASH_OPERATION_PROGRAM = 0x00000002U, + FLASH_OPERATION_ERASE = 0x00000004U, + FLASH_OPERATION_MASS_ERASE = 0x00000006U +} FLASH_OperationType; + +/** + * @brief Flash operation status enumeration definition. + */ +typedef enum { + FLASH_EXECUTION_STATUS_IDLE = 0x00000000U, + FLASH_EXECUTION_STATUS_RUNNING = 0x00000001U, + FLASH_EXECUTION_STATUS_FINISH = 0x00000002U +} FLASH_ExecutionStatusType; + +/** + * @brief Flash operation cmd code enumeration definition. + */ +typedef enum { + FLASH_CMD_READ = 0x00000001U, + FLASH_CMD_MAIN_RGN_PROGEAM = 0x00000002U, + FLASH_CMD_INFO_RGN_PROGEAM = 0x00000003U, + FLASH_CMD_MAIN_RGN_ERASE = 0x00000004U, + FLASH_CMD_INFO_RGN_ERASE = 0x00000005U, + FLASH_CMD_MASS_ERASE = 0x00000006U +} FLASH_CmdCodeType; + +/** + * @brief Callback Triggering Event Enumeration Definition + */ +typedef enum { + FLASH_WRITE_EVENT_SUCCESS, + FLASH_WRITE_EVENT_DONE, + FLASH_WRITE_EVENT_FAIL, + FLASH_ERASE_EVENT_SUCCESS, + FLASH_ERASE_EVENT_DONE, + FLASH_ERASE_EVENT_FAIL, +} FLASH_CallBackEvent; + +/** + * @brief FLASH extend handle, configuring some special parameters. + */ +typedef struct { + unsigned int onceOperateLen; /* Length of the flash memory to be operaten, write unit: byte, erase unit: page. */ +} FLASH_ExtendHandle; + +/** + * @brief User-defined callback function. + */ +typedef struct { + /** Event callback function of the flash module */ + void (*FlashCallBack)(void *handle, FLASH_CallBackEvent event, unsigned int opAddr); +} FLASH_UserCallBcak; +/** + * @} + */ + +/** + * @defgroup FLASH_Reg_Def FLASH Register Definition + * @brief register mapping structure + * @{ + */ + +/** + * @brief EFLASH command registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cmd_start : 1; /**< Write 0:no effect, 1:start cmd operation; + Read 0:cmd operation is complete, 1:cmd operation isn't complete. */ + unsigned int reserved0 : 5; + unsigned int exec_state : 2; /**< Read 0: no operation or operation completed, + 1: an operation is being performed, + 2: the operation is complete. */ + unsigned int cmd_code : 3; /**< Values represent 1: read, + 2: main_rgn0/main_rgn1 Program, + 3: info_rgn0/info_rgn1 Program, + 4: main_rgn0/main_rgn1 Erase, + 5: info_rgn0/info_rgn1 Erase, + 6: mass erase. */ + unsigned int reserved1 : 9; + unsigned int cmd_pgm_size : 6; /**< Program Size, unit:word(32bits). 0x1:4, 0x2:8,..., 0x1F:124, 0x20:128, + other values are invalid. */ + unsigned int reserved3 : 2; + unsigned int cmd_read_size : 2; /**< Read Size, unit:word(32bits). 0x0:1, 0x1:4, 0x2:8, 0x3:12. */ + unsigned int reserved4 : 2; + } BIT; +} volatile EFLASH_CMD_REG; + +/** + * @brief EFLASH address registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 2; + unsigned int cmd_addr : 22; /**< Program, erase, or read start address register. Unit:byte(8bits). + start address of Main_rgn0/main_rgn1: 0x00_0000, + start address of info_rgn0/info_rgn1: 0x80_0000, + note: the lower 2 bits cannot be written. */ + unsigned int reserved1 : 8; + } BIT; +} volatile EFLASH_ADDR_REG; + +/** + * @brief Command configuration registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int int_mode : 1; /**< Command operation mode 0:blocking mode, 1:interrupt mode. */ + unsigned int reserved1 : 30; + } BIT; +} volatile CMD_CFG_COMMON_REG; + +/** + * @brief The raw interrupt status registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int reserved1 : 1; + unsigned int reserved2 : 1; + unsigned int reserved3 : 1; + unsigned int int_raw_finish : 1; /**< Operation completion status, + 0:no operation performed or operation completed, + 1: the operation completed. */ + unsigned int reserved4 : 11; + unsigned int int_raw_err_illegal : 1; /**< Invalid cmd operation errors, 0:no errors, + 1: cmd operation error. */ + unsigned int int_raw_err_smwr : 1; /**< PGM/ERASE error, 0:pass, 1:failure. */ + unsigned int int_raw_err_ahb : 1; /**< AHB request error, 0:no errors, 1:AHB read address request + exceeds the range of Main_rgn0/main_rgn1 or + AHB write request occurs. */ + unsigned int int_raw_err_ecc_corr : 1; /**< Main_rgn0/rgn1 Read Data ECC Correction Error, 0:no errors, + 1:Uncorrectable ECC error occurred. */ + unsigned int int_raw_err_ecc_chk : 1; /**< Main_rgn0/main_rgn1 read data ECC error, 0:no errors, + 1:an ECC check error occurred. */ + unsigned int reserved5 : 11; + } BIT; +} volatile INT_RAW_STATUS_REG; + +/** + * @brief The interrupt enable configuration registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int reserved1 : 1; + unsigned int reserved2 : 1; + unsigned int reserved3 : 1; + unsigned int int_en_finish : 1; /**< Operation completion interrupt enable, 0:disable, 1:enable. */ + unsigned int reserved4 : 11; + unsigned int int_en_err_illegal : 1; /**< Invalid Cmd operation error interrupt enable, + 0:disable, 1:enable. */ + unsigned int int_en_err_smwr : 1; /**< PGM/ERASE error interrupt enable, 0:disable, 1:enable. */ + unsigned int int_en_err_ahb : 1; /**< AHB request error interrupt enable, 0:disable, 1:enable. */ + unsigned int int_en_err_ecc_corr : 1; /**< Main_rgn0/rgn1 read data ECC correction error interrupt, + 0:disable, 1:enable. */ + unsigned int int_en_err_ecc_chk : 1; /**< Main_rgn0/rgn1 read data ECC check error interrupt enable, + 0:disable, 1:enable. */ + unsigned int reserved5 : 11; + } BIT; +} volatile INT_ENABLE_REG; + +/** + * @brief Interrupt clear registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int reserved1 : 1; + unsigned int reserved2 : 1; + unsigned int reserved3 : 1; + unsigned int int_clr_finish : 1; /**< Operation completion interrupt clear, 0:not clear, + 1:clear raw interrupts and interrupt status. */ + unsigned int reserved4 : 11; + unsigned int int_clr_err_illegal : 1; /**< Invalid CMD operation error interrupt clear, 0:not clear, + 1:clear raw interrupts and interrupt status. */ + unsigned int int_clr_err_smwr : 1; /**< Pgm/erase error interrupt clear, 0:not clear, + 1:clear raw interrupts and interrupt status. */ + unsigned int int_clr_err_ahb : 1; /**< AHB request error interrupt clear, 0:not clear, + 1:clear raw interrupts and interrupt status. */ + unsigned int int_clr_err_ecc_corr : 1; /**< Main_rgn0/rgn1 read data ECC correction error interrupt clear, + 0:not clear, 1:clear raw interrupts and interrupt status. */ + unsigned int int_clr_err_ecc_chk : 1; /**< Main_rgn0/main_rgn1 read data ECC error interrupt clear, + 0:not clear, 1:clear raw interrupts and interrupt status. */ + unsigned int reserved5 : 11; + } BIT; +} volatile INT_CLEAR_REG; + +/** + * @brief Prefetch control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int prefetch_enable : 1; /**< Prefetch control enable, 0:disabled, 1:enable. */ + unsigned int reserved0 : 31; + } BIT; +} volatile PREFETCH_CTRL_REG; + +/** + * @brief Cache control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cache_enable : 1; /**< Prefetch control enable, 0:disabled, 1:enable. */ + unsigned int reserved0 : 3; + unsigned int cache_replacement_sel : 1; /**< Cache replacement policy selection, 0:PLRU policy, + 1:round robin policy. */ + unsigned int reserved1 : 3; + unsigned int cache_invalid_req : 1; /**< Cache data invalid request, 0:invalidation, + 1:request cache invalid. */ + unsigned int reserved2 : 23; + } BIT; +} volatile CACHE_CTRL_REG; + +/** + * @brief Flash ECC error detection and correction enable control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int flash_main_ecc_check_enable : 1; /**< Main_rgn0/main_rgn1 error detection enable, + 0:no ECC check, 1:ECC check. */ + unsigned int flash_main_ecc_correct_enable : 1; /**< Main_rgn0/main_rgn1 error detection enable, + 0:no ECC check, 1:ECC check. */ + unsigned int flash_info_ecc_check_enable : 1; /**< Main_rgn0/main_rgn1 ECC error detection enable, + 0:no ECC check, 1:ECC check. */ + unsigned int flash_info_ecc_correct_enable : 1; /**< Main_rgn0/main_rgn1 ECC error correction function, + 0:no ECC check, 1:ECC check. */ + unsigned int flash_ecc_blank_filter_enable : 1; /**< Flash unprogrammed area ECC mask and filter enable, + 0:disable, 1:enable. */ + unsigned int reserved0 : 27; + } BIT; +} volatile FLASH_ECC_CTRL_REG; + +/** + * @brief Flash status registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int opcode_illegal : 3; /**< Invalid opcode value. */ + unsigned int reserved0 : 1; + unsigned int mid_illegal : 3; /**< Invalid mid value. */ + unsigned int reserved1 : 1; + unsigned int info_rgn0_illegal : 1; /**< Illegally operation info_rgn0, 0:no error, + 1:illegally access occurs. */ + unsigned int info_rgn1_illegal : 1; /**< Illegally operation info_rgn1, 0:no error, + 1:illegally access occurs. */ + unsigned int reserved2 : 2; + unsigned int main_rgn0_illegal : 1; /**< Illegally operation main_rgn0, 0:no error, + 1:illegally access occurs. */ + unsigned int main_rgn1_illegal : 1; /**< Illegally operation main_rgn1, 0:no error, + 1:illegally access occurs. */ + unsigned int reserved3 : 2; + unsigned int parameter_illegal : 1; /**< Operation parameter is valid, 0:no error, + 1:Operation parameter error. */ + unsigned int address_unmap : 1; /**< Operation address out-of-bounds, 0:no error, + 1:address out-of-bounds error. */ + unsigned int reserved4 : 2; + unsigned int reserved5 : 12; + } BIT; +} volatile FLASH_STATUS_REG; + +/** + * @brief Flash read data validity indicator registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int flash_rdata_vld : 1; /**< Read data FIFO data validity indicator, 0:valid, 1:invalid. */ + unsigned int reserved0 : 31; + } BIT; +} volatile FLASH_RDATA_VLD_REG; + +/** + * @brief Flash Module information 1 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int page_size : 16; /**< Info_rgn0/info_rgn1 capacity, unit:byte. */ + unsigned int information_capacity : 16; /**< Eflash page capacity, unit:byte. */ + } BIT; +} volatile EFLASH_CAPACITY_1_REG; + +/** + * @brief Flash Module information 2 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int io_read_length : 4; /**< Read I/O size. */ + unsigned int io_write_length_information : 4; /**< Write information I/O size. */ + unsigned int io_write_length_main : 4; /**< Write main I/O size. */ + unsigned int min_pgm_size_information : 4; /**< Minimal programming size of information I/O size. */ + unsigned int min_pgm_size_main : 4; /**< Minimal programming size of main I/O size. */ + unsigned int max_pgm_size : 4; /**< Max programming size of I/O size. */ + unsigned int min_erase_size : 4; /**< Minimal erase size of I/O size. */ + unsigned int reserved0 : 4; + } BIT; +} volatile EFLASH_CAPACITY_2_REG; + +/** + * @brief Flash clears the programming data buffer registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pgm_wdata_clr : 1; /**< Clear Control, 0:no effect, 1:clear current buffer. */ + unsigned int reserved0 : 7; + unsigned int pgm_wbuf_cnt : 8; /**< Obtains the size of the data in the buffer, unit:word. */ + unsigned int reserved1 : 16; + } BIT; +} volatile BUF_CLEAR_REG; + +/** + * @brief Flash clock divider registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int m20ns_div : 4; /**< Clock divider, valid valuebits:0x0~0x0F. */ + unsigned int nread_div : 4; /**< Eflash normal read, valid valuebits:0x0~0x0F. */ + unsigned int sread_div : 3; /**< Eflash special read. */ + unsigned int reserved_0 : 1; + unsigned int ef_timer_option_unit : 8; /**< Used to setup timer option for eflash program/erase. */ + unsigned int busclk_sw_req : 1; /**< Check whether the handover is complete. */ + unsigned int busclk_switch_protect_enable : 1; /**< Frequency switching process protection, + 0:disable, 1:enable. */ + unsigned int reserved_1 : 2; + unsigned int data_vld_sel : 2; /**< Data vld sel. */ + unsigned int reserved_2 : 6; + } BIT; +} volatile EFLASH_CLK_CFG_REG; + +/** + * @brief Flash smart write timer control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved_0 : 8; + unsigned int smw_timer_option_value : 5; /**< Define of state required for PV/EV read cycle. */ + unsigned int reserved_1 : 19; + } BIT; +} volatile SMW_TIMER_OPTION_REG; + +/** + * @brief FLASH Register definition structure + */ +typedef struct { + EFLASH_CMD_REG EFLASH_CMD; /**< Command register. Offset Address: 0x0000. */ + EFLASH_ADDR_REG EFLASH_ADDR; /**< Address register. Offset Address: 0x0004. */ + unsigned char space0[120]; /**< 0x8~0x7c */ + CMD_CFG_COMMON_REG CMD_CFG_COMMON; /**< CMD configuration register. Offset Address: 0x0080. */ + unsigned char space1[124]; /**< 0x84~0xfc */ + INT_RAW_STATUS_REG INT_RAW_STATUS; /**< Raw interrupt status register. Offset Address: 0x0100. */ + unsigned char space2[4]; /**< 0x104 */ + INT_ENABLE_REG INT_ENABLE; /**< Interrupt enable configuration register. + Offset Address: 0x0108. */ + INT_CLEAR_REG INT_CLEAR; /**< Interrupt clear register. Offset Address: 0x010C. */ + unsigned char space3[16]; /**< 0x110~0x11c */ + PREFETCH_CTRL_REG PREFETCH_CTRL; /**< Prefetch control register. Offset Address: 0x0120. */ + CACHE_CTRL_REG CACHE_CTRL; /**< Cache control register. Offset Address: 0x0124. */ + unsigned char space4[4]; /**< 0x128~0x12C */ + FLASH_ECC_CTRL_REG FLASH_ECC_CTRL; /**< ECC error detection and correction enable control register. + Offset Address: 0x012C. */ + FLASH_STATUS_REG FLASH_STATUS; /**< CMD operation flash status register. + Offset Address: 0x0130. */ + FLASH_RDATA_VLD_REG FLASH_RDATA_VLD; /**< Flash read data validity indicator register. + Offset Address: 0x0134. */ + unsigned int AHB_ERR_ADDR; /**< AHB error request address record register. + Offset Address: 0x0138. */ + unsigned char space5[196]; /**< 0x13c~0x1fc */ + unsigned int MAGIC_LOCK; /**< CMD magic word protection register. + Offset Address: 0x0200. */ + unsigned char space6[492]; /**< 0x204~0x3ec */ + unsigned int EFLASH_CAPACITY_0; /**< Module information register 0. Offset Address: 0x03F0. */ + EFLASH_CAPACITY_1_REG EFLASH_CAPACITY_1; /**< Module information register 1. Offset Address: 0x03F4. */ + EFLASH_CAPACITY_2_REG EFLASH_CAPACITY_2; /**< Module information register 2. Offset Address: 0x03F8. */ + unsigned char space7[4]; /**< 0x3fc */ + unsigned int PGM_WDATA; /**< Program Data Register. Offset Address: 0x0400. */ + unsigned char space8[508]; /**< 0x404~0x5fc */ + unsigned int FLASH_RDATA; /**< Read data register. Offset Address: 0x0600. */ + BUF_CLEAR_REG BUF_CLEAR; /**< Programming data buffer cleanup register. + Offset Address: 0x0604. */ + unsigned int space9[206]; /**< 0x608~0x93c. */ + EFLASH_CLK_CFG_REG EFLASH_CLK_CFG; /**< Clock divider register. Offset Address: 0x940. */ + unsigned int space10[307]; /**< 0x944~0xe0c. */ + SMW_TIMER_OPTION_REG SMW_TIMER_OPTION; /**< Smart write timer control register. + Offset Address: 0xe10. */ +} volatile EFC_RegStruct; +/** + * @} + */ + +/* Parameter check definition-------------------------------------------*/ +/** + * @brief Check flash cmd code. + * @param cmdCode Flash cmd code. + * @retval true + * @retval false + */ +static inline bool IsFlashCmdCode(FLASH_CmdCodeType cmdCode) +{ + return (cmdCode == FLASH_CMD_READ || cmdCode == FLASH_CMD_MAIN_RGN_PROGEAM || \ + cmdCode == FLASH_CMD_INFO_RGN_PROGEAM || cmdCode == FLASH_CMD_MAIN_RGN_ERASE || \ + cmdCode == FLASH_CMD_INFO_RGN_ERASE || cmdCode == FLASH_CMD_MASS_ERASE); +} + +/** + * @brief Check flash cmd program size. + * @param size cmd program size, unit:Word(32bit). + * @retval true + * @retval false + */ +static inline bool IsFlashCmdProgramSize(unsigned int size) +{ + return ((size > 0x00) && (size <= FLASH_MAX_CMD_PROGRAM_SIZE)); /* The max value of cmd program size is 0x20. */ +} + +/** + * @brief Check flash cmd read size. + * @param size cmd read size, unit:Word(32bit). + * @retval true + * @retval false + */ +static inline bool IsFlashCmdReadSize(unsigned int size) +{ + return (size <= FLASH_MAX_CMD_READ_SIZE); /* The max value of cmd read size is 0x03. */ +} + +/** + * @brief Check flash program address. + * @param addr program address, unit:Byte(8bit). + * @retval true + * @retval false + */ +static inline bool IsFlashProgramAddress(unsigned int addr) +{ + return (((addr % FLASH_MIN_PGM_BYTES_SIZE) == 0) && (addr < FLASH_MAX_SIZE)); +} + +/** + * @brief Check flash erase address. + * @param addr erase address, unit:Byte(8bit). + * @retval true + * @retval false + */ +static inline bool IsFlashEraseAddress(unsigned int addr) +{ + return ((addr % FLASH_ONE_PAGE_SIZE) == 0) && (addr <= FLASH_PAGE_MAX); +} + +/** + * @brief Check flash read address. + * @param addr cmd read size, unit:Byte(8bit). + * @retval true + * @retval false + */ +static inline bool IsFlashReadAddress(unsigned int addr) +{ + return addr < FLASH_MAX_SIZE; +} + +/** + * @brief Check Operation mode selection. + * @param opMode Flash Operation mode. + * @retval true + * @retval false + */ +static inline bool IsFlashOperationMode(FLASH_PE_OpMode opMode) +{ + return (opMode == FLASH_PE_OP_BLOCK || + opMode == FLASH_PE_OP_IT); +} + +/** + * @brief Check flash write source addresss. + * @param addr write source addresss. + * @retval true + * @retval false + */ +static inline bool IsFlashWriteSrcAddress(unsigned int addr) +{ + return ((addr >= FLASH_SRAM_START_ADDRESS && addr <= FLASH_SRAM_END_ADDRESS) || + (addr >= FLASH_MAIN_RNG_START_ADDRESS && addr <= FLASH_MAIN_RNG_END_ADDRESS)); +} + +/** + * @brief Enable flash command start. + * @param efc FLASH register base address. + * @retval None. + */ +static inline void DCL_FLASH_CmdStartEnable(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + efcx->EFLASH_CMD.BIT.cmd_start = BASE_CFG_ENABLE; +} + +/** + * @brief Disable flash command start. + * @param efcx FLASH register base address. + * @retval None. + */ +static inline void DCL_FLASH_CmdStartDisable(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + efcx->EFLASH_CMD.BIT.cmd_start = BASE_CFG_DISABLE; +} + +/** + * @brief Getting flash command start State. + * @param efcx FLASH register base address. + * @retval command start value, 1: Operation complete or no operation, 0: Operation is not complete. + */ +static inline unsigned int DCL_FLASH_GetCmdStartState(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + return efcx->EFLASH_CMD.BIT.cmd_start; +} + +/** + * @brief Setting FLASH cmd code. + * @param efcx FLASH register base address. + * @param cmdCode flash cmd code. + * @retval None. + */ +static inline void DCL_FLASH_SetCmdCode(EFC_RegStruct *efcx, FLASH_CmdCodeType cmdCode) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + FLASH_PARAM_CHECK_NO_RET(IsFlashCmdCode(cmdCode)); + efcx->EFLASH_CMD.BIT.cmd_code = cmdCode; +} + +/** + * @brief Getting FLASH cmd code. + * @param efcx FLASH register base address. + * @retval cmd code, 1:READ, 2:FLASH_CMD_MAIN_RGN_PROGEAM, 3:FLASH_CMD_INFO_RGN_PROGEAM, 4:FLASH_CMD_MAIN_RGN_ERASE, + 5:FLASH_CMD_INFO_RGN_ERASE, 6:FLASH_CMD_MASS_ERASE. + */ +static inline unsigned int DCL_FLASH_GetCmdCode(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + return efcx->EFLASH_CMD.BIT.cmd_code; +} + +/** + * @brief Setting FLASH cmd program size. + * @param efcx FLASH register base address. + * @param size flash cmd program size, unit:Word(32bit). + * @retval None. + */ +static inline void DCL_FLASH_SetCmdProgramSize(EFC_RegStruct *efcx, unsigned int size) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + FLASH_PARAM_CHECK_NO_RET(IsFlashCmdProgramSize(size)); + efcx->EFLASH_CMD.BIT.cmd_pgm_size = size; +} + +/** + * @brief Getting FLASH cmd program size. + * @param efcx FLASH register base address. + * @retval cmd program size, unit:Word(32bit). + */ +static inline unsigned int DCL_FLASH_GetCmdProgramSize(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + return efcx->EFLASH_CMD.BIT.cmd_pgm_size; +} + +/** + * @brief Setting FLASH program start address. + * @param efcx FLASH register base address. + * @param addr flash cmd program start address, unit:Byte(8bit). + * @retval None. + */ +static inline void DCL_FLASH_SetProgramAddress(EFC_RegStruct *efcx, unsigned int addr) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + FLASH_PARAM_CHECK_NO_RET(IsFlashProgramAddress(addr)); + efcx->EFLASH_ADDR.BIT.cmd_addr = addr; +} + +/** + * @brief Setting FLASH erase start address. + * @param efcx FLASH register base address. + * @param addr flash cmd erase start address, unit:Byte(8bit). + * @retval None. + */ +static inline void DCL_FLASH_SetEraseAddress(EFC_RegStruct *efcx, unsigned int addr) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + FLASH_PARAM_CHECK_NO_RET(IsFlashEraseAddress(addr)); + efcx->EFLASH_ADDR.BIT.cmd_addr = addr; +} + +/** + * @brief Getting FLASH cmd program, erase, read start address. + * @param efcx FLASH register base address. + * @retval cmd program, erase, read start address, unit:Byte(8bit). + */ +static inline unsigned int DCL_FLASH_GetCmdStartAddress(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + return efcx->EFLASH_ADDR.BIT.cmd_addr; +} + +/** + * @brief Setting FLASH operation mode. + * @param efcx FLASH register base address. + * @param mode flash operation mode. + * @retval None. + */ +static inline void DCL_FLASH_SetOptMode(EFC_RegStruct *efcx, FLASH_PE_OpMode mode) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + FLASH_PARAM_CHECK_NO_RET(IsFlashOperationMode(mode)); + efcx->CMD_CFG_COMMON.BIT.int_mode = mode; +} + +/** + * @brief Getting FLASH operation mode. + * @param efcx FLASH register base address. + * @retval operation mode, 0:FLASH_PE_OP_BLOCK, 1:FLASH_PE_OP_IT. + */ +static inline unsigned int DCL_FLASH_GetOptMode(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + return efcx->CMD_CFG_COMMON.BIT.int_mode; +} + +/** + * @brief Obtains the interrupt status. + * @param efcx FLASH register base address. + * @retval Interrupt Status. + */ +static inline unsigned int DCL_FLASH_GetInterrupRawtStatus(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + return efcx->INT_RAW_STATUS.reg; +} + +/** + * @brief Configuring Interrupt Enable. + * @param efcx FLASH register base address. + * @param intrEn Corresponding interrupt enable bit, for example, 110011. + * @retval None. + */ +static inline void DCL_FLASH_SetInterruptEn(EFC_RegStruct *efcx, unsigned int intrEn) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + efcx->INT_ENABLE.reg = intrEn; +} + +/** + * @brief Obtaining the Interrupt Enable Configuration. + * @param efcx FLASH register base address. + * @retval Interrupt enable value. + */ +static inline unsigned int DCL_FLASH_GetInterruptEnState(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + return efcx->INT_ENABLE.reg; +} + +/** + * @brief Clear Interrupt. + * @param efcx FLASH register base address. + * @param intrRaw Corresponding interrupt bit, for example, 110011. + * @retval None. + */ +static inline void DCL_FLASH_ClearIrq(EFC_RegStruct *efcx, unsigned int intrRaw) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + efcx->INT_CLEAR.reg = intrRaw; +} + +/** + * @brief FLASH cache invalid request enable. + * @param efcx FLASH register base address. + * @retval None. + */ +static inline void DCL_FLASH_CacheInvalidRequestEnable(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + efcx->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_ENABLE; +} + +/** + * @brief FLASH cache invalid request disable. + * @param efcx FLASH register base address. + * @retval None. + */ +static inline void DCL_FLASH_CacheInvalidRequestDisable(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + efcx->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_DISABLE; +} + +/** + * @brief Getting FLASH cache invalid request state. + * @param efcx FLASH register base address. + * @retval state 0:The latest invalid request has been completed, + 1:The latest invalid request is not completed. + */ +static inline unsigned int DCL_FLASH_GetCacheInvalidRequestState(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + return efcx->CACHE_CTRL.BIT.cache_invalid_req; +} + +/** + * @brief Getting FLASH command operation status. + * @param efcx FLASH register base address. + * @retval command operation status. + */ +static inline unsigned int DCL_FLASH_GetCommandOptStatus(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + return efcx->FLASH_STATUS.reg; +} + +/** + * @brief Setting FLASH magic lock. + * @param efcx FLASH register base address. + * @retval None. + */ +static inline void DCL_FLASH_MagicLock(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + efcx->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; +} + +/** + * @brief Setting FLASH magic unlock. + * @param efcx FLASH register base address. + * @retval None. + */ +static inline void DCL_FLASH_MagicUnlock(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + efcx->MAGIC_LOCK = FLASH_KEY_REGISTER_UNLOCK_VALUE; +} + +/** + * @brief Getting FLASH magic lock. + * @param efcx FLASH register base address. + * @retval The value of magic lock, The value 0xFEDC_BA98 indicates magic unlock, others values is magic lock. + */ +static inline unsigned int DCL_FLASH_GetMagicLock(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + return efcx->MAGIC_LOCK; +} + +/** + * @brief Setting FLASH program wdata value. + * @param efcx FLASH register base address. + * @param value The value of program wdata. + * @retval None. + */ +static inline void DCL_FLASH_SetProgramWdata(EFC_RegStruct *efcx, unsigned int value) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + efcx->PGM_WDATA = value; +} + +/** + * @brief FLASH program wdata celar enable. + * @param efcx FLASH register base address. + * @retval None. + */ +static inline void DCL_FLASH_ProgramWdataClearEnable(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + efcx->BUF_CLEAR.BIT.pgm_wdata_clr = BASE_CFG_ENABLE; +} + +/** + * @brief FLASH program wdata celar disable. + * @param efcx FLASH register base address. + * @retval None. + */ +static inline void DCL_FLASH_ProgramWdataClearDisable(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + efcx->BUF_CLEAR.BIT.pgm_wdata_clr = BASE_CFG_DISABLE; +} + +/** + * @brief Getting FLASH buf clear value. + * @param efcx FLASH register base address. + * @retval None. + */ +static inline unsigned int DCL_FLASH_GetBufClearValue(EFC_RegStruct *efcx) +{ + FLASH_ASSERT_PARAM(efcx != NULL); + return efcx->BUF_CLEAR.reg; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* #ifndef McuMagicTag_FLASH_IP_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/flash/src/flash.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/flash/src/flash.c new file mode 100644 index 00000000..96672c16 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/flash/src/flash.c @@ -0,0 +1,690 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file flash.c + * @author MCU Driver Team + * @brief FLASH module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the FLASH. + * + Initialization and de-initialization functions. + * + Read, write, and erase functions. + */ + +/* Includes ------------------------------------------------------------------ */ +#include "flash.h" + +#define FLASH_CRC_SAVE_BUFFER_LEN 2 +#define FLASH_ALL_INTERRUPT_ENABLE 0x001F0010 +#define FLASH_ERR_INTERRUPT_MASK 0x001F0000 +#define FLASH_CMD_INTERRUPT_MASK 0x00000010 + +#define FLASH_KEY_REGISTER_UNLOCK_VALUE 0xFEDCBA98 +#define FLASH_KEY_REGISTER_LOCK_VALUE 0x0 + +#define FLASH_INT_ERR_ECC_CHK_MASK (1 << 20) +#define FLASH_INT_ERR_ECC_CORR_MASK (1 << 19) +#define FLASH_INT_ERR_AHB_MASK (1 << 18) +#define FLASH_INT_ERR_SMWR_MASK (1 << 17) +#define FLASH_INT_ERR_ILLEGAL_MASK (1 << 16) +#define FLASH_INT_FINISH_MASK (1<< 4) + +/** + * @brief Check all initial configuration parameters. + * @param handle FLASH handle. + * @retval None. + */ +static void CheckAllInitParameters(FLASH_Handle *handle) +{ +#ifndef FLASH_PARAM_CHECK + BASE_FUNC_UNUSED(handle); +#endif + FLASH_ASSERT_PARAM(IsFlashOperationMode(handle->peMode)); +} + +/** + * @brief Check whether errors occur. + * @param handle FLASH handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType CheckErrorStatus(FLASH_Handle *handle) +{ + /* Check whether errors occur. */ + if (handle->baseAddress->INT_RAW_STATUS.BIT.int_raw_err_illegal || + handle->baseAddress->INT_RAW_STATUS.BIT.int_raw_err_smwr) { + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; + return BASE_STATUS_ERROR; + } + if (handle->baseAddress->FLASH_STATUS.reg != 0) { + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief Writes to the flash memory in the unit of words. + * @param handle FLASH handle. + * @param srcAddr Start address of the data buffer to be written. + * @param destAddr Flash destination address, which must be word-aligned. + * @param wordNum Number of words written. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType FLASH_WriteWords(FLASH_Handle *handle, + const unsigned int srcAddr, + const unsigned int destAddr, + const unsigned int wordNum) +{ + unsigned int *data = NULL; + unsigned int i; + unsigned int writeSize; + /* Make sure the last operation is complete. */ + if (handle->baseAddress->EFLASH_CMD.BIT.cmd_start) { + return BASE_STATUS_BUSY; + } + + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_UNLOCK_VALUE; + /* The mask of program wdata celar is 0xFF. */ + if ((handle->baseAddress->BUF_CLEAR.reg >> FLASH_PGM_WBUF_CNT_POS) & 0xFF) { + handle->baseAddress->BUF_CLEAR.BIT.pgm_wdata_clr = BASE_CFG_SET; + } + /* Step 1: Calculated the cmd program size, get srcAddress and get destAddress. */ + writeSize = ((wordNum % FLASH_MIN_PGM_WORDS_SIZE) != 0) ? (wordNum / FLASH_MIN_PGM_WORDS_SIZE + 1) : + wordNum / FLASH_MIN_PGM_WORDS_SIZE; + + data = (unsigned int *)(uintptr_t)srcAddr; + handle->baseAddress->EFLASH_ADDR.BIT.cmd_addr = destAddr; + for (i = 0; i < wordNum; i++) { + handle->baseAddress->PGM_WDATA = *data; + data++; + } + /* Step 2: Configure the parameters and start programming. */ + handle->baseAddress->EFLASH_CMD.BIT.cmd_pgm_size = writeSize; + handle->baseAddress->EFLASH_CMD.BIT.cmd_code = FLASH_OPERATION_PROGRAM; + handle->baseAddress->EFLASH_CMD.BIT.cmd_start = BASE_CFG_SET; + /* Step 3: If the blocking mode is used, wait until the program operation is complete. */ + if (handle->peMode == FLASH_PE_OP_BLOCK) { + while (handle->baseAddress->EFLASH_CMD.BIT.cmd_start) { + ; + } + if (CheckErrorStatus(handle) != BASE_STATUS_OK) { + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; + return BASE_STATUS_ERROR; + } + } + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; + return BASE_STATUS_OK; +} + +/** + * @brief Obtains the number of words to be supplemented for write alignment to prevent cross-page write. + * @param handle FLASH handle. + * @retval Words. + */ +static unsigned int FLASH_GetWriteAlignmentWords(FLASH_Handle *handle) +{ + unsigned int numWords; + /* Step 1: Calculate the number of words occupied at the start address. */ + numWords = handle->destAddr % FLASH_MAX_PGM_WORD_SIZE; + if (numWords > 0) { + /* Step 2: Calculate the number of words in the remaining space of the ROW. */ + return FLASH_MAX_PGM_WORD_SIZE - numWords; + } + return 0; +} + +/** + * @brief Flash erase operation. + * @param handle FLASH handle. + * @param startAddr Erasing start address, which must be aligned with the minimum erasing unit. + * @param mode Erasing operation mode, supporting chip,and page. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType FLASH_EraseWithMode(FLASH_Handle *handle, unsigned int startAddr, unsigned int mode) +{ + /* Make sure the last operation is complete. */ + if (handle->baseAddress->EFLASH_CMD.BIT.cmd_start) { + return BASE_STATUS_BUSY; + } + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_UNLOCK_VALUE; + /* Step 1: Configure the erase start address and erase mode, then make cmd_satrt enable. */ + handle->baseAddress->EFLASH_ADDR.BIT.cmd_addr = startAddr; + handle->baseAddress->EFLASH_CMD.BIT.cmd_code = mode; + handle->baseAddress->EFLASH_CMD.BIT.cmd_start = BASE_CFG_SET; + /* Step 2: If the blocking mode is used, wait until the erase operation is complete. */ + if (handle->peMode == FLASH_PE_OP_BLOCK) { + while (handle->baseAddress->EFLASH_CMD.BIT.cmd_start) { + ; + } + /* Check whether errors occur. */ + if (handle->baseAddress->INT_RAW_STATUS.BIT.int_raw_err_illegal || + handle->baseAddress->INT_RAW_STATUS.BIT.int_raw_err_smwr) { + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; + return BASE_STATUS_ERROR; + } + if (handle->baseAddress->FLASH_STATUS.reg != 0) { + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; + return BASE_STATUS_ERROR; + } + } + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; + return BASE_STATUS_OK; +} + +/** + * @brief Write interrupt processing function, + * which completes the internal processing of the write operation in interrupt mode. + * @param handle FLASH handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType FLASH_WriteHandler(FLASH_Handle *handle) +{ + unsigned int dataLeft; + unsigned int dataLast; + BASE_StatusType ret; + /* If the number of bytes to be written is greater than a Row, + data is written based on the bytes number of a row. */ + if ((handle->writeLen / (FLASH_MAX_PGM_WORD_SIZE * FLASH_ONE_WORD_BYTES_SIZE)) > 0) { + handle->handleEx.onceOperateLen = FLASH_MAX_PGM_WORD_SIZE * FLASH_ONE_WORD_BYTES_SIZE; + ret = FLASH_WriteWords(handle, handle->srcAddr, handle->destAddr, FLASH_MAX_PGM_WORD_SIZE); + if (ret != BASE_STATUS_OK) { + return ret; + } + } else { + /* If the number of bytes to be written is less than a Row, + data is written in the unit of words. In addition, if data is less than one word, complete one word. */ + dataLeft = handle->writeLen; + dataLast = dataLeft % FLASH_ONE_WORD_BYTES_SIZE; + if (dataLeft > 0) { + if (dataLast > 0) { + handle->handleEx.onceOperateLen = + (dataLeft / FLASH_ONE_WORD_BYTES_SIZE + 1) * FLASH_ONE_WORD_BYTES_SIZE; + ret = FLASH_WriteWords( + handle, handle->srcAddr, handle->destAddr, dataLeft / FLASH_ONE_WORD_BYTES_SIZE + 1); + } else { + handle->handleEx.onceOperateLen = dataLeft; + ret = FLASH_WriteWords(handle, handle->srcAddr, handle->destAddr, dataLeft / FLASH_ONE_WORD_BYTES_SIZE); + } + if (ret != BASE_STATUS_OK) { + return ret; + } + } + } + return BASE_STATUS_OK; +} + +/** + * @brief Erase interrupt processing function, + * which completes the internal processing of the erase operation in interrupt mode. + * @param handle FLASH handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType FLASH_EraseHandler(FLASH_Handle *handle) +{ + BASE_StatusType ret; + handle->handleEx.onceOperateLen = 0x01; /* Erase 1 page at a time. */ + ret = FLASH_EraseWithMode(handle, handle->destAddr, FLASH_ERASE_MODE_PAGE); + if (ret != BASE_STATUS_OK) { + return ret; + } + return BASE_STATUS_OK; +} + +/** + * @brief Initializing the FLASH Module. + * @param handle FLASH handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_FLASH_Init(FLASH_Handle *handle) +{ + FLASH_ASSERT_PARAM(handle != NULL); + FLASH_ASSERT_PARAM(IsEFCInstance(handle->baseAddress)); + CheckAllInitParameters(handle); + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_UNLOCK_VALUE; /* Unlock key registers */ + if (handle->peMode == FLASH_PE_OP_IT) { + /* Enable the interrupt mode and clear the interrupt flag bit. */ + handle->baseAddress->CMD_CFG_COMMON.BIT.int_mode = BASE_CFG_SET; + handle->baseAddress->INT_ENABLE.reg = FLASH_ALL_INTERRUPT_ENABLE; + handle->baseAddress->INT_CLEAR.reg = FLASH_ALL_INTERRUPT_ENABLE; + } else { + /* If blocking mode is used, disable int_mode. */ + handle->baseAddress->CMD_CFG_COMMON.BIT.int_mode = BASE_CFG_UNSET; + } + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; /* Locking Key Registers */ + handle->state = FLASH_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief Deinitialize the FLASH Module. + * @param handle FLASH handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_FLASH_DeInit(FLASH_Handle *handle) +{ + FLASH_ASSERT_PARAM(handle != NULL); + FLASH_ASSERT_PARAM(IsEFCInstance(handle->baseAddress)); + handle->state = FLASH_STATE_RESET; + handle->userCallBack.FlashCallBack = NULL; /* Clean interrupt callback functions. */ + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_UNLOCK_VALUE; + /* Disable interrupt mode and interrupt enable bit. */ + handle->baseAddress->CMD_CFG_COMMON.BIT.int_mode = BASE_CFG_UNSET; + handle->baseAddress->INT_ENABLE.reg = 0x00000000; + handle->baseAddress->MAGIC_LOCK = FLASH_KEY_REGISTER_LOCK_VALUE; /* Locking Key Registers */ + return BASE_STATUS_OK; +} + +/** + * @brief Registering the Callback Function of the Flash Module. + * @param handle FLASH handle. + * @param pcallback Pointer to the callback function. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_FLASH_RegisterCallback(FLASH_Handle *handle, FLASH_CallbackFunType pcallback) +{ + FLASH_ASSERT_PARAM(handle != NULL); + FLASH_ASSERT_PARAM(IsEFCInstance(handle->baseAddress)); + handle->userCallBack.FlashCallBack = pcallback; + return BASE_STATUS_OK; +} + +/** + * @brief blocking write error handle. + * @param handle FLASH handle. + * @retval None. + */ +static void FLASH_WritteBlockingErrorHandle(FLASH_Handle *handle) +{ + handle->baseAddress->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_SET; + handle->state = FLASH_STATE_READY; +} + +/** + * @brief Write the flash memory in blocking mode. + * @param handle FLASH handle. + * @param srcAddr Start address of the data buffer to be written. + * @param destAddr Start address of the flash to be written.The address must be aligned with the minimum writable unit. + * @param srcLen Length of data to be written,unit:bytes. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_FLASH_WriteBlocking(FLASH_Handle *handle, unsigned int srcAddr, + unsigned int destAddr, const unsigned int srcLen) +{ + BASE_StatusType ret; + unsigned int dataLeft; + unsigned int dataLast; + unsigned int i; + unsigned int currentLen; + unsigned int currentWords; + + FLASH_ASSERT_PARAM((handle != NULL) && IsEFCInstance(handle->baseAddress)); + FLASH_PARAM_CHECK_WITH_RET(handle->state == FLASH_STATE_READY, BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(IsFlashWriteSrcAddress(srcAddr), BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET((destAddr % FLASH_MIN_PGM_BYTES_SIZE) == 0, BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(destAddr < FLASH_MAX_SIZE, BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(srcLen > 0 && srcLen <= (FLASH_MAX_SIZE - destAddr), BASE_STATUS_ERROR); + + handle->state = FLASH_STATE_PGM; + handle->destAddr = destAddr / FLASH_ONE_WORD_BYTES_SIZE; + handle->srcAddr = srcAddr; + /* Get the number of words in the remaining space of the ROW. */ + currentWords = FLASH_GetWriteAlignmentWords(handle); + /* Step 1: If there is remaining space and write length greater than remaining space, + write data in the remaining space. */ + if (srcLen > (currentWords * FLASH_ONE_WORD_BYTES_SIZE) && currentWords > 0) { + ret = FLASH_WriteWords(handle, handle->srcAddr, handle->destAddr, currentWords); + if (ret != BASE_STATUS_OK) { + FLASH_WritteBlockingErrorHandle(handle); + return ret; + } + handle->srcAddr += currentWords * FLASH_ONE_WORD_BYTES_SIZE; + handle->destAddr += currentWords; + currentLen = srcLen - currentWords * FLASH_ONE_WORD_BYTES_SIZE; + } else { + currentLen = srcLen; + } + /* Step 2: If the number of bytes to be written is greater than a Row, + data is written based on the bytes number of a row. */ + for (i = 0; i < currentLen / (FLASH_MAX_PGM_WORD_SIZE * FLASH_ONE_WORD_BYTES_SIZE); i++) { + ret = FLASH_WriteWords(handle, handle->srcAddr, handle->destAddr, FLASH_MAX_PGM_WORD_SIZE); + if (ret != BASE_STATUS_OK) { + FLASH_WritteBlockingErrorHandle(handle); + return ret; + } + handle->srcAddr += FLASH_MAX_PGM_WORD_SIZE * FLASH_ONE_WORD_BYTES_SIZE; + handle->destAddr += FLASH_MAX_PGM_WORD_SIZE; + } + /* Get the number of last remaining data. */ + dataLeft = (currentLen % (FLASH_MAX_PGM_WORD_SIZE * FLASH_ONE_WORD_BYTES_SIZE)); + dataLast = dataLeft % FLASH_ONE_WORD_BYTES_SIZE; + /* Step 3: Write the last remaining data. */ + if (dataLeft > 0) { + if (dataLast > 0) { + ret = FLASH_WriteWords(handle, handle->srcAddr, handle->destAddr, dataLeft / FLASH_ONE_WORD_BYTES_SIZE + 1); + } else { + ret = FLASH_WriteWords(handle, handle->srcAddr, handle->destAddr, dataLeft / FLASH_ONE_WORD_BYTES_SIZE); + } + } + + FLASH_WritteBlockingErrorHandle(handle); + return ret; +} + +/** + * @brief WriteErase the flash memory in blocking mode. + * @param handle FLASH handle. + * @param eraseMode Erasing mode. The options are chip erasing and page erasing. + * @param startAddr Start address of the flash to be erase. The address must be aligned with the minimum erasable unit. + * @param eraseNum Number of pages to be erased. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_FLASH_EraseBlocking(FLASH_Handle *handle, FLASH_EraseMode eraseMode, + FLASH_SectorAddr startAddr, unsigned int eraseNum) +{ + BASE_StatusType ret = BASE_STATUS_OK; + FLASH_ASSERT_PARAM(handle != NULL); + FLASH_ASSERT_PARAM(IsEFCInstance(handle->baseAddress)); + FLASH_PARAM_CHECK_WITH_RET(handle->state == FLASH_STATE_READY, BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(startAddr <= FLASH_PAGE_MAX, BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET((startAddr % FLASH_ONE_PAGE_SIZE == 0) || (eraseMode == FLASH_ERASE_MODE_CHIP),\ + BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(eraseNum > 0 && eraseNum <= (FLASH_MAX_PAGE_NUM - startAddr / FLASH_ONE_PAGE_SIZE),\ + BASE_STATUS_ERROR); + + handle->eraseNum = eraseNum; + handle->destAddr = startAddr / sizeof(unsigned int); + handle->state = FLASH_STATE_ERASE; + + if (eraseMode == FLASH_ERASE_MODE_CHIP) { + /* If the FLASH_ERASE_MODE_CHIP mode is used, all contents in the flash memory are erased. */ + ret = FLASH_EraseWithMode(handle, handle->destAddr, FLASH_ERASE_MODE_CHIP); + if (ret != BASE_STATUS_OK) { + handle->baseAddress->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_SET; + handle->state = FLASH_STATE_READY; + return ret; + } + } else if (eraseMode == FLASH_ERASE_MODE_PAGE) { + /* If the FLASH_ERASE_MODE_PAGE mode is used, erasing requires page-by-page. */ + while (handle->eraseNum) { + ret = FLASH_EraseHandler(handle); + if (ret != BASE_STATUS_OK) { + handle->baseAddress->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_SET; + handle->state = FLASH_STATE_READY; + return ret; + } + handle->destAddr += FLASH_ONE_PAGE_SIZE / sizeof(unsigned int); + handle->eraseNum--; + } + } + + handle->baseAddress->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_SET; + handle->state = FLASH_STATE_READY; + return ret; +} + +/** + * @brief Write the flash memory in interrupt mode. + * @param handle FLASH handle. + * @param srcAddr Start address of the data buffer to be written. + * @param destAddr Start address of the flash to be written.The address must be aligned with the minimum writable unit. + * @param srcLen Length of data to be written,unit:bytes. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_FLASH_WriteIT(FLASH_Handle *handle, unsigned int srcAddr, + unsigned int destAddr, unsigned int srcLen) +{ + unsigned int currentWords; + BASE_StatusType ret; + + FLASH_ASSERT_PARAM(handle != NULL); + FLASH_ASSERT_PARAM(IsEFCInstance(handle->baseAddress)); + FLASH_PARAM_CHECK_WITH_RET(destAddr < FLASH_MAX_SIZE, BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(handle->state == FLASH_STATE_READY, BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(IsFlashWriteSrcAddress(srcAddr), BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET((destAddr % FLASH_MIN_PGM_BYTES_SIZE) == 0, BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(srcLen > 0 && srcLen <= (FLASH_MAX_SIZE - destAddr), BASE_STATUS_ERROR); + + handle->state = FLASH_STATE_PGM; + + handle->destAddr = destAddr / FLASH_ONE_WORD_BYTES_SIZE; + handle->srcAddr = srcAddr; + handle->writeLen = srcLen; + /* Get the number of words in the remaining space of the ROW. */ + currentWords = FLASH_GetWriteAlignmentWords(handle); + /* If there is remaining space and write length greater than remaining space, + write data in the remaining space. */ + if (handle->writeLen > (currentWords * FLASH_ONE_WORD_BYTES_SIZE) && currentWords > 0) { + handle->handleEx.onceOperateLen = (currentWords * FLASH_ONE_WORD_BYTES_SIZE); + ret = FLASH_WriteWords(handle, handle->srcAddr, handle->destAddr, currentWords); + if (ret != BASE_STATUS_OK) { + handle->state = FLASH_STATE_READY; + return ret; + } + } else { + /* Write the last remaining data. */ + ret = FLASH_WriteHandler(handle); + if (ret != BASE_STATUS_OK) { + handle->state = FLASH_STATE_READY; + return ret; + } + } + return BASE_STATUS_OK; +} + +/** + * @brief WriteErase the flash memory in interrupt mode. + * @param handle FLASH handle. + * @param eraseMode Erasing mode. The options are chip erasing and page erasing. + * @param startAddr Start address of the flash to be erase. The address must be aligned with the minimum erasable unit. + * @param eraseNum Number of pages to be erased. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_FLASH_EraseIT(FLASH_Handle *handle, FLASH_EraseMode eraseMode, + FLASH_SectorAddr startAddr, unsigned int eraseNum) +{ + BASE_StatusType ret = BASE_STATUS_OK; + FLASH_ASSERT_PARAM(handle != NULL); + FLASH_ASSERT_PARAM(IsEFCInstance(handle->baseAddress)); + FLASH_PARAM_CHECK_WITH_RET(startAddr <= FLASH_PAGE_MAX, BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(handle->state == FLASH_STATE_READY, BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET((startAddr % FLASH_ONE_PAGE_SIZE == 0) || (eraseMode == FLASH_ERASE_MODE_CHIP),\ + BASE_STATUS_ERROR); + FLASH_PARAM_CHECK_WITH_RET(eraseNum > 0 && eraseNum <= (FLASH_MAX_PAGE_NUM - startAddr / FLASH_ONE_PAGE_SIZE),\ + BASE_STATUS_ERROR); + handle->eraseNum = eraseNum; + handle->state = FLASH_STATE_ERASE; + handle->destAddr = startAddr / sizeof(unsigned int); + + if (eraseMode == FLASH_ERASE_MODE_CHIP) { + /* If the FLASH_ERASE_MODE_CHIP mode is used, all contents in the flash memory are erased. */ + ret = FLASH_EraseWithMode(handle, handle->destAddr, FLASH_ERASE_MODE_CHIP); + if (ret != BASE_STATUS_OK) { + handle->state = FLASH_STATE_READY; + return ret; + } + handle->eraseNum = 0; + } else if (eraseMode == FLASH_ERASE_MODE_PAGE) { + /* If the FLASH_ERASE_MODE_PAGE mode is used, erasing requires page-by-page. */ + ret = FLASH_EraseHandler(handle); + if (ret != BASE_STATUS_OK) { + handle->state = FLASH_STATE_READY; + return ret; + } + } + return BASE_STATUS_OK; +} + +/** + * @brief Interface for reading data from the flash memory. + * @param handle FLASH handle. + * @param srcAddr Flash address of the data to be read. The address must be aligned with the minimum readable unit. + * @param readLen Read Data Length,unit:bytes. + * @param dataBuff Buffer for storing read data. + * @param buffLen Buffer size for storing read data,unit:bytes. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_FLASH_Read(FLASH_Handle *handle, + unsigned int srcAddr, + unsigned int readLen, + unsigned char *dataBuff, + unsigned int buffLen) +{ + unsigned char *ptemp = NULL; + unsigned char *dtemp = NULL; + unsigned int tempLen = readLen; +#ifndef FLASH_PARAM_CHECK + BASE_FUNC_UNUSED(handle); +#endif + FLASH_ASSERT_PARAM(handle != NULL); + FLASH_ASSERT_PARAM(IsEFCInstance(handle->baseAddress)); + FLASH_ASSERT_PARAM(dataBuff != NULL); + FLASH_PARAM_CHECK_WITH_RET(srcAddr < FLASH_MAX_SIZE, BASE_STATUS_ERROR); + + dtemp = dataBuff; + /* The basic offset address needs to be added to srcAddress. */ + ptemp = (unsigned char *)(uintptr_t)srcAddr + FLASH_READ_BASE; + if (readLen > buffLen) { + return BASE_STATUS_ERROR; + } + while (tempLen > 0) { + tempLen--; + *dtemp++ = *ptemp++; + } + return BASE_STATUS_OK; +} + +/** + * @brief Interrupt Processing Write. + * @param handle FLASH handle. + * @param status Interrupt status + * @retval None + */ +static void InterruptWriteHandle(FLASH_Handle *handle, unsigned int status) +{ + /* One operation complete */ + if ((status & FLASH_INT_FINISH_MASK) > 0) { + if (handle->userCallBack.FlashCallBack != NULL) { + handle->userCallBack.FlashCallBack(handle, FLASH_WRITE_EVENT_SUCCESS, handle->destAddr); + } + } + /* All operations are complete. */ + if (handle->writeLen == 0) { + if (handle->userCallBack.FlashCallBack != NULL) { + handle->userCallBack.FlashCallBack(handle, FLASH_WRITE_EVENT_DONE, handle->destAddr); + } + handle->baseAddress->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_SET; + handle->state = FLASH_STATE_READY; + } else { + FLASH_WriteHandler(handle); + } +} + +/** + * @brief Interrupt processing erase. + * @param handle FLASH handle. + * @param status Interrupt status + * @retval None + */ +static void InterruptEraseHandle(FLASH_Handle *handle, unsigned int status) +{ + /* One operation complete */ + if ((status & FLASH_INT_FINISH_MASK) > 0) { + if (handle->userCallBack.FlashCallBack != NULL) { + handle->userCallBack.FlashCallBack(handle, FLASH_ERASE_EVENT_SUCCESS, handle->destAddr); + } + } + /* All operations are complete. */ + if (handle->eraseNum == 0) { + if (handle->userCallBack.FlashCallBack != NULL) { + handle->userCallBack.FlashCallBack(handle, FLASH_ERASE_EVENT_DONE, handle->destAddr); + } + handle->baseAddress->CACHE_CTRL.BIT.cache_invalid_req = BASE_CFG_SET; + handle->state = FLASH_STATE_READY; + } else { + FLASH_EraseHandler(handle); + } +} + +/** + * @brief Interrupt Handling Function. + * @param handle Handle pointers + * @retval None + */ +void HAL_FLASH_IrqHandler(void *handle) +{ + FLASH_Handle *flashHandle = (FLASH_Handle *)handle; + unsigned int status; + FLASH_ASSERT_PARAM(flashHandle != NULL); + FLASH_ASSERT_PARAM(IsEFCInstance(flashHandle->baseAddress)); + status = flashHandle->baseAddress->INT_RAW_STATUS.reg; + flashHandle->baseAddress->INT_CLEAR.reg = status & FLASH_CMD_INTERRUPT_MASK; + /* Invoke the function for programming or erasing. */ + if (flashHandle->state == FLASH_STATE_PGM) { + if (flashHandle->writeLen < flashHandle->handleEx.onceOperateLen) { + flashHandle->writeLen = 0; + flashHandle->destAddr += flashHandle->handleEx.onceOperateLen >> 0x02; + } else { + flashHandle->writeLen -= flashHandle->handleEx.onceOperateLen; + flashHandle->srcAddr += flashHandle->handleEx.onceOperateLen; + flashHandle->destAddr += flashHandle->handleEx.onceOperateLen >> 0x02; /* Unit conversion to word */ + } + flashHandle->handleEx.onceOperateLen = 0; + InterruptWriteHandle(flashHandle, status); /* If state is FLASH_STATE_PGM, call write callback function. */ + } else if (flashHandle->state == FLASH_STATE_ERASE) { + if (flashHandle->handleEx.onceOperateLen != 0x00) { /* Erase page data valid. */ + flashHandle->destAddr += + (FLASH_ONE_PAGE_SIZE * flashHandle->handleEx.onceOperateLen) / sizeof(unsigned int); + flashHandle->eraseNum -= flashHandle->handleEx.onceOperateLen; + } else { + flashHandle->eraseNum = 0; /* Illegal state generation, and the status data is cleared. */ + } + flashHandle->handleEx.onceOperateLen = 0; + InterruptEraseHandle(flashHandle, status); /* If state is FLASH_STATE_ERASE, call erase callback function. */ + } +} + +/** + * @brief Flash Error interrupt Handling Function. + * @param handle Handle pointers + * @retval None + */ +void HAL_FLASH_IrqHandlerError(void *handle) +{ + FLASH_Handle *flashHandle = (FLASH_Handle *)handle; + unsigned int status; + FLASH_ASSERT_PARAM(flashHandle != NULL); + FLASH_ASSERT_PARAM(IsEFCInstance(flashHandle->baseAddress)); + status = flashHandle->baseAddress->INT_RAW_STATUS.reg; + flashHandle->baseAddress->INT_CLEAR.reg = status & FLASH_ERR_INTERRUPT_MASK; + + /* If any error occurs, call the programming error or erase error callback function. */ + if ((status & (FLASH_INT_ERR_ECC_CHK_MASK | FLASH_INT_ERR_ECC_CORR_MASK | + FLASH_INT_ERR_AHB_MASK | FLASH_INT_ERR_SMWR_MASK | FLASH_INT_ERR_ILLEGAL_MASK)) > 0) { + if (flashHandle->userCallBack.FlashCallBack != NULL) { + switch (flashHandle->state) { + case FLASH_STATE_PGM : /* If state is FLASH_STATE_PGM, call write error callback function. */ + flashHandle->userCallBack.FlashCallBack(flashHandle, FLASH_WRITE_EVENT_FAIL, flashHandle->destAddr); + break; + case FLASH_STATE_ERASE : /* If state is FLASH_STATE_ERASE, call erase error callback function. */ + flashHandle->userCallBack.FlashCallBack(flashHandle, FLASH_ERASE_EVENT_FAIL, flashHandle->destAddr); + break; + default: + break; + } + } + flashHandle->state = FLASH_STATE_READY; + } +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/gpio/common/inc/gpio.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/gpio/common/inc/gpio.h new file mode 100644 index 00000000..21cb00f3 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/gpio/common/inc/gpio.h @@ -0,0 +1,95 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file gpio.h + * @author MCU Driver Team + * @brief GPIO module driver + * @details The header file contains the following declaration: + * + GPIO handle structure definition. + * + Initialization functions. + * + GPIO Set And Get Functions. + * + Interrupt Service Functions. + */ + +#ifndef McuMagicTag_GPIO_H +#define McuMagicTag_GPIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "gpio_ip.h" + +/* Macro definition */ +/** + * @defgroup GPIO GPIO + * @brief GPIO module. + * @{ + */ + +/** + * @defgroup GPIO_Common GPIO Common + * @brief GPIO common external module. + * @{ + */ + +/** + * @defgroup GPIO_Handle_Definition GPIO Handle Definition + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ +typedef void (* GPIO_CallbackType)(void *param); + +typedef struct _GPIO_Handle { + GPIO_RegStruct *baseAddress; /**< GPIO Registers. */ + unsigned int pins; /**< Selected GPIO Pins. */ + GPIO_UserCallBcak userCallBack; /**< User-defined callback function. */ + GPIO_ExtendHandle handleEx; /**< Extend handle, configuring some special parameters. */ +} GPIO_Handle; + +/** + * @} + */ + +/** + * @defgroup GPIO_API_Declaration GPIO HAL API + * @{ + */ +void HAL_GPIO_Init(GPIO_Handle *handle); +void HAL_GPIO_DeInit(GPIO_Handle *handle); +void HAL_GPIO_SetDirection(GPIO_Handle *handle, unsigned int pins, GPIO_Direction dir); +void HAL_GPIO_SetValue(GPIO_Handle *handle, unsigned int pins, GPIO_Value value); +GPIO_InterruptMode HAL_GPIO_GetPinIrqType(GPIO_Handle *handle, GPIO_PIN pin); +GPIO_Value HAL_GPIO_GetPinValue(GPIO_Handle *handle, GPIO_PIN pin); +unsigned int HAL_GPIO_GetAllValue(GPIO_Handle *handle); +GPIO_Direction HAL_GPIO_GetPinDirection(GPIO_Handle *handle, GPIO_PIN pin); +unsigned int HAL_GPIO_GetAllDirection(GPIO_Handle *handle); +void HAL_GPIO_TogglePin(GPIO_Handle *handle, unsigned int pins); +BASE_StatusType HAL_GPIO_SetIrqType(GPIO_Handle *handle, unsigned int pins, GPIO_InterruptMode mode); +void HAL_GPIO_RegisterCallBack(GPIO_Handle *handle, GPIO_PIN pin, GPIO_CallbackType pCallback); +void HAL_GPIO_IrqHandler(void *handle); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_GPIO_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/gpio/inc/gpio_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/gpio/inc/gpio_ip.h new file mode 100644 index 00000000..ebf8d09e --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/gpio/inc/gpio_ip.h @@ -0,0 +1,678 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file gpio_ip.h + * @author MCU Driver Team + * @brief GPIO module driver + * @details The header file contains the following declaration: + * + GPIO configuration enums. + * + GPIO register structures. + * + GPIO DCL Functions. + * + Parameters check functions. + */ + +#ifndef McuMagicTag_GPIO_IP_H +#define McuMagicTag_GPIO_IP_H + +/* Includes ------------------------------------------------------------------*/ +#include "baseinc.h" +/* Macro definitions ---------------------------------------------------------*/ +#ifdef GPIO_PARAM_CHECK + #define GPIO_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM + #define GPIO_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET + #define GPIO_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else + #define GPIO_ASSERT_PARAM(para) ((void)0U) + #define GPIO_PARAM_CHECK_NO_RET(para) ((void)0U) + #define GPIO_PARAM_CHECK_WITH_RET(param, ret) ((void)0U) +#endif + +/** + * @addtogroup GPIO + * @{ + */ + +/** + * @defgroup GPIO_IP + * @{ + */ + +/* Macro definitions ---------------------------------------------------------*/ +#define GPIO_PIN_NUM (0x00000008U) +#define GPIO_PIN_MASK (0x000000FFU) + +/** + * @defgroup GPIO_Param_Def GPIO Parameters Definition + * @brief Description of GPIO configuration parameters. + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ +/** + * @brief GPIO PIN enum definition + */ +typedef enum { + GPIO_PIN_0 = 0x00000001U, + GPIO_PIN_1 = 0x00000002U, + GPIO_PIN_2 = 0x00000004U, + GPIO_PIN_3 = 0x00000008U, + GPIO_PIN_4 = 0x00000010U, + GPIO_PIN_5 = 0x00000020U, + GPIO_PIN_6 = 0x00000040U, + GPIO_PIN_7 = 0x00000080U, + GPIO_PIN_ALL = 0x000000FFU +} GPIO_PIN; + +/** + * @brief GPIO PIN value enum definition. + */ +typedef enum { + GPIO_LOW_LEVEL = 0x00000000U, + GPIO_HIGH_LEVEL = 0x00000001U +} GPIO_Value; + +/** + * @brief GPIO direction mode enum definition. + * @details status flag: + * + GPIO_INPUT_MODE -- GPIO pin as input, + * maximum input voltage of 3.63V for all types of I/O except 5V I/O, + * maximum input voltage of 5.0V for 5V I/O type. + * + GPIO_OUTPUT_MODE -- GPIO pin as output, + */ +typedef enum { + GPIO_INPUT_MODE = 0x00000000U, + GPIO_OUTPUT_MODE = 0x00000001U +} GPIO_Direction; + +/** + * @brief GPIO interrupt mode enum definition. + */ +typedef enum { + GPIO_INT_TYPE_FALL_EDGE = 0x00000000U, + GPIO_INT_TYPE_RISE_EDGE = 0x00000001U, + GPIO_INT_TYPE_LOW_LEVEL = 0x00000002U, + GPIO_INT_TYPE_HIGH_LEVEL = 0x00000003U, + GPIO_INT_TYPE_BOTH_EDGE = 0x00000004U, + GPIO_INT_TYPE_NONE = 0x00000005U +} GPIO_InterruptMode; + +/** + * @brief GPIO extend handle, configuring some special parameters. + */ +typedef struct { +} GPIO_ExtendHandle; + +/** + * @brief User-defined callback function. + */ +typedef struct { + /* GPIO pin callback functions */ + struct { + GPIO_PIN pin; + void (*callbackFunc)(void* handle); + } GPIO_CallbackFuncs[GPIO_PIN_NUM]; +} GPIO_UserCallBcak; + +/** + * @} + */ + +/** + * @defgroup GPIO_Reg_Def GPIO Register Definition + * @brief Description GPIO register mapping structure. + * @{ + */ + +/** + * @brief GPIO data registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pin0 : 1; /**< pin0 0:Input Data, 1:OutPut Data. */ + unsigned int pin1 : 1; /**< pin1 0:Input Data, 1:OutPut Data. */ + unsigned int pin2 : 1; /**< pin2 0:Input Data, 1:OutPut Data. */ + unsigned int pin3 : 1; /**< pin3 0:Input Data, 1:OutPut Data. */ + unsigned int pin4 : 1; /**< pin4 0:Input Data, 1:OutPut Data. */ + unsigned int pin5 : 1; /**< pin5 0:Input Data, 1:OutPut Data. */ + unsigned int pin6 : 1; /**< pin6 0:Input Data, 1:OutPut Data. */ + unsigned int pin7 : 1; /**< pin7 0:Input Data, 1:OutPut Data. */ + unsigned int reserved0 : 24; + } BIT; +} volatile GPIO_DATA_REG[256]; + +/** + * @brief GPIO direction registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pin0 : 1; /**< pin0 0:Input Direction, 1:OutPut Direction. */ + unsigned int pin1 : 1; /**< pin1 0:Input Direction, 1:OutPut Direction. */ + unsigned int pin2 : 1; /**< pin2 0:Input Direction, 1:OutPut Direction. */ + unsigned int pin3 : 1; /**< pin3 0:Input Direction, 1:OutPut Direction. */ + unsigned int pin4 : 1; /**< pin4 0:Input Direction, 1:OutPut Direction. */ + unsigned int pin5 : 1; /**< pin5 0:Input Direction, 1:OutPut Direction. */ + unsigned int pin6 : 1; /**< pin6 0:Input Direction, 1:OutPut Direction. */ + unsigned int pin7 : 1; /**< pin7 0:Input Direction, 1:OutPut Direction. */ + unsigned int reserved0 : 24; + } BIT; +} volatile GPIO_DIR_REG; + +/** + * @brief GPIO interrupt type registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pin0 : 1; /**< pin0 0:edge interrupt, 1:level interrupt. */ + unsigned int pin1 : 1; /**< pin1 0:edge interrupt, 1:level interrupt. */ + unsigned int pin2 : 1; /**< pin2 0:edge interrupt, 1:level interrupt. */ + unsigned int pin3 : 1; /**< pin3 0:edge interrupt, 1:level interrupt. */ + unsigned int pin4 : 1; /**< pin4 0:edge interrupt, 1:level interrupt. */ + unsigned int pin5 : 1; /**< pin5 0:edge interrupt, 1:level interrupt. */ + unsigned int pin6 : 1; /**< pin6 0:edge interrupt, 1:level interrupt. */ + unsigned int pin7 : 1; /**< pin7 0:edge interrupt, 1:level interrupt. */ + unsigned int reserved0 : 24; + } BIT; +} volatile GPIO_IS_REG; + +/** + * @brief GPIO edge type registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pin0 : 1; /**< pin0 0:rising or falling edge, 1: both edge. */ + unsigned int pin1 : 1; /**< pin1 0:rising or falling edge, 1: both edge. */ + unsigned int pin2 : 1; /**< pin2 0:rising or falling edge, 1: both edge. */ + unsigned int pin3 : 1; /**< pin3 0:rising or falling edge, 1: both edge. */ + unsigned int pin4 : 1; /**< pin4 0:rising or falling edge, 1: both edge. */ + unsigned int pin5 : 1; /**< pin5 0:rising or falling edge, 1: both edge. */ + unsigned int pin6 : 1; /**< pin6 0:rising or falling edge, 1: both edge. */ + unsigned int pin7 : 1; /**< pin7 0:rising or falling edge, 1: both edge. */ + unsigned int reserved0 : 24; + } BIT; +} volatile GPIO_IBE_REG; + +/** + * @brief GPIO interrupt condition registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pin0 : 1; /**< pin0 0:falling edge / low level, 1:rising edge / high level. */ + unsigned int pin1 : 1; /**< pin1 0:falling edge / low level, 1:rising edge / high level. */ + unsigned int pin2 : 1; /**< pin2 0:falling edge / low level, 1:rising edge / high level. */ + unsigned int pin3 : 1; /**< pin3 0:falling edge / low level, 1:rising edge / high level. */ + unsigned int pin4 : 1; /**< pin4 0:falling edge / low level, 1:rising edge / high level. */ + unsigned int pin5 : 1; /**< pin5 0:falling edge / low level, 1:rising edge / high level. */ + unsigned int pin6 : 1; /**< pin6 0:falling edge / low level, 1:rising edge / high level. */ + unsigned int pin7 : 1; /**< pin7 0:falling edge / low level, 1:rising edge / high level. */ + unsigned int reserved0 : 24; + } BIT; +} volatile GPIO_IEV_REG; + +/** + * @brief GPIO interrupt enable registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pin0 : 1; /**< pin0 0:mask interrupt, 1:unmask interrupt. */ + unsigned int pin1 : 1; /**< pin1 0:mask interrupt, 1:unmask interrupt. */ + unsigned int pin2 : 1; /**< pin2 0:mask interrupt, 1:unmask interrupt. */ + unsigned int pin3 : 1; /**< pin3 0:mask interrupt, 1:unmask interrupt. */ + unsigned int pin4 : 1; /**< pin4 0:mask interrupt, 1:unmask interrupt. */ + unsigned int pin5 : 1; /**< pin5 0:mask interrupt, 1:unmask interrupt. */ + unsigned int pin6 : 1; /**< pin6 0:mask interrupt, 1:unmask interrupt. */ + unsigned int pin7 : 1; /**< pin7 0:mask interrupt, 1:unmask interrupt. */ + unsigned int reserved0 : 24; + } BIT; +} volatile GPIO_IE_REG; + +/** + * @brief GPIO original interrupt signal registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pin0 : 1; /**< pin0 0:no interrupt, 1:has interrupt. */ + unsigned int pin1 : 1; /**< pin1 0:no interrupt, 1:has interrupt. */ + unsigned int pin2 : 1; /**< pin2 0:no interrupt, 1:has interrupt. */ + unsigned int pin3 : 1; /**< pin3 0:no interrupt, 1:has interrupt. */ + unsigned int pin4 : 1; /**< pin4 0:no interrupt, 1:has interrupt. */ + unsigned int pin5 : 1; /**< pin5 0:no interrupt, 1:has interrupt. */ + unsigned int pin6 : 1;; /**< pin6 0:no interrupt, 1:has interrupt. */ + unsigned int pin7 : 1; /**< pin7 0:no interrupt, 1:has interrupt. */ + unsigned int reserved0 : 24; + } BIT; +} volatile GPIO_RIS_REG; + +/** + * @brief GPIO mask interrupt signal registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pin0 : 1; /**< pin0 0:no interrupt, 1:has interrupt. */ + unsigned int pin1 : 1; /**< pin1 0:no interrupt, 1:has interrupt. */ + unsigned int pin2 : 1; /**< pin2 0:no interrupt, 1:has interrupt. */ + unsigned int pin3 : 1; /**< pin3 0:no interrupt, 1:has interrupt. */ + unsigned int pin4 : 1; /**< pin4 0:no interrupt, 1:has interrupt. */ + unsigned int pin5 : 1; /**< pin5 0:no interrupt, 1:has interrupt. */ + unsigned int pin6 : 1; /**< pin6 0:no interrupt, 1:has interrupt. */ + unsigned int pin7 : 1; /**< pin7 0:no interrupt, 1:has interrupt. */ + unsigned int reserved0 : 24; + } BIT; +} volatile GPIO_MIS_REG; + +/** + * @brief GPIO interrupt clear registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pin0 : 1; /**< pin0 0:no effect, 1:clear interrupt. */ + unsigned int pin1 : 1; /**< pin1 0:no effect, 1:clear interrupt. */ + unsigned int pin2 : 1; /**< pin2 0:no effect, 1:clear interrupt. */ + unsigned int pin3 : 1; /**< pin3 0:no effect, 1:clear interrupt. */ + unsigned int pin4 : 1; /**< pin4 0:no effect, 1:clear interrupt. */ + unsigned int pin5 : 1; /**< pin5 0:no effect, 1:clear interrupt. */ + unsigned int pin6 : 1; /**< pin6 0:no effect, 1:clear interrupt. */ + unsigned int pin7 : 1; /**< pin7 0:no effect, 1:clear interrupt. */ + unsigned int reserved0 : 24; + } BIT; +} volatile GPIO_IC_REG; + +/** + * @brief GPIO assemble registers structure definition + */ +typedef struct { + GPIO_DATA_REG GPIO_DATA; /**< gpio data register. Offset Address: 0x000～0x3FC.*/ + GPIO_DIR_REG GPIO_DIR; /**< gpio direction register. Offset Address: 0x400. */ + GPIO_IS_REG GPIO_IS; /**< gpio interrupt type register. Offset Address: 0x404. */ + GPIO_IBE_REG GPIO_IBE; /**< gpio edge type register. Offset Address: 0x408. */ + GPIO_IEV_REG GPIO_IEV; /**< gpio interrupt condition register. Offset Address: 0x40C. */ + GPIO_IE_REG GPIO_IE; /**< gpio interrupt enable register. Offset Address: 0x410. */ + GPIO_RIS_REG GPIO_RIS; /**< gpio original interrupt register. Offset Address: 0x414. */ + GPIO_MIS_REG GPIO_MIS; /**< gpio mask interrupt register. Offset Address: 0x418. */ + GPIO_IC_REG GPIO_IC; /**< gpio interrupt clear register. Offset Address: 0x41C. */ +} volatile GPIO_RegStruct; +/** + * @} + */ + +/** + * @brief Struct of map GPIO register and lock type. + */ +typedef struct { + GPIO_RegStruct *gpioGroup; + CHIP_LockType lockType; +} GPIO_MatchLockType; + +/** + * @brief Check gpio value parameter. + * @param value Value of @ref GPIO_Value + * @retval Bool. + */ +static inline bool IsGpioValue(GPIO_Value value) +{ + return (value == GPIO_LOW_LEVEL || value == GPIO_HIGH_LEVEL); +} + +/** + * @brief Check gpio direction parameter. + * @param dir Value of @ref GPIO_Direction. + * @retval Bool. + */ +static inline bool IsGpioDirection(GPIO_Direction dir) +{ + return (dir == GPIO_INPUT_MODE || dir == GPIO_OUTPUT_MODE); +} + +/** + * @brief Check gpio pins parameter. + * @param pins OR logical combination of pin. + * @retval Bool. + */ +static inline bool IsGpioPins(unsigned int pins) +{ + return ((pins & GPIO_PIN_MASK) != BASE_CFG_UNSET) && ((pins & ~GPIO_PIN_MASK) == BASE_CFG_UNSET); +} + +/** + * @brief Check gpio pin parameter. + * @param pin Value of @ref GPIO_PIN. + * @retval Bool. + */ +static inline bool IsGpioPin(GPIO_PIN pin) +{ + /* Check whether gpio pin */ + return (pin == GPIO_PIN_0 || pin == GPIO_PIN_1 || \ + pin == GPIO_PIN_2 || pin == GPIO_PIN_3 || \ + pin == GPIO_PIN_4 || pin == GPIO_PIN_5 || \ + pin == GPIO_PIN_6 || pin == GPIO_PIN_7 || \ + pin == GPIO_PIN_ALL); +} + +/** + * @brief Check gpio interrupt mode parameter. + * @param mode Value of @ref GPIO_InterruptMode. + * @retval Bool. + */ +static inline bool IsGpioITMode(GPIO_InterruptMode mode) +{ + /* Check whether gpio interrupt mode */ + return (mode == GPIO_INT_TYPE_HIGH_LEVEL || \ + mode == GPIO_INT_TYPE_LOW_LEVEL || \ + mode == GPIO_INT_TYPE_RISE_EDGE || \ + mode == GPIO_INT_TYPE_FALL_EDGE || \ + mode == GPIO_INT_TYPE_BOTH_EDGE || \ + mode == GPIO_INT_TYPE_NONE); +} + +/** + * @brief Setting GPIO pin level + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @param value Value of @ref GPIO_Value. + * @retval None. + */ +static inline void DCL_GPIO_SetValue(GPIO_RegStruct *gpiox, unsigned int pins, GPIO_Value value) +{ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + GPIO_PARAM_CHECK_NO_RET(IsGpioValue(value)); + gpiox->GPIO_DATA[pins].reg = (value == GPIO_HIGH_LEVEL ? pins : BASE_CFG_UNSET); /* Set GPIO pin level */ +} + +/** + * @brief Getting all GPIO level. + * @param gpiox Value of @ref GPIO_RegStruct. + * @retval unsigned int All GPIO pin level. + */ +static inline unsigned int DCL_GPIO_GetAllValue(const GPIO_RegStruct *gpiox) +{ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + return gpiox->GPIO_DATA[GPIO_PIN_MASK].reg & GPIO_PIN_MASK; /* Get all GPIO level. */ +} + +/** + * @brief Getting pin GPIO level. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pin OR logical combination of pin. + * @retval unsigned int GPIO pin level. + */ +static inline GPIO_Value DCL_GPIO_GetPinValue(const GPIO_RegStruct *gpiox, GPIO_PIN pin) +{ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_ASSERT_PARAM(IsGpioPin(pin)); + /* Get pin GPIO level. */ + return (gpiox->GPIO_DATA[GPIO_PIN_MASK].reg & pin) == BASE_CFG_UNSET ? GPIO_LOW_LEVEL : GPIO_HIGH_LEVEL; +} + +/** + * @brief Setting GPIO pin direction. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @param dir Value of @ref GPIO_Direction. + * @retval None. + */ +static inline void DCL_GPIO_SetDirection(GPIO_RegStruct *gpiox, unsigned int pins, GPIO_Direction dir) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + GPIO_PARAM_CHECK_NO_RET(IsGpioDirection(dir)); + if (dir == GPIO_INPUT_MODE) { /* Set GPIO pin direction */ + gpiox->GPIO_DIR.reg &= ~pins; + } else if (dir == GPIO_OUTPUT_MODE) { + gpiox->GPIO_DIR.reg |= pins; + } +} + +/** + * @brief Getting GPIO pin direction. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pin OR logical combination of pin. + * @retval GPIO direction, 0:input mode, 1:output mode. + */ +static inline GPIO_Direction DCL_GPIO_GetPinDirection(const GPIO_RegStruct *gpiox, GPIO_PIN pin) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_ASSERT_PARAM(IsGpioPin(pin)); + return (gpiox->GPIO_DIR.reg & pin) == BASE_CFG_UNSET ? GPIO_INPUT_MODE : GPIO_OUTPUT_MODE; +} + +/** + * @brief Getting GPIO all pin direction. + * @param gpiox Value of @ref GPIO_RegStruct. + * @retval unsigned int All GPIO pin direction. + */ +static inline unsigned int DCL_GPIO_GetAllPinDirection(const GPIO_RegStruct *gpiox) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + return gpiox->GPIO_DIR.reg & GPIO_PIN_MASK; +} + +/** + * @brief Setting GPIO pins edge trigger. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @retval None. + */ +static inline void DCL_GPIO_SetPinsEdgeTrigger(GPIO_RegStruct *gpiox, unsigned int pins) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + gpiox->GPIO_IS.reg &= ~pins; +} + +/** + * @brief Setting GPIO pins level trigger. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @retval None. + */ +static inline void DCL_GPIO_SetPinsLevelTrigger(GPIO_RegStruct *gpiox, unsigned int pins) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + gpiox->GPIO_IS.reg |= pins; +} + +/** + * @brief Getting GPIO pin trigger type. + * @param gpiox Value of @ref GPIO_RegStruct. + * @retval trigger type, 0:edge trigger; 1:level trigger. + */ +static inline unsigned int DCL_GPIO_GetPinsTriggerType(const GPIO_RegStruct *gpiox) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + return (gpiox->GPIO_IS.reg & GPIO_PIN_MASK); +} + +/** + * @brief Setting GPIO pins single edge trigger. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @retval None. + */ +static inline void DCL_GPIO_SetPinsSingleEdgeTrigger(GPIO_RegStruct *gpiox, unsigned int pins) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + gpiox->GPIO_IBE.reg &= ~pins; +} + +/** + * @brief Setting GPIO pins both edge trigger. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @retval None. + */ +static inline void DCL_GPIO_SetPinsBothEdgeTrigger(GPIO_RegStruct *gpiox, unsigned int pins) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + gpiox->GPIO_IBE.reg |= pins; +} + +/** + * @brief Getting GPIO pin edge trigger type. + * @param gpiox Value of @ref GPIO_RegStruct. + * @retval edge trigger type, pin value is 0:signle edge trigger; 1:both edge trigger. + */ +static inline unsigned int DCL_GPIO_GetPinsEdgeTriggerType(const GPIO_RegStruct *gpiox) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + return (gpiox->GPIO_IBE.reg & GPIO_PIN_MASK); +} + +/** + * @brief Setting GPIO pins falling edge or low level trigger. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @retval None. + */ +static inline void DCL_GPIO_SetPinsFallingEdgeOrLowLevelTrigger(GPIO_RegStruct *gpiox, unsigned int pins) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + gpiox->GPIO_IEV.reg &= ~pins; +} + +/** + * @brief Setting GPIO pins rising edge or high level trigger. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @retval None. + */ +static inline void DCL_GPIO_SetPinsRisingEdgeOrHighLevelTrigger(GPIO_RegStruct *gpiox, unsigned int pins) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + gpiox->GPIO_IEV.reg |= pins; +} + +/** + * @brief Getting GPIO pins trigger condition type. + * @param gpiox Value of @ref GPIO_RegStruct. + * @retval trigger condition type, pin value is 0:falling edge or low level trigger; + * @retval trigger condition type, pin value is 1:rising edge or high level trigger. + */ +static inline unsigned int DCL_GPIO_GetPinsTriggerConditionType(const GPIO_RegStruct *gpiox) +{ + /* param check */ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + return (gpiox->GPIO_IEV.reg & GPIO_PIN_MASK); +} + +/** + * @brief Clear all gpio interrupt signal. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @retval None. + */ +static inline void DCL_GPIO_ClearIrq(GPIO_RegStruct *gpiox, unsigned int pins) +{ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + gpiox->GPIO_IC.reg |= pins; +} + +/** + * @brief Enable gpio group interrupt. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pins. + * @retval None. + */ +static inline void DCL_GPIO_EnableIrq(GPIO_RegStruct *gpiox, unsigned int pins) +{ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + /* must clear interrupt first, prevents interrupts triggered by previous output mode. */ + DCL_GPIO_ClearIrq(gpiox, pins); + gpiox->GPIO_IE.reg |= pins; +} + +/** + * @brief Disable gpio interrupt. + * @param gpiox Value of @ref GPIO_RegStruct. + * @param pins OR logical combination of pin. + * @retval None. + */ +static inline void DCL_GPIO_DisableIrq(GPIO_RegStruct *gpiox, unsigned int pins) +{ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + gpiox->GPIO_IE.reg &= ~pins; +} + +/** + * @brief Getting all values of GPIO IE register. + * @param gpiox Value of @ref GPIO_RegStruct. + * @retval unsigned int All values of GPIO IE register. + */ +static inline unsigned int DCL_GPIO_GetIE(const GPIO_RegStruct *gpiox) +{ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + return gpiox->GPIO_IE.reg & GPIO_PIN_MASK; +} + +/** + * @brief Getting all values of GPIO RIS register. + * @param gpiox Value of @ref GPIO_RegStruct. + * @retval unsigned int All values of GPIO RIS register. + */ +static inline unsigned int DCL_GPIO_GetRIS(const GPIO_RegStruct *gpiox) +{ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + return gpiox->GPIO_RIS.reg & GPIO_PIN_MASK; +} + +/** + * @brief Getting all values of GPIO MIS register. + * @param gpiox Value of @ref GPIO_RegStruct. + * @retval unsigned int All values of GPIO MIS register. + */ +static inline unsigned int DCL_GPIO_GetMIS(const GPIO_RegStruct *gpiox) +{ + GPIO_ASSERT_PARAM(IsGPIOInstance(gpiox)); + return gpiox->GPIO_MIS.reg & GPIO_PIN_MASK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_GPIO_IP_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/gpio/src/gpio.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/gpio/src/gpio.c new file mode 100644 index 00000000..1a3e1a20 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/gpio/src/gpio.c @@ -0,0 +1,330 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file gpio.c + * @author MCU Driver Team + * @brief GPIO module driver + * @details This file provides firmware functions to manage the following functionalities of the GPIO. + * + GPIO configuration definetion. + * + Initialization functions. + * + GPIO Set And Get Functions. + * + Interrupt Service Functions. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "gpio.h" + +static void GPIO_ExcuteCallBack(GPIO_Handle *handle, GPIO_PIN pin); +static void GPIO_SetLevelIrqType(GPIO_Handle *handle, unsigned int pins, GPIO_InterruptMode mode); +static void GPIO_SetEdgeIrqType(GPIO_Handle *handle, unsigned int pins, GPIO_InterruptMode mode); + +/** + * @brief Initializing GPIO register values. + * @param handle Value of @ref GPIO_Handle. + * @retval None. + */ +void HAL_GPIO_Init(GPIO_Handle *handle) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(handle->pins)); + + /* Register GPIO callback ID */ + for (unsigned int i = 0; i < GPIO_PIN_NUM; i++) { + handle->userCallBack.GPIO_CallbackFuncs[i].pin = (1 << i); + } +} + +/** + * @brief DeInitializing GPIO register values. + * @param handle Value of @ref GPIO_Handle. + * @retval None. + */ +void HAL_GPIO_DeInit(GPIO_Handle *handle) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + /* Clean GPIO callback ID and interrupt callback functions. */ + for (unsigned int i = 0; i < GPIO_PIN_NUM; i++) { + handle->userCallBack.GPIO_CallbackFuncs[i].pin = 0x00000000; + handle->userCallBack.GPIO_CallbackFuncs[i].callbackFunc = NULL; + } + handle->pins = 0x00000000; /* Reset GPIO pins. */ +} + +/** + * @brief Setting GPIO pins direction. + * @param handle Value of @ref GPIO_Handle. + * @param pins OR logical combination of pin. + * @param dir GPIO pin direction. + * @retval None. + */ +void HAL_GPIO_SetDirection(GPIO_Handle *handle, unsigned int pins, GPIO_Direction dir) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + GPIO_PARAM_CHECK_NO_RET(IsGpioDirection(dir)); + DCL_GPIO_SetDirection(handle->baseAddress, pins, dir); +} + +/** + * @brief Setting GPIO pins level + * @param handle Value of @ref GPIO_Handle. + * @param pins OR logical combination of pin. + * @param value Value of @ref GPIO_Value. + * @retval None. + */ +void HAL_GPIO_SetValue(GPIO_Handle *handle, unsigned int pins, GPIO_Value value) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + GPIO_PARAM_CHECK_NO_RET(IsGpioValue(value)); + DCL_GPIO_SetValue(handle->baseAddress, pins, value); +} + +/** + * @brief Getting GPIO pin level + * @param handle Value of @ref GPIO_Handle. + * @param pin Value of @ref GPIO_PIN. + * @retval GPIO_Value Value of @ref GPIO_Value. + */ +GPIO_Value HAL_GPIO_GetPinValue(GPIO_Handle *handle, GPIO_PIN pin) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_ASSERT_PARAM(IsGpioPin(pin)); + return (handle->baseAddress->GPIO_DATA[GPIO_PIN_MASK].reg & pin) == BASE_CFG_UNSET ? \ + GPIO_LOW_LEVEL : GPIO_HIGH_LEVEL; +} + +/** + * @brief Getting GPIO pins level + * @param handle Value of @ref GPIO_Handle. + * @retval unsigned int Value of all GPIO pin. + */ +unsigned int HAL_GPIO_GetAllValue(GPIO_Handle *handle) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + return handle->baseAddress->GPIO_DATA[GPIO_PIN_MASK].reg & GPIO_PIN_MASK; +} + +/** + * @brief Getting GPIO pin direction + * @param handle Value of @ref GPIO_Handle. + * @param pin GPIO pin. + * @retval Value of @ref BASE_StatusType. + */ +GPIO_Direction HAL_GPIO_GetPinDirection(GPIO_Handle *handle, GPIO_PIN pin) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_ASSERT_PARAM(IsGpioPin(pin)); + return (handle->baseAddress->GPIO_DIR.reg & pin) == BASE_CFG_UNSET ? GPIO_INPUT_MODE : GPIO_OUTPUT_MODE; +} + +/** + * @brief Getting GPIO pins direction + * @param handle Value of @ref GPIO_Handle. + * @retval Value of @ref BASE_StatusType. + */ +unsigned int HAL_GPIO_GetAllDirection(GPIO_Handle *handle) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + return handle->baseAddress->GPIO_DIR.reg & GPIO_PIN_MASK; +} + +/** + * @brief Toggle GPIO level + * @param handle Value of @ref GPIO_Handle. + * @param pins GPIO pins. + * @retval None. + */ +void HAL_GPIO_TogglePin(GPIO_Handle *handle, unsigned int pins) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pins)); + handle->baseAddress->GPIO_DATA[pins].reg ^= pins; +} + +/** + * @brief Get GPIO pin interrupt types. + * @param handle Value of @ref GPIO_Handle. + * @param pin Value of @ref GPIO_PIN. + * @retval GPIO_InterruptMode Value of @ref GPIO_InterruptMode. + */ +GPIO_InterruptMode HAL_GPIO_GetPinIrqType(GPIO_Handle *handle, GPIO_PIN pin) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_ASSERT_PARAM(IsGpioPin(pin)); + /* If disable pin interrupt, return None mode */ + if ((handle->baseAddress->GPIO_IE.reg & pin) == BASE_CFG_UNSET) { + return GPIO_INT_TYPE_NONE; + } + unsigned int iev = ((handle->baseAddress->GPIO_IEV.reg & pin) != 0) ? 1 : 0; /* 1: iev effect. */ + unsigned int is = ((handle->baseAddress->GPIO_IS.reg & pin) != 0) ? 2 : 0; /* 2: is effect. */ + unsigned int ibe = ((handle->baseAddress->GPIO_IBE.reg & pin) != 0) ? 4 : 0; /* 4: ibe effect. */ + unsigned int value = (iev | is | ibe); + if (value >= GPIO_INT_TYPE_NONE) { + return GPIO_INT_TYPE_NONE; + } + return value; +} + +/** + * @brief Set GPIO level interrupt types. + * @param handle Value of @ref GPIO_Handle. + * @param pins OR logical combination of pin. + * @param mode Value of @ref GPIO_InterruptMode. + * @retval None. + */ +static void GPIO_SetLevelIrqType(GPIO_Handle *handle, unsigned int pins, GPIO_InterruptMode mode) +{ + handle->baseAddress->GPIO_IBE.reg &= ~pins; /* Disable edge detection */ + handle->baseAddress->GPIO_IS.reg |= pins; /* Enable level detection */ + if (mode == GPIO_INT_TYPE_HIGH_LEVEL) { + handle->baseAddress->GPIO_IEV.reg |= pins; + } else { + handle->baseAddress->GPIO_IEV.reg &= ~pins; + } +} + +/** + * @brief Set GPIO edge interrupt types. + * @param handle Value of @ref GPIO_Handle. + * @param pins OR logical combination of pin. + * @param mode Value of @ref GPIO_InterruptMode. + * @retval None. + */ +static void GPIO_SetEdgeIrqType(GPIO_Handle *handle, unsigned int pins, GPIO_InterruptMode mode) +{ + handle->baseAddress->GPIO_IS.reg &= ~pins; /* Disable level detection. */ + handle->baseAddress->GPIO_IBE.reg &= ~pins; /* Clear detection on both edges. */ + if (mode == GPIO_INT_TYPE_RISE_EDGE) { + handle->baseAddress->GPIO_IEV.reg |= pins; + } else { + handle->baseAddress->GPIO_IEV.reg &= ~pins; + } +} + +/** + * @brief Setting GPIO interrupt mode. + * @param handle Value of @ref GPIO_Handle. + * @param pins OR logical combination of pin. + * @param mode Value of @ref GPIO_InterruptMode. + * @retval Value of @ref BASE_StatusType. + */ +BASE_StatusType HAL_GPIO_SetIrqType(GPIO_Handle *handle, unsigned int pins, GPIO_InterruptMode mode) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_PARAM_CHECK_WITH_RET(IsGpioPins(pins), BASE_STATUS_ERROR); + GPIO_PARAM_CHECK_WITH_RET(IsGpioITMode(mode), BASE_STATUS_ERROR); + + /* It must be disabled to avoid triggering interrupts during configuration. */ + DCL_GPIO_DisableIrq(handle->baseAddress, pins); + + if ((mode == GPIO_INT_TYPE_HIGH_LEVEL) || (mode == GPIO_INT_TYPE_LOW_LEVEL)) { + GPIO_SetLevelIrqType(handle, pins, mode); + } else if (mode == GPIO_INT_TYPE_BOTH_EDGE) { + handle->baseAddress->GPIO_IEV.reg &= ~pins; + handle->baseAddress->GPIO_IS.reg &= ~pins; + handle->baseAddress->GPIO_IBE.reg |= pins; + } else if ((mode == GPIO_INT_TYPE_RISE_EDGE) || (mode == GPIO_INT_TYPE_FALL_EDGE)) { + GPIO_SetEdgeIrqType(handle, pins, mode); + } else if (mode == GPIO_INT_TYPE_NONE) { + /* No interruptMode: disable everything. */ + handle->baseAddress->GPIO_IEV.reg &= ~pins; + handle->baseAddress->GPIO_IS.reg &= ~pins; + handle->baseAddress->GPIO_IBE.reg &= ~pins; + return BASE_STATUS_ERROR; + } + + DCL_GPIO_EnableIrq(handle->baseAddress, pins); + return BASE_STATUS_OK; +} + +/** + * @brief Handle GPIO interrupt request. + * @param handle Value of @ref GPIO_Handle. + * @param pin Value of @ref GPIO_PIN. + * @retval None. + */ +static void GPIO_ExcuteCallBack(GPIO_Handle *handle, GPIO_PIN pin) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPins(pin)); + for (unsigned int i = 0; i < GPIO_PIN_NUM; i++) { + if (handle->userCallBack.GPIO_CallbackFuncs[i].pin == pin) { + if (handle->userCallBack.GPIO_CallbackFuncs[i].callbackFunc != NULL) { + handle->userCallBack.GPIO_CallbackFuncs[i].callbackFunc(handle); + } + } + } +} + +/** + * @brief Handle GPIO interrupt request. + * @param handle Interrupt parameter. + * @retval None. + */ +void HAL_GPIO_IrqHandler(void *handle) +{ + GPIO_Handle *gpioHandle = (GPIO_Handle *)handle; + GPIO_ASSERT_PARAM(gpioHandle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(gpioHandle->baseAddress)); + unsigned int position = 0x00000000U; + unsigned int pinCurrent = 0x00000000U; + unsigned int mis = DCL_GPIO_GetMIS(gpioHandle->baseAddress); /* Queries the masked GPIO interrupt status. */ + + /* Determine which pin sets the callback function. */ + while ((mis >> position) != BASE_CFG_UNSET) { + pinCurrent = mis & (1 << position); + if (pinCurrent) { + gpioHandle->pins = pinCurrent; + DCL_GPIO_ClearIrq(gpioHandle->baseAddress, pinCurrent); + GPIO_ExcuteCallBack(gpioHandle, pinCurrent); + } + position++; + } +} + +/** + * @brief Handle GPIO interrupt request. + * @param handle Value of @ref GPIO_Handle. + * @param pin Value of @ref GPIO_PIN. + * @param pCallback Value of @ref GPIO_CallbackType. + * @retval None. + */ +void HAL_GPIO_RegisterCallBack(GPIO_Handle *handle, GPIO_PIN pin, GPIO_CallbackType pCallback) +{ + GPIO_ASSERT_PARAM(handle != NULL); + GPIO_ASSERT_PARAM(IsGPIOInstance(handle->baseAddress)); + GPIO_PARAM_CHECK_NO_RET(IsGpioPin(pin)); + for (unsigned int i = 0; i < GPIO_PIN_NUM; i++) { + if (handle->userCallBack.GPIO_CallbackFuncs[i].pin == pin) { + handle->userCallBack.GPIO_CallbackFuncs[i].callbackFunc = pCallback; + } + } +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/gpt/common/inc/gpt.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/gpt/common/inc/gpt.h new file mode 100644 index 00000000..4db50f0a --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/gpt/common/inc/gpt.h @@ -0,0 +1,91 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file gpt.h + * @author MCU Driver Team + * @brief GPT module driver. + * @details This file provides firmware GPT Handle Structure and functions + * prototypes to manage the following functionalities of the GPT. + * + Initialization and de-initialization functions + * + config the register of GPT + * + interrupt register and register functions + */ + +#ifndef McuMagicTag_GPT_H +#define McuMagicTag_GPT_H + +/* Includes-------------------------------------------------------------------*/ +#include "gpt_ip.h" + +/** + * @defgroup GPT GPT + * @brief GPT module. + * @{ + */ + +/** + * @defgroup GPT_Common GPT Common + * @brief GPT common external module. + * @{ + */ + +/** + * @defgroup GPT_Handle_Definition GPT Handle Definition + * @{ + */ +typedef struct { + GPT_RegStruct *baseAddress; /**< Base address of GPT register */ + volatile unsigned int period; /**< PWM period, unit ns */ + volatile unsigned int duty; /**< PWM duty, unit ns */ + volatile unsigned int pwmNum; /**< PWM number, only valid when pwmKeep is false */ + bool pwmKeep; /**< PWM output mode */ + bool pwmPolarity; /**< PWM output positive and negative control */ + bool pwmEnable; /**< PWM Enable */ +} GPT_Handle; + +/** + * @} + */ + +/** + * @defgroup GPT_API_Declaration GPT HAL API + * @{ + */ +/** + * GPT Extended Control functions + */ +BASE_StatusType HAL_GPT_Init(GPT_Handle *handle); + +void HAL_GPT_Start(GPT_Handle *handle); + +void HAL_GPT_Stop(GPT_Handle *handle); + +BASE_StatusType HAL_GPT_Config(GPT_Handle *handle); + +BASE_StatusType HAL_GPT_GetConfig(GPT_Handle *handle); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_GPT_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/gpt/inc/gpt_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/gpt/inc/gpt_ip.h new file mode 100644 index 00000000..27ae7fca --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/gpt/inc/gpt_ip.h @@ -0,0 +1,391 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file gpt_ip.h + * @author MCU Driver Team + * @brief GPT module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the GPT. + * + Register Struct of GPT + * + GPT Register Map struct + * + Direct Configuration Layer functions of GPT + */ + +#ifndef McuMagicTag_GPT_IP_H +#define McuMagicTag_GPT_IP_H + +/* Includes-------------------------------------------------------------------*/ +#include "baseinc.h" + +/** + * @addtogroup GPT + * @{ + */ + +/** + * @defgroup GPT_IP GPT_IP + * @brief GPT_IP: gpt_v0 + * @{ + */ + +/** + * @defgroup GPT_Param_Def GPT Parameters Definition + * @brief Definition of GPT configuration parameters. + * @{ + */ + +/* Macro definitions ---------------------------------------------------------*/ +#ifdef GPT_PARAM_CHECK +#define GPT_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define GPT_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define GPT_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define GPT_ASSERT_PARAM(para) ((void)0U) +#define GPT_PARAM_CHECK_NO_RET(para) ((void)0U) +#define GPT_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +#define GPT_PWM_MAX_NUM 0x3FFU /**< The max num of pwmo_num */ +#define GPT_PWM_PERIOD_MIN_VALUE 2U /**< The min value of pwm_period */ +#define GPT_PWM_DUTY_MIN_VALUE 1U /**< The min value of pwm_duty */ +#define GPT_PWM_PERIOD_MAX_VALUE 0x3FFFFFFUL /**< The max value of pwm_period */ +#define GPT_PWM_DUTY_MAX_VALUE 0x3FFFFFFUL /**< The max value of pwm_duty */ +#define GPT_PWM_PERIOD_INVALID_VALUE 0xFFFFFFFF +#define GPT_PWM_DUTY_INVALID_VALUE 0xFFFFFFFF + +/** + * @} + */ + +/** + * @defgroup GPT_Reg_Def GPT Register Definition + * @brief register mapping structure + * @{ + */ +/** + * @brief PWM CFG2 register structure + */ +typedef struct { + unsigned int pwm_num : 10; /**< Number of output square waves of the GPTx. */ + unsigned int reserved0 : 22; +} volatile PWM_CFG2_Reg; + +/** + * @brief PWM CTRL register union + */ +typedef union { + unsigned int value; + struct { + unsigned int pwm_enable : 1; /**< GPT enable. */ + unsigned int pwm_inv : 1; /**< Positive and negative phase control of the GPT output. */ + unsigned int pwm_keep : 1; /**< GPT output mode. */ + unsigned int reserved0 : 29; + } BIT; +} volatile PWM_CTRL_Reg; + +/** + * @brief PWM STATE2 register union. + */ +typedef union { + unsigned int value; + struct { + unsigned int pwm_num_st : 10; /**< Number of output square waves used by internal modules. */ + unsigned int pwm_busy : 1; /**< Working status of the GPTx module. */ + unsigned int pwm_keep_st : 1; /**< Output square wave mode used by the internal modules. */ + unsigned int pwm_cnt_st : 10; /**< Indicates number of remaining output square waves. */ + unsigned int reserved0 : 10; + } BIT; +} volatile PWM_STATE2_Reg; + +/** + * @brief GPT register structure. + */ +typedef struct { + unsigned int pwm_period; /**< Number of cycles of PWM. Offset address: 0x00000000U. */ + unsigned int pwm_duty; /**< The number of high-level beats of PWM. Offset address: 0x00000004U. */ + PWM_CFG2_Reg PWM_CFG2; /**< PWM Config Register 2. Offset address: 0x00000008U.*/ + PWM_CTRL_Reg PWM_CTRL; /**< PWM Control Register. Offset address: 0x0000000CU. */ + unsigned int pwm_period_st; /**< Number of counting cycles in internal module. Offset address: 0x00000010U. */ + unsigned int pwm_duty_st; /**< High-level beats used by the internal module. Offset address: 0x00000014U. */ + PWM_STATE2_Reg PWM_STATE2; /**< PWM State Register. Offset address: 0x00000018U. */ +} volatile GPT_RegStruct; +/** + * @} + */ + +/* Parameter Check -----------------------------------------------------------*/ + +/** + * @brief Verify GPT max pwm num + * @param num Pwm number, only valid if keep equ 0 + * @retval true + * @retval false + */ +static inline bool IsGptPwmNum(unsigned int num) +{ + return ((num) <= GPT_PWM_MAX_NUM); +} + +/** + * @brief Verify GPT period value + * @param period Period of GPT + * @retval true + * @retval false + */ +static inline bool IsGptPeriod(unsigned int period) +{ + return ((period >= GPT_PWM_PERIOD_MIN_VALUE) && (period <= GPT_PWM_PERIOD_MAX_VALUE)); +} + +/** + * @brief Verify GPT duty value + * @param duty Duty of GPT + * @retval true + * @retval false + */ +static inline bool IsGptDuty(unsigned int duty) +{ + return ((duty >= GPT_PWM_DUTY_MIN_VALUE) && (duty <= GPT_PWM_DUTY_MAX_VALUE)); +} + +/* Direct Configuration Layer Functions --------------------------------------*/ +/** + * @brief Set PWM Period. + * @param gptx GPTx register baseAddr. + * @param period Number of cycles of PWM. + * @retval None + */ +static inline void DCL_GPT_SetPeriod(GPT_RegStruct * const gptx, unsigned int period) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_PARAM_CHECK_NO_RET(IsGptPeriod(period)); + gptx->pwm_period = period; +} + +/** + * @brief Get PWM Period. + * @param gptx GPTx register baseAddr. + * @retval period Number of cycles of PWM. + */ +static inline unsigned int DCL_GPT_GetPeriod(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + return gptx->pwm_period; +} + +/** + * @brief Set PWM duty. + * @param gptx GPTx register baseAddr. + * @param duty The number of high-level beats of PWM. + * @retval None + */ +static inline void DCL_GPT_SetDuty(GPT_RegStruct * const gptx, unsigned int duty) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_PARAM_CHECK_NO_RET(IsGptDuty(duty)); + gptx->pwm_duty = duty; +} + +/** + * @brief Get PWM duty. + * @param gptx gptx register baseAddr. + * @retval duty The number of high-level beats of PWM. + */ +static inline unsigned int DCL_GPT_GetDuty(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + return gptx->pwm_duty; +} + +/** + * @brief Set PWM number, only valid if pwm_keep is set. + * @param gptx GPTx register baseAddr. + * @param pwmNum The number of PWM. + * @retval None + */ +static inline void DCL_GPT_SetPwmNum(GPT_RegStruct * const gptx, unsigned int pwmNum) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_PARAM_CHECK_NO_RET(IsGptPwmNum(pwmNum)); + gptx->PWM_CFG2.pwm_num = pwmNum; +} + +/** + * @brief Get PWM number. + * @param gptx GPTx register baseAddr. + * @retval None + */ +static inline unsigned int DCL_GPT_GetPwmNum(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + return gptx->PWM_CFG2.pwm_num; +} + +/** + * @brief Enable GPT. + * @param gptx GPTx register baseAddr. + * @retval None + */ +static inline void DCL_GPT_Enable(GPT_RegStruct * const gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + gptx->PWM_CTRL.BIT.pwm_enable = BASE_CFG_SET; +} + +/** + * @brief Disable GPT. + * @param gptx GPTx register baseAddr. + * @retval None + */ +static inline void DCL_GPT_Disable(GPT_RegStruct * const gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + gptx->PWM_CTRL.BIT.pwm_enable = BASE_CFG_UNSET; +} + +/** + * @brief Get GPT Enable/Disable status. + * @param gptx GPTx register baseAddr. + * @retval None + */ +static inline bool DCL_GPT_GetPwmEnableStatus(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + return gptx->PWM_CTRL.BIT.pwm_enable; +} + +/** + * @brief Set PWM output polarity. + * @param gptx GPTx register baseAddr. + * @param polarity PWM output positive and negative control. + * @retval None + */ +static inline void DCL_GPT_SetPolarity(GPT_RegStruct * const gptx, bool polarity) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_PARAM_CHECK_NO_RET((polarity == BASE_CFG_SET) || (polarity == BASE_CFG_UNSET)); + gptx->PWM_CTRL.BIT.pwm_inv = polarity; +} + +/** + * @brief Get PWM output polarity. + * @param gptx GPTx register baseAddr. + * @retval pwm_inv 0(PWM output positive) or 1(PWM output negative). + */ +static inline bool DCL_GPT_GetPolarity(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + return gptx->PWM_CTRL.BIT.pwm_inv; +} + +/** + * @brief Set PWM Keep. + * @param gptx GPTx register baseAddr. + * @param keep Output square wave mode. + * @retval None + */ +static inline void DCL_GPT_Setkeep(GPT_RegStruct * const gptx, bool keep) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + GPT_PARAM_CHECK_NO_RET((keep == BASE_CFG_SET) || (keep == BASE_CFG_UNSET)); + gptx->PWM_CTRL.BIT.pwm_keep = keep; +} + +/** + * @brief Get PWM Keep. + * @param gptx GPTx register baseAddr. + * @retval 0(Single output) or 1(Continuous output). + */ +static inline bool DCL_GPT_Getkeep(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + return gptx->PWM_CTRL.BIT.pwm_keep; +} + +/** + * @brief Get PWM State0 Period. + * @param gptx GPTx register baseAddr. + * @retval unsigned int period. + */ +static inline unsigned int DCL_GPT_GetState0Period(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + return gptx->pwm_period_st; +} + +/** + * @brief Get PWM duty in State1. + * @param gptx GPTx register baseAddr. + * @retval unsigned int duty. + */ +static inline unsigned int DCL_GPT_GetState1Duty(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + return gptx->pwm_duty_st; +} + +/** + * @brief Get the number of square waves that the module also needs to output. + * @param gptx GPTx register baseAddr. + * @retval unsigned int the number of pwm needs to output. + */ +static inline unsigned int DCL_GPT_GetState2PwmCnt(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + return gptx->PWM_STATE2.BIT.pwm_cnt_st; +} + +/** + * @brief Get the output square wave mode adopted by the internal module of PWM. + * @param gptx GPTx register baseAddr. + * @retval mode 0(Single output) or 1(Continuous output). + */ +static inline unsigned int DCL_GPT_GetState2Keep(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + return gptx->PWM_STATE2.BIT.pwm_keep_st; +} + +/** + * @brief Get Working status of PWM module. + * @param gptx GPTx register baseAddr. + * @retval status 0(idle) or 1(busy). + */ +static inline unsigned int DCL_GPT_GetState2Busy(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + return gptx->PWM_STATE2.BIT.pwm_busy; +} + +/** + * @brief Get the number of output square waves used by the internal module. + * @param gptx GPTx register baseAddr. + * @retval unsigned int the number of period. + */ +static inline unsigned int DCL_GPT_GetState2Period(const GPT_RegStruct *gptx) +{ + GPT_ASSERT_PARAM(IsGPTInstance(gptx)); + return gptx->PWM_STATE2.BIT.pwm_num_st; +} +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_GPT_IP_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/gpt/src/gpt.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/gpt/src/gpt.c new file mode 100644 index 00000000..dd596874 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/gpt/src/gpt.c @@ -0,0 +1,154 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file gpt.c + * @author MCU Driver Team + * @brief GPT module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the GPT. + * + Initialization function of GPT + * + Clock Configuration of GPT + * + Get GPT State and Apply GPT + */ + +#include "gpt.h" + +#define FREQ_1000M (1000 * 1000 * 1000) + +/** + * @brief Init the GPT. + * @param handle GPT Handle. + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Parameter check fail + */ +BASE_StatusType HAL_GPT_Init(GPT_Handle *handle) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + + if (HAL_GPT_Config(handle) == BASE_STATUS_ERROR) { + return BASE_STATUS_ERROR; /* Configuration failed. */ + } + handle->baseAddress->PWM_CTRL.BIT.pwm_enable = 0; + + return BASE_STATUS_OK; +} + +/** + * @brief Start GPT + * @param handle GPT Handle. + * @retval None + */ +void HAL_GPT_Start(GPT_Handle *handle) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + handle->baseAddress->PWM_CTRL.BIT.pwm_enable = BASE_CFG_SET; +} + +/** + * @brief Stop GPT + * @param handle GPT Handle. + * @retval None + */ +void HAL_GPT_Stop(GPT_Handle *handle) +{ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + handle->baseAddress->PWM_CTRL.BIT.pwm_enable = BASE_CFG_UNSET; +} + +/** + * @brief Set basic GPT parameters. + * @param handle GPT Handle. + * @retval BASE_StatusType: BASE_STATUS_OK Success. + * @retval BASE_STATUS_ERROR Configuration failed. + */ +BASE_StatusType HAL_GPT_Config(GPT_Handle *handle) +{ + unsigned long long pwmPeriod; + unsigned long long pwmDuty; + unsigned int freq; + /* Input parameter macro check. */ + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + GPT_PARAM_CHECK_WITH_RET((handle->period > 0), BASE_STATUS_ERROR); + GPT_PARAM_CHECK_WITH_RET((handle->duty > 0), BASE_STATUS_ERROR); + GPT_PARAM_CHECK_WITH_RET(handle->duty <= handle->period, BASE_STATUS_ERROR); /* Duty is must less than period. */ + GPT_PARAM_CHECK_WITH_RET(IsGptPwmNum(handle->pwmNum), BASE_STATUS_ERROR); + GPT_PARAM_CHECK_WITH_RET((handle->pwmPolarity == BASE_CFG_SET) || \ + (handle->pwmPolarity == BASE_CFG_UNSET), BASE_STATUS_ERROR); + GPT_PARAM_CHECK_WITH_RET((handle->pwmKeep == BASE_CFG_SET) || \ + (handle->pwmKeep == BASE_CFG_UNSET), BASE_STATUS_ERROR); + /* Clock frequency of the GPT. */ + freq = HAL_CRG_GetIpFreq((void*)handle->baseAddress); + pwmPeriod = handle->period; + pwmPeriod = (freq * pwmPeriod) / FREQ_1000M; /* The period(us) is converted to the counting period. */ + if (pwmPeriod > GPT_PWM_PERIOD_MAX_VALUE) { + pwmPeriod = GPT_PWM_PERIOD_INVALID_VALUE; + } + /* The value of the duty cycle (percentage) in period. */ + pwmDuty = handle->duty; + pwmDuty = (freq * pwmDuty) / FREQ_1000M; + if (pwmDuty > GPT_PWM_DUTY_MAX_VALUE) { + pwmDuty = GPT_PWM_DUTY_INVALID_VALUE; + } + /* Check the duty and counting period. */ + if (!IsGptPeriod((unsigned int)pwmPeriod) || !IsGptDuty((unsigned int)pwmDuty) || (pwmDuty >= pwmPeriod)) { + return BASE_STATUS_ERROR; + } + /* Writing duty cycle and count period values */ + handle->baseAddress->pwm_period = (unsigned int)pwmPeriod; + handle->baseAddress->pwm_duty = (unsigned int)pwmDuty; + handle->baseAddress->PWM_CFG2.pwm_num = handle->pwmNum; /* Number of output PWM. */ + handle->baseAddress->PWM_CTRL.BIT.pwm_inv = handle->pwmPolarity; + handle->baseAddress->PWM_CTRL.BIT.pwm_keep = handle->pwmKeep; + return BASE_STATUS_OK; +} + +/** + * @brief Get State of GPT. + * @param handle GPT Handle. + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Parameter check fail + */ +BASE_StatusType HAL_GPT_GetConfig(GPT_Handle *handle) +{ + unsigned long long period; + unsigned long long duty; + unsigned int freq; + + GPT_ASSERT_PARAM(handle != NULL); + GPT_ASSERT_PARAM(IsGPTInstance(handle->baseAddress)); + + freq = HAL_CRG_GetIpFreq((void *)handle->baseAddress); + if (freq == 0) { + return BASE_STATUS_ERROR; + } + period = handle->baseAddress->pwm_period; + period = (period * FREQ_1000M + freq - 1) / freq; + handle->period = period; + duty = handle->baseAddress->pwm_duty; + duty = (duty * FREQ_1000M + freq - 1) / freq; + handle->duty = duty; + handle->pwmEnable = handle->baseAddress->PWM_CTRL.BIT.pwm_enable; + handle->pwmPolarity = handle->baseAddress->PWM_CTRL.BIT.pwm_inv; + handle->pwmKeep = handle->baseAddress->PWM_CTRL.BIT.pwm_keep; + handle->pwmNum = handle->baseAddress->PWM_CFG2.pwm_num; + + return BASE_STATUS_OK; +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/i2c/common/inc/i2c.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/i2c/common/inc/i2c.h new file mode 100644 index 00000000..decd4f3b --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/i2c/common/inc/i2c.h @@ -0,0 +1,169 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file i2c.h + * @author MCU Driver Team, + * @brief I2C module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the I2C. + * + Initialization and de-initialization functions. + * + Peripheral transmit and receiving functions. + * + I2C parameter handle definition. + * + Basic Configuration Parameter Enumeration Definition. + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef McuMagicTag_I2C_H +#define McuMagicTag_I2C_H + +/* Includes ------------------------------------------------------------------*/ +#include "dma.h" +#include "i2c_ip.h" + +/** + * @defgroup I2C I2C + * @brief I2C module. + * @{ + */ + +/** + * @defgroup I2C_Common I2C Common + * @brief I2C common external module. + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ + +/** + * @defgroup I2C_Handle_Definition I2C Handle Definition + * @{ + */ + +/** + * @brief Module Status Enumeration Definition + */ +typedef enum { + I2C_STATE_RESET = 0x00000000U, + I2C_STATE_READY = 0x00000001U, + I2C_STATE_BUSY = 0x00000002U, + I2C_STATE_BUSY_MASTER_TX = 0x00000003U, + I2C_STATE_BUSY_MASTER_RX = 0x00000004U, + I2C_STATE_BUSY_SLAVE_TX = 0x00000005U, + I2C_STATE_BUSY_SLAVE_RX = 0x00000006U, + I2C_STATE_TIMEOUT = 0x00000007U, + I2C_STATE_ERROR = 0x00000008U, +} I2C_StateType; + +/** + * @brief Module handle structure definition + */ +typedef struct _I2C_Handle { + I2C_RegStruct *baseAddress; /**< Register base address. */ + I2C_ModeSelectType functionMode; /**< Set master or slave. */ + I2C_AddressMode addrMode; /**< 7bit or 10bit. */ + unsigned int slaveOwnAddress; /**< Own address as slave. */ + unsigned int sdaHoldTime; /**< SDA hold time. */ + unsigned int freq; /**< Operating Frequency. */ + unsigned int ignoreAckFlag; /**< Ignore the response flag bit. */ + unsigned int generalCallMode; /**< General call mode. */ + + volatile unsigned char *transferBuff; /**< Transmission Data buffer. */ + volatile unsigned int transferSize; /**< Transmission Data Length. */ + volatile unsigned int transferCount; /**< Transferred Data Count. */ + + unsigned int timeout; /**< Timeout period. */ + unsigned int rxWaterMark; /**< RX threshold configuration. */ + unsigned int txWaterMark; /**< TX threshold configuration. */ + unsigned int rxDmaCh; /**< RX DMA channel */ + unsigned int txDmaCh; /**< TX DMA channel */ + DMA_Handle *dmaHandle; /**< DMA handle */ + + I2C_StateType state; /**< Running Status. */ + BASE_StatusType errorCode; /**< Error Code. */ + I2C_UserCallBack userCallBack; /**< User-defined callback function. */ + I2C_ExtendHandle handleEx; /**< Extend handle, configuring some special parameters. */ +} I2C_Handle; +/** + * @} + */ + +/** + * @defgroup I2C_API_Declaration I2C HAL API + * @{ + */ +/** + * @brief Callback Function Type Definition. + */ +typedef void (*I2C_CallbackFunType)(void *handle); + +/* Function Interface Definition -------------------------------------------------------*/ +BASE_StatusType HAL_I2C_Init(I2C_Handle *handle); +BASE_StatusType HAL_I2C_Deinit(I2C_Handle *handle); +BASE_StatusType HAL_I2C_RegisterCallback(I2C_Handle *handle, I2C_CallbackId callbackID, I2C_CallbackFunType pcallback); +BASE_StatusType HAL_I2C_MasterReadBlocking(I2C_Handle *handle, + unsigned short devAddr, + unsigned char *rData, + unsigned int dataSize, + unsigned int timeout); +BASE_StatusType HAL_I2C_MasterWriteBlocking(I2C_Handle *handle, + unsigned short devAddr, + unsigned char *wData, + unsigned int dataSize, + unsigned int timeout); +BASE_StatusType HAL_I2C_SlaveReadBlocking(I2C_Handle *handle, + unsigned char *rData, + unsigned int dataSize, + unsigned int timeout); +BASE_StatusType HAL_I2C_SlaveWriteBlocking(I2C_Handle *handle, + unsigned char *wData, + unsigned int dataSize, + unsigned int timeout); + +BASE_StatusType HAL_I2C_MasterReadIT(I2C_Handle *handle, + unsigned short devAddr, + unsigned char *rData, + unsigned int dataSize); +BASE_StatusType HAL_I2C_MasterWriteIT(I2C_Handle *handle, + unsigned short devAddr, + unsigned char *wData, + unsigned int dataSize); +BASE_StatusType HAL_I2C_SlaveReadIT(I2C_Handle *handle, unsigned char *rData, unsigned int dataSize); +BASE_StatusType HAL_I2C_SlaveWriteIT(I2C_Handle *handle, unsigned char *wData, unsigned int dataSize); + +BASE_StatusType HAL_I2C_MasterReadDMA(I2C_Handle *handle, + unsigned short devAddr, + unsigned char *rData, + unsigned int dataSize); +BASE_StatusType HAL_I2C_MasterWriteDMA(I2C_Handle *handle, + unsigned short devAddr, + unsigned char *wData, + unsigned int dataSize); +BASE_StatusType HAL_I2C_SlaveReadDMA(I2C_Handle *handle, unsigned char *rData, unsigned int dataSize); +BASE_StatusType HAL_I2C_SlaveWriteDMA(I2C_Handle *handle, unsigned char *wData, unsigned int dataSize); +void HAL_I2C_IrqHandler(void *handle); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* #ifndef McuMagicTag_I2C_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/i2c/inc/i2c_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/i2c/inc/i2c_ip.h new file mode 100644 index 00000000..fc87387e --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/i2c/inc/i2c_ip.h @@ -0,0 +1,1337 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file i2c_ip.h + * @author MCU Driver Team + * @brief I2C module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the I2C. + * + Register definition structure + * + Timing command enumeration + * + Direct configuration layer interface + * + Basic parameter configuration macro + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef McuMagicTag_I2C_IP_H +#define McuMagicTag_I2C_IP_H + +/* Includes ------------------------------------------------------------------*/ +#include "baseinc.h" + +/* Macro definitions --------------------------------------------------------- */ +#ifdef I2C_PARAM_CHECK +#define I2C_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define I2C_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define I2C_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define I2C_ASSERT_PARAM(para) ((void)0U) +#define I2C_PARAM_CHECK_NO_RET(para) ((void)0U) +#define I2C_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +/** + * @addtogroup I2C + * @{ + */ + +/** + * @defgroup I2C_IP I2C_IP + * @brief I2C_IP: i2c_v0 + * @{ + */ + +#define I2C_IGNORE_NAK_ENABLE BASE_CFG_ENABLE /**< Ignore acknowledgment configuration enable. */ +#define I2C_IGNORE_NAK_DISABLE BASE_CFG_DISABLE /**< Ignore acknowledgment configuration disable. */ + +#define I2C_MSG_STOP_FLAG_ENABLG BASE_CFG_ENABLE /**< Last frame data flag enable. */ +#define I2C_MSG_STOP_FLAG_DISABLE BASE_CFG_DISABLE /**< Last frame data flag disable. */ + +#define I2C_STANDARD_FREQ_TH 100000 /**< Standard mode,the frequency band is less than or equal to 100 kHz. */ +#define I2C_SDA_HOLD_DURATION 0x0000000AU /**< Sda hold duration.The value is fixed to 0xa. */ + +#define I2C_INTR_RAW_ALL_ENABLE 0x00001FFFU /**< 1111111111111 */ +#define I2C_INTR_RAWALL_DISABLE 0x00000000U /**< 0000000000000 */ + +#define I2C_INTR_EN_ALL_ENABLE 0x00001FFFU /**< 1111111111111 */ +#define I2C_INTR_EN_ALL_DISABLE 0x00000000U /**< 0000000000000 */ + +#define I2C_MAX_CMD_OFFSET_LEN 32 + +#define I2C_SDA_HOLD_DURATION_POS 8 +#define I2C_SDA_HOLD_DURATION_MASK (0xFFFF << I2C_SDA_HOLD_DURATION_POS) + +#define I2C_DEV_ADDR_BYTE1_POS 0 +#define I2C_DEV_ADDR_BYTE1_MASK (0xFF << I2C_DEV_ADDR_BYTE1_POS) +#define I2C_DEV_ADDR_BYTE2_POS 8 +#define I2C_DEV_ADDR_BYTE2_MASK (0xFF << I2C_DEV_ADDR_BYTE2_POS) +#define I2C_DEV_ADDR_BYTE3_POS 16 +#define I2C_DEV_ADDR_BYTE3_MASK (0xFF << I2C_DEV_ADDR_BYTE3_POS) +#define I2C_DEV_ADDR_BYTE4_POS 24 +#define I2C_DEV_ADDR_BYTE4_MASK (0xFF << I2C_DEV_ADDR_BYTE4_POS) + +#define I2C_DATA_BUF_BYTE1_POS 0 +#define I2C_DATA_BUF_BYTE1_MASK (0xFF << I2C_DATA_BUF_BYTE1_POS) +#define I2C_DATA_BUF_BYTE2_POS 8 +#define I2C_DATA_BUF_BYTE2_MASK (0xFF << I2C_DATA_BUF_BYTE2_POS) +#define I2C_DATA_BUF_BYTE3_POS 16 +#define I2C_DATA_BUF_BYTE3_MASK (0xFF << I2C_DATA_BUF_BYTE3_POS) +#define I2C_DATA_BUF_BYTE4_POS 24 +#define I2C_DATA_BUF_BYTE4_MASK (0xFF << I2C_DATA_BUF_BYTE4_POS) + +#define I2C_PATTERN_DATA_BYTE1_POS 0 +#define I2C_PATTERN_DATA_BYTE1_MASK (0xFF << I2C_PATTERN_DATA_BYTE1_POS) +#define I2C_PATTERN_DATA_BYTE2_POS 8 +#define I2C_PATTERN_DATA_BYTE2_MASK (0xFF << I2C_PATTERN_DATA_BYTE2_POS) +#define I2C_PATTERN_DATA_BYTE3_POS 16 +#define I2C_PATTERN_DATA_BYTE3_MASK (0xFF << I2C_PATTERN_DATA_BYTE3_POS) +#define I2C_PATTERN_DATA_BYTE4_POS 24 +#define I2C_PATTERN_DATA_BYTE4_MASK (0xFF << I2C_PATTERN_DATA_BYTE4_POS) + +#define I2C_PATTERN_DATA_BYTE5_POS 0 +#define I2C_PATTERN_DATA_BYTE5_MASK (0xFF << I2C_PATTERN_DATA_BYTE5_POS) +#define I2C_PATTERN_DATA_BYTE6_POS 8 +#define I2C_PATTERN_DATA_BYTE6_MASK (0xFF << I2C_PATTERN_DATA_BYTE6_POS) +#define I2C_PATTERN_DATA_BYTE7_POS 16 +#define I2C_PATTERN_DATA_BYTE7_MASK (0xFF << I2C_PATTERN_DATA_BYTE7_POS) +#define I2C_PATTERN_DATA_BYTE8_POS 24 +#define I2C_PATTERN_DATA_BYTE8_MASK (0xFF << I2C_PATTERN_DATA_BYTE8_POS) + +/** + * @defgroup I2C_Param_Def I2C Parameters Definition + * @brief Definition of I2C configuration parameters. + * @{ + */ +/* Typedef definitions -------------------------------------------------------*/ +/** + * @brief Address Mode Selection Enumeration Definition + */ +typedef enum { + I2C_7_BITS = 0x00000000U, + I2C_10_BITS = 0x00000001U +} I2C_AddressMode; + +/** + * @brief I2C DMA operation type enumeration definition + */ +typedef enum { + I2C_DMA_OP_NONE = 0x00000000U, + I2C_DMA_OP_READ = 0x00000003U, + I2C_DMA_OP_WRITE = 0x00000002U +} I2C_DmaOperationType; + +/** + * @brief Callback Function ID Enumeration Definition + */ +typedef enum { + I2C_MASTER_TX_COMPLETE_CB_ID = 0x00000000U, + I2C_MASTER_RX_COMPLETE_CB_ID = 0x00000001U, + I2C_SLAVE_TX_COMPLETE_CB_ID = 0x00000002U, + I2C_SLAVE_RX_COMPLETE_CB_ID = 0x00000003U, + I2C_ERROR_CB_ID = 0x00000004U, +} I2C_CallbackId; + +/** + * @brief I2C operation timing enumeration definition + */ +typedef enum { + I2C_CMD_EXIT = 0x00000000U, /**< End command for logical exit. */ + I2C_CMD_S = 0x00000001U, /**< Bus START command. */ + I2C_CMD_WDA4 = 0x00000002U, /**< Send the dev_addr_byte4 command. */ + I2C_CMD_WDA3 = 0x00000003U, /**< Send the dev_addr_byte3 command. */ + I2C_CMD_WDA2 = 0x00000004U, /**< Send the dev_addr_byte2 command. */ + I2C_CMD_WDA1 = 0x00000005U, /**< Send the dev_addr_byte1 command. */ + I2C_CMD_WDB4 = 0x00000006U, /**< Send the data_buf_byte4 command. */ + I2C_CMD_WDB3 = 0x00000007U, /**< Send the data_buf_byte3 command. */ + I2C_CMD_WDB2 = 0x00000008U, /**< Send the data_buf_byte2 command. */ + I2C_CMD_WDB1 = 0x00000009U, /**< Send the data_buf_byte1 command. */ + I2C_CMD_WPD8 = 0x0000000AU, /**< Send the pattern_data_byte8 command. */ + I2C_CMD_WPD7 = 0x0000000BU, /**< Send the pattern_data_byte7 command. */ + I2C_CMD_WPD6 = 0x0000000CU, /**< Send the pattern_data_byte6 command. */ + I2C_CMD_WPD5 = 0x0000000DU, /**< Send the pattern_data_byte5 command. */ + I2C_CMD_WPD4 = 0x0000000EU, /**< Send the pattern_data_byte4 command. */ + I2C_CMD_WPD3 = 0x0000000FU, /**< Send the pattern_data_byte3 command. */ + I2C_CMD_WPD2 = 0x00000010U, /**< Send the pattern_data_byte2 command. */ + I2C_CMD_WPD1 = 0x00000011U, /**< Send the pattern_data_byte1 command. */ + I2C_CMD_RD = 0x00000012U, /**< Command for receiving 1-byte data. */ + I2C_CMD_RACK = 0x00000013U, /**< Receive low-level acknowledgment command. */ + I2C_CMD_RNACK = 0x00000014U, /**< Receive high level no acknowledgment command.*/ + I2C_CMD_RNC = 0x00000015U, /**< Receives the response command. The high or low level does not matter.*/ + I2C_CMD_SACK = 0x00000016U, /**< Send low-level acknowledgment command. */ + I2C_CMD_SNACK = 0x00000017U, /**< Send high-level no-acknowledge command. */ + I2C_CMD_JMPN1 = 0x00000018U, /**< Jump command for a limited number of times. + The purpose is indicated by the DST1 register. + and the number of times is indicated by the LOOP1 register. */ + I2C_CMD_JMPN2 = 0x00000019U, /**< Jump command for a limited number of times. + The purpose is indicated by the DST2 register. + and the number of times is indicated by the LOOP2 register. */ + I2C_CMD_JMPN3 = 0x0000001AU, /**< Jump command for a limited number of times. + The purpose is indicated by the DST3 register. + and the number of times is indicated by the LOOP3 register. */ + I2C_CMD_UDB1 = 0x0000001DU, /**< Update data from the TX FIFO to data_buf_byte1. */ + I2C_CMD_SR = 0x0000001EU, /**< Bus Repeated START. */ + I2C_CMD_P = 0x0000001FU /**< Bus STOP. */ +} I2C_CmdType; + +/** + * @brief I2C mode selection enumeration definition + */ +typedef enum { + I2C_MODE_SELECT_NONE = 0x00000000U, + I2C_MODE_SELECT_MASTER_ONLY = 0x00000001U, + I2C_MODE_SELECT_SLAVE_ONLY = 0x00000002U, + I2C_MODE_SELECT_MASTER_SLAVE = 0x00000003U +} I2C_ModeSelectType; + +/** + * @brief I2C extend handle, configuring some special parameters. + */ +typedef struct { +} I2C_ExtendHandle; + +/** + * @brief User-defined callback function. + */ +typedef struct { + void (*TxCplCallback)(void* handle); /**< Sending completion callback function. */ + void (*RxCplCallback)(void* handle); /**< Receive completion callback function. */ + void (*ErrorCallback)(void* handle); /**< Error callback function. */ +} I2C_UserCallBack; + +/** + * @} + */ + +/** + * @defgroup I2C_Reg_Def I2C Register Definition + * @brief register mapping structure + * @{ + */ + +/** + * @brief I2C global configuration registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int i2c_enable : 1; /**< Enable Control, 0:disable, 1:enble. */ + unsigned int reserved0 : 7; + unsigned int sda_hold_duration : 16; /**< SDA hold time. */ + unsigned int reserved1 : 8; + } BIT; +} volatile I2C_GLB_REG; + +/** + * @brief I2C high level duration registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int i2c_high_duration : 16; /**< SCL high level duration. */ + unsigned int reserved0 : 16; + } BIT; +} volatile I2C_HCNT_REG; + +/** + * @brief I2C low level duration registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int i2c_low_duration : 16; /**< SCL Low Level Duration. */ + unsigned int reserved0 : 16; + } BIT; +} volatile I2C_LCNT_REG; + +/** + * @brief I2C device address registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int dev_addr_byte1 : 8; /**< Device Address Byte 1. */ + unsigned int dev_addr_byte2 : 8; /**< Device Address Byte 2. */ + unsigned int dev_addr_byte3 : 8; /**< Device Address Byte 3. */ + unsigned int dev_addr_byte4 : 8; /**< Device Address Byte 4. */ + } BIT; +} volatile I2C_DEV_ADDR_REG; + +/** + * @brief I2C data buffer registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int data_buf_byte1 : 8; /**< Data buffer byte 1. */ + unsigned int data_buf_byte2 : 8; /**< Data buffer byte 2. */ + unsigned int data_buf_byte3 : 8; /**< Data buffer byte 3. */ + unsigned int data_buf_byte4 : 8; /**< Data buffer byte 4. */ + } BIT; +} volatile I2C_DATA_BUF_REG; + +/** + * @brief I2C indicates the pattern data 1 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pattern_data_byte1 : 8; /**< PATTERN data byte 1. */ + unsigned int pattern_data_byte2 : 8; /**< PATTERN data byte 2. */ + unsigned int pattern_data_byte3 : 8; /**< PATTERN data byte 3. */ + unsigned int pattern_data_byte4 : 8; /**< PATTERN data byte 4. */ + } BIT; +} volatile I2C_PATTERN_DATA1_REG; + +/** + * @brief I2C indicates the pattern data 1 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pattern_data_byte5 : 8; /**< PATTERN data byte 5. */ + unsigned int pattern_data_byte6 : 8; /**< PATTERN data byte 6. */ + unsigned int pattern_data_byte7 : 8; /**< PATTERN data byte 7. */ + unsigned int pattern_data_byte8 : 8; /**< PATTERN data byte 8. */ + } BIT; +} volatile I2C_PATTERN_DATA2_REG; + +/** + * @brief I2C TX FIFO data registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int tx_fifo : 8; /**< TX FIFO entry. */ + unsigned int reserved0 : 24; + } BIT; +} volatile I2C_TX_FIFO_REG; + +/** + * @brief I2C RX FIFO data registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rx_fifo : 8; /**< RX FIFO entry. */ + unsigned int reserved0 : 24; + } BIT; +} volatile I2C_RX_FIFO_REG; + +/** + * @brief I2C timing command registers union structure definition. + */ +typedef union { + unsigned int reg[32]; + struct { + unsigned int timing_cmd : 5; /**< Timing Commands. */ + unsigned int reserved0 : 27; + } BIT[32]; +} volatile I2C_TIMING_CMD_REG; + +/** + * @brief I2C cycle count 1 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int loop_num1 : 32; /**< Specifies the number of cycles. */ + } BIT; +} volatile I2C_LOOP1_REG; + +/** + * @brief I2C jump destination 1 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int dst_timing_cmd1 : 5; /**< Specifies which timing command to jump. */ + unsigned int reserved0 : 27; + } BIT; +} volatile I2C_DST1_REG; + +/** + * @brief I2C cycle count 2 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int loop_num2 : 32; /**< Specifies the number of cycles. */ + } BIT; +} volatile I2C_LOOP2_REG; + +/** + * @brief I2C jump destination 2 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int dst_timing_cmd2 : 5; /**< Specifies which timing command to jump. */ + unsigned int reserved0 : 27; + } BIT; +} volatile I2C_DST2_REG; + +/** + * @brief I2C cycle count 3 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int loop_num3 : 32; /**< Specifies which timing command to jump. */ + } BIT; +} volatile I2C_LOOP3_REG; + +/** + * @brief I2C jump destination 3 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int dst_timing_cmd3 : 5; /**< Specifies which timing command to jump. */ + unsigned int reserved0 : 27; + } BIT; +} volatile I2C_DST3_REG; + +/** + * @brief I2C TX FIFO threshold registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int tx_watermark : 6; /**< TX FIFO Threshold. */ + unsigned int reserved0 : 26; + } BIT; +} volatile I2C_TX_WATERMARK_REG; + +/** + * @brief I2C RX FIFO threshold registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rx_watermark : 6; /**< RX FIFO Threshold. */ + unsigned int reserved0 : 26; + } BIT; +} volatile I2C_RX_WATERMARK_REG; + +/** + * @brief I2C control 1 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int start : 1; /**< Start-up control. */ + unsigned int reserved1 : 7; + unsigned int dma_operation : 2; /**< DMA operation control. */ + unsigned int reserved0 : 22; + } BIT; +} volatile I2C_CTRL1_REG; + +/** + * @brief I2C control 2 registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int force_sda_oen : 1; /**< Controls the SDA pin level, 0:low level, 1:high level. */ + unsigned int reserved0 : 3; + unsigned int force_scl_oen : 1; /**< Controls the SCL pin level, 0:low level, 1:high level. */ + unsigned int reserved1 : 3; + unsigned int gpio_mode : 1; /**< Use gpio mode, 0:disable, 1:enable. */ + unsigned int reserved2 : 7; + unsigned int i2c_sda_in : 1; /**< Monitors external the SDA level, 0:low level, 1:high level. */ + unsigned int reserved3 : 3; + unsigned int i2c_scl_in : 1; /**< Monitors external the SCL level, 0:low level, 1:high level. */ + unsigned int reserved4 : 3; + unsigned int i2c_sda_oen : 1; /**< Monitors internal the SDA level, 0:low level, 1:high level. */ + unsigned int reserved5 : 3; + unsigned int i2c_scl_oen : 1; /**< Monitors internal the SCL level, 0:low level, 1:high level. */ + unsigned int reserved6 : 3; + } BIT; +} volatile I2C_CTRL2_REG; + +/** + * @brief I2C FIFO status registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rx_fifo_vld_num : 7; /**< Number of valid values in the RX FIFO. */ + unsigned int reserved0 : 1; + unsigned int tx_fifo_vld_num : 7; /**< Number of valid values in the TX FIFO. */ + unsigned int reserved1 : 1; + unsigned int rx_fifo_not_empty : 1; /**< RX FIFO non-empty indicator, 0:empty, 1:non-empty. */ + unsigned int rx_fifo_not_full : 1; /**< RX FIFO non-full indicator, 0:full, 1:non-full. */ + unsigned int tx_fifo_not_empty : 1; /**< TX FIFO non-empty indicator, 0:empty, 1:non-empty. */ + unsigned int tx_fifo_not_full : 1; /**< TX FIFO non-full indicator, 0:full, 1:non-full. */ + unsigned int reserved2 : 12; + } BIT; +} volatile I2C_FIFO_STAT_REG; + +/** + * @brief I2C raw interrupt registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ack_bit_unmatch_raw : 1; /**< Ack unmatch interrupt, 0:no interrupt, 1:interrupt. */ + unsigned int reserved0 : 1; + unsigned int rx_gt_watermark_raw : 1; /**< Above the rx watermark, 0:no interrupt, 1:interrupt. */ + unsigned int reserved1 : 1; + unsigned int tx_lt_watermark_raw : 1; /**< Below the tx watermark, 0:no interrupt, 1:interrupt. */ + unsigned int reserved2 : 4; + unsigned int stop_det_raw : 1; /**< Stop detected. */ + unsigned int start_det_raw : 1; /**< Start detected. */ + unsigned int arb_lost_raw : 1; /**< Arbitration loss. */ + unsigned int all_cmd_done_raw : 1; /**< Timing command sequence execution completed. */ + unsigned int reserved3 : 19; + } BIT; +} volatile I2C_INTR_RAW_REG; + +/** + * @brief I2C interrupt enable registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ack_bit_unmatch_en : 1; /**< Interrupt enable, 0:disable, 1:enable. */ + unsigned int reserved0 : 1; + unsigned int rx_gt_watermark_en : 1; /**< Interrupt enable, 0:disable, 1:enable. */ + unsigned int reserved1 : 1; + unsigned int tx_lt_watermark_en : 1; /**< Interrupt enable, 0:disable, 1:enable. */ + unsigned int reserved2 : 4; + unsigned int stop_det_en : 1; /**< Interrupt enable, 0:disable, 1:enable. */ + unsigned int start_det_en : 1; /**< Interrupt enable, 0:disable, 1:enable. */ + unsigned int arb_lost_en : 1; /**< Interrupt enable, 0:disable, 1:enable. */ + unsigned int all_cmd_done_en : 1; /**< Interrupt enable, 0:disable, 1:enable. */ + unsigned int reserved3 : 19; + } BIT; +} volatile I2C_INTR_EN_REG; + +/** + * @brief I2C interrupt status registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ack_bit_unmatch : 1; /**< Interrupt status flag, 0:no interrupt, 1:interrupt. */ + unsigned int reserved0 : 1; + unsigned int rx_gt_watermark : 1; /**< Interrupt status flag, 0:no interrupt, 1:interrupt. */ + unsigned int reserved1 : 1; + unsigned int tx_lt_watermark : 1; /**< Interrupt status flag, 0:no interrupt, 1:interrupt. */ + unsigned int reserved2 : 4; + unsigned int stop_det : 1; /**< Interrupt status flag, 0:no interrupt, 1:interrupt. */ + unsigned int start_det : 1; /**< Interrupt status flag, 0:no interrupt, 1:interrupt. */ + unsigned int arb_lost : 1; /**< Interrupt status flag, 0:no interrupt, 1:interrupt. */ + unsigned int all_cmd_done : 1; /**< Interrupt status flag, 0:no interrupt, 1:interrupt. */ + unsigned int reserved3 : 19; + } BIT; +} volatile I2C_INTR_STAT_REG; + +/** + * @brief I2C Register definition structure + */ +typedef struct { + I2C_GLB_REG I2C_GLB; /**< Global configuration register. Offset Address: 0x0000. */ + I2C_HCNT_REG I2C_HCNT; /**< High level duration register. Offset Address: 0x0004. */ + I2C_LCNT_REG I2C_LCNT; /**< Low level duration register. Offset Address: 0x0008. */ + unsigned char space0[4]; + I2C_DEV_ADDR_REG I2C_DEV_ADDR; /**< Device address register. Offset Address: 0x0010. */ + I2C_DATA_BUF_REG I2C_DATA_BUF; /**< Data buffer register. Offset Address: 0x0014. */ + I2C_PATTERN_DATA1_REG I2C_PATTERN_DATA1; /**< PATTERN data 1 register. Offset Address: 0x0018. */ + I2C_PATTERN_DATA2_REG I2C_PATTERN_DATA2; /**< PATTERN data 2 register. Offset Address: 0x001C. */ + I2C_TX_FIFO_REG I2C_TX_FIFO; /**< TX FIFO data register. Offset Address: 0x0020. */ + I2C_RX_FIFO_REG I2C_RX_FIFO; /**< RX FIFO data register. Offset Address: 0x0024. */ + unsigned char space1[8]; + I2C_TIMING_CMD_REG I2C_TIMING_CMD; /**< Timing command register. Offset Address: 0x0030. */ + I2C_LOOP1_REG I2C_LOOP1; /**< Cycle count 1 register. Offset Address: 0x00b0. */ + I2C_DST1_REG I2C_DST1; /**< Jump destination 1 register. Offset Address: 0x00b4. */ + I2C_LOOP2_REG I2C_LOOP2; /**< Cycle count 2 register. Offset Address: 0x00b8. */ + I2C_DST2_REG I2C_DST2; /**< Jump destination 2 register. Offset Address: 0x00bc. */ + I2C_LOOP3_REG I2C_LOOP3; /**< Cycle count 3 register. Offset Address: 0x00c0. */ + I2C_DST3_REG I2C_DST3; /**< Jump destination 3 register. Offset Address: 0x00c4. */ + I2C_TX_WATERMARK_REG I2C_TX_WATERMARK; /**< TX FIFO threshold register. Offset Address: 0x00c8. */ + I2C_RX_WATERMARK_REG I2C_RX_WATERMARK; /**< RX FIFO threshold register. Offset Address: 0x00cc. */ + I2C_CTRL1_REG I2C_CTRL1; /**< Control 1 register. Offset Address: 0x00d0. */ + I2C_CTRL2_REG I2C_CTRL2; /**< Control 2 register. Offset Address: 0x00d4. */ + I2C_FIFO_STAT_REG I2C_FIFO_STAT; /**< FIFO status register.Offset Address: 0x00d8. */ + unsigned char space2[4]; + I2C_INTR_RAW_REG I2C_INTR_RAW; /**< Raw interrupt register. Offset Address: 0x00e0. */ + I2C_INTR_EN_REG I2C_INTR_EN; /**< Interrupt enable register. Offset Address: 0x00e4. */ + I2C_INTR_STAT_REG I2C_INTR_STAT; /**< Interrupt status register. Offset Address: 0x00e8 .*/ +} volatile I2C_RegStruct; +/** + * @} + */ + +/* Parameter check definition-------------------------------------------*/ +/** + * @brief Check address mode selection. + * @param addrMode I2C instance + * @retval true + * @retval false + */ +static inline bool IsI2cAddressMode(I2C_AddressMode addrMode) +{ + return (addrMode == I2C_7_BITS || + addrMode == I2C_10_BITS); +} + +/** + * @brief Check i2c sda hold time. + * @param sdaHoldTime I2C instance + * @retval true + * @retval false + */ +static inline bool IsI2cSdaHoldTime(unsigned int sdaHoldTime) +{ + return (sdaHoldTime <= 0xFFFF); /* SdaHoldTime value is 0 to 0xFFFF */ +} + +/** + * @brief Check i2c freq. + * @param freq I2C freq + * @retval true + * @retval false + */ +static inline bool IsI2cFreq(unsigned int freq) +{ + return (freq > 0); +} + +/** + * @brief Check i2c ignore ack flag. + * @param ignoreAckFlag I2C ignore ack flag. + * @retval true + * @retval false + */ +static inline bool IsI2cIgnoreAckFlag(unsigned int ignoreAckFlag) +{ + return (ignoreAckFlag == I2C_IGNORE_NAK_ENABLE || + ignoreAckFlag == I2C_IGNORE_NAK_DISABLE); +} + +/** + * @brief Check i2c tx water mark. + * @param txWaterMark I2C tx water mark. + * @retval true + * @retval false + */ +static inline bool IsI2cTxWaterMark(unsigned int txWaterMark) +{ + return (txWaterMark <= 0x3F); /* The txWaterMark value is 0 to 0x3F */ +} + +/** + * @brief Check i2c rx water mark. + * @param rxWaterMark I2C rx water mark. + * @retval true + * @retval false + */ +static inline bool IsI2cRxWaterMark(unsigned int rxWaterMark) +{ + return (rxWaterMark <= 0x3F); /* The rxWaterMark value is 0 to 0x3F */ +} + +/** + * @brief DCL I2C enable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_Enable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_GLB.BIT.i2c_enable = BASE_CFG_SET; +} + +/** + * @brief DCL I2C disable. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_Disable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_GLB.BIT.i2c_enable = BASE_CFG_UNSET; +} + +/** + * @brief DCL I2C get enable state. + * @param i2cx I2C register base address. + * @retval enable state 0 or 1. + */ +static inline int DCL_I2C_GetEnableState(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_GLB.BIT.i2c_enable; +} + +/** + * @brief DCL Configuring i2c SDA Hold Time. + * @param i2cx I2C register base address. + * @param sdaHoldTime Sda hold time. + * @retval None. + */ +static inline void DCL_I2C_SetSdaHoldDuration(I2C_RegStruct *i2cx, unsigned short sdaHoldTime) +{ + unsigned int glbReg; + unsigned int temp; + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + /* Read the entire register and write it back. */ + temp = ((unsigned int)sdaHoldTime) << I2C_SDA_HOLD_DURATION_POS; + glbReg = (i2cx->I2C_GLB.reg & (~I2C_SDA_HOLD_DURATION_MASK)) | temp; + i2cx->I2C_GLB.reg = glbReg; +} + +/** + * @brief Get DCL Configuring i2c SDA Hold Time. + * @param i2cx I2C register base address. + * @retval Sda hold time,0-65535. + */ +static inline int DCL_I2C_GetSdaHoldDuration(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return ((i2cx->I2C_GLB.reg >> I2C_SDA_HOLD_DURATION_POS) & 0xFFFF); /* 0xFFFF is mask of sda hold time. */ +} + +/** + * @brief DCL Configuring i2c SCL High Hold Time. + * @param i2cx I2C register base address. + * @param sclHighTime Scl high hold time. + * @retval None. + */ +static inline void DCL_I2C_SetHighDuration(I2C_RegStruct *i2cx, unsigned short sclHighTime) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_HCNT.BIT.i2c_high_duration = sclHighTime; +} + +/** + * @brief DCL get i2c SCL High Hold Time. + * @param i2cx I2C register base address. + * @retval Scl high hold time,0-65535. + */ +static inline int DCL_I2C_GetHighDuration(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_HCNT.BIT.i2c_high_duration; +} + +/** + * @brief DCL Configuring i2c SCL low Hold Time. + * @param i2cx I2C register base address. + * @param sclLowTime scl low hold time. + * @retval None. + */ +static inline void DCL_I2C_SetLowDuration(I2C_RegStruct *i2cx, unsigned short sclLowTime) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_LCNT.BIT.i2c_low_duration = sclLowTime; +} + +/** + * @brief DCL Get i2c SCL low Hold Time. + * @param i2cx I2C register base address. + * @retval Scl low hold time,0-65535. + */ +static inline int DCL_I2C_GetLowDuration(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_LCNT.BIT.i2c_low_duration; +} + +/** + * @brief DCL Set I2C Slave Address. + * @param i2cx I2C register base address. + * @param devAddr Slave address + * @retval None. + */ +static inline void DCL_I2C_SetDevAddr(I2C_RegStruct *i2cx, unsigned int devAddr) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_DEV_ADDR.reg = devAddr; +} + +/** + * @brief DCL Get I2C Slave Address. + * @param i2cx I2C register base address. + * @retval Slave address. + */ +static inline unsigned int DCL_I2C_GetDevAddr(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_DEV_ADDR.reg; +} + +/** + * @brief DCL Set I2C data buffer. + * @param i2cx I2C register base address. + * @param dataBuff Buffer data. + * @retval None. + */ +static inline void DCL_I2C_SetDataBuff(I2C_RegStruct *i2cx, unsigned int dataBuff) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_DATA_BUF.reg = dataBuff; +} + +/** + * @brief DCL Get I2C data buffer. + * @param i2cx I2C register base address. + * @retval Buffer data. + */ +static inline unsigned int DCL_I2C_GetDataBuff(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_DATA_BUF.reg; +} + +/** + * @brief DCL Set I2C pattern data1. + * @param i2cx I2C register base address. + * @param patternData Pattern data1. + * @retval None. + */ +static inline void DCL_I2C_SetPatternData1(I2C_RegStruct *i2cx, unsigned int patternData) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_PATTERN_DATA1.reg = patternData; +} + +/** + * @brief DCL Get I2C pattern data1. + * @param i2cx I2C register base address. + * @retval Pattern data1. + */ +static inline unsigned int DCL_I2C_GetPatternData1(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_PATTERN_DATA1.reg; +} + +/** + * @brief DCL Set I2C pattern data2. + * @param i2cx I2C register base address. + * @param patternData Pattern data2. + * @retval None. + */ +static inline void DCL_I2C_SetPatternData2(I2C_RegStruct *i2cx, unsigned int patternData) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_PATTERN_DATA2.reg = patternData; +} + +/** + * @brief DCL Get I2C pattern data2. + * @param i2cx I2C register base address. + * @retval Pattern data2. + */ +static inline unsigned int DCL_I2C_GetPatternData2(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_PATTERN_DATA2.reg; +} + +/** + * @brief DCL Set I2C Tx fifo. + * @param i2cx I2C register base address. + * @param fifoData Tx fifo data. + * @retval None. + */ +static inline void DCL_I2C_SetTxFifo(I2C_RegStruct *i2cx, unsigned char fifoData) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_TX_FIFO.BIT.tx_fifo = fifoData; +} + +/** + * @brief DCL Get I2C Rx fifo. + * @param i2cx I2C register base address. + * @retval Rx fifo data. + */ +static inline int DCL_I2C_GetRxFifo(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_RX_FIFO.BIT.rx_fifo; +} + +/** + * @brief DCL Set I2C timing cmd. + * @param i2cx I2C register base address. + * @param cmd Timing cmd + * @param offset Instruction storage offset position + * @retval None. + */ +static inline void DCL_I2C_SetTimingCmd(I2C_RegStruct *i2cx, I2C_CmdType cmd, unsigned char offset) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + I2C_ASSERT_PARAM(offset < I2C_MAX_CMD_OFFSET_LEN); + i2cx->I2C_TIMING_CMD.BIT[offset].timing_cmd = cmd; +} + +/** + * @brief DCL Get I2C timing cmd. + * @param i2cx I2C register base address. + * @param offset Instruction storage offset position + * @retval Timing cmd. + */ +static inline unsigned int DCL_I2C_GetTimingCmd(I2C_RegStruct *i2cx, unsigned char offset) +{ + I2C_ASSERT_PARAM(offset < I2C_MAX_CMD_OFFSET_LEN); + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_TIMING_CMD.BIT[offset].timing_cmd; +} + +/** + * @brief DCL Set I2C timing loop1 number. + * @param i2cx I2C register base address. + * @param loopValue Number of loop + * @retval None. + */ +static inline void DCL_I2C_SetLoop1(I2C_RegStruct *i2cx, unsigned int loopValue) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_LOOP1.BIT.loop_num1 = loopValue; +} + +/** + * @brief DCL Get I2C timing loop1 number. + * @param i2cx I2C register base address. + * @retval Number of loop. + */ +static inline unsigned int DCL_I2C_GetLoop1(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_LOOP1.BIT.loop_num1; +} + +/** + * @brief DCL Set I2C timing loop2 number. + * @param i2cx I2C register base address. + * @param loopValue Number of loop + * @retval None. + */ +static inline void DCL_I2C_SetLoop2(I2C_RegStruct *i2cx, unsigned int loopValue) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_LOOP2.BIT.loop_num2 = loopValue; +} + +/** + * @brief DCL Get I2C timing loop2 number. + * @param i2cx I2C register base address. + * @retval Number of loop. + */ +static inline unsigned int DCL_I2C_GetLoop2(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_LOOP2.BIT.loop_num2; +} + +/** + * @brief DCL Set I2C timing loop3 number. + * @param i2cx I2C register base address. + * @param loopValue Number of loop + * @retval None. + */ +static inline void DCL_I2C_SetLoop3(I2C_RegStruct *i2cx, unsigned int loopValue) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_LOOP3.BIT.loop_num3 = loopValue; +} + +/** + * @brief DCL Get I2C timing loop3 number. + * @param i2cx I2C register base address. + * @retval Number of loop. + */ +static inline unsigned int DCL_I2C_GetLoop3(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_LOOP3.BIT.loop_num3; +} + +/** + * @brief Configuring the Command for Jumping to a Specified Timing. + * @param i2cx I2C register base address. + * @param dstTimingCmd Jump timing command position + * @retval None. + */ +static inline void DCL_I2C_SetDst1(I2C_RegStruct *i2cx, unsigned char dstTimingCmd) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_DST1.BIT.dst_timing_cmd1 = dstTimingCmd; +} + +/** + * @brief Get the Command for Jumping to a Specified Timing. + * @param i2cx I2C register base address. + * @retval Jump timing command position. + */ +static inline unsigned int DCL_I2C_GetDst1(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_DST1.BIT.dst_timing_cmd1; +} + +/** + * @brief Configuring the Command for Jumping to a Specified Timing. + * @param i2cx I2C register base address. + * @param dstTimingCmd Jump timing command position + * @retval None. + */ +static inline void DCL_I2C_SetDst2(I2C_RegStruct *i2cx, unsigned char dstTimingCmd) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_DST2.BIT.dst_timing_cmd2 = dstTimingCmd; +} + +/** + * @brief Get the Command for Jumping to a Specified Timing. + * @param i2cx I2C register base address. + * @retval Jump timing command position. + */ +static inline unsigned int DCL_I2C_GetDst2(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_DST2.BIT.dst_timing_cmd2; +} + +/** + * @brief Configuring the Command for Jumping to a Specified Timing. + * @param i2cx I2C register base address. + * @param dstTimingCmd Jump timing command position + * @retval None. + */ +static inline void DCL_I2C_SetDst3(I2C_RegStruct *i2cx, unsigned char dstTimingCmd) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_DST3.BIT.dst_timing_cmd3 = dstTimingCmd; +} + +/** + * @brief Get the Command for Jumping to a Specified Timing. + * @param i2cx I2C register base address. + * @retval Jump timing command position. + */ +static inline unsigned int DCL_I2C_GetDst3(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_DST3.BIT.dst_timing_cmd3; +} + +/** + * @brief Set the I2C TX threshold. + * @param i2cx I2C register base address. + * @param waterMark I2C Tx threshold, 0-63. + * @retval None. + */ +static inline void DCL_I2C_SetTxWaterMark(I2C_RegStruct *i2cx, unsigned char waterMark) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_TX_WATERMARK.BIT.tx_watermark = waterMark; +} + +/** + * @brief Get the I2C TX threshold. + * @param i2cx I2C register base address. + * @retval I2C tx threshold. + */ +static inline unsigned int DCL_I2C_GetTxWaterMark(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_TX_WATERMARK.BIT.tx_watermark; +} + +/** + * @brief Set the I2C RX threshold. + * @param i2cx I2C register base address. + * @param waterMark I2C Rx threshold, 0-63. + * @retval None. + */ +static inline void DCL_I2C_SetRxWaterMark(I2C_RegStruct *i2cx, unsigned char waterMark) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_RX_WATERMARK.BIT.rx_watermark = waterMark; +} + +/** + * @brief Get the I2C RX threshold. + * @param i2cx I2C register base address. + * @param waterMark I2C Rx threshold, 0-63. + * @retval I2C rx threshold. + */ +static inline int DCL_I2C_GetRxWaterMark(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_RX_WATERMARK.BIT.rx_watermark; +} + +/** + * @brief Set the I2C DMA mode. + * @param i2cx I2C register base address. + * @param mode I2C DMA operation mode. + * @retval None. + */ +static inline void DCL_I2C_SetDmaMode(I2C_RegStruct *i2cx, unsigned char mode) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_CTRL1.BIT.dma_operation = mode; +} + +/** + * @brief Start and stop I2C timing execution. + * @param i2cx I2C register base address. + * @param startStop start : 1, stop :0. + * @retval None. + */ +static inline void DCL_I2C_SetStart(I2C_RegStruct *i2cx, unsigned char startStop) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_CTRL1.BIT.start = startStop; +} + +/** + * @brief Get start and stop I2C timing status. + * @param i2cx I2C register base address. + * @retval 0 or 1. + */ +static inline unsigned int DCL_I2C_GetStart(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_CTRL1.BIT.start; +} + +/** + * @brief Set the low level of the SDA pin. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_SetFroceSdaOenLowLevel(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_CTRL2.BIT.force_sda_oen = BASE_CFG_UNSET; +} + +/** + * @brief Set the high level of the SDA pin. + * @param i2cx I2C register base address. + * @retval None. + */ +static inline void DCL_I2C_SetFroceSdaOenHighLevel(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_CTRL2.BIT.force_sda_oen = BASE_CFG_SET; +} + +/** + * @brief Get the level of the SDA pin. + * @param i2cx I2C register base address. + * @retval 0 or 1 + */ +static inline unsigned int DCL_I2C_GetFroceSdaOen(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_CTRL2.BIT.force_sda_oen; +} + +/** + * @brief Set the SCL and SDA pins of the I2C to GPIO mode. + * @param i2cx I2C register base address. + * @param mode 0 disable,1 enable. + * @retval None. + */ +static inline void DCL_I2C_SetGpioMode(I2C_RegStruct *i2cx, unsigned char mode) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_CTRL2.BIT.gpio_mode = mode; +} + +/** + * @brief Get the SCL and SDA pins of the I2C to GPIO mode. + * @param i2cx I2C register base address. + * @retval 0 or 1 + */ +static inline unsigned int DCL_I2C_GetGpioMode(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_CTRL2.BIT.gpio_mode; +} + +/** + * @brief Get the level of the external I2C bus SDA. + * @param i2cx I2C register base address. + * @retval 0 or 1 + */ +static inline unsigned int DCL_I2C_GetSdaIn(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_CTRL2.BIT.i2c_sda_in; +} + +/** + * @brief Get the SDA output level. + * @param i2cx I2C register base address. + * @retval 0 or 1. + */ +static inline unsigned int DCL_I2C_GetSdaOen(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_CTRL2.BIT.i2c_sda_oen; +} + +/** + * @brief Get the SCL output level. + * @param i2cx I2C register base address. + * @retval 0 or 1. + */ +static inline unsigned int DCL_I2C_GetSclOen(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_CTRL2.BIT.i2c_scl_oen; +} + +/** + * @brief Enable SDA output level of the internal I2C. + * @param i2cx I2C register base address. + * @retval null. + */ +static inline void DCL_I2C_SclOenEnable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_CTRL2.BIT.i2c_scl_oen = BASE_CFG_ENABLE; +} + +/** + * @brief Disable SDA output level of the internal I2C. + * @param i2cx I2C register base address. + * @retval null. + */ +static inline void DCL_I2C_SclOenDisable(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_CTRL2.BIT.i2c_scl_oen = BASE_CFG_DISABLE; +} + +/** + * @brief Check whether the TX FIFO is not full. + * @param i2cx I2C register base address. + * @retval true or false. + */ +static inline bool DCL_I2C_CheckTxFifoNotFull(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_FIFO_STAT.BIT.rx_fifo_not_full; +} + +/** + * @brief Check whether the TX FIFO is not empty. + * @param i2cx I2C register base address. + * @retval true or false. + */ +static inline bool DCL_I2C_CheckTxFifoNotEmpty(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_FIFO_STAT.BIT.rx_fifo_not_empty; +} + +/** + * @brief Check whether the RX FIFO is not full. + * @param i2cx I2C register base address. + * @retval true or false. + */ +static inline bool DCL_I2C_CheckRxFifoNotFull(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_FIFO_STAT.BIT.tx_fifo_not_full; +} + +/** + * @brief Check whether the RX FIFO is not empty. + * @param i2cx I2C register base address. + * @retval true or false. + */ +static inline bool DCL_I2C_CheckRxFifoNotEmpty(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_FIFO_STAT.BIT.tx_fifo_not_empty; +} + +/** + * @brief Clear Interrupt. + * @param i2cx I2C register base address. + * @param intrRaw Corresponding interrupt bit, for example, 110011. + * @retval None. + */ +static inline void DCL_I2C_ClearIrq(I2C_RegStruct *i2cx, unsigned int intrRaw) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_INTR_RAW.reg = intrRaw; +} + +/** + * @brief Obtaining the Interrupt Raw Configuration. + * @param i2cx I2C register base address. + * @retval Interrupt raw status value. + */ +static inline unsigned int DCL_I2C_GetInterruptRaw(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_INTR_RAW.reg; +} + +/** + * @brief Configuring Interrupt Enable. + * @param i2cx I2C register base address. + * @param intrEn Corresponding interrupt enable bit, for example, 110011. + * @retval None. + */ +static inline void DCL_I2C_SetInterruptEn(I2C_RegStruct *i2cx, unsigned int intrEn) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + i2cx->I2C_INTR_EN.reg = intrEn; +} + +/** + * @brief Obtaining the Interrupt Enable Configuration. + * @param i2cx I2C register base address. + * @retval Interrupt enable value. + */ +static inline unsigned int DCL_I2C_GetInterruptEn(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_INTR_EN.reg; +} + +/** + * @brief Obtains the interrupt status. + * @param i2cx I2C register base address. + * @retval Interrupt Status. + */ +static inline unsigned int DCL_I2C_GetInterruptStatus(I2C_RegStruct *i2cx) +{ + I2C_ASSERT_PARAM(IsI2CInstance(i2cx)); + return i2cx->I2C_INTR_STAT.reg; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* #ifndef McuMagicTag_I2C_IP_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/i2c/src/i2c.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/i2c/src/i2c.c new file mode 100644 index 00000000..4c94b743 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/i2c/src/i2c.c @@ -0,0 +1,1151 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file i2c.c + * @author MCU Driver Team + * @brief I2C module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the I2C. + * + Initialization and de-initialization functions + * + Peripheral Control functions + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "i2c.h" + +/* Macro definitions ---------------------------------------------------------*/ +#define I2C_MAX_FIFO_SIZE 64 +#define I2C_WAIT_TIMEOUT 0x400 +#define I2C_MAX_DEV_ADDR 0x3FF + +#define I2C_CFG_INTERRUPT_RX 0x1805 /* Enable all_cmd_done\arb_lost\rx_gt_watermark\ack_bit_unmatch */ +#define I2C_CFG_INTERRUPT_TX 0x1811 /* Enable all_cmd_done\arb_lost\tx_lt_watermark\ack_bit_unmatch */ + +#define I2C_TICK_MS_DIV 1000 + +#define I2C_INTR_RAW_ALL_CMD_DONE_MASK (0x1 << 12) +#define I2C_INTR_RAW_ARB_LOST_MASK (0x1 << 11) +#define I2C_INTR_RAW_ACK_BIT_UNMATCH_MASK (0x1 << 0) + +/** + * @brief Check all initial configuration parameters. + * @param handle I2C handle. + * @retval None. + */ +static void CheckAllInitParameters(I2C_Handle *handle) +{ +#ifndef I2C_PARAM_CHECK + BASE_FUNC_UNUSED(handle); /* If macro verification is not enabled, avoid alarms. */ +#endif + I2C_ASSERT_PARAM(IsI2cAddressMode(handle->addrMode)); + I2C_ASSERT_PARAM(IsI2cSdaHoldTime(handle->sdaHoldTime)); + I2C_ASSERT_PARAM(IsI2cFreq(handle->freq)); + I2C_ASSERT_PARAM(IsI2cIgnoreAckFlag(handle->ignoreAckFlag)); + I2C_ASSERT_PARAM(IsI2cTxWaterMark(handle->txWaterMark)); + I2C_ASSERT_PARAM(IsI2cRxWaterMark(handle->rxWaterMark)); +} + +/** + * @brief I2C crash rescue. + * @param handle i2c handle. + * @retval None. + */ +static void I2cRescue(I2C_Handle *handle) +{ + unsigned int timeCnt; + unsigned int index; + + handle->baseAddress->I2C_GLB.BIT.i2c_enable = BASE_CFG_UNSET; + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + + /* Set the SCL and SDA pins of the I2C to GPIO mode. SCL = 1, SDA = 1 */ + handle->baseAddress->I2C_CTRL2.reg = 0x111; /* Set SCL = 1, SDA = 1, gpio mode enable. 0x111 = 0b10010001 */ + + timeCnt = 0; + do { + /* The device that controls the bus to be pulled down needs to release the bus within the 9 clocks. */ + for (index = 0; index < 9; index++) { + handle->baseAddress->I2C_CTRL2.BIT.i2c_scl_oen = BASE_CFG_UNSET; + BASE_FUNC_DELAY_US(5); /* The I2C timing is required. The delay is about 5 μs. */ + handle->baseAddress->I2C_CTRL2.BIT.i2c_scl_oen = BASE_CFG_SET; + BASE_FUNC_DELAY_US(5); /* The I2C timing is required. The delay is about 5 μs. */ + } + + timeCnt++; + if (timeCnt > I2C_WAIT_TIMEOUT) { + handle->baseAddress->I2C_CTRL2.reg = 0x11; /* Set SCL = 1, SDA = 1, gpio mode disable. 0x11 = 0b00010001 */ + return; + } + } while (!handle->baseAddress->I2C_CTRL2.BIT.i2c_sda_in); + handle->baseAddress->I2C_CTRL2.reg = 0x111; /* Set SCL = 1, SDA = 1, gpio mode enable. 0x111 = 0b10010001 */ + /* I2C start */ + handle->baseAddress->I2C_CTRL2.BIT.force_sda_oen = BASE_CFG_UNSET; + BASE_FUNC_DELAY_US(10); /* The I2C timing is required. The delay is about 10 μs. */ + /* I2C stop */ + handle->baseAddress->I2C_CTRL2.BIT.force_sda_oen = BASE_CFG_SET; + /* Exit the I2C SCL and SDA pins to GPIO mode. */ + handle->baseAddress->I2C_CTRL2.reg = 0x11; /* Set SCL = 1, SDA = 1, gpio mode disable. 0x11 = 0b00010001 */ +} + +/** + * @brief Setting a Single Timing Command. + * @param handle I2C handle. + * @param i2cCmd Timing Command. + * @param offset Timing offset position. + * @retval None. + */ +static void SetSingleTimingCmd(I2C_Handle *handle, I2C_CmdType i2cCmd, int *offset) +{ + handle->baseAddress->I2C_TIMING_CMD.BIT[*offset].timing_cmd = i2cCmd; + (*offset)++; +} + +/** + * @brief Setting slavel address. + * @param handle I2C handle. + * @param offset Timing offset position. + * @retval Current offset. + */ +static int SetSlaveAddress(I2C_Handle *handle, int offset) +{ + int currentOffset = offset; + + /* Write slave address */ + if (handle->addrMode == I2C_10_BITS) { /* 10bit address Configuration */ + if (handle->transferCount == 0) { + SetSingleTimingCmd(handle, I2C_CMD_WDA2, ¤tOffset); + if (handle->ignoreAckFlag == I2C_IGNORE_NAK_ENABLE) { + SetSingleTimingCmd(handle, I2C_CMD_RNC, ¤tOffset); /* I2C Ignore Reply Configuration */ + } else { + SetSingleTimingCmd(handle, I2C_CMD_RACK, ¤tOffset); + } + SetSingleTimingCmd(handle, I2C_CMD_WDA1, ¤tOffset); + } else { + SetSingleTimingCmd(handle, I2C_CMD_WDA2, ¤tOffset); + } + } else { + SetSingleTimingCmd(handle, I2C_CMD_WDA1, ¤tOffset); /* 7bit address Configuration */ + } + return currentOffset; +} + +/** + * @brief Set the Write Address Cmd object + * @param handle I2C handle. + * @retval Current instruction offset + */ +static int SetWriteAddressCmd(I2C_Handle *handle) +{ + int offset = 0; + + if (handle->transferCount == 0) { /* If no data is sent, send the start command first. */ + SetSingleTimingCmd(handle, I2C_CMD_S, &offset); + } else { + SetSingleTimingCmd(handle, I2C_CMD_SR, &offset); + } + /* Write slave address */ + offset = SetSlaveAddress(handle, offset); + if (handle->ignoreAckFlag == I2C_IGNORE_NAK_ENABLE) { + SetSingleTimingCmd(handle, I2C_CMD_RNC, &offset); + } else { + SetSingleTimingCmd(handle, I2C_CMD_RACK, &offset); + } + return offset; +} + +/** + * @brief Configuring the I2C Write Timing. + * @param handle I2C handle. + * @retval None. + */ +static void ConfigStandardWriteCmd(I2C_Handle *handle) +{ + int offset; + + offset = SetWriteAddressCmd(handle); + /* Set the specifies the jump command. */ + handle->baseAddress->I2C_DST1.BIT.dst_timing_cmd1 = offset; + SetSingleTimingCmd(handle, I2C_CMD_UDB1, &offset); + SetSingleTimingCmd(handle, I2C_CMD_WDB1, &offset); + /* If ignore ack is required, set the RNC command. */ + if (handle->ignoreAckFlag == I2C_IGNORE_NAK_ENABLE) { + SetSingleTimingCmd(handle, I2C_CMD_RNC, &offset); + } else { + SetSingleTimingCmd(handle, I2C_CMD_RACK, &offset); + } + SetSingleTimingCmd(handle, I2C_CMD_JMPN1, &offset); + /* If the data transfer is complete, set the STOP command. */ + SetSingleTimingCmd(handle, I2C_CMD_P, &offset); + SetSingleTimingCmd(handle, I2C_CMD_EXIT, &offset); +} + +/** + * @brief Configuring the I2C Read Timing. + * @param handle I2C handle. + * @retval None. + */ +static void ConfigStandardReadCmd(I2C_Handle *handle) +{ + int offset; + + offset = SetWriteAddressCmd(handle); + if (handle->transferSize > 1) { + /* Set the specifies the jump command. */ + handle->baseAddress->I2C_DST1.BIT.dst_timing_cmd1 = offset; + SetSingleTimingCmd(handle, I2C_CMD_RD, &offset); + SetSingleTimingCmd(handle, I2C_CMD_SACK, &offset); + SetSingleTimingCmd(handle, I2C_CMD_JMPN1, &offset); + } + + SetSingleTimingCmd(handle, I2C_CMD_RD, &offset); + SetSingleTimingCmd(handle, I2C_CMD_SNACK, &offset); + /* If the data transfer is complete, set the STOP command. */ + SetSingleTimingCmd(handle, I2C_CMD_P, &offset); + SetSingleTimingCmd(handle, I2C_CMD_EXIT, &offset); +} + +/** + * @brief Configuring the I2C Slave Device Address. + * @param handle I2C handle. + * @param devAddr Address of the communication device. + * @retval None. + */ +static void SetDevAddr(I2C_Handle *handle, const unsigned short devAddr) +{ + unsigned short addr; + if (handle->addrMode == I2C_10_BITS) { + handle->baseAddress->I2C_DEV_ADDR.reg = devAddr; + } else { + addr = devAddr & 0xFF; /* The 8th digit is used */ + handle->baseAddress->I2C_DEV_ADDR.BIT.dev_addr_byte1 = addr; + } +} + +/** + * @brief Waiting for RX not empty. + * @param handle I2C handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType WaitRxNotEmpty(I2C_Handle *handle) +{ + unsigned int preTick = DCL_SYSTICK_GetTick(); + unsigned int curTick; + unsigned long long delta = 0; + unsigned long long targetDelta = SYSTICK_GetCRGHZ() / I2C_TICK_MS_DIV * handle->timeout; + + while (1) { /* Start timing. */ + curTick = DCL_SYSTICK_GetTick(); + delta += curTick > preTick ? curTick - preTick : SYSTICK_MAX_VALUE - preTick + curTick; + if (handle->baseAddress->I2C_FIFO_STAT.BIT.rx_fifo_not_empty) { + return BASE_STATUS_OK; + } + /* Check whether the timeout occurs. */ + if (delta >= targetDelta) { + break; + } + preTick = curTick; + }; + + I2cRescue(handle); /* Perform related cleanup operations. */ + + return BASE_STATUS_TIMEOUT; +} + +/** + * @brief Waiting for TX not full. + * @param handle I2C handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType WaitTxNotFull(I2C_Handle *handle) +{ + unsigned int preTick = DCL_SYSTICK_GetTick(); + unsigned int curTick; + unsigned long long delta = 0; + unsigned long long targetDelta = SYSTICK_GetCRGHZ() / I2C_TICK_MS_DIV * handle->timeout; + + while (1) { /* Start timing. */ + curTick = DCL_SYSTICK_GetTick(); + delta += curTick > preTick ? curTick - preTick : SYSTICK_MAX_VALUE - preTick + curTick; + if (handle->baseAddress->I2C_FIFO_STAT.BIT.tx_fifo_not_full) { /* Check the tx fifo isn't full. */ + return BASE_STATUS_OK; + } else if (handle->baseAddress->I2C_CTRL1.BIT.start != BASE_CFG_SET) { + handle->baseAddress->I2C_CTRL1.BIT.start = BASE_CFG_SET; + } + preTick = curTick; + /* Check whether the timeout occurs. */ + if (delta >= targetDelta) { + break; + } + }; + + I2cRescue(handle); + + return BASE_STATUS_TIMEOUT; +} + +/** + * @brief Waiting for idle. + * @param handle I2C handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +static BASE_StatusType WaitIdle(I2C_Handle *handle) +{ + unsigned int preTick = DCL_SYSTICK_GetTick(); + unsigned int curTick; + unsigned long long delta = 0; + unsigned long long targetDelta = SYSTICK_GetCRGHZ() / I2C_TICK_MS_DIV * handle->timeout; + do { + curTick = DCL_SYSTICK_GetTick(); + delta += curTick > preTick ? curTick - preTick : SYSTICK_MAX_VALUE - preTick + curTick; + /* If any errors occurs, return error status. */ + if (handle->baseAddress->I2C_INTR_RAW.BIT.arb_lost_raw || + handle->baseAddress->I2C_INTR_RAW.BIT.ack_bit_unmatch_raw) { + return BASE_STATUS_ERROR; + } + /* If all command has done, return ok status. */ + if (handle->baseAddress->I2C_INTR_RAW.BIT.all_cmd_done_raw) { + return BASE_STATUS_OK; + } + /* Check whether the timeout occurs. */ + if (delta >= targetDelta) { + break; + } + preTick = curTick; + } while (true); + + I2cRescue(handle); + + return BASE_STATUS_TIMEOUT; +} + +/** + * @brief Check Sending Complete. + * @param handle I2C handle. + * @retval None. + */ +static void WaitSendComplete(I2C_Handle *handle) +{ + if (handle->baseAddress->I2C_GLB.BIT.i2c_enable) { + WaitIdle(handle); + handle->baseAddress->I2C_GLB.BIT.i2c_enable = BASE_CFG_UNSET; + } +} + +/** + * @brief Setting Error Handling. + * @param handle I2C handle. + * @retval None. + */ +static void SetErrorHandling(I2C_Handle *handle) +{ + handle->state = I2C_STATE_READY; + /* Disable */ + handle->baseAddress->I2C_GLB.BIT.i2c_enable = BASE_CFG_UNSET; + /* Clears interrupts and disables interrupt reporting to facilitate switching between different working modes. */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + if (handle->errorCode != BASE_STATUS_OK && handle->userCallBack.ErrorCallback != NULL) { + handle->userCallBack.ErrorCallback(handle); + } +} + +/** + * @brief Checking Interrupts Caused by I2C Timing Errors. + * @param handle I2C handle. + * @retval true or false + */ +static bool CheckInterruptErrorStatus(I2C_Handle *handle) +{ + if (handle->baseAddress->I2C_INTR_STAT.BIT.arb_lost || + handle->baseAddress->I2C_INTR_STAT.BIT.ack_bit_unmatch) { + handle->errorCode = BASE_STATUS_ERROR; + /* Disable */ + handle->baseAddress->I2C_GLB.BIT.i2c_enable = BASE_CFG_UNSET; + /* Clears interrupts and disables interrupt reporting to + facilitate switching between different working modes. */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + handle->state = I2C_STATE_READY; + if (handle->userCallBack.ErrorCallback != NULL) { + handle->userCallBack.ErrorCallback(handle); + } + return true; + } + return false; +} + +/** + * @brief I2C Interrupt TX Handling + * @param handle I2C handle. + * @retval None. + */ +static void InterruptTxHandle(I2C_Handle *handle) +{ + /* Cyclically move the data from the transfer buff to tx fifo. */ + while (handle->baseAddress->I2C_FIFO_STAT.BIT.tx_fifo_not_full && + handle->transferCount < handle->transferSize) { + handle->baseAddress->I2C_TX_FIFO.BIT.tx_fifo = *handle->transferBuff++; + handle->transferCount++; + } +} + +/** + * @brief I2C Interrupt RX Handling + * @param handle I2C handle. + * @retval None. + */ +static void InterruptRxHandle(I2C_Handle *handle) +{ + /* Cyclically get the data from the rx fifo. */ + while (handle->baseAddress->I2C_FIFO_STAT.BIT.rx_fifo_not_empty && + handle->transferCount < handle->transferSize) { + *handle->transferBuff++ = handle->baseAddress->I2C_RX_FIFO.BIT.rx_fifo; + handle->transferCount++; + } +} + +/** + * @brief I2C Interrupt done Handling + * @param handle I2C handle. + * @retval None. + */ +static void InterruptAllDoneHandle(I2C_Handle *handle) +{ + /* Disable */ + handle->baseAddress->I2C_GLB.BIT.i2c_enable = BASE_CFG_UNSET; + /* Clears interrupts and disables interrupt reporting to + facilitate switching between different working modes. */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + /* Called the user's callback based on the I2C status. */ + if (handle->userCallBack.RxCplCallback != NULL && handle->state == I2C_STATE_BUSY_MASTER_RX) { + handle->userCallBack.RxCplCallback(handle); + } else if (handle->userCallBack.TxCplCallback != NULL && handle->state == I2C_STATE_BUSY_MASTER_TX) { + handle->userCallBack.TxCplCallback(handle); + } + handle->state = I2C_STATE_READY; +} + +/** + * @brief Initializing the I2C Module. + * @param handle I2C handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_Init(I2C_Handle *handle) +{ + unsigned int freq; + unsigned int clockFreq; + unsigned int val; + unsigned int glbReg; + unsigned int temp; + + I2C_ASSERT_PARAM(handle != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + CheckAllInitParameters(handle); /* Check all config parameters. */ + + freq = handle->freq; + clockFreq = HAL_CRG_GetIpFreq((void *)handle->baseAddress); + if (freq > clockFreq) { + return BASE_STATUS_ERROR; + } + I2C_PARAM_CHECK_WITH_RET(freq, BASE_STATUS_ERROR); + + handle->state = I2C_STATE_BUSY; + /* Disable */ + handle->baseAddress->I2C_GLB.BIT.i2c_enable = BASE_CFG_UNSET; + /* Clears interrupts and disables interrupt reporting to facilitate switching between different working modes. */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + /* Set SCL high and low duratiom time */ + if (freq <= I2C_STANDARD_FREQ_TH) { + val = clockFreq / (freq * 2); /* The clockFreq / (freq * 2) = cloclFreq/0.5/freq */ + handle->baseAddress->I2C_HCNT.BIT.i2c_high_duration = val; + handle->baseAddress->I2C_LCNT.BIT.i2c_low_duration = val; + } else { + val = ((clockFreq / 100) * 36) / freq; /* The ((clockFreq / 100) * 36) / freq = cloclFreq/0.36/freq */ + handle->baseAddress->I2C_HCNT.BIT.i2c_high_duration = val; + val = ((clockFreq / 100) * 64) / freq; /* The ((clockFreq / 100) * 64) / freq = clockFreq/0.64/freq */ + handle->baseAddress->I2C_LCNT.BIT.i2c_low_duration = val; + } + /* Set sda hold duration.The value is fixed to 0xa */ + temp = ((unsigned int)I2C_SDA_HOLD_DURATION) << I2C_SDA_HOLD_DURATION_POS; + glbReg = (handle->baseAddress->I2C_GLB.reg & (~I2C_SDA_HOLD_DURATION_MASK)) | temp; + handle->baseAddress->I2C_GLB.reg = glbReg; + + /* Set I2C TX FIFO watermark */ + handle->baseAddress->I2C_TX_WATERMARK.BIT.tx_watermark = handle->txWaterMark; + /* Set I2C RX FIFO watermark */ + handle->baseAddress->I2C_RX_WATERMARK.BIT.rx_watermark = handle->rxWaterMark; + handle->state = I2C_STATE_READY; + + return BASE_STATUS_OK; +} + +/** + * @brief Deinitialize the I2C module. + * @param handle I2C handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_Deinit(I2C_Handle *handle) +{ + I2C_ASSERT_PARAM(handle != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + + handle->state = I2C_STATE_BUSY; + + /* Clears interrupts and disables interrupt reporting to facilitate switching between different working modes. */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + /* Clean interrupt callback functions. */ + handle->userCallBack.TxCplCallback = NULL; + handle->userCallBack.RxCplCallback = NULL; + handle->userCallBack.ErrorCallback = NULL; + handle->state = I2C_STATE_RESET; + + return BASE_STATUS_OK; +} + +/** + * @brief Receiving data in blocking mode as master. + * @param handle I2C handle. + * @param devAddr Slave Device Address. + * @param rData Address of the data buff to be receiving. + * @param dataSize Number of the data to be receiving. + * @param timeout Timeout period,unit: ms. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_MasterReadBlocking(I2C_Handle *handle, + unsigned short devAddr, + unsigned char *rData, + unsigned int dataSize, + unsigned int timeout) +{ + BASE_StatusType ret; + + I2C_ASSERT_PARAM(handle != NULL && rData != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_PARAM_CHECK_WITH_RET(devAddr <= I2C_MAX_DEV_ADDR, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + + /* Configuring the I2C state and transmission parameters. */ + handle->state = I2C_STATE_BUSY_MASTER_RX; + handle->transferBuff = rData; + handle->transferSize = dataSize; + handle->transferCount = 0; + handle->timeout = timeout; + + /* Wait I2C bus is idle. */ + WaitSendComplete(handle); + + /* Enable */ + handle->baseAddress->I2C_GLB.BIT.i2c_enable = BASE_CFG_SET; + SetDevAddr(handle, devAddr); + /* Configuring the I2C Timing */ + ConfigStandardReadCmd(handle); + /* The number of configuration cycles is used only when the read data is greater than 2. */ + if (handle->transferSize >= 2) { + handle->baseAddress->I2C_LOOP1.BIT.loop_num1 = handle->transferSize - 2; /* Subtract 2 bytes from the header. */ + } else { + handle->baseAddress->I2C_LOOP1.BIT.loop_num1 = 0; + } + + /* Startup Control */ + handle->baseAddress->I2C_CTRL1.BIT.dma_operation = I2C_DMA_OP_NONE; + handle->baseAddress->I2C_CTRL1.BIT.start = BASE_CFG_SET; + /* Cyclically get the data from the rx fifo. */ + while (handle->transferCount < handle->transferSize) { + ret = WaitRxNotEmpty(handle); + if (ret != BASE_STATUS_OK) { + SetErrorHandling(handle); + return ret; + } + *handle->transferBuff = handle->baseAddress->I2C_RX_FIFO.BIT.rx_fifo; + handle->transferBuff++; + handle->transferCount++; + } + + ret = WaitIdle(handle); /* Waiting for all data transfer to complete. */ + handle->errorCode = ret; + if (handle->userCallBack.RxCplCallback != NULL && ret == BASE_STATUS_OK) { + handle->userCallBack.RxCplCallback(handle); + } + SetErrorHandling(handle); + return ret; +} + +/** + * @brief Send data in blocking mode as master. + * @param handle I2C handle. + * @param devAddr Slave Device Address. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be sent. + * @param timeout Timeout period,unit: ms. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_MasterWriteBlocking(I2C_Handle *handle, + unsigned short devAddr, + unsigned char *wData, + unsigned int dataSize, + unsigned int timeout) +{ + BASE_StatusType ret; + + I2C_ASSERT_PARAM(handle != NULL && wData != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_PARAM_CHECK_WITH_RET(devAddr <= I2C_MAX_DEV_ADDR, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + + /* Configuring the I2C state and transmission parameters. */ + handle->state = I2C_STATE_BUSY_MASTER_TX; + handle->transferBuff = wData; + handle->transferSize = dataSize; + handle->transferCount = 0; + handle->timeout = timeout; + + /* Wait I2C bus is idle. */ + WaitSendComplete(handle); + + /* Enable */ + handle->baseAddress->I2C_GLB.BIT.i2c_enable = BASE_CFG_SET; + SetDevAddr(handle, devAddr); + /* Configuring the I2C Timing */ + ConfigStandardWriteCmd(handle); + handle->baseAddress->I2C_LOOP1.BIT.loop_num1 = handle->transferSize - 1; + /* Startup Control */ + handle->baseAddress->I2C_CTRL1.BIT.dma_operation = I2C_DMA_OP_NONE; + /* Cyclically move the data from the transfer buff to tx fifo. */ + while (handle->transferCount < handle->transferSize) { + ret = WaitTxNotFull(handle); + if (ret != BASE_STATUS_OK) { + SetErrorHandling(handle); + return ret; + } + handle->baseAddress->I2C_TX_FIFO.BIT.tx_fifo = *handle->transferBuff; + handle->transferBuff++; + handle->transferCount++; + } + /* If the size of the transferred data less than tx fifo size, set I2C start. */ + if (handle->baseAddress->I2C_CTRL1.BIT.start != BASE_CFG_SET && + handle->baseAddress->I2C_FIFO_STAT.BIT.tx_fifo_not_empty) { + handle->baseAddress->I2C_CTRL1.BIT.start = BASE_CFG_SET; + } + ret = WaitIdle(handle); /* Waiting for all data transfer to complete. */ + handle->errorCode = ret; + if (handle->userCallBack.TxCplCallback != NULL && ret == BASE_STATUS_OK) { + handle->userCallBack.TxCplCallback(handle); + } + SetErrorHandling(handle); + return ret; +} + +/** + * @brief Receiving data in blocking mode as slave. + * @param handle I2C handle. + * @param rData Address of the data buff to be receiving. + * @param dataSize Number of the data to be receiving. + * @param timeout Timeout period,unit: ms. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SlaveReadBlocking(I2C_Handle *handle, + unsigned char *rData, + unsigned int dataSize, + unsigned int timeout) +{ + BASE_FUNC_UNUSED(handle); + BASE_FUNC_UNUSED(rData); + BASE_FUNC_UNUSED(dataSize); + BASE_FUNC_UNUSED(timeout); + /* The slave mode is not supported. */ + return BASE_STATUS_NOT_SUPPORT; +} + +/** + * @brief Send data in blocking mode as slave. + * @param handle I2C handle. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be sent. + * @param timeout Timeout period,unit: ms. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SlaveWriteBlocking(I2C_Handle *handle, + unsigned char *wData, + unsigned int dataSize, + unsigned int timeout) +{ + BASE_FUNC_UNUSED(handle); + BASE_FUNC_UNUSED(wData); + BASE_FUNC_UNUSED(dataSize); + BASE_FUNC_UNUSED(timeout); + /* The slave mode is not supported. */ + return BASE_STATUS_NOT_SUPPORT; +} + +/** + * @brief Receiving data in interrupts mode as master. + * @param handle I2C handle. + * @param devAddr Slave Device Address. + * @param rData Address of the data buff to be receiving. + * @param dataSize Number of the data to be receiving. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_MasterReadIT(I2C_Handle *handle, unsigned short devAddr, + unsigned char *rData, unsigned int dataSize) +{ + I2C_ASSERT_PARAM(handle != NULL && rData != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_PARAM_CHECK_WITH_RET(devAddr <= I2C_MAX_DEV_ADDR, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + + /* Configuring the I2C state and transmission parameters. */ + handle->state = I2C_STATE_BUSY_MASTER_RX; + handle->transferCount = 0; + handle->transferBuff = rData; + handle->transferSize = dataSize; + + /* Wait I2C bus is idle. */ + WaitSendComplete(handle); + + /* Enable */ + handle->baseAddress->I2C_GLB.BIT.i2c_enable = BASE_CFG_SET; + /* Clean interrupt */ + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + + /* Enable interrupt */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_CFG_INTERRUPT_RX; + + SetDevAddr(handle, devAddr); + /* Configuring the I2C Timing */ + ConfigStandardReadCmd(handle); + /* The number of configuration cycles is used only when the read data is greater than 2. */ + if (handle->transferSize >= 2) { + handle->baseAddress->I2C_LOOP1.BIT.loop_num1 = handle->transferSize - 2; /* Subtract 2 bytes from the header. */ + } else { + handle->baseAddress->I2C_LOOP1.BIT.loop_num1 = 0; + } + /* Startup Control */ + handle->baseAddress->I2C_CTRL1.BIT.dma_operation = I2C_DMA_OP_NONE; + handle->baseAddress->I2C_CTRL1.BIT.start = BASE_CFG_SET; + + return BASE_STATUS_OK; +} + +/** + * @brief Send data in interrupts mode as master. + * @param handle I2C handle. + * @param devAddr Slave Device Address. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_MasterWriteIT(I2C_Handle *handle, unsigned short devAddr, + unsigned char *wData, unsigned int dataSize) +{ + I2C_ASSERT_PARAM(handle != NULL && wData != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_PARAM_CHECK_WITH_RET(devAddr <= I2C_MAX_DEV_ADDR, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + + /* Configuring the I2C state and transmission parameters. */ + handle->state = I2C_STATE_BUSY_MASTER_TX; + handle->transferBuff = wData; + handle->transferSize = dataSize; + handle->transferCount = 0; + + /* Wait I2C bus is idle. */ + WaitSendComplete(handle); + + /* Enable */ + handle->baseAddress->I2C_GLB.BIT.i2c_enable = BASE_CFG_SET; + /* Clean interrupt */ + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + /* Enable interrupt */ + handle->baseAddress->I2C_INTR_EN.reg = I2C_CFG_INTERRUPT_TX; + + SetDevAddr(handle, devAddr); + /* Configuring the I2C Timing */ + ConfigStandardWriteCmd(handle); + handle->baseAddress->I2C_LOOP1.BIT.loop_num1 = handle->transferSize - 1; + /* Clean interrupt */ + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + + /* Startup Control */ + handle->baseAddress->I2C_CTRL1.BIT.dma_operation = I2C_DMA_OP_NONE; + handle->baseAddress->I2C_CTRL1.BIT.start = BASE_CFG_SET; + return BASE_STATUS_OK; +} + +/** + * @brief Receiving data in interrupts mode as slave. + * @param handle I2C handle. + * @param rData Address of the data buff to be receiving. + * @param dataSize Number of the data to be receiving. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SlaveReadIT(I2C_Handle *handle, unsigned char *rData, unsigned int dataSize) +{ + BASE_FUNC_UNUSED(handle); + BASE_FUNC_UNUSED(rData); + BASE_FUNC_UNUSED(dataSize); + /* The slave mode is not supported. */ + return BASE_STATUS_NOT_SUPPORT; +} + +/** + * @brief Send data in interrupts mode as slave. + * @param handle I2C handle. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SlaveWriteIT(I2C_Handle *handle, unsigned char *wData, unsigned int dataSize) +{ + BASE_FUNC_UNUSED(handle); + BASE_FUNC_UNUSED(wData); + BASE_FUNC_UNUSED(dataSize); + /* The slave mode is not supported. */ + return BASE_STATUS_NOT_SUPPORT; +} + +/** + * @brief I2C DMA Error Handling. + * @param handle I2C handle. + * @retval None. + */ +static void I2CDmaErrorHandle(I2C_Handle *handle) +{ + /* Disable and reset related registers. */ + handle->baseAddress->I2C_GLB.BIT.i2c_enable = BASE_CFG_UNSET; + handle->baseAddress->I2C_CTRL1.BIT.dma_operation = I2C_DMA_OP_NONE; + handle->baseAddress->I2C_CTRL1.BIT.start = BASE_CFG_UNSET; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + handle->errorCode = BASE_STATUS_ERROR; + /* Invoke the error callback function set by the user. */ + if (handle->userCallBack.ErrorCallback != NULL) { + handle->userCallBack.ErrorCallback(handle); + } + handle->state = I2C_STATE_READY; +} + +/** + * @brief I2C DMA completes processing. + * @param handle I2C handle. + * @retval None. + */ +static void I2cDmaDoneHandle(I2C_Handle *handle) +{ + /* Disable and reset related registers. */ + handle->baseAddress->I2C_GLB.BIT.i2c_enable = BASE_CFG_UNSET; + handle->baseAddress->I2C_CTRL1.BIT.dma_operation = I2C_DMA_OP_NONE; + handle->baseAddress->I2C_CTRL1.BIT.start = BASE_CFG_UNSET; + handle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + /* Called the user's callback based on the I2C status. */ + if (handle->state == I2C_STATE_BUSY_MASTER_RX) { + if (handle->userCallBack.RxCplCallback != NULL) { + handle->userCallBack.RxCplCallback(handle); + } + } + if (handle->state == I2C_STATE_BUSY_MASTER_TX) { + if (handle->userCallBack.TxCplCallback != NULL) { + handle->userCallBack.TxCplCallback(handle); + } + } + handle->state = I2C_STATE_READY; +} + +/** + * @brief Wait until all I2C timings are processed. + * @param handle I2C handle. + * @retval None. + */ +static void WaitHandleFinish(I2C_Handle *handle) +{ + unsigned int intrRwa; + + while (1) { /* Wait until all I2C timings are processed in DMA mode. */ + intrRwa = handle->baseAddress->I2C_INTR_RAW.reg; + /* Check whether errors occur. */ + if ((intrRwa & (I2C_INTR_RAW_ARB_LOST_MASK | I2C_INTR_RAW_ACK_BIT_UNMATCH_MASK)) > 0) { + I2CDmaErrorHandle(handle); + break; + } + if ((intrRwa & I2C_INTR_RAW_ALL_CMD_DONE_MASK) > 0) { + I2cDmaDoneHandle(handle); + break; + } + } +} + +/** + * @brief The I2C uses the DMA completion callback function registered by the DMA module. + * @param handle I2C handle. + * @retval None. + */ +static void DMAFinishFun(void *handle) +{ + I2C_ASSERT_PARAM(handle != NULL); + I2C_Handle *i2cHandle = (I2C_Handle *)(handle); + I2C_ASSERT_PARAM(IsI2CInstance(i2cHandle->baseAddress)); + + WaitHandleFinish(i2cHandle); +} + +/** + * @brief The I2C uses the DMA error callback function registered by the DMA module. + * @param handle I2C handle. + * @retval None. + */ +static void DmaErrorHandlerFun(void *handle) +{ + I2C_ASSERT_PARAM(handle != NULL); + I2C_Handle *i2cHandle = (I2C_Handle *)(handle); + I2C_ASSERT_PARAM(IsI2CInstance(i2cHandle->baseAddress)); + + /* Disable and reset related registers. */ + i2cHandle->baseAddress->I2C_GLB.BIT.i2c_enable = BASE_CFG_UNSET; + i2cHandle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + i2cHandle->errorCode = BASE_STATUS_ERROR; + if (i2cHandle->userCallBack.ErrorCallback != NULL) { + i2cHandle->userCallBack.ErrorCallback(i2cHandle); + } + /* Called the user's callback based on the I2C status. */ + if (i2cHandle->state == I2C_STATE_BUSY_MASTER_TX) { + HAL_DMA_StopChannel(i2cHandle->dmaHandle, i2cHandle->txDmaCh); + } else if (i2cHandle->state == I2C_STATE_BUSY_MASTER_RX) { + HAL_DMA_StopChannel(i2cHandle->dmaHandle, i2cHandle->rxDmaCh); + } + i2cHandle->state = I2C_STATE_READY; +} + +/** + * @brief Receiving data in DMA mode as master. + * @param handle I2C handle. + * @param devAddr Slave Device Address. + * @param rData Address of the data buff to be receiving. + * @param dataSize Number of the data to be receiving. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_MasterReadDMA(I2C_Handle *handle, unsigned short devAddr, + unsigned char *rData, unsigned int dataSize) +{ + I2C_ASSERT_PARAM(handle != NULL && rData != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_ASSERT_PARAM(handle->rxDmaCh < CHANNEL_MAX_NUM); + I2C_PARAM_CHECK_WITH_RET(devAddr <= I2C_MAX_DEV_ADDR, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + + /* Configuring the I2C state and transmission parameters. */ + handle->state = I2C_STATE_BUSY_MASTER_RX; + handle->transferBuff = rData; + handle->transferSize = dataSize; + handle->transferCount = 0; + + /* Wait I2C bus is idle. */ + WaitSendComplete(handle); + + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->rxDmaCh].ChannelFinishCallBack = DMAFinishFun; + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->rxDmaCh].ChannelErrorCallBack = DmaErrorHandlerFun; + if (HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t)&(handle->baseAddress->I2C_RX_FIFO), + (uintptr_t)handle->transferBuff, handle->transferSize, handle->rxDmaCh) != BASE_STATUS_OK) { + handle->state = I2C_STATE_READY; + return BASE_STATUS_ERROR; + } + + /* Enable I2C */ + handle->baseAddress->I2C_GLB.BIT.i2c_enable = BASE_CFG_SET; + + SetDevAddr(handle, devAddr); + /* Configuring the I2C Timing */ + ConfigStandardReadCmd(handle); + /* The number of configuration cycles is used only when the read data is greater than 2. */ + if (handle->transferSize >= 2) { + handle->baseAddress->I2C_LOOP1.BIT.loop_num1 = handle->transferSize -2; /* Subtract 2 bytes from the header. */ + } else { + handle->baseAddress->I2C_LOOP1.BIT.loop_num1 = 0; + } + handle->baseAddress->I2C_CTRL1.BIT.dma_operation = I2C_DMA_OP_READ; + handle->baseAddress->I2C_CTRL1.BIT.start = BASE_CFG_SET; + return BASE_STATUS_OK; +} + +/** + * @brief Send data in DMA mode as master. + * @param handle I2C handle. + * @param devAddr Slave Device Address. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_MasterWriteDMA(I2C_Handle *handle, unsigned short devAddr, + unsigned char *wData, unsigned int dataSize) +{ + I2C_ASSERT_PARAM(handle != NULL && wData != NULL); + I2C_ASSERT_PARAM(handle->txDmaCh < CHANNEL_MAX_NUM); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + I2C_PARAM_CHECK_WITH_RET(devAddr <= I2C_MAX_DEV_ADDR, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + I2C_PARAM_CHECK_WITH_RET(handle->state == I2C_STATE_READY, BASE_STATUS_ERROR); + + /* Configuring the I2C state and transmission parameters. */ + handle->state = I2C_STATE_BUSY_MASTER_TX; + handle->transferSize = dataSize; + handle->transferCount = 0; + handle->transferBuff = wData; + + /* Wait I2C bus is idle. */ + WaitSendComplete(handle); + /* Registers the callback function after the DMA transfer is complete. */ + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->txDmaCh].ChannelFinishCallBack = DMAFinishFun; + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->txDmaCh].ChannelErrorCallBack = DmaErrorHandlerFun; + if (HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t)handle->transferBuff, + (uintptr_t)&handle->baseAddress->I2C_TX_FIFO, + handle->transferSize, handle->txDmaCh) != BASE_STATUS_OK) { + handle->state = I2C_STATE_READY; + return BASE_STATUS_ERROR; + } + + /* Enable I2C */ + handle->baseAddress->I2C_GLB.BIT.i2c_enable = BASE_CFG_SET; + + SetDevAddr(handle, devAddr); + /* Configuring the I2C Timing */ + ConfigStandardWriteCmd(handle); + handle->baseAddress->I2C_LOOP1.BIT.loop_num1 = handle->transferSize - 1; + handle->baseAddress->I2C_CTRL1.BIT.dma_operation = I2C_DMA_OP_WRITE; + handle->baseAddress->I2C_CTRL1.BIT.start = BASE_CFG_SET; + return BASE_STATUS_OK; +} + +/** + * @brief Receiving data in DMA mode as slave. + * @param handle I2C handle. + * @param rData Address of the data buff to be receiving. + * @param dataSize Number of the data to be receiving. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SlaveReadDMA(I2C_Handle *handle, unsigned char *rData, unsigned int dataSize) +{ + BASE_FUNC_UNUSED(handle); + BASE_FUNC_UNUSED(rData); + BASE_FUNC_UNUSED(dataSize); + /**< The slave mode is not supported. */ + return BASE_STATUS_NOT_SUPPORT; +} + +/** + * @brief Send data in DMA mode as salve. + * @param handle I2C handle. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_SlaveWriteDMA(I2C_Handle *handle, unsigned char *wData, unsigned int dataSize) +{ + BASE_FUNC_UNUSED(handle); + BASE_FUNC_UNUSED(wData); + BASE_FUNC_UNUSED(dataSize); + /**< The slave mode is not supported. */ + return BASE_STATUS_NOT_SUPPORT; +} + +/** + * @brief Callback Function Registration. + * @param handle I2C handle. + * @param callbackID Callback function ID.. + * @param pcallback Pointer to the address of the registered callback function. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT, NOT SUPPORT. + */ +BASE_StatusType HAL_I2C_RegisterCallback(I2C_Handle *handle, I2C_CallbackId callbackID, I2C_CallbackFunType pcallback) +{ + BASE_StatusType ret = BASE_STATUS_OK; + + I2C_ASSERT_PARAM(handle != NULL && pcallback != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(handle->baseAddress)); + /* Called the user's callback based on the I2C status. */ + if (handle->state == I2C_STATE_READY) { + switch (callbackID) { + case I2C_MASTER_TX_COMPLETE_CB_ID : /* Register the callback function when the transfer is complete. */ + handle->userCallBack.TxCplCallback = pcallback; + break; + case I2C_MASTER_RX_COMPLETE_CB_ID : + handle->userCallBack.RxCplCallback = pcallback; + break; + case I2C_ERROR_CB_ID : /* Registering an Error Callback Function. */ + handle->userCallBack.ErrorCallback = pcallback; + break; + default: + ret = BASE_STATUS_ERROR; + handle->errorCode = BASE_STATUS_ERROR; + break; + } + } else { /* If the status is not ready, an error is returned. */ + ret = BASE_STATUS_ERROR; + handle->errorCode = BASE_STATUS_ERROR; + } + return ret; +} + +/** + * @brief Interrupt Handling Function. + * @param handle Handle pointers + * @retval None + */ +void HAL_I2C_IrqHandler(void *handle) +{ + I2C_Handle *i2cHandle = (I2C_Handle *)handle; + + I2C_ASSERT_PARAM(i2cHandle != NULL); + I2C_ASSERT_PARAM(IsI2CInstance(i2cHandle->baseAddress)); + + if (CheckInterruptErrorStatus(i2cHandle)) { + return; + } + /* Called the corresponding processing function based on the I2C status. */ + if (i2cHandle->state == I2C_STATE_BUSY_MASTER_TX) { + InterruptTxHandle(i2cHandle); + } else if (i2cHandle->state == I2C_STATE_BUSY_MASTER_RX) { + InterruptRxHandle(i2cHandle); + } else { + i2cHandle->errorCode = BASE_STATUS_ERROR; + /* Disable */ + i2cHandle->baseAddress->I2C_GLB.BIT.i2c_enable = BASE_CFG_UNSET; + /* Clears interrupts and disables interrupt reporting to + facilitate switching between different working modes. */ + i2cHandle->baseAddress->I2C_INTR_EN.reg = I2C_INTR_EN_ALL_DISABLE; + i2cHandle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; + i2cHandle->state = I2C_STATE_READY; + if (i2cHandle->userCallBack.ErrorCallback != NULL) { + i2cHandle->userCallBack.ErrorCallback(i2cHandle); + } + } + /* Check whether all data transmissions are complete. */ + if (i2cHandle->baseAddress->I2C_INTR_STAT.BIT.all_cmd_done) { + InterruptAllDoneHandle(i2cHandle); + } + /* If all data transmissions are moved, close the water mark function. */ + if (i2cHandle->transferCount >= i2cHandle->transferSize) { + i2cHandle->baseAddress->I2C_INTR_EN.BIT.tx_lt_watermark_en = BASE_CFG_UNSET; + i2cHandle->baseAddress->I2C_INTR_EN.BIT.rx_gt_watermark_en = BASE_CFG_UNSET; + } + i2cHandle->baseAddress->I2C_INTR_RAW.reg = I2C_INTR_RAW_ALL_ENABLE; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/iocmg/common/iocmg.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/iocmg/common/iocmg.h new file mode 100644 index 00000000..5127d7a6 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/iocmg/common/iocmg.h @@ -0,0 +1,92 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file iocmg.h + * @author MCU Driver Team + * @brief IOCMG module driver + * @details This file provides functions declaration of iocmg + */ +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_IOCMG_H +#define McuMagicTag_IOCMG_H + +/* Includes ------------------------------------------------------------------ */ +#include "iocmg_ip.h" +/** + * @defgroup IOCMG ICOMG + * @brief IOCMG module. + * @{ + */ + +/** + * @defgroup IOCMG_Common IOMG Common + * @brief IOCMG common external module. + * @{ + */ + +/** + * @defgroup IOCMG_Handle_Definition IOCMG Handle Definition + * @{ + */ +typedef struct { + unsigned int pinTypedef; + IOCMG_PullMode pullMode; + IOCMG_SchmidtMode schmidtMode; + IOCMG_LevelShiftRate levelShiftRate; + IOCMG_DriveRate driveRate; + IOCMG_ExtendHandle handleEx; /**< Extend handle, configuring some special parameters. */ +} IOCMG_Handle; +/** + * @} + */ + +/** + * @defgroup IOCMG_API_Declaration IOCMG HAL API + * @{ + */ +/* Exported global functions ------------------------------------------------- */ +IOCMG_Status HAL_IOCMG_Init(IOCMG_Handle* handle); +IOCMG_Status HAL_IOCMG_SetPinAltFuncMode(unsigned int pinTypedef); +IOCMG_Status HAL_IOCMG_SetPinPullMode(unsigned int pinTypedef, IOCMG_PullMode pullMode); +IOCMG_Status HAL_IOCMG_SetPinSchmidtMode(unsigned int pinTypedef, IOCMG_SchmidtMode schmidtMode); +IOCMG_Status HAL_IOCMG_SetPinLevelShiftRate(unsigned int pinTypedef, IOCMG_LevelShiftRate levelShiftRate); +IOCMG_Status HAL_IOCMG_SetPinDriveRate(unsigned int pinTypedef, IOCMG_DriveRate driveRate); + +IOCMG_Status HAL_IOCMG_SetOscClkOutputMode(bool mode); +IOCMG_Status HAL_IOCMG_SetOscClkFuncMode(bool mode); +IOCMG_Status HAL_IOCMG_SetOscClkDriveRate(IOCMG_OscClkDriveRate oscClkDriveRate); + +IOCMG_FuncMode HAL_IOCMG_GetPinAltFuncMode(unsigned int pinTypedef); +IOCMG_PullMode HAL_IOCMG_GetPinPullMode(unsigned int pinTypedef); +IOCMG_SchmidtMode HAL_IOCMG_GetPinSchmidtMode(unsigned int pinTypedef); +IOCMG_LevelShiftRate HAL_IOCMG_GetPinLevelShiftRate(unsigned int pinTypedef); +IOCMG_DriveRate HAL_IOCMG_GetPinDriveRate(unsigned int pinTypedef); +bool HAL_IOCMG_GetOscClkOutputMode(void); +bool HAL_IOCMG_GetOscClkFuncMode(void); +IOCMG_OscClkDriveRate HAL_IOCMG_GetOscClkDriveRate(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_IOCMG_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/iocmg/inc/iocmg_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/iocmg/inc/iocmg_ip.h new file mode 100644 index 00000000..0f6169a2 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/iocmg/inc/iocmg_ip.h @@ -0,0 +1,347 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file iocmg_ip.h + * @author MCU Driver Team + * @brief IOCMG module driver + * @details This file provides IOConfig register mapping structure. + */ + +/* Macro definitions */ +#ifndef McuMagicTag_IOCMG_IP_H +#define McuMagicTag_IOCMG_IP_H + +/* Includes ------------------------------------------------------------------ */ +#include "baseinc.h" +#include "ioconfig.h" +#include "iomap.h" +/* Macro definitions ---------------------------------------------------------*/ +#ifdef IOCMG_PARAM_CHECK + #define IOCMG_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM + #define IOCMG_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET + #define IOCMG_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else + #define IOCMG_ASSERT_PARAM(para) ((void)0U) + #define IOCMG_PARAM_CHECK_NO_RET(para) ((void)0U) + #define IOCMG_PARAM_CHECK_WITH_RET(param, ret) ((void)0U) +#endif +/** + * @addtogroup IOCMG + * @{ + */ + +/** + * @defgroup IOCMG_IP + * @{ + */ +#define IOCMG_BASE_ADDR_MASK 0xFFFF0000 +#define IOCMG_FUNC_NUM_MASK 0x0000000F +#define IOCMG_REG_VALUE_MASK 0x0000FFFF +/** + * @defgroup IOCMG_Param_Def IOCMG Parameters Definition + * @brief Description of IOCMG configuration parameters. + * @{ + */ +typedef enum { + FUNC_MODE_0 = 0u, + FUNC_MODE_1, + FUNC_MODE_2, + FUNC_MODE_3, + FUNC_MODE_4, + FUNC_MODE_5, + FUNC_MODE_6, + FUNC_MODE_7, + FUNC_MODE_8, + FUNC_MODE_9, + FUNC_MODE_10, + FUNC_MODE_11, + FUNC_MODE_12, + FUNC_MODE_13, + FUNC_MODE_14, + FUNC_MODE_15, + FUNC_MODE_MAX +} IOCMG_FuncMode; + +typedef enum { + SCHMIDT_DISABLE = 0u, + SCHMIDT_ENABLE +} IOCMG_SchmidtMode; + +typedef enum { + PULL_NONE = 0u, + PULL_DOWN, + PULL_UP, + PULL_BOTH, + PULL_MODE_MAX +} IOCMG_PullMode; + +typedef enum { + LEVEL_SHIFT_RATE_FAST = 0u, + LEVEL_SHIFT_RATE_SLOW, + LEVEL_SHIFT_RATE_MAX +} IOCMG_LevelShiftRate; + +typedef enum { + DRIVER_RATE_4 = 0u, + DRIVER_RATE_3, + DRIVER_RATE_2, + DRIVER_RATE_1, + DRIVER_RATE_MAX +} IOCMG_DriveRate; + +typedef enum { + OSC_CLK_DRIVER_RATE_1 = 0u, + OSC_CLK_DRIVER_RATE_2, + OSC_CLK_DRIVER_RATE_3, + OSC_CLK_DRIVER_RATE_4, + OSC_CLK_DRIVER_RATE_MAX +} IOCMG_OscClkDriveRate; + +typedef enum { + IOCMG_STATUS_OK, + IOCMG_BASE_ADDR_ERROR, + IOCMG_REG_ADDR_ERROR, + IOCMG_PIN_FUNC_ERROR, + IOCMG_PARAM_ERROR +} IOCMG_Status; + +/** + * @brief IOCMG extend handle, configuring some special parameters. + */ +typedef struct { +} IOCMG_ExtendHandle; +/** + * @} + */ + +/** + * @brief Set iocmg reg value. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @param regValue value of @ref IOCMG_REG. + * @retval None. + */ +static inline void DCL_IOCMG_SetRegValue(IOCMG_REG *iocmgRegx, unsigned int regValue) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + iocmgRegx->reg = regValue; +} + +/** + * @brief Get iocmg reg value. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @retval iocmgRegx register value. + */ +static inline unsigned int DCL_IOCMG_GetRegValue(IOCMG_REG *iocmgRegx) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + return iocmgRegx->reg; +} + +/** + * @brief Set iocmg function number mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @param funcnum value of @ref IOCMG_FuncMode. + * @retval None. + */ +static inline void DCL_IOCMG_SetFuncNum(IOCMG_REG *iocmgRegx, IOCMG_FuncMode funcnum) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + IOCMG_PARAM_CHECK_NO_RET(funcnum < FUNC_MODE_MAX && funcnum >= FUNC_MODE_0); + iocmgRegx->BIT.func = funcnum; +} + +/** + * @brief Get iocmg function number mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @retval Value of @ref IOCMG_FuncMode. + */ +static inline IOCMG_FuncMode DCL_IOCMG_GetFuncMode(IOCMG_REG *iocmgRegx) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + return iocmgRegx->BIT.func; +} + +/** + * @brief Set iocmg drive rate mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @param driveRate value of @ref IOCMG_DriveRate. + * @retval None. + */ +static inline void DCL_IOCMG_SetDriveRate(IOCMG_REG *iocmgRegx, IOCMG_DriveRate driveRate) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + IOCMG_PARAM_CHECK_NO_RET(driveRate < DRIVER_RATE_MAX && driveRate >= DRIVER_RATE_4); + iocmgRegx->BIT.ds = driveRate; +} + +/** + * @brief Get iocmg drive rate mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @retval Value of @ref IOCMG_DriveRate. + */ +static inline IOCMG_DriveRate DCL_IOCMG_GetDriveRate(IOCMG_REG *iocmgRegx) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + return iocmgRegx->BIT.ds; +} + +/** + * @brief Set iocmg pull up or down mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @param pullMode value of @ref IOCMG_PullMode. + * @retval None. + */ +static inline void DCL_IOCMG_SetPullMode(IOCMG_REG *iocmgRegx, IOCMG_PullMode pullMode) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + IOCMG_PARAM_CHECK_NO_RET(pullMode < PULL_MODE_MAX && pullMode >= PULL_NONE); + iocmgRegx->BIT.pu = (pullMode & 0x02) >> 1; /* 10b: pull up mode */ + iocmgRegx->BIT.pd = pullMode & 0x01; /* 01b: pull down mode */ +} + +/** + * @brief Get iocmg pull up or down mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @retval pullMode value of @ref IOCMG_PullMode. + */ +static inline IOCMG_PullMode DCL_IOCMG_GetPullMode(IOCMG_REG *iocmgRegx) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + unsigned int pullUpMode = iocmgRegx->BIT.pu; + unsigned int pullDownMode = iocmgRegx->BIT.pd; + return (pullUpMode << 1) | pullDownMode; /* 1: shift for up mode bit */ +} + +/** + * @brief Set iocmg level shift rate mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @param levelShiftRate value of @ref IOCMG_LevelShiftRate. + * @retval None. + */ +static inline void DCL_IOCMG_SetLevelShiftRate(IOCMG_REG *iocmgRegx, IOCMG_LevelShiftRate levelShiftRate) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + IOCMG_PARAM_CHECK_NO_RET(levelShiftRate < LEVEL_SHIFT_RATE_MAX && levelShiftRate >= LEVEL_SHIFT_RATE_FAST); + iocmgRegx->BIT.sr = levelShiftRate; +} + +/** + * @brief Get iocmg level shift rate mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @retval levelShiftRate value of @ref IOCMG_LevelShiftRate. + */ +static inline IOCMG_LevelShiftRate DCL_IOCMG_GetLevelShiftRate(IOCMG_REG *iocmgRegx) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + return iocmgRegx->BIT.sr; +} + +/** + * @brief Set iocmg schmidt enable mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @param schmidtMode value of @ref IOCMG_SchmidtMode. + * @retval None. + */ +static inline void DCL_IOCMG_SetSchmidtMode(IOCMG_REG *iocmgRegx, IOCMG_SchmidtMode schmidtMode) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + IOCMG_PARAM_CHECK_NO_RET(schmidtMode <= SCHMIDT_ENABLE && schmidtMode >= SCHMIDT_DISABLE); + iocmgRegx->BIT.se = schmidtMode; +} + +/** + * @brief Get iocmg schmidt enable mode. + * @param iocmgRegx Value of @ref IOCMG_REG. + * @retval schmidtMode value of @ref IOCMG_SchmidtMode. + */ +static inline IOCMG_SchmidtMode DCL_IOCMG_GetSchmidtMode(IOCMG_REG *iocmgRegx) +{ + IOCMG_ASSERT_PARAM(IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))); + return iocmgRegx->BIT.se; +} + +/** + * @brief set iocmg OSC clock output mode. + * @param mode function enable or not. + * @retval None. + */ +static inline void DCL_IOCMG_SetOscClkOutputMode(bool mode) +{ + IOCMG_ASSERT_PARAM(mode == BASE_CFG_ENABLE || mode == BASE_CFG_DISABLE); + IOCMG->iocmg_6.BIT.osc_e = mode; +} + +/** + * @brief Get iocmg OSC clock output mode. + * @param None + * @retval None. + */ +static inline bool DCL_IOCMG_GetOscClkOutputMode(void) +{ + return IOCMG->iocmg_6.BIT.osc_e; +} + +/** + * @brief set iocmg OSC clock output mode. + * @param mode function enable or not. + * @retval None. + */ +static inline void DCL_IOCMG_SetOscClkFuncMode(bool mode) +{ + IOCMG_ASSERT_PARAM(mode == BASE_CFG_ENABLE || mode == BASE_CFG_DISABLE); + IOCMG->iocmg_6.BIT.osc_ie = mode; +} + +/** + * @brief Get iocmg OSC clock output enable mode. + * @param None. + * @retval None. + */ +static inline bool DCL_IOCMG_GetOscClkFuncMode(void) +{ + return IOCMG->iocmg_6.BIT.osc_ie; +} + +/** + * @brief Set iocmg OSC drive rate mode. + * @param oscClkDriveRate value of @ref IOCMG_DriveRate. + * @retval None. + */ +static inline void DCL_IOCMG_SetOscClkDriveRate(IOCMG_OscClkDriveRate oscClkDriveRate) +{ + IOCMG_PARAM_CHECK_NO_RET(oscClkDriveRate < OSC_CLK_DRIVER_RATE_MAX && oscClkDriveRate >= OSC_CLK_DRIVER_RATE_1); + IOCMG->iocmg_6.BIT.osc_ds = oscClkDriveRate; +} + +/** + * @brief Get iocmg OSC drive rate mode. + * @param None. + * @retval oscClkDriveRate value of @ref IOCMG_DriveRate. + */ +static inline IOCMG_DriveRate DCL_IOCMG_GetOscClkDriveRate(void) +{ + return IOCMG->iocmg_6.BIT.osc_ds; +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_IOCMG_IP_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/iocmg/src/iocmg.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/iocmg/src/iocmg.c new file mode 100644 index 00000000..c56ed8fa --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/iocmg/src/iocmg.c @@ -0,0 +1,316 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file iocmg.c + * @author MCU Driver Team + * @brief Provides functions about iocmg reg init and config. + */ + +/* Includes ---------------------------------------------------------------------- */ +#include "iocmg.h" +/* param definition -------------------------------------------------------------- */ +/* Function declaration----------------------------------------------------------- */ +static IOCMG_REG* IOCMG_GetRegAddr(unsigned int pinTypedef); + +IOCMG_Status HAL_IOCMG_Init(IOCMG_Handle* handle); +IOCMG_Status HAL_IOCMG_SetPinAltFuncMode(unsigned int pinTypedef); +IOCMG_Status HAL_IOCMG_SetPinPullMode(unsigned int pinTypedef, IOCMG_PullMode pullMode); +IOCMG_Status HAL_IOCMG_SetPinSchmidtMode(unsigned int pinTypedef, IOCMG_SchmidtMode schmidtMode); +IOCMG_Status HAL_IOCMG_SetPinLevelShiftRate(unsigned int pinTypedef, IOCMG_LevelShiftRate levelShiftRate); +IOCMG_Status HAL_IOCMG_SetPinDriveRate(unsigned int pinTypedef, IOCMG_DriveRate driveRate); +IOCMG_Status HAL_IOCMG_SetOscClkOutputMode(bool mode); +IOCMG_Status HAL_IOCMG_SetOscClkFuncMode(bool mode); +IOCMG_Status HAL_IOCMG_SetOscClkDriveRate(IOCMG_OscClkDriveRate oscClkDriveRate); + +IOCMG_FuncMode HAL_IOCMG_GetPinAltFuncMode(unsigned int pinTypedef); +IOCMG_PullMode HAL_IOCMG_GetPinPullMode(unsigned int pinTypedef); +IOCMG_SchmidtMode HAL_IOCMG_GetPinSchmidtMode(unsigned int pinTypedef); +IOCMG_LevelShiftRate HAL_IOCMG_GetPinLevelShiftRate(unsigned int pinTypedef); +IOCMG_DriveRate HAL_IOCMG_GetPinDriveRate(unsigned int pinTypedef); +bool HAL_IOCMG_GetOscClkOutputMode(void); +bool HAL_IOCMG_GetOscClkFuncMode(void); +IOCMG_OscClkDriveRate HAL_IOCMG_GetOscClkDriveRate(void); +/* Function definiton----------------------------------------------------------- */ +/** + * @brief Get pins iocmg reg address + * @param pinTypedef the pin type defined in iomap.h + * @retval IOCMG_REG iocmg reg address. + */ +static IOCMG_REG* IOCMG_GetRegAddr(unsigned int pinTypedef) +{ + /* decode pin's iocmg reg offset address in base address, and conver value to point address */ + unsigned int iocmgBaseAddrValue = (uintptr_t)IOCMG_BASE + ((pinTypedef & 0xFF000000) >> 8); /* 8 : shift 8 bit */ + unsigned int iocmgRegOffsetAddrValue = (pinTypedef & 0x00FF0000) >> 16; /* 16 : shift 16 bit */ + IOCMG_REG* iocmgRegxAddr = (IOCMG_REG*)(void*)(iocmgBaseAddrValue + iocmgRegOffsetAddrValue); + if (!IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegxAddr & IOCMG_BASE_ADDR_MASK))) { + return NULL; + } + return iocmgRegxAddr; +} + +/** + * @brief Initial IOCMG reg by pin number and function mode. + * @param handle IOCMG_Handle. + * @retval status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_Init(IOCMG_Handle* handle) +{ + IOCMG_ASSERT_PARAM(handle != NULL); + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(handle->pinTypedef); + if (!IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))) { + return IOCMG_REG_ADDR_ERROR; + } + IOCMG_REG regValue = {0}; + regValue.BIT.func = (handle->pinTypedef & IOCMG_FUNC_NUM_MASK); + regValue.BIT.ds = handle->driveRate; + regValue.BIT.pd = handle->pullMode & 0x01; /* bit0 : pd */ + regValue.BIT.pu = handle->pullMode >> 1; /* bit1 : pu */ + regValue.BIT.se = handle->schmidtMode; + regValue.BIT.sr = handle->levelShiftRate; + DCL_IOCMG_SetRegValue(iocmgRegx, regValue.reg); + return IOCMG_STATUS_OK; +} + +/** + * @brief Set pins as function mode + * @param pinTypedef the pin type defined in iomap.h + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetPinAltFuncMode(unsigned int pinTypedef) +{ + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + if (!IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))) { + return IOCMG_REG_ADDR_ERROR; + } + /* get iocmg reg default value */ + unsigned int regValue = pinTypedef & IOCMG_REG_VALUE_MASK; + DCL_IOCMG_SetRegValue(iocmgRegx, regValue); + return IOCMG_STATUS_OK; +} + +/** + * @brief Get pins func number + * @param pinTypedef the pin type defined in iomap.h + * @retval pin func number @ref IOCMG_FuncMode. + */ +IOCMG_FuncMode HAL_IOCMG_GetPinAltFuncMode(unsigned int pinTypedef) +{ + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + if (!IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))) { + return IOCMG_REG_ADDR_ERROR; + } + return DCL_IOCMG_GetFuncMode(iocmgRegx); +} + +/** + * @brief Set pins pull mode + * @param pinTypedef the pin type defined in iomap.h + * @param pullMode function define as @ref IOCMG_PullMode + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetPinPullMode(unsigned int pinTypedef, IOCMG_PullMode pullMode) +{ + IOCMG_PARAM_CHECK_WITH_RET(pullMode < PULL_MODE_MAX && pullMode >= PULL_NONE, IOCMG_PARAM_ERROR); + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + if (!IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))) { + return IOCMG_REG_ADDR_ERROR; + } + DCL_IOCMG_SetPullMode(iocmgRegx, pullMode); + return IOCMG_STATUS_OK; +} + +/** + * @brief Get pins pull mode + * @param pinTypedef the pin type defined in iomap.h + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_PullMode HAL_IOCMG_GetPinPullMode(unsigned int pinTypedef) +{ + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + if (!IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))) { + return IOCMG_REG_ADDR_ERROR; + } + return DCL_IOCMG_GetPullMode(iocmgRegx); +} + +/** + * @brief Set Pin Schmidt Mode + * @param pinTypedef the pin type defined in iomap.h + * @param schmidtMode function define as @ref IOCMG_SchmidtMode + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetPinSchmidtMode(unsigned int pinTypedef, IOCMG_SchmidtMode schmidtMode) +{ + IOCMG_PARAM_CHECK_WITH_RET(schmidtMode <= SCHMIDT_ENABLE && schmidtMode >= SCHMIDT_DISABLE, IOCMG_PARAM_ERROR); + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + if (!IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))) { + return IOCMG_REG_ADDR_ERROR; + } + DCL_IOCMG_SetSchmidtMode(iocmgRegx, schmidtMode); + return IOCMG_STATUS_OK; +} + +/** + * @brief Get Pin Schmidt Mode + * @param pinTypedef the pin type defined in iomap.h + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_SchmidtMode HAL_IOCMG_GetPinSchmidtMode(unsigned int pinTypedef) +{ + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + if (!IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))) { + return IOCMG_REG_ADDR_ERROR; + } + return DCL_IOCMG_GetSchmidtMode(iocmgRegx); +} + +/** + * @brief Set Pin level Shift Rate Mode + * @param pinTypedef the pin type defined in iomap.h + * @param schmidtMode function define as @ref IOCMG_SchmidtMode + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetPinLevelShiftRate(unsigned int pinTypedef, IOCMG_LevelShiftRate levelShiftRate) +{ + IOCMG_PARAM_CHECK_WITH_RET(levelShiftRate < LEVEL_SHIFT_RATE_MAX, IOCMG_PARAM_ERROR); + IOCMG_PARAM_CHECK_WITH_RET(levelShiftRate >= LEVEL_SHIFT_RATE_FAST, IOCMG_PARAM_ERROR); + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + if (!IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))) { + return IOCMG_REG_ADDR_ERROR; + } + DCL_IOCMG_SetLevelShiftRate(iocmgRegx, levelShiftRate); + return IOCMG_STATUS_OK; +} + +/** + * @brief Get Pin Schmidt Mode + * @param pinTypedef the pin type defined in iomap.h + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_LevelShiftRate HAL_IOCMG_GetPinLevelShiftRate(unsigned int pinTypedef) +{ + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + if (!IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))) { + return IOCMG_REG_ADDR_ERROR; + } + return DCL_IOCMG_GetLevelShiftRate(iocmgRegx); +} + +/** + * @brief Set Pin drive Rate Mode + * @param pinTypedef the pin type defined in iomap.h + * @param driveRate function define as @ref IOCMG_DriveRate + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetPinDriveRate(unsigned int pinTypedef, IOCMG_DriveRate driveRate) +{ + /* get iocmg reg address */ + IOCMG_PARAM_CHECK_WITH_RET(driveRate < DRIVER_RATE_MAX && driveRate >= DRIVER_RATE_4, IOCMG_PARAM_ERROR); + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + if (!IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))) { + return IOCMG_REG_ADDR_ERROR; + } + DCL_IOCMG_SetDriveRate(iocmgRegx, driveRate); + return IOCMG_STATUS_OK; +} + +/** + * @brief Get Pin drive Rate Mode + * @param pinTypedef the pin type defined in iomap.h + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_DriveRate HAL_IOCMG_GetPinDriveRate(unsigned int pinTypedef) +{ + /* get iocmg reg address */ + IOCMG_REG* iocmgRegx = IOCMG_GetRegAddr(pinTypedef); + if (!IsIOCMGInstance((void *)((uintptr_t)(void *)iocmgRegx & IOCMG_BASE_ADDR_MASK))) { + return IOCMG_REG_ADDR_ERROR; + } + return DCL_IOCMG_GetDriveRate(iocmgRegx); +} + +/** + * @brief Set OSC Pin clock output enable mode + * @param mode function enable or not + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetOscClkOutputMode(bool mode) +{ + IOCMG_ASSERT_PARAM(mode == BASE_CFG_ENABLE || mode == BASE_CFG_DISABLE); + DCL_IOCMG_SetOscClkOutputMode(mode); + return IOCMG_STATUS_OK; +} + +/** + * @brief Get OSC Pin clock output enable mode + * @retval bool enable or not + */ +bool HAL_IOCMG_GetOscClkOutputMode(void) +{ + return DCL_IOCMG_GetOscClkOutputMode(); +} + +/** + * @brief Set OSC Pin function enable mode + * @param mode function enable or not + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetOscClkFuncMode(bool mode) +{ + IOCMG_ASSERT_PARAM(mode == BASE_CFG_ENABLE || mode == BASE_CFG_DISABLE); + DCL_IOCMG_SetOscClkFuncMode(mode); + return IOCMG_STATUS_OK; +} + +/** + * @brief Get OSC Pin Pin function enable mode + * @retval bool enable or not + */ +bool HAL_IOCMG_GetOscClkFuncMode(void) +{ + return DCL_IOCMG_GetOscClkFuncMode(); +} + +/** + * @brief Set OSC Pin drive rate mode + * @param driveRate osc drive rate + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_Status HAL_IOCMG_SetOscClkDriveRate(IOCMG_OscClkDriveRate oscClkDriveRate) +{ + IOCMG_PARAM_CHECK_WITH_RET(oscClkDriveRate < OSC_CLK_DRIVER_RATE_MAX && \ + oscClkDriveRate >= OSC_CLK_DRIVER_RATE_1, IOCMG_PARAM_ERROR); + DCL_IOCMG_SetOscClkDriveRate(oscClkDriveRate); + return IOCMG_STATUS_OK; +} + +/** + * @brief Get OSC Pin drive rate mode + * @retval IOCMG_Status @ref IOCMG_Status. + */ +IOCMG_OscClkDriveRate HAL_IOCMG_GetOscClkDriveRate(void) +{ + return DCL_IOCMG_GetOscClkDriveRate(); +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/iwdg/common/inc/iwdg.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/iwdg/common/inc/iwdg.h new file mode 100644 index 00000000..48dc1086 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/iwdg/common/inc/iwdg.h @@ -0,0 +1,97 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file iwdg.h + * @author MCU Driver Team + * @brief IWDG module driver + * @details The header file contains the following declaration: + * + IWDG handle structure definition. + * + Initialization functions. + * + IWDG Set And Get Functions. + * + Interrupt Handler Functions. + */ + +#ifndef McuMagicTag_IWDG_H +#define McuMagicTag_IWDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "iwdg_ip.h" +/** + * @defgroup IWDG IWDG + * @brief IWDG module. + * @{ + */ + +/** + * @defgroup IWDG_Common IWDG Common + * @brief IWDG common external module. + * @{ + */ + +/** + * @defgroup IWDG_Handle_Definition IWDG Handle Definition + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ +typedef void (* IWDG_CallbackType)(void *handle); + +/** + * @brief IWDG handle structure definition. + */ +typedef struct _IWDG_Handle { + IWDG_RegStruct *baseAddress; /**< IWDG Registers address. */ + unsigned int timeValue; /**< IWDG time value. */ + unsigned int freqDivValue; /**< IWDG freq div value. */ + IWDG_TimeType timeType; /**< IWDG time type. */ + bool enableIT; /**< true:enable false:disable interrupt. */ + IWDG_UserCallBack userCallBack; /**< User callback */ + IWDG_ExtendHandle handleEx; /**< IWDG extend parameter */ +} IWDG_Handle; + +/** + * @} + */ + +/** + * @defgroup IWDG_API_Declaration IWDG HAL API + * @{ + */ + +BASE_StatusType HAL_IWDG_Init(IWDG_Handle *handle); +void HAL_IWDG_SetTimeValue(IWDG_Handle *handle, unsigned int timeValue, IWDG_TimeType timeType); +unsigned int HAL_IWDG_GetLoadValue(IWDG_Handle *handle); +unsigned int HAL_IWDG_GetCounterValue(IWDG_Handle *handle); +void HAL_IWDG_Refresh(IWDG_Handle *handle); +void HAL_IWDG_Start(IWDG_Handle *handle); +void HAL_IWDG_Stop(IWDG_Handle *handle); +void HAL_IWDG_RegisterCallback(IWDG_Handle *handle, IWDG_CallbackType callBackFunc); +void HAL_IWDG_IrqHandler(void *handle); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_IWDG_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/iwdg/inc/iwdg_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/iwdg/inc/iwdg_ip.h new file mode 100644 index 00000000..0b92c351 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/iwdg/inc/iwdg_ip.h @@ -0,0 +1,314 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file iwdg_ip.h + * @author MCU Driver Team + * @brief IWDG module driver + * @details The header file contains the following declaration: + * + IWDG configuration enums. + * + IWDG register structures. + * + IWDG DCL Functions. + * + Parameters check functions. + */ + +#ifndef McuMagicTag_IWDG_IP_H +#define McuMagicTag_IWDG_IP_H + +/* Includes ------------------------------------------------------------------*/ +#include "baseinc.h" +/* Macro definition */ +#ifdef IWDG_PARAM_CHECK + #define IWDG_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM + #define IWDG_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET + #define IWDG_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else + #define IWDG_ASSERT_PARAM(para) ((void)0U) + #define IWDG_PARAM_CHECK_NO_RET(para) ((void)0U) + #define IWDG_PARAM_CHECK_WITH_RET(param, ret) ((void)0U) +#endif +/** + * @addtogroup IWDG + * @{ + */ + +/** + * @defgroup IWDG_IP IWDG_IP + * @brief IWDG_IP: iwdg_v0. + * @{ + */ + +/** + * @defgroup IWDG_Param_Def IWDG Parameters Definition + * @brief Description of IWDG configuration parameters. + * @{ + */ +/* MACRO definitions -------------------------------------------------------*/ +#define FREQ_CONVERT_MS_UNIT 1000 +#define FREQ_CONVERT_US_UNIT 1000000 +/* Typedef definitions -------------------------------------------------------*/ +typedef enum { + IWDG_TIME_UNIT_TICK = 0x00000000U, + IWDG_TIME_UNIT_S = 0x00000001U, + IWDG_TIME_UNIT_MS = 0x00000002U, + IWDG_TIME_UNIT_US = 0x00000003U +} IWDG_TimeType; + +/** + * @brief IWDG extend handle. + */ +typedef struct _IWDG_ExtendHandle { +} IWDG_ExtendHandle; + +/** + * @brief IWDG user callback. + */ +typedef struct { + void (* CallbackFunc)(void *handle); /**< IWDG callback Function */ +} IWDG_UserCallBack; +/** + * @} + */ + +/** + * @defgroup IWDG_Reg_Def IWDG Register Definition + * @brief Description IWDG register mapping structure. + * @{ + */ + +/** + * @brief enable interrupt and reset. + */ +typedef union { + unsigned int reg; + struct { + unsigned int wdgen : 1; /**< enable interrupt. */ + unsigned int resen : 1; /**< enable reset. */ + unsigned int reserved0 : 30; + } BIT; +} volatile IWDG_CONTROL_REG; + +/** + * @brief original interrupt signal. + */ +typedef union { + unsigned int reg; + struct { + unsigned int wdogris : 1; /**< original interrupt status. */ + unsigned int reserved : 31; + } BIT; +} volatile IWDG_RIS_REG; + +/** + * @brief mask interrupt signal. + */ +typedef union { + unsigned int reg; + struct { + unsigned int wdogmis : 1; /**< maske interrupt status. */ + unsigned int reserved : 31; + } BIT; +} volatile IWDG_MIS_REG; + +/** + * @brief IWDG Register Structure definition. + */ +typedef struct { + unsigned int wdg_load; /**< WDG load value register. */ + unsigned int wdgvalue; /**< WDG current value register. */ + IWDG_CONTROL_REG WDG_CONTROL; /**< WDG interrupt and reset enable register. */ + unsigned int wdg_intclr; /**< WDG interrupt clear register. */ + IWDG_RIS_REG WDG_RIS; /**< WDG original interrupt register. */ + IWDG_MIS_REG WDG_MIS; /**< WDG mask interrupt register. */ + unsigned int reserved0[762]; + unsigned int wdg_lock; /**< WDG lock register. */ +} volatile IWDG_RegStruct; + +/** + * @} + */ + +/** + * @brief Setting the load value of the IWDG counter. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @param loadValue Load value of the IWDG counter. + * @retval None. + */ +static inline void DCL_IWDG_SetLoadValue(IWDG_RegStruct *iwdgx, unsigned int loadValue) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + iwdgx->wdg_load = loadValue; +} + +/** + * @brief Getting the load value of the IWDG load register. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval unsigned int IWDG load value. + */ +static inline unsigned int DCL_IWDG_GetLoadValue(const IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + return iwdgx->wdg_load; +} + +/** + * @brief Getting the value of the IWDG counter register. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval unsigned int IWDG counter value. + */ +static inline unsigned int DCL_IWDG_GetCounterValue(const IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + return iwdgx->wdgvalue; +} + +/** + * @brief Clear interrupt and reload watchdog counter value. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval None. + */ +static inline void DCL_IWDG_Refresh(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + iwdgx->wdg_intclr = BASE_CFG_SET; +} + +/** + * @brief Getting value of IWDG RIS register. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval unsigned int Value of IWDG RIS register. + */ +static inline unsigned int DCL_IWDG_GetRIS(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + return iwdgx->WDG_RIS.BIT.wdogris; +} + +/** + * @brief Getting value of IWDG MIS register. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval unsigned int Value of IWDG MIS register. + */ +static inline unsigned int DCL_IWDG_GetMIS(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + return iwdgx->WDG_MIS.BIT.wdogmis; +} + +/** + * @brief Disable write and read IWDG registers except IWDG_LOCK. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval None. + */ +static inline void DCL_IWDG_LockReg(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + iwdgx->wdg_lock = BASE_CFG_SET; +} + +/** + * @brief Enable write and read IWDG registers. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval None. + */ +static inline void DCL_IWDG_UnlockReg(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + iwdgx->wdg_lock = 0x1ACCE551U; /* Unlock register value */ +} + +/** + * @brief Enable reset signal. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval None. + */ +static inline void DCL_IWDG_EnableReset(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + iwdgx->WDG_CONTROL.BIT.resen = BASE_CFG_SET; +} + +/** + * @brief Disable reset signal. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval None. + */ +static inline void DCL_IWDG_DisableReset(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + iwdgx->WDG_CONTROL.BIT.resen = BASE_CFG_UNSET; +} + +/** + * @brief Start watchdog and enable interrupt signal. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval None. + */ +static inline void DCL_IWDG_EnableInterrupt(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + iwdgx->WDG_CONTROL.BIT.wdgen = BASE_CFG_SET; +} + +/** + * @brief Disable interrupt signal. + * @param iwdgx Value of @ref IWDG_RegStruct. + * @retval None. + */ +static inline void DCL_IWDG_DisableInterrupt(IWDG_RegStruct *iwdgx) +{ + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgx)); + iwdgx->WDG_CONTROL.BIT.wdgen = BASE_CFG_UNSET; +} + +/** + * @brief check iwdg time type parameter. + * @param timeType Value of @ref IWDG_TimeType. + * @retval Bool. + */ +static inline bool IsIwdgTimeType(IWDG_TimeType timeType) +{ + return (timeType == IWDG_TIME_UNIT_TICK || + timeType == IWDG_TIME_UNIT_S || + timeType == IWDG_TIME_UNIT_MS || + timeType == IWDG_TIME_UNIT_US); +} + +/** + * @brief check iwdg time value parameter. + * @param baseAddress Value of @ref IWDG_RegStruct + * @param timeValue time value + * @param timeType Value of @ref IWDG_TimeType. + * @retval Bool. + */ +static inline bool IsIwdgTimeValue(IWDG_RegStruct *baseAddress, float timeValue, IWDG_TimeType timeType) +{ + float clockFreq = (float)HAL_CRG_GetIpFreq((void *)baseAddress); + float maxSecond = (float)(0xFFFFFFFF / clockFreq); /* 0xFFFFFFFF max IWDG register value */ + return ((timeType == IWDG_TIME_UNIT_TICK && timeValue <= 0xFFFFFFFF) || + (timeType == IWDG_TIME_UNIT_S && maxSecond >= timeValue) || + (timeType == IWDG_TIME_UNIT_MS && maxSecond >= timeValue / FREQ_CONVERT_MS_UNIT) || + (timeType == IWDG_TIME_UNIT_US && maxSecond >= timeValue / FREQ_CONVERT_US_UNIT)); +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_IWDG_IP_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/iwdg/src/iwdg.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/iwdg/src/iwdg.c new file mode 100644 index 00000000..dcc57f0c --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/iwdg/src/iwdg.c @@ -0,0 +1,217 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file iwdg.c + * @author MCU Driver Team + * @brief IWDG module driver + * @details This file provides firmware functions to manage the following functionalities of the IWDG. + * + Initialization functions. + * + IWDG Set And Get Functions. + * + Interrupt Handler Functions. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "iwdg.h" + +static unsigned int IWDG_CalculateRegTimeout(IWDG_RegStruct *baseAddress, float timeValue, IWDG_TimeType timeType); + +/** + * @brief Initializing IWDG values + * @param handle Value of @ref IWDG_handle. + * @retval BASE_StatusType: OK, ERROR + */ +BASE_StatusType HAL_IWDG_Init(IWDG_Handle *handle) +{ + IWDG_ASSERT_PARAM(handle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(handle->baseAddress)); + IWDG_PARAM_CHECK_WITH_RET(IsIwdgTimeType(handle->timeType), BASE_STATUS_ERROR); + IWDG_PARAM_CHECK_WITH_RET(IsIwdgTimeValue(handle->baseAddress, handle->timeValue, handle->timeType), + BASE_STATUS_ERROR); + /* baseaddress = IWDG */ + HAL_IWDG_SetTimeValue(handle, handle->timeValue, handle->timeType); + /* Set IWDG Reset and Interrupt */ + handle->baseAddress->WDG_CONTROL.BIT.resen = BASE_CFG_ENABLE; + handle->baseAddress->WDG_CONTROL.BIT.wdgen = handle->enableIT; + return BASE_STATUS_OK; +} + +/** + * @brief Calculate Reg Timeout. + * @param timeValue Value to be load to iwdg. + * @param timeType Value of @ref IWDG_TimeType. + * @retval unsigned int timeout Value. + */ +static unsigned int IWDG_CalculateRegTimeout(IWDG_RegStruct *baseAddress, float timeValue, IWDG_TimeType timeType) +{ + float clockFreq = (float)HAL_CRG_GetIpFreq((void *)baseAddress); + unsigned int timeoutValue = 0x00000000U; + switch (timeType) { + case IWDG_TIME_UNIT_TICK: /* If the time type is tick, calculate the timeout value. */ + timeoutValue = (unsigned int)timeValue; + break; + case IWDG_TIME_UNIT_S: /* If the time type is s, calculate the timeout value. */ + timeoutValue = (unsigned int)(timeValue * clockFreq); + break; + case IWDG_TIME_UNIT_MS: /* If the time type is ms, calculate the timeout value. */ + timeoutValue = (unsigned int)(timeValue * clockFreq / FREQ_CONVERT_MS_UNIT); + break; + case IWDG_TIME_UNIT_US: /* If the time type is us, calculate the timeout value. */ + timeoutValue = (unsigned int)(timeValue * clockFreq / FREQ_CONVERT_US_UNIT); + break; + default: + break; + } + return timeoutValue; +} + +/** + * @brief Setting the load value of the IWDG counter. + * @param handle Value of @ref IWDG_handle. + * @param timeValue time value. + * @param timeType IWDG time type. + * @retval None. + */ +void HAL_IWDG_SetTimeValue(IWDG_Handle *handle, unsigned int timeValue, IWDG_TimeType timeType) +{ + IWDG_ASSERT_PARAM(handle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(handle->baseAddress)); + IWDG_PARAM_CHECK_NO_RET(IsIwdgTimeType(handle->timeType)); + IWDG_PARAM_CHECK_NO_RET(IsIwdgTimeValue(handle->baseAddress, handle->timeValue, handle->timeType)); + /* handle->baseAddress only could be configured IWDG */ + unsigned int value = IWDG_CalculateRegTimeout(handle->baseAddress, timeValue, timeType); + DCL_IWDG_SetLoadValue(handle->baseAddress, value); +} + +/** + * @brief refresh the IWDG counter. + * @param handle Value of @ref IWDG_handle. + * @retval None. + */ +void HAL_IWDG_Refresh(IWDG_Handle *handle) +{ + IWDG_ASSERT_PARAM(handle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(handle->baseAddress)); + handle->baseAddress->wdg_intclr = BASE_CFG_SET; /* clear iwdg interrupt and load value */ +} + +/** + * @brief obtain the load value. + * @param handle Value of @ref IWDG_handle. + * @retval unsigned int time value. + */ +unsigned int HAL_IWDG_GetLoadValue(IWDG_Handle *handle) +{ + IWDG_ASSERT_PARAM(handle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(handle->baseAddress)); + return DCL_IWDG_GetLoadValue(handle->baseAddress); +} + +/** + * @brief obtain the current count value.. + * @param handle Value of @ref IWDG_handle. + * @retval unsigned int Counter value. + */ +unsigned int HAL_IWDG_GetCounterValue(IWDG_Handle *handle) +{ + IWDG_ASSERT_PARAM(handle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(handle->baseAddress)); + float res = (float)handle->baseAddress->wdgvalue; + unsigned int freq = HAL_CRG_GetIpFreq((void *)handle->baseAddress); + /* check clockFreq not equal zero */ + if (freq == 0) { + return 0; + } + switch (handle->timeType) { + case IWDG_TIME_UNIT_TICK : /* Number of tick currently calculated */ + break; + case IWDG_TIME_UNIT_S : + /* Number of seconds currently calculated */ + res = res / freq; + break; + case IWDG_TIME_UNIT_MS : + res = res * FREQ_CONVERT_MS_UNIT / freq; + break; + case IWDG_TIME_UNIT_US : + /* Number of microseconds currently calculated */ + res = res * FREQ_CONVERT_US_UNIT / freq; + break; + default: + break; + } + return (unsigned int)res; /* return current counter value */ +} + +/** + * @brief Start the IWDG count. + * @param handle Value of @ref IWDG_handle. + * @retval None. + */ +void HAL_IWDG_Start(IWDG_Handle *handle) +{ + IWDG_ASSERT_PARAM(handle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(handle->baseAddress)); + DCL_IWDG_EnableInterrupt(handle->baseAddress); + DCL_IWDG_Refresh(handle->baseAddress); +} + +/** + * @brief Stop the IWDG count. + * @param handle Value of @ref IWDG_handle. + * @retval None. + */ +void HAL_IWDG_Stop(IWDG_Handle *handle) +{ + IWDG_ASSERT_PARAM(handle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(handle->baseAddress)); + DCL_IWDG_DisableReset(handle->baseAddress); + DCL_IWDG_DisableInterrupt(handle->baseAddress); +} + +/** + * @brief Register IWDG interrupt callback. + * @param handle Value of @ref IWDG_handle. + * @param callBackFunc Value of @ref IWDG_CallbackType. + * @retval None + */ +void HAL_IWDG_RegisterCallback(IWDG_Handle *handle, IWDG_CallbackType callBackFunc) +{ + IWDG_ASSERT_PARAM(handle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(handle->baseAddress)); + if (callBackFunc != NULL) { + /* Invoke the callback function. */ + handle->userCallBack.CallbackFunc = callBackFunc; + } +} + +/** + * @brief Interrupt handler processing function. + * @param handle IWDG_Handle. + * @retval None. + */ +void HAL_IWDG_IrqHandler(void *handle) +{ + IWDG_Handle *iwdgHandle = (IWDG_Handle *)handle; + IWDG_ASSERT_PARAM(iwdgHandle != NULL); + IWDG_ASSERT_PARAM(IsIWDGInstance(iwdgHandle->baseAddress)); + + if (iwdgHandle->baseAddress->WDG_MIS.BIT.wdogmis == 0x01) { /* Interrupt flag is set, fed dog in callback */ + if (iwdgHandle->userCallBack.CallbackFunc) { + iwdgHandle->userCallBack.CallbackFunc(iwdgHandle); + } + } +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/nav/bat.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/nav/bat.c new file mode 100644 index 00000000..c43e4623 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/nav/bat.c @@ -0,0 +1,162 @@ +#include "bat.h" +#include "adc.h" +#include "main.h" +#include "usart.h" +BAT_S Bat; + +uint8_t req_batBMS[6] = {0x06, 0x01, 0x10, 0x00, 0x00, 0x17}; +uint8_t set_batOPMOS[6] = {0x06, 0x01, 0x10, 0x00, 0x00, 0x17}; +uint8_t set_batCLMOS[6] = {0x06, 0x01, 0x10, 0x00, 0x00, 0x17}; + + +void bat_init(void) +{ + + + +} +//2820-2437 +float get_vbat(void)//õصѹ +{ + uint16_t adcvel; + if(ADC1_Rstart_DMA(&adcvel,0))//ADCִ + { + return -1; + }else + { + Bat.c_bat[1] = constrain(((adcvel-2144) / 6.32),0,100);//2144 -19~24.6V + //Bat.c_bat[1] = constrain(((adcvel-2437) /3.83),0,100); + //Bat.c_bat[1] = ((adcvel* 36.3) / 4095.0); + return Bat.c_bat[1]; + } +} + +float get_mbat(void)//õصѹ +{ + //uint8_t bat_msg[8]={0x40,0x0d,0x21,0x02,0x00,0x00,0x00,0x00}; + + + return Bat.c_bat[0]; +} + +void get_battery(void) +{ + battery_send(req_batBMS,6); +} +void RxBatteryMes(uint8_t* cell_buff) +{ + car_state.voltage = ((cell_buff[2] << 8 | cell_buff[3]) * 0x0A)/1000.0; //ܵѹ + car_state.current = ((cell_buff[4] << 8 | cell_buff[5]) * 0x0A)/1000.0; //ܵ + car_state.chargeState = cell_buff[10]; //״̬ + car_state.multistate = cell_buff[11]; //״̬--硢ŵ硢MOSѴ + car_state.temperature = cell_buff[12]; //ǰ¶(1) + car_state.capacityRatio = cell_buff[13]; // +} + + + +/* + ============================================================================ + Name : KaerMan.c + Author : + Version : + Copyright : Your copyright notice + Description : Hello World in C, Ansi-style + ============================================================================ + */ + +#include +#include + + + +static double p_last = 0; +static double x_last = 0; + +// ¶ȼжơ +#define P_Q 0.1 +// +#define M_R 0.05 +/* + Q:Q󣬶̬Ӧ죬ȶԱ仵 + R:R󣬶̬ӦȶԱ + pijֵȡDzΪ0Ϊ0Ļ˲ΪѾ˲ˣ +q,rֵҪԳ˾(¶ȼжƣԼijжǿ) +r˲ʵߵ̶ȣrԽСԽӽ +q˲ƽ̶ȣqԽСԽƽ +*/ +static double KalmanFilter(const double ResrcData) +{ + + double R = M_R; + double Q = P_Q; + + double x_mid = x_last; + double x_now; + + double p_mid ; + double p_now; + + double kg; + + //p_last kalmanFilter_A pֱȡ0 + x_mid=x_last; //x_last=x(k-1|k-1),x_mid=x(k|k-1) + p_mid=p_last+Q; //p_mid=p(k|k-1),p_last=p(k-1|k-1),Q= + + /* + * ˲Ҫʽ + */ + kg=p_mid/(p_mid+R); //kgΪkalman filterR Ϊ + x_now=x_mid+kg*(ResrcData-x_mid); //Ƴֵ + p_now=(1-kg)*p_mid; //ֵӦcovariance + p_last = p_now; //covariance ֵ + x_last = x_now; //ϵͳ״ֵ̬ + + return x_now; +} + +float prevData[3]={0,0,0}; +//pijֵȡDzΪ0Ϊ0Ļ˲ΪѾ˲ˣ +float p[3]={0.05,0.05,0.05}; +float q[3]={P_Q,P_Q,P_Q}; +float r[3]={M_R,M_R,M_R}; +float kGain[3]={0}; + +float kalmanFilter_3A(float inData,uint8_t wch) +{ + //float p=0.01, q=P_Q, r=M_R, kGain=0; + p[wch] = p[wch]+q[wch]; + kGain[wch] = p[wch]/(p[wch]+r[wch]); + + inData = prevData[wch]+(kGain[wch]*(inData-prevData[wch])); + p[wch] = (1-kGain[wch])*p[wch]; + + prevData[wch] = inData; + + return inData; +} + +//int main(void) { +// double datas[] = {99, 33, 45, 99, 100, 24}; +// int len = sizeof(datas)/ sizeof(datas[0]); +// +// for(int i = 0; i < len; i++){ +// printf("datas[i]=%lf, number=%lf, %f\n", datas[i], KalmanFilter(datas[i]), kalmanFilter_A(datas[i])); +// } +// +// return 0; +//} + + + + + + + + + + + + + + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/nav/bat.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/nav/bat.h new file mode 100644 index 00000000..e9a23ac6 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/nav/bat.h @@ -0,0 +1,43 @@ +#ifndef __BAT_H +#define __BAT_H + +#ifdef __cplusplus +extern "C" { +#endif + + +#include "stm32f1xx_hal.h" +typedef struct +{ + float c_bat[3];//ֵͨ + uint8_t bat_state;//ң״̬ң롢Ͽ + uint16_t bat_count; +}BAT_S; + +typedef struct QueryInstruction +{ + uint8_t batteryMes[6]; //ѹϢ + uint8_t openMOS[6]; //MOS + uint8_t closeMOS[6]; //رMOS +}queryInstruction; + +extern BAT_S Bat; +extern queryInstruction query; + +void bat_init(void); +float get_mbat(void);//õصѹ +float get_vbat(void);//õصѹ +float get_mangle(void);//õǶ + +void get_battery(void); +void RxBatteryMes(uint8_t* cell_buff); + + +float kalmanFilter_3A(float inData,uint8_t wch); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/nav/core.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/nav/core.c new file mode 100644 index 00000000..d8358c57 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/nav/core.c @@ -0,0 +1,8 @@ +#include "core.h" + + +void ctrl_task(void) +{ + // + +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/nav/core.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/nav/core.h new file mode 100644 index 00000000..24736f8d --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/nav/core.h @@ -0,0 +1,19 @@ +#ifndef __CORE_H__ +#define __CORE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + + + + + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/nav/mot.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/nav/mot.c new file mode 100644 index 00000000..a6cb4598 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/nav/mot.c @@ -0,0 +1,368 @@ +#include "mot.h" +#include "can.h" +#include "usart.h" +#include "math.h" +#include "stdlib.h" +#include "gpio.h" + +#include "FreeRTOS.h" +#include "task.h" +#include "main.h" +#include "cmsis_os.h" +/* +õ1 +2b 1d 26 00 79 05 1.401 1.4A/1S +2f 14 26 00 01 +//ת +2F 60 60 00 03 +23 FF 60 00 E8 03 00 00 1000RPM +2B 40 60 00 0F 00 +2B 40 60 00 0F 01 ֹͣ +//Ĭϵַ + +õ2 +2b 1d 26 00 79 05 1.401 1.4A/1S +2f 14 26 00 01 +//ת +2F 60 60 00 03 +23 FF 60 00 E8 03 00 00 1000RPM +2B 40 60 00 0F 00 +2B 40 60 00 0F 01 ֹͣ + +//ַ +2F 15 26 00 02 ַ2 +2f 14 26 00 01 + + +õ3 +2b 1d 26 00 B9 0B 3.001 3A/1S +23 83 60 00 20 03 00 00 üٶٶ800rpm +2f 14 26 00 01 + +//ת +2F 60 60 00 03 +23 FF 60 00 d0 07 00 00 2000RPM +2B 40 60 00 0F 00 +2B 40 60 00 0F 01 ֹͣ +//ַ +2F 15 26 00 03 ַ3 +2f 14 26 00 01 + +õ4 +2b 1d 26 00 59 02 0.601 0.6A/1S +23 81 60 00 C8 00 00 00 λģʽٶ200rpm +2f 14 26 00 01 + + + + +2F 60 60 00 03 +23 FF 60 00 d0 07 00 00 2000RPM +23 FF 60 00 E8 03 00 00 1000RPM +2B 40 60 00 0F 00 +//ַ +2F 15 26 00 04 ַ4 +2f 14 26 00 01 +*/ +void sm_run_spd(int *spd)//ٶ +{ + //PDO +uint8_t send_buf[7]={0x0F,0x00,0x03,0x00,0x00,0x00,0x00}; + + if( spd[0] > 0) + { + if( spd[0] < 200) + { + spd[0] = 200; + } + + } + else if( spd[0] < 0) + { + if( spd[0] > -200) + { + spd[0] = -200; + } + } + send_buf[6] = ((-spd[0])>>24) & 0xff; + send_buf[5] = ((-spd[0])>>16) & 0xff; + send_buf[4] = ((-spd[0])>>8) & 0xff; + send_buf[3] = ((-spd[0])) & 0xff; + CAN_senddata(0x401, send_buf); + osDelay(1); + + if( spd[1] > 0) + { + if( spd[1] < 200) + { + spd[1] = 200; + } + + } + else if( spd[1] < 0) + { + if( spd[1] > -200) + { + spd[1] = -200; + } + } + + send_buf[6] = (spd[1]>>24) & 0xff; + send_buf[5] = (spd[1]>>16) & 0xff; + send_buf[4] = (spd[1]>>8) & 0xff; + send_buf[3] = (spd[1]) & 0xff; + CAN_senddata(0x402, send_buf); + osDelay(1); + + send_buf[6] = (spd[2]>>24) & 0xff; + send_buf[5] = (spd[2]>>16) & 0xff; + send_buf[4] = (spd[2]>>8) & 0xff; + send_buf[3] = (spd[2]) & 0xff; + CAN_senddata(0x403, send_buf); + osDelay(1); + +// if( ) +// uint8_t send_buf[8]={0x23,0xff,0x60,0x00,0x00,0x00,0x00,0x00}; +// if((car_state.mot_sta & 0x08)) +// { +// send_buf[7] = ((-spd[0])>>24) & 0xff; +// send_buf[6] = ((-spd[0])>>16) & 0xff; +// send_buf[5] = ((-spd[0])>>8) & 0xff; +// send_buf[4] = ((-spd[0])) & 0xff; +// CAN_senddata(0x401, send_buf); +// osDelay(1); +// }else//ת +// { +// send_buf[0] = 0x2b; +// send_buf[1] = 0x40; +// send_buf[2] = 0x60; +// send_buf[3] = 0x00; +// send_buf[4] = 0x0f; +// send_buf[5] = 0x00; +// send_buf[6] = 0x00; +// send_buf[7] = 0x00; +// CAN_senddata(0x601, send_buf); +// osDelay(20); +// } +// if((car_state.mot_sta & 0x04)) +// { +// send_buf[7] = (spd[1]>>24) & 0xff; +// send_buf[6] = (spd[1]>>16) & 0xff; +// send_buf[5] = (spd[1]>>8) & 0xff; +// send_buf[4] = (spd[1]) & 0xff; +// CAN_senddata(0x602, send_buf); +// osDelay(1); +// }else//ת +// { +// send_buf[0] = 0x2b; +// send_buf[1] = 0x40; +// send_buf[2] = 0x60; +// send_buf[3] = 0x00; +// send_buf[4] = 0x0f; +// send_buf[5] = 0x00; +// send_buf[6] = 0x00; +// send_buf[7] = 0x00; +// CAN_senddata(0x602, send_buf); +// osDelay(20); +// } +// if((car_state.mot_sta & 0x02)) +// { +// send_buf[7] = (spd[2]>>24) & 0xff; +// send_buf[6] = (spd[2]>>16) & 0xff; +// send_buf[5] = (spd[2]>>8) & 0xff; +// send_buf[4] = (spd[2]) & 0xff; +// CAN_senddata(0x603, send_buf); +// osDelay(1); +// }else//ת +// { +// send_buf[0] = 0x2b; +// send_buf[1] = 0x40; +// send_buf[2] = 0x60; +// send_buf[3] = 0x00; +// send_buf[4] = 0x0f; +// send_buf[5] = 0x00; +// send_buf[6] = 0x00; +// send_buf[7] = 0x00; +// CAN_senddata(0x603, send_buf); +// osDelay(20); +// } +} + +void sm_start(uint8_t whc)// +{ +// if( ) + + uint8_t send_buf1[8]={0x2f,0x60,0x60,0x00,0x03,0x00,0x00,0x00};//ģʽΪٶģʽ + uint8_t send_buf2[8]={0x23,0xff,0x60,0x00,0x00,0x00,0x00,0x00};//ٶ0 + uint8_t send_buf3[8]={0x2b,0x40,0x60,0x00,0x0f,0x00,0x00,0x00};//ٶ + uint16_t timcnt =0; + + switch(whc) + { + case 1:// + CAN_senddata(0x601, send_buf1);//ٶģʽ + HAL_Delay(5); + CAN_senddata(0x601, send_buf2); //ٶ + HAL_Delay(5); + CAN_senddata(0x601, send_buf3); //ٶ + HAL_Delay(5); +// send_buf3[0] = 0x2b; +// send_buf3[1] = 0x17; +// send_buf3[2] = 0x10; +// send_buf3[3] = 0x00; +// send_buf3[4] = 0x28; +// send_buf3[5] = 0x00; +// send_buf3[6] = 0x00; +// send_buf3[7] = 0x00; +// CAN_senddata(0x601, send_buf3); //ٶ +// HAL_Delay(5); + + + break; + case 2:// + CAN_senddata(0x602, send_buf1);//ٶģʽ + HAL_Delay(5); + CAN_senddata(0x602, send_buf2); //ٶ + HAL_Delay(5); + CAN_senddata(0x602, send_buf3); //ٶ + HAL_Delay(5); + break; + case 3:// + + CAN_senddata(0x603, send_buf1);//ٶģʽ + HAL_Delay(5); + CAN_senddata(0x603, send_buf2); //ٶ + HAL_Delay(5); + CAN_senddata(0x603, send_buf3); //ٶ + HAL_Delay(5); + break; + case 4:// + if(g_upd()==1)//δ̨ûڶ + { + CAN_senddata(0x604, send_buf1);//ٶģʽ + HAL_Delay(5); + send_buf2[4]=0xC0; + send_buf2[5]=0xFF; + send_buf2[6]=0xFF; + send_buf2[7]=0xFF; + CAN_senddata(0x604, send_buf2); //ٶ + HAL_Delay(5); + CAN_senddata(0x604, send_buf3); //ٶ + while(g_upd()==1) + { + if(timcnt>5000) + { + //λر + break; + } + timcnt++; + HAL_Delay(1); + } + } + send_buf3[4] = 0x0f; + CAN_senddata(0x604, send_buf3);//+ѹ+ͣ+ + HAL_Delay(5); + send_buf1[4] = 0x01; + CAN_senddata(0x604, send_buf1);//λģʽ + HAL_Delay(5); + + send_buf2[0] = 0x40; + send_buf2[1] = 0x64; + send_buf2[2] = 0x60; + send_buf2[3] = 0x00; + send_buf2[4] = 0x00; + send_buf2[5] = 0x00; + send_buf2[6] = 0x00; + send_buf2[7] = 0x00; + CAN_senddata(0x604, send_buf2); //ȡλ + HAL_Delay(5); + send_buf3[4] = 0x2f; + CAN_senddata(0x604, send_buf3); //λÿģʽ+λִ + HAL_Delay(5); + break; + default: + break; + } + +} + +int gm_rpm(uint8_t whc)//ȡٶ +{ + uint8_t send_buf[8]={0x40,0x6c,0x60,0x00,0x00,0x00,0x00,0x00}; + CAN_senddata(0x600+whc, send_buf); +} + +int thro[2] ; +//·ֵתΪӵPWMֵ +void gm_pwm(int * tpwm,uint8_t * data) +{ + + thro[0] = 90 - data[1] ; //-90 - 90 + thro[1] = data[2] - 100; //-100 - 100 + + + tpwm[0] = (int)((thro[1] - thro[0])*10); + tpwm[1] = (int)((thro[1] + thro[0])*10); + + + car_state.c_ghigh = car_state.cmd_ghigh; + + if(car_state.s_cmd != 9) + { + if(car_state.c_gsw == 1)//ϲ㿪˸ + { + tpwm[2] = -2500; + }else if(car_state.c_gsw == 2)//ϲ㿪˸ + { + tpwm[2] = -3000; + }else + { + tpwm[2] = 0; + } + }else + { + tpwm[2] = 0; + } +} +//ֵ0-45Ϊõĸ߶ֵmm255Ϊȴʱ254ĿֵΧ + +void set_ghigh_task(void)//ø߶ +{ + //ǵĵ緢÷ʱ趨 + +} +void close_ghigh(void) +{ + uint8_t send_buf[8]={0x2f,0x01,0x26,0x00,0x00,0x00,0x00,0x00}; + CAN_senddata(0x604, send_buf); +} +void open_ghigh(void) +{ + uint8_t send_buf[8]={0x2f,0x01,0x26,0x00,0x01,0x00,0x00,0x00}; + CAN_senddata(0x604, send_buf); +} +void req_temp(uint8_t which) +{ + uint8_t send_buf[8]={0x40,0x12,0x26,0x00,0x01,0x00,0x00,0x00};//ģʽΪٶģʽ + CAN_senddata(0x600+which, send_buf); +} +// +// osDelay(1); +// if(spd[3] !=car_state.high_count) +// { +// send_buf[0] = 0x40; +// send_buf[1] = 0x64; +// send_buf[2] = 0x60; +// send_buf[3] = 0x00; +// CAN_senddata(0x604, send_buf); //ȡλ +// } + + + + + + + + + + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/nav/mot.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/nav/mot.h new file mode 100644 index 00000000..06594fa4 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/nav/mot.h @@ -0,0 +1,22 @@ + +#ifndef __MOT_H__ +#define __MOT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + + +void sm_run_spd(int *spd);//ٶ +void sm_start(uint8_t whc);// +void gm_pwm(int * tpwm,uint8_t * data);//PWMֵ +void set_ghigh_task(void);//ø߶ +void req_temp(uint8_t which);//¶ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/pga/common/inc/pga.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/pga/common/inc/pga.h new file mode 100644 index 00000000..4507a9f2 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/pga/common/inc/pga.h @@ -0,0 +1,81 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pga.h + * @author MCU Driver Team + * @brief Programmable Gain Apmlifier HAL level module driver head file. + * This file provides firmware functions to manage the following + * functionalities of the Amplifier. + * + Initialization and de-initialization functions + * + Programmable Gain Amplifier set gain value functions + */ +#ifndef McuMagicTag_PGA_H +#define McuMagicTag_PGA_H + +#include "pga_ip.h" +#include "baseinc.h" + +/** + * @defgroup PGA PGA + * @brief PGA module. + * @{ + */ + +/** + * @defgroup PGA_Common PGA Common + * @brief PGA common external module. + * @{ + */ + +/** + * @defgroup PGA_Handle_Definition PGA Handle Definition + * @{ + */ +/** + * @brief The define of the PGA handle structure + */ +typedef struct _PGA_Handle { + PGA_RegStruct *baseAddress; /**< PGA registers base address. */ + PGA_GainValue gain; /**< PGA gain selection. */ + bool externalResistorMode; /**< PGA resistance mode. */ + + PGA_ExtendHandle handleEx; /**< PGA handle extend. */ +} PGA_Handle; + +/** + * @} + */ + +/** + * @defgroup PGA_API_Declaration PGA HAL API + * @{ + */ +BASE_StatusType HAL_PGA_Init(PGA_Handle *pgaHandle); /* Initializet function */ +BASE_StatusType HAL_PGA_DeInit(PGA_Handle *pgaHandle); /* Deinitialize function */ +void HAL_PGA_SetGain(PGA_Handle *pgaHandle, PGA_GainValue gain); /* Set amplifier's gain function */ +void HAL_PGA_Start(PGA_Handle *pgaHandle); /* Start PGA */ +void HAL_PGA_Stop(PGA_Handle *pgaHandle); /* Stop PGA */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/pga/inc/pga_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/pga/inc/pga_ip.h new file mode 100644 index 00000000..1511da5f --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/pga/inc/pga_ip.h @@ -0,0 +1,352 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pga_ip.h + * @author MCU Driver Team + * @brief Programmable Gain Amplifier module driver. + * This file provides DCL functions to manage amplifier. + * + Programmable Gain Amplifier register mapping strtucture. + * + Direct configuration layer interface. + */ + +#ifndef McuMagicTag_PGA_IP_H +#define McuMagicTag_PGA_IP_H + +#include "baseinc.h" + +#ifdef PGA_PARAM_CHECK +#define PGA_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define PGA_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define PGA_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define PGA_ASSERT_PARAM(para) ((void)0U) +#define PGA_PARAM_CHECK_NO_RET(para) ((void)0U) +#define PGA_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +#define PGA_PGA_MAX_GAIN 7 +#define PGA_PAG_MAX_SMUX 7 +#define PGA_MAX_INPUT 8 +#define PGA_MAX_SWITCH 3 +/** + * @addtogroup PGA + * @{ + */ + +/** + * @defgroup PGA_IP PGA_IP + * @brief PGA_IP: pga_v0. + * @{ + */ + +/** + * @defgroup PGA_REG_Definition PGA Register Structure. + * @brief PGA Register Structure Definition. + * @{ + */ +/** + * @brief vin select + */ +typedef enum { + PGA_INTER_RES_VI0 = 0x00000000U, + PGA_INTER_RES_VI1 = 0x00000001U, + PGA_INTER_RES_VI2 = 0x00000002U, + PGA_INTER_RES_VI3 = 0x00000003U, + PGA_EXT_RES_VI0 = 0x00000004U, + PGA_EXT_RES_VI1 = 0x00000005U, + PGA_EXT_RES_VI2 = 0x00000006U, + PGA_EXT_RES_VI3 = 0x00000007U, +} PGA_VinMux; + +/** + * @brief PGA vin switch selection + */ +typedef enum { + PGA_SW_VIN0 = 0x00000001U, + PGA_SW_VIN1 = 0x00000002U, + PGA_SW_VIN2 = 0x00000004U, + PGA_SW_VIN3 = 0x00000008U, +} PGA_SW; + +/** + * @brief PGA gain value selection + */ +typedef enum { + PGA_GAIN_1X = 0x00000000U, + PGA_GAIN_2X = 0x00000001U, + PGA_GAIN_4X = 0x00000002U, + PGA_GAIN_8X = 0x00000003U, + PGA_GAIN_16X = 0x00000004U, +} PGA_GainValue; + +/** + * @brief Extent handle definition of PGA. + */ +typedef struct { + PGA_VinMux pgaMux; /**< PGA Input channel. */ +} PGA_ExtendHandle; + +/** + * @brief PGA control 0. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pga_ana_en : 1; /**< Overall enable of the PGA. */ + unsigned int pga_en_ext0 : 1; /**< PGA external output enable. */ + unsigned int pga_en_out : 1; /**< PGA output enable. */ + unsigned int reserved_0 : 29; + } BIT; +} volatile PGA_CTRL0_REG; + +/** + * @brief PGA control 1. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pga_trim_ofstp : 5; /**< PGA trim PMOS offset. */ + unsigned int pga_trim_ofstn : 5; /**< PGA trim NMOS offset. */ + unsigned int reserved_0 : 22; + } BIT; +} volatile PGA_CTRL1_REG; + +/** + * @brief PGA control 2. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pga_smux : 3; /**< PGA input channel select. */ + unsigned int pga_gain : 3; /**< PGA gain. */ + unsigned int reserved_0 : 26; + } BIT; +} volatile PGA_CTRL2_REG; + +/** + * @brief Controls PGA SW. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pga_sw_enlv_n : 4; /**< PGA N input SW enable, configured together with channel select. */ + unsigned int pga_sw_enlv_p : 4; /**< PGA P input SW enable, configured together with channel select. */ + unsigned int pga_ext_loopback : 2; /**< PGA loopback switch. */ + unsigned int reserved_0 : 22; + } BIT; +} volatile PGA_CTRL3_REG; + +/** + * @brief Register mapping structure. + */ +typedef struct _PGA_RegStruct { + PGA_CTRL0_REG PGA_CTRL0; /**< PGA control 0 register. Offset address: 0x00000000U. */ + PGA_CTRL1_REG PGA_CTRL1; /**< PGA control 1 register. Offset address: 0x00000004U. */ + PGA_CTRL2_REG PGA_CTRL2; /**< PGA control 2 register. Offset address: 0x00000008U. */ + PGA_CTRL3_REG PGA_CTRL3; /**< PGA SW control register. Offset address: 0x0000000CU. */ +} volatile PGA_RegStruct; + +/** + * @brief Enable amplifier's output + * @param pgax: amplifier register base address. + * @retval None. + */ +static inline void DCL_PGA_EnableOut(PGA_RegStruct *pgax) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + pgax->PGA_CTRL0.BIT.pga_en_out = BASE_CFG_ENABLE; +} + +/** + * @brief Disable amplifier's output + * @param pgax: amplifier register base address. + * @retval None. + */ +static inline void DCL_PGA_DisableOut(PGA_RegStruct *pgax) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + pgax->PGA_CTRL0.BIT.pga_en_out = BASE_CFG_DISABLE; +} + +/** + * @brief Enable amplifier's extra output + * @param pgax: amplifier register base address. + * @retval None. + */ +static inline void DCL_PGA_EnableExtOut(PGA_RegStruct *pgax) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + pgax->PGA_CTRL0.BIT.pga_en_ext0 = BASE_CFG_ENABLE; +} + +/** + * @brief Disable amplifier's extra output + * @param pgax: amplifier register base address. + * @retval None. + */ +static inline void DCL_PGA_DisableExtOut(PGA_RegStruct *pgax) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + pgax->PGA_CTRL0.BIT.pga_en_ext0 = BASE_CFG_DISABLE; +} + +/** + * @brief Enable amplifier module + * @param pgax: amplifier register base address. + * @retval None. + */ +static inline void DCL_PGA_EnableAnaOut(PGA_RegStruct *pgax) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + pgax->PGA_CTRL0.BIT.pga_ana_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable amplifier module + * @param pgax: amplifier register base address. + * @retval None. + */ +static inline void DCL_PGA_DisableAnaOut(PGA_RegStruct *pgax) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + pgax->PGA_CTRL0.BIT.pga_ana_en = BASE_CFG_DISABLE; +} + +/** + * @brief Set amplifier's gain + * @param pgax: amplifier register base address. + * @param value: gain value. + * @retval None. + */ +static inline void DCL_PGA_SetGain(PGA_RegStruct *pgax, unsigned int value) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + PGA_PARAM_CHECK_NO_RET(value <= PGA_PGA_MAX_GAIN); + pgax->PGA_CTRL2.BIT.pga_gain = value; +} + +/** + * @brief Get amplifier's gain + * @param pgax: amplifier register base address. + * @retval gain value. + */ +static inline unsigned int DCL_PGA_GetGain(PGA_RegStruct *pgax) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + return pgax->PGA_CTRL2.BIT.pga_gain; +} + +/** + * @brief Set amplifier mux + * @param pgax: amplifier register base address. + * @retval None. + */ +static inline void DCL_PGA_SetMux(PGA_RegStruct *pgax, unsigned int value) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + PGA_PARAM_CHECK_NO_RET(value <= PGA_PAG_MAX_SMUX); + pgax->PGA_CTRL2.BIT.pga_smux = value; +} + +/** + * @brief Get amplifier's Mux + * @param pgax: amplifier register base address. + * @retval None. + */ +static inline unsigned int DCL_PGA_GetMux(PGA_RegStruct *pgax) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + return pgax->PGA_CTRL2.BIT.pga_smux; +} + +/** + * @brief Set loopback switch P + * @param pgax: amplifier register base address. + * @param pgaNum: number of amplifier + * @retval None. + */ +static inline void DCL_PGA_EnablePInputByNum(PGA_RegStruct *pgax, unsigned int pgaNum) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + PGA_PARAM_CHECK_NO_RET(pgaNum < PGA_MAX_INPUT); + pgax->PGA_CTRL3.BIT.pga_sw_enlv_p |= pgaNum; +} + +/** + * @brief Unset loopback switch + * @param pgax: amplifier register base address. + * @param pgaNum: number of amplifier + * @retval None. + */ +static inline void DCL_PGA_DisablePInputByNum(PGA_RegStruct *pgax, unsigned int pgaNum) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + PGA_PARAM_CHECK_NO_RET(pgaNum < PGA_MAX_INPUT); + pgax->PGA_CTRL3.BIT.pga_sw_enlv_p &= ~pgaNum; +} + +/** + * @brief Set loopback switch N + * @param pgax: amplifier register base address. + * @param pgaNum: number of amplifier + * @retval None. + */ +static inline void DCL_PGA_EnableNInputByNum(PGA_RegStruct *pgax, unsigned int pgaNum) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + PGA_PARAM_CHECK_NO_RET(pgaNum < PGA_MAX_INPUT); + pgax->PGA_CTRL3.BIT.pga_sw_enlv_n |= pgaNum; +} + +/** + * @brief Unset loopback switch N + * @param pgax: amplifier register base address. + * @param pgaNum: number of amplifier + * @retval None. + */ +static inline void DCL_PGA_DisableNInputByNum(PGA_RegStruct *pgax, unsigned int pgaNum) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + PGA_PARAM_CHECK_NO_RET(pgaNum < PGA_MAX_INPUT); + pgax->PGA_CTRL3.BIT.pga_sw_enlv_n &= ~pgaNum; +} + +/** + * @brief Sets the PGA loopback switch. + Bit[8] controls channel 0 and bit[9] controls channel 3. + * @param pgax: amplifier register base address. + * @param switchNum: Loopback switch. + * @retval None. + */ +static inline void DCL_PGA_SetLoopBackSwitch(PGA_RegStruct *pgax, unsigned int switchNum) +{ + PGA_ASSERT_PARAM(IsPGAInstance(pgax)); + PGA_PARAM_CHECK_NO_RET(switchNum < PGA_MAX_SWITCH); + pgax->PGA_CTRL3.BIT.pga_ext_loopback = switchNum; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/pga/src/pga.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/pga/src/pga.c new file mode 100644 index 00000000..57774092 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/pga/src/pga.c @@ -0,0 +1,115 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pga.c + * @author MCU Driver Team. + * @brief Programmable Gain Amplifier HAL level module driver. + * This file provides firmware functions to manage the following + * functionalities of the amplifier + * + Programmable Gain Amplifier's Initialization and de-initialization functions + * + Set amplifier's gain value + */ +#include "pga.h" +#include "assert.h" + +#define PGA_OUT_CHANNEL_NUM 0x3 +#define PGA_SHIFT_NUMBER 0x3 +#define PGA_SHIFT_BITS 4 +#define PGA_OUT_ENABLE 0x4 +#define PGA_EXTOUT_ENABLE 0x2 + +/** + * @brief PGA HAL Init + * @param pgaHandle: PGA handle. + * @retval BASE_StatusType. + */ +BASE_StatusType HAL_PGA_Init(PGA_Handle *pgaHandle) +{ + PGA_ASSERT_PARAM(pgaHandle != NULL); + PGA_ASSERT_PARAM(IsPGAInstance(pgaHandle->baseAddress)); + PGA_PARAM_CHECK_WITH_RET(pgaHandle->gain <= PGA_PGA_MAX_GAIN, BASE_STATUS_ERROR); + PGA_PARAM_CHECK_WITH_RET(pgaHandle->handleEx.pgaMux <= PGA_PAG_MAX_SMUX, BASE_STATUS_ERROR); + pgaHandle->baseAddress->PGA_CTRL2.BIT.pga_gain = pgaHandle->gain; + /* PGA loopback switch, which needs to be enabled only when an external resistor is configured. */ + pgaHandle->baseAddress->PGA_CTRL3.BIT.pga_ext_loopback = pgaHandle->externalResistorMode; + /* PGA input and out setting. */ + pgaHandle->baseAddress->PGA_CTRL2.BIT.pga_smux = pgaHandle->handleEx.pgaMux; /* Output channel select. */ + /* PGA enable setting. */ + if (pgaHandle->handleEx.pgaMux > PGA_OUT_CHANNEL_NUM) { + pgaHandle->baseAddress->PGA_CTRL0.reg = PGA_EXTOUT_ENABLE; /* Enable external output of the PGA. */ + pgaHandle->baseAddress->PGA_CTRL3.BIT.pga_sw_enlv_p = 1 << (pgaHandle->handleEx.pgaMux - PGA_SHIFT_BITS); + pgaHandle->baseAddress->PGA_CTRL3.BIT.pga_sw_enlv_n = 1 << (pgaHandle->handleEx.pgaMux - PGA_SHIFT_BITS); + } else { + pgaHandle->baseAddress->PGA_CTRL0.reg = PGA_OUT_ENABLE; /* Enables the internal output of the PGA. */ + pgaHandle->baseAddress->PGA_CTRL3.BIT.pga_sw_enlv_p = 1 << pgaHandle->handleEx.pgaMux; + pgaHandle->baseAddress->PGA_CTRL3.BIT.pga_sw_enlv_n = 1 << pgaHandle->handleEx.pgaMux; + } + pgaHandle->baseAddress->PGA_CTRL0.BIT.pga_ana_en = BASE_CFG_SET; /* PGA enable */ + return BASE_STATUS_OK; +} + +/** + * @brief PGA HAL DeInit + * @param pgaHandle: PGA handle. + * @retval BASE_StatusType. + */ +BASE_StatusType HAL_PGA_DeInit(PGA_Handle *pgaHandle) +{ + PGA_ASSERT_PARAM(pgaHandle != NULL); + PGA_ASSERT_PARAM(IsPGAInstance(pgaHandle->baseAddress)); + pgaHandle->baseAddress->PGA_CTRL0.reg = BASE_CFG_DISABLE; /* Disable PGA. */ + pgaHandle->baseAddress->PGA_CTRL2.reg = BASE_CFG_DISABLE; /* Gain and channel deinitialization. */ + pgaHandle->baseAddress->PGA_CTRL3.reg = BASE_CFG_DISABLE; /* Deinitialize the loopback switch and SW switch. */ + return BASE_STATUS_OK; +} + +/** + * @brief Set Gain value + * @param pgaHandle: PGA handle. + * @param gain: gain value. @ref PGA_GainValue + * @retval None. + */ +void HAL_PGA_SetGain(PGA_Handle *pgaHandle, PGA_GainValue gain) +{ + PGA_ASSERT_PARAM(pgaHandle != NULL); + PGA_ASSERT_PARAM(IsPGAInstance(pgaHandle->baseAddress)); + pgaHandle->baseAddress->PGA_CTRL2.BIT.pga_gain = gain; +} + +/** + * @brief Start PGA + * @param pgaHandle: PGA handle. + * @retval None + */ +void HAL_PGA_Start(PGA_Handle *pgaHandle) +{ + PGA_ASSERT_PARAM(pgaHandle != NULL); + PGA_ASSERT_PARAM(IsPGAInstance(pgaHandle->baseAddress)); + pgaHandle->baseAddress->PGA_CTRL0.BIT.pga_ana_en = BASE_CFG_SET; /* Enable PGA. */ +} + +/** + * @brief Stop PGA + * @param pgaHandle: PGA handle. + * @retval None + */ +void HAL_PGA_Stop(PGA_Handle *pgaHandle) +{ + PGA_ASSERT_PARAM(pgaHandle != NULL); + PGA_ASSERT_PARAM(IsPGAInstance(pgaHandle->baseAddress)); + pgaHandle->baseAddress->PGA_CTRL0.BIT.pga_ana_en = BASE_CFG_DISABLE; /* Overall disable of the PGA. */ +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/pmc/common/inc/pmc.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/pmc/common/inc/pmc.h new file mode 100644 index 00000000..d05b6635 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/pmc/common/inc/pmc.h @@ -0,0 +1,96 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pmc.h + * @author MCU Driver Team. + * @brief PMC module driver. + * This file provides functions declaration of PMC. + * + PMC's initialization and de-initialization functions. + * + Interface declaration of enter sleep, deepsleep and shutdowm mode. + * + PMC's register callback function. + */ + +#ifndef __McuMagicTag_PMC_H__ +#define __McuMagicTag_PMC_H__ +#include "pmc_ip.h" + +/** + * @defgroup PMC PMC + * @brief PMC module. + * @{ + */ + +/** + * @defgroup PMC_Common PMC Common + * @brief PMC common external module. + * @{ + */ + + +/** + * @defgroup PMC_Common_Param PMC Common Parameters + * @{ + */ + +/** + * @brief Definition of callback function type + */ +typedef void (* PMC_CallbackType)(void *pmcHandle); + +/** + * @brief PMC Handle + */ +typedef struct _PMC_Handle { + PMC_RegStruct *baseAddress; /**< Register base address. */ + PMC_LowpowerWakeupSrc wakeupSrc; /**< Wakeup source of deep sleep. */ + PMC_ActMode wakeupActMode; /**< Wakeup pin level mode of PMC module. */ + unsigned int wakeupTime; /**< Wakeup time of deep sleep. */ + bool pvdEnable; /**< PVD function enable. */ + PMC_PvdThreshold pvdThreshold; /**< PVD threshold voltage level. */ + PMC_UserCallBack userCallBack; /**< User-defined callback function. */ + PMC_ExtendHandle handleEx; /**< Extend handle, configuring some special parameters. */ +} PMC_Handle; + +/** + * @} + */ + +/** + * @defgroup PMC_API_Declaration PMC HAL API + * @{ + */ +void HAL_PMC_Init(PMC_Handle *handle); +void HAL_PMC_DeInit(PMC_Handle *handle); +void HAL_PMC_EnterSleepMode(void); +void HAL_PMC_EnterDeepSleepMode(PMC_Handle *handle); +void HAL_PMC_EnterShutdownMode(PMC_Handle *handle); +PMC_LowpowerType HAL_PMC_GetWakeupType(PMC_Handle *handle); +void HAL_PMC_RegisterCallback(PMC_Handle *handle, PMC_CallBackID callbackID, PMC_CallbackType pCallback); +void HAL_PMC_IrqHandler(void *handle); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/pmc/inc/pmc_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/pmc/inc/pmc_ip.h new file mode 100644 index 00000000..b137fd73 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/pmc/inc/pmc_ip.h @@ -0,0 +1,734 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pmc_ip.h + * @author MCU Driver Team + * @brief Header file containing PMC module DCL driver functions. + * This file provides functions to manage the following functionalities of PMC module. + * + Definition of PMC configuration parameters. + * + PMC registers mapping structures. + * + Direct Configuration Layer driver functions. + */ +#ifndef McuMagicTag_PMC_IP_H +#define McuMagicTag_PMC_IP_H + +#include "baseinc.h" + +#ifdef PMC_PARAM_CHECK +#define PMC_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define PMC_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define PMC_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define PMC_ASSERT_PARAM(para) ((void)0U) +#define PMC_PARAM_CHECK_NO_RET(para) ((void)0U) +#define PMC_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +#define PMC_WAKEUP_SRC_MARSK 0x3F + +/** + * @addtogroup PMC + * @{ + */ + +/** + * @defgroup PMC_IP PMC_IP + * @brief PMC_IP: pmc_v0. + * @{ + */ + +/** + * @defgroup PMC_Param_Def PMC Parameters Definition + * @brief Definition of PMC configuration parameters + * @{ + */ + + +/** + * @brief wakeup pin level mode of PMC module. + * @details status flag: + * + PMC_WAKEUP_ACT_UP_EDGE -- Wakeup valid in up edge + * + PMC_WAKEUP_ACT_DOWN_EDGE -- Wakeup valid in down edge + * + PMC_WAKEUP_ACT_HIGH_LEVEL -- Wakeup valid in high edge + * + PMC_WAKEUP_ACT_LOW_LEVEL -- Wakeup valid in low edge + */ +typedef enum { + PMC_WAKEUP_ACT_UP_EDGE = 0x00000000U, + PMC_WAKEUP_ACT_DOWN_EDGE = 0x00000001U, + PMC_WAKEUP_ACT_HIGH_LEVEL = 0x00000002U, + PMC_WAKEUP_ACT_LOW_LEVEL = 0x00000003U, +} PMC_ActMode; + +/** + * @brief Wakeup source of deep sleep. + * @details status flag: + * + PMC_WAKEUP_0 -- Wakeup from DS_WAKEUP0. + * + PMC_WAKEUP_1 -- Wakeup from DS_WAKEUP1. + * + PMC_WAKEUP_2 -- Wakeup from DS_WAKEUP2. + * + PMC_WAKEUP_3 -- Wakeup from DS_WAKEUP3. + * + PMC_WAKEUP_CNT -- Wakeup from timer. + * + PMC_WAKEUP_NONE --No Wakeup source. + */ +typedef enum { + PMC_WAKEUP_0 = 0x00000000U, + PMC_WAKEUP_1 = 0x00000001U, + PMC_WAKEUP_2 = 0x00000002U, + PMC_WAKEUP_3 = 0x00000003U, + PMC_WAKEUP_CNT = 0x00000004U, + PMC_WAKEUP_NONE = 0x00000005U, +} PMC_LowpowerWakeupSrc; + +/** + * @brief Lowpower type. + * @details status flag: + * + PMC_LP_NONE -- Non-lowpower mode. + * + PMC_LP_DEEPSLEEP -- Deepsleep mode. + * + PMC_LP_SHUTDOWN -- Shutdown mode. + */ +typedef enum { + PMC_LP_NONE = 0x00000000U, + PMC_LP_DEEPSLEEP = 0x00000001U, + PMC_LP_SHUTDOWN = 0x00000002U, +} PMC_LowpowerType; + +/** + * @brief Callback Triggering Event Enumeration Definition + */ +typedef enum { + PMC_PVD_INT_ID = 0x00, +} PMC_CallBackID; + +/** + * @brief PMC PVD threshold voltage level. + * @details status flag: + * + PMC_PVD_THRED_LEVEL2 -- rising edge 2.38V, falling edge 2.28V. + * + PMC_PVD_THRED_LEVEL3 -- rising edge 2.48V, falling edge 2.38V. + * + PMC_PVD_THRED_LEVEL4 -- rising edge 2.58V, falling edge 2.48V. + * + PMC_PVD_THRED_LEVEL5 -- rising edge 2.68V, falling edge 2.58V. + * + PMC_PVD_THRED_LEVEL6 -- rising edge 2.78V, falling edge 2.68V. + * + PMC_PVD_THRED_LEVEL7 -- rising edge 2.88V, falling edge 2.78V. + */ +typedef enum { + PMC_PVD_THRED_LEVEL2 = 0x00000002U, + PMC_PVD_THRED_LEVEL3 = 0x00000003U, + PMC_PVD_THRED_LEVEL4 = 0x00000004U, + PMC_PVD_THRED_LEVEL5 = 0x00000005U, + PMC_PVD_THRED_LEVEL6 = 0x00000006U, + PMC_PVD_THRED_LEVEL7 = 0x00000007U, +} PMC_PvdThreshold; + +/** + * @brief PMC extend handle, configuring some special parameters. + */ +typedef struct { +} PMC_ExtendHandle; + +/** + * @brief User-defined callback function. + */ +typedef struct { + /** Event callback function of the flash module */ + void (*PmcCallBack)(void *handle); +} PMC_UserCallBack; + +/** + * @} + */ + +/** + * @defgroup PMC_REG_Definition PMC Register Structure. + * @brief PMC Register Structure Definition. + * @{ + */ + +/** + * @brief Low-power mode control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int shutdown_req : 1; /**< Indicates the request for the system to enter the shutdown mode. */ + unsigned int reserved_0 : 3; + unsigned int deepsleep_req : 1; /**< The system enters the deepsleep mode. */ + unsigned int reserved_1 : 27; + } BIT; +} volatile PMC_LOWPOWER_MODE; + +/** + * @brief Wakeup control register in deepsleep mode. + */ +typedef union { + unsigned int reg; + struct { + unsigned int wakeup0_act_mode : 2; /**< Valid mode select of WakeUP0. */ + unsigned int wakeup1_act_mode : 2; /**< Validity mode select of wakeup1. */ + unsigned int wakeup2_act_mode : 2; /**< Valid mode select of WakeUP2. */ + unsigned int wakeup3_act_mode : 2; /**< Validity mode select of wakeup3. */ + unsigned int wakeup0_en : 1; /**< Wakeup0 enable. */ + unsigned int wakeup1_en : 1; /**< Wakeup1 enable. */ + unsigned int wakeup2_en : 1; /**< Wakeup2 enable. */ + unsigned int wakeup3_en : 1; /**< Wakeup3 enable. */ + unsigned int reserved_0 : 4; + unsigned int cnt32k_wakeup_en : 1; /**< Scheduled wakeup enable. */ + unsigned int reserved_1 : 15; + } BIT; +} volatile PMC_WAKEUP_CTRL; + +/** + * @brief Low-power status query register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int wakeup_src_lock : 6; /**< Starts the wakeup source query. */ + unsigned int reserved_0 : 2; + unsigned int starup_from_shutdown : 1; /**< Indicates whether to start from the shutdown state. */ + unsigned int starup_from_deepsleep : 1; /**< Start from the deepsleep state. */ + unsigned int reserved_1 : 2; + unsigned int wakeup0_status : 1; /**< Wakeup0 wakeup source status. */ + unsigned int wakeup1_status : 1; /**< Wakeup1 wakeup source status. */ + unsigned int wakeup2_status : 1; /**< Wakeup2 wakeup source status. */ + unsigned int wakeup3_status : 1; /**< wakeup3: wakeup source status. */ + unsigned int reserved_2 : 8; + unsigned int cldo_po_cnt : 8; /**< Indicates the cldo power-on time statistics. */ + } BIT; +} volatile PMC_LOWPOWER_STATUS; + +/** + * @brief Core domain POR reset duration configuration register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int core_por_dly : 3; /**< Power-on reset duration of the core domain(ms). */ + unsigned int reserved_0 : 29; + } BIT; +} volatile PMC_CORE_POR_CTRL; + +/** + * @brief PVD control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pvd_en : 1; /**< PVD enable. */ + unsigned int reserved_0 : 3; + unsigned int pvd_lv : 3; /**< PVD voltage threshold. */ + unsigned int reserved_1 : 24; + unsigned int pvd_int : 1; /**< PVD interrupt status. */ + } BIT; +} volatile PMC_PVD_CTRL; + +/** + * @brief PMU CLDO voltage control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved_0 : 16; + unsigned int pmu_cldo_trim : 4; /**< PMU CLDO calibration value. */ + unsigned int reserved_1 : 12; + } BIT; +} volatile PMC_PMU_CLDO; + +/** + * @brief PMC registers definition structure. + */ +typedef struct { + unsigned int reserved_0[128]; + PMC_LOWPOWER_MODE LOWPOWER_MODE; /**< Low-power mode control register. Offset address: 0x00000200U. */ + unsigned int CNT32K_WAKE_CYC; /**< Timed wakeup period config reg. Offset address: 0x00000204U. */ + PMC_WAKEUP_CTRL WAKEUP_CTRL; /**< Wakeup control register in deepsleep mode. Offset address: 0x00000208U. */ + PMC_LOWPOWER_STATUS LOWPOWER_STATUS; /**< Low-power status query register. Offset address: 0x0000020CU. */ + PMC_CORE_POR_CTRL CORE_POR_CTRL; /**< Core domain POR reset duration config reg. Offset address: 0x00000210U. */ + unsigned int reserved_1[507]; + PMC_PVD_CTRL PVD_CTRL; /**< PVD control register. Offset address: 0x00000A00U. */ + unsigned int reserved_2[2]; + PMC_PMU_CLDO PMU_CLDO; /**< PMU CLDO voltage control register. Offset address: 0x00000A0CU. */ + unsigned int reserved_3[316]; + unsigned int AON_USER_REG0; /**< AON domain user register 0. Offset address: 0x00000F00U. */ + unsigned int AON_USER_REG1; /**< AON domain user register 1. Offset address: 0x00000F04U. */ + unsigned int AON_USER_REG2; /**< AON domain user register 2. Offset address: 0x00000F08U. */ + unsigned int AON_USER_REG3; /**< AON domain user register 3. Offset address: 0x00000F0CU. */ +} volatile PMC_RegStruct; + +/** + * @brief Enter sleep mode interface. + * @param None. + * @retval None. + */ +static inline void DCL_PMC_EnterSleep(void) +{ +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + /* If user mode is supported, make sure to execute WFI + commands in machine mode */ + static unsigned int priv = RISCV_U_MODE; + RISCV_PRIV_MODE_SWITCH(priv); + __asm("wfi"); + RISCV_PRIV_MODE_SWITCH(priv); +#else + /* Only machine mode, no need for mode switching */ + __asm("wfi"); +#endif +} + +/** + * @brief Enter deepsleep mode interface. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_EnterDeepSleep(PMC_RegStruct * const pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->LOWPOWER_MODE.BIT.deepsleep_req = BASE_CFG_ENABLE; +} + +/** + * @brief Quit deepsleep mode interface. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_QuitDeepSleep(PMC_RegStruct * const pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->LOWPOWER_MODE.BIT.deepsleep_req = BASE_CFG_DISABLE; +} + +/** + * @brief Enter shutdown mode interface. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_EnterShutDown(PMC_RegStruct * const pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->LOWPOWER_MODE.BIT.shutdown_req = BASE_CFG_ENABLE; +} + +/** + * @brief Quit shutdown mode interface. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_QuitShutDown(PMC_RegStruct * const pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->LOWPOWER_MODE.BIT.shutdown_req = BASE_CFG_DISABLE; +} + +/** + * @brief Setting wakeup timer cycle. + * @param pmcx PMC register base address. + * @param cycle Timer cycle value. + * @retval None. + */ +static inline void DCL_PMC_SetFixTimeWakeupTimer(PMC_RegStruct * const pmcx, unsigned int cycle) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->CNT32K_WAKE_CYC = cycle; +} + +/** + * @brief Enable wakeup from timer. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_FixTimeWakeupEnable(PMC_RegStruct * const pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->WAKEUP_CTRL.BIT.cnt32k_wakeup_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable wakeup from timer. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_FixTimeWakeupDisable(PMC_RegStruct * const pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->WAKEUP_CTRL.BIT.cnt32k_wakeup_en = BASE_CFG_DISABLE; +} + +/** + * @brief Enable wakeup from WAKEUP0. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_Wakeup0Enable(PMC_RegStruct * const pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->WAKEUP_CTRL.BIT.wakeup0_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable wakeup from WAKEUP0. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_Wakeup0Disable(PMC_RegStruct * const pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->WAKEUP_CTRL.BIT.wakeup0_en = BASE_CFG_DISABLE; +} + +/** + * @brief Enable wakeup from WAKEUP1. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_Wakeup1Enable(PMC_RegStruct * const pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->WAKEUP_CTRL.BIT.wakeup1_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable wakeup from WAKEUP1. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_Wakeup1Disable(PMC_RegStruct * const pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->WAKEUP_CTRL.BIT.wakeup1_en = BASE_CFG_DISABLE; +} + +/** + * @brief Enable wakeup from WAKEUP2. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_Wakeup2Enable(PMC_RegStruct * const pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->WAKEUP_CTRL.BIT.wakeup2_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable wakeup from WAKEUP2. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_Wakeup2Disable(PMC_RegStruct * const pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->WAKEUP_CTRL.BIT.wakeup2_en = BASE_CFG_DISABLE; +} + +/** + * @brief Enable wakeup from WAKEUP3. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_Wakeup3Enable(PMC_RegStruct * const pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->WAKEUP_CTRL.BIT.wakeup3_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable wakeup from WAKEUP3. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_Wakeup3Disable(PMC_RegStruct * const pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->WAKEUP_CTRL.BIT.wakeup3_en = BASE_CFG_DISABLE; +} + +/** + * @brief Setting WAKEUP0 active level mode. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_SetWakeup0ActiveMode(PMC_RegStruct * const pmcx, PMC_ActMode mode) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + PMC_PARAM_CHECK_NO_RET(mode <= PMC_WAKEUP_ACT_LOW_LEVEL); + pmcx->WAKEUP_CTRL.BIT.wakeup0_act_mode = ((unsigned int)mode & 0x3); +} + +/** + * @brief Setting WAKEUP1 active level mode. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_SetWakeup1ActiveMode(PMC_RegStruct * const pmcx, PMC_ActMode mode) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + PMC_PARAM_CHECK_NO_RET(mode <= PMC_WAKEUP_ACT_LOW_LEVEL); + pmcx->WAKEUP_CTRL.BIT.wakeup1_act_mode = ((unsigned int)mode & 0x3); +} + +/** + * @brief Setting WAKEUP2 active level mode. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_SetWakeup2ActiveMode(PMC_RegStruct * const pmcx, PMC_ActMode mode) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + PMC_PARAM_CHECK_NO_RET(mode <= PMC_WAKEUP_ACT_LOW_LEVEL); + pmcx->WAKEUP_CTRL.BIT.wakeup2_act_mode = ((unsigned int)mode & 0x3); +} + +/** + * @brief Setting WAKEUP3 active level mode. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_SetWakeup3ActiveMode(PMC_RegStruct * const pmcx, PMC_ActMode mode) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + PMC_PARAM_CHECK_NO_RET(mode <= PMC_WAKEUP_ACT_LOW_LEVEL); + pmcx->WAKEUP_CTRL.BIT.wakeup3_act_mode = ((unsigned int)mode & 0x3); +} + +/** + * @brief Getting WAKEUP0 status. + * @param pmcx PMC register base address. + * @retval Wakeup status. + */ +static inline bool DCL_PMC_GetWakeup0Status(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->LOWPOWER_STATUS.BIT.wakeup0_status); +} + +/** + * @brief Getting WAKEUP1 status. + * @param pmcx PMC register base address. + * @retval Wakeup status. + */ +static inline bool DCL_PMC_GetWakeup1Status(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->LOWPOWER_STATUS.BIT.wakeup1_status); +} + +/** + * @brief Getting WAKEUP2 status. + * @param pmcx PMC register base address. + * @retval Wakeup status. + */ +static inline bool DCL_PMC_GetWakeup2Status(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->LOWPOWER_STATUS.BIT.wakeup2_status); +} + +/** + * @brief Getting WAKEUP3 status. + * @param pmcx PMC register base address. + * @retval Wakeup status. + */ +static inline bool DCL_PMC_GetWakeup3Status(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->LOWPOWER_STATUS.BIT.wakeup3_status); +} + +/** + * @brief Getting flag of wakeup from deepsleep mode. + * @param pmcx PMC register base address. + * @retval flag of wakeup from deepsleep mode. + */ +static inline bool DCL_PMC_GetStartupFromDeepSleepFlag(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->LOWPOWER_STATUS.BIT.starup_from_deepsleep); +} + +/** + * @brief Getting flag of wakeup from shutdown mode. + * @param pmcx PMC register base address. + * @retval flag of wakeup from shutdown mode. + */ +static inline bool DCL_PMC_GetStartupFromShutDownFlag(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->LOWPOWER_STATUS.BIT.starup_from_shutdown); +} + +/** + * @brief Getting wakeup source. + * @param pmcx PMC register base address. + * @retval source of wakeup. + */ +static inline unsigned int DCL_PMC_GetWakeupSrc(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->LOWPOWER_STATUS.BIT.wakeup_src_lock & PMC_WAKEUP_SRC_MARSK); +} + +/** + * @brief Getting CLDO power-on time. + * @param pmcx PMC register base address. + * @retval time of CLDO power-on. + */ +static inline unsigned int DCL_PMC_GetCldoPowerOnTime(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->LOWPOWER_STATUS.BIT.cldo_po_cnt); +} + +/** + * @brief Setting always on user's register 0. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_SetAlwaysOnUserReg0(PMC_RegStruct * const pmcx, unsigned int value) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->AON_USER_REG0 = value; +} + +/** + * @brief Getting always on user's register 0. + * @param pmcx PMC register base address. + * @retval Register0's value. + */ +static inline unsigned int DCL_PMC_GetAlwaysOnUserReg0(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->AON_USER_REG0); +} + +/** + * @brief Setting always on user's register 1. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_SetAlwaysOnUserReg1(PMC_RegStruct * const pmcx, unsigned int value) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->AON_USER_REG1 = value; +} + +/** + * @brief Getting always on user's register 1. + * @param pmcx PMC register base address. + * @retval Register1's value. + */ +static inline unsigned int DCL_PMC_GetAlwaysOnUserReg1(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->AON_USER_REG1); +} + +/** + * @brief Setting always on user's register 2. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_SetAlwaysOnUserReg2(PMC_RegStruct * const pmcx, unsigned int value) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->AON_USER_REG2 = value; +} + +/** + * @brief Getting always on user's register 2. + * @param pmcx PMC register base address. + * @retval Register2's value. + */ +static inline unsigned int DCL_PMC_GetAlwaysOnUserReg2(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->AON_USER_REG2); +} + +/** + * @brief Setting always on user's register 3. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_SetAlwaysOnUserReg3(PMC_RegStruct * const pmcx, unsigned int value) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->AON_USER_REG3 = value; +} + +/** + * @brief Getting always on user's register 3. + * @param pmcx PMC register base address. + * @retval Register3's value. + */ +static inline unsigned int DCL_PMC_GetAlwaysOnUserReg3(const PMC_RegStruct *pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + return (pmcx->AON_USER_REG3); +} + +/** + * @brief Enable PVD function. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_EnablePvd(PMC_RegStruct * const pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->PVD_CTRL.BIT.pvd_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable PVD function. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_DisablePvd(PMC_RegStruct * const pmcx) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->PVD_CTRL.BIT.pvd_en = BASE_CFG_DISABLE; +} + +/** + * @brief Set PVD threshold function. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_SetPvdThreshold(PMC_RegStruct * const pmcx, PMC_PvdThreshold threshold) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->PVD_CTRL.BIT.pvd_lv = threshold; +} + +/** + * @brief Set Core poweron reset delay value, delay by ms. + * @param pmcx PMC register base address. + * @retval None. + */ +static inline void DCL_PMC_SetCorePorDelay(PMC_RegStruct * const pmcx, unsigned char delayValue) +{ + PMC_ASSERT_PARAM(IsPMCInstance(pmcx)); + pmcx->CORE_POR_CTRL.BIT.core_por_dly = (delayValue & 0x7); /* 0x7: delay value valid mask */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_PMC_IP_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/pmc/src/pmc.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/pmc/src/pmc.c new file mode 100644 index 00000000..6d59c73d --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/pmc/src/pmc.c @@ -0,0 +1,195 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pmc.c + * @author MCU Driver Team. + * @brief ACMP HAL level module driver. + * This file provides firmware functions to manage the following + * functionalities of the DAC and Comparator. + * + PMC's initialization and de-initialization functions. + * + Enter sleep, deepsleep and shutdowm mode functions. + */ + +#include "pmc_ip.h" +#include "pmc.h" + +#define WAKEUP_ENABLE_OFFSET 0x8 +#define WAKE_ACT_MODE_REG_WIDTH 0x2 + +/** + * @brief Setting deepsleep wakeup source. + * @param pmcHandle: PMC handle. + * @retval None. + */ +static void PMC_SetDeepSleepWakeupSrc(PMC_Handle *pmcHandle) +{ + PMC_ASSERT_PARAM(pmcHandle != NULL); + PMC_ASSERT_PARAM(IsPMCInstance(pmcHandle->baseAddress)); + if (pmcHandle->wakeupSrc == PMC_WAKEUP_NONE) { /* No wakeup source. */ + return; + } + if (pmcHandle->wakeupSrc == PMC_WAKEUP_CNT) { + pmcHandle->baseAddress->CNT32K_WAKE_CYC = pmcHandle->wakeupTime; /* Set wakeup time */ + pmcHandle->baseAddress->WAKEUP_CTRL.BIT.cnt32k_wakeup_en = BASE_CFG_ENABLE; /* Enable wakeup from timer */ + } else { + pmcHandle->baseAddress->WAKEUP_CTRL.reg |= (pmcHandle->wakeupActMode) \ + << (pmcHandle->wakeupSrc * WAKE_ACT_MODE_REG_WIDTH); + pmcHandle->baseAddress->WAKEUP_CTRL.reg |= ((0x1 << pmcHandle->wakeupSrc) << WAKEUP_ENABLE_OFFSET); + } +} + +/** + * @brief Init PVD function. + * @param pmcHandle: PMC handle. + * @retval None. + */ +static void PMC_PvdInit(PMC_Handle *pmcHandle) +{ + PMC_ASSERT_PARAM(pmcHandle != NULL); + PMC_ASSERT_PARAM(IsPMCInstance(pmcHandle->baseAddress)); + PMC_PARAM_CHECK_NO_RET(pmcHandle->pvdThreshold >= PMC_PVD_THRED_LEVEL2); + PMC_PARAM_CHECK_NO_RET(pmcHandle->pvdThreshold <= PMC_PVD_THRED_LEVEL7); + if (pmcHandle->pvdEnable == BASE_CFG_ENABLE) { /* if PVD function is enable */ + pmcHandle->baseAddress->PVD_CTRL.BIT.pvd_en = BASE_CFG_ENABLE; + pmcHandle->baseAddress->PVD_CTRL.BIT.pvd_lv = pmcHandle->pvdThreshold; /* set PVD threshold voltage */ + } else { + pmcHandle->baseAddress->PVD_CTRL.BIT.pvd_en = BASE_CFG_DISABLE; + } +} + +/** + * @brief PMC initialize interface. + * @param handle: PMC handle. + * @retval None. + */ +void HAL_PMC_Init(PMC_Handle *handle) +{ + PMC_ASSERT_PARAM(handle != NULL); + PMC_ASSERT_PARAM(IsPMCInstance(handle->baseAddress)); + PMC_PvdInit(handle); + PMC_SetDeepSleepWakeupSrc(handle); +} + +/** + * @brief PMC deinitialize interface. + * @param handle: PMC handle. + * @retval None. + */ +void HAL_PMC_DeInit(PMC_Handle *handle) +{ + PMC_ASSERT_PARAM(handle != NULL); + PMC_ASSERT_PARAM(IsPMCInstance(handle->baseAddress)); + handle->pvdEnable = BASE_CFG_DISABLE; /* Disable PVD function. */ + handle->baseAddress->PVD_CTRL.BIT.pvd_en = BASE_CFG_DISABLE; + handle->baseAddress->WAKEUP_CTRL.reg = BASE_CFG_DISABLE; /* Disable all wakeup source. */ + handle->userCallBack.PmcCallBack = NULL; /* Clean interrupt callback functions. */ +} + +/** + * @brief Enter sleep interface. + * @param None. + * @retval None. + */ +void HAL_PMC_EnterSleepMode(void) +{ +#if defined(USER_MODE_ENABLE) && (USER_MODE_ENABLE == 1) + /* If user mode is supported, make sure to execute WFI + commands in machine mode */ + static unsigned int priv = RISCV_U_MODE; + RISCV_PRIV_MODE_SWITCH(priv); + __asm("wfi"); + RISCV_PRIV_MODE_SWITCH(priv); +#else + __asm("wfi"); +#endif +} + +/** + * @brief Enter deep sleep interface. + * @param handle: PMC handle. + * @retval None. + */ +void HAL_PMC_EnterDeepSleepMode(PMC_Handle *handle) +{ + PMC_ASSERT_PARAM(handle != NULL); + PMC_ASSERT_PARAM(IsPMCInstance(handle->baseAddress)); + handle->baseAddress->LOWPOWER_MODE.BIT.deepsleep_req = BASE_CFG_ENABLE; +} + +/** + * @brief Enter shutdown interface. + * @param handle: PMC handle. + * @retval None. + */ +void HAL_PMC_EnterShutdownMode(PMC_Handle *handle) +{ + PMC_ASSERT_PARAM(handle != NULL); + PMC_ASSERT_PARAM(IsPMCInstance(handle->baseAddress)); + handle->baseAddress->LOWPOWER_MODE.BIT.shutdown_req = BASE_CFG_ENABLE; +} + +/** + * @brief Get wakeup source type. + * @param handle: PMC handle. + * @retval Lowpower type. + */ +PMC_LowpowerType HAL_PMC_GetWakeupType(PMC_Handle *handle) +{ + PMC_LowpowerType wakeupMode; + bool deepsleepFlag = BASE_CFG_UNSET; + bool shutdownFlag = BASE_CFG_UNSET; + deepsleepFlag = handle->baseAddress->LOWPOWER_STATUS.BIT.starup_from_deepsleep; + shutdownFlag = handle->baseAddress->LOWPOWER_STATUS.BIT.starup_from_shutdown; + if (deepsleepFlag == BASE_CFG_SET) { /* If deepsleep flag is set */ + wakeupMode = PMC_LP_DEEPSLEEP; + } else if (shutdownFlag == BASE_CFG_SET) { /* If shutdown flag is set */ + wakeupMode = PMC_LP_SHUTDOWN; + } else { + wakeupMode = PMC_LP_NONE; + } + return wakeupMode; +} + +/** + * @brief Interrupt handler function. + * @param handle PMC module handle. + * @retval None. + */ +void HAL_PMC_IrqHandler(void *handle) +{ + PMC_ASSERT_PARAM(handle != NULL); + PMC_Handle *pmcHandle = (PMC_Handle *)handle; + if (pmcHandle->baseAddress->PVD_CTRL.BIT.pvd_int == 1) { /* PVD interrupt */ + if (pmcHandle->userCallBack.PmcCallBack != NULL) { + pmcHandle->userCallBack.PmcCallBack(pmcHandle); /* execute user's callback */ + } + } +} + +/** + * @brief Interrupt callback functions registration interface. + * @param handle PMC module handle. + * @param callbackID base callback id + * @param pCallback Pointer for the user callback function. + * @retval None. + */ +void HAL_PMC_RegisterCallback(PMC_Handle *handle, PMC_CallBackID callbackID, PMC_CallbackType pCallback) +{ + PMC_ASSERT_PARAM(handle != NULL); + BASE_FUNC_UNUSED(callbackID); + handle->userCallBack.PmcCallBack = pCallback; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/qdm/common/inc/qdm.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/qdm/common/inc/qdm.h new file mode 100644 index 00000000..b890338e --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/qdm/common/inc/qdm.h @@ -0,0 +1,156 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file qdm.h + * @author MCU Driver Team + * @brief QDM HAL level module driver head file. + * @details This file provides firmware functions to manage the following + * functionalities of the QDM. + * + Initialization and de-initialization functions. + * + Capm Module Control functions. + * + Speed measure use M function. + * + Stall condition detection. + */ +#ifndef McuMagicTag_QDM_H +#define McuMagicTag_QDM_H + +#include "typedefs.h" +#include "qdm_ip.h" + +#define SECONDS_PER_MINUTES 60 + +/** + * @defgroup QDM QDM + * @brief QDM module. + * @{ + */ + +/** + * @defgroup QDM_Common QDM Common + * @brief QDM common external module. + * @{ + */ + + +/** + * @defgroup QDM_Common_Param QDM Common Parameters + * @{ + */ + +/** + * @brief QDM callback function type + */ +typedef enum { + QDM_TSU_CYCLE = 0x00000000U, + QDM_SPEED_LOSE = 0x00000001U, + QDM_INDEX_LOCKED = 0x00000002U, + QDM_DIR_CHANGE = 0x00000003U, + QDM_PHASE_ERROR = 0x00000004U, + QDM_POS_MATCH = 0x00000005U, + QDM_POS_READY = 0x00000006U, + QDM_POS_CNT_ERROR = 0x00000007U, + QDM_POS_CNT_OVERFLOW = 0x00000008U, + QDM_POS_CNT_UNDERFLOW = 0x00000009U +} QDM_CallbackFuncType; + +/** + * @} + */ + +/** + * @defgroup QDM_Handle_Definition QDM Handle Definition + * @{ + */ + +/** + * @brief configurations of QDU register + */ +typedef struct { + QDM_DecoderMode decoderMode; + QDM_Resolution resolution; + QDM_QtrgLockMode trgLockMode; + QDM_PtuMode ptuMode; + QDM_SwapSelect swap; + unsigned int polarity; +} QDMCtrlConfigure; + +/** + * @brief configurations of input filter level + */ +typedef struct { + unsigned int qdmAFilterLevel; + unsigned int qdmBFilterLevel; + unsigned int qdmZFilterLevel; +} QDMFilter; + +/** + * @brief configurations of input filter level + */ +typedef struct _QDM_handle { + QDM_RegStruct *baseAddress; /**< base address */ + QDM_EmulationMode emuMode; /**< emulation mode select */ + QDMFilter inputFilter; /**< filter settings */ + QDMCtrlConfigure ctrlConfig; /**< QDM control configurations */ + QDM_PcntMode pcntMode; /**< position count mode */ + QDM_PcntRstMode pcntRstMode; /**< position count reset mode */ + QDM_PcntIdxInitMode pcntIdxInitMode; /**< position count index initial mode */ + bool subModeEn; /**< sub-module enable */ + QDM_TSUPrescaler tsuPrescaler; /**< tsu prescaler */ + QDM_CEVTPrescaler cevtPrescaler; /**< cevt prescaler */ + unsigned int posInit; /**< init position */ + unsigned int posMax; /**< max position */ + unsigned int qcMax; /**< TSU maximum counter number, default zero */ + unsigned int period; /**< PTU period*/ + unsigned int interruptEn; /**< interrupt settings by bits */ + int motorLineNum; /**< encoder line number */ + int speedRpm; /**< motor speed */ + QDM_IndexLockMode lock_mode; /**< QDM Z index lock mode */ + QDM_UserCallBack userCallBack; /**< QDM Interrupt callback functions */ + QDM_ExtendHandle handleEx; /**< QDM extend parameter */ +} QDM_Handle; + +typedef void (* QDM_CallbackType)(void *handle); +/** + * @} + */ + +/** + * @defgroup QDM_API_Declaration QDM HAL API + * @{ + */ + +/* Hardware abstraction layer */ +BASE_StatusType HAL_QDM_Init(QDM_Handle *qdmHandle); +BASE_StatusType HAL_QDM_DeInit(QDM_Handle *qdmHandle); +void HAL_QDM_GetPhaseErrorStatus(const QDM_Handle *qdmHandle, unsigned int *errStatus); +void HAL_QDM_ReadPosCountAndDir(const QDM_Handle *qdmHandle, unsigned int *count, unsigned int *dir); +int HAL_QDM_GetSpeedRpmM(QDM_Handle *qdmHandle); +int HAL_QDM_GetSpeedRpmMT(QDM_Handle *qdmHandle); +void HAL_QDM_IrqHandler(void *handle); +void HAL_QDM_RegisterCallback(QDM_Handle *qdmHandle, QDM_CallbackFuncType typeID, QDM_CallbackType pCallback); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/qdm/inc/qdm_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/qdm/inc/qdm_ip.h new file mode 100644 index 00000000..e19e6caf --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/qdm/inc/qdm_ip.h @@ -0,0 +1,1663 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file qdm_ip.h + * @author MCU Driver Team + * @brief Header file containing QDM module DCL driver functions. + * This file provides functions to manage the following functionalities of QDM module. + * + Definition of QDM configuration parameters. + * + QDM registers mapping structure. + * + Direct Configuration Layer driver functions. + */ + +#ifndef McuMagicTag_QDM_IP_H +#define McuMagicTag_QDM_IP_H + +#include "baseinc.h" + +#ifdef QDM_PARAM_CHECK +#define QDM_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define QDM_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define QDM_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define QDM_ASSERT_PARAM(para) ((void)0U) +#define QDM_PARAM_CHECK_NO_RET(para) ((void)0U) +#define QDM_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +#define QDM_MAX_FILTER_LEVEL 0x00001FFF +#define QDM_PPU_MAX_SYNCOUT_PW 0x00000FFF +/** + * @addtogroup QDM + * @{ + */ + +/** + * @defgroup QDM_IP QDM_IP + * @brief QDM_IP: qdm_v0. + * @{ + */ + +/** + * @defgroup QDM_Param_Def QDM Parameters Definition + * @brief Definition of QDM configuration parameters + * @{ + */ + + +/** + * @brief Emulation mode of QDM module. + * @details Emulation mode: + * + QDM_EMULATION_MODE_STOP_IMMEDIATELY -- The position counter, unit timer, + * capture timer all stop immediately. + * + QDM_EMULATION_MODE_STOP_AT_ROLLOVER -- + * The position counter, unit timer count until period rollover, + * and the capture timer counts until the next unit period event. + * + QDM_EMULATION_MODE_RUN_FREE -- The position counter, unit timer, + * capture timer are all unaffected by an emulation suspend. + */ +typedef enum { + QDM_EMULATION_MODE_STOP_IMMEDIATELY = 0x00000000U, + QDM_EMULATION_MODE_STOP_AT_ROLLOVER = 0x00000001U, + QDM_EMULATION_MODE_RUN_FREE = 0x00000002U, +} QDM_EmulationMode; + +/** + * @brief Status flag of QDM module. + * @details status flag: + * + QDM_STATUS_POS_CNT_ERR -- Position counter error + * + QDM_STATUS_1ST_IDX_OCCURRED -- First index pulse occurred + * + QDM_STATUS_DIR_ON_1ST_IDX -- Direction of first index event + * + QDM_STATUS_CAP_DIR_ERR -- Direction changed between position capture events + * + QDM_STATUS_TSU_OVERFLW_ERR -- Timer stamp timer overflow + * + QDM_STATUS_SPEED_LOST -- Speed lost status + * + QDM_STATUS_DIR_FLAG -- Quadrature direction + * + QDM_STATUS_UNIT_POS_EVENT -- Unit position event detected + */ +typedef enum { + QDM_STATUS_POS_CNT_ERR = 0x00000001U, + QDM_STATUS_1ST_IDX_OCCURRED = 0x00000002U, + QDM_STATUS_DIR_ON_1ST_IDX = 0x00000004U, + QDM_STATUS_CAP_DIR_ERR = 0x00000008U, + QDM_STATUS_TSU_OVERFLW_ERR = 0x00000010U, + QDM_STATUS_SPEED_LOST = 0x00000020U, + QDM_STATUS_DIR_FLAG = 0x00000040U, + QDM_STATUS_UNIT_POS_EVENT = 0x00000080U, +} QDM_StatusFlag; + +/** + * @brief Decoder mode of QDM module. + * @details Decoder mode + * + QDM_QUADRATURE_COUNT -- Quadrature-clock mode + * + QDM_CLOCK_DIR_COUNT -- Direction-count mode + * + QDM_NONSTANDARD_TYPE1 -- Non-standard mode 1 + * + QDM_NONSTANDARD_TYPE2 -- Non-standard mode 2 + */ +typedef enum { + QDM_QUADRATURE_COUNT = 0x00000000U, + QDM_CLOCK_DIR_COUNT = 0x00000001U, + QDM_NONSTANDARD_TYPE1 = 0x00000002U, + QDM_NONSTANDARD_TYPE2 = 0x00000003U, +} QDM_DecoderMode; + +/** + * @brief Decode resolution of QDM module. + * @details Decode resolution: + * + QDM_1X_RESOLUTION -- Count rising edge of QDMA/QDMB only + * + QDM_2X_RESOLUTION -- Count rising and falling edge of QDMA/QDMB + * + QDM_4X_RESOLUTION -- Count rising and falling edge of both QDMA and QDMB + */ +typedef enum { + QDM_1X_RESOLUTION = 0x00000000U, + QDM_2X_RESOLUTION = 0x00000001U, + QDM_4X_RESOLUTION = 0x00000002U, +} QDM_Resolution; + +/** + * @brief Count mode of position processing submodule. + */ +typedef enum { + QDM_PPU_COUNT_MODE_CLK_DIR = 0x00000000U, + QDM_PPU_COUNT_MODE_INCREASE = 0x00000001U, + QDM_PPU_COUNT_MODE_DECREASE = 0x00000002U, +} QDM_PPUCountMode; + +/** + * @brief Reset mode of position counter. + * @details Reset mode: + * + QDM_POSITION_RESET_IDX -- Reset position on the rising edge of inde pulse + * + QDM_POSITION_RESET_MAX_POS -- Reset position on maximum position QCNTMAX + * + QDM_POSITION_RESET_1ST_IDX -- Reset position on the first index pulse + * + QDM_POSITION_RESET_UNIT_TIME_OUT -- Reset position on a unit time trigger + */ +typedef enum { + QDM_POSITION_RESET_IDX = 0x00000000, + QDM_POSITION_RESET_MAX_POS = 0x00000001, + QDM_POSITION_RESET_1ST_IDX = 0x00000002, + QDM_POSITION_RESET_UNIT_TIME_OUT = 0x00000003, +} QDM_PosResetMode; + +/** + * @brief Initializaion mode of the index of position counter. + * @details Initializaion mode: + * + QDM_POSITION_INIT_DO_NOTHING -- No action is configured + * + QDM_POSITION_INIT_RISING_INDEX -- On rising edge of index + * + QDM_POSITION_INIT_FALLING_INDEX -- On falling edge of index + */ +typedef enum { + QDM_POSITION_INIT_DO_NOTHING = 0x00000000U, + QDM_POSITION_INIT_RISING_INDEX = 0x00000002U, + QDM_POSITION_INIT_FALLING_INDEX = 0x00000003U, +} QDM_PosIdxInitMode; + +/** + * @brief Shadow load mode of compare counter. + * @details Load mode: + * + QDM_COMPARE_LOAD_ON_ZERO -- Load on QPOSCNT = 0 + * + QDM_COMPARE_LOAD_ON_MATCH -- Load on QPOSCNT = QPOSCMP + */ +typedef enum { + QDM_COMPARE_LOAD_ON_ZERO = 0x00000000U, + QDM_COMPARE_LOAD_ON_MATCH = 0x00000001U, +} QDM_CompShadowLoad; + +/** + * @brief Polarity of sync-out pulse for position compare. + */ +typedef enum { + QDM_SYNC_OUT_HIGH = 0x00000000U, + QDM_SYNC_OUT_LOW = 0x00000001U, +} QDM_CompSyncOutPolarity; + +/** + * @brief Lock mode of index event. + * @details Lock mode: + * + QDM_LOCK_RESERVE -- Do not lock + * + QDM_LOCK_RISING_INDEX -- On rising edge of index + * + QDM_LOCK_FALLING_INDEX -- On falling edge of index + * + QDM_LOCK_SW_INDEX_MARKER -- On software index marker + */ +typedef enum { + QDM_LOCK_RESERVE = 0x00000000, + QDM_LOCK_RISING_INDEX = 0x00000001, + QDM_LOCK_FALLING_INDEX = 0x00000002, + QDM_LOCK_SW_INDEX_MARKER = 0x00000003, +} QDM_IndexLockMode; + +/** + * @brief Prescaler of Time Stamp Unit clock. + * @details Prescaler: + * + QDM_TSU_CLK_DIV_1 -- TSUCLK = SYSCLKOUT/1 + * + QDM_TSU_CLK_DIV_2 -- TSUCLK = SYSCLKOUT/2 + * + QDM_TSU_CLK_DIV_4 -- TSUCLK = SYSCLKOUT/4 + * + QDM_TSUE_CLK_DIV_8 -- TSUCLK = SYSCLKOUT/8 + * + QDM_TSU_CLK_DIV_16 -- TSUCLK = SYSCLKOUT/16 + * + QDM_TSU_CLK_DIV_32 -- TSUCLK = SYSCLKOUT/32 + * + QDM_TSU_CLK_DIV_64 -- TSUCLK = SYSCLKOUT/64 + * + QDM_TSU_CLK_DIV_128 -- TSUCLK = SYSCLKOUT/128 + * + QDM_TSU_CLK_DIV_256 -- TSUCLK = SYSCLKOUT/256 + */ +typedef enum { + QDM_TSU_CLK_DIV_1 = 0x00000000U, + QDM_TSU_CLK_DIV_2 = 0x00000001U, + QDM_TSU_CLK_DIV_4 = 0x00000002U, + QDM_TSUE_CLK_DIV_8 = 0x00000003U, + QDM_TSU_CLK_DIV_16 = 0x00000004U, + QDM_TSU_CLK_DIV_32 = 0x00000005U, + QDM_TSU_CLK_DIV_64 = 0x00000006U, + QDM_TSU_CLK_DIV_128 = 0x00000007U, + QDM_TSU_CLK_DIV_256 = 0x00000008U, +} QDM_TSUCLKPrescale; + +/** + * @brief Prescaler of Unit Position Event. + * @details Prescaler: + * + QDM_UNIT_POS_EVNT_DIV_1 -- UPEVNT = QCLK/1 + * + QDM_UNIT_POS_EVNT_DIV_2 -- UPEVNT = QCLK/2 + * + QDM_UNIT_POS_EVNT_DIV_4 -- UPEVNT = QCLK/4 + * + QDM_UNIT_POS_EVNT_DIV_8 -- UPEVNT = QCLK/8 + * + QDM_UNIT_POS_EVNT_DIV_16 -- UPEVNT = QCLK/16 + * + QDM_UNIT_POS_EVNT_DIV_32 -- UPEVNT = QCLK/32 + * + QDM_UNIT_POS_EVNT_DIV_64 -- UPEVNT = QCLK/64 + * + QDM_UNIT_POS_EVNT_DIV_128 -- UPEVNT = QCLK/128 + * + QDM_UNIT_POS_EVNT_DIV_256 -- UPEVNT = QCLK/256 + * + QDM_UNIT_POS_EVNT_DIV_512 -- UPEVNT = QCLK/512 + * + QDM_UNIT_POS_EVNT_DIV_1024 -- UPEVNT = QCLK/1024 + * + QDM_UNIT_POS_EVNT_DIV_2048 -- UPEVNT = QCLK/2048 + */ +typedef enum { + QDM_UNIT_POS_EVNT_DIV_1 = 0x00000000U, + QDM_UNIT_POS_EVNT_DIV_2 = 0x00000001U, + QDM_UNIT_POS_EVNT_DIV_4 = 0x00000002U, + QDM_UNIT_POS_EVNT_DIV_8 = 0x00000003U, + QDM_UNIT_POS_EVNT_DIV_16 = 0x00000004U, + QDM_UNIT_POS_EVNT_DIV_32 = 0x00000005U, + QDM_UNIT_POS_EVNT_DIV_64 = 0x00000006U, + QDM_UNIT_POS_EVNT_DIV_128 = 0x00000007U, + QDM_UNIT_POS_EVNT_DIV_256 = 0x00000008U, + QDM_UNIT_POS_EVNT_DIV_512 = 0x00000009U, + QDM_UNIT_POS_EVNT_DIV_1024 = 0x0000000AU, + QDM_UNIT_POS_EVNT_DIV_2048 = 0x0000000BU, +} QDM_UPEvntPrescale; + +/** + * @brief Lock mode of Time Stamp Unit. + * @details Lock mode: + * + QDM_TSU_LOCK_ON_SW_READ -- When software read QPOSCNT + * + QDM_TSU_LOCK_ON_UTTRG -- When unit time trigger happens + */ +typedef enum { + QDM_TSU_LOCK_ON_SW_READ = 0x00000000U, + QDM_TSU_LOCK_ON_UTTRG = 0x00000001U, +} QDM_TSULockMode; + +/** + * @brief Working mode of Period Trigger Unit. + */ +typedef enum { + QDM_PERIOD_TRIGGER_MODE = 0x00000000U, + QDM_WATCHDOG_MODE = 0x00000001U, +} QDM_PTUMode; + +/** + * @brief Lock mode of Period Trigger Unit. + * @details Lock mode: + * + QDM_LOCK_POSCNT_READ_BY_CPU -- When QPOSCNT read by CPU/DMA, + * QCTMR and QCPRD are locked + * + QDM_LOCK_UNIT_TIME_TRIGGER,-- When PTU is enabled and unit time triggers, + * QPOSCNT, QCTMR, QCPRD are locked + */ +typedef enum { + QDM_LOCK_POSCNT_READ_BY_CPU, + QDM_LOCK_UNIT_TIME_TRIGGER, +} QDM_TriggerLockMode; /* QPOSCNT, QCTMR, QCPRD lock event */ + +/** + * @brief Interrupt events of QMD module. + * @details Interrupt events: + * + QDM_INT_POS_CNT_ERROR -- Position count error + * + QDM_INT_PHASE_ERROR -- Quadrature phase error + * + QDM_INT_WATCHDOG -- Speed lost error + * + QDM_INT_DIR_CHANGE -- Quadrature direction change + * + QDM_INT_UNDERFLOW -- Position counter underflow + * + QDM_INT_OVERFLOW -- Position counter overflow + * + QDM_INT_POS_COMP_READY -- Position-compare ready + * + QDM_INT_POS_COMP_MATCH -- Position-compare match + * + QDM_INT_INDEX_EVNT_LATCH -- Index event lock + * + QDM_INT_UNIT_TIME_OUT -- Unit time-out + */ +typedef enum { + QDM_INT_POS_CNT_ERROR = 0x00000001U, + QDM_INT_PHASE_ERROR = 0x00000002U, + QDM_INT_WATCHDOG = 0x00000004U, + QDM_INT_DIR_CHANGE = 0x00000008U, + QDM_INT_UNDERFLOW = 0x00000010U, + QDM_INT_OVERFLOW = 0x00000020U, + QDM_INT_POS_COMP_READY = 0x00000040U, + QDM_INT_POS_COMP_MATCH = 0x00000080U, + QDM_INT_INDEX_EVNT_LATCH = 0x00000100U, + QDM_INT_UNIT_TIME_OUT = 0x00000200U, +} QDM_InterruptEvent; + +/** + * @brief QDM TSU prescaler + * @details prescaler values: + * + QDM_TSU_PRESCALER_EQUAL -- Equal to the clock cycle + * + QDM_TSU_PRESCALER_2X -- 2x clock cycle + * + QDM_TSU_PRESCALER_4X -- 2x clock cycle + * + QDM_TSU_PRESCALER_8X -- 8x clock cycle + * + QDM_TSU_PRESCALER_16X -- 16x clock cycle + * + QDM_TSU_PRESCALER_32X -- 32x clock cycle + * + QDM_TSU_PRESCALER_64X -- 64x clock cycle + * + QDM_TSU_PRESCALER_128X -- 128x clock cycle + * + QDM_TSU_PRESCALER_256X -- 256x clock cycle + */ +typedef enum { + QDM_TSU_PRESCALER_EQUAL = 0x00000000U, + QDM_TSU_PRESCALER_2X = 0x00000001U, + QDM_TSU_PRESCALER_4X = 0x00000002U, + QDM_TSU_PRESCALER_8X = 0x00000003U, + QDM_TSU_PRESCALER_16X = 0x00000004U, + QDM_TSU_PRESCALER_32X = 0x00000005U, + QDM_TSU_PRESCALER_64X = 0x00000006U, + QDM_TSU_PRESCALER_128X = 0x00000007U, + QDM_TSU_PRESCALER_256X = 0x00000008U, +} QDM_TSUPrescaler; + +/** + * @brief QDM CEVT prescaler + * @details prescaler values: + * + QDM_CEVT_PRESCALER_DIVI1 -- Don't divided + * + QDM_CEVT_PRESCALER_DIVI2 -- Divide by 2 + * + QDM_CEVT_PRESCALER_DIVI4 -- Divide by 4 + * + QDM_CEVT_PRESCALER_DIVI8 -- Divide by 8 + * + QDM_CEVT_PRESCALER_DIVI16 -- Divide by 16 + * + QDM_CEVT_PRESCALER_DIVI32 -- Divide by 32 + * + QDM_CEVT_PRESCALER_DIVI64 -- Divide by 64 + * + QDM_CEVT_PRESCALER_DIVI128 -- Divide by 128 + * + QDM_CEVT_PRESCALER_DIVI256 -- Divide by 256 + * + QDM_CEVT_PRESCALER_DIVI512 -- Divide by 512 + * + QDM_CEVT_PRESCALER_DIVI1024 -- Divide by 1024 + * + QDM_CEVT_PRESCALER_DIVI2048 -- Divide by 2048 + */ +typedef enum { + QDM_CEVT_PRESCALER_DIVI1 = 0x00000000U, + QDM_CEVT_PRESCALER_DIVI2 = 0x00000001U, + QDM_CEVT_PRESCALER_DIVI4 = 0x00000002U, + QDM_CEVT_PRESCALER_DIVI8 = 0x00000003U, + QDM_CEVT_PRESCALER_DIVI16 = 0x00000004U, + QDM_CEVT_PRESCALER_DIVI32 = 0x00000005U, + QDM_CEVT_PRESCALER_DIVI64 = 0x00000006U, + QDM_CEVT_PRESCALER_DIVI128 = 0x00000007U, + QDM_CEVT_PRESCALER_DIVI256 = 0x00000008U, + QDM_CEVT_PRESCALER_DIVI512 = 0x00000009U, + QDM_CEVT_PRESCALER_DIVI1024 = 0x0000000AU, + QDM_CEVT_PRESCALER_DIVI2048 = 0x0000000BU, +} QDM_CEVTPrescaler; + +/** + * @brief QDM counter reset mode + */ +typedef enum { + QDM_IDX_INIT_DISABLE = 0x00000000U, + QDM_IDX_INIT_AUTO = 0x00000001U, + QDM_IDX_INIT_Z_UP = 0x00000002U, + QDM_IDX_INIT_Z_DOWN = 0x00000003U, +} QDM_PcntIdxInitMode; + +/** + * @brief QDM lock triggle mode + */ +typedef enum { + QDM_TRG_BY_READ = 0x00000000U, + QDM_TRG_BY_CYCLE = 0x00000001U, +} QDM_QtrgLockMode; + +/** + * @brief QDM PTU work mode + */ +typedef enum { + QDM_PTU_MODE_CYCLE = 0x00000000U, + QDM_PTU_MODE_WATCHDOG = 0x00000001U, +} QDM_PtuMode; + +/** + * @brief QDM count mode + */ +typedef enum { + QDM_PCNT_MODE_BY_DIR = 0x00000000U, + QDM_PCNT_MODE_UP = 0x00000001U, + QDM_PCNT_MODE_DOWN = 0x00000002U, +} QDM_PcntMode; + +/** + * @brief QDM counter reset mode + */ +typedef enum { + QDM_PCNT_RST_AUTO = 0x00000000U, + QDM_PCNT_RST_OVF = 0x00000001U, + QDM_PCNT_RST_HARDWARE_ONCE = 0x00000002U, + QDM_PCNT_RST_BY_PTU = 0x00000003U, +} QDM_PcntRstMode; + +/** + * @brief QDM swap selection + */ +typedef enum { + QDM_SWAP_DISABLE = 0x00000000U, + QDM_SWAP_ENABLE = 0x00000001U, +} QDM_SwapSelect; + +/** + * @brief Check whether the EMU mode is used. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsEmuMode(unsigned int mode) +{ + if (mode == QDM_EMULATION_MODE_STOP_IMMEDIATELY || mode == QDM_EMULATION_MODE_STOP_AT_ROLLOVER || + mode == QDM_EMULATION_MODE_RUN_FREE) { + return true; + } + return false; +} + +/** + * @brief Check whether the Z Index lock mode is used. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsLockMode(unsigned int mode) +{ + if (mode == QDM_LOCK_RESERVE || mode == QDM_LOCK_RISING_INDEX || + mode == QDM_LOCK_FALLING_INDEX || mode == QDM_LOCK_SW_INDEX_MARKER) { + return true; + } + return false; +} + +/** + * @brief Check whether the Decode mode is used. + * @param mode QDM decode mode + * @retval true + * @retval false + */ +static inline bool IsDecodeMode(unsigned int mode) +{ + if (mode <= QDM_NONSTANDARD_TYPE2) { + return true; + } + return false; +} + +/** + * @brief Check whether the resolution is right. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsResolution(unsigned int mode) +{ + if (mode == QDM_1X_RESOLUTION || mode == QDM_2X_RESOLUTION || mode == QDM_4X_RESOLUTION) { + return true; + } + return false; +} + +/** + * @brief Check whether the swap is right. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsSwap(unsigned int mode) +{ + if (mode == QDM_SWAP_DISABLE || mode == QDM_SWAP_ENABLE) { + return true; + } + return false; +} + +/** + * @brief Check whether the lock triggle mode is used. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsTrgLockMode(unsigned int mode) +{ + if (mode == QDM_TRG_BY_READ || mode == QDM_TRG_BY_CYCLE) { + return true; + } + return false; +} + +/** + * @brief Check whether the ptu mode is used. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsPtuMode(unsigned int mode) +{ + if (mode == QDM_PTU_MODE_CYCLE || mode == QDM_PTU_MODE_WATCHDOG) { + return true; + } + return false; +} + +/** + * @brief Check whether the position counter is used. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsPcntMode(unsigned int mode) +{ + if (mode == QDM_PCNT_MODE_BY_DIR || mode == QDM_PCNT_MODE_UP || mode == QDM_PCNT_MODE_DOWN) { + return true; + } + return false; +} + +/** + * @brief Check whether the PcntRstMode is used. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsPcntRstMode(unsigned int mode) +{ + if (mode == QDM_PCNT_RST_AUTO || mode == QDM_PCNT_RST_OVF || + mode == QDM_PCNT_RST_HARDWARE_ONCE || mode == QDM_PCNT_RST_BY_PTU) { + return true; + } + return false; +} + +/** + * @brief Check whether the PcntIdxInitMode is used. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsPcntIdxInitMode(unsigned int mode) +{ + if (mode == QDM_IDX_INIT_DISABLE || mode == QDM_IDX_INIT_AUTO || + mode == QDM_IDX_INIT_Z_UP || mode == QDM_IDX_INIT_Z_DOWN) { + return true; + } + return false; +} + +/** + * @brief Check whether the TsuPrescaler is used. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsTsuPrescaler(unsigned int mode) +{ + /* Check whether the TSU prescaler is right. */ + if (mode == QDM_TSU_PRESCALER_EQUAL || mode == QDM_TSU_PRESCALER_2X || + mode == QDM_TSU_PRESCALER_4X || mode == QDM_TSU_PRESCALER_8X || + mode == QDM_TSU_PRESCALER_16X || mode == QDM_TSU_PRESCALER_32X || + mode == QDM_TSU_PRESCALER_64X || mode == QDM_TSU_PRESCALER_128X || + mode == QDM_TSU_PRESCALER_256X) { + return true; + } + return false; +} + +/** + * @brief Check whether the CevtPrescaler is used. + * @param mode QDM mode + * @retval true + * @retval false + */ +static inline bool IsCevtPrescaler(unsigned int mode) +{ + /* Check whether the CEVT prescaler is right. */ + if (mode == QDM_CEVT_PRESCALER_DIVI1 || mode == QDM_CEVT_PRESCALER_DIVI2 || + mode == QDM_CEVT_PRESCALER_DIVI4 || mode == QDM_CEVT_PRESCALER_DIVI8 || + mode == QDM_CEVT_PRESCALER_DIVI16 || mode == QDM_CEVT_PRESCALER_DIVI32 || + mode == QDM_CEVT_PRESCALER_DIVI64 || mode == QDM_CEVT_PRESCALER_DIVI128 || + mode == QDM_CEVT_PRESCALER_DIVI256 || mode == QDM_CEVT_PRESCALER_DIVI512 || + mode == QDM_CEVT_PRESCALER_DIVI1024 || mode == QDM_CEVT_PRESCALER_DIVI2048) { + return true; + } + return false; +} + +/** + * @brief Check whether the QDM_StatusFlag is used. + * @param status QDM status flag + * @retval true + * @retval false + */ +static inline bool IsQDMStatusMode(QDM_StatusFlag status) +{ + /* Check whether the QDM Status flag is right. */ + if (status == QDM_STATUS_POS_CNT_ERR || status == QDM_STATUS_1ST_IDX_OCCURRED || + status == QDM_STATUS_DIR_ON_1ST_IDX || status == QDM_STATUS_CAP_DIR_ERR || + status == QDM_STATUS_TSU_OVERFLW_ERR || status == QDM_STATUS_SPEED_LOST || + status == QDM_STATUS_DIR_FLAG || status == QDM_STATUS_UNIT_POS_EVENT) { + return true; + } + return false; +} + +/** + * @brief Check whether the QDM interrupt event type is right. + * @param status QDM interrupt event + * @retval true + * @retval false + */ +static inline bool IsQDMInterruptEvent(QDM_InterruptEvent intEvt) +{ + /* Check whether the QDM interrupt type is right. */ + QDM_PARAM_CHECK_WITH_RET(intEvt >= QDM_INT_POS_CNT_ERROR, BASE_STATUS_ERROR); + QDM_PARAM_CHECK_WITH_RET(intEvt <= QDM_INT_UNIT_TIME_OUT, BASE_STATUS_ERROR); + if (intEvt == QDM_INT_POS_CNT_ERROR || ((unsigned int)intEvt % 2U) == 0) { + return true; + } + return false; +} + +/** + * @} + */ + + +/** + * @defgroup QDM_REG_Definition QDM Register Structure. + * @brief QDM Register Structure Definition. + * @{ + */ + +/** + * @brief QDM version registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int month_day : 16; /**< Month and day. */ + unsigned int year : 8; /**< Year. */ + unsigned int release_substep : 1; /**< Version information. */ + unsigned int release_step : 1; /**< Version information. */ + unsigned int release_ver : 1; /**< Version information. */ + unsigned int reserved_0 : 5; + } BIT; +} volatile QDM_QDMVER_REG; + +/** + * @brief QDM emulation mode configuration registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int emu_mode : 2; /**< QDM emulation access mode. */ + unsigned int reserved_0 : 30; + } BIT; +} volatile QDM_QEMUMODE_REG; + +/** + * @brief QDM control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ptu_en : 1; /**< PTU period triggle unit enable. */ + unsigned int ppu_en : 1; /**< PPU position process unit enable. */ + unsigned int tsu_en : 1; /**< TSU timestamp unit enable. */ + unsigned int ptu_mode : 1; /**< PTU work mode. */ + unsigned int qtrg_lock_mode : 1; /**< QDM triggle locked mode selection. */ + unsigned int reserved_0 : 3; + unsigned int qdmi_polarity : 1; /**< Z pulse polarity selection. */ + unsigned int qdmb_polarity : 1; /**< B pulse polarity selection. */ + unsigned int qdma_polarity : 1; /**< A pulse polarity selection. */ + unsigned int qdm_ab_swap : 1; /**< Input signal swap of A pulse and B pulse. */ + unsigned int qdu_xclk : 2; /**< QDM position pulse frequency multiplication. */ + unsigned int qdu_mode : 2; /**< QDM decode mode. */ + unsigned int reserved_1 : 16; + } BIT; +} volatile QDM_QCTRL_REG; + +/** + * @brief PPU control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int ppu_syncout_pw : 12; /**< Pulse width selection of position comparison sync output. */ + unsigned int ppu_syncout_pl : 1; /**< Polarity of position comparison sync output. */ + unsigned int syncout_en : 1; /**< Position comparison sync output enable. */ + unsigned int reserved_0 : 2; + unsigned int ppu_poscmp_en : 1; /**< Position comparison function enable. */ + unsigned int ppu_cmpshd_ld : 1; /**< Load mode of position comparison buffer register. */ + unsigned int ppu_cmpshd_en : 1; /**< Position comparison buffer register enable. */ + unsigned int reserved_1 : 1; + unsigned int pcnt_idx_lock_mode : 2; /**< Z pulse locked mode selection of position counter. */ + unsigned int pcnt_idx_init_mode : 2; /**< Z pulse initialization mode of position counter. */ + unsigned int pcnt_rst_mode : 2; /**< Reset selection of position counter. */ + unsigned int pcnt_mode : 2; /**< Count mode of position counter. */ + unsigned int pcnt_sw_init : 1; /**< Software initialization of position counter. */ + unsigned int reserved_2 : 3; + } BIT; +} volatile QDM_QPPUCTRL_REG; + +/** + * @brief TSU control registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cevt_prescaler : 4; /**< Frequency division selection of the capture event CEVT. */ + unsigned int tsu_prescaler : 4; /**< TSU timing step length selection. */ + unsigned int qtmr_lock_mode : 1; /**< TSU locked mode. */ + unsigned int reserved_0 : 23; + } BIT; +} volatile QDM_QTSUCTRL_REG; + +/** + * @brief QDM interrupt enable registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pcnt_err_en : 1; /**< Position count error interrupt enable. */ + unsigned int qphs_err_en : 1; /**< Quadrature pulse error interrupt enable. */ + unsigned int sped_lst_en : 1; /**< QDM speed loss interrupt enable. */ + unsigned int qdir_chg_en : 1; /**< Quadrature direction change interrupt enable. */ + unsigned int pcnt_udf_en : 1; /**< Position counter underflow interrupt enable. */ + unsigned int pcnt_ovf_en : 1; /**< Position counter overflow interrupt enable. */ + unsigned int pcnt_cpr_en : 1; /**< Position comparision ready interrupt enable. */ + unsigned int pcnt_cpm_en : 1; /**< Position comparision match interrupt enable. */ + unsigned int indx_lck_en : 1; /**< Z pulse locked fuction interrupt enable. */ + unsigned int utmr_prd_en : 1; /**< PTU period interrupt enable. */ + unsigned int reserved_0 : 2; + unsigned int reserved_1 : 20; + } BIT; +} volatile QDM_QINTENA_REG; + +/** + * @brief QDM interrupt status registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pcnt_err_int : 1; /**< Position count error interrupt. */ + unsigned int qphs_err_int : 1; /**< Quadrature pulse error interrupt. */ + unsigned int sped_lst_int : 1; /**< QDM speed loss interrupt. */ + unsigned int qdir_chg_int : 1; /**< Quadrature direction change interrupt. */ + unsigned int pcnt_udf_int : 1; /**< Position counter underflow interrupt. */ + unsigned int pcnt_ovf_int : 1; /**< Position counter overflow interrupt. */ + unsigned int pcnt_cpr_int : 1; /**< Position comparision ready interrupt. */ + unsigned int pcnt_cpm_int : 1; /**< Position comparision match interrupt. */ + unsigned int indx_lck_int : 1; /**< Z pulse locked fuction interrupt. */ + unsigned int utmr_prd_int : 1; /**< PTU period interrupt. */ + unsigned int reserved_0 : 2; + unsigned int reserved_1 : 20; + } BIT; +} volatile QDM_QINTSTS_REG; + +/** + * @brief QDM initial interrupt registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pcnt_err_raw : 1; /**< Position count error initial interrupt. */ + unsigned int qphs_err_raw : 1; /**< Quadrature pulse error initial interrupt. */ + unsigned int sped_lst_raw : 1; /**< QDM speed loss initial interrupt. */ + unsigned int qdir_chg_raw : 1; /**< Quadrature direction change initial interrupt. */ + unsigned int pcnt_udf_raw : 1; /**< Position counter underflow initial interrupt. */ + unsigned int pcnt_ovf_raw : 1; /**< Position counter overflow initial interrupt. */ + unsigned int pcnt_cpr_raw : 1; /**< Position comparision ready initial interrupt. */ + unsigned int pcnt_cpm_raw : 1; /**< Position comparision match initial interrupt. */ + unsigned int indx_lck_raw : 1; /**< Z pulse locked fuction initial interrupt. */ + unsigned int utmr_prd_raw : 1; /**< PTU period initial interrupt. */ + unsigned int reserved_0 : 2; + unsigned int reserved_1 : 20; + } BIT; +} volatile QDM_QINTRAW_REG; + +/** + * @brief QDM injection interrupt registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pcnt_err_inj : 1; /**< Position count error injection interrupt. */ + unsigned int qphs_err_inj : 1; /**< Quadrature pulse error injection interrupt. */ + unsigned int sped_lst_inj : 1; /**< QDM speed loss injection interrupt. */ + unsigned int qdir_chg_inj : 1; /**< Quadrature direction change injection interrupt. */ + unsigned int pcnt_udf_inj : 1; /**< Position counter underflow injection interrupt. */ + unsigned int pcnt_ovf_inj : 1; /**< Position counter overflow injection interrupt. */ + unsigned int pcnt_cpr_inj : 1; /**< Position comparision ready injection interrupt. */ + unsigned int pcnt_cpm_inj : 1; /**< Position comparision match injection interrupt. */ + unsigned int indx_lck_inj : 1; /**< Z pulse locked fuction injection interrupt. */ + unsigned int utmr_prd_inj : 1; /**< PTU period injection interrupt. */ + unsigned int reserved_0 : 2; + unsigned int reserved_1 : 20; + } BIT; +} volatile QDM_QINTINJ_REG; + +/** + * @brief QDM status registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int pcnt_err_sts : 1; /**< Position count error status. */ + unsigned int fidx_is_sts : 1; /**< Whether QDM passes the first Z-phase marker. */ + unsigned int fidx_dir_sts : 1; /**< The direction of QDM firstly passes the Z-phase marker. */ + unsigned int qcdr_err_sts : 1; /**< QDM capture direction error status. */ + unsigned int qctmr_ovf_sts : 1; /**< TSU timing count overflow status. */ + unsigned int sepd_lst_sts : 1; /**< QDM speed loss status. */ + unsigned int qdir_sts : 1; /**< QDM quadrature direction status. */ + unsigned int cevt_sts : 1; /**< QDM capture events status. */ + unsigned int reserved_0 : 24; + } BIT; +} volatile QDM_QDMSTS_REG; + +/** + * @brief QDM A-phase signal filter registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int qdma_ft_level : 13; /**< The filter level of A-phase signal. */ + unsigned int reserved_0 : 19; + } BIT; +} volatile QDM_QDMAFT_REG; + +/** + * @brief QDM B-phase signal filter registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int qdmb_ft_level : 13; /**< The filter level of B-phase signal. */ + unsigned int reserved_0 : 19; + } BIT; +} volatile QDM_QDMBFT_REG; + +/** + * @brief QDM Z-phase signal filter registers union structure definition. + */ +typedef union { + unsigned int reg; + struct { + unsigned int qdmi_ft_level : 13; /**< The filter level of Z-phase signal. */ + unsigned int reserved_0 : 19; + } BIT; +} volatile QDM_QDMIFT_REG; + +/** + * @brief QDM Interrupt callback functions. + * + */ +typedef struct { + void (* PtuCycleTrgCallback)(void *handle); /**< PTU triggle interrupt callback */ + void (* SpeedLoseCallback)(void *handle); /**< speed lose detection callback */ + void (* ZIndexLockedCallBack)(void *handle); /**< Z index lock interrupt callback.*/ + void (* PositionCompareMatchCallBack)(void *handle); /**< Position compare match interrupt. */ + void (* PositionCompareReadyCallBack)(void *handle); /**< Position compare ready interrupt. */ + void (* PositionCounterOverflowCallBack)(void *handle); /**< Position counter overflow interrupt. */ + void (* PositionCounterUnderflowCallBack)(void *handle); /**< Position counter underflow interrupt. */ + void (* OrthogonalDirectionChangeCallBack)(void *handle); /**< Orthogonal direction change interrupt. */ + void (* OrthogonalPhaseErrorCallBack)(void *handle); /**< Orthogonal phase error interrupt. */ + void (* PositionCounterErrorCallBack)(void *handle); /**< Position counter error interrupt. */ +} QDM_UserCallBack; + +/** + * @brief QDM extend handle. + */ +typedef struct _QDM_ExtendeHandle { +} QDM_ExtendHandle; + +/** + * @brief QDM registers definition structure. + */ +typedef struct { + QDM_QDMVER_REG QDMVER; /**< QDM version register, offset address: 0x0000. */ + QDM_QEMUMODE_REG QEMUMODE; /**< QDM emulation mode configuration register, offset address: 0x0004. */ + QDM_QCTRL_REG QCTRL; /**< QDM control register, offset address: 0x0008. */ + QDM_QPPUCTRL_REG QPPUCTRL; /**< PPU control register, offset address: 0x000C. */ + QDM_QTSUCTRL_REG QTSUCTRL; /**< TSU control register, offset address: 0x0010. */ + QDM_QINTENA_REG QINTENA; /**< QDM interrupt enable register, offset address: 0x0014. */ + QDM_QINTSTS_REG QINTSTS; /**< QDM interrupt status register, offset address: 0x0018. */ + QDM_QINTRAW_REG QINTRAW; /**< QDM initial interrupt register, offset address: 0x001C. */ + QDM_QINTINJ_REG QINTINJ; /**< QDM injection interrupt register, offset address: 0x0020. */ + QDM_QDMSTS_REG QDMSTS; /**< QDM status register, offset address: 0x0024. */ + unsigned int QPOSCNT; /**< PPU position counter value, offset address: 0x0028. */ + unsigned int QPOSINIT; /**< PPU position counter initialization value, offset address: 0x002C. */ + unsigned int QPOSMAX; /**< PPU position counter maximum value, offset address: 0x0030. */ + unsigned int QPOSCMP; /**< PPU position counter compare value, offset address: 0x0034. */ + unsigned int QPOSILOCK; /**< PPU QPOSCNT inde locked value, offset address: 0x0038. */ + unsigned int QPOSLOCK; /**< PPU QPOSCNT locked value, offset address: 0x003C. */ + unsigned int QUTMR; /**< PTU counter value, offset address: 0x0040. */ + unsigned int QUPRD; /**< PTU period value, offset address: 0x0044. */ + unsigned int QCTMR; /**< TSU counter value, offset address: 0x0048. */ + unsigned int QCMAX; /**< TSU counter maximum value, offset address: 0x004C. */ + unsigned int QCPRD; /**< TSU-captured CEVT's period, offset address: 0x0050. */ + unsigned int QCTMRLOCK; /**< QCTMR locked value, offset address: 0x0054. */ + unsigned int QCPRDLOCK; /**< QCPRD locked value, offset address: 0x0058. */ + QDM_QDMAFT_REG QDMAFT; /**< QDM A-phase signal filter register, offset address: 0x005C. */ + QDM_QDMBFT_REG QDMBFT; /**< QDM B-phase signal filter register, offset address: 0x0060. */ + QDM_QDMIFT_REG QDMIFT; /**< QDM Z-phase signal filter register, offset address: 0x0064. */ + unsigned int QPOSCMPA; /**< QDM Position Counter Active Compare Value, offset address: 0x0068. */ +} volatile QDM_RegStruct; + +/** + * @brief Set the emulation mode of QDM module. + * @param qdmx QDM register base address. + * @param emuMode Emulation mode. + * @retval None. + */ +static inline void DCL_QDM_SetEmulationMode(QDM_RegStruct *qdmx, QDM_EmulationMode emuMode) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(emuMode >= QDM_EMULATION_MODE_STOP_IMMEDIATELY); + QDM_PARAM_CHECK_NO_RET(emuMode <= QDM_EMULATION_MODE_RUN_FREE); + qdmx->QEMUMODE.BIT.emu_mode = emuMode; +} + +/** + * @brief Get the working status of QDM module. + * @param qdmx QDM register base address. + * @param status Working status flag. + * @retval unsigned short The flag value. + */ +static inline bool DCL_QDM_GetModuleStatus(const QDM_RegStruct *qdmx, QDM_StatusFlag status) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_ASSERT_PARAM(IsQDMStatusMode(status)); + return ((qdmx->QDMSTS.reg & (unsigned int)status) == status); +} + +/** + * @brief Clear the specific working status of QDM module. + * @param qdmx QDM register base address. + * @param status Working status flag. + * @retval None. + */ +static inline void DCL_QDM_ClearModuleStatus(QDM_RegStruct *qdmx, QDM_StatusFlag status) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_ASSERT_PARAM(IsQDMStatusMode(status)); + qdmx->QDMSTS.reg |= (unsigned int)status; +} + +/* Quadrature Decoder Unit --------------------------------------------------------------------- */ +/** + * @brief Set the polarity of QDM module inputs. + * @param qdmx QDM register base address. + * @param ivtQDMA QDMA input. + * @param ivtQDMB QDMB input. + * @param ivtQDMI QDMI input. + * @retval None. + */ +static inline void DCL_QDM_SetInputPolarity(QDM_RegStruct *qdmx, bool ivtQDMA, bool ivtQDMB, bool ivtQDMI) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QCTRL.BIT.qdma_polarity = ivtQDMA; + qdmx->QCTRL.BIT.qdmb_polarity = ivtQDMB; + qdmx->QCTRL.BIT.qdmi_polarity = ivtQDMI; +} + +/** + * @brief Set the filter width of QDM module inputs. + * @param qdmx QDM register base address. + * @param filtWidthQDMA Filter width of QDMA input. + * @param filtWidthQDMB Filter width of QDMB input. + * @param filtWidthQDMI Filter width of QDMI input. + * @retval None. + */ +static inline void DCL_QDM_SetInputFilterWidth(QDM_RegStruct *qdmx, + unsigned short filtWidthQDMA, + unsigned short filtWidthQDMB, + unsigned short filtWidthQDMI) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(filtWidthQDMA <= QDM_MAX_FILTER_LEVEL); + QDM_PARAM_CHECK_NO_RET(filtWidthQDMB <= QDM_MAX_FILTER_LEVEL); + QDM_PARAM_CHECK_NO_RET(filtWidthQDMI <= QDM_MAX_FILTER_LEVEL); + /* Set QDM input filter width. */ + qdmx->QDMAFT.BIT.qdma_ft_level = filtWidthQDMA; + qdmx->QDMBFT.BIT.qdmb_ft_level = filtWidthQDMB; + qdmx->QDMIFT.BIT.qdmi_ft_level = filtWidthQDMI; +} + +/** + * @brief Swap the inputs of QDMA and QDMB. + * @param qdmx QDM register base address. + * @param swap Swap enable. + * @retval None. + */ +static inline void DCL_QDM_SetABSwap(QDM_RegStruct *qdmx, bool swap) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QCTRL.BIT.qdm_ab_swap = swap; +} + +/** + * @brief Set the decoder mode of QDM module. + * @param qdmx QDM register base address. + * @param decoderMode Decoder mode. + * @retval None. + */ +static inline void DCL_QDM_SetDecoderMode(QDM_RegStruct *qdmx, QDM_DecoderMode decoderMode) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(IsDecodeMode(decoderMode)); + qdmx->QCTRL.BIT.qdu_mode = decoderMode; +} + +/** + * @brief Set the resolution of decoder. + * @param qdmx QDM register base address. + * @param resolution Decoder resolution. + * @retval None. + */ +static inline void DCL_QDM_SetResolution(QDM_RegStruct *qdmx, QDM_Resolution resolution) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(resolution >= QDM_1X_RESOLUTION); + QDM_PARAM_CHECK_NO_RET(resolution <= QDM_4X_RESOLUTION); + qdmx->QCTRL.BIT.qdu_xclk = resolution; +} + +/* Position Process Unit ----------------------------------------------------------------------- */ +/** + * @brief Enable Position Process Unit. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_EnablePosProcess(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QCTRL.BIT.ppu_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable Position Process Unit. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_DisablePosProcess(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QCTRL.BIT.ppu_en = BASE_CFG_DISABLE; +} + +/** + * @brief Enable/Disable software initialization of position counter. + * @param qdmx QDM register base address. + * @param swInit Software enable. + * @retval None. + */ +static inline void DCL_QDM_SetSWPosInit(QDM_RegStruct *qdmx, bool swInit) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPPUCTRL.BIT.pcnt_sw_init = swInit; +} + +/** + * @brief Set the count mode of position counter. + * @param qdmx QDM register base address. + * @param cntMode Count mode. + * @retval None. + */ +static inline void DCL_QDM_SetCountMode(QDM_RegStruct *qdmx, QDM_PPUCountMode cntMode) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(cntMode >= QDM_PPU_COUNT_MODE_CLK_DIR); + QDM_PARAM_CHECK_NO_RET(cntMode <= QDM_PPU_COUNT_MODE_DECREASE); + qdmx->QPPUCTRL.BIT.pcnt_mode = cntMode; +} + +/** + * @brief Set the reset mode of position counter. + * @param qdmx QDM register base address. + * @param rstMode Reset mode. + * @retval None. + */ +static inline void DCL_QDM_SetPosResetMode(QDM_RegStruct *qdmx, QDM_PosResetMode rstMode) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(rstMode >= QDM_POSITION_RESET_IDX); + QDM_PARAM_CHECK_NO_RET(rstMode <= QDM_POSITION_RESET_UNIT_TIME_OUT); + qdmx->QPPUCTRL.BIT.pcnt_rst_mode = rstMode; +} + +/** + * @brief Set the initialization mode of position counter. + * @param qdmx QDM register base address. + * @param initMode Initialization mode. + * @retval None. + */ +static inline void DCL_QDM_SetPosInitMode(QDM_RegStruct *qdmx, QDM_PosIdxInitMode initMode) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(initMode >= QDM_POSITION_INIT_DO_NOTHING); + QDM_PARAM_CHECK_NO_RET(initMode <= QDM_POSITION_INIT_FALLING_INDEX); + qdmx->QPPUCTRL.BIT.pcnt_idx_init_mode = initMode; +} + +/** + * @brief Set the index lock mode. + * @param qdmx QDM register base address. + * @param lockMode Lock mode of index. + * @retval None. + */ +static inline void DCL_QDM_SetIndexLockMode(QDM_RegStruct *qdmx, QDM_IndexLockMode lockMode) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(lockMode >= QDM_LOCK_RESERVE); + QDM_PARAM_CHECK_NO_RET(lockMode <= QDM_LOCK_SW_INDEX_MARKER); + qdmx->QPPUCTRL.BIT.pcnt_idx_lock_mode = lockMode; +} + +/** + * @brief Set the initial value of position counter. + * @param qdmx QDM register base address. + * @param position Initial value. + * @retval None. + */ +static inline void DCL_QDM_SetInitialPos(QDM_RegStruct *qdmx, unsigned int position) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPOSINIT = position; +} + +/** + * @brief Set the max value of position counter. + * @param qdmx QDM register base address. + * @param maxPos Max value. + * @retval None. + */ +static inline void DCL_QDM_SetMaxPos(QDM_RegStruct *qdmx, unsigned int maxPos) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPOSMAX = maxPos; +} + +/** + * @brief Get the current value of position counter. + * @param qdmx QDM register base address. + * @retval unsigned int Value of position counter. + * @retval None. + */ +static inline unsigned int DCL_QDM_GetCurPos(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return (qdmx->QPOSCNT); +} + +/** + * @brief Enable position compare. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_EnablePosComp(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPPUCTRL.BIT.ppu_poscmp_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable position compare. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_DisablePosComp(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPPUCTRL.BIT.ppu_poscmp_en = BASE_CFG_DISABLE; +} + +/** + * @brief Set the position compare value. + * @param qdmx QDM register base address. + * @param compVal Compare value. + * @retval None. + */ +static inline void DCL_QDM_SetPosCompVal(QDM_RegStruct *qdmx, unsigned int compVal) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPOSCMP = compVal; +} + +/** + * @brief Enable position compare sync-out pulse. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_EnableCompSyncOut(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPPUCTRL.BIT.syncout_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable position compare sync-out pulse. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_DisableCompSyncOut(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPPUCTRL.BIT.syncout_en = BASE_CFG_DISABLE; +} + +/** + * @brief Set the pulse width of position compare sync-out pulse. + * @param qdmx QDM register base address. + * @param width Pulse width. + * @retval None. + */ +static inline void DCL_QDM_SetCompSyncOutWidth(QDM_RegStruct *qdmx, unsigned short width) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(width <= QDM_PPU_MAX_SYNCOUT_PW); + /* In units of 4 PCLK cycles */ + qdmx->QPPUCTRL.BIT.ppu_syncout_pw = width; +} + +/** + * @brief Set the polarity of position compare sync-out pulse. + * @param qdmx QDM register base address. + * @param polarity Sync-out pulse polarity. + * @retval None. + */ +static inline void DCL_QDM_SetCompSyncOutPolarity(QDM_RegStruct *qdmx, QDM_CompSyncOutPolarity polarity) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(polarity == QDM_SYNC_OUT_HIGH || polarity == QDM_SYNC_OUT_LOW); + qdmx->QPPUCTRL.BIT.ppu_syncout_pl = polarity; +} + +/** + * @brief Enable shadow mode of position compare. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_EnablePosCompShadow(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPPUCTRL.BIT.ppu_cmpshd_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable shadow mode of position compare. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_DisablePosCompShadow(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QPPUCTRL.BIT.ppu_cmpshd_en = BASE_CFG_DISABLE; +} + +/** + * @brief Set the shadow load mode of position compare. + * @param qdmx QDM register base address. + * @param shadowMode Shadow load mode. + * @retval None. + */ +static inline void DCL_QDM_SetCompShadowMode(QDM_RegStruct *qdmx, QDM_CompShadowLoad shadowMode) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(shadowMode == QDM_COMPARE_LOAD_ON_ZERO || shadowMode == QDM_COMPARE_LOAD_ON_MATCH); + qdmx->QPPUCTRL.BIT.ppu_cmpshd_ld = shadowMode; +} + +/** + * @brief Get the position index lock value. + * @param qdmx QDM register base address. + * @retval unsigned int Index lock value. + */ +static inline unsigned int DCL_QDM_GetPosIndexLock(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return (qdmx->QPOSILOCK); +} + +/** + * @brief Get the unit time position lock value. + * @param qdmx QDM register base address. + * @retval unsigned int Unit time position lock value. + */ +static inline unsigned int DCL_QDM_GetPosUnitTimeLock(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return (qdmx->QPOSLOCK); +} + +/* Time Stamp Unit ----------------------------------------------------------------------------- */ +/** + * @brief Enable Time Stamp Unit capture. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_EnableTSUCap(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + /* EQEP_enableCapture */ + qdmx->QCTRL.BIT.tsu_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable Time Stamp Unit capture. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_DisableTSUCap(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + /* EQEP_disableCapture */ + qdmx->QCTRL.BIT.tsu_en = BASE_CFG_DISABLE; +} + +/** + * @brief Configure Time Stamp Unit capture. + * @param qdmx QDM register base address. + * @param tscPrsc Clock prescaler. + * @param evtPrsc Unit position event prescaler. + * @param tsuLock Time Stamp Unit lock mode. + * @retval None. + */ +static inline void DCL_QDM_ConfigTSUCap(QDM_RegStruct *qdmx, + QDM_TSUCLKPrescale tscPrsc, + QDM_UPEvntPrescale evtPrsc, + QDM_TSULockMode tsuLock) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + /* Check whether function parameters the is right. */ + QDM_PARAM_CHECK_NO_RET(tscPrsc >= QDM_TSU_CLK_DIV_1); + QDM_PARAM_CHECK_NO_RET(tscPrsc <= QDM_TSU_CLK_DIV_256); + QDM_PARAM_CHECK_NO_RET(evtPrsc >= QDM_UNIT_POS_EVNT_DIV_1); + QDM_PARAM_CHECK_NO_RET(evtPrsc <= QDM_UNIT_POS_EVNT_DIV_2048); + QDM_PARAM_CHECK_NO_RET(tsuLock == QDM_TSU_LOCK_ON_SW_READ || tsuLock == QDM_TSU_LOCK_ON_UTTRG); + qdmx->QTSUCTRL.BIT.tsu_prescaler = tscPrsc; + qdmx->QTSUCTRL.BIT.cevt_prescaler = evtPrsc; + qdmx->QTSUCTRL.BIT.qtmr_lock_mode = tsuLock; +} + +/** + * @brief Get the capture timer value. + * @param qdmx QDM register base address. + * @retval unsigned int The capture timer value. + */ +static inline unsigned int DCL_QDM_GetCapTimer(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return (qdmx->QCTMR); +} + +/** + * @brief Set the max value of capture timer. + * @param qdmx QDM register base address. + * @param maxCount Max value. + * @retval None. + */ +static inline void DCL_QDM_SetCapMaxCnt(QDM_RegStruct *qdmx, unsigned int maxCount) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QCMAX = maxCount; +} + +/** + * @brief Get the period of capture timer. + * @param qdmx QDM register base address. + * @retval unsigned int Period of capture timer. + */ +static inline unsigned int DCL_QDM_GetCapPeriod(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return (qdmx->QCPRD); +} + +/** + * @brief Get the lock value of capture timer. + * @param qdmx QDM register base address. + * @retval unsigned int Lock value. + */ +static inline unsigned int DCL_QDM_GetCapTimerLock(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return (qdmx->QCTMRLOCK); +} + +/** + * @brief Get the period value of capture timer. + * @param qdmx QDM register base address. + * @retval unsigned int Period value of capture timer. + */ +static inline unsigned int DCL_QDM_GetCapPeriodLock(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return (qdmx->QCPRDLOCK); +} + +/* Period Trigger Unit ------------------------------------------------------------------------- */ +/** + * @brief Enable Period Trigger Unit. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_EnablePeriodTrigger(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QCTRL.BIT.ptu_en = BASE_CFG_ENABLE; +} + +/** + * @brief Disable Period Trigger Unit. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_DisablePeriodTrigger(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QCTRL.BIT.ptu_en = BASE_CFG_DISABLE; +} + +/** + * @brief Set the working mode of Period Trigger Unit. + * @param qdmx QDM register base address. + * @param ptuMode Working mode of Period Trigger Unit. + * @retval None. + */ +static inline void DCL_QDM_SetPeriodTriggerUnitMode(QDM_RegStruct *qdmx, QDM_PTUMode ptuMode) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(ptuMode == QDM_PERIOD_TRIGGER_MODE || ptuMode == QDM_WATCHDOG_MODE); + qdmx->QCTRL.BIT.ptu_mode = ptuMode; +} + +/** + * @brief Set the trigger lock mode. + * @param qdmx QDM register base address. + * @param lockMode Trigger lock mode. + * @retval None. + */ +static inline void DCL_QDM_SetTriggerLockMode(QDM_RegStruct *qdmx, QDM_TriggerLockMode lockMode) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + QDM_PARAM_CHECK_NO_RET(lockMode == QDM_LOCK_POSCNT_READ_BY_CPU || lockMode == QDM_LOCK_UNIT_TIME_TRIGGER); + qdmx->QCTRL.BIT.qtrg_lock_mode = lockMode; +} + +/** + * @brief Set the period of unit time event. + * @param qdmx QDM register base address. + * @param period Period of unit time event. + * @retval None. + */ +static inline void DCL_QDM_SetTriggerPeriod(QDM_RegStruct *qdmx, unsigned int period) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QUPRD = period; +} + +/** + * @brief Get the value of period counter. + * @param qdmx QDM register base address. + * @retval unsigned int Value of period counter. + */ +static inline unsigned int DCL_QDM_GetPeriodCounter(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return (qdmx->QUTMR); +} + +/* Interrupt Generator ------------------------------------------------------------------------- */ +/** + * @brief Enable specific interrupt. + * @param qdmx QDM register base address. + * @param intEvt Interrupt event. + * @retval None. + */ +static inline void DCL_QDM_EnableInterrupt(QDM_RegStruct *qdmx, QDM_InterruptEvent intEvt) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + /* Check whether the QDM interrupt type is right. */ + QDM_PARAM_CHECK_NO_RET(IsQDMInterruptEvent(intEvt)); + qdmx->QINTENA.reg |= (unsigned int)intEvt; +} + +/** + * @brief Disable specific interrupt. + * @param qdmx QDM register base address. + * @param intEvt Interrupt event. + * @retval None. + */ +static inline void DCL_QDM_DisableInterrupt(QDM_RegStruct *qdmx, QDM_InterruptEvent intEvt) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + /* Check whether the QDM interrupt type is right. */ + QDM_PARAM_CHECK_NO_RET(IsQDMInterruptEvent(intEvt)); + qdmx->QINTENA.reg &= (~(unsigned int)intEvt); +} + +/** + * @brief Get the specific interrupt flag. + * @param qdmx QDM register base address. + * @param intEvt Interrupt event. + * @retval bool true, false. + */ +static inline bool DCL_QDM_GetInterruptFlag(QDM_RegStruct *qdmx, QDM_InterruptEvent intEvt) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + /* Check whether the QDM interrupt type is right. */ + QDM_ASSERT_PARAM(IsQDMInterruptEvent(intEvt)); + return ((qdmx->QINTSTS.reg & (unsigned int)intEvt) == intEvt); +} + +/** + * @brief Clear the specific interrupt flag. + * @param qdmx QDM register base address. + * @param intEvt Interrupt event. + * @retval None. + */ +static inline void DCL_QDM_ClearInterrupt(QDM_RegStruct *qdmx, QDM_InterruptEvent intEvt) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + /* Check whether the QDM interrupt type is right. */ + QDM_PARAM_CHECK_NO_RET(IsQDMInterruptEvent(intEvt)); + qdmx->QINTRAW.reg |= (unsigned int)intEvt; +} + +/** + * @brief Force a specific interrupt. + * @param qdmx QDM register base address. + * @param intEvt Interrupt event. + * @retval None. + */ +static inline void DCL_QDM_ForceInterrupt(QDM_RegStruct *qdmx, QDM_InterruptEvent intEvt) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + /* Check whether the QDM interrupt type is right. */ + QDM_PARAM_CHECK_NO_RET(IsQDMInterruptEvent(intEvt)); + qdmx->QINTINJ.reg |= (unsigned int)intEvt; +} + +/** + * @brief Enable speed lost raw interrupt. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_EnableSpedLstRaw(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QINTRAW.BIT.sped_lst_raw = BASE_CFG_ENABLE; +} + +/** + * @brief Enable PTU period raw interrupt. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_EnableUtmrPrdRaw(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QINTRAW.BIT.utmr_prd_raw = BASE_CFG_ENABLE; +} + +/** + * @brief Set the event status. + * @param qdmx QDM register base address. + * @retval None. + */ +static inline void DCL_QDM_SetCevtSts(QDM_RegStruct *qdmx, unsigned int status) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + qdmx->QDMSTS.BIT.cevt_sts = status; +} + +/** + * @brief Get the event status. + * @param qdmx QDM register base address. + * @retval unsigned int Value of cevt_sts. + */ +static inline unsigned int DCL_QDM_GetCevtSts(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return qdmx->QDMSTS.BIT.cevt_sts; +} + +/** + * @brief Get TSU overflow status. + * @param qdmx QDM register base address. + * @retval unsigned int Value of qctmr_ovf_sts. + */ +static inline unsigned int DCL_QDM_GetQctmrOvfSts(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return qdmx->QDMSTS.BIT.qctmr_ovf_sts; +} + +/** + * @brief Get quadrature direction status. + * @param qdmx QDM register base address. + * @retval unsigned int Value of qdir_sts. + */ +static inline unsigned int DCL_QDM_GetQdirSts(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return qdmx->QDMSTS.BIT.qdir_sts; +} + +/** + * @brief Get the direction error status. + * @param qdmx QDM register base address. + * @retval unsigned int Value of qcdr_err_sts. + */ +static inline unsigned int DCL_QDM_GetQcdrErrSts(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return qdmx->QDMSTS.BIT.qcdr_err_sts; +} + +/** + * @brief Get the position counter active compare value. + * @param qdmx QDM register base address. + * @retval unsigned int Value of qposcmpa. + */ +static inline unsigned int DCL_QDM_GetPositionCompareValue(QDM_RegStruct *qdmx) +{ + QDM_ASSERT_PARAM(IsQDMInstance(qdmx)); + return qdmx->QPOSCMPA; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_QDM_IP_H */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/qdm/src/qdm.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/qdm/src/qdm.c new file mode 100644 index 00000000..5c0083d4 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/qdm/src/qdm.c @@ -0,0 +1,550 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file qdm.c + * @author MCU Driver Team. + * @brief QDM HAL level module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the QDM. + * + Initialization and de-initialization functions. + * + Qdm Module Control functions. + * + Speed measure use M function. + * + Stall condition detection. + */ +#include "qdm.h" +#include "interrupt.h" + +#define QDM_INT_MASK 0x38 +/** + * @brief Set Decoder configurations + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void QDM_DecoderConfig(QDM_Handle *qdmHandle) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + QDM_PARAM_CHECK_NO_RET(IsDecodeMode(qdmHandle->ctrlConfig.decoderMode)); + QDM_PARAM_CHECK_NO_RET(IsSwap(qdmHandle->ctrlConfig.swap)); + QDM_PARAM_CHECK_NO_RET(IsResolution(qdmHandle->ctrlConfig.resolution)); + QDM_PARAM_CHECK_NO_RET(IsTrgLockMode(qdmHandle->ctrlConfig.trgLockMode)); + QDM_PARAM_CHECK_NO_RET(IsPtuMode(qdmHandle->ctrlConfig.ptuMode)); + + /* input mode setting */ + qdmHandle->baseAddress->QCTRL.BIT.qdu_mode = qdmHandle->ctrlConfig.decoderMode; + /* swap */ + qdmHandle->baseAddress->QCTRL.BIT.qdm_ab_swap = qdmHandle->ctrlConfig.swap; + /* qdm xclk */ + qdmHandle->baseAddress->QCTRL.BIT.qdu_xclk = qdmHandle->ctrlConfig.resolution; + /* polarity */ + /* bit0: A input polarity, bit value: 0--direct input, 1--invert input */ + qdmHandle->baseAddress->QCTRL.BIT.qdma_polarity = (qdmHandle->ctrlConfig.polarity & 0x01); + /* bit1: B input polarity, bit value: 0--direct input, 1--invert input */ + qdmHandle->baseAddress->QCTRL.BIT.qdmb_polarity = ((qdmHandle->ctrlConfig.polarity >> 1) & 0x01); + /* bit2: index input polarity, bit value: 0--direct input, 1--invert input */ + qdmHandle->baseAddress->QCTRL.BIT.qdmi_polarity = ((qdmHandle->ctrlConfig.polarity >> 2) & 0x01); + /* lock mode */ + qdmHandle->baseAddress->QCTRL.BIT.qtrg_lock_mode = qdmHandle->ctrlConfig.trgLockMode; + /* ptu mode */ + qdmHandle->baseAddress->QCTRL.BIT.ptu_mode = qdmHandle->ctrlConfig.ptuMode; +} + +/** + * @brief Set counter configurations + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void QDM_CounterConfig(QDM_Handle *qdmHandle) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + QDM_PARAM_CHECK_NO_RET(IsPcntMode(qdmHandle->pcntMode)); + QDM_PARAM_CHECK_NO_RET(IsPcntRstMode(qdmHandle->pcntRstMode)); + QDM_PARAM_CHECK_NO_RET(IsPcntIdxInitMode(qdmHandle->pcntIdxInitMode)); + QDM_PARAM_CHECK_NO_RET(IsTsuPrescaler(qdmHandle->tsuPrescaler)); + QDM_PARAM_CHECK_NO_RET(IsCevtPrescaler(qdmHandle->cevtPrescaler)); + + /* set pcnt mode */ + qdmHandle->baseAddress->QPPUCTRL.BIT.pcnt_mode = qdmHandle->pcntMode; + qdmHandle->baseAddress->QPPUCTRL.BIT.pcnt_rst_mode = qdmHandle->pcntRstMode; + qdmHandle->baseAddress->QPPUCTRL.BIT.pcnt_idx_init_mode = qdmHandle->pcntIdxInitMode; + /* set TSU */ + qdmHandle->baseAddress->QTSUCTRL.BIT.tsu_prescaler = qdmHandle->tsuPrescaler; + qdmHandle->baseAddress->QTSUCTRL.BIT.cevt_prescaler = qdmHandle->cevtPrescaler; + /* set init value */ + qdmHandle->baseAddress->QPOSINIT = qdmHandle->posInit; + /* set count max value */ + qdmHandle->baseAddress->QPOSMAX = qdmHandle->posMax; + qdmHandle->baseAddress->QUPRD = qdmHandle->period; + qdmHandle->baseAddress->QCMAX = qdmHandle->qcMax; +} + +/** + * @brief enable submodules + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void QDM_EnableSubmodule(QDM_Handle *qdmHandle) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + if (qdmHandle->subModeEn == true) { + qdmHandle->baseAddress->QCTRL.BIT.ppu_en = BASE_CFG_ENABLE; + qdmHandle->baseAddress->QCTRL.BIT.ptu_en = BASE_CFG_ENABLE; + qdmHandle->baseAddress->QCTRL.BIT.tsu_en = BASE_CFG_ENABLE; + } +} + +/** + * @brief enable interrupt + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void QDM_InterruptEnable(QDM_Handle *qdmHandle) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + qdmHandle->baseAddress->QINTENA.reg = qdmHandle->interruptEn; +} + +/** + * @brief Speed lose interrupt. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void SpeedLose(QDM_Handle *qdmHandle) +{ + if (qdmHandle->userCallBack.SpeedLoseCallback != NULL) { + qdmHandle->userCallBack.SpeedLoseCallback(qdmHandle); + } +} + +/** + * @brief QDM Z index lock interrupt. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void ZIndexLock(QDM_Handle *qdmHandle) +{ + if (qdmHandle->userCallBack.ZIndexLockedCallBack != NULL) { + qdmHandle->userCallBack.ZIndexLockedCallBack(qdmHandle); + } +} + +/** + * @brief Orthogonal direction change interrupt. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void OrthoDirChange(QDM_Handle *qdmHandle) +{ + if (qdmHandle->userCallBack.OrthogonalDirectionChangeCallBack != NULL) { + qdmHandle->userCallBack.OrthogonalDirectionChangeCallBack(qdmHandle); + } +} + +/** + * @brief Orthogonal phase error interrupt. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void OrthoPhaseErr(QDM_Handle *qdmHandle) +{ + if (qdmHandle->userCallBack.OrthogonalPhaseErrorCallBack != NULL) { + qdmHandle->userCallBack.OrthogonalPhaseErrorCallBack(qdmHandle); + } +} + +/** + * @brief Position compare match interrupt. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void PosCompareMatch(QDM_Handle *qdmHandle) +{ + if (qdmHandle->userCallBack.PositionCompareMatchCallBack != NULL) { + qdmHandle->userCallBack.PositionCompareMatchCallBack(qdmHandle); + } +} + +/** + * @brief Position compare ready interrupt. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void PosCompareReady(QDM_Handle *qdmHandle) +{ + if (qdmHandle->userCallBack.PositionCompareReadyCallBack != NULL) { + qdmHandle->userCallBack.PositionCompareReadyCallBack(qdmHandle); + } +} + +/** + * @brief Position counter error interrupt. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void PosCounterErr(QDM_Handle *qdmHandle) +{ + if (qdmHandle->userCallBack.PositionCounterErrorCallBack != NULL) { + qdmHandle->userCallBack.PositionCounterErrorCallBack(qdmHandle); + } +} + +/** + * @brief Position counter overflow interrupt. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void PosCounterOverflow(QDM_Handle *qdmHandle) +{ + if (qdmHandle->userCallBack.PositionCounterOverflowCallBack != NULL) { + qdmHandle->userCallBack.PositionCounterOverflowCallBack(qdmHandle); + } +} + +/** + * @brief Position counter underflow interrupt. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void PosCounterUnderflow(QDM_Handle *qdmHandle) +{ + if (qdmHandle->userCallBack.PositionCounterUnderflowCallBack != NULL) { + qdmHandle->userCallBack.PositionCounterUnderflowCallBack(qdmHandle); + } +} + +/** + * @brief Other interrupt callback function. + * @param qdmHandle Value of @ref QDM_Handle. + * @param qinsts: Interrupt status register. + * @retval None + */ +static void OtherInterruptCallBack(QDM_Handle *qdmHandle, QDM_QINTSTS_REG qinsts) +{ + if (qinsts.BIT.qphs_err_int == BASE_CFG_SET) { + /* Orthogonal phase error interrupt. */ + OrthoPhaseErr(qdmHandle); + qdmHandle->baseAddress->QINTRAW.BIT.qphs_err_raw = BASE_CFG_ENABLE; + } + if (qinsts.BIT.pcnt_cpm_int == BASE_CFG_SET) { + /* Position compare match interrupt. */ + PosCompareMatch(qdmHandle); + qdmHandle->baseAddress->QINTRAW.BIT.pcnt_cpm_raw = BASE_CFG_ENABLE; + } + if (qinsts.BIT.pcnt_cpr_int == BASE_CFG_SET) { + /* Position compare ready interrupt. */ + PosCompareReady(qdmHandle); + qdmHandle->baseAddress->QINTRAW.BIT.pcnt_cpr_raw = BASE_CFG_ENABLE; + } + if (qinsts.BIT.pcnt_err_int == BASE_CFG_SET) { + /* Position counter error interrupt. */ + PosCounterErr(qdmHandle); + qdmHandle->baseAddress->QINTRAW.BIT.pcnt_err_raw = BASE_CFG_ENABLE; + } + if (qinsts.BIT.pcnt_ovf_int == BASE_CFG_SET) { + /* Position counter overflow interrupt. */ + PosCounterOverflow(qdmHandle); + qdmHandle->baseAddress->QINTRAW.BIT.pcnt_ovf_raw = BASE_CFG_ENABLE; + } + if (qinsts.BIT.pcnt_udf_int == BASE_CFG_SET) { + /* Position counter underflow interrupt. */ + PosCounterUnderflow(qdmHandle); + qdmHandle->baseAddress->QINTRAW.BIT.pcnt_udf_raw = BASE_CFG_ENABLE; + } +} + +/** + * @brief M-method speed calculation. + * @param qdmHandle Value of @ref QDM_Handle. + * @retval None + */ +static void CalculateSpeed(QDM_Handle *qdmHandle) +{ + unsigned int deltaValue, tmp, intFlag; + /* Last QPOSLOCK value */ + static unsigned int lastPoslockValue = 0; + int speed; + deltaValue = qdmHandle->baseAddress->QPOSLOCK; + /* The position count reset mode is overflow reset. */ + intFlag = (qdmHandle->baseAddress->QINTSTS.reg & QDM_INT_MASK); + if ((qdmHandle->pcntRstMode == QDM_PCNT_RST_OVF) && (intFlag == 0)) { + deltaValue = qdmHandle->baseAddress->QPOSLOCK - lastPoslockValue; + } + lastPoslockValue = qdmHandle->baseAddress->QPOSLOCK; + if (qdmHandle->baseAddress->QDMSTS.BIT.qdir_sts == 1) { /* forward */ + tmp = deltaValue >> qdmHandle->baseAddress->QCTRL.BIT.qdu_xclk; + speed = ((tmp * SECONDS_PER_MINUTES) / qdmHandle->motorLineNum) \ + * (BASE_FUNC_GetCpuFreqHz() / qdmHandle->period); + qdmHandle->speedRpm = speed; + } else { /* reverse */ + tmp = (qdmHandle->posMax - deltaValue) >> qdmHandle->baseAddress->QCTRL.BIT.qdu_xclk; + speed = ((tmp * SECONDS_PER_MINUTES) / qdmHandle->motorLineNum) \ + * (BASE_FUNC_GetCpuFreqHz() / qdmHandle->period); + qdmHandle->speedRpm = -speed; + } +} + +/** + * @brief IRQ Handler + * @param handle: QDM handle. + * @retval None + */ +void HAL_QDM_IrqHandler(void *handle) +{ + QDM_ASSERT_PARAM(handle != NULL); + QDM_Handle *qdmHandle = (QDM_Handle *)handle; + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + + if (qdmHandle->motorLineNum == 0 || qdmHandle->period == 0) { + /* clear interrupt */ + qdmHandle->baseAddress->QINTRAW.BIT.sped_lst_raw = BASE_CFG_ENABLE; + qdmHandle->baseAddress->QINTRAW.BIT.utmr_prd_raw = BASE_CFG_ENABLE; + return; + } + + QDM_QINTSTS_REG qinsts = qdmHandle->baseAddress->QINTSTS; + if (qinsts.BIT.utmr_prd_int == BASE_CFG_SET) { + CalculateSpeed(qdmHandle); + /* PTU timer cycle triggle interrupt */ + if (qdmHandle->userCallBack.PtuCycleTrgCallback != NULL) { + qdmHandle->userCallBack.PtuCycleTrgCallback(qdmHandle); + } + qdmHandle->baseAddress->QINTRAW.BIT.utmr_prd_raw = BASE_CFG_ENABLE; + } + if (qinsts.BIT.sped_lst_int == BASE_CFG_SET) { + /* speed lose interrupt */ + SpeedLose(qdmHandle); + qdmHandle->baseAddress->QINTRAW.BIT.sped_lst_raw = BASE_CFG_ENABLE; + } + if (qinsts.BIT.indx_lck_int == BASE_CFG_SET) { + /* QDM Z index lock interrupt. */ + ZIndexLock(qdmHandle); + qdmHandle->baseAddress->QINTRAW.BIT.indx_lck_raw = BASE_CFG_ENABLE; + } + if (qinsts.BIT.qdir_chg_int == BASE_CFG_SET) { + /* Orthogonal direction change interrupt. */ + OrthoDirChange(qdmHandle); + qdmHandle->baseAddress->QINTRAW.BIT.qdir_chg_raw = BASE_CFG_ENABLE; + } + OtherInterruptCallBack(qdmHandle, qinsts); + return; +} + +/** + * @brief Select the interrupt callback function by the switch-case. + * @param qdmHandle Value of @ref QDM_Handle. + * @param typeId: Interrupt type. + * @param pCallBack: Interrupt callback function. + * @retval None + */ +static void SelectInterruptCallback(QDM_Handle *qdmHandle, QDM_CallbackFuncType typeID, QDM_CallbackType pCallback) +{ + switch (typeID) { + case QDM_TSU_CYCLE: + /* PTU timer cycle triggle interrupt. */ + qdmHandle->userCallBack.PtuCycleTrgCallback = pCallback; + break; + case QDM_SPEED_LOSE: + /* Speed lose interrupt. */ + qdmHandle->userCallBack.SpeedLoseCallback = pCallback; + break; + case QDM_INDEX_LOCKED: + /* QDM Z index lock interrupt. */ + qdmHandle->userCallBack.ZIndexLockedCallBack = pCallback; + break; + case QDM_DIR_CHANGE: + /* Orthogonal direction change interrupt. */ + qdmHandle->userCallBack.OrthogonalDirectionChangeCallBack = pCallback; + break; + case QDM_PHASE_ERROR: + /* Orthogonal phase error interrupt. */ + qdmHandle->userCallBack.OrthogonalPhaseErrorCallBack = pCallback; + break; + case QDM_POS_MATCH: + /* Position compare match interrupt. */ + qdmHandle->userCallBack.PositionCompareMatchCallBack = pCallback; + break; + case QDM_POS_READY: + /* Position compare ready interrupt. */ + qdmHandle->userCallBack.PositionCompareReadyCallBack = pCallback; + break; + case QDM_POS_CNT_ERROR: + /* Position counter error interrupt. */ + qdmHandle->userCallBack.PositionCounterErrorCallBack = pCallback; + break; + case QDM_POS_CNT_OVERFLOW: + /* Position counter overflow interrupt. */ + qdmHandle->userCallBack.PositionCounterOverflowCallBack = pCallback; + break; + case QDM_POS_CNT_UNDERFLOW: + /* Position counter underflow interrupt. */ + qdmHandle->userCallBack.PositionCounterUnderflowCallBack = pCallback; + break; + default: + return; + } +} + +/** + * @brief Register IRQ callback functions + * @param qdmHandle Value of @ref QDM_Handle. + * @param typeID: callback function type ID. + * @param pCallback: pointer of callback function. + * @retval None + */ +void HAL_QDM_RegisterCallback(QDM_Handle *qdmHandle, QDM_CallbackFuncType typeID, QDM_CallbackType pCallback) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(pCallback != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + /* Select the interrupt callback function by the switch-case. */ + SelectInterruptCallback(qdmHandle, typeID, pCallback); +} + +/** + * @brief QDM initialization functions + * @param qdmHandle Value of @ref QDM_Handle. + * @retval BASE_StatusType:BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT + */ +BASE_StatusType HAL_QDM_Init(QDM_Handle *qdmHandle) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + QDM_PARAM_CHECK_WITH_RET(IsEmuMode(qdmHandle->emuMode), BASE_STATUS_ERROR); + QDM_PARAM_CHECK_WITH_RET(IsLockMode(qdmHandle->lock_mode), BASE_STATUS_ERROR); + + qdmHandle->baseAddress->QEMUMODE.BIT.emu_mode = qdmHandle->emuMode; + /* Set Z index locked mode. */ + if ((qdmHandle->interruptEn & QDM_INT_INDEX_EVNT_LATCH) == QDM_INT_INDEX_EVNT_LATCH) { + DCL_QDM_SetIndexLockMode(qdmHandle->baseAddress, qdmHandle->lock_mode); + } + /* Set input filter width. */ + DCL_QDM_SetInputFilterWidth(qdmHandle->baseAddress, qdmHandle->inputFilter.qdmAFilterLevel, \ + qdmHandle->inputFilter.qdmBFilterLevel, qdmHandle->inputFilter.qdmZFilterLevel); + QDM_DecoderConfig(qdmHandle); + QDM_CounterConfig(qdmHandle); + /* Enable interrupt. */ + QDM_InterruptEnable(qdmHandle); + QDM_EnableSubmodule(qdmHandle); + return BASE_STATUS_OK; +} + +/** + * @brief QDM deinitialization functions + * @param qdmHandle Value of @ref QDM_Handle. + * @retval BASE_StatusType:BASE_STATUS_OK, BASE_STATUS_ERROR, BASE_STATUS_BUSY, BASE_STATUS_TIMEOUT + */ +BASE_StatusType HAL_QDM_DeInit(QDM_Handle *qdmHandle) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + /* Clear QDM interrupt callback functions. */ + qdmHandle->userCallBack.PtuCycleTrgCallback = NULL; + qdmHandle->userCallBack.SpeedLoseCallback = NULL; + + /* Disable interrupt. */ + qdmHandle->baseAddress->QINTENA.reg = BASE_CFG_DISABLE; + /* Disable submodules. */ + qdmHandle->baseAddress->QCTRL.BIT.ppu_en = BASE_CFG_DISABLE; + qdmHandle->baseAddress->QCTRL.BIT.ptu_en = BASE_CFG_DISABLE; + qdmHandle->baseAddress->QCTRL.BIT.tsu_en = BASE_CFG_DISABLE; + return BASE_STATUS_OK; +} + +/** + * @brief read position count register value and direct + * @param qdmHandle Value of @ref QDM_Handle. + * @param count: count value pointer. + * @param dir: dir. + * @retval none. + */ +void HAL_QDM_ReadPosCountAndDir(const QDM_Handle *qdmHandle, unsigned int *count, unsigned int *dir) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(count != NULL); + QDM_ASSERT_PARAM(dir != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + *count = qdmHandle->baseAddress->QPOSCNT; + *dir = qdmHandle->baseAddress->QDMSTS.BIT.qdir_sts; + + return; +} + +/** + * @brief get phase error status. + * @param qdmHandle Value of @ref QDM_Handle. + * @param errStatus: phase error status. + * @retval none. + */ +void HAL_QDM_GetPhaseErrorStatus(const QDM_Handle *qdmHandle, unsigned int *errStatus) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(errStatus != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + *errStatus = qdmHandle->baseAddress->QDMSTS.BIT.qcdr_err_sts; + + return; +} + +/** + * @brief Get motor speed use M method + * @param qdmHandle Value of @ref QDM_Handle. + * @retval int: motor's speed + */ +int HAL_QDM_GetSpeedRpmM(QDM_Handle *qdmHandle) +{ + QDM_ASSERT_PARAM(qdmHandle != NULL); + return qdmHandle->speedRpm; +} + +/** + * @brief Get motor speed use MT method + * @param qdmHandle Value of @ref QDM_Handle. + * @retval int: motor's speed + */ +int HAL_QDM_GetSpeedRpmMT(QDM_Handle *qdmHandle) +{ + int rpm; + unsigned int utime; + unsigned int tmp; + + QDM_ASSERT_PARAM(qdmHandle != NULL); + QDM_ASSERT_PARAM(IsQDMInstance(qdmHandle->baseAddress)); + QDM_ASSERT_PARAM(qdmHandle->motorLineNum != 0); + qdmHandle->baseAddress->QDMSTS.BIT.cevt_sts = BASE_CFG_SET; /* clear cevt status bit */ + while (qdmHandle->baseAddress->QDMSTS.BIT.cevt_sts != BASE_CFG_SET) { + ; + } + if (qdmHandle->baseAddress->QDMSTS.BIT.qctmr_ovf_sts == BASE_CFG_SET) { + qdmHandle->baseAddress->QDMSTS.reg = BASE_CFG_SET; /* clear qctmr overflow status */ + return 0; + } + utime = BASE_FUNC_GetCpuFreqHz() / qdmHandle->motorLineNum; + tmp = utime << qdmHandle->baseAddress->QTSUCTRL.BIT.cevt_prescaler \ + >> qdmHandle->baseAddress->QTSUCTRL.BIT.tsu_prescaler >> qdmHandle->baseAddress->QCTRL.BIT.qdu_xclk; + rpm = tmp * SECONDS_PER_MINUTES / qdmHandle->baseAddress->QCPRD; + + if (qdmHandle->baseAddress->QDMSTS.BIT.qdir_sts == BASE_CFG_SET) { + qdmHandle->speedRpm = rpm; + } else { + qdmHandle->speedRpm = -rpm; + } + + return qdmHandle->speedRpm; +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/spi/common/inc/spi.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/spi/common/inc/spi.h new file mode 100644 index 00000000..f6c8ef2f --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/spi/common/inc/spi.h @@ -0,0 +1,188 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file spi.h + * @author MCU Driver Team + * @brief SPI module driver. + * @details This file provides firmware functions to manage the following. + * functionalities of the SPI. + * + Initialization and de-initialization functions. + * + Peripheral transmit and receiving functions. + * + Enumerated definition of SPI basic parameter configuration. + */ +#ifndef McuMagicTag_SPI_H +#define McuMagicTag_SPI_H + +/* Includes ------------------------------------------------------------------*/ +#include "dma.h" +#include "spi_ip.h" + +/** + * @defgroup SPI SPI + * @brief SPI module. + * @{ + */ + + /** + * @defgroup SPI_Common SPI Common + * @brief SPI common external module. + * @{ + */ + +/* Macro definitions ---------------------------------------------------------*/ + +/* Definition of the chip selection configuration macro */ +#define SPI_CHIP_DESELECT 0 +#define SPI_CHIP_SELECT 1 + +/* Definition of the chip selection mode selection macro */ +#define SPI_CHIP_SELECT_MODE_INTERNAL 0 +#define SPI_CHIP_SELECT_MODE_CALLBACK 1 + +/** + * @defgroup SPI_Handle_Definition SPI Handle Definition + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ +/** + * @brief Callback Function ID Enumeration Definition. + */ +typedef enum { + SPI_TX_COMPLETE_CB_ID = 0x00000000U, + SPI_RX_COMPLETE_CB_ID = 0x00000001U, + SPI_TX_RX_COMPLETE_CB_ID = 0x00000002U, + SPI_ERROR_CB_ID = 0x00000003U, + SPI_CS_CB_ID = 0x00000004U +} HAL_SPI_CallbackID; + +/** + * @brief Module Status Enumeration Definition. + */ +typedef enum { + HAL_SPI_STATE_RESET = 0x00000000U, /**< Peripheral not Initialized */ + HAL_SPI_STATE_READY = 0x00000001U, /**< Peripheral Initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x00000002U, /**< An internal process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x00000003U, /**< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x00000004U, /**< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x00000005U, /**< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x00000006U, /**< SPI error state */ + HAL_SPI_STATE_ABORT = 0x00000007U /**< SPI abort is ongoing */ +} HAL_SPI_State; + +/** + * @brief Module handle structure definition. + */ +typedef struct _SPI_Handle { + SPI_RegStruct *baseAddress; /**< Register base address. */ + + unsigned int mode; /**< See HAL_SPI_Mode. */ + unsigned int csMode; /**< SPI_CHIP_SELECT_MODE_INTERNAL or SPI_CHIP_SELECT_MODE_CALLBACK. */ + unsigned int xFerMode; /**< See HAL_SPI_XferMode. */ + unsigned int clkPolarity; /**< See HAL_SPI_ClkPol. */ + unsigned int clkPhase; /**< See HAL_SPI_ClkPha. */ + unsigned int endian; /**< See HAL_SPI_Endian. */ + unsigned int frameFormat; /**< See HAL_SPI_FrameMode. */ + unsigned int dataWidth; /**< See HAL_SPI_DataWidth. */ + unsigned char freqScr; /**< Frequency scr, value range: 0 to 255. */ + unsigned char freqCpsdvsr; /**< Frequency Cpsdvsr, an even number ranging from 0 to 254. */ + unsigned char waitVal; /**< Number of beats waiting between write and read in National + Microwire frame format. */ + bool waitEn; /**< SPI Microwire waiting enable. */ + unsigned int txIntSize; /**< TX interrupt transmission threshold. */ + unsigned int rxIntSize; /**< RX interrupt transmission threshold. */ + + unsigned int txDMABurstSize; /**< TX DMA transmission threshold. */ + unsigned int rxDMABurstSize; /**< RX DMA transmission threshold. */ + DMA_Handle *dmaHandle; /**< SPI_DMA control handle*/ + unsigned int txDmaCh; /**< SPI DMA tx channel */ + unsigned int rxDmaCh; /**< SPI DMA rx channel */ + + unsigned int csCtrl; /**< Chip select status. */ + unsigned char *rxBuff; /**< Rx buffer pointer address. */ + unsigned char *txBuff; /**< Tx buffer pointer address. */ + unsigned int transferSize; /**< Total length of transmitted data. */ + unsigned int txCount; /**< Tx Length of data transferred. */ + unsigned int rxCount; /**< Rx Length of data transferred. */ + + HAL_SPI_State state; /**< Running Status. */ + BASE_StatusType errorCode; /**< Error Code. */ + SPI_UserCallBack userCallBack; /**< User callback. */ + SPI_ExtendHandle handleEx; /**< SPI extend parameter. */ +} SPI_Handle; +/** + * @} + */ + +/** + * @brief Callback Function Type Definition. + */ +typedef void (* SPI_CallbackFuncType)(void *handle); + +/** + * @defgroup SPI_API_Declaration SPI HAL API + * @{ + */ + +BASE_StatusType HAL_SPI_Init(SPI_Handle *handle); +BASE_StatusType HAL_SPI_Deinit(SPI_Handle *handle); +BASE_StatusType HAL_SPI_ConfigParameter(SPI_Handle *handle); +BASE_StatusType HAL_SPI_RegisterCallback(SPI_Handle *handle, + HAL_SPI_CallbackID callbackID, + SPI_CallbackFuncType pcallback); +BASE_StatusType HAL_SPI_ReadBlocking(SPI_Handle *handle, + unsigned char *rData, + unsigned int dataSize, + unsigned int timeout); +BASE_StatusType HAL_SPI_WriteBlocking(SPI_Handle *handle, + unsigned char *wData, + unsigned int dataSize, + unsigned int timeout); +BASE_StatusType HAL_SPI_WriteReadBlocking(SPI_Handle *handle, + unsigned char *rData, + unsigned char *wData, + unsigned int dataSize, + unsigned int timeout); +BASE_StatusType HAL_SPI_ReadIT(SPI_Handle *handle, unsigned char *rData, unsigned int dataSize); +BASE_StatusType HAL_SPI_WriteIT(SPI_Handle *handle, unsigned char *wData, unsigned int dataSize); +BASE_StatusType HAL_SPI_WriteReadIT(SPI_Handle *handle, + unsigned char *rData, + unsigned char *wData, + unsigned int dataSizeout); +BASE_StatusType HAL_SPI_ReadDMA(SPI_Handle *handle, unsigned char *rData, unsigned int dataSize); +BASE_StatusType HAL_SPI_WriteDMA(SPI_Handle *handle, unsigned char *wData, unsigned int dataSize); +BASE_StatusType HAL_SPI_WriteReadDMA(SPI_Handle *handle, + unsigned char *rData, + unsigned char *wData, + unsigned int dataSizeout); +BASE_StatusType HAL_SPI_DMAStop(SPI_Handle *handle); +BASE_StatusType HAL_SPI_ChipSelectChannelSet(SPI_Handle *handle, SPI_ChipSelectChannel channel); +BASE_StatusType HAL_SPI_ChipSelectChannelGet(SPI_Handle *handle, SPI_ChipSelectChannel *channel); +void HAL_SPI_IrqHandler(void *handle); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* #ifndef McuMagicTag_SPI_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/spi/inc/spi_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/spi/inc/spi_ip.h new file mode 100644 index 00000000..01f85382 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/spi/inc/spi_ip.h @@ -0,0 +1,1213 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file spi_ip.h + * @author MCU Driver Team. + * @brief SPI module driver. + * @details This file provides firmware functions to manage the following. + * functionalities of the SPI. + * + Definition of SPI configuration parameters. + * + Register definition structure. + * + Direct configuration layer interface. + * + Parameter check inline function. + */ +#ifndef McuMagicTag_SPI_IP_H +#define McuMagicTag_SPI_IP_H + +/* Includes ------------------------------------------------------------------*/ +#include "baseinc.h" +#ifdef SPI_PARAM_CHECK +#define SPI_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define SPI_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define SPI_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define SPI_ASSERT_PARAM(para) ((void)0U) +#define SPI_PARAM_CHECK_NO_RET(para) ((void)0U) +#define SPI_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +/** + * @addtogroup SPI + * @{ + */ + +/** + * @defgroup SPI_IP SPI_IP + * @brief SPI_IP: spi_v0 + * @{ + */ + +#define SPI_CR0_SCR_POS 8 +#define SPI_CR0_SCR_MASK (0xFF << SPI_CR0_SCR_POS) + +/** + * @defgroup SPI_Param_Def SPI Parameters Definition + * @brief Definition of SPI configuration parameters. + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ +/** + * @brief Master and Slave Device Enumeration Definition. + */ +typedef enum { + HAL_SPI_MASTER = 0x00000000U, + HAL_SPI_SLAVE = 0x00000001U +} HAL_SPI_Mode; + +/** + * @brief Clock Polarity Enumeration Definition. + */ +typedef enum { + HAL_SPI_CLKPOL_0 = 0x00000000U, + HAL_SPI_CLKPOL_1 = 0x00000001U +} HAL_SPI_ClkPol; + +/** + * @brief Clock Phase Enumeration Definition. + */ +typedef enum { + HAL_SPI_CLKPHA_0 = 0x00000000U, + HAL_SPI_CLKPHA_1 = 0x00000001U +} HAL_SPI_ClkPha; + +/** + * @brief Enumeration definition of data endian. + */ +typedef enum { + HAL_SPI_BIG_ENDIAN = 0x00000000U, + HAL_SPI_LITTILE_ENDIAN = 0x00000001U +} HAL_SPI_Endian; + +/** + * @brief Enumerated definition of data frame mode selection. + */ +typedef enum { + HAL_SPI_MODE_MOTOROLA = 0x00000000U, + HAL_SPI_MODE_TI = 0x00000001U, + HAL_SPI_MODE_MICROWIRE = 0x00000002U +} HAL_SPI_FrameMode; + +/** + * @brief Transmission Mode Selection Enumeration Definition. + */ +typedef enum { + HAL_XFER_MODE_BLOCKING = 0x00000000U, + HAL_XFER_MODE_INTERRUPTS = 0x00000001U, + HAL_XFER_MODE_DMA = 0x00000002U +} HAL_SPI_XferMode; + +/** + * @brief Data Bit Width Enumeration Definition. + */ +typedef enum { + SPI_DATA_WIDTH_4BIT = 0x00000003U, + SPI_DATA_WIDTH_5BIT = 0x00000004U, + SPI_DATA_WIDTH_6BIT = 0x00000005U, + SPI_DATA_WIDTH_7BIT = 0x00000006U, + SPI_DATA_WIDTH_8BIT = 0x00000007U, + SPI_DATA_WIDTH_9BIT = 0x00000008U, + SPI_DATA_WIDTH_10BIT = 0x00000009U, + SPI_DATA_WIDTH_11BIT = 0x0000000aU, + SPI_DATA_WIDTH_12BIT = 0x0000000bU, + SPI_DATA_WIDTH_13BIT = 0x0000000cU, + SPI_DATA_WIDTH_14BIT = 0x0000000dU, + SPI_DATA_WIDTH_15BIT = 0x0000000eU, + SPI_DATA_WIDTH_16BIT = 0x0000000fU +} HAL_SPI_DataWidth; + +/** + * @brief Definitions of available parameters for interrupt Tx thresholds. + */ +typedef enum { + SPI_TX_INTERRUPT_SIZE_1 = 0x00000000U, + SPI_TX_INTERRUPT_SIZE_4 = 0x00000001U, + SPI_TX_INTERRUPT_SIZE_8 = 0x00000002U, + SPI_TX_INTERRUPT_SIZE_16 = 0x00000003U, + SPI_TX_INTERRUPT_SIZE_32 = 0x00000004U, + SPI_TX_INTERRUPT_SIZE_64 = 0x00000005U, + SPI_TX_INTERRUPT_SIZE_128_0 = 0x00000006U, + SPI_TX_INTERRUPT_SIZE_128_1 = 0x00000007U +} HAL_SPI_TxInterruptSize; + +/** + * @brief Definitions of available parameters for interrupt Rx thresholds. + */ +typedef enum { + SPI_RX_INTERRUPT_SIZE_1 = 0x00000000U, + SPI_RX_INTERRUPT_SIZE_4 = 0x00000001U, + SPI_RX_INTERRUPT_SIZE_8 = 0x00000002U, + SPI_RX_INTERRUPT_SIZE_16 = 0x00000003U, + SPI_RX_INTERRUPT_SIZE_32 = 0x00000004U, + SPI_RX_INTERRUPT_SIZE_64 = 0x00000005U, + SPI_RX_INTERRUPT_SIZE_128 = 0x00000006U, + SPI_RX_INTERRUPT_SIZE_192 = 0x00000007U +} HAL_SPI_RxInterruptSize; + +/** + * @brief Definitions of available parameters for DMA Tx thresholds. + */ +typedef enum { + SPI_TX_DMA_BURST_SIZE_1 = 0x00000000U, + SPI_TX_DMA_BURST_SIZE_4 = 0x00000001U, + SPI_TX_DMA_BURST_SIZE_8 = 0x00000002U, + SPI_TX_DMA_BURST_SIZE_16 = 0x00000003U, + SPI_TX_DMA_BURST_SIZE_32 = 0x00000004U, + SPI_TX_DMA_BURST_SIZE_64_0 = 0x00000005U, + SPI_TX_DMA_BURST_SIZE_64_1 = 0x00000006U, + SPI_TX_DMA_BURST_SIZE_64_2 = 0x00000007U +} HAL_SPI_TxDmaBurstSize; + +/** + * @brief Definitions of available parameters for DMA Rx thresholds. + */ +typedef enum { + SPI_RX_DMA_BURST_SIZE_1 = 0x00000000U, + SPI_RX_DMA_BURST_SIZE_4 = 0x00000001U, + SPI_RX_DMA_BURST_SIZE_8 = 0x00000002U, + SPI_RX_DMA_BURST_SIZE_16 = 0x00000003U, + SPI_RX_DMA_BURST_SIZE_32 = 0x00000004U, + SPI_RX_DMA_BURST_SIZE_64 = 0x00000005U, + SPI_RX_DMA_BURST_SIZE_96 = 0x00000006U, + SPI_RX_DMA_BURST_SIZE_128 = 0x00000007U +} HAL_SPI_RxDmaBurstSize; + +/** + * @brief Defines the SPI chip select channel. + */ +typedef enum { + SPI_CHIP_SELECT_CHANNEL_0 = 0x00000000U, + SPI_CHIP_SELECT_CHANNEL_1 = 0x00000001U, + SPI_CHIP_SELECT_CHANNEL_MAX = 0x00000002U +} SPI_ChipSelectChannel; + +/** + * @brief SPI extend handle. + */ +typedef struct _SPI_ExtendHandle { +} SPI_ExtendHandle; + +/** + * @brief SPI user callback. + */ +typedef struct { + /* Sending completion callback function */ + void (* TxCpltCallback)(void *handle); + /* Receive completion callback function */ + void (* RxCpltCallback)(void *handle); + /* Receive and Sending completion callback function */ + void (* TxRxCpltCallback)(void *handle); + /* Error callback function */ + void (* ErrorCallback)(void *handle); + /* CS callback function */ + void (* CsCtrlCallback)(void *handle); +} SPI_UserCallBack; +/** + * @} + */ + +/** + * @defgroup SPI_Reg_Def SPI Register Definition + * @brief register mapping structure + * @{ + */ +/* Register Description Definition----------------------------------- */ + +/** + * @brief SPI clock, polarity, phase, frame format, data bit control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int dss : 4; /**< data width. */ + unsigned int frf : 2; /**< frame format: Motorola TI Mircowire. */ + unsigned int spo : 1; /**< motorola polarity. */ + unsigned int sph : 1; /**< motorola phase. */ + unsigned int scr : 8; /**< serial clock rate. */ + unsigned int reserved0 : 16; + } BIT; +} volatile SPICR0_REG; + +/** + * @brief SPI parameter control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int lbm : 1; /**< loopback mode enable. */ + unsigned int sse : 1; /**< SPI enable. */ + unsigned int ms : 1; /**< Master or Salve mode. */ + unsigned int reserved0 : 1; + unsigned int bitend : 1; /**< set the endian mode. */ + unsigned int reserved1 : 1; + unsigned int mode_altasens : 1; /**< chip select signal. */ + unsigned int reserved2 : 1; + unsigned int waitval : 7; /**< Microwire wait time. */ + unsigned int waiten : 1; /**< Microwire wait enable. */ + unsigned int reserved3 : 16; + } BIT; +} volatile SPICR1_REG; + +/** + * @brief SPI data FIFO register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int data : 16; /**< send and receive FIFO. */ + unsigned int reserved0 : 16; + } BIT; +} volatile SPIDR_REG; + +/** + * @brief SPI status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int tfe : 1; /**< tx FIFO empty flag. */ + unsigned int tnf : 1; /**< tx FIFO not full flag. */ + unsigned int rne : 1; /**< rx FIFO not empty flag. */ + unsigned int rff : 1; /**< rx FIFO full flag. */ + unsigned int bsy : 1; /**< SPI busy flag. */ + unsigned int reserved0 : 27; + } BIT; +} volatile SPISR_REG; + +/** + * @brief SPI clock divider register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cpsdvsr : 8; /**< clock divider value, value is even number between 2 and 254. */ + unsigned int reserved0 : 24; + } BIT; +} volatile SPICPSR_REG; + +/** + * @brief SPI interrupt mask control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rorim : 1; /**< rx overflow interrupt mask. */ + unsigned int rtim : 1; /**< rx timeout interrupt mask. */ + unsigned int rxim : 1; /**< rx FIFO interrupt mask. */ + unsigned int txim : 1; /**< tx FIFO interrupt mask. */ + unsigned int reserved0 : 28; + } BIT; +} volatile SPIIMSC_REG; + +/** + * @brief SPI raw interrupt status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rorris : 1; /**< raw status of the rx overflow interrupt. */ + unsigned int rtris : 1; /**< raw status of the rx timeout interrupt. */ + unsigned int rxris : 1; /**< raw status of the rx FIFO interrupt. */ + unsigned int txris : 1; /**< raw status of the tx FIFO interrupt. */ + unsigned int reserved0 : 28; + } BIT; +} volatile SPIRIS_REG; + +/** + * @brief SPI masked interrupt status register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rormis : 1; /**< masked status of the rx overflow interrupt. */ + unsigned int rtmis : 1; /**< masked status of the rx timeout interrupt. */ + unsigned int rxmis : 1; /**< masked status of the rx FIFO interrupt. */ + unsigned int txmis : 1; /**< masked status of the tx FIFO interrupt. */ + unsigned int reserved0 : 28; + } BIT; +} volatile SPIMIS_REG; + +/** + * @brief SPI interrupt clear register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int roric : 1; /**< clear the rx overflow interrupt. */ + unsigned int rtic : 1; /**< clear the rx timeout interrupt. */ + unsigned int reserved0 : 30; + } BIT; +} volatile SPIICR_REG; + +/** + * @brief SPI DMA control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rxdmae : 1; /**< DMA rx FIFO enable. */ + unsigned int txdmae : 1; /**< DMA tx FIFO enable. */ + unsigned int reserved0 : 30; + } BIT; +} volatile SPIDMACR_REG; + +/** + * @brief SPI tx FIFO control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int dmatxbrsize : 3; /**< set the threshold of the tx DMA burst. */ + unsigned int txintsize : 3; /**< set the threshold of the tx FIFO request interrupt. */ + unsigned int reserved0 : 26; + } BIT; +} volatile SPITXFIFOCR_REG; + +/** + * @brief SPI rx FIFO control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int dmarxbrsize : 3; /**< set the threshold of the rx DMA burst. */ + unsigned int rxintsize : 3; /**< set the threshold of the rx FIFO request interrupt. */ + unsigned int reserved0 : 26; + } BIT; +} volatile SPIRXFIFOCR_REG; + +/** + * @brief SPI cs mode control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int spi_csn_sel : 1; /**< chip select. */ + unsigned int reserved0 : 31; + } BIT; +} volatile SPICSNSEL_REG; + +/** + * @brief SPI Register definition structure + */ +typedef struct { + SPICR0_REG SPICR0; /**< SPI parameter control register 0. */ + SPICR1_REG SPICR1; /**< SPI parameter control register 1. */ + SPIDR_REG SPIDR; /**< SPI data FIFO register. */ + SPISR_REG SPISR; /**< SPI status register. */ + SPICPSR_REG SPICPSR; /**< SPI clock divider register. */ + SPIIMSC_REG SPIIMSC; /**< SPI interrupt mask control register. */ + SPIRIS_REG SPIRIS; /**< SPI raw interrupt status register. */ + SPIMIS_REG SPIMIS; /**< SPI masked interrupt status register. */ + SPIICR_REG SPIICR; /**< SPI interrupt clear register. */ + SPIDMACR_REG SPIDMACR; /**< SPI DMA control register. */ + SPITXFIFOCR_REG SPITXFIFOCR; /**< SPI tx FIFO control register. */ + SPIRXFIFOCR_REG SPIRXFIFOCR; /**< SPI rx FIFO control register. */ + unsigned char space0[208]; + SPICSNSEL_REG SPICSNSEL; /**< SPI cs mode control register. */ +} volatile SPI_RegStruct; +/** + * @} + */ + +/** + * @brief Check whether the SPI mode is used. + * @param mode Spi mode + * @retval true + * @retval false + */ +static inline bool IsSpiMode(unsigned int mode) +{ + if (mode == HAL_SPI_MASTER || mode == HAL_SPI_SLAVE) { + return true; + } + return false; +} + +/** + * @brief Check if the transfer mode specified for the SPI. + * @param xFermode Transfer mode. + * @retval true + * @retval false + */ +static inline bool IsSpiXferMode(unsigned int xFermode) +{ + if (xFermode == HAL_XFER_MODE_BLOCKING || + xFermode == HAL_XFER_MODE_INTERRUPTS || + xFermode == HAL_XFER_MODE_DMA) { + return true; + } + return false; +} + +/** + * @brief Checking SPI Polarity Parameters. + * @param clkPolarity Polarity Parameters. + * @retval true + * @retval false + */ +static inline bool IsSpiClkPolarity(unsigned int clkPolarity) +{ + if (clkPolarity == HAL_SPI_CLKPOL_0 || + clkPolarity == HAL_SPI_CLKPOL_1) { + return true; + } + return false; +} + +/** + * @brief Checking SPI Phase Parameters. + * @param clkPhase Phase Parameters. + * @retval true + * @retval false + */ +static inline bool IsSpiClkPhase(unsigned int clkPhase) +{ + if (clkPhase == HAL_SPI_CLKPHA_0 || + clkPhase == HAL_SPI_CLKPHA_1) { + return true; + } + return false; +} + +/** + * @brief Check the SPI big-endian configuration parameters. + * @param endian Big-endian configuration parameters. + * @retval true + * @retval false + */ +static inline bool IsSpiEndian(unsigned int endian) +{ + if (endian == HAL_SPI_BIG_ENDIAN || + endian == HAL_SPI_LITTILE_ENDIAN) { + return true; + } + return false; +} + +/** + * @brief Check the SPI frame format configuration. + * @param framFormat Frame format. + * @retval true + * @retval false + */ +static inline bool IsSpiFrameFormat(unsigned int framFormat) +{ + if (framFormat == HAL_SPI_MODE_MOTOROLA || + framFormat == HAL_SPI_MODE_TI || + framFormat == HAL_SPI_MODE_MICROWIRE) { + return true; + } + return false; +} + +/** + * @brief Checking the SPI Data Bit Width Configuration. + * @param dataWidth Data Bit Width. + * @retval true + * @retval false + */ +static inline bool IsSpiDataWidth(unsigned int dataWidth) +{ + if (dataWidth >= SPI_DATA_WIDTH_4BIT && dataWidth <= SPI_DATA_WIDTH_16BIT) { + return true; + } + return false; +} + +/** + * @brief Check the configuration of the waiting time between the TX and RX in the SPI microwire frame format. + * @param waitVal Waiting time. + * @retval true + * @retval false + */ +static inline bool IsSpiWaitVal(unsigned char waitVal) +{ + /* waitval value is 0 to 0x7f */ + if (waitVal <= 0x7f) { + return true; + } + return false; +} + +/** + * @brief Check the SPI interrupt TX threshold configuration. + * @param txIntSize TX threshold configuration. + * @retval true + * @retval false + */ +static inline bool IsSpiTxIntSize(unsigned int txIntSize) +{ + if (txIntSize == SPI_TX_INTERRUPT_SIZE_1 || txIntSize == SPI_TX_INTERRUPT_SIZE_4 || + txIntSize == SPI_TX_INTERRUPT_SIZE_8 || txIntSize == SPI_TX_INTERRUPT_SIZE_16 || + txIntSize == SPI_TX_INTERRUPT_SIZE_32 || txIntSize == SPI_TX_INTERRUPT_SIZE_64 || + txIntSize == SPI_TX_INTERRUPT_SIZE_128_0 || txIntSize == SPI_TX_INTERRUPT_SIZE_128_1) { + return true; + } + return false; +} + +/** + * @brief Check the SPI interrupt RX threshold configuration. + * @param rxIntSize RX threshold configuration. + * @retval true + * @retval false + */ +static inline bool IsSpiRxIntSize(unsigned int rxIntSize) +{ + if (rxIntSize == SPI_RX_INTERRUPT_SIZE_1 || rxIntSize == SPI_RX_INTERRUPT_SIZE_4 || + rxIntSize == SPI_RX_INTERRUPT_SIZE_8 || rxIntSize == SPI_RX_INTERRUPT_SIZE_16 || + rxIntSize == SPI_RX_INTERRUPT_SIZE_32 || rxIntSize == SPI_RX_INTERRUPT_SIZE_64 || + rxIntSize == SPI_RX_INTERRUPT_SIZE_128 || rxIntSize == SPI_RX_INTERRUPT_SIZE_192) { + return true; + } + return false; +} + +/** + * @brief Check the SPI DMA TX threshold configuration. + * @param txDMABurstSize TX threshold. + * @retval true + * @retval false + */ +static inline bool IsSpiTxDmaBurstSize(unsigned int txDMABurstSize) +{ + if (txDMABurstSize == SPI_TX_DMA_BURST_SIZE_1 || txDMABurstSize == SPI_TX_DMA_BURST_SIZE_4 || + txDMABurstSize == SPI_TX_DMA_BURST_SIZE_8 || txDMABurstSize == SPI_TX_DMA_BURST_SIZE_16 || + txDMABurstSize == SPI_TX_DMA_BURST_SIZE_32 || txDMABurstSize == SPI_TX_DMA_BURST_SIZE_64_0 || + txDMABurstSize == SPI_TX_DMA_BURST_SIZE_64_1 || txDMABurstSize == SPI_TX_DMA_BURST_SIZE_64_2) { + return true; + } + return false; +} + +/** + * @brief Check the SPI DMA RX threshold configuration. + * @param rxDMABurstSize RX threshold. + * @retval true + * @retval false + */ +static inline bool IsSpiRxDmaBurstSize(unsigned int rxDMABurstSize) +{ + if (rxDMABurstSize == SPI_RX_DMA_BURST_SIZE_1 || rxDMABurstSize == SPI_RX_DMA_BURST_SIZE_4 || + rxDMABurstSize == SPI_RX_DMA_BURST_SIZE_8 || rxDMABurstSize == SPI_RX_DMA_BURST_SIZE_16 || + rxDMABurstSize == SPI_RX_DMA_BURST_SIZE_32 || rxDMABurstSize == SPI_RX_DMA_BURST_SIZE_64 || + rxDMABurstSize == SPI_RX_DMA_BURST_SIZE_96 || rxDMABurstSize == SPI_RX_DMA_BURST_SIZE_128) { + return true; + } + return false; +} + +/** + * @brief Checking SPI frequency divider parameters. + * @param freqCpsdvsr Frequency division parameters to be checked. + * @retval true + * @retval false + */ +static inline bool IsSpiFreqCpsdvsr(unsigned char freqCpsdvsr) +{ + /* FreqCpsdvsr value is 0 to 255 */ + if (freqCpsdvsr >= 2) { + return true; + } + return false; +} + +/* Direct configuration layer interface----------------------------------*/ +/** + * @brief SPI module enable. + * @param spix SPI register base address. + * @param spiEnable SPI enable or disable. + * @retval None. + */ +static inline void DCL_SPI_SetSpiEnable(SPI_RegStruct *spix, bool spiEnable) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPICR1.BIT.sse = spiEnable; +} + +/** + * @brief Get SPI enable status. + * @param spix SPI register base address. + * @retval bool SPI enable or disable. + */ +static inline bool DCL_SPI_GetSpiEnable(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR1.BIT.sse; +} + +/** + * @brief Configuring SPI polarity + * @param spix SPI register base address. + * @param clkPolarity SPI Polarity,the value is 0 or 1. + * @retval None. + */ +static inline void DCL_SPI_SetClkPolarity(SPI_RegStruct *spix, unsigned char clkPolarity) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPICR0.BIT.spo = clkPolarity; +} + +/** + * @brief Get SPI polarity. + * @param spix SPI register base address. + * @retval SPI Polarity,the value is 0 or 1. + */ +static inline unsigned char DCL_SPI_GetClkPolarity(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR0.BIT.spo; +} + +/** + * @brief Configuring SPI phase. + * @param spix SPI register base address. + * @param clkPhase SPI phase,the value is 0 or 1. + * @retval None. + */ +static inline void DCL_SPI_SetClkPhase(SPI_RegStruct *spix, unsigned char clkPhase) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPICR0.BIT.sph = clkPhase; +} + +/** + * @brief Get SPI phase. + * @param spix SPI register base address. + * @retval SPI phase,the value is 0 or 1. + */ +static inline unsigned char DCL_SPI_GetClkPhase(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR0.BIT.sph; +} + +/** + * @brief SPI data big endian configuration. + * @param spix SPI register base address. + * @param bitEnd Big-endian configuration parameter. The value can be 0 or 1. + * @retval None. + */ +static inline void DCL_SPI_SetBitEnd(SPI_RegStruct *spix, unsigned char bitEnd) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPICR1.BIT.bitend = bitEnd; +} + +/** + * @brief Get SPI data big endian configuration. + * @param spix SPI register base address. + * @retval Big-endian configuration parameter. The value is 0 or 1. + */ +static inline unsigned char DCL_SPI_GetBitEnd(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR1.BIT.bitend; +} + +/** + * @brief SPI frame format configuration. + * @param spix SPI register base address. + * @param frameFormat Value: Motorola: 00, TI synchronous serial: 01, National Microwire: 10. + * @retval None. + */ +static inline void DCL_SPI_SetFrameFormat(SPI_RegStruct *spix, unsigned char frameFormat) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPICR0.BIT.frf = frameFormat; +} + +/** + * @brief Get SPI frame format configuration. + * @param spix SPI register base address. + * @retval Motorola: 00, TI synchronous serial: 01, National Microwire: 10. + */ +static inline unsigned char DCL_SPI_GetFrameFormat(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR0.BIT.frf; +} + +/** + * @brief Configuring the SPI data bit width. + * @param spix SPI register base address. + * @param dataWidth The data bit width can be set to 4 to 16 bytes. + * @retval None. + */ +static inline void DCL_SPI_SetDataWidth(SPI_RegStruct *spix, unsigned char dataWidth) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPICR0.BIT.dss = dataWidth; +} + +/** + * @brief Get the SPI data bit width configuring. + * @param spix SPI register base address. + * @retval SPI Data Bit Width configuring. + */ +static inline unsigned char DCL_SPI_GetDataWidth(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR0.BIT.dss; +} + +/** + * @brief SPI serial clock rate configuration. + * @param spix SPI register base address. + * @param freqScr Value range: 0 to 255. + * @retval None. + */ +static inline void DCL_SPI_SetFreqScr(SPI_RegStruct *spix, unsigned char freqScr) +{ + unsigned int cr0Reg; + unsigned int temp; + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + /* Read the entire register and write it back. */ + temp = ((unsigned int)freqScr) << SPI_CR0_SCR_POS; + cr0Reg = (spix->SPICR0.reg & (~SPI_CR0_SCR_MASK)) | temp; + spix->SPICR0.reg = cr0Reg; +} + +/** + * @brief Get SPI serial clock rate configuration. + * @param spix SPI register base address. + * @retval Value range: 0 to 255. + */ +static inline unsigned char DCL_SPI_GetFreqScr(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return ((spix->SPICR0.reg >> SPI_CR0_SCR_POS) & 0xFF); /* Minimum 8-bit mask 0xFF */ +} + +/** + * @brief SPI clock divider setting. + * @param spix SPI register base address. + * @param freqCpsdvsr The value must be an even number between 2 and 255. + * @retval None. + */ +static inline void DCL_SPI_SetFreqCpsdvsr(SPI_RegStruct *spix, unsigned char freqCpsdvsr) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPICPSR.BIT.cpsdvsr = freqCpsdvsr; +} + +/** + * @brief Get SPI clock divider setting. + * @param spix SPI register base address. + * @retval The value is an even number between 2 and 255. + */ +static inline unsigned char DCL_SPI_GetFreqCpsdvsr(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICPSR.BIT.cpsdvsr; +} + +/** + * @brief Configuring the SPI TX threshold. + * @param spix SPI register base address. + * @param txIntSize The value can be 1, 4, 8, 16, 32, 64, or 128. For details, see the register manual. + * @retval None. + */ +static inline void DCL_SPI_SetTxIntSize(SPI_RegStruct *spix, unsigned char txIntSize) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPITXFIFOCR.BIT.txintsize = txIntSize; +} + +/** + * @brief Get the SPI TX threshold configuring. + * @param spix SPI register base address. + * @retval The value is 000, 001, 010, 011, 100, 101,110, or 111. For details, see the register manual. + */ +static inline unsigned char DCL_SPI_GetTxIntSize(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPITXFIFOCR.BIT.txintsize; +} + +/** + * @brief Configuring the SPI RX threshold. + * @param spix SPI register base address. + * @param rxIntSize The value can be 1, 4, 8, 16, 32, 64, or 128. For details, see the register manual. + * @retval None. + */ +static inline void DCL_SPI_SetRxIntSize(SPI_RegStruct *spix, unsigned char rxIntSize) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPIRXFIFOCR.BIT.rxintsize = rxIntSize; +} + +/** + * @brief Get the SPI RX threshold configuring. + * @param spix SPI register base address. + * @retval The value is 000, 001, 010, 011, 100, 101,110, or 111. For details, see the register manual. + */ +static inline unsigned char DCL_SPI_GetRxIntSize(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPIRXFIFOCR.BIT.rxintsize; +} + +/** + * @brief Configure the threshold for the TX FIFO to request the DMA to perform burst transfer. + * @param spix SPI register base address. + * @param txDMABurstSize The value can be 1, 4, 8, 16, 32 or 64. For details, see the register manual. + * @retval None. + */ +static inline void DCL_SPI_SetTxDMABurstSize(SPI_RegStruct *spix, unsigned char txDMABurstSize) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPITXFIFOCR.BIT.dmatxbrsize = txDMABurstSize; +} + +/** + * @brief Get the threshold for the TX FIFO to request the DMA to perform burst transfer configure. + * @param spix SPI register base address. + * @retval The value is 000, 001, 010, 011, 100, 101,110, or 111. For details, see the register manual. + */ +static inline unsigned char DCL_SPI_GetTxDMABurstSize(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPITXFIFOCR.BIT.dmatxbrsize; +} + +/** + * @brief Configure the threshold for the RX FIFO to request the DMA to perform burst transfer. + * @param spix SPI register base address. + * @param txDMABurstSize The value can be 1, 4, 8, 16, 32 or 64. For details, see the register manual. + * @retval None. + */ +static inline void DCL_SPI_SetRxDMABurstSize(SPI_RegStruct *spix, unsigned char rxDMABurstSize) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPIRXFIFOCR.BIT.dmarxbrsize = rxDMABurstSize; +} + +/** + * @brief Get the threshold for the RX FIFO to request the DMA to perform burst transfer configure. + * @param spix SPI register base address. + * @retval The value is 000, 001, 010, 011, 100, 101,110, or 111. For details, see the register manual. + */ +static inline unsigned char DCL_SPI_GetRxDMABurstSize(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPIRXFIFOCR.BIT.dmarxbrsize; +} + +/** + * @brief Configuring the CS Channel. + * @param spix SPI register base address. + * @retval None. + */ +static inline void DCL_SPI_SetChipSelect(SPI_RegStruct *spix, unsigned char channel) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPICSNSEL.BIT.spi_csn_sel = channel; +} + +/** + * @brief Obtains the channel of the current CS. + * @param spix SPI register base address. + * @retval SPI_ChipSelectChannel. + */ +static inline unsigned char DCL_SPI_GetChipSelect(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICSNSEL.BIT.spi_csn_sel; +} + +/** + * @brief Set SPI loopback. + * @param spix SPI register base address. + * @param loop enable or disable + * @retval None. + */ +static inline void DCL_SPI_SetLoopBack(SPI_RegStruct *spix, bool loop) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPICR1.BIT.lbm = loop; +} + +/** + * @brief Get SPI loopback. + * @param spix SPI register base address. + * @retval bool loopback is enable or disable. + */ +static inline bool DCL_SPI_GetLoopBack(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR1.BIT.lbm; +} + +/** + * @brief Setting the Master/Slave Mode. + * @param spix SPI register base address. + * @param mode @ref HAL_SPI_Mode. + * @retval None. + */ +static inline void DCL_SPI_SetMasterSlaveMode(SPI_RegStruct *spix, HAL_SPI_Mode mode) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + SPI_PARAM_CHECK_NO_RET(mode >= HAL_SPI_MASTER && mode <= HAL_SPI_SLAVE); + spix->SPICR1.BIT.ms = mode; +} + +/** + * @brief Getting the Master/Slave Mode. + * @param spix SPI register base address. + * @retval HAL_SPI_Mode master or slave. + */ +static inline HAL_SPI_Mode DCL_SPI_GetMasterSlaveMode(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR1.BIT.ms; +} + +/** + * @brief Set altasens mode. + * @param spix SPI register base address. + * @param altMode The value is 0 or 1. + * @retval None. + */ +static inline void DCL_SPI_SetChipConfigSelect(SPI_RegStruct *spix, bool altMode) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPICR1.BIT.mode_altasens = altMode; +} + +/** + * @brief Get altasens mode. + * @param spix SPI register base address. + * @retval bool, 0 is chip automatically, 1 is motorola cs. + */ +static inline bool DCL_SPI_GetChipConfigSelect(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR1.BIT.mode_altasens; +} + +/** + * @brief Set microwire waitval. + * @param spix SPI register base address. + * @param value is microwire wait beats. + * @retval None. + */ +static inline void DCL_SPI_SetMircoWaitVal(SPI_RegStruct *spix, unsigned char value) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPICR1.BIT.waitval = value; +} + +/** + * @brief Get microwire waitval. + * @param spix SPI register base address. + * @retval unsigned char, For details, see the register manual + */ +static inline unsigned char DCL_SPI_GetMircoWaitVal(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR1.BIT.waitval; +} + +/** + * @brief Set microwire wait enable or disable. + * @param spix SPI register base address. + * @param waitEn is microwire wait enable or disable. + * @retval None. + */ +static inline void DCL_SPI_SetMircoWaitEn(SPI_RegStruct *spix, bool waitEn) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPICR1.BIT.waiten = waitEn; +} + +/** + * @brief Get microwire wait enable or disable. + * @param spix SPI register base address. + * @retval bool is microwire wait enable or disable + */ +static inline bool DCL_SPI_GetMircoWaitEn(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPICR1.BIT.waiten; +} + +/** + * @brief Put the data into the TX FIFO. + * @param spix SPI register base address. + * @param data is input data. + * @retval None. + */ +static inline void DCL_SPI_SetData(SPI_RegStruct *spix, unsigned short data) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPIDR.reg = data; +} + +/** + * @brief Get data from the RX FIFO. + * @param spix SPI register base address. + * @retval unsigned short data from the RX FIFO. + */ +static inline unsigned short DCL_SPI_GetData(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPIDR.reg; +} + +/** + * @brief Get whether the TX FIFO is empty. + * @param spix SPI register base address. + * @retval bool TX FIFO is not empty or is empty. + */ +static inline bool DCL_SPI_GetTxFifoEmpty(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPISR.BIT.tfe; +} + +/** + * @brief Get whether the TX FIFO is full. + * @param spix SPI register base address. + * @retval bool TX FIFO is not full or is full. + */ +static inline bool DCL_SPI_GetTxFifoFull(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPISR.BIT.tnf; +} + +/** + * @brief Get whether the RX FIFO is empty. + * @param spix SPI register base address. + * @retval bool RX FIFO is not empty or is empty. + */ +static inline bool DCL_SPI_GetRxFifoEmpty(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPISR.BIT.rne; +} + +/** + * @brief Get whether the RX FIFO is full. + * @param spix SPI register base address. + * @retval bool RX FIFO is not full or is full. + */ +static inline bool DCL_SPI_GetRxFifoFull(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPISR.BIT.rff; +} + +/** + * @brief Get Whether the SPI is busy. + * @param spix SPI register base address. + * @retval bool SPI is busy or not busy. + */ +static inline bool DCL_SPI_GetBusyFlag(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPISR.BIT.bsy; +} + +/** + * @brief Set the interrupt mask. + * @param spix SPI register base address. + * @param intMask For details, see the register manual. + * @retval None. + */ +static inline void DCL_SPI_SetIntMask(SPI_RegStruct *spix, unsigned int intMask) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPIIMSC.reg = intMask; +} + +/** + * @brief Get the interrupt mask. + * @param spix SPI register base address. + * @retval unsigned int interrupt mask. + */ +static inline unsigned int DCL_SPI_GetIntMask(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPIIMSC.reg; +} + +/** + * @brief Get SPIMIS register all mask interrupt status. + * @param spix SPI register base address. + * @retval unsigned short SPIMIS register interrupt mask. + */ +static inline unsigned int DCL_SPI_GetMisInt(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPIMIS.reg; +} + +/** + * @brief Clear RX timeout interrupt + * @param spix SPI register base address. + * @retval None. + */ +static inline void DCL_SPI_ClearRxTimeInt(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPIICR.BIT.roric = BASE_CFG_SET; +} + +/** + * @brief Clear RX overflow interrupt + * @param spix SPI register base address. + * @retval None. + */ +static inline void DCL_SPI_ClearRxOverInt(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPIICR.BIT.rtic = BASE_CFG_SET; +} + +/** + * @brief Set DMA FIFO enable register. + * @param spix SPI register base address. + * @param dmaCtl control DMA FIFO enable. + * @retval None. + */ +static inline void DCL_SPI_SetDmaTxFifo(SPI_RegStruct *spix, unsigned int dmaCtl) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + spix->SPIDMACR.reg = dmaCtl; +} + +/** + * @brief Get DMA FIFO enable register status. + * @param spix SPI register base address. + * @retval unsigned int DMA Control Register Status. + */ +static inline unsigned int DCL_SPI_GetDmaTxFifo(SPI_RegStruct *spix) +{ + SPI_ASSERT_PARAM(IsSPIInstance(spix)); + return spix->SPIDMACR.reg; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* #ifndef McuMagicTag_SPI_IP_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/spi/src/spi.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/spi/src/spi.c new file mode 100644 index 00000000..f9f5e1b4 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/spi/src/spi.c @@ -0,0 +1,1183 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file spi.c + * @author MCU Driver Team + * @brief SPI module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the SPI. + * + Initialization and de-initialization functions + * + Peripheral Control functions + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "systick.h" +#include "spi.h" +/* Macro definitions ---------------------------------------------------------*/ +#define SPI_WAIT_TIMEOUT 0x400 + +#define SPI_DATA_WIDTH_SHIFT_8BIT 1 +#define SPI_DATA_WIDTH_SHIFT_16BIT 2 + +#define SPI_INTERRUPT_SET_ALL 0xF +#define SPI_DMA_FIFO_ENABLE 0x3 + +#define SPI_TICK_MS_DIV 1000 +#define SPI_CLOCK_FREQ_MAX 25000000 + +/** + * @brief Check all initial configuration parameters. + * @param handle SPI handle. + * @retval BASE status type: OK, ERROR. + */ +static BASE_StatusType CheckAllInitParameters(SPI_Handle *handle) +{ + SPI_PARAM_CHECK_WITH_RET(IsSpiMode(handle->mode), BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(IsSpiXferMode(handle->xFerMode), BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(IsSpiEndian(handle->endian), BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(IsSpiFrameFormat(handle->frameFormat), BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(IsSpiDataWidth(handle->dataWidth), BASE_STATUS_ERROR); + /* Check spi freqCpsdvsr */ + if (handle->mode == HAL_SPI_MASTER) { + SPI_PARAM_CHECK_WITH_RET(IsSpiFreqCpsdvsr(handle->freqCpsdvsr), BASE_STATUS_ERROR); + } + /* Check motorola clkPolarity and clkPhase */ + if (handle->frameFormat == HAL_SPI_MODE_MOTOROLA) { + SPI_PARAM_CHECK_WITH_RET(IsSpiClkPolarity(handle->clkPolarity), BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(IsSpiClkPhase(handle->clkPhase), BASE_STATUS_ERROR); + } + /* Check microwire waitVal */ + if (handle->frameFormat == HAL_SPI_MODE_MICROWIRE) { + SPI_PARAM_CHECK_WITH_RET(IsSpiWaitVal(handle->waitVal), BASE_STATUS_ERROR); + } + /* Check tx rx interrupt size */ + if (handle->xFerMode == HAL_XFER_MODE_INTERRUPTS) { + SPI_PARAM_CHECK_WITH_RET(IsSpiTxIntSize(handle->txIntSize), BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(IsSpiRxIntSize(handle->rxIntSize), BASE_STATUS_ERROR); + } + /* Check tx rx dma burst size */ + if (handle->xFerMode == HAL_XFER_MODE_DMA) { + SPI_PARAM_CHECK_WITH_RET(IsSpiTxDmaBurstSize(handle->txDMABurstSize), BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(IsSpiRxDmaBurstSize(handle->rxDMABurstSize), BASE_STATUS_ERROR); + } + return BASE_STATUS_OK; +} + +/** + * @brief Configuring the Register Parameters of the Three Transfer Modes. + * @param handle SPI handle. + * @retval BASE status type: OK, ERROR. + */ +static BASE_StatusType ConfigThreeTransferParam(SPI_Handle *handle) +{ + SPI_ASSERT_PARAM(handle != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + /* Configurations related to the three transmission modes */ + if (handle->xFerMode == HAL_XFER_MODE_BLOCKING) { + handle->baseAddress->SPIIMSC.reg = 0x0; + } else if (handle->xFerMode == HAL_XFER_MODE_INTERRUPTS) { + handle->baseAddress->SPIIMSC.reg = SPI_INTERRUPT_SET_ALL; + /* Setting the rx and tx interrupt transfer size */ + handle->baseAddress->SPITXFIFOCR.BIT.txintsize = handle->txIntSize; + handle->baseAddress->SPIRXFIFOCR.BIT.rxintsize = handle->rxIntSize; + } else if (handle->xFerMode == HAL_XFER_MODE_DMA) { + handle->baseAddress->SPIIMSC.reg = 0x0; + /* Setting the DMA rx and tx burst transfer size */ + handle->baseAddress->SPITXFIFOCR.BIT.dmatxbrsize = handle->txDMABurstSize; + handle->baseAddress->SPIRXFIFOCR.BIT.dmarxbrsize = handle->rxDMABurstSize; + } else { + /* xFerMode set error */ + handle->errorCode = BASE_STATUS_ERROR; + handle->state = HAL_SPI_STATE_RESET; + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief Internal chip select control. + * @param handle SPI handle. + * @param control SPI_CHIP_DESELECT or SPI_CHIP_SELECT + * @retval None. + */ +static void InternalCsControl(SPI_Handle *handle, unsigned int control) +{ + BASE_FUNC_UNUSED(handle); + BASE_FUNC_UNUSED(control); +} + +/** + * @brief Chip select control. + * @param handle SPI handle. + * @param control SPI_CHIP_DESELECT or SPI_CHIP_SELECT + * @retval None. + */ +static void SpiCsControl(SPI_Handle *handle, unsigned int control) +{ + /* The chip select signal is determined by the chip logic. */ + if (handle->csMode == SPI_CHIP_SELECT_MODE_INTERNAL) { + InternalCsControl(handle, control); + } else { + /* The chip select signal is determined by callback */ + if (handle->userCallBack.CsCtrlCallback != NULL) { + handle->csCtrl = control; + handle->userCallBack.CsCtrlCallback(handle); + } + } +} + +/** + * @brief Invoke rx tx callback function. + * @param handle SPI handle. + * @retval None. + */ +static void SpiRxTxCallack(void *handle) +{ + SPI_Handle *spiHandle = (SPI_Handle *) handle; + SPI_ASSERT_PARAM(spiHandle != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(spiHandle->baseAddress)); + if (spiHandle->txCount == spiHandle->transferSize) { + /* Invoke tx callback function. */ + if (spiHandle->userCallBack.TxCpltCallback != NULL) { + spiHandle->userCallBack.TxCpltCallback(spiHandle); + } + spiHandle->baseAddress->SPIIMSC.BIT.txim = 0x0; + } + + if (spiHandle->rxCount >= spiHandle->transferSize) { + /* Disable all interrupt */ + spiHandle->baseAddress->SPIIMSC.reg = 0x0; + /* Clear all interrupt */ + spiHandle->baseAddress->SPIICR.BIT.roric = BASE_CFG_SET; + spiHandle->baseAddress->SPIICR.BIT.rtic = BASE_CFG_SET; + + SpiCsControl(spiHandle, SPI_CHIP_DESELECT); + + /* Invoke rx callback function. */ + if (spiHandle->userCallBack.RxCpltCallback != NULL) { + spiHandle->userCallBack.RxCpltCallback(spiHandle); + } + /* Invoke tx rx callback function. */ + if (spiHandle->userCallBack.TxRxCpltCallback != NULL) { + spiHandle->userCallBack.TxRxCpltCallback(spiHandle); + } + spiHandle->state = HAL_SPI_STATE_READY; + } +} + +/** + * @brief Writes data from the buffer to the FIFO. + * @param handle SPI handle. + * @retval None. + */ +static void WriteData(SPI_Handle *handle) +{ + while (handle->baseAddress->SPISR.BIT.tnf && + (handle->transferSize > handle->txCount)) { + if (handle->dataWidth > SPI_DATA_WIDTH_8BIT) { + /* Only data needs to be read. Due to SPI characteristics, + data must be transmitted before data can be read. Therefore, 0x0 is transmitted. */ + if (handle->txBuff == NULL) { + handle->baseAddress->SPIDR.reg = 0x0; + handle->txCount += SPI_DATA_WIDTH_SHIFT_16BIT; + } else { + handle->baseAddress->SPIDR.reg = *(unsigned short *)handle->txBuff; + handle->txCount += SPI_DATA_WIDTH_SHIFT_16BIT; /* txCount is number of bytes transferred */ + handle->txBuff += SPI_DATA_WIDTH_SHIFT_16BIT; + } + } else { /* datawidth is 8bit */ + if (handle->txBuff == NULL) { + handle->baseAddress->SPIDR.reg = 0x0; + handle->txCount += SPI_DATA_WIDTH_SHIFT_8BIT; + } else { + handle->baseAddress->SPIDR.reg = *(unsigned char *)handle->txBuff; + handle->txCount += SPI_DATA_WIDTH_SHIFT_8BIT; /* txCount is number of bytes transferred */ + handle->txBuff += SPI_DATA_WIDTH_SHIFT_8BIT; + } + } + } +} + +/** + * @brief Reads data from the FIFO to the buffer. + * @param handle SPI handle. + * @retval None. + */ +static void ReadData(SPI_Handle *handle) +{ + unsigned short val; + + while (handle->baseAddress->SPISR.BIT.rne && (handle->transferSize > handle->rxCount)) { + if (handle->dataWidth > SPI_DATA_WIDTH_8BIT) { + /* When only data is transmitted, the data in the RX FIFO needs to be read. */ + if (handle->rxBuff == NULL) { + val = handle->baseAddress->SPIDR.reg; + BASE_FUNC_UNUSED(val); + handle->rxCount += SPI_DATA_WIDTH_SHIFT_16BIT; + } else { + *(unsigned short *)handle->rxBuff = handle->baseAddress->SPIDR.reg; + handle->rxCount += SPI_DATA_WIDTH_SHIFT_16BIT; + handle->rxBuff += SPI_DATA_WIDTH_SHIFT_16BIT; + } + } else { /* datawidth is 8bit */ + if (handle->rxBuff == NULL) { + val = handle->baseAddress->SPIDR.reg; + BASE_FUNC_UNUSED(val); + handle->rxCount += SPI_DATA_WIDTH_SHIFT_8BIT; + } else { + *(unsigned char *)handle->rxBuff = handle->baseAddress->SPIDR.reg & 0xff; + handle->rxCount += SPI_DATA_WIDTH_SHIFT_8BIT; + handle->rxBuff += SPI_DATA_WIDTH_SHIFT_8BIT; + } + } + } +} + +/** + * @brief Check the SPI flag before reading data. + * @param handle SPI handle. + * @retval bool. + */ +static bool CheckSpiStatus(SPI_Handle* handle) +{ + /* Check the SPI Status. */ + if (handle->mode == HAL_SPI_MASTER) { /* SPI master */ + if (handle->baseAddress->SPISR.BIT.bsy == BASE_CFG_UNSET && + handle->baseAddress->SPISR.BIT.tfe == BASE_CFG_SET && + handle->baseAddress->SPISR.BIT.rne == BASE_CFG_SET) { + return true; + } + } + if (handle->mode == HAL_SPI_SLAVE) { /* SPI slave */ + if (handle->baseAddress->SPISR.BIT.rne == BASE_CFG_SET) { + return true; + } + } + return false; +} + + +/** + * @brief Read/write based on input parameters. + * The Motorola SPI/TI synchronous serial interface is full-duplex. + * Each data is received. Even if only data needs to be transmitted, + * the RX FIFO needs to be cleared. + * @param handle SPI handle. + * @retval None. + */ +static void ReadWriteData(SPI_Handle *handle) +{ + unsigned int preTick = DCL_SYSTICK_GetTick(); + unsigned int curTick = preTick; + unsigned long long delta = 0; + /* Calculate the timeout tick. */ + unsigned long long targetDelta = SYSTICK_GetCRGHZ() / SPI_TICK_MS_DIV * SPI_WAIT_TIMEOUT; + /* Disable SPI before wirte data */ + if (handle->mode == HAL_SPI_MASTER) { /* SPI master */ + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_UNSET; + } + WriteData(handle); /* Fill data into the TX FIFO. */ + /* Enable SPI after wirte data */ + if (handle->mode == HAL_SPI_MASTER) { + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_SET; + } + + while (true) { + /* Wait for the write operation to complete */ + if (CheckSpiStatus(handle)) { + break; + } + curTick = DCL_SYSTICK_GetTick(); + delta += curTick > preTick ? curTick - preTick : SYSTICK_MAX_VALUE - preTick + curTick; + /* Exit upon timeout */ + if (delta >= targetDelta) { + handle->errorCode = BASE_STATUS_TIMEOUT; + break; + } + preTick = curTick; + } + ReadData(handle); +} + +/** + * @brief Blocking read data processing. + * @param handle SPI handle. + * @param timeout Timeout period,unit: ms. + * @retval None. + */ +static void ReadBlocking(SPI_Handle *handle, unsigned int timeout) +{ + unsigned int preTick = DCL_SYSTICK_GetTick(); + unsigned int curTick = preTick; + unsigned long long delta = 0; + unsigned long long targetDelta = SYSTICK_GetCRGHZ() / SPI_TICK_MS_DIV * timeout; + + /* Pull down the CS before transmitting data. */ + SpiCsControl(handle, SPI_CHIP_SELECT); + if (!handle->baseAddress->SPICR1.BIT.sse) { + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_SET; /* spi enable */ + } + while (handle->transferSize > handle->rxCount) { + curTick = DCL_SYSTICK_GetTick(); + delta += curTick > preTick ? curTick - preTick : SYSTICK_MAX_VALUE - preTick + curTick; + if (delta >= targetDelta) { /* The configured timeout period is exceeded. */ + handle->errorCode = BASE_STATUS_TIMEOUT; + break; + } + ReadData(handle); + preTick = curTick; + } + /* Pull up the CS after transmitting data. */ + SpiCsControl(handle, SPI_CHIP_DESELECT); + handle->state = HAL_SPI_STATE_READY; +} + +/** + * @brief Blocking read/write data processing. + * @param handle SPI handle. + * @param timeout Timeout period,unit: ms. + * @retval None. + */ +static void ReadWriteBlocking(SPI_Handle *handle, unsigned int timeout) +{ + unsigned int preTick = DCL_SYSTICK_GetTick(); + unsigned int curTick = preTick; + unsigned long long delta = 0; + unsigned long long targetDelta = SYSTICK_GetCRGHZ() / SPI_TICK_MS_DIV * timeout; + /* Pull down the CS before transmitting data. */ + SpiCsControl(handle, SPI_CHIP_SELECT); + if (!handle->baseAddress->SPICR1.BIT.sse) { + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_SET; /* spi enable */ + } + + while (handle->transferSize > handle->txCount || handle->transferSize > handle->rxCount) { + curTick = DCL_SYSTICK_GetTick(); + delta += curTick > preTick ? curTick - preTick : SYSTICK_MAX_VALUE - preTick + curTick; + if (delta >= targetDelta) { /* The configured timeout period is exceeded. */ + handle->errorCode = BASE_STATUS_TIMEOUT; + break; + } + ReadWriteData(handle); + preTick = curTick; + } + /* Pull up the CS after transmitting data. */ + SpiCsControl(handle, SPI_CHIP_DESELECT); + handle->state = HAL_SPI_STATE_READY; +} + +/** + * @brief SPI read/write parameter configuration. + * @param handle SPI handle. + * @param rData Address of the data buff to be Receiving. + * @param wData Address of the data buff to be sent. + * @param dataSiz Number of the data to be Receivingd and sent. + * @retval None. + */ +static void ConfigTransmissionParameter(SPI_Handle *handle, + unsigned char *rData, + unsigned char *wData, + unsigned int dataSize) +{ + handle->errorCode = BASE_STATUS_OK; + handle->rxBuff = rData; + handle->txBuff = wData; + if (handle->dataWidth > SPI_DATA_WIDTH_8BIT && + handle->xFerMode == HAL_XFER_MODE_DMA) { + handle->transferSize = dataSize / 2; /* Processes 2 bytes at a time */ + } else { + handle->transferSize = dataSize; + } + handle->txCount = 0; + handle->rxCount = 0; +} + +/** + * @brief SPI Clear Rx Fifo. + * @param handle SPI handle. + * @retval None. + */ +static void ClearSpiRxFifo(SPI_Handle *handle) +{ + /* Invalid data in the RX FIFO, Clearing the RX FIFO. */ + unsigned short val; + while (handle->baseAddress->SPISR.BIT.rne) { + val = handle->baseAddress->SPIDR.reg; + BASE_FUNC_UNUSED(val); + } +} + +/** + * @brief Initializing the SPI Module. + * @param handle SPI handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_Init(SPI_Handle *handle) +{ + unsigned int cr0Reg; + unsigned int temp; + unsigned int cpsdvsrVal; + SPI_ASSERT_PARAM(handle != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + /* Check whether initialization parameters are correctly set */ + if (CheckAllInitParameters(handle) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + + unsigned int spiClock = HAL_CRG_GetIpFreq((void *)handle->baseAddress); + /* Modulo 2 to get an even number */ + cpsdvsrVal = ((handle->freqCpsdvsr % 2 == 0) ? handle->freqCpsdvsr : handle->freqCpsdvsr - 1); + unsigned int spiDivClock = spiClock / (cpsdvsrVal * (1 + handle->freqScr)); + /* The maximum clock rate in SPI master mode cannot be greater than 25 MHz. */ + if (spiDivClock > SPI_CLOCK_FREQ_MAX) { + return BASE_STATUS_ERROR; + } + + handle->state = HAL_SPI_STATE_BUSY; + + handle->baseAddress->SPICR1.BIT.lbm = BASE_CFG_UNSET; + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_UNSET; + handle->baseAddress->SPICR1.BIT.bitend = handle->endian; /* Setting the endian mode */ + handle->baseAddress->SPICR1.BIT.ms = handle->mode; + handle->baseAddress->SPICR1.BIT.mode_altasens = BASE_CFG_UNSET; + + temp = ((unsigned int)handle->freqScr) << SPI_CR0_SCR_POS; + cr0Reg = (handle->baseAddress->SPICR0.reg & (~SPI_CR0_SCR_MASK)) | temp; + handle->baseAddress->SPICR0.reg = cr0Reg; + handle->baseAddress->SPICPSR.BIT.cpsdvsr = cpsdvsrVal; + + handle->baseAddress->SPICR0.BIT.sph = handle->clkPhase; + handle->baseAddress->SPICR0.BIT.spo = handle->clkPolarity; + + handle->baseAddress->SPICR0.BIT.frf = handle->frameFormat; + handle->baseAddress->SPICR0.BIT.dss = handle->dataWidth; + + /* Indicates whether to enable the Microwire wait period. */ + if ((handle->frameFormat == HAL_SPI_MODE_MICROWIRE) && (handle->waitEn == BASE_CFG_ENABLE)) { + handle->baseAddress->SPICR1.BIT.waitval = handle->waitVal; + handle->baseAddress->SPICR1.BIT.waiten = BASE_CFG_SET; + } else { + handle->baseAddress->SPICR1.BIT.waiten = BASE_CFG_UNSET; + } + if (ConfigThreeTransferParam(handle) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + handle->state = HAL_SPI_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief Deinitialize the SPI module. + * @param handle SPI handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_Deinit(SPI_Handle *handle) +{ + SPI_ASSERT_PARAM(handle != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + + handle->state = HAL_SPI_STATE_BUSY; + /* Disable rx and tx DMA, SPI disable */ + handle->baseAddress->SPIIMSC.reg = 0x0; + handle->baseAddress->SPIDMACR.BIT.rxdmae = BASE_CFG_UNSET; + handle->baseAddress->SPIDMACR.BIT.txdmae = BASE_CFG_UNSET; + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_UNSET; + handle->state = HAL_SPI_STATE_RESET; + /* Clean callback */ + handle->userCallBack.TxCpltCallback = NULL; + handle->userCallBack.RxCpltCallback = NULL; + handle->userCallBack.TxRxCpltCallback = NULL; + handle->userCallBack.ErrorCallback = NULL; + handle->userCallBack.CsCtrlCallback = NULL; + return BASE_STATUS_OK; +} + +/** + * @brief SPI Parameter Configuration. + * @param handle SPI handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_ConfigParameter(SPI_Handle *handle) +{ + unsigned int cr0Reg; + unsigned int temp; + SPI_ASSERT_PARAM(handle != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + /* Check whether initialization parameters are correctly set */ + if (CheckAllInitParameters(handle) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_UNSET; + handle->baseAddress->SPICR1.BIT.ms = handle->mode; + handle->baseAddress->SPICR0.BIT.frf = handle->frameFormat; + handle->baseAddress->SPICR0.BIT.dss = handle->dataWidth; + handle->baseAddress->SPICR1.BIT.bitend = handle->endian; + handle->baseAddress->SPICR0.BIT.sph = handle->clkPhase; + handle->baseAddress->SPICR0.BIT.spo = handle->clkPolarity; + handle->baseAddress->SPICR1.BIT.waitval = handle->waitVal; + /* Setting freqScr */ + temp = ((unsigned int)handle->freqScr) << SPI_CR0_SCR_POS; + cr0Reg = (handle->baseAddress->SPICR0.reg & (~SPI_CR0_SCR_MASK)) | temp; + handle->baseAddress->SPICR0.reg = cr0Reg; + + /* Modulo 2 to get an even number */ + if ((handle->freqCpsdvsr % 2) == 0) { + handle->baseAddress->SPICPSR.BIT.cpsdvsr = handle->freqCpsdvsr; + } else { + handle->baseAddress->SPICPSR.BIT.cpsdvsr = handle->freqCpsdvsr - 1; + } + /* Setting the Interrupt and DMA Thresholds */ + if (handle->xFerMode == HAL_XFER_MODE_INTERRUPTS) { + handle->baseAddress->SPITXFIFOCR.BIT.txintsize = handle->txIntSize; + handle->baseAddress->SPIRXFIFOCR.BIT.rxintsize = handle->rxIntSize; + } else if (handle->xFerMode == HAL_XFER_MODE_DMA) { + handle->baseAddress->SPITXFIFOCR.BIT.dmatxbrsize = handle->txDMABurstSize; + handle->baseAddress->SPIRXFIFOCR.BIT.dmarxbrsize = handle->rxDMABurstSize; + } else { + ; + } + + return BASE_STATUS_OK; +} + +/** + * @brief Callback Function Registration. + * @param handle SPI handle. + * @param callbackID Callback function ID.. + * @param pcallback Pointer to the address of the registered callback function. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_RegisterCallback(SPI_Handle *handle, + HAL_SPI_CallbackID callbackID, + SPI_CallbackFuncType pcallback) +{ + BASE_StatusType ret = BASE_STATUS_OK; + SPI_ASSERT_PARAM(handle != NULL && pcallback != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + + if (handle->state == HAL_SPI_STATE_READY) { + switch (callbackID) { + case SPI_TX_COMPLETE_CB_ID : + handle->userCallBack.TxCpltCallback = pcallback; + break; + case SPI_RX_COMPLETE_CB_ID : + handle->userCallBack.RxCpltCallback = pcallback; + break; + case SPI_TX_RX_COMPLETE_CB_ID : + handle->userCallBack.TxRxCpltCallback = pcallback; + break; + case SPI_ERROR_CB_ID : + handle->userCallBack.ErrorCallback = pcallback; + break; + case SPI_CS_CB_ID: + handle->userCallBack.CsCtrlCallback = pcallback; + break; + default : + handle->errorCode = BASE_STATUS_ERROR; + ret = BASE_STATUS_ERROR; + break; + } + } else { + handle->errorCode = BASE_STATUS_ERROR; + ret = BASE_STATUS_ERROR; + } + return ret; +} + +/** + * @brief Receiving data in blocking mode. + * @param handle SPI handle. + * @param rData Address of the data buff to be Receiving. + * @param dataSize Number of the data to be Receiving. + * @param timeout Timeout period,unit: ms. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_ReadBlocking(SPI_Handle *handle, + unsigned char *rData, + unsigned int dataSize, + unsigned int timeout) +{ + SPI_ASSERT_PARAM(handle != NULL && rData != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + SPI_PARAM_CHECK_WITH_RET(handle->state == HAL_SPI_STATE_READY, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + + handle->state = HAL_SPI_STATE_BUSY_RX; + /* Configuring SPI transmission parameters */ + ConfigTransmissionParameter(handle, rData, NULL, dataSize); + ClearSpiRxFifo(handle); /* If there is residual data in the read FIFO, clear the data. */ + if (handle->mode == HAL_SPI_MASTER) { + ReadWriteBlocking(handle, timeout); + } else { + ReadBlocking(handle, timeout); + } + if (handle->errorCode != BASE_STATUS_OK) { + if (handle->userCallBack.ErrorCallback != NULL) { + handle->userCallBack.ErrorCallback(handle); + } + return handle->errorCode; + } + if (handle->userCallBack.RxCpltCallback != NULL) { + handle->userCallBack.RxCpltCallback(handle); + } + return BASE_STATUS_OK; +} + +/** + * @brief Send data in blocking mode. + * @param handle SPI handle. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be sent. + * @param timeout Timeout period,unit: ms. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_WriteBlocking(SPI_Handle *handle, + unsigned char *wData, + unsigned int dataSize, + unsigned int timeout) +{ + SPI_ASSERT_PARAM(handle != NULL && wData != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + + SPI_PARAM_CHECK_WITH_RET(handle->state == HAL_SPI_STATE_READY, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + + handle->state = HAL_SPI_STATE_BUSY_TX; + /* Configuring SPI transmission parameters */ + ConfigTransmissionParameter(handle, NULL, wData, dataSize); + ClearSpiRxFifo(handle); /* If there is residual data in the read FIFO, clear the data. */ + ReadWriteBlocking(handle, timeout); + if (handle->errorCode != BASE_STATUS_OK) { + if (handle->userCallBack.ErrorCallback != NULL) { + handle->userCallBack.ErrorCallback(handle); + } + return handle->errorCode; + } + if (handle->userCallBack.TxCpltCallback != NULL) { + handle->userCallBack.TxCpltCallback(handle); + } + return BASE_STATUS_OK; +} + +/** + * @brief Receiving and send data in blocking mode. + * @param handle SPI handle. + * @param rData Address of the data buff to be Receiving. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be Receivingd and sent. + * @param timeout Timeout period,unit: ms. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_WriteReadBlocking(SPI_Handle *handle, + unsigned char *rData, + unsigned char *wData, + unsigned int dataSize, + unsigned int timeout) +{ + SPI_ASSERT_PARAM(handle != NULL && rData != NULL && wData != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + + SPI_PARAM_CHECK_WITH_RET(handle->state == HAL_SPI_STATE_READY, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + + handle->state = HAL_SPI_STATE_BUSY_TX_RX; + /* Configuring SPI transmission parameters */ + ConfigTransmissionParameter(handle, rData, wData, dataSize); + ClearSpiRxFifo(handle); /* If there is residual data in the read FIFO, clear the data. */ + ReadWriteBlocking(handle, timeout); + if (handle->errorCode != BASE_STATUS_OK) { + if (handle->userCallBack.ErrorCallback != NULL) { + handle->userCallBack.ErrorCallback(handle); + } + return handle->errorCode; + } + if (handle->userCallBack.TxRxCpltCallback != NULL) { + handle->userCallBack.TxRxCpltCallback(handle); + } + return BASE_STATUS_OK; +} + +/** + * @brief Receiving data in interrupts mode. + * @param handle SPI handle. + * @param rData Address of the data buff to be Receiving. + * @param dataSize Number of the data to be Receiving. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_ReadIT(SPI_Handle *handle, unsigned char *rData, unsigned int dataSize) +{ + SPI_ASSERT_PARAM(handle != NULL && rData != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + + SPI_PARAM_CHECK_WITH_RET(handle->state == HAL_SPI_STATE_READY, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + + handle->state = HAL_SPI_STATE_BUSY_RX; + ConfigTransmissionParameter(handle, rData, NULL, dataSize); + ClearSpiRxFifo(handle); /* If there is residual data in the read FIFO, clear the data. */ + SpiCsControl(handle, SPI_CHIP_SELECT); + if (!handle->baseAddress->SPICR1.BIT.sse) { + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_SET; + } + /* Enable related interrupts. */ + if (handle->mode == HAL_SPI_MASTER) { + /* 0x0F indicate enables all interrupt. */ + handle->baseAddress->SPIIMSC.reg = 0x0F; + } else { + /* 0x07 indicate enables the RX FIFO, RX timeout, and RX overflow interrupt. */ + handle->baseAddress->SPIIMSC.reg = 0x07; + } + return BASE_STATUS_OK; +} + +/** + * @brief Send data in interrupts mode. + * @param handle SPI handle. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_WriteIT(SPI_Handle *handle, unsigned char *wData, unsigned int dataSize) +{ + SPI_ASSERT_PARAM(handle != NULL && wData != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + + SPI_PARAM_CHECK_WITH_RET(handle->state == HAL_SPI_STATE_READY, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + + handle->state = HAL_SPI_STATE_BUSY_TX; + ConfigTransmissionParameter(handle, NULL, wData, dataSize); + ClearSpiRxFifo(handle); /* If there is residual data in the read FIFO, clear the data. */ + /* interrupt enable */ + SpiCsControl(handle, SPI_CHIP_SELECT); + if (!handle->baseAddress->SPICR1.BIT.sse) { + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_SET; + } + /* 0x0F indicate enables all interrupt. */ + handle->baseAddress->SPIIMSC.reg = 0x0F; + + return BASE_STATUS_OK; +} + +/** + * @brief Receiving and send data in interrupts mode. + * @param handle SPI handle. + * @param rData Address of the data buff to be Receiving. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be Receiving and sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_WriteReadIT(SPI_Handle *handle, + unsigned char *rData, + unsigned char *wData, + unsigned int dataSize) +{ + SPI_ASSERT_PARAM(handle != NULL && rData != NULL && wData != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + + SPI_PARAM_CHECK_WITH_RET(handle->state == HAL_SPI_STATE_READY, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + + handle->state = HAL_SPI_STATE_BUSY_TX_RX; + ConfigTransmissionParameter(handle, rData, wData, dataSize); + ClearSpiRxFifo(handle); /* If there is residual data in the read FIFO, clear the data. */ + SpiCsControl(handle, SPI_CHIP_SELECT); + if (!handle->baseAddress->SPICR1.BIT.sse) { + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_SET; + } + /* 0x0F indicate enables all interrupt. */ + handle->baseAddress->SPIIMSC.reg = 0x0F; + + return BASE_STATUS_OK; +} + +/** + * @brief Wait until the SPI data transmission is complete. + * @param handle SPI handle. + * @retval None. + */ +static void WaitComplete(void *handle) +{ + SPI_ASSERT_PARAM(handle != NULL); + SPI_Handle *spiHandle = (SPI_Handle *)(handle); + SPI_ASSERT_PARAM(IsSPIInstance(spiHandle->baseAddress)); + while (true) { + /* Wait for the write operation to complete */ + if (spiHandle->baseAddress->SPISR.BIT.bsy == BASE_CFG_UNSET && + spiHandle->baseAddress->SPISR.BIT.tfe == BASE_CFG_SET && + spiHandle->baseAddress->SPISR.BIT.rne == BASE_CFG_UNSET) { + break; + } + } +} + +/** + * @brief SPI DMA read completion callback function. + * @param handle SPI handle. + * @retval None + */ +static void ReadDmaFinishFun(void *handle) +{ + SPI_ASSERT_PARAM(handle != NULL); + SPI_Handle *spiHandle = (SPI_Handle *)(handle); + SPI_ASSERT_PARAM(IsSPIInstance(spiHandle->baseAddress)); + /* Waiting for SPI data transfer to complete */ + WaitComplete(spiHandle); + SpiCsControl(spiHandle, SPI_CHIP_DESELECT); + + if (spiHandle->state == HAL_SPI_STATE_BUSY_RX) { + if (spiHandle->userCallBack.RxCpltCallback != NULL) { + spiHandle->userCallBack.RxCpltCallback(spiHandle); + } + } + + if (spiHandle->state == HAL_SPI_STATE_BUSY_TX_RX) { + if (spiHandle->userCallBack.TxRxCpltCallback != NULL) { + spiHandle->userCallBack.TxRxCpltCallback(spiHandle); + } + } + + if (spiHandle->state == HAL_SPI_STATE_BUSY_TX) { + if (spiHandle->userCallBack.TxCpltCallback != NULL) { + spiHandle->userCallBack.TxCpltCallback(spiHandle); + } + } + + spiHandle->state = HAL_SPI_STATE_READY; + /* Disable rx fifo DMA */ + spiHandle->baseAddress->SPIDMACR.BIT.rxdmae = BASE_CFG_UNSET; +} + +/** + * @brief SPI DMA write completion callback function. + * @param handle SPI handle. + * @retval None + */ +static void WriteDmaFinishFun(void *handle) +{ + SPI_ASSERT_PARAM(handle != NULL); + SPI_Handle *spiHandle = (SPI_Handle *)(handle); + SPI_ASSERT_PARAM(IsSPIInstance(spiHandle->baseAddress)); + /* Waiting for SPI data transfer to complete */ + WaitComplete(spiHandle); + SpiCsControl(spiHandle, SPI_CHIP_DESELECT); + /* Disable tx fifo DMA */ + spiHandle->baseAddress->SPIDMACR.BIT.txdmae = BASE_CFG_UNSET; + if (spiHandle->userCallBack.TxCpltCallback != NULL && spiHandle->state == HAL_SPI_STATE_READY) { + spiHandle->userCallBack.TxCpltCallback(spiHandle); + } + if (spiHandle->frameFormat == HAL_SPI_MODE_MICROWIRE) { + spiHandle->state = HAL_SPI_STATE_READY; + } +} + +/** + * @brief SPI DMA error callback function. + * @param handle SPI handle. + * @retval None + */ +static void DmaErrorFun(void *handle) +{ + SPI_ASSERT_PARAM(handle != NULL); + SPI_Handle *spiHandle = (SPI_Handle *)(handle); + SPI_ASSERT_PARAM(IsSPIInstance(spiHandle->baseAddress)); + /* Disable rx and tx fifo DMA */ + spiHandle->baseAddress->SPIDMACR.reg = 0; + SpiCsControl(spiHandle, SPI_CHIP_DESELECT); + + if (spiHandle->userCallBack.ErrorCallback != NULL) { + spiHandle->userCallBack.ErrorCallback(spiHandle); + } + spiHandle->state = HAL_SPI_STATE_READY; +} + +/** + * @brief DMA enable Configuration. + * @param handle SPI handle. + * @retval None + */ +static void EnableDma(SPI_Handle *handle) +{ + handle->baseAddress->SPIIMSC.reg = 0x0; + SpiCsControl(handle, SPI_CHIP_SELECT); + if (!handle->baseAddress->SPICR1.BIT.sse) { + handle->baseAddress->SPICR1.BIT.sse = BASE_CFG_SET; + } + handle->baseAddress->SPIDMACR.reg = SPI_DMA_FIFO_ENABLE; +} + +/** + * @brief SPI read and write configures the DMA for channel callback functions. + * @param handle SPI handle. + * @retval None + */ +static void SetDmaCallBack(SPI_Handle *handle) +{ + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->rxDmaCh].ChannelFinishCallBack = ReadDmaFinishFun; + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->rxDmaCh].ChannelErrorCallBack = DmaErrorFun; + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->txDmaCh].ChannelFinishCallBack = WriteDmaFinishFun; + handle->dmaHandle->userCallBack.DMA_CallbackFuns[handle->txDmaCh].ChannelErrorCallBack = DmaErrorFun; +} + +/** + * @brief Receiving data in DMA mode. + * @param handle SPI handle. + * @param rData Address of the data buff to be Receiving. + * @param dataSize Number of the data to be Receiving. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_ReadDMA(SPI_Handle *handle, unsigned char *rData, unsigned int dataSize) +{ + static unsigned short writeVal = 0; + BASE_StatusType ret; + + SPI_ASSERT_PARAM(handle != NULL && rData != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + SPI_PARAM_CHECK_WITH_RET(handle->txDmaCh < CHANNEL_MAX_NUM, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(handle->rxDmaCh < CHANNEL_MAX_NUM, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(handle->state == HAL_SPI_STATE_READY, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + + handle->state = HAL_SPI_STATE_BUSY_RX; + /* Configuring SPI transmission parameters */ + ConfigTransmissionParameter(handle, rData, NULL, dataSize); + ClearSpiRxFifo(handle); /* If there is residual data in the read FIFO, clear the data. */ + SetDmaCallBack(handle); + /* To set the auto-increment mode of the source and destination addresses */ + handle->dmaHandle->DMA_Channels[handle->rxDmaCh].srcAddrInc = DMA_ADDR_UNALTERED; + handle->dmaHandle->DMA_Channels[handle->rxDmaCh].destAddrInc = DMA_ADDR_INCREASE; + handle->dmaHandle->DMA_Channels[handle->txDmaCh].srcAddrInc = DMA_ADDR_UNALTERED; + handle->dmaHandle->DMA_Channels[handle->txDmaCh].destAddrInc = DMA_ADDR_UNALTERED; + + /* DMA rx channel Interrupt Transfer */ + ret = HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t)&(handle->baseAddress->SPIDR.reg), + (uintptr_t)handle->rxBuff, handle->transferSize, handle->rxDmaCh); + if (ret != BASE_STATUS_OK) { + handle->state = HAL_SPI_STATE_READY; + return ret; + } + /* DMA tx channel Interrupt Transfer */ + if (handle->mode == HAL_SPI_MASTER) { + ret = HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t)&writeVal, (uintptr_t)&(handle->baseAddress->SPIDR.reg), + handle->transferSize, handle->txDmaCh); + if (ret != BASE_STATUS_OK) { + handle->state = HAL_SPI_STATE_READY; + return ret; + } + } + EnableDma(handle); + return ret; +} + +/** + * @brief Send data in DMA mode. + * @param handle SPI handle. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_WriteDMA(SPI_Handle *handle, unsigned char *wData, unsigned int dataSize) +{ + static unsigned short readVal; + BASE_StatusType ret; + + SPI_ASSERT_PARAM(handle != NULL && wData != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + SPI_PARAM_CHECK_WITH_RET(handle->txDmaCh < CHANNEL_MAX_NUM, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(handle->rxDmaCh < CHANNEL_MAX_NUM, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(handle->state == HAL_SPI_STATE_READY, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + + handle->state = HAL_SPI_STATE_BUSY_TX; + /* Configuring SPI transmission parameters */ + ConfigTransmissionParameter(handle, NULL, wData, dataSize); + ClearSpiRxFifo(handle); /* If there is residual data in the read FIFO, clear the data. */ + SetDmaCallBack(handle); + /* To set the auto-increment mode of the source and destination addresses */ + handle->dmaHandle->DMA_Channels[handle->rxDmaCh].srcAddrInc = DMA_ADDR_UNALTERED; + handle->dmaHandle->DMA_Channels[handle->rxDmaCh].destAddrInc = DMA_ADDR_UNALTERED; + handle->dmaHandle->DMA_Channels[handle->txDmaCh].srcAddrInc = DMA_ADDR_INCREASE; + handle->dmaHandle->DMA_Channels[handle->txDmaCh].destAddrInc = DMA_ADDR_UNALTERED; + /* DMA tx channel Interrupt Transfer */ + ret = HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t)handle->txBuff, + (uintptr_t)&(handle->baseAddress->SPIDR.reg), handle->transferSize, handle->txDmaCh); + if (ret != BASE_STATUS_OK) { + handle->state = HAL_SPI_STATE_READY; + return ret; + } + /* DMA rx channel Interrupt Transfer */ + ret = HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t)&(handle->baseAddress->SPIDR.reg), + (uintptr_t)&readVal, handle->transferSize, handle->rxDmaCh); + if (ret != BASE_STATUS_OK) { + handle->state = HAL_SPI_STATE_READY; + return ret; + } + EnableDma(handle); + return ret; +} + +/** + * @brief Receiving and send data in DMA mode. + * @param handle SPI handle. + * @param rData Address of the data buff to be Receiving. + * @param wData Address of the data buff to be sent. + * @param dataSize Number of the data to be Receiving and sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_WriteReadDMA(SPI_Handle *handle, + unsigned char *rData, + unsigned char *wData, + unsigned int dataSize) +{ + BASE_StatusType ret; + + SPI_ASSERT_PARAM(handle != NULL && rData != NULL && wData != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + SPI_PARAM_CHECK_WITH_RET(handle->txDmaCh < CHANNEL_MAX_NUM, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(handle->rxDmaCh < CHANNEL_MAX_NUM, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(handle->state == HAL_SPI_STATE_READY, BASE_STATUS_ERROR); + SPI_PARAM_CHECK_WITH_RET(dataSize > 0, BASE_STATUS_ERROR); + + handle->state = HAL_SPI_STATE_BUSY_TX_RX; + /* Configuring SPI transmission parameters */ + ConfigTransmissionParameter(handle, rData, wData, dataSize); + ClearSpiRxFifo(handle); /* If there is residual data in the read FIFO, clear the data. */ + SetDmaCallBack(handle); + /* To set the auto-increment mode of the source and destination addresses */ + handle->dmaHandle->DMA_Channels[handle->rxDmaCh].srcAddrInc = DMA_ADDR_UNALTERED; + handle->dmaHandle->DMA_Channels[handle->rxDmaCh].destAddrInc = DMA_ADDR_INCREASE; + handle->dmaHandle->DMA_Channels[handle->txDmaCh].srcAddrInc = DMA_ADDR_INCREASE; + handle->dmaHandle->DMA_Channels[handle->txDmaCh].destAddrInc = DMA_ADDR_UNALTERED; + /* DMA rx channel Interrupt Transfer */ + ret = HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t)&(handle->baseAddress->SPIDR.reg), + (uintptr_t)handle->rxBuff, handle->transferSize, handle->rxDmaCh); + if (ret != BASE_STATUS_OK) { + handle->state = HAL_SPI_STATE_READY; + return ret; + } + /* DMA tx channel Interrupt Transfer */ + ret = HAL_DMA_StartIT(handle->dmaHandle, (uintptr_t)handle->txBuff, + (uintptr_t)&(handle->baseAddress->SPIDR.reg), handle->transferSize, handle->txDmaCh); + if (ret != BASE_STATUS_OK) { + handle->state = HAL_SPI_STATE_READY; + return ret; + } + EnableDma(handle); + return ret; +} + +/** + * @brief Stop DMA transfer. + * @param handle SPI handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_DMAStop(SPI_Handle *handle) +{ + SPI_ASSERT_PARAM(handle != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + BASE_StatusType ret; + + ret = HAL_DMA_StopChannel(handle->dmaHandle, handle->txDmaCh); + if (ret != BASE_STATUS_OK) { + return ret; + } + ret = HAL_DMA_StopChannel(handle->dmaHandle, handle->rxDmaCh); + return ret; +} + +/** + * @brief CS Channel Configuration. + * @param handle SPI handle. + * @param channel SPI CS channel.For details, see the enumeration definition of SPI_ChipSelectChannel. + * @retval BASE status type: OK, ERROR. + */ +BASE_StatusType HAL_SPI_ChipSelectChannelSet(SPI_Handle *handle, SPI_ChipSelectChannel channel) +{ + SPI_ASSERT_PARAM(handle != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + /* Check the validity of the CS parameters. */ + SPI_PARAM_CHECK_WITH_RET(channel >= SPI_CHIP_SELECT_CHANNEL_0 && channel < SPI_CHIP_SELECT_CHANNEL_MAX, + BASE_STATUS_ERROR); + handle->baseAddress->SPICSNSEL.BIT.spi_csn_sel = channel; + return BASE_STATUS_OK; +} + +/** + * @brief Obtains the currently configured CS channel. + * @param handle SPI handle. + * @param channel Pointer to the address for storing the obtained CS channel value. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_SPI_ChipSelectChannelGet(SPI_Handle *handle, SPI_ChipSelectChannel *channel) +{ + SPI_ASSERT_PARAM(handle != NULL && channel != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(handle->baseAddress)); + *channel = handle->baseAddress->SPICSNSEL.BIT.spi_csn_sel; + return BASE_STATUS_OK; +} + +/** + * @brief Interrupt Handling Function. + * @param handle SPI_Handle. + * @retval None. + */ +void HAL_SPI_IrqHandler(void *handle) +{ + SPI_Handle *spiHandle = (SPI_Handle *) handle; + SPI_ASSERT_PARAM(spiHandle != NULL); + SPI_ASSERT_PARAM(IsSPIInstance(spiHandle->baseAddress)); + /* Indicates that there is no interruption. */ + if (spiHandle->baseAddress->SPIMIS.reg == 0) { + return; + } + + /* Generating RX overflow interrupt. */ + if (spiHandle->baseAddress->SPIMIS.BIT.rormis) { + spiHandle->baseAddress->SPIIMSC.reg = 0x0; + /* Clear rx interrupt. */ + spiHandle->baseAddress->SPIICR.BIT.roric = BASE_CFG_SET; + spiHandle->baseAddress->SPIICR.BIT.rtic = BASE_CFG_SET; + + spiHandle->errorCode = BASE_STATUS_ERROR; + spiHandle->state = HAL_SPI_STATE_ERROR; + /* Invoke the error callback function. */ + if (spiHandle->userCallBack.ErrorCallback != NULL) { + spiHandle->userCallBack.ErrorCallback(spiHandle); + } + SpiCsControl(spiHandle, SPI_CHIP_DESELECT); + return; + } + /* 0x02 Receive timeout interrupt, 0x04 receive FIFO interrupt */ + if ((spiHandle->mode == HAL_SPI_SLAVE) && + ((spiHandle->baseAddress->SPIMIS.reg == 0x04) || + (spiHandle->baseAddress->SPIMIS.reg == 0x02))) { + ReadData(spiHandle); + } else { + /* Disable SPI before wirte data */ + if (spiHandle->mode == HAL_SPI_MASTER) { + spiHandle->baseAddress->SPICR1.BIT.sse = BASE_CFG_UNSET; + } + WriteData(spiHandle); + /* Enable SPI after wirte data */ + if (spiHandle->mode == HAL_SPI_MASTER) { + spiHandle->baseAddress->SPICR1.BIT.sse = BASE_CFG_SET; + } + ReadData(spiHandle); + } + SpiRxTxCallack(spiHandle); +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/timer/common/inc/timer.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/timer/common/inc/timer.h new file mode 100644 index 00000000..edd902cd --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/timer/common/inc/timer.h @@ -0,0 +1,112 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file timer.h + * @author MCU Driver Team + * @brief TIMER module driver. + * @details This file provides firmware TIMER Handle structure and Functions + * prototypes to manage the following functionalities of the TIMER. + * + Initialization and de-initialization functions + * + config the register of timer + */ + +#ifndef McuMagicTag_TIMER_H +#define McuMagicTag_TIMER_H + +/* Includes ------------------------------------------------------------------*/ +#include "timer_ip.h" + +/* Macro definitions ---------------------------------------------------------*/ + +/** + * @defgroup TIMER TIMER + * @brief TIMER module. + * @{ + */ + +/** + * @defgroup TIMER_Common TIMER Common + * @brief TIMER common external module. + * @{ + */ + +/** + * @defgroup TIMER_Handle_Definition TIMER Handle Definition + * @{ + */ + +/** + * @brief Time base address and Configuration Structure definition + */ +typedef struct _TIMER_Handle { + TIMER_RegStruct *baseAddress; /**< Base address of timer. */ + TIMER_CountMode cntMode; /**< Timer cnt Mode. */ + TIMER_Mode mode; /**< Timer counting mode selection. */ + TIMER_PrescalerFactor prescaler; /**< Timer prescaler. */ + TIMER_Size size; /**< Timer size 16 or 32 bits. */ + volatile unsigned int load; /**< Period, set the TIMERx_LOAD. */ + volatile unsigned int bgLoad; /**< Backgroud period, set the TIMEx_BGLOAD. */ + bool interruptEn; /**< Interrupt enable or disable. */ + bool adcSocReqEnable; /**< Trigger ADC Enable Sampling. */ + bool dmaReqEnable; /**< Enable bit for DMA single request and DAM burst sampling. */ + TIMER_UserCallBack userCallBack; /**< Callback function of timer. */ + TIMER_ExtendHandle handleEx; /**< TIMER extend handle */ +} TIMER_Handle; + +/** + * @brief Typedef callback function of TIMER + */ +typedef void (*TIMER_CallBackFunc)(void *param); + +/** + * @} + */ + +/** + * @defgroup TIMER_API_Declaration TIMER HAL API + * @{ + */ +BASE_StatusType HAL_TIMER_Init(TIMER_Handle *handle); + +void HAL_TIMER_DeInit(TIMER_Handle *handle); + +void HAL_TIMER_Start(TIMER_Handle *handle); + +void HAL_TIMER_Stop(TIMER_Handle *handle); + +BASE_StatusType HAL_TIMER_Config(TIMER_Handle *handle, TIMER_CFG_TYPE cfgType); + +BASE_StatusType HAL_TIMER_GetConfig(TIMER_Handle *handle); + +BASE_StatusType HAL_TIMER_RegisterCallback(TIMER_Handle *handle, TIMER_InterruptType typeID, + TIMER_CallBackFunc callBackFunc); + +BASE_StatusType HAL_TIMER_UnRegisterCallback(TIMER_Handle *handle, TIMER_InterruptType typeID); + +void HAL_TIMER_IrqHandler(void *handle); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_TIMER_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/timer/inc/timer_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/timer/inc/timer_ip.h new file mode 100644 index 00000000..c1bd05c7 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/timer/inc/timer_ip.h @@ -0,0 +1,621 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file timer_ip.h + * @author MCU Driver Team + * @brief TIMER module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the TIMER. + * + TIMER register mapping structure + * + Direct Configuration Layer functions of TIMER + */ + + +#ifndef McuMagicTag_TIMER_IP_H +#define McuMagicTag_TIMER_IP_H + +/* Includes ------------------------------------------------------------------*/ +#include "baseinc.h" + +/** + * @addtogroup TIMER + * @{ + */ + +/** + * @defgroup TIMER_IP TIMER_IP + * @brief TIMER_IP: timer_v0 + * @{ + */ + +/** + * @defgroup TIMER_Param_Def TIMER Parameters Definition + * @brief Definition of TIMER configuration parameters. + * @{ + */ +#ifdef TIMER_PARAM_CHECK +#define TIMER_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define TIMER_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define TIMER_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define TIMER_ASSERT_PARAM(para) ((void)0U) +#define TIMER_PARAM_CHECK_NO_RET(para) ((void)0U) +#define TIMER_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +/** + * @brief Period min value + */ +#define PERIOD_MIN_VALUE 1 + +/** + * @brief Extent handle definition of timer + */ +typedef struct { +} TIMER_ExtendHandle; + +/** + * @brief TIMER type of user callback function + */ +typedef enum { + TIMER_PERIOD_FIN = 0x00000000U, +} TIMER_InterruptType; + +/** + * @brief TIMER type of user callback function + */ +typedef struct { + void (* TimerPeriodFinCallBack)(void *handle); +} TIMER_UserCallBack; + +/** + * @brief TIMER counting mode definition + */ +typedef enum { + TIMER_COUNT_UP = 0x00000000U, + TIMER_COUNT_DOWN = 0x00000001U, +} TIMER_CountMode; + +/** + * @brief TIMER operating mode definition + */ +typedef enum { + TIMER_MODE_RUN_FREE = 0x00000000U, + TIMER_MODE_RUN_PERIODIC = 0x00000001U, + TIMER_MODE_RUN_ONTSHOT = 0x00000002U, +} TIMER_Mode; + +/** + * @brief TIMER division factor definition + */ +typedef enum { + TIMERPRESCALER_NO_DIV = 0x00000000U, + TIMERPRESCALER_DIV_16 = 0x00000001U, + TIMERPRESCALER_DIV_256 = 0x00000002U, +} TIMER_PrescalerFactor; + +/** + * @brief TIMER counter size definition + */ +typedef enum { + TIMER_SIZE_16BIT = 0x00000000U, + TIMER_SIZE_32BIT = 0x00000001U, +} TIMER_Size; + +/** + * @brief Typedef TIMER Parameter Config type + */ +typedef enum { + TIMER_CFG_LOAD = 0x00000001, + TIMER_CFG_BGLOAD = 0x00000002, + TIMER_CFG_MODE = 0x00000004, + TIMER_CFG_INTERRUPT = 0x00000008, + TIMER_CFG_PRESCALER = 0x00000010, + TIMER_CFG_SIZE = 0x00000020, + TIMER_CFG_DMAADC_SINGLE_REQ = 0x00000040, + TIMER_CFG_DMA_BURST_REQ = 0x00000080, +} TIMER_CFG_TYPE; + +/** + * @} + */ + +/** + * @defgroup TIMER_Reg_Def TIMER Register Definition + * @brief register mapping structure + * @{ + */ + +/** + * @brief TIMER control register structure + */ +typedef union { + unsigned int reg; + struct { + unsigned int oneshot : 1; /**< Counting mode: single counting mode, periodic counting mode. */ + unsigned int timersize : 1; /**< 16-bit/32-bit counter operation mode. */ + unsigned int timerpre : 2; /**< This field is used to set the prescale factor of the timer. */ + unsigned int reserved0 : 1; + unsigned int intenable : 1; /**< TIMERx_RIS interrupt mask. */ + unsigned int timermode : 1; /**< Indicates the count mode of the timer. */ + unsigned int timeren : 1; /**< Timer enable. */ + unsigned int reserved1 : 24; + } BIT; +} volatile TIMER_CONTROL_Reg; + +/** + * @brief TIMER original interrupt register + */ +typedef struct { + unsigned int timerris : 1; /**< Raw interrupt status of timer. */ + unsigned int reserved0 : 31; +} volatile TIMER_RIS_Reg; + +/** + * @brief TIMER interrupt register of shield + */ +typedef struct { + unsigned int timermis : 1; /**< Masked interrupt status of timer. */ + unsigned int reserved0 : 31; +} volatile TIMER_MIS_Reg; + +/** + * @brief TIMER ControlB + */ +typedef union { + unsigned int reg; + struct { + unsigned int dmabreqen : 1; /**< DMA burst request enable. */ + unsigned int dmasreqen : 1; /**< Enable bit for DMA single request and trigger ADC sampling. */ + unsigned int reserved0 : 29; + unsigned int dmaov : 1; /**< DMA request overflow flag. */ + } BIT; +} volatile TIMER_CONTROLB_Reg; + +/** + * @brief TIMER register structure + */ +typedef struct { + unsigned int timer_load; /**< Initial count value register. Offset address: 0x00000000U. */ + unsigned int timer_value; /**< Current count value register. Offset address: 0x00000004U. */ + TIMER_CONTROL_Reg TIMERx_CONTROL; /**< Timer control register. Offset address: 0x00000008U. */ + unsigned int timer_intclr; /**< Interrupt clear register. Offset address: 0x0000000CU. */ + TIMER_RIS_Reg TIMERx_RIS; /**< Raw interrupt register. Offset address: 0x00000010U. */ + TIMER_MIS_Reg TIMERx_MIS; /**< Masked interrupt register. Offset address: 0x00000014U. */ + unsigned int timerbgload; /**< Initial count value register. Offset address: 0x00000018U. */ + TIMER_CONTROLB_Reg TIMERx_CONTROLB; /**< Timerx control register B. Offset address: 0x0000001CU. */ +} volatile TIMER_RegStruct; +/** + * @} + */ + +/* Parameter Check -----------------------------------------------------------*/ +/** + * @brief Verify Timer mode configuration + * @param mode Timer Mode, @ref TIMER_Mode + * @retval true + * @retval false + */ +static inline bool IsTimerMode(TIMER_Mode mode) +{ + return (((mode) == TIMER_MODE_RUN_FREE) || + ((mode) == TIMER_MODE_RUN_PERIODIC) || + ((mode) == TIMER_MODE_RUN_ONTSHOT)); +} + +/** + * @brief Verify Timer count mode configuration + * @param mode Timer count mode, @ref TIMER_CountMode + * @retval true + * @retval false + */ +static inline bool IsTimerCntMode(TIMER_CountMode cntMode) +{ + return (((cntMode) == TIMER_COUNT_UP) || + ((cntMode) == TIMER_COUNT_DOWN)); +} + +/** + * @brief Verify Timer Interrupt Type + * @param mode Timer Interrupt Type, @ref TIMER_InterruptType + * @retval true + * @retval false + */ +static inline bool IsTimerInterruptType(TIMER_InterruptType interruptType) +{ + return ((interruptType) == TIMER_PERIOD_FIN); +} + +/** + * @brief Verify Timer counter size configuration + * @param size Timer Size, @ref TIMER_Size + * @retval true + * @retval false + */ +static inline bool IsTimerSize(TIMER_Size size) +{ + return (((size) == TIMER_SIZE_16BIT) || + ((size) == TIMER_SIZE_32BIT)); +} + +/** + * @brief Verify Timer period configuration + * @param period + * @retval true + * @retval false + */ +static inline bool IsTimerPeriod(unsigned int period) +{ + return ((period) >= PERIOD_MIN_VALUE); +} + +/** + * @brief Verify Timer div configuration + * @param div @see TIMER_PrescalerFactor + * @retval true + * @retval false + */ +static inline bool IsTimerDiv(TIMER_PrescalerFactor div) +{ + return (((div) == TIMERPRESCALER_NO_DIV) || + ((div) == TIMERPRESCALER_DIV_16) || + ((div) == TIMERPRESCALER_DIV_256)); +} + + +/* Direct configuration layer ------------------------------------------------*/ + +/** + * @brief Enable the timer, start to run + * @param timerx Timer register baseAddr + * @retval None + */ +static inline void DCL_TIMER_Enable(TIMER_RegStruct * const timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->TIMERx_CONTROL.BIT.timeren = BASE_CFG_SET; +} + +/** + * @brief Stop the timer + * @param timerx Timer register baseAddr + * @retval None + */ +static inline void DCL_TIMER_Disable(TIMER_RegStruct * const timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->TIMERx_CONTROL.BIT.timeren = BASE_CFG_UNSET; +} + +/** + * @brief Get the timer enable flag + * @param timerx Timer register baseAddr + * @retval None + */ +static inline bool DCL_TIMER_GetTimerEn(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_CONTROL.BIT.timeren; +} + +/** + * @brief Get current counter in timer + * @param timerx Timer register baseAddr + * @retval None + */ +static inline unsigned int DCL_TIMER_GetValue(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->timer_value; +} + +/** + * @brief Set the counter with load，which change timer value immediately + * @param timerx Timer register baseAddr + * @param period the init value of the counter + * @retval None + */ +static inline void DCL_TIMER_SetLoad(TIMER_RegStruct * const timerx, unsigned int period) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + TIMER_PARAM_CHECK_NO_RET(IsTimerPeriod(period)); + timerx->timer_load = period; +} + +/** + * @brief Get the period of counter + * @param timerx Timer register baseAddr + * @retval None + */ +static inline unsigned int DCL_TIMER_GetLoad(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->timer_load; +} + +/** + * @brief Set the counter with period with bgload + * @param timerx Timer register baseAddr + * @param period the init value of the counter + * @retval None + */ +static inline void DCL_TIMER_SetBgLoad(TIMER_RegStruct * const timerx, unsigned int period) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + TIMER_PARAM_CHECK_NO_RET(IsTimerPeriod(period)); + timerx->timerbgload = period; +} + +/** + * @brief Get the bgLoad of timer + * @param timerx Timer register baseAddr + * @retval None + */ +static inline unsigned int DCL_TIMER_GetBgLoad(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->timerbgload; +} + +/** + * @brief Enable timer interrupt + * @param timerx Timer register baseAddr + * @retval None + */ +static inline void DCL_TIMER_InterruptEnable(TIMER_RegStruct * const timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->TIMERx_CONTROL.BIT.intenable = BASE_CFG_SET; +} + +/** + * @brief Disable timer interrupt + * @param timerx Timer register baseAddr + * @retval None + */ +static inline void DCL_TIMER_InterruptDisable(TIMER_RegStruct * const timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->TIMERx_CONTROL.BIT.intenable = BASE_CFG_UNSET; +} + +/** + * @brief Get timer interrupt enable flag + * @param timerx Timer register baseAddr + * @retval None + */ +static inline bool DCL_TIMER_GetInterruptEnableFlag(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_CONTROL.BIT.intenable; +} + +/** + * @brief Set timer size + * @param timerx Timer register baseAddr + * @param size the size of counter, see @ref TIMER_Size + * @retval None + */ +static inline void DCL_TIMER_SetTimerSize(TIMER_RegStruct * const timerx, TIMER_Size size) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + TIMER_PARAM_CHECK_NO_RET(IsTimerSize(size)); + timerx->TIMERx_CONTROL.BIT.timersize = (size == TIMER_SIZE_16BIT) ? BASE_CFG_UNSET : BASE_CFG_SET; +} + +/** + * @brief Set timer size + * @param timerx Timer register baseAddr + * @retval None + */ +static inline TIMER_Size DCL_TIMER_GetTimerSize(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_CONTROL.BIT.timersize; +} + +/** + * @brief Set the counting mode is single counting or periodic counting mode + * @param timerx Timer register baseAddr + * @param mode counter mode, see @ref TIMER_Mode + * @retval None + */ +static inline void DCL_TIMER_SetTimerMode(TIMER_RegStruct * const timerx, TIMER_Mode mode) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + TIMER_PARAM_CHECK_NO_RET(IsTimerMode(mode)); + /* To set the counting mode of a timer. */ + if (mode == TIMER_MODE_RUN_ONTSHOT) { + timerx->TIMERx_CONTROL.BIT.oneshot = BASE_CFG_SET; + } else { + /* Set it to the periodic count mode or free count mode. */ + timerx->TIMERx_CONTROL.BIT.oneshot = BASE_CFG_UNSET; + timerx->TIMERx_CONTROL.BIT.timermode = (mode == TIMER_MODE_RUN_FREE) ? BASE_CFG_UNSET : BASE_CFG_SET; + } +} + +/** + * @brief Get the counting mode is single counting or periodic counting mode + * @param timerx Timer register baseAddr + * @retval TIMER_Mode + */ +static inline TIMER_Mode DCL_TIMER_GetTimerMode(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + if (timerx->TIMERx_CONTROL.BIT.oneshot == BASE_CFG_SET) { + return TIMER_MODE_RUN_ONTSHOT; + } else { + return (timerx->TIMERx_CONTROL.BIT.timermode == BASE_CFG_SET) ? TIMER_MODE_RUN_PERIODIC : TIMER_MODE_RUN_FREE; + } +} + +/** + * @brief Set the prescaler factor of the timer + * @param timerx Timer register baseAddr + * @param factor prescaler factor, see @ref TIMER_PrescalerFactor + * @retval None + */ +static inline void DCL_TIMER_SetTimerPre(TIMER_RegStruct * const timerx, TIMER_PrescalerFactor factor) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + TIMER_PARAM_CHECK_NO_RET(IsTimerDiv(factor)); + timerx->TIMERx_CONTROL.BIT.timerpre = factor; +} + +/** + * @brief Get the prescaler factor of the timer + * @param timerx Timer register baseAddr + * @retval TIMER_PrescalerFactor + */ +static inline TIMER_PrescalerFactor DCL_TIMER_GetTimerPre(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_CONTROL.BIT.timerpre; +} + +/** + * @brief Deinitializes TIMERx_CONTROL. + * @param timerx Timer register baseAddr + * @retval None. + */ +static inline void DCL_TIMER_DeinitTimerControl(TIMER_RegStruct * const timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->TIMERx_CONTROL.reg = BASE_CFG_UNSET; +} + + +/** + * @brief Clear the time irq flag + * @param timerx Timer register baseAddr + * @retval None + */ +static inline void DCL_TIMER_IrqClear(TIMER_RegStruct * const timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->timer_intclr = BASE_CFG_SET; +} + +/** + * @brief Get Original interrupt state + * @param timerx Timer register baseAddr + * @retval bool + */ +static inline bool DCL_TIMER_GetTimerOriginalInterruptState(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_RIS.timerris; +} + +/** + * @brief Get the interrupt status of Timer after shielding + * @param timerx Timer register baseAddr + * @retval bool + */ +static inline bool DCL_TIMER_GetTimerShieldlInterruptState(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_MIS.timermis; +} + +/** + * @brief Get DMA overflow status + * @param timerx Timer register baseAddr + * @retval bool + */ +static inline bool DCL_TIMER_GetTimerDmaOverflowStatus(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_CONTROLB.BIT.dmaov; +} + +/** + * @brief Clear DMA overflow status + * @param timerx Timer register baseAddr + * @retval None + */ +static inline void DCL_TIMER_ClearTimerDmaOverflowStatus(TIMER_RegStruct * const timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->TIMERx_CONTROLB.BIT.dmaov = BASE_CFG_SET; +} + +/** + * @brief Get DMA single request enable status + * @param timerx Timer register baseAddr + * @retval bool + */ +static inline bool DCL_TIMER_GetTimerDmaSingleRequest(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_CONTROLB.BIT.dmasreqen; +} + +/** + * @brief Set DMA single request + * @param timerx Timer register baseAddr + * @param enable DMA/ADC single trigger enable + * @retval None + */ +static inline void DCL_TIMER_SetTimerDmaSingleRequest(TIMER_RegStruct * const timerx, bool enable) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->TIMERx_CONTROLB.BIT.dmasreqen = (unsigned int)enable; +} + +/** + * @brief Get DMA burst request enable status + * @param timerx Timer register baseAddr + * @retval bool + */ +static inline bool DCL_TIMER_GetTimerDmaBurstRequest(const TIMER_RegStruct *timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + return timerx->TIMERx_CONTROLB.BIT.dmabreqen; +} + +/** + * @brief Set DMA burst request + * @param timerx Timer register baseAddr + * @param enable DMA burst trigger enable + * @retval None + */ +static inline void DCL_TIMER_SetTimerDmaBurstRequest(TIMER_RegStruct * const timerx, bool enable) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->TIMERx_CONTROLB.BIT.dmabreqen = (unsigned int)enable; +} + +/** + * @brief Deinitializes TIMERx_CONTROLB. + * @param timerx Timer register baseAddr + * @retval None. + */ +static inline void DCL_TIMER_DeinitTimerControlB(TIMER_RegStruct * const timerx) +{ + TIMER_ASSERT_PARAM(IsTIMERInstance(timerx)); + timerx->TIMERx_CONTROLB.reg = BASE_CFG_UNSET; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_TIMER_IP_H */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/timer/src/timer.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/timer/src/timer.c new file mode 100644 index 00000000..fbe96e13 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/timer/src/timer.c @@ -0,0 +1,267 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file timer.c + * @author MCU Driver Team + * @brief TIMER module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the TIMER. + * + Initialization and de-initialization functions + * + config the register of timer + */ + +/* Includes ------------------------------------------------------------------*/ +#include "timer.h" +#include "interrupt.h" + +/** + * @brief Init the timer + * @param handle Timer Handle + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR parameter check fail + */ +BASE_StatusType HAL_TIMER_Init(TIMER_Handle *handle) +{ + TIMER_ASSERT_PARAM(handle != NULL); + TIMER_ASSERT_PARAM(IsTIMERInstance(handle->baseAddress)); + + TIMER_PARAM_CHECK_WITH_RET(IsTimerPeriod(handle->load), BASE_STATUS_ERROR); + TIMER_PARAM_CHECK_WITH_RET(IsTimerPeriod(handle->bgLoad), BASE_STATUS_ERROR); + TIMER_PARAM_CHECK_WITH_RET(IsTimerMode(handle->mode), BASE_STATUS_ERROR); + TIMER_PARAM_CHECK_WITH_RET(IsTimerSize(handle->size), BASE_STATUS_ERROR); + TIMER_PARAM_CHECK_WITH_RET(IsTimerDiv(handle->prescaler), BASE_STATUS_ERROR); + TIMER_PARAM_CHECK_WITH_RET(IsTimerCntMode(handle->cntMode), BASE_STATUS_ERROR); + /* Initialize the configuration parameters of the timer */ + handle->baseAddress->timer_intclr = BASE_CFG_SET; /* Writing to this register clears interrupt output of timer */ + handle->baseAddress->timer_load = handle->load; + handle->baseAddress->timerbgload = handle->bgLoad; + handle->baseAddress->TIMERx_CONTROL.BIT.timeren = BASE_CFG_DISABLE; + handle->baseAddress->TIMERx_CONTROL.BIT.intenable = handle->interruptEn; + /* Sets the frequency divider and size of the timer module. */ + handle->baseAddress->TIMERx_CONTROL.BIT.timerpre = handle->prescaler; + handle->baseAddress->TIMERx_CONTROL.BIT.timersize = handle->size; + /* Sets the running mode of the timer. */ + if (handle->mode == TIMER_MODE_RUN_ONTSHOT) { + handle->baseAddress->TIMERx_CONTROL.BIT.oneshot = BASE_CFG_SET; + } else { + handle->baseAddress->TIMERx_CONTROL.BIT.oneshot = BASE_CFG_UNSET; + handle->baseAddress->TIMERx_CONTROL.BIT.timermode = + (handle->mode == TIMER_MODE_RUN_FREE) ? BASE_CFG_UNSET : BASE_CFG_SET; + } + /* Request for setting the DMA and ADC. */ + handle->baseAddress->TIMERx_CONTROLB.BIT.dmasreqen = handle->adcSocReqEnable || + handle->dmaReqEnable; + handle->baseAddress->TIMERx_CONTROLB.BIT.dmabreqen = handle->dmaReqEnable; + return BASE_STATUS_OK; +} + +/** + * @brief DeInit the timer + * @param handle Timer Handle + * @retval None + */ +void HAL_TIMER_DeInit(TIMER_Handle *handle) +{ + TIMER_ASSERT_PARAM(handle != NULL); + TIMER_ASSERT_PARAM(IsTIMERInstance(handle->baseAddress)); + /* Clears interrupts and masks interrupts. */ + handle->baseAddress->timer_intclr = BASE_CFG_SET; + handle->baseAddress->TIMERx_CONTROL.BIT.intenable = BASE_CFG_DISABLE; + handle->userCallBack.TimerPeriodFinCallBack = NULL; /* Clear all user call back function. */ + /* The counter loading value is set to 0, and the timer is disabled. */ + handle->baseAddress->timer_load = 0; + handle->baseAddress->timerbgload = 0; + handle->baseAddress->TIMERx_CONTROL.reg = 0; + handle->baseAddress->TIMERx_CONTROLB.reg = 0; +} + +/** + * @brief Config Timer + * @param handle Timer Handle + * @param cfgType Timer configures, @ref TIMER_CFG_TYPE + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR parameter check fail + */ +BASE_StatusType HAL_TIMER_Config(TIMER_Handle *handle, TIMER_CFG_TYPE cfgType) +{ + TIMER_ASSERT_PARAM(handle != NULL); + TIMER_ASSERT_PARAM(IsTIMERInstance(handle->baseAddress)); + + switch (cfgType) { + /* Configure timer count. */ + case TIMER_CFG_LOAD: + TIMER_PARAM_CHECK_WITH_RET(IsTimerPeriod(handle->load), BASE_STATUS_ERROR); + handle->baseAddress->timer_load = handle->load; + handle->bgLoad = handle->load; + break; + /* Configure timer reload count. */ + case TIMER_CFG_BGLOAD: + TIMER_PARAM_CHECK_WITH_RET(IsTimerPeriod(handle->bgLoad), BASE_STATUS_ERROR); + handle->baseAddress->timerbgload = handle->bgLoad; + break; + /* Configure timer work mode. */ + case TIMER_CFG_MODE: + DCL_TIMER_SetTimerMode(handle->baseAddress, handle->mode); + break; + /* Configure timer interrupt. */ + case TIMER_CFG_INTERRUPT: + handle->baseAddress->TIMERx_CONTROL.BIT.intenable = handle->interruptEn; + break; + /* Configure timer prescaler. */ + case TIMER_CFG_PRESCALER: + TIMER_PARAM_CHECK_WITH_RET(IsTimerDiv(handle->prescaler), BASE_STATUS_ERROR); + handle->baseAddress->TIMERx_CONTROL.BIT.timerpre = handle->prescaler; + break; + /* Configure the size of the timer counter. */ + case TIMER_CFG_SIZE: + TIMER_PARAM_CHECK_WITH_RET(IsTimerSize(handle->size), BASE_STATUS_ERROR); + handle->baseAddress->TIMERx_CONTROL.BIT.timersize = handle->size; + break; + /* Configure the ADC request. */ + case TIMER_CFG_DMAADC_SINGLE_REQ: + handle->baseAddress->TIMERx_CONTROLB.BIT.dmasreqen = handle->adcSocReqEnable || + handle->dmaReqEnable; + break; + /* Configure the DMA request. */ + case TIMER_CFG_DMA_BURST_REQ: + handle->baseAddress->TIMERx_CONTROLB.BIT.dmabreqen = handle->dmaReqEnable; + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief Get Timer Config + * @param handle Timer Handle + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Parameter check fail + */ +BASE_StatusType HAL_TIMER_GetConfig(TIMER_Handle *handle) +{ + TIMER_ASSERT_PARAM(handle != NULL); + TIMER_ASSERT_PARAM(IsTIMERInstance(handle->baseAddress)); + + handle->load = handle->baseAddress->timer_load; + handle->bgLoad = handle->baseAddress->timerbgload; + handle->mode = handle->baseAddress->TIMERx_CONTROL.BIT.timermode; + handle->size = handle->baseAddress->TIMERx_CONTROL.BIT.timersize; + handle->prescaler = handle->baseAddress->TIMERx_CONTROL.BIT.timerpre; + handle->interruptEn = handle->baseAddress->TIMERx_CONTROL.BIT.intenable; + handle->adcSocReqEnable = handle->baseAddress->TIMERx_CONTROLB.BIT.dmasreqen; + handle->dmaReqEnable = handle->baseAddress->TIMERx_CONTROLB.BIT.dmasreqen || + handle->baseAddress->TIMERx_CONTROLB.BIT.dmabreqen; + handle->mode = DCL_TIMER_GetTimerMode(handle->baseAddress); + + return BASE_STATUS_OK; +} + +/** + * @brief Start timer. + * @param handle Timer Handle + * @retval None + */ +void HAL_TIMER_Start(TIMER_Handle *handle) +{ + TIMER_ASSERT_PARAM(handle != NULL); + TIMER_ASSERT_PARAM(IsTIMERInstance(handle->baseAddress)); + + handle->baseAddress->TIMERx_CONTROL.BIT.timeren = BASE_CFG_SET; +} + +/** + * @brief Stop timer. + * @param handle Timer Handle + * @retval None + * @note Timer in OneShot Mode also need stop + */ +void HAL_TIMER_Stop(TIMER_Handle *handle) +{ + TIMER_ASSERT_PARAM(handle != NULL); + TIMER_ASSERT_PARAM(IsTIMERInstance(handle->baseAddress)); + + handle->baseAddress->TIMERx_CONTROL.BIT.timeren = BASE_CFG_UNSET; + handle->baseAddress->timer_intclr = BASE_CFG_SET; +} + +/** + * @brief TIMER Interrupt service processing function. + * @param handle TIMER handle. + * @retval None. + */ +void HAL_TIMER_IrqHandler(void *handle) +{ + TIMER_ASSERT_PARAM(handle != NULL); + TIMER_Handle *timerHandle = (TIMER_Handle *)handle; + TIMER_ASSERT_PARAM(IsTIMERInstance(timerHandle->baseAddress)); + /* Check interrupt type */ + if (timerHandle->baseAddress->TIMERx_MIS.timermis == 0x1) { + /* DMA overflow interrupt */ + timerHandle->baseAddress->timer_intclr = BASE_CFG_ENABLE; + /* Call the period finish callback function of the user. */ + if (timerHandle->userCallBack.TimerPeriodFinCallBack != NULL) { + timerHandle->userCallBack.TimerPeriodFinCallBack(timerHandle); + } + } + return; +} + +/** + * @brief Register the callback function of TIMER handle. + * @param handle Timer Handle + * @param typeID Timer interrupt typr, @ref TIMER_InterruptType + * @param callBackFunc CallBack function of user, @ref TIMER_CallBackFunc + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Parameter check fail + */ +BASE_StatusType HAL_TIMER_RegisterCallback(TIMER_Handle *handle, TIMER_InterruptType typeID, + TIMER_CallBackFunc callBackFunc) +{ + TIMER_ASSERT_PARAM(handle != NULL); + TIMER_ASSERT_PARAM(callBackFunc != NULL); + + switch (typeID) { + case TIMER_PERIOD_FIN: + handle->userCallBack.TimerPeriodFinCallBack = callBackFunc; /* User timer period finish call back. */ + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief Unregister the callback function of TIMER handle. + * @param handle Timer Handle + * @param typeID CallBack function of user, @ref TIMER_InterruptType + * @retval BASE_STATUS_OK Success + * @retval BASE_STATUS_ERROR Parameter check fail + */ +BASE_StatusType HAL_TIMER_UnRegisterCallback(TIMER_Handle *handle, TIMER_InterruptType typeID) +{ + TIMER_ASSERT_PARAM(handle != NULL); + /* Determine the callback function type. */ + switch (typeID) { + case TIMER_PERIOD_FIN: + handle->userCallBack.TimerPeriodFinCallBack = NULL; /* Periodic callback for timer period finish. */ + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/tsensor/common/inc/tsensor.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/tsensor/common/inc/tsensor.h new file mode 100644 index 00000000..754e7791 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/tsensor/common/inc/tsensor.h @@ -0,0 +1,53 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file tsensor.h + * @author MCU Driver Team + * @brief tsensor module driver + * @details This file provides API to manage tsensor. + */ + +/* Macro definitions */ +#ifndef McuMagicTag_TSENSOR_H +#define McuMagicTag_TSENSOR_H + +#include "tsensor_ip.h" + +/** + * @defgroup TSENSOR TSENSOR + * @brief TSENSOR module. + * @{ + */ + +/** + * @defgroup TSENSOR_Common TSENSOR Common + * @brief TSENSOR common external module. + * @{ + */ + +void HAL_TSENSOR_Init(void); +void HAL_TSENSOR_Deinit(void); +unsigned int HAL_TSENSOR_GetResult(void); +float HAL_TSENSOR_GetTemperature(void); +/** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/tsensor/inc/tsensor_ex.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/tsensor/inc/tsensor_ex.h new file mode 100644 index 00000000..c4fd6389 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/tsensor/inc/tsensor_ex.h @@ -0,0 +1,49 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file tsensor_ex.h + * @author MCU Driver Team + * @brief tsensor module driver + * @details This file provides dcl functions to manage tsensor and definition of + * specific parameters. + */ + +/* Macro definitions */ +#ifndef McuMagicTag_TSENSOR_EX_H +#define McuMagicTag_TSENSOR_EX_H + +#include "tsensor.h" + +/** + * @addtogroup TSENSOR + * @{ + */ + +/** + * @defgroup TSENSOR_IP TSENSOR_IP + * @brief TSENSOR_IP: tsensor_v0. + * @{ + */ +BASE_StatusType HAL_TSENSOR_CalibrateHosc(void); +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_TSENSOR_EX_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/tsensor/inc/tsensor_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/tsensor/inc/tsensor_ip.h new file mode 100644 index 00000000..c8f70ae0 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/tsensor/inc/tsensor_ip.h @@ -0,0 +1,64 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file tsensor_ip.h + * @author MCU Driver Team + * @brief tsensor module driver + * @details This file provides dcl functions to manage tsensor and definition of + * specific parameters. + */ + +/* Macro definitions */ +#ifndef McuMagicTag_TSENSOR_IP_H +#define McuMagicTag_TSENSOR_IP_H + +#include "baseinc.h" + +/** + * @addtogroup TSENSOR + * @{ + */ + +/** + * @defgroup TSENSOR_IP TSENSOR_IP + * @brief TSENSOR_IP: tsensor_v0. + * @{ + */ + +typedef union { + unsigned int reg; + struct { + unsigned int tsen_ana_en : 1; + unsigned int reserved0 : 31; + } BIT; +} volatile TSENSOR_CTRL_REG; + +/** + * @brief Define the tsensor resistor struct. + */ +typedef struct { + TSENSOR_CTRL_REG TSENSOR_CTRL; /**< Offset address: 0x00000000U */ +} volatile TSENSOR_RegStruct; + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_TSENSOR_IP_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/tsensor/src/tsensor.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/tsensor/src/tsensor.c new file mode 100644 index 00000000..746c7d5a --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/tsensor/src/tsensor.c @@ -0,0 +1,150 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file tsensor.c + * @author MCU Driver Team + * @brief tsensor module driver + * @details This file provides functions to manage tsensor and definition of + * specific parameters. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "crg.h" +#include "adc.h" +#include "adc_tsensor.h" +#include "fotp_info_read.h" +#include "tsensor.h" + +#define SAMPLE_MAX 4096 +#define NUM 16 +#define TSENSOR_SOC_NUM ADC_SOC_NUM15 /* This parameter can be modified according to the actual situation */ + +/** + * @brief ADC for tsensor clock initialization. + * @param None. + * @retval None. + */ +static void ADC_ClkEnable(void) +{ + HAL_CRG_IpEnableSet(ADCX_TSENSOR_BASE, IP_CLK_ENABLE); + HAL_CRG_IpClkSelectSet(ADCX_TSENSOR_BASE, CRG_ADC_CLK_SELECT_PLL_DIV); + HAL_CRG_IpClkDivSet(ADCX_TSENSOR_BASE, CRG_ADC_DIV_5); +} + +/** + * @brief ADC for tsensor sample configuration. + * @param None. + * @retval None. + */ +static void TSENSOR_SampleConfigure(void) +{ + ADC_Handle adcHandle = {0}; + adcHandle.baseAddress = ADCX_TSENSOR; + adcHandle.socPriority = ADC_PRIMODE_ALL_ROUND; + adcHandle.handleEx.vrefBuf = ADC_VREF_2P5V; + HAL_ADC_Init(&adcHandle); + + SOC_Param socParam = {0}; + socParam.adcInput = TSENSOR_SAMPLE_CH; + socParam.sampleHoldTime = 2; /* hold time is set as default value 2 */ + socParam.sampleTotalTime = 9; /* charge time is set as default value 9 */ + socParam.finishMode = ADC_SOCFINISH_NONE; + socParam.softTrigSource = ADC_TRIGSOC_SOFT; + socParam.intTrigSource = ADC_TRIGSOC_NONEINT; + socParam.periphTrigSource = ADC_TRIGSOC_NONEPERIPH; + unsigned int soc = TSENSOR_SOC_NUM; + HAL_ADC_ConfigureSoc(&adcHandle, soc, &socParam); + + TSENSOR_RegStruct *tsensor; + tsensor = TSENSOR; + tsensor->TSENSOR_CTRL.BIT.tsen_ana_en = BASE_CFG_ENABLE; + BASE_FUNC_DELAY_US(50); /* waite for 50us until stable */ +} + +/** + * @brief ADC Results Converted to Temperature. + * @param digital digital parameter of tsensor. + * @retval Temperature type: float, temperature of MCU, unit: ℃. + */ +static float TSENSOR_Conversion(unsigned int digital) +{ + float curV = ((float)digital / 4096.0f) * 3.33333f; /* 4096.0 and 3.33333 for voltage conversion */ + float curTemp = g_tsensor[0].vrefTemp + (curV - g_tsensor[0].vrefVoltage) / g_tsensor[0].slope; + return curTemp; +} + +/** + * @brief Configuration of tsensor. + * @param None. + * @retval None. + */ +void HAL_TSENSOR_Init(void) +{ + ADC_ClkEnable(); + TSENSOR_SampleConfigure(); +} + +/** + * @brief Deinitialize of tsensor. + * @param None. + * @retval None. + */ +void HAL_TSENSOR_Deinit(void) +{ + TSENSOR_RegStruct *tsensor; + tsensor = TSENSOR; + tsensor->TSENSOR_CTRL.BIT.tsen_ana_en = BASE_CFG_DISABLE; +} + + +/** + * @brief Get the result from the tsensor. + * @param None. + * @retval result of tsensor. + */ +unsigned int HAL_TSENSOR_GetResult(void) +{ + unsigned int ret = 0; + unsigned int count = 0; + ADC_RegStruct *adcAddr = ADCX_TSENSOR; + for (unsigned int i = 0; i < NUM; i++) { + unsigned int socRet; + DCL_ADC_SOCxSoftTrigger(adcAddr, TSENSOR_SOC_NUM); + BASE_FUNC_DELAY_MS(1); /* waite for 1ms until conversion finish */ + if (adcAddr->ADC_EOC_FLAG.BIT.eoc15_flag == BASE_CFG_ENABLE) { + socRet = DCL_ADC_ReadSOCxResult(adcAddr, TSENSOR_SOC_NUM); + ret += socRet; + count++; + } + } + if (count == 0) { + return 0xFFF; + } + return (ret / count); /* Average the results */ +} + +/** + * @brief Get the temperature from the tsensor. + * @param None. + * @retval Temperature type: float, temperature of MCU, unit: ℃. + */ +float HAL_TSENSOR_GetTemperature(void) +{ + unsigned int result = HAL_TSENSOR_GetResult(); + float temp = TSENSOR_Conversion(result); + return temp; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/tsensor/src/tsensor_ex.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/tsensor/src/tsensor_ex.c new file mode 100644 index 00000000..9f339181 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/tsensor/src/tsensor_ex.c @@ -0,0 +1,111 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file tsensor_ex.c + * @author MCU Driver Team + * @brief tsensor module driver + * @details This file provides functions to manage Extended tsensor functions. + */ + +/* Includes ------------------------------------------------------------------*/ + +#include "adc_tsensor.h" +#include "tsensor_ex.h" + +static int g_lastCode; +static float g_lastTemp; +static bool g_firstFlag = false; + +/** + * @brief The formula calculates the compensation value. + * @param temp, Temperature collected by the tsensor. + * @retval int, HOSC compensation code. + */ +static int HOSC_CalculateValue(float temp) +{ + float hosc = (-0.00002f * temp * temp) - (0.0013f * temp) + 25.2652f; /* Formula : -0.00002, 0.0013, 25.2652 */ + float tCode = (25.217f - hosc) / 0.057f; /* Formula Parameter: 25.217, 0.057 */ + float ret; + if (tCode >= 0) { + ret = tCode + 0.5f; /* 0.5 is for rounding */ + return (int)ret; + } else { + ret = 0.5f - tCode; /* 0.5 is for rounding */ + return (0 - (int)ret); + } +} + +/** + * @brief Set the compensation value. + * @param temp, Temperature collected by the tsensor. + * @param hoscCode, HOSC compensation code. + * @retval bool. + */ +static void HOSC_SetValue(float temp, int hoscCode) +{ + int value = (int)g_hosc_ctrim - hoscCode + 1; /* Calculate the value of the configured register */ + unsigned int *hoscReg; + hoscReg = (void *)0x10000100; + *hoscReg = (unsigned int)value; + g_lastCode = hoscCode; + g_lastTemp = temp; +} + +/** + * @brief Temperature compensation threshold check. + * @param temp, Temperature collected by the tsensor. + * @param hoscCode, HOSC compensation code + * @retval bool. + */ +static bool HOSC_ThresholdCheck(float temp, int hoscCode) +{ + if (hoscCode == g_lastCode) { + return false; + } + float threshold = ((temp > g_lastTemp) ? (temp - g_lastTemp) : (g_lastTemp - temp)); + if (threshold <= 5.0f) { /* 5.0f is the temperature threshold. */ + return false; + } + return true; +} + +/** + * @brief Get the result from the tsensor. + * @param None. + * @retval BASE_StatusType, OK, ERROR. + */ +BASE_StatusType HAL_TSENSOR_CalibrateHosc(void) +{ + if (g_hosc_ctrim == 0x1FF) { + return BASE_STATUS_ERROR; /* g_hosc_ctrim is invalid */ + } + if (g_firstFlag == false) { + HAL_TSENSOR_Init(); + } + float temp = HAL_TSENSOR_GetTemperature(); + if (temp < -55.0f || temp > 130.0f) { /* Collection Scope is: -55.0 ~ 130.0 */ + return BASE_STATUS_ERROR; + } + int hoscCode = HOSC_CalculateValue(temp); + if (g_firstFlag == false) { + HOSC_SetValue(temp, hoscCode); + g_firstFlag = true; + } else if (HOSC_ThresholdCheck(temp, hoscCode) == true) { /* The threshold condition is met */ + HOSC_SetValue(temp, hoscCode); + } + return BASE_STATUS_OK; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/uart/common/inc/uart.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/uart/common/inc/uart.h new file mode 100644 index 00000000..a80401c9 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/uart/common/inc/uart.h @@ -0,0 +1,134 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file uart.h + * @author MCU Driver Team + * @brief UART module driver. + * @details This file provides functions declaration of the UART, + * + Initialization and de-initialization functions + * + Peripheral querying the state functions. + * + Peripheral transmit and abort functions. + * + Peripheral interrupt service and callback registration functions. + * This file also provides the definition of the UART handle structure. + */ + +/* Includes ------------------------------------------------------------------*/ +#ifndef McuMagicTag_UART_H +#define McuMagicTag_UART_H + +#include "uart_ip.h" +#include "dma.h" + +/** + * @defgroup UART UART + * @brief UART module. + * @{ + */ + +/** + * @defgroup UART_Common UART Common + * @brief UART common external module. + * @{ + */ + +/** + * @defgroup UART_Handle_Definition UART Handle Definition + * @{ + */ + +/** + * @brief The definition of the UART handle structure. + */ +typedef struct _UART_Handle { + UART_RegStruct *baseAddress; /**< UART registers base address */ + unsigned int baudRate; /**< UART communication baud rate */ + UART_DataLength dataLength; /**< The length of UART frame */ + UART_StopBits stopBits; /**< The stop bit of UART frame */ + UART_Parity_Mode parity; /**< The parity bit of UART frame */ + UART_Transmit_Mode txMode; /**< Tx transmit mode setting */ + UART_Transmit_Mode rxMode; /**< tx transmit mode setting */ + volatile unsigned char *txbuff; /**< Start address of tx */ + volatile unsigned char *rxbuff; /**< Start address of rx */ + volatile unsigned int txBuffSize; /**< The length of tx buff */ + volatile unsigned int rxBuffSize; /**< The length of rx buff */ + bool fifoMode; /**< The FIFO mode */ + UART_FIFO_Threshold fifoTxThr; /**< Interrupt threshold of tx FIFO */ + UART_FIFO_Threshold fifoRxThr; /**< Interrupt threshold of rx FIFO */ + UART_HW_FlowCtr hwFlowCtr; /**< UART hardware flow control */ + DMA_Handle *dmaHandle; /**< UART_DMA control */ + unsigned int uartDmaTxChn; /**< UART_DMA tx channel */ + unsigned int uartDmaRxChn; /**< UART_DMA rx channel */ + volatile UART_State_Type txState; /**< The tx status of UART */ + volatile UART_State_Type rxState; /**< The rx status of UART */ + UART_Error_Type errorType; /**< The error of UART */ + + UART_UserCallBack userCallBack; /**< User callback function of UART. */ + UART_ExtendHandle handleEx; /**< UART extend handle. */ +} UART_Handle; + +typedef void (* UART_CallbackType)(void *handle); +/** + * @} + */ + +/** + * @defgroup UART_API_Declaration UART HAL API + * @{ + */ +/* Peripheral initialization and deinitialize functions */ +BASE_StatusType HAL_UART_Init(UART_Handle *uartHandle); +BASE_StatusType HAL_UART_DeInit(UART_Handle *uartHandle); + +/* Peripheral querying the state functions */ +UART_State_Type HAL_UART_GetState(UART_Handle *uartHandle); + +/* Peripheral transmit and abort functions */ +BASE_StatusType HAL_UART_WriteBlocking(UART_Handle *uartHandle, unsigned char *srcData, + unsigned int dataLength, unsigned int blockingTime); +BASE_StatusType HAL_UART_WriteIT(UART_Handle *uartHandle, unsigned char *srcData, unsigned int dataLength); +BASE_StatusType HAL_UART_WriteDMA(UART_Handle *uartHandle, unsigned char *srcData, + unsigned int dataLength); +BASE_StatusType HAL_UART_ReadBlocking(UART_Handle *uartHandle, unsigned char *saveData, + unsigned int dataLength, unsigned int blockingTime); +BASE_StatusType HAL_UART_ReadIT(UART_Handle *uartHandle, unsigned char *saveData, unsigned int dataLength); +BASE_StatusType HAL_UART_ReadDMA(UART_Handle *uartHandle, unsigned char *saveData, + unsigned int dataLength); +BASE_StatusType HAL_UART_StopRead(UART_Handle *uartHandle); +BASE_StatusType HAL_UART_StopWrite(UART_Handle *uartHandle); + +/* brief Peripheral interrupt service and callback registration functions */ +void HAL_UART_IrqHandler(void *handle); +BASE_StatusType HAL_UART_RegisterCallBack(UART_Handle *uartHandle, UART_CallbackFun_Type typeID, + UART_CallbackType pCallback); + +/* UART read using DMA cyclically stored function */ +BASE_StatusType HAL_UART_ReadDMAAndCyclicallyStored(UART_Handle *uartHandle, unsigned char *saveData, + DMA_LinkList *tempNode, unsigned int dataLength); +unsigned int HAL_UART_ReadDMAGetPos(UART_Handle *uartHandle); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_UART_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/uart/inc/uart_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/uart/inc/uart_ip.h new file mode 100644 index 00000000..3ed58547 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/uart/inc/uart_ip.h @@ -0,0 +1,1321 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file uart_ip.h + * @author MCU Driver Team + * @brief UART module driver + * @details This file provides DCL functions to manage UART and Definition of + * specific parameters. + * + Definition of UART configuration parameters. + * + UART register mapping structure. + * + Parameters check functions. + * + Direct configuration layer interface. + */ + +/* Macro definitions */ +#ifndef McuMagicTag_UART_IP_H +#define McuMagicTag_UART_IP_H + +#include "baseinc.h" + +#ifdef UART_PARAM_CHECK +#define UART_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define UART_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define UART_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define UART_ASSERT_PARAM(para) ((void)0U) +#define UART_PARAM_CHECK_NO_RET(para) ((void)0U) +#define UART_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +/** + * @addtogroup UART + * @{ + */ + +/** + * @defgroup UART_IP UART_IP + * @brief UART_IP: uart_v0 + * @{ + */ + +/** + * @defgroup UART_Param_Def UART Parameters Definition + * @brief Definition of UART configuration parameters. + * @{ + */ + +/** + * @brief Extent handle definition of UART + */ +typedef struct { +} UART_ExtendHandle; + +/** + * @brief Type ID of the callback function registered by the user. + */ +typedef enum { + UART_WRITE_IT_FINISH = 0x00000000U, + UART_READ_IT_FINISH = 0x00000001U, + UART_WRITE_DMA_FINISH = 0x00000002U, + UART_READ_DMA_FINISH = 0x00000003U, + UART_TRNS_IT_ERROR = 0x00000004U, + UART_TRNS_DMA_ERROR = 0x00000005U +} UART_CallbackFun_Type; + +/** + * @brief User Callback Function Definition + */ +typedef struct { + void (* WriteItFinishCallBack)(void *handle); /**< UART tx interrupt complete callback + function for users */ + void (* ReadItFinishCallBack)(void *handle); /**< UART rx interrupt complete callback + function for users */ + void (* WriteDmaFinishCallBack)(void *handle); /**< UART tx DMA complete callback function + for users */ + void (* ReadDmaFinishCallBack)(void *handle); /**< UART rx DMA complete callback function + for users */ + void (* TransmitItErrorCallBack)(void *handle); /**< UART interrupt mode error callback + function for users */ + void (* TransmitDmaErrorCallBack)(void *handle); /**< UART interrupt mode error callback + function for users */ +}UART_UserCallBack; + +/** + * @brief Type of error callback functuions. + */ +typedef enum { + UART_ERROR_FRAME = 0x00000080U, + UART_ERROR_PARITY = 0x00000100U, + UART_ERROR_BREAK = 0x00000200U, + UART_ERROR_OVERFLOW = 0x00000400U +} UART_Error_Type; + +/** + * @brief The number of data bits transmitted or received in a frame. + */ +typedef enum { + UART_DATALENGTH_5BIT = 0x00000000U, + UART_DATALENGTH_6BIT = 0x00000001U, + UART_DATALENGTH_7BIT = 0x00000002U, + UART_DATALENGTH_8BIT = 0x00000003U +} UART_DataLength; + +/** + * @brief UART parity mode. + * @details parity mode: + * + UART_PARITY_ODD -- odd check + * + UART_PARITY_EVEN -- even check + * + UART_PARITY_NONE -- none odd or even check + */ +typedef enum { + UART_PARITY_ODD = 0x00000000U, + UART_PARITY_EVEN = 0x00000001U, + UART_PARITY_NONE = 0x00000002U +} UART_Parity_Mode; + +/** + * @brief Stop bit setting. + * @details Stop bit type: + * + UART_STOPBITS_ONE -- frame with one stop bit + * + UART_STOPBITS_TWO -- frame with two stop bits + */ +typedef enum { + UART_STOPBITS_ONE = 0x00000000U, + UART_STOPBITS_TWO = 0x00000001U +} UART_StopBits; + +/** + * @brief Three transmit mode: blocking, DMA, interrupt. + */ +typedef enum { + UART_MODE_BLOCKING = 0x00000000U, + UART_MODE_INTERRUPT = 0x00000001U, + UART_MODE_DMA = 0x00000002U, + UART_MODE_DISABLE = 0x00000003U +} UART_Transmit_Mode; + +/** + * @brief Hardware flow control mode disable/enable. + */ +typedef enum { + UART_HW_FLOWCTR_DISABLE = 0x00000000U, + UART_HW_FLOWCTR_ENABLE = 0x00000001U +} UART_HW_FlowCtr; + +/** + * @brief UART running status: deinit, ready, busy, busy(TX), busy(RX). + */ +typedef enum { + UART_STATE_NONE_INIT = 0x00000000U, + UART_STATE_READY = 0x00000001U, + UART_STATE_BUSY = 0x00000002U, + UART_STATE_BUSY_TX = 0x00000003U, + UART_STATE_BUSY_RX = 0x00000004U, +} UART_State_Type; + +/** + * @brief UART RX/TX FIFO line interrupt threshold. An interrupt is triggered when the received or discovered data + * crosses the FIFO threshold. + * @details Description: + * + UART_FIFOFULL_ONE_EIGHT -- rxFIFO >= 1/8 FULL, txFIFO <= 1/8 FULL + * + UART_FIFOFULL_ONE_FOUR -- rxFIFO >= 1/4 FULL, txFIFO <= 1/4 FULL + * + UART_FIFOFULL_THREE_FOUR -- rxFIFO >= 3/4 FULL, txFIFO <= 3/4 FULL + * + UART_FIFOFULL_SEVEN_EIGHT -- rxFIFO >= 7/8 FULL, txFIFO <= 7/8 FULL + * + UART_FIFOFULL_ONE_SIXTEEN -- rxFIFO >= 1/16 FULL + * + UART_FIFOFULL_ONE_THIRTYTWO -- rxFIFO >= 1/32 FULL + * + UART_FIFOFULL_FIVETEEN_SIXTEEN -- txFIFO <= 15/16 FULL + * + UART_FIFOFULL_THIRTYONE_THIRTYTWO -- txFIFO <= 31/32 FULL + */ +typedef enum { + UART_FIFOFULL_ONE_EIGHT = 0x00000000U, + UART_FIFOFULL_ONE_FOUR = 0x00000001U, + UART_FIFOFULL_ONE_TWO = 0x00000002U, + UART_FIFOFULL_THREE_FOUR = 0x00000003U, + UART_FIFOFULL_SEVEN_EIGHT = 0x00000004U, + UART_FIFOFULL_ONE_SIXTEEN = 0x00000005U, + UART_FIFOFULL_ONE_THIRTYTWO = 0x00000006U, + UART_FIFOFULL_FIVETEEN_SIXTEEN = 0x00000005U, + UART_FIFOFULL_THIRTYONE_THIRTYTWO = 0x00000006U +} UART_FIFO_Threshold; + +/** + * @} + */ + +/** + * @defgroup UART_Reg_Def UART Register Definition + * @brief register mapping structure + * @{ + */ + + /** + * @brief UART data register, which stores RX data and TX data. and reads RX status from this register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int data : 8; /**< Receives data and transmits data. */ + unsigned int fe : 1; /**< Frame error. */ + unsigned int pe : 1; /**< Verification error. */ + unsigned int be : 1; /**< Break error. */ + unsigned int oe : 1; /**< Overflow error. */ + unsigned int reserved0 : 20; + } BIT; +} volatile UART_DR_REG; + + /** + * @brief Receive status register/error clear register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int fe : 1; /**< Frame error. */ + unsigned int pe : 1; /**< parity check error. */ + unsigned int be : 1; /**< Break error. */ + unsigned int oe : 1; /**< Overflow error. */ + unsigned int reserved0 : 28; + } BIT; +} volatile UART_RSR_REG; + + /** + * @brief UART flag register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int cts : 1; /**< Hardware flow control status. */ + unsigned int reserved0 : 2; + unsigned int busy : 1; /**< UART busy/idle status bit. */ + unsigned int rxfe : 1; /**< RX hold register/RX FIFO status. The value is 1 when it is empty. */ + unsigned int txff : 1; /**< TX hold register/Tx FIFO status. The value is 1 when it is full. */ + unsigned int rxff : 1; /**< RX hold register/RX FIFO status. The value is 1 when it is full. */ + unsigned int txfe : 1; /**< TX hold register/Tx FIFO status. The value is 1 when it is empty. */ + unsigned int reserved1 : 24; + } BIT; +} volatile UART_FR_REG; + + /** + * @brief Integer baud rate register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int bauddivint : 16; /**< Integer baud rate divider value. */ + unsigned int reserved0 : 16; + } BIT; +} volatile UART_IBRD_REG; + + /** + * @brief Fractional baud rate register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int bauddivfrac : 6; /**< Fractional baud rate divider. */ + unsigned int reserved0 : 26; + } BIT; +} volatile UART_FBRD_REG; + + /** + * @brief Line control register. UART_LCR_H, UART_IBRD, and UART_FBRD constitute a 30-bit register UART_LCR. + * UART_LCR is not flushed until UART_LCR_H is written. + */ +typedef union { + unsigned int reg; + struct { + unsigned int brk : 1; /**< Send a break. */ + unsigned int pen : 1; /**< Parity check select bit. */ + unsigned int eps : 1; /**< Parity check selection during transmission and reception. */ + unsigned int stp2 : 1; /**< TX frame tail stop bit select. */ + unsigned int fen : 1; /**< TX and RX FIFO enable control. */ + unsigned int wlen : 2; /**< Indicates number of transmitted and received data bits in a frame. */ + unsigned int sps : 1; /**< Select stick parity. */ + unsigned int reserved0 : 24; + } BIT; +} volatile UART_LCR_H_REG; + + /** + * @brief UART control register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int uarten : 1; /**< UART enable. */ + unsigned int reserved0 : 6; + unsigned int lbe : 1; /**< Indicates whether to enable loopback. */ + unsigned int txe : 1; /**< UART TX enable. */ + unsigned int rxe : 1; /**< UART RX enable. */ + unsigned int reserved1 : 1; + unsigned int rts : 1; /**< Request to send. */ + unsigned int reserved2 : 2; + unsigned int rtsen : 1; /**< RTS hardware flow control enable. */ + unsigned int ctsen : 1; /**< CTS hardware flow control enable. */ + unsigned int reserved3 : 16; + } BIT; +} volatile UART_CR_REG; + + /** + * @brief UART Interrupt FIFO threshold select register. + * It is used to set threshold for triggering FIFO interrupt (UART_TXinTR or UART_RXinTR). + */ +typedef union { + unsigned int reg; + struct { + unsigned int txiflsel : 3; /**< Threshold of the TX interrupt FIFO. */ + unsigned int rxiflsel : 3; /**< Threshold of the RX interrupt FIFO. */ + unsigned int reserved0 : 26; + } BIT; +} volatile UART_IFLS_REG; + + /** + * @brief UART interrupt mask register, which is used to mask interrupts. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int ctsmim : 1; /**< Mask status of the CTS interrupt. */ + unsigned int reserved1 : 2; + unsigned int rxim : 1; /**< Mask status of the RX interrupt. */ + unsigned int txim : 1; /**< Mask status of the TX interrupt. */ + unsigned int rtim : 1; /**< Mask status of the RX timeout interrupt. */ + unsigned int feim : 1; /**< Mask status of the frame error interrupt. */ + unsigned int peim : 1; /**< Mask status of the parity interrupt. */ + unsigned int beim : 1; /**< Mask status of break error interrupts. */ + unsigned int oeim : 1; /**< Mask status of the overflow error interrupt. */ + unsigned int reserved2 : 21; + } BIT; +} volatile UART_IMSC_REG; + + /** + * @brief UART raw interrupt status register. + * The content of this register is not affected by interrupt mask register. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int ctsmis : 1; /**< Raw CTS interrupt status. */ + unsigned int reserved1 : 2; + unsigned int rxris : 1; /**< Raw RX interrupt status. */ + unsigned int txris : 1; /**< Raw TX interrupt status. */ + unsigned int rtris : 1; /**< Raw RX timeout interrupt status. */ + unsigned int feris : 1; /**< Raw frame error interrupt status. */ + unsigned int peris : 1; /**< Raw parity interrupt status. */ + unsigned int beris : 1; /**< Raw break error interrupt status. */ + unsigned int oeris : 1; /**< Raw overflow error interrupt status. */ + unsigned int reserved2 : 21; + } BIT; +} volatile UART_RIS_REG; + + /** + * @brief Masked interrupt status register. + * It is result of AND operation between raw interrupt status and interrupt mask. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int ctsmmis : 1; /**< Masked CTS interrupt status. */ + unsigned int reserved1 : 2; + unsigned int rxmis : 1; /**< Masked RX interrupt status. */ + unsigned int txmis : 1; /**< Masked TX interrupt status. */ + unsigned int rtmis : 1; /**< Masked RX timeout interrupt status. */ + unsigned int femis : 1; /**< Status of masked frame error interrupts. */ + unsigned int pemis : 1; /**< Masked parity interrupt status. */ + unsigned int bemis : 1; /**< Status of masked break error interrupts. */ + unsigned int oemis : 1; /**< Masked overflow error interrupt status. */ + unsigned int reserved2 : 21; + } BIT; +} volatile UART_MIS_REG; + + /** + * @brief Interrupt clear register. + * Writing 1 clears the corresponding interrupt, and writing 0 does not take effect. + */ +typedef union { + unsigned int reg; + struct { + unsigned int reserved0 : 1; + unsigned int ctsmic : 1; /**< Clears the CTS interrupt. */ + unsigned int reserved1 : 2; + unsigned int rxic : 1; /**< Clears the RX interrupt. */ + unsigned int txic : 1; /**< Clear the TX interrupt. */ + unsigned int rtic : 1; /**< Receive timeout interrupt clear. */ + unsigned int feic : 1; /**< Frame error interrupt clear. */ + unsigned int peic : 1; /**< Clears the parity interrupt. */ + unsigned int beic : 1; /**< Clears the break error interrupt. */ + unsigned int oeic : 1; /**< Clears the overflow error interrupt. */ + unsigned int reserved2 : 21; + } BIT; +} volatile UART_ICR_REG; + + /** + * @brief DMA control register. + * which is used to enable the DMA of the TX FIFO and RX FIFO. + */ +typedef union { + unsigned int reg; + struct { + unsigned int rxdmae : 1; /**< DMA enable control for RX FIFO. */ + unsigned int txdmae : 1; /**< DMA enable control for TX FIFO. */ + unsigned int dmaonerr : 1; /**< DMA enable control for RX channel when UART error interrupt occurs. */ + unsigned int rxlastsreq_en : 1; /**< REQ enable for last data stream supported by UART RX DMA. */ + unsigned int reserved0 : 28; + } BIT; +} volatile UART_DMACR_REG; + +/** + * @brief Register mapping structure. + */ +typedef struct { + UART_DR_REG UART_DR; /**< Data register, offset address: 0x00000000U */ + UART_RSR_REG UART_RSR; /**< Receiving status/error clearing register, offset address: 0x00000004U */ + unsigned char space0[16]; + UART_FR_REG UART_FR; /**< Flag register, offset address: 0x00000018U */ + unsigned char space1[8]; + UART_IBRD_REG UART_IBRD; /**< Integer baud rate register, offset address: 0x00000024U */ + UART_FBRD_REG UART_FBRD; /**< Fractional baud rate register, offset address: 0x00000028U */ + UART_LCR_H_REG UART_LCR_H; /**< Wire control register, offset address: 0x0000002CU */ + UART_CR_REG UART_CR; /**< Control register, offset address: 0x00000030U */ + UART_IFLS_REG UART_IFLS; /**< Interrupt FIFO threshold register, offset address: 0x00000034U */ + UART_IMSC_REG UART_IMSC; /**< Interrupt mask status register, offset address: 0x00000038U */ + UART_RIS_REG UART_RIS; /**< Raw interrupt status register, offset address: 0x0000003CU */ + UART_MIS_REG UART_MIS; /**< Masked interrupt status register, offset address: 0x00000040U */ + UART_ICR_REG UART_ICR; /**< Interrupt clear register, offset address: 0x00000044U */ + UART_DMACR_REG UART_DMACR; /**< DMA control register register, offset address: 0x00000048U */ +} volatile UART_RegStruct; +/** + * @} + */ + +/** + * @brief Check UART datalength parameter. + * @param datalength The number of data bits in a frame, @ref UART_DataLength + * @retval bool + */ +static inline bool IsUartDatalength(UART_DataLength datalength) +{ + return (datalength >= UART_DATALENGTH_5BIT) && (datalength <= UART_DATALENGTH_8BIT); +} + +/** + * @brief Check UART stopbits parameter. + * @param stopbits The number of stop bits in a frame, @ref UART_StopBits + * @retval bool + */ +static inline bool IsUartStopbits(UART_StopBits stopbits) +{ + return (stopbits == UART_STOPBITS_ONE) || (stopbits == UART_STOPBITS_TWO); +} + +/** + * @brief Check UART paritymode parameter. + * @param paritymode UART parity check mode, @ref UART_Parity_Mode + * @retval bool + */ +static inline bool IsUartParitymode(UART_Parity_Mode paritymode) +{ + if ((paritymode == UART_PARITY_ODD) || + (paritymode == UART_PARITY_EVEN) || + (paritymode == UART_PARITY_NONE)) { + return true; + } + return false; +} + +/** + * @brief Check UART transmode parameter. + * @param transmode Transmit mode, @ref UART_Transmit_Mode + * @retval bool + */ +static inline bool IsUartTransmode(UART_Transmit_Mode transmode) +{ + if ((transmode == UART_MODE_BLOCKING) || + (transmode == UART_MODE_INTERRUPT) || + (transmode == UART_MODE_DMA) || + (transmode == UART_MODE_DISABLE)) { + return true; + } + return false; +} + +/** + * @brief Check UART fifoThreshold parameter. + * @param fifoThreshold UART TX/RX FIFO line interrupt threshold, @ref UART_FIFO_Threshold + * @retval bool + */ +static inline bool IsUartFIFOThreshold(UART_FIFO_Threshold fifoThreshold) +{ + return (fifoThreshold >= UART_FIFOFULL_ONE_EIGHT) && (fifoThreshold <= UART_FIFOFULL_ONE_THIRTYTWO); +} + +/* Direct configuration layer */ +/** + * @brief Send a character by UART + * @param uartx UART register base address. + * @param data Character to be sent. + * @retval None. + */ +static inline void DCL_UART_WriteData(UART_RegStruct * const uartx, unsigned char data) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_DR.BIT.data = data; /* Data to be sent. */ +} + +/** + * @brief Receive a character from UART. + * @param uartx UART register base address. + * @retval Data, read the received data from the UART data register. + */ +static inline unsigned char DCL_UART_ReadData(const UART_RegStruct *uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_DR.BIT.data; /* Data to be read. */ +} + +/** + * @brief Get receiving status. + * @param uartx UART register base address. + * @retval overall receive status + */ +static inline unsigned int DCL_UART_ReceiveStatus(const UART_RegStruct *uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_DR.reg; /* unsigned overall receive status */ +} + +/** + * @brief UART TX enable. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_WriteEnable(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CR.BIT.txe = BASE_CFG_ENABLE; /* Tx send enable */ +} + +/** + * @brief UART TX disable. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_WriteDisable(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CR.BIT.txe = BASE_CFG_DISABLE; /* Tx send disable */ +} + +/** + * @brief UART RX enable. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_ReadEnable(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CR.BIT.rxe = BASE_CFG_ENABLE; /* Rx read enable */ +} + +/** + * @brief UART RX disable. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_ReadDisable(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CR.BIT.rxe = BASE_CFG_DISABLE; /* Rx read disable */ +} + +/** + * @brief Request Tx send, output signal is 0. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_EnableRequestTxSend(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CR.BIT.rts = BASE_CFG_ENABLE; /* Rx read enable */ +} + +/** + * @brief Request Tx send, output signal does not change. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_DisableRequestTxSend(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CR.BIT.rts = BASE_CFG_DISABLE; +} + +/** + * @brief UART uses hardware flow control. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_Enable_HwFlowCtr(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CR.BIT.ctsen = BASE_CFG_ENABLE; + uartx->UART_CR.BIT.rtsen = BASE_CFG_ENABLE; +} + +/** + * @brief UART uses hardware flow control. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_Disable_HwFlowCtr(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CR.BIT.ctsen = BASE_CFG_DISABLE; + uartx->UART_CR.BIT.rtsen = BASE_CFG_DISABLE; +} + +/** + * @brief Enable UART. + * @param uartx UART register base address. + * @retval None + */ +static inline void DCL_UART_EnableUart(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CR.BIT.uarten = BASE_CFG_ENABLE; +} + +/** + * @brief Disable UART. If the UART is disabled during Tx and Rx, + * transfer of the current data ends before it stops normally. + * @param uartx UART register base address. + * @retval None + */ +static inline void DCL_UART_DisableUart(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CR.BIT.uarten = BASE_CFG_DISABLE; +} + +/** + * @brief Enable Loopback Tx-Rx. + * @param uartx UART register base address. + * @retval None + */ +static inline void DCL_UART_EnableLoopBack(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CR.BIT.lbe = BASE_CFG_ENABLE; +} + +/** + * @brief Disable Loopback Tx-Rx. + * @param uartx UART register base address. + * @retval None + */ +static inline void DCL_UART_DisableLoopBack(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_CR.BIT.lbe = BASE_CFG_DISABLE; +} + +/** + * @brief UART TX use DMA . + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_DMA_WriteEnable(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_DMACR.BIT.txdmae = BASE_CFG_ENABLE; +} + +/** + * @brief UART TX not use DMA . + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_DMA_WriteDisable(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_DMACR.BIT.txdmae = BASE_CFG_DISABLE; +} + +/** + * @brief UART RX use DMA. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_DMA_ReadEnable(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_DMACR.BIT.rxdmae = BASE_CFG_ENABLE; +} + +/** + * @brief UART RX not use DMA . + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_DMA_ReadDisable(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_DMACR.BIT.rxdmae = BASE_CFG_DISABLE; +} + +/** + * @brief Set UART word length. + * @param uartx UART register base address. + * @param dataLength Word length of sending and receiving, @ref UART_DataLength + * @retval None. + */ +static inline void DCL_UART_SetDataLength(UART_RegStruct * const uartx, UART_DataLength dataLength) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + UART_PARAM_CHECK_NO_RET(IsUartDatalength(dataLength)); + uartx->UART_LCR_H.BIT.wlen = dataLength; +} + +/** + * @brief Get UART word length. + * @param uartx UART register base address. + * @retval unsigned int: Word length of sending and receiving. + */ +static inline unsigned int DCL_UART_GetDataLength(const UART_RegStruct * uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_LCR_H.BIT.wlen; +} + +/** + * @brief Setting UART odd parity check. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_SetParityOdd(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_LCR_H.BIT.eps = BASE_CFG_DISABLE; + uartx->UART_LCR_H.BIT.pen = BASE_CFG_ENABLE; +} + +/** + * @brief Setting UART even parity check. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_SetParityEven(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_LCR_H.BIT.eps = BASE_CFG_ENABLE; + uartx->UART_LCR_H.BIT.pen = BASE_CFG_ENABLE; +} + +/** + * @brief UART does not use parity check. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_SetParityNone(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_LCR_H.BIT.pen = BASE_CFG_DISABLE; +} + +/** + * @brief Getting UART odd/even parity check. + * @param uartx UART register base address. + * @retval Odd/even parity check, 0: odd, 1: even, 2: None. + */ +static inline unsigned int DCL_UART_GetParityCheck(const UART_RegStruct * uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + unsigned int eps = uartx->UART_LCR_H.BIT.eps; + unsigned int pen = uartx->UART_LCR_H.BIT.pen; + if (eps == 0) { + return UART_PARITY_NONE; + } else if (pen == 0) { + return UART_PARITY_ODD; + } else { + return UART_PARITY_EVEN; + } +} + +/** + * @brief Set stop bit. + * @param uartx UART register base address. + * @param bit One or two stop bit, @ref UART_StopBits + * @retval None. + */ +static inline void DCL_UART_SetStopBits(UART_RegStruct * const uartx, UART_StopBits bit) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + UART_PARAM_CHECK_NO_RET(IsUartStopbits(bit)); + uartx->UART_LCR_H.BIT.stp2 = bit; +} + +/** + * @brief Get stop bit. + * @param uartx UART register base address. + * @retval bool: 0: 1-bit stop bit is attached to the transmitted frame tail. + * 1: 2-bit stop bit at the end of the transmitted frame. + */ +static inline bool DCL_UART_GetStopBits(const UART_RegStruct *uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_LCR_H.BIT.stp2; +} + +/** + * @brief UART disable stick parity. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_DisableStickParity(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_LCR_H.BIT.sps = BASE_CFG_DISABLE; +} + +/** + * @brief UART enable function of stick parity 0-bit check. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_EnableStickParity_Zero(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_LCR_H.BIT.pen = BASE_CFG_ENABLE; + uartx->UART_LCR_H.BIT.eps = BASE_CFG_ENABLE; + uartx->UART_LCR_H.BIT.sps = BASE_CFG_ENABLE; +} + +/** + * @brief UART enable function of stick parity 1-bit check. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_EnableStickParity_One(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_LCR_H.BIT.pen = BASE_CFG_ENABLE; + uartx->UART_LCR_H.BIT.eps = BASE_CFG_DISABLE; + uartx->UART_LCR_H.BIT.sps = BASE_CFG_ENABLE; +} + +/** + * @brief UART enable interrupt of CTS. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_EnableCTSInt(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_IMSC.BIT.ctsmim = BASE_CFG_ENABLE; +} + +/** + * @brief UART disable interrupt of CTS. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_DisableCTSInt(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_IMSC.BIT.ctsmim = BASE_CFG_DISABLE; +} + +/** + * @brief Set line control. + * @param uartx UART register base address. + * @param controlValue Configuration value of line controller. + * @retval None. + */ +static inline void DCL_UART_SetLineControl(UART_RegStruct * const uartx, unsigned int controlValue) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_LCR_H.reg = controlValue; +} + +/** + * @brief Enable TX and RX FIFO. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_EnableFIFO(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_LCR_H.BIT.fen = BASE_CFG_ENABLE; +} + +/** + * @brief Disable TX and RX FIFO. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_DisableFIFO(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_LCR_H.BIT.fen = BASE_CFG_DISABLE; +} + +/** + * @brief Enable Tx break. The current data is transmitted. + * Tx continuously outputs a low level. + * @param uartx UART register base address. + * @retval None + */ +static inline void DCL_UART_EnableTxBreak(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_LCR_H.BIT.brk = BASE_CFG_ENABLE; +} + +/** + * @brief Disable Tx break. no effect. + * @param uartx UART register base address. + * @retval None + */ +static inline void DCL_UART_DisableTxBreak(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_LCR_H.BIT.brk = BASE_CFG_DISABLE; +} + +/** + * @brief UART clear interrupt of CTS. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_ClearCTSInt(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_ICR.BIT.ctsmic = BASE_CFG_ENABLE; + uartx->UART_IMSC.BIT.ctsmim = BASE_CFG_DISABLE; +} + +/** + * @brief Clear Interrupts. + * @param uartx UART register base address. + * @param clearInterruptBits bit 1: clear interrupt, bit 0: no effect. + * @retval None + */ +static inline void DCL_UART_ClearInterrupts(UART_RegStruct * const uartx, unsigned int clearInterruptBits) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_ICR.reg = clearInterruptBits; +} + +/** + * @brief Clear Tx interrupt. + * @param uartx UART register base address. + * @retval void + */ +static inline void DCL_UART_ClearTxInt(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_ICR.BIT.txic = BASE_CFG_ENABLE; +} + +/** + * @brief Clear overflow interrupt. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_ClearOverflowINT(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_ICR.BIT.oeic = BASE_CFG_ENABLE; +} + +/** + * @brief Clear break error interrupt. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_ClearBreakErrorINT(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_ICR.BIT.beic = BASE_CFG_ENABLE; +} + +/** + * @brief Clear parity interrupt. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_ClearParityINT(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_ICR.BIT.peic = BASE_CFG_ENABLE; +} + +/** + * @brief Clear frame error interrupt. + * @param uartx UART register base address. + * @retval None. + */ +static inline void DCL_UART_ClearFrameErrorINT(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_ICR.BIT.feic = BASE_CFG_ENABLE; +} + +/** + * @brief UART get MIS interrupt status of CTS. + * @param uartx UART register base address. + * @retval status, 1: Interrupt generation, 0: interrupt is not generated. + */ +static inline unsigned int DCL_UART_GetMISCTSIntStatus(const UART_RegStruct *uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_MIS.BIT.ctsmmis; +} + +/** + * @brief MIS error interrupt status. + * @param uartx UART register base address. + * @retval bool: 1 Error interrupt generated, 0 No Error interrupt generated. + */ +static inline bool DCL_UART_GetMISErrorINTStatus(const UART_RegStruct * uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_MIS.BIT.oemis; +} + +/** + * @brief MIS break interrupt status. + * @param uartx UART register base address. + * @retval bool: 1 Break interrupt generated, 0 No break interrupt generated. + */ +static inline bool DCL_UART_GetMISBreakINTStatus(const UART_RegStruct * uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_MIS.BIT.bemis; +} + +/** + * @brief MIS Parity interrupt status. + * @param uartx UART register base address. + * @retval bool: 1 verification interrupt generated, 0 No verification interrupt generated. + */ +static inline bool DCL_UART_GetMISParityINTStatus(const UART_RegStruct * uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_MIS.BIT.pemis; +} + +/** + * @brief MIS frame error interrupt status. + * @param uartx UART register base address. + * @retval bool: 1 frame error interrupt generated, 0 No frame error interrupt generated. + */ +static inline bool DCL_UART_GetMISFrameErrorINTStatus(const UART_RegStruct * uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_MIS.BIT.femis; +} + +/** + * @brief MIS send interrupt status. + * @param uartx UART register base address. + * @retval bool: 1 send interrupt generated 0 No send interrupt generated. + */ +static inline bool DCL_UART_GetMISSendINTStatus(const UART_RegStruct * uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_MIS.BIT.txmis; +} + +/** + * @brief MIS receive interrupt status. + * @param uartx UART register base address. + * @retval bool: 1 receive interrupt generated 0 No receive interrupt generated. + */ +static inline bool DCL_UART_GetMISReceiveINTStatus(const UART_RegStruct * uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_MIS.BIT.rxmis; +} + + +/** + * @brief MIS receive timeout interrupt status. + * @param uartx UART register base address. + * @retval bool: 1 receive timeout interrupt generated 0 No receive timeout interrupt generated. + */ +static inline bool DCL_UART_GetMISReceiveTimeOutINTStatus(const UART_RegStruct * uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_MIS.BIT.rtmis; +} + +/** + * @brief Get Busy/idle status of UART. + * @param uartx UART register base address. + * @retval status, 1: busy, 0: idle. + */ +static inline bool DCL_UART_GetBusyIdleStatus(const UART_RegStruct * uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_FR.BIT.busy; +} + +/** + * @brief Get Tx FIFO Full status. + * @param uartx UART register base address. + * @retval bool: 1 TxFIFO is Full + */ +static inline bool DCL_UART_GetTxFIFOFullStatus(const UART_RegStruct *uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_FR.BIT.txff; +} + +/** + * @brief Whether Tx FIFO is empty. + * @param uartx UART register base address. + * @retval bool: 1 TxFIFO is empty + */ +static inline bool DCL_UART_GetTxFIFOEmptyStatus(const UART_RegStruct *uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_FR.BIT.txfe; +} + +/** + * @brief Get Rx FIFO status. + * @param uartx UART register base address. + * @retval bool: 1 TxFIFO is Full. + */ +static inline bool DCL_UART_GetRxFIFOFullStatus(const UART_RegStruct *uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_FR.BIT.rxff; +} + +/** + * @brief Whether Rx FIFO is empty. + * @param uartx UART register base address. + * @retval bool: 1 RxFIFO is empty. + */ +static inline bool DCL_UART_GetRxFIFOEmptyStatus(const UART_RegStruct *uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + return uartx->UART_FR.BIT.rxfe; +} + +/** + * @brief Set fractional baud rate. + * @param uartx UART register base address. + * @param fractionBaud fractional baud rate. + * @retval None. + */ +static inline void DCL_UART_SetfractiondBaud(UART_RegStruct * const uartx, unsigned int fractionBaud) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_FBRD.reg = fractionBaud; +} + +/** + * @brief Set integer baud rate. + * @param uartx UART register base address. + * @param integerBaud integer baud rate. + * @retval None + */ +static inline void DCL_UART_SetIntegerBaud(UART_RegStruct * const uartx, unsigned int IntegerBaud) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_IBRD.reg = IntegerBaud; +} + +/** + * @brief Set Rx FIFO threshold select. + * @param uartx UART register base address. + * @param thresholdValue value of Rx FIFO threshold, @ref UART_FIFO_Threshold + * @retval None. + */ +static inline void DCL_UART_SetRxFIFOThreshold(UART_RegStruct * const uartx, UART_FIFO_Threshold thresholdValue) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + UART_ASSERT_PARAM(IsUartFIFOThreshold(thresholdValue)); + uartx->UART_IFLS.BIT.rxiflsel = thresholdValue; +} + +/** + * @brief Set Tx FIFO threshold select. + * @param uartx UART register base address. + * @param thresholdValue value of tx FIFO threshold, @ref UART_FIFO_Threshold + * @retval None. + */ +static inline void DCL_UART_SetTxFIFOThreshold(UART_RegStruct * const uartx, UART_FIFO_Threshold thresholdValue) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + UART_ASSERT_PARAM(IsUartFIFOThreshold(thresholdValue)); + uartx->UART_IFLS.BIT.txiflsel = thresholdValue; +} + +/** + * @brief Masking interrupts. + * @param uartx UART register base address. + * @param clearInterruptBits bit 1: Not mask interrupt, bit 0: Mask interrupt. + * @retval None + */ +static inline void DCL_UART_MaskingInterrupts(UART_RegStruct * const uartx, unsigned int maskingInterruptBits) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_IMSC.reg = maskingInterruptBits; +} + +/** + * @brief Enable MSC Tx Interrupt. + * @param uartx UART register base address. + * @retval None + */ +static inline void DCL_UART_EnableMSCTxInterrupt(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_IMSC.BIT.txim = BASE_CFG_ENABLE; +} + +/** + * @brief Disable MSC Tx Interrupt. + * @param uartx UART register base address. + * @retval None + */ +static inline void DCL_UART_DisableMSCTxInterrupt(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_IMSC.BIT.txim = BASE_CFG_DISABLE; +} + +/** + * @brief Disable Rx interrupt. + * @param uartx UART register base address. + * @retval void + */ +static inline void DCL_UART_DisableRxInt(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_IMSC.BIT.rxim = BASE_CFG_DISABLE; +} + +/** + * @brief Enable Rx interrupt. + * @param uartx UART register base address. + * @retval void + */ +static inline void DCL_UART_EnableRxInt(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_IMSC.BIT.rxim = BASE_CFG_ENABLE; +} + +/** + * @brief UART DMA enable Rx last request. + * @param uartx UART register base address. + * @retval None + */ +static inline void DCL_UART_EnableDMARxLastReq(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_DMACR.BIT.rxlastsreq_en = BASE_CFG_ENABLE; +} + +/** + * @brief UART DMA disable Rx last request. + * @param uartx UART register base address. + * @retval None + */ +static inline void DCL_UART_DisableDMARxLastReq(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_DMACR.BIT.rxlastsreq_en = BASE_CFG_DISABLE; +} + +/** + * @brief UART DMA enable DMA on error interrupt. + * @param uartx UART register base address. + * @retval None + */ +static inline void DCL_UART_EnableDMANoErrorINT(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_DMACR.BIT.dmaonerr = BASE_CFG_ENABLE; +} + +/** + * @brief UART DMA disable DMA on error interrupt. + * @param uartx UART register base address. + * @retval None + */ +static inline void DCL_UART_DisableDMANoErrorINT(UART_RegStruct * const uartx) +{ + UART_ASSERT_PARAM(IsUARTInstance(uartx)); + uartx->UART_DMACR.BIT.dmaonerr = BASE_CFG_DISABLE; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_UART_IP_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/uart/src/uart.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/uart/src/uart.c new file mode 100644 index 00000000..8bd5626c --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/uart/src/uart.c @@ -0,0 +1,786 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file uart.c + * @author MCU Driver Team + * @brief UART module driver. + * @details This file provides firmware functions to manage the following + * functionalities of the UART. + * + Initialization and de-initialization functions. + * + Peripheral send and receive functions in blocking mode. + * + Peripheral send and receive functions in interrupt mode. + * + Peripheral send and receive functions in DMA mode. + * + Peripheral stop sending and receiving functions in interrupt/DMA mode. + * + Interrupt callback function and user registration function. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "systick.h" +#include "uart.h" +/* Macro definitions ---------------------------------------------------------*/ + +#define OVERSAMPLING_PARAM 16 +#define SYSTICK_MS_DIV 1000 + +static unsigned int GreaterMaxraund(unsigned int clk) +{ + return clk * 8; /* 8 is greaterMaxraund param */ +} +static unsigned int SmallerMaxraund(unsigned int clk) +{ + return clk * 4; /* 4 is smallerMaxraund param */ +} + +static unsigned int DivClosest(unsigned int x, unsigned int divisor) +{ + unsigned int ret; + if (divisor == 0) { + return 0; + } + ret = (((x) + ((divisor) / 2)) / (divisor)); /* Round up the result, add 1/2 */ + return ret; +} + +static void WriteDMAFinishFun(void *handle); +static void ReadDMAFinishFun(void *handle); +static void TransmitDMAErrorFun(void *handle); + +static void ReadITCallBack(UART_Handle *uartHandle); +static void WriteITCallBack(UART_Handle *uartHandle); +static void ErrorServiceCallback(UART_Handle *uartHandle); + +/** + * @brief Initialize the UART hardware configuration and configure parameters based on the specified handle. + * @param uartHandle UART handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_Init(UART_Handle *uartHandle) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_PARAM_CHECK_WITH_RET(uartHandle->txState == UART_STATE_NONE_INIT, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(uartHandle->rxState == UART_STATE_NONE_INIT, BASE_STATUS_ERROR); + unsigned int uartClock, quot; + UART_PARAM_CHECK_WITH_RET(IsUartDatalength(uartHandle->dataLength), BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(IsUartStopbits(uartHandle->stopBits), BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(IsUartParitymode(uartHandle->parity), BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(IsUartTransmode(uartHandle->txMode), BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(IsUartTransmode(uartHandle->rxMode), BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(IsUartFIFOThreshold(uartHandle->fifoTxThr), BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(IsUartFIFOThreshold(uartHandle->fifoRxThr), BASE_STATUS_ERROR); + + while (uartHandle->baseAddress->UART_FR.BIT.busy == 0x01) { + ; + } + uartHandle->baseAddress->UART_CR.BIT.uarten = BASE_CFG_DISABLE; + uartClock = HAL_CRG_GetIpFreq((void *)uartHandle->baseAddress); + /* The baud rate divider(BRD) based on the baud rate and clock frequency, calculation formula */ + if (uartHandle->baudRate > (uartClock / OVERSAMPLING_PARAM)) { + quot = DivClosest(GreaterMaxraund(uartClock), uartHandle->baudRate); + } else { + quot = DivClosest(SmallerMaxraund(uartClock), uartHandle->baudRate); + } + /* Clear the baud rate divider register */ + uartHandle->baseAddress->UART_FBRD.reg = 0; + uartHandle->baseAddress->UART_IBRD.reg = 0; + /* The fractional baud rate divider value is stored to the lower 6 bits of the FBRD */ + uartHandle->baseAddress->UART_FBRD.reg = (quot & 0x3F); + /* Right shift 6 bits is the integer baud rate divider value, is stored to IBRD */ + uartHandle->baseAddress->UART_IBRD.reg = (quot >> 6); + + uartHandle->baseAddress->UART_LCR_H.BIT.wlen = uartHandle->dataLength; /* Frame length setting */ + uartHandle->baseAddress->UART_LCR_H.BIT.stp2 = uartHandle->stopBits; /* Stop bit setting */ + if (uartHandle->parity == UART_PARITY_NONE) { /* Parity setting */ + uartHandle->baseAddress->UART_LCR_H.BIT.pen = BASE_CFG_DISABLE; + } else { + unsigned int val = 0x0002; /* UART_LCR_H [1]bit enable */ + val |= (uartHandle->parity) << 2; /* Set uartHandle->parity into UART_LCR_H [2]bit */ + uartHandle->baseAddress->UART_LCR_H.reg |= val; + } + if (uartHandle->fifoMode == true) { /* FIFO threshold setting */ + uartHandle->baseAddress->UART_LCR_H.BIT.fen = BASE_CFG_ENABLE; + uartHandle->baseAddress->UART_IFLS.BIT.rxiflsel = uartHandle->fifoRxThr; + uartHandle->baseAddress->UART_IFLS.BIT.txiflsel = uartHandle->fifoTxThr; + } + if (uartHandle->hwFlowCtr == UART_HW_FLOWCTR_ENABLE) { /* Hardwarer flow control setting */ + uartHandle->baseAddress->UART_CR.reg |= 0xC000; + } + uartHandle->baseAddress->UART_CR.reg |= 0x301; /* Enable bit use 0x301 is to set txe/rxe/uarten */ + uartHandle->txState = UART_STATE_READY; + uartHandle->rxState = UART_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief DeInitialize the UART and restoring default parameters based on the specified handle. + * @param uartHandle UART handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_DeInit(UART_Handle *uartHandle) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + uartHandle->baseAddress->UART_CR.reg = BASE_CFG_DISABLE; + uartHandle->baseAddress->UART_ICR.reg |= 0xFFFF; /* Clear all interruptions */ + uartHandle->baseAddress->UART_IMSC.reg = BASE_CFG_DISABLE; + uartHandle->baseAddress->UART_DMACR.reg = BASE_CFG_DISABLE; + uartHandle->baseAddress->UART_LCR_H.BIT.brk = BASE_CFG_DISABLE; + uartHandle->baseAddress->UART_LCR_H.BIT.fen = BASE_CFG_DISABLE; + uartHandle->userCallBack.WriteItFinishCallBack = NULL; /* Clear all user call back function. */ + uartHandle->userCallBack.ReadItFinishCallBack = NULL; + uartHandle->userCallBack.TransmitItErrorCallBack = NULL; + uartHandle->userCallBack.WriteDmaFinishCallBack = NULL; /* Clear user call back function of DMA. */ + uartHandle->userCallBack.ReadDmaFinishCallBack = NULL; + uartHandle->userCallBack.TransmitDmaErrorCallBack = NULL; + uartHandle->txState = UART_STATE_NONE_INIT; /* Clear all state */ + uartHandle->rxState = UART_STATE_NONE_INIT; + return BASE_STATUS_OK; +} + +/** + * @brief Return the specified UART state. + * @param uartHandle UART handle. + * @retval UART state: UART_STATE_NONE_INIT(can not use), UART_STATE_READY, UART_STATE_BUSY + * @retval UART_STATE_BUSY_TX, UART_STATE_BUSY_RX. + */ +UART_State_Type HAL_UART_GetState(UART_Handle *uartHandle) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + if (uartHandle->txState == UART_STATE_NONE_INIT) { + return UART_STATE_NONE_INIT; /* Uart Tx and Rx are not initialized */ + } + if (uartHandle->txState == UART_STATE_READY && uartHandle->rxState == UART_STATE_READY) { + return UART_STATE_READY; /* Uart Tx and Rx are ready */ + } + if (uartHandle->txState == UART_STATE_READY) { + return UART_STATE_BUSY_RX; /* Uart Rx is busy */ + } + if (uartHandle->rxState == UART_STATE_READY) { + return UART_STATE_BUSY_TX; /* Uart Tx is busy */ + } + return UART_STATE_BUSY; /* Uart Tx and Rx are busy */ +} + +/** + * @brief Send data in blocking mode. + * @param uartHandle UART handle. + * @param srcData Address of the data buff to be sent. + * @param dataLength number of the data to be sent. + * @param blockingTime Blocking time, unit: milliseconds. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_WriteBlocking(UART_Handle *uartHandle, unsigned char *srcData, + unsigned int dataLength, unsigned int blockingTime) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_ASSERT_PARAM(srcData != NULL); + UART_PARAM_CHECK_WITH_RET(uartHandle->txMode == UART_MODE_BLOCKING, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + unsigned long long setTick = SYSTICK_GetCRGHZ() / SYSTICK_MS_DIV * blockingTime; + UART_PARAM_CHECK_WITH_RET(setTick < SYSTICK_MAX_VALUE, BASE_STATUS_ERROR); + if (uartHandle->txState == UART_STATE_READY) { + uartHandle->txState = UART_STATE_BUSY_TX; + unsigned int txCount = dataLength; + unsigned char *src = srcData; + uartHandle->baseAddress->UART_IMSC.BIT.txim = BASE_CFG_DISABLE; /* Disable TX interrupt bit */ + uartHandle->baseAddress->UART_CR.BIT.txe = BASE_CFG_ENABLE; + unsigned long long deltaTick; + unsigned int preTick = DCL_SYSTICK_GetTick(); + unsigned int curTick = preTick; + while (txCount > 0x00) { + curTick = DCL_SYSTICK_GetTick(); + deltaTick = (curTick > preTick) ? (curTick - preTick) : (SYSTICK_MAX_VALUE - preTick + curTick); + if (deltaTick >= setTick) { + uartHandle->txState = UART_STATE_READY; + return BASE_STATUS_TIMEOUT; + } + if (uartHandle->baseAddress->UART_FR.BIT.txff == 0x01) { /* True when the TX FIFO is full */ + continue; + } + /* Blocking write to DR when register is empty */ + uartHandle->baseAddress->UART_DR.BIT.data = *(src); + src++; + txCount--; + } + } else { + return BASE_STATUS_BUSY; + } + uartHandle->txState = UART_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief Send data in interrupt mode. + * @param uartHandle UART handle. + * @param srcData Address of the data buff to be sent. + * @param dataLength Number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_WriteIT(UART_Handle *uartHandle, unsigned char *srcData, unsigned int dataLength) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_PARAM_CHECK_WITH_RET(uartHandle->txMode == UART_MODE_INTERRUPT, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(srcData != NULL, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + + if (uartHandle->txState == UART_STATE_READY) { + uartHandle->txState = UART_STATE_BUSY_TX; + uartHandle->txbuff = srcData; + uartHandle->txBuffSize = dataLength; + uartHandle->baseAddress->UART_ICR.BIT.txic = BASE_CFG_ENABLE; + uartHandle->baseAddress->UART_IMSC.BIT.txim = BASE_CFG_ENABLE; + WriteITCallBack(uartHandle); + } else { + return BASE_STATUS_BUSY; + } + return BASE_STATUS_OK; +} + +/** + * @brief Interrupt Clearing and Interrupt Callback. + * @param uartHandle UART handle. + * @retval None. + */ +static void WriteItCheck(UART_Handle *uartHandle) +{ + if (uartHandle->txBuffSize == 0) { + uartHandle->baseAddress->UART_IMSC.BIT.txim = BASE_CFG_DISABLE; + uartHandle->baseAddress->UART_ICR.BIT.txic = BASE_CFG_ENABLE; + uartHandle->txState = UART_STATE_READY; + if (uartHandle->userCallBack.WriteItFinishCallBack != NULL) { + uartHandle->userCallBack.WriteItFinishCallBack(uartHandle); /* user function callback */ + } + } else { + uartHandle->baseAddress->UART_IMSC.BIT.txim = BASE_CFG_ENABLE; + } +} + + +/** + * @brief Interrupt sending callback function. + * The hanler function is called when Tx interruption occurs. + * @param uartHandle UART handle. + * @retval None. + */ +static void WriteITCallBack(UART_Handle *uartHandle) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_ASSERT_PARAM(uartHandle->txbuff != NULL); + uartHandle->baseAddress->UART_IMSC.BIT.txim = BASE_CFG_DISABLE; + if (uartHandle->txState == UART_STATE_BUSY_TX) { + while (uartHandle->txBuffSize > 0) { + if (uartHandle->baseAddress->UART_FR.BIT.txff == 1) { /* True when the TX FIFO is full */ + break; + } + uartHandle->txBuffSize -= 1; + uartHandle->baseAddress->UART_DR.BIT.data = *(uartHandle->txbuff); + (uartHandle->txbuff)++; + } + WriteItCheck(uartHandle); + } + return; +} + +/** + * @brief Send data in DMA mode. + * @param uartHandle UART handle. + * @param srcData Address of the data buff to be sent. + * @param dataLength Number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_WriteDMA(UART_Handle *uartHandle, unsigned char *srcData, + unsigned int dataLength) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_PARAM_CHECK_WITH_RET(uartHandle->txMode == UART_MODE_DMA, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(srcData != NULL, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(IsDmaChannelNum(uartHandle->uartDmaTxChn) == true, BASE_STATUS_ERROR); + UART_ASSERT_PARAM(uartHandle->dmaHandle != NULL); + unsigned int channel = uartHandle->uartDmaTxChn; + if (uartHandle->txState == UART_STATE_READY) { + uartHandle->txState = UART_STATE_BUSY_TX; + uartHandle->baseAddress->UART_IMSC.BIT.txim = BASE_CFG_DISABLE; /* Disable TX interrupt bit */ + uartHandle->dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelFinishCallBack = WriteDMAFinishFun; + uartHandle->dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelErrorCallBack = TransmitDMAErrorFun; + uartHandle->txbuff = srcData; + uartHandle->txBuffSize = dataLength; + if (HAL_DMA_StartIT(uartHandle->dmaHandle, (uintptr_t)(void *)uartHandle->txbuff, + (uintptr_t)(void *)&(uartHandle->baseAddress->UART_DR), \ + dataLength, channel) != BASE_STATUS_OK) { + uartHandle->txState = UART_STATE_READY; + return BASE_STATUS_ERROR; + } + uartHandle->baseAddress->UART_DMACR.BIT.txdmae = BASE_CFG_ENABLE; /* Enable TX DMA bit */ + } else { + return BASE_STATUS_BUSY; + } + return BASE_STATUS_OK; +} + +/** + * @brief Receive data in blocking mode. + * @param uartHandle UART handle. + * @param saveData Address of the data buff to be saved. + * @param dataLength Length of the data int the storage buffer. + * @param blockingTime Blocking time, unit: milliseconds. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_ReadBlocking(UART_Handle *uartHandle, unsigned char *saveData, + unsigned int dataLength, unsigned int blockingTime) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(saveData != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_PARAM_CHECK_WITH_RET(uartHandle->rxMode == UART_MODE_BLOCKING, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(blockingTime > 0, BASE_STATUS_ERROR); + unsigned long long setTick = SYSTICK_GetCRGHZ() / SYSTICK_MS_DIV * blockingTime; + UART_PARAM_CHECK_WITH_RET(setTick < SYSTICK_MAX_VALUE, BASE_STATUS_ERROR); + if (uartHandle->rxState == UART_STATE_READY) { + uartHandle->rxState = UART_STATE_BUSY_RX; + unsigned int rxCount = dataLength; + unsigned char *save = saveData; + uartHandle->baseAddress->UART_IMSC.BIT.rxim = BASE_CFG_DISABLE; /* Disable RX interrupt bit */ + uartHandle->baseAddress->UART_ICR.reg = 0XFF; /* Clear interrupt flag */ + unsigned int tmp; + unsigned long long deltaTick; + unsigned int preTick = DCL_SYSTICK_GetTick(); + unsigned int curTick = preTick; + while (rxCount > 0) { + curTick = DCL_SYSTICK_GetTick(); + deltaTick = (curTick > preTick) ? (curTick - preTick) : (SYSTICK_MAX_VALUE - preTick + curTick); + if (deltaTick >= setTick) { + uartHandle->rxState = UART_STATE_READY; + return BASE_STATUS_TIMEOUT; + } + if (uartHandle->baseAddress->UART_FR.BIT.rxfe == 0x01) { + continue; + } + tmp = uartHandle->baseAddress->UART_DR.reg; + if (tmp & 0xF00) { /* True when receiving generated error */ + uartHandle->rxState = UART_STATE_READY; + return BASE_STATUS_ERROR; + } + *(save) = (tmp & 0xFF); /* The lower eight bits are the register data bits */ + save++; + rxCount--; + } + } else { + return BASE_STATUS_BUSY; + } + uartHandle->rxState = UART_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief Receive data in interrupt mode. + * @param uartHandle UART handle. + * @param saveData Address of the data buff to be saved. + * @param dataLength length of the data int the storage buffer. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_ReadIT(UART_Handle *uartHandle, unsigned char *saveData, unsigned int dataLength) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_ASSERT_PARAM(saveData != NULL); + UART_PARAM_CHECK_WITH_RET(uartHandle->rxMode == UART_MODE_INTERRUPT, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + + if (uartHandle->rxState == UART_STATE_READY) { + uartHandle->rxState = UART_STATE_BUSY_RX; + uartHandle->rxbuff = saveData; + uartHandle->rxBuffSize = dataLength; + uartHandle->baseAddress->UART_IMSC.reg |= 0x7D0; /* Enable rx interrupt and rx timeout interrupt */ + } else { + return BASE_STATUS_BUSY; + } + return BASE_STATUS_OK; +} + +/** + * @brief Interrupt receiving callback function. + * The hanler function is called when Rx interruption occurs. + * @param uartHandle UART handle. + * @retval None. + */ +static void ReadITCallBack(UART_Handle *uartHandle) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(uartHandle->rxbuff != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + if (uartHandle->rxState == UART_STATE_BUSY_RX) { + unsigned int tmp; + while (uartHandle->rxBuffSize > 0) { + if (uartHandle->baseAddress->UART_FR.BIT.rxfe == 0x01) { /* True when the RX FIFO is empty */ + break; + } + uartHandle->rxBuffSize -= 1; + tmp = uartHandle->baseAddress->UART_DR.reg; + *(uartHandle->rxbuff) = (tmp & 0xFF); /* Read from DR when holding register/FIFO is not empty */ + uartHandle->rxbuff++; + } + if (uartHandle->rxBuffSize == 0) { + uartHandle->baseAddress->UART_IMSC.reg &= 0xFFAF; /* Disable rxim and rtim */ + uartHandle->rxState = UART_STATE_READY; + } + uartHandle->baseAddress->UART_ICR.reg |= 0x50; /* Clear rxic and rtic */ + if (uartHandle->userCallBack.ReadItFinishCallBack != NULL && uartHandle->rxBuffSize == 0) { + uartHandle->userCallBack.ReadItFinishCallBack(uartHandle); + } + } + return; +} + +/** + * @brief Callback function of finishing receiving in DMA mode. + * The hanler function is called when Rx DMA Finish interruption occurs. + * @param handle DMA handle. + * @retval None. + */ +static void ReadDMAFinishFun(void *handle) +{ + UART_ASSERT_PARAM(handle != NULL); + UART_Handle *uartHandle = (UART_Handle *)(handle); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + uartHandle->rxState = UART_STATE_READY; + uartHandle->baseAddress->UART_DMACR.BIT.rxdmae = BASE_CFG_DISABLE; + uartHandle->rxBuffSize = 0; + if (uartHandle->userCallBack.ReadDmaFinishCallBack != NULL) { + uartHandle->userCallBack.ReadDmaFinishCallBack(uartHandle); /* User callback function */ + } + return; +} + +/** + * @brief Callback function of finishing sending in DMA mode. + * The hanler function is called when Tx DMA Finish interruption occurs. + * @param handle DMA handle. + * @retval None. + */ +static void WriteDMAFinishFun(void *handle) +{ + UART_ASSERT_PARAM(handle != NULL); + UART_Handle *uartHandle = (UART_Handle *)(handle); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + uartHandle->txState = UART_STATE_READY; + uartHandle->baseAddress->UART_DMACR.BIT.txdmae = BASE_CFG_DISABLE; + uartHandle->txBuffSize = 0; + if (uartHandle->userCallBack.WriteDmaFinishCallBack != NULL) { + uartHandle->userCallBack.WriteDmaFinishCallBack(uartHandle); /* User callback function */ + } + return; +} + +/** + * @brief Callback function of Tx/Rx error interrupt in DMA mode. + * The hanler function is called when Tx/Rx transmission error interruption occurs. + * @param handle DMA handle. + * @retval None. + */ +static void TransmitDMAErrorFun(void *handle) +{ + UART_ASSERT_PARAM(handle != NULL); + UART_Handle *uartHandle = (UART_Handle *)(handle); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + if (uartHandle->rxState == UART_STATE_BUSY_RX) { + uartHandle->baseAddress->UART_DMACR.BIT.rxdmae = BASE_CFG_DISABLE; + } + if (uartHandle->txState == UART_STATE_BUSY_TX) { + uartHandle->baseAddress->UART_DMACR.BIT.txdmae = BASE_CFG_DISABLE; + } + if (uartHandle->userCallBack.TransmitDmaErrorCallBack != NULL) { + uartHandle->userCallBack.TransmitDmaErrorCallBack(uartHandle); + } + uartHandle->txState = UART_STATE_READY; + uartHandle->rxState = UART_STATE_READY; + return; +} + +/** + * @brief Receive data in DMA mode. + * @param uartHandle UART handle. + * @param saveData Address of the data buff to be sent. + * @param dataLength number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_ReadDMA(UART_Handle *uartHandle, unsigned char *saveData, + unsigned int dataLength) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_ASSERT_PARAM(saveData != NULL); + UART_PARAM_CHECK_WITH_RET(uartHandle->rxMode == UART_MODE_DMA, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(IsDmaChannelNum(uartHandle->uartDmaRxChn) == true, BASE_STATUS_ERROR); + UART_ASSERT_PARAM(uartHandle->dmaHandle != NULL); + unsigned int channel = uartHandle->uartDmaRxChn; + if (uartHandle->rxState == UART_STATE_READY) { + uartHandle->rxState = UART_STATE_BUSY_RX; + uartHandle->baseAddress->UART_IMSC.BIT.rxim = BASE_CFG_DISABLE; /* Disable RX interrupt bit */ + uartHandle->dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelFinishCallBack = ReadDMAFinishFun; + uartHandle->dmaHandle->userCallBack.DMA_CallbackFuns[channel].ChannelErrorCallBack = TransmitDMAErrorFun; + uartHandle->rxbuff = saveData; + uartHandle->rxBuffSize = dataLength; + /* Can not masking overflow error, break error, check error, frame error interrupt */ + if (HAL_DMA_StartIT(uartHandle->dmaHandle, (uintptr_t)(void *)&(uartHandle->baseAddress->UART_DR), + (uintptr_t)(void *)uartHandle->rxbuff, dataLength, channel) != BASE_STATUS_OK) { + uartHandle->rxState = UART_STATE_READY; + return BASE_STATUS_ERROR; + } + uartHandle->baseAddress->UART_DMACR.BIT.rxdmae = BASE_CFG_ENABLE; /* Enable RX_DMA bit */ + } else { + return BASE_STATUS_BUSY; + } + return BASE_STATUS_OK; +} + +/** + * @brief Stop the process of sending data in interrupt or DMA mode. + * @param uartHandle UART handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_StopWrite(UART_Handle *uartHandle) /* Only support UART_MODE_INTERRUPT and UART_MODE_DMA */ +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_ASSERT_PARAM(uartHandle->dmaHandle != NULL); + UART_PARAM_CHECK_WITH_RET(IsDmaChannelNum(uartHandle->uartDmaRxChn) == true, BASE_STATUS_ERROR); + /* Blocking send interrupt. */ + uartHandle->baseAddress->UART_IMSC.BIT.txim = BASE_CFG_DISABLE; + if (uartHandle->txMode == UART_MODE_DMA) { + uartHandle->baseAddress->UART_DMACR.BIT.txdmae = BASE_CFG_DISABLE; /* Disable TX FIFO of DMA. */ + if (HAL_DMA_StopChannel(uartHandle->dmaHandle, uartHandle->uartDmaTxChn) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + } + uartHandle->txState = UART_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief Stop the process of receiving data in interrupt or DMA mode. + * @param uartHandle UART handle. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_StopRead(UART_Handle *uartHandle) /* Only support UART_MODE_INTERRUPT and UART_MODE_DMA */ +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_ASSERT_PARAM(uartHandle->dmaHandle != NULL); + UART_PARAM_CHECK_WITH_RET(IsDmaChannelNum(uartHandle->uartDmaRxChn) == true, BASE_STATUS_ERROR); + unsigned int val = uartHandle->baseAddress->UART_IMSC.reg; + val &= 0xFFFFF82F; /* Disable bits: rxim, rtim, feim, peim, beim, oeim */ + uartHandle->baseAddress->UART_IMSC.reg = val; + if (uartHandle->rxMode == UART_MODE_DMA) { + uartHandle->baseAddress->UART_DMACR.BIT.rxdmae = BASE_CFG_DISABLE; + if (HAL_DMA_StopChannel(uartHandle->dmaHandle, uartHandle->uartDmaRxChn) != BASE_STATUS_OK) { + return BASE_STATUS_ERROR; + } + } + uartHandle->rxState = UART_STATE_READY; + return BASE_STATUS_OK; +} + +/** + * @brief Error handler function of receiving. + * @param uartHandle UART handle. + * @retval None. + */ +static void ErrorServiceCallback(UART_Handle *uartHandle) +{ + unsigned int error = 0x00; + if (uartHandle->baseAddress->UART_MIS.BIT.oemis == BASE_CFG_ENABLE) { /* Overflow error interrupt */ + error |= uartHandle->baseAddress->UART_MIS.BIT.oemis; + uartHandle->baseAddress->UART_ICR.BIT.oeic = BASE_CFG_ENABLE; + } else if (uartHandle->baseAddress->UART_MIS.BIT.bemis == BASE_CFG_ENABLE) { /* Break error interrupt */ + error |= uartHandle->baseAddress->UART_MIS.BIT.bemis; + uartHandle->baseAddress->UART_ICR.BIT.beic = BASE_CFG_ENABLE; + } else if (uartHandle->baseAddress->UART_MIS.BIT.pemis == BASE_CFG_ENABLE) { /* Check error interrupt */ + error |= uartHandle->baseAddress->UART_MIS.BIT.pemis; + uartHandle->baseAddress->UART_ICR.BIT.peic = BASE_CFG_ENABLE; + } else if (uartHandle->baseAddress->UART_MIS.BIT.femis == BASE_CFG_ENABLE) { /* Frame error interrupt */ + error |= uartHandle->baseAddress->UART_MIS.BIT.femis; + uartHandle->baseAddress->UART_ICR.BIT.feic = BASE_CFG_ENABLE; + } + if (error != 0x00) { + uartHandle->errorType = error; + if (uartHandle->rxMode == UART_MODE_INTERRUPT && uartHandle->userCallBack.TransmitItErrorCallBack != NULL) { + uartHandle->userCallBack.TransmitItErrorCallBack(uartHandle); + } + } + return; +} + +/** + * @brief UART Interrupt service processing function. + * @param handle UART handle. + * @retval None. + */ +void HAL_UART_IrqHandler(void *handle) +{ + UART_ASSERT_PARAM(handle != NULL); + UART_Handle *uartHandle = (UART_Handle *)handle; + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + /* when tx interrupt is generated and register/FIFO is empty */ + if ((uartHandle->baseAddress->UART_MIS.BIT.txmis == 0x01) && + (uartHandle->baseAddress->UART_FR.BIT.txfe == 0x01)) { + WriteITCallBack(uartHandle); + } + /* when rx interrupt is generated and register/FIFO is not empty */ + if ((uartHandle->baseAddress->UART_MIS.BIT.rxmis == 0x01 || uartHandle->baseAddress->UART_MIS.BIT.rtmis == 0x01) && + (uartHandle->baseAddress->UART_FR.BIT.rxfe != 0x1)) { + ReadITCallBack(uartHandle); + } + if ((uartHandle->baseAddress->UART_MIS.reg & 0x780)) { + ErrorServiceCallback(uartHandle); + } + return; +} + +/** + * @brief User callback function registration interface. + * @param uartHandle UART handle. + * @param typeID Id of callback function type, @ref UART_CallbackFun_Type + * @param pCallback pointer of the specified callbcak function, @ref UART_CallbackType + * @retval BASE_StatusType: OK, ERROR. + */ +BASE_StatusType HAL_UART_RegisterCallBack(UART_Handle *uartHandle, UART_CallbackFun_Type typeID, + UART_CallbackType pCallback) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + switch (typeID) { + case UART_WRITE_IT_FINISH: /* uart write finish call back. */ + uartHandle->userCallBack.WriteItFinishCallBack = pCallback; + break; + case UART_READ_IT_FINISH: /* uart read interrupt call back. */ + uartHandle->userCallBack.ReadItFinishCallBack = pCallback; + break; + case UART_WRITE_DMA_FINISH: /* uart write dma finish call back. */ + uartHandle->userCallBack.WriteDmaFinishCallBack = pCallback; + break; + case UART_READ_DMA_FINISH: /* uart read dma finish call back. */ + uartHandle->userCallBack.ReadDmaFinishCallBack = pCallback; + break; + case UART_TRNS_IT_ERROR: /* uart transmit error call back. */ + uartHandle->userCallBack.TransmitItErrorCallBack = pCallback; + break; + case UART_TRNS_DMA_ERROR: /* uart transmit DMA error call back. */ + uartHandle->userCallBack.TransmitDmaErrorCallBack = pCallback; + break; + default: + return BASE_STATUS_ERROR; + } + return BASE_STATUS_OK; +} + +/** + * @brief UART DAM(rx to memory), cyclically stores data to specified memory(saveData). + * @param uartHandle UART handle. + * @param saveData Address of the data buff to be sent. + * @param tempNode DMA Link List, @ref DMA_LinkList + * @param dataLength number of the data to be sent. + * @retval BASE status type: OK, ERROR, BUSY, TIMEOUT. + */ +BASE_StatusType HAL_UART_ReadDMAAndCyclicallyStored(UART_Handle *uartHandle, unsigned char *saveData, + DMA_LinkList *tempNode, unsigned int dataLength) +{ + /* Param check */ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(tempNode != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_ASSERT_PARAM(saveData != NULL); + UART_PARAM_CHECK_WITH_RET(dataLength > 0, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(uartHandle->rxMode == UART_MODE_DMA, BASE_STATUS_ERROR); + UART_PARAM_CHECK_WITH_RET(IsDmaChannelNum(uartHandle->uartDmaRxChn) == true, BASE_STATUS_ERROR); + UART_ASSERT_PARAM(uartHandle->dmaHandle != NULL); + + unsigned int channel = uartHandle->uartDmaRxChn; + if (uartHandle->rxState == UART_STATE_READY) { + uartHandle->rxState = UART_STATE_BUSY_RX; + uartHandle->baseAddress->UART_IMSC.BIT.rxim = BASE_CFG_DISABLE; /* Disable RX interrupt bit */ + uartHandle->rxbuff = saveData; + uartHandle->rxBuffSize = dataLength; + + /* Init DAM Channel Params */ + DMA_ChannelParam dmaParams; + dmaParams.direction = uartHandle->dmaHandle->DMA_Channels[channel].direction; + dmaParams.srcAddrInc = uartHandle->dmaHandle->DMA_Channels[channel].srcAddrInc; + dmaParams.destAddrInc = uartHandle->dmaHandle->DMA_Channels[channel].destAddrInc; + dmaParams.srcPeriph = uartHandle->dmaHandle->DMA_Channels[channel].srcPeriph; + dmaParams.destPeriph = uartHandle->dmaHandle->DMA_Channels[channel].destPeriph; + dmaParams.srcWidth = uartHandle->dmaHandle->DMA_Channels[channel].srcWidth; + dmaParams.destWidth = uartHandle->dmaHandle->DMA_Channels[channel].destWidth; + dmaParams.srcBurst = uartHandle->dmaHandle->DMA_Channels[channel].srcBurst; + dmaParams.destBurst = uartHandle->dmaHandle->DMA_Channels[channel].destBurst; + + /* Initialize List Node */ + if (HAL_DMA_InitNewNode(tempNode, &dmaParams, (uintptr_t)(void *)&(uartHandle->baseAddress->UART_DR), \ + (uintptr_t)(void *)uartHandle->rxbuff, dataLength) != BASE_STATUS_OK) { + uartHandle->rxState = UART_STATE_READY; + return BASE_STATUS_ERROR; + } + if (HAL_DMA_ListAddNode(tempNode, tempNode) != BASE_STATUS_OK) { + uartHandle->rxState = UART_STATE_READY; + return BASE_STATUS_ERROR; + } + + /* Can not masking overflow error, break error, check error, frame error interrupt */ + if (HAL_DMA_StartListTransfer(uartHandle->dmaHandle, tempNode, channel) != BASE_STATUS_OK) { + uartHandle->rxState = UART_STATE_READY; + return BASE_STATUS_ERROR; + } + uartHandle->baseAddress->UART_DMACR.BIT.rxdmae = BASE_CFG_ENABLE; /* Enable RX_DMA bit */ + } else { + /* Rx not ready */ + return BASE_STATUS_BUSY; + } + /* All done */ + return BASE_STATUS_OK; +} + +/** + * @brief Obtains offset address of DMA transfer address relative to specified memory (rxbuff). + * @param uartHandle UART handle. + * @retval offset address of DMA transfer address relative to specified memory (rxbuff). + */ +unsigned int HAL_UART_ReadDMAGetPos(UART_Handle *uartHandle) +{ + UART_ASSERT_PARAM(uartHandle != NULL); + UART_ASSERT_PARAM(uartHandle->dmaHandle != NULL); + UART_ASSERT_PARAM(uartHandle->rxbuff != NULL); + UART_ASSERT_PARAM(IsUARTInstance(uartHandle->baseAddress)); + UART_PARAM_CHECK_WITH_RET(IsDmaChannelNum(uartHandle->uartDmaRxChn) == true, BASE_STATUS_ERROR); + UART_ASSERT_PARAM(uartHandle->dmaHandle->DMA_Channels[uartHandle->uartDmaRxChn].channelAddr != NULL); + unsigned int writePos = 0; + /* Obtain the read destination address */ + unsigned int readAddress = uartHandle->dmaHandle->\ + DMA_Channels[uartHandle->uartDmaRxChn].channelAddr->DMAC_Cn_DEST_ADDR.reg; + if (readAddress > (uintptr_t)uartHandle->rxbuff) { + writePos = readAddress - (uintptr_t)uartHandle->rxbuff; /* Number of characters currently transferred */ + } else { + writePos = 0; + } + return writePos; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/wdg/common/inc/wdg.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/wdg/common/inc/wdg.h new file mode 100644 index 00000000..5892ddf4 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/wdg/common/inc/wdg.h @@ -0,0 +1,96 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file wdg.h + * @author MCU Driver Team + * @brief WDG module driver + * @details The header file contains the following declaration: + * + WDG handle structure definition. + * + Initialization functions. + * + WDG Set And Get Functions. + * + Interrupt Handler Functions. + */ + +#ifndef McuMagicTag_WDG_H +#define McuMagicTag_WDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "wdg_ip.h" +/** + * @defgroup WDG WDG + * @brief WDG module. + * @{ + */ + +/** + * @defgroup WDG_Common WDG Common + * @brief WDG common external module. + * @{ + */ + +/** + * @defgroup WDG_Handle_Definition WDG Handle Definition + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ +typedef void (* WDG_CallbackType)(void *handle); + +/** + * @brief WDG handle structure definition. + */ +typedef struct _WDG_Handle { + WDG_RegStruct *baseAddress; /**< WDG Registers address. */ + unsigned int timeValue; /**< WDG time value. */ + WDG_TimeType timeType; /**< WDG time type. */ + bool enableIT; /**< true:enable false:disable interrupt. */ + WDG_UserCallBack userCallBack; /**< User callback */ + WDG_ExtendHandle handleEx; /**< WDG extend parameter */ +} WDG_Handle; + +/** + * @} + */ + +/** + * @defgroup WDG_API_Declaration WDG HAL API + * @{ + */ + +BASE_StatusType HAL_WDG_Init(WDG_Handle *handle); +void HAL_WDG_SetTimeValue(WDG_Handle *handle, unsigned int timeValue, WDG_TimeType timeType); +unsigned int HAL_WDG_GetLoadValue(WDG_Handle *handle); +unsigned int HAL_WDG_GetCounterValue(WDG_Handle *handle); +void HAL_WDG_Refresh(WDG_Handle *handle); +void HAL_WDG_Start(WDG_Handle *handle); +void HAL_WDG_Stop(WDG_Handle *handle); +void HAL_WDG_RegisterCallback(WDG_Handle *handle, WDG_CallbackType callBackFunc); +void HAL_WDG_IrqHandler(void *handle); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_WDG_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/wdg/inc/wdg_ip.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/wdg/inc/wdg_ip.h new file mode 100644 index 00000000..512f5793 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/wdg/inc/wdg_ip.h @@ -0,0 +1,314 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file wdg_ip.h + * @author MCU Driver Team + * @brief WDG module driver + * @details The header file contains the following declaration: + * + WDG configuration enums. + * + WDG register structures. + * + WDG DCL Functions. + * + Parameters check functions. + */ + +#ifndef McuMagicTag_WDG_IP_H +#define McuMagicTag_WDG_IP_H + +/* Includes ------------------------------------------------------------------*/ +#include "baseinc.h" +/* Macro definition */ +#ifdef WDG_PARAM_CHECK + #define WDG_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM + #define WDG_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET + #define WDG_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else + #define WDG_ASSERT_PARAM(para) ((void)0U) + #define WDG_PARAM_CHECK_NO_RET(para) ((void)0U) + #define WDG_PARAM_CHECK_WITH_RET(param, ret) ((void)0U) +#endif +/** + * @addtogroup WDG + * @{ + */ + +/** + * @defgroup WDG_IP WDG_IP + * @brief WDG_IP: wdg_v0. + * @{ + */ + +/** + * @defgroup WDG_Param_Def WDG Parameters Definition + * @brief Description of WDG configuration parameters. + * @{ + */ +/* MACRO definitions -------------------------------------------------------*/ +#define FREQ_CONVERT_MS_UNIT 1000 +#define FREQ_CONVERT_US_UNIT 1000000 +/* Typedef definitions -------------------------------------------------------*/ +typedef enum { + WDG_TIME_UNIT_TICK = 0x00000000U, + WDG_TIME_UNIT_S = 0x00000001U, + WDG_TIME_UNIT_MS = 0x00000002U, + WDG_TIME_UNIT_US = 0x00000003U +} WDG_TimeType; + +/** + * @brief WDG extend handle. + */ +typedef struct _WDG_ExtendHandle { +} WDG_ExtendHandle; + +/** + * @brief WDG user callback. + */ +typedef struct { + void (* CallbackFunc)(void *handle); /**< WDG callback Function */ +} WDG_UserCallBack; +/** + * @} + */ + +/** + * @defgroup WDG_Reg_Def WDG Register Definition + * @brief Description WDG register mapping structure. + * @{ + */ + +/** + * @brief WDG enable interrupt and reset. + */ +typedef union { + unsigned int reg; + struct { + unsigned int wdgen : 1; /**< enable interrupt. */ + unsigned int resen : 1; /**< enable reset. */ + unsigned int reserved0 : 30; + } BIT; +} volatile WDG_CONTROL_REG; + +/** + * @brief WDG original interrupt signal. + */ +typedef union { + unsigned int reg; + struct { + unsigned int wdogris : 1; /**< original interrupt status. */ + unsigned int reserved : 31; + } BIT; +} volatile WDG_RIS_REG; + +/** + * @brief mask interrupt signal. + */ +typedef union { + unsigned int reg; + struct { + unsigned int wdogmis : 1; /**< maske interrupt status. */ + unsigned int reserved : 31; + } BIT; +} volatile WDG_MIS_REG; + +/** + * @brief WDG Register Structure definition. + */ +typedef struct { + unsigned int wdg_load; /**< WDG load value register. */ + unsigned int wdgvalue; /**< WDG current value register. */ + WDG_CONTROL_REG WDG_CONTROL; /**< WDG interrupt and reset enable register. */ + unsigned int wdg_intclr; /**< WDG interrupt clear register. */ + WDG_RIS_REG WDG_RIS; /**< WDG original interrupt register. */ + WDG_MIS_REG WDG_MIS; /**< WDG mask interrupt register. */ + unsigned int reserved0[762]; + unsigned int wdg_lock; /**< WDG lock register. */ +} volatile WDG_RegStruct; + +/** + * @} + */ + +/** + * @brief Setting the load value of the WDG counter. + * @param wdgx Value of @ref WDG_RegStruct. + * @param loadValue Load value of the WDG counter. + * @retval None. + */ +static inline void DCL_WDG_SetLoadValue(WDG_RegStruct *wdgx, unsigned int loadValue) +{ + WDG_ASSERT_PARAM(IsWDGInstance(wdgx)); + wdgx->wdg_load = loadValue; +} + +/** + * @brief Getting the load value of the WDG load register. + * @param wdgx Value of @ref WDG_RegStruct. + * @retval unsigned int WDG load value. + */ +static inline unsigned int DCL_WDG_GetLoadValue(const WDG_RegStruct *wdgx) +{ + WDG_ASSERT_PARAM(IsWDGInstance(wdgx)); + return wdgx->wdg_load; +} + +/** + * @brief Getting the value of the WDG counter register. + * @param wdgx Value of @ref WDG_RegStruct. + * @retval unsigned int WDG counter value. + */ +static inline unsigned int DCL_WDG_GetCounterValue(const WDG_RegStruct *wdgx) +{ + WDG_ASSERT_PARAM(IsWDGInstance(wdgx)); + return wdgx->wdgvalue; +} + +/** + * @brief Clear interrupt and reload watchdog counter value. + * @param wdgx Value of @ref WDG_RegStruct. + * @retval None. + */ +static inline void DCL_WDG_Refresh(WDG_RegStruct *wdgx) +{ + WDG_ASSERT_PARAM(IsWDGInstance(wdgx)); + wdgx->wdg_intclr = BASE_CFG_SET; +} + +/** + * @brief Getting value of WDG RIS register. + * @param wdgx Value of @ref WDG_RegStruct. + * @retval unsigned int Value of WDG RIS register. + */ +static inline unsigned int DCL_WDG_GetRIS(WDG_RegStruct *wdgx) +{ + WDG_ASSERT_PARAM(IsWDGInstance(wdgx)); + return wdgx->WDG_RIS.BIT.wdogris; +} + +/** + * @brief Getting value of WDG MIS register. + * @param wdgx Value of @ref WDG_RegStruct. + * @retval unsigned int Value of WDG MIS register. + */ +static inline unsigned int DCL_WDG_GetMIS(WDG_RegStruct *wdgx) +{ + WDG_ASSERT_PARAM(IsWDGInstance(wdgx)); + return wdgx->WDG_MIS.BIT.wdogmis; +} + +/** + * @brief Disable write and read WDG registers except WDG_LOCK. + * @param wdgx Value of @ref WDG_RegStruct. + * @retval None. + */ +static inline void DCL_WDG_LockReg(WDG_RegStruct *wdgx) +{ + WDG_ASSERT_PARAM(IsWDGInstance(wdgx)); + wdgx->wdg_lock = BASE_CFG_SET; +} + +/** + * @brief Enable write and read WDG registers. + * @param wdgx Value of @ref WDG_RegStruct. + * @retval None. + */ +static inline void DCL_WDG_UnlockReg(WDG_RegStruct *wdgx) +{ + WDG_ASSERT_PARAM(IsWDGInstance(wdgx)); + wdgx->wdg_lock = 0x1ACCE551U; /* Unlock register value */ +} + +/** + * @brief Enable reset signal. + * @param wdgx Value of @ref WDG_RegStruct. + * @retval None. + */ +static inline void DCL_WDG_EnableReset(WDG_RegStruct *wdgx) +{ + WDG_ASSERT_PARAM(IsWDGInstance(wdgx)); + wdgx->WDG_CONTROL.BIT.resen = BASE_CFG_SET; +} + +/** + * @brief Disable reset signal. + * @param wdgx Value of @ref WDG_RegStruct. + * @retval None. + */ +static inline void DCL_WDG_DisableReset(WDG_RegStruct *wdgx) +{ + WDG_ASSERT_PARAM(IsWDGInstance(wdgx)); + wdgx->WDG_CONTROL.BIT.resen = BASE_CFG_UNSET; +} + +/** + * @brief Start watchdog and enable interrupt signal. + * @param wdgx Value of @ref WDG_RegStruct. + * @retval None. + */ +static inline void DCL_WDG_EnableInterrupt(WDG_RegStruct *wdgx) +{ + WDG_ASSERT_PARAM(IsWDGInstance(wdgx)); + wdgx->WDG_CONTROL.BIT.wdgen = BASE_CFG_SET; +} + +/** + * @brief Disable interrupt signal. + * @param wdgx Value of @ref WDG_RegStruct. + * @retval None. + */ +static inline void DCL_WDG_DisableInterrupt(WDG_RegStruct *wdgx) +{ + WDG_ASSERT_PARAM(IsWDGInstance(wdgx)); + wdgx->WDG_CONTROL.BIT.wdgen = BASE_CFG_UNSET; +} + +/** + * @brief check wdg time type parameter. + * @param timeType Value of @ref WDG_TimeType. + * @retval Bool. + */ +static inline bool IsWdgTimeType(WDG_TimeType timeType) +{ + return (timeType == WDG_TIME_UNIT_TICK || + timeType == WDG_TIME_UNIT_S || + timeType == WDG_TIME_UNIT_MS || + timeType == WDG_TIME_UNIT_US); +} + +/** + * @brief check wdg time value parameter. + * @param baseAddress Value of @ref WDG_RegStruct + * @param timeValue time value + * @param timeType Value of @ref WDG_TimeType. + * @retval Bool. + */ +static inline bool IsWdgTimeValue(WDG_RegStruct *baseAddress, float timeValue, WDG_TimeType timeType) +{ + float clockFreq = (float)HAL_CRG_GetIpFreq((void *)baseAddress); + float maxSecond = (float)(0xFFFFFFFF / clockFreq); /* 0xFFFFFFFF max WDG register value */ + return ((timeType == WDG_TIME_UNIT_TICK && timeValue <= 0xFFFFFFFF) || + (timeType == WDG_TIME_UNIT_S && maxSecond >= timeValue) || + (timeType == WDG_TIME_UNIT_MS && maxSecond >= timeValue / FREQ_CONVERT_MS_UNIT) || + (timeType == WDG_TIME_UNIT_US && maxSecond >= timeValue / FREQ_CONVERT_US_UNIT)); +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_WDG_IP_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/wdg/src/wdg.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/wdg/src/wdg.c new file mode 100644 index 00000000..3edca1d2 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/drivers/wdg/src/wdg.c @@ -0,0 +1,216 @@ +/** + * @copyright Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file wdg.c + * @author MCU Driver Team + * @brief WDG module driver + * @details This file provides firmware functions to manage the following functionalities of the WDG. + * + Initialization functions. + * + WDG Set And Get Functions. + * + Interrupt Handler Functions. + */ + +/* Includes ------------------------------------------------------------------*/ +#include "interrupt.h" +#include "wdg.h" + +static unsigned int WDG_CalculateRegTimeout(WDG_RegStruct *baseAddress, float timeValue, WDG_TimeType timeType); + +/** + * @brief Initializing WDG values + * @param handle Value of @ref WDG_handle. + * @retval BASE_StatusType: OK, Error + */ +BASE_StatusType HAL_WDG_Init(WDG_Handle *handle) +{ + WDG_ASSERT_PARAM(handle != NULL); + WDG_ASSERT_PARAM(IsWDGInstance(handle->baseAddress)); + WDG_PARAM_CHECK_WITH_RET(IsWdgTimeType(handle->timeType), BASE_STATUS_ERROR); + WDG_PARAM_CHECK_WITH_RET(IsWdgTimeValue(handle->baseAddress, handle->timeValue, handle->timeType), + BASE_STATUS_ERROR); + /* baseaddress = WDG */ + HAL_WDG_SetTimeValue(handle, handle->timeValue, handle->timeType); + /* Set Watchdog Reset and Interrupt */ + handle->baseAddress->WDG_CONTROL.BIT.resen = BASE_CFG_ENABLE; + handle->baseAddress->WDG_CONTROL.BIT.wdgen = handle->enableIT; + return BASE_STATUS_OK; +} + +/** + * @brief Calculate Reg Timeout. + * @param timeValue Value to be load to wdg. + * @param timeType Value of @ref WDG_TimeType. + * @retval unsigned int timeout Value. + */ +static unsigned int WDG_CalculateRegTimeout(WDG_RegStruct *baseAddress, float timeValue, WDG_TimeType timeType) +{ + float clockFreq = (float)HAL_CRG_GetIpFreq((void *)baseAddress); + unsigned int timeoutValue = 0x00000000U; + switch (timeType) { + case WDG_TIME_UNIT_TICK: /* If the time type is tick, calculate the timeout value. */ + timeoutValue = (unsigned int)timeValue; + break; + case WDG_TIME_UNIT_S: /* If the time type is s, calculate the timeout value. */ + timeoutValue = (unsigned int)(timeValue * clockFreq); + break; + case WDG_TIME_UNIT_MS: /* If the time type is ms, calculate the timeout value. */ + timeoutValue = (unsigned int)(timeValue * clockFreq / FREQ_CONVERT_MS_UNIT); + break; + case WDG_TIME_UNIT_US: /* If the time type is us, calculate the timeout value. */ + timeoutValue = (unsigned int)(timeValue * clockFreq / FREQ_CONVERT_US_UNIT); + break; + default: + break; + } + return timeoutValue; +} + +/** + * @brief Setting the load value of the WDG counter. + * @param handle Value of @ref WDG_handle. + * @param timeValue time value. + * @param timeType WDG time type. + * @retval None. + */ +void HAL_WDG_SetTimeValue(WDG_Handle *handle, unsigned int timeValue, WDG_TimeType timeType) +{ + WDG_ASSERT_PARAM(handle != NULL); + WDG_ASSERT_PARAM(IsWDGInstance(handle->baseAddress)); + WDG_PARAM_CHECK_NO_RET(IsWdgTimeType(timeType)); + WDG_PARAM_CHECK_NO_RET(IsWdgTimeValue(handle->baseAddress, timeValue, timeType)); + /* handle->baseAddress only could be configured WDG */ + unsigned int value = WDG_CalculateRegTimeout(handle->baseAddress, timeValue, timeType); + DCL_WDG_SetLoadValue(handle->baseAddress, value); +} + +/** + * @brief refresh the WDG counter. + * @param handle Value of @ref WDG_handle. + * @retval None. + */ +void HAL_WDG_Refresh(WDG_Handle *handle) +{ + WDG_ASSERT_PARAM(handle != NULL); + WDG_ASSERT_PARAM(IsWDGInstance(handle->baseAddress)); + handle->baseAddress->wdg_intclr = BASE_CFG_SET; /* clear wdg interrupt and load value */ +} + +/** + * @brief obtain the wdg load value. + * @param handle Value of @ref WDG_handle. + * @retval unsigned int time value. + */ +unsigned int HAL_WDG_GetLoadValue(WDG_Handle *handle) +{ + WDG_ASSERT_PARAM(handle != NULL); + WDG_ASSERT_PARAM(IsWDGInstance(handle->baseAddress)); + return DCL_WDG_GetLoadValue(handle->baseAddress); +} + +/** + * @brief obtain the current count value.. + * @param handle Value of @ref WDG_handle. + * @retval unsigned int Counter value. + */ +unsigned int HAL_WDG_GetCounterValue(WDG_Handle *handle) +{ + WDG_ASSERT_PARAM(handle != NULL); + WDG_ASSERT_PARAM(IsWDGInstance(handle->baseAddress)); + float res = (float)handle->baseAddress->wdgvalue; + unsigned int freq = HAL_CRG_GetIpFreq((void *)handle->baseAddress); + /* check clockFreq not equal zero */ + if (freq == 0) { + return 0; + } + switch (handle->timeType) { + case WDG_TIME_UNIT_TICK : /* Number of tick currently calculated */ + break; + case WDG_TIME_UNIT_S : + /* Number of seconds currently calculated */ + res = res / freq; + break; + case WDG_TIME_UNIT_MS : + res = res * FREQ_CONVERT_MS_UNIT / freq; + break; + case WDG_TIME_UNIT_US : + /* Number of microseconds currently calculated */ + res = res * FREQ_CONVERT_US_UNIT / freq; + break; + default: + break; + } + return (unsigned int)res; /* return current counter value */ +} + +/** + * @brief Start the WDG count. + * @param handle Value of @ref WDG_handle. + * @retval None. + */ +void HAL_WDG_Start(WDG_Handle *handle) +{ + WDG_ASSERT_PARAM(handle != NULL); + WDG_ASSERT_PARAM(IsWDGInstance(handle->baseAddress)); + DCL_WDG_EnableInterrupt(handle->baseAddress); + DCL_WDG_Refresh(handle->baseAddress); +} + +/** + * @brief Stop the WDG count. + * @param handle Value of @ref WDG_handle. + * @retval None. + */ +void HAL_WDG_Stop(WDG_Handle *handle) +{ + WDG_ASSERT_PARAM(handle != NULL); + WDG_ASSERT_PARAM(IsWDGInstance(handle->baseAddress)); + DCL_WDG_DisableReset(handle->baseAddress); + DCL_WDG_DisableInterrupt(handle->baseAddress); +} + +/** + * @brief Register WDG interrupt callback. + * @param handle Value of @ref WDG_handle. + * @param callBackFunc Value of @ref WDG_CallbackType. + * @retval None + */ +void HAL_WDG_RegisterCallback(WDG_Handle *handle, WDG_CallbackType callBackFunc) +{ + WDG_ASSERT_PARAM(handle != NULL); + WDG_ASSERT_PARAM(IsWDGInstance(handle->baseAddress)); + if (callBackFunc != NULL) { + handle->userCallBack.CallbackFunc = callBackFunc; + } +} + +/** + * @brief Interrupt hanlder processing function. + * @param handle WDG_Handle. + * @retval None. + */ +void HAL_WDG_IrqHandler(void *handle) +{ + WDG_Handle *wdgHandle = (WDG_Handle *)handle; + WDG_ASSERT_PARAM(wdgHandle != NULL); + WDG_ASSERT_PARAM(IsWDGInstance(wdgHandle->baseAddress)); + + if (wdgHandle->baseAddress->WDG_MIS.BIT.wdogmis == 0x01) { /* Interrupt flag is set, fed dog in callback */ + if (wdgHandle->userCallBack.CallbackFunc) { + wdgHandle->userCallBack.CallbackFunc(wdgHandle); + } + } +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/adc_calibra/mcs_adcCalibr.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/adc_calibra/mcs_adcCalibr.c new file mode 100644 index 00000000..a4fdeb63 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/adc_calibra/mcs_adcCalibr.c @@ -0,0 +1,98 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_adcCalibr.c + * @author MCU Algorithm Team + * @brief This file provides adc bias calibration function. 0722-7 + */ +#include "mcs_adcCalibr.h" +#include "mcs_assert.h" + + +/** + * @brief Get ADC result when ADC conversion completes. + * @param adcCalibr ADC calibration value. + * @param soc ID of SOC. + * @retval None. + */ +static unsigned int ADCCALIBR_GetSocResult(ADC_Handle *adcHandle, unsigned int soc) +{ + MCS_ASSERT_PARAM(adcHandle != NULL); + /* wait for ADC conversion complete */ + while (1) { + /* Check ADC conversion if completes. */ + if (HAL_ADC_CheckSocFinish(adcHandle, soc) == BASE_STATUS_OK) { + break; + } + } + return DCL_ADC_ReadSOCxResult(adcHandle->baseAddress, soc); +} + +/** + * @brief ADC calibration initialization. + * @param adcCalibr ADC calibration value. + * @retval None. + */ +void ADCCALIBR_Init(ADC_CALIBR_Handle *adcCalibr) +{ + MCS_ASSERT_PARAM(adcCalibr != NULL); + adcCalibr->adcShiftAccu = 0; + adcCalibr->cnt = 0; + adcCalibr->state = ADC_CALIBR_NOT_FINISH; +} + +/** + * @brief Compute current sampling adc offset. + * @param adcCalibr ADC calibration handle. + * @param adcHandle ADC handle. + * @param soc ID of SOC. + * @retval offset val. + */ +unsigned int ADCCALIBR_Exec(ADC_CALIBR_Handle *adcCalibr, ADC_Handle *adcHandle, unsigned int soc) +{ + MCS_ASSERT_PARAM(adcCalibr != NULL); + MCS_ASSERT_PARAM(adcHandle != NULL); + MCS_ASSERT_PARAM(adcCalibr->adcShiftAccu <= 4096 * ADC_CNT_POINTS); /* 4096: 12-bit adc precision. */ + adcCalibr->cnt++; + /* sum of 50 points value */ + if (adcCalibr->cnt > ADC_CNT_POINTS) { + adcCalibr->cnt = ADC_CNT_POINTS; + adcCalibr->state = ADC_CALIBR_FINISH; + return (unsigned int)((float)(adcCalibr->adcShiftAccu) / (float)ADC_CNT_POINTS); + } else { + adcCalibr->adcShiftAccu += ADCCALIBR_GetSocResult(adcHandle, soc); + adcCalibr->state = ADC_CALIBR_NOT_FINISH; + return 0; + } + /* Returns the offset sampling average */ + return 0; +} + +/** + * @brief Returns the motor control status based on whether the calibration is complete or not. + * @param adcCalibr ADC calibration handle. + * @retval bool. + */ +bool ADCCALIBR_IsFinish(ADC_CALIBR_Handle *adcCalibr) +{ + MCS_ASSERT_PARAM(adcCalibr != NULL); + if (adcCalibr->state == ADC_CALIBR_FINISH) { + return true; + } + + return false; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/adc_calibra/mcs_adcCalibr.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/adc_calibra/mcs_adcCalibr.h new file mode 100644 index 00000000..87a21c00 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/adc_calibra/mcs_adcCalibr.h @@ -0,0 +1,55 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_adcCalibr.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration for adc bias calibration function. + */ +#ifndef McuMagicTag_MCS_ADCCALIB_H +#define McuMagicTag_MCS_ADCCALIB_H + +#include "adc.h" +#include "typedefs.h" + +/* Macro definitions --------------------------------------------------------------------------- */ +#define ADC_CNT_POINTS 50 /* the number of continuous adc results for calibration */ + +/** + * @brief ADC temperature calibration state. + */ +typedef enum { + ADC_CALIBR_NOT_FINISH = 0, + ADC_CALIBR_FINISH +} ADC_CALIBR_State; + +/** + * @brief Adc temperature shift calibration structure. + */ +typedef struct { + unsigned int adcShiftAccu; + unsigned int cnt; + ADC_CALIBR_State state; +} ADC_CALIBR_Handle; + + +void ADCCALIBR_Init(ADC_CALIBR_Handle *adcCalibr); + +unsigned int ADCCALIBR_Exec(ADC_CALIBR_Handle *adcCalibr, ADC_Handle *adcHandle, unsigned int soc); + +bool ADCCALIBR_IsFinish(ADC_CALIBR_Handle *adcCalibr); + +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/brake/mcs_brake.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/brake/mcs_brake.c new file mode 100644 index 00000000..357cce8d --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/brake/mcs_brake.c @@ -0,0 +1,105 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_brake.c + * @author MCU Algorithm Team + * @brief This file provides functions of brake module. + */ +#include "mcs_brake.h" +#include "mcs_math.h" +#include "mcs_assert.h" + + +/** + * @brief Initialize brake handle. + * @param brake: Pointer of Brake Handle. + * @param brkParam: Brake parameters. + * @retval None. + */ +void BRAKE_Init(BRAKE_Handle *brake, BRAKE_Param *brkParam) +{ + MCS_ASSERT_PARAM(brake != NULL); + MCS_ASSERT_PARAM(brkParam != NULL); + MCS_ASSERT_PARAM(brkParam->ts > 0.0f); + /* Set brake parameter. */ + brake->brkParam = brkParam; + brake->sampleShiftDuty = brkParam->sampleWinTime / brkParam->ts; + /* Brake count. */ + brake->tickNum = (unsigned int)(brkParam->brkTime / brkParam->ts); +} + +/** + * @brief Clear historical values of brake handle. + * @param brake: Pointer of Brake Handle. + * @retval None. + */ +void BRAKE_Clear(BRAKE_Handle *brake) +{ + MCS_ASSERT_PARAM(brake != NULL); + brake->brkDuty = 0.0f; /* brake duty */ + /* counter for calculating brake time */ + brake->tickCnt = 0; + /* brake status */ + brake->brkFlg = 0; + + brake->brkFlg = BRAKE_WAIT; +} + +/** + * @brief Brake execution. + * @param brake: Pointer of Brake Handle. + * @param brkCurr: Sampling result of current during brake condition (A). + * @retval None. + */ +void BRAKE_Exec(BRAKE_Handle *brake, float brkCurr) +{ + MCS_ASSERT_PARAM(brake != NULL); + MCS_ASSERT_PARAM(brkCurr > 0.0f); + float dutyMax = 1.0f; + float curr = Abs(brkCurr); + float maxCurr = brake->brkParam->maxBrkCurr; + float sampleShiftDuty = brake->sampleShiftDuty; + unsigned int tickNum = brake->tickNum; + + if (brake->brkFlg == BRAKE_FINISHED) { + return; + } + + /* Collect statistics on the total braking duration */ + brake->tickCnt++; + if (brake->tickCnt >= tickNum) { + /* Time to push out the brakes */ + brake->brkFlg = BRAKE_FINISHED; + } + + if (curr < (maxCurr * brake->brkParam->fastBrkCurrCoeff)) { + brake->brkDuty += brake->brkParam->maxBrkDutyStep; + } else if (curr < maxCurr) { + brake->brkDuty += brake->brkParam->minBrkDutyStep; + } else { + brake->brkDuty -= brake->brkParam->maxBrkDutyStep; + } + + /* Reserved sampling window */ + brake->brkDuty = Clamp(brake->brkDuty, dutyMax - 2.0f * sampleShiftDuty, 0.0f); + if (curr <= (maxCurr * brake->brkParam->openLoopBrkCurrCoeff) && + brake->brkDuty >= dutyMax - 3.0f * sampleShiftDuty) { + /* Because the duty cycle is too large to collect the current, the brake open loop control */ + brake->brkDuty += brake->brkParam->openLoopBrkDutyStep; + brake->brkDuty = Clamp(brake->brkDuty, dutyMax, 0.0f); + } +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/brake/mcs_brake.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/brake/mcs_brake.h new file mode 100644 index 00000000..26a867ae --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/brake/mcs_brake.h @@ -0,0 +1,61 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_brake.c + * @author MCU Algorithm Team + * @brief This file provides functions of brake module. + */ + +#ifndef McuMagicTag_MCS_BRAKE_H +#define McuMagicTag_MCS_BRAKE_H + +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief Brake Struct. + */ +typedef struct { + float ts; /**< control period (s). */ + float brkTime; /**< brake time (s). */ + float sampleWinTime; /**< sample shift. */ + float maxBrkCurr; /**< maximum brake current (A). */ + float minBrkDutyStep; /**< small brake duty step, recommend value: 0.001f. */ + float maxBrkDutyStep; /**< large brake duty step, recommend value: 0.005f. */ + float fastBrkCurrCoeff; /**< current threshold coefficient for fast braking, recommend value: 0.5f. */ + float openLoopBrkDutyStep; /**< open-loop brake duty step, recommend value: 0.0001f. */ + float openLoopBrkCurrCoeff; /**< current threshold coefficient for open-loop braking, recommend value: 0.2f. */ +} BRAKE_Param; + + +typedef struct { + float brkDuty; /**< pwm duty ratio of lower switch during brake condition (0~1). */ + float sampleShiftDuty; /**< phase shift duty of sample point for brake current (0~1). */ + unsigned int tickCnt; /**< counter for calculating brake time. */ + unsigned int tickNum; /**< count number corresponding to brake time. */ + unsigned char brkFlg; /**< brake status. */ + BRAKE_Param *brkParam; +} BRAKE_Handle; + +typedef enum { + BRAKE_WAIT = 0, + BRAKE_FINISHED +} BRAKE_Status; + +void BRAKE_Init(BRAKE_Handle *brake, BRAKE_Param *brkParam); +void BRAKE_Clear(BRAKE_Handle *brake); +void BRAKE_Exec(BRAKE_Handle *brake, float brkCurr); + +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/filter/mcs_filter.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/filter/mcs_filter.c new file mode 100644 index 00000000..1aadd97a --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/filter/mcs_filter.c @@ -0,0 +1,94 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_filter.c + * @author MCU Algorithm Team + * @brief This file provides functions of first-order filter. + */ + +#include "mcs_filter.h" +#include "mcs_math_const.h" +#include "mcs_assert.h" + +/** + * @brief Initialzer of first-order low-pass filter handle. + * @param lpfHandle First-order filter handle. + * @param ts Control period (s). + * @param fc Cut-off frequency (Hz). + * @retval None. + */ +void FOLPF_Init(FOFLT_Handle *lpfHandle, float ts, float fc) +{ + MCS_ASSERT_PARAM(lpfHandle != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + MCS_ASSERT_PARAM(fc > 0.0f); + lpfHandle->ts = ts; + lpfHandle->fc = fc; + + FOLPF_Clear(lpfHandle); + + /* y(k) = (1/(1+wcTs)) * y(k-1) + (wcTs/(1+wcTs)) * u(k) */ + float wcTs = DOUBLE_PI * fc * ts; + lpfHandle->a1 = 1.0f / (1.0f + wcTs); /* wcTs > 0 */ + lpfHandle->b1 = 1.0f - lpfHandle->a1; +} + +/** + * @brief Clear historical values of first-order filter handle. + * @param FOFLT_Handle First-order filter handle. + * @retval None. + */ +void FOLPF_Clear(FOFLT_Handle *lpfHandle) +{ + MCS_ASSERT_PARAM(lpfHandle != NULL); + lpfHandle->uLast = 0.0f; + lpfHandle->yLast = 0.0f; +} + +/**lpfBkwd + * @brief Calculation method of first-order filter. + * @param lpfHandle First-order filter handle. + * @param u The signal that wants to be filtered. + * @retval The signal that is filtered. + */ +float FOLPF_Exec(FOFLT_Handle *lpfHandle, float u) +{ + MCS_ASSERT_PARAM(lpfHandle != NULL); + float out; + /* Transfer Func: G(s) = kw/(s+w), k = 1. */ + /* y(k) = (1/(1+wcTs)) * y(k-1) + (wcTs/(1+wcTs)) * u(k) */ + out = lpfHandle->a1 * lpfHandle->yLast + lpfHandle->b1 * u; + lpfHandle->yLast = out; + return out; +} + +/** + * @brief Set ts of first-order filter. + * @param lpfHandle First-order filter handle. + * @param ts Control period (s). + * @retval None. + */ +void FOLPF_SetTs(FOFLT_Handle *lpfHandle, float ts) +{ + MCS_ASSERT_PARAM(lpfHandle != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + lpfHandle->ts = ts; + + float wcTs = DOUBLE_PI * lpfHandle->fc * ts; + lpfHandle->a1 = 1.0f / (1.0f + wcTs); /* wcTs > 0 */ + lpfHandle->b1 = 1.0f - lpfHandle->a1; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/filter/mcs_filter.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/filter/mcs_filter.h new file mode 100644 index 00000000..7fee90fc --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/filter/mcs_filter.h @@ -0,0 +1,61 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_filter.h + * @author MCU Algorithm Team + * @brief filter library. + * This file provides functions declaration of the filter module. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_FILTER_H +#define McuMagicTag_MCS_FILTER_H + +/* Typedef definitions ------------------------------------------------------------------------- */ + +/** + * @brief 1st-order Filter struct members and parameters. + * LPF(low-pass filter): y(k)=a1*y(k-1)+b1*u(k) + * HPF(high-pass filter): y(k)=a1*y(k-1)+b1*u(k)+b2*u(k-1) + */ +typedef struct { + float yLast; /**< Last output of 1st-order filter. */ + float uLast; /**< Last input variable. */ + float fc; /**< 1st-order filter cut-off frequency (Hz). */ + float ts; /**< 1st-order filter running period. */ + float a1; /**< Coefficient of 1st-order filter. */ + float b1; /**< Coefficient of 1st-order filter. */ + float b2; /**< Coefficient of 1st-order filter. */ +} FOFLT_Handle; + + +/** + * @defgroup FILTER_API FILTER API + * @brief Filter function API declaration. + * Transfer Func: G(s) = kw/(s+w), k = 1. + */ +void FOLPF_Init(FOFLT_Handle *lpfHandle, float ts, float fc); +void FOLPF_Clear(FOFLT_Handle *lpfHandle); +float FOLPF_Exec(FOFLT_Handle *lpfHandle, float u); +void FOLPF_SetTs(FOFLT_Handle *lpfHandle, float ts); + + +/** + * @} + */ + +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/filter/mcs_lpfRk4.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/filter/mcs_lpfRk4.c new file mode 100644 index 00000000..47f495aa --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/filter/mcs_lpfRk4.c @@ -0,0 +1,82 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_LpfRk4.c + * @author MCU Algorithm Team + * @brief This file provides function of 4-order low-pass filter. + */ + +#include "mcs_lpfRk4.h" +#include "mcs_math_const.h" +#include "mcs_assert.h" +#include "mcs_math.h" + +#define RK4_GAIN (0.5f) +#define RK4_COEFF (0.1666667f) +#define LARGE_NUM (100000000.0f) +#define SMALL_NUM (-100000000.0f) + +/** + * @brief Clear historical values of 4-order low-pass filter handle. + * @param LPF_RK4_Handle 4-order low-pass filter handle. + * @retval None. + */ +void LPFRK4_Clear(LPF_RK4_Handle *lpf) +{ + MCS_ASSERT_PARAM(lpf != NULL); + lpf->y1 = 0.0f; +} + +/** + * @brief Calculation method of 4-order low-pass filter. + * @param LPF_RK4_Handle filter handle. + * @param u The signal that wants to be filtered. + * @param freq Cut-off frequency (Hz). + * @param ts Control period (s). + * @retval The signal that is filered. + */ +float LPFRK4_Exec(LPF_RK4_Handle *lpf, float u, float freq, float ts) +{ + MCS_ASSERT_PARAM(lpf != NULL); + MCS_ASSERT_PARAM(freq > 0.0f); + MCS_ASSERT_PARAM(ts > 0.0f); + float wc = freq * DOUBLE_PI; + float y1 = lpf->y1; + float k1, k2, k3, k4, temp; + + /* Calculate K1. */ + float diff = wc * (u - y1); + k1 = diff * ts; + temp = y1 + k1 * RK4_GAIN; + /* Calculate K2. */ + diff = wc * (u - temp); + k2 = diff * ts; + temp = y1 + k2 * RK4_GAIN; + /* Calculate K3. */ + diff = wc * (u - temp); + k3 = diff * ts; + temp = y1 + k3; + /* Calculate K4. */ + diff = wc * (u - temp); + k4 = diff * ts; + /* Calculate the final result. */ + y1 += (k1 + 2.0f * k2 + 2.0f * k3 + k4) * RK4_COEFF; + y1 = Clamp(y1, LARGE_NUM, SMALL_NUM); + lpf->y1 = y1; + + return y1; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/filter/mcs_lpfRk4.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/filter/mcs_lpfRk4.h new file mode 100644 index 00000000..3cf8b2a7 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/filter/mcs_lpfRk4.h @@ -0,0 +1,39 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_LpfRk4.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of 4-order low-pass filter. + */ +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_LPFRK4_H +#define McuMagicTag_MCS_LPFRK4_H + + +/** + * @brief First Order Low-pass-filter by RK4. + */ +typedef struct { + float y1; +} LPF_RK4_Handle; + + +void LPFRK4_Clear(LPF_RK4_Handle *lpf); + +float LPFRK4_Exec(LPF_RK4_Handle *lpf, float u, float freq, float ts); + +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/filter/mcs_pll.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/filter/mcs_pll.c new file mode 100644 index 00000000..8eba6cca --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/filter/mcs_pll.c @@ -0,0 +1,142 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_pll.c + * @author MCU Algorithm Team + * @brief This file provides function of phase-locked loop (PLL) module. + */ + +#include "mcs_pll.h" +#include "mcs_math.h" +#include "mcs_math_const.h" +#include "mcs_assert.h" + +/** + * @brief Initialzer of Pll struct handle. + * @param pllHandle pll struct handle. + * @param ts control period (s). + * @param bdw bandwidth (Hz). + * @retval None. + */ +void PLL_Init(PLL_Handle *pllHandle, float ts, float bdw) +{ + MCS_ASSERT_PARAM(pllHandle != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + MCS_ASSERT_PARAM(bdw > 0.0f); + /* Reset PLL PID. */ + PID_Reset(&pllHandle->pi); + /* Initializing PLL Parameters. */ + pllHandle->ts = ts; + pllHandle->pi.upperLimit = LARGE_FLOAT; /* The upper limit value of the pid comp output. */ + pllHandle->pi.lowerLimit = -pllHandle->pi.upperLimit; + pllHandle->minAmp = 0.1f; /* Minimum value of the input value in case of the divergence of the PLL. */ + pllHandle->freq = 0.0f; + pllHandle->angle = 0.0f; + pllHandle->ratio = DOUBLE_PI * ts; + pllHandle->pllBdw = bdw; + pllHandle->pi.ts = pllHandle->ts; + PLL_ParamUpdate(pllHandle, pllHandle->pllBdw); +} + +/** + * @brief Updating PLL PI Parameters. + * @param pllHandle pll struct handle. + * @param bdw bandwidth (Hz). + * @retval None. + */ +void PLL_ParamUpdate(PLL_Handle *pllHandle, float bdw) +{ + MCS_ASSERT_PARAM(pllHandle != NULL); + MCS_ASSERT_PARAM(bdw > 0.0f); + float we = bdw * DOUBLE_PI; /* PLL bandwidth (unit: Hz) */ + pllHandle->pi.kp = 2.0f * we; /* 2.0f * we */ + pllHandle->pi.ki = we * we; +} + +/** + * @brief Reset the PLL handle, fill all parameters with zero. + * @param pllHandle PLL struct handle. + * @retval None. + */ +void PLL_Reset(PLL_Handle *pllHandle) +{ + MCS_ASSERT_PARAM(pllHandle != NULL); + /* Reset PLL PID parameters */ + PID_Reset(&(pllHandle->pi)); + pllHandle->minAmp = 0.0f; + pllHandle->ts = 0.0f; + pllHandle->ratio = 0.0f; + pllHandle->freq = 0.0f; + pllHandle->angle = 0; +} + +/** + * @brief Clear historical values of PLL controller. + * @param pllHandle PLL struct handle. + * @retval None. + */ +void PLL_Clear(PLL_Handle *pllHandle) +{ + MCS_ASSERT_PARAM(pllHandle != NULL); + PID_Clear(&pllHandle->pi); +} + +/** + * @brief Calculation method of PLL controller. + * @param pllHandle PLL struct handle. + * @param sinVal Input sin value. + * @param cosVal Input cos value. + * @retval None. + */ +void PLL_Exec(PLL_Handle *pllHandle, float sinVal, float cosVal) +{ + MCS_ASSERT_PARAM(pllHandle != NULL); + + float amplitude = Sqrt(sinVal * sinVal + cosVal * cosVal); + amplitude = (amplitude < pllHandle->minAmp) ? pllHandle->minAmp : amplitude; /* amplitude > minAmp > 0 */ + + TrigVal localTrigVal; + pllHandle->angle += pllHandle->freq * pllHandle->ratio; + pllHandle->angle = Mod(pllHandle->angle, DOUBLE_PI); + if (pllHandle->angle > ONE_PI) { + pllHandle->angle -= DOUBLE_PI; + } + if (pllHandle->angle < -ONE_PI) { + pllHandle->angle += DOUBLE_PI; + } + TrigCalc(&localTrigVal, pllHandle->angle); + + float err = sinVal * localTrigVal.cos - cosVal * localTrigVal.sin; + pllHandle->pi.error = err / amplitude; /* amplitude != 0 */ + pllHandle->freq = PI_Exec(&pllHandle->pi); +} + +/** + * @brief Set ts of PLL controller. + * @param pllHandle PLL struct handle. + * @param ts control period (s). + * @retval None. + */ +void PLL_SetTs(PLL_Handle *pllHandle, float ts) +{ + MCS_ASSERT_PARAM(pllHandle != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + /* It is need to modify the pid sample time, pll ratio when set PLL ts. */ + pllHandle->ts = ts; + PID_SetTs(&pllHandle->pi, ts); + pllHandle->ratio = DOUBLE_PI * ts; +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/filter/mcs_pll.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/filter/mcs_pll.h new file mode 100644 index 00000000..7a0228b8 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/filter/mcs_pll.h @@ -0,0 +1,72 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_pll.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of Phase-locked loop (PLL) module. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_PLL_H +#define McuMagicTag_MCS_PLL_H + +/* Includes ------------------------------------------------------------------------------------ */ +#include "mcs_pid_ctrl.h" + +/** + * @defgroup PLL_MODULE PLL MODULE + * @brief The PLL module. + * @{ + */ + +/** + * @defgroup PLL_STRUCT PLL STRUCT + * @brief The PLL module data structure. + * @{ + */ +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief PLL struct. + */ +typedef struct { + PID_Handle pi; /**< PI controller for the PLL. */ + float minAmp; /**< Minimum value of the input value in case of the divergence of the PLL. */ + float ts; /**< Control period of the PLL. */ + float ratio; /**< Conversion factor, ts * 65535 / TWO_PI. */ + float freq; /**< Output estimated frequency (Hz). */ + float angle; /**< Output estimated phasse angle. */ + float pllBdw; /**< pll bandWidth. */ +} PLL_Handle; + + +/** + * @defgroup PLL_API PLL API + * @brief The PLL module API definitions. + */ +void PLL_Init(PLL_Handle *pllHandle, float ts, float bdw); + +void PLL_Reset(PLL_Handle *pllHandle); + +void PLL_Clear(PLL_Handle *pllHandle); + +void PLL_Exec(PLL_Handle *pllHandle, float sinVal, float cosVal); + +void PLL_SetTs(PLL_Handle *pllHandle, float ts); + +void PLL_ParamUpdate(PLL_Handle *pllHandle, float bdw); + +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_curr_ctrl.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_curr_ctrl.c new file mode 100644 index 00000000..17ecb6ee --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_curr_ctrl.c @@ -0,0 +1,148 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_curr_ctrl.c + * @author MCU Algorithm Team + * @brief This file provides function of motor current control. + */ + +#include "typedefs.h" +#include "mcs_curr_ctrl.h" +#include "mcs_math_const.h" +#include "mcs_assert.h" +#include "mcs_curr_ff.h" + + +/** + * @brief Initialzer of Current controller. + * @param currHandle Current control handle. + * @param pidTable Motor control handle. + * @param mtrParam Motor parameters. + * @param idqRef idqRef. + * @param idqFbk idqFbk. + * @param busVolt Bus voltage. + * @param ts control period. + * @retval None. + */ +void CURRCTRL_Init(CURRCTRL_Handle *currHandle, MOTOR_Param *mtrParam, DqAxis *idqRef, DqAxis *idqFbk, + const PI_Param dAxisPi, const PI_Param qAxisPi, float ts) +{ + MCS_ASSERT_PARAM(currHandle != NULL); + MCS_ASSERT_PARAM(mtrParam != NULL); + MCS_ASSERT_PARAM(idqRef != NULL); + MCS_ASSERT_PARAM(idqFbk != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + /* Clear the control parameter. */ + CURRCTRL_Reset(currHandle); + /* Current Pointer. */ + currHandle->idqRef = idqRef; + currHandle->idqFbk = idqFbk; + currHandle->mtrParam = mtrParam; + /* The feedforward value is set to 0 by default. */ + currHandle->idqFf.d = 0.0f; + currHandle->idqFf.q = 0.0f; + + /* Parameter initialization. */ + currHandle->ts = ts; + currHandle->dAxisPi.ts = ts; + currHandle->qAxisPi.ts = ts; + + currHandle->dAxisPi.kp = dAxisPi.kp; + currHandle->dAxisPi.ki = dAxisPi.ki; + currHandle->qAxisPi.kp = qAxisPi.kp; + currHandle->qAxisPi.ki = qAxisPi.ki; + /* output voltage limit. */ + currHandle->outLimit = qAxisPi.upperLim; + currHandle->dAxisPi.upperLimit = dAxisPi.upperLim; + currHandle->dAxisPi.lowerLimit = dAxisPi.lowerLim; + currHandle->qAxisPi.upperLimit = qAxisPi.upperLim; + currHandle->qAxisPi.lowerLimit = qAxisPi.lowerLim; +} + +/** + * @brief Reset the current control handle, fill with zero, NULL. + * @param currHandle The current control handle. + * @retval None. + */ +void CURRCTRL_Reset(CURRCTRL_Handle *currHandle) +{ + MCS_ASSERT_PARAM(currHandle != NULL); + /* Reset the current control handle, fill with zero, NULL. */ + currHandle->idqRef = NULL; + currHandle->idqFbk = NULL; + currHandle->idqFf.d = 0.0f; + currHandle->idqFf.q = 0.0f; + currHandle->mtrParam = NULL; + currHandle->outLimit = 0.0f; + currHandle->ts = 0.0f; + /* Reset Dq axis PID current control */ + PID_Reset(&currHandle->dAxisPi); + PID_Reset(&currHandle->qAxisPi); +} + +/** + * @brief Clear historical values of current controller. + * @param currHandle Current controller struct handle. + * @retval None. + */ +void CURRCTRL_Clear(CURRCTRL_Handle *currHandle) +{ + MCS_ASSERT_PARAM(currHandle != NULL); + PID_Clear(&currHandle->dAxisPi); + PID_Clear(&currHandle->qAxisPi); +} + + +/** + * @brief Simplified current controller PI calculation. + * @param currHandle Current controller struct handle. + * @param voltRef Dq-axis voltage reference which is the output of current controller. + * @param spd speed (Hz). + * @param ffEnable Feedforward compensation enable. + * @retval None. + */ +void CURRCTRL_Exec(CURRCTRL_Handle *currHandle, DqAxis *vdqRef, float spd, int ffEnable) +{ + MCS_ASSERT_PARAM(currHandle != NULL); + MCS_ASSERT_PARAM(vdqRef != NULL); + DqAxis vdqFf; + + /* Calculate the current error of the dq axis. */ + currHandle->dAxisPi.error = currHandle->idqRef->d - currHandle->idqFbk->d; + currHandle->qAxisPi.error = currHandle->idqRef->q - currHandle->idqFbk->q; + CURRFF_Exec(&vdqFf, *currHandle->idqFbk, currHandle->mtrParam, spd, ffEnable); + currHandle->dAxisPi.feedforward = vdqFf.d; + currHandle->qAxisPi.feedforward = vdqFf.q; + /* Calculation of the PI of the Dq axis current. */ + vdqRef->d = PI_Exec(&currHandle->dAxisPi); + vdqRef->q = PI_Exec(&currHandle->qAxisPi); +} + +/** + * @brief Set ts of current controller. + * @param currHandle Current controller struct handle. + * @retval None. + */ +void CURRCTRL_SetTs(CURRCTRL_Handle *currHandle, float ts) +{ + MCS_ASSERT_PARAM(currHandle != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + currHandle->ts = ts; + /* Set d and q axes pid sample time. */ + PID_SetTs(&currHandle->dAxisPi, ts); + PID_SetTs(&currHandle->qAxisPi, ts); +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_curr_ctrl.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_curr_ctrl.h new file mode 100644 index 00000000..0fe6b555 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_curr_ctrl.h @@ -0,0 +1,87 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_curr_ctrl.h + * @author MCU Algorithm Team + * @brief Current controller for motor control. + * This file provides functions declaration of the current controller module. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_CURR_CTRL_H +#define McuMagicTag_MCS_CURR_CTRL_H + +/* Includes ------------------------------------------------------------------------------------ */ +#include "mcs_typedef.h" +#include "mcs_pid_ctrl.h" +#include "mcs_mtr_param.h" + +/** + * @defgroup CURRENT_CONTROLLER CURRENT CONTROLLER MODULE + * @brief The current controller function. + * @{ + */ + +/** + * @defgroup CURRENT_CONTROLLER_STRUCT CURRENT CONTROLLER STRUCT + * @brief The current controller's data structure definition. + * @{ + */ + +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief Current controller struct members and parameters. + */ +typedef struct { + DqAxis *idqRef; /**< Current reference in the d-q coordinate (A). */ + DqAxis *idqFbk; /**< Current feedback in the d-q coordinate (A). */ + DqAxis idqFf; /**< Current feedforward value (V). */ + PID_Handle dAxisPi; /**< d-axis current PI controller. */ + PID_Handle qAxisPi; /**< q-axis current PI controller. */ + MOTOR_Param *mtrParam; /**< Motor parameters. */ + float outLimit; /**< Current controller output voltage limitation (V). */ + float ts; /**< Current controller control period (s). */ +} CURRCTRL_Handle; +/** + * @} + */ + +/** + * @defgroup CURRENT_CONTROLLER_API CURRENT CONTROLLER API + * @brief The current controller's API declaration. + * @{ + */ +void CURRCTRL_Init(CURRCTRL_Handle *currHandle, MOTOR_Param *mtrParam, DqAxis *idqRef, DqAxis *idqFbk, + const PI_Param dAxisPi, const PI_Param qAxisPi, float ts); + +void CURRCTRL_Reset(CURRCTRL_Handle *currHandle); + +void CURRCTRL_Clear(CURRCTRL_Handle *currHandle); + +void CURRCTRL_Exec(CURRCTRL_Handle *currHandle, DqAxis *vdqRef, float spd, int ffEnable); + +void CURRCTRL_SetTs(CURRCTRL_Handle *currHandle, float ts); + +/** + * @} + */ + +/** + * @} + */ + +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_curr_ff.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_curr_ff.c new file mode 100644 index 00000000..84ae2854 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_curr_ff.c @@ -0,0 +1,50 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_curr_ff.c + * @author MCU Algorithm Team + * @brief This file provides current loop feedforward compensation declaration for motor control. + */ + +#include "mcs_curr_ff.h" +#include "mcs_math_const.h" +#include "mcs_assert.h" + +/** + * @brief Current loop feedforward compensation execution function. + * @param vdqFf DQ axis volt feedforward compensation value. + * @param idqFbk DQ axis feedback current value. + * @param param Motor parameters. + * @param spd Speed (Hz). + * @param enable Whether to enable feedforward compensation. + * @retval None. + */ +void CURRFF_Exec(DqAxis *vdqFf, DqAxis idqFbk, MOTOR_Param *param, float spd, int enable) +{ + MCS_ASSERT_PARAM(vdqFf != NULL); + MCS_ASSERT_PARAM(param != NULL); + /* The unit is converted from Hz to rad. */ + float we = spd * DOUBLE_PI; + if (enable) { + /* Calculate the feedforward compensation value. */ + vdqFf->d = -param->mtrLq * we * idqFbk.q; + vdqFf->q = we * (param->mtrLd * idqFbk.d + param->mtrPsif); + } else { + vdqFf->d = 0.0f; + vdqFf->q = 0.0f; + } +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_curr_ff.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_curr_ff.h new file mode 100644 index 00000000..ba15e15b --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_curr_ff.h @@ -0,0 +1,31 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_curr_ff.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of current loop feedforward compensation. + */ + +#ifndef McuMagicTag_MCS_CURR_FF_H +#define McuMagicTag_MCS_CURR_FF_H + +#include "mcs_typedef.h" +#include "mcs_mtr_param.h" + +void CURRFF_Exec(DqAxis *vdqRef, DqAxis idqFbk, MOTOR_Param *param, float spd, int enable); + +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_fw_ctrl.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_fw_ctrl.c new file mode 100644 index 00000000..3100ef65 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_fw_ctrl.c @@ -0,0 +1,130 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_fw_ctrl.c + * @author MCU Algorithm Team + * @brief This file provides Flux-Weakening control for motor control. + */ +#include "mcs_fw_ctrl.h" +#include "mcs_math.h" +#include "mcs_math_const.h" +#include "mcs_assert.h" + +/** + * @brief Clear historical values of Flux-Weakening handle. + * @param fw Flux-Weakening struct handle. + * @retval None. + */ +static void FW_Clear(FW_Handle *fw) +{ + MCS_ASSERT_PARAM(fw != NULL); + fw->idRef = 0.0f; +} + +/** + * @brief Flux-Weakening control Handle Initialization. + * @param fw Flux-Weakening struct handle. + * @param ts Control period (s). + * @param enable Enable flux-weakening. + * @param currMax Maximum phase current (A). + * @param idDemag Demagnetizing d-axis current (A). + * @param thr . + * @retval None. + */ +void FW_Init(FW_Handle *fw, float ts, bool enable, float currMax, float idDemag, float thr, float slope) +{ + MCS_ASSERT_PARAM(fw != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + /* Indicates whether to enable the Flux-Weakening field function. */ + fw->enable = enable; + fw->ts = ts; + fw->udcThreshPer = thr * ONE_DIV_SQRT3; + /* id control slope */ + fw->idSlope = slope; + fw->idMaxAmp = (currMax < idDemag) ? currMax : idDemag; + fw->currMaxSquare = currMax * currMax; + FW_Clear(fw); +} + +/** + * @brief Flux-Weakening calculation execution function. + * @param fw Flux-Weakening struct handle. + * @param udqRef dq axis voltage reference. + * @param udc bus voltage. + * @param idqRefRaw Command value of the d and q axis current. + * @retval None. + */ +void FW_Exec(FW_Handle *fw, DqAxis udqRef, float udc, DqAxis *idqRefRaw) +{ + MCS_ASSERT_PARAM(fw != NULL); + MCS_ASSERT_PARAM(udc > 0.0f); + MCS_ASSERT_PARAM(idqRefRaw != NULL); + float udcLimit = udc * fw->udcThreshPer; + float voltRefAmp = Sqrt(udqRef.d * udqRef.d + udqRef.q * udqRef.q); + float voltErr = udcLimit - voltRefAmp; + float idRefRaw = idqRefRaw->d; + float iqRefRaw = idqRefRaw->q; + float iqRef; + float dir = (idqRefRaw->q > 0.0f) ? 1.0f : -1.0f; + + /* Check whether the Flux-Weakening field function is enabled. */ + if (!fw->enable) { + fw->idRef = idRefRaw; + /* if fw is disabled, just return without any change. */ + return; + } + float idStep = fw->idSlope * fw->ts; + /* Adjust the injection d-axis current based on the output voltage error. */ + /* When voltage error is positive, adjust id to idRefRaw, no need to fw. */ + if (voltErr >= 0.0f) { + fw->idRef += idStep; + if (fw->idRef > idRefRaw) { + fw->idRef = idRefRaw; + } + } else { + /* When voltage error is negative. Add negtive id to the motor, need to fw. */ + fw->idRef -= idStep; + if (fw->idRef < -fw->idMaxAmp) { + fw->idRef = -fw->idMaxAmp; + } + } + + /* Limit q-axis current output. */ + float idRefSquare = fw->idRef * fw->idRef; + if (idRefSquare + iqRefRaw * iqRefRaw > fw->currMaxSquare) { + iqRef = dir * Sqrt(fw->currMaxSquare - idRefSquare); + } else { + iqRef = iqRefRaw; + } + + idqRefRaw->d = fw->idRef; + idqRefRaw->q = iqRef; + + return; +} + +/** + * @brief Set ts of Flux-Weakening. + * @param fw Flux-Weakening struct handle. + * @param ts Control period (s). + * @retval None. + */ +void FW_SetTs(FW_Handle *fw, float ts) +{ + MCS_ASSERT_PARAM(fw != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + fw->ts = ts; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_fw_ctrl.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_fw_ctrl.h new file mode 100644 index 00000000..78ca1185 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_fw_ctrl.h @@ -0,0 +1,45 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_fw_ctrl.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of Flux-Weakening control. + */ +#ifndef McuMagicTag_MCS_FW_CTRL_H +#define McuMagicTag_MCS_FW_CTRL_H + +#include "typedefs.h" +#include "mcs_typedef.h" + +typedef struct { + bool enable; + float udcThreshPer; + float ts; + float idSlope; + float idRef; /* reference instruction value. */ + float idMaxAmp; /* Maximum id ingested */ + + float currMax; /* maximum phase current (A) */ + float currMaxSquare; /* square of maximum current. */ + float idDemag; /* demagnetizing d-axis current (A) */ +} FW_Handle; + +void FW_Init(FW_Handle *fw, float ts, bool enable, float currMax, float idDemag, float thr, float slope); + +void FW_Exec(FW_Handle *fw, DqAxis udqRef, float udc, DqAxis *idqRefRaw); + +void FW_SetTs(FW_Handle *fw, float ts); +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_if_ctrl.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_if_ctrl.c new file mode 100644 index 00000000..7db97eb0 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_if_ctrl.c @@ -0,0 +1,115 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_if_ctrl.c + * @author MCU Algorithm Team + * @brief This file provides function of I/F control. + */ + +#include "mcs_if_ctrl.h" +#include "mcs_assert.h" +#include "mcs_math_const.h" + +/** + * @brief Initialzer of I/F control struct handle. + * @param ifHandle I/F handle. + * @param targetAmp Target value of the I/F current (A). + * @param currSlope Current slope. + * @param stepAmpPeriod Step control period, using systick---spd_loop_ctrl_period (s). + * @param anglePeriod Calculation period of the I/F angle---curr_loop_ctrl_period (s). + * @retval None. + */ +void IF_Init(IF_Handle *ifHandle, float targetAmp, float currSlope, float stepAmpPeriod, float anglePeriod) +{ + MCS_ASSERT_PARAM(ifHandle != NULL); + MCS_ASSERT_PARAM(targetAmp > 0.0f); + MCS_ASSERT_PARAM(currSlope > 0.0f); + MCS_ASSERT_PARAM(anglePeriod > 0.0f); + MCS_ASSERT_PARAM(stepAmpPeriod > 0.0f); + /* Initialize IF parameters. */ + ifHandle->targetAmp = targetAmp; + ifHandle->stepAmp = currSlope * stepAmpPeriod; /* current step increment */ + ifHandle->curAmp = 0.0f; + /* Angle period. */ + ifHandle->anglePeriod = anglePeriod; + ifHandle->angle = 0.0f; +} + +/** + * @brief Clear historical values of first-order filter handle. + * @param ifHandle I/F control handle. + * @retval None. + */ +void IF_Clear(IF_Handle *ifHandle) +{ + MCS_ASSERT_PARAM(ifHandle != NULL); + ifHandle->curAmp = 0.0f; + ifHandle->angle = 0; +} + +/** + * @brief I/F current amplitude calculation. + * @param ifHandle I/F control handle. + * @retval I/F current amplitude (A). + */ +float IF_CurrAmpCalc(IF_Handle *ifHandle) +{ + MCS_ASSERT_PARAM(ifHandle != NULL); + /* Calculation of IF Current Amplitude */ + if (ifHandle->curAmp < ifHandle->targetAmp) { + ifHandle->curAmp += ifHandle->stepAmp; + } else { + ifHandle->curAmp = ifHandle->targetAmp; + } + + return ifHandle->curAmp; +} + +/** + * @brief I/F current angle calculation. + * @param ifHandle I/F control handle. + * @param spdRef Frequency of current vector. + * @retval I/F output angle. + */ +float IF_CurrAngleCalc(IF_Handle *ifHandle, float spdRef) +{ + MCS_ASSERT_PARAM(ifHandle != NULL); + /* Calculate IF angle. */ + ifHandle->angle += spdRef * DOUBLE_PI * ifHandle->anglePeriod; + /* Limit the angle: [-pi, pi]. */ + if (ifHandle->angle > ONE_PI) { + ifHandle->angle -= DOUBLE_PI; + } + if (ifHandle->angle < -ONE_PI) { + ifHandle->angle += DOUBLE_PI; + } + + return ifHandle->angle; +} + +/** + * @brief Set ts of I/F. + * @param ifHandle I/F control handle. + * @param ts Control period (s). + * @retval None. + */ +void IF_SetAngleTs(IF_Handle *ifHandle, float ts) +{ + MCS_ASSERT_PARAM(ifHandle != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + ifHandle->anglePeriod = ts; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_if_ctrl.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_if_ctrl.h new file mode 100644 index 00000000..cd32b5c7 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_if_ctrl.h @@ -0,0 +1,76 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_if_ctrl.h + * @author MCU Algorithm Team + * @brief Current controller for motor I/F control. + * This file provides functions declaration of I/F control. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_IF_CTRL_H +#define McuMagicTag_MCS_IF_CTRL_H + +/** + * @defgroup IF_MODULE I/F MODULE + * @brief The I/F motor control method module. + * @{ + */ + +/** + * @defgroup IF_STRUCT I/F STRUCT + * @brief The I/F motor control method data struct definition. + * @{ + */ +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief General IF controller struct members and parameters. + */ +typedef struct { + float anglePeriod; /**< Calculation period of the I/F angle (s). */ + float curAmpPeriod; /**< Calculation period of the I/F current amplitude (s). */ + + float targetAmp; /**< Target value of the I/F current (A). */ + float curAmp; /**< Current value of the I/F current (A). */ + float stepAmp; /**< Increment of the I/F current (A). */ + float angle; /**< I/F output angle. */ +} IF_Handle; + +/** + * @defgroup IF_API I/F API + * @brief The I/F motor control method API declaration. + * @{ + */ +void IF_Init(IF_Handle *ifHandle, float targetAmp, float currSlope, float stepAmpPeriod, float anglePeriod); + +void IF_Clear(IF_Handle *ifHandle); + +float IF_CurrAmpCalc(IF_Handle *ifHandle); + +float IF_CurrAngleCalc(IF_Handle *ifHandle, float spdRef); + +void IF_SetAngleTs(IF_Handle *ifHandle, float ts); + +/** + * @} + */ + +/** + * @} + */ + +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_pos_ctrl.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_pos_ctrl.c new file mode 100644 index 00000000..1e892263 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_pos_ctrl.c @@ -0,0 +1,218 @@ +/** + * Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_posctrl.c + * @author MCU Algorithm Team + * @brief This file provides function of motor position control. + */ + +#include "typedefs.h" +#include "mcs_math_const.h" +#include "mcs_math.h" +#include "mcs_pos_ctrl.h" + +/** + * @brief Reset the position controller, fill with zero, NULL. + * @param posHandle position controller struct handle. + * @retval None. + */ +void POSCTRL_Clear(POSCTRL_Handle *posHandle) +{ + /* PID controller history values clear */ + posHandle->posPi.error = 0.0f; + posHandle->posPi.feedforward = 0.0f; + posHandle->posPi.differ = 0.0f; + posHandle->posPi.integral = 0.0f; + posHandle->posPi.saturation = 0.0f; + + posHandle->posTarget = 0.0f; + posHandle->posErr = 0.0f; +} + +/** + * @brief Position control initialization function. + * @param posHandle position controller struct handle. + * @param ts Control period. + */ +void POSCTRL_Init(POSCTRL_Handle *posHandle, const PID_Param *piCtrlTable, float ts) +{ + POSCTRL_Clear(posHandle); + posHandle->ts = ts; + + /* position PID controller initialization */ + posHandle->posPi.ts = posHandle->ts; + posHandle->posPi.kp = piCtrlTable->kp; + posHandle->posPi.ki = piCtrlTable->ki; + posHandle->posPi.kd = piCtrlTable->kd; + posHandle->posPi.ns = piCtrlTable->ns; + posHandle->posPi.ka = 1.0f / posHandle->posPi.kp; + posHandle->posPi.upperLimit = piCtrlTable->upperLim; + posHandle->posPi.lowerLimit = piCtrlTable->lowerLim; + + /* continuous mode: ramp controller initialization */ + RMG_Init(&posHandle->posRmg, posHandle->ts, posHandle->posRmg.slope * DOUBLE_PI); + posHandle->posRmg.ts = posHandle->ts; + + /* position feedback history values clear */ + posHandle->angFbkLoop = 0; + posHandle->angFbkPrev = 0.0f; + + /* position control mode configuration */ + posHandle->mode = POSCTRL_MODE_CONTINUOUS; +} + +/** + * @brief Position control mode settings. + * @param posHandle position controller struct handle. + * @param mode control mode. + */ +void POSCTRL_ModeSelect(POSCTRL_Handle *posHandle, POSCTRL_Mode mode) +{ + posHandle->mode = mode; +} + +/** + * @brief Set position change rate. + * @param posHandle Position controller struct handle. + * @param slope position change rate (Hz). + * @retval None. + */ +void POSCTRL_SetSlope(POSCTRL_Handle *posHandle, float slope) +{ + posHandle->posRmg.slope = slope; + posHandle->posRmg.delta = posHandle->posRmg.ts * posHandle->posRmg.slope * DOUBLE_PI; +} + +/** + * @brief Position ring target position setting. + * @param posHandle Position controller struct handle. + * @param posTarget Target location. + */ +void POSCTRL_SetTarget(POSCTRL_Handle *posHandle, float posTarget) +{ + posHandle->posTarget = posTarget; + posHandle->posTargetShadow = posTarget; +} + +/** + * @brief Absolute position calculation. + * @param posHandle Position controller struct handle. + * @param angFbk Angle feedback. + * @return float, Position feedback. + */ +float POSCTRL_AngleExpand(POSCTRL_Handle *posHandle, float angFbk) +{ + float angFbkPrevFloat = posHandle->angFbkPrev; + int loopPrev = posHandle->angFbkLoop; + int loop; + + /* unify feedback angle to ±2*pi */ + angFbk = Mod(angFbk, DOUBLE_PI); + /* unify feedback angle to 0 ~ 2*pi */ + if (angFbk < 0.0f) { + angFbk += DOUBLE_PI; + } + + /* check if angle rotates one cycle */ + if (angFbkPrevFloat > THREE_PI_DIV_TWO && angFbkPrevFloat <= DOUBLE_PI && angFbk < HALF_PI) { + loop = loopPrev + 1; + } else if (angFbk > THREE_PI_DIV_TWO && THREE_PI_DIV_TWO <= DOUBLE_PI && angFbkPrevFloat < HALF_PI) { + loop = loopPrev - 1; + } else { + loop = loopPrev; + } + + /* update prev value */ + posHandle->angFbkLoop = loop; + posHandle->angFbkPrev = angFbk; + + /* update output value */ + posHandle->posFbk = angFbk + loop * DOUBLE_PI; + + return posHandle->posFbk; +} + +/** + * @brief Position ring PID execution function. + * @param posHandle Position controller struct handle. + * @param posErr position error. + * @return float + */ +float POSCTRL_PidExec(POSCTRL_Handle *posHandle, float posErr) +{ + float spdRef; + posHandle->posPi.error = posErr; + spdRef = PID_Exec(&posHandle->posPi); + return spdRef; +} + +/** + * @brief position loop execution function. + * @param posHandle Position controller struct handle. + * @param posFbk Position feedback. + * @return float, Speed reference value. + */ +float POSCTRL_Exec(POSCTRL_Handle *posHandle, float posTarget, float posFbk) +{ + float posRef, spdRef; + posRef = RMG_Exec(&posHandle->posRmg, posTarget); + posHandle->posRef = posRef; + spdRef = POSCTRL_PidExec(posHandle, posRef - posFbk); + spdRef *= ONE_DIV_DOUBLE_PI; /* transfer spdRef from rad/s to Hz */ + posHandle->spdRef = spdRef; + return spdRef; +} + +/** + * @brief Set position loop kp parameter function. + * @param posHandle Position controller struct handle. + * @param kp PID-kp paramter. + */ +void POSCTRL_SetKp(POSCTRL_Handle *posHandle, float kp) +{ + posHandle->posPi.kp = kp; +} + +/** + * @brief Set position loop ki parameter function. + * @param posHandle Position controller struct handle. + * @param ki PID-ki paramter. + */ +void POSCTRL_SetKi(POSCTRL_Handle *posHandle, float ki) +{ + posHandle->posPi.ki = ki; +} + +/** + * @brief Set position loop kd parameter function. + * @param posHandle Position controller struct handle. + * @param kd PID-kd paramter. + */ +void POSCTRL_SetKd(POSCTRL_Handle *posHandle, float kd) +{ + posHandle->posPi.kd = kd; +} + +/** + * @brief Set position loop Ns parameter function. + * @param posHandle Position controller struct handle. + * @param ns ns paramter. + */ +void POSCTRL_SetNs(POSCTRL_Handle *posHandle, float ns) +{ + posHandle->posPi.ns = ns; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_pos_ctrl.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_pos_ctrl.h new file mode 100644 index 00000000..999dd359 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_pos_ctrl.h @@ -0,0 +1,97 @@ +/** + * Copyright (c) 2022, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_pos_ctrl.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of position control . + */ +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_MCS_POS_CTRL_H +#define McuMagicTag_MCS_MCS_POS_CTRL_H + +/* Includes ------------------------------------------------------------------------------------ */ +#include "mcs_typedef.h" +#include "mcs_pid_ctrl.h" +#include "mcs_ramp_mgmt.h" +#include "mcs_mtr_param.h" + + +/* Macro definitions --------------------------------------------------------------------------- */ + +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief Position control mode. + */ +typedef enum { + POSCTRL_MODE_CONTINUOUS = 0, + POSCTRL_MODE_TRAJ +} POSCTRL_Mode; + +/** + * @brief Position controller struct members and parameters. + */ +typedef struct { + PID_Handle posPi; /**< PI controller struct in the position controller. */ + float posTarget; /**< position controller input target value (rad) */ + float posTargetBk; + RMG_Handle posRmg; /**< position reference ramp management . */ + float ts; /**< position controller control period (s). */ + int angFbkLoop; /**< feedback position loop count. */ + float angFbkPrev; /**< feedback position in last cycle (rad). */ + float posFbk; /**< feedback position absolutely (rad). */ + float posIncRef; /**< position controller reference (rad) */ + float posIncRefPrev; /**< position controller reference in last cycle (rad) */ + float spdRef; /**< position controller outpur speed reference (Hz) */ + float posRef; /**< position controller reference (rad) */ + float posFbkPrev; + float posErr; + + /* trajectory planning */ + /* position controller work mode. 0: continuous mode; 1: trajectory control mode. */ + /* trajectory mode can only be enabled when input mode is set absolute position. */ + POSCTRL_Mode mode; + float posTargetShadow; + float runTime; /**< single trajectory control last time time (s). */ + float timeTick; /**< trajectory control inner timer (s) */ + float deltaTime; + float accMax; + float jerk; + int targetUpdateBlockFlag; /**< whether the position target can be update or not. 0: can be updated; 1: block */ + float deltaTimeSq; + float deltaTimeCu; + float timeStg[7]; +} POSCTRL_Handle; + +/** + * @defgroup POSITION_CONTROLLER_API POSITION CONTROLLER API + * @brief The position controller API declaration. + * @retval Speed Reference. + */ +void POSCTRL_Clear(POSCTRL_Handle *posHandle); +void POSCTRL_Init(POSCTRL_Handle *posHandle, const PID_Param *piCtrlTable, float ts); +float POSCTRL_PidExec(POSCTRL_Handle *posHandle, float posErr); +void POSCTRL_ModeSelect(POSCTRL_Handle *posHandle, POSCTRL_Mode mode); +void POSCTRL_SetSlope(POSCTRL_Handle *posHandle, float slope); +void POSCTRL_SetTarget(POSCTRL_Handle *posHandle, float posTarget); +float POSCTRL_Exec(POSCTRL_Handle *posHandle, float posTarget, float posFbk); +float POSCTRL_AngleExpand(POSCTRL_Handle *posHandle, float angFbk); +void POSCTRL_SetKp(POSCTRL_Handle *posHandle, float kp); +void POSCTRL_SetKi(POSCTRL_Handle *posHandle, float ki); +void POSCTRL_SetKd(POSCTRL_Handle *posHandle, float kd); +void POSCTRL_SetNs(POSCTRL_Handle *posHandle, float ns); + +#endif /* McuMagicTag_MCS_POS_CTRL_H */ \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_spd_ctrl.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_spd_ctrl.c new file mode 100644 index 00000000..5f88e833 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_spd_ctrl.c @@ -0,0 +1,96 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_spd_ctrl.c + * @author MCU Algorithm Team + * @brief This file provides function of motor speed control. + */ + +#include "typedefs.h" +#include "mcs_spd_ctrl.h" +#include "mcs_assert.h" + +/** + * @brief Initialzer of speed control struct handle. + * @param spdHandle Speed control struct handle. + * @param PID_Param PI controller parameter table. + * @param ts Speed control period. + * @retval None. + */ +void SPDCTRL_Init(SPDCTRL_Handle *spdHandle, MOTOR_Param *mtrParam, const PI_Param piParam, float ts) +{ + MCS_ASSERT_PARAM(spdHandle != NULL); + MCS_ASSERT_PARAM(mtrParam != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + /* reset speed loop PI */ + PID_Reset(&spdHandle->spdPi); + /* Parameter Initialization. */ + spdHandle->mtrParam = mtrParam; + spdHandle->ts = ts; + spdHandle->spdPi.ts = ts; + spdHandle->spdPi.kp = piParam.kp; + spdHandle->spdPi.ki = piParam.ki; + spdHandle->outLimit = piParam.upperLim; + spdHandle->spdPi.upperLimit = piParam.upperLim; + spdHandle->spdPi.lowerLimit = piParam.lowerLim; +} + + +/** + * @brief Simplified speed controller PI calculation. + * @param spdHandle Speed controller struct handle. + * @param spdTarget The target speed value (Hz). + * @param spdFbk Motor electrical speed (Hz). + * @retval None. + */ +float SPDCTRL_Exec(SPDCTRL_Handle *spdHandle, float spdTarget, float spdFbk) +{ + MCS_ASSERT_PARAM(spdHandle != NULL); + float iqRef; + /* Speed error calculation */ + spdHandle->spdPi.error = spdTarget - spdFbk; + /* speed controller pid calculation */ + iqRef = PI_Exec(&spdHandle->spdPi); + return iqRef; +} + +/** + * @brief Clear historical values of speed controller. + * @param spdHandle Speed controller struct handle. + * @retval None. + */ +void SPDCTRL_Clear(SPDCTRL_Handle *spdHandle) +{ + MCS_ASSERT_PARAM(spdHandle != NULL); + PID_Clear(&spdHandle->spdPi); +} + +/** + * @brief Reset the speed controller, fill with zero, NULL. + * @param spdHandle Speed controller struct handle. + * @retval None. + */ +void SPDCTRL_Reset(SPDCTRL_Handle *spdHandle) +{ + MCS_ASSERT_PARAM(spdHandle != NULL); + /* Reset speed ring PI */ + PID_Reset(&spdHandle->spdPi); + /* Reset the speed controller, fill with zero, NULL. */ + spdHandle->outLimit = 0.0f; + spdHandle->mtrParam = NULL; + spdHandle->ts = 0.0f; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_spd_ctrl.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_spd_ctrl.h new file mode 100644 index 00000000..5767f3a2 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_spd_ctrl.h @@ -0,0 +1,49 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_spd_ctrl.h + * @author MCU Algorithm Team + * @brief Speed controller for motor control. + * This file provides functions declaration of the speed controller module. + */ + +#ifndef McuMagicTag_MCS_SPD_CTRL_H +#define McuMagicTag_MCS_SPD_CTRL_H + +#include "mcs_typedef.h" +#include "mcs_pid_ctrl.h" +#include "mcs_mtr_param.h" + +/** + * @brief Speed controller struct members and parameters. + */ +typedef struct { + PID_Handle spdPi; /**< PI controller struct in the speed controller. */ + float outLimit; /**< Maximum of the speed controller output. */ + MOTOR_Param *mtrParam; /**< Motor parameters. */ + float ts; /**< Speed controller control period (s). */ +} SPDCTRL_Handle; + +void SPDCTRL_Init(SPDCTRL_Handle *spdHandle, MOTOR_Param *mtrParam, const PI_Param piParam, float ts); + +void SPDCTRL_Reset(SPDCTRL_Handle *spdHandle); + +void SPDCTRL_Clear(SPDCTRL_Handle *spdHandle); + +float SPDCTRL_Exec(SPDCTRL_Handle *spdHandle, float spdTarget, float spdFbk); + +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_startup.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_startup.c new file mode 100644 index 00000000..3bc2138d --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_startup.c @@ -0,0 +1,75 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_startup.c + * @author MCU Algorithm Team + * @brief This file provides transition method from startup stage to run stage。 + */ + +#include "mcs_startup.h" +#include "mcs_math.h" +#include "mcs_assert.h" + +/** + * @brief Init the startup control handle. + * @param startHandle The startup coontrol handle. + * @param spdBegin The begin speed for transition process. + * @param spdEnd The end speed for transition process. + * @retval None. + */ +void STARTUP_Init(STARTUP_Handle *startHandle, float spdBegin, float spdEnd) +{ + MCS_ASSERT_PARAM(startHandle != NULL); + MCS_ASSERT_PARAM(spdBegin > 0.0f); + MCS_ASSERT_PARAM(spdEnd > 0.0f); + MCS_ASSERT_PARAM(spdBegin < spdEnd); + startHandle->stage = STARTUP_STAGE_CURR; + startHandle->spdBegin = spdBegin; + startHandle->spdEnd = spdEnd; + /* current AMP = slope * control period */ + startHandle->regionInv = 1.0f / (startHandle->spdEnd - startHandle->spdBegin); +} + +/** + * @brief Clear hisitory value, assign the stage to current change. + * @param startHandle The startup control handle. + * @retval None. + */ +void STARTUP_Clear(STARTUP_Handle *startHandle) +{ + MCS_ASSERT_PARAM(startHandle != NULL); + startHandle->stage = STARTUP_STAGE_CURR; +} + +/** + * @brief Calculate the reference current in the startup stage. + * @param startHandle The startup control handle. + * @param refHz The speed reference in the startup stage. + * @return The current AMP. + */ +float STARTUP_CurrCal(const STARTUP_Handle *startHandle, float refHz) +{ + MCS_ASSERT_PARAM(startHandle != NULL); + float out; + float tmp; + /* Calculate the reference current in the startup stage */ + tmp = startHandle->spdEnd - Abs(refHz); + tmp = tmp * startHandle->regionInv; + out = tmp * startHandle->initCurr; + + return out; +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_startup.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_startup.h new file mode 100644 index 00000000..725cdd99 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/foc_loop_ctrl/mcs_startup.h @@ -0,0 +1,63 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_startup.h + * @author MCU Algorithm Team + * @brief Motor transition process from one speed and angle to another speed and angle. + */ + + +#ifndef McuMagicTag_MCS_STARTUP_H +#define McuMagicTag_MCS_STARTUP_H + +/** + * @brief Startup process enum. + * @details Speed transition stages: + * + STARTUP_STAGE_CURR -- Stage of current AMP is changing + * + STARTUP_STAGE_SPD -- Stage of speed is changing + * + STARTUP_STAGE_SWITCH -- Stage of switch + * + STARTUP_STAGE_DETECT -- Stage of detect switch open loop + */ +typedef enum { + STARTUP_STAGE_CURR = 1, + STARTUP_STAGE_SPD, + STARTUP_STAGE_SWITCH, + STARTUP_STAGE_DETECT, +} STARTUP_Stage; + +/** + * @brief Startup handover method struct members and parameters. + */ +typedef struct { + STARTUP_Stage stage; /**< Startup switching status. */ + float spdBegin; /**< Startup switching start speed (Hz). */ + float spdEnd; /**< Startup switching end speed (Hz). */ + float regionInv; /**< Inverse of the speed region. */ + float initCurr; /**< The initial current (A). */ +} STARTUP_Handle; + + +/** + * @defgroup STARTUP_API STARTUP API + * @brief The startup management API declaration. + * @{ + */ +void STARTUP_Init(STARTUP_Handle *startHandle, float spdBegin, float spdEnd); +void STARTUP_Clear(STARTUP_Handle *startHandle); +float STARTUP_CurrCal(const STARTUP_Handle *startHandle, float refHz); + +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/math/mcs_math.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/math/mcs_math.c new file mode 100644 index 00000000..d1e932f0 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/math/mcs_math.c @@ -0,0 +1,557 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_math.c + * @author MCU Algorithm Team + * @brief This file provides common math functions including trigonometric, coordinate transformation, + * square root math calculation. + */ + +#include "mcs_math.h" +#include "mcs_math_const.h" +#include "mcs_assert.h" + +/* Macro definitions --------------------------------------------------------------------------- */ +#define SIN_TABLE \ + { \ + 0, 51, 101, 151, 202, 252, 302, 352, 403, 453, 503, 553, 604, 654, 704, 754, 805, 855, 905, 955, 1006, 1056, \ + 1106, 1156, 1207, 1257, 1307, 1357, 1407, 1458, 1508, 1558, 1608, 1659, 1709, 1759, 1809, 1859, 1909, \ + 1960, 2010, 2060, 2110, 2160, 2210, 2261, 2311, 2361, 2411, 2461, 2511, 2561, 2611, 2662, 2712, 2762, \ + 2812, 2862, 2912, 2962, 3012, 3062, 3112, 3162, 3212, 3262, 3312, 3362, 3412, 3462, 3512, 3562, 3612, \ + 3662, 3712, 3762, 3812, 3862, 3912, 3962, 4012, 4061, 4111, 4161, 4211, 4261, 4311, 4360, 4410, 4460, \ + 4510, 4560, 4609, 4659, 4709, 4759, 4808, 4858, 4908, 4958, 5007, 5057, 5107, 5156, 5206, 5255, 5305, \ + 5355, 5404, 5454, 5503, 5553, 5602, 5652, 5701, 5751, 5800, 5850, 5899, 5949, 5998, 6048, 6097, 6146, \ + 6196, 6245, 6294, 6344, 6393, 6442, 6492, 6541, 6590, 6639, 6689, 6738, 6787, 6836, 6885, 6934, 6983, \ + 7033, 7082, 7131, 7180, 7229, 7278, 7327, 7376, 7425, 7474, 7523, 7572, 7620, 7669, 7718, 7767, 7816, \ + 7865, 7913, 7962, 8011, 8060, 8108, 8157, 8206, 8254, 8303, 8352, 8400, 8449, 8497, 8546, 8594, 8643, \ + 8691, 8740, 8788, 8837, 8885, 8933, 8982, 9030, 9078, 9127, 9175, 9223, 9271, 9320, 9368, 9416, 9464, \ + 9512, 9560, 9608, 9656, 9704, 9752, 9800, 9848, 9896, 9944, 9992, 10040, 10088, 10136, 10183, 10231, \ + 10279, 10327, 10374, 10422, 10470, 10517, 10565, 10612, 10660, 10707, 10755, 10802, 10850, 10897, 10945, \ + 10992, 11039, 11087, 11134, 11181, 11228, 11276, 11323, 11370, 11417, 11464, 11511, 11558, 11605, 11652, \ + 11699, 11746, 11793, 11840, 11887, 11934, 11981, 12027, 12074, 12121, 12167, 12214, 12261, 12307, 12354, \ + 12400, 12447, 12493, 12540, 12586, 12633, 12679, 12725, 12772, 12818, 12864, 12910, 12957, 13003, 13049, \ + 13095, 13141, 13187, 13233, 13279, 13325, 13371, 13417, 13463, 13508, 13554, 13600, 13646, 13691, 13737, \ + 13783, 13828, 13874, 13919, 13965, 14010, 14056, 14101, 14146, 14192, 14237, 14282, 14327, 14373, 14418, \ + 14463, 14508, 14553, 14598, 14643, 14688, 14733, 14778, 14823, 14867, 14912, 14957, 15002, 15046, 15091, \ + 15136, 15180, 15225, 15269, 15314, 15358, 15402, 15447, 15491, 15535, 15580, 15624, 15668, 15712, 15756, \ + 15800, 15844, 15888, 15932, 15976, 16020, 16064, 16108, 16151, 16195, 16239, 16282, 16326, 16369, 16413, \ + 16456, 16500, 16543, 16587, 16630, 16673, 16717, 16760, 16803, 16846, 16889, 16932, 16975, 17018, 17061, \ + 17104, 17147, 17190, 17233, 17275, 17318, 17361, 17403, 17446, 17488, 17531, 17573, 17616, 17658, 17700, \ + 17743, 17785, 17827, 17869, 17911, 17953, 17995, 18037, 18079, 18121, 18163, 18205, 18247, 18288, 18330, \ + 18372, 18413, 18455, 18496, 18538, 18579, 18621, 18662, 18703, 18745, 18786, 18827, 18868, 18909, 18950, \ + 18991, 19032, 19073, 19114, 19155, 19195, 19236, 19277, 19317, 19358, 19398, 19439, 19479, 19520, 19560, \ + 19600, 19641, 19681, 19721, 19761, 19801, 19841, 19881, 19921, 19961, 20001, 20041, 20080, 20120, 20160, \ + 20199, 20239, 20278, 20318, 20357, 20397, 20436, 20475, 20514, 20554, 20593, 20632, 20671, 20710, 20749, \ + 20788, 20826, 20865, 20904, 20943, 20981, 21020, 21058, 21097, 21135, 21174, 21212, 21250, 21289, 21327, \ + 21365, 21403, 21441, 21479, 21517, 21555, 21593, 21630, 21668, 21706, 21744, 21781, 21819, 21856, 21894, \ + 21931, 21968, 22005, 22043, 22080, 22117, 22154, 22191, 22228, 22265, 22302, 22339, 22375, 22412, 22449, \ + 22485, 22522, 22558, 22595, 22631, 22667, 22704, 22740, 22776, 22812, 22848, 22884, 22920, 22956, 22992, \ + 23028, 23063, 23099, 23135, 23170, 23206, 23241, 23277, 23312, 23347, 23383, 23418, 23453, 23488, 23523, \ + 23558, 23593, 23628, 23662, 23697, 23732, 23767, 23801, 23836, 23870, 23904, 23939, 23973, 24007, 24042, \ + 24076, 24110, 24144, 24178, 24212, 24245, 24279, 24313, 24347, 24380, 24414, 24447, 24481, 24514, 24547, \ + 24581, 24614, 24647, 24680, 24713, 24746, 24779, 24812, 24845, 24878, 24910, 24943, 24975, 25008, 25040, \ + 25073, 25105, 25137, 25170, 25202, 25234, 25266, 25298, 25330, 25362, 25393, 25425, 25457, 25488, 25520, \ + 25551, 25583, 25614, 25646, 25677, 25708, 25739, 25770, 25801, 25832, 25863, 25894, 25925, 25955, 25986, \ + 26017, 26047, 26078, 26108, 26138, 26169, 26199, 26229, 26259, 26289, 26319, 26349, 26379, 26409, 26438, \ + 26468, 26498, 26527, 26557, 26586, 26616, 26645, 26674, 26703, 26732, 26761, 26790, 26819, 26848, 26877, \ + 26906, 26934, 26963, 26991, 27020, 27048, 27077, 27105, 27133, 27161, 27189, 27217, 27245, 27273, 27301, \ + 27329, 27356, 27384, 27412, 27439, 27467, 27494, 27521, 27549, 27576, 27603, 27630, 27657, 27684, 27711, \ + 27737, 27764, 27791, 27817, 27844, 27870, 27897, 27923, 27949, 27976, 28002, 28028, 28054, 28080, 28106, \ + 28132, 28157, 28183, 28209, 28234, 28260, 28285, 28310, 28336, 28361, 28386, 28411, 28436, 28461, 28486, \ + 28511, 28535, 28560, 28585, 28609, 28634, 28658, 28682, 28707, 28731, 28755, 28779, 28803, 28827, 28851, \ + 28875, 28898, 28922, 28946, 28969, 28993, 29016, 29039, 29063, 29086, 29109, 29132, 29155, 29178, 29201, \ + 29223, 29246, 29269, 29291, 29314, 29336, 29359, 29381, 29403, 29425, 29447, 29469, 29491, 29513, 29535, \ + 29557, 29578, 29600, 29622, 29643, 29664, 29686, 29707, 29728, 29749, 29770, 29791, 29812, 29833, 29854, \ + 29874, 29895, 29916, 29936, 29956, 29977, 29997, 30017, 30037, 30057, 30077, 30097, 30117, 30137, 30157, \ + 30176, 30196, 30215, 30235, 30254, 30273, 30292, 30312, 30331, 30350, 30369, 30387, 30406, 30425, 30443, \ + 30462, 30481, 30499, 30517, 30536, 30554, 30572, 30590, 30608, 30626, 30644, 30661, 30679, 30697, 30714, \ + 30732, 30749, 30767, 30784, 30801, 30818, 30835, 30852, 30869, 30886, 30903, 30919, 30936, 30952, 30969, \ + 30985, 31002, 31018, 31034, 31050, 31066, 31082, 31098, 31114, 31129, 31145, 31161, 31176, 31192, 31207, \ + 31222, 31237, 31253, 31268, 31283, 31298, 31312, 31327, 31342, 31357, 31371, 31386, 31400, 31414, 31429, \ + 31443, 31457, 31471, 31485, 31499, 31513, 31526, 31540, 31554, 31567, 31581, 31594, 31607, 31620, 31634, \ + 31647, 31660, 31673, 31685, 31698, 31711, 31724, 31736, 31749, 31761, 31773, 31786, 31798, 31810, 31822, \ + 31834, 31846, 31857, 31869, 31881, 31892, 31904, 31915, 31927, 31938, 31949, 31960, 31971, 31982, 31993, \ + 32004, 32015, 32025, 32036, 32047, 32057, 32067, 32078, 32088, 32098, 32108, 32118, 32128, 32138, 32148, \ + 32157, 32167, 32177, 32186, 32195, 32205, 32214, 32223, 32232, 32241, 32250, 32259, 32268, 32276, 32285, \ + 32294, 32302, 32311, 32319, 32327, 32335, 32343, 32351, 32359, 32367, 32375, 32383, 32390, 32398, 32405, \ + 32413, 32420, 32427, 32435, 32442, 32449, 32456, 32463, 32469, 32476, 32483, 32489, 32496, 32502, 32509, \ + 32515, 32521, 32527, 32533, 32539, 32545, 32551, 32557, 32562, 32568, 32573, 32579, 32584, 32589, 32595, \ + 32600, 32605, 32610, 32615, 32619, 32624, 32629, 32633, 32638, 32642, 32647, 32651, 32655, 32659, 32663, \ + 32667, 32671, 32675, 32679, 32682, 32686, 32689, 32693, 32696, 32700, 32703, 32706, 32709, 32712, 32715, \ + 32718, 32720, 32723, 32726, 32728, 32730, 32733, 32735, 32737, 32739, 32741, 32743, 32745, 32747, 32749, \ + 32751, 32752, 32754, 32755, 32756, 32758, 32759, 32760, 32761, 32762, 32763, 32764, 32764, 32765, 32766, \ + 32766, 32767, 32767, 32767, 32767, 32767 \ + } + +const float atanInBottom[50] = { 0.0f, 0.102040816326531f, 0.204081632653061f, 0.306122448979592f, \ + 0.408163265306122f, 0.510204081632653f, 0.612244897959184f, 0.714285714285714f, \ + 0.816326530612245f, 0.918367346938776f, 1.02040816326531f, 1.12244897959184f, \ + 1.22448979591837f, 1.32653061224490f, 1.42857142857143f, 1.53061224489796f, \ + 1.63265306122449f, 1.73469387755102f, 1.83673469387755f, 1.93877551020408f, \ + 2.04081632653061f, 2.14285714285714f, 2.24489795918367f, 2.34693877551020f, \ + 2.44897959183673f, 2.55102040816327f, 2.65306122448980f, 2.75510204081633f, \ + 2.85714285714286f, 2.95918367346939f, 3.06122448979592f, 3.16326530612245f, \ + 3.26530612244898f, 3.36734693877551f, 3.46938775510204f, 3.57142857142857f, \ + 3.67346938775510f, 3.77551020408163f, 3.87755102040816f, 3.97959183673469f, \ + 4.08163265306123f, 4.18367346938776f, 4.28571428571429f, 4.38775510204082f, \ + 4.48979591836735f, 4.59183673469388f, 4.69387755102041f, 4.79591836734694f, \ + 4.89795918367347f, 5.0f}; +const float atanValBottom[50] = { 0.0f, 0.101688851763077f, 0.201317108374641f, 0.297064212341043f, \ + 0.387523805780279f, 0.471777511180750f, 0.549374484771551f, 0.620249485982822f, \ + 0.684617164312781f, 0.742870628777664f, 0.795498829982770f, 0.843026590874922f, \ + 0.885975080852296f, 0.924838220488786f, 0.960070362405688f, 0.992081381881698f, \ + 1.02123631326852f, 1.04785756322372f, 1.07222842115668f, 1.09459707572452f, \ + 1.11518067358367f, 1.13416916698136f, 1.15172882709508f, 1.16800537775525f, \ + 1.18312674842090f, 1.19720546875916f, 1.21034073815249f, 1.22262020713844f, \ + 1.23412150740817f, 1.24491356451280f, 1.25505772401419f, 1.26460871813527f, \ + 1.27361549637858f, 1.28212194027307f, 1.29016747945525f, 1.29778762370819f, \ + 1.30501442335451f, 1.31187686849742f, 1.31840123598843f, 1.32461139163550f, \ + 1.33052905401396f, 1.33617402527335f, 1.34156439351790f, 1.34671671065198f, \ + 1.35164614900430f, 1.35636663955779f, 1.36089099420126f, 1.36523101407236f, \ + 1.36939758576738f, 1.37340076694502f}; +const float atanInMid[25] = { 5.0f, 5.625f, 6.25f, 6.875f, 7.5f, \ + 8.125f, 8.75f, 9.375f, 10.0f, 10.625f, \ + 11.25f, 11.875f, 12.5f, 13.125f, 13.75f, \ + 14.375f, 15.0f, 15.625f, 16.25f, 16.875f, \ + 17.5f, 18.125f, 18.75f, 19.375f, 20.0f}; +const float atanValMid[25] = { 1.373400766945016f, 1.394856701342369f, 1.41214106460850f, 1.42635474842025f, \ + 1.43824479449822f, 1.44833526937756f, 1.45700431965119f, 1.46453146390382f, \ + 1.47112767430373f, 1.47695511416556f, 1.48214044492746f, 1.48678401498740f, \ + 1.49096634108266f, 1.49475276751578f, 1.49819687306440f, 1.50134300079957f, \ + 1.50422816301907f, 1.50688349400616f, 1.50933537091213f, 1.51160628786678f, \ + 1.51371554438863f, 1.51567979250081f, 1.51751347523520f, 1.51922918085206f, \ + 1.52083793107295f}; +const float atanInTop[10] = { 20.0f, 128.888888888889f, 237.777777777778f, 346.666666666667f, \ + 455.555555555556f, 564.444444444445f, 673.333333333333f, 782.222222222222f, \ + 891.111111111111f, 1000.0f}; +const float atanValTop[10] = { 1.52083793107295f, 1.56303786177943f, 1.56659074411305f, 1.56791171941121f, \ + 1.56860120836944f, 1.56902467510518f, 1.56931117937196f, 1.56951791840043f, \ + 1.56967413275225f, 1.56979632712823f}; + +#define SIN_MASK 0x0C00 +#define U0_90 0x0800 +#define U90_180 0x0C00 +#define U180_270 0x0000 +#define U270_360 0x0400 +#define SIN_TAB_LEN 0x03FF +#define Q15_BASE 32768 +#define ANGLE_TO_INDEX_SHIFT 4 + +#define ATAN_INPUTVALUE_MIN 5.0f +#define ATAN_INPUTVALUE_MID 20.0f +#define ATAN_INPUTVALUE_MAX 1000.0f + +#define MATH_FACTORIAL3INVERSE 0.16666667f /**< 1 / 6 */ +#define MATH_FACTORIAL5INVERSE 0.008333333f /**< 1 / 120 */ +#define MATH_FACTORIAL7INVERSE 0.0001984127f /**< 1 / 5040 */ + +/* Private variables --------------------------------------------------------- */ +const short g_sinTable[SIN_TAB_LEN + 1] = SIN_TABLE; + + +/** + * @brief Using Taylor Expansion to Calculate Sin Values in rad. + * @param angle Angle value to be calculated. + * @retval float Calculated sin value. + */ +static float TaylorCalSinIn90(float angle) +{ + float radian = angle; + float radian3 = radian * radian * radian; /* power(3) */ + float radian5 = radian3 * radian * radian; + float radian7 = radian5 * radian * radian; /* power(7) */ + /* Using Taylor Expansion to Calculate Sin Values in 90 Degrees. */ + return (radian - radian3 * MATH_FACTORIAL3INVERSE + \ + radian5 * MATH_FACTORIAL5INVERSE - radian7 * MATH_FACTORIAL7INVERSE); +} + +/** + * @brief Using Taylor Expansion to Calculate Sin Values for Any Angle. + * @param angle Angle value to be calculated. + * @retval float Calculated sin value. + */ +float GetSin(float angle) +{ + /* limit the data scope to (0 - 2PI) */ + float angleIn2pi = Mod(angle, DOUBLE_PI); + if (angleIn2pi < 0) { + angleIn2pi = angleIn2pi + DOUBLE_PI; + } + if (angleIn2pi < HALF_PI) { /* 0 ~ 90° */ + return TaylorCalSinIn90(angleIn2pi); + } + if (angleIn2pi < ONE_PI) { /* 90 ~ 180° */ + return TaylorCalSinIn90(ONE_PI - angleIn2pi); + } + if (angleIn2pi < THREE_PI_DIV_TWO) { /* 180 ~ 270° */ + return -TaylorCalSinIn90(angleIn2pi - ONE_PI); + } + return -TaylorCalSinIn90(DOUBLE_PI - angleIn2pi); /* 270 ~ 360° */ +} + +/** + * @brief Using Taylor Expansion to Calculate Sin Values for Any Angle. + * @param angle Angle value to be calculated. + * @retval float Calculated sin value. + */ +float GetCos(float angle) +{ + /* limit the data scope to (0 - 2PI) */ + float angleIn2pi = Mod(angle, DOUBLE_PI); + if (angleIn2pi < 0) { + angleIn2pi = angleIn2pi + DOUBLE_PI; + } + if (angleIn2pi < HALF_PI) { /* 0 ~ 90° */ + return TaylorCalSinIn90(HALF_PI - angleIn2pi); + } + if (angleIn2pi < ONE_PI) { /* 90 ~ 180° */ + return -TaylorCalSinIn90(angleIn2pi - HALF_PI); + } + if (angleIn2pi < THREE_PI_DIV_TWO) { /* 180 ~ 270° */ + return -TaylorCalSinIn90(THREE_PI_DIV_TWO - angleIn2pi); + } + return TaylorCalSinIn90(angleIn2pi - THREE_PI_DIV_TWO); /* 270 ~ 360° */ +} + + +/** + * @brief Calculate sine and cosine function of the input angle. + * @param val: Output result, which contain the calculated sin, cos value. + * @param angle: The input parameter angle (rad). + * @retval None. + */ +void TrigCalc(TrigVal *val, float angle) +{ + MCS_ASSERT_PARAM(val != NULL); + val->sin = GetSin(angle); + val->cos = GetCos(angle); +} + +/** + * @brief Park transformation: transforms stator values alpha and beta, which + * belong to a stationary albe reference frame, to a rotor flux + * synchronous reference dq frame. + * @param albe: Input alpha beta axis value. + * @param angle: Input the theta angle (rad). + * @param dq: Output DQ axis value. + * @retval None + */ +void ParkCalc(const AlbeAxis *albe, float angle, DqAxis *dq) +{ + MCS_ASSERT_PARAM(albe != NULL); + MCS_ASSERT_PARAM(dq != NULL); + float alpha = albe->alpha; + float beta = albe->beta; + TrigVal localTrigVal; + /* The projection of ia, ib, and ic currents on alpha and beta axes is equivalent to that on d, q axes. */ + TrigCalc(&localTrigVal, angle); + dq->d = alpha * localTrigVal.cos + beta * localTrigVal.sin; + dq->q = -alpha * localTrigVal.sin + beta * localTrigVal.cos; +} + +/** + * @brief Inverse Park transformation: transforms stator values d and q, which + * belong to a rotor flux synchronous reference dq frame, to a stationary + * albe reference frame. + * @param dq: Input DQ axis value. + * @param angle: Input the theta angle (rad). + * @param albe: Output alpha beta axis value. + * @retval None + */ +void InvParkCalc(const DqAxis *dq, float angle, AlbeAxis *albe) +{ + MCS_ASSERT_PARAM(dq != NULL); + MCS_ASSERT_PARAM(albe != NULL); + float d = dq->d; + float q = dq->q; + TrigVal localTrigVal; + /* Inversely transform the d, q-axis current to alpha ,beta. */ + TrigCalc(&localTrigVal, angle); + albe->alpha = d * localTrigVal.cos - q * localTrigVal.sin; + albe->beta = d * localTrigVal.sin + q * localTrigVal.cos; +} + +/** + * @brief Clarke transformation: transforms stationary three-phase quantites to + * stationary albe quantites. + * @param uvw: Clarke struct handle. + * @param albe: AlbeAxis struct handle used to store the Clarke transform output. + * @retval None. + */ +void ClarkeCalc(const UvwAxis *uvw, AlbeAxis *albe) +{ + MCS_ASSERT_PARAM(uvw != NULL); + MCS_ASSERT_PARAM(albe != NULL); + albe->alpha = uvw->u; + albe->beta = ONE_DIV_SQRT3 * (uvw->u + 2.0f * uvw->v); +} + +/** + * @brief This function returns the absolute value of the input value. + * @param val: The quantity that wants to execute absolute operation. + * @retval The absolute value of the input value. + */ +float Abs(float val) +{ + return (val >= 0.0f) ? val : (-val); +} + +/** + * @brief Clamp operation. + * @param val Value that needs to be clamped. + * @param upperLimit The upper limitation. + * @param lowerLimit The lower limitation. + * @retval Clamped value. + */ +float Clamp(float val, float upperLimit, float lowerLimit) +{ + MCS_ASSERT_PARAM(upperLimit > lowerLimit); + float result; + /* Clamping Calculation. */ + if (val >= upperLimit) { + result = upperLimit; + } else if (val <= lowerLimit) { + result = lowerLimit; + } else { + result = val; + } + return result; +} + +/** + * @brief Get bigger value. + * @param val1 The value to be compared. + * @param val2 The value to be compared. + * @retval The greater value. + */ +float Max(float val1, float val2) +{ + return ((val1 >= val2) ? val1 : val2); +} + +/** + * @brief Get smaller value. + * @param val1 The value to be compared. + * @param val2 The value to be compared. + * @retval The smaller value. + */ +float Min(float val1, float val2) +{ + return ((val1 <= val2) ? val1 : val2); +} + +/** + * @brief Fast sqrt calculation using ASM. + * @param val Float val. + * @retval Sqrt result. + */ +float Sqrt(float val) +{ + MCS_ASSERT_PARAM(val >= 0.0f); + float rd = val; + + __asm volatile("fsqrt.s %0, %1" : "=f"(rd) : "f"(val)); + + return rd; +} + + +/** + * @brief Angle difference calculation. + * @param angle1 Angle to be substracted. + * @param angle2 Angle to substract. + * @retval Angle difference. + */ +float AngleSub(float angle1, float angle2) +{ + /* Calculate the error of the two angle. */ + float err = angle1 - angle2; + + /* If error between -pi to pi, return error without changes. */ + err = Mod(err, DOUBLE_PI); + if (err > ONE_PI) { + err -= DOUBLE_PI; + } else if (err < -ONE_PI) { + err += DOUBLE_PI; + } + + return err; +} + + +/** + * @brief Dichotomy to find the position of the target value in the array. + * @param u: Target Value. + * @param table: Pointer of Array. + * @param startIndex: Start Index + * @param maxIndex: Max Index. + * @retval Target index. + */ + +static unsigned short BinSearch(float u, const float *table, + unsigned short startIndex, + unsigned short maxIndex) +{ + MCS_ASSERT_PARAM(table != NULL); + /* The dot to the left of the dichotomy */ + unsigned short iLeft; + /* The dot to the right of the dichotomy */ + unsigned short iRight; + /* The point in the middle of the dichotomy */ + unsigned short iMid; + + /* Binary Search */ + iMid = startIndex; + iLeft = 0U; + iRight = maxIndex; + while ((unsigned short)(iRight - iLeft) > 1U) { + if (u < table[iMid]) { + /* The target value is a bit smaller than the current value on the left */ + iRight = iMid; + } else { + /* TThe target value is greater than the current value on the right */ + iLeft = iMid; + } + /* Get the next intermediate point */ + iMid = ((unsigned short)(iRight + iLeft)) >> 1; + } + return iLeft; +} + +/** + * @brief Dichotomy to find the position of the target value in the array. + * @param u: Target Value. + * @param table: Pointer of Array. + * @param fraction: Poniter ratio value addr. + * @param maxIndex: Max Index. + * @retval Target index. + */ +static unsigned short PreLookBinSearch(float u, const float *table, + unsigned short maxIndex, + float *fraction) +{ + MCS_ASSERT_PARAM(table != NULL); + MCS_ASSERT_PARAM(fraction != NULL); + /* Dichotomy to find the position of the target value in the array */ + unsigned short index; + if (u <= table[0U]) { + /* Less than the minimum value in the table */ + index = 0U; + *fraction = 0.0f; + } else if (u < table[maxIndex]) { + index = BinSearch(u, table, maxIndex >> 1U, maxIndex); + *fraction = (u - table[index]) / (table[index + 1U] - table[index]); + } else { + /* Greater than the minimum value in the table */ + index = maxIndex; + *fraction = 0.0f; + } + return index; +} + +/** + * @brief calculating arc tangent. + * @param u: Target Value. + * @retval Arctangent value of U. + */ +static float ATan(float u) +{ + float tmp = Abs(u); + float frac = 0.0f; + unsigned short index = 0; + float y = 0.0f; + if (tmp >= 0.0f && tmp < ATAN_INPUTVALUE_MIN) { + index = PreLookBinSearch(tmp, atanInBottom, 49U, &frac); /* atanInBottom Max Index is 49 */ + y = atanValBottom[index] + frac * (atanValBottom[index + 1] - atanValBottom[index]); + } else if (tmp >= ATAN_INPUTVALUE_MIN && tmp < ATAN_INPUTVALUE_MID) { + index = PreLookBinSearch(tmp, atanInMid, 24U, &frac); /* atanInMid Max Index is 24 */ + y = atanValMid[index] + frac * (atanValMid[index + 1] - atanValMid[index]); + } else if (tmp >= ATAN_INPUTVALUE_MID && tmp < ATAN_INPUTVALUE_MAX) { + index = PreLookBinSearch(tmp, atanInTop, 9U, &frac); /* atanInTop Max Index is 9 */ + y = atanValTop[index] + frac * (atanValTop[index + 1] - atanValTop[index]); + } else { + y = HALF_PI; /* The input parameter is greater than the maximum radian, The value is PI/2. */ + } + return (u > 0.0f)? y : (- y); +} + + +/** + * @brief modulo operation. + * @param val1 The value to be modulo. + * @param val2 The value to modulo. + * @retval modulo result. + */ +float Mod(float val1, float val2) +{ + MCS_ASSERT_PARAM(val2 > 0.0f); + + int temp = (int)(val1 / val2); + float res = val1 - (float)temp * val2; + return res; +} + + +/** + * @brief Atan2 arctangent calculation. + * @param x Floating-point value representing the X-axis coordinate. + * @param y Floating-point value representing the Y-axis coordinate. + * @retval The atan2 function returns the azimuth from the origin to the point (x, y), that is, + the angle from the x axis. It can also be understood as the argument of the complex number x+yi. + The unit of the returned value is radian. The value range is -pi ~ pi. + */ +float Atan2(float x, float y) +{ + float fZero = 0.0f; + if (x > fZero) { + return ATan(y / x); + } + if (x < fZero && y >= fZero) { + return ATan(y / x) + ONE_PI; + } + if (x < fZero && y < fZero) { + return ATan(y / x) - ONE_PI; + } + /* boundary condition */ + if ((Abs(x) < 0.0001f) && y > fZero) { + return (HALF_PI); + } + if (Abs(x) < 0.0001f && y < fZero) { + return -(HALF_PI); + } + /* default return */ + return fZero; +} + +/** + * @brief Saturation function for dead voltage computing. + * @param u The current amp of zero crossing point. + * @param delta Saturated output point. + * @return Saturation value ([-1.0f, 1.0f]). + */ +float Sat(float u, float delta) +{ + BASE_FUNC_ASSERT_PARAM(delta > 0.0f); + /* less than -0.1, return -1 */ + if (u < -delta) { + return -1.0f; + } else if (u > delta) { /* large than 0.1, return 1 */ + return 1.0f; + } else { + return (u / delta); /* all other values */ + } +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/math/mcs_math.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/math/mcs_math.h new file mode 100644 index 00000000..0992dc10 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/math/mcs_math.h @@ -0,0 +1,63 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_math.h + * @author MCU Algorithm Team + * @brief Math library. + * This file provides math functions declaration of motor math module. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_MATH_H +#define McuMagicTag_MCS_MATH_H + +/* Includes ------------------------------------------------------------------------------------ */ +#include "mcs_typedef.h" +#include "base_math.h" + + +/** + * @brief sin cos define + */ +typedef struct { + float sin; /**< The sine value of input angle. */ + float cos; /**< The cosine value of input angle. */ +} TrigVal; + + +/** + * @defgroup MATH_API MATH API + * @brief The common math API definition. + * @{ + */ +float GetSin(float angle); +float GetCos(float angle); +void TrigCalc(TrigVal *val, float angle); +void ParkCalc(const AlbeAxis *albe, float angle, DqAxis *dq); +void InvParkCalc(const DqAxis *dq, float angle, AlbeAxis *albe); +void ClarkeCalc(const UvwAxis *uvw, AlbeAxis *albe); +float Abs(float val); +float Clamp(float val, float upperLimit, float lowerLimit); +float Max(float val1, float val2); +float Min(float val1, float val2); +float Sqrt(float val); +float AngleSub(float angle1, float angle2); +float Mod(float val1, float val2); +float Sat(float u, float delta); +float Atan2(float x, float y); + +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/math/mcs_math_const.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/math/mcs_math_const.h new file mode 100644 index 00000000..6a605bd9 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/math/mcs_math_const.h @@ -0,0 +1,72 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_math_const.h + * @author MCU Algorithm Team + * @brief This file provides math constant macro definition functionality for + * managing math calculation number definitions. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_MCS_MATH_CONST_H +#define McuMagicTag_MCS_MATH_CONST_H + +/** + * @addtogroup MATH + * @brief Math const definition. + * @{ + */ + +/** + * @defgroup MATH_CONST MATH CONST + * @brief The common math const definition for motor control. + * @{ + */ +/* Macro definitions ---------------------------------------------------------*/ +#define ONE_DIV_THREE (0.3333333f) /**< 1/3 */ +#define TWO_DIV_THREE (0.6666667f) /**< 2/3 */ +#define ONE_PI_DIV_SIX (0.5235988f) /**< PI/6 */ +#define ONE_PI_DIV_THREE (1.047197f) /**< PI/3 */ +#define ONE_PI (3.141593f) /**< PI */ +#define DOUBLE_PI_DIV_THREE (2.094395f) /**< 2PI/3 */ +#define DOUBLE_PI (6.283185f) /**< 2*PI */ +#define SQRT3_DIV_TWO (0.8660254f) /**< Sqrt(3)/2 */ +#define ONE_DIV_SQRT3 (0.5773503f) /**< 1/sqrt(3) */ +#define ONE_DIV_DOUBLE_PI (0.1591549f) /**< 1/(2*PI) */ +#define RAD_TO_DEG (57.29578f) /**< 1/pi*180 */ +#define RAD_TO_DIGITAL (10430.06f) /**< 1/pi*32767 */ +#define DIGITAL_TO_RAD (0.00009587673f) /**< pi/32767 */ +#define HALF_PI (1.5707963f) /**< 0.5*pi */ +#define THREE_PI_DIV_TWO (4.7123890f) /**< 1.5*pi */ +#define ONE_DIV_SIX (0.16666667f) /**< 1/6 */ +#define SEVEN_DIV_SIX (1.16666667f) /**< 7/6 */ +#define SIXTY_FIVE_DIV_SIX (10.8333333f) /**< 65/6 */ +#define SEVENTY_ONE_DIV_SIX (11.8333333f) /**< 71/6 */ +#define ONE_DIV_NINE (0.11111111f) /**< 1/9 */ +#define ONE_DIV_TWELVE (0.08333333f) /**< 1/12 */ +#define SQRT2 (1.41421356f) /**< sqrt(2) */ +#define SMALL_FLOAT (0.00000001f) +#define LARGE_FLOAT (10000.0f) +/** + * @} + */ + + /** + * @} + */ + +#endif /* McuMagicTag_MCS_MATH_CONST_H */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/modulation/mcs_r1_svpwm.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/modulation/mcs_r1_svpwm.c new file mode 100644 index 00000000..911f6702 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/modulation/mcs_r1_svpwm.c @@ -0,0 +1,234 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_r1_svpwm.c + * @author MCU Algorithm Team + * @brief This file provides function of Space-vector pulse-width-modulation calculations + * in case of single shunt current sample and current reconstruction. + */ + + +#include "mcs_r1_svpwm.h" +#include "mcs_assert.h" + + +/** + * @brief R1SVPWM handlel init. + * @param r1svHandle The R1SVPWM handle. + * @param voltPu Voltage per unit value. + */ +void R1SVPWM_Init(R1SVPWM_Handle *r1svHandle, float voltPu, float samplePointShift, float sampleWindow) +{ + MCS_ASSERT_PARAM(r1svHandle != NULL); + MCS_ASSERT_PARAM(voltPu > 0.0f); + MCS_ASSERT_PARAM(sampleWindow >= 0.0f && sampleWindow < 1.0f); + MCS_ASSERT_PARAM(samplePointShift > -1.0f && samplePointShift < 1.0f); + /* Initialize the phase-shift sampling window size and sampling point offset. */ + r1svHandle->samplePointShift = samplePointShift; + r1svHandle->sampleWindow = sampleWindow; + /* Initialize the Voltage per unit value */ + r1svHandle->voltPu = voltPu; + r1svHandle->oneDivVoltPu = 1.0f / voltPu; +} + +/** + * @brief R1SVPWM clear. + * @param r1svHandle The R1SVPWM handle. + * @retval None. + */ +void R1SVPWM_Clear(R1SVPWM_Handle *r1svHandle) +{ + MCS_ASSERT_PARAM(r1svHandle != NULL); + /* Clear the historical values calculated by the R1 SVPWM. */ + r1svHandle->voltIndex = 0; + r1svHandle->voltIndexLast = 0; + r1svHandle->samplePoint[SOCA] = 0.0f; + r1svHandle->samplePoint[SOCB] = 0.0f; +} + +/** + * @brief Phase shift calculation for single resistance sampling. + * @param r1SvCalc R1 svpwm calculation handle. + * @param sampleWindow sample window. + * @retval None. + */ +void R1SVPWM_PhaseShift(R1SVPWM_CALC_Handle *r1SvCalc, float sampleWindow) +{ + MCS_ASSERT_PARAM(r1SvCalc != NULL); + MCS_ASSERT_PARAM(sampleWindow >= 0.0f && sampleWindow < 1.0f); + /* Pointer to the array of left and right comparison values. */ + float *compRight = r1SvCalc->compRight; + float *compLeft = r1SvCalc->compLeft; + /* Comparison of three levels. */ + float compMax = r1SvCalc->svCalc.comp[SVPWM_COMP_VAL_MAX]; + float compMid = r1SvCalc->svCalc.comp[SVPWM_COMP_VAL_MID]; + float compMin = r1SvCalc->svCalc.comp[SVPWM_COMP_VAL_MIN]; + /* action time of two vectors */ + float t1 = r1SvCalc->svCalc.t1; + float t2 = r1SvCalc->svCalc.t2; + /** + * PWM phase shift: + * When the action time t1 of the first vector is less than the minimum sampling window, + * the phase with the smallest comparison value(with the largest duty) shifts to the right. + */ + if (t1 < sampleWindow) { + compRight[SVPWM_COMP_VAL_MIN] = compMid - sampleWindow; + compLeft[SVPWM_COMP_VAL_MIN] = compMin + sampleWindow - t1; + } else { + compRight[SVPWM_COMP_VAL_MIN] = compMin; + compLeft[SVPWM_COMP_VAL_MIN] = compMin; + } + + /** + * When the action time t2 of the second vector is less than the minimum sampling window, + * the phase with the largest comparison value (minimum duty) shifts to the left. + */ + if (t2 < sampleWindow) { + compRight[SVPWM_COMP_VAL_MAX] = compMid + sampleWindow; + compLeft[SVPWM_COMP_VAL_MAX] = compMax - sampleWindow + t2; + } else { + compRight[SVPWM_COMP_VAL_MAX] = compMax; + compLeft[SVPWM_COMP_VAL_MAX] = compMax; + } + /* intermediate large unshifted phase */ + compRight[SVPWM_COMP_VAL_MID] = compMid; + compLeft[SVPWM_COMP_VAL_MID] = compMid; +} + +/** + * @brief The duty cycles of PWM wave of three-phase upper switches are + * calculated in the two-phase stationary coordinate system (albe). + * @param r1svHandle R1SVPWM struct handle. + * @param uAlbe Input voltage vector. + * @param dutyUvwLeft Three-phase left duty cycle. + * @param dutyUvwRight Three-phase right duty cycle. + * @retval None. + */ +void R1SVPWM_Exec(R1SVPWM_Handle *r1svHandle, const AlbeAxis *uAlbe, UvwAxis *dutyUvwLeft, UvwAxis *dutyUvwRight) +{ + MCS_ASSERT_PARAM(r1svHandle != NULL); + MCS_ASSERT_PARAM(uAlbe != NULL); + MCS_ASSERT_PARAM(dutyUvwLeft != NULL); + MCS_ASSERT_PARAM(dutyUvwRight != NULL); + R1SVPWM_CALC_Handle r1SvCalc; + float *samplePoint = r1svHandle->samplePoint; + r1SvCalc.svCalc.vAlpha = uAlbe->alpha * r1svHandle->oneDivVoltPu; + r1SvCalc.svCalc.vBeta = uAlbe->beta * r1svHandle->oneDivVoltPu; + + /* Sector Calculation */ + SVPWM_SectorCalc(&r1SvCalc.svCalc); + /** + * In control tick k, record the sector number of the voltage vector calculated in the k–1 tick. + * For the next tick(k+1), it is the voltage vector to be applied. + * Calculate the sector number of the voltage vector that actually acts on the (k+1)th tick. + */ + r1svHandle->voltIndexLast = r1svHandle->voltIndex; + r1svHandle->voltIndex = r1SvCalc.svCalc.sectorIndex; + + if (r1SvCalc.svCalc.sectorIndex < SVPWM_SECTOR_INDEX_MIN || r1SvCalc.svCalc.sectorIndex > SVPWM_SECTOR_INDEX_MAX) { + dutyUvwLeft->u = 0.5f; + dutyUvwLeft->v = 0.5f; + dutyUvwLeft->w = 0.5f; + dutyUvwRight->u = 0.5f; + dutyUvwRight->v = 0.5f; + dutyUvwRight->w = 0.5f; + samplePoint[SOCA] = 0.5f; + samplePoint[SOCB] = 0.5f; + return; + } + /* Calculate three comparison values: max, medium, and min. */ + SVPWM_CompareValCalc(&r1SvCalc.svCalc); + /* phase shift */ + R1SVPWM_PhaseShift(&r1SvCalc, r1svHandle->sampleWindow); + + /* Set sample point SOCA */ + samplePoint[SOCA] = r1SvCalc.compRight[SVPWM_COMP_VAL_MIN] + r1svHandle->samplePointShift; + /* Set sample point SOCB */ + samplePoint[SOCB] = r1SvCalc.compRight[SVPWM_COMP_VAL_MID] + r1svHandle->samplePointShift; + /* Three-phase duty cycle data index based on sector convert */ + SVPWM_IndexConvert(&r1SvCalc.svCalc); + + dutyUvwLeft->u = r1SvCalc.compLeft[r1SvCalc.svCalc.indexU]; + dutyUvwLeft->v = r1SvCalc.compLeft[r1SvCalc.svCalc.indexV]; + dutyUvwLeft->w = r1SvCalc.compLeft[r1SvCalc.svCalc.indexW]; + dutyUvwRight->u = r1SvCalc.compRight[r1SvCalc.svCalc.indexU]; + dutyUvwRight->v = r1SvCalc.compRight[r1SvCalc.svCalc.indexV]; + dutyUvwRight->w = r1SvCalc.compRight[r1SvCalc.svCalc.indexW]; +} + +/** + * @brief The stator current uvw is reconstructed from bus current according to the sector index + * of the output voltage vector. + * @param sectorIndex Sector index of the output voltage vector. + * @param currSocA Bus current at the sample point A. + * @param currSocB Bus current at the sample point B. + * @param curr The reconstructed stator current uvw. + * @retval None. + */ +void R1CurrReconstruct(unsigned int sectorIndex, float currSocA, float currSocB, UvwAxis *curr) +{ + MCS_ASSERT_PARAM(curr != NULL); + /* Reconstructed uvw three-phase current */ + float u; + float v; + float w; + + /* + * The stator current uvw is reconstructed from bus current according to the sector index + * of the output voltage vector. + */ + switch (sectorIndex) { + case SVPWM_ANGLE_0_TO_60_DEG: /* 0 ~ 60° Voltage vector sector */ + u = currSocA; + w = -currSocB; + v = -u - w; + break; + case SVPWM_ANGLE_60_TO_120_DEG: /* 60 ~ 120° Voltage vector sector */ + v = currSocA; + w = -currSocB; + u = -v - w; + break; + case SVPWM_ANGLE_120_TO_180_DEG: /* 120 ~ 180° Voltage vector sector */ + v = currSocA; + u = -currSocB; + w = -u - v; + break; + case SVPWM_ANGLE_180_TO_240_DEG: /* 180 ~ 240° Voltage vector sector */ + w = currSocA; + u = -currSocB; + v = -u - w; + break; + case SVPWM_ANGLE_240_TO_300_DEG: /* 240 ~ 300° Voltage vector sector */ + w = currSocA; + v = -currSocB; + u = -v - w; + break; + case SVPWM_ANGLE_300_TO_360_DEG: /* 300 ~ 360° Voltage vector sector */ + u = currSocA; + v = -currSocB; + w = -u - v; + break; + default: + u = 0.0f; + v = 0.0f; + w = 0.0f; + break; + } + curr->u = u; + curr->v = v; + curr->w = w; +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/modulation/mcs_r1_svpwm.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/modulation/mcs_r1_svpwm.h new file mode 100644 index 00000000..3bc19901 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/modulation/mcs_r1_svpwm.h @@ -0,0 +1,90 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_r1_svpwm.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of Space-vector pulse-width-modulation calculations. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_MCS_R1_SVPWM_H +#define McuMagicTag_MCS_R1_SVPWM_H + +/* Includes ------------------------------------------------------------------*/ +#include "mcs_typedef.h" +#include "mcs_svpwm.h" + +/** The ADC sampling twice for one resistor motor control application, SOCA + SOCB */ +#define SOCA 0 +#define SOCB 1 +#define R1_ADC_SAMPLE_NUMS 2 + +/** + * @brief Structure of temporary variables for R1SVPWM calculation. + */ +typedef struct { + SVPWM_CALC_Handle svCalc; + float compLeft[SVPWM_COMP_VAL_TOTAL]; + float compRight[SVPWM_COMP_VAL_TOTAL]; +} R1SVPWM_CALC_Handle; +/** + * @defgroup R1_SVPWM_MODULE R1 SVPWM MODULE + * @brief The SVPWM module for R1(One Resistor) application. + * @{ + */ + +/** + * @defgroup R1_SVPWM_STRUCT R1 SVPWM STRUCT + * @brief The SVPWM module's struct definition for R1(One Resistor) application. + * @{ + */ +/* Typedef definitions -------------------------------------------------------*/ +/** + * @brief R1SVPWM struct members and parameters. + */ +typedef struct { + float voltPu; /**< Voltage per unit value. */ + float oneDivVoltPu; /**< Reciprocal of voltage unit value. */ + float sampleWindow; /**< Sampling Window */ + float samplePointShift; /**< Sampling point phase shift */ + unsigned int voltIndex; /**< Index of voltage sector. */ + unsigned int voltIndexLast; /**< Index of last voltage sector. */ + float samplePoint[R1_ADC_SAMPLE_NUMS]; /**< Sample point of twice sample. */ +} R1SVPWM_Handle; +/** + * @} + */ + +/** + * @defgroup R1_SVPWM_API R1 SVPWM API + * @brief The SVPWM module's API declaration for R1(One Resistor) application. + * @{ + */ +void R1SVPWM_Init(R1SVPWM_Handle *r1svHandle, float voltPu, float samplePointShift, float sampleWindow); +void R1SVPWM_Clear(R1SVPWM_Handle *r1svHandle); +void R1SVPWM_Exec(R1SVPWM_Handle *r1svHandle, const AlbeAxis *uAlbe, UvwAxis *dutyUvwLeft, UvwAxis *dutyUvwRight); +void R1SVPWM_PhaseShift(R1SVPWM_CALC_Handle *r1SvCalc, float sampleWindow); +void R1CurrReconstruct(unsigned int sectorIndex, float currSocA, float currSocB, UvwAxis *curr); +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_MCS_SVPWM_H */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/modulation/mcs_svpwm.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/modulation/mcs_svpwm.c new file mode 100644 index 00000000..71b595ec --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/modulation/mcs_svpwm.c @@ -0,0 +1,217 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_svpwm.c + * @author MCU Algorithm Team + * @brief This file provides function of Space-Vector Pulse-Width-Modulation(SVPWM) calculations. + */ + +#include "mcs_svpwm.h" +#include "mcs_math_const.h" +#include "mcs_assert.h" +#include "mcs_math.h" + +/* Macro definitions ---------------------------------------------------------*/ +/** + * @brief Initialzer of SVPWM handle. + * @param svHandle The SVPWM handle. + * @param voltPu The per-unit voltage value. + * @retval None. + */ +void SVPWM_Init(SVPWM_Handle *svHandle, float voltPu) +{ + MCS_ASSERT_PARAM(svHandle != NULL); + MCS_ASSERT_PARAM(voltPu > 0.0f); + svHandle->voltPu = voltPu; + svHandle->oneDivVoltPu = 1.0f / voltPu; +} + +/** + * @brief Calculate svpwm sector. + * @param svCalc The svpwm calc struct. + * @retval None. + */ +void SVPWM_SectorCalc(SVPWM_CALC_Handle *svCalc) +{ + MCS_ASSERT_PARAM(svCalc != NULL); + /* The initial sector is 0. */ + svCalc->sectorIndex = 0; + /* Three-level voltage calculation */ + svCalc->volt[SVPWM_VOLT_0] = svCalc->vBeta; + svCalc->volt[SVPWM_VOLT_1] = SQRT3_DIV_TWO * svCalc->vAlpha - 0.5f * svCalc->vBeta; + svCalc->volt[SVPWM_VOLT_2] = -SQRT3_DIV_TWO * svCalc->vAlpha - 0.5f * svCalc->vBeta; + + /* sector index calculate && calculate abs values (V) */ + if (svCalc->volt[SVPWM_VOLT_0] > 0.0f) { + svCalc->sectorIndex += SVPWM_SECTOR_ADD_1; + } else { + svCalc->volt[SVPWM_VOLT_0] = -svCalc->volt[SVPWM_VOLT_0]; + } + if (svCalc->volt[SVPWM_VOLT_1] > 0.0f) { + svCalc->sectorIndex += SVPWM_SECTOR_ADD_2; + } else { + svCalc->volt[SVPWM_VOLT_1] = -svCalc->volt[SVPWM_VOLT_1]; + } + if (svCalc->volt[SVPWM_VOLT_2] > 0.0f) { + svCalc->sectorIndex += SVPWM_SECTOR_ADD_4; + } else { + svCalc->volt[SVPWM_VOLT_2] = -svCalc->volt[SVPWM_VOLT_2]; + } +} + +/** + * @brief Calculate three comparison values: max, medium, and min.. + * @param svCalc The svpwm calc struct. + * @retval None. + */ +void SVPWM_CompareValCalc(SVPWM_CALC_Handle *svCalc) +{ + MCS_ASSERT_PARAM(svCalc != NULL); + /* Calculate the action time of the two vectors based on the sector. */ + switch (svCalc->sectorIndex) { + case SVPWM_ANGLE_0_TO_60_DEG: /* 0 ~ 60° Voltage vector sector */ + svCalc->t1 = svCalc->volt[SVPWM_VOLT_1]; + svCalc->t2 = svCalc->volt[SVPWM_VOLT_0]; + break; + case SVPWM_ANGLE_60_TO_120_DEG: /* 60 ~ 120° Voltage vector sector */ + svCalc->t1 = svCalc->volt[SVPWM_VOLT_1]; + svCalc->t2 = svCalc->volt[SVPWM_VOLT_2]; + break; + case SVPWM_ANGLE_120_TO_180_DEG: /* 120 ~ 180° Voltage vector sector */ + svCalc->t1 = svCalc->volt[SVPWM_VOLT_0]; + svCalc->t2 = svCalc->volt[SVPWM_VOLT_2]; + break; + case SVPWM_ANGLE_180_TO_240_DEG: /* 180 ~ 240° Voltage vector sector */ + svCalc->t1 = svCalc->volt[SVPWM_VOLT_0]; + svCalc->t2 = svCalc->volt[SVPWM_VOLT_1]; + break; + case SVPWM_ANGLE_240_TO_300_DEG: /* 240 ~ 300° Voltage vector sector */ + svCalc->t1 = svCalc->volt[SVPWM_VOLT_2]; + svCalc->t2 = svCalc->volt[SVPWM_VOLT_1]; + break; + case SVPWM_ANGLE_300_TO_360_DEG: /* 300 ~ 360° Voltage vector sector */ + svCalc->t1 = svCalc->volt[SVPWM_VOLT_2]; + svCalc->t2 = svCalc->volt[SVPWM_VOLT_0]; + break; + default: + break; + } + + /* The action time of two vectors is converted to three comparison values. */ + svCalc->comp[SVPWM_COMP_VAL_MIN] = (1.0f - svCalc->t1 - svCalc->t2) * 0.5f; + svCalc->comp[SVPWM_COMP_VAL_MID] = svCalc->comp[SVPWM_COMP_VAL_MIN] + svCalc->t1; + svCalc->comp[SVPWM_COMP_VAL_MAX] = svCalc->comp[SVPWM_COMP_VAL_MID] + svCalc->t2; +} + +/** + * @brief Three-phase duty cycle data index based on sector convert. + * @param svCalc The svpwm calc struct. + * @retval None. + */ +void SVPWM_IndexConvert(SVPWM_CALC_Handle *svCalc) +{ + MCS_ASSERT_PARAM(svCalc != NULL); + /* Three-phase duty cycle data index based on sector convert */ + switch (svCalc->sectorIndex) { + case SVPWM_ANGLE_0_TO_60_DEG: /* 0 ~ 60° Voltage vector sector */ + svCalc->indexU = SVPWM_COMP_VAL_MIN; + svCalc->indexV = SVPWM_COMP_VAL_MID; + svCalc->indexW = SVPWM_COMP_VAL_MAX; + break; + case SVPWM_ANGLE_60_TO_120_DEG: /* 60 ~ 120° Voltage vector sector */ + svCalc->indexU = SVPWM_COMP_VAL_MID; + svCalc->indexV = SVPWM_COMP_VAL_MIN; + svCalc->indexW = SVPWM_COMP_VAL_MAX; + break; + case SVPWM_ANGLE_120_TO_180_DEG: /* 120 ~ 180° Voltage vector sector */ + svCalc->indexU = SVPWM_COMP_VAL_MAX; + svCalc->indexV = SVPWM_COMP_VAL_MIN; + svCalc->indexW = SVPWM_COMP_VAL_MID; + break; + case SVPWM_ANGLE_180_TO_240_DEG: /* 180 ~ 240° Voltage vector sector */ + svCalc->indexU = SVPWM_COMP_VAL_MAX; + svCalc->indexV = SVPWM_COMP_VAL_MID; + svCalc->indexW = SVPWM_COMP_VAL_MIN; + break; + case SVPWM_ANGLE_240_TO_300_DEG: /* 240 ~ 300° Voltage vector sector */ + svCalc->indexU = SVPWM_COMP_VAL_MID; + svCalc->indexV = SVPWM_COMP_VAL_MAX; + svCalc->indexW = SVPWM_COMP_VAL_MIN; + break; + case SVPWM_ANGLE_300_TO_360_DEG: /* 300 ~ 360° Voltage vector sector */ + svCalc->indexU = SVPWM_COMP_VAL_MIN; + svCalc->indexV = SVPWM_COMP_VAL_MAX; + svCalc->indexW = SVPWM_COMP_VAL_MID; + break; + default: + break; + } +} + +/** + * @brief The duty cycles of PWM wave of three-phase upper switches are + * calculated in the two-phase stationary coordinate system (albe). + * @param svHandle The SVPWM struct handle. + * @param uAlbe Input voltage vector. + * @param dutyUvw Three-phase A compare value. + * @retval None. + */ +void SVPWM_Exec(const SVPWM_Handle *svHandle, const AlbeAxis *uAlbe, UvwAxis *dutyUvw) +{ + MCS_ASSERT_PARAM(svHandle != NULL); + MCS_ASSERT_PARAM(uAlbe != NULL); + MCS_ASSERT_PARAM(dutyUvw != NULL); + SVPWM_CALC_Handle svCalc; + + /* Amplitude limited */ + float voltMax = 1.0f / svHandle->oneDivVoltPu; + float amp = Sqrt(uAlbe->alpha * uAlbe->alpha + uAlbe->beta * uAlbe->beta); /* Voltage amplitude. */ + AlbeAxis uAlbeLimited; + float coeff; + if (amp < 0.001f) { + coeff = 1.0f; + } else { + coeff = voltMax / amp; /* Amplitude limit coefficient. */ + } + if (amp > voltMax) { + uAlbeLimited.alpha = uAlbe->alpha * coeff; + uAlbeLimited.beta = uAlbe->beta * coeff; + } else { + uAlbeLimited.alpha = uAlbe->alpha; + uAlbeLimited.beta = uAlbe->beta; + } + svCalc.vAlpha = uAlbeLimited.alpha * svHandle->oneDivVoltPu; + svCalc.vBeta = uAlbeLimited.beta * svHandle->oneDivVoltPu; + + /* Voltage vector sector calculation */ + SVPWM_SectorCalc(&svCalc); + /* Check whether the current sector is abnormal. */ + if (svCalc.sectorIndex < SVPWM_SECTOR_INDEX_MIN || svCalc.sectorIndex > SVPWM_SECTOR_INDEX_MAX) { + dutyUvw->u = 0.5f; + dutyUvw->v = 0.5f; + dutyUvw->w = 0.5f; + return; + } + /* Calculate three comparison values: max, medium, and min. */ + SVPWM_CompareValCalc(&svCalc); + /* Three-phase duty cycle data index based on sector convert */ + SVPWM_IndexConvert(&svCalc); + /* Output UVW three-phase duty cycle */ + dutyUvw->u = svCalc.comp[svCalc.indexU]; + dutyUvw->v = svCalc.comp[svCalc.indexV]; + dutyUvw->w = svCalc.comp[svCalc.indexW]; +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/modulation/mcs_svpwm.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/modulation/mcs_svpwm.h new file mode 100644 index 00000000..fe636fa5 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/modulation/mcs_svpwm.h @@ -0,0 +1,117 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_svpwm.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of Space-Vector Pulse-Width-Modulation(SVPWM) calculations. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_MCS_SVPWM_H +#define McuMagicTag_MCS_SVPWM_H + +/* Includes ------------------------------------------------------------------*/ +#include "mcs_typedef.h" + +/** Voltage vector sector */ +#define SVPWM_ANGLE_0_TO_60_DEG 3 +#define SVPWM_ANGLE_60_TO_120_DEG 1 +#define SVPWM_ANGLE_120_TO_180_DEG 5 +#define SVPWM_ANGLE_180_TO_240_DEG 4 +#define SVPWM_ANGLE_240_TO_300_DEG 6 +#define SVPWM_ANGLE_300_TO_360_DEG 2 + +/** The U-V-W phase compare value's index of APT timers. */ +#define SVPWM_COMP_VAL_MAX 2 +#define SVPWM_COMP_VAL_MID 1 +#define SVPWM_COMP_VAL_MIN 0 +#define SVPWM_COMP_VAL_TOTAL 3 + +/** The three voltage level to compare, for sector index decision. */ +#define SVPWM_VOLT_0 0 +#define SVPWM_VOLT_1 1 +#define SVPWM_VOLT_2 2 +#define SVPWM_VOLT_TOTAL 3 + +/** Sector index calculate: N = A + 2B + 4C */ +#define SVPWM_SECTOR_ADD_1 1 +#define SVPWM_SECTOR_ADD_2 2 +#define SVPWM_SECTOR_ADD_4 4 + +#define SVPWM_SECTOR_INDEX_MIN 1 +#define SVPWM_SECTOR_INDEX_MAX 6 + +/** + * @defgroup SVPWM_MODULE SVPWM MODULE + * @brief The Space-Vector Pulse-Width-Modulation(SVPWM) module. + * @{ + */ + +/** + * @defgroup SVPWM_STRUCT SVPWM STRUCT + * @brief The SVPWM module's data struct definition. + * @{ + */ + +/* Typedef definitions -------------------------------------------------------*/ +/** + * @brief SVPWM struct members and parameters. + */ +typedef struct { + float voltPu; /**< Voltage per unit value. */ + float oneDivVoltPu; /**< Reciprocal of voltage unit value. */ +} SVPWM_Handle; + +/** + * @brief Structure of temporary variables for SVPWM calculation. + */ +typedef struct { + float vAlpha; /**< Voltage vector. */ + float vBeta; /**< Voltage vector. */ + float t1; /**< T1 are the action times of the sequential action vectors. */ + float t2; /**< T2 are the action times of the sequential action vectors. */ + unsigned short indexU; /**< U-phase duty cycle conversion index */ + unsigned short indexV; /**< V-phase duty cycle conversion index */ + unsigned short indexW; /**< W-phase duty cycle conversion index */ + unsigned int sectorIndex; /**< Sector index */ + float volt[SVPWM_VOLT_TOTAL]; /**< temporary voltage to calculate sector index */ + float comp[SVPWM_COMP_VAL_TOTAL]; /**< Duty cycle corresponding to the comparison value */ +} SVPWM_CALC_Handle; + +/** + * @} + */ + +/** + * @defgroup SVPWM_API SVPWM API + * @brief The SVPWM module's API declaration. + * @{ + */ +void SVPWM_Init(SVPWM_Handle *svHandle, float voltPu); +void SVPWM_SectorCalc(SVPWM_CALC_Handle *svCalc); +void SVPWM_CompareValCalc(SVPWM_CALC_Handle *svCalc); +void SVPWM_IndexConvert(SVPWM_CALC_Handle *svCalc); +void SVPWM_Exec(const SVPWM_Handle *svHandle, const AlbeAxis *uAlbe, UvwAxis *dutyUvw); +/** + * @} + */ + +/** + * @} + */ + +#endif /* McuMagicTag_MCS_SVPWM_H */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/observer/mcs_fosmo.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/observer/mcs_fosmo.c new file mode 100644 index 00000000..690bbb95 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/observer/mcs_fosmo.c @@ -0,0 +1,199 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_fosmo.c + * @author MCU Algorithm Team + * @brief This file provides functions of position sliding mode observer (SMO) module. + */ + +#include "mcs_fosmo.h" +#include "mcs_math_const.h" +#include "mcs_math.h" +#include "mcs_assert.h" + + +void FOSMO_Init(FOSMO_Handle *fosmo, const FOSMO_Param foSmoParam, const MOTOR_Param mtrParam, float ts) +{ + MCS_ASSERT_PARAM(fosmo != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + /* time sample, unit: s */ + fosmo->ts = ts; + /* filter coefficient */ + fosmo->a1 = 1.0f - (fosmo->ts * mtrParam.mtrRs / mtrParam.mtrLd); + fosmo->a2 = fosmo->ts / mtrParam.mtrLd; + + fosmo->kSmo = foSmoParam.gain; + fosmo->lambda = foSmoParam.lambda; /* SMO coefficient of cut-off frequency = lambda * we, unit: rad/2. */ + /* smo angle filcompAngle */ + fosmo->filCompAngle = Atan2(1.0f, 1.0f / fosmo->lambda); + fosmo->pllBdw = foSmoParam.pllBdw; + fosmo->fcLpf = foSmoParam.fcLpf; + + FOSMO_Clear(fosmo); + + fosmo->emfLpfMinFreq = foSmoParam.fcEmf; /* The minimum cutoff frequency of the back EMF filter is 2.0. */ + + PLL_Init(&fosmo->pll, fosmo->ts, fosmo->pllBdw); // bdw + + /* low pass filter cutoff freqency for speed estimation is 40Hz */ + FOLPF_Init(&fosmo->spdFilter, fosmo->ts, fosmo->fcLpf); +} + +/** + * @brief Set parameters for fosmo. + * @param fosmo The SMO handle. + * @param gain The smo gain. + * @param pllBdw The PLL bandwidth (Hz). + * @param fc The first-order low pass filter cut-off frequency. + * @retval None. + */ +void FOSMO_ParamUpdate(FOSMO_Handle *fosmo, float gain, float pllBdw, float fc) +{ + MCS_ASSERT_PARAM(fosmo != NULL); + MCS_ASSERT_PARAM(pllBdw > 0.0f); + MCS_ASSERT_PARAM(fc > 0.0f); + + fosmo->kSmo = gain; + fosmo->fcLpf = fc; + fosmo->pllBdw = pllBdw; + + /* Set PI parameters with given bandwidth */ + float we = DOUBLE_PI * pllBdw; + fosmo->pll.pi.kp = 2.0f * we; + fosmo->pll.pi.ki = we * we; + + /* Set LPF parameters with given fc */ + fosmo->spdFilter.fc = fc; + float wcTs = DOUBLE_PI * fc * fosmo->spdFilter.ts; + fosmo->spdFilter.a1 = 1.0f / (1.0f + wcTs); /* wcTs > 0 */ + fosmo->spdFilter.b1 = 1.0f - fosmo->spdFilter.a1; +} + + +/** + * @brief Clear historical values of SMO handle. + * @param fosmo SMO struct handle. + * @retval None. + */ +void FOSMO_Clear(FOSMO_Handle *fosmo) +{ + MCS_ASSERT_PARAM(fosmo != NULL); + /* Clear historical values of SMO handle */ + fosmo->ialbeEst.alpha = 0.0f; + fosmo->ialbeEst.beta = 0.0f; + fosmo->ialbeEstLast.alpha = 0.0f; + fosmo->ialbeEstLast.beta = 0.0f; + fosmo->emfEstUnFil.alpha = 0.0f; + fosmo->emfEstUnFil.beta = 0.0f; + fosmo->emfEstFil.alpha = 0.0f; + fosmo->emfEstFil.beta = 0.0f; + /* Clear historical values of PLL controller */ + PLL_Clear(&fosmo->pll); + /* Clear historical values of first-order fosmo speed filter */ + FOLPF_Clear(&fosmo->spdFilter); +} + +/** + * @brief Calculation method of first-order SMO. + * @param fosmo SMO struct handle. + * @param ialbeFbk Feedback currents in the alpha-beta coordinate (A). + * @param valbeRef FOC output voltages in alpha-beta coordinate (V). + * @param refHz The reference frequency (Hz). + * @retval None. + */ +void FOSMO_Exec(FOSMO_Handle *fosmo, const AlbeAxis *ialbeFbk, const AlbeAxis *valbeRef, float refHz) +{ + MCS_ASSERT_PARAM(fosmo != NULL); + MCS_ASSERT_PARAM(ialbeFbk != NULL); + MCS_ASSERT_PARAM(valbeRef != NULL); + float err; + float wcTs; + float fcAbs = Abs(refHz); + float filCompAngle; /* Compensation angle (rad) */ + float currAlpha = fosmo->ialbeEstLast.alpha; + float currBeta = fosmo->ialbeEstLast.beta; + float emfUnAlpha = fosmo->emfEstUnFil.alpha; + float emfUnBeta = fosmo->emfEstUnFil.beta; + /* Alpha beta current observation value */ + fosmo->ialbeEst.alpha = + (fosmo->a1 * currAlpha) + (fosmo->a2 * (valbeRef->alpha - emfUnAlpha)); + fosmo->ialbeEst.beta = + (fosmo->a1 * currBeta) + (fosmo->a2 * (valbeRef->beta - emfUnBeta)); + + fosmo->ialbeEstLast.alpha = fosmo->ialbeEst.alpha; + fosmo->ialbeEstLast.beta = fosmo->ialbeEst.beta; + + /* Estmated back EMF by sign function. */ + err = fosmo->ialbeEst.alpha - ialbeFbk->alpha; + fosmo->emfEstUnFil.alpha = fosmo->kSmo * ((err > 0.0f) ? 1.0f : -1.0f); + err = fosmo->ialbeEst.beta - ialbeFbk->beta; + fosmo->emfEstUnFil.beta = fosmo->kSmo * ((err > 0.0f) ? 1.0f : -1.0f); + + /* Estmated back EMF is filtered by first-order LPF. */ + if (fcAbs <= fosmo->emfLpfMinFreq) { + wcTs = fosmo->emfLpfMinFreq * DOUBLE_PI * fosmo->ts * fosmo->lambda; + } else { + wcTs = fcAbs * DOUBLE_PI * fosmo->ts * fosmo->lambda; + } + fosmo->emfEstFil.alpha = (fosmo->emfEstFil.alpha + wcTs * fosmo->emfEstUnFil.alpha) / (wcTs + 1.0f); + fosmo->emfEstFil.beta = (fosmo->emfEstFil.beta + wcTs * fosmo->emfEstUnFil.beta) / (wcTs + 1.0f); + + /* Get phase angle and frequency from BEMF by PLL. */ + PLL_Exec(&fosmo->pll, -fosmo->emfEstFil.alpha, fosmo->emfEstFil.beta); + + /* Compensation phase lag caused by the LPF. */ + filCompAngle = (refHz > 0.0f) ? (fosmo->filCompAngle) : AngleSub(ONE_PI, fosmo->filCompAngle); + fosmo->elecAngle = Mod(fosmo->pll.angle + filCompAngle, DOUBLE_PI); + if (fosmo->elecAngle > ONE_PI) { + fosmo->elecAngle -= DOUBLE_PI; + } + if (fosmo->elecAngle < -ONE_PI) { + fosmo->elecAngle += DOUBLE_PI; + } + /* Estmated speed is filtered by first-order LPF. */ + fosmo->spdEst = FOLPF_Exec(&fosmo->spdFilter, fosmo->pll.freq); +} + +/** + * @brief Set ts for first-order SMO. + * @param fosmo SMO struct handle. + * @param ts Control period (s). + * @retval None. + */ +void FOSMO_SetTs(FOSMO_Handle *fosmo, float ts) +{ + MCS_ASSERT_PARAM(fosmo != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + fosmo->ts = ts; + /* Set PLL ts and filter ts. */ + PLL_SetTs(&fosmo->pll, ts); + FOLPF_SetTs(&fosmo->spdFilter, ts); +} + +/** + * @brief Set coefficient of cut-off frequency(lambda * we rad/2) for first-order SMO. + * @param fosmo SMO struct handle. + * @param lambda SMO filter coefficient. + * @retval None. + */ +void FOSMO_SetLambda(FOSMO_Handle *fosmo, float lambda) +{ + MCS_ASSERT_PARAM(fosmo != NULL); + MCS_ASSERT_PARAM(lambda > 0.0f); + fosmo->lambda = lambda; + fosmo->filCompAngle = Atan2(1.0f, 1.0f / fosmo->lambda); +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/observer/mcs_fosmo.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/observer/mcs_fosmo.h new file mode 100644 index 00000000..350842e2 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/observer/mcs_fosmo.h @@ -0,0 +1,106 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_fosmo.h + * @author MCU Algorithm Team + * @brief Sliding-mode observer (SMO) for motor position acquisition. + * This file provides position SMO and Phase-locked loop (PLL) declaration for motor control. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_FOSMO_H +#define McuMagicTag_MCS_FOSMO_H + +/* Includes ------------------------------------------------------------------------------------ */ +#include "mcs_mtr_param.h" +#include "mcs_typedef.h" +#include "mcs_pll.h" +#include "mcs_filter.h" + +/** + * @defgroup FOSMO_MODULE FOSMO MODULE + * @brief The First Order Sliding Mode Observer module. + * @{ + */ + +/** + * @defgroup FOSMO_STRUCT FOSMO STRUCT + * @brief The First Order Sliding Mode Observer's data struct definition. + * @{ + */ +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief Position SMO struct members and parameters. + */ +typedef struct { + float ts; /**< SMO control period (s). */ + float a1; /**< Coefficient of differential equation. */ + float a2; /**< Coefficient of differential equation. */ + float kSmo; /**< SMO gain. */ + float lambda; /**< SMO coefficient of cut-off frequency, its value = lambda * we. */ + float emfLpfMinFreq; /**< The minimum cut-off frequency of back-EMF filter. */ + float pllBdw; /**< The PLL bandwidth. */ + float fcLpf; /**< The cut-off frequency of First-order LPF for speed (Hz). */ + float filCompAngle; /**< Compensation angle (atan(1/lambda)) for the back-EMF filter. */ + float elecAngle; /**< SMO estimated electronic angle (rad). */ + float spdEst; /**< SMO estimated electronic speed (Hz). */ + AlbeAxis emfEstUnFil; /**< Estimated back-EMF in the alpha-beta coordinate by differential equation. */ + AlbeAxis ialbeEst; /**< SMO estimated currents in the alpha-beta coordinate. */ + AlbeAxis ialbeEstLast; /**< SMO history values of estimated currents in the alpha-beta coordinate. */ + AlbeAxis emfEstFil; /**< SMO estimated back-EMF in the alpha-beta coordinate. */ + PLL_Handle pll; /**< PLL handle. */ + FOFLT_Handle spdFilter; /**< First-order LPF for speed. */ +} FOSMO_Handle; + +/** + * @} + */ +typedef struct { + float gain; + float lambda; + float fcEmf; + float pllBdw; + float fcLpf; +} FOSMO_Param; + + +/** + * @defgroup FOSMO_API FOSMO API + * @brief The First Order Sliding Mode Observer's API declaration. + * @{ + */ + +void FOSMO_Init(FOSMO_Handle *fosmo, const FOSMO_Param foSmoParam, const MOTOR_Param mtrParam, float ts); + +void FOSMO_Exec(FOSMO_Handle *fosmo, const AlbeAxis *ialbeFbk, const AlbeAxis *valbeRef, float refHz); + +void FOSMO_ParamUpdate(FOSMO_Handle *fosmo, float gain, float pllBdw, float fc); + +void FOSMO_Clear(FOSMO_Handle *fosmo); + +void FOSMO_SetTs(FOSMO_Handle *fosmo, float ts); + +void FOSMO_SetLambda(FOSMO_Handle *fosmo, float lambda); +/** + * @} + */ + +/** + * @} + */ + +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/pfc/pfc_curr_ctrl.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/pfc/pfc_curr_ctrl.c new file mode 100644 index 00000000..3eda2abd --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/pfc/pfc_curr_ctrl.c @@ -0,0 +1,50 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pfc_curr_ctrl.c + * @author MCU Algorithm Team + * @brief This file provides function of power factor correction(PFC) current control + */ +#include "pfc_curr_ctrl.h" +#include "mcs_assert.h" + + +/** + * @brief Clear historical values of power factor correction(PFC) current controller. + * @param currCtrl PFC current control structure + * @retval None. + */ +void PFC_CurrCtrlClear(PFC_CURRCTRL_Handle *currCtrl) +{ + MCS_ASSERT_PARAM(currCtrl != NULL); + currCtrl->currPiCtrl.differ = 0.0f; + currCtrl->currPiCtrl.integral = 0.0f; +} + +/** + * @brief Simplified power factor correction(PFC) current controller PI calculation. + * @param currCtrl PFC current control structure + * @retval None. + */ +void PFC_CurrCtrlExec(PFC_CURRCTRL_Handle *currCtrl) +{ + MCS_ASSERT_PARAM(currCtrl != NULL); + /* Calculate the current error of power factor correction(PFC). */ + currCtrl->currPiCtrl.error = currCtrl->currRef - currCtrl->unitCurrFdbk; + /* Calculation the output pwm duty of power factor correction(PFC) current. */ + currCtrl->pwmDuty = PI_Exec(&currCtrl->currPiCtrl); +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/pfc/pfc_curr_ctrl.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/pfc/pfc_curr_ctrl.h new file mode 100644 index 00000000..d7ed3d9f --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/pfc/pfc_curr_ctrl.h @@ -0,0 +1,79 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pfc_curr_ctrl.h + * @author MCU Algorithm Team + * @brief Current loop control. This file provides function of power factor correction(PFC) current control + */ +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_PFC_CURR_CTRL_H +#define McuMagicTag_PFC_CURR_CTRL_H + +/* Includes ------------------------------------------------------------------------------------ */ +#include "mcs_pid_ctrl.h" + +/** + * @defgroup PFC_CURRENT_CONTROLLER PFC_CURRENT CONTROLLER MODULE + * @brief The current controller function. + * @{ + */ + +/** + * @defgroup PFC_CURRENT_CONTROLLER_STRUCT PFC_CURRENT CONTROLLER STRUCT + * @brief The current controller's data structure definition. + * @{ + */ + +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief current Controller Struct members and parameters. + */ +typedef struct { + float currRef; /* < current loop control reference current(A) */ + float currFdbk; /* < current loop control feedback current(A) */ + float unitCurrFdbk; /* < current loop control feedback unitary current */ + float maxCurrFdbk; /* < current loop control max feedback current(A) */ + float startCurrFdbk; /* < current loop control start feedback current(A) */ + float stopCurrFdbk; /* < current loop control stop feedback current(A) */ + float pwmDuty; /* < current loop control pulse width modulation(PWM) duty */ + float pwmOut; /* < current loop control PWM final output (output = cmpst + duty) */ + float rectVoltFdbk; /* < current loop control rectified feedback voltage(V) */ + float unitRectVoltFdbk; /* < current loop control rectified feedback unitary voltage */ + float compensation; + PID_Handle currPiCtrl; /* < current loop controller define */ +} PFC_CURRCTRL_Handle; +/** + * @} + */ + +/** + * @defgroup PFC_CURRENT_CONTROLLER_API PFC_CURRENT CONTROLLER API + * @brief The current controller's API declaration. + * @{ + */ + +void PFC_CurrCtrlClear(PFC_CURRCTRL_Handle *currCtrl); + +void PFC_CurrCtrlExec(PFC_CURRCTRL_Handle *currCtrl); +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_PFC_CURR_CTRL_H */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/pfc/pfc_volt_ctrl.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/pfc/pfc_volt_ctrl.c new file mode 100644 index 00000000..1fdf5dfd --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/pfc/pfc_volt_ctrl.c @@ -0,0 +1,51 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pfc_volt_ctrl.c + * @author MCU Algorithm Team + * @brief This file provides function of power factor correction(PFC) voltage control + */ +#include "pfc_volt_ctrl.h" +#include "mcs_math.h" +#include "mcs_assert.h" + + +/** + * @brief Clear historical values of power factor correction(PFC) voltage controller. + * @param voltCtrl PFC voltage control structure + * @retval None. + */ +void PFC_VoltCtrlClear(PFC_VOLTCTRL_Handle *voltCtrl) +{ + MCS_ASSERT_PARAM(voltCtrl != NULL); + voltCtrl->voltPiCtrl.differ = 0.0f; + voltCtrl->voltPiCtrl.integral = 0.0f; +} + +/** + * @brief Simplified power factor correction(PFC) voltage controller PI calculation. + * @param voltCtrl PFC voltage control structure + * @retval None. + */ +void PFC_VoltCtrlExec(PFC_VOLTCTRL_Handle *voltCtrl) +{ + MCS_ASSERT_PARAM(voltCtrl != NULL); + /* Calculate the voltage error of power factor correction(PFC). */ + voltCtrl->voltPiCtrl.error = voltCtrl->uniVoltRef - voltCtrl->unitVoltFdbk; + /* Calculation the voltage loop control output of power factor correction(PFC). */ + voltCtrl->voltOut = PI_Exec(&voltCtrl->voltPiCtrl); +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/pfc/pfc_volt_ctrl.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/pfc/pfc_volt_ctrl.h new file mode 100644 index 00000000..b1f6e94d --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/pfc/pfc_volt_ctrl.h @@ -0,0 +1,72 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file pfc_volt_ctrl.h + * @author MCU Algorithm Team + * @brief Voltage loop control. This file provides function of power factor correction(PFC) voltage control + */ +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_PFC_VOLT_CTRL_H +#define McuMagicTag_PFC_VOLT_CTRL_H + +/* Includes ------------------------------------------------------------------------------------ */ +#include "mcs_pid_ctrl.h" + +/** + * @defgroup VOLTAGE_CONTROLLER VOLTAGE CONTROLLER MODULE + * @brief The voltage controller function. + * @{ + */ + +/** + * @defgroup VOLTAGE_CONTROLLER_STRUCT VOLTAGE CONTROLLER STRUCT + * @brief The voltage controller's data structure definition. + * @{ + */ + +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief Voltage controller struct. + */ +typedef struct { + float uniVoltRef; /* < voltage loop control unitary reference voltage(V) */ + float voltFdbk; /* < voltage loop control feedback voltage(V) */ + float unitVoltFdbk; /* < voltage loop control feedback unitary voltage */ + float startVolt; /* < voltage loop control start voltage(V) */ + float voltOut; /* < voltage loop control output */ + PID_Handle voltPiCtrl; /* < voltage loop controller define */ +} PFC_VOLTCTRL_Handle; +/** + * @} + */ + +/** + * @defgroup VOLTAGE_CONTROLLER_API VOLTAGE CONTROLLER API + * @brief The voltage controller's API declaration. + * @{ + */ +void PFC_VoltCtrlClear(PFC_VOLTCTRL_Handle *voltCtrl); + +void PFC_VoltCtrlExec(PFC_VOLTCTRL_Handle *voltCtrl); +/** + * @} + */ + +/** + * @} + */ +#endif /* McuMagicTag_PFC_VOLT_CTRL_H */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/pid_controller/mcs_pid_ctrl.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/pid_controller/mcs_pid_ctrl.c new file mode 100644 index 00000000..f780fd62 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/pid_controller/mcs_pid_ctrl.c @@ -0,0 +1,199 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_pid_ctrl.c + * @author MCU Algorithm Team + * @brief This file provides functions of general PID controller + */ + +#include "mcs_pid_ctrl.h" +#include "mcs_math.h" +#include "mcs_assert.h" + +/** + * @brief Reset all member variables of PID controller to zero. + * @param piHandle PID controller struct handle. + * @retval None. + */ +void PID_Reset(PID_Handle *pidHandle) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + /* Reset the PID parameter. */ + pidHandle->kp = 0.0f; + pidHandle->ki = 0.0f; + pidHandle->kd = 0.0f; + pidHandle->ns = 0.0f; + pidHandle->ka = 0.0f; + pidHandle->ts = 0.0f; + /* Reset the Limiting Value. */ + pidHandle->upperLimit = 0.0f; + pidHandle->lowerLimit = 0.0f; + + PID_Clear(pidHandle); +} + +/** + * @brief Clear historical values of PID controller. + * @param pidHandle PID controller struct handle. + * @retval None. + */ +void PID_Clear(PID_Handle *pidHandle) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + /* Clear historical values of PID controller. */ + pidHandle->differ = 0.0f; + pidHandle->integral = 0.0f; + pidHandle->saturation = 0.0f; + pidHandle->feedforward = 0.0f; + pidHandle->error = 0.0f; + pidHandle->errorLast = 0.0f; +} + +/** + * @brief Execute simplified PI controller calculation, static clamping, no feedforward. + * @param pidHandle PI controller struct handle. + * @retval PI control output. + */ +float PI_Exec(PID_Handle *pidHandle) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + /* Proportional Item */ + float p = pidHandle->kp * pidHandle->error; + + /* Integral Item */ + float i = pidHandle->ki * pidHandle->ts * pidHandle->error + pidHandle->integral; + i = Clamp(i, pidHandle->upperLimit, pidHandle->lowerLimit); + pidHandle->integral = i; + + /* static clamping and output calculaiton */ + float val = p + i + pidHandle->feedforward; + float out = Clamp(val, pidHandle->upperLimit, pidHandle->lowerLimit); + + return out; +} + +/** + * @brief Execute PID controller calculation. dynamic clamping, feedforward compensataion + * @param pidHandle PID controller struct handle. + * @retval PID control output. + */ +float PID_Exec(PID_Handle *pidHandle) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + /* Proportional Item */ + float error = pidHandle->error; + float errorLast = pidHandle->errorLast; + float ts = pidHandle->ts; + + float p = pidHandle->kp * error; + + /* Integral Item */ + float i = pidHandle->ki * ts * (error - pidHandle->ka * pidHandle->saturation) + pidHandle->integral; + i = Clamp(i, Max(0.0f, pidHandle->upperLimit), Min(0.0f, pidHandle->lowerLimit)); + pidHandle->integral = i; + + /* Differential Item */ + float kd = pidHandle->kd; + float ns = pidHandle->ns; + float d = 1.0f / (1.0f + ts * ns) * (kd * ns * error - kd * ns * errorLast + pidHandle->differ); + + pidHandle->errorLast = pidHandle->error; + pidHandle->differ = d; + + /* Output value update and saturation value calculation */ + float val = p + i + d + pidHandle->feedforward; + float out = Clamp(val, pidHandle->upperLimit, pidHandle->lowerLimit); + pidHandle->saturation = val - out; + + return out; +} + +/** + * @brief Set the proportional parameter kp of PID controller. + * @param pidHandle PID controller struct handle. + * @param kp The proportional parameter. + * @retval None. + */ +void PID_SetKp(PID_Handle *pidHandle, float kp) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + pidHandle->kp = kp; +} + +/** + * @brief Set the integral parameter ki of PID controller. + * @param pidHandle PID controller struct handle. + * @param ki The integral parameter. + * @retval None. + */ +void PID_SetKi(PID_Handle *pidHandle, float ki) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + pidHandle->ki = ki; +} + +/** + * @brief Set the derivative parameter kd of PID controller. + * @param pidHandle PID controller struct handle. + * @param kd The derivative parameter. + * @retval None. + */ +void PID_SetKd(PID_Handle *pidHandle, float kd) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + pidHandle->kd = kd; +} + +/** + * @brief Set the filter parameter of the differential item parameter ns of PID controller. + * @param pidHandle PID controller struct handle. + * @param ns Filter parameter of the differential item. + * @retval None. + */ +void PID_SetNs(PID_Handle *pidHandle, float ns) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + MCS_ASSERT_PARAM(ns >= 0.0f); + pidHandle->ns = ns; +} + +/** + * @brief Set the ts of PID controller. + * @param pidHandle PID controller struct handle. + * @param ts Control period (s). + * @retval None. + */ +void PID_SetTs(PID_Handle *pidHandle, float ts) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + MCS_ASSERT_PARAM(ts >= 0.0f); + pidHandle->ts = ts; +} + +/** + * @brief Set the derivative parameter upper and lower limit of PID controller. + * @param pidHandle PID controller struct handle. + * @param kd The derivative parameter. + * @retval None. + */ +void PID_SetLimit(PID_Handle *pidHandle, float limit) +{ + MCS_ASSERT_PARAM(pidHandle != NULL); + MCS_ASSERT_PARAM(limit >= 0.0f); + pidHandle->upperLimit = limit; + pidHandle->lowerLimit = -limit; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/pid_controller/mcs_pid_ctrl.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/pid_controller/mcs_pid_ctrl.h new file mode 100644 index 00000000..65185097 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/pid_controller/mcs_pid_ctrl.h @@ -0,0 +1,105 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_pid_ctrl.h + * @author MCU Algorithm Team + * @brief General PI controller. + * This file provides functions declaration of the PI controller module. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_PID_CTRL_H +#define McuMagicTag_MCS_PID_CTRL_H + +/** + * @defgroup PID PID + * @brief The PID module. + * @{ + */ + +/** + * @defgroup PID_STRUCT PID STRUCT + * @brief The PID control structure definition. + * @{ + */ +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief General PID Controller struct members and parameters. + */ +typedef struct { + float error; /**< Error feedback. */ + float errorLast; /**< Error feedback history values. */ + float feedforward; /**< Feedforward item. */ + float integral; /**< Integral item. */ + float saturation; /**< Saturation value of the integral item. */ + float differ; /**< Differential item. */ + float kp; /**< Gained of the proportional item. */ + float ki; /**< Gained of the integral item, not multiplied by control period. */ + float kd; /**< Gained of the differential item. */ + float ns; /**< Filter parameter of the differential item. */ + float ka; /**< Gained of the saturation item. */ + float ts; /**< Control period (s) */ + float upperLimit; /**< The upper limit value of the pid comp output. */ + float lowerLimit; /**< The lower limit value of the pid output. */ +} PID_Handle; + +typedef struct { + float kp; + float ki; + float upperLim; + float lowerLim; +} PI_Param; + +typedef struct { + float kp; + float ki; + float kd; + float ns; /**< Filter parameter of the differential item. */ + float ka; /**< Gained of the saturation item. */ + float saturation; + float upperLim; + float lowerLim; +} PID_Param; +/** + * @} + */ + +/** + * @defgroup PID_API PID API + * @brief The PID control API definitions. + * @{ + */ +void PID_Reset(PID_Handle *pidHandle); +void PID_Clear(PID_Handle *pidHandle); +float PI_Exec(PID_Handle *pidHandle); +float PID_Exec(PID_Handle *pidHandle); + +void PID_SetKp(PID_Handle *pidHandle, float kp); +void PID_SetKi(PID_Handle *pidHandle, float ki); +void PID_SetKd(PID_Handle *pidHandle, float kd); +void PID_SetNs(PID_Handle *pidHandle, float ns); +void PID_SetTs(PID_Handle *pidHandle, float ts); +void PID_SetLimit(PID_Handle *pidHandle, float limit); +/** + * @} + */ + +/** + * @} + */ + +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/power/mcs_power_mgmt.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/power/mcs_power_mgmt.c new file mode 100644 index 00000000..a15b3f66 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/power/mcs_power_mgmt.c @@ -0,0 +1,71 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_power_mgmt.c + * @author MCU Algorithm Team + * @brief This file provides functions of motor average power management. + */ + + +#include "mcs_power_mgmt.h" +#include "mcs_math.h" +#include "mcs_assert.h" + +/** + * @brief Init motor power management. + * @param avgPower Pointer of motor power handle. + * @param vdqRef Pointer of vdqRef handle. + * @param idqFbk Pointer of idqFbk handle. + * @retval None. + */ +void MotorPowerInit(POWER_Handle *avgPower, DqAxis *vdqRef, DqAxis *idqFbk) +{ + MCS_ASSERT_PARAM(avgPower != NULL); + MCS_ASSERT_PARAM(vdqRef != NULL); + MCS_ASSERT_PARAM(idqFbk != NULL); + /* Initialization. */ + avgPower->avgPower = 0.0f; + /* Initialization. */ + avgPower->vdqRef = vdqRef; + avgPower->idqFbk = idqFbk; +} + +/** + * @brief Power result value. + * @param avgPower Pointer of motor power handle. + * @retval Motor power value (w). + */ +float MotorPowerCalc(POWER_Handle *avgPower) +{ + MCS_ASSERT_PARAM(avgPower != NULL); + /* Calculate average power. */ + float activePower = 1.5f * (avgPower->idqFbk->d * avgPower->vdqRef->d + avgPower->idqFbk->q * avgPower->vdqRef->q); + avgPower->avgPower = activePower; + return activePower; +} + +/** + * @brief Clear motor power history value. + * @param avgPower Pointer of motor power handle. + * @retval None. + */ +void MotorPowerClear(POWER_Handle *avgPower) +{ + MCS_ASSERT_PARAM(avgPower != NULL); + /* Clear history value. */ + avgPower->avgPower = 0.0f; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/power/mcs_power_mgmt.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/power/mcs_power_mgmt.h new file mode 100644 index 00000000..1133c06b --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/power/mcs_power_mgmt.h @@ -0,0 +1,44 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_power_mgmt.h + * @author MCU Algorithm Team + * @brief This file provides functions of motor average power management. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_POWER_MGMT_H +#define McuMagicTag_MCS_POWER_MGMT_H + +#include "mcs_typedef.h" + +/* Typedef definitions ------------------------------------------------------------------------- */ + +typedef struct { + float avgPower; /**< Average power. */ + DqAxis *idqFbk; /**< Current value of d, q axis. */ + DqAxis *vdqRef; /**< Voltage value of d, q axis. */ +} POWER_Handle; + + +void MotorPowerInit(POWER_Handle *avgPower, DqAxis *vdqRef, DqAxis *idqFbk); + +float MotorPowerCalc(POWER_Handle *avgPower); + +void MotorPowerClear(POWER_Handle *avgPower); + +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/protection/mcs_openphs_det.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/protection/mcs_openphs_det.c new file mode 100644 index 00000000..2c195eba --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/protection/mcs_openphs_det.c @@ -0,0 +1,87 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_openphs_det.c + * @author MCU Algorithm Team + * @brief This file contains self-check open phase fault detection function data struct and api declaration. + */ + + +#include "mcs_openphs_det.h" +#include "mcs_assert.h" + + +/** + * @brief Open phase detection initialization. + * @param opp Open phase detection handle. + * @param minOpenPhsCurr Minimum current for open-phase detection (A). + * @retval None. + */ +void OPD_Init(OPD_Handle *opd, float minOpenPhsCurr) +{ + MCS_ASSERT_PARAM(opd != NULL); + MCS_ASSERT_PARAM(minOpenPhsCurr > 0.0f); + /* Minimum current for open-phase detection (A). */ + opd->minOpenPhsCurr = minOpenPhsCurr; + /* No phase open. */ + opd->isOpenPhsU = 0; + opd->isOpenPhsV = 0; + opd->isOpenPhsW = 0; +} + + +/** + * @brief Open phase detection execution. + * @param opd Open phase detection handle. + * @param iuvw Phase current feedback values (A). + * @retval Whether the motor is open phase, ture: open phase, 0: no open phase. + */ +bool OPD_Exec(OPD_Handle *opd, const float *iuvw) +{ + MCS_ASSERT_PARAM(opd != NULL); + MCS_ASSERT_PARAM(iuvw != NULL); + float minCurr = opd->minOpenPhsCurr; + /* Open phase detection for phase U */ + if (iuvw[OPD_V_U] <= minCurr && iuvw[OPD_W_U] <= minCurr) { /* 4th step curr */ + opd->isOpenPhsU = true; + } + /* Open phase detection for phase V */ + if (iuvw[OPD_U_V] <= minCurr && iuvw[OPD_W_V] <= minCurr) { /* 2th step curr */ + opd->isOpenPhsV = true; + } + + /* Open phase detection for phase W */ + if (iuvw[OPD_V_W] <= minCurr && iuvw[OPD_U_W] <= minCurr) { /* 2th ,4th step curr */ + opd->isOpenPhsW = true; + } + + return (opd->isOpenPhsU || opd->isOpenPhsV || opd->isOpenPhsW); +} + + +/** + * @brief Clear Open phase history value. + * @param opd Open phase detection handle. + * @retval None. + */ +void OPD_Clear(OPD_Handle *opd) +{ + MCS_ASSERT_PARAM(opd != NULL); + opd->isOpenPhsU = 0; + opd->isOpenPhsV = 0; + opd->isOpenPhsW = 0; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/protection/mcs_openphs_det.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/protection/mcs_openphs_det.h new file mode 100644 index 00000000..771953d8 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/protection/mcs_openphs_det.h @@ -0,0 +1,51 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_openphs_det.h + * @author MCU Algorithm Team + * @brief This file contains self-check open phase fault detection function data struct and api declaration. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_MCS_OPENPHS_DET_H +#define McuMagicTag_MCS_OPENPHS_DET_H + +#include "typedefs.h" + +typedef enum { + OPD_U_V = 0, + OPD_V_U, + OPD_V_W, + OPD_W_V, + OPD_W_U, + OPD_U_W, + OPD_END +} OPD_Index; + +typedef struct { + float minOpenPhsCurr; /* Minimum current for open-phase detection (A). */ + bool isOpenPhsU; + bool isOpenPhsV; + bool isOpenPhsW; +} OPD_Handle; + +void OPD_Init(OPD_Handle *opd, float minOpenPhsCurr); + +bool OPD_Exec(OPD_Handle *opd, const float *iuvw); + +void OPD_Clear(OPD_Handle *opd); +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/protection/mcs_stall_det.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/protection/mcs_stall_det.c new file mode 100644 index 00000000..be54fab4 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/protection/mcs_stall_det.c @@ -0,0 +1,90 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_stall_det.c + * @author MCU Algorithm Team + * @brief This file contains motor stalling protection data struct and api declaration. + */ + +#include "mcs_stall_det.h" +#include "mcs_assert.h" +#include "mcs_math.h" + + +/** + * @brief Initilization motor stalling protection function. + * @param stall Motor stalling handle. + * @param ts Ctrl period (s). + * @param currLimit The current amplitude that triggers fault. (A). + * @param spdLimit The speed amplitude that triggers fault. (Hz). + * @param timeLimit The threshold time that current amplitude over the limit (s). + * @retval None. + */ +void STD_Init(STD_Handle *stall, float currLimit, float spdLimit, float timeLimit, float ts) +{ + MCS_ASSERT_PARAM(stall != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + MCS_ASSERT_PARAM(currLimit > 0.0f); + MCS_ASSERT_PARAM(spdLimit > 0.0f); + MCS_ASSERT_PARAM(timeLimit > 0.0f); + /* Configuring parameters for stalling detection. */ + stall->ts = ts; + /* Current threshold and speed threshold for stalling fault. */ + stall->currAmpLimit = currLimit; + stall->spdLimit = spdLimit; + stall->timeLimit = timeLimit; + stall->timer = 0.0f; +} + + +/** + * @brief Motor stalling detection. + * @param stall Motor stalling handle. + * @param motorErrStatus Motor error status. + * @param spd Speed feedback (Hz). + * @param idq Dq-axis current feedback (A). + * @retval Whether the motor is stalled, 1: motor stall, 0: no stall. + */ +bool STD_Exec_ByCurrSpd(STD_Handle *stall, float spdFbk, float currAmp) +{ + MCS_ASSERT_PARAM(stall != NULL); + /* Calculate current amplitude. */ + float currAbs = Abs(currAmp); + float spdAbs = Abs(spdFbk); + /* Check if value goes over threshold for continuous cycles. */ + if (spdAbs > stall->spdLimit || currAbs < stall->currAmpLimit) { + stall->timer = 0.0f; + return false; + } + /* Time accumulation. */ + if (stall->timer < stall->timeLimit) { + stall->timer += stall->ts; + return false; + } + return true; +} + +/** + * @brief Clear stall history value. + * @param stall Motor stalling handle. + * @retval None. + */ +void STD_Clear(STD_Handle *stall) +{ + MCS_ASSERT_PARAM(stall != NULL); + stall->timer = 0.0f; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/protection/mcs_stall_det.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/protection/mcs_stall_det.h new file mode 100644 index 00000000..67055498 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/protection/mcs_stall_det.h @@ -0,0 +1,44 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_stall_det.h + * @author MCU Algorithm Team + * @brief This file contains motor stalling protection data struct and api declaration. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_MCS_STALL_DET_H +#define McuMagicTag_MCS_STALL_DET_H + +#include "typedefs.h" + + +typedef struct { + float currAmpLimit; /**< Feedback current higher than this value triggers fault. (A). */ + float spdLimit; /**< Feedback speed lower than this value triggers fault (Hz). */ + float timeLimit; /**< The threshold time that current and speed feedback over ranges (s). */ + float timer; /**< Timer to get speed and current over range time. */ + float ts; /**< Ctrl period (s). */ +} STD_Handle; + +void STD_Init(STD_Handle *stall, float currLimit, float spdLimit, float timeLimit, float ts); + +bool STD_Exec_ByCurrSpd(STD_Handle *stall, float spdFbk, float currAmp); + +void STD_Clear(STD_Handle *stall); + +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/protection/mcs_unbalance_det.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/protection/mcs_unbalance_det.c new file mode 100644 index 00000000..b7f24d89 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/protection/mcs_unbalance_det.c @@ -0,0 +1,225 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_unbalance_det.c + * @author MCU Algorithm Team + * @brief This file provides motor application for Three-phase imbalance detection. + */ + + +#include "mcs_unbalance_det.h" +#include "mcs_math.h" +#include "mcs_math_const.h" +#include "mcs_assert.h" + + +#define START_UNBAL_DET_TIME_S 5 + +/** + * @brief Initilization three-phase unbalance protection function. + * @param unbal Three-phase unbalance detect handle. + * @param currDelta Threshold for determining the zero-crossing point of the phase current. + * @param timeThr Time thredhold of duration , unit: s. + * @param unbalDegreeLim Threshold of the imbalance degree. + * @param ts Ctrl period (s). + * @retval None. + */ +void UNBAL_Init(UNBAL_Handle *unbal, float currDelta, float timeThr, float unbalDegreeLim, float ts) +{ + MCS_ASSERT_PARAM(unbal != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + unbal->detCntLimit = (unsigned int)(timeThr / ts); + unbal->unbalDegreeLimit = unbalDegreeLim; + /* Configuring Limit Times */ + unbal->delta = currDelta; + /* Restore the initial state. */ + unbal->startFlagLast = false; + unbal->startFlag = false; + unbal->ts = ts; + unbal->startupCnt = (unsigned int)(START_UNBAL_DET_TIME_S / ts); + unbal->detCnt = 0; + UNBAL_Clear(unbal); +} + + +/** + * @brief Get three-phase current rms. + * @param unbal Three-phase unbalance detect handle. + * @param iUvw Three-phase current (A). + * @retval None. + */ +static void UNBAL_RmsCurrCalc(UNBAL_Handle *unbal, UvwAxis iUvw) +{ + MCS_ASSERT_PARAM(unbal != NULL); + if (unbal->calFlag) { + /* rms integral */ + unbal->ia += (iUvw.u * iUvw.u * unbal->ts); + unbal->ib += (iUvw.v * iUvw.v * unbal->ts); + unbal->ic += (iUvw.w * iUvw.w * unbal->ts); + unbal->ia = Clamp(unbal->ia, LARGE_FLOAT, -LARGE_FLOAT); + unbal->ib = Clamp(unbal->ib, LARGE_FLOAT, -LARGE_FLOAT); + unbal->ic = Clamp(unbal->ic, LARGE_FLOAT, -LARGE_FLOAT); + + unbal->timeCnt++; + /* Filter out the incomplete period data before the calculation starts. */ + if (unbal->timeCnt < unbal->startupCnt) { + unbal->unbalDegree = 0.0f; + } else if (unbal->timeCnt > unbal->startupCnt + unbal->startupCnt) { + /* Current accumulation is abnormal. */ + unbal->calFlag = false; + unbal->unbalDegree = 0.0f; + unbal->timeCnt = 0; + } else { + if (unbal->startFlagLast != unbal->startFlag) { + unbal->timeCnt = unbal->startupCnt; + } + } + } +} + + +/** + * @brief Get three-phase current rms. + * @param unbal Three-phase unbalance detect handle. + * @param iuvwFbk Three-phase current (A). + * @retval None. + */ +static void UNBAL_RmsCurrGet(UNBAL_Handle *unbal, UvwAxis *iuvwFbk) +{ + UvwAxis iUvw; + float delta = unbal->delta; + + iUvw.u = iuvwFbk->u; + iUvw.v = iuvwFbk->v; + iUvw.w = iuvwFbk->w; + /* Current zero-crossing detection */ + if (iUvw.u < -delta && unbal->startFlag == false) { + unbal->zeroFlag = true; + } + /* Current cycle start judgment */ + if (iUvw.u > delta && unbal->startFlag == false && unbal->zeroFlag) { + unbal->startFlag = true; + unbal->zeroFlag = false; + } + + if (unbal->startFlag) { + /* Accumulated number of integral */ + unbal->integralCnt++; + /* Periodic zero crossing detection */ + if (iUvw.u < -delta) { + unbal->zeroFlag = true; + } + if (iUvw.u > delta && unbal->zeroFlag) { + unbal->zeroFlag = false; + unbal->startFlag = false; + } + } + UNBAL_RmsCurrCalc(unbal, iUvw); +} + + +/** + * @brief Three-phase unbalance calculation. + * @param unbal Three-phase unbalance detect handle. + * @param iuvwFbk Three-phase current (A). + * @param unbalFltCoeff Average filter coefficient for calculating current unbalance degree. + * @retval None. + */ +static void UNBAL_Calc(UNBAL_Handle *unbal, UvwAxis *iuvwFbk, float unbalFltCoeff) +{ + /* Get rms current */ + UNBAL_RmsCurrGet(unbal, iuvwFbk); + /* Current cycle sampling completed */ + if (unbal->startFlagLast != unbal->startFlag) { + unbal->calFlag = true; + if (Abs(unbal->ia) <= 1e-6) { /* Whether there is current */ + unbal->unbalDegree = 0.0f; + return; + } + /* Calculate the three-phase current rms value. */ + float time = (float)unbal->integralCnt * unbal->ts; + float ia = Sqrt(unbal->ia / time); + float ib = Sqrt(unbal->ib / time); + float ic = Sqrt(unbal->ic / time); + unbal->integralCnt = 0; + + /* Based on the symmetrical component method, + three groups of symmetrical components and three-phase currents are + decomposed under the condition of three-phase phase symmetry. + The relationship between amplitudes is as follows: */ + float ia1 = ONE_DIV_THREE * (ia + ib + ic); /* Ia1 = 1/3 * (ia + ib + ic) */ + float tmp = (ia - 0.5f * ib - 0.5f * ic) * (ia - 0.5f * ib - 0.5f * ic); + float tmp2 = 0.75f * (ib - ic) * (ib - ic); /* Ia2 = 1/3 * sqrt((ia - 0.5 * ib)^2 + 3/4 * (ib -ic)^2) */ + float tmp3 = 0.75f * (ic - ib) * (ic - ib); /* Ia0 = 1/3 * sqrt((ia - 0.5 * ib)^2 + 3/4 * (ic -ib)^2) */ + float ia2 = ONE_DIV_THREE * Sqrt(tmp + tmp2); + float ia0 = ONE_DIV_THREE * Sqrt(tmp + tmp3); + float ig = Sqrt(ia0 * ia0 + ia2 * ia2); /* Total unbalanced current */ + float igPer = ig / ia1; /* Current unbalance factor */ + unbal->unbalDegree = unbal->unbalDegree * (1.0f - unbalFltCoeff) + igPer * unbalFltCoeff; + /* Clear current history value */ + unbal->ia = 0.0f; + unbal->ib = 0.0f; + unbal->ic = 0.0f; + } + unbal->startFlagLast = unbal->startFlag; +} + + +/** + * @brief Three-phase unbalance protection detection. + * @param unbal Three-phase unbalance detect handle. + * @param iuvwFbk Three-phase current. + * @retval None. + */ +bool UNBAL_Det(UNBAL_Handle *unbal, UvwAxis *iuvwFbk, float unbalFltCoeff) +{ + MCS_ASSERT_PARAM(unbal != NULL); + MCS_ASSERT_PARAM(iuvwFbk != NULL); + + UNBAL_Calc(unbal, iuvwFbk, unbalFltCoeff); + /* The three-phase imbalance exceeds the limit value. */ + if (unbal->unbalDegree > unbal->unbalDegreeLimit) { + unbal->detCnt++; + /* Current out of balance fault is detected, */ + /* when the protection hysteresis count is greater than the threshold. */ + if (unbal->detCnt > unbal->detCntLimit) { + unbal->detCnt = 0; + return false; + } + } else { + unbal->detCnt = 0; + } + return true; +} + +/** + * @brief Clear historical status of three-phase unbalance detection. + * @param unbal Three-phase unbalance detect handle. + * @retval None. + */ +void UNBAL_Clear(UNBAL_Handle *unbal) +{ + MCS_ASSERT_PARAM(unbal != NULL); + /* Clear historical status */ + unbal->ia = 0.0f; + unbal->ib = 0.0f; + unbal->ic = 0.0f; + unbal->unbalDegree = 0.0f; + unbal->calFlag = false; + /* Detection time count. */ + unbal->timeCnt = 0; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/protection/mcs_unbalance_det.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/protection/mcs_unbalance_det.h new file mode 100644 index 00000000..ac94519e --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/protection/mcs_unbalance_det.h @@ -0,0 +1,55 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_unbalance_det.h + * @author MCU Algorithm Team + * @brief This file contains three-phase imbalance protection data struct and api declaration. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_MCS_UNBALANCE_DET_H +#define McuMagicTag_MCS_UNBALANCE_DET_H + +#include "typedefs.h" +#include "mcs_typedef.h" + +typedef struct { + unsigned int detCnt; + unsigned int detCntLimit; + unsigned int integralCnt; + unsigned int timeCnt; + unsigned int startupCnt; + bool startFlag; + bool startFlagLast; + bool zeroFlag; + bool calFlag; + float unbalDegree; + float unbalDegreeLimit; + float delta; + float ts; + float ia; + float ib; + float ic; +} UNBAL_Handle; + + +void UNBAL_Init(UNBAL_Handle *unbal, float currDelta, float timeThr, float unbalDegreeLim, float ts); + +bool UNBAL_Det(UNBAL_Handle *unbal, UvwAxis *iuvwFbk, float unbalFltCoeff); + +void UNBAL_Clear(UNBAL_Handle *unbal); +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/ramp/mcs_ramp_mgmt.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/ramp/mcs_ramp_mgmt.c new file mode 100644 index 00000000..eaf9a301 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/ramp/mcs_ramp_mgmt.c @@ -0,0 +1,96 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_ramp_mgmt.c + * @author MCU Algorithm Team + * @brief This file provides function of ramp function. + */ + +#include "mcs_ramp_mgmt.h" +#include "mcs_assert.h" + +/** + * @brief Initializer of RMG handle. + * @param rmg: Pointer of RMG handle. + * @param ts: Control period of the RMG module. + * @param slope: Target value divide time of variation. + * @retval None. + */ +void RMG_Init(RMG_Handle *rmg, float ts, float slope) +{ + MCS_ASSERT_PARAM(rmg != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + /* Initializer of RMG handle. */ + rmg->slope = slope; + rmg->yLast = 0.0f; + rmg->ts = ts; + rmg->delta = rmg->slope * rmg->ts; +} + +/** + * @brief Clear historical values of RMG handle. + * @param rmg: Pointer of RMG handle. + * @retval None. + */ +void RMG_Clear(RMG_Handle *rmg) +{ + MCS_ASSERT_PARAM(rmg != NULL); + rmg->yLast = 0.0f; +} + +/** + * @brief Ramp generation and management. + * @param rmg: Pointer of RMG handle. + */ +float RMG_Exec(RMG_Handle *rmg, float targetVal) +{ + MCS_ASSERT_PARAM(rmg != NULL); + float out; + /* Calculate the current output value based on the target value and slope. */ + if (rmg->yLast <= (targetVal - rmg->delta)) { + out = rmg->yLast + rmg->delta; + } else if (rmg->yLast >= (targetVal + rmg->delta)) { + out = rmg->yLast - rmg->delta; + } else { + out = rmg->yLast = targetVal; + } + /* Recording and outputting slope calculation results. */ + rmg->yLast = out; + return out; +} + +/** + * @brief Set ts for ramp. + * @param rmg Pointer of RMG handle. + * @retval The reference value which is ramped. + */ +void RMG_SetTs(RMG_Handle *rmg, float ts) +{ + MCS_ASSERT_PARAM(rmg != NULL); + /* Set ts. */ + rmg->ts = ts; + rmg->delta = rmg->slope * rmg->ts; +} + +void RMG_SetSlope(RMG_Handle *rmg, float slope) +{ + MCS_ASSERT_PARAM(rmg != NULL); + MCS_ASSERT_PARAM(slope > 0.0f); + /* Set slope. */ + rmg->slope = slope; + rmg->delta = rmg->slope * rmg->ts; +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/ramp/mcs_ramp_mgmt.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/ramp/mcs_ramp_mgmt.h new file mode 100644 index 00000000..fecbbe48 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/ramp/mcs_ramp_mgmt.h @@ -0,0 +1,49 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_ramp_mgmt.h + * @author MCU Algorithm Team + * @brief Ramp generation and management for motor control. + * This file provides functions declaration of ramp generation and management module. + */ + +#ifndef McuMagicTag_MCS_RAMP_MGMT_H +#define McuMagicTag_MCS_RAMP_MGMT_H + + +/** + * @brief Ramp mgmt Struct. + */ +typedef struct { + float delta; /**< Step value per calculate period. */ + float yLast; /**< History value of output value. */ + float ts; /**< Control period of the RMG module. */ + float slope; /**< Slope, target value divide time of variation. */ +} RMG_Handle; + + +/** + * @defgroup RAMP_API RAMP API + * @brief The RAMP API definitions. + * @{ + */ +void RMG_Init(RMG_Handle *rmg, float ts, float slope); +void RMG_Clear(RMG_Handle *rmg); +float RMG_Exec(RMG_Handle *rmg, float targetVal); +void RMG_SetTs(RMG_Handle *rmg, float ts); +void RMG_SetSlope(RMG_Handle *rmg, float slope); +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/utilities/mcs_assert.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/utilities/mcs_assert.h new file mode 100644 index 00000000..c61b1275 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/utilities/mcs_assert.h @@ -0,0 +1,57 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_assert.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of the assert. + */ + +/* Define to prevent recursive inclusion ------------------------------------- */ +#ifndef McuMagicTag_MCS_ASSERT_H +#define McuMagicTag_MCS_ASSERT_H + +/* Includes ------------------------------------------------------------------ */ +#include "baseinc.h" + +/** + * @defgroup MCS_ASSERT MCS_ASSERT + * @brief MCS ASSERT module. + * @{ + */ + +/** + * @defgroup ASSERT_Macro ASSERT Macro Function Definition + * @{ + */ +#ifdef MCS_PARAM_CHECK +#define MCS_ASSERT_PARAM BASE_FUNC_ASSERT_PARAM +#define MCS_PARAM_CHECK_NO_RET BASE_FUNC_PARAMCHECK_NO_RET +#define MCS_PARAM_CHECK_WITH_RET BASE_FUNC_PARAMCHECK_WITH_RET +#else +#define MCS_ASSERT_PARAM(para) ((void)0U) +#define MCS_PARAM_CHECK_NO_RET(para) ((void)0U) +#define MCS_PARAM_CHECK_WITH_RET(para, ret) ((void)0U) +#endif + +/** + * @} + */ + +/** + * @} + */ +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/utilities/mcs_mtr_param.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/utilities/mcs_mtr_param.c new file mode 100644 index 00000000..29eaffbf --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/utilities/mcs_mtr_param.c @@ -0,0 +1,47 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_mtr_param.c + * @author MCU Algorithm Team + * @brief This file provides data structure define of motor parameters. + */ + +#include "mcs_mtr_param.h" + + +/** + * @brief Initialzer of motor parameters. + * @param handle Motor parameters handle. + * @param motorTable Motor parameters table. + * @retval None. + */ + void MtrParamInit(MOTOR_Param *handle, const MOTOR_Param motorTable) +{ + MCS_ASSERT_PARAM(handle != NULL); + /* Initialzer of motor parameters */ + handle->mtrRs = motorTable.mtrRs; /* resistor of stator */ + handle->mtrLd = motorTable.mtrLd; /* inductance of D-axis */ + handle->mtrLq = motorTable.mtrLq; /* inductance of Q-axis */ + /* Average inductance, mtrLs = (mtrLd + mtrLq) * 0.5f */ + handle->mtrLs = (motorTable.mtrLd + motorTable.mtrLq) * 0.5f; + handle->mtrPsif = motorTable.mtrPsif; /* permanent magnet flux */ + handle->mtrNp = motorTable.mtrNp; /* numbers of pole pairs */ + handle->mtrJ = motorTable.mtrJ; /* rotor inertia */ + handle->maxElecSpd = motorTable.maxElecSpd; /* max elec speed */ + handle->maxCurr = motorTable.maxCurr; /* max current */ + handle->maxTrq = motorTable.maxTrq; /* max torque */ +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/utilities/mcs_mtr_param.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/utilities/mcs_mtr_param.h new file mode 100644 index 00000000..678d58a3 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/utilities/mcs_mtr_param.h @@ -0,0 +1,59 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_mtr_param.h + * @author MCU Algorithm Team + * @brief This file provides data structure define of motor parameters. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_MTR_PARAM_H +#define McuMagicTag_MCS_MTR_PARAM_H + +/* Typedef definitions ------------------------------------------------------------------------- */ +#include "mcs_assert.h" +/** + * @defgroup MOTOR_PARAMETER MOTOR PARAMETER + * @brief The motor parameter definitions. + * @{ + */ +/** + * @brief motor parameters data structure + */ +typedef struct { + unsigned short mtrNp; /**< Numbers of pole pairs. */ + float mtrRs; /**< Resistor of stator, Ohm. */ + float mtrLd; /**< Inductance of D-axis, H. */ + float mtrLq; /**< Inductance of Q-axis, H. */ + float mtrLs; /**< Average inductance, H. */ + float mtrPsif; /**< Permanent magnet flux, Wb. */ + float mtrJ; /**< Rotor inertia, Kg*m2. */ + float maxElecSpd; /**< Max elec speed, Hz. */ + float maxCurr; /**< Max current, A. */ + float maxTrq; /**< Max torque, Nm. */ + /* Encoder parameters */ + unsigned int mtrPPMR; /**< pulse per mechanical round */ + unsigned int zShift; /**< pulse Z shift */ +} MOTOR_Param; + + +void MtrParamInit(MOTOR_Param *handle, const MOTOR_Param motorTable); +/** + * @} + */ + +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/utilities/mcs_sys_status.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/utilities/mcs_sys_status.h new file mode 100644 index 00000000..c26301fc --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/utilities/mcs_sys_status.h @@ -0,0 +1,188 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_sys_status.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of system status. + */ + +/* Define to prevent recursive inclusion ------------------------------------------------------- */ +#ifndef McuMagicTag_MCS_SYS_STATUS_H +#define McuMagicTag_MCS_SYS_STATUS_H + +/* Includes ------------------------------------------------------------------------------------ */ +#include "typedefs.h" +#include "mcs_assert.h" + +/* Typedef definitions ------------------------------------------------------------------------- */ +/** + * @brief System status define + */ +typedef union { + unsigned short all; + struct { + unsigned short cmdStart : 1; /**< Indicates that a start system command has been received. */ + unsigned short cmdStop : 1; /**< Indicates that a stop system command has been received. */ + unsigned short isRunning : 1; /**< Indicates that the system is running (enable signal) */ + unsigned short sysError : 1; /**< Indicates that the system reports an error. */ + unsigned short poweron : 1; /**< Indicates that the power-on initialization phase is complete. */ + unsigned short capcharge : 1; /**< Indicates that the bootstrap capacitor charging phase is complete. */ + unsigned short adczero : 1; /**< The current sampling point is reset to zero after power-on. */ + } Bit; +} SysStatusReg; + +/** + * @brief Get status of Bit cmdStart. + * @param sysStatus System status register handle. + * @retval Status of Bit cmdStart. + */ +static inline bool SysGetCmdStart(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + bool ret; + ret = (sysStatus->Bit.cmdStart == 1) ? true : false; + return ret; +} + +/** + * @brief Set Bit cmdStart. + * @param sysStatus System status register handle. + * @retval None. + */ +static inline void SysCmdStartSet(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + sysStatus->Bit.cmdStart = 1; +} + +/** + * @brief Clear Bit cmdStart. + * @param handle System status register handle. + * @retval None. + */ +static inline void SysCmdStartClr(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + sysStatus->Bit.cmdStart = 0; +} + +/** + * @brief Get status of Bit cmdStop. + * @param sysStatus System status register handle. + * @retval Status of Bit cmdStart. + */ +static inline bool SysGetCmdStop(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + bool ret; + ret = (sysStatus->Bit.cmdStop == 1) ? true : false; + return ret; +} + +/** + * @brief Set Bit cmdStop. + * @param sysStatus System status register handle. + * @retval None. + */ +static inline void SysCmdStopSet(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + sysStatus->Bit.cmdStop = 1; +} + +/** + * @brief Clear Bit cmdStop. + * @param sysStatus System status register handle. + * @retval None. + */ +static inline void SysCmdStopClr(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + sysStatus->Bit.cmdStop = 0; +} + +/** + * @brief Get status of Bit isRunning. + * @param sysStatus System status register handle. + * @retval Status of Bit isRunning. + */ +static inline bool SysIsRunning(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + bool ret; + ret = (sysStatus->Bit.isRunning == 1) ? true : false; + return ret; +} + +/** + * @brief Set Bit isRuning. + * @param sysStatus System status register handle. + * @retval None. + */ +static inline void SysRunningSet(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + sysStatus->Bit.isRunning = 1; +} + +/** + * @brief Clear Bit isRuning. + * @param sysStatus System status register handle. + * @retval None. + */ +static inline void SysRunningClr(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + sysStatus->Bit.isRunning = 0; +} + +/** + * @brief Get status of Bit sysError. + * @param sysStatus System status register handle. + * @retval Status of Bit sysError. + */ +static inline bool SysIsError(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + bool ret; + ret = (sysStatus->Bit.sysError == 1) ? true : false; + return ret; +} + +/** + * @brief Set Bit sysError. + * @param sysStatus System status register handle. + * @retval None. + */ +static inline void SysErrorSet(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + sysStatus->Bit.sysError = 1; +} + +/** + * @brief Clear Bit sysError. + * @param sysStatus System status register handle. + * @retval None. + */ +static inline void SysErrorClr(SysStatusReg *sysStatus) +{ + MCS_ASSERT_PARAM(sysStatus != NULL); + sysStatus->Bit.sysError = 0; +} + +#endif diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/utilities/mcs_typedef.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/utilities/mcs_typedef.h new file mode 100644 index 00000000..9a9fb890 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/utilities/mcs_typedef.h @@ -0,0 +1,59 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_typedef.h + * @author MCU Algorithm Team + * @brief This file provides the definition of the motor basic data structure. + */ + +#ifndef McuMagicTag_MCS_TYPEDEF_H +#define McuMagicTag_MCS_TYPEDEF_H + + +/** + * @defgroup MCS COORDINATE + * @brief Motor Basic coordinate data structures. + * @{ + */ + +/** + * @brief Rotor synchronous rotation coordinate frame Variables. + */ +typedef struct { + float d; /**< Component d of the rotor synchronous rotation coordinate variable. */ + float q; /**< Component q of the rotor synchronous rotation coordinate variable. */ +} DqAxis; + +/** + * @brief Two-phase stationary coordinate frame variable. + */ +typedef struct { + float alpha; /**< Component alpha of the two-phase stationary coordinate variable. */ + float beta; /**< Component beta of the two-phase stationary coordinate variable. */ +} AlbeAxis; + +/** + * @brief Three-phase static coordinate frame variable. + */ +typedef struct { + float u; /**< Component u of the three-phase static coordinate frame variable. */ + float v; /**< Component v of the three-phase static coordinate frame variable. */ + float w; /**< Component w of the three-phase static coordinate frame variable. */ +} UvwAxis; + + +#endif /* McuMagicTag_MCS_TYPEDEF_H */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/vf/mcs_vf_ctrl.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/vf/mcs_vf_ctrl.c new file mode 100644 index 00000000..ea2457a1 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/vf/mcs_vf_ctrl.c @@ -0,0 +1,155 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_vf_ctrl.c + * @author MCU Algorithm Team + * @brief This file provides functions declaration of v/f control. + */ + +#include "mcs_vf_ctrl.h" +#include "mcs_math.h" +#include "mcs_assert.h" +#include "mcs_math_const.h" + +/** + * @brief Init the vf control handle. + * @param vf The vf control handle. + * @param spdThr Minimum (spdThr[0]) and maximum(spdThr[1]) speed thresholds for ramp command. + * @param voltThr Minimum (voltThr[0]) and maximum(voltThr[1]) voltage for thresholds ramp command. + * @param ts Control period. + * @param spdCmd Motor target speed frequency (Hz). + * @param spdSlope Slope of motor speed reference. + * @retval None. + */ +void VF_Init(VF_Handle *vf, const float *spdThr, const float *voltThr, float ts, float spdCmd, float spdSlope) +{ + MCS_ASSERT_PARAM(vf != NULL); + MCS_ASSERT_PARAM(spdThr != NULL); + MCS_ASSERT_PARAM(voltThr != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + VF_Clear(vf); + RMG_Init(&vf->rmg, ts, spdSlope); + vf->spdCmd = spdCmd; + vf->ts = ts; + /* Set voltage-speed curve. */ + vf->spdThr[0] = spdThr[0]; /* The minimum vf speed. */ + vf->spdThr[1] = spdThr[1]; /* The maximum vf speed. */ + vf->voltThr[0] = voltThr[0]; /* The minimum voltage. */ + vf->voltThr[1] = voltThr[1]; /* The maximum vf voltage. */ + /* Calculate vf slope. */ + vf->slope = (voltThr[1] - voltThr[0]) / (spdThr[1] - spdThr[0]); + vf->ratio.d = 1.0f; + vf->ratio.q = 0.0f; +} + +/** + * @brief Vf control Execution. + * @param vf The vf control handle. + * @param vdqRef Dq axis voltage reference vf control. + * @retval None. + */ +void VF_Exec(VF_Handle *vf, DqAxis *vdqRef) +{ + MCS_ASSERT_PARAM(vf != NULL); + MCS_ASSERT_PARAM(vdqRef != NULL); + /* Vf speed generation. */ + vf->spdRef = RMG_Exec(&vf->rmg, vf->spdCmd); + float vs = 0.0f; + float lowSpdHz = vf->spdThr[0]; + float highSpdHz = vf->spdThr[1]; + float voltMin = vf->voltThr[0]; + float voltMax = vf->voltThr[1]; + /* When the vf reference speed is less than the minimum speed threshold, */ + /* the voltage is set to the minimum voltage threshold. */ + /* When the vf reference speed is greater than the maximum speed threshold, */ + /* the voltage is set to the maximum voltage threshold. */ + if (vf->spdRef < lowSpdHz) { + vs = voltMin; + } else if (vf->spdRef > highSpdHz) { + vs = voltMax; + } else { + vs = voltMin + vf->slope * (vf->spdRef - lowSpdHz); + } + /* Sets dq voltage based on the dq axis proportion */ + vf->vdqRef.d = vs * vf->ratio.d; + vf->vdqRef.q = vs * vf->ratio.q; + vf->vfAngle += DOUBLE_PI * vf->spdRef * vf->ts; + vf->vfAngle = Mod(vf->vfAngle, DOUBLE_PI); + if (vf->vfAngle > ONE_PI) { + vf->vfAngle -= DOUBLE_PI; + } + if (vf->vfAngle < -ONE_PI) { + vf->vfAngle += DOUBLE_PI; + } + vdqRef->d = vf->vdqRef.d; + vdqRef->q = vf->vdqRef.q; +} + +/** + * @brief Clear the vf control history value. + * @param vf The vf control handle. + * @retval None. + */ +void VF_Clear(VF_Handle *vf) +{ + MCS_ASSERT_PARAM(vf != NULL); + /* Clear history value. */ + vf->vfAngle = 0.0f; + vf->spdRef = 0.0f; + vf->vdqRef.d = 0.0f; + vf->vdqRef.q = 0.0f; +} + +/** + * @brief Set vf control period. + * @param vf The vf control handle. + * @param ts The updated vf control period. + * @retval None. + */ +void VF_SetTs(VF_Handle *vf, float ts) +{ + MCS_ASSERT_PARAM(vf != NULL); + MCS_ASSERT_PARAM(ts > 0.0f); + RMG_SetTs(&vf->rmg, ts); + vf->ts = ts; +} + +/** + * @brief Set the slope for the motor to accelerate to the target speed. + * @param vf The vf control handle. + * @param spdSlope The slope. + * @retval None. + */ +void VF_SetSpdSlope(VF_Handle *vf, float spdSlope) +{ + MCS_ASSERT_PARAM(vf != NULL); + RMG_SetSlope(&vf->rmg, spdSlope); +} + +/** + * @brief Set the voltage reference ratio of d, q axis. + * @param vf The vf control handle. + * @param dRatio D axis reference voltage ratio. + * @retval None. + */ +void VF_SetDRatio(VF_Handle *vf, float dRatio) +{ + MCS_ASSERT_PARAM(vf != NULL); + MCS_ASSERT_PARAM(dRatio >= 0.0f && dRatio <= 1.0f); + vf->ratio.d = dRatio; + vf->ratio.q = Sqrt(1.0f - dRatio * dRatio); +} \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/vf/mcs_vf_ctrl.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/vf/mcs_vf_ctrl.h new file mode 100644 index 00000000..5de22b3a --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/control_library/vf/mcs_vf_ctrl.h @@ -0,0 +1,53 @@ +/** + * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the + * following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the + * following disclaimer in the documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * @file mcs_vf_ctrl.h + * @author MCU Algorithm Team + * @brief This file provides functions declaration of v/f control. + * + */ + +#ifndef McuMagicTag_MCS_VF_CTRL_H +#define McuMagicTag_MCS_VF_CTRL_H + + +#include "mcs_typedef.h" +#include "mcs_ramp_mgmt.h" + + +typedef struct { + float spdCmd; /**< Motor target speed frequency (Hz). */ + float spdRef; /**< Motor reference speed frequency (Hz). */ + float vfAngle; /**< Vf control angle. */ + float ts; /**< Control period. */ + float spdThr[2]; /**< Minimum (spdThr[0]) and maximum(spdThr[1]) speed thresholds for ramp command. */ + float voltThr[2]; /**< Minimum (voltThr[0]) and maximum(voltThr[1]) voltage for thresholds ramp command. */ + float slope; /**< Slope of the voltage-speed curve. */ + DqAxis ratio; /**< Proportion of dq-axis reference voltage. */ + DqAxis vdqRef; /**< Dq-axis reference voltage. */ + RMG_Handle rmg; /**< Ramp management structure */ +} VF_Handle; + + +void VF_Init(VF_Handle *vf, const float *spdThr, const float *voltThr, float ts, float spdCmd, float spdSlope); +void VF_Exec(VF_Handle *vf, DqAxis *vdqRef); +void VF_Clear(VF_Handle *vf); +void VF_SetTs(VF_Handle *vf, float ts); +void VF_SetSpdSlope(VF_Handle *vf, float spdSlope); +void VF_SetDRatio(VF_Handle *vf, float dRatio); + +#endif \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/LICENSE b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/LICENSE new file mode 100644 index 00000000..42f2a836 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/LICENSE @@ -0,0 +1,124 @@ +木兰宽松许可证， 第2版 + +2020年1月 http://license.coscl.org.cn/MulanPSL2 + +您对“软件”的复制、使用、修改及分发受木兰宽松许可证，第2版（“本许可证”）的如下条款的约束： + +0. 定义 + +“软件” 是指由“贡献”构成的许可在“本许可证”下的程序和相关文档的集合。 + +“贡献” 是指由任一“贡献者”许可在“本许可证”下的受版权法保护的作品。 + +“贡献者” 是指将受版权法保护的作品许可在“本许可证”下的自然人或“法人实体”。 + +“法人实体” 是指提交贡献的机构及其“关联实体”。 + +“关联实体” 是指，对“本许可证”下的行为方而言，控制、受控制或与其共同受控制的机构，此处的控制是指有受控方或共同受控方至少50%直接或间接的投票权、资金或其他有价证券。 + +1. 授予版权许可 + +每个“贡献者”根据“本许可证”授予您永久性的、全球性的、免费的、非独占的、不可撤销的版权许可，您可以复制、使用、修改、分发其“贡献”，不论修改与否。 + +2. 授予专利许可 + +每个“贡献者”根据“本许可证”授予您永久性的、全球性的、免费的、非独占的、不可撤销的（根据本条规定撤销除外）专利许可，供您制造、委托制造、使用、许诺销售、销售、进口其“贡献”或以其他方式转移其“贡献”。前述专利许可仅限于“贡献者”现在或将来拥有或控制的其“贡献”本身或其“贡献”与许可“贡献”时的“软件”结合而将必然会侵犯的专利权利要求，不包括对“贡献”的修改或包含“贡献”的其他结合。如果您或您的“关联实体”直接或间接地，就“软件”或其中的“贡献”对任何人发起专利侵权诉讼（包括反诉或交叉诉讼）或其他专利维权行动，指控其侵犯专利权，则“本许可证”授予您对“软件”的专利许可自您提起诉讼或发起维权行动之日终止。 + +3. 无商标许可 + +“本许可证”不提供对“贡献者”的商品名称、商标、服务标志或产品名称的商标许可，但您为满足第4条规定的声明义务而必须使用除外。 + +4. 分发限制 + +您可以在任何媒介中将“软件”以源程序形式或可执行形式重新分发，不论修改与否，但您必须向接收者提供“本许可证”的副本，并保留“软件”中的版权、商标、专利及免责声明。 + +5. 免责声明与责任限制 + +“软件”及其中的“贡献”在提供时不带任何明示或默示的担保。在任何情况下，“贡献者”或版权所有者不对任何人因使用“软件”或其中的“贡献”而引发的任何直接或间接损失承担责任，不论因何种原因导致或者基于何种法律理论，即使其曾被建议有此种损失的可能性。 + +6. 语言 + +“本许可证”以中英文双语表述，中英文版本具有同等法律效力。如果中英文版本存在任何冲突不一致，以中文版为准。 + +条款结束 + +如何将木兰宽松许可证，第2版，应用到您的软件 + +如果您希望将木兰宽松许可证，第2版，应用到您的新软件，为了方便接收者查阅，建议您完成如下三步： + +1， 请您补充如下声明中的空白，包括软件名、软件的首次发表年份以及您作为版权人的名字； + +2， 请您在软件包的一级目录下创建以“LICENSE”为名的文件，将整个许可证文本放入该文件中； + +3， 请将如下声明文本放入每个源文件的头部注释中。 + +Copyright (c) [Year] [name of copyright holder] +[Software Name] is licensed under Mulan PSL v2. +You can use this software according to the terms and conditions of the Mulan PSL v2. +You may obtain a copy of Mulan PSL v2 at: + http://license.coscl.org.cn/MulanPSL2 +THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +See the Mulan PSL v2 for more details. +Mulan Permissive Software License,Version 2 +Mulan Permissive Software License,Version 2 (Mulan PSL v2) + +January 2020 http://license.coscl.org.cn/MulanPSL2 + +Your reproduction, use, modification and distribution of the Software shall be subject to Mulan PSL v2 (this License) with the following terms and conditions: + +0. Definition + +Software means the program and related documents which are licensed under this License and comprise all Contribution(s). + +Contribution means the copyrightable work licensed by a particular Contributor under this License. + +Contributor means the Individual or Legal Entity who licenses its copyrightable work under this License. + +Legal Entity means the entity making a Contribution and all its Affiliates. + +Affiliates means entities that control, are controlled by, or are under common control with the acting entity under this License, 'control' means direct or indirect ownership of at least fifty percent (50%) of the voting power, capital or other securities of controlled or commonly controlled entity. + +1. Grant of Copyright License + +Subject to the terms and conditions of this License, each Contributor hereby grants to you a perpetual, worldwide, royalty-free, non-exclusive, irrevocable copyright license to reproduce, use, modify, or distribute its Contribution, with modification or not. + +2. Grant of Patent License + +Subject to the terms and conditions of this License, each Contributor hereby grants to you a perpetual, worldwide, royalty-free, non-exclusive, irrevocable (except for revocation under this Section) patent license to make, have made, use, offer for sale, sell, import or otherwise transfer its Contribution, where such patent license is only limited to the patent claims owned or controlled by such Contributor now or in future which will be necessarily infringed by its Contribution alone, or by combination of the Contribution with the Software to which the Contribution was contributed. The patent license shall not apply to any modification of the Contribution, and any other combination which includes the Contribution. If you or your Affiliates directly or indirectly institute patent litigation (including a cross claim or counterclaim in a litigation) or other patent enforcement activities against any individual or entity by alleging that the Software or any Contribution in it infringes patents, then any patent license granted to you under this License for the Software shall terminate as of the date such litigation or activity is filed or taken. + +3. No Trademark License + +No trademark license is granted to use the trade names, trademarks, service marks, or product names of Contributor, except as required to fulfill notice requirements in section 4. + +4. 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IN THE CASE OF DIVERGENCE BETWEEN THE CHINESE AND ENGLISH VERSIONS, THE CHINESE VERSION SHALL PREVAIL. + +END OF THE TERMS AND CONDITIONS + +How to Apply the Mulan Permissive Software License,Version 2 (Mulan PSL v2) to Your Software + +To apply the Mulan PSL v2 to your work, for easy identification by recipients, you are suggested to complete following three steps: + +Fill in the blanks in following statement, including insert your software name, the year of the first publication of your software, and your name identified as the copyright owner; +Create a file named "LICENSE" which contains the whole context of this License in the first directory of your software package; +Attach the statement to the appropriate annotated syntax at the beginning of each source file. +Copyright (c) [Year] [name of copyright holder] +[Software Name] is licensed under Mulan PSL v2. +You can use this software according to the terms and conditions of the Mulan PSL v2. +You may obtain a copy of Mulan PSL v2 at: + http://license.coscl.org.cn/MulanPSL2 +THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +See the Mulan PSL v2 for more details. \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/Makefile b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/Makefile new file mode 100644 index 00000000..bdeee085 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/Makefile @@ -0,0 +1,44 @@ +PROJECT=libboundscheck.so + +CC?=gcc + +OPTION = -fPIC +OPTION += -fstack-protector-all +OPTION += -D_FORTIFY_SOURCE=2 -O2 +OPTION += -Wformat=2 -Wfloat-equal -Wshadow +OPTION += -Wconversion +OPTION += -Wformat-security +OPTION += -Wextra +OPTION += --param ssp-buffer-size=4 +OPTION += -Warray-bounds +OPTION += -Wpointer-arith +OPTION += -Wcast-qual +OPTION += -Wstrict-prototypes +OPTION += -Wmissing-prototypes +OPTION += -Wstrict-overflow=1 +OPTION += -Wstrict-aliasing=2 +OPTION += -Wswitch -Wswitch-default + +CFLAG = -Wall -DNDEBUG -O2 $(OPTION) + +SOURCES=$(wildcard src/*.c) + +OBJECTS=$(patsubst %.c,%.o,$(SOURCES)) + +.PHONY:clean + +CFLAG += -Iinclude +LD_FLAG = -fPIC -s -Wl,-z,relro,-z,now,-z,noexecstack -fstack-protector-all + +$(PROJECT): $(OBJECTS) + mkdir -p lib + $(CC) -shared -o lib/$@ $(patsubst %.o,obj/%.o,$(notdir $(OBJECTS))) $(LD_FLAG) + @echo "finish $(PROJECT)" + +.c.o: + @mkdir -p obj + $(CC) -c $< $(CFLAG) -o obj/$(patsubst %.c,%.o,$(notdir $<)) + +clean: + -rm -rf obj lib + @echo "clean up" diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/README.en.md b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/README.en.md new file mode 100644 index 00000000..60c477fe --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/README.en.md @@ -0,0 +1,59 @@ +# libboundscheck + +#### Description + +- following the standard of C11 Annex K (bound-checking interfaces), functions of the common memory/string operation classes, such as memcpy_s, strcpy_s, are selected and implemented. + +- other standard functions in C11 Annex K will be analyzed in the future and implemented in this organization if necessary. + +- handles the release, update, and maintenance of bounds_checking_function. + +#### Function List + +- memcpy_s +- wmemcpy_s +- memmove_s +- wmemmove_s +- memset_s +- strcpy_s +- wcscpy_s +- strncpy_s +- wcsncpy_s +- strcat_s +- wcscat_s +- strncat_s +- wcsncat_s +- strtok_s +- wcstok_s +- sprintf_s +- swprintf_s +- vsprintf_s +- vswprintf_s +- snprintf_s +- vsnprintf_s +- scanf_s +- wscanf_s +- vscanf_s +- vwscanf_s +- fscanf_s +- fwscanf_s +- vfscanf_s +- vfwscanf_s +- sscanf_s +- swscanf_s +- vsscanf_s +- vswscanf_s +- gets_s + + +#### Build + +``` +CC=gcc make +``` +The generated Dynamic library libboundscheck.so is stored in the newly created directory lib. + +#### How to use +1. Copy the libboundscheck.so to the library file directory, for example: "/usr/local/lib/". + +2. To use the libboundscheck, add the “-lboundscheck” parameters to the compiler, for example: “gcc -g -o test test.c -lboundscheck”. \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/README.md b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/README.md new file mode 100644 index 00000000..c16cbb17 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/README.md @@ -0,0 +1,56 @@ +# libboundscheck + +#### 介绍 +- 遵循C11 Annex K (Bounds-checking interfaces)的标准，选取并实现了常见的内存/字符串操作类的函数，如memcpy_s、strcpy_s等函数。 +- 未来将分析C11 Annex K中的其他标准函数，如果有必要，将在该组织中实现。 +- 处理边界检查函数的版本发布、更新以及维护。 + +#### 函数清单 + +- memcpy_s +- wmemcpy_s +- memmove_s +- wmemmove_s +- memset_s +- strcpy_s +- wcscpy_s +- strncpy_s +- wcsncpy_s +- strcat_s +- wcscat_s +- strncat_s +- wcsncat_s +- strtok_s +- wcstok_s +- sprintf_s +- swprintf_s +- vsprintf_s +- vswprintf_s +- snprintf_s +- vsnprintf_s +- scanf_s +- wscanf_s +- vscanf_s +- vwscanf_s +- fscanf_s +- fwscanf_s +- vfscanf_s +- vfwscanf_s +- sscanf_s +- swscanf_s +- vsscanf_s +- vswscanf_s +- gets_s + +#### 构建方法 + +运行命令 +``` +make CC=gcc +``` +生成的动态库libboundscheck.so存放在新创建的lib目录下。 + +#### 使用方法 +1. 将构建生成的动态库libboundscheck.so放到库文件目录下，例如："/usr/local/lib/"。 + +2. 为使用libboundscheck，编译程序时需增加编译参数"-lboundscheck"，例如："gcc -g -o test test.c -lboundscheck"。 \ No newline at end of file diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/include/securec.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/include/securec.h new file mode 100644 index 00000000..b1dea967 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/include/securec.h @@ -0,0 +1,637 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: The user of this secure c library should include this header file in you source code. + * This header file declare all supported API prototype of the library, + * such as memcpy_s, strcpy_s, wcscpy_s,strcat_s, strncat_s, sprintf_s, scanf_s, and so on. + * Create: 2014-02-25 + * Notes: Do not modify this file by yourself. + */ + +#ifndef SECUREC_H_5D13A042_DC3F_4ED9_A8D1_882811274C27 +#define SECUREC_H_5D13A042_DC3F_4ED9_A8D1_882811274C27 + +#include "securectype.h" +#ifndef SECUREC_HAVE_STDARG_H +#define SECUREC_HAVE_STDARG_H 1 +#endif + +#if SECUREC_HAVE_STDARG_H +#include +#endif + +#ifndef SECUREC_HAVE_ERRNO_H +#define SECUREC_HAVE_ERRNO_H 1 +#endif + +/* EINVAL ERANGE may defined in errno.h */ +#if SECUREC_HAVE_ERRNO_H +#if SECUREC_IN_KERNEL +#include +#else +#include +#endif +#endif + +/* Define error code */ +#if defined(SECUREC_NEED_ERRNO_TYPE) || !defined(__STDC_WANT_LIB_EXT1__) || \ + (defined(__STDC_WANT_LIB_EXT1__) && (!__STDC_WANT_LIB_EXT1__)) +#ifndef SECUREC_DEFINED_ERRNO_TYPE +#define SECUREC_DEFINED_ERRNO_TYPE +/* Just check whether macrodefinition exists. */ +#ifndef errno_t +typedef int errno_t; +#endif +#endif +#endif + +/* Success */ +#ifndef EOK +#define EOK 0 +#endif + +#ifndef EINVAL +/* The src buffer is not correct and destination buffer can not be reset */ +#define EINVAL 22 +#endif + +#ifndef EINVAL_AND_RESET +/* Once the error is detected, the dest buffer must be reset! Value is 22 or 128 */ +#define EINVAL_AND_RESET 150 +#endif + +#ifndef ERANGE +/* The destination buffer is not long enough and destination buffer can not be reset */ +#define ERANGE 34 +#endif + +#ifndef ERANGE_AND_RESET +/* Once the error is detected, the dest buffer must be reset! Value is 34 or 128 */ +#define ERANGE_AND_RESET 162 +#endif + +#ifndef EOVERLAP_AND_RESET +/* Once the buffer overlap is detected, the dest buffer must be reset! Value is 54 or 128 */ +#define EOVERLAP_AND_RESET 182 +#endif + +/* If you need export the function of this library in Win32 dll, use __declspec(dllexport) */ +#ifndef SECUREC_API +#if defined(SECUREC_DLL_EXPORT) +#if defined(_MSC_VER) +#define SECUREC_API __declspec(dllexport) +#else /* build for linux */ +#define SECUREC_API __attribute__((visibility("default"))) +#endif /* end of _MSC_VER and SECUREC_DLL_EXPORT */ +#elif defined(SECUREC_DLL_IMPORT) +#if defined(_MSC_VER) +#define SECUREC_API __declspec(dllimport) +#else +#define SECUREC_API +#endif /* end of _MSC_VER and SECUREC_DLL_IMPORT */ +#else +/* + * Standardized function declaration. If a security function is declared in the your code, + * it may cause a compilation alarm,Please delete the security function you declared. + * Adding extern under windows will cause the system to have inline functions to expand, + * so do not add the extern in default + */ +#if defined(_MSC_VER) +#define SECUREC_API +#else +#define SECUREC_API extern +#endif +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif +/* + * Description: The GetHwSecureCVersion function get SecureC Version string and version number. + * Parameter: verNumber - to store version number (for example value is 0x500 | 0xa) + * Return: version string + */ +SECUREC_API const char *GetHwSecureCVersion(unsigned short *verNumber); + +#if SECUREC_ENABLE_MEMSET +/* + * Description: The memset_s function copies the value of c (converted to an unsigned char) into each of + * the first count characters of the object pointed to by dest. + * Parameter: dest - destination address + * Parameter: destMax - The maximum length of destination buffer + * Parameter: c - the value to be copied + * Parameter: count - copies count bytes of value to dest + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t memset_s(void *dest, size_t destMax, int c, size_t count); +#endif + +#ifndef SECUREC_ONLY_DECLARE_MEMSET +#define SECUREC_ONLY_DECLARE_MEMSET 0 +#endif + +#if !SECUREC_ONLY_DECLARE_MEMSET + +#if SECUREC_ENABLE_MEMMOVE +/* + * Description: The memmove_s function copies n characters from the object pointed to by src + * into the object pointed to by dest. + * Parameter: dest - destination address + * Parameter: destMax - The maximum length of destination buffer + * Parameter: src - source address + * Parameter: count - copies count bytes from the src + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t memmove_s(void *dest, size_t destMax, const void *src, size_t count); +#endif + +#if SECUREC_ENABLE_MEMCPY +/* + * Description: The memcpy_s function copies n characters from the object pointed to + * by src into the object pointed to by dest. + * Parameter: dest - destination address + * Parameter: destMax - The maximum length of destination buffer + * Parameter: src - source address + * Parameter: count - copies count bytes from the src + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t memcpy_s(void *dest, size_t destMax, const void *src, size_t count); +#endif + +#if SECUREC_ENABLE_STRCPY +/* + * Description: The strcpy_s function copies the string pointed to by strSrc (including + * the terminating null character) into the array pointed to by strDest + * Parameter: strDest - destination address + * Parameter: destMax - The maximum length of destination buffer(including the terminating null character) + * Parameter: strSrc - source address + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t strcpy_s(char *strDest, size_t destMax, const char *strSrc); +#endif + +#if SECUREC_ENABLE_STRNCPY +/* + * Description: The strncpy_s function copies not more than n successive characters (not including + * the terminating null character) from the array pointed to by strSrc to the array pointed to by strDest. + * Parameter: strDest - destination address + * Parameter: destMax - The maximum length of destination buffer(including the terminating null character) + * Parameter: strSrc - source address + * Parameter: count - copies count characters from the src + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t strncpy_s(char *strDest, size_t destMax, const char *strSrc, size_t count); +#endif + +#if SECUREC_ENABLE_STRCAT +/* + * Description: The strcat_s function appends a copy of the string pointed to by strSrc (including + * the terminating null character) to the end of the string pointed to by strDest. + * Parameter: strDest - destination address + * Parameter: destMax - The maximum length of destination buffer(including the terminating null wide character) + * Parameter: strSrc - source address + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t strcat_s(char *strDest, size_t destMax, const char *strSrc); +#endif + +#if SECUREC_ENABLE_STRNCAT +/* + * Description: The strncat_s function appends not more than n successive characters (not including + * the terminating null character) + * from the array pointed to by strSrc to the end of the string pointed to by strDest. + * Parameter: strDest - destination address + * Parameter: destMax - The maximum length of destination buffer(including the terminating null character) + * Parameter: strSrc - source address + * Parameter: count - copies count characters from the src + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t strncat_s(char *strDest, size_t destMax, const char *strSrc, size_t count); +#endif + +#if SECUREC_ENABLE_VSPRINTF +/* + * Description: The vsprintf_s function is equivalent to the vsprintf function except for the parameter destMax + * and the explicit runtime-constraints violation + * Parameter: strDest - produce output according to a format,write to the character string strDest. + * Parameter: destMax - The maximum length of destination buffer(including the terminating null wide character) + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of characters printed(not including the terminating null byte '\0'), + * If an error occurred Return: -1. + */ +SECUREC_API int vsprintf_s(char *strDest, size_t destMax, const char *format, + va_list argList) SECUREC_ATTRIBUTE(3, 0); +#endif + +#if SECUREC_ENABLE_SPRINTF +/* + * Description: The sprintf_s function is equivalent to the sprintf function except for the parameter destMax + * and the explicit runtime-constraints violation + * Parameter: strDest - produce output according to a format ,write to the character string strDest. + * Parameter: destMax - The maximum length of destination buffer(including the terminating null byte '\0') + * Parameter: format - format string + * Return: the number of characters printed(not including the terminating null byte '\0'), + * If an error occurred Return: -1. +*/ +SECUREC_API int sprintf_s(char *strDest, size_t destMax, const char *format, ...) SECUREC_ATTRIBUTE(3, 4); +#endif + +#if SECUREC_ENABLE_VSNPRINTF +/* + * Description: The vsnprintf_s function is equivalent to the vsnprintf function except for + * the parameter destMax/count and the explicit runtime-constraints violation + * Parameter: strDest - produce output according to a format ,write to the character string strDest. + * Parameter: destMax - The maximum length of destination buffer(including the terminating null byte '\0') + * Parameter: count - do not write more than count bytes to strDest(not including the terminating null byte '\0') + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of characters printed(not including the terminating null byte '\0'), + * If an error occurred Return: -1.Pay special attention to returning -1 when truncation occurs. + */ +SECUREC_API int vsnprintf_s(char *strDest, size_t destMax, size_t count, const char *format, + va_list argList) SECUREC_ATTRIBUTE(4, 0); +#endif + +#if SECUREC_ENABLE_SNPRINTF +/* + * Description: The snprintf_s function is equivalent to the snprintf function except for + * the parameter destMax/count and the explicit runtime-constraints violation + * Parameter: strDest - produce output according to a format ,write to the character string strDest. + * Parameter: destMax - The maximum length of destination buffer(including the terminating null byte '\0') + * Parameter: count - do not write more than count bytes to strDest(not including the terminating null byte '\0') + * Parameter: format - format string + * Return: the number of characters printed(not including the terminating null byte '\0'), + * If an error occurred Return: -1.Pay special attention to returning -1 when truncation occurs. + */ +SECUREC_API int snprintf_s(char *strDest, size_t destMax, size_t count, const char *format, + ...) SECUREC_ATTRIBUTE(4, 5); +#endif + +#if SECUREC_SNPRINTF_TRUNCATED +/* + * Description: The vsnprintf_truncated_s function is equivalent to the vsnprintf_s function except + * no count parameter and return value + * Parameter: strDest - produce output according to a format ,write to the character string strDest + * Parameter: destMax - The maximum length of destination buffer(including the terminating null byte '\0') + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of characters printed(not including the terminating null byte '\0'), + * If an error occurred Return: -1.Pay special attention to returning destMax - 1 when truncation occurs +*/ +SECUREC_API int vsnprintf_truncated_s(char *strDest, size_t destMax, const char *format, + va_list argList) SECUREC_ATTRIBUTE(3, 0); + +/* + * Description: The snprintf_truncated_s function is equivalent to the snprintf_s function except + * no count parameter and return value + * Parameter: strDest - produce output according to a format,write to the character string strDest. + * Parameter: destMax - The maximum length of destination buffer(including the terminating null byte '\0') + * Parameter: format - format string + * Return: the number of characters printed(not including the terminating null byte '\0'), + * If an error occurred Return: -1.Pay special attention to returning destMax - 1 when truncation occurs. + */ +SECUREC_API int snprintf_truncated_s(char *strDest, size_t destMax, + const char *format, ...) SECUREC_ATTRIBUTE(3, 4); +#endif + +#if SECUREC_ENABLE_SCANF +/* + * Description: The scanf_s function is equivalent to fscanf_s with the argument stdin + * interposed before the arguments to scanf_s + * Parameter: format - format string + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int scanf_s(const char *format, ...); +#endif + +#if SECUREC_ENABLE_VSCANF +/* + * Description: The vscanf_s function is equivalent to scanf_s, with the variable argument list replaced by argList + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int vscanf_s(const char *format, va_list argList); +#endif + +#if SECUREC_ENABLE_SSCANF +/* + * Description: The sscanf_s function is equivalent to fscanf_s, except that input is obtained from a + * string (specified by the argument buffer) rather than from a stream + * Parameter: buffer - read character from buffer + * Parameter: format - format string + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int sscanf_s(const char *buffer, const char *format, ...); +#endif + +#if SECUREC_ENABLE_VSSCANF +/* + * Description: The vsscanf_s function is equivalent to sscanf_s, with the variable argument list + * replaced by argList + * Parameter: buffer - read character from buffer + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int vsscanf_s(const char *buffer, const char *format, va_list argList); +#endif + +#if SECUREC_ENABLE_FSCANF +/* + * Description: The fscanf_s function is equivalent to fscanf except that the c, s, and [ conversion specifiers + * apply to a pair of arguments (unless assignment suppression is indicated by a *) + * Parameter: stream - stdio file stream + * Parameter: format - format string + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int fscanf_s(FILE *stream, const char *format, ...); +#endif + +#if SECUREC_ENABLE_VFSCANF +/* + * Description: The vfscanf_s function is equivalent to fscanf_s, with the variable argument list + * replaced by argList + * Parameter: stream - stdio file stream + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int vfscanf_s(FILE *stream, const char *format, va_list argList); +#endif + +#if SECUREC_ENABLE_STRTOK +/* + * Description: The strtok_s function parses a string into a sequence of strToken, + * replace all characters in strToken string that match to strDelimit set with 0. + * On the first call to strtok_s the string to be parsed should be specified in strToken. + * In each subsequent call that should parse the same string, strToken should be NULL + * Parameter: strToken - the string to be delimited + * Parameter: strDelimit - specifies a set of characters that delimit the tokens in the parsed string + * Parameter: context - is a pointer to a char * variable that is used internally by strtok_s function + * Return: On the first call returns the address of the first non \0 character, otherwise NULL is returned. + * In subsequent calls, the strtoken is set to NULL, and the context set is the same as the previous call, + * return NULL if the *context string length is equal 0, otherwise return *context. + */ +SECUREC_API char *strtok_s(char *strToken, const char *strDelimit, char **context); +#endif + +#if SECUREC_ENABLE_GETS && !SECUREC_IN_KERNEL +/* + * Description: The gets_s function reads at most one less than the number of characters specified + * by destMax from the stream pointed to by stdin, into the array pointed to by buffer + * Parameter: buffer - destination address + * Parameter: destMax - The maximum length of destination buffer(including the terminating null character) + * Return: buffer if there was no runtime-constraint violation,If an error occurred Return: NULL. + */ +SECUREC_API char *gets_s(char *buffer, size_t destMax); +#endif + +#if SECUREC_ENABLE_WCHAR_FUNC +#if SECUREC_ENABLE_MEMCPY +/* + * Description: The wmemcpy_s function copies n successive wide characters from the object pointed to + * by src into the object pointed to by dest. + * Parameter: dest - destination address + * Parameter: destMax - The maximum length of destination buffer + * Parameter: src - source address + * Parameter: count - copies count wide characters from the src + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t wmemcpy_s(wchar_t *dest, size_t destMax, const wchar_t *src, size_t count); +#endif + +#if SECUREC_ENABLE_MEMMOVE +/* + * Description: The wmemmove_s function copies n successive wide characters from the object + * pointed to by src into the object pointed to by dest. + * Parameter: dest - destination address + * Parameter: destMax - The maximum length of destination buffer + * Parameter: src - source address + * Parameter: count - copies count wide characters from the src + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t wmemmove_s(wchar_t *dest, size_t destMax, const wchar_t *src, size_t count); +#endif + +#if SECUREC_ENABLE_STRCPY +/* + * Description: The wcscpy_s function copies the wide string pointed to by strSrc(including the terminating + * null wide character) into the array pointed to by strDest + * Parameter: strDest - destination address + * Parameter: destMax - The maximum length of destination buffer + * Parameter: strSrc - source address + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t wcscpy_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc); +#endif + +#if SECUREC_ENABLE_STRNCPY +/* + * Description: The wcsncpy_s function copies not more than n successive wide characters (not including the + * terminating null wide character) from the array pointed to by strSrc to the array pointed to by strDest + * Parameter: strDest - destination address + * Parameter: destMax - The maximum length of destination buffer(including the terminating wide character) + * Parameter: strSrc - source address + * Parameter: count - copies count wide characters from the src + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t wcsncpy_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc, size_t count); +#endif + +#if SECUREC_ENABLE_STRCAT +/* + * Description: The wcscat_s function appends a copy of the wide string pointed to by strSrc (including the + * terminating null wide character) to the end of the wide string pointed to by strDest + * Parameter: strDest - destination address + * Parameter: destMax - The maximum length of destination buffer(including the terminating wide character) + * Parameter: strSrc - source address + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t wcscat_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc); +#endif + +#if SECUREC_ENABLE_STRNCAT +/* + * Description: The wcsncat_s function appends not more than n successive wide characters (not including the + * terminating null wide character) from the array pointed to by strSrc to the end of the wide string pointed to + * by strDest. + * Parameter: strDest - destination address + * Parameter: destMax - The maximum length of destination buffer(including the terminating wide character) + * Parameter: strSrc - source address + * Parameter: count - copies count wide characters from the src + * Return: EOK if there was no runtime-constraint violation + */ +SECUREC_API errno_t wcsncat_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc, size_t count); +#endif + +#if SECUREC_ENABLE_STRTOK +/* + * Description: The wcstok_s function is the wide-character equivalent of the strtok_s function + * Parameter: strToken - the string to be delimited + * Parameter: strDelimit - specifies a set of characters that delimit the tokens in the parsed string + * Parameter: context - is a pointer to a char * variable that is used internally by strtok_s function + * Return: a pointer to the first character of a token, or a null pointer if there is no token + * or there is a runtime-constraint violation. + */ +SECUREC_API wchar_t *wcstok_s(wchar_t *strToken, const wchar_t *strDelimit, wchar_t **context); +#endif + +#if SECUREC_ENABLE_VSPRINTF +/* + * Description: The vswprintf_s function is the wide-character equivalent of the vsprintf_s function + * Parameter: strDest - produce output according to a format,write to the character string strDest + * Parameter: destMax - The maximum length of destination buffer(including the terminating null) + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of characters printed(not including the terminating null wide character), + * If an error occurred Return: -1. + */ +SECUREC_API int vswprintf_s(wchar_t *strDest, size_t destMax, const wchar_t *format, va_list argList); +#endif + +#if SECUREC_ENABLE_SPRINTF +/* + * Description: The swprintf_s function is the wide-character equivalent of the sprintf_s function + * Parameter: strDest - produce output according to a format,write to the character string strDest + * Parameter: destMax - The maximum length of destination buffer(including the terminating null) + * Parameter: format - format string + * Return: the number of characters printed(not including the terminating null wide character), + * If an error occurred Return: -1. + */ +SECUREC_API int swprintf_s(wchar_t *strDest, size_t destMax, const wchar_t *format, ...); +#endif + +#if SECUREC_ENABLE_FSCANF +/* + * Description: The fwscanf_s function is the wide-character equivalent of the fscanf_s function + * Parameter: stream - stdio file stream + * Parameter: format - format string + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int fwscanf_s(FILE *stream, const wchar_t *format, ...); +#endif + +#if SECUREC_ENABLE_VFSCANF +/* + * Description: The vfwscanf_s function is the wide-character equivalent of the vfscanf_s function + * Parameter: stream - stdio file stream + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int vfwscanf_s(FILE *stream, const wchar_t *format, va_list argList); +#endif + +#if SECUREC_ENABLE_SCANF +/* + * Description: The wscanf_s function is the wide-character equivalent of the scanf_s function + * Parameter: format - format string + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int wscanf_s(const wchar_t *format, ...); +#endif + +#if SECUREC_ENABLE_VSCANF +/* + * Description: The vwscanf_s function is the wide-character equivalent of the vscanf_s function + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int vwscanf_s(const wchar_t *format, va_list argList); +#endif + +#if SECUREC_ENABLE_SSCANF +/* + * Description: The swscanf_s function is the wide-character equivalent of the sscanf_s function + * Parameter: buffer - read character from buffer + * Parameter: format - format string + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int swscanf_s(const wchar_t *buffer, const wchar_t *format, ...); +#endif + +#if SECUREC_ENABLE_VSSCANF +/* + * Description: The vswscanf_s function is the wide-character equivalent of the vsscanf_s function + * Parameter: buffer - read character from buffer + * Parameter: format - format string + * Parameter: argList - instead of a variable number of arguments + * Return: the number of input items assigned, If an error occurred Return: -1. + */ +SECUREC_API int vswscanf_s(const wchar_t *buffer, const wchar_t *format, va_list argList); +#endif +#endif /* SECUREC_ENABLE_WCHAR_FUNC */ +#endif + +/* Those functions are used by macro,must declare hare, also for without function declaration warning */ +extern errno_t strncpy_error(char *strDest, size_t destMax, const char *strSrc, size_t count); +extern errno_t strcpy_error(char *strDest, size_t destMax, const char *strSrc); + +#if SECUREC_WITH_PERFORMANCE_ADDONS +/* Those functions are used by macro */ +extern errno_t memset_sOptAsm(void *dest, size_t destMax, int c, size_t count); +extern errno_t memset_sOptTc(void *dest, size_t destMax, int c, size_t count); +extern errno_t memcpy_sOptAsm(void *dest, size_t destMax, const void *src, size_t count); +extern errno_t memcpy_sOptTc(void *dest, size_t destMax, const void *src, size_t count); + +/* The strcpy_sp is a macro, not a function in performance optimization mode. */ +#define strcpy_sp(dest, destMax, src) ((__builtin_constant_p((destMax)) && \ + __builtin_constant_p((src))) ? \ + SECUREC_STRCPY_SM((dest), (destMax), (src)) : \ + strcpy_s((dest), (destMax), (src))) + +/* The strncpy_sp is a macro, not a function in performance optimization mode. */ +#define strncpy_sp(dest, destMax, src, count) ((__builtin_constant_p((count)) && \ + __builtin_constant_p((destMax)) && \ + __builtin_constant_p((src))) ? \ + SECUREC_STRNCPY_SM((dest), (destMax), (src), (count)) : \ + strncpy_s((dest), (destMax), (src), (count))) + +/* The strcat_sp is a macro, not a function in performance optimization mode. */ +#define strcat_sp(dest, destMax, src) ((__builtin_constant_p((destMax)) && \ + __builtin_constant_p((src))) ? \ + SECUREC_STRCAT_SM((dest), (destMax), (src)) : \ + strcat_s((dest), (destMax), (src))) + +/* The strncat_sp is a macro, not a function in performance optimization mode. */ +#define strncat_sp(dest, destMax, src, count) ((__builtin_constant_p((count)) && \ + __builtin_constant_p((destMax)) && \ + __builtin_constant_p((src))) ? \ + SECUREC_STRNCAT_SM((dest), (destMax), (src), (count)) : \ + strncat_s((dest), (destMax), (src), (count))) + +/* The memcpy_sp is a macro, not a function in performance optimization mode. */ +#define memcpy_sp(dest, destMax, src, count) (__builtin_constant_p((count)) ? \ + (SECUREC_MEMCPY_SM((dest), (destMax), (src), (count))) : \ + (__builtin_constant_p((destMax)) ? \ + (((size_t)(destMax) > 0 && \ + (((unsigned long long)(destMax) & (unsigned long long)(-2)) < SECUREC_MEM_MAX_LEN)) ? \ + memcpy_sOptTc((dest), (destMax), (src), (count)) : ERANGE) : \ + memcpy_sOptAsm((dest), (destMax), (src), (count)))) + +/* The memset_sp is a macro, not a function in performance optimization mode. */ +#define memset_sp(dest, destMax, c, count) (__builtin_constant_p((count)) ? \ + (SECUREC_MEMSET_SM((dest), (destMax), (c), (count))) : \ + (__builtin_constant_p((destMax)) ? \ + (((((unsigned long long)(destMax) & (unsigned long long)(-2)) < SECUREC_MEM_MAX_LEN)) ? \ + memset_sOptTc((dest), (destMax), (c), (count)) : ERANGE) : \ + memset_sOptAsm((dest), (destMax), (c), (count)))) + +#endif + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/include/securectype.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/include/securectype.h new file mode 100644 index 00000000..69e79c2f --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/include/securectype.h @@ -0,0 +1,585 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: Define internal used macro and data type. The marco of SECUREC_ON_64BITS + * will be determined in this header file, which is a switch for part + * of code. Some macro are used to suppress warning by MS compiler. + * Create: 2014-02-25 + * Notes: User can change the value of SECUREC_STRING_MAX_LEN and SECUREC_MEM_MAX_LEN + * macro to meet their special need, but The maximum value should not exceed 2G. + */ +/* + * [Standardize-exceptions]: Performance-sensitive + * [reason]: Strict parameter verification has been done before use + */ + +#ifndef SECURECTYPE_H_A7BBB686_AADA_451B_B9F9_44DACDAE18A7 +#define SECURECTYPE_H_A7BBB686_AADA_451B_B9F9_44DACDAE18A7 + +#ifndef SECUREC_USING_STD_SECURE_LIB +#if defined(_MSC_VER) && _MSC_VER >= 1400 +#if defined(__STDC_WANT_SECURE_LIB__) && (!__STDC_WANT_SECURE_LIB__) +/* Security functions have been provided since vs2005, default use of system library functions */ +#define SECUREC_USING_STD_SECURE_LIB 0 +#else +#define SECUREC_USING_STD_SECURE_LIB 1 +#endif +#else +#define SECUREC_USING_STD_SECURE_LIB 0 +#endif +#endif + +/* Compatibility with older Secure C versions, shielding VC symbol redefinition warning */ +#if defined(_MSC_VER) && (_MSC_VER >= 1400) && (!SECUREC_USING_STD_SECURE_LIB) +#ifndef SECUREC_DISABLE_CRT_FUNC +#define SECUREC_DISABLE_CRT_FUNC 1 +#endif +#ifndef SECUREC_DISABLE_CRT_IMP +#define SECUREC_DISABLE_CRT_IMP 1 +#endif +#else /* MSC VER */ +#ifndef SECUREC_DISABLE_CRT_FUNC +#define SECUREC_DISABLE_CRT_FUNC 0 +#endif +#ifndef SECUREC_DISABLE_CRT_IMP +#define SECUREC_DISABLE_CRT_IMP 0 +#endif +#endif + +#if SECUREC_DISABLE_CRT_FUNC +#ifdef __STDC_WANT_SECURE_LIB__ +#undef __STDC_WANT_SECURE_LIB__ +#endif +#define __STDC_WANT_SECURE_LIB__ 0 +#endif + +#if SECUREC_DISABLE_CRT_IMP +#ifdef _CRTIMP_ALTERNATIVE +#undef _CRTIMP_ALTERNATIVE +#endif +#define _CRTIMP_ALTERNATIVE /* Comment Microsoft *_s function */ +#endif + +/* Compile in kernel under macro control */ +#ifndef SECUREC_IN_KERNEL +#ifdef __KERNEL__ +#define SECUREC_IN_KERNEL 1 +#else +#define SECUREC_IN_KERNEL 0 +#endif +#endif + +/* make kernel symbols of functions available to loadable modules */ +#ifndef SECUREC_EXPORT_KERNEL_SYMBOL +#if SECUREC_IN_KERNEL +#define SECUREC_EXPORT_KERNEL_SYMBOL 1 +#else +#define SECUREC_EXPORT_KERNEL_SYMBOL 0 +#endif +#endif + +#if SECUREC_IN_KERNEL +#ifndef SECUREC_ENABLE_SCANF_FILE +#define SECUREC_ENABLE_SCANF_FILE 0 +#endif +#ifndef SECUREC_ENABLE_WCHAR_FUNC +#define SECUREC_ENABLE_WCHAR_FUNC 0 +#endif +#else /* SECUREC_IN_KERNEL */ +#ifndef SECUREC_ENABLE_SCANF_FILE +#define SECUREC_ENABLE_SCANF_FILE 1 +#endif +#ifndef SECUREC_ENABLE_WCHAR_FUNC +#define SECUREC_ENABLE_WCHAR_FUNC 1 +#endif +#endif + +/* Default secure function declaration, default declarations for non-standard functions */ +#ifndef SECUREC_SNPRINTF_TRUNCATED +#define SECUREC_SNPRINTF_TRUNCATED 1 +#endif + +#if SECUREC_USING_STD_SECURE_LIB +#if defined(_MSC_VER) && _MSC_VER >= 1400 +/* Declare secure functions that are not available in the VS compiler */ +#ifndef SECUREC_ENABLE_MEMSET +#define SECUREC_ENABLE_MEMSET 1 +#endif +/* VS 2005 have vsnprintf_s function */ +#ifndef SECUREC_ENABLE_VSNPRINTF +#define SECUREC_ENABLE_VSNPRINTF 0 +#endif +#ifndef SECUREC_ENABLE_SNPRINTF +/* VS 2005 have vsnprintf_s function Adapt the snprintf_s of the security function */ +#define snprintf_s _snprintf_s +#define SECUREC_ENABLE_SNPRINTF 0 +#endif +/* Before VS 2010 do not have v functions */ +#if _MSC_VER <= 1600 || defined(SECUREC_FOR_V_SCANFS) +#ifndef SECUREC_ENABLE_VFSCANF +#define SECUREC_ENABLE_VFSCANF 1 +#endif +#ifndef SECUREC_ENABLE_VSCANF +#define SECUREC_ENABLE_VSCANF 1 +#endif +#ifndef SECUREC_ENABLE_VSSCANF +#define SECUREC_ENABLE_VSSCANF 1 +#endif +#endif + +#else /* MSC VER */ +#ifndef SECUREC_ENABLE_MEMSET +#define SECUREC_ENABLE_MEMSET 0 +#endif +#ifndef SECUREC_ENABLE_SNPRINTF +#define SECUREC_ENABLE_SNPRINTF 0 +#endif +#ifndef SECUREC_ENABLE_VSNPRINTF +#define SECUREC_ENABLE_VSNPRINTF 0 +#endif +#endif + +#ifndef SECUREC_ENABLE_MEMMOVE +#define SECUREC_ENABLE_MEMMOVE 0 +#endif +#ifndef SECUREC_ENABLE_MEMCPY +#define SECUREC_ENABLE_MEMCPY 0 +#endif +#ifndef SECUREC_ENABLE_STRCPY +#define SECUREC_ENABLE_STRCPY 0 +#endif +#ifndef SECUREC_ENABLE_STRNCPY +#define SECUREC_ENABLE_STRNCPY 0 +#endif +#ifndef SECUREC_ENABLE_STRCAT +#define SECUREC_ENABLE_STRCAT 0 +#endif +#ifndef SECUREC_ENABLE_STRNCAT +#define SECUREC_ENABLE_STRNCAT 0 +#endif +#ifndef SECUREC_ENABLE_SPRINTF +#define SECUREC_ENABLE_SPRINTF 0 +#endif +#ifndef SECUREC_ENABLE_VSPRINTF +#define SECUREC_ENABLE_VSPRINTF 0 +#endif +#ifndef SECUREC_ENABLE_SSCANF +#define SECUREC_ENABLE_SSCANF 0 +#endif +#ifndef SECUREC_ENABLE_VSSCANF +#define SECUREC_ENABLE_VSSCANF 0 +#endif +#ifndef SECUREC_ENABLE_SCANF +#define SECUREC_ENABLE_SCANF 0 +#endif +#ifndef SECUREC_ENABLE_VSCANF +#define SECUREC_ENABLE_VSCANF 0 +#endif + +#ifndef SECUREC_ENABLE_FSCANF +#define SECUREC_ENABLE_FSCANF 0 +#endif +#ifndef SECUREC_ENABLE_VFSCANF +#define SECUREC_ENABLE_VFSCANF 0 +#endif +#ifndef SECUREC_ENABLE_STRTOK +#define SECUREC_ENABLE_STRTOK 0 +#endif +#ifndef SECUREC_ENABLE_GETS +#define SECUREC_ENABLE_GETS 0 +#endif + +#else /* SECUREC USE STD SECURE LIB */ + +#ifndef SECUREC_ENABLE_MEMSET +#define SECUREC_ENABLE_MEMSET 1 +#endif +#ifndef SECUREC_ENABLE_MEMMOVE +#define SECUREC_ENABLE_MEMMOVE 1 +#endif +#ifndef SECUREC_ENABLE_MEMCPY +#define SECUREC_ENABLE_MEMCPY 1 +#endif +#ifndef SECUREC_ENABLE_STRCPY +#define SECUREC_ENABLE_STRCPY 1 +#endif +#ifndef SECUREC_ENABLE_STRNCPY +#define SECUREC_ENABLE_STRNCPY 1 +#endif +#ifndef SECUREC_ENABLE_STRCAT +#define SECUREC_ENABLE_STRCAT 1 +#endif +#ifndef SECUREC_ENABLE_STRNCAT +#define SECUREC_ENABLE_STRNCAT 1 +#endif +#ifndef SECUREC_ENABLE_SPRINTF +#define SECUREC_ENABLE_SPRINTF 1 +#endif +#ifndef SECUREC_ENABLE_VSPRINTF +#define SECUREC_ENABLE_VSPRINTF 1 +#endif +#ifndef SECUREC_ENABLE_SNPRINTF +#define SECUREC_ENABLE_SNPRINTF 1 +#endif +#ifndef SECUREC_ENABLE_VSNPRINTF +#define SECUREC_ENABLE_VSNPRINTF 1 +#endif +#ifndef SECUREC_ENABLE_SSCANF +#define SECUREC_ENABLE_SSCANF 1 +#endif +#ifndef SECUREC_ENABLE_VSSCANF +#define SECUREC_ENABLE_VSSCANF 1 +#endif +#ifndef SECUREC_ENABLE_SCANF +#if SECUREC_ENABLE_SCANF_FILE +#define SECUREC_ENABLE_SCANF 1 +#else +#define SECUREC_ENABLE_SCANF 0 +#endif +#endif +#ifndef SECUREC_ENABLE_VSCANF +#if SECUREC_ENABLE_SCANF_FILE +#define SECUREC_ENABLE_VSCANF 1 +#else +#define SECUREC_ENABLE_VSCANF 0 +#endif +#endif + +#ifndef SECUREC_ENABLE_FSCANF +#if SECUREC_ENABLE_SCANF_FILE +#define SECUREC_ENABLE_FSCANF 1 +#else +#define SECUREC_ENABLE_FSCANF 0 +#endif +#endif +#ifndef SECUREC_ENABLE_VFSCANF +#if SECUREC_ENABLE_SCANF_FILE +#define SECUREC_ENABLE_VFSCANF 1 +#else +#define SECUREC_ENABLE_VFSCANF 0 +#endif +#endif + +#ifndef SECUREC_ENABLE_STRTOK +#define SECUREC_ENABLE_STRTOK 1 +#endif +#ifndef SECUREC_ENABLE_GETS +#define SECUREC_ENABLE_GETS 1 +#endif +#endif /* SECUREC_USE_STD_SECURE_LIB */ + +#if !SECUREC_ENABLE_SCANF_FILE +#if SECUREC_ENABLE_FSCANF +#undef SECUREC_ENABLE_FSCANF +#define SECUREC_ENABLE_FSCANF 0 +#endif +#if SECUREC_ENABLE_VFSCANF +#undef SECUREC_ENABLE_VFSCANF +#define SECUREC_ENABLE_VFSCANF 0 +#endif +#if SECUREC_ENABLE_SCANF +#undef SECUREC_ENABLE_SCANF +#define SECUREC_ENABLE_SCANF 0 +#endif +#if SECUREC_ENABLE_FSCANF +#undef SECUREC_ENABLE_FSCANF +#define SECUREC_ENABLE_FSCANF 0 +#endif + +#endif + +#if SECUREC_IN_KERNEL +#include +#include +#else +#ifndef SECUREC_HAVE_STDIO_H +#define SECUREC_HAVE_STDIO_H 1 +#endif +#ifndef SECUREC_HAVE_STRING_H +#define SECUREC_HAVE_STRING_H 1 +#endif +#ifndef SECUREC_HAVE_STDLIB_H +#define SECUREC_HAVE_STDLIB_H 1 +#endif +#if SECUREC_HAVE_STDIO_H +#include +#endif +#if SECUREC_HAVE_STRING_H +#include +#endif +#if SECUREC_HAVE_STDLIB_H +#include +#endif +#endif + +/* + * If you need high performance, enable the SECUREC_WITH_PERFORMANCE_ADDONS macro, default is enable. + * The macro is automatically closed on the windows platform and linux kernel + */ +#ifndef SECUREC_WITH_PERFORMANCE_ADDONS +#if SECUREC_IN_KERNEL +#define SECUREC_WITH_PERFORMANCE_ADDONS 0 +#else +#define SECUREC_WITH_PERFORMANCE_ADDONS 1 +#endif +#endif + +/* If enable SECUREC_COMPATIBLE_WIN_FORMAT, the output format will be compatible to Windows. */ +#if (defined(_WIN32) || defined(_WIN64) || defined(_MSC_VER)) && !defined(SECUREC_COMPATIBLE_LINUX_FORMAT) +#ifndef SECUREC_COMPATIBLE_WIN_FORMAT +#define SECUREC_COMPATIBLE_WIN_FORMAT +#endif +#endif + +#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) +/* On windows platform, can't use optimized function for there is no __builtin_constant_p like function */ +/* If need optimized macro, can define this: define __builtin_constant_p(x) 0 */ +#ifdef SECUREC_WITH_PERFORMANCE_ADDONS +#undef SECUREC_WITH_PERFORMANCE_ADDONS +#define SECUREC_WITH_PERFORMANCE_ADDONS 0 +#endif +#endif + +#if defined(__VXWORKS__) || defined(__vxworks) || defined(__VXWORKS) || defined(_VXWORKS_PLATFORM_) || \ + defined(SECUREC_VXWORKS_VERSION_5_4) +#ifndef SECUREC_VXWORKS_PLATFORM +#define SECUREC_VXWORKS_PLATFORM +#endif +#endif + +/* If enable SECUREC_COMPATIBLE_LINUX_FORMAT, the output format will be compatible to Linux. */ +#if !defined(SECUREC_COMPATIBLE_WIN_FORMAT) && !defined(SECUREC_VXWORKS_PLATFORM) +#ifndef SECUREC_COMPATIBLE_LINUX_FORMAT +#define SECUREC_COMPATIBLE_LINUX_FORMAT +#endif +#endif + +#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT +#ifndef SECUREC_HAVE_STDDEF_H +#define SECUREC_HAVE_STDDEF_H 1 +#endif +/* Some system may no stddef.h */ +#if SECUREC_HAVE_STDDEF_H +#if !SECUREC_IN_KERNEL +#include +#endif +#endif +#endif + +/* + * Add the -DSECUREC_SUPPORT_FORMAT_WARNING=1 compiler option to supoort -Wformat=2. + * Default does not check the format is that the same data type in the actual code. + * In the product is different in the original data type definition of VxWorks and Linux. + */ +#ifndef SECUREC_SUPPORT_FORMAT_WARNING +#define SECUREC_SUPPORT_FORMAT_WARNING 0 +#endif + +#if SECUREC_SUPPORT_FORMAT_WARNING +#define SECUREC_ATTRIBUTE(x, y) __attribute__((format(printf, (x), (y)))) +#else +#define SECUREC_ATTRIBUTE(x, y) +#endif + +/* + * Add the -DSECUREC_SUPPORT_BUILTIN_EXPECT=0 compiler option, if compiler can not support __builtin_expect. + */ +#ifndef SECUREC_SUPPORT_BUILTIN_EXPECT +#define SECUREC_SUPPORT_BUILTIN_EXPECT 1 +#endif + +#if SECUREC_SUPPORT_BUILTIN_EXPECT && defined(__GNUC__) && ((__GNUC__ > 3) || \ + (defined(__GNUC_MINOR__) && (__GNUC__ == 3 && __GNUC_MINOR__ > 3))) +/* + * This is a built-in function that can be used without a declaration, if warning for declaration not found occurred, + * you can add -DSECUREC_NEED_BUILTIN_EXPECT_DECLARE to compiler options + */ +#ifdef SECUREC_NEED_BUILTIN_EXPECT_DECLARE +long __builtin_expect(long exp, long c); +#endif + +#define SECUREC_LIKELY(x) __builtin_expect(!!(x), 1) +#define SECUREC_UNLIKELY(x) __builtin_expect(!!(x), 0) +#else +#define SECUREC_LIKELY(x) (x) +#define SECUREC_UNLIKELY(x) (x) +#endif + +/* Define the max length of the string */ +#ifndef SECUREC_STRING_MAX_LEN +#define SECUREC_STRING_MAX_LEN 0x7fffffffUL +#endif +#define SECUREC_WCHAR_STRING_MAX_LEN (SECUREC_STRING_MAX_LEN / sizeof(wchar_t)) + +/* Add SECUREC_MEM_MAX_LEN for memcpy and memmove */ +#ifndef SECUREC_MEM_MAX_LEN +#define SECUREC_MEM_MAX_LEN 0x7fffffffUL +#endif +#define SECUREC_WCHAR_MEM_MAX_LEN (SECUREC_MEM_MAX_LEN / sizeof(wchar_t)) + +#if SECUREC_STRING_MAX_LEN > 0x7fffffffUL +#error "max string is 2G" +#endif + +#if (defined(__GNUC__) && defined(__SIZEOF_POINTER__)) +#if (__SIZEOF_POINTER__ != 4) && (__SIZEOF_POINTER__ != 8) +#error "unsupported system" +#endif +#endif + +#if defined(_WIN64) || defined(WIN64) || defined(__LP64__) || defined(_LP64) +#define SECUREC_ON_64BITS +#endif + +#if (!defined(SECUREC_ON_64BITS) && defined(__GNUC__) && defined(__SIZEOF_POINTER__)) +#if __SIZEOF_POINTER__ == 8 +#define SECUREC_ON_64BITS +#endif +#endif + +#if defined(__SVR4) || defined(__svr4__) +#define SECUREC_ON_SOLARIS +#endif + +#if (defined(__hpux) || defined(_AIX) || defined(SECUREC_ON_SOLARIS)) +#define SECUREC_ON_UNIX +#endif + +/* + * Codes should run under the macro SECUREC_COMPATIBLE_LINUX_FORMAT in unknown system on default, + * and strtold. + * The function strtold is referenced first at ISO9899:1999(C99), and some old compilers can + * not support these functions. Here provides a macro to open these functions: + * SECUREC_SUPPORT_STRTOLD -- If defined, strtold will be used + */ +#ifndef SECUREC_SUPPORT_STRTOLD +#define SECUREC_SUPPORT_STRTOLD 0 +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT)) +#if defined(__USE_ISOC99) || \ + (defined(_AIX) && defined(_ISOC99_SOURCE)) || \ + (defined(__hpux) && defined(__ia64)) || \ + (defined(SECUREC_ON_SOLARIS) && (!defined(_STRICT_STDC) && !defined(__XOPEN_OR_POSIX)) || \ + defined(_STDC_C99) || defined(__EXTENSIONS__)) +#undef SECUREC_SUPPORT_STRTOLD +#define SECUREC_SUPPORT_STRTOLD 1 +#endif +#endif +#if ((defined(SECUREC_WRLINUX_BELOW4) || defined(_WRLINUX_BELOW4_))) +#undef SECUREC_SUPPORT_STRTOLD +#define SECUREC_SUPPORT_STRTOLD 0 +#endif +#endif + +#if SECUREC_WITH_PERFORMANCE_ADDONS + +#ifndef SECUREC_TWO_MIN +#define SECUREC_TWO_MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +/* For strncpy_s performance optimization */ +#define SECUREC_STRNCPY_SM(dest, destMax, src, count) \ + (((void *)(dest) != NULL && (const void *)(src) != NULL && (size_t)(destMax) > 0 && \ + (((unsigned long long)(destMax) & (unsigned long long)(-2)) < SECUREC_STRING_MAX_LEN) && \ + (SECUREC_TWO_MIN((size_t)(count), strlen(src)) + 1) <= (size_t)(destMax)) ? \ + (((size_t)(count) < strlen(src)) ? (memcpy((dest), (src), (count)), *((char *)(dest) + (count)) = '\0', EOK) : \ + (memcpy((dest), (src), strlen(src) + 1), EOK)) : (strncpy_error((dest), (destMax), (src), (count)))) + +#define SECUREC_STRCPY_SM(dest, destMax, src) \ + (((void *)(dest) != NULL && (const void *)(src) != NULL && (size_t)(destMax) > 0 && \ + (((unsigned long long)(destMax) & (unsigned long long)(-2)) < SECUREC_STRING_MAX_LEN) && \ + (strlen(src) + 1) <= (size_t)(destMax)) ? (memcpy((dest), (src), strlen(src) + 1), EOK) : \ + (strcpy_error((dest), (destMax), (src)))) + +/* For strcat_s performance optimization */ +#if defined(__GNUC__) +#define SECUREC_STRCAT_SM(dest, destMax, src) ({ \ + int catRet_ = EOK; \ + if ((void *)(dest) != NULL && (const void *)(src) != NULL && (size_t)(destMax) > 0 && \ + (((unsigned long long)(destMax) & (unsigned long long)(-2)) < SECUREC_STRING_MAX_LEN)) { \ + char *catTmpDst_ = (char *)(dest); \ + size_t catRestSize_ = (destMax); \ + while (catRestSize_ > 0 && *catTmpDst_ != '\0') { \ + ++catTmpDst_; \ + --catRestSize_; \ + } \ + if (catRestSize_ == 0) { \ + catRet_ = EINVAL; \ + } else if ((strlen(src) + 1) <= catRestSize_) { \ + memcpy(catTmpDst_, (src), strlen(src) + 1); \ + catRet_ = EOK; \ + } else { \ + catRet_ = ERANGE; \ + } \ + if (catRet_ != EOK) { \ + catRet_ = strcat_s((dest), (destMax), (src)); \ + } \ + } else { \ + catRet_ = strcat_s((dest), (destMax), (src)); \ + } \ + catRet_; \ +}) +#else +#define SECUREC_STRCAT_SM(dest, destMax, src) strcat_s((dest), (destMax), (src)) +#endif + +/* For strncat_s performance optimization */ +#if defined(__GNUC__) +#define SECUREC_STRNCAT_SM(dest, destMax, src, count) ({ \ + int ncatRet_ = EOK; \ + if ((void *)(dest) != NULL && (const void *)(src) != NULL && (size_t)(destMax) > 0 && \ + (((unsigned long long)(destMax) & (unsigned long long)(-2)) < SECUREC_STRING_MAX_LEN) && \ + (((unsigned long long)(count) & (unsigned long long)(-2)) < SECUREC_STRING_MAX_LEN)) { \ + char *ncatTmpDest_ = (char *)(dest); \ + size_t ncatRestSize_ = (size_t)(destMax); \ + while (ncatRestSize_ > 0 && *ncatTmpDest_ != '\0') { \ + ++ncatTmpDest_; \ + --ncatRestSize_; \ + } \ + if (ncatRestSize_ == 0) { \ + ncatRet_ = EINVAL; \ + } else if ((SECUREC_TWO_MIN((count), strlen(src)) + 1) <= ncatRestSize_) { \ + if ((size_t)(count) < strlen(src)) { \ + memcpy(ncatTmpDest_, (src), (count)); \ + *(ncatTmpDest_ + (count)) = '\0'; \ + } else { \ + memcpy(ncatTmpDest_, (src), strlen(src) + 1); \ + } \ + } else { \ + ncatRet_ = ERANGE; \ + } \ + if (ncatRet_ != EOK) { \ + ncatRet_ = strncat_s((dest), (destMax), (src), (count)); \ + } \ + } else { \ + ncatRet_ = strncat_s((dest), (destMax), (src), (count)); \ + } \ + ncatRet_; \ +}) +#else +#define SECUREC_STRNCAT_SM(dest, destMax, src, count) strncat_s((dest), (destMax), (src), (count)) +#endif + +/* This macro do not check buffer overlap by default */ +#define SECUREC_MEMCPY_SM(dest, destMax, src, count) \ + (!(((size_t)(destMax) == 0) || \ + (((unsigned long long)(destMax) & (unsigned long long)(-2)) > SECUREC_MEM_MAX_LEN) || \ + ((size_t)(count) > (size_t)(destMax)) || ((void *)(dest)) == NULL || ((const void *)(src) == NULL)) ? \ + (memcpy((dest), (src), (count)), EOK) : \ + (memcpy_s((dest), (destMax), (src), (count)))) + +#define SECUREC_MEMSET_SM(dest, destMax, c, count) \ + (!((((unsigned long long)(destMax) & (unsigned long long)(-2)) > SECUREC_MEM_MAX_LEN) || \ + ((void *)(dest) == NULL) || ((size_t)(count) > (size_t)(destMax))) ? \ + (memset((dest), (c), (count)), EOK) : \ + (memset_s((dest), (destMax), (c), (count)))) + +#endif +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/fscanf_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/fscanf_s.c new file mode 100644 index 00000000..d3c7f06c --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/fscanf_s.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: fscanf_s function + * Create: 2014-02-25 + */ + +#include "securec.h" + +/* + * + * The fscanf_s function is equivalent to fscanf except that the c, s, + * and [ conversion specifiers apply to a pair of arguments (unless assignment suppression is indicated by a*) + * The fscanf function reads data from the current position of stream into + * the locations given by argument (if any). Each argument must be a pointer + * to a variable of a type that corresponds to a type specifier in format. + * format controls the interpretation of the input fields and has the same + * form and function as the format argument for scanf. + * + * + * stream Pointer to FILE structure. + * format Format control string, see Format Specifications. + * ... Optional arguments. + * + * + * ... The converted value stored in user assigned address + * + * + * Each of these functions returns the number of fields successfully converted + * and assigned; the return value does not include fields that were read but + * not assigned. A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int fscanf_s(FILE *stream, const char *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vfscanf_s(stream, format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/fwscanf_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/fwscanf_s.c new file mode 100644 index 00000000..bd0f12a9 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/fwscanf_s.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: fwscanf_s function + * Create: 2014-02-25 + */ + +#include "securec.h" + +/* + * + * The fwscanf_s function is the wide-character equivalent of the fscanf_s function + * The fwscanf_s function reads data from the current position of stream into + * the locations given by argument (if any). Each argument must be a pointer + * to a variable of a type that corresponds to a type specifier in format. + * format controls the interpretation of the input fields and has the same + * form and function as the format argument for scanf. + * + * + * stream Pointer to FILE structure. + * format Format control string, see Format Specifications. + * ... Optional arguments. + * + * + * ... The converted value stored in user assigned address + * + * + * Each of these functions returns the number of fields successfully converted + * and assigned; the return value does not include fields that were read but + * not assigned. A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int fwscanf_s(FILE *stream, const wchar_t *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vfwscanf_s(stream, format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/gets_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/gets_s.c new file mode 100644 index 00000000..d12495aa --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/gets_s.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: gets_s function + * Create: 2014-02-25 + */ + +#include "securecutil.h" + +/* + * The parameter size is buffer size in byte + */ +SECUREC_INLINE void SecTrimCRLF(char *buffer, size_t size) +{ + size_t len = strlen(buffer); + --len; /* Unsigned integer wrapping is accepted and is checked afterwards */ + while (len < size && (buffer[len] == '\r' || buffer[len] == '\n')) { + buffer[len] = '\0'; + --len; /* Unsigned integer wrapping is accepted and is checked next loop */ + } +} + +/* + * + * The gets_s function reads at most one less than the number of characters + * specified by destMax from the std input stream, into the array pointed to by buffer + * The line consists of all characters up to and including + * the first newline character ('\n'). gets_s then replaces the newline + * character with a null character ('\0') before returning the line. + * If the first character read is the end-of-file character, a null character + * is stored at the beginning of buffer and NULL is returned. + * + * + * buffer Storage location for input string. + * destMax The size of the buffer. + * + * + * buffer is updated + * + * + * buffer Successful operation + * NULL Improper parameter or read fail + */ +char *gets_s(char *buffer, size_t destMax) +{ +#ifdef SECUREC_COMPATIBLE_WIN_FORMAT + size_t bufferSize = ((destMax == (size_t)(-1)) ? SECUREC_STRING_MAX_LEN : destMax); +#else + size_t bufferSize = destMax; +#endif + + if (buffer == NULL || bufferSize == 0 || bufferSize > SECUREC_STRING_MAX_LEN) { + SECUREC_ERROR_INVALID_PARAMTER("gets_s"); + return NULL; + } + + if (fgets(buffer, (int)bufferSize, SECUREC_STREAM_STDIN) != NULL) { + SecTrimCRLF(buffer, bufferSize); + return buffer; + } + + return NULL; +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/input.inl b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/input.inl new file mode 100644 index 00000000..41d401cf --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/input.inl @@ -0,0 +1,2229 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: Used by secureinput_a.c and secureinput_w.c to include. + * This file provides a template function for ANSI and UNICODE compiling by + * different type definition. The functions of SecInputS or + * SecInputSW provides internal implementation for scanf family API, such as sscanf_s, fscanf_s. + * Create: 2014-02-25 + * Notes: The formatted input processing results of integers on different platforms are different. + */ +/* + * [Standardize-exceptions] Use unsafe function: Performance-sensitive + * [reason] Always used in the performance critical path, + * and sufficient input validation is performed before calling + */ +#ifndef INPUT_INL_5D13A042_DC3F_4ED9_A8D1_882811274C27 +#define INPUT_INL_5D13A042_DC3F_4ED9_A8D1_882811274C27 + +#if SECUREC_IN_KERNEL +#if !defined(SECUREC_CTYPE_MACRO_ADAPT) +#include +#endif +#else +#if !defined(SECUREC_SYSAPI4VXWORKS) && !defined(SECUREC_CTYPE_MACRO_ADAPT) +#include +#ifdef SECUREC_FOR_WCHAR +#include /* For iswspace */ +#endif +#endif +#endif + +#ifndef EOF +#define EOF (-1) +#endif + +#define SECUREC_NUM_WIDTH_SHORT 0 +#define SECUREC_NUM_WIDTH_INT 1 +#define SECUREC_NUM_WIDTH_LONG 2 +#define SECUREC_NUM_WIDTH_LONG_LONG 3 /* Also long double */ + +#define SECUREC_BUFFERED_BLOK_SIZE 1024U + +#if defined(SECUREC_VXWORKS_PLATFORM) && !defined(va_copy) && !defined(__va_copy) +/* The name is the same as system macro. */ +#define __va_copy(dest, src) do { \ + size_t destSize_ = (size_t)sizeof(dest); \ + size_t srcSize_ = (size_t)sizeof(src); \ + if (destSize_ != srcSize_) { \ + SECUREC_MEMCPY_WARP_OPT((dest), (src), sizeof(va_list)); \ + } else { \ + SECUREC_MEMCPY_WARP_OPT(&(dest), &(src), sizeof(va_list)); \ + } \ +} SECUREC_WHILE_ZERO +#endif + +#define SECUREC_MULTI_BYTE_MAX_LEN 6 + +/* Compatibility macro name cannot be modifie */ +#ifndef UNALIGNED +#if !(defined(_M_IA64)) && !(defined(_M_AMD64)) +#define UNALIGNED +#else +#define UNALIGNED __unaligned +#endif +#endif + +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) +/* Max 64bit value is 0xffffffffffffffff */ +#define SECUREC_MAX_64BITS_VALUE 18446744073709551615ULL +#define SECUREC_MAX_64BITS_VALUE_DIV_TEN 1844674407370955161ULL +#define SECUREC_MAX_64BITS_VALUE_CUT_LAST_DIGIT 18446744073709551610ULL +#define SECUREC_MIN_64BITS_NEG_VALUE 9223372036854775808ULL +#define SECUREC_MAX_64BITS_POS_VALUE 9223372036854775807ULL +#define SECUREC_MIN_32BITS_NEG_VALUE 2147483648UL +#define SECUREC_MAX_32BITS_POS_VALUE 2147483647UL +#define SECUREC_MAX_32BITS_VALUE 4294967295UL +#define SECUREC_MAX_32BITS_VALUE_INC 4294967296UL +#define SECUREC_MAX_32BITS_VALUE_DIV_TEN 429496729UL +#define SECUREC_LONG_BIT_NUM ((unsigned int)(sizeof(long) << 3U)) +/* Use ULL to clean up cl6x compilation alerts */ +#define SECUREC_MAX_LONG_POS_VALUE ((unsigned long)(1ULL << (SECUREC_LONG_BIT_NUM - 1)) - 1) +#define SECUREC_MIN_LONG_NEG_VALUE ((unsigned long)(1ULL << (SECUREC_LONG_BIT_NUM - 1))) + +/* Covert to long long to clean up cl6x compilation alerts */ +#define SECUREC_LONG_HEX_BEYOND_MAX(number) (((unsigned long long)(number) >> (SECUREC_LONG_BIT_NUM - 4U)) > 0) +#define SECUREC_LONG_OCTAL_BEYOND_MAX(number) (((unsigned long long)(number) >> (SECUREC_LONG_BIT_NUM - 3U)) > 0) + +#define SECUREC_QWORD_HEX_BEYOND_MAX(number) (((number) >> (64U - 4U)) > 0) +#define SECUREC_QWORD_OCTAL_BEYOND_MAX(number) (((number) >> (64U - 3U)) > 0) + +#define SECUREC_LP64_BIT_WIDTH 64 +#define SECUREC_LP32_BIT_WIDTH 32 + +#define SECUREC_CONVERT_IS_SIGNED(conv) ((conv) == 'd' || (conv) == 'i') +#endif + +#define SECUREC_BRACE '{' /* [ to { */ +#define SECUREC_FILED_WIDTH_ENOUGH(spec) ((spec)->widthSet == 0 || (spec)->width > 0) +#define SECUREC_FILED_WIDTH_DEC(spec) do { \ + if ((spec)->widthSet != 0) { \ + --(spec)->width; \ + } \ +} SECUREC_WHILE_ZERO + +#ifdef SECUREC_FOR_WCHAR +/* Bits for all wchar, size is 65536/8, only supports wide characters with a maximum length of two bytes */ +#define SECUREC_BRACKET_TABLE_SIZE 8192 +#define SECUREC_EOF WEOF +#define SECUREC_MB_LEN 16 /* Max. # bytes in multibyte char ,see MB_LEN_MAX */ +#else +/* Bits for all char, size is 256/8 */ +#define SECUREC_BRACKET_TABLE_SIZE 32 +#define SECUREC_EOF EOF +#endif + +#if SECUREC_HAVE_WCHART +#define SECUREC_ARRAY_WIDTH_IS_WRONG(spec) ((spec).arrayWidth == 0 || \ + ((spec).isWCharOrLong <= 0 && (spec).arrayWidth > SECUREC_STRING_MAX_LEN) || \ + ((spec).isWCharOrLong > 0 && (spec).arrayWidth > SECUREC_WCHAR_STRING_MAX_LEN)) +#else +#define SECUREC_ARRAY_WIDTH_IS_WRONG(spec) ((spec).arrayWidth == 0 || (spec).arrayWidth > SECUREC_STRING_MAX_LEN) +#endif + +#ifdef SECUREC_ON_64BITS +/* Use 0xffffffffUL mask to pass integer as array length */ +#define SECUREC_GET_ARRAYWIDTH(argList) (((size_t)va_arg((argList), size_t)) & 0xffffffffUL) +#else /* !SECUREC_ON_64BITS */ +#define SECUREC_GET_ARRAYWIDTH(argList) ((size_t)va_arg((argList), size_t)) +#endif + +typedef struct { +#ifdef SECUREC_FOR_WCHAR + unsigned char *table; /* Default NULL */ +#else + unsigned char table[SECUREC_BRACKET_TABLE_SIZE]; /* Array length is large enough in application scenarios */ +#endif + unsigned char mask; /* Default 0 */ +} SecBracketTable; + +#ifdef SECUREC_FOR_WCHAR +#define SECUREC_INIT_BRACKET_TABLE { NULL, 0 } +#else +#define SECUREC_INIT_BRACKET_TABLE { {0}, 0 } +#endif + +#if SECUREC_ENABLE_SCANF_FLOAT +typedef struct { + size_t floatStrTotalLen; /* Initialization must be length of buffer in charater */ + size_t floatStrUsedLen; /* Store float string len */ + SecChar *floatStr; /* Initialization must point to buffer */ + SecChar *allocatedFloatStr; /* Initialization must be NULL to store alloced point */ + SecChar buffer[SECUREC_FLOAT_BUFSIZE + 1]; +} SecFloatSpec; +#endif + +#define SECUREC_NUMBER_STATE_DEFAULT 0U +#define SECUREC_NUMBER_STATE_STARTED 1U + +typedef struct { + SecInt ch; /* Char read from input */ + int charCount; /* Number of characters processed */ + void *argPtr; /* Variable parameter pointer, point to the end of the string */ + size_t arrayWidth; /* Length of pointer Variable parameter, in charaters */ + SecUnsignedInt64 number64; /* Store input number64 value */ + unsigned long number; /* Store input number32 value */ + int numberWidth; /* 0 = SHORT, 1 = int, > 1 long or L_DOUBLE */ + int numberArgType; /* 1 for 64-bit integer, 0 otherwise. use it as decode function index */ + unsigned int negative; /* 0 is positive */ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + unsigned int beyondMax; /* Non-zero means beyond */ +#endif + unsigned int numberState; /* Identifies whether to start processing numbers, 1 is can input number */ + int width; /* Width number in format */ + int widthSet; /* 0 is not set width in format */ + int convChr; /* Lowercase format conversion characters */ + int oriConvChr; /* Store original format conversion, convChr may change when parsing integers */ + signed char isWCharOrLong; /* -1/0 not wchar or long, 1 for wchar or long */ + unsigned char suppress; /* 0 is not have %* in format */ +} SecScanSpec; + +#ifdef SECUREC_FOR_WCHAR +#define SECUREC_GETC fgetwc +#define SECUREC_UN_GETC ungetwc +/* Only supports wide characters with a maximum length of two bytes in format string */ +#define SECUREC_BRACKET_CHAR_MASK 0xffffU +#else +#define SECUREC_GETC fgetc +#define SECUREC_UN_GETC ungetc +#define SECUREC_BRACKET_CHAR_MASK 0xffU +#endif + +#define SECUREC_CHAR_SIZE ((unsigned int)(sizeof(SecChar))) +/* To avoid 648, mask high bit: 0x00ffffff 0x0000ffff or 0x00000000 */ +#define SECUREC_CHAR_MASK_HIGH (((((((((unsigned int)(-1) >> SECUREC_CHAR_SIZE) >> SECUREC_CHAR_SIZE) >> \ + SECUREC_CHAR_SIZE) >> SECUREC_CHAR_SIZE) >> \ + SECUREC_CHAR_SIZE) >> SECUREC_CHAR_SIZE) >> \ + SECUREC_CHAR_SIZE) >> SECUREC_CHAR_SIZE) + +/* For char is 0xff, wcahr_t is 0xffff or 0xffffffff. */ +#define SECUREC_CHAR_MASK (~((((((((((unsigned int)(-1) & SECUREC_CHAR_MASK_HIGH) << \ + SECUREC_CHAR_SIZE) << SECUREC_CHAR_SIZE) << \ + SECUREC_CHAR_SIZE) << SECUREC_CHAR_SIZE) << \ + SECUREC_CHAR_SIZE) << SECUREC_CHAR_SIZE) << \ + SECUREC_CHAR_SIZE) << SECUREC_CHAR_SIZE)) + +/* According wchar_t has multiple bytes, so use sizeof */ +#define SECUREC_GET_CHAR(stream, outCh) do { \ + if ((stream)->count >= sizeof(SecChar)) { \ + *(outCh) = (SecInt)(SECUREC_CHAR_MASK & \ + (unsigned int)(int)(*((const SecChar *)(const void *)(stream)->cur))); \ + (stream)->cur += sizeof(SecChar); \ + (stream)->count -= sizeof(SecChar); \ + } else { \ + *(outCh) = SECUREC_EOF; \ + } \ +} SECUREC_WHILE_ZERO + +#define SECUREC_UN_GET_CHAR(stream) do { \ + if ((stream)->cur > (stream)->base) { \ + (stream)->cur -= sizeof(SecChar); \ + (stream)->count += sizeof(SecChar); \ + } \ +} SECUREC_WHILE_ZERO + +/* Convert wchar_t to int and then to unsigned int to keep data clearing warning */ +#define SECUREC_TO_LOWERCASE(chr) ((int)((unsigned int)(int)(chr) | (unsigned int)('a' - 'A'))) + +/* Record a flag for each bit */ +#define SECUREC_BRACKET_INDEX(x) ((unsigned int)(x) >> 3U) +#define SECUREC_BRACKET_VALUE(x) ((unsigned char)(1U << ((unsigned int)(x) & 7U))) +#if SECUREC_IN_KERNEL +#define SECUREC_CONVERT_IS_UNSIGNED(conv) ((conv) == 'x' || (conv) == 'o' || (conv) == 'u') +#endif + +/* + * Set char in %[xxx] into table, only supports wide characters with a maximum length of two bytes + */ +SECUREC_INLINE void SecBracketSetBit(unsigned char *table, SecUnsignedChar ch) +{ + unsigned int tableIndex = SECUREC_BRACKET_INDEX(((unsigned int)(int)ch & SECUREC_BRACKET_CHAR_MASK)); + unsigned int tableValue = SECUREC_BRACKET_VALUE(((unsigned int)(int)ch & SECUREC_BRACKET_CHAR_MASK)); + /* Do not use |= optimize this code, it will cause compiling warning */ + table[tableIndex] = (unsigned char)(table[tableIndex] | tableValue); +} + +SECUREC_INLINE void SecBracketSetBitRange(unsigned char *table, SecUnsignedChar startCh, SecUnsignedChar endCh) +{ + SecUnsignedChar expCh; + /* %[a-z] %[a-a] Format %[a-\xff] end is 0xFF, condition (expCh <= endChar) cause dead loop */ + for (expCh = startCh; expCh < endCh; ++expCh) { + SecBracketSetBit(table, expCh); + } + SecBracketSetBit(table, endCh); +} +/* + * Determine whether the expression can be satisfied + */ +SECUREC_INLINE int SecCanInputForBracket(int convChr, SecInt ch, const SecBracketTable *bracketTable) +{ + unsigned int tableIndex = SECUREC_BRACKET_INDEX(((unsigned int)(int)ch & SECUREC_BRACKET_CHAR_MASK)); + unsigned int tableValue = SECUREC_BRACKET_VALUE(((unsigned int)(int)ch & SECUREC_BRACKET_CHAR_MASK)); +#ifdef SECUREC_FOR_WCHAR + if (((unsigned int)(int)ch & (~(SECUREC_BRACKET_CHAR_MASK))) != 0) { + /* The value of the wide character exceeds the size of two bytes */ + return 0; + } + return (int)(convChr == SECUREC_BRACE && + (((unsigned int)bracketTable->table[tableIndex] ^ (unsigned int)bracketTable->mask) & tableValue) != 0); +#else + return (int)(convChr == SECUREC_BRACE && + (((unsigned int)bracketTable->table[tableIndex] ^ (unsigned int)bracketTable->mask) & tableValue) != 0); +#endif +} + +/* + * String input ends when blank character is encountered + */ +SECUREC_INLINE int SecCanInputString(int convChr, SecInt ch) +{ + return (int)(convChr == 's' && + (!(ch >= SECUREC_CHAR('\t') && ch <= SECUREC_CHAR('\r')) && ch != SECUREC_CHAR(' '))); +} + +/* + * Can input a character when format is %c + */ +SECUREC_INLINE int SecCanInputCharacter(int convChr) +{ + return (int)(convChr == 'c'); +} + +/* + * Determine if it is a 64-bit pointer function + * Return 0 is not ,1 is 64bit pointer + */ +SECUREC_INLINE int SecNumberArgType(size_t sizeOfVoidStar) +{ + /* Point size is 4 or 8 , Under the 64 bit system, the value not 0 */ + /* To clear e778 */ + if ((sizeOfVoidStar & sizeof(SecInt64)) != 0) { + return 1; + } + return 0; +} +SECUREC_INLINE int SecIsDigit(SecInt ch); +SECUREC_INLINE int SecIsXdigit(SecInt ch); +SECUREC_INLINE int SecIsSpace(SecInt ch); +SECUREC_INLINE SecInt SecSkipSpaceChar(SecFileStream *stream, int *counter); +SECUREC_INLINE SecInt SecGetChar(SecFileStream *stream, int *counter); +SECUREC_INLINE void SecUnGetChar(SecInt ch, SecFileStream *stream, int *counter); + +#if SECUREC_ENABLE_SCANF_FLOAT + +/* + * Convert a floating point string to a floating point number + */ +SECUREC_INLINE int SecAssignNarrowFloat(const char *floatStr, const SecScanSpec *spec) +{ + char *endPtr = NULL; + double d; +#if SECUREC_SUPPORT_STRTOLD + if (spec->numberWidth == SECUREC_NUM_WIDTH_LONG_LONG) { + long double d2 = strtold(floatStr, &endPtr); + if (endPtr == floatStr) { + return -1; + } + *(long double UNALIGNED *)(spec->argPtr) = d2; + return 0; + } +#endif + d = strtod(floatStr, &endPtr); + /* cannot detect if endPtr points to the end of floatStr,because strtod handles only two characters for 1.E */ + if (endPtr == floatStr) { + return -1; + } + if (spec->numberWidth > SECUREC_NUM_WIDTH_INT) { + *(double UNALIGNED *)(spec->argPtr) = (double)d; + } else { + *(float UNALIGNED *)(spec->argPtr) = (float)d; + } + return 0; +} + +#ifdef SECUREC_FOR_WCHAR +/* + * Convert a floating point wchar string to a floating point number + * Success ret 0 + */ +SECUREC_INLINE int SecAssignWideFloat(const SecFloatSpec *floatSpec, const SecScanSpec *spec) +{ + int retVal; + /* Convert float string */ + size_t mbsLen; + size_t tempFloatStrLen = (size_t)(floatSpec->floatStrUsedLen + 1) * sizeof(wchar_t); + char *tempFloatStr = (char *)SECUREC_MALLOC(tempFloatStrLen); + if (tempFloatStr == NULL) { + return -1; + } + tempFloatStr[0] = '\0'; + SECUREC_MASK_MSVC_CRT_WARNING + mbsLen = wcstombs(tempFloatStr, floatSpec->floatStr, tempFloatStrLen - 1); + SECUREC_END_MASK_MSVC_CRT_WARNING + /* This condition must satisfy mbsLen is not -1 */ + if (mbsLen >= tempFloatStrLen) { + SECUREC_FREE(tempFloatStr); + return -1; + } + tempFloatStr[mbsLen] = '\0'; + retVal = SecAssignNarrowFloat(tempFloatStr, spec); + SECUREC_FREE(tempFloatStr); + return retVal; +} +#endif + +SECUREC_INLINE int SecAssignFloat(const SecFloatSpec *floatSpec, const SecScanSpec *spec) +{ +#ifdef SECUREC_FOR_WCHAR + return SecAssignWideFloat(floatSpec, spec); +#else + return SecAssignNarrowFloat(floatSpec->floatStr, spec); +#endif +} + +/* + * Init SecFloatSpec before parse format + */ +SECUREC_INLINE void SecInitFloatSpec(SecFloatSpec *floatSpec) +{ + floatSpec->floatStr = floatSpec->buffer; + floatSpec->allocatedFloatStr = NULL; + floatSpec->floatStrTotalLen = sizeof(floatSpec->buffer) / sizeof(floatSpec->buffer[0]); + floatSpec->floatStrUsedLen = 0; +} + +SECUREC_INLINE void SecFreeFloatSpec(SecFloatSpec *floatSpec, int *doneCount) +{ + /* 2014.3.6 add, clear the stack data */ + if (memset_s(floatSpec->buffer, sizeof(floatSpec->buffer), 0, sizeof(floatSpec->buffer)) != EOK) { + *doneCount = 0; /* This code just to meet the coding requirements */ + } + /* The pFloatStr can be alloced in SecExtendFloatLen function, clear and free it */ + if (floatSpec->allocatedFloatStr != NULL) { + size_t bufferSize = floatSpec->floatStrTotalLen * sizeof(SecChar); + if (memset_s(floatSpec->allocatedFloatStr, bufferSize, 0, bufferSize) != EOK) { + *doneCount = 0; /* This code just to meet the coding requirements */ + } + SECUREC_FREE(floatSpec->allocatedFloatStr); + floatSpec->allocatedFloatStr = NULL; + floatSpec->floatStr = NULL; + } +} + +/* + * Splice floating point string + * Return 0 OK + */ +SECUREC_INLINE int SecExtendFloatLen(SecFloatSpec *floatSpec) +{ + if (floatSpec->floatStrUsedLen >= floatSpec->floatStrTotalLen) { + /* Buffer size is len x sizeof(SecChar) */ + size_t oriSize = floatSpec->floatStrTotalLen * sizeof(SecChar); + /* Add one character to clear tool warning */ + size_t nextSize = (oriSize * 2) + sizeof(SecChar); /* Multiply 2 to extend buffer size */ + + /* Prevents integer overflow, the maximum length of SECUREC_MAX_WIDTH_LEN is enough */ + if (nextSize <= (size_t)SECUREC_MAX_WIDTH_LEN) { + void *nextBuffer = (void *)SECUREC_MALLOC(nextSize); + if (nextBuffer == NULL) { + return -1; + } + if (memcpy_s(nextBuffer, nextSize, floatSpec->floatStr, oriSize) != EOK) { + SECUREC_FREE(nextBuffer); /* This is a dead code, just to meet the coding requirements */ + return -1; + } + /* Clear old buffer memory */ + if (memset_s(floatSpec->floatStr, oriSize, 0, oriSize) != EOK) { + SECUREC_FREE(nextBuffer); /* This is a dead code, just to meet the coding requirements */ + return -1; + } + /* Free old allocated buffer */ + if (floatSpec->allocatedFloatStr != NULL) { + SECUREC_FREE(floatSpec->allocatedFloatStr); + } + floatSpec->allocatedFloatStr = (SecChar *)(nextBuffer); /* Use to clear free on stack warning */ + floatSpec->floatStr = (SecChar *)(nextBuffer); + floatSpec->floatStrTotalLen = nextSize / sizeof(SecChar); /* Get buffer total len in character */ + return 0; + } + return -1; /* Next size is beyond max */ + } + return 0; +} + +/* Do not use localeconv()->decimal_pointif only support '.' */ +SECUREC_INLINE int SecIsFloatDecimal(SecChar ch) +{ + return (int)(ch == SECUREC_CHAR('.')); +} + +SECUREC_INLINE int SecInputFloatSign(SecFileStream *stream, SecScanSpec *spec, SecFloatSpec *floatSpec) +{ + if (!SECUREC_FILED_WIDTH_ENOUGH(spec)) { + return 0; + } + spec->ch = SecGetChar(stream, &(spec->charCount)); + if (spec->ch == SECUREC_CHAR('+') || spec->ch == SECUREC_CHAR('-')) { + SECUREC_FILED_WIDTH_DEC(spec); /* Make sure the count after un get char is correct */ + if (spec->ch == SECUREC_CHAR('-')) { + floatSpec->floatStr[floatSpec->floatStrUsedLen] = SECUREC_CHAR('-'); + ++floatSpec->floatStrUsedLen; + if (SecExtendFloatLen(floatSpec) != 0) { + return -1; + } + } + } else { + SecUnGetChar(spec->ch, stream, &(spec->charCount)); + } + return 0; +} + +SECUREC_INLINE int SecInputFloatDigit(SecFileStream *stream, SecScanSpec *spec, SecFloatSpec *floatSpec) +{ + /* Now get integral part */ + while (SECUREC_FILED_WIDTH_ENOUGH(spec)) { + spec->ch = SecGetChar(stream, &(spec->charCount)); + if (SecIsDigit(spec->ch) == 0) { + SecUnGetChar(spec->ch, stream, &(spec->charCount)); + return 0; + } + SECUREC_FILED_WIDTH_DEC(spec); /* Must be behind un get char, otherwise the logic is incorrect */ + spec->numberState = SECUREC_NUMBER_STATE_STARTED; + floatSpec->floatStr[floatSpec->floatStrUsedLen] = (SecChar)spec->ch; + ++floatSpec->floatStrUsedLen; + if (SecExtendFloatLen(floatSpec) != 0) { + return -1; + } + } + return 0; +} + +/* +* Scan value of exponent. +* Return 0 OK +*/ +SECUREC_INLINE int SecInputFloatE(SecFileStream *stream, SecScanSpec *spec, SecFloatSpec *floatSpec) +{ + if (SecInputFloatSign(stream, spec, floatSpec) == -1) { + return -1; + } + if (SecInputFloatDigit(stream, spec, floatSpec) != 0) { + return -1; + } + return 0; +} + +SECUREC_INLINE int SecInputFloatFractional(SecFileStream *stream, SecScanSpec *spec, SecFloatSpec *floatSpec) +{ + if (SECUREC_FILED_WIDTH_ENOUGH(spec)) { + spec->ch = SecGetChar(stream, &(spec->charCount)); + if (SecIsFloatDecimal((SecChar)spec->ch) == 0) { + SecUnGetChar(spec->ch, stream, &(spec->charCount)); + return 0; + } + SECUREC_FILED_WIDTH_DEC(spec); /* Must be behind un get char, otherwise the logic is incorrect */ + /* Now check for decimal */ + floatSpec->floatStr[floatSpec->floatStrUsedLen] = (SecChar)spec->ch; + ++floatSpec->floatStrUsedLen; + if (SecExtendFloatLen(floatSpec) != 0) { + return -1; + } + if (SecInputFloatDigit(stream, spec, floatSpec) != 0) { + return -1; + } + } + return 0; +} + +SECUREC_INLINE int SecInputFloatExponent(SecFileStream *stream, SecScanSpec *spec, SecFloatSpec *floatSpec) +{ + /* Now get exponent part */ + if (spec->numberState == SECUREC_NUMBER_STATE_STARTED && SECUREC_FILED_WIDTH_ENOUGH(spec)) { + spec->ch = SecGetChar(stream, &(spec->charCount)); + if (spec->ch != SECUREC_CHAR('e') && spec->ch != SECUREC_CHAR('E')) { + SecUnGetChar(spec->ch, stream, &(spec->charCount)); + return 0; + } + SECUREC_FILED_WIDTH_DEC(spec); /* Must be behind un get char, otherwise the logic is incorrect */ + floatSpec->floatStr[floatSpec->floatStrUsedLen] = SECUREC_CHAR('e'); + ++floatSpec->floatStrUsedLen; + if (SecExtendFloatLen(floatSpec) != 0) { + return -1; + } + if (SecInputFloatE(stream, spec, floatSpec) != 0) { + return -1; + } + } + return 0; +} + +/* +* Scan %f. +* Return 0 OK +*/ +SECUREC_INLINE int SecInputFloat(SecFileStream *stream, SecScanSpec *spec, SecFloatSpec *floatSpec) +{ + floatSpec->floatStrUsedLen = 0; + + /* The following code sequence is strict */ + if (SecInputFloatSign(stream, spec, floatSpec) != 0) { + return -1; + } + if (SecInputFloatDigit(stream, spec, floatSpec) != 0) { + return -1; + } + if (SecInputFloatFractional(stream, spec, floatSpec) != 0) { + return -1; + } + if (SecInputFloatExponent(stream, spec, floatSpec) != 0) { + return -1; + } + + /* Make sure have a string terminator, buffer is large enough */ + floatSpec->floatStr[floatSpec->floatStrUsedLen] = SECUREC_CHAR('\0'); + if (spec->numberState == SECUREC_NUMBER_STATE_STARTED) { + return 0; + } + return -1; +} +#endif + +#if (!defined(SECUREC_FOR_WCHAR) && SECUREC_HAVE_WCHART && SECUREC_HAVE_MBTOWC) || \ + (!defined(SECUREC_FOR_WCHAR) && defined(SECUREC_COMPATIBLE_VERSION)) +/* only multi-bytes string need isleadbyte() function */ +SECUREC_INLINE int SecIsLeadByte(SecInt ch) +{ + unsigned int c = (unsigned int)ch; +#if !(defined(_MSC_VER) || defined(_INC_WCTYPE)) + return (int)(c & 0x80U); /* Use bitwise operation to check if the most significant bit is 1 */ +#else + return (int)isleadbyte((int)(c & 0xffU)); /* Use bitwise operations to limit character values to valid ranges */ +#endif +} +#endif + +/* + * Parsing whether it is a wide character + */ +SECUREC_INLINE void SecUpdateWcharFlagByType(SecUnsignedChar ch, SecScanSpec *spec) +{ + if (spec->isWCharOrLong != 0) { + /* Wide character identifiers have been explicitly set by l or h flag */ + return; + } + + /* Set default flag */ +#if defined(SECUREC_FOR_WCHAR) && defined(SECUREC_COMPATIBLE_WIN_FORMAT) + spec->isWCharOrLong = 1; /* On windows wide char version %c %s %[ is wide char */ +#else + spec->isWCharOrLong = -1; /* On linux all version %c %s %[ is multi char */ +#endif + + if (ch == SECUREC_CHAR('C') || ch == SECUREC_CHAR('S')) { +#if defined(SECUREC_FOR_WCHAR) && defined(SECUREC_COMPATIBLE_WIN_FORMAT) + spec->isWCharOrLong = -1; /* On windows wide char version %C %S is multi char */ +#else + spec->isWCharOrLong = 1; /* On linux all version %C %S is wide char */ +#endif + } + + return; +} +/* + * Decode %l %ll + */ +SECUREC_INLINE void SecDecodeScanQualifierL(const SecUnsignedChar **format, SecScanSpec *spec) +{ + const SecUnsignedChar *fmt = *format; + if (*(fmt + 1) == SECUREC_CHAR('l')) { + spec->numberArgType = 1; + spec->numberWidth = SECUREC_NUM_WIDTH_LONG_LONG; + ++fmt; + } else { + spec->numberWidth = SECUREC_NUM_WIDTH_LONG; +#if defined(SECUREC_ON_64BITS) && !(defined(SECUREC_COMPATIBLE_WIN_FORMAT)) + /* On window 64 system sizeof long is 32bit */ + spec->numberArgType = 1; +#endif + spec->isWCharOrLong = 1; + } + *format = fmt; +} + +/* + * Decode %I %I43 %I64 %Id %Ii %Io ... + * Set finishFlag to 1 finish Flag + */ +SECUREC_INLINE void SecDecodeScanQualifierI(const SecUnsignedChar **format, SecScanSpec *spec, int *finishFlag) +{ + const SecUnsignedChar *fmt = *format; + if ((*(fmt + 1) == SECUREC_CHAR('6')) && + (*(fmt + 2) == SECUREC_CHAR('4'))) { /* Offset 2 for I64 */ + spec->numberArgType = 1; + *format = *format + 2; /* Add 2 to skip I64 point to '4' next loop will inc */ + } else if ((*(fmt + 1) == SECUREC_CHAR('3')) && + (*(fmt + 2) == SECUREC_CHAR('2'))) { /* Offset 2 for I32 */ + *format = *format + 2; /* Add 2 to skip I32 point to '2' next loop will inc */ + } else if ((*(fmt + 1) == SECUREC_CHAR('d')) || + (*(fmt + 1) == SECUREC_CHAR('i')) || + (*(fmt + 1) == SECUREC_CHAR('o')) || + (*(fmt + 1) == SECUREC_CHAR('x')) || + (*(fmt + 1) == SECUREC_CHAR('X'))) { + spec->numberArgType = SecNumberArgType(sizeof(void *)); + } else { + /* For %I */ + spec->numberArgType = SecNumberArgType(sizeof(void *)); + *finishFlag = 1; + } +} + +SECUREC_INLINE int SecDecodeScanWidth(const SecUnsignedChar **format, SecScanSpec *spec) +{ + const SecUnsignedChar *fmt = *format; + while (SecIsDigit((SecInt)(int)(*fmt)) != 0) { + spec->widthSet = 1; + if (SECUREC_MUL_TEN_ADD_BEYOND_MAX(spec->width)) { + return -1; + } + spec->width = (int)SECUREC_MUL_TEN((unsigned int)spec->width) + (unsigned char)(*fmt - SECUREC_CHAR('0')); + ++fmt; + } + *format = fmt; + return 0; +} + +/* + * Init default flags for each format. do not init ch this variable is context-dependent + */ +SECUREC_INLINE void SecSetDefaultScanSpec(SecScanSpec *spec) +{ + /* The ch and charCount member variables cannot be initialized here */ + spec->argPtr = NULL; + spec->arrayWidth = 0; + spec->number64 = 0; + spec->number = 0; + spec->numberWidth = SECUREC_NUM_WIDTH_INT; /* 0 = SHORT, 1 = int, > 1 long or L_DOUBLE */ + spec->numberArgType = 0; /* 1 for 64-bit integer, 0 otherwise */ + spec->width = 0; + spec->widthSet = 0; + spec->convChr = 0; + spec->oriConvChr = 0; + spec->isWCharOrLong = 0; + spec->suppress = 0; +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + spec->beyondMax = 0; +#endif + spec->negative = 0; + spec->numberState = SECUREC_NUMBER_STATE_DEFAULT; +} + +/* + * Decode qualifier %I %L %h ... + * Set finishFlag to 1 finish Flag + */ +SECUREC_INLINE void SecDecodeScanQualifier(const SecUnsignedChar **format, SecScanSpec *spec, int *finishFlag) +{ + switch (**format) { + case SECUREC_CHAR('F'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('N'): + break; + case SECUREC_CHAR('h'): + --spec->numberWidth; /* The h for SHORT , hh for CHAR */ + spec->isWCharOrLong = -1; + break; +#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT + case SECUREC_CHAR('j'): + spec->numberWidth = SECUREC_NUM_WIDTH_LONG_LONG; /* For intmax_t or uintmax_t */ + spec->numberArgType = 1; + break; + case SECUREC_CHAR('t'): /* fall-through */ /* FALLTHRU */ +#endif +#if SECUREC_IN_KERNEL + case SECUREC_CHAR('Z'): /* fall-through */ /* FALLTHRU */ +#endif + case SECUREC_CHAR('z'): +#ifdef SECUREC_ON_64BITS + spec->numberWidth = SECUREC_NUM_WIDTH_LONG_LONG; + spec->numberArgType = 1; +#else + spec->numberWidth = SECUREC_NUM_WIDTH_LONG; +#endif + break; + case SECUREC_CHAR('L'): /* For long double */ /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('q'): + spec->numberWidth = SECUREC_NUM_WIDTH_LONG_LONG; + spec->numberArgType = 1; + break; + case SECUREC_CHAR('l'): + SecDecodeScanQualifierL(format, spec); + break; + case SECUREC_CHAR('w'): + spec->isWCharOrLong = 1; + break; + case SECUREC_CHAR('*'): + spec->suppress = 1; + break; + case SECUREC_CHAR('I'): + SecDecodeScanQualifierI(format, spec, finishFlag); + break; + default: + *finishFlag = 1; + break; + } +} +/* + * Decode width and qualifier in format + */ +SECUREC_INLINE int SecDecodeScanFlag(const SecUnsignedChar **format, SecScanSpec *spec) +{ + const SecUnsignedChar *fmt = *format; + int finishFlag = 0; + + do { + ++fmt; /* First skip % , next seek fmt */ + /* May %*6d , so put it inside the loop */ + if (SecDecodeScanWidth(&fmt, spec) != 0) { + return -1; + } + SecDecodeScanQualifier(&fmt, spec, &finishFlag); + } while (finishFlag == 0); + *format = fmt; + return 0; +} + +/* + * Judging whether a zeroing buffer is needed according to different formats + */ +SECUREC_INLINE int SecDecodeClearFormat(const SecUnsignedChar *format, int *convChr) +{ + const SecUnsignedChar *fmt = format; + /* To lowercase */ + int ch = SECUREC_TO_LOWERCASE(*fmt); + if (!(ch == 'c' || ch == 's' || ch == SECUREC_BRACE)) { + return -1; /* First argument is not a string type */ + } + if (ch == SECUREC_BRACE) { +#if !(defined(SECUREC_COMPATIBLE_WIN_FORMAT)) + if (*fmt == SECUREC_CHAR('{')) { + return -1; + } +#endif + ++fmt; + if (*fmt == SECUREC_CHAR('^')) { + ++fmt; + } + if (*fmt == SECUREC_CHAR(']')) { + ++fmt; + } + while (*fmt != SECUREC_CHAR('\0') && *fmt != SECUREC_CHAR(']')) { + ++fmt; + } + if (*fmt == SECUREC_CHAR('\0')) { + return -1; /* Trunc'd format string */ + } + } + *convChr = ch; + return 0; +} + +/* + * Add L'\0' for wchar string , add '\0' for char string + */ +SECUREC_INLINE void SecAddEndingZero(void *ptr, const SecScanSpec *spec) +{ + if (spec->suppress == 0) { + *(char *)ptr = '\0'; +#if SECUREC_HAVE_WCHART + if (spec->isWCharOrLong > 0) { + *(wchar_t UNALIGNED *)ptr = L'\0'; + } +#endif + } +} + +SECUREC_INLINE void SecDecodeClearArg(SecScanSpec *spec, va_list argList) +{ + va_list argListSave; /* Backup for argList value, this variable don't need initialized */ + (void)SECUREC_MEMSET_FUNC_OPT(&argListSave, 0, sizeof(va_list)); /* To clear e530 argListSave not initialized */ +#if defined(va_copy) + va_copy(argListSave, argList); +#elif defined(__va_copy) /* For vxworks */ + __va_copy(argListSave, argList); +#else + argListSave = argList; +#endif + spec->argPtr = (void *)va_arg(argListSave, void *); + /* Get the next argument, size of the array in characters */ + /* Use 0xffffffffUL mask to Support pass integer as array length */ + spec->arrayWidth = ((size_t)(va_arg(argListSave, size_t))) & 0xffffffffUL; + va_end(argListSave); + /* To clear e438 last value assigned not used , the compiler will optimize this code */ + (void)argListSave; +} + +#ifdef SECUREC_FOR_WCHAR +/* + * Clean up the first %s %c buffer to zero for wchar version + */ +void SecClearDestBufW(const wchar_t *buffer, const wchar_t *format, va_list argList) +#else +/* + * Clean up the first %s %c buffer to zero for char version + */ +void SecClearDestBuf(const char *buffer, const char *format, va_list argList) +#endif +{ + SecScanSpec spec; + int convChr = 0; + const SecUnsignedChar *fmt = (const SecUnsignedChar *)format; + + /* Find first % */ + while (*fmt != SECUREC_CHAR('\0') && *fmt != SECUREC_CHAR('%')) { + ++fmt; + } + if (*fmt == SECUREC_CHAR('\0')) { + return; + } + + SecSetDefaultScanSpec(&spec); + if (SecDecodeScanFlag(&fmt, &spec) != 0) { + return; + } + + /* Update wchar flag for %S %C */ + SecUpdateWcharFlagByType(*fmt, &spec); + if (spec.suppress != 0) { + return; + } + + if (SecDecodeClearFormat(fmt, &convChr) != 0) { + return; + } + + if (*buffer != SECUREC_CHAR('\0') && convChr != 's') { + /* + * When buffer not empty just clear %s. + * Example call sscanf by argment of (" \n", "%s", s, sizeof(s)) + */ + return; + } + + SecDecodeClearArg(&spec, argList); + /* There is no need to judge the upper limit */ + if (spec.arrayWidth == 0 || spec.argPtr == NULL) { + return; + } + /* Clear one char */ + SecAddEndingZero(spec.argPtr, &spec); + return; +} + +/* + * Assign number to output buffer + */ +SECUREC_INLINE void SecAssignNumber(const SecScanSpec *spec) +{ + void *argPtr = spec->argPtr; + if (spec->numberArgType != 0) { +#if defined(SECUREC_VXWORKS_PLATFORM) +#if defined(SECUREC_VXWORKS_PLATFORM_COMP) + *(SecInt64 UNALIGNED *)argPtr = (SecInt64)(spec->number64); +#else + /* Take number64 as unsigned number unsigned to int clear Compile warning */ + *(SecInt64 UNALIGNED *)argPtr = *(SecUnsignedInt64 *)(&(spec->number64)); +#endif +#else + /* Take number64 as unsigned number */ + *(SecInt64 UNALIGNED *)argPtr = (SecInt64)(spec->number64); +#endif + return; + } + if (spec->numberWidth > SECUREC_NUM_WIDTH_INT) { + /* Take number as unsigned number */ + *(long UNALIGNED *)argPtr = (long)(spec->number); + } else if (spec->numberWidth == SECUREC_NUM_WIDTH_INT) { + *(int UNALIGNED *)argPtr = (int)(spec->number); + } else if (spec->numberWidth == SECUREC_NUM_WIDTH_SHORT) { + /* Take number as unsigned number */ + *(short UNALIGNED *)argPtr = (short)(spec->number); + } else { /* < 0 for hh format modifier */ + /* Take number as unsigned number */ + *(char UNALIGNED *)argPtr = (char)(spec->number); + } +} + +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) +/* + * Judge the long bit width + */ +SECUREC_INLINE int SecIsLongBitEqual(int bitNum) +{ + return (int)((unsigned int)bitNum == SECUREC_LONG_BIT_NUM); +} +#endif + +/* + * Convert hexadecimal characters to decimal value + */ +SECUREC_INLINE int SecHexValueOfChar(SecInt ch) +{ + /* Use isdigit Causing tool false alarms */ + return (int)((ch >= '0' && ch <= '9') ? ((unsigned char)ch - '0') : + ((((unsigned char)ch | (unsigned char)('a' - 'A')) - ('a')) + 10)); /* Adding 10 is to hex value */ +} + +/* + * Parse decimal character to integer for 32bit . + */ +static void SecDecodeNumberDecimal(SecScanSpec *spec) +{ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + unsigned long decimalEdge = SECUREC_MAX_32BITS_VALUE_DIV_TEN; +#ifdef SECUREC_ON_64BITS + if (SecIsLongBitEqual(SECUREC_LP64_BIT_WIDTH) != 0) { + decimalEdge = (unsigned long)SECUREC_MAX_64BITS_VALUE_DIV_TEN; + } +#endif + if (spec->number > decimalEdge) { + spec->beyondMax = 1; + } +#endif + spec->number = SECUREC_MUL_TEN(spec->number); +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + if (spec->number == SECUREC_MUL_TEN(decimalEdge)) { + /* This code is specially converted to unsigned long type for compatibility */ + SecUnsignedInt64 number64As = (unsigned long)SECUREC_MAX_64BITS_VALUE - spec->number; + if (number64As < (SecUnsignedInt64)(SecUnsignedInt)spec->ch - (SecUnsignedInt)SECUREC_CHAR('0')) { + spec->beyondMax = 1; + } + } +#endif + spec->number += ((unsigned long)(SecUnsignedInt)spec->ch - (SecUnsignedInt)SECUREC_CHAR('0')); +} + +/* + * Parse Hex character to integer for 32bit . + */ +static void SecDecodeNumberHex(SecScanSpec *spec) +{ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + if (SECUREC_LONG_HEX_BEYOND_MAX(spec->number)) { + spec->beyondMax = 1; + } +#endif + spec->number = SECUREC_MUL_SIXTEEN(spec->number); + spec->number += (unsigned long)(unsigned int)SecHexValueOfChar(spec->ch); +} + +/* + * Parse Octal character to integer for 32bit . + */ +static void SecDecodeNumberOctal(SecScanSpec *spec) +{ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + if (SECUREC_LONG_OCTAL_BEYOND_MAX(spec->number)) { + spec->beyondMax = 1; + } +#endif + spec->number = SECUREC_MUL_EIGHT(spec->number); + spec->number += ((unsigned long)(SecUnsignedInt)spec->ch - (SecUnsignedInt)SECUREC_CHAR('0')); +} + +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) +/* Compatible with integer negative values other than int */ +SECUREC_INLINE void SecFinishNumberNegativeOther(SecScanSpec *spec) +{ + if (SECUREC_CONVERT_IS_SIGNED(spec->oriConvChr)) { + if (spec->number > SECUREC_MIN_LONG_NEG_VALUE) { + spec->number = SECUREC_MIN_LONG_NEG_VALUE; + } else { + spec->number = (unsigned long)(0U - spec->number); /* Wrap with unsigned long numbers */ + } + if (spec->beyondMax != 0) { + if (spec->numberWidth < SECUREC_NUM_WIDTH_INT) { + spec->number = 0; + } + if (spec->numberWidth == SECUREC_NUM_WIDTH_LONG) { + spec->number = SECUREC_MIN_LONG_NEG_VALUE; + } + } + } else { /* For o, u, x, X, p */ + spec->number = (unsigned long)(0U - spec->number); /* Wrap with unsigned long numbers */ + if (spec->beyondMax != 0) { + spec->number = (unsigned long)SECUREC_MAX_64BITS_VALUE; + } + } +} +/* Compatible processing of integer negative numbers */ +SECUREC_INLINE void SecFinishNumberNegativeInt(SecScanSpec *spec) +{ + if (SECUREC_CONVERT_IS_SIGNED(spec->oriConvChr)) { +#ifdef SECUREC_ON_64BITS + if (SecIsLongBitEqual(SECUREC_LP64_BIT_WIDTH) != 0) { + if ((spec->number > SECUREC_MIN_64BITS_NEG_VALUE)) { + spec->number = 0; + } else { + spec->number = (unsigned int)(0U - (unsigned int)spec->number); /* Wrap with unsigned int numbers */ + } + } +#else + if (SecIsLongBitEqual(SECUREC_LP32_BIT_WIDTH) != 0) { + if ((spec->number > SECUREC_MIN_32BITS_NEG_VALUE)) { + spec->number = SECUREC_MIN_32BITS_NEG_VALUE; + } else { + spec->number = (unsigned int)(0U - (unsigned int)spec->number); /* Wrap with unsigned int numbers */ + } + } +#endif + if (spec->beyondMax != 0) { +#ifdef SECUREC_ON_64BITS + if (SecIsLongBitEqual(SECUREC_LP64_BIT_WIDTH) != 0) { + spec->number = 0; + } +#else + if (SecIsLongBitEqual(SECUREC_LP32_BIT_WIDTH) != 0) { + spec->number = SECUREC_MIN_32BITS_NEG_VALUE; + } +#endif + } + } else { /* For o, u, x, X ,p */ +#ifdef SECUREC_ON_64BITS + if (spec->number > SECUREC_MAX_32BITS_VALUE_INC) { + spec->number = SECUREC_MAX_32BITS_VALUE; + } else { + spec->number = (unsigned int)(0U - (unsigned int)spec->number); /* Wrap with unsigned int numbers */ + } +#else + spec->number = (unsigned int)(0U - (unsigned int)spec->number); /* Wrap with unsigned int numbers */ +#endif + if (spec->beyondMax != 0) { + spec->number = (unsigned long)SECUREC_MAX_64BITS_VALUE; + } + } +} + +/* Compatible with integer positive values other than int */ +SECUREC_INLINE void SecFinishNumberPositiveOther(SecScanSpec *spec) +{ + if (SECUREC_CONVERT_IS_SIGNED(spec->oriConvChr)) { + if (spec->number > SECUREC_MAX_LONG_POS_VALUE) { + spec->number = SECUREC_MAX_LONG_POS_VALUE; + } + if ((spec->beyondMax != 0 && spec->numberWidth < SECUREC_NUM_WIDTH_INT)) { + spec->number = (unsigned long)SECUREC_MAX_64BITS_VALUE; + } + if (spec->beyondMax != 0 && spec->numberWidth == SECUREC_NUM_WIDTH_LONG) { + spec->number = SECUREC_MAX_LONG_POS_VALUE; + } + } else { + if (spec->beyondMax != 0) { + spec->number = (unsigned long)SECUREC_MAX_64BITS_VALUE; + } + } +} + +/* Compatible processing of integer positive numbers */ +SECUREC_INLINE void SecFinishNumberPositiveInt(SecScanSpec *spec) +{ + if (SECUREC_CONVERT_IS_SIGNED(spec->oriConvChr)) { +#ifdef SECUREC_ON_64BITS + if (SecIsLongBitEqual(SECUREC_LP64_BIT_WIDTH) != 0) { + if (spec->number > SECUREC_MAX_64BITS_POS_VALUE) { + spec->number = (unsigned long)SECUREC_MAX_64BITS_VALUE; + } + } + if (spec->beyondMax != 0 && SecIsLongBitEqual(SECUREC_LP64_BIT_WIDTH) != 0) { + spec->number = (unsigned long)SECUREC_MAX_64BITS_VALUE; + } +#else + if (SecIsLongBitEqual(SECUREC_LP32_BIT_WIDTH) != 0) { + if (spec->number > SECUREC_MAX_32BITS_POS_VALUE) { + spec->number = SECUREC_MAX_32BITS_POS_VALUE; + } + } + if (spec->beyondMax != 0 && SecIsLongBitEqual(SECUREC_LP32_BIT_WIDTH) != 0) { + spec->number = SECUREC_MAX_32BITS_POS_VALUE; + } +#endif + } else { /* For o,u,x,X,p */ + if (spec->beyondMax != 0) { + spec->number = SECUREC_MAX_32BITS_VALUE; + } + } +} + +#endif + +/* + * Parse decimal character to integer for 64bit . + */ +static void SecDecodeNumber64Decimal(SecScanSpec *spec) +{ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + if (spec->number64 > SECUREC_MAX_64BITS_VALUE_DIV_TEN) { + spec->beyondMax = 1; + } +#endif + spec->number64 = SECUREC_MUL_TEN(spec->number64); +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + if (spec->number64 == SECUREC_MAX_64BITS_VALUE_CUT_LAST_DIGIT) { + SecUnsignedInt64 number64As = (SecUnsignedInt64)SECUREC_MAX_64BITS_VALUE - spec->number64; + if (number64As < (SecUnsignedInt64)(SecUnsignedInt)spec->ch - (SecUnsignedInt)SECUREC_CHAR('0')) { + spec->beyondMax = 1; + } + } +#endif + spec->number64 += ((SecUnsignedInt64)(SecUnsignedInt)spec->ch - (SecUnsignedInt)SECUREC_CHAR('0')); +} + +/* + * Parse Hex character to integer for 64bit . + */ +static void SecDecodeNumber64Hex(SecScanSpec *spec) +{ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + if (SECUREC_QWORD_HEX_BEYOND_MAX(spec->number64)) { + spec->beyondMax = 1; + } +#endif + spec->number64 = SECUREC_MUL_SIXTEEN(spec->number64); + spec->number64 += (SecUnsignedInt64)(unsigned int)SecHexValueOfChar(spec->ch); +} + +/* + * Parse Octal character to integer for 64bit . + */ +static void SecDecodeNumber64Octal(SecScanSpec *spec) +{ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + if (SECUREC_QWORD_OCTAL_BEYOND_MAX(spec->number64)) { + spec->beyondMax = 1; + } +#endif + spec->number64 = SECUREC_MUL_EIGHT(spec->number64); + spec->number64 += ((SecUnsignedInt64)(SecUnsignedInt)spec->ch - (SecUnsignedInt)SECUREC_CHAR('0')); +} + +#define SECUREC_DECODE_NUMBER_FUNC_NUM 2 + +/* + * Parse 64-bit integer formatted input, return 0 when ch is a number. + */ +SECUREC_INLINE int SecDecodeNumber(SecScanSpec *spec) +{ + /* Function name cannot add address symbol, causing 546 alarm */ + static void (* const secDecodeNumberHex[SECUREC_DECODE_NUMBER_FUNC_NUM])(SecScanSpec *spec) = { + SecDecodeNumberHex, SecDecodeNumber64Hex + }; + static void (* const secDecodeNumberOctal[SECUREC_DECODE_NUMBER_FUNC_NUM])(SecScanSpec *spec) = { + SecDecodeNumberOctal, SecDecodeNumber64Octal + }; + static void (* const secDecodeNumberDecimal[SECUREC_DECODE_NUMBER_FUNC_NUM])(SecScanSpec *spec) = { + SecDecodeNumberDecimal, SecDecodeNumber64Decimal + }; + if (spec->convChr == 'x' || spec->convChr == 'p') { + if (SecIsXdigit(spec->ch) != 0) { + (*secDecodeNumberHex[spec->numberArgType])(spec); + } else { + return -1; + } + return 0; + } + if (SecIsDigit(spec->ch) == 0) { + return -1; + } + if (spec->convChr == 'o') { + if (spec->ch < SECUREC_CHAR('8')) { /* Octal maximum limit '8' */ + (*secDecodeNumberOctal[spec->numberArgType])(spec); + } else { + return -1; + } + } else { /* The convChr is 'd' */ + (*secDecodeNumberDecimal[spec->numberArgType])(spec); + } + return 0; +} + +/* + * Complete the final 32-bit integer formatted input + */ +static void SecFinishNumber(SecScanSpec *spec) +{ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + if (spec->negative != 0) { + if (spec->numberWidth == SECUREC_NUM_WIDTH_INT) { + SecFinishNumberNegativeInt(spec); + } else { + SecFinishNumberNegativeOther(spec); + } + } else { + if (spec->numberWidth == SECUREC_NUM_WIDTH_INT) { + SecFinishNumberPositiveInt(spec); + } else { + SecFinishNumberPositiveOther(spec); + } + } +#else + if (spec->negative != 0) { +#if defined(__hpux) + if (spec->oriConvChr != 'p') { + spec->number = (unsigned long)(0U - spec->number); /* Wrap with unsigned long numbers */ + } +#else + spec->number = (unsigned long)(0U - spec->number); /* Wrap with unsigned long numbers */ +#endif + } +#endif + return; +} + +/* + * Complete the final 64-bit integer formatted input + */ +static void SecFinishNumber64(SecScanSpec *spec) +{ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) + if (spec->negative != 0) { + if (SECUREC_CONVERT_IS_SIGNED(spec->oriConvChr)) { + if (spec->number64 > SECUREC_MIN_64BITS_NEG_VALUE) { + spec->number64 = SECUREC_MIN_64BITS_NEG_VALUE; + } else { + spec->number64 = (SecUnsignedInt64)(0U - spec->number64); /* Wrap with unsigned int64 numbers */ + } + if (spec->beyondMax != 0) { + spec->number64 = SECUREC_MIN_64BITS_NEG_VALUE; + } + } else { /* For o, u, x, X, p */ + spec->number64 = (SecUnsignedInt64)(0U - spec->number64); /* Wrap with unsigned int64 numbers */ + if (spec->beyondMax != 0) { + spec->number64 = SECUREC_MAX_64BITS_VALUE; + } + } + } else { + if (SECUREC_CONVERT_IS_SIGNED(spec->oriConvChr)) { + if (spec->number64 > SECUREC_MAX_64BITS_POS_VALUE) { + spec->number64 = SECUREC_MAX_64BITS_POS_VALUE; + } + if (spec->beyondMax != 0) { + spec->number64 = SECUREC_MAX_64BITS_POS_VALUE; + } + } else { + if (spec->beyondMax != 0) { + spec->number64 = SECUREC_MAX_64BITS_VALUE; + } + } + } +#else + if (spec->negative != 0) { +#if defined(__hpux) + if (spec->oriConvChr != 'p') { + spec->number64 = (SecUnsignedInt64)(0U - spec->number64); /* Wrap with unsigned int64 numbers */ + } +#else + spec->number64 = (SecUnsignedInt64)(0U - spec->number64); /* Wrap with unsigned int64 numbers */ +#endif + } +#endif + return; +} + +#if SECUREC_ENABLE_SCANF_FILE + +/* + * Adjust the pointer position of the file stream + */ +SECUREC_INLINE void SecSeekStream(SecFileStream *stream) +{ + if (stream->count == 0) { + if (feof(stream->pf) != 0) { + /* File pointer at the end of file, don't need to seek back */ + stream->base[0] = '\0'; + return; + } + } + /* Seek to original position, for file read, but nothing to input */ + if (fseek(stream->pf, stream->oriFilePos, SEEK_SET) != 0) { + /* Seek failed, ignore it */ + stream->oriFilePos = 0; + return; + } + + if (stream->fileRealRead > 0) { /* Do not seek without input data */ +#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) + size_t residue = stream->fileRealRead % SECUREC_BUFFERED_BLOK_SIZE; + size_t loops; + for (loops = 0; loops < (stream->fileRealRead / SECUREC_BUFFERED_BLOK_SIZE); ++loops) { + if (fread(stream->base, (size_t)SECUREC_BUFFERED_BLOK_SIZE, (size_t)1, stream->pf) != (size_t)1) { + break; + } + } + if (residue != 0) { + long curFilePos; + if (fread(stream->base, residue, (size_t)1, stream->pf) != (size_t)1) { + return; + } + curFilePos = ftell(stream->pf); + if (curFilePos < stream->oriFilePos || + (size_t)(unsigned long)(curFilePos - stream->oriFilePos) < stream->fileRealRead) { + /* Try to remedy the problem */ + long adjustNum = (long)(stream->fileRealRead - (size_t)(unsigned long)(curFilePos - stream->oriFilePos)); + (void)fseek(stream->pf, adjustNum, SEEK_CUR); + } + } +#else + /* Seek from oriFilePos. Regardless of the integer sign problem, call scanf will not read very large data */ + if (fseek(stream->pf, (long)stream->fileRealRead, SEEK_CUR) != 0) { + /* Seek failed, ignore it */ + stream->oriFilePos = 0; + return; + } +#endif + } + return; +} + +/* + * Adjust the pointer position of the file stream and free memory + */ +SECUREC_INLINE void SecAdjustStream(SecFileStream *stream) +{ + if ((stream->flag & SECUREC_FILE_STREAM_FLAG) != 0 && stream->base != NULL) { + SecSeekStream(stream); + SECUREC_FREE(stream->base); + stream->base = NULL; + } + return; +} +#endif + +SECUREC_INLINE void SecSkipSpaceFormat(const SecUnsignedChar **format) +{ + const SecUnsignedChar *fmt = *format; + while (SecIsSpace((SecInt)(int)(*fmt)) != 0) { + ++fmt; + } + *format = fmt; +} + +#if !defined(SECUREC_FOR_WCHAR) && defined(SECUREC_COMPATIBLE_VERSION) +/* + * Handling multi-character characters + */ +SECUREC_INLINE int SecDecodeLeadByte(SecScanSpec *spec, const SecUnsignedChar **format, SecFileStream *stream) +{ +#if SECUREC_HAVE_MBTOWC + const SecUnsignedChar *fmt = *format; + int ch1 = (int)spec->ch; + int ch2 = SecGetChar(stream, &(spec->charCount)); + spec->ch = (SecInt)ch2; + if (*fmt == SECUREC_CHAR('\0') || (int)(*fmt) != ch2) { + /* in console mode, ungetc twice may cause problem */ + SecUnGetChar(ch2, stream, &(spec->charCount)); + SecUnGetChar(ch1, stream, &(spec->charCount)); + return -1; + } + ++fmt; + if ((unsigned int)MB_CUR_MAX >= SECUREC_UTF8_BOM_HEADER_SIZE && + (((unsigned char)ch1 & SECUREC_UTF8_LEAD_1ST) == SECUREC_UTF8_LEAD_1ST) && + (((unsigned char)ch2 & SECUREC_UTF8_LEAD_2ND) == SECUREC_UTF8_LEAD_2ND)) { + /* This char is very likely to be a UTF-8 char */ + wchar_t tempWChar; + char temp[SECUREC_MULTI_BYTE_MAX_LEN]; + int ch3 = (int)SecGetChar(stream, &(spec->charCount)); + spec->ch = (SecInt)ch3; + if (*fmt == SECUREC_CHAR('\0') || (int)(*fmt) != ch3) { + SecUnGetChar(ch3, stream, &(spec->charCount)); + return -1; + } + temp[0] = (char)ch1; + temp[1] = (char)ch2; /* 1 index of second character */ + temp[2] = (char)ch3; /* 2 index of third character */ + temp[3] = '\0'; /* 3 of string terminator position */ + if (mbtowc(&tempWChar, temp, sizeof(temp)) > 0) { + /* Succeed */ + ++fmt; + --spec->charCount; + } else { + SecUnGetChar(ch3, stream, &(spec->charCount)); + } + } + --spec->charCount; /* Only count as one character read */ + *format = fmt; + return 0; +#else + SecUnGetChar(spec->ch, stream, &(spec->charCount)); + (void)format; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + return -1; +#endif +} + +SECUREC_INLINE int SecFilterWcharInFormat(SecScanSpec *spec, const SecUnsignedChar **format, SecFileStream *stream) +{ + if (SecIsLeadByte(spec->ch) != 0) { + if (SecDecodeLeadByte(spec, format, stream) != 0) { + return -1; + } + } + return 0; +} +#endif + +/* + * Resolving sequence of characters from %[ format, format wile point to ']' + */ +SECUREC_INLINE int SecSetupBracketTable(const SecUnsignedChar **format, SecBracketTable *bracketTable) +{ + const SecUnsignedChar *fmt = *format; + SecUnsignedChar prevChar = 0; +#if !(defined(SECUREC_COMPATIBLE_WIN_FORMAT)) + if (*fmt == SECUREC_CHAR('{')) { + return -1; + } +#endif + /* For building "table" data */ + ++fmt; /* Skip [ */ + bracketTable->mask = 0; /* Set all bits to 0 */ + if (*fmt == SECUREC_CHAR('^')) { + ++fmt; + bracketTable->mask = (unsigned char)0xffU; /* Use 0xffU to set all bits to 1 */ + } + if (*fmt == SECUREC_CHAR(']')) { + prevChar = SECUREC_CHAR(']'); + ++fmt; + SecBracketSetBit(bracketTable->table, SECUREC_CHAR(']')); + } + while (*fmt != SECUREC_CHAR('\0') && *fmt != SECUREC_CHAR(']')) { + SecUnsignedChar expCh = *fmt; + ++fmt; + if (expCh != SECUREC_CHAR('-') || prevChar == 0 || *fmt == SECUREC_CHAR(']')) { + /* Normal character */ + prevChar = expCh; + SecBracketSetBit(bracketTable->table, expCh); + } else { + /* For %[a-z] */ + expCh = *fmt; /* Get end of range */ + ++fmt; + if (prevChar <= expCh) { /* %[a-z] %[a-a] */ + SecBracketSetBitRange(bracketTable->table, prevChar, expCh); + } else { + /* For %[z-a] */ +#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) + /* Swap start and end characters */ + SecBracketSetBitRange(bracketTable->table, expCh, prevChar); +#else + SecBracketSetBit(bracketTable->table, SECUREC_CHAR('-')); + SecBracketSetBit(bracketTable->table, expCh); +#endif + } + prevChar = 0; + } + } + *format = fmt; + return 0; +} + +#ifdef SECUREC_FOR_WCHAR +SECUREC_INLINE int SecInputForWchar(SecScanSpec *spec) +{ + void *endPtr = spec->argPtr; + if (spec->isWCharOrLong > 0) { + *(wchar_t UNALIGNED *)endPtr = (wchar_t)spec->ch; + endPtr = (wchar_t *)endPtr + 1; + --spec->arrayWidth; + } else { +#if SECUREC_HAVE_WCTOMB + int temp; + char tmpBuf[SECUREC_MB_LEN + 1]; + SECUREC_MASK_MSVC_CRT_WARNING temp = wctomb(tmpBuf, (wchar_t)spec->ch); + SECUREC_END_MASK_MSVC_CRT_WARNING + if (temp <= 0 || (size_t)(unsigned int)temp > sizeof(tmpBuf)) { + /* If wctomb error, then ignore character */ + return 0; + } + if (((size_t)(unsigned int)temp) > spec->arrayWidth) { + return -1; + } + if (memcpy_s(endPtr, spec->arrayWidth, tmpBuf, (size_t)(unsigned int)temp) != EOK) { + return -1; + } + endPtr = (char *)endPtr + temp; + spec->arrayWidth -= (size_t)(unsigned int)temp; +#else + return -1; +#endif + } + spec->argPtr = endPtr; + return 0; +} +#endif + +#ifndef SECUREC_FOR_WCHAR +#if SECUREC_HAVE_WCHART +SECUREC_INLINE wchar_t SecConvertInputCharToWchar(SecScanSpec *spec, SecFileStream *stream) +{ + wchar_t tempWChar = L'?'; /* Set default char is ? */ +#if SECUREC_HAVE_MBTOWC + char temp[SECUREC_MULTI_BYTE_MAX_LEN + 1]; + temp[0] = (char)spec->ch; + temp[1] = '\0'; +#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) + if (SecIsLeadByte(spec->ch) != 0) { + spec->ch = SecGetChar(stream, &(spec->charCount)); + temp[1] = (char)spec->ch; + temp[2] = '\0'; /* 2 of string terminator position */ + } + if (mbtowc(&tempWChar, temp, sizeof(temp)) <= 0) { + /* No string termination error for tool */ + tempWChar = L'?'; + } +#else + if (SecIsLeadByte(spec->ch) != 0) { + int convRes = 0; + int di = 1; + /* On Linux like system, the string is encoded in UTF-8 */ + while (convRes <= 0 && di < (int)MB_CUR_MAX && di < SECUREC_MULTI_BYTE_MAX_LEN) { + spec->ch = SecGetChar(stream, &(spec->charCount)); + temp[di] = (char)spec->ch; + ++di; + temp[di] = '\0'; + convRes = mbtowc(&tempWChar, temp, sizeof(temp)); + } + if (convRes <= 0) { + tempWChar = L'?'; + } + } else { + if (mbtowc(&tempWChar, temp, sizeof(temp)) <= 0) { + tempWChar = L'?'; + } + } +#endif +#else + (void)spec; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + (void)stream; /* To clear e438 last value assigned not used , the compiler will optimize this code */ +#endif /* SECUREC_HAVE_MBTOWC */ + + return tempWChar; +} +#endif /* SECUREC_HAVE_WCHART */ + +SECUREC_INLINE int SecInputForChar(SecScanSpec *spec, SecFileStream *stream) +{ + void *endPtr = spec->argPtr; + if (spec->isWCharOrLong > 0) { +#if SECUREC_HAVE_WCHART + *(wchar_t UNALIGNED *)endPtr = SecConvertInputCharToWchar(spec, stream); + endPtr = (wchar_t *)endPtr + 1; + --spec->arrayWidth; +#else + (void)stream; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + return -1; +#endif + } else { + *(char *)endPtr = (char)spec->ch; + endPtr = (char *)endPtr + 1; + --spec->arrayWidth; + } + spec->argPtr = endPtr; + return 0; +} +#endif + +/* + * Scan digital part of %d %i %o %u %x %p. + * Return 0 OK + */ +SECUREC_INLINE int SecInputNumberDigital(SecFileStream *stream, SecScanSpec *spec) +{ + static void (* const secFinishNumber[SECUREC_DECODE_NUMBER_FUNC_NUM])(SecScanSpec *spec) = { + SecFinishNumber, SecFinishNumber64 + }; + while (SECUREC_FILED_WIDTH_ENOUGH(spec)) { + spec->ch = SecGetChar(stream, &(spec->charCount)); + /* Decode ch to number */ + if (SecDecodeNumber(spec) != 0) { + SecUnGetChar(spec->ch, stream, &(spec->charCount)); + break; + } + SECUREC_FILED_WIDTH_DEC(spec); /* Must be behind un get char, otherwise the logic is incorrect */ + spec->numberState = SECUREC_NUMBER_STATE_STARTED; + } + /* Handling integer negative numbers and beyond max */ + (*secFinishNumber[spec->numberArgType])(spec); + if (spec->numberState == SECUREC_NUMBER_STATE_STARTED) { + return 0; + } + return -1; +} + +/* + * Scan %d %i %o %u %x %p. + * Return 0 OK + */ +SECUREC_INLINE int SecInputNumber(SecFileStream *stream, SecScanSpec *spec) +{ + /* Character already read */ + if (spec->ch == SECUREC_CHAR('+') || spec->ch == SECUREC_CHAR('-')) { + if (spec->ch == SECUREC_CHAR('-')) { + spec->negative = 1; +#if SECUREC_IN_KERNEL + /* In kernel Refuse to enter negative number */ + if (SECUREC_CONVERT_IS_UNSIGNED(spec->oriConvChr)) { + return -1; + } +#endif + } + SECUREC_FILED_WIDTH_DEC(spec); /* Do not need to check width here, must be greater than 0 */ + spec->ch = SecGetChar(stream, &(spec->charCount)); /* Eat + or - */ + spec->ch = SecGetChar(stream, &(spec->charCount)); /* Get next character, used for the '0' judgments */ + SecUnGetChar(spec->ch, stream, &(spec->charCount)); /* Not sure if it was actually read, so push back */ + } + + if (spec->oriConvChr == 'i') { + spec->convChr = 'd'; /* The i could be d, o, or x, use d as default */ + } + + if (spec->ch == SECUREC_CHAR('0') && (spec->oriConvChr == 'x' || spec->oriConvChr == 'i') && + SECUREC_FILED_WIDTH_ENOUGH(spec)) { + /* Input string begin with 0, may be 0x123 0X123 0123 0x 01 0yy 09 0 0ab 00 */ + SECUREC_FILED_WIDTH_DEC(spec); + spec->ch = SecGetChar(stream, &(spec->charCount)); /* ch is '0' */ + + /* Read only '0' due to width limitation */ + if (!SECUREC_FILED_WIDTH_ENOUGH(spec)) { + /* The number or number64 in spec has been set 0 */ + return 0; + } + + spec->ch = SecGetChar(stream, &(spec->charCount)); /* Get next char to check x or X, do not dec width */ + if ((SecChar)spec->ch == SECUREC_CHAR('x') || (SecChar)spec->ch == SECUREC_CHAR('X')) { + spec->convChr = 'x'; + SECUREC_FILED_WIDTH_DEC(spec); /* Make incorrect width for x or X */ + } else { + if (spec->oriConvChr == 'i') { + spec->convChr = 'o'; + } + /* For "0y" "08" "01" "0a" ... ,push the 'y' '8' '1' 'a' back */ + SecUnGetChar(spec->ch, stream, &(spec->charCount)); + /* Since 0 has been read, it indicates that a valid character has been read */ + spec->numberState = SECUREC_NUMBER_STATE_STARTED; + } + } + return SecInputNumberDigital(stream, spec); +} + +/* + * Scan %c %s %[ + * Return 0 OK + */ +SECUREC_INLINE int SecInputString(SecFileStream *stream, SecScanSpec *spec, + const SecBracketTable *bracketTable, int *doneCount) +{ + void *startPtr = spec->argPtr; + int suppressed = 0; + int errNoMem = 0; + + while (SECUREC_FILED_WIDTH_ENOUGH(spec)) { + SECUREC_FILED_WIDTH_DEC(spec); + spec->ch = SecGetChar(stream, &(spec->charCount)); + /* + * The char condition or string condition and bracket condition. + * Only supports wide characters with a maximum length of two bytes + */ + if (spec->ch != SECUREC_EOF && (SecCanInputCharacter(spec->convChr) != 0 || + SecCanInputString(spec->convChr, spec->ch) != 0 || + SecCanInputForBracket(spec->convChr, spec->ch, bracketTable) != 0)) { + if (spec->suppress != 0) { + /* Used to identify processed data for %*, use argPtr to identify will cause 613, so use suppressed */ + suppressed = 1; + continue; + } + /* Now suppress is not set */ + if (spec->arrayWidth == 0) { + errNoMem = 1; /* We have exhausted the user's buffer */ + break; + } +#ifdef SECUREC_FOR_WCHAR + errNoMem = SecInputForWchar(spec); +#else + errNoMem = SecInputForChar(spec, stream); +#endif + if (errNoMem != 0) { + break; + } + } else { + SecUnGetChar(spec->ch, stream, &(spec->charCount)); + break; + } + } + + if (errNoMem != 0) { + /* In case of error, blank out the input buffer */ + SecAddEndingZero(startPtr, spec); + return -1; + } + if ((spec->suppress != 0 && suppressed == 0) || + (spec->suppress == 0 && startPtr == spec->argPtr)) { + /* No input was scanned */ + return -1; + } + if (spec->convChr != 'c') { + /* Add null-terminate for strings */ + SecAddEndingZero(spec->argPtr, spec); + } + if (spec->suppress == 0) { + *doneCount = *doneCount + 1; + } + return 0; +} + +#ifdef SECUREC_FOR_WCHAR +/* + * Allocate buffer for wchar version of %[. + * Return 0 OK + */ +SECUREC_INLINE int SecAllocBracketTable(SecBracketTable *bracketTable) +{ + if (bracketTable->table == NULL) { + /* Table should be freed after use */ + bracketTable->table = (unsigned char *)SECUREC_MALLOC(SECUREC_BRACKET_TABLE_SIZE); + if (bracketTable->table == NULL) { + return -1; + } + } + return 0; +} + +/* + * Free buffer for wchar version of %[ + */ +SECUREC_INLINE void SecFreeBracketTable(SecBracketTable *bracketTable) +{ + if (bracketTable->table != NULL) { + SECUREC_FREE(bracketTable->table); + bracketTable->table = NULL; + } +} +#endif + +#ifdef SECUREC_FOR_WCHAR +/* + * Formatting input core functions for wchar version.Called by a function such as vswscanf_s + */ +int SecInputSW(SecFileStream *stream, const wchar_t *cFormat, va_list argList) +#else +/* + * Formatting input core functions for char version.Called by a function such as vsscanf_s + */ +int SecInputS(SecFileStream *stream, const char *cFormat, va_list argList) +#endif +{ + const SecUnsignedChar *format = (const SecUnsignedChar *)cFormat; + SecBracketTable bracketTable = SECUREC_INIT_BRACKET_TABLE; + SecScanSpec spec; + int doneCount = 0; + int formatError = 0; + int paraIsNull = 0; + int match = 0; /* When % is found , inc this value */ + int errRet = 0; +#if SECUREC_ENABLE_SCANF_FLOAT + SecFloatSpec floatSpec; + SecInitFloatSpec(&floatSpec); +#endif + spec.ch = 0; /* Need to initialize to 0 */ + spec.charCount = 0; /* Need to initialize to 0 */ + + /* Format must not NULL, use err < 1 to clear 845 */ + while (errRet < 1 && *format != SECUREC_CHAR('\0')) { + /* Skip space in format and space in input */ + if (SecIsSpace((SecInt)(int)(*format)) != 0) { + /* Read first no space char */ + spec.ch = SecSkipSpaceChar(stream, &(spec.charCount)); + /* Read the EOF cannot be returned directly here, because the case of " %n" needs to be handled */ + /* Put fist no space char backup. put EOF back is also OK, and to modify the character count */ + SecUnGetChar(spec.ch, stream, &(spec.charCount)); + SecSkipSpaceFormat(&format); + continue; + } + + if (*format != SECUREC_CHAR('%')) { + spec.ch = SecGetChar(stream, &(spec.charCount)); + if ((int)(*format) != (int)(spec.ch)) { + SecUnGetChar(spec.ch, stream, &(spec.charCount)); + break; + } + ++format; +#if !defined(SECUREC_FOR_WCHAR) && defined(SECUREC_COMPATIBLE_VERSION) + if (SecFilterWcharInFormat(&spec, &format, stream) != 0) { + break; + } +#endif + continue; + } + + /* Now *format is % */ + /* Set default value for each % */ + SecSetDefaultScanSpec(&spec); + if (SecDecodeScanFlag(&format, &spec) != 0) { + formatError = 1; + ++errRet; + continue; + } + if (!SECUREC_FILED_WIDTH_ENOUGH(&spec)) { + /* 0 width in format */ + ++errRet; + continue; + } + + /* Update wchar flag for %S %C */ + SecUpdateWcharFlagByType(*format, &spec); + + spec.convChr = SECUREC_TO_LOWERCASE(*format); + spec.oriConvChr = spec.convChr; /* convChr may be modified to handle integer logic */ + if (spec.convChr != 'n') { + if (spec.convChr != 'c' && spec.convChr != SECUREC_BRACE) { + spec.ch = SecSkipSpaceChar(stream, &(spec.charCount)); + } else { + spec.ch = SecGetChar(stream, &(spec.charCount)); + } + if (spec.ch == SECUREC_EOF) { + ++errRet; + continue; + } + } + + /* Now no 0 width in format and get one char from input */ + switch (spec.oriConvChr) { + case 'c': /* Also 'C' */ + if (spec.widthSet == 0) { + spec.widthSet = 1; + spec.width = 1; + } + /* fall-through */ /* FALLTHRU */ + case 's': /* Also 'S': */ + /* fall-through */ /* FALLTHRU */ + case SECUREC_BRACE: + /* Unset last char to stream */ + SecUnGetChar(spec.ch, stream, &(spec.charCount)); + /* Check dest buffer and size */ + if (spec.suppress == 0) { + spec.argPtr = (void *)va_arg(argList, void *); + if (spec.argPtr == NULL) { + paraIsNull = 1; + ++errRet; + continue; + } + /* Get the next argument, size of the array in characters */ + spec.arrayWidth = SECUREC_GET_ARRAYWIDTH(argList); + if (SECUREC_ARRAY_WIDTH_IS_WRONG(spec)) { + /* Do not clear buffer just go error */ + ++errRet; + continue; + } + /* One element is needed for '\0' for %s and %[ */ + if (spec.convChr != 'c') { + --spec.arrayWidth; + } + } else { + /* Set argPtr to NULL is necessary, in suppress mode we don't use argPtr to store data */ + spec.argPtr = NULL; + } + + if (spec.convChr == SECUREC_BRACE) { + /* Malloc when first %[ is meet for wchar version */ +#ifdef SECUREC_FOR_WCHAR + if (SecAllocBracketTable(&bracketTable) != 0) { + ++errRet; + continue; + } +#endif + (void)SECUREC_MEMSET_FUNC_OPT(bracketTable.table, 0, (size_t)SECUREC_BRACKET_TABLE_SIZE); + if (SecSetupBracketTable(&format, &bracketTable) != 0) { + ++errRet; + continue; + } + + if (*format == SECUREC_CHAR('\0')) { + /* Default add string terminator */ + SecAddEndingZero(spec.argPtr, &spec); + ++errRet; + /* Truncated format */ + continue; + } + } + + /* Set completed. Now read string or character */ + if (SecInputString(stream, &spec, &bracketTable, &doneCount) != 0) { + ++errRet; + continue; + } + break; + case 'p': + /* Make %hp same as %p */ + spec.numberWidth = SECUREC_NUM_WIDTH_INT; +#ifdef SECUREC_ON_64BITS + spec.numberArgType = 1; +#endif + /* fall-through */ /* FALLTHRU */ + case 'o': /* fall-through */ /* FALLTHRU */ + case 'u': /* fall-through */ /* FALLTHRU */ + case 'd': /* fall-through */ /* FALLTHRU */ + case 'i': /* fall-through */ /* FALLTHRU */ + case 'x': + /* Unset last char to stream */ + SecUnGetChar(spec.ch, stream, &(spec.charCount)); + if (SecInputNumber(stream, &spec) != 0) { + ++errRet; + continue; + } + if (spec.suppress == 0) { + spec.argPtr = (void *)va_arg(argList, void *); + if (spec.argPtr == NULL) { + paraIsNull = 1; + ++errRet; + continue; + } + SecAssignNumber(&spec); + ++doneCount; + } + break; + case 'n': /* Char count */ + if (spec.suppress == 0) { + spec.argPtr = (void *)va_arg(argList, void *); + if (spec.argPtr == NULL) { + paraIsNull = 1; + ++errRet; + continue; + } + spec.number = (unsigned long)(unsigned int)(spec.charCount); + spec.numberArgType = 0; + SecAssignNumber(&spec); + } + break; + case 'e': /* fall-through */ /* FALLTHRU */ + case 'f': /* fall-through */ /* FALLTHRU */ + case 'g': /* Scan a float */ + /* Unset last char to stream */ + SecUnGetChar(spec.ch, stream, &(spec.charCount)); +#if SECUREC_ENABLE_SCANF_FLOAT + if (SecInputFloat(stream, &spec, &floatSpec) != 0) { + ++errRet; + continue; + } + if (spec.suppress == 0) { + spec.argPtr = (void *)va_arg(argList, void *); + if (spec.argPtr == NULL) { + ++errRet; + paraIsNull = 1; + continue; + } + if (SecAssignFloat(&floatSpec, &spec) != 0) { + ++errRet; + continue; + } + ++doneCount; + } + break; +#else /* SECUREC_ENABLE_SCANF_FLOAT */ + ++errRet; + continue; +#endif + default: + if ((int)(*format) != (int)spec.ch) { + SecUnGetChar(spec.ch, stream, &(spec.charCount)); + formatError = 1; + ++errRet; + continue; + } else { + --match; /* Compensate for the self-increment of the following code */ + } + break; + } + ++match; + ++format; + } + +#ifdef SECUREC_FOR_WCHAR + SecFreeBracketTable(&bracketTable); +#endif + +#if SECUREC_ENABLE_SCANF_FLOAT + SecFreeFloatSpec(&floatSpec, &doneCount); +#endif + +#if SECUREC_ENABLE_SCANF_FILE + SecAdjustStream(stream); +#endif + + if (spec.ch == SECUREC_EOF) { + return ((doneCount != 0 || match != 0) ? doneCount : SECUREC_SCANF_EINVAL); + } + if (formatError != 0 || paraIsNull != 0) { + /* Invalid Input Format or parameter, but not meet EOF */ + return SECUREC_SCANF_ERROR_PARA; + } + return doneCount; +} + +#if SECUREC_ENABLE_SCANF_FILE +/* + * Get char from stream use std function + */ +SECUREC_INLINE SecInt SecGetCharFromStream(const SecFileStream *stream) +{ + SecInt ch; + ch = SECUREC_GETC(stream->pf); + return ch; +} + +/* + * Try to read the BOM header, when meet a BOM head, discard it, then data is Aligned to base + */ +SECUREC_INLINE void SecReadAndSkipBomHeader(SecFileStream *stream) +{ + /* Use size_t type conversion to clean e747 */ + stream->count = fread(stream->base, (size_t)1, (size_t)SECUREC_BOM_HEADER_SIZE, stream->pf); + if (stream->count > SECUREC_BOM_HEADER_SIZE) { + stream->count = 0; + } + if (SECUREC_BEGIN_WITH_BOM(stream->base, stream->count)) { + /* It's BOM header, discard it */ + stream->count = 0; + } +} + +/* + * Get char from file stream or buffer + */ +SECUREC_INLINE SecInt SecGetCharFromFile(SecFileStream *stream) +{ + SecInt ch; + if (stream->count < sizeof(SecChar)) { + /* Load file to buffer */ + size_t len; + if (stream->base != NULL) { + /* Put the last unread data in the buffer head */ + for (len = 0; len < stream->count; ++len) { + stream->base[len] = stream->cur[len]; + } + } else { + stream->oriFilePos = ftell(stream->pf); /* Save original file read position */ + if (stream->oriFilePos == -1) { + /* It may be a pipe stream */ + stream->flag = SECUREC_PIPE_STREAM_FLAG; + return SecGetCharFromStream(stream); + } + /* Reserve the length of BOM head */ + stream->base = (char *)SECUREC_MALLOC(SECUREC_BUFFERED_BLOK_SIZE + + SECUREC_BOM_HEADER_SIZE + sizeof(SecChar)); /* To store '\0' and aligned to wide char */ + if (stream->base == NULL) { + return SECUREC_EOF; + } + /* First read file */ + if (stream->oriFilePos == 0) { + /* Make sure the data is aligned to base */ + SecReadAndSkipBomHeader(stream); + } + } + + /* Skip existing data and read data */ + len = fread(stream->base + stream->count, (size_t)1, (size_t)SECUREC_BUFFERED_BLOK_SIZE, stream->pf); + if (len > SECUREC_BUFFERED_BLOK_SIZE) { /* It won't happen, */ + len = 0; + } + stream->count += len; + stream->cur = stream->base; + stream->flag |= SECUREC_LOAD_FILE_TO_MEM_FLAG; + stream->base[stream->count] = '\0'; /* For tool Warning string null */ + } + + SECUREC_GET_CHAR(stream, &ch); + if (ch != SECUREC_EOF) { + stream->fileRealRead += sizeof(SecChar); + } + return ch; +} +#endif + +/* + * Get char for wchar version + */ +SECUREC_INLINE SecInt SecGetChar(SecFileStream *stream, int *counter) +{ + *counter = *counter + 1; /* Always plus 1 */ + /* The main scenario is scanf str */ + if ((stream->flag & SECUREC_MEM_STR_FLAG) != 0) { + SecInt ch; + SECUREC_GET_CHAR(stream, &ch); + return ch; + } +#if SECUREC_ENABLE_SCANF_FILE + if ((stream->flag & SECUREC_FILE_STREAM_FLAG) != 0) { + return SecGetCharFromFile(stream); + } + if ((stream->flag & SECUREC_PIPE_STREAM_FLAG) != 0) { + return SecGetCharFromStream(stream); + } +#endif + return SECUREC_EOF; +} + +/* + * Unget Public realization char for wchar and char version + */ +SECUREC_INLINE void SecUnGetCharImpl(SecInt ch, SecFileStream *stream) +{ + if ((stream->flag & SECUREC_MEM_STR_FLAG) != 0) { + SECUREC_UN_GET_CHAR(stream); + return; + } +#if SECUREC_ENABLE_SCANF_FILE + if ((stream->flag & SECUREC_LOAD_FILE_TO_MEM_FLAG) != 0) { + SECUREC_UN_GET_CHAR(stream); + if (stream->fileRealRead > 0) { + stream->fileRealRead -= sizeof(SecChar); + } + return; + } + if ((stream->flag & SECUREC_PIPE_STREAM_FLAG) != 0) { + (void)SECUREC_UN_GETC(ch, stream->pf); + return; + } +#else + (void)ch; /* To clear e438 last value assigned not used , the compiler will optimize this code */ +#endif +} + +/* + * Unget char for char version + */ +SECUREC_INLINE void SecUnGetChar(SecInt ch, SecFileStream *stream, int *counter) +{ + *counter = *counter - 1; /* Always minus 1 */ + if (ch != SECUREC_EOF) { + SecUnGetCharImpl(ch, stream); + } +} + +/* + * Skip space char by isspace + */ +SECUREC_INLINE SecInt SecSkipSpaceChar(SecFileStream *stream, int *counter) +{ + SecInt ch; + do { + ch = SecGetChar(stream, counter); + if (ch == SECUREC_EOF) { + break; + } + } while (SecIsSpace(ch) != 0); + return ch; +} +#endif /* INPUT_INL_5D13A042_DC3F_4ED9_A8D1_882811274C27 */ + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/memcpy_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/memcpy_s.c new file mode 100644 index 00000000..a7fd4874 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/memcpy_s.c @@ -0,0 +1,555 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: memcpy_s function + * Create: 2014-02-25 + */ +/* + * [Standardize-exceptions] Use unsafe function: Portability + * [reason] Use unsafe function to implement security function to maintain platform compatibility. + * And sufficient input validation is performed before calling + */ + +#include "securecutil.h" + +#if SECUREC_WITH_PERFORMANCE_ADDONS +#ifndef SECUREC_MEMCOPY_THRESHOLD_SIZE +#define SECUREC_MEMCOPY_THRESHOLD_SIZE 64UL +#endif + +#define SECUREC_SMALL_MEM_COPY(dest, src, count) do { \ + if (SECUREC_ADDR_ALIGNED_8(dest) && SECUREC_ADDR_ALIGNED_8(src)) { \ + /* Use struct assignment */ \ + switch (count) { \ + case 1: \ + *(unsigned char *)(dest) = *(const unsigned char *)(src); \ + break; \ + case 2: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 2); \ + break; \ + case 3: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 3); \ + break; \ + case 4: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 4); \ + break; \ + case 5: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 5); \ + break; \ + case 6: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 6); \ + break; \ + case 7: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 7); \ + break; \ + case 8: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 8); \ + break; \ + case 9: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 9); \ + break; \ + case 10: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 10); \ + break; \ + case 11: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 11); \ + break; \ + case 12: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 12); \ + break; \ + case 13: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 13); \ + break; \ + case 14: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 14); \ + break; \ + case 15: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 15); \ + break; \ + case 16: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 16); \ + break; \ + case 17: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 17); \ + break; \ + case 18: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 18); \ + break; \ + case 19: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 19); \ + break; \ + case 20: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 20); \ + break; \ + case 21: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 21); \ + break; \ + case 22: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 22); \ + break; \ + case 23: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 23); \ + break; \ + case 24: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 24); \ + break; \ + case 25: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 25); \ + break; \ + case 26: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 26); \ + break; \ + case 27: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 27); \ + break; \ + case 28: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 28); \ + break; \ + case 29: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 29); \ + break; \ + case 30: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 30); \ + break; \ + case 31: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 31); \ + break; \ + case 32: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 32); \ + break; \ + case 33: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 33); \ + break; \ + case 34: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 34); \ + break; \ + case 35: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 35); \ + break; \ + case 36: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 36); \ + break; \ + case 37: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 37); \ + break; \ + case 38: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 38); \ + break; \ + case 39: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 39); \ + break; \ + case 40: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 40); \ + break; \ + case 41: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 41); \ + break; \ + case 42: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 42); \ + break; \ + case 43: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 43); \ + break; \ + case 44: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 44); \ + break; \ + case 45: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 45); \ + break; \ + case 46: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 46); \ + break; \ + case 47: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 47); \ + break; \ + case 48: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 48); \ + break; \ + case 49: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 49); \ + break; \ + case 50: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 50); \ + break; \ + case 51: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 51); \ + break; \ + case 52: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 52); \ + break; \ + case 53: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 53); \ + break; \ + case 54: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 54); \ + break; \ + case 55: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 55); \ + break; \ + case 56: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 56); \ + break; \ + case 57: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 57); \ + break; \ + case 58: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 58); \ + break; \ + case 59: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 59); \ + break; \ + case 60: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 60); \ + break; \ + case 61: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 61); \ + break; \ + case 62: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 62); \ + break; \ + case 63: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 63); \ + break; \ + case 64: \ + SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 64); \ + break; \ + default: \ + /* Do nothing */ \ + break; \ + } /* END switch */ \ + } else { \ + unsigned char *tmpDest_ = (unsigned char *)(dest); \ + const unsigned char *tmpSrc_ = (const unsigned char *)(src); \ + switch (count) { \ + case 64: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 63: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 62: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 61: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 60: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 59: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 58: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 57: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 56: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 55: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 54: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 53: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 52: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 51: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 50: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 49: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 48: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 47: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 46: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 45: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 44: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 43: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 42: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 41: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 40: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 39: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 38: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 37: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 36: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 35: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 34: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 33: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 32: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 31: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 30: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 29: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 28: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 27: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 26: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 25: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 24: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 23: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 22: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 21: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 20: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 19: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 18: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 17: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 16: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 15: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 14: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 13: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 12: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 11: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 10: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 9: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 8: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 7: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 6: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 5: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 4: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 3: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 2: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 1: \ + *(tmpDest_++) = *(tmpSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + default: \ + /* Do nothing */ \ + break; \ + } \ + } \ +} SECUREC_WHILE_ZERO + +/* + * Performance optimization + */ +#define SECUREC_MEMCPY_OPT(dest, src, count) do { \ + if ((count) > SECUREC_MEMCOPY_THRESHOLD_SIZE) { \ + SECUREC_MEMCPY_WARP_OPT((dest), (src), (count)); \ + } else { \ + SECUREC_SMALL_MEM_COPY((dest), (src), (count)); \ + } \ +} SECUREC_WHILE_ZERO +#endif + +/* + * Handling errors + */ +SECUREC_INLINE errno_t SecMemcpyError(void *dest, size_t destMax, const void *src, size_t count) +{ + if (destMax == 0 || destMax > SECUREC_MEM_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("memcpy_s"); + return ERANGE; + } + if (dest == NULL || src == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("memcpy_s"); + if (dest != NULL) { + (void)SECUREC_MEMSET_FUNC_OPT(dest, 0, destMax); + return EINVAL_AND_RESET; + } + return EINVAL; + } + if (count > destMax) { + (void)SECUREC_MEMSET_FUNC_OPT(dest, 0, destMax); + SECUREC_ERROR_INVALID_RANGE("memcpy_s"); + return ERANGE_AND_RESET; + } + if (SECUREC_MEMORY_IS_OVERLAP(dest, src, count)) { + (void)SECUREC_MEMSET_FUNC_OPT(dest, 0, destMax); + SECUREC_ERROR_BUFFER_OVERLAP("memcpy_s"); + return EOVERLAP_AND_RESET; + } + /* Count is 0 or dest equal src also ret EOK */ + return EOK; +} + +#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) + /* + * The fread API in windows will call memcpy_s and pass 0xffffffff to destMax. + * To avoid the failure of fread, we don't check desMax limit. + */ +#define SECUREC_MEMCPY_PARAM_OK(dest, destMax, src, count) (SECUREC_LIKELY((count) <= (destMax) && \ + (dest) != NULL && (src) != NULL && \ + (count) > 0 && SECUREC_MEMORY_NO_OVERLAP((dest), (src), (count)))) +#else +#define SECUREC_MEMCPY_PARAM_OK(dest, destMax, src, count) (SECUREC_LIKELY((count) <= (destMax) && \ + (dest) != NULL && (src) != NULL && (destMax) <= SECUREC_MEM_MAX_LEN && \ + (count) > 0 && SECUREC_MEMORY_NO_OVERLAP((dest), (src), (count)))) +#endif + +/* + * + * The memcpy_s function copies n characters from the object pointed to by src into the object pointed to by dest + * + * + * dest Destination buffer. + * destMax Size of the destination buffer. + * src Buffer to copy from. + * count Number of characters to copy + * + * + * dest buffer is updated. + * + * + * EOK Success + * EINVAL dest is NULL and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN + * EINVAL_AND_RESET dest != NULL and src is NULL and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN + * ERANGE destMax > SECUREC_MEM_MAX_LEN or destMax is 0 + * ERANGE_AND_RESET count > destMax and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN + * and dest != NULL and src != NULL + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and + * count <= destMax destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN and dest != NULL + * and src != NULL and dest != src + * + * if an error occurred, dest will be filled with 0. + * If the source and destination overlap, the behavior of memcpy_s is undefined. + * Use memmove_s to handle overlapping regions. + */ +errno_t memcpy_s(void *dest, size_t destMax, const void *src, size_t count) +{ + if (SECUREC_MEMCPY_PARAM_OK(dest, destMax, src, count)) { + SECUREC_MEMCPY_WARP_OPT(dest, src, count); + return EOK; + } + /* Meet some runtime violation, return error code */ + return SecMemcpyError(dest, destMax, src, count); +} + +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(memcpy_s); +#endif + +#if SECUREC_WITH_PERFORMANCE_ADDONS +/* + * Performance optimization + */ +errno_t memcpy_sOptAsm(void *dest, size_t destMax, const void *src, size_t count) +{ + if (SECUREC_MEMCPY_PARAM_OK(dest, destMax, src, count)) { + SECUREC_MEMCPY_OPT(dest, src, count); + return EOK; + } + /* Meet some runtime violation, return error code */ + return SecMemcpyError(dest, destMax, src, count); +} + +/* Trim judgement on "destMax <= SECUREC_MEM_MAX_LEN" */ +errno_t memcpy_sOptTc(void *dest, size_t destMax, const void *src, size_t count) +{ + if (SECUREC_LIKELY(count <= destMax && dest != NULL && src != NULL && \ + count > 0 && SECUREC_MEMORY_NO_OVERLAP((dest), (src), (count)))) { + SECUREC_MEMCPY_OPT(dest, src, count); + return EOK; + } + /* Meet some runtime violation, return error code */ + return SecMemcpyError(dest, destMax, src, count); +} +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/memmove_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/memmove_s.c new file mode 100644 index 00000000..f231f05d --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/memmove_s.c @@ -0,0 +1,123 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: memmove_s function + * Create: 2014-02-25 + */ +/* + * [Standardize-exceptions] Use unsafe function: Portability + * [reason] Use unsafe function to implement security function to maintain platform compatibility. + * And sufficient input validation is performed before calling + */ + +#include "securecutil.h" + +#ifdef SECUREC_NOT_CALL_LIBC_CORE_API +/* + * Implementing memory data movement + */ +SECUREC_INLINE void SecUtilMemmove(void *dst, const void *src, size_t count) +{ + unsigned char *pDest = (unsigned char *)dst; + const unsigned char *pSrc = (const unsigned char *)src; + size_t maxCount = count; + + if (dst <= src || pDest >= (pSrc + maxCount)) { + /* + * Non-Overlapping Buffers + * Copy from lower addresses to higher addresses + */ + while (maxCount > 0) { + --maxCount; + *pDest = *pSrc; + ++pDest; + ++pSrc; + } + } else { + /* + * Overlapping Buffers + * Copy from higher addresses to lower addresses + */ + pDest = pDest + maxCount - 1; + pSrc = pSrc + maxCount - 1; + while (maxCount > 0) { + --maxCount; + *pDest = *pSrc; + --pDest; + --pSrc; + } + } +} +#endif + +/* + * + * The memmove_s function copies count bytes of characters from src to dest. + * This function can be assigned correctly when memory overlaps. + * + * dest Destination object. + * destMax Size of the destination buffer. + * src Source object. + * count Number of characters to copy. + * + * + * dest buffer is updated. + * + * + * EOK Success + * EINVAL dest is NULL and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN + * EINVAL_AND_RESET dest != NULL and src is NULL and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN + * ERANGE destMax > SECUREC_MEM_MAX_LEN or destMax is 0 + * ERANGE_AND_RESET count > destMax and dest != NULL and src != NULL and destMax != 0 + * and destMax <= SECUREC_MEM_MAX_LEN + * + * If an error occurred, dest will be filled with 0 when dest and destMax valid. + * If some regions of the source area and the destination overlap, memmove_s + * ensures that the original source bytes in the overlapping region are copied + * before being overwritten. + */ +errno_t memmove_s(void *dest, size_t destMax, const void *src, size_t count) +{ + if (destMax == 0 || destMax > SECUREC_MEM_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("memmove_s"); + return ERANGE; + } + if (dest == NULL || src == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("memmove_s"); + if (dest != NULL) { + (void)SECUREC_MEMSET_FUNC_OPT(dest, 0, destMax); + return EINVAL_AND_RESET; + } + return EINVAL; + } + if (count > destMax) { + (void)SECUREC_MEMSET_FUNC_OPT(dest, 0, destMax); + SECUREC_ERROR_INVALID_RANGE("memmove_s"); + return ERANGE_AND_RESET; + } + if (dest == src) { + return EOK; + } + + if (count > 0) { +#ifdef SECUREC_NOT_CALL_LIBC_CORE_API + SecUtilMemmove(dest, src, count); +#else + /* Use underlying memmove for performance consideration */ + (void)memmove(dest, src, count); +#endif + } + return EOK; +} + +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(memmove_s); +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/memset_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/memset_s.c new file mode 100644 index 00000000..d9a657fd --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/memset_s.c @@ -0,0 +1,510 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: memset_s function + * Create: 2014-02-25 + */ +/* + * [Standardize-exceptions] Use unsafe function: Portability + * [reason] Use unsafe function to implement security function to maintain platform compatibility. + * And sufficient input validation is performed before calling + */ + +#include "securecutil.h" + +#define SECUREC_MEMSET_PARAM_OK(dest, destMax, count) (SECUREC_LIKELY((destMax) <= SECUREC_MEM_MAX_LEN && \ + (dest) != NULL && (count) <= (destMax))) + +#if SECUREC_WITH_PERFORMANCE_ADDONS + +/* Use union to clear strict-aliasing warning */ +typedef union { + SecStrBuf32 buf32; + SecStrBuf31 buf31; + SecStrBuf30 buf30; + SecStrBuf29 buf29; + SecStrBuf28 buf28; + SecStrBuf27 buf27; + SecStrBuf26 buf26; + SecStrBuf25 buf25; + SecStrBuf24 buf24; + SecStrBuf23 buf23; + SecStrBuf22 buf22; + SecStrBuf21 buf21; + SecStrBuf20 buf20; + SecStrBuf19 buf19; + SecStrBuf18 buf18; + SecStrBuf17 buf17; + SecStrBuf16 buf16; + SecStrBuf15 buf15; + SecStrBuf14 buf14; + SecStrBuf13 buf13; + SecStrBuf12 buf12; + SecStrBuf11 buf11; + SecStrBuf10 buf10; + SecStrBuf9 buf9; + SecStrBuf8 buf8; + SecStrBuf7 buf7; + SecStrBuf6 buf6; + SecStrBuf5 buf5; + SecStrBuf4 buf4; + SecStrBuf3 buf3; + SecStrBuf2 buf2; +} SecStrBuf32Union; +/* C standard initializes the first member of the consortium. */ +static const SecStrBuf32 g_allZero = {{ + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U +}}; +static const SecStrBuf32 g_allFF = {{ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF +}}; + +/* Clear conversion warning strict aliasing" */ +SECUREC_INLINE const SecStrBuf32Union *SecStrictAliasingCast(const SecStrBuf32 *buf) +{ + return (const SecStrBuf32Union *)buf; +} + +#ifndef SECUREC_MEMSET_THRESHOLD_SIZE +#define SECUREC_MEMSET_THRESHOLD_SIZE 32UL +#endif + +#define SECUREC_UNALIGNED_SET(dest, c, count) do { \ + unsigned char *pDest_ = (unsigned char *)(dest); \ + switch (count) { \ + case 32: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 31: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 30: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 29: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 28: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 27: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 26: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 25: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 24: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 23: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 22: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 21: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 20: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 19: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 18: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 17: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 16: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 15: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 14: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 13: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 12: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 11: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 10: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 9: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 8: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 7: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 6: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 5: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 4: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 3: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 2: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + case 1: \ + *(pDest_++) = (unsigned char)(c); \ + /* fall-through */ /* FALLTHRU */ \ + default: \ + /* Do nothing */ \ + break; \ + } \ +} SECUREC_WHILE_ZERO + +#define SECUREC_SET_VALUE_BY_STRUCT(dest, dataName, n) do { \ + *(SecStrBuf##n *)(dest) = *(const SecStrBuf##n *)(&((SecStrictAliasingCast(&(dataName)))->buf##n)); \ +} SECUREC_WHILE_ZERO + +#define SECUREC_ALIGNED_SET_OPT_ZERO_FF(dest, c, count) do { \ + switch (c) { \ + case 0: \ + switch (count) { \ + case 1: \ + *(unsigned char *)(dest) = (unsigned char)0; \ + break; \ + case 2: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 2); \ + break; \ + case 3: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 3); \ + break; \ + case 4: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 4); \ + break; \ + case 5: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 5); \ + break; \ + case 6: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 6); \ + break; \ + case 7: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 7); \ + break; \ + case 8: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 8); \ + break; \ + case 9: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 9); \ + break; \ + case 10: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 10); \ + break; \ + case 11: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 11); \ + break; \ + case 12: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 12); \ + break; \ + case 13: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 13); \ + break; \ + case 14: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 14); \ + break; \ + case 15: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 15); \ + break; \ + case 16: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 16); \ + break; \ + case 17: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 17); \ + break; \ + case 18: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 18); \ + break; \ + case 19: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 19); \ + break; \ + case 20: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 20); \ + break; \ + case 21: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 21); \ + break; \ + case 22: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 22); \ + break; \ + case 23: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 23); \ + break; \ + case 24: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 24); \ + break; \ + case 25: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 25); \ + break; \ + case 26: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 26); \ + break; \ + case 27: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 27); \ + break; \ + case 28: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 28); \ + break; \ + case 29: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 29); \ + break; \ + case 30: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 30); \ + break; \ + case 31: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 31); \ + break; \ + case 32: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 32); \ + break; \ + default: \ + /* Do nothing */ \ + break; \ + } \ + break; \ + case 0xFF: \ + switch (count) { \ + case 1: \ + *(unsigned char *)(dest) = (unsigned char)0xffU; \ + break; \ + case 2: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 2); \ + break; \ + case 3: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 3); \ + break; \ + case 4: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 4); \ + break; \ + case 5: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 5); \ + break; \ + case 6: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 6); \ + break; \ + case 7: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 7); \ + break; \ + case 8: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 8); \ + break; \ + case 9: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 9); \ + break; \ + case 10: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 10); \ + break; \ + case 11: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 11); \ + break; \ + case 12: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 12); \ + break; \ + case 13: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 13); \ + break; \ + case 14: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 14); \ + break; \ + case 15: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 15); \ + break; \ + case 16: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 16); \ + break; \ + case 17: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 17); \ + break; \ + case 18: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 18); \ + break; \ + case 19: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 19); \ + break; \ + case 20: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 20); \ + break; \ + case 21: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 21); \ + break; \ + case 22: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 22); \ + break; \ + case 23: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 23); \ + break; \ + case 24: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 24); \ + break; \ + case 25: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 25); \ + break; \ + case 26: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 26); \ + break; \ + case 27: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 27); \ + break; \ + case 28: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 28); \ + break; \ + case 29: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 29); \ + break; \ + case 30: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 30); \ + break; \ + case 31: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 31); \ + break; \ + case 32: \ + SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 32); \ + break; \ + default: \ + /* Do nothing */ \ + break; \ + } \ + break; \ + default: \ + SECUREC_UNALIGNED_SET((dest), (c), (count)); \ + break; \ + } /* END switch */ \ +} SECUREC_WHILE_ZERO + +#define SECUREC_SMALL_MEM_SET(dest, c, count) do { \ + if (SECUREC_ADDR_ALIGNED_8((dest))) { \ + SECUREC_ALIGNED_SET_OPT_ZERO_FF((dest), (c), (count)); \ + } else { \ + SECUREC_UNALIGNED_SET((dest), (c), (count)); \ + } \ +} SECUREC_WHILE_ZERO + +/* + * Performance optimization + */ +#define SECUREC_MEMSET_OPT(dest, c, count) do { \ + if ((count) > SECUREC_MEMSET_THRESHOLD_SIZE) { \ + SECUREC_MEMSET_PREVENT_DSE((dest), (c), (count)); \ + } else { \ + SECUREC_SMALL_MEM_SET((dest), (c), (count)); \ + } \ +} SECUREC_WHILE_ZERO +#endif + +/* + * Handling errors + */ +SECUREC_INLINE errno_t SecMemsetError(void *dest, size_t destMax, int c) +{ + /* Check destMax is 0 compatible with _sp macro */ + if (destMax == 0 || destMax > SECUREC_MEM_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("memset_s"); + return ERANGE; + } + if (dest == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("memset_s"); + return EINVAL; + } + SECUREC_MEMSET_PREVENT_DSE(dest, c, destMax); /* Set entire buffer to value c */ + SECUREC_ERROR_INVALID_RANGE("memset_s"); + return ERANGE_AND_RESET; +} + +/* + * + * The memset_s function copies the value of c (converted to an unsigned char) + * into each of the first count characters of the object pointed to by dest. + * + * + * dest Pointer to destination. + * destMax The size of the buffer. + * c Character to set. + * count Number of characters. + * + * + * dest buffer is updated. + * + * + * EOK Success + * EINVAL dest == NULL and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN + * ERANGE destMax > SECUREC_MEM_MAX_LEN or (destMax is 0 and count > destMax) + * ERANGE_AND_RESET count > destMax and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN and dest != NULL + * + * if return ERANGE_AND_RESET then fill dest to c ,fill length is destMax + */ +errno_t memset_s(void *dest, size_t destMax, int c, size_t count) +{ + if (SECUREC_MEMSET_PARAM_OK(dest, destMax, count)) { + SECUREC_MEMSET_PREVENT_DSE(dest, c, count); + return EOK; + } + /* Meet some runtime violation, return error code */ + return SecMemsetError(dest, destMax, c); +} + +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(memset_s); +#endif + +#if SECUREC_WITH_PERFORMANCE_ADDONS +/* + * Performance optimization + */ +errno_t memset_sOptAsm(void *dest, size_t destMax, int c, size_t count) +{ + if (SECUREC_MEMSET_PARAM_OK(dest, destMax, count)) { + SECUREC_MEMSET_OPT(dest, c, count); + return EOK; + } + /* Meet some runtime violation, return error code */ + return SecMemsetError(dest, destMax, c); +} + +/* + * Performance optimization, trim judgement on "destMax <= SECUREC_MEM_MAX_LEN" + */ +errno_t memset_sOptTc(void *dest, size_t destMax, int c, size_t count) +{ + if (SECUREC_LIKELY(count <= destMax && dest != NULL)) { + SECUREC_MEMSET_OPT(dest, c, count); + return EOK; + } + /* Meet some runtime violation, return error code */ + return SecMemsetError(dest, destMax, c); +} +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/output.inl b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/output.inl new file mode 100644 index 00000000..9392efaa --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/output.inl @@ -0,0 +1,1720 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: Used by secureprintoutput_a.c and secureprintoutput_w.c to include. + * This file provides a template function for ANSI and UNICODE compiling + * by different type definition. The functions of SecOutputS or + * SecOutputSW provides internal implementation for printf family API, such as sprintf, swprintf_s. + * Create: 2014-02-25 + * Notes: see www.cplusplus.com/reference/cstdio/printf/ + */ +/* + * [Standardize-exceptions] Use unsafe function: Portability + * [reason] Use unsafe function to implement security function to maintain platform compatibility. + * And sufficient input validation is performed before calling + */ +#ifndef OUTPUT_INL_2B263E9C_43D8_44BB_B17A_6D2033DECEE5 +#define OUTPUT_INL_2B263E9C_43D8_44BB_B17A_6D2033DECEE5 + +#ifndef SECUREC_ENABLE_SPRINTF_LONG_DOUBLE +/* Some compilers do not support long double */ +#define SECUREC_ENABLE_SPRINTF_LONG_DOUBLE 1 +#endif + +#define SECUREC_NULL_STRING_SIZE 8 +#define SECUREC_STATE_TABLE_SIZE 337 + +#if defined(SECUREC_VXWORKS_VERSION_5_4) && !defined(SECUREC_ON_64BITS) +#define SECUREC_DIV_QUOTIENT_OCTAL(val64) ((val64) >> 3ULL) +#define SECUREC_DIV_RESIDUE_OCTAL(val64) ((val64) & 7ULL) + +#define SECUREC_DIV_QUOTIENT_HEX(val64) ((val64) >> 4ULL) +#define SECUREC_DIV_RESIDUE_HEX(val64) ((val64) & 0xfULL) +#endif + +#define SECUREC_RADIX_OCTAL 8U +#define SECUREC_RADIX_DECIMAL 10U +#define SECUREC_RADIX_HEX 16U +#define SECUREC_PREFIX_LEN 2 +/* Size include '+' and '\0' */ +#define SECUREC_FLOAT_BUF_EXT 2 + +/* Sign extend or Zero-extend */ +#define SECUREC_GET_LONG_FROM_ARG(attr) ((((attr).flags & SECUREC_FLAG_SIGNED) != 0) ? \ + (SecInt64)(long)va_arg(argList, long) : \ + (SecInt64)(unsigned long)va_arg(argList, long)) + +/* Sign extend or Zero-extend */ +#define SECUREC_GET_CHAR_FROM_ARG(attr) ((((attr).flags & SECUREC_FLAG_SIGNED) != 0) ? \ + SecUpdateNegativeChar(&(attr), ((char)va_arg(argList, int))) : \ + (SecInt64)(unsigned char)va_arg(argList, int)) + +/* Sign extend or Zero-extend */ +#define SECUREC_GET_SHORT_FROM_ARG(attr) ((((attr).flags & SECUREC_FLAG_SIGNED) != 0) ? \ + (SecInt64)(short)va_arg(argList, int) : \ + (SecInt64)(unsigned short)va_arg(argList, int)) + +/* Sign extend or Zero-extend */ +#define SECUREC_GET_INT_FROM_ARG(attr) ((((attr).flags & SECUREC_FLAG_SIGNED) != 0) ? \ + (SecInt64)(int)va_arg(argList, int) : \ + (SecInt64)(unsigned int)va_arg(argList, int)) + +#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT +/* Sign extend or Zero-extend. No suitable macros were found to handle the branch */ +#define SECUREC_GET_SIZE_FROM_ARG(attr) ((((attr).flags & SECUREC_FLAG_SIGNED) != 0) ? \ + ((SecIsSameSize(sizeof(size_t), sizeof(long)) != 0) ? (SecInt64)(long)va_arg(argList, long) : \ + ((SecIsSameSize(sizeof(size_t), sizeof(long long)) != 0) ? (SecInt64)(long long)va_arg(argList, long long) : \ + (SecInt64)(int)va_arg(argList, int))) : \ + (SecInt64)(size_t)va_arg(argList, size_t)) +#endif + +/* Format output buffer pointer and available size */ +typedef struct { + int count; + SecChar *cur; +} SecPrintfStream; + +typedef union { + /* Integer formatting refers to the end of the buffer, plus 1 to prevent tool alarms */ + char str[SECUREC_BUFFER_SIZE + 1]; +#if SECUREC_HAVE_WCHART + wchar_t wStr[SECUREC_WCHAR_BUFFER_SIZE]; /* Just for %lc */ +#endif +} SecBuffer; + +typedef union { + char *str; /* Not a null terminated string */ +#if SECUREC_HAVE_WCHART + wchar_t *wStr; +#endif +} SecFormatBuf; + +typedef struct { + const char *digits; /* Point to the hexadecimal subset */ + SecFormatBuf text; /* Point to formatted string */ + int textLen; /* Length of the text */ + int textIsWide; /* Flag for text is wide chars ; 0 is not wide char */ + unsigned int radix; /* Use for output number , default set to 10 */ + unsigned int flags; + int fldWidth; + int precision; + int dynWidth; /* %* 1 width from variable parameter ;0 not */ + int dynPrecision; /* %.* 1 precision from variable parameter ;0 not */ + int padding; /* Padding len */ + int prefixLen; /* Length of prefix, 0 or 1 or 2 */ + SecChar prefix[SECUREC_PREFIX_LEN]; /* Prefix is 0 or 0x */ + SecBuffer buffer; +} SecFormatAttr; + +#if SECUREC_ENABLE_SPRINTF_FLOAT +#ifdef SECUREC_STACK_SIZE_LESS_THAN_1K +#define SECUREC_FMT_STR_LEN 8 +#else +#define SECUREC_FMT_STR_LEN 16 +#endif +typedef struct { + char buffer[SECUREC_FMT_STR_LEN]; + char *fmtStr; /* Initialization must point to buffer */ + char *allocatedFmtStr; /* Initialization must be NULL to store allocated point */ + char *floatBuffer; /* Use heap memory if the SecFormatAttr.buffer is not enough */ + int bufferSize; /* The size of floatBuffer */ +} SecFloatAdapt; +#endif + +/* Use 20 to Align the data */ +#define SECUREC_DIGITS_BUF_SIZE 20 +/* The serial number of 'x' or 'X' is 16 */ +#define SECUREC_NUMBER_OF_X 16 +/* Some systems can not use pointers to point to string literals, but can use string arrays. */ +/* For example, when handling code under uboot, there is a problem with the pointer */ +static const char g_itoaUpperDigits[SECUREC_DIGITS_BUF_SIZE] = "0123456789ABCDEFX"; +static const char g_itoaLowerDigits[SECUREC_DIGITS_BUF_SIZE] = "0123456789abcdefx"; + +#if SECUREC_ENABLE_SPRINTF_FLOAT +/* Call system sprintf to format float value */ +SECUREC_INLINE int SecFormatFloat(char *strDest, const char *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + SECUREC_MASK_VSPRINTF_WARNING + ret = vsprintf(strDest, format, argList); + SECUREC_END_MASK_VSPRINTF_WARNING + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} + +#if defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && SECUREC_ENABLE_SPRINTF_LONG_DOUBLE +/* Out put long double value to dest */ +SECUREC_INLINE void SecFormatLongDouble(SecFormatAttr *attr, const SecFloatAdapt *floatAdapt, long double ldValue) +{ + int fldWidth = (((attr->flags & SECUREC_FLAG_LEFT) != 0) ? (-attr->fldWidth) : attr->fldWidth); + if (attr->dynWidth != 0 && attr->dynPrecision != 0) { + attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, fldWidth, attr->precision, ldValue); + } else if (attr->dynWidth != 0) { + attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, fldWidth, ldValue); + } else if (attr->dynPrecision != 0) { + attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, attr->precision, ldValue); + } else { + attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, ldValue); + } + if (attr->textLen < 0 || attr->textLen >= floatAdapt->bufferSize) { + attr->textLen = 0; + } +} +#endif + +/* Out put double value to dest */ +SECUREC_INLINE void SecFormatDouble(SecFormatAttr *attr, const SecFloatAdapt *floatAdapt, double dValue) +{ + int fldWidth = (((attr->flags & SECUREC_FLAG_LEFT) != 0) ? (-attr->fldWidth) : attr->fldWidth); + if (attr->dynWidth != 0 && attr->dynPrecision != 0) { + attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, fldWidth, attr->precision, dValue); + } else if (attr->dynWidth != 0) { + attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, fldWidth, dValue); + } else if (attr->dynPrecision != 0) { + attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, attr->precision, dValue); + } else { + attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, dValue); + } + if (attr->textLen < 0 || attr->textLen >= floatAdapt->bufferSize) { + attr->textLen = 0; + } +} +#endif + +#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT +/* To clear e506 warning */ +SECUREC_INLINE int SecIsSameSize(size_t sizeA, size_t sizeB) +{ + return (int)(sizeA == sizeB); +} +#endif + +#ifndef SECUREC_ON_64BITS +/* + * Compiler Optimized Division 8. + * The text.str point to buffer end, must be Large enough + */ +SECUREC_INLINE void SecNumber32ToOctalString(SecUnsignedInt32 number, SecFormatAttr *attr) +{ + SecUnsignedInt32 val32 = number; + do { + --attr->text.str; + /* Just use lowerDigits for 0 - 9 */ + *(attr->text.str) = g_itoaLowerDigits[val32 % SECUREC_RADIX_OCTAL]; + val32 /= SECUREC_RADIX_OCTAL; + } while (val32 != 0); +} + +#ifdef _AIX +/* + * Compiler Optimized Division 10. + * The text.str point to buffer end, must be Large enough + */ +SECUREC_INLINE void SecNumber32ToDecString(SecUnsignedInt32 number, SecFormatAttr *attr) +{ + SecUnsignedInt32 val32 = number; + do { + --attr->text.str; + /* Just use lowerDigits for 0 - 9 */ + *(attr->text.str) = g_itoaLowerDigits[val32 % SECUREC_RADIX_DECIMAL]; + val32 /= SECUREC_RADIX_DECIMAL; + } while (val32 != 0); +} +#endif +/* + * Compiler Optimized Division 16. + * The text.str point to buffer end, must be Large enough + */ +SECUREC_INLINE void SecNumber32ToHexString(SecUnsignedInt32 number, SecFormatAttr *attr) +{ + SecUnsignedInt32 val32 = number; + do { + --attr->text.str; + *(attr->text.str) = attr->digits[val32 % SECUREC_RADIX_HEX]; + val32 /= SECUREC_RADIX_HEX; + } while (val32 != 0); +} + +#ifndef _AIX +/* Use fast div 10 */ +SECUREC_INLINE void SecNumber32ToDecStringFast(SecUnsignedInt32 number, SecFormatAttr *attr) +{ + SecUnsignedInt32 val32 = number; + do { + SecUnsignedInt32 quotient; + SecUnsignedInt32 remain; + --attr->text.str; + *(attr->text.str) = g_itoaLowerDigits[val32 % SECUREC_RADIX_DECIMAL]; + quotient = (val32 >> 1U) + (val32 >> 2U); /* Fast div magic 2 */ + quotient = quotient + (quotient >> 4U); /* Fast div magic 4 */ + quotient = quotient + (quotient >> 8U); /* Fast div magic 8 */ + quotient = quotient + (quotient >> 16U); /* Fast div magic 16 */ + quotient = quotient >> 3U; /* Fast div magic 3 */ + remain = val32 - SECUREC_MUL_TEN(quotient); + val32 = (remain > 9U) ? (quotient + 1U) : quotient; /* Fast div magic 9 */ + } while (val32 != 0); +} +#endif + +SECUREC_INLINE void SecNumber32ToString(SecUnsignedInt32 number, SecFormatAttr *attr) +{ + switch (attr->radix) { + case SECUREC_RADIX_HEX: + SecNumber32ToHexString(number, attr); + break; + case SECUREC_RADIX_OCTAL: + SecNumber32ToOctalString(number, attr); + break; + case SECUREC_RADIX_DECIMAL: +#ifdef _AIX + /* The compiler will optimize div 10 */ + SecNumber32ToDecString(number, attr); +#else + SecNumber32ToDecStringFast(number, attr); +#endif + break; + default: + /* Do nothing */ + break; + } +} +#endif + +#if defined(SECUREC_USE_SPECIAL_DIV64) || (defined(SECUREC_VXWORKS_VERSION_5_4) && !defined(SECUREC_ON_64BITS)) +/* + * This function just to clear warning, on sume vxworks compiler shift 32 bit make warnings + */ +SECUREC_INLINE SecUnsignedInt64 SecU64Shr32(SecUnsignedInt64 number) +{ + return (((number) >> 16U) >> 16U); /* Two shifts of 16 bits to realize shifts of 32 bits */ +} +/* + * Fast divide by 10 algorithm. + * Calculation divisor multiply 0xcccccccccccccccdULL, resultHi64 >> 3 as quotient + */ +SECUREC_INLINE void SecU64Div10(SecUnsignedInt64 divisor, SecUnsignedInt64 *quotient, SecUnsignedInt32 *residue) +{ + SecUnsignedInt64 mask = 0xffffffffULL; /* Use 0xffffffffULL as 32 bit mask */ + SecUnsignedInt64 magicHi = 0xccccccccULL; /* Fast divide 10 magic numbers high 32bit 0xccccccccULL */ + SecUnsignedInt64 magicLow = 0xcccccccdULL; /* Fast divide 10 magic numbers low 32bit 0xcccccccdULL */ + SecUnsignedInt64 divisorHi = (SecUnsignedInt64)(SecU64Shr32(divisor)); /* High 32 bit use */ + SecUnsignedInt64 divisorLow = (SecUnsignedInt64)(divisor & mask); /* Low 32 bit mask */ + SecUnsignedInt64 factorHi = divisorHi * magicHi; + SecUnsignedInt64 factorLow1 = divisorHi * magicLow; + SecUnsignedInt64 factorLow2 = divisorLow * magicHi; + SecUnsignedInt64 factorLow3 = divisorLow * magicLow; + SecUnsignedInt64 carry = (factorLow1 & mask) + (factorLow2 & mask) + SecU64Shr32(factorLow3); + SecUnsignedInt64 resultHi64 = factorHi + SecU64Shr32(factorLow1) + SecU64Shr32(factorLow2) + SecU64Shr32(carry); + + *quotient = resultHi64 >> 3U; /* Fast divide 10 magic numbers 3 */ + *residue = (SecUnsignedInt32)(divisor - ((*quotient) * 10)); /* Quotient mul 10 */ + return; +} +#if defined(SECUREC_VXWORKS_VERSION_5_4) && !defined(SECUREC_ON_64BITS) +/* + * Divide function for VXWORKS + */ +SECUREC_INLINE int SecU64Div32(SecUnsignedInt64 divisor, SecUnsignedInt32 radix, + SecUnsignedInt64 *quotient, SecUnsignedInt32 *residue) +{ + switch (radix) { + case SECUREC_RADIX_DECIMAL: + SecU64Div10(divisor, quotient, residue); + break; + case SECUREC_RADIX_HEX: + *quotient = SECUREC_DIV_QUOTIENT_HEX(divisor); + *residue = (SecUnsignedInt32)SECUREC_DIV_RESIDUE_HEX(divisor); + break; + case SECUREC_RADIX_OCTAL: + *quotient = SECUREC_DIV_QUOTIENT_OCTAL(divisor); + *residue = (SecUnsignedInt32)SECUREC_DIV_RESIDUE_OCTAL(divisor); + break; + default: + return -1; /* This does not happen in the current file */ + } + return 0; +} +SECUREC_INLINE void SecNumber64ToStringSpecial(SecUnsignedInt64 number, SecFormatAttr *attr) +{ + SecUnsignedInt64 val64 = number; + do { + SecUnsignedInt32 digit = 0; /* Ascii value of digit */ + SecUnsignedInt64 quotient = 0; + if (SecU64Div32(val64, (SecUnsignedInt32)attr->radix, "ient, &digit) != 0) { + /* Just break, when enter this function, no error is returned */ + break; + } + --attr->text.str; + *(attr->text.str) = attr->digits[digit]; + val64 = quotient; + } while (val64 != 0); +} +#endif +#endif + +#if defined(SECUREC_ON_64BITS) || !defined(SECUREC_VXWORKS_VERSION_5_4) +#if defined(SECUREC_USE_SPECIAL_DIV64) +/* The compiler does not provide 64 bit division problems */ +SECUREC_INLINE void SecNumber64ToDecString(SecUnsignedInt64 number, SecFormatAttr *attr) +{ + SecUnsignedInt64 val64 = number; + do { + SecUnsignedInt64 quotient = 0; + SecUnsignedInt32 digit = 0; + SecU64Div10(val64, "ient, &digit); + --attr->text.str; + /* Just use lowerDigits for 0 - 9 */ + *(attr->text.str) = g_itoaLowerDigits[digit]; + val64 = quotient; + } while (val64 != 0); +} +#else +/* + * Compiler Optimized Division 10. + * The text.str point to buffer end, must be Large enough + */ +SECUREC_INLINE void SecNumber64ToDecString(SecUnsignedInt64 number, SecFormatAttr *attr) +{ + SecUnsignedInt64 val64 = number; + do { + --attr->text.str; + /* Just use lowerDigits for 0 - 9 */ + *(attr->text.str) = g_itoaLowerDigits[val64 % SECUREC_RADIX_DECIMAL]; + val64 /= SECUREC_RADIX_DECIMAL; + } while (val64 != 0); +} +#endif + +/* + * Compiler Optimized Division 8. + * The text.str point to buffer end, must be Large enough + */ +SECUREC_INLINE void SecNumber64ToOctalString(SecUnsignedInt64 number, SecFormatAttr *attr) +{ + SecUnsignedInt64 val64 = number; + do { + --attr->text.str; + /* Just use lowerDigits for 0 - 9 */ + *(attr->text.str) = g_itoaLowerDigits[val64 % SECUREC_RADIX_OCTAL]; + val64 /= SECUREC_RADIX_OCTAL; + } while (val64 != 0); +} +/* + * Compiler Optimized Division 16. + * The text.str point to buffer end, must be Large enough + */ +SECUREC_INLINE void SecNumber64ToHexString(SecUnsignedInt64 number, SecFormatAttr *attr) +{ + SecUnsignedInt64 val64 = number; + do { + --attr->text.str; + *(attr->text.str) = attr->digits[val64 % SECUREC_RADIX_HEX]; + val64 /= SECUREC_RADIX_HEX; + } while (val64 != 0); +} + +SECUREC_INLINE void SecNumber64ToString(SecUnsignedInt64 number, SecFormatAttr *attr) +{ + switch (attr->radix) { + /* The compiler will optimize div 10 */ + case SECUREC_RADIX_DECIMAL: + SecNumber64ToDecString(number, attr); + break; + case SECUREC_RADIX_OCTAL: + SecNumber64ToOctalString(number, attr); + break; + case SECUREC_RADIX_HEX: + SecNumber64ToHexString(number, attr); + break; + default: + /* Do nothing */ + break; + } +} +#endif + +/* + * Converting integers to string + */ +SECUREC_INLINE void SecNumberToString(SecUnsignedInt64 number, SecFormatAttr *attr) +{ +#ifdef SECUREC_ON_64BITS + SecNumber64ToString(number, attr); +#else /* For 32 bits system */ + if (number <= 0xffffffffUL) { /* Use 0xffffffffUL to check if the value is in the 32-bit range */ + /* In most case, the value to be converted is small value */ + SecUnsignedInt32 n32Tmp = (SecUnsignedInt32)number; + SecNumber32ToString(n32Tmp, attr); + } else { + /* The value to be converted is greater than 4G */ +#if defined(SECUREC_VXWORKS_VERSION_5_4) + SecNumber64ToStringSpecial(number, attr); +#else + SecNumber64ToString(number, attr); +#endif + } +#endif +} + +SECUREC_INLINE int SecIsNumberNeedTo32Bit(const SecFormatAttr *attr) +{ + return (int)(((attr->flags & SECUREC_FLAG_I64) == 0) && +#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT + ((attr->flags & SECUREC_FLAG_INTMAX) == 0) && +#endif +#ifdef SECUREC_ON_64BITS + ((attr->flags & SECUREC_FLAG_PTRDIFF) == 0) && + ((attr->flags & SECUREC_FLAG_SIZE) == 0) && +#if !defined(SECUREC_COMPATIBLE_WIN_FORMAT) /* on window 64 system sizeof long is 32bit */ + ((attr->flags & SECUREC_FLAG_LONG) == 0) && +#endif +#endif + ((attr->flags & SECUREC_FLAG_LONGLONG) == 0)); +} + +SECUREC_INLINE void SecNumberToBuffer(SecFormatAttr *attr, SecInt64 num64) +{ + SecUnsignedInt64 number; + /* Check for negative; copy into number */ + if ((attr->flags & SECUREC_FLAG_SIGNED) != 0 && num64 < 0) { + number = (SecUnsignedInt64)(0 - (SecUnsignedInt64)num64); /* Wrap with unsigned int64 numbers */ + attr->flags |= SECUREC_FLAG_NEGATIVE; + } else { + number = (SecUnsignedInt64)num64; + } + if (SecIsNumberNeedTo32Bit(attr) != 0) { + number = (number & (SecUnsignedInt64)0xffffffffUL); /* Use 0xffffffff as 32 bit mask */ + } + + /* The text.str must be point to buffer.str, this pointer is used outside the function */ + attr->text.str = &attr->buffer.str[SECUREC_BUFFER_SIZE]; + + if (number == 0) { + /* Turn off hex prefix default, and textLen is zero */ + attr->prefixLen = 0; + attr->textLen = 0; + return; + } + + /* Convert integer to string. It must be invoked when number > 0, otherwise the following logic is incorrect */ + SecNumberToString(number, attr); + /* Compute length of number, text.str must be in buffer.str */ + attr->textLen = (int)(size_t)((char *)&attr->buffer.str[SECUREC_BUFFER_SIZE] - attr->text.str); +} + +/* + * Write one character to dest buffer + */ +SECUREC_INLINE void SecWriteChar(SecPrintfStream *stream, SecChar ch, int *charsOut) +{ + /* Count must be reduced first, In order to identify insufficient length */ + --stream->count; + if (stream->count >= 0) { + *(stream->cur) = ch; + ++stream->cur; + *charsOut = *charsOut + 1; + return; + } + /* No enough length */ + *charsOut = -1; +} + +/* +* Write multiple identical characters. +*/ +SECUREC_INLINE void SecWriteMultiChar(SecPrintfStream *stream, SecChar ch, int num, int *charsOut) +{ + int count; + for (count = num; count > 0; --count) { + --stream->count; /* count may be negative,indicating insufficient space */ + if (stream->count < 0) { + *charsOut = -1; + return; + } + *(stream->cur) = ch; + ++stream->cur; + } + *charsOut = *charsOut + num; +} + +/* +* Write string function, where this function is called, make sure that len is greater than 0 +*/ +SECUREC_INLINE void SecWriteString(SecPrintfStream *stream, const SecChar *str, int len, int *charsOut) +{ + const SecChar *tmp = str; + int count; + for (count = len; count > 0; --count) { + --stream->count; /* count may be negative,indicating insufficient space */ + if (stream->count < 0) { + *charsOut = -1; + return; + } + *(stream->cur) = *tmp; + ++stream->cur; + ++tmp; + } + *charsOut = *charsOut + len; +} + +/* Use loop copy char or wchar_t string */ +SECUREC_INLINE void SecWriteStringByLoop(SecPrintfStream *stream, const SecChar *str, int len) +{ + int i; + const SecChar *tmp = str; + for (i = 0; i < len; ++i) { + *stream->cur = *tmp; + ++stream->cur; + ++tmp; + } + stream->count -= len; +} + +SECUREC_INLINE void SecWriteStringOpt(SecPrintfStream *stream, const SecChar *str, int len) +{ + if (len < 12) { /* Performance optimization for mobile number length 12 */ + SecWriteStringByLoop(stream, str, len); + } else { + size_t count = (size_t)(unsigned int)len * sizeof(SecChar); + SECUREC_MEMCPY_WARP_OPT(stream->cur, str, count); + stream->cur += len; + stream->count -= len; + } +} + +/* + * Return if buffer length is enough + * The count variable can be reduced to 0, and the external function complements the \0 terminator. + */ +SECUREC_INLINE int SecIsStreamBufEnough(const SecPrintfStream *stream, int needLen) +{ + return (int)(stream->count >= needLen); +} + +/* Write text string */ +SECUREC_INLINE void SecWriteTextOpt(SecPrintfStream *stream, const SecChar *str, int len, int *charsOut) +{ + if (SecIsStreamBufEnough(stream, len) != 0) { + SecWriteStringOpt(stream, str, len); + *charsOut += len; + } else { + SecWriteString(stream, str, len, charsOut); + } +} + +/* Write left padding */ +SECUREC_INLINE void SecWriteLeftPadding(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) +{ + if ((attr->flags & (SECUREC_FLAG_LEFT | SECUREC_FLAG_LEADZERO)) == 0 && attr->padding > 0) { + /* Pad on left with blanks */ + SecWriteMultiChar(stream, SECUREC_CHAR(' '), attr->padding, charsOut); + } +} + +/* Write prefix */ +SECUREC_INLINE void SecWritePrefix(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) +{ + if (attr->prefixLen > 0) { + SecWriteString(stream, attr->prefix, attr->prefixLen, charsOut); + } +} + +/* Write leading zeros */ +SECUREC_INLINE void SecWriteLeadingZero(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) +{ + if ((attr->flags & SECUREC_FLAG_LEADZERO) != 0 && (attr->flags & SECUREC_FLAG_LEFT) == 0 && + attr->padding > 0) { + SecWriteMultiChar(stream, SECUREC_CHAR('0'), attr->padding, charsOut); + } +} + +/* Write right padding */ +SECUREC_INLINE void SecWriteRightPadding(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) +{ + if (*charsOut >= 0 && (attr->flags & SECUREC_FLAG_LEFT) != 0 && attr->padding > 0) { + /* Pad on right with blanks */ + SecWriteMultiChar(stream, SECUREC_CHAR(' '), attr->padding, charsOut); + } +} + +#ifdef SECUREC_FOR_WCHAR +#define SECUREC_TEXT_CHAR_PTR(text) ((text).wStr) +#define SECUREC_NEED_CONVERT_TEXT(attr) ((attr)->textIsWide == 0) +#if SECUREC_HAVE_MBTOWC +#define SECUREC_WRITE_TEXT_AFTER_CONVERT(stream, attr, charsOut) SecWriteTextAfterMbtowc((stream), (attr), (charsOut)) +#else +#define SECUREC_WRITE_TEXT_AFTER_CONVERT(stream, attr, charsOut) (*(charsOut) = -1) +#endif +#else +#define SECUREC_TEXT_CHAR_PTR(text) ((text).str) +#define SECUREC_NEED_CONVERT_TEXT(attr) ((attr)->textIsWide != 0) +#if SECUREC_HAVE_WCTOMB +#define SECUREC_WRITE_TEXT_AFTER_CONVERT(stream, attr, charsOut) SecWriteTextAfterWctomb((stream), (attr), (charsOut)) +#else +#define SECUREC_WRITE_TEXT_AFTER_CONVERT(stream, attr, charsOut) (*(charsOut) = -1) +#endif +#endif + +#ifdef SECUREC_FOR_WCHAR +#if SECUREC_HAVE_MBTOWC +SECUREC_INLINE void SecWriteTextAfterMbtowc(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) +{ + const char *p = attr->text.str; + int count = attr->textLen; + while (count > 0) { + wchar_t wChar = L'\0'; + int retVal = mbtowc(&wChar, p, (size_t)MB_CUR_MAX); + if (retVal <= 0) { + *charsOut = -1; + break; + } + SecWriteChar(stream, wChar, charsOut); + if (*charsOut == -1) { + break; + } + p += retVal; + count -= retVal; + } +} +#endif +#else /* Not SECUREC_FOR_WCHAR */ +#if SECUREC_HAVE_WCTOMB +SECUREC_INLINE void SecWriteTextAfterWctomb(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) +{ + const wchar_t *p = attr->text.wStr; + int count = attr->textLen; + while (count > 0) { + char tmpBuf[SECUREC_MB_LEN + 1]; + SECUREC_MASK_MSVC_CRT_WARNING + int retVal = wctomb(tmpBuf, *p); + SECUREC_END_MASK_MSVC_CRT_WARNING + if (retVal <= 0) { + *charsOut = -1; + break; + } + SecWriteString(stream, tmpBuf, retVal, charsOut); + if (*charsOut == -1) { + break; + } + --count; + ++p; + } +} +#endif +#endif + +#if SECUREC_ENABLE_SPRINTF_FLOAT +/* + * Write text of float + * Using independent functions to optimize the expansion of inline functions by the compiler + */ +SECUREC_INLINE void SecWriteFloatText(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) +{ +#ifdef SECUREC_FOR_WCHAR +#if SECUREC_HAVE_MBTOWC + SecWriteTextAfterMbtowc(stream, attr, charsOut); +#else + *charsOut = -1; + (void)stream; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + (void)attr; /* To clear e438 last value assigned not used , the compiler will optimize this code */ +#endif +#else /* Not SECUREC_FOR_WCHAR */ + SecWriteString(stream, attr->text.str, attr->textLen, charsOut); +#endif +} +#endif + +/* Write text of integer or string ... */ +SECUREC_INLINE void SecWriteText(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) +{ + if (SECUREC_NEED_CONVERT_TEXT(attr)) { + SECUREC_WRITE_TEXT_AFTER_CONVERT(stream, attr, charsOut); + } else { + SecWriteTextOpt(stream, SECUREC_TEXT_CHAR_PTR(attr->text), attr->textLen, charsOut); + } +} + +#define SECUREC_FMT_STATE_OFFSET 256 + +SECUREC_INLINE SecFmtState SecDecodeState(SecChar ch, SecFmtState lastState) +{ + static const unsigned char stateTable[SECUREC_STATE_TABLE_SIZE] = { + /* + * Type + * 0: nospecial meaning; + * 1: '%' + * 2: '.' + * 3: '*' + * 4: '0' + * 5: '1' ... '9' + * 6: ' ', '+', '-', '#' + * 7: 'h', 'l', 'L', 'w' , 'N', 'z', 'q', 't', 'j' + * 8: 'd', 'o', 'u', 'i', 'x', 'X', 'e', 'f', 'g', 'E', 'F', 'G', 's', 'c', '[', 'p' + */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x06, 0x00, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x03, 0x06, 0x00, 0x06, 0x02, 0x00, + 0x04, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x08, 0x08, 0x00, 0x07, 0x00, 0x00, 0x07, 0x00, 0x07, 0x00, + 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x07, 0x08, 0x07, 0x00, 0x07, 0x00, 0x00, 0x08, + 0x08, 0x07, 0x00, 0x08, 0x07, 0x08, 0x00, 0x07, 0x08, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, + /* Fill zero for normal char 128 byte for 0x80 - 0xff */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* + * State + * 0: normal + * 1: percent + * 2: flag + * 3: width + * 4: dot + * 5: precis + * 6: size + * 7: type + * 8: invalid + */ + 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x01, 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, + 0x01, 0x00, 0x00, 0x04, 0x04, 0x04, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x03, 0x03, 0x08, 0x05, + 0x08, 0x08, 0x00, 0x00, 0x00, 0x02, 0x02, 0x03, 0x05, 0x05, 0x08, 0x00, 0x00, 0x00, 0x03, 0x03, + 0x03, 0x05, 0x05, 0x08, 0x00, 0x00, 0x00, 0x02, 0x02, 0x02, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, + 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x00, + 0x00 + }; + +#ifdef SECUREC_FOR_WCHAR + /* Convert to unsigned char to clear gcc 4.3.4 warning */ + unsigned char fmtType = (unsigned char)((((unsigned int)(int)(ch)) <= (unsigned int)(int)(L'~')) ? \ + (stateTable[(unsigned char)(ch)]) : 0); + return (SecFmtState)(stateTable[fmtType * ((unsigned char)STAT_INVALID + 1) + + (unsigned char)(lastState) + SECUREC_FMT_STATE_OFFSET]); +#else + unsigned char fmtType = stateTable[(unsigned char)(ch)]; + return (SecFmtState)(stateTable[fmtType * ((unsigned char)STAT_INVALID + 1) + + (unsigned char)(lastState) + SECUREC_FMT_STATE_OFFSET]); +#endif +} + +SECUREC_INLINE void SecDecodeFlags(SecChar ch, SecFormatAttr *attr) +{ + switch (ch) { + case SECUREC_CHAR(' '): + attr->flags |= SECUREC_FLAG_SIGN_SPACE; + break; + case SECUREC_CHAR('+'): + attr->flags |= SECUREC_FLAG_SIGN; + break; + case SECUREC_CHAR('-'): + attr->flags |= SECUREC_FLAG_LEFT; + break; + case SECUREC_CHAR('0'): + attr->flags |= SECUREC_FLAG_LEADZERO; /* Add zero th the front */ + break; + case SECUREC_CHAR('#'): + attr->flags |= SECUREC_FLAG_ALTERNATE; /* Output %x with 0x */ + break; + default: + /* Do nothing */ + break; + } + return; +} + +/* + * Decoded size identifier in format string to Reduce the number of lines of function code + */ +SECUREC_INLINE int SecDecodeSizeI(SecFormatAttr *attr, const SecChar **format) +{ +#ifdef SECUREC_ON_64BITS + attr->flags |= SECUREC_FLAG_I64; /* %I to INT64 */ +#endif + if ((**format == SECUREC_CHAR('6')) && (*((*format) + 1) == SECUREC_CHAR('4'))) { + (*format) += 2; /* Add 2 to skip I64 */ + attr->flags |= SECUREC_FLAG_I64; /* %I64 to INT64 */ + } else if ((**format == SECUREC_CHAR('3')) && (*((*format) + 1) == SECUREC_CHAR('2'))) { + (*format) += 2; /* Add 2 to skip I32 */ + attr->flags &= ~SECUREC_FLAG_I64; /* %I64 to INT32 */ + } else if ((**format == SECUREC_CHAR('d')) || (**format == SECUREC_CHAR('i')) || + (**format == SECUREC_CHAR('o')) || (**format == SECUREC_CHAR('u')) || + (**format == SECUREC_CHAR('x')) || (**format == SECUREC_CHAR('X'))) { + /* Do nothing */ + } else { + /* Compatibility code for "%I" just print I */ + return -1; + } + return 0; +} + +/* + * Decoded size identifier in format string, and skip format to next charater + */ +SECUREC_INLINE int SecDecodeSize(SecChar ch, SecFormatAttr *attr, const SecChar **format) +{ + switch (ch) { + case SECUREC_CHAR('l'): + if (**format == SECUREC_CHAR('l')) { + *format = *format + 1; + attr->flags |= SECUREC_FLAG_LONGLONG; /* For long long */ + } else { + attr->flags |= SECUREC_FLAG_LONG; /* For long int or wchar_t */ + } + break; +#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT + case SECUREC_CHAR('z'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('Z'): + attr->flags |= SECUREC_FLAG_SIZE; + break; + case SECUREC_CHAR('j'): + attr->flags |= SECUREC_FLAG_INTMAX; + break; +#endif + case SECUREC_CHAR('t'): + attr->flags |= SECUREC_FLAG_PTRDIFF; + break; + case SECUREC_CHAR('q'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('L'): + attr->flags |= (SECUREC_FLAG_LONGLONG | SECUREC_FLAG_LONG_DOUBLE); + break; + case SECUREC_CHAR('I'): + if (SecDecodeSizeI(attr, format) != 0) { + /* Compatibility code for "%I" just print I */ + return -1; + } + break; + case SECUREC_CHAR('h'): + if (**format == SECUREC_CHAR('h')) { + *format = *format + 1; + attr->flags |= SECUREC_FLAG_CHAR; /* For char */ + } else { + attr->flags |= SECUREC_FLAG_SHORT; /* For short int */ + } + break; + case SECUREC_CHAR('w'): + attr->flags |= SECUREC_FLAG_WIDECHAR; /* For wide char */ + break; + default: + /* Do nothing */ + break; + } + return 0; +} + +/* + * Decoded char type identifier + */ +SECUREC_INLINE void SecDecodeTypeC(SecFormatAttr *attr, unsigned int c) +{ + attr->textLen = 1; /* Only 1 wide character */ + +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT)) && !(defined(__hpux)) && !(defined(SECUREC_ON_SOLARIS)) + attr->flags &= ~SECUREC_FLAG_LEADZERO; +#endif + +#ifdef SECUREC_FOR_WCHAR + if ((attr->flags & SECUREC_FLAG_SHORT) != 0) { + /* Get multibyte character from argument */ + attr->buffer.str[0] = (char)c; + attr->text.str = attr->buffer.str; + attr->textIsWide = 0; + } else { + attr->buffer.wStr[0] = (wchar_t)c; + attr->text.wStr = attr->buffer.wStr; + attr->textIsWide = 1; + } +#else /* Not SECUREC_FOR_WCHAR */ + if ((attr->flags & (SECUREC_FLAG_LONG | SECUREC_FLAG_WIDECHAR)) != 0) { +#if SECUREC_HAVE_WCHART + attr->buffer.wStr[0] = (wchar_t)c; + attr->text.wStr = attr->buffer.wStr; + attr->textIsWide = 1; +#else + attr->textLen = 0; /* Ignore unsupported characters */ + attr->fldWidth = 0; /* No paddings */ +#endif + } else { + /* Get multibyte character from argument */ + attr->buffer.str[0] = (char)c; + attr->text.str = attr->buffer.str; + attr->textIsWide = 0; + } +#endif +} + +#ifdef SECUREC_FOR_WCHAR +#define SECUREC_IS_NARROW_STRING(attr) (((attr)->flags & SECUREC_FLAG_SHORT) != 0) +#else +#define SECUREC_IS_NARROW_STRING(attr) (((attr)->flags & (SECUREC_FLAG_LONG | SECUREC_FLAG_WIDECHAR)) == 0) +#endif + +SECUREC_INLINE void SecDecodeTypeSchar(SecFormatAttr *attr) +{ + size_t textLen; + if (attr->text.str == NULL) { + /* + * Literal string to print null ptr, define it as array rather than const text area + * To avoid gcc warning with pointing const text with variable + */ + static char strNullString[SECUREC_NULL_STRING_SIZE] = "(null)"; + attr->text.str = strNullString; + } + if (attr->precision == -1) { + /* Precision NOT assigned */ + /* The strlen performance is high when the string length is greater than 32 */ + textLen = strlen(attr->text.str); + if (textLen > SECUREC_STRING_MAX_LEN) { + textLen = 0; + } + } else { + /* Precision assigned */ + SECUREC_CALC_STR_LEN(attr->text.str, (size_t)(unsigned int)attr->precision, &textLen); + } + attr->textLen = (int)textLen; +} + +SECUREC_INLINE void SecDecodeTypeSwchar(SecFormatAttr *attr) +{ +#if SECUREC_HAVE_WCHART + size_t textLen; + attr->textIsWide = 1; + if (attr->text.wStr == NULL) { + /* + * Literal string to print null ptr, define it as array rather than const text area + * To avoid gcc warning with pointing const text with variable + */ + static wchar_t wStrNullString[SECUREC_NULL_STRING_SIZE] = { L'(', L'n', L'u', L'l', L'l', L')', L'\0', L'\0' }; + attr->text.wStr = wStrNullString; + } + /* The textLen in wchar_t,when precision is -1, it is unlimited */ + SECUREC_CALC_WSTR_LEN(attr->text.wStr, (size_t)(unsigned int)attr->precision, &textLen); + if (textLen > SECUREC_WCHAR_STRING_MAX_LEN) { + textLen = 0; + } + attr->textLen = (int)textLen; +#else + attr->textLen = 0; +#endif +} + +/* + * Decoded string identifier + */ +SECUREC_INLINE void SecDecodeTypeS(SecFormatAttr *attr, char *argPtr) +{ +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT)) +#if (!defined(SECUREC_ON_UNIX)) + attr->flags &= ~SECUREC_FLAG_LEADZERO; +#endif +#if (defined(SECUREC_FOR_WCHAR)) + if ((attr->flags & SECUREC_FLAG_LONG) == 0) { + attr->flags |= SECUREC_FLAG_SHORT; + } +#endif +#endif + attr->text.str = argPtr; + if (SECUREC_IS_NARROW_STRING(attr)) { + /* The textLen now contains length in multibyte chars */ + SecDecodeTypeSchar(attr); + } else { + /* The textLen now contains length in wide chars */ + SecDecodeTypeSwchar(attr); + } +} + +/* + * Check precision in format + */ +SECUREC_INLINE int SecDecodePrecision(SecChar ch, SecFormatAttr *attr) +{ + if (attr->dynPrecision == 0) { + /* Add digit to current precision */ + if (SECUREC_MUL_TEN_ADD_BEYOND_MAX(attr->precision)) { + return -1; + } + attr->precision = (int)SECUREC_MUL_TEN((unsigned int)attr->precision) + + (unsigned char)(ch - SECUREC_CHAR('0')); + } else { + if (attr->precision < 0) { + attr->precision = -1; + } + if (attr->precision > SECUREC_MAX_WIDTH_LEN) { + return -1; + } + } + return 0; +} + +/* + * Check width in format + */ +SECUREC_INLINE int SecDecodeWidth(SecChar ch, SecFormatAttr *attr, SecFmtState lastState) +{ + if (attr->dynWidth == 0) { + if (lastState != STAT_WIDTH) { + attr->fldWidth = 0; + } + if (SECUREC_MUL_TEN_ADD_BEYOND_MAX(attr->fldWidth)) { + return -1; + } + attr->fldWidth = (int)SECUREC_MUL_TEN((unsigned int)attr->fldWidth) + + (unsigned char)(ch - SECUREC_CHAR('0')); + } else { + if (attr->fldWidth < 0) { + attr->flags |= SECUREC_FLAG_LEFT; + attr->fldWidth = (-attr->fldWidth); + } + if (attr->fldWidth > SECUREC_MAX_WIDTH_LEN) { + return -1; + } + } + return 0; +} + +/* + * The sprintf_s function processes the wide character as a parameter for %C + * The swprintf_s function processes the multiple character as a parameter for %C + */ +SECUREC_INLINE void SecUpdateWcharFlags(SecFormatAttr *attr) +{ + if ((attr->flags & (SECUREC_FLAG_SHORT | SECUREC_FLAG_LONG | SECUREC_FLAG_WIDECHAR)) == 0) { +#ifdef SECUREC_FOR_WCHAR + attr->flags |= SECUREC_FLAG_SHORT; +#else + attr->flags |= SECUREC_FLAG_WIDECHAR; +#endif + } +} +/* + * When encountering %S, current just same as %C + */ +SECUREC_INLINE void SecUpdateWstringFlags(SecFormatAttr *attr) +{ + SecUpdateWcharFlags(attr); +} + +#if SECUREC_IN_KERNEL +SECUREC_INLINE void SecUpdatePointFlagsForKernel(SecFormatAttr *attr) +{ + /* Width is not set */ + if (attr->fldWidth <= 0) { + attr->flags |= SECUREC_FLAG_LEADZERO; + attr->fldWidth = 2 * sizeof(void *); /* 2 x byte number is the length of hex */ + } + if ((attr->flags & SECUREC_FLAG_ALTERNATE) != 0) { + /* Alternate form means '0x' prefix */ + attr->prefix[0] = SECUREC_CHAR('0'); + attr->prefix[1] = SECUREC_CHAR('x'); + attr->prefixLen = SECUREC_PREFIX_LEN; + } + attr->flags |= SECUREC_FLAG_LONG; /* Converting a long */ +} +#endif + +SECUREC_INLINE void SecUpdatePointFlags(SecFormatAttr *attr) +{ + attr->flags |= SECUREC_FLAG_POINTER; +#if SECUREC_IN_KERNEL + SecUpdatePointFlagsForKernel(attr); +#else +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) || defined(SECUREC_VXWORKS_PLATFORM)) && (!defined(SECUREC_ON_UNIX)) +#if defined(SECUREC_VXWORKS_PLATFORM) + attr->precision = 1; +#else + attr->precision = 0; +#endif + attr->flags |= SECUREC_FLAG_ALTERNATE; /* "0x" is not default prefix in UNIX */ + attr->digits = g_itoaLowerDigits; +#else /* On unix or win */ +#if defined(_AIX) || defined(SECUREC_ON_SOLARIS) + attr->precision = 1; +#else + attr->precision = 2 * sizeof(void *); /* 2 x byte number is the length of hex */ +#endif +#if defined(SECUREC_ON_UNIX) + attr->digits = g_itoaLowerDigits; +#else + attr->digits = g_itoaUpperDigits; +#endif +#endif + +#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) + attr->flags &= ~SECUREC_FLAG_LEADZERO; +#endif + +#ifdef SECUREC_ON_64BITS + attr->flags |= SECUREC_FLAG_I64; /* Converting an int64 */ +#else + attr->flags |= SECUREC_FLAG_LONG; /* Converting a long */ +#endif + /* Set up for %#p on different system */ + if ((attr->flags & SECUREC_FLAG_ALTERNATE) != 0) { + /* Alternate form means '0x' prefix */ + attr->prefix[0] = SECUREC_CHAR('0'); +#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) || defined(SECUREC_VXWORKS_PLATFORM)) + attr->prefix[1] = SECUREC_CHAR('x'); +#else + attr->prefix[1] = (SecChar)(attr->digits[SECUREC_NUMBER_OF_X]); +#endif +#if defined(_AIX) || defined(SECUREC_ON_SOLARIS) + attr->prefixLen = 0; +#else + attr->prefixLen = SECUREC_PREFIX_LEN; +#endif + } +#endif +} + +SECUREC_INLINE void SecUpdateXpxFlags(SecFormatAttr *attr, SecChar ch) +{ + /* Use unsigned lower hex output for 'x' */ + attr->digits = g_itoaLowerDigits; + attr->radix = SECUREC_RADIX_HEX; + switch (ch) { + case SECUREC_CHAR('p'): + /* Print a pointer */ + SecUpdatePointFlags(attr); + break; + case SECUREC_CHAR('X'): /* fall-through */ /* FALLTHRU */ + /* Unsigned upper hex output */ + attr->digits = g_itoaUpperDigits; + /* fall-through */ /* FALLTHRU */ + default: + /* For %#x or %#X */ + if ((attr->flags & SECUREC_FLAG_ALTERNATE) != 0) { + /* Alternate form means '0x' prefix */ + attr->prefix[0] = SECUREC_CHAR('0'); + attr->prefix[1] = (SecChar)(attr->digits[SECUREC_NUMBER_OF_X]); + attr->prefixLen = SECUREC_PREFIX_LEN; + } + break; + } +} + +SECUREC_INLINE void SecUpdateOudiFlags(SecFormatAttr *attr, SecChar ch) +{ + /* Do not set digits here */ + switch (ch) { + case SECUREC_CHAR('i'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('d'): /* fall-through */ /* FALLTHRU */ + /* For signed decimal output */ + attr->flags |= SECUREC_FLAG_SIGNED; + /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('u'): + attr->radix = SECUREC_RADIX_DECIMAL; + attr->digits = g_itoaLowerDigits; + break; + case SECUREC_CHAR('o'): + /* For unsigned octal output */ + attr->radix = SECUREC_RADIX_OCTAL; + attr->digits = g_itoaLowerDigits; + if ((attr->flags & SECUREC_FLAG_ALTERNATE) != 0) { + /* Alternate form means force a leading 0 */ + attr->flags |= SECUREC_FLAG_FORCE_OCTAL; + } + break; + default: + /* Do nothing */ + break; + } +} + +#if SECUREC_ENABLE_SPRINTF_FLOAT +SECUREC_INLINE void SecFreeFloatBuffer(SecFloatAdapt *floatAdapt) +{ + if (floatAdapt->floatBuffer != NULL) { + SECUREC_FREE(floatAdapt->floatBuffer); + } + if (floatAdapt->allocatedFmtStr != NULL) { + SECUREC_FREE(floatAdapt->allocatedFmtStr); + } + floatAdapt->floatBuffer = NULL; + floatAdapt->allocatedFmtStr = NULL; + floatAdapt->fmtStr = NULL; + floatAdapt->bufferSize = 0; +} + +SECUREC_INLINE void SecSeekToFrontPercent(const SecChar **format) +{ + const SecChar *fmt = *format; + while (*fmt != SECUREC_CHAR('%')) { /* Must meet '%' */ + --fmt; + } + *format = fmt; +} + +/* Init float format, return 0 is OK */ +SECUREC_INLINE int SecInitFloatFmt(SecFloatAdapt *floatFmt, const SecChar *format) +{ + const SecChar *fmt = format - 2; /* Sub 2 to the position before 'f' or 'g' */ + int fmtStrLen; + int i; + + SecSeekToFrontPercent(&fmt); + /* Now fmt point to '%' */ + fmtStrLen = (int)(size_t)(format - fmt) + 1; /* With ending terminator */ + if (fmtStrLen > (int)sizeof(floatFmt->buffer)) { + /* When buffer is NOT enough, alloc a new buffer */ + floatFmt->allocatedFmtStr = (char *)SECUREC_MALLOC((size_t)((unsigned int)fmtStrLen)); + if (floatFmt->allocatedFmtStr == NULL) { + return -1; + } + floatFmt->fmtStr = floatFmt->allocatedFmtStr; + } else { + floatFmt->fmtStr = floatFmt->buffer; + floatFmt->allocatedFmtStr = NULL; /* Must set to NULL, later code free memory based on this identity */ + } + + for (i = 0; i < fmtStrLen - 1; ++i) { + /* Convert wchar to char */ + floatFmt->fmtStr[i] = (char)(fmt[i]); /* Copy the format string */ + } + floatFmt->fmtStr[fmtStrLen - 1] = '\0'; + + return 0; +} + +/* Init float buffer and format, return 0 is OK */ +SECUREC_INLINE int SecInitFloatBuffer(SecFloatAdapt *floatAdapt, const SecChar *format, SecFormatAttr *attr) +{ + floatAdapt->allocatedFmtStr = NULL; + floatAdapt->fmtStr = NULL; + floatAdapt->floatBuffer = NULL; + /* Compute the precision value */ + if (attr->precision < 0) { + attr->precision = SECUREC_FLOAT_DEFAULT_PRECISION; + } + /* + * Calc buffer size to store double value + * The maximum length of SECUREC_MAX_WIDTH_LEN is enough + */ + if ((attr->flags & SECUREC_FLAG_LONG_DOUBLE) != 0) { + if (attr->precision > (SECUREC_MAX_WIDTH_LEN - SECUREC_FLOAT_BUFSIZE_LB)) { + return -1; + } + /* Long double needs to meet the basic print length */ + floatAdapt->bufferSize = SECUREC_FLOAT_BUFSIZE_LB + attr->precision + SECUREC_FLOAT_BUF_EXT; + } else { + if (attr->precision > (SECUREC_MAX_WIDTH_LEN - SECUREC_FLOAT_BUFSIZE)) { + return -1; + } + /* Double needs to meet the basic print length */ + floatAdapt->bufferSize = SECUREC_FLOAT_BUFSIZE + attr->precision + SECUREC_FLOAT_BUF_EXT; + } + if (attr->fldWidth > floatAdapt->bufferSize) { + floatAdapt->bufferSize = attr->fldWidth + SECUREC_FLOAT_BUF_EXT; + } + + if (floatAdapt->bufferSize > SECUREC_BUFFER_SIZE) { + /* The current value of SECUREC_BUFFER_SIZE could not store the formatted float string */ + floatAdapt->floatBuffer = (char *)SECUREC_MALLOC(((size_t)(unsigned int)floatAdapt->bufferSize)); + if (floatAdapt->floatBuffer == NULL) { + return -1; + } + attr->text.str = floatAdapt->floatBuffer; + } else { + attr->text.str = attr->buffer.str; /* Output buffer for float string with default size */ + } + + if (SecInitFloatFmt(floatAdapt, format) != 0) { + if (floatAdapt->floatBuffer != NULL) { + SECUREC_FREE(floatAdapt->floatBuffer); + floatAdapt->floatBuffer = NULL; + } + return -1; + } + return 0; +} +#endif + +SECUREC_INLINE SecInt64 SecUpdateNegativeChar(SecFormatAttr *attr, char ch) +{ + SecInt64 num64 = ch; /* Sign extend */ + if (num64 >= 128) { /* 128 on some platform, char is always unsigned */ + unsigned char tmp = (unsigned char)(~((unsigned char)ch)); + num64 = tmp + 1; + attr->flags |= SECUREC_FLAG_NEGATIVE; + } + return num64; +} + +/* + * If the precision is not satisfied, zero is added before the string + */ +SECUREC_INLINE void SecNumberSatisfyPrecision(SecFormatAttr *attr) +{ + int precision; + if (attr->precision < 0) { + precision = 1; /* Default precision 1 */ + } else { +#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) + attr->flags &= ~SECUREC_FLAG_LEADZERO; +#else + if ((attr->flags & SECUREC_FLAG_POINTER) == 0) { + attr->flags &= ~SECUREC_FLAG_LEADZERO; + } +#endif + if (attr->precision > SECUREC_MAX_PRECISION) { + attr->precision = SECUREC_MAX_PRECISION; + } + precision = attr->precision; + } + while (attr->textLen < precision) { + --attr->text.str; + *(attr->text.str) = '0'; + ++attr->textLen; + } +} + +/* + * Add leading zero for %#o + */ +SECUREC_INLINE void SecNumberForceOctal(SecFormatAttr *attr) +{ + /* Force a leading zero if FORCEOCTAL flag set */ + if ((attr->flags & SECUREC_FLAG_FORCE_OCTAL) != 0 && + (attr->textLen == 0 || attr->text.str[0] != '0')) { + --attr->text.str; + *(attr->text.str) = '0'; + ++attr->textLen; + } +} + +SECUREC_INLINE void SecUpdateSignedNumberPrefix(SecFormatAttr *attr) +{ + if ((attr->flags & SECUREC_FLAG_SIGNED) == 0) { + return; + } + if ((attr->flags & SECUREC_FLAG_NEGATIVE) != 0) { + /* Prefix is '-' */ + attr->prefix[0] = SECUREC_CHAR('-'); + attr->prefixLen = 1; + return; + } + if ((attr->flags & SECUREC_FLAG_SIGN) != 0) { + /* Prefix is '+' */ + attr->prefix[0] = SECUREC_CHAR('+'); + attr->prefixLen = 1; + return; + } + if ((attr->flags & SECUREC_FLAG_SIGN_SPACE) != 0) { + /* Prefix is ' ' */ + attr->prefix[0] = SECUREC_CHAR(' '); + attr->prefixLen = 1; + return; + } + return; +} + +SECUREC_INLINE void SecNumberCompatZero(SecFormatAttr *attr) +{ +#if SECUREC_IN_KERNEL + if ((attr->flags & SECUREC_FLAG_POINTER) != 0) { + static char strNullPointer[SECUREC_NULL_STRING_SIZE] = "(null)"; + attr->text.str = strNullPointer; + attr->textLen = 6; /* Length of (null) is 6 */ + attr->flags &= ~SECUREC_FLAG_LEADZERO; + attr->prefixLen = 0; + if (attr->precision >= 0 && attr->precision < attr->textLen) { + attr->textLen = attr->precision; + } + } + if ((attr->flags & SECUREC_FLAG_POINTER) == 0 && attr->radix == SECUREC_RADIX_HEX && + (attr->flags & SECUREC_FLAG_ALTERNATE) != 0) { + /* Add 0x prefix for %x or %X, the prefix string has been set before */ + attr->prefixLen = SECUREC_PREFIX_LEN; + } +#elif defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && (!defined(SECUREC_ON_UNIX)) + if ((attr->flags & SECUREC_FLAG_POINTER) != 0) { + static char strNullPointer[SECUREC_NULL_STRING_SIZE] = "(nil)"; + attr->text.str = strNullPointer; + attr->textLen = 5; /* Length of (nil) is 5 */ + attr->flags &= ~SECUREC_FLAG_LEADZERO; + } +#elif defined(SECUREC_VXWORKS_PLATFORM) || defined(__hpux) + if ((attr->flags & SECUREC_FLAG_POINTER) != 0 && (attr->flags & SECUREC_FLAG_ALTERNATE) != 0) { + /* Add 0x prefix for %p, the prefix string has been set before */ + attr->prefixLen = SECUREC_PREFIX_LEN; + } +#endif + (void)attr; /* To clear e438 last value assigned not used , the compiler will optimize this code */ +} + +/* + * Formatting output core function + */ +SECUREC_INLINE int SecOutput(SecPrintfStream *stream, const SecChar *cFormat, va_list argList) +{ + const SecChar *format = cFormat; + int charsOut; /* Characters written */ + int noOutput = 0; /* Must be initialized or compiler alerts */ + SecFmtState state; + SecFormatAttr formatAttr; + + formatAttr.flags = 0; + formatAttr.textIsWide = 0; /* Flag for buffer contains wide chars */ + formatAttr.fldWidth = 0; + formatAttr.precision = 0; + formatAttr.dynWidth = 0; + formatAttr.dynPrecision = 0; + formatAttr.digits = g_itoaUpperDigits; + formatAttr.radix = SECUREC_RADIX_DECIMAL; + formatAttr.padding = 0; + formatAttr.textLen = 0; + formatAttr.text.str = NULL; + formatAttr.prefixLen = 0; + formatAttr.prefix[0] = SECUREC_CHAR('\0'); + formatAttr.prefix[1] = SECUREC_CHAR('\0'); + charsOut = 0; + state = STAT_NORMAL; /* Starting state */ + + /* Loop each format character */ + while (*format != SECUREC_CHAR('\0') && charsOut >= 0) { + SecFmtState lastState = state; + SecChar ch = *format; /* Currently read character */ + ++format; + state = SecDecodeState(ch, lastState); + switch (state) { + case STAT_NORMAL: + SecWriteChar(stream, ch, &charsOut); + continue; + case STAT_PERCENT: + /* Set default values */ + noOutput = 0; + formatAttr.prefixLen = 0; + formatAttr.textLen = 0; + formatAttr.flags = 0; + formatAttr.fldWidth = 0; + formatAttr.precision = -1; + formatAttr.textIsWide = 0; + formatAttr.dynWidth = 0; + formatAttr.dynPrecision = 0; + break; + case STAT_FLAG: + /* Set flag based on which flag character */ + SecDecodeFlags(ch, &formatAttr); + break; + case STAT_WIDTH: + /* Update width value */ + if (ch == SECUREC_CHAR('*')) { + /* get width from arg list */ + formatAttr.fldWidth = (int)va_arg(argList, int); + formatAttr.dynWidth = 1; + } + if (SecDecodeWidth(ch, &formatAttr, lastState) != 0) { + return -1; + } + break; + case STAT_DOT: + formatAttr.precision = 0; + break; + case STAT_PRECIS: + /* Update precision value */ + if (ch == SECUREC_CHAR('*')) { + /* Get precision from arg list */ + formatAttr.precision = (int)va_arg(argList, int); + formatAttr.dynPrecision = 1; + } + if (SecDecodePrecision(ch, &formatAttr) != 0) { + return -1; + } + break; + case STAT_SIZE: + /* Read a size specifier, set the formatAttr.flags based on it, and skip format to next character */ + if (SecDecodeSize(ch, &formatAttr, &format) != 0) { + /* Compatibility code for "%I" just print I */ + SecWriteChar(stream, ch, &charsOut); + state = STAT_NORMAL; + continue; + } + break; + case STAT_TYPE: + switch (ch) { + case SECUREC_CHAR('C'): /* Wide char */ + SecUpdateWcharFlags(&formatAttr); + /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('c'): { + unsigned int cValue = (unsigned int)va_arg(argList, int); + SecDecodeTypeC(&formatAttr, cValue); + break; + } + case SECUREC_CHAR('S'): /* Wide char string */ + SecUpdateWstringFlags(&formatAttr); + /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('s'): { + char *argPtr = (char *)va_arg(argList, char *); + SecDecodeTypeS(&formatAttr, argPtr); + break; + } + case SECUREC_CHAR('G'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('g'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('E'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('F'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('e'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('f'): { +#if SECUREC_ENABLE_SPRINTF_FLOAT + /* Add following code to call system sprintf API for float number */ + SecFloatAdapt floatAdapt; + noOutput = 1; /* It's no more data needs to be written */ + + /* Now format is pointer to the next character of 'f' */ + if (SecInitFloatBuffer(&floatAdapt, format, &formatAttr) != 0) { + break; + } + + if ((formatAttr.flags & SECUREC_FLAG_LONG_DOUBLE) != 0) { +#if defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && SECUREC_ENABLE_SPRINTF_LONG_DOUBLE + long double tmp = (long double)va_arg(argList, long double); + SecFormatLongDouble(&formatAttr, &floatAdapt, tmp); +#else + double tmp = (double)va_arg(argList, double); + SecFormatDouble(&formatAttr, &floatAdapt, tmp); +#endif + } else { + double tmp = (double)va_arg(argList, double); + SecFormatDouble(&formatAttr, &floatAdapt, tmp); + } + + /* Only need write formatted float string */ + SecWriteFloatText(stream, &formatAttr, &charsOut); + SecFreeFloatBuffer(&floatAdapt); + break; +#else + return -1; +#endif + } + case SECUREC_CHAR('X'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('p'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('x'): /* fall-through */ /* FALLTHRU */ + SecUpdateXpxFlags(&formatAttr, ch); + /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('i'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('d'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('u'): /* fall-through */ /* FALLTHRU */ + case SECUREC_CHAR('o'): { + SecInt64 num64; + SecUpdateOudiFlags(&formatAttr, ch); + /* Read argument into variable num64. Be careful, depend on the order of judgment */ + if ((formatAttr.flags & SECUREC_FLAG_I64) != 0 || + (formatAttr.flags & SECUREC_FLAG_LONGLONG) != 0) { + num64 = (SecInt64)va_arg(argList, SecInt64); /* Maximum Bit Width sign bit unchanged */ + } else if ((formatAttr.flags & SECUREC_FLAG_LONG) != 0) { + num64 = SECUREC_GET_LONG_FROM_ARG(formatAttr); + } else if ((formatAttr.flags & SECUREC_FLAG_CHAR) != 0) { + num64 = SECUREC_GET_CHAR_FROM_ARG(formatAttr); + } else if ((formatAttr.flags & SECUREC_FLAG_SHORT) != 0) { + num64 = SECUREC_GET_SHORT_FROM_ARG(formatAttr); +#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT + } else if ((formatAttr.flags & SECUREC_FLAG_PTRDIFF) != 0) { + num64 = (ptrdiff_t)va_arg(argList, ptrdiff_t); /* Sign extend */ + } else if ((formatAttr.flags & SECUREC_FLAG_SIZE) != 0) { + num64 = SECUREC_GET_SIZE_FROM_ARG(formatAttr); + } else if ((formatAttr.flags & SECUREC_FLAG_INTMAX) != 0) { + num64 = (SecInt64)va_arg(argList, SecInt64); +#endif + } else { + num64 = SECUREC_GET_INT_FROM_ARG(formatAttr); + } + + /* The order of the following calls must be correct */ + SecNumberToBuffer(&formatAttr, num64); + SecNumberSatisfyPrecision(&formatAttr); + SecNumberForceOctal(&formatAttr); + SecUpdateSignedNumberPrefix(&formatAttr); + if (num64 == 0) { + SecNumberCompatZero(&formatAttr); + } + break; + } + default: + /* Do nothing */ + break; + } + + if (noOutput == 0) { + /* Calculate amount of padding */ + formatAttr.padding = (formatAttr.fldWidth - formatAttr.textLen) - formatAttr.prefixLen; + + /* Put out the padding, prefix, and text, in the correct order */ + SecWriteLeftPadding(stream, &formatAttr, &charsOut); + SecWritePrefix(stream, &formatAttr, &charsOut); + SecWriteLeadingZero(stream, &formatAttr, &charsOut); + SecWriteText(stream, &formatAttr, &charsOut); + SecWriteRightPadding(stream, &formatAttr, &charsOut); + } + break; + case STAT_INVALID: /* fall-through */ /* FALLTHRU */ + default: + return -1; /* Input format is wrong(STAT_INVALID), directly return */ + } + } + + if (state != STAT_NORMAL && state != STAT_TYPE) { + return -1; + } + + return charsOut; /* The number of characters written */ +} + +/* + * Output one zero character zero into the SecPrintfStream structure + * If there is not enough space, make sure f->count is less than 0 + */ +SECUREC_INLINE int SecPutZeroChar(SecPrintfStream *stream) +{ + --stream->count; + if (stream->count >= 0) { + *(stream->cur) = SECUREC_CHAR('\0'); + ++stream->cur; + return 0; + } + return -1; +} + +/* + * Multi character formatted output implementation + */ +#ifdef SECUREC_FOR_WCHAR +int SecVswprintfImpl(wchar_t *string, size_t count, const wchar_t *format, va_list argList) +#else +int SecVsnprintfImpl(char *string, size_t count, const char *format, va_list argList) +#endif +{ + SecPrintfStream stream; + int retVal; + + stream.count = (int)count; /* The count include \0 character, must be greater than zero */ + stream.cur = string; + + retVal = SecOutput(&stream, format, argList); + if (retVal >= 0) { + if (SecPutZeroChar(&stream) == 0) { + return retVal; + } + } + if (stream.count < 0) { + /* The buffer was too small, then truncate */ + string[count - 1] = SECUREC_CHAR('\0'); + return SECUREC_PRINTF_TRUNCATE; + } + string[0] = SECUREC_CHAR('\0'); /* Empty the dest string */ + return -1; +} +#endif /* OUTPUT_INL_2B263E9C_43D8_44BB_B17A_6D2033DECEE5 */ + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/scanf_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/scanf_s.c new file mode 100644 index 00000000..fa5470b8 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/scanf_s.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: scanf_s function + * Create: 2014-02-25 + */ + +#include "securec.h" + +/* + * + * The scanf_s function is equivalent to fscanf_s with the argument stdin interposed before the arguments to scanf_s + * The scanf_s function reads data from the standard input stream stdin and + * writes the data into the location that's given by argument. Each argument + * must be a pointer to a variable of a type that corresponds to a type specifier + * in format. If copying occurs between strings that overlap, the behavior is + * undefined. + * + * + * format Format control string. + * ... Optional arguments. + * + * + * ... The converted value stored in user assigned address + * + * + * Returns the number of fields successfully converted and assigned; + * the return value does not include fields that were read but not assigned. + * A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int scanf_s(const char *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vscanf_s(format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/secinput.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/secinput.h new file mode 100644 index 00000000..176ee05d --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/secinput.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: Define macro, data struct, and declare function prototype, + * which is used by input.inl, secureinput_a.c and secureinput_w.c. + * Create: 2014-02-25 + */ + +#ifndef SEC_INPUT_H_E950DA2C_902F_4B15_BECD_948E99090D9C +#define SEC_INPUT_H_E950DA2C_902F_4B15_BECD_948E99090D9C +#include "securecutil.h" + +#define SECUREC_SCANF_EINVAL (-1) +#define SECUREC_SCANF_ERROR_PARA (-2) + +/* For internal stream flag */ +#define SECUREC_MEM_STR_FLAG 0x01U +#define SECUREC_FILE_STREAM_FLAG 0x02U +#define SECUREC_PIPE_STREAM_FLAG 0x04U +#define SECUREC_LOAD_FILE_TO_MEM_FLAG 0x08U + +#define SECUREC_UCS_BOM_HEADER_SIZE 2U +#define SECUREC_UCS_BOM_HEADER_BE_1ST 0xfeU +#define SECUREC_UCS_BOM_HEADER_BE_2ST 0xffU +#define SECUREC_UCS_BOM_HEADER_LE_1ST 0xffU +#define SECUREC_UCS_BOM_HEADER_LE_2ST 0xfeU +#define SECUREC_UTF8_BOM_HEADER_SIZE 3U +#define SECUREC_UTF8_BOM_HEADER_1ST 0xefU +#define SECUREC_UTF8_BOM_HEADER_2ND 0xbbU +#define SECUREC_UTF8_BOM_HEADER_3RD 0xbfU +#define SECUREC_UTF8_LEAD_1ST 0xe0U +#define SECUREC_UTF8_LEAD_2ND 0x80U + +#define SECUREC_BEGIN_WITH_UCS_BOM(s, len) ((len) == SECUREC_UCS_BOM_HEADER_SIZE && \ + (((unsigned char)((s)[0]) == SECUREC_UCS_BOM_HEADER_LE_1ST && \ + (unsigned char)((s)[1]) == SECUREC_UCS_BOM_HEADER_LE_2ST) || \ + ((unsigned char)((s)[0]) == SECUREC_UCS_BOM_HEADER_BE_1ST && \ + (unsigned char)((s)[1]) == SECUREC_UCS_BOM_HEADER_BE_2ST))) + +#define SECUREC_BEGIN_WITH_UTF8_BOM(s, len) ((len) == SECUREC_UTF8_BOM_HEADER_SIZE && \ + (unsigned char)((s)[0]) == SECUREC_UTF8_BOM_HEADER_1ST && \ + (unsigned char)((s)[1]) == SECUREC_UTF8_BOM_HEADER_2ND && \ + (unsigned char)((s)[2]) == SECUREC_UTF8_BOM_HEADER_3RD) + +#ifdef SECUREC_FOR_WCHAR +#define SECUREC_BOM_HEADER_SIZE SECUREC_UCS_BOM_HEADER_SIZE +#define SECUREC_BEGIN_WITH_BOM(s, len) SECUREC_BEGIN_WITH_UCS_BOM((s), (len)) +#else +#define SECUREC_BOM_HEADER_SIZE SECUREC_UTF8_BOM_HEADER_SIZE +#define SECUREC_BEGIN_WITH_BOM(s, len) SECUREC_BEGIN_WITH_UTF8_BOM((s), (len)) +#endif + +typedef struct { + unsigned int flag; /* Mark the properties of input stream */ + char *base; /* The pointer to the header of buffered string */ + const char *cur; /* The pointer to next read position */ + size_t count; /* The size of buffered string in bytes */ +#if SECUREC_ENABLE_SCANF_FILE + FILE *pf; /* The file pointer */ + size_t fileRealRead; + long oriFilePos; /* The original position of file offset when fscanf is called */ +#endif +} SecFileStream; + +#if SECUREC_ENABLE_SCANF_FILE +#define SECUREC_FILE_STREAM_INIT_FILE(stream, fp) do { \ + (stream)->pf = (fp); \ + (stream)->fileRealRead = 0; \ + (stream)->oriFilePos = 0; \ +} SECUREC_WHILE_ZERO +#else +/* Disable file */ +#define SECUREC_FILE_STREAM_INIT_FILE(stream, fp) +#endif + +/* This initialization for eliminating redundant initialization. */ +#define SECUREC_FILE_STREAM_FROM_STRING(stream, buf, cnt) do { \ + (stream)->flag = SECUREC_MEM_STR_FLAG; \ + (stream)->base = NULL; \ + (stream)->cur = (buf); \ + (stream)->count = (cnt); \ + SECUREC_FILE_STREAM_INIT_FILE((stream), NULL); \ +} SECUREC_WHILE_ZERO + +/* This initialization for eliminating redundant initialization. */ +#define SECUREC_FILE_STREAM_FROM_FILE(stream, fp) do { \ + (stream)->flag = SECUREC_FILE_STREAM_FLAG; \ + (stream)->base = NULL; \ + (stream)->cur = NULL; \ + (stream)->count = 0; \ + SECUREC_FILE_STREAM_INIT_FILE((stream), (fp)); \ +} SECUREC_WHILE_ZERO + +/* This initialization for eliminating redundant initialization. */ +#define SECUREC_FILE_STREAM_FROM_STDIN(stream) do { \ + (stream)->flag = SECUREC_PIPE_STREAM_FLAG; \ + (stream)->base = NULL; \ + (stream)->cur = NULL; \ + (stream)->count = 0; \ + SECUREC_FILE_STREAM_INIT_FILE((stream), SECUREC_STREAM_STDIN); \ +} SECUREC_WHILE_ZERO + +#ifdef __cplusplus +extern "C" { +#endif +int SecInputS(SecFileStream *stream, const char *cFormat, va_list argList); +void SecClearDestBuf(const char *buffer, const char *format, va_list argList); +#ifdef SECUREC_FOR_WCHAR +int SecInputSW(SecFileStream *stream, const wchar_t *cFormat, va_list argList); +void SecClearDestBufW(const wchar_t *buffer, const wchar_t *format, va_list argList); +#endif + +/* 20150105 For software and hardware decoupling,such as UMG */ +#ifdef SECUREC_SYSAPI4VXWORKS +#ifdef feof +#undef feof +#endif +extern int feof(FILE *stream); +#endif + +#if defined(SECUREC_SYSAPI4VXWORKS) || defined(SECUREC_CTYPE_MACRO_ADAPT) +#ifndef isspace +#define isspace(c) (((c) == ' ') || ((c) == '\t') || ((c) == '\r') || ((c) == '\n')) +#endif +#ifndef iswspace +#define iswspace(c) (((c) == L' ') || ((c) == L'\t') || ((c) == L'\r') || ((c) == L'\n')) +#endif +#ifndef isascii +#define isascii(c) (((unsigned char)(c)) <= 0x7f) +#endif +#ifndef isupper +#define isupper(c) ((c) >= 'A' && (c) <= 'Z') +#endif +#ifndef islower +#define islower(c) ((c) >= 'a' && (c) <= 'z') +#endif +#ifndef isalpha +#define isalpha(c) (isupper(c) || (islower(c))) +#endif +#ifndef isdigit +#define isdigit(c) ((c) >= '0' && (c) <= '9') +#endif +#ifndef isxupper +#define isxupper(c) ((c) >= 'A' && (c) <= 'F') +#endif +#ifndef isxlower +#define isxlower(c) ((c) >= 'a' && (c) <= 'f') +#endif +#ifndef isxdigit +#define isxdigit(c) (isdigit(c) || isxupper(c) || isxlower(c)) +#endif +#endif + +#ifdef __cplusplus +} +#endif +/* Reserved file operation macro interface, s is FILE *, i is fileno zero. */ +#ifndef SECUREC_LOCK_FILE +#define SECUREC_LOCK_FILE(s) +#endif + +#ifndef SECUREC_UNLOCK_FILE +#define SECUREC_UNLOCK_FILE(s) +#endif + +#ifndef SECUREC_LOCK_STDIN +#define SECUREC_LOCK_STDIN(i, s) +#endif + +#ifndef SECUREC_UNLOCK_STDIN +#define SECUREC_UNLOCK_STDIN(i, s) +#endif +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/securecutil.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/securecutil.c new file mode 100644 index 00000000..0053a72c --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/securecutil.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: Provides internal functions used by this library, such as memory + * copy and memory move. Besides, include some helper function for + * printf family API, such as SecVsnprintfImpl + * Create: 2014-02-25 + */ + +/* Avoid duplicate header files,not include securecutil.h */ +#include "securecutil.h" + +#if defined(ANDROID) && !defined(SECUREC_CLOSE_ANDROID_HANDLE) && (SECUREC_HAVE_WCTOMB || SECUREC_HAVE_MBTOWC) +#include +#if SECUREC_HAVE_WCTOMB +/* + * Convert wide characters to narrow multi-bytes + */ +int wctomb(char *s, wchar_t wc) +{ + return (int)wcrtomb(s, wc, NULL); +} +#endif + +#if SECUREC_HAVE_MBTOWC +/* + * Converting narrow multi-byte characters to wide characters + * mbrtowc returns -1 or -2 upon failure, unlike mbtowc, which only returns -1 + * When the return value is less than zero, we treat it as a failure + */ +int mbtowc(wchar_t *pwc, const char *s, size_t n) +{ + return (int)mbrtowc(pwc, s, n, NULL); +} +#endif +#endif + +/* The V100R001C01 version num is 0x5 (High 8 bits) */ +#define SECUREC_C_VERSION 0x500U +#define SECUREC_SPC_VERSION 0x10U +#define SECUREC_VERSION_STR "1.1.16" + +/* + * Get version string and version number. + * The rules for version number are as follows: + * 1) SPC verNumber<->verStr like: + * 0x201<->C01 + * 0x202<->C01SPC001 Redefine numbers after this version + * 0x502<->C01SPC002 + * 0x503<->C01SPC003 + * ... + * 0X50a<->SPC010 + * 0X50b<->SPC011 + * ... + * 0x700<->C02 + * 0x701<->C01SPC001 + * 0x702<->C02SPC002 + * ... + * 2) CP verNumber<->verStr like: + * 0X601<->CP0001 + * 0X602<->CP0002 + * ... + */ +const char *GetHwSecureCVersion(unsigned short *verNumber) +{ + if (verNumber != NULL) { + *verNumber = (unsigned short)(SECUREC_C_VERSION | SECUREC_SPC_VERSION); + } + return SECUREC_VERSION_STR; +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(GetHwSecureCVersion); +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/securecutil.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/securecutil.h new file mode 100644 index 00000000..7e3bd691 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/securecutil.h @@ -0,0 +1,574 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: Define macro, data struct, and declare internal used function prototype, + * which is used by secure functions. + * Create: 2014-02-25 + */ + +#ifndef SECURECUTIL_H_46C86578_F8FF_4E49_8E64_9B175241761F +#define SECURECUTIL_H_46C86578_F8FF_4E49_8E64_9B175241761F +#include "securec.h" + +#if (defined(_MSC_VER)) && (_MSC_VER >= 1400) +/* Shield compilation alerts using discarded functions and Constant expression to maximize code compatibility */ +#define SECUREC_MASK_MSVC_CRT_WARNING __pragma(warning(push)) \ + __pragma(warning(disable : 4996 4127)) +#define SECUREC_END_MASK_MSVC_CRT_WARNING __pragma(warning(pop)) +#else +#define SECUREC_MASK_MSVC_CRT_WARNING +#define SECUREC_END_MASK_MSVC_CRT_WARNING +#endif +#define SECUREC_WHILE_ZERO SECUREC_MASK_MSVC_CRT_WARNING while (0) SECUREC_END_MASK_MSVC_CRT_WARNING + +/* Automatically identify the platform that supports strnlen function, and use this function to improve performance */ +#ifndef SECUREC_HAVE_STRNLEN +#if (defined(_XOPEN_SOURCE) && _XOPEN_SOURCE >= 700) || (defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE >= 200809L) +#if SECUREC_IN_KERNEL +#define SECUREC_HAVE_STRNLEN 0 +#else +#if defined(__GLIBC__) && __GLIBC__ >= 2 && defined(__GLIBC_MINOR__) && __GLIBC_MINOR__ >= 10 +#define SECUREC_HAVE_STRNLEN 1 +#else +#define SECUREC_HAVE_STRNLEN 0 +#endif +#endif +#else +#define SECUREC_HAVE_STRNLEN 0 +#endif +#endif + +#if SECUREC_IN_KERNEL +/* In kernel disable functions */ +#ifndef SECUREC_ENABLE_SCANF_FILE +#define SECUREC_ENABLE_SCANF_FILE 0 +#endif +#ifndef SECUREC_ENABLE_SCANF_FLOAT +#define SECUREC_ENABLE_SCANF_FLOAT 0 +#endif +#ifndef SECUREC_ENABLE_SPRINTF_FLOAT +#define SECUREC_ENABLE_SPRINTF_FLOAT 0 +#endif +#ifndef SECUREC_HAVE_MBTOWC +#define SECUREC_HAVE_MBTOWC 0 +#endif +#ifndef SECUREC_HAVE_WCTOMB +#define SECUREC_HAVE_WCTOMB 0 +#endif +#ifndef SECUREC_HAVE_WCHART +#define SECUREC_HAVE_WCHART 0 +#endif +#else /* Not in kernel */ +/* Systems that do not support file, can define this macro to 0. */ +#ifndef SECUREC_ENABLE_SCANF_FILE +#define SECUREC_ENABLE_SCANF_FILE 1 +#endif +#ifndef SECUREC_ENABLE_SCANF_FLOAT +#define SECUREC_ENABLE_SCANF_FLOAT 1 +#endif +/* Systems that do not support float, can define this macro to 0. */ +#ifndef SECUREC_ENABLE_SPRINTF_FLOAT +#define SECUREC_ENABLE_SPRINTF_FLOAT 1 +#endif +#ifndef SECUREC_HAVE_MBTOWC +#define SECUREC_HAVE_MBTOWC 1 +#endif +#ifndef SECUREC_HAVE_WCTOMB +#define SECUREC_HAVE_WCTOMB 1 +#endif +#ifndef SECUREC_HAVE_WCHART +#define SECUREC_HAVE_WCHART 1 +#endif +#endif + +#ifndef SECUREC_ENABLE_INLINE +#define SECUREC_ENABLE_INLINE 0 +#endif + +#ifndef SECUREC_INLINE +#if SECUREC_ENABLE_INLINE +#define SECUREC_INLINE static inline +#else +#define SECUREC_INLINE static +#endif +#endif + +#ifndef SECUREC_WARP_OUTPUT +#if SECUREC_IN_KERNEL +#define SECUREC_WARP_OUTPUT 1 +#else +#define SECUREC_WARP_OUTPUT 0 +#endif +#endif + +#ifndef SECUREC_STREAM_STDIN +#define SECUREC_STREAM_STDIN stdin +#endif + +#define SECUREC_MUL_SIXTEEN(x) ((x) << 4U) +#define SECUREC_MUL_EIGHT(x) ((x) << 3U) +#define SECUREC_MUL_TEN(x) ((((x) << 2U) + (x)) << 1U) +/* Limited format input and output width, use signed integer */ +#define SECUREC_MAX_WIDTH_LEN_DIV_TEN 21474836 +#define SECUREC_MAX_WIDTH_LEN (SECUREC_MAX_WIDTH_LEN_DIV_TEN * 10) +/* Is the x multiplied by 10 greater than */ +#define SECUREC_MUL_TEN_ADD_BEYOND_MAX(x) (((x) > SECUREC_MAX_WIDTH_LEN_DIV_TEN)) + +#define SECUREC_FLOAT_BUFSIZE (309 + 40) /* Max length of double value */ +#define SECUREC_FLOAT_BUFSIZE_LB (4932 + 40) /* Max length of long double value */ +#define SECUREC_FLOAT_DEFAULT_PRECISION 6 + +/* This macro does not handle pointer equality or integer overflow */ +#define SECUREC_MEMORY_NO_OVERLAP(dest, src, count) \ + (((src) < (dest) && ((const char *)(src) + (count)) <= (char *)(dest)) || \ + ((dest) < (src) && ((char *)(dest) + (count)) <= (const char *)(src))) + +#define SECUREC_MEMORY_IS_OVERLAP(dest, src, count) \ + (((src) < (dest) && ((const char *)(src) + (count)) > (char *)(dest)) || \ + ((dest) < (src) && ((char *)(dest) + (count)) > (const char *)(src))) + +/* + * Check whether the strings overlap, len is the length of the string not include terminator + * Length is related to data type char or wchar , do not force conversion of types + */ +#define SECUREC_STRING_NO_OVERLAP(dest, src, len) \ + (((src) < (dest) && ((src) + (len)) < (dest)) || \ + ((dest) < (src) && ((dest) + (len)) < (src))) + +/* + * Check whether the strings overlap for strcpy wcscpy function, dest len and src Len are not include terminator + * Length is related to data type char or wchar , do not force conversion of types + */ +#define SECUREC_STRING_IS_OVERLAP(dest, src, len) \ + (((src) < (dest) && ((src) + (len)) >= (dest)) || \ + ((dest) < (src) && ((dest) + (len)) >= (src))) + +/* + * Check whether the strings overlap for strcat wcscat function, dest len and src Len are not include terminator + * Length is related to data type char or wchar , do not force conversion of types + */ +#define SECUREC_CAT_STRING_IS_OVERLAP(dest, destLen, src, srcLen) \ + (((dest) < (src) && ((dest) + (destLen) + (srcLen)) >= (src)) || \ + ((src) < (dest) && ((src) + (srcLen)) >= (dest))) + +#if SECUREC_HAVE_STRNLEN +#define SECUREC_CALC_STR_LEN(str, maxLen, outLen) do { \ + *(outLen) = strnlen((str), (maxLen)); \ +} SECUREC_WHILE_ZERO +#define SECUREC_CALC_STR_LEN_OPT(str, maxLen, outLen) do { \ + if ((maxLen) > 8) { \ + /* Optimization or len less then 8 */ \ + if (*((str) + 0) == '\0') { \ + *(outLen) = 0; \ + } else if (*((str) + 1) == '\0') { \ + *(outLen) = 1; \ + } else if (*((str) + 2) == '\0') { \ + *(outLen) = 2; \ + } else if (*((str) + 3) == '\0') { \ + *(outLen) = 3; \ + } else if (*((str) + 4) == '\0') { \ + *(outLen) = 4; \ + } else if (*((str) + 5) == '\0') { \ + *(outLen) = 5; \ + } else if (*((str) + 6) == '\0') { \ + *(outLen) = 6; \ + } else if (*((str) + 7) == '\0') { \ + *(outLen) = 7; \ + } else if (*((str) + 8) == '\0') { \ + /* Optimization with a length of 8 */ \ + *(outLen) = 8; \ + } else { \ + /* The offset is 8 because the performance of 8 byte alignment is high */ \ + *(outLen) = 8 + strnlen((str) + 8, (maxLen) - 8); \ + } \ + } else { \ + SECUREC_CALC_STR_LEN((str), (maxLen), (outLen)); \ + } \ +} SECUREC_WHILE_ZERO +#else +#define SECUREC_CALC_STR_LEN(str, maxLen, outLen) do { \ + const char *strEnd_ = (const char *)(str); \ + size_t availableSize_ = (size_t)(maxLen); \ + while (availableSize_ > 0 && *strEnd_ != '\0') { \ + --availableSize_; \ + ++strEnd_; \ + } \ + *(outLen) = (size_t)(strEnd_ - (str)); \ +} SECUREC_WHILE_ZERO +#define SECUREC_CALC_STR_LEN_OPT SECUREC_CALC_STR_LEN +#endif + +#define SECUREC_CALC_WSTR_LEN(str, maxLen, outLen) do { \ + const wchar_t *strEnd_ = (const wchar_t *)(str); \ + size_t len_ = 0; \ + while (len_ < (maxLen) && *strEnd_ != L'\0') { \ + ++len_; \ + ++strEnd_; \ + } \ + *(outLen) = len_; \ +} SECUREC_WHILE_ZERO + +/* + * Performance optimization, product may disable inline function. + * Using function pointer for MEMSET to prevent compiler optimization when cleaning up memory. + */ +#ifdef SECUREC_USE_ASM +#define SECUREC_MEMSET_FUNC_OPT memset_opt +#define SECUREC_MEMCPY_FUNC_OPT memcpy_opt +#else +#define SECUREC_MEMSET_FUNC_OPT memset +#define SECUREC_MEMCPY_FUNC_OPT memcpy +#endif + +#define SECUREC_MEMCPY_WARP_OPT(dest, src, count) (void)SECUREC_MEMCPY_FUNC_OPT((dest), (src), (count)) + +#ifndef SECUREC_MEMSET_BARRIER +#if defined(__GNUC__) +/* Can be turned off for scenarios that do not use memory barrier */ +#define SECUREC_MEMSET_BARRIER 1 +#else +#define SECUREC_MEMSET_BARRIER 0 +#endif +#endif + +#ifndef SECUREC_MEMSET_INDIRECT_USE +/* Can be turned off for scenarios that do not allow pointer calls */ +#define SECUREC_MEMSET_INDIRECT_USE 1 +#endif + +#if SECUREC_MEMSET_BARRIER +#define SECUREC_MEMORY_BARRIER(dest) __asm__ __volatile__("": : "r"(dest) : "memory") +#else +#define SECUREC_MEMORY_BARRIER(dest) +#endif + +#if SECUREC_MEMSET_BARRIER +#define SECUREC_MEMSET_PREVENT_DSE(dest, value, count) do { \ + (void)SECUREC_MEMSET_FUNC_OPT(dest, value, count); \ + SECUREC_MEMORY_BARRIER(dest); \ +} SECUREC_WHILE_ZERO +#elif SECUREC_MEMSET_INDIRECT_USE +#define SECUREC_MEMSET_PREVENT_DSE(dest, value, count) do { \ + void *(* const volatile fn_)(void *s_, int c_, size_t n_) = SECUREC_MEMSET_FUNC_OPT; \ + (void)(*fn_)((dest), (value), (count)); \ +} SECUREC_WHILE_ZERO +#else +#define SECUREC_MEMSET_PREVENT_DSE(dest, value, count) (void)SECUREC_MEMSET_FUNC_OPT((dest), (value), (count)) +#endif + +#ifdef SECUREC_FORMAT_OUTPUT_INPUT +#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) || defined(__ARMCC_VERSION) +typedef __int64 SecInt64; +typedef unsigned __int64 SecUnsignedInt64; +#if defined(__ARMCC_VERSION) +typedef unsigned int SecUnsignedInt32; +#else +typedef unsigned __int32 SecUnsignedInt32; +#endif +#else +typedef unsigned int SecUnsignedInt32; +typedef long long SecInt64; +typedef unsigned long long SecUnsignedInt64; +#endif + +#ifdef SECUREC_FOR_WCHAR +#if defined(SECUREC_VXWORKS_PLATFORM) && !defined(__WINT_TYPE__) +typedef wchar_t wint_t; +#endif +#ifndef WEOF +#define WEOF ((wchar_t)(-1)) +#endif +#define SECUREC_CHAR(x) L ## x +typedef wchar_t SecChar; +typedef wchar_t SecUnsignedChar; +typedef wint_t SecInt; +typedef wint_t SecUnsignedInt; +#else /* no SECUREC_FOR_WCHAR */ +#define SECUREC_CHAR(x) (x) +typedef char SecChar; +typedef unsigned char SecUnsignedChar; +typedef int SecInt; +typedef unsigned int SecUnsignedInt; +#endif +#endif + +/* + * Determine whether the address is 8-byte aligned + * Some systems do not have uintptr_t type, so use NULL to clear tool alarm 507 + */ +#define SECUREC_ADDR_ALIGNED_8(addr) ((((size_t)(addr)) & 7U) == 0) /* Use 7 to check aligned 8 */ + +/* + * If you define the memory allocation function, you need to define the function prototype. + * You can define this macro as a header file. + */ +#if defined(SECUREC_MALLOC_PROTOTYPE) +SECUREC_MALLOC_PROTOTYPE +#endif + +#ifndef SECUREC_MALLOC +#define SECUREC_MALLOC(x) malloc((size_t)(x)) +#endif + +#ifndef SECUREC_FREE +#define SECUREC_FREE(x) free((void *)(x)) +#endif + +/* Improve performance with struct assignment, buf1 is not defined to avoid tool false positive */ +#define SECUREC_COPY_VALUE_BY_STRUCT(dest, src, n) do { \ + *(SecStrBuf##n *)(void *)(dest) = *(const SecStrBuf##n *)(const void *)(src); \ +} SECUREC_WHILE_ZERO + +typedef struct { + unsigned char buf[2]; /* Performance optimization code structure assignment length 2 bytes */ +} SecStrBuf2; +typedef struct { + unsigned char buf[3]; /* Performance optimization code structure assignment length 3 bytes */ +} SecStrBuf3; +typedef struct { + unsigned char buf[4]; /* Performance optimization code structure assignment length 4 bytes */ +} SecStrBuf4; +typedef struct { + unsigned char buf[5]; /* Performance optimization code structure assignment length 5 bytes */ +} SecStrBuf5; +typedef struct { + unsigned char buf[6]; /* Performance optimization code structure assignment length 6 bytes */ +} SecStrBuf6; +typedef struct { + unsigned char buf[7]; /* Performance optimization code structure assignment length 7 bytes */ +} SecStrBuf7; +typedef struct { + unsigned char buf[8]; /* Performance optimization code structure assignment length 8 bytes */ +} SecStrBuf8; +typedef struct { + unsigned char buf[9]; /* Performance optimization code structure assignment length 9 bytes */ +} SecStrBuf9; +typedef struct { + unsigned char buf[10]; /* Performance optimization code structure assignment length 10 bytes */ +} SecStrBuf10; +typedef struct { + unsigned char buf[11]; /* Performance optimization code structure assignment length 11 bytes */ +} SecStrBuf11; +typedef struct { + unsigned char buf[12]; /* Performance optimization code structure assignment length 12 bytes */ +} SecStrBuf12; +typedef struct { + unsigned char buf[13]; /* Performance optimization code structure assignment length 13 bytes */ +} SecStrBuf13; +typedef struct { + unsigned char buf[14]; /* Performance optimization code structure assignment length 14 bytes */ +} SecStrBuf14; +typedef struct { + unsigned char buf[15]; /* Performance optimization code structure assignment length 15 bytes */ +} SecStrBuf15; +typedef struct { + unsigned char buf[16]; /* Performance optimization code structure assignment length 16 bytes */ +} SecStrBuf16; +typedef struct { + unsigned char buf[17]; /* Performance optimization code structure assignment length 17 bytes */ +} SecStrBuf17; +typedef struct { + unsigned char buf[18]; /* Performance optimization code structure assignment length 18 bytes */ +} SecStrBuf18; +typedef struct { + unsigned char buf[19]; /* Performance optimization code structure assignment length 19 bytes */ +} SecStrBuf19; +typedef struct { + unsigned char buf[20]; /* Performance optimization code structure assignment length 20 bytes */ +} SecStrBuf20; +typedef struct { + unsigned char buf[21]; /* Performance optimization code structure assignment length 21 bytes */ +} SecStrBuf21; +typedef struct { + unsigned char buf[22]; /* Performance optimization code structure assignment length 22 bytes */ +} SecStrBuf22; +typedef struct { + unsigned char buf[23]; /* Performance optimization code structure assignment length 23 bytes */ +} SecStrBuf23; +typedef struct { + unsigned char buf[24]; /* Performance optimization code structure assignment length 24 bytes */ +} SecStrBuf24; +typedef struct { + unsigned char buf[25]; /* Performance optimization code structure assignment length 25 bytes */ +} SecStrBuf25; +typedef struct { + unsigned char buf[26]; /* Performance optimization code structure assignment length 26 bytes */ +} SecStrBuf26; +typedef struct { + unsigned char buf[27]; /* Performance optimization code structure assignment length 27 bytes */ +} SecStrBuf27; +typedef struct { + unsigned char buf[28]; /* Performance optimization code structure assignment length 28 bytes */ +} SecStrBuf28; +typedef struct { + unsigned char buf[29]; /* Performance optimization code structure assignment length 29 bytes */ +} SecStrBuf29; +typedef struct { + unsigned char buf[30]; /* Performance optimization code structure assignment length 30 bytes */ +} SecStrBuf30; +typedef struct { + unsigned char buf[31]; /* Performance optimization code structure assignment length 31 bytes */ +} SecStrBuf31; +typedef struct { + unsigned char buf[32]; /* Performance optimization code structure assignment length 32 bytes */ +} SecStrBuf32; +typedef struct { + unsigned char buf[33]; /* Performance optimization code structure assignment length 33 bytes */ +} SecStrBuf33; +typedef struct { + unsigned char buf[34]; /* Performance optimization code structure assignment length 34 bytes */ +} SecStrBuf34; +typedef struct { + unsigned char buf[35]; /* Performance optimization code structure assignment length 35 bytes */ +} SecStrBuf35; +typedef struct { + unsigned char buf[36]; /* Performance optimization code structure assignment length 36 bytes */ +} SecStrBuf36; +typedef struct { + unsigned char buf[37]; /* Performance optimization code structure assignment length 37 bytes */ +} SecStrBuf37; +typedef struct { + unsigned char buf[38]; /* Performance optimization code structure assignment length 38 bytes */ +} SecStrBuf38; +typedef struct { + unsigned char buf[39]; /* Performance optimization code structure assignment length 39 bytes */ +} SecStrBuf39; +typedef struct { + unsigned char buf[40]; /* Performance optimization code structure assignment length 40 bytes */ +} SecStrBuf40; +typedef struct { + unsigned char buf[41]; /* Performance optimization code structure assignment length 41 bytes */ +} SecStrBuf41; +typedef struct { + unsigned char buf[42]; /* Performance optimization code structure assignment length 42 bytes */ +} SecStrBuf42; +typedef struct { + unsigned char buf[43]; /* Performance optimization code structure assignment length 43 bytes */ +} SecStrBuf43; +typedef struct { + unsigned char buf[44]; /* Performance optimization code structure assignment length 44 bytes */ +} SecStrBuf44; +typedef struct { + unsigned char buf[45]; /* Performance optimization code structure assignment length 45 bytes */ +} SecStrBuf45; +typedef struct { + unsigned char buf[46]; /* Performance optimization code structure assignment length 46 bytes */ +} SecStrBuf46; +typedef struct { + unsigned char buf[47]; /* Performance optimization code structure assignment length 47 bytes */ +} SecStrBuf47; +typedef struct { + unsigned char buf[48]; /* Performance optimization code structure assignment length 48 bytes */ +} SecStrBuf48; +typedef struct { + unsigned char buf[49]; /* Performance optimization code structure assignment length 49 bytes */ +} SecStrBuf49; +typedef struct { + unsigned char buf[50]; /* Performance optimization code structure assignment length 50 bytes */ +} SecStrBuf50; +typedef struct { + unsigned char buf[51]; /* Performance optimization code structure assignment length 51 bytes */ +} SecStrBuf51; +typedef struct { + unsigned char buf[52]; /* Performance optimization code structure assignment length 52 bytes */ +} SecStrBuf52; +typedef struct { + unsigned char buf[53]; /* Performance optimization code structure assignment length 53 bytes */ +} SecStrBuf53; +typedef struct { + unsigned char buf[54]; /* Performance optimization code structure assignment length 54 bytes */ +} SecStrBuf54; +typedef struct { + unsigned char buf[55]; /* Performance optimization code structure assignment length 55 bytes */ +} SecStrBuf55; +typedef struct { + unsigned char buf[56]; /* Performance optimization code structure assignment length 56 bytes */ +} SecStrBuf56; +typedef struct { + unsigned char buf[57]; /* Performance optimization code structure assignment length 57 bytes */ +} SecStrBuf57; +typedef struct { + unsigned char buf[58]; /* Performance optimization code structure assignment length 58 bytes */ +} SecStrBuf58; +typedef struct { + unsigned char buf[59]; /* Performance optimization code structure assignment length 59 bytes */ +} SecStrBuf59; +typedef struct { + unsigned char buf[60]; /* Performance optimization code structure assignment length 60 bytes */ +} SecStrBuf60; +typedef struct { + unsigned char buf[61]; /* Performance optimization code structure assignment length 61 bytes */ +} SecStrBuf61; +typedef struct { + unsigned char buf[62]; /* Performance optimization code structure assignment length 62 bytes */ +} SecStrBuf62; +typedef struct { + unsigned char buf[63]; /* Performance optimization code structure assignment length 63 bytes */ +} SecStrBuf63; +typedef struct { + unsigned char buf[64]; /* Performance optimization code structure assignment length 64 bytes */ +} SecStrBuf64; + +/* + * User can change the error handler by modify the following definition, + * such as logging the detail error in file. + */ +#if defined(_DEBUG) || defined(DEBUG) +#if defined(SECUREC_ERROR_HANDLER_BY_ASSERT) +#define SECUREC_ERROR_INVALID_PARAMTER(msg) assert(msg "invalid argument" == NULL) +#define SECUREC_ERROR_INVALID_RANGE(msg) assert(msg "invalid dest buffer size" == NULL) +#define SECUREC_ERROR_BUFFER_OVERLAP(msg) assert(msg "buffer overlap" == NULL) +#elif defined(SECUREC_ERROR_HANDLER_BY_PRINTF) +#if SECUREC_IN_KERNEL +#define SECUREC_ERROR_INVALID_PARAMTER(msg) printk("%s invalid argument\n", msg) +#define SECUREC_ERROR_INVALID_RANGE(msg) printk("%s invalid dest buffer size\n", msg) +#define SECUREC_ERROR_BUFFER_OVERLAP(msg) printk("%s buffer overlap\n", msg) +#else +#define SECUREC_ERROR_INVALID_PARAMTER(msg) printf("%s invalid argument\n", msg) +#define SECUREC_ERROR_INVALID_RANGE(msg) printf("%s invalid dest buffer size\n", msg) +#define SECUREC_ERROR_BUFFER_OVERLAP(msg) printf("%s buffer overlap\n", msg) +#endif +#elif defined(SECUREC_ERROR_HANDLER_BY_FILE_LOG) +#define SECUREC_ERROR_INVALID_PARAMTER(msg) LogSecureCRuntimeError(msg " EINVAL\n") +#define SECUREC_ERROR_INVALID_RANGE(msg) LogSecureCRuntimeError(msg " ERANGE\n") +#define SECUREC_ERROR_BUFFER_OVERLAP(msg) LogSecureCRuntimeError(msg " EOVERLAP\n") +#endif +#endif + +/* Default handler is none */ +#ifndef SECUREC_ERROR_INVALID_PARAMTER +#define SECUREC_ERROR_INVALID_PARAMTER(msg) +#endif +#ifndef SECUREC_ERROR_INVALID_RANGE +#define SECUREC_ERROR_INVALID_RANGE(msg) +#endif +#ifndef SECUREC_ERROR_BUFFER_OVERLAP +#define SECUREC_ERROR_BUFFER_OVERLAP(msg) +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* Assembly language memory copy and memory set for X86 or MIPS ... */ +#ifdef SECUREC_USE_ASM +void *memcpy_opt(void *dest, const void *src, size_t n); +void *memset_opt(void *s, int c, size_t n); +#endif + +#if defined(SECUREC_ERROR_HANDLER_BY_FILE_LOG) +void LogSecureCRuntimeError(const char *errDetail); +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_a.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_a.c new file mode 100644 index 00000000..e79868f4 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_a.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: By defining data type for ANSI string and including "input.inl", + * this file generates real underlying function used by scanf family API. + * Create: 2014-02-25 + */ + +#define SECUREC_FORMAT_OUTPUT_INPUT 1 +#ifdef SECUREC_FOR_WCHAR +#undef SECUREC_FOR_WCHAR +#endif + +#include "secinput.h" + +#include "input.inl" + +SECUREC_INLINE int SecIsDigit(SecInt ch) +{ + /* SecInt to unsigned char clear 571, use bit mask to clear negative return of ch */ + return isdigit((int)((unsigned int)(unsigned char)(ch) & 0xffU)); +} +SECUREC_INLINE int SecIsXdigit(SecInt ch) +{ + return isxdigit((int)((unsigned int)(unsigned char)(ch) & 0xffU)); +} +SECUREC_INLINE int SecIsSpace(SecInt ch) +{ + return isspace((int)((unsigned int)(unsigned char)(ch) & 0xffU)); +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_w.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_w.c new file mode 100644 index 00000000..12c9ef81 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_w.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: By defining data type for UNICODE string and including "input.inl", + * this file generates real underlying function used by scanf family API. + * Create: 2014-02-25 + */ + +/* If some platforms don't have wchar.h, don't include it */ +#if !(defined(SECUREC_VXWORKS_PLATFORM)) +/* If there is no macro below, it will cause vs2010 compiling alarm */ +#if defined(_MSC_VER) && (_MSC_VER >= 1400) +#ifndef __STDC_WANT_SECURE_LIB__ +/* The order of adjustment is to eliminate alarm of Duplicate Block */ +#define __STDC_WANT_SECURE_LIB__ 0 +#endif +#ifndef _CRTIMP_ALTERNATIVE +#define _CRTIMP_ALTERNATIVE /* Comment microsoft *_s function */ +#endif +#endif +#include +#endif + +/* Disable wchar func to clear vs warning */ +#define SECUREC_ENABLE_WCHAR_FUNC 0 +#define SECUREC_FORMAT_OUTPUT_INPUT 1 + +#ifndef SECUREC_FOR_WCHAR +#define SECUREC_FOR_WCHAR +#endif + +#include "secinput.h" + +#include "input.inl" + +SECUREC_INLINE unsigned int SecWcharHighBits(SecInt ch) +{ + /* Convert int to unsigned int clear 571 */ + return ((unsigned int)(int)ch & (~0xffU)); +} + +SECUREC_INLINE unsigned char SecWcharLowByte(SecInt ch) +{ + /* Convert int to unsigned int clear 571 */ + return (unsigned char)((unsigned int)(int)ch & 0xffU); +} + +SECUREC_INLINE int SecIsDigit(SecInt ch) +{ + if (SecWcharHighBits(ch) != 0) { + return 0; /* Same as isdigit */ + } + return isdigit((int)SecWcharLowByte(ch)); +} + +SECUREC_INLINE int SecIsXdigit(SecInt ch) +{ + if (SecWcharHighBits(ch) != 0) { + return 0; /* Same as isxdigit */ + } + return isxdigit((int)SecWcharLowByte(ch)); +} + +SECUREC_INLINE int SecIsSpace(SecInt ch) +{ + return iswspace((wint_t)(int)(ch)); +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput.h new file mode 100644 index 00000000..dc483f58 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput.h @@ -0,0 +1,153 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: Define macro, enum, data struct, and declare internal used function + * prototype, which is used by output.inl, secureprintoutput_w.c and + * secureprintoutput_a.c. + * Create: 2014-02-25 + */ + +#ifndef SECUREPRINTOUTPUT_H_E950DA2C_902F_4B15_BECD_948E99090D9C +#define SECUREPRINTOUTPUT_H_E950DA2C_902F_4B15_BECD_948E99090D9C +#include "securecutil.h" + +/* Shield compilation alerts about using sprintf without format attribute to format float value. */ +#ifndef SECUREC_HANDLE_WFORMAT +#define SECUREC_HANDLE_WFORMAT 1 +#endif + +#if defined(__clang__) +#if SECUREC_HANDLE_WFORMAT && defined(__GNUC__) && ((__GNUC__ >= 5) || \ + (defined(__GNUC_MINOR__) && (__GNUC__ == 4 && __GNUC_MINOR__ >= 2))) +#define SECUREC_MASK_WFORMAT_WARNING _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wformat-nonliteral\"") +#define SECUREC_END_MASK_WFORMAT_WARNING _Pragma("GCC diagnostic pop") +#else +#define SECUREC_MASK_WFORMAT_WARNING +#define SECUREC_END_MASK_WFORMAT_WARNING +#endif +#else +#if SECUREC_HANDLE_WFORMAT && defined(__GNUC__) && ((__GNUC__ >= 5 ) || \ + (defined(__GNUC_MINOR__) && (__GNUC__ == 4 && __GNUC_MINOR__ > 7))) +#define SECUREC_MASK_WFORMAT_WARNING _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wformat-nonliteral\"") \ + _Pragma("GCC diagnostic ignored \"-Wmissing-format-attribute\"") \ + _Pragma("GCC diagnostic ignored \"-Wsuggest-attribute=format\"") +#define SECUREC_END_MASK_WFORMAT_WARNING _Pragma("GCC diagnostic pop") +#else +#define SECUREC_MASK_WFORMAT_WARNING +#define SECUREC_END_MASK_WFORMAT_WARNING +#endif +#endif + +#define SECUREC_MASK_VSPRINTF_WARNING SECUREC_MASK_WFORMAT_WARNING \ + SECUREC_MASK_MSVC_CRT_WARNING + +#define SECUREC_END_MASK_VSPRINTF_WARNING SECUREC_END_MASK_WFORMAT_WARNING \ + SECUREC_END_MASK_MSVC_CRT_WARNING + +/* + * Flag definitions. + * Using macros instead of enumerations is because some of the enumerated types under the compiler are 16bit. + */ +#define SECUREC_FLAG_SIGN 0x00001U +#define SECUREC_FLAG_SIGN_SPACE 0x00002U +#define SECUREC_FLAG_LEFT 0x00004U +#define SECUREC_FLAG_LEADZERO 0x00008U +#define SECUREC_FLAG_LONG 0x00010U +#define SECUREC_FLAG_SHORT 0x00020U +#define SECUREC_FLAG_SIGNED 0x00040U +#define SECUREC_FLAG_ALTERNATE 0x00080U +#define SECUREC_FLAG_NEGATIVE 0x00100U +#define SECUREC_FLAG_FORCE_OCTAL 0x00200U +#define SECUREC_FLAG_LONG_DOUBLE 0x00400U +#define SECUREC_FLAG_WIDECHAR 0x00800U +#define SECUREC_FLAG_LONGLONG 0x01000U +#define SECUREC_FLAG_CHAR 0x02000U +#define SECUREC_FLAG_POINTER 0x04000U +#define SECUREC_FLAG_I64 0x08000U +#define SECUREC_FLAG_PTRDIFF 0x10000U +#define SECUREC_FLAG_SIZE 0x20000U +#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT +#define SECUREC_FLAG_INTMAX 0x40000U +#endif + +/* State definitions. Identify the status of the current format */ +typedef enum { + STAT_NORMAL, + STAT_PERCENT, + STAT_FLAG, + STAT_WIDTH, + STAT_DOT, + STAT_PRECIS, + STAT_SIZE, + STAT_TYPE, + STAT_INVALID +} SecFmtState; + +#ifndef SECUREC_BUFFER_SIZE +#if SECUREC_IN_KERNEL +#define SECUREC_BUFFER_SIZE 32 +#elif defined(SECUREC_STACK_SIZE_LESS_THAN_1K) +/* + * SECUREC BUFFER SIZE Can not be less than 23 + * The length of the octal representation of 64-bit integers with zero lead + */ +#define SECUREC_BUFFER_SIZE 256 +#else +#define SECUREC_BUFFER_SIZE 512 +#endif +#endif +#if SECUREC_BUFFER_SIZE < 23 +#error SECUREC_BUFFER_SIZE Can not be less than 23 +#endif +/* Buffer size for wchar, use 4 to make the compiler aligns as 8 bytes as possible */ +#define SECUREC_WCHAR_BUFFER_SIZE 4 + +#define SECUREC_MAX_PRECISION SECUREC_BUFFER_SIZE +/* Max. # bytes in multibyte char,see MB_LEN_MAX */ +#define SECUREC_MB_LEN 16 +/* The return value of the internal function, which is returned when truncated */ +#define SECUREC_PRINTF_TRUNCATE (-2) + +#define SECUREC_VSPRINTF_PARAM_ERROR(format, strDest, destMax, maxLimit) \ + ((format) == NULL || (strDest) == NULL || (destMax) == 0 || (destMax) > (maxLimit)) + +#define SECUREC_VSPRINTF_CLEAR_DEST(strDest, destMax, maxLimit) do { \ + if ((strDest) != NULL && (destMax) > 0 && (destMax) <= (maxLimit)) { \ + *(strDest) = '\0'; \ + } \ +} SECUREC_WHILE_ZERO + +#ifdef SECUREC_COMPATIBLE_WIN_FORMAT +#define SECUREC_VSNPRINTF_PARAM_ERROR(format, strDest, destMax, count, maxLimit) \ + (((format) == NULL || (strDest) == NULL || (destMax) == 0 || (destMax) > (maxLimit)) || \ + ((count) > (SECUREC_STRING_MAX_LEN - 1) && (count) != (size_t)(-1))) + +#else +#define SECUREC_VSNPRINTF_PARAM_ERROR(format, strDest, destMax, count, maxLimit) \ + (((format) == NULL || (strDest) == NULL || (destMax) == 0 || (destMax) > (maxLimit)) || \ + ((count) > (SECUREC_STRING_MAX_LEN - 1))) +#endif + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef SECUREC_FOR_WCHAR +int SecVswprintfImpl(wchar_t *string, size_t count, const wchar_t *format, va_list argList); +#else +int SecVsnprintfImpl(char *string, size_t count, const char *format, va_list argList); +#endif +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_a.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_a.c new file mode 100644 index 00000000..b2b4b6a6 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_a.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: By defining corresponding macro for ANSI string and including "output.inl", + * this file generates real underlying function used by printf family API. + * Create: 2014-02-25 + */ + +#define SECUREC_FORMAT_OUTPUT_INPUT 1 + +#ifdef SECUREC_FOR_WCHAR +#undef SECUREC_FOR_WCHAR +#endif + +#include "secureprintoutput.h" +#if SECUREC_WARP_OUTPUT +#define SECUREC_FORMAT_FLAG_TABLE_SIZE 128 +SECUREC_INLINE const char *SecSkipKnownFlags(const char *format) +{ + static const unsigned char flagTable[SECUREC_FORMAT_FLAG_TABLE_SIZE] = { + /* + * Known flag is "0123456789 +-#hlLwZzjqt*I$" + */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x01, 0x00, 0x00, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + const char *fmt = format; + while (*fmt != '\0') { + char fmtChar = *fmt; + if ((unsigned char)fmtChar > 0x7f) { /* 0x7f is upper limit of format char value */ + break; + } + if (flagTable[(unsigned char)fmtChar] == 0) { + break; + } + ++fmt; + } + return fmt; +} + +SECUREC_INLINE int SecFormatContainN(const char *format) +{ + const char *fmt = format; + while (*fmt != '\0') { + ++fmt; + /* Skip normal char */ + if (*(fmt - 1) != '%') { + continue; + } + /* Meet %% */ + if (*fmt == '%') { + ++fmt; /* Point to the character after the %. Correct handling %%xx */ + continue; + } + /* Now parse %..., fmt point to the character after the % */ + fmt = SecSkipKnownFlags(fmt); + if (*fmt == 'n') { + return 1; + } + } + return 0; +} +/* + * Multi character formatted output implementation, the count include \0 character, must be greater than zero + */ +int SecVsnprintfImpl(char *string, size_t count, const char *format, va_list argList) +{ + int retVal; + if (SecFormatContainN(format) != 0) { + string[0] = '\0'; + return -1; + } + SECUREC_MASK_VSPRINTF_WARNING + retVal = vsnprintf(string, count, format, argList); + SECUREC_END_MASK_VSPRINTF_WARNING + if (retVal >= (int)count) { /* The size_t to int is ok, count max is SECUREC_STRING_MAX_LEN */ + /* The buffer was too small; we return truncation */ + string[count - 1] = '\0'; + return SECUREC_PRINTF_TRUNCATE; + } + if (retVal < 0) { + string[0] = '\0'; /* Empty the dest strDest */ + return -1; + } + return retVal; +} +#else +#if SECUREC_IN_KERNEL +#include +#endif + +#ifndef EOF +#define EOF (-1) +#endif + +#include "output.inl" + +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_w.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_w.c new file mode 100644 index 00000000..672c0184 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_w.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: By defining corresponding macro for UNICODE string and including "output.inl", + * this file generates real underlying function used by printf family API. + * Create: 2014-02-25 + */ + +/* If some platforms don't have wchar.h, don't include it */ +#if !(defined(SECUREC_VXWORKS_PLATFORM)) +/* If there is no macro above, it will cause compiling alarm */ +#if defined(_MSC_VER) && (_MSC_VER >= 1400) +#ifndef _CRTIMP_ALTERNATIVE +#define _CRTIMP_ALTERNATIVE /* Comment microsoft *_s function */ +#endif +#ifndef __STDC_WANT_SECURE_LIB__ +#define __STDC_WANT_SECURE_LIB__ 0 +#endif +#endif +#include +#endif + +/* Disable wchar func to clear vs warning */ +#define SECUREC_ENABLE_WCHAR_FUNC 0 +#define SECUREC_FORMAT_OUTPUT_INPUT 1 + +#ifndef SECUREC_FOR_WCHAR +#define SECUREC_FOR_WCHAR +#endif + +#include "secureprintoutput.h" + +#include "output.inl" + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/snprintf_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/snprintf_s.c new file mode 100644 index 00000000..e9b94f37 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/snprintf_s.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: snprintf_s function + * Create: 2014-02-25 + */ + +#include "securec.h" + +#if SECUREC_ENABLE_SNPRINTF +/* + * + * The snprintf_s function is equivalent to the snprintf function + * except for the parameter destMax/count and the explicit runtime-constraints violation + * The snprintf_s function formats and stores count or fewer characters in + * strDest and appends a terminating null. Each argument (if any) is converted + * and output according to the corresponding format specification in format. + * The formatting is consistent with the printf family of functions; If copying + * occurs between strings that overlap, the behavior is undefined. + * + * + * strDest Storage location for the output. + * destMax The size of the storage location for output. Size + * in bytes for snprintf_s or size in words for snwprintf_s. + * count Maximum number of character to store. + * format Format-control string. + * ... Optional arguments. + * + * + * strDest is updated + * + * + * return the number of characters written, not including the terminating null + * return -1 if an error occurs. + * return -1 if count < destMax and the output string has been truncated + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + * + */ +int snprintf_s(char *strDest, size_t destMax, size_t count, const char *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vsnprintf_s(strDest, destMax, count, format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(snprintf_s); +#endif +#endif + +#if SECUREC_SNPRINTF_TRUNCATED +/* + * + * The snprintf_truncated_s function is equivalent to the snprintf function + * except for the parameter destMax/count and the explicit runtime-constraints violation + * The snprintf_truncated_s function formats and stores count or fewer characters in + * strDest and appends a terminating null. Each argument (if any) is converted + * and output according to the corresponding format specification in format. + * The formatting is consistent with the printf family of functions; If copying + * occurs between strings that overlap, the behavior is undefined. + * + * + * strDest Storage location for the output. + * destMax The size of the storage location for output. Size + * in bytes for snprintf_truncated_s or size in words for snwprintf_s. + * format Format-control string. + * ... Optional arguments. + * + * + * strDest is updated + * + * + * return the number of characters written, not including the terminating null + * return -1 if an error occurs. + * return destMax-1 if output string has been truncated + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + * + */ +int snprintf_truncated_s(char *strDest, size_t destMax, const char *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vsnprintf_truncated_s(strDest, destMax, format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(snprintf_truncated_s); +#endif + +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/sprintf_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/sprintf_s.c new file mode 100644 index 00000000..0cf3fca9 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/sprintf_s.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: sprintf_s function + * Create: 2014-02-25 + */ + +#include "securec.h" + +/* + * + * The sprintf_s function is equivalent to the sprintf function + * except for the parameter destMax and the explicit runtime-constraints violation + * The sprintf_s function formats and stores a series of characters and values + * in strDest. Each argument (if any) is converted and output according to + * the corresponding format specification in format. The format consists of + * ordinary characters and has the same form and function as the format argument + * for printf. A null character is appended after the last character written. + * If copying occurs between strings that overlap, the behavior is undefined. + * + * + * strDest Storage location for output. + * destMax Maximum number of characters to store. + * format Format-control string. + * ... Optional arguments + * + * + * strDest is updated + * + * + * return the number of bytes stored in strDest, not counting the terminating null character. + * return -1 if an error occurred. + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +int sprintf_s(char *strDest, size_t destMax, const char *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vsprintf_s(strDest, destMax, format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(sprintf_s); +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/sscanf_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/sscanf_s.c new file mode 100644 index 00000000..b441329e --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/sscanf_s.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: sscanf_s function + * Create: 2014-02-25 + */ + +#include "securec.h" + +/* + * + * The sscanf_s function is equivalent to fscanf_s, + * except that input is obtained from a string (specified by the argument buffer) rather than from a stream + * The sscanf function reads data from buffer into the location given by each + * argument. Every argument must be a pointer to a variable with a type that + * corresponds to a type specifier in format. The format argument controls the + * interpretation of the input fields and has the same form and function as + * the format argument for the scanf function. + * If copying takes place between strings that overlap, the behavior is undefined. + * + * + * buffer Stored data. + * format Format control string, see Format Specifications. + * ... Optional arguments. + * + * + * ... The converted value stored in user assigned address + * + * + * Each of these functions returns the number of fields successfully converted + * and assigned; the return value does not include fields that were read but + * not assigned. + * A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int sscanf_s(const char *buffer, const char *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vsscanf_s(buffer, format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(sscanf_s); +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/strcat_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/strcat_s.c new file mode 100644 index 00000000..f835e7bc --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/strcat_s.c @@ -0,0 +1,101 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: strcat_s function + * Create: 2014-02-25 + */ + +#include "securecutil.h" + +/* + * Befor this function, the basic parameter checking has been done + */ +SECUREC_INLINE errno_t SecDoCat(char *strDest, size_t destMax, const char *strSrc) +{ + size_t destLen; + size_t srcLen; + size_t maxSrcLen; + SECUREC_CALC_STR_LEN(strDest, destMax, &destLen); + /* Only optimize strSrc, do not apply this function to strDest */ + maxSrcLen = destMax - destLen; + SECUREC_CALC_STR_LEN_OPT(strSrc, maxSrcLen, &srcLen); + + if (SECUREC_CAT_STRING_IS_OVERLAP(strDest, destLen, strSrc, srcLen)) { + strDest[0] = '\0'; + if (strDest + destLen <= strSrc && destLen == destMax) { + SECUREC_ERROR_INVALID_PARAMTER("strcat_s"); + return EINVAL_AND_RESET; + } + SECUREC_ERROR_BUFFER_OVERLAP("strcat_s"); + return EOVERLAP_AND_RESET; + } + if (srcLen + destLen >= destMax || strDest == strSrc) { + strDest[0] = '\0'; + if (destLen == destMax) { + SECUREC_ERROR_INVALID_PARAMTER("strcat_s"); + return EINVAL_AND_RESET; + } + SECUREC_ERROR_INVALID_RANGE("strcat_s"); + return ERANGE_AND_RESET; + } + SECUREC_MEMCPY_WARP_OPT(strDest + destLen, strSrc, srcLen + 1); /* Single character length include \0 */ + return EOK; +} + +/* + * + * The strcat_s function appends a copy of the string pointed to by strSrc (including the terminating null character) + * to the end of the string pointed to by strDest. + * The initial character of strSrc overwrites the terminating null character of strDest. + * strcat_s will return EOVERLAP_AND_RESET if the source and destination strings overlap. + * + * Note that the second parameter is the total size of the buffer, not the + * remaining size. + * + * + * strDest Null-terminated destination string buffer. + * destMax Size of the destination string buffer. + * strSrc Null-terminated source string buffer. + * + * + * strDest is updated + * + * + * EOK Success + * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN + * EINVAL_AND_RESET (strDest unterminated and all other parameters are valid) or + * (strDest != NULL and strSrc is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN) + * ERANGE destMax is 0 and destMax > SECUREC_STRING_MAX_LEN + * ERANGE_AND_RESET strDest have not enough space and all other parameters are valid and not overlap + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and all parameters are valid + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +errno_t strcat_s(char *strDest, size_t destMax, const char *strSrc) +{ + if (destMax == 0 || destMax > SECUREC_STRING_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("strcat_s"); + return ERANGE; + } + if (strDest == NULL || strSrc == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("strcat_s"); + if (strDest != NULL) { + strDest[0] = '\0'; + return EINVAL_AND_RESET; + } + return EINVAL; + } + return SecDoCat(strDest, destMax, strSrc); +} + +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(strcat_s); +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/strcpy_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/strcpy_s.c new file mode 100644 index 00000000..ca1b2ddb --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/strcpy_s.c @@ -0,0 +1,353 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: strcpy_s function + * Create: 2014-02-25 + */ +/* + * [Standardize-exceptions] Use unsafe function: Performance-sensitive + * [reason] Always used in the performance critical path, + * and sufficient input validation is performed before calling + */ + +#include "securecutil.h" + +#ifndef SECUREC_STRCPY_WITH_PERFORMANCE +#define SECUREC_STRCPY_WITH_PERFORMANCE 1 +#endif + +#define SECUREC_STRCPY_PARAM_OK(strDest, destMax, strSrc) ((destMax) > 0 && \ + (destMax) <= SECUREC_STRING_MAX_LEN && (strDest) != NULL && (strSrc) != NULL && (strDest) != (strSrc)) + +#if (!SECUREC_IN_KERNEL) && SECUREC_STRCPY_WITH_PERFORMANCE +#ifndef SECUREC_STRCOPY_THRESHOLD_SIZE +#define SECUREC_STRCOPY_THRESHOLD_SIZE 32UL +#endif +/* The purpose of converting to void is to clean up the alarm */ +#define SECUREC_SMALL_STR_COPY(strDest, strSrc, lenWithTerm) do { \ + if (SECUREC_ADDR_ALIGNED_8(strDest) && SECUREC_ADDR_ALIGNED_8(strSrc)) { \ + /* Use struct assignment */ \ + switch (lenWithTerm) { \ + case 1: \ + *(strDest) = *(strSrc); \ + break; \ + case 2: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 2); \ + break; \ + case 3: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 3); \ + break; \ + case 4: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 4); \ + break; \ + case 5: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 5); \ + break; \ + case 6: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 6); \ + break; \ + case 7: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 7); \ + break; \ + case 8: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 8); \ + break; \ + case 9: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 9); \ + break; \ + case 10: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 10); \ + break; \ + case 11: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 11); \ + break; \ + case 12: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 12); \ + break; \ + case 13: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 13); \ + break; \ + case 14: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 14); \ + break; \ + case 15: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 15); \ + break; \ + case 16: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 16); \ + break; \ + case 17: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 17); \ + break; \ + case 18: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 18); \ + break; \ + case 19: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 19); \ + break; \ + case 20: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 20); \ + break; \ + case 21: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 21); \ + break; \ + case 22: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 22); \ + break; \ + case 23: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 23); \ + break; \ + case 24: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 24); \ + break; \ + case 25: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 25); \ + break; \ + case 26: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 26); \ + break; \ + case 27: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 27); \ + break; \ + case 28: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 28); \ + break; \ + case 29: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 29); \ + break; \ + case 30: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 30); \ + break; \ + case 31: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 31); \ + break; \ + case 32: \ + SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 32); \ + break; \ + default: \ + /* Do nothing */ \ + break; \ + } /* END switch */ \ + } else { \ + char *tmpStrDest_ = (char *)(strDest); \ + const char *tmpStrSrc_ = (const char *)(strSrc); \ + switch (lenWithTerm) { \ + case 32: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 31: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 30: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 29: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 28: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 27: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 26: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 25: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 24: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 23: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 22: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 21: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 20: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 19: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 18: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 17: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 16: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 15: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 14: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 13: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 12: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 11: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 10: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 9: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 8: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 7: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 6: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 5: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 4: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 3: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 2: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + case 1: \ + *(tmpStrDest_++) = *(tmpStrSrc_++); \ + /* fall-through */ /* FALLTHRU */ \ + default: \ + /* Do nothing */ \ + break; \ + } \ + } \ +} SECUREC_WHILE_ZERO +#endif + +#if SECUREC_IN_KERNEL || (!SECUREC_STRCPY_WITH_PERFORMANCE) +#define SECUREC_STRCPY_OPT(dest, src, lenWithTerm) SECUREC_MEMCPY_WARP_OPT((dest), (src), (lenWithTerm)) +#else +/* + * Performance optimization. lenWithTerm include '\0' + */ +#define SECUREC_STRCPY_OPT(dest, src, lenWithTerm) do { \ + if ((lenWithTerm) > SECUREC_STRCOPY_THRESHOLD_SIZE) { \ + SECUREC_MEMCPY_WARP_OPT((dest), (src), (lenWithTerm)); \ + } else { \ + SECUREC_SMALL_STR_COPY((dest), (src), (lenWithTerm)); \ + } \ +} SECUREC_WHILE_ZERO +#endif + +/* + * Check Src Range + */ +SECUREC_INLINE errno_t CheckSrcRange(char *strDest, size_t destMax, const char *strSrc) +{ + size_t tmpDestMax = destMax; + const char *tmpSrc = strSrc; + /* Use destMax as boundary checker and destMax must be greater than zero */ + while (*tmpSrc != '\0' && tmpDestMax > 0) { + ++tmpSrc; + --tmpDestMax; + } + if (tmpDestMax == 0) { + strDest[0] = '\0'; + SECUREC_ERROR_INVALID_RANGE("strcpy_s"); + return ERANGE_AND_RESET; + } + return EOK; +} + +/* + * Handling errors + */ +errno_t strcpy_error(char *strDest, size_t destMax, const char *strSrc) +{ + if (destMax == 0 || destMax > SECUREC_STRING_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("strcpy_s"); + return ERANGE; + } + if (strDest == NULL || strSrc == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("strcpy_s"); + if (strDest != NULL) { + strDest[0] = '\0'; + return EINVAL_AND_RESET; + } + return EINVAL; + } + return CheckSrcRange(strDest, destMax, strSrc); +} + +/* + * + * The strcpy_s function copies the string pointed to strSrc + * (including the terminating null character) into the array pointed to by strDest + * The destination string must be large enough to hold the source string, + * including the terminating null character. strcpy_s will return EOVERLAP_AND_RESET + * if the source and destination strings overlap. + * + * + * strDest Location of destination string buffer + * destMax Size of the destination string buffer. + * strSrc Null-terminated source string buffer. + * + * + * strDest is updated. + * + * + * EOK Success + * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN + * EINVAL_AND_RESET strDest != NULL and strSrc is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN + * ERANGE destMax is 0 and destMax > SECUREC_STRING_MAX_LEN + * ERANGE_AND_RESET strDest have not enough space and all other parameters are valid and not overlap + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and all parameters are valid + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +errno_t strcpy_s(char *strDest, size_t destMax, const char *strSrc) +{ + if (SECUREC_STRCPY_PARAM_OK(strDest, destMax, strSrc)) { + size_t srcStrLen; + SECUREC_CALC_STR_LEN(strSrc, destMax, &srcStrLen); + ++srcStrLen; /* The length include '\0' */ + + if (srcStrLen <= destMax) { + /* Use mem overlap check include '\0' */ + if (SECUREC_MEMORY_NO_OVERLAP(strDest, strSrc, srcStrLen)) { + /* Performance optimization srcStrLen include '\0' */ + SECUREC_STRCPY_OPT(strDest, strSrc, srcStrLen); + return EOK; + } else { + strDest[0] = '\0'; + SECUREC_ERROR_BUFFER_OVERLAP("strcpy_s"); + return EOVERLAP_AND_RESET; + } + } + } + return strcpy_error(strDest, destMax, strSrc); +} + +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(strcpy_s); +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/strncat_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/strncat_s.c new file mode 100644 index 00000000..6686d299 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/strncat_s.c @@ -0,0 +1,119 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: strncat_s function + * Create: 2014-02-25 + */ + +#include "securecutil.h" + +/* + * Befor this function, the basic parameter checking has been done + */ +SECUREC_INLINE errno_t SecDoCatLimit(char *strDest, size_t destMax, const char *strSrc, size_t count) +{ + size_t destLen; + size_t srcLen; + SECUREC_CALC_STR_LEN(strDest, destMax, &destLen); + /* + * The strSrc is no longer optimized. The reason is that when count is small, + * the efficiency of strnlen is higher than that of self realization. + */ + SECUREC_CALC_STR_LEN(strSrc, count, &srcLen); + + if (SECUREC_CAT_STRING_IS_OVERLAP(strDest, destLen, strSrc, srcLen)) { + strDest[0] = '\0'; + if (strDest + destLen <= strSrc && destLen == destMax) { + SECUREC_ERROR_INVALID_PARAMTER("strncat_s"); + return EINVAL_AND_RESET; + } + SECUREC_ERROR_BUFFER_OVERLAP("strncat_s"); + return EOVERLAP_AND_RESET; + } + if (srcLen + destLen >= destMax || strDest == strSrc) { + strDest[0] = '\0'; + if (destLen == destMax) { + SECUREC_ERROR_INVALID_PARAMTER("strncat_s"); + return EINVAL_AND_RESET; + } + SECUREC_ERROR_INVALID_RANGE("strncat_s"); + return ERANGE_AND_RESET; + } + SECUREC_MEMCPY_WARP_OPT(strDest + destLen, strSrc, srcLen); /* No terminator */ + *(strDest + destLen + srcLen) = '\0'; + return EOK; +} + +/* + * + * The strncat_s function appends not more than n successive characters + * (not including the terminating null character) + * from the array pointed to by strSrc to the end of the string pointed to by strDest + * The strncat_s function try to append the first D characters of strSrc to + * the end of strDest, where D is the lesser of count and the length of strSrc. + * If appending those D characters will fit within strDest (whose size is given + * as destMax) and still leave room for a null terminator, then those characters + * are appended, starting at the original terminating null of strDest, and a + * new terminating null is appended; otherwise, strDest[0] is set to the null + * character. + * + * + * strDest Null-terminated destination string. + * destMax Size of the destination buffer. + * strSrc Null-terminated source string. + * count Number of character to append, or truncate. + * + * + * strDest is updated + * + * + * EOK Success + * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN + * EINVAL_AND_RESET (strDest unterminated and all other parameters are valid)or + * (strDest != NULL and strSrc is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN) + * ERANGE destMax is 0 and destMax > SECUREC_STRING_MAX_LEN + * ERANGE_AND_RESET strDest have not enough space and all other parameters are valid and not overlap + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and all parameters are valid + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +errno_t strncat_s(char *strDest, size_t destMax, const char *strSrc, size_t count) +{ + if (destMax == 0 || destMax > SECUREC_STRING_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("strncat_s"); + return ERANGE; + } + + if (strDest == NULL || strSrc == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("strncat_s"); + if (strDest != NULL) { + strDest[0] = '\0'; + return EINVAL_AND_RESET; + } + return EINVAL; + } + if (count > SECUREC_STRING_MAX_LEN) { +#ifdef SECUREC_COMPATIBLE_WIN_FORMAT + if (count == (size_t)(-1)) { + /* Windows internal functions may pass in -1 when calling this function */ + return SecDoCatLimit(strDest, destMax, strSrc, destMax); + } +#endif + strDest[0] = '\0'; + SECUREC_ERROR_INVALID_RANGE("strncat_s"); + return ERANGE_AND_RESET; + } + return SecDoCatLimit(strDest, destMax, strSrc, count); +} + +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(strncat_s); +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/strncpy_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/strncpy_s.c new file mode 100644 index 00000000..5f4c5b70 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/strncpy_s.c @@ -0,0 +1,145 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: strncpy_s function + * Create: 2014-02-25 + */ +/* + * [Standardize-exceptions] Use unsafe function: Performance-sensitive + * [reason] Always used in the performance critical path, + * and sufficient input validation is performed before calling + */ + +#include "securecutil.h" + +#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) +#define SECUREC_STRNCPY_PARAM_OK(strDest, destMax, strSrc, count) \ + (((destMax) > 0 && (destMax) <= SECUREC_STRING_MAX_LEN && (strDest) != NULL && (strSrc) != NULL && \ + ((count) <= SECUREC_STRING_MAX_LEN || (count) == ((size_t)(-1))) && (count) > 0)) +#else +#define SECUREC_STRNCPY_PARAM_OK(strDest, destMax, strSrc, count) \ + (((destMax) > 0 && (destMax) <= SECUREC_STRING_MAX_LEN && (strDest) != NULL && (strSrc) != NULL && \ + (count) <= SECUREC_STRING_MAX_LEN && (count) > 0)) +#endif + +/* + * Check Src Count Range + */ +SECUREC_INLINE errno_t CheckSrcCountRange(char *strDest, size_t destMax, const char *strSrc, size_t count) +{ + size_t tmpDestMax = destMax; + size_t tmpCount = count; + const char *endPos = strSrc; + + /* Use destMax and count as boundary checker and destMax must be greater than zero */ + while (*(endPos) != '\0' && tmpDestMax > 0 && tmpCount > 0) { + ++endPos; + --tmpCount; + --tmpDestMax; + } + if (tmpDestMax == 0) { + strDest[0] = '\0'; + SECUREC_ERROR_INVALID_RANGE("strncpy_s"); + return ERANGE_AND_RESET; + } + return EOK; +} + +/* + * Handling errors, when dest equal src return EOK + */ +errno_t strncpy_error(char *strDest, size_t destMax, const char *strSrc, size_t count) +{ + if (destMax == 0 || destMax > SECUREC_STRING_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("strncpy_s"); + return ERANGE; + } + if (strDest == NULL || strSrc == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("strncpy_s"); + if (strDest != NULL) { + strDest[0] = '\0'; + return EINVAL_AND_RESET; + } + return EINVAL; + } + if (count > SECUREC_STRING_MAX_LEN) { + strDest[0] = '\0'; /* Clear dest string */ + SECUREC_ERROR_INVALID_RANGE("strncpy_s"); + return ERANGE_AND_RESET; + } + if (count == 0) { + strDest[0] = '\0'; + return EOK; + } + return CheckSrcCountRange(strDest, destMax, strSrc, count); +} + +/* + * + * The strncpy_s function copies not more than n successive characters (not including the terminating null character) + * from the array pointed to by strSrc to the array pointed to by strDest. + * + * + * strDest Destination string. + * destMax The size of the destination string, in characters. + * strSrc Source string. + * count Number of characters to be copied. + * + * + * strDest is updated + * + * + * EOK Success + * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN + * EINVAL_AND_RESET strDest != NULL and strSrc is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN + * ERANGE destMax is 0 and destMax > SECUREC_STRING_MAX_LEN + * ERANGE_AND_RESET strDest have not enough space and all other parameters are valid and not overlap + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and all parameters are valid + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +errno_t strncpy_s(char *strDest, size_t destMax, const char *strSrc, size_t count) +{ + if (SECUREC_STRNCPY_PARAM_OK(strDest, destMax, strSrc, count)) { + size_t minCpLen; /* Use it to store the maxi length limit */ + if (count < destMax) { + SECUREC_CALC_STR_LEN(strSrc, count, &minCpLen); /* No ending terminator */ + } else { + size_t tmpCount = destMax; +#ifdef SECUREC_COMPATIBLE_WIN_FORMAT + if (count == ((size_t)(-1))) { + tmpCount = destMax - 1; + } +#endif + SECUREC_CALC_STR_LEN(strSrc, tmpCount, &minCpLen); /* No ending terminator */ + if (minCpLen == destMax) { + strDest[0] = '\0'; + SECUREC_ERROR_INVALID_RANGE("strncpy_s"); + return ERANGE_AND_RESET; + } + } + if (SECUREC_STRING_NO_OVERLAP(strDest, strSrc, minCpLen) || strDest == strSrc) { + /* Not overlap */ + SECUREC_MEMCPY_WARP_OPT(strDest, strSrc, minCpLen); /* Copy string without terminator */ + strDest[minCpLen] = '\0'; + return EOK; + } else { + strDest[0] = '\0'; + SECUREC_ERROR_BUFFER_OVERLAP("strncpy_s"); + return EOVERLAP_AND_RESET; + } + } + return strncpy_error(strDest, destMax, strSrc, count); +} + +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(strncpy_s); +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/strtok_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/strtok_s.c new file mode 100644 index 00000000..cd5dcd2c --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/strtok_s.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: strtok_s function + * Create: 2014-02-25 + */ + +#include "securecutil.h" + +SECUREC_INLINE int SecIsInDelimit(char ch, const char *strDelimit) +{ + const char *ctl = strDelimit; + while (*ctl != '\0' && *ctl != ch) { + ++ctl; + } + return (int)(*ctl != '\0'); +} + +/* + * Find beginning of token (skip over leading delimiters). + * Note that there is no token if this loop sets string to point to the terminal null. + */ +SECUREC_INLINE char *SecFindBegin(char *strToken, const char *strDelimit) +{ + char *token = strToken; + while (*token != '\0') { + if (SecIsInDelimit(*token, strDelimit) != 0) { + ++token; + continue; + } + /* Don't find any delimiter in string header, break the loop */ + break; + } + return token; +} + +/* + * Find rest of token + */ +SECUREC_INLINE char *SecFindRest(char *strToken, const char *strDelimit) +{ + /* Find the rest of the token. If it is not the end of the string, put a null there */ + char *token = strToken; + while (*token != '\0') { + if (SecIsInDelimit(*token, strDelimit) != 0) { + /* Find a delimiter, set string terminator */ + *token = '\0'; + ++token; + break; + } + ++token; + } + return token; +} + +/* + * Find the final position pointer + */ +SECUREC_INLINE char *SecUpdateToken(char *strToken, const char *strDelimit, char **context) +{ + /* Point to updated position. Record string position for next search in the context */ + *context = SecFindRest(strToken, strDelimit); + /* Determine if a token has been found. */ + if (*context == strToken) { + return NULL; + } + return strToken; +} + +/* + * + * The strtok_s function parses a string into a sequence of strToken, + * replace all characters in strToken string that match to strDelimit set with 0. + * On the first call to strtok_s the string to be parsed should be specified in strToken. + * In each subsequent call that should parse the same string, strToken should be NULL + * + * strToken String containing token or tokens. + * strDelimit Set of delimiter characters. + * context Used to store position information between calls + * to strtok_s + * + * context is updated + * + * On the first call returns the address of the first non \0 character, otherwise NULL is returned. + * In subsequent calls, the strtoken is set to NULL, and the context set is the same as the previous call, + * return NULL if the *context string length is equal 0, otherwise return *context. + */ +char *strtok_s(char *strToken, const char *strDelimit, char **context) +{ + char *orgToken = strToken; + /* Validate delimiter and string context */ + if (context == NULL || strDelimit == NULL) { + return NULL; + } + /* Valid input string and string pointer from where to search */ + if (orgToken == NULL && *context == NULL) { + return NULL; + } + /* If string is null, continue searching from previous string position stored in context */ + if (orgToken == NULL) { + orgToken = *context; + } + orgToken = SecFindBegin(orgToken, strDelimit); + return SecUpdateToken(orgToken, strDelimit, context); +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(strtok_s); +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/swprintf_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/swprintf_s.c new file mode 100644 index 00000000..09d77a2f --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/swprintf_s.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: swprintf_s function + * Create: 2014-02-25 + */ + +#include "securec.h" + +/* + * + * The swprintf_s function is the wide-character equivalent of the sprintf_s function + * + * + * strDest Storage location for the output. + * destMax Maximum number of characters to store. + * format Format-control string. + * ... Optional arguments + * + * + * strDest is updated + * + * + * return the number of wide characters stored in strDest, not counting the terminating null wide character. + * return -1 if an error occurred. + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +int swprintf_s(wchar_t *strDest, size_t destMax, const wchar_t *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vswprintf_s(strDest, destMax, format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/swscanf_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/swscanf_s.c new file mode 100644 index 00000000..e5b8bbfc --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/swscanf_s.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: swscanf_s function + * Create: 2014-02-25 + */ + +#include "securec.h" + +/* + * + * The swscanf_s function is the wide-character equivalent of the sscanf_s function + * The swscanf_s function reads data from buffer into the location given by + * each argument. Every argument must be a pointer to a variable with a type + * that corresponds to a type specifier in format. The format argument controls + * the interpretation of the input fields and has the same form and function + * as the format argument for the scanf function. If copying takes place between + * strings that overlap, the behavior is undefined. + * + * + * buffer Stored data. + * format Format control string, see Format Specifications. + * ... Optional arguments. + * + * + * ... the converted value stored in user assigned address + * + * + * Each of these functions returns the number of fields successfully converted + * and assigned; The return value does not include fields that were read but not + * assigned. + * A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int swscanf_s(const wchar_t *buffer, const wchar_t *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vswscanf_s(buffer, format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vfscanf_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vfscanf_s.c new file mode 100644 index 00000000..214ee6a2 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vfscanf_s.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: vfscanf_s function + * Create: 2014-02-25 + */ + +#include "secinput.h" + +/* + * + * The vfscanf_s function is equivalent to fscanf_s, with the variable argument list replaced by argList + * The vfscanf_s function reads data from the current position of stream into + * the locations given by argument (if any). Each argument must be a pointer + * to a variable of a type that corresponds to a type specifier in format. + * format controls the interpretation of the input fields and has the same + * form and function as the format argument for scanf. + * + * + * stream Pointer to FILE structure. + * format Format control string, see Format Specifications. + * argList pointer to list of arguments + * + * + * argList the converted value stored in user assigned address + * + * + * Each of these functions returns the number of fields successfully converted + * and assigned; the return value does not include fields that were read but + * not assigned. A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int vfscanf_s(FILE *stream, const char *format, va_list argList) +{ + int retVal; /* If initialization causes e838 */ + SecFileStream fStr; + + if (stream == NULL || format == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("vfscanf_s"); + return SECUREC_SCANF_EINVAL; + } + if (stream == SECUREC_STREAM_STDIN) { + return vscanf_s(format, argList); + } + + SECUREC_LOCK_FILE(stream); + SECUREC_FILE_STREAM_FROM_FILE(&fStr, stream); + retVal = SecInputS(&fStr, format, argList); + SECUREC_UNLOCK_FILE(stream); + if (retVal < 0) { + SECUREC_ERROR_INVALID_PARAMTER("vfscanf_s"); + return SECUREC_SCANF_EINVAL; + } + + return retVal; +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vfwscanf_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vfwscanf_s.c new file mode 100644 index 00000000..1ab9c3cb --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vfwscanf_s.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: vfwscanf_s function + * Create: 2014-02-25 + */ + +#ifndef SECUREC_FOR_WCHAR +#define SECUREC_FOR_WCHAR +#endif + +#include "secinput.h" + +/* + * + * The vfwscanf_s function is the wide-character equivalent of the vfscanf_s function + * The vfwscanf_s function reads data from the current position of stream into + * the locations given by argument (if any). Each argument must be a pointer + * to a variable of a type that corresponds to a type specifier in format. + * format controls the interpretation of the input fields and has the same form + * and function as the format argument for scanf. + * + * + * stream Pointer to FILE structure. + * format Format control string, see Format Specifications. + * argList pointer to list of arguments + * + * + * argList the converted value stored in user assigned address + * + * + * Each of these functions returns the number of fields successfully converted + * and assigned; the return value does not include fields that were read but + * not assigned. A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int vfwscanf_s(FILE *stream, const wchar_t *format, va_list argList) +{ + int retVal; /* If initialization causes e838 */ + SecFileStream fStr; + + if (stream == NULL || format == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("vfwscanf_s"); + return SECUREC_SCANF_EINVAL; + } + if (stream == SECUREC_STREAM_STDIN) { + return vwscanf_s(format, argList); + } + + SECUREC_LOCK_FILE(stream); + SECUREC_FILE_STREAM_FROM_FILE(&fStr, stream); + retVal = SecInputSW(&fStr, format, argList); + SECUREC_UNLOCK_FILE(stream); + if (retVal < 0) { + SECUREC_ERROR_INVALID_PARAMTER("vfwscanf_s"); + return SECUREC_SCANF_EINVAL; + } + return retVal; +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vscanf_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vscanf_s.c new file mode 100644 index 00000000..61480a69 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vscanf_s.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: vscanf_s function + * Create: 2014-02-25 + */ + +#include "secinput.h" + +/* + * + * The vscanf_s function is equivalent to scanf_s, with the variable argument list replaced by argList, + * The vscanf_s function reads data from the standard input stream stdin and + * writes the data into the location that's given by argument. Each argument + * must be a pointer to a variable of a type that corresponds to a type specifier + * in format. If copying occurs between strings that overlap, the behavior is + * undefined. + * + * + * format Format control string. + * argList pointer to list of arguments + * + * + * argList the converted value stored in user assigned address + * + * + * Returns the number of fields successfully converted and assigned; + * the return value does not include fields that were read but not assigned. + * A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int vscanf_s(const char *format, va_list argList) +{ + int retVal; /* If initialization causes e838 */ + SecFileStream fStr; + SECUREC_FILE_STREAM_FROM_STDIN(&fStr); + /* + * The "va_list" has different definition on different platform, so we can't use argList == NULL + * To determine it's invalid. If you has fixed platform, you can check some fields to validate it, + * such as "argList == NULL" or argList.xxx != NULL or *(size_t *)&argList != 0. + */ + if (format == NULL || fStr.pf == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("vscanf_s"); + return SECUREC_SCANF_EINVAL; + } + + SECUREC_LOCK_STDIN(0, fStr.pf); + retVal = SecInputS(&fStr, format, argList); + SECUREC_UNLOCK_STDIN(0, fStr.pf); + if (retVal < 0) { + SECUREC_ERROR_INVALID_PARAMTER("vscanf_s"); + return SECUREC_SCANF_EINVAL; + } + return retVal; +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vsnprintf_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vsnprintf_s.c new file mode 100644 index 00000000..35caaa22 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vsnprintf_s.c @@ -0,0 +1,138 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: vsnprintf_s function + * Create: 2014-02-25 + */ + +#include "secureprintoutput.h" + +#if SECUREC_ENABLE_VSNPRINTF +/* + * + * The vsnprintf_s function is equivalent to the vsnprintf function + * except for the parameter destMax/count and the explicit runtime-constraints violation + * The vsnprintf_s function takes a pointer to an argument list, then formats + * and writes up to count characters of the given data to the memory pointed + * to by strDest and appends a terminating null. + * + * + * strDest Storage location for the output. + * destMax The size of the strDest for output. + * count Maximum number of character to write(not including + * the terminating NULL) + * format Format-control string. + * argList pointer to list of arguments. + * + * + * strDest is updated + * + * + * return the number of characters written, not including the terminating null + * return -1 if an error occurs. + * return -1 if count < destMax and the output string has been truncated + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +int vsnprintf_s(char *strDest, size_t destMax, size_t count, const char *format, va_list argList) +{ + int retVal; + + if (SECUREC_VSNPRINTF_PARAM_ERROR(format, strDest, destMax, count, SECUREC_STRING_MAX_LEN)) { + SECUREC_VSPRINTF_CLEAR_DEST(strDest, destMax, SECUREC_STRING_MAX_LEN); + SECUREC_ERROR_INVALID_PARAMTER("vsnprintf_s"); + return -1; + } + + if (destMax > count) { + retVal = SecVsnprintfImpl(strDest, count + 1, format, argList); + if (retVal == SECUREC_PRINTF_TRUNCATE) { /* To keep dest buffer not destroyed 2014.2.18 */ + /* The string has been truncated, return -1 */ + return -1; /* To skip error handler, return strlen(strDest) or -1 */ + } + } else { + retVal = SecVsnprintfImpl(strDest, destMax, format, argList); +#ifdef SECUREC_COMPATIBLE_WIN_FORMAT + if (retVal == SECUREC_PRINTF_TRUNCATE && count == (size_t)(-1)) { + return -1; + } +#endif + } + + if (retVal < 0) { + strDest[0] = '\0'; /* Empty the dest strDest */ + if (retVal == SECUREC_PRINTF_TRUNCATE) { + /* Buffer too small */ + SECUREC_ERROR_INVALID_RANGE("vsnprintf_s"); + } + SECUREC_ERROR_INVALID_PARAMTER("vsnprintf_s"); + return -1; + } + + return retVal; +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(vsnprintf_s); +#endif +#endif + +#if SECUREC_SNPRINTF_TRUNCATED +/* + * + * The vsnprintf_truncated_s function is equivalent to the vsnprintf function + * except for the parameter destMax/count and the explicit runtime-constraints violation + * The vsnprintf_truncated_s function takes a pointer to an argument list, then formats + * and writes up to count characters of the given data to the memory pointed + * to by strDest and appends a terminating null. + * + * + * strDest Storage location for the output. + * destMax The size of the strDest for output. + * the terminating NULL) + * format Format-control string. + * argList pointer to list of arguments. + * + * + * strDest is updated + * + * + * return the number of characters written, not including the terminating null + * return -1 if an error occurs. + * return destMax-1 if output string has been truncated + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +int vsnprintf_truncated_s(char *strDest, size_t destMax, const char *format, va_list argList) +{ + int retVal; + + if (SECUREC_VSPRINTF_PARAM_ERROR(format, strDest, destMax, SECUREC_STRING_MAX_LEN)) { + SECUREC_VSPRINTF_CLEAR_DEST(strDest, destMax, SECUREC_STRING_MAX_LEN); + SECUREC_ERROR_INVALID_PARAMTER("vsnprintf_truncated_s"); + return -1; + } + + retVal = SecVsnprintfImpl(strDest, destMax, format, argList); + if (retVal < 0) { + if (retVal == SECUREC_PRINTF_TRUNCATE) { + return (int)(destMax - 1); /* To skip error handler, return strlen(strDest) */ + } + strDest[0] = '\0'; /* Empty the dest strDest */ + SECUREC_ERROR_INVALID_PARAMTER("vsnprintf_truncated_s"); + return -1; + } + + return retVal; +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(vsnprintf_truncated_s); +#endif +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vsprintf_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vsprintf_s.c new file mode 100644 index 00000000..f50fa4a9 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vsprintf_s.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: vsprintf_s function + * Create: 2014-02-25 + */ + +#include "secureprintoutput.h" + +/* + * + * The vsprintf_s function is equivalent to the vsprintf function + * except for the parameter destMax and the explicit runtime-constraints violation + * The vsprintf_s function takes a pointer to an argument list, and then formats + * and writes the given data to the memory pointed to by strDest. + * The function differ from the non-secure versions only in that the secure + * versions support positional parameters. + * + * + * strDest Storage location for the output. + * destMax Size of strDest + * format Format specification. + * argList pointer to list of arguments + * + * + * strDest is updated + * + * + * return the number of characters written, not including the terminating null character, + * return -1 if an error occurs. + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +int vsprintf_s(char *strDest, size_t destMax, const char *format, va_list argList) +{ + int retVal; /* If initialization causes e838 */ + + if (SECUREC_VSPRINTF_PARAM_ERROR(format, strDest, destMax, SECUREC_STRING_MAX_LEN)) { + SECUREC_VSPRINTF_CLEAR_DEST(strDest, destMax, SECUREC_STRING_MAX_LEN); + SECUREC_ERROR_INVALID_PARAMTER("vsprintf_s"); + return -1; + } + + retVal = SecVsnprintfImpl(strDest, destMax, format, argList); + if (retVal < 0) { + strDest[0] = '\0'; + if (retVal == SECUREC_PRINTF_TRUNCATE) { + /* Buffer is too small */ + SECUREC_ERROR_INVALID_RANGE("vsprintf_s"); + } + SECUREC_ERROR_INVALID_PARAMTER("vsprintf_s"); + return -1; + } + + return retVal; +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(vsprintf_s); +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vsscanf_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vsscanf_s.c new file mode 100644 index 00000000..a19abe2b --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vsscanf_s.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: vsscanf_s function + * Create: 2014-02-25 + */ + +#include "secinput.h" +#if defined(SECUREC_VXWORKS_PLATFORM) && !SECUREC_IN_KERNEL && \ + (!defined(SECUREC_SYSAPI4VXWORKS) && !defined(SECUREC_CTYPE_MACRO_ADAPT)) +#include +#endif + +/* + * + * vsscanf_s + * + * + * + * The vsscanf_s function is equivalent to sscanf_s, with the variable argument list replaced by argList + * The vsscanf_s function reads data from buffer into the location given by + * each argument. Every argument must be a pointer to a variable with a type + * that corresponds to a type specifier in format. The format argument controls + * the interpretation of the input fields and has the same form and function + * as the format argument for the scanf function. + * If copying takes place between strings that overlap, the behavior is undefined. + * + * + * buffer Stored data + * format Format control string, see Format Specifications. + * argList pointer to list of arguments + * + * + * argList the converted value stored in user assigned address + * + * + * Each of these functions returns the number of fields successfully converted + * and assigned; the return value does not include fields that were read but + * not assigned. A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int vsscanf_s(const char *buffer, const char *format, va_list argList) +{ + size_t count; /* If initialization causes e838 */ + int retVal; + SecFileStream fStr; + + /* Validation section */ + if (buffer == NULL || format == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("vsscanf_s"); + return SECUREC_SCANF_EINVAL; + } + count = strlen(buffer); + if (count == 0 || count > SECUREC_STRING_MAX_LEN) { + SecClearDestBuf(buffer, format, argList); + SECUREC_ERROR_INVALID_PARAMTER("vsscanf_s"); + return SECUREC_SCANF_EINVAL; + } +#if defined(SECUREC_VXWORKS_PLATFORM) && !SECUREC_IN_KERNEL + /* + * On vxworks platform when buffer is white string, will set first %s argument to zero.Like following usage: + * " \v\f\t\r\n", "%s", str, strSize + * Do not check all character, just first and last character then consider it is white string + */ + if (isspace((int)(unsigned char)buffer[0]) != 0 && isspace((int)(unsigned char)buffer[count - 1]) != 0) { + SecClearDestBuf(buffer, format, argList); + } +#endif + SECUREC_FILE_STREAM_FROM_STRING(&fStr, buffer, count); + retVal = SecInputS(&fStr, format, argList); + if (retVal < 0) { + SECUREC_ERROR_INVALID_PARAMTER("vsscanf_s"); + return SECUREC_SCANF_EINVAL; + } + return retVal; +} +#if SECUREC_EXPORT_KERNEL_SYMBOL +EXPORT_SYMBOL(vsscanf_s); +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vswprintf_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vswprintf_s.c new file mode 100644 index 00000000..29715fc6 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vswprintf_s.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: vswprintf_s function + * Create: 2014-02-25 + */ + +#ifndef SECUREC_FOR_WCHAR +#define SECUREC_FOR_WCHAR +#endif + +#include "secureprintoutput.h" + +/* + * + * The vswprintf_s function is the wide-character equivalent of the vsprintf_s function + * + * + * strDest Storage location for the output. + * destMax Maximum number of characters to store + * format Format specification. + * argList pointer to list of arguments + * + * + * strDest is updated + * + * + * return the number of wide characters stored in strDest, not counting the terminating null wide character. + * return -1 if an error occurred. + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +int vswprintf_s(wchar_t *strDest, size_t destMax, const wchar_t *format, va_list argList) +{ + int retVal; /* If initialization causes e838 */ + if (SECUREC_VSPRINTF_PARAM_ERROR(format, strDest, destMax, SECUREC_WCHAR_STRING_MAX_LEN)) { + SECUREC_VSPRINTF_CLEAR_DEST(strDest, destMax, SECUREC_WCHAR_STRING_MAX_LEN); + SECUREC_ERROR_INVALID_PARAMTER("vswprintf_s"); + return -1; + } + + retVal = SecVswprintfImpl(strDest, destMax, format, argList); + if (retVal < 0) { + strDest[0] = L'\0'; + if (retVal == SECUREC_PRINTF_TRUNCATE) { + /* Buffer too small */ + SECUREC_ERROR_INVALID_RANGE("vswprintf_s"); + } + SECUREC_ERROR_INVALID_PARAMTER("vswprintf_s"); + return -1; + } + + return retVal; +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vswscanf_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vswscanf_s.c new file mode 100644 index 00000000..bab53a3e --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vswscanf_s.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: vswscanf_s function + * Create: 2014-02-25 + */ + +#ifndef SECUREC_FOR_WCHAR +#define SECUREC_FOR_WCHAR +#endif + +#include "secinput.h" + +SECUREC_INLINE size_t SecWcslen(const wchar_t *s) +{ + const wchar_t *end = s; + while (*end != L'\0') { + ++end; + } + return ((size_t)((end - s))); +} + +/* + * + * The vswscanf_s function is the wide-character equivalent of the vsscanf_s function + * The vsscanf_s function reads data from buffer into the location given by + * each argument. Every argument must be a pointer to a variable with a type + * that corresponds to a type specifier in format. + * The format argument controls the interpretation of the input fields and + * has the same form and function as the format argument for the scanf function. + * If copying takes place between strings that overlap, the behavior is undefined. + * + * + * buffer Stored data + * format Format control string, see Format Specifications. + * argList pointer to list of arguments + * + * + * argList the converted value stored in user assigned address + * + * + * Each of these functions returns the number of fields successfully converted + * and assigned; the return value does not include fields that were read but + * not assigned. A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int vswscanf_s(const wchar_t *buffer, const wchar_t *format, va_list argList) +{ + size_t count; /* If initialization causes e838 */ + SecFileStream fStr; + int retVal; + + /* Validation section */ + if (buffer == NULL || format == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("vswscanf_s"); + return SECUREC_SCANF_EINVAL; + } + count = SecWcslen(buffer); + if (count == 0 || count > SECUREC_WCHAR_STRING_MAX_LEN) { + SecClearDestBufW(buffer, format, argList); + SECUREC_ERROR_INVALID_PARAMTER("vswscanf_s"); + return SECUREC_SCANF_EINVAL; + } + SECUREC_FILE_STREAM_FROM_STRING(&fStr, (const char *)buffer, count * sizeof(wchar_t)); + retVal = SecInputSW(&fStr, format, argList); + if (retVal < 0) { + SECUREC_ERROR_INVALID_PARAMTER("vswscanf_s"); + return SECUREC_SCANF_EINVAL; + } + return retVal; +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vwscanf_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vwscanf_s.c new file mode 100644 index 00000000..b39f9bc7 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/vwscanf_s.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: vwscanf_s function + * Create: 2014-02-25 + */ + +#ifndef SECUREC_FOR_WCHAR +#define SECUREC_FOR_WCHAR +#endif + +#include "secinput.h" + +/* + * + * The vwscanf_s function is the wide-character equivalent of the vscanf_s function + * The vwscanf_s function is the wide-character version of vscanf_s. The + * function reads data from the standard input stream stdin and writes the + * data into the location that's given by argument. Each argument must be a + * pointer to a variable of a type that corresponds to a type specifier in + * format. If copying occurs between strings that overlap, the behavior is + * undefined. + * + * + * format Format control string. + * argList pointer to list of arguments + * + * + * argList the converted value stored in user assigned address + * + * + * Returns the number of fields successfully converted and assigned; + * the return value does not include fields that were read but not assigned. + * A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int vwscanf_s(const wchar_t *format, va_list argList) +{ + int retVal; /* If initialization causes e838 */ + SecFileStream fStr; + SECUREC_FILE_STREAM_FROM_STDIN(&fStr); + if (format == NULL || fStr.pf == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("vwscanf_s"); + return SECUREC_SCANF_EINVAL; + } + + SECUREC_LOCK_STDIN(0, fStr.pf); + retVal = SecInputSW(&fStr, format, argList); + SECUREC_UNLOCK_STDIN(0, fStr.pf); + if (retVal < 0) { + SECUREC_ERROR_INVALID_PARAMTER("vwscanf_s"); + return SECUREC_SCANF_EINVAL; + } + + return retVal; +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wcscat_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wcscat_s.c new file mode 100644 index 00000000..fa7d847c --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wcscat_s.c @@ -0,0 +1,107 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: wcscat_s function + * Create: 2014-02-25 + */ + +#include "securecutil.h" + +/* + * Befor this function, the basic parameter checking has been done + */ +SECUREC_INLINE errno_t SecDoCatW(wchar_t *strDest, size_t destMax, const wchar_t *strSrc) +{ + size_t destLen; + size_t srcLen; + size_t maxCount; /* Store the maximum available count */ + + /* To calculate the length of a wide character, the parameter must be a wide character */ + SECUREC_CALC_WSTR_LEN(strDest, destMax, &destLen); + maxCount = destMax - destLen; + SECUREC_CALC_WSTR_LEN(strSrc, maxCount, &srcLen); + + if (SECUREC_CAT_STRING_IS_OVERLAP(strDest, destLen, strSrc, srcLen)) { + strDest[0] = L'\0'; + if (strDest + destLen <= strSrc && destLen == destMax) { + SECUREC_ERROR_INVALID_PARAMTER("wcscat_s"); + return EINVAL_AND_RESET; + } + SECUREC_ERROR_BUFFER_OVERLAP("wcscat_s"); + return EOVERLAP_AND_RESET; + } + if (srcLen + destLen >= destMax || strDest == strSrc) { + strDest[0] = L'\0'; + if (destLen == destMax) { + SECUREC_ERROR_INVALID_PARAMTER("wcscat_s"); + return EINVAL_AND_RESET; + } + SECUREC_ERROR_INVALID_RANGE("wcscat_s"); + return ERANGE_AND_RESET; + } + /* Copy single character length include \0 */ + SECUREC_MEMCPY_WARP_OPT(strDest + destLen, strSrc, (srcLen + 1) * sizeof(wchar_t)); + return EOK; +} + +/* + * + * The wcscat_s function appends a copy of the wide string pointed to by strSrc +* (including the terminating null wide character) + * to the end of the wide string pointed to by strDest. + * The arguments and return value of wcscat_s are wide-character strings. + * + * The wcscat_s function appends strSrc to strDest and terminates the resulting + * string with a null character. The initial character of strSrc overwrites the + * terminating null character of strDest. wcscat_s will return EOVERLAP_AND_RESET if the + * source and destination strings overlap. + * + * Note that the second parameter is the total size of the buffer, not the + * remaining size. + * + * + * strDest Null-terminated destination string buffer. + * destMax Size of the destination string buffer. + * strSrc Null-terminated source string buffer. + * + * + * strDest is updated + * + * + * EOK Success + * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_WCHAR_STRING_MAX_LEN + * EINVAL_AND_RESET (strDest unterminated and all other parameters are valid) or + * (strDest != NULL and strSrc is NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_STRING_MAX_LEN) + * ERANGE destMax > SECUREC_WCHAR_STRING_MAX_LEN or destMax is 0 + * ERANGE_AND_RESET strDest have not enough space and all other parameters are valid and not overlap + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and all parameters are valid + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +errno_t wcscat_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc) +{ + if (destMax == 0 || destMax > SECUREC_WCHAR_STRING_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("wcscat_s"); + return ERANGE; + } + + if (strDest == NULL || strSrc == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("wcscat_s"); + if (strDest != NULL) { + strDest[0] = L'\0'; + return EINVAL_AND_RESET; + } + return EINVAL; + } + + return SecDoCatW(strDest, destMax, strSrc); +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wcscpy_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wcscpy_s.c new file mode 100644 index 00000000..8c4a4af8 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wcscpy_s.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: wcscpy_s function + * Create: 2014-02-25 + */ + +#include "securecutil.h" + +SECUREC_INLINE errno_t SecDoCpyW(wchar_t *strDest, size_t destMax, const wchar_t *strSrc) +{ + size_t srcStrLen; + SECUREC_CALC_WSTR_LEN(strSrc, destMax, &srcStrLen); + + if (srcStrLen == destMax) { + strDest[0] = L'\0'; + SECUREC_ERROR_INVALID_RANGE("wcscpy_s"); + return ERANGE_AND_RESET; + } + if (strDest == strSrc) { + return EOK; + } + + if (SECUREC_STRING_NO_OVERLAP(strDest, strSrc, srcStrLen)) { + /* Performance optimization, srcStrLen is single character length include '\0' */ + SECUREC_MEMCPY_WARP_OPT(strDest, strSrc, (srcStrLen + 1) * sizeof(wchar_t)); + return EOK; + } else { + strDest[0] = L'\0'; + SECUREC_ERROR_BUFFER_OVERLAP("wcscpy_s"); + return EOVERLAP_AND_RESET; + } +} + +/* + * + * The wcscpy_s function copies the wide string pointed to by strSrc + * (including the terminating null wide character) into the array pointed to by strDest + + * + * strDest Destination string buffer + * destMax Size of the destination string buffer. + * strSrc Null-terminated source string buffer. + * + * + * strDest is updated. + * + * + * EOK Success + * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_WCHAR_STRING_MAX_LEN + * EINVAL_AND_RESET strDest != NULL and strSrc is NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_STRING_MAX_LEN + * ERANGE destMax > SECUREC_WCHAR_STRING_MAX_LEN or destMax is 0 + * ERANGE_AND_RESET destMax <= length of strSrc and strDest != strSrc + * and strDest != NULL and strSrc != NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_STRING_MAX_LEN and not overlap + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and destMax != 0 + * and destMax <= SECUREC_WCHAR_STRING_MAX_LEN + * and strDest != NULL and strSrc !=NULL and strDest != strSrc + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +errno_t wcscpy_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc) +{ + if (destMax == 0 || destMax > SECUREC_WCHAR_STRING_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("wcscpy_s"); + return ERANGE; + } + if (strDest == NULL || strSrc == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("wcscpy_s"); + if (strDest != NULL) { + strDest[0] = L'\0'; + return EINVAL_AND_RESET; + } + return EINVAL; + } + return SecDoCpyW(strDest, destMax, strSrc); +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncat_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncat_s.c new file mode 100644 index 00000000..33e53a32 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncat_s.c @@ -0,0 +1,113 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: wcsncat_s function + * Create: 2014-02-25 + */ + +#include "securecutil.h" + +/* + * Befor this function, the basic parameter checking has been done + */ +SECUREC_INLINE errno_t SecDoCatLimitW(wchar_t *strDest, size_t destMax, const wchar_t *strSrc, size_t count) +{ + /* To calculate the length of a wide character, the parameter must be a wide character */ + size_t destLen; + size_t srcLen; + SECUREC_CALC_WSTR_LEN(strDest, destMax, &destLen); + SECUREC_CALC_WSTR_LEN(strSrc, count, &srcLen); + + if (SECUREC_CAT_STRING_IS_OVERLAP(strDest, destLen, strSrc, srcLen)) { + strDest[0] = L'\0'; + if (strDest + destLen <= strSrc && destLen == destMax) { + SECUREC_ERROR_INVALID_PARAMTER("wcsncat_s"); + return EINVAL_AND_RESET; + } + SECUREC_ERROR_BUFFER_OVERLAP("wcsncat_s"); + return EOVERLAP_AND_RESET; + } + if (srcLen + destLen >= destMax || strDest == strSrc) { + strDest[0] = L'\0'; + if (destLen == destMax) { + SECUREC_ERROR_INVALID_PARAMTER("wcsncat_s"); + return EINVAL_AND_RESET; + } + SECUREC_ERROR_INVALID_RANGE("wcsncat_s"); + return ERANGE_AND_RESET; + } + SECUREC_MEMCPY_WARP_OPT(strDest + destLen, strSrc, srcLen * sizeof(wchar_t)); /* no terminator */ + *(strDest + destLen + srcLen) = L'\0'; + return EOK; +} + +/* + * + * The wcsncat_s function appends not more than n successive wide characters + * (not including the terminating null wide character) + * from the array pointed to by strSrc to the end of the wide string pointed to by strDest. + * + * The wcsncat_s function try to append the first D characters of strSrc to + * the end of strDest, where D is the lesser of count and the length of strSrc. + * If appending those D characters will fit within strDest (whose size is + * given as destMax) and still leave room for a null terminator, then those + * characters are appended, starting at the original terminating null of + * strDest, and a new terminating null is appended; otherwise, strDest[0] is + * set to the null character. + * + * + * strDest Null-terminated destination string. + * destMax Size of the destination buffer. + * strSrc Null-terminated source string. + * count Number of character to append, or truncate. + * + * + * strDest is updated + * + * + * EOK Success + * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_WCHAR_STRING_MAX_LEN + * EINVAL_AND_RESET (strDest unterminated and all other parameters are valid) or + * (strDest != NULL and strSrc is NULL and destMax != 0 and + * destMax <= SECUREC_WCHAR_STRING_MAX_LEN) + * ERANGE destMax > SECUREC_WCHAR_STRING_MAX_LEN or destMax is 0 + * ERANGE_AND_RESET strDest have not enough space and all other parameters are valid and not overlap + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and all parameters are valid + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +errno_t wcsncat_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc, size_t count) +{ + if (destMax == 0 || destMax > SECUREC_WCHAR_STRING_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("wcsncat_s"); + return ERANGE; + } + if (strDest == NULL || strSrc == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("wcsncat_s"); + if (strDest != NULL) { + strDest[0] = L'\0'; + return EINVAL_AND_RESET; + } + return EINVAL; + } + if (count > SECUREC_WCHAR_STRING_MAX_LEN) { +#ifdef SECUREC_COMPATIBLE_WIN_FORMAT + if (count == ((size_t)(-1))) { + /* Windows internal functions may pass in -1 when calling this function */ + return SecDoCatLimitW(strDest, destMax, strSrc, destMax); + } +#endif + strDest[0] = L'\0'; + SECUREC_ERROR_INVALID_RANGE("wcsncat_s"); + return ERANGE_AND_RESET; + } + return SecDoCatLimitW(strDest, destMax, strSrc, count); +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncpy_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncpy_s.c new file mode 100644 index 00000000..463f90e1 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncpy_s.c @@ -0,0 +1,107 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: wcsncpy_s function + * Create: 2014-02-25 + */ + +#include "securecutil.h" + +SECUREC_INLINE errno_t SecDoCpyLimitW(wchar_t *strDest, size_t destMax, const wchar_t *strSrc, size_t count) +{ + size_t srcStrLen; + if (count < destMax) { + SECUREC_CALC_WSTR_LEN(strSrc, count, &srcStrLen); + } else { + SECUREC_CALC_WSTR_LEN(strSrc, destMax, &srcStrLen); + } + if (srcStrLen == destMax) { + strDest[0] = L'\0'; + SECUREC_ERROR_INVALID_RANGE("wcsncpy_s"); + return ERANGE_AND_RESET; + } + if (strDest == strSrc) { + return EOK; + } + if (SECUREC_STRING_NO_OVERLAP(strDest, strSrc, srcStrLen)) { + /* Performance optimization srcStrLen not include '\0' */ + SECUREC_MEMCPY_WARP_OPT(strDest, strSrc, srcStrLen * sizeof(wchar_t)); + *(strDest + srcStrLen) = L'\0'; + return EOK; + } else { + strDest[0] = L'\0'; + SECUREC_ERROR_BUFFER_OVERLAP("wcsncpy_s"); + return EOVERLAP_AND_RESET; + } +} + +/* + * + * The wcsncpy_s function copies not more than n successive wide characters + * (not including the terminating null wide character) + * from the array pointed to by strSrc to the array pointed to by strDest + * + * + * strDest Destination string. + * destMax The size of the destination string, in characters. + * strSrc Source string. + * count Number of characters to be copied. + * + * + * strDest is updated + * + * + * EOK Success + * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_WCHAR_STRING_MAX_LEN + * EINVAL_AND_RESET strDest != NULL and strSrc is NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_STRING_MAX_LEN + * ERANGE destMax > SECUREC_WCHAR_STRING_MAX_LEN or destMax is 0 + * ERANGE_AND_RESET count > SECUREC_WCHAR_STRING_MAX_LEN or + * (destMax <= length of strSrc and destMax <= count and strDest != strSrc + * and strDest != NULL and strSrc != NULL and destMax != 0 and + * destMax <= SECUREC_WCHAR_STRING_MAX_LEN and not overlap) + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and all parameters are valid + * + * + * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid + */ +errno_t wcsncpy_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc, size_t count) +{ + if (destMax == 0 || destMax > SECUREC_WCHAR_STRING_MAX_LEN) { + SECUREC_ERROR_INVALID_RANGE("wcsncpy_s"); + return ERANGE; + } + if (strDest == NULL || strSrc == NULL) { + SECUREC_ERROR_INVALID_PARAMTER("wcsncpy_s"); + if (strDest != NULL) { + strDest[0] = L'\0'; + return EINVAL_AND_RESET; + } + return EINVAL; + } + if (count > SECUREC_WCHAR_STRING_MAX_LEN) { +#ifdef SECUREC_COMPATIBLE_WIN_FORMAT + if (count == (size_t)(-1)) { + return SecDoCpyLimitW(strDest, destMax, strSrc, destMax - 1); + } +#endif + strDest[0] = L'\0'; /* Clear dest string */ + SECUREC_ERROR_INVALID_RANGE("wcsncpy_s"); + return ERANGE_AND_RESET; + } + + if (count == 0) { + strDest[0] = L'\0'; + return EOK; + } + + return SecDoCpyLimitW(strDest, destMax, strSrc, count); +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wcstok_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wcstok_s.c new file mode 100644 index 00000000..063ca691 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wcstok_s.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: wcstok_s function + * Create: 2014-02-25 + */ + +#include "securecutil.h" + +SECUREC_INLINE int SecIsInDelimitW(wchar_t ch, const wchar_t *strDelimit) +{ + const wchar_t *ctl = strDelimit; + while (*ctl != L'\0' && *ctl != ch) { + ++ctl; + } + return (int)(*ctl != L'\0'); +} + +/* + * Find beginning of token (skip over leading delimiters). + * Note that there is no token if this loop sets string to point to the terminal null. + */ +SECUREC_INLINE wchar_t *SecFindBeginW(wchar_t *strToken, const wchar_t *strDelimit) +{ + wchar_t *token = strToken; + while (*token != L'\0') { + if (SecIsInDelimitW(*token, strDelimit) != 0) { + ++token; + continue; + } + /* Don't find any delimiter in string header, break the loop */ + break; + } + return token; +} + +/* + * Find the end of the token. If it is not the end of the string, put a null there. + */ +SECUREC_INLINE wchar_t *SecFindRestW(wchar_t *strToken, const wchar_t *strDelimit) +{ + wchar_t *token = strToken; + while (*token != L'\0') { + if (SecIsInDelimitW(*token, strDelimit) != 0) { + /* Find a delimiter, set string terminator */ + *token = L'\0'; + ++token; + break; + } + ++token; + } + return token; +} + +/* + * Update Token wide character function + */ +SECUREC_INLINE wchar_t *SecUpdateTokenW(wchar_t *strToken, const wchar_t *strDelimit, wchar_t **context) +{ + /* Point to updated position. Record string position for next search in the context */ + *context = SecFindRestW(strToken, strDelimit); + /* Determine if a token has been found */ + if (*context == strToken) { + return NULL; + } + return strToken; +} + +/* + * + * wcstok_s + * + * + * + * The wcstok_s function is the wide-character equivalent of the strtok_s function + * + * + * strToken String containing token or tokens. + * strDelimit Set of delimiter characters. + * context Used to store position information between calls to + * wcstok_s. + * + * + * context is updated + * + * The wcstok_s function is the wide-character equivalent of the strtok_s function + */ +wchar_t *wcstok_s(wchar_t *strToken, const wchar_t *strDelimit, wchar_t **context) +{ + wchar_t *orgToken = strToken; + /* Validation section */ + if (context == NULL || strDelimit == NULL) { + return NULL; + } + if (orgToken == NULL && *context == NULL) { + return NULL; + } + /* If string==NULL, continue with previous string */ + if (orgToken == NULL) { + orgToken = *context; + } + orgToken = SecFindBeginW(orgToken, strDelimit); + return SecUpdateTokenW(orgToken, strDelimit, context); +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wmemcpy_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wmemcpy_s.c new file mode 100644 index 00000000..2f2b4a33 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wmemcpy_s.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: wmemcpy_s function + * Create: 2014-02-25 + */ +/* + * [Standardize-exceptions] Use unsafe function: Portability + * [reason] Use unsafe function to implement security function to maintain platform compatibility. + * And sufficient input validation is performed before calling + */ + +#include "securecutil.h" + +/* + * + * The wmemcpy_s function copies n successive wide characters + * from the object pointed to by src into the object pointed to by dest.t. + * + * + * dest Destination buffer. + * destMax Size of the destination buffer. + * src Buffer to copy from. + * count Number of characters to copy. + * + * + * dest buffer is updated. + * + * + * EOK Success + * EINVAL dest is NULL and destMax != 0 and count <= destMax + * and destMax <= SECUREC_WCHAR_MEM_MAX_LEN + * EINVAL_AND_RESET dest != NULL and src is NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_MEM_MAX_LEN and count <= destMax + * ERANGE destMax > SECUREC_WCHAR_MEM_MAX_LEN or destMax is 0 or + * (count > destMax and dest is NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_MEM_MAX_LEN) + * ERANGE_AND_RESET count > destMax and dest != NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_MEM_MAX_LEN + * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and + * count <= destMax destMax != 0 and destMax <= SECUREC_WCHAR_MEM_MAX_LEN + * and dest != NULL and src != NULL and dest != src + * + * if an error occurred, dest will be filled with 0 when dest and destMax valid . + * If the source and destination overlap, the behavior of wmemcpy_s is undefined. + * Use wmemmove_s to handle overlapping regions. + */ +errno_t wmemcpy_s(wchar_t *dest, size_t destMax, const wchar_t *src, size_t count) +{ + if (destMax == 0 || destMax > SECUREC_WCHAR_MEM_MAX_LEN) { + SECUREC_ERROR_INVALID_PARAMTER("wmemcpy_s"); + return ERANGE; + } + if (count > destMax) { + SECUREC_ERROR_INVALID_PARAMTER("wmemcpy_s"); + if (dest != NULL) { + (void)SECUREC_MEMSET_FUNC_OPT(dest, 0, destMax * sizeof(wchar_t)); + return ERANGE_AND_RESET; + } + return ERANGE; + } + return memcpy_s(dest, destMax * sizeof(wchar_t), src, count * sizeof(wchar_t)); +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wmemmove_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wmemmove_s.c new file mode 100644 index 00000000..88bb97b9 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wmemmove_s.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: wmemmove_s function + * Create: 2014-02-25 + */ +/* + * [Standardize-exceptions] Use unsafe function: Portability + * [reason] Use unsafe function to implement security function to maintain platform compatibility. + * And sufficient input validation is performed before calling + */ + +#include "securecutil.h" + +/* + * + * The wmemmove_s function copies n successive wide characters from the object pointed + * to by src into the object pointed to by dest. + * + * + * dest Destination buffer. + * destMax Size of the destination buffer. + * src Source object. + * count Number of bytes or character to copy. + * + * + * dest is updated. + * + * + * EOK Success + * EINVAL dest is NULL and destMax != 0 and count <= destMax + * and destMax <= SECUREC_WCHAR_MEM_MAX_LEN + * EINVAL_AND_RESET dest != NULL and src is NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_MEM_MAX_LEN and count <= destMax + * ERANGE destMax > SECUREC_WCHAR_MEM_MAX_LEN or destMax is 0 or + * (count > destMax and dest is NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_MEM_MAX_LEN) + * ERANGE_AND_RESET count > destMax and dest != NULL and destMax != 0 + * and destMax <= SECUREC_WCHAR_MEM_MAX_LEN + * + * + * If an error occurred, dest will be filled with 0 when dest and destMax valid. + * If some regions of the source area and the destination overlap, wmemmove_s + * ensures that the original source bytes in the overlapping region are copied + * before being overwritten + */ +errno_t wmemmove_s(wchar_t *dest, size_t destMax, const wchar_t *src, size_t count) +{ + if (destMax == 0 || destMax > SECUREC_WCHAR_MEM_MAX_LEN) { + SECUREC_ERROR_INVALID_PARAMTER("wmemmove_s"); + return ERANGE; + } + if (count > destMax) { + SECUREC_ERROR_INVALID_PARAMTER("wmemmove_s"); + if (dest != NULL) { + (void)SECUREC_MEMSET_FUNC_OPT(dest, 0, destMax * sizeof(wchar_t)); + return ERANGE_AND_RESET; + } + return ERANGE; + } + return memmove_s(dest, destMax * sizeof(wchar_t), src, count * sizeof(wchar_t)); +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wscanf_s.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wscanf_s.c new file mode 100644 index 00000000..badb04ef --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/libboundscheck_v1.1.16/src/wscanf_s.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. + * Licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + * Description: wscanf_s function + * Create: 2014-02-25 + */ + +#include "securec.h" + +/* + * + * + * The wscanf_s function is the wide-character equivalent of the scanf_s function + * The wscanf_s function reads data from the standard input stream stdin and + * writes the data into the location that's given by argument. Each argument + * must be a pointer to a variable of a type that corresponds to a type specifier + * in format. If copying occurs between strings that overlap, the behavior is + * undefined. + * + * + * format Format control string. + * ... Optional arguments. + * + * + * ... the converted value stored in user assigned address + * + * + * Returns the number of fields successfully converted and assigned; + * the return value does not include fields that were read but not assigned. + * A return value of 0 indicates that no fields were assigned. + * return -1 if an error occurs. + */ +int wscanf_s(const wchar_t *format, ...) +{ + int ret; /* If initialization causes e838 */ + va_list argList; + + va_start(argList, format); + ret = vwscanf_s(format, argList); + va_end(argList); + (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ + + return ret; +} + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/loaderboot/loader.bin b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/hisilicon/loaderboot/loader.bin new file mode 100644 index 0000000000000000000000000000000000000000..48314a7a20ccb468fbcfe52b943847785e90e128 GIT binary patch literal 5096 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keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + + #include +#endif + +extern void xPortSysTickHandler(void); + +/* Convert from CMSIS type osPriority to FreeRTOS priority number */ +static unsigned portBASE_TYPE makeFreeRtosPriority (osPriority priority) +{ + unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY; + + if (priority != osPriorityError) { + fpriority += (priority - osPriorityIdle); + } + + return fpriority; +} + +#if (INCLUDE_uxTaskPriorityGet == 1) +/* Convert from FreeRTOS priority number to CMSIS type osPriority */ +static osPriority makeCmsisPriority (unsigned portBASE_TYPE fpriority) +{ + osPriority priority = osPriorityError; + + if ((fpriority - tskIDLE_PRIORITY) <= (osPriorityRealtime - osPriorityIdle)) { + priority = (osPriority)((int)osPriorityIdle + (int)(fpriority - tskIDLE_PRIORITY)); + } + + return priority; +} +#endif + + +/* Determine whether we are in thread mode or handler mode. */ +static int inHandlerMode (void) +{ + return __get_IPSR() != 0; +} + +/*********************** Kernel Control Functions *****************************/ +/** +* @brief Initialize the RTOS Kernel for creating objects. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS. +*/ +osStatus osKernelInitialize (void); + +/** +* @brief Start the RTOS Kernel with executing the specified thread. +* @param thread_def thread definition referenced with \ref osThread. +* @param argument pointer that is passed to the thread function as start argument. +* @retval status code that indicates the execution status of the function +* @note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +*/ +osStatus osKernelStart (void) +{ + vTaskStartScheduler(); + + return osOK; +} + +/** +* @brief Check if the RTOS kernel is already started +* @param None +* @retval (0) RTOS is not started +* (1) RTOS is started +* (-1) if this feature is disabled in FreeRTOSConfig.h +* @note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. +*/ +int32_t osKernelRunning(void) +{ +#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + if (xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED) + return 0; + else + return 1; +#else + return (-1); +#endif +} + +#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available +/** +* @brief Get the value of the Kernel SysTick timer +* @param None +* @retval None +* @note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS. +*/ +uint32_t osKernelSysTick(void) +{ + if (inHandlerMode()) { + return xTaskGetTickCountFromISR(); + } + else { + return xTaskGetTickCount(); + } +} +#endif // System Timer available +/*********************** Thread Management *****************************/ +/** +* @brief Create a thread and add it to Active Threads and set it to state READY. +* @param thread_def thread definition referenced with \ref osThread. +* @param argument pointer that is passed to the thread function as start argument. +* @retval thread ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +*/ +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) +{ + TaskHandle_t handle; + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + if((thread_def->buffer != NULL) && (thread_def->controlblock != NULL)) { + handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), + thread_def->buffer, thread_def->controlblock); + } + else { + if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), + &handle) != pdPASS) { + return NULL; + } + } +#elif( configSUPPORT_STATIC_ALLOCATION == 1 ) + + handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), + thread_def->buffer, thread_def->controlblock); +#else + if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), + &handle) != pdPASS) { + return NULL; + } +#endif + + return handle; +} + +/** +* @brief Return the thread ID of the current running thread. +* @retval thread ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS. +*/ +osThreadId osThreadGetId (void) +{ +#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + return xTaskGetCurrentTaskHandle(); +#else + return NULL; +#endif +} + +/** +* @brief Terminate execution of a thread and remove it from Active Threads. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS. +*/ +osStatus osThreadTerminate (osThreadId thread_id) +{ +#if (INCLUDE_vTaskDelete == 1) + vTaskDelete(thread_id); + return osOK; +#else + return osErrorOS; +#endif +} + +/** +* @brief Pass control to next thread that is in state \b READY. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS. +*/ +osStatus osThreadYield (void) +{ + taskYIELD(); + + return osOK; +} + +/** +* @brief Change priority of an active thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @param priority new priority value for the thread function. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS. +*/ +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority) +{ +#if (INCLUDE_vTaskPrioritySet == 1) + vTaskPrioritySet(thread_id, makeFreeRtosPriority(priority)); + return osOK; +#else + return osErrorOS; +#endif +} + +/** +* @brief Get current priority of an active thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval current priority value of the thread function. +* @note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS. +*/ +osPriority osThreadGetPriority (osThreadId thread_id) +{ +#if (INCLUDE_uxTaskPriorityGet == 1) + if (inHandlerMode()) + { + return makeCmsisPriority(uxTaskPriorityGetFromISR(thread_id)); + } + else + { + return makeCmsisPriority(uxTaskPriorityGet(thread_id)); + } +#else + return osPriorityError; +#endif +} + +/*********************** Generic Wait Functions *******************************/ +/** +* @brief Wait for Timeout (Time Delay) +* @param millisec time delay value +* @retval status code that indicates the execution status of the function. +*/ +osStatus osDelay (uint32_t millisec) +{ +#if INCLUDE_vTaskDelay + TickType_t ticks = millisec / portTICK_PERIOD_MS; + + vTaskDelay(ticks ? ticks : 1); /* Minimum delay = 1 tick */ + + return osOK; +#else + (void) millisec; + + return osErrorResource; +#endif +} + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) /* Generic Wait available */ +/** +* @brief Wait for Signal, Message, Mail, or Timeout +* @param millisec timeout value or 0 in case of no time-out +* @retval event that contains signal, message, or mail information or error code. +* @note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS. +*/ +osEvent osWait (uint32_t millisec); + +#endif /* Generic Wait available */ + +/*********************** Timer Management Functions ***************************/ +/** +* @brief Create a timer. +* @param timer_def timer object referenced with \ref osTimer. +* @param type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +* @param argument argument to the timer call back function. +* @retval timer ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS. +*/ +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) +{ +#if (configUSE_TIMERS == 1) + +#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + if(timer_def->controlblock != NULL) { + return xTimerCreateStatic((const char *)"", + 1, // period should be filled when starting the Timer using osTimerStart + (type == osTimerPeriodic) ? pdTRUE : pdFALSE, + (void *) argument, + (TaskFunction_t)timer_def->ptimer, + (StaticTimer_t *)timer_def->controlblock); + } + else { + return xTimerCreate((const char *)"", + 1, // period should be filled when starting the Timer using osTimerStart + (type == osTimerPeriodic) ? pdTRUE : pdFALSE, + (void *) argument, + (TaskFunction_t)timer_def->ptimer); + } +#elif( configSUPPORT_STATIC_ALLOCATION == 1 ) + return xTimerCreateStatic((const char *)"", + 1, // period should be filled when starting the Timer using osTimerStart + (type == osTimerPeriodic) ? pdTRUE : pdFALSE, + (void *) argument, + (TaskFunction_t)timer_def->ptimer, + (StaticTimer_t *)timer_def->controlblock); +#else + return xTimerCreate((const char *)"", + 1, // period should be filled when starting the Timer using osTimerStart + (type == osTimerPeriodic) ? pdTRUE : pdFALSE, + (void *) argument, + (TaskFunction_t)timer_def->ptimer); +#endif + +#else + return NULL; +#endif +} + +/** +* @brief Start or restart a timer. +* @param timer_id timer ID obtained by \ref osTimerCreate. +* @param millisec time delay value of the timer. +* @retval status code that indicates the execution status of the function +* @note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS. +*/ +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec) +{ + osStatus result = osOK; +#if (configUSE_TIMERS == 1) + portBASE_TYPE taskWoken = pdFALSE; + TickType_t ticks = millisec / portTICK_PERIOD_MS; + + if (ticks == 0) + ticks = 1; + + if (inHandlerMode()) + { + if (xTimerChangePeriodFromISR(timer_id, ticks, &taskWoken) != pdPASS) + { + result = osErrorOS; + } + else + { + portEND_SWITCHING_ISR(taskWoken); + } + } + else + { + if (xTimerChangePeriod(timer_id, ticks, 0) != pdPASS) + result = osErrorOS; + } + +#else + result = osErrorOS; +#endif + return result; +} + +/** +* @brief Stop a timer. +* @param timer_id timer ID obtained by \ref osTimerCreate +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS. +*/ +osStatus osTimerStop (osTimerId timer_id) +{ + osStatus result = osOK; +#if (configUSE_TIMERS == 1) + portBASE_TYPE taskWoken = pdFALSE; + + if (inHandlerMode()) { + if (xTimerStopFromISR(timer_id, &taskWoken) != pdPASS) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else { + if (xTimerStop(timer_id, 0) != pdPASS) { + result = osErrorOS; + } + } +#else + result = osErrorOS; +#endif + return result; +} + +/** +* @brief Delete a timer. +* @param timer_id timer ID obtained by \ref osTimerCreate +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS. +*/ +osStatus osTimerDelete (osTimerId timer_id) +{ +osStatus result = osOK; + +#if (configUSE_TIMERS == 1) + + if (inHandlerMode()) { + return osErrorISR; + } + else { + if ((xTimerDelete(timer_id, osWaitForever )) != pdPASS) { + result = osErrorOS; + } + } + +#else + result = osErrorOS; +#endif + + return result; +} + +/*************************** Signal Management ********************************/ +/** +* @brief Set the specified Signal Flags of an active thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @param signals specifies the signal flags of the thread that should be set. +* @retval previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +* @note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. +*/ +int32_t osSignalSet (osThreadId thread_id, int32_t signal) +{ +#if( configUSE_TASK_NOTIFICATIONS == 1 ) + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + uint32_t ulPreviousNotificationValue = 0; + + if (inHandlerMode()) + { + if(xTaskGenericNotifyFromISR( thread_id , (uint32_t)signal, eSetBits, &ulPreviousNotificationValue, &xHigherPriorityTaskWoken ) != pdPASS ) + return 0x80000000; + + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } + else if(xTaskGenericNotify( thread_id , (uint32_t)signal, eSetBits, &ulPreviousNotificationValue) != pdPASS ) + return 0x80000000; + + return ulPreviousNotificationValue; +#else + (void) thread_id; + (void) signal; + + return 0x80000000; /* Task Notification not supported */ +#endif +} + +/** +* @brief Clear the specified Signal Flags of an active thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @param signals specifies the signal flags of the thread that shall be cleared. +* @retval previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +* @note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS. +*/ +int32_t osSignalClear (osThreadId thread_id, int32_t signal); + +/** +* @brief Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +* @param signals wait until all specified signal flags set or 0 for any single signal flag. +* @param millisec timeout value or 0 in case of no time-out. +* @retval event flag information or error code. +* @note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS. +*/ +osEvent osSignalWait (int32_t signals, uint32_t millisec) +{ + osEvent ret; + +#if( configUSE_TASK_NOTIFICATIONS == 1 ) + + TickType_t ticks; + + ret.value.signals = 0; + ticks = 0; + if (millisec == osWaitForever) { + ticks = portMAX_DELAY; + } + else if (millisec != 0) { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + } + + if (inHandlerMode()) + { + ret.status = osErrorISR; /*Not allowed in ISR*/ + } + else + { + if(xTaskNotifyWait( 0,(uint32_t) signals, (uint32_t *)&ret.value.signals, ticks) != pdTRUE) + { + if(ticks == 0) ret.status = osOK; + else ret.status = osEventTimeout; + } + else if(ret.value.signals < 0) + { + ret.status = osErrorValue; + } + else ret.status = osEventSignal; + } +#else + (void) signals; + (void) millisec; + + ret.status = osErrorOS; /* Task Notification not supported */ +#endif + + return ret; +} + +/**************************** Mutex Management ********************************/ +/** +* @brief Create and Initialize a Mutex object +* @param mutex_def mutex definition referenced with \ref osMutex. +* @retval mutex ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. +*/ +osMutexId osMutexCreate (const osMutexDef_t *mutex_def) +{ +#if ( configUSE_MUTEXES == 1) + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + if (mutex_def->controlblock != NULL) { + return xSemaphoreCreateMutexStatic( mutex_def->controlblock ); + } + else { + return xSemaphoreCreateMutex(); + } +#elif ( configSUPPORT_STATIC_ALLOCATION == 1 ) + return xSemaphoreCreateMutexStatic( mutex_def->controlblock ); +#else + return xSemaphoreCreateMutex(); +#endif +#else + return NULL; +#endif +} + +/** +* @brief Wait until a Mutex becomes available +* @param mutex_id mutex ID obtained by \ref osMutexCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec) +{ + TickType_t ticks; + portBASE_TYPE taskWoken = pdFALSE; + + + if (mutex_id == NULL) { + return osErrorParameter; + } + + ticks = 0; + if (millisec == osWaitForever) { + ticks = portMAX_DELAY; + } + else if (millisec != 0) { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + } + + if (inHandlerMode()) { + if (xSemaphoreTakeFromISR(mutex_id, &taskWoken) != pdTRUE) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else if (xSemaphoreTake(mutex_id, ticks) != pdTRUE) { + return osErrorOS; + } + + return osOK; +} + +/** +* @brief Release a Mutex that was obtained by \ref osMutexWait +* @param mutex_id mutex ID obtained by \ref osMutexCreate. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMutexRelease (osMutexId mutex_id) +{ + osStatus result = osOK; + portBASE_TYPE taskWoken = pdFALSE; + + if (inHandlerMode()) { + if (xSemaphoreGiveFromISR(mutex_id, &taskWoken) != pdTRUE) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else if (xSemaphoreGive(mutex_id) != pdTRUE) + { + result = osErrorOS; + } + return result; +} + +/** +* @brief Delete a Mutex +* @param mutex_id mutex ID obtained by \ref osMutexCreate. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMutexDelete (osMutexId mutex_id) +{ + if (inHandlerMode()) { + return osErrorISR; + } + + vQueueDelete(mutex_id); + + return osOK; +} + +/******************** Semaphore Management Functions **************************/ + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) + +/** +* @brief Create and Initialize a Semaphore object used for managing resources +* @param semaphore_def semaphore definition referenced with \ref osSemaphore. +* @param count number of available resources. +* @retval semaphore ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS. +*/ +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) +{ +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + osSemaphoreId sema; + + if (semaphore_def->controlblock != NULL){ + if (count == 1) { + return xSemaphoreCreateBinaryStatic( semaphore_def->controlblock ); + } + else { +#if (configUSE_COUNTING_SEMAPHORES == 1 ) + return xSemaphoreCreateCountingStatic( count, count, semaphore_def->controlblock ); +#else + return NULL; +#endif + } + } + else { + if (count == 1) { + vSemaphoreCreateBinary(sema); + return sema; + } + else { +#if (configUSE_COUNTING_SEMAPHORES == 1 ) + return xSemaphoreCreateCounting(count, count); +#else + return NULL; +#endif + } + } +#elif ( configSUPPORT_STATIC_ALLOCATION == 1 ) // configSUPPORT_DYNAMIC_ALLOCATION == 0 + if(count == 1) { + return xSemaphoreCreateBinaryStatic( semaphore_def->controlblock ); + } + else + { +#if (configUSE_COUNTING_SEMAPHORES == 1 ) + return xSemaphoreCreateCountingStatic( count, count, semaphore_def->controlblock ); +#else + return NULL; +#endif + } +#else // configSUPPORT_STATIC_ALLOCATION == 0 && configSUPPORT_DYNAMIC_ALLOCATION == 1 + osSemaphoreId sema; + + if (count == 1) { + vSemaphoreCreateBinary(sema); + return sema; + } + else { +#if (configUSE_COUNTING_SEMAPHORES == 1 ) + return xSemaphoreCreateCounting(count, count); +#else + return NULL; +#endif + } +#endif +} + +/** +* @brief Wait until a Semaphore token becomes available +* @param semaphore_id semaphore object referenced with \ref osSemaphore. +* @param millisec timeout value or 0 in case of no time-out. +* @retval number of available tokens, or -1 in case of incorrect parameters. +* @note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. +*/ +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) +{ + TickType_t ticks; + portBASE_TYPE taskWoken = pdFALSE; + + + if (semaphore_id == NULL) { + return osErrorParameter; + } + + ticks = 0; + if (millisec == osWaitForever) { + ticks = portMAX_DELAY; + } + else if (millisec != 0) { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + } + + if (inHandlerMode()) { + if (xSemaphoreTakeFromISR(semaphore_id, &taskWoken) != pdTRUE) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else if (xSemaphoreTake(semaphore_id, ticks) != pdTRUE) { + return osErrorOS; + } + + return osOK; +} + +/** +* @brief Release a Semaphore token +* @param semaphore_id semaphore object referenced with \ref osSemaphore. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. +*/ +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id) +{ + osStatus result = osOK; + portBASE_TYPE taskWoken = pdFALSE; + + + if (inHandlerMode()) { + if (xSemaphoreGiveFromISR(semaphore_id, &taskWoken) != pdTRUE) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else { + if (xSemaphoreGive(semaphore_id) != pdTRUE) { + result = osErrorOS; + } + } + + return result; +} + +/** +* @brief Delete a Semaphore +* @param semaphore_id semaphore object referenced with \ref osSemaphore. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS. +*/ +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id) +{ + if (inHandlerMode()) { + return osErrorISR; + } + + vSemaphoreDelete(semaphore_id); + + return osOK; +} + +#endif /* Use Semaphores */ + +/******************* Memory Pool Management Functions ***********************/ + +#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) + +//TODO +//This is a primitive and inefficient wrapper around the existing FreeRTOS memory management. +//A better implementation will have to modify heap_x.c! + + +typedef struct os_pool_cb { + void *pool; + uint8_t *markers; + uint32_t pool_sz; + uint32_t item_sz; + uint32_t currentIndex; +} os_pool_cb_t; + + +/** +* @brief Create and Initialize a memory pool +* @param pool_def memory pool definition referenced with \ref osPool. +* @retval memory pool ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS. +*/ +osPoolId osPoolCreate (const osPoolDef_t *pool_def) +{ +#if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + osPoolId thePool; + int itemSize = 4 * ((pool_def->item_sz + 3) / 4); + uint32_t i; + + /* First have to allocate memory for the pool control block. */ + thePool = pvPortMalloc(sizeof(os_pool_cb_t)); + + + if (thePool) { + thePool->pool_sz = pool_def->pool_sz; + thePool->item_sz = itemSize; + thePool->currentIndex = 0; + + /* Memory for markers */ + thePool->markers = pvPortMalloc(pool_def->pool_sz); + + if (thePool->markers) { + /* Now allocate the pool itself. */ + thePool->pool = pvPortMalloc(pool_def->pool_sz * itemSize); + + if (thePool->pool) { + for (i = 0; i < pool_def->pool_sz; i++) { + thePool->markers[i] = 0; + } + } + else { + vPortFree(thePool->markers); + vPortFree(thePool); + thePool = NULL; + } + } + else { + vPortFree(thePool); + thePool = NULL; + } + } + + return thePool; + +#else + return NULL; +#endif +} + +/** +* @brief Allocate a memory block from a memory pool +* @param pool_id memory pool ID obtain referenced with \ref osPoolCreate. +* @retval address of the allocated memory block or NULL in case of no memory available. +* @note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. +*/ +void *osPoolAlloc (osPoolId pool_id) +{ + int dummy = 0; + void *p = NULL; + uint32_t i; + uint32_t index; + + if (inHandlerMode()) { + dummy = portSET_INTERRUPT_MASK_FROM_ISR(); + } + else { + vPortEnterCritical(); + } + + for (i = 0; i < pool_id->pool_sz; i++) { + index = (pool_id->currentIndex + i) % pool_id->pool_sz; + + if (pool_id->markers[index] == 0) { + pool_id->markers[index] = 1; + p = (void *)((uint32_t)(pool_id->pool) + (index * pool_id->item_sz)); + pool_id->currentIndex = index; + break; + } + } + + if (inHandlerMode()) { + portCLEAR_INTERRUPT_MASK_FROM_ISR(dummy); + } + else { + vPortExitCritical(); + } + + return p; +} + +/** +* @brief Allocate a memory block from a memory pool and set memory block to zero +* @param pool_id memory pool ID obtain referenced with \ref osPoolCreate. +* @retval address of the allocated memory block or NULL in case of no memory available. +* @note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS. +*/ +void *osPoolCAlloc (osPoolId pool_id) +{ + void *p = osPoolAlloc(pool_id); + + if (p != NULL) + { + memset(p, 0, sizeof(pool_id->pool_sz)); + } + + return p; +} + +/** +* @brief Return an allocated memory block back to a specific memory pool +* @param pool_id memory pool ID obtain referenced with \ref osPoolCreate. +* @param block address of the allocated memory block that is returned to the memory pool. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS. +*/ +osStatus osPoolFree (osPoolId pool_id, void *block) +{ + uint32_t index; + + if (pool_id == NULL) { + return osErrorParameter; + } + + if (block == NULL) { + return osErrorParameter; + } + + if (block < pool_id->pool) { + return osErrorParameter; + } + + index = (uint32_t)block - (uint32_t)(pool_id->pool); + if (index % pool_id->item_sz) { + return osErrorParameter; + } + index = index / pool_id->item_sz; + if (index >= pool_id->pool_sz) { + return osErrorParameter; + } + + pool_id->markers[index] = 0; + + return osOK; +} + + +#endif /* Use Memory Pool Management */ + +/******************* Message Queue Management Functions *********************/ + +#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) /* Use Message Queues */ + +/** +* @brief Create and Initialize a Message Queue +* @param queue_def queue definition referenced with \ref osMessageQ. +* @param thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +* @retval message queue ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. +*/ +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) +{ + (void) thread_id; + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + if ((queue_def->buffer != NULL) && (queue_def->controlblock != NULL)) { + return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock); + } + else { + return xQueueCreate(queue_def->queue_sz, queue_def->item_sz); + } +#elif ( configSUPPORT_STATIC_ALLOCATION == 1 ) + return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock); +#else + return xQueueCreate(queue_def->queue_sz, queue_def->item_sz); +#endif +} + +/** +* @brief Put a Message to a Queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @param info message information. +* @param millisec timeout value or 0 in case of no time-out. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) +{ + portBASE_TYPE taskWoken = pdFALSE; + TickType_t ticks; + + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + + if (inHandlerMode()) { + if (xQueueSendFromISR(queue_id, &info, &taskWoken) != pdTRUE) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else { + if (xQueueSend(queue_id, &info, ticks) != pdTRUE) { + return osErrorOS; + } + } + + return osOK; +} + +/** +* @brief Get a Message or Wait for a Message from a Queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval event information that includes status code. +* @note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. +*/ +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) +{ + portBASE_TYPE taskWoken; + TickType_t ticks; + osEvent event; + + event.def.message_id = queue_id; + event.value.v = 0; + + if (queue_id == NULL) { + event.status = osErrorParameter; + return event; + } + + taskWoken = pdFALSE; + + ticks = 0; + if (millisec == osWaitForever) { + ticks = portMAX_DELAY; + } + else if (millisec != 0) { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + } + + if (inHandlerMode()) { + if (xQueueReceiveFromISR(queue_id, &event.value.v, &taskWoken) == pdTRUE) { + /* We have mail */ + event.status = osEventMessage; + } + else { + event.status = osOK; + } + portEND_SWITCHING_ISR(taskWoken); + } + else { + if (xQueueReceive(queue_id, &event.value.v, ticks) == pdTRUE) { + /* We have mail */ + event.status = osEventMessage; + } + else { + event.status = (ticks == 0) ? osOK : osEventTimeout; + } + } + + return event; +} + +#endif /* Use Message Queues */ + +/******************** Mail Queue Management Functions ***********************/ +#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) /* Use Mail Queues */ + + +typedef struct os_mailQ_cb { + const osMailQDef_t *queue_def; + QueueHandle_t handle; + osPoolId pool; +} os_mailQ_cb_t; + +/** +* @brief Create and Initialize mail queue +* @param queue_def reference to the mail queue definition obtain with \ref osMailQ +* @param thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +* @retval mail queue ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS. +*/ +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) +{ +#if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + (void) thread_id; + + osPoolDef_t pool_def = {queue_def->queue_sz, queue_def->item_sz, NULL}; + + /* Create a mail queue control block */ + + *(queue_def->cb) = pvPortMalloc(sizeof(struct os_mailQ_cb)); + + if (*(queue_def->cb) == NULL) { + return NULL; + } + (*(queue_def->cb))->queue_def = queue_def; + + /* Create a queue in FreeRTOS */ + (*(queue_def->cb))->handle = xQueueCreate(queue_def->queue_sz, sizeof(void *)); + + + if ((*(queue_def->cb))->handle == NULL) { + vPortFree(*(queue_def->cb)); + return NULL; + } + + /* Create a mail pool */ + (*(queue_def->cb))->pool = osPoolCreate(&pool_def); + if ((*(queue_def->cb))->pool == NULL) { + //TODO: Delete queue. How to do it in FreeRTOS? + vPortFree(*(queue_def->cb)); + return NULL; + } + + return *(queue_def->cb); +#else + return NULL; +#endif +} + +/** +* @brief Allocate a memory block from a mail +* @param queue_id mail queue ID obtained with \ref osMailCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval pointer to memory block that can be filled with mail or NULL in case error. +* @note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS. +*/ +void *osMailAlloc (osMailQId queue_id, uint32_t millisec) +{ + (void) millisec; + void *p; + + + if (queue_id == NULL) { + return NULL; + } + + p = osPoolAlloc(queue_id->pool); + + return p; +} + +/** +* @brief Allocate a memory block from a mail and set memory block to zero +* @param queue_id mail queue ID obtained with \ref osMailCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval pointer to memory block that can be filled with mail or NULL in case error. +* @note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS. +*/ +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) +{ + uint32_t i; + void *p = osMailAlloc(queue_id, millisec); + + if (p) { + for (i = 0; i < queue_id->queue_def->item_sz; i++) { + ((uint8_t *)p)[i] = 0; + } + } + + return p; +} + +/** +* @brief Put a mail to a queue +* @param queue_id mail queue ID obtained with \ref osMailCreate. +* @param mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMailPut (osMailQId queue_id, void *mail) +{ + portBASE_TYPE taskWoken; + + + if (queue_id == NULL) { + return osErrorParameter; + } + + taskWoken = pdFALSE; + + if (inHandlerMode()) { + if (xQueueSendFromISR(queue_id->handle, &mail, &taskWoken) != pdTRUE) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else { + if (xQueueSend(queue_id->handle, &mail, 0) != pdTRUE) { + return osErrorOS; + } + } + + return osOK; +} + +/** +* @brief Get a mail from a queue +* @param queue_id mail queue ID obtained with \ref osMailCreate. +* @param millisec timeout value or 0 in case of no time-out +* @retval event that contains mail information or error code. +* @note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS. +*/ +osEvent osMailGet (osMailQId queue_id, uint32_t millisec) +{ + portBASE_TYPE taskWoken; + TickType_t ticks; + osEvent event; + + event.def.mail_id = queue_id; + + if (queue_id == NULL) { + event.status = osErrorParameter; + return event; + } + + taskWoken = pdFALSE; + + ticks = 0; + if (millisec == osWaitForever) { + ticks = portMAX_DELAY; + } + else if (millisec != 0) { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + } + + if (inHandlerMode()) { + if (xQueueReceiveFromISR(queue_id->handle, &event.value.p, &taskWoken) == pdTRUE) { + /* We have mail */ + event.status = osEventMail; + } + else { + event.status = osOK; + } + portEND_SWITCHING_ISR(taskWoken); + } + else { + if (xQueueReceive(queue_id->handle, &event.value.p, ticks) == pdTRUE) { + /* We have mail */ + event.status = osEventMail; + } + else { + event.status = (ticks == 0) ? osOK : osEventTimeout; + } + } + + return event; +} + +/** +* @brief Free a memory block from a mail +* @param queue_id mail queue ID obtained with \ref osMailCreate. +* @param mail pointer to the memory block that was obtained with \ref osMailGet. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMailFree (osMailQId queue_id, void *mail) +{ + if (queue_id == NULL) { + return osErrorParameter; + } + + return osPoolFree(queue_id->pool, mail); +} +#endif /* Use Mail Queues */ + +/*************************** Additional specific APIs to Free RTOS ************/ +/** +* @brief Handles the tick increment +* @param none. +* @retval none. +*/ +void osSystickHandler(void) +{ + +#if (INCLUDE_xTaskGetSchedulerState == 1 ) + if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) + { +#endif /* INCLUDE_xTaskGetSchedulerState */ + xPortSysTickHandler(); +#if (INCLUDE_xTaskGetSchedulerState == 1 ) + } +#endif /* INCLUDE_xTaskGetSchedulerState */ +} + +#if ( INCLUDE_eTaskGetState == 1 ) +/** +* @brief Obtain the state of any thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval the stae of the thread, states are encoded by the osThreadState enumerated type. +*/ +osThreadState osThreadGetState(osThreadId thread_id) +{ + eTaskState ThreadState; + osThreadState result; + + ThreadState = eTaskGetState(thread_id); + + switch (ThreadState) + { + case eRunning : + result = osThreadRunning; + break; + case eReady : + result = osThreadReady; + break; + case eBlocked : + result = osThreadBlocked; + break; + case eSuspended : + result = osThreadSuspended; + break; + case eDeleted : + result = osThreadDeleted; + break; + default: + result = osThreadError; + } + + return result; +} +#endif /* INCLUDE_eTaskGetState */ + +#if (INCLUDE_eTaskGetState == 1) +/** +* @brief Check if a thread is already suspended or not. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadIsSuspended(osThreadId thread_id) +{ + if (eTaskGetState(thread_id) == eSuspended) + return osOK; + else + return osErrorOS; +} +#endif /* INCLUDE_eTaskGetState */ +/** +* @brief Suspend execution of a thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadSuspend (osThreadId thread_id) +{ +#if (INCLUDE_vTaskSuspend == 1) + vTaskSuspend(thread_id); + + return osOK; +#else + return osErrorResource; +#endif +} + +/** +* @brief Resume execution of a suspended thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadResume (osThreadId thread_id) +{ +#if (INCLUDE_vTaskSuspend == 1) + if(inHandlerMode()) + { + if (xTaskResumeFromISR(thread_id) == pdTRUE) + { + portYIELD_FROM_ISR(pdTRUE); + } + } + else + { + vTaskResume(thread_id); + } + return osOK; +#else + return osErrorResource; +#endif +} + +/** +* @brief Suspend execution of a all active threads. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadSuspendAll (void) +{ + vTaskSuspendAll(); + + return osOK; +} + +/** +* @brief Resume execution of a all suspended threads. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadResumeAll (void) +{ + if (xTaskResumeAll() == pdTRUE) + return osOK; + else + return osErrorOS; + +} + +/** +* @brief Delay a task until a specified time +* @param PreviousWakeTime Pointer to a variable that holds the time at which the +* task was last unblocked. PreviousWakeTime must be initialised with the current time +* prior to its first use (PreviousWakeTime = osKernelSysTick() ) +* @param millisec time delay value +* @retval status code that indicates the execution status of the function. +*/ +osStatus osDelayUntil (uint32_t *PreviousWakeTime, uint32_t millisec) +{ +#if INCLUDE_vTaskDelayUntil + TickType_t ticks = (millisec / portTICK_PERIOD_MS); + vTaskDelayUntil((TickType_t *) PreviousWakeTime, ticks ? ticks : 1); + + return osOK; +#else + (void) millisec; + (void) PreviousWakeTime; + + return osErrorResource; +#endif +} + +/** +* @brief Abort the delay for a specific thread +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId +* @retval status code that indicates the execution status of the function. +*/ +osStatus osAbortDelay(osThreadId thread_id) +{ +#if INCLUDE_xTaskAbortDelay + + xTaskAbortDelay(thread_id); + + return osOK; +#else + (void) thread_id; + + return osErrorResource; +#endif +} + +/** +* @brief Lists all the current threads, along with their current state +* and stack usage high water mark. +* @param buffer A buffer into which the above mentioned details +* will be written +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadList (uint8_t *buffer) +{ +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) ) + vTaskList((char *)buffer); +#endif + return osOK; +} + +/** +* @brief Receive an item from a queue without removing the item from the queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval event information that includes status code. +*/ +osEvent osMessagePeek (osMessageQId queue_id, uint32_t millisec) +{ + TickType_t ticks; + osEvent event; + + event.def.message_id = queue_id; + + if (queue_id == NULL) { + event.status = osErrorParameter; + return event; + } + + ticks = 0; + if (millisec == osWaitForever) { + ticks = portMAX_DELAY; + } + else if (millisec != 0) { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + } + + if (xQueuePeek(queue_id, &event.value.v, ticks) == pdTRUE) + { + /* We have mail */ + event.status = osEventMessage; + } + else + { + event.status = (ticks == 0) ? osOK : osEventTimeout; + } + + return event; +} + +/** +* @brief Get the number of messaged stored in a queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @retval number of messages stored in a queue. +*/ +uint32_t osMessageWaiting(osMessageQId queue_id) +{ + if (inHandlerMode()) { + return uxQueueMessagesWaitingFromISR(queue_id); + } + else + { + return uxQueueMessagesWaiting(queue_id); + } +} + +/** +* @brief Get the available space in a message queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @retval available space in a message queue. +*/ +uint32_t osMessageAvailableSpace(osMessageQId queue_id) +{ + return uxQueueSpacesAvailable(queue_id); +} + +/** +* @brief Delete a Message Queue +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osMessageDelete (osMessageQId queue_id) +{ + if (inHandlerMode()) { + return osErrorISR; + } + + vQueueDelete(queue_id); + + return osOK; +} + +/** +* @brief Create and Initialize a Recursive Mutex +* @param mutex_def mutex definition referenced with \ref osMutex. +* @retval mutex ID for reference by other functions or NULL in case of error.. +*/ +osMutexId osRecursiveMutexCreate (const osMutexDef_t *mutex_def) +{ +#if (configUSE_RECURSIVE_MUTEXES == 1) +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + if (mutex_def->controlblock != NULL){ + return xSemaphoreCreateRecursiveMutexStatic( mutex_def->controlblock ); + } + else { + return xSemaphoreCreateRecursiveMutex(); + } +#elif ( configSUPPORT_STATIC_ALLOCATION == 1 ) + return xSemaphoreCreateRecursiveMutexStatic( mutex_def->controlblock ); +#else + return xSemaphoreCreateRecursiveMutex(); +#endif +#else + return NULL; +#endif +} + +/** +* @brief Release a Recursive Mutex +* @param mutex_id mutex ID obtained by \ref osRecursiveMutexCreate. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osRecursiveMutexRelease (osMutexId mutex_id) +{ +#if (configUSE_RECURSIVE_MUTEXES == 1) + osStatus result = osOK; + + if (xSemaphoreGiveRecursive(mutex_id) != pdTRUE) + { + result = osErrorOS; + } + return result; +#else + return osErrorResource; +#endif +} + +/** +* @brief Release a Recursive Mutex +* @param mutex_id mutex ID obtained by \ref osRecursiveMutexCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osRecursiveMutexWait (osMutexId mutex_id, uint32_t millisec) +{ +#if (configUSE_RECURSIVE_MUTEXES == 1) + TickType_t ticks; + + if (mutex_id == NULL) + { + return osErrorParameter; + } + + ticks = 0; + if (millisec == osWaitForever) + { + ticks = portMAX_DELAY; + } + else if (millisec != 0) + { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) + { + ticks = 1; + } + } + + if (xSemaphoreTakeRecursive(mutex_id, ticks) != pdTRUE) + { + return osErrorOS; + } + return osOK; +#else + return osErrorResource; +#endif +} + +/** +* @brief Returns the current count value of a counting semaphore +* @param semaphore_id semaphore_id ID obtained by \ref osSemaphoreCreate. +* @retval count value +*/ +uint32_t osSemaphoreGetCount(osSemaphoreId semaphore_id) +{ + return uxSemaphoreGetCount(semaphore_id); +} diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h new file mode 100644 index 00000000..f53a132a --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h @@ -0,0 +1,1026 @@ +/* ---------------------------------------------------------------------- + * $Date: 5. February 2013 + * $Revision: V1.02 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedef's + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + * Version 1.02 + * Control functions for short timeouts in microsecond resolution: + * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec + * Removed: osSignalGet + * + * + *---------------------------------------------------------------------------- + * + * Portions Copyright 2016 STMicroelectronics International N.V. All rights reserved. + * Portions Copyright (c) 2013 ARM LIMITED + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "queue.h" +#include "semphr.h" +#include "event_groups.h" + +/** +\page cmsis_os_h Header File Template: cmsis_os.h + +The file \b cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS). +Each RTOS that is compliant with CMSIS-RTOS shall provide a specific \b cmsis_os.h header file that represents +its implementation. + +The file cmsis_os.h contains: + - CMSIS-RTOS API function definitions + - struct definitions for parameters and return types + - status and priority values used by CMSIS-RTOS API functions + - macros for defining threads and other kernel objects + + +Name conventions and header file modifications + +All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions. +Definitions that are prefixed \b os_ are not used in the application code but local to this header file. +All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread. + +Definitions that are marked with CAN BE CHANGED can be adapted towards the needs of the actual CMSIS-RTOS implementation. +These definitions can be specific to the underlying RTOS kernel. + +Definitions that are marked with MUST REMAIN UNCHANGED cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer +compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation. + + +Function calls from interrupt service routines + +The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR): + - \ref osSignalSet + - \ref osSemaphoreRelease + - \ref osPoolAlloc, \ref osPoolCAlloc, \ref osPoolFree + - \ref osMessagePut, \ref osMessageGet + - \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree + +Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called +from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector. + +Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time. +If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code \b osErrorISRRecursive. + + +Define and reference object definitions + +With \#define osObjectsExternal objects are defined as external symbols. This allows to create a consistent header file +that is used throughout a project as shown below: + +Header File +\code +#include // CMSIS RTOS header file + +// Thread definition +extern void thread_sample (void const *argument); // function prototype +osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100); + +// Pool definition +osPoolDef(MyPool, 10, long); +\endcode + + +This header file defines all objects when included in a C/C++ source file. When \#define osObjectsExternal is +present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be +used throughout the whole project. + +Example +\code +#include "osObjects.h" // Definition of the CMSIS-RTOS objects +\endcode + +\code +#define osObjectExternal // Objects will be defined as external symbols +#include "osObjects.h" // Reference to the CMSIS-RTOS objects +\endcode + +*/ + +#ifndef _CMSIS_OS_H +#define _CMSIS_OS_H + +/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version. +#define osCMSIS 0x10002 ///< API version (main [31:16] .sub [15:0]) + +/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. +#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0]) + +/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS. +#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string + +/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS. +#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 1 ///< osFeature_Semaphore function: 1=available, 0=not available +#define osFeature_Wait 0 ///< osWait function: 1=available, 0=not available +#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumeration, structures, defines ==== + +/// Priority used for thread control. +/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS. +typedef enum { + osPriorityIdle = -3, ///< priority: idle (lowest) + osPriorityLow = -2, ///< priority: low + osPriorityBelowNormal = -1, ///< priority: below normal + osPriorityNormal = 0, ///< priority: normal (default) + osPriorityAboveNormal = +1, ///< priority: above normal + osPriorityHigh = +2, ///< priority: high + osPriorityRealtime = +3, ///< priority: realtime (highest) + osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority +} osPriority; + +/// Timeout value. +/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS. +#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value + +/// Status code values returned by CMSIS-RTOS functions. +/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS. +typedef enum { + osOK = 0, ///< function completed; no error or event occurred. + osEventSignal = 0x08, ///< function completed; signal event occurred. + osEventMessage = 0x10, ///< function completed; message event occurred. + osEventMail = 0x20, ///< function completed; mail event occurred. + osEventTimeout = 0x40, ///< function completed; timeout occurred. + osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< value of a parameter is out of range. + osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits. + os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization. +} osStatus; + +#if ( INCLUDE_eTaskGetState == 1 ) +/* Thread state returned by osThreadGetState */ +typedef enum { + osThreadRunning = 0x0, /* A thread is querying the state of itself, so must be running. */ + osThreadReady = 0x1 , /* The thread being queried is in a read or pending ready list. */ + osThreadBlocked = 0x2, /* The thread being queried is in the Blocked state. */ + osThreadSuspended = 0x3, /* The thread being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */ + osThreadDeleted = 0x4, /* The thread being queried has been deleted, but its TCB has not yet been freed. */ + osThreadError = 0x7FFFFFFF +} osThreadState; +#endif /* INCLUDE_eTaskGetState */ + +/// Timer type value for the timer definition. +/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS. +typedef enum { + osTimerOnce = 0, ///< one-shot timer + osTimerPeriodic = 1 ///< repeating timer +} os_timer_type; + +/// Entry point of a thread. +/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. +typedef void (*os_ptimer) (void const *argument); + +// >>> the following data type definitions may shall adapted towards a specific RTOS + +/// Thread ID identifies the thread (pointer to a thread control block). +/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS. +typedef TaskHandle_t osThreadId; + +/// Timer ID identifies the timer (pointer to a timer control block). +/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS. +typedef TimerHandle_t osTimerId; + +/// Mutex ID identifies the mutex (pointer to a mutex control block). +/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS. +typedef SemaphoreHandle_t osMutexId; + +/// Semaphore ID identifies the semaphore (pointer to a semaphore control block). +/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS. +typedef SemaphoreHandle_t osSemaphoreId; + +/// Pool ID identifies the memory pool (pointer to a memory pool control block). +/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_cb *osPoolId; + +/// Message ID identifies the message queue (pointer to a message queue control block). +/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS. +typedef QueueHandle_t osMessageQId; + +/// Mail ID identifies the mail queue (pointer to a mail queue control block). +/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_cb *osMailQId; + + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + +typedef StaticTask_t osStaticThreadDef_t; +typedef StaticTimer_t osStaticTimerDef_t; +typedef StaticSemaphore_t osStaticMutexDef_t; +typedef StaticSemaphore_t osStaticSemaphoreDef_t; +typedef StaticQueue_t osStaticMessageQDef_t; + +#endif + + + + +/// Thread Definition structure contains startup information of a thread. +/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_def { + char *name; ///< Thread name + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t instances; ///< maximum number of instances of that thread function + uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + uint32_t *buffer; ///< stack buffer for static allocation; NULL for dynamic allocation + osStaticThreadDef_t *controlblock; ///< control block to hold thread's data for static allocation; NULL for dynamic allocation +#endif +} osThreadDef_t; + +/// Timer Definition structure contains timer parameters. +/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + osStaticTimerDef_t *controlblock; ///< control block to hold timer's data for static allocation; NULL for dynamic allocation +#endif +} osTimerDef_t; + +/// Mutex Definition structure contains setup information for a mutex. +/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_def { + uint32_t dummy; ///< dummy value. +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + osStaticMutexDef_t *controlblock; ///< control block for static allocation; NULL for dynamic allocation +#endif +} osMutexDef_t; + +/// Semaphore Definition structure contains setup information for a semaphore. +/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_def { + uint32_t dummy; ///< dummy value. +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + osStaticSemaphoreDef_t *controlblock; ///< control block for static allocation; NULL for dynamic allocation +#endif +} osSemaphoreDef_t; + +/// Definition structure for memory block allocation. +/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; + +/// Definition structure for message queue. +/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + uint8_t *buffer; ///< buffer for static allocation; NULL for dynamic allocation + osStaticMessageQDef_t *controlblock; ///< control block to hold queue's data for static allocation; NULL for dynamic allocation +#endif + //void *pool; ///< memory array for messages +} osMessageQDef_t; + +/// Definition structure for mail queue. +/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + struct os_mailQ_cb **cb; +} osMailQDef_t; + +/// Event structure contains detailed information about an event. +/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS. +/// However the struct may be extended at the end. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Control Functions ==== + +/// Initialize the RTOS Kernel for creating objects. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS. +osStatus osKernelInitialize (void); + +/// Start the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +osStatus osKernelStart (void); + +/// Check if the RTOS kernel is already started. +/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. +/// \return 0 RTOS is not started, 1 RTOS is started. +int32_t osKernelRunning(void); + +#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available + +/// Get the RTOS kernel system timer counter +/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS. +/// \return RTOS kernel system timer as 32-bit value +uint32_t osKernelSysTick (void); + +/// The RTOS kernel system timer frequency in Hz +/// \note Reflects the system timer setting and is typically defined in a configuration file. +#define osKernelSysTickFrequency (configTICK_RATE_HZ) + +/// Convert a microseconds value to a RTOS kernel system timer value. +/// \param microsec time value in microseconds. +/// \return time value normalized to the \ref osKernelSysTickFrequency +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000) + +#endif // System Timer available + +// ==== Thread Management ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param instances number of possible thread instances. +/// \param stacksz stack size (in bytes) requirements for the thread function. +/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, thread, priority, instances, stacksz) \ +extern const osThreadDef_t os_thread_def_##name +#else // define the object + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) +#define osThreadDef(name, thread, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ #name, (thread), (priority), (instances), (stacksz), NULL, NULL } + +#define osThreadStaticDef(name, thread, priority, instances, stacksz, buffer, control) \ +const osThreadDef_t os_thread_def_##name = \ +{ #name, (thread), (priority), (instances), (stacksz), (buffer), (control) } +#else //configSUPPORT_STATIC_ALLOCATION == 0 + +#define osThreadDef(name, thread, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ #name, (thread), (priority), (instances), (stacksz)} +#endif +#endif + +/// Access a Thread definition. +/// \param name name of the thread definition object. +/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osThread(name) \ +&os_thread_def_##name + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS. +osThreadId osThreadGetId (void); + +/// Terminate execution of a thread and remove it from Active Threads. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS. +osStatus osThreadTerminate (osThreadId thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS. +osStatus osThreadYield (void); + +/// Change priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS. +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); + +/// Get current priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the thread function. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS. +osPriority osThreadGetPriority (osThreadId thread_id); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] millisec time delay value +/// \return status code that indicates the execution status of the function. +osStatus osDelay (uint32_t millisec); + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS. +osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern const osTimerDef_t os_timer_def_##name +#else // define the object + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = \ +{ (function), NULL } + +#define osTimerStaticDef(name, function, control) \ +const osTimerDef_t os_timer_def_##name = \ +{ (function), (control) } +#else //configSUPPORT_STATIC_ALLOCATION == 0 +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = \ +{ (function) } +#endif +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS. +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec time delay value of the timer. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS. +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); + +/// Stop the timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS. +osStatus osTimerStop (osTimerId timer_id); + +/// Delete a timer that was created by \ref osTimerCreate. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS. +osStatus osTimerDelete (osTimerId timer_id); + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return osOK if successful, osErrorOS if failed. +/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. +int32_t osSignalSet (osThreadId thread_id, int32_t signals); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS. +int32_t osSignalClear (osThreadId thread_id, int32_t signals); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return event flag information or error code. +/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS. +osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Mutex Management ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern const osMutexDef_t os_mutex_def_##name +#else // define the object + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = { 0, NULL } + +#define osMutexStaticDef(name, control) \ +const osMutexDef_t os_mutex_def_##name = { 0, (control) } +#else //configSUPPORT_STATIC_ALLOCATION == 0 +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = { 0 } + +#endif + +#endif + +/// Access a Mutex definition. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object. +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. +osMutexId osMutexCreate (const osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); + +/// Release a Mutex that was obtained by \ref osMutexWait. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. +osStatus osMutexRelease (osMutexId mutex_id); + +/// Delete a Mutex that was created by \ref osMutexCreate. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS. +osStatus osMutexDelete (osMutexId mutex_id); + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern const osSemaphoreDef_t os_semaphore_def_##name +#else // define the object + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = { 0, NULL } + +#define osSemaphoreStaticDef(name, control) \ +const osSemaphoreDef_t os_semaphore_def_##name = { 0, (control) } + +#else //configSUPPORT_STATIC_ALLOCATION == 0 +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = { 0 } +#endif +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object used for managing resources. +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count number of available resources. +/// \return semaphore ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS. +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); + +/// Delete a Semaphore that was created by \ref osSemaphoreCreate. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); + +#endif // Semaphore available + + +// ==== Memory Pool Management Functions ==== + +#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of blocks (objects) in the memory pool. +/// \param type data type of a single block (object). +/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern const osPoolDef_t os_pool_def_##name +#else // define the object +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), NULL } +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a memory pool. +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS. +osPoolId osPoolCreate (const osPoolDef_t *pool_def); + +/// Allocate a memory block from a memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a memory pool and set memory block to zero. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a specific memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block that is returned to the memory pool. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool Management available + + +// ==== Message Queue Management Functions ==== + +#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern const osMessageQDef_t os_messageQ_def_##name +#else // define the object +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), sizeof (type), NULL, NULL } + +#define osMessageQStaticDef(name, queue_sz, type, buffer, control) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), sizeof (type) , (buffer), (control)} +#else //configSUPPORT_STATIC_ALLOCATION == 1 +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), sizeof (type) } + +#endif +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue. +/// \param[in] queue_def queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message or Wait for a Message from a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return event information that includes status code. +/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queues available + + +// ==== Mail Queue Management Functions ==== + +#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available + +/// \brief Create a Mail Queue Definition. +/// \param name name of the queue +/// \param queue_sz maximum number of messages in queue +/// \param type data type of a single message element +/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern struct os_mailQ_cb *os_mailQ_cb_##name \ +extern osMailQDef_t os_mailQ_def_##name +#else // define the object +#define osMailQDef(name, queue_sz, type) \ +struct os_mailQ_cb *os_mailQ_cb_##name; \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof (type), (&os_mailQ_cb_##name) } +#endif + +/// \brief Access a Mail Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize mail queue. +/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS. +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block from a mail and set memory block to zero. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a mail to a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS. +osStatus osMailPut (osMailQId queue_id, void *mail); + +/// Get a mail from a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return event that contains mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS. +osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queues available + +/*************************** Additional specific APIs to Free RTOS ************/ +/** +* @brief Handles the tick increment +* @param none. +* @retval none. +*/ +void osSystickHandler(void); + +#if ( INCLUDE_eTaskGetState == 1 ) +/** +* @brief Obtain the state of any thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval the stae of the thread, states are encoded by the osThreadState enumerated type. +*/ +osThreadState osThreadGetState(osThreadId thread_id); +#endif /* INCLUDE_eTaskGetState */ + +#if ( INCLUDE_eTaskGetState == 1 ) +/** +* @brief Check if a thread is already suspended or not. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +*/ + +osStatus osThreadIsSuspended(osThreadId thread_id); + +#endif /* INCLUDE_eTaskGetState */ + +/** +* @brief Suspend execution of a thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadSuspend (osThreadId thread_id); + +/** +* @brief Resume execution of a suspended thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadResume (osThreadId thread_id); + +/** +* @brief Suspend execution of a all active threads. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadSuspendAll (void); + +/** +* @brief Resume execution of a all suspended threads. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadResumeAll (void); + +/** +* @brief Delay a task until a specified time +* @param PreviousWakeTime Pointer to a variable that holds the time at which the +* task was last unblocked. PreviousWakeTime must be initialised with the current time +* prior to its first use (PreviousWakeTime = osKernelSysTick() ) +* @param millisec time delay value +* @retval status code that indicates the execution status of the function. +*/ +osStatus osDelayUntil (uint32_t *PreviousWakeTime, uint32_t millisec); + +/** +* @brief Abort the delay for a specific thread +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId +* @retval status code that indicates the execution status of the function. +*/ +osStatus osAbortDelay(osThreadId thread_id); + +/** +* @brief Lists all the current threads, along with their current state +* and stack usage high water mark. +* @param buffer A buffer into which the above mentioned details +* will be written +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadList (uint8_t *buffer); + +/** +* @brief Receive an item from a queue without removing the item from the queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval event information that includes status code. +*/ +osEvent osMessagePeek (osMessageQId queue_id, uint32_t millisec); + +/** +* @brief Get the number of messaged stored in a queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @retval number of messages stored in a queue. +*/ +uint32_t osMessageWaiting(osMessageQId queue_id); + +/** +* @brief Get the available space in a message queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @retval available space in a message queue. +*/ +uint32_t osMessageAvailableSpace(osMessageQId queue_id); + +/** +* @brief Delete a Message Queue +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osMessageDelete (osMessageQId queue_id); + +/** +* @brief Create and Initialize a Recursive Mutex +* @param mutex_def mutex definition referenced with \ref osMutex. +* @retval mutex ID for reference by other functions or NULL in case of error.. +*/ +osMutexId osRecursiveMutexCreate (const osMutexDef_t *mutex_def); + +/** +* @brief Release a Recursive Mutex +* @param mutex_id mutex ID obtained by \ref osRecursiveMutexCreate. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osRecursiveMutexRelease (osMutexId mutex_id); + +/** +* @brief Release a Recursive Mutex +* @param mutex_id mutex ID obtained by \ref osRecursiveMutexCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osRecursiveMutexWait (osMutexId mutex_id, uint32_t millisec); + +/** +* @brief Returns the current count value of a counting semaphore +* @param semaphore_id semaphore_id ID obtained by \ref osSemaphoreCreate. +* @retval count value +*/ +uint32_t osSemaphoreGetCount(osSemaphoreId semaphore_id); + +#ifdef __cplusplus +} +#endif + +#endif // _CMSIS_OS_H diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/croutine.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/croutine.c new file mode 100644 index 00000000..b7158845 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/croutine.c @@ -0,0 +1,353 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" + +/* Remove the whole file is co-routines are not being used. */ +#if( configUSE_CO_ROUTINES != 0 ) + +/* + * Some kernel aware debuggers require data to be viewed to be global, rather + * than file scope. + */ +#ifdef portREMOVE_STATIC_QUALIFIER + #define static +#endif + + +/* Lists for ready and blocked co-routines. --------------------*/ +static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ +static List_t xDelayedCoRoutineList1; /*< Delayed co-routines. */ +static List_t xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ +static List_t * pxDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used. */ +static List_t * pxOverflowDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ +static List_t xPendingReadyCoRoutineList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ + +/* Other file private variables. --------------------------------*/ +CRCB_t * pxCurrentCoRoutine = NULL; +static UBaseType_t uxTopCoRoutineReadyPriority = 0; +static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0; + +/* The initial state of the co-routine when it is created. */ +#define corINITIAL_STATE ( 0 ) + +/* + * Place the co-routine represented by pxCRCB into the appropriate ready queue + * for the priority. It is inserted at the end of the list. + * + * This macro accesses the co-routine ready lists and therefore must not be + * used from within an ISR. + */ +#define prvAddCoRoutineToReadyQueue( pxCRCB ) \ +{ \ + if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \ + { \ + uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \ + } \ + vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \ +} + +/* + * Utility to ready all the lists used by the scheduler. This is called + * automatically upon the creation of the first co-routine. + */ +static void prvInitialiseCoRoutineLists( void ); + +/* + * Co-routines that are readied by an interrupt cannot be placed directly into + * the ready lists (there is no mutual exclusion). Instead they are placed in + * in the pending ready list in order that they can later be moved to the ready + * list by the co-routine scheduler. + */ +static void prvCheckPendingReadyList( void ); + +/* + * Macro that looks at the list of co-routines that are currently delayed to + * see if any require waking. + * + * Co-routines are stored in the queue in the order of their wake time - + * meaning once one co-routine has been found whose timer has not expired + * we need not look any further down the list. + */ +static void prvCheckDelayedList( void ); + +/*-----------------------------------------------------------*/ + +BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex ) +{ +BaseType_t xReturn; +CRCB_t *pxCoRoutine; + + /* Allocate the memory that will store the co-routine control block. */ + pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) ); + if( pxCoRoutine ) + { + /* If pxCurrentCoRoutine is NULL then this is the first co-routine to + be created and the co-routine data structures need initialising. */ + if( pxCurrentCoRoutine == NULL ) + { + pxCurrentCoRoutine = pxCoRoutine; + prvInitialiseCoRoutineLists(); + } + + /* Check the priority is within limits. */ + if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) + { + uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; + } + + /* Fill out the co-routine control block from the function parameters. */ + pxCoRoutine->uxState = corINITIAL_STATE; + pxCoRoutine->uxPriority = uxPriority; + pxCoRoutine->uxIndex = uxIndex; + pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; + + /* Initialise all the other co-routine control block parameters. */ + vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); + vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); + + /* Set the co-routine control block as a link back from the ListItem_t. + This is so we can get back to the containing CRCB from a generic item + in a list. */ + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) ); + + /* Now the co-routine has been initialised it can be added to the ready + list at the correct priority. */ + prvAddCoRoutineToReadyQueue( pxCoRoutine ); + + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList ) +{ +TickType_t xTimeToWake; + + /* Calculate the time to wake - this may overflow but this is + not a problem. */ + xTimeToWake = xCoRoutineTickCount + xTicksToDelay; + + /* We must remove ourselves from the ready list before adding + ourselves to the blocked list as the same list item is used for + both lists. */ + ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); + + if( xTimeToWake < xCoRoutineTickCount ) + { + /* Wake time has overflowed. Place this item in the + overflow list. */ + vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + else + { + /* The wake time has not overflowed, so we can use the + current block list. */ + vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + + if( pxEventList ) + { + /* Also add the co-routine to an event list. If this is done then the + function must be called with interrupts disabled. */ + vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckPendingReadyList( void ) +{ + /* Are there any co-routines waiting to get moved to the ready list? These + are co-routines that have been readied by an ISR. The ISR cannot access + the ready lists itself. */ + while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE ) + { + CRCB_t *pxUnblockedCRCB; + + /* The pending ready list can be accessed by an ISR. */ + portDISABLE_INTERRUPTS(); + { + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + } + portENABLE_INTERRUPTS(); + + ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); + prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckDelayedList( void ) +{ +CRCB_t *pxCRCB; + + xPassedTicks = xTaskGetTickCount() - xLastTickCount; + while( xPassedTicks ) + { + xCoRoutineTickCount++; + xPassedTicks--; + + /* If the tick count has overflowed we need to swap the ready lists. */ + if( xCoRoutineTickCount == 0 ) + { + List_t * pxTemp; + + /* Tick count has overflowed so we need to swap the delay lists. If there are + any items in pxDelayedCoRoutineList here then there is an error! */ + pxTemp = pxDelayedCoRoutineList; + pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; + pxOverflowDelayedCoRoutineList = pxTemp; + } + + /* See if this tick has made a timeout expire. */ + while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE ) + { + pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ); + + if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) + { + /* Timeout not yet expired. */ + break; + } + + portDISABLE_INTERRUPTS(); + { + /* The event could have occurred just before this critical + section. If this is the case then the generic list item will + have been moved to the pending ready list and the following + line is still valid. Also the pvContainer parameter will have + been set to NULL so the following lines are also valid. */ + ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) ); + + /* Is the co-routine waiting on an event also? */ + if( pxCRCB->xEventListItem.pvContainer ) + { + ( void ) uxListRemove( &( pxCRCB->xEventListItem ) ); + } + } + portENABLE_INTERRUPTS(); + + prvAddCoRoutineToReadyQueue( pxCRCB ); + } + } + + xLastTickCount = xCoRoutineTickCount; +} +/*-----------------------------------------------------------*/ + +void vCoRoutineSchedule( void ) +{ + /* See if any co-routines readied by events need moving to the ready lists. */ + prvCheckPendingReadyList(); + + /* See if any delayed co-routines have timed out. */ + prvCheckDelayedList(); + + /* Find the highest priority queue that contains ready co-routines. */ + while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) + { + if( uxTopCoRoutineReadyPriority == 0 ) + { + /* No more co-routines to check. */ + return; + } + --uxTopCoRoutineReadyPriority; + } + + /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines + of the same priority get an equal share of the processor time. */ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); + + /* Call the co-routine. */ + ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); + + return; +} +/*-----------------------------------------------------------*/ + +static void prvInitialiseCoRoutineLists( void ) +{ +UBaseType_t uxPriority; + + for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) + { + vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); + } + + vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 ); + vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 ); + vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList ); + + /* Start with pxDelayedCoRoutineList using list1 and the + pxOverflowDelayedCoRoutineList using list2. */ + pxDelayedCoRoutineList = &xDelayedCoRoutineList1; + pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; +} +/*-----------------------------------------------------------*/ + +BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList ) +{ +CRCB_t *pxUnblockedCRCB; +BaseType_t xReturn; + + /* This function is called from within an interrupt. It can only access + event lists and the pending ready list. This function assumes that a + check has already been made to ensure pxEventList is not empty. */ + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) ); + + if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} + +#endif /* configUSE_CO_ROUTINES == 0 */ + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/event_groups.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/event_groups.c new file mode 100644 index 00000000..14d7b024 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/event_groups.c @@ -0,0 +1,738 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining +all the API functions to use the MPU wrappers. That should only be done when +task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "event_groups.h" + +/* Lint e961 and e750 are suppressed as a MISRA exception justified because the +MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the +header files above, but not in this file, in order to generate the correct +privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */ + +/* The following bit fields convey control information in a task's event list +item value. It is important they don't clash with the +taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */ +#if configUSE_16_BIT_TICKS == 1 + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U + #define eventWAIT_FOR_ALL_BITS 0x0400U + #define eventEVENT_BITS_CONTROL_BYTES 0xff00U +#else + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL + #define eventWAIT_FOR_ALL_BITS 0x04000000UL + #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL +#endif + +typedef struct xEventGroupDefinition +{ + EventBits_t uxEventBits; + List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */ + + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxEventGroupNumber; + #endif + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */ + #endif +} EventGroup_t; + +/*-----------------------------------------------------------*/ + +/* + * Test the bits set in uxCurrentEventBits to see if the wait condition is met. + * The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is + * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor + * are also set in uxCurrentEventBits. If xWaitForAllBits is pdFALSE then the + * wait condition is met if any of the bits set in uxBitsToWait for are also set + * in uxCurrentEventBits. + */ +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) + { + EventGroup_t *pxEventBits; + + /* A StaticEventGroup_t object must be provided. */ + configASSERT( pxEventGroupBuffer ); + + #if( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + variable of type StaticEventGroup_t equals the size of the real + event group structure. */ + volatile size_t xSize = sizeof( StaticEventGroup_t ); + configASSERT( xSize == sizeof( EventGroup_t ) ); + } + #endif /* configASSERT_DEFINED */ + + /* The user has provided a statically allocated event group - use it. */ + pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 EventGroup_t and StaticEventGroup_t are guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note that + this event group was created statically in case the event group + is later deleted. */ + pxEventBits->ucStaticallyAllocated = pdTRUE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + traceEVENT_GROUP_CREATE_FAILED(); + } + + return ( EventGroupHandle_t ) pxEventBits; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreate( void ) + { + EventGroup_t *pxEventBits; + + /* Allocate the event group. */ + pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note this + event group was allocated statically in case the event group is + later deleted. */ + pxEventBits->ucStaticallyAllocated = pdFALSE; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + traceEVENT_GROUP_CREATE_FAILED(); + } + + return ( EventGroupHandle_t ) pxEventBits; + } + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) +{ +EventBits_t uxOriginalBitValue, uxReturn; +EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +BaseType_t xAlreadyYielded; +BaseType_t xTimeoutOccurred = pdFALSE; + + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + uxOriginalBitValue = pxEventBits->uxEventBits; + + ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet ); + + if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + /* All the rendezvous bits are now set - no need to block. */ + uxReturn = ( uxOriginalBitValue | uxBitsToSet ); + + /* Rendezvous always clear the bits. They will have been cleared + already unless this is the only task in the rendezvous. */ + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + + xTicksToWait = 0; + } + else + { + if( xTicksToWait != ( TickType_t ) 0 ) + { + traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ); + + /* Store the bits that the calling task is waiting for in the + task's event list item so the kernel knows when a match is + found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait ); + + /* This assignment is obsolete as uxReturn will get set after + the task unblocks, but some compilers mistakenly generate a + warning about uxReturn being returned without being set if the + assignment is omitted. */ + uxReturn = 0; + } + else + { + /* The rendezvous bits were not set, but no block time was + specified - just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + xTimeoutOccurred = pdTRUE; + } + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + point either the required bits were set or the block time expired. If + the required bits were set they will have been stored in the task's + event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + /* The task timed out, just return the current event bit value. */ + taskENTER_CRITICAL(); + { + uxReturn = pxEventBits->uxEventBits; + + /* Although the task got here because it timed out before the + bits it was waiting for were set, it is possible that since it + unblocked another task has set the bits. If this is the case + then it needs to clear the bits before exiting. */ + if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* Control bits might be set as the task had blocked should not be + returned. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + + traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) +{ +EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventBits_t uxReturn, uxControlBits = 0; +BaseType_t xWaitConditionMet, xAlreadyYielded; +BaseType_t xTimeoutOccurred = pdFALSE; + + /* Check the user is not attempting to wait on the bits used by the kernel + itself, and that at least one bit is being requested. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits; + + /* Check to see if the wait condition is already met or not. */ + xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits ); + + if( xWaitConditionMet != pdFALSE ) + { + /* The wait condition has already been met so there is no need to + block. */ + uxReturn = uxCurrentEventBits; + xTicksToWait = ( TickType_t ) 0; + + /* Clear the wait bits if requested to do so. */ + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The wait condition has not been met, but no block time was + specified, so just return the current value. */ + uxReturn = uxCurrentEventBits; + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task is going to block to wait for its required bits to be + set. uxControlBits are used to remember the specified behaviour of + this call to xEventGroupWaitBits() - for use when the event bits + unblock the task. */ + if( xClearOnExit != pdFALSE ) + { + uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWaitForAllBits != pdFALSE ) + { + uxControlBits |= eventWAIT_FOR_ALL_BITS; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the bits that the calling task is waiting for in the + task's event list item so the kernel knows when a match is + found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait ); + + /* This is obsolete as it will get set after the task unblocks, but + some compilers mistakenly generate a warning about the variable + being returned without being set if it is not done. */ + uxReturn = 0; + + traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ); + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + point either the required bits were set or the block time expired. If + the required bits were set they will have been stored in the task's + event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + taskENTER_CRITICAL(); + { + /* The task timed out, just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + + /* It is possible that the event bits were updated between this + task leaving the Blocked state and running again. */ + if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE ) + { + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + xTimeoutOccurred = pdTRUE; + } + taskEXIT_CRITICAL(); + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* The task blocked so control bits may have been set. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) +{ +EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventBits_t uxReturn; + + /* Check the user is not attempting to clear the bits used by the kernel + itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + taskENTER_CRITICAL(); + { + traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ); + + /* The value returned is the event group value prior to the bits being + cleared. */ + uxReturn = pxEventBits->uxEventBits; + + /* Clear the bits. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); + + return xReturn; + } + +#endif +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) +{ +UBaseType_t uxSavedInterruptStatus; +EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventBits_t uxReturn; + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + uxReturn = pxEventBits->uxEventBits; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) +{ +ListItem_t *pxListItem, *pxNext; +ListItem_t const *pxListEnd; +List_t *pxList; +EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits; +EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +BaseType_t xMatchFound = pdFALSE; + + /* Check the user is not attempting to set the bits used by the kernel + itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + pxList = &( pxEventBits->xTasksWaitingForBits ); + pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + vTaskSuspendAll(); + { + traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ); + + pxListItem = listGET_HEAD_ENTRY( pxList ); + + /* Set the bits. */ + pxEventBits->uxEventBits |= uxBitsToSet; + + /* See if the new bit value should unblock any tasks. */ + while( pxListItem != pxListEnd ) + { + pxNext = listGET_NEXT( pxListItem ); + uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem ); + xMatchFound = pdFALSE; + + /* Split the bits waited for from the control bits. */ + uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES; + uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES; + + if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 ) + { + /* Just looking for single bit being set. */ + if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 ) + { + xMatchFound = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor ) + { + /* All bits are set. */ + xMatchFound = pdTRUE; + } + else + { + /* Need all bits to be set, but not all the bits were set. */ + } + + if( xMatchFound != pdFALSE ) + { + /* The bits match. Should the bits be cleared on exit? */ + if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 ) + { + uxBitsToClear |= uxBitsWaitedFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the actual event flag value in the task's event list + item before removing the task from the event list. The + eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows + that is was unblocked due to its required bits matching, rather + than because it timed out. */ + vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + /* Move onto the next list item. Note pxListItem->pxNext is not + used here as the list item may have been removed from the event list + and inserted into the ready/pending reading list. */ + pxListItem = pxNext; + } + + /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT + bit was set in the control word. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + ( void ) xTaskResumeAll(); + + return pxEventBits->uxEventBits; +} +/*-----------------------------------------------------------*/ + +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) +{ +EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); + + vTaskSuspendAll(); + { + traceEVENT_GROUP_DELETE( xEventGroup ); + + while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 ) + { + /* Unblock the task, returning 0 as the event list is being deleted + and cannot therefore have any bits set. */ + configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) ); + vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + #if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) + { + /* The event group can only have been allocated dynamically - free + it again. */ + vPortFree( pxEventBits ); + } + #elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + { + /* The event group could have been allocated statically or + dynamically, so check before attempting to free the memory. */ + if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) + { + vPortFree( pxEventBits ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + } + ( void ) xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'set bits' command that was pended from +an interrupt. */ +void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) +{ + ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'clear bits' command that was pended from +an interrupt. */ +void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) +{ + ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) +{ +BaseType_t xWaitConditionMet = pdFALSE; + + if( xWaitForAllBits == pdFALSE ) + { + /* Task only has to wait for one bit within uxBitsToWaitFor to be + set. Is one already set? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Task has to wait for all the bits in uxBitsToWaitFor to be set. + Are they set already? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return xWaitConditionMet; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); + + return xReturn; + } + +#endif +/*-----------------------------------------------------------*/ + +#if (configUSE_TRACE_FACILITY == 1) + + UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) + { + UBaseType_t xReturn; + EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; + + if( xEventGroup == NULL ) + { + xReturn = 0; + } + else + { + xReturn = pxEventBits->uxEventGroupNumber; + } + + return xReturn; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber ) + { + ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/FreeRTOS.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/FreeRTOS.h new file mode 100644 index 00000000..78d176a0 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/FreeRTOS.h @@ -0,0 +1,1168 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef INC_FREERTOS_H +#define INC_FREERTOS_H + +/* + * Include the generic headers required for the FreeRTOS port being used. + */ +#include + +/* + * If stdint.h cannot be located then: + * + If using GCC ensure the -nostdint options is *not* being used. + * + Ensure the project's include path includes the directory in which your + * compiler stores stdint.h. + * + Set any compiler options necessary for it to support C99, as technically + * stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any + * other way). + * + The FreeRTOS download includes a simple stdint.h definition that can be + * used in cases where none is provided by the compiler. The files only + * contains the typedefs required to build FreeRTOS. Read the instructions + * in FreeRTOS/source/stdint.readme for more information. + */ +#include /* READ COMMENT ABOVE. */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Application specific configuration options. */ +#include "FreeRTOSConfig.h" + +/* Basic FreeRTOS definitions. */ +#include "projdefs.h" + +/* Definitions specific to the port being used. */ +#include "portable.h" + +/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */ +#ifndef configUSE_NEWLIB_REENTRANT + #define configUSE_NEWLIB_REENTRANT 0 +#endif + +/* Required if struct _reent is used. */ +#if ( configUSE_NEWLIB_REENTRANT == 1 ) + #include +#endif +/* + * Check all the required application specific macros have been defined. + * These macros are application specific and (as downloaded) are defined + * within FreeRTOSConfig.h. + */ + +#ifndef configMINIMAL_STACK_SIZE + #error Missing definition: configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h. configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task. Refer to the demo project provided for your port for a suitable value. +#endif + +#ifndef configMAX_PRIORITIES + #error Missing definition: configMAX_PRIORITIES must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#if configMAX_PRIORITIES < 1 + #error configMAX_PRIORITIES must be defined to be greater than or equal to 1. +#endif + +#ifndef configUSE_PREEMPTION + #error Missing definition: configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_IDLE_HOOK + #error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_TICK_HOOK + #error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_16_BIT_TICKS + #error Missing definition: configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_CO_ROUTINES + #define configUSE_CO_ROUTINES 0 +#endif + +#ifndef INCLUDE_vTaskPrioritySet + #define INCLUDE_vTaskPrioritySet 0 +#endif + +#ifndef INCLUDE_uxTaskPriorityGet + #define INCLUDE_uxTaskPriorityGet 0 +#endif + +#ifndef INCLUDE_vTaskDelete + #define INCLUDE_vTaskDelete 0 +#endif + +#ifndef INCLUDE_vTaskSuspend + #define INCLUDE_vTaskSuspend 0 +#endif + +#ifndef INCLUDE_vTaskDelayUntil + #define INCLUDE_vTaskDelayUntil 0 +#endif + +#ifndef INCLUDE_vTaskDelay + #define INCLUDE_vTaskDelay 0 +#endif + +#ifndef INCLUDE_xTaskGetIdleTaskHandle + #define INCLUDE_xTaskGetIdleTaskHandle 0 +#endif + +#ifndef INCLUDE_xTaskAbortDelay + #define INCLUDE_xTaskAbortDelay 0 +#endif + +#ifndef INCLUDE_xQueueGetMutexHolder + #define INCLUDE_xQueueGetMutexHolder 0 +#endif + +#ifndef INCLUDE_xSemaphoreGetMutexHolder + #define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder +#endif + +#ifndef INCLUDE_xTaskGetHandle + #define INCLUDE_xTaskGetHandle 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark + #define INCLUDE_uxTaskGetStackHighWaterMark 0 +#endif + +#ifndef INCLUDE_eTaskGetState + #define INCLUDE_eTaskGetState 0 +#endif + +#ifndef INCLUDE_xTaskResumeFromISR + #define INCLUDE_xTaskResumeFromISR 1 +#endif + +#ifndef INCLUDE_xTimerPendFunctionCall + #define INCLUDE_xTimerPendFunctionCall 0 +#endif + +#ifndef INCLUDE_xTaskGetSchedulerState + #define INCLUDE_xTaskGetSchedulerState 0 +#endif + +#ifndef INCLUDE_xTaskGetCurrentTaskHandle + #define INCLUDE_xTaskGetCurrentTaskHandle 0 +#endif + +#if configUSE_CO_ROUTINES != 0 + #ifndef configMAX_CO_ROUTINE_PRIORITIES + #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1. + #endif +#endif + +#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK + #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 +#endif + +#ifndef configUSE_APPLICATION_TASK_TAG + #define configUSE_APPLICATION_TASK_TAG 0 +#endif + +#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 +#endif + +#ifndef configUSE_RECURSIVE_MUTEXES + #define configUSE_RECURSIVE_MUTEXES 0 +#endif + +#ifndef configUSE_MUTEXES + #define configUSE_MUTEXES 0 +#endif + +#ifndef configUSE_TIMERS + #define configUSE_TIMERS 0 +#endif + +#ifndef configUSE_COUNTING_SEMAPHORES + #define configUSE_COUNTING_SEMAPHORES 0 +#endif + +#ifndef configUSE_ALTERNATIVE_API + #define configUSE_ALTERNATIVE_API 0 +#endif + +#ifndef portCRITICAL_NESTING_IN_TCB + #define portCRITICAL_NESTING_IN_TCB 0 +#endif + +#ifndef configMAX_TASK_NAME_LEN + #define configMAX_TASK_NAME_LEN 16 +#endif + +#ifndef configIDLE_SHOULD_YIELD + #define configIDLE_SHOULD_YIELD 1 +#endif + +#if configMAX_TASK_NAME_LEN < 1 + #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h +#endif + +#ifndef configASSERT + #define configASSERT( x ) + #define configASSERT_DEFINED 0 +#else + #define configASSERT_DEFINED 1 +#endif + +/* The timers module relies on xTaskGetSchedulerState(). */ +#if configUSE_TIMERS == 1 + + #ifndef configTIMER_TASK_PRIORITY + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined. + #endif /* configTIMER_TASK_PRIORITY */ + + #ifndef configTIMER_QUEUE_LENGTH + #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined. + #endif /* configTIMER_QUEUE_LENGTH */ + + #ifndef configTIMER_TASK_STACK_DEPTH + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined. + #endif /* configTIMER_TASK_STACK_DEPTH */ + +#endif /* configUSE_TIMERS */ + +#ifndef portSET_INTERRUPT_MASK_FROM_ISR + #define portSET_INTERRUPT_MASK_FROM_ISR() 0 +#endif + +#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue +#endif + +#ifndef portCLEAN_UP_TCB + #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef portPRE_TASK_DELETE_HOOK + #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending ) +#endif + +#ifndef portSETUP_TCB + #define portSETUP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef configQUEUE_REGISTRY_SIZE + #define configQUEUE_REGISTRY_SIZE 0U +#endif + +#if ( configQUEUE_REGISTRY_SIZE < 1 ) + #define vQueueAddToRegistry( xQueue, pcName ) + #define vQueueUnregisterQueue( xQueue ) + #define pcQueueGetName( xQueue ) +#endif + +#ifndef portPOINTER_SIZE_TYPE + #define portPOINTER_SIZE_TYPE uint32_t +#endif + +/* Remove any unused trace macros. */ +#ifndef traceSTART + /* Used to perform any necessary initialisation - for example, open a file + into which trace is to be written. */ + #define traceSTART() +#endif + +#ifndef traceEND + /* Use to close a trace, for example close a file into which trace has been + written. */ + #define traceEND() +#endif + +#ifndef traceTASK_SWITCHED_IN + /* Called after a task has been selected to run. pxCurrentTCB holds a pointer + to the task control block of the selected task. */ + #define traceTASK_SWITCHED_IN() +#endif + +#ifndef traceINCREASE_TICK_COUNT + /* Called before stepping the tick count after waking from tickless idle + sleep. */ + #define traceINCREASE_TICK_COUNT( x ) +#endif + +#ifndef traceLOW_POWER_IDLE_BEGIN + /* Called immediately before entering tickless idle. */ + #define traceLOW_POWER_IDLE_BEGIN() +#endif + +#ifndef traceLOW_POWER_IDLE_END + /* Called when returning to the Idle task after a tickless idle. */ + #define traceLOW_POWER_IDLE_END() +#endif + +#ifndef traceTASK_SWITCHED_OUT + /* Called before a task has been selected to run. pxCurrentTCB holds a pointer + to the task control block of the task being switched out. */ + #define traceTASK_SWITCHED_OUT() +#endif + +#ifndef traceTASK_PRIORITY_INHERIT + /* Called when a task attempts to take a mutex that is already held by a + lower priority task. pxTCBOfMutexHolder is a pointer to the TCB of the task + that holds the mutex. uxInheritedPriority is the priority the mutex holder + will inherit (the priority of the task that is attempting to obtain the + muted. */ + #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority ) +#endif + +#ifndef traceTASK_PRIORITY_DISINHERIT + /* Called when a task releases a mutex, the holding of which had resulted in + the task inheriting the priority of a higher priority task. + pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the + mutex. uxOriginalPriority is the task's configured (base) priority. */ + #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_RECEIVE + /* Task is about to block because it cannot read from a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the read was attempted. pxCurrentTCB points to the TCB of the + task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_PEEK + /* Task is about to block because it cannot read from a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the read was attempted. pxCurrentTCB points to the TCB of the + task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_SEND + /* Task is about to block because it cannot write to a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the write was attempted. pxCurrentTCB points to the TCB of the + task that attempted the write. */ + #define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) +#endif + +#ifndef configCHECK_FOR_STACK_OVERFLOW + #define configCHECK_FOR_STACK_OVERFLOW 0 +#endif + +#ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 0 +#endif + +#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H + #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 +#endif + +/* The following event macros are embedded in the kernel API calls. */ + +#ifndef traceMOVED_TASK_TO_READY_STATE + #define traceMOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef tracePOST_MOVED_TASK_TO_READY_STATE + #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef traceQUEUE_CREATE + #define traceQUEUE_CREATE( pxNewQueue ) +#endif + +#ifndef traceQUEUE_CREATE_FAILED + #define traceQUEUE_CREATE_FAILED( ucQueueType ) +#endif + +#ifndef traceCREATE_MUTEX + #define traceCREATE_MUTEX( pxNewQueue ) +#endif + +#ifndef traceCREATE_MUTEX_FAILED + #define traceCREATE_MUTEX_FAILED() +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE + #define traceGIVE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED + #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE + #define traceTAKE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED + #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE + #define traceCREATE_COUNTING_SEMAPHORE() +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED + #define traceCREATE_COUNTING_SEMAPHORE_FAILED() +#endif + +#ifndef traceQUEUE_SEND + #define traceQUEUE_SEND( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FAILED + #define traceQUEUE_SEND_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE + #define traceQUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK + #define traceQUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FAILED + #define traceQUEUE_PEEK_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR + #define traceQUEUE_PEEK_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FAILED + #define traceQUEUE_RECEIVE_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR + #define traceQUEUE_SEND_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR_FAILED + #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR + #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED + #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED + #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_DELETE + #define traceQUEUE_DELETE( pxQueue ) +#endif + +#ifndef traceTASK_CREATE + #define traceTASK_CREATE( pxNewTCB ) +#endif + +#ifndef traceTASK_CREATE_FAILED + #define traceTASK_CREATE_FAILED() +#endif + +#ifndef traceTASK_DELETE + #define traceTASK_DELETE( pxTaskToDelete ) +#endif + +#ifndef traceTASK_DELAY_UNTIL + #define traceTASK_DELAY_UNTIL( x ) +#endif + +#ifndef traceTASK_DELAY + #define traceTASK_DELAY() +#endif + +#ifndef traceTASK_PRIORITY_SET + #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) +#endif + +#ifndef traceTASK_SUSPEND + #define traceTASK_SUSPEND( pxTaskToSuspend ) +#endif + +#ifndef traceTASK_RESUME + #define traceTASK_RESUME( pxTaskToResume ) +#endif + +#ifndef traceTASK_RESUME_FROM_ISR + #define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) +#endif + +#ifndef traceTASK_INCREMENT_TICK + #define traceTASK_INCREMENT_TICK( xTickCount ) +#endif + +#ifndef traceTIMER_CREATE + #define traceTIMER_CREATE( pxNewTimer ) +#endif + +#ifndef traceTIMER_CREATE_FAILED + #define traceTIMER_CREATE_FAILED() +#endif + +#ifndef traceTIMER_COMMAND_SEND + #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn ) +#endif + +#ifndef traceTIMER_EXPIRED + #define traceTIMER_EXPIRED( pxTimer ) +#endif + +#ifndef traceTIMER_COMMAND_RECEIVED + #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue ) +#endif + +#ifndef traceMALLOC + #define traceMALLOC( pvAddress, uiSize ) +#endif + +#ifndef traceFREE + #define traceFREE( pvAddress, uiSize ) +#endif + +#ifndef traceEVENT_GROUP_CREATE + #define traceEVENT_GROUP_CREATE( xEventGroup ) +#endif + +#ifndef traceEVENT_GROUP_CREATE_FAILED + #define traceEVENT_GROUP_CREATE_FAILED() +#endif + +#ifndef traceEVENT_GROUP_SYNC_BLOCK + #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_SYNC_END + #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK + #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_END + #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS + #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR + #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS + #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR + #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_DELETE + #define traceEVENT_GROUP_DELETE( xEventGroup ) +#endif + +#ifndef tracePEND_FUNC_CALL + #define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret) +#endif + +#ifndef tracePEND_FUNC_CALL_FROM_ISR + #define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret) +#endif + +#ifndef traceQUEUE_REGISTRY_ADD + #define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName) +#endif + +#ifndef traceTASK_NOTIFY_TAKE_BLOCK + #define traceTASK_NOTIFY_TAKE_BLOCK() +#endif + +#ifndef traceTASK_NOTIFY_TAKE + #define traceTASK_NOTIFY_TAKE() +#endif + +#ifndef traceTASK_NOTIFY_WAIT_BLOCK + #define traceTASK_NOTIFY_WAIT_BLOCK() +#endif + +#ifndef traceTASK_NOTIFY_WAIT + #define traceTASK_NOTIFY_WAIT() +#endif + +#ifndef traceTASK_NOTIFY + #define traceTASK_NOTIFY() +#endif + +#ifndef traceTASK_NOTIFY_FROM_ISR + #define traceTASK_NOTIFY_FROM_ISR() +#endif + +#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR + #define traceTASK_NOTIFY_GIVE_FROM_ISR() +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_FAILED + #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED + #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE + #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_DELETE + #define traceSTREAM_BUFFER_DELETE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RESET + #define traceSTREAM_BUFFER_RESET( xStreamBuffer ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND + #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND + #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FAILED + #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR + #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE + #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE + #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED + #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR + #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef configGENERATE_RUN_TIME_STATS + #define configGENERATE_RUN_TIME_STATS 0 +#endif + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + + #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. + #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */ + + #ifndef portGET_RUN_TIME_COUNTER_VALUE + #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE + #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information. + #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */ + #endif /* portGET_RUN_TIME_COUNTER_VALUE */ + +#endif /* configGENERATE_RUN_TIME_STATS */ + +#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#endif + +#ifndef configUSE_MALLOC_FAILED_HOOK + #define configUSE_MALLOC_FAILED_HOOK 0 +#endif + +#ifndef portPRIVILEGE_BIT + #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 ) +#endif + +#ifndef portYIELD_WITHIN_API + #define portYIELD_WITHIN_API portYIELD +#endif + +#ifndef portSUPPRESS_TICKS_AND_SLEEP + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) +#endif + +#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP + #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2 +#endif + +#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2 + #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2 +#endif + +#ifndef configUSE_TICKLESS_IDLE + #define configUSE_TICKLESS_IDLE 0 +#endif + +#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING + #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPRE_SLEEP_PROCESSING + #define configPRE_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPOST_SLEEP_PROCESSING + #define configPOST_SLEEP_PROCESSING( x ) +#endif + +#ifndef configUSE_QUEUE_SETS + #define configUSE_QUEUE_SETS 0 +#endif + +#ifndef portTASK_USES_FLOATING_POINT + #define portTASK_USES_FLOATING_POINT() +#endif + +#ifndef portTASK_CALLS_SECURE_FUNCTIONS + #define portTASK_CALLS_SECURE_FUNCTIONS() +#endif + +#ifndef configUSE_TIME_SLICING + #define configUSE_TIME_SLICING 1 +#endif + +#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 +#endif + +#ifndef configUSE_STATS_FORMATTING_FUNCTIONS + #define configUSE_STATS_FORMATTING_FUNCTIONS 0 +#endif + +#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() +#endif + +#ifndef configUSE_TRACE_FACILITY + #define configUSE_TRACE_FACILITY 0 +#endif + +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +#ifndef mtCOVERAGE_TEST_DELAY + #define mtCOVERAGE_TEST_DELAY() +#endif + +#ifndef portASSERT_IF_IN_ISR + #define portASSERT_IF_IN_ISR() +#endif + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif + +#ifndef configAPPLICATION_ALLOCATED_HEAP + #define configAPPLICATION_ALLOCATED_HEAP 0 +#endif + +#ifndef configUSE_TASK_NOTIFICATIONS + #define configUSE_TASK_NOTIFICATIONS 1 +#endif + +#ifndef portTICK_TYPE_IS_ATOMIC + #define portTICK_TYPE_IS_ATOMIC 0 +#endif + +#ifndef configSUPPORT_STATIC_ALLOCATION + /* Defaults to 0 for backward compatibility. */ + #define configSUPPORT_STATIC_ALLOCATION 0 +#endif + +#ifndef configSUPPORT_DYNAMIC_ALLOCATION + /* Defaults to 1 for backward compatibility. */ + #define configSUPPORT_DYNAMIC_ALLOCATION 1 +#endif + +#ifndef configSTACK_DEPTH_TYPE + /* Defaults to uint16_t for backward compatibility, but can be overridden + in FreeRTOSConfig.h if uint16_t is too restrictive. */ + #define configSTACK_DEPTH_TYPE uint16_t +#endif + +/* Sanity check the configuration. */ +#if( configUSE_TICKLESS_IDLE != 0 ) + #if( INCLUDE_vTaskSuspend != 1 ) + #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0 + #endif /* INCLUDE_vTaskSuspend */ +#endif /* configUSE_TICKLESS_IDLE */ + +#if( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) + #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1. +#endif + +#if( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) ) + #error configUSE_MUTEXES must be set to 1 to use recursive mutexes +#endif + +#ifndef configINITIAL_TICK_COUNT + #define configINITIAL_TICK_COUNT 0 +#endif + +#if( portTICK_TYPE_IS_ATOMIC == 0 ) + /* Either variables of tick type cannot be read atomically, or + portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when + the tick count is returned to the standard critical section macros. */ + #define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) ) +#else + /* The tick type can be read atomically, so critical sections used when the + tick count is returned can be defined away. */ + #define portTICK_TYPE_ENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0 + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x +#endif + +/* Definitions to allow backward compatibility with FreeRTOS versions prior to +V8 if desired. */ +#ifndef configENABLE_BACKWARD_COMPATIBILITY + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#endif + +#ifndef configPRINTF + /* configPRINTF() was not defined, so define it away to nothing. To use + configPRINTF() then define it as follows (where MyPrintFunction() is + provided by the application writer): + + void MyPrintFunction(const char *pcFormat, ... ); + #define configPRINTF( X ) MyPrintFunction X + + Then call like a standard printf() function, but placing brackets around + all parameters so they are passed as a single parameter. For example: + configPRINTF( ("Value = %d", MyVariable) ); */ + #define configPRINTF( X ) +#endif + +#ifndef configMAX + /* The application writer has not provided their own MAX macro, so define + the following generic implementation. */ + #define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) +#endif + +#ifndef configMIN + /* The application writer has not provided their own MAX macro, so define + the following generic implementation. */ + #define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) ) +#endif + +#if configENABLE_BACKWARD_COMPATIBILITY == 1 + #define eTaskStateGet eTaskGetState + #define portTickType TickType_t + #define xTaskHandle TaskHandle_t + #define xQueueHandle QueueHandle_t + #define xSemaphoreHandle SemaphoreHandle_t + #define xQueueSetHandle QueueSetHandle_t + #define xQueueSetMemberHandle QueueSetMemberHandle_t + #define xTimeOutType TimeOut_t + #define xMemoryRegion MemoryRegion_t + #define xTaskParameters TaskParameters_t + #define xTaskStatusType TaskStatus_t + #define xTimerHandle TimerHandle_t + #define xCoRoutineHandle CoRoutineHandle_t + #define pdTASK_HOOK_CODE TaskHookFunction_t + #define portTICK_RATE_MS portTICK_PERIOD_MS + #define pcTaskGetTaskName pcTaskGetName + #define pcTimerGetTimerName pcTimerGetName + #define pcQueueGetQueueName pcQueueGetName + #define vTaskGetTaskInfo vTaskGetInfo + + /* Backward compatibility within the scheduler code only - these definitions + are not really required but are included for completeness. */ + #define tmrTIMER_CALLBACK TimerCallbackFunction_t + #define pdTASK_CODE TaskFunction_t + #define xListItem ListItem_t + #define xList List_t +#endif /* configENABLE_BACKWARD_COMPATIBILITY */ + +#if( configUSE_ALTERNATIVE_API != 0 ) + #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0 +#endif + +/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even +if floating point hardware is otherwise supported by the FreeRTOS port in use. +This constant is not supported by all FreeRTOS ports that include floating +point support. */ +#ifndef configUSE_TASK_FPU_SUPPORT + #define configUSE_TASK_FPU_SUPPORT 1 +#endif + +/* + * In line with software engineering best practice, FreeRTOS implements a strict + * data hiding policy, so the real structures used by FreeRTOS to maintain the + * state of tasks, queues, semaphores, etc. are not accessible to the application + * code. However, if the application writer wants to statically allocate such + * an object then the size of the object needs to be know. Dummy structures + * that are guaranteed to have the same size and alignment requirements of the + * real objects are used for this purpose. The dummy list and list item + * structures below are used for inclusion in such a dummy structure. + */ +struct xSTATIC_LIST_ITEM +{ + TickType_t xDummy1; + void *pvDummy2[ 4 ]; +}; +typedef struct xSTATIC_LIST_ITEM StaticListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +struct xSTATIC_MINI_LIST_ITEM +{ + TickType_t xDummy1; + void *pvDummy2[ 2 ]; +}; +typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +typedef struct xSTATIC_LIST +{ + UBaseType_t uxDummy1; + void *pvDummy2; + StaticMiniListItem_t xDummy3; +} StaticList_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Task structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a task then + * the size of the task object needs to be know. The StaticTask_t structure + * below is provided for this purpose. Its sizes and alignment requirements are + * guaranteed to match those of the genuine structure, no matter which + * architecture is being used, and no matter how the values in FreeRTOSConfig.h + * are set. Its contents are somewhat obfuscated in the hope users will + * recognise that it would be unwise to make direct use of the structure members. + */ +typedef struct xSTATIC_TCB +{ + void *pxDummy1; + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xDummy2; + #endif + StaticListItem_t xDummy3[ 2 ]; + UBaseType_t uxDummy5; + void *pxDummy6; + uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ]; + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + void *pxDummy8; + #endif + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxDummy9; + #endif + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy10[ 2 ]; + #endif + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxDummy12[ 2 ]; + #endif + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + void *pxDummy14; + #endif + #if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void *pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + uint32_t ulDummy16; + #endif + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + struct _reent xDummy17; + #endif + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + uint32_t ulDummy18; + uint8_t ucDummy19; + #endif + #if( ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) || ( portUSING_MPU_WRAPPERS == 1 ) ) + uint8_t uxDummy20; + #endif + + #if( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDummy21; + #endif + +} StaticTask_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Queue structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a queue + * then the size of the queue object needs to be know. The StaticQueue_t + * structure below is provided for this purpose. Its sizes and alignment + * requirements are guaranteed to match those of the genuine structure, no + * matter which architecture is being used, and no matter how the values in + * FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in the hope + * users will recognise that it would be unwise to make direct use of the + * structure members. + */ +typedef struct xSTATIC_QUEUE +{ + void *pvDummy1[ 3 ]; + + union + { + void *pvDummy2; + UBaseType_t uxDummy2; + } u; + + StaticList_t xDummy3[ 2 ]; + UBaseType_t uxDummy4[ 3 ]; + uint8_t ucDummy5[ 2 ]; + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy6; + #endif + + #if ( configUSE_QUEUE_SETS == 1 ) + void *pvDummy7; + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy8; + uint8_t ucDummy9; + #endif + +} StaticQueue_t; +typedef StaticQueue_t StaticSemaphore_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the event group structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create an event group then the size of the event group object needs to be + * know. The StaticEventGroup_t structure below is provided for this purpose. + * Its sizes and alignment requirements are guaranteed to match those of the + * genuine structure, no matter which architecture is being used, and no matter + * how the values in FreeRTOSConfig.h are set. Its contents are somewhat + * obfuscated in the hope users will recognise that it would be unwise to make + * direct use of the structure members. + */ +typedef struct xSTATIC_EVENT_GROUP +{ + TickType_t xDummy1; + StaticList_t xDummy2; + + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy3; + #endif + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy4; + #endif + +} StaticEventGroup_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the software timer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a software timer then the size of the queue object needs to be know. + * The StaticTimer_t structure below is provided for this purpose. Its sizes + * and alignment requirements are guaranteed to match those of the genuine + * structure, no matter which architecture is being used, and no matter how the + * values in FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in + * the hope users will recognise that it would be unwise to make direct use of + * the structure members. + */ +typedef struct xSTATIC_TIMER +{ + void *pvDummy1; + StaticListItem_t xDummy2; + TickType_t xDummy3; + UBaseType_t uxDummy4; + void *pvDummy5[ 2 ]; + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy6; + #endif + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy7; + #endif + +} StaticTimer_t; + +/* +* In line with software engineering best practice, especially when supplying a +* library that is likely to change in future versions, FreeRTOS implements a +* strict data hiding policy. This means the stream buffer structure used +* internally by FreeRTOS is not accessible to application code. However, if +* the application writer wants to statically allocate the memory required to +* create a stream buffer then the size of the stream buffer object needs to be +* know. The StaticStreamBuffer_t structure below is provided for this purpose. +* Its size and alignment requirements are guaranteed to match those of the +* genuine structure, no matter which architecture is being used, and no matter +* how the values in FreeRTOSConfig.h are set. Its contents are somewhat +* obfuscated in the hope users will recognise that it would be unwise to make +* direct use of the structure members. +*/ +typedef struct xSTATIC_STREAM_BUFFER +{ + size_t uxDummy1[ 4 ]; + void * pvDummy2[ 3 ]; + uint8_t ucDummy3; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy4; + #endif +} StaticStreamBuffer_t; + +/* Message buffers are built on stream buffers. */ +typedef StaticStreamBuffer_t StaticMessageBuffer_t; + +#ifdef __cplusplus +} +#endif + +#endif /* INC_FREERTOS_H */ + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/StackMacros.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/StackMacros.h new file mode 100644 index 00000000..534f0045 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/StackMacros.h @@ -0,0 +1,133 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef STACK_MACROS_H +#define STACK_MACROS_H + +#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */ + #warning The name of this file has changed to stack_macros.h. Please update your code accordingly. This source file (which has the original name) will be removed in future released. +#endif + +/* + * Call the stack overflow hook function if the stack of the task being swapped + * out is currently overflowed, or looks like it might have overflowed in the + * past. + * + * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check + * the current stack state only - comparing the current top of stack value to + * the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1 + * will also cause the last few stack bytes to be checked to ensure the value + * to which the bytes were set when the task was created have not been + * overwritten. Note this second test does not guarantee that an overflowed + * stack will always be recognised. + */ + +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) ) + + /* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) ) + + /* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \ + const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \ + \ + if( ( pulStack[ 0 ] != ulCheckValue ) || \ + ( pulStack[ 1 ] != ulCheckValue ) || \ + ( pulStack[ 2 ] != ulCheckValue ) || \ + ( pulStack[ 3 ] != ulCheckValue ) ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack; \ + static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \ + \ + \ + pcEndOfStack -= sizeof( ucExpectedStackBytes ); \ + \ + /* Has the extremity of the task stack ever been written over? */ \ + if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +/* Remove stack overflow macro if not being used. */ +#ifndef taskCHECK_FOR_STACK_OVERFLOW + #define taskCHECK_FOR_STACK_OVERFLOW() +#endif + + + +#endif /* STACK_MACROS_H */ + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/croutine.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/croutine.h new file mode 100644 index 00000000..f4c54d2e --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/croutine.h @@ -0,0 +1,720 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef CO_ROUTINE_H +#define CO_ROUTINE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include croutine.h" +#endif + +#include "list.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Used to hide the implementation of the co-routine control block. The +control block structure however has to be included in the header due to +the macro implementation of the co-routine functionality. */ +typedef void * CoRoutineHandle_t; + +/* Defines the prototype to which co-routine functions must conform. */ +typedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t ); + +typedef struct corCoRoutineControlBlock +{ + crCOROUTINE_CODE pxCoRoutineFunction; + ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ + ListItem_t xEventListItem; /*< List item used to place the CRCB in event lists. */ + UBaseType_t uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ + UBaseType_t uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ + uint16_t uxState; /*< Used internally by the co-routine implementation. */ +} CRCB_t; /* Co-routine control block. Note must be identical in size down to uxPriority with TCB_t. */ + +/** + * croutine. h + *
+ BaseType_t xCoRoutineCreate(
+                                 crCOROUTINE_CODE pxCoRoutineCode,
+                                 UBaseType_t uxPriority,
+                                 UBaseType_t uxIndex
+                               );
+ * + * Create a new co-routine and add it to the list of co-routines that are + * ready to run. + * + * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine + * functions require special syntax - see the co-routine section of the WEB + * documentation for more information. + * + * @param uxPriority The priority with respect to other co-routines at which + * the co-routine will run. + * + * @param uxIndex Used to distinguish between different co-routines that + * execute the same function. See the example below and the co-routine section + * of the WEB documentation for further information. + * + * @return pdPASS if the co-routine was successfully created and added to a ready + * list, otherwise an error code defined with ProjDefs.h. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ static const char cLedToFlash[ 2 ] = { 5, 6 };
+ static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // This co-routine just delays for a fixed period, then toggles
+         // an LED.  Two co-routines are created using this function, so
+         // the uxIndex parameter is used to tell the co-routine which
+         // LED to flash and how int32_t to delay.  This assumes xQueue has
+         // already been created.
+         vParTestToggleLED( cLedToFlash[ uxIndex ] );
+         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+
+ // Function that creates two co-routines.
+ void vOtherFunction( void )
+ {
+ uint8_t ucParameterToPass;
+ TaskHandle_t xHandle;
+
+     // Create two co-routines at priority 0.  The first is given index 0
+     // so (from the code above) toggles LED 5 every 200 ticks.  The second
+     // is given index 1 so toggles LED 6 every 400 ticks.
+     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+     {
+         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+     }
+ }
+
+ * \defgroup xCoRoutineCreate xCoRoutineCreate + * \ingroup Tasks + */ +BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex ); + + +/** + * croutine. h + *
+ void vCoRoutineSchedule( void );
+ * + * Run a co-routine. + * + * vCoRoutineSchedule() executes the highest priority co-routine that is able + * to run. The co-routine will execute until it either blocks, yields or is + * preempted by a task. Co-routines execute cooperatively so one + * co-routine cannot be preempted by another, but can be preempted by a task. + * + * If an application comprises of both tasks and co-routines then + * vCoRoutineSchedule should be called from the idle task (in an idle task + * hook). + * + * Example usage: + 
+ // This idle task hook will schedule a co-routine each time it is called.
+ // The rest of the idle task will execute between co-routine calls.
+ void vApplicationIdleHook( void )
+ {
+	vCoRoutineSchedule();
+ }
+
+ // Alternatively, if you do not require any other part of the idle task to
+ // execute, the idle task hook can call vCoRoutineScheduler() within an
+ // infinite loop.
+ void vApplicationIdleHook( void )
+ {
+    for( ;; )
+    {
+        vCoRoutineSchedule();
+    }
+ }
+
+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule + * \ingroup Tasks + */ +void vCoRoutineSchedule( void ); + +/** + * croutine. h + * 
+ crSTART( CoRoutineHandle_t xHandle );
+ * + * This macro MUST always be called at the start of a co-routine function. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+ * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0: + +/** + * croutine. h + * 
+ crEND();
+ * + * This macro MUST always be called at the end of a co-routine function. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+ * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crEND() } + +/* + * These macros are intended for internal use by the co-routine implementation + * only. The macros should not be used directly by application writers. + */ +#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2): +#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1): + +/** + * croutine. h + *
+ crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );
+ * + * Delay a co-routine for a fixed period of time. + * + * crDELAY can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * @param xHandle The handle of the co-routine to delay. This is the xHandle + * parameter of the co-routine function. + * + * @param xTickToDelay The number of ticks that the co-routine should delay + * for. The actual amount of time this equates to is defined by + * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_PERIOD_MS + * can be used to convert ticks to milliseconds. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ // We are to delay for 200ms.
+ static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+        // Delay for 200ms.
+        crDELAY( xHandle, xDelayTime );
+
+        // Do something here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+ * \defgroup crDELAY crDELAY + * \ingroup Tasks + */ +#define crDELAY( xHandle, xTicksToDelay ) \ + if( ( xTicksToDelay ) > 0 ) \ + { \ + vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \ + } \ + crSET_STATE0( ( xHandle ) ); + +/** + * 
+ crQUEUE_SEND(
+                  CoRoutineHandle_t xHandle,
+                  QueueHandle_t pxQueue,
+                  void *pvItemToQueue,
+                  TickType_t xTicksToWait,
+                  BaseType_t *pxResult
+             )
+ * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_SEND can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue on which the data will be posted. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvItemToQueue A pointer to the data being posted onto the queue. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied from pvItemToQueue into the queue + * itself. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for space to become available on the queue, should space not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example + * below). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully posted onto the queue, otherwise it will be set to an + * error defined within ProjDefs.h. + * + * Example usage: + 
+ // Co-routine function that blocks for a fixed period then posts a number onto
+ // a queue.
+ static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xNumberToPost = 0;
+ static BaseType_t xResult;
+
+    // Co-routines must begin with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // This assumes the queue has already been created.
+        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+
+        if( xResult != pdPASS )
+        {
+            // The message was not posted!
+        }
+
+        // Increment the number to be posted onto the queue.
+        xNumberToPost++;
+
+        // Delay for 100 ticks.
+        crDELAY( xHandle, 100 );
+    }
+
+    // Co-routines must end with a call to crEND().
+    crEND();
+ }
+ * \defgroup crQUEUE_SEND crQUEUE_SEND + * \ingroup Tasks + */ +#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ +{ \ + *( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \ + } \ + if( *pxResult == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *pxResult = pdPASS; \ + } \ +} + +/** + * croutine. h + * 
+  crQUEUE_RECEIVE(
+                     CoRoutineHandle_t xHandle,
+                     QueueHandle_t pxQueue,
+                     void *pvBuffer,
+                     TickType_t xTicksToWait,
+                     BaseType_t *pxResult
+                 )
+ * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_RECEIVE can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue from which the data will be received. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvBuffer The buffer into which the received item is to be copied. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied into pvBuffer. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for data to become available from the queue, should data not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the + * crQUEUE_SEND example). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully retrieved from the queue, otherwise it will be set to + * an error code as defined within ProjDefs.h. + * + * Example usage: + 
+ // A co-routine receives the number of an LED to flash from a queue.  It
+ // blocks on the queue until the number is received.
+ static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xResult;
+ static UBaseType_t uxLEDToFlash;
+
+    // All co-routines must start with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // Wait for data to become available on the queue.
+        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+        if( xResult == pdPASS )
+        {
+            // We received the LED to flash - flash it!
+            vParTestToggleLED( uxLEDToFlash );
+        }
+    }
+
+    crEND();
+ }
+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ +{ \ + *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 ); \ + } \ + if( *( pxResult ) == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *( pxResult ) = pdPASS; \ + } \ +} + +/** + * croutine. h + * 
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvItemToQueue,
+                            BaseType_t xCoRoutinePreviouslyWoken
+                       )
+ * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue + * that is being used from within a co-routine. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto + * the same queue multiple times from a single interrupt. The first call + * should always pass in pdFALSE. Subsequent calls should pass in + * the value returned from the previous call. + * + * @return pdTRUE if a co-routine was woken by posting onto the queue. This is + * used by the ISR to determine if a context switch may be required following + * the ISR. + * + * Example usage: + 
+ // A co-routine that blocks on a queue waiting for characters to be received.
+ static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ char cRxedChar;
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Wait for data to become available on the queue.  This assumes the
+         // queue xCommsRxQueue has already been created!
+         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+         // Was a character received?
+         if( xResult == pdPASS )
+         {
+             // Process the character here.
+         }
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to send characters received on a serial port to
+ // a co-routine.
+ void vUART_ISR( void )
+ {
+ char cRxedChar;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     // We loop around reading characters until there are none left in the UART.
+     while( UART_RX_REG_NOT_EMPTY() )
+     {
+         // Obtain the character from the UART.
+         cRxedChar = UART_RX_REG;
+
+         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
+         // the first time around the loop.  If the post causes a co-routine
+         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+         // In this manner we can ensure that if more than one co-routine is
+         // blocked on the queue only one is woken by this ISR no matter how
+         // many characters are posted to the queue.
+         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+     }
+ }
+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) ) + + +/** + * croutine. h + * 
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvBuffer,
+                            BaseType_t * pxCoRoutineWoken
+                       )
+ * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data + * from a queue that is being used from within a co-routine (a co-routine + * posted to the queue). + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvBuffer A pointer to a buffer into which the received item will be + * placed. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from the queue into + * pvBuffer. + * + * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become + * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a + * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise + * *pxCoRoutineWoken will remain unchanged. + * + * @return pdTRUE an item was successfully received from the queue, otherwise + * pdFALSE. + * + * Example usage: + 
+ // A co-routine that posts a character to a queue then blocks for a fixed
+ // period.  The character is incremented each time.
+ static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // cChar holds its value while this co-routine is blocked and must therefore
+ // be declared static.
+ static char cCharToTx = 'a';
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Send the next character to the queue.
+         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+
+         if( xResult == pdPASS )
+         {
+             // The character was successfully posted to the queue.
+         }
+		 else
+		 {
+			// Could not post the character to the queue.
+		 }
+
+         // Enable the UART Tx interrupt to cause an interrupt in this
+		 // hypothetical UART.  The interrupt will obtain the character
+		 // from the queue and send it.
+		 ENABLE_RX_INTERRUPT();
+
+		 // Increment to the next character then block for a fixed period.
+		 // cCharToTx will maintain its value across the delay as it is
+		 // declared static.
+		 cCharToTx++;
+		 if( cCharToTx > 'x' )
+		 {
+			cCharToTx = 'a';
+		 }
+		 crDELAY( 100 );
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to receive characters to send on a UART.
+ void vUART_ISR( void )
+ {
+ char cCharToTx;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     while( UART_TX_REG_EMPTY() )
+     {
+         // Are there any characters in the queue waiting to be sent?
+		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+		 // is woken by the post - ensuring that only a single co-routine is
+		 // woken no matter how many times we go around this loop.
+         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+		 {
+			 SEND_CHARACTER( cCharToTx );
+		 }
+     }
+ }
+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) ) + +/* + * This function is intended for internal use by the co-routine macros only. + * The macro nature of the co-routine implementation requires that the + * prototype appears here. The function should not be used by application + * writers. + * + * Removes the current co-routine from its ready list and places it in the + * appropriate delayed list. + */ +void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList ); + +/* + * This function is intended for internal use by the queue implementation only. + * The function should not be used by application writers. + * + * Removes the highest priority co-routine from the event list and places it in + * the pending ready list. + */ +BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList ); + +#ifdef __cplusplus +} +#endif + +#endif /* CO_ROUTINE_H */ diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/deprecated_definitions.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/deprecated_definitions.h new file mode 100644 index 00000000..1125673c --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/deprecated_definitions.h @@ -0,0 +1,279 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef DEPRECATED_DEFINITIONS_H +#define DEPRECATED_DEFINITIONS_H + + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a +pre-processor definition was used to ensure the pre-processor found the correct +portmacro.h file for the port being used. That scheme was deprecated in favour +of setting the compiler's include path such that it found the correct +portmacro.h file - removing the need for the constant and allowing the +portmacro.h file to be located anywhere in relation to the port being used. The +definitions below remain in the code for backward compatibility only. New +projects should not use them. */ + +#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT + #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT + #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef GCC_MEGA_AVR + #include "../portable/GCC/ATMega323/portmacro.h" +#endif + +#ifdef IAR_MEGA_AVR + #include "../portable/IAR/ATMega323/portmacro.h" +#endif + +#ifdef MPLAB_PIC24_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_DSPIC_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_PIC18F_PORT + #include "../../Source/portable/MPLAB/PIC18F/portmacro.h" +#endif + +#ifdef MPLAB_PIC32MX_PORT + #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h" +#endif + +#ifdef _FEDPICC + #include "libFreeRTOS/Include/portmacro.h" +#endif + +#ifdef SDCC_CYGNAL + #include "../../Source/portable/SDCC/Cygnal/portmacro.h" +#endif + +#ifdef GCC_ARM7 + #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" +#endif + +#ifdef GCC_ARM7_ECLIPSE + #include "portmacro.h" +#endif + +#ifdef ROWLEY_LPC23xx + #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h" +#endif + +#ifdef IAR_MSP430 + #include "..\..\Source\portable\IAR\MSP430\portmacro.h" +#endif + +#ifdef GCC_MSP430 + #include "../../Source/portable/GCC/MSP430F449/portmacro.h" +#endif + +#ifdef ROWLEY_MSP430 + #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" +#endif + +#ifdef ARM7_LPC21xx_KEIL_RVDS + #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h" +#endif + +#ifdef SAM7_GCC + #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" +#endif + +#ifdef SAM7_IAR + #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" +#endif + +#ifdef SAM9XE_IAR + #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h" +#endif + +#ifdef LPC2000_IAR + #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" +#endif + +#ifdef STR71X_IAR + #include "..\..\Source\portable\IAR\STR71x\portmacro.h" +#endif + +#ifdef STR75X_IAR + #include "..\..\Source\portable\IAR\STR75x\portmacro.h" +#endif + +#ifdef STR75X_GCC + #include "..\..\Source\portable\GCC\STR75x\portmacro.h" +#endif + +#ifdef STR91X_IAR + #include "..\..\Source\portable\IAR\STR91x\portmacro.h" +#endif + +#ifdef GCC_H8S + #include "../../Source/portable/GCC/H8S2329/portmacro.h" +#endif + +#ifdef GCC_AT91FR40008 + #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" +#endif + +#ifdef RVDS_ARMCM3_LM3S102 + #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3_LM3S102 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARM_CM3 + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARMCM3_LM + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef HCS12_CODE_WARRIOR + #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" +#endif + +#ifdef MICROBLAZE_GCC + #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" +#endif + +#ifdef TERN_EE + #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" +#endif + +#ifdef GCC_HCS12 + #include "../../Source/portable/GCC/HCS12/portmacro.h" +#endif + +#ifdef GCC_MCF5235 + #include "../../Source/portable/GCC/MCF5235/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_GCC + #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_CODEWARRIOR + #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h" +#endif + +#ifdef GCC_PPC405 + #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h" +#endif + +#ifdef GCC_PPC440 + #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h" +#endif + +#ifdef _16FX_SOFTUNE + #include "..\..\Source\portable\Softune\MB96340\portmacro.h" +#endif + +#ifdef BCC_INDUSTRIAL_PC_PORT + /* A short file name has to be used in place of the normal + FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef BCC_FLASH_LITE_186_PORT + /* A short file name has to be used in place of the normal + FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef __GNUC__ + #ifdef __AVR32_AVR32A__ + #include "portmacro.h" + #endif +#endif + +#ifdef __ICCAVR32__ + #ifdef __CORE__ + #if __CORE__ == __AVR32A__ + #include "portmacro.h" + #endif + #endif +#endif + +#ifdef __91467D + #include "portmacro.h" +#endif + +#ifdef __96340 + #include "portmacro.h" +#endif + + +#ifdef __IAR_V850ES_Fx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3_L__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Hx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3L__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#endif /* DEPRECATED_DEFINITIONS_H */ + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/event_groups.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/event_groups.h new file mode 100644 index 00000000..69ec2e60 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/event_groups.h @@ -0,0 +1,756 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef EVENT_GROUPS_H +#define EVENT_GROUPS_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include event_groups.h" +#endif + +/* FreeRTOS includes. */ +#include "timers.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * An event group is a collection of bits to which an application can assign a + * meaning. For example, an application may create an event group to convey + * the status of various CAN bus related events in which bit 0 might mean "A CAN + * message has been received and is ready for processing", bit 1 might mean "The + * application has queued a message that is ready for sending onto the CAN + * network", and bit 2 might mean "It is time to send a SYNC message onto the + * CAN network" etc. A task can then test the bit values to see which events + * are active, and optionally enter the Blocked state to wait for a specified + * bit or a group of specified bits to be active. To continue the CAN bus + * example, a CAN controlling task can enter the Blocked state (and therefore + * not consume any processing time) until either bit 0, bit 1 or bit 2 are + * active, at which time the bit that was actually active would inform the task + * which action it had to take (process a received message, send a message, or + * send a SYNC). + * + * The event groups implementation contains intelligence to avoid race + * conditions that would otherwise occur were an application to use a simple + * variable for the same purpose. This is particularly important with respect + * to when a bit within an event group is to be cleared, and when bits have to + * be set and then tested atomically - as is the case where event groups are + * used to create a synchronisation point between multiple tasks (a + * 'rendezvous'). + * + * \defgroup EventGroup + */ + + + +/** + * event_groups.h + * + * Type by which event groups are referenced. For example, a call to + * xEventGroupCreate() returns an EventGroupHandle_t variable that can then + * be used as a parameter to other event group functions. + * + * \defgroup EventGroupHandle_t EventGroupHandle_t + * \ingroup EventGroup + */ +typedef void * EventGroupHandle_t; + +/* + * The type that holds event bits always matches TickType_t - therefore the + * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1, + * 32 bits if set to 0. + * + * \defgroup EventBits_t EventBits_t + * \ingroup EventGroup + */ +typedef TickType_t EventBits_t; + +/** + * event_groups.h + *
+ EventGroupHandle_t xEventGroupCreate( void );
+
+ * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGropuCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see http://www.freertos.org/a00111.html). If an event group is created + * using xEventGropuCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @return If the event group was created then a handle to the event group is + * returned. If there was insufficient FreeRTOS heap available to create the + * event group then NULL is returned. See http://www.freertos.org/a00111.html + * + * Example usage: + 
+	// Declare a variable to hold the created event group.
+	EventGroupHandle_t xCreatedEventGroup;
+
+	// Attempt to create the event group.
+	xCreatedEventGroup = xEventGroupCreate();
+
+	// Was the event group created successfully?
+	if( xCreatedEventGroup == NULL )
+	{
+		// The event group was not created because there was insufficient
+		// FreeRTOS heap available.
+	}
+	else
+	{
+		// The event group was created.
+	}
+
+ * \defgroup xEventGroupCreate xEventGroupCreate + * \ingroup EventGroup + */ +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + *
+ EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
+
+ * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGropuCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see http://www.freertos.org/a00111.html). If an event group is created + * using xEventGropuCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type + * StaticEventGroup_t, which will be then be used to hold the event group's data + * structures, removing the need for the memory to be allocated dynamically. + * + * @return If the event group was created then a handle to the event group is + * returned. If pxEventGroupBuffer was NULL then NULL is returned. + * + * Example usage: + 
+	// StaticEventGroup_t is a publicly accessible structure that has the same
+	// size and alignment requirements as the real event group structure.  It is
+	// provided as a mechanism for applications to know the size of the event
+	// group (which is dependent on the architecture and configuration file
+	// settings) without breaking the strict data hiding policy by exposing the
+	// real event group internals.  This StaticEventGroup_t variable is passed
+	// into the xSemaphoreCreateEventGroupStatic() function and is used to store
+	// the event group's data structures
+	StaticEventGroup_t xEventGroupBuffer;
+
+	// Create the event group without dynamically allocating any memory.
+	xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+
+ */ +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + *
+	EventBits_t xEventGroupWaitBits( 	EventGroupHandle_t xEventGroup,
+										const EventBits_t uxBitsToWaitFor,
+										const BaseType_t xClearOnExit,
+										const BaseType_t xWaitForAllBits,
+										const TickType_t xTicksToWait );
+
+ * + * [Potentially] block to wait for one or more bits to be set within a + * previously created event group. + * + * This function cannot be called from an interrupt. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and/or bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within + * uxBitsToWaitFor that are set within the event group will be cleared before + * xEventGroupWaitBits() returns if the wait condition was met (if the function + * returns for a reason other than a timeout). If xClearOnExit is set to + * pdFALSE then the bits set in the event group are not altered when the call to + * xEventGroupWaitBits() returns. + * + * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then + * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor + * are set or the specified block time expires. If xWaitForAllBits is set to + * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set + * in uxBitsToWaitFor is set or the specified block time expires. The block + * time is specified by the xTicksToWait parameter. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for one/all (depending on the xWaitForAllBits value) of the bits specified by + * uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupWaitBits() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupWaitBits() returned because the bits it was waiting for were set + * then the returned value is the event group value before any bits were + * automatically cleared in the case that xClearOnExit parameter was set to + * pdTRUE. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+   const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+		// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
+		// the event group.  Clear the bits before exiting.
+		uxBits = xEventGroupWaitBits(
+					xEventGroup,	// The event group being tested.
+					BIT_0 | BIT_4,	// The bits within the event group to wait for.
+					pdTRUE,			// BIT_0 and BIT_4 should be cleared before returning.
+					pdFALSE,		// Don't wait for both bits, either bit will do.
+					xTicksToWait );	// Wait a maximum of 100ms for either bit to be set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// xEventGroupWaitBits() returned because both bits were set.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_0 was set.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_4 was set.
+		}
+		else
+		{
+			// xEventGroupWaitBits() returned because xTicksToWait ticks passed
+			// without either BIT_0 or BIT_4 becoming set.
+		}
+   }
+
+ * \defgroup xEventGroupWaitBits xEventGroupWaitBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+
+ * + * Clear bits within an event group. This function cannot be called from an + * interrupt. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear + * in the event group. For example, to clear bit 3 only, set uxBitsToClear to + * 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09. + * + * @return The value of the event group before the specified bits were cleared. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Clear bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupClearBits(
+								xEventGroup,	// The event group being updated.
+								BIT_0 | BIT_4 );// The bits being cleared.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 were set before xEventGroupClearBits() was
+			// called.  Both will now be clear (not set).
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 were set in the first place.
+		}
+   }
+
+ * \defgroup xEventGroupClearBits xEventGroupClearBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+
+ * + * A version of xEventGroupClearBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed + * while interrupts are disabled, so protects event groups that are accessed + * from tasks by suspending the scheduler rather than disabling interrupts. As + * a result event groups cannot be accessed directly from an interrupt service + * routine. Therefore xEventGroupClearBitsFromISR() sends a message to the + * timer task to have the clear operation performed in the context of the timer + * task. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear. + * For example, to clear bit 3 only, set uxBitsToClear to 0x08. To clear bit 3 + * and bit 0 set uxBitsToClear to 0x09. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+		// Clear bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupClearBitsFromISR(
+							xEventGroup,	 // The event group being updated.
+							BIT_0 | BIT_4 ); // The bits being set.
+
+		if( xResult == pdPASS )
+		{
+			// The message was posted successfully.
+		}
+  }
+
+ * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR + * \ingroup EventGroup + */ +#if( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ) +#endif + +/** + * event_groups.h + *
+	EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+
+ * + * Set bits within an event group. + * This function cannot be called from an interrupt. xEventGroupSetBitsFromISR() + * is a version that can be called from an interrupt. + * + * Setting bits in an event group will automatically unblock tasks that are + * blocked waiting for the bits. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @return The value of the event group at the time the call to + * xEventGroupSetBits() returns. There are two reasons why the returned value + * might have the bits specified by the uxBitsToSet parameter cleared. First, + * if setting a bit results in a task that was waiting for the bit leaving the + * blocked state then it is possible the bit will be cleared automatically + * (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any + * unblocked (or otherwise Ready state) task that has a priority above that of + * the task that called xEventGroupSetBits() will execute and may change the + * event group value before the call to xEventGroupSetBits() returns. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupSetBits(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4 );// The bits being set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 remained set when the function returned.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 remained set when the function returned, but bit 4 was
+			// cleared.  It might be that bit 4 was cleared automatically as a
+			// task that was waiting for bit 4 was removed from the Blocked
+			// state.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 remained set when the function returned, but bit 0 was
+			// cleared.  It might be that bit 0 was cleared automatically as a
+			// task that was waiting for bit 0 was removed from the Blocked
+			// state.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 remained set.  It might be that a task
+			// was waiting for both of the bits to be set, and the bits were
+			// cleared as the task left the Blocked state.
+		}
+   }
+
+ * \defgroup xEventGroupSetBits xEventGroupSetBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+
+ * + * A version of xEventGroupSetBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed in + * interrupts or from critical sections. Therefore xEventGroupSetBitsFromISR() + * sends a message to the timer task to have the set operation performed in the + * context of the timer task - where a scheduler lock is used in place of a + * critical section. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @param pxHigherPriorityTaskWoken As mentioned above, calling this function + * will result in a message being sent to the timer daemon task. If the + * priority of the timer daemon task is higher than the priority of the + * currently running task (the task the interrupt interrupted) then + * *pxHigherPriorityTaskWoken will be set to pdTRUE by + * xEventGroupSetBitsFromISR(), indicating that a context switch should be + * requested before the interrupt exits. For that reason + * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the + * example code below. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+   BaseType_t xHigherPriorityTaskWoken, xResult;
+
+		// xHigherPriorityTaskWoken must be initialised to pdFALSE.
+		xHigherPriorityTaskWoken = pdFALSE;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupSetBitsFromISR(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4   // The bits being set.
+							&xHigherPriorityTaskWoken );
+
+		// Was the message posted successfully?
+		if( xResult == pdPASS )
+		{
+			// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+			// switch should be requested.  The macro used is port specific and
+			// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+			// refer to the documentation page for the port being used.
+			portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+		}
+  }
+
+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR + * \ingroup EventGroup + */ +#if( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ) +#endif + +/** + * event_groups.h + *
+	EventBits_t xEventGroupSync(	EventGroupHandle_t xEventGroup,
+									const EventBits_t uxBitsToSet,
+									const EventBits_t uxBitsToWaitFor,
+									TickType_t xTicksToWait );
+
+ * + * Atomically set bits within an event group, then wait for a combination of + * bits to be set within the same event group. This functionality is typically + * used to synchronise multiple tasks, where each task has to wait for the other + * tasks to reach a synchronisation point before proceeding. + * + * This function cannot be used from an interrupt. + * + * The function will return before its block time expires if the bits specified + * by the uxBitsToWait parameter are set, or become set within that time. In + * this case all the bits specified by uxBitsToWait will be automatically + * cleared before the function returns. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToSet The bits to set in the event group before determining + * if, and possibly waiting for, all the bits specified by the uxBitsToWait + * parameter are set. + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for all of the bits specified by uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupSync() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupSync() returned because all the bits it was waiting for were + * set then the returned value is the event group value before any bits were + * automatically cleared. + * + * Example usage: + 
+ // Bits used by the three tasks.
+ #define TASK_0_BIT		( 1 << 0 )
+ #define TASK_1_BIT		( 1 << 1 )
+ #define TASK_2_BIT		( 1 << 2 )
+
+ #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
+
+ // Use an event group to synchronise three tasks.  It is assumed this event
+ // group has already been created elsewhere.
+ EventGroupHandle_t xEventBits;
+
+ void vTask0( void *pvParameters )
+ {
+ EventBits_t uxReturn;
+ TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 0 in the event flag to note this task has reached the
+		// sync point.  The other two tasks will set the other two bits defined
+		// by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
+		// point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
+		// for this to happen.
+		uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
+
+		if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
+		{
+			// All three tasks reached the synchronisation point before the call
+			// to xEventGroupSync() timed out.
+		}
+	}
+ }
+
+ void vTask1( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 1 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	 }
+ }
+
+ void vTask2( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 2 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	}
+ }
+
+
+ * \defgroup xEventGroupSync xEventGroupSync + * \ingroup EventGroup + */ +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + +/** + * event_groups.h + *
+	EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
+
+ * + * Returns the current value of the bits in an event group. This function + * cannot be used from an interrupt. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBits() was called. + * + * \defgroup xEventGroupGetBits xEventGroupGetBits + * \ingroup EventGroup + */ +#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 ) + +/** + * event_groups.h + *
+	EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+
+ * + * A version of xEventGroupGetBits() that can be called from an ISR. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBitsFromISR() was called. + * + * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR + * \ingroup EventGroup + */ +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	void xEventGroupDelete( EventGroupHandle_t xEventGroup );
+
+ * + * Delete an event group that was previously created by a call to + * xEventGroupCreate(). Tasks that are blocked on the event group will be + * unblocked and obtain 0 as the event group's value. + * + * @param xEventGroup The event group being deleted. + */ +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/* For internal use only. */ +void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION; +void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; + + +#if (configUSE_TRACE_FACILITY == 1) + UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION; + void vEventGroupSetNumber( void* xEventGroup, UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION; +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* EVENT_GROUPS_H */ + + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/list.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/list.h new file mode 100644 index 00000000..4a3afa16 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/list.h @@ -0,0 +1,411 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * This is the list implementation used by the scheduler. While it is tailored + * heavily for the schedulers needs, it is also available for use by + * application code. + * + * list_ts can only store pointers to list_item_ts. Each ListItem_t contains a + * numeric value (xItemValue). Most of the time the lists are sorted in + * descending item value order. + * + * Lists are created already containing one list item. The value of this + * item is the maximum possible that can be stored, it is therefore always at + * the end of the list and acts as a marker. The list member pxHead always + * points to this marker - even though it is at the tail of the list. This + * is because the tail contains a wrap back pointer to the true head of + * the list. + * + * In addition to it's value, each list item contains a pointer to the next + * item in the list (pxNext), a pointer to the list it is in (pxContainer) + * and a pointer to back to the object that contains it. These later two + * pointers are included for efficiency of list manipulation. There is + * effectively a two way link between the object containing the list item and + * the list item itself. + * + * + * \page ListIntroduction List Implementation + * \ingroup FreeRTOSIntro + */ + +#ifndef INC_FREERTOS_H + #error FreeRTOS.h must be included before list.h +#endif + +#ifndef LIST_H +#define LIST_H + +/* + * The list structure members are modified from within interrupts, and therefore + * by rights should be declared volatile. However, they are only modified in a + * functionally atomic way (within critical sections of with the scheduler + * suspended) and are either passed by reference into a function or indexed via + * a volatile variable. Therefore, in all use cases tested so far, the volatile + * qualifier can be omitted in order to provide a moderate performance + * improvement without adversely affecting functional behaviour. The assembly + * instructions generated by the IAR, ARM and GCC compilers when the respective + * compiler's options were set for maximum optimisation has been inspected and + * deemed to be as intended. That said, as compiler technology advances, and + * especially if aggressive cross module optimisation is used (a use case that + * has not been exercised to any great extend) then it is feasible that the + * volatile qualifier will be needed for correct optimisation. It is expected + * that a compiler removing essential code because, without the volatile + * qualifier on the list structure members and with aggressive cross module + * optimisation, the compiler deemed the code unnecessary will result in + * complete and obvious failure of the scheduler. If this is ever experienced + * then the volatile qualifier can be inserted in the relevant places within the + * list structures by simply defining configLIST_VOLATILE to volatile in + * FreeRTOSConfig.h (as per the example at the bottom of this comment block). + * If configLIST_VOLATILE is not defined then the preprocessor directives below + * will simply #define configLIST_VOLATILE away completely. + * + * To use volatile list structure members then add the following line to + * FreeRTOSConfig.h (without the quotes): + * "#define configLIST_VOLATILE volatile" + */ +#ifndef configLIST_VOLATILE + #define configLIST_VOLATILE +#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Macros that can be used to place known values within the list structures, +then check that the known values do not get corrupted during the execution of +the application. These may catch the list data structures being overwritten in +memory. They will not catch data errors caused by incorrect configuration or +use of FreeRTOS.*/ +#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) + /* Define the macros to do nothing. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) + #define listTEST_LIST_INTEGRITY( pxList ) +#else + /* Define macros that add new members into the list structures. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue1; + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue2; + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue1; + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue2; + + /* Define macros that set the new structure members to known values. */ + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + + /* Define macros that will assert if one of the structure members does not + contain its expected value. */ + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) + #define listTEST_LIST_INTEGRITY( pxList ) configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) +#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */ + + +/* + * Definition of the only type of object that a list can contain. + */ +struct xLIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ + struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */ + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */ + void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ + void * configLIST_VOLATILE pvContainer; /*< Pointer to the list in which this list item is placed (if any). */ + listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +}; +typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */ + +struct xMINI_LIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; + struct xLIST_ITEM * configLIST_VOLATILE pxNext; + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; +}; +typedef struct xMINI_LIST_ITEM MiniListItem_t; + +/* + * Definition of the type of queue used by the scheduler. + */ +typedef struct xLIST +{ + listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + volatile UBaseType_t uxNumberOfItems; + ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */ + MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ + listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +} List_t; + +/* + * Access macro to set the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) ) + +/* + * Access macro to get the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner ) + +/* + * Access macro to set the value of the list item. In most cases the value is + * used to sort the list in descending order. + * + * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) ) + +/* + * Access macro to retrieve the value of the list item. The value can + * represent anything - for example the priority of a task, or the time at + * which a task should be unblocked. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) + +/* + * Access macro to retrieve the value of the list item at the head of a given + * list. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue ) + +/* + * Return the list item at the head of the list. + * + * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext ) + +/* + * Return the list item at the head of the list. + * + * \page listGET_NEXT listGET_NEXT + * \ingroup LinkedList + */ +#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext ) + +/* + * Return the list item that marks the end of the list + * + * \page listGET_END_MARKER listGET_END_MARKER + * \ingroup LinkedList + */ +#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) ) + +/* + * Access macro to determine if a list contains any items. The macro will + * only have the value true if the list is empty. + * + * \page listLIST_IS_EMPTY listLIST_IS_EMPTY + * \ingroup LinkedList + */ +#define listLIST_IS_EMPTY( pxList ) ( ( BaseType_t ) ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ) + +/* + * Access macro to return the number of items in the list. + */ +#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) + +/* + * Access function to obtain the owner of the next entry in a list. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list + * and returns that entry's pxOwner parameter. Using multiple calls to this + * function it is therefore possible to move through every item contained in + * a list. + * + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxTCB pxTCB is set to the address of the owner of the next list item. + * @param pxList The list from which the next item owner is to be returned. + * + * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ +{ \ +List_t * const pxConstList = ( pxList ); \ + /* Increment the index to the next item and return the item, ensuring */ \ + /* we don't return the marker used at the end of the list. */ \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \ + { \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + } \ + ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \ +} + + +/* + * Access function to obtain the owner of the first entry in a list. Lists + * are normally sorted in ascending item value order. + * + * This function returns the pxOwner member of the first item in the list. + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxList The list from which the owner of the head item is to be + * returned. + * + * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner ) + +/* + * Check to see if a list item is within a list. The list item maintains a + * "container" pointer that points to the list it is in. All this macro does + * is check to see if the container and the list match. + * + * @param pxList The list we want to know if the list item is within. + * @param pxListItem The list item we want to know if is in the list. + * @return pdTRUE if the list item is in the list, otherwise pdFALSE. + */ +#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( BaseType_t ) ( ( pxListItem )->pvContainer == ( void * ) ( pxList ) ) ) + +/* + * Return the list a list item is contained within (referenced from). + * + * @param pxListItem The list item being queried. + * @return A pointer to the List_t object that references the pxListItem + */ +#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pvContainer ) + +/* + * This provides a crude means of knowing if a list has been initialised, as + * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise() + * function. + */ +#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY ) + +/* + * Must be called before a list is used! This initialises all the members + * of the list structure and inserts the xListEnd item into the list as a + * marker to the back of the list. + * + * @param pxList Pointer to the list being initialised. + * + * \page vListInitialise vListInitialise + * \ingroup LinkedList + */ +void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION; + +/* + * Must be called before a list item is used. This sets the list container to + * null so the item does not think that it is already contained in a list. + * + * @param pxItem Pointer to the list item being initialised. + * + * \page vListInitialiseItem vListInitialiseItem + * \ingroup LinkedList + */ +void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted into the list in + * a position determined by its item value (descending item value order). + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The item that is to be placed in the list. + * + * \page vListInsert vListInsert + * \ingroup LinkedList + */ +void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted in a position + * such that it will be the last item within the list returned by multiple + * calls to listGET_OWNER_OF_NEXT_ENTRY. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list. + * Placing an item in a list using vListInsertEnd effectively places the item + * in the list position pointed to by pxIndex. This means that every other + * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before + * the pxIndex parameter again points to the item being inserted. + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The list item to be inserted into the list. + * + * \page vListInsertEnd vListInsertEnd + * \ingroup LinkedList + */ +void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Remove an item from a list. The list item has a pointer to the list that + * it is in, so only the list item need be passed into the function. + * + * @param uxListRemove The item to be removed. The item will remove itself from + * the list pointed to by it's pxContainer parameter. + * + * @return The number of items that remain in the list after the list item has + * been removed. + * + * \page uxListRemove uxListRemove + * \ingroup LinkedList + */ +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/message_buffer.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/message_buffer.h new file mode 100644 index 00000000..91e34fa1 --- /dev/null +++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/message_buffer.h @@ -0,0 +1,779 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +/* + * Message buffers build functionality on top of FreeRTOS stream buffers. + * Whereas stream buffers are used to send a continuous stream of data from one + * task or interrupt to another, message buffers are used to send variable + * length discrete messages from one task or interrupt to another. Their + * implementation is light weight, making them particularly suited for interrupt + * to task and core to core communication scenarios. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * timeout to 0. + * + * Message buffers hold variable length messages. To enable that, when a + * message is written to the message buffer an additional sizeof( size_t ) bytes + * are also written to store the message's length (that happens internally, with + * the API function). sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so writing a 10 byte message to a message buffer on a 32-bit + * architecture will actually reduce the available space in the message buffer + * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length + * of the message). + */ + +#ifndef FREERTOS_MESSAGE_BUFFER_H +#define FREERTOS_MESSAGE_BUFFER_H + +/* Message buffers are built onto of stream buffers. */ +#include "stream_buffer.h" + +#if defined( __cplusplus ) +extern "C" { +#endif + +/** + * Type by which message buffers are referenced. For example, a call to + * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can + * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(), + * etc. + */ +typedef void * MessageBufferHandle_t; + +/*-----------------------------------------------------------*/ + +/** + * message_buffer.h + * +
+MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
+
+ * + * Creates a new message buffer using dynamically allocated memory. See + * xMessageBufferCreateStatic() for a version that uses statically allocated + * memory (memory that is allocated at compile time). + * + * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in + * FreeRTOSConfig.h for xMessageBufferCreate() to be available. + * + * @param xBufferSizeBytes The total number of bytes (not messages) the message + * buffer will be able to hold at any one time. When a message is written to + * the message buffer an additional sizeof( size_t ) bytes are also written to + * store the message's length. sizeof( size_t ) is typically 4 bytes on a + * 32-bit architecture, so on most 32-bit architectures a 10 byte message will + * take up 14 bytes of message buffer space. + * + * @return If NULL is returned, then the message buffer cannot be created + * because there is insufficient heap memory available for FreeRTOS to allocate + * the message buffer data structures and storage area. A non-NULL value being + * returned indicates that the message buffer has been created successfully - + * the returned value should be stored as the handle to the created message + * buffer. + * + * Example use: +
+
+void vAFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+const size_t xMessageBufferSizeBytes = 100;
+
+    // Create a message buffer that can hold 100 bytes.  The memory used to hold
+    // both the message buffer structure and the messages themselves is allocated
+    // dynamically.  Each message added to the buffer consumes an additional 4
+    // bytes which are used to hold the lengh of the message.
+    xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
+
+    if( xMessageBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // message buffer.
+    }
+    else
+    {
+        // The message buffer was created successfully and can now be used.
+    }
+
+
+ * \defgroup xMessageBufferCreate xMessageBufferCreate + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreate( xBufferSizeBytes ) ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE ) + +/** + * message_buffer.h + * +
+MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
+                                                  uint8_t *pucMessageBufferStorageArea,
+                                                  StaticMessageBuffer_t *pxStaticMessageBuffer );
+
+ * Creates a new message buffer using statically allocated memory. See + * xMessageBufferCreate() for a version that uses dynamically allocated memory. + * + * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the + * pucMessageBufferStorageArea parameter. When a message is written to the + * message buffer an additional sizeof( size_t ) bytes are also written to store + * the message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so on most 32-bit architecture a 10 byte message will take up + * 14 bytes of message buffer space. The maximum number of bytes that can be + * stored in the message buffer is actually (xBufferSizeBytes - 1). + * + * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at + * least xBufferSizeBytes + 1 big. This is the array to which messages are + * copied when they are written to the message buffer. + * + * @param pxStaticMessageBuffer Must point to a variable of type + * StaticMessageBuffer_t, which will be used to hold the message buffer's data + * structure. + * + * @return If the message buffer is created successfully then a handle to the + * created message buffer is returned. If either pucMessageBufferStorageArea or + * pxStaticmessageBuffer are NULL then NULL is returned. + * + * Example use: +
+
+// Used to dimension the array used to hold the messages.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the messages within the message
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the message buffer structure.
+StaticMessageBuffer_t xMessageBufferStruct;
+
+void MyFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+
+    xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
+                                                 ucBufferStorage,
+                                                 &xMessageBufferStruct );
+
+    // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
+    // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
+    // reference the created message buffer in other message buffer API calls.
+
+    // Other code that uses the message buffer can go here.
+}
+
+
+ * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer ) + +/** + * message_buffer.h + * +
+size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
+                           const void *pvTxData,
+                           size_t xDataLengthBytes,
+                           TickType_t xTicksToWait );
+
+ *
+ * Sends a discrete message to the message buffer.  The message can be any
+ * length that fits within the buffer's free space, and is copied into the
+ * buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param xTicksToWait The maximum amount of time the calling task should remain
+ * in the Blocked state to wait for enough space to become available in the
+ * message buffer, should the message buffer have insufficient space when
+ * xMessageBufferSend() is called.  The calling task will never block if
+ * xTicksToWait is zero.  The block time is specified in tick periods, so the
+ * absolute time it represents is dependent on the tick frequency.  The macro
+ * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
+ * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause
+ * the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The number of bytes written to the message buffer.  If the call to
+ * xMessageBufferSend() times out before there was enough space to write the
+ * message into the message buffer then zero is returned.  If the call did not
+ * time out then xDataLengthBytes is returned.
+ *
+ * Example use:
+
+void vAFunction( MessageBufferHandle_t xMessageBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the message buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the message buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xMessageBufferSend() times out before there was enough
+        // space in the buffer for the data to be written.
+    }
+
+    // Send the string to the message buffer.  Return immediately if there is
+    // not enough space in the buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+}
+

+ * \defgroup xMessageBufferSend xMessageBufferSend
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
+                                  const void *pvTxData,
+                                  size_t xDataLengthBytes,
+                                  BaseType_t *pxHigherPriorityTaskWoken );
+
+ *
+ * Interrupt safe version of the API function that sends a discrete message to
+ * the message buffer.  The message can be any length that fits within the
+ * buffer's free space, and is copied into the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xMessageBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xMessageBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes actually written to the message buffer.  If the
+ * message buffer didn't have enough free space for the message to be stored
+ * then 0 is returned, otherwise xDataLengthBytes is returned.
+ *
+ * Example use:
+
+// A message buffer that has already been created.
+MessageBufferHandle_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the message buffer.
+    xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
+                                            ( void * ) pcStringToSend,
+                                            strlen( pcStringToSend ),
+                                            &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
+                              void *pvRxData,
+                              size_t xBufferLengthBytes,
+                              TickType_t xTicksToWait );
+

+ *
+ * Receives a discrete message from a message buffer.  Messages can be of
+ * variable length and are copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for a message, should the message buffer be empty.
+ * xMessageBufferReceive() will return immediately if xTicksToWait is zero and
+ * the message buffer is empty.  The block time is specified in tick periods, so
+ * the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.  If xMessageBufferReceive() times out before a message became available
+ * then zero is returned.  If the length of the message is greater than
+ * xBufferLengthBytes then the message will be left in the message buffer and
+ * zero is returned.
+ *
+ * Example use:
+
+void vAFunction( MessageBuffer_t xMessageBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive the next message from the message buffer.  Wait in the Blocked
+    // state (so not using any CPU processing time) for a maximum of 100ms for
+    // a message to become available.
+    xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
+                                            ( void * ) ucRxData,
+                                            sizeof( ucRxData ),
+                                            xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+}
+

+ * \defgroup xMessageBufferReceive xMessageBufferReceive
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
+
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
+                                     void *pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * An interrupt safe version of the API function that receives a discrete
+ * message from a message buffer.  Messages can be of variable length and are
+ * copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xMessageBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.
+ *
+ * Example use:
+
+// A message buffer that has already been created.
+MessageBuffer_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next message from the message buffer.
+    xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
+

+ *
+ * Deletes a message buffer that was previously created using a call to
+ * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message
+ * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A message buffer handle must not be used after the message buffer has been
+ * deleted.
+ *
+ * @param xMessageBuffer The handle of the message buffer to be deleted.
+ *
+ */
+#define vMessageBufferDelete( xMessageBuffer ) vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
+

+ *
+ * Tests to see if a message buffer is full.  A message buffer is full if it
+ * cannot accept any more messages, of any size, until space is made available
+ * by a message being removed from the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is full then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ */
+#define xMessageBufferIsFull( xMessageBuffer ) xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
+

+ *
+ * Tests to see if a message buffer is empty (does not contain any messages).
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is empty then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ *
+ */
+#define xMessageBufferIsEmpty( xMessageBuffer ) xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
+

+ *
+ * Resets a message buffer to its initial empty state, discarding any message it
+ * contained.
+ *
+ * A message buffer can only be reset if there are no tasks blocked on it.
+ *
+ * @param xMessageBuffer The handle of the message buffer being reset.
+ *
+ * @return If the message buffer was reset then pdPASS is returned.  If the
+ * message buffer could not be reset because either there was a task blocked on
+ * the message queue to wait for space to become available, or to wait for a
+ * a message to be available, then pdFAIL is returned.
+ *
+ * \defgroup xMessageBufferReset xMessageBufferReset
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReset( xMessageBuffer ) xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
+
+
+/**
+ * message_buffer.h
+
+size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
+

+ * Returns the number of bytes of free space in the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The number of bytes that can be written to the message buffer before
+ * the message buffer would be full.  When a message is written to the message
+ * buffer an additional sizeof( size_t ) bytes are also written to store the
+ * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
+ * of the largest message that can be written to the message buffer is 6 bytes.
+ *
+ * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+ *
+
+BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferSendCompletedFromISR().  If calling
+ * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferReceiveCompletedFromISR().  If calling
+ * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+#if defined( __cplusplus )
+} /* extern "C" */
+#endif
+
+#endif	/* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/mpu_prototypes.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/mpu_prototypes.h
new file mode 100644
index 00000000..e2c89ab8
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/mpu_prototypes.h
@@ -0,0 +1,155 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * When the MPU is used the standard (non MPU) API functions are mapped to
+ * equivalents that start "MPU_", the prototypes for which are defined in this
+ * header files.  This will cause the application code to call the MPU_ version
+ * which wraps the non-MPU version with privilege promoting then demoting code,
+ * so the kernel code always runs will full privileges.
+ */
+
+
+#ifndef MPU_PROTOTYPES_H
+#define MPU_PROTOTYPES_H
+
+/* MPU versions of tasks.h API functions. */
+BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask );
+TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer );
+BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask );
+BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask );
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );
+void MPU_vTaskDelete( TaskHandle_t xTaskToDelete );
+void MPU_vTaskDelay( const TickType_t xTicksToDelay );
+void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement );
+BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask );
+UBaseType_t MPU_uxTaskPriorityGet( TaskHandle_t xTask );
+eTaskState MPU_eTaskGetState( TaskHandle_t xTask );
+void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );
+void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );
+void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend );
+void MPU_vTaskResume( TaskHandle_t xTaskToResume );
+void MPU_vTaskStartScheduler( void );
+void MPU_vTaskSuspendAll( void );
+BaseType_t MPU_xTaskResumeAll( void );
+TickType_t MPU_xTaskGetTickCount( void );
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void );
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery );
+TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery );
+UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask );
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask );
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue );
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex );
+BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );
+TaskHandle_t MPU_xTaskGetIdleTaskHandle( void );
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime );
+void MPU_vTaskList( char * pcWriteBuffer );
+void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer );
+BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue );
+BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
+uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
+BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask );
+BaseType_t MPU_xTaskIncrementTick( void );
+TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void );
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut );
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );
+void MPU_vTaskMissedYield( void );
+BaseType_t MPU_xTaskGetSchedulerState( void );
+
+/* MPU versions of queue.h API functions. */
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition );
+BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait );
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait );
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait );
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue );
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue );
+void MPU_vQueueDelete( QueueHandle_t xQueue );
+QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType );
+QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue );
+QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount );
+QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue );
+void* MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore );
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait );
+BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex );
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName );
+void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue );
+const char * MPU_pcQueueGetName( QueueHandle_t xQueue );
+QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType );
+QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType );
+QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength );
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );
+BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait );
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue );
+void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber );
+UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue );
+uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue );
+
+/* MPU versions of timers.h API functions. */
+TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction );
+TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer );
+void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer );
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
+BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer );
+TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void );
+BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait );
+const char * MPU_pcTimerGetName( TimerHandle_t xTimer );
+TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer );
+TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer );
+BaseType_t MPU_xTimerCreateTimerTask( void );
+BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait );
+
+/* MPU versions of event_group.h API functions. */
+EventGroupHandle_t MPU_xEventGroupCreate( void );
+EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer );
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait );
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait );
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup );
+UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup );
+
+/* MPU versions of message/stream_buffer.h API functions. */
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait );
+size_t MPU_xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken );
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait );
+size_t MPU_xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken );
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer );
+StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer );
+
+
+
+#endif /* MPU_PROTOTYPES_H */
+
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/mpu_wrappers.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/mpu_wrappers.h
new file mode 100644
index 00000000..eb326e76
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/mpu_wrappers.h
@@ -0,0 +1,181 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef MPU_WRAPPERS_H
+#define MPU_WRAPPERS_H
+
+/* This file redefines API functions to be called through a wrapper macro, but
+only for ports that are using the MPU. */
+#ifdef portUSING_MPU_WRAPPERS
+
+	/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
+	included from queue.c or task.c to prevent it from having an effect within
+	those files. */
+	#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+		/*
+		 * Map standard (non MPU) API functions to equivalents that start
+		 * "MPU_".  This will cause the application code to call the MPU_
+		 * version, which wraps the non-MPU version with privilege promoting
+		 * then demoting code, so the kernel code always runs will full
+		 * privileges.
+		 */
+
+		/* Map standard tasks.h API functions to the MPU equivalents. */
+		#define xTaskCreate								MPU_xTaskCreate
+		#define xTaskCreateStatic						MPU_xTaskCreateStatic
+		#define xTaskCreateRestricted					MPU_xTaskCreateRestricted
+		#define vTaskAllocateMPURegions					MPU_vTaskAllocateMPURegions
+		#define vTaskDelete								MPU_vTaskDelete
+		#define vTaskDelay								MPU_vTaskDelay
+		#define vTaskDelayUntil							MPU_vTaskDelayUntil
+		#define xTaskAbortDelay							MPU_xTaskAbortDelay
+		#define uxTaskPriorityGet						MPU_uxTaskPriorityGet
+		#define eTaskGetState							MPU_eTaskGetState
+		#define vTaskGetInfo							MPU_vTaskGetInfo
+		#define vTaskPrioritySet						MPU_vTaskPrioritySet
+		#define vTaskSuspend							MPU_vTaskSuspend
+		#define vTaskResume								MPU_vTaskResume
+		#define vTaskSuspendAll							MPU_vTaskSuspendAll
+		#define xTaskResumeAll							MPU_xTaskResumeAll
+		#define xTaskGetTickCount						MPU_xTaskGetTickCount
+		#define uxTaskGetNumberOfTasks					MPU_uxTaskGetNumberOfTasks
+		#define pcTaskGetName							MPU_pcTaskGetName
+		#define xTaskGetHandle							MPU_xTaskGetHandle
+		#define uxTaskGetStackHighWaterMark				MPU_uxTaskGetStackHighWaterMark
+		#define vTaskSetApplicationTaskTag				MPU_vTaskSetApplicationTaskTag
+		#define xTaskGetApplicationTaskTag				MPU_xTaskGetApplicationTaskTag
+		#define vTaskSetThreadLocalStoragePointer		MPU_vTaskSetThreadLocalStoragePointer
+		#define pvTaskGetThreadLocalStoragePointer		MPU_pvTaskGetThreadLocalStoragePointer
+		#define xTaskCallApplicationTaskHook			MPU_xTaskCallApplicationTaskHook
+		#define xTaskGetIdleTaskHandle					MPU_xTaskGetIdleTaskHandle
+		#define uxTaskGetSystemState					MPU_uxTaskGetSystemState
+		#define vTaskList								MPU_vTaskList
+		#define vTaskGetRunTimeStats					MPU_vTaskGetRunTimeStats
+		#define xTaskGenericNotify						MPU_xTaskGenericNotify
+		#define xTaskNotifyWait							MPU_xTaskNotifyWait
+		#define ulTaskNotifyTake						MPU_ulTaskNotifyTake
+		#define xTaskNotifyStateClear					MPU_xTaskNotifyStateClear
+
+		#define xTaskGetCurrentTaskHandle				MPU_xTaskGetCurrentTaskHandle
+		#define vTaskSetTimeOutState					MPU_vTaskSetTimeOutState
+		#define xTaskCheckForTimeOut					MPU_xTaskCheckForTimeOut
+		#define xTaskGetSchedulerState					MPU_xTaskGetSchedulerState
+
+		/* Map standard queue.h API functions to the MPU equivalents. */
+		#define xQueueGenericSend						MPU_xQueueGenericSend
+		#define xQueueReceive							MPU_xQueueReceive
+		#define xQueuePeek								MPU_xQueuePeek
+		#define xQueueSemaphoreTake						MPU_xQueueSemaphoreTake
+		#define uxQueueMessagesWaiting					MPU_uxQueueMessagesWaiting
+		#define uxQueueSpacesAvailable					MPU_uxQueueSpacesAvailable
+		#define vQueueDelete							MPU_vQueueDelete
+		#define xQueueCreateMutex						MPU_xQueueCreateMutex
+		#define xQueueCreateMutexStatic					MPU_xQueueCreateMutexStatic
+		#define xQueueCreateCountingSemaphore			MPU_xQueueCreateCountingSemaphore
+		#define xQueueCreateCountingSemaphoreStatic		MPU_xQueueCreateCountingSemaphoreStatic
+		#define xQueueGetMutexHolder					MPU_xQueueGetMutexHolder
+		#define xQueueTakeMutexRecursive				MPU_xQueueTakeMutexRecursive
+		#define xQueueGiveMutexRecursive				MPU_xQueueGiveMutexRecursive
+		#define xQueueGenericCreate						MPU_xQueueGenericCreate
+		#define xQueueGenericCreateStatic				MPU_xQueueGenericCreateStatic
+		#define xQueueCreateSet							MPU_xQueueCreateSet
+		#define xQueueAddToSet							MPU_xQueueAddToSet
+		#define xQueueRemoveFromSet						MPU_xQueueRemoveFromSet
+		#define xQueueSelectFromSet						MPU_xQueueSelectFromSet
+		#define xQueueGenericReset						MPU_xQueueGenericReset
+
+		#if( configQUEUE_REGISTRY_SIZE > 0 )
+			#define vQueueAddToRegistry						MPU_vQueueAddToRegistry
+			#define vQueueUnregisterQueue					MPU_vQueueUnregisterQueue
+			#define pcQueueGetName							MPU_pcQueueGetName
+		#endif
+
+		/* Map standard timer.h API functions to the MPU equivalents. */
+		#define xTimerCreate							MPU_xTimerCreate
+		#define xTimerCreateStatic						MPU_xTimerCreateStatic
+		#define pvTimerGetTimerID						MPU_pvTimerGetTimerID
+		#define vTimerSetTimerID						MPU_vTimerSetTimerID
+		#define xTimerIsTimerActive						MPU_xTimerIsTimerActive
+		#define xTimerGetTimerDaemonTaskHandle			MPU_xTimerGetTimerDaemonTaskHandle
+		#define xTimerPendFunctionCall					MPU_xTimerPendFunctionCall
+		#define pcTimerGetName							MPU_pcTimerGetName
+		#define xTimerGetPeriod							MPU_xTimerGetPeriod
+		#define xTimerGetExpiryTime						MPU_xTimerGetExpiryTime
+		#define xTimerGenericCommand					MPU_xTimerGenericCommand
+
+		/* Map standard event_group.h API functions to the MPU equivalents. */
+		#define xEventGroupCreate						MPU_xEventGroupCreate
+		#define xEventGroupCreateStatic					MPU_xEventGroupCreateStatic
+		#define xEventGroupWaitBits						MPU_xEventGroupWaitBits
+		#define xEventGroupClearBits					MPU_xEventGroupClearBits
+		#define xEventGroupSetBits						MPU_xEventGroupSetBits
+		#define xEventGroupSync							MPU_xEventGroupSync
+		#define vEventGroupDelete						MPU_vEventGroupDelete
+
+		/* Map standard message/stream_buffer.h API functions to the MPU
+		equivalents. */
+		#define xStreamBufferSend						MPU_xStreamBufferSend
+		#define xStreamBufferSendFromISR				MPU_xStreamBufferSendFromISR
+		#define xStreamBufferReceive					MPU_xStreamBufferReceive
+		#define xStreamBufferReceiveFromISR				MPU_xStreamBufferReceiveFromISR
+		#define vStreamBufferDelete						MPU_vStreamBufferDelete
+		#define xStreamBufferIsFull						MPU_xStreamBufferIsFull
+		#define xStreamBufferIsEmpty					MPU_xStreamBufferIsEmpty
+		#define xStreamBufferReset						MPU_xStreamBufferReset
+		#define xStreamBufferSpacesAvailable			MPU_xStreamBufferSpacesAvailable
+		#define xStreamBufferBytesAvailable				MPU_xStreamBufferBytesAvailable
+		#define xStreamBufferSetTriggerLevel			MPU_xStreamBufferSetTriggerLevel
+		#define xStreamBufferGenericCreate				MPU_xStreamBufferGenericCreate
+		#define xStreamBufferGenericCreateStatic		MPU_xStreamBufferGenericCreateStatic
+
+
+		/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
+		macro so applications can place data in privileged access sections
+		(useful when using statically allocated objects). */
+		#define PRIVILEGED_FUNCTION
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+
+	#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+		/* Ensure API functions go in the privileged execution section. */
+		#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+
+	#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+#else /* portUSING_MPU_WRAPPERS */
+
+	#define PRIVILEGED_FUNCTION
+	#define PRIVILEGED_DATA
+	#define portUSING_MPU_WRAPPERS 0
+
+#endif /* portUSING_MPU_WRAPPERS */
+
+
+#endif /* MPU_WRAPPERS_H */
+
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/portable.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/portable.h
new file mode 100644
index 00000000..3d0ef0a6
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/portable.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Portable layer API.  Each function must be defined for each port.
+ *----------------------------------------------------------*/
+
+#ifndef PORTABLE_H
+#define PORTABLE_H
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+pre-processor definition was used to ensure the pre-processor found the correct
+portmacro.h file for the port being used.  That scheme was deprecated in favour
+of setting the compiler's include path such that it found the correct
+portmacro.h file - removing the need for the constant and allowing the
+portmacro.h file to be located anywhere in relation to the port being used.
+Purely for reasons of backward compatibility the old method is still valid, but
+to make it clear that new projects should not use it, support for the port
+specific constants has been moved into the deprecated_definitions.h header
+file. */
+#include "deprecated_definitions.h"
+
+/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
+did not result in a portmacro.h header file being included - and it should be
+included here.  In this case the path to the correct portmacro.h header file
+must be set in the compiler's include path. */
+#ifndef portENTER_CRITICAL
+	#include "portmacro.h"
+#endif
+
+#if portBYTE_ALIGNMENT == 32
+	#define portBYTE_ALIGNMENT_MASK ( 0x001f )
+#endif
+
+#if portBYTE_ALIGNMENT == 16
+	#define portBYTE_ALIGNMENT_MASK ( 0x000f )
+#endif
+
+#if portBYTE_ALIGNMENT == 8
+	#define portBYTE_ALIGNMENT_MASK ( 0x0007 )
+#endif
+
+#if portBYTE_ALIGNMENT == 4
+	#define portBYTE_ALIGNMENT_MASK	( 0x0003 )
+#endif
+
+#if portBYTE_ALIGNMENT == 2
+	#define portBYTE_ALIGNMENT_MASK	( 0x0001 )
+#endif
+
+#if portBYTE_ALIGNMENT == 1
+	#define portBYTE_ALIGNMENT_MASK	( 0x0000 )
+#endif
+
+#ifndef portBYTE_ALIGNMENT_MASK
+	#error "Invalid portBYTE_ALIGNMENT definition"
+#endif
+
+#ifndef portNUM_CONFIGURABLE_REGIONS
+	#define portNUM_CONFIGURABLE_REGIONS 1
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mpu_wrappers.h"
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control.  The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+#endif
+
+/* Used by heap_5.c. */
+typedef struct HeapRegion
+{
+	uint8_t *pucStartAddress;
+	size_t xSizeInBytes;
+} HeapRegion_t;
+
+/*
+ * Used to define multiple heap regions for use by heap_5.c.  This function
+ * must be called before any calls to pvPortMalloc() - not creating a task,
+ * queue, semaphore, mutex, software timer, event group, etc. will result in
+ * pvPortMalloc being called.
+ *
+ * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
+ * defines a region of memory that can be used as the heap.  The array is
+ * terminated by a HeapRegions_t structure that has a size of 0.  The region
+ * with the lowest start address must appear first in the array.
+ */
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
+
+
+/*
+ * Map to the memory management routines required for the port.
+ */
+void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void vPortFree( void *pv ) PRIVILEGED_FUNCTION;
+void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the hardware ready for the scheduler to take control.  This generally
+ * sets up a tick interrupt and sets timers for the correct tick frequency.
+ */
+BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
+ * the hardware is left in its original condition after the scheduler stops
+ * executing.
+ */
+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The structures and methods of manipulating the MPU are contained within the
+ * port layer.
+ *
+ * Fills the xMPUSettings structure with the memory region information
+ * contained in xRegions.
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	struct xMEMORY_REGION;
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTABLE_H */
+
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/projdefs.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/projdefs.h
new file mode 100644
index 00000000..27337a89
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/projdefs.h
@@ -0,0 +1,124 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PROJDEFS_H
+#define PROJDEFS_H
+
+/*
+ * Defines the prototype to which task functions must conform.  Defined in this
+ * file to ensure the type is known before portable.h is included.
+ */
+typedef void (*TaskFunction_t)( void * );
+
+/* Converts a time in milliseconds to a time in ticks.  This macro can be
+overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+definition here is not suitable for your application. */
+#ifndef pdMS_TO_TICKS
+	#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )
+#endif
+
+#define pdFALSE			( ( BaseType_t ) 0 )
+#define pdTRUE			( ( BaseType_t ) 1 )
+
+#define pdPASS			( pdTRUE )
+#define pdFAIL			( pdFALSE )
+#define errQUEUE_EMPTY	( ( BaseType_t ) 0 )
+#define errQUEUE_FULL	( ( BaseType_t ) 0 )
+
+/* FreeRTOS error definitions. */
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY	( -1 )
+#define errQUEUE_BLOCKED						( -4 )
+#define errQUEUE_YIELD							( -5 )
+
+/* Macros used for basic data corruption checks. */
+#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
+	#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
+#endif
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a
+#else
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
+#endif
+
+/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_ERRNO_NONE			0	/* No errors */
+#define	pdFREERTOS_ERRNO_ENOENT			2	/* No such file or directory */
+#define	pdFREERTOS_ERRNO_EINTR			4	/* Interrupted system call */
+#define	pdFREERTOS_ERRNO_EIO			5	/* I/O error */
+#define	pdFREERTOS_ERRNO_ENXIO			6	/* No such device or address */
+#define	pdFREERTOS_ERRNO_EBADF			9	/* Bad file number */
+#define	pdFREERTOS_ERRNO_EAGAIN			11	/* No more processes */
+#define	pdFREERTOS_ERRNO_EWOULDBLOCK	11	/* Operation would block */
+#define	pdFREERTOS_ERRNO_ENOMEM			12	/* Not enough memory */
+#define	pdFREERTOS_ERRNO_EACCES			13	/* Permission denied */
+#define	pdFREERTOS_ERRNO_EFAULT			14	/* Bad address */
+#define	pdFREERTOS_ERRNO_EBUSY			16	/* Mount device busy */
+#define	pdFREERTOS_ERRNO_EEXIST			17	/* File exists */
+#define	pdFREERTOS_ERRNO_EXDEV			18	/* Cross-device link */
+#define	pdFREERTOS_ERRNO_ENODEV			19	/* No such device */
+#define	pdFREERTOS_ERRNO_ENOTDIR		20	/* Not a directory */
+#define	pdFREERTOS_ERRNO_EISDIR			21	/* Is a directory */
+#define	pdFREERTOS_ERRNO_EINVAL			22	/* Invalid argument */
+#define	pdFREERTOS_ERRNO_ENOSPC			28	/* No space left on device */
+#define	pdFREERTOS_ERRNO_ESPIPE			29	/* Illegal seek */
+#define	pdFREERTOS_ERRNO_EROFS			30	/* Read only file system */
+#define	pdFREERTOS_ERRNO_EUNATCH		42	/* Protocol driver not attached */
+#define	pdFREERTOS_ERRNO_EBADE			50	/* Invalid exchange */
+#define	pdFREERTOS_ERRNO_EFTYPE			79	/* Inappropriate file type or format */
+#define	pdFREERTOS_ERRNO_ENMFILE		89	/* No more files */
+#define	pdFREERTOS_ERRNO_ENOTEMPTY		90	/* Directory not empty */
+#define	pdFREERTOS_ERRNO_ENAMETOOLONG 	91	/* File or path name too long */
+#define	pdFREERTOS_ERRNO_EOPNOTSUPP		95	/* Operation not supported on transport endpoint */
+#define	pdFREERTOS_ERRNO_ENOBUFS		105	/* No buffer space available */
+#define	pdFREERTOS_ERRNO_ENOPROTOOPT	109	/* Protocol not available */
+#define	pdFREERTOS_ERRNO_EADDRINUSE		112	/* Address already in use */
+#define	pdFREERTOS_ERRNO_ETIMEDOUT		116	/* Connection timed out */
+#define	pdFREERTOS_ERRNO_EINPROGRESS	119	/* Connection already in progress */
+#define	pdFREERTOS_ERRNO_EALREADY		120	/* Socket already connected */
+#define	pdFREERTOS_ERRNO_EADDRNOTAVAIL 	125	/* Address not available */
+#define	pdFREERTOS_ERRNO_EISCONN		127	/* Socket is already connected */
+#define	pdFREERTOS_ERRNO_ENOTCONN		128	/* Socket is not connected */
+#define	pdFREERTOS_ERRNO_ENOMEDIUM		135	/* No medium inserted */
+#define	pdFREERTOS_ERRNO_EILSEQ			138	/* An invalid UTF-16 sequence was encountered. */
+#define	pdFREERTOS_ERRNO_ECANCELED		140	/* Operation canceled. */
+
+/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_LITTLE_ENDIAN		0
+#define pdFREERTOS_BIG_ENDIAN			1
+
+/* Re-defining endian values for generic naming. */
+#define pdLITTLE_ENDIAN					pdFREERTOS_LITTLE_ENDIAN
+#define pdBIG_ENDIAN					pdFREERTOS_BIG_ENDIAN
+
+
+#endif /* PROJDEFS_H */
+
+
+
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/queue.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/queue.h
new file mode 100644
index 00000000..a23fa1e6
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/queue.h
@@ -0,0 +1,1653 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include queue.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * Type by which queues are referenced.  For example, a call to xQueueCreate()
+ * returns an QueueHandle_t variable that can then be used as a parameter to
+ * xQueueSend(), xQueueReceive(), etc.
+ */
+typedef void * QueueHandle_t;
+
+/**
+ * Type by which queue sets are referenced.  For example, a call to
+ * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
+ * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
+ */
+typedef void * QueueSetHandle_t;
+
+/**
+ * Queue sets can contain both queues and semaphores, so the
+ * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
+ * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
+ */
+typedef void * QueueSetMemberHandle_t;
+
+/* For internal use only. */
+#define	queueSEND_TO_BACK		( ( BaseType_t ) 0 )
+#define	queueSEND_TO_FRONT		( ( BaseType_t ) 1 )
+#define queueOVERWRITE			( ( BaseType_t ) 2 )
+
+/* For internal use only.  These definitions *must* match those in queue.c. */
+#define queueQUEUE_TYPE_BASE				( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_SET					( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_MUTEX 				( ( uint8_t ) 1U )
+#define queueQUEUE_TYPE_COUNTING_SEMAPHORE	( ( uint8_t ) 2U )
+#define queueQUEUE_TYPE_BINARY_SEMAPHORE	( ( uint8_t ) 3U )
+#define queueQUEUE_TYPE_RECURSIVE_MUTEX		( ( uint8_t ) 4U )
+
+/**
+ * queue. h
+ * 
+ QueueHandle_t xQueueCreate(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize
+						  );
+ * 

+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @return If the queue is successfully create then a handle to the newly
+ * created queue is returned.  If the queue cannot be created then 0 is
+ * returned.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+	if( xQueue1 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue2 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueCreate xQueueCreate
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
+#endif
+
+/**
+ * queue. h
+ * 
+ QueueHandle_t xQueueCreateStatic(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize,
+							  uint8_t *pucQueueStorageBuffer,
+							  StaticQueue_t *pxQueueBuffer
+						  );
+ * 

+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @param pucQueueStorageBuffer If uxItemSize is not zero then
+ * pucQueueStorageBuffer must point to a uint8_t array that is at least large
+ * enough to hold the maximum number of items that can be in the queue at any
+ * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is
+ * zero then pucQueueStorageBuffer can be NULL.
+ *
+ * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
+ * will be used to hold the queue's data structure.
+ *
+ * @return If the queue is created then a handle to the created queue is
+ * returned.  If pxQueueBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ #define QUEUE_LENGTH 10
+ #define ITEM_SIZE sizeof( uint32_t )
+
+ // xQueueBuffer will hold the queue structure.
+ StaticQueue_t xQueueBuffer;
+
+ // ucQueueStorage will hold the items posted to the queue.  Must be at least
+ // [(queue length) * ( queue item size)] bytes long.
+ uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
+							ITEM_SIZE	  // The size of each item in the queue
+							&( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
+							&xQueueBuffer ); // The buffer that will hold the queue structure.
+
+	// The queue is guaranteed to be created successfully as no dynamic memory
+	// allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueCreateStatic xQueueCreateStatic
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToToFront(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * 

+ *
+ * Post an item to the front of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToBack(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * 

+ *
+ * This is a macro that calls xQueueGenericSend().
+ *
+ * Post an item to the back of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the queue
+ * is full.  The  time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSend(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  TickType_t xTicksToWait
+						 );
+ * 

+ *
+ * This is a macro that calls xQueueGenericSend().  It is included for
+ * backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is
+ * equivalent to xQueueSendToBack().
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueOverwrite(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue
+						 );
+ * 

+ *
+ * Only for use with queues that have a length of one - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * This function must not be called from an interrupt service routine.
+ * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle of the queue to which the data is being sent.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
+ * therefore has the same return values as xQueueSendToFront().  However, pdPASS
+ * is the only value that can be returned because xQueueOverwrite() will write
+ * to the queue even when the queue is already full.
+ *
+ * Example usage:
+   
+
+ void vFunction( void *pvParameters )
+ {
+ QueueHandle_t xQueue;
+ uint32_t ulVarToSend, ulValReceived;
+
+	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwrite() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+
+	// Write the value 10 to the queue using xQueueOverwrite().
+	ulVarToSend = 10;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// Peeking the queue should now return 10, but leave the value 10 in
+	// the queue.  A block time of zero is used as it is known that the
+	// queue holds a value.
+	ulValReceived = 0;
+	xQueuePeek( xQueue, &ulValReceived, 0 );
+
+	if( ulValReceived != 10 )
+	{
+		// Error unless the item was removed by a different task.
+	}
+
+	// The queue is still full.  Use xQueueOverwrite() to overwrite the
+	// value held in the queue with 100.
+	ulVarToSend = 100;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// This time read from the queue, leaving the queue empty once more.
+	// A block time of 0 is used again.
+	xQueueReceive( xQueue, &ulValReceived, 0 );
+
+	// The value read should be the last value written, even though the
+	// queue was already full when the value was written.
+	if( ulValReceived != 100 )
+	{
+		// Error!
+	}
+
+	// ...
+}
+ 

+ * \defgroup xQueueOverwrite xQueueOverwrite
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
+
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueGenericSend(
+									QueueHandle_t xQueue,
+									const void * pvItemToQueue,
+									TickType_t xTicksToWait
+									BaseType_t xCopyPosition
+								);
+ * 

+ *
+ * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
+ * xQueueSendToBack() are used in place of calling this function directly.
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueuePeek(
+							 QueueHandle_t xQueue,
+							 void * const pvBuffer,
+							 TickType_t xTicksToWait
+						 );

+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * This macro must not be used in an interrupt service routine.  See
+ * xQueuePeekFromISR() for an alternative that can be called from an interrupt
+ * service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
+ * is empty.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to peek the data from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Peek a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask, but the item still remains on the queue.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueuePeek xQueuePeek
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueuePeekFromISR(
+									QueueHandle_t xQueue,
+									void *pvBuffer,
+								);

+ *
+ * A version of xQueuePeek() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * \defgroup xQueuePeekFromISR xQueuePeekFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueReceive(
+								 QueueHandle_t xQueue,
+								 void *pvBuffer,
+								 TickType_t xTicksToWait
+							);

+ *
+ * Receive an item from a queue.  The item is received by copy so a buffer of
+ * adequate size must be provided.  The number of bytes copied into the buffer
+ * was defined when the queue was created.
+ *
+ * Successfully received items are removed from the queue.
+ *
+ * This function must not be used in an interrupt service routine.  See
+ * xQueueReceiveFromISR for an alternative that can.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 xQueueReceive() will return immediately if xTicksToWait
+ * is zero and the queue is empty.  The time is defined in tick periods so the
+ * constant portTICK_PERIOD_MS should be used to convert to real time if this is
+ * required.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Receive a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );

+ *
+ * Return the number of messages stored in a queue.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of messages available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );

+ *
+ * Return the number of free spaces available in a queue.  This is equal to the
+ * number of items that can be sent to the queue before the queue becomes full
+ * if no items are removed.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of spaces available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
void vQueueDelete( QueueHandle_t xQueue );

+ *
+ * Delete a queue - freeing all the memory allocated for storing of items
+ * placed on the queue.
+ *
+ * @param xQueue A handle to the queue to be deleted.
+ *
+ * \defgroup vQueueDelete vQueueDelete
+ * \ingroup QueueManagement
+ */
+void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToFrontFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ 

+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the front of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPrioritTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
+
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToBackFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ 

+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the back of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueOverwriteFromISR(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  BaseType_t *pxHigherPriorityTaskWoken
+						 );
+ * 

+ *
+ * A version of xQueueOverwrite() that can be used in an interrupt service
+ * routine (ISR).
+ *
+ * Only for use with queues that can hold a single item - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return xQueueOverwriteFromISR() is a macro that calls
+ * xQueueGenericSendFromISR(), and therefore has the same return values as
+ * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be
+ * returned because xQueueOverwriteFromISR() will write to the queue even when
+ * the queue is already full.
+ *
+ * Example usage:
+   
+
+ QueueHandle_t xQueue;
+
+ void vFunction( void *pvParameters )
+ {
+ 	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwriteFromISR() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+}
+
+void vAnInterruptHandler( void )
+{
+// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+uint32_t ulVarToSend, ulValReceived;
+
+	// Write the value 10 to the queue using xQueueOverwriteFromISR().
+	ulVarToSend = 10;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// The queue is full, but calling xQueueOverwriteFromISR() again will still
+	// pass because the value held in the queue will be overwritten with the
+	// new value.
+	ulVarToSend = 100;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// Reading from the queue will now return 100.
+
+	// ...
+
+	if( xHigherPrioritytaskWoken == pdTRUE )
+	{
+		// Writing to the queue caused a task to unblock and the unblocked task
+		// has a priority higher than or equal to the priority of the currently
+		// executing task (the task this interrupt interrupted).  Perform a context
+		// switch so this interrupt returns directly to the unblocked task.
+		portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+	}
+}
+ 

+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendFromISR(
+									 QueueHandle_t xQueue,
+									 const void *pvItemToQueue,
+									 BaseType_t *pxHigherPriorityTaskWoken
+								);
+ 

+ *
+ * This is a macro that calls xQueueGenericSendFromISR().  It is included
+ * for backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
+ * macros.
+ *
+ * Post an item to the back of a queue.  It is safe to use this function from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		// Actual macro used here is port specific.
+		portYIELD_FROM_ISR ();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueGenericSendFromISR(
+										   QueueHandle_t		xQueue,
+										   const	void	*pvItemToQueue,
+										   BaseType_t	*pxHigherPriorityTaskWoken,
+										   BaseType_t	xCopyPosition
+									   );
+ 

+ *
+ * It is preferred that the macros xQueueSendFromISR(),
+ * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
+ * of calling this function directly.  xQueueGiveFromISR() is an
+ * equivalent for use by semaphores that don't actually copy any data.
+ *
+ * Post an item on a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWokenByPost;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWokenByPost = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post each byte.
+		xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.  Note that the
+	// name of the yield function required is port specific.
+	if( xHigherPriorityTaskWokenByPost )
+	{
+		taskYIELD_YIELD_FROM_ISR();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueReceiveFromISR(
+									   QueueHandle_t	xQueue,
+									   void	*pvBuffer,
+									   BaseType_t *pxTaskWoken
+								   );
+ * 

+ *
+ * Receive an item from a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param pxTaskWoken A task may be blocked waiting for space to become
+ * available on the queue.  If xQueueReceiveFromISR causes such a task to
+ * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
+ * remain unchanged.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+
+ QueueHandle_t xQueue;
+
+ // Function to create a queue and post some values.
+ void vAFunction( void *pvParameters )
+ {
+ char cValueToPost;
+ const TickType_t xTicksToWait = ( TickType_t )0xff;
+
+	// Create a queue capable of containing 10 characters.
+	xQueue = xQueueCreate( 10, sizeof( char ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Post some characters that will be used within an ISR.  If the queue
+	// is full then this task will block for xTicksToWait ticks.
+	cValueToPost = 'a';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+	cValueToPost = 'b';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+
+	// ... keep posting characters ... this task may block when the queue
+	// becomes full.
+
+	cValueToPost = 'c';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ }
+
+ // ISR that outputs all the characters received on the queue.
+ void vISR_Routine( void )
+ {
+ BaseType_t xTaskWokenByReceive = pdFALSE;
+ char cRxedChar;
+
+	while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+	{
+		// A character was received.  Output the character now.
+		vOutputCharacter( cRxedChar );
+
+		// If removing the character from the queue woke the task that was
+		// posting onto the queue cTaskWokenByReceive will have been set to
+		// pdTRUE.  No matter how many times this loop iterates only one
+		// task will be woken.
+	}
+
+	if( cTaskWokenByPost != ( char ) pdFALSE;
+	{
+		taskYIELD ();
+	}
+ }
+ 

+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/*
+ * Utilities to query queues that are safe to use from an ISR.  These utilities
+ * should be used only from witin an ISR, or within a critical section.
+ */
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * The functions defined above are for passing data to and from tasks.  The
+ * functions below are the equivalents for passing data to and from
+ * co-routines.
+ *
+ * These functions are called from the co-routine macro implementation and
+ * should not be called directly from application code.  Instead use the macro
+ * wrappers defined within croutine.h.
+ */
+BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );
+BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );
+BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );
+BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );
+
+/*
+ * For internal use only.  Use xSemaphoreCreateMutex(),
+ * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
+ * these functions directly.
+ */
+QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+void* xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+void* xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
+ * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
+ */
+BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION;
+
+/*
+ * Reset a queue back to its original empty state.  The return value is now
+ * obsolete and is always set to pdPASS.
+ */
+#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger.  If you are not using a kernel
+ * aware debugger then this function can be ignored.
+ *
+ * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
+ * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0
+ * within FreeRTOSConfig.h for the registry to be available.  Its value
+ * does not effect the number of queues, semaphores and mutexes that can be
+ * created - just the number that the registry can hold.
+ *
+ * @param xQueue The handle of the queue being added to the registry.  This
+ * is the handle returned by a call to xQueueCreate().  Semaphore and mutex
+ * handles can also be passed in here.
+ *
+ * @param pcName The name to be associated with the handle.  This is the
+ * name that the kernel aware debugger will display.  The queue registry only
+ * stores a pointer to the string - so the string must be persistent (global or
+ * preferably in ROM/Flash), not on the stack.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
+ * remove the queue, semaphore or mutex from the register.  If you are not using
+ * a kernel aware debugger then this function can be ignored.
+ *
+ * @param xQueue The handle of the queue being removed from the registry.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * The queue registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look
+ * up and return the name of a queue in the queue registry from the queue's
+ * handle.
+ *
+ * @param xQueue The handle of the queue the name of which will be returned.
+ * @return If the queue is in the registry then a pointer to the name of the
+ * queue is returned.  If the queue is not in the registry then NULL is
+ * returned.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	const char *pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Queue sets provide a mechanism to allow a task to block (pend) on a read
+ * operation from multiple queues or semaphores simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * A queue set must be explicitly created using a call to xQueueCreateSet()
+ * before it can be used.  Once created, standard FreeRTOS queues and semaphores
+ * can be added to the set using calls to xQueueAddToSet().
+ * xQueueSelectFromSet() is then used to determine which, if any, of the queues
+ * or semaphores contained in the set is in a state where a queue read or
+ * semaphore take operation would be successful.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  An additional 4 bytes of RAM is required for each space in a every
+ * queue added to a queue set.  Therefore counting semaphores that have a high
+ * maximum count value should not be added to a queue set.
+ *
+ * Note 4:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param uxEventQueueLength Queue sets store events that occur on
+ * the queues and semaphores contained in the set.  uxEventQueueLength specifies
+ * the maximum number of events that can be queued at once.  To be absolutely
+ * certain that events are not lost uxEventQueueLength should be set to the
+ * total sum of the length of the queues added to the set, where binary
+ * semaphores and mutexes have a length of 1, and counting semaphores have a
+ * length set by their maximum count value.  Examples:
+ *  + If a queue set is to hold a queue of length 5, another queue of length 12,
+ *    and a binary semaphore, then uxEventQueueLength should be set to
+ *    (5 + 12 + 1), or 18.
+ *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
+ *    should be set to (1 + 1 + 1 ), or 3.
+ *  + If a queue set is to hold a counting semaphore that has a maximum count of
+ *    5, and a counting semaphore that has a maximum count of 3, then
+ *    uxEventQueueLength should be set to (5 + 3), or 8.
+ *
+ * @return If the queue set is created successfully then a handle to the created
+ * queue set is returned.  Otherwise NULL is returned.
+ */
+QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * Adds a queue or semaphore to a queue set that was previously created by a
+ * call to xQueueCreateSet().
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
+ * the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set to which the queue or semaphore
+ * is being added.
+ *
+ * @return If the queue or semaphore was successfully added to the queue set
+ * then pdPASS is returned.  If the queue could not be successfully added to the
+ * queue set because it is already a member of a different queue set then pdFAIL
+ * is returned.
+ */
+BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
+ * be removed from a set if the queue or semaphore is empty.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
+ * from the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set in which the queue or semaphore
+ * is included.
+ *
+ * @return If the queue or semaphore was successfully removed from the queue set
+ * then pdPASS is returned.  If the queue was not in the queue set, or the
+ * queue (or semaphore) was not empty, then pdFAIL is returned.
+ */
+BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * xQueueSelectFromSet() selects from the members of a queue set a queue or
+ * semaphore that either contains data (in the case of a queue) or is available
+ * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively
+ * allows a task to block (pend) on a read operation on all the queues and
+ * semaphores in a queue set simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueSet The queue set on which the task will (potentially) block.
+ *
+ * @param xTicksToWait The maximum time, in ticks, that the calling task will
+ * remain in the Blocked state (with other tasks executing) to wait for a member
+ * of the queue set to be ready for a successful queue read or semaphore take
+ * operation.
+ *
+ * @return xQueueSelectFromSet() will return the handle of a queue (cast to
+ * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
+ * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
+ * in the queue set that is available, or NULL if no such queue or semaphore
+ * exists before before the specified block time expires.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * A version of xQueueSelectFromSet() that can be used from an ISR.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/* Not public API functions. */
+void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* QUEUE_H */
+
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/semphr.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/semphr.h
new file mode 100644
index 00000000..e603b4af
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/semphr.h
@@ -0,0 +1,1140 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include semphr.h"
+#endif
+
+#include "queue.h"
+
+typedef QueueHandle_t SemaphoreHandle_t;
+
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH	( ( uint8_t ) 1U )
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH		( ( uint8_t ) 0U )
+#define semGIVE_BLOCK_TIME					( ( TickType_t ) 0U )
+
+
+/**
+ * semphr. h
+ * 
vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )

+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * Macro that implements a semaphore by using the existing queue mechanism.
+ * The queue length is 1 as this is a binary semaphore.  The data size is 0
+ * as we don't want to actually store any data - we just want to know if the
+ * queue is empty or full.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+    // This is a macro so pass the variable in directly.
+    vSemaphoreCreateBinary( xSemaphore );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define vSemaphoreCreateBinary( xSemaphore )																							\
+		{																																	\
+			( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE );	\
+			if( ( xSemaphore ) != NULL )																									\
+			{																																\
+				( void ) xSemaphoreGive( ( xSemaphore ) );																					\
+			}																																\
+		}
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateBinary( void )

+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @return Handle to the created semaphore, or NULL if the memory required to
+ * hold the semaphore's data structures could not be allocated.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer )

+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * NOTE: In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the semaphore is created then a handle to the created semaphore is
+ * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // The semaphore's data structures will be placed in the xSemaphoreBuffer
+    // variable, the address of which is passed into the function.  The
+    // function's parameter is not NULL, so the function will not attempt any
+    // dynamic memory allocation, and therefore the function will not return
+    // return NULL.
+    xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
+
+    // Rest of task code goes here.
+ }
+ 

+ * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
xSemaphoreTake(
+ *                   SemaphoreHandle_t xSemaphore,
+ *                   TickType_t xBlockTime
+ *               )

+ *
+ * Macro to obtain a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting().
+ *
+ * @param xSemaphore A handle to the semaphore being taken - obtained when
+ * the semaphore was created.
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  A block
+ * time of portMAX_DELAY can be used to block indefinitely (provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE
+ * if xBlockTime expired without the semaphore becoming available.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // A task that creates a semaphore.
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = xSemaphoreCreateBinary();
+ }
+
+ // A task that uses the semaphore.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xSemaphore != NULL )
+    {
+        // See if we can obtain the semaphore.  If the semaphore is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the semaphore and can now access the
+            // shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource.  Release the
+            // semaphore.
+            xSemaphoreGive( xSemaphore );
+        }
+        else
+        {
+            // We could not obtain the semaphore and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreTake xSemaphoreTake
+ * \ingroup Semaphores
+ */
+#define xSemaphoreTake( xSemaphore, xBlockTime )		xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )
+
+/**
+ * semphr. h
+ * xSemaphoreTakeRecursive(
+ *                          SemaphoreHandle_t xMutex,
+ *                          TickType_t xBlockTime
+ *                        )
+ *
+ * Macro to recursively obtain, or 'take', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being obtained.  This is the
+ * handle returned by xSemaphoreCreateRecursiveMutex();
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  If
+ * the task already owns the semaphore then xSemaphoreTakeRecursive() will
+ * return immediately no matter what the value of xBlockTime.
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime
+ * expired without the semaphore becoming available.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+            // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+            // code these would not be just sequential calls as this would make
+            // no sense.  Instead the calls are likely to be buried inside
+            // a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+            // available to another task until it has also been given back
+            // three times.  Again it is unlikely that real code would have
+            // these calls sequentially, but instead buried in a more complex
+            // call structure.  This is just for illustrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+
+            // Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreTakeRecursive( xMutex, xBlockTime )	xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
+#endif
+
+/**
+ * semphr. h
+ * 
xSemaphoreGive( SemaphoreHandle_t xSemaphore )

+ *
+ * Macro to release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
+ *
+ * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for
+ * an alternative which can be used from an ISR.
+ *
+ * This macro must also not be used on semaphores created using
+ * xSemaphoreCreateRecursiveMutex().
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.
+ * Semaphores are implemented using queues.  An error can occur if there is
+ * no space on the queue to post a message - indicating that the
+ * semaphore was not first obtained correctly.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = vSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+        {
+            // We would expect this call to fail because we cannot give
+            // a semaphore without first "taking" it!
+        }
+
+        // Obtain the semaphore - don't block if the semaphore is not
+        // immediately available.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
+        {
+            // We now have the semaphore and can access the shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource so can free the
+            // semaphore.
+            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+            {
+                // We would not expect this call to fail because we must have
+                // obtained the semaphore to get here.
+            }
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreGive xSemaphoreGive
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGive( xSemaphore )		xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
+
+/**
+ * semphr. h
+ * 
xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )

+ *
+ * Macro to recursively release, or 'give', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being released, or 'given'.  This is the
+ * handle returned by xSemaphoreCreateMutex();
+ *
+ * @return pdTRUE if the semaphore was given.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
+			// code these would not be just sequential calls as this would make
+			// no sense.  Instead the calls are likely to be buried inside
+			// a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+			// available to another task until it has also been given back
+			// three times.  Again it is unlikely that real code would have
+			// these calls sequentially, it would be more likely that the calls
+			// to xSemaphoreGiveRecursive() would be called as a call stack
+			// unwound.  This is just for demonstrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+
+			// Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreGiveRecursive( xMutex )	xQueueGiveMutexRecursive( ( xMutex ) )
+#endif
+
+/**
+ * semphr. h
+ * 
+ xSemaphoreGiveFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )

+ *
+ * Macro to  release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR.
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ 
+ \#define LONG_TIME 0xffff
+ \#define TICKS_TO_WAIT	10
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // Repetitive task.
+ void vATask( void * pvParameters )
+ {
+    for( ;; )
+    {
+        // We want this task to run every 10 ticks of a timer.  The semaphore
+        // was created before this task was started.
+
+        // Block waiting for the semaphore to become available.
+        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+        {
+            // It is time to execute.
+
+            // ...
+
+            // We have finished our task.  Return to the top of the loop where
+            // we will block on the semaphore until it is time to execute
+            // again.  Note when using the semaphore for synchronisation with an
+			// ISR in this manner there is no need to 'give' the semaphore back.
+        }
+    }
+ }
+
+ // Timer ISR
+ void vTimerISR( void * pvParameters )
+ {
+ static uint8_t ucLocalTickCount = 0;
+ static BaseType_t xHigherPriorityTaskWoken;
+
+    // A timer tick has occurred.
+
+    // ... Do other time functions.
+
+    // Is it time for vATask () to run?
+	xHigherPriorityTaskWoken = pdFALSE;
+    ucLocalTickCount++;
+    if( ucLocalTickCount >= TICKS_TO_WAIT )
+    {
+        // Unblock the task by releasing the semaphore.
+        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
+
+        // Reset the count so we release the semaphore again in 10 ticks time.
+        ucLocalTickCount = 0;
+    }
+
+    if( xHigherPriorityTaskWoken != pdFALSE )
+    {
+        // We can force a context switch here.  Context switching from an
+        // ISR uses port specific syntax.  Check the demo task for your port
+        // to find the syntax required.
+    }
+ }
+ 

+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * 
+ xSemaphoreTakeFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )

+ *
+ * Macro to  take a semaphore from an ISR.  The semaphore must have
+ * previously been created with a call to xSemaphoreCreateBinary() or
+ * xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR, however taking a semaphore from an ISR
+ * is not a common operation.  It is likely to only be useful when taking a
+ * counting semaphore when an interrupt is obtaining an object from a resource
+ * pool (when the semaphore count indicates the number of resources available).
+ *
+ * @param xSemaphore A handle to the semaphore being taken.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully taken, otherwise
+ * pdFALSE
+ */
+#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateMutex( void )

+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * semaphore is returned.  If there was not enough heap to allocate the mutex
+ * data structures then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer )

+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will be used to hold the mutex's data structure, removing the need for
+ * the memory to be allocated dynamically.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A mutex cannot be used before it has been created.  xMutexBuffer is
+    // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
+    // attempted.
+    xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ 

+ * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic
+ * \ingroup Semaphores
+ */
+ #if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )

+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return xSemaphore Handle to the created mutex semaphore.  Should be of type
+ * SemaphoreHandle_t.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateRecursiveMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer )

+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the recursive mutex's data structure,
+ * removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the recursive mutex was successfully created then a handle to the
+ * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is
+ * returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A recursive semaphore cannot be used before it is created.  Here a
+    // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
+    // The address of xMutexBuffer is passed into the function, and will hold
+    // the mutexes data structures - so no dynamic memory allocation will be
+    // attempted.
+    xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ 

+ * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )

+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer can
+ * instead optionally provide the memory that will get used by the counting
+ * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting
+ * semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @return Handle to the created semaphore.  Null if the semaphore could not be
+ *         created.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+    // The max value to which the semaphore can count should be 10, and the
+    // initial value assigned to the count should be 0.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer )

+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer must
+ * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a
+ * counting semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the counting semaphore was successfully created then a handle to
+ * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL
+ * then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Counting semaphore cannot be used before they have been created.  Create
+    // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
+    // value to which the semaphore can count is 10, and the initial value
+    // assigned to the count will be 0.  The address of xSemaphoreBuffer is
+    // passed in and will be used to hold the semaphore structure, so no dynamic
+    // memory allocation will be used.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
+
+    // No memory allocation was attempted so xSemaphore cannot be NULL, so there
+    // is no need to check its value.
+ }
+ 

+ * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );

+ *
+ * Delete a semaphore.  This function must be used with care.  For example,
+ * do not delete a mutex type semaphore if the mutex is held by a task.
+ *
+ * @param xSemaphore A handle to the semaphore to be deleted.
+ *
+ * \defgroup vSemaphoreDelete vSemaphoreDelete
+ * \ingroup Semaphores
+ */
+#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );

+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ * Note: This is a good way of determining if the calling task is the mutex
+ * holder, but not a good way of determining the identity of the mutex holder as
+ * the holder may change between the function exiting and the returned value
+ * being tested.
+ */
+#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );

+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ */
+#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );

+ *
+ * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns
+ * its current count value.  If the semaphore is a binary semaphore then
+ * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the
+ * semaphore is not available.
+ *
+ */
+#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
+
+#endif /* SEMAPHORE_H */
+
+
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/stack_macros.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/stack_macros.h
new file mode 100644
index 00000000..79a83ea3
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/stack_macros.h
@@ -0,0 +1,129 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten.  Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+																										\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
+		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
+																										\
+		if( ( pulStack[ 0 ] != ulCheckValue ) ||												\
+			( pulStack[ 1 ] != ulCheckValue ) ||												\
+			( pulStack[ 2 ] != ulCheckValue ) ||												\
+			( pulStack[ 3 ] != ulCheckValue ) )												\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
+	{																																	\
+	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
+	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
+																																		\
+																																		\
+		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
+																																		\
+		/* Has the extremity of the task stack ever been written over? */																\
+		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
+		{																																\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
+		}																																\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+	#define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
+
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/stream_buffer.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/stream_buffer.h
new file mode 100644
index 00000000..5418e05b
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/stream_buffer.h
@@ -0,0 +1,852 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Stream buffers are used to send a continuous stream of data from one task or
+ * interrupt to another.  Their implementation is light weight, making them
+ * particularly suited for interrupt to task and core to core communication
+ * scenarios.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section section and set the
+ * receive block time to 0.
+ *
+ */
+
+#ifndef STREAM_BUFFER_H
+#define STREAM_BUFFER_H
+
+#if defined( __cplusplus )
+extern "C" {
+#endif
+
+/**
+ * Type by which stream buffers are referenced.  For example, a call to
+ * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
+ * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
+ * etc.
+ */
+typedef void * StreamBufferHandle_t;
+
+
+/**
+ * message_buffer.h
+ *
+
+StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+

+ *
+ * Creates a new stream buffer using dynamically allocated memory.  See
+ * xStreamBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes the stream buffer will be
+ * able to hold at any one time.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @return If NULL is returned, then the stream buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the stream buffer data structures and storage area.  A non-NULL value being
+ * returned indicates that the stream buffer has been created successfully -
+ * the returned value should be stored as the handle to the created stream
+ * buffer.
+ *
+ * Example use:
+
+
+void vAFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+
+    // Create a stream buffer that can hold 100 bytes.  The memory used to hold
+    // both the stream buffer structure and the data in the stream buffer is
+    // allocated dynamically.
+    xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+
+    if( xStreamBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // stream buffer.
+    }
+    else
+    {
+        // The stream buffer was created successfully and can now be used.
+    }
+}
+

+ * \defgroup xStreamBufferCreate xStreamBufferCreate
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )
+
+/**
+ * stream_buffer.h
+ *
+
+StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
+                                                size_t xTriggerLevelBytes,
+                                                uint8_t *pucStreamBufferStorageArea,
+                                                StaticStreamBuffer_t *pxStaticStreamBuffer );
+

+ * Creates a new stream buffer using statically allocated memory.  See
+ * xStreamBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
+ * xStreamBufferCreateStatic() to be available.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucStreamBufferStorageArea parameter.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes + 1 big.  This is the array to which streams are
+ * copied when they are written to the stream buffer.
+ *
+ * @param pxStaticStreamBuffer Must point to a variable of type
+ * StaticStreamBuffer_t, which will be used to hold the stream buffer's data
+ * structure.
+ *
+ * @return If the stream buffer is created successfully then a handle to the
+ * created stream buffer is returned. If either pucStreamBufferStorageArea or
+ * pxStaticstreamBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+
+
+// Used to dimension the array used to hold the streams.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the streams within the stream
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the stream buffer structure.
+StaticStreamBuffer_t xStreamBufferStruct;
+
+void MyFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xTriggerLevel = 1;
+
+    xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),
+                                               xTriggerLevel,
+                                               ucBufferStorage,
+                                               &xStreamBufferStruct );
+
+    // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+    // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
+    // reference the created stream buffer in other stream buffer API calls.
+
+    // Other code that uses the stream buffer can go here.
+}
+
+

+ * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                          const void *pvTxData,
+                          size_t xDataLengthBytes,
+                          TickType_t xTicksToWait );
+
+ *
+ * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the buffer that holds the bytes to be copied
+ * into the stream buffer.
+ *
+ * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for enough space to become available in the stream
+ * buffer, should the stream buffer contain too little space to hold the
+ * another xDataLengthBytes bytes.  The block time is specified in tick periods,
+ * so the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out
+ * before it can write all xDataLengthBytes into the buffer it will still write
+ * as many bytes as possible.  A task does not use any CPU time when it is in
+ * the blocked state.
+ *
+ * @return The number of bytes written to the stream buffer.  If a task times
+ * out before it can write all xDataLengthBytes into the buffer it will still
+ * write as many bytes as possible.
+ *
+ * Example use:
+
+void vAFunction( StreamBufferHandle_t xStreamBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the stream buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the stream buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xStreamBufferSend() times out before there was enough
+        // space in the buffer for the data to be written, but it did
+        // successfully write xBytesSent bytes.
+    }
+
+    // Send the string to the stream buffer.  Return immediately if there is not
+    // enough space in the buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The entire string could not be added to the stream buffer because
+        // there was not enough free space in the buffer, but xBytesSent bytes
+        // were sent.  Could try again to send the remaining bytes.
+    }
+}
+

+ * \defgroup xStreamBufferSend xStreamBufferSend
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+                                 const void *pvTxData,
+                                 size_t xDataLengthBytes,
+                                 BaseType_t *pxHigherPriorityTaskWoken );
+
+ *
+ * Interrupt safe version of the API function that sends a stream of bytes to
+ * the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the data that is to be copied into the stream
+ * buffer.
+ *
+ * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xStreamBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xStreamBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the example code below for an example.
+ *
+ * @return The number of bytes actually written to the stream buffer, which will
+ * be less than xDataLengthBytes if the stream buffer didn't have enough free
+ * space for all the bytes to be written.
+ *
+ * Example use:
+
+// A stream buffer that has already been created.
+StreamBufferHandle_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the stream buffer.
+    xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
+                                           ( void * ) pcStringToSend,
+                                           strlen( pcStringToSend ),
+                                           &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // There was not enough free space in the stream buffer for the entire
+        // string to be written, ut xBytesSent bytes were written.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                             void *pvRxData,
+                             size_t xBufferLengthBytes,
+                             TickType_t xTicksToWait );
+

+ *
+ * Receives bytes from a stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use
+ * xStreamBufferReceiveFromISR() to read from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which bytes are to
+ * be received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes will be
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for data to become available if the stream buffer is
+ * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is
+ * zero.  The block time is specified in tick periods, so the absolute time it
+ * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can
+ * be used to convert a time specified in milliseconds into a time specified in
+ * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait
+ * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1
+ * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the
+ * Blocked state.
+ *
+ * @return The number of bytes actually read from the stream buffer, which will
+ * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed
+ * out before xBufferLengthBytes were available.
+ *
+ * Example use:
+
+void vAFunction( StreamBuffer_t xStreamBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
+    // Wait in the Blocked state (so not using any CPU processing time) for a
+    // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
+    // available.
+    xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
+                                           ( void * ) ucRxData,
+                                           sizeof( ucRxData ),
+                                           xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains another xRecievedBytes bytes of data, which can
+        // be processed here....
+    }
+}
+

+ * \defgroup xStreamBufferReceive xStreamBufferReceive
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+                                    void *pvRxData,
+                                    size_t xBufferLengthBytes,
+                                    BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * An interrupt safe version of the API function that receives bytes from a
+ * stream buffer.
+ *
+ * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.
+ * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which a stream
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes are
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xStreamBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes read from the stream buffer, if any.
+ *
+ * Example use:
+
+// A stream buffer that has already been created.
+StreamBuffer_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next stream from the stream buffer.
+    xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // ucRxData contains xReceivedBytes read from the stream buffer.
+        // Process the stream here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Deletes a stream buffer that was previously created using a call to
+ * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream
+ * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A stream buffer handle must not be used after the stream buffer has been
+ * deleted.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to be deleted.
+ *
+ * \defgroup vStreamBufferDelete vStreamBufferDelete
+ * \ingroup StreamBufferManagement
+ */
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see if it is full.  A stream buffer is full if it
+ * does not have any free space, and therefore cannot accept any more data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is full then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsFull xStreamBufferIsFull
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
+ * it does not contain any data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Resets a stream buffer to its initial, empty, state.  Any data that was in
+ * the stream buffer is discarded.  A stream buffer can only be reset if there
+ * are no tasks blocked waiting to either send to or receive from the stream
+ * buffer.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being reset.
+ *
+ * @return If the stream buffer is reset then pdPASS is returned.  If there was
+ * a task blocked waiting to send to or read from the stream buffer then the
+ * stream buffer is not reset and pdFAIL is returned.
+ *
+ * \defgroup xStreamBufferReset xStreamBufferReset
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see how much free space it contains, which is
+ * equal to the amount of data that can be sent to the stream buffer before it
+ * is full.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be written to the stream buffer before
+ * the stream buffer would be full.
+ *
+ * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see how much data it contains, which is equal to
+ * the number of bytes that can be read from the stream buffer before the stream
+ * buffer would be empty.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be read from the stream buffer before
+ * the stream buffer would be empty.
+ *
+ * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+

+ *
+ * A stream buffer's trigger level is the number of bytes that must be in the
+ * stream buffer before a task that is blocked on the stream buffer to
+ * wait for data is moved out of the blocked state.  For example, if a task is
+ * blocked on a read of an empty stream buffer that has a trigger level of 1
+ * then the task will be unblocked when a single byte is written to the buffer
+ * or the task's block time expires.  As another example, if a task is blocked
+ * on a read of an empty stream buffer that has a trigger level of 10 then the
+ * task will not be unblocked until the stream buffer contains at least 10 bytes
+ * or the task's block time expires.  If a reading task's block time expires
+ * before the trigger level is reached then the task will still receive however
+ * many bytes are actually available.  Setting a trigger level of 0 will result
+ * in a trigger level of 1 being used.  It is not valid to specify a trigger
+ * level that is greater than the buffer size.
+ *
+ * A trigger level is set when the stream buffer is created, and can be modified
+ * using xStreamBufferSetTriggerLevel().
+ *
+ * @param xStreamBuffer The handle of the stream buffer being updated.
+ *
+ * @param xTriggerLevel The new trigger level for the stream buffer.
+ *
+ * @return If xTriggerLevel was less than or equal to the stream buffer's length
+ * then the trigger level will be updated and pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferSendCompletedFromISR().  If calling
+ * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferReceiveCompletedFromISR().  If calling
+ * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/* Functions below here are not part of the public API. */
+StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+												 size_t xTriggerLevelBytes,
+												 BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
+
+StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+													   size_t xTriggerLevelBytes,
+													   BaseType_t xIsMessageBuffer,
+													   uint8_t * const pucStreamBufferStorageArea,
+													   StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+#if defined( __cplusplus )
+}
+#endif
+
+#endif	/* !defined( STREAM_BUFFER_H ) */
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/task.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/task.h
new file mode 100644
index 00000000..d0ee0681
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/task.h
@@ -0,0 +1,2338 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef INC_TASK_H
+#define INC_TASK_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include task.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+#define tskKERNEL_VERSION_NUMBER "V10.0.1"
+#define tskKERNEL_VERSION_MAJOR 10
+#define tskKERNEL_VERSION_MINOR 0
+#define tskKERNEL_VERSION_BUILD 1
+
+/**
+ * task. h
+ *
+ * Type by which tasks are referenced.  For example, a call to xTaskCreate
+ * returns (via a pointer parameter) an TaskHandle_t variable that can then
+ * be used as a parameter to vTaskDelete to delete the task.
+ *
+ * \defgroup TaskHandle_t TaskHandle_t
+ * \ingroup Tasks
+ */
+typedef void * TaskHandle_t;
+
+/*
+ * Defines the prototype to which the application task hook function must
+ * conform.
+ */
+typedef BaseType_t (*TaskHookFunction_t)( void * );
+
+/* Task states returned by eTaskGetState. */
+typedef enum
+{
+	eRunning = 0,	/* A task is querying the state of itself, so must be running. */
+	eReady,			/* The task being queried is in a read or pending ready list. */
+	eBlocked,		/* The task being queried is in the Blocked state. */
+	eSuspended,		/* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
+	eDeleted,		/* The task being queried has been deleted, but its TCB has not yet been freed. */
+	eInvalid			/* Used as an 'invalid state' value. */
+} eTaskState;
+
+/* Actions that can be performed when vTaskNotify() is called. */
+typedef enum
+{
+	eNoAction = 0,				/* Notify the task without updating its notify value. */
+	eSetBits,					/* Set bits in the task's notification value. */
+	eIncrement,					/* Increment the task's notification value. */
+	eSetValueWithOverwrite,		/* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */
+	eSetValueWithoutOverwrite	/* Set the task's notification value if the previous value has been read by the task. */
+} eNotifyAction;
+
+/*
+ * Used internally only.
+ */
+typedef struct xTIME_OUT
+{
+	BaseType_t xOverflowCount;
+	TickType_t xTimeOnEntering;
+} TimeOut_t;
+
+/*
+ * Defines the memory ranges allocated to the task when an MPU is used.
+ */
+typedef struct xMEMORY_REGION
+{
+	void *pvBaseAddress;
+	uint32_t ulLengthInBytes;
+	uint32_t ulParameters;
+} MemoryRegion_t;
+
+/*
+ * Parameters required to create an MPU protected task.
+ */
+typedef struct xTASK_PARAMETERS
+{
+	TaskFunction_t pvTaskCode;
+	const char * const pcName;	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	uint16_t usStackDepth;
+	void *pvParameters;
+	UBaseType_t uxPriority;
+	StackType_t *puxStackBuffer;
+	MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
+	#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+		StaticTask_t * const pxTaskBuffer;
+	#endif
+} TaskParameters_t;
+
+/* Used with the uxTaskGetSystemState() function to return the state of each task
+in the system. */
+typedef struct xTASK_STATUS
+{
+	TaskHandle_t xHandle;			/* The handle of the task to which the rest of the information in the structure relates. */
+	const char *pcTaskName;			/* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	UBaseType_t xTaskNumber;		/* A number unique to the task. */
+	eTaskState eCurrentState;		/* The state in which the task existed when the structure was populated. */
+	UBaseType_t uxCurrentPriority;	/* The priority at which the task was running (may be inherited) when the structure was populated. */
+	UBaseType_t uxBasePriority;		/* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
+	uint32_t ulRunTimeCounter;		/* The total run time allocated to the task so far, as defined by the run time stats clock.  See http://www.freertos.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
+	StackType_t *pxStackBase;		/* Points to the lowest address of the task's stack area. */
+	uint16_t usStackHighWaterMark;	/* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
+} TaskStatus_t;
+
+/* Possible return values for eTaskConfirmSleepModeStatus(). */
+typedef enum
+{
+	eAbortSleep = 0,		/* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
+	eStandardSleep,			/* Enter a sleep mode that will not last any longer than the expected idle time. */
+	eNoTasksWaitingTimeout	/* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
+} eSleepModeStatus;
+
+/**
+ * Defines the priority used by the idle task.  This must not be modified.
+ *
+ * \ingroup TaskUtils
+ */
+#define tskIDLE_PRIORITY			( ( UBaseType_t ) 0U )
+
+/**
+ * task. h
+ *
+ * Macro for forcing a context switch.
+ *
+ * \defgroup taskYIELD taskYIELD
+ * \ingroup SchedulerControl
+ */
+#define taskYIELD()					portYIELD()
+
+/**
+ * task. h
+ *
+ * Macro to mark the start of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskENTER_CRITICAL()		portENTER_CRITICAL()
+#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
+
+/**
+ * task. h
+ *
+ * Macro to mark the end of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskEXIT_CRITICAL()			portEXIT_CRITICAL()
+#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
+/**
+ * task. h
+ *
+ * Macro to disable all maskable interrupts.
+ *
+ * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskDISABLE_INTERRUPTS()	portDISABLE_INTERRUPTS()
+
+/**
+ * task. h
+ *
+ * Macro to enable microcontroller interrupts.
+ *
+ * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskENABLE_INTERRUPTS()		portENABLE_INTERRUPTS()
+
+/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is
+0 to generate more optimal code when configASSERT() is defined as the constant
+is used in assert() statements. */
+#define taskSCHEDULER_SUSPENDED		( ( BaseType_t ) 0 )
+#define taskSCHEDULER_NOT_STARTED	( ( BaseType_t ) 1 )
+#define taskSCHEDULER_RUNNING		( ( BaseType_t ) 2 )
+
+
+/*-----------------------------------------------------------
+ * TASK CREATION API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreate(
+							  TaskFunction_t pvTaskCode,
+							  const char * const pcName,
+							  configSTACK_DEPTH_TYPE usStackDepth,
+							  void *pvParameters,
+							  UBaseType_t uxPriority,
+							  TaskHandle_t *pvCreatedTask
+						  );

+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * See xTaskCreateStatic() for a version that does not use any dynamic memory
+ * allocation.
+ *
+ * xTaskCreate() can only be used to create a task that has unrestricted
+ * access to the entire microcontroller memory map.  Systems that include MPU
+ * support can alternatively create an MPU constrained task using
+ * xTaskCreateRestricted().
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
+ * is 16.
+ *
+ * @param usStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task should run.  Systems that
+ * include MPU support can optionally create tasks in a privileged (system)
+ * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For
+ * example, to create a privileged task at priority 2 the uxPriority parameter
+ * should be set to ( 2 | portPRIVILEGE_BIT ).
+ *
+ * @param pvCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
+ // Task to be created.
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+	 }
+ }
+
+ // Function that creates a task.
+ void vOtherFunction( void )
+ {
+ static uint8_t ucParameterToPass;
+ TaskHandle_t xHandle = NULL;
+
+	 // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
+	 // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
+	 // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
+	 // the new task attempts to access it.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+     configASSERT( xHandle );
+
+	 // Use the handle to delete the task.
+     if( xHandle != NULL )
+     {
+	     vTaskDelete( xHandle );
+     }
+ }
+   

+ * \defgroup xTaskCreate xTaskCreate
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
+ TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,
+								 const char * const pcName,
+								 uint32_t ulStackDepth,
+								 void *pvParameters,
+								 UBaseType_t uxPriority,
+								 StackType_t *pxStackBuffer,
+								 StaticTask_t *pxTaskBuffer );

+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  The maximum length of the string is defined by
+ * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
+ *
+ * @param ulStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task will run.
+ *
+ * @param pxStackBuffer Must point to a StackType_t array that has at least
+ * ulStackDepth indexes - the array will then be used as the task's stack,
+ * removing the need for the stack to be allocated dynamically.
+ *
+ * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
+ * then be used to hold the task's data structures, removing the need for the
+ * memory to be allocated dynamically.
+ *
+ * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
+ * be created and pdPASS is returned.  If either pxStackBuffer or pxTaskBuffer
+ * are NULL then the task will not be created and
+ * errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY is returned.
+ *
+ * Example usage:
+   
+
+    // Dimensions the buffer that the task being created will use as its stack.
+    // NOTE:  This is the number of words the stack will hold, not the number of
+    // bytes.  For example, if each stack item is 32-bits, and this is set to 100,
+    // then 400 bytes (100 * 32-bits) will be allocated.
+    #define STACK_SIZE 200
+
+    // Structure that will hold the TCB of the task being created.
+    StaticTask_t xTaskBuffer;
+
+    // Buffer that the task being created will use as its stack.  Note this is
+    // an array of StackType_t variables.  The size of StackType_t is dependent on
+    // the RTOS port.
+    StackType_t xStack[ STACK_SIZE ];
+
+    // Function that implements the task being created.
+    void vTaskCode( void * pvParameters )
+    {
+        // The parameter value is expected to be 1 as 1 is passed in the
+        // pvParameters value in the call to xTaskCreateStatic().
+        configASSERT( ( uint32_t ) pvParameters == 1UL );
+
+        for( ;; )
+        {
+            // Task code goes here.
+        }
+    }
+
+    // Function that creates a task.
+    void vOtherFunction( void )
+    {
+        TaskHandle_t xHandle = NULL;
+
+        // Create the task without using any dynamic memory allocation.
+        xHandle = xTaskCreateStatic(
+                      vTaskCode,       // Function that implements the task.
+                      "NAME",          // Text name for the task.
+                      STACK_SIZE,      // Stack size in words, not bytes.
+                      ( void * ) 1,    // Parameter passed into the task.
+                      tskIDLE_PRIORITY,// Priority at which the task is created.
+                      xStack,          // Array to use as the task's stack.
+                      &xTaskBuffer );  // Variable to hold the task's data structure.
+
+        // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
+        // been created, and xHandle will be the task's handle.  Use the handle
+        // to suspend the task.
+        vTaskSuspend( xHandle );
+    }
+   

+ * \defgroup xTaskCreateStatic xTaskCreateStatic
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );

+ *
+ * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestricted() should only be used in systems that include an MPU
+ * implementation.
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ * The function parameters define the memory regions and associated access
+ * permissions allocated to the task.
+ *
+ * See xTaskCreateRestrictedStatic() for a version that does not use any
+ * dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
+// Create an TaskParameters_t structure that defines the task to be created.
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+        { cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+        { cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+        { cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   

+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );

+ *
+ * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestrictedStatic() should only be used in systems that include an
+ * MPU implementation.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreateRestricted() then the stack is provided by the application writer,
+ * and the memory used to hold the task's data structure is automatically
+ * dynamically allocated inside the xTaskCreateRestricted() function.  If a task
+ * is created using xTaskCreateRestrictedStatic() then the application writer
+ * must provide the memory used to hold the task's data structures too.
+ * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be
+ * created without using any dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure
+ * contains an additional member, which is used to point to a variable of type
+ * StaticTask_t - which is then used to hold the task's data structure.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
+// Create an TaskParameters_t structure that defines the task to be created.
+// The StaticTask_t variable is only included in the structure when
+// configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can
+// be used to force the variable into the RTOS kernel's privileged data area.
+static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+        { cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+        { cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+        { cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+
+	&xTaskBuffer; // Holds the task's data structure.
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   

+ * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic
+ * \ingroup Tasks
+ */
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
+ void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );

+ *
+ * Memory regions are assigned to a restricted task when the task is created by
+ * a call to xTaskCreateRestricted().  These regions can be redefined using
+ * vTaskAllocateMPURegions().
+ *
+ * @param xTask The handle of the task being updated.
+ *
+ * @param xRegions A pointer to an MemoryRegion_t structure that contains the
+ * new memory region definitions.
+ *
+ * Example usage:
+   
+// Define an array of MemoryRegion_t structures that configures an MPU region
+// allowing read/write access for 1024 bytes starting at the beginning of the
+// ucOneKByte array.  The other two of the maximum 3 definable regions are
+// unused so set to zero.
+static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
+{
+	// Base address		Length		Parameters
+	{ ucOneKByte,		1024,		portMPU_REGION_READ_WRITE },
+	{ 0,				0,			0 },
+	{ 0,				0,			0 }
+};
+
+void vATask( void *pvParameters )
+{
+	// This task was created such that it has access to certain regions of
+	// memory as defined by the MPU configuration.  At some point it is
+	// desired that these MPU regions are replaced with that defined in the
+	// xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
+	// for this purpose.  NULL is used as the task handle to indicate that this
+	// function should modify the MPU regions of the calling task.
+	vTaskAllocateMPURegions( NULL, xAltRegions );
+
+	// Now the task can continue its function, but from this point on can only
+	// access its stack and the ucOneKByte array (unless any other statically
+	// defined or shared regions have been declared elsewhere).
+}
+   

+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskDelete( TaskHandle_t xTask );

+ *
+ * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Remove a task from the RTOS real time kernel's management.  The task being
+ * deleted will be removed from all ready, blocked, suspended and event lists.
+ *
+ * NOTE:  The idle task is responsible for freeing the kernel allocated
+ * memory from tasks that have been deleted.  It is therefore important that
+ * the idle task is not starved of microcontroller processing time if your
+ * application makes any calls to vTaskDelete ().  Memory allocated by the
+ * task code is not automatically freed, and should be freed before the task
+ * is deleted.
+ *
+ * See the demo application file death.c for sample code that utilises
+ * vTaskDelete ().
+ *
+ * @param xTask The handle of the task to be deleted.  Passing NULL will
+ * cause the calling task to be deleted.
+ *
+ * Example usage:
+   
+ void vOtherFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create the task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // Use the handle to delete the task.
+	 vTaskDelete( xHandle );
+ }
+   

+ * \defgroup vTaskDelete vTaskDelete
+ * \ingroup Tasks
+ */
+void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK CONTROL API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
void vTaskDelay( const TickType_t xTicksToDelay );

+ *
+ * Delay a task for a given number of ticks.  The actual time that the
+ * task remains blocked depends on the tick rate.  The constant
+ * portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ *
+ * vTaskDelay() specifies a time at which the task wishes to unblock relative to
+ * the time at which vTaskDelay() is called.  For example, specifying a block
+ * period of 100 ticks will cause the task to unblock 100 ticks after
+ * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method
+ * of controlling the frequency of a periodic task as the path taken through the
+ * code, as well as other task and interrupt activity, will effect the frequency
+ * at which vTaskDelay() gets called and therefore the time at which the task
+ * next executes.  See vTaskDelayUntil() for an alternative API function designed
+ * to facilitate fixed frequency execution.  It does this by specifying an
+ * absolute time (rather than a relative time) at which the calling task should
+ * unblock.
+ *
+ * @param xTicksToDelay The amount of time, in tick periods, that
+ * the calling task should block.
+ *
+ * Example usage:
+
+ void vTaskFunction( void * pvParameters )
+ {
+ // Block for 500ms.
+ const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		 // Simply toggle the LED every 500ms, blocking between each toggle.
+		 vToggleLED();
+		 vTaskDelay( xDelay );
+	 }
+ }
+
+ * \defgroup vTaskDelay vTaskDelay
+ * \ingroup TaskCtrl
+ */
+void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );

+ *
+ * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Delay a task until a specified time.  This function can be used by periodic
+ * tasks to ensure a constant execution frequency.
+ *
+ * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will
+ * cause a task to block for the specified number of ticks from the time vTaskDelay () is
+ * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed
+ * execution frequency as the time between a task starting to execute and that task
+ * calling vTaskDelay () may not be fixed [the task may take a different path though the
+ * code between calls, or may get interrupted or preempted a different number of times
+ * each time it executes].
+ *
+ * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
+ * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
+ * unblock.
+ *
+ * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
+ * task was last unblocked.  The variable must be initialised with the current time
+ * prior to its first use (see the example below).  Following this the variable is
+ * automatically updated within vTaskDelayUntil ().
+ *
+ * @param xTimeIncrement The cycle time period.  The task will be unblocked at
+ * time *pxPreviousWakeTime + xTimeIncrement.  Calling vTaskDelayUntil with the
+ * same xTimeIncrement parameter value will cause the task to execute with
+ * a fixed interface period.
+ *
+ * Example usage:
+   
+ // Perform an action every 10 ticks.
+ void vTaskFunction( void * pvParameters )
+ {
+ TickType_t xLastWakeTime;
+ const TickType_t xFrequency = 10;
+
+	 // Initialise the xLastWakeTime variable with the current time.
+	 xLastWakeTime = xTaskGetTickCount ();
+	 for( ;; )
+	 {
+		 // Wait for the next cycle.
+		 vTaskDelayUntil( &xLastWakeTime, xFrequency );
+
+		 // Perform action here.
+	 }
+ }
+   

+ * \defgroup vTaskDelayUntil vTaskDelayUntil
+ * \ingroup TaskCtrl
+ */
+void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskAbortDelay( TaskHandle_t xTask );

+ *
+ * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this
+ * function to be available.
+ *
+ * A task will enter the Blocked state when it is waiting for an event.  The
+ * event it is waiting for can be a temporal event (waiting for a time), such
+ * as when vTaskDelay() is called, or an event on an object, such as when
+ * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task
+ * that is in the Blocked state is used in a call to xTaskAbortDelay() then the
+ * task will leave the Blocked state, and return from whichever function call
+ * placed the task into the Blocked state.
+ *
+ * @param xTask The handle of the task to remove from the Blocked state.
+ *
+ * @return If the task referenced by xTask was not in the Blocked state then
+ * pdFAIL is returned.  Otherwise pdPASS is returned.
+ *
+ * \defgroup xTaskAbortDelay xTaskAbortDelay
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask );

+ *
+ * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the priority of any task.
+ *
+ * @param xTask Handle of the task to be queried.  Passing a NULL
+ * handle results in the priority of the calling task being returned.
+ *
+ * @return The priority of xTask.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to obtain the priority of the created task.
+	 // It was created with tskIDLE_PRIORITY, but may have changed
+	 // it itself.
+	 if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+	 {
+		 // The task has changed it's priority.
+	 }
+
+	 // ...
+
+	 // Is our priority higher than the created task?
+	 if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+	 {
+		 // Our priority (obtained using NULL handle) is higher.
+	 }
+ }
+   

+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet
+ * \ingroup TaskCtrl
+ */
+UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask );

+ *
+ * A version of uxTaskPriorityGet() that can be used from an ISR.
+ */
+UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
eTaskState eTaskGetState( TaskHandle_t xTask );

+ *
+ * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the state of any task.  States are encoded by the eTaskState
+ * enumerated type.
+ *
+ * @param xTask Handle of the task to be queried.
+ *
+ * @return The state of xTask at the time the function was called.  Note the
+ * state of the task might change between the function being called, and the
+ * functions return value being tested by the calling task.
+ */
+eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );

+ *
+ * configUSE_TRACE_FACILITY must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * Populates a TaskStatus_t structure with information about a task.
+ *
+ * @param xTask Handle of the task being queried.  If xTask is NULL then
+ * information will be returned about the calling task.
+ *
+ * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be
+ * filled with information about the task referenced by the handle passed using
+ * the xTask parameter.
+ *
+ * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report
+ * the stack high water mark of the task being queried.  Calculating the stack
+ * high water mark takes a relatively long time, and can make the system
+ * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to
+ * allow the high water mark checking to be skipped.  The high watermark value
+ * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is
+ * not set to pdFALSE;
+ *
+ * @param eState The TaskStatus_t structure contains a member to report the
+ * state of the task being queried.  Obtaining the task state is not as fast as
+ * a simple assignment - so the eState parameter is provided to allow the state
+ * information to be omitted from the TaskStatus_t structure.  To obtain state
+ * information then set eState to eInvalid - otherwise the value passed in
+ * eState will be reported as the task state in the TaskStatus_t structure.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+ TaskStatus_t xTaskDetails;
+
+    // Obtain the handle of a task from its name.
+    xHandle = xTaskGetHandle( "Task_Name" );
+
+    // Check the handle is not NULL.
+    configASSERT( xHandle );
+
+    // Use the handle to obtain further information about the task.
+    vTaskGetInfo( xHandle,
+                  &xTaskDetails,
+                  pdTRUE, // Include the high water mark in xTaskDetails.
+                  eInvalid ); // Include the task state in xTaskDetails.
+ }
+   

+ * \defgroup vTaskGetInfo vTaskGetInfo
+ * \ingroup TaskCtrl
+ */
+void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );

+ *
+ * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Set the priority of any task.
+ *
+ * A context switch will occur before the function returns if the priority
+ * being set is higher than the currently executing task.
+ *
+ * @param xTask Handle to the task for which the priority is being set.
+ * Passing a NULL handle results in the priority of the calling task being set.
+ *
+ * @param uxNewPriority The priority to which the task will be set.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to raise the priority of the created task.
+	 vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+
+	 // ...
+
+	 // Use a NULL handle to raise our priority to the same value.
+	 vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ }
+   

+ * \defgroup vTaskPrioritySet vTaskPrioritySet
+ * \ingroup TaskCtrl
+ */
+void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskSuspend( TaskHandle_t xTaskToSuspend );

+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Suspend any task.  When suspended a task will never get any microcontroller
+ * processing time, no matter what its priority.
+ *
+ * Calls to vTaskSuspend are not accumulative -
+ * i.e. calling vTaskSuspend () twice on the same task still only requires one
+ * call to vTaskResume () to ready the suspended task.
+ *
+ * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL
+ * handle will cause the calling task to be suspended.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Suspend ourselves.
+	 vTaskSuspend( NULL );
+
+	 // We cannot get here unless another task calls vTaskResume
+	 // with our handle as the parameter.
+ }
+   

+ * \defgroup vTaskSuspend vTaskSuspend
+ * \ingroup TaskCtrl
+ */
+void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskResume( TaskHandle_t xTaskToResume );

+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Resumes a suspended task.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * vTaskResume ().
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Resume the suspended task ourselves.
+	 vTaskResume( xHandle );
+
+	 // The created task will once again get microcontroller processing
+	 // time in accordance with its priority within the system.
+ }
+   

+ * \defgroup vTaskResume vTaskResume
+ * \ingroup TaskCtrl
+ */
+void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void xTaskResumeFromISR( TaskHandle_t xTaskToResume );

+ *
+ * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * An implementation of vTaskResume() that can be called from within an ISR.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * xTaskResumeFromISR ().
+ *
+ * xTaskResumeFromISR() should not be used to synchronise a task with an
+ * interrupt if there is a chance that the interrupt could arrive prior to the
+ * task being suspended - as this can lead to interrupts being missed. Use of a
+ * semaphore as a synchronisation mechanism would avoid this eventuality.
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * @return pdTRUE if resuming the task should result in a context switch,
+ * otherwise pdFALSE. This is used by the ISR to determine if a context switch
+ * may be required following the ISR.
+ *
+ * \defgroup vTaskResumeFromISR vTaskResumeFromISR
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * SCHEDULER CONTROL
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
void vTaskStartScheduler( void );

+ *
+ * Starts the real time kernel tick processing.  After calling the kernel
+ * has control over which tasks are executed and when.
+ *
+ * See the demo application file main.c for an example of creating
+ * tasks and starting the kernel.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will not get here unless a task calls vTaskEndScheduler ()
+ }
+   

+ *
+ * \defgroup vTaskStartScheduler vTaskStartScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskEndScheduler( void );

+ *
+ * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC
+ * in place of DOS, implements this function.
+ *
+ * Stops the real time kernel tick.  All created tasks will be automatically
+ * deleted and multitasking (either preemptive or cooperative) will
+ * stop.  Execution then resumes from the point where vTaskStartScheduler ()
+ * was called, as if vTaskStartScheduler () had just returned.
+ *
+ * See the demo application file main. c in the demo/PC directory for an
+ * example that uses vTaskEndScheduler ().
+ *
+ * vTaskEndScheduler () requires an exit function to be defined within the
+ * portable layer (see vPortEndScheduler () in port. c for the PC port).  This
+ * performs hardware specific operations such as stopping the kernel tick.
+ *
+ * vTaskEndScheduler () will cause all of the resources allocated by the
+ * kernel to be freed - but will not free resources allocated by application
+ * tasks.
+ *
+ * Example usage:
+   
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // At some point we want to end the real time kernel processing
+		 // so call ...
+		 vTaskEndScheduler ();
+	 }
+ }
+
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will only get here when the vTaskCode () task has called
+	 // vTaskEndScheduler ().  When we get here we are back to single task
+	 // execution.
+ }
+   

+ *
+ * \defgroup vTaskEndScheduler vTaskEndScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskSuspendAll( void );

+ *
+ * Suspends the scheduler without disabling interrupts.  Context switches will
+ * not occur while the scheduler is suspended.
+ *
+ * After calling vTaskSuspendAll () the calling task will continue to execute
+ * without risk of being swapped out until a call to xTaskResumeAll () has been
+ * made.
+ *
+ * API functions that have the potential to cause a context switch (for example,
+ * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
+ * is suspended.
+ *
+ * Example usage:
+   
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the kernel
+		 // tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.
+		 xTaskResumeAll ();
+	 }
+ }
+   

+ * \defgroup vTaskSuspendAll vTaskSuspendAll
+ * \ingroup SchedulerControl
+ */
+void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskResumeAll( void );

+ *
+ * Resumes scheduler activity after it was suspended by a call to
+ * vTaskSuspendAll().
+ *
+ * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks
+ * that were previously suspended by a call to vTaskSuspend().
+ *
+ * @return If resuming the scheduler caused a context switch then pdTRUE is
+ *		  returned, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+   
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the real
+		 // time kernel tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.  We want to force
+		 // a context switch - but there is no point if resuming the scheduler
+		 // caused a context switch already.
+		 if( !xTaskResumeAll () )
+		 {
+			  taskYIELD ();
+		 }
+	 }
+ }
+   

+ * \defgroup xTaskResumeAll xTaskResumeAll
+ * \ingroup SchedulerControl
+ */
+BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK UTILITIES
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
TickType_t xTaskGetTickCount( void );

+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * \defgroup xTaskGetTickCount xTaskGetTickCount
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
TickType_t xTaskGetTickCountFromISR( void );

+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * This is a version of xTaskGetTickCount() that is safe to be called from an
+ * ISR - provided that TickType_t is the natural word size of the
+ * microcontroller being used or interrupt nesting is either not supported or
+ * not being used.
+ *
+ * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
uint16_t uxTaskGetNumberOfTasks( void );

+ *
+ * @return The number of tasks that the real time kernel is currently managing.
+ * This includes all ready, blocked and suspended tasks.  A task that
+ * has been deleted but not yet freed by the idle task will also be
+ * included in the count.
+ *
+ * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
+ * \ingroup TaskUtils
+ */
+UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
char *pcTaskGetName( TaskHandle_t xTaskToQuery );

+ *
+ * @return The text (human readable) name of the task referenced by the handle
+ * xTaskToQuery.  A task can query its own name by either passing in its own
+ * handle, or by setting xTaskToQuery to NULL.
+ *
+ * \defgroup pcTaskGetName pcTaskGetName
+ * \ingroup TaskUtils
+ */
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * 
TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );

+ *
+ * NOTE:  This function takes a relatively long time to complete and should be
+ * used sparingly.
+ *
+ * @return The handle of the task that has the human readable name pcNameToQuery.
+ * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle
+ * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.
+ *
+ * \defgroup pcTaskGetHandle pcTaskGetHandle
+ * \ingroup TaskUtils
+ */
+TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task.h
+ * 
UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );

+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/* When using trace macros it is sometimes necessary to include task.h before
+FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
+so the following two prototypes will cause a compilation error.  This can be
+fixed by simply guarding against the inclusion of these two prototypes unless
+they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
+constant. */
+#ifdef configUSE_APPLICATION_TASK_TAG
+	#if configUSE_APPLICATION_TASK_TAG == 1
+		/**
+		 * task.h
+		 * 
void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );

+		 *
+		 * Sets pxHookFunction to be the task hook function used by the task xTask.
+		 * Passing xTask as NULL has the effect of setting the calling tasks hook
+		 * function.
+		 */
+		void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * 
void xTaskGetApplicationTaskTag( TaskHandle_t xTask );

+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+	#endif /* configUSE_APPLICATION_TASK_TAG ==1 */
+#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
+
+#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+
+	/* Each task contains an array of pointers that is dimensioned by the
+	configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The
+	kernel does not use the pointers itself, so the application writer can use
+	the pointers for any purpose they wish.  The following two functions are
+	used to set and query a pointer respectively. */
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) PRIVILEGED_FUNCTION;
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/**
+ * task.h
+ * 
BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );

+ *
+ * Calls the hook function associated with xTask.  Passing xTask as NULL has
+ * the effect of calling the Running tasks (the calling task) hook function.
+ *
+ * pvParameter is passed to the hook function for the task to interpret as it
+ * wants.  The return value is the value returned by the task hook function
+ * registered by the user.
+ */
+BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;
+
+/**
+ * xTaskGetIdleTaskHandle() is only available if
+ * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
+ *
+ * Simply returns the handle of the idle task.  It is not valid to call
+ * xTaskGetIdleTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
+ * uxTaskGetSystemState() to be available.
+ *
+ * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
+ * the system.  TaskStatus_t structures contain, among other things, members
+ * for the task handle, task name, task priority, task state, and total amount
+ * of run time consumed by the task.  See the TaskStatus_t structure
+ * definition in this file for the full member list.
+ *
+ * NOTE:  This function is intended for debugging use only as its use results in
+ * the scheduler remaining suspended for an extended period.
+ *
+ * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
+ * The array must contain at least one TaskStatus_t structure for each task
+ * that is under the control of the RTOS.  The number of tasks under the control
+ * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
+ *
+ * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
+ * parameter.  The size is specified as the number of indexes in the array, or
+ * the number of TaskStatus_t structures contained in the array, not by the
+ * number of bytes in the array.
+ *
+ * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
+ * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
+ * total run time (as defined by the run time stats clock, see
+ * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.
+ * pulTotalRunTime can be set to NULL to omit the total run time information.
+ *
+ * @return The number of TaskStatus_t structures that were populated by
+ * uxTaskGetSystemState().  This should equal the number returned by the
+ * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
+ * in the uxArraySize parameter was too small.
+ *
+ * Example usage:
+   
+    // This example demonstrates how a human readable table of run time stats
+	// information is generated from raw data provided by uxTaskGetSystemState().
+	// The human readable table is written to pcWriteBuffer
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	volatile UBaseType_t uxArraySize, x;
+	uint32_t ulTotalRunTime, ulStatsAsPercentage;
+
+		// Make sure the write buffer does not contain a string.
+		*pcWriteBuffer = 0x00;
+
+		// Take a snapshot of the number of tasks in case it changes while this
+		// function is executing.
+		uxArraySize = uxTaskGetNumberOfTasks();
+
+		// Allocate a TaskStatus_t structure for each task.  An array could be
+		// allocated statically at compile time.
+		pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
+
+		if( pxTaskStatusArray != NULL )
+		{
+			// Generate raw status information about each task.
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
+
+			// For percentage calculations.
+			ulTotalRunTime /= 100UL;
+
+			// Avoid divide by zero errors.
+			if( ulTotalRunTime > 0 )
+			{
+				// For each populated position in the pxTaskStatusArray array,
+				// format the raw data as human readable ASCII data
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					// What percentage of the total run time has the task used?
+					// This will always be rounded down to the nearest integer.
+					// ulTotalRunTimeDiv100 has already been divided by 100.
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+					}
+					else
+					{
+						// If the percentage is zero here then the task has
+						// consumed less than 1% of the total run time.
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
+					}
+
+					pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
+				}
+			}
+
+			// The array is no longer needed, free the memory it consumes.
+			vPortFree( pxTaskStatusArray );
+		}
+	}
+	

+ */
+UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskList( char *pcWriteBuffer );

+ *
+ * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
+ * both be defined as 1 for this function to be available.  See the
+ * configuration section of the FreeRTOS.org website for more information.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Lists all the current tasks, along with their current state and stack
+ * usage high water mark.
+ *
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
+ * suspended ('S').
+ *
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays task
+ * names, states and stack usage.
+ *
+ * vTaskList() has a dependency on the sprintf() C library function that might
+ * bloat the code size, use a lot of stack, and provide different results on
+ * different platforms.  An alternative, tiny, third party, and limited
+ * functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly through a
+ * call to vTaskList().
+ *
+ * @param pcWriteBuffer A buffer into which the above mentioned details
+ * will be written, in ASCII form.  This buffer is assumed to be large
+ * enough to contain the generated report.  Approximately 40 bytes per
+ * task should be sufficient.
+ *
+ * \defgroup vTaskList vTaskList
+ * \ingroup TaskUtils
+ */
+void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * 
void vTaskGetRunTimeStats( char *pcWriteBuffer );

+ *
+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+ * must both be defined as 1 for this function to be available.  The application
+ * must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+ * to configure a peripheral timer/counter and return the timers current count
+ * value respectively.  The counter should be at least 10 times the frequency of
+ * the tick count.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task.  The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * Calling vTaskGetRunTimeStats() writes the total execution time of each
+ * task into a buffer, both as an absolute count value and as a percentage
+ * of the total system execution time.
+ *
+ * NOTE 2:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays the
+ * amount of time each task has spent in the Running state in both absolute and
+ * percentage terms.
+ *
+ * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
+ * that might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms.  An alternative, tiny, third party, and
+ * limited functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState() directly
+ * to get access to raw stats data, rather than indirectly through a call to
+ * vTaskGetRunTimeStats().
+ *
+ * @param pcWriteBuffer A buffer into which the execution times will be
+ * written, in ASCII form.  This buffer is assumed to be large enough to
+ * contain the generated report.  Approximately 40 bytes per task should
+ * be sufficient.
+ *
+ * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
+ * \ingroup TaskUtils
+ */
+void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ *  pulPreviousNotificationValue -
+ *  Can be used to pass out the subject task's notification value before any
+ *  bits are modified by the notify function.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;
+#define xTaskNotify( xTaskToNotify, ulValue, eAction ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL )
+#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotify() that can be used from an interrupt service routine
+ * (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should
+ * be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
+#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value
+ * will be cleared in the calling task's notification value before the task
+ * checks to see if any notifications are pending, and optionally blocks if no
+ * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if
+ * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
+ * the effect of resetting the task's notification value to 0.  Setting
+ * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
+ *
+ * @param ulBitsToClearOnExit If a notification is pending or received before
+ * the calling task exits the xTaskNotifyWait() function then the task's
+ * notification value (see the xTaskNotify() API function) is passed out using
+ * the pulNotificationValue parameter.  Then any bits that are set in
+ * ulBitsToClearOnExit will be cleared in the task's notification value (note
+ * *pulNotificationValue is set before any bits are cleared).  Setting
+ * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL
+ * (if limits.h is not included) will have the effect of resetting the task's
+ * notification value to 0 before the function exits.  Setting
+ * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged
+ * when the function exits (in which case the value passed out in
+ * pulNotificationValue will match the task's notification value).
+ *
+ * @param pulNotificationValue Used to pass the task's notification value out
+ * of the function.  Note the value passed out will not be effected by the
+ * clearing of any bits caused by ulBitsToClearOnExit being non-zero.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for a notification to be received, should a notification
+ * not already be pending when xTaskNotifyWait() was called.  The task
+ * will not consume any processing time while it is in the Blocked state.  This
+ * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be
+ * used to convert a time specified in milliseconds to a time specified in
+ * ticks.
+ *
+ * @return If a notification was received (including notifications that were
+ * already pending when xTaskNotifyWait was called) then pdPASS is
+ * returned.  Otherwise pdFAIL is returned.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * xTaskNotifyGive() is a helper macro intended for use when task notifications
+ * are used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given using the xSemaphoreGive() API function,
+ * the equivalent action that instead uses a task notification is
+ * xTaskNotifyGive().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the
+ * eAction parameter set to eIncrement - so pdPASS is always returned.
+ *
+ * \defgroup xTaskNotifyGive xTaskNotifyGive
+ * \ingroup TaskNotifications
+ */
+#define xTaskNotifyGive( xTaskToNotify ) xTaskGenericNotify( ( xTaskToNotify ), ( 0 ), eIncrement, NULL )
+
+/**
+ * task. h
+ * 
void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotifyGive() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * vTaskNotifyGiveFromISR() is intended for use when task notifications are
+ * used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given from an ISR using the
+ * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
+ * a task notification is vTaskNotifyGiveFromISR().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
+ * should be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * ulTaskNotifyTake() is intended for use when a task notification is used as a
+ * faster and lighter weight binary or counting semaphore alternative.  Actual
+ * FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the
+ * equivalent action that instead uses a task notification is
+ * ulTaskNotifyTake().
+ *
+ * When a task is using its notification value as a binary or counting semaphore
+ * other tasks should send notifications to it using the xTaskNotifyGive()
+ * macro, or xTaskNotify() function with the eAction parameter set to
+ * eIncrement.
+ *
+ * ulTaskNotifyTake() can either clear the task's notification value to
+ * zero on exit, in which case the notification value acts like a binary
+ * semaphore, or decrement the task's notification value on exit, in which case
+ * the notification value acts like a counting semaphore.
+ *
+ * A task can use ulTaskNotifyTake() to [optionally] block to wait for a
+ * the task's notification value to be non-zero.  The task does not consume any
+ * CPU time while it is in the Blocked state.
+ *
+ * Where as xTaskNotifyWait() will return when a notification is pending,
+ * ulTaskNotifyTake() will return when the task's notification value is
+ * not zero.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
+ * notification value is decremented when the function exits.  In this way the
+ * notification value acts like a counting semaphore.  If xClearCountOnExit is
+ * not pdFALSE then the task's notification value is cleared to zero when the
+ * function exits.  In this way the notification value acts like a binary
+ * semaphore.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for the task's notification value to be greater than zero,
+ * should the count not already be greater than zero when
+ * ulTaskNotifyTake() was called.  The task will not consume any processing
+ * time while it is in the Blocked state.  This is specified in kernel ticks,
+ * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time
+ * specified in milliseconds to a time specified in ticks.
+ *
+ * @return The task's notification count before it is either cleared to zero or
+ * decremented (see the xClearCountOnExit parameter).
+ *
+ * \defgroup ulTaskNotifyTake ulTaskNotifyTake
+ * \ingroup TaskNotifications
+ */
+uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );

+ *
+ * If the notification state of the task referenced by the handle xTask is
+ * eNotified, then set the task's notification state to eNotWaitingNotification.
+ * The task's notification value is not altered.  Set xTask to NULL to clear the
+ * notification state of the calling task.
+ *
+ * @return pdTRUE if the task's notification state was set to
+ * eNotWaitingNotification, otherwise pdFALSE.
+ * \defgroup xTaskNotifyStateClear xTaskNotifyStateClear
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
+
+/*-----------------------------------------------------------
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
+ *----------------------------------------------------------*/
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Called from the real time kernel tick (either preemptive or cooperative),
+ * this increments the tick count and checks if any tasks that are blocked
+ * for a finite period required removing from a blocked list and placing on
+ * a ready list.  If a non-zero value is returned then a context switch is
+ * required because either:
+ *   + A task was removed from a blocked list because its timeout had expired,
+ *     or
+ *   + Time slicing is in use and there is a task of equal priority to the
+ *     currently running task.
+ */
+BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes the calling task from the ready list and places it both
+ * on the list of tasks waiting for a particular event, and the
+ * list of delayed tasks.  The task will be removed from both lists
+ * and replaced on the ready list should either the event occur (and
+ * there be no higher priority tasks waiting on the same event) or
+ * the delay period expires.
+ *
+ * The 'unordered' version replaces the event list item value with the
+ * xItemValue value, and inserts the list item at the end of the list.
+ *
+ * The 'ordered' version uses the existing event list item value (which is the
+ * owning tasks priority) to insert the list item into the event list is task
+ * priority order.
+ *
+ * @param pxEventList The list containing tasks that are blocked waiting
+ * for the event to occur.
+ *
+ * @param xItemValue The item value to use for the event list item when the
+ * event list is not ordered by task priority.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait
+ * for the event to occur.  This is specified in kernel ticks,the constant
+ * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
+ * period.
+ */
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * This function performs nearly the same function as vTaskPlaceOnEventList().
+ * The difference being that this function does not permit tasks to block
+ * indefinitely, whereas vTaskPlaceOnEventList() does.
+ *
+ */
+void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes a task from both the specified event list and the list of blocked
+ * tasks, and places it on a ready queue.
+ *
+ * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called
+ * if either an event occurs to unblock a task, or the block timeout period
+ * expires.
+ *
+ * xTaskRemoveFromEventList() is used when the event list is in task priority
+ * order.  It removes the list item from the head of the event list as that will
+ * have the highest priority owning task of all the tasks on the event list.
+ * vTaskRemoveFromUnorderedEventList() is used when the event list is not
+ * ordered and the event list items hold something other than the owning tasks
+ * priority.  In this case the event list item value is updated to the value
+ * passed in the xItemValue parameter.
+ *
+ * @return pdTRUE if the task being removed has a higher priority than the task
+ * making the call, otherwise pdFALSE.
+ */
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Sets the pointer to the current TCB to the TCB of the highest priority task
+ * that is ready to run.
+ */
+void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
+ * THE EVENT BITS MODULE.
+ */
+TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the handle of the calling task.
+ */
+TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Capture the current time status for future reference.
+ */
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+/*
+ * Compare the time status now with that previously captured to see if the
+ * timeout has expired.
+ */
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * Shortcut used by the queue implementation to prevent unnecessary call to
+ * taskYIELD();
+ */
+void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns the scheduler state as taskSCHEDULER_RUNNING,
+ * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
+ */
+BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Raises the priority of the mutex holder to that of the calling task should
+ * the mutex holder have a priority less than the calling task.
+ */
+BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the priority of a task back to its proper priority in the case that it
+ * inherited a higher priority while it was holding a semaphore.
+ */
+BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a higher priority task attempting to obtain a mutex caused a lower
+ * priority task to inherit the higher priority task's priority - but the higher
+ * priority task then timed out without obtaining the mutex, then the lower
+ * priority task will disinherit the priority again - but only down as far as
+ * the highest priority task that is still waiting for the mutex (if there were
+ * more than one task waiting for the mutex).
+ */
+void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
+ */
+UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the uxTaskNumber of the task referenced by the xTask parameter to
+ * uxHandle.
+ */
+void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * If tickless mode is being used, or a low power mode is implemented, then
+ * the tick interrupt will not execute during idle periods.  When this is the
+ * case, the tick count value maintained by the scheduler needs to be kept up
+ * to date with the actual execution time by being skipped forward by a time
+ * equal to the idle period.
+ */
+void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only avilable when configUSE_TICKLESS_IDLE is set to 1.
+ * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
+ * specific sleep function to determine if it is ok to proceed with the sleep,
+ * and if it is ok to proceed, if it is ok to sleep indefinitely.
+ *
+ * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
+ * called with the scheduler suspended, not from within a critical section.  It
+ * is therefore possible for an interrupt to request a context switch between
+ * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
+ * entered.  eTaskConfirmSleepModeStatus() should be called from a short
+ * critical section between the timer being stopped and the sleep mode being
+ * entered to ensure it is ok to proceed into the sleep mode.
+ */
+eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Increment the mutex held count when a mutex is
+ * taken and return the handle of the task that has taken the mutex.
+ */
+void *pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Same as vTaskSetTimeOutState(), but without a critial
+ * section.
+ */
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* INC_TASK_H */
+
+
+
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/timers.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/timers.h
new file mode 100644
index 00000000..05eb90fc
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/include/timers.h
@@ -0,0 +1,1277 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef TIMERS_H
+#define TIMERS_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include timers.h"
+#endif
+
+/*lint -save -e537 This headers are only multiply included if the application code
+happens to also be including task.h. */
+#include "task.h"
+/*lint -restore */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+/* IDs for commands that can be sent/received on the timer queue.  These are to
+be used solely through the macros that make up the public software timer API,
+as defined below.  The commands that are sent from interrupts must use the
+highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
+or interrupt version of the queue send function should be used. */
+#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR 	( ( BaseType_t ) -2 )
+#define tmrCOMMAND_EXECUTE_CALLBACK				( ( BaseType_t ) -1 )
+#define tmrCOMMAND_START_DONT_TRACE				( ( BaseType_t ) 0 )
+#define tmrCOMMAND_START					    ( ( BaseType_t ) 1 )
+#define tmrCOMMAND_RESET						( ( BaseType_t ) 2 )
+#define tmrCOMMAND_STOP							( ( BaseType_t ) 3 )
+#define tmrCOMMAND_CHANGE_PERIOD				( ( BaseType_t ) 4 )
+#define tmrCOMMAND_DELETE						( ( BaseType_t ) 5 )
+
+#define tmrFIRST_FROM_ISR_COMMAND				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_START_FROM_ISR				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_RESET_FROM_ISR				( ( BaseType_t ) 7 )
+#define tmrCOMMAND_STOP_FROM_ISR				( ( BaseType_t ) 8 )
+#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR		( ( BaseType_t ) 9 )
+
+
+/**
+ * Type by which software timers are referenced.  For example, a call to
+ * xTimerCreate() returns an TimerHandle_t variable that can then be used to
+ * reference the subject timer in calls to other software timer API functions
+ * (for example, xTimerStart(), xTimerReset(), etc.).
+ */
+typedef void * TimerHandle_t;
+
+/*
+ * Defines the prototype to which timer callback functions must conform.
+ */
+typedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );
+
+/*
+ * Defines the prototype to which functions used with the
+ * xTimerPendFunctionCallFromISR() function must conform.
+ */
+typedef void (*PendedFunction_t)( void *, uint32_t );
+
+/**
+ * TimerHandle_t xTimerCreate( 	const char * const pcTimerName,
+ * 								TickType_t xTimerPeriodInTicks,
+ * 								UBaseType_t uxAutoReload,
+ * 								void * pvTimerID,
+ * 								TimerCallbackFunction_t pxCallbackFunction );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is	"void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @return If the timer is successfully created then a handle to the newly
+ * created timer is returned.  If the timer cannot be created (because either
+ * there is insufficient FreeRTOS heap remaining to allocate the timer
+ * structures, or the timer period was set to 0) then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ * #define NUM_TIMERS 5
+ *
+ * // An array to hold handles to the created timers.
+ * TimerHandle_t xTimers[ NUM_TIMERS ];
+ *
+ * // An array to hold a count of the number of times each timer expires.
+ * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
+ *
+ * // Define a callback function that will be used by multiple timer instances.
+ * // The callback function does nothing but count the number of times the
+ * // associated timer expires, and stop the timer once the timer has expired
+ * // 10 times.
+ * void vTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * int32_t lArrayIndex;
+ * const int32_t xMaxExpiryCountBeforeStopping = 10;
+ *
+ * 	   // Optionally do something if the pxTimer parameter is NULL.
+ * 	   configASSERT( pxTimer );
+ *
+ *     // Which timer expired?
+ *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
+ *
+ *     // Increment the number of times that pxTimer has expired.
+ *     lExpireCounters[ lArrayIndex ] += 1;
+ *
+ *     // If the timer has expired 10 times then stop it from running.
+ *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
+ *     {
+ *         // Do not use a block time if calling a timer API function from a
+ *         // timer callback function, as doing so could cause a deadlock!
+ *         xTimerStop( pxTimer, 0 );
+ *     }
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start some timers.  Starting the timers before the scheduler
+ *     // has been started means the timers will start running immediately that
+ *     // the scheduler starts.
+ *     for( x = 0; x < NUM_TIMERS; x++ )
+ *     {
+ *         xTimers[ x ] = xTimerCreate(    "Timer",       // Just a text name, not used by the kernel.
+ *                                         ( 100 * x ),   // The timer period in ticks.
+ *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.
+ *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.
+ *                                         vTimerCallback // Each timer calls the same callback when it expires.
+ *                                     );
+ *
+ *         if( xTimers[ x ] == NULL )
+ *         {
+ *             // The timer was not created.
+ *         }
+ *         else
+ *         {
+ *             // Start the timer.  No block time is specified, and even if one was
+ *             // it would be ignored because the scheduler has not yet been
+ *             // started.
+ *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
+ *             {
+ *                 // The timer could not be set into the Active state.
+ *             }
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,
+ * 									TickType_t xTimerPeriodInTicks,
+ * 									UBaseType_t uxAutoReload,
+ * 									void * pvTimerID,
+ * 									TimerCallbackFunction_t pxCallbackFunction,
+ *									StaticTimer_t *pxTimerBuffer );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is "void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which
+ * will be then be used to hold the software timer's data structures, removing
+ * the need for the memory to be allocated dynamically.
+ *
+ * @return If the timer is created then a handle to the created timer is
+ * returned.  If pxTimerBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ * // The buffer used to hold the software timer's data structure.
+ * static StaticTimer_t xTimerBuffer;
+ *
+ * // A variable that will be incremented by the software timer's callback
+ * // function.
+ * UBaseType_t uxVariableToIncrement = 0;
+ *
+ * // A software timer callback function that increments a variable passed to
+ * // it when the software timer was created.  After the 5th increment the
+ * // callback function stops the software timer.
+ * static void prvTimerCallback( TimerHandle_t xExpiredTimer )
+ * {
+ * UBaseType_t *puxVariableToIncrement;
+ * BaseType_t xReturned;
+ *
+ *     // Obtain the address of the variable to increment from the timer ID.
+ *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
+ *
+ *     // Increment the variable to show the timer callback has executed.
+ *     ( *puxVariableToIncrement )++;
+ *
+ *     // If this callback has executed the required number of times, stop the
+ *     // timer.
+ *     if( *puxVariableToIncrement == 5 )
+ *     {
+ *         // This is called from a timer callback so must not block.
+ *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );
+ *     }
+ * }
+ *
+ *
+ * void main( void )
+ * {
+ *     // Create the software time.  xTimerCreateStatic() has an extra parameter
+ *     // than the normal xTimerCreate() API function.  The parameter is a pointer
+ *     // to the StaticTimer_t structure that will hold the software timer
+ *     // structure.  If the parameter is passed as NULL then the structure will be
+ *     // allocated dynamically, just as if xTimerCreate() had been called.
+ *     xTimer = xTimerCreateStatic( "T1",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.
+ *                                  xTimerPeriod,     // The period of the timer in ticks.
+ *                                  pdTRUE,           // This is an auto-reload timer.
+ *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function
+ *                                  prvTimerCallback, // The function to execute when the timer expires.
+ *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.
+ *
+ *     // The scheduler has not started yet so a block time is not used.
+ *     xReturned = xTimerStart( xTimer, 0 );
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * void *pvTimerGetTimerID( TimerHandle_t xTimer );
+ *
+ * Returns the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer, and by calling the
+ * vTimerSetTimerID() API function.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return The ID assigned to the timer being queried.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void *pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
+ *
+ * Sets the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being updated.
+ *
+ * @param pvNewID The ID to assign to the timer.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
+ *
+ * Queries a timer to see if it is active or dormant.
+ *
+ * A timer will be dormant if:
+ *     1) It has been created but not started, or
+ *     2) It is an expired one-shot timer that has not been restarted.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
+ * active state.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return pdFALSE will be returned if the timer is dormant.  A value other than
+ * pdFALSE will be returned if the timer is active.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is active, do something.
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, do something else.
+ *     }
+ * }
+ * @endverbatim
+ */
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
+ *
+ * Simply returns the handle of the timer service/daemon task.  It it not valid
+ * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStart() starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerStart() has equivalent functionality
+ * to the xTimerReset() API function.
+ *
+ * Starting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerStart() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerStart() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerStart() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the start command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStop() stops a timer that was previously started using either of the
+ * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
+ * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
+ *
+ * Stopping a timer ensures the timer is not in the active state.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the stop command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerChangePeriod( 	TimerHandle_t xTimer,
+ *										TickType_t xNewPeriod,
+ *										TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerChangePeriod() changes the period of a timer that was previously
+ * created using the xTimerCreate() API function.
+ *
+ * xTimerChangePeriod() can be called to change the period of an active or
+ * dormant state timer.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerChangePeriod() to be available.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the change period command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if
+ * xTimerChangePeriod() is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the change period command could not be
+ * sent to the timer command queue even after xTicksToWait ticks had passed.
+ * pdPASS will be returned if the command was successfully sent to the timer
+ * command queue.  When the command is actually processed will depend on the
+ * priority of the timer service/daemon task relative to other tasks in the
+ * system.  The timer service/daemon task priority is set by the
+ * configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.  If the timer
+ * // referenced by xTimer is already active when it is called, then the timer
+ * // is deleted.  If the timer referenced by xTimer is not active when it is
+ * // called, then the period of the timer is set to 500ms and the timer is
+ * // started.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is already active - delete it.
+ *         xTimerDelete( xTimer );
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, change its period to 500ms.  This will also
+ *         // cause the timer to start.  Block for a maximum of 100 ticks if the
+ *         // change period command cannot immediately be sent to the timer
+ *         // command queue.
+ *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
+ *         {
+ *             // The command was successfully sent.
+ *         }
+ *         else
+ *         {
+ *             // The command could not be sent, even after waiting for 100 ticks
+ *             // to pass.  Take appropriate action here.
+ *         }
+ *     }
+ * }
+ * @endverbatim
+ */
+ #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerDelete() deletes a timer that was previously created using the
+ * xTimerCreate() API function.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerDelete() to be available.
+ *
+ * @param xTimer The handle of the timer being deleted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the delete command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()
+ * is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the delete command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerChangePeriod() API function example usage scenario.
+ */
+#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerReset() re-starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerReset() will cause the timer to
+ * re-evaluate its expiry time so that it is relative to when xTimerReset() was
+ * called.  If the timer was in the dormant state then xTimerReset() has
+ * equivalent functionality to the xTimerStart() API function.
+ *
+ * Resetting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerReset() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerReset() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerReset() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being reset/started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the reset command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer.
+ *
+ * TimerHandle_t xBacklightTimer = NULL;
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press event handler.
+ * void vKeyPressEventHandler( char cKey )
+ * {
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
+ *     // if it cannot be sent immediately.
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start the one-shot timer that is responsible for turning
+ *     // the back-light off if no keys are pressed within a 5 second period.
+ *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
+ *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
+ *                                     pdFALSE,                    // The timer is a one-shot timer.
+ *                                     0,                          // The id is not used by the callback so can take any value.
+ *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
+ *                                   );
+ *
+ *     if( xBacklightTimer == NULL )
+ *     {
+ *         // The timer was not created.
+ *     }
+ *     else
+ *     {
+ *         // Start the timer.  No block time is specified, and even if one was
+ *         // it would be ignored because the scheduler has not yet been
+ *         // started.
+ *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
+ *         {
+ *             // The timer could not be set into the Active state.
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timer running as it has already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStartFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStart() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStartFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStartFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStartFromISR() function.  If
+ * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerStartFromISR() is actually called.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then restart the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The start command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerStopFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStop() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStopFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStopFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStopFromISR() function.  If
+ * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the timer should be simply stopped.
+ *
+ * // The interrupt service routine that stops the timer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - simply stop the timer.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The stop command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
+ *										 TickType_t xNewPeriod,
+ *										 BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerChangePeriod() that can be called from an interrupt
+ * service routine.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the
+ * timer command queue, so has the potential to transition the timer service/
+ * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()
+ * causes the timer service/daemon task to leave the Blocked state, and the
+ * timer service/daemon task has a priority equal to or greater than the
+ * currently executing task (the task that was interrupted), then
+ * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
+ * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets
+ * this value to pdTRUE then a context switch should be performed before the
+ * interrupt exits.
+ *
+ * @return pdFAIL will be returned if the command to change the timers period
+ * could not be sent to the timer command queue.  pdPASS will be returned if the
+ * command was successfully sent to the timer command queue.  When the command
+ * is actually processed will depend on the priority of the timer service/daemon
+ * task relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the period of xTimer should be changed to 500ms.
+ *
+ * // The interrupt service routine that changes the period of xTimer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - change the period of xTimer to 500ms.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The command to change the timers period was not executed
+ *         // successfully.  Take appropriate action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerResetFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerReset() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer that is to be started, reset, or
+ * restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerResetFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerResetFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerResetFromISR() function.  If
+ * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+
+/**
+ * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+ *                                          void *pvParameter1,
+ *                                          uint32_t ulParameter2,
+ *                                          BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ *
+ * Used from application interrupt service routines to defer the execution of a
+ * function to the RTOS daemon task (the timer service task, hence this function
+ * is implemented in timers.c and is prefixed with 'Timer').
+ *
+ * Ideally an interrupt service routine (ISR) is kept as short as possible, but
+ * sometimes an ISR either has a lot of processing to do, or needs to perform
+ * processing that is not deterministic.  In these cases
+ * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
+ * to the RTOS daemon task.
+ *
+ * A mechanism is provided that allows the interrupt to return directly to the
+ * task that will subsequently execute the pended callback function.  This
+ * allows the callback function to execute contiguously in time with the
+ * interrupt - just as if the callback had executed in the interrupt itself.
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task.  The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task (which is set using
+ * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
+ * the currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE within
+ * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ *	// The callback function that will execute in the context of the daemon task.
+ *  // Note callback functions must all use this same prototype.
+ *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
+ *	{
+ *		BaseType_t xInterfaceToService;
+ *
+ *		// The interface that requires servicing is passed in the second
+ *      // parameter.  The first parameter is not used in this case.
+ *		xInterfaceToService = ( BaseType_t ) ulParameter2;
+ *
+ *		// ...Perform the processing here...
+ *	}
+ *
+ *	// An ISR that receives data packets from multiple interfaces
+ *  void vAnISR( void )
+ *	{
+ *		BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
+ *
+ *		// Query the hardware to determine which interface needs processing.
+ *		xInterfaceToService = prvCheckInterfaces();
+ *
+ *      // The actual processing is to be deferred to a task.  Request the
+ *      // vProcessInterface() callback function is executed, passing in the
+ *		// number of the interface that needs processing.  The interface to
+ *		// service is passed in the second parameter.  The first parameter is
+ *		// not used in this case.
+ *		xHigherPriorityTaskWoken = pdFALSE;
+ *		xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
+ *
+ *		// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *		// switch should be requested.  The macro used is port specific and will
+ *		// be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
+ *		// the documentation page for the port being used.
+ *		portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *
+ *	}
+ * @endverbatim
+ */
+BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+ /**
+  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+  *                                    void *pvParameter1,
+  *                                    uint32_t ulParameter2,
+  *                                    TickType_t xTicksToWait );
+  *
+  *
+  * Used to defer the execution of a function to the RTOS daemon task (the timer
+  * service task, hence this function is implemented in timers.c and is prefixed
+  * with 'Timer').
+  *
+  * @param xFunctionToPend The function to execute from the timer service/
+  * daemon task.  The function must conform to the PendedFunction_t
+  * prototype.
+  *
+  * @param pvParameter1 The value of the callback function's first parameter.
+  * The parameter has a void * type to allow it to be used to pass any type.
+  * For example, unsigned longs can be cast to a void *, or the void * can be
+  * used to point to a structure.
+  *
+  * @param ulParameter2 The value of the callback function's second parameter.
+  *
+  * @param xTicksToWait Calling this function will result in a message being
+  * sent to the timer daemon task on a queue.  xTicksToWait is the amount of
+  * time the calling task should remain in the Blocked state (so not using any
+  * processing time) for space to become available on the timer queue if the
+  * queue is found to be full.
+  *
+  * @return pdPASS is returned if the message was successfully sent to the
+  * timer daemon task, otherwise pdFALSE is returned.
+  *
+  */
+BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * const char * const pcTimerGetName( TimerHandle_t xTimer );
+ *
+ * Returns the name that was assigned to a timer when the timer was created.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The name assigned to the timer specified by the xTimer parameter.
+ */
+const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
+ *
+ * Returns the period of a timer.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The period of the timer in ticks.
+ */
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+* TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );
+*
+* Returns the time in ticks at which the timer will expire.  If this is less
+* than the current tick count then the expiry time has overflowed from the
+* current time.
+*
+* @param xTimer The handle of the timer being queried.
+*
+* @return If the timer is running then the time in ticks at which the timer
+* will next expire is returned.  If the timer is not running then the return
+* value is undefined.
+*/
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Functions beyond this part are not part of the public API and are intended
+ * for use by the kernel only.
+ */
+BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* TIMERS_H */
+
+
+
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/list.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/list.c
new file mode 100644
index 00000000..758523a3
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/list.c
@@ -0,0 +1,198 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#include 
+#include "FreeRTOS.h"
+#include "list.h"
+
+/*-----------------------------------------------------------
+ * PUBLIC LIST API documented in list.h
+ *----------------------------------------------------------*/
+
+void vListInitialise( List_t * const pxList )
+{
+	/* The list structure contains a list item which is used to mark the
+	end of the list.  To initialise the list the list end is inserted
+	as the only list entry. */
+	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	/* The list end value is the highest possible value in the list to
+	ensure it remains at the end of the list. */
+	pxList->xListEnd.xItemValue = portMAX_DELAY;
+
+	/* The list end next and previous pointers point to itself so we know
+	when the list is empty. */
+	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+
+	/* Write known values into the list if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
+	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+}
+/*-----------------------------------------------------------*/
+
+void vListInitialiseItem( ListItem_t * const pxItem )
+{
+	/* Make sure the list item is not recorded as being on a list. */
+	pxItem->pvContainer = NULL;
+
+	/* Write known values into the list item if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+}
+/*-----------------------------------------------------------*/
+
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t * const pxIndex = pxList->pxIndex;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert a new list item into pxList, but rather than sort the list,
+	makes the new list item the last item to be removed by a call to
+	listGET_OWNER_OF_NEXT_ENTRY(). */
+	pxNewListItem->pxNext = pxIndex;
+	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	pxIndex->pxPrevious->pxNext = pxNewListItem;
+	pxIndex->pxPrevious = pxNewListItem;
+
+	/* Remember which list the item is in. */
+	pxNewListItem->pvContainer = ( void * ) pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t *pxIterator;
+const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert the new list item into the list, sorted in xItemValue order.
+
+	If the list already contains a list item with the same item value then the
+	new list item should be placed after it.  This ensures that TCB's which are
+	stored in ready lists (all of which have the same xItemValue value) get a
+	share of the CPU.  However, if the xItemValue is the same as the back marker
+	the iteration loop below will not end.  Therefore the value is checked
+	first, and the algorithm slightly modified if necessary. */
+	if( xValueOfInsertion == portMAX_DELAY )
+	{
+		pxIterator = pxList->xListEnd.pxPrevious;
+	}
+	else
+	{
+		/* *** NOTE ***********************************************************
+		If you find your application is crashing here then likely causes are
+		listed below.  In addition see http://www.freertos.org/FAQHelp.html for
+		more tips, and ensure configASSERT() is defined!
+		http://www.freertos.org/a00110.html#configASSERT
+
+			1) Stack overflow -
+			   see http://www.freertos.org/Stacks-and-stack-overflow-checking.html
+			2) Incorrect interrupt priority assignment, especially on Cortex-M
+			   parts where numerically high priority values denote low actual
+			   interrupt priorities, which can seem counter intuitive.  See
+			   http://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
+			   of configMAX_SYSCALL_INTERRUPT_PRIORITY on
+			   http://www.freertos.org/a00110.html
+			3) Calling an API function from within a critical section or when
+			   the scheduler is suspended, or calling an API function that does
+			   not end in "FromISR" from an interrupt.
+			4) Using a queue or semaphore before it has been initialised or
+			   before the scheduler has been started (are interrupts firing
+			   before vTaskStartScheduler() has been called?).
+		**********************************************************************/
+
+		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+		{
+			/* There is nothing to do here, just iterating to the wanted
+			insertion position. */
+		}
+	}
+
+	pxNewListItem->pxNext = pxIterator->pxNext;
+	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
+	pxNewListItem->pxPrevious = pxIterator;
+	pxIterator->pxNext = pxNewListItem;
+
+	/* Remember which list the item is in.  This allows fast removal of the
+	item later. */
+	pxNewListItem->pvContainer = ( void * ) pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
+{
+/* The list item knows which list it is in.  Obtain the list from the list
+item. */
+List_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer;
+
+	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
+	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	/* Make sure the index is left pointing to a valid item. */
+	if( pxList->pxIndex == pxItemToRemove )
+	{
+		pxList->pxIndex = pxItemToRemove->pxPrevious;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxItemToRemove->pvContainer = NULL;
+	( pxList->uxNumberOfItems )--;
+
+	return pxList->uxNumberOfItems;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/portable/MemMang/heap_4.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/portable/MemMang/heap_4.c
new file mode 100644
index 00000000..02251c09
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/portable/MemMang/heap_4.c
@@ -0,0 +1,436 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * A sample implementation of pvPortMalloc() and vPortFree() that combines
+ * (coalescences) adjacent memory blocks as they are freed, and in so doing
+ * limits memory fragmentation.
+ *
+ * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* Block sizes must not get too small. */
+#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE		( ( size_t ) 8 )
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#else
+	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/* Define the linked list structure.  This is used to link free blocks in order
+of their memory address. */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
+	size_t xBlockSize;						/*<< The size of the free block. */
+} BlockLink_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Inserts a block of memory that is being freed into the correct position in
+ * the list of free memory blocks.  The block being freed will be merged with
+ * the block in front it and/or the block behind it if the memory blocks are
+ * adjacent to each other.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+
+/*
+ * Called automatically to setup the required heap structures the first time
+ * pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/*-----------------------------------------------------------*/
+
+/* The size of the structure placed at the beginning of each allocated memory
+block must by correctly byte aligned. */
+static const size_t xHeapStructSize	= ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/* Keeps track of the number of free bytes remaining, but says nothing about
+fragmentation. */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
+member of an BlockLink_t structure is set then the block belongs to the
+application.  When the bit is free the block is still part of the free heap
+space. */
+static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	vTaskSuspendAll();
+	{
+		/* If this is the first call to malloc then the heap will require
+		initialisation to setup the list of free blocks. */
+		if( pxEnd == NULL )
+		{
+			prvHeapInit();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Check the requested block size is not so large that the top bit is
+		set.  The top bit of the block size member of the BlockLink_t structure
+		is used to determine who owns the block - the application or the
+		kernel, so it must be free. */
+		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+		{
+			/* The wanted size is increased so it can contain a BlockLink_t
+			structure in addition to the requested amount of bytes. */
+			if( xWantedSize > 0 )
+			{
+				xWantedSize += xHeapStructSize;
+
+				/* Ensure that blocks are always aligned to the required number
+				of bytes. */
+				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+				{
+					/* Byte alignment required. */
+					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+			{
+				/* Traverse the list from the start	(lowest address) block until
+				one	of adequate size is found. */
+				pxPreviousBlock = &xStart;
+				pxBlock = xStart.pxNextFreeBlock;
+				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+				{
+					pxPreviousBlock = pxBlock;
+					pxBlock = pxBlock->pxNextFreeBlock;
+				}
+
+				/* If the end marker was reached then a block of adequate size
+				was	not found. */
+				if( pxBlock != pxEnd )
+				{
+					/* Return the memory space pointed to - jumping over the
+					BlockLink_t structure at its start. */
+					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+					/* This block is being returned for use so must be taken out
+					of the list of free blocks. */
+					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+					/* If the block is larger than required it can be split into
+					two. */
+					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+					{
+						/* This block is to be split into two.  Create a new
+						block following the number of bytes requested. The void
+						cast is used to prevent byte alignment warnings from the
+						compiler. */
+						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+
+						/* Calculate the sizes of two blocks split from the
+						single block. */
+						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+						pxBlock->xBlockSize = xWantedSize;
+
+						/* Insert the new block into the list of free blocks. */
+						prvInsertBlockIntoFreeList( pxNewBlockLink );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+					{
+						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The block is being returned - it is allocated and owned
+					by the application and has no "next" block. */
+					pxBlock->xBlockSize |= xBlockAllocatedBit;
+					pxBlock->pxNextFreeBlock = NULL;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				vTaskSuspendAll();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( portBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	before and the block after, then it's pxNextFreeBlock pointer will have
+	already been set, and should not be set here as that would make it point
+	to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c
new file mode 100644
index 00000000..fab5a4d8
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c
@@ -0,0 +1,698 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM3 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef configKERNEL_INTERRUPT_PRIORITY
+	#define configKERNEL_INTERRUPT_PRIORITY 255
+#endif
+
+#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
+	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* The __weak attribute does not work as you might expect with the Keil tools
+so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if
+the application writer wants to provide their own implementation of
+vPortSetupTimerInterrupt().  Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
+is defined. */
+#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
+	#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR			( 0x01000000 )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvStartFirstTask( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
+
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+__asm void vPortSVCHandler( void )
+{
+	PRESERVE8
+
+	ldr	r3, =pxCurrentTCB	/* Restore the context. */
+	ldr r1, [r3]			/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+	ldr r0, [r1]			/* The first item in pxCurrentTCB is the task top of stack. */
+	ldmia r0!, {r4-r11}		/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+	msr psp, r0				/* Restore the task stack pointer. */
+	isb
+	mov r0, #0
+	msr	basepri, r0
+	orr r14, #0xd
+	bx r14
+}
+/*-----------------------------------------------------------*/
+
+__asm void prvStartFirstTask( void )
+{
+	PRESERVE8
+
+	/* Use the NVIC offset register to locate the stack. */
+	ldr r0, =0xE000ED08
+	ldr r0, [r0]
+	ldr r0, [r0]
+
+	/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	/* Globally enable interrupts. */
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	/* Call SVC to start the first task. */
+	svc 0
+	nop
+	nop
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* The kernel interrupt priority should be set to the lowest
+		priority. */
+		configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Start the first task. */
+	prvStartFirstTask();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+__asm void xPortPendSVHandler( void )
+{
+	extern uxCriticalNesting;
+	extern pxCurrentTCB;
+	extern vTaskSwitchContext;
+
+	PRESERVE8
+
+	mrs r0, psp
+	isb
+
+	ldr	r3, =pxCurrentTCB		/* Get the location of the current TCB. */
+	ldr	r2, [r3]
+
+	stmdb r0!, {r4-r11}			/* Save the remaining registers. */
+	str r0, [r2]				/* Save the new top of stack into the first member of the TCB. */
+
+	stmdb sp!, {r3, r14}
+	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	msr basepri, r0
+	dsb
+	isb
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r3, r14}
+
+	ldr r1, [r3]
+	ldr r0, [r1]				/* The first item in pxCurrentTCB is the task top of stack. */
+	ldmia r0!, {r4-r11}			/* Pop the registers and the critical nesting count. */
+	msr psp, r0
+	isb
+	bx r14
+	nop
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known - therefore the slightly faster vPortRaiseBASEPRI() function is used
+	in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
+	vPortRaiseBASEPRI();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	vPortClearBASEPRIFromISR();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+	__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__disable_irq();
+		__dsb( portSY_FULL_READ_WRITE );
+		__isb( portSY_FULL_READ_WRITE );
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above __disable_irq() call
+			above. */
+			__enable_irq();
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( &xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__dsb( portSY_FULL_READ_WRITE );
+				__wfi();
+				__isb( portSY_FULL_READ_WRITE );
+			}
+			configPOST_SLEEP_PROCESSING( &xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__enable_irq();
+			__dsb( portSY_FULL_READ_WRITE );
+			__isb( portSY_FULL_READ_WRITE );
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__disable_irq();
+			__dsb( portSY_FULL_READ_WRITE );
+			__isb( portSY_FULL_READ_WRITE );
+			
+			/* Disable the SysTick clock without reading the 
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again, 
+			the time the SysTick is stopped for is accounted for as best it can 
+			be, but using the tickless mode will inevitably result in some tiny 
+			drift of the time maintained by the kernel with respect to calendar 
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrpts enabled. */
+			__enable_irq();
+		}
+	}
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the SysTick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+#if( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
+
+	void vPortSetupTimerInterrupt( void )
+	{
+		/* Calculate the constants required to configure the tick interrupt. */
+		#if( configUSE_TICKLESS_IDLE == 1 )
+		{
+			ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+			xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+			ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+		}
+		#endif /* configUSE_TICKLESS_IDLE */
+
+		/* Stop and clear the SysTick. */
+		portNVIC_SYSTICK_CTRL_REG = 0UL;
+		portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+		/* Configure SysTick to interrupt at the requested rate. */
+		portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+		portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+	}
+
+#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
+/*-----------------------------------------------------------*/
+
+__asm uint32_t vPortGetIPSR( void )
+{
+	PRESERVE8
+
+	mrs r0, ipsr
+	bx r14
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		ulCurrentInterrupt = vPortGetIPSR();
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h
new file mode 100644
index 00000000..a2bf018f
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h
@@ -0,0 +1,252 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+
+/* Constants used with memory barrier intrinsics. */
+#define portSY_FULL_READ_WRITE		( 15 )
+
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD()																\
+{																				\
+	/* Set a PendSV to request a context switch. */								\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
+																				\
+	/* Barriers are normally not required but do ensure the code is completely	\
+	within the specified behaviour for the architecture. */						\
+	__dsb( portSY_FULL_READ_WRITE );											\
+	__isb( portSY_FULL_READ_WRITE );											\
+}
+/*-----------------------------------------------------------*/
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()					vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
+
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/* Port specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
+
+#endif /* taskRECORD_READY_PRIORITY */
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE __inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE __forceinline
+#endif
+
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+{
+	__asm
+	{
+		/* Barrier instructions are not used as this function is only used to
+		lower the BASEPRI value. */
+		msr basepri, ulBASEPRI
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+	__asm
+	{
+		/* Set BASEPRI to the max syscall priority to effect a critical
+		section. */
+		msr basepri, ulNewBASEPRI
+		dsb
+		isb
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+{
+	__asm
+	{
+		/* Set BASEPRI to 0 so no interrupts are masked.  This function is only
+		used to lower the mask in an interrupt, so memory barriers are not 
+		used. */
+		msr basepri, #0
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+	__asm
+	{
+		/* Set BASEPRI to the max syscall priority to effect a critical
+		section. */
+		mrs ulReturn, basepri
+		msr basepri, ulNewBASEPRI
+		dsb
+		isb
+	}
+
+	return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	__asm
+	{
+		mrs ulCurrentInterrupt, ipsr
+	}
+
+	if( ulCurrentInterrupt == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/queue.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/queue.c
new file mode 100644
index 00000000..0730950e
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/queue.c
@@ -0,0 +1,2908 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+#if ( configUSE_CO_ROUTINES == 1 )
+	#include "croutine.h"
+#endif
+
+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
+header files above, but not in this file, in order to generate the correct
+privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+
+
+/* Constants used with the cRxLock and cTxLock structure members. */
+#define queueUNLOCKED					( ( int8_t ) -1 )
+#define queueLOCKED_UNMODIFIED			( ( int8_t ) 0 )
+
+/* When the Queue_t structure is used to represent a base queue its pcHead and
+pcTail members are used as pointers into the queue storage area.  When the
+Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
+not necessary, and the pcHead pointer is set to NULL to indicate that the
+pcTail pointer actually points to the mutex holder (if any).  Map alternative
+names to the pcHead and pcTail structure members to ensure the readability of
+the code is maintained despite this dual use of two structure members.  An
+alternative implementation would be to use a union, but use of a union is
+against the coding standard (although an exception to the standard has been
+permitted where the dual use also significantly changes the type of the
+structure member). */
+#define pxMutexHolder					pcTail
+#define uxQueueType						pcHead
+#define queueQUEUE_IS_MUTEX				NULL
+
+/* Semaphores do not actually store or copy data, so have an item size of
+zero. */
+#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )
+#define queueMUTEX_GIVE_BLOCK_TIME		 ( ( TickType_t ) 0U )
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define queueYIELD_IF_USING_PREEMPTION()
+#else
+	#define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/*
+ * Definition of the queue used by the scheduler.
+ * Items are queued by copy, not reference.  See the following link for the
+ * rationale: http://www.freertos.org/Embedded-RTOS-Queues.html
+ */
+typedef struct QueueDefinition
+{
+	int8_t *pcHead;					/*< Points to the beginning of the queue storage area. */
+	int8_t *pcTail;					/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
+	int8_t *pcWriteTo;				/*< Points to the free next place in the storage area. */
+
+	union							/* Use of a union is an exception to the coding standard to ensure two mutually exclusive structure members don't appear simultaneously (wasting RAM). */
+	{
+		int8_t *pcReadFrom;			/*< Points to the last place that a queued item was read from when the structure is used as a queue. */
+		UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+	} u;
+
+	List_t xTasksWaitingToSend;		/*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */
+	List_t xTasksWaitingToReceive;	/*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */
+
+	volatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */
+	UBaseType_t uxLength;			/*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
+	UBaseType_t uxItemSize;			/*< The size of each items that the queue will hold. */
+
+	volatile int8_t cRxLock;		/*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+	volatile int8_t cTxLock;		/*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucStaticallyAllocated;	/*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if ( configUSE_QUEUE_SETS == 1 )
+		struct QueueDefinition *pxQueueSetContainer;
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxQueueNumber;
+		uint8_t ucQueueType;
+	#endif
+
+} xQUEUE;
+
+/* The old xQUEUE name is maintained above then typedefed to the new Queue_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xQUEUE Queue_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The queue registry is just a means for kernel aware debuggers to locate
+ * queue structures.  It has no other purpose so is an optional component.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	/* The type stored within the queue registry array.  This allows a name
+	to be assigned to each queue making kernel aware debugging a little
+	more user friendly. */
+	typedef struct QUEUE_REGISTRY_ITEM
+	{
+		const char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+		QueueHandle_t xHandle;
+	} xQueueRegistryItem;
+
+	/* The old xQueueRegistryItem name is maintained above then typedefed to the
+	new xQueueRegistryItem name below to enable the use of older kernel aware
+	debuggers. */
+	typedef xQueueRegistryItem QueueRegistryItem_t;
+
+	/* The queue registry is simply an array of QueueRegistryItem_t structures.
+	The pcQueueName member of a structure being NULL is indicative of the
+	array position being vacant. */
+	PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+
+/*
+ * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not
+ * prevent an ISR from adding or removing items to the queue, but does prevent
+ * an ISR from removing tasks from the queue event lists.  If an ISR finds a
+ * queue is locked it will instead increment the appropriate queue lock count
+ * to indicate that a task may require unblocking.  When the queue in unlocked
+ * these lock counts are inspected, and the appropriate action taken.
+ */
+static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any data in a queue.
+ *
+ * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
+ */
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any space in a queue.
+ *
+ * @return pdTRUE if there is no space, otherwise pdFALSE;
+ */
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item into the queue, either at the front of the queue or the
+ * back of the queue.
+ */
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item out of a queue.
+ */
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_QUEUE_SETS == 1 )
+	/*
+	 * Checks to see if a queue is a member of a queue set, and if so, notifies
+	 * the queue set that the queue contains data.
+	 */
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Called after a Queue_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Mutexes are a special type of queue.  When a mutex is created, first the
+ * queue is created, then prvInitialiseMutex() is called to configure the queue
+ * as a mutex.
+ */
+#if( configUSE_MUTEXES == 1 )
+	static void prvInitialiseMutex( Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if( configUSE_MUTEXES == 1 )
+	/*
+	 * If a task waiting for a mutex causes the mutex holder to inherit a
+	 * priority, but the waiting task times out, then the holder should
+	 * disinherit the priority - but only down to the highest priority of any
+	 * other tasks that are waiting for the same mutex.  This function returns
+	 * that priority.
+	 */
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to mark a queue as locked.  Locking a queue prevents an ISR from
+ * accessing the queue event lists.
+ */
+#define prvLockQueue( pxQueue )								\
+	taskENTER_CRITICAL();									\
+	{														\
+		if( ( pxQueue )->cRxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+		if( ( pxQueue )->cTxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+	}														\
+	taskEXIT_CRITICAL()
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
+{
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		pxQueue->pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize );
+		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
+		pxQueue->pcWriteTo = pxQueue->pcHead;
+		pxQueue->u.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - ( UBaseType_t ) 1U ) * pxQueue->uxItemSize );
+		pxQueue->cRxLock = queueUNLOCKED;
+		pxQueue->cTxLock = queueUNLOCKED;
+
+		if( xNewQueue == pdFALSE )
+		{
+			/* If there are tasks blocked waiting to read from the queue, then
+			the tasks will remain blocked as after this function exits the queue
+			will still be empty.  If there are tasks blocked waiting to write to
+			the queue, then one should be unblocked as after this function exits
+			it will be possible to write to it. */
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					queueYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* Ensure the event queues start in the correct state. */
+			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
+			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	/* A value is returned for calling semantic consistency with previous
+	versions. */
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		/* The StaticQueue_t structure and the queue storage area must be
+		supplied. */
+		configASSERT( pxStaticQueue != NULL );
+
+		/* A queue storage area should be provided if the item size is not 0, and
+		should not be provided if the item size is 0. */
+		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
+		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
+			the real queue and semaphore structures. */
+			volatile size_t xSize = sizeof( StaticQueue_t );
+			configASSERT( xSize == sizeof( Queue_t ) );
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* The address of a statically allocated queue was passed in, use it.
+		The address of a statically allocated storage area was also passed in
+		but is already set. */
+		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+
+		if( pxNewQueue != NULL )
+		{
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Queues can be allocated wither statically or dynamically, so
+				note this queue was allocated statically in case the queue is
+				later deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdTRUE;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+	size_t xQueueSizeInBytes;
+	uint8_t *pucQueueStorage;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		if( uxItemSize == ( UBaseType_t ) 0 )
+		{
+			/* There is not going to be a queue storage area. */
+			xQueueSizeInBytes = ( size_t ) 0;
+		}
+		else
+		{
+			/* Allocate enough space to hold the maximum number of items that
+			can be in the queue at any time. */
+			xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+		}
+
+		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes );
+
+		if( pxNewQueue != NULL )
+		{
+			/* Jump past the queue structure to find the location of the queue
+			storage area. */
+			pucQueueStorage = ( ( uint8_t * ) pxNewQueue ) + sizeof( Queue_t );
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Queues can be created either statically or dynamically, so
+				note this task was created dynamically in case it is later
+				deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdFALSE;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
+{
+	/* Remove compiler warnings about unused parameters should
+	configUSE_TRACE_FACILITY not be set to 1. */
+	( void ) ucQueueType;
+
+	if( uxItemSize == ( UBaseType_t ) 0 )
+	{
+		/* No RAM was allocated for the queue storage area, but PC head cannot
+		be set to NULL because NULL is used as a key to say the queue is used as
+		a mutex.  Therefore just set pcHead to point to the queue as a benign
+		value that is known to be within the memory map. */
+		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
+	}
+	else
+	{
+		/* Set the head to the start of the queue storage area. */
+		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
+	}
+
+	/* Initialise the queue members as described where the queue type is
+	defined. */
+	pxNewQueue->uxLength = uxQueueLength;
+	pxNewQueue->uxItemSize = uxItemSize;
+	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+	{
+		pxNewQueue->ucQueueType = ucQueueType;
+	}
+	#endif /* configUSE_TRACE_FACILITY */
+
+	#if( configUSE_QUEUE_SETS == 1 )
+	{
+		pxNewQueue->pxQueueSetContainer = NULL;
+	}
+	#endif /* configUSE_QUEUE_SETS */
+
+	traceQUEUE_CREATE( pxNewQueue );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static void prvInitialiseMutex( Queue_t *pxNewQueue )
+	{
+		if( pxNewQueue != NULL )
+		{
+			/* The queue create function will set all the queue structure members
+			correctly for a generic queue, but this function is creating a
+			mutex.  Overwrite those members that need to be set differently -
+			in particular the information required for priority inheritance. */
+			pxNewQueue->pxMutexHolder = NULL;
+			pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
+
+			/* In case this is a recursive mutex. */
+			pxNewQueue->u.uxRecursiveCallCount = 0;
+
+			traceCREATE_MUTEX( pxNewQueue );
+
+			/* Start with the semaphore in the expected state. */
+			( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
+		}
+		else
+		{
+			traceCREATE_MUTEX_FAILED();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		pxNewQueue = ( Queue_t * ) xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
+		prvInitialiseMutex( pxNewQueue );
+
+		return pxNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
+	{
+	Queue_t *pxNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		/* Prevent compiler warnings about unused parameters if
+		configUSE_TRACE_FACILITY does not equal 1. */
+		( void ) ucQueueType;
+
+		pxNewQueue = ( Queue_t * ) xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
+		prvInitialiseMutex( pxNewQueue );
+
+		return pxNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	void* xQueueGetMutexHolder( QueueHandle_t xSemaphore )
+	{
+	void *pxReturn;
+
+		/* This function is called by xSemaphoreGetMutexHolder(), and should not
+		be called directly.  Note:  This is a good way of determining if the
+		calling task is the mutex holder, but not a good way of determining the
+		identity of the mutex holder, as the holder may change between the
+		following critical section exiting and the function returning. */
+		taskENTER_CRITICAL();
+		{
+			if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				pxReturn = ( void * ) ( ( Queue_t * ) xSemaphore )->pxMutexHolder;
+			}
+			else
+			{
+				pxReturn = NULL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	void* xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
+	{
+	void *pxReturn;
+
+		configASSERT( xSemaphore );
+
+		/* Mutexes cannot be used in interrupt service routines, so the mutex
+		holder should not change in an ISR, and therefore a critical section is
+		not required here. */
+		if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+		{
+			pxReturn = ( void * ) ( ( Queue_t * ) xSemaphore )->pxMutexHolder;
+		}
+		else
+		{
+			pxReturn = NULL;
+		}
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* If this is the task that holds the mutex then pxMutexHolder will not
+		change outside of this task.  If this task does not hold the mutex then
+		pxMutexHolder can never coincidentally equal the tasks handle, and as
+		this is the only condition we are interested in it does not matter if
+		pxMutexHolder is accessed simultaneously by another task.  Therefore no
+		mutual exclusion is required to test the pxMutexHolder variable. */
+		if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Not a redundant cast as TaskHandle_t is a typedef. */
+		{
+			traceGIVE_MUTEX_RECURSIVE( pxMutex );
+
+			/* uxRecursiveCallCount cannot be zero if pxMutexHolder is equal to
+			the task handle, therefore no underflow check is required.  Also,
+			uxRecursiveCallCount is only modified by the mutex holder, and as
+			there can only be one, no mutual exclusion is required to modify the
+			uxRecursiveCallCount member. */
+			( pxMutex->u.uxRecursiveCallCount )--;
+
+			/* Has the recursive call count unwound to 0? */
+			if( pxMutex->u.uxRecursiveCallCount == ( UBaseType_t ) 0 )
+			{
+				/* Return the mutex.  This will automatically unblock any other
+				task that might be waiting to access the mutex. */
+				( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			/* The mutex cannot be given because the calling task is not the
+			holder. */
+			xReturn = pdFAIL;
+
+			traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* Comments regarding mutual exclusion as per those within
+		xQueueGiveMutexRecursive(). */
+
+		traceTAKE_MUTEX_RECURSIVE( pxMutex );
+
+		if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */
+		{
+			( pxMutex->u.uxRecursiveCallCount )++;
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
+
+			/* pdPASS will only be returned if the mutex was successfully
+			obtained.  The calling task may have entered the Blocked state
+			before reaching here. */
+			if( xReturn != pdFAIL )
+			{
+				( pxMutex->u.uxRecursiveCallCount )++;
+			}
+			else
+			{
+				traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
+{
+BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/* This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Is there room on the queue now?  The running task must be the
+			highest priority task wanting to access the queue.  If the head item
+			in the queue is to be overwritten then it does not matter if the
+			queue is full. */
+			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+			{
+				traceQUEUE_SEND( pxQueue );
+				xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock. A context switch is required. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* If there was a task waiting for data to arrive on the
+						queue then unblock it now. */
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The unblocked task has a priority higher than
+								our own so yield immediately.  Yes it is ok to
+								do this from within the critical section - the
+								kernel takes care of that. */
+								queueYIELD_IF_USING_PREEMPTION();
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else if( xYieldRequired != pdFALSE )
+						{
+							/* This path is a special case that will only get
+							executed if the task was holding multiple mutexes
+							and the mutexes were given back in an order that is
+							different to that in which they were taken. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					/* If there was a task waiting for data to arrive on the
+					queue then unblock it now. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The unblocked task has a priority higher than
+							our own so yield immediately.  Yes it is ok to do
+							this from within the critical section - the kernel
+							takes care of that. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else if( xYieldRequired != pdFALSE )
+					{
+						/* This path is a special case that will only get
+						executed if the task was holding multiple mutexes and
+						the mutexes were given back in an order that is
+						different to that in which they were taken. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was full and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+
+					/* Return to the original privilege level before exiting
+					the function. */
+					traceQUEUE_SEND_FAILED( pxQueue );
+					return errQUEUE_FULL;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was full and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
+
+				/* Unlocking the queue means queue events can effect the
+				event list.  It is possible that interrupts occurring now
+				remove this task from the event list again - but as the
+				scheduler is suspended the task will go onto the pending
+				ready last instead of the actual ready list. */
+				prvUnlockQueue( pxQueue );
+
+				/* Resuming the scheduler will move tasks from the pending
+				ready list into the ready list - so it is feasible that this
+				task is already in a ready list before it yields - in which
+				case the yield will not cause a context switch unless there
+				is also a higher priority task in the pending ready list. */
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+			}
+			else
+			{
+				/* Try again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			traceQUEUE_SEND_FAILED( pxQueue );
+			return errQUEUE_FULL;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	/* Similar to xQueueGenericSend, except without blocking if there is no room
+	in the queue.  Also don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
+			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
+			in a task disinheriting a priority and prvCopyDataToQueue() can be
+			called here even though the disinherit function does not check if
+			the scheduler is suspended before accessing the ready lists. */
+			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	/* Similar to xQueueGenericSendFromISR() but used with semaphores where the
+	item size is 0.  Don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+
+	configASSERT( pxQueue );
+
+	/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
+	if the item size is not 0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Normally a mutex would not be given from an interrupt, especially if
+	there is a mutex holder, as priority inheritance makes no sense for an
+	interrupts, only tasks. */
+	configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->pxMutexHolder != NULL ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* When the queue is used to implement a semaphore no data is ever
+		moved through the queue but it is still valid to see if the queue 'has
+		space'. */
+		if( uxMessagesWaiting < pxQueue->uxLength )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* A task can only have an inherited priority if it is a mutex
+			holder - and if there is a mutex holder then the mutex cannot be
+			given from an ISR.  As this is the ISR version of the function it
+			can be assumed there is no mutex holder and no need to determine if
+			priority disinheritance is needed.  Simply increase the count of
+			messages (semaphores) available. */
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE )
+						{
+							/* The semaphore is a member of a queue set, and
+							posting	to the queue set caused a higher priority
+							task to	unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+	/* This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data available, remove one item. */
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_RECEIVE( pxQueue );
+				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+				/* There is now space in the queue, were any tasks waiting to
+				post to the queue?  If so, unblock the highest priority waiting
+				task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* The timeout has not expired.  If the queue is still empty place
+			the task on the list of tasks waiting to receive from the queue. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The queue contains data again.  Loop back to try and read the
+				data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out.  If there is no data in the queue exit, otherwise loop
+			back and attempt to read the data. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+#if( configUSE_MUTEXES == 1 )
+	BaseType_t xInheritanceOccurred = pdFALSE;
+#endif
+
+	/* Check the queue pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* Check this really is a semaphore, in which case the item size will be
+	0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/* This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Semaphores are queues with an item size of 0, and where the
+			number of messages in the queue is the semaphore's count value. */
+			const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxSemaphoreCount > ( UBaseType_t ) 0 )
+			{
+				traceQUEUE_RECEIVE( pxQueue );
+
+				/* Semaphores are queues with a data size of zero and where the
+				messages waiting is the semaphore's count.  Reduce the count. */
+				pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						/* Record the information required to implement
+						priority inheritance should it become necessary. */
+						pxQueue->pxMutexHolder = ( int8_t * ) pvTaskIncrementMutexHeldCount(); /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				/* Check to see if other tasks are blocked waiting to give the
+				semaphore, and if so, unblock the highest priority such task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* For inheritance to have occurred there must have been an
+					initial timeout, and an adjusted timeout cannot become 0, as
+					if it were 0 the function would have exited. */
+					#if( configUSE_MUTEXES == 1 )
+					{
+						configASSERT( xInheritanceOccurred == pdFALSE );
+					}
+					#endif /* configUSE_MUTEXES */
+
+					/* The semaphore count was 0 and no block time is specified
+					(or the block time has expired) so exit now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The semaphore count was 0 and a block time was specified
+					so configure the timeout structure ready to block. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can give to and take from the semaphore
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* A block time is specified and not expired.  If the semaphore
+			count is 0 then enter the Blocked state to wait for a semaphore to
+			become available.  As semaphores are implemented with queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						taskENTER_CRITICAL();
+						{
+							xInheritanceOccurred = xTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );
+						}
+						taskEXIT_CRITICAL();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif
+
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There was no timeout and the semaphore count was not 0, so
+				attempt to take the semaphore again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			/* If the semaphore count is 0 exit now as the timeout has
+			expired.  Otherwise return to attempt to take the semaphore that is
+			known to be available.  As semaphores are implemented by queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* xInheritanceOccurred could only have be set if
+					pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
+					test the mutex type again to check it is actually a mutex. */
+					if( xInheritanceOccurred != pdFALSE )
+					{
+						taskENTER_CRITICAL();
+						{
+							UBaseType_t uxHighestWaitingPriority;
+
+							/* This task blocking on the mutex caused another
+							task to inherit this task's priority.  Now this task
+							has timed out the priority should be disinherited
+							again, but only as low as the next highest priority
+							task that is waiting for the same mutex. */
+							uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
+							vTaskPriorityDisinheritAfterTimeout( ( void * ) pxQueue->pxMutexHolder, uxHighestWaitingPriority );
+						}
+						taskEXIT_CRITICAL();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/* This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Remember the read position so it can be reset after the data
+				is read from the queue as this function is only peeking the
+				data, not removing it. */
+				pcOriginalReadPosition = pxQueue->u.pcReadFrom;
+
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_PEEK( pxQueue );
+
+				/* The data is not being removed, so reset the read pointer. */
+				pxQueue->u.pcReadFrom = pcOriginalReadPosition;
+
+				/* The data is being left in the queue, so see if there are
+				any other tasks waiting for the data. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than this task. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_PEEK_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure ready to enter the blocked
+					state. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* Timeout has not expired yet, check to see if there is data in the
+			queue now, and if not enter the Blocked state to wait for data. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_PEEK( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There is data in the queue now, so don't enter the blocked
+				state, instead return to try and obtain the data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired.  If there is still no data in the queue
+			exit, otherwise go back and try to read the data again. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_PEEK_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* Cannot block in an ISR, so check there is data available. */
+		if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			const int8_t cRxLock = pxQueue->cRxLock;
+
+			traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
+
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+			/* If the queue is locked the event list will not be modified.
+			Instead update the lock count so the task that unlocks the queue
+			will know that an ISR has removed data while the queue was
+			locked. */
+			if( cRxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than us so
+						force a context switch. */
+						if( pxHigherPriorityTaskWoken != NULL )
+						{
+							*pxHigherPriorityTaskWoken = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was removed while it was locked. */
+				pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,  void * const pvBuffer )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Cannot block in an ISR, so check there is data available. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			traceQUEUE_PEEK_FROM_ISR( pxQueue );
+
+			/* Remember the read position so it can be reset as nothing is
+			actually being removed from the queue. */
+			pcOriginalReadPosition = pxQueue->u.pcReadFrom;
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->u.pcReadFrom = pcOriginalReadPosition;
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+
+	configASSERT( xQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t *pxQueue;
+
+	pxQueue = ( Queue_t * ) xQueue;
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+
+	configASSERT( xQueue );
+
+	uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+void vQueueDelete( QueueHandle_t xQueue )
+{
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	configASSERT( pxQueue );
+	traceQUEUE_DELETE( pxQueue );
+
+	#if ( configQUEUE_REGISTRY_SIZE > 0 )
+	{
+		vQueueUnregisterQueue( pxQueue );
+	}
+	#endif
+
+	#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+	{
+		/* The queue can only have been allocated dynamically - free it
+		again. */
+		vPortFree( pxQueue );
+	}
+	#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	{
+		/* The queue could have been allocated statically or dynamically, so
+		check before attempting to free the memory. */
+		if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+		{
+			vPortFree( pxQueue );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#else
+	{
+		/* The queue must have been statically allocated, so is not going to be
+		deleted.  Avoid compiler warnings about the unused parameter. */
+		( void ) pxQueue;
+	}
+	#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )
+	{
+		( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->ucQueueType;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
+	{
+	UBaseType_t uxHighestPriorityOfWaitingTasks;
+
+		/* If a task waiting for a mutex causes the mutex holder to inherit a
+		priority, but the waiting task times out, then the holder should
+		disinherit the priority - but only down to the highest priority of any
+		other tasks that are waiting for the same mutex.  For this purpose,
+		return the priority of the highest priority task that is waiting for the
+		mutex. */
+		if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0 )
+		{
+			uxHighestPriorityOfWaitingTasks = configMAX_PRIORITIES - listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+		else
+		{
+			uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
+		}
+
+		return uxHighestPriorityOfWaitingTasks;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
+{
+BaseType_t xReturn = pdFALSE;
+UBaseType_t uxMessagesWaiting;
+
+	/* This function is called from a critical section. */
+
+	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
+	{
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				/* The mutex is no longer being held. */
+				xReturn = xTaskPriorityDisinherit( ( void * ) pxQueue->pxMutexHolder );
+				pxQueue->pxMutexHolder = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_MUTEXES */
+	}
+	else if( xPosition == queueSEND_TO_BACK )
+	{
+		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. */
+		pxQueue->pcWriteTo += pxQueue->uxItemSize;
+		if( pxQueue->pcWriteTo >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->pcWriteTo = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		( void ) memcpy( ( void * ) pxQueue->u.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+		pxQueue->u.pcReadFrom -= pxQueue->uxItemSize;
+		if( pxQueue->u.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->u.pcReadFrom = ( pxQueue->pcTail - pxQueue->uxItemSize );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( xPosition == queueOVERWRITE )
+		{
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* An item is not being added but overwritten, so subtract
+				one from the recorded number of items in the queue so when
+				one is added again below the number of recorded items remains
+				correct. */
+				--uxMessagesWaiting;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
+{
+	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
+	{
+		pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
+		if( pxQueue->u.pcReadFrom >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+		{
+			pxQueue->u.pcReadFrom = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvUnlockQueue( Queue_t * const pxQueue )
+{
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
+
+	/* The lock counts contains the number of extra data items placed or
+	removed from the queue while the queue was locked.  When a queue is
+	locked items can be added or removed, but the event lists cannot be
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cTxLock = pxQueue->cTxLock;
+
+		/* See if data was added to the queue while it was locked. */
+		while( cTxLock > queueLOCKED_UNMODIFIED )
+		{
+			/* Data was posted while the queue was locked.  Are any tasks
+			blocked waiting for data to become available? */
+			#if ( configUSE_QUEUE_SETS == 1 )
+			{
+				if( pxQueue->pxQueueSetContainer != NULL )
+				{
+					if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE )
+					{
+						/* The queue is a member of a queue set, and posting to
+						the queue set caused a higher priority task to unblock.
+						A context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					/* Tasks that are removed from the event list will get
+					added to the pending ready list as the scheduler is still
+					suspended. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							vTaskMissedYield();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						break;
+					}
+				}
+			}
+			#else /* configUSE_QUEUE_SETS */
+			{
+				/* Tasks that are removed from the event list will get added to
+				the pending ready list as the scheduler is still suspended. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority so record that
+						a context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					break;
+				}
+			}
+			#endif /* configUSE_QUEUE_SETS */
+
+			--cTxLock;
+		}
+
+		pxQueue->cTxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+
+	/* Do the same for the Rx lock. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cRxLock = pxQueue->cRxLock;
+
+		while( cRxLock > queueLOCKED_UNMODIFIED )
+		{
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					vTaskMissedYield();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				--cRxLock;
+			}
+			else
+			{
+				break;
+			}
+		}
+
+		pxQueue->cRxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+
+	configASSERT( xQueue );
+	if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( UBaseType_t ) 0 )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+
+	configASSERT( xQueue );
+	if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( ( Queue_t * ) xQueue )->uxLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+		/* If the queue is already full we may have to block.  A critical section
+		is required to prevent an interrupt removing something from the queue
+		between the check to see if the queue is full and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				/* The queue is full - do we want to block or just leave without
+				posting? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is called from a coroutine we cannot block directly, but
+					return indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+			{
+				/* There is room in the queue, copy the data into the queue. */
+				prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for data to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The co-routine waiting has a higher priority so record
+						that a yield might be appropriate. */
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = errQUEUE_FULL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+		/* If the queue is already empty we may have to block.  A critical section
+		is required to prevent an interrupt adding something to the queue
+		between the check to see if the queue is empty and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+			{
+				/* There are no messages in the queue, do we want to block or just
+				leave with nothing? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is a co-routine we cannot block directly, but return
+					indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data is available from the queue. */
+				pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
+				if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )
+				{
+					pxQueue->u.pcReadFrom = pxQueue->pcHead;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+				--( pxQueue->uxMessagesWaiting );
+				( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for space to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )
+	{
+	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+		/* Cannot block within an ISR so if there is no space on the queue then
+		exit without doing anything. */
+		if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+		{
+			prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+
+			/* We only want to wake one co-routine per ISR, so check that a
+			co-routine has not already been woken. */
+			if( xCoRoutinePreviouslyWoken == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						return pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xCoRoutinePreviouslyWoken;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+		/* We cannot block from an ISR, so check there is data available. If
+		not then just leave without doing anything. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			/* Copy the data from the queue. */
+			pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
+			if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )
+			{
+				pxQueue->u.pcReadFrom = pxQueue->pcHead;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			--( pxQueue->uxMessagesWaiting );
+			( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+			if( ( *pxCoRoutineWoken ) == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						*pxCoRoutineWoken = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+
+		/* See if there is an empty space in the registry.  A NULL name denotes
+		a free slot. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].pcQueueName == NULL )
+			{
+				/* Store the information on this queue. */
+				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
+				xQueueRegistry[ ux ].xHandle = xQueue;
+
+				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	const char *pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+	const char *pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+		/* Note there is nothing here to protect against another task adding or
+		removing entries from the registry while it is being searched. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				pcReturn = xQueueRegistry[ ux ].pcQueueName;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return pcReturn;
+	} /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueUnregisterQueue( QueueHandle_t xQueue )
+	{
+	UBaseType_t ux;
+
+		/* See if the handle of the queue being unregistered in actually in the
+		registry. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				/* Set the name to NULL to show that this slot if free again. */
+				xQueueRegistry[ ux ].pcQueueName = NULL;
+
+				/* Set the handle to NULL to ensure the same queue handle cannot
+				appear in the registry twice if it is added, removed, then
+				added again. */
+				xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+	} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements.
+		It can result in vListInsert() being called on a list that can only
+		possibly ever have one item in it, so the list will be fast, but even
+		so it should be called with the scheduler locked and not from a critical
+		section. */
+
+		/* Only do anything if there are no messages in the queue.  This function
+		will not actually cause the task to block, just place it on a blocked
+		list.  It will not block until the scheduler is unlocked - at which
+		time a yield will be performed.  If an item is added to the queue while
+		the queue is locked, and the calling task blocks on the queue, then the
+		calling task will be immediately unblocked when the queue is unlocked. */
+		prvLockQueue( pxQueue );
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
+		{
+			/* There is nothing in the queue, block for the specified period. */
+			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		prvUnlockQueue( pxQueue );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
+	{
+	QueueSetHandle_t pxQueue;
+
+		pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
+
+		return pxQueue;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
+			{
+				/* Cannot add a queue/semaphore to more than one queue set. */
+				xReturn = pdFAIL;
+			}
+			else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
+			{
+				/* Cannot add a queue/semaphore to a queue set if there are already
+				items in the queue/semaphore. */
+				xReturn = pdFAIL;
+			}
+			else
+			{
+				( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
+				xReturn = pdPASS;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
+
+		if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
+		{
+			/* The queue was not a member of the set. */
+			xReturn = pdFAIL;
+		}
+		else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
+		{
+			/* It is dangerous to remove a queue from a set when the queue is
+			not empty because the queue set will still hold pending events for
+			the queue. */
+			xReturn = pdFAIL;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				/* The queue is no longer contained in the set. */
+				pxQueueOrSemaphore->pxQueueSetContainer = NULL;
+			}
+			taskEXIT_CRITICAL();
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	} /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition )
+	{
+	Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;
+	BaseType_t xReturn = pdFALSE;
+
+		/* This function must be called form a critical section. */
+
+		configASSERT( pxQueueSetContainer );
+		configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );
+
+		if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
+		{
+			const int8_t cTxLock = pxQueueSetContainer->cTxLock;
+
+			traceQUEUE_SEND( pxQueueSetContainer );
+
+			/* The data copied is the handle of the queue that contains data. */
+			xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, xCopyPosition );
+
+			if( cTxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority. */
+						xReturn = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/stream_buffer.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/stream_buffer.c
new file mode 100644
index 00000000..c60045f6
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/stream_buffer.c
@@ -0,0 +1,1199 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "stream_buffer.h"
+
+#if( configUSE_TASK_NOTIFICATIONS != 1 )
+	#error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
+#endif
+
+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
+header files above, but not in this file, in order to generate the correct
+privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+
+/* If the user has not provided application specific Rx notification macros,
+or #defined the notification macros away, them provide default implementations
+that uses task notifications. */
+/*lint -save -e9026 Function like macros allowed and needed here so they can be overidden. */
+#ifndef sbRECEIVE_COMPLETED
+	#define sbRECEIVE_COMPLETED( pxStreamBuffer )										\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend,			\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbRECEIVE_COMPLETED */
+
+#ifndef sbRECEIVE_COMPLETED_FROM_ISR
+	#define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,								\
+										  pxHigherPriorityTaskWoken )					\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
+
+/* If the user has not provided an application specific Tx notification macro,
+or #defined the notification macro away, them provide a default implementation
+that uses task notifications. */
+#ifndef sbSEND_COMPLETED
+	#define sbSEND_COMPLETED( pxStreamBuffer )											\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive,		\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbSEND_COMPLETED */
+
+#ifndef sbSEND_COMPLETE_FROM_ISR
+	#define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )		\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbSEND_COMPLETE_FROM_ISR */
+/*lint -restore (9026) */
+
+/* The number of bytes used to hold the length of a message in the buffer. */
+#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( size_t ) )
+
+/* Bits stored in the ucFlags field of the stream buffer. */
+#define sbFLAGS_IS_MESSAGE_BUFFER		( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
+#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
+
+/*-----------------------------------------------------------*/
+
+/* Structure that hold state information on the buffer. */
+typedef struct xSTREAM_BUFFER /*lint !e9058 Style convention uses tag. */
+{
+	volatile size_t xTail;				/* Index to the next item to read within the buffer. */
+	volatile size_t xHead;				/* Index to the next item to write within the buffer. */
+	size_t xLength;						/* The length of the buffer pointed to by pucBuffer. */
+	size_t xTriggerLevelBytes;			/* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */
+	volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */
+	volatile TaskHandle_t xTaskWaitingToSend;	/* Holds the handle of a task waiting to send data to a message buffer that is full. */
+	uint8_t *pucBuffer;					/* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */
+	uint8_t ucFlags;
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxStreamBufferNumber;		/* Used for tracing purposes. */
+	#endif
+} StreamBuffer_t;
+
+/*
+ * The number of bytes available to be read from the buffer.
+ */
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Add xCount bytes from pucData into the pxStreamBuffer message buffer.
+ * Returns the number of bytes written, which will either equal xCount in the
+ * success case, or 0 if there was not enough space in the buffer (in which case
+ * no data is written into the buffer).
+ */
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then reads an entire
+ * message out of the buffer.  If the stream buffer is being used as a stream
+ * buffer then read as many bytes as possible from the buffer.
+ * prvReadBytesFromBuffer() is called to actually extract the bytes from the
+ * buffer's data storage area.
+ */
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then writes an entire
+ * message to the buffer.  If the stream buffer is being used as a stream
+ * buffer then write as many bytes as possible to the buffer.
+ * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's
+ * data storage area.
+ */
+static size_t prvWriteMessageToBuffer(  StreamBuffer_t * const pxStreamBuffer,
+										const void * pvTxData,
+										size_t xDataLengthBytes,
+										size_t xSpace,
+										size_t xRequiredSpace ) PRIVILEGED_FUNCTION;
+
+/*
+ * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them
+ * to pucData.
+ */
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer,
+									  uint8_t *pucData,
+									  size_t xMaxCount,
+									  size_t xBytesAvailable ); PRIVILEGED_FUNCTION
+
+/*
+ * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
+ * initialise the members of the newly created stream buffer structure.
+ */
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )
+	{
+	uint8_t *pucAllocatedMemory;
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1; /*lint !e9044 Parameter modified to ensure it doesn't have a dangerous value. */
+		}
+
+		/* A stream buffer requires a StreamBuffer_t structure and a buffer.
+		Both are allocated in a single call to pvPortMalloc().  The
+		StreamBuffer_t structure is placed at the start of the allocated memory
+		and the buffer follows immediately after.  The requested size is
+		incremented so the free space is returned as the user would expect -
+		this is a quirk of the implementation that means otherwise the free
+		space would be reported as one byte smaller than would be logically
+		expected. */
+		xBufferSizeBytes++;
+		pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */
+
+		if( pucAllocatedMemory != NULL )
+		{
+			prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */
+										   pucAllocatedMemory + sizeof( StreamBuffer_t ),  /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
+										   xBufferSizeBytes,
+										   xTriggerLevelBytes,
+										   xIsMessageBuffer );
+
+			traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );
+		}
+		else
+		{
+			traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+		}
+
+		return ( StreamBufferHandle_t * ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+														   size_t xTriggerLevelBytes,
+														   BaseType_t xIsMessageBuffer,
+														   uint8_t * const pucStreamBufferStorageArea,
+														   StaticStreamBuffer_t * const pxStaticStreamBuffer )
+	{
+	StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
+	StreamBufferHandle_t xReturn;
+
+		configASSERT( pucStreamBufferStorageArea );
+		configASSERT( pxStaticStreamBuffer );
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1; /*lint !e9044 Function parameter deliberately modified to ensure it is in range. */
+		}
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticStreamBuffer_t equals the size of the real
+			message buffer structure. */
+			volatile size_t xSize = sizeof( StaticStreamBuffer_t );
+			configASSERT( xSize == sizeof( StreamBuffer_t ) );
+		}
+		#endif /* configASSERT_DEFINED */
+
+		if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
+		{
+			prvInitialiseNewStreamBuffer( pxStreamBuffer,
+										  pucStreamBufferStorageArea,
+										  xBufferSizeBytes,
+										  xTriggerLevelBytes,
+										  xIsMessageBuffer );
+
+			/* Remember this was statically allocated in case it is ever deleted
+			again. */
+			pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;
+
+			traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
+
+			xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */
+		}
+		else
+		{
+			xReturn = NULL;
+			traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+
+	configASSERT( pxStreamBuffer );
+
+	traceSTREAM_BUFFER_DELETE( xStreamBuffer );
+
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )
+	{
+		#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+		{
+			/* Both the structure and the buffer were allocated using a single call
+			to pvPortMalloc(), hence only one call to vPortFree() is required. */
+			vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
+		}
+		#else
+		{
+			/* Should not be possible to get here, ucFlags must be corrupt.
+			Force an assert. */
+			configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
+		}
+		#endif
+	}
+	else
+	{
+		/* The structure and buffer were not allocated dynamically and cannot be
+		freed - just scrub the structure so future use will assert. */
+		memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+BaseType_t xReturn = pdFAIL, xIsMessageBuffer;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	UBaseType_t uxStreamBufferNumber;
+#endif
+
+	configASSERT( pxStreamBuffer );
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+	{
+		/* Store the stream buffer number so it can be restored after the
+		reset. */
+		uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
+	}
+	#endif
+
+	/* Can only reset a message buffer if there are no tasks blocked on it. */
+	if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
+	{
+		if( pxStreamBuffer->xTaskWaitingToSend == NULL )
+		{
+			if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+			{
+				xIsMessageBuffer = pdTRUE;
+			}
+			else
+			{
+				xIsMessageBuffer = pdFALSE;
+			}
+
+			prvInitialiseNewStreamBuffer( pxStreamBuffer,
+										  pxStreamBuffer->pucBuffer,
+										  pxStreamBuffer->xLength,
+										  pxStreamBuffer->xTriggerLevelBytes,
+										  xIsMessageBuffer );
+			xReturn = pdPASS;
+
+			#if( configUSE_TRACE_FACILITY == 1 )
+			{
+				pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+			}
+			#endif
+
+			traceSTREAM_BUFFER_RESET( xStreamBuffer );
+		}
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )
+{
+StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+BaseType_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* It is not valid for the trigger level to be 0. */
+	if( xTriggerLevel == ( size_t ) 0 )
+	{
+		xTriggerLevel = ( size_t ) 1; /*lint !e9044 Parameter modified to ensure it doesn't have a dangerous value. */
+	}
+
+	/* The trigger level is the number of bytes that must be in the stream
+	buffer before a task that is waiting for data is unblocked. */
+	if( xTriggerLevel <= pxStreamBuffer->xLength )
+	{
+		pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;
+		xReturn = pdPASS;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+size_t xSpace;
+
+	configASSERT( pxStreamBuffer );
+
+	xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
+	xSpace -= pxStreamBuffer->xHead;
+	xSpace -= ( size_t ) 1;
+
+	if( xSpace >= pxStreamBuffer->xLength )
+	{
+		xSpace -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xSpace;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+size_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	xReturn = prvBytesInBuffer( pxStreamBuffer );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+size_t xReturn, xSpace = 0;
+size_t xRequiredSpace = xDataLengthBytes;
+TimeOut_t xTimeOut;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		vTaskSetTimeOutState( &xTimeOut );
+
+		do
+		{
+			/* Wait until the required number of bytes are free in the message
+			buffer. */
+			taskENTER_CRITICAL();
+			{
+				xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+
+				if( xSpace < xRequiredSpace )
+				{
+					/* Clear notification state as going to wait for space. */
+					( void ) xTaskNotifyStateClear( NULL );
+
+					/* Should only be one writer. */
+					configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
+					pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
+				}
+				else
+				{
+					taskEXIT_CRITICAL();
+					break;
+				}
+			}
+			taskEXIT_CRITICAL();
+
+			traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, UINT32_MAX, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToSend = NULL;
+
+		} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );
+
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+		traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+size_t xReturn, xSpace;
+size_t xRequiredSpace = xDataLengthBytes;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
+									   const void * pvTxData,
+									   size_t xDataLengthBytes,
+									   size_t xSpace,
+									   size_t xRequiredSpace )
+{
+	BaseType_t xShouldWrite;
+	size_t xReturn;
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		/* Doesn't matter if this is a stream buffer or a message buffer, there
+		is no space to write. */
+		xShouldWrite = pdFALSE;
+	}
+	else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )
+	{
+		/* This is a stream buffer, as opposed to a message buffer, so writing a
+		stream of bytes rather than discrete messages.  Write as many bytes as
+		possible. */
+		xShouldWrite = pdTRUE;
+		xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); /*lint !e9044 Function parameter modified to ensure it is capped to available space. */
+	}
+	else if( xSpace >= xRequiredSpace )
+	{
+		/* This is a message buffer, as opposed to a stream buffer, and there
+		is enough space to write both the message length and the message itself
+		into the buffer.  Start by writing the length of the data, the data
+		itself will be written later in this function. */
+		xShouldWrite = pdTRUE;
+		( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );
+	}
+	else
+	{
+		/* There is space available, but not enough space. */
+		xShouldWrite = pdFALSE;
+	}
+
+	if( xShouldWrite != pdFALSE )
+	{
+		/* Writes the data itself. */
+		xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		/* Checking if there is data and clearing the notification state must be
+		performed atomically. */
+		taskENTER_CRITICAL();
+		{
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+			/* If this function was invoked by a message buffer read then
+			xBytesToStoreMessageLength holds the number of bytes used to hold
+			the length of the next discrete message.  If this function was
+			invoked by a stream buffer read then xBytesToStoreMessageLength will
+			be 0. */
+			if( xBytesAvailable <= xBytesToStoreMessageLength )
+			{
+				/* Clear notification state as going to wait for data. */
+				( void ) xTaskNotifyStateClear( NULL );
+
+				/* Should only be one reader. */
+				configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
+				pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		if( xBytesAvailable <= xBytesToStoreMessageLength )
+		{
+			/* Wait for data to be available. */
+			traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, UINT32_MAX, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToReceive = NULL;
+
+			/* Recheck the data available after blocking. */
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+	}
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );
+			sbRECEIVE_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength )
+{
+size_t xOriginalTail, xReceivedLength, xNextMessageLength;
+
+	if( xBytesToStoreMessageLength != ( size_t ) 0 )
+	{
+		/* A discrete message is being received.  First receive the length
+		of the message.  A copy of the tail is stored so the buffer can be
+		returned to its prior state if the length of the message is too
+		large for the provided buffer. */
+		xOriginalTail = pxStreamBuffer->xTail;
+		( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
+
+		/* Reduce the number of bytes available by the number of bytes just
+		read out. */
+		xBytesAvailable -= xBytesToStoreMessageLength;
+
+		/* Check there is enough space in the buffer provided by the
+		user. */
+		if( xNextMessageLength > xBufferLengthBytes )
+		{
+			/* The user has provided insufficient space to read the message
+			so return the buffer to its previous state (so the length of
+			the message is in the buffer again). */
+			pxStreamBuffer->xTail = xOriginalTail;
+			xNextMessageLength = 0;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		/* A stream of bytes is being received (as opposed to a discrete
+		message), so read as many bytes as possible. */
+		xNextMessageLength = xBufferLengthBytes;
+	}
+
+	/* Read the actual data. */
+	xReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+BaseType_t xReturn;
+size_t xTail;
+
+	configASSERT( pxStreamBuffer );
+
+	/* True if no bytes are available. */
+	xTail = pxStreamBuffer->xTail;
+	if( pxStreamBuffer->xHead == xTail )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
+{
+BaseType_t xReturn;
+size_t xBytesToStoreMessageLength;
+const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+
+	configASSERT( pxStreamBuffer );
+
+	/* This generic version of the receive function is used by both message
+	buffers, which store discrete messages, and stream buffers, which store a
+	continuous stream of bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	/* True if the available space equals zero. */
+	if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToSend = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )
+{
+size_t xNextHead, xFirstLength;
+
+	configASSERT( xCount > ( size_t ) 0 );
+
+	xNextHead = pxStreamBuffer->xHead;
+
+	/* Calculate the number of bytes that can be added in the first write -
+	which may be less than the total number of bytes that need to be added if
+	the buffer will wrap back to the beginning. */
+	xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
+
+	/* Write as many bytes as can be written in the first write. */
+	configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
+	memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+	/* If the number of bytes written was less than the number that could be
+	written in the first write... */
+	if( xCount > xFirstLength )
+	{
+		/* ...then write the remaining bytes to the start of the buffer. */
+		configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
+		memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xNextHead += xCount;
+	if( xNextHead >= pxStreamBuffer->xLength )
+	{
+		xNextHead -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxStreamBuffer->xHead = xNextHead;
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer, uint8_t *pucData, size_t xMaxCount, size_t xBytesAvailable )
+{
+size_t xCount, xFirstLength, xNextTail;
+
+	/* Use the minimum of the wanted bytes and the available bytes. */
+	xCount = configMIN( xBytesAvailable, xMaxCount );
+
+	if( xCount > ( size_t ) 0 )
+	{
+		xNextTail = pxStreamBuffer->xTail;
+
+		/* Calculate the number of bytes that can be read - which may be
+		less than the number wanted if the data wraps around to the start of
+		the buffer. */
+		xFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount );
+
+		/* Obtain the number of bytes it is possible to obtain in the first
+		read.  Asserts check bounds of read and write. */
+		configASSERT( xFirstLength <= xMaxCount );
+		configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );
+		memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+		/* If the total number of wanted bytes is greater than the number
+		that could be read in the first read... */
+		if( xCount > xFirstLength )
+		{
+			/*...then read the remaining bytes from the start of the buffer. */
+			configASSERT( xCount <= xMaxCount );
+			memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Move the tail pointer to effectively remove the data read from
+		the buffer. */
+		xNextTail += xCount;
+
+		if( xNextTail >= pxStreamBuffer->xLength )
+		{
+			xNextTail -= pxStreamBuffer->xLength;
+		}
+
+		pxStreamBuffer->xTail = xNextTail;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
+{
+/* Returns the distance between xTail and xHead. */
+size_t xCount;
+
+	xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
+	xCount -= pxStreamBuffer->xTail;
+	if ( xCount >= pxStreamBuffer->xLength )
+	{
+		xCount -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  BaseType_t xIsMessageBuffer )
+{
+	/* Assert here is deliberately writing to the entire buffer to ensure it can
+	be written to without generating exceptions, and is setting the buffer to a
+	known value to assist in development/debugging. */
+	#if( configASSERT_DEFINED == 1 )
+	{
+		/* The value written just has to be identifiable when looking at the
+		memory.  Don't use 0xA5 as that is the stack fill value and could
+		result in confusion as to what is actually being observed. */
+		const BaseType_t xWriteValue = 0x55;
+		configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
+	}
+	#endif
+
+	memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
+	pxStreamBuffer->pucBuffer = pucBuffer;
+	pxStreamBuffer->xLength = xBufferSizeBytes;
+	pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
+
+	if( xIsMessageBuffer != pdFALSE )
+	{
+		pxStreamBuffer->ucFlags |= sbFLAGS_IS_MESSAGE_BUFFER;
+	}
+}
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
+	{
+		return ( ( StreamBuffer_t * ) xStreamBuffer )->uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber )
+	{
+		( ( StreamBuffer_t * ) xStreamBuffer )->uxStreamBufferNumber = uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
+	{
+		return ( ( StreamBuffer_t * )xStreamBuffer )->ucFlags | sbFLAGS_IS_MESSAGE_BUFFER;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/tasks.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/tasks.c
new file mode 100644
index 00000000..e41d9d18
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/tasks.c
@@ -0,0 +1,5039 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "stack_macros.h"
+
+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
+header files above, but not in this file, in order to generate the correct
+privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+
+/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
+functions but without including stdio.h here. */
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )
+	/* At the bottom of this file are two optional functions that can be used
+	to generate human readable text from the raw data generated by the
+	uxTaskGetSystemState() function.  Note the formatting functions are provided
+	for convenience only, and are NOT considered part of the kernel. */
+	#include 
+#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define taskYIELD_IF_USING_PREEMPTION()
+#else
+	#define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/* Values that can be assigned to the ucNotifyState member of the TCB. */
+#define taskNOT_WAITING_NOTIFICATION	( ( uint8_t ) 0 )
+#define taskWAITING_NOTIFICATION		( ( uint8_t ) 1 )
+#define taskNOTIFICATION_RECEIVED		( ( uint8_t ) 2 )
+
+/*
+ * The value used to fill the stack of a task when the task is created.  This
+ * is used purely for checking the high water mark for tasks.
+ */
+#define tskSTACK_FILL_BYTE	( 0xa5U )
+
+/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
+dynamically allocated RAM, in which case when any task is deleted it is known
+that both the task's stack and TCB need to be freed.  Sometimes the
+FreeRTOSConfig.h settings only allow a task to be created using statically
+allocated RAM, in which case when any task is deleted it is known that neither
+the task's stack or TCB should be freed.  Sometimes the FreeRTOSConfig.h
+settings allow a task to be created using either statically or dynamically
+allocated RAM, in which case a member of the TCB is used to record whether the
+stack and/or TCB were allocated statically or dynamically, so when a task is
+deleted the RAM that was allocated dynamically is freed again and no attempt is
+made to free the RAM that was allocated statically.
+tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a
+task to be created using either statically or dynamically allocated RAM.  Note
+that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with
+a statically allocated stack and a dynamically allocated TCB.
+!!!NOTE!!! If the definition of tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is
+changed then the definition of StaticTask_t must also be updated. */
+#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE	( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB 		( ( uint8_t ) 0 )
+#define tskSTATICALLY_ALLOCATED_STACK_ONLY 			( ( uint8_t ) 1 )
+#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB		( ( uint8_t ) 2 )
+
+/* If any of the following are set then task stacks are filled with a known
+value so the high water mark can be determined.  If none of the following are
+set then don't fill the stack so there is no unnecessary dependency on memset. */
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	1
+#else
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	0
+#endif
+
+/*
+ * Macros used by vListTask to indicate which state a task is in.
+ */
+#define tskRUNNING_CHAR		( 'X' )
+#define tskBLOCKED_CHAR		( 'B' )
+#define tskREADY_CHAR		( 'R' )
+#define tskDELETED_CHAR		( 'D' )
+#define tskSUSPENDED_CHAR	( 'S' )
+
+/*
+ * Some kernel aware debuggers require the data the debugger needs access to be
+ * global, rather than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+	#define static
+#endif
+
+/* The name allocated to the Idle task.  This can be overridden by defining
+configIDLE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configIDLE_TASK_NAME
+	#define configIDLE_TASK_NAME "IDLE"
+#endif
+
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
+	performed in a generic way that is not optimised to any particular
+	microcontroller architecture. */
+
+	/* uxTopReadyPriority holds the priority of the highest priority ready
+	state task. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( ( uxPriority ) > uxTopReadyPriority )														\
+		{																								\
+			uxTopReadyPriority = ( uxPriority );														\
+		}																								\
+	} /* taskRECORD_READY_PRIORITY */
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()															\
+	{																									\
+	UBaseType_t uxTopPriority = uxTopReadyPriority;														\
+																										\
+		/* Find the highest priority queue that contains ready tasks. */								\
+		while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) )							\
+		{																								\
+			configASSERT( uxTopPriority );																\
+			--uxTopPriority;																			\
+		}																								\
+																										\
+		/* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of						\
+		the	same priority get an equal share of the processor time. */									\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );			\
+		uxTopReadyPriority = uxTopPriority;																\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK */
+
+	/*-----------------------------------------------------------*/
+
+	/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
+	they are only required when a port optimised method of task selection is
+	being used. */
+	#define taskRESET_READY_PRIORITY( uxPriority )
+	#define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
+	performed in a way that is tailored to the particular microcontroller
+	architecture being used. */
+
+	/* A port optimised version is provided.  Call the port defined macros. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )	portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()														\
+	{																								\
+	UBaseType_t uxTopPriority;																		\
+																									\
+		/* Find the highest priority list that contains ready tasks. */								\
+		portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );								\
+		configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 );		\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );		\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK() */
+
+	/*-----------------------------------------------------------*/
+
+	/* A port optimised version is provided, call it only if the TCB being reset
+	is being referenced from a ready list.  If it is referenced from a delayed
+	or suspended list then it won't be in a ready list. */
+	#define taskRESET_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 )	\
+		{																								\
+			portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );							\
+		}																								\
+	}
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
+count overflows. */
+#define taskSWITCH_DELAYED_LISTS()																	\
+{																									\
+	List_t *pxTemp;																					\
+																									\
+	/* The delayed tasks list should be empty when the lists are switched. */						\
+	configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );										\
+																									\
+	pxTemp = pxDelayedTaskList;																		\
+	pxDelayedTaskList = pxOverflowDelayedTaskList;													\
+	pxOverflowDelayedTaskList = pxTemp;																\
+	xNumOfOverflows++;																				\
+	prvResetNextTaskUnblockTime();																	\
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Place the task represented by pxTCB into the appropriate ready list for
+ * the task.  It is inserted at the end of the list.
+ */
+#define prvAddTaskToReadyList( pxTCB )																\
+	traceMOVED_TASK_TO_READY_STATE( pxTCB );														\
+	taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );												\
+	vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \
+	tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+/*-----------------------------------------------------------*/
+
+/*
+ * Several functions take an TaskHandle_t parameter that can optionally be NULL,
+ * where NULL is used to indicate that the handle of the currently executing
+ * task should be used in place of the parameter.  This macro simply checks to
+ * see if the parameter is NULL and returns a pointer to the appropriate TCB.
+ */
+#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? ( TCB_t * ) pxCurrentTCB : ( TCB_t * ) ( pxHandle ) )
+
+/* The item value of the event list item is normally used to hold the priority
+of the task to which it belongs (coded to allow it to be held in reverse
+priority order).  However, it is occasionally borrowed for other purposes.  It
+is important its value is not updated due to a task priority change while it is
+being used for another purpose.  The following bit definition is used to inform
+the scheduler that the value should not be changed - in which case it is the
+responsibility of whichever module is using the value to ensure it gets set back
+to its original value when it is released. */
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x8000U
+#else
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x80000000UL
+#endif
+
+/*
+ * Task control block.  A task control block (TCB) is allocated for each task,
+ * and stores task state information, including a pointer to the task's context
+ * (the task's run time environment, including register values)
+ */
+typedef struct tskTaskControlBlock
+{
+	volatile StackType_t	*pxTopOfStack;	/*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+		xMPU_SETTINGS	xMPUSettings;		/*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+	#endif
+
+	ListItem_t			xStateListItem;	/*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+	ListItem_t			xEventListItem;		/*< Used to reference a task from an event list. */
+	UBaseType_t			uxPriority;			/*< The priority of the task.  0 is the lowest priority. */
+	StackType_t			*pxStack;			/*< Points to the start of the stack. */
+	char				pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+	#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+		StackType_t		*pxEndOfStack;		/*< Points to the highest valid address for the stack. */
+	#endif
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+		UBaseType_t		uxCriticalNesting;	/*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxTCBNumber;		/*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
+		UBaseType_t		uxTaskNumber;		/*< Stores a number specifically for use by third party trace code. */
+	#endif
+
+	#if ( configUSE_MUTEXES == 1 )
+		UBaseType_t		uxBasePriority;		/*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+		UBaseType_t		uxMutexesHeld;
+	#endif
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+		TaskHookFunction_t pxTaskTag;
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+		void			*pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+	#endif
+
+	#if( configGENERATE_RUN_TIME_STATS == 1 )
+		uint32_t		ulRunTimeCounter;	/*< Stores the amount of time the task has spent in the Running state. */
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		/* Allocate a Newlib reent structure that is specific to this task.
+		Note Newlib support has been included by popular demand, but is not
+		used by the FreeRTOS maintainers themselves.  FreeRTOS is not
+		responsible for resulting newlib operation.  User must be familiar with
+		newlib and must provide system-wide implementations of the necessary
+		stubs. Be warned that (at the time of writing) the current newlib design
+		implements a system-wide malloc() that must be provided with locks. */
+		struct	_reent xNewLib_reent;
+	#endif
+
+	#if( configUSE_TASK_NOTIFICATIONS == 1 )
+		volatile uint32_t ulNotifiedValue;
+		volatile uint8_t ucNotifyState;
+	#endif
+
+	/* See the comments above the definition of
+	tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
+	#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */
+		uint8_t	ucStaticallyAllocated; 		/*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+		uint8_t ucDelayAborted;
+	#endif
+
+} tskTCB;
+
+/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
+below to enable the use of older kernel aware debuggers. */
+typedef tskTCB TCB_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+
+PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+
+/* Lists for ready and blocked tasks. --------------------*/
+PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ] = {0};	/*< Prioritised ready tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList1 = {0};								/*< Delayed tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList2 = {0};								/*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList = NULL;					/*< Points to the delayed task list currently being used. */
+PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList = NULL;			/*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t xPendingReadyList = {0};								/*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */
+
+#if( INCLUDE_vTaskDelete == 1 )
+
+	PRIVILEGED_DATA static List_t xTasksWaitingTermination = {0};					/*< Tasks that have been deleted - but their memory not yet freed. */
+	PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
+
+#endif
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	PRIVILEGED_DATA static List_t xSuspendedTaskList = {0};						/*< Tasks that are currently suspended. */
+
+#endif
+
+/* Other file private variables. --------------------------------*/
+PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks 	= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xTickCount 				= ( TickType_t ) configINITIAL_TICK_COUNT;
+PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority 		= tskIDLE_PRIORITY;
+PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning 		= pdFALSE;
+PRIVILEGED_DATA static volatile UBaseType_t uxPendedTicks 			= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile BaseType_t xYieldPending 			= pdFALSE;
+PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows 			= ( BaseType_t ) 0;
+PRIVILEGED_DATA static UBaseType_t uxTaskNumber 					= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime		= ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
+PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle					= NULL;			/*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */
+
+/* Context switches are held pending while the scheduler is suspended.  Also,
+interrupts must not manipulate the xStateListItem of a TCB, or any of the
+lists the xStateListItem can be referenced from, if the scheduler is suspended.
+If an interrupt needs to unblock a task while the scheduler is suspended then it
+moves the task's event list item into the xPendingReadyList, ready for the
+kernel to move the task from the pending ready list into the real ready list
+when the scheduler is unsuspended.  The pending ready list itself can only be
+accessed from a critical section. */
+PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended	= ( UBaseType_t ) pdFALSE;
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+	PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;	/*< Holds the value of a timer/counter the last time a task was switched in. */
+	PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL;		/*< Holds the total amount of execution time as defined by the run time counter clock. */
+
+#endif
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+/* Callback function prototypes. --------------------------*/
+#if(  configCHECK_FOR_STACK_OVERFLOW > 0 )
+	extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );
+#endif
+
+#if( configUSE_TICK_HOOK > 0 )
+	extern void vApplicationTickHook( void );
+#endif
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize );
+#endif
+
+/* File private functions. --------------------------------*/
+
+/**
+ * Utility task that simply returns pdTRUE if the task referenced by xTask is
+ * currently in the Suspended state, or pdFALSE if the task referenced by xTask
+ * is in any other state.
+ */
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first task.
+ */
+static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The idle task, which as all tasks is implemented as a never ending loop.
+ * The idle task is automatically created and added to the ready lists upon
+ * creation of the first user task.
+ *
+ * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );
+
+/*
+ * Utility to free all memory allocated by the scheduler to hold a TCB,
+ * including the stack pointed to by the TCB.
+ *
+ * This does not free memory allocated by the task itself (i.e. memory
+ * allocated by calls to pvPortMalloc from within the tasks application code).
+ */
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Used only by the idle task.  This checks to see if anything has been placed
+ * in the list of tasks waiting to be deleted.  If so the task is cleaned up
+ * and its TCB deleted.
+ */
+static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The currently executing task is entering the Blocked state.  Add the task to
+ * either the current or the overflow delayed task list.
+ */
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * Fills an TaskStatus_t structure with information on each task that is
+ * referenced from the pxList list (which may be a ready list, a delayed list,
+ * a suspended list, etc.).
+ *
+ * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
+ * NORMAL APPLICATION CODE.
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Searches pxList for a task with name pcNameToQuery - returning a handle to
+ * the task if it is found, or NULL if the task is not found.
+ */
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * When a task is created, the stack of the task is filled with a known value.
+ * This function determines the 'high water mark' of the task stack by
+ * determining how much of the stack remains at the original preset value.
+ */
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+
+	static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Return the amount of time, in ticks, that will pass before the kernel will
+ * next move a task from the Blocked state to the Running state.
+ *
+ * This conditional compilation should use inequality to 0, not equality to 1.
+ * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
+ * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
+ * set to a value other than 1.
+ */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Set xNextTaskUnblockTime to the time at which the next Blocked state task
+ * will exit the Blocked state.
+ */
+static void prvResetNextTaskUnblockTime( void );
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	/*
+	 * Helper function used to pad task names with spaces when printing out
+	 * human readable tables of task information.
+	 */
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Called after a Task_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName, 		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a new task has been created and initialised to place the task
+ * under the control of the scheduler.
+ */
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
+
+/*
+ * freertos_tasks_c_additions_init() should only be called if the user definable
+ * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
+ * called by the function.
+ */
+#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+
+	static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer )
+	{
+	TCB_t *pxNewTCB;
+	TaskHandle_t xReturn;
+
+		configASSERT( puxStackBuffer != NULL );
+		configASSERT( pxTaskBuffer != NULL );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTask_t equals the size of the real task
+			structure. */
+			volatile size_t xSize = sizeof( StaticTask_t );
+			configASSERT( xSize == sizeof( TCB_t ) );
+		}
+		#endif /* configASSERT_DEFINED */
+
+
+		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
+		{
+			/* The memory used for the task's TCB and stack are passed into this
+			function - use them. */
+			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+		}
+		else
+		{
+			xReturn = NULL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* SUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
+		configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
+
+		if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
+
+			/* Store the stack location in the TCB. */
+			pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+									pxTaskDefinition->pcName,
+									( uint32_t ) pxTaskDefinition->usStackDepth,
+									pxTaskDefinition->pvParameters,
+									pxTaskDefinition->uxPriority,
+									pxCreatedTask, pxNewTCB,
+									pxTaskDefinition->xRegions );
+
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer );
+
+		if( pxTaskDefinition->puxStackBuffer != NULL )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Store the stack location in the TCB. */
+				pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+				#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+				{
+					/* Tasks can be created statically or dynamically, so note
+					this task had a statically allocated stack in case it is
+					later deleted.  The TCB was allocated dynamically. */
+					pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
+				}
+				#endif
+
+				prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+										pxTaskDefinition->pcName,
+										( uint32_t ) pxTaskDefinition->usStackDepth,
+										pxTaskDefinition->pvParameters,
+										pxTaskDefinition->uxPriority,
+										pxCreatedTask, pxNewTCB,
+										pxTaskDefinition->xRegions );
+
+				prvAddNewTaskToReadyList( pxNewTCB );
+				xReturn = pdPASS;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn;
+
+		/* If the stack grows down then allocate the stack then the TCB so the stack
+		does not grow into the TCB.  Likewise if the stack grows up then allocate
+		the TCB then the stack. */
+		#if( portSTACK_GROWTH > 0 )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends on
+			the implementation of the port malloc function and whether or not static
+			allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Allocate space for the stack used by the task being created.
+				The base of the stack memory stored in the TCB so the task can
+				be deleted later if required. */
+				pxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				if( pxNewTCB->pxStack == NULL )
+				{
+					/* Could not allocate the stack.  Delete the allocated TCB. */
+					vPortFree( pxNewTCB );
+					pxNewTCB = NULL;
+				}
+			}
+		}
+		#else /* portSTACK_GROWTH */
+		{
+		StackType_t *pxStack;
+
+			/* Allocate space for the stack used by the task being created. */
+			pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+			if( pxStack != NULL )
+			{
+				/* Allocate space for the TCB. */
+				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e961 MISRA exception as the casts are only redundant for some paths. */
+
+				if( pxNewTCB != NULL )
+				{
+					/* Store the stack location in the TCB. */
+					pxNewTCB->pxStack = pxStack;
+				}
+				else
+				{
+					/* The stack cannot be used as the TCB was not created.  Free
+					it again. */
+					vPortFree( pxStack );
+				}
+			}
+			else
+			{
+				pxNewTCB = NULL;
+			}
+		}
+		#endif /* portSTACK_GROWTH */
+
+		if( pxNewTCB != NULL )
+		{
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created dynamically in case it is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions )
+{
+StackType_t *pxTopOfStack;
+UBaseType_t x;
+
+	#if( portUSING_MPU_WRAPPERS == 1 )
+		/* Should the task be created in privileged mode? */
+		BaseType_t xRunPrivileged;
+		if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
+		{
+			xRunPrivileged = pdTRUE;
+		}
+		else
+		{
+			xRunPrivileged = pdFALSE;
+		}
+		uxPriority &= ~portPRIVILEGE_BIT;
+	#endif /* portUSING_MPU_WRAPPERS == 1 */
+
+	/* Avoid dependency on memset() if it is not required. */
+	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
+	{
+		/* Fill the stack with a known value to assist debugging. */
+		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
+	}
+	#endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
+
+	/* Calculate the top of stack address.  This depends on whether the stack
+	grows from high memory to low (as per the 80x86) or vice versa.
+	portSTACK_GROWTH is used to make the result positive or negative as required
+	by the port. */
+	#if( portSTACK_GROWTH < 0 )
+	{
+		pxTopOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type. */
+
+		/* Check the alignment of the calculated top of stack is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		#if( configRECORD_STACK_HIGH_ADDRESS == 1 )
+		{
+			/* Also record the stack's high address, which may assist
+			debugging. */
+			pxNewTCB->pxEndOfStack = pxTopOfStack;
+		}
+		#endif /* configRECORD_STACK_HIGH_ADDRESS */
+	}
+	#else /* portSTACK_GROWTH */
+	{
+		pxTopOfStack = pxNewTCB->pxStack;
+
+		/* Check the alignment of the stack buffer is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		/* The other extreme of the stack space is required if stack checking is
+		performed. */
+		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+	}
+	#endif /* portSTACK_GROWTH */
+
+	/* Store the task name in the TCB. */
+	for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+	{
+		pxNewTCB->pcTaskName[ x ] = pcName[ x ];
+
+		/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+		configMAX_TASK_NAME_LEN characters just in case the memory after the
+		string is not accessible (extremely unlikely). */
+		if( pcName[ x ] == 0x00 )
+		{
+			break;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	/* Ensure the name string is terminated in the case that the string length
+	was greater or equal to configMAX_TASK_NAME_LEN. */
+	pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+
+	/* This is used as an array index so must ensure it's not too large.  First
+	remove the privilege bit if one is present. */
+	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+	{
+		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxNewTCB->uxPriority = uxPriority;
+	#if ( configUSE_MUTEXES == 1 )
+	{
+		pxNewTCB->uxBasePriority = uxPriority;
+		pxNewTCB->uxMutexesHeld = 0;
+	}
+	#endif /* configUSE_MUTEXES */
+
+	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
+	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
+
+	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
+	back to	the containing TCB from a generic item in a list. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
+
+	/* Event lists are always in priority order. */
+	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+	{
+		pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U;
+	}
+	#endif /* portCRITICAL_NESTING_IN_TCB */
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+	{
+		pxNewTCB->pxTaskTag = NULL;
+	}
+	#endif /* configUSE_APPLICATION_TASK_TAG */
+
+	#if ( configGENERATE_RUN_TIME_STATS == 1 )
+	{
+		pxNewTCB->ulRunTimeCounter = 0UL;
+	}
+	#endif /* configGENERATE_RUN_TIME_STATS */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+	{
+		vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
+	}
+	#else
+	{
+		/* Avoid compiler warning about unreferenced parameter. */
+		( void ) xRegions;
+	}
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+	{
+		for( x = 0; x < ( UBaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS; x++ )
+		{
+			pxNewTCB->pvThreadLocalStoragePointers[ x ] = NULL;
+		}
+	}
+	#endif
+
+	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+	{
+		pxNewTCB->ulNotifiedValue = 0;
+		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+	}
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+	{
+		/* Initialise this task's Newlib reent structure. */
+		_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
+	}
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		pxNewTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Initialize the TCB stack to look as if the task was already running,
+	but had been interrupted by the scheduler.  The return address is set
+	to the start of the task function. Once the stack has been initialised
+	the top of stack variable is updated. */
+	#if( portUSING_MPU_WRAPPERS == 1 )
+	{
+		pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+	}
+	#else /* portUSING_MPU_WRAPPERS */
+	{
+		pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+	}
+	#endif /* portUSING_MPU_WRAPPERS */
+
+	if( ( void * ) pxCreatedTask != NULL )
+	{
+		/* Pass the handle out in an anonymous way.  The handle can be used to
+		change the created task's priority, delete the created task, etc.*/
+		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
+{
+	/* Ensure interrupts don't access the task lists while the lists are being
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		uxCurrentNumberOfTasks++;
+		if( pxCurrentTCB == NULL )
+		{
+			/* There are no other tasks, or all the other tasks are in
+			the suspended state - make this the current task. */
+			pxCurrentTCB = pxNewTCB;
+
+			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+			{
+				/* This is the first task to be created so do the preliminary
+				initialisation required.  We will not recover if this call
+				fails, but we will report the failure. */
+				prvInitialiseTaskLists();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* If the scheduler is not already running, make this task the
+			current task if it is the highest priority task to be created
+			so far. */
+			if( xSchedulerRunning == pdFALSE )
+			{
+				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+				{
+					pxCurrentTCB = pxNewTCB;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		uxTaskNumber++;
+
+		#if ( configUSE_TRACE_FACILITY == 1 )
+		{
+			/* Add a counter into the TCB for tracing only. */
+			pxNewTCB->uxTCBNumber = uxTaskNumber;
+		}
+		#endif /* configUSE_TRACE_FACILITY */
+		traceTASK_CREATE( pxNewTCB );
+
+		prvAddTaskToReadyList( pxNewTCB );
+
+		portSETUP_TCB( pxNewTCB );
+	}
+	taskEXIT_CRITICAL();
+
+	if( xSchedulerRunning != pdFALSE )
+	{
+		/* If the created task is of a higher priority than the current task
+		then it should run now. */
+		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
+		{
+			taskYIELD_IF_USING_PREEMPTION();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	void vTaskDelete( TaskHandle_t xTaskToDelete )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the calling task that is
+			being deleted. */
+			pxTCB = prvGetTCBFromHandle( xTaskToDelete );
+
+			/* Remove task from the ready list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Increment the uxTaskNumber also so kernel aware debuggers can
+			detect that the task lists need re-generating.  This is done before
+			portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
+			not return. */
+			uxTaskNumber++;
+
+			if( pxTCB == pxCurrentTCB )
+			{
+				/* A task is deleting itself.  This cannot complete within the
+				task itself, as a context switch to another task is required.
+				Place the task in the termination list.  The idle task will
+				check the termination list and free up any memory allocated by
+				the scheduler for the TCB and stack of the deleted task. */
+				vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
+
+				/* Increment the ucTasksDeleted variable so the idle task knows
+				there is a task that has been deleted and that it should therefore
+				check the xTasksWaitingTermination list. */
+				++uxDeletedTasksWaitingCleanUp;
+
+				/* The pre-delete hook is primarily for the Windows simulator,
+				in which Windows specific clean up operations are performed,
+				after which it is not possible to yield away from this task -
+				hence xYieldPending is used to latch that a context switch is
+				required. */
+				portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
+			}
+			else
+			{
+				--uxCurrentNumberOfTasks;
+				prvDeleteTCB( pxTCB );
+
+				/* Reset the next expected unblock time in case it referred to
+				the task that has just been deleted. */
+				prvResetNextTaskUnblockTime();
+			}
+
+			traceTASK_DELETE( pxTCB );
+		}
+		taskEXIT_CRITICAL();
+
+		/* Force a reschedule if it is the currently running task that has just
+		been deleted. */
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelayUntil == 1 )
+
+	void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
+	{
+	TickType_t xTimeToWake;
+	BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
+
+		configASSERT( pxPreviousWakeTime );
+		configASSERT( ( xTimeIncrement > 0U ) );
+		configASSERT( uxSchedulerSuspended == 0 );
+
+		vTaskSuspendAll();
+		{
+			/* Minor optimisation.  The tick count cannot change in this
+			block. */
+			const TickType_t xConstTickCount = xTickCount;
+
+			/* Generate the tick time at which the task wants to wake. */
+			xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
+
+			if( xConstTickCount < *pxPreviousWakeTime )
+			{
+				/* The tick count has overflowed since this function was
+				lasted called.  In this case the only time we should ever
+				actually delay is if the wake time has also	overflowed,
+				and the wake time is greater than the tick time.  When this
+				is the case it is as if neither time had overflowed. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The tick time has not overflowed.  In this case we will
+				delay if either the wake time has overflowed, and/or the
+				tick time is less than the wake time. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+
+			/* Update the wake time ready for the next call. */
+			*pxPreviousWakeTime = xTimeToWake;
+
+			if( xShouldDelay != pdFALSE )
+			{
+				traceTASK_DELAY_UNTIL( xTimeToWake );
+
+				/* prvAddCurrentTaskToDelayedList() needs the block time, not
+				the time to wake, so subtract the current tick count. */
+				prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		xAlreadyYielded = xTaskResumeAll();
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelayUntil */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+
+	void vTaskDelay( const TickType_t xTicksToDelay )
+	{
+	BaseType_t xAlreadyYielded = pdFALSE;
+
+		/* A delay time of zero just forces a reschedule. */
+		if( xTicksToDelay > ( TickType_t ) 0U )
+		{
+			configASSERT( uxSchedulerSuspended == 0 );
+			vTaskSuspendAll();
+			{
+				traceTASK_DELAY();
+
+				/* A task that is removed from the event list while the
+				scheduler is suspended will not get placed in the ready
+				list or removed from the blocked list until the scheduler
+				is resumed.
+
+				This task cannot be in an event list as it is the currently
+				executing task. */
+				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
+			}
+			xAlreadyYielded = xTaskResumeAll();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelay */
+/*-----------------------------------------------------------*/
+
+#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) )
+
+	eTaskState eTaskGetState( TaskHandle_t xTask )
+	{
+	eTaskState eReturn;
+	List_t *pxStateList;
+	const TCB_t * const pxTCB = ( TCB_t * ) xTask;
+
+		configASSERT( pxTCB );
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			/* The task calling this function is querying its own state. */
+			eReturn = eRunning;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				pxStateList = ( List_t * ) listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+			}
+			taskEXIT_CRITICAL();
+
+			if( ( pxStateList == pxDelayedTaskList ) || ( pxStateList == pxOverflowDelayedTaskList ) )
+			{
+				/* The task being queried is referenced from one of the Blocked
+				lists. */
+				eReturn = eBlocked;
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+				else if( pxStateList == &xSuspendedTaskList )
+				{
+					/* The task being queried is referenced from the suspended
+					list.  Is it genuinely suspended or is it block
+					indefinitely? */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
+					{
+						eReturn = eSuspended;
+					}
+					else
+					{
+						eReturn = eBlocked;
+					}
+				}
+			#endif
+
+			#if ( INCLUDE_vTaskDelete == 1 )
+				else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )
+				{
+					/* The task being queried is referenced from the deleted
+					tasks list, or it is not referenced from any lists at
+					all. */
+					eReturn = eDeleted;
+				}
+			#endif
+
+			else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
+			{
+				/* If the task is not in any other state, it must be in the
+				Ready (including pending ready) state. */
+				eReturn = eReady;
+			}
+		}
+
+		return eReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_eTaskGetState */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	UBaseType_t uxReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the that
+			called uxTaskPriorityGet() that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		taskEXIT_CRITICAL();
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	UBaseType_t uxReturn, uxSavedInterruptState;
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskPrioritySet == 1 )
+
+	void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )
+	{
+	TCB_t *pxTCB;
+	UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
+	BaseType_t xYieldRequired = pdFALSE;
+
+		configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );
+
+		/* Ensure the new priority is valid. */
+		if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+		{
+			uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being changed. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+
+			traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
+
+			#if ( configUSE_MUTEXES == 1 )
+			{
+				uxCurrentBasePriority = pxTCB->uxBasePriority;
+			}
+			#else
+			{
+				uxCurrentBasePriority = pxTCB->uxPriority;
+			}
+			#endif
+
+			if( uxCurrentBasePriority != uxNewPriority )
+			{
+				/* The priority change may have readied a task of higher
+				priority than the calling task. */
+				if( uxNewPriority > uxCurrentBasePriority )
+				{
+					if( pxTCB != pxCurrentTCB )
+					{
+						/* The priority of a task other than the currently
+						running task is being raised.  Is the priority being
+						raised above that of the running task? */
+						if( uxNewPriority >= pxCurrentTCB->uxPriority )
+						{
+							xYieldRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* The priority of the running task is being raised,
+						but the running task must already be the highest
+						priority task able to run so no yield is required. */
+					}
+				}
+				else if( pxTCB == pxCurrentTCB )
+				{
+					/* Setting the priority of the running task down means
+					there may now be another task of higher priority that
+					is ready to execute. */
+					xYieldRequired = pdTRUE;
+				}
+				else
+				{
+					/* Setting the priority of any other task down does not
+					require a yield as the running task must be above the
+					new priority of the task being modified. */
+				}
+
+				/* Remember the ready list the task might be referenced from
+				before its uxPriority member is changed so the
+				taskRESET_READY_PRIORITY() macro can function correctly. */
+				uxPriorityUsedOnEntry = pxTCB->uxPriority;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* Only change the priority being used if the task is not
+					currently using an inherited priority. */
+					if( pxTCB->uxBasePriority == pxTCB->uxPriority )
+					{
+						pxTCB->uxPriority = uxNewPriority;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The base priority gets set whatever. */
+					pxTCB->uxBasePriority = uxNewPriority;
+				}
+				#else
+				{
+					pxTCB->uxPriority = uxNewPriority;
+				}
+				#endif
+
+				/* Only reset the event list item value if the value is not
+				being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task is in the blocked or suspended list we need do
+				nothing more than change its priority variable. However, if
+				the task is in a ready list it needs to be removed and placed
+				in the list appropriate to its new priority. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+				{
+					/* The task is currently in its ready list - remove before
+					adding it to it's new ready list.  As we are in a critical
+					section we can do this even if the scheduler is suspended. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						/* It is known that the task is in its ready list so
+						there is no need to check again and the port level
+						reset macro can be called directly. */
+						portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				if( xYieldRequired != pdFALSE )
+				{
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* Remove compiler warning about unused variables when the port
+				optimised task selection is not being used. */
+				( void ) uxPriorityUsedOnEntry;
+			}
+		}
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* INCLUDE_vTaskPrioritySet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskSuspend( TaskHandle_t xTaskToSuspend )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the running task that is
+			being suspended. */
+			pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
+
+			traceTASK_SUSPEND( pxTCB );
+
+			/* Remove task from the ready/delayed list and place in the
+			suspended list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );
+
+			#if( configUSE_TASK_NOTIFICATIONS == 1 )
+			{
+				if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+				{
+					/* The task was blocked to wait for a notification, but is
+					now suspended, so no notification was received. */
+					pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				}
+			}
+			#endif
+		}
+		taskEXIT_CRITICAL();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			/* Reset the next expected unblock time in case it referred to the
+			task that is now in the Suspended state. */
+			taskENTER_CRITICAL();
+			{
+				prvResetNextTaskUnblockTime();
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			if( xSchedulerRunning != pdFALSE )
+			{
+				/* The current task has just been suspended. */
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				/* The scheduler is not running, but the task that was pointed
+				to by pxCurrentTCB has just been suspended and pxCurrentTCB
+				must be adjusted to point to a different task. */
+				if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks )
+				{
+					/* No other tasks are ready, so set pxCurrentTCB back to
+					NULL so when the next task is created pxCurrentTCB will
+					be set to point to it no matter what its relative priority
+					is. */
+					pxCurrentTCB = NULL;
+				}
+				else
+				{
+					vTaskSwitchContext();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
+	{
+	BaseType_t xReturn = pdFALSE;
+	const TCB_t * const pxTCB = ( TCB_t * ) xTask;
+
+		/* Accesses xPendingReadyList so must be called from a critical
+		section. */
+
+		/* It does not make sense to check if the calling task is suspended. */
+		configASSERT( xTask );
+
+		/* Is the task being resumed actually in the suspended list? */
+		if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )
+		{
+			/* Has the task already been resumed from within an ISR? */
+			if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
+			{
+				/* Is it in the suspended list because it is in the	Suspended
+				state, or because is is blocked with no timeout? */
+				if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */
+				{
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskResume( TaskHandle_t xTaskToResume )
+	{
+	TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;
+
+		/* It does not make sense to resume the calling task. */
+		configASSERT( xTaskToResume );
+
+		/* The parameter cannot be NULL as it is impossible to resume the
+		currently executing task. */
+		if( ( pxTCB != NULL ) && ( pxTCB != pxCurrentTCB ) )
+		{
+			taskENTER_CRITICAL();
+			{
+				if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+				{
+					traceTASK_RESUME( pxTCB );
+
+					/* The ready list can be accessed even if the scheduler is
+					suspended because this is inside a critical section. */
+					( void ) uxListRemove(  &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A higher priority task may have just been resumed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						/* This yield may not cause the task just resumed to run,
+						but will leave the lists in the correct state for the
+						next yield. */
+						taskYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
+
+	BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
+	{
+	BaseType_t xYieldRequired = pdFALSE;
+	TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToResume );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+			{
+				traceTASK_RESUME_FROM_ISR( pxTCB );
+
+				/* Check the ready lists can be accessed. */
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					/* Ready lists can be accessed so move the task from the
+					suspended list to the ready list directly. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldRequired = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed or ready lists cannot be accessed so the task
+					is held in the pending ready list until the scheduler is
+					unsuspended. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xYieldRequired;
+	}
+
+#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+void vTaskStartScheduler( void )
+{
+BaseType_t xReturn;
+
+	/* Add the idle task at the lowest priority. */
+	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	{
+		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
+		StackType_t *pxIdleTaskStackBuffer = NULL;
+		uint32_t ulIdleTaskStackSize;
+
+		/* The Idle task is created using user provided RAM - obtain the
+		address of the RAM then create the idle task. */
+		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
+												configIDLE_TASK_NAME,
+												ulIdleTaskStackSize,
+												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
+												( tskIDLE_PRIORITY | portPRIVILEGE_BIT ),
+												pxIdleTaskStackBuffer,
+												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+
+		if( xIdleTaskHandle != NULL )
+		{
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+	}
+	#else
+	{
+		/* The Idle task is being created using dynamically allocated RAM. */
+		xReturn = xTaskCreate(	prvIdleTask,
+								configIDLE_TASK_NAME,
+								configMINIMAL_STACK_SIZE,
+								( void * ) NULL,
+								( tskIDLE_PRIORITY | portPRIVILEGE_BIT ),
+								&xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+	}
+	#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+	#if ( configUSE_TIMERS == 1 )
+	{
+		if( xReturn == pdPASS )
+		{
+			xReturn = xTimerCreateTimerTask();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif /* configUSE_TIMERS */
+
+	if( xReturn == pdPASS )
+	{
+		/* freertos_tasks_c_additions_init() should only be called if the user
+		definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is
+		the only macro called by the function. */
+		#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		{
+			freertos_tasks_c_additions_init();
+		}
+		#endif
+
+		/* Interrupts are turned off here, to ensure a tick does not occur
+		before or during the call to xPortStartScheduler().  The stacks of
+		the created tasks contain a status word with interrupts switched on
+		so interrupts will automatically get re-enabled when the first task
+		starts to run. */
+		portDISABLE_INTERRUPTS();
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to the task that will run first. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		xNextTaskUnblockTime = portMAX_DELAY;
+		xSchedulerRunning = pdTRUE;
+		xTickCount = ( TickType_t ) 0U;
+
+		/* If configGENERATE_RUN_TIME_STATS is defined then the following
+		macro must be defined to configure the timer/counter used to generate
+		the run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS
+		is set to 0 and the following line fails to build then ensure you do not
+		have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your
+		FreeRTOSConfig.h file. */
+		portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
+
+		/* Setting up the timer tick is hardware specific and thus in the
+		portable interface. */
+		if( xPortStartScheduler() != pdFALSE )
+		{
+			/* Should not reach here as if the scheduler is running the
+			function will not return. */
+		}
+		else
+		{
+			/* Should only reach here if a task calls xTaskEndScheduler(). */
+		}
+	}
+	else
+	{
+		/* This line will only be reached if the kernel could not be started,
+		because there was not enough FreeRTOS heap to create the idle task
+		or the timer task. */
+		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
+	}
+
+	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
+	meaning xIdleTaskHandle is not used anywhere else. */
+	( void ) xIdleTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskEndScheduler( void )
+{
+	/* Stop the scheduler interrupts and call the portable scheduler end
+	routine so the original ISRs can be restored if necessary.  The port
+	layer must ensure interrupts enable	bit is left in the correct state. */
+	portDISABLE_INTERRUPTS();
+	xSchedulerRunning = pdFALSE;
+	vPortEndScheduler();
+}
+/*----------------------------------------------------------*/
+
+void vTaskSuspendAll( void )
+{
+	/* A critical section is not required as the variable is of type
+	BaseType_t.  Please read Richard Barry's reply in the following link to a
+	post in the FreeRTOS support forum before reporting this as a bug! -
+	http://goo.gl/wu4acr */
+	++uxSchedulerSuspended;
+}
+/*----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void )
+	{
+	TickType_t xReturn;
+	UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
+
+		/* uxHigherPriorityReadyTasks takes care of the case where
+		configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
+		task that are in the Ready state, even though the idle task is
+		running. */
+		#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+		{
+			if( uxTopReadyPriority > tskIDLE_PRIORITY )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#else
+		{
+			const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;
+
+			/* When port optimised task selection is used the uxTopReadyPriority
+			variable is used as a bit map.  If bits other than the least
+			significant bit are set then there are tasks that have a priority
+			above the idle priority that are in the Ready state.  This takes
+			care of the case where the co-operative scheduler is in use. */
+			if( uxTopReadyPriority > uxLeastSignificantBit )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#endif
+
+		if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
+		{
+			xReturn = 0;
+		}
+		else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
+		{
+			/* There are other idle priority tasks in the ready state.  If
+			time slicing is used then the very next tick interrupt must be
+			processed. */
+			xReturn = 0;
+		}
+		else if( uxHigherPriorityReadyTasks != pdFALSE )
+		{
+			/* There are tasks in the Ready state that have a priority above the
+			idle priority.  This path can only be reached if
+			configUSE_PREEMPTION is 0. */
+			xReturn = 0;
+		}
+		else
+		{
+			xReturn = xNextTaskUnblockTime - xTickCount;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskResumeAll( void )
+{
+TCB_t *pxTCB = NULL;
+BaseType_t xAlreadyYielded = pdFALSE;
+
+	/* If uxSchedulerSuspended is zero then this function does not match a
+	previous call to vTaskSuspendAll(). */
+	configASSERT( uxSchedulerSuspended );
+
+	/* It is possible that an ISR caused a task to be removed from an event
+	list while the scheduler was suspended.  If this was the case then the
+	removed task will have been added to the xPendingReadyList.  Once the
+	scheduler has been resumed it is safe to move all the pending ready
+	tasks from this list into their appropriate ready list. */
+	taskENTER_CRITICAL();
+	{
+		--uxSchedulerSuspended;
+
+		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+		{
+			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
+			{
+				/* Move any readied tasks from the pending list into the
+				appropriate ready list. */
+				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+				{
+					pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) );
+					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* If the moved task has a priority higher than the current
+					task then a yield must be performed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( pxTCB != NULL )
+				{
+					/* A task was unblocked while the scheduler was suspended,
+					which may have prevented the next unblock time from being
+					re-calculated, in which case re-calculate it now.  Mainly
+					important for low power tickless implementations, where
+					this can prevent an unnecessary exit from low power
+					state. */
+					prvResetNextTaskUnblockTime();
+				}
+
+				/* If any ticks occurred while the scheduler was suspended then
+				they should be processed now.  This ensures the tick count does
+				not	slip, and that any delayed tasks are resumed at the correct
+				time. */
+				{
+					UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */
+
+					if( uxPendedCounts > ( UBaseType_t ) 0U )
+					{
+						do
+						{
+							if( xTaskIncrementTick() != pdFALSE )
+							{
+								xYieldPending = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+							--uxPendedCounts;
+						} while( uxPendedCounts > ( UBaseType_t ) 0U );
+
+						uxPendedTicks = 0;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( xYieldPending != pdFALSE )
+				{
+					#if( configUSE_PREEMPTION != 0 )
+					{
+						xAlreadyYielded = pdTRUE;
+					}
+					#endif
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xAlreadyYielded;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCount( void )
+{
+TickType_t xTicks;
+
+	/* Critical section required if running on a 16 bit processor. */
+	portTICK_TYPE_ENTER_CRITICAL();
+	{
+		xTicks = xTickCount;
+	}
+	portTICK_TYPE_EXIT_CRITICAL();
+
+	return xTicks;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCountFromISR( void )
+{
+TickType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
+	{
+		xReturn = xTickCount;
+	}
+	portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTaskGetNumberOfTasks( void )
+{
+	/* A critical section is not required because the variables are of type
+	BaseType_t. */
+	return uxCurrentNumberOfTasks;
+}
+/*-----------------------------------------------------------*/
+
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+TCB_t *pxTCB;
+
+	/* If null is passed in here then the name of the calling task is being
+	queried. */
+	pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+	configASSERT( pxTCB );
+	return &( pxTCB->pcTaskName[ 0 ] );
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] )
+	{
+	TCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL;
+	UBaseType_t x;
+	char cNextChar;
+
+		/* This function is called with the scheduler suspended. */
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
+
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
+
+				/* Check each character in the name looking for a match or
+				mismatch. */
+				for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+				{
+					cNextChar = pxNextTCB->pcTaskName[ x ];
+
+					if( cNextChar != pcNameToQuery[ x ] )
+					{
+						/* Characters didn't match. */
+						break;
+					}
+					else if( cNextChar == 0x00 )
+					{
+						/* Both strings terminated, a match must have been
+						found. */
+						pxReturn = pxNextTCB;
+						break;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( pxReturn != NULL )
+				{
+					/* The handle has been found. */
+					break;
+				}
+
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxReturn;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t uxQueue = configMAX_PRIORITIES;
+	TCB_t* pxTCB;
+
+		/* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
+		configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );
+
+		vTaskSuspendAll();
+		{
+			/* Search the ready lists. */
+			do
+			{
+				uxQueue--;
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );
+
+				if( pxTCB != NULL )
+				{
+					/* Found the handle. */
+					break;
+				}
+
+			} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+			/* Search the delayed lists. */
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );
+			}
+
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the suspended list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
+				}
+			}
+			#endif
+
+			#if( INCLUDE_vTaskDelete == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the deleted list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
+				}
+			}
+			#endif
+		}
+		( void ) xTaskResumeAll();
+
+		return ( TaskHandle_t ) pxTCB;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )
+	{
+	UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
+
+		vTaskSuspendAll();
+		{
+			/* Is there a space in the array for each task in the system? */
+			if( uxArraySize >= uxCurrentNumberOfTasks )
+			{
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Ready state. */
+				do
+				{
+					uxQueue--;
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
+
+				} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Blocked state. */
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
+
+				#if( INCLUDE_vTaskDelete == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task that has been deleted but not yet cleaned up. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
+				}
+				#endif
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task in the Suspended state. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
+				}
+				#endif
+
+				#if ( configGENERATE_RUN_TIME_STATS == 1)
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+							portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
+						#else
+							*pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+						#endif
+					}
+				}
+				#else
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						*pulTotalRunTime = 0;
+					}
+				}
+				#endif
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+	TaskHandle_t xTaskGetIdleTaskHandle( void )
+	{
+		/* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+		started, then xIdleTaskHandle will be NULL. */
+		configASSERT( ( xIdleTaskHandle != NULL ) );
+		return xIdleTaskHandle;
+	}
+
+#endif /* INCLUDE_xTaskGetIdleTaskHandle */
+/*----------------------------------------------------------*/
+
+/* This conditional compilation should use inequality to 0, not equality to 1.
+This is to ensure vTaskStepTick() is available when user defined low power mode
+implementations require configUSE_TICKLESS_IDLE to be set to a value other than
+1. */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	void vTaskStepTick( const TickType_t xTicksToJump )
+	{
+		/* Correct the tick count value after a period during which the tick
+		was suppressed.  Note this does *not* call the tick hook function for
+		each stepped tick. */
+		configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
+		xTickCount += xTicksToJump;
+		traceINCREASE_TICK_COUNT( xTicksToJump );
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+
+	BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB = ( TCB_t * ) xTask;
+	BaseType_t xReturn;
+
+		configASSERT( pxTCB );
+
+		vTaskSuspendAll();
+		{
+			/* A task can only be prematurely removed from the Blocked state if
+			it is actually in the Blocked state. */
+			if( eTaskGetState( xTask ) == eBlocked )
+			{
+				xReturn = pdPASS;
+
+				/* Remove the reference to the task from the blocked list.  An
+				interrupt won't touch the xStateListItem because the
+				scheduler is suspended. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+				/* Is the task waiting on an event also?  If so remove it from
+				the event list too.  Interrupts can touch the event list item,
+				even though the scheduler is suspended, so a critical section
+				is used. */
+				taskENTER_CRITICAL();
+				{
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+						pxTCB->ucDelayAborted = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				taskEXIT_CRITICAL();
+
+				/* Place the unblocked task into the appropriate ready list. */
+				prvAddTaskToReadyList( pxTCB );
+
+				/* A task being unblocked cannot cause an immediate context
+				switch if preemption is turned off. */
+				#if (  configUSE_PREEMPTION == 1 )
+				{
+					/* Preemption is on, but a context switch should only be
+					performed if the unblocked task has a priority that is
+					equal to or higher than the currently executing task. */
+					if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+					{
+						/* Pend the yield to be performed when the scheduler
+						is unsuspended. */
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_PREEMPTION */
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTaskAbortDelay */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskIncrementTick( void )
+{
+TCB_t * pxTCB;
+TickType_t xItemValue;
+BaseType_t xSwitchRequired = pdFALSE;
+
+	/* Called by the portable layer each time a tick interrupt occurs.
+	Increments the tick then checks to see if the new tick value will cause any
+	tasks to be unblocked. */
+	traceTASK_INCREMENT_TICK( xTickCount );
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		/* Minor optimisation.  The tick count cannot change in this
+		block. */
+		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
+
+		/* Increment the RTOS tick, switching the delayed and overflowed
+		delayed lists if it wraps to 0. */
+		xTickCount = xConstTickCount;
+
+		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
+		{
+			taskSWITCH_DELAYED_LISTS();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* See if this tick has made a timeout expire.  Tasks are stored in
+		the	queue in the order of their wake time - meaning once one task
+		has been found whose block time has not expired there is no need to
+		look any further down the list. */
+		if( xConstTickCount >= xNextTaskUnblockTime )
+		{
+			for( ;; )
+			{
+				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+				{
+					/* The delayed list is empty.  Set xNextTaskUnblockTime
+					to the maximum possible value so it is extremely
+					unlikely that the
+					if( xTickCount >= xNextTaskUnblockTime ) test will pass
+					next time through. */
+					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					break;
+				}
+				else
+				{
+					/* The delayed list is not empty, get the value of the
+					item at the head of the delayed list.  This is the time
+					at which the task at the head of the delayed list must
+					be removed from the Blocked state. */
+					pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
+					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
+
+					if( xConstTickCount < xItemValue )
+					{
+						/* It is not time to unblock this item yet, but the
+						item value is the time at which the task at the head
+						of the blocked list must be removed from the Blocked
+						state -	so record the item value in
+						xNextTaskUnblockTime. */
+						xNextTaskUnblockTime = xItemValue;
+						break;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* It is time to remove the item from the Blocked state. */
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+					/* Is the task waiting on an event also?  If so remove
+					it from the event list. */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Place the unblocked task into the appropriate ready
+					list. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A task being unblocked cannot cause an immediate
+					context switch if preemption is turned off. */
+					#if (  configUSE_PREEMPTION == 1 )
+					{
+						/* Preemption is on, but a context switch should
+						only be performed if the unblocked task has a
+						priority that is equal to or higher than the
+						currently executing task. */
+						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+						{
+							xSwitchRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					#endif /* configUSE_PREEMPTION */
+				}
+			}
+		}
+
+		/* Tasks of equal priority to the currently running task will share
+		processing time (time slice) if preemption is on, and the application
+		writer has not explicitly turned time slicing off. */
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
+		{
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+			{
+				xSwitchRequired = pdTRUE;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
+
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			/* Guard against the tick hook being called when the pended tick
+			count is being unwound (when the scheduler is being unlocked). */
+			if( uxPendedTicks == ( UBaseType_t ) 0U )
+			{
+				vApplicationTickHook();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICK_HOOK */
+	}
+	else
+	{
+		++uxPendedTicks;
+
+		/* The tick hook gets called at regular intervals, even if the
+		scheduler is locked. */
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			vApplicationTickHook();
+		}
+		#endif
+	}
+
+	#if ( configUSE_PREEMPTION == 1 )
+	{
+		if( xYieldPending != pdFALSE )
+		{
+			xSwitchRequired = pdTRUE;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif /* configUSE_PREEMPTION */
+
+	return xSwitchRequired;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )
+	{
+	TCB_t *xTCB;
+
+		/* If xTask is NULL then it is the task hook of the calling task that is
+		getting set. */
+		if( xTask == NULL )
+		{
+			xTCB = ( TCB_t * ) pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = ( TCB_t * ) xTask;
+		}
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+			xTCB->pxTaskTag = pxHookFunction;
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
+	{
+	TCB_t *xTCB;
+	TaskHookFunction_t xReturn;
+
+		/* If xTask is NULL then we are setting our own task hook. */
+		if( xTask == NULL )
+		{
+			xTCB = ( TCB_t * ) pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = ( TCB_t * ) xTask;
+		}
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+		{
+			xReturn = xTCB->pxTaskTag;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
+	{
+	TCB_t *xTCB;
+	BaseType_t xReturn;
+
+		/* If xTask is NULL then we are calling our own task hook. */
+		if( xTask == NULL )
+		{
+			xTCB = ( TCB_t * ) pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = ( TCB_t * ) xTask;
+		}
+
+		if( xTCB->pxTaskTag != NULL )
+		{
+			xReturn = xTCB->pxTaskTag( pvParameter );
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+void vTaskSwitchContext( void )
+{
+	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
+	{
+		/* The scheduler is currently suspended - do not allow a context
+		switch. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xYieldPending = pdFALSE;
+		traceTASK_SWITCHED_OUT();
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+				#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+					portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
+				#else
+					ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+				#endif
+
+				/* Add the amount of time the task has been running to the
+				accumulated time so far.  The time the task started running was
+				stored in ulTaskSwitchedInTime.  Note that there is no overflow
+				protection here so count values are only valid until the timer
+				overflows.  The guard against negative values is to protect
+				against suspect run time stat counter implementations - which
+				are provided by the application, not the kernel. */
+				if( ulTotalRunTime > ulTaskSwitchedInTime )
+				{
+					pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+				ulTaskSwitchedInTime = ulTotalRunTime;
+		}
+		#endif /* configGENERATE_RUN_TIME_STATS */
+
+		/* Check for stack overflow, if configured. */
+		taskCHECK_FOR_STACK_OVERFLOW();
+
+		/* Select a new task to run using either the generic C or port
+		optimised asm code. */
+		taskSELECT_HIGHEST_PRIORITY_TASK();
+		traceTASK_SWITCHED_IN();
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to this task. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
+	SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
+
+	/* Place the event list item of the TCB in the appropriate event list.
+	This is placed in the list in priority order so the highest priority task
+	is the first to be woken by the event.  The queue that contains the event
+	list is locked, preventing simultaneous access from interrupts. */
+	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event groups implementation. */
+	configASSERT( uxSchedulerSuspended != 0 );
+
+	/* Store the item value in the event list item.  It is safe to access the
+	event list item here as interrupts won't access the event list item of a
+	task that is not in the Blocked state. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Place the event list item of the TCB at the end of the appropriate event
+	list.  It is safe to access the event list here because it is part of an
+	event group implementation - and interrupts don't access event groups
+	directly (instead they access them indirectly by pending function calls to
+	the task level). */
+	vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+
+	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+		configASSERT( pxEventList );
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements -
+		it should be called with the scheduler suspended. */
+
+
+		/* Place the event list item of the TCB in the appropriate event list.
+		In this case it is assume that this is the only task that is going to
+		be waiting on this event list, so the faster vListInsertEnd() function
+		can be used in place of vListInsert. */
+		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+		/* If the task should block indefinitely then set the block time to a
+		value that will be recognised as an indefinite delay inside the
+		prvAddCurrentTaskToDelayedList() function. */
+		if( xWaitIndefinitely != pdFALSE )
+		{
+			xTicksToWait = portMAX_DELAY;
+		}
+
+		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
+		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
+{
+TCB_t *pxUnblockedTCB;
+BaseType_t xReturn;
+
+	/* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be
+	called from a critical section within an ISR. */
+
+	/* The event list is sorted in priority order, so the first in the list can
+	be removed as it is known to be the highest priority.  Remove the TCB from
+	the delayed list, and add it to the ready list.
+
+	If an event is for a queue that is locked then this function will never
+	get called - the lock count on the queue will get modified instead.  This
+	means exclusive access to the event list is guaranteed here.
+
+	This function assumes that a check has already been made to ensure that
+	pxEventList is not empty. */
+	pxUnblockedTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
+
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+		prvAddTaskToReadyList( pxUnblockedTCB );
+	}
+	else
+	{
+		/* The delayed and ready lists cannot be accessed, so hold this task
+		pending until the scheduler is resumed. */
+		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
+	}
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* Return true if the task removed from the event list has a higher
+		priority than the calling task.  This allows the calling task to know if
+		it should force a context switch now. */
+		xReturn = pdTRUE;
+
+		/* Mark that a yield is pending in case the user is not using the
+		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	#if( configUSE_TICKLESS_IDLE != 0 )
+	{
+		/* If a task is blocked on a kernel object then xNextTaskUnblockTime
+		might be set to the blocked task's time out time.  If the task is
+		unblocked for a reason other than a timeout xNextTaskUnblockTime is
+		normally left unchanged, because it is automatically reset to a new
+		value when the tick count equals xNextTaskUnblockTime.  However if
+		tickless idling is used it might be more important to enter sleep mode
+		at the earliest possible time - so reset xNextTaskUnblockTime here to
+		ensure it is updated at the earliest possible time. */
+		prvResetNextTaskUnblockTime();
+	}
+	#endif
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )
+{
+TCB_t *pxUnblockedTCB;
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event flags implementation. */
+	configASSERT( uxSchedulerSuspended != pdFALSE );
+
+	/* Store the new item value in the event list. */
+	listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Remove the event list form the event flag.  Interrupts do not access
+	event flags. */
+	pxUnblockedTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxEventListItem );
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( pxEventListItem );
+
+	/* Remove the task from the delayed list and add it to the ready list.  The
+	scheduler is suspended so interrupts will not be accessing the ready
+	lists. */
+	( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+	prvAddTaskToReadyList( pxUnblockedTCB );
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* The unblocked task has a priority above that of the calling task, so
+		a context switch is required.  This function is called with the
+		scheduler suspended so xYieldPending is set so the context switch
+		occurs immediately that the scheduler is resumed (unsuspended). */
+		xYieldPending = pdTRUE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	configASSERT( pxTimeOut );
+	taskENTER_CRITICAL();
+	{
+		pxTimeOut->xOverflowCount = xNumOfOverflows;
+		pxTimeOut->xTimeOnEntering = xTickCount;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	/* For internal use only as it does not use a critical section. */
+	pxTimeOut->xOverflowCount = xNumOfOverflows;
+	pxTimeOut->xTimeOnEntering = xTickCount;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
+{
+BaseType_t xReturn;
+
+	configASSERT( pxTimeOut );
+	configASSERT( pxTicksToWait );
+
+	taskENTER_CRITICAL();
+	{
+		/* Minor optimisation.  The tick count cannot change in this block. */
+		const TickType_t xConstTickCount = xTickCount;
+		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
+
+		#if( INCLUDE_xTaskAbortDelay == 1 )
+			if( pxCurrentTCB->ucDelayAborted != pdFALSE )
+			{
+				/* The delay was aborted, which is not the same as a time out,
+				but has the same result. */
+				pxCurrentTCB->ucDelayAborted = pdFALSE;
+				xReturn = pdTRUE;
+			}
+			else
+		#endif
+
+		#if ( INCLUDE_vTaskSuspend == 1 )
+			if( *pxTicksToWait == portMAX_DELAY )
+			{
+				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
+				specified is the maximum block time then the task should block
+				indefinitely, and therefore never time out. */
+				xReturn = pdFALSE;
+			}
+			else
+		#endif
+
+		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
+		{
+			/* The tick count is greater than the time at which
+			vTaskSetTimeout() was called, but has also overflowed since
+			vTaskSetTimeOut() was called.  It must have wrapped all the way
+			around and gone past again. This passed since vTaskSetTimeout()
+			was called. */
+			xReturn = pdTRUE;
+		}
+		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
+		{
+			/* Not a genuine timeout. Adjust parameters for time remaining. */
+			*pxTicksToWait -= xElapsedTime;
+			vTaskInternalSetTimeOutState( pxTimeOut );
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			*pxTicksToWait = 0;
+			xReturn = pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskMissedYield( void )
+{
+	xYieldPending = pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
+	{
+	UBaseType_t uxReturn;
+	TCB_t *pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = ( TCB_t * ) xTask;
+			uxReturn = pxTCB->uxTaskNumber;
+		}
+		else
+		{
+			uxReturn = 0U;
+		}
+
+		return uxReturn;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )
+	{
+	TCB_t *pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = ( TCB_t * ) xTask;
+			pxTCB->uxTaskNumber = uxHandle;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+
+/*
+ * -----------------------------------------------------------
+ * The Idle task.
+ * ----------------------------------------------------------
+ *
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION( prvIdleTask, pvParameters )
+{
+	/* Stop warnings. */
+	( void ) pvParameters;
+
+	/** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE
+	SCHEDULER IS STARTED. **/
+
+	/* In case a task that has a secure context deletes itself, in which case
+	the idle task is responsible for deleting the task's secure context, if
+	any. */
+	portTASK_CALLS_SECURE_FUNCTIONS();
+
+	for( ;; )
+	{
+		/* See if any tasks have deleted themselves - if so then the idle task
+		is responsible for freeing the deleted task's TCB and stack. */
+		prvCheckTasksWaitingTermination();
+
+		#if ( configUSE_PREEMPTION == 0 )
+		{
+			/* If we are not using preemption we keep forcing a task switch to
+			see if any other task has become available.  If we are using
+			preemption we don't need to do this as any task becoming available
+			will automatically get the processor anyway. */
+			taskYIELD();
+		}
+		#endif /* configUSE_PREEMPTION */
+
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
+		{
+			/* When using preemption tasks of equal priority will be
+			timesliced.  If a task that is sharing the idle priority is ready
+			to run then the idle task should yield before the end of the
+			timeslice.
+
+			A critical region is not required here as we are just reading from
+			the list, and an occasional incorrect value will not matter.  If
+			the ready list at the idle priority contains more than one task
+			then a task other than the idle task is ready to execute. */
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
+			{
+				taskYIELD();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
+
+		#if ( configUSE_IDLE_HOOK == 1 )
+		{
+			extern void vApplicationIdleHook( void );
+
+			/* Call the user defined function from within the idle task.  This
+			allows the application designer to add background functionality
+			without the overhead of a separate task.
+			NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+			CALL A FUNCTION THAT MIGHT BLOCK. */
+			vApplicationIdleHook();
+		}
+		#endif /* configUSE_IDLE_HOOK */
+
+		/* This conditional compilation should use inequality to 0, not equality
+		to 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
+		user defined low power mode	implementations require
+		configUSE_TICKLESS_IDLE to be set to a value other than 1. */
+		#if ( configUSE_TICKLESS_IDLE != 0 )
+		{
+		TickType_t xExpectedIdleTime;
+
+			/* It is not desirable to suspend then resume the scheduler on
+			each iteration of the idle task.  Therefore, a preliminary
+			test of the expected idle time is performed without the
+			scheduler suspended.  The result here is not necessarily
+			valid. */
+			xExpectedIdleTime = prvGetExpectedIdleTime();
+
+			if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+			{
+				vTaskSuspendAll();
+				{
+					/* Now the scheduler is suspended, the expected idle
+					time can be sampled again, and this time its value can
+					be used. */
+					configASSERT( xNextTaskUnblockTime >= xTickCount );
+					xExpectedIdleTime = prvGetExpectedIdleTime();
+
+					/* Define the following macro to set xExpectedIdleTime to 0
+					if the application does not want
+					portSUPPRESS_TICKS_AND_SLEEP() to be called. */
+					configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
+
+					if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+					{
+						traceLOW_POWER_IDLE_BEGIN();
+						portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
+						traceLOW_POWER_IDLE_END();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICKLESS_IDLE */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE != 0 )
+
+	eSleepModeStatus eTaskConfirmSleepModeStatus( void )
+	{
+	/* The idle task exists in addition to the application tasks. */
+	const UBaseType_t uxNonApplicationTasks = 1;
+	eSleepModeStatus eReturn = eStandardSleep;
+
+		if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
+		{
+			/* A task was made ready while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else if( xYieldPending != pdFALSE )
+		{
+			/* A yield was pended while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else
+		{
+			/* If all the tasks are in the suspended list (which might mean they
+			have an infinite block time rather than actually being suspended)
+			then it is safe to turn all clocks off and just wait for external
+			interrupts. */
+			if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
+			{
+				eReturn = eNoTasksWaitingTimeout;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return eReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )
+	{
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToSet );
+			pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
+		}
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )
+	{
+	void *pvReturn = NULL;
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+			pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
+		}
+		else
+		{
+			pvReturn = NULL;
+		}
+
+		return pvReturn;
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( portUSING_MPU_WRAPPERS == 1 )
+
+	void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )
+	{
+	TCB_t *pxTCB;
+
+		/* If null is passed in here then we are modifying the MPU settings of
+		the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTaskToModify );
+
+		vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseTaskLists( void )
+{
+UBaseType_t uxPriority;
+
+	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
+	{
+		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
+	}
+
+	vListInitialise( &xDelayedTaskList1 );
+	vListInitialise( &xDelayedTaskList2 );
+	vListInitialise( &xPendingReadyList );
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		vListInitialise( &xTasksWaitingTermination );
+	}
+	#endif /* INCLUDE_vTaskDelete */
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		vListInitialise( &xSuspendedTaskList );
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+
+	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
+	using list2. */
+	pxDelayedTaskList = &xDelayedTaskList1;
+	pxOverflowDelayedTaskList = &xDelayedTaskList2;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTasksWaitingTermination( void )
+{
+
+	/** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		TCB_t *pxTCB;
+
+		/* uxDeletedTasksWaitingCleanUp is used to prevent vTaskSuspendAll()
+		being called too often in the idle task. */
+		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+		{
+			taskENTER_CRITICAL();
+			{
+				pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				--uxCurrentNumberOfTasks;
+				--uxDeletedTasksWaitingCleanUp;
+			}
+			taskEXIT_CRITICAL();
+
+			prvDeleteTCB( pxTCB );
+		}
+	}
+	#endif /* INCLUDE_vTaskDelete */
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )
+	{
+	TCB_t *pxTCB;
+
+		/* xTask is NULL then get the state of the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;
+		pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName [ 0 ] );
+		pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
+		pxTaskStatus->pxStackBase = pxTCB->pxStack;
+		pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
+
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
+		}
+		#else
+		{
+			pxTaskStatus->uxBasePriority = 0;
+		}
+		#endif
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+			pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
+		}
+		#else
+		{
+			pxTaskStatus->ulRunTimeCounter = 0;
+		}
+		#endif
+
+		/* Obtaining the task state is a little fiddly, so is only done if the
+		value of eState passed into this function is eInvalid - otherwise the
+		state is just set to whatever is passed in. */
+		if( eState != eInvalid )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				pxTaskStatus->eCurrentState = eRunning;
+			}
+			else
+			{
+				pxTaskStatus->eCurrentState = eState;
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* If the task is in the suspended list then there is a
+					chance it is actually just blocked indefinitely - so really
+					it should be reported as being in the Blocked state. */
+					if( eState == eSuspended )
+					{
+						vTaskSuspendAll();
+						{
+							if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+							{
+								pxTaskStatus->eCurrentState = eBlocked;
+							}
+						}
+						( void ) xTaskResumeAll();
+					}
+				}
+				#endif /* INCLUDE_vTaskSuspend */
+			}
+		}
+		else
+		{
+			pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );
+		}
+
+		/* Obtaining the stack space takes some time, so the xGetFreeStackSpace
+		parameter is provided to allow it to be skipped. */
+		if( xGetFreeStackSpace != pdFALSE )
+		{
+			#if ( portSTACK_GROWTH > 0 )
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
+			}
+			#else
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
+			}
+			#endif
+		}
+		else
+		{
+			pxTaskStatus->usStackHighWaterMark = 0;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )
+	{
+	configLIST_VOLATILE TCB_t *pxNextTCB, *pxFirstTCB;
+	UBaseType_t uxTask = 0;
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
+
+			/* Populate an TaskStatus_t structure within the
+			pxTaskStatusArray array for each task that is referenced from
+			pxList.  See the definition of TaskStatus_t in task.h for the
+			meaning of each TaskStatus_t structure member. */
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
+				vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
+				uxTask++;
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+
+	static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
+	{
+	uint32_t ulCount = 0U;
+
+		while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
+		{
+			pucStackByte -= portSTACK_GROWTH;
+			ulCount++;
+		}
+
+		ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
+
+		return ( uint16_t ) ulCount;
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+	UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	UBaseType_t uxReturn;
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB )
+	{
+		/* This call is required specifically for the TriCore port.  It must be
+		above the vPortFree() calls.  The call is also used by ports/demos that
+		want to allocate and clean RAM statically. */
+		portCLEAN_UP_TCB( pxTCB );
+
+		/* Free up the memory allocated by the scheduler for the task.  It is up
+		to the task to free any memory allocated at the application level. */
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			_reclaim_reent( &( pxTCB->xNewLib_reent ) );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+		{
+			/* The task can only have been allocated dynamically - free both
+			the stack and TCB. */
+			vPortFree( pxTCB->pxStack );
+			vPortFree( pxTCB );
+		}
+		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */
+		{
+			/* The task could have been allocated statically or dynamically, so
+			check what was statically allocated before trying to free the
+			memory. */
+			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
+			{
+				/* Both the stack and TCB were allocated dynamically, so both
+				must be freed. */
+				vPortFree( pxTCB->pxStack );
+				vPortFree( pxTCB );
+			}
+			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
+			{
+				/* Only the stack was statically allocated, so the TCB is the
+				only memory that must be freed. */
+				vPortFree( pxTCB );
+			}
+			else
+			{
+				/* Neither the stack nor the TCB were allocated dynamically, so
+				nothing needs to be freed. */
+				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+static void prvResetNextTaskUnblockTime( void )
+{
+TCB_t *pxTCB;
+
+	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+	{
+		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
+		the maximum possible value so it is	extremely unlikely that the
+		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
+		there is an item in the delayed list. */
+		xNextTaskUnblockTime = portMAX_DELAY;
+	}
+	else
+	{
+		/* The new current delayed list is not empty, get the value of
+		the item at the head of the delayed list.  This is the time at
+		which the task at the head of the delayed list should be removed
+		from the Blocked state. */
+		( pxTCB ) = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
+		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+	TaskHandle_t xTaskGetCurrentTaskHandle( void )
+	{
+	TaskHandle_t xReturn;
+
+		/* A critical section is not required as this is not called from
+		an interrupt and the current TCB will always be the same for any
+		individual execution thread. */
+		xReturn = pxCurrentTCB;
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xTaskGetSchedulerState( void )
+	{
+	BaseType_t xReturn;
+
+		if( xSchedulerRunning == pdFALSE )
+		{
+			xReturn = taskSCHEDULER_NOT_STARTED;
+		}
+		else
+		{
+			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+			{
+				xReturn = taskSCHEDULER_RUNNING;
+			}
+			else
+			{
+				xReturn = taskSCHEDULER_SUSPENDED;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxMutexHolderTCB = ( TCB_t * ) pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		/* If the mutex was given back by an interrupt while the queue was
+		locked then the mutex holder might now be NULL.  _RB_ Is this still
+		needed as interrupts can no longer use mutexes? */
+		if( pxMutexHolder != NULL )
+		{
+			/* If the holder of the mutex has a priority below the priority of
+			the task attempting to obtain the mutex then it will temporarily
+			inherit the priority of the task attempting to obtain the mutex. */
+			if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
+			{
+				/* Adjust the mutex holder state to account for its new
+				priority.  Only reset the event list item value if the value is
+				not being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task being modified is in the ready state it will need
+				to be moved into a new list. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
+				{
+					if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						taskRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Inherit the priority before being moved into the new list. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+					prvAddTaskToReadyList( pxMutexHolderTCB );
+				}
+				else
+				{
+					/* Just inherit the priority. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+				}
+
+				traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
+
+				/* Inheritance occurred. */
+				xReturn = pdTRUE;
+			}
+			else
+			{
+				if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
+				{
+					/* The base priority of the mutex holder is lower than the
+					priority of the task attempting to take the mutex, but the
+					current priority of the mutex holder is not lower than the
+					priority of the task attempting to take the mutex.
+					Therefore the mutex holder must have already inherited a
+					priority, but inheritance would have occurred if that had
+					not been the case. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* A task can only have an inherited priority if it holds the mutex.
+			If the mutex is held by a task then it cannot be given from an
+			interrupt, and if a mutex is given by the holding task then it must
+			be the running state task. */
+			configASSERT( pxTCB == pxCurrentTCB );
+			configASSERT( pxTCB->uxMutexesHeld );
+			( pxTCB->uxMutexesHeld )--;
+
+			/* Has the holder of the mutex inherited the priority of another
+			task? */
+			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
+			{
+				/* Only disinherit if no other mutexes are held. */
+				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
+				{
+					/* A task can only have an inherited priority if it holds
+					the mutex.  If the mutex is held by a task then it cannot be
+					given from an interrupt, and if a mutex is given by the
+					holding task then it must be the running state task.  Remove
+					the holding task from the ready list. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Disinherit the priority before adding the task into the
+					new	ready list. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					pxTCB->uxPriority = pxTCB->uxBasePriority;
+
+					/* Reset the event list item value.  It cannot be in use for
+					any other purpose if this task is running, and it must be
+					running to give back the mutex. */
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* Return true to indicate that a context switch is required.
+					This is only actually required in the corner case whereby
+					multiple mutexes were held and the mutexes were given back
+					in an order different to that in which they were taken.
+					If a context switch did not occur when the first mutex was
+					returned, even if a task was waiting on it, then a context
+					switch should occur when the last mutex is returned whether
+					a task is waiting on it or not. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
+	{
+	TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;
+	UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
+	const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* If pxMutexHolder is not NULL then the holder must hold at least
+			one mutex. */
+			configASSERT( pxTCB->uxMutexesHeld );
+
+			/* Determine the priority to which the priority of the task that
+			holds the mutex should be set.  This will be the greater of the
+			holding task's base priority and the priority of the highest
+			priority task that is waiting to obtain the mutex. */
+			if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
+			{
+				uxPriorityToUse = uxHighestPriorityWaitingTask;
+			}
+			else
+			{
+				uxPriorityToUse = pxTCB->uxBasePriority;
+			}
+
+			/* Does the priority need to change? */
+			if( pxTCB->uxPriority != uxPriorityToUse )
+			{
+				/* Only disinherit if no other mutexes are held.  This is a
+				simplification in the priority inheritance implementation.  If
+				the task that holds the mutex is also holding other mutexes then
+				the other mutexes may have caused the priority inheritance. */
+				if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
+				{
+					/* If a task has timed out because it already holds the
+					mutex it was trying to obtain then it cannot of inherited
+					its own priority. */
+					configASSERT( pxTCB != pxCurrentTCB );
+
+					/* Disinherit the priority, remembering the previous
+					priority to facilitate determining the subject task's
+					state. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					uxPriorityUsedOnEntry = pxTCB->uxPriority;
+					pxTCB->uxPriority = uxPriorityToUse;
+
+					/* Only reset the event list item value if the value is not
+					being used for anything else. */
+					if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+					{
+						listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* If the running task is not the task that holds the mutex
+					then the task that holds the mutex could be in either the
+					Ready, Blocked or Suspended states.  Only remove the task
+					from its current state list if it is in the Ready state as
+					the task's priority is going to change and there is one
+					Ready list per priority. */
+					if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+					{
+						if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+						{
+							taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+
+						prvAddTaskToReadyList( pxTCB );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskEnterCritical( void )
+	{
+		portDISABLE_INTERRUPTS();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			( pxCurrentTCB->uxCriticalNesting )++;
+
+			/* This is not the interrupt safe version of the enter critical
+			function so	assert() if it is being called from an interrupt
+			context.  Only API functions that end in "FromISR" can be used in an
+			interrupt.  Only assert if the critical nesting count is 1 to
+			protect against recursive calls if the assert function also uses a
+			critical section. */
+			if( pxCurrentTCB->uxCriticalNesting == 1 )
+			{
+				portASSERT_IF_IN_ISR();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskExitCritical( void )
+	{
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxCurrentTCB->uxCriticalNesting > 0U )
+			{
+				( pxCurrentTCB->uxCriticalNesting )--;
+
+				if( pxCurrentTCB->uxCriticalNesting == 0U )
+				{
+					portENABLE_INTERRUPTS();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )
+	{
+	size_t x;
+
+		/* Start by copying the entire string. */
+		strcpy( pcBuffer, pcTaskName );
+
+		/* Pad the end of the string with spaces to ensure columns line up when
+		printed out. */
+		for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )
+		{
+			pcBuffer[ x ] = ' ';
+		}
+
+		/* Terminate. */
+		pcBuffer[ x ] = 0x00;
+
+		/* Return the new end of string. */
+		return &( pcBuffer[ x ] );
+	}
+
+#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskList( char * pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	volatile UBaseType_t uxArraySize, x;
+	char cStatus;
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+		 * uxTaskGetSystemState() output into a human readable table that
+		 * displays task names, states and stack usage.
+		 *
+		 * vTaskList() has a dependency on the sprintf() C library function that
+		 * might bloat the code size, use a lot of stack, and provide different
+		 * results on different platforms.  An alternative, tiny, third party,
+		 * and limited functionality implementation of sprintf() is provided in
+		 * many of the FreeRTOS/Demo sub-directories in a file called
+		 * printf-stdarg.c (note printf-stdarg.c does not provide a full
+		 * snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskList().
+		 */
+
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  if
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
+
+			/* Create a human readable table from the binary data. */
+			for( x = 0; x < uxArraySize; x++ )
+			{
+				switch( pxTaskStatusArray[ x ].eCurrentState )
+				{
+					case eRunning:		cStatus = tskRUNNING_CHAR;
+										break;
+
+					case eReady:		cStatus = tskREADY_CHAR;
+										break;
+
+					case eBlocked:		cStatus = tskBLOCKED_CHAR;
+										break;
+
+					case eSuspended:	cStatus = tskSUSPENDED_CHAR;
+										break;
+
+					case eDeleted:		cStatus = tskDELETED_CHAR;
+										break;
+
+					default:			/* Should not get here, but it is included
+										to prevent static checking errors. */
+										cStatus = 0x00;
+										break;
+				}
+
+				/* Write the task name to the string, padding with spaces so it
+				can be printed in tabular form more easily. */
+				pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+				/* Write the rest of the string. */
+				sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber );
+				pcWriteBuffer += strlen( pcWriteBuffer );
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	volatile UBaseType_t uxArraySize, x;
+	uint32_t ulTotalTime, ulStatsAsPercentage;
+
+		#if( configUSE_TRACE_FACILITY != 1 )
+		{
+			#error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
+		}
+		#endif
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
+		 * of the uxTaskGetSystemState() output into a human readable table that
+		 * displays the amount of time each task has spent in the Running state
+		 * in both absolute and percentage terms.
+		 *
+		 * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
+		 * function that might bloat the code size, use a lot of stack, and
+		 * provide different results on different platforms.  An alternative,
+		 * tiny, third party, and limited functionality implementation of
+		 * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
+		 * a file called printf-stdarg.c (note printf-stdarg.c does not provide
+		 * a full snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskGetRunTimeStats().
+		 */
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  If
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
+
+			/* For percentage calculations. */
+			ulTotalTime /= 100UL;
+
+			/* Avoid divide by zero errors. */
+			if( ulTotalTime > 0 )
+			{
+				/* Create a human readable table from the binary data. */
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					/* What percentage of the total run time has the task used?
+					This will always be rounded down to the nearest integer.
+					ulTotalRunTimeDiv100 has already been divided by 100. */
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
+
+					/* Write the task name to the string, padding with
+					spaces so it can be printed in tabular form more
+					easily. */
+					pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage );
+						}
+						#endif
+					}
+					else
+					{
+						/* If the percentage is zero here then the task has
+						consumed less than 1% of the total run time. */
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter );
+						}
+						#endif
+					}
+
+					pcWriteBuffer += strlen( pcWriteBuffer );
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+TickType_t uxTaskResetEventItemValue( void )
+{
+TickType_t uxReturn;
+
+	uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
+
+	/* Reset the event list item to its normal value - so it can be used with
+	queues and semaphores. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	void *pvTaskIncrementMutexHeldCount( void )
+	{
+		/* If xSemaphoreCreateMutex() is called before any tasks have been created
+		then pxCurrentTCB will be NULL. */
+		if( pxCurrentTCB != NULL )
+		{
+			( pxCurrentTCB->uxMutexesHeld )++;
+		}
+
+		return pxCurrentTCB;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )
+	{
+	uint32_t ulReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if the notification count is not already non-zero. */
+			if( pxCurrentTCB->ulNotifiedValue == 0UL )
+			{
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_TAKE_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_TAKE();
+			ulReturn = pxCurrentTCB->ulNotifiedValue;
+
+			if( ulReturn != 0UL )
+			{
+				if( xClearCountOnExit != pdFALSE )
+				{
+					pxCurrentTCB->ulNotifiedValue = 0UL;
+				}
+				else
+				{
+					pxCurrentTCB->ulNotifiedValue = ulReturn - ( uint32_t ) 1;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return ulReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if a notification is not already pending. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* Clear bits in the task's notification value as bits may get
+				set	by the notifying task or interrupt.  This can be used to
+				clear the value to zero. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;
+
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_WAIT_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_WAIT();
+
+			if( pulNotificationValue != NULL )
+			{
+				/* Output the current notification value, which may or may not
+				have changed. */
+				*pulNotificationValue = pxCurrentTCB->ulNotifiedValue;
+			}
+
+			/* If ucNotifyValue is set then either the task never entered the
+			blocked state (because a notification was already pending) or the
+			task unblocked because of a notification.  Otherwise the task
+			unblocked because of a timeout. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* A notification was not received. */
+				xReturn = pdFALSE;
+			}
+			else
+			{
+				/* A notification was already pending or a notification was
+				received while the task was waiting. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;
+				xReturn = pdTRUE;
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
+	{
+	TCB_t * pxTCB;
+	BaseType_t xReturn = pdPASS;
+	uint8_t ucOriginalNotifyState;
+
+		configASSERT( xTaskToNotify );
+		pxTCB = ( TCB_t * ) xTaskToNotify;
+
+		taskENTER_CRITICAL();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction:
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+			}
+
+			traceTASK_NOTIFY();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				prvAddTaskToReadyList( pxTCB );
+
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				#if( configUSE_TICKLESS_IDLE != 0 )
+				{
+					/* If a task is blocked waiting for a notification then
+					xNextTaskUnblockTime might be set to the blocked task's time
+					out time.  If the task is unblocked for a reason other than
+					a timeout xNextTaskUnblockTime is normally left unchanged,
+					because it will automatically get reset to a new value when
+					the tick count equals xNextTaskUnblockTime.  However if
+					tickless idling is used it might be more important to enter
+					sleep mode at the earliest possible time - so reset
+					xNextTaskUnblockTime here to ensure it is updated at the
+					earliest possible time. */
+					prvResetNextTaskUnblockTime();
+				}
+				#endif
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	BaseType_t xReturn = pdPASS;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = ( TCB_t * ) xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction :
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+			}
+
+			traceTASK_NOTIFY_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+					else
+					{
+						/* Mark that a yield is pending in case the user is not
+						using the "xHigherPriorityTaskWoken" parameter to an ISR
+						safe FreeRTOS function. */
+						xYieldPending = pdTRUE;
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = ( TCB_t * ) xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			/* 'Giving' is equivalent to incrementing a count in a counting
+			semaphore. */
+			( pxTCB->ulNotifiedValue )++;
+
+			traceTASK_NOTIFY_GIVE_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+					else
+					{
+						/* Mark that a yield is pending in case the user is not
+						using the "xHigherPriorityTaskWoken" parameter in an ISR
+						safe FreeRTOS function. */
+						xYieldPending = pdTRUE;
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	BaseType_t xReturn;
+
+		/* If null is passed in here then it is the calling task that is having
+		its notification state cleared. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		taskENTER_CRITICAL();
+		{
+			if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED )
+			{
+				pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				xReturn = pdPASS;
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
+{
+TickType_t xTimeToWake;
+const TickType_t xConstTickCount = xTickCount;
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		/* About to enter a delayed list, so ensure the ucDelayAborted flag is
+		reset to pdFALSE so it can be detected as having been set to pdTRUE
+		when the task leaves the Blocked state. */
+		pxCurrentTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Remove the task from the ready list before adding it to the blocked list
+	as the same list item is used for both lists. */
+	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+	{
+		/* The current task must be in a ready list, so there is no need to
+		check, and the port reset macro can be called directly. */
+		portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
+		{
+			/* Add the task to the suspended task list instead of a delayed task
+			list to ensure it is not woken by a timing event.  It will block
+			indefinitely. */
+			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* Calculate the time at which the task should be woken if the event
+			does not occur.  This may overflow but this doesn't matter, the
+			kernel will manage it correctly. */
+			xTimeToWake = xConstTickCount + xTicksToWait;
+
+			/* The list item will be inserted in wake time order. */
+			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+			if( xTimeToWake < xConstTickCount )
+			{
+				/* Wake time has overflowed.  Place this item in the overflow
+				list. */
+				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+			}
+			else
+			{
+				/* The wake time has not overflowed, so the current block list
+				is used. */
+				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+				/* If the task entering the blocked state was placed at the
+				head of the list of blocked tasks then xNextTaskUnblockTime
+				needs to be updated too. */
+				if( xTimeToWake < xNextTaskUnblockTime )
+				{
+					xNextTaskUnblockTime = xTimeToWake;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+	}
+	#else /* INCLUDE_vTaskSuspend */
+	{
+		/* Calculate the time at which the task should be woken if the event
+		does not occur.  This may overflow but this doesn't matter, the kernel
+		will manage it correctly. */
+		xTimeToWake = xConstTickCount + xTicksToWait;
+
+		/* The list item will be inserted in wake time order. */
+		listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+		if( xTimeToWake < xConstTickCount )
+		{
+			/* Wake time has overflowed.  Place this item in the overflow list. */
+			vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* The wake time has not overflowed, so the current block list is used. */
+			vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+			/* If the task entering the blocked state was placed at the head of the
+			list of blocked tasks then xNextTaskUnblockTime needs to be updated
+			too. */
+			if( xTimeToWake < xNextTaskUnblockTime )
+			{
+				xNextTaskUnblockTime = xTimeToWake;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
+		( void ) xCanBlockIndefinitely;
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+}
+
+/* Code below here allows additional code to be inserted into this source file,
+especially where access to file scope functions and data is needed (for example
+when performing module tests). */
+
+#ifdef FREERTOS_MODULE_TEST
+	#include "tasks_test_access_functions.h"
+#endif
+
+
+#if( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )
+
+	#include "freertos_tasks_c_additions.h"
+
+	static void freertos_tasks_c_additions_init( void )
+	{
+		#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+			FREERTOS_TASKS_C_ADDITIONS_INIT();
+		#endif
+	}
+
+#endif
+
+
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/timers.c b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/timers.c
new file mode 100644
index 00000000..002dd8ba
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/FreeRTOS/Source/timers.c
@@ -0,0 +1,1076 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
+	#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
+#endif
+
+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
+header files above, but not in this file, in order to generate the correct
+privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  This #if is closed at the very bottom
+of this file.  If you want to include software timer functionality then ensure
+configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#if ( configUSE_TIMERS == 1 )
+
+/* Misc definitions. */
+#define tmrNO_DELAY		( TickType_t ) 0U
+
+/* The name assigned to the timer service task.  This can be overridden by
+defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configTIMER_SERVICE_TASK_NAME
+	#define configTIMER_SERVICE_TASK_NAME "Tmr Svc"
+#endif
+
+/* The definition of the timers themselves. */
+typedef struct tmrTimerControl
+{
+	const char				*pcTimerName;		/*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	ListItem_t				xTimerListItem;		/*<< Standard linked list item as used by all kernel features for event management. */
+	TickType_t				xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */
+	UBaseType_t				uxAutoReload;		/*<< Set to pdTRUE if the timer should be automatically restarted once expired.  Set to pdFALSE if the timer is, in effect, a one-shot timer. */
+	void 					*pvTimerID;			/*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
+	TimerCallbackFunction_t	pxCallbackFunction;	/*<< The function that will be called when the timer expires. */
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t			uxTimerNumber;		/*<< An ID assigned by trace tools such as FreeRTOS+Trace */
+	#endif
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t 			ucStaticallyAllocated; /*<< Set to pdTRUE if the timer was created statically so no attempt is made to free the memory again if the timer is later deleted. */
+	#endif
+} xTIMER;
+
+/* The old xTIMER name is maintained above then typedefed to the new Timer_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xTIMER Timer_t;
+
+/* The definition of messages that can be sent and received on the timer queue.
+Two types of message can be queued - messages that manipulate a software timer,
+and messages that request the execution of a non-timer related callback.  The
+two message types are defined in two separate structures, xTimerParametersType
+and xCallbackParametersType respectively. */
+typedef struct tmrTimerParameters
+{
+	TickType_t			xMessageValue;		/*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */
+	Timer_t *			pxTimer;			/*<< The timer to which the command will be applied. */
+} TimerParameter_t;
+
+
+typedef struct tmrCallbackParameters
+{
+	PendedFunction_t	pxCallbackFunction;	/* << The callback function to execute. */
+	void *pvParameter1;						/* << The value that will be used as the callback functions first parameter. */
+	uint32_t ulParameter2;					/* << The value that will be used as the callback functions second parameter. */
+} CallbackParameters_t;
+
+/* The structure that contains the two message types, along with an identifier
+that is used to determine which message type is valid. */
+typedef struct tmrTimerQueueMessage
+{
+	BaseType_t			xMessageID;			/*<< The command being sent to the timer service task. */
+	union
+	{
+		TimerParameter_t xTimerParameters;
+
+		/* Don't include xCallbackParameters if it is not going to be used as
+		it makes the structure (and therefore the timer queue) larger. */
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+			CallbackParameters_t xCallbackParameters;
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+	} u;
+} DaemonTaskMessage_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+
+/* The list in which active timers are stored.  Timers are referenced in expire
+time order, with the nearest expiry time at the front of the list.  Only the
+timer service task is allowed to access these lists. */
+PRIVILEGED_DATA static List_t xActiveTimerList1 = {0};
+PRIVILEGED_DATA static List_t xActiveTimerList2 = {0};
+PRIVILEGED_DATA static List_t *pxCurrentTimerList = NULL;
+PRIVILEGED_DATA static List_t *pxOverflowTimerList = NULL;
+
+/* A queue that is used to send commands to the timer service task. */
+PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
+PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	/* If static allocation is supported then the application must provide the
+	following callback function - which enables the application to optionally
+	provide the memory that will be used by the timer task as the task's stack
+	and TCB. */
+	extern void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );
+
+#endif
+
+/*
+ * Initialise the infrastructure used by the timer service task if it has not
+ * been initialised already.
+ */
+static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The timer service task (daemon).  Timer functionality is controlled by this
+ * task.  Other tasks communicate with the timer service task using the
+ * xTimerQueue queue.
+ */
+static void prvTimerTask( void *pvParameters ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by the timer service task to interpret and process a command it
+ * received on the timer queue.
+ */
+static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
+ * depending on if the expire time causes a timer counter overflow.
+ */
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;
+
+/*
+ * An active timer has reached its expire time.  Reload the timer if it is an
+ * auto reload timer, then call its callback.
+ */
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
+
+/*
+ * The tick count has overflowed.  Switch the timer lists after ensuring the
+ * current timer list does not still reference some timers.
+ */
+static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
+ * if a tick count overflow occurred since prvSampleTimeNow() was last called.
+ */
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the timer list contains any active timers then return the expire time of
+ * the timer that will expire first and set *pxListWasEmpty to false.  If the
+ * timer list does not contain any timers then return 0 and set *pxListWasEmpty
+ * to pdTRUE.
+ */
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a timer has expired, process it.  Otherwise, block the timer service task
+ * until either a timer does expire or a command is received.
+ */
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a Timer_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerCreateTimerTask( void )
+{
+BaseType_t xReturn = pdFAIL;
+
+	/* This function is called when the scheduler is started if
+	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
+	timer service task has been created/initialised.  If timers have already
+	been created then the initialisation will already have been performed. */
+	prvCheckForValidListAndQueue();
+
+	if( xTimerQueue != NULL )
+	{
+		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+		{
+			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
+			StackType_t *pxTimerTaskStackBuffer = NULL;
+			uint32_t ulTimerTaskStackSize;
+
+			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
+													configTIMER_SERVICE_TASK_NAME,
+													ulTimerTaskStackSize,
+													NULL,
+													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+													pxTimerTaskStackBuffer,
+													pxTimerTaskTCBBuffer );
+
+			if( xTimerTaskHandle != NULL )
+			{
+				xReturn = pdPASS;
+			}
+		}
+		#else
+		{
+			xReturn = xTaskCreate(	prvTimerTask,
+									configTIMER_SERVICE_TASK_NAME,
+									configTIMER_TASK_STACK_DEPTH,
+									NULL,
+									( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+									&xTimerTaskHandle );
+		}
+		#endif /* configSUPPORT_STATIC_ALLOCATION */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	configASSERT( xReturn );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction )
+	{
+	Timer_t *pxNewTimer;
+
+		pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) );
+
+		if( pxNewTimer != NULL )
+		{
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Timers can be created statically or dynamically, so note this
+				timer was created dynamically in case the timer is later
+				deleted. */
+				pxNewTimer->ucStaticallyAllocated = pdFALSE;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer )
+	{
+	Timer_t *pxNewTimer;
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTimer_t equals the size of the real timer
+			structure. */
+			volatile size_t xSize = sizeof( StaticTimer_t );
+			configASSERT( xSize == sizeof( Timer_t ) );
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* A pointer to a StaticTimer_t structure MUST be provided, use it. */
+		configASSERT( pxTimerBuffer );
+		pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+
+		if( pxNewTimer != NULL )
+		{
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Timers can be created statically or dynamically so note this
+				timer was created statically in case it is later deleted. */
+				pxNewTimer->ucStaticallyAllocated = pdTRUE;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer )
+{
+	/* 0 is not a valid value for xTimerPeriodInTicks. */
+	configASSERT( ( xTimerPeriodInTicks > 0 ) );
+
+	if( pxNewTimer != NULL )
+	{
+		/* Ensure the infrastructure used by the timer service task has been
+		created/initialised. */
+		prvCheckForValidListAndQueue();
+
+		/* Initialise the timer structure members using the function
+		parameters. */
+		pxNewTimer->pcTimerName = pcTimerName;
+		pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
+		pxNewTimer->uxAutoReload = uxAutoReload;
+		pxNewTimer->pvTimerID = pvTimerID;
+		pxNewTimer->pxCallbackFunction = pxCallbackFunction;
+		vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
+		traceTIMER_CREATE( pxNewTimer );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
+{
+BaseType_t xReturn = pdFAIL;
+DaemonTaskMessage_t xMessage;
+
+	configASSERT( xTimer );
+
+	/* Send a message to the timer service task to perform a particular action
+	on a particular timer definition. */
+	if( xTimerQueue != NULL )
+	{
+		/* Send a command to the timer service task to start the xTimer timer. */
+		xMessage.xMessageID = xCommandID;
+		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+		xMessage.u.xTimerParameters.pxTimer = ( Timer_t * ) xTimer;
+
+		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
+		{
+			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+			}
+			else
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
+			}
+		}
+		else
+		{
+			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+		}
+
+		traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
+{
+	/* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
+	started, then xTimerTaskHandle will be NULL. */
+	configASSERT( ( xTimerTaskHandle != NULL ) );
+	return xTimerTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
+{
+Timer_t *pxTimer = ( Timer_t * ) xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->xTimerPeriodInTicks;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
+{
+Timer_t * pxTimer = ( Timer_t * ) xTimer;
+TickType_t xReturn;
+
+	configASSERT( xTimer );
+	xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+Timer_t *pxTimer = ( Timer_t * ) xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->pcTimerName;
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
+{
+BaseType_t xResult;
+Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+	/* Remove the timer from the list of active timers.  A check has already
+	been performed to ensure the list is not empty. */
+	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+	traceTIMER_EXPIRED( pxTimer );
+
+	/* If the timer is an auto reload timer then calculate the next
+	expiry time and re-insert the timer in the list of active timers. */
+	if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
+	{
+		/* The timer is inserted into a list using a time relative to anything
+		other than the current time.  It will therefore be inserted into the
+		correct list relative to the time this task thinks it is now. */
+		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
+		{
+			/* The timer expired before it was added to the active timer
+			list.  Reload it now.  */
+			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+			configASSERT( xResult );
+			( void ) xResult;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Call the timer callback. */
+	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+}
+/*-----------------------------------------------------------*/
+
+static void prvTimerTask( void *pvParameters )
+{
+TickType_t xNextExpireTime;
+BaseType_t xListWasEmpty;
+
+	/* Just to avoid compiler warnings. */
+	( void ) pvParameters;
+
+	#if( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )
+	{
+		extern void vApplicationDaemonTaskStartupHook( void );
+
+		/* Allow the application writer to execute some code in the context of
+		this task at the point the task starts executing.  This is useful if the
+		application includes initialisation code that would benefit from
+		executing after the scheduler has been started. */
+		vApplicationDaemonTaskStartupHook();
+	}
+	#endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
+
+	for( ;; )
+	{
+		/* Query the timers list to see if it contains any timers, and if so,
+		obtain the time at which the next timer will expire. */
+		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
+
+		/* If a timer has expired, process it.  Otherwise, block this task
+		until either a timer does expire, or a command is received. */
+		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
+
+		/* Empty the command queue. */
+		prvProcessReceivedCommands();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
+{
+TickType_t xTimeNow;
+BaseType_t xTimerListsWereSwitched;
+
+	vTaskSuspendAll();
+	{
+		/* Obtain the time now to make an assessment as to whether the timer
+		has expired or not.  If obtaining the time causes the lists to switch
+		then don't process this timer as any timers that remained in the list
+		when the lists were switched will have been processed within the
+		prvSampleTimeNow() function. */
+		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+		if( xTimerListsWereSwitched == pdFALSE )
+		{
+			/* The tick count has not overflowed, has the timer expired? */
+			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
+			{
+				( void ) xTaskResumeAll();
+				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
+			}
+			else
+			{
+				/* The tick count has not overflowed, and the next expire
+				time has not been reached yet.  This task should therefore
+				block to wait for the next expire time or a command to be
+				received - whichever comes first.  The following line cannot
+				be reached unless xNextExpireTime > xTimeNow, except in the
+				case when the current timer list is empty. */
+				if( xListWasEmpty != pdFALSE )
+				{
+					/* The current timer list is empty - is the overflow list
+					also empty? */
+					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
+				}
+
+				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
+
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					/* Yield to wait for either a command to arrive, or the
+					block time to expire.  If a command arrived between the
+					critical section being exited and this yield then the yield
+					will not cause the task to block. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			( void ) xTaskResumeAll();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
+{
+TickType_t xNextExpireTime;
+
+	/* Timers are listed in expiry time order, with the head of the list
+	referencing the task that will expire first.  Obtain the time at which
+	the timer with the nearest expiry time will expire.  If there are no
+	active timers then just set the next expire time to 0.  That will cause
+	this task to unblock when the tick count overflows, at which point the
+	timer lists will be switched and the next expiry time can be
+	re-assessed.  */
+	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
+	if( *pxListWasEmpty == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+	}
+	else
+	{
+		/* Ensure the task unblocks when the tick count rolls over. */
+		xNextExpireTime = ( TickType_t ) 0U;
+	}
+
+	return xNextExpireTime;
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
+{
+TickType_t xTimeNow;
+PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
+
+	xTimeNow = xTaskGetTickCount();
+
+	if( xTimeNow < xLastTime )
+	{
+		prvSwitchTimerLists();
+		*pxTimerListsWereSwitched = pdTRUE;
+	}
+	else
+	{
+		*pxTimerListsWereSwitched = pdFALSE;
+	}
+
+	xLastTime = xTimeNow;
+
+	return xTimeNow;
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
+{
+BaseType_t xProcessTimerNow = pdFALSE;
+
+	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
+	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+
+	if( xNextExpiryTime <= xTimeNow )
+	{
+		/* Has the expiry time elapsed between the command to start/reset a
+		timer was issued, and the time the command was processed? */
+		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+		{
+			/* The time between a command being issued and the command being
+			processed actually exceeds the timers period.  */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+	else
+	{
+		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
+		{
+			/* If, since the command was issued, the tick count has overflowed
+			but the expiry time has not, then the timer must have already passed
+			its expiry time and should be processed immediately. */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+
+	return xProcessTimerNow;
+}
+/*-----------------------------------------------------------*/
+
+static void	prvProcessReceivedCommands( void )
+{
+DaemonTaskMessage_t xMessage;
+Timer_t *pxTimer;
+BaseType_t xTimerListsWereSwitched, xResult;
+TickType_t xTimeNow;
+
+	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+	{
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+		{
+			/* Negative commands are pended function calls rather than timer
+			commands. */
+			if( xMessage.xMessageID < ( BaseType_t ) 0 )
+			{
+				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
+
+				/* The timer uses the xCallbackParameters member to request a
+				callback be executed.  Check the callback is not NULL. */
+				configASSERT( pxCallback );
+
+				/* Call the function. */
+				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+
+		/* Commands that are positive are timer commands rather than pended
+		function calls. */
+		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
+		{
+			/* The messages uses the xTimerParameters member to work on a
+			software timer. */
+			pxTimer = xMessage.u.xTimerParameters.pxTimer;
+
+			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
+			{
+				/* The timer is in a list, remove it. */
+				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
+
+			/* In this case the xTimerListsWereSwitched parameter is not used, but
+			it must be present in the function call.  prvSampleTimeNow() must be
+			called after the message is received from xTimerQueue so there is no
+			possibility of a higher priority task adding a message to the message
+			queue with a time that is ahead of the timer daemon task (because it
+			pre-empted the timer daemon task after the xTimeNow value was set). */
+			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+
+			switch( xMessage.xMessageID )
+			{
+				case tmrCOMMAND_START :
+			    case tmrCOMMAND_START_FROM_ISR :
+			    case tmrCOMMAND_RESET :
+			    case tmrCOMMAND_RESET_FROM_ISR :
+				case tmrCOMMAND_START_DONT_TRACE :
+					/* Start or restart a timer. */
+					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
+					{
+						/* The timer expired before it was added to the active
+						timer list.  Process it now. */
+						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+						traceTIMER_EXPIRED( pxTimer );
+
+						if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
+						{
+							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
+							configASSERT( xResult );
+							( void ) xResult;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					break;
+
+				case tmrCOMMAND_STOP :
+				case tmrCOMMAND_STOP_FROM_ISR :
+					/* The timer has already been removed from the active list.
+					There is nothing to do here. */
+					break;
+
+				case tmrCOMMAND_CHANGE_PERIOD :
+				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
+					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
+					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
+
+					/* The new period does not really have a reference, and can
+					be longer or shorter than the old one.  The command time is
+					therefore set to the current time, and as the period cannot
+					be zero the next expiry time can only be in the future,
+					meaning (unlike for the xTimerStart() case above) there is
+					no fail case that needs to be handled here. */
+					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
+					break;
+
+				case tmrCOMMAND_DELETE :
+					/* The timer has already been removed from the active list,
+					just free up the memory if the memory was dynamically
+					allocated. */
+					#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+					{
+						/* The timer can only have been allocated dynamically -
+						free it again. */
+						vPortFree( pxTimer );
+					}
+					#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+					{
+						/* The timer could have been allocated statically or
+						dynamically, so check before attempting to free the
+						memory. */
+						if( pxTimer->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+						{
+							vPortFree( pxTimer );
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+					break;
+
+				default	:
+					/* Don't expect to get here. */
+					break;
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSwitchTimerLists( void )
+{
+TickType_t xNextExpireTime, xReloadTime;
+List_t *pxTemp;
+Timer_t *pxTimer;
+BaseType_t xResult;
+
+	/* The tick count has overflowed.  The timer lists must be switched.
+	If there are any timers still referenced from the current timer list
+	then they must have expired and should be processed before the lists
+	are switched. */
+	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+		/* Remove the timer from the list. */
+		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
+		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+		traceTIMER_EXPIRED( pxTimer );
+
+		/* Execute its callback, then send a command to restart the timer if
+		it is an auto-reload timer.  It cannot be restarted here as the lists
+		have not yet been switched. */
+		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+
+		if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
+		{
+			/* Calculate the reload value, and if the reload value results in
+			the timer going into the same timer list then it has already expired
+			and the timer should be re-inserted into the current list so it is
+			processed again within this loop.  Otherwise a command should be sent
+			to restart the timer to ensure it is only inserted into a list after
+			the lists have been swapped. */
+			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
+			if( xReloadTime > xNextExpireTime )
+			{
+				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
+				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+				configASSERT( xResult );
+				( void ) xResult;
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxTemp = pxCurrentTimerList;
+	pxCurrentTimerList = pxOverflowTimerList;
+	pxOverflowTimerList = pxTemp;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckForValidListAndQueue( void )
+{
+	/* Check that the list from which active timers are referenced, and the
+	queue used to communicate with the timer service, have been
+	initialised. */
+	taskENTER_CRITICAL();
+	{
+		if( xTimerQueue == NULL )
+		{
+			vListInitialise( &xActiveTimerList1 );
+			vListInitialise( &xActiveTimerList2 );
+			pxCurrentTimerList = &xActiveTimerList1;
+			pxOverflowTimerList = &xActiveTimerList2;
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* The timer queue is allocated statically in case
+				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
+				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+
+				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
+			}
+			#else
+			{
+				xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
+			}
+			#endif
+
+			#if ( configQUEUE_REGISTRY_SIZE > 0 )
+			{
+				if( xTimerQueue != NULL )
+				{
+					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			#endif /* configQUEUE_REGISTRY_SIZE */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
+{
+BaseType_t xTimerIsInActiveList;
+Timer_t *pxTimer = ( Timer_t * ) xTimer;
+
+	configASSERT( xTimer );
+
+	/* Is the timer in the list of active timers? */
+	taskENTER_CRITICAL();
+	{
+		/* Checking to see if it is in the NULL list in effect checks to see if
+		it is referenced from either the current or the overflow timer lists in
+		one go, but the logic has to be reversed, hence the '!'. */
+		xTimerIsInActiveList = ( BaseType_t ) !( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) ); /*lint !e961. Cast is only redundant when NULL is passed into the macro. */
+	}
+	taskEXIT_CRITICAL();
+
+	return xTimerIsInActiveList;
+} /*lint !e818 Can't be pointer to const due to the typedef. */
+/*-----------------------------------------------------------*/
+
+void *pvTimerGetTimerID( const TimerHandle_t xTimer )
+{
+Timer_t * const pxTimer = ( Timer_t * ) xTimer;
+void *pvReturn;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pvReturn = pxTimer->pvTimerID;
+	}
+	taskEXIT_CRITICAL();
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
+{
+Timer_t * const pxTimer = ( Timer_t * ) xTimer;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pxTimer->pvTimerID = pvNewID;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+
+		tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* This function can only be called after a timer has been created or
+		after the scheduler has been started because, until then, the timer
+		queue does not exist. */
+		configASSERT( xTimerQueue );
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+
+		tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
+	{
+		return ( ( Timer_t * ) xTimer )->uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber )
+	{
+		( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  If you want to include software timer
+functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#endif /* configUSE_TIMERS == 1 */
+
+
+
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/sysroot/include/mcs_smo_4th.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/sysroot/include/mcs_smo_4th.h
new file mode 100644
index 00000000..5fb9a507
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/sysroot/include/mcs_smo_4th.h
@@ -0,0 +1,71 @@
+/**
+  * @ Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved.
+  * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
+  * following conditions are met:
+  * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following
+  * disclaimer.
+  * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
+  * following disclaimer in the documentation and/or other materials provided with the distribution.
+  * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote
+  * products derived from this software without specific prior written permission.
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * @file      mcs_smo_4th.h
+  * @author    MCU Algorithm Team
+  * @brief     This file provides functions declaration of 4th order smo module.
+  */
+#ifndef McuMagicTag_MCS_SMO_4TH_H
+#define McuMagicTag_MCS_SMO_4TH_H
+
+#include "mcs_typedef.h"
+#include "mcs_pll.h"
+#include "mcs_filter.h"
+#include "mcs_mtr_param.h"
+
+
+typedef struct {
+    /* Model parameters */
+    float ld;
+    float lq;
+    float rs;
+    float ts;
+    float kd;
+    float kq;
+    float pllBdw;
+    float fcLpf;     /**< The cut-off frequency of First-order LPF for speed (Hz). */
+    float elecAngle;
+    float spdEst;
+    /* Internal variable */
+    AlbeAxis ialbeEst;
+    AlbeAxis ealbeEst;
+    PLL_Handle pll;
+    FOFLT_Handle spdFilter;
+} SMO4TH_Handle;
+
+/**
+ * @brief SMO4TH_Param
+ */
+typedef struct {
+    float kd;
+    float kq;
+    float pllBdw;
+    float fcLpf;
+} SMO4TH_Param;
+
+
+void SMO4TH_Init(SMO4TH_Handle *smo4th, const SMO4TH_Param smo4thParam, const MOTOR_Param mtrParam, float ts);
+
+void SMO4TH_Exec(SMO4TH_Handle *smo4th, const AlbeAxis *ialbeFbk, const AlbeAxis *valbeRef);
+
+void SMO4TH_ParamUpdate(SMO4TH_Handle *smo4th, float kd, float kq, float pllBdw, float fc);
+
+void SMO4TH_Clear(SMO4TH_Handle *smo4th);
+
+void SMO4TH_SetTs(SMO4TH_Handle *smo4th, float ts);
+
+#endif
\ No newline at end of file
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/sysroot/include/nos_task.h b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/sysroot/include/nos_task.h
new file mode 100644
index 00000000..78ff8127
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/sysroot/include/nos_task.h
@@ -0,0 +1,84 @@
+/**
+  * @copyright Copyright (c) 2023, HiSilicon (Shanghai) Technologies Co., Ltd. All rights reserved.
+  * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
+  * following conditions are met:
+  * 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following
+  * disclaimer.
+  * 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
+  * following disclaimer in the documentation and/or other materials provided with the distribution.
+  * 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote
+  * products derived from this software without specific prior written permission.
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+  * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * @file      nos_task.h
+  */
+
+#ifndef NOS_TASK_H
+#define NOS_TASK_H
+
+#define NOS_TASK_PRIORITY_LOWEST 4
+
+typedef void (*NOS_TaskEntryFunc)(void* param);
+typedef void (*NOS_TimerCallBack)(void* param);
+typedef struct {
+    const char *name;
+    NOS_TaskEntryFunc taskEntry;
+    void* param;
+    unsigned int priority; /* scope:[0-NOS_TASK_PRIORITY_LOWEST] */
+    unsigned int stackAddr; /* notice: addr must 16Bytes align && not zero */
+    unsigned int stackSize;
+    unsigned int privateData;
+} NOS_TaskInitParam;
+
+typedef struct {
+    const char *name;
+    unsigned int timeout; // us
+    NOS_TimerCallBack callback;
+    void *callbackParam;
+    unsigned int priority; /* scope:[0-NOS_TASK_PRIORITY_LOWEST] */
+    unsigned int stackSize;
+    unsigned int stackAddr;
+}NOS_TimerTaskInitParam;
+
+typedef struct {
+    unsigned int cyclePerUs;
+    unsigned int usecPerTick;
+    unsigned long long (*getTickFunc)(void);
+}NOS_SysConfig;
+
+int NOS_TaskInit(NOS_SysConfig *config);
+
+int NOS_StartScheduler(void);
+
+int NOS_TaskCreateOnly(NOS_TaskInitParam *initParam, unsigned int *taskId);
+
+int NOS_TaskCreate(NOS_TaskInitParam *initParam, unsigned int *taskId);
+
+int NOS_TaskDelete(unsigned int taskId);
+
+int NOS_TaskSuspend(unsigned int taskId);
+
+int NOS_TaskResume(unsigned int taskId);
+
+int NOS_TaskDelay(unsigned int timeout);
+
+int NOS_TaskPrioritySet(unsigned int taskId, unsigned short priority);
+
+int NOS_TaskPriorityGet(unsigned int taskId, unsigned short *priority);
+
+/* **********************timer task********************* */
+
+int NOS_CreateTimerTask(unsigned int *timerTaskId, NOS_TimerTaskInitParam *timerParam);
+
+/* 接口约束 必须systick启动后. taskId 必须是 NOS_CreateTimerTask 创建的 */
+int NOS_StartTimerTask(unsigned int taskId);
+
+/* 接口约束 必须systick启动后. taskId 必须是 NOS_CreateTimerTask 创建的 */
+int NOS_StopTimerTask(unsigned int taskId);
+
+#endif // NOS_TASK_H
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/sysroot/lib/libmcs_smo_4th.a b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/sysroot/lib/libmcs_smo_4th.a
new file mode 100644
index 0000000000000000000000000000000000000000..2852d63db2444ccc666bce64872c3e6db1d23d31
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diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/sysroot/lib/libnostask.a b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/middleware/thirdparty/sysroot/lib/libnostask.a
new file mode 100644
index 0000000000000000000000000000000000000000..2dd6fe666747eb1f9fcf764a7fa5b2c5130cdde3
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/out/.ninja_log b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/out/.ninja_log
new file mode 100644
index 00000000..e9269a5e
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/out/.ninja_log
@@ -0,0 +1,128 @@
+# ninja log v6
+48	1883	7527790540507621	obj/chip/3065h/chipinit/adc_tsensor/adc_tsensor.o	5bed1584b5733795
+31	9981	7527790540340051	obj/chip/3065h/chipinit/adcinit/adcinit.o	c1fd5a7c31985ec4
+18	12019	7527790540215767	obj/chip/3065h/chipinit/chipinit.o	a7900c9350d633dc
+7	14059	7527790540089516	obj/chip/3065h/startup.o	c0ffba46d4c347fc
+63	14179	7527790540632551	obj/chip/3065h/chipinit/crginit/crginit.o	55f48ce9a3bad228
+114	18239	7527790541147123	obj/chip/3065h/chipinit/flashinit/flashinit.o	5cfd834a16e01a71
+9982	23221	7527790639845028	obj/chip/3065h/chipinit/pgainit/pgainit.o	6b8fc8a61497a9a5
+1884	28243	7527790558871414	obj/chip/3065h/chipinit/nosinit/nosinit.o	61c0c4da8eaa340b
+12019	35313	7527790660208912	obj/chip/3065h/chipinit/pmcinit/pmcinit.o	9e5be56176841a1b
+14059	44386	7527790680619266	obj/chip/3065h/chipinit/systickinit/systickinit.o	f28dd920fe08058a
+14180	52433	7527790681825502	obj/chip/3065h/fotp/fotp_info_read.o	59ef125e0f66ba67
+18239	60488	7527790722403553	obj/chip/3065h/ip_crg/ip_crg_common.o	50d61ec345776d1f
+23221	66513	7527790772239216	obj/drivers/acmp/src/acmp.o	a2d5fbd827adec26
+28243	73551	7527790822458461	obj/drivers/adc/src/adc.o	bffe77b0471e9d8e
+35313	80610	7527790893160785	obj/drivers/adc/src/adc_ex.o	d373e567ca5e49c4
+44386	87647	7527790983889877	obj/drivers/apt/src/apt.o	a294915730c67d1
+52433	95702	7527791064355426	obj/drivers/base/src/assert.o	b2ae5fcdf60b5259
+60489	102783	7527791144888616	obj/drivers/base/src/base_math.o	b459861bcf9a439a
+66513	110838	7527791205153159	obj/drivers/base/src/clock.o	26307b169be7f95e
+73551	119908	7527791275518041	obj/drivers/base/src/generalfunc.o	60e7159d4949291a
+80610	129956	7527791346131211	obj/drivers/base/src/interrupt.o	3f6e621a58f57af4
+87648	138050	7527791416487604	obj/drivers/base/src/lock.o	442ca8b25bc3034d
+95703	144104	7527791497028273	obj/drivers/base/src/reset.o	cf20b4020aca3c41
+102783	151101	7527791567833780	obj/drivers/can/src/can.o	bb80fe93956f455a
+110839	158161	7527791648422967	obj/drivers/capm/src/capm.o	718a45ca8ab4bf60
+119908	165240	7527791739095683	obj/drivers/cfd/src/cfd.o	673b8471e047914c
+129956	172251	7527791839598163	obj/drivers/cmm/src/cmm.o	44e2a8555f89c832
+138050	179303	7527791920511988	obj/drivers/crc/src/crc.o	7ed8a52acbcd93c3
+144104	186337	7527791981056654	obj/drivers/crg/src/crg.o	cda1628605acdd14
+151101	194382	7527792051139722	obj/drivers/dac/src/dac.o	a9291facaa93b593
+158161	203431	7527792121627189	obj/drivers/dac/src/dac_ex.o	f84470fc5ff6e29c
+165240	211501	7527792192436122	obj/drivers/debug/log/src/app_command.o	5641fdc4cc273e80
+172251	218548	7527792262544334	obj/drivers/debug/log/src/cmd.o	8362b04c0b393d9e
+179303	225585	7527792333057969	obj/drivers/debug/log/src/cmd_common.o	288ab2e9c9689ce5
+186338	233642	7527792403371617	obj/drivers/debug/log/src/config.o	bf1fe374bf397142
+194382	240704	7527792483850846	obj/drivers/debug/log/src/console.o	7103e801df0c3083
+203431	247763	7527792574310726	obj/drivers/debug/log/src/dfx_debug.o	371a4d8dc27ee291
+211502	254807	7527792655018039	obj/drivers/debug/log/src/dfx_log.o	ad134c44fd2c132d
+218549	261841	7527792725491416	obj/drivers/debug/log/src/dfx_log_proc.o	91ab2efc2764c3bc
+225585	268910	7527792795865235	obj/drivers/debug/log/src/event.o	280384bad12c5780
+233642	275949	7527792876441832	obj/drivers/debug/log/src/ext_command.o	f1ade74cac4a9d66
+240705	282989	7527792947053364	obj/drivers/debug/src/debug.o	cce3e6206e048252
+247764	291031	7527793017640939	obj/drivers/dma/src/dma.o	d514a420d6346ee5
+254807	301103	7527793088087422	obj/drivers/flash/src/flash.o	b06d383bc97a1dc2
+261841	307163	7527793158427977	obj/drivers/gpio/src/gpio.o	9305b84d3e52ec8e
+268910	314217	7527793229119276	obj/drivers/gpt/src/gpt.o	8d415b14109b67f1
+275949	323259	7527793299528466	obj/drivers/i2c/src/i2c.o	e1a063eef7ba3d2c
+282989	332299	7527793369894456	obj/drivers/iocmg/src/iocmg.o	d135520b5864fc5d
+291031	339346	7527793450348809	obj/drivers/iwdg/src/iwdg.o	faaff374cba18531
+301104	348417	7527793551075144	obj/drivers/pga/src/pga.o	e3ab7e4c028fda89
+307163	355463	7527793611642457	obj/drivers/pmc/src/pmc.o	acc252ccba02c055
+314217	362508	7527793682191756	obj/drivers/qdm/src/qdm.o	d64a143bacd90c1d
+323259	371557	7527793772616687	obj/drivers/spi/src/spi.o	f4a0d8c3e8a65441
+332299	379606	7527793863001346	obj/drivers/timer/src/timer.o	53fb36405f961c24
+339346	387675	7527793933468951	obj/drivers/tsensor/src/tsensor.o	816ba2f9113bea80
+348417	394739	7527794024186104	obj/drivers/tsensor/src/tsensor_ex.o	bd6cb4fc00767d2a
+355463	401777	7527794094663084	obj/drivers/uart/src/uart.o	c6549781ffbec5fe
+362508	408819	7527794165117159	obj/drivers/wdg/src/wdg.o	fa5fa7d1614bc066
+371557	415856	7527794255581700	obj/middleware/control_library/adc_calibra/mcs_adcCalibr.o	135d0dea5e217dad
+379606	422904	7527794336078386	obj/middleware/control_library/brake/mcs_brake.o	61602559ecc6dcc8
+387675	429940	7527794416757932	obj/middleware/control_library/filter/mcs_filter.o	6345624730d2fda7
+394739	436985	7527794487403004	obj/middleware/control_library/filter/mcs_lpfRk4.o	46b1b2958c1763b0
+401777	444042	7527794557783995	obj/middleware/control_library/filter/mcs_pll.o	e2b6a535cf4dd05d
+408819	452085	7527794628201153	obj/middleware/control_library/foc_loop_ctrl/mcs_curr_ctrl.o	ac12d1bed8b3bab2
+415857	459113	7527794698578952	obj/middleware/control_library/foc_loop_ctrl/mcs_curr_ff.o	eabe7d3a7794d774
+422904	470202	7527794769070539	obj/middleware/control_library/foc_loop_ctrl/mcs_fw_ctrl.o	c9e653d3827d7b0d
+429941	476219	7527794839405774	obj/middleware/control_library/foc_loop_ctrl/mcs_if_ctrl.o	eb6089ff1864d513
+436985	482260	7527794909857672	obj/middleware/control_library/foc_loop_ctrl/mcs_pos_ctrl.o	8ccd50c4b987e9f1
+444042	489304	7527794980432165	obj/middleware/control_library/foc_loop_ctrl/mcs_spd_ctrl.o	e602e6acc65d2f7
+452085	496346	7527795060852266	obj/middleware/control_library/foc_loop_ctrl/mcs_startup.o	30a776f5eb6f3f5d
+459113	503383	7527795131151120	obj/middleware/control_library/math/mcs_math.o	19f60d2052aa053c
+470202	512438	7527795242030821	obj/middleware/control_library/modulation/mcs_r1_svpwm.o	a724827d1f34d49
+476219	519490	7527795302204423	obj/middleware/control_library/modulation/mcs_svpwm.o	cadbc909d8fe94d5
+482260	526528	7527795362600877	obj/middleware/control_library/observer/mcs_fosmo.o	abb8c8c4bbeeaa36
+489305	530860	7527795433044131	obj/middleware/control_library/pfc/pfc_curr_ctrl.o	c948629ba0bce146
+496346	531569	7527795503472838	obj/middleware/control_library/pfc/pfc_volt_ctrl.o	eaf1fce75c3949e5
+512438	532314	7527795664389157	obj/middleware/control_library/power/mcs_power_mgmt.o	6a2f90fd2b8c1a26
+519490	532539	7527795734906590	obj/middleware/control_library/protection/mcs_openphs_det.o	c971d654ed45373b
+503383	532691	7527795573853234	obj/middleware/control_library/pid_controller/mcs_pid_ctrl.o	f67455d8e53ed9fb
+526528	532866	7527795805299563	obj/middleware/control_library/protection/mcs_stall_det.o	b6bb7219b38ceab9
+530860	533336	7527795848606055	obj/middleware/control_library/protection/mcs_unbalance_det.o	28c3ea4b51c9f6a8
+531569	533416	7527795855720000	obj/middleware/control_library/ramp/mcs_ramp_mgmt.o	887dd5aa0dfe5aa4
+532540	533437	7527795865459676	obj/middleware/control_library/vf/mcs_vf_ctrl.o	7c90b969a90a93f3
+532866	533485	7527795868692848	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/fwscanf_s.o	718619ceb1975d3c
+532692	533544	7527795866953263	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/fscanf_s.o	6025244f450b2244
+532314	533584	7527795863178216	obj/middleware/control_library/utilities/mcs_mtr_param.o	993c6d3f1789bfa4
+533337	534492	7527795873382999	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/gets_s.o	f29c92854af03feb
+533416	534994	7527795874156825	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/memcpy_s.o	dcd0ae07d2bcd7a3
+533437	537946	7527795874396508	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/memmove_s.o	129d0e1885d6c816
+533485	542984	7527795874865721	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/memset_s.o	58ed634ca7433bab
+533584	546003	7527795875850925	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/securecutil.o	e2741f5a8ad33844
+533545	548015	7527795875474035	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/scanf_s.o	2484ce3a51db8c9b
+534492	552040	7527795884936259	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_a.o	ee5bb05b531ff55
+534994	558073	7527795889949560	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/secureinput_w.o	820fed1393eb84c
+537946	565127	7527795919470176	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_a.o	ac81dc6e09730707
+542984	573190	7527795969843181	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/secureprintoutput_w.o	801de811d192584e
+546003	580233	7527796000040213	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/snprintf_s.o	9ff49ef3f49366db
+548015	587290	7527796020173298	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/sprintf_s.o	b2cde80e646a2cc8
+552040	594344	7527796060405197	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/sscanf_s.o	567415bb074aeefa
+558074	602378	7527796120748272	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/strcat_s.o	156d202bb1952634
+565127	609410	7527796191289334	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/strcpy_s.o	bffa4e2a63b125b
+573190	616469	7527796271930393	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/strncat_s.o	39166a652597e833
+580233	623510	7527796342331710	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/strncpy_s.o	aeae8aa19d8a9fbd
+587290	630556	7527796412925850	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/strtok_s.o	952fafe4707a2ace
+594345	638615	7527796483442611	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/swprintf_s.o	2160d768ba6c75fc
+602378	646670	7527796563781138	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/swscanf_s.o	5dc5dac29b8381fe
+609410	653738	7527796634116860	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vfscanf_s.o	a262eabf30fc3258
+616470	660761	7527796704696843	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vfwscanf_s.o	1d829b86c19aa236
+623510	667804	7527796775125870	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vscanf_s.o	eb6c3246e12a28af
+630556	674861	7527796845579680	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vsnprintf_s.o	494ef9ebbf442d08
+638615	681895	7527796926161790	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vsprintf_s.o	be946fc12365f1e7
+646670	688954	7527797006710834	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vsscanf_s.o	796680415934359d
+653738	695995	7527797077411752	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vswprintf_s.o	e68ba9ba196f1bf3
+660761	703046	7527797147638249	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vswscanf_s.o	208ffca04c271ffe
+667804	710080	7527797218050650	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/vwscanf_s.o	ed886ae76de36d60
+674861	717117	7527797288644761	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wcscat_s.o	5fa93982c553898f
+681895	724171	7527797358974165	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wcscpy_s.o	a7fbb3ff1ce2c709
+688954	731212	7527797429553994	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncat_s.o	4c1727d648dba403
+695996	738252	7527797499962825	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wcsncpy_s.o	180eea6594eb3d81
+703047	745298	7527797570461195	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wcstok_s.o	2651be6c57273fad
+710080	752340	7527797640798046	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wmemcpy_s.o	1c76a9dda5882cc2
+717117	755867	7527797711185573	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wmemmove_s.o	b7af8a42f5795d78
+724171	762405	7527797781720194	obj/middleware/hisilicon/libboundscheck_v1.1.16/src/wscanf_s.o	1e45511005d3e62
+731212	767431	7527797852133027	obj/user/main.o	7115fc7629b9dc76
+738252	777493	7527797922558998	obj/user/generatecode/system_init.o	3845ce407783165f
+745298	781527	7527797993000256	obj/user/sample_gpio_led/src/gpio_led_sample.o	468237f365ce50c5
+781527	812727	7527798355282317	bin/target.elf	86468be09caae5e7
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/out/args.gn b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/out/args.gn
new file mode 100644
index 00000000..9fe8d9de
--- /dev/null
+++ b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/out/args.gn
@@ -0,0 +1,2 @@
+build_type = "debug"
+build_compiler_specified = "hcc_fpu"
diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/out/bin/allinone.bin b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/out/bin/allinone.bin
new file mode 100644
index 0000000000000000000000000000000000000000..5ee3cc6efb3849b0767578a77bfdbfc873d4cedb
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diff --git a/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/out/bin/target.elf b/vendor/yibaina_3061M/demo/HI306XH_RTK.7Z/out/bin/target.elf
new file mode 100644
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