Watch LinYang/sdio_controller_verilog forked from david6chen/sdio_controller_verilog

Controller SDIo host compatible with wishbone I/F {verilog}

Watch LinYang/SM3_core

Watch LinYang/aes forked from openroad-cloud/aes

Watch LinYang/serdes

学习iserdese原语和oserdese原语的使用

Watch LinYang/AMBA_APB_SRAM

AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

Watch LinYang/Verilator forked from Gitee 极速下载/Verilator

Verilator 是一个高性能 Verilog HDL 模拟器与 lint 系统，用户编写一个小的 C++/SystemC 封装文件，该文件实例化用户顶层模块的“已验证”模型

Watch LinYang/iverilog_module forked from yhp/iverilog_module

使用vscode+iverilog+gtkwave搭建的verilog仿真环境。

Watch LinYang/riscv-gnu-toolchain forked from Gitee 极速下载/riscv-gnu-toolchain

riscv-gnu-toolchain 是一个用来支持 RISC-V 为后端的C和C++交叉编译工具链, 包含通用的ELF/Newlib和更复杂的Linux-ELF/glibc两种

Watch LinYang/hbird-sdk forked from RISCV-MCU/hbird-sdk

HummingBird RISC-V Software Development Kit

Watch LinYang/LTE_ZUC_algorithm forked from thanksGreed/LTE_ZUC_algorithm

ZUC祖冲之算法，及算法在LTE中的使用 注意： 因为算法是对int流的计算，而不是对char流的计算。所以一定要考虑输入流的大小端问题