diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 423258a3f0dfe7b5b64d56d16cce84b196a79bf0..4173fc43306a401b08041634c3872f9fe77feb0c 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -110,6 +110,29 @@ static u32 get_umc_base_f18h_m4h(u16 node, u8 channel) return get_umc_base(channel) + (0x80000000 + (0x10000000 * df_id)); } +static u32 get_umc_base_f18h_m18h(u8 channel) +{ + return 0x70000000 + (channel << 20); +} + +static u32 hygon_get_umc_base(struct amd64_pvt *pvt, u8 channel) +{ + u32 umc_base; + + if (hygon_f18h_m4h()) + umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, channel); + /* + * For Hygon family 18h model 0x18h-0x1fh processors, the UMC base + * are identical. + */ + else if (hygon_f18h_m10h() && boot_cpu_data.x86_model >= 0x18) + umc_base = get_umc_base_f18h_m18h(channel); + else + umc_base = get_umc_base(channel); + + return umc_base; +} + /* * Select DCT to which PCI cfg accesses are routed */ @@ -1308,8 +1331,8 @@ static void __dump_misc_regs_df(struct amd64_pvt *pvt) if (!hygon_umc_channel_enabled(pvt->mc_node_id, i)) continue; - if (hygon_f18h_m4h()) - umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, i); + if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) + umc_base = hygon_get_umc_base(pvt, i); else umc_base = get_umc_base(i); umc = &pvt->umc[i]; @@ -1435,8 +1458,8 @@ static void read_umc_base_mask(struct amd64_pvt *pvt) if (!hygon_umc_channel_enabled(pvt->mc_node_id, umc)) continue; - if (hygon_f18h_m4h()) - umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, umc); + if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) + umc_base = hygon_get_umc_base(pvt, umc); else umc_base = get_umc_base(umc); @@ -2971,8 +2994,8 @@ static void __read_mc_regs_df(struct amd64_pvt *pvt) if (!hygon_umc_channel_enabled(pvt->mc_node_id, i)) continue; - if (hygon_f18h_m4h()) - umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, i); + if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) + umc_base = hygon_get_umc_base(pvt, i); else umc_base = get_umc_base(i);