From 1681d721c8509c6584684daebf14a8cc09159afc Mon Sep 17 00:00:00 2001 From: Wan Ahmad Zainie Date: Tue, 5 May 2020 21:06:12 +0800 Subject: [PATCH 1/7] spi: dw: Fix typo in few registers name commit 299cb65c9dd4791242a102f216583773d962c1ac anolis. This patch will fix typo in the register name used in the source code, to be consistent with the register name used in the databook. Databook: DW_apb_ssi_databook.pdf version 4.01a Hygon-SIG: commit 299cb65c9dd4 anolis spi: dw: Fix typo in few registers name Backport from anolis as dependency of spi: dw: Add device HID for Hygon SPI controller Signed-off-by: Wan Ahmad Zainie Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200505130618.554-2-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Mark Brown [ YuntongJin : amend commit log ] Signed-off-by: YuntongJin --- drivers/spi/spi-dw.c | 18 +++++++++--------- drivers/spi/spi-dw.h | 8 ++++---- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index c2f96941ad04..aebf3f7f8e89 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -50,9 +50,9 @@ static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf, len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, "=================================\n"); len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, - "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0)); + "CTRLR0: \t0x%08x\n", dw_readl(dws, DW_SPI_CTRLR0)); len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, - "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1)); + "CTRLR1: \t0x%08x\n", dw_readl(dws, DW_SPI_CTRLR1)); len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR)); len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, @@ -60,9 +60,9 @@ static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf, len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR)); len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, - "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR)); + "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFTLR)); len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, - "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR)); + "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFTLR)); len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR)); len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, @@ -348,7 +348,7 @@ static int dw_spi_transfer_one(struct spi_controller *master, cr0 |= (chip->tmode << SPI_TMOD_OFFSET); } - dw_writel(dws, DW_SPI_CTRL0, cr0); + dw_writel(dws, DW_SPI_CTRLR0, cr0); /* Check if current transfer is a DMA transaction */ if (master->can_dma && master->can_dma(master, spi, transfer)) @@ -369,7 +369,7 @@ static int dw_spi_transfer_one(struct spi_controller *master, } } else if (!chip->poll_mode) { txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes); - dw_writel(dws, DW_SPI_TXFLTR, txlevel); + dw_writel(dws, DW_SPI_TXFTLR, txlevel); /* Set the interrupt mask */ imask |= SPI_INT_TXEI | SPI_INT_TXOI | @@ -457,11 +457,11 @@ static void spi_hw_init(struct device *dev, struct dw_spi *dws) u32 fifo; for (fifo = 1; fifo < 256; fifo++) { - dw_writel(dws, DW_SPI_TXFLTR, fifo); - if (fifo != dw_readl(dws, DW_SPI_TXFLTR)) + dw_writel(dws, DW_SPI_TXFTLR, fifo); + if (fifo != dw_readl(dws, DW_SPI_TXFTLR)) break; } - dw_writel(dws, DW_SPI_TXFLTR, 0); + dw_writel(dws, DW_SPI_TXFTLR, 0); dws->fifo_len = (fifo == 1) ? 0 : fifo; dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len); diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index f3a2f157a2b1..fda08c50cec8 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -7,14 +7,14 @@ #include /* Register offsets */ -#define DW_SPI_CTRL0 0x00 -#define DW_SPI_CTRL1 0x04 +#define DW_SPI_CTRLR0 0x00 +#define DW_SPI_CTRLR1 0x04 #define DW_SPI_SSIENR 0x08 #define DW_SPI_MWCR 0x0c #define DW_SPI_SER 0x10 #define DW_SPI_BAUDR 0x14 -#define DW_SPI_TXFLTR 0x18 -#define DW_SPI_RXFLTR 0x1c +#define DW_SPI_TXFTLR 0x18 +#define DW_SPI_RXFTLR 0x1c #define DW_SPI_TXFLR 0x20 #define DW_SPI_RXFLR 0x24 #define DW_SPI_SR 0x28 -- Gitee From 296e77c84bece0a42cced34ee503f6d2bc2e52c0 Mon Sep 17 00:00:00 2001 From: Wan Ahmad Zainie Date: Tue, 5 May 2020 21:06:13 +0800 Subject: [PATCH 2/7] spi: dw: Add update_cr0() callback to update CTRLR0 commit c4eadee21fa9afd3dc9dd867c71b642177bf671f anolis. This patch adds update_cr0() callback, in struct dw_spi. Existing code that configure register CTRLR0 is moved into a new function, dw_spi_update_cr0(), and this will be the default. Hygon-SIG: commit c4eadee21fa9 anolis spi: dw: Add update_cr0() callback to update CTRLR0 Backport from anolis as dependency of spi: dw: Add device HID for Hygon SPI controller Suggested-by: Andy Shevchenko Signed-off-by: Wan Ahmad Zainie Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200505130618.554-3-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Mark Brown [ YuntongJin : amend commit log ] Signed-off-by: YuntongJin --- drivers/spi/spi-dw-mid.c | 4 ++++ drivers/spi/spi-dw-mmio.c | 20 ++++++++++++++++++-- drivers/spi/spi-dw.c | 28 +++++++++++++++++++++------- drivers/spi/spi-dw.h | 5 +++++ 4 files changed, 48 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c index b07710c76fc9..ec2b9bc04a62 100644 --- a/drivers/spi/spi-dw-mid.c +++ b/drivers/spi/spi-dw-mid.c @@ -324,5 +324,9 @@ int dw_spi_mid_init(struct dw_spi *dws) dws->dma_rx = &mid_dma_rx; dws->dma_ops = &mid_dma_ops; #endif + + /* Register hook to configure CTRLR0 */ + dws->update_cr0 = dw_spi_update_cr0; + return 0; } diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index bd46fca3f094..4237a3a1d194 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -105,6 +105,9 @@ static int dw_spi_mscc_init(struct platform_device *pdev, dwsmmio->dws.set_cs = dw_spi_mscc_set_cs; dwsmmio->priv = dwsmscc; + /* Register hook to configure CTRLR0 */ + dwsmmio->dws.update_cr0 = dw_spi_update_cr0; + return 0; } @@ -127,6 +130,18 @@ static int dw_spi_alpine_init(struct platform_device *pdev, { dwsmmio->dws.cs_override = 1; + /* Register hook to configure CTRLR0 */ + dwsmmio->dws.update_cr0 = dw_spi_update_cr0; + + return 0; +} + +static int dw_spi_dw_apb_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + /* Register hook to configure CTRLR0 */ + dwsmmio->dws.update_cr0 = dw_spi_update_cr0; + return 0; } @@ -219,16 +234,17 @@ static int dw_spi_mmio_remove(struct platform_device *pdev) } static const struct of_device_id dw_spi_mmio_of_match[] = { - { .compatible = "snps,dw-apb-ssi", }, + { .compatible = "snps,dw-apb-ssi", .data = dw_spi_dw_apb_init}, { .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init}, { .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init}, { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init}, + { .compatible = "renesas,rzn1-spi", .data = dw_spi_dw_apb_init}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match); static const struct acpi_device_id dw_spi_mmio_acpi_match[] = { - {"HISI0173", 0}, + {"HISI0173", (kernel_ulong_t)dw_spi_dw_apb_init}, {}, }; MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match); diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index aebf3f7f8e89..9c6e9379136e 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -273,6 +273,26 @@ static irqreturn_t dw_spi_irq(int irq, void *dev_id) return dws->transfer_handler(dws); } +/* Configure CTRLR0 for DW_apb_ssi */ +u32 dw_spi_update_cr0(struct spi_controller *master, struct spi_device *spi, + struct spi_transfer *transfer) +{ + struct dw_spi *dws = spi_controller_get_devdata(master); + struct chip_data *chip = spi_get_ctldata(spi); + u32 cr0; + + /* Default SPI mode is SCPOL = 0, SCPH = 0 */ + cr0 = (transfer->bits_per_word - 1) + | (chip->type << SPI_FRF_OFFSET) + | ((((spi->mode & SPI_CPOL) ? 1 : 0) << SPI_SCOL_OFFSET) | + (((spi->mode & SPI_CPHA) ? 1 : 0) << SPI_SCPH_OFFSET) | + (((spi->mode & SPI_LOOP) ? 1 : 0) << SPI_SRL_OFFSET)) + | (chip->tmode << SPI_TMOD_OFFSET); + + return cr0; +} +EXPORT_SYMBOL_GPL(dw_spi_update_cr0); + /* Must be called inside pump_transfers() */ static int poll_transfer(struct dw_spi *dws) { @@ -324,13 +344,7 @@ static int dw_spi_transfer_one(struct spi_controller *master, dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE); dws->dma_width = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE); - /* Default SPI mode is SCPOL = 0, SCPH = 0 */ - cr0 = (transfer->bits_per_word - 1) - | (chip->type << SPI_FRF_OFFSET) - | ((((spi->mode & SPI_CPOL) ? 1 : 0) << SPI_SCOL_OFFSET) | - (((spi->mode & SPI_CPHA) ? 1 : 0) << SPI_SCPH_OFFSET) | - (((spi->mode & SPI_LOOP) ? 1 : 0) << SPI_SRL_OFFSET)) - | (chip->tmode << SPI_TMOD_OFFSET); + cr0 = dws->update_cr0(master, spi, transfer); /* * Adjust transfer mode if necessary. Requires platform dependent diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index fda08c50cec8..473a7ec9b109 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -115,6 +115,8 @@ struct dw_spi { u16 bus_num; u16 num_cs; /* supported slave numbers */ void (*set_cs)(struct spi_device *spi, bool enable); + u32 (*update_cr0)(struct spi_controller *master, struct spi_device *spi, + struct spi_transfer *transfer); /* Current message transfer state info */ size_t len; @@ -253,6 +255,9 @@ extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws); extern void dw_spi_remove_host(struct dw_spi *dws); extern int dw_spi_suspend_host(struct dw_spi *dws); extern int dw_spi_resume_host(struct dw_spi *dws); +extern u32 dw_spi_update_cr0(struct spi_controller *master, + struct spi_device *spi, + struct spi_transfer *transfer); /* platform related setup */ extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */ -- Gitee From 03bccbfb4983801cc1c12f1654ffe6bc8c87f499 Mon Sep 17 00:00:00 2001 From: Wan Ahmad Zainie Date: Tue, 5 May 2020 21:06:14 +0800 Subject: [PATCH 3/7] spi: dw: Add support for DesignWare DWC_ssi commit e539f435cb9c78c6984b75f16b65a2ece7867981 anolis. This patch adds initial support for DesignWare DWC_ssi soft IP. DWC_ssi is the enhanced version of DW_apb_ssi, which is currently supported by this driver. Their registers are same, but the bit fields of register CTRLR0 are different. DWC_ssi has additional features compared to DW_apb_ssi. Major enhancements in DWC_ssi are hyper bus protocol, boot mode support and advanced XIP support. DWC_ssi is an AHB slave device, whilst DW_apb_ssi is an APB slave device. Register offset DW_ssi DW_apb_ssi CTRLR0 0x00 0x00 CTRLR1 0x04 0x04 SSIENR 0x08 0x08 MWCR 0x0c 0x0c SER 0x10 0x10 BAUDR 0x14 0x14 TXFTLR 0x18 0x18 RXFTLR 0x1c 0x1c TXFLR 0x20 0x20 RXFLR 0x24 0x24 SR 0x28 0x28 IMR 0x2c 0x2c ISR 0x30 0x30 RISR 0x34 0x34 TXOICR 0x38 0x38 RXOICR 0x3c 0x3c RXUICR 0x40 0x40 MSTICR 0x44 0x44 ICR 0x48 0x48 DMACR 0x4c 0x4c DMATDLR 0x50 0x50 DMARDLR 0x54 0x54 IDR 0x58 0x58 SSI_VERSION_ID 0x5c 0x5c DRx (0 to 35) 0x60+i*0x4 0x60+i*0x4 RX_SAMPLE_DLY 0xf0 0xf0 SPI_CTRLR0 0xf4 0xf4 TXD_DRIVE_EDGE 0xf8 0xf8 XIP_MODE_BITS 0xfc RSVD Register configuration - CTRLR0 DW_ssi DW_apb_ssi SPI_HYPERBUS_EN bit[24] NONE SPI_FRF bit[23:22] bit[22:21] DFS_32 NONE bit[20:16] CFS bit[19:16] bit[15:12] SSTE bit[14] bit[24] SRL bit[13] bit[11] SLV_OE bit[12] bit[10] TMOD bit[11:10] bit[9:8] SCPOL | SPHA bit[9:8] bit[7:6] FRF bit[7:6] bit[5:4] DFS bit[4:0] bit[3:0] The documents used are [1] DW_apb_ssi_databook.pdf version 4.01a (2016.10a). [2] DWC_ssi_databook.pdf version 1.01a. Hygon-SIG: commit e539f435cb9c anolis spi: dw: Add support for DesignWare DWC_ssi Backport from anolis as dependency of spi: dw: Add device HID for Hygon SPI controller Signed-off-by: Wan Ahmad Zainie Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200505130618.554-4-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Mark Brown [ YuntongJin : amend commit log ] Signed-off-by: YuntongJin --- drivers/spi/spi-dw-mmio.c | 10 ++++++++++ drivers/spi/spi-dw.c | 33 +++++++++++++++++++++++++++++++++ drivers/spi/spi-dw.h | 12 ++++++++++++ 3 files changed, 55 insertions(+) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 4237a3a1d194..75129756b6ce 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -145,6 +145,15 @@ static int dw_spi_dw_apb_init(struct platform_device *pdev, return 0; } +static int dw_spi_dwc_ssi_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + /* Register hook to configure CTRLR0 */ + dwsmmio->dws.update_cr0 = dw_spi_update_cr0_v1_01a; + + return 0; +} + static int dw_spi_mmio_probe(struct platform_device *pdev) { int (*init_func)(struct platform_device *pdev, @@ -239,6 +248,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init}, { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init}, { .compatible = "renesas,rzn1-spi", .data = dw_spi_dw_apb_init}, + { .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_dwc_ssi_init}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match); diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 9c6e9379136e..ad588bfe29b4 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -293,6 +293,39 @@ u32 dw_spi_update_cr0(struct spi_controller *master, struct spi_device *spi, } EXPORT_SYMBOL_GPL(dw_spi_update_cr0); +/* Configure CTRLR0 for DWC_ssi */ +u32 dw_spi_update_cr0_v1_01a(struct spi_controller *master, + struct spi_device *spi, + struct spi_transfer *transfer) +{ + struct dw_spi *dws = spi_controller_get_devdata(master); + struct chip_data *chip = spi_get_ctldata(spi); + u32 cr0; + + /* CTRLR0[ 4: 0] Data Frame Size */ + cr0 = (transfer->bits_per_word - 1); + + /* CTRLR0[ 7: 6] Frame Format */ + cr0 |= chip->type << DWC_SSI_CTRLR0_FRF_OFFSET; + + /* + * SPI mode (SCPOL|SCPH) + * CTRLR0[ 8] Serial Clock Phase + * CTRLR0[ 9] Serial Clock Polarity + */ + cr0 |= ((spi->mode & SPI_CPOL) ? 1 : 0) << DWC_SSI_CTRLR0_SCPOL_OFFSET; + cr0 |= ((spi->mode & SPI_CPHA) ? 1 : 0) << DWC_SSI_CTRLR0_SCPH_OFFSET; + + /* CTRLR0[11:10] Transfer Mode */ + cr0 |= chip->tmode << DWC_SSI_CTRLR0_TMOD_OFFSET; + + /* CTRLR0[13] Shift Register Loop */ + cr0 |= ((spi->mode & SPI_LOOP) ? 1 : 0) << DWC_SSI_CTRLR0_SRL_OFFSET; + + return cr0; +} +EXPORT_SYMBOL_GPL(dw_spi_update_cr0_v1_01a); + /* Must be called inside pump_transfers() */ static int poll_transfer(struct dw_spi *dws) { diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 473a7ec9b109..1a5422921f32 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -58,6 +58,15 @@ #define SPI_SRL_OFFSET 11 #define SPI_CFS_OFFSET 12 +/* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */ +#define DWC_SSI_CTRLR0_SRL_OFFSET 13 +#define DWC_SSI_CTRLR0_TMOD_OFFSET 10 +#define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10) +#define DWC_SSI_CTRLR0_SCPOL_OFFSET 9 +#define DWC_SSI_CTRLR0_SCPH_OFFSET 8 +#define DWC_SSI_CTRLR0_FRF_OFFSET 6 +#define DWC_SSI_CTRLR0_DFS_OFFSET 0 + /* Bit fields in SR, 7 bits */ #define SR_MASK 0x7f /* cover 7 bits */ #define SR_BUSY (1 << 0) @@ -258,6 +267,9 @@ extern int dw_spi_resume_host(struct dw_spi *dws); extern u32 dw_spi_update_cr0(struct spi_controller *master, struct spi_device *spi, struct spi_transfer *transfer); +extern u32 dw_spi_update_cr0_v1_01a(struct spi_controller *master, + struct spi_device *spi, + struct spi_transfer *transfer); /* platform related setup */ extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */ -- Gitee From 955dcc42de1c405af67a43b5cbb582593386e6f5 Mon Sep 17 00:00:00 2001 From: Wan Ahmad Zainie Date: Tue, 5 May 2020 21:06:16 +0800 Subject: [PATCH 4/7] spi: dw: Add support for Intel Keem Bay SPI commit f42377916ed534649341777669628f22ef1edf59 anolis. Add support for Intel Keem Bay SPI controller, which uses DesignWare DWC_ssi core. Bit 31 of CTRLR0 register is added for Keem Bay, to configure the device as a master or as a slave serial peripheral. Hygon-SIG: commit f42377916ed5 anolis spi: dw: Add support for Intel Keem Bay SPI Backport from anolis as dependency of spi: dw: Add device HID for Hygon SPI controller Signed-off-by: Wan Ahmad Zainie Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200505130618.554-6-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Mark Brown [ YuntongJin : amend commit log ] Signed-off-by: YuntongJin --- drivers/spi/spi-dw-mmio.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 75129756b6ce..cdf66a6db963 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -43,6 +43,13 @@ struct dw_spi_mmio { #define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13) #define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5) +/* + * For Keem Bay, CTRLR0[31] is used to select controller mode. + * 0: SSI is slave + * 1: SSI is master + */ +#define KEEMBAY_CTRLR0_SSIC_IS_MST BIT(31) + struct dw_spi_mscc { struct regmap *syscon; void __iomem *spi_mst; @@ -154,6 +161,24 @@ static int dw_spi_dwc_ssi_init(struct platform_device *pdev, return 0; } +static u32 dw_spi_update_cr0_keembay(struct spi_controller *master, + struct spi_device *spi, + struct spi_transfer *transfer) +{ + u32 cr0 = dw_spi_update_cr0_v1_01a(master, spi, transfer); + + return cr0 | KEEMBAY_CTRLR0_SSIC_IS_MST; +} + +static int dw_spi_keembay_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + /* Register hook to configure CTRLR0 */ + dwsmmio->dws.update_cr0 = dw_spi_update_cr0_keembay; + + return 0; +} + static int dw_spi_mmio_probe(struct platform_device *pdev) { int (*init_func)(struct platform_device *pdev, @@ -249,6 +274,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init}, { .compatible = "renesas,rzn1-spi", .data = dw_spi_dw_apb_init}, { .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_dwc_ssi_init}, + { .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match); -- Gitee From d671654b56f4e224cc45df45593c5a5ae569708d Mon Sep 17 00:00:00 2001 From: Wan Ahmad Zainie Date: Tue, 5 May 2020 21:06:15 +0800 Subject: [PATCH 5/7] spi: dw-apb-ssi: Add compatible string for DesignWare DWC_ssi commit 3812a081d2fcc297d039c4ffafa7778d75abcbe2 anolis. This patch adds compatible string "snps,dwc-ssi-1.01a" to the above DT binding document, to provide support for DesignWare DWC_ssi IP [1]. Current driver supports DW_apb_ssi IP [2]. References: [1] https://www.synopsys.com/dw/ipdir.php?c=dwc_ssi [2] https://www.synopsys.com/dw/ipdir.php?c=DW_apb_ssi Hygon-SIG: commit 3812a081d2fc anolis spi: dw-apb-ssi: Add compatible string for DesignWare DWC_ssi Backport from anolis as dependency of spi: dw: Add device HID for Hygon SPI controller Signed-off-by: Wan Ahmad Zainie Link: https://lore.kernel.org/r/20200505130618.554-5-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Mark Brown [ YuntongJin : amend commit log ] Signed-off-by: YuntongJin --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index f54c8c36395e..87805454c73c 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -2,7 +2,7 @@ Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface. Required properties: - compatible : "snps,dw-apb-ssi" or "mscc,-spi", where soc is "ocelot" or - "jaguar2", or "amazon,alpine-dw-apb-ssi" + "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a" - reg : The register base for the controller. For "mscc,-spi", a second register set is required (named ICPU_CFG:SPI_MST) - interrupts : One interrupt, used by the controller. -- Gitee From edee5be47bf3dba84db8bd733d405d6f69da5905 Mon Sep 17 00:00:00 2001 From: Wan Ahmad Zainie Date: Tue, 5 May 2020 21:06:17 +0800 Subject: [PATCH 6/7] spi: dw-apb-ssi: Add Intel Keem Bay support commit c48e0c533e72ca264ac914addccab8a328806ed3 anolis. Document Intel Keem Bay SPI controller DT bindings. Hygon-SIG: commit c48e0c533e72 anolis spi: dw-apb-ssi: Add Intel Keem Bay support Backport from anolis as dependency of spi: dw: Add device HID for Hygon SPI controller Signed-off-by: Wan Ahmad Zainie Link: https://lore.kernel.org/r/20200505130618.554-7-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Mark Brown [ YuntongJin : amend commit log ] Signed-off-by: YuntongJin --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index 87805454c73c..92408029bc39 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -2,7 +2,8 @@ Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface. Required properties: - compatible : "snps,dw-apb-ssi" or "mscc,-spi", where soc is "ocelot" or - "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a" + "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a" or + "intel,keembay-ssi" - reg : The register base for the controller. For "mscc,-spi", a second register set is required (named ICPU_CFG:SPI_MST) - interrupts : One interrupt, used by the controller. -- Gitee From bde93fc8c4ed52f79e119af3d59d8c0661772028 Mon Sep 17 00:00:00 2001 From: Liao Xuan Date: Tue, 27 Jan 2026 16:43:41 +0800 Subject: [PATCH 7/7] spi: dw: Add device HID for Hygon SPI controller commit 4bf4507e1cf3c59031c12d2b7c5e93043dd11c69 anolis. ANBZ: #30152 Add HID HYGO0062 to support Hygon SPI controller. Hygon-SIG: commit none hygon anolis: spi: dw: Add device HID for Hygon SPI controller Hygon-SIG: commit 4bf4507e1cf3 anolis anolis: spi: dw: Add device HID for Hygon SPI controller Backport from anolis to support Hygon family 18h model 18h Signed-off-by: Liao Xuan Reviewed-by Guixin Liu Link: https://gitee.com/anolis/cloud-kernel/pulls/6463 [ YuntongJin : amend commit log, backport dependency ] Signed-off-by: YuntongJin --- drivers/spi/spi-dw-mmio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index cdf66a6db963..1cdce1e4cfd1 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -281,6 +281,7 @@ MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match); static const struct acpi_device_id dw_spi_mmio_acpi_match[] = { {"HISI0173", (kernel_ulong_t)dw_spi_dw_apb_init}, + {"HYGO0062", (kernel_ulong_t)dw_spi_dwc_ssi_init}, {}, }; MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match); -- Gitee