# BenchPCNP

**Repository Path**: SenRui/bench-pcnp

## Basic Information

- **Project Name**: BenchPCNP
- **Description**: 这是一个用于印刷电路网表分区的数据集。
- **Primary Language**: Python
- **License**: CC-BY-4.0
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2025-04-01
- **Last Updated**: 2026-03-31

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# BenchPCNP: Benchmark Dataset for Printed Circuit Board Netlist Processing

## Project Overview

BenchPCNP is a comprehensive benchmark dataset and toolkit for printed circuit board (PCB) netlist segmentation and analysis. The project provides tools for converting netlist files into graph representations suitable for machine learning applications, with support for both traditional graphs and hypergraphs.

## Project Structure

```
BenchPCNP/
├── Data/                          # Data directory containing all datasets
│   ├── Nets  /                    # Original netlist files
│   ├── Graphs/                    # Traditional graph representations
│   ├── HyperGraphs/               # Hypergraph representations  
│   ├── MergeGraphs/               # Merged graph datasets
│   └── MergeHyperGraphs/          # Merged hypergraph datasets
├── utils/                         # Utility modules
│   ├── unit.py                    # Unit class for circuit components
│   ├── net.py                     # Net class for electrical connections
│   ├── env_config.py              # Configuration parameters
│   └── seeds.py                   # Random seed settings
├── GraphConstruction.py           # Main data processing script
└── README.md                      # This file
```

## Data Section

### Data Organization

The project contains 50 different circuit designs, each represented in multiple formats:

#### 1. Original Netlist Files (`Data/Nets/`)
- **Format**: Protel/Protel2 netlist files (`.net` extension)
- **Content**: Raw circuit connectivity information
- **Structure**: Each project folder contains:
  - One main netlist file (complete circuit)
  - Multiple sub-circuit netlist files (functional modules)

#### 2. Traditional Graph Representations (`Data/Graphs/`)
- **Format**: JSON files
- **Content**: Node-edge graph representations
- **Structure**: Each `GraphN/` folder contains:
  - `graph.json`: Complete graph with nodes, edges, and labels
  - Node features: Component type, footprint, pin count
  - Edge information: Electrical connections between components
  - Labels: Functional classification of circuit modules

#### 3. Hypergraph Representations (`Data/HyperGraphs/`)
- **Format**: JSON files  
- **Content**: Hypergraph structures where hyperedges represent electrical nets
- **Structure**: Each `GraphN/` folder contains:
  - `hypergraph.json`: Hypergraph with nodes, hyperedges, and labels
  - Hyperedges: Groups of components connected by the same electrical net
  - Enhanced representation for multi-pin connections

#### 4. Merged Datasets (`Data/MergeGraphs/`, `Data/MergeHyperGraphs/`)
- **Format**: PyTorch tensors (`.pt` files)
- **Content**: Preprocessed, merged datasets ready for machine learning
- **Features**: 
  - Combined node features from all circuits
  - Train/validation/test splits
  - PyTorch Geometric Data objects

### Data Labels and Classification

The dataset includes 54 functional circuit categories:

'LED', 'Download', 'Control', 'Power', 'Buzzer Alarm', 'Touch', 'Communication', 'Storage', 'Serial Port',
'Reset', 'Status Read', 'Isolation', 'IO', 'Amplification', 'Driver', 'Detection', 'Connection', 'Filter',
'Others', 'ADC', 'Sampling', 'Boot', 'Button', 'Display', 'Crystal', 'Test', 'Pull Up-Down', 'AV Multimedia',
'Motor Control', 'Signal Isolation', 'CYUSB', 'Flash', 'Transformer', 'Protection', 'Impedance Match',
'Signal Receive', 'Charge-Discharge', 'Switch', 'Interface', 'Conversion', 'Sine Wave Gen', 'Encoder',
'rtc': 'RTC', Level Shift' 'Servo', 'Common Ground', 'Current Limit', 'Voltage Reg', 'Buffer', 'Enable', 
'Vibration Motor', 'Three Phase Inv', 'Latch', 'Transceiver'

## Data Processing Pipeline

### 1. Netlist Parsing (`NetReader` class)

The `NetReader` class supports multiple netlist formats:

```python
# Supported formats
- None: Custom format with space-separated values
- "protel": Protel format with bracket notation
- "protel2": Enhanced Protel format with pipe-separated values
```

**Key Features**:
- Automatic component identification and classification
- Pin-to-net mapping extraction
- Component footprint and type recognition
- Core unit and input/output unit classification

### 2. Graph Construction

#### Traditional Graph Building
- **Nodes**: Circuit components (resistors, capacitors, ICs, etc.)
- **Edges**: Electrical connections between components
- **Features**: Component type, footprint, pin count encoded as feature vectors

#### Hypergraph Building
- **Nodes**: Circuit components
- **Hyperedges**: Electrical nets connecting multiple components
- **Advantages**: Better representation of multi-pin connections and electrical nets

### 3. Feature Engineering

#### Node Feature Encoding
```python
# Feature modes (configurable via node_features_mode parameter)
- '1': Include feature (one-hot encoding for class/footprint, binary for pin count)
- '2': Constant feature (all 1s)
- '0': Zero feature (all 0s)

# Example: node_features_mode='111'
# - Component class: one-hot encoded
# - Footprint: one-hot encoded  
# - Pin count: binary encoded
```

#### Label Processing
- Automatic circuit module classification
- Hierarchical label organization
- Train/validation/test split generation

### 4. Data Preprocessing

#### Graph Preprocessing (`data_preprocess` function)
- Converts JSON data to PyTorch Geometric Data objects
- Handles both traditional graphs and hypergraphs
- Generates appropriate masks for training/validation/testing

#### Dataset Merging
- Combines multiple circuit graphs into unified datasets
- Maintains consistent node indexing across graphs
- Configurable training ratios (default: 60% train, 20% validation, 20% test)

## Usage Examples

### Building Individual Graphs
```python
from GraphConstruction import build_graph, build_hypergraph

# Build traditional graphs
build_graph()

# Build hypergraphs  
build_hypergraph()
```

### Loading Merged Datasets
```python
from GraphConstruction import read_graph, read_hypergraph

# Load traditional graph dataset
graph_data = read_graph(
    node_features_mode='111',  # Include all features
    train_rate=0.6            # 60% training data
)

# Load hypergraph dataset
hypergraph_data = read_hypergraph(
    node_features_mode='111',
    train_rate=0.6
)
```

### Custom Feature Configuration
```python
# Different feature modes
graph_data = read_graph(
    node_features_mode='101',  # Only class and pin count features
    train_rate=0.7            # 70% training data
)
```

## Data Statistics

- **Total Circuits**: 50
- **Component Types**: 50+ unique component classes
- **Footprint Types**: 100+ different package footprints
- **Pin Count Range**: 1-50+ pins per component
- **Label Categories**: 50+ functional circuit types
- **Data Formats**: JSON (raw), PyTorch tensors (processed)

## Technical Requirements

- **Python**: 3.6+
- **Dependencies**: 
  - PyTorch
  - PyTorch Geometric
  - NumPy
  - JSON
- **File Formats**: 
  - Input: `.net` (Protel netlists)
  - Output: `.json`, `.pt` (PyTorch tensors)

## Applications

This dataset is designed for:
- **Circuit Classification**: Identifying functional modules in PCB designs
- **Component Placement**: Learning optimal component positioning
- **Netlist Analysis**: Understanding circuit connectivity patterns
- **PCB Design Automation**: Training ML models for design assistance
- **Circuit Verification**: Validating circuit functionality and connections

## Citation

If you use this dataset in your research, please cite:

```
BenchPCNP: A Benchmark Dataset for Printed Circuit Board Netlist Processing
2025
```