diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 58cb9495e40f426323cd65569cd53145e7b2f9e7..d88ea3c12ea04e35a1ab3c38adcf804dde1818fa 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -156,6 +156,23 @@
 #define X86_FEATURE_PHE_EN		( 5*32+11) /* PHE enabled */
 #define X86_FEATURE_PMM			( 5*32+12) /* PadLock Montgomery Multiplier */
 #define X86_FEATURE_PMM_EN		( 5*32+13) /* PMM enabled */
+#define X86_FEATURE_ZX_FMA		(5*32+15) /* FMA supported */
+#define X86_FEATURE_PARALLAX	(5*32+16) /* Adaptive P-state control present */
+#define X86_FEATURE_PARALLAX_EN (5*32+17) /* Adaptive P-state control enabled */
+#define X86_FEATURE_OVERSTRESS	(5*32+18) /* Overstress Feature for auto overclock present */
+#define X86_FEATURE_OVERSTRESS_EN (5*32+19) /* Overstress Feature for auto overclock enabled */
+#define X86_FEATURE_TM3        (5*32+20) /* Thermal Monitor 3 present */
+#define X86_FEATURE_TM3_EN		(5*32+21) /* Thermal Monitor 3 enabled */
+#define X86_FEATURE_RNG2		(5*32+22) /* 2nd generation of RNG present */
+#define X86_FEATURE_RNG2_EN    (5*32+23) /* 2nd generation of RNG enabled */
+#define X86_FEATURE_SEM        (5*32+24) /* SME feature present */
+#define X86_FEATURE_PHE2		(5*32+25) /* SHA384 and SHA 512 present */
+#define X86_FEATURE_PHE2_EN    (5*32+26) /* SHA384 and SHA 512 enabled */
+#define X86_FEATURE_XMODX      (5*32+27) /* "rsa" XMODEXP and MONTMUL2 are present */
+#define X86_FEATURE_XMODX_EN   (5*32+28) /* "rsa_en" XMODEXP and MONTMUL2 are enabled */
+#define X86_FEATURE_VEX        (5*32+29) /* VEX instructions are present */
+#define X86_FEATURE_VEX_EN		(5*32+30) /* VEX instructions are enabled */
+#define X86_FEATURE_STK        (5*32+31) /* STK are present */
 
 /* More extended AMD flags: CPUID level 0x80000001, ECX, word 6 */
 #define X86_FEATURE_LAHF_LM		( 6*32+ 0) /* LAHF/SAHF in long mode */
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 345f7d905db677291f7f8eb9b33b692263afe447..a5c01c8f88241ef584af9970103de43846e3bcad 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -109,6 +109,9 @@ static void early_init_centaur(struct cpuinfo_x86 *c)
 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
 	}
+
+	if (detect_extended_topology_early(c) < 0)
+		detect_ht_early(c);
 }
 
 static void init_centaur(struct cpuinfo_x86 *c)
@@ -127,11 +130,14 @@ static void init_centaur(struct cpuinfo_x86 *c)
 	clear_cpu_cap(c, 0*32+31);
 #endif
 	early_init_centaur(c);
+	detect_extended_topology(c);
 	init_intel_cacheinfo(c);
-	detect_num_cpu_cores(c);
+	if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
+		detect_num_cpu_cores(c);
 #ifdef CONFIG_X86_32
 	detect_ht(c);
 #endif
+	}
 
 	if (c->cpuid_level > 9) {
 		unsigned int eax = cpuid_eax(10);
diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
index 05fa4ef634902293e3286705134168b40d812932..2126b10de796ac2f51619fae83edc43beb078b22 100644
--- a/arch/x86/kernel/cpu/zhaoxin.c
+++ b/arch/x86/kernel/cpu/zhaoxin.c
@@ -79,16 +79,21 @@ static void early_init_zhaoxin(struct cpuinfo_x86 *c)
 			c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
 	}
 
+	if (detect_extended_topology_early(c) < 0)
+		detect_ht_early(c);
 }
 
 static void init_zhaoxin(struct cpuinfo_x86 *c)
 {
 	early_init_zhaoxin(c);
+	detect_extended_topology(c);
 	init_intel_cacheinfo(c);
-	detect_num_cpu_cores(c);
+	if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
+		detect_num_cpu_cores(c);
 #ifdef CONFIG_X86_32
 	detect_ht(c);
 #endif
+	}
 
 	if (c->cpuid_level > 9) {
 		unsigned int eax = cpuid_eax(10);