diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 3f5ccf2b5c0264b79803d6130172c2d292f8b948..0049f546a60109f218f83cbf8ba483324ead72d3 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -92,6 +92,9 @@
 #define PHYTIUM_CPU_PART_2000PLUS	0x662
 #define PHYTIUM_CPU_PART_2004		0x663
 #define PHYTIUM_CPU_PART_2500		0x663
+#define PHYTIUM_CPU_PART_FTC862                0x862
+
+#define PHYTIUM_CPU_SOCID_PS24080      0x6
 
 #define CAVIUM_CPU_PART_THUNDERX	0x0A1
 #define CAVIUM_CPU_PART_THUNDERX_81XX	0x0A2
@@ -181,6 +184,7 @@
 #define MIDR_FT_2000PLUS MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_2000PLUS)
 #define MIDR_FT_2004 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_2004)
 #define MIDR_FT_2500 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_2500)
+#define MIDR_PHYTIUM_FTC862 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC862)
 
 #ifndef __ASSEMBLY__
 
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 83abb8aadd9391b1fa4fc56fc72ec05e96bb09fa..7fa1c7f0d28d8c4fdba290089e06979be3e500c5 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -1409,7 +1409,17 @@ static void arm_smmu_evtq_read_events(struct arm_smmu_device *smmu)
 	do {
 		while (!queue_remove_raw(q, evt)) {
 			u8 id = FIELD_GET(EVTQ_0_ID, evt[0]);
-
+#ifdef CONFIG_ARCH_PHYTIUM
+			if (read_cpuid_id() == MIDR_PHYTIUM_FTC862 &&
+			    read_sysreg_s(SYS_AIDR_EL1) == PHYTIUM_CPU_SOCID_PS24080) {
+				u8 type = FIELD_GET(EVTQ_0_ID, evt[0]);
+				u64 addr = FIELD_GET(EVTQ_2_ADDR, evt[2]);
+
+				if (type == EVT_ID_TRANSLATION_FAULT &&
+					addr == TRANSLATE_INVALID_ADDR)
+					continue;
+			}
+#endif
 			dev_info(smmu->dev, "event 0x%02x received:\n", id);
 			for (i = 0; i < ARRAY_SIZE(evt); ++i)
 				dev_info(smmu->dev, "\t0x%016llx\n",
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index bdc1069a43f82f10019e6d5208aa675f4a0d6e0f..ddc30799151d2a7575dd2cfcfe8a0ad7013284a1 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -385,6 +385,7 @@
 #define EVTQ_MAX_SZ_SHIFT		(Q_MAX_SZ_SHIFT - EVTQ_ENT_SZ_SHIFT)
 
 #define EVTQ_0_ID			GENMASK_ULL(7, 0)
+#define EVTQ_2_ADDR			GENMASK_ULL(63, 0)
 
 /* PRI queue */
 #define PRIQ_ENT_SZ_SHIFT		4
@@ -410,6 +411,9 @@
 #define MSI_IOVA_BASE			0x8000000
 #define MSI_IOVA_LENGTH			0x100000
 
+#define TRANSLATE_INVALID_ADDR		0x0
+#define EVT_ID_TRANSLATION_FAULT	0x10
+
 enum pri_resp {
 	PRI_RESP_DENY = 0,
 	PRI_RESP_FAIL = 1,