From 4043f82c73af007046a01ef09403c3424d5a18a7 Mon Sep 17 00:00:00 2001 From: Li Guohui Date: Fri, 13 Jun 2025 17:38:56 +0800 Subject: [PATCH 1/2] anolis: arm64: Add phytium PS24080 SoC platform judgement ANBZ: #21777 This patch adds PS24080 SoC platform judgement according to MIDR encoding for FTC862 cores and its SoC ID. Signed-off-by: Li Guohui Signed-off-by: Xiao Cong Signed-off-by: Wang Yinfeng --- arch/arm64/include/asm/cputype.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 3f5ccf2b5c02..0049f546a601 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -92,6 +92,9 @@ #define PHYTIUM_CPU_PART_2000PLUS 0x662 #define PHYTIUM_CPU_PART_2004 0x663 #define PHYTIUM_CPU_PART_2500 0x663 +#define PHYTIUM_CPU_PART_FTC862 0x862 + +#define PHYTIUM_CPU_SOCID_PS24080 0x6 #define CAVIUM_CPU_PART_THUNDERX 0x0A1 #define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2 @@ -181,6 +184,7 @@ #define MIDR_FT_2000PLUS MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_2000PLUS) #define MIDR_FT_2004 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_2004) #define MIDR_FT_2500 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_2500) +#define MIDR_PHYTIUM_FTC862 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC862) #ifndef __ASSEMBLY__ -- Gitee From 5595a2708b055bb314240b5d0a209d7485975af1 Mon Sep 17 00:00:00 2001 From: Li Guohui Date: Fri, 13 Jun 2025 17:43:30 +0800 Subject: [PATCH 2/2] anolis: iommu: smmuv3: phytium: Not print information of SMMU 0x10 event ANBZ: #21777 In the Phytium PS24080 SoC platforms, when SMMU event type is 0x10 and the fault translate address is 0x0, we skip this error informfation. Due to our RC controller's inability to fully handle the MCTP protocol. Signed-off-by: Li Guohui Signed-off-by: Xiao Cong Signed-off-by: Wang Yinfeng --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 12 +++++++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 ++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 83abb8aadd93..7fa1c7f0d28d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1409,7 +1409,17 @@ static void arm_smmu_evtq_read_events(struct arm_smmu_device *smmu) do { while (!queue_remove_raw(q, evt)) { u8 id = FIELD_GET(EVTQ_0_ID, evt[0]); - +#ifdef CONFIG_ARCH_PHYTIUM + if (read_cpuid_id() == MIDR_PHYTIUM_FTC862 && + read_sysreg_s(SYS_AIDR_EL1) == PHYTIUM_CPU_SOCID_PS24080) { + u8 type = FIELD_GET(EVTQ_0_ID, evt[0]); + u64 addr = FIELD_GET(EVTQ_2_ADDR, evt[2]); + + if (type == EVT_ID_TRANSLATION_FAULT && + addr == TRANSLATE_INVALID_ADDR) + continue; + } +#endif dev_info(smmu->dev, "event 0x%02x received:\n", id); for (i = 0; i < ARRAY_SIZE(evt); ++i) dev_info(smmu->dev, "\t0x%016llx\n", diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index bdc1069a43f8..ddc30799151d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -385,6 +385,7 @@ #define EVTQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - EVTQ_ENT_SZ_SHIFT) #define EVTQ_0_ID GENMASK_ULL(7, 0) +#define EVTQ_2_ADDR GENMASK_ULL(63, 0) /* PRI queue */ #define PRIQ_ENT_SZ_SHIFT 4 @@ -410,6 +411,9 @@ #define MSI_IOVA_BASE 0x8000000 #define MSI_IOVA_LENGTH 0x100000 +#define TRANSLATE_INVALID_ADDR 0x0 +#define EVT_ID_TRANSLATION_FAULT 0x10 + enum pri_resp { PRI_RESP_DENY = 0, PRI_RESP_FAIL = 1, -- Gitee