diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index be297190b8291156a2c4be9fc0880e4bb7678c7b..8a682e57a97d8f07695fe590dddec8bc5293b4b6 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -106,6 +106,9 @@
 #define PHYTIUM_CPU_PART_2000PLUS	0X662
 #define PHYTIUM_CPU_PART_2004	0X663
 #define PHYTIUM_CPU_PART_2500	0X663
+#define PHYTIUM_CPU_PART_FTC862                0x862
+
+#define PHYTIUM_CPU_SOCID_PS24080      0x6
 
 #define CAVIUM_CPU_PART_THUNDERX	0x0A1
 #define CAVIUM_CPU_PART_THUNDERX_81XX	0x0A2
@@ -167,6 +170,7 @@
 #define MIDR_FT_2000PLUS	MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_2000PLUS)
 #define MIDR_FT_2004	MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_2004)
 #define MIDR_FT_2500	MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_2500)
+#define MIDR_PHYTIUM_FTC862 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC862)
 
 #define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35)
 #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 798d07a04107c43a013eadbb4987eef6d4b68907..d3579acfec246f5851a28a4dd464a97bf14ff2a0 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -1573,6 +1573,17 @@ static irqreturn_t arm_smmu_evtq_thread(int irq, void *dev)
 			ret = arm_smmu_handle_evt(smmu, evt);
 			if (!ret || !__ratelimit(&rs))
 				continue;
+#ifdef CONFIG_ARCH_PHYTIUM
+			if (read_cpuid_id() == MIDR_PHYTIUM_FTC862 &&
+			    read_sysreg_s(SYS_AIDR_EL1) == PHYTIUM_CPU_SOCID_PS24080) {
+				u8 type = FIELD_GET(EVTQ_0_ID, evt[0]);
+				u64 addr = FIELD_GET(EVTQ_2_ADDR, evt[2]);
+
+				if (type == EVT_ID_TRANSLATION_FAULT &&
+					addr == TRANSLATE_INVALID_ADDR)
+					continue;
+			}
+#endif
 
 			dev_info(smmu->dev, "event 0x%02x received:\n", id);
 			for (i = 0; i < ARRAY_SIZE(evt); ++i)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index f26dcb38deacb1f72f7cb798624278b6d1f02db0..d428017cc28fbb1e2ab47acb73c7755d329bc09b 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -431,6 +431,8 @@ struct arm_smmu_ste {
 #define MSI_IOVA_BASE			0x8000000
 #define MSI_IOVA_LENGTH			0x100000
 
+#define TRANSLATE_INVALID_ADDR		0x0
+
 enum pri_resp {
 	PRI_RESP_DENY = 0,
 	PRI_RESP_FAIL = 1,