diff --git a/sig/CXL/README.en.md b/sig/CXL/README.en.md new file mode 100644 index 0000000000000000000000000000000000000000..0fda99ef225469b0f42002d3480b4d52977efaa4 --- /dev/null +++ b/sig/CXL/README.en.md @@ -0,0 +1,72 @@ +## SIG Website + +https://openanolis.cn/sig/cxl + +## SIG Goal +CXL (Compute Express Link) technology is a new high-speed interconnect technology designed to provide higher data throughput and lower latency to meet the memory demands of modern computing systems. The CXL SIG will initially focus on the Intel platform combined with Agilex CXL and gradually support other architectures and platforms. It aims to assist users in the direct utilization of CXL by providing a memory management system that supports CXL. As shown in the diagram, through the CXL SIG, and centered around the current CXL-SHM and CXL-SDK open-source projects, a solid foundation is established with device manufacturers like Haiguang, Inspur, and Intel. This will strengthen the ecosystem from multiple perspectives and adequately meet the diverse business scenario needs of community developers. + +![](assets/cxl-sig-arch.png) + +## SIG Directions +Based on the current CXL hardware (Intel Agilex FPGA or Montage/Samsung CXL), we will develop support for CXL from the following aspects: +1. CXL 1.1/2.0 related drivers in Anolis OS, along with support for different types of CXL hardware. +2. A memory management system for CXL shared memory, focusing on distributed memory management from the perspective of user space, providing users with a semantically consistent distributed management mechanism and semantics. +3. An SDK for different types of CXL memory, supporting the management of heterogeneous memory, including support for PMEM and other memory types. + +## CXL in OpenAnolis +1. Anolis OS: 5.10 release support CXL1.1, Backport RCEC feature +2. Anolis OS: 6.6 release support CXL2.0 +2. RCEC feature：PCIe protocol extension，support CXL RCiEP (Root Complex Integrated Endpoints) device, PME message & terminating error +3. CXL Deive: Support FPGA based CXL and ASIC based CXL +4. WIP: Virtualization, support CXL3.0 + +## CXL Community Contribution and Use Cases + +### Community Contribution +1. CXL IDE security mechanisms and driver implementation +2. CXL PMEM management mechanisms and adaptation +3. CXL RAS drivers and adaptation +4. Open source project CXL-SHM + +### Use Cases +1. Upstream AnolisOS Community +2. Large-scale deployment in the cloud, using related drivers and features for internal products +3. Internal customers directly using CXL products, along with performance and usage optimization +4. Works published in top conferences + +## Publication +``` +[1] Partial Failure Resilient Memory Management System for (CXL-based) Distributed Shared Memory; +Mingxing Zhang, Teng Ma, Jinqi Hua, Zheng Liu, Kang Chen, Ning Ding, Fan Du, Jinlei Jiang, Tao Ma, Yongwei Wu; +The 29th ACM Symposium on Operating Systems Principles (SOSP); 2023 +[2] HydraRPC: RPC in the CXL Era; Teng Ma, Zheng Liu, Chengkun Wei, Jialiang Huang, Youwei Zhuo, Haoyu Li, Ning Zhang, Yijin Guan, Dimin Niu, Mingxing Zhang, Tao Ma; 2024 USENIX Annual Technical Conference (ATC); 2024 +[3] TrEnv: Transparently Share Serverless Execution Environments Across Different Functions and Nodes; Jialiang Huang, MingXing Zhang, Teng Ma, Zheng Liu, Sixing Lin, Kang Chen, Jinlei Jiang, Xia Liao, Yingdi Shan, Ning Zhang, Mengting Lu, Tao Ma, Haifeng Gong, YongWei Wu; The 30th ACM Symposium on Operating Systems Principles (SOSP); 2024 +[4] Revisiting Distributed Programming in the CXL Era; Teng Ma, Mingxing Zhang, Kang Chen, Jialiang Huang, Zheng Liu, Yongwei Wu; The 2nd Workshop on Hot Topics in System Infrastructure (HotInfra); 2024 +``` + +## Maintainer List +| Name | Affliation | Role | +| ------------ | ------------ | ------------ | +| [Teng Ma](https://gitee.com/stmatengss) | Alibaba | chief maintainer | +| [Hao Fu](https://gitee.com/fh87lm) | Hygon | maintainer | +| [Wei Li](https://gitee.com/allen846356) | Hygon | maintainer | +| [Kun Hu](https://gitee.com/kun-llfl) | Alibaba | maintainer | +| [Mingxing Zhang](https://gitee.com/zhang_mingxing) | Tsinghua | maintainer | +| [Haifeng Gong](https://gitee.com/gong_haifeng) | Intel | maintainer | +| [Rongfei Xu](https://gitee.com/xurongfei2023) | Inspur | maintainer | +| [Renze Zhang](https://gitee.com/buddyzhang1) | H3C | maintainer | +| Xing He | SAMSUNG | maintainer | +| June Kim | SAMSUNG | maintainer | +| Jinin So | SAMSUNG | maintainer | +| James Lim | SAMSUNG | maintainer | + +## SIG Repo + +Source code repositories: +- https://gitee.com/anolis/cxl-shm (From Alibaba) +- https://gitee.com/anolis/h3cxl (From H3C) + + +## Dingtalk Group + +![](assets/cxl-sig.png) diff --git a/sig/CXL/README.md b/sig/CXL/README.md index 941db622a039d134e1ee20e838d6793f01e34999..c32292bec6332aad20fc77a3bd84ca0db48092a3 100644 --- a/sig/CXL/README.md +++ b/sig/CXL/README.md @@ -5,12 +5,45 @@ https://openanolis.cn/sig/cxl ## SIG目标 CXL (Compute Express Link) 技术是一种新型的高速互联技术，旨在提供更高的数据吞吐量和更低的延迟，以满足现代计算系统对于内存的需求。CXL SIG会以intel平台结合Agilex CXL为基点并逐渐支持其他架构和平台，通过提供支持CXL的内存管理系统以助力用户对于CXL的直接使用。如图所示，通过CXL SIG，以当前的CXL-SHM和CXL-SDK开源项目为中心，底层以海光/浪潮/Intel等设备生产厂家为底座，结合龙蜥现有生态环境，从多角度出发强化生态领域，多层次满足社区开发者广泛的业务场景需要。 +![](assets/cxl-sig-arch.png) + ## SIG组技术方向 基于目前的CXL硬件（Intel Agilex FPGA或者澜起/三星CXL）进行开发，从以下几个方面对CXL进行支持： 1. Anolis OS中CXL1.1/2.0相关驱动，以及对于CXL不同类型硬件的支持。 2. 面向CXL共享内存的内存管理系统，这里我们主要从用户态分布式内存管理的角度，为用户提供一套语义一致的分布式管理机制和语义。 3. 面向CXL不同类型内存的SDK，支持对异构内存进行管理，支持PMEM等内存。 +## 龙蜥社区对于CXL支持程度 +1. Anolis OS: 5.10 release 支持CXL1.1，Backport RCEC特性 +2. Anolis OS: 6.6 release 支持CXL2.0 +2. RCEC特性：PCIe协议的扩展，支持CXL上的RCiEP (Root Complex Integrated Endpoints)设备，PME message & terminating error +3. CXL物理设备：目前能够支持FPGA模拟形式的CXL硬件设备，当前支持“I-Config”和“Y-Config”两种配置，CXL连接到 Node 0 的PCIe之上，虚拟成Node 2 +4. WIP：虚拟化支持，支持CXL3.0 + +## CXL社区贡献和场景案例 + +### 社区贡献 +1. CXL IDE相关安全机制和驱动实现 +2. CXL PMEM相关管理机制和适配 +3. CXL RAS相关驱动和适配 +4. 开源项目CXL-SHM + +### 场景案例 +1. Upstream龙蜥社区Anolis发行版 +2. 云上大规模部署，内部产品使用相关驱动和特性 +3. 内部客户直接使用CXL产品，以及相关性能/使用方式优化 +4. 相关内容发表在系统相关领域会议上 + +## 相关学术成果 +``` +[1] Partial Failure Resilient Memory Management System for (CXL-based) Distributed Shared Memory; +Mingxing Zhang, Teng Ma, Jinqi Hua, Zheng Liu, Kang Chen, Ning Ding, Fan Du, Jinlei Jiang, Tao Ma, Yongwei Wu; +The 29th ACM Symposium on Operating Systems Principles (SOSP); 2023 +[2] HydraRPC: RPC in the CXL Era; Teng Ma, Zheng Liu, Chengkun Wei, Jialiang Huang, Youwei Zhuo, Haoyu Li, Ning Zhang, Yijin Guan, Dimin Niu, Mingxing Zhang, Tao Ma; 2024 USENIX Annual Technical Conference (ATC); 2024 +[3] TrEnv: Transparently Share Serverless Execution Environments Across Different Functions and Nodes; Jialiang Huang, MingXing Zhang, Teng Ma, Zheng Liu, Sixing Lin, Kang Chen, Jinlei Jiang, Xia Liao, Yingdi Shan, Ning Zhang, Mengting Lu, Tao Ma, Haifeng Gong, YongWei Wu; The 30th ACM Symposium on Operating Systems Principles (SOSP); 2024 +[4] Revisiting Distributed Programming in the CXL Era; Teng Ma, Mingxing Zhang, Kang Chen, Jialiang Huang, Zheng Liu, Yongwei Wu; The 2nd Workshop on Hot Topics in System Infrastructure (HotInfra); 2024 +``` + ## 成员列表 | 成员 | 单位 | 角色 | | ------------ | ------------ | ------------ | @@ -21,11 +54,18 @@ CXL (Compute Express Link) 技术是一种新型的高速互联技术，旨在 | [Mingxing Zhang](https://gitee.com/zhang_mingxing) | Tsinghua | maintainer | | [Haifeng Gong](https://gitee.com/gong_haifeng) | Intel | maintainer | | [Rongfei Xu](https://gitee.com/xurongfei2023) | Inspur | maintainer | +| [Renze Zhang](https://gitee.com/buddyzhang1) | H3C | maintainer | +| Xing He | SAMSUNG | maintainer | +| June Kim | SAMSUNG | maintainer | +| Jinin So | SAMSUNG | maintainer | +| James Lim | SAMSUNG | maintainer | ## SIG仓库 -Source code repositories: -- https://gitee.com/anolis/cxl-shm +源码仓库: +- https://gitee.com/anolis/cxl-shm (Alibaba开源) +- https://gitee.com/anolis/h3cxl (H3C开源) + ## 小组例会 diff --git a/sig/CXL/assets/cxl-sig-arch.png b/sig/CXL/assets/cxl-sig-arch.png new file mode 100644 index 0000000000000000000000000000000000000000..f3695d44179dfdc79ac28f182d3de8f344b21078 Binary files /dev/null and b/sig/CXL/assets/cxl-sig-arch.png differ diff --git a/sig/CXL/sig-info.yaml b/sig/CXL/sig-info.yaml index 55cbee5e22ec6afcf4290465be326e51c166f504..fff0def1b643b40051b4ad1c7d10404eefe73364 100644 --- a/sig/CXL/sig-info.yaml +++ b/sig/CXL/sig-info.yaml @@ -17,6 +17,10 @@ maintainers: gitee_id: zhang_mingxing - openanolis_id: gong_haifeng gitee_id: gong_haifeng +- openanolis_id: buddyzhang1 + gitee_id: buddyzhang1 +- openanolis_id: xurongfei2023 + gitee_id: xurongfei2023 contributors: - openanolis_id: stmatengss @@ -25,3 +29,4 @@ contributors: repositories: - repo: - anolis/cxl-shm + - anolis/h3cxl