From 1d361de3b3efed147969e535859d7ce3ea80b444 Mon Sep 17 00:00:00 2001 From: Ruidong Tian Date: Fri, 20 Jun 2025 16:06:17 +0800 Subject: [PATCH 1/2] RISCV SIG: Correct linguistic descriptions and formatting problems Signed-off-by: Ruidong Tian --- sig/RISCV_SIG/README.md | 26 ++++++++++++++----- ...10\346\234\254\350\247\204\345\210\222.md" | 14 +++++----- sig/RISCV_SIG/sig-info.yaml | 1 + 3 files changed, 28 insertions(+), 13 deletions(-) diff --git a/sig/RISCV_SIG/README.md b/sig/RISCV_SIG/README.md index d8cb31cc3..714e0639c 100644 --- a/sig/RISCV_SIG/README.md +++ b/sig/RISCV_SIG/README.md @@ -1,12 +1,26 @@ -## SIG说明 +## SIG 成员 -RISCV ARCH SIG 致力于 RISCV 架构软件生态的共建和推广，以及基于 Anolis 社区 ANCK 内核支持 RISCV Vendors平台。 +排名不分先后 -## 邮件列表 -riscv-arch@lists.openanolis.cn +| 成员 | 公司 | 角色 | +| :----- | :------- | :--------- | +| 郭任 | 达摩院 | Maintainer | +| 宋卓 | 阿里云 | Maintainer | +| 王江波 | 阿里云 | Maintainer | +| 田瑞冬 | 阿里云 | Maintainer | +| 罗海洋 | ZTE | Contributors | +| 贺晏安 | 达摩院 | Contributors | +| 高睿 | ZTE | Contributors | -## 代码仓库 -https://gitee.com/anolis/cloud-kernel +## SIG 目标 + ++ 完善 Anolis OS 在内核、编译器、应用软件等层面对 RISC-V 服务器芯片的支持 ++ 完善 Anolis 社区基础设施（测试、CI、文档）对 RISC-V 架构的支持，构建良好的社区开发、讨论环境 ++ 探索云上 RISC-V 架构的端到端优化方案 ++ 孵化 RISC-V 新标准 + +## 社区资源 +镜像、软件包仓库（非正式）：https://mirrors.openanolis.cn/alt/anolis/23/ ## 钉钉群 diff --git "a/sig/RISCV_SIG/content/\346\227\266\351\227\264\347\272\277\344\270\216\347\211\210\346\234\254\350\247\204\345\210\222.md" "b/sig/RISCV_SIG/content/\346\227\266\351\227\264\347\272\277\344\270\216\347\211\210\346\234\254\350\247\204\345\210\222.md" index ae9ea269d..d213f2b62 100644 --- "a/sig/RISCV_SIG/content/\346\227\266\351\227\264\347\272\277\344\270\216\347\211\210\346\234\254\350\247\204\345\210\222.md" +++ "b/sig/RISCV_SIG/content/\346\227\266\351\227\264\347\272\277\344\270\216\347\211\210\346\234\254\350\247\204\345\210\222.md" @@ -1,14 +1,14 @@ Cloud kernel 总体规划参考 https://openanolis.cn/sig/Cloud-Kernel/doc/ 中 Cloud Kernel 产品规划章节 # 与 RISC-V 相关的内核/BaseOS 版本规划 -注：发布时间提前一个月为代码冻结时间，代码冻结第1、2周只允许合入bugfix，第3、4周原则上不在合入新补丁 +注：发布时间提前一个月为代码冻结时间，代码冻结第1、2周只允许合入bugfix，第3、4周原则上不在合入新补丁。 ## 内核 -2025.06.30: ANCK-004 支持 SG2042 -2025.09.XX: ANCK-005 支持更多 RVA23 特性 -2025.12.XX: ANCK-006 支持 RISC-V Server SoC 主要特性 +2025.06.30: ANCK-004 支持 SG2042 +2025.09.XX: ANCK-005 支持更多 RVA23 特性 +2025.12.XX: ANCK-006 支持 RISC-V Server SoC 主要特性 ## BaseOS -2025.06.30: 发布 Anolis23.3 RISC-V 预览版本，同时搭载 ANCK-6.6-004 内核 -2025.09.30: 发布 Anolis23.3 RISC-V 正式版本，同时搭载 ANCK-6.6-005 内核 +2025.06.30: 发布 Anolis23.3 RISC-V 预览版本，同时搭载 ANCK-6.6-004 内核 +2025.09.30: 发布 Anolis23.3 RISC-V 正式版本，同时搭载 ANCK-6.6-005 内核 2025.12.30: 发布 Anolis23.4 RISC-V 正式版本，使用 GCC14.3 编译，同时搭载内核待定 -# 工作细则 +# 工作内容 具体内核、BaseOS、编译器、软件优化的工作内容请到对应目录下寻找 diff --git a/sig/RISCV_SIG/sig-info.yaml b/sig/RISCV_SIG/sig-info.yaml index 0dc7d0179..81ed7f538 100644 --- a/sig/RISCV_SIG/sig-info.yaml +++ b/sig/RISCV_SIG/sig-info.yaml @@ -23,3 +23,4 @@ contributors: repositories: - repo: - anolis/cloud-kernel + - src-anolis-os/gcc-toolset-14-gcc -- Gitee From 60c59f05bd645498da0b3beaef03c17ff322fe15 Mon Sep 17 00:00:00 2001 From: Ruidong Tian Date: Thu, 26 Jun 2025 14:22:37 +0800 Subject: [PATCH 2/2] RISC-V SIG: add more RISCV patch backport planning Signed-off-by: Ruidong Tian --- sig/RISCV_SIG/README.md | 3 +- ...02\351\205\215\350\247\204\345\210\222.md" | 5 + .../ISA extension.md" | 10 ++ ...57\345\212\250\346\226\271\346\263\225.md" | 65 +++++++++ ...36\345\220\210\350\267\237\350\270\252.md" | 126 ++++++++++++++++-- ...10\346\234\254\350\247\204\345\210\222.md" | 3 + 6 files changed, 200 insertions(+), 12 deletions(-) create mode 100644 "sig/RISCV_SIG/content/BaseOS/\350\275\257\344\273\266\351\200\202\351\205\215\350\247\204\345\210\222.md" create mode 100644 "sig/RISCV_SIG/content/\345\206\205\346\240\270/ISA extension.md" create mode 100644 "sig/RISCV_SIG/content/\345\206\205\346\240\270/QEMU \345\220\257\345\212\250\346\226\271\346\263\225.md" diff --git a/sig/RISCV_SIG/README.md b/sig/RISCV_SIG/README.md index 714e0639c..53ae74e9f 100644 --- a/sig/RISCV_SIG/README.md +++ b/sig/RISCV_SIG/README.md @@ -20,8 +20,7 @@ + 孵化 RISC-V 新标准 ## 社区资源 -镜像、软件包仓库（非正式）：https://mirrors.openanolis.cn/alt/anolis/23/ - +镜像、软件包仓库（预览版）：https://mirrors.openanolis.cn/anolis/23.3/isos/GA/riscv64/ ## 钉钉群 欢迎使用钉钉扫码入群 diff --git "a/sig/RISCV_SIG/content/BaseOS/\350\275\257\344\273\266\351\200\202\351\205\215\350\247\204\345\210\222.md" "b/sig/RISCV_SIG/content/BaseOS/\350\275\257\344\273\266\351\200\202\351\205\215\350\247\204\345\210\222.md" new file mode 100644 index 000000000..5bf95b703 --- /dev/null +++ "b/sig/RISCV_SIG/content/BaseOS/\350\275\257\344\273\266\351\200\202\351\205\215\350\247\204\345\210\222.md" @@ -0,0 +1,5 @@ +# kexec +| Field | Description | PR | status | +|-------|-------------|---------|---| +| kexec-tools | [kexec-tools RISC-V port](https://lore.kernel.org/all/20250422162304.169431-1-bjorn@kernel.org/) | | +| makedumpfile | | | \ No newline at end of file diff --git "a/sig/RISCV_SIG/content/\345\206\205\346\240\270/ISA extension.md" "b/sig/RISCV_SIG/content/\345\206\205\346\240\270/ISA extension.md" new file mode 100644 index 000000000..d48659f66 --- /dev/null +++ "b/sig/RISCV_SIG/content/\345\206\205\346\240\270/ISA extension.md" @@ -0,0 +1,10 @@ +# HWprobe +| Extension | Description | upstream | anolis | owner | +|----------|----------|---------------|--------|-------| +|Smstatten| feature 状态寄存器，标明当前启用的扩展 | [Risc-V Kvm Smstateen](http://lists.infradead.org/pipermail/kvm-riscv/2023-July/004200.html) | https://gitee.com/anolis/cloud-kernel/pulls/5315 | 罗海洋（ZTE） | +|ZICBOZ| 分支指令整合为一条指令，避免分支预测 | [KVM RISC-V Conditional Operations](https://lore.kernel.org/all/20231003035226.1945725-1-apatel@ventanamicro.com/) | https://gitee.com/anolis/cloud-kernel/pulls/5469 | 罗海洋（ZTE） | +|ZICBOZ| | [riscv: report more ISA extensions through hwprobe](https://lore.kernel.org/all/20231114141256.126749-2-cleger@rivosinc.com/) | 罗海洋（ZTE） | +|Zicboz| 已合入 | [RISC-V: Enable cbo.zero in usermode](https://lwn.net/Articles/924488/) | +|Zicboz| | [RISC-V: Apply Zicboz to clear_page](https://lwn.net/Articles/924488/) | + +# Optimize \ No newline at end of file diff --git "a/sig/RISCV_SIG/content/\345\206\205\346\240\270/QEMU \345\220\257\345\212\250\346\226\271\346\263\225.md" "b/sig/RISCV_SIG/content/\345\206\205\346\240\270/QEMU \345\220\257\345\212\250\346\226\271\346\263\225.md" new file mode 100644 index 000000000..1a69d13b2 --- /dev/null +++ "b/sig/RISCV_SIG/content/\345\206\205\346\240\270/QEMU \345\220\257\345\212\250\346\226\271\346\263\225.md" @@ -0,0 +1,65 @@ +# 编译交叉工具链 + +```shell +yum install autoconf automake python3 libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo patchutils gcc gcc-c++ zlib-devel expat-devel libslirp-devel -y +git clone https://github.com/riscv-collab/riscv-gnu-toolchain.git +pushd riscv-gnu-toolchain +./configure --prefix=/opt/riscv +make linux -j +echo 'export PATH="/opt/riscv/bin:$PATH"' >> ~/.bashrc +source ~/.bashrc +popd +``` + +# 编译 QEMU +```shell +sudo yum install autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex \ + texinfo patchutils gcc gcc-c++ zlib-devel expat-devel git ninja-build python3-sphinx glib2 glib2-devel -y +git clone https://github.com/qemu/qemu.git -b v10.0.0 +pushd qemu +./configure --target-list=riscv64-softmmu +make -j +make install +popd +``` + +# 编译 opensbi +```shell +git clone https://github.com/riscv/opensbi.git +make -C opensbi \ + -j $(getconf _NPROCESSORS_ONLN) \ + CROSS_COMPILE=riscv64-unknown-linux-gnu- \ + PLATFORM=generic +``` +# 编译 edk2 +```shell +git clone --recurse-submodule git@github.com:tianocore/edk2.git +export WORKSPACE=`pwd` +export GCC5_RISCV64_PREFIX=riscv64-unknown-linux-gnu- +export PACKAGES_PATH=$WORKSPACE/edk2 +export EDK_TOOLS_PATH=$WORKSPACE/edk2/BaseTools +source edk2/edksetup.sh --reconfig +make -C edk2/BaseTools +source edk2/edksetup.sh BaseTools +build -a RISCV64 --buildtarget RELEASE -p OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc -t GCC5 +``` +# 启动 QEMU +```shell +ln -s Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT_CODE.fd ./RISCV_VIRT_CODE.fd +ln -s Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT_VARS.fd ./RISCV_VIRT_VARS.fd +ln -s opensbi/build/platform/generic/firmware/fw_dynamic.bin fw_dynamic.bin +truncate -s 32M RISCV_VIRT_CODE.fd + +truncate -s 32M RISCV_VIRT_VARS.fd + +qemu-system-riscv64 \ + -M virt,pflash0=pflash0,pflash1=pflash1,acpi=off \ + -m 4096 -smp 2 \ + -nographic \ + -device virtio-rng-pci \ + -blockdev node-name=pflash0,driver=file,read-only=on,filename=RISCV_VIRT_CODE.fd \ + -blockdev node-name=pflash1,driver=file,filename=RISCV_VIRT_VARS.fd \ + -netdev user,id=net0 \ + -device virtio-net-pci,netdev=net0 \ + -device virtio-blk-device,drive=hd0 \ + -drive file=,format=raw,id=hd0 diff --git "a/sig/RISCV_SIG/content/\345\206\205\346\240\270/RISC-V Server SoC patch \345\233\236\345\220\210\350\267\237\350\270\252.md" "b/sig/RISCV_SIG/content/\345\206\205\346\240\270/RISC-V Server SoC patch \345\233\236\345\220\210\350\267\237\350\270\252.md" index 55e1e4877..bf47fb7c4 100644 --- "a/sig/RISCV_SIG/content/\345\206\205\346\240\270/RISC-V Server SoC patch \345\233\236\345\220\210\350\267\237\350\270\252.md" +++ "b/sig/RISCV_SIG/content/\345\206\205\346\240\270/RISC-V Server SoC patch \345\233\236\345\220\210\350\267\237\350\270\252.md" @@ -1,21 +1,127 @@ + # ACPI -| Field | Description | status | +| Field | Patch List | status | |-------|-------------|---------| -| Misc. Support | common dependencies and more | | -| RHCT | HART features | | -| PPTT | HART topology (and cache) | | -|LPI |cpuidle | | -|CPPC | cpufreq | | +| Misc. Support | [ACPI: Enable ACPI_PROCESSOR for RISC-V](https://lore.kernel.org/all/20240118062930.245937-4-sunilvl@ventanamicro.com/) | | +| | [riscv: Use the same CPU operations for all CPUs](https://lore.kernel.org/r/20231121234736.3489608-4-samuel.holland@sifive.com) | | +| | [riscv: Deduplicate code in setup_smp()](https://lore.kernel.org/r/20231121234736.3489608-2-samuel.holland@sifive.com) | | +| | [drivers: base: Implement weak arch_unregister_cpu()](https://lore.kernel.org/r/E1r5R3H-00CszC-2n@rmk-PC.armlinux.org.uk) | | +| | [drivers: base: Use present CPUs in GENERIC_CPU_DEVICES](https://lore.kernel.org/r/E1r5R36-00Csz0-Px@rmk-PC.armlinux.org.uk) | | +| | [ACPI: Move ACPI_HOTPLUG_CPU to be disabled on arm64 and riscv](https://lore.kernel.org/r/E1r5R31-00Csyt-Jq@rmk-PC.armlinux.org.uk) | | +| | [arm64: PCI: Migrate ACPI related functions to pci-acpi.c](https://patch.msgid.link/20240812005929.113499-2-sunilvl@ventanamicro.com) | | +| | [RISC-V: ACPI: Enhance acpi_os_ioremap with MMIO remapping](https://lore.kernel.org/r/20231018124007.1306159-2-sunilvl@ventanamicro.com) | | +| RHCT | [clocksource/timer-riscv: ACPI: Add timer_cannot_wakeup_cpu](https://lore.kernel.org/r/20230927170015.295232-5-sunilvl@ventanamicro.com) | | +| | [RISC-V: ACPI: Update the return value of acpi_get_rhct()](https://lore.kernel.org/r/20231018124007.1306159-3-sunilvl@ventanamicro.com) | | +| | [RISC-V: ACPI: RHCT: Add function to get CBO block sizes](https://lore.kernel.org/r/20231018124007.1306159-4-sunilvl@ventanamicro.com) | | +| | [RISC-V: cacheflush: Initialize CBO variables on ACPI systems](https://lore.kernel.org/r/20231018124007.1306159-5-sunilvl@ventanamicro.com) | | +| | [RISC-V: ACPI: RHCT: Add function to get CBO block sizes](https://lore.kernel.org/r/20231018124007.1306159-4-sunilvl@ventanamicro.com) | | +| | [RISC-V: ACPI: Update the return value of acpi_get_rhct()](https://lore.kernel.org/r/20231018124007.1306159-3-sunilvl@ventanamicro.com) | | +| PPTT | [riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT](https://lore.kernel.org/r/20240617131425.7526-2-cuiyunhui@bytedance.com) | | +| | [riscv: Prevent a bad reference count on CPU nodes](https://lore.kernel.org/r/20240913080053.36636-1-mikisabate@gmail.com) | | +| | [RISC-V: Select ACPI PPTT drivers](https://lore.kernel.org/r/20240617131425.7526-3-cuiyunhui@bytedance.com) | | +|LPI | [ACPI: RISC-V: Add LPI driver](https://lore.kernel.org/r/20240118062930.245937-3-sunilvl@ventanamicro.com) | | +| | [cpuidle: RISC-V: Move few functions to arch/riscv](https://lore.kernel.org/r/20240118062930.245937-2-sunilvl@ventanamicro.com) | | +|CPPC | [ACPI: RISC-V: Add CPPC driver](https://lore.kernel.org/r/20240208034414.22579-2-sunilvl@ventanamicro.com) | | +| | [RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ](https://lore.kernel.org/r/20240208034414.22579-4-sunilvl@ventanamicro.com) | | |SPCR |serial port | | -|SRAT/SLIT| NUMA toplogy | | +|SRAT/SLIT| [Add ACPI NUMA support for RISC-V ](https://lore.kernel.org/all/cover.1718268003.git.haibo1.xu@intel.com/) | | |RINTC |APLIC, IMSIC stuffs | | |MHP |mem hotplug | | |RIMT |IOMMU stuffs | | |APEI |RAS stuffs | | |FFH |- | | |RQSC |QoS stuffs | | -# Driver + +# AIA +| Field | Description | status | +|-------|-------------|---------| +| | [RISC-V: ACPI: Add external interrupt controller support](https://lwn.net/Articles/969949/) | | +| | [Linux RISC-V AIA Support](https://lwn.net/Articles/959744/) | | +| | [RISC-V IPI Improvements](https://lwn.net/Articles/927554/) | | +# perf +| Field | Description | status | +|-------|-------------|---------| +| | [RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest](https://lwn.net/Articles/969482/) | | +| | [riscv: Add perf support to collect KVM guest statistics from host side](https://lwn.net/Articles/990081/) | | +| | [riscv: pmu: Add support for Control Transfer Records Ext.](https://lwn.net/Articles/1022367/) | | +| | [Add Counter delegation ISA extension support](https://lwn.net/Articles/962651/) | | +| | [riscv: Introduce Pseudo NMI](https://lwn.net/Articles/948524/) | | +# Power +| Field | Description | status | +|-------|-------------|---------| +| | [riscv: Idle thread using Zawrs extension](https://lwn.net/Articles/970354/) | | +# RAS +| Field | Description | status | +|-------|-------------|---------| +| SSE | [riscv: add support for SBI Supervisor Software Events](https://lwn.net/Articles/1001446/) | | +| APEI | [Add RAS support for RISC-V architecture](https://lwn.net/Articles/1012226/) | | +| TRAP | [riscv: Add support for Ssdbltrp extension](https://lwn.net/Articles/970359/) | | + +# IOMMU +| Field | Description | status | +|-------|-------------|---------| +| | [Linux RISC-V IOMMU Support](https://lwn.net/Articles/938638/) | | +| | [iommu/riscv: Add irqbypass support](https://lwn.net/Articles/998203/) | | +| | [riscv: iommu: Support Svnapot](https://lwn.net/Articles/1013736/) | | +| | [RISC-V IOMMU HPM and nested IOMMU support](https://lwn.net/Articles/978457/) | | +| | [Linux RISC-V IOMMU Support](https://lwn.net/Articles/938638/) | | + +# Qos +| Field | Description | status | +|-------|-------------|---------| +| | [RISC-V: Detect Ssqosid extension and handle sqoscfg CSR](https://lwn.net/Articles/930620/) | | +| | [RISC-V: QoS: add CBQRI resctrl interface](https://lwn.net/Articles/929553/) | | + +# timer +| Field | Description | status | +|-------|-------------|---------| +| | [Add Sstc extension support](https://lwn.net/Articles/886863/) | | + +# SBI +| Field | Description | upstream | anolis | owner | +|-------|-------------|---------|-------|------| +| | [Linux SBI MPXY and RPMI drivers](https://lwn.net/Articles/1022473/) | | +| DBCN | SBI DBCN 扩展支持 | [RISC-V SBI debug console extension support](https://lore.kernel.org/all/20231124070905.1043092-1-apatel@ventanamicro.com/) | https://gitee.com/anolis/cloud-kernel/pulls/5472 | 田瑞冬（阿里云）| + +# Opt +| Field | Description | status | +|-------|-------------|---------| +| | [riscv: ASID-related and UP-related TLB flush enhancements](https://lwn.net/Articles/956703/) | | +| | [riscv: optimize memcpy/memmove/memset](https://lwn.net/Articles/959885/) | | +| | [riscv: Add Native/Paravirt qspinlock support](https://lwn.net/Articles/944111/) | | +| | [riscv: ASID-related and UP-related TLB flush enhancements](https://lwn.net/Articles/956703/) | | +| | [riscv: Add Zicbop & prefetchw support](https://lwn.net/Articles/956463/) | | +| | [riscv: report more ISA extensions through hwprobe](https://lwn.net/Articles/950530/) | | +| | [RISC-V: Optimize memset for data sizes less than 16 bytes](https://lwn.net/Articles/931594/) | | +| | [Zacas/Zabha support and qspinlocks](https://lwn.net/Articles/982278/) | | +| | [riscv: Optimize bitops with Zbb extension](https://lwn.net/Articles/949402/)| | +# Mem +| Field | Description | status | +|-------|-------------|---------| +| | [RISC-V: mm: Make SV48 the default address space](https://lwn.net/Articles/937671/) | | +| | [riscv: Memory Hot(Un)Plug support](https://lwn.net/Articles/977258/) | | +| | [riscv: Introduce 64K base page](https://lwn.net/Articles/952722/) | | +| | [Add Svade and Svadu Extensions Support](https://lwn.net/Articles/980016/) | | +| | [riscv: Introduce 64K base page](https://lwn.net/Articles/952722/) | | +| | [RISC-V: Add dynamic TSO support](https://lwn.net/Articles/961587/) | | + +# KVM +| Field | Description | status | +|-------|-------------|---------| +| | [Risc-V Kvm Smstateen](https://lwn.net/Articles/944667/) | | +| | [MMU related improvements for KVM RISC-V](https://lwn.net/Articles/1023935/) | | +| | [RISC-V: KVM: Implement guest external interrupt line management](https://lwn.net/Articles/932148/) | | +| | [riscv: KVM perf support](https://lwn.net/Articles/921972/) | | +| | [RISC-V: KVM: Allow Svvptc/Zabha/Ziccrse exts for guests](https://lwn.net/Articles/1000289/) | | + +# UEFI +| Field | Description | status | +|-------|-------------|---------| +| | [RISC-V: enable XIP](https://lwn.net/Articles/852119/) | | + +# TEE | Field | Description | status | |-------|-------------|---------| -| AIA | | | -| IOMMU | | | \ No newline at end of file +| | [RISC-V CoVE support](https://lwn.net/Articles/929690/) | | +# TODO +| | [Support Zve32[xf] and Zve64[xfd] Vector subextensions](https://lwn.net/Articles/973117/) | | \ No newline at end of file diff --git "a/sig/RISCV_SIG/content/\346\227\266\351\227\264\347\272\277\344\270\216\347\211\210\346\234\254\350\247\204\345\210\222.md" "b/sig/RISCV_SIG/content/\346\227\266\351\227\264\347\272\277\344\270\216\347\211\210\346\234\254\350\247\204\345\210\222.md" index d213f2b62..7e4897284 100644 --- "a/sig/RISCV_SIG/content/\346\227\266\351\227\264\347\272\277\344\270\216\347\211\210\346\234\254\350\247\204\345\210\222.md" +++ "b/sig/RISCV_SIG/content/\346\227\266\351\227\264\347\272\277\344\270\216\347\211\210\346\234\254\350\247\204\345\210\222.md" @@ -9,6 +9,9 @@ Cloud kernel 总体规划参考 https://openanolis.cn/sig/Cloud-Kernel/doc/ 中 2025.06.30: 发布 Anolis23.3 RISC-V 预览版本，同时搭载 ANCK-6.6-004 内核 2025.09.30: 发布 Anolis23.3 RISC-V 正式版本，同时搭载 ANCK-6.6-005 内核 2025.12.30: 发布 Anolis23.4 RISC-V 正式版本，使用 GCC14.3 编译，同时搭载内核待定 +## 镜像源 +https://mirrors.openanolis.cn/anolis/23.3/isos/GA/riscv64/ +https://mirrors.openanolis.cn/anolis/23.3/os/riscv64/os/Packages/ # 工作内容 具体内核、BaseOS、编译器、软件优化的工作内容请到对应目录下寻找 -- Gitee