From 8367a0857ebb913b0d2ef66f393503bd9d96748a Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 24 Feb 2023 17:23:17 +0800 Subject: [PATCH 1/4] ttm: disallow cached mapping Signed-off-by: Icenowy Zheng --- drivers/gpu/drm/drm_gem_vram_helper.c | 2 +- drivers/gpu/drm/drm_vm.c | 5 +++-- drivers/gpu/drm/ttm/ttm_bo_util.c | 5 ++++- drivers/gpu/drm/ttm/ttm_module.c | 4 ++-- drivers/gpu/drm/ttm/ttm_resource.c | 6 ++++-- drivers/gpu/drm/ttm/ttm_tt.c | 2 +- 6 files changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c b/drivers/gpu/drm/drm_gem_vram_helper.c index 125160b53..fb29f3b43 100644 --- a/drivers/gpu/drm/drm_gem_vram_helper.c +++ b/drivers/gpu/drm/drm_gem_vram_helper.c @@ -881,7 +881,7 @@ static struct ttm_tt *bo_driver_ttm_tt_create(struct ttm_buffer_object *bo, if (!tt) return NULL; - ret = ttm_tt_init(tt, bo, page_flags, ttm_cached, 0); + ret = ttm_tt_init(tt, bo, page_flags, ttm_uncached, 0); if (ret < 0) goto err_ttm_tt_init; diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c index f024dc939..440dd8c53 100644 --- a/drivers/gpu/drm/drm_vm.c +++ b/drivers/gpu/drm/drm_vm.c @@ -69,11 +69,11 @@ static pgprot_t drm_io_prot(struct drm_local_map *map, pgprot_t tmp = vm_get_page_prot(vma->vm_flags); #if defined(__i386__) || defined(__x86_64__) || defined(__powerpc__) || \ - defined(__mips__) || defined(__loongarch__) + defined(__mips__) || defined(__loongarch__) || defined(__riscv) if (map->type == _DRM_REGISTERS && !(map->flags & _DRM_WRITE_COMBINING)) tmp = pgprot_noncached(tmp); else - tmp = pgprot_writecombine(tmp); + tmp = pgprot_noncached(tmp); #elif defined(__ia64__) if (efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start)) @@ -93,6 +93,7 @@ static pgprot_t drm_dma_prot(uint32_t map_type, struct vm_area_struct *vma) #if defined(__powerpc__) && defined(CONFIG_NOT_COHERENT_CACHE) tmp = pgprot_noncached_wc(tmp); #endif + tmp = pgprot_noncached(tmp); return tmp; } diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index fa04e6220..8327e9651 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -326,6 +326,7 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo, if (ret) return ret; +#if 0 if (num_pages == 1 && ttm->caching == ttm_cached) { /* * We're mapping a single page, and the desired @@ -335,7 +336,9 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo, map->bo_kmap_type = ttm_bo_map_kmap; map->page = ttm->pages[start_page]; map->virtual = kmap(map->page); - } else { + } else +#endif + { /* * We need to use vmap to get the desired page protection * or to make the buffer object look contiguous. diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c index b3fffe7b5..fcdc5aaa4 100644 --- a/drivers/gpu/drm/ttm/ttm_module.c +++ b/drivers/gpu/drm/ttm/ttm_module.c @@ -63,7 +63,7 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp) { /* Cached mappings need no adjustment */ if (caching == ttm_cached) - return tmp; + caching = ttm_write_combined; #if defined(__i386__) || defined(__x86_64__) if (caching == ttm_write_combined) @@ -80,7 +80,7 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp) else tmp = pgprot_noncached(tmp); #endif -#if defined(__sparc__) +#if defined(__sparc__) || defined(__riscv) tmp = pgprot_noncached(tmp); #endif return tmp; diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c index a729c32a1..c2b68b774 100644 --- a/drivers/gpu/drm/ttm/ttm_resource.c +++ b/drivers/gpu/drm/ttm/ttm_resource.c @@ -183,7 +183,7 @@ void ttm_resource_init(struct ttm_buffer_object *bo, res->bus.addr = NULL; res->bus.offset = 0; res->bus.is_iomem = false; - res->bus.caching = ttm_cached; + res->bus.caching = ttm_write_combined; res->bo = bo; man = ttm_manager_type(bo->bdev, place->mem_type); @@ -669,16 +669,18 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io, iter_io->needs_unmap = true; memset(&iter_io->dmap, 0, sizeof(iter_io->dmap)); - if (mem->bus.caching == ttm_write_combined) + if (mem->bus.caching == ttm_write_combined || mem->bus.caching == ttm_cached) iosys_map_set_vaddr_iomem(&iter_io->dmap, ioremap_wc(mem->bus.offset, bus_size)); +#if 0 else if (mem->bus.caching == ttm_cached) iosys_map_set_vaddr(&iter_io->dmap, memremap(mem->bus.offset, bus_size, MEMREMAP_WB | MEMREMAP_WT | MEMREMAP_WC)); +#endif /* If uncached requested or if mapping cached or wc failed */ if (iosys_map_is_null(&iter_io->dmap)) diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index d50560393..c5b7647f1 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -136,7 +136,7 @@ static void ttm_tt_init_fields(struct ttm_tt *ttm, unsigned long extra_pages) { ttm->num_pages = (PAGE_ALIGN(bo->base.size) >> PAGE_SHIFT) + extra_pages; - ttm->caching = ttm_cached; + ttm->caching = ttm_write_combined; ttm->page_flags = page_flags; ttm->dma_address = NULL; ttm->swap_storage = NULL; -- Gitee From cfd29aed10ad4210dbe243ca2520f961fcf5ba85 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 21 Jun 2024 15:10:31 +0800 Subject: [PATCH 2/4] radeon/amdgpu: force 32-bit dma Signed-off-by: Icenowy Zheng --- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++-- drivers/gpu/drm/radeon/radeon_device.c | 2 +- 7 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index f513e2c2e..b71d8c044 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -978,13 +978,13 @@ static int gmc_v10_0_sw_init(void *handle) */ adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ - r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); + r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(32)); if (r) { printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); return r; } - adev->need_swiotlb = drm_need_swiotlb(44); + adev->need_swiotlb = drm_need_swiotlb(32); r = gmc_v10_0_mc_init(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 96e0bb5be..83e5807db 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -790,13 +790,13 @@ static int gmc_v11_0_sw_init(void *handle) */ adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ - r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); + r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(32)); if (r) { printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); return r; } - adev->need_swiotlb = drm_need_swiotlb(44); + adev->need_swiotlb = drm_need_swiotlb(32); r = gmc_v11_0_mc_init(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index ec291d28e..18589add9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -837,12 +837,12 @@ static int gmc_v6_0_sw_init(void *handle) adev->gmc.mc_mask = 0xffffffffffULL; - r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); + r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(32)); if (r) { dev_warn(adev->dev, "No suitable DMA available.\n"); return r; } - adev->need_swiotlb = drm_need_swiotlb(40); + adev->need_swiotlb = drm_need_swiotlb(32); r = gmc_v6_0_init_microcode(adev); if (r) { diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 979da6f51..ba5549efd 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -1016,12 +1016,12 @@ static int gmc_v7_0_sw_init(void *handle) */ adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ - r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); + r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(32)); if (r) { pr_warn("No suitable DMA available\n"); return r; } - adev->need_swiotlb = drm_need_swiotlb(40); + adev->need_swiotlb = drm_need_swiotlb(32); r = gmc_v7_0_init_microcode(adev); if (r) { diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 382dde1ce..bd5b81d17 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1138,12 +1138,12 @@ static int gmc_v8_0_sw_init(void *handle) */ adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ - r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); + r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(32)); if (r) { pr_warn("No suitable DMA available\n"); return r; } - adev->need_swiotlb = drm_need_swiotlb(40); + adev->need_swiotlb = drm_need_swiotlb(32); r = gmc_v8_0_init_microcode(adev); if (r) { diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 67ca16a80..a46956637 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1677,12 +1677,12 @@ static int gmc_v9_0_sw_init(void *handle) adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ dma_addr_bits = adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ? 48:44; - r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); + r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(32)); if (r) { printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); return r; } - adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); + adev->need_swiotlb = drm_need_swiotlb(32); r = gmc_v9_0_mc_init(adev); if (r) diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index a556b6be1..8cec7fbf1 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -1359,7 +1359,7 @@ int radeon_device_init(struct radeon_device *rdev, * AGP - generally dma32 is safest * PCI - dma32 for legacy pci gart, 40 bits on newer asics */ - dma_bits = 40; + dma_bits = 32; if (rdev->flags & RADEON_IS_AGP) dma_bits = 32; if ((rdev->flags & RADEON_IS_PCI) && -- Gitee From 6ffdccac308ae770b238ada5000abb30c639077c Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 7 Jul 2024 16:33:21 +0800 Subject: [PATCH 3/4] very dirty hack to allocate memory for new AMD cards Signed-off-by: Icenowy Zheng --- drivers/pci/setup-bus.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index b4096598d..b59ca6b6d 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1074,6 +1074,8 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, min_align = calculate_mem_align(aligns, max_order); min_align = max(min_align, window_alignment(bus, b_res->flags)); size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), min_align); + if (size0 == 0x18000000U) + size0 = 0x16000000U; add_align = max(min_align, add_align); size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 : calculate_memsize(size, min_size, add_size, children_add_size, -- Gitee From 919e751b41c42bc566e07d05d3079599cfcd90bc Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 11 Oct 2024 14:19:03 +0800 Subject: [PATCH 4/4] drm/radeon: mask MSI on K1x Signed-off-by: Icenowy Zheng --- drivers/gpu/drm/radeon/radeon_irq_kms.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c index da2173435..7a7b491d6 100644 --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c +++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c @@ -236,6 +236,11 @@ static bool radeon_msi_ok(struct radeon_device *rdev) if (rdev->flags & RADEON_IS_AGP) return false; +#if IS_ENABLED(CONFIG_SOC_SPACEMIT_K1X) + /* Chips <= GCN1 cannot get MSI to work on K1 */ + return false; +#endif + /* * Older chips have a HW limitation, they can only generate 40 bits * of address for "64-bit" MSIs which breaks on some platforms, notably -- Gitee