From c47140c9cec4256ffada987bac9eef31fa2bec07 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Tue, 17 Oct 2023 21:40:20 +0000 Subject: [PATCH 1/2] mtd: spi-nor: Add support for XMC XM25QU128C Add support for XMC XM25QU128C (128M-bit) Serial Flash memory. Used on the Xunlong Orange Pi 3B, 5 and 5 Plus boards. Datasheet: https://www.xmcwh.com/uploads/806/XM25QU128C_Ver2.0.pdf Signed-off-by: Ricardo Pardini [jonas@kwiboo.se: update commit message] Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Signed-off-by: Icenowy Zheng --- drivers/mtd/spi/spi-nor-ids.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 14a79746..76b44d48 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -450,6 +450,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("XM25QU128C", 0x204118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif #ifdef CONFIG_SPI_FLASH_XTX /* XTX Technology (Shenzhen) Limited */ -- Gitee From 0c71eb9379be2a1e6518380c51a880ffeb4cb185 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 7 Apr 2025 17:42:10 +0800 Subject: [PATCH 2/2] riscv: dts: orangepi-rv2: fix pcie The board features a PCIe power controlling GPIO and two M.2 slots (one 2280 to pcie1_rc and one 2230 to pcie2_rc). Fix the DT definition of these PCIe controllers. Signed-off-by: Icenowy Zheng --- arch/riscv/dts/k1-x_orangepi-rv2.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/dts/k1-x_orangepi-rv2.dts b/arch/riscv/dts/k1-x_orangepi-rv2.dts index 5a68bafe..219700f4 100644 --- a/arch/riscv/dts/k1-x_orangepi-rv2.dts +++ b/arch/riscv/dts/k1-x_orangepi-rv2.dts @@ -245,6 +245,13 @@ &pcie1_rc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie1_3>; + k1x,pwr_on = <&gpio 116 0>; + status = "okay"; +}; + +&pcie2_rc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie2_4>; status = "okay"; }; -- Gitee