# FPGA-ZynqNet

**Repository Path**: biasbb/FPGA-ZynqNet

## Basic Information

- **Project Name**: FPGA-ZynqNet
- **Description**: FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS 
- **Primary Language**: C++
- **License**: GPL-3.0
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 1
- **Created**: 2019-08-11
- **Last Updated**: 2020-12-19

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# FPGA-ZynqNet
FPGA-based CNN accelerator developed by Vivado HLS.  
ZynqNet(https://github.com/dgschwend/zynqnet) is a Convolution Neural Network designed for ImageNet classification which is similar to SqueezeNet-V1.1

Quantization: 8-bit dynamic fixed point  
Environment: Vivado HLS 2016.4  
Target Device: xc7k325tffg900-2

Usage:  
    1.Open Vivado HLS Command Prompt  
    2.Change to source file direction  
    3.Type "vivado_hls -f run_hls.tcl" to create HLS project  
    4.Type "vivado_hls -p proj_ZynqNet" to open HLS project