# awesome-spinalhdl

**Repository Path**: courageheart/awesome-spinalhdl

## Basic Information

- **Project Name**: awesome-spinalhdl
- **Description**: No description available
- **Primary Language**: Scala
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2025-10-09
- **Last Updated**: 2025-10-09

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# Awesome SpinalHDL
This is a curated list of SpinalHDL projects, libraries, and learning resources.

Feel free to open a merge request if you would like to see anything added.

## Learning Resources
* [SpinalHDL Documentation](https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html)
* [Spinal-bootcamp](https://github.com/jijingg/Spinal-bootcamp) - Tutorial based on Jupyter Notebook
* [SpinalHDL labs](https://github.com/SpinalHDL/SpinalWorkshop) - Labs to learn SpinalHDL

## CPU
* [VexRiscV](https://github.com/SpinalHDL/VexRiscv) - A FPGA friendly 32 bit RISC-V CPU implementation
* [VexiiRiscv](https://github.com/SpinalHDL/VexiiRiscv) - Successor to VexRiscV
* [NaxRiscv](https://github.com/SpinalHDL/NaxRiscv) - Superscalar RISC-V core
* [J1Sc](https://github.com/SteffenReith/J1Sc) - A reimplementation of a tiny stack CPU
* [NOP-Core](https://github.com/NOP-Processor/NOP-Core) - High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
* [FPGACosmacELF](https://github.com/wel97459/FPGACosmacELF) - A re-creation of a Cosmac ELF computer
* [Proteus](https://github.com/proteus-core/proteus) - The SpinalHDL design of the Proteus core, an extensible RISC-V core.
* [flare32_cpu](https://github.com/fl4shk/flare32_cpu) - 32-bit CPU
* [shdl6800](https://github.com/GuzTech/shdl6800) - 6800 processor
* [MIPS CPU](https://github.com/dhy2000/spinalhdl-mips-cpu) - MIPS with 5-stage pipeline
* [OPCSH](https://github.com/riktw/OPCSH) - One Page CPU
* [Subleq Spinalhdl](https://github.com/stopnoanime/subleq-spinalhdl) - Subleq CPU
* [MicroRV32](https://github.com/agra-uni-bremen/microrv32) - FPGA Suitable RTL Implementation of RISC-V RV32
* [mr1](https://github.com/tomverbeure/mr1) - Formally verified RISC-V CPU
* [LAS32](https://github.com/ay-tony/LAS32) - Loongarch 32-bits Reduced ISA CPU
* [eepyu](https://github.com/64/eepyu) - 4-stage pipelined RISC-V CPU

## SoC
* [SaxonSoc](https://github.com/SpinalHDL/SaxonSoc) - SoC based on VexRiscv and ICE40 UP5K

## Neural Network Accelerators
* [SpinalHDL\_CNN\_Accelerator](https://github.com/19801201/SpinalHDL_CNN_Accelerator) -  CNN accelerator implemented with Spinal HDL
* [SpAtten](https://github.com/mit-han-lab/spatten-llm) -  [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
* [SpinalResNet](https://github.com/yportne13/SpinalResNet) - AdderNet ResNet20 for cifar10

## I/O
* [FPGA-PWM Module](https://github.com/Ncerzzk/FPGA-PWM) -  A FPGA-based PWM module with support for I2C and SPI

## Memory
* [Clio](https://github.com/WukLab/Clio) - Disaggregated memory system that virtualizes, protects, and manages disaggregated memory at hardware-based memory nodes
* [FPGA Multiport RAMs](https://github.com/voldemoriarty/fpga-mprams) - FPGA friendly Multiport memories (N-read-M-write) based on LVT

## Math
* [math](https://github.com/tomverbeure/math) - SpinalHDL Hardware Floating Point Math Library
* [fpu-wrappers](https://github.com/jiegec/fpu-wrappers) -  Wrappers for open source FPU hardware implementations.
* [SpinalHDL Integer Divider](https://github.com/janschiefer/SpinalHDLIntegerDivider) - Integer division module
* [PiMAC](https://github.com/SteffenReith/PiMAC) - Pipelined multiplier

## Cryptography
* [SpinalCrypto](https://github.com/SpinalHDL/SpinalCrypto) - Cryptography library
* [Poseidon-SpinalHDL](https://github.com/datenlord/poseidon-spinal) - Implementation of Poseidon hash function
* [xoroshiro](https://github.com/ZiCog/xoroshiro) - xoroshiro32++ and xoroshiro64++ PRNG algorithms

## Networking
* [SpinalCorundum](https://github.com/brightai-nl/SpinalCorundum) - Components for Corundum Ethernet
* [BlackwireSpinal](https://github.com/brightai-nl/BlackwireSpinal) - Components implementing WireGuard primitives for Corundum Ethernet
* [Programmed I/O (PIO) NIC on Enzian](https://github.com/KireinaHoro/enzian-pio-nic) - Network interface card with PCI-E for Enzian platform
* [SpinalHDL-ethernet](https://github.com/jjyy-Huang/SpinalHDL-ethernet) - A UDP/IP Tx/Rx Component for Xilinx 100GbE Ethernet-Subsystem (MRMAC/CMAC)

## Signal Processing
* [SpinalFFT](https://github.com/wswslzp/SpinalFFT) - A FFT hardware generator in SpinalHDL
* [FFT\_Radix\_6](https://github.com/QiaoHui7/FFT_Radix_6/tree/main) -  FFT Radix-6 design
* [Chainsaw](https://github.com/Chainsaw-Team/Chainsaw) - A hardware design library for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communication and Crypto applications

## Audio
* [spinal\_synth](https://github.com/lawrie/spinal_synth) - Simple synth

## Graphics
* [rt](https://github.com/tomverbeure/rt) - A Full Hardware Real-Time Ray-Tracer

## Utils

* [SpinalUtils](https://github.com/xueweiwujxw/SpinalUtils) - A collection of utils based on SpinalHDL, including scripts for Xilinx IP cores integration, Vivado flow, and implementations of algorithms such as CRC checksums, M-sequence generator and detector and etc.