# Design_Digital_Systems_2

**Repository Path**: david6chen/Design_Digital_Systems_2

## Basic Information

- **Project Name**: Design_Digital_Systems_2
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 1
- **Created**: 2021-08-10
- **Last Updated**: 2023-06-26

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# Design_Digital_Systems_2
Verification of RTL modules according specific requirements.

Testbenches created manually and by "formal verification" and validation done by immediate and concurrent assertions. Constrained randomisation and functional coverage.

Implementation done in SystemVerilog. The IDE used was a text editor under Linux OS.

Lecture from master "Electronic Systems Design" in NTNU Trondheim.