# Open_RegModel

**Repository Path**: david6chen/Open_RegModel

## Basic Information

- **Project Name**: Open_RegModel
- **Description**: https://systemrdl.github.io/RALBot-html
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 1
- **Created**: 2021-08-25
- **Last Updated**: 2023-06-26

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# openreg
---
Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs using SystemRDL.

## Directory Structure

In this repository, you will find:
  * tools -- tools used for building the reg models.
  * spec -- REG configuration option settings.
  * outdir -- generate register RTL and UVM regmodel dir.

```
├── outdir
│   └── pico_def_demo
│       └── spec
│           ├── defs
│           ├── manual
│           │   ├── accelera-generic_example
│           │   │   └── docs
│           │   ├── hwa_wrapper
│           │   │   └── docs
│           └── odif
├── spec
│   ├── defs            -- define file location(not used in our project)
│   ├── manual          -- *.rdl register description file location
│   │   └── RALBot-gen  -- ralbotgen python scripts(used to generate header file, uvm regmodel and html doc) 
|   |
│   └── odif            -- (not used in our project)
│       └── gen
└── tools               -- build tools
    ├── bin
    ├── etc
    └── make
```

| Directory               | Name	Description        |
|---                      |---                         |
| *.h                     | C header files             |
| *.svh                   | SystemVerilog header files |
| *_uvmreg.sv/*uvm_reg.sv | UVM register model         |
| */docs                  | Html document              |
| *_reg.v                 | Register RTL file          |

## Using the openreg tools
first， modify tree.make，change tools path to your supports

`%> ./tools/bin/tmake`