# core-v-xif

**Repository Path**: david6chen/core-v-xif

## Basic Information

- **Project Name**: core-v-xif
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: main
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2021-06-28
- **Last Updated**: 2021-06-28

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# CORE-V X-Interface

The CORE-V X-Interface (core-v-xif) is a RISC-V extension interface that provides a generalized framework suitable to implement custom co-processors and ISA extensions for existing RISC-V CPU cores.
It features independent channels for accelerator-agnostic offloading of instructions and writeback of the result, pseudo dual-issue behaviour and configurable sharing granularity of external functional units.
A more thourough documentation can be found in the [doc](doc/index.md) folder.

## List of Modules

| Name               | Description                                                                 | Status        |
| ----               | -----------                                                                 | ------        |
| `acc_intf`         | Systemverilog interface definition of the `X/C-` and `XMem/CMem-Interface`. | active (v0.1) |
| `acc_interconnect` | Instruction offload and response interconnect.                              | active (v0.1) |
| `acc_adapter`      | Accelerator-agnostic offloading adapter.                                    | active (v0.1) |
| `acc_predecoder`   | Accelerator-specific instruction predecoder.                                | active (v0.1) |