# easysim

**Repository Path**: david6chen/easysim

## Basic Information

- **Project Name**: easysim
- **Description**: No description available
- **Primary Language**: Python
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2022-02-17
- **Last Updated**: 2023-06-26

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README


# Intro.

This is a simple and quick simulation tool for module level design.

Support the following features:
- run simulation with irun, xrun or vcs
- debug with verdi
- view rtl only with verdi

# Usage:

0. make sure you have installed python3 and git
1. git clone https://gitee.com/exasic/easysim 
2. copy rtl to rtl directory
3. edit sim/conf/conf.json
4. go to sim/rsim directory and run cmd `./run_sim.py`

Example:
1. Run simulation with Cadence Incisive

```
  python3 run_sim.py -tc=tc_sanity
  python3 run_sim.py -top=iic -tc=tc_sanity
```

2. Run Verdi

```
  python3 run_sim.py -verdi
  python3 run_sim.py -verdi -tc=tc_sanity
  python3 run_sim.py -verdi -top=iic -tc=tc_sanity
```

3. View RTL

```
  python3 run_sim.py -rtl_view
  python3 run_sim.py -rtl_view -top=iic
```

4. Switch Cadence Incisive to Synopsys VCS

  Edit conf.json, add "simulator"="vcs"
  
5. Print final command line info only for debug

```
  python3 run_sim.py ...  -dryrun
```
  
6. Specify or override fron conf file

  Edit conf.json, add "timescale=1ns/1ps", or "override_timescale=1ns/1ps"


v1.1版支持：

切换仿真器irun、xrun、vcs，在conf.json里指定。

支持打开Verdi，并支持只打开RTL。

增加了options可以仿真fpga代码，支持多顶层。

增加了dryrun，只打印最终的cmd，但不运行，方便调试脚本本身的错误。

支持灵活的timescale，功能仿真用粗精度，后仿用高精度，支持从conf文件里覆盖timescale。



快速建立环境
make sure you have installed python3 and git

git clone https://gitee.com/exasic/easysim

copy rtl to rtl directory

edit sim/conf/conf.json

go to sim/rsim directory and run cmd ./run_sim.py

使用方法
Run simulation with Cadence Incisive

  python3 run_sim.py -tc=tc_sanity
  python3 run_sim.py -top=iic -tc=tc_sanity
Run Verdi

  python3 run_sim.py -verdi
  python3 run_sim.py -verdi -tc=tc_sanity
  python3 run_sim.py -verdi -top=iic -tc=tc_sanity
View RTL

  python3 run_sim.py -rtl_view
  python3 run_sim.py -rtl_view -top=iic
Switch Cadence Incisive to Synopsys VCS

Edit conf.json, add "simulator"="vcs"

Print final command line info only for debug

  python3 run_sim.py ...  -dryrun
Specify or override fron conf file

Edit conf.json, add "timescale=1ns/1ps", or "override_timescale=1ns/1ps"





下载链接
EasySim 1.1

https://gitee.com/exasic/easysim