# RV-JTAG-VIP

**Repository Path**: david6chen/rv-jtag-vip

## Basic Information

- **Project Name**: RV-JTAG-VIP
- **Description**: RISCV JTAG VIP
- **Primary Language**: Verilog
- **License**: MIT
- **Default Branch**: main
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 2
- **Forks**: 0
- **Created**: 2024-05-10
- **Last Updated**: 2025-07-16

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# RV-JTAG-VIP


## usage1

1. instantiate and connect interface
2. instantiate rv_jtag and configure virutal interface
3. call write_SYS_reg()/read_SYS_reg() access system register
```sv
rv_jtag jtag = rv_jtag::type_id::create("jtag");
jtag.vif = rv_jtag_if;
jtag.trst_rst();
jtag.tms_rst();
// access system register via DAP
jtag.write_SYS_reg(base_addr, addr, data);
jtag.read_SYS_reg(base_addr, addr, data);
```

## usage2

1. instantiate and connect interface
2. instantiate rv_jtag and configure virutal interface
3. call write_DM_reg()/read_DM_reg() access debug module register
```sv
rv_jtag jtag = rv_jtag::type_id::create("jtag");
jtag.vif = rv_jtag_if;
jtag.trst_rst();
jtag.tms_rst();
// access system register via DP
jtag.write_DM_reg(addr, data);
jtag.read_DM_reg(addr, data);
```