# mips-cpu

**Repository Path**: debug-zhang/mips-cpu

## Basic Information

- **Project Name**: mips-cpu
- **Description**: This is a MIPS32 CPU implemented in Verilog.
- **Primary Language**: Verilog
- **License**: Apache-2.0
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 1
- **Forks**: 0
- **Created**: 2021-12-31
- **Last Updated**: 2025-06-18

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# MIPS CPU

This is a MIPS32 CPU implemented in Verilog.

## Features

- 5-stage pipline
- forwarding & stalling
- branch delay slot

## Software
- Xilinx ISE
- MARS (MIPS32 assemble simulator)
- Logisim (interactive circuits simulator)

## Instruction Set

- MIPS32 instructions
  - CPU Arithmetic Instructions 14
    - ADD
    - ADDI
    - ADDIU
    - ADDU
    - DIV
    - DIVU
    - MULT
    - MULTU
    - SLT
    - SLTI
    - SLTIU
    - SLTU
    - SUB
    - SUBU
  - CPU Branch and Jump Instructions 10
    - BEQ
    - BGEZ
    - BGTZ
    - BLEZ
    - BLTZ
    - BNE
    - J
    - JAL
    - JALR
    - JR
  - CPU Instruction Control Instructions 1
    - NOP
  - CPU Load, Store, and Memory Control Instructions 8
    - LB
    - LBU
    - LH
    - LHU
    - LW
    - SB
    - SH
    - SW
  - CPU Logical Instructions 8
    - AND
    - ANDI
    - OR
    - ORI
    - XOR
    - XORI
    - NOR
    - LUI
  - CPU Insert/Extract Instructions 0
  - CPU Move Instructions 4
    - MFHI
    - MFLO
    - MTHI 
    - MTLO
  - CPU Shift Instructions 6
    - SLL
    - SRL
    - SRA
    - SLLV
    - SRLV
    - SRAV
  - CPU Trap Instructions 0
  - Obsolete1 CPU Branch Instructions 0
  - FPU and cop2 not included
  - Privileged Instructions 0
  - EJTAG Instructions 0

stay tuned...