# Mips-cpu-logisim-version

**Repository Path**: dongfenga/Mips-cpu-logisim-version

## Basic Information

- **Project Name**: Mips-cpu-logisim-version
- **Description**: Mips cpu built by logisim, include single cycle cpu, single cycle cpu with trap(interrupt), 5 stage pipeline with BHT
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 2
- **Forks**: 1
- **Created**: 2020-07-01
- **Last Updated**: 2023-07-05

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# Mips-cpu-logisim-version

Mips cpu built by logisim, include single cycle cpu, single cycle cpu with trap(interrupt), 5 stage pipeline