diff --git a/src/drivers/artosyn/adc/adc.cpp b/src/drivers/artosyn/adc/adc.cpp
index 5ae96cebefc5fdb55c8baf6117e2b365b8faf20f..810a0da42236e19c47dd2fe04b91b2e5e8cef049 100644
--- a/src/drivers/artosyn/adc/adc.cpp
+++ b/src/drivers/artosyn/adc/adc.cpp
@@ -131,30 +131,24 @@ ADC::ADC(uint32_t channels) :
 	channels |= 1 << ADC_HW_VER_SENSE_CHANNEL;
 
 	/* allocate the sample array */
-	for (unsigned i = 0; i < 16; i++) 
-	{
-		if (channels & (1 << i)) 
-		{
+	for (unsigned i = 0; i < 16; i++) {
+		if (channels & (1 << i)) {
 			_channel_count++;
 		}
 	}
 
-	if (_channel_count > PX4_MAX_ADC_CHANNELS) 
-	{
+	if (_channel_count > PX4_MAX_ADC_CHANNELS) {
 		PX4_ERR("PX4_MAX_ADC_CHANNELS is too small:is %d needed:%d", PX4_MAX_ADC_CHANNELS, _channel_count);
 	}
 
 	_samples = new px4_adc_msg_t[_channel_count];
 
 	/* prefill the channel numbers in the sample array */
-	if (_samples != nullptr) 
-	{
+	if (_samples != nullptr) {
 		unsigned index = 0;
 
-		for (unsigned i = 0; i < 16; i++) 
-		{
-			if (channels & (1 << i)) 
-			{
+		for (unsigned i = 0; i < 16; i++) {
+			if (channels & (1 << i)) {
 				_samples[index].am_channel = i;
 				_samples[index].am_data = 0;
 				index++;
@@ -165,8 +159,7 @@ ADC::ADC(uint32_t channels) :
 
 ADC::~ADC()
 {
-	if (_samples != nullptr) 
-	{
+	if (_samples != nullptr) {
 		delete _samples;
 	}
 }
@@ -202,8 +195,7 @@ ADC::read(file *filp, char *buffer, size_t len)
 {
 	const size_t maxsize = sizeof(px4_adc_msg_t) * _channel_count;
 
-	if (len > maxsize) 
-	{
+	if (len > maxsize) {
 		len = maxsize;
 	}
 
@@ -246,8 +238,7 @@ ADC::_tick()
 	hrt_abstime now = hrt_absolute_time();
 
 	/* scan the channel set and sample each */
-	for (unsigned i = 0; i < _channel_count; i++) 
-    {
+	for (unsigned i = 0; i < _channel_count; i++) {
 		_samples[i].am_data = _sample(_samples[i].am_channel);
 	}
 
@@ -263,13 +254,11 @@ ADC::update_adc_report(hrt_abstime now)
 
 	unsigned max_num = _channel_count;
 
-	if (max_num > (sizeof(adc.channel_id) / sizeof(adc.channel_id[0]))) 
-    {
-	    max_num = (sizeof(adc.channel_id) / sizeof(adc.channel_id[0]));
+	if (max_num > (sizeof(adc.channel_id) / sizeof(adc.channel_id[0]))) {
+		max_num = (sizeof(adc.channel_id) / sizeof(adc.channel_id[0]));
 	}
 
-	for (unsigned i = 0; i < max_num; i++) 
-    {
+	for (unsigned i = 0; i < max_num; i++) {
 		adc.channel_id[i] = _samples[i].am_channel;
 		adc.channel_value[i] = _samples[i].am_data * 3.3f / 4096.0f;
 	}
@@ -281,13 +270,13 @@ ADC::update_adc_report(hrt_abstime now)
 void
 ADC::update_system_power(hrt_abstime now)
 {
-    ;   // liuwei : jump for now
+	;   // liuwei : jump for now
 }
 
 uint16_t board_adc_sample(unsigned channel)
 {
 
-    putreg32(channel << 2,ARGREG1_ADC_CHANNEL);
+	putreg32(channel << 2, ARGREG1_ADC_CHANNEL);
 
 	/* wait for the conversion to complete */
 	hrt_abstime now = hrt_absolute_time();
@@ -305,8 +294,7 @@ ADC::_sample(unsigned channel)
 	perf_begin(_sample_perf);
 	uint16_t result = board_adc_sample(channel);
 
-	if (result == 0xffff) 
-    {
+	if (result == 0xffff) {
 		DEVICE_LOG("sample timeout");
 	}
 
@@ -329,25 +317,21 @@ test(void)
 
 	int fd = open(ADC0_DEVICE_PATH, O_RDONLY);
 
-	if (fd < 0) 
-    {
+	if (fd < 0) {
 		err(1, "can't open ADC device");
 	}
 
-	for (unsigned i = 0; i < 50; i++) 
-    {
+	for (unsigned i = 0; i < 50; i++) {
 		px4_adc_msg_t data[PX4_MAX_ADC_CHANNELS];
 		ssize_t count = read(fd, data, sizeof(data));
 
-		if (count < 0) 
-        {
+		if (count < 0) {
 			errx(1, "read error");
 		}
 
 		unsigned channels = count / sizeof(data[0]);
 
-		for (unsigned j = 0; j < channels; j++) 
-        {
+		for (unsigned j = 0; j < channels; j++) {
 			printf("%d: %u  ", data[j].am_channel, data[j].am_data);
 		}
 
@@ -362,27 +346,22 @@ test(void)
 int
 adc_main(int argc, char *argv[])
 {
-	if (g_adc == nullptr) 
-    {
+	if (g_adc == nullptr) {
 		/* XXX this hardcodes the default channel set for the board in board_config.h - should be configurable */
 		g_adc = new ADC(ADC_CHANNELS);
 
-		if (g_adc == nullptr) 
-        {
+		if (g_adc == nullptr) {
 			errx(1, "couldn't allocate the ADC driver");
 		}
 
-		if (g_adc->init() != OK) 
-        {
+		if (g_adc->init() != OK) {
 			delete g_adc;
 			errx(1, "ADC init failed");
 		}
 	}
 
-	if (argc > 1) 
-    {
-		if (!strcmp(argv[1], "test")) 
-        {
+	if (argc > 1) {
+		if (!strcmp(argv[1], "test")) {
 			test();
 		}
 	}
diff --git a/src/drivers/artosyn/drv_hrt.c b/src/drivers/artosyn/drv_hrt.c
index 03a521b78d0ed777a2ca0d075949aee0ecef11a5..2c5f7f2aebe51e8a7077985290bd7ec59fda7bae 100644
--- a/src/drivers/artosyn/drv_hrt.c
+++ b/src/drivers/artosyn/drv_hrt.c
@@ -91,136 +91,136 @@
 
 /* freerun timer */
 #if HRT_TIMER_FREERUN == 0
-	# define HRT_TIMER_FREERUN_BASE         AR_TIM0_BASE
+# define HRT_TIMER_FREERUN_BASE         AR_TIM0_BASE
 #elif HRT_TIMER_FREERUN == 1
-	# define HRT_TIMER_FREERUN_BASE         AR_TIM1_BASE
+# define HRT_TIMER_FREERUN_BASE         AR_TIM1_BASE
 #elif   HRT_TIMER_FREERUN == 2
-	# define HRT_TIMER_FREERUN_BASE         AR_TIM2_BASE
+# define HRT_TIMER_FREERUN_BASE         AR_TIM2_BASE
 #endif
 
 /* freerun timer channel */
 #if HRT_TIMER_FREERUN == 0
-	#if HRT_TIMER_FREERUN_CHANNEL == 0
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM0_CH0
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 1
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM0_CH1
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 2
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM0_CH2
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 3
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM0_CH3
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 4
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM0_CH4
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 5
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM0_CH5
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 6
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM0_CH6
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 7
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM0_CH7
-	#endif
+#if HRT_TIMER_FREERUN_CHANNEL == 0
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM0_CH0
+#elif   HRT_TIMER_FREERUN_CHANNEL == 1
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM0_CH1
+#elif   HRT_TIMER_FREERUN_CHANNEL == 2
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM0_CH2
+#elif   HRT_TIMER_FREERUN_CHANNEL == 3
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM0_CH3
+#elif   HRT_TIMER_FREERUN_CHANNEL == 4
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM0_CH4
+#elif   HRT_TIMER_FREERUN_CHANNEL == 5
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM0_CH5
+#elif   HRT_TIMER_FREERUN_CHANNEL == 6
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM0_CH6
+#elif   HRT_TIMER_FREERUN_CHANNEL == 7
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM0_CH7
+#endif
 #elif HRT_TIMER_FREERUN == 1
-	#if HRT_TIMER_FREERUN_CHANNEL == 0
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM1_CH0
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 1					 
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM1_CH1
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 2					
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM1_CH2
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 3					
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM1_CH3
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 4					
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM1_CH4
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 5					
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM1_CH5
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 6					
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM1_CH6
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 7					
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM1_CH7
-	#endif
+#if HRT_TIMER_FREERUN_CHANNEL == 0
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM1_CH0
+#elif   HRT_TIMER_FREERUN_CHANNEL == 1
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM1_CH1
+#elif   HRT_TIMER_FREERUN_CHANNEL == 2
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM1_CH2
+#elif   HRT_TIMER_FREERUN_CHANNEL == 3
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM1_CH3
+#elif   HRT_TIMER_FREERUN_CHANNEL == 4
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM1_CH4
+#elif   HRT_TIMER_FREERUN_CHANNEL == 5
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM1_CH5
+#elif   HRT_TIMER_FREERUN_CHANNEL == 6
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM1_CH6
+#elif   HRT_TIMER_FREERUN_CHANNEL == 7
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM1_CH7
+#endif
 #elif   HRT_TIMER_FREERUN == 2
-	#if HRT_TIMER_FREERUN_CHANNEL == 0
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM2_CH0
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 1                      	
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM2_CH1
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 2                      
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM2_CH2
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 3                      
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM2_CH3
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 4                      
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM2_CH4
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 5                      
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM2_CH5
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 6                      
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM2_CH6
-	#elif   HRT_TIMER_FREERUN_CHANNEL == 7                      
-	# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM2_CH7
-	#endif
+#if HRT_TIMER_FREERUN_CHANNEL == 0
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM2_CH0
+#elif   HRT_TIMER_FREERUN_CHANNEL == 1
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM2_CH1
+#elif   HRT_TIMER_FREERUN_CHANNEL == 2
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM2_CH2
+#elif   HRT_TIMER_FREERUN_CHANNEL == 3
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM2_CH3
+#elif   HRT_TIMER_FREERUN_CHANNEL == 4
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM2_CH4
+#elif   HRT_TIMER_FREERUN_CHANNEL == 5
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM2_CH5
+#elif   HRT_TIMER_FREERUN_CHANNEL == 6
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM2_CH6
+#elif   HRT_TIMER_FREERUN_CHANNEL == 7
+# 	define HRT_TIMER_FREERUN_VECTOR       AR_IRQ_TIM2_CH7
+#endif
 #endif
 
 
 /* compare timer */
 #if HRT_TIMER_CCR == 0
-	# define HRT_TIMER_CCR_BASE         AR_TIM0_BASE
+# define HRT_TIMER_CCR_BASE         AR_TIM0_BASE
 #elif HRT_TIMER_CCR == 1
-	# define HRT_TIMER_CCR_BASE         AR_TIM1_BASE
+# define HRT_TIMER_CCR_BASE         AR_TIM1_BASE
 #elif   HRT_TIMER_CCR == 2
-	# define HRT_TIMER_CCR_BASE         AR_TIM2_BASE
+# define HRT_TIMER_CCR_BASE         AR_TIM2_BASE
 #endif
 
 
 /* compare timer channel */
 #if HRT_TIMER_CCR == 0
-	#if HRT_TIMER_CCR_CHANNEL == 0
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM0_CH0
-	#elif   HRT_TIMER_CCR_CHANNEL == 1
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM0_CH1
-	#elif   HRT_TIMER_CCR_CHANNEL == 2
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM0_CH2
-	#elif   HRT_TIMER_CCR_CHANNEL == 3
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM0_CH3
-	#elif   HRT_TIMER_CCR_CHANNEL == 4
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM0_CH4
-	#elif   HRT_TIMER_CCR_CHANNEL == 5
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM0_CH5
-	#elif   HRT_TIMER_CCR_CHANNEL == 6
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM0_CH6
-	#elif   HRT_TIMER_CCR_CHANNEL == 7
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM0_CH7
-	#endif
+#if HRT_TIMER_CCR_CHANNEL == 0
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM0_CH0
+#elif   HRT_TIMER_CCR_CHANNEL == 1
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM0_CH1
+#elif   HRT_TIMER_CCR_CHANNEL == 2
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM0_CH2
+#elif   HRT_TIMER_CCR_CHANNEL == 3
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM0_CH3
+#elif   HRT_TIMER_CCR_CHANNEL == 4
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM0_CH4
+#elif   HRT_TIMER_CCR_CHANNEL == 5
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM0_CH5
+#elif   HRT_TIMER_CCR_CHANNEL == 6
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM0_CH6
+#elif   HRT_TIMER_CCR_CHANNEL == 7
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM0_CH7
+#endif
 #elif HRT_TIMER_CCR == 1
-	#if HRT_TIMER_CCR_CHANNEL == 0
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM1_CH0
-	#elif   HRT_TIMER_CCR_CHANNEL == 1					 
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM1_CH1
-	#elif   HRT_TIMER_CCR_CHANNEL == 2					
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM1_CH2
-	#elif   HRT_TIMER_CCR_CHANNEL == 3					
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM1_CH3
-	#elif   HRT_TIMER_CCR_CHANNEL == 4					
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM1_CH4
-	#elif   HRT_TIMER_CCR_CHANNEL == 5					
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM1_CH5
-	#elif   HRT_TIMER_CCR_CHANNEL == 6					
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM1_CH6
-	#elif   HRT_TIMER_CCR_CHANNEL == 7					
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM1_CH7
-	#endif
+#if HRT_TIMER_CCR_CHANNEL == 0
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM1_CH0
+#elif   HRT_TIMER_CCR_CHANNEL == 1
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM1_CH1
+#elif   HRT_TIMER_CCR_CHANNEL == 2
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM1_CH2
+#elif   HRT_TIMER_CCR_CHANNEL == 3
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM1_CH3
+#elif   HRT_TIMER_CCR_CHANNEL == 4
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM1_CH4
+#elif   HRT_TIMER_CCR_CHANNEL == 5
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM1_CH5
+#elif   HRT_TIMER_CCR_CHANNEL == 6
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM1_CH6
+#elif   HRT_TIMER_CCR_CHANNEL == 7
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM1_CH7
+#endif
 #elif   HRT_TIMER_CCR == 2
-	#if HRT_TIMER_CCR_CHANNEL == 0
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM2_CH0
-	#elif   HRT_TIMER_CCR_CHANNEL == 1                      	
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM2_CH1
-	#elif   HRT_TIMER_CCR_CHANNEL == 2                      
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM2_CH2
-	#elif   HRT_TIMER_CCR_CHANNEL == 3                      
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM2_CH3
-	#elif   HRT_TIMER_CCR_CHANNEL == 4                      
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM2_CH4
-	#elif   HRT_TIMER_CCR_CHANNEL == 5                      
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM2_CH5
-	#elif   HRT_TIMER_CCR_CHANNEL == 6                      
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM2_CH6
-	#elif   HRT_TIMER_CCR_CHANNEL == 7                      
-	# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM2_CH7
-	#endif
+#if HRT_TIMER_CCR_CHANNEL == 0
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM2_CH0
+#elif   HRT_TIMER_CCR_CHANNEL == 1
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM2_CH1
+#elif   HRT_TIMER_CCR_CHANNEL == 2
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM2_CH2
+#elif   HRT_TIMER_CCR_CHANNEL == 3
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM2_CH3
+#elif   HRT_TIMER_CCR_CHANNEL == 4
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM2_CH4
+#elif   HRT_TIMER_CCR_CHANNEL == 5
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM2_CH5
+#elif   HRT_TIMER_CCR_CHANNEL == 6
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM2_CH6
+#elif   HRT_TIMER_CCR_CHANNEL == 7
+# 	define HRT_TIMER_CCR_VECTOR       AR_IRQ_TIM2_CH7
+#endif
 #endif
 
 
@@ -257,7 +257,7 @@
  */
 
 #define REG_FR(_reg)       	(HRT_TIMER_FREERUN_BASE + _reg)
- 
+
 
 #if HRT_TIMER_FREERUN_CHANNEL == 0
 #   define rTIMERLOADCOUNT_HRT_FR                REG_FR(AR_TIM_TIMER0LOADCOUNT_OFFSET   )
@@ -404,10 +404,10 @@ static void		hrt_latency_update(void);
 
 /* callout list manipulation */
 static void		hrt_call_internal(struct hrt_call *entry,
-		                            hrt_abstime deadline,
-		                            hrt_abstime interval,
-		                            hrt_callout callout,
-		                            void *arg);
+		hrt_abstime deadline,
+		hrt_abstime interval,
+		hrt_callout callout,
+		void *arg);
 
 static void		hrt_call_enter(struct hrt_call *entry);
 static void		hrt_call_reschedule(void);
@@ -426,41 +426,41 @@ hrt_tim_init(void)
 
 	/* claim our interrupt vector */
 	irq_attach(HRT_TIMER_CCR_VECTOR, hrt_tim_ccr_isr, NULL);
-	
-	/* clock/power on our timer */ 
+
+	/* clock/power on our timer */
 	// ar8020 clock is power by default
 
 	/*freerun timer*/
-	putreg32(AR_TIMERCONTROLREG_ENABLE_DISABLE,rTIMERCONTROLREG_HRT_FR);
+	putreg32(AR_TIMERCONTROLREG_ENABLE_DISABLE, rTIMERCONTROLREG_HRT_FR);
 
-    /* clear cnt */
-	putreg32(0xFFFFFFFF,rTIMERLOADCOUNT_HRT_FR);
+	/* clear cnt */
+	putreg32(0xFFFFFFFF, rTIMERLOADCOUNT_HRT_FR);
 
-    /* clear cnt2 */
-	putreg32(0,rTIMERLOADCOUNT2_HRT_FR);
+	/* clear cnt2 */
+	putreg32(0, rTIMERLOADCOUNT2_HRT_FR);
 
-    getreg32(rTIMEREOI_HRT_FR);	/* clear inturput */
+	getreg32(rTIMEREOI_HRT_FR);	/* clear inturput */
 
 	putreg32(AR_TIMERCONTROLREG_PWM_DISABLE	|   \
-							AR_TIMERCONTROLREG_INTMASK_MASKED 	|   \
-							AR_TIMERCONTROLREG_MODE_FREERUN 	|   \
-							AR_TIMERCONTROLREG_ENABLE_ENABLE,rTIMERCONTROLREG_HRT_FR);
+		 AR_TIMERCONTROLREG_INTMASK_MASKED 	|   \
+		 AR_TIMERCONTROLREG_MODE_FREERUN 	|   \
+		 AR_TIMERCONTROLREG_ENABLE_ENABLE, rTIMERCONTROLREG_HRT_FR);
 
 
 	/*ccr timer*/
-	putreg32(AR_TIMERCONTROLREG_ENABLE_DISABLE,rTIMERCONTROLREG_HRT_CCR);
-	
-    /* clear cnt */
-	putreg32(128000-1,rTIMERLOADCOUNT_HRT_CCR);
-	
-	putreg32(0,rTIMERLOADCOUNT2_HRT_CCR);
+	putreg32(AR_TIMERCONTROLREG_ENABLE_DISABLE, rTIMERCONTROLREG_HRT_CCR);
+
+	/* clear cnt */
+	putreg32(128000 - 1, rTIMERLOADCOUNT_HRT_CCR);
 
-    getreg32(rTIMEREOI_HRT_CCR);	/* clear inturput */
+	putreg32(0, rTIMERLOADCOUNT2_HRT_CCR);
+
+	getreg32(rTIMEREOI_HRT_CCR);	/* clear inturput */
 
 	putreg32(AR_TIMERCONTROLREG_PWM_DISABLE	|   \
-							AR_TIMERCONTROLREG_INTMASK_NOMASKED 	|   \
-							AR_TIMERCONTROLREG_MODE_USERDEFINED 		|   \
-							AR_TIMERCONTROLREG_ENABLE_ENABLE,rTIMERCONTROLREG_HRT_CCR);
+		 AR_TIMERCONTROLREG_INTMASK_NOMASKED 	|   \
+		 AR_TIMERCONTROLREG_MODE_USERDEFINED 		|   \
+		 AR_TIMERCONTROLREG_ENABLE_ENABLE, rTIMERCONTROLREG_HRT_CCR);
 
 	/* enable interrupts */
 	up_enable_irq(HRT_TIMER_CCR_VECTOR);
@@ -470,27 +470,26 @@ static bool flash =  true;
 
 static uint16_t flashCnt = 0;
 
-	//static uint8_t cnt = 0;
+//static uint8_t cnt = 0;
 /**
  * Handle the compare interrupt by calling the callout dispatcher
  * and then re-scheduling the next deadline.
  */
-static int 
+static int
 hrt_tim_ccr_isr(int irq, void *context, void *arg)
 {
-	if (flashCnt ++ == 4500)
-	{
+	if (flashCnt ++ == 4500) {
 		flash = !flash;
-		ar_gpiowrite(GPIO_OUTPUT|GPIO_OUTSET|GPIO_PIN14, flash); 
+		ar_gpiowrite(GPIO_OUTPUT | GPIO_OUTSET | GPIO_PIN14, flash);
 
 		flashCnt = 0;
 	}
-	
+
 	/* grab the timer for latency tracking purposes */
 	// because the ar8020 is only -1 cnt mode
-		
+
 	latency_actual = 0xFFFFFFFF - getreg32(rTIMERCURRENTVALUE_HRT_FR);
-	
+
 	/* ack the interrupts we just read */
 	getreg32(rTIMEREOI_HRT_CCR);
 
@@ -502,7 +501,7 @@ hrt_tim_ccr_isr(int irq, void *context, void *arg)
 
 	/* and schedule the next interrupt */
 	hrt_call_reschedule();
-	
+
 	return OK;
 }
 
@@ -510,7 +509,7 @@ hrt_tim_ccr_isr(int irq, void *context, void *arg)
  * Fetch a never-wrapping absolute time value in microseconds from
  * some arbitrary epoch shortly after system start.
  */
-hrt_abstime 
+hrt_abstime
 hrt_absolute_time(void)
 {
 	hrt_abstime	abstime;
@@ -530,9 +529,9 @@ hrt_absolute_time(void)
 	flags = px4_enter_critical_section();
 
 	/* get the current counter value */
-	/* because the ar8020 is -1 cnt mode */ 
+	/* because the ar8020 is -1 cnt mode */
 	count = (0xFFFFFFFF - getreg32(rTIMERCURRENTVALUE_HRT_FR));
-	
+
 	/*
 	 * Determine whether the counter has wrapped since the
 	 * last time we're called.
@@ -540,9 +539,8 @@ hrt_absolute_time(void)
 	 * This simple test is sufficient due to the guarantee that
 	 * we are always called at least once per counter period.
 	 */
-	
-	if (count < last_count) 
-	{
+
+	if (count < last_count) {
 		base_time += 0xFFFFFFFF;
 	}
 
@@ -723,22 +721,17 @@ hrt_call_enter(struct hrt_call *entry)
 
 	call = (struct hrt_call *)sq_peek(&callout_queue);
 
-	if ((call == NULL) || (entry->deadline < call->deadline))
-    {
+	if ((call == NULL) || (entry->deadline < call->deadline)) {
 		sq_addfirst(&entry->link, &callout_queue);
 		hrtinfo("call enter at head, reschedule\n");
 		/* we changed the next deadline, reschedule the timer event */
 		hrt_call_reschedule();
 
-	} 
-    else 
-    {
-		do 
-        {
+	} else {
+		do {
 			next = (struct hrt_call *)sq_next(&call->link);
 
-			if ((next == NULL) || (entry->deadline < next->deadline)) 
-            {
+			if ((next == NULL) || (entry->deadline < next->deadline)) {
 				hrtinfo("call enter after head\n");
 				sq_addafter(&call->link, &entry->link, &callout_queue);
 				break;
@@ -755,20 +748,17 @@ hrt_call_invoke(void)
 	struct hrt_call	*call;
 	hrt_abstime deadline;
 
-	while (true) 
-    {
+	while (true) {
 		/* get the current time */
 		hrt_abstime now = hrt_absolute_time();
 
 		call = (struct hrt_call *)sq_peek(&callout_queue);
 
-		if (call == NULL) 
-        {
+		if (call == NULL) {
 			break;
 		}
 
-		if (call->deadline > now) 
-        {
+		if (call->deadline > now) {
 			break;
 		}
 
@@ -782,20 +772,17 @@ hrt_call_invoke(void)
 		call->deadline = 0;
 
 		/* invoke the callout (if there is one) */
-		if (call->callout) 
-        {
+		if (call->callout) {
 			hrtinfo("call %p: %p(%p)\n", call, call->callout, call->arg);
 			call->callout(call->arg);
 		}
 
 		/* if the callout has a non-zero period, it has to be re-entered */
-		if (call->period != 0) 
-        {
+		if (call->period != 0) {
 			// re-check call->deadline to allow for
 			// callouts to re-schedule themselves
 			// using hrt_call_delay()
-			if (call->deadline <= now) 
-            {
+			if (call->deadline <= now) {
 				call->deadline = deadline + call->period;
 			}
 
@@ -829,18 +816,15 @@ hrt_call_reschedule()
 		* interrupt fires sufficiently often that the base_time update in
 		* hrt_absolute_time runs at least once per timer period.
 		*/
-	if (next != NULL) 
-	{
+	if (next != NULL) {
 		hrtinfo("entry in queue\n");
 
-		if (next->deadline <= (now + HRT_INTERVAL_MIN)) 
-		{
+		if (next->deadline <= (now + HRT_INTERVAL_MIN)) {
 			hrtinfo("pre-expired\n");
 			/* set a minimal deadline so that we call ASAP */
 			deadline = now + HRT_INTERVAL_MIN;
-		} 
-		else if (next->deadline < deadline) 
-		{
+
+		} else if (next->deadline < deadline) {
 			hrtinfo("due soon\n");
 			deadline = next->deadline;
 		}
@@ -849,34 +833,32 @@ hrt_call_reschedule()
 	//hrtinfo("schedule for %u at %u\n", (unsigned)(deadline & 0xffffffff), (unsigned)(now & 0xffffffff));
 
 	/* set the new compare value and remember it for latency tracking */
-	
 
-	uint32_t temp = deadline -now;
-	
 
-	latency_baseline = now_fr_cnt + temp *128;
+	uint32_t temp = deadline - now;
+
+
+	latency_baseline = now_fr_cnt + temp * 128;
 
 	// latency_baseline -= deadline * 128;
-	putreg32(AR_TIMERCONTROLREG_ENABLE_DISABLE,rTIMERCONTROLREG_HRT_CCR);
-	putreg32(temp *128, rTIMERLOADCOUNT_HRT_CCR);
+	putreg32(AR_TIMERCONTROLREG_ENABLE_DISABLE, rTIMERCONTROLREG_HRT_CCR);
+	putreg32(temp * 128, rTIMERLOADCOUNT_HRT_CCR);
 
 	putreg32(AR_TIMERCONTROLREG_PWM_DISABLE	|   \
-							AR_TIMERCONTROLREG_INTMASK_NOMASKED 	|   \
-							AR_TIMERCONTROLREG_MODE_USERDEFINED 		|   \
-							AR_TIMERCONTROLREG_ENABLE_ENABLE,rTIMERCONTROLREG_HRT_CCR);
+		 AR_TIMERCONTROLREG_INTMASK_NOMASKED 	|   \
+		 AR_TIMERCONTROLREG_MODE_USERDEFINED 		|   \
+		 AR_TIMERCONTROLREG_ENABLE_ENABLE, rTIMERCONTROLREG_HRT_CCR);
 }
 
 static void
 hrt_latency_update(void)
 {
-	uint32_t latency = (latency_actual - latency_baseline)/128;
+	uint32_t latency = (latency_actual - latency_baseline) / 128;
 	unsigned	index;
-	
+
 	/* bounded buckets */
-	for (index = 0; index < LATENCY_BUCKET_COUNT; index++)
-     {
-		if (latency <= latency_buckets[index]) 
-        {
+	for (index = 0; index < LATENCY_BUCKET_COUNT; index++) {
+		if (latency <= latency_buckets[index]) {
 			latency_counters[index]++;
 			return;
 		}
diff --git a/src/drivers/artosyn/drv_io_timer.c b/src/drivers/artosyn/drv_io_timer.c
index eb1468f3568feb0690d4f9884322de210a6b958d..201184928ba3107e4353001c6293f47519e30194 100644
--- a/src/drivers/artosyn/drv_io_timer.c
+++ b/src/drivers/artosyn/drv_io_timer.c
@@ -97,8 +97,7 @@
 // #define TIMER_EOI(channel) (CHANNER_IN_TIMER_OFFSET(channel))*0x014 + 0x0C + TIMER_BASE(channel)
 // #define TIMER_INT_STATUS(channel) (CHANNER_IN_TIMER_OFFSET(channel))*0x014 + 0x10 + TIMER_BASE(channel)
 
-typedef enum io_timer_reg_t
-{
+typedef enum io_timer_reg_t {
 	rTIM_LOADCOUNT,
 	rTIM_LOADCOUNT2,
 	rTIM_CURRENTVALUE,
@@ -111,26 +110,31 @@ static void set_timer_reg(unsigned timer, io_timer_reg_t reg, uint32_t value)
 {
 	uint32_t reg_addr = 0;
 
-	switch (reg)
-	{
+	switch (reg) {
 	case rTIM_LOADCOUNT:
 		reg_addr = io_timers[timer].rTIM_LOADCOUNT;
 		break;
+
 	case rTIM_LOADCOUNT2:
 		reg_addr = io_timers[timer].rTIM_LOADCOUNT2;
 		break;
+
 	case rTIM_CURRENTVALUE:
 		reg_addr = io_timers[timer].rTIM_CURRENTVALUE;
 		break;
+
 	case rTIM_CONTROLREG:
 		reg_addr = io_timers[timer].rTIM_CONTROLREG;
 		break;
+
 	case rTIM_EOI:
 		reg_addr = io_timers[timer].rTIM_EOI;
 		break;
+
 	case rTIM_INTSTATUS:
 		reg_addr = io_timers[timer].rTIM_INTSTATUS;
 		break;
+
 	default:
 		break; //error
 	}
@@ -139,32 +143,38 @@ static void set_timer_reg(unsigned timer, io_timer_reg_t reg, uint32_t value)
 }
 
 static uint32_t get_timer_reg(unsigned timer, io_timer_reg_t reg)
-{	
+{
 	uint32_t reg_addr = 0;
 
-	switch (reg)
-	{
+	switch (reg) {
 	case rTIM_LOADCOUNT:
 		reg_addr = io_timers[timer].rTIM_LOADCOUNT;
 		break;
+
 	case rTIM_LOADCOUNT2:
 		reg_addr = io_timers[timer].rTIM_LOADCOUNT2;
 		break;
+
 	case rTIM_CURRENTVALUE:
 		reg_addr = io_timers[timer].rTIM_CURRENTVALUE;
 		break;
+
 	case rTIM_CONTROLREG:
 		reg_addr = io_timers[timer].rTIM_CONTROLREG;
 		break;
+
 	case rTIM_EOI:
 		reg_addr = io_timers[timer].rTIM_EOI;
 		break;
+
 	case rTIM_INTSTATUS:
 		reg_addr = io_timers[timer].rTIM_INTSTATUS;
 		break;
+
 	default:
 		break; //error
 	}
+
 	return getreg32(reg_addr);
 }
 
@@ -203,8 +213,7 @@ static inline int is_timer_uninitalized(unsigned timer)
 {
 	int rv = 0;
 
-	if (once & 1 << timer)
-	{
+	if (once & 1 << timer) {
 		rv = -EBUSY;
 	}
 
@@ -231,14 +240,11 @@ static uint32_t get_timer_channels(unsigned timer)
 	uint32_t channels = 0;
 	static uint32_t channels_cache[MAX_IO_TIMERS] = {0};
 
-	if (validate_timer_index(timer) < 0)
-	{
+	if (validate_timer_index(timer) < 0) {
 		return channels;
-	}
-	else
-	{
-		if (channels_cache[timer] == 0)
-		{
+
+	} else {
+		if (channels_cache[timer] == 0) {
 			const io_timers_t *tmr = &io_timers[timer];
 
 			channels_cache[timer] = 1 << (tmr->channel_index);
@@ -257,12 +263,10 @@ int io_timer_is_channel_free(unsigned channel)
 {
 	int rv = io_timer_validate_channel_index(channel);
 
-	if (rv == 0)
-	{
+	if (rv == 0) {
 		io_timers_t *io_timer = (io_timers_t *)(&io_timers[channel]);
 
-		if (io_timer->channel_mode != IOTimerChanMode_NotUsed)
-		{
+		if (io_timer->channel_mode != IOTimerChanMode_NotUsed) {
 			rv = -EBUSY;
 		}
 	}
@@ -281,11 +285,10 @@ int io_timer_get_mode_channels(io_timer_channel_mode_t mode)
 
 	io_timers_t *io_timer;
 
-	for (uint8_t i = 0; i < MAX_IO_TIMERS; i++)
-	{
+	for (uint8_t i = 0; i < MAX_IO_TIMERS; i++) {
 		io_timer = (io_timers_t *)(&io_timers[i]);
-		if (io_timer->channel_mode == mode)
-		{
+
+		if (io_timer->channel_mode == mode) {
 			channels |= (1 << io_timer->channel_index);
 		}
 	}
@@ -295,8 +298,7 @@ int io_timer_get_mode_channels(io_timer_channel_mode_t mode)
 
 int io_timer_get_channel_mode(unsigned channel)
 {
-	if (channel >= MAX_IO_TIMERS)
-	{
+	if (channel >= MAX_IO_TIMERS) {
 		return -1;
 	}
 
@@ -309,15 +311,13 @@ int io_timer_free_channel(unsigned channel)
 {
 	int ret = io_timer_validate_channel_index(channel);
 
-	if (ret != 0)
-	{
+	if (ret != 0) {
 		return ret;
 	}
 
 	int mode = io_timer_get_channel_mode(channel);
 
-	if (mode > IOTimerChanMode_NotUsed)
-	{
+	if (mode > IOTimerChanMode_NotUsed) {
 		io_timer_set_enable(false, IOTimerChanMode_NotUsed, 1 << channel);
 	}
 
@@ -372,8 +372,7 @@ void io_timer_trigger(void)
 {
 	int oneshots = io_timer_get_mode_channels(IOTimerChanMode_OneShot);
 
-	if (oneshots != 0)
-	{
+	if (oneshots != 0) {
 		// uint32_t action_cache[MAX_IO_TIMERS] = {0};
 		// int actions = 0;
 
@@ -408,8 +407,7 @@ int io_timer_init_timer(unsigned timer)
 	/* Do this only once per timer */
 	int rv = is_timer_uninitalized(timer);
 
-	if (rv == 0)
-	{
+	if (rv == 0) {
 		irqstate_t flags = px4_enter_critical_section();
 
 		set_timer_initalized(timer);
@@ -426,7 +424,8 @@ int io_timer_init_timer(unsigned timer)
 
 		get_timer_reg(timer, rTIM_EOI);
 
-		set_timer_reg(timer, rTIM_CONTROLREG, AR_TIMERCONTROLREG_PWM_ENABLE | AR_TIMERCONTROLREG_INTMASK_MASKED | AR_TIMERCONTROLREG_MODE_USERDEFINED);
+		set_timer_reg(timer, rTIM_CONTROLREG,
+			      AR_TIMERCONTROLREG_PWM_ENABLE | AR_TIMERCONTROLREG_INTMASK_MASKED | AR_TIMERCONTROLREG_MODE_USERDEFINED);
 
 		/*
 		 * Note we do the Standard PWM Out init here
@@ -452,20 +451,17 @@ int io_timer_set_rate(unsigned timer, unsigned rate)
 {
 	int ret = io_timer_validate_channel_index(timer);
 
-	if (ret != 0)
-	{
+	if (ret != 0) {
 		return ret;
 	}
 
 	io_timers_t *io_timer = (io_timers_t *)(&io_timers[timer]);
 
-	if (rate == 0)
-	{
+	if (rate == 0) {
 		io_timer->channel_mode = IOTimerChanMode_OneShot;
 		io_timer_set_oneshot_mode(timer);
-	}
-	else
-	{
+
+	} else {
 		timer_set_rate(timer, rate);
 	}
 
@@ -473,7 +469,7 @@ int io_timer_set_rate(unsigned timer, unsigned rate)
 }
 
 int io_timer_channel_init(unsigned channel, io_timer_channel_mode_t mode,
-						  channel_handler_t channel_handler, void *context)
+			  channel_handler_t channel_handler, void *context)
 {
 
 	io_timers_t *io_timer = (io_timers_t *)(&io_timers[channel]);
@@ -484,8 +480,7 @@ int io_timer_channel_init(unsigned channel, io_timer_channel_mode_t mode,
 	uint32_t gpio = io_timer->gpio_out;
 	uint32_t tmp;
 
-	switch (mode)
-	{
+	switch (mode) {
 	case IOTimerChanMode_OneShot:
 	case IOTimerChanMode_PWMOut:
 	case IOTimerChanMode_Trigger:
@@ -510,8 +505,7 @@ int io_timer_channel_init(unsigned channel, io_timer_channel_mode_t mode,
 	irqstate_t flags = px4_enter_critical_section();
 
 	/* Set up IO */
-	if (gpio)
-	{
+	if (gpio) {
 		px4_arch_configgpio(gpio);
 	}
 
@@ -527,12 +521,10 @@ int io_timer_set_enable(bool state, io_timer_channel_mode_t mode, io_timer_chann
 
 	irqstate_t flags = px4_enter_critical_section();
 
-	for (uint8_t chan_index = 0; masks != 0 && chan_index < MAX_TIMER_IO_CHANNELS; chan_index++)
-	{
+	for (uint8_t chan_index = 0; masks != 0 && chan_index < MAX_TIMER_IO_CHANNELS; chan_index++) {
 		io_timer = (io_timers_t *)(&io_timers[chan_index]);
 
-		if (masks & (1 << chan_index))
-		{
+		if (masks & (1 << chan_index)) {
 			masks &= ~(1 << chan_index);
 
 			uint32_t tmp_data = get_timer_reg(chan_index, rTIM_CONTROLREG);
@@ -554,34 +546,30 @@ int io_timer_set_ccr(unsigned channel, uint16_t value)
 	int rv = io_timer_validate_channel_index(channel);
 	int mode = io_timer_get_channel_mode(channel);
 
-	if (rv == 0)
-	{
+	if (rv == 0) {
 		if ((mode != IOTimerChanMode_PWMOut) &&
-			(mode != IOTimerChanMode_OneShot) &&
-			(mode != IOTimerChanMode_Trigger))
-		{
+		    (mode != IOTimerChanMode_OneShot) &&
+		    (mode != IOTimerChanMode_Trigger)) {
 
 			rv = -EIO;
-		}
-		else
-		{
+
+		} else {
 
 			uint32_t cnt2 = get_timer_reg(channels_timer(channel), rTIM_LOADCOUNT2);
- 
+
 			uint32_t cnt_value = value * 128;
 
-			if(cnt2 != cnt_value)
-			{
+			if (cnt2 != cnt_value) {
 
 				//PX4_INFO("cnt2 = %d ; cnt_value = %d ", cnt2,cnt_value);
 				uint32_t cnt1 = get_timer_reg(channels_timer(channel), rTIM_LOADCOUNT);
-				
+
 				/* configure the channel */
 				uint32_t cnt_sum =  cnt1 + cnt2 ;
 
 				set_timer_reg(channels_timer(channel), rTIM_LOADCOUNT2, cnt_value);
 				set_timer_reg(channels_timer(channel), rTIM_LOADCOUNT, cnt_sum - cnt_value);
-			
+
 			}
 		}
 	}
@@ -593,14 +581,12 @@ uint16_t io_channel_get_ccr(unsigned channel)
 {
 	uint16_t value = 0;
 
-	if (io_timer_validate_channel_index(channel) == 0)
-	{
+	if (io_timer_validate_channel_index(channel) == 0) {
 		int mode = io_timer_get_channel_mode(channel);
 
 		if ((mode == IOTimerChanMode_PWMOut) ||
-			(mode == IOTimerChanMode_OneShot) ||
-			(mode == IOTimerChanMode_Trigger))
-		{
+		    (mode == IOTimerChanMode_OneShot) ||
+		    (mode == IOTimerChanMode_Trigger)) {
 			value = get_timer_reg(channels_timer(channel), rTIM_LOADCOUNT2) / 128;
 		}
 	}
diff --git a/src/drivers/artosyn/drv_io_timer.h b/src/drivers/artosyn/drv_io_timer.h
index 98eef40c99922a3299b8b4fcfc10e99ef63bbeb6..dfaa5bdf5fec203a3ba1d7ec94a8ff71656f4b31 100644
--- a/src/drivers/artosyn/drv_io_timer.h
+++ b/src/drivers/artosyn/drv_io_timer.h
@@ -74,16 +74,16 @@ typedef uint16_t io_timer_channel_allocation_t; /* big enough to hold MAX_TIMER_
  *** the resulting PSC will be one and the timer will count at it's clock frequency.
  */
 
-				  
+
 // Timer == Channel == group
 typedef struct io_timers_t {
 	uint32_t	base;			// base address in chip
-	uint32_t	clock_freq;	
+	uint32_t	clock_freq;
 	uint32_t	vectorno;
 	xcpt_t      handler;
 	uint32_t	gpio_out;
 	uint32_t	gpio_in;
-	uint8_t 	channel_index; // index of channel, same to tinmer 
+	uint8_t 	channel_index; // index of channel, same to tinmer
 	io_timer_channel_mode_t channel_mode;
 	// channel_handler_t callback;
 	void			  *context;
diff --git a/src/drivers/artosyn/drv_led_pwm.cpp b/src/drivers/artosyn/drv_led_pwm.cpp
index 479591df4522b385c48f876a3a3d8a092ec86fba..3859333c0c8dd3c916f43c7d671f1e9f709f9dff 100644
--- a/src/drivers/artosyn/drv_led_pwm.cpp
+++ b/src/drivers/artosyn/drv_led_pwm.cpp
@@ -117,50 +117,50 @@ led_pwm_timer_get_period(unsigned timer)
 
 // static void led_pwm_timer_init_timer(unsigned timer)
 // {
-	
-	// irqstate_t flags = px4_enter_critical_section();
 
-	// /* enable the timer clock before we try to talk to it */
+// irqstate_t flags = px4_enter_critical_section();
 
-	// modifyreg32(led_pwm_timers[timer].clock_register, 0, led_pwm_timers[timer].clock_bit);
+// /* enable the timer clock before we try to talk to it */
 
-	// /* disable and configure the timer */
-	// rCR1(timer) = 0;
-	// rCR2(timer) = 0;
-	// rSMCR(timer) = 0;
-	// rDIER(timer) = 0;
-	// rCCER(timer) = 0;
-	// rCCMR1(timer) = 0;
-	// rCCMR2(timer) = 0;
-	// rCCR1(timer) = 0;
-	// rCCR2(timer) = 0;
-	// rCCR3(timer) = 0;
-	// rCCR4(timer) = 0;
-	// rCCER(timer) = 0;
-	// rDCR(timer) = 0;
+// modifyreg32(led_pwm_timers[timer].clock_register, 0, led_pwm_timers[timer].clock_bit);
 
-	// if ((led_pwm_timers[timer].base == STM32_TIM1_BASE) || (led_pwm_timers[timer].base == STM32_TIM8_BASE)) {
+// /* disable and configure the timer */
+// rCR1(timer) = 0;
+// rCR2(timer) = 0;
+// rSMCR(timer) = 0;
+// rDIER(timer) = 0;
+// rCCER(timer) = 0;
+// rCCMR1(timer) = 0;
+// rCCMR2(timer) = 0;
+// rCCR1(timer) = 0;
+// rCCR2(timer) = 0;
+// rCCR3(timer) = 0;
+// rCCR4(timer) = 0;
+// rCCER(timer) = 0;
+// rDCR(timer) = 0;
 
-	// 	/* master output enable = on */
+// if ((led_pwm_timers[timer].base == STM32_TIM1_BASE) || (led_pwm_timers[timer].base == STM32_TIM8_BASE)) {
 
-	// 	rBDTR(timer) = ATIM_BDTR_MOE;
-	// }
+// 	/* master output enable = on */
+
+// 	rBDTR(timer) = ATIM_BDTR_MOE;
+// }
 
-	// /* If the timer clock source provided as clock_freq is the STM32_APBx_TIMx_CLKIN
-	//  * then configure the timer to free-run at 1MHz.
-	//  * Otherwise, other frequencies are attainable by adjusting .clock_freq accordingly.
-	//  */
+// /* If the timer clock source provided as clock_freq is the STM32_APBx_TIMx_CLKIN
+//  * then configure the timer to free-run at 1MHz.
+//  * Otherwise, other frequencies are attainable by adjusting .clock_freq accordingly.
+//  */
 
-	// rPSC(timer) = (led_pwm_timers[timer].clock_freq / 1000000) - 1;
+// rPSC(timer) = (led_pwm_timers[timer].clock_freq / 1000000) - 1;
 
-	// /* configure the timer to update at the desired rate */
+// /* configure the timer to update at the desired rate */
 
-	// rARR(timer) = (1000000 / LED_PWM_RATE) - 1;
+// rARR(timer) = (1000000 / LED_PWM_RATE) - 1;
 
-	// /* generate an update event; reloads the counter and all registers */
-	// rEGR(timer) = GTIM_EGR_UG;
+// /* generate an update event; reloads the counter and all registers */
+// rEGR(timer) = GTIM_EGR_UG;
 
-	// px4_leave_critical_section(flags);
+// px4_leave_critical_section(flags);
 
 // }
 #endif
diff --git a/src/drivers/artosyn/drv_pwm_servo.c b/src/drivers/artosyn/drv_pwm_servo.c
index a10d914c99fd7dbd66ed1eaa91a421827b261c22..ff80ea18dbfe03ad1f76e5225e422137c164269a 100644
--- a/src/drivers/artosyn/drv_pwm_servo.c
+++ b/src/drivers/artosyn/drv_pwm_servo.c
@@ -156,7 +156,7 @@ uint32_t up_pwm_servo_get_rate_group(unsigned group)
 {
 	/* only return the set of channels in the group which we own */
 	return (io_timer_get_mode_channels(IOTimerChanMode_PWMOut) |
-		    io_timer_get_mode_channels(IOTimerChanMode_OneShot)) &
+		io_timer_get_mode_channels(IOTimerChanMode_OneShot)) &
 	       io_timer_get_group(group);
 }
 
diff --git a/src/drivers/artosyn/tone_alarm/tone_alarm.cpp b/src/drivers/artosyn/tone_alarm/tone_alarm.cpp
index f6fb337476e609d03c8ccef35257ecd15aca4f0a..db95cc4066a77b571d35f7eaacbd0c7e6191d53d 100644
--- a/src/drivers/artosyn/tone_alarm/tone_alarm.cpp
+++ b/src/drivers/artosyn/tone_alarm/tone_alarm.cpp
@@ -127,7 +127,7 @@
 
 /*
  * Timer register accessors
- */                        
+ */
 #define REG_TONE(_reg)	    (TONE_ALARM_TIMER_BASE + _reg)
 
 #define rTIMERLOADCOUNT_TONE        REG_TONE(AR_TIM_TIMER0LOADCOUNT_OFFSET   )
@@ -151,11 +151,10 @@ public:
 	_EXT_ITCM virtual int init();
 	_EXT_ITCM void status();
 
-	enum
-    {
-        CBRK_OFF = 0,
-        CBRK_ON,
-        CBRK_UNINIT
+	enum {
+		CBRK_OFF = 0,
+		CBRK_ON,
+		CBRK_UNINIT
 	};
 
 private:
@@ -223,8 +222,7 @@ ToneAlarm::~ToneAlarm()
 	_should_run = false;
 	int counter = 0;
 
-	while (_running && ++counter < 10) 
-	{
+	while (_running && ++counter < 10) {
 		usleep(100000);
 	}
 }
@@ -235,8 +233,7 @@ int ToneAlarm::init()
 
 	ret = CDev::init();
 
-	if (ret != OK) 
-	{
+	if (ret != OK) {
 		return ret;
 	}
 
@@ -244,25 +241,25 @@ int ToneAlarm::init()
 	px4_arch_configgpio(GPIO_TONE_ALARM_IDLE);
 
 	/* clock/power on our timer */
-    // AR8020 do nothing 
+	// AR8020 do nothing
 
 	/* initialise the timer */
 	/*freerun timer*/
 	putreg32(AR_TIMERCONTROLREG_ENABLE_DISABLE, rTIMERCONTROLREG_TONE);
 
-    /* clear cnt */
-	putreg32(0x0000FFFF,rTIMERLOADCOUNT_TONE);
+	/* clear cnt */
+	putreg32(0x0000FFFF, rTIMERLOADCOUNT_TONE);
 
-    /* clear cnt2 */
-	putreg32(0x0000FFFF,rTIMERLOADCOUNT2_TONE);
+	/* clear cnt2 */
+	putreg32(0x0000FFFF, rTIMERLOADCOUNT2_TONE);
 
-    getreg32(rTIMEREOI_TONE);	/* clear inturput */
+	getreg32(rTIMEREOI_TONE);	/* clear inturput */
 
 	putreg32(AR_TIMERCONTROLREG_PWM_DISABLE	| \
-			AR_TIMERCONTROLREG_INTMASK_MASKED 	| \
-			AR_TIMERCONTROLREG_MODE_USERDEFINED | \
-			AR_TIMERCONTROLREG_ENABLE_ENABLE, \
-            rTIMERCONTROLREG_TONE);
+		 AR_TIMERCONTROLREG_INTMASK_MASKED 	| \
+		 AR_TIMERCONTROLREG_MODE_USERDEFINED | \
+		 AR_TIMERCONTROLREG_ENABLE_ENABLE, \
+		 rTIMERCONTROLREG_TONE);
 
 	DEVICE_DEBUG("ready");
 
@@ -273,12 +270,10 @@ int ToneAlarm::init()
 
 void ToneAlarm::status()
 {
-	if (_running) 
-    {
+	if (_running) {
 		PX4_INFO("running");
-	} 
-    else 
-    {
+
+	} else {
 		PX4_INFO("stopped");
 	}
 }
@@ -296,8 +291,7 @@ unsigned ToneAlarm::frequency_to_divisor(unsigned frequency)
 void ToneAlarm::start_note(unsigned frequency)
 {
 	// check if circuit breaker is enabled
-	if (_cbrk == CBRK_UNINIT) 
-    {
+	if (_cbrk == CBRK_UNINIT) {
 		_cbrk = circuit_breaker_enabled("CBRK_BUZZER", CBRK_BUZZER_KEY);
 	}
 
@@ -309,14 +303,14 @@ void ToneAlarm::start_note(unsigned frequency)
 	// calculate the timer period for the selected prescaler value
 	unsigned period = (divisor / 2) - 1;
 
-    putreg32(period,rTIMERLOADCOUNT_TONE);
-    putreg32(period,rTIMERLOADCOUNT2_TONE);
+	putreg32(period, rTIMERLOADCOUNT_TONE);
+	putreg32(period, rTIMERLOADCOUNT2_TONE);
 
-    putreg32(AR_TIMERCONTROLREG_PWM_ENABLE	| \
-			AR_TIMERCONTROLREG_INTMASK_MASKED 	| \
-			AR_TIMERCONTROLREG_MODE_USERDEFINED | \
-			AR_TIMERCONTROLREG_ENABLE_ENABLE, \
-            rTIMERCONTROLREG_TONE);
+	putreg32(AR_TIMERCONTROLREG_PWM_ENABLE	| \
+		 AR_TIMERCONTROLREG_INTMASK_MASKED 	| \
+		 AR_TIMERCONTROLREG_MODE_USERDEFINED | \
+		 AR_TIMERCONTROLREG_ENABLE_ENABLE, \
+		 rTIMERCONTROLREG_TONE);
 
 	// configure the GPIO to enable timer output
 	px4_arch_configgpio(GPIO_TONE_ALARM);
@@ -326,10 +320,10 @@ void ToneAlarm::stop_note()
 {
 	/* stop the current note */
 	putreg32(AR_TIMERCONTROLREG_PWM_DISABLE	| \
-			AR_TIMERCONTROLREG_INTMASK_MASKED 	| \
-			AR_TIMERCONTROLREG_MODE_USERDEFINED | \
-			AR_TIMERCONTROLREG_ENABLE_ENABLE, \
-            rTIMERCONTROLREG_TONE);
+		 AR_TIMERCONTROLREG_INTMASK_MASKED 	| \
+		 AR_TIMERCONTROLREG_MODE_USERDEFINED | \
+		 AR_TIMERCONTROLREG_ENABLE_ENABLE, \
+		 rTIMERCONTROLREG_TONE);
 
 	/*
 	 * Make sure the GPIO is not driving the speaker.
@@ -339,10 +333,8 @@ void ToneAlarm::stop_note()
 
 void ToneAlarm::next_note()
 {
-	if (!_should_run) 
-	{
-		if (_tune_control_sub >= 0) 
-		{
+	if (!_should_run) {
+		if (_tune_control_sub >= 0) {
 			orb_unsubscribe(_tune_control_sub);
 		}
 
@@ -351,14 +343,12 @@ void ToneAlarm::next_note()
 	}
 
 	// subscribe to tune_control
-	if (_tune_control_sub < 0) 
-	{
+	if (_tune_control_sub < 0) {
 		_tune_control_sub = orb_subscribe(ORB_ID(tune_control));
 	}
 
 	// do we have an inter-note gap to wait for?
-	if (_silence_length > 0) 
-	{
+	if (_silence_length > 0) {
 		stop_note();
 		work_queue(HPWORK, &_work, (worker_t)&ToneAlarm::next_trampoline, this, USEC2TICK(_silence_length));
 		_silence_length = 0;
@@ -369,8 +359,7 @@ void ToneAlarm::next_note()
 	bool updated = false;
 	orb_check(_tune_control_sub, &updated);
 
-	if (updated) 
-	{
+	if (updated) {
 		orb_copy(ORB_ID(tune_control), _tune_control_sub, &_tune);
 
 		if (_tunes.set_control(_tune) == 0) {
@@ -383,38 +372,32 @@ void ToneAlarm::next_note()
 
 	unsigned frequency = 0, duration = 0;
 
-	if (_play_tone) 
-	{
+	if (_play_tone) {
 		_play_tone = false;
 		int parse_ret_val = _tunes.get_next_tune(frequency, duration, _silence_length);
 
-		if (parse_ret_val >= 0) 
-		{
+		if (parse_ret_val >= 0) {
 			// a frequency of 0 correspond to stop_note
-            if (frequency > 0) 
-            {
-                // start playing the note
-                start_note(frequency);
-            } 
-            else 
-            {
-                stop_note();
-            }
-
-            if (parse_ret_val > 0) 
-            {
-                // continue playing
-                _play_tone = true;
-            }
+			if (frequency > 0) {
+				// start playing the note
+				start_note(frequency);
+
+			} else {
+				stop_note();
+			}
+
+			if (parse_ret_val > 0) {
+				// continue playing
+				_play_tone = true;
+			}
 		}
-    } 
-    else 
-    {
-        // schedule a call with the tunes max interval
-        duration = _tunes.get_maximum_update_interval();
-        // stop playing the last note after the duration elapsed
-        stop_note();
-    }
+
+	} else {
+		// schedule a call with the tunes max interval
+		duration = _tunes.get_maximum_update_interval();
+		// stop playing the last note after the duration elapsed
+		stop_note();
+	}
 
 	// and arrange a callback when the note should stop
 	work_queue(HPWORK, &_work, (worker_t)&ToneAlarm::next_trampoline, this, USEC2TICK(duration));
@@ -446,30 +429,24 @@ _EXT_ITCM void tone_alarm_usage()
 _EXT_ITCM int tone_alarm_main(int argc, char *argv[])
 {
 
-	if (argc > 1) 
-    {
+	if (argc > 1) {
 		const char *argv1 = argv[1];
 
-		if (!strcmp(argv1, "start")) 
-        {
-			if (g_dev != nullptr) 
-            {
+		if (!strcmp(argv1, "start")) {
+			if (g_dev != nullptr) {
 				PX4_ERR("already started");
 				exit(1);
 			}
 
-			if (g_dev == nullptr) 
-            {
+			if (g_dev == nullptr) {
 				g_dev = new ToneAlarm();
 
-				if (g_dev == nullptr) 
-                {
+				if (g_dev == nullptr) {
 					PX4_ERR("couldn't allocate the ToneAlarm driver");
 					exit(1);
 				}
 
-				if (OK != g_dev->init()) 
-                {
+				if (OK != g_dev->init()) {
 					delete g_dev;
 					g_dev = nullptr;
 					PX4_ERR("ToneAlarm init failed");
@@ -480,15 +457,13 @@ _EXT_ITCM int tone_alarm_main(int argc, char *argv[])
 			exit(0);
 		}
 
-		if (!strcmp(argv1, "stop")) 
-        {
+		if (!strcmp(argv1, "stop")) {
 			delete g_dev;
 			g_dev = nullptr;
 			exit(0);
 		}
 
-		if (!strcmp(argv1, "status")) 
-        {
+		if (!strcmp(argv1, "status")) {
 			g_dev->status();
 			exit(0);
 		}
diff --git a/src/drivers/barometer/ms5611/ms5611.cpp b/src/drivers/barometer/ms5611/ms5611.cpp
index 03f027da6bceccf24a89b867e1b7a5a21996f197..fc3cc4a34e9612b03867b96d83880f33da76e862 100644
--- a/src/drivers/barometer/ms5611/ms5611.cpp
+++ b/src/drivers/barometer/ms5611/ms5611.cpp
@@ -288,7 +288,7 @@ MS5611::init()
 	bool autodetect = false;
 
 	ret = CDev::init();
-	
+
 	if (ret != OK) {
 		DEVICE_DEBUG("CDev init failed");
 		goto out;
@@ -325,6 +325,7 @@ MS5611::init()
 		}
 
 		usleep(MS5611_CONVERSION_INTERVAL);
+
 		if (OK != collect()) {
 			ret = -EIO;
 			break;
@@ -383,16 +384,14 @@ MS5611::init()
 		brp.device_id = _device_id.devid;
 
 		ret = OK;
-		
-		if (_interface->get_device_address() == PX4_SPIDEV_EXT_BARO)
-		{
+
+		if (_interface->get_device_address() == PX4_SPIDEV_EXT_BARO) {
 			_baro_topic = orb_advertise_multi(ORB_ID(sensor_baro), &brp,
-						  &_orb_class_instance, ORB_PRIO_HIGH );
-		}
-		else 
-		{
+							  &_orb_class_instance, ORB_PRIO_HIGH);
+
+		} else {
 			_baro_topic = orb_advertise_multi(ORB_ID(sensor_baro), &brp,
-						  &_orb_class_instance, ORB_PRIO_DEFAULT );
+							  &_orb_class_instance, ORB_PRIO_DEFAULT);
 		}
 
 		if (_baro_topic == nullptr) {
@@ -867,7 +866,7 @@ struct ms5611_bus_option {
 	MS5611 *dev;
 } bus_options[] = {
 #if defined(PX4_SPIDEV_EXT_BARO) && defined(PX4_SPI_BUS_EXT)
-	{ MS5611_BUS_SPI_EXTERNAL, "/dev/ms5611_spi_ext", &MS5611_spi_interface, PX4_SPI_BUS_EXT + 1 , NULL }, // due to  PX4_SPI_BUS_EXT == PX4_SPI_BUS_BARO
+	{ MS5611_BUS_SPI_EXTERNAL, "/dev/ms5611_spi_ext", &MS5611_spi_interface, PX4_SPI_BUS_EXT + 1, NULL },  // due to  PX4_SPI_BUS_EXT == PX4_SPI_BUS_BARO
 #endif
 #ifdef PX4_SPIDEV_BARO
 	{ MS5611_BUS_SPI_INTERNAL, "/dev/ms5611_spi_int", &MS5611_spi_interface, PX4_SPI_BUS_BARO, NULL },
@@ -941,7 +940,7 @@ start_bus(struct ms5611_bus_option &bus, enum MS56XX_DEVICE_TYPES device_type)
 	if (bus.dev != nullptr) {
 		errx(1, "bus option already started");
 	}
-	
+
 	prom_u prom_buf;
 	device::Device *interface = bus.interface_constructor(prom_buf, bus.busnum);
 
diff --git a/src/drivers/barometer/ms5611/ms5611_spi.cpp b/src/drivers/barometer/ms5611/ms5611_spi.cpp
index 1ee80dfa2ae847b65ecfbf340ba628f002fc3506..eb53ca432e9507d26d3e01f7258aa88b361458ac 100644
--- a/src/drivers/barometer/ms5611/ms5611_spi.cpp
+++ b/src/drivers/barometer/ms5611/ms5611_spi.cpp
@@ -119,7 +119,8 @@ MS5611_spi_interface(ms5611::prom_u &prom_buf, uint8_t busnum)
 {
 
 #ifdef PX4_SPI_BUS_EXT
-	if (busnum == (PX4_SPI_BUS_EXT + 1) ) {
+
+	if (busnum == (PX4_SPI_BUS_EXT + 1)) {
 #ifdef PX4_SPIDEV_EXT_BARO
 		return new MS5611_SPI(busnum - 1, PX4_SPIDEV_EXT_BARO, prom_buf);
 #else
@@ -267,6 +268,7 @@ MS5611_SPI::_read_prom()
 		if (_prom.c[i] != 0) {
 			all_zero = false;
 		}
+
 		//DEVICE_DEBUG("prom[%u]=0x%x", (unsigned)i, (unsigned)_prom.c[i]);
 	}
 
diff --git a/src/drivers/boards/common/artosyn/board_hw_rev_ver.c b/src/drivers/boards/common/artosyn/board_hw_rev_ver.c
index aa4b80d0b61d486b103d2ce1f05b7f506dc6d647..72e48f3998fcaec723f5192da753f22f0c73f996 100644
--- a/src/drivers/boards/common/artosyn/board_hw_rev_ver.c
+++ b/src/drivers/boards/common/artosyn/board_hw_rev_ver.c
@@ -81,16 +81,14 @@ static char hw_info[] = HW_INFO_INIT;
 _EXT_ITCM static int dn_to_ordinal(uint16_t dn)
 {
 
-	const struct 
-    {
-		uint16_t low;  
-		uint16_t high; 
-	} dn2o[] = 
-    {
-		                //    R1(up) R2(down) V tpy   V min   V Max   DN Min  DN Max
-		{0   ,  205 },  //0   NC     0R       0.000   0.000   0.125   0       205                                    
-		{206 ,  615 },  //1   180K   20K      0.025   0.125   0.375   206     615 
-		{616 ,  1024},  //2   82K    20K      0.490   0.375   0.625   616     1024
+	const struct {
+		uint16_t low;
+		uint16_t high;
+	} dn2o[] = {
+		//    R1(up) R2(down) V tpy   V min   V Max   DN Min  DN Max
+		{0,  205 },     //0   NC     0R       0.000   0.000   0.125   0       205
+		{206,  615 },   //1   180K   20K      0.025   0.125   0.375   206     615
+		{616,  1024},   //2   82K    20K      0.490   0.375   0.625   616     1024
 		{1025,  1434},  //3   120K   51K      0.756   0.625   0.875   1025    1434
 		{1435,  1843},  //4   150K   100K     1.000   0.875   1.125   1435    1843
 		{1844,  2253},  //5   100K   100K     1.250   1.125   1.375   1844    2253
@@ -101,10 +99,8 @@ _EXT_ITCM static int dn_to_ordinal(uint16_t dn)
 		{3892,  4095},  //10  0R     NC       2.500   2.375   2.500   3892    4095
 	};
 
-	for (unsigned int i = 0; i < arraySize(dn2o); i++) 
-    {
-		if (dn >= dn2o[i].low && dn <= dn2o[i].high) 
-        {
+	for (unsigned int i = 0; i < arraySize(dn2o); i++) {
+		if (dn >= dn2o[i].low && dn <= dn2o[i].high) {
 			return i;
 		}
 	}
@@ -144,7 +140,7 @@ _EXT_ITCM static int dn_to_ordinal(uint16_t dn)
  *
  ************************************************************************************/
 
-_EXT_ITCM static int read_id_dn( int *id, int adc_channel)
+_EXT_ITCM static int read_id_dn(int *id, int adc_channel)
 {
 	int rv = -EIO;
 	const unsigned int samples  = 16;
@@ -152,45 +148,41 @@ _EXT_ITCM static int read_id_dn( int *id, int adc_channel)
 	uint32_t dn_sum = 0;
 	uint16_t dn = 0;
 
-	if (board_adc_init() == OK) 
-	{
+	if (board_adc_init() == OK) {
 		/* Read the value */
-		for (unsigned av = 0; av < samples; av++) 
-		{
+		for (unsigned av = 0; av < samples; av++) {
 			dn = board_adc_sample(adc_channel);
-			hwinfo("dn = %d\r\n",dn);
+			hwinfo("dn = %d\r\n", dn);
+
 			if (dn == 0xffff) { break; }
 
 			dn_sum  += dn;
 		}
 
-		if (dn != 0xffff) 
-		{
+		if (dn != 0xffff) {
 			*id = dn_sum / samples;
 			rv = OK;
 		}
 	}
-	
+
 	return rv;
 }
 
 
 _EXT_ITCM static int determine_hw_info(int *revision, int *version)
 {
-    int dn;
-    int rv = read_id_dn(&dn, ADC_HW_REV_SENSE_CHANNEL);
+	int dn;
+	int rv = read_id_dn(&dn, ADC_HW_REV_SENSE_CHANNEL);
 
-    if (rv == OK) 
-    {
-        *revision =  dn_to_ordinal(dn);
-    }
+	if (rv == OK) {
+		*revision =  dn_to_ordinal(dn);
+	}
 
-    rv = read_id_dn(&dn, ADC_HW_VER_SENSE_CHANNEL);
+	rv = read_id_dn(&dn, ADC_HW_VER_SENSE_CHANNEL);
 
-    if (rv == OK) 
-    {
-        *version =  dn_to_ordinal(dn);
-    }
+	if (rv == OK) {
+		*version =  dn_to_ordinal(dn);
+	}
 
 	return rv;
 }
@@ -285,8 +277,7 @@ int board_determine_hw_info()
 {
 	int rv = determine_hw_info(&hw_revision, &hw_version);
 
-	if (rv == OK) 
-	{
+	if (rv == OK) {
 		hw_info[HW_INFO_INIT_REV] = board_get_hw_revision() + '0';
 		hw_info[HW_INFO_INIT_VER] = board_get_hw_version() + '0';
 	}
diff --git a/src/drivers/boards/common/artosyn/board_identity.c b/src/drivers/boards/common/artosyn/board_identity.c
index 6a25476717d2220e032367e9be7ff69d15e9e77a..fd579444ab4a2d5d3eab13425a934949c337c195 100644
--- a/src/drivers/boards/common/artosyn/board_identity.c
+++ b/src/drivers/boards/common/artosyn/board_identity.c
@@ -80,8 +80,8 @@ __EXPORT void board_get_uuid32(uuid_uint32_t uuid_words)
 }
 
 _EXT_ITCM int board_get_uuid32_formated(char *format_buffer, int size,
-			      const char *format,
-			      const char *seperator)
+					const char *format,
+					const char *seperator)
 {
 	// uuid_uint32_t uuid;
 	// board_get_uuid32(uuid);
diff --git a/src/drivers/boards/coolfly-f1/board_config.h b/src/drivers/boards/coolfly-f1/board_config.h
index 906cbbec57de842aa8d97abe75815ad0b2b47c6a..2fc42c6cb57067c5f63a9011aa373266d7bc1fb0 100644
--- a/src/drivers/boards/coolfly-f1/board_config.h
+++ b/src/drivers/boards/coolfly-f1/board_config.h
@@ -60,7 +60,7 @@
  */
 //#define PX4_FMUV5_RC00
 
-#define COOLFLY_F1						
+#define COOLFLY_F1
 
 #define PX4_FMUV5_RC01
 #define BOARD_HAS_LTC4417
@@ -161,10 +161,10 @@
 // #define PX4_SPIDEV_AUX_MEM          PX4_MK_SPI_SEL(PX4_SPI_BUS_SENSORS,4)
 
 #define PX4_SENSOR_BUS_CS_GPIO      {	GPIO_SPI6_CS1_ICM20689, 	\
-										GPIO_SPI6_CS2_ICM20602, 	\
-										GPIO_SPI6_CS3_BMI055_GYRO, 	\
-										GPIO_SPI6_CS4_BMI055_ACC	\
-									}
+		GPIO_SPI6_CS2_ICM20602, 	\
+		GPIO_SPI6_CS3_BMI055_GYRO, 	\
+		GPIO_SPI6_CS4_BMI055_ACC	\
+	}
 
 #define PX4_SENSORS_BUS_FIRST_CS    PX4_SPIDEV_ICM_20689
 #define PX4_SENSORS_BUS_LAST_CS     GPIO_SPI6_CS4_BMI055_ACC
@@ -175,9 +175,9 @@
 #define PX4_SPIDEV_EXT_BARO					PX4_SPIDEV_BARO_ONBOARD
 
 #define PX4_BARO_BUS_CS_GPIO            {\
-											GPIO_SPI4_CS1_MS5611, 		  \
-											GPIO_SPI4_CS2_MS5611_ONBOARD  \
-										}
+		GPIO_SPI4_CS1_MS5611, 		  \
+		GPIO_SPI4_CS2_MS5611_ONBOARD  \
+	}
 
 
 #define PX4_BARO_BUS_FIRST_CS       PX4_SPIDEV_BARO
@@ -265,8 +265,8 @@
 	 (1 << ADC_HW_VER_SENSE_CHANNEL)           | \
 	 (1 << ADC_HW_REV_SENSE_CHANNEL)           | \
 	 (1 << ADC1_SPARE_1_CHANNEL)               | \
-     (1 << ADC_TEMPERATURE_AR8020_CHANNEL)     | \
-     (1 << ADC_TEMPERATURE_PA_A_CHANNEL)       | \
+	 (1 << ADC_TEMPERATURE_AR8020_CHANNEL)     | \
+	 (1 << ADC_TEMPERATURE_PA_A_CHANNEL)       | \
 	 (1 << ADC_TEMPERATURE_PA_B_CHANNEL))
 
 
@@ -283,7 +283,7 @@
 
 /* HW Version and Revision drive signals Default to 1 to detect */
 
-#define BOARD_HAS_HW_VERSIONING				
+#define BOARD_HAS_HW_VERSIONING
 
 
 #define HW_INFO_INIT         {'V','2','x', 'x',0}
@@ -552,7 +552,7 @@
 
 
 #define PX4_GPIO_PWM_INIT_LIST { \
-        GPIO_GPIO9_INPUT, \
+		GPIO_GPIO9_INPUT, \
 		GPIO_GPIO8_INPUT, \
 		GPIO_GPIO7_INPUT, \
 		GPIO_GPIO6_INPUT, \
@@ -578,7 +578,7 @@
 		GPIO_CAN0_RX,       \
 		GPIO_CAN1_TX,       \
 		GPIO_CAN1_RX,       \
-        GPIO_LNA_BYPASS,    \
+		GPIO_LNA_BYPASS,    \
 		GPIO_nPOWER_IN_A,                 	\
 		GPIO_nPOWER_IN_B,                 	\
 		GPIO_nPOWER_IN_C,                 	\
@@ -633,15 +633,15 @@
 #define GPIO_SPI3_MISO     	(GPIO_OUTPUT|GPIO_OUTRESET|GPIO_PIN61)
 
 #define CF_GPIO_INIT_NOUSED_LIST {    \
-        GPIO_SPI2_CS,  		\
-        GPIO_SPI2_SCK, 		\
-        GPIO_SPI2_MOSI,		\
-        GPIO_SPI2_MISO,     \
-        GPIO_SPI3_CS,  		\
-        GPIO_SPI3_SCK, 		\
-        GPIO_SPI3_MOSI,		\
-        GPIO_SPI3_MISO      \
-    }
+		GPIO_SPI2_CS,  		\
+		GPIO_SPI2_SCK, 		\
+		GPIO_SPI2_MOSI,		\
+		GPIO_SPI2_MISO,     \
+		GPIO_SPI3_CS,  		\
+		GPIO_SPI3_SCK, 		\
+		GPIO_SPI3_MOSI,		\
+		GPIO_SPI3_MISO      \
+	}
 
 
 #define GPIO_DVP0_DATA0     (GPIO_DEFAULT|GPIO_PIN16)
@@ -674,32 +674,32 @@
 #define GPIO_ITE_INT1     	(GPIO_INPUT|GPIO_PIN27)
 
 #define CF_GPIO_INIT_DVP_LIST {    \
-        GPIO_DVP0_DATA0,    \
-        GPIO_DVP0_DATA1,    \
-        GPIO_DVP0_DATA2,    \
-        GPIO_DVP0_DATA3,    \
-        GPIO_DVP0_DATA4,    \
-        GPIO_DVP0_DATA5,    \
-        GPIO_DVP0_DATA6,    \
-        GPIO_DVP0_DATA7,    \
-        GPIO_DVP0_VS,       \
-        GPIO_DVP0_HS,       \
-        GPIO_DVP0_DE,       \
-        GPIO_DVP1_DATA0,    \
-        GPIO_DVP1_DATA1,    \
-        GPIO_DVP1_DATA2,    \
-        GPIO_DVP1_DATA3,    \
-        GPIO_DVP1_DATA4,    \
-        GPIO_DVP1_DATA5,    \
-        GPIO_DVP1_DATA6,    \
-        GPIO_DVP1_DATA7,    \
-        GPIO_DVP1_VS , 	 	\
-        GPIO_DVP1_HS ,  	\
-        GPIO_DVP1_DE,		\
+		GPIO_DVP0_DATA0,    \
+		GPIO_DVP0_DATA1,    \
+		GPIO_DVP0_DATA2,    \
+		GPIO_DVP0_DATA3,    \
+		GPIO_DVP0_DATA4,    \
+		GPIO_DVP0_DATA5,    \
+		GPIO_DVP0_DATA6,    \
+		GPIO_DVP0_DATA7,    \
+		GPIO_DVP0_VS,       \
+		GPIO_DVP0_HS,       \
+		GPIO_DVP0_DE,       \
+		GPIO_DVP1_DATA0,    \
+		GPIO_DVP1_DATA1,    \
+		GPIO_DVP1_DATA2,    \
+		GPIO_DVP1_DATA3,    \
+		GPIO_DVP1_DATA4,    \
+		GPIO_DVP1_DATA5,    \
+		GPIO_DVP1_DATA6,    \
+		GPIO_DVP1_DATA7,    \
+		GPIO_DVP1_VS , 	 	\
+		GPIO_DVP1_HS ,  	\
+		GPIO_DVP1_DE,		\
 		GPIO_ITE_RST0,      \
 		GPIO_ITE_RST1,      \
-        GPIO_ITE_INT0,      \
-        GPIO_ITE_INT1      	\
+		GPIO_ITE_INT0,      \
+		GPIO_ITE_INT1      	\
 	}
 
 
diff --git a/src/drivers/boards/coolfly-f1/init.c b/src/drivers/boards/coolfly-f1/init.c
index 32fc0b5a401a18687fedf1170176f34451cfbf0e..9933170f36079172239743eb1b1ca48176448fa0 100644
--- a/src/drivers/boards/coolfly-f1/init.c
+++ b/src/drivers/boards/coolfly-f1/init.c
@@ -206,25 +206,23 @@ __EXPORT void board_on_reset(int status)
 {
 	/* configure the GPIO pins to outputs and keep them low */
 	// reset to boot loader
-	if(status >= 0)
-	{		
-		*((volatile uint32_t*)0xA0030088) = 1;
+	if (status >= 0) {
+		*((volatile uint32_t *)0xA0030088) = 1;
 
-		uint32_t *signal = (uint32_t * )SRAM_REBOOT_SIGNAL_ST_ADDR;
+		uint32_t *signal = (uint32_t *)SRAM_REBOOT_SIGNAL_ST_ADDR;
 
 		*signal = 0x12345678;
 
 		up_mdelay(1000);
 
-		if (*signal != 0x87654321)
-		{
-			PX4_INFO("CPU2 NOT RESPONSE");	
+		if (*signal != 0x87654321) {
+			PX4_INFO("CPU2 NOT RESPONSE");
 		}
 	}
 
 	const uint32_t gpio[] = PX4_GPIO_PWM_INIT_LIST;
 	board_gpio_init(gpio, arraySize(gpio));
-	
+
 	if (status >= 0) {
 		up_mdelay(6);
 	}
@@ -240,20 +238,20 @@ __EXPORT void board_on_reset(int status)
  *   and mapped but before any devices have been initialized.
  *	 cf: initialize the all GPIO
  ************************************************************************************/
- void
+void
 _EXT_ITCM ar_boardinitialize(void)
 {
 	board_on_reset(-1); /* Reset PWM first thing */
 
 	/* configure LEDs */
 
-	board_autoled_initialize();		
+	board_autoled_initialize();
 
 	/* configure pins */
 
 	const uint32_t gpio1[] = PX4_GPIO_INIT_LIST;
 	board_gpio_init(gpio1, arraySize(gpio1));
-	
+
 	const uint32_t gpio2[] = CF_GPIO_INIT_NOUSED_LIST;
 	board_gpio_init(gpio2, arraySize(gpio2));
 
@@ -324,7 +322,7 @@ _EXT_ITCM  int board_app_initialize(uintptr_t arg)
 
 	/* configure the high-resolution time/callout interface */
 	hrt_init();
-	
+
 	if (OK == board_determine_hw_info()) {
 		PX4_INFO("Rev 0x%1x : Ver 0x%1x %s", board_get_hw_revision(), board_get_hw_version(), board_get_hw_type_name());
 
@@ -344,7 +342,7 @@ _EXT_ITCM  int board_app_initialize(uintptr_t arg)
 #ifdef CONFIG_SCHED_INSTRUMENTATION
 	cpuload_initialize_once();
 #endif
-	
+
 
 #if defined(CONFIG_AR_BBSRAM)
 
@@ -355,7 +353,7 @@ _EXT_ITCM  int board_app_initialize(uintptr_t arg)
 	/* Using Battery Backed Up SRAM */
 
 	int filesizes[CONFIG_AR_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES;
-					
+
 	ar_bbsraminitialize(BBSRAM_PATH, filesizes);
 
 #if defined(CONFIG_AR_SAVE_CRASHDUMP)
@@ -380,6 +378,7 @@ _EXT_ITCM  int board_app_initialize(uintptr_t arg)
 	 *  - this will be reset after a successful commit to SD
 	 */
 	int hadCrash = hardfault_check_status("boot");
+
 	if (hadCrash == OK) {
 
 		PX4_ERR("[boot] There is a hard fault logged. Hold down the SPACE BAR," \
@@ -494,7 +493,7 @@ _EXT_ITCM  int board_app_initialize(uintptr_t arg)
 #endif
 
 #ifdef CONFIG_MMCSD
-	
+
 	ret = ar_sdio_initialize();
 
 	if (ret != OK) {
diff --git a/src/drivers/boards/coolfly-f1/led.c b/src/drivers/boards/coolfly-f1/led.c
index 3bbc0857187923d8463e6e5adf2cde95e89d121b..4a3dfa89d12f92fbc74eca1e3a88da7716ec1c48 100644
--- a/src/drivers/boards/coolfly-f1/led.c
+++ b/src/drivers/boards/coolfly-f1/led.c
@@ -88,7 +88,7 @@ static uint32_t g_ledmap[] = {
 
 #endif
 
- __EXPORT void led_init(void)
+__EXPORT void led_init(void)
 {
 	/* Configure LED GPIOs for output */
 	for (size_t l = 0; l < (sizeof(g_ledmap) / sizeof(g_ledmap[0])); l++) {
@@ -109,19 +109,19 @@ _EXT_ITCM static bool phy_get_led(int led)
 	return !ar_gpioread(g_ledmap[led]);
 }
 
- __EXPORT void led_on(int led)
+__EXPORT void led_on(int led)
 {
 	phy_set_led(xlat(led), true);
 }
 
- __EXPORT void led_off(int led)
+__EXPORT void led_off(int led)
 {
 	phy_set_led(xlat(led), false);
 }
 
- __EXPORT void led_toggle(int led)
+__EXPORT void led_toggle(int led)
 {
-	
+
 	phy_set_led(xlat(led), !phy_get_led(xlat(led)));
 }
 
diff --git a/src/drivers/boards/coolfly-f1/sdio.c b/src/drivers/boards/coolfly-f1/sdio.c
index 3abae369e7b83c022ba8bc051cde7fb4d85756e6..9e3f1e0ca9d7e84781b3a83add4c02f2b548b0d9 100644
--- a/src/drivers/boards/coolfly-f1/sdio.c
+++ b/src/drivers/boards/coolfly-f1/sdio.c
@@ -73,7 +73,7 @@
 
 static FAR struct sdio_dev_s *sdio_dev;
 #ifdef HAVE_NCD
-	static bool g_sd_inserted = 0xff; /* Impossible value */
+static bool g_sd_inserted = 0xff; /* Impossible value */
 #endif
 
 /****************************************************************************
@@ -95,7 +95,7 @@ static FAR struct sdio_dev_s *sdio_dev;
 
 _EXT_ITCM int ar_sdio_initialize(void)
 {
-int ret;
+	int ret;
 
 
 
@@ -105,8 +105,7 @@ int ret;
 
 	sdio_dev = ar_sdmmc_initialize(SDIO_SLOTNO);
 
-	if (!sdio_dev) 
-	{
+	if (!sdio_dev) {
 		PX4_ERR("[boot] Failed to initialize SDIO slot %d\n", SDIO_SLOTNO);
 		return -ENODEV;
 	}
@@ -117,8 +116,7 @@ int ret;
 
 	ret = mmcsd_slotinitialize(SDIO_MINOR, sdio_dev);
 
-	if (ret != OK) 
-	{
+	if (ret != OK) {
 		PX4_ERR("[boot] Failed to bind SDIO to the MMC/SD driver: %d\n", ret);
 		return ret;
 	}
diff --git a/src/drivers/boards/coolfly-f1/spi.c b/src/drivers/boards/coolfly-f1/spi.c
index 973cd111877a05bef3616dc3a7295dd69eff84d3..476b70ce042e1d7a9984437b64b00ea5cc5b475c 100644
--- a/src/drivers/boards/coolfly-f1/spi.c
+++ b/src/drivers/boards/coolfly-f1/spi.c
@@ -85,13 +85,13 @@ static const uint32_t spi0selects_gpio[] = PX4_MEMORY_BUS_CS_GPIO;
  *
  ************************************************************************************/
 
- __EXPORT void ar_spiinitialize(void)
+__EXPORT void ar_spiinitialize(void)
 {
 	board_gpio_init(spi0selects_gpio, arraySize(spi0selects_gpio));
 	board_gpio_init(spi4selects_gpio, arraySize(spi4selects_gpio));
 	board_gpio_init(spi6selects_gpio, arraySize(spi6selects_gpio));
-	putreg32(0, AR_SPI0_BASE + SPI_SSIENR);	
-	putreg32(0, AR_SPI4_BASE + SPI_SSIENR);    
+	putreg32(0, AR_SPI0_BASE + SPI_SSIENR);
+	putreg32(0, AR_SPI4_BASE + SPI_SSIENR);
 	putreg32(0, AR_SPI6_BASE + SPI_SSIENR);
 }
 
@@ -107,7 +107,7 @@ static struct spi_dev_s *spi_memory;
 static struct spi_dev_s *spi_sensors;
 static struct spi_dev_s *spi_baro;
 
- __EXPORT int ar_spi_bus_initialize(void)
+__EXPORT int ar_spi_bus_initialize(void)
 {
 	/* Configure SPI-based devices */
 
@@ -115,8 +115,7 @@ static struct spi_dev_s *spi_baro;
 
 	spi_sensors = ar_spibus_initialize(PX4_SPI_BUS_SENSORS);
 
-	if (!spi_sensors) 
-	{
+	if (!spi_sensors) {
 		PX4_ERR("[boot] FAILED to initialize SPI port %d\n", PX4_SPI_BUS_SENSORS);
 		return -ENODEV;
 	}
@@ -127,8 +126,7 @@ static struct spi_dev_s *spi_baro;
 	SPI_SETBITS(spi_sensors, 8);
 	SPI_SETMODE(spi_sensors, SPIDEV_MODE3);
 
-	for (int cs = PX4_SENSORS_BUS_FIRST_CS; cs <= PX4_SENSORS_BUS_LAST_CS; cs++) 
-	{
+	for (int cs = PX4_SENSORS_BUS_FIRST_CS; cs <= PX4_SENSORS_BUS_LAST_CS; cs++) {
 		SPI_SELECT(spi_sensors, cs, false);
 	}
 
@@ -136,8 +134,7 @@ static struct spi_dev_s *spi_baro;
 
 	spi_baro = ar_spibus_initialize(PX4_SPI_BUS_BARO);
 
-	if (!spi_baro) 
-	{
+	if (!spi_baro) {
 		PX4_ERR("[boot] FAILED to initialize SPI port %d\n", PX4_SPI_BUS_BARO);
 		return -ENODEV;
 	}
@@ -226,15 +223,13 @@ __EXPORT void ar_spi4select(FAR struct spi_dev_s *dev, uint32_t devid, bool sele
 	ASSERT(PX4_SPI_BUS_ID(sel) == PX4_SPI_BUS_BARO);
 
 	/* Making sure the other peripherals are not selected */
-	for (size_t cs = 0; arraySize(spi4selects_gpio) > 1 && cs < arraySize(spi4selects_gpio); cs++) 
-	{
+	for (size_t cs = 0; arraySize(spi4selects_gpio) > 1 && cs < arraySize(spi4selects_gpio); cs++) {
 		ar_gpiowrite(spi4selects_gpio[cs], 1);
 	}
 
 	uint32_t gpio = spi4selects_gpio[PX4_SPI_DEV_ID(sel)];
 
-	if (gpio) 
-	{
+	if (gpio) {
 		ar_gpiowrite(gpio, !selected);
 	}
 }
@@ -260,15 +255,13 @@ __EXPORT void ar_spi0select(FAR struct spi_dev_s *dev, uint32_t devid, bool sele
 	ASSERT(PX4_SPI_BUS_ID(sel) == PX4_SPI_BUS_MEMORY);
 
 	/* Making sure the other peripherals are not selected */
-	for (size_t cs = 0; arraySize(spi0selects_gpio) > 1 && cs < arraySize(spi0selects_gpio); cs++) 
-	{
+	for (size_t cs = 0; arraySize(spi0selects_gpio) > 1 && cs < arraySize(spi0selects_gpio); cs++) {
 		ar_gpiowrite(spi0selects_gpio[cs], 1);
 	}
 
 	uint32_t gpio = spi0selects_gpio[PX4_SPI_DEV_ID(sel)];
 
-	if (gpio) 
-	{
+	if (gpio) {
 		ar_gpiowrite(gpio, !selected);
 	}
 }
@@ -286,7 +279,7 @@ __EXPORT uint8_t ar_spi0status(FAR struct spi_dev_s *dev, uint32_t devid)
  *
  ************************************************************************************/
 
- __EXPORT void board_spi_reset(int ms)
+__EXPORT void board_spi_reset(int ms)
 {
 	/* disable SPI bus */
 	for (size_t cs = 0;  arraySize(spi6selects_gpio) > 1 && cs < arraySize(spi6selects_gpio); cs++) {
@@ -318,7 +311,7 @@ __EXPORT uint8_t ar_spi0status(FAR struct spi_dev_s *dev, uint32_t devid)
 	ar_configgpio(GPIO_DRDY_OFF_SPI6_DRDY6_BMI055_ACC);
 #endif
 	/* set the sensor rail off */
-    ar_gpiowrite(GPIO_VDD_3V3_SENSORS_EN, 0);
+	ar_gpiowrite(GPIO_VDD_3V3_SENSORS_EN, 0);
 
 	/* wait for the sensor rail to reach GND */
 	usleep(ms * 1000);
@@ -327,7 +320,7 @@ __EXPORT uint8_t ar_spi0status(FAR struct spi_dev_s *dev, uint32_t devid)
 	/* re-enable power */
 
 	/* switch the sensor rail back on */
-    ar_gpiowrite(GPIO_VDD_3V3_SENSORS_EN, 1);
+	ar_gpiowrite(GPIO_VDD_3V3_SENSORS_EN, 1);
 
 	/* wait a bit before starting SPI, different times didn't influence results */
 	usleep(100);
diff --git a/src/drivers/boards/coolfly-f1/usb.c b/src/drivers/boards/coolfly-f1/usb.c
index ee51a19fd8e6d18b6799597727bc1fb1de0638ab..eec60103d204543e44d375bf663a8e51814d068f 100644
--- a/src/drivers/boards/coolfly-f1/usb.c
+++ b/src/drivers/boards/coolfly-f1/usb.c
@@ -78,7 +78,7 @@
  *
  ************************************************************************************/
 
- __EXPORT void ar_usbinitialize(void)
+__EXPORT void ar_usbinitialize(void)
 {
 	/* The OTG FS has an internal soft pull-up */
 
@@ -97,7 +97,7 @@
  *
  ************************************************************************************/
 
- __EXPORT void ar_usbsuspend(FAR struct usbdev_s *dev, bool resume)
+__EXPORT void ar_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
 	uinfo("resume: %d\n", resume);
 }
diff --git a/src/drivers/bootloaders/boot_app_shared.c b/src/drivers/bootloaders/boot_app_shared.c
index 9d8c1308ae46c7aaa42e8331d67b9f3372b37092..6cf46061996677c58ebf6edcc5dff4971706ab97 100644
--- a/src/drivers/bootloaders/boot_app_shared.c
+++ b/src/drivers/bootloaders/boot_app_shared.c
@@ -184,7 +184,7 @@ _EXT_ITCM static void bootloader_app_shared_init(bootloader_app_shared_t *pshare
 
 __EXPORT
 _EXT_ITCM int bootloader_app_shared_read(bootloader_app_shared_t *shared,
-			       eRole_t role)
+		eRole_t role)
 {
 	int rv = -EBADR;
 	bootloader_app_shared_t working;
@@ -226,7 +226,7 @@ _EXT_ITCM int bootloader_app_shared_read(bootloader_app_shared_t *shared,
  ****************************************************************************/
 __EXPORT
 _EXT_ITCM void bootloader_app_shared_write(bootloader_app_shared_t *shared,
-				 eRole_t role)
+		eRole_t role)
 {
 	bootloader_app_shared_t working = *shared;
 	working.signature =
diff --git a/src/drivers/coolfly/RFUart/RFUart.cpp b/src/drivers/coolfly/RFUart/RFUart.cpp
index b6ab4b46cbe9379d67d6ca5d4d126d6934c60d95..c48a8b4916b27deda3075ed449c66b9446e17601 100644
--- a/src/drivers/coolfly/RFUart/RFUart.cpp
+++ b/src/drivers/coolfly/RFUart/RFUart.cpp
@@ -33,7 +33,7 @@ public:
 private:
 	static void	cycle_trampoline(void *arg);
 
-    void transceiver();
+	void transceiver();
 
 	void handle_uart_data_send_to_sram();
 
@@ -50,14 +50,13 @@ int RFUart::print_status()
 {
 	PX4_INFO("Running as task");
 
-	if (_uart_fd < 0) 
-	{	
+	if (_uart_fd < 0) {
 		PX4_INFO("Bad fd number");
-	}
-	else
-	{
+
+	} else {
 		PX4_INFO("uart fd = %d", _uart_fd);
-	}	
+	}
+
 	return PX4_OK;
 }
 
@@ -76,13 +75,12 @@ void RFUart::transceiver()
 {
 	_uart_fd = open_uart(115200, "/dev/ttyS7");
 
-	while(!should_exit() && (_uart_fd > 0))
-	{	
+	while (!should_exit() && (_uart_fd > 0)) {
 		handle_uart_data_send_to_sram();
 
 		handle_sram_data_send_to_uart();
 
-		usleep(5000);		
+		usleep(5000);
 	}
 }
 
@@ -97,51 +95,45 @@ void RFUart::handle_uart_data_send_to_sram()
 
 	const int timeout = 10;
 
-	if (poll(&fds[0], 1, timeout) <= 0)
-	{
+	if (poll(&fds[0], 1, timeout) <= 0) {
 		return;
 	}
 
-	if ((nread = ::read(fds[0].fd, buf, sizeof(buf))) <= 0)
-	{
+	if ((nread = ::read(fds[0].fd, buf, sizeof(buf))) <= 0) {
 		return;
 	}
+
 	buf[nread] = '\0';
-	
-	do 
-	{
+
+	do {
 		char *wr_pos;
 		char *rd_pos;
 		char *tail;
 		char *head;
-		
-		STRU_SramBuffer *uartBuffer = (STRU_SramBuffer*)SRAM_UART_TO_SESSION1_DATA_ST_ADDR;
+
+		STRU_SramBuffer *uartBuffer = (STRU_SramBuffer *)SRAM_UART_TO_SESSION1_DATA_ST_ADDR;
 
 		wr_pos = (char *)uartBuffer->header.buf_wr_pos;
 		rd_pos = (char *)uartBuffer->header.buf_rd_pos;
 		head = (char *)uartBuffer->buf;
 		tail = (char *)SRAM_UART_TO_SESSION1_DATA_END_ADDR;
 
-		for (ssize_t i = 0; i < nread; i++)
-		{
+		for (ssize_t i = 0; i < nread; i++) {
 			*wr_pos = buf[i];
 
 			wr_pos++;
 
-			if (wr_pos > tail)
-			{
+			if (wr_pos > tail) {
 				wr_pos = head;
-			} 
+			}
 
-			if ((wr_pos == rd_pos) && (wr_pos != head))
-			{
+			if ((wr_pos == rd_pos) && (wr_pos != head)) {
 				PX4_INFO("wr_pos == rd_pos, may miss uart info");
 			}
 		}
 
 		uartBuffer->header.buf_wr_pos = (uint32_t)wr_pos;
-	}
-	while (0);
+	} while (0);
 }
 
 int RFUart::open_uart(int baud, const char *uart_name)
@@ -156,6 +148,7 @@ int RFUart::open_uart(int baud, const char *uart_name)
 	}
 
 	struct termios uart_config;
+
 	int termios_state;
 
 	if ((termios_state = tcgetattr(fd, &uart_config)) < 0) {
@@ -178,8 +171,7 @@ int RFUart::open_uart(int baud, const char *uart_name)
 		return -1;
 	}
 
-	do 
-	{
+	do {
 		struct termios uart_config1;
 
 		tcgetattr(fd, &uart_config1);
@@ -188,7 +180,7 @@ int RFUart::open_uart(int baud, const char *uart_name)
 
 		tcsetattr(fd, TCSANOW, &uart_config1);
 
-	} while(0);
+	} while (0);
 
 	return fd;
 }
@@ -201,31 +193,28 @@ void RFUart::handle_sram_data_send_to_uart()
 	char *head;
 
 	uint8_t data_buf_proc[512] = {0};
-    uint32_t u32_rcvLen = 0;
+	uint32_t u32_rcvLen = 0;
 
-	STRU_SramBuffer *uartBuffer = (STRU_SramBuffer*)SRAM_SESSION1_TO_UART_DATA_ST_ADDR;
+	STRU_SramBuffer *uartBuffer = (STRU_SramBuffer *)SRAM_SESSION1_TO_UART_DATA_ST_ADDR;
 
 	wr_pos = (char *)uartBuffer->header.buf_wr_pos;
 	rd_pos = (char *)uartBuffer->header.buf_rd_pos;
 	head = (char *)uartBuffer->buf;
 	tail = (char *)SRAM_SESSION1_TO_UART_DATA_END_ADDR;
 
-	while ((wr_pos != rd_pos) && (u32_rcvLen < 512))
-	{
+	while ((wr_pos != rd_pos) && (u32_rcvLen < 512)) {
 		data_buf_proc[u32_rcvLen++] = *rd_pos;
 
 		rd_pos++;
 
-		if (rd_pos > tail)
-        {
-            rd_pos = head;
-        }
+		if (rd_pos > tail) {
+			rd_pos = head;
+		}
 	}
 
 	uartBuffer->header.buf_rd_pos = (uint32_t)rd_pos;
 
-	if(u32_rcvLen > 0)
-	{
+	if (u32_rcvLen > 0) {
 		write(_uart_fd, data_buf_proc, u32_rcvLen);
 	}
 }
@@ -247,12 +236,12 @@ void RFUart::cycle_trampoline(void *arg)
 	if (dev == nullptr) {
 
 		dev = new RFUart();
-		
-		if (dev == nullptr)
-		{
+
+		if (dev == nullptr) {
 			PX4_ERR("alloc failed");
 			return;
 		}
+
 		_object = dev;
 	}
 
@@ -261,9 +250,10 @@ void RFUart::cycle_trampoline(void *arg)
 
 int RFUart::task_spawn(int argc, char *argv[])
 {
-	_task_id = px4_task_spawn_cmd("rfuart", SCHED_DEFAULT, SCHED_PRIORITY_ACTUATOR_OUTPUTS, 1800, (px4_main_t)&run_trampoline, nullptr);
+	_task_id = px4_task_spawn_cmd("rfuart", SCHED_DEFAULT, SCHED_PRIORITY_ACTUATOR_OUTPUTS, 1800,
+				      (px4_main_t)&run_trampoline, nullptr);
 
-	PX4_INFO("task spawn %d \n",_task_id);
+	PX4_INFO("task spawn %d \n", _task_id);
 
 	if (_task_id < 0) {
 		_task_id = -1;
diff --git a/src/drivers/coolfly/bb/bb.c b/src/drivers/coolfly/bb/bb.c
index 0863d219feb64c0c244d76c889e5775e9cb4a2b5..058da2f0a8e48e7c35900c7ca84bebc76e9ad658 100644
--- a/src/drivers/coolfly/bb/bb.c
+++ b/src/drivers/coolfly/bb/bb.c
@@ -53,51 +53,51 @@
 #include <drivers/drv_hrt.h>
 #include <px4_module.h>
 
-typedef struct
-{
-    uint8_t         magic_header[2];
-    uint16_t        msg_id;
-    uint8_t         packet_num;
-    uint8_t         packet_cur;
-    uint16_t        msg_len;
-    uint16_t        msg_chksum;
-    uint16_t        snr_vlaue[2];           //0,1 3,2
-    uint16_t        u16_afterErr;           //5,4  masoic
-    uint8_t         u8_optCh;               //6 current optional channel
-    uint8_t         u8_mcs;                 //7
-    int16_t         sweep_energy[21*8];     //Max channel: 21
-    uint16_t        ldpc_error;             //9,8 error after Harq
-    uint8_t         agc_value[4];           //13 12 11 10
-    uint8_t         harq_count;             //14
-    uint8_t         modulation_mode;        //15
-    uint8_t         e_bandwidth;            //16
-    uint8_t         code_rate;              //17
-    uint8_t         osd_enable;             //18
-    uint8_t         IT_channel;             //19
-    uint8_t         head;                   //20
-    uint8_t         tail;                   //21
-    uint8_t         in_debug;               //22
-    uint8_t         lock_status;            //23
-    uint16_t        video_width[2];         //27,26 25,24
-    uint16_t        video_height[2];        //31,30 29,28
-    uint8_t         frameRate[2];           //33,32
-    uint8_t         encoder_bitrate[2];     //35,34
-    uint8_t         rc_modulation_mode;     //36
-    uint8_t         rc_code_rate;           //37
-    uint8_t         encoder_status;         //38
-    uint8_t         errcnt1;                //39
-    uint8_t         errcnt2;                //40
-    uint8_t         u8_rclock;              //41
-    uint8_t         u8_nrlock;              //42
-    uint8_t         sky_agc[4];             //43,44,45,46
-    uint8_t         reserved0;              //47
-    uint16_t        dist_zero;              //49,48
-    uint16_t        dist_value;             //50,51
-    uint16_t        sky_snr;                //52~53
-    uint8_t         reserved[2];            //54~55
-    uint32_t        sdram_buf_size[2];      //56~63
-    uint8_t         find_beside_dev_finish;     //64
-    uint8_t         find_beside_dev_num;    //65, sky start, search how many the same device type beside(default function is off , need app open)
+typedef struct {
+	uint8_t         magic_header[2];
+	uint16_t        msg_id;
+	uint8_t         packet_num;
+	uint8_t         packet_cur;
+	uint16_t        msg_len;
+	uint16_t        msg_chksum;
+	uint16_t        snr_vlaue[2];           //0,1 3,2
+	uint16_t        u16_afterErr;           //5,4  masoic
+	uint8_t         u8_optCh;               //6 current optional channel
+	uint8_t         u8_mcs;                 //7
+	int16_t         sweep_energy[21 * 8];   //Max channel: 21
+	uint16_t        ldpc_error;             //9,8 error after Harq
+	uint8_t         agc_value[4];           //13 12 11 10
+	uint8_t         harq_count;             //14
+	uint8_t         modulation_mode;        //15
+	uint8_t         e_bandwidth;            //16
+	uint8_t         code_rate;              //17
+	uint8_t         osd_enable;             //18
+	uint8_t         IT_channel;             //19
+	uint8_t         head;                   //20
+	uint8_t         tail;                   //21
+	uint8_t         in_debug;               //22
+	uint8_t         lock_status;            //23
+	uint16_t        video_width[2];         //27,26 25,24
+	uint16_t        video_height[2];        //31,30 29,28
+	uint8_t         frameRate[2];           //33,32
+	uint8_t         encoder_bitrate[2];     //35,34
+	uint8_t         rc_modulation_mode;     //36
+	uint8_t         rc_code_rate;           //37
+	uint8_t         encoder_status;         //38
+	uint8_t         errcnt1;                //39
+	uint8_t         errcnt2;                //40
+	uint8_t         u8_rclock;              //41
+	uint8_t         u8_nrlock;              //42
+	uint8_t         sky_agc[4];             //43,44,45,46
+	uint8_t         reserved0;              //47
+	uint16_t        dist_zero;              //49,48
+	uint16_t        dist_value;             //50,51
+	uint16_t        sky_snr;                //52~53
+	uint8_t         reserved[2];            //54~55
+	uint32_t        sdram_buf_size[2];      //56~63
+	uint8_t         find_beside_dev_finish;     //64
+	uint8_t
+	find_beside_dev_num;    //65, sky start, search how many the same device type beside(default function is off , need app open)
 } BB_STRU_WIRELESS_INFO_DISPLAY;
 
 HAL_RET_T HAL_BB_GetInfo(BB_STRU_WIRELESS_INFO_DISPLAY **ppst_bbInfoAddr);
@@ -120,109 +120,108 @@ typedef uint32_t HAL_RET_T;
 
 HAL_RET_T HAL_BB_GetInfo(BB_STRU_WIRELESS_INFO_DISPLAY **ppst_bbInfoAddr)
 {
-    if (NULL != ppst_bbInfoAddr && NULL != *ppst_bbInfoAddr)
-    {
-        *ppst_bbInfoAddr = (BB_STRU_WIRELESS_INFO_DISPLAY *)(SRAM_BB_STATUS_SHARE_MEMORY_ST_ADDR);     
-    }
-
-    if (((*ppst_bbInfoAddr)->head != 0x00) || ((*ppst_bbInfoAddr)->tail != 0xFF))
-    {
-        return HAL_BUSY;
-    }
-    else
-    {
-        return HAL_OK;
-    }
+	if (NULL != ppst_bbInfoAddr && NULL != *ppst_bbInfoAddr) {
+		*ppst_bbInfoAddr = (BB_STRU_WIRELESS_INFO_DISPLAY *)(SRAM_BB_STATUS_SHARE_MEMORY_ST_ADDR);
+	}
+
+	if (((*ppst_bbInfoAddr)->head != 0x00) || ((*ppst_bbInfoAddr)->tail != 0xFF)) {
+		return HAL_BUSY;
+
+	} else {
+		return HAL_OK;
+	}
 }
 
 
 static char *modulationModeName(uint8_t mode)
 {
-    switch (mode)
-    {
-    case 0x0:
-        return "BPSK";
-    case 0x1:
-        return "QPSK";
-    case 0x2:
-        return "QAM16";
-    case 0x3:
-        return "QAM64";
-    default:
-        break;
-    }
-    return "";
+	switch (mode) {
+	case 0x0:
+		return "BPSK";
+
+	case 0x1:
+		return "QPSK";
+
+	case 0x2:
+		return "QAM16";
+
+	case 0x3:
+		return "QAM64";
+
+	default:
+		break;
+	}
+
+	return "";
 }
 
 static void bb_print(BB_STRU_WIRELESS_INFO_DISPLAY *pst_bbInfoAddr, int fd)
 {
-    BB_STRU_WIRELESS_INFO_DISPLAY *info = (BB_STRU_WIRELESS_INFO_DISPLAY *)(SRAM_BB_STATUS_SHARE_MEMORY_ST_ADDR);
-
-    // -信噪比　,滤波打印
-    infoDisplay.snr_vlaue[0] = (infoDisplay.snr_vlaue[0] + info->snr_vlaue[0]) >>1;
-    infoDisplay.snr_vlaue[1] = (infoDisplay.snr_vlaue[1] + info->snr_vlaue[1]) >>1;
-
-
-    // 接受信号的能量，滤波打印
-    infoDisplay.agc_value[0] = (infoDisplay.agc_value[0] + info->agc_value[0]) >>1;
-    infoDisplay.agc_value[1] = (infoDisplay.agc_value[1] + info->agc_value[1]) >>1;
-    infoDisplay.agc_value[2] = (infoDisplay.agc_value[2] + info->agc_value[2]) >>1;
-    infoDisplay.agc_value[3] = (infoDisplay.agc_value[3] + info->agc_value[3]) >>1; 
-
-    // -调制模式　BPSK QPSK 16QAM 64QAM　，直接打印
-    infoDisplay.modulation_mode = info->modulation_mode;
-
-    // 图传信道　　直接打印
-    infoDisplay.IT_channel = info->IT_channel;
-
-    //  锁定状态　　判断打印
-    infoDisplay.lock_status = info->lock_status;
-
-    // 视频分辨率　判断打印
-    infoDisplay.video_width[0] = info->video_width[0];
-    infoDisplay.video_width[1] = info->video_width[1];
-    infoDisplay.video_height[0] = info->video_height[0];
-    infoDisplay.video_height[1] = info->video_height[1];
-    
-    // 视频帧率   滤波打印
-    infoDisplay.frameRate[0] = (infoDisplay.frameRate[0] + info->frameRate[0]) >>1;
-    infoDisplay.frameRate[1] = (infoDisplay.frameRate[1] + info->frameRate[1]) >>1;
-
-    // 视频压缩码率　　滤波打印
-    infoDisplay.encoder_bitrate[0] = (infoDisplay.encoder_bitrate[0] + info->encoder_bitrate[0]) >>1;
-    infoDisplay.encoder_bitrate[1] = (infoDisplay.encoder_bitrate[1] + info->encoder_bitrate[1]) >>1;
-
-    //  rc调制模式   直接打印
-    infoDisplay.rc_modulation_mode = info->rc_modulation_mode;
-
-    // rc码率   滤波打印
-    infoDisplay.rc_code_rate = (infoDisplay.rc_code_rate + info->rc_code_rate) >>1;
-
-    // 遥控锁定  判断打印
-    if (info->u8_rclock)
-    {
-        lockCnt++;
-    } 
-    else
-    {
-        unlockCnt++;
-    }
-    
-    //  天空端信噪比　　滤波打印
-    infoDisplay.sky_snr = (infoDisplay.sky_snr + info->sky_snr) >> 1;
-
-    if (cycleCnt ++ <= 50)
-    {
-        return;
-    }
-
-    cycleCnt = 0;
+	BB_STRU_WIRELESS_INFO_DISPLAY *info = (BB_STRU_WIRELESS_INFO_DISPLAY *)(SRAM_BB_STATUS_SHARE_MEMORY_ST_ADDR);
+
+	// -信噪比　,滤波打印
+	infoDisplay.snr_vlaue[0] = (infoDisplay.snr_vlaue[0] + info->snr_vlaue[0]) >> 1;
+	infoDisplay.snr_vlaue[1] = (infoDisplay.snr_vlaue[1] + info->snr_vlaue[1]) >> 1;
+
+
+	// 接受信号的能量，滤波打印
+	infoDisplay.agc_value[0] = (infoDisplay.agc_value[0] + info->agc_value[0]) >> 1;
+	infoDisplay.agc_value[1] = (infoDisplay.agc_value[1] + info->agc_value[1]) >> 1;
+	infoDisplay.agc_value[2] = (infoDisplay.agc_value[2] + info->agc_value[2]) >> 1;
+	infoDisplay.agc_value[3] = (infoDisplay.agc_value[3] + info->agc_value[3]) >> 1;
+
+	// -调制模式　BPSK QPSK 16QAM 64QAM　，直接打印
+	infoDisplay.modulation_mode = info->modulation_mode;
+
+	// 图传信道　　直接打印
+	infoDisplay.IT_channel = info->IT_channel;
+
+	//  锁定状态　　判断打印
+	infoDisplay.lock_status = info->lock_status;
+
+	// 视频分辨率　判断打印
+	infoDisplay.video_width[0] = info->video_width[0];
+	infoDisplay.video_width[1] = info->video_width[1];
+	infoDisplay.video_height[0] = info->video_height[0];
+	infoDisplay.video_height[1] = info->video_height[1];
+
+	// 视频帧率   滤波打印
+	infoDisplay.frameRate[0] = (infoDisplay.frameRate[0] + info->frameRate[0]) >> 1;
+	infoDisplay.frameRate[1] = (infoDisplay.frameRate[1] + info->frameRate[1]) >> 1;
+
+	// 视频压缩码率　　滤波打印
+	infoDisplay.encoder_bitrate[0] = (infoDisplay.encoder_bitrate[0] + info->encoder_bitrate[0]) >> 1;
+	infoDisplay.encoder_bitrate[1] = (infoDisplay.encoder_bitrate[1] + info->encoder_bitrate[1]) >> 1;
+
+	//  rc调制模式   直接打印
+	infoDisplay.rc_modulation_mode = info->rc_modulation_mode;
+
+	// rc码率   滤波打印
+	infoDisplay.rc_code_rate = (infoDisplay.rc_code_rate + info->rc_code_rate) >> 1;
+
+	// 遥控锁定  判断打印
+	if (info->u8_rclock) {
+		lockCnt++;
+
+	} else {
+		unlockCnt++;
+	}
+
+	//  天空端信噪比　　滤波打印
+	infoDisplay.sky_snr = (infoDisplay.sky_snr + info->sky_snr) >> 1;
+
+	if (cycleCnt ++ <= 50) {
+		return;
+	}
+
+	cycleCnt = 0;
 
 	if (fd == 1) {
         // ref:http://www.termsys.demon.co.uk/vtansi.htm
 		dprintf(fd, "\033[2J\033[H");
 	}
 
+<<<<<<< 42466c03ef493b4fbea7ea998b881a11b1fd5539:src/drivers/coolfly/bb/bb.c
     printf("\r\n------------------- BB INFO STATUS --------------------\r\n\r\n");
 
     printf("    %-20s    0x%x\r\n", "snr_vlaue[0]",   infoDisplay.snr_vlaue[0]);
@@ -249,6 +248,34 @@ static void bb_print(BB_STRU_WIRELESS_INFO_DISPLAY *pst_bbInfoAddr, int fd)
     printf("\r\n\r\n");
 
     fflush(stdout);
+=======
+	printf("\r\n------------------- BB INFO STATUS --------------------\r\n\r\n");
+
+	printf("    %-20s    0x%x\r\n", "snr_vlaue[0]",   infoDisplay.snr_vlaue[0]);
+	printf("    %-20s    0x%x\r\n", "snr_vlaue[1]",   infoDisplay.snr_vlaue[1]);
+	printf("    %-20s    0x%x\r\n", "agc_value[0]",   infoDisplay.agc_value[0]);
+	printf("    %-20s    0x%x\r\n", "agc_value[1]",   infoDisplay.agc_value[1]);
+	printf("    %-20s    0x%x\r\n", "agc_value[2]",   infoDisplay.agc_value[2]);
+	printf("    %-20s    0x%x\r\n", "agc_value[3]",   infoDisplay.agc_value[3]);
+	printf("    %-20s    %s\r\n", "modulation_mode", modulationModeName(infoDisplay.modulation_mode));
+	printf("    %-20s    %d\r\n", "IT_channel",     infoDisplay.IT_channel);
+	printf("    %-20s    %d\r\n", "lock_status",    infoDisplay.lock_status);
+	printf("    %-20s    %d\r\n", "video_width[0]", infoDisplay.video_width[0]);
+	printf("    %-20s    %d\r\n", "video_width[1]", infoDisplay.video_width[1]);
+	printf("    %-20s    %d\r\n", "video_height[0]", infoDisplay.video_height[0]);
+	printf("    %-20s    %d\r\n", "video_height[1]", infoDisplay.video_height[1]);
+	printf("    %-20s    %d\r\n", "frameRate[0]",   infoDisplay.frameRate[0]);
+	printf("    %-20s    %d\r\n", "frameRate[1]",   infoDisplay.frameRate[1]);
+	printf("    %-20s    %d\r\n", "encoder_bitrate[0]",  infoDisplay.encoder_bitrate[0]);
+	printf("    %-20s    %d\r\n", "encoder_bitrate[1]",  infoDisplay.encoder_bitrate[1]);
+	printf("    %-20s    %d\r\n", "rc_modulation_mode",  infoDisplay.rc_modulation_mode);
+	printf("    %-20s    %d/%d\r\n", "u8_rclock",      lockCnt, unlockCnt);
+	printf("    %-20s    %d\r\n", "sky_snr",        infoDisplay.sky_snr);
+
+	printf("\r\n\r\n");
+
+	fflush(stdout);
+>>>>>>> update the format:src/systemcmds/bb/bb.c
 }
 
 /**
@@ -267,7 +294,7 @@ __EXPORT int bb_main(int argc, char *argv[]);
 int
 bb_main(int argc, char *argv[])
 {
-    memset(&infoDisplay, 0, sizeof(BB_STRU_WIRELESS_INFO_DISPLAY));
+	memset(&infoDisplay, 0, sizeof(BB_STRU_WIRELESS_INFO_DISPLAY));
 
 	dprintf(1, "\033[2J\n");
 
@@ -277,12 +304,11 @@ bb_main(int argc, char *argv[])
 
 		HAL_RET_T hal_ret;
 
-    	BB_STRU_WIRELESS_INFO_DISPLAY *pst_bbInfoAddr;
+		BB_STRU_WIRELESS_INFO_DISPLAY *pst_bbInfoAddr;
 
-    	hal_ret = HAL_BB_GetInfo(&pst_bbInfoAddr);
+		hal_ret = HAL_BB_GetInfo(&pst_bbInfoAddr);
 
-		if(hal_ret != HAL_OK)
-		{
+		if (hal_ret != HAL_OK) {
 			// // PX4_INFO("hal_ret = %d \r\n", hal_ret);
 			// continue;
 		}
diff --git a/src/drivers/coolfly/cpu2/cpu2.cpp b/src/drivers/coolfly/cpu2/cpu2.cpp
index bac3382e6084def5296e779df3e717b5d26dbc79..10df079465ad124286fbe73d0ca538aba74f73e2 100644
--- a/src/drivers/coolfly/cpu2/cpu2.cpp
+++ b/src/drivers/coolfly/cpu2/cpu2.cpp
@@ -69,7 +69,7 @@ static struct work_s h264_work = {};
 
 static int h264_fd = 0;
 
-static struct h264_input_format_s att = {0}; 
+static struct h264_input_format_s att = {0};
 
 
 class CPU2 : public device::CDev, public ModuleBase<CPU2>
@@ -99,7 +99,7 @@ private:
 };
 
 
-// _EXT_ITCM void CPU2::clog() 
+// _EXT_ITCM void CPU2::clog()
 // {
 // 	if (shouldLog == false) {
 // 		return;
@@ -121,7 +121,8 @@ void CPU2::cycle_trampoline(void *arg)
 
 		if (dev->init() != PX4_OK) {
 			return;
-		} 
+		}
+
 		_object = dev;
 	}
 
@@ -130,73 +131,71 @@ void CPU2::cycle_trampoline(void *arg)
 }
 
 
-void CPU2::intercore_event_msg_cycle_trampoline(void *arg) 
+void CPU2::intercore_event_msg_cycle_trampoline(void *arg)
 {
 	uint8_t i = 0;
 
-    volatile AR_INTERCORE_EVENT* msgPtr = (AR_INTERCORE_EVENT*)SRAM_INTERCORE_EVENT_CPU2T0_ST_STARTADDR;
+	volatile AR_INTERCORE_EVENT *msgPtr = (AR_INTERCORE_EVENT *)SRAM_INTERCORE_EVENT_CPU2T0_ST_STARTADDR;
 
-    for(i = 0; i < SRAM_INTERCORE_EVENT_MAX_COUNT; i++)
-    {
-        if (msgPtr[i].isUsed == 1) {
-			switch (msgPtr[i].type)
-			{
+	for (i = 0; i < SRAM_INTERCORE_EVENT_MAX_COUNT; i++) {
+		if (msgPtr[i].isUsed == 1) {
+			switch (msgPtr[i].type) {
 			case SYS_EVENT_ID_CPU2_LOG:
-				if(needlogging == 1)
-				{
+				if (needlogging == 1) {
 					PX4_INFO("%s", msgPtr[i].data);
 				}
+
 				msgPtr[i].isUsed = 2;
 				break;
+
 			default:
 				break;
 			}
-        }        
-    }
+		}
+	}
+
 	work_queue(LPWORK, &_work, (worker_t)&CPU2::intercore_event_msg_cycle_trampoline, nullptr, 5);
 }
 
 
-_EXT_ITCM static void initSram() 
-{	
-    memset((void *)SRAM_MAVLINK_RC_MSG_ST_ADDR, 0, SRAM_MAVLINK_RC_MSG_SIZE);
+_EXT_ITCM static void initSram()
+{
+	memset((void *)SRAM_MAVLINK_RC_MSG_ST_ADDR, 0, SRAM_MAVLINK_RC_MSG_SIZE);
 
 	STRU_SramBuffer *sramBuffer;
 
-	sramBuffer = (STRU_SramBuffer*)SRAM_MAVLINK_RC_MSG_ST_ADDR;
+	sramBuffer = (STRU_SramBuffer *)SRAM_MAVLINK_RC_MSG_ST_ADDR;
 	sramBuffer->header.buf_wr_pos = (uint32_t)sramBuffer->buf;
 	sramBuffer->header.buf_rd_pos = (uint32_t)sramBuffer->buf;
 
-	sramBuffer = (STRU_SramBuffer*)SRAM_SESSION1_TO_UART_DATA_ST_ADDR;
-    sramBuffer->header.buf_wr_pos = (uint32_t)sramBuffer->buf;
-    sramBuffer->header.buf_rd_pos = (uint32_t)sramBuffer->buf;
+	sramBuffer = (STRU_SramBuffer *)SRAM_SESSION1_TO_UART_DATA_ST_ADDR;
+	sramBuffer->header.buf_wr_pos = (uint32_t)sramBuffer->buf;
+	sramBuffer->header.buf_rd_pos = (uint32_t)sramBuffer->buf;
 
-    sramBuffer = (STRU_SramBuffer*)SRAM_UART_TO_SESSION1_DATA_ST_ADDR;
-    sramBuffer->header.buf_wr_pos = (uint32_t)sramBuffer->buf;
-    sramBuffer->header.buf_rd_pos = (uint32_t)sramBuffer->buf;
+	sramBuffer = (STRU_SramBuffer *)SRAM_UART_TO_SESSION1_DATA_ST_ADDR;
+	sramBuffer->header.buf_wr_pos = (uint32_t)sramBuffer->buf;
+	sramBuffer->header.buf_rd_pos = (uint32_t)sramBuffer->buf;
 }
 
 
 
 _EXT_ITCM void CPU2::h264_cycle(void *arg)
 {
-    if (h264_fd == 0)
-    {
-        h264_fd = orb_subscribe(ORB_ID(h264_input_format));
-    }
+	if (h264_fd == 0) {
+		h264_fd = orb_subscribe(ORB_ID(h264_input_format));
+	}
 
-    bool updated = false;
+	bool updated = false;
 
-    if (orb_check(h264_fd, &updated) != PX4_OK) { return; }
+	if (orb_check(h264_fd, &updated) != PX4_OK) { return; }
 
-    if (updated)
-    {
-        orb_copy(ORB_ID(h264_input_format), h264_fd, &att);
+	if (updated) {
+		orb_copy(ORB_ID(h264_input_format), h264_fd, &att);
 
 		AR_INTERCORE_EVENT msg;
-		uint8_t length = 13;		
+		uint8_t length = 13;
 		msg.data[0] = att.index;
-		msg.data[1] = (att.width >> 8) & 0xff;	
+		msg.data[1] = (att.width >> 8) & 0xff;
 		msg.data[2] = att.width & 0xff;
 		msg.data[3] = (att.hight >> 8) & 0xff;
 		msg.data[4] = att.hight & 0xff;
@@ -204,63 +203,59 @@ _EXT_ITCM void CPU2::h264_cycle(void *arg)
 		msg.data[6] = att.vic;
 		msg.data[7] = att.e_h264InputSrc;
 
-    	msg.length = length;
-    	msg.type = SYS_EVENT_ID_H264_INPUT_FORMAT_CHANGE;
+		msg.length = length;
+		msg.type = SYS_EVENT_ID_H264_INPUT_FORMAT_CHANGE;
 
 		bool needIndicator = (att.width != 0 && att.hight != 0 && att.framerate != 0);
 		px4_arch_gpiowrite(GPIO_HDMI_VIDEO_INDICATOR, !needIndicator);
 
 		PX4_INFO("-----------------------------------------");
-        PX4_INFO("index = %d ", att.index);
-        PX4_INFO("width = %d ", att.width);
-        PX4_INFO("hight = %d ", att.hight);
-        PX4_INFO("framerate = %d", att.framerate);
-        PX4_INFO("vic = %d", att.vic);
-        PX4_INFO("e_h264InputSrc = %d", att.e_h264InputSrc);
+		PX4_INFO("index = %d ", att.index);
+		PX4_INFO("width = %d ", att.width);
+		PX4_INFO("hight = %d ", att.hight);
+		PX4_INFO("framerate = %d", att.framerate);
+		PX4_INFO("vic = %d", att.vic);
+		PX4_INFO("e_h264InputSrc = %d", att.e_h264InputSrc);
 		PX4_INFO("-----------------------------------------\n");
 
 		arsys_event_cpu0t2_append(&msg);
-    }	
+	}
 
 	(void)work_queue(LPWORK, &h264_work, (worker_t)&CPU2::h264_cycle, nullptr, USEC2TICK(1000 * 1000));
 }
 
-CPU2::CPU2(): CDev("cpu2", "/dev/cpu2") 
+CPU2::CPU2(): CDev("cpu2", "/dev/cpu2")
 {}
- 
+
 
 _EXT_ITCM uint8_t arsys_event_cpu0t2_append(AR_INTERCORE_EVENT *message)
-{   
+{
 	static uint8_t seq = 0;
 
 	uint8_t i = 0;
-    volatile AR_INTERCORE_EVENT* msgPtr = (AR_INTERCORE_EVENT*)SRAM_INTERCORE_EVENT_CPU0T2_ST_STARTADDR;
-
-    for(i = 0; i < SRAM_INTERCORE_EVENT_MAX_COUNT; i++)
-    {
-        if (msgPtr[i].isUsed == 0) 
-        {
-            msgPtr[i].length = message->length;
-            msgPtr[i].type = message->type;
-            memcpy((void *)msgPtr[i].data, message->data, message->length);
-            msgPtr[i].isUsed = 1;
-            msgPtr[i].seq = seq++;
-
-            break;
-        }        
-    }
-   
-    if (i == SRAM_INTERCORE_EVENT_MAX_COUNT) 
-    {
-        for(i = 0; i < SRAM_INTERCORE_EVENT_MAX_COUNT; i++)
-        {
-            msgPtr[i].isUsed = 0;
-        }
-        
-        arsys_event_cpu0t2_append(message);
-    }
-    
-    return 0;
+	volatile AR_INTERCORE_EVENT *msgPtr = (AR_INTERCORE_EVENT *)SRAM_INTERCORE_EVENT_CPU0T2_ST_STARTADDR;
+
+	for (i = 0; i < SRAM_INTERCORE_EVENT_MAX_COUNT; i++) {
+		if (msgPtr[i].isUsed == 0) {
+			msgPtr[i].length = message->length;
+			msgPtr[i].type = message->type;
+			memcpy((void *)msgPtr[i].data, message->data, message->length);
+			msgPtr[i].isUsed = 1;
+			msgPtr[i].seq = seq++;
+
+			break;
+		}
+	}
+
+	if (i == SRAM_INTERCORE_EVENT_MAX_COUNT) {
+		for (i = 0; i < SRAM_INTERCORE_EVENT_MAX_COUNT; i++) {
+			msgPtr[i].isUsed = 0;
+		}
+
+		arsys_event_cpu0t2_append(message);
+	}
+
+	return 0;
 }
 
 
@@ -269,8 +264,8 @@ CPU2::~CPU2() {}
 int CPU2::init()
 {
 	int ret;
-	if ((ret = CDev::init()) != PX4_OK) 
-	{
+
+	if ((ret = CDev::init()) != PX4_OK) {
 		PX4_ERR("CPU2::init fail");
 		return ret;
 	}
@@ -281,58 +276,53 @@ int CPU2::init()
 
 	return PX4_OK;
 }
- 
-int tolower(int c)  
-{  
-    if (c >= 'A' && c <= 'Z')  
-    {  
-        return c + 'a' - 'A';  
-    }  
-    else  
-    {  
-        return c;  
-    }  
+
+int tolower(int c)
+{
+	if (c >= 'A' && c <= 'Z') {
+		return c + 'a' - 'A';
+
+	} else {
+		return c;
+	}
 }
 
-int htoi(char s[])  
-{  
-    int i;  
-    int n = 0; 
-
-    if (s[0] == '0' && (s[1]=='x' || s[1]=='X'))  
-    {  
-        i = 2;  
-    }  
-    else  
-    {  
-        i = 0;  
-    }
-
-
-    for (; (s[i] >= '0' && s[i] <= '9') || (s[i] >= 'a' && s[i] <= 'z') || (s[i] >='A' && s[i] <= 'Z');++i)  
-    {  	
-        if (tolower(s[i]) > '9')  
-        {  
-            n = 16 * n + (10 + tolower(s[i]) - 'a');  
-        }  
-        else  
-        {  
-            n = 16 * n + (tolower(s[i]) - '0');  
-        }  
-    }  
-    return n;  
-}  
+int htoi(char s[])
+{
+	int i;
+	int n = 0;
+
+	if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) {
+		i = 2;
+
+	} else {
+		i = 0;
+	}
+
+
+	for (; (s[i] >= '0' && s[i] <= '9') || (s[i] >= 'a' && s[i] <= 'z') || (s[i] >= 'A' && s[i] <= 'Z'); ++i) {
+		if (tolower(s[i]) > '9') {
+			n = 16 * n + (10 + tolower(s[i]) - 'a');
+
+		} else {
+			n = 16 * n + (tolower(s[i]) - '0');
+		}
+	}
+
+	return n;
+}
 
 
 int CPU2::task_spawn(int argc, char *argv[])
 {
 	int ret;
+
 	if ((ret = work_queue(LPWORK, &_work, (worker_t)&CPU2::cycle_trampoline, nullptr, 0)) < 0) {
 		return ret;
 	}
 
 	_task_id = task_id_is_work_queue;
-		
+
 	return PX4_OK;
 }
 
@@ -356,17 +346,16 @@ int CPU2::print_usage(const char *reason)
 }
 
 
-int CPU2::custom_command(int argc, char *argv[]) 
+int CPU2::custom_command(int argc, char *argv[])
 {
 	const char *verb = argv[0];
+
 	if (strcmp(verb, "setid") == 0) {
-		if (argc < 8) 
-		{
+		if (argc < 8) {
 			print_usage();
-		}
-		else 
-		{
-			uint8_t buffer[7] = {0};			
+
+		} else {
+			uint8_t buffer[7] = {0};
 
 			buffer[0] = htoi(argv[1]);
 			buffer[1] = htoi(argv[2]);
@@ -377,17 +366,14 @@ int CPU2::custom_command(int argc, char *argv[])
 			buffer[6] = htoi(argv[7]);
 			px4_flash_updateid(buffer, sizeof(buffer), 2);
 		}
-	} 
-	else if (strcmp(verb, "log") == 0) 
-	{
+
+	} else if (strcmp(verb, "log") == 0) {
 		needlogging = 1;
-	} 
-	else if (strcmp(verb, "blind") == 0) 
-	{
+
+	} else if (strcmp(verb, "blind") == 0) {
 		needlogging = 0;
-	}
-	else 
-	{
+
+	} else {
 		print_usage();
 	}
 
diff --git a/src/drivers/coolfly/cpu2/cpu2.h b/src/drivers/coolfly/cpu2/cpu2.h
index 6d1d9eba5276201ab1b869a52be7e196bdff80fc..330261f01a0869409b4e21409768c2439ae7ac32 100644
--- a/src/drivers/coolfly/cpu2/cpu2.h
+++ b/src/drivers/coolfly/cpu2/cpu2.h
@@ -14,13 +14,12 @@
 #define SRAM_INTERCORE_MSG_LENGTH           64
 #define SRAM_INTERCORE_EVENT_MAX_COUNT            (SRAM_INTERCORE_EVENT_CPU2T0_ST_SIZE / sizeof(AR_INTERCORE_EVENT))
 
-typedef struct
-{
-    uint16_t             length;
-    uint16_t             seq;
-    char                data[SRAM_INTERCORE_MSG_LENGTH];
-    uint32_t            type;
-    uint32_t             isUsed;
+typedef struct {
+	uint16_t             length;
+	uint16_t             seq;
+	char                data[SRAM_INTERCORE_MSG_LENGTH];
+	uint32_t            type;
+	uint32_t             isUsed;
 } AR_INTERCORE_EVENT;
 
 #define SYS_EVENT_ID_CPU2_LOG                        (SYS_EVENT_LEVEL_MIDIUM_MASK   | 0x001F)
diff --git a/src/drivers/drv_intercore.h b/src/drivers/drv_intercore.h
index 19917d95f5e68472f7118ec27ad222098b301465..3f21ce24275be013ee0091ba0dd815c808166675 100644
--- a/src/drivers/drv_intercore.h
+++ b/src/drivers/drv_intercore.h
@@ -55,25 +55,23 @@ __BEGIN_DECLS
 #define SYS_EVENT_ID_USB_SWITCH_HOST_DEVICE           (SYS_EVENT_LEVEL_HIGH_MASK   | 0x0007)
 
 
-typedef enum
-{
-    ENCODER_INPUT_SRC_HDMI_0 = 1,
-    ENCODER_INPUT_SRC_HDMI_1,
-    ENCODER_INPUT_SRC_DVP_0,
-    ENCODER_INPUT_SRC_DVP_1,
-    ENCODER_INPUT_SRC_MIPI,
+typedef enum {
+	ENCODER_INPUT_SRC_HDMI_0 = 1,
+	ENCODER_INPUT_SRC_HDMI_1,
+	ENCODER_INPUT_SRC_DVP_0,
+	ENCODER_INPUT_SRC_DVP_1,
+	ENCODER_INPUT_SRC_MIPI,
 } ENUM_ENCODER_INPUT_SRC;
 
 
-typedef struct _SysEvent_H264InputFormatChangeParameter
-{
-    uint8_t  index;
-    uint16_t width;
-    uint16_t hight;
-    uint8_t  framerate;
-    uint8_t  vic;
-    ENUM_ENCODER_INPUT_SRC  e_h264InputSrc;
-    uint8_t  reserve[SYS_EVENT_HANDLER_PARAMETER_LENGTH - 9];
+typedef struct _SysEvent_H264InputFormatChangeParameter {
+	uint8_t  index;
+	uint16_t width;
+	uint16_t hight;
+	uint8_t  framerate;
+	uint8_t  vic;
+	ENUM_ENCODER_INPUT_SRC  e_h264InputSrc;
+	uint8_t  reserve[SYS_EVENT_HANDLER_PARAMETER_LENGTH - 9];
 } STRU_SysEvent_H264InputFormatChangeParameter;
 
 
diff --git a/src/drivers/imu/bmi055/bmi055.hpp b/src/drivers/imu/bmi055/bmi055.hpp
index 971e079a9a85b09d5d0f76b3651f90fb0af5649e..bb5b16c9fc38bb98b146d3e9174ee625eb60dc49 100644
--- a/src/drivers/imu/bmi055/bmi055.hpp
+++ b/src/drivers/imu/bmi055/bmi055.hpp
@@ -300,8 +300,9 @@ protected:
 
 public:
 
-	_EXT_ITCM BMI055(const char *name, const char *devname, int bus, uint32_t device, enum spi_mode_e mode, uint32_t frequency,
-	       enum Rotation rotation);
+	_EXT_ITCM BMI055(const char *name, const char *devname, int bus, uint32_t device, enum spi_mode_e mode,
+			 uint32_t frequency,
+			 enum Rotation rotation);
 	_EXT_ITCM virtual ~BMI055();
 
 
diff --git a/src/drivers/imu/mpu6000/mpu6000.cpp b/src/drivers/imu/mpu6000/mpu6000.cpp
index 0a1cb275e1b569f4c4db4fcf715c5291502c13cb..89d043465a35b6ce29ce985da2f0f3f2b766c2f9 100644
--- a/src/drivers/imu/mpu6000/mpu6000.cpp
+++ b/src/drivers/imu/mpu6000/mpu6000.cpp
@@ -132,7 +132,7 @@ class MPU6000 : public device::CDev
 {
 public:
 	_EXT_ITCM MPU6000(device::Device *interface, const char *path_accel, const char *path_gyro, enum Rotation rotation,
-		int device_type);
+			  int device_type);
 	_EXT_ITCM virtual ~MPU6000();
 
 	_EXT_ITCM virtual int		init();
diff --git a/src/drivers/it66021/edid.cpp b/src/drivers/it66021/edid.cpp
index a99f1879a5fc7152aa21395fa6de71dfad283293..42bdf7fcd306997326e096037c6ffecff04d35cf 100644
--- a/src/drivers/it66021/edid.cpp
+++ b/src/drivers/it66021/edid.cpp
@@ -36,9 +36,9 @@
 #include "px4_log.h"
 
 
-EDID::EDID(I2CARG arg) : I2C(arg.name, arg.devname, arg.bus, arg.address,  arg.frequency) 
+EDID::EDID(I2CARG arg) : I2C(arg.name, arg.devname, arg.bus, arg.address,  arg.frequency)
 {
-    PX4_INFO("EDID INIT \r\n");
+	PX4_INFO("EDID INIT \r\n");
 }
 
 EDID::~EDID()
@@ -53,8 +53,7 @@ int EDID::init()
 	int ret;
 	ret = I2C::init();
 
-	if (ret != OK)
-	{
+	if (ret != OK) {
 		PX4_INFO("ret != OK\r\n");
 		return ret;
 	}
@@ -92,10 +91,10 @@ int EDID::write(unsigned address, void *data, unsigned count)
 {
 	uint8_t buf[32];
 
-	if (sizeof(buf) < (count + 1))
-	{
+	if (sizeof(buf) < (count + 1)) {
 		return -EIO;
 	}
+
 	buf[0] = address;
 
 	memcpy(&buf[1], data, count);
diff --git a/src/drivers/it66021/edid.h b/src/drivers/it66021/edid.h
index a251bf15e6b8527d6e348ebdeb9923ed119e684b..bf592ad092bb6c87cbfd92a4dc2d3d8c9ccd16bd 100644
--- a/src/drivers/it66021/edid.h
+++ b/src/drivers/it66021/edid.h
@@ -41,13 +41,13 @@
 class EDID : public device::I2C
 {
 public:
-    EDID(I2CARG arg);
-    ~EDID();
+	EDID(I2CARG arg);
+	~EDID();
 
-    virtual int init();
-    virtual int probe();
+	virtual int init();
+	virtual int probe();
 
-    int read(unsigned address, void *data, unsigned count);
+	int read(unsigned address, void *data, unsigned count);
 	int write(unsigned address, void *data, unsigned count);
 };
 
diff --git a/src/drivers/it66021/it66021.cpp b/src/drivers/it66021/it66021.cpp
index ee116eb9a1be0221030ccb128388ae8aa23f079c..8c552a08af6f9c9624a7b339a8f741492efbb9e4 100644
--- a/src/drivers/it66021/it66021.cpp
+++ b/src/drivers/it66021/it66021.cpp
@@ -66,47 +66,43 @@
 #include "it66021_i2c.h"
 
 
-static STRU_HDMI_RX_OUTPUT_FORMAT s_st_hdmiRxSupportedOutputFormat[] =
-{
-    {720,  480,  60},
-    {1280, 720,  30},
-    {1280, 720,  25},
-    {1280, 720,  50},
-    {1280, 720,  60},
-    {1920, 1080, 25},
-    {1920, 1080, 30},
+static STRU_HDMI_RX_OUTPUT_FORMAT s_st_hdmiRxSupportedOutputFormat[] = {
+	{720,  480,  60},
+	{1280, 720,  30},
+	{1280, 720,  25},
+	{1280, 720,  50},
+	{1280, 720,  60},
+	{1920, 1080, 25},
+	{1920, 1080, 30},
 //    {1920, 1080, 50},
 //    {1920, 1080, 60},
 };
 
-static unsigned int s_u8Array_ARCastSupportedOutputFormat[][4] =
-{
-    { 720, 480,  50,  2},//4:3
-    { 720, 480,  60,  3},//16:9
-    { 720, 576,  50, 17},//4:3
-    { 720, 576,  60, 18},//16:9
-    {1280, 720,  60,  4},//16:9
-    {1280, 720,  50, 19},//16:9
-    {1920, 1080, 25, 33}, //16:9
-    {1920, 1080, 30, 34},//16:9
+static unsigned int s_u8Array_ARCastSupportedOutputFormat[][4] = {
+	{ 720, 480,  50,  2},//4:3
+	{ 720, 480,  60,  3},//16:9
+	{ 720, 576,  50, 17},//4:3
+	{ 720, 576,  60, 18},//16:9
+	{1280, 720,  60,  4},//16:9
+	{1280, 720,  50, 19},//16:9
+	{1920, 1080, 25, 33}, //16:9
+	{1920, 1080, 30, 34},//16:9
 };
 
 
 
 static uint32_t HDMI_RX_CheckVideoFormatSupportOrNot(uint16_t u16_width, uint16_t u16_hight, uint8_t u8_framerate)
 {
-	uint8_t count = sizeof(s_st_hdmiRxSupportedOutputFormat)/sizeof(s_st_hdmiRxSupportedOutputFormat[0]);
-	
-	for (uint8_t i = 0; i < count; i++)
-	{
+	uint8_t count = sizeof(s_st_hdmiRxSupportedOutputFormat) / sizeof(s_st_hdmiRxSupportedOutputFormat[0]);
+
+	for (uint8_t i = 0; i < count; i++) {
 		if ((u16_width == s_st_hdmiRxSupportedOutputFormat[i].u16_width) &&
-            (u16_hight == s_st_hdmiRxSupportedOutputFormat[i].u16_hight) &&
-            (u8_framerate == s_st_hdmiRxSupportedOutputFormat[i].u8_framerate))
-		{
+		    (u16_hight == s_st_hdmiRxSupportedOutputFormat[i].u16_hight) &&
+		    (u8_framerate == s_st_hdmiRxSupportedOutputFormat[i].u8_framerate)) {
 			return HAL_OK;
 		}
 	}
-	
+
 	return HAL_HDMI_RX_FALSE;
 }
 
@@ -116,7 +112,7 @@ static uint32_t HDMI_RX_CheckVideoFormatSupportOrNot(uint16_t u16_width, uint16_
 
 //FIX_ID_016 xxxxx Support Dual Pixel Mode for IT66023 Only
 #if defined(_IT66023_)
-    #pragma message ("defined ENABLE_IT66023")
+#pragma message ("defined ENABLE_IT66023")
 #endif
 //FIX_ID_016 xxxxx
 
@@ -149,9 +145,9 @@ static uint32_t HDMI_RX_CheckVideoFormatSupportOrNot(uint16_t u16_width, uint16_
 
 
 #ifndef IT6811B0
-    #define PPHDCPOpt2	TRUE	//2013-0509 MHL 1080p packet pixel mode HDCP
+#define PPHDCPOpt2	TRUE	//2013-0509 MHL 1080p packet pixel mode HDCP
 #else
-    #define PPHDCPOpt2	FALSE 	//only for it6811b0
+#define PPHDCPOpt2	FALSE 	//only for it6811b0
 #endif
 
 
@@ -274,7 +270,7 @@ static uint32_t HDMI_RX_CheckVideoFormatSupportOrNot(uint16_t u16_width, uint16_
 #define MaxEQIndex 3
 
 
-unsigned char IT6602EQTable[]={0xFF,0x9F,0x83};
+unsigned char IT6602EQTable[] = {0xFF, 0x9F, 0x83};
 
 //for EQ state machine handler
 //#define	MAXSYNCOFF 		5
@@ -305,7 +301,7 @@ static _CODE struct IT6602_REG_INI  IT6602_HDMI_INIT_TABLE[] = {
 	{REG_RX_010,	0xFF,	0x08},	//[3]1: Register reset
 	{REG_RX_00F,	0x03,	0x00},	//change bank 0
 
-	{REG_RX_034,	0xFF,	MHL_ADDR+0x01},	//I2C Slave Addresss for MHL block
+	{REG_RX_034,	0xFF,	MHL_ADDR + 0x01},	//I2C Slave Addresss for MHL block
 
 	{REG_RX_010,	0xFF,	0x17},	//[4]Auto Video Reset [2]Int Reset [1]Audio Reset [0]Video Reset
 
@@ -338,7 +334,7 @@ static _CODE struct IT6602_REG_INI  IT6602_HDMI_INIT_TABLE[] = {
 
 #ifdef Enable_IT6602_CEC
 	{REG_RX_00E,	0xFF,	0xFF},	//for enable CEC Clock
-	{REG_RX_086,	0xFF,	(CEC_ADDR|0x01)},	//CEC chip Slave Adr
+	{REG_RX_086,	0xFF,	(CEC_ADDR | 0x01)},	//CEC chip Slave Adr
 #endif
 
 	//	{0xFE,	0x80,	0x80},	//BUS10B for FPGA
@@ -357,11 +353,11 @@ static _CODE struct IT6602_REG_INI  IT6602_HDMI_INIT_TABLE[] = {
 	//20131129 move to top side->	{REG_RX_034,	0xFF,	MHL_ADDR+0x01},	//I2C Slave Addresss for MHL block
 	//FIX_ID_017 xxxxx Disable IPLockChk
 	//FIX_ID_001 xxxxx UseIPLock = 0 for avoid clk change
-	{REG_RX_035,	0x1E,	(0x10+(DeltaNum<<2))},	//[3:2] RCLKDeltaSel , [1] UseIPLock = 0
-	{REG_RX_04B,	0x1E,	(0x10+(DeltaNum<<2))},	//[3:2] RCLKDeltaSel , [1] UseIPLock = 0
+	{REG_RX_035,	0x1E,	(0x10 + (DeltaNum << 2))},	//[3:2] RCLKDeltaSel , [1] UseIPLock = 0
+	{REG_RX_04B,	0x1E,	(0x10 + (DeltaNum << 2))},	//[3:2] RCLKDeltaSel , [1] UseIPLock = 0
 //FIX_ID_001 xxxxx
 //FIX_ID_017 xxxxx
-	{REG_RX_054,	0xFF,	(1<<4)+RCLKFreqSel},	//[1:0]RCLK frequency select
+	{REG_RX_054,	0xFF,	(1 << 4) + RCLKFreqSel},	//[1:0]RCLK frequency select
 	{REG_RX_06A,	0xFF,	GenPktRecType},			//Decide which kind of packet to be fully recorded on General PKT register
 	{REG_RX_074,	0xFF,	0xA0},	//[7]Enable i2s and SPDIFoutput [5]Disable false DE output
 	{REG_RX_050,	0x1F,	0x12},	//[4]1: Invert output DCLK and DCLK DELAY 2 Step
@@ -380,7 +376,7 @@ static _CODE struct IT6602_REG_INI  IT6602_HDMI_INIT_TABLE[] = {
 
 #ifdef  _SUPPORT_EDID_RAM_
 	{REG_RX_0C0,	0x43,	0x40},	//[0]1:Reg_P0DisableShadow
-	{REG_RX_087,	0xFF,	(EDID_ADDR|0x01)},	//[7:1] EDID RAM Slave Adr ,[0]1: Enable access EDID block
+	{REG_RX_087,	0xFF,	(EDID_ADDR | 0x01)},	//[7:1] EDID RAM Slave Adr ,[0]1: Enable access EDID block
 #else
 	{REG_RX_0C0,	0x03,	0x03},	//[0]1:Reg_P0DisableShadow
 	{REG_RX_087,	0xFF,	(0x00)},	//[7:1] EDID RAM Slave Adr ,[0]1: Enable access EDID block
@@ -393,7 +389,7 @@ static _CODE struct IT6602_REG_INI  IT6602_HDMI_INIT_TABLE[] = {
 //FIX_ID_030 xxxxx
 	{REG_RX_067,	0x80,	0x00},	//Reg67[7] disable HW CSCSel
 
-	{REG_RX_07A,B_CTS_RES,B_CTS_RES},
+	{REG_RX_07A, B_CTS_RES, B_CTS_RES},
 
 //FIX_ID_037 xxxxx //Allion MHL compliance issue debug !!!
 //FIX_ID_018 xxxxx 	modify 1K pull-down to 1.033K ohm HDMI Reg1C0[3:2]=2
@@ -417,23 +413,23 @@ static _CODE struct IT6602_REG_INI  IT6602_HDMI_INIT_TABLE[] = {
 //FIX_ID_037 xxxxx
 
 #ifdef _HBR_I2S_
-	{REG_RX_07E,B_HBRSel,0x00},
+	{REG_RX_07E, B_HBRSel, 0x00},
 #else
-	{REG_RX_07E,B_HBRSel,B_HBRSel},
+	{REG_RX_07E, B_HBRSel, B_HBRSel},
 #endif
 
-	{REG_RX_052,(B_DisVAutoMute),(B_DisVAutoMute)},				//Reg52[5] = 1 for disable Auto video MUTE
-	{REG_RX_053,(B_VDGatting|B_VIOSel|B_TriVDIO|B_TriSYNC),(B_VIOSel|B_TriVDIO|B_TriSYNC)},				//Reg53[7][5] = 01    // for disable B_VDIO_GATTING
+	{REG_RX_052, (B_DisVAutoMute), (B_DisVAutoMute)},				//Reg52[5] = 1 for disable Auto video MUTE
+	{REG_RX_053, (B_VDGatting | B_VIOSel | B_TriVDIO | B_TriSYNC), (B_VIOSel | B_TriVDIO | B_TriSYNC)},				//Reg53[7][5] = 01    // for disable B_VDIO_GATTING
 
-	{REG_RX_058,0xFF,0x33},			// Reg58 for 4Kx2K Video output Driving Strength
+	{REG_RX_058, 0xFF, 0x33},			// Reg58 for 4Kx2K Video output Driving Strength
 
 //	{REG_RX_059,0xFF,0xAA},			// Reg59 for Audio output Driving Strength
 
 //FIX_ID_001 xxxxx Add Auto EQ with Manual EQ
 //!!!  For Manual Adjust EQ only  !!!
 #ifdef _SUPPORT_MANUAL_ADJUST_EQ_
-	{REG_RX_03E,0x20,0x20},	// Enable OvWrRsCs
-	{REG_RX_026,0x20,0x20},	// Enable OvWrRsCs
+	{REG_RX_03E, 0x20, 0x20},	// Enable OvWrRsCs
+	{REG_RX_026, 0x20, 0x20},	// Enable OvWrRsCs
 #endif
 //FIX_ID_001 xxxxx
 
@@ -505,7 +501,7 @@ static _CODE struct IT6602_REG_INI  IT6602_HDMI_INIT_TABLE[] = {
 
 	// {REG_RX_014,0xFF,0xFF},		//for enable interrupt output Pin
 	// {REG_RX_063,0xFF,0x3F},		//for enable interrupt output Pin MZY 17/5/5
- 
+
 	{REG_RX_073, 0x08, 0x00},		// for HDCPIntKey = false
 
 	{REG_RX_060, 0x40, 0x00},		// disable interrupt mask for NoGenPkt_Rcv
@@ -535,36 +531,32 @@ static _CODE struct IT6602_REG_INI  IT6602_HDMI_INIT_TABLE[] = {
 
 //FIX_ID_036	xxxxx
 
-static _CODE unsigned char bCSCMtx_RGB2YUV_ITU601_16_235[]=
-{
+static _CODE unsigned char bCSCMtx_RGB2YUV_ITU601_16_235[] = {
 	0x00,		0x80,		0x10,
-	0xB2,0x04,	0x65,0x02,	0xE9,0x00,
-	0x93,0x3C,	0x18,0x04,	0x55,0x3F,
-	0x49,0x3D,	0x9F,0x3E,	0x18,0x04
+	0xB2, 0x04,	0x65, 0x02,	0xE9, 0x00,
+	0x93, 0x3C,	0x18, 0x04,	0x55, 0x3F,
+	0x49, 0x3D,	0x9F, 0x3E,	0x18, 0x04
 };
 
-static unsigned char bCSCMtx_RGB2YUV_ITU601_0_255[]=
-{
+static unsigned char bCSCMtx_RGB2YUV_ITU601_0_255[] = {
 	0x10,		0x80,		0x10,
-	0x09,0x04,	0x0E,0x02,	0xC9,0x00,
-	0x0F,0x3D,	0x84,0x03,	0x6D,0x3F,
-	0xAB,0x3D,	0xD1,0x3E,	0x84,0x03
+	0x09, 0x04,	0x0E, 0x02,	0xC9, 0x00,
+	0x0F, 0x3D,	0x84, 0x03,	0x6D, 0x3F,
+	0xAB, 0x3D,	0xD1, 0x3E,	0x84, 0x03
 };
 
-static _CODE unsigned char bCSCMtx_RGB2YUV_ITU709_16_235[]=
-{
+static _CODE unsigned char bCSCMtx_RGB2YUV_ITU709_16_235[] = {
 	0x00,		0x80,		0x10,
-	0xB8,0x05,	0xB4,0x01,	0x94,0x00,
-	0x4A,0x3C,	0x17,0x04,	0x9F,0x3F,
-	0xD9,0x3C,	0x10,0x3F,	0x17,0x04
+	0xB8, 0x05,	0xB4, 0x01,	0x94, 0x00,
+	0x4A, 0x3C,	0x17, 0x04,	0x9F, 0x3F,
+	0xD9, 0x3C,	0x10, 0x3F,	0x17, 0x04
 };
 
-static _CODE unsigned char bCSCMtx_RGB2YUV_ITU709_0_255[]=
-{
+static _CODE unsigned char bCSCMtx_RGB2YUV_ITU709_0_255[] = {
 	0x10,		0x80,		0x10,
-	0xEA,0x04,	0x77,0x01,	0x7F,0x00,
-	0xD0,0x3C,	0x83,0x03,	0xAD,0x3F,
-	0x4B,0x3D,	0x32,0x3F,	0x83,0x03
+	0xEA, 0x04,	0x77, 0x01,	0x7F, 0x00,
+	0xD0, 0x3C,	0x83, 0x03,	0xAD, 0x3F,
+	0x4B, 0x3D,	0x32, 0x3F,	0x83, 0x03
 };
 
 
@@ -637,40 +629,40 @@ static _CODE unsigned char bCSCMtx_RGB2YUV_ITU709_0_255[]=
 #define EDID_SELECT_TABLE	(8)
 
 static unsigned char _CODE Default_Edid_Block[256] = {
-	
-	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x06, 0x8F, 0x07, 0x11, 0x01, 0x00, 0x00, 0x00, 
-	0x17, 0x11, 0x01, 0x03, 0x80, 0x0C, 0x09, 0x78, 0x0A, 0x1E, 0xAC, 0x98, 0x59, 0x56, 0x85, 0x28, 
-	0x29, 0x52, 0x57, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 
-	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x8C, 0x0A, 0xD0, 0x8A, 0x20, 0xE0, 0x2D, 0x10, 0x10, 0x3E, 
-	0x96, 0x00, 0x81, 0x60, 0x00, 0x00, 0x00, 0x18, 0x01, 0x1D, 0x80, 0x18, 0x71, 0x1C, 0x16, 0x20, 
-	0x58, 0x2C, 0x25, 0x00, 0x81, 0x49, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x56, 
-	0x41, 0x2D, 0x31, 0x38, 0x30, 0x39, 0x41, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFD, 
-	0x00, 0x17, 0x3D, 0x0D, 0x2E, 0x11, 0x00, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x9C, 
-	0x02, 0x03, 0x0F, 0x10, 0x42, 0x04, 0x22, 0x67, 0x03, 0x0C, 0x00, 0x10, 0x00, 0x88, 0x2D, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+
+	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x06, 0x8F, 0x07, 0x11, 0x01, 0x00, 0x00, 0x00,
+	0x17, 0x11, 0x01, 0x03, 0x80, 0x0C, 0x09, 0x78, 0x0A, 0x1E, 0xAC, 0x98, 0x59, 0x56, 0x85, 0x28,
+	0x29, 0x52, 0x57, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x8C, 0x0A, 0xD0, 0x8A, 0x20, 0xE0, 0x2D, 0x10, 0x10, 0x3E,
+	0x96, 0x00, 0x81, 0x60, 0x00, 0x00, 0x00, 0x18, 0x01, 0x1D, 0x80, 0x18, 0x71, 0x1C, 0x16, 0x20,
+	0x58, 0x2C, 0x25, 0x00, 0x81, 0x49, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x56,
+	0x41, 0x2D, 0x31, 0x38, 0x30, 0x39, 0x41, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFD,
+	0x00, 0x17, 0x3D, 0x0D, 0x2E, 0x11, 0x00, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x9C,
+	0x02, 0x03, 0x0F, 0x10, 0x42, 0x04, 0x22, 0x67, 0x03, 0x0C, 0x00, 0x10, 0x00, 0x88, 0x2D, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x39
 
 	// 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x05, 0xE3, 0x69, 0x23, 0x66, 0x00, 0x00, 0x00,
-    // 0x0D, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1D, 0x78, 0x2A, 0xE5, 0x95, 0xA6, 0x56, 0x52, 0x9D, 0x27,
-    // 0x10, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01, 0x81, 0xC0, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    // 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x1D, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
-    // 0x45, 0x00, 0xFD, 0x1E, 0x11, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFD, 0x00, 0x32, 0x4C, 0x1E,
-    // 0x53, 0x11, 0x00, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x32,
-    // 0x33, 0x36, 0x39, 0x4D, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFF,
-    // 0x00, 0x42, 0x46, 0x44, 0x44, 0x33, 0x39, 0x41, 0x30, 0x30, 0x30, 0x31, 0x30, 0x32, 0x01, 0x76,
-    // 0x02, 0x03, 0x20, 0xF1, 0x4D, 0xA2, 0x04, 0x13, 0x03, 0x01, 0x11, 0x02, 0x12, 0x3E, 0x3D, 0x3C,
-    // 0x21, 0x20, 0x23, 0x09, 0x06, 0x01, 0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0C, 0x00, 0x10, 0x00,
-    // 0x01, 0x1D, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C, 0x45, 0x00, 0xFD, 0x1E, 0x11, 0x00,
-    // 0x00, 0x1E, 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20, 0x6E, 0x28, 0x55, 0x00, 0xFD, 0x1E,
-    // 0x11, 0x00, 0x00, 0x1E, 0x01, 0x1D, 0x00, 0xBC, 0x52, 0xD0, 0x1E, 0x20, 0xB8, 0x28, 0x55, 0x40,
-    // 0xFD, 0x1E, 0x11, 0x00, 0x00, 0x18, 0x8C, 0x0A, 0xD0, 0x8A, 0x20, 0xE0, 0x2D, 0x10, 0x10, 0x3E,
-    // 0x96, 0x00, 0xFD, 0x1E, 0x11, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    // 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3D
+	// 0x0D, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1D, 0x78, 0x2A, 0xE5, 0x95, 0xA6, 0x56, 0x52, 0x9D, 0x27,
+	// 0x10, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01, 0x81, 0xC0, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+	// 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x1D, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
+	// 0x45, 0x00, 0xFD, 0x1E, 0x11, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFD, 0x00, 0x32, 0x4C, 0x1E,
+	// 0x53, 0x11, 0x00, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x32,
+	// 0x33, 0x36, 0x39, 0x4D, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFF,
+	// 0x00, 0x42, 0x46, 0x44, 0x44, 0x33, 0x39, 0x41, 0x30, 0x30, 0x30, 0x31, 0x30, 0x32, 0x01, 0x76,
+	// 0x02, 0x03, 0x20, 0xF1, 0x4D, 0xA2, 0x04, 0x13, 0x03, 0x01, 0x11, 0x02, 0x12, 0x3E, 0x3D, 0x3C,
+	// 0x21, 0x20, 0x23, 0x09, 0x06, 0x01, 0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0C, 0x00, 0x10, 0x00,
+	// 0x01, 0x1D, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C, 0x45, 0x00, 0xFD, 0x1E, 0x11, 0x00,
+	// 0x00, 0x1E, 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20, 0x6E, 0x28, 0x55, 0x00, 0xFD, 0x1E,
+	// 0x11, 0x00, 0x00, 0x1E, 0x01, 0x1D, 0x00, 0xBC, 0x52, 0xD0, 0x1E, 0x20, 0xB8, 0x28, 0x55, 0x40,
+	// 0xFD, 0x1E, 0x11, 0x00, 0x00, 0x18, 0x8C, 0x0A, 0xD0, 0x8A, 0x20, 0xE0, 0x2D, 0x10, 0x10, 0x3E,
+	// 0x96, 0x00, 0xFD, 0x1E, 0x11, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	// 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3D
 };
 #endif
 
@@ -717,7 +709,7 @@ const char  *VModeStateStr[] = {
 #endif
 
 
-// transfer to cpu2 
+// transfer to cpu2
 static struct h264_input_format_s att;
 static orb_advert_t h264_input_format_topic;
 
@@ -833,7 +825,7 @@ unsigned char rxphyadr[2][2];										   // for EDID RAM function
 unsigned char rxphyA, rxphyB, rxphyC, rxphyD, rxcurport;			   // for CEC function
 
 #ifdef FIX_ID_013
-	//FIX_ID_013	xxxxx	//For MSC 3D request issue
+//FIX_ID_013	xxxxx	//For MSC 3D request issue
 unsigned char uc3DDtd[] = {0x00};
 struct PARSE3D_STR st3DParse;
 MHL3D_STATE e3DReqState = MHL3D_REQ_DONE;
@@ -857,173 +849,163 @@ unsigned char m_MHLabortID = 0x00;
 
 ///////////////////////////////// hdmi /////////////////////////////
 
-// TODO check 
+// TODO check
 uint8_t IT66021::HDMI_RX_MapToDeviceIndex(ENUM_HAL_HDMI_RX e_hdmiIndex)
 {
 	return (e_hdmiIndex == HAL_HDMI_RX_0) ? 1 : 0;
 }
 
 
-uint32_t IT66021::HDMI_RX_CheckVideoFormatChangeOrNot(ENUM_HAL_HDMI_RX e_hdmiIndex, 
-                                                      uint16_t u16_width, 
-                                                      uint16_t u16_hight, 
-                                                      uint8_t u8_framerate)
+uint32_t IT66021::HDMI_RX_CheckVideoFormatChangeOrNot(ENUM_HAL_HDMI_RX e_hdmiIndex,
+		uint16_t u16_width,
+		uint16_t u16_hight,
+		uint8_t u8_framerate)
 {
 	STRU_HDMI_RX_OUTPUT_FORMAT videoFormat = this->s_st_hdmiRxStatus.st_videoFormat;
 
-	if (videoFormat.u16_width != u16_width || videoFormat.u16_hight != u16_hight || videoFormat.u8_framerate != u8_framerate)
-	{
+	if (videoFormat.u16_width != u16_width || videoFormat.u16_hight != u16_hight
+	    || videoFormat.u8_framerate != u8_framerate) {
 		return HAL_OK;
 	}
 
 	return HAL_HDMI_RX_FALSE;
 }
 
-uint8_t IT66021::IT_66021_GetVideoFormat(uint8_t index, uint16_t* widthPtr, uint16_t* hightPtr, uint8_t* framteratePtr, uint8_t* vic)
+uint8_t IT66021::IT_66021_GetVideoFormat(uint8_t index, uint16_t *widthPtr, uint16_t *hightPtr, uint8_t *framteratePtr,
+		uint8_t *vic)
 {
-    if (this->it6602DEV.m_VState == VSTATE_VideoOn)
-    {
-        uint8_t i = 0;
-        uint8_t array_size = sizeof(s_u8Array_ARCastSupportedOutputFormat)/sizeof(s_u8Array_ARCastSupportedOutputFormat[0]);
+	if (this->it6602DEV.m_VState == VSTATE_VideoOn) {
+		uint8_t i = 0;
+		uint8_t array_size = sizeof(s_u8Array_ARCastSupportedOutputFormat) / sizeof(s_u8Array_ARCastSupportedOutputFormat[0]);
 		IT_INFO("%d", array_size);
 
-        for (i = 0; i < array_size; i++)
-        {
-            if (this->it6602DEV.VIC == s_u8Array_ARCastSupportedOutputFormat[i][3])
-            {
-                *widthPtr = s_u8Array_ARCastSupportedOutputFormat[i][0];
-                *hightPtr = s_u8Array_ARCastSupportedOutputFormat[i][1];
-                *framteratePtr = s_u8Array_ARCastSupportedOutputFormat[i][2];
-                *vic = this->it6602DEV.VIC;
-				
+		for (i = 0; i < array_size; i++) {
+			if (this->it6602DEV.VIC == s_u8Array_ARCastSupportedOutputFormat[i][3]) {
+				*widthPtr = s_u8Array_ARCastSupportedOutputFormat[i][0];
+				*hightPtr = s_u8Array_ARCastSupportedOutputFormat[i][1];
+				*framteratePtr = s_u8Array_ARCastSupportedOutputFormat[i][2];
+				*vic = this->it6602DEV.VIC;
+
 				IT_INFO("111 widthPtr = %d \n", *widthPtr);
 				IT_INFO("222 hightPtr = %d \n", *hightPtr);
 				IT_INFO("333 framteratePtr = %d \n", *framteratePtr);
 				IT_INFO("444 vic = %d \n", *vic);
 
-                return TRUE;
-            }
-        }
+				return TRUE;
+			}
+		}
+
+		// uint8_t hdmi_i2c_addr = (index == 0) ? RX_I2C_HDMI_MAP_ADDR : (RX_I2C_HDMI_MAP_ADDR + 2);
 
-        // uint8_t hdmi_i2c_addr = (index == 0) ? RX_I2C_HDMI_MAP_ADDR : (RX_I2C_HDMI_MAP_ADDR + 2);
-		
-        uint32_t u32_HTotal   = ((hdmirxrd(0x9D)&0x3F)<<8) + hdmirxrd(0x9C);
-        uint32_t u32_HActive  = ((hdmirxrd(0x9F)&0x3F)<<8) + hdmirxrd(0x9E);
+		uint32_t u32_HTotal   = ((hdmirxrd(0x9D) & 0x3F) << 8) + hdmirxrd(0x9C);
+		uint32_t u32_HActive  = ((hdmirxrd(0x9F) & 0x3F) << 8) + hdmirxrd(0x9E);
+
+		uint32_t u32_VTotal   = ((hdmirxrd(0xA4) & 0x0F) << 8) + hdmirxrd(0xA3);
+		uint32_t u32_VActive  = ((hdmirxrd(0xA4) & 0xF0) << 4) + hdmirxrd(0xA5);
 
-        uint32_t u32_VTotal   = ((hdmirxrd(0xA4)&0x0F)<<8) + hdmirxrd(0xA3);
-        uint32_t u32_VActive  = ((hdmirxrd(0xA4)&0xF0)<<4) + hdmirxrd(0xA5);
-		
 		IT_INFO("u32_HTotal = %d \n", u32_HTotal);
 		IT_INFO("u32_HActive = %d \n", u32_HActive);
 		IT_INFO("u32_VTotal = %d \n", u32_VTotal);
 		IT_INFO("u32_VActive = %d \n", u32_VActive);
 
 
-        uint8_t u8_rddata = hdmirxrd(0x9A);
-        uint32_t PCLK = (124*255/u8_rddata)/10;
+		uint8_t u8_rddata = hdmirxrd(0x9A);
+		uint32_t PCLK = (124 * 255 / u8_rddata) / 10;
 
-        uint64_t u64_FrameRate = (uint64_t)(PCLK)*1000*1000;
-        u64_FrameRate /= u32_HTotal;
-        u64_FrameRate /= u32_VTotal;
+		uint64_t u64_FrameRate = (uint64_t)(PCLK) * 1000 * 1000;
+		u64_FrameRate /= u32_HTotal;
+		u64_FrameRate /= u32_VTotal;
 
 		IT_INFO("PCLK = %d, u64_FrameRate = %d", PCLK, u64_FrameRate);
-         
-        *widthPtr = (uint16_t)u32_HActive;
-        *hightPtr = (uint16_t)u32_VActive;
-       
-        if ((u64_FrameRate > 55) || (u64_FrameRate > 65))   
-        {
-            *framteratePtr = 60;
-        }
-        else if ((u64_FrameRate > 45) || (u64_FrameRate > 55))
-        {
-            *framteratePtr = 50;    
-        }
-        else if ((u64_FrameRate > 25) || (u64_FrameRate > 35))
-        {
-            *framteratePtr = 30;
-        }
-        *vic = 0xff;
-        return TRUE;
-    }
-    else
-    {
-        *widthPtr = 0;
-        *hightPtr = 0;
-        *framteratePtr = 0;
-        *vic = 0xff;
-        return FALSE;
-    }
+
+		*widthPtr = (uint16_t)u32_HActive;
+		*hightPtr = (uint16_t)u32_VActive;
+
+		if ((u64_FrameRate > 55) || (u64_FrameRate > 65)) {
+			*framteratePtr = 60;
+
+		} else if ((u64_FrameRate > 45) || (u64_FrameRate > 55)) {
+			*framteratePtr = 50;
+
+		} else if ((u64_FrameRate > 25) || (u64_FrameRate > 35)) {
+			*framteratePtr = 30;
+		}
+
+		*vic = 0xff;
+		return TRUE;
+
+	} else {
+		*widthPtr = 0;
+		*hightPtr = 0;
+		*framteratePtr = 0;
+		*vic = 0xff;
+		return FALSE;
+	}
 }
 
 
 
 void IT66021::HDMI_RX_CheckFormatStatus(ENUM_HAL_HDMI_RX e_hdmiIndex, uint32_t b_noDiffCheck)
 {
-    static uint8_t s_u8_formatNotSupportCount = 0;
+	static uint8_t s_u8_formatNotSupportCount = 0;
 
-    uint16_t u16_width;
-    uint16_t u16_hight;
-    uint8_t u8_framerate;
-    uint8_t u8_vic;
+	uint16_t u16_width;
+	uint16_t u16_hight;
+	uint8_t u8_framerate;
+	uint8_t u8_vic;
 
-    uint8_t u8_hdmiIndex = HDMI_RX_MapToDeviceIndex(e_hdmiIndex);
+	uint8_t u8_hdmiIndex = HDMI_RX_MapToDeviceIndex(e_hdmiIndex);
 
 	IT_INFO("s_u8_formatNotSupportCount = %d", s_u8_formatNotSupportCount);
 
-    IT_66021_GetVideoFormat(u8_hdmiIndex, &u16_width, &u16_hight, &u8_framerate, &u8_vic);
-	
-	if (h264_input_format_topic == NULL)
-	{
+	IT_66021_GetVideoFormat(u8_hdmiIndex, &u16_width, &u16_hight, &u8_framerate, &u8_vic);
+
+	if (h264_input_format_topic == NULL) {
 		h264_input_format_topic = orb_advertise(ORB_ID(h264_input_format), &att);
 	}
 
-    if (HDMI_RX_CheckVideoFormatSupportOrNot(u16_width, u16_hight, u8_framerate) == HAL_OK)
-    {
-        s_u8_formatNotSupportCount = 0;
-        if ((b_noDiffCheck == HAL_OK) || 
-            (HDMI_RX_CheckVideoFormatChangeOrNot(e_hdmiIndex, u16_width, u16_hight, u8_framerate) == HAL_OK))
-        {
-            // STRU_SysEvent_H264InputFormatChangeParameter p;
+	if (HDMI_RX_CheckVideoFormatSupportOrNot(u16_width, u16_hight, u8_framerate) == HAL_OK) {
+		s_u8_formatNotSupportCount = 0;
+
+		if ((b_noDiffCheck == HAL_OK) ||
+		    (HDMI_RX_CheckVideoFormatChangeOrNot(e_hdmiIndex, u16_width, u16_hight, u8_framerate) == HAL_OK)) {
+			// STRU_SysEvent_H264InputFormatChangeParameter p;
 			att.index = this->s_st_hdmiRxStatus.st_configure.u8_hdmiToEncoderCh;
-            att.width = u16_width;
-            att.hight = u16_hight;
-            att.framerate = u8_framerate;
-            att.vic = u8_vic;
-            if (HAL_HDMI_RX_0 == e_hdmiIndex)
-            {
-                att.e_h264InputSrc = ENCODER_INPUT_SRC_HDMI_0;
-            }
-            else
-            {
-                att.e_h264InputSrc = ENCODER_INPUT_SRC_HDMI_1;
-            }
-			
+			att.width = u16_width;
+			att.hight = u16_hight;
+			att.framerate = u8_framerate;
+			att.vic = u8_vic;
+
+			if (HAL_HDMI_RX_0 == e_hdmiIndex) {
+				att.e_h264InputSrc = ENCODER_INPUT_SRC_HDMI_0;
+
+			} else {
+				att.e_h264InputSrc = ENCODER_INPUT_SRC_HDMI_1;
+			}
+
 			IT_INFO("index = %d, width = %d, height = %d, frame = %d, vic = %d, e_h264InputSrc = %d", \
-			att.index, att.width, att.hight, att.framerate, att.vic, att.e_h264InputSrc);
+				att.index, att.width, att.hight, att.framerate, att.vic, att.e_h264InputSrc);
 
 			orb_publish(ORB_ID(h264_input_format), h264_input_format_topic, &att);
 
-            this->s_st_hdmiRxStatus.st_videoFormat.u16_width    = u16_width;
-            this->s_st_hdmiRxStatus.st_videoFormat.u16_hight    = u16_hight;
-            this->s_st_hdmiRxStatus.st_videoFormat.u8_framerate = u8_framerate;
-            this->s_st_hdmiRxStatus.st_videoFormat.u8_vic = u8_vic;
-        }
-    }
-    else
-    {
+			this->s_st_hdmiRxStatus.st_videoFormat.u16_width    = u16_width;
+			this->s_st_hdmiRxStatus.st_videoFormat.u16_hight    = u16_hight;
+			this->s_st_hdmiRxStatus.st_videoFormat.u8_framerate = u8_framerate;
+			this->s_st_hdmiRxStatus.st_videoFormat.u8_vic = u8_vic;
+		}
+
+	} else {
 		// STRU_SysEvent_H264InputFormatChangeParameter p;
 		att.index = HAL_HDMI_RX_8BIT; // this->s_st_hdmiRxStatus.st_configure.u8_hdmiToEncoderCh;
 		att.width = 0;
 		att.hight = 0;
 		att.framerate = 0;
 		att.vic = u8_vic;
-		if (HAL_HDMI_RX_0 == e_hdmiIndex)
-		{
+
+		if (HAL_HDMI_RX_0 == e_hdmiIndex) {
 			att.e_h264InputSrc = ENCODER_INPUT_SRC_HDMI_0;
-		}
-		else
-		{
+
+		} else {
 			att.e_h264InputSrc = ENCODER_INPUT_SRC_HDMI_1;
 		}
 
@@ -1034,8 +1016,8 @@ void IT66021::HDMI_RX_CheckFormatStatus(ENUM_HAL_HDMI_RX e_hdmiIndex, uint32_t b
 		this->s_st_hdmiRxStatus.st_videoFormat.u16_hight    = 0;
 		this->s_st_hdmiRxStatus.st_videoFormat.u8_framerate = 0;
 		this->s_st_hdmiRxStatus.st_videoFormat.u8_vic = u8_vic;
-       
-    }
+
+	}
 }
 
 unsigned char IT66021::CheckAVMute(void)
@@ -1047,12 +1029,10 @@ unsigned char IT66021::CheckAVMute(void)
 	ucPortSel = hdmirxrd(REG_RX_051) & B_PORT_SEL;
 
 	if (((ucAVMute & B_P0_AVMUTE) && (ucPortSel == F_PORT_SEL_0)) ||
-		((ucAVMute & B_P1_AVMUTE) && (ucPortSel == F_PORT_SEL_1)))
-	{
+	    ((ucAVMute & B_P1_AVMUTE) && (ucPortSel == F_PORT_SEL_1))) {
 		return TRUE;
-	}
-	else
-	{
+
+	} else {
 		return FALSE;
 	}
 }
@@ -1062,30 +1042,25 @@ unsigned char IT66021::CheckPlg5VPwr(unsigned char ucPortSel)
 	unsigned char sys_state_P0;
 	unsigned char sys_state_P1;
 
-	if (ucPortSel == 0)
-	{
+	if (ucPortSel == 0) {
 		sys_state_P0 = hdmirxrd(REG_RX_P0_SYS_STATUS) & B_P0_PWR5V_DET;
 
 		IT_INFO("CheckPlg5VPwr: sys_state_P0 = %d", sys_state_P0);
 
-		if ((sys_state_P0 & B_P0_PWR5V_DET))
-		{
+		if ((sys_state_P0 & B_P0_PWR5V_DET)) {
 			return TRUE;
-		}
-		else
-		{
+
+		} else {
 			return FALSE;
 		}
-	}
-	else
-	{
+
+	} else {
 		sys_state_P1 = hdmirxrd(REG_RX_P1_SYS_STATUS) & B_P1_PWR5V_DET;
-		if ((sys_state_P1 & B_P1_PWR5V_DET))
-		{
+
+		if ((sys_state_P1 & B_P1_PWR5V_DET)) {
 			return TRUE;
-		}
-		else
-		{
+
+		} else {
 			return FALSE;
 		}
 	}
@@ -1098,7 +1073,7 @@ unsigned char IT66021::IsHDMIMode(void)
 	unsigned char sys_state_P1;
 	unsigned char ucPortSel;
 
-	// TODO: 0x0B 与 Ox51 中的 0x01 
+	// TODO: 0x0B 与 Ox51 中的 0x01
 	sys_state_P0 = hdmirxrd(REG_RX_P0_SYS_STATUS) & B_P0_HDMI_MODE;
 	sys_state_P1 = hdmirxrd(REG_RX_P1_SYS_STATUS) & B_P1_HDMI_MODE;
 	ucPortSel = hdmirxrd(REG_RX_051) & B_PORT_SEL;
@@ -1106,12 +1081,10 @@ unsigned char IT66021::IsHDMIMode(void)
 	IT_INFO("P0 = %d, p1 = %d, sel = %d", sys_state_P0, sys_state_P1, ucPortSel);
 
 	if (((sys_state_P0 & B_P0_HDMI_MODE) && (ucPortSel == F_PORT_SEL_0)) ||
-		((sys_state_P1 & B_P1_HDMI_MODE) && (ucPortSel == F_PORT_SEL_1)))
-	{
+	    ((sys_state_P1 & B_P1_HDMI_MODE) && (ucPortSel == F_PORT_SEL_1))) {
 		return TRUE;
-	}
-	else
-	{
+
+	} else {
 		return FALSE;
 	}
 }
@@ -1128,15 +1101,12 @@ void IT66021::GetAVIInfoFrame(struct it6602_dev_data *it6602)
 	chgbank(0);
 
 	//FIX_ID_027 xxxxx Support RGB limited / Full range convert
-	if (it6602->RGBQuantizationRange == 0)
-	{
-		if (it6602->VIC >= 2)
-		{
+	if (it6602->RGBQuantizationRange == 0) {
+		if (it6602->VIC >= 2) {
 			// CE Mode
 			it6602->RGBQuantizationRange = 1; // limited range
-		}
-		else
-		{
+
+		} else {
 			// IT mode
 			it6602->RGBQuantizationRange = 2; // Full range
 		}
@@ -1164,8 +1134,8 @@ struct it6602_dev_data *IT66021::get_it6602_dev_data(void)
 void IT66021::hdimrx_write_init(struct IT6602_REG_INI _CODE *tdata)
 {
 	int cnt = 0;
-	while (tdata[cnt].ucAddr != 0xFF)
-	{
+
+	while (tdata[cnt].ucAddr != 0xFF) {
 		hdmirxset(tdata[cnt].ucAddr, tdata[cnt].andmask, tdata[cnt].ucValue);
 		cnt++;
 	}
@@ -1177,20 +1147,23 @@ void IT66021::hdimrx_write_init(struct IT6602_REG_INI _CODE *tdata)
 
 void IT66021::chgbank(int bank)
 {
-	switch (bank)
-	{
+	switch (bank) {
 	case 0:
 		hdmirxset(0x0F, 0x03, 0x00);
 		break;
+
 	case 1:
 		hdmirxset(0x0F, 0x03, 0x01);
 		break;
+
 	case 2:
 		hdmirxset(0x0F, 0x03, 0x02);
 		break;
+
 	case 3:
 		hdmirxset(0x0F, 0x03, 0x03);
 		break;
+
 	default:
 		break;
 	}
@@ -1206,21 +1179,19 @@ unsigned char IT66021::CheckSCDT(struct it6602_dev_data *it6602)
 
 	IT_INFO("CheckSCDT: SEL = %d, po = %d, curr = %d", ucPortSel, sys_state_P0, it6602->m_ucCurrentHDMIPort);
 
-	if (ucPortSel == it6602->m_ucCurrentHDMIPort)
-	{
+	if (ucPortSel == it6602->m_ucCurrentHDMIPort) {
 
-		if (sys_state_P0 & B_P0_SCDT)
-		{
+		if (sys_state_P0 & B_P0_SCDT) {
 			//SCDT on
 			//it6602->m_ucSCDTOffCount=0;
 			return TRUE;
-		}
-		else
-		{
+
+		} else {
 			//SCDT off
 			return FALSE;
 		}
 	}
+
 	return FALSE;
 }
 
@@ -1235,44 +1206,39 @@ void IT66021::WaitingForSCDT(struct it6602_dev_data *it6602)
 	sys_state_P1 = hdmirxrd(REG_RX_P1_SYS_STATUS) & (B_P1_SCDT | B_P1_PWR5V_DET | B_P1_RXCK_VALID);
 	ucPortSel = hdmirxrd(REG_RX_051) & B_PORT_SEL;
 
-	IT_INFO("WaitingForSCDT sys_state_P0 = %02x, sys_state_P1 = %02x, ucPortSel = %02x", sys_state_P0, sys_state_P1, ucPortSel);
+	IT_INFO("WaitingForSCDT sys_state_P0 = %02x, sys_state_P1 = %02x, ucPortSel = %02x", sys_state_P0, sys_state_P1,
+		ucPortSel);
 
-	if (sys_state_P0 & B_P0_SCDT) 
-	{
+	if (sys_state_P0 & B_P0_SCDT) {
 		IT6602SwitchVideoState(it6602, VSTATE_SyncChecking); //2013-0520
 		return;
-	}
-	else
-	{
+
+	} else {
 #ifdef _SUPPORT_EQ_ADJUST_
-		if (it6602->EQPort[ucPortSel].f_manualEQadjust == TRUE) // ignore SCDT off when manual EQ adjust !!!
-		{
+
+		if (it6602->EQPort[ucPortSel].f_manualEQadjust == TRUE) { // ignore SCDT off when manual EQ adjust !!!
 			return;
 		}
+
 #endif
 
-		if (ucPortSel == F_PORT_SEL_0)
-		{
+		if (ucPortSel == F_PORT_SEL_0) {
 
-			if ((sys_state_P0 & (B_P0_PWR5V_DET | B_P0_RXCK_VALID)) == (B_P0_PWR5V_DET | B_P0_RXCK_VALID))
-			{
+			if ((sys_state_P0 & (B_P0_PWR5V_DET | B_P0_RXCK_VALID)) == (B_P0_PWR5V_DET | B_P0_RXCK_VALID)) {
 				it6602->m_ucSCDTOffCount++;
 				IT_INFO(" SCDT off count = %X ", (int)it6602->m_ucSCDTOffCount);
 				IT_INFO(" sys_state_P0 = %X", (int)hdmirxrd(REG_RX_P0_SYS_STATUS));
 			}
-		}
-		else
-		{
-			if ((sys_state_P1 & (B_P1_PWR5V_DET | B_P1_RXCK_VALID)) == (B_P1_PWR5V_DET | B_P1_RXCK_VALID))
-			{
+
+		} else {
+			if ((sys_state_P1 & (B_P1_PWR5V_DET | B_P1_RXCK_VALID)) == (B_P1_PWR5V_DET | B_P1_RXCK_VALID)) {
 				it6602->m_ucSCDTOffCount++;
 				IT_INFO(" SCDT off count = %X", (int)it6602->m_ucSCDTOffCount);
 				IT_INFO(" sys_state_P1 = %X", (int)hdmirxrd(REG_RX_P1_SYS_STATUS));
 			}
 		}
 
-		if ((it6602->m_ucSCDTOffCount) > SCDT_OFF_TIMEOUT)
-		{
+		if ((it6602->m_ucSCDTOffCount) > SCDT_OFF_TIMEOUT) {
 			it6602->m_ucSCDTOffCount = 0;
 			IT_INFO(" WaitingForSCDT( ) CDR reset !!! \r\n");
 			hdmirx_ECCTimingOut(ucPortSel);
@@ -1290,19 +1256,22 @@ void IT66021::WaitingForSCDT(struct it6602_dev_data *it6602)
 unsigned char IT66021::CLKCheck(unsigned char ucPortSel)
 {
 	unsigned char sys_state;
-	if (ucPortSel == F_PORT_SEL_1)
-	{
+
+	if (ucPortSel == F_PORT_SEL_1) {
 		sys_state = hdmirxrd(REG_RX_P1_SYS_STATUS) & (B_P1_RXCK_VALID);
-	}
-	else
-	{
+
+	} else {
 		sys_state = hdmirxrd(REG_RX_P0_SYS_STATUS) & (B_P0_RXCK_VALID);
 	}
+
 	IT_INFO("CLKCheck: %d", sys_state);
-	if (sys_state == B_P0_RXCK_VALID)
+
+	if (sys_state == B_P0_RXCK_VALID) {
 		return TRUE;
-	else
+
+	} else {
 		return FALSE;
+	}
 }
 
 //FIX_ID_009 xxxxx	//verify interrupt event with reg51[0] select port
@@ -1314,12 +1283,10 @@ unsigned char IT66021::IT6602_IsSelectedPort(unsigned char ucPortSel)
 
 	ucCurrentPort = hdmirxrd(REG_RX_051) & B_PORT_SEL;
 
-	if (ucCurrentPort == ucPortSel)
-	{
+	if (ucCurrentPort == ucPortSel) {
 		return TRUE;
-	}
-	else
-	{
+
+	} else {
 		return FALSE;
 	}
 }
@@ -1328,8 +1295,7 @@ void IT66021::IT6602_VideoOutputConfigure_Init(struct it6602_dev_data *it6602, V
 {
 	it6602->m_VidOutConfigMode = eVidOutConfig;
 
-	switch (eVidOutConfig)
-	{
+	switch (eVidOutConfig) {
 	case eRGB444_SDR:
 		it6602->m_bOutputVideoMode = F_MODE_RGB444;
 		it6602->m_bOutputVideoMode = F_MODE_RGB444 | F_MODE_0_255;
@@ -1426,6 +1392,7 @@ void IT66021::IT6602_VideoOutputConfigure_Init(struct it6602_dev_data *it6602, V
 		it6602->m_VidOutDataTrgger = eDDR_BTA1004; // eHalfPCLKDDR
 		it6602->m_VidOutSyncMode = eEmbSync;
 		break;
+
 	default:
 		break;
 	}
@@ -1460,40 +1427,40 @@ void IT66021::hdmirx_Var_init(struct it6602_dev_data *it6602)
 
 	it6602->m_bRxAVmute = FALSE;
 
-	#ifdef _SUPPORT_EQ_ADJUST_
-		it6602->EQPort[0].ucEQState = 0xFF;
-		it6602->EQPort[0].ucAuthR0 = 0;
-		it6602->EQPort[0].ucECCvalue = 0;
-		it6602->EQPort[0].ucECCfailCount = 0;
-		it6602->EQPort[0].ucPkt_Err = 0; //Pkt_Err
-		it6602->EQPort[0].ucPortID = F_PORT_SEL_0;
-
-		it6602->EQPort[1].ucEQState = 0xFF;
-		it6602->EQPort[1].ucAuthR0 = 0;
-		it6602->EQPort[1].ucECCvalue = 0;
-		it6602->EQPort[1].ucECCfailCount = 0;
-		it6602->EQPort[1].ucPkt_Err = 0;
-		it6602->EQPort[1].ucPortID = F_PORT_SEL_1;
-
-		it6602->EQPort[0].f_manualEQadjust = FALSE;
-		it6602->EQPort[1].f_manualEQadjust = FALSE;
-
-	#endif
-
-	#ifdef _SUPPORT_AUTO_EQ_
-
-		ucPortAMPOverWrite[1] = 0; //2013-0801
-		ucPortAMPValid[1] = 0;
-		ucChannelB[1] = 0;
-		ucChannelG[1] = 0;
-		ucChannelR[1] = 0;
-
-		ucPortAMPOverWrite[0] = 0; //2013-0801
-		ucPortAMPValid[0] = 0;
-		ucChannelB[0] = 0;
-		ucChannelG[0] = 0;
-		ucChannelR[0] = 0;
-	#endif
+#ifdef _SUPPORT_EQ_ADJUST_
+	it6602->EQPort[0].ucEQState = 0xFF;
+	it6602->EQPort[0].ucAuthR0 = 0;
+	it6602->EQPort[0].ucECCvalue = 0;
+	it6602->EQPort[0].ucECCfailCount = 0;
+	it6602->EQPort[0].ucPkt_Err = 0; //Pkt_Err
+	it6602->EQPort[0].ucPortID = F_PORT_SEL_0;
+
+	it6602->EQPort[1].ucEQState = 0xFF;
+	it6602->EQPort[1].ucAuthR0 = 0;
+	it6602->EQPort[1].ucECCvalue = 0;
+	it6602->EQPort[1].ucECCfailCount = 0;
+	it6602->EQPort[1].ucPkt_Err = 0;
+	it6602->EQPort[1].ucPortID = F_PORT_SEL_1;
+
+	it6602->EQPort[0].f_manualEQadjust = FALSE;
+	it6602->EQPort[1].f_manualEQadjust = FALSE;
+
+#endif
+
+#ifdef _SUPPORT_AUTO_EQ_
+
+	ucPortAMPOverWrite[1] = 0; //2013-0801
+	ucPortAMPValid[1] = 0;
+	ucChannelB[1] = 0;
+	ucChannelG[1] = 0;
+	ucChannelR[1] = 0;
+
+	ucPortAMPOverWrite[0] = 0; //2013-0801
+	ucPortAMPValid[0] = 0;
+	ucChannelB[0] = 0;
+	ucChannelG[0] = 0;
+	ucChannelR[0] = 0;
+#endif
 
 	//FIX_ID_005 xxxxx 	//Add Cbus Event Handler
 	it6602->CBusIntEvent = 0;
@@ -1507,14 +1474,14 @@ void IT66021::hdmirx_Var_init(struct it6602_dev_data *it6602)
 	it6602->HDMIWaitNo[1] = 0;
 	//FIX_ID_005 xxxxx
 
-	#ifdef _IT6607_GeNPacket_Usage_
+#ifdef _IT6607_GeNPacket_Usage_
 	asdasdasda
-    it6602->m_PollingPacket=0;
-    it6602->m_PacketState=0;
-    it6602->m_ACPState=0;
-    it6602->m_GamutPacketRequest=FALSE;
-    it6602->m_GeneralRecPackType=0x00;
-    #endif
+	it6602->m_PollingPacket = 0;
+	it6602->m_PacketState = 0;
+	it6602->m_ACPState = 0;
+	it6602->m_GamutPacketRequest = FALSE;
+	it6602->m_GeneralRecPackType = 0x00;
+#endif
 	it6602->m_ucCurrentHDMIPort = 0xff;
 
 	//FIX_ID_034 xxxxx //Add MHL HPD Control by it6602HPDCtrl( )
@@ -1544,7 +1511,7 @@ char IT66021::IT6602_fsm_init(void)
 
 	EDIDRAMInitial(&Default_Edid_Block[0]);
 
-	hdmirxset(REG_RX_0C0, 0x20, 0x20); 
+	hdmirxset(REG_RX_0C0, 0x20, 0x20);
 
 	IT_Delay(1);
 
@@ -1565,25 +1532,28 @@ void IT66021::SetVideoInputFormatWithInfoFrame(struct it6602_dev_data *it6602)
 	chgbank(0);
 	it6602->m_bInputVideoMode &= ~F_MODE_CLRMOD_MASK;
 
-	switch ((i >> O_AVI_COLOR_MODE) & M_AVI_COLOR_MASK)
-	{
+	switch ((i >> O_AVI_COLOR_MODE) & M_AVI_COLOR_MASK) {
 	case B_AVI_COLOR_YUV444:
 		IT_INFO("input YUV444 mode ");
 		it6602->m_bInputVideoMode |= F_MODE_YUV444;
 		break;
+
 	case B_AVI_COLOR_YUV422:
 		IT_INFO("input YUV422 mode ");
 		it6602->m_bInputVideoMode |= F_MODE_YUV422;
 		break;
+
 	case B_AVI_COLOR_RGB24:
 		IT_INFO("input RGB24 mode ");
 		it6602->m_bInputVideoMode |= F_MODE_RGB24;
 		break;
+
 	default:
 		return;
 	}
 
-	IT_INFO("SetVideoInputFormatWithInfoFrame - RegAE=%X it6602->m_bInputVideoMode=%X\n", (int)i, (int)it6602->m_bInputVideoMode);
+	IT_INFO("SetVideoInputFormatWithInfoFrame - RegAE=%X it6602->m_bInputVideoMode=%X\n", (int)i,
+		(int)it6602->m_bInputVideoMode);
 	i = hdmirxrd(REG_RX_IN_CSC_CTRL);
 	i &= ~B_IN_FORCE_COLOR_MODE;
 	hdmirxwr(REG_RX_IN_CSC_CTRL, i);
@@ -1600,12 +1570,10 @@ void IT66021::SetColorimetryByInfoFrame(struct it6602_dev_data *it6602)
 
 	i &= M_AVI_CLRMET_MASK << O_AVI_CLRMET;
 
-	if (i == (B_AVI_CLRMET_ITU601 << O_AVI_CLRMET))
-	{
+	if (i == (B_AVI_CLRMET_ITU601 << O_AVI_CLRMET)) {
 		it6602->m_bInputVideoMode &= ~F_MODE_ITU709;
-	}
-	else if (i == (B_AVI_CLRMET_ITU709 << O_AVI_CLRMET))
-	{
+
+	} else if (i == (B_AVI_CLRMET_ITU709 << O_AVI_CLRMET)) {
 		it6602->m_bInputVideoMode |= F_MODE_ITU709;
 	}
 }
@@ -1614,20 +1582,21 @@ void IT66021::SetCSCBYPASS(struct it6602_dev_data *it6602)
 {
 	it6602->m_bOutputVideoMode = it6602->m_bInputVideoMode;
 
-	switch (it6602->m_bInputVideoMode & F_MODE_CLRMOD_MASK)
-	{
+	switch (it6602->m_bInputVideoMode & F_MODE_CLRMOD_MASK) {
 	case F_MODE_RGB24:
 		hdmirxset(REG_RX_OUT_CSC_CTRL, (M_OUTPUT_COLOR_MASK), B_OUTPUT_RGB24);
 #ifdef _SUPPORT_RBSWAP_
 		hdmirxset(REG_RX_064, 0x18, 0x08);
 #endif
 		break;
+
 	case F_MODE_YUV422:
 		hdmirxset(REG_RX_OUT_CSC_CTRL, (M_OUTPUT_COLOR_MASK), B_OUTPUT_YUV422);
 #ifdef _SUPPORT_RBSWAP_
 		hdmirxset(REG_RX_064, 0x18, 0x10);
 #endif
 		break;
+
 	case F_MODE_YUV444:
 		hdmirxset(REG_RX_OUT_CSC_CTRL, (M_OUTPUT_COLOR_MASK), B_OUTPUT_YUV444);
 #ifdef _SUPPORT_RBSWAP_
@@ -1654,195 +1623,202 @@ void IT66021::SetColorSpaceConvert(struct it6602_dev_data *it6602)
 	IT_INFO("\n!!! SetColorSpaceConvert( ) !!!\n");
 
 #ifdef _AVOID_REDUNDANCE_CSC_
-	if ((it6602->m_Backup_OutputVideoMode == it6602->m_bOutputVideoMode) && (it6602->m_Backup_InputVideoMode == it6602->m_bInputVideoMode))
-	{
+
+	if ((it6602->m_Backup_OutputVideoMode == it6602->m_bOutputVideoMode)
+	    && (it6602->m_Backup_InputVideoMode == it6602->m_bInputVideoMode)) {
 		IT_INFO("I/P and O/P color without change , No need to setup CSC convert again \n");
 		return;
 	}
+
 #endif
 
 	//IT_INFO("Input mode is YUV444 ");
-	switch (it6602->m_bOutputVideoMode & F_MODE_CLRMOD_MASK)
-	{
+	switch (it6602->m_bOutputVideoMode & F_MODE_CLRMOD_MASK) {
 #if defined(SUPPORT_OUTPUTYUV444)
+
 	case F_MODE_YUV444:
 		IT_INFO("Output mode is YUV444\n");
-		switch (it6602->m_bInputVideoMode & F_MODE_CLRMOD_MASK)
-		{
+
+		switch (it6602->m_bInputVideoMode & F_MODE_CLRMOD_MASK) {
 		case F_MODE_YUV444:
 			IT_INFO("Input mode is YUV444\n");
 			csc = B_CSC_BYPASS;
 			break;
+
 		case F_MODE_YUV422:
 			IT_INFO("Input mode is YUV422\n");
 			csc = B_CSC_BYPASS;
-			if (it6602->m_bOutputVideoMode & F_MODE_EN_UDFILT) // RGB24 to YUV422 need up/dn filter.
-			{
+
+			if (it6602->m_bOutputVideoMode & F_MODE_EN_UDFILT) { // RGB24 to YUV422 need up/dn filter.
 				filter |= B_RX_EN_UDFILTER;
 			}
 
-			if (it6602->m_bOutputVideoMode & F_MODE_EN_DITHER) // RGB24 to YUV422 need up/dn filter.
-			{
+			if (it6602->m_bOutputVideoMode & F_MODE_EN_DITHER) { // RGB24 to YUV422 need up/dn filter.
 				filter |= B_RX_EN_UDFILTER | B_RX_DNFREE_GO;
 			}
 
 			break;
+
 		case F_MODE_RGB24:
 			IT_INFO("Input mode is RGB444\n");
 			csc = B_CSC_RGB2YUV;
 			break;
 		}
+
 		break;
 #endif
 
 #if defined(SUPPORT_OUTPUTYUV422)
 
 	case F_MODE_YUV422:
-		switch (it6602->m_bInputVideoMode & F_MODE_CLRMOD_MASK)
-		{
+		switch (it6602->m_bInputVideoMode & F_MODE_CLRMOD_MASK) {
 		case F_MODE_YUV444:
 			IT_INFO("Input mode is YUV444\n");
-			if (it6602->m_bOutputVideoMode & F_MODE_EN_UDFILT)
-			{
+
+			if (it6602->m_bOutputVideoMode & F_MODE_EN_UDFILT) {
 				filter |= B_RX_EN_UDFILTER;
 			}
+
 			csc = B_CSC_BYPASS;
 			break;
+
 		case F_MODE_YUV422:
 			IT_INFO("Input mode is YUV422\n");
 			csc = B_CSC_BYPASS;
 
-			if (it6602->m_bOutputVideoMode & F_MODE_EN_DITHER) // RGB24 to YUV422 need up/dn filter.
-			{
+			if (it6602->m_bOutputVideoMode & F_MODE_EN_DITHER) { // RGB24 to YUV422 need up/dn filter.
 				filter |= B_RX_EN_UDFILTER | B_RX_DNFREE_GO;
 			}
+
 			break;
+
 		case F_MODE_RGB24:
 			IT_INFO("Input mode is RGB444\n");
-			if (it6602->m_bOutputVideoMode & F_MODE_EN_UDFILT) // RGB24 to YUV422 need up/dn filter.
-			{
+
+			if (it6602->m_bOutputVideoMode & F_MODE_EN_UDFILT) { // RGB24 to YUV422 need up/dn filter.
 				filter |= B_RX_EN_UDFILTER;
 			}
+
 			csc = B_CSC_RGB2YUV;
 			break;
 		}
+
 		break;
 #endif
 
 #if defined(SUPPORT_OUTPUTRGB)
+
 	case F_MODE_RGB24:
 		IT_INFO("Output mode is RGB24\n");
-		switch (it6602->m_bInputVideoMode & F_MODE_CLRMOD_MASK)
-		{
+
+		switch (it6602->m_bInputVideoMode & F_MODE_CLRMOD_MASK) {
 		case F_MODE_YUV444:
 			IT_INFO("Input mode is YUV444\n");
 			csc = B_CSC_YUV2RGB;
 			break;
+
 		case F_MODE_YUV422:
 			IT_INFO("Input mode is YUV422\n");
 			csc = B_CSC_YUV2RGB;
-			if (it6602->m_bOutputVideoMode & F_MODE_EN_UDFILT) // RGB24 to YUV422 need up/dn filter.
-			{
+
+			if (it6602->m_bOutputVideoMode & F_MODE_EN_UDFILT) { // RGB24 to YUV422 need up/dn filter.
 				filter |= B_RX_EN_UDFILTER;
 			}
-			if (it6602->m_bOutputVideoMode & F_MODE_EN_DITHER) // RGB24 to YUV422 need up/dn filter.
-			{
+
+			if (it6602->m_bOutputVideoMode & F_MODE_EN_DITHER) { // RGB24 to YUV422 need up/dn filter.
 				filter |= B_RX_EN_UDFILTER | B_RX_DNFREE_GO;
 			}
+
 			break;
+
 		case F_MODE_RGB24:
 			IT_INFO("Input mode is RGB444\n");
 			csc = B_CSC_BYPASS;
 			break;
 		}
+
 		break;
 #endif
 	}
 
 #if defined(SUPPORT_OUTPUTYUV)
+
 	// set the CSC associated registers
-	if (csc == B_CSC_RGB2YUV)
-	{
+	if (csc == B_CSC_RGB2YUV) {
 		// IT_INFO("CSC = RGB2YUV ");
 		//FIX_ID_039 xxxxx fix image flick when enable RGB limited / Full range convert
 		//default to turn off CSC offset
 		hdmirxset(REG_RX_067, 0x78, 0x00);
 		hdmirxwr(REG_RX_068, 0x00);
 		IT_INFO(" Clear Reg67 and Reg68 ... \r\n");
+
 		//FIX_ID_039 xxxxx
-		if (it6602->m_bInputVideoMode & F_MODE_ITU709)
-		{
+		if (it6602->m_bInputVideoMode & F_MODE_ITU709) {
 			IT_INFO("ITU709 ");
 
-			if (it6602->m_bInputVideoMode & F_MODE_16_235)
-			{
+			if (it6602->m_bInputVideoMode & F_MODE_16_235) {
 				IT_INFO(" 16-235\n");
 				chgbank(1); //for CSC setting Reg170 ~ Reg184 !!!!
 				hdmirxbwr(REG_RX_170, sizeof(bCSCMtx_RGB2YUV_ITU709_16_235), &bCSCMtx_RGB2YUV_ITU709_16_235[0]);
-			}
-			else
-			{
+
+			} else {
 				IT_INFO(" 0-255\n");
 				chgbank(1); //for CSC setting Reg170 ~ Reg184 !!!!
 				hdmirxbwr(REG_RX_170, sizeof(bCSCMtx_RGB2YUV_ITU709_0_255), &bCSCMtx_RGB2YUV_ITU709_0_255[0]);
 			}
-		}
-		else
-		{
+
+		} else {
 			IT_INFO("ITU601 ");
-			if (it6602->m_bInputVideoMode & F_MODE_16_235)
-			{
+
+			if (it6602->m_bInputVideoMode & F_MODE_16_235) {
 				chgbank(1); //for CSC setting Reg170 ~ Reg184 !!!!
 				hdmirxbwr(REG_RX_170, sizeof(bCSCMtx_RGB2YUV_ITU601_16_235), &bCSCMtx_RGB2YUV_ITU601_16_235[0]);
 				IT_INFO(" 16-235\n");
-			}
-			else
-			{
+
+			} else {
 				chgbank(1); //for CSC setting Reg170 ~ Reg184 !!!!
 				hdmirxbwr(REG_RX_170, sizeof(bCSCMtx_RGB2YUV_ITU601_0_255), &bCSCMtx_RGB2YUV_ITU601_0_255[0]);
 				IT_INFO(" 0-255\n");
 			}
 		}
 	}
+
 #endif
 
 #if defined(SUPPORT_OUTPUTRGB)
-	if (csc == B_CSC_YUV2RGB)
-	{
+
+	if (csc == B_CSC_YUV2RGB) {
 		IT_INFO("CSC = YUV2RGB ");
 		//FIX_ID_039 xxxxx fix image flick when enable RGB limited / Full range convert
 		//default to turn off CSC offset
 		hdmirxset(REG_RX_067, 0x78, 0x00);
 		hdmirxwr(REG_RX_068, 0x00);
 		IT_INFO(" Clear Reg67 and Reg68 ... \r\n");
+
 		//FIX_ID_039 xxxxx
-		if (it6602->m_bInputVideoMode & F_MODE_ITU709)
-		{
+		if (it6602->m_bInputVideoMode & F_MODE_ITU709) {
 			IT_INFO("ITU709 ");
-			if (it6602->m_bOutputVideoMode & F_MODE_16_235)
-			{
+
+			if (it6602->m_bOutputVideoMode & F_MODE_16_235) {
 				IT_INFO("16-235\n");
 				chgbank(1); //for CSC setting Reg170 ~ Reg184 !!!!
 				hdmirxbwr(REG_RX_170, sizeof(bCSCMtx_YUV2RGB_ITU709_16_235), &bCSCMtx_YUV2RGB_ITU709_16_235[0]);
-			}
-			else
-			{
+
+			} else {
 				IT_INFO("0-255\n");
 				chgbank(1); //for CSC setting Reg170 ~ Reg184 !!!!
 				hdmirxbwr(REG_RX_170, sizeof(bCSCMtx_YUV2RGB_ITU709_0_255), &bCSCMtx_YUV2RGB_ITU709_0_255[0]);
 			}
-		}
-		else
-		{
+
+		} else {
 			IT_INFO("ITU601 ");
-			if (it6602->m_bOutputVideoMode & F_MODE_16_235)
-			{
+
+			if (it6602->m_bOutputVideoMode & F_MODE_16_235) {
 				IT_INFO("16-235\n");
 				chgbank(1); //for CSC setting Reg170 ~ Reg184 !!!!
 				hdmirxbwr(REG_RX_170, sizeof(bCSCMtx_YUV2RGB_ITU601_16_235), &bCSCMtx_YUV2RGB_ITU601_16_235[0]);
-			}
-			else
-			{
+
+			} else {
 				IT_INFO("0-255\n");
 				chgbank(1); //for CSC setting Reg170 ~ Reg184 !!!!
 				hdmirxbwr(REG_RX_170, sizeof(bCSCMtx_YUV2RGB_ITU601_0_255), &bCSCMtx_YUV2RGB_ITU601_0_255[0]);
@@ -1851,15 +1827,11 @@ void IT66021::SetColorSpaceConvert(struct it6602_dev_data *it6602)
 	}
 
 	//FIX_ID_027 xxxxx Support Full/Limited Range convert
-	if (csc == B_CSC_BYPASS)
-	{
+	if (csc == B_CSC_BYPASS) {
 
-		if ((it6602->m_bInputVideoMode & F_MODE_CLRMOD_MASK) == F_MODE_RGB24)
-		{
-			if (it6602->RGBQuantizationRange == 1) // Limited range from HDMI source
-			{
-				if ((it6602->m_bOutputVideoMode & F_MODE_16_235) != F_MODE_16_235) // Full range to back-end device
-				{
+		if ((it6602->m_bInputVideoMode & F_MODE_CLRMOD_MASK) == F_MODE_RGB24) {
+			if (it6602->RGBQuantizationRange == 1) { // Limited range from HDMI source
+				if ((it6602->m_bOutputVideoMode & F_MODE_16_235) != F_MODE_16_235) { // Full range to back-end device
 					// RedText;
 					IT_INFO(" bCSCMtx_RGB_16_235_RGB_0_255 \r\n");
 					// printf("pccmd w 65 02 90;\r\n");
@@ -1874,11 +1846,9 @@ void IT66021::SetColorSpaceConvert(struct it6602_dev_data *it6602)
 					hdmirxset(REG_RX_067, 0x78, 0x78);
 					hdmirxwr(REG_RX_068, 0xED);
 				}
-			}
-			else if (it6602->RGBQuantizationRange == 2) //Full range from HDMI source
-			{
-				if ((it6602->m_bOutputVideoMode & F_MODE_16_235) == F_MODE_16_235) // Limited range to back-end device
-				{
+
+			} else if (it6602->RGBQuantizationRange == 2) { //Full range from HDMI source
+				if ((it6602->m_bOutputVideoMode & F_MODE_16_235) == F_MODE_16_235) { // Limited range to back-end device
 					// RedText;
 					IT_INFO(" bCSCMtx_RGB_0_255_RGB_16_235 \r\n");
 					// printf("pccmd w 65 02 90;\r\n");
@@ -1896,6 +1866,7 @@ void IT66021::SetColorSpaceConvert(struct it6602_dev_data *it6602)
 			}
 		}
 	}
+
 	//FIX_ID_027 xxxxx
 
 #endif // SUPPORT_OUTPUTRGB
@@ -1907,9 +1878,9 @@ void IT66021::SetColorSpaceConvert(struct it6602_dev_data *it6602)
 
 	// set output Up/Down Filter, Dither control
 	hdmirxset(REG_RX_VIDEO_CTRL1, (B_RX_DNFREE_GO | B_RX_EN_DITHER | B_RX_EN_UDFILTER), filter);
+
 	//FIX_ID_039 xxxxx fix image flick when enable RGB limited / Full range convert
-	if (csc == B_CSC_BYPASS)
-	{
+	if (csc == B_CSC_BYPASS) {
 		//default to turn off CSC offset
 		hdmirxset(REG_RX_067, 0x78, 0x00);
 		hdmirxwr(REG_RX_068, 0x00);
@@ -1946,23 +1917,26 @@ void IT66021::SetVideoInputFormatWithoutInfoFrame(struct it6602_dev_data *it6602
 	i &= (~M_INPUT_COLOR_MASK);
 	it6602->m_bInputVideoMode &= ~F_MODE_CLRMOD_MASK;
 
-	switch (bInMode)
-	{
+	switch (bInMode) {
 	case F_MODE_YUV444:
 		i |= B_INPUT_YUV444;
 		it6602->m_bInputVideoMode |= F_MODE_YUV444;
 		break;
+
 	case F_MODE_YUV422:
 		i |= B_INPUT_YUV422;
 		it6602->m_bInputVideoMode |= F_MODE_YUV422;
 		break;
+
 	case F_MODE_RGB24:
 		i |= B_INPUT_RGB24;
 		it6602->m_bInputVideoMode |= F_MODE_RGB24;
 		break;
+
 	default:
 		return;
 	}
+
 	hdmirxwr(REG_RX_IN_CSC_CTRL, i);
 }
 
@@ -1976,13 +1950,11 @@ void IT66021::SetColorimetryByMode(struct it6602_dev_data *it6602)
 
 	it6602->m_bInputVideoMode &= ~F_MODE_ITU709;
 
-	if (RxClkXCNT < 0x34)
-	{
+	if (RxClkXCNT < 0x34) {
 
 		it6602->m_bInputVideoMode |= F_MODE_ITU709;
-	}
-	else
-	{
+
+	} else {
 
 		it6602->m_bInputVideoMode &= ~F_MODE_ITU709;
 	}
@@ -2011,22 +1983,24 @@ void IT66021::IT6602_VideoOutputModeSet(struct it6602_dev_data *it6602)
 	IT_INFO("+++ %s", VModeStateStr[(unsigned char)it6602->m_VidOutConfigMode]);
 
 	ucReg51 = hdmirxrd(REG_RX_051) & 0x9B; // Reg51 [6] Half PCLK DDR , [5] Half Bus DDR , [2] CCIR656 mode
-	ucReg65 = hdmirxrd(REG_RX_065) & 0x0F; // Reg65 [7] BTA1004Fmt , [6] SyncEmb , [5:4] output color 0x00 RGB, 0x10 YUV422, 0x20 YUV444
+	ucReg65 = hdmirxrd(REG_RX_065) &
+		  0x0F; // Reg65 [7] BTA1004Fmt , [6] SyncEmb , [5:4] output color 0x00 RGB, 0x10 YUV422, 0x20 YUV444
 
-	switch ((it6602->m_bOutputVideoMode & F_MODE_CLRMOD_MASK))
-	{
+	switch ((it6602->m_bOutputVideoMode & F_MODE_CLRMOD_MASK)) {
 	case F_MODE_RGB444:
 		ucReg65 |= (B_OUTPUT_RGB24); // 0x00 B_OUTPUT_RGB24
 #ifdef _SUPPORT_RBSWAP_
 		hdmirxset(REG_RX_064, 0x18, 0x08);
 #endif
 		break;
+
 	case F_MODE_YUV422:
 		ucReg65 |= (B_OUTPUT_YUV422); // 0x10 B_OUTPUT_YUV422
 #ifdef _SUPPORT_RBSWAP_
 		hdmirxset(REG_RX_064, 0x18, 0x10);
 #endif
 		break;
+
 	case F_MODE_YUV444:
 		ucReg65 |= (B_OUTPUT_YUV444); // 0x20 B_OUTPUT_YUV444
 #ifdef _SUPPORT_RBSWAP_
@@ -2035,8 +2009,7 @@ void IT66021::IT6602_VideoOutputModeSet(struct it6602_dev_data *it6602)
 		break;
 	}
 
-	switch (it6602->m_VidOutDataTrgger)
-	{
+	switch (it6602->m_VidOutDataTrgger) {
 	case eSDR:
 		break;
 
@@ -2058,8 +2031,7 @@ void IT66021::IT6602_VideoOutputModeSet(struct it6602_dev_data *it6602)
 		break;
 	}
 
-	switch (it6602->m_VidOutSyncMode)
-	{
+	switch (it6602->m_VidOutSyncMode) {
 	case eSepSync:
 		break;
 
@@ -2087,28 +2059,30 @@ void IT66021::IT6602_VideoOutputModeSet(struct it6602_dev_data *it6602)
 void IT66021::IT6602VideoOutputConfigure(struct it6602_dev_data *it6602)
 {
 	it6602->m_bUpHDMIMode = IsHDMIMode();
-	if (it6602->m_bUpHDMIMode == FALSE)
-	{
+
+	if (it6602->m_bUpHDMIMode == FALSE) {
 		SetDVIVideoOutput(it6602);
-	}
-	else
-	{
+
+	} else {
 		GetAVIInfoFrame(it6602);
 		SetNewInfoVideoOutput(it6602);
 	}
+
 	it6602->m_NewAVIInfoFrameF = FALSE;
 
 	it6602->GCP_CD = ((hdmirxrd(0x99) & 0xF0) >> 4);
-	switch (it6602->GCP_CD)
-	{
+
+	switch (it6602->GCP_CD) {
 	case 5:
 		IT_INFO("\n Output ColorDepth = 30 bits per pixel\r\n");
 		hdmirxset(0x65, 0x0C, 0x04);
 		break;
+
 	case 6:
 		IT_INFO("\n Output ColorDepth = 36 bits per pixel\r\n");
 		hdmirxset(0x65, 0x0C, 0x08);
 		break;
+
 	default:
 		IT_INFO("\n Output ColorDepth = 24 bits per pixel\r\n");
 		hdmirxset(0x65, 0x0C, 0x00);
@@ -2122,8 +2096,7 @@ void IT66021::IT6602VideoOutputConfigure(struct it6602_dev_data *it6602)
 // ---------------------------------------------------------------------------
 void IT66021::SetVideoOutputColorFormat(struct it6602_dev_data *it6602)
 {
-	switch (it6602->m_bOutputVideoMode & F_MODE_CLRMOD_MASK)
-	{
+	switch (it6602->m_bOutputVideoMode & F_MODE_CLRMOD_MASK) {
 	case F_MODE_RGB24:
 		hdmirxset(REG_RX_OUT_CSC_CTRL, (M_OUTPUT_COLOR_MASK), B_OUTPUT_RGB24);
 #ifdef _SUPPORT_RBSWAP_
@@ -2131,12 +2104,14 @@ void IT66021::SetVideoOutputColorFormat(struct it6602_dev_data *it6602)
 #endif
 
 		break;
+
 	case F_MODE_YUV422:
 		hdmirxset(REG_RX_OUT_CSC_CTRL, (M_OUTPUT_COLOR_MASK), B_OUTPUT_YUV422);
 #ifdef _SUPPORT_RBSWAP_
 		hdmirxset(REG_RX_064, 0x18, 0x10);
 #endif
 		break;
+
 	case F_MODE_YUV444:
 		hdmirxset(REG_RX_OUT_CSC_CTRL, (M_OUTPUT_COLOR_MASK), B_OUTPUT_YUV444);
 #ifdef _SUPPORT_RBSWAP_
@@ -2161,8 +2136,7 @@ void IT66021::it6602PortSelect(unsigned char ucPortSel)
 	it6602data->m_ucCurrentHDMIPort = F_PORT_SEL_0;
 #endif
 
-	if (it6602data->m_ucCurrentHDMIPort != ucPortSel)
-	{		
+	if (it6602data->m_ucCurrentHDMIPort != ucPortSel) {
 		IT6602SwitchVideoState(it6602data, VSTATE_SyncWait);
 		it6602data->m_ucCurrentHDMIPort = ucPortSel;
 		IT_INFO("it6602PortSelect = %X \r\n", (int)ucPortSel);
@@ -2173,22 +2147,22 @@ void IT66021::hdmirx_ECCTimingOut(unsigned char ucport)
 {
 	IT_INFO("CDR reset for hdmirx_ECCTimingOut()  \r\n");
 
-	if (ucport == F_PORT_SEL_0)
-	{
+	if (ucport == F_PORT_SEL_0) {
 		it6602HPDCtrl(0, 0); // MHL port , set HPD = 0
 
-		hdmirxset(REG_RX_011, (B_P0_DCLKRST | B_P0_CDRRST | B_P0_HDCPRST | B_P0_SWRST), (B_P0_DCLKRST | B_P0_CDRRST | B_P0_HDCPRST | B_P0_SWRST));
+		hdmirxset(REG_RX_011, (B_P0_DCLKRST | B_P0_CDRRST | B_P0_HDCPRST | B_P0_SWRST),
+			  (B_P0_DCLKRST | B_P0_CDRRST | B_P0_HDCPRST | B_P0_SWRST));
 		IT_Delay(300);
 		hdmirxset(REG_RX_011, (B_P0_DCLKRST | B_P0_CDRRST | B_P0_HDCPRST | B_P0_SWRST), 0x00);
 		//set port 0 HPD=1
 		it6602HPDCtrl(0, 1); // MHL port , set HPD = 1
-	}
-	else
-	{
+
+	} else {
 		//set port 1 HPD=0
 		it6602HPDCtrl(1, 0); // HDMI port , set HPD = 0
 
-		hdmirxset(REG_RX_018, (B_P1_DCLKRST | B_P1_CDRRST | B_P1_HDCPRST | B_P1_SWRST), (B_P1_DCLKRST | B_P1_CDRRST | B_P1_HDCPRST | B_P1_SWRST));
+		hdmirxset(REG_RX_018, (B_P1_DCLKRST | B_P1_CDRRST | B_P1_HDCPRST | B_P1_SWRST),
+			  (B_P1_DCLKRST | B_P1_CDRRST | B_P1_HDCPRST | B_P1_SWRST));
 		IT_Delay(300);
 		hdmirxset(REG_RX_018, (B_P1_DCLKRST | B_P1_CDRRST | B_P1_HDCPRST | B_P1_SWRST), 0x00);
 		//set port 1 HPD=1
@@ -2206,8 +2180,8 @@ void IT66021::IT6602_AFE_Rst(void)
 
 	chgbank(0);
 	Reg51h = hdmirxrd(0x51);
-	if (Reg51h & 0x01)
-	{
+
+	if (Reg51h & 0x01) {
 		IT_INFO("=== port 1 IT6602_AFE_Rst() === \r\n");
 		hdmirxset(REG_RX_018, 0x01, 0x01);
 		IT_Delay(1);
@@ -2215,9 +2189,8 @@ void IT66021::IT6602_AFE_Rst(void)
 #ifdef _SUPPORT_AUTO_EQ_
 		DisableOverWriteRS(1); //2013-1129
 #endif
-	}
-	else
-	{
+
+	} else {
 		IT_INFO("=== port 0 IT6602_AFE_Rst() === \r\n");
 		hdmirxset(REG_RX_011, 0x01, 0x01);
 		IT_Delay(1);
@@ -2234,25 +2207,23 @@ void IT66021::IT6602_HDCP_ContentOff(unsigned char ucPort, unsigned char bOff)
 {
 	struct it6602_dev_data *it6602data = get_it6602_dev_data(); //2013-0814
 
-	if (IT6602_IsSelectedPort(ucPort) == FALSE)
+	if (IT6602_IsSelectedPort(ucPort) == FALSE) {
 		return;
+	}
 
-	if (bOff != 0)
-	{
+	if (bOff != 0) {
 		IT6602_ManualVideoTristate(1);
 		it6602data->m_HDCP_ContentOff = 1;
 		IT_INFO("+++++++++++ HDCP Content Off   +++++++++++++++++\n");
-	}
-	else
-	{
-		if (it6602data->m_VState == VSTATE_VideoOn)
-		{
-			if (it6602data->m_HDCP_ContentOff == 1)
-			{
+
+	} else {
+		if (it6602data->m_VState == VSTATE_VideoOn) {
+			if (it6602data->m_HDCP_ContentOff == 1) {
 				IT6602_ManualVideoTristate(0);
 				IT_INFO("+++++++++++ HDCP Content On   +++++++++++++++++\n");
 			}
 		}
+
 		it6602data->m_HDCP_ContentOff = 0;
 	}
 }
@@ -2261,23 +2232,20 @@ void IT66021::IT6602_RAPContentOff(unsigned char bOff)
 {
 	struct it6602_dev_data *it6602data = get_it6602_dev_data(); //2013-0814
 
-	if (IT6602_IsSelectedPort(0) == FALSE)
+	if (IT6602_IsSelectedPort(0) == FALSE) {
 		return;
+	}
 
-	if (bOff != 0)
-	{
+	if (bOff != 0) {
 		IT6602_ManualVideoTristate(1);
 		it6602data->m_RAP_ContentOff = 1;
 		IT_INFO("+++++++++++ RAP Content Off   +++++++++++++++++\n");
 
 		IT6602AudioOutputEnable(0);
-	}
-	else
-	{
-		if (it6602data->m_VState == VSTATE_VideoOn)
-		{
-			if (it6602data->m_RAP_ContentOff == 1)
-			{
+
+	} else {
+		if (it6602data->m_VState == VSTATE_VideoOn) {
+			if (it6602data->m_RAP_ContentOff == 1) {
 				IT6602_ManualVideoTristate(0);
 				IT_INFO("+++++++++++ RAP Content On   +++++++++++++++++\n");
 
@@ -2286,6 +2254,7 @@ void IT66021::IT6602_RAPContentOff(unsigned char bOff)
 #endif
 			}
 		}
+
 		it6602data->m_RAP_ContentOff = 0;
 	}
 }
@@ -2293,33 +2262,30 @@ void IT66021::IT6602_RAPContentOff(unsigned char bOff)
 void IT66021::IT6602_SetVideoMute(struct it6602_dev_data *it6602, unsigned char bMute)
 {
 
-	if (bMute)
-	{
+	if (bMute) {
 		//******** AV Mute -> ON ********//
-		hdmirxset(REG_RX_053, (B_VDGatting | B_VIOSel), (B_VDGatting | B_VIOSel)); //Reg53[7][5] = 11    // for enable B_VDIO_GATTING and VIO_SEL
+		hdmirxset(REG_RX_053, (B_VDGatting | B_VIOSel),
+			  (B_VDGatting | B_VIOSel)); //Reg53[7][5] = 11    // for enable B_VDIO_GATTING and VIO_SEL
 		hdmirxset(REG_RX_052, (B_DisVAutoMute), (B_DisVAutoMute));				   //Reg52[5] = 1 for disable Auto video MUTE
 		hdmirxset(REG_RX_053, (B_TriVDIO), (0x00));								   //Reg53[2:0] = 000;         // 0 for enable video io data output
 
 		IT_INFO("+++++++++++ IT6602_SetVideoMute -> On +++++++++++++++++\n");
-	}
-	else
-	{
-		if (it6602->m_VState == VSTATE_VideoOn)
-		{
+
+	} else {
+		if (it6602->m_VState == VSTATE_VideoOn) {
 			//******** AV Mute -> OFF ********//
 			hdmirxset(REG_RX_053, (B_TriSYNC), (0x00)); //Reg53[0] = 0;                 // for enable video sync
 			hdmirxset(REG_RX_053, (B_TriVDIO), (0x00)); //Reg53[3:1] = 000;         // 0 for enable video io data output
 
-			if (CheckAVMute() == TRUE)
-			{
+			if (CheckAVMute() == TRUE) {
 				hdmirxset(REG_RX_052, (B_DisVAutoMute), (B_DisVAutoMute)); //Reg52[5] = 1 for disable Auto video MUTE
-			}
-			else
-			{
+
+			} else {
 				hdmirxset(REG_RX_053, (B_TriVDIO), (B_TriVDIO)); //Reg53[2:0] = 111;         // 1 for enable tri-state of video io data
 				hdmirxset(REG_RX_053, (B_TriVDIO), (0x00));		 //Reg53[2:0] = 000;         // 0 for enable video io data output
 
-				hdmirxset(REG_RX_053, (B_VDGatting | B_VIOSel), (B_VDGatting | B_VIOSel)); //Reg53[7][5] = 11    // for enable B_VDIO_GATTING and VIO_SEL
+				hdmirxset(REG_RX_053, (B_VDGatting | B_VIOSel),
+					  (B_VDGatting | B_VIOSel)); //Reg53[7][5] = 11    // for enable B_VDIO_GATTING and VIO_SEL
 				hdmirxset(REG_RX_053, (B_VDGatting | B_VIOSel), (B_VIOSel));			   //Reg53[7][5] = 01    // for disable B_VDIO_GATTING
 
 				IT_INFO("+++++++++++  IT6602_SetVideoMute -> Off +++++++++++++++++\n");
@@ -2331,94 +2297,88 @@ void IT66021::IT6602_SetVideoMute(struct it6602_dev_data *it6602, unsigned char
 void IT66021::IT6602VideoOutputEnable(unsigned char bEnableOutput)
 {
 	//	struct it6602_dev_data *it6602data = get_it6602_dev_data();
-	if (bEnableOutput)
-	{
+	if (bEnableOutput) {
 		hdmirxset(REG_RX_053, (B_TriSYNC | B_TriVDIO), (0x00));
 		IT_INFO("---------------- IT6602VideoOutputEnable -> On ----------------\n");
 
-	#if defined(_IT66023_)
-			IT66023JudgeOutputMode();
-	#endif
-	}
-	else
-	{
+#if defined(_IT66023_)
+		IT66023JudgeOutputMode();
+#endif
+
+	} else {
 		hdmirxset(REG_RX_053, (B_TriSYNC | B_TriVDIO), (B_TriSYNC | B_TriVDIO));
 		IT_INFO("---------------- IT6602VideoOutputEnable -> Off ----------------\n");
 
-	#if defined(_IT66023_)
-			hdmirxset(REG_RX_08C, 0x08, 0x00); // Reg8C[3] = 0    // VDIO3en�G//  for disable QA IO
-	#endif
+#if defined(_IT66023_)
+		hdmirxset(REG_RX_08C, 0x08, 0x00); // Reg8C[3] = 0    // VDIO3en�G//  for disable QA IO
+#endif
 	}
 }
 
 void IT66021::IT6602SwitchVideoState(struct it6602_dev_data *it6602, Video_State_Type eNewVState)
 {
 
-	if (it6602->m_VState == eNewVState)
+	if (it6602->m_VState == eNewVState) {
 		return;
+	}
 
 	IT_INFO("@@@ %s\n", VStateStr[(unsigned char)eNewVState]);
 
 	it6602->m_VState = eNewVState;
 
-	switch (it6602->m_VState)
-	{
-		case VSTATE_SWReset:
-		{
+	switch (it6602->m_VState) {
+	case VSTATE_SWReset: {
 			IT6602VideoOutputEnable(FALSE);
-		//FIX_ID_039 xxxxx fix image flick when enable RGB limited / Full range convert
-		#ifdef _AVOID_REDUNDANCE_CSC_
-				it6602->m_Backup_OutputVideoMode = 0xFF;
-				it6602->m_Backup_InputVideoMode = 0xFF;
-		#endif
-		//FIX_ID_039 xxxxx				IT6602_AFE_Rst();
-		#ifdef Enable_IT6602_CEC
-				//xxxxx FIX_ID_022		//Fixed for CEC capacitor issue
-				IT6602_ResetCEC();
-		//xxxxx
-		#endif
+			//FIX_ID_039 xxxxx fix image flick when enable RGB limited / Full range convert
+#ifdef _AVOID_REDUNDANCE_CSC_
+			it6602->m_Backup_OutputVideoMode = 0xFF;
+			it6602->m_Backup_InputVideoMode = 0xFF;
+#endif
+			//FIX_ID_039 xxxxx				IT6602_AFE_Rst();
+#ifdef Enable_IT6602_CEC
+			//xxxxx FIX_ID_022		//Fixed for CEC capacitor issue
+			IT6602_ResetCEC();
+			//xxxxx
+#endif
 		}
 		break;
 
-		case VSTATE_SyncWait:
-		{
+	case VSTATE_SyncWait: {
 			// 1. SCDT off interrupt
 			// 2. VideoMode_Chg interrupt
 			IT6602VideoOutputEnable(FALSE);
-		//FIX_ID_039 xxxxx fix image flick when enable RGB limited / Full range convert
-		#ifdef _AVOID_REDUNDANCE_CSC_
-				it6602->m_Backup_OutputVideoMode = 0xFF;
-				it6602->m_Backup_InputVideoMode = 0xFF;
-		#endif
-				//FIX_ID_039 xxxxx
-				it6602->m_NewAVIInfoFrameF = FALSE;
-				it6602->m_ucDeskew_P0 = 0;
-				it6602->m_ucDeskew_P1 = 0;
-				//it6602->m_ucSCDTOffCount=0;
-
-		#ifdef Enable_Vendor_Specific_packet
-				it6602->f_de3dframe_hdmi = FALSE;
-				hdmirxwr(REG_RX_06A, 0x82);
-		#endif
+			//FIX_ID_039 xxxxx fix image flick when enable RGB limited / Full range convert
+#ifdef _AVOID_REDUNDANCE_CSC_
+			it6602->m_Backup_OutputVideoMode = 0xFF;
+			it6602->m_Backup_InputVideoMode = 0xFF;
+#endif
+			//FIX_ID_039 xxxxx
+			it6602->m_NewAVIInfoFrameF = FALSE;
+			it6602->m_ucDeskew_P0 = 0;
+			it6602->m_ucDeskew_P1 = 0;
+			//it6602->m_ucSCDTOffCount=0;
+
+#ifdef Enable_Vendor_Specific_packet
+			it6602->f_de3dframe_hdmi = FALSE;
+			hdmirxwr(REG_RX_06A, 0x82);
+#endif
 		}
 		break;
 
-		case VSTATE_SyncChecking:
-		{
+	case VSTATE_SyncChecking: {
 			// 1. SCDT on interrupt
 			//AssignVideoVirtualTime(VSATE_CONFIRM_SCDT_COUNT);
 			//AssignVideoTimerTimeout(VSATE_CONFIRM_SCDT_COUNT);
 
 			it6602->m_VideoCountingTimer = VSATE_CONFIRM_SCDT_COUNT;
 
-		#ifdef Enable_Vendor_Specific_packet
-				hdmirxwr(REG_RX_06A, 0x82);
-		#endif
+#ifdef Enable_Vendor_Specific_packet
+			hdmirxwr(REG_RX_06A, 0x82);
+#endif
 		}
 		break;
 
-		case VSTATE_VideoOn:
-		{
+	case VSTATE_VideoOn: {
 			IT6602VideoOutputConfigure(it6602);
 			IT6602VideoOutputEnable(TRUE);
 			IT6602SwitchAudioState(it6602, ASTATE_RequestAudio);
@@ -2430,9 +2390,9 @@ void IT66021::IT6602SwitchVideoState(struct it6602_dev_data *it6602, Video_State
 			// DLOG_Output(1000);
 			hdmirxwr(0x84, 0x8F); //2011/06/17 xxxxx, for enable Rx Chip count
 
-		#ifdef Enable_Vendor_Specific_packet
-				hdmirxwr(REG_RX_06A, 0x81);
-		#endif
+#ifdef Enable_Vendor_Specific_packet
+			hdmirxwr(REG_RX_06A, 0x81);
+#endif
 
 			//FIX_ID_001 xxxxx Add Auto EQ with Manual EQ
 			//	#ifdef _SUPPORT_EQ_ADJUST_
@@ -2444,15 +2404,19 @@ void IT66021::IT6602SwitchVideoState(struct it6602_dev_data *it6602, Video_State
 			it6602->m_ucSCDTOffCount = 0;
 			//xxxxx 2013-0812
 
-	#ifdef _SUPPORT_HDCP_REPEATER_
-	#ifdef _PSEUDO_HDCP_REPEATER_TEST_
+#ifdef _SUPPORT_HDCP_REPEATER_
+#ifdef _PSEUDO_HDCP_REPEATER_TEST_
+
 			// TX_BSTATUS = 0x102;
-			if (m_RxHDCPstatus == 2)
+			if (m_RxHDCPstatus == 2) {
 				ITEHDMI_RxHDCP2ndAuthenticationRequest(TX_KSVList, TX_BKSV, TX_BSTATUS);
-	#endif
-	#endif
+			}
+
+#endif
+#endif
 			break;
 		}
+
 	default:
 		break;
 	}
@@ -2479,41 +2443,47 @@ void IT66021::get_vid_info(void)
 	ucPortSel = hdmirxrd(REG_RX_051) & B_PORT_SEL;
 	rddata = hdmirxrd(0x90);
 
-	if (ucPortSel == F_PORT_SEL_1)
-	{
+	if (ucPortSel == F_PORT_SEL_1) {
 
 		IT_INFO("Reg51[0] = 1 Active Port HDMI \r\n");
 		ucClk = hdmirxrd(REG_RX_092);
-		if (ucClk != 0)
-		{
 
-			if (rddata & 0x04)
+		if (ucClk != 0) {
+
+			if (rddata & 0x04) {
 				ucTMDSClk = 2 * RCLKVALUE * 256 / ucClk;
-			else if (rddata & 0x08)
+
+			} else if (rddata & 0x08) {
 				ucTMDSClk = 4 * RCLKVALUE * 256 / ucClk;
-			else
+
+			} else {
 				ucTMDSClk = RCLKVALUE * 256 / ucClk;
+			}
 
 			IT_INFO(" Port 1 TMDS CLK  = %d \r\n", (int)ucTMDSClk);
 		}
+
 		//IT_INFO(" HDMI Reg92  = %X \r\n",(int) hdmirxrd(0x92));
 		//IT_INFO(" HDMI Reg38  = %X \r\n",(int) hdmirxrd(0x38));
-	}
-	else
-	{
+
+	} else {
 		IT_INFO("Reg51[0] = 0 Active Port MHL \r\n");
 		ucClk = hdmirxrd(REG_RX_091);
-		if (ucClk != 0)
-		{
-			if (rddata & 0x01)
+
+		if (ucClk != 0) {
+			if (rddata & 0x01) {
 				ucTMDSClk = 2 * RCLKVALUE * 256 / ucClk;
-			else if (rddata & 0x02)
+
+			} else if (rddata & 0x02) {
 				ucTMDSClk = 4 * RCLKVALUE * 256 / ucClk;
-			else
+
+			} else {
 				ucTMDSClk = RCLKVALUE * 256 / ucClk;
+			}
 
 			IT_INFO("Port 0 TMDS CLK  = %d \r\n", (int)ucTMDSClk);
 		}
+
 		//IT_INFO(" HDMI Reg91  = %X \r\n",(int) hdmirxrd(0x91));
 		//IT_INFO(" HDMI Reg20  = %X \r\n",(int) hdmirxrd(0x20));
 	}
@@ -2545,9 +2515,9 @@ void IT66021::get_vid_info(void)
 	CurVTiming.VFrontPorch = VFP;
 	CurVTiming.VSyncWidth = VSYNCW;
 	CurVTiming.VBackPorch = VTotal - VActive - VFP - VSYNCW;
-	CurVTiming.ScanMode = (InterLaced)&0x01;
-	CurVTiming.VPolarity = (VSyncPol)&0x01;
-	CurVTiming.HPolarity = (HSyncPol)&0x01;
+	CurVTiming.ScanMode = (InterLaced) & 0x01;
+	CurVTiming.VPolarity = (VSyncPol) & 0x01;
+	CurVTiming.HPolarity = (HSyncPol) & 0x01;
 #endif
 }
 
@@ -2563,20 +2533,21 @@ void IT66021::show_vid_info(void)
 
 	GCP_CD = ((hdmirxrd(0x99) & 0xF0) >> 4);
 
-	switch (GCP_CD)
-	{
+	switch (GCP_CD) {
 	case 5:
 		IT_INFO("I/P ColorDepth = 30 bits per pixel \r\n");
 		InBPC = 10;
 		hdmirxset(0x65, 0x0C, 0x04);
 		OutCD = OUT10B;
 		break;
+
 	case 6:
 		IT_INFO("I/P ColorDepth = 36 bits per pixel \r\n");
 		InBPC = 12;
 		hdmirxset(0x65, 0x0C, 0x08);
 		OutCD = OUT12B;
 		break;
+
 	default:
 		IT_INFO("I/P ColorDepth = 24 bits per pixel \r\n");
 		InBPC = 8;
@@ -2585,14 +2556,15 @@ void IT66021::show_vid_info(void)
 		break;
 	}
 
-	switch (OutCD)
-	{
+	switch (OutCD) {
 	case 1:
 		IT_INFO("O/P ColorDepth = 30 bits per pixel \r\n");
 		break;
+
 	case 2:
 		IT_INFO("O/P ColorDepth = 36 bits per pixel \r\n");
 		break;
+
 	default:
 		IT_INFO("O/P ColorDepth = 24 bits per pixel \r\n");
 		break;
@@ -2602,54 +2574,58 @@ void IT66021::show_vid_info(void)
 	InColorMode = (hdmirxrd(0x15) & 0x60) >> 5;
 	chgbank(0);
 
-	if (InColorMode == 1)
-	{ //YCbCr422
+	if (InColorMode == 1) {
+		//YCbCr422
 		InBPP = InBPC * 2;
-	}
-	else
-	{
+
+	} else {
 		InBPP = InBPC * 3;
 	}
 
 	IT_INFO("InBPP = %d", InBPP);
 
-	switch (InColorMode)
-	{
+	switch (InColorMode) {
 	case 0:
 		IT_INFO("Input Color Mode = RGB444 \n");
 		//		 hdmirxset(0xAE, 0x01, 0x01);
 		//		 defaultrgb();
 		break;
+
 	case 1:
 		IT_INFO("Input Color Mode = YCbCr422\n");
 		//		 hdmirxset(0xAE, 0x01, 0x00);
 		//		 yuv422torgb();
 		break;
+
 	case 2:
 		IT_INFO("Input Color Mode = YCbCr444\n");
 		//		 hdmirxset(0xAE, 0x01, 0x00);
 		//		 yuv444torgb();
 		break;
+
 	default:
 		IT_INFO("Input Color Mode = Reserved !!!\n");
 		break;
 	}
 
 	OutColorMode = (hdmirxrd(0x65) & 0x30) >> 4;
-	switch (OutColorMode)
-	{
+
+	switch (OutColorMode) {
 	case 0:
 		IT_INFO("Output Color Mode = RGB444\n");
 		//		 hdmirxset(0x65, 0x30, 0x00);
 		break;
+
 	case 1:
 		IT_INFO("Output Color Mode = YCbCr422\n");
 		//		 hdmirxset(0x65, 0x30, 0x10);
 		break;
+
 	case 2:
 		IT_INFO("Output Color Mode = YCbCr444\n");
 		//		 hdmirxset(0x65, 0x30, 0x20);
 		break;
+
 	default:
 		IT_INFO("Output Color Mode = Reserved !!!\n");
 		break;
@@ -2670,35 +2646,29 @@ void IT66021::show_vid_info(void)
 	FrameRate /= CurVTiming.HTotal;
 	FrameRate /= CurVTiming.VTotal;
 	IT_INFO("FrameRate = %ld Hz\n", FrameRate);
-	if (CurVTiming.ScanMode == 0)
-	{
+
+	if (CurVTiming.ScanMode == 0) {
 		IT_INFO("ScanMode = Progressive\n");
-	}
-	else
-	{
+
+	} else {
 		IT_INFO("ScanMode = InterLaced\n");
 	}
 
-	if (CurVTiming.VPolarity == 1)
-	{
+	if (CurVTiming.VPolarity == 1) {
 		IT_INFO("VSyncPol = Positive\n");
-	}
-	else
-	{
+
+	} else {
 		IT_INFO("VSyncPol = Negative\n");
 	}
 
-	if (CurVTiming.HPolarity == 1)
-	{
+	if (CurVTiming.HPolarity == 1) {
 		IT_INFO("HSyncPol = Positive\n");
-	}
-	else
-	{
+
+	} else {
 		IT_INFO("HSyncPol = Negative\n");
 	}
 
-	if (((hdmirxrd(0x51) & 0x01)))
-	{
+	if (((hdmirxrd(0x51) & 0x01))) {
 		IT_INFO("Port= 1 ,Reg18=%X ,", (int)hdmirxrd(REG_RX_018));
 		IT_INFO("Reg38=%X, ", (int)hdmirxrd(REG_RX_038));
 		IT_INFO("Reg3E=%X, ", (int)hdmirxrd(REG_RX_03E));
@@ -2714,9 +2684,8 @@ void IT66021::show_vid_info(void)
 		IT_INFO("Rec_R_RS=%X  \n", (int)(hdmirxrd(REG_RX_1DF) & 0x7F));
 		IT_INFO(" Reg1C1  = %X , Reg1C2  = %X\r\n", (int)hdmirxrd(REG_RX_1C1), (int)hdmirxrd(REG_RX_1C2));
 		chgbank(0);
-	}
-	else
-	{
+
+	} else {
 
 		IT_INFO("Port= 0 ,Reg11=%X ,", (int)hdmirxrd(REG_RX_011));
 		IT_INFO("Reg20=%X, ", (int)hdmirxrd(REG_RX_020));
@@ -2751,27 +2720,25 @@ void IT66021::show_vid_info(void)
 #else
 	MHL_Mode = 0;
 #endif
+
 	//FIX_ID_036	xxxxx
-	if (MHL_Mode)
-	{
-		if (MHL_CLK_Mode == 0x02)
-		{
+	if (MHL_Mode) {
+		if (MHL_CLK_Mode == 0x02) {
 			IT_INFO("BUS MODE : MHL PackPixel Mode\n");
-		}	
-		else
-		{
+
+		} else {
 			IT_INFO("BUS MODE : MHL 24 bits Mode\n");
 
 		}
 	}
-	if (IsHDMIMode())
-	{
+
+	if (IsHDMIMode()) {
 		IT_INFO("HDMI/DVI Mode : HDMI \n");
-	}
-	else
-	{
+
+	} else {
 		IT_INFO("HDMI/DVI Mode : DVI \n");
 	}
+
 #endif
 }
 
@@ -2781,106 +2748,97 @@ void IT66021::IT6602VideoHandler(struct it6602_dev_data *it6602)
 {
 	//	unsigned char uc;
 	IT_Delay(500);
-	if (it6602->m_VideoCountingTimer > MS_LOOP)
-	{
+
+	if (it6602->m_VideoCountingTimer > MS_LOOP) {
 		it6602->m_VideoCountingTimer -= MS_LOOP;
-	}
-	else
-	{
+
+	} else {
 		it6602->m_VideoCountingTimer = 0;
 	}
 
 	IT_INFO("it6602->m_VideoCountingTimer = %d", it6602->m_VideoCountingTimer);
 	IT_INFO("it6602->m_VState = %d", it6602->m_VState);
 
-	switch (it6602->m_VState)
-	{
-	case VSTATE_SyncWait:
-	{
-		WaitingForSCDT(it6602);
-		break;
-	}
+	switch (it6602->m_VState) {
+	case VSTATE_SyncWait: {
+			WaitingForSCDT(it6602);
+			break;
+		}
 
-	case VSTATE_SyncChecking:
-	{
-		if (it6602->m_VideoCountingTimer == 0)
-		{
-			IT6602SwitchVideoState(it6602, VSTATE_VideoOn);
+	case VSTATE_SyncChecking: {
+			if (it6602->m_VideoCountingTimer == 0) {
+				IT6602SwitchVideoState(it6602, VSTATE_VideoOn);
+			}
+
+			break;
 		}
-		break;
-	}
 
-	case VSTATE_VideoOn:
-	{
+	case VSTATE_VideoOn: {
 #ifdef _SUPPORT_HDCP_REPEATER_
 #ifdef _PSEUDO_HDCP_REPEATER_TEST_
-		// TX_BSTATUS = 0x102;
-		if (m_RxHDCPstatus == 2)
-			ITEHDMI_RxHDCP2ndAuthenticationRequest(TX_KSVList, TX_BKSV, TX_BSTATUS);
+
+			// TX_BSTATUS = 0x102;
+			if (m_RxHDCPstatus == 2) {
+				ITEHDMI_RxHDCP2ndAuthenticationRequest(TX_KSVList, TX_BKSV, TX_BSTATUS);
+			}
+
 #endif
 #endif
-		if (it6602->m_NewAVIInfoFrameF == TRUE)
-		{
-			if (it6602->m_RxHDCPState != RxHDCP_ModeCheck)
-			{
-				IT6602VideoOutputConfigure(it6602);
-				it6602->m_NewAVIInfoFrameF = FALSE;
+
+			if (it6602->m_NewAVIInfoFrameF == TRUE) {
+				if (it6602->m_RxHDCPState != RxHDCP_ModeCheck) {
+					IT6602VideoOutputConfigure(it6602);
+					it6602->m_NewAVIInfoFrameF = FALSE;
+				}
 			}
-		}
 
-		if (hdmirxrd(REG_RX_053) & B_VDGatting)
-		{
-			//if(IT6602_IsSelectedPort(0)
-			{
-				if ((it6602->m_RAP_ContentOff == 0) && (it6602->m_HDCP_ContentOff == 0))
+			if (hdmirxrd(REG_RX_053) & B_VDGatting) {
+				//if(IT6602_IsSelectedPort(0)
 				{
-					if (CheckAVMute() == FALSE)
-					{
-						IT6602_SetVideoMute(it6602, OFF);
+					if ((it6602->m_RAP_ContentOff == 0) && (it6602->m_HDCP_ContentOff == 0)) {
+						if (CheckAVMute() == FALSE) {
+							IT6602_SetVideoMute(it6602, OFF);
+						}
 					}
 				}
 			}
-		}
 
 #ifdef _FIX_ID_028_
-		if (hdmirxrd(REG_RX_0AA) & 0x80)
-		{
-			//FIX_ID_037 xxxxx //Allion MHL compliance issue !!!
-			if (it6602->m_RAP_ContentOff == 0) //xxxxx 2014-0529 //Manual Content On/Off
-			{
-				if (it6602->m_AState != ASTATE_AudioOn)
-				{
-					it6602->m_AudioCountingTimer = AUDIO_READY_TIMEOUT;
-					it6602->m_AState = ASTATE_AudioOn;
-					m_bAudioWaiting = TRUE;
-				}
-				else
-				{
 
-					if (it6602->m_AudioCountingTimer > MS_LOOP)
-					{
-						it6602->m_AudioCountingTimer -= MS_LOOP;
-					}
-					else
-					{
-						it6602->m_AudioCountingTimer = 0;
-						if (m_bAudioWaiting == TRUE)
-						{
-							IT6602AudioOutputEnable(TRUE);
+			if (hdmirxrd(REG_RX_0AA) & 0x80) {
+				//FIX_ID_037 xxxxx //Allion MHL compliance issue !!!
+				if (it6602->m_RAP_ContentOff == 0) { //xxxxx 2014-0529 //Manual Content On/Off
+					if (it6602->m_AState != ASTATE_AudioOn) {
+						it6602->m_AudioCountingTimer = AUDIO_READY_TIMEOUT;
+						it6602->m_AState = ASTATE_AudioOn;
+						m_bAudioWaiting = TRUE;
+
+					} else {
+
+						if (it6602->m_AudioCountingTimer > MS_LOOP) {
+							it6602->m_AudioCountingTimer -= MS_LOOP;
+
+						} else {
+							it6602->m_AudioCountingTimer = 0;
+
+							if (m_bAudioWaiting == TRUE) {
+								IT6602AudioOutputEnable(TRUE);
+							}
 						}
 					}
+				} //xxxxx 2014-0529
+
+				//FIX_ID_037 xxxxx
+
+			} else {
+				if (it6602->m_AState == ASTATE_AudioOn) {
+					IT6602AudioOutputEnable(FALSE);
 				}
-			} //xxxxx 2014-0529
-			  //FIX_ID_037 xxxxx
-		}
-		else
-		{
-			if (it6602->m_AState == ASTATE_AudioOn)
-				IT6602AudioOutputEnable(FALSE);
-		}
+			}
+
 #endif
-		break;
-	}
+			break;
+		}
 
 	default:
 		break;
@@ -2898,35 +2856,30 @@ void IT66021::hdmirx_INT_5V_Pwr_Chg(struct it6602_dev_data *it6602, unsigned cha
 	IT_INFO("hdmirx_INT_5V_Pwr_Chg: ucPortSel = %d", ucPortSel);
 
 	//FIX_ID_037 xxxxx //Allion MHL compliance issue !!!
-	if (ucPortSel == ucport)
-	{
-		if (CheckPlg5VPwr(ucport) == TRUE)
-		{
+	if (ucPortSel == ucport) {
+		if (CheckPlg5VPwr(ucport) == TRUE) {
 			IT_INFO("#### Power 5V ON ####\r\n");
 			IT6602SwitchVideoState(it6602, VSTATE_SyncWait);
 			it6602HPDCtrl(ucport, 1); // set ucport's HPD = 1
-		}
-		else
-		{
+
+		} else {
 			IT_INFO("#### Power 5V OFF ####\r\n");
 			IT6602SwitchVideoState(it6602, VSTATE_SWReset);
 			it6602HPDCtrl(ucport, 0); // clear ucport's HPD = 0
 		}
-	}
-	else
-	{
-		if (CheckPlg5VPwr(ucport) == FALSE)
-		{
+
+	} else {
+		if (CheckPlg5VPwr(ucport) == FALSE) {
 #ifdef _SUPPORT_AUTO_EQ_
 			DisableOverWriteRS(ucport);
 #endif
 			it6602HPDCtrl(ucport, 0); // clear ucport's HPD = 0
-		}
-		else
-		{
+
+		} else {
 			it6602HPDCtrl(ucport, 1); // set ucport's HPD = 1
 		}
 	}
+
 	//FIX_ID_037 xxxxx
 }
 // ---------------------------------------------------------------------------
@@ -2934,12 +2887,14 @@ void IT66021::hdmirx_INT_P0_ECC(struct it6602_dev_data *it6602)
 {
 	// struct it6602_dev_data *it6602data = get_it6602_dev_data();
 
-	if ((it6602->m_ucEccCount_P0++) > ECC_TIMEOUT)
-	{
+	if ((it6602->m_ucEccCount_P0++) > ECC_TIMEOUT) {
 
 #ifdef _SUPPORT_EQ_ADJUST_
-		if (it6602->EQPort[F_PORT_SEL_0].f_manualEQadjust == TRUE) // ignore ECC interrupt when manual EQ adjust !!!
+
+		if (it6602->EQPort[F_PORT_SEL_0].f_manualEQadjust == TRUE) { // ignore ECC interrupt when manual EQ adjust !!!
 			return;
+		}
+
 #endif
 
 		it6602->m_ucEccCount_P0 = 0;
@@ -2954,11 +2909,13 @@ void IT66021::hdmirx_INT_P0_ECC(struct it6602_dev_data *it6602)
 void IT66021::hdmirx_INT_P1_ECC(struct it6602_dev_data *it6602)
 {
 
-	if ((it6602->m_ucEccCount_P1++) > ECC_TIMEOUT)
-	{
+	if ((it6602->m_ucEccCount_P1++) > ECC_TIMEOUT) {
 #ifdef _SUPPORT_EQ_ADJUST_
-		if (it6602->EQPort[F_PORT_SEL_1].f_manualEQadjust == TRUE) // ignore ECC interrupt when manual EQ adjust !!!
+
+		if (it6602->EQPort[F_PORT_SEL_1].f_manualEQadjust == TRUE) { // ignore ECC interrupt when manual EQ adjust !!!
 			return;
+		}
+
 #endif
 
 		it6602->m_ucEccCount_P1 = 0;
@@ -2973,41 +2930,49 @@ void IT66021::hdmirx_INT_P0_Deskew(struct it6602_dev_data *it6602)
 {
 	IT_INFO("m_ucDeskew_P0 = %d", it6602->m_ucDeskew_P0);
 
-	if ((it6602->m_ucDeskew_P0++) > DESKEW_TIMEOUT)
-	{
+	if ((it6602->m_ucDeskew_P0++) > DESKEW_TIMEOUT) {
 #ifdef _SUPPORT_EQ_ADJUST_
-		if (it6602->EQPort[F_PORT_SEL_0].f_manualEQadjust == TRUE) // ignore ECC interrupt when manual EQ adjust !!!
+
+		if (it6602->EQPort[F_PORT_SEL_0].f_manualEQadjust == TRUE) { // ignore ECC interrupt when manual EQ adjust !!!
 			return;
+		}
+
 #endif
 		it6602->m_ucDeskew_P0 = 0;
 
 		IT_INFO("CDR reset for Port0 DESKEW_TIMEOUT !!!\r\n");
 
-		if (hdmirxrd(REG_RX_020) == 0x00)
-			hdmirxwr(REG_RX_020, 0x3F); // Dr. Liu suggestion to 0x00
-		else
-			hdmirxwr(REG_RX_020, 0x00); // Dr. Liu suggestion to 0x3F
+		if (hdmirxrd(REG_RX_020) == 0x00) {
+			hdmirxwr(REG_RX_020, 0x3F);        // Dr. Liu suggestion to 0x00
+
+		} else {
+			hdmirxwr(REG_RX_020, 0x00);        // Dr. Liu suggestion to 0x3F
+		}
 	}
 }
 
 // ---------------------------------------------------------------------------
 void IT66021::hdmirx_INT_P1_Deskew(struct it6602_dev_data *it6602)
 {
-	if ((it6602->m_ucDeskew_P1++) > DESKEW_TIMEOUT)
-	{
+	if ((it6602->m_ucDeskew_P1++) > DESKEW_TIMEOUT) {
 #ifdef _SUPPORT_EQ_ADJUST_
-		if (it6602->EQPort[F_PORT_SEL_1].f_manualEQadjust == TRUE) // ignore ECC interrupt when manual EQ adjust !!!
+
+		if (it6602->EQPort[F_PORT_SEL_1].f_manualEQadjust == TRUE) { // ignore ECC interrupt when manual EQ adjust !!!
 			return;
+		}
+
 #endif
 
 		it6602->m_ucDeskew_P1 = 0;
 
 		IT_INFO("CDR reset for Port1 DESKEW_TIMEOUT !!!\r\n");
 
-		if (hdmirxrd(REG_RX_038) == 0x00)
-			hdmirxwr(REG_RX_038, 0x3F); // Dr. Liu suggestion to 0x00
-		else
-			hdmirxwr(REG_RX_038, 0x00); // Dr. Liu suggestion to 0x3F
+		if (hdmirxrd(REG_RX_038) == 0x00) {
+			hdmirxwr(REG_RX_038, 0x3F);        // Dr. Liu suggestion to 0x00
+
+		} else {
+			hdmirxwr(REG_RX_038, 0x00);        // Dr. Liu suggestion to 0x3F
+		}
 	}
 }
 
@@ -3017,28 +2982,26 @@ void IT66021::hdmirx_INT_HDMIMode_Chg(struct it6602_dev_data *it6602, unsigned c
 	ucPortSel = hdmirxrd(REG_RX_051) & B_PORT_SEL;
 	IT_INFO("hdmirx_INT_HDMIMode_Chg = %d", ucPortSel);
 
-	if (ucPortSel != ucport)
-	{
+	if (ucPortSel != ucport) {
 		return;
 	}
 
-	if (IsHDMIMode())
-	{
-		if (it6602->m_VState == VSTATE_VideoOn)
-		{
+	if (IsHDMIMode()) {
+		if (it6602->m_VState == VSTATE_VideoOn) {
 			IT6602SwitchAudioState(it6602, ASTATE_RequestAudio);
 		}
+
 		it6602->m_bUpHDMIMode = TRUE;
 		IT_INFO("#### HDMI/DVI Mode : HDMI ####\r\n");
-	}
-	else
-	{
+
+	} else {
 		IT6602SwitchAudioState(it6602, ASTATE_AudioOff);
 		it6602->m_NewAVIInfoFrameF = FALSE;
-		if (it6602->m_VState == VSTATE_VideoOn)
-		{
+
+		if (it6602->m_VState == VSTATE_VideoOn) {
 			SetDVIVideoOutput(it6602);
 		}
+
 		it6602->m_bUpHDMIMode = FALSE;
 		IT_INFO("#### HDMI/DVI Mode : DVI ####\r\n");
 	}
@@ -3046,13 +3009,11 @@ void IT66021::hdmirx_INT_HDMIMode_Chg(struct it6602_dev_data *it6602, unsigned c
 
 void IT66021::hdmirx_INT_SCDT_Chg(struct it6602_dev_data *it6602)
 {
-	if (CheckSCDT(it6602) == TRUE)
-	{
+	if (CheckSCDT(it6602) == TRUE) {
 		IT_INFO("#### SCDT ON ####\r\n");
 		IT6602SwitchVideoState(it6602, VSTATE_SyncChecking);
-	}
-	else
-	{
+
+	} else {
 		IT_INFO("#### SCDT OFF ####\r\n");
 		IT6602SwitchVideoState(it6602, VSTATE_SyncWait);
 		IT6602SwitchAudioState(it6602, ASTATE_AudioOff);
@@ -3062,98 +3023,88 @@ void IT66021::hdmirx_INT_SCDT_Chg(struct it6602_dev_data *it6602)
 #ifdef _SUPPORT_AUTO_EQ_
 void IT66021::hdmirx_INT_EQ_FAIL(struct it6602_dev_data *it6602, unsigned char ucPortSel)
 {
-	if (ucPortSel > F_PORT_SEL_1)
+	if (ucPortSel > F_PORT_SEL_1) {
 		return;
+	}
 
 #ifdef _SUPPORT_EQ_ADJUST_
+
 	if (it6602->EQPort[ucPortSel].f_manualEQadjust == FALSE) // ignore EQ fail interrupt when manual EQ adjust !!!
 #endif
 	{
-		if (CheckPlg5VPwr(ucPortSel))
-		{
+		if (CheckPlg5VPwr(ucPortSel)) {
 
 			//07-08
-			if (ucPortSel == 0)
-			{
-				if ((it6602->HDMIIntEvent & (B_PORT0_TMDSEvent)))
-				{
+			if (ucPortSel == 0) {
+				if ((it6602->HDMIIntEvent & (B_PORT0_TMDSEvent))) {
 					IT_INFO("#### hdmirx_INT_EQ_FAIL not yet !!! ####\r\n");
+
 					//FIX_ID_033 xxxxx  //Fine-tune EQ Adjust function for HDCP receiver and repeater mode
-					if ((it6602->HDMIIntEvent & (B_PORT0_Waiting)) == 0)
-					{
+					if ((it6602->HDMIIntEvent & (B_PORT0_Waiting)) == 0) {
 						hdmirxwr(REG_RX_022, 0x00); // power down auto EQ
 						it6602->HDMIIntEvent |= (B_PORT0_Waiting);
 						it6602->HDMIIntEvent |= (B_PORT0_TMDSEvent);
 						it6602->HDMIWaitNo[0] = MAX_TMDS_WAITNO;
-					}
-					else if ((it6602->HDMIIntEvent & (B_PORT0_TMDSEvent)))
-					{
+
+					} else if ((it6602->HDMIIntEvent & (B_PORT0_TMDSEvent))) {
 						it6602->HDMIIntEvent |= (B_PORT0_Waiting);
 						it6602->HDMIWaitNo[0] += MAX_HDCP_WAITNO;
 					}
+
 					return;
 				}
 
-				if (hdmirxrd(REG_RX_P0_SYS_STATUS) & (B_P0_MHL_MODE))
-				{
-					if ((ucPortAMPValid[0] & 0x03) != 0x03)
-					{
+				if (hdmirxrd(REG_RX_P0_SYS_STATUS) & (B_P0_MHL_MODE)) {
+					if ((ucPortAMPValid[0] & 0x03) != 0x03) {
 						AmpValidCheck(ucPortSel);
 					}
-				}
-				else
-				{
-					if ((ucPortAMPValid[ucPortSel] & 0x3F) != 0x3F)
-					{
+
+				} else {
+					if ((ucPortAMPValid[ucPortSel] & 0x3F) != 0x3F) {
 						AmpValidCheck(ucPortSel);
 					}
 				}
-			}
-			else
-			{
-				if ((it6602->HDMIIntEvent & (B_PORT1_TMDSEvent)))
-				{
+
+			} else {
+				if ((it6602->HDMIIntEvent & (B_PORT1_TMDSEvent))) {
 					IT_INFO("#### hdmirx_INT_EQ_FAIL not yet !!! ####\r\n");
 
-					if ((it6602->HDMIIntEvent & (B_PORT1_Waiting)) == 0)
-					{
+					if ((it6602->HDMIIntEvent & (B_PORT1_Waiting)) == 0) {
 						hdmirxwr(REG_RX_03A, 0x00); // power down auto EQ
 						it6602->HDMIIntEvent |= (B_PORT1_Waiting);
 						it6602->HDMIIntEvent |= (B_PORT1_TMDSEvent);
 						it6602->HDMIWaitNo[1] = MAX_TMDS_WAITNO;
-					}
-					else if ((it6602->HDMIIntEvent & (B_PORT1_TMDSEvent)))
-					{
+
+					} else if ((it6602->HDMIIntEvent & (B_PORT1_TMDSEvent))) {
 						it6602->HDMIIntEvent |= (B_PORT1_Waiting);
 						it6602->HDMIWaitNo[1] += MAX_HDCP_WAITNO;
 					}
+
 					return;
 				}
 
-				if ((ucPortAMPValid[ucPortSel] & 0x3F) != 0x3F)
-				{
+				if ((ucPortAMPValid[ucPortSel] & 0x3F) != 0x3F) {
 					AmpValidCheck(ucPortSel);
 				}
 			}
 
 			{
-				if (ucPortSel == 0)
-				{
-					if (hdmirxrd(REG_RX_P0_SYS_STATUS) & (B_P0_MHL_MODE))
-					{
-						if ((ucPortAMPValid[0] & 0x03) != 0x03)
+				if (ucPortSel == 0) {
+					if (hdmirxrd(REG_RX_P0_SYS_STATUS) & (B_P0_MHL_MODE)) {
+						if ((ucPortAMPValid[0] & 0x03) != 0x03) {
 							TogglePolarity(ucPortSel);
-					}
-					else
-					{
-						if ((ucPortAMPValid[ucPortSel] & 0x3F) != 0x3F)
+						}
+
+					} else {
+						if ((ucPortAMPValid[ucPortSel] & 0x3F) != 0x3F) {
 							TogglePolarity(ucPortSel);
+						}
 					}
-				}
-				else
-				{
-					if ((ucPortAMPValid[ucPortSel] & 0x3F) != 0x3F)
+
+				} else {
+					if ((ucPortAMPValid[ucPortSel] & 0x3F) != 0x3F) {
 						TogglePolarity(ucPortSel);
+					}
 				}
 			}
 		}
@@ -3170,26 +3121,23 @@ unsigned char IT66021::UpdateEDIDRAM(unsigned char *pEDID, unsigned char BlockNU
 {
 	unsigned char i, offset, sum = 0;
 
-	if (BlockNUM == 0x02)
-	{
+	if (BlockNUM == 0x02) {
 		offset = 0x00 + 128 * 0x01;
-	}	
-	else
-	{
+
+	} else {
 		offset = 0x00 + 128 * BlockNUM;
 	}
 
 	IT_INFO("block No =%02X offset = %02X \n", (int)BlockNUM, (int)offset);
 
-	for (i = 0; i < 0x7F; i++)
-	{
+	for (i = 0; i < 0x7F; i++) {
 		EDID_RAM_Write(offset, 1, pEDID + offset);
 
 		// IT_INFO("%02X ", (int)*(pEDID + offset));
 		sum += *(pEDID + offset);
 		offset++;
 	}
-	
+
 	sum = 0x00 - sum;
 
 	return sum;
@@ -3216,35 +3164,32 @@ void IT66021::EDIDRAMInitial(unsigned char *pIT6602EDID)
 	unsigned char u8_VSDB_Addr;
 	unsigned char BlockNo;
 
-	u8_VSDB_Addr=0;
+	u8_VSDB_Addr = 0;
 
 	EnableEDIDupdata();
 
-	for(BlockNo=0;BlockNo<2;BlockNo++){
+	for (BlockNo = 0; BlockNo < 2; BlockNo++) {
 
 		IT_INFO("IT6602 EDIDRAMInitial = %02X\n", (int) BlockNo);
 
-		if(BlockNo==0)
-		{
-			Block0_CheckSum =  UpdateEDIDRAM(pIT6602EDID,0);
-			hdmirxwr(REG_RX_0C4,Block0_CheckSum);		//Port 0 Bank 0 CheckSum
-			hdmirxwr(REG_RX_0C8,Block0_CheckSum);		//Port 1 Bank 0 CheckSum
+		if (BlockNo == 0) {
+			Block0_CheckSum =  UpdateEDIDRAM(pIT6602EDID, 0);
+			hdmirxwr(REG_RX_0C4, Block0_CheckSum);		//Port 0 Bank 0 CheckSum
+			hdmirxwr(REG_RX_0C8, Block0_CheckSum);		//Port 1 Bank 0 CheckSum
 
 			IT_INFO(" Block0_CheckSum = %02X\n", (int) Block0_CheckSum);
-		}
-		else
-		{
-			Block1_CheckSum =  UpdateEDIDRAM(pIT6602EDID,1);
+
+		} else {
+			Block1_CheckSum =  UpdateEDIDRAM(pIT6602EDID, 1);
 			IT_INFO(" Block1_CheckSum = %02X\n", (int) Block1_CheckSum);
-			u8_VSDB_Addr=Find_Phyaddress_Location(pIT6602EDID,1);
+			u8_VSDB_Addr = Find_Phyaddress_Location(pIT6602EDID, 1);
 
 			IT_INFO("u8_VSDB_Addr = %02X\n", (int) u8_VSDB_Addr);
 			PhyAdrSet();
 
-			if(u8_VSDB_Addr!=0)
-			{
+			if (u8_VSDB_Addr != 0) {
 
-				UpdateEDIDReg(u8_VSDB_Addr, pIT6602EDID[u8_VSDB_Addr],pIT6602EDID[u8_VSDB_Addr+1], Block1_CheckSum);
+				UpdateEDIDReg(u8_VSDB_Addr, pIT6602EDID[u8_VSDB_Addr], pIT6602EDID[u8_VSDB_Addr + 1], Block1_CheckSum);
 				IT_INFO("EDID Parsing OK\n");
 			}
 		}
@@ -3258,92 +3203,97 @@ unsigned char IT66021:: Find_Phyaddress_Location(unsigned char *pEDID, unsigned
 {
 	unsigned char AddStart;
 	unsigned char tag, count;
-	unsigned char offset,End;
+	unsigned char offset, End;
 	unsigned char u8_VSDB_Addr;
 
-	#ifdef FIX_ID_013_
+#ifdef FIX_ID_013_
 	//FIX_ID_013	xxxxx	//For MSC 3D request issue
-		unsigned char u8_3DPresent_Addr;
-		unsigned char ucTemp;
-		struct PARSE3D_STR *pstParse3D = get_EDID_VSDB_3Ddata();
+	unsigned char u8_3DPresent_Addr;
+	unsigned char ucTemp;
+	struct PARSE3D_STR *pstParse3D = get_EDID_VSDB_3Ddata();
 	//FIX_ID_013	xxxxx
-	#endif //FIX_ID_013
+#endif //FIX_ID_013
+
+	if (Block_Number == 0x02) {
+		AddStart = 0x00 + 128 * 0x01;
 
-	if ( Block_Number == 0x02 )
-		AddStart = 0x00+128*0x01;
-	else
-		AddStart = 0x00+128*Block_Number;
+	} else {
+		AddStart = 0x00 + 128 * Block_Number;
+	}
 
-	if((*(pEDID+AddStart))!=0x2 || (*(pEDID+AddStart+1))!=0x3)
+	if ((*(pEDID + AddStart)) != 0x2 || (*(pEDID + AddStart + 1)) != 0x3) {
 		return 0;
-	End = (*(pEDID+AddStart+2));
-	u8_VSDB_Addr=0;
+	}
+
+	End = (*(pEDID + AddStart + 2));
+	u8_VSDB_Addr = 0;
 
-	#ifdef FIX_ID_013_
+#ifdef FIX_ID_013_
 	//FIX_ID_013	xxxxx	//For MSC 3D request issue
-		// initial value then check with SVD and VSDB block to find the SVD of 3D support timing
-		pstParse3D->bVSDBspport3D = 0x00;
-		pstParse3D->ucVicCnt=0;
+	// initial value then check with SVD and VSDB block to find the SVD of 3D support timing
+	pstParse3D->bVSDBspport3D = 0x00;
+	pstParse3D->ucVicCnt = 0;
 	//FIX_ID_013	xxxxx
-	#endif //FIX_ID_013
+#endif //FIX_ID_013
 
-	for(offset=(AddStart+0x04);offset<(AddStart+End); )
-	{
+	for (offset = (AddStart + 0x04); offset < (AddStart + End);) {
 
 
-		tag=(*(pEDID+offset))>>5;
-		count=(*(pEDID+offset)) & 0x1f;
+		tag = (*(pEDID + offset)) >> 5;
+		count = (*(pEDID + offset)) & 0x1f;
 
 		//#ifdef printf_EDID
-		IT_INFO("offset = %X , Tag = %X , count =%X \n", (int) offset,(int)  tag, (int) count);
+		IT_INFO("offset = %X , Tag = %X , count =%X \n", (int) offset, (int)  tag, (int) count);
 		//#endif
 
 		offset++;
-	if(tag==0x03)	// HDMI VSDB Block of EDID
-        {
-        	//#ifdef printf_EDID
-	        	IT_INFO("HDMI VSDB Block address = %X\n",(int)  offset);
-        	//#endif
-
-			if(	(*(pEDID+offset  ))==0x03 &&
-				(*(pEDID+offset+1))==0x0C &&
-				(*(pEDID+offset+2))==0x0    )
-			{
-				u8_VSDB_Addr=offset+3;
-				txphyadr[0]=(*(pEDID+offset+3));
-				txphyadr[1]=(*(pEDID+offset+4));
+
+		if (tag == 0x03) {	// HDMI VSDB Block of EDID
+			//#ifdef printf_EDID
+			IT_INFO("HDMI VSDB Block address = %X\n", (int)  offset);
+			//#endif
+
+			if ((*(pEDID + offset)) == 0x03 &&
+			    (*(pEDID + offset + 1)) == 0x0C &&
+			    (*(pEDID + offset + 2)) == 0x0) {
+				u8_VSDB_Addr = offset + 3;
+				txphyadr[0] = (*(pEDID + offset + 3));
+				txphyadr[1] = (*(pEDID + offset + 4));
 				//#ifdef printf_EDID
-				IT_INFO("txphyadr[0] = %X\n",(int)  txphyadr[0]);
-				IT_INFO("txphyadr[1] = %X\n",(int)  txphyadr[1]);
+				IT_INFO("txphyadr[0] = %X\n", (int)  txphyadr[0]);
+				IT_INFO("txphyadr[1] = %X\n", (int)  txphyadr[1]);
 				//#endif
 
-	#ifdef FIX_ID_013_
-	//FIX_ID_013	xxxxx	//For MSC 3D request issue
+#ifdef FIX_ID_013_
+				//FIX_ID_013	xxxxx	//For MSC 3D request issue
 
-					if(count < 7)		// no 3D support !!!
-						return u8_VSDB_Addr;
+				if (count < 7) {	// no 3D support !!!
+					return u8_VSDB_Addr;
+				}
 
-					u8_3DPresent_Addr = offset+7;
+				u8_3DPresent_Addr = offset + 7;
 
-					ucTemp = *(pEDID+offset+7);
+				ucTemp = *(pEDID + offset + 7);
 
-					if(ucTemp & 0x80)				// Video and Audio Latency present
-						u8_3DPresent_Addr += 2;
+				if (ucTemp & 0x80) {			// Video and Audio Latency present
+					u8_3DPresent_Addr += 2;
+				}
 
-					if(ucTemp & 0x40) 			// Interlaced Video and Audio Latency present
-						u8_3DPresent_Addr += 2;
+				if (ucTemp & 0x40) {		// Interlaced Video and Audio Latency present
+					u8_3DPresent_Addr += 2;
+				}
 
-					if(ucTemp & 0x20)				// HDMI additional video format present
-					{
-						u8_3DPresent_Addr++;
-					}
-					pstParse3D->uc3DEdidStart = u8_3DPresent_Addr;
+				if (ucTemp & 0x20) {			// HDMI additional video format present
+					u8_3DPresent_Addr++;
+				}
 
-					pstParse3D->uc3DBlock = Block_Number;
+				pstParse3D->uc3DEdidStart = u8_3DPresent_Addr;
 
-					pstParse3D->bVSDBspport3D = 0x01;		// for identify the HDMI VSDB 3D support
-	//FIX_ID_013	xxxxx
-	#endif //FIX_ID_013
+				pstParse3D->uc3DBlock = Block_Number;
+
+				pstParse3D->bVSDBspport3D = 0x01;		// for identify the HDMI VSDB 3D support
+				//FIX_ID_013	xxxxx
+#endif //FIX_ID_013
 				return u8_VSDB_Addr;
 			}
 		}
@@ -3351,55 +3301,56 @@ unsigned char IT66021:: Find_Phyaddress_Location(unsigned char *pEDID, unsigned
 #ifdef FIX_ID_013_
 //FIX_ID_013	xxxxx	//For MSC 3D request issue
 
-	        if(tag==0x02)	// Short Video Descriptor of EDID
-       	 {
-	        	//#ifdef printf_EDID
-	        	IT_INFO("Short Video Descriptor Address = %X, VIC count = %X \r\n",(int)  offset,(int) count);
-	        	//#endif
+		if (tag == 0x02) {	// Short Video Descriptor of EDID
+			//#ifdef printf_EDID
+			IT_INFO("Short Video Descriptor Address = %X, VIC count = %X \r\n", (int)  offset, (int) count);
+			//#endif
 
 			// get the SVD size
 			pstParse3D->ucVicCnt = count;
 
-			for(ucTemp=0;ucTemp<count;ucTemp++)
-			{
-				u8_3DPresent_Addr = (*(pEDID+offset+ucTemp) ) & 0x7F;
+			for (ucTemp = 0; ucTemp < count; ucTemp++) {
+				u8_3DPresent_Addr = (*(pEDID + offset + ucTemp)) & 0x7F;
 				SVD_LIST[ucTemp] = u8_3DPresent_Addr;
-				IT_INFO("SVD[%X] = %X\n", ucTemp,u8_3DPresent_Addr);
+				IT_INFO("SVD[%X] = %X\n", ucTemp, u8_3DPresent_Addr);
 			}
-		 }
+		}
+
 //FIX_ID_013	xxxxx
 #endif //FIX_ID_013
 
-		offset=offset+count;
+		offset = offset + count;
 	}
-    return 0;
+
+	return 0;
 }
 
-void IT66021::UpdateEDIDReg(unsigned char u8_VSDB_Addr, unsigned char CEC_AB, unsigned char CEC_CD, unsigned char Block1_CheckSum)
+void IT66021::UpdateEDIDReg(unsigned char u8_VSDB_Addr, unsigned char CEC_AB, unsigned char CEC_CD,
+			    unsigned char Block1_CheckSum)
 {
 
-    unsigned char  A_Addr_AB, A_Addr_CD, A_Block1_CheckSum;
-    unsigned char  B_Addr_AB, B_Addr_CD, B_Block1_CheckSum;
+	unsigned char  A_Addr_AB, A_Addr_CD, A_Block1_CheckSum;
+	unsigned char  B_Addr_AB, B_Addr_CD, B_Block1_CheckSum;
 
-	A_Addr_AB=rxphyadr[0][0];
-	A_Addr_CD=rxphyadr[0][1];
+	A_Addr_AB = rxphyadr[0][0];
+	A_Addr_CD = rxphyadr[0][1];
 
-	B_Addr_AB=rxphyadr[1][0];
-	B_Addr_CD=rxphyadr[1][1];
+	B_Addr_AB = rxphyadr[1][0];
+	B_Addr_CD = rxphyadr[1][1];
 
 
-	A_Block1_CheckSum=(Block1_CheckSum+CEC_AB+CEC_CD -A_Addr_AB-A_Addr_CD)%0x100;
-	B_Block1_CheckSum=(Block1_CheckSum+CEC_AB+CEC_CD -B_Addr_AB-B_Addr_CD)%0x100;
+	A_Block1_CheckSum = (Block1_CheckSum + CEC_AB + CEC_CD - A_Addr_AB - A_Addr_CD) % 0x100;
+	B_Block1_CheckSum = (Block1_CheckSum + CEC_AB + CEC_CD - B_Addr_AB - B_Addr_CD) % 0x100;
 
 
-	hdmirxwr(REG_RX_0C1,u8_VSDB_Addr);			//VSDB Start Address
-	hdmirxwr(REG_RX_0C2,A_Addr_AB);					//Port 0 AB
-	hdmirxwr(REG_RX_0C3,A_Addr_CD);				//Port 0 CD
-	hdmirxwr(REG_RX_0C5,A_Block1_CheckSum);		//Port 0 Bank 1 CheckSum
+	hdmirxwr(REG_RX_0C1, u8_VSDB_Addr);			//VSDB Start Address
+	hdmirxwr(REG_RX_0C2, A_Addr_AB);					//Port 0 AB
+	hdmirxwr(REG_RX_0C3, A_Addr_CD);				//Port 0 CD
+	hdmirxwr(REG_RX_0C5, A_Block1_CheckSum);		//Port 0 Bank 1 CheckSum
 
-	hdmirxwr(REG_RX_0C6,B_Addr_AB);					//Port 1 AB
-	hdmirxwr(REG_RX_0C7,B_Addr_CD);				//Port 1 CD
-	hdmirxwr(REG_RX_0C9,B_Block1_CheckSum);		//Port 1 Bank 1 CheckSum
+	hdmirxwr(REG_RX_0C6, B_Addr_AB);					//Port 1 AB
+	hdmirxwr(REG_RX_0C7, B_Addr_CD);				//Port 1 CD
+	hdmirxwr(REG_RX_0C9, B_Block1_CheckSum);		//Port 1 Bank 1 CheckSum
 }
 
 void IT66021::PhyAdrSet(void)
@@ -3496,138 +3447,131 @@ void IT66021::IT6602HDMIInterruptHandler(struct it6602_dev_data *it6602)
 	IT_INFO("ClearReg0A = %X", (int)ClearReg0Ah);
 	IT_INFO("ClearRegD0 = %X", (int)ClearRegD0h);
 
-	if (Reg05h != 0x00)
-	{
+	if (Reg05h != 0x00) {
 		IT_INFO("Reg05 = 0x%x \r\n", (int)Reg05h);
-		if (Reg05h & 0x80)
-		{
+
+		if (Reg05h & 0x80) {
 			IT_INFO("#### Port 0 HDCP Off Detected ###\r\n");
 			it6602->m_ucEccCount_P0 = 0;
 		}
 
-		if (Reg05h & 0x40)
-		{
+		if (Reg05h & 0x40) {
 			IT_INFO("#### Port 0 ECC Error %X ####\r\n", (int)(it6602->m_ucEccCount_P0));
 			//	HDMICheckErrorCount(&(it6602->EQPort[F_PORT_SEL_0]));	//07-04 for port 0
 			hdmirx_INT_P0_ECC(it6602);
 		}
 
-		if (Reg05h & 0x20)
-		{
+		if (Reg05h & 0x20) {
 
 			IT_INFO("#### Port 0 HDMI/DVI Mode change ####\r\n");
-			if (CLKCheck(0))
+
+			if (CLKCheck(0)) {
 				hdmirx_INT_HDMIMode_Chg(it6602, 0);
+			}
 		}
 
-		if (Reg05h & 0x08)
-		{
+		if (Reg05h & 0x08) {
 			IT_INFO("#### Port 0 HDCP Authentication Start ####\r\n");
 			it6602->m_ucEccCount_P0 = 0;
 
-			#ifdef _SUPPORT_HDCP_REPEATER_
-				if (m_bHDCPrepeater == TRUE)
-				{
-					ITEHDMI_RxHDCPRepeaterCapabilityClear(B_KSV_READY);
-					ITEHDMI_Event_Notify_Callback(eAKSV_WRITTEN_NOTIFY);
-					//RxAuthStartInt();
-					//bEnableAuth = TRUE ;
-				}
-			#endif
+#ifdef _SUPPORT_HDCP_REPEATER_
 
-			#ifdef _SUPPORT_AUTO_EQ_
-				if (ucPortAMPOverWrite[F_PORT_SEL_0] == 0)
-				{
-					if ((it6602->HDMIIntEvent & (B_PORT0_Waiting)) == 0)
-					{
-						hdmirxwr(REG_RX_022, 0x00); // power down auto EQ
+			if (m_bHDCPrepeater == TRUE) {
+				ITEHDMI_RxHDCPRepeaterCapabilityClear(B_KSV_READY);
+				ITEHDMI_Event_Notify_Callback(eAKSV_WRITTEN_NOTIFY);
+				//RxAuthStartInt();
+				//bEnableAuth = TRUE ;
+			}
 
-						it6602->HDMIIntEvent |= (B_PORT0_Waiting);
-						it6602->HDMIIntEvent |= (B_PORT0_TMDSEvent);
-						it6602->HDMIWaitNo[0] = MAX_TMDS_WAITNO;
-					}
-					else if ((it6602->HDMIIntEvent & (B_PORT0_TMDSEvent)))
-					{
-						it6602->HDMIIntEvent |= (B_PORT0_Waiting);
-						it6602->HDMIWaitNo[0] += MAX_HDCP_WAITNO;
-					}
+#endif
+
+#ifdef _SUPPORT_AUTO_EQ_
+
+			if (ucPortAMPOverWrite[F_PORT_SEL_0] == 0) {
+				if ((it6602->HDMIIntEvent & (B_PORT0_Waiting)) == 0) {
+					hdmirxwr(REG_RX_022, 0x00); // power down auto EQ
+
+					it6602->HDMIIntEvent |= (B_PORT0_Waiting);
+					it6602->HDMIIntEvent |= (B_PORT0_TMDSEvent);
+					it6602->HDMIWaitNo[0] = MAX_TMDS_WAITNO;
+
+				} else if ((it6602->HDMIIntEvent & (B_PORT0_TMDSEvent))) {
+					it6602->HDMIIntEvent |= (B_PORT0_Waiting);
+					it6602->HDMIWaitNo[0] += MAX_HDCP_WAITNO;
 				}
-				else
-				{
-					if ((it6602->HDMIIntEvent & (B_PORT0_TMDSEvent)))
-					{
-						it6602->HDMIIntEvent |= (B_PORT0_Waiting);
-						it6602->HDMIWaitNo[0] += MAX_HDCP_WAITNO;
-					}
+
+			} else {
+				if ((it6602->HDMIIntEvent & (B_PORT0_TMDSEvent))) {
+					it6602->HDMIIntEvent |= (B_PORT0_Waiting);
+					it6602->HDMIWaitNo[0] += MAX_HDCP_WAITNO;
 				}
-			#endif
+			}
 
-			if ((Reg0Ah & 0x40))
-			{
+#endif
+
+			if ((Reg0Ah & 0x40)) {
 				it6602->CBusIntEvent |= (B_MSC_Waiting);
 				it6602->CBusWaitNo = MAX_CBUS_WAITNO;
 			}
 		}
 
-		if (Reg05h & 0x10)
-		{
+		if (Reg05h & 0x10) {
 			IT_INFO("#### Port 0 HDCP Authentication Done ####\r\n");
 
-			if ((Reg0Ah & 0x40))
-			{
+			if ((Reg0Ah & 0x40)) {
 				it6602->CBusIntEvent |= (B_MSC_Waiting);
 				it6602->CBusWaitNo = MAX_CBUS_WAITNO;
 			}
 
-		#ifdef _SUPPORT_HDCP_REPEATER_
+#ifdef _SUPPORT_HDCP_REPEATER_
 
-				if (m_bHDCPrepeater == FALSE)
-					m_RxHDCPstatus = 0;
-				else
-					m_RxHDCPstatus = 2;
+			if (m_bHDCPrepeater == FALSE) {
+				m_RxHDCPstatus = 0;
 
-			#ifdef _PSEUDO_HDCP_REPEATER_TEST_
-						// TX_BSTATUS = 0x102;
-						//ITEHDMI_RxHDCP2ndAuthenticationRequest(TX_KSVList, TX_BKSV, TX_BSTATUS);
-			#else
+			} else {
+				m_RxHDCPstatus = 2;
+			}
 
-			#endif
+#ifdef _PSEUDO_HDCP_REPEATER_TEST_
+			// TX_BSTATUS = 0x102;
+			//ITEHDMI_RxHDCP2ndAuthenticationRequest(TX_KSVList, TX_BKSV, TX_BSTATUS);
+#else
 
-			#ifdef _SUPPORT_AUTO_EQ_
-						//FIX_ID_033 xxxxx  //Fine-tune EQ Adjust function for HDCP receiver and repeater mode
-						if (ucPortAMPOverWrite[0] == 0) // 2013-0801
-						{
-							it6602->HDMIIntEvent &= ~(B_PORT0_Waiting);
-							it6602->HDMIWaitNo[0] = 0;
-							it6602->HDMIIntEvent |= B_PORT0_TMDSEvent;
-							//return;
-						}
-			#endif
+#endif
 
-		#else
+#ifdef _SUPPORT_AUTO_EQ_
 
-			#ifdef _SUPPORT_AUTO_EQ_
+			//FIX_ID_033 xxxxx  //Fine-tune EQ Adjust function for HDCP receiver and repeater mode
+			if (ucPortAMPOverWrite[0] == 0) { // 2013-0801
+				it6602->HDMIIntEvent &= ~(B_PORT0_Waiting);
+				it6602->HDMIWaitNo[0] = 0;
+				it6602->HDMIIntEvent |= B_PORT0_TMDSEvent;
+				//return;
+			}
 
-						if (ucPortAMPOverWrite[0] == 0) // 2013-0801
-						{
-							it6602->HDMIIntEvent &= ~(B_PORT0_Waiting);
-							it6602->HDMIWaitNo[0] = 0;
-							it6602->HDMIIntEvent |= B_PORT0_TMDSEvent;
-							//return;
-						}
+#endif
 
-			#endif
+#else
+
+#ifdef _SUPPORT_AUTO_EQ_
+
+			if (ucPortAMPOverWrite[0] == 0) { // 2013-0801
+				it6602->HDMIIntEvent &= ~(B_PORT0_Waiting);
+				it6602->HDMIWaitNo[0] = 0;
+				it6602->HDMIIntEvent |= B_PORT0_TMDSEvent;
+				//return;
+			}
 
-		#endif
+#endif
+
+#endif
 		}
 
-		if (Reg05h & 0x04)
-		{
+		if (Reg05h & 0x04) {
 			IT_INFO("#### Port 0 Input Clock Change Detect ####\r\n");
 		}
 
-		if (Reg05h & 0x02)
-		{
+		if (Reg05h & 0x02) {
 
 			it6602->m_ucEccCount_P0 = 0;
 			it6602->m_ucDeskew_P0 = 0;
@@ -3635,139 +3579,123 @@ void IT66021::IT6602HDMIInterruptHandler(struct it6602_dev_data *it6602)
 			//it6602->m_ucEccCount_P1=0;
 
 			IT_INFO("#### Port 0 Rx CKOn Detect ####\r\n");
-			if (CLKCheck(F_PORT_SEL_0))
-			{
-				#ifdef _SUPPORT_AUTO_EQ_
-					TMDSCheck(F_PORT_SEL_0);
-				#else
-			//FIX_ID_001 xxxxx Add Auto EQ with Manual EQ
-				#ifdef _SUPPORT_EQ_ADJUST_
-					HDMIStartEQDetect(&(it6602->EQPort[F_PORT_SEL_0]));
-				#endif
+
+			if (CLKCheck(F_PORT_SEL_0)) {
+#ifdef _SUPPORT_AUTO_EQ_
+				TMDSCheck(F_PORT_SEL_0);
+#else
+				//FIX_ID_001 xxxxx Add Auto EQ with Manual EQ
+#ifdef _SUPPORT_EQ_ADJUST_
+				HDMIStartEQDetect(&(it6602->EQPort[F_PORT_SEL_0]));
+#endif
 				//FIX_ID_001 xxxxx
-				#endif
+#endif
 			}
 		}
 
-		if (Reg05h & 0x01)
-		{
+		if (Reg05h & 0x01) {
 			IT_INFO("#### Port 0 Power 5V change ####\r\n");
 			hdmirx_INT_5V_Pwr_Chg(it6602, 0);
 		}
 	}
 
-	if (Reg06h != 0x00)
-	{
+	if (Reg06h != 0x00) {
 		//IT_INFO("Reg06h = %X",(int) Reg06h);
-		if (Reg06h & 0x80)
-		{
+		if (Reg06h & 0x80) {
 			IT_INFO("#### Port 1 HDCP Off Detected ###\r\n");
 			it6602->m_ucEccCount_P1 = 0;
 		}
 
-		if (Reg06h & 0x40)
-		{
+		if (Reg06h & 0x40) {
 			IT_INFO("#### Port 1 ECC Error ####\r\n");
 			hdmirx_INT_P1_ECC(it6602);
 		}
 
-		if (Reg06h & 0x20)
-		{
+		if (Reg06h & 0x20) {
 			IT_INFO("#### Port 1 HDMI/DVI Mode change ####\r\n");
-			if (CLKCheck(1))
+
+			if (CLKCheck(1)) {
 				hdmirx_INT_HDMIMode_Chg(it6602, 1);
+			}
 		}
 
-		if (Reg06h & 0x08)
-		{
+		if (Reg06h & 0x08) {
 			IT_INFO("#### Port 1 HDCP Authentication Start ####\r\n");
 			it6602->m_ucEccCount_P1 = 0;
 
 #ifdef _SUPPORT_AUTO_EQ_
-			if (ucPortAMPOverWrite[F_PORT_SEL_1] == 0)
-			{
-				if ((it6602->HDMIIntEvent & (B_PORT1_Waiting)) == 0)
-				{
+
+			if (ucPortAMPOverWrite[F_PORT_SEL_1] == 0) {
+				if ((it6602->HDMIIntEvent & (B_PORT1_Waiting)) == 0) {
 					IT_INFO(" power down auto EQ of PORT 1\r\n");
 					hdmirxwr(REG_RX_03A, 0x00); // power down auto EQ
 
 					it6602->HDMIIntEvent |= (B_PORT1_Waiting);
 					it6602->HDMIIntEvent |= (B_PORT1_TMDSEvent);
-					it6602->HDMIWaitNo[1] = MAX_TMDS_WAITNO;
-				}
-				else if ((it6602->HDMIIntEvent & (B_PORT1_TMDSEvent)))
-				{
+					it6602->HDMIWaitNo[1] = MAX_TMDS_WAITNO;
+
+				} else if ((it6602->HDMIIntEvent & (B_PORT1_TMDSEvent))) {
 					it6602->HDMIIntEvent |= (B_PORT1_Waiting);
 					it6602->HDMIWaitNo[1] += MAX_HDCP_WAITNO;
 				}
-			}
-			else
-			{
-				if ((it6602->HDMIIntEvent & (B_PORT1_TMDSEvent)))
-				{
+
+			} else {
+				if ((it6602->HDMIIntEvent & (B_PORT1_TMDSEvent))) {
 					it6602->HDMIIntEvent |= (B_PORT1_Waiting);
 					it6602->HDMIWaitNo[1] += MAX_HDCP_WAITNO;
 				}
 			}
+
 #endif
 		}
 
-		if (Reg06h & 0x10)
-		{
+		if (Reg06h & 0x10) {
 			IT_INFO("#### Port 1 HDCP Authentication Done ####\r\n");
-			if ((it6602->HDMIIntEvent & (B_PORT1_Waiting)))
-			{
+
+			if ((it6602->HDMIIntEvent & (B_PORT1_Waiting))) {
 				it6602->HDMIWaitNo[1] = 0;
 			}
 
 #ifdef _SUPPORT_AUTO_EQ_
-			if (ucPortAMPOverWrite[1] == 0) // 2013-0801
-			{
+
+			if (ucPortAMPOverWrite[1] == 0) { // 2013-0801
 				it6602->HDMIIntEvent &= ~(B_PORT1_Waiting);
 				it6602->HDMIWaitNo[1] = 0;
 				it6602->HDMIIntEvent |= B_PORT1_TMDSEvent;
 			}
+
 #endif
 		}
 
-		if (Reg06h & 0x04)
-		{
+		if (Reg06h & 0x04) {
 			IT_INFO("#### Port 1 Input Clock Change Detect ####\r\n");
 		}
 
-		if (Reg06h & 0x02)
-		{
+		if (Reg06h & 0x02) {
 			IT_INFO("#### Port 1 Rx CKOn Detect ####\r\n");
 			//it6602->m_ucEccCount_P0=0;
 			//it6602->m_ucDeskew_P0=0;
 			it6602->m_ucDeskew_P1 = 0;
 			it6602->m_ucEccCount_P1 = 0;
 
-			if ((Reg06h & 0x08) == 0 && (Reg06h & 0x04) == 0 && (it6602->HDMIIntEvent & (B_PORT1_TMDSEvent)) == 0)
-			{
-				if (CLKCheck(F_PORT_SEL_1))
-				{
+			if ((Reg06h & 0x08) == 0 && (Reg06h & 0x04) == 0 && (it6602->HDMIIntEvent & (B_PORT1_TMDSEvent)) == 0) {
+				if (CLKCheck(F_PORT_SEL_1)) {
 #ifdef _SUPPORT_AUTO_EQ_
 					TMDSCheck(F_PORT_SEL_1);
 #endif
 				}
-			}
-			else
-			{
-				if ((Reg06h & 0x10) == 0)
-				{
-					if ((it6602->HDMIIntEvent & (B_PORT1_Waiting)) == 0)
-					{
+
+			} else {
+				if ((Reg06h & 0x10) == 0) {
+					if ((it6602->HDMIIntEvent & (B_PORT1_Waiting)) == 0) {
 						hdmirxwr(REG_RX_03A, 0x00); // power down auto EQ
 						it6602->HDMIIntEvent |= (B_PORT1_Waiting);
 						it6602->HDMIIntEvent |= (B_PORT1_TMDSEvent);
 						it6602->HDMIWaitNo[1] = MAX_TMDS_WAITNO;
 					}
-				}
-				else
-				{
-					if (CLKCheck(F_PORT_SEL_1))
-					{
+
+				} else {
+					if (CLKCheck(F_PORT_SEL_1)) {
 #ifdef _SUPPORT_AUTO_EQ_
 						TMDSCheck(F_PORT_SEL_1);
 #else
@@ -3782,68 +3710,56 @@ void IT66021::IT6602HDMIInterruptHandler(struct it6602_dev_data *it6602)
 			}
 		}
 
-		if (Reg06h & 0x01)
-		{
+		if (Reg06h & 0x01) {
 			IT_INFO("#### Port 1 Power 5V change ####\r\n");
 			hdmirx_INT_5V_Pwr_Chg(it6602, 1);
 		}
 	}
 
-	if (Reg07h != 0x00)
-	{
-		if (Reg07h & 0x80)
-		{
+	if (Reg07h != 0x00) {
+		if (Reg07h & 0x80) {
 			IT_INFO("#### Audio FIFO Error ####\r\n");
 			aud_fiforst();
-		#ifdef EnableCalFs
-					//FIX_ID_023 xxxxx		//Fixed for Audio Channel Status Error with invalid HDMI source
-					AudioFsCal();
-		//FIX_ID_023 xxxxx
-		#endif
+#ifdef EnableCalFs
+			//FIX_ID_023 xxxxx		//Fixed for Audio Channel Status Error with invalid HDMI source
+			AudioFsCal();
+			//FIX_ID_023 xxxxx
+#endif
 		}
 
-		if (Reg07h & 0x40)
-		{
+		if (Reg07h & 0x40) {
 			IT_INFO("#### Audio Auto Mute ####\r\n");
 		}
 
-		if (Reg07h & 0x20)
-		{
+		if (Reg07h & 0x20) {
 			IT_INFO("#### Packet Left Mute ####\r\n");
 			IT6602_SetVideoMute(it6602, OFF);
 		}
 
-		if (Reg07h & 0x10)
-		{
+		if (Reg07h & 0x10) {
 			IT_INFO("#### Set Mute Packet Received ####\r\n");
 
 			IT6602_SetVideoMute(it6602, ON);
 		}
 
-		if (Reg07h & 0x08)
-		{
+		if (Reg07h & 0x08) {
 			IT_INFO("#### Timer Counter Tntterrupt ####\r\n");
 		}
 
-		if (Reg07h & 0x04)
-		{
+		if (Reg07h & 0x04) {
 			IT_INFO("#### Video Mode Changed ####\r\n");
 		}
 
-		if (Reg07h & 0x02)
-		{
+		if (Reg07h & 0x02) {
 			hdmirx_INT_SCDT_Chg(it6602);
 		}
 
-		if (Reg07h & 0x01)
-		{
-			if ((Reg0Ah & 0x40) >> 6)
-			{
+		if (Reg07h & 0x01) {
+			if ((Reg0Ah & 0x40) >> 6) {
 				IT_INFO("#### Port 0 Bus Mode : MHL ####\r\n");
 
 				//FIX_ID_002 xxxxx 	Check IT6602 chip version Identify for TogglePolarity and Port 1 Deskew
-				if (HdmiI2cAddr == IT6602A0_HDMI_ADDR)
-				{
+				if (HdmiI2cAddr == IT6602A0_HDMI_ADDR) {
 					chgbank(1);
 					hdmirxset(REG_RX_1B6, 0x07, 0x00);
 					//FIX_ID_007 xxxxx 	//for debug IT6681  HDCP issue
@@ -3853,13 +3769,12 @@ void IT66021::IT6602HDMIInterruptHandler(struct it6602_dev_data *it6602)
 					//FIX_ID_007 xxxxx
 					chgbank(0);
 				}
-			}
-			else
-			{
+
+			} else {
 				IT_INFO("#### Port 0 Bus Mode : HDMI ####\r\n");
+
 				//FIX_ID_002 xxxxx 	Check IT6602 chip version Identify for TogglePolarity and Port 1 Deskew
-				if (HdmiI2cAddr == IT6602A0_HDMI_ADDR)
-				{
+				if (HdmiI2cAddr == IT6602A0_HDMI_ADDR) {
 					chgbank(1);
 					hdmirxset(REG_RX_1B6, 0x07, 0x03);
 					////FIX_ID_007 xxxxx 	//for debug IT6681  HDCP issue
@@ -3869,172 +3784,150 @@ void IT66021::IT6602HDMIInterruptHandler(struct it6602_dev_data *it6602)
 					////FIX_ID_007 xxxxx
 					chgbank(0);
 				}
+
 				//FIX_ID_002 xxxxx
 			}
 		};
 	}
 
-	if (Reg08h != 0x00)
-	{
+	if (Reg08h != 0x00) {
 		//IT_INFO("Reg08h = %X",(int) Reg08h);
-		if (Reg08h & 0x80)
-		{
+		if (Reg08h & 0x80) {
 			//			 IT_INFO("#### No General Packet 2 Received ####\n");
 		}
 
-		if (Reg08h & 0x40)
-		{
+		if (Reg08h & 0x40) {
 			//			 IT_INFO("#### No General Packet Received ####\n");
 		}
 
-		if (Reg08h & 0x20)
-		{
+		if (Reg08h & 0x20) {
 			IT_INFO("#### No Audio InfoFrame Received ####\r\n");
 		}
 
-		if (Reg08h & 0x10)
-		{
+		if (Reg08h & 0x10) {
 			IT_INFO("#### No AVI InfoFrame Received ####\r\n");
 		}
 
-		if (Reg08h & 0x08)
-		{
+		if (Reg08h & 0x08) {
 			IT_INFO("#### CD Detect ####\r\n");
 		}
 
-		if (Reg08h & 0x04)
-		{
+		if (Reg08h & 0x04) {
 			//			 IT_INFO("#### Gen Pkt Detect ####\n");
 			IT_INFO("#### 3D InfoFrame Detect ####\r\n");
 
-		#ifdef Enable_Vendor_Specific_packet
-					if (it6602->f_de3dframe_hdmi == FALSE)
-					{
-						it6602->f_de3dframe_hdmi = IT6602_DE3DFrame(TRUE);
-					}
-		#endif
+#ifdef Enable_Vendor_Specific_packet
+
+			if (it6602->f_de3dframe_hdmi == FALSE) {
+				it6602->f_de3dframe_hdmi = IT6602_DE3DFrame(TRUE);
+			}
+
+#endif
 		}
 
-		if (Reg08h & 0x02)
-		{
+		if (Reg08h & 0x02) {
 			IT_INFO("#### ISRC2 Detect ####\r\n");
 		}
 
-		if (Reg08h & 0x01)
-		{
+		if (Reg08h & 0x01) {
 			IT_INFO("#### ISRC1 Detect ####\r\n");
 		}
 	}
 
-	if (Reg09h != 0x00)
-	{
+	if (Reg09h != 0x00) {
 		//IT_INFO("Reg09h = %X",(int) Reg09h);
-		if (Reg09h & 0x80)
-		{
+		if (Reg09h & 0x80) {
 			IT_INFO("#### H2V Buffer Skew Fail ####\r\n");
 		}
 
-		if (Reg09h & 0x40)
-		{
+		if (Reg09h & 0x40) {
 
 			//FIX_ID_002 xxxxx 	Check IT6602 chip version Identify for TogglePolarity and Port 1 Deskew
-			if (HdmiI2cAddr == IT6602A0_HDMI_ADDR)
-			{
+			if (HdmiI2cAddr == IT6602A0_HDMI_ADDR) {
 				hdmirxwr(0x09, 0x20); //bug ~ need to update by Andrew
-			}
-			else
-			{
+
+			} else {
 				hdmirxwr(0x09, 0x40);
 			}
+
 			//FIX_ID_002 xxxxx
 			IT_INFO("#### Port 1 Deskew Error ####\r\n");
 			hdmirx_INT_P1_Deskew(it6602);
 		}
 
-		if (Reg09h & 0x20)
-		{
+		if (Reg09h & 0x20) {
 			hdmirxwr(0x09, 0x20);
 			IT_INFO("#### Port 0 Deskew Error ####\r\n");
 			hdmirx_INT_P0_Deskew(it6602);
 		}
 
-		if (Reg09h & 0x10)
-		{
+		if (Reg09h & 0x10) {
 			IT_INFO("#### New Audio Packet Received ####\r\n");
 		}
 
-		if (Reg09h & 0x08)
-		{
+		if (Reg09h & 0x08) {
 			IT_INFO("#### New ACP Packet Received ####\r\n");
 		}
 
-		if (Reg09h & 0x04)
-		{
+		if (Reg09h & 0x04) {
 			IT_INFO("#### New SPD Packet Received ####\r\n");
 		}
 
-		if (Reg09h & 0x02)
-		{
+		if (Reg09h & 0x02) {
 			IT_INFO("#### New MPEG InfoFrame Received ####\r\n");
 		}
 
-		if (Reg09h & 0x01)
-		{
+		if (Reg09h & 0x01) {
 			IT_INFO("#### New AVI InfoFrame Received ####\r\n");
 			//IT6602VideoOutputConfigure();
 			it6602->m_NewAVIInfoFrameF = TRUE;
 		}
 	}
 
-	if (RegD0h != 0x00)
-	{
-		if (RegD0h & 0x10)
-		{
+	if (RegD0h != 0x00) {
+		if (RegD0h & 0x10) {
 
 			hdmirxwr(0xD0, 0x30);
 			RegD0h &= 0x30;
 			IT_INFO("#### Port 0 EQ done interrupt ####\r\n");
 
-		#ifdef _SUPPORT_AUTO_EQ_
-					AmpValidCheck(0); //2013-0801
-		#endif
+#ifdef _SUPPORT_AUTO_EQ_
+			AmpValidCheck(0); //2013-0801
+#endif
 
-		#ifdef _SUPPORT_EQ_ADJUST_
-					HDMIStartEQDetect(&(it6602->EQPort[F_PORT_SEL_0]));
-		#endif
+#ifdef _SUPPORT_EQ_ADJUST_
+			HDMIStartEQDetect(&(it6602->EQPort[F_PORT_SEL_0]));
+#endif
 		}
 
-		if (RegD0h & 0x40)
-		{
+		if (RegD0h & 0x40) {
 
 			hdmirxwr(0xD0, 0xC0);
 			RegD0h &= 0xC0;
 			IT_INFO("#### Port 1 EQ done interrupt ####\r\n");
 
-		#ifdef _SUPPORT_AUTO_EQ_
-					AmpValidCheck(1); //2013-0801
-		#endif
-				}
+#ifdef _SUPPORT_AUTO_EQ_
+			AmpValidCheck(1); //2013-0801
+#endif
+		}
 
-				if (RegD0h & 0x20)
-				{
-					hdmirxwr(0xD0, 0x20);
-					IT_INFO("#### Port 0 EQ Fail Interrupt ####\r\n");
-		#ifdef _SUPPORT_AUTO_EQ_
-					hdmirx_INT_EQ_FAIL(it6602, F_PORT_SEL_0);
-		#endif
+		if (RegD0h & 0x20) {
+			hdmirxwr(0xD0, 0x20);
+			IT_INFO("#### Port 0 EQ Fail Interrupt ####\r\n");
+#ifdef _SUPPORT_AUTO_EQ_
+			hdmirx_INT_EQ_FAIL(it6602, F_PORT_SEL_0);
+#endif
 		}
 
-		if (RegD0h & 0x80)
-		{
+		if (RegD0h & 0x80) {
 
 			hdmirxwr(0xD0, 0x80);
 			IT_INFO("#### Port 1 EQ Fail Interrupt ####\r\n");
 			//	HDMICheckErrorCount(&(it6602->EQPort[F_PORT_SEL_1]));	//07-04 for port 0
 			//FIX_ID_001 xxxxx Add Auto EQ with Manual EQ
-		#ifdef _SUPPORT_AUTO_EQ_
-					hdmirx_INT_EQ_FAIL(it6602, F_PORT_SEL_1);
-		#endif
+#ifdef _SUPPORT_AUTO_EQ_
+			hdmirx_INT_EQ_FAIL(it6602, F_PORT_SEL_1);
+#endif
 		}
 	}
 }
@@ -4042,17 +3935,13 @@ void IT66021::IT6602HDMIInterruptHandler(struct it6602_dev_data *it6602)
 #if Enable_IR
 void IT66021::it6602AutoPortSelect(struct it6602_dev_data *it6602)
 {
-	if (SEL_PORT_1 == 1)
-	{
-		if (it6602->m_ucCurrentHDMIPort != 0)
-		{
+	if (SEL_PORT_1 == 1) {
+		if (it6602->m_ucCurrentHDMIPort != 0) {
 			it6602PortSelect(0);
 		}
-	}
-	else
-	{
-		if (it6602->m_ucCurrentHDMIPort == 0)
-		{
+
+	} else {
+		if (it6602->m_ucCurrentHDMIPort == 0) {
 			it6602PortSelect(1);
 		}
 	}
@@ -4067,39 +3956,39 @@ void IT66021::it6602AutoPortSelect(struct it6602_dev_data *it6602)
 #define TOP_AND_BOTTOM 0x60
 #define SIDE_BY_SIDE 0x80
 
-SET_DE3D_FRAME t_3d_syncgen[] =
-	{
-		//640x480      //524   //559   //514   //526
-		{0x01, 0x020C, 0x022F, 0x0202, 0x020E, 480}, // 60Hz
-		//480p      //524   //560   //515   //530
-		{0x02, 0x020C, 0x0230, 0x0203, 0x0212, 480}, // 60Hz
-		{0x03, 0x020C, 0x0230, 0x0203, 0x0212, 480}, // 60Hz
-		//576p      //624   //668   //619   //629
-		{0x11, 0x0270, 0x029C, 0x026B, 0x0275, 576}, // 50Hz
-		{0x12, 0x0270, 0x029C, 0x026B, 0x0275, 576}, // 50Hz
-		//720p      //749   //774   //744   //754
-		{0x3c, 0x02ED, 0x0306, 0x02E8, 0x02F2, 720}, // 24Hz
-		{0x3d, 0x02ED, 0x0306, 0x02E8, 0x02F2, 720}, // 25Hz
-		{0x3e, 0x02ED, 0x0306, 0x02E8, 0x02F2, 720}, // 30Hz
-		{0x13, 0x02ED, 0x0306, 0x02E8, 0x02F2, 720}, // 50Hz
-		{0x04, 0x02ED, 0x0306, 0x02E8, 0x02F2, 720}, // 60Hz
-
-		//disable -> 1080i     //1124   //1165   //1120   //1129
-		//disable ->     {0x05      ,0x0464  ,0x048D  ,0x0460  ,0x0469,	540}, // 50Hz
-		//disable ->     {0x14      ,0x0464  ,0x048D  ,0x0460  ,0x0469,	540}, // 60Hz
-		//disable -> 1080i     //1124   //1165   //1120   //1129
-		//disable ->     {0x20      ,0x0464  ,0x048D  ,0x0460  ,0x0469,	540}, // 24Hz
-		//disable ->     {0x22      ,0x0464  ,0x048D  ,0x0460  ,0x0469,	540}, // 30Hz
-		//disable ->     {0x1f      ,0x0464  ,0x048D  ,0x0460  ,0x0469,	540}, // 50Hz
-		//disable ->     {0x10      ,0x0464  ,0x048D  ,0x0460  ,0x0469,	540}, // 60Hz
-
-		//1080p    //1124   //1165   //1120   //1129
-		{0x20, 0x0464, 0x048D, 0x0460, 0x0469, 1080}, // 24Hz
-		{0x21, 0x0464, 0x048D, 0x0460, 0x0469, 1080}, // 25Hz
-		{0x22, 0x0464, 0x048D, 0x0460, 0x0469, 1080}, // 30Hz
-
-		//default
-		{0xFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}};
+SET_DE3D_FRAME t_3d_syncgen[] = {
+	//640x480      //524   //559   //514   //526
+	{0x01, 0x020C, 0x022F, 0x0202, 0x020E, 480}, // 60Hz
+	//480p      //524   //560   //515   //530
+	{0x02, 0x020C, 0x0230, 0x0203, 0x0212, 480}, // 60Hz
+	{0x03, 0x020C, 0x0230, 0x0203, 0x0212, 480}, // 60Hz
+	//576p      //624   //668   //619   //629
+	{0x11, 0x0270, 0x029C, 0x026B, 0x0275, 576}, // 50Hz
+	{0x12, 0x0270, 0x029C, 0x026B, 0x0275, 576}, // 50Hz
+	//720p      //749   //774   //744   //754
+	{0x3c, 0x02ED, 0x0306, 0x02E8, 0x02F2, 720}, // 24Hz
+	{0x3d, 0x02ED, 0x0306, 0x02E8, 0x02F2, 720}, // 25Hz
+	{0x3e, 0x02ED, 0x0306, 0x02E8, 0x02F2, 720}, // 30Hz
+	{0x13, 0x02ED, 0x0306, 0x02E8, 0x02F2, 720}, // 50Hz
+	{0x04, 0x02ED, 0x0306, 0x02E8, 0x02F2, 720}, // 60Hz
+
+	//disable -> 1080i     //1124   //1165   //1120   //1129
+	//disable ->     {0x05      ,0x0464  ,0x048D  ,0x0460  ,0x0469,	540}, // 50Hz
+	//disable ->     {0x14      ,0x0464  ,0x048D  ,0x0460  ,0x0469,	540}, // 60Hz
+	//disable -> 1080i     //1124   //1165   //1120   //1129
+	//disable ->     {0x20      ,0x0464  ,0x048D  ,0x0460  ,0x0469,	540}, // 24Hz
+	//disable ->     {0x22      ,0x0464  ,0x048D  ,0x0460  ,0x0469,	540}, // 30Hz
+	//disable ->     {0x1f      ,0x0464  ,0x048D  ,0x0460  ,0x0469,	540}, // 50Hz
+	//disable ->     {0x10      ,0x0464  ,0x048D  ,0x0460  ,0x0469,	540}, // 60Hz
+
+	//1080p    //1124   //1165   //1120   //1129
+	{0x20, 0x0464, 0x048D, 0x0460, 0x0469, 1080}, // 24Hz
+	{0x21, 0x0464, 0x048D, 0x0460, 0x0469, 1080}, // 25Hz
+	{0x22, 0x0464, 0x048D, 0x0460, 0x0469, 1080}, // 30Hz
+
+	//default
+	{0xFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
+};
 //Reg_PGVTotal	749		// 0x2ED
 //Reg_PGVActst 	774		// 0x306
 //Reg_PGVActEd	744		// 0x2E8
@@ -4140,30 +4029,31 @@ void IT66021::Dump3DReg(void)
 	BYTE ucData;
 
 	IT_INFO("\r\n       ");
-	for (j = 0; j < 16; j++)
-	{
+
+	for (j = 0; j < 16; j++) {
 		IT_INFO(" %02X", (int)j);
-		if ((j == 3) || (j == 7) || (j == 11))
-		{
+
+		if ((j == 3) || (j == 7) || (j == 11)) {
 			IT_INFO(" :");
 		}
 	}
+
 	IT_INFO("\r\n");
 
 	chgbank(1);
 
-	for (i = 0x80; i < 0xa0; i += 16)
-	{
+	for (i = 0x80; i < 0xa0; i += 16) {
 		IT_INFO("[%03X]  ", i);
-		for (j = 0; j < 16; j++)
-		{
+
+		for (j = 0; j < 16; j++) {
 			ucData = hdmirxrd((BYTE)((i + j) & 0xFF));
 			IT_INFO(" %02X", (int)ucData);
-			if ((j == 3) || (j == 7) || (j == 11))
-			{
+
+			if ((j == 3) || (j == 7) || (j == 11)) {
 				IT_INFO(" :");
 			}
 		}
+
 		IT_INFO("\r\n");
 	}
 
@@ -4191,14 +4081,13 @@ unsigned char IT66021::IT6602_DE3DFrame(unsigned char ena_de3d)
 
 	struct it6602_dev_data *it6602data = get_it6602_dev_data();
 
-	if (ena_de3d == TRUE)
-	{
+	if (ena_de3d == TRUE) {
 
 		chgbank(2);
 		uc = hdmirxrd(REG_RX_224);
 		chgbank(0);
-		if (uc == 0x81) // 3D InfoFrame Packet Type is valid
-		{
+
+		if (uc == 0x81) { // 3D InfoFrame Packet Type is valid
 
 			chgbank(2);
 			it6602data->s_Current3DFr.VIC = hdmirxrd(REG_RX_218); //AVI INFO PB4
@@ -4239,24 +4128,29 @@ unsigned char IT66021::IT6602_DE3DFrame(unsigned char ena_de3d)
 			it6602data->de3dframe_config.TB_Reference = 2;   // Top/Bottom reference for vertically sub-sampled sources
 			it6602data->de3dframe_config.OE_Reference = 2;   // Odd/Even reference for horizontally sub-sampled sources
 
-			it6602data->de3dframe_config.NumActiveBlankLines = 0;		// Number of lines separating vertically packed L/R data to be removed (cropped)before being displayed
-			it6602data->de3dframe_config.NumberOfEncodedLines = 0;		// Number of encoded lines in one L/R eye frame of the display data to be blanked out with "Blanking Color".
-			it6602data->de3dframe_config.LeftEncodedLineLocation = -1;  // Active line number of 1st encoded line in one Left eye frame of the display data (-1=unknown).
-			it6602data->de3dframe_config.RightEncodedLineLocation = -1; // Active line number of 1st encoded line in one Right eye frame of the display data (-1=unknown).
-			it6602data->de3dframe_config.BlankingColor = 7;				// Color to use when blanking (or masking off) any embedded L/R encoding
-
-			if (((it6602data->s_Current3DFr.PB4 & 0xE0) == HDMI_3DFORMAT_PRESENT) && ((it6602data->s_Current3DFr.PB5 & 0xF0) == FRAME_PACKING))
-			{
+			it6602data->de3dframe_config.NumActiveBlankLines =
+				0;		// Number of lines separating vertically packed L/R data to be removed (cropped)before being displayed
+			it6602data->de3dframe_config.NumberOfEncodedLines =
+				0;		// Number of encoded lines in one L/R eye frame of the display data to be blanked out with "Blanking Color".
+			it6602data->de3dframe_config.LeftEncodedLineLocation =
+				-1;  // Active line number of 1st encoded line in one Left eye frame of the display data (-1=unknown).
+			it6602data->de3dframe_config.RightEncodedLineLocation =
+				-1; // Active line number of 1st encoded line in one Right eye frame of the display data (-1=unknown).
+			it6602data->de3dframe_config.BlankingColor =
+				7;				// Color to use when blanking (or masking off) any embedded L/R encoding
+
+			if (((it6602data->s_Current3DFr.PB4 & 0xE0) == HDMI_3DFORMAT_PRESENT)
+			    && ((it6602data->s_Current3DFr.PB5 & 0xF0) == FRAME_PACKING)) {
 				i = 0;
 
-				while (t_3d_syncgen[i].Vic != 0xFF)
-				{
-					if (t_3d_syncgen[i].Vic == it6602data->s_Current3DFr.VIC)
-					{
+				while (t_3d_syncgen[i].Vic != 0xFF) {
+					if (t_3d_syncgen[i].Vic == it6602data->s_Current3DFr.VIC) {
 						break;
 					}
+
 					i++;
 				}
+
 				v_total = t_3d_syncgen[i].V_total;
 				v_act_start = t_3d_syncgen[i].V_act_start;
 				v_act_end = t_3d_syncgen[i].V_act_end;
@@ -4321,29 +4215,27 @@ unsigned char IT66021::IT6602_DE3DFrame(unsigned char ena_de3d)
 				v_act_bspace = v_act_start - v_act_end;
 			}
 
-			if (((it6602data->s_Current3DFr.PB4 & 0xE0) == HDMI_3DFORMAT_PRESENT) && (!it6602data->DE3DFormat_HDMIFlag))
-			{
+			if (((it6602data->s_Current3DFr.PB4 & 0xE0) == HDMI_3DFORMAT_PRESENT) && (!it6602data->DE3DFormat_HDMIFlag)) {
 				it6602data->DE3DFormat_HDMIFlag = TRUE;
 			}
 
-			if (((it6602data->s_Current3DFr.PB4 & 0xE0) == HDMI_3DFORMAT_PRESENT) && (it6602data->DE3DFormat_HDMIFlag))
-			{
-				if (((it6602data->s_Current3DFr.PB5 & 0xF0) == FRAME_PACKING) && (!it6602data->FramePacking_Flag))
-				{
+			if (((it6602data->s_Current3DFr.PB4 & 0xE0) == HDMI_3DFORMAT_PRESENT) && (it6602data->DE3DFormat_HDMIFlag)) {
+				if (((it6602data->s_Current3DFr.PB5 & 0xF0) == FRAME_PACKING) && (!it6602data->FramePacking_Flag)) {
 					it6602data->FramePacking_Flag = TRUE;
 					it6602data->TopAndBottom_Flag = FALSE;
 					it6602data->SideBySide_Flag = FALSE;
 					it6602data->oldVIC = 0;
 				}
 
-				if (((it6602data->s_Current3DFr.PB5 & 0xF0) == FRAME_PACKING) && (it6602data->FramePacking_Flag))
-				{
+				if (((it6602data->s_Current3DFr.PB5 & 0xF0) == FRAME_PACKING) && (it6602data->FramePacking_Flag)) {
 					it6602data->newVIC = it6602data->s_Current3DFr.VIC;
-					if (it6602data->newVIC != it6602data->oldVIC)
-					{
-						if ((it6602data->s_Current3DFr.VIC == 0x3c) || (it6602data->s_Current3DFr.VIC == 0x3e) || (it6602data->s_Current3DFr.VIC == 0x13) ||
-							(it6602data->s_Current3DFr.VIC == 0x04) || (it6602data->s_Current3DFr.VIC == 0x20) || (it6602data->s_Current3DFr.VIC == 0x22))
-						//(it6602data->s_Current3DFr.VIC == 0x05) ||(it6602data->s_Current3DFr.VIC == 0x14) // 1080i@50&60Hz not supported for frame packing
+
+					if (it6602data->newVIC != it6602data->oldVIC) {
+						if ((it6602data->s_Current3DFr.VIC == 0x3c) || (it6602data->s_Current3DFr.VIC == 0x3e)
+						    || (it6602data->s_Current3DFr.VIC == 0x13) ||
+						    (it6602data->s_Current3DFr.VIC == 0x04) || (it6602data->s_Current3DFr.VIC == 0x20)
+						    || (it6602data->s_Current3DFr.VIC == 0x22))
+							//(it6602data->s_Current3DFr.VIC == 0x05) ||(it6602data->s_Current3DFr.VIC == 0x14) // 1080i@50&60Hz not supported for frame packing
 						{
 							it6602data->de3dframe_config.NumActiveBlankLines = (unsigned char)v_act_bspace;
 							it6602data->de3dframe_config.Format = VERT_PACKED_FULL; // Type of 3D source format is FRAME_PACKING(VERT_PACKED_FULL)
@@ -4354,15 +4246,15 @@ unsigned char IT66021::IT6602_DE3DFrame(unsigned char ena_de3d)
 							IT_INFO("ITEHDMI - HDMI_3DFORMAT is FRAME_PACKING \r\n");
 
 #endif
-						}
-						else
-						{
+
+						} else {
 							it6602data->de3dframe_config.Format = 6; // Type of 3D source format is UNDEFINED_FORMAT
 
 #ifdef DEBUG_MODE_3D
 							dbmsg_trace(DBM_3D, "ITEHDMI - HDMI_3DFORMAT is UNDEFINED_FORMAT \r\n");
 #endif
 						}
+
 #ifdef DEBUG_MODE_3D
 						dbmsg_trace(DBM_3D, "ITEHDMI - HDMI_3DFORMAT is FRAME_PACKING call detect3D_Port_3D_On( ) \r\n");
 #endif
@@ -4372,11 +4264,13 @@ unsigned char IT66021::IT6602_DE3DFrame(unsigned char ena_de3d)
 					}
 				}
 
-				if (((it6602data->s_Current3DFr.PB5 & 0xF0) == TOP_AND_BOTTOM) && (!it6602data->TopAndBottom_Flag))
-				{
-					if ((it6602data->s_Current3DFr.VIC == 0x3c) || (it6602data->s_Current3DFr.VIC == 0x3e) || (it6602data->s_Current3DFr.VIC == 0x13) || (it6602data->s_Current3DFr.VIC == 0x04) || (it6602data->s_Current3DFr.VIC == 0x05) ||
-						(it6602data->s_Current3DFr.VIC == 0x14) || (it6602data->s_Current3DFr.VIC == 0x20) || (it6602data->s_Current3DFr.VIC == 0x22) || (it6602data->s_Current3DFr.VIC == 0x1f) || (it6602data->s_Current3DFr.VIC == 0x10))
-					{
+				if (((it6602data->s_Current3DFr.PB5 & 0xF0) == TOP_AND_BOTTOM) && (!it6602data->TopAndBottom_Flag)) {
+					if ((it6602data->s_Current3DFr.VIC == 0x3c) || (it6602data->s_Current3DFr.VIC == 0x3e)
+					    || (it6602data->s_Current3DFr.VIC == 0x13) || (it6602data->s_Current3DFr.VIC == 0x04)
+					    || (it6602data->s_Current3DFr.VIC == 0x05) ||
+					    (it6602data->s_Current3DFr.VIC == 0x14) || (it6602data->s_Current3DFr.VIC == 0x20)
+					    || (it6602data->s_Current3DFr.VIC == 0x22) || (it6602data->s_Current3DFr.VIC == 0x1f)
+					    || (it6602data->s_Current3DFr.VIC == 0x10)) {
 						it6602data->de3dframe_config.Format = VERT_PACKED_HALF; // Type of 3D source format is TOP_AND_BOTTOM(VERT_PACKED_HALF)
 
 #ifdef DEBUG_MODE_3D
@@ -4384,9 +4278,8 @@ unsigned char IT66021::IT6602_DE3DFrame(unsigned char ena_de3d)
 #else
 						IT_INFO("ITEHDMI - HDMI_3DFORMAT is TOP_AND_BOTTOM \r\n");
 #endif
-					}
-					else
-					{
+
+					} else {
 						it6602data->de3dframe_config.Format = 6; // Type of 3D source format is UNDEFINED_FORMAT
 
 #ifdef DEBUG_MODE_3D
@@ -4402,11 +4295,13 @@ unsigned char IT66021::IT6602_DE3DFrame(unsigned char ena_de3d)
 					it6602data->SideBySide_Flag = FALSE;
 				}
 
-				if (((it6602data->s_Current3DFr.PB5 & 0xF0) == SIDE_BY_SIDE) && (!it6602data->SideBySide_Flag))
-				{
-					if ((it6602data->s_Current3DFr.VIC == 0x3c) || (it6602data->s_Current3DFr.VIC == 0x3e) || (it6602data->s_Current3DFr.VIC == 0x13) || (it6602data->s_Current3DFr.VIC == 0x04) || (it6602data->s_Current3DFr.VIC == 0x05) ||
-						(it6602data->s_Current3DFr.VIC == 0x14) || (it6602data->s_Current3DFr.VIC == 0x20) || (it6602data->s_Current3DFr.VIC == 0x22) || (it6602data->s_Current3DFr.VIC == 0x1f) || (it6602data->s_Current3DFr.VIC == 0x10))
-					{
+				if (((it6602data->s_Current3DFr.PB5 & 0xF0) == SIDE_BY_SIDE) && (!it6602data->SideBySide_Flag)) {
+					if ((it6602data->s_Current3DFr.VIC == 0x3c) || (it6602data->s_Current3DFr.VIC == 0x3e)
+					    || (it6602data->s_Current3DFr.VIC == 0x13) || (it6602data->s_Current3DFr.VIC == 0x04)
+					    || (it6602data->s_Current3DFr.VIC == 0x05) ||
+					    (it6602data->s_Current3DFr.VIC == 0x14) || (it6602data->s_Current3DFr.VIC == 0x20)
+					    || (it6602data->s_Current3DFr.VIC == 0x22) || (it6602data->s_Current3DFr.VIC == 0x1f)
+					    || (it6602data->s_Current3DFr.VIC == 0x10)) {
 						it6602data->de3dframe_config.Format = HORIZ_PACKED_HALF; // Type of 3D source format is SIDE_BY_SIDE(HORIZ_PACKED_HALF)
 
 #ifdef DEBUG_MODE_3D
@@ -4414,9 +4309,8 @@ unsigned char IT66021::IT6602_DE3DFrame(unsigned char ena_de3d)
 #else
 						IT_INFO("ITEHDMI - HDMI_3DFORMAT is SIDE_BY_SIDE \r\n");
 #endif
-					}
-					else
-					{
+
+					} else {
 						it6602data->de3dframe_config.Format = 6; // Type of 3D source format is UNDEFINED_FORMAT
 
 #ifdef DEBUG_MODE_3D
@@ -4440,10 +4334,14 @@ unsigned char IT66021::IT6602_DE3DFrame(unsigned char ena_de3d)
 				dbmsg_ftrace(DBM_3D, "        LR_Encoding              = %X \r\n", (int)it6602data->de3dframe_config.LR_Encoding);
 				dbmsg_ftrace(DBM_3D, "        TB_Reference             = %X \r\n", (int)it6602data->de3dframe_config.TB_Reference);
 				dbmsg_ftrace(DBM_3D, "        OE_Reference             = %X \r\n", (int)it6602data->de3dframe_config.OE_Reference);
-				dbmsg_ftrace(DBM_3D, "        NumActiveBlankLines      = %X \r\n", (int)it6602data->de3dframe_config.NumActiveBlankLines);
-				dbmsg_ftrace(DBM_3D, "        NumberOfEncodedLines     = %X \r\n", (int)it6602data->de3dframe_config.NumberOfEncodedLines);
-				dbmsg_ftrace(DBM_3D, "        LeftEncodedLineLocation  = %X \r\n", (int)it6602data->de3dframe_config.LeftEncodedLineLocation);
-				dbmsg_ftrace(DBM_3D, "        RightEncodedLineLocation = %X \r\n", (int)it6602data->de3dframe_config.RightEncodedLineLocation);
+				dbmsg_ftrace(DBM_3D, "        NumActiveBlankLines      = %X \r\n",
+					     (int)it6602data->de3dframe_config.NumActiveBlankLines);
+				dbmsg_ftrace(DBM_3D, "        NumberOfEncodedLines     = %X \r\n",
+					     (int)it6602data->de3dframe_config.NumberOfEncodedLines);
+				dbmsg_ftrace(DBM_3D, "        LeftEncodedLineLocation  = %X \r\n",
+					     (int)it6602data->de3dframe_config.LeftEncodedLineLocation);
+				dbmsg_ftrace(DBM_3D, "        RightEncodedLineLocation = %X \r\n",
+					     (int)it6602data->de3dframe_config.RightEncodedLineLocation);
 				dbmsg_ftrace(DBM_3D, "        BlankingColor            = %X \r\n", (int)it6602data->de3dframe_config.BlankingColor);
 
 #else
@@ -4465,8 +4363,7 @@ unsigned char IT66021::IT6602_DE3DFrame(unsigned char ena_de3d)
 			}
 		}
 
-		if (it6602data->DE3DFormat_HDMIFlag) // 3D InfoFrame Packet Type is not valid
-		{
+		if (it6602data->DE3DFormat_HDMIFlag) { // 3D InfoFrame Packet Type is not valid
 #ifdef DEBUG_MODE_3D
 			dbmsg_trace(DBM_3D, "ITEHDMI - HDMI_3DFORMAT is OFF \r\n");
 #endif
@@ -4483,15 +4380,15 @@ unsigned char IT66021::IT6602_DE3DFrame(unsigned char ena_de3d)
 		}
 
 		/******************************  3D integration  *************************************/
-	}
-	else
-	{
+
+	} else {
 
 		//it6602data->f_de3dframe_hdmi = FALSE;
 		hdmirxwr(REG_RX_06A, 0x82);
 		hdmirxset(REG_RX_066_4_DE3DFrame, 0x10, 0x00); // Reg66[4] = 0 for disable 3D FP2FS
 		hdmirxset(REG_RX_085_5_En3DROut, 0x20, 0x00);  // Reg85[5] = 0 for disable 3DR output
 	}
+
 	return FALSE;
 }
 #endif
@@ -4524,56 +4421,53 @@ void IT66021::TMDSGet(void)
 
 	ucCurrentPort = hdmirxrd(REG_RX_051) & B_PORT_SEL;
 
-	if (ucCurrentPort == F_PORT_SEL_1)
-	{
+	if (ucCurrentPort == F_PORT_SEL_1) {
 		ucClk = hdmirxrd(REG_RX_092);
 		rddata = hdmirxrd(0x90);
 
-		if (ucClk != 0)
-		{
-			if (rddata & 0x04)
+		if (ucClk != 0) {
+			if (rddata & 0x04) {
 				ucTMDSClk = 2 * RCLKVALUE * 256 / ucClk;
-			else if (rddata & 0x08)
+
+			} else if (rddata & 0x08) {
 				ucTMDSClk = 4 * RCLKVALUE * 256 / ucClk;
-			else
+
+			} else {
 				ucTMDSClk = RCLKVALUE * 256 / ucClk;
+			}
 
 			HDMIRX_AUDIO_PRINTF((" TMDSGet() Port 1 TMDS org  = %d \r\n", (int)m_u16TMDSCLK));
 		}
-	}
-	else
-	{
-		if (hdmirxrd(REG_RX_P0_SYS_STATUS) & (B_P0_MHL_MODE)) // judge MHL mode
-		{
+
+	} else {
+		if (hdmirxrd(REG_RX_P0_SYS_STATUS) & (B_P0_MHL_MODE)) { // judge MHL mode
 			ucTMDSClk = PCLKGet();
 			//HDMIRX_AUDIO_PRINTF(("MHL use Pclk to calculate FS %d \r\n",(int) ucTMDSClk));
-		}
-		else //else HDMI mode
-		{
+
+		} else { //else HDMI mode
 			ucClk = hdmirxrd(REG_RX_091);
 			rddata = hdmirxrd(0x90);
 
-			if (ucClk != 0)
-			{
-				if (rddata & 0x01)
-				{
+			if (ucClk != 0) {
+				if (rddata & 0x01) {
 					ucTMDSClk = 2 * RCLKVALUE * 256 / ucClk;
-					else if (rddata & 0x02)
+					else if (rddata & 0x02) {
 						ucTMDSClk = 4 * RCLKVALUE * 256 / ucClk;
-					else ucTMDSClk = RCLKVALUE * 256 / ucClk;
+
+					} else { ucTMDSClk = RCLKVALUE * 256 / ucClk; }
 				}
+
 				//HDMIRX_AUDIO_PRINTF(("HDMI use TMDS to calculate FS %d \r\n",(int) ucTMDSClk));
 			}
 		}
+
 		HDMIRX_AUDIO_PRINTF((" TMDSGet() Port 0 TMDS org  = %d \r\n", (int)m_u16TMDSCLK));
 	}
 
-	if (m_u16TMDSCLK == 0)
-	{
+	if (m_u16TMDSCLK == 0) {
 		m_u16TMDSCLK = ucTMDSClk;
-	}
-	else
-	{
+
+	} else {
 		m_u16TMDSCLK = ((ucTMDSClk + m_u16TMDSCLK));
 		m_u16TMDSCLK /= 2;
 	}
@@ -4604,8 +4498,9 @@ void IT66021::AudioFsCal(void)
 	HDMIRX_AUDIO_PRINTF((" u32_N %ld \r\n", (unsigned long)u32_N));
 	HDMIRX_AUDIO_PRINTF((" u32_CTS %ld \r\n", (unsigned long)u32_CTS));
 
-	if ((u32_N == 0) || (u32_CTS == 0))
+	if ((u32_N == 0) || (u32_CTS == 0)) {
 		return;
+	}
 
 	TMDSGet();
 
@@ -4615,44 +4510,37 @@ void IT66021::AudioFsCal(void)
 
 #if 0
 	u8_FS = m_u16TMDSCLK;
-	HDMIRX_AUDIO_PRINTF(("m_u16TMDSCLK %d \r\n",(int) u8_FS));
-	u8_FS = (((u32_N*m_u16TMDSCLK*78)/u32_CTS)/10);
+	HDMIRX_AUDIO_PRINTF(("m_u16TMDSCLK %d \r\n", (int) u8_FS));
+	u8_FS = (((u32_N * m_u16TMDSCLK * 78) / u32_CTS) / 10);
 #endif
 	HDMIRX_AUDIO_PRINTF(("u8_FS %d \r\n", (int)u8_FS));
 
 	//Judge FS by FS calulate
-	if (u8_FS > 25 && u8_FS <= 38)
-	{
+	if (u8_FS > 25 && u8_FS <= 38) {
 		// FS=32k , Calu Value = 29k~36k
 		m_ForceFsValue = (B_32K);
-	}
-	else if (u8_FS > 38 && u8_FS <= 44)
-	{
+
+	} else if (u8_FS > 38 && u8_FS <= 44) {
 		// FS=44k , Calu Value = 41k~46k
 		m_ForceFsValue = (B_44P1K);
-	}
-	else if (u8_FS > 44 && u8_FS <= 58)
-	{
+
+	} else if (u8_FS > 44 && u8_FS <= 58) {
 		// FS=48k , Calu Value = 47k~51k
 		m_ForceFsValue = (B_48K);
-	}
-	else if (u8_FS > 78 && u8_FS <= 92)
-	{
+
+	} else if (u8_FS > 78 && u8_FS <= 92) {
 		// FS=88k , Calu Value = 85k~91k
 		m_ForceFsValue = (B_88P2K);
-	}
-	else if (u8_FS > 92 && u8_FS <= 106)
-	{
+
+	} else if (u8_FS > 92 && u8_FS <= 106) {
 		// FS=96k , Calu Value = 93k~99k
 		m_ForceFsValue = (B_96K);
-	}
-	else if (u8_FS > 166 && u8_FS <= 182)
-	{
+
+	} else if (u8_FS > 166 && u8_FS <= 182) {
 		// FS=176k , Calu Value = 173k~179k
 		m_ForceFsValue = (B_176P4K);
-	}
-	else if (u8_FS > 182 && u8_FS <= 202)
-	{
+
+	} else if (u8_FS > 182 && u8_FS <= 202) {
 		// FS=192k , Calu Value = 188k~195k
 		m_ForceFsValue = (B_192K);
 	}
@@ -4660,8 +4548,8 @@ void IT66021::AudioFsCal(void)
 	uc = hdmirxrd(REG_RX_0AE); // REG_RX_AUD_CHSTAT3
 	HDMIRX_AUDIO_PRINTF(("REG_RX_0AE %x ,", (int)(uc & M_FS)));
 	HDMIRX_AUDIO_PRINTF(("m_ForceFsValue %x \r\n", (int)(m_ForceFsValue)));
-	if ((uc & M_FS) == (m_ForceFsValue))
-	{
+
+	if ((uc & M_FS) == (m_ForceFsValue)) {
 		m_AudioChannelStatusErrorCount = 0;
 		// no need to enable Force FS mode
 		HDMIRX_AUDIO_PRINTF(("CHS_FS %x , !!!No need !!! to enable Force FS mode \r\n", (int)(uc & M_FS)));
@@ -4669,8 +4557,7 @@ void IT66021::AudioFsCal(void)
 		return;
 	}
 
-	if (++m_AudioChannelStatusErrorCount > MAX_AUDIO_CHANNEL_STATUS_ERROR)
-	{
+	if (++m_AudioChannelStatusErrorCount > MAX_AUDIO_CHANNEL_STATUS_ERROR) {
 		m_AudioChannelStatusErrorCount = 0;
 		// a. if find Audio Error in a period timers,assue the FS message is wrong,then try to force FS setting.
 		// b. set Reg0x74[6]=1=> select Force FS mode.
@@ -4689,23 +4576,19 @@ void IT66021::AudioFsCal(void)
 #endif
 
 void IT66021::it6602HPDCtrl(unsigned char ucport, unsigned char ucEnable)
-{	
+{
 	// struct it6602_dev_data *it6602data = get_it6602_dev_data();
-	if (ucport == 0)
-	{
-		if (ucEnable == 0)
-		{
+	if (ucport == 0) {
+		if (ucEnable == 0) {
 			// Disable HDMI DDC Bus to access ITEHDMI EDID RAM
 			//hdmirxset(REG_RX_0C0, 0x01, 0x01);                            // HDMI RegC0[1:0]=11 for disable HDMI DDC bus to access EDID RAM
 			IT_INFO("Port 0 HPD HDMI 00000 \r\n");
 			chgbank(1);
-			hdmirxset(REG_RX_1B0, 0x03, 0x01); //clear port 0 HPD=1 for EDID update   
+			hdmirxset(REG_RX_1B0, 0x03, 0x01); //clear port 0 HPD=1 for EDID update
 			chgbank(0);
-		}
-		else
-		{
-			if ((hdmirxrd(REG_RX_P0_SYS_STATUS) & B_P0_PWR5V_DET))
-			{
+
+		} else {
+			if ((hdmirxrd(REG_RX_P0_SYS_STATUS) & B_P0_PWR5V_DET)) {
 				// Enable HDMI DDC bus to access ITEHDMI EDID RAM
 				//hdmirxset(REG_RX_0C0, 0x01, 0x00);                        // HDMI RegC0[1:0]=00 for enable HDMI DDC bus to access EDID RAM
 				IT_INFO("Port 0 HPD HDMI 11111 \r\n");
@@ -4715,6 +4598,7 @@ void IT66021::it6602HPDCtrl(unsigned char ucport, unsigned char ucEnable)
 			}
 		}
 	}
+
 // #if defined(_IT6602_) || defined(_IT66023_)
 
 // 	else
@@ -4743,7 +4627,7 @@ char IT66021::	it66021_init(void)
 {
 	char ret = false;
 
-	
+
 	it6602HPDCtrl(1, 0); // HDMI port , set HPD = 0
 
 	usleep(10 * 1000);
@@ -4752,29 +4636,28 @@ char IT66021::	it66021_init(void)
 
 	it6602HPDCtrl(1, 1);
 
-	if (FALSE != ret)
-	{
+	if (FALSE != ret) {
 		// mhlrxwr(MHL_RX_0A,0xFF);
 		// mhlrxwr(MHL_RX_08,0xFF);
 		// mhlrxwr(MHL_RX_09,0xFF);
 
-	    hdmirxset(REG_RX_063,0xFF,0x3F);
-	    hdmirxset(REG_RX_012,0xFF,0xF8);
+		hdmirxset(REG_RX_063, 0xFF, 0x3F);
+		hdmirxset(REG_RX_012, 0xFF, 0xF8);
 
-	    IT_INFO("REG_RX_012=%2x",hdmirxrd(REG_RX_012));
-	    IT_INFO("REG_RX_063=%2x",hdmirxrd(REG_RX_063));
-	    // IT_INFO("MHL_RX_0A=%2x", mhlrxrd(MHL_RX_0A));
-	    // IT_INFO("MHL_RX_08=%2x", mhlrxrd(MHL_RX_08));
-	    // IT_INFO("MHL_RX_09=%2x", mhlrxrd(MHL_RX_09));
+		IT_INFO("REG_RX_012=%2x", hdmirxrd(REG_RX_012));
+		IT_INFO("REG_RX_063=%2x", hdmirxrd(REG_RX_063));
+		// IT_INFO("MHL_RX_0A=%2x", mhlrxrd(MHL_RX_0A));
+		// IT_INFO("MHL_RX_08=%2x", mhlrxrd(MHL_RX_08));
+		// IT_INFO("MHL_RX_09=%2x", mhlrxrd(MHL_RX_09));
 	}
 
 
-	uint32_t u32_HTotal   = ((hdmirxrd(0x9D)&0x3F)<<8) + hdmirxrd(0x9C);
-    uint32_t u32_HActive  = ((hdmirxrd(0x9F)&0x3F)<<8) + hdmirxrd(0x9E);
+	uint32_t u32_HTotal   = ((hdmirxrd(0x9D) & 0x3F) << 8) + hdmirxrd(0x9C);
+	uint32_t u32_HActive  = ((hdmirxrd(0x9F) & 0x3F) << 8) + hdmirxrd(0x9E);
+
+	uint32_t u32_VTotal   = ((hdmirxrd(0xA4) & 0x0F) << 8) + hdmirxrd(0xA3);
+	uint32_t u32_VActive  = ((hdmirxrd(0xA4) & 0xF0) << 4) + hdmirxrd(0xA5);
 
-	uint32_t u32_VTotal   = ((hdmirxrd(0xA4)&0x0F)<<8) + hdmirxrd(0xA3);
-	uint32_t u32_VActive  = ((hdmirxrd(0xA4)&0xF0)<<4) + hdmirxrd(0xA5);
-	
 	IT_INFO("init u32_HTotal = %d \n", u32_HTotal);
 	IT_INFO("init u32_HActive = %d \n", u32_HActive);
 	IT_INFO("init u32_VTotal = %d \n", u32_VTotal);
@@ -4798,20 +4681,21 @@ char IT66021::	it66021_init(void)
 //xxxxx 2014-0529 //HDCP Content On/Off
 void IT66021::IT6602_ManualVideoTristate(unsigned char bOff)
 {
-	if (bOff)
-	{
-		hdmirxset(REG_RX_053, (B_VDGatting | B_VIOSel), (B_VDGatting | B_VIOSel)); //Reg53[7][5] = 11    // for enable B_VDIO_GATTING and VIO_SEL
+	if (bOff) {
+		hdmirxset(REG_RX_053, (B_VDGatting | B_VIOSel),
+			  (B_VDGatting | B_VIOSel)); //Reg53[7][5] = 11    // for enable B_VDIO_GATTING and VIO_SEL
 		hdmirxset(REG_RX_052, (B_DisVAutoMute), (B_DisVAutoMute));				   //Reg52[5] = 1 for disable Auto video MUTE
 		hdmirxset(REG_RX_053, (B_TriVDIO), (0x00));								   //Reg53[2:0] = 000;         // 0 for enable video io data output
 		IT_INFO("+++++++++++ Manual Video / Audio off  +++++++++++++++++\n");
-	}
-	else
-	{
+
+	} else {
 		hdmirxset(REG_RX_053, (B_TriSYNC), (0x00));								   //Reg53[0] = 0;                 // for enable video sync
 		hdmirxset(REG_RX_053, (B_TriVDIO), (0x00));								   //Reg53[3:1] = 000;         // 0 for enable video io data output
-		hdmirxset(REG_RX_053, (B_TriVDIO), (B_TriVDIO));						   //Reg53[2:0] = 111;         // 1 for enable tri-state of video io data
+		hdmirxset(REG_RX_053, (B_TriVDIO), (
+				  B_TriVDIO));						   //Reg53[2:0] = 111;         // 1 for enable tri-state of video io data
 		hdmirxset(REG_RX_053, (B_TriVDIO), (0x00));								   //Reg53[2:0] = 000;         // 0 for enable video io data output
-		hdmirxset(REG_RX_053, (B_VDGatting | B_VIOSel), (B_VDGatting | B_VIOSel)); //Reg53[7][5] = 11    // for enable B_VDIO_GATTING and VIO_SEL
+		hdmirxset(REG_RX_053, (B_VDGatting | B_VIOSel),
+			  (B_VDGatting | B_VIOSel)); //Reg53[7][5] = 11    // for enable B_VDIO_GATTING and VIO_SEL
 		hdmirxset(REG_RX_053, (B_VDGatting | B_VIOSel), (B_VIOSel));			   //Reg53[7][5] = 01    // for disable B_VDIO_GATTING
 		IT_INFO("+++++++++++ Manual Video on  +++++++++++++++++\n");
 	}
@@ -4823,25 +4707,21 @@ void IT66021::IT6602_ManualVideoTristate(unsigned char bOff)
 void IT66021::HDMIStartEQDetect(struct it6602_eq_data *ucEQPort)
 {
 	unsigned char ucPortSel;
-	if (ucEQPort->ucPortID == F_PORT_SEL_0)
-	{
+
+	if (ucEQPort->ucPortID == F_PORT_SEL_0) {
 		// for MHL mode , there are no need to adjust EQ for long cable.
-		if (hdmirxrd(REG_RX_P0_SYS_STATUS) & (B_P0_MHL_MODE))
-		{
+		if (hdmirxrd(REG_RX_P0_SYS_STATUS) & (B_P0_MHL_MODE)) {
 			return;
 		}
 	}
 
-	if (ucEQPort->ucEQState == 0xFF)
-	{
+	if (ucEQPort->ucEQState == 0xFF) {
 		ucPortSel = hdmirxrd(REG_RX_051) & B_PORT_SEL;
 
-		if (ucPortSel == ucEQPort->ucPortID)
-		{
+		if (ucPortSel == ucEQPort->ucPortID) {
 			HDMISwitchEQstate(ucEQPort, 0); // for SCDT off state
-		}
-		else
-		{
+
+		} else {
 			HDMISwitchEQstate(ucEQPort, EQSTATE_WAIT + 1); //for SCDT on state
 		}
 
@@ -4856,25 +4736,24 @@ void IT66021::HDMIStartEQDetect(struct it6602_eq_data *ucEQPort)
 
 void IT66021::HDMISetEQValue(struct it6602_eq_data *ucEQPort, unsigned char ucIndex)
 {
-	if (ucIndex < MaxEQIndex)
-	{
-		if (ucEQPort->ucPortID == F_PORT_SEL_0)
-		{
+	if (ucIndex < MaxEQIndex) {
+		if (ucEQPort->ucPortID == F_PORT_SEL_0) {
 #ifdef _SUPPORT_AUTO_EQ_
 			ucEQMode[F_PORT_SEL_0] = 1; // 1 for Manual Mode
 #endif
 			hdmirxset(REG_RX_026, 0x20, 0x20); //07-04 add for adjust EQ
 			hdmirxwr(REG_RX_027, IT6602EQTable[ucIndex]);
-			IT_INFO("Port=%X ,ucIndex = %X ,HDMISetEQValue Reg027 = %X \r\n", (int)ucEQPort->ucPortID, (int)ucIndex, (int)hdmirxrd(REG_RX_027));
-		}
-		else
-		{
+			IT_INFO("Port=%X ,ucIndex = %X ,HDMISetEQValue Reg027 = %X \r\n", (int)ucEQPort->ucPortID, (int)ucIndex,
+				(int)hdmirxrd(REG_RX_027));
+
+		} else {
 #ifdef _SUPPORT_AUTO_EQ_
 			ucEQMode[F_PORT_SEL_1] = 1; // 1 for Manual Mode
 #endif
 			hdmirxset(REG_RX_03E, 0x20, 0x20); //07-04 add for adjust EQ
 			hdmirxwr(REG_RX_03F, IT6602EQTable[ucIndex]);
-			IT_INFO("Port=%X ,ucIndex = %X ,HDMISetEQValue Reg03F = %X \r\n", (int)ucEQPort->ucPortID, (int)ucIndex, (int)hdmirxrd(REG_RX_03F));
+			IT_INFO("Port=%X ,ucIndex = %X ,HDMISetEQValue Reg03F = %X \r\n", (int)ucEQPort->ucPortID, (int)ucIndex,
+				(int)hdmirxrd(REG_RX_03F));
 		}
 	}
 }
@@ -4884,17 +4763,19 @@ void IT66021::HDMISwitchEQstate(struct it6602_eq_data *ucEQPort, unsigned char s
 	ucEQPort->ucEQState = state;
 	IT_INFO("!!! Port=%X ,HDMISwitchEQstate %X \r\n", (int)ucEQPort->ucPortID, (int)ucEQPort->ucEQState);
 
-	switch (ucEQPort->ucEQState)
-	{
+	switch (ucEQPort->ucEQState) {
 	case EQSTATE_START:
 		HDMISetEQValue(ucEQPort, 0);
 		break;
+
 	case EQSTATE_LOW:
 		HDMISetEQValue(ucEQPort, 1);
 		break;
+
 	case EQSTATE_MIDDLE:
 		HDMISetEQValue(ucEQPort, 2);
 		break;
+
 	case EQSTATE_HIGH:
 		HDMISetEQValue(ucEQPort, 3);
 		break;
@@ -4921,22 +4802,19 @@ void IT66021::HDMICheckSCDTon(struct it6602_eq_data *ucEQPort)
 
 	ucCurrentPort = hdmirxrd(REG_RX_051) & B_PORT_SEL;
 
-	if (ucEQPort->ucPortID != ucCurrentPort)
-	{
+	if (ucEQPort->ucPortID != ucCurrentPort) {
 		return;
 	}
 
-	if (ucEQPort->ucPortID == F_PORT_SEL_1)
-	{
+	if (ucEQPort->ucPortID == F_PORT_SEL_1) {
 		ucStatus = hdmirxrd(REG_RX_P1_SYS_STATUS);
 		// !!! check ECC error register  !!!
 		Receive_Err = hdmirxrd(REG_RX_0B7);
 		hdmirxwr(REG_RX_0B7, Receive_Err);
 
 		ucHDCP = hdmirxrd(REG_RX_095);
-	}
-	else
-	{
+
+	} else {
 		ucStatus = hdmirxrd(REG_RX_P0_SYS_STATUS);
 		// !!! check ECC error register  !!!
 		Receive_Err = hdmirxrd(REG_RX_0B2);
@@ -4945,37 +4823,31 @@ void IT66021::HDMICheckSCDTon(struct it6602_eq_data *ucEQPort)
 		ucHDCP = hdmirxrd(REG_RX_093);
 	}
 
-	if ((ucStatus & (B_P0_SCDT | B_P0_PWR5V_DET | B_P0_RXCK_VALID)) == (B_P0_PWR5V_DET | B_P0_RXCK_VALID))
-	{
+	if ((ucStatus & (B_P0_SCDT | B_P0_PWR5V_DET | B_P0_RXCK_VALID)) == (B_P0_PWR5V_DET | B_P0_RXCK_VALID)) {
 		ucEQPort->ucECCfailCount++;
 	}
 
 	IT_INFO("Port=%d, CheckSCDTon=%d, Receive_Err=%X, ucECCfailCount=%X, SCDT=%X, HDCP=%X \r\n",
-			 (int)ucEQPort->ucPortID, (int)ucEQPort->ucEQState, (int)Receive_Err, (int)ucEQPort->ucECCfailCount, (int)ucStatus, (int)ucHDCP);
+		(int)ucEQPort->ucPortID, (int)ucEQPort->ucEQState, (int)Receive_Err, (int)ucEQPort->ucECCfailCount, (int)ucStatus,
+		(int)ucHDCP);
 
-	if ((Receive_Err & 0xC0) != 0x00)
-	{
+	if ((Receive_Err & 0xC0) != 0x00) {
 		ucEQPort->ucECCvalue++;
 
 		IT6602_HDCP_ContentOff(ucEQPort->ucPortID, 1);
 
-		if (ucEQPort->ucECCvalue > ((MINECCFAILCOUNT / 2)))
-		{
+		if (ucEQPort->ucECCvalue > ((MINECCFAILCOUNT / 2))) {
 			ucEQPort->ucECCvalue = 0;
 			IT_INFO("HDMICheckSCDTon() for ECC / Deskew issue !!!");
 
-			if (ucEQPort->ucPortID == F_PORT_SEL_1)
-			{
-				if (hdmirxrd(REG_RX_038) == 0x00)
-				{
+			if (ucEQPort->ucPortID == F_PORT_SEL_1) {
+				if (hdmirxrd(REG_RX_038) == 0x00) {
 					hdmirxwr(REG_RX_038, 0x3F); // Dr. Liu suggestion to 0x00
 					IT_INFO("Port 1 Reg38=%X !!!\n", (int)hdmirxrd(REG_RX_038));
 				}
-			}
-			else
-			{
-				if (hdmirxrd(REG_RX_020) == 0x00)
-				{
+
+			} else {
+				if (hdmirxrd(REG_RX_020) == 0x00) {
 					hdmirxwr(REG_RX_020, 0x3F); // Dr. Liu suggestion to 0x00
 					IT_INFO("Port 0 Reg20=%X !!!\n", (int)hdmirxrd(REG_RX_020));
 				}
@@ -4983,13 +4855,12 @@ void IT66021::HDMICheckSCDTon(struct it6602_eq_data *ucEQPort)
 		}
 	}
 
-	if (ucEQPort->ucEQState == EQSTATE_WAIT - 1)
-	{
+	if (ucEQPort->ucEQState == EQSTATE_WAIT - 1) {
 		IT_INFO("Port=%d, CheckSCDTon=%d, Receive_Err=%X, ucECCfailCount=%X, SCDT=%X, HDCP=%X \r\n",
-				 (int)ucEQPort->ucPortID, (int)ucEQPort->ucEQState, (int)Receive_Err, (int)ucEQPort->ucECCfailCount, (int)ucStatus, (int)ucHDCP);
+			(int)ucEQPort->ucPortID, (int)ucEQPort->ucEQState, (int)Receive_Err, (int)ucEQPort->ucECCfailCount, (int)ucStatus,
+			(int)ucHDCP);
 
-		if ((Receive_Err & 0xC0) == 0xC0)
-		{
+		if ((Receive_Err & 0xC0) == 0xC0) {
 			IT_INFO("HDMICheckSCDTon() CDR reset for Port %d ECC_TIMEOUT !!!\n", ucCurrentPort);
 			hdmirx_ECCTimingOut(ucCurrentPort);
 
@@ -4998,37 +4869,29 @@ void IT66021::HDMICheckSCDTon(struct it6602_eq_data *ucEQPort)
 		}
 
 #ifdef _SUPPORT_AUTO_EQ_
-		if ((ucEQPort->ucECCfailCount) == 0)
-		{
-			if (ucEQPort->ucPortID == F_PORT_SEL_1)
-			{
-				if (ucEQMode[F_PORT_SEL_1] == 0) // verfiy Auto EQ Value wehn auto EQ finish
-				{
+
+		if ((ucEQPort->ucECCfailCount) == 0) {
+			if (ucEQPort->ucPortID == F_PORT_SEL_1) {
+				if (ucEQMode[F_PORT_SEL_1] == 0) { // verfiy Auto EQ Value wehn auto EQ finish
 
 					if (((ucChannelB[F_PORT_SEL_1] & 0x7F) < 0x0F) ||
-						((ucChannelG[F_PORT_SEL_1] & 0x7F) < 0x0F) ||
-						((ucChannelR[F_PORT_SEL_1] & 0x7F) < 0x0F))
-					{
+					    ((ucChannelG[F_PORT_SEL_1] & 0x7F) < 0x0F) ||
+					    ((ucChannelR[F_PORT_SEL_1] & 0x7F) < 0x0F)) {
 						ucResult = 1; // 1 for EQ start
 					}
 				}
-			}
-			else
-			{
-				if (ucEQMode[F_PORT_SEL_0] == 0) // verfiy Auto EQ Value when auto EQ finish
-				{
-					if (hdmirxrd(REG_RX_P0_SYS_STATUS) & (B_P0_MHL_MODE))
-					{
-						if ((ucChannelB[F_PORT_SEL_0] & 0x7F) < 0x0F)
-						{
+
+			} else {
+				if (ucEQMode[F_PORT_SEL_0] == 0) { // verfiy Auto EQ Value when auto EQ finish
+					if (hdmirxrd(REG_RX_P0_SYS_STATUS) & (B_P0_MHL_MODE)) {
+						if ((ucChannelB[F_PORT_SEL_0] & 0x7F) < 0x0F) {
 							ucResult = 1; // 1 for EQ start
 						}
-					}
-					else
-					{
+
+					} else {
 						if (((ucChannelB[F_PORT_SEL_0] & 0x7F) < 0x0F) ||
-							((ucChannelG[F_PORT_SEL_0] & 0x7F) < 0x0F) ||
-							((ucChannelR[F_PORT_SEL_0] & 0x7F) < 0x0F))
+						    ((ucChannelG[F_PORT_SEL_0] & 0x7F) < 0x0F) ||
+						    ((ucChannelR[F_PORT_SEL_0] & 0x7F) < 0x0F))
 
 						{
 							ucResult = 1; // 1 for EQ start
@@ -5037,12 +4900,12 @@ void IT66021::HDMICheckSCDTon(struct it6602_eq_data *ucEQPort)
 				}
 			}
 
-			if (ucResult == 0) // no need to do manual EQ adjust when SCDT always On !!!
-			{
+			if (ucResult == 0) { // no need to do manual EQ adjust when SCDT always On !!!
 				HDMISwitchEQstate(ucEQPort, EQSTATE_END);
 				return;
 			}
 		}
+
 #endif
 		HDMISwitchEQstate(ucEQPort, EQSTATE_WAIT);
 	}
@@ -5061,8 +4924,7 @@ void IT66021::HDMIPollingErrorCount(struct it6602_eq_data *ucEQPort)
 	unsigned char ucCurrentPort;
 	ucCurrentPort = hdmirxrd(REG_RX_051) & B_PORT_SEL;
 
-	if (ucEQPort->ucPortID == F_PORT_SEL_1)
-	{
+	if (ucEQPort->ucPortID == F_PORT_SEL_1) {
 		ucStatus = hdmirxrd(REG_RX_P1_SYS_STATUS);
 		// !!! check ECC error register  !!!
 		Receive_Err = hdmirxrd(REG_RX_0B7);
@@ -5078,9 +4940,8 @@ void IT66021::HDMIPollingErrorCount(struct it6602_eq_data *ucEQPort)
 		hdmirxwr(REG_RX_0BB, CrtErr);
 
 		ucHDCP = hdmirxrd(REG_RX_095);
-	}
-	else
-	{
+
+	} else {
 		ucStatus = hdmirxrd(REG_RX_P0_SYS_STATUS);
 		// !!! check ECC error register  !!!
 		Receive_Err = hdmirxrd(REG_RX_0B2);
@@ -5098,89 +4959,85 @@ void IT66021::HDMIPollingErrorCount(struct it6602_eq_data *ucEQPort)
 		ucHDCP = hdmirxrd(REG_RX_093);
 	}
 
-	if (ucCurrentPort == ucEQPort->ucPortID)
-	{
-		if ((ucStatus & B_P0_SCDT) == 0x00)
-		{
+	if (ucCurrentPort == ucEQPort->ucPortID) {
+		if ((ucStatus & B_P0_SCDT) == 0x00) {
 			Receive_Err = 0xFF;
 			ucEQPort->ucECCfailCount |= 0x80;
 		}
 	}
 
 	IT_INFO("Port=%d ,EQState2No=%d, Receive_Err=%X, HDCP=%X \r\n",
-			 (int)ucEQPort->ucPortID, (int)ucEQPort->ucEQState, (int)Receive_Err, (int)ucHDCP);
+		(int)ucEQPort->ucPortID, (int)ucEQPort->ucEQState, (int)Receive_Err, (int)ucHDCP);
 
 #if 1
-	if (Pkt_Err == 0xFF || Code_Err == 0xFF)
-	{
+
+	if (Pkt_Err == 0xFF || Code_Err == 0xFF) {
 		ucEQPort->ucPkt_Err++; // judge whether CDR reset
-	}
-	else
-	{
+
+	} else {
 		ucEQPort->ucPkt_Err = 0;
 	}
 
-	if (ucEQPort->ucPkt_Err > (MINECCFAILCOUNT - 2))
-	{
+	if (ucEQPort->ucPkt_Err > (MINECCFAILCOUNT - 2)) {
 
-		if (ucEQPort->ucEQState > EQSTATE_START)
-		{
+		if (ucEQPort->ucEQState > EQSTATE_START) {
 
 			IT_INFO("1111111111111111111111111111111111111111111111111111111111111111111111111\r\n");
 
-			if (ucEQPort->ucPortID == F_PORT_SEL_1)
-			{
+			if (ucEQPort->ucPortID == F_PORT_SEL_1) {
 				Code_Err = hdmirxrd(REG_RX_0B9);
 				hdmirxwr(REG_RX_0B9, Code_Err);
 
-				if (Code_Err == 0xFF)
-				{
-					if (hdmirxrd(REG_RX_038) == 0x00)
-						hdmirxwr(REG_RX_038, 0x3F); // Dr. Liu suggestion to 0x00
-					else
-						hdmirxwr(REG_RX_038, 0x00); // Dr. Liu suggestion to 0x3F
+				if (Code_Err == 0xFF) {
+					if (hdmirxrd(REG_RX_038) == 0x00) {
+						hdmirxwr(REG_RX_038, 0x3F);        // Dr. Liu suggestion to 0x00
+
+					} else {
+						hdmirxwr(REG_RX_038, 0x00);        // Dr. Liu suggestion to 0x3F
+					}
+
 					IT_INFO("Port 1 Reg38=%X !!!\n", (int)hdmirxrd(REG_RX_038));
 				}
-			}
-			else
-			{
+
+			} else {
 				Code_Err = hdmirxrd(REG_RX_0B4);
 				hdmirxwr(REG_RX_0B4, Code_Err);
 
-				if (Code_Err == 0xFF)
-				{
-					if (hdmirxrd(REG_RX_020) == 0x00)
-						hdmirxwr(REG_RX_020, 0x3F); // Dr. Liu suggestion to 0x00
-					else
-						hdmirxwr(REG_RX_020, 0x00); // Dr. Liu suggestion to 0x3F
+				if (Code_Err == 0xFF) {
+					if (hdmirxrd(REG_RX_020) == 0x00) {
+						hdmirxwr(REG_RX_020, 0x3F);        // Dr. Liu suggestion to 0x00
+
+					} else {
+						hdmirxwr(REG_RX_020, 0x00);        // Dr. Liu suggestion to 0x3F
+					}
 
 					IT_INFO("Port 0 Reg20=%X !!!\n", (int)hdmirxrd(REG_RX_020));
 				}
 			}
+
 			IT_INFO("1111111111111111111111111111111111111111111111111111111111111111111111111\r\n");
 
-			if (ucEQPort->ucPortID == F_PORT_SEL_0)
-			{
+			if (ucEQPort->ucPortID == F_PORT_SEL_0) {
 
 				hdmirxset(REG_RX_011, (B_P0_DCLKRST | B_P0_CDRRST), (B_P0_DCLKRST | B_P0_CDRRST /*|B_P0_SWRST*/));
 				hdmirxset(REG_RX_011, (B_P0_DCLKRST | B_P0_CDRRST), 0x00);
 				IT_INFO(" HDMIPollingErrorCount( ) Port 0 CDR reset !!!!!!!!!!!!!!!!!! \r\n");
-			}
-			else
-			{
+
+			} else {
 				hdmirxset(REG_RX_018, (B_P1_DCLKRST | B_P1_CDRRST), (B_P1_DCLKRST | B_P1_CDRRST /*|B_P1_SWRST*/));
 				hdmirxset(REG_RX_018, (B_P1_DCLKRST | B_P1_CDRRST), 0x00);
 				IT_INFO(" HDMIPollingErrorCount( ) Port 1 CDR reset !!!!!!!!!!!!!!!!!! \r\n");
 			}
 		}
+
 		ucEQPort->ucPkt_Err = 0;
 		ucEQPort->ucECCfailCount |= 0x40;
 		ucEQPort->ucECCfailCount &= 0xF0;
 	}
+
 #endif
 
-	if (Receive_Err != 0)
-	{
+	if (Receive_Err != 0) {
 		IT_INFO("Video_Err = %X \r\n", (int)Video_Err);
 		IT_INFO("Code_Err = %X \r\n", (int)Code_Err);
 		IT_INFO("Pkt_Err = %X \r\n", (int)Pkt_Err);
@@ -5188,55 +5045,55 @@ void IT66021::HDMIPollingErrorCount(struct it6602_eq_data *ucEQPort)
 
 		ucEQPort->ucECCvalue++;
 		ucEQPort->ucECCfailCount++;
-	}
-	else
-	{
+
+	} else {
 		ucEQPort->ucECCfailCount = 0;
 	}
 
 #if 1
-	if ((ucEQPort->ucECCfailCount & 0x7F) < (0x40)) // before CDR reset , dont care pkt_error and code_error
-	{
 
-		if (Pkt_Err == 0xFF || Code_Err == 0xFF)
+	if ((ucEQPort->ucECCfailCount & 0x7F) < (0x40)) { // before CDR reset , dont care pkt_error and code_error
+
+		if (Pkt_Err == 0xFF || Code_Err == 0xFF) {
 			return;
+		}
 	}
+
 #endif
 
-	if ((ucEQPort->ucECCfailCount & 0x0F) > (MINECCFAILCOUNT - 2))
-	{
+	if ((ucEQPort->ucECCfailCount & 0x0F) > (MINECCFAILCOUNT - 2)) {
 
 		ucEQPort->ucECCvalue = MAXECCWAIT;
 
 		ucCurrentPort = hdmirxrd(REG_RX_051) & B_PORT_SEL;
 
-		if (ucEQPort->ucPortID == F_PORT_SEL_1)
-		{
+		if (ucEQPort->ucPortID == F_PORT_SEL_1) {
 			ucStatus = hdmirxrd(REG_RX_P1_SYS_STATUS);
-		}
-		else
-		{
+
+		} else {
 			ucStatus = hdmirxrd(REG_RX_P0_SYS_STATUS);
 		}
 
-		if (ucCurrentPort == ucEQPort->ucPortID)
-		{
-			if (((ucStatus & B_P0_SCDT) == 0x00) || ((ucEQPort->ucECCfailCount & 0x80) != 0x00))
-			{
+		if (ucCurrentPort == ucEQPort->ucPortID) {
+			if (((ucStatus & B_P0_SCDT) == 0x00) || ((ucEQPort->ucECCfailCount & 0x80) != 0x00)) {
 				ucEQPort->ucECCvalue = MAXECCWAIT | 0x80; // 0x80 for Identify SCDT off with Ecc error
 			}
 		}
 
 		StoreEccCount(ucEQPort); // abnormal judge ucECCvalue mode
 
-		if (ucEQPort->ucEQState < EQSTATE_START)
+		if (ucEQPort->ucEQState < EQSTATE_START) {
 			HDMISwitchEQstate(ucEQPort, EQSTATE_START);
-		else if (ucEQPort->ucEQState < EQSTATE_LOW)
+
+		} else if (ucEQPort->ucEQState < EQSTATE_LOW) {
 			HDMISwitchEQstate(ucEQPort, EQSTATE_LOW);
-		else if (ucEQPort->ucEQState < EQSTATE_MIDDLE)
+
+		} else if (ucEQPort->ucEQState < EQSTATE_MIDDLE) {
 			HDMISwitchEQstate(ucEQPort, EQSTATE_MIDDLE);
-		else if (ucEQPort->ucEQState <= EQSTATE_HIGH)
+
+		} else if (ucEQPort->ucEQState <= EQSTATE_HIGH) {
 			HDMISwitchEQstate(ucEQPort, EQSTATE_HIGH);
+		}
 	}
 }
 
@@ -5245,19 +5102,21 @@ void IT66021::HDMIJudgeECCvalue(struct it6602_eq_data *ucEQPort)
 	IT_INFO("!!! HDMI Judge ECCvalue( ) %X!!! \r\n", (int)ucEQPort->ucECCvalue);
 	StoreEccCount(ucEQPort); // normal judge ucECCvalue mode
 
-	if ((ucEQPort->ucECCvalue) > (MAXECCWAIT / 2))
-	{
-		if (ucEQPort->ucEQState == EQSTATE_START)
+	if ((ucEQPort->ucECCvalue) > (MAXECCWAIT / 2)) {
+		if (ucEQPort->ucEQState == EQSTATE_START) {
 			HDMISwitchEQstate(ucEQPort, EQSTATE_START);
-		else if (ucEQPort->ucEQState == EQSTATE_LOW)
+
+		} else if (ucEQPort->ucEQState == EQSTATE_LOW) {
 			HDMISwitchEQstate(ucEQPort, EQSTATE_LOW);
-		else if (ucEQPort->ucEQState == EQSTATE_MIDDLE)
+
+		} else if (ucEQPort->ucEQState == EQSTATE_MIDDLE) {
 			HDMISwitchEQstate(ucEQPort, EQSTATE_MIDDLE);
-		else if (ucEQPort->ucEQState == EQSTATE_HIGH)
+
+		} else if (ucEQPort->ucEQState == EQSTATE_HIGH) {
 			HDMISwitchEQstate(ucEQPort, EQSTATE_HIGH);
-	}
-	else
-	{
+		}
+
+	} else {
 		HDMISwitchEQstate(ucEQPort, EQSTATE_END); // quit EQadjust( )
 	}
 
@@ -5271,10 +5130,10 @@ void IT66021::HDMIAdjustEQ(struct it6602_eq_data *ucEQPort)
 	unsigned char ucCurrentPort;
 	ucCurrentPort = hdmirxrd(REG_RX_051) & B_PORT_SEL;
 
-	switch (ucEQPort->ucEQState)
-	{
+	switch (ucEQPort->ucEQState) {
 	case EQSTATE_WAIT:
 		break;
+
 	case EQSTATE_START:
 	case EQSTATE_LOW:
 	case EQSTATE_MIDDLE:
@@ -5292,9 +5151,12 @@ void IT66021::HDMIAdjustEQ(struct it6602_eq_data *ucEQPort)
 		ucEQPort->f_manualEQadjust = FALSE;
 		ucEQPort->ucEQState = 0xFF;
 
-		if (ucEQPort->ucPortID == ucCurrentPort)
+		if (ucEQPort->ucPortID == ucCurrentPort) {
 			IT6602VideoCountClr();
+		}
+
 		break;
+
 	case 0xff:
 		IT_INFO("====================== f_manualEQadjust = FALSE ====================== \r\n");
 
@@ -5302,18 +5164,19 @@ void IT66021::HDMIAdjustEQ(struct it6602_eq_data *ucEQPort)
 		break;
 	}
 
-	if (ucEQPort->ucEQState != 0xFF)
-	{
-		if (ucEQPort->ucEQState < EQSTATE_WAIT) //20120410
+	if (ucEQPort->ucEQState != 0xFF) {
+		if (ucEQPort->ucEQState < EQSTATE_WAIT) { //20120410
 			HDMICheckSCDTon(ucEQPort);
-		else if (ucEQPort->ucEQState < EQSTATE_HIGH)
+
+		} else if (ucEQPort->ucEQState < EQSTATE_HIGH) {
 			HDMIPollingErrorCount(ucEQPort);
+		}
+
 		//		else
 		//			HDMICheckErrorCount(ucEQPort);
 		ucEQPort->ucEQState++;
-	}
-	else
-	{
+
+	} else {
 		ucEQPort->f_manualEQadjust = FALSE;
 	}
 }
@@ -5323,12 +5186,13 @@ void IT66021::StoreEccCount(struct it6602_eq_data *ucEQPort)
 {
 	IT_INFO("StoreEccCount() ucEQPort->ucECCvalue = %02X \r\n", (int)ucEQPort->ucECCvalue);
 
-	if (ucEQPort->ucEQState <= EQSTATE_LOW)
+	if (ucEQPort->ucEQState <= EQSTATE_LOW) {
 		ucEQPort->ErrorCount[0] = ucEQPort->ucECCvalue;
-	else if (ucEQPort->ucEQState <= EQSTATE_MIDDLE)
+
+	} else if (ucEQPort->ucEQState <= EQSTATE_MIDDLE) {
 		ucEQPort->ErrorCount[1] = ucEQPort->ucECCvalue;
-	else if (ucEQPort->ucEQState <= EQSTATE_HIGH)
-	{
+
+	} else if (ucEQPort->ucEQState <= EQSTATE_HIGH) {
 		ucEQPort->ErrorCount[2] = ucEQPort->ucECCvalue;
 		JudgeBestEQ(ucEQPort);
 	}
@@ -5341,45 +5205,44 @@ void IT66021::JudgeBestEQ(struct it6602_eq_data *ucEQPort)
 	j = 0;
 	Result = ucEQPort->ErrorCount[0];
 
-	for (i = 1; i < MaxEQIndex; i++)
-	{
-		if (Result >= ucEQPort->ErrorCount[i])
-		{
+	for (i = 1; i < MaxEQIndex; i++) {
+		if (Result >= ucEQPort->ErrorCount[i]) {
 			Result = ucEQPort->ErrorCount[i];
 			j = i;
 		}
 	}
 
-	IT_INFO(" Best IT6602EQTable ErrorCount[%X]=%X !!! IT6602EQTable Value=%X !!!\n", (int)j, (int)Result, (int)IT6602EQTable[j]);
+	IT_INFO(" Best IT6602EQTable ErrorCount[%X]=%X !!! IT6602EQTable Value=%X !!!\n", (int)j, (int)Result,
+		(int)IT6602EQTable[j]);
 
-	if (ucEQPort->ucPortID == F_PORT_SEL_0)
-	{
+	if (ucEQPort->ucPortID == F_PORT_SEL_0) {
 #ifdef _SUPPORT_AUTO_EQ_
-		if ((hdmirxrd(REG_RX_027) & 0x80) == 0)
-		{
+
+		if ((hdmirxrd(REG_RX_027) & 0x80) == 0) {
 			OverWriteAmpValue2EQ(ucEQPort->ucPortID);
-		}
-		else
+
+		} else
 #endif
 		{
 			hdmirxset(REG_RX_026, 0x20, 0x20); //07-04 add for adjust EQ
 			hdmirxwr(REG_RX_027, IT6602EQTable[j]);
-			IT_INFO("Port=%X ,ucIndex = %X ,JudgeBestEQ Reg027 = %X \r\n", (int)ucEQPort->ucPortID, (int)j, (int)hdmirxrd(REG_RX_027));
+			IT_INFO("Port=%X ,ucIndex = %X ,JudgeBestEQ Reg027 = %X \r\n", (int)ucEQPort->ucPortID, (int)j,
+				(int)hdmirxrd(REG_RX_027));
 		}
-	}
-	else
-	{
+
+	} else {
 #ifdef _SUPPORT_AUTO_EQ_
-		if ((hdmirxrd(REG_RX_03F) & 0x80) == 0)
-		{
+
+		if ((hdmirxrd(REG_RX_03F) & 0x80) == 0) {
 			OverWriteAmpValue2EQ(ucEQPort->ucPortID);
-		}
-		else
+
+		} else
 #endif
 		{
 			hdmirxset(REG_RX_03E, 0x20, 0x20); //07-04 add for adjust EQ
 			hdmirxwr(REG_RX_03F, IT6602EQTable[j]);
-			IT_INFO("Port=%X ,ucIndex = %X ,JudgeBestEQ Reg03F = %X \r\n", (int)ucEQPort->ucPortID, (int)j, (int)hdmirxrd(REG_RX_03F));
+			IT_INFO("Port=%X ,ucIndex = %X ,JudgeBestEQ Reg03F = %X \r\n", (int)ucEQPort->ucPortID, (int)j,
+				(int)hdmirxrd(REG_RX_03F));
 		}
 	}
 }
@@ -5402,8 +5265,7 @@ void IT66021::DisableOverWriteRS(unsigned char ucPortSel)
 
 	struct it6602_dev_data *it6602data = get_it6602_dev_data();
 
-	if (ucPortSel == F_PORT_SEL_1)
-	{
+	if (ucPortSel == F_PORT_SEL_1) {
 
 #ifdef _SUPPORT_AUTO_EQ_
 		ucPortAMPOverWrite[F_PORT_SEL_1] = 0; //2013-0801
@@ -5425,9 +5287,8 @@ void IT66021::DisableOverWriteRS(unsigned char ucPortSel)
 		it6602data->HDMIIntEvent &= 0x0F;
 		;
 		it6602data->HDMIWaitNo[F_PORT_SEL_1] = 0;
-	}
-	else
-	{
+
+	} else {
 
 #ifdef _SUPPORT_AUTO_EQ_
 		ucPortAMPOverWrite[F_PORT_SEL_0] = 0; //2013-0801
@@ -5458,7 +5319,8 @@ void IT66021::DisableOverWriteRS(unsigned char ucPortSel)
 
 		chgbank(1);
 		hdmirxset(REG_RX_1B8, 0x80, 0x00); // [7] Reg_HWENHYS = 0
-		hdmirxset(REG_RX_1B6, 0x07, 0x03); // [2:0]Reg_P0_ENHYS = 03  [2:0]Reg_P0_ENHYS = 03 for default enable filter to gating output
+		hdmirxset(REG_RX_1B6, 0x07,
+			  0x03); // [2:0]Reg_P0_ENHYS = 03  [2:0]Reg_P0_ENHYS = 03 for default enable filter to gating output
 		chgbank(0);
 		uc = mhlrxrd(0x05);
 		mhlrxwr(0x05, uc);
@@ -5490,30 +5352,26 @@ void IT66021::AmpValidCheck(unsigned char ucPortSel)
 #ifdef _SUPPORT_AUTO_EQ_
 	unsigned char uc;
 
-	if (ucPortSel == F_PORT_SEL_1)
-	{
+	if (ucPortSel == F_PORT_SEL_1) {
 		chgbank(1);
 		uc = hdmirxrd(REG_RX_1D8);
 		IT_INFO(" ############# AmpValidCheck( ) port 1 ###############\n");
 		IT_INFO(" ############# Reg1D8 = %X ###############\n", (int)uc);
 		IT_INFO(" ############# Reg1DC = %X ###############\n", (int)hdmirxrd(REG_RX_1DC));
 
-		if ((uc & 0x03) == 0x03)
-		{
+		if ((uc & 0x03) == 0x03) {
 			ucChannelB[1] = hdmirxrd(REG_RX_1DD);
 			ucPortAMPValid[1] |= 0x03;
 			IT_INFO(" ############# B AMP VALID port 1 Reg1DD = 0x%X  ###############\n", (int)ucChannelB[1]);
 		}
 
-		if ((uc & 0x0C) == 0x0C)
-		{
+		if ((uc & 0x0C) == 0x0C) {
 			ucChannelG[1] = hdmirxrd(REG_RX_1DE);
 			ucPortAMPValid[1] |= 0x0C;
 			IT_INFO(" ############# G AMP VALID port 1 Reg1DD = 0x%X  ###############\n", (int)ucChannelG[1]);
 		}
 
-		if ((uc & 0x30) == 0x30)
-		{
+		if ((uc & 0x30) == 0x30) {
 			ucChannelR[1] = hdmirxrd(REG_RX_1DF);
 			ucPortAMPValid[1] |= 0x30;
 			IT_INFO(" ############# R AMP VALID port 1 Reg1DD = 0x%X  ###############\n", (int)ucChannelR[1]);
@@ -5521,60 +5379,52 @@ void IT66021::AmpValidCheck(unsigned char ucPortSel)
 
 		chgbank(0);
 
-		if ((ucPortAMPValid[1] & 0x3F) == 0x3F)
-		{
+		if ((ucPortAMPValid[1] & 0x3F) == 0x3F) {
 			OverWriteAmpValue2EQ(F_PORT_SEL_1);
 			//FIX_ID_001 xxxxx Add Auto EQ with Manual EQ
 #ifdef _SUPPORT_EQ_ADJUST_
 			HDMIStartEQDetect(&(it6602data->EQPort[F_PORT_SEL_1]));
 #endif
 		}
-	}
-	else
-	{
+
+	} else {
 		chgbank(1);
 		uc = hdmirxrd(REG_RX_1D0);
 		IT_INFO(" ############# AmpValidCheck( ) port 0 ###############\n");
 		IT_INFO(" ############# REG_RX_1D0 = %X ###############\n", (int)uc);
 		IT_INFO(" ############# Reg1D4 = %X ###############\n", (int)hdmirxrd(REG_RX_1D4));
 
-		if ((uc & 0x03) == 0x03)
-		{
+		if ((uc & 0x03) == 0x03) {
 			ucChannelB[0] = hdmirxrd(REG_RX_1D5);
 			ucPortAMPValid[0] |= 0x03;
 			IT_INFO(" ############# B AMP VALID port 0 Reg1D5 = 0x%X  ###############\n", (int)ucChannelB[0]);
 		}
 
-		if ((uc & 0x0C) == 0x0C)
-		{
+		if ((uc & 0x0C) == 0x0C) {
 			ucChannelG[0] = hdmirxrd(REG_RX_1D6);
 			ucPortAMPValid[0] |= 0x0C;
 			IT_INFO(" ############# G AMP VALID port 0 Reg1D6 = 0x%X  ###############\n", (int)ucChannelG[0]);
 		}
 
-		if ((uc & 0x30) == 0x30)
-		{
+		if ((uc & 0x30) == 0x30) {
 			ucChannelR[0] = hdmirxrd(REG_RX_1D7);
 			ucPortAMPValid[0] |= 0x30;
 			IT_INFO(" ############# R AMP VALID port 0 Reg1D7 = 0x%X  ###############\n", (int)ucChannelR[0]);
 		}
+
 		chgbank(0);
 
-		if (hdmirxrd(REG_RX_P0_SYS_STATUS) & (B_P0_MHL_MODE))
-		{
-			if ((ucPortAMPValid[0] & 0x03) == 0x03)
-			{
+		if (hdmirxrd(REG_RX_P0_SYS_STATUS) & (B_P0_MHL_MODE)) {
+			if ((ucPortAMPValid[0] & 0x03) == 0x03) {
 
 				OverWriteAmpValue2EQ(F_PORT_SEL_0);
 #ifdef _SUPPORT_EQ_ADJUST_
 				HDMIStartEQDetect(&(it6602data->EQPort[F_PORT_SEL_0]));
 #endif
 			}
-		}
-		else
-		{
-			if ((ucPortAMPValid[0] & 0x3F) == 0x3F)
-			{
+
+		} else {
+			if ((ucPortAMPValid[0] & 0x3F) == 0x3F) {
 				OverWriteAmpValue2EQ(F_PORT_SEL_0);
 
 #ifdef _SUPPORT_EQ_ADJUST_
@@ -5583,6 +5433,7 @@ void IT66021::AmpValidCheck(unsigned char ucPortSel)
 			}
 		}
 	}
+
 #endif
 }
 
@@ -5596,42 +5447,33 @@ void IT66021::TogglePolarity(unsigned char ucPortSel)
 	return;
 #endif
 
-	if (HdmiI2cAddr == IT6602A0_HDMI_ADDR)
-	{
-		if (ucPortSelCurrent != ucPortSel)
-		{
+	if (HdmiI2cAddr == IT6602A0_HDMI_ADDR) {
+		if (ucPortSelCurrent != ucPortSel) {
 			return;
 		}
 	}
 
-	if (ucPortSel == F_PORT_SEL_1)
-	{
+	if (ucPortSel == F_PORT_SEL_1) {
 		IT_INFO(" ############# TogglePolarity Port 1###############\n");
 		chgbank(1);
 
 		hdmirxset(REG_RX_1C5, 0x10, 0x00);
 
 		//FIX_ID_002 xxxxx 	Check IT6602 chip version Identify for TogglePolarity and Port 1 Deskew
-		if (HdmiI2cAddr == IT6602A0_HDMI_ADDR)
-		{
+		if (HdmiI2cAddr == IT6602A0_HDMI_ADDR) {
 			//xxxxx only for IT6602A0 Version
-			if ((hdmirxrd(REG_RX_1B9) & 0x80) >> 7)
-			{
+			if ((hdmirxrd(REG_RX_1B9) & 0x80) >> 7) {
 				hdmirxset(REG_RX_1B9, 0x80, 0x00); // Change Polarity
-			}
-			else
-			{
+
+			} else {
 				hdmirxset(REG_RX_1B9, 0x80, 0x80); // Change Polarity
 			}
-		}
-		else
-		{
-			if ((hdmirxrd(REG_RX_1C9) & 0x80) >> 7)
-			{
+
+		} else {
+			if ((hdmirxrd(REG_RX_1C9) & 0x80) >> 7) {
 				hdmirxset(REG_RX_1C9, 0x80, 0x00); // Change Polarity
-			}
-			else
-			{
+
+			} else {
 				hdmirxset(REG_RX_1C9, 0x80, 0x80); // Change Polarity
 			}
 		}
@@ -5643,19 +5485,16 @@ void IT66021::TogglePolarity(unsigned char ucPortSel)
 		hdmirxset(REG_RX_03A, 0xFF, 0x38);
 		hdmirxset(REG_RX_03A, 0x04, 0x04);
 		hdmirxset(REG_RX_03A, 0x04, 0x00);
-	}
-	else
-	{
+
+	} else {
 		IT_INFO(" ############# TogglePolarity Port 0###############\n");
 		chgbank(1);
 		hdmirxset(REG_RX_1B5, 0x10, 0x00);
 
-		if ((hdmirxrd(REG_RX_1B9) & 0x80) >> 7)
-		{
+		if ((hdmirxrd(REG_RX_1B9) & 0x80) >> 7) {
 			hdmirxset(REG_RX_1B9, 0x80, 0x00); // Change Polarity
-		}
-		else
-		{
+
+		} else {
 			hdmirxset(REG_RX_1B9, 0x80, 0x80); // Change Polarity
 		}
 
@@ -5668,6 +5507,7 @@ void IT66021::TogglePolarity(unsigned char ucPortSel)
 		hdmirxset(REG_RX_022, 0x04, 0x04);
 		hdmirxset(REG_RX_022, 0x04, 0x00);
 	}
+
 #endif
 }
 
@@ -5682,29 +5522,31 @@ void IT66021::TMDSCheck(unsigned char ucPortSel)
 
 	IT_INFO("TMDSCheck() !!!\n");
 
-	if (ucPortSel == F_PORT_SEL_1)
-	{
+	if (ucPortSel == F_PORT_SEL_1) {
 		ucClk = hdmirxrd(REG_RX_092);
 		rddata = hdmirxrd(0x90);
 
-		if (ucClk != 0)
-		{
-			if (rddata & 0x04)
+		if (ucClk != 0) {
+			if (rddata & 0x04) {
 				ucTMDSClk = 2 * RCLKVALUE * 256 / ucClk;
-			else if (rddata & 0x08)
+
+			} else if (rddata & 0x08) {
 				ucTMDSClk = 4 * RCLKVALUE * 256 / ucClk;
-			else
+
+			} else {
 				ucTMDSClk = RCLKVALUE * 256 / ucClk;
+			}
 
 			IT_INFO(" Port 1 TMDS CLK  = %d \r\n", (int)ucTMDSClk);
 		}
 
-		if (HdmiI2cAddr == IT6602A0_HDMI_ADDR)
-		{
-			if (ucTMDSClk < TMDSCLKVALUE_480P || ucTMDSClk > TMDSCLKVALUE_1080P)
-				hdmirxwr(REG_RX_038, 0x00); // Dr. Liu suggestion to 0x00
-			else
-				hdmirxwr(REG_RX_038, 0x3F); // Dr. Liu suggestion to 0x3F
+		if (HdmiI2cAddr == IT6602A0_HDMI_ADDR) {
+			if (ucTMDSClk < TMDSCLKVALUE_480P || ucTMDSClk > TMDSCLKVALUE_1080P) {
+				hdmirxwr(REG_RX_038, 0x00);        // Dr. Liu suggestion to 0x00
+
+			} else {
+				hdmirxwr(REG_RX_038, 0x3F);        // Dr. Liu suggestion to 0x3F
+			}
 		}
 
 		IT_INFO(" HDMI Reg038  = %X \r\n", (int)hdmirxrd(REG_RX_038));
@@ -5713,41 +5555,40 @@ void IT66021::TMDSCheck(unsigned char ucPortSel)
 		IT_INFO(" HDMI Reg1C1  = %X ,Reg1C2  = %X\r\n", hdmirxrd(REG_RX_1C1), hdmirxrd(REG_RX_1C2));
 		chgbank(0);
 
-		if (ucPortAMPOverWrite[1] == 0) // 2013-0801
-		{
+		if (ucPortAMPOverWrite[1] == 0) { // 2013-0801
 			chgbank(1);
 			rddata = hdmirxrd(REG_RX_1DC);
 			chgbank(0);
-			if (rddata == 0)
-			{
+
+			if (rddata == 0) {
 				IT_INFO(" ############# Trigger Port 1 EQ ###############\n");
 				hdmirxset(REG_RX_03A, 0xFF, 0x38); //07-04
 				hdmirxset(REG_RX_03A, 0x04, 0x04);
 				hdmirxset(REG_RX_03A, 0x04, 0x00);
 			}
-		}
-		else
-		{
+
+		} else {
 			IT_INFO(" ############# B_PORT1_TimingChgEvent###############\n");
 			it6602data->HDMIIntEvent |= (B_PORT1_Waiting);
 			it6602data->HDMIIntEvent |= (B_PORT1_TimingChgEvent);
 			it6602data->HDMIWaitNo[1] = MAX_TMDS_WAITNO;
 		}
-	}
-	else
-	{
+
+	} else {
 		IT_INFO(" HDMI Reg90  = %X ,Reg91  = %X\r\n", (int)hdmirxrd(0x90), (int)hdmirxrd(0x91));
 		ucClk = hdmirxrd(REG_RX_091);
 		rddata = hdmirxrd(0x90);
 
-		if (ucClk != 0)
-		{
-			if (rddata & 0x01)
+		if (ucClk != 0) {
+			if (rddata & 0x01) {
 				ucTMDSClk = 2 * RCLKVALUE * 256 / ucClk;
-			else if (rddata & 0x02)
+
+			} else if (rddata & 0x02) {
 				ucTMDSClk = 4 * RCLKVALUE * 256 / ucClk;
-			else
+
+			} else {
 				ucTMDSClk = RCLKVALUE * 256 / ucClk;
+			}
 
 			IT_INFO(" Port 0 TMDS CLK  = %X \r\n", (int)ucTMDSClk);
 		}
@@ -5785,8 +5626,7 @@ void IT66021::TMDSCheck(unsigned char ucPortSel)
 		IT_INFO(" HDMI Reg020  = %X \r\n", (int)hdmirxrd(REG_RX_020));
 
 		//FIX_ID_019	xxxxx modify ENHYS control for MHL mode
-		if (hdmirxrd(REG_RX_P0_SYS_STATUS) & (B_P0_MHL_MODE))
-		{
+		if (hdmirxrd(REG_RX_P0_SYS_STATUS) & (B_P0_MHL_MODE)) {
 			IT_INFO("hdmirxrd(REG_RX_P0_SYS_STATUS) = %d", hdmirxrd(REG_RX_P0_SYS_STATUS));
 
 			chgbank(1);
@@ -5795,8 +5635,7 @@ void IT66021::TMDSCheck(unsigned char ucPortSel)
 			chgbank(0);
 		}
 
-		if (ucPortAMPOverWrite[0] == 0) // 2013-0801
-		{
+		if (ucPortAMPOverWrite[0] == 0) { // 2013-0801
 			//FIX_ID_001 xxxxx check State of AutoEQ
 			chgbank(1);
 			rddata = hdmirxrd(REG_RX_1D4);
@@ -5810,24 +5649,25 @@ void IT66021::TMDSCheck(unsigned char ucPortSel)
 #endif
 #endif
 #else
-			if (rddata == 0)
-			{
+
+			if (rddata == 0) {
 				IT_INFO(" ############# Trigger Port 0 EQ ###############\n");
 				hdmirxset(REG_RX_022, 0xFF, 0x38); //07-04
 				hdmirxset(REG_RX_022, 0x04, 0x04);
 				hdmirxset(REG_RX_022, 0x04, 0x00);
 			}
+
 #endif
 			it6602data->HDMIIntEvent &= ~(B_PORT0_TMDSEvent | B_PORT0_Waiting | B_PORT0_TimingChgEvent);
-		}
-		else
-		{
+
+		} else {
 			IT_INFO(" ############# B_PORT0_TimingChgEvent###############\n");
 			it6602data->HDMIIntEvent |= (B_PORT0_Waiting);
 			it6602data->HDMIIntEvent |= (B_PORT0_TimingChgEvent);
 			it6602data->HDMIWaitNo[0] = MAX_TMDS_WAITNO;
 		}
 	}
+
 #endif
 }
 
@@ -5842,40 +5682,32 @@ void IT66021::OverWriteAmpValue2EQ(unsigned char ucPortSel)
 	IT_INFO(" 111111111111111111 OverWriteAmpValue2EQ 111111111111111111111111111111\r\n");
 	IT_INFO(" 111111111111111111 OverWriteAmpValue2EQ 111111111111111111111111111111\r\n");
 
-	if (ucPortSel == F_PORT_SEL_1)
-	{
-		if ((ucPortAMPValid[1] & 0x3F) == 0x3F)
-		{
+	if (ucPortSel == F_PORT_SEL_1) {
+		if ((ucPortAMPValid[1] & 0x3F) == 0x3F) {
 			ucPortAMPOverWrite[F_PORT_SEL_1] = 1; //2013-0801
 			ucEQMode[F_PORT_SEL_1] = 0;			  // 0 for Auto Mode
 			IT_INFO("#### REG_RX_03E = 0x%X ####\r\n", (int)hdmirxrd(REG_RX_03E));
 			hdmirxset(REG_RX_03E, 0x20, 0x20); //Manually set RS Value
 			IT_INFO("#### REG_RX_03E = 0x%X ####\r\n", (int)hdmirxrd(REG_RX_03E));
 
-			if (ucChannelB[F_PORT_SEL_1] < MinEQValue)
-			{
+			if (ucChannelB[F_PORT_SEL_1] < MinEQValue) {
 				hdmirxwr(REG_RX_03F, MinEQValue);
-			}
-			else
-			{
+
+			} else {
 				hdmirxwr(REG_RX_03F, (ucChannelB[F_PORT_SEL_1] & 0x7F));
 			}
 
-			if (ucChannelG[F_PORT_SEL_1] < MinEQValue)
-			{
+			if (ucChannelG[F_PORT_SEL_1] < MinEQValue) {
 				hdmirxwr(REG_RX_040, MinEQValue);
-			}
-			else
-			{
+
+			} else {
 				hdmirxwr(REG_RX_040, (ucChannelG[F_PORT_SEL_1] & 0x7F));
 			}
 
-			if (ucChannelR[F_PORT_SEL_1] < MinEQValue)
-			{
+			if (ucChannelR[F_PORT_SEL_1] < MinEQValue) {
 				hdmirxwr(REG_RX_041, MinEQValue);
-			}
-			else
-			{
+
+			} else {
 				hdmirxwr(REG_RX_041, (ucChannelR[F_PORT_SEL_1] & 0x7F));
 			}
 
@@ -5889,13 +5721,10 @@ void IT66021::OverWriteAmpValue2EQ(unsigned char ucPortSel)
 			hdmirxwr(REG_RX_03A, 0x00); // power down auto EQ
 			hdmirxwr(0xD0, 0xC0);
 		}
-	}
-	else
-	{
-		if (hdmirxrd(REG_RX_P0_SYS_STATUS) & (B_P0_MHL_MODE))
-		{
-			if ((ucPortAMPValid[F_PORT_SEL_0] & 0x03) == 0x03)
-			{
+
+	} else {
+		if (hdmirxrd(REG_RX_P0_SYS_STATUS) & (B_P0_MHL_MODE)) {
+			if ((ucPortAMPValid[F_PORT_SEL_0] & 0x03) == 0x03) {
 				ucPortAMPOverWrite[F_PORT_SEL_0] = 1; //2013-0801
 				ucEQMode[F_PORT_SEL_0] = 0;			  // 0 for Auto Mode
 				IT_INFO("#### REG_RX_026 = 0x%X ####\r\n", (int)hdmirxrd(REG_RX_026));
@@ -5903,14 +5732,12 @@ void IT66021::OverWriteAmpValue2EQ(unsigned char ucPortSel)
 				hdmirxset(REG_RX_026, 0x20, 0x20); //Manually set RS Value
 				IT_INFO("#### REG_RX_026 = 0x%X ####\r\n", (int)hdmirxrd(REG_RX_026));
 
-				if ((ucChannelB[F_PORT_SEL_0]) < MinEQValue)
-				{
+				if ((ucChannelB[F_PORT_SEL_0]) < MinEQValue) {
 					hdmirxwr(REG_RX_027, (MinEQValue));
 					hdmirxwr(REG_RX_028, (MinEQValue)); //07-08 using B channal to over-write G and R channel
 					hdmirxwr(REG_RX_029, (MinEQValue));
-				}
-				else
-				{
+
+				} else {
 					hdmirxwr(REG_RX_027, (ucChannelB[F_PORT_SEL_0] & 0x7F));
 					hdmirxwr(REG_RX_028, (ucChannelB[F_PORT_SEL_0] & 0x7F)); //07-08 using B channal to over-write G and R channel
 					hdmirxwr(REG_RX_029, (ucChannelB[F_PORT_SEL_0] & 0x7F));
@@ -5925,41 +5752,33 @@ void IT66021::OverWriteAmpValue2EQ(unsigned char ucPortSel)
 				hdmirxwr(0xD0, 0x30);
 				//FIX_ID_033 xxxxx
 			}
-		}
-		else
-		{
-			if ((ucPortAMPValid[F_PORT_SEL_0] & 0x3F) == 0x3F)
-			{
+
+		} else {
+			if ((ucPortAMPValid[F_PORT_SEL_0] & 0x3F) == 0x3F) {
 				ucPortAMPOverWrite[F_PORT_SEL_0] = 1; //2013-0801
 				ucEQMode[F_PORT_SEL_0] = 0;			  // 0 for Auto Mode
 				IT_INFO("#### REG_RX_026 = 0x%X ####\r\n", (int)hdmirxrd(REG_RX_026));
 				hdmirxset(REG_RX_026, 0x20, 0x20); //Manually set RS Value
 				IT_INFO("#### REG_RX_026 = 0x%X ####\r\n", (int)hdmirxrd(REG_RX_026));
 
-				if (ucChannelB[F_PORT_SEL_0] < MinEQValue)
-				{
+				if (ucChannelB[F_PORT_SEL_0] < MinEQValue) {
 					hdmirxwr(REG_RX_027, MinEQValue);
-				}
-				else
-				{
+
+				} else {
 					hdmirxwr(REG_RX_027, (ucChannelB[F_PORT_SEL_0] & 0x7F));
 				}
 
-				if (ucChannelG[F_PORT_SEL_0] < MinEQValue)
-				{
+				if (ucChannelG[F_PORT_SEL_0] < MinEQValue) {
 					hdmirxwr(REG_RX_028, MinEQValue);
-				}
-				else
-				{
+
+				} else {
 					hdmirxwr(REG_RX_028, (ucChannelG[F_PORT_SEL_0] & 0x7F));
 				}
 
-				if (ucChannelR[F_PORT_SEL_0] < MinEQValue)
-				{
+				if (ucChannelR[F_PORT_SEL_0] < MinEQValue) {
 					hdmirxwr(REG_RX_029, MinEQValue);
-				}
-				else
-				{
+
+				} else {
 					hdmirxwr(REG_RX_029, (ucChannelR[F_PORT_SEL_0] & 0x7F));
 				}
 
@@ -5983,28 +5802,21 @@ void IT66021::OverWriteAmpValue2EQ(unsigned char ucPortSel)
 //FIX_ID_014 xxxxx
 void IT66021::IT6602HDMIEventManager(struct it6602_dev_data *it6602)
 {
-	if (it6602->HDMIIntEvent != 0)
-	{
-		if ((it6602->HDMIIntEvent & B_PORT0_Waiting) == B_PORT0_Waiting)
-		{
-			if (it6602->HDMIWaitNo[0] == 0)
-			{
+	if (it6602->HDMIIntEvent != 0) {
+		if ((it6602->HDMIIntEvent & B_PORT0_Waiting) == B_PORT0_Waiting) {
+			if (it6602->HDMIWaitNo[0] == 0) {
 				it6602->HDMIIntEvent &= ~(B_PORT0_Waiting);
 				IT_INFO("B_PORT0_Waiting  OK ...\n");
-			}
-			else
-			{
+
+			} else {
 				it6602->HDMIWaitNo[0]--;
 				IT_INFO("B_PORT0_Waiting  %X ...Event=%X ...Reg93=%X \n",
-						 (int)it6602->HDMIWaitNo[0], (int)it6602->HDMIIntEvent, (int)hdmirxrd(0x93));
+					(int)it6602->HDMIWaitNo[0], (int)it6602->HDMIIntEvent, (int)hdmirxrd(0x93));
 			}
-		}
-		else
-		{
-			if ((it6602->HDMIIntEvent & B_PORT0_TMDSEvent) == B_PORT0_TMDSEvent)
-			{
-				if (CLKCheck(F_PORT_SEL_0))
-				{
+
+		} else {
+			if ((it6602->HDMIIntEvent & B_PORT0_TMDSEvent) == B_PORT0_TMDSEvent) {
+				if (CLKCheck(F_PORT_SEL_0)) {
 					IT_INFO("TMDSEvent &&&&& Port 0 Rx CKOn Detect &&&&&\r\n");
 #ifdef _SUPPORT_AUTO_EQ_
 					TMDSCheck(F_PORT_SEL_0);
@@ -6017,11 +5829,9 @@ void IT66021::IT6602HDMIEventManager(struct it6602_dev_data *it6602)
 #endif
 					it6602->HDMIIntEvent &= ~(B_PORT0_TMDSEvent); // finish MSC
 				}
-			}
-			else if ((it6602->HDMIIntEvent & B_PORT0_TimingChgEvent) == B_PORT0_TimingChgEvent)
-			{
-				if (CLKCheck(F_PORT_SEL_0))
-				{
+
+			} else if ((it6602->HDMIIntEvent & B_PORT0_TimingChgEvent) == B_PORT0_TimingChgEvent) {
+				if (CLKCheck(F_PORT_SEL_0)) {
 					IT_INFO("TimingChgEvent &&&&& Port 0 Rx CKOn Detect &&&&&\r\n");
 //FIX_ID_001 xxxxx Add Auto EQ with Manual EQ
 #ifdef _SUPPORT_EQ_ADJUST_
@@ -6034,25 +5844,19 @@ void IT66021::IT6602HDMIEventManager(struct it6602_dev_data *it6602)
 			}
 		}
 
-		if ((it6602->HDMIIntEvent & B_PORT1_Waiting) == B_PORT1_Waiting)
-		{
-			if (it6602->HDMIWaitNo[1] == 0)
-			{
+		if ((it6602->HDMIIntEvent & B_PORT1_Waiting) == B_PORT1_Waiting) {
+			if (it6602->HDMIWaitNo[1] == 0) {
 				it6602->HDMIIntEvent &= ~(B_PORT1_Waiting);
 				IT_INFO("B_PORT1_Waiting  OK ...\n");
-			}
-			else
-			{
+
+			} else {
 				it6602->HDMIWaitNo[1]--;
 				IT_INFO("B_PORT1_Waiting  %X ...\n", (int)it6602->HDMIWaitNo[1]);
 			}
-		}
-		else
-		{
-			if ((it6602->HDMIIntEvent & B_PORT1_TMDSEvent) == B_PORT1_TMDSEvent)
-			{
-				if (CLKCheck(F_PORT_SEL_1))
-				{
+
+		} else {
+			if ((it6602->HDMIIntEvent & B_PORT1_TMDSEvent) == B_PORT1_TMDSEvent) {
+				if (CLKCheck(F_PORT_SEL_1)) {
 					IT_INFO("TMDSEvent &&&&& Port 1 Rx CKOn Detect &&&&&\r\n");
 #ifdef _SUPPORT_AUTO_EQ_
 					TMDSCheck(F_PORT_SEL_1);
@@ -6065,11 +5869,9 @@ void IT66021::IT6602HDMIEventManager(struct it6602_dev_data *it6602)
 #endif
 					it6602->HDMIIntEvent &= ~(B_PORT1_TMDSEvent); // finish MSC
 				}
-			}
-			else if ((it6602->HDMIIntEvent & B_PORT1_TimingChgEvent) == B_PORT1_TimingChgEvent)
-			{
-				if (CLKCheck(F_PORT_SEL_1))
-				{
+
+			} else if ((it6602->HDMIIntEvent & B_PORT1_TimingChgEvent) == B_PORT1_TimingChgEvent) {
+				if (CLKCheck(F_PORT_SEL_1)) {
 					IT_INFO("TimingChgEvent &&&&& Port 1 Rx CKOn Detect &&&&&\r\n");
 #ifdef _SUPPORT_EQ_ADJUST_
 					HDMIStartEQDetect(&(it6602->EQPort[F_PORT_SEL_1]));
@@ -6080,7 +5882,7 @@ void IT66021::IT6602HDMIEventManager(struct it6602_dev_data *it6602)
 		}
 	}
 }
- 
+
 
 #endif
 
@@ -6118,30 +5920,33 @@ void IT66021::IT6602_fsm(void)
 	// 	IT6602MHLInterruptHandler(it6602data);
 	// #endif
 
-		IT6602VideoHandler(it6602data);
-	#ifndef _FIX_ID_028_
-		IT6602AudioHandler(it6602data);
-	#endif
+	IT6602VideoHandler(it6602data);
+#ifndef _FIX_ID_028_
+	IT6602AudioHandler(it6602data);
+#endif
 
 	// #ifdef _ENABLE_IT68XX_MHL_FUNCTION_
 	// 	RCPManager(it6602data);
 	// #endif
 
-	#ifdef _SUPPORT_EQ_ADJUST_
-		IT_INFO("IT6602_fsm _SUPPORT_EQ_ADJUST_");
+#ifdef _SUPPORT_EQ_ADJUST_
+	IT_INFO("IT6602_fsm _SUPPORT_EQ_ADJUST_");
+
+	if (it6602data->EQPort[F_PORT_SEL_0].f_manualEQadjust == TRUE) {
+		HDMIAdjustEQ(&(it6602data->EQPort[F_PORT_SEL_0]));        // for port 0
+	}
 
-		if (it6602data->EQPort[F_PORT_SEL_0].f_manualEQadjust == TRUE)
-			HDMIAdjustEQ(&(it6602data->EQPort[F_PORT_SEL_0])); // for port 0
+	if (it6602data->EQPort[F_PORT_SEL_1].f_manualEQadjust == TRUE) {
+		HDMIAdjustEQ(&(it6602data->EQPort[F_PORT_SEL_1]));        // for port 1
+	}
 
-		if (it6602data->EQPort[F_PORT_SEL_1].f_manualEQadjust == TRUE)
-			HDMIAdjustEQ(&(it6602data->EQPort[F_PORT_SEL_1])); // for port 1
-	#endif
+#endif
 
 	// #ifdef _ENABLE_IT68XX_MHL_FUNCTION_
 	// 	IT6602CbusEventManager(it6602data);
 	// #endif
 
-		IT6602HDMIEventManager(it6602data);
+	IT6602HDMIEventManager(it6602data);
 
 	// #ifdef Enable_IT6602_CEC
 	// 	CECManager(); // detect CEC for IT6602_CEC
@@ -6154,8 +5959,8 @@ void IT66021::IT6602_fsm(void)
 void IT66021::cycletest()
 {
 	static uint8_t base = 0;
-	if (h264_input_format_topic == NULL)
-	{
+
+	if (h264_input_format_topic == NULL) {
 		h264_input_format_topic = orb_advertise(ORB_ID(h264_input_format), &att);
 	}
 
@@ -6166,10 +5971,10 @@ void IT66021::cycletest()
 	att.vic = 44 + base;
 	att.e_h264InputSrc = 99 + base;
 
-	if (++base >= 5)
-	{	
+	if (++base >= 5) {
 		return;
 	}
+
 	orb_publish(ORB_ID(h264_input_format), h264_input_format_topic, &att);
 }
 
@@ -6179,65 +5984,68 @@ void  IT66021::Dump_ITEHDMIReg(void)//max7088
 {
 
 #if 1
-    ushort	i,j ;
-    //BYTE reg ;
-    //BYTE bank ;
-    BYTE ucData ;
+	ushort	i, j ;
+	//BYTE reg ;
+	//BYTE bank ;
+	BYTE ucData ;
 
 //    printf(" ITEHDMI \r\n");
 //    printf("\n 11111:") ;
 //    printf("\n        ===================================================\r") ;
-    IT_INFO("\r\n       ") ;
-    for(j = 0 ; j < 16 ; j++)
-    {
-        IT_INFO(" %02X",(int) j) ;
-        if((j == 3)||(j==7)||(j==11))
-        {
-                IT_INFO(" :") ;
-        }
-    }
-    IT_INFO("\n        =====================================================\r\n") ;
-
-chgbank(0);
-
-    for(i = 0 ; i < 0x100 ; i+=16)
-    {
-        IT_INFO("[%03X]  ",i) ;
-        for(j = 0 ; j < 16 ; j++)
-        {
-            ucData = hdmirxrd((BYTE)((i+j)&0xFF)) ;
-            IT_INFO(" %02X",(int) ucData) ;
-            if((j == 3)||(j==7)||(j==11))
-            {
-                IT_INFO(" :") ;
-            }
-        }
-        IT_INFO("\r\n") ;
-        if((i % 0x40) == 0x30)
-        {
-    IT_INFO("\n        =====================================================\r\n") ;
-        }
-    }
-
-chgbank(1);
-    for(i = 0xb0 ; i < 0xd0 ; i+=16)
-    {
-        IT_INFO("[%03X]  ",i+0x100) ;
-        for(j = 0 ; j < 16 ; j++)
-        {
-            ucData = hdmirxrd((BYTE)((i+j)&0xFF)) ;
-            IT_INFO(" %02X",(int) ucData) ;
-            if((j == 3)||(j==7)||(j==11))
-            {
-                IT_INFO(" :") ;
-            }
-        }
-        IT_INFO("\r\n") ;
+	IT_INFO("\r\n       ") ;
+
+	for (j = 0 ; j < 16 ; j++) {
+		IT_INFO(" %02X", (int) j) ;
+
+		if ((j == 3) || (j == 7) || (j == 11)) {
+			IT_INFO(" :") ;
+		}
+	}
+
+	IT_INFO("\n        =====================================================\r\n") ;
+
+	chgbank(0);
+
+	for (i = 0 ; i < 0x100 ; i += 16) {
+		IT_INFO("[%03X]  ", i) ;
+
+		for (j = 0 ; j < 16 ; j++) {
+			ucData = hdmirxrd((BYTE)((i + j) & 0xFF)) ;
+			IT_INFO(" %02X", (int) ucData) ;
+
+			if ((j == 3) || (j == 7) || (j == 11)) {
+				IT_INFO(" :") ;
+			}
+		}
+
+		IT_INFO("\r\n") ;
+
+		if ((i % 0x40) == 0x30) {
+			IT_INFO("\n        =====================================================\r\n") ;
+		}
+	}
+
+	chgbank(1);
+
+	for (i = 0xb0 ; i < 0xd0 ; i += 16) {
+		IT_INFO("[%03X]  ", i + 0x100) ;
+
+		for (j = 0 ; j < 16 ; j++) {
+			ucData = hdmirxrd((BYTE)((i + j) & 0xFF)) ;
+			IT_INFO(" %02X", (int) ucData) ;
+
+			if ((j == 3) || (j == 7) || (j == 11)) {
+				IT_INFO(" :") ;
+			}
+		}
+
+		IT_INFO("\r\n") ;
 //        if((i % 0x40) == 0x30)
 //        {
 //    printf("\n        =====================================================\r\n") ;
 //        }
-    }
-chgbank(0);
+	}
+
+	chgbank(0);
 #endif
 }
\ No newline at end of file
diff --git a/src/drivers/it66021/it66021.h b/src/drivers/it66021/it66021.h
index 3dea5760b2f121c8294734476f59521d0a007450..db1e12e53550706572f2a50288a8821ff66563d3 100644
--- a/src/drivers/it66021/it66021.h
+++ b/src/drivers/it66021/it66021.h
@@ -37,25 +37,22 @@
 //xxxxx 2014-0421
 //FIX_ID_033 xxxxx
 
-enum
-{
-  MHD_RAP_CMD_POLL         	= 0x00,
-  MHD_RAP_CMD_CHG_ACTIVE_PWR  = 0x10,
-  MHD_RAP_CMD_CHG_QUIET       = 0x11,
-  MHD_RAP_CMD_END             = 0x12
+enum {
+	MHD_RAP_CMD_POLL         	= 0x00,
+	MHD_RAP_CMD_CHG_ACTIVE_PWR  = 0x10,
+	MHD_RAP_CMD_CHG_QUIET       = 0x11,
+	MHD_RAP_CMD_END             = 0x12
 };
 
 //RAPK sub commands
-enum
-{
-    MHD_MSC_MSG_RAP_NO_ERROR        		= 0x00,     // RAP No Error
-    MHD_MSC_MSG_RAP_UNRECOGNIZED_ACT_CODE  	= 0x01,
-    MHD_MSC_MSG_RAP_UNSUPPORTED_ACT_CODE  	= 0x02,
-    MHD_MSC_MSG_RAP_RESPONDER_BUSY   		= 0x03
+enum {
+	MHD_MSC_MSG_RAP_NO_ERROR        		= 0x00,     // RAP No Error
+	MHD_MSC_MSG_RAP_UNRECOGNIZED_ACT_CODE  	= 0x01,
+	MHD_MSC_MSG_RAP_UNSUPPORTED_ACT_CODE  	= 0x02,
+	MHD_MSC_MSG_RAP_RESPONDER_BUSY   		= 0x03
 };
 
-enum
-{
+enum {
 	RCP_SELECT          = 0x00,
 	RCP_UP              = 0x01,
 	RCP_DOWN            = 0x02,
@@ -148,9 +145,8 @@ enum
 };
 
 //FIX_ID_003 xxxxx	//Add IT6602 Video Output Configure setting
-typedef enum _Video_Output_Configure
-{
-	eRGB444_SDR=0,
+typedef enum _Video_Output_Configure {
+	eRGB444_SDR = 0,
 	eYUV444_SDR,
 	eRGB444_DDR,
 	eYUV444_DDR,
@@ -167,55 +163,53 @@ typedef enum _Video_Output_Configure
 	eBTA1004_SDR,
 	eBTA1004_DDR,
 	eVOMreserve
-}Video_Output_Configure;
+} Video_Output_Configure;
 
-typedef enum _Video_OutputDataTrigger_Mode
-{
-	eSDR=0,
+typedef enum _Video_OutputDataTrigger_Mode {
+	eSDR = 0,
 	eHalfPCLKDDR,
 	eHalfBusDDR,
 	eSDR_BTA1004,
 	eDDR_BTA1004
-}Video_DataTrigger_Mode;
+} Video_DataTrigger_Mode;
 
-typedef enum _Video_OutputSync_Mode
-{
-	eSepSync=0,
+typedef enum _Video_OutputSync_Mode {
+	eSepSync = 0,
 	eEmbSync,
 	eCCIR656SepSync,
 	eCCIR656EmbSync
-}Video_OutputSync_Mode;
+} Video_OutputSync_Mode;
 
 //FIX_ID_003 xxxxx
 
 typedef enum _Video_State_Type {
-    VSTATE_Off=0,
-    VSTATE_TerminationOff,
-    VSTATE_TerminationOn,
-    VSTATE_5VOff,
-    VSTATE_SyncWait,
-    VSTATE_SWReset,
-    VSTATE_SyncChecking,
-    VSTATE_HDCPSet,
-    VSTATE_HDCP_Reset,
-    VSTATE_ModeDetecting,
-    VSTATE_VideoOn,
-    VSTATE_ColorDetectReset,
-    VSTATE_HDMI_OFF,
-    VSTATE_Reserved
+	VSTATE_Off = 0,
+	VSTATE_TerminationOff,
+	VSTATE_TerminationOn,
+	VSTATE_5VOff,
+	VSTATE_SyncWait,
+	VSTATE_SWReset,
+	VSTATE_SyncChecking,
+	VSTATE_HDCPSet,
+	VSTATE_HDCP_Reset,
+	VSTATE_ModeDetecting,
+	VSTATE_VideoOn,
+	VSTATE_ColorDetectReset,
+	VSTATE_HDMI_OFF,
+	VSTATE_Reserved
 } Video_State_Type;
 
 typedef enum _RxHDCP_State_Type {
-    RxHDCP_PwrOff=0,
-    RxHDCP_ModeCheck,
-    RxHDCP_Receiver,
-    RxHDCP_Repeater,
-    RxHDCP_SetKSVFifoList,
-    RxHDCP_GenVR,
-    RxHDCP_WriteVR,
-    RxHDCP_Auth_WaitRi,
-    RxHDCP_Authenticated,
-    RxHDCP_Reserved
+	RxHDCP_PwrOff = 0,
+	RxHDCP_ModeCheck,
+	RxHDCP_Receiver,
+	RxHDCP_Repeater,
+	RxHDCP_SetKSVFifoList,
+	RxHDCP_GenVR,
+	RxHDCP_WriteVR,
+	RxHDCP_Auth_WaitRi,
+	RxHDCP_Authenticated,
+	RxHDCP_Reserved
 } RxHDCP_State_Type;
 
 typedef enum  {
@@ -225,7 +219,7 @@ typedef enum  {
 	RCP_Transfer,
 	RCP_Empty,
 	RCP_Unknown
-}RCPState_Type;
+} RCPState_Type;
 
 typedef enum  {
 	RCP_Result_OK = 0,
@@ -234,7 +228,7 @@ typedef enum  {
 	RCP_Result_Transfer,
 	RCP_Result_Finish,
 	RCP_Result_Unknown
-}RCPResult_Type;
+} RCPResult_Type;
 
 
 
@@ -355,82 +349,85 @@ typedef enum  {
 /*****************************************************************************/
 /* Type defs struct **********************************************************/
 /*****************************************************************************/
-struct IT6602_REG_INI
-{
-    unsigned char ucAddr;
-    unsigned char andmask;
-    unsigned char ucValue;
+struct IT6602_REG_INI {
+	unsigned char ucAddr;
+	unsigned char andmask;
+	unsigned char ucValue;
 };
 
 
-struct IT6602_VIDEO_CONFIGURE_REG
-{
-    unsigned char ucReg51;
-    unsigned char ucReg65;
+struct IT6602_VIDEO_CONFIGURE_REG {
+	unsigned char ucReg51;
+	unsigned char ucReg65;
 };
 
-typedef struct _3D_SourceConfiguration
-{
-    unsigned char          Format;              /**< Type of 3D source format expected or found.                                                        */
-    unsigned char    LR_Reference;        /**< Source of the 3D L/R reference.                                                                    */
-    unsigned char FrameDominance;      /**< Left or Right Eye is first in L/R image pair.                                                      */
-    unsigned char     LR_Encoding;         /**< Type of 3D L/R encoding expected or detected.                                                      */
-    unsigned char    TB_Reference;        /**< Top/Bottom reference for vertically sub-sampled sources.                                           */
-    unsigned char    OE_Reference;        /**< Odd/Even reference for horizontally sub-sampled sources.                                           */
-    unsigned char NumActiveBlankLines;                 /**< Number of lines separating vertically packed L/R data to be removed (cropped)
+typedef struct _3D_SourceConfiguration {
+	unsigned char
+	Format;              /**< Type of 3D source format expected or found.                                                        */
+	unsigned char
+	LR_Reference;        /**< Source of the 3D L/R reference.                                                                    */
+	unsigned char
+	FrameDominance;      /**< Left or Right Eye is first in L/R image pair.                                                      */
+	unsigned char
+	LR_Encoding;         /**< Type of 3D L/R encoding expected or detected.                                                      */
+	unsigned char
+	TB_Reference;        /**< Top/Bottom reference for vertically sub-sampled sources.                                           */
+	unsigned char
+	OE_Reference;        /**< Odd/Even reference for horizontally sub-sampled sources.                                           */
+	unsigned char
+	NumActiveBlankLines;                 /**< Number of lines separating vertically packed L/R data to be removed (cropped)
                                                   *  before being displayed. Does not include any embedded encoding.                                    */
-    unsigned char NumberOfEncodedLines;                /**< Number of encoded lines in one L/R eye frame of the display data
+	unsigned char NumberOfEncodedLines;                /**< Number of encoded lines in one L/R eye frame of the display data
                                                   *  to be blanked out with "Blanking Color". (assumed same number in second eye frame)                 */
-    unsigned int  LeftEncodedLineLocation;             /**< Active line number of 1st encoded line in one Left eye frame of the display data (-1=unknown).     */
-    unsigned int  RightEncodedLineLocation;            /**< Active line number of 1st encoded line in one Right eye frame of the display data (-1=unknown).
+	unsigned int
+	LeftEncodedLineLocation;             /**< Active line number of 1st encoded line in one Left eye frame of the display data (-1=unknown).     */
+	unsigned int
+	RightEncodedLineLocation;            /**< Active line number of 1st encoded line in one Right eye frame of the display data (-1=unknown).
                                                   *  If format is Horizontally Packed, set RightEncodedLineLocation=LeftEncodedLineLocation             */
-    unsigned char BlankingColor;                 /**< Color to use when blanking (or masking off) any embedded L/R encoding.                             */
+	unsigned char
+	BlankingColor;                 /**< Color to use when blanking (or masking off) any embedded L/R encoding.                             */
 } SRC_3D_SOURCE_CONFIG;
 
-typedef struct _de3dframe
-{
-    unsigned char VIC;
-    unsigned char HB0;
-    unsigned char HB1;
-    unsigned char HB2;
-    unsigned char PB0;
-    unsigned char PB1;
-    unsigned char PB2;
-    unsigned char PB3;
-    unsigned char PB4;
-    unsigned char PB5;
-    unsigned char PB6;
-    unsigned char PB7;
+typedef struct _de3dframe {
+	unsigned char VIC;
+	unsigned char HB0;
+	unsigned char HB1;
+	unsigned char HB2;
+	unsigned char PB0;
+	unsigned char PB1;
+	unsigned char PB2;
+	unsigned char PB3;
+	unsigned char PB4;
+	unsigned char PB5;
+	unsigned char PB6;
+	unsigned char PB7;
 } DE3DFRAME ;
 
-typedef struct _set_de3d_frame
-{
-    unsigned char Vic;
-    unsigned int V_total;        // Vtotal -1
-    unsigned int V_act_start;    // VTotal -1 + Vactive_start -1
-    unsigned int V_act_end;      // Vactive end -1
-    unsigned int V_sync_end;     // LSB(Vtotal -1 + sync With)
-    unsigned int V_2D_active_total;     // V_2D_active_total
+typedef struct _set_de3d_frame {
+	unsigned char Vic;
+	unsigned int V_total;        // Vtotal -1
+	unsigned int V_act_start;    // VTotal -1 + Vactive_start -1
+	unsigned int V_act_end;      // Vactive end -1
+	unsigned int V_sync_end;     // LSB(Vtotal -1 + sync With)
+	unsigned int V_2D_active_total;     // V_2D_active_total
 
 } SET_DE3D_FRAME;
 
-typedef enum
-{
-    VSYNC_SEPARATED_HALF,       /**< VSync separated (field sequential) format.                         */
-    VSYNC_SEPARATED_FULL,       /**< VSync separated (frame sequential progressive) format.             */
-    VERT_PACKED_HALF,           /**< Over Under (vertically packed) half resolution format.             */
-    VERT_PACKED_FULL,           /**< Over Under (vertically packed) full resolution format.             */
-    HORIZ_PACKED_HALF,          /**< Side by Side (horizontally packed) half resolution format.         */
-    HORIZ_PACKED_FULL,          /**< Side by Side (horizontally packed) full resolution format.         */
-    UNDEFINED_FORMAT            /**< Undefined format.                                                  */
+typedef enum {
+	VSYNC_SEPARATED_HALF,       /**< VSync separated (field sequential) format.                         */
+	VSYNC_SEPARATED_FULL,       /**< VSync separated (frame sequential progressive) format.             */
+	VERT_PACKED_HALF,           /**< Over Under (vertically packed) half resolution format.             */
+	VERT_PACKED_FULL,           /**< Over Under (vertically packed) full resolution format.             */
+	HORIZ_PACKED_HALF,          /**< Side by Side (horizontally packed) half resolution format.         */
+	HORIZ_PACKED_FULL,          /**< Side by Side (horizontally packed) full resolution format.         */
+	UNDEFINED_FORMAT            /**< Undefined format.                                                  */
 } SRC_3D_FORMAT;
 
-typedef enum _pixel_mode
-{
-    SINGLE_PIXEL,
-    DUAL_PIXEL  ,
-    MODE_UNKNOWN
-}PIXEL_MODE;
+typedef enum _pixel_mode {
+	SINGLE_PIXEL,
+	DUAL_PIXEL,
+	MODE_UNKNOWN
+} PIXEL_MODE;
 
 
 //FIX_ID_010 xxxxx 	//Add JudgeBestEQ to avoid wrong EQ setting
@@ -439,17 +436,16 @@ typedef enum _pixel_mode
 
 //FIX_ID_001 xxxxx Add Auto EQ with Manual EQ
 #ifdef _SUPPORT_EQ_ADJUST_
-struct it6602_eq_data
-{
-unsigned char ucEQState;
-unsigned char ucAuthR0;								//20130327 for R0 fail issue
-unsigned char ucECCvalue;								//20130328 for acc ecc error
-unsigned char ucECCfailCount;							//20130328 for acc ecc error
-unsigned char ucPkt_Err;
-unsigned char ucPortID;
-unsigned char f_manualEQadjust;
+struct it6602_eq_data {
+	unsigned char ucEQState;
+	unsigned char ucAuthR0;								//20130327 for R0 fail issue
+	unsigned char ucECCvalue;								//20130328 for acc ecc error
+	unsigned char ucECCfailCount;							//20130328 for acc ecc error
+	unsigned char ucPkt_Err;
+	unsigned char ucPortID;
+	unsigned char f_manualEQadjust;
 //FIX_ID_010 xxxxx 	//Add JudgeBestEQ to avoid wrong EQ setting
-unsigned char ErrorCount[MaxEQIndex];
+	unsigned char ErrorCount[MaxEQIndex];
 //FIX_ID_010 xxxxx
 };
 #endif
@@ -458,27 +454,27 @@ unsigned char ErrorCount[MaxEQIndex];
 
 
 //FIX_ID_005 xxxxx	//Add Cbus Event Handler
-	#define B_MSC_Waiting 		0x10
-	#define B_DevCapChange 		0x08
-	#define B_3DSupporpt 		0x04 // bit2 B_3DSupporpt
-	#define B_ReadDevCap 		0x02 // bit1 B_ReadDevCap
-	#define B_DiscoveryDone 		0x01 // bit0 B_DiscoveryDone
+#define B_MSC_Waiting 		0x10
+#define B_DevCapChange 		0x08
+#define B_3DSupporpt 		0x04 // bit2 B_3DSupporpt
+#define B_ReadDevCap 		0x02 // bit1 B_ReadDevCap
+#define B_DiscoveryDone 		0x01 // bit0 B_DiscoveryDone
 //FIX_ID_005 xxxxx
 
 //FIX_ID_014 xxxxx
-	#define B_PORT1_TimingChgEvent	0x40
-	#define B_PORT1_TMDSEvent	0x20
-	#define B_PORT1_Waiting		0x10
-	#define B_PORT0_TimingChgEvent	0x04
-	#define B_PORT0_TMDSEvent	0x02
-	#define B_PORT0_Waiting		0x01
+#define B_PORT1_TimingChgEvent	0x40
+#define B_PORT1_TMDSEvent	0x20
+#define B_PORT1_Waiting		0x10
+#define B_PORT0_TimingChgEvent	0x04
+#define B_PORT0_TMDSEvent	0x02
+#define B_PORT0_Waiting		0x01
 //FIX_ID_014 xxxxx
 
 //FIX_ID_013	xxxxx	//For MSC 3D request issue
 #define MSC_3D_VIC		(0x0010)
 #define MSC_3D_DTD		(0x0011)
 
-typedef enum _PARSE3D_STA{
+typedef enum _PARSE3D_STA {
 	PARSE3D_START,
 	PARSE3D_LEN,
 	PARSE3D_STRUCT_H,
@@ -487,18 +483,17 @@ typedef enum _PARSE3D_STA{
 	PARSE3D_MASK_L,
 	PARSE3D_VIC,
 	PARSE3D_DONE
-}PARSE3D_STA;
+} PARSE3D_STA;
 
-typedef enum _MHL3D_STATE{
+typedef enum _MHL3D_STATE {
 	MHL3D_REQ_START,
 	MHL3D_REQ_WRT,
 	MHL3D_GNT_WRT,
 	MHL3D_WRT_BURST,
 	MHL3D_REQ_DONE
-}MHL3D_STATE;
+} MHL3D_STATE;
 
-struct PARSE3D_STR
-{
+struct PARSE3D_STR {
 	unsigned char	uc3DEdidStart;
 	unsigned char	uc3DBlock;
 	unsigned char	uc3DInfor[32];
@@ -511,71 +506,69 @@ struct PARSE3D_STR
 //FIX_ID_013	xxxxx
 
 
-struct AVI_info
-{
-    unsigned char ColorMode;
-    unsigned char Colorimetry;
-    unsigned char ExtendedColorimetry;
-    unsigned char RGBQuantizationRange;
-    unsigned char YCCQuantizationRange;
-    unsigned char VIC;
-    //unsigned char PixelRepetition;
+struct AVI_info {
+	unsigned char ColorMode;
+	unsigned char Colorimetry;
+	unsigned char ExtendedColorimetry;
+	unsigned char RGBQuantizationRange;
+	unsigned char YCCQuantizationRange;
+	unsigned char VIC;
+	//unsigned char PixelRepetition;
 };
 
 
-struct it6602_dev_data
-{
-    Video_State_Type m_VState;
-    Audio_State_Type m_AState;
-    RxHDCP_State_Type m_RxHDCPState;
-    AUDIO_CAPS m_RxAudioCaps;
-    unsigned short m_SWResetTimeOut;
-    unsigned short m_VideoCountingTimer;
-    unsigned short m_AudioCountingTimer;
-    unsigned char m_ucCurrentHDMIPort;
-    unsigned char m_bOutputVideoMode;
-    unsigned char m_bInputVideoMode;
+struct it6602_dev_data {
+	Video_State_Type m_VState;
+	Audio_State_Type m_AState;
+	RxHDCP_State_Type m_RxHDCPState;
+	AUDIO_CAPS m_RxAudioCaps;
+	unsigned short m_SWResetTimeOut;
+	unsigned short m_VideoCountingTimer;
+	unsigned short m_AudioCountingTimer;
+	unsigned char m_ucCurrentHDMIPort;
+	unsigned char m_bOutputVideoMode;
+	unsigned char m_bInputVideoMode;
 //FIX_ID_039 xxxxx fix image flick when enable RGB limited / Full range convert
 #ifdef _AVOID_REDUNDANCE_CSC_
-    unsigned char m_Backup_OutputVideoMode;
-    unsigned char m_Backup_InputVideoMode;
+	unsigned char m_Backup_OutputVideoMode;
+	unsigned char m_Backup_InputVideoMode;
 #endif
 //FIX_ID_039 xxxxx
 
 
-    unsigned char m_ucSCDTOffCount;
-    unsigned char m_ucEccCount_P0;
-    unsigned char m_ucEccCount_P1;
-    unsigned char m_ucDeskew_P0;
-    unsigned char m_ucDeskew_P1;
+	unsigned char m_ucSCDTOffCount;
+	unsigned char m_ucEccCount_P0;
+	unsigned char m_ucEccCount_P1;
+	unsigned char m_ucDeskew_P0;
+	unsigned char m_ucDeskew_P1;
 
-    SRC_3D_SOURCE_CONFIG de3dframe_config;
-    DE3DFRAME s_Current3DFr;
+	SRC_3D_SOURCE_CONFIG de3dframe_config;
+	DE3DFRAME s_Current3DFr;
 
-    unsigned char oldVIC;
-    unsigned char newVIC;
-    unsigned char  f_de3dframe_hdmi;
+	unsigned char oldVIC;
+	unsigned char newVIC;
+	unsigned char  f_de3dframe_hdmi;
 
 //FIX_ID_001 xxxxx Add Auto EQ with Manual EQ
-    #ifdef _SUPPORT_EQ_ADJUST_
-    struct it6602_eq_data EQPort[2];
-    #endif
+#ifdef _SUPPORT_EQ_ADJUST_
+	struct it6602_eq_data EQPort[2];
+#endif
 //FIX_ID_001 xxxxx
 
-    //FIX_ID_003 xxxxx	//Add IT6602 Video Output Configure setting
-    Video_Output_Configure m_VidOutConfigMode;
-    Video_DataTrigger_Mode m_VidOutDataTrgger;
-    Video_OutputSync_Mode m_VidOutSyncMode;
-    //FIX_ID_003 xxxxx
+	//FIX_ID_003 xxxxx	//Add IT6602 Video Output Configure setting
+	Video_Output_Configure m_VidOutConfigMode;
+	Video_DataTrigger_Mode m_VidOutDataTrgger;
+	Video_OutputSync_Mode m_VidOutSyncMode;
+	//FIX_ID_003 xxxxx
 //FIX_ID_005 xxxxx	//Add Cbus Event Handler
-    unsigned char CBusIntEvent;
-    unsigned char CBusSeqNo;
-    unsigned char CBusWaitNo;
+	unsigned char CBusIntEvent;
+	unsigned char CBusSeqNo;
+	unsigned char CBusWaitNo;
 //FIX_ID_005 xxxxx
 
 //FIX_ID_014 xxxxx	//Add Cbus Event Handler
-    unsigned char HDMIIntEvent;
-    unsigned char HDMIWaitNo[2];
+	unsigned char HDMIIntEvent;
+	unsigned char HDMIWaitNo[2];
 //FIX_ID_014 xxxxx
 
 //FIX_ID_021 xxxxx		//To use CP_100ms for CBus_100ms and CEC_100m
@@ -589,43 +582,43 @@ struct it6602_dev_data
 //FIX_ID_021 xxxxx
 
 	//AVI_info m_avi;
-    unsigned char ColorMode;
-    unsigned char Colorimetry;
-    unsigned char ExtendedColorimetry;
-    unsigned char RGBQuantizationRange;
-    unsigned char YCCQuantizationRange;
-    unsigned char VIC;
+	unsigned char ColorMode;
+	unsigned char Colorimetry;
+	unsigned char ExtendedColorimetry;
+	unsigned char RGBQuantizationRange;
+	unsigned char YCCQuantizationRange;
+	unsigned char VIC;
 
 
 
 //FIX_ID_034 xxxxx //Add MHL HPD Control by it6602HPDCtrl( )
-    unsigned char m_DiscoveryDone;
+	unsigned char m_DiscoveryDone;
 //FIX_ID_034 xxxxx
 
 //FIX_ID_037 xxxxx //Allion MHL compliance issue !!!
 //xxxxx 2014-0529 //Manual Content On/Off
-    unsigned char m_RAP_ContentOff;
-    unsigned char m_HDCP_ContentOff;
+	unsigned char m_RAP_ContentOff;
+	unsigned char m_HDCP_ContentOff;
 //xxxxx
 //FIX_ID_037 xxxxx
 
-    PIXEL_MODE pixelMode;	//Output TTL Pixel mode
-    unsigned char GCP_CD;	//Output Color Depth
-    unsigned char  DE3DFormat_HDMIFlag:1;
-    unsigned char  FramePacking_Flag:1;
-    unsigned char  TopAndBottom_Flag:1;
-    unsigned char  SideBySide_Flag:1;
+	PIXEL_MODE pixelMode;	//Output TTL Pixel mode
+	unsigned char GCP_CD;	//Output Color Depth
+	unsigned char  DE3DFormat_HDMIFlag: 1;
+	unsigned char  FramePacking_Flag: 1;
+	unsigned char  TopAndBottom_Flag: 1;
+	unsigned char  SideBySide_Flag: 1;
 
 
 
 
-    #ifdef _IT6607_GeNPacket_Usage_
-    BYTE m_PollingPacket;
-    BYTE m_PacketState;
-    BYTE m_ACPState;
-    BYTE m_GeneralRecPackType;
-    BYTE m_GamutPacketRequest:1;
-    #endif
+#ifdef _IT6607_GeNPacket_Usage_
+	BYTE m_PollingPacket;
+	BYTE m_PacketState;
+	BYTE m_ACPState;
+	BYTE m_GeneralRecPackType;
+	BYTE m_GamutPacketRequest: 1;
+#endif
 
 //#if(_SUPPORT_HDCP_)
 //    //HDCP
@@ -634,34 +627,34 @@ struct it6602_dev_data
 //    unsigned int HDCPFireCnt ;
 //#endif
 
-    //CBUS MSC
-    unsigned char Mhl_devcap[16];
-    unsigned char txmsgdata[2];
-    unsigned char rxmsgdata[2];
-    unsigned char txscrpad[16];
-    unsigned char rxscrpad[16];
-    unsigned char RCPTxArray[MAXRCPINDEX];
-    unsigned char	RCPhead;
-    unsigned char	RCPtail;
-    RCPState_Type RCPState;
-    RCPResult_Type RCPResult;
+	//CBUS MSC
+	unsigned char Mhl_devcap[16];
+	unsigned char txmsgdata[2];
+	unsigned char rxmsgdata[2];
+	unsigned char txscrpad[16];
+	unsigned char rxscrpad[16];
+	unsigned char RCPTxArray[MAXRCPINDEX];
+	unsigned char	RCPhead;
+	unsigned char	RCPtail;
+	RCPState_Type RCPState;
+	RCPResult_Type RCPResult;
 //FIX_ID_015	xxxxx peer device no response
-    unsigned char RCPCheckResponse;
+	unsigned char RCPCheckResponse;
 //FIX_ID_015	xxxxx
 
 //FIX_ID_024	xxxxx Fixed for RCP compliance issue
-    unsigned char m_bRCPTimeOut:1;
-    unsigned char m_bRCPError:1;
+	unsigned char m_bRCPTimeOut: 1;
+	unsigned char m_bRCPError: 1;
 //FIX_ID_024	xxxxx
-    unsigned char m_bRxAVmute:1;
-    unsigned char m_bVideoOnCountFlag:1;
-    unsigned char m_MuteAutoOff:1;
-    unsigned char m_bUpHDMIMode:1;
-    unsigned char m_bUpHDCPMode:1;
-    unsigned char m_NewAVIInfoFrameF:1;
-    unsigned char m_NewAUDInfoFrameF:1;
-    unsigned char m_HDCPRepeater:1;
-    unsigned char m_MuteByPKG:1;
+	unsigned char m_bRxAVmute: 1;
+	unsigned char m_bVideoOnCountFlag: 1;
+	unsigned char m_MuteAutoOff: 1;
+	unsigned char m_bUpHDMIMode: 1;
+	unsigned char m_bUpHDCPMode: 1;
+	unsigned char m_NewAVIInfoFrameF: 1;
+	unsigned char m_NewAUDInfoFrameF: 1;
+	unsigned char m_HDCPRepeater: 1;
+	unsigned char m_MuteByPKG: 1;
 
 };
 
@@ -688,7 +681,7 @@ struct it6602_dev_data
 char IT6602_fsm_init(void);
 /* HDMI RX functions   *********************************************************/
 void it6602PortSelect(unsigned char ucPortSel);
-void it6602HPDCtrl(unsigned char ucport,unsigned char ucEnable)	;
+void it6602HPDCtrl(unsigned char ucport, unsigned char ucEnable)	;
 /* HDMI Audio function    *********************************************************/
 /* HDMI Video function    *********************************************************/
 /* HDMI Interrupt function    *********************************************************/
@@ -729,23 +722,24 @@ class IT66021 : public device::I2C
 public:
 	IT66021(I2CARG arg);
 	virtual ~IT66021();
-	
+
 	EDID *edid;
 
 	work_s work;
-	
+
 	struct it6602_dev_data it6602DEV;
 
 	STRU_HDMI_RX_STATUS s_st_hdmiRxStatus;
 
 	uint8_t HDMI_RX_MapToDeviceIndex(ENUM_HAL_HDMI_RX e_hdmiIndex);
 
-	uint32_t HDMI_RX_CheckVideoFormatChangeOrNot(ENUM_HAL_HDMI_RX e_hdmiIndex, 
-                                                      uint16_t u16_width, 
-                                                      uint16_t u16_hight, 
-                                                      uint8_t u8_framerate);
+	uint32_t HDMI_RX_CheckVideoFormatChangeOrNot(ENUM_HAL_HDMI_RX e_hdmiIndex,
+			uint16_t u16_width,
+			uint16_t u16_hight,
+			uint8_t u8_framerate);
 
-	uint8_t IT_66021_GetVideoFormat(uint8_t index, uint16_t* widthPtr, uint16_t* hightPtr, uint8_t* framteratePtr, uint8_t* vic);
+	uint8_t IT_66021_GetVideoFormat(uint8_t index, uint16_t *widthPtr, uint16_t *hightPtr, uint8_t *framteratePtr,
+					uint8_t *vic);
 
 	void HDMI_RX_CheckFormatStatus(ENUM_HAL_HDMI_RX e_hdmiIndex, uint32_t b_noDiffCheck);
 
@@ -762,7 +756,7 @@ public:
 
 	unsigned char mhlrxrd(unsigned char offset);
 	unsigned char mhlrxwr(unsigned char offset, unsigned char ucdata);
-	
+
 	int read(unsigned address, void *data, unsigned count);
 	int write(unsigned address, void *data, unsigned count);
 
@@ -870,7 +864,7 @@ public:
 #endif
 
 
-/* EDID RAM  functions    *******************************************************/
+	/* EDID RAM  functions    *******************************************************/
 #ifdef _SUPPORT_EDID_RAM_
 	unsigned char UpdateEDIDRAM(unsigned char *pEDID, unsigned char BlockNUM);
 
@@ -880,7 +874,8 @@ public:
 	void EDIDRAMInitial(unsigned char *pIT6602EDID);
 	// unsigned char Find_Phyaddress_Location(_CODE unsigned char *pEDID,unsigned char Block_Number);
 	unsigned char Find_Phyaddress_Location(unsigned char *pEDID, unsigned char Block_Number);
-	void UpdateEDIDReg(unsigned char u8_VSDB_Addr, unsigned char CEC_AB, unsigned char CEC_CD, unsigned char Block1_CheckSum);
+	void UpdateEDIDReg(unsigned char u8_VSDB_Addr, unsigned char CEC_AB, unsigned char CEC_CD,
+			   unsigned char Block1_CheckSum);
 	void PhyAdrSet(void);
 #endif
 
diff --git a/src/drivers/it66021/it66021_audio.cpp b/src/drivers/it66021/it66021_audio.cpp
index c06b8da06a006e6a99745baff21cf0bb0f7b3fa2..bd511086c2c4e461e13dfe9de066fbd0dc33e562 100644
--- a/src/drivers/it66021/it66021_audio.cpp
+++ b/src/drivers/it66021/it66021_audio.cpp
@@ -38,15 +38,15 @@
 
 
 #ifdef _FIX_ID_028_
-    //xxxxx 2014-0417
-    //FIX_ID_028 xxxxx //For Debug Audio error with S2
-        #define AUDIO_READY_TIMEOUT                 	MS_TimeOut(0)	// change 100ms to 0 for speed up audio on
-    //FIX_ID_028 xxxxx
-    //xxxxx 2014-0417
+//xxxxx 2014-0417
+//FIX_ID_028 xxxxx //For Debug Audio error with S2
+#define AUDIO_READY_TIMEOUT                 	MS_TimeOut(0)	// change 100ms to 0 for speed up audio on
+//FIX_ID_028 xxxxx
+//xxxxx 2014-0417
 #else
-    //FIX_ID_023 xxxxx		//Fixed for Audio Channel Status Error with invalid HDMI source
-    #define AUDIO_READY_TIMEOUT                 	MS_TimeOut(200)
-    //FIX_ID_023 xxxxx
+//FIX_ID_023 xxxxx		//Fixed for Audio Channel Status Error with invalid HDMI source
+#define AUDIO_READY_TIMEOUT                 	MS_TimeOut(200)
+//FIX_ID_023 xxxxx
 #endif
 
 #define AUDIO_MONITOR_TIMEOUT               MS_TimeOut(150)
@@ -73,21 +73,20 @@ void IT66021::getHDMIRXInputAudio(AUDIO_CAPS *pAudioCaps)
 	pAudioCaps->AudSrcEnable = uc & M_AUDIO_CH;
 	pAudioCaps->AudSrcEnable |= hdmirxrd(REG_RX_0AA) & M_AUDIO_CH;
 
-	if ((uc & (B_HBRAUDIO | B_DSDAUDIO)) == 0)
-	{
+	if ((uc & (B_HBRAUDIO | B_DSDAUDIO)) == 0) {
 		uc = hdmirxrd(REG_RX_0AB); //REG_RX_AUD_CHSTAT0
 
-		if ((uc & B_NLPCM) == 0)
-		{
+		if ((uc & B_NLPCM) == 0) {
 			pAudioCaps->AudioFlag |= B_CAP_LPCM;
 		}
 	}
 
 #ifdef EnableCalFs
-	if (hdmirxrd(REG_RX_074) & 0x40)
-	{
+
+	if (hdmirxrd(REG_RX_074) & 0x40) {
 		AudioFsCal();
 	}
+
 #endif
 }
 
@@ -106,15 +105,13 @@ void IT66021::IT6602AudioOutputEnable(unsigned char bEnable)
 	hdmirxset(REG_RX_HWMuteCtrl, (B_HWAudMuteClrMode), (0));
 	aud_fiforst();
 
-	if (bEnable == TRUE)
-	{
+	if (bEnable == TRUE) {
 		hdmirxset(REG_RX_052, (B_TriI2SIO | B_TriSPDIF), 0x00);
 		it6602data->m_AState = ASTATE_AudioOn;
 
 		IT_INFO(" === IT6602AudioOutputEnable 11111111111 ==== \r\n");
-	}
-	else
-	{
+
+	} else {
 		hdmirxset(REG_RX_052, (B_TriI2SIO | B_TriSPDIF), (B_TriI2SIO | B_TriSPDIF));
 		it6602data->m_AState = ASTATE_AudioOff;
 
@@ -128,18 +125,16 @@ void IT66021::IT6602AudioOutputEnable(unsigned char bEnable)
 // ---------------------------------------------------------------------------
 void IT66021::IT6602AudioOutputEnable(unsigned char bEnable)
 {
-	if (bEnable == true)
-	{
+	if (bEnable == true) {
 		hdmirxset(REG_RX_052, (B_TriI2SIO | B_TriSPDIF), 0x00);
-	}
-	else
-	{
+
+	} else {
 #ifdef EnableCalFs
 		//FIX_ID_023 xxxxx		//Fixed for Audio Channel Status Error with invalid HDMI source
 		m_u16TMDSCLK = 0;
 		m_AudioChannelStatusErrorCount = 0;
 		hdmirxset(REG_RX_074, 0x40, 0x00); // reg74[6]=0 disable Force FS mode
-										   //FIX_ID_023 xxxxx
+		//FIX_ID_023 xxxxx
 #endif
 
 		hdmirxset(REG_RX_052, (B_TriI2SIO | B_TriSPDIF), (B_TriI2SIO | B_TriSPDIF));
@@ -153,8 +148,7 @@ void IT66021::IT6602SwitchAudioState(struct it6602_dev_data *it6602, Audio_State
 {
 	//	unsigned char uc;
 
-	if (it6602->m_AState == state)
-	{
+	if (it6602->m_AState == state) {
 		return;
 	}
 
@@ -163,13 +157,13 @@ void IT66021::IT6602SwitchAudioState(struct it6602_dev_data *it6602, Audio_State
 	it6602->m_AState = state;
 	//AssignAudioVirtualTime();
 
-	switch (it6602->m_AState)
-	{
+	switch (it6602->m_AState) {
 	case ASTATE_AudioOff:
 		hdmirxset(REG_RX_RST_CTRL, B_AUDRST, B_AUDRST);
 		IT6602AudioOutputEnable(false);
 
 		break;
+
 	case ASTATE_RequestAudio:
 		IT6602AudioOutputEnable(false);
 
@@ -190,10 +184,11 @@ void IT66021::IT6602SwitchAudioState(struct it6602_dev_data *it6602, Audio_State
 		IT6602AudioOutputEnable(true);
 
 		IT_INFO("Cat6023 Audio--> Audio flag=%02X,Ch No=%02X,Fs=%02X ... \n",
-				 (int)it6602->m_RxAudioCaps.AudioFlag,
-				 (int)it6602->m_RxAudioCaps.AudSrcEnable,
-				 (int)it6602->m_RxAudioCaps.SampleFreq);
+			(int)it6602->m_RxAudioCaps.AudioFlag,
+			(int)it6602->m_RxAudioCaps.AudSrcEnable,
+			(int)it6602->m_RxAudioCaps.SampleFreq);
 		break;
+
 	default:
 		break;
 	}
@@ -210,46 +205,40 @@ void IT66021::IT6602AudioHandler(struct it6602_dev_data *it6602)
 {
 	//    unsigned char uc;
 
-	if (it6602->m_AudioCountingTimer > MS_LOOP)
-	{
+	if (it6602->m_AudioCountingTimer > MS_LOOP) {
 		it6602->m_AudioCountingTimer -= MS_LOOP;
-	}
-	else
-	{
+
+	} else {
 		it6602->m_AudioCountingTimer = 0;
 	}
 
-	if (it6602->m_RxHDCPState == RxHDCP_ModeCheck)
+	if (it6602->m_RxHDCPState == RxHDCP_ModeCheck) {
 		return;
+	}
 
-	switch (it6602->m_AState)
-	{
+	switch (it6602->m_AState) {
 	case ASTATE_RequestAudio:
 
 		getHDMIRXInputAudio(&it6602->m_RxAudioCaps);
 
-		if (it6602->m_RxAudioCaps.AudioFlag & B_CAP_AUDIO_ON)
-		{
+		if (it6602->m_RxAudioCaps.AudioFlag & B_CAP_AUDIO_ON) {
 
 			hdmirxset(REG_RX_MCLK_CTRL, M_MCLKSel, B_256FS);
 
-			if (it6602->m_RxAudioCaps.AudioFlag & B_CAP_HBR_AUDIO)
-			{
+			if (it6602->m_RxAudioCaps.AudioFlag & B_CAP_HBR_AUDIO) {
 				IT_INFO("+++++++++++ B_CAP_HBR_AUDIO +++++++++++++++++\n");
 
 				hdmirxset(REG_RX_MCLK_CTRL, M_MCLKSel, B_128FS); // MCLK = 128fs only for HBR audio
 
 				hdmirx_SetHWMuteClrMode();
 				hdmirx_ResetAudio();
-			}
-			else if (it6602->m_RxAudioCaps.AudioFlag & B_CAP_DSD_AUDIO)
-			{
+
+			} else if (it6602->m_RxAudioCaps.AudioFlag & B_CAP_DSD_AUDIO) {
 
 				hdmirx_SetHWMuteClrMode();
 				hdmirx_ResetAudio();
-			}
-			else
-			{
+
+			} else {
 
 				hdmirxset(REG_RX_HWMuteCtrl, B_HWMuteClr, 0x00);
 				hdmirx_SetHWMuteClrMode();
@@ -258,6 +247,7 @@ void IT66021::IT6602AudioHandler(struct it6602_dev_data *it6602)
 
 			IT6602SwitchAudioState(it6602, ASTATE_WaitForReady);
 		}
+
 		break;
 
 	case ASTATE_WaitForReady:
@@ -268,16 +258,17 @@ void IT66021::IT6602AudioHandler(struct it6602_dev_data *it6602)
 		TMDSGet();
 //FIX_ID_023 xxxxx
 #endif
-		if (it6602->m_AudioCountingTimer == 0)
-		{
+
+		if (it6602->m_AudioCountingTimer == 0) {
 			IT6602SwitchAudioState(it6602, ASTATE_AudioOn);
 		}
+
 		break;
 
 	case ASTATE_AudioOn:
+
 		//if(AudioTimeOutCheck(AUDIO_MONITOR_TIMEOUT)==TRUE)
-		if (it6602->m_AudioCountingTimer == 0)
-		{
+		if (it6602->m_AudioCountingTimer == 0) {
 			AUDIO_CAPS CurAudioCaps;
 			//it6602->m_AudioCountingTimer = GetCurrentVirtualTime();
 			//AssignAudioTimerTimeout(AUDIO_MONITOR_TIMEOUT);
@@ -285,13 +276,16 @@ void IT66021::IT6602AudioHandler(struct it6602_dev_data *it6602)
 
 			getHDMIRXInputAudio(&CurAudioCaps);
 
-			if (it6602->m_RxAudioCaps.AudioFlag != CurAudioCaps.AudioFlag || it6602->m_RxAudioCaps.AudSrcEnable != CurAudioCaps.AudSrcEnable || it6602->m_RxAudioCaps.SampleFreq != CurAudioCaps.SampleFreq)
-			{
+			if (it6602->m_RxAudioCaps.AudioFlag != CurAudioCaps.AudioFlag
+			    || it6602->m_RxAudioCaps.AudSrcEnable != CurAudioCaps.AudSrcEnable
+			    || it6602->m_RxAudioCaps.SampleFreq != CurAudioCaps.SampleFreq) {
 				//it6602->m_ucHDMIAudioErrorCount=0;
 				IT6602SwitchAudioState(it6602, ASTATE_RequestAudio);
 			}
 		}
+
 		break;
+
 	default:
 		break;
 	}
diff --git a/src/drivers/it66021/it66021_config.h b/src/drivers/it66021/it66021_config.h
index 8dda1b303ec0e1863c52023a08bd66377113622e..afa973c0c8e256266777d4010f8575763f1bce53 100644
--- a/src/drivers/it66021/it66021_config.h
+++ b/src/drivers/it66021/it66021_config.h
@@ -5,12 +5,12 @@
 
 #define MS_TimeOut(x) (x+1)
 
-#ifndef TRUE 
-	#define TRUE  (1)
+#ifndef TRUE
+#define TRUE  (1)
 #endif
 
 #ifndef FALSE
-	#define FALSE (0)
+#define FALSE (0)
 #endif
 
 // #define IT66021DEBUG
diff --git a/src/drivers/it66021/it66021_define.h b/src/drivers/it66021/it66021_define.h
index 99f91182964c08cfb3604fbea6dce856289ab951..c2c75cb52c0d0f48da5dbefc639aeda34a003bd5 100644
--- a/src/drivers/it66021/it66021_define.h
+++ b/src/drivers/it66021/it66021_define.h
@@ -55,29 +55,29 @@ typedef unsigned int UINT, uint, *PUINT, *puint ;
 //////////////////////////////////////////////////
 
 typedef enum _SYS_STATUS {
-    ER_SUCCESS = 0,
-    ER_FAIL,
-    ER_RESERVED
+	ER_SUCCESS = 0,
+	ER_FAIL,
+	ER_RESERVED
 } SYS_STATUS ;
 
 #define abs(x) (((x)>=0)?(x):(-(x)))
 
 typedef struct {
-    WORD HActive ;
-    WORD VActive ;
-    WORD HTotal ;
-    WORD VTotal ;
-    LONG PCLK ;
-    BYTE xCnt ;
-    WORD HFrontPorch ;
-    WORD HSyncWidth ;
-    WORD HBackPorch ;
-    USHORT VFrontPorch ;
-    USHORT VSyncWidth ;
-    USHORT VBackPorch ;
-    BYTE ScanMode:1 ;
-    BYTE VPolarity:1 ;
-    BYTE HPolarity:1 ;
+	WORD HActive ;
+	WORD VActive ;
+	WORD HTotal ;
+	WORD VTotal ;
+	LONG PCLK ;
+	BYTE xCnt ;
+	WORD HFrontPorch ;
+	WORD HSyncWidth ;
+	WORD HBackPorch ;
+	USHORT VFrontPorch ;
+	USHORT VSyncWidth ;
+	USHORT VBackPorch ;
+	BYTE ScanMode: 1 ;
+	BYTE VPolarity: 1 ;
+	BYTE HPolarity: 1 ;
 } VTiming ;
 
 #define PROG 1
@@ -101,73 +101,73 @@ typedef struct {
 // 2006/10/31 added by jjtseng
 // for customized uc
 typedef struct _REGPAIR {
-    BYTE ucAddr ;
-    BYTE ucValue ;
+	BYTE ucAddr ;
+	BYTE ucValue ;
 } REGPAIR ;
 //~jjtseng 2006/10/31
 
 typedef struct {
-    BYTE AudioFlag ;
-    BYTE AudSrcEnable ;
-    BYTE SampleFreq ;
-    BYTE ChStat[5] ;
+	BYTE AudioFlag ;
+	BYTE AudSrcEnable ;
+	BYTE SampleFreq ;
+	BYTE ChStat[5] ;
 } AUDIO_CAPS ;
 
 
 typedef enum _Audio_State_Type {
-    ASTATE_AudioOff = 0,
-    ASTATE_RequestAudio ,
-    ASTATE_ResetAudio,
-    ASTATE_WaitForReady,
-    ASTATE_AudioOn ,
-    ASTATE_Reserved
+	ASTATE_AudioOff = 0,
+	ASTATE_RequestAudio,
+	ASTATE_ResetAudio,
+	ASTATE_WaitForReady,
+	ASTATE_AudioOn,
+	ASTATE_Reserved
 } Audio_State_Type ;
 
 typedef enum _TXVideo_State_Type {
-    TXVSTATE_Unplug = 0,
-    TXVSTATE_HPD,
-    TXVSTATE_WaitForMode,
-    TXVSTATE_WaitForVStable,
-    TXVSTATE_VideoInit,
-    TXVSTATE_VideoSetup,
-    TXVSTATE_VideoOn,
-    TXVSTATE_Reserved
+	TXVSTATE_Unplug = 0,
+	TXVSTATE_HPD,
+	TXVSTATE_WaitForMode,
+	TXVSTATE_WaitForVStable,
+	TXVSTATE_VideoInit,
+	TXVSTATE_VideoSetup,
+	TXVSTATE_VideoOn,
+	TXVSTATE_Reserved
 } TXVideo_State_Type ;
 
 
 typedef enum _TXAudio_State_Type {
-    TXASTATE_AudioOff = 0,
-    TXASTATE_AudioPrepare,
-    TXASTATE_AudioOn,
-    TXASTATE_AudioFIFOFail,
-    TXASTATE_Reserved
+	TXASTATE_AudioOff = 0,
+	TXASTATE_AudioPrepare,
+	TXASTATE_AudioOn,
+	TXASTATE_AudioFIFOFail,
+	TXASTATE_Reserved
 } TXAudio_State_Type ;
 
 typedef enum _RXHDCP_State_Type {
-    RXHDCP_Reset = 0,
-    RXHDCP_AuthStart,
-    RXHDCP_AuthDone,
-    RXHDCP_UpdateKSVList,
+	RXHDCP_Reset = 0,
+	RXHDCP_AuthStart,
+	RXHDCP_AuthDone,
+	RXHDCP_UpdateKSVList,
 //    RXHDCP_Ready,
 	RXHDCP_CAP_REady,
-    RXHDCP_FailReady,
-    RXHDCP_Reserved
+	RXHDCP_FailReady,
+	RXHDCP_Reserved
 } RXHDCP_State_Type ;
 
 
 
 typedef enum _ADC_State_Type {
-	ADCSTATE_DetectVideo =0,
-    ADCSTATE_WaitVstable,
-    ADCSTATE_ConfigVideo,
+	ADCSTATE_DetectVideo = 0,
+	ADCSTATE_WaitVstable,
+	ADCSTATE_ConfigVideo,
 	ADCSTATE_Video_ON,
-    ADCSTATE_Reserved
+	ADCSTATE_Reserved
 } ADC_State_Type ;
 
 typedef enum {
-    PCLK_LOW = 0 ,
-    PCLK_MEDIUM,
-    PCLK_HIGH
+	PCLK_LOW = 0,
+	PCLK_MEDIUM,
+	PCLK_HIGH
 } VIDEOPCLKLEVEL ;
 
 ///////////////////////////////////////////////////////////////////////
@@ -192,18 +192,16 @@ typedef enum {
 #define F_MODE_EN_DITHER (1<<7) // output mode only, and loaded from EEPROM
 
 
-typedef union _VideoFormatCode
-{
-    struct _VFC
-    {
-        BYTE colorfmt:2 ;
-        BYTE interlace:1 ;
-        BYTE Colorimetry:1 ;
-        BYTE Quantization:1 ;
-        BYTE UpDownFilter:1 ;
-        BYTE Dither:1 ;
-    } VFCCode ;
-    unsigned char VFCByte ;
+typedef union _VideoFormatCode {
+	struct _VFC {
+		BYTE colorfmt: 2 ;
+		BYTE interlace: 1 ;
+		BYTE Colorimetry: 1 ;
+		BYTE Quantization: 1 ;
+		BYTE UpDownFilter: 1 ;
+		BYTE Dither: 1 ;
+	} VFCCode ;
+	unsigned char VFCByte ;
 } VideoFormatCode ;
 
 #define T_MODE_CCIR656 (1<<0)
@@ -273,117 +271,116 @@ typedef union _VideoFormatCode
 #define ISRC1_PKT_LEN 16
 #define ISRC2_PKT_LEN 16
 
-typedef union _AVI_InfoFrame
-{
-    struct {
-        BYTE Type ;
-        BYTE Ver ;
-        BYTE Len ;
-
-        BYTE Scan:2 ;
-        BYTE BarInfo:2 ;
-        BYTE ActiveFmtInfoPresent:1 ;
-        BYTE ColorMode:2 ;
-        BYTE FU1:1 ;
-
-        BYTE ActiveFormatAspectRatio:4 ;
-        BYTE PictureAspectRatio:2 ;
-        BYTE Colorimetry:2 ;
-
-        BYTE Scaling:2 ;
-        BYTE FU2:6 ;
-
-        BYTE VIC:7 ;
-        BYTE FU3:1 ;
-
-        BYTE PixelRepetition:4 ;
-        BYTE FU4:4 ;
-
-        SHORT Ln_End_Top ;
-        SHORT Ln_Start_Bottom ;
-        SHORT Pix_End_Left ;
-        SHORT Pix_Start_Right ;
-    } info ;
-    struct {
-        BYTE AVI_HB[3] ;
-        BYTE AVI_DB[AVI_INFOFRAME_LEN] ;
-    } pktbyte ;
+typedef union _AVI_InfoFrame {
+	struct {
+		BYTE Type ;
+		BYTE Ver ;
+		BYTE Len ;
+
+		BYTE Scan: 2 ;
+		BYTE BarInfo: 2 ;
+		BYTE ActiveFmtInfoPresent: 1 ;
+		BYTE ColorMode: 2 ;
+		BYTE FU1: 1 ;
+
+		BYTE ActiveFormatAspectRatio: 4 ;
+		BYTE PictureAspectRatio: 2 ;
+		BYTE Colorimetry: 2 ;
+
+		BYTE Scaling: 2 ;
+		BYTE FU2: 6 ;
+
+		BYTE VIC: 7 ;
+		BYTE FU3: 1 ;
+
+		BYTE PixelRepetition: 4 ;
+		BYTE FU4: 4 ;
+
+		SHORT Ln_End_Top ;
+		SHORT Ln_Start_Bottom ;
+		SHORT Pix_End_Left ;
+		SHORT Pix_Start_Right ;
+	} info ;
+	struct {
+		BYTE AVI_HB[3] ;
+		BYTE AVI_DB[AVI_INFOFRAME_LEN] ;
+	} pktbyte ;
 } AVI_InfoFrame ;
 
 typedef union _Audio_InfoFrame {
 
-    struct {
-        BYTE Type ;
-        BYTE Ver ;
-        BYTE Len ;
+	struct {
+		BYTE Type ;
+		BYTE Ver ;
+		BYTE Len ;
 
-        BYTE AudioChannelCount:3 ;
-        BYTE RSVD1:1 ;
-        BYTE AudioCodingType:4 ;
+		BYTE AudioChannelCount: 3 ;
+		BYTE RSVD1: 1 ;
+		BYTE AudioCodingType: 4 ;
 
-        BYTE SampleSize:2 ;
-        BYTE SampleFreq:3 ;
-        BYTE Rsvd2:3 ;
+		BYTE SampleSize: 2 ;
+		BYTE SampleFreq: 3 ;
+		BYTE Rsvd2: 3 ;
 
-        BYTE FmtCoding ;
+		BYTE FmtCoding ;
 
-        BYTE SpeakerPlacement ;
+		BYTE SpeakerPlacement ;
 
-        BYTE Rsvd3:3 ;
-        BYTE LevelShiftValue:4 ;
-        BYTE DM_INH:1 ;
-    } info ;
+		BYTE Rsvd3: 3 ;
+		BYTE LevelShiftValue: 4 ;
+		BYTE DM_INH: 1 ;
+	} info ;
 
-    struct {
-        BYTE AUD_HB[3] ;
-        BYTE AUD_DB[AUDIO_INFOFRAME_LEN] ;
-    } pktbyte ;
+	struct {
+		BYTE AUD_HB[3] ;
+		BYTE AUD_DB[AUDIO_INFOFRAME_LEN] ;
+	} pktbyte ;
 
 } Audio_InfoFrame ;
 
 typedef union _MPEG_InfoFrame {
-    struct {
-        BYTE Type ;
-        BYTE Ver ;
-        BYTE Len ;
-
-        ULONG MpegBitRate ;
-
-        BYTE MpegFrame:2 ;
-        BYTE Rvsd1:2 ;
-        BYTE FieldRepeat:1 ;
-        BYTE Rvsd2:3 ;
-    } info ;
-    struct {
-        BYTE MPG_HB[3] ;
-        BYTE MPG_DB[MPEG_INFOFRAME_LEN] ;
-    } pktbyte ;
+	struct {
+		BYTE Type ;
+		BYTE Ver ;
+		BYTE Len ;
+
+		ULONG MpegBitRate ;
+
+		BYTE MpegFrame: 2 ;
+		BYTE Rvsd1: 2 ;
+		BYTE FieldRepeat: 1 ;
+		BYTE Rvsd2: 3 ;
+	} info ;
+	struct {
+		BYTE MPG_HB[3] ;
+		BYTE MPG_DB[MPEG_INFOFRAME_LEN] ;
+	} pktbyte ;
 } MPEG_InfoFrame ;
 
 // Source Product Description
 typedef union _SPD_InfoFrame {
-    struct {
-        BYTE Type ;
-        BYTE Ver ;
-        BYTE Len ;
-
-        char VN[8] ; // vendor name character in 7bit ascii characters
-        char PD[16] ; // product description character in 7bit ascii characters
-        BYTE SourceDeviceInfomation ;
-    } info ;
-    struct {
-        BYTE SPD_HB[3] ;
-        BYTE SPD_DB[SPD_INFOFRAME_LEN] ;
-    } pktbyte ;
+	struct {
+		BYTE Type ;
+		BYTE Ver ;
+		BYTE Len ;
+
+		char VN[8] ; // vendor name character in 7bit ascii characters
+		char PD[16] ; // product description character in 7bit ascii characters
+		BYTE SourceDeviceInfomation ;
+	} info ;
+	struct {
+		BYTE SPD_HB[3] ;
+		BYTE SPD_DB[SPD_INFOFRAME_LEN] ;
+	} pktbyte ;
 } SPD_InfoFrame ;
 
 ///////////////////////////////////////////////////////////////////////////
 // Using for interface.
 ///////////////////////////////////////////////////////////////////////////
 struct VideoTiming {
-    ULONG VideoPixelClock ;
-    BYTE VIC ;
-    BYTE pixelrep ;
+	ULONG VideoPixelClock ;
+	BYTE VIC ;
+	BYTE pixelrep ;
 	BYTE outputVideoMode ;
 } ;
 
@@ -441,48 +438,48 @@ struct VideoTiming {
 
 
 typedef enum tagHDMI_Video_Type {
-    HDMI_Unkown = 0 ,
-    HDMI_640x480p60 = 1 ,
-    HDMI_480p60,
-    HDMI_480p60_16x9,
-    HDMI_720p60,
-    HDMI_1080i60,
-    HDMI_480i60,
-    HDMI_480i60_16x9,
-    HDMI_240p60,
-    HDMI_1440x480p60,
-    HDMI_1080p60 = 16,
-    HDMI_576p50,
-    HDMI_576p50_16x9,
-    HDMI_720p50,
-    HDMI_1080i50,
-    HDMI_576i50,
-    HDMI_576i50_16x9,
-    HDMI_288p50,
-    HDMI_1440x576p50,
-    HDMI_1080p50 = 31,
-    HDMI_1080p24,
-    HDMI_1080p25,
-    HDMI_1080p30
+	HDMI_Unkown = 0,
+	HDMI_640x480p60 = 1,
+	HDMI_480p60,
+	HDMI_480p60_16x9,
+	HDMI_720p60,
+	HDMI_1080i60,
+	HDMI_480i60,
+	HDMI_480i60_16x9,
+	HDMI_240p60,
+	HDMI_1440x480p60,
+	HDMI_1080p60 = 16,
+	HDMI_576p50,
+	HDMI_576p50_16x9,
+	HDMI_720p50,
+	HDMI_1080i50,
+	HDMI_576i50,
+	HDMI_576i50_16x9,
+	HDMI_288p50,
+	HDMI_1440x576p50,
+	HDMI_1080p50 = 31,
+	HDMI_1080p24,
+	HDMI_1080p25,
+	HDMI_1080p30
 } HDMI_Video_Type ;
 
 typedef enum tagHDMI_Aspec {
-    HDMI_4x3 ,
-    HDMI_16x9
+	HDMI_4x3,
+	HDMI_16x9
 } HDMI_Aspec;
 
 typedef enum tagHDMI_OutputColorMode {
-    HDMI_RGB444,
-    HDMI_YUV444,
-    HDMI_YUV422
+	HDMI_RGB444,
+	HDMI_YUV444,
+	HDMI_YUV422
 } HDMI_OutputColorMode ;
 
 typedef enum tagHDMI_Colorimetry {
-    HDMI_ITU601,
-    HDMI_ITU709
+	HDMI_ITU601,
+	HDMI_ITU709
 } HDMI_Colorimetry ;
 
-typedef enum tagMODE_ID{
+typedef enum tagMODE_ID {
 	CEA_640x480p60,
 	CEA_720x480p60,
 	CEA_1280x720p60,
@@ -569,27 +566,26 @@ typedef enum tagMODE_ID{
 
 
 
-typedef enum _IT6536_INTERFACE_
-{
+typedef enum _IT6536_INTERFACE_ {
 #ifdef _SUPPORT_ADC_
-   PORT_ADC0  ,
-   PORT_ADC1  ,
+	PORT_ADC0,
+	PORT_ADC1,
 #endif
 
-   PORT_HDMI  ,
-   PORT_DP    ,
-   PORT_Unknow
-}IT6536_INTERFACE;
+	PORT_HDMI,
+	PORT_DP,
+	PORT_Unknow
+} IT6536_INTERFACE;
 
 typedef enum HDCPState_Type {
-    HDCP_Reset = 0,
-    HDCP_AuthStart ,
-    HDCP_AuthDone,
-    HDCP_WaitKSV,
-    HDCP_CalcKSV,
-    HDCP_Ready,
-    HDCP_Fail,
-    HDCP_Unknown
+	HDCP_Reset = 0,
+	HDCP_AuthStart,
+	HDCP_AuthDone,
+	HDCP_WaitKSV,
+	HDCP_CalcKSV,
+	HDCP_Ready,
+	HDCP_Fail,
+	HDCP_Unknown
 } HDCPState;
 
 
diff --git a/src/drivers/it66021/it66021_i2c.h b/src/drivers/it66021/it66021_i2c.h
index ef2785c5f0f74045acaffa997467482bb221d180..2cacc39e01abce036b57a5132d1b9b13a8a02a4f 100644
--- a/src/drivers/it66021/it66021_i2c.h
+++ b/src/drivers/it66021/it66021_i2c.h
@@ -25,82 +25,73 @@
 #define IT66021_DEFAULT_BUS_SPEED 100000
 
 
-typedef struct 
-{   
-    const char *name;
-    const char *devname;
-    uint8_t bus;
-    uint32_t address;
-    uint32_t frequency;
+typedef struct {
+	const char *name;
+	const char *devname;
+	uint8_t bus;
+	uint32_t address;
+	uint32_t frequency;
 
 } I2CARG; // I2C parameter
 
-typedef enum
-{
+typedef enum {
 	IT66021TYPE_A,
 	IT66021TYPE_B,
 } IT66021TYPE;
 
 
-class IT66021; 
+class IT66021;
+
+typedef struct {
+	I2CARG *it66021arg;
 
-typedef struct
-{
-    I2CARG *it66021arg;
-	
 	I2CARG *edidarg;
 
 	IT66021TYPE type;
 
-    IT66021 *dev;
+	IT66021 *dev;
 
 } IT66021_BUS_ARG;
 
 typedef void (*HAL_HDMI_RxHandle)(void *pu8_rxBuf);
 
-typedef struct
-{
-    uint16_t u16_width;
-    uint16_t u16_hight;
-    uint8_t  u8_framerate;
-    uint8_t  u8_vic;
+typedef struct {
+	uint16_t u16_width;
+	uint16_t u16_hight;
+	uint8_t  u8_framerate;
+	uint8_t  u8_vic;
 } STRU_HDMI_RX_OUTPUT_FORMAT;
 
 
-typedef enum
-{
-    HAL_HDMI_POLLING = 0,
-    HAL_HDMI_INTERRUPT,
+typedef enum {
+	HAL_HDMI_POLLING = 0,
+	HAL_HDMI_INTERRUPT,
 } ENUM_HAL_HDMI_GETFORMATMETHOD;
 
 
-typedef enum
-{
-    HAL_HDMI_RX_16BIT = 0,
-    HAL_HDMI_RX_8BIT,
+typedef enum {
+	HAL_HDMI_RX_16BIT = 0,
+	HAL_HDMI_RX_8BIT,
 } ENUM_HAL_HDMI_COLOR_DEPTH;
 
 
-typedef struct
-{
-    ENUM_HAL_HDMI_GETFORMATMETHOD e_getFormatMethod;
-    ENUM_HAL_HDMI_COLOR_DEPTH e_colorDepth;
-    // STRU_HDMI_GPIOCONFIGURE st_interruptGpio;
-    uint8_t u8_hdmiToEncoderCh;
+typedef struct {
+	ENUM_HAL_HDMI_GETFORMATMETHOD e_getFormatMethod;
+	ENUM_HAL_HDMI_COLOR_DEPTH e_colorDepth;
+	// STRU_HDMI_GPIOCONFIGURE st_interruptGpio;
+	uint8_t u8_hdmiToEncoderCh;
 } STRU_HDMI_CONFIGURE;
 
-typedef struct
-{
-    uint8_t u8_devEnable;
-    STRU_HDMI_RX_OUTPUT_FORMAT st_videoFormat;
-    STRU_HDMI_CONFIGURE        st_configure;
+typedef struct {
+	uint8_t u8_devEnable;
+	STRU_HDMI_RX_OUTPUT_FORMAT st_videoFormat;
+	STRU_HDMI_CONFIGURE        st_configure;
 } STRU_HDMI_RX_STATUS;
 
-typedef enum
-{
-    HAL_HDMI_RX_1 = 0,
-    HAL_HDMI_RX_0,
-    HAL_HDMI_RX_MAX
+typedef enum {
+	HAL_HDMI_RX_1 = 0,
+	HAL_HDMI_RX_0,
+	HAL_HDMI_RX_MAX
 } ENUM_HAL_HDMI_RX;
 
 
diff --git a/src/drivers/it66021/it66021_main.cpp b/src/drivers/it66021/it66021_main.cpp
index ed83801ee0249b51b6d2a0f08d69855f084ab45b..ed1f7c4c180ed66453057dd658f873f939c78b2a 100644
--- a/src/drivers/it66021/it66021_main.cpp
+++ b/src/drivers/it66021/it66021_main.cpp
@@ -41,31 +41,28 @@
 #include "it66021_config.h"
 
 // static IT66021 *it66021_B = nullptr;
-static I2CARG IT66021_I2CARG_A = 
-{
+static I2CARG IT66021_I2CARG_A = {
 	.name 		= "it66021",
 	.devname 	= "/dev/it66021_A",
 	.bus 		= PX4_I2C_BUS_IT66021_A,
 	.address	= IT6602A0_HDMI_ADDR >> 1,
-	.frequency	= IT66021_DEFAULT_BUS_SPEED
+					     .frequency	= IT66021_DEFAULT_BUS_SPEED
 };
 
-static I2CARG IT66021_I2CARG_A_EDID = 
-{
+static I2CARG IT66021_I2CARG_A_EDID = {
 	.name 		= "it66021_edid",
 	.devname 	= "/dev/it66021_A_edid",
 	.bus 		= PX4_I2C_BUS_IT66021_A_EDID,
 	.address	= IT66021A_HDMI_ADDR_EDID >> 1,
-	.frequency	= IT66021_DEFAULT_BUS_SPEED
+			.frequency	= IT66021_DEFAULT_BUS_SPEED
 };
 
 
-static IT66021_BUS_ARG IT66021_BUS_ARG_A = 
-{
-    .it66021arg = &IT66021_I2CARG_A,
+static IT66021_BUS_ARG IT66021_BUS_ARG_A = {
+	.it66021arg = &IT66021_I2CARG_A,
 	.edidarg 	= &IT66021_I2CARG_A_EDID,
 	.type 		= IT66021TYPE_A,
-    .dev        = nullptr
+	.dev        = nullptr
 };
 
 static IT66021 *it66021_A 	= new IT66021(*IT66021_BUS_ARG_A.it66021arg);
@@ -123,8 +120,7 @@ int IT66021::init()
 	int ret;
 	ret = I2C::init();
 
-	if (ret != OK)
-	{
+	if (ret != OK) {
 		IT_INFO("ret != OK\r\n");
 		return ret;
 	}
@@ -142,37 +138,35 @@ int IT66021::probe()
 	uint8_t data[1] = {0};
 
 	_retries = 4;
-	
+
 	uint8_t res;
 
 	res = read(REG_RX_000, &data[0], 1);
 	IT_INFO("res = %d, data = %02x", res, data[0]);
-	
-	
-	if (res != OK || data[0] != 0x54)
-	{
+
+
+	if (res != OK || data[0] != 0x54) {
 		IT_INFO("read_reg1 fail \r\n");
 		return -EIO;
 	}
-	
+
 	res = read(REG_RX_001, &data[0], 1);
 
-	if (res != OK || data[0] != 0x49)
-	{
+	if (res != OK || data[0] != 0x49) {
 		IT_INFO("read_reg2 fail \r\n");
 		return -EIO;
 	}
 
 	res = read(REG_RX_002, &data[0], 1);
-	if (res != OK || data[0] != 0x02)
-	{
+
+	if (res != OK || data[0] != 0x02) {
 		IT_INFO("read_re3g fail \r\n");
 		return -EIO;
-	}	
+	}
 
 	res = read(REG_RX_003, &data[0], 1);
-	if (res != OK || data[0] != 0x68)
-	{
+
+	if (res != OK || data[0] != 0x68) {
 		IT_INFO("read_reg4 fail \r\n");
 		return -EIO;
 	}
@@ -207,10 +201,10 @@ int IT66021::write(unsigned address, void *data, unsigned count)
 {
 	uint8_t buf[32];
 
-	if (sizeof(buf) < (count + 1))
-	{
+	if (sizeof(buf) < (count + 1)) {
 		return -EIO;
 	}
+
 	buf[0] = address;
 
 	memcpy(&buf[1], data, count);
@@ -225,29 +219,31 @@ int IT66021::read(unsigned address, void *data, unsigned count)
 }
 
 SYS_STATUS IT66021::EDID_RAM_Write(unsigned char offset, unsigned char byteno, _CODE unsigned char *p_data)
-{	// EDID *edit= *this->edid;
-	EDID *edit= it66021_A_EDID;
-	if (edit->write(offset, p_data, byteno) == OK) 
-	{	
+{
+	// EDID *edit= *this->edid;
+	EDID *edit = it66021_A_EDID;
+
+	if (edit->write(offset, p_data, byteno) == OK) {
 		uint8_t value = EDID_RAM_Read(offset);
-		if (value != p_data[0])
-		{
+
+		if (value != p_data[0]) {
 			IT_INFO("edit write address = 0x%02x, value = 0x%02x \n", offset, p_data[0]);
 		}
-		
+
 		return ER_SUCCESS;
 	};
 
 	PX4_LOG("edit write address = 0x%02x, value = 0x%02x \n", offset, p_data[0]);
+
 	// TODO：
 	// IT_66021_WriteBytes(RX_I2C_EDID_MAP_ADDR, offset, byteno, p_data);
 	return ER_FAIL;
 }
 
 unsigned char IT66021::EDID_RAM_Read(unsigned char offset)
-{	
+{
 	uint8_t value = 0;
-	EDID *edit= it66021_A_EDID;//*this->edid;
+	EDID *edit = it66021_A_EDID; //*this->edid;
 	edit->read(offset, &value, 1);
 
 	return value;
@@ -261,24 +257,24 @@ unsigned char IT66021::hdmirxrd(unsigned char address)
 	// IT_66021_ReadByte(HdmiI2cAddr,RegAddr);
 	uint8_t data[1] = {0};
 
-	if (read(address, &data[0], 1))
-	{
+	if (read(address, &data[0], 1)) {
 		IT_INFO("hdmirxrd %x \n", address);
 
 		return 0;
 	}
+
 	return data[0];
 }
 
 unsigned char IT66021::hdmirxwr(unsigned char address, unsigned char data)
-{	
+{
 	unsigned char wres = write(address, &data, 1);
 	unsigned char rdrew = hdmirxrd(address);
-	
-	if (rdrew != data) 
-	{
+
+	if (rdrew != data) {
 		IT_INFO("address = %x, write data = %02x, rddata = %02x", address, data, rdrew);
 	}
+
 	return wres;
 }
 
@@ -297,14 +293,13 @@ unsigned char IT66021::hdmirxset(unsigned char offset, unsigned char mask, unsig
 void IT66021::cycle_trampoline(void *arg)
 {
 	IT66021 *dev = (IT66021 *)arg;
-	
-	if (ar_gpioread(27) == 0) 
-	{
+
+	if (ar_gpioread(27) == 0) {
 		IT_INFO("\r\n------------------------------\r\n");
 
 		dev->IT6602_Interrupt();
 
-    	dev->IT6602_fsm(); 		
+		dev->IT6602_fsm();
 
 
 
@@ -315,16 +310,17 @@ void IT66021::cycle_trampoline(void *arg)
 		// 	dev->Dump_ITEHDMIReg();
 		// }
 
-	} 
+	}
+
 	// else if (ar_gpioread(68) == 0)
 	// {
 	// 	IT_INFO("read gpio  68 zero");
 
 	// 	dev->IT6602_Interrupt();
 
-    // 	dev->IT6602_fsm(); 
+	// 	dev->IT6602_fsm();
 
-    // 	dev->IT6602_fsm(); 
+	// 	dev->IT6602_fsm();
 
 	// 	dev->HDMI_RX_CheckFormatStatus(HAL_HDMI_RX_0, HAL_HDMI_RX_FALSE);
 	// }
@@ -337,49 +333,48 @@ void IT66021::cycle_trampoline(void *arg)
 /* for now, we only support one g_it66021 */
 namespace it66021
 {
-	void usage(void);
-	int start(IT66021_BUS_ARG &bus_op);
-
-	_EXT_ITCM void usage()
-	{
-		IT_INFO("missing command: try 'start");
-		IT_INFO("options:");
-		IT_INFO("    -d I2C device (a or b)");
-	}
+void usage(void);
+int start(IT66021_BUS_ARG &bus_op);
 
-	_EXT_ITCM int start(IT66021_BUS_ARG &bus_op)
-	{
-		if (bus_op.dev != nullptr && it66021_i2c_intialized)
-		{
-			errx(1, "bus option already started");
-			return false;
-		}
+_EXT_ITCM void usage()
+{
+	IT_INFO("missing command: try 'start");
+	IT_INFO("options:");
+	IT_INFO("    -d I2C device (a or b)");
+}
 
-		it66021_i2c_intialized = true;
-		IT66021 *interface = bus_op.dev;		
+_EXT_ITCM int start(IT66021_BUS_ARG &bus_op)
+{
+	if (bus_op.dev != nullptr && it66021_i2c_intialized) {
+		errx(1, "bus option already started");
+		return false;
+	}
 
-		if (interface->init() != OK)
-		{
-			return false;
-		}
+	it66021_i2c_intialized = true;
+	IT66021 *interface = bus_op.dev;
 
-		// EDID 
-		interface->hdmirxset(REG_RX_0C0, 0x43, 0x40);
-		interface->hdmirxset(REG_RX_087, 0xFF, bus_op.edidarg->address | 0x01);
+	if (interface->init() != OK) {
+		return false;
+	}
 
-		EDID *edid = interface->edid;
-		if (edid->init() != OK)
-		{
-			return false;
-		}
-		it66021_A_EDID = edid;
+	// EDID
+	interface->hdmirxset(REG_RX_0C0, 0x43, 0x40);
+	interface->hdmirxset(REG_RX_087, 0xFF, bus_op.edidarg->address | 0x01);
 
-		interface->it66021_init();
-		
-		work_queue(LPWORK, &interface->work, (worker_t)&IT66021::cycle_trampoline, interface, USEC2TICK(1000));
+	EDID *edid = interface->edid;
 
-		return true;
+	if (edid->init() != OK) {
+		return false;
 	}
+
+	it66021_A_EDID = edid;
+
+	interface->it66021_init();
+
+	work_queue(LPWORK, &interface->work, (worker_t)&IT66021::cycle_trampoline, interface, USEC2TICK(1000));
+
+	return true;
+}
 } // namespace it66021
 
 
@@ -392,38 +387,35 @@ _EXT_ITCM int it66021_main(int argc, char *argv[])
 	const char *myoptarg = nullptr;
 	IT66021_BUS_ARG bus_option;
 
-	while ((ch = px4_getopt(argc, argv, "d:", &myoptind, &myoptarg)) != EOF)
-	{
-		switch (ch)
-		{
+	while ((ch = px4_getopt(argc, argv, "d:", &myoptind, &myoptarg)) != EOF) {
+		switch (ch) {
 		case 'd':
 			dev = *myoptarg;
 			break;
+
 		default:
 			it66021::usage();
 			exit(0);
 		}
 	}
 
-	if (myoptind >= argc)
-	{
+	if (myoptind >= argc) {
 		it66021::usage();
 		return false;
 	}
 
-	if (dev == 'a')
-	{
+	if (dev == 'a') {
 		// link relationship
 		bus_option = IT66021_BUS_ARG_A;
 		bus_option.dev = it66021_A;
 		it66021_A->edid = it66021_A_EDID;
 	}
+
 	// else if (dev == 'b')
 	// {
 	// 	bus_option = BUS_IT66021_B;
 	// }
-	else
-	{
+	else {
 		it66021::usage();
 		return false;
 	}
@@ -432,11 +424,11 @@ _EXT_ITCM int it66021_main(int argc, char *argv[])
 
 	IT_INFO("verb = %s", verb);
 
-	if (!strcmp(verb, "start"))
-	{
+	if (!strcmp(verb, "start")) {
 		it66021::start(bus_option);
 		return true;
 	}
+
 	it66021::usage();
 	return false;
 }
diff --git a/src/drivers/it66021/it66021_reg.h b/src/drivers/it66021/it66021_reg.h
index cd82d8fb7b89679781c0b55b9adc1b1d3c59f573..971fcd9879dffb07e79c1c00de98f82fbbc4d96a 100644
--- a/src/drivers/it66021/it66021_reg.h
+++ b/src/drivers/it66021/it66021_reg.h
@@ -307,7 +307,7 @@
 #define REG_RX_0FD 0xFD // REG_RX_0FD
 #define REG_RX_0FE 0xFE // REG_RX_0FE
 #define REG_RX_0FF 0xFF // REG_RX_0FF
-                        //
+//
 #define REG_RX_100 0x00 // REG_RX_100
 #define REG_RX_101 0x01 // REG_RX_101
 #define REG_RX_102 0x02 // REG_RX_102
@@ -603,7 +603,7 @@
 #define REG_RX_1FD 0xFD // REG_RX_1FD
 #define REG_RX_1FE 0xFE // REG_RX_1FE
 #define REG_RX_1FF 0xFF // REG_RX_1FF
-                        //
+//
 #define REG_RX_200 0x00 // REG_RX_200
 #define REG_RX_201 0x01 // REG_RX_201
 #define REG_RX_202 0x02 // REG_RX_202
@@ -926,9 +926,9 @@
 #define MHL_RX_1A 0x1A	//MHL_RX_1A
 #define MHL_RX_1B 0x1B	//MHL_RX_1B
 #define MHL_RX_1C 0x1C	//MHL_RX_1C
-	#define B_MSG_Busy 0x04 // bit2
-	#define B_MSC_Busy 0x02 // bit1
-	#define B_DDC_Busy 0x01 // bit0
+#define B_MSG_Busy 0x04 // bit2
+#define B_MSC_Busy 0x02 // bit1
+#define B_DDC_Busy 0x01 // bit0
 
 
 #define MHL_RX_1D 0x1D	//MHL_RX_1D
@@ -984,19 +984,19 @@
 #define MHL_RX_4F 0x4F	//MHL_RX_4F
 
 #define MHL_MSC_CtrlPacket0 0x50	//MHL_RX_50
-	#define B_WRITE_STAT_SET_INT 	0x80 // bit7
-	#define B_READ_DEVCAP 			0x40 // bit6
-	#define B_GET_MSC_ERRORCODE 	0x20 // bit5
-	#define B_GET_DDC_ERRORCODE 	0x10 // bit4
-	#define B_CLR_HPD 				0x08 // bit3
-	#define B_SET_HPD 				0x04 // bit2
-	#define B_GET_VENDOR_ID 		0x02 // bit1
-	#define B_GET_STATE 			0x01 // bit0
+#define B_WRITE_STAT_SET_INT 	0x80 // bit7
+#define B_READ_DEVCAP 			0x40 // bit6
+#define B_GET_MSC_ERRORCODE 	0x20 // bit5
+#define B_GET_DDC_ERRORCODE 	0x10 // bit4
+#define B_CLR_HPD 				0x08 // bit3
+#define B_SET_HPD 				0x04 // bit2
+#define B_GET_VENDOR_ID 		0x02 // bit1
+#define B_GET_STATE 			0x01 // bit0
 
 #define MHL_MSC_CtrlPacket1 0x51	//MHL_RX_51
-	#define B_FW_MODE 				0x80 // bit7
-	#define B_MSC_MSG 				0x02 // bit1
-	#define B_WRITE_BURST 			0x01 // bit0
+#define B_FW_MODE 				0x80 // bit7
+#define B_MSC_MSG 				0x02 // bit1
+#define B_WRITE_BURST 			0x01 // bit0
 
 #define MHL_RX_52 0x52	//MHL_RX_52
 #define MHL_RX_53 0x53	//MHL_RX_53
@@ -1178,250 +1178,250 @@
 /*****************************************************************************/
 /* Mask Definitions **********************************************************/
 /*****************************************************************************/
-	#define B_7 0x80 // bit7
-	#define B_6 0x40 // bit6
-	#define B_5 0x20 // bit5
-	#define B_4 0x10 // bit4
-	#define B_3 0x08 // bit3
-	#define B_2 0x04 // bit2
-	#define B_1 0x02 // bit1
-	#define B_0 0x01 // bit0
+#define B_7 0x80 // bit7
+#define B_6 0x40 // bit6
+#define B_5 0x20 // bit5
+#define B_4 0x10 // bit4
+#define B_3 0x08 // bit3
+#define B_2 0x04 // bit2
+#define B_1 0x02 // bit1
+#define B_0 0x01 // bit0
 
 
 #define REG_RX_P0_SYS_STATUS 0x0A
-	#define B_P0_SCDT 0x80 // bit7
-	#define B_P0_MHL_MODE 0x40 // bit6
-	#define B_P0_IPLL_LOCK 0x20 // bit5
-	#define B_P0_RXCK_SPEED 0x10 // bit4
-	#define B_P0_RXCK_VALID 0x08 // bit3
-	#define B_P0_VCLK_DET 0x04 // bit2
-	#define B_P0_HDMI_MODE 0x02 // bit1
-	#define B_P0_PWR5V_DET 0x01 // bit0
+#define B_P0_SCDT 0x80 // bit7
+#define B_P0_MHL_MODE 0x40 // bit6
+#define B_P0_IPLL_LOCK 0x20 // bit5
+#define B_P0_RXCK_SPEED 0x10 // bit4
+#define B_P0_RXCK_VALID 0x08 // bit3
+#define B_P0_VCLK_DET 0x04 // bit2
+#define B_P0_HDMI_MODE 0x02 // bit1
+#define B_P0_PWR5V_DET 0x01 // bit0
 
 #define REG_RX_P1_SYS_STATUS 0x0B
-	#define B_P1_SCDT 0x80 // bit7
-	#define B_P1_OPLL_LOCK 0x40 // bit6
-	#define B_P1_IPLL_LOCK 0x20 // bit5
-	#define B_P1_RXCK_SPEED 0x10 // bit4
-	#define B_P1_RXCK_VALID 0x08 // bit3
-	#define B_P1_VCLK_DET 0x04 // bit2
-	#define B_P1_HDMI_MODE 0x02 // bit1
-	#define B_P1_PWR5V_DET 0x01 // bit0
+#define B_P1_SCDT 0x80 // bit7
+#define B_P1_OPLL_LOCK 0x40 // bit6
+#define B_P1_IPLL_LOCK 0x20 // bit5
+#define B_P1_RXCK_SPEED 0x10 // bit4
+#define B_P1_RXCK_VALID 0x08 // bit3
+#define B_P1_VCLK_DET 0x04 // bit2
+#define B_P1_HDMI_MODE 0x02 // bit1
+#define B_P1_PWR5V_DET 0x01 // bit0
 
 #define REG_RX_RST_CTRL 0x10 // REG_RX_010
-	#define B_PWDACLK	0x80
-	#define B_PWDPCLK	0x40
-	#define B_EN_AUTO_AUDRST	0x20
-	#define B_EN_AUTO_VDORST	0x10
-	#define B_REGRST	0x08
-	#define B_EN_INTRST	0x04
-	#define B_AUDRST	0x02
-	#define B_VDORST	0x01
+#define B_PWDACLK	0x80
+#define B_PWDPCLK	0x40
+#define B_EN_AUTO_AUDRST	0x20
+#define B_EN_AUTO_VDORST	0x10
+#define B_REGRST	0x08
+#define B_EN_INTRST	0x04
+#define B_AUDRST	0x02
+#define B_VDORST	0x01
 
 #define REG_RX_RST2_CTRL 0x11 // REG_RX_011
-	#define B_P0_DCLKRST	0x08
-	#define B_P0_CDRRST		0x04
-	#define B_P0_HDCPRST	0x02
-	#define B_P0_SWRST		0x01
+#define B_P0_DCLKRST	0x08
+#define B_P0_CDRRST		0x04
+#define B_P0_HDCPRST	0x02
+#define B_P0_SWRST		0x01
 
 //#define REG_RX_018 0x18 // REG_RX_018
-	#define B_P1_DCLKRST	0x08
-	#define B_P1_CDRRST		0x04
-	#define B_P1_HDCPRST	0x02
-	#define B_P1_SWRST		0x01
+#define B_P1_DCLKRST	0x08
+#define B_P1_CDRRST		0x04
+#define B_P1_HDCPRST	0x02
+#define B_P1_SWRST		0x01
 
 //#define REG_RX_051 0x51 // REG_RX_051
-	#define B_PORT_SEL 0x01 // bit0
-	#define B_EN_DEBUG 0x02 // bit1
-	#define B_CCIR656 0x04 // bit2
-	#define B_DisPixRpt 0x08 // bit3
-	#define B_HALF_CLK 0x10 // bit4
-	#define B_OUT_DDR 0x20 // bit5
-	#define B_HALF_PCLKC 0x40 // bit6
-	#define B_PWD_CSC 0x80 // bit7
+#define B_PORT_SEL 0x01 // bit0
+#define B_EN_DEBUG 0x02 // bit1
+#define B_CCIR656 0x04 // bit2
+#define B_DisPixRpt 0x08 // bit3
+#define B_HALF_CLK 0x10 // bit4
+#define B_OUT_DDR 0x20 // bit5
+#define B_HALF_PCLKC 0x40 // bit6
+#define B_PWD_CSC 0x80 // bit7
 
 #define REG_RX_OUPT_CTRL1 0x52
-	#define B_HCLKSel        	0x80
-	#define B_EnSWHCLKSel 	0x40
-	#define B_DisVAutoMute    0x20
-	#define B_TriSPDIF   		0x10
-	#define B_TriI2SIO       	0x0F
+#define B_HCLKSel        	0x80
+#define B_EnSWHCLKSel 	0x40
+#define B_DisVAutoMute    0x20
+#define B_TriSPDIF   		0x10
+#define B_TriI2SIO       	0x0F
 
 #define REG_RX_OUPT_CTRL2  0x53 // REG_RX_053
-	#define B_VDGatting 0x80 // bit7 -> Enable output data gating to zero when no Video display
-	#define B_VIOSel 0x40 // bit6 -> 1: video IO enable depent on VIOenable
-	#define B_VDIOLLdisable 0x20 // bit5 -> 1: disable video IO QE0, QE1, QE12, QE13, QE24, QE25
-	#define B_VDIOLHdisable 0x10 // bit4 -> 1:  disable video IO QE2, QE3, QE14, QE15, QE26, QE27
-	#define B_TriVDIO 0x0E // bit2~1 -> 111: enable tri-state Video IO
-	#define B_TriSYNC 0x01 // bit0 ->1: Tristate video control signal IO
+#define B_VDGatting 0x80 // bit7 -> Enable output data gating to zero when no Video display
+#define B_VIOSel 0x40 // bit6 -> 1: video IO enable depent on VIOenable
+#define B_VDIOLLdisable 0x20 // bit5 -> 1: disable video IO QE0, QE1, QE12, QE13, QE24, QE25
+#define B_VDIOLHdisable 0x10 // bit4 -> 1:  disable video IO QE2, QE3, QE14, QE15, QE26, QE27
+#define B_TriVDIO 0x0E // bit2~1 -> 111: enable tri-state Video IO
+#define B_TriSYNC 0x01 // bit0 ->1: Tristate video control signal IO
 
 
 #define REG_RX_MCLK_CTRL    0x54
-	#define B_EnAsynRst	0x80
-	#define M_MCLKSel 	0x70
-	#define B_128FS 0x00
-	#define B_256FS 0x10
-	#define B_384FS 0x20
-	#define B_512FS 0x30
-	#define B_640FS 0x40
-	#define B_768FS 0x50
-	#define B_894FS 0x60
-	#define B_1024FS 0x70
+#define B_EnAsynRst	0x80
+#define M_MCLKSel 	0x70
+#define B_128FS 0x00
+#define B_256FS 0x10
+#define B_384FS 0x20
+#define B_512FS 0x30
+#define B_640FS 0x40
+#define B_768FS 0x50
+#define B_894FS 0x60
+#define B_1024FS 0x70
 
-	#define B_RCLKFreqSel	0x03
-	#define B_RCLKDIV2 0x0
-	#define B_RCLKDIV4 0x1
-	#define B_RCLKDIV8 0x2
-	#define B_RCLKDIV16 0x3
+#define B_RCLKFreqSel	0x03
+#define B_RCLKDIV2 0x0
+#define B_RCLKDIV4 0x1
+#define B_RCLKDIV8 0x2
+#define B_RCLKDIV16 0x3
 
 #define REG_RX_OUT_CSC_CTRL 0x65 // REG_RX_065
-	//#define B_OUT_CSCSel0 0x01 // bit0
-	//#define B_OUT_CSCSel1 0x02 // bit1
-	//#define B_OUT_COLOR_DEPTH0 0x04 // bit2
-	//#define B_OUT_COLOR_DEPTH1 0x08 // bit3
-	//#define B_OUT_COLOR_MODE0 0x10 // bit4
-	//#define B_OUT_COLOR_MODE1 0x20 // bit5
-	#define B_SyncEmb 0x40 // bit6
-	#define B_BTA1004Fmt 0x80 // bit7
+//#define B_OUT_CSCSel0 0x01 // bit0
+//#define B_OUT_CSCSel1 0x02 // bit1
+//#define B_OUT_COLOR_DEPTH0 0x04 // bit2
+//#define B_OUT_COLOR_DEPTH1 0x08 // bit3
+//#define B_OUT_COLOR_MODE0 0x10 // bit4
+//#define B_OUT_COLOR_MODE1 0x20 // bit5
+#define B_SyncEmb 0x40 // bit6
+#define B_BTA1004Fmt 0x80 // bit7
 
-	#define M_OUTPUT_COLOR_MASK 0x30
-	#define B_OUTPUT_RGB24      0x00
-	#define B_OUTPUT_YUV422     0x10
-	#define B_OUTPUT_YUV444     0x20
+#define M_OUTPUT_COLOR_MASK 0x30
+#define B_OUTPUT_RGB24      0x00
+#define B_OUTPUT_YUV422     0x10
+#define B_OUTPUT_YUV444     0x20
 
-	#define M_CD_SEL_MASK   0x0C
-	#define B_CD_8BIT        0x00
-	#define B_CD_10BIT      0x04
-	#define B_CD_12BIT      0x08
+#define M_CD_SEL_MASK   0x0C
+#define B_CD_8BIT        0x00
+#define B_CD_10BIT      0x04
+#define B_CD_12BIT      0x08
 
-	#define M_CSC_SEL_MASK   0x03
-	#define B_CSC_BYPASS        0x00
-	#define B_CSC_RGB2YUV      0x02	// for Andrew modify to 10
-	#define B_CSC_YUV2RGB      0x03
+#define M_CSC_SEL_MASK   0x03
+#define B_CSC_BYPASS        0x00
+#define B_CSC_RGB2YUV      0x02	// for Andrew modify to 10
+#define B_CSC_YUV2RGB      0x03
 
 #define REG_RX_OUPT_CTRL3 0x66
-	#define B_3DFreSeq		0x80
-	#define B_EnHW3DFreSeq	0x40
-	#define B_3DFldPol		0x20
-	#define B_DE3DFrame	0x10
-	#define B_EnSyncOut        	0x08
-	#define B_YCSwap       	0x04
-	#define B_STBMode_1       	0x02
-	#define B_STBMode_0		0x01
+#define B_3DFreSeq		0x80
+#define B_EnHW3DFreSeq	0x40
+#define B_3DFldPol		0x20
+#define B_DE3DFrame	0x10
+#define B_EnSyncOut        	0x08
+#define B_YCSwap       	0x04
+#define B_STBMode_1       	0x02
+#define B_STBMode_0		0x01
 
 #define REG_RX_VIDEO_CTRL1 0x67 // REG_RX_067
-	#define B_RX_EN_UDFILTER 0x01 // bit0
-	#define B_RX_EN_DITHER 0x02 // bit1
-	#define B_RX_DNFREE_GO 0x04 // bit2
-	//#define B_3 0x08 // bit3
-	//#define B_4 0x10 // bit4
-	//#define B_5 0x20 // bit5
-	//#define B_6 0x40 // bit6
-	#define B_AutoCSCSel 0x80 // bit7
+#define B_RX_EN_UDFILTER 0x01 // bit0
+#define B_RX_EN_DITHER 0x02 // bit1
+#define B_RX_DNFREE_GO 0x04 // bit2
+//#define B_3 0x08 // bit3
+//#define B_4 0x10 // bit4
+//#define B_5 0x20 // bit5
+//#define B_6 0x40 // bit6
+#define B_AutoCSCSel 0x80 // bit7
 
 #define REG_RX_IN_CSC_CTRL 0x71 // REG_RX_071
-	//#define B_IN_ColMod_Set0 0x01 // bit0
-	//#define B_IN_ColMod_Set1 0x02 // bit1
-	#define B_IN_FORCE_COLOR_MODE 0x04 // bit2
-	//#define B_3 0x08 // bit3
-	//#define B_4 0x10 // bit4
-	//#define B_5 0x20 // bit5
-	//#define B_6 0x40 // bit6
-	//#define B_7 0x80 // bit7
+//#define B_IN_ColMod_Set0 0x01 // bit0
+//#define B_IN_ColMod_Set1 0x02 // bit1
+#define B_IN_FORCE_COLOR_MODE 0x04 // bit2
+//#define B_3 0x08 // bit3
+//#define B_4 0x10 // bit4
+//#define B_5 0x20 // bit5
+//#define B_6 0x40 // bit6
+//#define B_7 0x80 // bit7
 
-	#define M_INPUT_COLOR_MASK 0x03
-	#define B_INPUT_RGB24      0x00
-	#define B_INPUT_YUV422     0x01
-	#define B_INPUT_YUV444     0x02
+#define M_INPUT_COLOR_MASK 0x03
+#define B_INPUT_RGB24      0x00
+#define B_INPUT_YUV422     0x01
+#define B_INPUT_YUV444     0x02
 
 //#define REG_RX_074 0x74 // REG_RX_074
-	#define B_I2SCEn 0x80 // bit7
-	#define B_Force_FS 0x40 // bit6
-	#define B_Dis_False_DE 0x20 // bit5
-	#define B_Aud_Info_Force 0x10 // bit4
-	#define B_AVMute_Value 0x08 // bit3
-	#define B_Force_AVMute 0x04 // bit2
-	#define B_Dien 0x02 // bit1
-	#define B_Dis_sdm 0x01 // bit0
+#define B_I2SCEn 0x80 // bit7
+#define B_Force_FS 0x40 // bit6
+#define B_Dis_False_DE 0x20 // bit5
+#define B_Aud_Info_Force 0x10 // bit4
+#define B_AVMute_Value 0x08 // bit3
+#define B_Force_AVMute 0x04 // bit2
+#define B_Dien 0x02 // bit1
+#define B_Dis_sdm 0x01 // bit0
 
 //#define REG_RX_07A 0x7A // REG_RX_07A
-	#define B_CTS_RES 0x70 // bit6~4
+#define B_CTS_RES 0x70 // bit6~4
 
 //#define REG_RX_07B 0x7B // REG_RX_07B
-	#define M_FS 0x0F
-	#define B_192K 	0x0E
-	#define B_176P4K 0x0C
-	#define B_96K 	0x0A
-	#define B_88P2K 	0x08
-	#define B_48K 	0x02
-	#define B_44P1K 	0x00
-	#define B_32K 	0x03
+#define M_FS 0x0F
+#define B_192K 	0x0E
+#define B_176P4K 0x0C
+#define B_96K 	0x0A
+#define B_88P2K 	0x08
+#define B_48K 	0x02
+#define B_44P1K 	0x00
+#define B_32K 	0x03
 
 #define REG_RX_HWMuteRate 0x7C
 
 #define REG_RX_HWMuteCtrl 0x7D
-	#define B_ARAM_BIST_EN 0x80 // bit7
-	#define B_HWForceMute 0x40 // bit6
-	#define B_HWAudMuteClrMode 0x20 // bit5
-	#define B_HWMuteClr 0x10 // bit4
-	#define B_HWMuteEn 0x08 // bit3
-	#define B_HWMuteRate 0x07 // bit0
+#define B_ARAM_BIST_EN 0x80 // bit7
+#define B_HWForceMute 0x40 // bit6
+#define B_HWAudMuteClrMode 0x20 // bit5
+#define B_HWMuteClr 0x10 // bit4
+#define B_HWMuteEn 0x08 // bit3
+#define B_HWMuteRate 0x07 // bit0
 
 //#define REG_RX_07E 0x7E // REG_RX_07E
-	#define B_BiPhaseMode 0x80 // bit7
-	#define B_HBRSel 0x40 // bit6
-	#define B_I2SOut_Fmt 0x20 // bit5
-	#define B_Force_I2SOut 0x10 // bit4
+#define B_BiPhaseMode 0x80 // bit7
+#define B_HBRSel 0x40 // bit6
+#define B_I2SOut_Fmt 0x20 // bit5
+#define B_Force_I2SOut 0x10 // bit4
 
 #define REG_RX_PIXCLK_SPEED 0x9A // REG_RX_09A
 
 //#define REG_RX_0A8 0xA8 // REG_RX_0A8
-	//#define B_7 0x80 // bit7
-	//#define B_6 0x40 // bit6
-	//#define B_5 0x20 // bit5
-	#define B_P1_AVMUTE 0x10 // bit4
-	//#define B_3 0x08 // bit3
-	//#define B_2 0x04 // bit2
-	//#define B_1 0x02 // bit1
-	#define B_P0_AVMUTE 0x01 // bit0
+//#define B_7 0x80 // bit7
+//#define B_6 0x40 // bit6
+//#define B_5 0x20 // bit5
+#define B_P1_AVMUTE 0x10 // bit4
+//#define B_3 0x08 // bit3
+//#define B_2 0x04 // bit2
+//#define B_1 0x02 // bit1
+#define B_P0_AVMUTE 0x01 // bit0
 
 #define REG_RX_AUDIO_CH_STAT 0xAA
-    #define B_AUDIO_ON 0x80
-    #define B_HBRAUDIO 0x40
-    #define B_DSDAUDIO 0x20
-    #define B_AUDIO_LAYOUT 0x10
-    #define M_AUDIO_CH         0xF
-    #define B_AUDIO_SRC_VALID_3 0x08
-    #define B_AUDIO_SRC_VALID_2 0x04
-    #define B_AUDIO_SRC_VALID_1 0x02
-    #define B_AUDIO_SRC_VALID_0 0x01
+#define B_AUDIO_ON 0x80
+#define B_HBRAUDIO 0x40
+#define B_DSDAUDIO 0x20
+#define B_AUDIO_LAYOUT 0x10
+#define M_AUDIO_CH         0xF
+#define B_AUDIO_SRC_VALID_3 0x08
+#define B_AUDIO_SRC_VALID_2 0x04
+#define B_AUDIO_SRC_VALID_1 0x02
+#define B_AUDIO_SRC_VALID_0 0x01
 
 #define REG_RX_AUD_CHSTAT0 0xAB
-	#define B_AUD_NLPCM 0x01
-	#define B_NLPCM 0x01
-	#define B_SW_COPYRIGHT_ASSERT 0x02
+#define B_AUD_NLPCM 0x01
+#define B_NLPCM 0x01
+#define B_SW_COPYRIGHT_ASSERT 0x02
 
 #define REG_RX_AUD_CHSTAT1 0xAC
 
 #define REG_RX_AUD_CHSTAT2 0xAD
-	#define M_CH_NUM    0xF0
-	#define O_CH_NUM    4
-	#define M_SRC_NUM   0x0F
-	#define O_SRC_NUM   0
+#define M_CH_NUM    0xF0
+#define O_CH_NUM    4
+#define M_SRC_NUM   0x0F
+#define O_SRC_NUM   0
 
 #define REG_RX_AUD_CHSTAT3 0xAE
-	#define M_FS              0x0F /* mask - sample frequency */
-	#define B_FS_44100        (0<<0)  /* 44.1kHz */
-	#define B_FS_NOTID        (1<<0)  /* non indicated */
-	#define B_FS_48000        (2<<0)  /* 48kHz */
-	#define B_FS_32000        (3<<0)  /* 32kHz */
-	#define B_FS_22050        (4<<0)  /* 22.05kHz */
-	#define B_FS_24000        (6<<0)  /* 24kHz */
-	#define B_FS_88200        (8<<0)  /* 88.2kHz */
-	#define B_FS_768000       (9<<0)  /* 768kHz */
-	#define B_FS_96000        (10<<0) /* 96kHz */
-	#define B_FS_176400       (12<<0) /* 176.4kHz */
-	#define B_FS_192000       (14<<0) /* 192kHz */
+#define M_FS              0x0F /* mask - sample frequency */
+#define B_FS_44100        (0<<0)  /* 44.1kHz */
+#define B_FS_NOTID        (1<<0)  /* non indicated */
+#define B_FS_48000        (2<<0)  /* 48kHz */
+#define B_FS_32000        (3<<0)  /* 32kHz */
+#define B_FS_22050        (4<<0)  /* 22.05kHz */
+#define B_FS_24000        (6<<0)  /* 24kHz */
+#define B_FS_88200        (8<<0)  /* 88.2kHz */
+#define B_FS_768000       (9<<0)  /* 768kHz */
+#define B_FS_96000        (10<<0) /* 96kHz */
+#define B_FS_176400       (12<<0) /* 176.4kHz */
+#define B_FS_192000       (14<<0) /* 192kHz */
 
 #define REG_RX_CSC_YOFF 0x70 // REG_RX_170
 #define REG_RX_CSC_COFF 0x71 // REG_RX_171
@@ -1450,60 +1450,60 @@
 #define REG_RX_AVI_LENGTH 0x12 // REG_RX_212
 #define REG_RX_AVI_VER 0x13 // REG_RX_213
 #define REG_RX_AVI_DB0 0x14 // REG_RX_214
-	#define O_AVI_COLOR_MODE 5
-	#define M_AVI_COLOR_MASK   3
-	#define B_AVI_COLOR_RGB24  0
-	#define B_AVI_COLOR_YUV422 1
-	#define B_AVI_COLOR_YUV444 2
+#define O_AVI_COLOR_MODE 5
+#define M_AVI_COLOR_MASK   3
+#define B_AVI_COLOR_RGB24  0
+#define B_AVI_COLOR_YUV422 1
+#define B_AVI_COLOR_YUV444 2
 
-	#define B_AVI_PRESENT (1<<4)
+#define B_AVI_PRESENT (1<<4)
 
-	#define O_AVI_BAR_INFO 2
-	#define M_AVI_BAR_INFO_MASK 3
-	#define B_AVI_BAR_NOT_VALID 0
-	#define B_AVI_BAR_VINFO_VALID 1
-	#define B_AVI_BAR_HINFO_VALID 2
-	#define B_AVI_BAR_VHINFO_VALID 3
+#define O_AVI_BAR_INFO 2
+#define M_AVI_BAR_INFO_MASK 3
+#define B_AVI_BAR_NOT_VALID 0
+#define B_AVI_BAR_VINFO_VALID 1
+#define B_AVI_BAR_HINFO_VALID 2
+#define B_AVI_BAR_VHINFO_VALID 3
 
-	#define O_AVI_SCAN_INFO 0
-	#define M_AVI_SCAN_INFO_MASK 3
-	#define M_AVI_SCAN_NODATA    0
-	#define M_AVI_SCAN_OVER_SCAN 1
-	#define M_AVI_SCAN_UNDER_SCAN 2
+#define O_AVI_SCAN_INFO 0
+#define M_AVI_SCAN_INFO_MASK 3
+#define M_AVI_SCAN_NODATA    0
+#define M_AVI_SCAN_OVER_SCAN 1
+#define M_AVI_SCAN_UNDER_SCAN 2
 #define REG_RX_AVI_DB1 0x15 // REG_RX_215
-	// D[7:6] C1C0 Colorimetry
-	#define O_AVI_CLRMET 6
-	#define M_AVI_CLRMET_MASK 3
-	#define B_AVI_CLRMET_NODATA 0
-	#define B_AVI_CLRMET_ITU601  1
-	#define B_AVI_CLRMET_ITU709  2
-	#define B_AVI_CLRMET_Extend  3	// _SupportXVYcc_ --> indicated in bits EC0~EC2
-	// D[5:4] M1M0 Picture Aspect Ratio
-	#define O_AVI_PIC_ASRATIO 4
-	#define M_AVI_PIC_ASRATIO_MASK 3
-	#define B_AVI_PIC_ASRATIO_NODATA 0
-	#define B_AVI_PIC_ASRATIO_4_3    1
-	#define B_AVI_PIC_ASRATIO_16_9   2
-	// D[3:0] R3R2R1R0 Active Format Aspect Ratio
-	#define O_AVI_FMT_ASRATIO 0
-	#define M_AVI_FMT_ASRATIO_MASK  0xF
-	#define M_AVI_FMT_ASRATIO_EQPIC 0x8
-	#define M_AVI_FMT_ASRATIO_4_3 0x9
-	#define M_AVI_FMT_ASRATIO_16_9 0xA
-	#define M_AVI_FMT_ASRATIO_14_9 0xB
+// D[7:6] C1C0 Colorimetry
+#define O_AVI_CLRMET 6
+#define M_AVI_CLRMET_MASK 3
+#define B_AVI_CLRMET_NODATA 0
+#define B_AVI_CLRMET_ITU601  1
+#define B_AVI_CLRMET_ITU709  2
+#define B_AVI_CLRMET_Extend  3	// _SupportXVYcc_ --> indicated in bits EC0~EC2
+// D[5:4] M1M0 Picture Aspect Ratio
+#define O_AVI_PIC_ASRATIO 4
+#define M_AVI_PIC_ASRATIO_MASK 3
+#define B_AVI_PIC_ASRATIO_NODATA 0
+#define B_AVI_PIC_ASRATIO_4_3    1
+#define B_AVI_PIC_ASRATIO_16_9   2
+// D[3:0] R3R2R1R0 Active Format Aspect Ratio
+#define O_AVI_FMT_ASRATIO 0
+#define M_AVI_FMT_ASRATIO_MASK  0xF
+#define M_AVI_FMT_ASRATIO_EQPIC 0x8
+#define M_AVI_FMT_ASRATIO_4_3 0x9
+#define M_AVI_FMT_ASRATIO_16_9 0xA
+#define M_AVI_FMT_ASRATIO_14_9 0xB
 #define REG_RX_AVI_DB2 0x16 // REG_RX_216
-	#define O_AVI_NUNI_SCALE 0
-	#define M_AVI_NUNI_SCALE_MASK 3
-	#define B_AVI_NUNI_SCALE_NODATA 0
-	#define B_AVI_NUNI_SCALE_HORZ 1
-	#define B_AVI_NUNI_SCALE_VERT 2
-	#define B_AVI_NUNI_SCALE_HORZVERT 3
+#define O_AVI_NUNI_SCALE 0
+#define M_AVI_NUNI_SCALE_MASK 3
+#define B_AVI_NUNI_SCALE_NODATA 0
+#define B_AVI_NUNI_SCALE_HORZ 1
+#define B_AVI_NUNI_SCALE_VERT 2
+#define B_AVI_NUNI_SCALE_HORZVERT 3
 #define REG_RX_AVI_DB3 0x17 // REG_RX_217
-	#define O_AVI_VIDCODE 0
-	#define O_AVI_VIDCODE_MASK 0x7f
+#define O_AVI_VIDCODE 0
+#define O_AVI_VIDCODE_MASK 0x7f
 #define REG_RX_AVI_DB4 0x18 // REG_RX_218
-	#define O_AVI_PIXREPT 0
-	#define M_AVI_PIXREPT_MASK 0xF
+#define O_AVI_PIXREPT 0
+#define M_AVI_PIXREPT_MASK 0xF
 #define REG_RX_AVI_DB5 0x19 // REG_RX_219
 #define REG_RX_AVI_DB6 0x1A // REG_RX_21A
 #define REG_RX_AVI_DB7 0x1B // REG_RX_21B
diff --git a/src/drivers/px4fmu/fmu.cpp b/src/drivers/px4fmu/fmu.cpp
index 77b65445a30b90b2730ff81a52336e7c3fd80eda..8905e34854164432abc9655e5c0db3ed078fbb7e 100644
--- a/src/drivers/px4fmu/fmu.cpp
+++ b/src/drivers/px4fmu/fmu.cpp
@@ -517,26 +517,26 @@ PX4FMU::init()
 	/* initialize PWM limit lib */
 	pwm_limit_init(&_pwm_limit);
 
-	#ifdef RC_SERIAL_PORT
-
-		#ifdef RF_RADIO_POWER_CONTROL
-			// power radio on
-			RF_RADIO_POWER_CONTROL(true);
-		#endif
-			_vehicle_cmd_sub = orb_subscribe(ORB_ID(vehicle_command));
-
-		#ifndef COOLFLY_F1
-			// dsm_init sets some file static variables and returns a file descriptor
-			_rcs_fd = dsm_init(RC_SERIAL_PORT);
-			// assume SBUS input
-			sbus_config(_rcs_fd, false);
-		#endif
-
-		#ifdef GPIO_PPM_IN
-			// disable CPPM input by mapping it away from the timer capture input
-			px4_arch_unconfiggpio(GPIO_PPM_IN);
-		#endif
-	#endif
+#ifdef RC_SERIAL_PORT
+
+#ifdef RF_RADIO_POWER_CONTROL
+	// power radio on
+	RF_RADIO_POWER_CONTROL(true);
+#endif
+	_vehicle_cmd_sub = orb_subscribe(ORB_ID(vehicle_command));
+
+#ifndef COOLFLY_F1
+	// dsm_init sets some file static variables and returns a file descriptor
+	_rcs_fd = dsm_init(RC_SERIAL_PORT);
+	// assume SBUS input
+	sbus_config(_rcs_fd, false);
+#endif
+
+#ifdef GPIO_PPM_IN
+	// disable CPPM input by mapping it away from the timer capture input
+	px4_arch_unconfiggpio(GPIO_PPM_IN);
+#endif
+#endif
 	// Getting initial parameter values
 	update_params();
 
@@ -809,7 +809,7 @@ PX4FMU::set_mode(Mode mode)
 int
 PX4FMU::set_pwm_rate(uint32_t rate_map, unsigned default_rate, unsigned alt_rate)
 {
-    // PX4_INFO("set_pwm_rate %x %u %u --------------------------\r\n", rate_map, default_rate, alt_rate);
+	// PX4_INFO("set_pwm_rate %x %u %u --------------------------\r\n", rate_map, default_rate, alt_rate);
 
 	for (unsigned pass = 0; pass < 2; pass++) {
 
@@ -831,7 +831,7 @@ PX4FMU::set_pwm_rate(uint32_t rate_map, unsigned default_rate, unsigned alt_rate
 
 			// get the channel mask for this rate group
 			uint32_t mask = up_pwm_servo_get_rate_group(group);
-		    // PX4_INFO("mask = 0x%08x-------------------\r\n",mask);
+			// PX4_INFO("mask = 0x%08x-------------------\r\n",mask);
 
 			if (mask == 0) {
 				continue;
@@ -1216,8 +1216,8 @@ PX4FMU::run()
 
 #include <chip/ar_config.h>
 
-static void retrieveRcMavlinkMsgFromSram(uint8_t *buffer, int *length) 
-{	
+static void retrieveRcMavlinkMsgFromSram(uint8_t *buffer, int *length)
+{
 	char *wr_pos;
 	char *rd_pos;
 	char *tail;
@@ -1228,37 +1228,32 @@ static void retrieveRcMavlinkMsgFromSram(uint8_t *buffer, int *length)
 
 	// uint16_t length;
 
-	msgBuffer = (STRU_SramBuffer*)SRAM_MAVLINK_RC_MSG_ST_ADDR;
+	msgBuffer = (STRU_SramBuffer *)SRAM_MAVLINK_RC_MSG_ST_ADDR;
 
 	wr_pos = (char *)msgBuffer->header.buf_wr_pos;
 	rd_pos = (char *)msgBuffer->header.buf_rd_pos;
 	head = (char *)msgBuffer->buf;
-    tail = (char *)SRAM_MAVLINK_RC_MSG_END_ADDR;
+	tail = (char *)SRAM_MAVLINK_RC_MSG_END_ADDR;
 
 	// length = 0;
 
-	if (wr_pos >= rd_pos) 	
-	{
+	if (wr_pos >= rd_pos) {
 		*length = wr_pos - rd_pos;
-	} 
-	else 
-	{
+
+	} else {
 		*length = wr_pos + (tail - head) - rd_pos;
 	}
 
-	for (uint16_t i = 0; i < *length; i++)
-	{
+	for (uint16_t i = 0; i < *length; i++) {
 		buffer[i] = *rd_pos;
 
-		if (rd_pos >= tail)
-        {
-            rd_pos = head;
-        } 
-        else
-        {
-            rd_pos++;
-        } 
-	}	
+		if (rd_pos >= tail) {
+			rd_pos = head;
+
+		} else {
+			rd_pos++;
+		}
+	}
 
 	msgBuffer->header.buf_rd_pos = (uint32_t)rd_pos;
 
@@ -1644,8 +1639,9 @@ PX4FMU::cycle()
 
 			} else if (_rc_scan_locked
 				   || _cycle_timestamp - _rc_scan_begin < rc_scan_max) {
-					
+
 				PX4_INFO("RC_SCAN_SBUS Bytes = %d", newBytes);
+
 				// parse new data
 				if (newBytes > 0) {
 					rc_updated = sbus_parse(_cycle_timestamp, &_rcs_buf[0], newBytes, &raw_rc_values[0], &raw_rc_count, &sbus_failsafe,
@@ -1655,7 +1651,7 @@ PX4FMU::cycle()
 						// we have a new SBUS frame. Publish it.
 						_rc_in.input_source = input_rc_s::RC_INPUT_SOURCE_PX4FMU_SBUS;
 						fill_rc_in(raw_rc_count, raw_rc_values, _cycle_timestamp,
- 							   sbus_frame_drop, sbus_failsafe, frame_drops, 100);
+							   sbus_frame_drop, sbus_failsafe, frame_drops, 100);
 						_rc_scan_locked = true;
 					}
 				}
@@ -1820,7 +1816,8 @@ PX4FMU::cycle()
 
 #endif  // HRT_PPM_CHANNEL
 
-			break;	
+			break;
+
 		case RC_SCAN_COOLFLY_SBUS:
 #ifdef COOLFLY_F1
 			if (_rc_scan_begin == 0) {
@@ -1828,8 +1825,8 @@ PX4FMU::cycle()
 				rc_io_invert(true);
 
 			} else if (_rc_scan_locked
-				|| _cycle_timestamp - _rc_scan_begin < rc_scan_max) {
-					
+				   || _cycle_timestamp - _rc_scan_begin < rc_scan_max) {
+
 				retrieveRcMavlinkMsgFromSram(&_rcs_buf[0], &newBytes);
 
 				// parse new data
@@ -1841,7 +1838,7 @@ PX4FMU::cycle()
 						// we have a new SBUS frame. Publish it.
 						_rc_in.input_source = input_rc_s::RC_INPUT_SOURCE_PX4FMU_SBUS;
 						fill_rc_in(raw_rc_count, raw_rc_values, _cycle_timestamp,
-							sbus_frame_drop, sbus_failsafe, frame_drops, 100);
+							   sbus_frame_drop, sbus_failsafe, frame_drops, 100);
 						_rc_scan_locked = true;
 					}
 				}
@@ -1849,9 +1846,10 @@ PX4FMU::cycle()
 			} else {
 				set_rc_scan_state(RC_SCAN_COOLFLY_SBUS);
 			}
+
 #else
 			set_rc_scan_state(RC_SCAN_SBUS);
-	
+
 
 #endif
 
@@ -1896,7 +1894,7 @@ PX4FMU::cycle()
 		} else {
 			if (should_exit()) {
 				exit_and_cleanup();
- 
+
 			} else {
 				/* schedule next cycle */
 				work_queue(HPWORK, &_work, (worker_t)&PX4FMU::cycle_trampoline, this, USEC2TICK(SCHEDULE_INTERVAL));
diff --git a/src/drivers/rgbled_ncp5623c/rgbled_ncp5623c.cpp b/src/drivers/rgbled_ncp5623c/rgbled_ncp5623c.cpp
index c6ce07da2c2a1f663a8443a9280c068d53fe0342..22b887b37adccd314e37119be7ea126a1e08f04d 100755
--- a/src/drivers/rgbled_ncp5623c/rgbled_ncp5623c.cpp
+++ b/src/drivers/rgbled_ncp5623c/rgbled_ncp5623c.cpp
@@ -230,7 +230,7 @@ RGBLED_NPC5623C::led()
 			parameter_update_s pupdate;
 			orb_copy(ORB_ID(parameter_update), _param_sub, &pupdate);
 			update_params();
-			// Immediately update to change brightness	
+			// Immediately update to change brightness
 			send_led_rgb();
 		}
 	}
diff --git a/src/lib/FlightTasks/tasks/FlightTaskManualAltitudeSmooth.hpp b/src/lib/FlightTasks/tasks/FlightTaskManualAltitudeSmooth.hpp
index 42c3d26c0ed89e693a32695fc3fb74067618e108..9f0b07f96732933d96fa75ce2e8bfb95ae1c9685 100644
--- a/src/lib/FlightTasks/tasks/FlightTaskManualAltitudeSmooth.hpp
+++ b/src/lib/FlightTasks/tasks/FlightTaskManualAltitudeSmooth.hpp
@@ -45,7 +45,7 @@ class FlightTaskManualAltitudeSmooth : public FlightTaskManualAltitude
 {
 public:
 	_EXT_ITCM FlightTaskManualAltitudeSmooth();
-	 virtual ~FlightTaskManualAltitudeSmooth() = default;
+	virtual ~FlightTaskManualAltitudeSmooth() = default;
 
 protected:
 	_EXT_ITCM virtual void _updateSetpoints() override;
diff --git a/src/lib/FlightTasks/tasks/Utility/ManualSmoothingXY.hpp b/src/lib/FlightTasks/tasks/Utility/ManualSmoothingXY.hpp
index 2a6503ca534b0a9c80ea1896eb8720a0226fe44a..b3a7b2907079633c5aa414b3f8d87e087d44a4da 100644
--- a/src/lib/FlightTasks/tasks/Utility/ManualSmoothingXY.hpp
+++ b/src/lib/FlightTasks/tasks/Utility/ManualSmoothingXY.hpp
@@ -55,7 +55,7 @@ public:
 	 * @param dt: time delta in seconds
 	 */
 	_EXT_ITCM void smoothVelocity(matrix::Vector2f &vel_sp, const matrix::Vector2f &vel,  const float &yaw,
-			    const float &yawrate_sp, const float dt);
+				      const float &yawrate_sp, const float dt);
 
 	/* User intention: brake or acceleration */
 	enum class Intention {
@@ -79,11 +79,12 @@ public:
 
 private:
 	_EXT_ITCM void _updateAcceleration(matrix::Vector2f &vel_sp, const matrix::Vector2f &vel, const float &yaw,
-				 const float &yawrate_sp, const float dt);
+					   const float &yawrate_sp, const float dt);
 	_EXT_ITCM Intention _getIntention(const matrix::Vector2f &vel_sp, const matrix::Vector2f &vel, const float &yaw,
-				const float &yawrate_sp);
-	_EXT_ITCM void _getStateAcceleration(const matrix::Vector2f &vel_sp, const matrix::Vector2f &vel, const Intention &intention,
-				   const float dt);
+					  const float &yawrate_sp);
+	_EXT_ITCM void _getStateAcceleration(const matrix::Vector2f &vel_sp, const matrix::Vector2f &vel,
+					     const Intention &intention,
+					     const float dt);
 	_EXT_ITCM void _velocitySlewRate(matrix::Vector2f &vel_sp, const float dt);
 	_EXT_ITCM matrix::Vector2f _getWorldToHeadingFrame(const matrix::Vector2f &vec, const float &yaw);
 	_EXT_ITCM matrix::Vector2f _getHeadingToWorldFrame(const matrix::Vector2f &vec, const float &yaw);
diff --git a/src/lib/battery/battery.h b/src/lib/battery/battery.h
index da09ee0a8a4d368024d0de9307140d37cf72643a..fde10f7fcf8ff77901376c0186d26a3e272b0c2c 100644
--- a/src/lib/battery/battery.h
+++ b/src/lib/battery/battery.h
@@ -82,9 +82,9 @@ public:
 	 * @param throttle_normalized: throttle from 0 to 1
 	 */
 	_EXT_ITCM void updateBatteryStatus(hrt_abstime timestamp, float voltage_v, float current_a,
-				 bool connected, bool selected_source, int priority,
-				 float throttle_normalized,
-				 bool armed, battery_status_s *status);
+					   bool connected, bool selected_source, int priority,
+					   float throttle_normalized,
+					   bool armed, battery_status_s *status);
 
 private:
 	_EXT_ITCM void filterVoltage(float voltage_v);
diff --git a/src/lib/drivers/device/nuttx/I2C.cpp b/src/lib/drivers/device/nuttx/I2C.cpp
index 051927655ea15d7ebe9a21536c42ea16573b8267..96e6355d85e3e780926ac07ed4c86f2db1cf9ff8 100644
--- a/src/lib/drivers/device/nuttx/I2C.cpp
+++ b/src/lib/drivers/device/nuttx/I2C.cpp
@@ -141,7 +141,7 @@ I2C::init()
 
 	if (ret != OK) {
 		DEVICE_DEBUG("probe failed");
-		
+
 		goto out;
 	}
 
@@ -174,7 +174,7 @@ I2C::transfer(const uint8_t *send, unsigned send_len, uint8_t *recv, unsigned re
 	unsigned msgs;
 	int ret = PX4_ERROR;
 	unsigned retry_count = 0;
-		
+
 	if (_dev == nullptr) {
 		PX4_ERR("I2C device not opened");
 		return 1;
diff --git a/src/lib/drivers/device/nuttx/SPI.cpp b/src/lib/drivers/device/nuttx/SPI.cpp
index 13632b3e537ddd5b5ebee0b6a55f217879d2a8ad..292e7f0960edc14dd393d86159fdf89a31c257f4 100644
--- a/src/lib/drivers/device/nuttx/SPI.cpp
+++ b/src/lib/drivers/device/nuttx/SPI.cpp
@@ -98,6 +98,7 @@ SPI::init()
 	if (_dev == nullptr) {
 		_dev = px4_spibus_initialize(get_device_bus());
 	}
+
 	if (_dev == nullptr) {
 		DEVICE_DEBUG("failed to init SPI");
 		ret = -ENOENT;
diff --git a/src/lib/parameters/flashparams/flashfs.c b/src/lib/parameters/flashparams/flashfs.c
index 7016f9c1544f182cf902c42249a8d61a5626d18f..7c07d40f91e38b042f62137d7938fc7ab1bcb953 100644
--- a/src/lib/parameters/flashparams/flashfs.c
+++ b/src/lib/parameters/flashparams/flashfs.c
@@ -182,7 +182,7 @@ _EXT_ITCM static inline int blank_flash(uint32_t *pf)
  ****************************************************************************/
 
 _EXT_ITCM static bool blank_check(flash_entry_header_t *pf,
-			size_t new_size)
+				  size_t new_size)
 {
 	bool rv = true;
 	uint32_t *pm = (uint32_t *) pf;
@@ -738,7 +738,7 @@ _EXT_ITCM static sector_descriptor_t *check_free_space_in_sector(flash_entry_hea
  ****************************************************************************/
 
 _EXT_ITCM int parameter_flashfs_read(flash_file_token_t token, uint8_t **buffer, size_t
-			   *buf_size)
+				     *buf_size)
 {
 	int rv = -ENXIO;
 
diff --git a/src/lib/pid/pid.c b/src/lib/pid/pid.c
index 25e8347ed8bdd5217a35a7abf17cd02490131fbc..17e25ae01d4dedcb7fb4ea18fd5277ad06ec83d4 100644
--- a/src/lib/pid/pid.c
+++ b/src/lib/pid/pid.c
@@ -67,7 +67,8 @@ _EXT_DTCM_EKF2 __EXPORT void pid_init(PID_t *pid, pid_mode_t mode, float dt_min)
 	pid->last_output = 0.0f;
 }
 
-_EXT_DTCM_EKF2 __EXPORT int pid_set_parameters(PID_t *pid, float kp, float ki, float kd, float integral_limit, float output_limit)
+_EXT_DTCM_EKF2 __EXPORT int pid_set_parameters(PID_t *pid, float kp, float ki, float kd, float integral_limit,
+		float output_limit)
 {
 	int ret = 0;
 
diff --git a/src/lib/tunes/tunes.h b/src/lib/tunes/tunes.h
index ebd7330086edf19cf319fbbe9bc54e93e1d1f579..7368123bfe181943d8f58b7c59d5105b41dc973a 100644
--- a/src/lib/tunes/tunes.h
+++ b/src/lib/tunes/tunes.h
@@ -114,7 +114,7 @@ public:
 	 * @return           -1 for error, 0 for play one tone and 1 for continue a sequence
 	 */
 	_EXT_ITCM int get_next_tune(unsigned &frequency, unsigned &duration, unsigned &silence,
-			  uint8_t &strength);
+				    uint8_t &strength);
 
 	/**
 	 *  Get the number of default tunes. This is useful for when a tune is
diff --git a/src/modules/land_detector/RoverLandDetector.h b/src/modules/land_detector/RoverLandDetector.h
index 139d88b2386f638560824e4430c43832dd3b8356..0486a85566021701e6ba7be7f2b6dfc25dbb9834 100644
--- a/src/modules/land_detector/RoverLandDetector.h
+++ b/src/modules/land_detector/RoverLandDetector.h
@@ -51,7 +51,7 @@ namespace land_detector
 class RoverLandDetector : public LandDetector
 {
 public:
-	 RoverLandDetector() = default;
+	RoverLandDetector() = default;
 
 protected:
 	_EXT_ITCM virtual void _initialize_topics() override;
diff --git a/src/modules/logger/watchdog.cpp b/src/modules/logger/watchdog.cpp
index 71fc9db28971637e22fad25880d86aa9c7063911..df496f249abdbf4f5373cae83cb6f41e114a95b6 100644
--- a/src/modules/logger/watchdog.cpp
+++ b/src/modules/logger/watchdog.cpp
@@ -127,7 +127,8 @@ _EXT_ITCM bool watchdog_update(watchdog_data_t &watchdog_data)
 
 }
 
-_EXT_ITCM void watchdog_initialize(const pid_t pid_logger_main, const pthread_t writer_thread, watchdog_data_t &watchdog_data)
+_EXT_ITCM void watchdog_initialize(const pid_t pid_logger_main, const pthread_t writer_thread,
+				   watchdog_data_t &watchdog_data)
 {
 #ifdef __PX4_NUTTX
 
diff --git a/src/modules/mavlink/mavlink_bridge_header.h b/src/modules/mavlink/mavlink_bridge_header.h
index 1acf4214cb6fc9ed09d6696a0d4428a79d738572..50785848a579375211499c8e342bb544f3e03db2 100644
--- a/src/modules/mavlink/mavlink_bridge_header.h
+++ b/src/modules/mavlink/mavlink_bridge_header.h
@@ -56,7 +56,7 @@
 #define MAVLINK_GET_CHANNEL_STATUS mavlink_get_channel_status
 
 
-/** sram address for  mavlink inter core */ 
+/** sram address for  mavlink inter core */
 #define SRAM_BASE_ADDRESS                             0x21000000     /* start address of SRAM */
 #define SRAM_SIZE                                     (60 * 1024)    /* size of SRAM */
 
@@ -67,11 +67,11 @@
 #define SRAM_MAVLINK_INTERCORE_WR_HEADER_ST_ADDR        SRAM_MAVLINK_INTERCORE_BUFFER_ST_ADDR
 #define SRAM_MAVLINK_INTERCORE_WR_HEADER_SIZE           100
 
-// 2k for write buffer 
+// 2k for write buffer
 #define SRAM_MAVLINK_INTERCORE_WR_BUFFER                (SRAM_MAVLINK_INTERCORE_WR_HEADER_ST_ADDR + SRAM_MAVLINK_INTERCORE_WR_HEADER_SIZE)
 #define SRAM_MAVLINK_INTERCORE_WR_SIZE                  0x800
 
-// 100 for read header 
+// 100 for read header
 #define SRAM_MAVLINK_INTERCORE_RD_HEADER_ST_ADDR        (SRAM_MAVLINK_INTERCORE_WR_BUFFER + SRAM_MAVLINK_INTERCORE_WR_SIZE)
 #define SRAM_MAVLINK_INTERCORE_RD_HEADER_SIZE           100
 
@@ -82,11 +82,10 @@
 #define MAVLINK_SERIAL_NAME "/dev/ttyS20"
 
 
-typedef struct
-{
-    volatile uint16_t buf_wr_pos;
-    volatile uint16_t buf_rd_pos;
-    volatile uint8_t in_use;
+typedef struct {
+	volatile uint16_t buf_wr_pos;
+	volatile uint16_t buf_rd_pos;
+	volatile uint8_t in_use;
 
 } STRU_MavlinkInterCoreHeader;
 
diff --git a/src/modules/mavlink/mavlink_main.cpp b/src/modules/mavlink/mavlink_main.cpp
index eb81423c116aa4daf167ad20ac9bfb17c5ffac05..4ef6ceb8dd1d1139bba13e5e82bf98104c5a39c8 100644
--- a/src/modules/mavlink/mavlink_main.cpp
+++ b/src/modules/mavlink/mavlink_main.cpp
@@ -890,13 +890,11 @@ Mavlink::set_hil_enabled(bool hil_enabled)
 
 bool Mavlink::isUserCustomUart()
 {
-	if (std::strcmp(_device_name, MAVLINK_SERIAL_NAME) == 0)
-	{
+	if (std::strcmp(_device_name, MAVLINK_SERIAL_NAME) == 0) {
 		return true;
-	}
-	else 
-	{
-		return false; 
+
+	} else {
+		return false;
 	}
 }
 
@@ -904,10 +902,10 @@ bool Mavlink::isUserCustomUart()
 unsigned
 Mavlink::get_free_tx_buf()
 {
-	if (isUserCustomUart())
-	{
+	if (isUserCustomUart()) {
 		return 1500;
 	}
+
 	/*
 	 * Check if the OS buffer is full and disable HW
 	 * flow control if it continues to be full
@@ -1014,14 +1012,13 @@ void
 Mavlink::send_bytes(const uint8_t *buf, unsigned packet_len)
 {
 	size_t ret = -1;
+
 	/* send message to UART */
-	if (isUserCustomUart())
-	{
+	if (isUserCustomUart()) {
 		volatile STRU_MavlinkInterCoreHeader *header = (STRU_MavlinkInterCoreHeader *)SRAM_MAVLINK_INTERCORE_WR_HEADER_ST_ADDR;
 		volatile uint8_t *wr_buffer = (uint8_t *)SRAM_MAVLINK_INTERCORE_WR_BUFFER;
 
-		for (unsigned i = 0; i < packet_len; i++)
-		{
+		for (unsigned i = 0; i < packet_len; i++) {
 			wr_buffer[header->buf_wr_pos++] = buf[i];
 
 			if (header->buf_wr_pos == SRAM_MAVLINK_INTERCORE_WR_SIZE) {
@@ -1030,7 +1027,7 @@ Mavlink::send_bytes(const uint8_t *buf, unsigned packet_len)
 
 			if (header->buf_rd_pos == header->buf_wr_pos) {
 				// PX4_ERR("mavlink rd_pos ==  wr_pos");
-			}	
+			}
 		}
 
 		ret = packet_len;
@@ -1061,12 +1058,11 @@ Mavlink::send_bytes(const uint8_t *buf, unsigned packet_len)
 		}
 
 		/* send message to UART */
-		if (get_protocol() == SERIAL) 
-		{
+		if (get_protocol() == SERIAL) {
 			ret = ::write(_uart_fd, buf, packet_len);
 		}
 
-	#ifdef __PX4_POSIX
+#ifdef __PX4_POSIX
 
 		else {
 			if (_network_buf_len + packet_len < sizeof(_network_buf) / sizeof(_network_buf[0])) {
@@ -1077,7 +1073,7 @@ Mavlink::send_bytes(const uint8_t *buf, unsigned packet_len)
 			}
 		}
 
-	#endif
+#endif
 
 	}
 
@@ -1974,12 +1970,10 @@ Mavlink::task_main(int argc, char *argv[])
 		/* flush stdout in case MAVLink is about to take it over */
 		fflush(stdout);
 
-		if (isUserCustomUart()) 
-		{
+		if (isUserCustomUart()) {
 			_flow_control_mode = FLOW_CONTROL_AUTO;
-		}
-		else 
-		{
+
+		} else {
 			/* default values for arguments */
 			_uart_fd = mavlink_open_uart(_baudrate, _device_name, _force_flow_control);
 
diff --git a/src/modules/mavlink/mavlink_receiver.cpp b/src/modules/mavlink/mavlink_receiver.cpp
index bfc350512f811796c83c70c8475a88c372adf91e..496cfb47886080439cb0f556034948c167d9b10f 100644
--- a/src/modules/mavlink/mavlink_receiver.cpp
+++ b/src/modules/mavlink/mavlink_receiver.cpp
@@ -2520,32 +2520,30 @@ MavlinkReceiver::receive_thread(void *arg)
 
 	while (!_mavlink->_task_should_exit) {
 
-		if(_mavlink->isUserCustomUart()) {
-			
+		if (_mavlink->isUserCustomUart()) {
+
 			const unsigned character_count = 20;
 
 			STRU_MavlinkInterCoreHeader *header = (STRU_MavlinkInterCoreHeader *)SRAM_MAVLINK_INTERCORE_RD_HEADER_ST_ADDR;
 
-	 		uint8_t *rd_buffer = (uint8_t *)SRAM_MAVLINK_INTERCORE_RD_BUFFER;
+			uint8_t *rd_buffer = (uint8_t *)SRAM_MAVLINK_INTERCORE_RD_BUFFER;
 
-			nread = 0;  
+			nread = 0;
 
 			// set in_use tell cpu2 cpu0 is write data
 			header->in_use = 1;
 
-			while ((header->buf_rd_pos != header->buf_wr_pos) && nread < sizeof(buf))
-			{
+			while ((header->buf_rd_pos != header->buf_wr_pos) && nread < sizeof(buf)) {
 				uint8_t data = rd_buffer[header->buf_rd_pos++];
 				buf[nread++] = data;
-				
+
 				// PX4_INFO("buf_rd_pos %d, buf_wr_pos = %d", header->buf_rd_pos, header->buf_wr_pos);
 				if (header->buf_rd_pos == SRAM_MAVLINK_INTERCORE_RD_SIZE) {
 					header->buf_rd_pos = 0;
 				}
 			}
 
-			if (nread < (ssize_t)character_count) 
-			{
+			if (nread < (ssize_t)character_count) {
 				unsigned sleeptime = (1.0f / (_mavlink->get_baudrate() / 10)) * character_count * 1000000;
 				usleep(sleeptime);
 			}
@@ -2584,51 +2582,51 @@ MavlinkReceiver::receive_thread(void *arg)
 // #endif
 			// only start accepting messages once we're sure who we talk to
 			/* if read failed, this loop won't execute */
-				for (ssize_t i = 0; i < nread; i++) {
-					if (mavlink_parse_char(_mavlink->get_channel(), buf[i], &msg, &_status)) {
-						/* check if we received version 2 and request a switch. */
-						if (!(_mavlink->get_status()->flags & MAVLINK_STATUS_FLAG_IN_MAVLINK1)) {
-							/* this will only switch to proto version 2 if allowed in settings */
+			for (ssize_t i = 0; i < nread; i++) {
+				if (mavlink_parse_char(_mavlink->get_channel(), buf[i], &msg, &_status)) {
+					/* check if we received version 2 and request a switch. */
+					if (!(_mavlink->get_status()->flags & MAVLINK_STATUS_FLAG_IN_MAVLINK1)) {
+						/* this will only switch to proto version 2 if allowed in settings */
 
-							_mavlink->set_proto_version(2);
-						}
+						_mavlink->set_proto_version(2);
+					}
 
-						/* handle generic messages and commands */
-						handle_message(&msg);
+					/* handle generic messages and commands */
+					handle_message(&msg);
 
-						/* handle packet with mission manager */
-						if (_mission_manager != nullptr) {
-							_mission_manager->handle_message(&msg);
-						}
+					/* handle packet with mission manager */
+					if (_mission_manager != nullptr) {
+						_mission_manager->handle_message(&msg);
+					}
 
-						/* handle packet with parameter component */
-						_parameters_manager.handle_message(&msg);
+					/* handle packet with parameter component */
+					_parameters_manager.handle_message(&msg);
 
-						if (_mavlink->ftp_enabled()) {
-							/* handle packet with ftp component */
-							_mavlink_ftp.handle_message(&msg);
-						}
+					if (_mavlink->ftp_enabled()) {
+						/* handle packet with ftp component */
+						_mavlink_ftp.handle_message(&msg);
+					}
 
-						/* handle packet with log component */
-						_mavlink_log_handler.handle_message(&msg);
+					/* handle packet with log component */
+					_mavlink_log_handler.handle_message(&msg);
 
-						/* handle packet with timesync component */
-						_mavlink_timesync.handle_message(&msg);
+					/* handle packet with timesync component */
+					_mavlink_timesync.handle_message(&msg);
 
-						/* handle packet with parent object */
-						_mavlink->handle_message(&msg);
-					}
+					/* handle packet with parent object */
+					_mavlink->handle_message(&msg);
 				}
+			}
 
-				/* count received bytes (nread will be -1 on read error) */
-				if (nread > 0) {
-					_mavlink->count_rxbytes(nread);
-				}
+			/* count received bytes (nread will be -1 on read error) */
+			if (nread > 0) {
+				_mavlink->count_rxbytes(nread);
+			}
 
 		} else if (poll(&fds[0], 1, timeout) > 0) {
 
 			if (_mavlink->get_protocol() == SERIAL) {
-				
+
 				/*
 				 * to avoid reading very small chunks wait for data before reading
 				 * this is designed to target one message, so >20 bytes at a time
@@ -2686,7 +2684,7 @@ MavlinkReceiver::receive_thread(void *arg)
 							/* this will only switch to proto version 2 if allowed in settings */
 							_mavlink->set_proto_version(2);
 						}
-						
+
 						/* handle generic messages and commands */
 						handle_message(&msg);
 
diff --git a/src/modules/mc_pos_control/mc_pos_control_main.cpp b/src/modules/mc_pos_control/mc_pos_control_main.cpp
index 85e3f2c285cc24fef5093d01f9512439aa47c63a..c733fcaad3800e6a1e3e3f282014e94043869d5a 100644
--- a/src/modules/mc_pos_control/mc_pos_control_main.cpp
+++ b/src/modules/mc_pos_control/mc_pos_control_main.cpp
@@ -110,7 +110,7 @@ public:
 	_EXT_ITCM int		start();
 
 	_EXT_ITCM bool		cross_sphere_line(const matrix::Vector3f &sphere_c, const float sphere_r,
-					  const matrix::Vector3f &line_a, const matrix::Vector3f &line_b, matrix::Vector3f &res);
+			const matrix::Vector3f &line_a, const matrix::Vector3f &line_b, matrix::Vector3f &res);
 
 private:
 
@@ -378,7 +378,8 @@ private:
 
 	_EXT_ITCM bool in_auto_takeoff();
 
-	_EXT_ITCM float get_vel_close(const matrix::Vector2f &unit_prev_to_current, const matrix::Vector2f &unit_current_to_next);
+	_EXT_ITCM float get_vel_close(const matrix::Vector2f &unit_prev_to_current,
+				      const matrix::Vector2f &unit_current_to_next);
 
 	_EXT_ITCM void set_manual_acceleration_xy(matrix::Vector2f &stick_input_xy_NED);
 
diff --git a/src/modules/navigator/follow_target.h b/src/modules/navigator/follow_target.h
index 0778e8e4bf21fe3a8a209e8790a274c4deae28df..76f7611f1b0a4082afa84b8a8d4e90549e9b4f42 100644
--- a/src/modules/navigator/follow_target.h
+++ b/src/modules/navigator/follow_target.h
@@ -143,5 +143,6 @@ private:
 	/**
 	 * Set follow_target item
 	 */
-	_EXT_ITCM void set_follow_target_item(struct mission_item_s *item, float min_clearance, follow_target_s &target, float yaw);
+	_EXT_ITCM void set_follow_target_item(struct mission_item_s *item, float min_clearance, follow_target_s &target,
+					      float yaw);
 };
diff --git a/src/modules/navigator/geofence.h b/src/modules/navigator/geofence.h
index 1dd8ef0d9138d02d894fa5de88957ec6a4312b40..bfbdd15c7764a7247144640d5edd1cf8885d00a8 100644
--- a/src/modules/navigator/geofence.h
+++ b/src/modules/navigator/geofence.h
@@ -88,7 +88,7 @@ public:
 	 * @return true: system is obeying fence, false: system is violating fence
 	 */
 	_EXT_ITCM bool check(const vehicle_global_position_s &global_position,
-		   const vehicle_gps_position_s &gps_position, const home_position_s home_pos, bool home_position_set);
+			     const vehicle_gps_position_s &gps_position, const home_position_s home_pos, bool home_position_set);
 
 	/**
 	 * Return whether a mission item obeys the geofence.
diff --git a/src/modules/navigator/land.h b/src/modules/navigator/land.h
index 9f9ac07ae32fda20b5e917ad681645de9c860abf..725f991ae1af1cc010ab438416350aef94275e6c 100644
--- a/src/modules/navigator/land.h
+++ b/src/modules/navigator/land.h
@@ -47,7 +47,7 @@ class Land : public MissionBlock
 {
 public:
 	_EXT_ITCM Land(Navigator *navigator);
-	 ~Land() = default;
+	~Land() = default;
 
 	_EXT_ITCM void on_activation() override;
 	_EXT_ITCM void on_active() override;
diff --git a/src/modules/navigator/mission.h b/src/modules/navigator/mission.h
index 0b18a3816d991fc59692e47742fbc951574ca821..7b903d393183ae29bda7a3b2d9072ecea932462e 100644
--- a/src/modules/navigator/mission.h
+++ b/src/modules/navigator/mission.h
@@ -181,7 +181,7 @@ private:
 	 * @return true if current mission item available
 	 */
 	_EXT_ITCM bool prepare_mission_items(mission_item_s *mission_item,
-				   mission_item_s *next_position_mission_item, bool *has_next_position_item);
+					     mission_item_s *next_position_mission_item, bool *has_next_position_item);
 
 	/**
 	 * Read current (offset == 0) or a specific (offset > 0) mission item
diff --git a/src/modules/navigator/mission_feasibility_checker.h b/src/modules/navigator/mission_feasibility_checker.h
index c5d2eadda49fdcfb6e740d16d4681ff9c23c2412..415a0b9193c36501436f71066fd6535ad5ccb607 100644
--- a/src/modules/navigator/mission_feasibility_checker.h
+++ b/src/modules/navigator/mission_feasibility_checker.h
@@ -56,7 +56,8 @@ private:
 	/* Checks for all airframes */
 	_EXT_ITCM bool checkGeofence(const mission_s &mission, float home_alt, bool home_valid);
 
-	_EXT_ITCM bool checkHomePositionAltitude(const mission_s &mission, float home_alt, bool home_alt_valid, bool throw_error);
+	_EXT_ITCM bool checkHomePositionAltitude(const mission_s &mission, float home_alt, bool home_alt_valid,
+			bool throw_error);
 
 	_EXT_ITCM bool checkMissionItemValidity(const mission_s &mission);
 
@@ -82,8 +83,8 @@ public:
 	 * Returns true if mission is feasible and false otherwise
 	 */
 	_EXT_ITCM bool checkMissionFeasible(const mission_s &mission,
-				  float max_distance_to_1st_waypoint, float max_distance_between_waypoints,
-				  bool land_start_req);
+					    float max_distance_to_1st_waypoint, float max_distance_between_waypoints,
+					    bool land_start_req);
 
 };
 
diff --git a/src/modules/navigator/navigator.h b/src/modules/navigator/navigator.h
index 314673150eec33e0a092752c6e944ca24826194f..51b87ed14c7b2418282ba9dc5f2f5f30b80912dc 100644
--- a/src/modules/navigator/navigator.h
+++ b/src/modules/navigator/navigator.h
@@ -127,8 +127,9 @@ public:
 	 * @param hor_velocity Horizontal velocity of traffic, in m/s
 	 * @param ver_velocity Vertical velocity of traffic, in m/s
 	 */
-	_EXT_ITCM void		fake_traffic(const char *callsign, float distance, float direction, float traffic_heading, float altitude_diff,
-				     float hor_velocity, float ver_velocity);
+	_EXT_ITCM void		fake_traffic(const char *callsign, float distance, float direction, float traffic_heading,
+					     float altitude_diff,
+					     float hor_velocity, float ver_velocity);
 
 	/**
 	 * Check nearby traffic for potential collisions
diff --git a/src/modules/navigator/navigator_mode.h b/src/modules/navigator/navigator_mode.h
index cfc464aaa5e4a73d1cd8e46bfacf5183b8083587..d036ec36c6a56cb6c4b0063bd7704f00fcc2049b 100644
--- a/src/modules/navigator/navigator_mode.h
+++ b/src/modules/navigator/navigator_mode.h
@@ -79,5 +79,5 @@ protected:
 	Navigator *_navigator{nullptr};
 
 private:
-	 bool _active{false};
+	bool _active{false};
 };
diff --git a/src/modules/position_estimator_inav/position_estimator_inav_main.cpp b/src/modules/position_estimator_inav/position_estimator_inav_main.cpp
index 5a8c025fa099c41785f63c814ee56a94015a642b..b71c99b34b2f77666baa50ca5a76ca2e77470c15 100644
--- a/src/modules/position_estimator_inav/position_estimator_inav_main.cpp
+++ b/src/modules/position_estimator_inav/position_estimator_inav_main.cpp
@@ -187,9 +187,9 @@ _EXT_ITCM int position_estimator_inav_main(int argc, char *argv[])
 
 #ifdef INAV_DEBUG
 _EXT_ITCM static void write_debug_log(const char *msg, float dt, float x_est[2], float y_est[2], float z_est[2],
-			    float x_est_prev[2], float y_est_prev[2], float z_est_prev[2],
-			    float acc[3], float corr_gps[3][2], float w_xy_gps_p, float w_xy_gps_v, float corr_mocap[3][1], float w_mocap_p,
-			    float corr_vision[3][2], float w_xy_vision_p, float w_z_vision_p, float w_xy_vision_v)
+				      float x_est_prev[2], float y_est_prev[2], float z_est_prev[2],
+				      float acc[3], float corr_gps[3][2], float w_xy_gps_p, float w_xy_gps_v, float corr_mocap[3][1], float w_mocap_p,
+				      float corr_vision[3][2], float w_xy_vision_p, float w_z_vision_p, float w_xy_vision_v)
 {
 	FILE *f = fopen(PX4_ROOTFSDIR"/fs/microsd/inav.log", "a");
 
@@ -1472,7 +1472,7 @@ _EXT_ITCM int inav_parameters_init(struct position_estimator_inav_param_handles
 }
 
 _EXT_ITCM int inav_parameters_update(const struct position_estimator_inav_param_handles *h,
-			   struct position_estimator_inav_params *p)
+				     struct position_estimator_inav_params *p)
 {
 	param_get(h->w_z_baro, &(p->w_z_baro));
 	param_get(h->w_z_gps_p, &(p->w_z_gps_p));
diff --git a/src/modules/systemlib/mavlink_log.c b/src/modules/systemlib/mavlink_log.c
index 9317fd5608a645f18623e0db162dc424347a2f96..a83a6d680a82bb77fcbd94ceca86b43be7d331c8 100644
--- a/src/modules/systemlib/mavlink_log.c
+++ b/src/modules/systemlib/mavlink_log.c
@@ -51,7 +51,7 @@
 #define MAVLINK_LOG_QUEUE_SIZE 5
 
 
- __EXPORT void mavlink_vasprintf(int severity, orb_advert_t *mavlink_log_pub, const char *fmt, ...)
+__EXPORT void mavlink_vasprintf(int severity, orb_advert_t *mavlink_log_pub, const char *fmt, ...)
 {
 	// TODO: add compile check for maxlen
 
diff --git a/src/modules/systemlib/print_load_nuttx.c b/src/modules/systemlib/print_load_nuttx.c
index 476ab051371b4ab4474e177276245a6963e0f5e7..dfe9c28982129bc94adf08f6df955bb984c353ed 100644
--- a/src/modules/systemlib/print_load_nuttx.c
+++ b/src/modules/systemlib/print_load_nuttx.c
@@ -114,7 +114,7 @@ tstate_name(const tstate_t s)
 }
 
 _EXT_ITCM void print_load_buffer(uint64_t t, char *buffer, int buffer_length, print_load_callback_f cb, void *user,
-		       struct print_load_s *print_state)
+				 struct print_load_s *print_state)
 {
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Wformat" // NuttX uses a different printf format
diff --git a/src/modules/vtol_att_control/vtol_type.h b/src/modules/vtol_att_control/vtol_type.h
index e743166241cd3bf8cfe4d58ff78045cc3e641cdd..b2e18f30acff85aeedc1a8dd43a132a16279bd4e 100644
--- a/src/modules/vtol_att_control/vtol_type.h
+++ b/src/modules/vtol_att_control/vtol_type.h
@@ -244,7 +244,8 @@ protected:
 	 *
 	 * @return     next_state if succesfull, otherwise current_state
 	 */
-	_EXT_ITCM motor_state set_motor_state(const motor_state current_state, const motor_state next_state, const int value = 0);
+	_EXT_ITCM motor_state set_motor_state(const motor_state current_state, const motor_state next_state,
+					      const int value = 0);
 
 private:
 
diff --git a/src/platforms/common/shutdown.cpp b/src/platforms/common/shutdown.cpp
index 68f152a629195fde90174d16266faea4a266a28c..e66d0d42719865cfe064af04d8eb5f13cd5e5f19 100644
--- a/src/platforms/common/shutdown.cpp
+++ b/src/platforms/common/shutdown.cpp
@@ -186,7 +186,7 @@ void shutdown_worker(void *arg)
 
 	if ((done && shutdown_lock_counter == 0) || ++shutdown_counter > shutdown_timeout_ms / 10) {
 		if (shutdown_args & SHUTDOWN_ARG_REBOOT) {
-			PX4_WARN("Reboot NOW1. = %d ",shutdown_args & SHUTDOWN_ARG_TO_BOOTLOADER);
+			PX4_WARN("Reboot NOW1. = %d ", shutdown_args & SHUTDOWN_ARG_TO_BOOTLOADER);
 			px4_systemreset(shutdown_args & SHUTDOWN_ARG_TO_BOOTLOADER);
 
 		} else {
diff --git a/src/platforms/px4_micro_hal.h b/src/platforms/px4_micro_hal.h
index 497efb76de1d8136854bf77c63413f02a90dd649..4b78abe5675967cb5274aa2a39fde8d75abfa4fb 100644
--- a/src/platforms/px4_micro_hal.h
+++ b/src/platforms/px4_micro_hal.h
@@ -349,7 +349,7 @@ __BEGIN_DECLS
 #    define px4_arch_gpioread(pinset)               ar_gpioread(pinset)
 #    define px4_arch_gpiowrite(pinset, value)       ar_gpiowrite(pinset, value)
 #    define px4_arch_gpiosetevent(pinset,r,f,e,fp)  ar_gpiosetevent(pinset,r,f, e,fp)
-#    define px4_flash_init()                        ar_flash_init()  
+#    define px4_flash_init()                        ar_flash_init()
 #    define px4_flash_updateid(b, l, t)             ar_flash_update_id(b, l, t)
 
 #endif // defined(CONFIG_ARCH_CHIP_STM32) || defined(CONFIG_ARCH_CHIP_STM32F7)
diff --git a/src/systemcmds/hardfault_log/hardfault_log.c b/src/systemcmds/hardfault_log/hardfault_log.c
index a187e149a1c62051dcd2128292dcf311df173566..1951231d42fccf47084cd3056fccf7dc52b47b8d 100644
--- a/src/systemcmds/hardfault_log/hardfault_log.c
+++ b/src/systemcmds/hardfault_log/hardfault_log.c
@@ -234,7 +234,7 @@ _EXT_ITCM static int hardfault_get_desc(char *caller, struct bbsramd_s *desc, bo
  * write_stack_detail
  ****************************************************************************/
 _EXT_ITCM static int write_stack_detail(bool inValid, _stack_s *si, char *sp_name,
-			      char *buffer, int max, int fd)
+					char *buffer, int max, int fd)
 {
 
 	int n = 0;
@@ -283,8 +283,8 @@ _EXT_ITCM static int read_stack(int fd, stack_word_t *words, int num)
 	return bytes;
 }
 _EXT_ITCM static int  write_stack(bool inValid, int winsize, uint32_t wtopaddr,
-			uint32_t topaddr, uint32_t spaddr, uint32_t botaddr,
-			char *sp_name, char *buffer, int max, int infd, int outfd)
+				  uint32_t topaddr, uint32_t spaddr, uint32_t botaddr,
+				  char *sp_name, char *buffer, int max, int infd, int outfd)
 {
 	char marker[30];
 	stack_word_t stack[32];
@@ -415,7 +415,7 @@ _EXT_ITCM static int write_registers_info(int fdout, info_s *pi, char *buffer, i
  * write_interrupt_stack_info
  ****************************************************************************/
 _EXT_ITCM static int write_interrupt_stack_info(int fdout, info_s *pi, char *buffer,
-				      unsigned int sz)
+		unsigned int sz)
 {
 	int ret = ENOENT;
 
@@ -432,7 +432,7 @@ _EXT_ITCM static int write_interrupt_stack_info(int fdout, info_s *pi, char *buf
  * write_user_stack_info
  ****************************************************************************/
 _EXT_ITCM static int write_user_stack_info(int fdout, info_s *pi, char *buffer,
-				 unsigned int sz)
+		unsigned int sz)
 {
 	int ret = ENOENT;
 
@@ -448,7 +448,7 @@ _EXT_ITCM static int write_user_stack_info(int fdout, info_s *pi, char *buffer,
  * write_dump_info
  ****************************************************************************/
 _EXT_ITCM static int write_dump_info(int fdout, info_s *info, struct bbsramd_s *desc,
-			   char *buffer, unsigned int sz)
+				     char *buffer, unsigned int sz)
 {
 	char fmtbuff[ TIME_FMT_LEN + 1];
 	format_fault_time(HEADER_TIME_FMT, &desc->lastwrite, fmtbuff, sizeof(fmtbuff));
@@ -509,7 +509,7 @@ _EXT_ITCM static int write_dump_info(int fdout, info_s *info, struct bbsramd_s *
  * write_dump_time
  ****************************************************************************/
 _EXT_ITCM static int write_dump_time(char *caller, char *tag, int fdout,
-			   struct timespec *ts, char *buffer, unsigned int sz)
+				     struct timespec *ts, char *buffer, unsigned int sz)
 {
 	int ret = OK;
 	char fmtbuff[ TIME_FMT_LEN + 1];
@@ -526,7 +526,7 @@ _EXT_ITCM static int write_dump_time(char *caller, char *tag, int fdout,
  * write_dump_footer
  ****************************************************************************/
 _EXT_ITCM static int write_dump_header(char *caller, int fdout, struct timespec *ts,
-			     char *buffer, unsigned int sz)
+				       char *buffer, unsigned int sz)
 {
 	return write_dump_time(caller, "Begin", fdout, ts, buffer, sz);
 }
@@ -534,7 +534,7 @@ _EXT_ITCM static int write_dump_header(char *caller, int fdout, struct timespec
  * write_dump_footer
  ****************************************************************************/
 _EXT_ITCM static int write_dump_footer(char *caller, int fdout, struct timespec *ts,
-			     char *buffer, unsigned int sz)
+				       char *buffer, unsigned int sz)
 {
 	return write_dump_time(caller, "END", fdout, ts, buffer, sz);
 }
@@ -542,7 +542,7 @@ _EXT_ITCM static int write_dump_footer(char *caller, int fdout, struct timespec
  * write_intterupt_satck
  ****************************************************************************/
 _EXT_ITCM static int write_intterupt_stack(int fdin, int fdout, info_s *pi, char *buffer,
-				 unsigned int sz)
+		unsigned int sz)
 {
 	int ret = ENOENT;
 
@@ -565,7 +565,7 @@ _EXT_ITCM static int write_intterupt_stack(int fdin, int fdout, info_s *pi, char
  * write_user_stack
  ****************************************************************************/
 _EXT_ITCM static int write_user_stack(int fdin, int fdout, info_s *pi, char *buffer,
-			    unsigned int sz)
+				      unsigned int sz)
 {
 	int ret = ENOENT;
 
@@ -860,7 +860,7 @@ _EXT_ITCM static int hardfault_commit(char *caller)
  * hardfault_dowrite
  ****************************************************************************/
 _EXT_ITCM static int hardfault_dowrite(char *caller, int infd, int outfd,
-			     struct bbsramd_s *desc, int format)
+				       struct bbsramd_s *desc, int format)
 {
 	int ret = -ENOMEM;
 	char *line = zalloc(OUT_BUFFER_LEN);
@@ -961,7 +961,7 @@ _EXT_ITCM static int hardfault_dowrite(char *caller, int infd, int outfd,
 /****************************************************************************
  * hardfault_rearm
  ****************************************************************************/
- __EXPORT int hardfault_rearm(char *caller)
+__EXPORT int hardfault_rearm(char *caller)
 {
 	int ret = OK;
 	int rv = unlink(HARDFAULT_PATH);
@@ -982,7 +982,7 @@ _EXT_ITCM static int hardfault_dowrite(char *caller, int infd, int outfd,
 /****************************************************************************
  * hardfault_check_status
  ****************************************************************************/
- __EXPORT int hardfault_check_status(char *caller)
+__EXPORT int hardfault_check_status(char *caller)
 {
 	int state = -1;
 	struct bbsramd_s desc;
@@ -1035,7 +1035,7 @@ _EXT_ITCM static int hardfault_dowrite(char *caller, int infd, int outfd,
 /****************************************************************************
  * hardfault_increment_reboot
  ****************************************************************************/
- __EXPORT int hardfault_increment_reboot(char *caller, bool reset)
+__EXPORT int hardfault_increment_reboot(char *caller, bool reset)
 {
 	int ret = -EIO;
 	int count = 0;
@@ -1082,7 +1082,7 @@ _EXT_ITCM static int hardfault_dowrite(char *caller, int infd, int outfd,
  * hardfault_write
  ****************************************************************************/
 
- __EXPORT int hardfault_write(char *caller, int fd, int format, bool rearm)
+__EXPORT int hardfault_write(char *caller, int fd, int format, bool rearm)
 {
 	struct bbsramd_s desc;
 
@@ -1159,7 +1159,7 @@ _EXT_ITCM static void print_usage(void)
 /****************************************************************************
  * Name: hardfault_log_main
  ****************************************************************************/
- __EXPORT int hardfault_log_main(int argc, char *argv[])
+__EXPORT int hardfault_log_main(int argc, char *argv[])
 {
 	char *self = "hardfault_log";
 
diff --git a/src/systemcmds/mtd/24xxxx_mtd.c b/src/systemcmds/mtd/24xxxx_mtd.c
index e76f42cf58a63918bdfbcb0fa8987e0e5411a690..9ea6e29dc38d5bdcb9d5456760f4f15ce4f10a0e 100644
--- a/src/systemcmds/mtd/24xxxx_mtd.c
+++ b/src/systemcmds/mtd/24xxxx_mtd.c
@@ -282,7 +282,7 @@ _EXT_ITCM void at24c_test(void)
  ************************************************************************************/
 
 _EXT_ITCM static ssize_t at24c_bread(FAR struct mtd_dev_s *dev, off_t startblock,
-			   size_t nblocks, FAR uint8_t *buffer)
+				     size_t nblocks, FAR uint8_t *buffer)
 {
 	FAR struct at24c_dev_s *priv = (FAR struct at24c_dev_s *)dev;
 	size_t blocksleft;
@@ -376,7 +376,7 @@ _EXT_ITCM static ssize_t at24c_bread(FAR struct mtd_dev_s *dev, off_t startblock
  ************************************************************************************/
 
 _EXT_ITCM static ssize_t at24c_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks,
-			    FAR const uint8_t *buffer)
+				      FAR const uint8_t *buffer)
 {
 	FAR struct at24c_dev_s *priv = (FAR struct at24c_dev_s *)dev;
 	size_t blocksleft;
diff --git a/src/systemcmds/mtd/mtd.c b/src/systemcmds/mtd/mtd.c
index cee08a8b142f0b6a228ab25ba4f715ea75f56705..533fc1c713f980dd2b23d51b6e630824f07f85ff 100644
--- a/src/systemcmds/mtd/mtd.c
+++ b/src/systemcmds/mtd/mtd.c
@@ -377,7 +377,7 @@ mtd_start(char *partition_names[], unsigned n_partitions)
 }
 
 _EXT_ITCM int mtd_get_geometry(unsigned long *blocksize, unsigned long *erasesize, unsigned long *neraseblocks,
-		     unsigned *blkpererase, unsigned *nblocks, unsigned *partsize, unsigned n_partitions)
+			       unsigned *blkpererase, unsigned *nblocks, unsigned *partsize, unsigned n_partitions)
 {
 	/* Get the geometry of the FLASH device */