A domain-specific-language and compiler for low-level bitstream processing.
Open Test Platform for LTE/LTE-U
bladeRF USB 3.0 Superspeed Software Defined Radio Source Code
一个从零开始写的极简、非常易懂的RISC-V处理器核。
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The Ultra-Low Power RISC Core
QEMU with RISC-V (RV64G, RV32G) Emulation Support
RISC-V Tools (ISA Simulator and Tests)
A collection of core generators to use with FuseSoC
Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
Machine management for a container-centric world
Advanced Interface Bus (AIB) die-to-die hardware open source
OmniXtend cache coherence protocol
FuseSoC standard core library
FuseSoC-based SoC for SweRV EH1
OpenEmbedded/Yocto layer for RISC-V Architecture