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Hunyter/verilog-axis

Verilog AXI stream components for FPGA implementation

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Hunyter/verilog-axi

Verilog AXI components for FPGA implementation

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Hunyter/darkriscv forked from paulzlb/darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

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Hunyter/DQN-Fighter forked from Cybersh1t/DQN-Fighter

使用DQN玩格斗游戏。

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Hunyter/DQN-Atari-Agents forked from LiuPanfeng/DQN-Atari-Agents

DQN-Atari-Agents: Modularized & Parallel PyTorch implementation of several DQN Agents, i.a. DDQN, Dueling DQN, Noisy DQN, C51, Rainbow, and DRQN

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Hunyter/Ori-DQN forked from Cybersh1t/Ori-DQN

使用DQN打Ori and The Will of Wisps

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Hunyter/LiteOS forked from Huawei LiteOS/LiteOS

Huawei LiteOS开源代码官方主仓库. LiteOS Studio 开发工具请访问https://gitee.com/LiteOS/LiteOS_Studio

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Hunyter/fifo forked from kingstacker/fifo

8*8同步fifo和异步fifo，用Verilog语言描述。

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Hunyter/apb_spi_master forked from hyb/apb_spi_master