# ram

**Repository Path**: kingstacker/ram

## Basic Information

- **Project Name**: ram
- **Description**: Verilog语言描述一个ram
- **Primary Language**: Verilog
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 1
- **Created**: 2017-10-25
- **Last Updated**: 2020-12-19

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# ram
use verilog to describe the ram model