From 57589934a7130bf864506bfbfe54abedb7875047 Mon Sep 17 00:00:00 2001
From: yuezenglin <yuezenglin@hisilicon.com>
Date: Sun, 26 Jan 2025 16:05:29 +0800
Subject: [PATCH] pipeline_config amend

---
 .../model_train/parallel/pipeline_parallel.md             | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/docs/mindspore/source_zh_cn/model_train/parallel/pipeline_parallel.md b/docs/mindspore/source_zh_cn/model_train/parallel/pipeline_parallel.md
index a2b3371112..3ad87208a2 100644
--- a/docs/mindspore/source_zh_cn/model_train/parallel/pipeline_parallel.md
+++ b/docs/mindspore/source_zh_cn/model_train/parallel/pipeline_parallel.md
@@ -186,6 +186,14 @@ net.layer2.pipeline_stage = 0
 net.relu2.pipeline_stage = 1
 net.layer3.pipeline_stage = 1
 ```
+使能interleaved pipeline调度，`pipeline_stage`的非连续模型层需要进行交错式配置，配置如下：
+```
+net.layer1.pipeline_stage = 0
+net.relu1.pipeline_stage = 1
+net.layer2.pipeline_stage = 0
+net.relu2.pipeline_stage = 1
+net.layer3.pipeline_stage = 1
+```
 
 ### 训练网络
 
-- 
Gitee