From 0c53ca833d1114173fc6b6740bb1c74bc74bd24e Mon Sep 17 00:00:00 2001 From: Roman Rusyaev Date: Sat, 26 Feb 2022 18:17:53 +0300 Subject: [PATCH 1/7] Dump function IR before constant folding at CG phase Make refactoring related to function dumping at CG phase --- .../maple_be/src/cg/cg_phasemanager.cpp | 39 +++++++++++++------ 1 file changed, 28 insertions(+), 11 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/cg_phasemanager.cpp b/src/mapleall/maple_be/src/cg/cg_phasemanager.cpp index a7ae2e7280..eebcdf4623 100644 --- a/src/mapleall/maple_be/src/cg/cg_phasemanager.cpp +++ b/src/mapleall/maple_be/src/cg/cg_phasemanager.cpp @@ -45,6 +45,24 @@ namespace maplebe { } \ } while (0) +namespace { + +void DumpMIRFunc(MIRFunction &func, const char *msg, bool printAlways = false, const char* extraMsg = nullptr) { + bool dumpAll = (CGOptions::GetDumpPhases().find("*") != CGOptions::GetDumpPhases().end()); + bool dumpFunc = CGOptions::FuncFilter(func.GetName()); + + if (printAlways || (dumpAll && dumpFunc)) { + LogInfo::MapleLogger() << msg << '\n'; + func.Dump(); + + if (extraMsg) { + LogInfo::MapleLogger() << extraMsg << '\n'; + } + } +} + +} // anonymous namespace + void CgFuncPM::GenerateOutPutFile(MIRModule &m) { CHECK_FATAL(cg != nullptr, "cg is null"); CHECK_FATAL(cg->GetEmitter(), "emitter is null"); @@ -116,6 +134,7 @@ bool CgFuncPM::PhaseRun(MIRModule &m) { /* LowerIR. */ m.SetCurFunction(mirFunc); if (cg->DoConstFold()) { + DumpMIRFunc(*mirFunc, "************* before ConstantFold **************"); ConstantFold cf(m); (void)cf.Simplify(mirFunc->GetBody()); } @@ -249,20 +268,18 @@ void CgFuncPM::DoFuncCGLower(const MIRModule &m, MIRFunction &mirFunc) { if (m.GetFlavor() <= kFeProduced) { mirLower->SetLowerCG(); mirLower->SetMirFunc(&mirFunc); + + DumpMIRFunc(mirFunc, "************* before MIRLowerer **************"); mirLower->LowerFunc(mirFunc); } - bool dumpAll = (CGOptions::GetDumpPhases().find("*") != CGOptions::GetDumpPhases().end()); - bool dumpFunc = CGOptions::FuncFilter(mirFunc.GetName()); - if (!cg->IsQuiet() || (dumpAll && dumpFunc)) { - LogInfo::MapleLogger() << "************* before CGLowerer **************" << '\n'; - mirFunc.Dump(); - } + + bool isNotQuiet = !cg->IsQuiet(); + DumpMIRFunc(mirFunc, "************* before CGLowerer **************", isNotQuiet); + cgLower->LowerFunc(mirFunc); - if (!cg->IsQuiet() || (dumpAll && dumpFunc)) { - LogInfo::MapleLogger() << "************* after CGLowerer **************" << '\n'; - mirFunc.Dump(); - LogInfo::MapleLogger() << "************* end CGLowerer **************" << '\n'; - } + + DumpMIRFunc(mirFunc, "************* after CGLowerer **************", isNotQuiet, + "************* end CGLowerer **************"); } void CgFuncPM::EmitDuplicatedAsmFunc(MIRModule &m) const { -- Gitee From 766c981810e63eb921bb987adac3f5f88278aed0 Mon Sep 17 00:00:00 2001 From: Roman Rusyaev Date: Sat, 26 Feb 2022 18:23:32 +0300 Subject: [PATCH 2/7] Always select 64bit operand for adrp instruction --- src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 754c00e723..330d0d319e 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -2405,9 +2405,9 @@ void AArch64CGFunc::SelectAddrof(Operand &result, StImmOperand &stImm, FieldID f Operand *srcOpnd = &result; if (!IsAfterRegAlloc()) { // Create a new vreg/preg for the upper bits of the address - PregIdx pregIdx = GetFunction().GetPregTab()->CreatePreg(LOWERED_PTR_TYPE); + PregIdx pregIdx = GetFunction().GetPregTab()->CreatePreg(PTY_a64); MIRPreg *tmpPreg = GetFunction().GetPregTab()->PregFromPregIdx(pregIdx); - regno_t vRegNO = NewVReg(kRegTyInt, GetPrimTypeSize(LOWERED_PTR_TYPE)); + regno_t vRegNO = NewVReg(kRegTyInt, GetPrimTypeSize(PTY_a64)); RegOperand &tmpreg = GetOrCreateVirtualRegisterOperand(vRegNO); // Register this vreg mapping @@ -3372,8 +3372,7 @@ Operand &AArch64CGFunc::SelectCGArrayElemAdd(BinaryNode &node, const BaseNode &p MIRSymbol &symbol = *mirModule.CurFunction()->GetLocalOrGlobalSymbol(addrofNode->GetStIdx()); ASSERT(addrofNode->GetFieldID() == 0, "For debug SelectCGArrayElemAdd."); - PrimType primType = addrofNode->GetPrimType(); - Operand &result = GetOrCreateResOperand(parent, primType); + Operand &result = GetOrCreateResOperand(parent, PTY_a64); /* OP_constval */ ConstvalNode *constvalNode = static_cast(opnd1); -- Gitee From f72a1290c3afc27197b3db8f4f3f7a4b49f38b8e Mon Sep 17 00:00:00 2001 From: Roman Rusyaev Date: Sat, 26 Feb 2022 18:26:50 +0300 Subject: [PATCH 3/7] Let u32 type have a pointer and address properties for ILP32 mode --- src/mapleall/maple_ir/include/prim_types.def | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/src/mapleall/maple_ir/include/prim_types.def b/src/mapleall/maple_ir/include/prim_types.def index 3d2324f0c5..5492f972bf 100644 --- a/src/mapleall/maple_ir/include/prim_types.def +++ b/src/mapleall/maple_ir/include/prim_types.def @@ -141,18 +141,29 @@ static const PrimitiveTypeProperty PTProperty_u16 = { /*isVector*/false }; +#ifdef ILP32 +#define IS_U32_PTR true +#define IS_U64_PTR false +#else +#define IS_U32_PTR false +#define IS_U64_PTR true +#endif + static const PrimitiveTypeProperty PTProperty_u32 = { - /*type=*/PTY_u32, /*isInteger=*/true, /*isUnsigned=*/true, /*isAddress=*/false, /*isFloat=*/false, - /*isPointer=*/false, /*isSimple=*/false, /*isDynamic=*/false, /*isDynamicAny=*/false, /*isDynamicNone=*/false, + /*type=*/PTY_u32, /*isInteger=*/true, /*isUnsigned=*/true, /*isAddress=*/IS_U32_PTR, /*isFloat=*/false, + /*isPointer=*/IS_U32_PTR, /*isSimple=*/false, /*isDynamic=*/false, /*isDynamicAny=*/false, /*isDynamicNone=*/false, /*isVector*/false }; static const PrimitiveTypeProperty PTProperty_u64 = { - /*type=*/PTY_u64, /*isInteger=*/true, /*isUnsigned=*/true, /*isAddress=*/true, /*isFloat=*/false, - /*isPointer=*/true, /*isSimple=*/false, /*isDynamic=*/false, /*isDynamicAny=*/false, /*isDynamicNone=*/false, + /*type=*/PTY_u64, /*isInteger=*/true, /*isUnsigned=*/true, /*isAddress=*/IS_U64_PTR, /*isFloat=*/false, + /*isPointer=*/IS_U64_PTR, /*isSimple=*/false, /*isDynamic=*/false, /*isDynamicAny=*/false, /*isDynamicNone=*/false, /*isVector*/false }; +#undef IS_U32_PTR +#undef IS_U64_PTR + static const PrimitiveTypeProperty PTProperty_u128 = { /*type=*/PTY_u128, /*isInteger=*/true, /*isUnsigned=*/true, /*isAddress=*/false, /*isFloat=*/false, /*isPointer=*/false, /*isSimple=*/false, /*isDynamic=*/false, /*isDynamicAny=*/false, /*isDynamicNone=*/false, -- Gitee From 2e0c2150a3a45146238cc155d3cc21f7376ddc17 Mon Sep 17 00:00:00 2001 From: Roman Rusyaev Date: Sat, 26 Feb 2022 18:29:50 +0300 Subject: [PATCH 4/7] Remove unnecessary checking for a32 type in MIRIntConst ctor Introduce GetSXTValue function that obtains sign-extended value from a constant Fix bug in forming offset for a load instruction in ILP32 mode --- src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 2 +- src/mapleall/maple_ir/include/mir_const.h | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 330d0d319e..77dfc05ac8 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -8235,7 +8235,7 @@ MemOperand &AArch64CGFunc::CreateNonExtendMemOpnd(PrimType ptype, const BaseNode ASSERT(constOfstNode->GetConstVal()->GetKind() == kConstInt, "expect MIRIntConst"); MIRIntConst *intOfst = safe_cast(constOfstNode->GetConstVal()); CHECK_FATAL(intOfst != nullptr, "just checking"); - offset = (addrExpr.GetOpCode() == OP_add) ? offset + intOfst->GetValue() : offset - intOfst->GetValue(); + offset = (addrExpr.GetOpCode() == OP_add) ? offset + intOfst->GetSXTValue() : offset - intOfst->GetSXTValue(); } else { addrOpnd = HandleExpr(parent, addrExpr); } diff --git a/src/mapleall/maple_ir/include/mir_const.h b/src/mapleall/maple_ir/include/mir_const.h index a8abffac85..bd66b92894 100644 --- a/src/mapleall/maple_ir/include/mir_const.h +++ b/src/mapleall/maple_ir/include/mir_const.h @@ -97,8 +97,6 @@ class MIRIntConst : public MIRConst { if (!IsPrimitiveDynType(type.GetPrimType())) { if (type.GetPrimType() == PTY_u128 || type.GetPrimType() == PTY_i128) { Trunc(64u); - } else if (type.GetPrimType() == PTY_a32) { - CHECK_FATAL(val <= INT32_MAX && val >= INT32_MIN, "address out of range"); } else { Trunc(GetPrimTypeBitSize(type.GetPrimType())); } @@ -141,6 +139,11 @@ class MIRIntConst : public MIRConst { return value; } + int64 GetSXTValue() const { + uint32 width = GetPrimTypeBitSize(GetType().GetPrimType()); + return static_cast(value << (64 - width)) >> (64 - width); + } + void SetValue(int64 val) const { (void)val; CHECK_FATAL(false, "Can't Use This Interface in This Object"); -- Gitee From 38be7326b05e23c6879444dc2f1eb5ccf0ab924c Mon Sep 17 00:00:00 2001 From: Roman Rusyaev Date: Sat, 26 Feb 2022 18:31:30 +0300 Subject: [PATCH 5/7] Select an appropriate load instruction while re-materialization --- src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp index 859e968f70..e47437aa80 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp @@ -242,7 +242,8 @@ std::vector LiveRange::Rematerialize(AArch64CGFunc *cgFunc, kSizeOfPtr * kBitsPerByte, static_cast(®Op), nullptr, &offsetOp, nullptr); - insn = &cg->BuildInstruction(MOP_xldr, regOp, memOpnd); + MOperator ldOp = (memOpnd.GetSize() == k64BitSize) ? MOP_xldr : MOP_wldr; + insn = &cg->BuildInstruction(ldOp, regOp, memOpnd); insns.push_back(insn); if (offset > 0) { AArch64OfstOperand &ofstOpnd = cgFunc->GetOrCreateOfstOpnd(static_cast(offset), k32BitSize); -- Gitee From 044d1af57ffbf3442038ff5aeca5779b68e50d81 Mon Sep 17 00:00:00 2001 From: Roman Rusyaev Date: Sat, 26 Feb 2022 18:33:55 +0300 Subject: [PATCH 6/7] Support 32bit instructions in cgtargetprop phase --- src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp index 06fde8e3c9..3557ec087b 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp @@ -99,6 +99,8 @@ MOperator A64ConstProp::GetReversalMOP(MOperator arithMop) { return MOP_xsubrri12; case MOP_xsubrri12: return MOP_xaddrri12; + case MOP_wsubrri12: + return MOP_waddrri12; default: CHECK_FATAL(false, "NYI"); break; @@ -1592,10 +1594,9 @@ void FpSpConstProp::Optimize(Insn &insn) { PropInMem(*useInsnInfo.second, *useInsn); switch (useMop) { case MOP_xmovrr: + case MOP_wmovrr: PropInCopy(*useInsnInfo.second, *useInsn, insn.GetMachineOpcode()); break; - case MOP_wmovrr: - CHECK_FATAL(false, "NIY mov 32"); case MOP_xaddrri12: PropInArith(*useInsnInfo.second, *useInsn, kAArch64Add); break; -- Gitee From 103a18e20ce2917a1cd247b788562dc29a2e9e25 Mon Sep 17 00:00:00 2001 From: Roman Rusyaev Date: Sat, 26 Feb 2022 18:34:44 +0300 Subject: [PATCH 7/7] Always emit memory operand as 64bit register --- src/mapleall/maple_be/src/cg/aarch64/aarch64_operand.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_operand.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_operand.cpp index be6f5aaacc..3fb761948b 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_operand.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_operand.cpp @@ -256,7 +256,7 @@ void AArch64MemOperand::Emit(Emitter &emitter, const OpndProp *opndProp) const { auto *baseReg = static_cast(GetBaseRegister()); ASSERT(baseReg != nullptr, "expect an AArch64RegOperand here"); uint32 baseSize = baseReg->GetSize(); - if (CGOptions::IsPIC() && (baseSize != k64BitSize)) { + if (baseSize != k64BitSize) { baseReg->SetSize(k64BitSize); } baseReg->Emit(emitter, nullptr); -- Gitee