From 84d961de658c19cde12eea5487ebbfebae33247f Mon Sep 17 00:00:00 2001 From: William Chen Date: Wed, 8 Jun 2022 16:21:12 -0700 Subject: [PATCH 001/179] Changes from mplcglmbc10 --- .../clang/src/ast_struct2fe_helper.cpp | 3 + src/mapleall/maple_be/include/be/lower.h | 2 +- .../include/cg/aarch64/aarch64_cgfunc.h | 30 +- .../include/cg/aarch64/aarch64_color_ra.h | 1 + .../include/cg/aarch64/aarch64_phases.def | 2 +- src/mapleall/maple_be/include/cg/call_conv.h | 20 +- src/mapleall/maple_be/include/cg/cg.h | 19 +- src/mapleall/maple_be/include/cg/cgfunc.h | 11 + src/mapleall/maple_be/src/be/lower.cpp | 82 ++- .../maple_be/src/cg/aarch64/aarch64_args.cpp | 4 +- .../src/cg/aarch64/aarch64_call_conv.cpp | 13 +- .../src/cg/aarch64/aarch64_cgfunc.cpp | 555 +++++++++++++++--- .../src/cg/aarch64/aarch64_color_ra.cpp | 6 + .../maple_be/src/cg/aarch64/aarch64_ebo.cpp | 4 +- .../src/cg/aarch64/aarch64_memlayout.cpp | 34 +- .../src/cg/aarch64/aarch64_offset_adjust.cpp | 2 +- .../src/cg/aarch64/aarch64_proepilog.cpp | 94 ++- .../src/cg/aarch64/aarch64_reaching.cpp | 3 +- .../maple_be/src/cg/cg_phasemanager.cpp | 1 + src/mapleall/maple_be/src/cg/cgfunc.cpp | 44 +- src/mapleall/maple_be/src/cg/emit.cpp | 5 + src/mapleall/maple_be/src/cg/memlayout.cpp | 6 +- .../maple_ir/include/bin_mpl_export.h | 28 +- .../maple_ir/include/bin_mpl_import.h | 12 +- .../maple_ir/include/ir_safe_cast_traits.def | 4 +- src/mapleall/maple_ir/include/keywords.def | 1 - src/mapleall/maple_ir/include/mir_builder.h | 2 + src/mapleall/maple_ir/include/mir_function.h | 18 +- src/mapleall/maple_ir/include/mir_lower.h | 1 + src/mapleall/maple_ir/include/mir_nodes.h | 2 +- src/mapleall/maple_ir/include/mir_parser.h | 2 +- src/mapleall/maple_ir/include/mir_symbol.h | 6 +- src/mapleall/maple_ir/include/mir_type.h | 27 +- src/mapleall/maple_ir/include/opcode_info.h | 1 + src/mapleall/maple_ir/include/opcodes.def | 1 + src/mapleall/maple_ir/include/opcodes.h | 4 +- src/mapleall/maple_ir/src/bin_func_export.cpp | 238 ++++---- src/mapleall/maple_ir/src/bin_func_import.cpp | 244 ++++---- src/mapleall/maple_ir/src/bin_mpl_export.cpp | 112 ++-- src/mapleall/maple_ir/src/bin_mpl_import.cpp | 48 +- src/mapleall/maple_ir/src/global_tables.cpp | 4 +- src/mapleall/maple_ir/src/mir_builder.cpp | 24 + src/mapleall/maple_ir/src/mir_function.cpp | 4 +- src/mapleall/maple_ir/src/mir_lower.cpp | 111 ++++ src/mapleall/maple_ir/src/mir_nodes.cpp | 4 +- src/mapleall/maple_ir/src/mir_parser.cpp | 31 +- src/mapleall/maple_ir/src/mir_type.cpp | 8 +- src/mapleall/maple_ir/src/parser.cpp | 18 +- src/mapleall/maple_me/include/lmbc_lower.h | 3 - .../maple_me/include/lmbc_memlayout.h | 59 +- src/mapleall/maple_me/src/alias_class.cpp | 8 +- src/mapleall/maple_me/src/code_factoring.cpp | 4 +- .../src/demand_driven_alias_analysis.cpp | 4 +- src/mapleall/maple_me/src/irmap_build.cpp | 7 +- src/mapleall/maple_me/src/irmap_emit.cpp | 5 +- src/mapleall/maple_me/src/lfo_dep_test.cpp | 2 + src/mapleall/maple_me/src/lmbc_lower.cpp | 258 ++------ src/mapleall/maple_me/src/lmbc_memlayout.cpp | 439 +------------- src/mapleall/maple_me/src/me_cfg.cpp | 2 + src/mapleall/maple_me/src/me_function.cpp | 4 +- .../maple_me/src/me_lower_globals.cpp | 13 +- .../maple_me/src/me_phase_manager.cpp | 7 +- src/mapleall/maple_me/src/me_rc_lowering.cpp | 1 + src/mapleall/maple_me/src/me_rename2preg.cpp | 1 + src/mapleall/maple_me/src/me_side_effect.cpp | 4 +- src/mapleall/maple_me/src/me_stmt_pre.cpp | 4 +- src/mapleall/maple_me/src/pme_emit.cpp | 9 +- src/mapleall/maple_me/src/ssa_devirtual.cpp | 4 +- src/mapleall/maple_me/src/ssa_pre.cpp | 2 + src/mapleall/mpl2mpl/src/constantfold.cpp | 6 +- 70 files changed, 1442 insertions(+), 1300 deletions(-) diff --git a/src/hir2mpl/ast_input/clang/src/ast_struct2fe_helper.cpp b/src/hir2mpl/ast_input/clang/src/ast_struct2fe_helper.cpp index 3a77948b15..63c34ea154 100644 --- a/src/hir2mpl/ast_input/clang/src/ast_struct2fe_helper.cpp +++ b/src/hir2mpl/ast_input/clang/src/ast_struct2fe_helper.cpp @@ -278,6 +278,9 @@ bool ASTFunc2FEHelper::ProcessDeclImpl(MapleAllocator &allocator) { ENCChecker::InsertBoundaryInAtts(attrs, func.GetBoundaryInfo()); mirMethodPair.second.second = attrs; mirFunc->SetFuncAttrs(attrs); + if (firstArgRet) { + mirFunc->GetMIRFuncType()->funcAttrs.SetAttr(FUNCATTR_firstarg_return); + } func.ClearGenericAttrsContentMap(); return true; } diff --git a/src/mapleall/maple_be/include/be/lower.h b/src/mapleall/maple_be/include/be/lower.h index 155f42daaf..12b4260f3d 100644 --- a/src/mapleall/maple_be/include/be/lower.h +++ b/src/mapleall/maple_be/include/be/lower.h @@ -187,7 +187,7 @@ class CGLowerer { void LowerTryCatchBlocks(BlockNode &body); #if TARGARM32 || TARGAARCH64 || TARGRISCV64 - BlockNode *LowerReturnStruct(NaryStmtNode &retNode); + BlockNode *LowerReturnStructUsingFakeParm(NaryStmtNode &retNode); #endif virtual BlockNode *LowerReturn(NaryStmtNode &retNode); void LowerEntry(MIRFunction &func); diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index 58a88cd943..525a620315 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -38,6 +38,7 @@ class LmbcArgInfo { MapleVector lmbcCallArgTypes; MapleVector lmbcCallArgOffsets; MapleVector lmbcCallArgNumOfRegs; // # of regs needed to complete struct + uint32 lmbcTotalStkUsed = -1; // TBD: remove when explicit addr for large agg is available }; class AArch64CGFunc : public CGFunc { @@ -101,7 +102,7 @@ class AArch64CGFunc : public CGFunc { return kRFLAG; } - MIRType *GetAggTyFromCallSite(StmtNode *stmt); + MIRType *LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList); RegOperand &GetOrCreateResOperand(const BaseNode &parent, PrimType primType); void IntrinsifyGetAndAddInt(ListOperand &srcOpnds, PrimType pty); @@ -125,9 +126,11 @@ class AArch64CGFunc : public CGFunc { bool needLow12 = false); MemOperand *FixLargeMemOpnd(MemOperand &memOpnd, uint32 align); MemOperand *FixLargeMemOpnd(MOperator mOp, MemOperand &memOpnd, uint32 dSize, uint32 opndIdx); + uint32 LmbcFindTotalStkUsed(std::vector* paramList); + uint32 LmbcTotalRegsUsed(); void LmbcSelectParmList(ListOperand *srcOpnds, bool isArgReturn); bool LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src); - bool LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src); + bool LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src, std::vector **parmList); void SelectAggDassign(DassignNode &stmt) override; void SelectIassign(IassignNode &stmt) override; void SelectIassignoff(IassignoffNode &stmt) override; @@ -135,6 +138,7 @@ class AArch64CGFunc : public CGFunc { void SelectIassignspoff(PrimType pTy, int32 offset, Operand &opnd) override; void SelectBlkassignoff(BlkassignoffNode &bNode, Operand *src) override; void SelectAggIassign(IassignNode &stmt, Operand &lhsAddrOpnd) override; + void SelectReturnSendOfStructInRegs(BaseNode *x) override; void SelectReturn(Operand *opnd0) override; void SelectIgoto(Operand *opnd0) override; void SelectCondGoto(CondGotoNode &stmt, Operand &opnd0, Operand &opnd1) override; @@ -486,7 +490,10 @@ class AArch64CGFunc : public CGFunc { void GenerateCleanupCodeForExtEpilog(BB &bb) override; uint32 FloatParamRegRequired(MIRStructType *structType, uint32 &fpSize) override; void AssignLmbcFormalParams() override; - RegOperand *GenLmbcParamLoad(int32 offset, uint32 byteSize, RegType regType, PrimType primType); + void LmbcGenSaveSpForAlloca() override; + MemOperand *GenLmbcFpMemOperand(int32 offset, uint32 byteSize, AArch64reg base = RFP); + RegOperand *GenLmbcParamLoad(int32 offset, uint32 byteSize, RegType regType, PrimType primType, AArch64reg baseRegno = RFP); + RegOperand *LmbcStructReturnLoad(int32 offset); Operand *GetBaseReg(const AArch64SymbolAlloc &symAlloc); int32 GetBaseOffset(const SymbolAlloc &symAlloc) override; @@ -726,6 +733,22 @@ class AArch64CGFunc : public CGFunc { return lmbcArgInfo->lmbcCallArgNumOfRegs; } + int32 GetLmbcTotalStkUsed() { + return lmbcArgInfo->lmbcTotalStkUsed; + } + + void SetLmbcTotalStkUsed(int32 offset) { + lmbcArgInfo->lmbcTotalStkUsed = offset; + } + + void SetLmbcCallReturnType(MIRType *ty) { + lmbcCallReturnType = ty; + } + + MIRType *GetLmbcCallReturnType() { + return lmbcCallReturnType; + } + private: enum RelationOperator : uint8 { kAND, @@ -793,6 +816,7 @@ class AArch64CGFunc : public CGFunc { regno_t methodHandleVreg = -1; uint32 alignPow = 5; /* function align pow defaults to 5 i.e. 2^5*/ LmbcArgInfo *lmbcArgInfo = nullptr; + MIRType *lmbcCallReturnType = nullptr; void SelectLoadAcquire(Operand &dest, PrimType dtype, Operand &src, PrimType stype, AArch64isa::MemoryOrdering memOrd, bool isDirect); diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_color_ra.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_color_ra.h index 491d59453f..d0588c51c4 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_color_ra.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_color_ra.h @@ -1519,6 +1519,7 @@ class GraphColorRegAllocator : public RegAllocator { #endif bool hasSpill = false; bool doMultiPass = false; + bool seenFP = false; }; class CallerSavePre: public CGPre { diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index a3a74d7b2f..ff08e81852 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -16,8 +16,8 @@ ADDTARGETPHASE("createstartendlabel", true); ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); + ADDTARGETPHASE("moveargs", true); if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("moveargs", true); /* SSA PHASES */ ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); diff --git a/src/mapleall/maple_be/include/cg/call_conv.h b/src/mapleall/maple_be/include/cg/call_conv.h index d7a194022c..4310cd986a 100644 --- a/src/mapleall/maple_be/include/cg/call_conv.h +++ b/src/mapleall/maple_be/include/cg/call_conv.h @@ -63,8 +63,8 @@ struct CCLocInfo { class LmbcFormalParamInfo { public: LmbcFormalParamInfo(PrimType pType, uint32 ofst, uint32 sz) : - type(nullptr), primType(pType), offset(ofst), size(sz), regNO(0), vregNO(0), numRegs(0), - fpSize(0), isReturn(false), isPureFloat(false), isOnStack(false) {} + type(nullptr), primType(pType), offset(ofst), onStackOffset(0), size(sz), regNO(0), vregNO(0), numRegs(0), + fpSize(0), isReturn(false), isPureFloat(false), isOnStack(false), hasRegassign(false) {} ~LmbcFormalParamInfo() = default; @@ -86,6 +86,12 @@ class LmbcFormalParamInfo { void SetOffset(uint32 ofs) { offset = ofs; } + uint32 GetOnStackOffset() { + return onStackOffset; + } + void SetOnStackOffset(uint32 ofs) { + onStackOffset = ofs; + } uint32 GetSize() { return size; } @@ -137,10 +143,17 @@ class LmbcFormalParamInfo { void SetIsOnStack() { isOnStack = true; } + bool HasRegassign() { + return hasRegassign; + } + void SetHasRegassign() { + hasRegassign = true; + } private: MIRStructType *type; PrimType primType; uint32 offset; + uint32 onStackOffset; /* stack location if isOnStack */ uint32 size; /* size primtype or struct */ regno_t regNO = 0; /* param reg num or starting reg num if numRegs > 0 */ regno_t vregNO = 0; /* if no explicit regassing from IR, create move from param reg */ @@ -148,7 +161,8 @@ class LmbcFormalParamInfo { uint32 fpSize = 0; /* size of fp param if isPureFloat */ bool isReturn; bool isPureFloat = false; - bool isOnStack; /* small struct with arrays need to be saved onto stack */ + bool isOnStack; /* large struct is passed by a copy on stack */ + bool hasRegassign; }; } /* namespace maplebe */ diff --git a/src/mapleall/maple_be/include/cg/cg.h b/src/mapleall/maple_be/include/cg/cg.h index 093289e42b..e1368acb1d 100644 --- a/src/mapleall/maple_be/include/cg/cg.h +++ b/src/mapleall/maple_be/include/cg/cg.h @@ -121,11 +121,13 @@ class CG { emitter(nullptr), labelOrderCnt(0), cgOption(cgOptions), - instrumentationFunction(nullptr) { + instrumentationFunction(nullptr), + fileGP(nullptr) { const std::string &internalNameLiteral = namemangler::GetInternalNameLiteral(namemangler::kJavaLangObjectStr); GStrIdx strIdxFromName = GlobalTables::GetStrTable().GetStrIdxFromName(internalNameLiteral); isLibcore = (GlobalTables::GetGsymTable().GetSymbolFromStrIdx(strIdxFromName) != nullptr); DefineDebugTraceFunctions(); + isLmbc = (mirModule->GetFlavor() == MIRFlavor::kFlavorLmbc); } virtual ~CG(); @@ -361,6 +363,10 @@ class CG { return isLibcore; } + bool IsLmbc() const { + return isLmbc; + } + MIRSymbol *GetDebugTraceEnterFunction() { return dbgTraceEnter; } @@ -421,6 +427,13 @@ class CG { /* Object map generation helper */ std::vector GetReferenceOffsets64(const BECommon &beCommon, MIRStructType &structType); + void SetGP(MIRSymbol *sym) { + fileGP = sym; + } + MIRSymbol *GetGP() const { + return fileGP; + } + static bool IsInFuncWrapLabels(MIRFunction *func) { return funcWrapLabels.find(func) != funcWrapLabels.end(); } @@ -449,12 +462,14 @@ class CG { LabelIDOrder labelOrderCnt; static CGFunc *currentCGFunction; /* current cg function being compiled */ CGOptions cgOption; - bool isLibcore; MIRSymbol *instrumentationFunction; MIRSymbol *dbgTraceEnter; MIRSymbol *dbgTraceExit; MIRSymbol *dbgFuncProfile; + MIRSymbol *fileGP; /* for lmbc, one local %GP per file */ static std::map> funcWrapLabels; + bool isLibcore; + bool isLmbc; }; /* class CG */ } /* namespace maplebe */ diff --git a/src/mapleall/maple_be/include/cg/cgfunc.h b/src/mapleall/maple_be/include/cg/cgfunc.h index 20a3f4c7c2..f79c4216df 100644 --- a/src/mapleall/maple_be/include/cg/cgfunc.h +++ b/src/mapleall/maple_be/include/cg/cgfunc.h @@ -160,6 +160,7 @@ class CGFunc { virtual uint32 FloatParamRegRequired(MIRStructType *structType, uint32 &fpSize) = 0; virtual void AssignLmbcFormalParams() = 0; LmbcFormalParamInfo *GetLmbcFormalParamInfo(uint32 offset); + virtual void LmbcGenSaveSpForAlloca() = 0; void GenerateLoc(StmtNode *stmt, unsigned &lastSrcLoc, unsigned &lastMplLoc); int32 GetFreqFromStmt(uint32 stmtId); void GenerateInstruction(); @@ -201,6 +202,7 @@ class CGFunc { virtual void SelectIassignspoff(PrimType pTy, int32 offset, Operand &opnd) = 0; virtual void SelectBlkassignoff(BlkassignoffNode &bNode, Operand *src) = 0; virtual void SelectAggIassign(IassignNode &stmt, Operand &lhsAddrOpnd) = 0; + virtual void SelectReturnSendOfStructInRegs(BaseNode *x) = 0; virtual void SelectReturn(Operand *opnd) = 0; virtual void SelectIgoto(Operand *opnd0) = 0; virtual void SelectCondGoto(CondGotoNode &stmt, Operand &opnd0, Operand &opnd1) = 0; @@ -1105,6 +1107,14 @@ class CGFunc { return useFP; } + void UnsetSeenFP() { + seenFP = false; + } + + bool SeenFP() const { + return seenFP; + } + void UpdateAllRegisterVregMapping(MapleMap &newMap); void RegisterVregMapping(regno_t vRegNum, PregIdx pidx) { @@ -1274,6 +1284,7 @@ class CGFunc { const MapleString shortFuncName; bool hasAsm = false; bool useFP = true; + bool seenFP = true; /* save stack protect kinds which can trigger stack protect */ uint8 stackProtectInfo = 0; diff --git a/src/mapleall/maple_be/src/be/lower.cpp b/src/mapleall/maple_be/src/be/lower.cpp index 8afc12bb7b..a5e1e015d6 100644 --- a/src/mapleall/maple_be/src/be/lower.cpp +++ b/src/mapleall/maple_be/src/be/lower.cpp @@ -121,6 +121,7 @@ void CGLowerer::RegisterExternalLibraryFunctions() { func->AllocSymTab(); MIRSymbol *funcSym = func->GetFuncSymbol(); funcSym->SetStorageClass(kScExtern); + funcSym->SetAppearsInCode(true); /* return type */ MIRType *retTy = GlobalTables::GetTypeTable().GetPrimType(extFnDescrs[i].retType); @@ -876,7 +877,7 @@ void CGLowerer::LowerTypePtr(BaseNode &node) const { #if TARGARM32 || TARGAARCH64 || TARGRISCV64 -BlockNode *CGLowerer::LowerReturnStruct(NaryStmtNode &retNode) { +BlockNode *CGLowerer::LowerReturnStructUsingFakeParm(NaryStmtNode &retNode) { BlockNode *blk = mirModule.CurFuncCodeMemPool()->New(); for (size_t i = 0; i < retNode.GetNopndSize(); ++i) { retNode.SetOpnd(LowerExpr(retNode, *retNode.GetNopndAt(i), *blk), i); @@ -1101,7 +1102,7 @@ void CGLowerer::LowerCallStmt(StmtNode &stmt, StmtNode *&nextStmt, BlockNode &ne return; } - if ((newStmt->GetOpCode() == OP_call) || (newStmt->GetOpCode() == OP_icall)) { + if (newStmt->GetOpCode() == OP_call || newStmt->GetOpCode() == OP_icall || newStmt->GetOpCode() == OP_icallproto) { newStmt = LowerCall(static_cast(*newStmt), nextStmt, newBlk, retty, uselvar); } newStmt->SetSrcPos(stmt.GetSrcPos()); @@ -1172,7 +1173,12 @@ StmtNode *CGLowerer::GenIntrinsiccallNode(const StmtNode &stmt, PUIdx &funcCalle StmtNode *CGLowerer::GenIcallNode(PUIdx &funcCalled, IcallNode &origCall) { StmtNode *newCall = nullptr; - newCall = mirModule.GetMIRBuilder()->CreateStmtIcall(origCall.GetNopnd()); + if (origCall.GetOpCode() == OP_icallassigned) { + newCall = mirModule.GetMIRBuilder()->CreateStmtIcall(origCall.GetNopnd()); + } else { + newCall = mirModule.GetMIRBuilder()->CreateStmtIcallproto(origCall.GetNopnd()); + static_cast(newCall)->SetRetTyIdx(static_cast(origCall).GetRetTyIdx()); + } newCall->SetSrcPos(origCall.GetSrcPos()); CHECK_FATAL(newCall != nullptr, "nullptr is not expected"); funcCalled = kFuncNotFound; @@ -1373,6 +1379,7 @@ BlockNode *CGLowerer::LowerCallAssignedStmt(StmtNode &stmt, bool uselvar) { static_cast(newCall)->SetReturnVec(*p2nRets); break; } + case OP_icallprotoassigned: case OP_icallassigned: { auto &origCall = static_cast(stmt); newCall = GenIcallNode(funcCalled, origCall); @@ -1480,6 +1487,15 @@ bool CGLowerer::LowerStructReturn(BlockNode &newBlk, StmtNode *stmt, (*p2nrets)[0].first = dnodeStmt->GetStIdx(); (*p2nrets)[0].second.SetFieldID(dnodeStmt->GetFieldID()); lvar = true; + // set ATTR_firstarg_return for callee + if (stmt->GetOpCode() == OP_callassigned) { + CallNode *callNode = static_cast(stmt); + MIRFunction *f = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(callNode->GetPUIdx()); + f->SetFirstArgReturn(); + f->GetMIRFuncType()->SetFirstArgReturn(); + } else { + // for icall, front-end already set ATTR_firstarg_return + } } else { /* struct <= 16 passed in regs lowered into call &foo regassign u64 %1 (regread u64 %%retval0) @@ -1497,13 +1513,19 @@ bool CGLowerer::LowerStructReturn(BlockNode &newBlk, StmtNode *stmt, CallNode *callStmt = mirModule.GetMIRBuilder()->CreateStmtCall(callNode->GetPUIdx(), callNode->GetNopnd()); callStmt->SetSrcPos(callNode->GetSrcPos()); newBlk.AddStatement(callStmt); - } else if (stmt->GetOpCode() == OP_icallassigned) { + } else if (stmt->GetOpCode() == OP_icallassigned || stmt->GetOpCode() == OP_icallprotoassigned) { auto *icallNode = static_cast(stmt); for (size_t i = 0; i < icallNode->GetNopndSize(); ++i) { BaseNode *newOpnd = LowerExpr(*icallNode, *icallNode->GetNopndAt(i), newBlk); icallNode->SetOpnd(newOpnd, i); } - IcallNode *icallStmt = mirModule.GetMIRBuilder()->CreateStmtIcall(icallNode->GetNopnd()); + IcallNode *icallStmt = nullptr; + if (stmt->GetOpCode() == OP_icallassigned) { + icallStmt = mirModule.GetMIRBuilder()->CreateStmtIcall(icallNode->GetNopnd()); + } else { + icallStmt = mirModule.GetMIRBuilder()->CreateStmtIcallproto(icallNode->GetNopnd()); + icallStmt->SetRetTyIdx(icallNode->GetRetTyIdx()); + } icallStmt->SetSrcPos(icallNode->GetSrcPos()); newBlk.AddStatement(icallStmt); } else { @@ -1768,6 +1790,7 @@ void CGLowerer::LowerAssertBoundary(StmtNode &stmt, BlockNode &block, BlockNode CondGotoNode *brFalseNode = mirBuilder->CreateStmtCondGoto(cond, OP_brfalse, labIdx); MIRFunction *printf = mirBuilder->GetOrCreateFunction("printf", TyIdx(PTY_i32)); + printf->GetFuncSymbol()->SetAppearsInCode(true); beCommon.UpdateTypeTable(*printf->GetMIRFuncType()); MapleVector argsPrintf(mirBuilder->GetCurrentFuncCodeMpAllocator()->Adapter()); uint32 oldTypeTableSize = GlobalTables::GetTypeTable().GetTypeTableSize(); @@ -1843,7 +1866,8 @@ BlockNode *CGLowerer::LowerBlock(BlockNode &block) { break; } case OP_callassigned: - case OP_icallassigned: { + case OP_icallassigned: + case OP_icallprotoassigned: { // pass the addr of lvar if this is a struct call assignment bool lvar = false; // nextStmt could be changed by the call to LowerStructReturn @@ -1863,6 +1887,7 @@ BlockNode *CGLowerer::LowerBlock(BlockNode &block) { case OP_intrinsiccall: case OP_call: case OP_icall: + case OP_icallproto: #if TARGARM32 || TARGAARCH64 || TARGRISCV64 || TARGX86_64 // nextStmt could be changed by the call to LowerStructReturn LowerCallStmt(*stmt, nextStmt, *newBlk); @@ -1872,8 +1897,8 @@ BlockNode *CGLowerer::LowerBlock(BlockNode &block) { break; case OP_return: { #if TARGARM32 || TARGAARCH64 || TARGRISCV64 - if (GetCurrentFunc()->IsReturnStruct()) { - newBlk->AppendStatementsFromBlock(*LowerReturnStruct(static_cast(*stmt))); + if (GetCurrentFunc()->IsFirstArgReturn() && stmt->NumOpnds() > 0) { + newBlk->AppendStatementsFromBlock(*LowerReturnStructUsingFakeParm(static_cast(*stmt))); } else { #endif NaryStmtNode *retNode = static_cast(stmt); @@ -1971,7 +1996,9 @@ void CGLowerer::SimplifyBlock(BlockNode &block) { } auto *newFunc = theMIRModule->GetMIRBuilder()->GetOrCreateFunction(asmMap.at(oldFunc->GetName()), callStmt->GetTyIdx()); - newFunc->GetFuncSymbol()->SetStorageClass(kScExtern); + MIRSymbol *funcSym = newFunc->GetFuncSymbol(); + funcSym->SetStorageClass(kScExtern); + funcSym->SetAppearsInCode(true); callStmt->SetPUIdx(newFunc->GetPuidx()); break; } @@ -2081,6 +2108,7 @@ StmtNode *CGLowerer::LowerCall( if (needCheckStore) { MIRFunction *fn = mirModule.GetMIRBuilder()->GetOrCreateFunction("MCC_Reflect_Check_Arraystore", TyIdx(PTY_void)); + fn->GetFuncSymbol()->SetAppearsInCode(true); beCommon.UpdateTypeTable(*fn->GetMIRFuncType()); fn->AllocSymTab(); MapleVector args(mirModule.GetMIRBuilder()->GetCurrentFuncCodeMpAllocator()->Adapter()); @@ -2107,7 +2135,7 @@ StmtNode *CGLowerer::LowerCall( } MIRType *retType = nullptr; - if (callNode.op == OP_icall) { + if (callNode.op == OP_icall || callNode.op == OP_icallproto) { if (retTy == nullptr) { return &callNode; } else { @@ -2153,7 +2181,7 @@ StmtNode *CGLowerer::LowerCall( addrofNode->SetStIdx(dsgnSt->GetStIdx()); addrofNode->SetFieldID(0); - if (callNode.op == OP_icall) { + if (callNode.op == OP_icall || callNode.op == OP_icallproto) { auto ond = callNode.GetNopnd().begin(); newNopnd.emplace_back(*ond); newNopnd.emplace_back(addrofNode); @@ -2175,7 +2203,27 @@ StmtNode *CGLowerer::LowerCall( } void CGLowerer::LowerEntry(MIRFunction &func) { + // determine if needed to insert fake parameter to return struct for current function if (func.IsReturnStruct()) { + MIRType *retType = func.GetReturnType(); +#if TARGAARCH64 + PrimType pty = IsStructElementSame(retType); + if (pty == PTY_f32 || pty == PTY_f64 || IsPrimitiveVector(pty)) { + func.SetStructReturnedInRegs(); + return; + } +#endif + if (retType->GetPrimType() != PTY_agg) { + return; + } + if (retType->GetSize() > k16ByteSize) { + func.SetFirstArgReturn(); + func.GetMIRFuncType()->SetFirstArgReturn(); + } else { + func.SetStructReturnedInRegs(); + } + } + if (func.IsFirstArgReturn() && func.GetReturnType()->GetPrimType() != PTY_void) { MIRSymbol *retSt = func.GetSymTab()->CreateSymbol(kScopeLocal); retSt->SetStorageClass(kScFormal); retSt->SetSKind(kStVar); @@ -2192,12 +2240,14 @@ void CGLowerer::LowerEntry(MIRFunction &func) { auto formal = func.GetFormal(i); formals.emplace_back(formal); } + func.SetFirstArgReturn(); beCommon.AddElementToFuncReturnType(func, func.GetReturnTyIdx()); func.UpdateFuncTypeAndFormalsAndReturnType(formals, TyIdx(PTY_void), true); auto *funcType = func.GetMIRFuncType(); ASSERT(funcType != nullptr, "null ptr check"); + funcType->SetFirstArgReturn(); beCommon.AddTypeSizeAndAlign(funcType->GetTypeIndex(), GetPrimTypeSize(funcType->GetPrimType())); } } @@ -2375,6 +2425,7 @@ MIRFunction *CGLowerer::RegisterFunctionVoidStarToVoid(BuiltinFunctionID id, con func->AllocSymTab(); MIRSymbol *funcSym = func->GetFuncSymbol(); funcSym->SetStorageClass(kScExtern); + funcSym->SetAppearsInCode(true); MIRType *argTy = GlobalTables::GetTypeTable().GetPtr(); MIRSymbol *argSt = func->GetSymTab()->CreateSymbol(kScopeLocal); argSt->SetNameStrIdx(mirBuilder->GetOrCreateStringIndex(paramName)); @@ -2416,6 +2467,7 @@ void CGLowerer::RegisterBuiltIns() { func->AllocSymTab(); MIRSymbol *funcSym = func->GetFuncSymbol(); funcSym->SetStorageClass(kScExtern); + funcSym->SetAppearsInCode(true); /* return type */ MIRType *retTy = desc.GetReturnType(); CHECK_FATAL(retTy != nullptr, "retTy should not be nullptr"); @@ -2571,6 +2623,7 @@ void CGLowerer::ProcessArrayExpr(BaseNode &expr, BlockNode &blkNode) { arrayNode.GetNopndAt(1), lenRegreadNode); CondGotoNode *brFalseNode = mirBuilder->CreateStmtCondGoto(cond, OP_brfalse, labIdx); MIRFunction *fn = mirBuilder->GetOrCreateFunction("MCC_Array_Boundary_Check", TyIdx(PTY_void)); + fn->GetFuncSymbol()->SetAppearsInCode(true); beCommon.UpdateTypeTable(*fn->GetMIRFuncType()); fn->AllocSymTab(); MapleVector args(mirBuilder->GetCurrentFuncCodeMpAllocator()->Adapter()); @@ -3102,6 +3155,7 @@ BaseNode *CGLowerer::LowerIntrinJavaArrayLength(const BaseNode &parent, Intrinsi MIRFunction *newFunc = mirBuilder->GetOrCreateFunction("MCC_ThrowNullArrayNullPointerException", GlobalTables::GetTypeTable().GetVoid()->GetTypeIndex()); + newFunc->GetFuncSymbol()->SetAppearsInCode(true); beCommon.UpdateTypeTable(*newFunc->GetMIRFuncType()); newFunc->AllocSymTab(); MapleVector args(mirBuilder->GetCurrentFuncCodeMpAllocator()->Adapter()); @@ -3473,6 +3527,7 @@ StmtNode *CGLowerer::LowerIntrinsicRCCall(const IntrinsiccallNode &intrincall) { if (intrinFuncIDs.find(intrinDesc) == intrinFuncIDs.end()) { /* add funcid into map */ MIRFunction *fn = mirBuilder->GetOrCreateFunction(intrinDesc->name, TyIdx(PTY_void)); + fn->GetFuncSymbol()->SetAppearsInCode(true); beCommon.UpdateTypeTable(*fn->GetMIRFuncType()); fn->AllocSymTab(); intrinFuncIDs[intrinDesc] = fn->GetPuidx(); @@ -3501,6 +3556,7 @@ void CGLowerer::LowerArrayStore(const IntrinsiccallNode &intrincall, BlockNode & if (needCheckStore) { MIRFunction *fn = mirBuilder->GetOrCreateFunction("MCC_Reflect_Check_Arraystore", TyIdx(PTY_void)); + fn->GetFuncSymbol()->SetAppearsInCode(true); beCommon.UpdateTypeTable(*fn->GetMIRFuncType()); fn->AllocSymTab(); MapleVector args(mirBuilder->GetCurrentFuncCodeMpAllocator()->Adapter()); @@ -3590,6 +3646,7 @@ StmtNode *CGLowerer::LowerIntrinsiccall(IntrinsiccallNode &intrincall, BlockNode beCommon.UpdateTypeTable(*fn->GetMIRFuncType()); fn->AllocSymTab(); st->SetFunction(fn); + st->SetAppearsInCode(true); return LowerDefaultIntrinsicCall(intrincall, *st, *fn); } @@ -3660,6 +3717,7 @@ PUIdx CGLowerer::GetBuiltinToUse(BuiltinFunctionID id) const { void CGLowerer::LowerGCMalloc(const BaseNode &node, const GCMallocNode &gcmalloc, BlockNode &blkNode, bool perm) { MIRFunction *func = mirBuilder->GetOrCreateFunction((perm ? "MCC_NewPermanentObject" : "MCC_NewObj_fixed_class"), (TyIdx)(LOWERED_PTR_TYPE)); + func->GetFuncSymbol()->SetAppearsInCode(true); beCommon.UpdateTypeTable(*func->GetMIRFuncType()); func->AllocSymTab(); /* Get the classinfo */ @@ -3678,6 +3736,7 @@ void CGLowerer::LowerGCMalloc(const BaseNode &node, const GCMallocNode &gcmalloc if (classSym->GetAttr(ATTR_abstract) || classSym->GetAttr(ATTR_interface)) { MIRFunction *funcSecond = mirBuilder->GetOrCreateFunction("MCC_Reflect_ThrowInstantiationError", (TyIdx)(LOWERED_PTR_TYPE)); + funcSecond->GetFuncSymbol()->SetAppearsInCode(true); beCommon.UpdateTypeTable(*funcSecond->GetMIRFuncType()); funcSecond->AllocSymTab(); BaseNode *arg = mirBuilder->CreateExprAddrof(0, *classSym); @@ -3796,6 +3855,7 @@ void CGLowerer::LowerJarrayMalloc(const StmtNode &stmt, const JarrayMallocNode & args.emplace_back(mirBuilder->CreateIntConst(0, PTY_u32)); } MIRFunction *func = mirBuilder->GetOrCreateFunction(funcName, (TyIdx)(LOWERED_PTR_TYPE)); + func->GetFuncSymbol()->SetAppearsInCode(true); beCommon.UpdateTypeTable(*func->GetMIRFuncType()); func->AllocSymTab(); CallNode *callAssign = nullptr; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_args.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_args.cpp index e0acbe83e7..cc8b10b6c5 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_args.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_args.cpp @@ -38,7 +38,7 @@ void AArch64MoveRegArgs::CollectRegisterArgs(std::map &argsL uint32 start = 0; if (numFormal) { MIRFunction *func = const_cast(aarchCGFunc->GetBecommon().GetMIRModule().CurFunction()); - if (func->IsReturnStruct()) { + if (func->IsReturnStruct() && func->IsFirstArgReturn()) { TyIdx tyIdx = func->GetFuncRetStructTyIdx(); if (aarchCGFunc->GetBecommon().GetTypeSize(tyIdx) <= k16ByteSize) { start = 1; @@ -436,7 +436,7 @@ void AArch64MoveRegArgs::MoveVRegisterArgs() { uint32 start = 0; if (formalCount) { MIRFunction *func = const_cast(aarchCGFunc->GetBecommon().GetMIRModule().CurFunction()); - if (func->IsReturnStruct()) { + if (func->IsReturnStruct() && func->IsFirstArgReturn()) { TyIdx tyIdx = func->GetFuncRetStructTyIdx(); if (aarchCGFunc->GetBecommon().GetTypeSize(tyIdx) <= k16BitSize) { start = 1; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_call_conv.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_call_conv.cpp index 2f0bb5b94f..17a08c5e9b 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_call_conv.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_call_conv.cpp @@ -304,24 +304,24 @@ int32 AArch64CallConvImpl::LocateNextParm(MIRType &mirType, CCLocInfo &pLoc, boo if (isFirst) { MIRFunction *func = tFunc != nullptr ? tFunc : const_cast(beCommon.GetMIRModule().CurFunction()); - if (func->IsReturnStruct()) { + if (func->IsFirstArgReturn()) { TyIdx tyIdx = func->GetFuncRetStructTyIdx(); size_t size = beCommon.GetTypeSize(tyIdx); if (size == 0) { /* For return struct size 0 there is no return value. */ return 0; - } else if (size > k16ByteSize) { - /* For return struct size > 16 bytes the pointer returns in x8. */ - pLoc.reg0 = R8; - return kSizeOfPtr; } + /* For return struct size > 16 bytes the pointer returns in x8. */ + pLoc.reg0 = R8; + return kSizeOfPtr; +#if 0 /* For return struct size less or equal to 16 bytes, the values * are returned in register pairs. * Check for pure float struct. */ AArch64ArgumentClass classes[kMaxRegCount] = { kAArch64NoClass }; uint32 fpSize; - MIRType *retType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(beCommon.GetFuncReturnType(*func)); + MIRType *retType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(tyIdx); uint32 numRegs = static_cast(ClassifyAggregate(beCommon, *retType, classes, sizeof(classes), fpSize)); if (classes[0] == kAArch64FloatClass) { CHECK_FATAL(numRegs <= kMaxRegCount, "LocateNextParm: illegal number of regs"); @@ -338,6 +338,7 @@ int32 AArch64CallConvImpl::LocateNextParm(MIRType &mirType, CCLocInfo &pLoc, boo } return 0; } +#endif } } uint64 typeSize = beCommon.GetTypeSize(mirType.GetTypeIndex()); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 92107c6804..f2b54fa274 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1411,15 +1411,44 @@ void AArch64CGFunc::SelectAsm(AsmNode &node) { } void AArch64CGFunc::SelectRegassign(RegassignNode &stmt, Operand &opnd0) { + if (GetCG()->IsLmbc()) { + PrimType lhsSize = stmt.GetPrimType(); + PrimType rhsSize = stmt.Opnd(0)->GetPrimType(); + if (lhsSize != rhsSize && stmt.Opnd(0)->GetOpCode() == OP_ireadoff) { + Insn *prev = GetCurBB()->GetLastInsn(); + if (prev->GetMachineOpcode() == MOP_wldrsb || prev->GetMachineOpcode() == MOP_wldrsh) { + opnd0.SetSize(GetPrimTypeBitSize(stmt.GetPrimType())); + prev->SetMOP(prev->GetMachineOpcode() == MOP_wldrsb ? MOP_xldrsb : MOP_xldrsh); + } else if (prev->GetMachineOpcode() == MOP_wldr && stmt.GetPrimType() == PTY_i64) { + opnd0.SetSize(GetPrimTypeBitSize(stmt.GetPrimType())); + prev->SetMOP(MOP_xldrsw); + } + } + } RegOperand *regOpnd = nullptr; PregIdx pregIdx = stmt.GetRegIdx(); if (IsSpecialPseudoRegister(pregIdx)) { - regOpnd = &GetOrCreateSpecialRegisterOperand(-pregIdx, stmt.GetPrimType()); + if (GetCG()->IsLmbc() && stmt.GetPrimType() == PTY_agg) { + if (static_cast(opnd0).IsOfIntClass()) { + regOpnd = &GetOrCreateSpecialRegisterOperand(-pregIdx, PTY_i64); + } else if (opnd0.GetSize() <= k4ByteSize) { + regOpnd = &GetOrCreateSpecialRegisterOperand(-pregIdx, PTY_f32); + } else { + regOpnd = &GetOrCreateSpecialRegisterOperand(-pregIdx, PTY_f64); + } + } else { + regOpnd = &GetOrCreateSpecialRegisterOperand(-pregIdx, stmt.GetPrimType()); + } } else { regOpnd = &GetOrCreateVirtualRegisterOperand(GetVirtualRegNOFromPseudoRegIdx(pregIdx)); } /* look at rhs */ PrimType rhsType = stmt.Opnd(0)->GetPrimType(); + if (GetCG()->IsLmbc() && rhsType == PTY_agg) { + /* This occurs when a call returns a small struct */ + /* The subtree should already taken care of the agg type that is in excess of 8 bytes */ + rhsType = PTY_i64; + } PrimType dtype = rhsType; if (GetPrimTypeBitSize(dtype) < k32BitSize) { ASSERT(IsPrimitiveInteger(dtype), ""); @@ -1441,6 +1470,12 @@ void AArch64CGFunc::SelectRegassign(RegassignNode &stmt, Operand &opnd0) { MIRPreg *preg = GetFunction().GetPregTab()->PregFromPregIdx(pregIdx); uint32 srcBitLength = GetPrimTypeSize(preg->GetPrimType()) * kBitsPerByte; GetCurBB()->AppendInsn(GetCG()->BuildInstruction(PickStInsn(srcBitLength, stype), *regOpnd, *dest)); + } else if (regOpnd->GetRegisterNumber() == R0 || regOpnd->GetRegisterNumber() == R1) { + Insn &pseudo = GetCG()->BuildInstruction(MOP_pseudo_ret_int, *regOpnd); + GetCurBB()->AppendInsn(pseudo); + } else if (regOpnd->GetRegisterNumber() >= V0 && regOpnd->GetRegisterNumber() <= V3) { + Insn &pseudo = GetCG()->BuildInstruction(MOP_pseudo_ret_float, *regOpnd); + GetCurBB()->AppendInsn(pseudo); } } @@ -1922,15 +1957,11 @@ void AArch64CGFunc::SelectIassignoff(IassignoffNode &stmt) { SelectCopy(memOpnd, destType, srcOpnd, destType); } -void AArch64CGFunc::SelectIassignfpoff(IassignFPoffNode &stmt, Operand &opnd) { - int32 offset = stmt.GetOffset(); - PrimType primType = stmt.GetPrimType(); - uint32 bitlen = GetPrimTypeSize(primType) * kBitsPerByte; - - Operand &srcOpnd = LoadIntoRegister(opnd, primType); +MemOperand *AArch64CGFunc::GenLmbcFpMemOperand(int32 offset, uint32 byteSize, AArch64reg baseRegno) { MemOperand *memOpnd; - RegOperand *rfp = &GetOrCreatePhysicalRegisterOperand(RFP, k64BitSize, kRegTyInt); - if (offset < 0) { + RegOperand *rfp = &GetOrCreatePhysicalRegisterOperand(baseRegno, k64BitSize, kRegTyInt); + uint32 bitlen = byteSize * kBitsPerByte; + if (offset < 0 && offset < -256) { RegOperand *baseOpnd = &CreateRegisterOperandOfType(PTY_a64); ImmOperand &immOpnd = CreateImmOperand(offset, k32BitSize, true); Insn &addInsn = GetCG()->BuildInstruction(MOP_xaddrri12, *baseOpnd, *rfp, immOpnd); @@ -1942,11 +1973,45 @@ void AArch64CGFunc::SelectIassignfpoff(IassignFPoffNode &stmt, Operand &opnd) { memOpnd = &GetOrCreateMemOpnd(MemOperand::kAddrModeBOi, bitlen, rfp, nullptr, offsetOpnd, nullptr); } memOpnd->SetStackMem(true); - MOperator mOp = PickStInsn(bitlen, primType); - Insn &store = GetCG()->BuildInstruction(mOp, srcOpnd, *memOpnd); - GetCurBB()->AppendInsn(store); + return memOpnd; +} + +void AArch64CGFunc::SelectIassignfpoff(IassignFPoffNode &stmt, Operand &opnd) { + int32 offset = stmt.GetOffset(); + PrimType primType = stmt.GetPrimType(); + MIRType *rType = GetLmbcCallReturnType(); + bool isPureFpStruct = false; + uint32 numRegs = 0; + if (rType && rType->GetPrimType() == PTY_agg && opnd.IsRegister() && static_cast(opnd).IsPhysicalRegister()) { + CHECK_FATAL(rType->GetSize() <= 16, "SelectIassignfpoff invalid agg size"); + uint32 fpSize; + numRegs = FloatParamRegRequired(static_cast(rType), fpSize); + if (numRegs) { + primType = (fpSize == k4ByteSize) ? PTY_f32 : PTY_f64; + isPureFpStruct = true; + } + } + uint32 byteSize = GetPrimTypeSize(primType); + uint32 bitlen = byteSize * kBitsPerByte; + if (isPureFpStruct) { + for (int i = 0 ; i < numRegs; ++i) { + MemOperand *memOpnd = GenLmbcFpMemOperand(offset + (i * byteSize), byteSize); + RegOperand &srcOpnd = GetOrCreatePhysicalRegisterOperand(AArch64reg(V0 + i), bitlen, kRegTyFloat); + MOperator mOp = PickStInsn(bitlen, primType); + Insn &store = GetCG()->BuildInstruction(mOp, srcOpnd, *memOpnd); + GetCurBB()->AppendInsn(store); + } + } else { + Operand &srcOpnd = LoadIntoRegister(opnd, primType); + MemOperand *memOpnd = GenLmbcFpMemOperand(offset, byteSize); + MOperator mOp = PickStInsn(bitlen, primType); + Insn &store = GetCG()->BuildInstruction(mOp, srcOpnd, *memOpnd); + GetCurBB()->AppendInsn(store); + } } +/* Load and assign to a new register. To be moved to the correct call register OR stack + location in LmbcSelectParmList */ void AArch64CGFunc::SelectIassignspoff(PrimType pTy, int32 offset, Operand &opnd) { if (GetLmbcArgInfo() == nullptr) { LmbcArgInfo *p = memPool->New(*GetFuncScopeAllocator()); @@ -1973,7 +2038,7 @@ void AArch64CGFunc::SelectIassignspoff(PrimType pTy, int32 offset, Operand &opnd } /* Search for CALL/ICALL/ICALLPROTO node, must be called from a blkassignoff node */ -MIRType *AArch64CGFunc::GetAggTyFromCallSite(StmtNode *stmt) { +MIRType *AArch64CGFunc::LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList) { for ( ; stmt != nullptr; stmt = stmt->GetNext()) { if (stmt->GetOpCode() == OP_call || stmt->GetOpCode() == OP_icallproto) { break; @@ -1986,25 +2051,20 @@ MIRType *AArch64CGFunc::GetAggTyFromCallSite(StmtNode *stmt) { if (stmt->GetOpCode() == OP_call) { CallNode *callNode = static_cast(stmt); MIRFunction *fn = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(callNode->GetPUIdx()); - if (fn->IsReturnStruct()) { - ++nargs; - } if (fn->GetFormalCount() > 0) { - ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(fn->GetNthParamTyIdx(nargs)); + ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(fn->GetFormalDefVec()[nargs].formalTyIdx); } + *parmList = &fn->GetParamTypes(); // would return null if the actual parameter is bogus } else if (stmt->GetOpCode() == OP_icallproto) { IcallNode *icallproto = static_cast(stmt); MIRType *type = GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallproto->GetRetTyIdx()); MIRFuncType *fType = static_cast(type); - MIRType *retType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(fType->GetRetTyIdx()); - if (retType->GetKind() == kTypeStruct) { - ++nargs; - } ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(fType->GetNthParamType(nargs)); + *parmList = &fType->GetParamTypeList(); } else { CHECK_FATAL(stmt->GetOpCode() == OP_icallproto, - "GetAggTyFromCallSite:: unexpected call operator"); + "LmbcGetAggTyFromCallSite:: unexpected call operator"); } return ty; } @@ -2081,11 +2141,11 @@ bool AArch64CGFunc::LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src) { } /* return true if blkassignoff for return, false otherwise */ -bool AArch64CGFunc::LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src) { +bool AArch64CGFunc::LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src, std::vector **parmList) { AArch64reg regno = static_cast(static_cast(src)->GetRegisterNumber()); if (IsBlkassignForPush(bNode)) { PrimType pTy = PTY_i64; - MIRStructType *ty = static_cast(GetAggTyFromCallSite(&bNode)); + MIRStructType *ty = static_cast(LmbcGetAggTyFromCallSite(&bNode, parmList)); uint32 size = 0; uint32 fpregs = ty ? FloatParamRegRequired(ty, size) : 0; /* fp size determined */ if (fpregs > 0) { @@ -2096,7 +2156,7 @@ bool AArch64CGFunc::LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src) { MemOperand &mem = CreateMemOpnd(regno, s, size * kBitsPerByte); RegOperand *res = &CreateVirtualRegisterOperand(NewVReg(kRegTyFloat, size)); SelectCopy(*res, pTy, mem, pTy); - SetLmbcArgInfo(res, pTy, bNode.offset + s, fpregs); + SetLmbcArgInfo(res, pTy, 0, fpregs); IncLmbcArgsInRegs(kRegTyFloat); } IncLmbcTotalArgs(); @@ -2137,6 +2197,41 @@ bool AArch64CGFunc::LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src) { return false; } +/* This function is incomplete and may be removed when Lmbc IR is changed + to have the lowerer figures out the address of the large agg to reside */ +uint32 AArch64CGFunc::LmbcFindTotalStkUsed(std::vector *paramList) { + AArch64CallConvImpl parmlocator(GetBecommon()); + CCLocInfo pLoc; + for (TyIdx tyIdx : *paramList) { + MIRType *ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(tyIdx); + parmlocator.LocateNextParm(*ty, pLoc); + } + return 0; +} + +/* All arguments passed as registers */ +uint32 AArch64CGFunc::LmbcTotalRegsUsed() { + if (GetLmbcArgInfo() == nullptr) { + return 0; /* no arg */ + } + MapleVector ®s = GetLmbcCallArgNumOfRegs(); + MapleVector &types = GetLmbcCallArgTypes(); + uint32 iCnt = 0; + uint32 fCnt = 0; + for (uint32 i = 0; i < regs.size(); i++) { + if (IsPrimitiveInteger(types[i])) { + if ((iCnt + regs[i]) <= k8ByteSize) { + iCnt += regs[i]; + }; + } else { + if ((fCnt + regs[i]) <= k8ByteSize) { + fCnt += regs[i]; + }; + } + } + return iCnt + fCnt; +} + /* If blkassignoff for argument, this function loads the agg arguments into virtual registers, disregard if there is sufficient physicall call registers. Argument > 16-bytes are copied to preset space and ptr @@ -2145,29 +2240,40 @@ bool AArch64CGFunc::LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src) { void AArch64CGFunc::SelectBlkassignoff(BlkassignoffNode &bNode, Operand *src) { CHECK_FATAL(src->GetKind() == Operand::kOpdRegister, "blkassign src type not in register"); + std::vector *parmList; if (GetLmbcArgInfo() == nullptr) { LmbcArgInfo *p = memPool->New(*GetFuncScopeAllocator()); SetLmbcArgInfo(p); } if (LmbcSmallAggForRet(bNode, src)) { return; - } else if (LmbcSmallAggForCall(bNode, src)) { + } else if (LmbcSmallAggForCall(bNode, src, &parmList)) { return; } - /* memcpy for agg assign OR large agg for arg/ret */ Operand *dest = HandleExpr(bNode, *bNode.Opnd(0)); RegOperand *regResult = &CreateVirtualRegisterOperand(NewVReg(kRegTyInt, k8ByteSize)); + /* memcpy for agg assign OR large agg for arg/ret */ + int32 offset = bNode.offset; + if (IsBlkassignForPush(bNode)) { + /* large agg for call, addr to be pushed in SelectCall */ + offset = GetLmbcTotalStkUsed(); + if (offset < 0) { + /* length of ALL stack based args for this call, this location is where the + next large agg resides, its addr will then be passed */ + offset = LmbcFindTotalStkUsed(parmList) + LmbcTotalRegsUsed(); + } + SetLmbcTotalStkUsed(offset + bNode.blockSize); /* next use */ + SetLmbcArgInfo(regResult, PTY_i64, 0, 1); /* 1 reg for ptr */ + IncLmbcArgsInRegs(kRegTyInt); + IncLmbcTotalArgs(); + /* copy large agg arg to offset below */ + } std::vector opndVec; opndVec.push_back(regResult); /* result */ - opndVec.push_back(PrepareMemcpyParamOpnd(bNode.offset, *dest));/* param 0 */ + opndVec.push_back(PrepareMemcpyParamOpnd(offset, *dest)); /* param 0 */ opndVec.push_back(src); /* param 1 */ opndVec.push_back(PrepareMemcpyParamOpnd(bNode.blockSize));/* param 2 */ SelectLibCall("memcpy", opndVec, PTY_a64, PTY_a64); - if (IsBlkassignForPush(bNode)) { - SetLmbcArgInfo(static_cast(src), PTY_i64, (int32)bNode.offset, 1); - IncLmbcArgsInRegs(kRegTyInt); - IncLmbcTotalArgs(); - } } void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) { @@ -2554,6 +2660,159 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) { } } +void AArch64CGFunc::SelectReturnSendOfStructInRegs(BaseNode *x) { + uint32 offset = 0; + if (x->GetOpCode() == OP_dread) { + DreadNode *dread = static_cast(x); + MIRSymbol *sym = GetFunction().GetLocalOrGlobalSymbol(dread->GetStIdx()); + MIRType *mirType = sym->GetType(); + if (dread->GetFieldID() != 0) { + MIRStructType *structType = static_cast(mirType); + mirType = structType->GetFieldType(dread->GetFieldID()); + offset = static_cast(GetBecommon().GetFieldOffset(*structType, dread->GetFieldID()).first); + } + uint32 typeSize = GetBecommon().GetTypeSize(mirType->GetTypeIndex()); + /* generate move to regs for agg return */ + AArch64CallConvImpl parmlocator(GetBecommon()); + CCLocInfo pLoc; + parmlocator.LocateNextParm(*mirType, pLoc, true, GetBecommon().GetMIRModule().CurFunction()); + /* aggregates are 8 byte aligned. */ + Operand *rhsmemopnd = nullptr; + RegOperand *result[kFourRegister]; /* up to 2 int or 4 fp */ + uint32 loadSize; + uint32 numRegs; + RegType regType; + PrimType retPty; + bool fpParm = false; + if (pLoc.numFpPureRegs) { + loadSize = pLoc.fpSize; + numRegs = pLoc.numFpPureRegs; + fpParm = true; + regType = kRegTyFloat; + retPty = (pLoc.fpSize == k4ByteSize) ? PTY_f32 : PTY_f64; + } else { + if (CGOptions::IsBigEndian()) { + loadSize = k8ByteSize; + numRegs = (typeSize <= k8ByteSize) ? kOneRegister : kTwoRegister; + regType = kRegTyInt; + retPty = PTY_u64; + } else { + loadSize = (typeSize <= k4ByteSize) ? k4ByteSize : k8ByteSize; + numRegs = (typeSize <= k8ByteSize) ? kOneRegister : kTwoRegister; + regType = kRegTyInt; + retPty = PTY_u32; + } + } + bool parmCopy = IsParamStructCopy(*sym); + for (uint32 i = 0; i < numRegs; i++) { + if (parmCopy) { + rhsmemopnd = &LoadStructCopyBase(*sym, + (offset + static_cast(i * (fpParm ? loadSize : k8ByteSize))), + static_cast(loadSize * kBitsPerByte)); + } else { + rhsmemopnd = &GetOrCreateMemOpnd(*sym, + (offset + static_cast(i * (fpParm ? loadSize : k8ByteSize))), + (loadSize * kBitsPerByte)); + } + result[i] = &CreateVirtualRegisterOperand(NewVReg(regType, loadSize)); + MOperator mop1 = PickLdInsn(loadSize * kBitsPerByte, retPty); + Insn &ld = GetCG()->BuildInstruction(mop1, *(result[i]), *rhsmemopnd); + GetCurBB()->AppendInsn(ld); + } + AArch64reg regs[kFourRegister]; + regs[0] = static_cast(pLoc.reg0); + regs[1] = static_cast(pLoc.reg1); + regs[2] = static_cast(pLoc.reg2); + regs[3] = static_cast(pLoc.reg3); + RegOperand *dest; + for (uint32 i = 0; i < numRegs; i++) { + AArch64reg preg; + MOperator mop2; + if (fpParm) { + preg = regs[i]; + mop2 = (loadSize == k4ByteSize) ? MOP_xvmovs : MOP_xvmovd; + } else { + preg = (i == 0 ? R0 : R1); + mop2 = (loadSize == k4ByteSize) ? MOP_wmovrr : MOP_xmovrr; + } + dest = &GetOrCreatePhysicalRegisterOperand(preg, (loadSize * kBitsPerByte), regType); + Insn &mov = GetCG()->BuildInstruction(mop2, *dest, *(result[i])); + GetCurBB()->AppendInsn(mov); + } + /* Create artificial dependency to extend the live range */ + for (uint32 i = 0; i < numRegs; i++) { + AArch64reg preg; + MOperator mop3; + if (fpParm) { + preg = regs[i]; + mop3 = MOP_pseudo_ret_float; + } else { + preg = (i == 0 ? R0 : R1); + mop3 = MOP_pseudo_ret_int; + } + dest = &GetOrCreatePhysicalRegisterOperand(preg, loadSize * kBitsPerByte, regType); + Insn &pseudo = GetCG()->BuildInstruction(mop3, *dest); + GetCurBB()->AppendInsn(pseudo); + } + return; + } else if (x->GetOpCode() == OP_iread) { + IreadNode *iread = static_cast(x); + RegOperand *rhsAddrOpnd = static_cast(HandleExpr(*iread, *iread->Opnd(0))); + rhsAddrOpnd = &LoadIntoRegister(*rhsAddrOpnd, iread->Opnd(0)->GetPrimType()); + MIRPtrType *ptrType = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(iread->GetTyIdx())); + MIRType *mirType = static_cast(ptrType->GetPointedType()); + bool isRefField = false; + if (iread->GetFieldID() != 0) { + MIRStructType *structType = static_cast(mirType); + mirType = structType->GetFieldType(iread->GetFieldID()); + offset = static_cast(GetBecommon().GetFieldOffset(*structType, iread->GetFieldID()).first); + isRefField = GetBecommon().IsRefField(*structType, iread->GetFieldID()); + } + uint32 typeSize = GetBecommon().GetTypeSize(mirType->GetTypeIndex()); + /* generate move to regs. */ + RegOperand *result[kTwoRegister]; /* maximum 16 bytes, 2 registers */ + uint32 loadSize; + if (CGOptions::IsBigEndian()) { + loadSize = k8ByteSize; + } else { + loadSize = (typeSize <= k4ByteSize) ? k4ByteSize : k8ByteSize; + } + uint32 numRegs = (typeSize <= k8ByteSize) ? kOneRegister : kTwoRegister; + for (uint32 i = 0; i < numRegs; i++) { + OfstOperand *rhsOffOpnd = &GetOrCreateOfstOpnd(offset + i * loadSize, loadSize * kBitsPerByte); + Operand &rhsmemopnd = GetOrCreateMemOpnd(MemOperand::kAddrModeBOi, loadSize * kBitsPerByte, + rhsAddrOpnd, nullptr, rhsOffOpnd, nullptr); + result[i] = &CreateVirtualRegisterOperand(NewVReg(kRegTyInt, loadSize)); + MOperator mop1 = PickLdInsn(loadSize * kBitsPerByte, PTY_u32); + Insn &ld = GetCG()->BuildInstruction(mop1, *(result[i]), rhsmemopnd); + ld.MarkAsAccessRefField(isRefField); + GetCurBB()->AppendInsn(ld); + } + RegOperand *dest; + for (uint32 i = 0; i < numRegs; i++) { + AArch64reg preg = (i == 0 ? R0 : R1); + dest = &GetOrCreatePhysicalRegisterOperand(preg, loadSize * kBitsPerByte, kRegTyInt); + Insn &mov = GetCG()->BuildInstruction(MOP_xmovrr, *dest, *(result[i])); + GetCurBB()->AppendInsn(mov); + } + /* Create artificial dependency to extend the live range */ + for (uint32 i = 0; i < numRegs; i++) { + AArch64reg preg = (i == 0 ? R0 : R1); + dest = &GetOrCreatePhysicalRegisterOperand(preg, loadSize * kBitsPerByte, kRegTyInt); + Insn &pseudo = cg->BuildInstruction(MOP_pseudo_ret_int, *dest); + GetCurBB()->AppendInsn(pseudo); + } + return; + } else { // dummy return of 0 inserted by front-end at absence of return + ASSERT(x->GetOpCode() == OP_constval, "SelectReturnSendOfStructInRegs: unexpected return operand"); + uint32 typeSize = GetPrimTypeSize(x->GetPrimType()); + RegOperand &dest = GetOrCreatePhysicalRegisterOperand(R0, typeSize * kBitsPerByte, kRegTyInt); + ImmOperand &src = CreateImmOperand(0, k16BitSize, false); + GetCurBB()->AppendInsn(GetCG()->BuildInstruction(MOP_xmovri32, dest, src)); + return; + } +} + Operand *AArch64CGFunc::SelectDread(const BaseNode &parent, DreadNode &expr) { MIRSymbol *symbol = GetFunction().GetLocalOrGlobalSymbol(expr.GetStIdx()); if (symbol->IsEhIndex()) { @@ -2917,31 +3176,50 @@ Operand *AArch64CGFunc::SelectIreadoff(const BaseNode &parent, IreadoffNode &ire return result; } -RegOperand *AArch64CGFunc::GenLmbcParamLoad(int32 offset, uint32 byteSize, RegType regType, PrimType primType) { - MemOperand *memOpnd; - RegOperand *rfp = &GetOrCreatePhysicalRegisterOperand(RFP, k64BitSize, kRegTyInt); - uint32 bitlen = byteSize * kBitsPerByte; - if (offset < 0) { - RegOperand *baseOpnd = &CreateRegisterOperandOfType(PTY_a64); - ImmOperand &immOpnd = CreateImmOperand(offset, k32BitSize, true); - Insn &addInsn = GetCG()->BuildInstruction(MOP_xaddrri12, *baseOpnd, *rfp, immOpnd); - GetCurBB()->AppendInsn(addInsn); - OfstOperand *offsetOpnd = &CreateOfstOpnd(0, k32BitSize); - memOpnd = &GetOrCreateMemOpnd(MemOperand::kAddrModeBOi, bitlen, baseOpnd, - nullptr, offsetOpnd, nullptr); - } else { - OfstOperand *offsetOpnd = &CreateOfstOpnd(offset, k32BitSize); - memOpnd = &GetOrCreateMemOpnd(MemOperand::kAddrModeBOi, bitlen, rfp, - nullptr, offsetOpnd, nullptr); - } - memOpnd->SetStackMem(true); +RegOperand *AArch64CGFunc::GenLmbcParamLoad(int32 offset, uint32 byteSize, RegType regType, PrimType primType, + AArch64reg baseRegno) { + MemOperand *memOpnd = GenLmbcFpMemOperand(offset, byteSize, baseRegno); RegOperand *result = &GetOrCreateVirtualRegisterOperand(NewVReg(regType, byteSize)); - MOperator mOp = PickLdInsn(bitlen, primType); + MOperator mOp = PickLdInsn(byteSize * kBitsPerByte, primType); Insn &load = GetCG()->BuildInstruction(mOp, *result, *memOpnd); GetCurBB()->AppendInsn(load); return result; } +RegOperand *AArch64CGFunc::LmbcStructReturnLoad(int32 offset) { + RegOperand *result = nullptr; + MIRFunction &func = GetFunction(); + CHECK_FATAL(func.IsReturnStruct(), "LmbcStructReturnLoad: not struct return"); + MIRType *ty = func.GetReturnType(); + uint32 sz = GetBecommon().GetTypeSize(ty->GetTypeIndex()); + uint32 fpSize; + uint32 numFpRegs = FloatParamRegRequired(static_cast(ty), fpSize); + if (numFpRegs > 0) { + PrimType pType = (fpSize <= k4ByteSize) ? PTY_f32 : PTY_f64; + for (int32 i = (numFpRegs - kOneRegister); i > 0; --i) { + result = GenLmbcParamLoad(offset + (i * fpSize), fpSize, kRegTyFloat, pType); + AArch64reg regNo = static_cast(V0 + i); + RegOperand *reg = &GetOrCreatePhysicalRegisterOperand(regNo, fpSize * kBitsPerByte, kRegTyFloat); + SelectCopy(*reg, pType, *result, pType); + Insn &pseudo = GetCG()->BuildInstruction(MOP_pseudo_ret_float, *reg); + GetCurBB()->AppendInsn(pseudo); + } + result = GenLmbcParamLoad(offset, fpSize, kRegTyFloat, pType); + } else if (sz <= k4ByteSize) { + result = GenLmbcParamLoad(offset, k4ByteSize, kRegTyInt, PTY_u32); + } else if (sz <= k8ByteSize) { + result = GenLmbcParamLoad(offset, k8ByteSize, kRegTyInt, PTY_i64); + } else if (sz <= k16ByteSize) { + result = GenLmbcParamLoad(offset + k8ByteSize, k8ByteSize, kRegTyInt, PTY_i64); + RegOperand *r1 = &GetOrCreatePhysicalRegisterOperand(R1, k8ByteSize * kBitsPerByte, kRegTyInt); + SelectCopy(*r1, PTY_i64, *result, PTY_i64); + Insn &pseudo = GetCG()->BuildInstruction(MOP_pseudo_ret_int, *r1); + GetCurBB()->AppendInsn(pseudo); + result = GenLmbcParamLoad(offset, k8ByteSize, kRegTyInt, PTY_i64); + } + return result; +} + Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff) { int32 offset = ireadoff.GetOffset(); PrimType primType = ireadoff.GetPrimType(); @@ -2952,19 +3230,32 @@ Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode if (offset >= 0) { LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(offset); if (info->GetPrimType() == PTY_agg) { - result = GenLmbcParamLoad(offset, bytelen, regty, primType); + if (info->IsOnStack()) { + result = GenLmbcParamLoad(info->GetOnStackOffset(), GetPrimTypeSize(PTY_a64), kRegTyInt, PTY_a64); + regno_t baseRegno = result->GetRegisterNumber(); + result = GenLmbcParamLoad(offset - info->GetOffset(), bytelen, regty, primType, (AArch64reg)baseRegno); + } else if (primType == PTY_agg) { + CHECK_FATAL(parent.GetOpCode() == OP_regassign, "SelectIreadfpoff of agg"); + result = LmbcStructReturnLoad(offset); + } else { + result = GenLmbcParamLoad(offset, bytelen, regty, primType); + } } else { CHECK_FATAL(primType == info->GetPrimType(), "Incorrect primtype"); CHECK_FATAL(offset == info->GetOffset(), "Incorrect offset"); - if (info->GetRegNO() == 0) { - /* TODO : follow lmbc sp offset for now */ + if (info->GetRegNO() == 0 || info->HasRegassign() == false) { result = GenLmbcParamLoad(offset, bytelen, regty, primType); } else { result = &GetOrCreatePhysicalRegisterOperand((AArch64reg)(info->GetRegNO()), bitlen, regty); } } } else { - result = GenLmbcParamLoad(offset, bytelen, regty, primType); + if (primType == PTY_agg) { + CHECK_FATAL(parent.GetOpCode() == OP_regassign, "SelectIreadfpoff of agg"); + result = LmbcStructReturnLoad(offset); + } else { + result = GenLmbcParamLoad(offset, bytelen, regty, primType); + } } return result; } @@ -5761,6 +6052,9 @@ Operand *AArch64CGFunc::SelectAlloca(UnaryNode &node, Operand &opnd0) { if (!CGOptions::IsArm64ilp32()) { ASSERT((node.GetPrimType() == PTY_a64), "wrong type"); } + if (GetCG()->IsLmbc()) { + SetHasVLAOrAlloca(true); + } PrimType stype = node.Opnd(0)->GetPrimType(); Operand *resOpnd = &opnd0; if (GetPrimTypeBitSize(stype) < GetPrimTypeBitSize(PTY_u64)) { @@ -5776,10 +6070,13 @@ Operand *AArch64CGFunc::SelectAlloca(UnaryNode &node, Operand &opnd0) { SelectShift(aliOp, aliOp, shifOpnd, kShiftLeft, PTY_u64); Operand &spOpnd = GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); SelectSub(spOpnd, spOpnd, aliOp, PTY_u64); - int64 argsToStkpassSize = GetMemlayout()->SizeOfArgsToStackPass(); - if (argsToStkpassSize > 0) { + int64 allocaOffset = GetMemlayout()->SizeOfArgsToStackPass(); + if (GetCG()->IsLmbc()) { + allocaOffset -= kDivide2 * k8ByteSize; + } + if (allocaOffset > 0) { RegOperand &resallo = CreateRegisterOperandOfType(PTY_u64); - SelectAdd(resallo, spOpnd, CreateImmOperand(argsToStkpassSize, k64BitSize, true), PTY_u64); + SelectAdd(resallo, spOpnd, CreateImmOperand(allocaOffset, k64BitSize, true), PTY_u64); return &resallo; } else { return &SelectCopy(spOpnd, PTY_u64, PTY_u64); @@ -6221,6 +6518,15 @@ void AArch64CGFunc::AssignLmbcFormalParams() { param->SetRegNO(0); } else { param->SetRegNO(intReg); + if (param->HasRegassign() == false) { + uint32 bytelen = GetPrimTypeSize(primType); + uint32 bitlen = bytelen * kBitsPerByte; + MemOperand *mOpnd = GenLmbcFpMemOperand(offset, bytelen); + RegOperand &src = GetOrCreatePhysicalRegisterOperand(AArch64reg(intReg), bitlen, kRegTyInt); + MOperator mOp = PickStInsn(bitlen, primType); + Insn &store = GetCG()->BuildInstruction(mOp, src, *mOpnd); + GetCurBB()->AppendInsn(store); + } intReg++; } } else if (IsPrimitiveFloat(primType)) { @@ -6228,6 +6534,15 @@ void AArch64CGFunc::AssignLmbcFormalParams() { param->SetRegNO(0); } else { param->SetRegNO(fpReg); + if (param->HasRegassign() == false) { + uint32 bytelen = GetPrimTypeSize(primType); + uint32 bitlen = bytelen * kBitsPerByte; + MemOperand *mOpnd = GenLmbcFpMemOperand(offset, bytelen); + RegOperand &src = GetOrCreatePhysicalRegisterOperand(AArch64reg(fpReg), bitlen, kRegTyFloat); + MOperator mOp = PickStInsn(bitlen, primType); + Insn &store = GetCG()->BuildInstruction(mOp, src, *mOpnd); + GetCurBB()->AppendInsn(store); + } fpReg++; } } else if (primType == PTY_agg) { @@ -6246,6 +6561,14 @@ void AArch64CGFunc::AssignLmbcFormalParams() { } else { param->SetRegNO(intReg); param->SetIsOnStack(); + param->SetOnStackOffset((intReg - R0 + fpReg - V0) * k8ByteSize); + uint32 bytelen = GetPrimTypeSize(PTY_a64); + uint32 bitlen = bytelen * kBitsPerByte; + MemOperand *mOpnd = GenLmbcFpMemOperand(param->GetOnStackOffset(), bytelen); + RegOperand &src = GetOrCreatePhysicalRegisterOperand(AArch64reg(intReg), bitlen, kRegTyInt); + MOperator mOp = PickStInsn(bitlen, PTY_a64); + Insn &store = GetCG()->BuildInstruction(mOp, src, *mOpnd); + GetCurBB()->AppendInsn(store); intReg++; } } else if (param->GetSize() <= k8ByteSize) { @@ -6291,7 +6614,6 @@ void AArch64CGFunc::AssignLmbcFormalParams() { Operand *memOpd = &CreateMemOpnd(RFP, offset + (i * rSize), rSize); GetCurBB()->AppendInsn(GetCG()->BuildInstruction( PickStInsn(rSize * kBitsPerByte, pType), dest, *memOpd)); - param->SetIsOnStack(); } } } else { @@ -6300,6 +6622,22 @@ void AArch64CGFunc::AssignLmbcFormalParams() { } } +void AArch64CGFunc::LmbcGenSaveSpForAlloca() { + if (GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc || HasVLAOrAlloca() == false) { + return; + } + Operand &spOpnd = GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); + RegOperand &spSaveOpnd = CreateVirtualRegisterOperand(NewVReg(kRegTyInt, kSizeOfPtr)); + Insn &save = GetCG()->BuildInstruction(MOP_xmovrr, spSaveOpnd, spOpnd); + GetFirstBB()->AppendInsn(save); + //save.SetFrameDef(true); + for (auto *retBB : GetExitBBsVec()) { + Insn &restore = GetCG()->BuildInstruction(MOP_xmovrr, spOpnd, spSaveOpnd); + retBB->AppendInsn(restore); + restore.SetFrameDef(true); + } +} + /* if offset < 0, allocation; otherwise, deallocation */ MemOperand &AArch64CGFunc::CreateCallFrameOperand(int32 offset, int32 size) { MemOperand *memOpnd = CreateStackMemOpnd(RSP, offset, size); @@ -7585,6 +7923,10 @@ size_t AArch64CGFunc::SelectParmListGetStructReturnSize(StmtNode &naryNode) { CallNode &callNode = static_cast(naryNode); MIRFunction *callFunc = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(callNode.GetPUIdx()); TyIdx retIdx = callFunc->GetReturnTyIdx(); + if (callFunc->IsFirstArgReturn()) { + MIRType *ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(callFunc->GetFormalDefVec()[0].formalTyIdx); + return GetBecommon().GetTypeSize(static_cast(ty)->GetPointedTyIdx()); + } size_t retSize = GetBecommon().GetTypeSize(retIdx.GetIdx()); if ((retSize == 0) && callFunc->IsReturnStruct()) { TyIdx tyIdx = callFunc->GetFuncRetStructTyIdx(); @@ -7601,6 +7943,14 @@ size_t AArch64CGFunc::SelectParmListGetStructReturnSize(StmtNode &naryNode) { return GetBecommon().GetTypeSize(sym->GetTyIdx().GetIdx()); } } + } else if (naryNode.GetOpCode() == OP_icallproto) { + IcallNode &icallProto = static_cast(naryNode); + MIRFuncType *funcTy = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallProto.GetRetTyIdx())); + if (funcTy->FirstArgReturn()) { + MIRType *ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(funcTy->GetNthParamType(0)); + return GetBecommon().GetTypeSize(static_cast(ty)->GetPointedTyIdx()); + } + return GetBecommon().GetTypeSize(funcTy->GetRetTyIdx()); } return 0; } @@ -7708,12 +8058,23 @@ void AArch64CGFunc::SelectParmListPreprocess(const StmtNode &naryNode, size_t st */ void AArch64CGFunc::SelectParmList(StmtNode &naryNode, ListOperand &srcOpnds, bool isCallNative) { size_t i = 0; - if ((naryNode.GetOpCode() == OP_icall) || isCallNative) { + if (naryNode.GetOpCode() == OP_icall || naryNode.GetOpCode() == OP_icallproto || isCallNative) { i++; } std::set specialArgs; SelectParmListPreprocess(naryNode, i, specialArgs); bool specialArg = false; + bool firstArgReturn = false; + MIRFunction *callee = nullptr; + if (dynamic_cast(&naryNode) != nullptr) { + auto calleePuIdx = static_cast(naryNode).GetPUIdx(); + callee = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(calleePuIdx); + firstArgReturn = callee->IsFirstArgReturn(); + } else if (naryNode.GetOpCode() == OP_icallproto) { + IcallNode *icallnode = &static_cast(naryNode); + MIRFuncType *funcType = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallnode->GetRetTyIdx())); + firstArgReturn = funcType->FirstArgReturn(); + } BB *curBBrecord = GetCurBB(); BB *tmpBB = nullptr; if (!specialArgs.empty()) { @@ -7735,8 +8096,6 @@ void AArch64CGFunc::SelectParmList(StmtNode &naryNode, ListOperand &srcOpnds, bo BaseNode *argExpr = naryNode.Opnd(i); PrimType primType = argExpr->GetPrimType(); ASSERT(primType != PTY_void, "primType should not be void"); - auto calleePuIdx = static_cast(naryNode).GetPUIdx(); - auto *callee = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(calleePuIdx); if (callee != nullptr && pnum < callee->GetFormalCount() && callee->GetFormal(pnum) != nullptr) { is64x1vec = callee->GetFormal(pnum)->GetAttr(ATTR_oneelem_simd); } @@ -7801,7 +8160,7 @@ void AArch64CGFunc::SelectParmList(StmtNode &naryNode, ListOperand &srcOpnds, bo } expRegOpnd = static_cast(opnd); - if ((pnum == 0) && (SelectParmListGetStructReturnSize(naryNode) > k16ByteSize)) { + if ((pnum == 0) && firstArgReturn) { parmLocator.InitCCLocInfo(ploc); ploc.reg0 = R8; } else { @@ -8259,7 +8618,18 @@ void AArch64CGFunc::SelectCall(CallNode &callNode) { ListOperand *srcOpnds = CreateListOpnd(*GetFuncScopeAllocator()); if (GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { - LmbcSelectParmList(srcOpnds, fn->IsFirstArgReturn()); + SetLmbcCallReturnType(nullptr); + bool largeStructRet = false; + if (fn->IsFirstArgReturn()) { + MIRPtrType *ptrTy = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(fn->GetFormalDefVec()[0].formalTyIdx)); + MIRType *sTy = GlobalTables::GetTypeTable().GetTypeFromTyIdx(ptrTy->GetPointedTyIdx()); + largeStructRet = sTy->GetSize() > k16ByteSize; + SetLmbcCallReturnType(sTy); + } else { + MIRType *ty = fn->GetReturnType(); + SetLmbcCallReturnType(ty); + } + LmbcSelectParmList(srcOpnds, largeStructRet); } bool callNative = false; if ((fsym->GetName() == "MCC_CallFastNative") || (fsym->GetName() == "MCC_CallFastNativeExt") || @@ -8335,11 +8705,21 @@ void AArch64CGFunc::SelectCall(CallNode &callNode) { void AArch64CGFunc::SelectIcall(IcallNode &icallNode, Operand &srcOpnd) { ListOperand *srcOpnds = CreateListOpnd(*GetFuncScopeAllocator()); - if (GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { - LmbcSelectParmList(srcOpnds, false /*fType->GetRetAttrs().GetAttr(ATTR_firstarg_return)*/); - } else { +// if (GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { +// /* icallproto */ +// MIRType *retTy = GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallNode.GetRetTyIdx()); +// MIRFuncType *funcTy = static_cast(retTy); +// bool largeStructRet = false; +// if (funcTy->FirstArgReturn()) { +// TyIdx idx = funcTy->GetNthParamType(0); +// MIRPtrType *ptrTy = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(idx)); +// MIRType *sTy = GlobalTables::GetTypeTable().GetTypeFromTyIdx(ptrTy->GetPointedTyIdx()); +// largeStructRet = sTy->GetSize() > k16ByteSize; +// } +// LmbcSelectParmList(srcOpnds, largeStructRet); +// } else { SelectParmList(icallNode, *srcOpnds); - } +// } Operand *fptrOpnd = &srcOpnd; if (fptrOpnd->GetKind() != Operand::kOpdRegister) { @@ -8350,7 +8730,7 @@ void AArch64CGFunc::SelectIcall(IcallNode &icallNode, Operand &srcOpnd) { RegOperand *regOpnd = static_cast(fptrOpnd); Insn &callInsn = GetCG()->BuildInstruction(MOP_xblr, *regOpnd, *srcOpnds); - MIRType *retType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallNode.GetRetTyIdx()); + MIRType *retType = icallNode.GetCallReturnType(); if (retType != nullptr) { callInsn.SetRetSize(static_cast(retType->GetSize())); callInsn.SetIsCallReturnUnsigned(IsUnsignedInteger(retType->GetPrimType())); @@ -8463,9 +8843,18 @@ RegOperand &AArch64CGFunc::GetOrCreateSpecialRegisterOperand(PregIdx sregIdx, Pr case kSregFp: reg = RFP; break; - case kSregGp: - reg = RFP; - break; + case kSregGp: { + MIRSymbol *sym = GetCG()->GetGP(); + if (sym == nullptr) { + sym = GetFunction().GetSymTab()->CreateSymbol(kScopeLocal); + std::string strBuf("__file__local__GP"); + sym->SetNameStrIdx(GetMirModule().GetMIRBuilder()->GetOrCreateStringIndex(strBuf)); + GetCG()->SetGP(sym); + } + RegOperand &result = GetOrCreateVirtualRegisterOperand(NewVReg(kRegTyInt, k8ByteSize)); + SelectAddrof(result, CreateStImmOperand(*sym, 0, 0)); + return result; + } case kSregThrownval: { /* uses x0 == R0 */ ASSERT(uCatch.regNOCatch > 0, "regNOCatch should greater than 0."); if (Globals::GetInstance()->GetOptimLevel() == 0) { @@ -9202,6 +9591,9 @@ int32 AArch64CGFunc::GetBaseOffset(const SymbolAlloc &sa) { int32 baseOffset = symAlloc->GetOffset(); return baseOffset + sizeofFplr; } else if (sgKind == kMsSpillReg) { + if (GetCG()->IsLmbc()) { + return symAlloc->GetOffset() + memLayout->SizeOfArgsToStackPass(); + } int32 baseOffset = symAlloc->GetOffset() + memLayout->SizeOfArgsRegisterPassed() + memLayout->GetSizeOfLocals() + memLayout->GetSizeOfRefLocals(); return baseOffset + sizeofFplr; @@ -9776,16 +10168,21 @@ void AArch64CGFunc::GenCVaStartIntrin(RegOperand &opnd, uint32 stkSize) { Operand &stkOpnd = GetOrCreatePhysicalRegisterOperand(RFP, k64BitSize, kRegTyInt); /* __stack */ - ImmOperand *offsOpnd = &CreateImmOperand(0, k64BitSize, true, kUnAdjustVary); /* isvary reset StackFrameSize */ + ImmOperand *offsOpnd; + if (GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { + offsOpnd = &CreateImmOperand(0, k64BitSize, true, kUnAdjustVary); /* isvary reset StackFrameSize */ + } else { + offsOpnd = &CreateImmOperand(0, k64BitSize, true); + } ImmOperand *offsOpnd2 = &CreateImmOperand(stkSize, k64BitSize, false); RegOperand &vReg = CreateVirtualRegisterOperand(NewVReg(kRegTyInt, GetPrimTypeSize(LOWERED_PTR_TYPE))); if (stkSize) { SelectAdd(vReg, *offsOpnd, *offsOpnd2, LOWERED_PTR_TYPE); SelectAdd(vReg, stkOpnd, vReg, LOWERED_PTR_TYPE); } else { - SelectAdd(vReg, stkOpnd, *offsOpnd, LOWERED_PTR_TYPE); + SelectAdd(vReg, stkOpnd, *offsOpnd, LOWERED_PTR_TYPE); /* stack pointer */ } - OfstOperand *offOpnd = &GetOrCreateOfstOpnd(0, k64BitSize); + OfstOperand *offOpnd = &GetOrCreateOfstOpnd(0, k64BitSize); /* va_list ptr */ /* mem operand in va_list struct (lhs) */ MemOperand *strOpnd = &GetOrCreateMemOpnd(MemOperand::kAddrModeBOi, k64BitSize, &opnd, nullptr, offOpnd, static_cast(nullptr)); @@ -9860,13 +10257,19 @@ void AArch64CGFunc::SelectCVaStart(const IntrinsiccallNode &intrnNode) { AArch64CallConvImpl parmLocator(GetBecommon()); CCLocInfo pLoc; uint32 stkSize = 0; + uint32 inReg = 0; for (uint32 i = 0; i < GetFunction().GetFormalCount(); i++) { MIRType *ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(GetFunction().GetNthParamTyIdx(i)); parmLocator.LocateNextParm(*ty, pLoc); if (pLoc.reg0 == kRinvalid) { /* on stack */ stkSize = static_cast(pLoc.memOffset + pLoc.memSize); + } else { + inReg++; } } + if (GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { + stkSize += (inReg * k8ByteSize); + } if (CGOptions::IsArm64ilp32()) { stkSize = static_cast(RoundUp(stkSize, k8ByteSize)); } else { diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp index 3b878b6c7a..1ed5f1480a 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp @@ -3629,6 +3629,9 @@ RegOperand *GraphColorRegAllocator::GetReplaceOpnd(Insn &insn, const Operand &op auto ®Opnd = static_cast(opnd); uint32 vregNO = regOpnd.GetRegisterNumber(); + if (vregNO == RFP) { + seenFP = true; + } RegType regType = regOpnd.GetRegisterType(); if (vregNO < kAllRegNum) { return nullptr; @@ -4996,6 +4999,9 @@ bool GraphColorRegAllocator::AllocateRegisters() { MarkCalleeSaveRegs(); + if (seenFP == false) { + cgFunc->UnsetSeenFP(); + } if (GCRA_DUMP) { cgFunc->DumpCGIR(); } diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp index 5716509ad6..433aeeee3a 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp @@ -40,8 +40,8 @@ constexpr uint8 insPairsNum = 5; PairMOperator extInsnPairTable[ExtTableSize][insPairsNum] = { /* {origMop, newMop} */ - {{MOP_wldrb, MOP_wldrb}, {MOP_undef, MOP_undef}, {MOP_undef, MOP_undef}, {MOP_undef, MOP_undef}, - {MOP_undef, MOP_undef}}, /* AND */ + {{MOP_wldrb, MOP_wldrb}, {MOP_wldrsh, MOP_wldrb}, {MOP_wldrh, MOP_wldrb}, {MOP_xldrsw, MOP_wldrb}, + {MOP_wldr, MOP_wldrb}}, /* AND */ {{MOP_wldrb, MOP_wldrsb}, {MOP_wldr, MOP_wldrsb}, {MOP_undef, MOP_undef}, {MOP_undef, MOP_undef}, {MOP_undef, MOP_undef}}, /* SXTB */ {{MOP_wldrh, MOP_wldrsh}, {MOP_wldrb, MOP_wldrb}, {MOP_wldrsb, MOP_wldrsb}, {MOP_wldrsh, MOP_wldrsh}, diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index 5f2b7f37ba..bf888d5d3b 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -134,7 +134,7 @@ void AArch64MemLayout::LayoutVarargParams() { if (be.GetMIRModule().IsCModule() && func->GetAttr(FUNCATTR_varargs)) { for (uint32 i = 0; i < func->GetFormalCount(); i++) { if (i == 0) { - if (func->IsReturnStruct()) { + if (func->IsFirstArgReturn() && func->GetReturnType()->GetPrimType() != PTY_void) { TyIdx tyIdx = func->GetFuncRetStructTyIdx(); if (be.GetTypeSize(tyIdx.GetIdx()) <= k16ByteSize) { continue; @@ -198,7 +198,7 @@ void AArch64MemLayout::LayoutFormalParams() { * outparmsize - portion of frame size of current function used by call parameters */ segArgsStkPassed.SetSize(mirFunction->GetOutParmSize()); - segArgsRegPassed.SetSize(mirFunction->GetOutParmSize() + kTwoRegister * k8ByteSize); + segArgsRegPassed.SetSize(mirFunction->GetOutParmSize()); return; } @@ -210,7 +210,7 @@ void AArch64MemLayout::LayoutFormalParams() { AArch64SymbolAlloc *symLoc = memAllocator->GetMemPool()->New(); SetSymAllocInfo(stIndex, *symLoc); if (i == 0) { - if (mirFunction->IsReturnStruct()) { + if (mirFunction->IsReturnStruct() && mirFunction->IsFirstArgReturn()) { symLoc->SetMemSegment(GetSegArgsRegPassed()); symLoc->SetOffset(GetSegArgsRegPassed().GetSize()); TyIdx tyIdx = mirFunction->GetFuncRetStructTyIdx(); @@ -224,13 +224,13 @@ void AArch64MemLayout::LayoutFormalParams() { continue; } } - MIRType *ty = mirFunction->GetNthParamType(i); + MIRType *ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(mirFunction->GetFormalDefVec()[i].formalTyIdx); uint32 ptyIdx = ty->GetTypeIndex(); parmLocator.LocateNextParm(*ty, ploc, i == 0, mirFunction); if (ploc.reg0 != kRinvalid) { /* register */ symLoc->SetRegisters(static_cast(ploc.reg0), static_cast(ploc.reg1), static_cast(ploc.reg2), static_cast(ploc.reg3)); - if (mirFunction->GetNthParamAttr(i).GetAttr(ATTR_localrefvar)) { + if (mirFunction->GetFormalDefVec()[i].formalAttrs.GetAttr(ATTR_localrefvar)) { symLoc->SetMemSegment(segRefLocals); SetSegmentSize(*symLoc, segRefLocals, ptyIdx); } else if (!sym->IsPreg()) { @@ -272,7 +272,7 @@ void AArch64MemLayout::LayoutFormalParams() { } else { segArgsStkPassed.SetSize(static_cast(RoundUp(segArgsStkPassed.GetSize(), kSizeOfPtr))); } - if (mirFunction->GetNthParamAttr(i).GetAttr(ATTR_localrefvar)) { + if (mirFunction->GetFormalDefVec()[i].formalAttrs.GetAttr(ATTR_localrefvar)) { SetLocalRegLocInfo(sym->GetStIdx(), *symLoc); AArch64SymbolAlloc *symLoc1 = memAllocator->GetMemPool()->New(); symLoc1->SetMemSegment(segRefLocals); @@ -287,7 +287,7 @@ void AArch64MemLayout::LayoutFormalParams() { } void AArch64MemLayout::LayoutLocalVariables(std::vector &tempVar, std::vector &returnDelays) { - if (be.GetMIRModule().GetFlavor() == kFlavorLmbc && mirFunction->GetFormalCount() == 0) { + if (be.GetMIRModule().GetFlavor() == kFlavorLmbc) { segLocals.SetSize(mirFunction->GetFrameSize() - mirFunction->GetOutParmSize()); return; } @@ -372,7 +372,7 @@ void AArch64MemLayout::LayoutReturnRef(std::vector &returnDelays, segRefLocals.SetSize(segRefLocals.GetSize() + be.GetTypeSize(tyIdx)); } if (be.GetMIRModule().GetFlavor() == kFlavorLmbc) { - segArgsToStkPass.SetSize(mirFunction->GetOutParmSize()); + segArgsToStkPass.SetSize(mirFunction->GetOutParmSize() + kDivide2 * k8ByteSize); } else { segArgsToStkPass.SetSize(FindLargestActualArea(structCopySize)); } @@ -395,7 +395,7 @@ void AArch64MemLayout::LayoutReturnRef(std::vector &returnDelays, void AArch64MemLayout::LayoutActualParams() { for (size_t i = 0; i < mirFunction->GetFormalCount(); ++i) { if (i == 0) { - if (mirFunction->IsReturnStruct()) { + if (mirFunction->IsReturnStruct() && mirFunction->IsFirstArgReturn()) { continue; } } @@ -423,7 +423,7 @@ void AArch64MemLayout::LayoutActualParams() { * variables get assigned their respecitve storage, i.e. * CallFrameSize (discounting callee-saved and FP/LR) is known. */ - MIRType *ty = mirFunction->GetNthParamType(i); + MIRType *ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(mirFunction->GetFormalDefVec()[i].formalTyIdx); uint32 ptyIdx = ty->GetTypeIndex(); static_cast(cgFunc)->GetOrCreateMemOpnd(*sym, 0, be.GetTypeAlign(ptyIdx) * kBitsPerByte); } @@ -440,7 +440,7 @@ void AArch64MemLayout::LayoutStackFrame(int32 &structCopySize, int32 &maxParmSta */ if (CGOptions::IsArm64ilp32()) { segArgsRegPassed.SetSize(RoundUp(segArgsRegPassed.GetSize(), k8ByteSize)); - /* we do need this as SP has to be aligned at a 16-bytes bounardy */ + /* we do need this as SP has to be aligned at a 16-bytes bounardy */ segArgsStkPassed.SetSize(RoundUp(segArgsStkPassed.GetSize(), k8ByteSize + k8ByteSize)); } else { segArgsRegPassed.SetSize(RoundUp(segArgsRegPassed.GetSize(), kSizeOfPtr)); @@ -527,11 +527,13 @@ uint64 AArch64MemLayout::StackFrameSize() const { uint64 total = segArgsRegPassed.GetSize() + static_cast(cgFunc)->SizeOfCalleeSaved() + GetSizeOfRefLocals() + locals().GetSize() + GetSizeOfSpillReg(); - if (GetSizeOfGRSaveArea() > 0) { - total += RoundUp(GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); - } - if (GetSizeOfVRSaveArea() > 0) { - total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); + if (cgFunc->GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { + if (GetSizeOfGRSaveArea() > 0) { + total += RoundUp(GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); + } + if (GetSizeOfVRSaveArea() > 0) { + total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); + } } /* diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_offset_adjust.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_offset_adjust.cpp index eaa5726d43..7ef7190645 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_offset_adjust.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_offset_adjust.cpp @@ -50,7 +50,7 @@ void AArch64FPLROffsetAdjustment::AdjustmentOffsetForOpnd(Insn &insn, AArch64CGF if (memBaseReg->GetRegisterNumber() == RFP) { RegOperand &newBaseOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); MemOperand &newMemOpnd = aarchCGFunc.GetOrCreateMemOpnd( - MemOperand::kAddrModeBOi, memOpnd.GetSize(), &newBaseOpnd, memOpnd.GetIndexRegister(), + memOpnd.GetAddrMode(), memOpnd.GetSize(), &newBaseOpnd, memOpnd.GetIndexRegister(), memOpnd.GetOffsetImmediate(), memOpnd.GetSymbol()); insn.SetOperand(i, newMemOpnd); stackBaseOpnd = true; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 8ea922dac1..7e6a33f401 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -185,9 +185,6 @@ void AArch64GenProEpilog::TailCallBBOpt(BB &bb, MapleSet &callInsns, BB & * Return value: true if function do not need Prologue/Epilogue. false otherwise. */ bool AArch64GenProEpilog::TailCallOpt() { - if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { - return false; - } /* Count how many call insns in the whole function. */ uint32 nCount = 0; bool hasGetStackClass = false; @@ -1118,6 +1115,9 @@ void AArch64GenProEpilog::AppendInstructionAllocateCallFrameDebug(AArch64reg reg ipoint = cgFunc.GetCurBB()->GetLastInsn(); cfiOffset = stackFrameSize; (void)InsertCFIDefCfaOffset(cfiOffset, *ipoint); + if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { + argsToStkPassSize -= (kDivide2 * k8ByteSize); + } ipoint = &CreateAndAppendInstructionForAllocateCallFrame(argsToStkPassSize, reg0, reg1, rty); CHECK_FATAL(ipoint != nullptr, "ipoint should not be nullptr at this point"); cfiOffset = GetOffsetFromCFA(); @@ -1226,7 +1226,9 @@ void AArch64GenProEpilog::GeneratePushRegs() { } else { immOpnd = &aarchCGFunc.CreateImmOperand(argsToStkPassSize, k32BitSize, true); } - aarchCGFunc.SelectAdd(fpOpnd, spOpnd, *immOpnd, PTY_u64); + if (isLmbc == false || cgFunc.SeenFP() || cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + aarchCGFunc.SelectAdd(fpOpnd, spOpnd, *immOpnd, PTY_u64); + } cgFunc.GetCurBB()->GetLastInsn()->SetFrameDef(true); if (cgFunc.GenCfi()) { cgFunc.GetCurBB()->AppendInsn(aarchCGFunc.CreateCfiDefCfaInsn(stackBaseReg, @@ -1251,9 +1253,16 @@ void AArch64GenProEpilog::GeneratePushRegs() { CHECK_FATAL(*it == RLR, "The second callee saved reg is expected to be RLR"); ++it; - auto offset = static_cast(static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - - cgFunc.GetMemlayout()->SizeOfArgsToStackPass()); + AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); + int32 offset; + if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { + offset = static_cast(memLayout->RealStackFrameSize() - + aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); + } else { + offset = static_cast(memLayout->RealStackFrameSize() - + (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - + memLayout->SizeOfArgsToStackPass()); + } if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= static_cast(kAarch64StackPtrAlignment); @@ -1313,10 +1322,19 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { size = kSizeOfPtr; } uint32 dataSizeBits = size * kBitsPerByte; - uint32 offset = static_cast(memlayout->GetGRSaveAreaBaseLoc()); - if (memlayout->GetSizeOfGRSaveArea() % kAarch64StackPtrAlignment) { - offset += size; /* End of area should be aligned. Hole between VR and GR area */ + uint32 offset; + if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { + offset = static_cast(memlayout->GetGRSaveAreaBaseLoc()); /* SP reference */ + if (memlayout->GetSizeOfGRSaveArea() % kAarch64StackPtrAlignment) { + offset += size; /* End of area should be aligned. Hole between VR and GR area */ + } + } else { + offset = -memlayout->GetSizeOfGRSaveArea(); /* FP reference */ + if (memlayout->GetSizeOfGRSaveArea() % kAarch64StackPtrAlignment) { + offset -= size; + } } + uint32 grSize = -offset; uint32 start_regno = k8BitSize - (memlayout->GetSizeOfGRSaveArea() / size); ASSERT(start_regno <= k8BitSize, "Incorrect starting GR regno for GR Save Area"); for (uint32 i = start_regno + static_cast(R0); i < static_cast(R8); i++) { @@ -1326,16 +1344,25 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { tmpOffset += 8U - (dataSizeBits >> 3); } } - Operand &stackloc = aarchCGFunc.CreateStkTopOpnd(offset + tmpOffset, dataSizeBits); + Operand *stackLoc; + if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { + stackLoc = &aarchCGFunc.CreateStkTopOpnd(offset + tmpOffset, dataSizeBits); + } else { + stackLoc = aarchCGFunc.GenLmbcFpMemOperand(offset, size); + } RegOperand ® = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(static_cast(i), k64BitSize, kRegTyInt); Insn &inst = - currCG->BuildInstruction(aarchCGFunc.PickStInsn(dataSizeBits, PTY_i64), reg, stackloc); + currCG->BuildInstruction(aarchCGFunc.PickStInsn(dataSizeBits, PTY_i64), reg, *stackLoc); cgFunc.GetCurBB()->AppendInsn(inst); offset += size; } if (!CGOptions::UseGeneralRegOnly()) { - offset = static_cast(memlayout->GetVRSaveAreaBaseLoc()); + if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { + offset = static_cast(memlayout->GetVRSaveAreaBaseLoc()); + } else { + offset = -(memlayout->GetSizeOfVRSaveArea() + grSize); + } start_regno = k8BitSize - (memlayout->GetSizeOfVRSaveArea() / (size * k2BitSize)); ASSERT(start_regno <= k8BitSize, "Incorrect starting GR regno for VR Save Area"); for (uint32 i = start_regno + static_cast(V0); i < static_cast(V8); i++) { @@ -1345,11 +1372,16 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { tmpOffset += 16U - (dataSizeBits >> 3); } } - Operand &stackloc = aarchCGFunc.CreateStkTopOpnd(offset + tmpOffset, dataSizeBits); + Operand *stackLoc; + if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { + stackLoc = &aarchCGFunc.CreateStkTopOpnd(offset + tmpOffset, dataSizeBits); + } else { + stackLoc = aarchCGFunc.GenLmbcFpMemOperand(offset, size); + } RegOperand ® = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(static_cast(i), k64BitSize, kRegTyFloat); Insn &inst = - currCG->BuildInstruction(aarchCGFunc.PickStInsn(dataSizeBits, PTY_f64), reg, stackloc); + currCG->BuildInstruction(aarchCGFunc.PickStInsn(dataSizeBits, PTY_f64), reg, *stackLoc); cgFunc.GetCurBB()->AppendInsn(inst); offset += (size * k2BitSize); } @@ -1389,7 +1421,8 @@ void AArch64GenProEpilog::GenerateProlog(BB &bb) { } // insert .loc for function - if (currCG->GetCGOptions().WithLoc()) { + if (currCG->GetCGOptions().WithLoc() && + (!currCG->GetMIRModule()->IsCModule() || currCG->GetMIRModule()->IsWithDbgInfo())) { MIRFunction *func = &cgFunc.GetFunction(); MIRSymbol *fSym = GlobalTables::GetGsymTable().GetSymbolFromStidx(func->GetStIdx().Idx()); if (currCG->GetCGOptions().WithSrc()) { @@ -1649,11 +1682,17 @@ void AArch64GenProEpilog::AppendInstructionDeallocateCallFrameDebug(AArch64reg r * ldp/stp's imm should be within -512 and 504; * if ldp's imm > 504, we fall back to the ldp-add version */ - if (cgFunc.HasVLAOrAlloca() || argsToStkPassSize == 0) { - stackFrameSize -= argsToStkPassSize; - if (stackFrameSize > kStpLdpImm64UpperBound) { + bool isLmbc = (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc); + if (cgFunc.HasVLAOrAlloca() || argsToStkPassSize == 0 || isLmbc) { + int lmbcOffset = 0; + if (isLmbc == false) { + stackFrameSize -= argsToStkPassSize; + } else { + lmbcOffset = argsToStkPassSize - (kDivide2 * k8ByteSize); + } + if (stackFrameSize > kStpLdpImm64UpperBound || isLmbc) { Operand *o2; - o2 = aarchCGFunc.CreateStackMemOpnd(RSP, 0, kSizeOfPtr * kBitsPerByte); + o2 = aarchCGFunc.CreateStackMemOpnd(RSP, (isLmbc ? lmbcOffset : 0), kSizeOfPtr * kBitsPerByte); Insn &deallocInsn = currCG->BuildInstruction(mOp, o0, o1, *o2); cgFunc.GetCurBB()->AppendInsn(deallocInsn); if (cgFunc.GenCfi()) { @@ -1728,9 +1767,16 @@ void AArch64GenProEpilog::GeneratePopRegs() { CHECK_FATAL(*it == RLR, "The second callee saved reg is expected to be RLR"); ++it; - int32 offset = static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - - cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); + AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); + int32 offset; + if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { + offset = static_cast(memLayout->RealStackFrameSize() - + aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); + } else { + offset = static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - + (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - + memLayout->SizeOfArgsToStackPass(); + } if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= static_cast(kAarch64StackPtrAlignment); @@ -1821,7 +1867,7 @@ void AArch64GenProEpilog::GenerateEpilog(BB &bb) { Operand &spOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); - if (cgFunc.HasVLAOrAlloca()) { + if (cgFunc.HasVLAOrAlloca() && cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { aarchCGFunc.SelectCopy(spOpnd, PTY_u64, fpOpnd, PTY_u64); } diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp index 433cc85754..5ca154b1aa 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp @@ -161,8 +161,7 @@ void AArch64ReachingDefinition::AddRetPseudoInsn(BB &bb) { Insn &retInsn = cgFunc->GetCG()->BuildInstruction(MOP_pseudo_ret_int, regOpnd); bb.AppendInsn(retInsn); pseudoInsns.emplace_back(&retInsn); - } else { - ASSERT(regNO == V0, "CG internal error. Return value should be R0 or V0."); + } else if (regNO == V0) { RegOperand ®Opnd = static_cast(cgFunc)->GetOrCreatePhysicalRegisterOperand(regNO, k64BitSize, kRegTyFloat); Insn &retInsn = cgFunc->GetCG()->BuildInstruction(MOP_pseudo_ret_float, regOpnd); diff --git a/src/mapleall/maple_be/src/cg/cg_phasemanager.cpp b/src/mapleall/maple_be/src/cg/cg_phasemanager.cpp index d2ae2c25c9..bf645c15cd 100644 --- a/src/mapleall/maple_be/src/cg/cg_phasemanager.cpp +++ b/src/mapleall/maple_be/src/cg/cg_phasemanager.cpp @@ -160,6 +160,7 @@ void RecursiveMarkUsedStaticSymbol(const BaseNode *baseNode) { break; } case OP_addrof: + case OP_addrofoff: case OP_dread: { const AddrofNode *dreadNode = static_cast(baseNode); MarkUsedStaticSymbol(dreadNode->GetStIdx()); diff --git a/src/mapleall/maple_be/src/cg/cgfunc.cpp b/src/mapleall/maple_be/src/cg/cgfunc.cpp index 0964af1809..4fb7db62c8 100644 --- a/src/mapleall/maple_be/src/cg/cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/cgfunc.cpp @@ -1146,7 +1146,11 @@ void HandleReturn(StmtNode &stmt, CGFunc &cgFunc) { ASSERT(retNode.NumOpnds() <= 1, "NYI return nodes number > 1"); Operand *opnd = nullptr; if (retNode.NumOpnds() != 0) { - opnd = cgFunc.HandleExpr(retNode, *retNode.Opnd(0)); + if (!cgFunc.GetFunction().StructReturnedInRegs()) { + opnd = cgFunc.HandleExpr(retNode, *retNode.Opnd(0)); + } else { + cgFunc.SelectReturnSendOfStructInRegs(retNode.Opnd(0)); + } } cgFunc.SelectReturn(opnd); cgFunc.SetCurBBKind(BB::kBBReturn); @@ -1562,14 +1566,15 @@ void CGFunc::CreateLmbcFormalParamInfo() { uint32 offset; uint32 typeSize; MIRFunction &func = GetFunction(); - if (func.GetParamSize() > 0) { + if (func.GetFormalCount() > 0) { + /* Whenever lmbc cannot delete call type info, the prototype is available */ uint32 stackOffset = 0; - for (size_t idx = 0; idx < func.GetParamSize(); ++idx) { + for (size_t idx = 0; idx < func.GetFormalCount(); ++idx) { MIRSymbol *sym = func.GetFormal(idx); MIRType *type; TyIdx tyIdx; if (sym) { - tyIdx = func.GetNthParamTyIdx(idx); + tyIdx = func.GetFormalDefVec()[idx].formalTyIdx; type = GlobalTables::GetTypeTable().GetTypeFromTyIdx(tyIdx); } else { FormalDef vec = const_cast(GetBecommon().GetMIRModule().CurFunction())->GetFormalDefAt(idx); @@ -1616,6 +1621,9 @@ void CGFunc::CreateLmbcFormalParamInfo() { } IreadFPoffNode *ireadNode = static_cast(operand); primType = ireadNode->GetPrimType(); + if (ireadNode->GetOffset() < 0) { + continue; + } offset = static_cast(ireadNode->GetOffset()); typeSize = GetPrimTypeSize(primType); CHECK_FATAL((offset % k8ByteSize) == 0, ""); /* scalar only, no struct for now */ @@ -1627,6 +1635,31 @@ void CGFunc::CreateLmbcFormalParamInfo() { [] (LmbcFormalParamInfo *x, LmbcFormalParamInfo *y) { return x->GetOffset() < y->GetOffset(); } ); + + /* When a scalar param address is taken, its regassign is not in the 1st block */ + for (StmtNode *stmt = func.GetBody()->GetFirst(); stmt != nullptr; stmt = stmt->GetNext()) { + if (stmt == nullptr) { + break; + } + if (stmt->GetOpCode() == OP_label) { + continue; + } + if (stmt->GetOpCode() != OP_regassign) { + break; + } + RegassignNode *regAssignNode = static_cast(stmt); + BaseNode *operand = regAssignNode->Opnd(0); + if (operand->GetOpCode() != OP_ireadfpoff) { + break; + } + IreadFPoffNode *ireadNode = static_cast(operand); + if (ireadNode->GetOffset() < 0) { + continue; + } + LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(ireadNode->GetOffset()); + info->SetHasRegassign(); + } + AssignLmbcFormalParams(); } @@ -1635,7 +1668,7 @@ void CGFunc::GenerateInstruction() { InitHandleStmtFactory(); StmtNode *secondStmt = HandleFirstStmt(); - CreateLmbcFormalParamInfo(); + //CreateLmbcFormalParamInfo(); /* First Pass: Creates the doubly-linked list of BBs (next,prev) */ volReleaseInsn = nullptr; unsigned lastSrcLoc = 0; @@ -2006,6 +2039,7 @@ void CGFunc::HandleFunction() { ASSERT(exitBBVec.size() <= 1, "there are more than one BB_return in func"); } ProcessExitBBVec(); + LmbcGenSaveSpForAlloca(); if (func.IsJava()) { GenerateCleanupCodeForExtEpilog(*cleanupBB); diff --git a/src/mapleall/maple_be/src/cg/emit.cpp b/src/mapleall/maple_be/src/cg/emit.cpp index 37112f6cfb..bde5d4d383 100644 --- a/src/mapleall/maple_be/src/cg/emit.cpp +++ b/src/mapleall/maple_be/src/cg/emit.cpp @@ -2169,6 +2169,11 @@ void Emitter::EmitGlobalVar(const MIRSymbol &globalVar) { } void Emitter::EmitGlobalVars(std::vector> &globalVars) { + if (GetCG()->IsLmbc() && GetCG()->GetGP() != nullptr) { + Emit(asmInfo->GetLocal()).Emit("\t").Emit(GetCG()->GetGP()->GetName()).Emit("\n"); + Emit(asmInfo->GetComm()).Emit("\t").Emit(GetCG()->GetGP()->GetName()); + Emit(", ").Emit(GetCG()->GetMIRModule()->GetGlobalMemSize()).Emit(", ").Emit("8\n"); + } /* load globalVars profile */ if (globalVars.empty()) { return; diff --git a/src/mapleall/maple_be/src/cg/memlayout.cpp b/src/mapleall/maple_be/src/cg/memlayout.cpp index 57e45e8a2d..1b636207c6 100644 --- a/src/mapleall/maple_be/src/cg/memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/memlayout.cpp @@ -38,7 +38,7 @@ uint32 MemLayout::FindLargestActualArea(int32 &aggCopySize) { uint32 maxCopyStackSize = 0; // Size of aggregate param stack copy requirement for (; stmt != nullptr; stmt = stmt->GetNext()) { Opcode opCode = stmt->GetOpCode(); - if (opCode < OP_call || opCode > OP_xintrinsiccallassigned) { + if ((opCode < OP_call || opCode > OP_xintrinsiccallassigned) && opCode != OP_icallproto) { continue; } if (opCode == OP_intrinsiccallwithtypeassigned || opCode == OP_intrinsiccallwithtype || @@ -54,9 +54,9 @@ uint32 MemLayout::FindLargestActualArea(int32 &aggCopySize) { * if the following check fails, most likely dex has invoke-custom etc * that is not supported yet */ - DCHECK((opCode == OP_call || opCode == OP_icall), "Not lowered to call or icall?"); + DCHECK((opCode == OP_call || opCode == OP_icall || opCode == OP_icallproto), "Not lowered to call or icall?"); int32 copySize; - uint32 size = ComputeStackSpaceRequirementForCall(*stmt, copySize, opCode == OP_icall); + uint32 size = ComputeStackSpaceRequirementForCall(*stmt, copySize, opCode == OP_icall || opCode == OP_icallproto); if (size > maxParamStackSize) { maxParamStackSize = size; } diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 09952cb8c7..f12bec7081 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -67,8 +67,8 @@ enum : uint8 { kBinEaCgStart = 41, kBinEaStart = 42, kBinNodeBlock = 43, - kBinOpStatement = 44, - kBinOpExpression = 45, +//kBinOpStatement = 44, +//kBinOpExpression = 45, kBinReturnvals = 46, kBinTypeTabStart = 47, kBinSymStart = 48, @@ -76,14 +76,14 @@ enum : uint8 { kBinFuncIdInfoStart = 50, kBinFormalStart = 51, kBinPreg = 52, - kBinPregStart = 53, - kBinLabelStart = 54, + kBinSpecialReg = 53, + kBinLabel = 54, kBinTypenameStart = 55, kBinHeaderStart = 56, kBinAliasMapStart = 57, - kBinKindTypeViaTypename = 58, - kBinKindSymViaSymname = 59, - kBinKindFuncViaSymname = 60, +//kBinKindTypeViaTypename = 58, +//kBinKindSymViaSymname = 59, +//kBinKindFuncViaSymname = 60, kBinFunctionBodyStart = 61, kBinFormalWordsTypeTagged = 62, kBinFormalWordsRefCounted = 63, @@ -103,8 +103,7 @@ class BinaryMplExport { void Export(const std::string &fname, std::unordered_set *dumpFuncSet); void WriteNum(int64 x); void Write(uint8 b); - void OutputType(TyIdx tyIdx, bool canUseTypename); - void OutputTypeViaTypeName(TyIdx tidx) { OutputType(tidx, true); } + void OutputType(TyIdx tyIdx); void WriteFunctionBodyField(uint64 contentIdx, std::unordered_set *dumpFuncSet); void OutputConst(MIRConst *c); void OutputConstBase(const MIRConst &c); @@ -133,12 +132,11 @@ class BinaryMplExport { void OutputInfoVector(const MIRInfoVector &infoVector, const MapleVector &infoVectorIsString); void OutputFuncIdInfo(MIRFunction *func); void OutputLocalSymbol(MIRSymbol *sym); - void OutputLocalSymTab(const MIRFunction *func); - void OutputPregTab(const MIRFunction *func); - void OutputLabelTab(const MIRFunction *func); + void OutputPreg(MIRPreg *preg); + void OutputLabel(LabelIdx lidx); void OutputLocalTypeNameTab(const MIRTypeNameTable *tyNameTab); void OutputFormalsStIdx(MIRFunction *func); - void OutputFuncViaSymName(PUIdx puIdx); + void OutputFuncViaSym(PUIdx puIdx); void OutputExpression(BaseNode *e); void OutputBaseNode(const BaseNode *b); void OutputReturnValues(const CallReturnVector *retv); @@ -182,6 +180,7 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; + MIRFunction *curFunc = nullptr; size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; @@ -190,6 +189,9 @@ class BinaryMplExport { std::unordered_map uStrMark; std::unordered_map symMark; std::unordered_map typMark; + std::unordered_map localSymMark; + std::unordered_map localPregMark; + std::unordered_map labelMark; friend class UpdateMplt; std::unordered_map callInfoMark; std::map *func2SEMap = nullptr; diff --git a/src/mapleall/maple_ir/include/bin_mpl_import.h b/src/mapleall/maple_ir/include/bin_mpl_import.h index 3697654872..ee7f909f9b 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_import.h +++ b/src/mapleall/maple_ir/include/bin_mpl_import.h @@ -126,15 +126,14 @@ class BinaryMplImport { void ImportInfoVector(MIRInfoVector &infoVector, MapleVector &infoVectorIsString); void ImportLocalTypeNameTable(MIRTypeNameTable *typeNameTab); void ImportFuncIdInfo(MIRFunction *func); - void ImportLocalSymbol(MIRFunction *func); - void ImportLocalSymTab(MIRFunction *func); - void ImportPregTab(const MIRFunction *func); - void ImportLabelTab(MIRFunction *func); + MIRSymbol *ImportLocalSymbol(MIRFunction *func); + PregIdx ImportPreg(MIRFunction *func); + LabelIdx ImportLabel(MIRFunction *func); void ImportFormalsStIdx(MIRFunction *func); void ImportAliasMap(MIRFunction *func); void ImportSrcPos(SrcPosition &pos); void ImportBaseNode(Opcode &o, PrimType &typ); - PUIdx ImportFuncViaSymName(); + PUIdx ImportFuncViaSym(MIRFunction *func); BaseNode *ImportExpression(MIRFunction *func); void ImportReturnValues(MIRFunction *func, CallReturnVector *retv); BlockNode *ImportBlockNode(MIRFunction *fn); @@ -162,6 +161,9 @@ class BinaryMplImport { std::vector typTab; std::vector funcTab; std::vector symTab; + std::vector localSymTab; + std::vector localPregTab; + std::vector localLabelTab; std::vector callInfoTab; std::vector eaCgTab; std::vector methodSymbols; diff --git a/src/mapleall/maple_ir/include/ir_safe_cast_traits.def b/src/mapleall/maple_ir/include/ir_safe_cast_traits.def index 1439b49d57..14ed1a367b 100644 --- a/src/mapleall/maple_ir/include/ir_safe_cast_traits.def +++ b/src/mapleall/maple_ir/include/ir_safe_cast_traits.def @@ -224,7 +224,9 @@ REGISTER_SAFE_CAST(CallNode, from.GetOpCode() == OP_call || from.GetOpCode() == OP_virtualicallassigned || instance_of(from)); REGISTER_SAFE_CAST(IcallNode, from.GetOpCode() == OP_icall || - from.GetOpCode() == OP_icallassigned); + from.GetOpCode() == OP_icallassigned || + from.GetOpCode() == OP_icallproto || + from.GetOpCode() == OP_icallprotoassigned); REGISTER_SAFE_CAST(IntrinsiccallNode, from.GetOpCode() == OP_intrinsiccall || from.GetOpCode() == OP_intrinsiccallwithtype || from.GetOpCode() == OP_xintrinsiccall || diff --git a/src/mapleall/maple_ir/include/keywords.def b/src/mapleall/maple_ir/include/keywords.def index eddff2f80a..51a603eafa 100644 --- a/src/mapleall/maple_ir/include/keywords.def +++ b/src/mapleall/maple_ir/include/keywords.def @@ -55,7 +55,6 @@ // per-function declaration keywords KEYWORD(framesize) KEYWORD(upformalsize) - KEYWORD(outparmsize) KEYWORD(moduleid) KEYWORD(funcsize) KEYWORD(funcid) diff --git a/src/mapleall/maple_ir/include/mir_builder.h b/src/mapleall/maple_ir/include/mir_builder.h index ac3215724e..64f6a2723c 100755 --- a/src/mapleall/maple_ir/include/mir_builder.h +++ b/src/mapleall/maple_ir/include/mir_builder.h @@ -262,6 +262,8 @@ class MIRBuilder { IcallNode *CreateStmtIcall(const MapleVector &args); IcallNode *CreateStmtIcallAssigned(const MapleVector &args, const MIRSymbol &ret); + IcallNode *CreateStmtIcallproto(const MapleVector &args); + IcallNode *CreateStmtIcallprotoAssigned(const MapleVector &args, const MIRSymbol &ret); // For Call, VirtualCall, SuperclassCall, InterfaceCall IntrinsiccallNode *CreateStmtIntrinsicCall(MIRIntrinsicID idx, const MapleVector &arguments, TyIdx tyIdx = TyIdx()); diff --git a/src/mapleall/maple_ir/include/mir_function.h b/src/mapleall/maple_ir/include/mir_function.h index 53ea78d1f3..259eb8fc40 100644 --- a/src/mapleall/maple_ir/include/mir_function.h +++ b/src/mapleall/maple_ir/include/mir_function.h @@ -827,24 +827,24 @@ class MIRFunction { callTimes = times; } - uint16 GetFrameSize() const { + uint32 GetFrameSize() const { return frameSize; } - void SetFrameSize(uint16 size) { + void SetFrameSize(uint32 size) { frameSize = size; } - uint16 GetUpFormalSize() const { + uint32 GetUpFormalSize() const { return upFormalSize; } - void SetUpFormalSize(uint16 size) { + void SetUpFormalSize(uint32 size) { upFormalSize = size; } - uint16 GetOutParmSize() const { + uint32 GetOutParmSize() const { return outParmSize; } - void SetOutParmSize(uint16 size) { + void SetOutParmSize(uint32 size) { outParmSize = size; } @@ -1295,9 +1295,9 @@ class MIRFunction { bool isDirty = false; bool fromMpltInline = false; // Whether this function is imported from mplt_inline file or not. uint8_t layoutType = kLayoutUnused; - uint16 frameSize = 0; - uint16 upFormalSize = 0; - uint16 outParmSize = 0; + uint32 frameSize = 0; + uint32 upFormalSize = 0; + uint32 outParmSize = 0; uint16 moduleID = 0; uint32 funcSize = 0; // size of code in words uint32 tempCount = 0; diff --git a/src/mapleall/maple_ir/include/mir_lower.h b/src/mapleall/maple_ir/include/mir_lower.h index 332a6de89f..be479f65a6 100644 --- a/src/mapleall/maple_ir/include/mir_lower.h +++ b/src/mapleall/maple_ir/include/mir_lower.h @@ -86,6 +86,7 @@ class MIRLower { ForeachelemNode *ExpandArrayMrtForeachelemBlock(ForeachelemNode &node); BlockNode *ExpandArrayMrtBlock(BlockNode &block); void AddArrayMrtMpl(BaseNode &exp, BlockNode &newblk); + MIRFuncType *FuncTypeFromFuncPtrExpr(BaseNode *x); void SetLowerME() { lowerPhase |= kShiftLowerMe; } diff --git a/src/mapleall/maple_ir/include/mir_nodes.h b/src/mapleall/maple_ir/include/mir_nodes.h index 0ebf07beff..3481c75c60 100755 --- a/src/mapleall/maple_ir/include/mir_nodes.h +++ b/src/mapleall/maple_ir/include/mir_nodes.h @@ -3304,7 +3304,7 @@ class CallNode : public NaryStmtNode { CallReturnVector returnValues; }; -// icall and icallproto +// icall, icallassigned, icallproto and icallprotoassigned class IcallNode : public NaryStmtNode { public: IcallNode(MapleAllocator &allocator, Opcode o) diff --git a/src/mapleall/maple_ir/include/mir_parser.h b/src/mapleall/maple_ir/include/mir_parser.h index 10d1dd028a..b49370d0ff 100755 --- a/src/mapleall/maple_ir/include/mir_parser.h +++ b/src/mapleall/maple_ir/include/mir_parser.h @@ -134,6 +134,7 @@ class MIRParser { bool ParseStmtIcall(StmtNodePtr&); bool ParseStmtIcallassigned(StmtNodePtr&); bool ParseStmtIcallproto(StmtNodePtr&); + bool ParseStmtIcallprotoassigned(StmtNodePtr&); bool ParseStmtIntrinsiccall(StmtNodePtr&, bool isAssigned); bool ParseStmtIntrinsiccall(StmtNodePtr&); bool ParseStmtIntrinsiccallassigned(StmtNodePtr&); @@ -291,7 +292,6 @@ class MIRParser { bool ParseStmtBlockForType(); bool ParseStmtBlockForFrameSize(); bool ParseStmtBlockForUpformalSize(); - bool ParseStmtBlockForOutParmSize(); bool ParseStmtBlockForModuleID(); bool ParseStmtBlockForFuncSize(); bool ParseStmtBlockForFuncID(); diff --git a/src/mapleall/maple_ir/include/mir_symbol.h b/src/mapleall/maple_ir/include/mir_symbol.h index 2f4e37c80b..4291a0c24b 100644 --- a/src/mapleall/maple_ir/include/mir_symbol.h +++ b/src/mapleall/maple_ir/include/mir_symbol.h @@ -484,12 +484,11 @@ class MIRSymbol { return false; } switch (storageClass) { - case kScFormal: case kScAuto: return true; case kScPstatic: case kScFstatic: - return value.konst == nullptr; + return value.konst == nullptr && !hasPotentialAssignment; default: return false; } @@ -638,7 +637,8 @@ class MIRLabelTable { LabelIdx CreateLabel() { LabelIdx labelIdx = labelTable.size(); - labelTable.push_back(GStrIdx(0)); // insert dummy global string index for anonymous label + GStrIdx strIdx = GlobalTables::GetStrTable().GetOrCreateStrIdxFromName(std::to_string(labelIdx)); + labelTable.push_back(strIdx); return labelIdx; } diff --git a/src/mapleall/maple_ir/include/mir_type.h b/src/mapleall/maple_ir/include/mir_type.h index d6d32d999b..83585981e9 100644 --- a/src/mapleall/maple_ir/include/mir_type.h +++ b/src/mapleall/maple_ir/include/mir_type.h @@ -1189,14 +1189,6 @@ class MIRStructType : public MIRType { isImported = flag; } - bool IsUsed() const { - return isUsed; - } - - void SetIsUsed(bool flag) { - isUsed = flag; - } - bool IsCPlusPlus() const { return isCPlusPlus; } @@ -1368,7 +1360,6 @@ class MIRStructType : public MIRType { vTableMethods.clear(); iTableMethods.clear(); isImported = false; - isUsed = false; hasVolatileField = false; hasVolatileFieldSet = false; } @@ -1471,7 +1462,6 @@ class MIRStructType : public MIRType { // implementation functions, For interfaces, they are abstact functions. // Weak indicates the actual definition is in another module. bool isImported = false; - bool isUsed = false; bool isCPlusPlus = false; // empty struct in C++ has size 1 byte mutable bool hasVolatileField = false; // for caching computed value mutable bool hasVolatileFieldSet = false; // if true, just read hasVolatileField; @@ -1928,11 +1918,19 @@ class MIRFuncType : public MIRType { } bool IsVarargs() const { - return isVarArgs; + return funcAttrs.GetAttr(FUNCATTR_varargs); } - void SetVarArgs(bool flag) { - isVarArgs = flag; + void SetVarArgs() { + funcAttrs.SetAttr(FUNCATTR_varargs); + } + + bool FirstArgReturn() const { + return funcAttrs.GetAttr(FUNCATTR_firstarg_return); + } + + void SetFirstArgReturn() { + funcAttrs.SetAttr(FUNCATTR_firstarg_return); } const TypeAttrs &GetRetAttrs() const { @@ -1960,7 +1958,8 @@ class MIRFuncType : public MIRType { std::vector paramTypeList; std::vector paramAttrsList; TypeAttrs retAttrs; - bool isVarArgs = false; + public: + FuncAttrs funcAttrs; }; class MIRTypeByName : public MIRType { diff --git a/src/mapleall/maple_ir/include/opcode_info.h b/src/mapleall/maple_ir/include/opcode_info.h index 814f15b2f2..5a82646b11 100644 --- a/src/mapleall/maple_ir/include/opcode_info.h +++ b/src/mapleall/maple_ir/include/opcode_info.h @@ -117,6 +117,7 @@ class OpcodeTable { bool IsICall(Opcode o) const { ASSERT(o < OP_last, "invalid opcode"); return o == OP_icall || o == OP_icallassigned || + o == OP_icallproto || o == OP_icallprotoassigned || o == OP_virtualicall || o == OP_virtualicallassigned || o == OP_interfaceicall || o == OP_interfaceicallassigned; } diff --git a/src/mapleall/maple_ir/include/opcodes.def b/src/mapleall/maple_ir/include/opcodes.def index 34cfb51c8d..0e842141ed 100755 --- a/src/mapleall/maple_ir/include/opcodes.def +++ b/src/mapleall/maple_ir/include/opcodes.def @@ -221,3 +221,4 @@ OPCODE(iassignspoff, IassignFPoffNode, OPCODEISSTMT, 8) OPCODE(blkassignoff, BlkassignoffNode, OPCODEISSTMT, 8) OPCODE(icallproto, IcallNode, (OPCODEISSTMT | OPCODEISVARSIZE | OPCODEHASSSAUSE | OPCODEHASSSADEF | OPCODEISCALL), 8) + OPCODE(icallprotoassigned, IcallNode, (OPCODEISSTMT | OPCODEISVARSIZE | OPCODEHASSSAUSE | OPCODEHASSSADEF | OPCODEISCALL | OPCODEISCALLASSIGNED), 8) diff --git a/src/mapleall/maple_ir/include/opcodes.h b/src/mapleall/maple_ir/include/opcodes.h index ea4ed2c1c9..b9f5e0f8c5 100644 --- a/src/mapleall/maple_ir/include/opcodes.h +++ b/src/mapleall/maple_ir/include/opcodes.h @@ -50,7 +50,7 @@ inline constexpr bool IsCallAssigned(Opcode code) { code == OP_virtualicallassigned || code == OP_superclasscallassigned || code == OP_interfacecallassigned || code == OP_interfaceicallassigned || code == OP_customcallassigned || code == OP_polymorphiccallassigned || - code == OP_icallassigned || code == OP_intrinsiccallassigned || + code == OP_icallassigned || code == OP_icallprotoassigned || code == OP_intrinsiccallassigned || code == OP_xintrinsiccallassigned || code == OP_intrinsiccallwithtypeassigned); } @@ -113,6 +113,8 @@ constexpr bool IsStmtMustRequire(Opcode opcode) { case OP_polymorphiccallassigned: case OP_icall: case OP_icallassigned: + case OP_icallproto: + case OP_icallprotoassigned: case OP_intrinsiccall: case OP_xintrinsiccall: case OP_intrinsiccallassigned: diff --git a/src/mapleall/maple_ir/src/bin_func_export.cpp b/src/mapleall/maple_ir/src/bin_func_export.cpp index 5117ed8ed0..6815c8151d 100644 --- a/src/mapleall/maple_ir/src/bin_func_export.cpp +++ b/src/mapleall/maple_ir/src/bin_func_export.cpp @@ -24,6 +24,10 @@ using namespace std; namespace maple { void BinaryMplExport::OutputInfoVector(const MIRInfoVector &infoVector, const MapleVector &infoVectorIsString) { + if (!mod.IsWithDbgInfo()) { + Write(0); + return; + } WriteNum(infoVector.size()); for (uint32 i = 0; i < infoVector.size(); i++) { OutputStr(infoVector[i].first); @@ -41,98 +45,73 @@ void BinaryMplExport::OutputFuncIdInfo(MIRFunction *func) { WriteNum(func->GetPuidxOrigin()); // the funcid OutputInfoVector(func->GetInfoVector(), func->InfoIsString()); if (mod.GetFlavor() == kFlavorLmbc) { - WriteNum(func->GetUpFormalSize()); WriteNum(func->GetFrameSize()); - WriteNum(func->GetOutParmSize()); } - WriteNum(~kBinFuncIdInfoStart); } void BinaryMplExport::OutputBaseNode(const BaseNode *b) { - WriteNum(b->GetOpCode()); - WriteNum(b->GetPrimType()); + Write(static_cast(b->GetOpCode())); + Write(static_cast(b->GetPrimType())); } void BinaryMplExport::OutputLocalSymbol(MIRSymbol *sym) { - if (sym == nullptr) { - WriteNum(0); + std::unordered_map::iterator it = localSymMark.find(sym); + if (it != localSymMark.end()) { + WriteNum(-(it->second)); return; } + WriteNum(kBinSymbol); - WriteNum(sym->GetStIndex()); // preserve original st index OutputStr(sym->GetNameStrIdx()); WriteNum(sym->GetSKind()); WriteNum(sym->GetStorageClass()); + size_t mark = localSymMark.size(); + localSymMark[sym] = mark; OutputTypeAttrs(sym->GetAttrs()); WriteNum(static_cast(sym->GetIsTmp())); if (sym->GetSKind() == kStVar || sym->GetSKind() == kStFunc) { OutputSrcPos(sym->GetSrcPosition()); } - OutputTypeViaTypeName(sym->GetTyIdx()); + OutputType(sym->GetTyIdx()); if (sym->GetSKind() == kStPreg) { - WriteNum(sym->GetPreg()->GetPregNo()); + OutputPreg(sym->GetPreg()); } else if (sym->GetSKind() == kStConst || sym->GetSKind() == kStVar) { OutputConst(sym->GetKonst()); } else if (sym->GetSKind() == kStFunc) { - OutputFuncViaSymName(sym->GetFunction()->GetPuidx()); - OutputTypeViaTypeName(sym->GetTyIdx()); + OutputFuncViaSym(sym->GetFunction()->GetPuidx()); } else { CHECK_FATAL(false, "should not used"); } } -void BinaryMplExport::OutputLocalSymTab(const MIRFunction *func) { - WriteNum(kBinSymStart); - uint64 outsymSizeIdx = buf.size(); - ExpandFourBuffSize(); /// size of OutSym - int32 size = 0; - - for (uint32 i = 1; i < func->GetSymTab()->GetSymbolTableSize(); i++) { - MIRSymbol *s = func->GetSymTab()->GetSymbolFromStIdx(i); - if (s->IsDeleted()) { - OutputLocalSymbol(nullptr); - } else { - OutputLocalSymbol(s); - } - size++; +void BinaryMplExport::OutputPreg(MIRPreg *preg) { + if (preg->GetPregNo() < 0) { + WriteNum(kBinSpecialReg); + Write(-preg->GetPregNo()); + return; } - - Fixup(outsymSizeIdx, size); - WriteNum(~kBinSymStart); -} - -void BinaryMplExport::OutputPregTab(const MIRFunction *func) { - WriteNum(kBinPregStart); - uint64 outRegSizeIdx = buf.size(); - ExpandFourBuffSize(); /// size of OutReg - int32 size = 0; - - for (uint32 i = 1; i < func->GetPregTab()->Size(); ++i) { - MIRPreg *mirpreg = func->GetPregTab()->PregFromPregIdx(static_cast(i)); - if (mirpreg == nullptr) { - WriteNum(0); - size++; - continue; - } - WriteNum(kBinPreg); - WriteNum(mirpreg->GetPregNo()); - TyIdx tyIdx = (mirpreg->GetMIRType() == nullptr) ? TyIdx(0) : mirpreg->GetMIRType()->GetTypeIndex(); - OutputTypeViaTypeName(tyIdx); - WriteNum(mirpreg->GetPrimType()); - size++; + std::unordered_map::iterator it = localPregMark.find(preg); + if (it != localPregMark.end()) { + WriteNum(-(it->second)); + return; } - Fixup(outRegSizeIdx, size); - WriteNum(~kBinPregStart); + WriteNum(kBinPreg); + Write(static_cast(preg->GetPrimType())); + size_t mark = localPregMark.size(); + localPregMark[preg] = mark; } -void BinaryMplExport::OutputLabelTab(const MIRFunction *func) { - WriteNum(kBinLabelStart); - WriteNum(static_cast(func->GetLabelTab()->Size()-1)); // entry 0 is skipped - for (uint32 i = 1; i < func->GetLabelTab()->Size(); i++) { - OutputStr(func->GetLabelTab()->GetLabelTable()[i]); +void BinaryMplExport::OutputLabel(LabelIdx lidx) { + std::unordered_map::iterator it = labelMark.find(lidx); + if (it != labelMark.end()) { + WriteNum(-(it->second)); + return; } - WriteNum(~kBinLabelStart); + + WriteNum(kBinLabel); + size_t mark = labelMark.size(); + labelMark[lidx] = mark; } void BinaryMplExport::OutputLocalTypeNameTab(const MIRTypeNameTable *typeNameTab) { @@ -140,18 +119,16 @@ void BinaryMplExport::OutputLocalTypeNameTab(const MIRTypeNameTable *typeNameTab WriteNum(static_cast(typeNameTab->Size())); for (std::pair it : typeNameTab->GetGStrIdxToTyIdxMap()) { OutputStr(it.first); - OutputTypeViaTypeName(it.second); + OutputType(it.second); } - WriteNum(~kBinTypenameStart); } void BinaryMplExport::OutputFormalsStIdx(MIRFunction *func) { WriteNum(kBinFormalStart); WriteNum(func->GetFormalDefVec().size()); for (FormalDef formalDef : func->GetFormalDefVec()) { - WriteNum(formalDef.formalSym->GetStIndex()); + OutputLocalSymbol(formalDef.formalSym); } - WriteNum(~kBinFormalStart); } void BinaryMplExport::OutputAliasMap(MapleMap &aliasVarMap) { @@ -160,21 +137,18 @@ void BinaryMplExport::OutputAliasMap(MapleMap &aliasVarMa for (std::pair it : aliasVarMap) { OutputStr(it.first); OutputStr(it.second.memPoolStrIdx); - OutputTypeViaTypeName(it.second.tyIdx); + OutputType(it.second.tyIdx); OutputStr(it.second.sigStrIdx); } - WriteNum(~kBinAliasMapStart); } -void BinaryMplExport::OutputFuncViaSymName(PUIdx puIdx) { +void BinaryMplExport::OutputFuncViaSym(PUIdx puIdx) { MIRFunction *func = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(puIdx); MIRSymbol *funcSt = GlobalTables::GetGsymTable().GetSymbolFromStidx(func->GetStIdx().Idx()); - WriteNum(kBinKindFuncViaSymname); - OutputStr(funcSt->GetNameStrIdx()); + OutputSymbol(funcSt); } void BinaryMplExport::OutputExpression(BaseNode *e) { - WriteNum(kBinOpExpression); OutputBaseNode(e); switch (e->GetOpCode()) { // leaf @@ -190,17 +164,17 @@ void BinaryMplExport::OutputExpression(BaseNode *e) { } case OP_addroflabel: { AddroflabelNode *lNode = static_cast(e); - WriteNum(lNode->GetOffset()); + OutputLabel(lNode->GetOffset()); return; } case OP_addroffunc: { AddroffuncNode *addrNode = static_cast(e); - OutputFuncViaSymName(addrNode->GetPUIdx()); + OutputFuncViaSym(addrNode->GetPUIdx()); return; } case OP_sizeoftype: { SizeoftypeNode *sot = static_cast(e); - OutputTypeViaTypeName(sot->GetTyIdx()); + OutputType(sot->GetTyIdx()); return; } case OP_addrof: @@ -219,24 +193,23 @@ void BinaryMplExport::OutputExpression(BaseNode *e) { } WriteNum(stIdx.Scope()); if (stIdx.Islocal()) { - WriteNum(stIdx.Idx()); // preserve original st index + OutputLocalSymbol(curFunc->GetLocalOrGlobalSymbol(stIdx)); } else { - MIRSymbol *sym = GlobalTables::GetGsymTable().GetSymbolFromStidx(stIdx.Idx()); - WriteNum(kBinKindSymViaSymname); - OutputStr(sym->GetNameStrIdx()); + OutputSymbol(curFunc->GetLocalOrGlobalSymbol(stIdx)); } return; } case OP_regread: { RegreadNode *regreadNode = static_cast(e); - WriteNum(regreadNode->GetRegIdx()); + MIRPreg *preg = curFunc->GetPregTab()->PregFromPregIdx(regreadNode->GetRegIdx()); + OutputPreg(preg); return; } case OP_gcmalloc: case OP_gcpermalloc: case OP_stackmalloc: { GCMallocNode *gcNode = static_cast(e); - OutputTypeViaTypeName(gcNode->GetTyIdx()); + OutputType(gcNode->GetTyIdx()); return; } // unary @@ -245,18 +218,18 @@ void BinaryMplExport::OutputExpression(BaseNode *e) { case OP_floor: case OP_trunc: { TypeCvtNode *typecvtNode = static_cast(e); - WriteNum(typecvtNode->FromType()); + Write(static_cast(typecvtNode->FromType())); break; } case OP_retype: { RetypeNode *retypeNode = static_cast(e); - OutputTypeViaTypeName(retypeNode->GetTyIdx()); + OutputType(retypeNode->GetTyIdx()); break; } case OP_iread: case OP_iaddrof: { IreadNode *irNode = static_cast(e); - OutputTypeViaTypeName(irNode->GetTyIdx()); + OutputType(irNode->GetTyIdx()); WriteNum(irNode->GetFieldID()); break; } @@ -274,20 +247,20 @@ void BinaryMplExport::OutputExpression(BaseNode *e) { case OP_zext: case OP_extractbits: { ExtractbitsNode *extNode = static_cast(e); - WriteNum(extNode->GetBitsOffset()); - WriteNum(extNode->GetBitsSize()); + Write(extNode->GetBitsOffset()); + Write(extNode->GetBitsSize()); break; } case OP_depositbits: { DepositbitsNode *dbNode = static_cast(e); - WriteNum(dbNode->GetBitsOffset()); - WriteNum(dbNode->GetBitsSize()); + Write(dbNode->GetBitsOffset()); + Write(dbNode->GetBitsSize()); break; } case OP_gcmallocjarray: case OP_gcpermallocjarray: { JarrayMallocNode *gcNode = static_cast(e); - OutputTypeViaTypeName(gcNode->GetTyIdx()); + OutputType(gcNode->GetTyIdx()); break; } // binary @@ -320,13 +293,13 @@ void BinaryMplExport::OutputExpression(BaseNode *e) { case OP_cmpl: case OP_cmp: { CompareNode *cmpNode = static_cast(e); - WriteNum(cmpNode->GetOpndType()); + Write(static_cast(cmpNode->GetOpndType())); break; } case OP_resolveinterfacefunc: case OP_resolvevirtualfunc: { ResolveFuncNode *rsNode = static_cast(e); - OutputFuncViaSymName(rsNode->GetPuIdx()); + OutputFuncViaSym(rsNode->GetPuIdx()); break; } // ternary @@ -336,8 +309,8 @@ void BinaryMplExport::OutputExpression(BaseNode *e) { // nary case OP_array: { ArrayNode *arrNode = static_cast(e); - OutputTypeViaTypeName(arrNode->GetTyIdx()); - WriteNum(static_cast(arrNode->GetBoundsCheck())); + OutputType(arrNode->GetTyIdx()); + Write(static_cast(arrNode->GetBoundsCheck())); WriteNum(static_cast(arrNode->NumOpnds())); break; } @@ -350,7 +323,7 @@ void BinaryMplExport::OutputExpression(BaseNode *e) { case OP_intrinsicopwithtype: { IntrinsicopNode *intrnNode = static_cast(e); WriteNum(intrnNode->GetIntrinsic()); - OutputTypeViaTypeName(intrnNode->GetTyIdx()); + OutputType(intrnNode->GetTyIdx()); WriteNum(static_cast(intrnNode->NumOpnds())); break; } @@ -365,6 +338,9 @@ void BinaryMplExport::OutputExpression(BaseNode *e) { static SrcPosition lastOutputSrcPosition; void BinaryMplExport::OutputSrcPos(const SrcPosition &pos) { + if (!mod.IsWithDbgInfo()) { + return; + } if (pos.FileNum() == 0 || pos.LineNum() == 0) { // error case, so output 0 WriteNum(lastOutputSrcPosition.RawData()); WriteNum(lastOutputSrcPosition.LineNum()); @@ -379,9 +355,15 @@ void BinaryMplExport::OutputReturnValues(const CallReturnVector *retv) { WriteNum(kBinReturnvals); WriteNum(static_cast(retv->size())); for (uint32 i = 0; i < retv->size(); i++) { - WriteNum((*retv)[i].first.Idx()); - WriteNum((*retv)[i].second.GetFieldID()); - WriteNum((*retv)[i].second.GetPregIdx()); + RegFieldPair rfp = (*retv)[i].second; + if (rfp.IsReg()) { + MIRPreg *preg = curFunc->GetPregTab()->PregFromPregIdx(rfp.GetPregIdx()); + OutputPreg(preg); + } else { + WriteNum(0); + WriteNum((rfp.GetFieldID())); + OutputLocalSymbol(curFunc->GetLocalOrGlobalSymbol((*retv)[i].first)); + } } } @@ -397,7 +379,6 @@ void BinaryMplExport::OutputBlockNode(BlockNode *block) { ExpandFourBuffSize(); // place holder, Fixup later for (StmtNode *s = block->GetFirst(); s; s = s->GetNext()) { bool doneWithOpnds = false; - WriteNum(kBinOpStatement); OutputSrcPos(s->GetSrcPos()); WriteNum(s->GetOpCode()); switch (s->GetOpCode()) { @@ -416,36 +397,35 @@ void BinaryMplExport::OutputBlockNode(BlockNode *block) { } WriteNum(stIdx.Scope()); if (stIdx.Islocal()) { - WriteNum(stIdx.Idx()); // preserve original st index + OutputLocalSymbol(curFunc->GetLocalOrGlobalSymbol(stIdx)); } else { - MIRSymbol *sym = GlobalTables::GetGsymTable().GetSymbolFromStidx(stIdx.Idx()); - WriteNum(kBinKindSymViaSymname); - OutputStr(sym->GetNameStrIdx()); + OutputSymbol(curFunc->GetLocalOrGlobalSymbol(stIdx)); } break; } case OP_regassign: { RegassignNode *rass = static_cast(s); - WriteNum(rass->GetPrimType()); - WriteNum(rass->GetRegIdx()); + Write(static_cast(rass->GetPrimType())); + MIRPreg *preg = curFunc->GetPregTab()->PregFromPregIdx(rass->GetRegIdx()); + OutputPreg(preg); break; } case OP_iassign: { IassignNode *iass = static_cast(s); - OutputTypeViaTypeName(iass->GetTyIdx()); + OutputType(iass->GetTyIdx()); WriteNum(iass->GetFieldID()); break; } case OP_iassignoff: { IassignoffNode *iassoff = static_cast(s); - WriteNum(iassoff->GetPrimType()); + Write(static_cast(iassoff->GetPrimType())); WriteNum(iassoff->GetOffset()); break; } case OP_iassignspoff: case OP_iassignfpoff: { IassignFPoffNode *iassfpoff = static_cast(s); - WriteNum(iassfpoff->GetPrimType()); + Write(static_cast(iassfpoff->GetPrimType())); WriteNum(iassfpoff->GetOffset()); break; } @@ -465,9 +445,9 @@ void BinaryMplExport::OutputBlockNode(BlockNode *block) { case OP_customcall: case OP_polymorphiccall: { CallNode *callnode = static_cast(s); - OutputFuncViaSymName(callnode->GetPUIdx()); + OutputFuncViaSym(callnode->GetPUIdx()); if (s->GetOpCode() == OP_polymorphiccall) { - OutputTypeViaTypeName(static_cast(callnode)->GetTyIdx()); + OutputType(static_cast(callnode)->GetTyIdx()); } WriteNum(static_cast(s->NumOpnds())); break; @@ -480,15 +460,15 @@ void BinaryMplExport::OutputBlockNode(BlockNode *block) { case OP_interfaceicallassigned: case OP_customcallassigned: { CallNode *callnode = static_cast(s); - OutputFuncViaSymName(callnode->GetPUIdx()); + OutputFuncViaSym(callnode->GetPUIdx()); OutputReturnValues(&callnode->GetReturnVec()); WriteNum(static_cast(s->NumOpnds())); break; } case OP_polymorphiccallassigned: { CallNode *callnode = static_cast(s); - OutputFuncViaSymName(callnode->GetPUIdx()); - OutputTypeViaTypeName(callnode->GetTyIdx()); + OutputFuncViaSym(callnode->GetPUIdx()); + OutputType(callnode->GetTyIdx()); OutputReturnValues(&callnode->GetReturnVec()); WriteNum(static_cast(s->NumOpnds())); break; @@ -496,13 +476,14 @@ void BinaryMplExport::OutputBlockNode(BlockNode *block) { case OP_icallproto: case OP_icall: { IcallNode *icallnode = static_cast(s); - OutputTypeViaTypeName(icallnode->GetRetTyIdx()); + OutputType(icallnode->GetRetTyIdx()); WriteNum(static_cast(s->NumOpnds())); break; } + case OP_icallprotoassigned: case OP_icallassigned: { IcallNode *icallnode = static_cast(s); - OutputTypeViaTypeName(icallnode->GetRetTyIdx()); + OutputType(icallnode->GetRetTyIdx()); OutputReturnValues(&icallnode->GetReturnVec()); WriteNum(static_cast(s->NumOpnds())); break; @@ -525,14 +506,14 @@ void BinaryMplExport::OutputBlockNode(BlockNode *block) { case OP_intrinsiccallwithtype: { IntrinsiccallNode *intrnNode = static_cast(s); WriteNum(intrnNode->GetIntrinsic()); - OutputTypeViaTypeName(intrnNode->GetTyIdx()); + OutputType(intrnNode->GetTyIdx()); WriteNum(static_cast(s->NumOpnds())); break; } case OP_intrinsiccallwithtypeassigned: { IntrinsiccallNode *intrnNode = static_cast(s); WriteNum(intrnNode->GetIntrinsic()); - OutputTypeViaTypeName(intrnNode->GetTyIdx()); + OutputType(intrnNode->GetTyIdx()); OutputReturnValues(&intrnNode->GetReturnVec()); WriteNum(static_cast(s->NumOpnds())); break; @@ -567,28 +548,28 @@ void BinaryMplExport::OutputBlockNode(BlockNode *block) { } case OP_label: { LabelNode *lNode = static_cast(s); - WriteNum(lNode->GetLabelIdx()); + OutputLabel(lNode->GetLabelIdx()); break; } case OP_goto: case OP_gosub: { GotoNode *gtoNode = static_cast(s); - WriteNum(gtoNode->GetOffset()); + OutputLabel(gtoNode->GetOffset()); break; } case OP_brfalse: case OP_brtrue: { CondGotoNode *cgotoNode = static_cast(s); - WriteNum(cgotoNode->GetOffset()); + OutputLabel(cgotoNode->GetOffset()); break; } case OP_switch: { SwitchNode *swNode = static_cast(s); - WriteNum(swNode->GetDefaultLabel()); + OutputLabel(swNode->GetDefaultLabel()); WriteNum(static_cast(swNode->GetSwitchTable().size())); for (CasePair cpair : swNode->GetSwitchTable()) { WriteNum(cpair.first); - WriteNum(cpair.second); + OutputLabel(cpair.second); } break; } @@ -598,14 +579,14 @@ void BinaryMplExport::OutputBlockNode(BlockNode *block) { WriteNum(static_cast(rgoto->GetRangeGotoTable().size())); for (SmallCasePair cpair : rgoto->GetRangeGotoTable()) { WriteNum(cpair.first); - WriteNum(cpair.second); + OutputLabel(cpair.second); } break; } case OP_jstry: { JsTryNode *tryNode = static_cast(s); - WriteNum(tryNode->GetCatchOffset()); - WriteNum(tryNode->GetFinallyOffset()); + OutputLabel(tryNode->GetCatchOffset()); + OutputLabel(tryNode->GetFinallyOffset()); break; } case OP_cpptry: @@ -613,7 +594,7 @@ void BinaryMplExport::OutputBlockNode(BlockNode *block) { TryNode *tryNode = static_cast(s); WriteNum(static_cast(tryNode->GetOffsetsCount())); for (LabelIdx lidx : tryNode->GetOffsets()) { - WriteNum(lidx); + OutputLabel(lidx); } break; } @@ -621,7 +602,7 @@ void BinaryMplExport::OutputBlockNode(BlockNode *block) { CatchNode *catchNode = static_cast(s); WriteNum(static_cast(catchNode->GetExceptionTyIdxVec().size())); for (TyIdx tidx : catchNode->GetExceptionTyIdxVec()) { - OutputTypeViaTypeName(tidx); + OutputType(tidx); } break; } @@ -678,7 +659,7 @@ void BinaryMplExport::OutputBlockNode(BlockNode *block) { count = asmNode->gotoLabels.size(); WriteNum(static_cast(count)); for (size_t i = 0; i < count; ++i) { - WriteNum(asmNode->gotoLabels[i]); + OutputLabel(asmNode->gotoLabels[i]); } // the inputs WriteNum(asmNode->NumOpnds()); @@ -713,6 +694,7 @@ void BinaryMplExport::WriteFunctionBodyField(uint64 contentIdx, std::unordered_s if (not2mplt) { for (MIRFunction *func : GetMIRModule().GetFunctionList()) { + curFunc = func; if (func->GetAttr(FUNCATTR_optimized)) { continue; } @@ -733,12 +715,15 @@ void BinaryMplExport::WriteFunctionBodyField(uint64 contentIdx, std::unordered_s continue; } } + localSymMark.clear(); + localSymMark[nullptr] = 0; + localPregMark.clear(); + localPregMark[nullptr] = 0; + labelMark.clear(); + labelMark[0] = 0; OutputFunction(func->GetPuidx()); CHECK_FATAL(func->GetBody() != nullptr, "WriteFunctionBodyField: no function body"); OutputFuncIdInfo(func); - OutputPregTab(func); - OutputLocalSymTab(func); - OutputLabelTab(func); OutputLocalTypeNameTab(func->GetTypeNameTab()); OutputFormalsStIdx(func); if (mod.GetFlavor() < kMmpl) { @@ -752,7 +737,6 @@ void BinaryMplExport::WriteFunctionBodyField(uint64 contentIdx, std::unordered_s Fixup(totalSizeIdx, static_cast(buf.size() - totalSizeIdx)); Fixup(outFunctionBodySizeIdx, size); - WriteNum(~kBinFunctionBodyStart); return; } } // namespace maple diff --git a/src/mapleall/maple_ir/src/bin_func_import.cpp b/src/mapleall/maple_ir/src/bin_func_import.cpp index f54a72bca1..8355bb4c58 100644 --- a/src/mapleall/maple_ir/src/bin_func_import.cpp +++ b/src/mapleall/maple_ir/src/bin_func_import.cpp @@ -47,29 +47,27 @@ void BinaryMplImport::ImportFuncIdInfo(MIRFunction *func) { func->SetPuidxOrigin(static_cast(ReadNum())); ImportInfoVector(func->GetInfoVector(), func->InfoIsString()); if (mod.GetFlavor() == kFlavorLmbc) { - func->SetUpFormalSize(static_cast(ReadNum())); func->SetFrameSize(static_cast(ReadNum())); - func->SetOutParmSize(static_cast(ReadNum())); } - tag = ReadNum(); - CHECK_FATAL(tag == ~kBinFuncIdInfoStart, "pattern mismatch in ImportFuncIdInfo()"); } void BinaryMplImport::ImportBaseNode(Opcode &o, PrimType &typ) { - o = (Opcode)ReadNum(); - typ = (PrimType)ReadNum(); + o = (Opcode)Read(); + typ = (PrimType)Read(); } -void BinaryMplImport::ImportLocalSymbol(MIRFunction *func) { +MIRSymbol *BinaryMplImport::ImportLocalSymbol(MIRFunction *func) { int64 tag = ReadNum(); if (tag == 0) { - func->GetSymTab()->PushNullSymbol(); - return; + return nullptr; } + if (tag < 0) { + CHECK_FATAL(static_cast(-tag) < localSymTab.size(), "index out of bounds"); + return localSymTab.at(-tag); + } CHECK_FATAL(tag == kBinSymbol, "expecting kBinSymbol in ImportLocalSymbol()"); - auto indx = static_cast(ReadNum()); - CHECK_FATAL(indx == func->GetSymTab()->GetSymbolTableSize(), "inconsistant local stIdx"); MIRSymbol *sym = func->GetSymTab()->CreateSymbol(kScopeLocal); + localSymTab.push_back(sym); sym->SetNameStrIdx(ImportStr()); (void)func->GetSymTab()->AddToStringSymbolMap(*sym); sym->SetSKind((MIRSymKind)ReadNum()); @@ -81,66 +79,52 @@ void BinaryMplImport::ImportLocalSymbol(MIRFunction *func) { } sym->SetTyIdx(ImportType()); if (sym->GetSKind() == kStPreg) { - auto thepregno = static_cast(ReadNum()); - MIRType *mirType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(sym->GetTyIdx()); - PregIdx pregidx = func->GetPregTab()->EnterPregNo(thepregno, mirType->GetPrimType(), mirType); - MIRPregTable *pregTab = func->GetPregTab(); - MIRPreg *preg = pregTab->PregFromPregIdx(pregidx); - preg->SetPrimType(mirType->GetPrimType()); + PregIdx pregidx = ImportPreg(func); + MIRPreg *preg = func->GetPregTab()->PregFromPregIdx(pregidx); sym->SetPreg(preg); } else if (sym->GetSKind() == kStConst || sym->GetSKind() == kStVar) { sym->SetKonst(ImportConst(func)); } else if (sym->GetSKind() == kStFunc) { - PUIdx puIdx = ImportFuncViaSymName(); - TyIdx tyIdx = ImportType(); - sym->SetTyIdx(tyIdx); + PUIdx puIdx = ImportFuncViaSym(func); sym->SetFunction(GlobalTables::GetFunctionTable().GetFunctionFromPuidx(puIdx)); } + return sym; } -void BinaryMplImport::ImportLocalSymTab(MIRFunction *func) { +PregIdx BinaryMplImport::ImportPreg(MIRFunction *func) { int64 tag = ReadNum(); - CHECK_FATAL(tag == kBinSymStart, "kBinSymStart expected in ImportLocalSymTab()"); - int32 size = ReadInt(); - for (int64 i = 0; i < size; ++i) { - ImportLocalSymbol(func); + if (tag == 0) { + return 0; } - tag = ReadNum(); - CHECK_FATAL(tag == ~kBinSymStart, "pattern mismatch in ImportLocalSymTab()"); -} - -void BinaryMplImport::ImportPregTab(const MIRFunction *func) { - int64 tag = ReadNum(); - CHECK_FATAL(tag == kBinPregStart, "kBinPregStart expected in ImportPregTab()"); - int32 size = ReadInt(); - for (int64 i = 0; i < size; ++i) { - int64 nextTag = ReadNum(); - if (nextTag == 0) { - func->GetPregTab()->GetPregTable().push_back(nullptr); - continue; - } - CHECK_FATAL(nextTag == kBinPreg, "expecting kBinPreg in ImportPregTab()"); - auto pregNo = static_cast(ReadNum()); - TyIdx tyIdx = ImportType(); - MIRType *ty = (tyIdx == 0) ? nullptr : GlobalTables::GetTypeTable().GetTypeFromTyIdx(tyIdx); - PrimType primType = (PrimType)ReadNum(); - CHECK_FATAL(ty == nullptr || primType == ty->GetPrimType(), "ImportPregTab: inconsistent primitive type"); - (void)func->GetPregTab()->EnterPregNo(pregNo, primType, ty); + if (tag == kBinSpecialReg) { + return -Read(); + } + if (tag < 0) { + CHECK_FATAL(static_cast(-tag) < localPregTab.size(), "index out of bounds"); + return localPregTab.at(-tag); } - tag = ReadNum(); - CHECK_FATAL(tag == ~kBinPregStart, "pattern mismatch in ImportPregTab()"); + CHECK_FATAL(tag == kBinPreg, "expecting kBinPreg in ImportPreg()"); + + PrimType primType = (PrimType)Read(); + PregIdx pidx = func->GetPregTab()->CreatePreg(primType); + localPregTab.push_back(pidx); + return pidx; } -void BinaryMplImport::ImportLabelTab(MIRFunction *func) { +LabelIdx BinaryMplImport::ImportLabel(MIRFunction *func) { int64 tag = ReadNum(); - CHECK_FATAL(tag == kBinLabelStart, "kBinLabelStart expected in ImportLabelTab()"); - int64 size = ReadNum(); - for (int64 i = 0; i < size; ++i) { - GStrIdx gStrIdx = ImportStr(); - (void)func->GetLabelTab()->AddLabel(gStrIdx); + if (tag == 0) { + return 0; + } + if (tag < 0) { + CHECK_FATAL(static_cast(-tag) < localLabelTab.size(), "index out of bounds"); + return localLabelTab.at(-tag); } - tag = ReadNum(); - CHECK_FATAL(tag == ~kBinLabelStart, "pattern mismatch in ImportLabelTab()"); + CHECK_FATAL(tag == kBinLabel, "kBinLabel expected in ImportLabel()"); + + LabelIdx lidx = func->GetLabelTab()->CreateLabel(); + localLabelTab.push_back(lidx); + return lidx; } void BinaryMplImport::ImportLocalTypeNameTable(MIRTypeNameTable *typeNameTab) { @@ -152,8 +136,6 @@ void BinaryMplImport::ImportLocalTypeNameTable(MIRTypeNameTable *typeNameTab) { TyIdx tyIdx = ImportType(); typeNameTab->SetGStrIdxToTyIdx(strIdx, tyIdx); } - tag = ReadNum(); - CHECK_FATAL(tag == ~kBinTypenameStart, "pattern mismatch in ImportTypenametab()"); } void BinaryMplImport::ImportFormalsStIdx(MIRFunction *func) { @@ -161,11 +143,8 @@ void BinaryMplImport::ImportFormalsStIdx(MIRFunction *func) { CHECK_FATAL(tag == kBinFormalStart, "kBinFormalStart expected in ImportFormalsStIdx()"); auto size = ReadNum(); for (int64 i = 0; i < size; ++i) { - uint32 indx = static_cast(ReadNum()); - func->GetFormalDefVec()[static_cast(i)].formalSym = func->GetSymTab()->GetSymbolFromStIdx(indx); + func->GetFormalDefVec()[static_cast(i)].formalSym = ImportLocalSymbol(func); } - tag = ReadNum(); - CHECK_FATAL(tag == ~kBinFormalStart, "pattern mismatch in ImportFormalsStIdx()"); } void BinaryMplImport::ImportAliasMap(MIRFunction *func) { @@ -180,22 +159,15 @@ void BinaryMplImport::ImportAliasMap(MIRFunction *func) { (void)ImportStr(); // not assigning to mimic parser func->GetAliasVarMap()[strIdx] = aliasvars; } - tag = ReadNum(); - CHECK_FATAL(tag == ~kBinAliasMapStart, "pattern mismatch in ImportAliasMap()"); } -PUIdx BinaryMplImport::ImportFuncViaSymName() { - int64 tag = ReadNum(); - CHECK_FATAL(tag == kBinKindFuncViaSymname, "kBinKindFuncViaSymname expected"); - GStrIdx strIdx = ImportStr(); - MIRSymbol *sym = GlobalTables::GetGsymTable().GetSymbolFromStrIdx(strIdx); - MIRFunction *func = sym->GetFunction(); - return func->GetPuidx(); +PUIdx BinaryMplImport::ImportFuncViaSym(MIRFunction *func) { + MIRSymbol *sym = InSymbol(func); + MIRFunction *f = sym->GetFunction(); + return f->GetPuidx(); } BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { - int64 tag = ReadNum(); - CHECK_FATAL(tag == kBinOpExpression, "kBinOpExpression expected"); Opcode op; PrimType typ; ImportBaseNode(op, typ); @@ -215,13 +187,15 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { } case OP_addroflabel: { AddroflabelNode *alabNode = mod.CurFuncCodeMemPool()->New(); - alabNode->SetOffset(static_cast(ReadNum())); + alabNode->SetOffset(ImportLabel(func)); alabNode->SetPrimType(typ); (void)func->GetLabelTab()->addrTakenLabels.insert(alabNode->GetOffset()); return alabNode; } case OP_addroffunc: { - PUIdx puIdx = ImportFuncViaSymName(); + PUIdx puIdx = ImportFuncViaSym(func); + MIRFunction *f = GlobalTables::GetFunctionTable().GetFuncTable()[puIdx]; + f->GetFuncSymbol()->SetAppearsInCode(true); AddroffuncNode *addrNode = mod.CurFuncCodeMemPool()->New(typ, puIdx); return addrNode; } @@ -237,18 +211,18 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { int32 num = static_cast(ReadNum()); StIdx stIdx; stIdx.SetScope(static_cast(ReadNum())); + MIRSymbol *sym = nullptr; if (stIdx.Islocal()) { - stIdx.SetIdx(static_cast(ReadNum())); + sym = ImportLocalSymbol(func); + CHECK_FATAL(sym != nullptr, "null ptr check"); } else { - int32 stag = static_cast(ReadNum()); - CHECK_FATAL(stag == kBinKindSymViaSymname, "kBinKindSymViaSymname expected"); - GStrIdx strIdx = ImportStr(); - MIRSymbol *sym = GlobalTables::GetGsymTable().GetSymbolFromStrIdx(strIdx); + sym = InSymbol(func); + CHECK_FATAL(sym != nullptr, "null ptr check"); if (op == OP_addrof) { sym->SetHasPotentialAssignment(); } - stIdx.SetIdx(sym->GetStIdx().Idx()); } + stIdx.SetIdx(sym->GetStIdx().Idx()); if (op == OP_addrof || op == OP_dread) { AddrofNode *drNode = mod.CurFuncCodeMemPool()->New(op); drNode->SetPrimType(typ); @@ -265,7 +239,7 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { } case OP_regread: { RegreadNode *regreadNode = mod.CurFuncCodeMemPool()->New(); - regreadNode->SetRegIdx(static_cast(ReadNum())); + regreadNode->SetRegIdx(ImportPreg(func)); regreadNode->SetPrimType(typ); return regreadNode; } @@ -294,7 +268,7 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { case OP_floor: case OP_trunc: { TypeCvtNode *typecvtNode = mod.CurFuncCodeMemPool()->New(op, typ); - typecvtNode->SetFromType((PrimType)ReadNum()); + typecvtNode->SetFromType((PrimType)Read()); typecvtNode->SetOpnd(ImportExpression(func), 0); return typecvtNode; } @@ -327,15 +301,15 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { case OP_zext: case OP_extractbits: { ExtractbitsNode *extNode = mod.CurFuncCodeMemPool()->New(op, typ); - extNode->SetBitsOffset(static_cast(ReadNum())); - extNode->SetBitsSize(static_cast(ReadNum())); + extNode->SetBitsOffset(Read()); + extNode->SetBitsSize(Read()); extNode->SetOpnd(ImportExpression(func), 0); return extNode; } case OP_depositbits: { DepositbitsNode *dbNode = mod.CurFuncCodeMemPool()->New(op, typ); - dbNode->SetBitsOffset(static_cast(ReadNum())); - dbNode->SetBitsSize(static_cast(ReadNum())); + dbNode->SetBitsOffset(ReadNum()); + dbNode->SetBitsSize(ReadNum()); dbNode->SetOpnd(ImportExpression(func), 0); dbNode->SetOpnd(ImportExpression(func), 1); return dbNode; @@ -380,7 +354,7 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { case OP_cmpl: case OP_cmp: { CompareNode *cmpNode = mod.CurFuncCodeMemPool()->New(op, typ); - cmpNode->SetOpndType((PrimType)ReadNum()); + cmpNode->SetOpndType((PrimType)Read()); cmpNode->SetOpnd(ImportExpression(func), 0); cmpNode->SetOpnd(ImportExpression(func), 1); return cmpNode; @@ -388,7 +362,7 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { case OP_resolveinterfacefunc: case OP_resolvevirtualfunc: { ResolveFuncNode *rsNode = mod.CurFuncCodeMemPool()->New(op, typ); - rsNode->SetPUIdx(ImportFuncViaSymName()); + rsNode->SetPUIdx(ImportFuncViaSym(func)); rsNode->SetOpnd(ImportExpression(func), 0); rsNode->SetOpnd(ImportExpression(func), 1); return rsNode; @@ -404,7 +378,7 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { // nary case OP_array: { TyIdx tidx = ImportType(); - auto boundsCheck = static_cast(ReadNum()); + bool boundsCheck = static_cast(Read()); ArrayNode *arrNode = mod.CurFuncCodeMemPool()->New(func->GetCodeMPAllocator(), typ, tidx, boundsCheck); auto n = static_cast(ReadNum()); @@ -437,12 +411,15 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { return intrnNode; } default: - CHECK_FATAL(false, "Unhandled op %d", tag); + CHECK_FATAL(false, "Unhandled op %d", op); break; } } void BinaryMplImport::ImportSrcPos(SrcPosition &pos) { + if (!mod.IsWithDbgInfo()) { + return; + } pos.SetRawData(static_cast(ReadNum())); pos.SetLineNum(static_cast(ReadNum())); } @@ -452,14 +429,16 @@ void BinaryMplImport::ImportReturnValues(MIRFunction *func, CallReturnVector *re CHECK_FATAL(tag == kBinReturnvals, "expecting return values"); auto size = static_cast(ReadNum()); for (uint32 i = 0; i < size; ++i) { - uint32 idx = static_cast(ReadNum()); - FieldID fid = static_cast(ReadNum()); - PregIdx ridx = static_cast(ReadNum()); - retv->push_back(std::make_pair(StIdx(kScopeLocal, idx), RegFieldPair(fid, ridx))); - if (idx == 0) { + RegFieldPair rfp; + rfp.SetPregIdx(ImportPreg(func)); + if (rfp.IsReg()) { + retv->push_back(std::make_pair(StIdx(), rfp)); continue; } - MIRSymbol *lsym = func->GetSymTab()->GetSymbolFromStIdx(idx, false); + rfp.SetFieldID(static_cast(ReadNum())); + MIRSymbol *lsym = ImportLocalSymbol(func); + CHECK_FATAL(lsym != nullptr, "null ptr check"); + retv->push_back(std::make_pair(lsym->GetStIdx(), rfp)); if (lsym->GetName().find("L_STR") == 0) { MIRType *ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(lsym->GetTyIdx()); CHECK_FATAL(ty->GetKind() == kTypePointer, "Pointer type expected for L_STR prefix"); @@ -480,8 +459,6 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { ImportSrcPos(block->GetSrcPos()); int32 size = ReadInt(); for (int32 k = 0; k < size; ++k) { - tag = ReadNum(); - CHECK_FATAL(tag == kBinOpStatement, "kBinOpStatement expected"); SrcPosition thesrcPosition; ImportSrcPos(thesrcPosition); op = (Opcode)ReadNum(); @@ -496,16 +473,16 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { int32 num = static_cast(ReadNum()); StIdx stIdx; stIdx.SetScope(static_cast(ReadNum())); + MIRSymbol *sym = nullptr; if (stIdx.Islocal()) { - stIdx.SetIdx(static_cast(ReadNum())); + sym = ImportLocalSymbol(func); + CHECK_FATAL(sym != nullptr, "null ptr check"); } else { - int32 stag = static_cast(ReadNum()); - CHECK_FATAL(stag == kBinKindSymViaSymname, "kBinKindSymViaSymname expected"); - GStrIdx strIdx = ImportStr(); - MIRSymbol *sym = GlobalTables::GetGsymTable().GetSymbolFromStrIdx(strIdx); + sym = InSymbol(func); + CHECK_FATAL(sym != nullptr, "null ptr check"); sym->SetHasPotentialAssignment(); - stIdx.SetIdx(sym->GetStIdx().Idx()); } + stIdx.SetIdx(sym->GetStIdx().Idx()); if (op == OP_dassign) { DassignNode *s = func->GetCodeMemPool()->New(); s->SetStIdx(stIdx); @@ -524,8 +501,8 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { } case OP_regassign: { RegassignNode *s = func->GetCodeMemPool()->New(); - s->SetPrimType((PrimType)ReadNum()); - s->SetRegIdx(static_cast(ReadNum())); + s->SetPrimType((PrimType)Read()); + s->SetRegIdx(ImportPreg(func)); s->SetOpnd(ImportExpression(func), 0); stmt = s; break; @@ -541,7 +518,7 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { } case OP_iassignoff: { IassignoffNode *s = func->GetCodeMemPool()->New(); - s->SetPrimType((PrimType)ReadNum()); + s->SetPrimType((PrimType)Read()); s->SetOffset(static_cast(ReadNum())); s->SetOpnd(ImportExpression(func), 0); s->SetOpnd(ImportExpression(func), 1); @@ -551,7 +528,7 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { case OP_iassignspoff: case OP_iassignfpoff: { IassignFPoffNode *s = func->GetCodeMemPool()->New(op); - s->SetPrimType((PrimType)ReadNum()); + s->SetPrimType((PrimType)Read()); s->SetOffset(static_cast(ReadNum())); s->SetOpnd(ImportExpression(func), 0); stmt = s; @@ -576,7 +553,9 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { case OP_interfaceicall: case OP_customcall: { CallNode *s = func->GetCodeMemPool()->New(mod, op); - s->SetPUIdx(ImportFuncViaSymName()); + s->SetPUIdx(ImportFuncViaSym(func)); + MIRFunction *f = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(s->GetPUIdx()); + f->GetFuncSymbol()->SetAppearsInCode(true); numOpr = static_cast(ReadNum()); s->SetNumOpnds(numOpr); for (int32 i = 0; i < numOpr; ++i) { @@ -593,7 +572,9 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { case OP_interfaceicallassigned: case OP_customcallassigned: { CallNode *s = func->GetCodeMemPool()->New(mod, op); - s->SetPUIdx(ImportFuncViaSymName()); + s->SetPUIdx(ImportFuncViaSym(func)); + MIRFunction *f = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(s->GetPUIdx()); + f->GetFuncSymbol()->SetAppearsInCode(true); ImportReturnValues(func, &s->GetReturnVec()); numOpr = static_cast(ReadNum()); s->SetNumOpnds(numOpr); @@ -609,7 +590,9 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { } case OP_polymorphiccall: { CallNode *s = func->GetCodeMemPool()->New(mod, op); - s->SetPUIdx(ImportFuncViaSymName()); + s->SetPUIdx(ImportFuncViaSym(func)); + MIRFunction *f = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(s->GetPUIdx()); + f->GetFuncSymbol()->SetAppearsInCode(true); s->SetTyIdx(ImportType()); numOpr = static_cast(ReadNum()); s->SetNumOpnds(numOpr); @@ -621,7 +604,9 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { } case OP_polymorphiccallassigned: { CallNode *s = func->GetCodeMemPool()->New(mod, op); - s->SetPUIdx(ImportFuncViaSymName()); + s->SetPUIdx(ImportFuncViaSym(func)); + MIRFunction *f = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(s->GetPUIdx()); + f->GetFuncSymbol()->SetAppearsInCode(true); s->SetTyIdx(ImportType()); ImportReturnValues(func, &s->GetReturnVec()); numOpr = static_cast(ReadNum()); @@ -644,6 +629,7 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { stmt = s; break; } + case OP_icallprotoassigned: case OP_icallassigned: { IcallNode *s = func->GetCodeMemPool()->New(mod, op); s->SetRetTyIdx(ImportType()); @@ -758,32 +744,32 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { } case OP_label: { LabelNode *s = mod.CurFuncCodeMemPool()->New(); - s->SetLabelIdx(static_cast(ReadNum())); + s->SetLabelIdx(ImportLabel(func)); stmt = s; break; } case OP_goto: case OP_gosub: { GotoNode *s = mod.CurFuncCodeMemPool()->New(op); - s->SetOffset(static_cast(ReadNum())); + s->SetOffset(ImportLabel(func)); stmt = s; break; } case OP_brfalse: case OP_brtrue: { CondGotoNode *s = mod.CurFuncCodeMemPool()->New(op); - s->SetOffset(static_cast(ReadNum())); + s->SetOffset(ImportLabel(func)); s->SetOpnd(ImportExpression(func), 0); stmt = s; break; } case OP_switch: { SwitchNode *s = mod.CurFuncCodeMemPool()->New(mod); - s->SetDefaultLabel(static_cast(ReadNum())); + s->SetDefaultLabel(ImportLabel(func)); auto tagSize = static_cast(ReadNum()); for (uint32 i = 0; i < tagSize; ++i) { int64 casetag = ReadNum(); - LabelIdx lidx(ReadNum()); + LabelIdx lidx = ImportLabel(func); CasePair cpair = std::make_pair(casetag, lidx); s->GetSwitchTable().push_back(cpair); } @@ -797,7 +783,7 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { uint32 tagSize = static_cast(ReadNum()); for (uint32 i = 0; i < tagSize; ++i) { uint16 casetag = static_cast(ReadNum()); - LabelIdx lidx(ReadNum()); + LabelIdx lidx = ImportLabel(func); s->AddRangeGoto(casetag, lidx); } s->SetOpnd(ImportExpression(func), 0); @@ -806,8 +792,8 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { } case OP_jstry: { JsTryNode *s = mod.CurFuncCodeMemPool()->New(); - s->SetCatchOffset(static_cast(ReadNum())); - s->SetFinallyOffset(static_cast(ReadNum())); + s->SetCatchOffset(ImportLabel(func)); + s->SetFinallyOffset(ImportLabel(func)); stmt = s; break; } @@ -816,7 +802,7 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { TryNode *s = mod.CurFuncCodeMemPool()->New(mod); auto numLabels = static_cast(ReadNum()); for (uint32 i = 0; i < numLabels; ++i) { - s->GetOffsets().push_back(ReadNum()); + s->GetOffsets().push_back(ImportLabel(func)); } stmt = s; break; @@ -886,7 +872,7 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { // the labels count = static_cast(ReadNum()); for (size_t i = 0; i < count; ++i) { - auto lidx = static_cast(ReadNum()); + LabelIdx lidx = ImportLabel(func); s->gotoLabels.push_back(lidx); } // the inputs @@ -926,6 +912,13 @@ void BinaryMplImport::ReadFunctionBodyField() { PUIdx puIdx = ImportFunction(); MIRFunction *fn = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(puIdx); mod.SetCurFunction(fn); + fn->GetFuncSymbol()->SetAppearsInCode(true); + localSymTab.clear(); + localSymTab.push_back(nullptr); + localPregTab.clear(); + localPregTab.push_back(0); + localLabelTab.clear(); + localLabelTab.push_back(0); fn->AllocSymTab(); fn->AllocPregTab(); @@ -933,9 +926,6 @@ void BinaryMplImport::ReadFunctionBodyField() { fn->AllocLabelTab(); ImportFuncIdInfo(fn); - ImportPregTab(fn); - ImportLocalSymTab(fn); - ImportLabelTab(fn); ImportLocalTypeNameTable(fn->GetTypeNameTab()); ImportFormalsStIdx(fn); if (mod.GetFlavor() < kMmpl) { @@ -944,8 +934,6 @@ void BinaryMplImport::ReadFunctionBodyField() { (void)ImportBlockNode(fn); mod.AddFunction(fn); } - int64 tag = ReadNum(); - CHECK_FATAL(tag == ~kBinFunctionBodyStart, "pattern mismatch in Read FunctionBody"); return; } } // namespace maple diff --git a/src/mapleall/maple_ir/src/bin_mpl_export.cpp b/src/mapleall/maple_ir/src/bin_mpl_export.cpp index 879e34074d..e777db2ba6 100644 --- a/src/mapleall/maple_ir/src/bin_mpl_export.cpp +++ b/src/mapleall/maple_ir/src/bin_mpl_export.cpp @@ -26,7 +26,7 @@ namespace { using namespace maple; using OutputConstFactory = FunctionFactory; -using OutputTypeFactory = FunctionFactory; +using OutputTypeFactory = FunctionFactory; void OutputConstInt(const MIRConst &constVal, BinaryMplExport &mplExport) { mplExport.WriteNum(kBinKindConstInt); @@ -62,7 +62,7 @@ void OutputConstLbl(const MIRConst &constVal, BinaryMplExport &mplExport) { mplExport.WriteNum(kBinKindConstAddrofLabel); mplExport.OutputConstBase(constVal); const MIRLblConst &lblConst = static_cast(constVal); - mplExport.WriteNum(lblConst.GetValue()); // LabelIdx not needed to output puIdx + mplExport.OutputLabel(lblConst.GetValue()); } void OutputConstStr(const MIRConst &constVal, BinaryMplExport &mplExport) { @@ -141,39 +141,39 @@ static bool InitOutputConstFactory() { return true; } -void OutputTypeScalar(const MIRType &ty, BinaryMplExport &mplExport, bool) { +void OutputTypeScalar(const MIRType &ty, BinaryMplExport &mplExport) { mplExport.WriteNum(kBinKindTypeScalar); mplExport.OutputTypeBase(ty); } -void OutputTypePointer(const MIRType &ty, BinaryMplExport &mplExport, bool canUseTypename) { +void OutputTypePointer(const MIRType &ty, BinaryMplExport &mplExport) { const auto &type = static_cast(ty); mplExport.WriteNum(kBinKindTypePointer); mplExport.OutputTypeBase(type); mplExport.OutputTypeAttrs(type.GetTypeAttrs()); - mplExport.OutputType(type.GetPointedTyIdx(), canUseTypename); + mplExport.OutputType(type.GetPointedTyIdx()); } -void OutputTypeByName(const MIRType &ty, BinaryMplExport &mplExport, bool) { +void OutputTypeByName(const MIRType &ty, BinaryMplExport &mplExport) { mplExport.WriteNum(kBinKindTypeByName); mplExport.OutputTypeBase(ty); } -void OutputTypeFArray(const MIRType &ty, BinaryMplExport &mplExport, bool canUseTypename) { +void OutputTypeFArray(const MIRType &ty, BinaryMplExport &mplExport) { const auto &type = static_cast(ty); mplExport.WriteNum(kBinKindTypeFArray); mplExport.OutputTypeBase(type); - mplExport.OutputType(type.GetElemTyIdx(), canUseTypename); + mplExport.OutputType(type.GetElemTyIdx()); } -void OutputTypeJArray(const MIRType &ty, BinaryMplExport &mplExport, bool canUseTypename) { +void OutputTypeJArray(const MIRType &ty, BinaryMplExport &mplExport) { const auto &type = static_cast(ty); mplExport.WriteNum(kBinKindTypeJarray); mplExport.OutputTypeBase(type); - mplExport.OutputType(type.GetElemTyIdx(), canUseTypename); + mplExport.OutputType(type.GetElemTyIdx()); } -void OutputTypeArray(const MIRType &ty, BinaryMplExport &mplExport, bool canUseTypename) { +void OutputTypeArray(const MIRType &ty, BinaryMplExport &mplExport) { const auto &type = static_cast(ty); mplExport.WriteNum(kBinKindTypeArray); mplExport.OutputTypeBase(type); @@ -181,20 +181,20 @@ void OutputTypeArray(const MIRType &ty, BinaryMplExport &mplExport, bool canUseT for (uint16 i = 0; i < type.GetDim(); ++i) { mplExport.WriteNum(type.GetSizeArrayItem(i)); } - mplExport.OutputType(type.GetElemTyIdx(), canUseTypename); + mplExport.OutputType(type.GetElemTyIdx()); mplExport.OutputTypeAttrs(type.GetTypeAttrs()); } -void OutputTypeFunction(const MIRType &ty, BinaryMplExport &mplExport, bool canUseTypename) { +void OutputTypeFunction(const MIRType &ty, BinaryMplExport &mplExport) { const auto &type = static_cast(ty); mplExport.WriteNum(kBinKindTypeFunction); mplExport.OutputTypeBase(type); - mplExport.OutputType(type.GetRetTyIdx(), canUseTypename); - mplExport.WriteNum(type.IsVarargs()); + mplExport.OutputType(type.GetRetTyIdx()); + mplExport.WriteNum(type.funcAttrs.GetAttrFlag()); size_t size = type.GetParamTypeList().size(); mplExport.WriteNum(size); for (size_t i = 0; i < size; ++i) { - mplExport.OutputType(type.GetNthParamType(i), canUseTypename); + mplExport.OutputType(type.GetNthParamType(i)); } size = type.GetParamAttrsList().size(); mplExport.WriteNum(size); @@ -203,13 +203,13 @@ void OutputTypeFunction(const MIRType &ty, BinaryMplExport &mplExport, bool canU } } -void OutputTypeParam(const MIRType &ty, BinaryMplExport &mplExport, bool) { +void OutputTypeParam(const MIRType &ty, BinaryMplExport &mplExport) { const auto &type = static_cast(ty); mplExport.WriteNum(kBinKindTypeParam); mplExport.OutputTypeBase(type); } -void OutputTypeInstantVector(const MIRType &ty, BinaryMplExport &mplExport, bool) { +void OutputTypeInstantVector(const MIRType &ty, BinaryMplExport &mplExport) { const auto &type = static_cast(ty); mplExport.WriteNum(kBinKindTypeInstantVector); mplExport.OutputTypeBase(type); @@ -217,15 +217,15 @@ void OutputTypeInstantVector(const MIRType &ty, BinaryMplExport &mplExport, bool mplExport.OutputTypePairs(type); } -void OutputTypeGenericInstant(const MIRType &ty, BinaryMplExport &mplExport, bool canUseTypename) { +void OutputTypeGenericInstant(const MIRType &ty, BinaryMplExport &mplExport) { const auto &type = static_cast(ty); mplExport.WriteNum(kBinKindTypeGenericInstant); mplExport.OutputTypeBase(type); mplExport.OutputTypePairs(type); - mplExport.OutputType(type.GetGenericTyIdx(), canUseTypename); + mplExport.OutputType(type.GetGenericTyIdx()); } -void OutputTypeBitField(const MIRType &ty, BinaryMplExport &mplExport, bool) { +void OutputTypeBitField(const MIRType &ty, BinaryMplExport &mplExport) { const auto &type = static_cast(ty); mplExport.WriteNum(kBinKindTypeBitField); mplExport.OutputTypeBase(type); @@ -233,7 +233,7 @@ void OutputTypeBitField(const MIRType &ty, BinaryMplExport &mplExport, bool) { } // for Struct/StructIncomplete/Union -void OutputTypeStruct(const MIRType &ty, BinaryMplExport &mplExport, bool) { +void OutputTypeStruct(const MIRType &ty, BinaryMplExport &mplExport) { const auto &type = static_cast(ty); mplExport.WriteNum(kBinKindTypeStruct); mplExport.OutputTypeBase(type); @@ -249,7 +249,7 @@ void OutputTypeStruct(const MIRType &ty, BinaryMplExport &mplExport, bool) { } } -void OutputTypeClass(const MIRType &ty, BinaryMplExport &mplExport, bool) { +void OutputTypeClass(const MIRType &ty, BinaryMplExport &mplExport) { const auto &type = static_cast(ty); mplExport.WriteNum(kBinKindTypeClass); mplExport.OutputTypeBase(type); @@ -264,7 +264,7 @@ void OutputTypeClass(const MIRType &ty, BinaryMplExport &mplExport, bool) { } } -void OutputTypeInterface(const MIRType &ty, BinaryMplExport &mplExport, bool) { +void OutputTypeInterface(const MIRType &ty, BinaryMplExport &mplExport) { const auto &type = static_cast(ty); mplExport.WriteNum(kBinKindTypeInterface); mplExport.OutputTypeBase(type); @@ -279,7 +279,7 @@ void OutputTypeInterface(const MIRType &ty, BinaryMplExport &mplExport, bool) { } } -void OutputTypeConstString(const MIRType &ty, BinaryMplExport&, bool) { +void OutputTypeConstString(const MIRType &ty, BinaryMplExport&) { ASSERT(false, "Type's kind not yet implemented: %d", ty.GetKind()); (void)ty; } @@ -397,7 +397,7 @@ void BinaryMplExport::DumpBuf(const std::string &name) { void BinaryMplExport::OutputConstBase(const MIRConst &constVal) { WriteNum(constVal.GetKind()); - OutputTypeViaTypeName(constVal.GetType().GetTypeIndex()); + OutputType(constVal.GetType().GetTypeIndex()); } void BinaryMplExport::OutputConst(MIRConst *constVal) { @@ -470,8 +470,8 @@ void BinaryMplExport::OutputPragma(const MIRPragma &p) { WriteNum(p.GetKind()); WriteNum(p.GetVisibility()); OutputStr(p.GetStrIdx()); - OutputType(p.GetTyIdx(), false); - OutputType(p.GetTyIdxEx(), false); + OutputType(p.GetTyIdx()); + OutputType(p.GetTyIdxEx()); WriteNum(p.GetParamNum()); size_t size = p.GetElementVector().size(); WriteNum(size); @@ -488,7 +488,7 @@ void BinaryMplExport::OutputTypeBase(const MIRType &type) { void BinaryMplExport::OutputFieldPair(const FieldPair &fp) { OutputStr(fp.first); // GStrIdx - OutputType(fp.second.first, false); // TyIdx + OutputType(fp.second.first); // TyIdx FieldAttrs fa = fp.second.second; WriteNum(fa.GetAttrFlag()); WriteNum(fa.GetAlignValue()); @@ -511,7 +511,7 @@ void BinaryMplExport::OutputMethodPair(const MethodPair &memPool) { MIRSymbol *funcSt = GlobalTables::GetGsymTable().GetSymbolFromStidx(memPool.first.Idx()); CHECK_FATAL(funcSt != nullptr, "Pointer funcSt is nullptr, can't get symbol! Check it!"); WriteAsciiStr(GlobalTables::GetStrTable().GetStringFromStrIdx(funcSt->GetNameStrIdx())); - OutputType(memPool.second.first, false); // TyIdx + OutputType(memPool.second.first); // TyIdx WriteNum(memPool.second.second.GetAttrFlag()); // FuncAttrs } @@ -539,7 +539,7 @@ void BinaryMplExport::OutputStructTypeData(const MIRStructType &type) { void BinaryMplExport::OutputImplementedInterfaces(const std::vector &interfaces) { WriteNum(interfaces.size()); for (const TyIdx &tyIdx : interfaces) { - OutputType(tyIdx, false); + OutputType(tyIdx); } } @@ -571,7 +571,7 @@ void BinaryMplExport::OutputPragmaVec(const std::vector &pragmaVec) } void BinaryMplExport::OutputClassTypeData(const MIRClassType &type) { - OutputType(type.GetParentTyIdx(), false); + OutputType(type.GetParentTyIdx()); OutputImplementedInterfaces(type.GetInterfaceImplemented()); OutputInfoIsString(type.GetInfoIsString()); if (!inIPA) { @@ -601,6 +601,7 @@ void BinaryMplExport::Init() { symMark[nullptr] = 0; funcMark[nullptr] = 0; eaNodeMark[nullptr] = 0; + curFunc = nullptr; for (uint32 pti = static_cast(PTY_begin); pti < static_cast(PTY_end); ++pti) { typMark[GlobalTables::GetTypeTable().GetTypeFromTyIdx(TyIdx(pti))] = pti; } @@ -612,7 +613,7 @@ void BinaryMplExport::OutputSymbol(MIRSymbol *sym) { return; } - auto it = symMark.find(sym); + std::unordered_map::iterator it = symMark.find(sym); if (it != symMark.end()) { WriteNum(-(it->second)); return; @@ -645,7 +646,7 @@ void BinaryMplExport::OutputSymbol(MIRSymbol *sym) { if (sym->GetSKind() == kStVar || sym->GetSKind() == kStFunc) { OutputSrcPos(sym->GetSrcPosition()); } - OutputTypeViaTypeName(sym->GetTyIdx()); + OutputType(sym->GetTyIdx()); } void BinaryMplExport::OutputFunction(PUIdx puIdx) { @@ -671,7 +672,7 @@ void BinaryMplExport::OutputFunction(PUIdx puIdx) { MIRSymbol *funcSt = GlobalTables::GetGsymTable().GetSymbolFromStidx(func->GetStIdx().Idx()); CHECK_FATAL(funcSt != nullptr, "Pointer funcSt is nullptr, cannot get symbol! Check it!"); OutputSymbol(funcSt); - OutputTypeViaTypeName(func->GetMIRFuncType()->GetTypeIndex()); + OutputType(func->GetMIRFuncType()->GetTypeIndex()); WriteNum(func->GetFuncAttrs().GetAttrFlag()); auto &attributes = func->GetFuncAttrs(); @@ -684,12 +685,12 @@ void BinaryMplExport::OutputFunction(PUIdx puIdx) { } WriteNum(func->GetFlag()); - OutputTypeViaTypeName(func->GetClassTyIdx()); + OutputType(func->GetClassTyIdx()); // output formal parameter information WriteNum(static_cast(func->GetFormalDefVec().size())); for (FormalDef formalDef : func->GetFormalDefVec()) { OutputStr(formalDef.formalStrIdx); - OutputType(formalDef.formalTyIdx, false); + OutputType(formalDef.formalTyIdx); WriteNum(static_cast(formalDef.formalAttrs.GetAttrFlag())); } // store Side Effect for each func @@ -751,15 +752,20 @@ void BinaryMplExport::WriteHeaderField(uint64 contentIdx) { WriteNum(mod.GetID()); if (mod.GetFlavor() == kFlavorLmbc) { WriteNum(mod.GetGlobalMemSize()); + WriteNum(mod.IsWithDbgInfo()); } WriteNum(mod.GetNumFuncs()); WriteAsciiStr(mod.GetEntryFuncName()); OutputInfoVector(mod.GetFileInfo(), mod.GetFileInfoIsString()); - WriteNum(static_cast(mod.GetSrcFileInfo().size())); - for (uint32 i = 0; i < mod.GetSrcFileInfo().size(); i++) { - OutputStr(mod.GetSrcFileInfo()[i].first); - WriteNum(mod.GetSrcFileInfo()[i].second); + if (mod.IsWithDbgInfo()) { + WriteNum(static_cast(mod.GetSrcFileInfo().size())); + for (uint32 i = 0; i < mod.GetSrcFileInfo().size(); i++) { + OutputStr(mod.GetSrcFileInfo()[i].first); + WriteNum(mod.GetSrcFileInfo()[i].second); + } + } else { + Write(0); } WriteNum(static_cast(mod.GetImportFiles().size())); @@ -795,7 +801,7 @@ void BinaryMplExport::WriteTypeField(uint64 contentIdx, bool useClassList) { auto *structType = static_cast(type); // skip imported class/interface and incomplete types if (!structType->IsImported() && !structType->IsIncomplete()) { - OutputType(curTyidx, false); + OutputType(curTyidx); ++size; } } @@ -803,7 +809,7 @@ void BinaryMplExport::WriteTypeField(uint64 contentIdx, bool useClassList) { } else { uint32 idx = GlobalTables::GetTypeTable().lastDefaultTyIdx.GetIdx(); for (idx = idx + 1; idx < GlobalTables::GetTypeTable().GetTypeTableSize(); idx++) { - OutputType(TyIdx(idx), false); + OutputType(TyIdx(idx)); size++; } } @@ -884,7 +890,7 @@ void BinaryMplExport::WriteSeField() { GlobalTables::GetGsymTable().GetSymbolFromStrIdx(GlobalTables::GetStrTable().GetStrIdxFromName(funcStr)); MIRFunction *func = (funcSymbol != nullptr) ? GetMIRModule().GetMIRBuilder()->GetFunctionFromSymbol(*funcSymbol) : nullptr; - OutputType(func->GetReturnTyIdx(), false); + OutputType(func->GetReturnTyIdx()); } ++size; } @@ -1102,7 +1108,7 @@ void BinaryMplExport::WriteSymField(uint64 contentIdx) { MIRSymKind sKind = s->GetSKind(); if (s->IsDeleted() || storageClass == kScUnused || (s->GetIsImported() && !s->GetAppearsInCode()) || - (storageClass == kScExtern && sKind == kStFunc)) { + (sKind == kStFunc && (storageClass == kScExtern || !s->GetAppearsInCode()))) { continue; } OutputSymbol(s); @@ -1213,8 +1219,6 @@ void BinaryMplExport::Export(const std::string &fname, std::unordered_setIsNameIsLocal() && ty->GetNameStrIdx() != GStrIdx(0)) { - WriteNum(kBinKindTypeViaTypename); - OutputStr(ty->GetNameStrIdx()); - return; - } - auto func = CreateProductFunction(ty->GetKind()); if (func != nullptr) { - func(*ty, *this, canUseTypename); + func(*ty, *this); } else { ASSERT(false, "Type's kind not yet implemented: %d", ty->GetKind()); } diff --git a/src/mapleall/maple_ir/src/bin_mpl_import.cpp b/src/mapleall/maple_ir/src/bin_mpl_import.cpp index 50779027df..1f79751ed6 100644 --- a/src/mapleall/maple_ir/src/bin_mpl_import.cpp +++ b/src/mapleall/maple_ir/src/bin_mpl_import.cpp @@ -129,11 +129,13 @@ MIRConst *BinaryMplImport::ImportConst(MIRFunction *func) { } case kBinKindConstAddrofFunc: { PUIdx puIdx = ImportFunction(); + MIRFunction *f = GlobalTables::GetFunctionTable().GetFuncTable()[puIdx]; + f->GetFuncSymbol()->SetAppearsInCode(true); mod.SetCurFunction(func); return memPool->New(puIdx, *type); } case kBinKindConstAddrofLabel: { - LabelIdx lidx = static_cast(ReadNum()); + LabelIdx lidx = ImportLabel(func); PUIdx puIdx = func->GetPuidx(); MIRLblConst *lblConst = memPool->New(lidx, puIdx, *type); (void)func->GetLabelTab()->addrTakenLabels.insert(lidx); @@ -541,19 +543,6 @@ TyIdx BinaryMplImport::ImportType(bool forPointedType) { CHECK_FATAL(static_cast(-tag) < typTab.size(), "index out of bounds"); return typTab.at(static_cast(-tag)); } - if (tag == kBinKindTypeViaTypename) { - GStrIdx typenameStrIdx = ImportStr(); - TyIdx tyIdx = mod.GetTypeNameTab()->GetTyIdxFromGStrIdx(typenameStrIdx); - if (tyIdx != 0) { - typTab.push_back(tyIdx); - return tyIdx; - } - MIRTypeByName ltype(typenameStrIdx); - ltype.SetNameIsLocal(false); - MIRType *type = GlobalTables::GetTypeTable().GetOrCreateMIRTypeNode(ltype); - typTab.push_back(type->GetTypeIndex()); - return type->GetTypeIndex(); - } PrimType primType = (PrimType)0; GStrIdx strIdx(0); bool nameIsLocal = false; @@ -580,13 +569,6 @@ TyIdx BinaryMplImport::ImportType(bool forPointedType) { } return origType->GetTypeIndex(); } - case kBinKindTypeByName: { - MIRTypeByName type(strIdx); - type.SetNameIsLocal(nameIsLocal); - MIRType *origType = &InsertInTypeTables(type); - typTab.push_back(origType->GetTypeIndex()); - return origType->GetTypeIndex(); - } case kBinKindTypeFArray: { MIRFarrayType type(strIdx); type.SetNameIsLocal(nameIsLocal); @@ -629,7 +611,7 @@ TyIdx BinaryMplImport::ImportType(bool forPointedType) { size_t idx = typTab.size(); typTab.push_back(TyIdx(0)); type.SetRetTyIdx(ImportType()); - type.SetVarArgs(ReadNum()); + type.funcAttrs.SetAttrFlag(ReadNum()); int64 size = ReadNum(); for (int64 i = 0; i < size; ++i) { type.GetParamTypeList().push_back(ImportType()); @@ -737,19 +719,6 @@ TyIdx BinaryMplImport::ImportTypeNonJava() { CHECK_FATAL(static_cast(-tag) < typTab.size(), "index out of bounds"); return typTab[static_cast(-tag)]; } - if (tag == kBinKindTypeViaTypename) { - GStrIdx typenameStrIdx = ImportStr(); - TyIdx tyIdx = mod.GetTypeNameTab()->GetTyIdxFromGStrIdx(typenameStrIdx); - if (tyIdx != 0) { - typTab.push_back(tyIdx); - return tyIdx; - } - MIRTypeByName ltype(typenameStrIdx); - ltype.SetNameIsLocal(false); - MIRType *type = GlobalTables::GetTypeTable().GetOrCreateMIRTypeNode(ltype); - typTab.push_back(type->GetTypeIndex()); - return type->GetTypeIndex(); - } PrimType primType = (PrimType)0; GStrIdx strIdx(0); bool nameIsLocal = false; @@ -771,12 +740,6 @@ TyIdx BinaryMplImport::ImportTypeNonJava() { GlobalTables::GetTypeTable().CreateMirTypeNodeAt(type, tyIdxUsed, &mod, false, false); return tyIdxUsed; } - case kBinKindTypeByName: { - MIRTypeByName type(strIdx); - type.SetNameIsLocal(nameIsLocal); - GlobalTables::GetTypeTable().CreateMirTypeNodeAt(type, tyIdxUsed, &mod, false, false); - return tyIdxUsed; - } case kBinKindTypeFArray: { MIRFarrayType type(strIdx); type.SetNameIsLocal(nameIsLocal); @@ -808,7 +771,7 @@ TyIdx BinaryMplImport::ImportTypeNonJava() { MIRFuncType type(strIdx); type.SetNameIsLocal(nameIsLocal); type.SetRetTyIdx(ImportTypeNonJava()); - type.SetVarArgs(ReadNum()); + type.funcAttrs.SetAttrFlag(ReadNum()); int64 size = ReadNum(); for (int64 i = 0; i < size; ++i) { type.GetParamTypeList().push_back(ImportTypeNonJava()); @@ -1159,6 +1122,7 @@ void BinaryMplImport::ReadHeaderField() { mod.SetID(static_cast(ReadNum())); if (mod.GetFlavor() == kFlavorLmbc) { mod.SetGlobalMemSize(static_cast(ReadNum())); + mod.SetWithDbgInfo(static_cast(ReadNum())); } mod.SetNumFuncs(static_cast(ReadNum())); std::string inStr; diff --git a/src/mapleall/maple_ir/src/global_tables.cpp b/src/mapleall/maple_ir/src/global_tables.cpp index c7051c1257..2ee3711760 100644 --- a/src/mapleall/maple_ir/src/global_tables.cpp +++ b/src/mapleall/maple_ir/src/global_tables.cpp @@ -226,7 +226,9 @@ MIRType *TypeTable::GetOrCreateFunctionType(const TyIdx &retTyIdx, const std::ve const std::vector &vecAttrs, bool isVarg, const TypeAttrs &retAttrs) { MIRFuncType funcType(retTyIdx, vecType, vecAttrs, retAttrs); - funcType.SetVarArgs(isVarg); + if (isVarg) { + funcType.SetVarArgs(); + } TyIdx tyIdx = GetOrCreateMIRType(&funcType); ASSERT(tyIdx < typeTable.size(), "index out of range in TypeTable::GetOrCreateFunctionType"); return typeTable.at(tyIdx); diff --git a/src/mapleall/maple_ir/src/mir_builder.cpp b/src/mapleall/maple_ir/src/mir_builder.cpp index 20d46306c0..f1aa2583e4 100755 --- a/src/mapleall/maple_ir/src/mir_builder.cpp +++ b/src/mapleall/maple_ir/src/mir_builder.cpp @@ -835,6 +835,13 @@ IcallNode *MIRBuilder::CreateStmtIcall(const MapleVector &args) { return stmt; } +IcallNode *MIRBuilder::CreateStmtIcallproto(const MapleVector &args) { + auto *stmt = GetCurrentFuncCodeMp()->New(*GetCurrentFuncCodeMpAllocator(), OP_icallproto); + ASSERT(stmt != nullptr, "stmt is null"); + stmt->SetOpnds(args); + return stmt; +} + IcallNode *MIRBuilder::CreateStmtIcallAssigned(const MapleVector &args, const MIRSymbol &ret) { auto *stmt = GetCurrentFuncCodeMp()->New(*GetCurrentFuncCodeMpAllocator(), OP_icallassigned); CallReturnVector nrets(GetCurrentFuncCodeMpAllocator()->Adapter()); @@ -852,6 +859,23 @@ IcallNode *MIRBuilder::CreateStmtIcallAssigned(const MapleVector &arg return stmt; } +IcallNode *MIRBuilder::CreateStmtIcallprotoAssigned(const MapleVector &args, const MIRSymbol &ret) { + auto *stmt = GetCurrentFuncCodeMp()->New(*GetCurrentFuncCodeMpAllocator(), OP_icallprotoassigned); + CallReturnVector nrets(GetCurrentFuncCodeMpAllocator()->Adapter()); + CHECK_FATAL((ret.GetStorageClass() == kScAuto || ret.GetStorageClass() == kScFormal || + ret.GetStorageClass() == kScExtern || ret.GetStorageClass() == kScGlobal), + "unknown classtype! check it!"); + nrets.emplace_back(CallReturnPair(ret.GetStIdx(), RegFieldPair(0, 0))); + stmt->SetNumOpnds(args.size()); + stmt->GetNopnd().resize(stmt->GetNumOpnds()); + stmt->SetReturnVec(nrets); + for (size_t i = 0; i < stmt->GetNopndSize(); ++i) { + stmt->SetNOpndAt(i, args.at(i)); + } + stmt->SetRetTyIdx(ret.GetTyIdx()); + return stmt; +} + IntrinsiccallNode *MIRBuilder::CreateStmtIntrinsicCall(MIRIntrinsicID idx, const MapleVector &arguments, TyIdx tyIdx) { auto *stmt = GetCurrentFuncCodeMp()->New( diff --git a/src/mapleall/maple_ir/src/mir_function.cpp b/src/mapleall/maple_ir/src/mir_function.cpp index 9bff3cd66c..4ee30a2b6a 100644 --- a/src/mapleall/maple_ir/src/mir_function.cpp +++ b/src/mapleall/maple_ir/src/mir_function.cpp @@ -362,10 +362,8 @@ void MIRFunction::Dump(bool withoutBody) { LogInfo::MapleLogger() << " )"; } - if (module->GetFlavor() < kMmpl) { + if (module->GetFlavor() != kMmpl) { DumpFlavorLoweredThanMmpl(); - } else { - LogInfo::MapleLogger() << " () void"; } // codeMemPool is nullptr, means maple_ir has been released for memory's sake diff --git a/src/mapleall/maple_ir/src/mir_lower.cpp b/src/mapleall/maple_ir/src/mir_lower.cpp index 99dbd04c3f..9b8c3f8d92 100644 --- a/src/mapleall/maple_ir/src/mir_lower.cpp +++ b/src/mapleall/maple_ir/src/mir_lower.cpp @@ -530,6 +530,23 @@ BlockNode *MIRLower::LowerBlock(BlockNode &block) { case OP_doloop: newBlock->AppendStatementsFromBlock(*LowerDoloopStmt(static_cast(*stmt))); break; + case OP_icallassigned: + case OP_icall: { + if (mirModule.IsCModule()) { + // convert to icallproto/icallprotoassigned + IcallNode *ic = static_cast(stmt); + ic->SetOpCode(stmt->GetOpCode() == OP_icall ? OP_icallproto : OP_icallprotoassigned); + MIRFuncType *funcType = FuncTypeFromFuncPtrExpr(stmt->Opnd(0)); + CHECK_FATAL(funcType != nullptr, "MIRLower::LowerBlock: cannot find prototype for icall"); + ic->SetRetTyIdx(funcType->GetTypeIndex()); + MIRType *retType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(funcType->GetRetTyIdx()); + if (retType->GetPrimType() == PTY_agg && retType->GetSize() > 16) { + funcType->funcAttrs.SetAttr(FUNCATTR_firstarg_return); + } + } + newBlock->AddStatement(stmt); + break; + } case OP_block: tmp = LowerBlock(static_cast(*stmt)); newBlock->AppendStatementsFromBlock(*tmp); @@ -985,6 +1002,100 @@ void MIRLower::ExpandArrayMrt(MIRFunction &func) { } } +MIRFuncType *MIRLower::FuncTypeFromFuncPtrExpr(BaseNode *x) { + MIRFuncType *res = nullptr; + MIRFunction *func = mirModule.CurFunction(); + switch (x->GetOpCode()) { + case OP_regread: { + RegreadNode *regread = static_cast(x); + MIRPreg *preg = func->GetPregTab()->PregFromPregIdx(regread->GetRegIdx()); + // see if it is promoted from a symbol + if (preg->GetOp() == OP_dread) { + const MIRSymbol *symbol = preg->rematInfo.sym; + MIRType *mirType = symbol->GetType(); + if (preg->fieldID != 0) { + MIRStructType *structty = static_cast(mirType); + FieldPair thepair = structty->TraverseToField(preg->fieldID); + mirType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(thepair.second.first); + } + + if (mirType->GetKind() == kTypePointer) { + res = static_cast(mirType)->GetPointedFuncType(); + } + if (res != nullptr) { + break; + } + } + // check if a formal promoted to preg + for (FormalDef &formalDef : func->GetFormalDefVec()) { + if (!formalDef.formalSym->IsPreg()) { + continue; + } + if (formalDef.formalSym->GetPreg() == preg) { + MIRType *mirType = formalDef.formalSym->GetType(); + if (mirType->GetKind() == kTypePointer) { + res = static_cast(mirType)->GetPointedFuncType(); + } + break; + } + } + break; + } + case OP_dread: { + DreadNode *dread = static_cast(x); + MIRSymbol *symbol = func->GetLocalOrGlobalSymbol(dread->GetStIdx()); + MIRType *mirType = symbol->GetType(); + if (dread->GetFieldID() != 0) { + MIRStructType *structty = static_cast(mirType); + FieldPair thepair = structty->TraverseToField(dread->GetFieldID()); + mirType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(thepair.second.first); + } + if (mirType->GetKind() == kTypePointer) { + res = static_cast(mirType)->GetPointedFuncType(); + } + break; + } + case OP_iread: { + IreadNode *iread = static_cast(x); + MIRPtrType *ptrType = static_cast(iread->GetType()); + MIRType *mirType = ptrType->GetPointedType(); + if (mirType->GetKind() == kTypeFunction) { + res = static_cast(mirType); + } else if (mirType->GetKind() == kTypePointer) { + res = static_cast(mirType)->GetPointedFuncType(); + } + break; + } + case OP_addroffunc: { + AddroffuncNode *addrofFunc = static_cast(x); + PUIdx puIdx = addrofFunc->GetPUIdx(); + MIRFunction *f = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(puIdx); + res = f->GetMIRFuncType(); + break; + } + case OP_retype: { + MIRType *mirType = GlobalTables::GetTypeTable().GetTypeFromTyIdx( + static_cast(x)->GetTyIdx()); + if (mirType->GetKind() == kTypePointer) { + res = static_cast(mirType)->GetPointedFuncType(); + } + if (res == nullptr) { + res = FuncTypeFromFuncPtrExpr(x->Opnd(0)); + } + break; + } + case OP_select: { + res = FuncTypeFromFuncPtrExpr(x->Opnd(1)); + if (res == nullptr) { + res = FuncTypeFromFuncPtrExpr(x->Opnd(2)); + } + break; + } + default: CHECK_FATAL(false, "LMBCLowerer::FuncTypeFromFuncPtrExpr: NYI"); + } + return res; +} + const std::set MIRLower::kSetArrayHotFunc = {}; bool MIRLower::ShouldOptArrayMrt(const MIRFunction &func) { diff --git a/src/mapleall/maple_ir/src/mir_nodes.cpp b/src/mapleall/maple_ir/src/mir_nodes.cpp index 3bd3308295..9295964bd1 100755 --- a/src/mapleall/maple_ir/src/mir_nodes.cpp +++ b/src/mapleall/maple_ir/src/mir_nodes.cpp @@ -1196,7 +1196,7 @@ MIRType *IcallNode::GetCallReturnType() { if (op == OP_icall || op == OP_icallassigned) { return GlobalTables::GetTypeTable().GetTypeFromTyIdx(retTyIdx); } - // icallproto + // icallproto or icallprotoassigned MIRFuncType *funcType = static_cast( GlobalTables::GetTypeTable().GetTypeFromTyIdx(retTyIdx)); return GlobalTables::GetTypeTable().GetTypeFromTyIdx(funcType->GetRetTyIdx()); @@ -1221,7 +1221,7 @@ const MIRSymbol *IcallNode::GetCallReturnSymbol(const MIRModule &mod) const { void IcallNode::Dump(int32 indent, bool newline) const { StmtNode::DumpBase(indent); - if (op == OP_icallproto) { + if (op == OP_icallproto || op == OP_icallprotoassigned) { LogInfo::MapleLogger() << " "; GlobalTables::GetTypeTable().GetTypeFromTyIdx(retTyIdx)->Dump(indent + 1); } diff --git a/src/mapleall/maple_ir/src/mir_parser.cpp b/src/mapleall/maple_ir/src/mir_parser.cpp index 87ea494b4d..fc097e3e73 100755 --- a/src/mapleall/maple_ir/src/mir_parser.cpp +++ b/src/mapleall/maple_ir/src/mir_parser.cpp @@ -894,6 +894,7 @@ bool MIRParser::ParseStmtCall(StmtNodePtr &stmt) { callStmt->SetPUIdx(pIdx); MIRFunction *callee = GlobalTables::GetFunctionTable().GetFuncTable()[pIdx]; + callee->GetFuncSymbol()->SetAppearsInCode(true); if (callee->GetName() == "setjmp") { mod.CurFunction()->SetHasSetjmp(); } @@ -930,9 +931,14 @@ bool MIRParser::ParseStmtIcall(StmtNodePtr &stmt, Opcode op) { // . . . // dassign } // icallproto (, , ..., ) + // icallprotoassigned (, , ..., ) { + // dassign + // dassign + // . . . + // dassign } IcallNode *iCallStmt = mod.CurFuncCodeMemPool()->New(mod, op); lexer.NextToken(); - if (op == OP_icallproto) { + if (op == OP_icallproto || op == OP_icallprotoassigned) { TyIdx tyIdx(0); if (!ParseDerivedType(tyIdx)) { Error("error parsing type in ParseStmtIcall for icallproto at "); @@ -946,7 +952,7 @@ bool MIRParser::ParseStmtIcall(StmtNodePtr &stmt, Opcode op) { } iCallStmt->SetNOpnd(opndsVec); iCallStmt->SetNumOpnds(opndsVec.size()); - if (op == OP_icallassigned) { + if (op == OP_icallassigned || op == OP_icallprotoassigned) { CallReturnVector retsVec(mod.CurFuncCodeMemPoolAllocator()->Adapter()); if (!ParseCallReturns(retsVec)) { return false; @@ -970,6 +976,10 @@ bool MIRParser::ParseStmtIcallproto(StmtNodePtr &stmt) { return ParseStmtIcall(stmt, OP_icallproto); } +bool MIRParser::ParseStmtIcallprotoassigned(StmtNodePtr &stmt) { + return ParseStmtIcall(stmt, OP_icallprotoassigned); +} + bool MIRParser::ParseStmtIntrinsiccall(StmtNodePtr &stmt, bool isAssigned) { Opcode o = !isAssigned ? (lexer.GetTokenKind() == TK_intrinsiccall ? OP_intrinsiccall : OP_xintrinsiccall) : (lexer.GetTokenKind() == TK_intrinsiccallassigned ? OP_intrinsiccallassigned @@ -2011,18 +2021,6 @@ bool MIRParser::ParseStmtBlockForUpformalSize() { return true; } -bool MIRParser::ParseStmtBlockForOutParmSize() { - MIRFunction *fn = paramCurrFuncForParseStmtBlock; - lexer.NextToken(); - if (lexer.GetTokenKind() != TK_intconst) { - Error("expect integer after outparmsize but get "); - return false; - } - fn->SetOutParmSize(static_cast(lexer.GetTheIntVal())); - lexer.NextToken(); - return true; -} - bool MIRParser::ParseStmtBlockForModuleID() { MIRFunction *fn = paramCurrFuncForParseStmtBlock; lexer.NextToken(); @@ -3235,7 +3233,8 @@ bool MIRParser::ParseConstAddrLeafExpr(MIRConstPtr &cexpr) { } else if (expr->GetOpCode() == OP_addroffunc) { auto *aof = static_cast(expr); MIRFunction *f = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(aof->GetPUIdx()); - const MIRSymbol *fName = f->GetFuncSymbol(); + MIRSymbol *fName = f->GetFuncSymbol(); + fName->SetAppearsInCode(true); TyIdx ptyIdx = fName->GetTyIdx(); MIRPtrType ptrType(ptyIdx); ptyIdx = GlobalTables::GetTypeTable().GetOrCreateMIRType(&ptrType); @@ -3409,6 +3408,7 @@ std::map MIRParser::InitFuncPtrMapForPar funcPtrMap[TK_icall] = &MIRParser::ParseStmtIcall; funcPtrMap[TK_icallassigned] = &MIRParser::ParseStmtIcallassigned; funcPtrMap[TK_icallproto] = &MIRParser::ParseStmtIcallproto; + funcPtrMap[TK_icallprotoassigned] = &MIRParser::ParseStmtIcallprotoassigned; funcPtrMap[TK_intrinsiccall] = &MIRParser::ParseStmtIntrinsiccall; funcPtrMap[TK_intrinsiccallassigned] = &MIRParser::ParseStmtIntrinsiccallassigned; funcPtrMap[TK_xintrinsiccall] = &MIRParser::ParseStmtIntrinsiccall; @@ -3469,7 +3469,6 @@ std::map MIRParser::InitFuncPtrMapF funcPtrMap[TK_type] = &MIRParser::ParseStmtBlockForType; funcPtrMap[TK_framesize] = &MIRParser::ParseStmtBlockForFrameSize; funcPtrMap[TK_upformalsize] = &MIRParser::ParseStmtBlockForUpformalSize; - funcPtrMap[TK_outparmsize] = &MIRParser::ParseStmtBlockForOutParmSize; funcPtrMap[TK_moduleid] = &MIRParser::ParseStmtBlockForModuleID; funcPtrMap[TK_funcsize] = &MIRParser::ParseStmtBlockForFuncSize; funcPtrMap[TK_funcid] = &MIRParser::ParseStmtBlockForFuncID; diff --git a/src/mapleall/maple_ir/src/mir_type.cpp b/src/mapleall/maple_ir/src/mir_type.cpp index 64ee74b164..08180754b7 100644 --- a/src/mapleall/maple_ir/src/mir_type.cpp +++ b/src/mapleall/maple_ir/src/mir_type.cpp @@ -740,7 +740,9 @@ void MIRFuncType::Dump(int indent, bool dontUseName) const { if (!dontUseName && CheckAndDumpTypeName(nameStrIdx, nameIsLocal)) { return; } - LogInfo::MapleLogger() << "Dump(indent + 1); @@ -751,7 +753,7 @@ void MIRFuncType::Dump(int indent, bool dontUseName) const { LogInfo::MapleLogger() << ","; } } - if (isVarArgs) { + if (IsVarargs()) { LogInfo::MapleLogger() << ", ..."; } LogInfo::MapleLogger() << ") "; @@ -1662,7 +1664,7 @@ bool MIRFuncType::EqualTo(const MIRType &type) const { } const auto &pType = static_cast(type); return (pType.retTyIdx == retTyIdx && pType.paramTypeList == paramTypeList && - pType.isVarArgs == isVarArgs && pType.paramAttrsList == paramAttrsList && + pType.funcAttrs == funcAttrs && pType.paramAttrsList == paramAttrsList && pType.retAttrs == retAttrs); } diff --git a/src/mapleall/maple_ir/src/parser.cpp b/src/mapleall/maple_ir/src/parser.cpp index 4587c26fbe..755f120f95 100644 --- a/src/mapleall/maple_ir/src/parser.cpp +++ b/src/mapleall/maple_ir/src/parser.cpp @@ -229,9 +229,7 @@ bool MIRParser::ParsePseudoReg(PrimType primType, PregIdx &pRegIdx) { MIRPreg *preg = curfunc->GetPregTab()->PregFromPregIdx(pRegIdx); if (primType != kPtyInvalid) { if (preg->GetPrimType() != primType) { - if ((primType == PTY_ref || primType == PTY_ptr) && - (preg->GetPrimType() == PTY_ref || preg->GetPrimType() == PTY_ptr)) { - ; // PTY_ref and PTY_ptr are compatible with each other + if (IsAddress(preg->GetPrimType()) && IsAddress(primType)) { } else { Error("inconsistent preg primitive type at "); return false; @@ -1299,6 +1297,15 @@ bool MIRParser::ParsePointType(TyIdx &tyIdx) { // in function pointer specification and member function prototypes inside // structs and classes bool MIRParser::ParseFuncType(TyIdx &tyIdx) { + // parse function attributes + FuncAttrs fAttrs; + if (lexer.GetTokenKind() != TK_lparen) { + if (!ParseFuncAttrs(fAttrs)) { + Error("bad function attribute specification in function type at "); + return false; + } + } + // parse parameters if (lexer.GetTokenKind() != TK_lparen) { Error("expect ( parse function type parameters but get "); @@ -1359,7 +1366,10 @@ bool MIRParser::ParseFuncType(TyIdx &tyIdx) { return false; } MIRFuncType functype(retTyIdx, vecTyIdx, vecAttrs, retTypeAttrs); - functype.SetVarArgs(varargs); + functype.funcAttrs = fAttrs; + if (varargs) { + functype.SetVarArgs(); + } tyIdx = GlobalTables::GetTypeTable().GetOrCreateMIRType(&functype); return true; } diff --git a/src/mapleall/maple_me/include/lmbc_lower.h b/src/mapleall/maple_me/include/lmbc_lower.h index 9462204fd7..bbeaabf098 100644 --- a/src/mapleall/maple_me/include/lmbc_lower.h +++ b/src/mapleall/maple_me/include/lmbc_lower.h @@ -40,10 +40,7 @@ class LMBCLowerer { void LowerIassign(IassignNode *, BlockNode *); void LowerAggIassign(IassignNode *, MIRType *type, int32 offset, BlockNode *); void LowerReturn(NaryStmtNode *retNode, BlockNode *newblk); - MIRFuncType *FuncTypeFromFuncPtrExpr(BaseNode *x); - void LowerCall(NaryStmtNode *callNode, BlockNode *newblk); BlockNode *LowerBlock(BlockNode *); - void LoadFormalsAssignedToPregs(); void LowerFunction(); MIRModule *mirModule; diff --git a/src/mapleall/maple_me/include/lmbc_memlayout.h b/src/mapleall/maple_me/include/lmbc_memlayout.h index 7cea863a22..0f2bf5cbea 100644 --- a/src/mapleall/maple_me/include/lmbc_memlayout.h +++ b/src/mapleall/maple_me/include/lmbc_memlayout.h @@ -31,8 +31,8 @@ typedef enum { MS_actual, // for the outgoing parameters MS_local, // for all local variables and temporaries MS_FPbased, // addressed via offset from the frame pointer - MS_SPbased, // addressed via offset from the stack pointer MS_GPbased, // addressed via offset from the global pointer + MS_largeStructActual, // for storing large struct actuals passed by value for ARM CPU } MemSegmentKind; class MemSegment; @@ -64,15 +64,10 @@ class MemSegment { class LMBCMemLayout { public: - uint32 FindLargestActualArea(void); - uint32 FindLargestActualArea(StmtNode *, int &); - LMBCMemLayout(MIRFunction *f, MapleAllocator *mallocator) + LMBCMemLayout(MIRFunction *f, MemSegment *segGP, MapleAllocator *mallocator) : func(f), - seg_upformal(MS_upformal), - seg_formal(MS_formal), - seg_actual(MS_actual), + seg_GPbased(segGP), seg_FPbased(MS_FPbased), - seg_SPbased(MS_SPbased), sym_alloc_table(mallocator->Adapter()) { sym_alloc_table.resize(f->GetSymTab()->GetSymbolTableSize()); } @@ -81,67 +76,25 @@ class LMBCMemLayout { void LayoutStackFrame(void); int32 StackFrameSize(void) const { - return seg_SPbased.size - seg_FPbased.size; - } - - int32 UpformalSize(void) const { - return seg_upformal.size; + return -seg_FPbased.size; } MIRFunction *func; - MemSegment seg_upformal; - MemSegment seg_formal; - MemSegment seg_actual; + MemSegment *seg_GPbased; MemSegment seg_FPbased; - MemSegment seg_SPbased; MapleVector sym_alloc_table; // index is StIdx }; class GlobalMemLayout { public: - GlobalMemLayout(maplebe::BECommon *b, MIRModule *mod, MapleAllocator *mallocator); + GlobalMemLayout(MIRModule *mod, MapleAllocator *mallocator); ~GlobalMemLayout() {} MemSegment seg_GPbased; MapleVector sym_alloc_table; // index is StIdx - - private: - void FillScalarValueInMap(uint32 startaddress, PrimType pty, MIRConst *c); - void FillTypeValueInMap(uint32 startaddress, MIRType *ty, MIRConst *c); - void FillSymbolValueInMap(const MIRSymbol *sym); - - maplebe::BECommon *be; MIRModule *mirModule; }; -// for specifying how a parameter is passed -struct PLocInfo { - int32 memoffset; - int32 memsize; -}; - -// for processing an incoming or outgoing parameter list -class ParmLocator { - public: - explicit ParmLocator() : parmNum(0), lastMemOffset(0) {} - - ~ParmLocator() {} - - void LocateNextParm(const MIRType *ty, PLocInfo &ploc); - - private: - int32 parmNum; // number of all types of parameters processed so far - int32 lastMemOffset; -}; - -// given the type of the return value, determines the return mechanism -class ReturnMechanism { - public: - ReturnMechanism(const MIRType *retty); - bool fake_first_parm; // whether returning in memory via fake first parameter - PrimType ptype0; // the primitive type stored in retval0 -}; - } /* namespace maple */ #endif /* MAPLEME_INCLUDE_LMBC_MEMLAYOUT_H */ diff --git a/src/mapleall/maple_me/src/alias_class.cpp b/src/mapleall/maple_me/src/alias_class.cpp index 788a9a3540..1a63043e27 100644 --- a/src/mapleall/maple_me/src/alias_class.cpp +++ b/src/mapleall/maple_me/src/alias_class.cpp @@ -1017,7 +1017,9 @@ void AliasClass::ApplyUnionForCopies(StmtNode &stmt) { } case OP_asm: case OP_icall: - case OP_icallassigned: { + case OP_icallassigned: + case OP_icallproto: + case OP_icallprotoassigned: { for (uint32 i = 0; i < stmt.NumOpnds(); ++i) { const AliasInfo &ainfo = CreateAliasInfoExpr(*stmt.Opnd(i)); if (stmt.GetOpCode() != OP_asm && i == 0) { @@ -2563,6 +2565,7 @@ void AliasClass::GenericInsertMayDefUse(StmtNode &stmt, BBId bbID) { case OP_customcallassigned: case OP_polymorphiccallassigned: case OP_icallassigned: + case OP_icallprotoassigned: case OP_virtualcall: case OP_virtualicall: case OP_superclasscall: @@ -2570,7 +2573,8 @@ void AliasClass::GenericInsertMayDefUse(StmtNode &stmt, BBId bbID) { case OP_interfaceicall: case OP_customcall: case OP_polymorphiccall: - case OP_icall: { + case OP_icall: + case OP_icallproto: { InsertMayDefUseCall(stmt, bbID, false); return; } diff --git a/src/mapleall/maple_me/src/code_factoring.cpp b/src/mapleall/maple_me/src/code_factoring.cpp index 6cabb59adc..2f40e7b821 100644 --- a/src/mapleall/maple_me/src/code_factoring.cpp +++ b/src/mapleall/maple_me/src/code_factoring.cpp @@ -122,7 +122,9 @@ bool FactoringOptimizer::IsIdenticalStmt(StmtNode *stmt1, StmtNode *stmt2) { break; } case OP_icall: - case OP_icallassigned: { + case OP_icallassigned: + case OP_icallproto: + case OP_icallprotoassigned: { auto *icall1 = static_cast(stmt1); auto *icall2 = static_cast(stmt2); if (icall1->GetRetTyIdx() != icall2->GetRetTyIdx() || diff --git a/src/mapleall/maple_me/src/demand_driven_alias_analysis.cpp b/src/mapleall/maple_me/src/demand_driven_alias_analysis.cpp index db34036937..50a25a6101 100644 --- a/src/mapleall/maple_me/src/demand_driven_alias_analysis.cpp +++ b/src/mapleall/maple_me/src/demand_driven_alias_analysis.cpp @@ -641,7 +641,9 @@ void PEGBuilder::BuildPEGNodeInStmt(const StmtNode *stmt) { break; } case OP_icall: - case OP_icallassigned: { + case OP_icallassigned: + case OP_icallproto: + case OP_icallprotoassigned: { BuildPEGNodeInIcall(static_cast(stmt)); break; } diff --git a/src/mapleall/maple_me/src/irmap_build.cpp b/src/mapleall/maple_me/src/irmap_build.cpp index cd801b7b5b..29afaca89b 100755 --- a/src/mapleall/maple_me/src/irmap_build.cpp +++ b/src/mapleall/maple_me/src/irmap_build.cpp @@ -806,7 +806,7 @@ MeStmt *IRMapBuild::BuildCallMeStmt(StmtNode &stmt, AccessSSANodes &ssaPart) { MeStmt *IRMapBuild::BuildNaryMeStmt(StmtNode &stmt, AccessSSANodes &ssaPart) { Opcode op = stmt.GetOpCode(); - NaryMeStmt *naryMeStmt = (op == OP_icall || op == OP_icallassigned) + NaryMeStmt *naryMeStmt = (op == OP_icall || op == OP_icallassigned || op == OP_icallproto || op == OP_icallprotoassigned) ? static_cast(irMap->NewInPool(&stmt)) : static_cast(irMap->NewInPool(&stmt)); auto &naryStmtNode = static_cast(stmt); @@ -821,6 +821,9 @@ MeStmt *IRMapBuild::BuildNaryMeStmt(StmtNode &stmt, AccessSSANodes &ssaPart) { if (propagater) { propagater->PropUpdateChiListDef(*naryMeStmt->GetChiList()); } + if (op == OP_icallproto || op == OP_icallprotoassigned) { + static_cast(naryMeStmt)->SetRetTyIdx(static_cast(stmt).GetRetTyIdx()); + } return naryMeStmt; } @@ -921,6 +924,8 @@ void IRMapBuild::InitMeStmtFactory() { RegisterFactoryFunction(OP_polymorphiccallassigned, &IRMapBuild::BuildCallMeStmt); RegisterFactoryFunction(OP_icall, &IRMapBuild::BuildNaryMeStmt); RegisterFactoryFunction(OP_icallassigned, &IRMapBuild::BuildNaryMeStmt); + RegisterFactoryFunction(OP_icallproto, &IRMapBuild::BuildNaryMeStmt); + RegisterFactoryFunction(OP_icallprotoassigned, &IRMapBuild::BuildNaryMeStmt); RegisterFactoryFunction(OP_intrinsiccall, &IRMapBuild::BuildNaryMeStmt); RegisterFactoryFunction(OP_xintrinsiccall, &IRMapBuild::BuildNaryMeStmt); RegisterFactoryFunction(OP_intrinsiccallwithtype, &IRMapBuild::BuildNaryMeStmt); diff --git a/src/mapleall/maple_me/src/irmap_emit.cpp b/src/mapleall/maple_me/src/irmap_emit.cpp index 824e7c7e53..7fcbd3804b 100755 --- a/src/mapleall/maple_me/src/irmap_emit.cpp +++ b/src/mapleall/maple_me/src/irmap_emit.cpp @@ -412,7 +412,7 @@ MIRFunction &CallMeStmt::GetTargetFunction() { } StmtNode &CallMeStmt::EmitStmt(SSATab &ssaTab) { - if (GetOp() != OP_icall && GetOp() != OP_icallassigned) { + if (GetOp() != OP_icall && GetOp() != OP_icallassigned && GetOp() != OP_icallproto && GetOp() != OP_icallprotoassigned) { auto *callNode = ssaTab.GetModule().CurFunction()->GetCodeMempool()->New(ssaTab.GetModule(), Opcode(GetOp())); callNode->SetPUIdx(puIdx); @@ -496,6 +496,9 @@ StmtNode &IcallMeStmt::EmitStmt(SSATab &ssaTab) { } } } + if (GetOp() == OP_icallproto || GetOp() == OP_icallprotoassigned) { + icallNode->SetRetTyIdx(retTyIdx); + } return *icallNode; } diff --git a/src/mapleall/maple_me/src/lfo_dep_test.cpp b/src/mapleall/maple_me/src/lfo_dep_test.cpp index 19a523e138..ac3340e843 100644 --- a/src/mapleall/maple_me/src/lfo_dep_test.cpp +++ b/src/mapleall/maple_me/src/lfo_dep_test.cpp @@ -66,6 +66,8 @@ void LfoDepInfo::CreateDoloopInfo(BlockNode *block, DoloopInfo *parent) { case OP_callassigned: case OP_icall: case OP_icallassigned: + case OP_icallproto: + case OP_icallprotoassigned: case OP_return: case OP_throw: case OP_asm: diff --git a/src/mapleall/maple_me/src/lmbc_lower.cpp b/src/mapleall/maple_me/src/lmbc_lower.cpp index a155b25fa4..f5893447ba 100644 --- a/src/mapleall/maple_me/src/lmbc_lower.cpp +++ b/src/mapleall/maple_me/src/lmbc_lower.cpp @@ -22,16 +22,12 @@ using namespace std; PregIdx LMBCLowerer::GetSpecialRegFromSt(const MIRSymbol *sym) { MIRStorageClass storageClass = sym->GetStorageClass(); PregIdx specreg = 0; - if (storageClass == kScAuto || storageClass == kScFormal) { + if (storageClass == kScAuto) { CHECK(sym->GetStIndex() < memlayout->sym_alloc_table.size(), "index out of range in LMBCLowerer::GetSpecialRegFromSt"); SymbolAlloc symalloc = memlayout->sym_alloc_table[sym->GetStIndex()]; - if (symalloc.mem_segment->kind == MS_upformal || symalloc.mem_segment->kind == MS_formal || - symalloc.mem_segment->kind == MS_FPbased) { + if (symalloc.mem_segment->kind == MS_FPbased) { specreg = -kSregFp; - } else if (symalloc.mem_segment->kind == MS_actual || - symalloc.mem_segment->kind == MS_SPbased) { - specreg = -kSregSp; } else { CHECK_FATAL(false, "LMBCLowerer::LowerDread: bad memory layout for local variable"); } @@ -46,6 +42,7 @@ PregIdx LMBCLowerer::GetSpecialRegFromSt(const MIRSymbol *sym) { BaseNode *LMBCLowerer::LowerAddrof(AddrofNode *expr) { MIRSymbol *symbol = func->GetLocalOrGlobalSymbol(expr->GetStIdx()); + symbol->ResetIsDeleted(); int32 offset = 0; if (expr->GetFieldID() != 0) { MIRStructType *structty = static_cast(symbol->GetType()); @@ -66,6 +63,7 @@ BaseNode *LMBCLowerer::LowerAddrof(AddrofNode *expr) { BaseNode *LMBCLowerer::LowerDread(AddrofNode *expr) { MIRSymbol *symbol = func->GetLocalOrGlobalSymbol(expr->GetStIdx()); + symbol->ResetIsDeleted(); PrimType symty = symbol->GetType()->GetPrimType(); int32 offset = 0; if (expr->GetFieldID() != 0) { @@ -96,20 +94,22 @@ BaseNode *LMBCLowerer::LowerDread(AddrofNode *expr) { BaseNode *LMBCLowerer::LowerDreadoff(DreadoffNode *dreadoff) { MIRSymbol *symbol = func->GetLocalOrGlobalSymbol(dreadoff->stIdx); + symbol->ResetIsDeleted(); if (!symbol->LMBCAllocateOffSpecialReg()) { return dreadoff; } + PrimType symty = symbol->GetType()->GetPrimType(); PregIdx spcreg = GetSpecialRegFromSt(symbol); if (spcreg == -kSregFp) { CHECK_FATAL(symbol->IsLocal(), "load from fp non local?"); - IreadFPoffNode *ireadoff = mirBuilder->CreateExprIreadFPoff( - dreadoff->GetPrimType(), memlayout->sym_alloc_table[symbol->GetStIndex()].offset + dreadoff->offset); + IreadFPoffNode *ireadoff = mirBuilder->CreateExprIreadFPoff(symty, + memlayout->sym_alloc_table[symbol->GetStIndex()].offset + dreadoff->offset); return ireadoff; } else { BaseNode *rrn = mirBuilder->CreateExprRegread(LOWERED_PTR_TYPE, spcreg); SymbolAlloc &symalloc = symbol->IsLocal() ? memlayout->sym_alloc_table[symbol->GetStIndex()] : globmemlayout->sym_alloc_table[symbol->GetStIndex()]; - IreadoffNode *ireadoff = mirBuilder->CreateExprIreadoff(dreadoff->GetPrimType(), symalloc.offset + dreadoff->offset, rrn); + IreadoffNode *ireadoff = mirBuilder->CreateExprIreadoff(symty, symalloc.offset + dreadoff->offset, rrn); return ireadoff; } } @@ -129,14 +129,14 @@ static MIRType *GetPointedToType(const MIRPtrType *pointerty) { BaseNode *LMBCLowerer::LowerIread(IreadNode *expr) { int32 offset = 0; + MIRPtrType *ptrType = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(expr->GetTyIdx())); + MIRType *type = ptrType->GetPointedType(); if (expr->GetFieldID() != 0) { - MIRType *type = GlobalTables::GetTypeTable().GetTypeFromTyIdx(expr->GetTyIdx()); - MIRStructType *structty = - static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx( - static_cast(type)->GetPointedTyIdx())); + MIRStructType *structty = static_cast(type); offset = becommon->GetFieldOffset(*structty, expr->GetFieldID()).first; + type = structty->GetFieldType(expr->GetFieldID()); } - BaseNode *ireadoff = mirBuilder->CreateExprIreadoff(expr->GetPrimType(), offset, expr->Opnd(0)); + BaseNode *ireadoff = mirBuilder->CreateExprIreadoff(type->GetPrimType(), offset, expr->Opnd(0)); return ireadoff; } @@ -165,6 +165,7 @@ BaseNode *LMBCLowerer::LowerExpr(BaseNode *expr) { return LowerAddrof(static_cast(expr)); case OP_addrofoff: { MIRSymbol *symbol = func->GetLocalOrGlobalSymbol(static_cast(expr)->stIdx); + symbol->ResetIsDeleted(); CHECK_FATAL(!symbol->LMBCAllocateOffSpecialReg(), "LMBCLowerer:: illegal addrofoff instruction"); break; @@ -199,6 +200,7 @@ void LMBCLowerer::LowerAggDassign(const DassignNode *dsnode, MIRType *lhsty, // generate lhs address expression BaseNode *lhs = nullptr; MIRSymbol *symbol = func->GetLocalOrGlobalSymbol(dsnode->GetStIdx()); + symbol->ResetIsDeleted(); if (!symbol->LMBCAllocateOffSpecialReg()) { lhs = mirBuilder->CreateExprDreadoff(OP_addrofoff, LOWERED_PTR_TYPE, *symbol, offset); } else { @@ -218,6 +220,7 @@ void LMBCLowerer::LowerAggDassign(const DassignNode *dsnode, MIRType *lhsty, void LMBCLowerer::LowerDassign(DassignNode *dsnode, BlockNode *newblk) { MIRSymbol *symbol = func->GetLocalOrGlobalSymbol(dsnode->GetStIdx()); + symbol->ResetIsDeleted(); MIRType *symty = symbol->GetType(); int32 offset = 0; if (dsnode->GetFieldID() != 0) { @@ -259,6 +262,7 @@ void LMBCLowerer::LowerDassign(DassignNode *dsnode, BlockNode *newblk) { void LMBCLowerer::LowerDassignoff(DassignoffNode *dsnode, BlockNode *newblk) { MIRSymbol *symbol = func->GetLocalOrGlobalSymbol(dsnode->stIdx); + symbol->ResetIsDeleted(); CHECK_FATAL(dsnode->Opnd(0)->GetPrimType() != PTY_agg, "LowerDassignoff: agg primitive type NYI"); BaseNode *rhs = LowerExpr(dsnode->Opnd(0)); if (!symbol->LMBCAllocateOffSpecialReg()) { @@ -334,6 +338,9 @@ void LMBCLowerer::LowerIassign(IassignNode *iassign, BlockNode *newblk) { } if (iassign->GetRHS()->GetPrimType() != PTY_agg) { PrimType ptypused = type->GetPrimType(); + if (ptypused == PTY_agg) { + ptypused = iassign->GetRHS()->GetPrimType(); + } IassignoffNode *iassignoff = mirBuilder->CreateStmtIassignoff(ptypused, offset, iassign->addrExpr, @@ -347,15 +354,20 @@ void LMBCLowerer::LowerIassign(IassignNode *iassign, BlockNode *newblk) { // called only if the return has > 1 operand; assume prior lowering already // converted any return of structs to be via fake parameter void LMBCLowerer::LowerReturn(NaryStmtNode *retNode, BlockNode *newblk) { - CHECK_FATAL(retNode->NumOpnds() <= 2, "LMBCLowerer::LowerReturn: more than 2 return values NYI"); - for (int i = 0; i < retNode->NumOpnds(); i++) { - CHECK_FATAL(retNode->Opnd(i)->GetPrimType() != PTY_agg, - "LMBCLowerer::LowerReturn: return of aggregate needs to be handled first"); - // insert regassign for the returned value - BaseNode *rhs = LowerExpr(retNode->Opnd(i)); - RegassignNode *regasgn = mirBuilder->CreateStmtRegassign(rhs->GetPrimType(), - i == 0 ? -kSregRetval0 : -kSregRetval1, - rhs); + if (retNode->Opnd(0)->GetPrimType() != PTY_agg) { + CHECK_FATAL(retNode->NumOpnds() <= 2, "LMBCLowerer::LowerReturn: more than 2 return values NYI"); + for (int i = 0; i < retNode->NumOpnds(); i++) { + // insert regassign for the returned value + PrimType ptyp = retNode->Opnd(i)->GetPrimType(); + BaseNode *rhs = LowerExpr(retNode->Opnd(i)); + RegassignNode *regasgn = mirBuilder->CreateStmtRegassign(ptyp, + i == 0 ? -kSregRetval0 : -kSregRetval1, + rhs); + newblk->AddStatement(regasgn); + } + } else { // handle return of small struct using only %%retval0 + BaseNode *rhs = LowerExpr(retNode->Opnd(0)); + RegassignNode *regasgn = mirBuilder->CreateStmtRegassign(PTY_agg, -kSregRetval0, rhs); newblk->AddStatement(regasgn); } retNode->GetNopnd().clear(); // remove the return operands @@ -363,178 +375,6 @@ void LMBCLowerer::LowerReturn(NaryStmtNode *retNode, BlockNode *newblk) { newblk->AddStatement(retNode); } -MIRFuncType *LMBCLowerer::FuncTypeFromFuncPtrExpr(BaseNode *x) { - MIRFuncType *res = nullptr; - switch (x->GetOpCode()) { - case OP_regread: { - RegreadNode *regread = static_cast(x); - MIRPreg *preg = func->GetPregTab()->PregFromPregIdx(regread->GetRegIdx()); - // see if it is promoted from a symbol - if (preg->GetOp() == OP_dread) { - const MIRSymbol *symbol = preg->rematInfo.sym; - MIRType *mirType = symbol->GetType(); - if (preg->fieldID != 0) { - MIRStructType *structty = static_cast(mirType); - FieldPair thepair = structty->TraverseToField(preg->fieldID); - mirType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(thepair.second.first); - } - - if (mirType->GetKind() == kTypePointer) { - res = static_cast(mirType)->GetPointedFuncType(); - } - if (res != nullptr) { - break; - } - } - // check if a formal promoted to preg - for (FormalDef &formalDef : func->GetFormalDefVec()) { - if (!formalDef.formalSym->IsPreg()) { - continue; - } - if (formalDef.formalSym->GetPreg() == preg) { - MIRType *mirType = formalDef.formalSym->GetType(); - if (mirType->GetKind() == kTypePointer) { - res = static_cast(mirType)->GetPointedFuncType(); - } - break; - } - } - break; - } - case OP_dread: { - DreadNode *dread = static_cast(x); - MIRSymbol *symbol = func->GetLocalOrGlobalSymbol(dread->GetStIdx()); - MIRType *mirType = symbol->GetType(); - if (dread->GetFieldID() != 0) { - MIRStructType *structty = static_cast(mirType); - FieldPair thepair = structty->TraverseToField(dread->GetFieldID()); - mirType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(thepair.second.first); - } - if (mirType->GetKind() == kTypePointer) { - res = static_cast(mirType)->GetPointedFuncType(); - } - break; - } - case OP_iread: { - IreadNode *iread = static_cast(x); - MIRPtrType *ptrType = static_cast(iread->GetType()); - MIRType *mirType = ptrType->GetPointedType(); - if (mirType->GetKind() == kTypePointer) { - res = static_cast(mirType)->GetPointedFuncType(); - } - break; - } - case OP_addroffunc: { - AddroffuncNode *addrofFunc = static_cast(x); - PUIdx puIdx = addrofFunc->GetPUIdx(); - MIRFunction *f = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(puIdx); - res = f->GetMIRFuncType(); - break; - } - case OP_retype: { - MIRType *mirType = GlobalTables::GetTypeTable().GetTypeFromTyIdx( - static_cast(x)->GetTyIdx()); - if (mirType->GetKind() == kTypePointer) { - res = static_cast(mirType)->GetPointedFuncType(); - } - if (res == nullptr) { - res = FuncTypeFromFuncPtrExpr(x->Opnd(0)); - } - break; - } - case OP_select: { - res = FuncTypeFromFuncPtrExpr(x->Opnd(1)); - if (res == nullptr) { - res = FuncTypeFromFuncPtrExpr(x->Opnd(2)); - } - break; - } - default: CHECK_FATAL(false, "LMBCLowerer::FuncTypeFromFuncPtrExpr: NYI"); - } - return res; -} - -void LMBCLowerer::LowerCall(NaryStmtNode *naryStmt, BlockNode *newblk) { - // go through each parameter - uint32 i = 0; - if (naryStmt->GetOpCode() == OP_icall || naryStmt->GetOpCode() == OP_icallassigned) { - i = 1; - } - ParmLocator parmlocator; - for (; i < naryStmt->NumOpnds(); i++) { - BaseNode *opnd = naryStmt->Opnd(i); - MIRType *ty = nullptr; - // get ty for this parameter - if (opnd->GetPrimType() != PTY_agg) { - ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(static_cast(opnd->GetPrimType())); - } else { - Opcode opnd_opcode = opnd->GetOpCode(); - CHECK_FATAL(opnd_opcode == OP_dread || opnd_opcode == OP_iread, ""); - if (opnd_opcode == OP_dread) { - AddrofNode *dread = static_cast(opnd); - MIRSymbol *sym = func->GetLocalOrGlobalSymbol(dread->GetStIdx()); - ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(sym->GetTyIdx()); - if (dread->GetFieldID() != 0) { - CHECK_FATAL(ty->IsStructType(), ""); - FieldPair thepair = static_cast(ty)->TraverseToField(dread->GetFieldID()); - ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(thepair.second.first); - } - } else { // OP_iread - IreadNode *iread = static_cast(opnd); - ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(iread->GetTyIdx()); - CHECK_FATAL(ty->GetKind() == kTypePointer, ""); - ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx( - static_cast(ty)->GetPointedTyIdx()); - if (iread->GetFieldID() != 0) { - CHECK_FATAL(ty->IsStructType(), ""); - FieldPair thepair = static_cast(ty)->TraverseToField(iread->GetFieldID()); - ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(thepair.second.first); - } - } - } - PLocInfo ploc; - parmlocator.LocateNextParm(ty, ploc); - if (opnd->GetPrimType() != PTY_agg) { - IassignFPoffNode *iass = mirBuilder->CreateStmtIassignFPoff(OP_iassignspoff, - opnd->GetPrimType(), - ploc.memoffset, - LowerExpr(opnd)); - newblk->AddStatement(iass); - } else { - BlkassignoffNode *bass = - mirModule->CurFuncCodeMemPool()->New(ploc.memoffset, ploc.memsize); - bass->SetAlign(std::min(ty->GetAlign(), 8u)); - bass->SetBOpnd(mirBuilder->CreateExprRegread(LOWERED_PTR_TYPE, -kSregSp), 0); - // the operand is either OP_dread or OP_iread; use its address instead - if (opnd->GetOpCode() == OP_dread) { - opnd->SetOpCode(OP_addrof); - } else { - opnd->SetOpCode(OP_iaddrof); - } - opnd->SetPrimType(LOWERED_PTR_TYPE); - bass->SetBOpnd(LowerExpr(opnd), 1); - newblk->AddStatement(bass); - } - } - BaseNode *opnd0 = nullptr; - if (naryStmt->GetOpCode() == OP_icall || naryStmt->GetOpCode() == OP_icallassigned) { - opnd0 = naryStmt->Opnd(0); - naryStmt->GetNopnd().clear(); // remove the call operands - // convert to OP_icallproto by finding the function prototype and record in stmt - naryStmt->SetOpCode(OP_icallproto); - MIRFuncType *funcType = FuncTypeFromFuncPtrExpr(opnd0); - CHECK_FATAL(funcType != nullptr, "LMBCLowerer::LowerCall: cannot find prototype for icall"); - static_cast(naryStmt)->SetRetTyIdx(funcType->GetTypeIndex()); - // add back the function pointer operand - naryStmt->GetNopnd().push_back(LowerExpr(opnd0)); - naryStmt->SetNumOpnds(1); - } else { - naryStmt->GetNopnd().clear(); // remove the call operands - naryStmt->SetNumOpnds(0); - } - newblk->AddStatement(naryStmt); -} - BlockNode *LMBCLowerer::LowerBlock(BlockNode *block) { BlockNode *newblk = mirModule->CurFuncCodeMemPool()->New(); if (!block->GetFirst()) { @@ -569,10 +409,6 @@ BlockNode *LMBCLowerer::LowerBlock(BlockNode *block) { } else { LowerReturn(retNode, newblk); } - } - case OP_call: - case OP_icall: { - LowerCall(static_cast(stmt), newblk); break; } default: { @@ -587,29 +423,19 @@ BlockNode *LMBCLowerer::LowerBlock(BlockNode *block) { return newblk; } -void LMBCLowerer::LoadFormalsAssignedToPregs() { - // go through each formals - for (int32 i = func->GetFormalDefVec().size()-1; i >= 0; i--) { - MIRSymbol *formalSt = func->GetFormalDefVec()[i].formalSym; - if (formalSt->GetSKind() != kStPreg) { - continue; +void LMBCLowerer::LowerFunction() { + // set extern global vars' isDeleted field; will reset when visited + MapleVector::const_iterator sit = mirModule->GetSymbolDefOrder().begin(); + for (; sit != mirModule->GetSymbolDefOrder().end(); ++sit) { + MIRSymbol *s = GlobalTables::GetGsymTable().GetSymbolFromStidx(sit->Idx()); + if (s->GetSKind() == kStVar && s->GetStorageClass() == kScExtern && !s->HasPotentialAssignment()) { + s->SetIsDeleted(); } - MIRPreg *preg = formalSt->GetPreg(); - uint32 stindex = formalSt->GetStIndex(); - PrimType pty = formalSt->GetType()->GetPrimType(); - IreadFPoffNode *ireadfpoff = mirBuilder->CreateExprIreadFPoff(pty, - memlayout->sym_alloc_table[stindex].offset); - RegassignNode *rass = mirBuilder->CreateStmtRegassign(pty, - func->GetPregTab()->GetPregIdxFromPregno(preg->GetPregNo()), ireadfpoff); - func->GetBody()->InsertFirst(rass); } -} -void LMBCLowerer::LowerFunction() { BlockNode *origbody = func->GetBody(); BlockNode *newbody = LowerBlock(origbody); func->SetBody(newbody); - LoadFormalsAssignedToPregs(); } } // namespace maple diff --git a/src/mapleall/maple_me/src/lmbc_memlayout.cpp b/src/mapleall/maple_me/src/lmbc_memlayout.cpp index e740c5d13f..b32acae493 100644 --- a/src/mapleall/maple_me/src/lmbc_memlayout.cpp +++ b/src/mapleall/maple_me/src/lmbc_memlayout.cpp @@ -13,146 +13,40 @@ * See the MulanPSL - 2.0 for more details. */ -// For each function being compiled, lay out its parameters, return values and -// local variables on its stack frame. This involves determining how parameters -// and return values are passed from analyzing their types. -// -// Allocate all the global variables within the global memory block which is -// addressed via offset from the global pointer GP during execution. Allocate -// this block pointed to by mirModule.globalBlkMap and perform the static -// initializations. +// For each function being compiled, lay out its local variables on its stack +// frame. Allocate all the global variables within the global memory block +// which is addressed via offset from the global pointer GP during execution. +// Allocate this block pointed to by mirModule.globalBlkMap. #include "lmbc_memlayout.h" #include "mir_symbol.h" namespace maple { -uint32 LMBCMemLayout::FindLargestActualArea(StmtNode *stmt, int &maxActualSize) { - if (!stmt) { - return maxActualSize; - } - Opcode opcode = stmt->op; - switch (opcode) { - case OP_block: { - BlockNode *blcknode = static_cast(stmt); - for (StmtNode &s : blcknode->GetStmtNodes()) { - FindLargestActualArea(&s, maxActualSize); - } - break; - } - case OP_if: { - IfStmtNode *ifnode = static_cast(stmt); - FindLargestActualArea(ifnode->GetThenPart(), maxActualSize); - FindLargestActualArea(ifnode->GetElsePart(), maxActualSize); - break; - } - case OP_doloop: { - FindLargestActualArea(static_cast(stmt)->GetDoBody(), maxActualSize); - break; - } - case OP_dowhile: - case OP_while: - FindLargestActualArea(static_cast(stmt)->GetBody(), maxActualSize); - break; - case OP_call: - case OP_icall: - case OP_intrinsiccall: { - ParmLocator parmlocator; // instantiate a parm locator - NaryStmtNode *callstmt = static_cast(stmt); - for (uint32 i = 0; i < callstmt->NumOpnds(); i++) { - BaseNode *opnd = callstmt->Opnd(i); - CHECK_FATAL(opnd->GetPrimType() != PTY_void, ""); - MIRType *ty = nullptr; - if (opnd->GetPrimType() != PTY_agg) { - ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx( - static_cast(opnd->GetPrimType())); - } else { - Opcode opnd_opcode = opnd->GetOpCode(); - CHECK_FATAL(opnd_opcode == OP_dread || opnd_opcode == OP_iread, ""); - if (opnd_opcode == OP_dread) { - AddrofNode *dread = static_cast(opnd); - MIRSymbol *sym = func->GetLocalOrGlobalSymbol(dread->GetStIdx()); - ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(sym->GetTyIdx()); - if (dread->GetFieldID() != 0) { - CHECK_FATAL(ty->IsStructType(), "expect struct or class or union"); - FieldPair thepair = - static_cast(ty)->TraverseToField(dread->GetFieldID()); - ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(thepair.second.first); - } - } else { // OP_iread - IreadNode *iread = static_cast(opnd); - ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(iread->GetTyIdx()); - CHECK_FATAL(ty->GetKind() == kTypePointer, ""); - ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx( - static_cast(ty)->GetPointedTyIdx()); - if (iread->GetFieldID() != 0) { - CHECK_FATAL(ty->IsStructType(), "expect struct or class or union"); - FieldPair thepair = - static_cast(ty)->TraverseToField(iread->GetFieldID()); - ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(thepair.second.first); - } - } - } - PLocInfo ploc; - parmlocator.LocateNextParm(ty, ploc); - maxActualSize = std::max(maxActualSize, ploc.memoffset + ploc.memsize); - maxActualSize = maplebe::RoundUp(maxActualSize, GetPrimTypeSize(PTY_ptr)); - } - break; - } - default: - return maxActualSize; - } - maxActualSize = maplebe::RoundUp(maxActualSize, GetPrimTypeSize(PTY_ptr)); - return maxActualSize; -} - -// go over all outgoing calls in the function body and get the maximum space -// needed for storing the actuals based on the actual parameters and the ABI; -// this assumes that all nesting of statements has been removed, so that all -// the statements are at only one block level -uint32 LMBCMemLayout::FindLargestActualArea(void) { - int32 maxActualSize = 0; - FindLargestActualArea(func->GetBody(), maxActualSize); - return static_cast(maxActualSize); -} +constexpr size_t kVarargSaveAreaSize = 192; void LMBCMemLayout::LayoutStackFrame(void) { - MIRSymbol *sym = nullptr; - // go through formal parameters - ParmLocator parmlocator; // instantiate a parm locator - PLocInfo ploc; - for (uint32 i = 0; i < func->GetFormalDefVec().size(); i++) { - FormalDef formalDef = func->GetFormalDefAt(i); - sym = formalDef.formalSym; - MIRType *ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(formalDef.formalTyIdx); - parmlocator.LocateNextParm(ty, ploc); - uint32 stindex = sym->GetStIndex(); - // always passed in memory, so allocate in seg_upformal - sym_alloc_table[stindex].mem_segment = &seg_upformal; - seg_upformal.size = maplebe::RoundUp(seg_upformal.size, ty->GetAlign()); - sym_alloc_table[stindex].offset = seg_upformal.size; - seg_upformal.size += ty->GetSize(); - seg_upformal.size = maplebe::RoundUp(seg_upformal.size, GetPrimTypeSize(PTY_ptr)); + if (func->IsVarargs()) { + seg_FPbased.size -= kVarargSaveAreaSize; } - // allocate seg_formal in seg_FPbased - seg_formal.how_alloc.mem_segment = &seg_FPbased; - seg_FPbased.size = maplebe::RoundDown(seg_FPbased.size, GetPrimTypeSize(PTY_ptr)); - seg_FPbased.size -= seg_formal.size; - seg_FPbased.size = maplebe::RoundDown(seg_FPbased.size, GetPrimTypeSize(PTY_ptr)); - seg_formal.how_alloc.offset = seg_FPbased.size; - // allocate the local variables uint32 symtabsize = func->GetSymTab()->GetSymbolTableSize(); for (uint32 i = 0; i < symtabsize; i++) { - sym = func->GetSymTab()->GetSymbolFromStIdx(i); + MIRSymbol *sym = func->GetSymTab()->GetSymbolFromStIdx(i); if (!sym) { continue; } if (sym->IsDeleted()) { continue; } + if (sym->GetStorageClass() == kScPstatic && sym->LMBCAllocateOffSpecialReg()) { + uint32 stindex = sym->GetStIndex(); + sym_alloc_table[stindex].mem_segment = seg_GPbased; + seg_GPbased->size = maplebe::RoundUp(seg_GPbased->size, sym->GetType()->GetAlign()); + sym_alloc_table[stindex].offset = seg_GPbased->size; + seg_GPbased->size += sym->GetType()->GetSize(); + } if (sym->GetStorageClass() != kScAuto) { continue; } @@ -162,160 +56,10 @@ void LMBCMemLayout::LayoutStackFrame(void) { seg_FPbased.size = maplebe::RoundDown(seg_FPbased.size, sym->GetType()->GetAlign()); sym_alloc_table[stindex].offset = seg_FPbased.size; } - seg_FPbased.size = maplebe::RoundDown(seg_FPbased.size, GetPrimTypeSize(PTY_ptr)); - - // allocate seg_actual for storing the outgoing parameters; this requires - // going over all outgoing calls and get the maximum space needed for the - // actuals - seg_actual.size = FindLargestActualArea(); - func->SetOutParmSize(seg_actual.size); - - // allocate seg_actual in seg_SPbased - seg_actual.how_alloc.mem_segment = &seg_SPbased; - seg_actual.how_alloc.offset = seg_SPbased.size; - seg_SPbased.size = maplebe::RoundUp(seg_SPbased.size, GetPrimTypeSize(PTY_ptr)); - seg_SPbased.size += seg_actual.size; - seg_SPbased.size = maplebe::RoundUp(seg_SPbased.size, GetPrimTypeSize(PTY_ptr)); -} - -inline uint8 GetU8Const(MIRConst *c) { - MIRIntConst *intconst = static_cast(c); - return static_cast(intconst->GetValue()); -} - -inline uint16 GetU16Const(MIRConst *c) { - MIRIntConst *intconst = static_cast(c); - return static_cast(intconst->GetValue()); -} - -inline uint32 GetU32Const(MIRConst *c) { - MIRIntConst *intconst = static_cast(c); - return static_cast(intconst->GetValue()); -} - -inline uint64 GetU64Const(MIRConst *c) { - MIRIntConst *intconst = static_cast(c); - return static_cast(intconst->GetValue()); -} - -inline uint32 GetF32Const(MIRConst *c) { - MIRFloatConst *floatconst = static_cast(c); - return static_cast(floatconst->GetIntValue()); -} - -inline uint64 GetF64Const(MIRConst *c) { - MIRDoubleConst *doubleconst = static_cast(c); - return static_cast(doubleconst->GetIntValue()); -} - -void GlobalMemLayout::FillScalarValueInMap(uint32 startaddress, PrimType pty, MIRConst *c) { - switch (pty) { - case PTY_u1: - case PTY_u8: - case PTY_i8: { - uint8 *p = &mirModule->GetGlobalBlockMap()[startaddress]; - *p = GetU8Const(c); - break; - } - case PTY_u16: - case PTY_i16: { - uint16 *p = (uint16 *)(&mirModule->GetGlobalBlockMap()[startaddress]); - *p = GetU16Const(c); - break; - } - case PTY_u32: - case PTY_i32: { - uint32 *p = (uint32 *)(&mirModule->GetGlobalBlockMap()[startaddress]); - *p = GetU32Const(c); - break; - } - case PTY_u64: - case PTY_i64: { - uint64 *p = (uint64 *)(&mirModule->GetGlobalBlockMap()[startaddress]); - *p = GetU64Const(c); - break; - } - case PTY_f32: { - uint32 *p = (uint32 *)(&mirModule->GetGlobalBlockMap()[startaddress]); - *p = GetF32Const(c); - break; - } - case PTY_f64: { - uint64 *p = (uint64 *)(&mirModule->GetGlobalBlockMap()[startaddress]); - *p = GetF64Const(c); - break; - } - default: - CHECK_FATAL(false, "FillScalarValueInMap: NYI"); - } - return; } -void GlobalMemLayout::FillTypeValueInMap(uint32 startaddress, MIRType *ty, MIRConst *c) { - switch (ty->GetKind()) { - case kTypeScalar: - FillScalarValueInMap(startaddress, ty->GetPrimType(), c); - break; - case kTypeArray: { - MIRArrayType *arraytype = static_cast(ty); - MIRType *elemtype = arraytype->GetElemType(); - int32 elemsize = elemtype->GetSize(); - MIRAggConst *aggconst = static_cast(c); - CHECK_FATAL(aggconst, "FillTypeValueInMap: inconsistent array initialization specification"); - MapleVector &constvec = aggconst->GetConstVec(); - for (MapleVector::iterator it = constvec.begin(); it != constvec.end(); - it++, startaddress += elemsize) { - FillTypeValueInMap(startaddress, elemtype, *it); - } - break; - } - case kTypeStruct: { - MIRStructType *structty = static_cast(ty); - MIRAggConst *aggconst = static_cast(c); - CHECK_FATAL(aggconst, "FillTypeValueInMap: inconsistent struct initialization specification"); - MapleVector &constvec = aggconst->GetConstVec(); - for (uint32 i = 0; i < constvec.size(); i++) { - uint32 fieldID = aggconst->GetFieldIdItem(i); - FieldPair thepair = structty->TraverseToField(fieldID); - MIRType *fieldty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(thepair.second.first); - uint32 offset = be->GetFieldOffset(*structty, fieldID).first; - FillTypeValueInMap(startaddress + offset, fieldty, constvec[i]); - } - break; - } - case kTypeClass: { - MIRClassType *classty = static_cast(ty); - MIRAggConst *aggconst = static_cast(c); - CHECK_FATAL(aggconst, "FillTypeValueInMap: inconsistent class initialization specification"); - MapleVector &constvec = aggconst->GetConstVec(); - for (uint32 i = 0; i < constvec.size(); i++) { - uint32 fieldID = aggconst->GetFieldIdItem(i); - FieldPair thepair = classty->TraverseToField(fieldID); - MIRType *fieldty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(thepair.second.first); - uint32 offset = be->GetFieldOffset(*classty, fieldID).first; - FillTypeValueInMap(startaddress + offset, fieldty, constvec[i]); - } - break; - } - default: - CHECK_FATAL(false, "FillTypeValueInMap: NYI"); - } -} - -void GlobalMemLayout::FillSymbolValueInMap(const MIRSymbol *sym) { - if (sym->GetKonst() == nullptr) { - return; - } - uint32 stindex = sym->GetStIndex(); - CHECK(stindex < sym_alloc_table.size(), - "index out of range in GlobalMemLayout::FillSymbolValueInMap"); - uint32 symaddress = sym_alloc_table[stindex].offset; - FillTypeValueInMap(symaddress, sym->GetType(), sym->GetKonst()); - return; -} - -GlobalMemLayout::GlobalMemLayout(maplebe::BECommon *b, MIRModule *mod, MapleAllocator *mallocator) : - seg_GPbased(MS_GPbased), sym_alloc_table(mallocator->Adapter()), be(b), mirModule(mod) { +GlobalMemLayout::GlobalMemLayout(MIRModule *mod, MapleAllocator *mallocator) : + seg_GPbased(MS_GPbased), sym_alloc_table(mallocator->Adapter()), mirModule(mod) { uint32 symtabsize = GlobalTables::GetGsymTable().GetSymbolTableSize(); sym_alloc_table.resize(symtabsize); MIRSymbol *sym = nullptr; @@ -329,6 +73,9 @@ GlobalMemLayout::GlobalMemLayout(maplebe::BECommon *b, MIRModule *mod, MapleAll if (sym->GetStorageClass() != kScGlobal && sym->GetStorageClass() != kScFstatic) { continue; } + if (!sym->LMBCAllocateOffSpecialReg()) { + continue; + } if (sym->GetType()->GetAlign() != curalign) { continue; } @@ -341,152 +88,6 @@ GlobalMemLayout::GlobalMemLayout(maplebe::BECommon *b, MIRModule *mod, MapleAll } seg_GPbased.size = maplebe::RoundUp(seg_GPbased.size, GetPrimTypeSize(PTY_ptr)); mirModule->SetGlobalMemSize(seg_GPbased.size); - // allocate the memory map for the GP block - mirModule->SetGlobalBlockMap( - static_cast(mirModule->GetMemPool()->Calloc(seg_GPbased.size))); - // perform initialization on globalblkmap - for (uint32 i = 0; i < symtabsize; i++) { - sym = GlobalTables::GetGsymTable().GetSymbolFromStidx(i); - if (!sym) { - continue; - } - if (sym->GetStorageClass() != kScGlobal && sym->GetStorageClass() != kScFstatic) { - continue; - } - } -} - -// LocateNextParm should be called with each parameter in the parameter list -// starting from the beginning, one call per parameter in sequence; it returns -// the information on how each parameter is passed in ploc -void ParmLocator::LocateNextParm(const MIRType *ty, PLocInfo &ploc) { - ploc.memoffset = maplebe::RoundUp(lastMemOffset, 8); - ploc.memsize = ty->GetSize(); - - uint32 rightpad = 0; - parmNum++; - - switch (ty->GetPrimType()) { - case PTY_u1: - case PTY_u8: - case PTY_i8: - case PTY_u16: - case PTY_i16: - rightpad = GetPrimTypeSize(PTY_i32) - ploc.memsize; - break; - case PTY_a32: - case PTY_u32: - case PTY_i32: - case PTY_a64: - case PTY_u64: - case PTY_i64: - case PTY_ptr: - case PTY_ref: -#ifdef DYNAMICLANG - case PTY_simplestr: - case PTY_simpleobj: - case PTY_dynany: - case PTY_dyni32: - case PTY_dynf64: - case PTY_dynstr: - case PTY_dynobj: - case PTY_dynundef: - case PTY_dynbool: - case PTY_dynf32: - case PTY_dynnone: - case PTY_dynnull: -#endif - break; - - case PTY_f32: - rightpad = GetPrimTypeSize(PTY_f64) - ploc.memsize; - break; - case PTY_c64: - case PTY_f64: - case PTY_v2i32: - case PTY_v4i16: - case PTY_v8i8: - case PTY_v2u32: - case PTY_v4u16: - case PTY_v8u8: - case PTY_v2f32: - break; - - case PTY_c128: - case PTY_v2i64: - case PTY_v4i32: - case PTY_v8i16: - case PTY_v16i8: - case PTY_v2u64: - case PTY_v4u32: - case PTY_v8u16: - case PTY_v16u8: - case PTY_v2f64: - case PTY_v4f32: - break; - - case PTY_agg: { - // compute rightpad - int32 paddedSize = maplebe::RoundUp(ploc.memsize, 8); - rightpad = paddedSize - ploc.memsize; - break; - } - default: - CHECK_FATAL(false, "unsupported type"); - } - - lastMemOffset = ploc.memoffset + ploc.memsize + rightpad; - return; -} - -// instantiated with the type of the function return value, it describes how -// the return value is to be passed back to the caller -ReturnMechanism::ReturnMechanism(const MIRType *retty) : fake_first_parm(false) { - switch (retty->GetPrimType()) { - case PTY_u1: - case PTY_u8: - case PTY_i8: - case PTY_u16: - case PTY_i16: - case PTY_a32: - case PTY_u32: - case PTY_i32: - case PTY_a64: - case PTY_u64: - case PTY_i64: - case PTY_f32: - case PTY_f64: -#ifdef DYNAMICLANG - case PTY_simplestr: - case PTY_simpleobj: - case PTY_dynany: - case PTY_dyni32: - case PTY_dynstr: - case PTY_dynobj: -#endif - ptype0 = retty->GetPrimType(); - return; - - case PTY_c64: - case PTY_c128: - fake_first_parm = true; - ptype0 = PTY_a32; - return; - - case PTY_agg: { - uint32 size = retty->GetSize(); - if (size > 4) { - fake_first_parm = true; - ptype0 = PTY_a32; - } else { - ptype0 = PTY_u32; - } - return; - } - - default: - return; - } } } // namespace maple diff --git a/src/mapleall/maple_me/src/me_cfg.cpp b/src/mapleall/maple_me/src/me_cfg.cpp index c1d452d10a..521cb1a944 100644 --- a/src/mapleall/maple_me/src/me_cfg.cpp +++ b/src/mapleall/maple_me/src/me_cfg.cpp @@ -260,6 +260,7 @@ bool MeCFG::FindUse(const StmtNode &stmt, StIdx stIdx) const { case OP_customcall: case OP_polymorphiccall: case OP_icall: + case OP_icallproto: case OP_intrinsiccall: case OP_xintrinsiccall: case OP_intrinsiccallwithtype: @@ -272,6 +273,7 @@ bool MeCFG::FindUse(const StmtNode &stmt, StIdx stIdx) const { case OP_customcallassigned: case OP_polymorphiccallassigned: case OP_icallassigned: + case OP_icallprotoassigned: case OP_intrinsiccallassigned: case OP_xintrinsiccallassigned: case OP_intrinsiccallwithtypeassigned: diff --git a/src/mapleall/maple_me/src/me_function.cpp b/src/mapleall/maple_me/src/me_function.cpp index 05181df796..a62f1a89a3 100755 --- a/src/mapleall/maple_me/src/me_function.cpp +++ b/src/mapleall/maple_me/src/me_function.cpp @@ -303,7 +303,9 @@ void MeFunction::CloneBBMeStmts(BB &srcBB, BB &destBB, std::map(&stmt); newStmt = irmap->NewInPool(static_cast(icallStmt), icallStmt->GetRetTyIdx(), icallStmt->GetStmtID()); diff --git a/src/mapleall/maple_me/src/me_lower_globals.cpp b/src/mapleall/maple_me/src/me_lower_globals.cpp index c14dd5c764..fdf2df8e3f 100644 --- a/src/mapleall/maple_me/src/me_lower_globals.cpp +++ b/src/mapleall/maple_me/src/me_lower_globals.cpp @@ -185,7 +185,12 @@ void MeLowerGlobals::Run() { MeExpr *addroffuncExpr = irMap->CreateAddroffuncMeExpr(callee.GetPuidx()); auto insertpos = callStmt.GetOpnds().begin(); callStmt.InsertOpnds(insertpos, addroffuncExpr); - IcallMeStmt *icallStmt = irMap->NewInPool(stmt.GetOp() == OP_call ? OP_icall : OP_icallassigned); + IcallMeStmt *icallStmt = nullptr; + if (func.GetMIRModule().IsCModule()) { + icallStmt = irMap->NewInPool(stmt.GetOp() == OP_call ? OP_icallproto : OP_icallprotoassigned); + } else { + icallStmt = irMap->NewInPool(stmt.GetOp() == OP_call ? OP_icall : OP_icallassigned); + } icallStmt->SetIsLive(callStmt.GetIsLive()); icallStmt->SetSrcPos(callStmt.GetSrcPosition()); for (MeExpr *o : callStmt.GetOpnds()) { @@ -193,7 +198,11 @@ void MeLowerGlobals::Run() { } icallStmt->GetMuList()->insert(callStmt.GetMuList()->begin(), callStmt.GetMuList()->end()); icallStmt->GetChiList()->insert(callStmt.GetChiList()->begin(), callStmt.GetChiList()->end()); - icallStmt->SetRetTyIdx(callee.GetReturnTyIdx()); + if (func.GetMIRModule().IsCModule()) { + icallStmt->SetRetTyIdx(callee.GetMIRFuncType()->GetTypeIndex()); + } else { + icallStmt->SetRetTyIdx(callee.GetReturnTyIdx()); + } if (stmt.GetOp() != OP_call) { if (callStmt.NeedDecref()) { icallStmt->EnableNeedDecref(); diff --git a/src/mapleall/maple_me/src/me_phase_manager.cpp b/src/mapleall/maple_me/src/me_phase_manager.cpp index 09a1b64e5a..a0b5419a8e 100644 --- a/src/mapleall/maple_me/src/me_phase_manager.cpp +++ b/src/mapleall/maple_me/src/me_phase_manager.cpp @@ -140,8 +140,8 @@ bool MeFuncPM::PhaseRun(maple::MIRModule &m) { } if (genLMBC) { m.SetFlavor(kFlavorLmbc); + GlobalMemLayout globalMemLayout(&m, &m.GetMPAllocator()); maplebe::BECommon beCommon(m); - GlobalMemLayout globalMemLayout(&beCommon, &m, &m.GetMPAllocator()); maplebe::CGLowerer cgLower(m, beCommon, false, false); cgLower.RegisterBuiltIns(); cgLower.RegisterExternalLibraryFunctions(); @@ -153,14 +153,15 @@ bool MeFuncPM::PhaseRun(maple::MIRModule &m) { cgLower.LowerFunc(*func); MemPool *layoutMp = memPoolCtrler.NewMemPool("layout mempool", true); MapleAllocator layoutAlloc(layoutMp); - LMBCMemLayout localMemLayout(func, &layoutAlloc); + LMBCMemLayout localMemLayout(func, &globalMemLayout.seg_GPbased, &layoutAlloc); localMemLayout.LayoutStackFrame(); LMBCLowerer lmbcLowerer(&m, &beCommon, func, &globalMemLayout, &localMemLayout); lmbcLowerer.LowerFunction(); func->SetFrameSize(localMemLayout.StackFrameSize()); - func->SetUpFormalSize(localMemLayout.UpformalSize()); memPoolCtrler.DeleteMemPool(layoutMp); } + globalMemLayout.seg_GPbased.size = maplebe::RoundUp(globalMemLayout.seg_GPbased.size, GetPrimTypeSize(PTY_ptr)); + m.SetGlobalMemSize(globalMemLayout.seg_GPbased.size); // output .lmbc BinaryMplt binMplt(m); std::string modFileName = m.GetFileName(); diff --git a/src/mapleall/maple_me/src/me_rc_lowering.cpp b/src/mapleall/maple_me/src/me_rc_lowering.cpp index 8b3897a1c6..edf6f45509 100644 --- a/src/mapleall/maple_me/src/me_rc_lowering.cpp +++ b/src/mapleall/maple_me/src/me_rc_lowering.cpp @@ -1144,6 +1144,7 @@ void RCLowering::HandleArguments() { firstBB->InsertMeStmtBefore(firstMeStmt, incCall); } sym->SetLocalRefVar(); + mirFunc->GetFormalDefVec()[i].formalAttrs.SetAttr(ATTR_localrefvar); for (auto *stmt : rets) { std::vector opnds = { argVar }; diff --git a/src/mapleall/maple_me/src/me_rename2preg.cpp b/src/mapleall/maple_me/src/me_rename2preg.cpp index 9549dff004..eddc9704b9 100644 --- a/src/mapleall/maple_me/src/me_rename2preg.cpp +++ b/src/mapleall/maple_me/src/me_rename2preg.cpp @@ -317,6 +317,7 @@ void SSARename2Preg::Rename2PregStmt(MeStmt *stmt) { case OP_customcallassigned: case OP_polymorphiccallassigned: case OP_icallassigned: + case OP_icallprotoassigned: case OP_intrinsiccallassigned: case OP_xintrinsiccallassigned: case OP_intrinsiccallwithtypeassigned: { diff --git a/src/mapleall/maple_me/src/me_side_effect.cpp b/src/mapleall/maple_me/src/me_side_effect.cpp index ad493a9e01..2df2f0a2c5 100644 --- a/src/mapleall/maple_me/src/me_side_effect.cpp +++ b/src/mapleall/maple_me/src/me_side_effect.cpp @@ -932,6 +932,7 @@ bool IpaSideEffect::UpdateSideEffectWithStmt(MeStmt &meStmt, case OP_customcallassigned: case OP_polymorphiccallassigned: case OP_icallassigned: + case OP_icallprotoassigned: case OP_superclasscallassigned: case OP_asm: { hasPrivateDef = hasThrException = true; @@ -958,7 +959,8 @@ bool IpaSideEffect::UpdateSideEffectWithStmt(MeStmt &meStmt, case OP_interfaceicall: case OP_customcall: case OP_polymorphiccall: - case OP_icall: { + case OP_icall: + case OP_icallproto: { hasPrivateDef = hasThrException = true; SetHasDef(); for (size_t i = 0; i < meStmt.NumMeStmtOpnds(); ++i) { diff --git a/src/mapleall/maple_me/src/me_stmt_pre.cpp b/src/mapleall/maple_me/src/me_stmt_pre.cpp index 9e2325f142..55888c9bce 100755 --- a/src/mapleall/maple_me/src/me_stmt_pre.cpp +++ b/src/mapleall/maple_me/src/me_stmt_pre.cpp @@ -966,7 +966,9 @@ void MeStmtPre::BuildWorkListBB(BB *bb) { break; } case OP_icall: - case OP_icallassigned: { + case OP_icallassigned: + case OP_icallproto: + case OP_icallprotoassigned: { auto &icallMeStmt = static_cast(stmt); VersionStackChiListUpdate(*icallMeStmt.GetChiList()); break; diff --git a/src/mapleall/maple_me/src/pme_emit.cpp b/src/mapleall/maple_me/src/pme_emit.cpp index 227cb6a761..52e1df6beb 100755 --- a/src/mapleall/maple_me/src/pme_emit.cpp +++ b/src/mapleall/maple_me/src/pme_emit.cpp @@ -485,10 +485,12 @@ StmtNode* PreMeEmitter::EmitPreMeStmt(MeStmt *mestmt, BaseNode *parent) { return callnode; } case OP_icall: - case OP_icallassigned: { + case OP_icallassigned: + case OP_icallproto: + case OP_icallprotoassigned: { IcallMeStmt *icallMeStmt = static_cast (mestmt); IcallNode *icallnode = - codeMP->New(*codeMPAlloc, OP_icallassigned, icallMeStmt->GetRetTyIdx()); + codeMP->New(*codeMPAlloc, OP_icallprotoassigned, icallMeStmt->GetRetTyIdx()); for (uint32 i = 0; i < icallMeStmt->GetOpnds().size(); i++) { icallnode->GetNopnd().push_back(EmitPreMeExpr(icallMeStmt->GetOpnd(i), icallnode)); } @@ -509,6 +511,9 @@ StmtNode* PreMeEmitter::EmitPreMeStmt(MeStmt *mestmt, BaseNode *parent) { icallnode->SetRetTyIdx(TyIdx(preg->GetPrimType())); } } + if (mestmt->GetOp() == OP_icallproto || mestmt->GetOp() == OP_icallprotoassigned) { + icallnode->SetRetTyIdx(icallMeStmt->GetRetTyIdx()); + } icallnode->CopySafeRegionAttr(mestmt->GetStmtAttr()); icallnode->SetOriginalID(mestmt->GetOriginalId()); PreMeStmtExtensionMap[icallnode->GetStmtID()] = pmeExt; diff --git a/src/mapleall/maple_me/src/ssa_devirtual.cpp b/src/mapleall/maple_me/src/ssa_devirtual.cpp index 15a609e427..f46e8e06ce 100644 --- a/src/mapleall/maple_me/src/ssa_devirtual.cpp +++ b/src/mapleall/maple_me/src/ssa_devirtual.cpp @@ -534,7 +534,9 @@ void SSADevirtual::TraversalMeStmt(MeStmt &meStmt) { break; } case OP_icall: - case OP_icallassigned: { + case OP_icallassigned: + case OP_icallproto: + case OP_icallprotoassigned: { auto *icallMeStmt = static_cast(&meStmt); const MapleVector &opnds = icallMeStmt->GetOpnds(); for (size_t i = 0; i < opnds.size(); ++i) { diff --git a/src/mapleall/maple_me/src/ssa_pre.cpp b/src/mapleall/maple_me/src/ssa_pre.cpp index ceff080daa..a082b80b9f 100644 --- a/src/mapleall/maple_me/src/ssa_pre.cpp +++ b/src/mapleall/maple_me/src/ssa_pre.cpp @@ -1666,6 +1666,7 @@ void SSAPre::BuildWorkListStmt(MeStmt &stmt, uint32 seqStmt, bool isRebuilt, MeE case OP_customcall: case OP_polymorphiccall: case OP_icall: + case OP_icallproto: case OP_callassigned: case OP_virtualcallassigned: case OP_virtualicallassigned: @@ -1675,6 +1676,7 @@ void SSAPre::BuildWorkListStmt(MeStmt &stmt, uint32 seqStmt, bool isRebuilt, MeE case OP_customcallassigned: case OP_polymorphiccallassigned: case OP_icallassigned: + case OP_icallprotoassigned: case OP_asm: { auto *naryMeStmt = static_cast(meStmt); const MapleVector &opnds = naryMeStmt->GetOpnds(); diff --git a/src/mapleall/mpl2mpl/src/constantfold.cpp b/src/mapleall/mpl2mpl/src/constantfold.cpp index 860ed2846a..d89d6ef64d 100644 --- a/src/mapleall/mpl2mpl/src/constantfold.cpp +++ b/src/mapleall/mpl2mpl/src/constantfold.cpp @@ -162,6 +162,8 @@ StmtNode *ConstantFold::Simplify(StmtNode *node) { return SimplifyNary(static_cast(node)); case OP_icall: case OP_icallassigned: + case OP_icallproto: + case OP_icallprotoassigned: return SimplifyIcall(static_cast(node)); case OP_asm: return SimplifyAsm(static_cast(node)); @@ -2618,8 +2620,8 @@ StmtNode *ConstantFold::SimplifyIcall(IcallNode *node) { AddroffuncNode *addrofNode = static_cast(node->GetNopndAt(0)); CallNode *callNode = mirModule->CurFuncCodeMemPool()->New(*mirModule, - node->GetOpCode() == OP_icall ? OP_call : OP_callassigned); - if (node->GetOpCode() == OP_icallassigned) { + (node->GetOpCode() == OP_icall || node->GetOpCode() == OP_icallproto) ? OP_call : OP_callassigned); + if (node->GetOpCode() == OP_icallassigned || node->GetOpCode() == OP_icallprotoassigned) { callNode->SetReturnVec(node->GetReturnVec()); } callNode->SetPUIdx(addrofNode->GetPUIdx()); -- Gitee From 2a03ce21a2d56984aaaf07be48147e25766396b5 Mon Sep 17 00:00:00 2001 From: William Chen Date: Thu, 9 Jun 2022 15:13:55 -0700 Subject: [PATCH 002/179] Enhance ebo for extension to and 0xff 0xffff optimization --- .../maple_be/include/cg/aarch64/aarch64_ebo.h | 1 + .../maple_be/src/cg/aarch64/aarch64_ebo.cpp | 62 +++++++++++++------ 2 files changed, 43 insertions(+), 20 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h index 18e6413fb6..7ee996514f 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h @@ -84,6 +84,7 @@ class AArch64Ebo : public Ebo { uint32 opndSize); AArch64CC_t GetReverseCond(const CondOperand &cond) const; bool CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp); + bool CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp, int64 immVal); }; } /* namespace maplebe */ diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp index 433aeeee3a..97012af84d 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp @@ -1075,6 +1075,38 @@ bool AArch64Ebo::CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi return false; } +bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp, int64 immVal) { + if (opndInfo.insn == nullptr) { + return false; + } + if (!cgFunc->GetMirModule().IsCModule()) { + return false; + } + Insn *prevInsn = opndInfo.insn; + InsnInfo *insnInfo = opndInfo.insnInfo; + if (insnInfo == nullptr) { + return false; + } + CHECK_NULL_FATAL(insnInfo); + MOperator opc1 = prevInsn->GetMachineOpcode(); + if (!isFp && + (((immVal == 0xff) && + (opc1 >= MOP_xsxtb32) && (opc1 <= MOP_xuxtw64)) || + ((immVal == 0xffff) && + (opc1 == MOP_xsxth32 || opc1 == MOP_xsxth64 || opc1 == MOP_xsxtw64 || + opc1 == MOP_xsxth32 || opc1 == MOP_xsxtw64)))) { + /* don't use register if it was redefined. */ + OpndInfo *opndInfo1 = insnInfo->origOpnd[kInsnSecondOpnd]; + if ((opndInfo1 != nullptr) && opndInfo1->redefined) { + return false; + } + Operand &opnd1 = prevInsn->GetOperand(kInsnSecondOpnd); + insn.SetOperand(kInsnSecondOpnd, opnd1); + return true; + } + return false; +} + /* Do some special pattern */ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origInfos) { MOperator opCode = insn.GetMachineOpcode(); @@ -1121,10 +1153,12 @@ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origI * ===> ldrb x1, [] ===> ldrb x1, [] ===> ldrsb x1, [] ===> no change * mov x1, x1 mov x1, x1 mov x1, x1 */ - case MOP_wandrri12: { + case MOP_wandrri12: + case MOP_xandrri13: { + bool is64Bits = (opCode == MOP_xandrri13); bool doAndOpt = false; if (static_cast(insn.GetOperand(kInsnThirdOpnd)).GetValue() == 0xff) { - doAndOpt = CombineExtensionAndLoad(&insn, origInfos, AND, false); + doAndOpt = CombineExtensionAndLoad(&insn, origInfos, AND, is64Bits); } if (doAndOpt) { return doAndOpt; @@ -1139,29 +1173,17 @@ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origI (static_cast(immValue) & (static_cast(immValue) + 1)) == 0) { /* immValue is (1 << n - 1) */ OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); - return CombineLsrAnd(insn, *opndInfo, false, false); - } - break; - } - case MOP_xandrri13: { - bool doAndOpt = false; - if (static_cast(insn.GetOperand(kInsnThirdOpnd)).GetValue() == 0xff) { - doAndOpt = CombineExtensionAndLoad(&insn, origInfos, AND, true); - } - if (doAndOpt) { - return doAndOpt; + return CombineLsrAnd(insn, *opndInfo, is64Bits, false); } /* - * lsr d0, d1, #6 - * and d0, d0, #1 - * ===> ubfx d0, d1, #6, #1 + * extension dest, src0 + * and dest, dest, 0xff or 0xffff + * ===> if extension is >= imm then can eliminate extension */ - int64 immValue = static_cast(insn.GetOperand(kInsnThirdOpnd)).GetValue(); - if (!beforeRegAlloc && immValue != 0 && + if (beforeRegAlloc && immValue != 0 && (static_cast(immValue) & (static_cast(immValue) + 1)) == 0) { - /* immValue is (1 << n - 1) */ OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); - return CombineLsrAnd(insn, *opndInfo, true, false); + return CombineExtAnd(insn, *opndInfo, is64Bits, false, immValue); } break; } -- Gitee From 20b56d62e3b9ad7350f7869c03064e94c23551d0 Mon Sep 17 00:00:00 2001 From: William Chen Date: Thu, 9 Jun 2022 16:33:38 -0700 Subject: [PATCH 003/179] Enhance ebo for back to back and optimization --- .../maple_be/src/cg/aarch64/aarch64_ebo.cpp | 44 ++++++++++++------- 1 file changed, 29 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp index 97012af84d..ccd8c28e00 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp @@ -1075,11 +1075,17 @@ bool AArch64Ebo::CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi return false; } +/* + * extension dest, src0 + * and dest, dest, 0xff or 0xffff + * ===> if extension is >= imm then can eliminate extension + * + * and dst1, src0, imm1 + * and dst2, dst1, imm2 where imm2 is 0xff or 0xffff + * ===> and dst2, src0, imm1 if imm1 <= imm2 + */ bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp, int64 immVal) { - if (opndInfo.insn == nullptr) { - return false; - } - if (!cgFunc->GetMirModule().IsCModule()) { + if (isFp || opndInfo.insn == nullptr || !cgFunc->GetMirModule().IsCModule()) { return false; } Insn *prevInsn = opndInfo.insn; @@ -1089,12 +1095,11 @@ bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi } CHECK_NULL_FATAL(insnInfo); MOperator opc1 = prevInsn->GetMachineOpcode(); - if (!isFp && - (((immVal == 0xff) && - (opc1 >= MOP_xsxtb32) && (opc1 <= MOP_xuxtw64)) || - ((immVal == 0xffff) && - (opc1 == MOP_xsxth32 || opc1 == MOP_xsxth64 || opc1 == MOP_xsxtw64 || - opc1 == MOP_xsxth32 || opc1 == MOP_xsxtw64)))) { + if (((immVal == 0xff) && + (opc1 >= MOP_xsxtb32) && (opc1 <= MOP_xuxtw64)) || + ((immVal == 0xffff) && + (opc1 == MOP_xsxth32 || opc1 == MOP_xsxth64 || opc1 == MOP_xsxtw64 || + opc1 == MOP_xsxth32 || opc1 == MOP_xsxtw64))) { /* don't use register if it was redefined. */ OpndInfo *opndInfo1 = insnInfo->origOpnd[kInsnSecondOpnd]; if ((opndInfo1 != nullptr) && opndInfo1->redefined) { @@ -1104,6 +1109,20 @@ bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi insn.SetOperand(kInsnSecondOpnd, opnd1); return true; } + if ((immVal == 0xff || immVal == 0xffff) && (opc1 == MOP_wandrri12 || opc1 == MOP_xandrri13)) { + OpndInfo *opndInfo1 = insnInfo->origOpnd[kInsnSecondOpnd]; + if ((opndInfo1 != nullptr) && opndInfo1->redefined) { + return false; + } + int64 prevImmVal = static_cast(prevInsn->GetOperand(kInsnThirdOpnd)).GetValue(); + if (prevImmVal > immVal) { + return false; + } + Operand &opnd1 = prevInsn->GetOperand(kInsnSecondOpnd); + insn.SetOperand(kInsnSecondOpnd, opnd1); + Operand &opnd2 = prevInsn->GetOperand(kInsnThirdOpnd); + insn.SetOperand(kInsnThirdOpnd, opnd2); + } return false; } @@ -1175,11 +1194,6 @@ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origI OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); return CombineLsrAnd(insn, *opndInfo, is64Bits, false); } - /* - * extension dest, src0 - * and dest, dest, 0xff or 0xffff - * ===> if extension is >= imm then can eliminate extension - */ if (beforeRegAlloc && immValue != 0 && (static_cast(immValue) & (static_cast(immValue) + 1)) == 0) { OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); -- Gitee From 11aeac4d9a6f2f78b458859250d2f819f5897d7d Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Thu, 9 Jun 2022 23:47:57 -0700 Subject: [PATCH 004/179] remove adjacent occurrence of sext/zext of the same width --- src/mapleall/mpl2mpl/src/constantfold.cpp | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/src/mapleall/mpl2mpl/src/constantfold.cpp b/src/mapleall/mpl2mpl/src/constantfold.cpp index d89d6ef64d..1b296c1de7 100644 --- a/src/mapleall/mpl2mpl/src/constantfold.cpp +++ b/src/mapleall/mpl2mpl/src/constantfold.cpp @@ -1678,13 +1678,23 @@ std::pair ConstantFold::FoldExtractbits(ExtractbitsNode *node) ConstvalNode *cst = safe_cast(p.first); if (cst != nullptr && (opcode == OP_sext || opcode == OP_zext)) { result = FoldSignExtend(opcode, node->GetPrimType(), size, *cst); + return std::make_pair(result, 0); + } + BaseNode *e = PairToExpr(node->Opnd(0)->GetPrimType(), p); + if (e != node->Opnd(0)) { + result = mirModule->CurFuncCodeMemPool()->New(opcode, PrimType(node->GetPrimType()), + offset, size, e); } else { - BaseNode *e = PairToExpr(node->Opnd(0)->GetPrimType(), p); - if (e != node->Opnd(0)) { - result = mirModule->CurFuncCodeMemPool()->New(opcode, PrimType(node->GetPrimType()), - offset, size, e); - } else { - result = node; + result = node; + } + // check for consecutive and redundant extraction of same bits + BaseNode *opnd = result->Opnd(0); + Opcode opndOp = opnd->GetOpCode(); + if (opndOp == OP_extractbits || opndOp == OP_sext || opndOp == OP_zext) { + uint8 opndOffset = static_cast(opnd)->GetBitsOffset(); + uint8 opndSize = static_cast(opnd)->GetBitsSize(); + if (offset == opndOffset && size == opndSize) { + result->SetOpnd(opnd->Opnd(0), 0); // delete the redundant extraction } } return std::make_pair(result, 0); -- Gitee From d17478fea1b5846da8dfd974d3937e8bd4afb1ff Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:15:50 -0700 Subject: [PATCH 005/179] Turn off rematerialization for lmbc --- .../src/cg/aarch64/aarch64_color_ra.cpp | 20 +++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp index 1ed5f1480a..b79422873f 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp @@ -476,14 +476,18 @@ void GraphColorRegAllocator::CalculatePriority(LiveRange &lr) const { auto *a64CGFunc = static_cast(cgFunc); CG *cg = a64CGFunc->GetCG(); - if (cg->GetRematLevel() >= rematConst && lr.IsRematerializable(*a64CGFunc, rematConst)) { - lr.SetRematLevel(rematConst); - } else if (cg->GetRematLevel() >= rematAddr && lr.IsRematerializable(*a64CGFunc, rematAddr)) { - lr.SetRematLevel(rematAddr); - } else if (cg->GetRematLevel() >= rematDreadLocal && lr.IsRematerializable(*a64CGFunc, rematDreadLocal)) { - lr.SetRematLevel(rematDreadLocal); - } else if (cg->GetRematLevel() >= rematDreadGlobal && lr.IsRematerializable(*a64CGFunc, rematDreadGlobal)) { - lr.SetRematLevel(rematDreadGlobal); + if (cgFunc->GetCG()->IsLmbc()) { + lr.SetRematLevel(rematOff); + } else { + if (cg->GetRematLevel() >= rematConst && lr.IsRematerializable(*a64CGFunc, rematConst)) { + lr.SetRematLevel(rematConst); + } else if (cg->GetRematLevel() >= rematAddr && lr.IsRematerializable(*a64CGFunc, rematAddr)) { + lr.SetRematLevel(rematAddr); + } else if (cg->GetRematLevel() >= rematDreadLocal && lr.IsRematerializable(*a64CGFunc, rematDreadLocal)) { + lr.SetRematLevel(rematDreadLocal); + } else if (cg->GetRematLevel() >= rematDreadGlobal && lr.IsRematerializable(*a64CGFunc, rematDreadGlobal)) { + lr.SetRematLevel(rematDreadGlobal); + } } auto calculatePriorityFunc = [&lr, &bbNum, &numDefs, &numUses, &pri, this] (uint32 bbID) { -- Gitee From d2c031547e225d32e3a933220c8b64585a2ced98 Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:16:12 -0700 Subject: [PATCH 006/179] Turn on globalopt for lmbc, but leave SSA opt off --- .../include/cg/aarch64/aarch64_phases.def | 12 ++++-------- src/mapleall/maple_be/include/cg/reaching.h | 1 + .../maple_be/src/cg/aarch64/aarch64_global.cpp | 4 +++- .../src/cg/aarch64/aarch64_reaching.cpp | 18 ++++++++++++++++++ src/mapleall/maple_be/src/cg/reaching.cpp | 10 +++++----- 5 files changed, 31 insertions(+), 14 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index ff08e81852..5595b17c0c 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -36,10 +36,8 @@ ADDTARGETPHASE("ico", CGOptions::DoICO()) ADDTARGETPHASE("cfgo", !GetMIRModule()->IsCModule() && CGOptions::DoCFGO()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); - ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); - } + ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); + ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); ADDTARGETPHASE("clearrdinfo", (CGOptions::DoStoreLoadOpt()) || CGOptions::DoGlobalOpt()); ADDTARGETPHASE("prepeephole1", CGOptions::DoPrePeephole()); @@ -49,10 +47,8 @@ ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); - } + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/include/cg/reaching.h b/src/mapleall/maple_be/include/cg/reaching.h index 76d9fd9291..8a0a6cdf1b 100644 --- a/src/mapleall/maple_be/include/cg/reaching.h +++ b/src/mapleall/maple_be/include/cg/reaching.h @@ -146,6 +146,7 @@ class ReachingDefinition : public AnalysisResult { std::vector memIn; std::vector memOut; const uint32 kMaxBBNum; + uint32 stackSize = 0; private: void Initialize(); void InitDataSize(); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index a719bd6bf1..cd5bfeeb2c 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,7 +412,9 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - CHECK_FATAL(false, "check case in ssa"); + if (cgFunc.GetCG()->IsLmbc() == false) { + CHECK_FATAL(false, "check case in ssa"); + } } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp index 5ca154b1aa..f2540a2286 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp @@ -463,6 +463,9 @@ std::vector AArch64ReachingDefinition::FindMemDefBetweenInsn( ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffset < 0) { + memOffset = stackSize - memOffset; + } if ((offset == memOffset) || (insn->IsStorePair() && offset == memOffset + GetEachMemSizeOfPair(insn->GetMachineOpcode()))) { defInsnVec.emplace_back(insn); @@ -515,6 +518,9 @@ void AArch64ReachingDefinition::FindMemDefInBB(uint32 offset, BB &bb, InsnSet &d ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffset < 0) { + memOffset = stackSize - memOffset; + } if (offset == memOffset) { (void)defInsnSet.insert(insn); break; @@ -1000,6 +1006,9 @@ bool AArch64ReachingDefinition::FindMemUseBetweenInsn(uint32 offset, Insn *start ASSERT(memOpnd.GetIndexRegister() == nullptr, "offset must not be Register for frame MemOperand"); ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetValue(); + if (memOffset < 0) { + memOffset = stackSize - memOffset; + } if (insn->IsStore() || insn->IsPseudoInstruction()) { if (memOffset == offset) { @@ -1049,6 +1058,9 @@ InsnSet AArch64ReachingDefinition::FindDefForMemOpnd(Insn &insn, uint32 indexOrO } ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffSet < 0) { + memOffSet = stackSize - memOffSet; + } } else { memOffSet = indexOrOffset; } @@ -1100,6 +1112,9 @@ InsnSet AArch64ReachingDefinition::FindUseForMemOpnd(Insn &insn, uint8 index, bo ASSERT(memOpnd.GetIndexRegister() == nullptr, "IndexRegister no nullptr"); ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffSet < 0) { + memOffSet = stackSize - memOffSet; + } if (secondMem) { ASSERT(insn.IsStorePair(), "second MemOperand can only be defined in stp insn"); memOffSet += GetEachMemSizeOfPair(insn.GetMachineOpcode()); @@ -1213,6 +1228,9 @@ void AArch64ReachingDefinition::InitInfoForMemOperand(Insn &insn, Operand &opnd, CHECK_FATAL(index == nullptr, "Existing [x29 + index] Memory Address"); ASSERT(memOpnd.GetOffsetImmediate(), "offset must be a immediate value"); int64 offsetVal = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (offsetVal < 0) { + offsetVal = stackSize - offsetVal; + } if ((offsetVal % kMemZoomSize) != 0) { SetAnalysisMode(kRDRegAnalysis); } diff --git a/src/mapleall/maple_be/src/cg/reaching.cpp b/src/mapleall/maple_be/src/cg/reaching.cpp index 72c6fa87e3..b7d95caf59 100644 --- a/src/mapleall/maple_be/src/cg/reaching.cpp +++ b/src/mapleall/maple_be/src/cg/reaching.cpp @@ -546,11 +546,10 @@ void ReachingDefinition::InitRegAndMemInfo(const BB &bb) { } if (mode & kRDMemAnalysis) { - const int32 kStackSize = GetStackSize(); - memGen[bb.GetId()] = new DataInfo((kStackSize / kMemZoomSize), rdAlloc); - memUse[bb.GetId()] = new DataInfo((kStackSize / kMemZoomSize), rdAlloc); - memIn[bb.GetId()] = new DataInfo((kStackSize / kMemZoomSize), rdAlloc); - memOut[bb.GetId()] = new DataInfo((kStackSize / kMemZoomSize), rdAlloc); + memGen[bb.GetId()] = new DataInfo((stackSize / kMemZoomSize), rdAlloc); + memUse[bb.GetId()] = new DataInfo((stackSize / kMemZoomSize), rdAlloc); + memIn[bb.GetId()] = new DataInfo((stackSize / kMemZoomSize), rdAlloc); + memOut[bb.GetId()] = new DataInfo((stackSize / kMemZoomSize), rdAlloc); } } @@ -778,6 +777,7 @@ void ReachingDefinition::AnalysisStart() { if (!cgFunc->GetFirstBB()) { return; } + stackSize = GetStackSize(); Initialize(); /* Build in/out for function body first. (Except cleanup bb) */ BuildInOutForFuncBody(); -- Gitee From 167e564126d965845ba8bce5f91ea4c7e6e4ad43 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Fri, 10 Jun 2022 17:56:05 -0700 Subject: [PATCH 007/179] delete obsolete code in SelectAggIassign() where small struct returned in regs was represented in an iassign --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 130 ------------------ 1 file changed, 130 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index f2b54fa274..ee0b7293b2 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -2282,15 +2282,6 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) { uint32 lhsOffset = 0; MIRType *stmtType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(stmt.GetTyIdx()); MIRPtrType *lhsPointerType = static_cast(stmtType); - bool loadToRegs4StructReturn = false; - if (mirModule.CurFunction()->StructReturnedInRegs()) { - MIRSymbol *retSt = mirModule.CurFunction()->GetFormal(0); - if (stmt.Opnd(0)->GetOpCode() == OP_dread) { - DreadNode *dread = static_cast(stmt.Opnd(0)); - MIRSymbol *addrSym = mirModule.CurFunction()->GetLocalOrGlobalSymbol(dread->GetStIdx()); - loadToRegs4StructReturn = (retSt == addrSym); - } - } MIRType *lhsType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(lhsPointerType->GetPointedTyIdx()); if (stmt.GetFieldID() != 0) { MIRStructType *structType = static_cast(lhsType); @@ -2334,91 +2325,6 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) { rhsType = structType->GetFieldType(rhsDread->GetFieldID()); rhsOffset = static_cast(GetBecommon().GetFieldOffset(*structType, rhsDread->GetFieldID()).first); } - if (loadToRegs4StructReturn) { - /* generate move to regs for agg return */ - CHECK_FATAL(lhsSize <= k16ByteSize, "SelectAggIassign: illegal struct size"); - AArch64CallConvImpl parmlocator(GetBecommon()); - CCLocInfo pLoc; - parmlocator.LocateNextParm(*lhsType, pLoc, true, GetBecommon().GetMIRModule().CurFunction()); - /* aggregates are 8 byte aligned. */ - Operand *rhsmemopnd = nullptr; - RegOperand *result[kFourRegister]; /* up to 2 int or 4 fp */ - uint32 loadSize; - uint32 numRegs; - RegType regType; - PrimType retPty; - bool fpParm = false; - if (pLoc.numFpPureRegs) { - loadSize = pLoc.fpSize; - numRegs = pLoc.numFpPureRegs; - fpParm = true; - regType = kRegTyFloat; - retPty = (pLoc.fpSize == k4ByteSize) ? PTY_f32 : PTY_f64; - } else { - if (CGOptions::IsBigEndian()) { - loadSize = k8ByteSize; - numRegs = (lhsSize <= k8ByteSize) ? kOneRegister : kTwoRegister; - regType = kRegTyInt; - retPty = PTY_u64; - } else { - loadSize = (lhsSize <= k4ByteSize) ? k4ByteSize : k8ByteSize; - numRegs = (lhsSize <= k8ByteSize) ? kOneRegister : kTwoRegister; - regType = kRegTyInt; - retPty = PTY_u32; - } - } - bool parmCopy = IsParamStructCopy(*rhsSymbol); - for (uint32 i = 0; i < numRegs; i++) { - if (parmCopy) { - rhsmemopnd = &LoadStructCopyBase(*rhsSymbol, - (rhsOffset + static_cast(i * (fpParm ? loadSize : k8ByteSize))), - static_cast(loadSize * kBitsPerByte)); - } else { - rhsmemopnd = &GetOrCreateMemOpnd(*rhsSymbol, - (rhsOffset + static_cast(i * (fpParm ? loadSize : k8ByteSize))), - (loadSize * kBitsPerByte)); - } - result[i] = &CreateVirtualRegisterOperand(NewVReg(regType, loadSize)); - MOperator mop1 = PickLdInsn(loadSize * kBitsPerByte, retPty); - Insn &ld = GetCG()->BuildInstruction(mop1, *(result[i]), *rhsmemopnd); - GetCurBB()->AppendInsn(ld); - } - AArch64reg regs[kFourRegister]; - regs[0] = static_cast(pLoc.reg0); - regs[1] = static_cast(pLoc.reg1); - regs[2] = static_cast(pLoc.reg2); - regs[3] = static_cast(pLoc.reg3); - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg; - MOperator mop2; - if (fpParm) { - preg = regs[i]; - mop2 = (loadSize == k4ByteSize) ? MOP_xvmovs : MOP_xvmovd; - } else { - preg = (i == 0 ? R0 : R1); - mop2 = (loadSize == k4ByteSize) ? MOP_wmovrr : MOP_xmovrr; - } - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, (loadSize * kBitsPerByte), regType); - Insn &mov = GetCG()->BuildInstruction(mop2, dest, *(result[i])); - GetCurBB()->AppendInsn(mov); - } - /* Create artificial dependency to extend the live range */ - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg; - MOperator mop3; - if (fpParm) { - preg = regs[i]; - mop3 = MOP_pseudo_ret_float; - } else { - preg = (i == 0 ? R0 : R1); - mop3 = MOP_pseudo_ret_int; - } - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, loadSize * kBitsPerByte, regType); - Insn &pseudo = GetCG()->BuildInstruction(mop3, dest); - GetCurBB()->AppendInsn(pseudo); - } - return; - } rhsAlign = GetBecommon().GetTypeAlign(rhsType->GetTypeIndex()); alignUsed = std::min(lhsAlign, rhsAlign); ASSERT(alignUsed != 0, "expect non-zero"); @@ -2534,42 +2440,6 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) { rhsOffset = static_cast(GetBecommon().GetFieldOffset(*rhsStructType, rhsIread->GetFieldID()).first); isRefField = GetBecommon().IsRefField(*rhsStructType, rhsIread->GetFieldID()); } - if (loadToRegs4StructReturn) { - /* generate move to regs. */ - CHECK_FATAL(lhsSize <= k16ByteSize, "SelectAggIassign: illegal struct size"); - RegOperand *result[kTwoRegister]; /* maximum 16 bytes, 2 registers */ - uint32 loadSize; - if (CGOptions::IsBigEndian()) { - loadSize = k8ByteSize; - } else { - loadSize = (lhsSize <= k4ByteSize) ? k4ByteSize : k8ByteSize; - } - uint32 numRegs = (lhsSize <= k8ByteSize) ? kOneRegister : kTwoRegister; - for (uint32 i = 0; i < numRegs; i++) { - OfstOperand *rhsOffOpnd = &GetOrCreateOfstOpnd(rhsOffset + i * loadSize, loadSize * kBitsPerByte); - Operand &rhsmemopnd = GetOrCreateMemOpnd(MemOperand::kAddrModeBOi, loadSize * kBitsPerByte, - rhsAddrOpnd, nullptr, rhsOffOpnd, nullptr); - result[i] = &CreateVirtualRegisterOperand(NewVReg(kRegTyInt, loadSize)); - MOperator mop1 = PickLdInsn(loadSize * kBitsPerByte, PTY_u32); - Insn &ld = GetCG()->BuildInstruction(mop1, *(result[i]), rhsmemopnd); - ld.MarkAsAccessRefField(isRefField); - GetCurBB()->AppendInsn(ld); - } - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg = (i == 0 ? R0 : R1); - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, loadSize * kBitsPerByte, kRegTyInt); - Insn &mov = GetCG()->BuildInstruction(MOP_xmovrr, dest, *(result[i])); - GetCurBB()->AppendInsn(mov); - } - /* Create artificial dependency to extend the live range */ - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg = (i == 0 ? R0 : R1); - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, loadSize * kBitsPerByte, kRegTyInt); - Insn &pseudo = cg->BuildInstruction(MOP_pseudo_ret_int, dest); - GetCurBB()->AppendInsn(pseudo); - } - return; - } rhsAlign = GetBecommon().GetTypeAlign(rhsType->GetTypeIndex()); alignUsed = std::min(lhsAlign, rhsAlign); ASSERT(alignUsed != 0, "expect non-zero"); -- Gitee From 1c996de52037c0e61c91e5b1bc164ea8a7f06a9b Mon Sep 17 00:00:00 2001 From: William Chen Date: Mon, 13 Jun 2022 14:06:17 -0700 Subject: [PATCH 008/179] Do not optimize for ssa for physical regs. --- .../include/cg/aarch64/aarch64_phases.def | 22 +++++++++---------- .../src/cg/aarch64/aarch64_global.cpp | 4 +--- .../maple_be/src/cg/aarch64/aarch64_prop.cpp | 3 +++ 3 files changed, 14 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 5595b17c0c..531e7f0535 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,18 +17,16 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); - } + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index cd5bfeeb2c..a719bd6bf1 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,9 +412,7 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - if (cgFunc.GetCG()->IsLmbc() == false) { - CHECK_FATAL(false, "check case in ssa"); - } + CHECK_FATAL(false, "check case in ssa"); } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp index c5f56cd1c2..12d2e7117f 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp @@ -1465,6 +1465,9 @@ bool ExtendMovPattern::CheckSrcReg(regno_t srcRegNo, uint32 validNum) { bool ExtendMovPattern::BitNotAffected(const Insn &insn, uint32 validNum) { RegOperand &firstOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); + if (firstOpnd.IsPhysicalRegister()) { + return false; + } RegOperand &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); regno_t desRegNo = firstOpnd.GetRegisterNumber(); regno_t srcRegNo = secondOpnd.GetRegisterNumber(); -- Gitee From 51a3f91cd1b488525a338422886c6329cd4a1754 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 13 Jun 2022 23:36:13 -0700 Subject: [PATCH 009/179] Fold shr followed by band to bitsextract --- src/mapleall/maple_ir/src/bin_func_import.cpp | 3 -- src/mapleall/mpl2mpl/src/constantfold.cpp | 35 +++++++++++++++++++ 2 files changed, 35 insertions(+), 3 deletions(-) diff --git a/src/mapleall/maple_ir/src/bin_func_import.cpp b/src/mapleall/maple_ir/src/bin_func_import.cpp index 8355bb4c58..b23b6895f4 100644 --- a/src/mapleall/maple_ir/src/bin_func_import.cpp +++ b/src/mapleall/maple_ir/src/bin_func_import.cpp @@ -19,9 +19,6 @@ #include "opcode_info.h" #include "mir_pragma.h" #include "mir_builder.h" -#include -#include -#include using namespace std; namespace maple { diff --git a/src/mapleall/mpl2mpl/src/constantfold.cpp b/src/mapleall/mpl2mpl/src/constantfold.cpp index 1b296c1de7..bcd1144b18 100644 --- a/src/mapleall/mpl2mpl/src/constantfold.cpp +++ b/src/mapleall/mpl2mpl/src/constantfold.cpp @@ -47,6 +47,16 @@ namespace maple { // A. Analyze expression type // B. Analysis operator type // C. Replace the expression with the result of the operation + +// true if the constant's bits are made of only one group of contiguous 1's +// starting at bit 0 +static bool ContiguousBitsOf1(uint64 x) { + if (x == 0) { + return false; + } + return (~x & (x+1)) == (x+1); +} + BinaryNode *ConstantFold::NewBinaryNode(BinaryNode *old, Opcode op, PrimType primType, BaseNode *lhs, BaseNode *rhs) const { CHECK_NULL_FATAL(old); @@ -1917,6 +1927,31 @@ std::pair ConstantFold::FoldBinary(BinaryNode *node) { // X & (-1) -> X sum = lp.second; result = l; + } else if (op == OP_band && ContiguousBitsOf1(cst) && lp.second == 0) { + bool fold2extractbits = false; + if (l->GetOpCode() == OP_ashr || l->GetOpCode() == OP_lshr) { + BinaryNode *shrNode = static_cast(l); + if (shrNode->Opnd(1)->GetOpCode() == OP_constval) { + ConstvalNode *shrOpnd = static_cast(shrNode->Opnd(1)); + int64 shrAmt = static_cast(shrOpnd->GetConstVal())->GetValue(); + uint64 ucst = cst; + uint64 bsize = 0; + do { + bsize++; + ucst >>= 1; + } while (ucst != 0); + if (shrAmt + bsize <= GetPrimTypeSize(primType) * 8) { + fold2extractbits = true; + // change to use extractbits + result = mirModule->GetMIRBuilder()->CreateExprExtractbits(OP_extractbits, GetUnsignedPrimType(primType), shrAmt, bsize, shrNode->Opnd(0)); + sum = 0; + } + } + } + if (!fold2extractbits) { + result = NewBinaryNode(node, op, primType, PairToExpr(lPrimTypes, lp), r); + sum = 0; + } } else if (op == OP_bior && cst == -1) { // X | (-1) -> -1 sum = 0; -- Gitee From 372c2c643c67e37f0ff3cb91409fa0ac409da53c Mon Sep 17 00:00:00 2001 From: William Chen Date: Tue, 14 Jun 2022 09:21:24 -0700 Subject: [PATCH 010/179] Fix globalopt bug of negative offset with lmbc --- .../maple_be/src/cg/aarch64/aarch64_reaching.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp index f2540a2286..e5776655c7 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp @@ -464,7 +464,7 @@ std::vector AArch64ReachingDefinition::FindMemDefBetweenInsn( ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffset < 0) { - memOffset = stackSize - memOffset; + memOffset = stackSize + memOffset; } if ((offset == memOffset) || (insn->IsStorePair() && offset == memOffset + GetEachMemSizeOfPair(insn->GetMachineOpcode()))) { @@ -519,7 +519,7 @@ void AArch64ReachingDefinition::FindMemDefInBB(uint32 offset, BB &bb, InsnSet &d ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffset < 0) { - memOffset = stackSize - memOffset; + memOffset = stackSize + memOffset; } if (offset == memOffset) { (void)defInsnSet.insert(insn); @@ -1007,7 +1007,7 @@ bool AArch64ReachingDefinition::FindMemUseBetweenInsn(uint32 offset, Insn *start ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetValue(); if (memOffset < 0) { - memOffset = stackSize - memOffset; + memOffset = stackSize + memOffset; } if (insn->IsStore() || insn->IsPseudoInstruction()) { @@ -1059,7 +1059,7 @@ InsnSet AArch64ReachingDefinition::FindDefForMemOpnd(Insn &insn, uint32 indexOrO ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffSet < 0) { - memOffSet = stackSize - memOffSet; + memOffSet = stackSize + memOffSet; } } else { memOffSet = indexOrOffset; @@ -1113,7 +1113,7 @@ InsnSet AArch64ReachingDefinition::FindUseForMemOpnd(Insn &insn, uint8 index, bo ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffSet < 0) { - memOffSet = stackSize - memOffSet; + memOffSet = stackSize + memOffSet; } if (secondMem) { ASSERT(insn.IsStorePair(), "second MemOperand can only be defined in stp insn"); @@ -1229,7 +1229,7 @@ void AArch64ReachingDefinition::InitInfoForMemOperand(Insn &insn, Operand &opnd, ASSERT(memOpnd.GetOffsetImmediate(), "offset must be a immediate value"); int64 offsetVal = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (offsetVal < 0) { - offsetVal = stackSize - offsetVal; + offsetVal = stackSize + offsetVal; } if ((offsetVal % kMemZoomSize) != 0) { SetAnalysisMode(kRDRegAnalysis); -- Gitee From a4138e167acb28adbfc2e37bd3615f09bda36be7 Mon Sep 17 00:00:00 2001 From: William Chen Date: Tue, 14 Jun 2022 15:55:34 -0700 Subject: [PATCH 011/179] Merge return bb for small C functions --- src/mapleall/maple_be/include/cg/cgfunc.h | 1 + src/mapleall/maple_be/src/cg/cgbb.cpp | 1 + src/mapleall/maple_be/src/cg/cgfunc.cpp | 3 ++- 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/include/cg/cgfunc.h b/src/mapleall/maple_be/include/cg/cgfunc.h index f79c4216df..a4aed235e9 100644 --- a/src/mapleall/maple_be/include/cg/cgfunc.h +++ b/src/mapleall/maple_be/include/cg/cgfunc.h @@ -81,6 +81,7 @@ class SpillMemOperandSet { class LiveRange; #endif /* TARGARM32 */ constexpr uint32 kVRegisterNumber = 80; +constexpr uint32 kNumBBOptReturn = 30; class CGFunc { public: enum ShiftDirection : uint8 { diff --git a/src/mapleall/maple_be/src/cg/cgbb.cpp b/src/mapleall/maple_be/src/cg/cgbb.cpp index a8635be709..f0bd3b833f 100644 --- a/src/mapleall/maple_be/src/cg/cgbb.cpp +++ b/src/mapleall/maple_be/src/cg/cgbb.cpp @@ -525,6 +525,7 @@ void Bfs::ComputeBlockOrder() { done = true; } else { LogInfo::MapleLogger() << "Error: RA BFS loop " << sortedCnt << " in func " << cgfunc->GetName() << "\n"; + CHECK_FATAL(false, ""); } } sortedCnt = sortedBBs.size(); diff --git a/src/mapleall/maple_be/src/cg/cgfunc.cpp b/src/mapleall/maple_be/src/cg/cgfunc.cpp index 4fb7db62c8..646c693c94 100644 --- a/src/mapleall/maple_be/src/cg/cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/cgfunc.cpp @@ -2032,7 +2032,8 @@ void CGFunc::HandleFunction() { /* select instruction */ GenerateInstruction(); /* merge multi return */ - if (!func.GetModule()->IsCModule() || CGOptions::DoRetMerge() || CGOptions::OptimizeForSize()) { + if (!func.GetModule()->IsCModule() || (func.GetModule()->IsCModule() && (NumBBs() < kNumBBOptReturn)) || + CGOptions::DoRetMerge() || CGOptions::OptimizeForSize()) { MergeReturn(); } if (func.IsJava()) { -- Gitee From 1cc6b73a9a58c69531c70d669a40fd8f1ce6a7f8 Mon Sep 17 00:00:00 2001 From: William Chen Date: Thu, 16 Jun 2022 10:53:55 -0700 Subject: [PATCH 012/179] Reorder back-to-back cond branch and uncond brach to loop head bb --- src/mapleall/maple_be/include/cg/cfgo.h | 24 +++++++ src/mapleall/maple_be/include/cg/loop.h | 1 + .../src/cg/aarch64/aarch64_memlayout.cpp | 4 +- src/mapleall/maple_be/src/cg/cfgo.cpp | 65 ++++++++++++++++++- src/mapleall/maple_be/src/cg/loop.cpp | 4 ++ 5 files changed, 94 insertions(+), 4 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/cfgo.h b/src/mapleall/maple_be/include/cg/cfgo.h index e7d6e07e14..2528f03413 100644 --- a/src/mapleall/maple_be/include/cg/cfgo.h +++ b/src/mapleall/maple_be/include/cg/cfgo.h @@ -18,6 +18,14 @@ #include "optimize_common.h" namespace maplebe { + +enum CfgoPhase : maple::uint8 { + CfgoDefault, + CfgoPreRegAlloc, + CfgoPostRegAlloc, + PostCfgo, +}; + class ChainingPattern : public OptimizationPattern { public: explicit ChainingPattern(CGFunc &func) : OptimizationPattern(func) { @@ -63,6 +71,14 @@ class FlipBRPattern : public OptimizationPattern { ~FlipBRPattern() override = default; bool Optimize(BB &curBB) override; + CfgoPhase GetPhase() const { + return phase; + } + void SetPhase(CfgoPhase val) { + phase = val; + } + CfgoPhase phase = CfgoDefault; + protected: void RelocateThrowBB(BB &curBB); }; @@ -120,6 +136,14 @@ class CFGOptimizer : public Optimizer { ~CFGOptimizer() override = default; void InitOptimizePatterns() override; + + CfgoPhase GetPhase() const { + return phase; + } + void SetPhase(CfgoPhase val) { + phase = val; + } + CfgoPhase phase = CfgoDefault; }; MAPLE_FUNC_PHASE_DECLARE_BEGIN(CgCfgo, maplebe::CGFunc) diff --git a/src/mapleall/maple_be/include/cg/loop.h b/src/mapleall/maple_be/include/cg/loop.h index 8a67c29a29..efe40d621f 100644 --- a/src/mapleall/maple_be/include/cg/loop.h +++ b/src/mapleall/maple_be/include/cg/loop.h @@ -172,6 +172,7 @@ class CGFuncLoops { const MapleVector &loopMembers) const; void CheckLoops() const; void PrintLoops(const CGFuncLoops &loops) const; + bool IsBBLoopMember(const BB *bb) const; const BB *GetHeader() const { return header; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index bf888d5d3b..48054ebe82 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -230,7 +230,7 @@ void AArch64MemLayout::LayoutFormalParams() { if (ploc.reg0 != kRinvalid) { /* register */ symLoc->SetRegisters(static_cast(ploc.reg0), static_cast(ploc.reg1), static_cast(ploc.reg2), static_cast(ploc.reg3)); - if (mirFunction->GetFormalDefVec()[i].formalAttrs.GetAttr(ATTR_localrefvar)) { + if (!cgFunc->GetMirModule().IsCModule() && mirFunction->GetNthParamAttr(i).GetAttr(ATTR_localrefvar)) { symLoc->SetMemSegment(segRefLocals); SetSegmentSize(*symLoc, segRefLocals, ptyIdx); } else if (!sym->IsPreg()) { @@ -272,7 +272,7 @@ void AArch64MemLayout::LayoutFormalParams() { } else { segArgsStkPassed.SetSize(static_cast(RoundUp(segArgsStkPassed.GetSize(), kSizeOfPtr))); } - if (mirFunction->GetFormalDefVec()[i].formalAttrs.GetAttr(ATTR_localrefvar)) { + if (!cgFunc->GetMirModule().IsCModule() && mirFunction->GetNthParamAttr(i).GetAttr(ATTR_localrefvar)) { SetLocalRegLocInfo(sym->GetStIdx(), *symLoc); AArch64SymbolAlloc *symLoc1 = memAllocator->GetMemPool()->New(); symLoc1->SetMemSegment(segRefLocals); diff --git a/src/mapleall/maple_be/src/cg/cfgo.cpp b/src/mapleall/maple_be/src/cg/cfgo.cpp index aa47fa100d..5c21bfdb36 100644 --- a/src/mapleall/maple_be/src/cg/cfgo.cpp +++ b/src/mapleall/maple_be/src/cg/cfgo.cpp @@ -42,7 +42,11 @@ void CFGOptimizer::InitOptimizePatterns() { diffPassPatterns.emplace_back(memPool->New(*cgFunc)); } diffPassPatterns.emplace_back(memPool->New(*cgFunc)); - diffPassPatterns.emplace_back(memPool->New(*cgFunc)); + FlipBRPattern *brOpt = memPool->New(*cgFunc); + if (GetPhase() == CfgoPostRegAlloc) { + brOpt->SetPhase(CfgoPostRegAlloc); + } + diffPassPatterns.emplace_back(brOpt); diffPassPatterns.emplace_back(memPool->New(*cgFunc)); diffPassPatterns.emplace_back(memPool->New(*cgFunc)); diffPassPatterns.emplace_back(memPool->New(*cgFunc)); @@ -547,7 +551,13 @@ void FlipBRPattern::RelocateThrowBB(BB &curBB) { * ftBB * targetBB * - * 2. relocate throw BB in RelocateThrowBB() + * loopHeaderBB: loopHeaderBB: + * ... ... + * cond_br loopExit: cond_br loopHeaderBB + * ftBB: ftBB: + * goto loopHeaderBB: goto loopExit + * + * 3. relocate throw BB in RelocateThrowBB() */ bool FlipBRPattern::Optimize(BB &curBB) { if (curBB.GetKind() == BB::kBBIf && !curBB.IsEmpty()) { @@ -647,6 +657,50 @@ bool FlipBRPattern::Optimize(BB &curBB) { ftBB->RemoveInsn(*brInsn); ftBB->SetKind(BB::kBBFallthru); } + } else if (GetPhase() == CfgoPostRegAlloc && ftBB->GetKind() == BB::kBBGoto && + curBB.GetLoop() != nullptr && curBB.GetLoop() == ftBB->GetLoop() && + ftBB->IsSoloGoto() && + ftBB->GetLoop()->GetHeader() == *(ftBB->GetSuccsBegin()) && + curBB.GetLoop()->IsBBLoopMember((curBB.GetSuccs().front() == ftBB) ? + curBB.GetSuccs().back() : curBB.GetSuccs().front()) == false) { + Insn *curBBBranchInsn = nullptr; + for (curBBBranchInsn = curBB.GetLastInsn(); curBBBranchInsn != nullptr; + curBBBranchInsn = curBBBranchInsn->GetPrev()) { + if (curBBBranchInsn->IsBranch()) { + break; + } + } + ASSERT(curBBBranchInsn != nullptr, "FlipBRPattern: curBB has no branch"); + Insn *brInsn = nullptr; + for (brInsn = ftBB->GetLastInsn(); brInsn != nullptr; brInsn = brInsn->GetPrev()) { + if (brInsn->IsGoto()) { + break; + } + } + ASSERT(brInsn != nullptr, "FlipBRPattern: ftBB has no branch"); + uint32 condTargetIdx = curBBBranchInsn->GetJumpTargetIdx(); + LabelOperand &condTarget = static_cast(curBBBranchInsn->GetOperand(condTargetIdx)); + MOperator mOp = curBBBranchInsn->FlipConditionOp(curBBBranchInsn->GetMachineOpcode(), condTargetIdx); + if (mOp == 0) { + return false; + } + uint32 gotoTargetIdx = brInsn->GetJumpTargetIdx(); + LabelOperand &gotoTarget = static_cast(brInsn->GetOperand(gotoTargetIdx)); + curBBBranchInsn->SetMOP(mOp); + curBBBranchInsn->SetOperand(condTargetIdx, gotoTarget); + brInsn->SetOperand(gotoTargetIdx, condTarget); + auto it = ftBB->GetSuccsBegin(); + BB *loopHeadBB = *it; + + curBB.RemoveSuccs(*brBB); + brBB->RemovePreds(curBB); + ftBB->RemoveSuccs(*loopHeadBB); + loopHeadBB->RemovePreds(*ftBB); + + curBB.PushBackSuccs(*loopHeadBB); + loopHeadBB->PushBackPreds(curBB); + ftBB->PushBackSuccs(*brBB); + brBB->PushBackPreds(*ftBB); } else { RelocateThrowBB(curBB); } @@ -847,6 +901,10 @@ bool DuplicateBBPattern::Optimize(BB &curBB) { /* === new pm === */ bool CgCfgo::PhaseRun(maplebe::CGFunc &f) { CFGOptimizer *cfgOptimizer = GetPhaseAllocator()->New(f, *GetPhaseMemPool()); + if (f.IsAfterRegAlloc()) { + (void)GetAnalysisInfoHook()->ForceRunAnalysisPhase, CGFunc>(&CgLoopAnalysis::id, f); + cfgOptimizer->SetPhase(CfgoPostRegAlloc); + } const std::string &funcClass = f.GetFunction().GetBaseClassName(); const std::string &funcName = f.GetFunction().GetBaseFuncName(); const std::string &name = funcClass + funcName; @@ -854,6 +912,9 @@ bool CgCfgo::PhaseRun(maplebe::CGFunc &f) { DotGenerator::GenerateDot("before-cfgo", f, f.GetMirModule()); } cfgOptimizer->Run(name); + if (f.IsAfterRegAlloc()) { + GetAnalysisInfoHook()->ForceEraseAnalysisPhase(f.GetUniqueID(), &CgLoopAnalysis::id); + } if (CFGO_DUMP_NEWPM) { DotGenerator::GenerateDot("after-cfgo", f, f.GetMirModule()); } diff --git a/src/mapleall/maple_be/src/cg/loop.cpp b/src/mapleall/maple_be/src/cg/loop.cpp index a402ebe4f0..48ec9eb5b7 100644 --- a/src/mapleall/maple_be/src/cg/loop.cpp +++ b/src/mapleall/maple_be/src/cg/loop.cpp @@ -161,6 +161,10 @@ void CGFuncLoops::PrintLoops(const CGFuncLoops &funcLoop) const { } } +bool CGFuncLoops::IsBBLoopMember(const BB *bb) const { + return (*(std::find(loopMembers.begin(), loopMembers.end(), bb)) == bb); +} + // partial loop body found with formLoop is NOT really needed in down stream // It should be simplied later void LoopFinder::formLoop(BB* headBB, BB* backBB) { -- Gitee From 78bf941857556cd9755c5d9aa42d714cf503de23 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Mon, 20 Jun 2022 15:49:32 -0700 Subject: [PATCH 013/179] Updating to "new" lmbc --- .../include/cg/aarch64/aarch64_cgfunc.h | 14 +- src/mapleall/maple_be/include/cg/cgfunc.h | 4 +- .../src/cg/aarch64/aarch64_cgfunc.cpp | 125 ++++++++++++++++-- .../src/cg/aarch64/aarch64_memlayout.cpp | 24 +++- .../src/cg/aarch64/aarch64_proepilog.cpp | 33 +++++ 5 files changed, 176 insertions(+), 24 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index 525a620315..6e6e1dd88b 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -104,6 +104,7 @@ class AArch64CGFunc : public CGFunc { MIRType *LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList); RegOperand &GetOrCreateResOperand(const BaseNode &parent, PrimType primType); + MIRStructType *GetLmbcStructArgType(BaseNode &stmt, int32 argNo); void IntrinsifyGetAndAddInt(ListOperand &srcOpnds, PrimType pty); void IntrinsifyGetAndSetInt(ListOperand &srcOpnds, PrimType pty); @@ -191,7 +192,8 @@ class AArch64CGFunc : public CGFunc { Operand *SelectIread(const BaseNode &parent, IreadNode &expr, int extraOffset = 0, PrimType finalBitFieldDestType = kPtyInvalid) override; Operand *SelectIreadoff(const BaseNode &parent, IreadoffNode &ireadoff) override; - Operand *SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff) override; + Operand *SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff /*, MIRType &ty, + ListOperand &srcOpnds, AArch64CallConvImpl &parmLocator */) override; Operand *SelectIntConst(MIRIntConst &intConst) override; Operand *HandleFmovImm(PrimType stype, int64 val, MIRConst &mirConst, const BaseNode &parent); Operand *SelectFloatConst(MIRFloatConst &floatConst, const BaseNode &parent) override; @@ -866,7 +868,7 @@ class AArch64CGFunc : public CGFunc { void SelectParmListDreadSmallAggregate(const MIRSymbol &sym, MIRType &structType, ListOperand &srcOpnds, int32 offset, AArch64CallConvImpl &parmLocator, FieldID fieldID); - void SelectParmListIreadSmallAggregate(const IreadNode &iread, MIRType &structType, ListOperand &srcOpnds, + void SelectParmListIreadSmallAggregate(BaseNode &iread, MIRType &structType, ListOperand &srcOpnds, int32 offset, AArch64CallConvImpl &parmLocator); void SelectParmListDreadLargeAggregate(const MIRSymbol &sym, MIRType &structType, ListOperand &srcOpnds, @@ -875,12 +877,12 @@ class AArch64CGFunc : public CGFunc { AArch64CallConvImpl &parmLocator, int32 &structCopyOffset, int32 fromOffset); void CreateCallStructMemcpyToParamReg(MIRType &structType, int32 structCopyOffset, AArch64CallConvImpl &parmLocator, ListOperand &srcOpnds); - void SelectParmListForAggregate(BaseNode &argExpr, ListOperand &srcOpnds, AArch64CallConvImpl &parmLocator, - int32 &structCopyOffset); + void SelectParmListForAggregate(BaseNode &parent, BaseNode &argExpr, ListOperand &srcOpnds, + AArch64CallConvImpl &parmLocator, int32 &structCopyOffset, int32 argNo); size_t SelectParmListGetStructReturnSize(StmtNode &naryNode); bool MarkParmListCall(BaseNode &expr); - void SelectParmListPreprocessLargeStruct(BaseNode &argExpr, int32 &structCopyOffset); - void SelectParmListPreprocess(const StmtNode &naryNode, size_t start, std::set &specialArgs); + void SelectParmListPreprocessLargeStruct(BaseNode &parent, BaseNode &argExpr, int32 &structCopyOffset, int32 argNo); + void SelectParmListPreprocess(StmtNode &naryNode, size_t start, std::set &specialArgs); void SelectParmList(StmtNode &naryNode, ListOperand &srcOpnds, bool isCallNative = false); Operand *SelectClearStackCallParam(const AddrofNode &expr, int64 &offsetValue); void SelectClearStackCallParmList(const StmtNode &naryNode, ListOperand &srcOpnds, diff --git a/src/mapleall/maple_be/include/cg/cgfunc.h b/src/mapleall/maple_be/include/cg/cgfunc.h index a4aed235e9..43cc353ec6 100644 --- a/src/mapleall/maple_be/include/cg/cgfunc.h +++ b/src/mapleall/maple_be/include/cg/cgfunc.h @@ -1154,8 +1154,8 @@ class CGFunc { #endif MapleMap vregsToPregsMap; uint32 totalInsns = 0; - int32 structCopySize; - int32 maxParamStackSize; + int32 structCopySize = 0; + int32 maxParamStackSize = 0; static constexpr int kRegIncrStepLen = 80; /* reg number increate step length */ bool hasVLAOrAlloca = false; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index ee0b7293b2..47c814fb79 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -161,6 +161,28 @@ bool IsBlkassignForPush(BlkassignoffNode &bNode) { return spBased; } +MIRStructType *AArch64CGFunc::GetLmbcStructArgType(BaseNode &stmt, int32 argNo) { + MIRType *ty = nullptr; + if (stmt.GetOpCode() == OP_call) { + CallNode &callNode = static_cast(stmt); + MIRFunction *callFunc = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(callNode.GetPUIdx()); + if (callFunc->GetFormalCount() < (argNo + 1)) { + return nullptr; /* formals less than actuals */ + } + ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(callFunc->GetFormalDefVec()[argNo].formalTyIdx); + } else if (stmt.GetOpCode() == OP_icallproto) { + IcallNode &icallproto = static_cast(stmt); + MIRType *type = GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallproto.GetRetTyIdx()); + MIRFuncType *fType = static_cast(type); + if (fType->GetParamTypeList().size() < (argNo + 1)) { + return nullptr; + } + ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(fType->GetNthParamType(argNo)); + } + CHECK_FATAL(ty && ty->IsStructType(), "lmbc agg arg error"); + return static_cast(ty); +} + RegOperand &AArch64CGFunc::GetOrCreateResOperand(const BaseNode &parent, PrimType primType) { RegOperand *resOpnd = nullptr; if (parent.GetOpCode() == OP_regassign) { @@ -3090,14 +3112,18 @@ RegOperand *AArch64CGFunc::LmbcStructReturnLoad(int32 offset) { return result; } -Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff) { +Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff /*, MIRType &ty, + ListOperand &srcOpnds, AArch64CallConvImpl &parmLocator*/) { int32 offset = ireadoff.GetOffset(); PrimType primType = ireadoff.GetPrimType(); uint32 bytelen = GetPrimTypeSize(primType); +#if 1 uint32 bitlen = bytelen * kBitsPerByte; +#endif RegType regty = GetRegTyFromPrimTy(primType); RegOperand *result = nullptr; if (offset >= 0) { +#if 1 LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(offset); if (info->GetPrimType() == PTY_agg) { if (info->IsOnStack()) { @@ -3119,10 +3145,23 @@ Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode result = &GetOrCreatePhysicalRegisterOperand((AArch64reg)(info->GetRegNO()), bitlen, regty); } } +#endif + CHECK_FATAL(0, "Invalid ireadfpoff offset"); } else { if (primType == PTY_agg) { - CHECK_FATAL(parent.GetOpCode() == OP_regassign, "SelectIreadfpoff of agg"); - result = LmbcStructReturnLoad(offset); +#if OLD_LMBC // TBD + if (parent.GetOpCode() == OP_call || parent.GetOpCode() == OP_icallproto) { + /* ireadfpoff is now for loading locals under calls. Large agg arg is handled via + SelectParmListPreprocess, Hence only small agg is handled here */ + SelectParmListIreadSmallAggregate(ireadoff, ty, srcOpnds, 0, parmLocator); + } else { +#endif + /* agg return */ + CHECK_FATAL(parent.GetOpCode() == OP_regassign, "SelectIreadfpoff of agg"); + result = LmbcStructReturnLoad(offset); +#if OLD_LMBC // TBD + } +#endif } else { result = GenLmbcParamLoad(offset, bytelen, regty, primType); } @@ -7355,12 +7394,26 @@ void AArch64CGFunc::SelectParmListDreadSmallAggregate(const MIRSymbol &sym, MIRT } } -void AArch64CGFunc::SelectParmListIreadSmallAggregate(const IreadNode &iread, MIRType &structType, +void AArch64CGFunc::SelectParmListIreadSmallAggregate(BaseNode &iread, MIRType &structType, ListOperand &srcOpnds, int32 offset, AArch64CallConvImpl &parmLocator) { int32 symSize = GetBecommon().GetTypeSize(structType.GetTypeIndex().GetIdx()); - RegOperand *addrOpnd0 = static_cast(HandleExpr(iread, *(iread.Opnd(0)))); - RegOperand *addrOpnd1 = &LoadIntoRegister(*addrOpnd0, iread.Opnd(0)->GetPrimType()); + RegOperand *addrOpnd1; + if (iread.GetOpCode() == OP_iread) { + RegOperand *addrOpnd0 = static_cast(HandleExpr(iread, *(iread.Opnd(0)))); + addrOpnd1 = &LoadIntoRegister(*addrOpnd0, iread.Opnd(0)->GetPrimType()); + } else if (iread.GetOpCode() == OP_ireadfpoff) { + IreadFPoffNode &ireadoff = static_cast(iread); + RegOperand *rfp = &GetOrCreatePhysicalRegisterOperand(RFP, k64BitSize, kRegTyInt); + RegOperand *addrOpnd0 = &CreateRegisterOperandOfType(PTY_a64); + ImmOperand &immOpnd = CreateImmOperand(ireadoff.GetOffset(), k32BitSize, true); + GetCurBB()->AppendInsn(GetCG()->BuildInstruction(MOP_xaddrri12, *addrOpnd0, *rfp, immOpnd)); + addrOpnd1 = &LoadIntoRegister(*addrOpnd0, PTY_i64); + } else if (iread.GetOpCode() == OP_ireadoff) { + IreadoffNode &ireadoff = static_cast(iread); + RegOperand *addrOpnd0 = static_cast(HandleExpr(ireadoff, *(ireadoff.Opnd(0)))); + addrOpnd1 = &LoadIntoRegister(*addrOpnd0, PTY_i64); + } CCLocInfo ploc; parmLocator.LocateNextParm(structType, ploc); if (ploc.reg0 == 0) { @@ -7734,8 +7787,8 @@ void AArch64CGFunc::CreateCallStructMemcpyToParamReg(MIRType &structType, int32 } } -void AArch64CGFunc::SelectParmListForAggregate(BaseNode &argExpr, ListOperand &srcOpnds, - AArch64CallConvImpl &parmLocator, int32 &structCopyOffset) { +void AArch64CGFunc::SelectParmListForAggregate(BaseNode &parent, BaseNode &argExpr, ListOperand &srcOpnds, + AArch64CallConvImpl &parmLocator, int32 &structCopyOffset, int32 argNo) { uint64 symSize; int32 rhsOffset = 0; if (argExpr.GetOpCode() == OP_dread) { @@ -7783,6 +7836,32 @@ void AArch64CGFunc::SelectParmListForAggregate(BaseNode &argExpr, ListOperand &s } else { SelectParmListIreadLargeAggregate(iread, *ty, srcOpnds, parmLocator, structCopyOffset, rhsOffset); } + } else if (argExpr.GetOpCode() == OP_ireadfpoff) { + IreadFPoffNode &iread = static_cast(argExpr); + MIRStructType *ty = GetLmbcStructArgType(parent, argNo); + if (ty == nullptr) { /* param < arg */ + return; + } + symSize = GetBecommon().GetTypeSize(ty->GetTypeIndex().GetIdx()); + if (symSize <= k16ByteSize) { + SelectParmListIreadSmallAggregate(iread, *ty, srcOpnds, rhsOffset, parmLocator); + } else { + CreateCallStructMemcpyToParamReg(*ty, structCopyOffset, parmLocator, srcOpnds); + structCopyOffset += static_cast(RoundUp(symSize, kSizeOfPtr)); + } + } else if (argExpr.GetOpCode() == OP_ireadoff) { + IreadoffNode &iread = static_cast(argExpr); + MIRStructType *ty = GetLmbcStructArgType(parent, argNo); + if (ty == nullptr) { + return; + } + symSize = GetBecommon().GetTypeSize(ty->GetTypeIndex().GetIdx()); + if (symSize <= k16ByteSize) { + SelectParmListIreadSmallAggregate(iread, *ty, srcOpnds, rhsOffset, parmLocator); + } else { + CreateCallStructMemcpyToParamReg(*ty, structCopyOffset, parmLocator, srcOpnds); + structCopyOffset += static_cast(RoundUp(symSize, kSizeOfPtr)); + } } else { CHECK_FATAL(0, "NYI"); } @@ -7825,7 +7904,7 @@ size_t AArch64CGFunc::SelectParmListGetStructReturnSize(StmtNode &naryNode) { return 0; } -void AArch64CGFunc::SelectParmListPreprocessLargeStruct(BaseNode &argExpr, int32 &structCopyOffset) { +void AArch64CGFunc::SelectParmListPreprocessLargeStruct(BaseNode &parent, BaseNode &argExpr, int32 &structCopyOffset, int32 argNo) { uint64 symSize; int32 rhsOffset = 0; if (argExpr.GetOpCode() == OP_dread) { @@ -7872,6 +7951,22 @@ void AArch64CGFunc::SelectParmListPreprocessLargeStruct(BaseNode &argExpr, int32 uint32 numMemOp = static_cast(RoundUp(symSize, kSizeOfPtr) / kSizeOfPtr); structCopyOffset += static_cast(numMemOp * kSizeOfPtr); } + } else if (argExpr.GetOpCode() == OP_ireadfpoff) { + IreadFPoffNode &ireadoff = static_cast(argExpr); + MIRStructType *ty = GetLmbcStructArgType(parent, argNo); + symSize = GetBecommon().GetTypeSize(ty->GetTypeIndex()); + if (symSize > 16 /*kParmMemcpySize*/) { +#if OLD_LMBC // TBD + MemOperand *addrOpnd0 = GenLmbcFpMemOperand(ireadoff.GetOffset(), kSizeOfPtr, RFP); + RegOperand *addrOpnd1 = &LoadIntoRegister(*addrOpnd0, PTY_i64); +#endif + RegOperand *rfp = &GetOrCreatePhysicalRegisterOperand(RFP, k64BitSize, kRegTyInt); + RegOperand *addrOpnd = &CreateRegisterOperandOfType(PTY_a64); + ImmOperand &immOpnd = CreateImmOperand(ireadoff.GetOffset(), k32BitSize, true); + GetCurBB()->AppendInsn(GetCG()->BuildInstruction(MOP_xaddrri12, *addrOpnd, *rfp, immOpnd)); + CreateCallStructParamMemcpy(nullptr, addrOpnd, static_cast(symSize), structCopyOffset, 0); + structCopyOffset += static_cast(RoundUp(symSize, kSizeOfPtr)); + } } } @@ -7903,7 +7998,7 @@ bool AArch64CGFunc::MarkParmListCall(BaseNode &expr) { return false; } -void AArch64CGFunc::SelectParmListPreprocess(const StmtNode &naryNode, size_t start, std::set &specialArgs) { +void AArch64CGFunc::SelectParmListPreprocess(StmtNode &naryNode, size_t start, std::set &specialArgs) { size_t i = start; int32 structCopyOffset = GetMaxParamStackSize() - GetStructCopySize(); for (; i < naryNode.NumOpnds(); ++i) { @@ -7916,7 +8011,7 @@ void AArch64CGFunc::SelectParmListPreprocess(const StmtNode &naryNode, size_t st if (primType != PTY_agg) { continue; } - SelectParmListPreprocessLargeStruct(*argExpr, structCopyOffset); + SelectParmListPreprocessLargeStruct(naryNode, *argExpr, structCopyOffset, i); } } @@ -8016,7 +8111,7 @@ void AArch64CGFunc::SelectParmList(StmtNode &naryNode, ListOperand &srcOpnds, bo } /* use alloca */ if (primType == PTY_agg) { - SelectParmListForAggregate(*argExpr, srcOpnds, parmLocator, structCopyOffset); + SelectParmListForAggregate(naryNode, *argExpr, srcOpnds, parmLocator, structCopyOffset, i); continue; } ty = GlobalTables::GetTypeTable().GetTypeTable()[static_cast(primType)]; @@ -9434,7 +9529,11 @@ Operand *AArch64CGFunc::GetBaseReg(const AArch64SymbolAlloc &symAlloc) { } if (fsp == nullptr) { - fsp = &GetOrCreatePhysicalRegisterOperand(RFP, kSizeOfPtr * kBitsPerByte, kRegTyInt); + if (GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { + fsp = &GetOrCreatePhysicalRegisterOperand(RSP, kSizeOfPtr * kBitsPerByte, kRegTyInt); + } else { + fsp = &GetOrCreatePhysicalRegisterOperand(RFP, kSizeOfPtr * kBitsPerByte, kRegTyInt); + } } return fsp; } diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index 48054ebe82..16d4884f2b 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -58,7 +58,9 @@ uint32 AArch64MemLayout::ComputeStackSpaceRequirementForCall(StmtNode &stmt, in ty = GlobalTables::GetTypeTable().GetTypeTable()[static_cast(opnd->GetPrimType())]; } else { Opcode opndOpcode = opnd->GetOpCode(); - ASSERT(opndOpcode == OP_dread || opndOpcode == OP_iread, "opndOpcode should be OP_dread or OP_iread"); + if (be.GetMIRModule().GetFlavor() != kFlavorLmbc) { + ASSERT(opndOpcode == OP_dread || opndOpcode == OP_iread, "opndOpcode should be OP_dread or OP_iread"); + } if (opndOpcode == OP_dread) { DreadNode *dread = static_cast(opnd); MIRSymbol *sym = be.GetMIRModule().CurFunction()->GetLocalOrGlobalSymbol(dread->GetStIdx()); @@ -72,8 +74,7 @@ uint32 AArch64MemLayout::ComputeStackSpaceRequirementForCall(StmtNode &stmt, in ty = static_cast(ty)->GetFieldType(dread->GetFieldID()); } } - } else { - /* OP_iread */ + } else if (opndOpcode == OP_iread) { IreadNode *iread = static_cast(opnd); ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(iread->GetTyIdx()); ASSERT(ty->GetKind() == kTypePointer, "expect pointer"); @@ -87,6 +88,11 @@ uint32 AArch64MemLayout::ComputeStackSpaceRequirementForCall(StmtNode &stmt, in ty = static_cast(ty)->GetFieldType(iread->GetFieldID()); } } + } else if ((opndOpcode == OP_ireadfpoff || opndOpcode == OP_ireadoff || opndOpcode == OP_dreadoff) && opnd->GetPrimType() == PTY_agg) { + ty = static_cast(cgFunc)->GetLmbcStructArgType(stmt, i); + } + if (ty == nullptr) { /* type mismatch */ + continue; } } CCLocInfo ploc; @@ -190,6 +196,7 @@ void AArch64MemLayout::LayoutVarargParams() { } void AArch64MemLayout::LayoutFormalParams() { +#if OLD_LMBC // TBD bool isLmbc = (be.GetMIRModule().GetFlavor() == kFlavorLmbc); if (isLmbc && mirFunction->GetFormalCount() == 0) { /* @@ -201,6 +208,7 @@ void AArch64MemLayout::LayoutFormalParams() { segArgsRegPassed.SetSize(mirFunction->GetOutParmSize()); return; } +#endif AArch64CallConvImpl parmLocator(be); CCLocInfo ploc; @@ -255,8 +263,10 @@ void AArch64MemLayout::LayoutFormalParams() { segArgsRegPassed.SetSize(static_cast(RoundUp(segArgsRegPassed.GetSize(), align))); symLoc->SetOffset(segArgsRegPassed.GetSize()); segArgsRegPassed.SetSize(segArgsRegPassed.GetSize() + size); +#if OLD_LMBC // TBD } else if (isLmbc) { segArgsRegPassed.SetSize(segArgsRegPassed.GetSize() + k8ByteSize); +#endif } } else { /* stack */ uint32 size; @@ -371,11 +381,15 @@ void AArch64MemLayout::LayoutReturnRef(std::vector &returnDelays, symLoc->SetOffset(segRefLocals.GetSize()); segRefLocals.SetSize(segRefLocals.GetSize() + be.GetTypeSize(tyIdx)); } +#if OLD_LMBC // TBD if (be.GetMIRModule().GetFlavor() == kFlavorLmbc) { segArgsToStkPass.SetSize(mirFunction->GetOutParmSize() + kDivide2 * k8ByteSize); } else { segArgsToStkPass.SetSize(FindLargestActualArea(structCopySize)); } +#else + segArgsToStkPass.SetSize(FindLargestActualArea(structCopySize)); +#endif maxParmStackSize = static_cast(segArgsToStkPass.GetSize()); if (Globals::GetInstance()->GetOptimLevel() == 0) { AssignSpillLocationsToPseudoRegisters(); @@ -527,14 +541,18 @@ uint64 AArch64MemLayout::StackFrameSize() const { uint64 total = segArgsRegPassed.GetSize() + static_cast(cgFunc)->SizeOfCalleeSaved() + GetSizeOfRefLocals() + locals().GetSize() + GetSizeOfSpillReg(); +#if OLD_LMBC // TBD if (cgFunc->GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif if (GetSizeOfGRSaveArea() > 0) { total += RoundUp(GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); } if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } +#if OLD_LMBC // TBD } +#endif /* * if the function does not have VLA nor alloca, diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 7e6a33f401..d6208e2f4b 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -1115,9 +1115,11 @@ void AArch64GenProEpilog::AppendInstructionAllocateCallFrameDebug(AArch64reg reg ipoint = cgFunc.GetCurBB()->GetLastInsn(); cfiOffset = stackFrameSize; (void)InsertCFIDefCfaOffset(cfiOffset, *ipoint); +#if OLD_LMBC //TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { argsToStkPassSize -= (kDivide2 * k8ByteSize); } +#endif ipoint = &CreateAndAppendInstructionForAllocateCallFrame(argsToStkPassSize, reg0, reg1, rty); CHECK_FATAL(ipoint != nullptr, "ipoint should not be nullptr at this point"); cfiOffset = GetOffsetFromCFA(); @@ -1217,7 +1219,9 @@ void AArch64GenProEpilog::GeneratePushRegs() { Operand &spOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); +#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; +#endif if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; if (isLmbc) { @@ -1255,14 +1259,18 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); } else { +#endif offset = static_cast(memLayout->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass()); +#if OLD_LMBC // TBD } +#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= static_cast(kAarch64StackPtrAlignment); @@ -1323,11 +1331,14 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { } uint32 dataSizeBits = size * kBitsPerByte; uint32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif offset = static_cast(memlayout->GetGRSaveAreaBaseLoc()); /* SP reference */ if (memlayout->GetSizeOfGRSaveArea() % kAarch64StackPtrAlignment) { offset += size; /* End of area should be aligned. Hole between VR and GR area */ } +#if OLD_LMBC // TBD } else { offset = -memlayout->GetSizeOfGRSaveArea(); /* FP reference */ if (memlayout->GetSizeOfGRSaveArea() % kAarch64StackPtrAlignment) { @@ -1335,6 +1346,7 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { } } uint32 grSize = -offset; +#endif uint32 start_regno = k8BitSize - (memlayout->GetSizeOfGRSaveArea() / size); ASSERT(start_regno <= k8BitSize, "Incorrect starting GR regno for GR Save Area"); for (uint32 i = start_regno + static_cast(R0); i < static_cast(R8); i++) { @@ -1345,11 +1357,15 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { } } Operand *stackLoc; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif stackLoc = &aarchCGFunc.CreateStkTopOpnd(offset + tmpOffset, dataSizeBits); +#if OLD_LMBC // TBD } else { stackLoc = aarchCGFunc.GenLmbcFpMemOperand(offset, size); } +#endif RegOperand ® = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(static_cast(i), k64BitSize, kRegTyInt); Insn &inst = @@ -1358,11 +1374,15 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { offset += size; } if (!CGOptions::UseGeneralRegOnly()) { +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif offset = static_cast(memlayout->GetVRSaveAreaBaseLoc()); +#if OLD_LMBC // TBD } else { offset = -(memlayout->GetSizeOfVRSaveArea() + grSize); } +#endif start_regno = k8BitSize - (memlayout->GetSizeOfVRSaveArea() / (size * k2BitSize)); ASSERT(start_regno <= k8BitSize, "Incorrect starting GR regno for VR Save Area"); for (uint32 i = start_regno + static_cast(V0); i < static_cast(V8); i++) { @@ -1373,11 +1393,15 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { } } Operand *stackLoc; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif stackLoc = &aarchCGFunc.CreateStkTopOpnd(offset + tmpOffset, dataSizeBits); +#if OLD_LMBC // TBD } else { stackLoc = aarchCGFunc.GenLmbcFpMemOperand(offset, size); } +#endif RegOperand ® = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(static_cast(i), k64BitSize, kRegTyFloat); Insn &inst = @@ -1479,7 +1503,9 @@ void AArch64GenProEpilog::GenerateProlog(BB &bb) { } if (useFP) { Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); +#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; +#endif int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; @@ -1682,7 +1708,10 @@ void AArch64GenProEpilog::AppendInstructionDeallocateCallFrameDebug(AArch64reg r * ldp/stp's imm should be within -512 and 504; * if ldp's imm > 504, we fall back to the ldp-add version */ +#if OLD_LMBC // TBD bool isLmbc = (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc); +#endif + bool isLmbc = false; if (cgFunc.HasVLAOrAlloca() || argsToStkPassSize == 0 || isLmbc) { int lmbcOffset = 0; if (isLmbc == false) { @@ -1769,14 +1798,18 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); } else { +#endif offset = static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass(); +#if OLD_LMBC // TBD } +#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= static_cast(kAarch64StackPtrAlignment); -- Gitee From 337ff0d8cd5ba1edc2b0514ef2e7d217a87f2035 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Thu, 16 Jun 2022 10:44:59 -0700 Subject: [PATCH 014/179] Set appearsInCode and puidxOrigin fields in newly cloned functions --- src/mapleall/maple_ipa/src/ipa_clone.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mapleall/maple_ipa/src/ipa_clone.cpp b/src/mapleall/maple_ipa/src/ipa_clone.cpp index c8ba82db37..afffeb3aa1 100644 --- a/src/mapleall/maple_ipa/src/ipa_clone.cpp +++ b/src/mapleall/maple_ipa/src/ipa_clone.cpp @@ -109,6 +109,8 @@ MIRFunction *IpaClone::IpaCloneFunction(MIRFunction &originalFunction, const std newFunc->SetSrcPosition(originalFunction.GetSrcPosition()); newFunc->SetFuncAttrs(originalFunction.GetFuncAttrs()); newFunc->SetBaseClassFuncNames(GlobalTables::GetStrTable().GetOrCreateStrIdxFromName(fullName)); + newFunc->GetFuncSymbol()->SetAppearsInCode(true); + newFunc->SetPuidxOrigin(newFunc->GetPuidx()); if (originalFunction.GetBody() != nullptr) { CopyFuncInfo(originalFunction, *newFunc); newFunc->SetBody( @@ -137,6 +139,8 @@ MIRFunction *IpaClone::IpaCloneFunctionWithFreq(MIRFunction &originalFunction, newFunc->SetSrcPosition(originalFunction.GetSrcPosition()); newFunc->SetFuncAttrs(originalFunction.GetFuncAttrs()); newFunc->SetBaseClassFuncNames(GlobalTables::GetStrTable().GetOrCreateStrIdxFromName(fullName)); + newFunc->GetFuncSymbol()->SetAppearsInCode(true); + newFunc->SetPuidxOrigin(newFunc->GetPuidx()); GcovFuncInfo *origProfData = originalFunction.GetFuncProfData(); auto *moduleMp = mirBuilder.GetMirModule().GetMemPool(); GcovFuncInfo *newProfData = moduleMp->New(&mirBuilder.GetMirModule().GetMPAllocator(), -- Gitee From cf79c64fa8cf7b976b59a34a69835c72b88fa3f4 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Fri, 17 Jun 2022 21:32:32 -0700 Subject: [PATCH 015/179] Fixed bug in importing typeAttrs field of MIRStructType Also, handle the export and import of MIRAddrofConst of local symbols properly. --- src/mapleall/maple_ir/include/bin_mpl_export.h | 2 ++ src/mapleall/maple_ir/src/bin_mpl_export.cpp | 2 +- src/mapleall/maple_ir/src/bin_mpl_import.cpp | 8 ++++---- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index f12bec7081..0d3d6d6457 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -180,7 +180,9 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; + public: MIRFunction *curFunc = nullptr; + private: size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; diff --git a/src/mapleall/maple_ir/src/bin_mpl_export.cpp b/src/mapleall/maple_ir/src/bin_mpl_export.cpp index e777db2ba6..7716148794 100644 --- a/src/mapleall/maple_ir/src/bin_mpl_export.cpp +++ b/src/mapleall/maple_ir/src/bin_mpl_export.cpp @@ -45,7 +45,7 @@ void OutputConstAddrof(const MIRConst &constVal, BinaryMplExport &mplExport) { if (addrof.GetSymbolIndex().IsGlobal()) { mplExport.OutputSymbol(mplExport.GetMIRModule().CurFunction()->GetLocalOrGlobalSymbol(addrof.GetSymbolIndex())); } else { - mplExport.WriteNum(addrof.GetSymbolIndex().FullIdx()); + mplExport.OutputLocalSymbol(mplExport.curFunc->GetLocalOrGlobalSymbol(addrof.GetSymbolIndex())); } mplExport.WriteNum(addrof.GetFieldID()); mplExport.WriteNum(addrof.GetOffset()); diff --git a/src/mapleall/maple_ir/src/bin_mpl_import.cpp b/src/mapleall/maple_ir/src/bin_mpl_import.cpp index 1f79751ed6..e3ab6f9689 100644 --- a/src/mapleall/maple_ir/src/bin_mpl_import.cpp +++ b/src/mapleall/maple_ir/src/bin_mpl_import.cpp @@ -122,10 +122,10 @@ MIRConst *BinaryMplImport::ImportConst(MIRFunction *func) { return memPool->New(sym->GetStIdx(), fi, *exprTy, ofst); } case kBinKindConstAddrofLocal: { - uint32 fullidx = static_cast(ReadNum()); + MIRSymbol *sym = ImportLocalSymbol(func); FieldID fi = static_cast(ReadNum()); int32 ofst = static_cast(ReadNum()); - return memPool->New(StIdx(fullidx), fi, *type, ofst); + return memPool->New(sym->GetStIdx(), fi, *type, ofst); } case kBinKindConstAddrofFunc: { PUIdx puIdx = ImportFunction(); @@ -661,9 +661,9 @@ TyIdx BinaryMplImport::ImportType(bool forPointedType) { auto kind = static_cast(ReadNum()); MIRStructType type(kind, strIdx); type.SetNameIsLocal(nameIsLocal); - auto &origType = static_cast(InsertInTypeTables(type)); - typTab.push_back(origType.GetTypeIndex()); type.SetTypeAttrs(ImportTypeAttrs()); + MIRStructType &origType = static_cast(InsertInTypeTables(type)); + typTab.push_back(origType.GetTypeIndex()); if (kind != kTypeStructIncomplete) { if (forPointedType) { typeNeedsComplete = &origType; -- Gitee From 61df8b00003be09b871dc8d54c63bbeeff8c4748 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 20 Jun 2022 16:33:25 -0700 Subject: [PATCH 016/179] Set isFirst in calling LocateNextParm() so it knows to check for use of x8 to pass the first parameter --- src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp index e5776655c7..1c13d2a731 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp @@ -30,7 +30,7 @@ void AArch64ReachingDefinition::InitStartGen() { CCLocInfo pLoc; for (uint32 i = 0; i < cgFunc->GetFunction().GetFormalCount(); ++i) { MIRType *type = cgFunc->GetFunction().GetNthParamType(i); - parmLocator.LocateNextParm(*type, pLoc); + parmLocator.LocateNextParm(*type, pLoc, i == 0, &cgFunc->GetFunction()); if (pLoc.reg0 == 0) { /* If is a large frame, parameter addressing mode is based vreg:Vra. */ continue; -- Gitee From ae836b6a32860d164d4f8d7ce5e804c8ec87387e Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 20 Jun 2022 21:57:07 -0700 Subject: [PATCH 017/179] Turned some optimizations back off under lmbc and re-enabled some old code The OLD_LMBC define-disabled code caused coremark to fail execution. I have to put #define OLD_LMBC on aarch64_memlayout.cpp and aarch64_proepilog.cpp so coremark can work again. --- .../include/cg/aarch64/aarch64_phases.def | 34 +++++++++++-------- .../src/cg/aarch64/aarch64_memlayout.cpp | 2 ++ .../src/cg/aarch64/aarch64_proepilog.cpp | 5 ++- 3 files changed, 26 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 531e7f0535..e5627ecba3 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,16 +17,18 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + } /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); @@ -34,8 +36,10 @@ ADDTARGETPHASE("ico", CGOptions::DoICO()) ADDTARGETPHASE("cfgo", !GetMIRModule()->IsCModule() && CGOptions::DoCFGO()); - ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); - ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); +if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); + ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); +} ADDTARGETPHASE("clearrdinfo", (CGOptions::DoStoreLoadOpt()) || CGOptions::DoGlobalOpt()); ADDTARGETPHASE("prepeephole1", CGOptions::DoPrePeephole()); @@ -45,8 +49,10 @@ ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + } ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index 16d4884f2b..bbb54b47d7 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -17,6 +17,8 @@ #include "becommon.h" #include "mir_nodes.h" +#define OLD_LMBC 1 + namespace maplebe { using namespace maple; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index d6208e2f4b..fe2d16478c 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -16,6 +16,8 @@ #include "cg_option.h" #include "cgfunc.h" +#define OLD_LMBC 1 + namespace maplebe { using namespace maple; @@ -1710,8 +1712,9 @@ void AArch64GenProEpilog::AppendInstructionDeallocateCallFrameDebug(AArch64reg r */ #if OLD_LMBC // TBD bool isLmbc = (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc); -#endif +#else bool isLmbc = false; +#endif if (cgFunc.HasVLAOrAlloca() || argsToStkPassSize == 0 || isLmbc) { int lmbcOffset = 0; if (isLmbc == false) { -- Gitee From 87e47f63d329a3d72d4f8ad13d5a0647547e818d Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Tue, 21 Jun 2022 22:59:19 -0700 Subject: [PATCH 018/179] Fixed a bug in importing a global symbol inside a function which resulted in entering into the local symbol table --- src/mapleall/maple_ir/src/bin_func_import.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mapleall/maple_ir/src/bin_func_import.cpp b/src/mapleall/maple_ir/src/bin_func_import.cpp index b23b6895f4..f433aff5d0 100644 --- a/src/mapleall/maple_ir/src/bin_func_import.cpp +++ b/src/mapleall/maple_ir/src/bin_func_import.cpp @@ -213,7 +213,7 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { sym = ImportLocalSymbol(func); CHECK_FATAL(sym != nullptr, "null ptr check"); } else { - sym = InSymbol(func); + sym = InSymbol(nullptr); CHECK_FATAL(sym != nullptr, "null ptr check"); if (op == OP_addrof) { sym->SetHasPotentialAssignment(); @@ -475,7 +475,7 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { sym = ImportLocalSymbol(func); CHECK_FATAL(sym != nullptr, "null ptr check"); } else { - sym = InSymbol(func); + sym = InSymbol(nullptr); CHECK_FATAL(sym != nullptr, "null ptr check"); sym->SetHasPotentialAssignment(); } -- Gitee From b6c7493fdc6c99531dd5a0e626028ae280ba26d9 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Wed, 22 Jun 2022 22:07:59 -0700 Subject: [PATCH 019/179] Handle addrofoff as operand of OP_asm --- .../maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 12 ++++++++++++ src/mapleall/maple_ir/src/bin_func_import.cpp | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 47c814fb79..33f01bcf43 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1251,6 +1251,18 @@ void AArch64CGFunc::SelectAsm(AsmNode &node) { } break; } + case OP_addrofoff: { + auto &addrofoffNode = static_cast(*node.Opnd(i)); + Operand *inOpnd = SelectAddrofoff(addrofoffNode, node); + listInputOpnd->PushOpnd(static_cast(*inOpnd)); + PrimType pType = addrofoffNode.GetPrimType(); + listInRegPrefix->stringList.push_back( + static_cast(&CreateStringOperand(GetRegPrefixFromPrimType(pType, inOpnd->GetSize(), str)))); + if (isOutputTempNode) { + rPlusOpnd.emplace_back(std::make_pair(inOpnd, pType)); + } + break; + } case OP_constval: { CHECK_FATAL(!isOutputTempNode, "Unexpect"); auto &constNode = static_cast(*node.Opnd(i)); diff --git a/src/mapleall/maple_ir/src/bin_func_import.cpp b/src/mapleall/maple_ir/src/bin_func_import.cpp index f433aff5d0..3fa37cbf24 100644 --- a/src/mapleall/maple_ir/src/bin_func_import.cpp +++ b/src/mapleall/maple_ir/src/bin_func_import.cpp @@ -44,7 +44,7 @@ void BinaryMplImport::ImportFuncIdInfo(MIRFunction *func) { func->SetPuidxOrigin(static_cast(ReadNum())); ImportInfoVector(func->GetInfoVector(), func->InfoIsString()); if (mod.GetFlavor() == kFlavorLmbc) { - func->SetFrameSize(static_cast(ReadNum())); + func->SetFrameSize(static_cast(ReadNum())); } } -- Gitee From 5ec78116473cf3b1c5a03d83a5cf9c871e4e4c37 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Fri, 24 Jun 2022 21:00:36 -0700 Subject: [PATCH 020/179] Handled more types of asm operands --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 24 +++++++++++++++++++ src/mapleall/maple_me/src/prop.cpp | 2 +- src/mapleall/maple_me/src/ssa_tab.cpp | 10 ++++++++ 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 33f01bcf43..a3c9f7355d 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1263,6 +1263,30 @@ void AArch64CGFunc::SelectAsm(AsmNode &node) { } break; } + case OP_ireadoff: { + IreadoffNode *ireadoff = static_cast(node.Opnd(i)); + Operand *inOpnd = SelectIreadoff(node, *ireadoff); + listInputOpnd->PushOpnd(static_cast(*inOpnd)); + PrimType pType = ireadoff->GetPrimType(); + listInRegPrefix->stringList.push_back( + static_cast(&CreateStringOperand(GetRegPrefixFromPrimType(pType, inOpnd->GetSize(), str)))); + if (isOutputTempNode) { + rPlusOpnd.emplace_back(std::make_pair(inOpnd, pType)); + } + break; + } + case OP_add: { + BinaryNode *addNode = static_cast(node.Opnd(i)); + Operand *inOpnd = SelectAdd(*addNode, *HandleExpr(*addNode, *addNode->Opnd(0)), *HandleExpr(*addNode, *addNode->Opnd(1)), node); + listInputOpnd->PushOpnd(static_cast(*inOpnd)); + PrimType pType = addNode->GetPrimType(); + listInRegPrefix->stringList.push_back( + static_cast(&CreateStringOperand(GetRegPrefixFromPrimType(pType, inOpnd->GetSize(), str)))); + if (isOutputTempNode) { + rPlusOpnd.emplace_back(std::make_pair(inOpnd, pType)); + } + break; + } case OP_constval: { CHECK_FATAL(!isOutputTempNode, "Unexpect"); auto &constNode = static_cast(*node.Opnd(i)); diff --git a/src/mapleall/maple_me/src/prop.cpp b/src/mapleall/maple_me/src/prop.cpp index 0ff35e8454..bbe599f1fc 100644 --- a/src/mapleall/maple_me/src/prop.cpp +++ b/src/mapleall/maple_me/src/prop.cpp @@ -596,7 +596,7 @@ MeExpr *Prop::CheckTruncation(MeExpr *lhs, MeExpr *rhs) const { } if (IsPrimitiveInteger(lhsTy->GetPrimType()) && lhsTy->GetPrimType() != PTY_ptr && lhsTy->GetPrimType() != PTY_ref) { - if (GetPrimTypeSize(lhsTy->GetPrimType()) < GetPrimTypeSize(rhs->GetPrimType())) { + if (GetPrimTypeSize(lhsTy->GetPrimType()) < GetPrimTypeSize(GetRegPrimType(rhs->GetPrimType()))) { if (GetPrimTypeSize(lhsTy->GetPrimType()) >= 4) { return irMap.CreateMeExprTypeCvt(lhsTy->GetPrimType(), rhs->GetPrimType(), *rhs); } else { diff --git a/src/mapleall/maple_me/src/ssa_tab.cpp b/src/mapleall/maple_me/src/ssa_tab.cpp index 7da7182a2d..555abb6ff0 100644 --- a/src/mapleall/maple_me/src/ssa_tab.cpp +++ b/src/mapleall/maple_me/src/ssa_tab.cpp @@ -78,6 +78,16 @@ BaseNode *SSATab::CreateSSAExpr(BaseNode *expr) { expr->SetOpnd(newOpnd, i); } } + // special lowering for trunc whose result has size less than 4 bytes + if (expr->GetOpCode() == OP_trunc && GetPrimTypeSize(expr->GetPrimType()) < 4) { + Opcode extOp = IsSignedInteger(expr->GetPrimType()) ? OP_sext : OP_zext; + uint32 extSize = GetPrimTypeBitSize(expr->GetPrimType()); + PrimType newPrimType = GetRegPrimType(expr->GetPrimType()); + expr->SetPrimType(newPrimType); + BaseNode *extNode = mirModule.CurFunction()->GetCodeMemPool()->New(extOp, newPrimType, 0, extSize); + extNode->SetOpnd(expr, 0); + return extNode; + } return arrayLowered ? expr : nullptr; } -- Gitee From 1af4bf210ed658c8feaaaabd41be88ca041be430 Mon Sep 17 00:00:00 2001 From: William Chen Date: Wed, 8 Jun 2022 16:21:12 -0700 Subject: [PATCH 021/179] Changes from mplcglmbc10 --- .../include/cg/aarch64/aarch64_cgfunc.h | 7 +-- .../src/cg/aarch64/aarch64_cgfunc.cpp | 56 +++++++++---------- .../src/cg/aarch64/aarch64_color_ra.cpp | 2 +- .../src/cg/aarch64/aarch64_proepilog.cpp | 20 +++---- src/mapleall/maple_be/src/cg/cgfunc.cpp | 15 +++-- src/mapleall/maple_be/src/cg/emit.cpp | 6 +- .../maple_ir/include/bin_mpl_export.h | 1 + src/mapleall/maple_ir/include/mir_type.h | 10 ---- src/mapleall/maple_ir/src/bin_func_export.cpp | 2 +- src/mapleall/maple_ir/src/bin_func_import.cpp | 24 ++++---- src/mapleall/maple_ir/src/bin_mpl_import.cpp | 4 +- src/mapleall/maple_ir/src/mir_lower.cpp | 8 +-- src/mapleall/maple_me/src/irmap_build.cpp | 3 +- src/mapleall/maple_me/src/irmap_emit.cpp | 3 +- .../maple_me/src/me_phase_manager.cpp | 2 +- 15 files changed, 73 insertions(+), 90 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index 4ecaffcd45..37172e28ab 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -38,7 +38,7 @@ class LmbcArgInfo { MapleVector lmbcCallArgTypes; MapleVector lmbcCallArgOffsets; MapleVector lmbcCallArgNumOfRegs; // # of regs needed to complete struct - uint32 lmbcTotalStkUsed = -1; // remove when explicit addr for large agg is available + uint32 lmbcTotalStkUsed = -1; // TBD: remove when explicit addr for large agg is available }; class AArch64CGFunc : public CGFunc { @@ -129,7 +129,7 @@ class AArch64CGFunc : public CGFunc { uint32 LmbcFindTotalStkUsed(std::vector* paramList); uint32 LmbcTotalRegsUsed(); void LmbcSelectParmList(ListOperand *srcOpnds, bool isArgReturn); - bool LmbcSmallAggForRet(const BlkassignoffNode &bNode, Operand *src); + bool LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src); bool LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src, std::vector **parmList); void SelectAggDassign(DassignNode &stmt) override; void SelectIassign(IassignNode &stmt) override; @@ -492,8 +492,7 @@ class AArch64CGFunc : public CGFunc { void AssignLmbcFormalParams() override; void LmbcGenSaveSpForAlloca() override; MemOperand *GenLmbcFpMemOperand(int32 offset, uint32 byteSize, AArch64reg base = RFP); - RegOperand *GenLmbcParamLoad(int32 offset, uint32 byteSize, RegType regType, - PrimType primType, AArch64reg baseRegno = RFP); + RegOperand *GenLmbcParamLoad(int32 offset, uint32 byteSize, RegType regType, PrimType primType, AArch64reg baseRegno = RFP); RegOperand *LmbcStructReturnLoad(int32 offset); Operand *GetBaseReg(const AArch64SymbolAlloc &symAlloc); int32 GetBaseOffset(const SymbolAlloc &symAlloc) override; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 1fc9f04ba0..01a3e8c1a3 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1982,9 +1982,8 @@ void AArch64CGFunc::SelectIassignfpoff(IassignFPoffNode &stmt, Operand &opnd) { MIRType *rType = GetLmbcCallReturnType(); bool isPureFpStruct = false; uint32 numRegs = 0; - if (rType && rType->GetPrimType() == PTY_agg && opnd.IsRegister() && - static_cast(opnd).IsPhysicalRegister()) { - CHECK_FATAL(rType->GetSize() <= k16BitSize, "SelectIassignfpoff invalid agg size"); + if (rType && rType->GetPrimType() == PTY_agg && opnd.IsRegister() && static_cast(opnd).IsPhysicalRegister()) { + CHECK_FATAL(rType->GetSize() <= 16, "SelectIassignfpoff invalid agg size"); uint32 fpSize; numRegs = FloatParamRegRequired(static_cast(rType), fpSize); if (numRegs) { @@ -1995,8 +1994,8 @@ void AArch64CGFunc::SelectIassignfpoff(IassignFPoffNode &stmt, Operand &opnd) { uint32 byteSize = GetPrimTypeSize(primType); uint32 bitlen = byteSize * kBitsPerByte; if (isPureFpStruct) { - for (uint32 i = 0 ; i < numRegs; ++i) { - MemOperand *memOpnd = GenLmbcFpMemOperand(offset + static_cast(i * byteSize), byteSize); + for (int i = 0 ; i < numRegs; ++i) { + MemOperand *memOpnd = GenLmbcFpMemOperand(offset + (i * byteSize), byteSize); RegOperand &srcOpnd = GetOrCreatePhysicalRegisterOperand(AArch64reg(V0 + i), bitlen, kRegTyFloat); MOperator mOp = PickStInsn(bitlen, primType); Insn &store = GetCG()->BuildInstruction(mOp, srcOpnd, *memOpnd); @@ -2040,7 +2039,7 @@ void AArch64CGFunc::SelectIassignspoff(PrimType pTy, int32 offset, Operand &opnd /* Search for CALL/ICALL/ICALLPROTO node, must be called from a blkassignoff node */ MIRType *AArch64CGFunc::LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList) { - for (; stmt != nullptr; stmt = stmt->GetNext()) { + for ( ; stmt != nullptr; stmt = stmt->GetNext()) { if (stmt->GetOpCode() == OP_call || stmt->GetOpCode() == OP_icallproto) { break; } @@ -2156,7 +2155,7 @@ bool AArch64CGFunc::LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src, s MemOperand &mem = CreateMemOpnd(regno, s, size * kBitsPerByte); RegOperand *res = &CreateVirtualRegisterOperand(NewVReg(kRegTyFloat, size)); SelectCopy(*res, pTy, mem, pTy); - SetLmbcArgInfo(res, pTy, 0, static_cast(fpregs)); + SetLmbcArgInfo(res, pTy, 0, fpregs); IncLmbcArgsInRegs(kRegTyFloat); } IncLmbcTotalArgs(); @@ -2204,7 +2203,7 @@ uint32 AArch64CGFunc::LmbcFindTotalStkUsed(std::vector *paramList) { CCLocInfo pLoc; for (TyIdx tyIdx : *paramList) { MIRType *ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(tyIdx); - (void)parmlocator.LocateNextParm(*ty, pLoc); + parmlocator.LocateNextParm(*ty, pLoc); } return 0; } @@ -2220,12 +2219,12 @@ uint32 AArch64CGFunc::LmbcTotalRegsUsed() { uint32 fCnt = 0; for (uint32 i = 0; i < regs.size(); i++) { if (IsPrimitiveInteger(types[i])) { - if ((iCnt + static_cast(regs[i])) <= k8ByteSize) { - iCnt += static_cast(regs[i]); + if ((iCnt + regs[i]) <= k8ByteSize) { + iCnt += regs[i]; }; } else { - if ((fCnt + static_cast(regs[i])) <= k8ByteSize) { - fCnt += static_cast(regs[i]); + if ((fCnt + regs[i]) <= k8ByteSize) { + fCnt += regs[i]; }; } } @@ -2272,7 +2271,7 @@ void AArch64CGFunc::SelectBlkassignoff(BlkassignoffNode &bNode, Operand *src) opndVec.push_back(regResult); /* result */ opndVec.push_back(PrepareMemcpyParamOpnd(offset, *dest)); /* param 0 */ opndVec.push_back(src); /* param 1 */ - opndVec.push_back(PrepareMemcpyParamOpnd(static_cast(bNode.blockSize))); /* param 2 */ + opndVec.push_back(PrepareMemcpyParamOpnd(bNode.blockSize));/* param 2 */ SelectLibCall("memcpy", opndVec, PTY_a64, PTY_a64); } @@ -2675,7 +2674,7 @@ void AArch64CGFunc::SelectReturnSendOfStructInRegs(BaseNode *x) { /* generate move to regs for agg return */ AArch64CallConvImpl parmlocator(GetBecommon()); CCLocInfo pLoc; - (void)parmlocator.LocateNextParm(*mirType, pLoc, true, GetBecommon().GetMIRModule().CurFunction()); + parmlocator.LocateNextParm(*mirType, pLoc, true, GetBecommon().GetMIRModule().CurFunction()); /* aggregates are 8 byte aligned. */ Operand *rhsmemopnd = nullptr; RegOperand *result[kFourRegister]; /* up to 2 int or 4 fp */ @@ -3197,8 +3196,8 @@ RegOperand *AArch64CGFunc::LmbcStructReturnLoad(int32 offset) { if (numFpRegs > 0) { PrimType pType = (fpSize <= k4ByteSize) ? PTY_f32 : PTY_f64; for (int32 i = (numFpRegs - kOneRegister); i > 0; --i) { - result = GenLmbcParamLoad(offset + (i * static_cast(fpSize)), fpSize, kRegTyFloat, pType); - AArch64reg regNo = static_cast(V0 + static_cast(i)); + result = GenLmbcParamLoad(offset + (i * fpSize), fpSize, kRegTyFloat, pType); + AArch64reg regNo = static_cast(V0 + i); RegOperand *reg = &GetOrCreatePhysicalRegisterOperand(regNo, fpSize * kBitsPerByte, kRegTyFloat); SelectCopy(*reg, pType, *result, pType); Insn &pseudo = GetCG()->BuildInstruction(MOP_pseudo_ret_float, *reg); @@ -3210,7 +3209,7 @@ RegOperand *AArch64CGFunc::LmbcStructReturnLoad(int32 offset) { } else if (sz <= k8ByteSize) { result = GenLmbcParamLoad(offset, k8ByteSize, kRegTyInt, PTY_i64); } else if (sz <= k16ByteSize) { - result = GenLmbcParamLoad(offset + k8ByteSizeInt, k8ByteSize, kRegTyInt, PTY_i64); + result = GenLmbcParamLoad(offset + k8ByteSize, k8ByteSize, kRegTyInt, PTY_i64); RegOperand *r1 = &GetOrCreatePhysicalRegisterOperand(R1, k8ByteSize * kBitsPerByte, kRegTyInt); SelectCopy(*r1, PTY_i64, *result, PTY_i64); Insn &pseudo = GetCG()->BuildInstruction(MOP_pseudo_ret_int, *r1); @@ -3233,8 +3232,7 @@ Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode if (info->IsOnStack()) { result = GenLmbcParamLoad(info->GetOnStackOffset(), GetPrimTypeSize(PTY_a64), kRegTyInt, PTY_a64); regno_t baseRegno = result->GetRegisterNumber(); - result = GenLmbcParamLoad(offset - static_cast(info->GetOffset()), - bytelen, regty, primType, (AArch64reg)baseRegno); + result = GenLmbcParamLoad(offset - info->GetOffset(), bytelen, regty, primType, (AArch64reg)baseRegno); } else if (primType == PTY_agg) { CHECK_FATAL(parent.GetOpCode() == OP_regassign, "SelectIreadfpoff of agg"); result = LmbcStructReturnLoad(offset); @@ -6534,10 +6532,10 @@ void AArch64CGFunc::AssignLmbcFormalParams() { param->SetRegNO(0); } else { param->SetRegNO(fpReg); - if (!param->HasRegassign()) { + if (param->HasRegassign() == false) { uint32 bytelen = GetPrimTypeSize(primType); uint32 bitlen = bytelen * kBitsPerByte; - MemOperand *mOpnd = GenLmbcFpMemOperand(static_cast(offset), bytelen); + MemOperand *mOpnd = GenLmbcFpMemOperand(offset, bytelen); RegOperand &src = GetOrCreatePhysicalRegisterOperand(AArch64reg(fpReg), bitlen, kRegTyFloat); MOperator mOp = PickStInsn(bitlen, primType); Insn &store = GetCG()->BuildInstruction(mOp, src, *mOpnd); @@ -6561,10 +6559,10 @@ void AArch64CGFunc::AssignLmbcFormalParams() { } else { param->SetRegNO(intReg); param->SetIsOnStack(); - param->SetOnStackOffset(((intReg - R0 + fpReg) - V0) * k8ByteSize); + param->SetOnStackOffset((intReg - R0 + fpReg - V0) * k8ByteSize); uint32 bytelen = GetPrimTypeSize(PTY_a64); uint32 bitlen = bytelen * kBitsPerByte; - MemOperand *mOpnd = GenLmbcFpMemOperand(static_cast(param->GetOnStackOffset()), bytelen); + MemOperand *mOpnd = GenLmbcFpMemOperand(param->GetOnStackOffset(), bytelen); RegOperand &src = GetOrCreatePhysicalRegisterOperand(AArch64reg(intReg), bitlen, kRegTyInt); MOperator mOp = PickStInsn(bitlen, PTY_a64); Insn &store = GetCG()->BuildInstruction(mOp, src, *mOpnd); @@ -6623,13 +6621,14 @@ void AArch64CGFunc::AssignLmbcFormalParams() { } void AArch64CGFunc::LmbcGenSaveSpForAlloca() { - if (GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc || !HasVLAOrAlloca()) { + if (GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc || HasVLAOrAlloca() == false) { return; } Operand &spOpnd = GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); RegOperand &spSaveOpnd = CreateVirtualRegisterOperand(NewVReg(kRegTyInt, kSizeOfPtr)); Insn &save = GetCG()->BuildInstruction(MOP_xmovrr, spSaveOpnd, spOpnd); GetFirstBB()->AppendInsn(save); + //save.SetFrameDef(true); for (auto *retBB : GetExitBBsVec()) { Insn &restore = GetCG()->BuildInstruction(MOP_xmovrr, spOpnd, spSaveOpnd); retBB->AppendInsn(restore); @@ -7944,8 +7943,7 @@ size_t AArch64CGFunc::SelectParmListGetStructReturnSize(StmtNode &naryNode) { } } else if (naryNode.GetOpCode() == OP_icallproto) { IcallNode &icallProto = static_cast(naryNode); - MIRFuncType *funcTy = static_cast( - GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallProto.GetRetTyIdx())); + MIRFuncType *funcTy = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallProto.GetRetTyIdx())); if (funcTy->FirstArgReturn()) { MIRType *ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(funcTy->GetNthParamType(0)); return GetBecommon().GetTypeSize(static_cast(ty)->GetPointedTyIdx()); @@ -8072,8 +8070,7 @@ void AArch64CGFunc::SelectParmList(StmtNode &naryNode, ListOperand &srcOpnds, bo firstArgReturn = callee->IsFirstArgReturn(); } else if (naryNode.GetOpCode() == OP_icallproto) { IcallNode *icallnode = &static_cast(naryNode); - MIRFuncType *funcType = static_cast( - GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallnode->GetRetTyIdx())); + MIRFuncType *funcType = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallnode->GetRetTyIdx())); firstArgReturn = funcType->FirstArgReturn(); } BB *curBBrecord = GetCurBB(); @@ -8621,8 +8618,7 @@ void AArch64CGFunc::SelectCall(CallNode &callNode) { SetLmbcCallReturnType(nullptr); bool largeStructRet = false; if (fn->IsFirstArgReturn()) { - MIRPtrType *ptrTy = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx( - fn->GetFormalDefVec()[0].formalTyIdx)); + MIRPtrType *ptrTy = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(fn->GetFormalDefVec()[0].formalTyIdx)); MIRType *sTy = GlobalTables::GetTypeTable().GetTypeFromTyIdx(ptrTy->GetPointedTyIdx()); largeStructRet = sTy->GetSize() > k16ByteSize; SetLmbcCallReturnType(sTy); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp index 73c015576e..b77161f548 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp @@ -4979,7 +4979,7 @@ bool GraphColorRegAllocator::AllocateRegisters() { MarkCalleeSaveRegs(); - if (!seenFP) { + if (seenFP == false) { cgFunc->UnsetSeenFP(); } if (GCRA_DUMP) { diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index bae75074e8..455acc86bd 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -1226,7 +1226,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { } else { immOpnd = &aarchCGFunc.CreateImmOperand(argsToStkPassSize, k32BitSize, true); } - if (!isLmbc || cgFunc.SeenFP() || cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (isLmbc == false || cgFunc.SeenFP() || cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { aarchCGFunc.SelectAdd(fpOpnd, spOpnd, *immOpnd, PTY_u64); } cgFunc.GetCurBB()->GetLastInsn()->SetFrameDef(true); @@ -1256,11 +1256,11 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { - offset = static_cast((memLayout->RealStackFrameSize() - - aarchCGFunc.SizeOfCalleeSaved()) - memLayout->GetSizeOfLocals()); + offset = static_cast(memLayout->RealStackFrameSize() - + aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); } else { - offset = (static_cast(memLayout->RealStackFrameSize() - - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - /* for FP/LR */ + offset = static_cast(memLayout->RealStackFrameSize() - + (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass()); } @@ -1685,7 +1685,7 @@ void AArch64GenProEpilog::AppendInstructionDeallocateCallFrameDebug(AArch64reg r bool isLmbc = (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc); if (cgFunc.HasVLAOrAlloca() || argsToStkPassSize == 0 || isLmbc) { int lmbcOffset = 0; - if (!isLmbc) { + if (isLmbc == false) { stackFrameSize -= argsToStkPassSize; } else { lmbcOffset = argsToStkPassSize - (kDivide2 * k8ByteSize); @@ -1770,11 +1770,11 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { - offset = static_cast((memLayout->RealStackFrameSize() - - aarchCGFunc.SizeOfCalleeSaved()) - memLayout->GetSizeOfLocals()); + offset = static_cast(memLayout->RealStackFrameSize() - + aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); } else { - offset = (static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - /* for FP/LR */ + offset = static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - + (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass(); } diff --git a/src/mapleall/maple_be/src/cg/cgfunc.cpp b/src/mapleall/maple_be/src/cg/cgfunc.cpp index 3857b2dd13..56da78af48 100644 --- a/src/mapleall/maple_be/src/cg/cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/cgfunc.cpp @@ -1565,16 +1565,16 @@ void CGFunc::CreateLmbcFormalParamInfo() { PrimType primType; uint32 offset; uint32 typeSize; - MIRFunction &lmbcFunc = GetFunction(); - if (lmbcFunc.GetFormalCount() > 0) { + MIRFunction &func = GetFunction(); + if (func.GetFormalCount() > 0) { /* Whenever lmbc cannot delete call type info, the prototype is available */ uint32 stackOffset = 0; - for (size_t idx = 0; idx < lmbcFunc.GetFormalCount(); ++idx) { - MIRSymbol *sym = lmbcFunc.GetFormal(idx); + for (size_t idx = 0; idx < func.GetFormalCount(); ++idx) { + MIRSymbol *sym = func.GetFormal(idx); MIRType *type; TyIdx tyIdx; if (sym) { - tyIdx = lmbcFunc.GetFormalDefVec()[idx].formalTyIdx; + tyIdx = func.GetFormalDefVec()[idx].formalTyIdx; type = GlobalTables::GetTypeTable().GetTypeFromTyIdx(tyIdx); } else { FormalDef vec = const_cast(GetBecommon().GetMIRModule().CurFunction())->GetFormalDefAt(idx); @@ -1637,7 +1637,7 @@ void CGFunc::CreateLmbcFormalParamInfo() { ); /* When a scalar param address is taken, its regassign is not in the 1st block */ - for (StmtNode *stmt = lmbcFunc.GetBody()->GetFirst(); stmt != nullptr; stmt = stmt->GetNext()) { + for (StmtNode *stmt = func.GetBody()->GetFirst(); stmt != nullptr; stmt = stmt->GetNext()) { if (stmt == nullptr) { break; } @@ -1656,8 +1656,7 @@ void CGFunc::CreateLmbcFormalParamInfo() { if (ireadNode->GetOffset() < 0) { continue; } - LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(static_cast(ireadNode->GetOffset())); - ASSERT_NOT_NULL(info); + LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(ireadNode->GetOffset()); info->SetHasRegassign(); } diff --git a/src/mapleall/maple_be/src/cg/emit.cpp b/src/mapleall/maple_be/src/cg/emit.cpp index fb607bda2c..782198b428 100644 --- a/src/mapleall/maple_be/src/cg/emit.cpp +++ b/src/mapleall/maple_be/src/cg/emit.cpp @@ -2171,9 +2171,9 @@ void Emitter::EmitGlobalVar(const MIRSymbol &globalVar) { void Emitter::EmitGlobalVars(std::vector> &globalVars) { if (GetCG()->IsLmbc() && GetCG()->GetGP() != nullptr) { - (void)Emit(asmInfo->GetLocal()).Emit("\t").Emit(GetCG()->GetGP()->GetName()).Emit("\n"); - (void)Emit(asmInfo->GetComm()).Emit("\t").Emit(GetCG()->GetGP()->GetName()); - (void)Emit(", ").Emit(GetCG()->GetMIRModule()->GetGlobalMemSize()).Emit(", ").Emit("8\n"); + Emit(asmInfo->GetLocal()).Emit("\t").Emit(GetCG()->GetGP()->GetName()).Emit("\n"); + Emit(asmInfo->GetComm()).Emit("\t").Emit(GetCG()->GetGP()->GetName()); + Emit(", ").Emit(GetCG()->GetMIRModule()->GetGlobalMemSize()).Emit(", ").Emit("8\n"); } /* load globalVars profile */ if (globalVars.empty()) { diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index e171763e13..ee8e94c615 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,6 +181,7 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; + MIRFunction *curFunc = nullptr; size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; diff --git a/src/mapleall/maple_ir/include/mir_type.h b/src/mapleall/maple_ir/include/mir_type.h index 0caa8da87a..6c50c72df7 100644 --- a/src/mapleall/maple_ir/include/mir_type.h +++ b/src/mapleall/maple_ir/include/mir_type.h @@ -1189,14 +1189,6 @@ class MIRStructType : public MIRType { isImported = flag; } - bool IsUsed() const { - return isUsed; - } - - void SetIsUsed(bool flag) { - isUsed = flag; - } - bool IsCPlusPlus() const { return isCPlusPlus; } @@ -1368,7 +1360,6 @@ class MIRStructType : public MIRType { vTableMethods.clear(); iTableMethods.clear(); isImported = false; - isUsed = false; hasVolatileField = false; hasVolatileFieldSet = false; } @@ -1471,7 +1462,6 @@ class MIRStructType : public MIRType { // implementation functions, For interfaces, they are abstact functions. // Weak indicates the actual definition is in another module. bool isImported = false; - bool isUsed = false; bool isCPlusPlus = false; // empty struct in C++ has size 1 byte mutable bool hasVolatileField = false; // for caching computed value mutable bool hasVolatileFieldSet = false; // if true, just read hasVolatileField; diff --git a/src/mapleall/maple_ir/src/bin_func_export.cpp b/src/mapleall/maple_ir/src/bin_func_export.cpp index 693e7f82fe..6815c8151d 100644 --- a/src/mapleall/maple_ir/src/bin_func_export.cpp +++ b/src/mapleall/maple_ir/src/bin_func_export.cpp @@ -87,7 +87,7 @@ void BinaryMplExport::OutputLocalSymbol(MIRSymbol *sym) { void BinaryMplExport::OutputPreg(MIRPreg *preg) { if (preg->GetPregNo() < 0) { WriteNum(kBinSpecialReg); - Write(static_cast(-preg->GetPregNo())); + Write(-preg->GetPregNo()); return; } std::unordered_map::iterator it = localPregMark.find(preg); diff --git a/src/mapleall/maple_ir/src/bin_func_import.cpp b/src/mapleall/maple_ir/src/bin_func_import.cpp index 42b76766c2..d0dd163ba4 100644 --- a/src/mapleall/maple_ir/src/bin_func_import.cpp +++ b/src/mapleall/maple_ir/src/bin_func_import.cpp @@ -49,8 +49,8 @@ void BinaryMplImport::ImportFuncIdInfo(MIRFunction *func) { } void BinaryMplImport::ImportBaseNode(Opcode &o, PrimType &typ) { - o = static_cast(Read()); - typ = static_cast(Read()); + o = (Opcode)Read(); + typ = (PrimType)Read(); } MIRSymbol *BinaryMplImport::ImportLocalSymbol(MIRFunction *func) { @@ -60,8 +60,8 @@ MIRSymbol *BinaryMplImport::ImportLocalSymbol(MIRFunction *func) { } if (tag < 0) { CHECK_FATAL(static_cast(-tag) < localSymTab.size(), "index out of bounds"); - return localSymTab.at(static_cast(-tag)); - } + return localSymTab.at(-tag); + } CHECK_FATAL(tag == kBinSymbol, "expecting kBinSymbol in ImportLocalSymbol()"); MIRSymbol *sym = func->GetSymTab()->CreateSymbol(kScopeLocal); localSymTab.push_back(sym); @@ -98,11 +98,11 @@ PregIdx BinaryMplImport::ImportPreg(MIRFunction *func) { } if (tag < 0) { CHECK_FATAL(static_cast(-tag) < localPregTab.size(), "index out of bounds"); - return localPregTab.at(static_cast(-tag)); + return localPregTab.at(-tag); } CHECK_FATAL(tag == kBinPreg, "expecting kBinPreg in ImportPreg()"); - PrimType primType = static_cast(Read()); + PrimType primType = (PrimType)Read(); PregIdx pidx = func->GetPregTab()->CreatePreg(primType); localPregTab.push_back(pidx); return pidx; @@ -115,7 +115,7 @@ LabelIdx BinaryMplImport::ImportLabel(MIRFunction *func) { } if (tag < 0) { CHECK_FATAL(static_cast(-tag) < localLabelTab.size(), "index out of bounds"); - return localLabelTab.at(static_cast(-tag)); + return localLabelTab.at(-tag); } CHECK_FATAL(tag == kBinLabel, "kBinLabel expected in ImportLabel()"); @@ -265,7 +265,7 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { case OP_floor: case OP_trunc: { TypeCvtNode *typecvtNode = mod.CurFuncCodeMemPool()->New(op, typ); - typecvtNode->SetFromType(static_cast(Read())); + typecvtNode->SetFromType((PrimType)Read()); typecvtNode->SetOpnd(ImportExpression(func), 0); return typecvtNode; } @@ -305,8 +305,8 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { } case OP_depositbits: { DepositbitsNode *dbNode = mod.CurFuncCodeMemPool()->New(op, typ); - dbNode->SetBitsOffset(static_cast(ReadNum())); - dbNode->SetBitsSize(static_cast(ReadNum())); + dbNode->SetBitsOffset(ReadNum()); + dbNode->SetBitsSize(ReadNum()); dbNode->SetOpnd(ImportExpression(func), 0); dbNode->SetOpnd(ImportExpression(func), 1); return dbNode; @@ -351,7 +351,7 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { case OP_cmpl: case OP_cmp: { CompareNode *cmpNode = mod.CurFuncCodeMemPool()->New(op, typ); - cmpNode->SetOpndType(static_cast(Read())); + cmpNode->SetOpndType((PrimType)Read()); cmpNode->SetOpnd(ImportExpression(func), 0); cmpNode->SetOpnd(ImportExpression(func), 1); return cmpNode; @@ -525,7 +525,7 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { case OP_iassignspoff: case OP_iassignfpoff: { IassignFPoffNode *s = func->GetCodeMemPool()->New(op); - s->SetPrimType(static_cast(Read())); + s->SetPrimType((PrimType)Read()); s->SetOffset(static_cast(ReadNum())); s->SetOpnd(ImportExpression(func), 0); stmt = s; diff --git a/src/mapleall/maple_ir/src/bin_mpl_import.cpp b/src/mapleall/maple_ir/src/bin_mpl_import.cpp index ddd38f6014..cc7bd4a2c1 100644 --- a/src/mapleall/maple_ir/src/bin_mpl_import.cpp +++ b/src/mapleall/maple_ir/src/bin_mpl_import.cpp @@ -543,7 +543,7 @@ TyIdx BinaryMplImport::ImportType(bool forPointedType) { CHECK_FATAL(static_cast(-tag) < typTab.size(), "index out of bounds"); return typTab.at(static_cast(-tag)); } - PrimType primType = static_cast(0); + PrimType primType = (PrimType)0; GStrIdx strIdx(0); bool nameIsLocal = false; ImportTypeBase(primType, strIdx, nameIsLocal); @@ -719,7 +719,7 @@ TyIdx BinaryMplImport::ImportTypeNonJava() { CHECK_FATAL(static_cast(-tag) < typTab.size(), "index out of bounds"); return typTab[static_cast(-tag)]; } - PrimType primType = static_cast(0); + PrimType primType = (PrimType)0; GStrIdx strIdx(0); bool nameIsLocal = false; ImportTypeBase(primType, strIdx, nameIsLocal); diff --git a/src/mapleall/maple_ir/src/mir_lower.cpp b/src/mapleall/maple_ir/src/mir_lower.cpp index f4324cdb81..53413ee084 100644 --- a/src/mapleall/maple_ir/src/mir_lower.cpp +++ b/src/mapleall/maple_ir/src/mir_lower.cpp @@ -554,7 +554,7 @@ BlockNode *MIRLower::LowerBlock(BlockNode &block) { CHECK_FATAL(funcType != nullptr, "MIRLower::LowerBlock: cannot find prototype for icall"); ic->SetRetTyIdx(funcType->GetTypeIndex()); MIRType *retType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(funcType->GetRetTyIdx()); - if (retType->GetPrimType() == PTY_agg && retType->GetSize() > k16BitSize) { + if (retType->GetPrimType() == PTY_agg && retType->GetSize() > 16) { funcType->funcAttrs.SetAttr(FUNCATTR_firstarg_return); } } @@ -1094,14 +1094,14 @@ MIRFuncType *MIRLower::FuncTypeFromFuncPtrExpr(BaseNode *x) { res = static_cast(mirType)->GetPointedFuncType(); } if (res == nullptr) { - res = FuncTypeFromFuncPtrExpr(x->Opnd(kNodeFirstOpnd)); + res = FuncTypeFromFuncPtrExpr(x->Opnd(0)); } break; } case OP_select: { - res = FuncTypeFromFuncPtrExpr(x->Opnd(kNodeSecondOpnd)); + res = FuncTypeFromFuncPtrExpr(x->Opnd(1)); if (res == nullptr) { - res = FuncTypeFromFuncPtrExpr(x->Opnd(kNodeThirdOpnd)); + res = FuncTypeFromFuncPtrExpr(x->Opnd(2)); } break; } diff --git a/src/mapleall/maple_me/src/irmap_build.cpp b/src/mapleall/maple_me/src/irmap_build.cpp index 9acc290d37..b6d96b6726 100755 --- a/src/mapleall/maple_me/src/irmap_build.cpp +++ b/src/mapleall/maple_me/src/irmap_build.cpp @@ -808,8 +808,7 @@ MeStmt *IRMapBuild::BuildCallMeStmt(StmtNode &stmt, AccessSSANodes &ssaPart) { MeStmt *IRMapBuild::BuildNaryMeStmt(StmtNode &stmt, AccessSSANodes &ssaPart) { Opcode op = stmt.GetOpCode(); - NaryMeStmt *naryMeStmt = (op == OP_icall || op == OP_icallassigned || - op == OP_icallproto || op == OP_icallprotoassigned) + NaryMeStmt *naryMeStmt = (op == OP_icall || op == OP_icallassigned || op == OP_icallproto || op == OP_icallprotoassigned) ? static_cast(irMap->NewInPool(&stmt)) : static_cast(irMap->NewInPool(&stmt)); auto &naryStmtNode = static_cast(stmt); diff --git a/src/mapleall/maple_me/src/irmap_emit.cpp b/src/mapleall/maple_me/src/irmap_emit.cpp index ea13d7b91b..f6d7b046d8 100755 --- a/src/mapleall/maple_me/src/irmap_emit.cpp +++ b/src/mapleall/maple_me/src/irmap_emit.cpp @@ -412,8 +412,7 @@ MIRFunction &CallMeStmt::GetTargetFunction() { } StmtNode &CallMeStmt::EmitStmt(SSATab &ssaTab) { - if (GetOp() != OP_icall && GetOp() != OP_icallassigned && - GetOp() != OP_icallproto && GetOp() != OP_icallprotoassigned) { + if (GetOp() != OP_icall && GetOp() != OP_icallassigned && GetOp() != OP_icallproto && GetOp() != OP_icallprotoassigned) { auto *callNode = ssaTab.GetModule().CurFunction()->GetCodeMempool()->New(ssaTab.GetModule(), Opcode(GetOp())); callNode->SetPUIdx(puIdx); diff --git a/src/mapleall/maple_me/src/me_phase_manager.cpp b/src/mapleall/maple_me/src/me_phase_manager.cpp index eef57b0aeb..a0b5419a8e 100644 --- a/src/mapleall/maple_me/src/me_phase_manager.cpp +++ b/src/mapleall/maple_me/src/me_phase_manager.cpp @@ -160,7 +160,7 @@ bool MeFuncPM::PhaseRun(maple::MIRModule &m) { func->SetFrameSize(localMemLayout.StackFrameSize()); memPoolCtrler.DeleteMemPool(layoutMp); } - globalMemLayout.seg_GPbased.size = maplebe::RoundUp(static_cast(globalMemLayout.seg_GPbased.size), GetPrimTypeSize(PTY_ptr)); + globalMemLayout.seg_GPbased.size = maplebe::RoundUp(globalMemLayout.seg_GPbased.size, GetPrimTypeSize(PTY_ptr)); m.SetGlobalMemSize(globalMemLayout.seg_GPbased.size); // output .lmbc BinaryMplt binMplt(m); -- Gitee From 2d13b383852c35a526dfeb4579cf4e268b5c4b97 Mon Sep 17 00:00:00 2001 From: William Chen Date: Thu, 9 Jun 2022 15:13:55 -0700 Subject: [PATCH 022/179] Enhance ebo for extension to and 0xff 0xffff optimization --- .../maple_be/include/cg/aarch64/aarch64_ebo.h | 1 + .../maple_be/src/cg/aarch64/aarch64_ebo.cpp | 62 +++++++++++++------ 2 files changed, 43 insertions(+), 20 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h index 18e6413fb6..7ee996514f 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h @@ -84,6 +84,7 @@ class AArch64Ebo : public Ebo { uint32 opndSize); AArch64CC_t GetReverseCond(const CondOperand &cond) const; bool CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp); + bool CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp, int64 immVal); }; } /* namespace maplebe */ diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp index 77f6a2e70f..c4b8744397 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp @@ -1058,6 +1058,38 @@ bool AArch64Ebo::CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi return false; } +bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp, int64 immVal) { + if (opndInfo.insn == nullptr) { + return false; + } + if (!cgFunc->GetMirModule().IsCModule()) { + return false; + } + Insn *prevInsn = opndInfo.insn; + InsnInfo *insnInfo = opndInfo.insnInfo; + if (insnInfo == nullptr) { + return false; + } + CHECK_NULL_FATAL(insnInfo); + MOperator opc1 = prevInsn->GetMachineOpcode(); + if (!isFp && + (((immVal == 0xff) && + (opc1 >= MOP_xsxtb32) && (opc1 <= MOP_xuxtw64)) || + ((immVal == 0xffff) && + (opc1 == MOP_xsxth32 || opc1 == MOP_xsxth64 || opc1 == MOP_xsxtw64 || + opc1 == MOP_xsxth32 || opc1 == MOP_xsxtw64)))) { + /* don't use register if it was redefined. */ + OpndInfo *opndInfo1 = insnInfo->origOpnd[kInsnSecondOpnd]; + if ((opndInfo1 != nullptr) && opndInfo1->redefined) { + return false; + } + Operand &opnd1 = prevInsn->GetOperand(kInsnSecondOpnd); + insn.SetOperand(kInsnSecondOpnd, opnd1); + return true; + } + return false; +} + /* Do some special pattern */ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origInfos) { MOperator opCode = insn.GetMachineOpcode(); @@ -1104,10 +1136,12 @@ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origI * ===> ldrb x1, [] ===> ldrb x1, [] ===> ldrsb x1, [] ===> no change * mov x1, x1 mov x1, x1 mov x1, x1 */ - case MOP_wandrri12: { + case MOP_wandrri12: + case MOP_xandrri13: { + bool is64Bits = (opCode == MOP_xandrri13); bool doAndOpt = false; if (static_cast(insn.GetOperand(kInsnThirdOpnd)).GetValue() == 0xff) { - doAndOpt = CombineExtensionAndLoad(&insn, origInfos, AND, false); + doAndOpt = CombineExtensionAndLoad(&insn, origInfos, AND, is64Bits); } if (doAndOpt) { return doAndOpt; @@ -1122,29 +1156,17 @@ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origI (static_cast(immValue) & (static_cast(immValue) + 1)) == 0) { /* immValue is (1 << n - 1) */ OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); - return CombineLsrAnd(insn, *opndInfo, false, false); - } - break; - } - case MOP_xandrri13: { - bool doAndOpt = false; - if (static_cast(insn.GetOperand(kInsnThirdOpnd)).GetValue() == 0xff) { - doAndOpt = CombineExtensionAndLoad(&insn, origInfos, AND, true); - } - if (doAndOpt) { - return doAndOpt; + return CombineLsrAnd(insn, *opndInfo, is64Bits, false); } /* - * lsr d0, d1, #6 - * and d0, d0, #1 - * ===> ubfx d0, d1, #6, #1 + * extension dest, src0 + * and dest, dest, 0xff or 0xffff + * ===> if extension is >= imm then can eliminate extension */ - int64 immValue = static_cast(insn.GetOperand(kInsnThirdOpnd)).GetValue(); - if (!beforeRegAlloc && immValue != 0 && + if (beforeRegAlloc && immValue != 0 && (static_cast(immValue) & (static_cast(immValue) + 1)) == 0) { - /* immValue is (1 << n - 1) */ OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); - return CombineLsrAnd(insn, *opndInfo, true, false); + return CombineExtAnd(insn, *opndInfo, is64Bits, false, immValue); } break; } -- Gitee From ef1b04367830ff7d1dffa6262c41fef426c8910f Mon Sep 17 00:00:00 2001 From: William Chen Date: Thu, 9 Jun 2022 16:33:38 -0700 Subject: [PATCH 023/179] Enhance ebo for back to back and optimization --- .../maple_be/src/cg/aarch64/aarch64_ebo.cpp | 44 ++++++++++++------- 1 file changed, 29 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp index c4b8744397..74c229bbe5 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp @@ -1058,11 +1058,17 @@ bool AArch64Ebo::CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi return false; } +/* + * extension dest, src0 + * and dest, dest, 0xff or 0xffff + * ===> if extension is >= imm then can eliminate extension + * + * and dst1, src0, imm1 + * and dst2, dst1, imm2 where imm2 is 0xff or 0xffff + * ===> and dst2, src0, imm1 if imm1 <= imm2 + */ bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp, int64 immVal) { - if (opndInfo.insn == nullptr) { - return false; - } - if (!cgFunc->GetMirModule().IsCModule()) { + if (isFp || opndInfo.insn == nullptr || !cgFunc->GetMirModule().IsCModule()) { return false; } Insn *prevInsn = opndInfo.insn; @@ -1072,12 +1078,11 @@ bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi } CHECK_NULL_FATAL(insnInfo); MOperator opc1 = prevInsn->GetMachineOpcode(); - if (!isFp && - (((immVal == 0xff) && - (opc1 >= MOP_xsxtb32) && (opc1 <= MOP_xuxtw64)) || - ((immVal == 0xffff) && - (opc1 == MOP_xsxth32 || opc1 == MOP_xsxth64 || opc1 == MOP_xsxtw64 || - opc1 == MOP_xsxth32 || opc1 == MOP_xsxtw64)))) { + if (((immVal == 0xff) && + (opc1 >= MOP_xsxtb32) && (opc1 <= MOP_xuxtw64)) || + ((immVal == 0xffff) && + (opc1 == MOP_xsxth32 || opc1 == MOP_xsxth64 || opc1 == MOP_xsxtw64 || + opc1 == MOP_xsxth32 || opc1 == MOP_xsxtw64))) { /* don't use register if it was redefined. */ OpndInfo *opndInfo1 = insnInfo->origOpnd[kInsnSecondOpnd]; if ((opndInfo1 != nullptr) && opndInfo1->redefined) { @@ -1087,6 +1092,20 @@ bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi insn.SetOperand(kInsnSecondOpnd, opnd1); return true; } + if ((immVal == 0xff || immVal == 0xffff) && (opc1 == MOP_wandrri12 || opc1 == MOP_xandrri13)) { + OpndInfo *opndInfo1 = insnInfo->origOpnd[kInsnSecondOpnd]; + if ((opndInfo1 != nullptr) && opndInfo1->redefined) { + return false; + } + int64 prevImmVal = static_cast(prevInsn->GetOperand(kInsnThirdOpnd)).GetValue(); + if (prevImmVal > immVal) { + return false; + } + Operand &opnd1 = prevInsn->GetOperand(kInsnSecondOpnd); + insn.SetOperand(kInsnSecondOpnd, opnd1); + Operand &opnd2 = prevInsn->GetOperand(kInsnThirdOpnd); + insn.SetOperand(kInsnThirdOpnd, opnd2); + } return false; } @@ -1158,11 +1177,6 @@ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origI OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); return CombineLsrAnd(insn, *opndInfo, is64Bits, false); } - /* - * extension dest, src0 - * and dest, dest, 0xff or 0xffff - * ===> if extension is >= imm then can eliminate extension - */ if (beforeRegAlloc && immValue != 0 && (static_cast(immValue) & (static_cast(immValue) + 1)) == 0) { OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); -- Gitee From 89c23d06876a1578a0adfe6eb67a476c99fac4f8 Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:15:50 -0700 Subject: [PATCH 024/179] Turn off rematerialization for lmbc --- .../src/cg/aarch64/aarch64_color_ra.cpp | 20 +++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp index b77161f548..7b0fb8bf74 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp @@ -455,14 +455,18 @@ void GraphColorRegAllocator::CalculatePriority(LiveRange &lr) const { auto *a64CGFunc = static_cast(cgFunc); CG *cg = a64CGFunc->GetCG(); - if (cg->GetRematLevel() >= rematConst && lr.IsRematerializable(*a64CGFunc, rematConst)) { - lr.SetRematLevel(rematConst); - } else if (cg->GetRematLevel() >= rematAddr && lr.IsRematerializable(*a64CGFunc, rematAddr)) { - lr.SetRematLevel(rematAddr); - } else if (cg->GetRematLevel() >= rematDreadLocal && lr.IsRematerializable(*a64CGFunc, rematDreadLocal)) { - lr.SetRematLevel(rematDreadLocal); - } else if (cg->GetRematLevel() >= rematDreadGlobal && lr.IsRematerializable(*a64CGFunc, rematDreadGlobal)) { - lr.SetRematLevel(rematDreadGlobal); + if (cgFunc->GetCG()->IsLmbc()) { + lr.SetRematLevel(rematOff); + } else { + if (cg->GetRematLevel() >= rematConst && lr.IsRematerializable(*a64CGFunc, rematConst)) { + lr.SetRematLevel(rematConst); + } else if (cg->GetRematLevel() >= rematAddr && lr.IsRematerializable(*a64CGFunc, rematAddr)) { + lr.SetRematLevel(rematAddr); + } else if (cg->GetRematLevel() >= rematDreadLocal && lr.IsRematerializable(*a64CGFunc, rematDreadLocal)) { + lr.SetRematLevel(rematDreadLocal); + } else if (cg->GetRematLevel() >= rematDreadGlobal && lr.IsRematerializable(*a64CGFunc, rematDreadGlobal)) { + lr.SetRematLevel(rematDreadGlobal); + } } auto calculatePriorityFunc = [&lr, &bbNum, &numDefs, &numUses, &pri, this] (uint32 bbID) { -- Gitee From 0613eb04ced04d52f5962e207dabd54103187164 Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:16:12 -0700 Subject: [PATCH 025/179] Turn on globalopt for lmbc, but leave SSA opt off --- .../include/cg/aarch64/aarch64_phases.def | 12 ++++-------- src/mapleall/maple_be/include/cg/reaching.h | 1 + .../maple_be/src/cg/aarch64/aarch64_global.cpp | 4 +++- .../src/cg/aarch64/aarch64_reaching.cpp | 18 ++++++++++++++++++ src/mapleall/maple_be/src/cg/reaching.cpp | 10 +++++----- 5 files changed, 31 insertions(+), 14 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index ff08e81852..5595b17c0c 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -36,10 +36,8 @@ ADDTARGETPHASE("ico", CGOptions::DoICO()) ADDTARGETPHASE("cfgo", !GetMIRModule()->IsCModule() && CGOptions::DoCFGO()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); - ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); - } + ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); + ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); ADDTARGETPHASE("clearrdinfo", (CGOptions::DoStoreLoadOpt()) || CGOptions::DoGlobalOpt()); ADDTARGETPHASE("prepeephole1", CGOptions::DoPrePeephole()); @@ -49,10 +47,8 @@ ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); - } + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/include/cg/reaching.h b/src/mapleall/maple_be/include/cg/reaching.h index 76d9fd9291..8a0a6cdf1b 100644 --- a/src/mapleall/maple_be/include/cg/reaching.h +++ b/src/mapleall/maple_be/include/cg/reaching.h @@ -146,6 +146,7 @@ class ReachingDefinition : public AnalysisResult { std::vector memIn; std::vector memOut; const uint32 kMaxBBNum; + uint32 stackSize = 0; private: void Initialize(); void InitDataSize(); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 1d84120c59..be3375975c 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,7 +412,9 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - CHECK_FATAL(false, "check case in ssa"); + if (cgFunc.GetCG()->IsLmbc() == false) { + CHECK_FATAL(false, "check case in ssa"); + } } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp index b5788eb167..48dcea92df 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp @@ -463,6 +463,9 @@ std::vector AArch64ReachingDefinition::FindMemDefBetweenInsn( ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffset < 0) { + memOffset = stackSize - memOffset; + } if ((offset == memOffset) || (insn->IsStorePair() && offset == memOffset + GetEachMemSizeOfPair(insn->GetMachineOpcode()))) { defInsnVec.emplace_back(insn); @@ -515,6 +518,9 @@ void AArch64ReachingDefinition::FindMemDefInBB(uint32 offset, BB &bb, InsnSet &d ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffset < 0) { + memOffset = stackSize - memOffset; + } if (offset == memOffset) { (void)defInsnSet.insert(insn); break; @@ -1000,6 +1006,9 @@ bool AArch64ReachingDefinition::FindMemUseBetweenInsn(uint32 offset, Insn *start ASSERT(memOpnd.GetIndexRegister() == nullptr, "offset must not be Register for frame MemOperand"); ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetValue(); + if (memOffset < 0) { + memOffset = stackSize - memOffset; + } if (insn->IsStore() || insn->IsPseudoInstruction()) { if (memOffset == offset) { @@ -1049,6 +1058,9 @@ InsnSet AArch64ReachingDefinition::FindDefForMemOpnd(Insn &insn, uint32 indexOrO } ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffSet < 0) { + memOffSet = stackSize - memOffSet; + } } else { memOffSet = indexOrOffset; } @@ -1100,6 +1112,9 @@ InsnSet AArch64ReachingDefinition::FindUseForMemOpnd(Insn &insn, uint8 index, bo ASSERT(memOpnd.GetIndexRegister() == nullptr, "IndexRegister no nullptr"); ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffSet < 0) { + memOffSet = stackSize - memOffSet; + } if (secondMem) { ASSERT(insn.IsStorePair(), "second MemOperand can only be defined in stp insn"); memOffSet += GetEachMemSizeOfPair(insn.GetMachineOpcode()); @@ -1213,6 +1228,9 @@ void AArch64ReachingDefinition::InitInfoForMemOperand(Insn &insn, Operand &opnd, CHECK_FATAL(index == nullptr, "Existing [x29 + index] Memory Address"); ASSERT(memOpnd.GetOffsetImmediate(), "offset must be a immediate value"); int64 offsetVal = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (offsetVal < 0) { + offsetVal = stackSize - offsetVal; + } if ((offsetVal % kMemZoomSize) != 0) { SetAnalysisMode(kRDRegAnalysis); } diff --git a/src/mapleall/maple_be/src/cg/reaching.cpp b/src/mapleall/maple_be/src/cg/reaching.cpp index 72c6fa87e3..b7d95caf59 100644 --- a/src/mapleall/maple_be/src/cg/reaching.cpp +++ b/src/mapleall/maple_be/src/cg/reaching.cpp @@ -546,11 +546,10 @@ void ReachingDefinition::InitRegAndMemInfo(const BB &bb) { } if (mode & kRDMemAnalysis) { - const int32 kStackSize = GetStackSize(); - memGen[bb.GetId()] = new DataInfo((kStackSize / kMemZoomSize), rdAlloc); - memUse[bb.GetId()] = new DataInfo((kStackSize / kMemZoomSize), rdAlloc); - memIn[bb.GetId()] = new DataInfo((kStackSize / kMemZoomSize), rdAlloc); - memOut[bb.GetId()] = new DataInfo((kStackSize / kMemZoomSize), rdAlloc); + memGen[bb.GetId()] = new DataInfo((stackSize / kMemZoomSize), rdAlloc); + memUse[bb.GetId()] = new DataInfo((stackSize / kMemZoomSize), rdAlloc); + memIn[bb.GetId()] = new DataInfo((stackSize / kMemZoomSize), rdAlloc); + memOut[bb.GetId()] = new DataInfo((stackSize / kMemZoomSize), rdAlloc); } } @@ -778,6 +777,7 @@ void ReachingDefinition::AnalysisStart() { if (!cgFunc->GetFirstBB()) { return; } + stackSize = GetStackSize(); Initialize(); /* Build in/out for function body first. (Except cleanup bb) */ BuildInOutForFuncBody(); -- Gitee From e3c1499137021a9e641fedcbc4e4bd2685a2a9de Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Fri, 10 Jun 2022 17:56:05 -0700 Subject: [PATCH 026/179] delete obsolete code in SelectAggIassign() where small struct returned in regs was represented in an iassign --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 130 ------------------ 1 file changed, 130 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 01a3e8c1a3..c2907e0c2b 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -2281,15 +2281,6 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) { uint32 lhsOffset = 0; MIRType *stmtType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(stmt.GetTyIdx()); MIRPtrType *lhsPointerType = static_cast(stmtType); - bool loadToRegs4StructReturn = false; - if (mirModule.CurFunction()->StructReturnedInRegs()) { - MIRSymbol *retSt = mirModule.CurFunction()->GetFormal(0); - if (stmt.Opnd(0)->GetOpCode() == OP_dread) { - DreadNode *dread = static_cast(stmt.Opnd(0)); - MIRSymbol *addrSym = mirModule.CurFunction()->GetLocalOrGlobalSymbol(dread->GetStIdx()); - loadToRegs4StructReturn = (retSt == addrSym); - } - } MIRType *lhsType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(lhsPointerType->GetPointedTyIdx()); if (stmt.GetFieldID() != 0) { MIRStructType *structType = static_cast(lhsType); @@ -2333,91 +2324,6 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) { rhsType = structType->GetFieldType(rhsDread->GetFieldID()); rhsOffset = static_cast(GetBecommon().GetFieldOffset(*structType, rhsDread->GetFieldID()).first); } - if (loadToRegs4StructReturn) { - /* generate move to regs for agg return */ - CHECK_FATAL(lhsSize <= k16ByteSize, "SelectAggIassign: illegal struct size"); - AArch64CallConvImpl parmlocator(GetBecommon()); - CCLocInfo pLoc; - parmlocator.LocateNextParm(*lhsType, pLoc, true, GetBecommon().GetMIRModule().CurFunction()); - /* aggregates are 8 byte aligned. */ - Operand *rhsmemopnd = nullptr; - RegOperand *result[kFourRegister]; /* up to 2 int or 4 fp */ - uint32 loadSize; - uint32 numRegs; - RegType regType; - PrimType retPty; - bool fpParm = false; - if (pLoc.numFpPureRegs) { - loadSize = pLoc.fpSize; - numRegs = pLoc.numFpPureRegs; - fpParm = true; - regType = kRegTyFloat; - retPty = (pLoc.fpSize == k4ByteSize) ? PTY_f32 : PTY_f64; - } else { - if (CGOptions::IsBigEndian()) { - loadSize = k8ByteSize; - numRegs = (lhsSize <= k8ByteSize) ? kOneRegister : kTwoRegister; - regType = kRegTyInt; - retPty = PTY_u64; - } else { - loadSize = (lhsSize <= k4ByteSize) ? k4ByteSize : k8ByteSize; - numRegs = (lhsSize <= k8ByteSize) ? kOneRegister : kTwoRegister; - regType = kRegTyInt; - retPty = PTY_u32; - } - } - bool parmCopy = IsParamStructCopy(*rhsSymbol); - for (uint32 i = 0; i < numRegs; i++) { - if (parmCopy) { - rhsmemopnd = &LoadStructCopyBase(*rhsSymbol, - (rhsOffset + static_cast(i * (fpParm ? loadSize : k8ByteSize))), - static_cast(loadSize * kBitsPerByte)); - } else { - rhsmemopnd = &GetOrCreateMemOpnd(*rhsSymbol, - (rhsOffset + static_cast(i * (fpParm ? loadSize : k8ByteSize))), - (loadSize * kBitsPerByte)); - } - result[i] = &CreateVirtualRegisterOperand(NewVReg(regType, loadSize)); - MOperator mop1 = PickLdInsn(loadSize * kBitsPerByte, retPty); - Insn &ld = GetCG()->BuildInstruction(mop1, *(result[i]), *rhsmemopnd); - GetCurBB()->AppendInsn(ld); - } - AArch64reg regs[kFourRegister]; - regs[kFirstReg] = static_cast(pLoc.reg0); - regs[kSecondReg] = static_cast(pLoc.reg1); - regs[kThirdReg] = static_cast(pLoc.reg2); - regs[kFourthReg] = static_cast(pLoc.reg3); - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg; - MOperator mop2; - if (fpParm) { - preg = regs[i]; - mop2 = (loadSize == k4ByteSize) ? MOP_xvmovs : MOP_xvmovd; - } else { - preg = (i == 0 ? R0 : R1); - mop2 = (loadSize == k4ByteSize) ? MOP_wmovrr : MOP_xmovrr; - } - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, (loadSize * kBitsPerByte), regType); - Insn &mov = GetCG()->BuildInstruction(mop2, dest, *(result[i])); - GetCurBB()->AppendInsn(mov); - } - /* Create artificial dependency to extend the live range */ - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg; - MOperator mop3; - if (fpParm) { - preg = regs[i]; - mop3 = MOP_pseudo_ret_float; - } else { - preg = (i == 0 ? R0 : R1); - mop3 = MOP_pseudo_ret_int; - } - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, loadSize * kBitsPerByte, regType); - Insn &pseudo = GetCG()->BuildInstruction(mop3, dest); - GetCurBB()->AppendInsn(pseudo); - } - return; - } rhsAlign = GetBecommon().GetTypeAlign(rhsType->GetTypeIndex()); alignUsed = std::min(lhsAlign, rhsAlign); ASSERT(alignUsed != 0, "expect non-zero"); @@ -2533,42 +2439,6 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) { rhsOffset = static_cast(GetBecommon().GetFieldOffset(*rhsStructType, rhsIread->GetFieldID()).first); isRefField = GetBecommon().IsRefField(*rhsStructType, rhsIread->GetFieldID()); } - if (loadToRegs4StructReturn) { - /* generate move to regs. */ - CHECK_FATAL(lhsSize <= k16ByteSize, "SelectAggIassign: illegal struct size"); - RegOperand *result[kTwoRegister]; /* maximum 16 bytes, 2 registers */ - uint32 loadSize; - if (CGOptions::IsBigEndian()) { - loadSize = k8ByteSize; - } else { - loadSize = (lhsSize <= k4ByteSize) ? k4ByteSize : k8ByteSize; - } - uint32 numRegs = (lhsSize <= k8ByteSize) ? kOneRegister : kTwoRegister; - for (uint32 i = 0; i < numRegs; i++) { - OfstOperand *rhsOffOpnd = &GetOrCreateOfstOpnd(rhsOffset + i * loadSize, loadSize * kBitsPerByte); - Operand &rhsmemopnd = GetOrCreateMemOpnd(MemOperand::kAddrModeBOi, loadSize * kBitsPerByte, - rhsAddrOpnd, nullptr, rhsOffOpnd, nullptr); - result[i] = &CreateVirtualRegisterOperand(NewVReg(kRegTyInt, loadSize)); - MOperator mop1 = PickLdInsn(loadSize * kBitsPerByte, PTY_u32); - Insn &ld = GetCG()->BuildInstruction(mop1, *(result[i]), rhsmemopnd); - ld.MarkAsAccessRefField(isRefField); - GetCurBB()->AppendInsn(ld); - } - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg = (i == 0 ? R0 : R1); - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, loadSize * kBitsPerByte, kRegTyInt); - Insn &mov = GetCG()->BuildInstruction(MOP_xmovrr, dest, *(result[i])); - GetCurBB()->AppendInsn(mov); - } - /* Create artificial dependency to extend the live range */ - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg = (i == 0 ? R0 : R1); - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, loadSize * kBitsPerByte, kRegTyInt); - Insn &pseudo = cg->BuildInstruction(MOP_pseudo_ret_int, dest); - GetCurBB()->AppendInsn(pseudo); - } - return; - } rhsAlign = GetBecommon().GetTypeAlign(rhsType->GetTypeIndex()); alignUsed = std::min(lhsAlign, rhsAlign); ASSERT(alignUsed != 0, "expect non-zero"); -- Gitee From 78ceb552d5a13927fe67cd694a83646af583967b Mon Sep 17 00:00:00 2001 From: William Chen Date: Mon, 13 Jun 2022 14:06:17 -0700 Subject: [PATCH 027/179] Do not optimize for ssa for physical regs. --- .../include/cg/aarch64/aarch64_phases.def | 22 +++++++++---------- .../src/cg/aarch64/aarch64_global.cpp | 4 +--- .../maple_be/src/cg/aarch64/aarch64_prop.cpp | 3 +++ 3 files changed, 14 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 5595b17c0c..531e7f0535 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,18 +17,16 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); - } + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index be3375975c..1d84120c59 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,9 +412,7 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - if (cgFunc.GetCG()->IsLmbc() == false) { - CHECK_FATAL(false, "check case in ssa"); - } + CHECK_FATAL(false, "check case in ssa"); } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp index 4c2e86be20..e3e60192fa 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp @@ -1467,6 +1467,9 @@ bool ExtendMovPattern::CheckSrcReg(regno_t srcRegNo, uint32 validNum) { bool ExtendMovPattern::BitNotAffected(const Insn &insn, uint32 validNum) { RegOperand &firstOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); + if (firstOpnd.IsPhysicalRegister()) { + return false; + } RegOperand &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); regno_t desRegNo = firstOpnd.GetRegisterNumber(); regno_t srcRegNo = secondOpnd.GetRegisterNumber(); -- Gitee From 7d71db7da9f95ea353b030593a5d000eb448881d Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 13 Jun 2022 23:36:13 -0700 Subject: [PATCH 028/179] Fold shr followed by band to bitsextract --- src/mapleall/mpl2mpl/src/constantfold.cpp | 35 +++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/src/mapleall/mpl2mpl/src/constantfold.cpp b/src/mapleall/mpl2mpl/src/constantfold.cpp index 1b296c1de7..bcd1144b18 100644 --- a/src/mapleall/mpl2mpl/src/constantfold.cpp +++ b/src/mapleall/mpl2mpl/src/constantfold.cpp @@ -47,6 +47,16 @@ namespace maple { // A. Analyze expression type // B. Analysis operator type // C. Replace the expression with the result of the operation + +// true if the constant's bits are made of only one group of contiguous 1's +// starting at bit 0 +static bool ContiguousBitsOf1(uint64 x) { + if (x == 0) { + return false; + } + return (~x & (x+1)) == (x+1); +} + BinaryNode *ConstantFold::NewBinaryNode(BinaryNode *old, Opcode op, PrimType primType, BaseNode *lhs, BaseNode *rhs) const { CHECK_NULL_FATAL(old); @@ -1917,6 +1927,31 @@ std::pair ConstantFold::FoldBinary(BinaryNode *node) { // X & (-1) -> X sum = lp.second; result = l; + } else if (op == OP_band && ContiguousBitsOf1(cst) && lp.second == 0) { + bool fold2extractbits = false; + if (l->GetOpCode() == OP_ashr || l->GetOpCode() == OP_lshr) { + BinaryNode *shrNode = static_cast(l); + if (shrNode->Opnd(1)->GetOpCode() == OP_constval) { + ConstvalNode *shrOpnd = static_cast(shrNode->Opnd(1)); + int64 shrAmt = static_cast(shrOpnd->GetConstVal())->GetValue(); + uint64 ucst = cst; + uint64 bsize = 0; + do { + bsize++; + ucst >>= 1; + } while (ucst != 0); + if (shrAmt + bsize <= GetPrimTypeSize(primType) * 8) { + fold2extractbits = true; + // change to use extractbits + result = mirModule->GetMIRBuilder()->CreateExprExtractbits(OP_extractbits, GetUnsignedPrimType(primType), shrAmt, bsize, shrNode->Opnd(0)); + sum = 0; + } + } + } + if (!fold2extractbits) { + result = NewBinaryNode(node, op, primType, PairToExpr(lPrimTypes, lp), r); + sum = 0; + } } else if (op == OP_bior && cst == -1) { // X | (-1) -> -1 sum = 0; -- Gitee From aaa5006c36b7a89b818748b4560f0d29064d176e Mon Sep 17 00:00:00 2001 From: William Chen Date: Tue, 14 Jun 2022 09:21:24 -0700 Subject: [PATCH 029/179] Fix globalopt bug of negative offset with lmbc --- .../maple_be/src/cg/aarch64/aarch64_reaching.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp index 48dcea92df..1c13d2a731 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp @@ -464,7 +464,7 @@ std::vector AArch64ReachingDefinition::FindMemDefBetweenInsn( ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffset < 0) { - memOffset = stackSize - memOffset; + memOffset = stackSize + memOffset; } if ((offset == memOffset) || (insn->IsStorePair() && offset == memOffset + GetEachMemSizeOfPair(insn->GetMachineOpcode()))) { @@ -519,7 +519,7 @@ void AArch64ReachingDefinition::FindMemDefInBB(uint32 offset, BB &bb, InsnSet &d ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffset < 0) { - memOffset = stackSize - memOffset; + memOffset = stackSize + memOffset; } if (offset == memOffset) { (void)defInsnSet.insert(insn); @@ -1007,7 +1007,7 @@ bool AArch64ReachingDefinition::FindMemUseBetweenInsn(uint32 offset, Insn *start ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetValue(); if (memOffset < 0) { - memOffset = stackSize - memOffset; + memOffset = stackSize + memOffset; } if (insn->IsStore() || insn->IsPseudoInstruction()) { @@ -1059,7 +1059,7 @@ InsnSet AArch64ReachingDefinition::FindDefForMemOpnd(Insn &insn, uint32 indexOrO ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffSet < 0) { - memOffSet = stackSize - memOffSet; + memOffSet = stackSize + memOffSet; } } else { memOffSet = indexOrOffset; @@ -1113,7 +1113,7 @@ InsnSet AArch64ReachingDefinition::FindUseForMemOpnd(Insn &insn, uint8 index, bo ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffSet < 0) { - memOffSet = stackSize - memOffSet; + memOffSet = stackSize + memOffSet; } if (secondMem) { ASSERT(insn.IsStorePair(), "second MemOperand can only be defined in stp insn"); @@ -1229,7 +1229,7 @@ void AArch64ReachingDefinition::InitInfoForMemOperand(Insn &insn, Operand &opnd, ASSERT(memOpnd.GetOffsetImmediate(), "offset must be a immediate value"); int64 offsetVal = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (offsetVal < 0) { - offsetVal = stackSize - offsetVal; + offsetVal = stackSize + offsetVal; } if ((offsetVal % kMemZoomSize) != 0) { SetAnalysisMode(kRDRegAnalysis); -- Gitee From 2f2cf824e37774a25cd33aef65221bfcc3058257 Mon Sep 17 00:00:00 2001 From: William Chen Date: Tue, 14 Jun 2022 15:55:34 -0700 Subject: [PATCH 030/179] Merge return bb for small C functions --- src/mapleall/maple_be/include/cg/cgfunc.h | 1 + src/mapleall/maple_be/src/cg/cgbb.cpp | 1 + src/mapleall/maple_be/src/cg/cgfunc.cpp | 3 ++- 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/include/cg/cgfunc.h b/src/mapleall/maple_be/include/cg/cgfunc.h index a664565276..f51ec407d9 100644 --- a/src/mapleall/maple_be/include/cg/cgfunc.h +++ b/src/mapleall/maple_be/include/cg/cgfunc.h @@ -81,6 +81,7 @@ class SpillMemOperandSet { class LiveRange; #endif /* TARGARM32 */ constexpr uint32 kVRegisterNumber = 80; +constexpr uint32 kNumBBOptReturn = 30; class CGFunc { public: enum ShiftDirection : uint8 { diff --git a/src/mapleall/maple_be/src/cg/cgbb.cpp b/src/mapleall/maple_be/src/cg/cgbb.cpp index a8635be709..f0bd3b833f 100644 --- a/src/mapleall/maple_be/src/cg/cgbb.cpp +++ b/src/mapleall/maple_be/src/cg/cgbb.cpp @@ -525,6 +525,7 @@ void Bfs::ComputeBlockOrder() { done = true; } else { LogInfo::MapleLogger() << "Error: RA BFS loop " << sortedCnt << " in func " << cgfunc->GetName() << "\n"; + CHECK_FATAL(false, ""); } } sortedCnt = sortedBBs.size(); diff --git a/src/mapleall/maple_be/src/cg/cgfunc.cpp b/src/mapleall/maple_be/src/cg/cgfunc.cpp index 56da78af48..6d7ffa22b4 100644 --- a/src/mapleall/maple_be/src/cg/cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/cgfunc.cpp @@ -2032,7 +2032,8 @@ void CGFunc::HandleFunction() { /* select instruction */ GenerateInstruction(); /* merge multi return */ - if (!func.GetModule()->IsCModule() || CGOptions::DoRetMerge() || CGOptions::OptimizeForSize()) { + if (!func.GetModule()->IsCModule() || (func.GetModule()->IsCModule() && (NumBBs() < kNumBBOptReturn)) || + CGOptions::DoRetMerge() || CGOptions::OptimizeForSize()) { MergeReturn(); } if (func.IsJava()) { -- Gitee From 5b3dc92a135ff8ef48c2c4b2be2e3001524f7979 Mon Sep 17 00:00:00 2001 From: William Chen Date: Thu, 16 Jun 2022 10:53:55 -0700 Subject: [PATCH 031/179] Reorder back-to-back cond branch and uncond brach to loop head bb --- src/mapleall/maple_be/include/cg/cfgo.h | 24 +++++++++ src/mapleall/maple_be/include/cg/loop.h | 1 + src/mapleall/maple_be/src/cg/cfgo.cpp | 65 ++++++++++++++++++++++++- src/mapleall/maple_be/src/cg/loop.cpp | 4 ++ 4 files changed, 92 insertions(+), 2 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/cfgo.h b/src/mapleall/maple_be/include/cg/cfgo.h index e7d6e07e14..2528f03413 100644 --- a/src/mapleall/maple_be/include/cg/cfgo.h +++ b/src/mapleall/maple_be/include/cg/cfgo.h @@ -18,6 +18,14 @@ #include "optimize_common.h" namespace maplebe { + +enum CfgoPhase : maple::uint8 { + CfgoDefault, + CfgoPreRegAlloc, + CfgoPostRegAlloc, + PostCfgo, +}; + class ChainingPattern : public OptimizationPattern { public: explicit ChainingPattern(CGFunc &func) : OptimizationPattern(func) { @@ -63,6 +71,14 @@ class FlipBRPattern : public OptimizationPattern { ~FlipBRPattern() override = default; bool Optimize(BB &curBB) override; + CfgoPhase GetPhase() const { + return phase; + } + void SetPhase(CfgoPhase val) { + phase = val; + } + CfgoPhase phase = CfgoDefault; + protected: void RelocateThrowBB(BB &curBB); }; @@ -120,6 +136,14 @@ class CFGOptimizer : public Optimizer { ~CFGOptimizer() override = default; void InitOptimizePatterns() override; + + CfgoPhase GetPhase() const { + return phase; + } + void SetPhase(CfgoPhase val) { + phase = val; + } + CfgoPhase phase = CfgoDefault; }; MAPLE_FUNC_PHASE_DECLARE_BEGIN(CgCfgo, maplebe::CGFunc) diff --git a/src/mapleall/maple_be/include/cg/loop.h b/src/mapleall/maple_be/include/cg/loop.h index 8a67c29a29..efe40d621f 100644 --- a/src/mapleall/maple_be/include/cg/loop.h +++ b/src/mapleall/maple_be/include/cg/loop.h @@ -172,6 +172,7 @@ class CGFuncLoops { const MapleVector &loopMembers) const; void CheckLoops() const; void PrintLoops(const CGFuncLoops &loops) const; + bool IsBBLoopMember(const BB *bb) const; const BB *GetHeader() const { return header; diff --git a/src/mapleall/maple_be/src/cg/cfgo.cpp b/src/mapleall/maple_be/src/cg/cfgo.cpp index 46822d45d2..4b89308ec5 100644 --- a/src/mapleall/maple_be/src/cg/cfgo.cpp +++ b/src/mapleall/maple_be/src/cg/cfgo.cpp @@ -42,7 +42,11 @@ void CFGOptimizer::InitOptimizePatterns() { diffPassPatterns.emplace_back(memPool->New(*cgFunc)); } diffPassPatterns.emplace_back(memPool->New(*cgFunc)); - diffPassPatterns.emplace_back(memPool->New(*cgFunc)); + FlipBRPattern *brOpt = memPool->New(*cgFunc); + if (GetPhase() == CfgoPostRegAlloc) { + brOpt->SetPhase(CfgoPostRegAlloc); + } + diffPassPatterns.emplace_back(brOpt); diffPassPatterns.emplace_back(memPool->New(*cgFunc)); diffPassPatterns.emplace_back(memPool->New(*cgFunc)); diffPassPatterns.emplace_back(memPool->New(*cgFunc)); @@ -547,7 +551,13 @@ void FlipBRPattern::RelocateThrowBB(BB &curBB) { * ftBB * targetBB * - * 2. relocate throw BB in RelocateThrowBB() + * loopHeaderBB: loopHeaderBB: + * ... ... + * cond_br loopExit: cond_br loopHeaderBB + * ftBB: ftBB: + * goto loopHeaderBB: goto loopExit + * + * 3. relocate throw BB in RelocateThrowBB() */ bool FlipBRPattern::Optimize(BB &curBB) { if (curBB.GetKind() == BB::kBBIf && !curBB.IsEmpty()) { @@ -647,6 +657,50 @@ bool FlipBRPattern::Optimize(BB &curBB) { ftBB->RemoveInsn(*brInsn); ftBB->SetKind(BB::kBBFallthru); } + } else if (GetPhase() == CfgoPostRegAlloc && ftBB->GetKind() == BB::kBBGoto && + curBB.GetLoop() != nullptr && curBB.GetLoop() == ftBB->GetLoop() && + ftBB->IsSoloGoto() && + ftBB->GetLoop()->GetHeader() == *(ftBB->GetSuccsBegin()) && + curBB.GetLoop()->IsBBLoopMember((curBB.GetSuccs().front() == ftBB) ? + curBB.GetSuccs().back() : curBB.GetSuccs().front()) == false) { + Insn *curBBBranchInsn = nullptr; + for (curBBBranchInsn = curBB.GetLastInsn(); curBBBranchInsn != nullptr; + curBBBranchInsn = curBBBranchInsn->GetPrev()) { + if (curBBBranchInsn->IsBranch()) { + break; + } + } + ASSERT(curBBBranchInsn != nullptr, "FlipBRPattern: curBB has no branch"); + Insn *brInsn = nullptr; + for (brInsn = ftBB->GetLastInsn(); brInsn != nullptr; brInsn = brInsn->GetPrev()) { + if (brInsn->IsGoto()) { + break; + } + } + ASSERT(brInsn != nullptr, "FlipBRPattern: ftBB has no branch"); + uint32 condTargetIdx = curBBBranchInsn->GetJumpTargetIdx(); + LabelOperand &condTarget = static_cast(curBBBranchInsn->GetOperand(condTargetIdx)); + MOperator mOp = curBBBranchInsn->FlipConditionOp(curBBBranchInsn->GetMachineOpcode(), condTargetIdx); + if (mOp == 0) { + return false; + } + uint32 gotoTargetIdx = brInsn->GetJumpTargetIdx(); + LabelOperand &gotoTarget = static_cast(brInsn->GetOperand(gotoTargetIdx)); + curBBBranchInsn->SetMOP(mOp); + curBBBranchInsn->SetOperand(condTargetIdx, gotoTarget); + brInsn->SetOperand(gotoTargetIdx, condTarget); + auto it = ftBB->GetSuccsBegin(); + BB *loopHeadBB = *it; + + curBB.RemoveSuccs(*brBB); + brBB->RemovePreds(curBB); + ftBB->RemoveSuccs(*loopHeadBB); + loopHeadBB->RemovePreds(*ftBB); + + curBB.PushBackSuccs(*loopHeadBB); + loopHeadBB->PushBackPreds(curBB); + ftBB->PushBackSuccs(*brBB); + brBB->PushBackPreds(*ftBB); } else { RelocateThrowBB(curBB); } @@ -847,6 +901,10 @@ bool DuplicateBBPattern::Optimize(BB &curBB) { /* === new pm === */ bool CgCfgo::PhaseRun(maplebe::CGFunc &f) { CFGOptimizer *cfgOptimizer = GetPhaseAllocator()->New(f, *GetPhaseMemPool()); + if (f.IsAfterRegAlloc()) { + (void)GetAnalysisInfoHook()->ForceRunAnalysisPhase, CGFunc>(&CgLoopAnalysis::id, f); + cfgOptimizer->SetPhase(CfgoPostRegAlloc); + } const std::string &funcClass = f.GetFunction().GetBaseClassName(); const std::string &funcName = f.GetFunction().GetBaseFuncName(); const std::string &name = funcClass + funcName; @@ -854,6 +912,9 @@ bool CgCfgo::PhaseRun(maplebe::CGFunc &f) { DotGenerator::GenerateDot("before-cfgo", f, f.GetMirModule()); } cfgOptimizer->Run(name); + if (f.IsAfterRegAlloc()) { + GetAnalysisInfoHook()->ForceEraseAnalysisPhase(f.GetUniqueID(), &CgLoopAnalysis::id); + } if (CFGO_DUMP_NEWPM) { DotGenerator::GenerateDot("after-cfgo", f, f.GetMirModule()); } diff --git a/src/mapleall/maple_be/src/cg/loop.cpp b/src/mapleall/maple_be/src/cg/loop.cpp index a402ebe4f0..48ec9eb5b7 100644 --- a/src/mapleall/maple_be/src/cg/loop.cpp +++ b/src/mapleall/maple_be/src/cg/loop.cpp @@ -161,6 +161,10 @@ void CGFuncLoops::PrintLoops(const CGFuncLoops &funcLoop) const { } } +bool CGFuncLoops::IsBBLoopMember(const BB *bb) const { + return (*(std::find(loopMembers.begin(), loopMembers.end(), bb)) == bb); +} + // partial loop body found with formLoop is NOT really needed in down stream // It should be simplied later void LoopFinder::formLoop(BB* headBB, BB* backBB) { -- Gitee From fdb762b2dab0b498988f843cc3eccff2f4c7bb51 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Mon, 20 Jun 2022 15:49:32 -0700 Subject: [PATCH 032/179] Updating to "new" lmbc --- .../include/cg/aarch64/aarch64_cgfunc.h | 14 +- src/mapleall/maple_be/include/cg/cgfunc.h | 4 +- .../src/cg/aarch64/aarch64_cgfunc.cpp | 127 ++++++++++++++++-- .../src/cg/aarch64/aarch64_memlayout.cpp | 24 +++- .../src/cg/aarch64/aarch64_proepilog.cpp | 33 +++++ 5 files changed, 177 insertions(+), 25 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index 37172e28ab..3485c2efe1 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -104,6 +104,7 @@ class AArch64CGFunc : public CGFunc { MIRType *LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList); RegOperand &GetOrCreateResOperand(const BaseNode &parent, PrimType primType); + MIRStructType *GetLmbcStructArgType(BaseNode &stmt, int32 argNo); void IntrinsifyGetAndAddInt(ListOperand &srcOpnds, PrimType pty); void IntrinsifyGetAndSetInt(ListOperand &srcOpnds, PrimType pty); @@ -191,7 +192,8 @@ class AArch64CGFunc : public CGFunc { Operand *SelectIread(const BaseNode &parent, IreadNode &expr, int extraOffset = 0, PrimType finalBitFieldDestType = kPtyInvalid) override; Operand *SelectIreadoff(const BaseNode &parent, IreadoffNode &ireadoff) override; - Operand *SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff) override; + Operand *SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff /*, MIRType &ty, + ListOperand &srcOpnds, AArch64CallConvImpl &parmLocator */) override; Operand *SelectIntConst(MIRIntConst &intConst) override; Operand *HandleFmovImm(PrimType stype, int64 val, MIRConst &mirConst, const BaseNode &parent); Operand *SelectFloatConst(MIRFloatConst &floatConst, const BaseNode &parent) override; @@ -867,7 +869,7 @@ class AArch64CGFunc : public CGFunc { void SelectParmListDreadSmallAggregate(const MIRSymbol &sym, MIRType &structType, ListOperand &srcOpnds, int32 offset, AArch64CallConvImpl &parmLocator, FieldID fieldID); - void SelectParmListIreadSmallAggregate(const IreadNode &iread, MIRType &structType, ListOperand &srcOpnds, + void SelectParmListIreadSmallAggregate(BaseNode &iread, MIRType &structType, ListOperand &srcOpnds, int32 offset, AArch64CallConvImpl &parmLocator); void SelectParmListDreadLargeAggregate(const MIRSymbol &sym, MIRType &structType, ListOperand &srcOpnds, @@ -876,12 +878,12 @@ class AArch64CGFunc : public CGFunc { AArch64CallConvImpl &parmLocator, int32 &structCopyOffset, int32 fromOffset); void CreateCallStructMemcpyToParamReg(MIRType &structType, int32 structCopyOffset, AArch64CallConvImpl &parmLocator, ListOperand &srcOpnds); - void SelectParmListForAggregate(BaseNode &argExpr, ListOperand &srcOpnds, AArch64CallConvImpl &parmLocator, - int32 &structCopyOffset); + void SelectParmListForAggregate(BaseNode &parent, BaseNode &argExpr, ListOperand &srcOpnds, + AArch64CallConvImpl &parmLocator, int32 &structCopyOffset, int32 argNo); size_t SelectParmListGetStructReturnSize(StmtNode &naryNode); bool MarkParmListCall(BaseNode &expr); - void SelectParmListPreprocessLargeStruct(BaseNode &argExpr, int32 &structCopyOffset); - void SelectParmListPreprocess(const StmtNode &naryNode, size_t start, std::set &specialArgs); + void SelectParmListPreprocessLargeStruct(BaseNode &parent, BaseNode &argExpr, int32 &structCopyOffset, int32 argNo); + void SelectParmListPreprocess(StmtNode &naryNode, size_t start, std::set &specialArgs); void SelectParmList(StmtNode &naryNode, ListOperand &srcOpnds, bool isCallNative = false); Operand *SelectClearStackCallParam(const AddrofNode &expr, int64 &offsetValue); void SelectClearStackCallParmList(const StmtNode &naryNode, ListOperand &srcOpnds, diff --git a/src/mapleall/maple_be/include/cg/cgfunc.h b/src/mapleall/maple_be/include/cg/cgfunc.h index f51ec407d9..adf7adb96f 100644 --- a/src/mapleall/maple_be/include/cg/cgfunc.h +++ b/src/mapleall/maple_be/include/cg/cgfunc.h @@ -1154,8 +1154,8 @@ class CGFunc { #endif MapleMap vregsToPregsMap; uint32 totalInsns = 0; - int32 structCopySize; - int32 maxParamStackSize; + int32 structCopySize = 0; + int32 maxParamStackSize = 0; static constexpr int kRegIncrStepLen = 80; /* reg number increate step length */ bool hasVLAOrAlloca = false; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index c2907e0c2b..8eacc20986 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -161,6 +161,28 @@ bool IsBlkassignForPush(const BlkassignoffNode &bNode) { return spBased; } +MIRStructType *AArch64CGFunc::GetLmbcStructArgType(BaseNode &stmt, int32 argNo) { + MIRType *ty = nullptr; + if (stmt.GetOpCode() == OP_call) { + CallNode &callNode = static_cast(stmt); + MIRFunction *callFunc = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(callNode.GetPUIdx()); + if (callFunc->GetFormalCount() < (argNo + 1)) { + return nullptr; /* formals less than actuals */ + } + ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(callFunc->GetFormalDefVec()[argNo].formalTyIdx); + } else if (stmt.GetOpCode() == OP_icallproto) { + IcallNode &icallproto = static_cast(stmt); + MIRType *type = GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallproto.GetRetTyIdx()); + MIRFuncType *fType = static_cast(type); + if (fType->GetParamTypeList().size() < (argNo + 1)) { + return nullptr; + } + ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(fType->GetNthParamType(argNo)); + } + CHECK_FATAL(ty && ty->IsStructType(), "lmbc agg arg error"); + return static_cast(ty); +} + RegOperand &AArch64CGFunc::GetOrCreateResOperand(const BaseNode &parent, PrimType primType) { RegOperand *resOpnd = nullptr; if (parent.GetOpCode() == OP_regassign) { @@ -3089,15 +3111,19 @@ RegOperand *AArch64CGFunc::LmbcStructReturnLoad(int32 offset) { return result; } -Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff) { +Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff /*, MIRType &ty, + ListOperand &srcOpnds, AArch64CallConvImpl &parmLocator*/) { int32 offset = ireadoff.GetOffset(); PrimType primType = ireadoff.GetPrimType(); uint32 bytelen = GetPrimTypeSize(primType); +#if 1 uint32 bitlen = bytelen * kBitsPerByte; +#endif RegType regty = GetRegTyFromPrimTy(primType); RegOperand *result = nullptr; if (offset >= 0) { - LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(static_cast(offset)); +#if 1 + LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(offset); if (info->GetPrimType() == PTY_agg) { if (info->IsOnStack()) { result = GenLmbcParamLoad(info->GetOnStackOffset(), GetPrimTypeSize(PTY_a64), kRegTyInt, PTY_a64); @@ -3118,10 +3144,23 @@ Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode result = &GetOrCreatePhysicalRegisterOperand((AArch64reg)(info->GetRegNO()), bitlen, regty); } } +#endif + CHECK_FATAL(0, "Invalid ireadfpoff offset"); } else { if (primType == PTY_agg) { - CHECK_FATAL(parent.GetOpCode() == OP_regassign, "SelectIreadfpoff of agg"); - result = LmbcStructReturnLoad(offset); +#if OLD_LMBC // TBD + if (parent.GetOpCode() == OP_call || parent.GetOpCode() == OP_icallproto) { + /* ireadfpoff is now for loading locals under calls. Large agg arg is handled via + SelectParmListPreprocess, Hence only small agg is handled here */ + SelectParmListIreadSmallAggregate(ireadoff, ty, srcOpnds, 0, parmLocator); + } else { +#endif + /* agg return */ + CHECK_FATAL(parent.GetOpCode() == OP_regassign, "SelectIreadfpoff of agg"); + result = LmbcStructReturnLoad(offset); +#if OLD_LMBC // TBD + } +#endif } else { result = GenLmbcParamLoad(offset, bytelen, regty, primType); } @@ -7353,12 +7392,26 @@ void AArch64CGFunc::SelectParmListDreadSmallAggregate(const MIRSymbol &sym, MIRT } } -void AArch64CGFunc::SelectParmListIreadSmallAggregate(const IreadNode &iread, MIRType &structType, +void AArch64CGFunc::SelectParmListIreadSmallAggregate(BaseNode &iread, MIRType &structType, ListOperand &srcOpnds, int32 offset, AArch64CallConvImpl &parmLocator) { int32 symSize = GetBecommon().GetTypeSize(structType.GetTypeIndex().GetIdx()); - RegOperand *addrOpnd0 = static_cast(HandleExpr(iread, *(iread.Opnd(0)))); - RegOperand *addrOpnd1 = &LoadIntoRegister(*addrOpnd0, iread.Opnd(0)->GetPrimType()); + RegOperand *addrOpnd1; + if (iread.GetOpCode() == OP_iread) { + RegOperand *addrOpnd0 = static_cast(HandleExpr(iread, *(iread.Opnd(0)))); + addrOpnd1 = &LoadIntoRegister(*addrOpnd0, iread.Opnd(0)->GetPrimType()); + } else if (iread.GetOpCode() == OP_ireadfpoff) { + IreadFPoffNode &ireadoff = static_cast(iread); + RegOperand *rfp = &GetOrCreatePhysicalRegisterOperand(RFP, k64BitSize, kRegTyInt); + RegOperand *addrOpnd0 = &CreateRegisterOperandOfType(PTY_a64); + ImmOperand &immOpnd = CreateImmOperand(ireadoff.GetOffset(), k32BitSize, true); + GetCurBB()->AppendInsn(GetCG()->BuildInstruction(MOP_xaddrri12, *addrOpnd0, *rfp, immOpnd)); + addrOpnd1 = &LoadIntoRegister(*addrOpnd0, PTY_i64); + } else if (iread.GetOpCode() == OP_ireadoff) { + IreadoffNode &ireadoff = static_cast(iread); + RegOperand *addrOpnd0 = static_cast(HandleExpr(ireadoff, *(ireadoff.Opnd(0)))); + addrOpnd1 = &LoadIntoRegister(*addrOpnd0, PTY_i64); + } CCLocInfo ploc; parmLocator.LocateNextParm(structType, ploc); if (ploc.reg0 == 0) { @@ -7732,8 +7785,8 @@ void AArch64CGFunc::CreateCallStructMemcpyToParamReg(MIRType &structType, int32 } } -void AArch64CGFunc::SelectParmListForAggregate(BaseNode &argExpr, ListOperand &srcOpnds, - AArch64CallConvImpl &parmLocator, int32 &structCopyOffset) { +void AArch64CGFunc::SelectParmListForAggregate(BaseNode &parent, BaseNode &argExpr, ListOperand &srcOpnds, + AArch64CallConvImpl &parmLocator, int32 &structCopyOffset, int32 argNo) { uint64 symSize; int32 rhsOffset = 0; if (argExpr.GetOpCode() == OP_dread) { @@ -7781,6 +7834,32 @@ void AArch64CGFunc::SelectParmListForAggregate(BaseNode &argExpr, ListOperand &s } else { SelectParmListIreadLargeAggregate(iread, *ty, srcOpnds, parmLocator, structCopyOffset, rhsOffset); } + } else if (argExpr.GetOpCode() == OP_ireadfpoff) { + IreadFPoffNode &iread = static_cast(argExpr); + MIRStructType *ty = GetLmbcStructArgType(parent, argNo); + if (ty == nullptr) { /* param < arg */ + return; + } + symSize = GetBecommon().GetTypeSize(ty->GetTypeIndex().GetIdx()); + if (symSize <= k16ByteSize) { + SelectParmListIreadSmallAggregate(iread, *ty, srcOpnds, rhsOffset, parmLocator); + } else { + CreateCallStructMemcpyToParamReg(*ty, structCopyOffset, parmLocator, srcOpnds); + structCopyOffset += static_cast(RoundUp(symSize, kSizeOfPtr)); + } + } else if (argExpr.GetOpCode() == OP_ireadoff) { + IreadoffNode &iread = static_cast(argExpr); + MIRStructType *ty = GetLmbcStructArgType(parent, argNo); + if (ty == nullptr) { + return; + } + symSize = GetBecommon().GetTypeSize(ty->GetTypeIndex().GetIdx()); + if (symSize <= k16ByteSize) { + SelectParmListIreadSmallAggregate(iread, *ty, srcOpnds, rhsOffset, parmLocator); + } else { + CreateCallStructMemcpyToParamReg(*ty, structCopyOffset, parmLocator, srcOpnds); + structCopyOffset += static_cast(RoundUp(symSize, kSizeOfPtr)); + } } else { CHECK_FATAL(0, "NYI"); } @@ -7823,7 +7902,7 @@ size_t AArch64CGFunc::SelectParmListGetStructReturnSize(StmtNode &naryNode) { return 0; } -void AArch64CGFunc::SelectParmListPreprocessLargeStruct(BaseNode &argExpr, int32 &structCopyOffset) { +void AArch64CGFunc::SelectParmListPreprocessLargeStruct(BaseNode &parent, BaseNode &argExpr, int32 &structCopyOffset, int32 argNo) { uint64 symSize; int32 rhsOffset = 0; if (argExpr.GetOpCode() == OP_dread) { @@ -7870,6 +7949,22 @@ void AArch64CGFunc::SelectParmListPreprocessLargeStruct(BaseNode &argExpr, int32 uint32 numMemOp = static_cast(RoundUp(symSize, kSizeOfPtr) / kSizeOfPtr); structCopyOffset += static_cast(numMemOp * kSizeOfPtr); } + } else if (argExpr.GetOpCode() == OP_ireadfpoff) { + IreadFPoffNode &ireadoff = static_cast(argExpr); + MIRStructType *ty = GetLmbcStructArgType(parent, argNo); + symSize = GetBecommon().GetTypeSize(ty->GetTypeIndex()); + if (symSize > 16 /*kParmMemcpySize*/) { +#if OLD_LMBC // TBD + MemOperand *addrOpnd0 = GenLmbcFpMemOperand(ireadoff.GetOffset(), kSizeOfPtr, RFP); + RegOperand *addrOpnd1 = &LoadIntoRegister(*addrOpnd0, PTY_i64); +#endif + RegOperand *rfp = &GetOrCreatePhysicalRegisterOperand(RFP, k64BitSize, kRegTyInt); + RegOperand *addrOpnd = &CreateRegisterOperandOfType(PTY_a64); + ImmOperand &immOpnd = CreateImmOperand(ireadoff.GetOffset(), k32BitSize, true); + GetCurBB()->AppendInsn(GetCG()->BuildInstruction(MOP_xaddrri12, *addrOpnd, *rfp, immOpnd)); + CreateCallStructParamMemcpy(nullptr, addrOpnd, static_cast(symSize), structCopyOffset, 0); + structCopyOffset += static_cast(RoundUp(symSize, kSizeOfPtr)); + } } } @@ -7901,7 +7996,7 @@ bool AArch64CGFunc::MarkParmListCall(BaseNode &expr) { return false; } -void AArch64CGFunc::SelectParmListPreprocess(const StmtNode &naryNode, size_t start, std::set &specialArgs) { +void AArch64CGFunc::SelectParmListPreprocess(StmtNode &naryNode, size_t start, std::set &specialArgs) { size_t i = start; int32 structCopyOffset = GetMaxParamStackSize() - GetStructCopySize(); for (; i < naryNode.NumOpnds(); ++i) { @@ -7914,7 +8009,7 @@ void AArch64CGFunc::SelectParmListPreprocess(const StmtNode &naryNode, size_t st if (primType != PTY_agg) { continue; } - SelectParmListPreprocessLargeStruct(*argExpr, structCopyOffset); + SelectParmListPreprocessLargeStruct(naryNode, *argExpr, structCopyOffset, i); } } @@ -8014,7 +8109,7 @@ void AArch64CGFunc::SelectParmList(StmtNode &naryNode, ListOperand &srcOpnds, bo } /* use alloca */ if (primType == PTY_agg) { - SelectParmListForAggregate(*argExpr, srcOpnds, parmLocator, structCopyOffset); + SelectParmListForAggregate(naryNode, *argExpr, srcOpnds, parmLocator, structCopyOffset, i); continue; } ty = GlobalTables::GetTypeTable().GetTypeTable()[static_cast(primType)]; @@ -9419,7 +9514,11 @@ Operand *AArch64CGFunc::GetBaseReg(const AArch64SymbolAlloc &symAlloc) { } if (fsp == nullptr) { - fsp = &GetOrCreatePhysicalRegisterOperand(RFP, kSizeOfPtr * kBitsPerByte, kRegTyInt); + if (GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { + fsp = &GetOrCreatePhysicalRegisterOperand(RSP, kSizeOfPtr * kBitsPerByte, kRegTyInt); + } else { + fsp = &GetOrCreatePhysicalRegisterOperand(RFP, kSizeOfPtr * kBitsPerByte, kRegTyInt); + } } return fsp; } diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index e7d4432330..c4c99f6109 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -58,7 +58,9 @@ uint32 AArch64MemLayout::ComputeStackSpaceRequirementForCall(StmtNode &stmt, in ty = GlobalTables::GetTypeTable().GetTypeTable()[static_cast(opnd->GetPrimType())]; } else { Opcode opndOpcode = opnd->GetOpCode(); - ASSERT(opndOpcode == OP_dread || opndOpcode == OP_iread, "opndOpcode should be OP_dread or OP_iread"); + if (be.GetMIRModule().GetFlavor() != kFlavorLmbc) { + ASSERT(opndOpcode == OP_dread || opndOpcode == OP_iread, "opndOpcode should be OP_dread or OP_iread"); + } if (opndOpcode == OP_dread) { DreadNode *dread = static_cast(opnd); MIRSymbol *sym = be.GetMIRModule().CurFunction()->GetLocalOrGlobalSymbol(dread->GetStIdx()); @@ -72,8 +74,7 @@ uint32 AArch64MemLayout::ComputeStackSpaceRequirementForCall(StmtNode &stmt, in ty = static_cast(ty)->GetFieldType(dread->GetFieldID()); } } - } else { - /* OP_iread */ + } else if (opndOpcode == OP_iread) { IreadNode *iread = static_cast(opnd); ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(iread->GetTyIdx()); ASSERT(ty->GetKind() == kTypePointer, "expect pointer"); @@ -87,6 +88,11 @@ uint32 AArch64MemLayout::ComputeStackSpaceRequirementForCall(StmtNode &stmt, in ty = static_cast(ty)->GetFieldType(iread->GetFieldID()); } } + } else if ((opndOpcode == OP_ireadfpoff || opndOpcode == OP_ireadoff || opndOpcode == OP_dreadoff) && opnd->GetPrimType() == PTY_agg) { + ty = static_cast(cgFunc)->GetLmbcStructArgType(stmt, i); + } + if (ty == nullptr) { /* type mismatch */ + continue; } } CCLocInfo ploc; @@ -190,6 +196,7 @@ void AArch64MemLayout::LayoutVarargParams() { } void AArch64MemLayout::LayoutFormalParams() { +#if OLD_LMBC // TBD bool isLmbc = (be.GetMIRModule().GetFlavor() == kFlavorLmbc); if (isLmbc && mirFunction->GetFormalCount() == 0) { /* @@ -201,6 +208,7 @@ void AArch64MemLayout::LayoutFormalParams() { segArgsRegPassed.SetSize(mirFunction->GetOutParmSize()); return; } +#endif AArch64CallConvImpl parmLocator(be); CCLocInfo ploc; @@ -255,8 +263,10 @@ void AArch64MemLayout::LayoutFormalParams() { segArgsRegPassed.SetSize(static_cast(RoundUp(segArgsRegPassed.GetSize(), align))); symLoc->SetOffset(segArgsRegPassed.GetSize()); segArgsRegPassed.SetSize(segArgsRegPassed.GetSize() + size); +#if OLD_LMBC // TBD } else if (isLmbc) { segArgsRegPassed.SetSize(segArgsRegPassed.GetSize() + k8ByteSize); +#endif } } else { /* stack */ uint32 size; @@ -371,11 +381,15 @@ void AArch64MemLayout::LayoutReturnRef(std::vector &returnDelays, symLoc->SetOffset(segRefLocals.GetSize()); segRefLocals.SetSize(segRefLocals.GetSize() + be.GetTypeSize(tyIdx)); } +#if OLD_LMBC // TBD if (be.GetMIRModule().GetFlavor() == kFlavorLmbc) { segArgsToStkPass.SetSize(mirFunction->GetOutParmSize() + kDivide2 * k8ByteSize); } else { segArgsToStkPass.SetSize(FindLargestActualArea(structCopySize)); } +#else + segArgsToStkPass.SetSize(FindLargestActualArea(structCopySize)); +#endif maxParmStackSize = static_cast(segArgsToStkPass.GetSize()); if (Globals::GetInstance()->GetOptimLevel() == 0) { AssignSpillLocationsToPseudoRegisters(); @@ -527,14 +541,18 @@ uint64 AArch64MemLayout::StackFrameSize() const { uint64 total = segArgsRegPassed.GetSize() + static_cast(cgFunc)->SizeOfCalleeSaved() + GetSizeOfRefLocals() + locals().GetSize() + GetSizeOfSpillReg(); +#if OLD_LMBC // TBD if (cgFunc->GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif if (GetSizeOfGRSaveArea() > 0) { total += RoundUp(GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); } if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } +#if OLD_LMBC // TBD } +#endif /* * if the function does not have VLA nor alloca, diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 455acc86bd..b2b8626989 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -1115,9 +1115,11 @@ void AArch64GenProEpilog::AppendInstructionAllocateCallFrameDebug(AArch64reg reg ipoint = cgFunc.GetCurBB()->GetLastInsn(); cfiOffset = stackFrameSize; (void)InsertCFIDefCfaOffset(cfiOffset, *ipoint); +#if OLD_LMBC //TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { argsToStkPassSize -= (kDivide2 * k8ByteSize); } +#endif ipoint = &CreateAndAppendInstructionForAllocateCallFrame(argsToStkPassSize, reg0, reg1, rty); CHECK_FATAL(ipoint != nullptr, "ipoint should not be nullptr at this point"); cfiOffset = GetOffsetFromCFA(); @@ -1217,7 +1219,9 @@ void AArch64GenProEpilog::GeneratePushRegs() { Operand &spOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); +#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; +#endif if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; if (isLmbc) { @@ -1255,14 +1259,18 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); } else { +#endif offset = static_cast(memLayout->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass()); +#if OLD_LMBC // TBD } +#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignment; @@ -1323,11 +1331,14 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { } uint32 dataSizeBits = size * kBitsPerByte; uint32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif offset = static_cast(memlayout->GetGRSaveAreaBaseLoc()); /* SP reference */ if (memlayout->GetSizeOfGRSaveArea() % kAarch64StackPtrAlignment) { offset += size; /* End of area should be aligned. Hole between VR and GR area */ } +#if OLD_LMBC // TBD } else { offset = -memlayout->GetSizeOfGRSaveArea(); /* FP reference */ if (memlayout->GetSizeOfGRSaveArea() % kAarch64StackPtrAlignment) { @@ -1335,6 +1346,7 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { } } uint32 grSize = -offset; +#endif uint32 start_regno = k8BitSize - (memlayout->GetSizeOfGRSaveArea() / size); ASSERT(start_regno <= k8BitSize, "Incorrect starting GR regno for GR Save Area"); for (uint32 i = start_regno + static_cast(R0); i < static_cast(R8); i++) { @@ -1345,11 +1357,15 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { } } Operand *stackLoc; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif stackLoc = &aarchCGFunc.CreateStkTopOpnd(offset + tmpOffset, dataSizeBits); +#if OLD_LMBC // TBD } else { stackLoc = aarchCGFunc.GenLmbcFpMemOperand(offset, size); } +#endif RegOperand ® = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(static_cast(i), k64BitSize, kRegTyInt); Insn &inst = @@ -1358,11 +1374,15 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { offset += size; } if (!CGOptions::UseGeneralRegOnly()) { +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif offset = static_cast(memlayout->GetVRSaveAreaBaseLoc()); +#if OLD_LMBC // TBD } else { offset = -(memlayout->GetSizeOfVRSaveArea() + grSize); } +#endif start_regno = k8BitSize - (memlayout->GetSizeOfVRSaveArea() / (size * k2BitSize)); ASSERT(start_regno <= k8BitSize, "Incorrect starting GR regno for VR Save Area"); for (uint32 i = start_regno + static_cast(V0); i < static_cast(V8); i++) { @@ -1373,11 +1393,15 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { } } Operand *stackLoc; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif stackLoc = &aarchCGFunc.CreateStkTopOpnd(offset + tmpOffset, dataSizeBits); +#if OLD_LMBC // TBD } else { stackLoc = aarchCGFunc.GenLmbcFpMemOperand(offset, size); } +#endif RegOperand ® = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(static_cast(i), k64BitSize, kRegTyFloat); Insn &inst = @@ -1479,7 +1503,9 @@ void AArch64GenProEpilog::GenerateProlog(BB &bb) { } if (useFP) { Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); +#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; +#endif int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; @@ -1682,7 +1708,10 @@ void AArch64GenProEpilog::AppendInstructionDeallocateCallFrameDebug(AArch64reg r * ldp/stp's imm should be within -512 and 504; * if ldp's imm > 504, we fall back to the ldp-add version */ +#if OLD_LMBC // TBD bool isLmbc = (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc); +#endif + bool isLmbc = false; if (cgFunc.HasVLAOrAlloca() || argsToStkPassSize == 0 || isLmbc) { int lmbcOffset = 0; if (isLmbc == false) { @@ -1769,14 +1798,18 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); } else { +#endif offset = static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass(); +#if OLD_LMBC // TBD } +#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignment; -- Gitee From 8039c4b8ba9bbdc54f369e12dff8bac85a2a2e8f Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 20 Jun 2022 21:57:07 -0700 Subject: [PATCH 033/179] Turned some optimizations back off under lmbc and re-enabled some old code The OLD_LMBC define-disabled code caused coremark to fail execution. I have to put #define OLD_LMBC on aarch64_memlayout.cpp and aarch64_proepilog.cpp so coremark can work again. --- .../include/cg/aarch64/aarch64_phases.def | 34 +++++++++++-------- .../src/cg/aarch64/aarch64_memlayout.cpp | 2 ++ .../src/cg/aarch64/aarch64_proepilog.cpp | 5 ++- 3 files changed, 26 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 531e7f0535..e5627ecba3 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,16 +17,18 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + } /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); @@ -34,8 +36,10 @@ ADDTARGETPHASE("ico", CGOptions::DoICO()) ADDTARGETPHASE("cfgo", !GetMIRModule()->IsCModule() && CGOptions::DoCFGO()); - ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); - ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); +if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); + ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); +} ADDTARGETPHASE("clearrdinfo", (CGOptions::DoStoreLoadOpt()) || CGOptions::DoGlobalOpt()); ADDTARGETPHASE("prepeephole1", CGOptions::DoPrePeephole()); @@ -45,8 +49,10 @@ ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + } ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index c4c99f6109..9612ce2c91 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -17,6 +17,8 @@ #include "becommon.h" #include "mir_nodes.h" +#define OLD_LMBC 1 + namespace maplebe { using namespace maple; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index b2b8626989..2a19960319 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -16,6 +16,8 @@ #include "cg_option.h" #include "cgfunc.h" +#define OLD_LMBC 1 + namespace maplebe { using namespace maple; @@ -1710,8 +1712,9 @@ void AArch64GenProEpilog::AppendInstructionDeallocateCallFrameDebug(AArch64reg r */ #if OLD_LMBC // TBD bool isLmbc = (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc); -#endif +#else bool isLmbc = false; +#endif if (cgFunc.HasVLAOrAlloca() || argsToStkPassSize == 0 || isLmbc) { int lmbcOffset = 0; if (isLmbc == false) { -- Gitee From c8857ced53e5d48fd5611e91e80577541d1e96e4 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Wed, 22 Jun 2022 22:07:59 -0700 Subject: [PATCH 034/179] Handle addrofoff as operand of OP_asm --- .../maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 12 ++++++++++++ src/mapleall/maple_ir/src/bin_func_import.cpp | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 8eacc20986..10983351a6 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1251,6 +1251,18 @@ void AArch64CGFunc::SelectAsm(AsmNode &node) { } break; } + case OP_addrofoff: { + auto &addrofoffNode = static_cast(*node.Opnd(i)); + Operand *inOpnd = SelectAddrofoff(addrofoffNode, node); + listInputOpnd->PushOpnd(static_cast(*inOpnd)); + PrimType pType = addrofoffNode.GetPrimType(); + listInRegPrefix->stringList.push_back( + static_cast(&CreateStringOperand(GetRegPrefixFromPrimType(pType, inOpnd->GetSize(), str)))); + if (isOutputTempNode) { + rPlusOpnd.emplace_back(std::make_pair(inOpnd, pType)); + } + break; + } case OP_constval: { CHECK_FATAL(!isOutputTempNode, "Unexpect"); auto &constNode = static_cast(*node.Opnd(i)); diff --git a/src/mapleall/maple_ir/src/bin_func_import.cpp b/src/mapleall/maple_ir/src/bin_func_import.cpp index d0dd163ba4..28c90746a7 100644 --- a/src/mapleall/maple_ir/src/bin_func_import.cpp +++ b/src/mapleall/maple_ir/src/bin_func_import.cpp @@ -44,7 +44,7 @@ void BinaryMplImport::ImportFuncIdInfo(MIRFunction *func) { func->SetPuidxOrigin(static_cast(ReadNum())); ImportInfoVector(func->GetInfoVector(), func->InfoIsString()); if (mod.GetFlavor() == kFlavorLmbc) { - func->SetFrameSize(static_cast(ReadNum())); + func->SetFrameSize(static_cast(ReadNum())); } } -- Gitee From a7131df5a4bcb66c41198c7fdd46fe43a636f9d7 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Fri, 24 Jun 2022 21:00:36 -0700 Subject: [PATCH 035/179] Handled more types of asm operands --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 24 +++++++++++++++++++ src/mapleall/maple_me/src/prop.cpp | 2 +- src/mapleall/maple_me/src/ssa_tab.cpp | 10 ++++++++ 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 10983351a6..c5e282a5f8 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1263,6 +1263,30 @@ void AArch64CGFunc::SelectAsm(AsmNode &node) { } break; } + case OP_ireadoff: { + IreadoffNode *ireadoff = static_cast(node.Opnd(i)); + Operand *inOpnd = SelectIreadoff(node, *ireadoff); + listInputOpnd->PushOpnd(static_cast(*inOpnd)); + PrimType pType = ireadoff->GetPrimType(); + listInRegPrefix->stringList.push_back( + static_cast(&CreateStringOperand(GetRegPrefixFromPrimType(pType, inOpnd->GetSize(), str)))); + if (isOutputTempNode) { + rPlusOpnd.emplace_back(std::make_pair(inOpnd, pType)); + } + break; + } + case OP_add: { + BinaryNode *addNode = static_cast(node.Opnd(i)); + Operand *inOpnd = SelectAdd(*addNode, *HandleExpr(*addNode, *addNode->Opnd(0)), *HandleExpr(*addNode, *addNode->Opnd(1)), node); + listInputOpnd->PushOpnd(static_cast(*inOpnd)); + PrimType pType = addNode->GetPrimType(); + listInRegPrefix->stringList.push_back( + static_cast(&CreateStringOperand(GetRegPrefixFromPrimType(pType, inOpnd->GetSize(), str)))); + if (isOutputTempNode) { + rPlusOpnd.emplace_back(std::make_pair(inOpnd, pType)); + } + break; + } case OP_constval: { CHECK_FATAL(!isOutputTempNode, "Unexpect"); auto &constNode = static_cast(*node.Opnd(i)); diff --git a/src/mapleall/maple_me/src/prop.cpp b/src/mapleall/maple_me/src/prop.cpp index 0ff35e8454..bbe599f1fc 100644 --- a/src/mapleall/maple_me/src/prop.cpp +++ b/src/mapleall/maple_me/src/prop.cpp @@ -596,7 +596,7 @@ MeExpr *Prop::CheckTruncation(MeExpr *lhs, MeExpr *rhs) const { } if (IsPrimitiveInteger(lhsTy->GetPrimType()) && lhsTy->GetPrimType() != PTY_ptr && lhsTy->GetPrimType() != PTY_ref) { - if (GetPrimTypeSize(lhsTy->GetPrimType()) < GetPrimTypeSize(rhs->GetPrimType())) { + if (GetPrimTypeSize(lhsTy->GetPrimType()) < GetPrimTypeSize(GetRegPrimType(rhs->GetPrimType()))) { if (GetPrimTypeSize(lhsTy->GetPrimType()) >= 4) { return irMap.CreateMeExprTypeCvt(lhsTy->GetPrimType(), rhs->GetPrimType(), *rhs); } else { diff --git a/src/mapleall/maple_me/src/ssa_tab.cpp b/src/mapleall/maple_me/src/ssa_tab.cpp index 4dfc713c94..d3e7973ced 100644 --- a/src/mapleall/maple_me/src/ssa_tab.cpp +++ b/src/mapleall/maple_me/src/ssa_tab.cpp @@ -92,6 +92,16 @@ BaseNode *SSATab::CreateSSAExpr(BaseNode *expr) { expr->SetOpnd(newOpnd, i); } } + // special lowering for trunc whose result has size less than 4 bytes + if (expr->GetOpCode() == OP_trunc && GetPrimTypeSize(expr->GetPrimType()) < 4) { + Opcode extOp = IsSignedInteger(expr->GetPrimType()) ? OP_sext : OP_zext; + uint32 extSize = GetPrimTypeBitSize(expr->GetPrimType()); + PrimType newPrimType = GetRegPrimType(expr->GetPrimType()); + expr->SetPrimType(newPrimType); + BaseNode *extNode = mirModule.CurFunction()->GetCodeMemPool()->New(extOp, newPrimType, 0, extSize); + extNode->SetOpnd(expr, 0); + return extNode; + } return arrayLowered ? expr : nullptr; } -- Gitee From 75752f4747dc335fc887ae252bd71b6c95b0662c Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Sat, 25 Jun 2022 12:21:10 -0700 Subject: [PATCH 036/179] More edits to rebase to master branch --- src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 2 +- src/mapleall/maple_be/src/cg/cgfunc.cpp | 4 ++-- src/mapleall/maple_ir/include/bin_mpl_export.h | 1 - src/mapleall/maple_ir/src/bin_mpl_export.cpp | 3 +-- src/mapleall/maple_me/include/lmbc_memlayout.h | 4 +--- 5 files changed, 5 insertions(+), 9 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index c5e282a5f8..43d00f789a 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -2128,7 +2128,7 @@ MIRType *AArch64CGFunc::LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector(static_cast(src)->GetRegisterNumber()); diff --git a/src/mapleall/maple_be/src/cg/cgfunc.cpp b/src/mapleall/maple_be/src/cg/cgfunc.cpp index 6d7ffa22b4..7ae79a83f3 100644 --- a/src/mapleall/maple_be/src/cg/cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/cgfunc.cpp @@ -1587,7 +1587,7 @@ void CGFunc::CreateLmbcFormalParamInfo() { stackOffset += (typeSize + 7) & (-8); LmbcFormalParamInfo *info = GetMemoryPool()->New(primType, offset, typeSize); lmbcParamVec.push_back(info); - if (idx == 0 && lmbcFunc.IsFirstArgReturn()) { + if (idx == 0 && func.IsFirstArgReturn()) { info->SetIsReturn(); } if (type->GetKind() == kTypeStruct) { @@ -1604,7 +1604,7 @@ void CGFunc::CreateLmbcFormalParamInfo() { } } else { /* No aggregate pass by value here */ - for (StmtNode *stmt = lmbcFunc.GetBody()->GetFirst(); stmt != nullptr; stmt = stmt->GetNext()) { + for (StmtNode *stmt = func.GetBody()->GetFirst(); stmt != nullptr; stmt = stmt->GetNext()) { if (stmt == nullptr) { break; } diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index ee8e94c615..e171763e13 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,7 +181,6 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; - MIRFunction *curFunc = nullptr; size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; diff --git a/src/mapleall/maple_ir/src/bin_mpl_export.cpp b/src/mapleall/maple_ir/src/bin_mpl_export.cpp index b28891b8ef..8197e5be40 100644 --- a/src/mapleall/maple_ir/src/bin_mpl_export.cpp +++ b/src/mapleall/maple_ir/src/bin_mpl_export.cpp @@ -1102,7 +1102,6 @@ void BinaryMplExport::WriteSymField(uint64 contentIdx) { for (auto sit = GetMIRModule().GetSymbolDefOrder().begin(); sit != GetMIRModule().GetSymbolDefOrder().end(); ++sit) { MIRSymbol *s = GlobalTables::GetGsymTable().GetSymbolFromStidx(sit->Idx()); - ASSERT(s != nullptr, "null ptr check"); // Verify: all wpofake variables should have been deleted from globaltable ASSERT(!(s->IsWpoFakeParm() || s->IsWpoFakeRet()) || s->IsDeleted(), "wpofake var not deleted"); MIRStorageClass storageClass = s->GetStorageClass(); @@ -1234,7 +1233,7 @@ void BinaryMplExport::AppendAt(const std::string &name, int32 offset) { LogInfo::MapleLogger(kLlErr) << "Error while opening the binary file: " << name << '\n'; FATAL(kLncFatal, "Error while creating the binary file: %s\n", name.c_str()); } - int seekRet = fseek(f, static_cast(offset), SEEK_SET); + int seekRet = fseek(f, (long int)offset, SEEK_SET); CHECK_FATAL(seekRet == 0, "Call fseek failed."); size_t size = buf.size(); size_t k = fwrite(&buf[0], sizeof(uint8), size, f); diff --git a/src/mapleall/maple_me/include/lmbc_memlayout.h b/src/mapleall/maple_me/include/lmbc_memlayout.h index 833b357561..923c118665 100644 --- a/src/mapleall/maple_me/include/lmbc_memlayout.h +++ b/src/mapleall/maple_me/include/lmbc_memlayout.h @@ -42,9 +42,7 @@ class SymbolAlloc { public: SymbolAlloc() : mem_segment(nullptr), offset(0) {} - ~SymbolAlloc() { - mem_segment = nullptr; - } + ~SymbolAlloc() {} MemSegment *mem_segment; int32 offset; -- Gitee From 0e838608b37573c8211206a6f5508b517a53cd14 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Sat, 25 Jun 2022 14:55:37 -0700 Subject: [PATCH 037/179] Fixed a rebase bug --- src/mapleall/maple_ir/include/bin_mpl_export.h | 2 -- src/mapleall/maple_me/include/lmbc_memlayout.h | 12 +++--------- src/mapleall/maple_me/src/lmbc_lower.cpp | 4 ++-- 3 files changed, 5 insertions(+), 13 deletions(-) diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 40404212e1..610caee1a3 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,8 +181,6 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; - public: - MIRFunction *curFunc = nullptr; private: size_t bufI = 0; std::vector buf; diff --git a/src/mapleall/maple_me/include/lmbc_memlayout.h b/src/mapleall/maple_me/include/lmbc_memlayout.h index 923c118665..83b59ba69f 100644 --- a/src/mapleall/maple_me/include/lmbc_memlayout.h +++ b/src/mapleall/maple_me/include/lmbc_memlayout.h @@ -38,14 +38,9 @@ typedef enum { class MemSegment; // describes where a symbol is allocated -class SymbolAlloc { - public: - SymbolAlloc() : mem_segment(nullptr), offset(0) {} - - ~SymbolAlloc() {} - - MemSegment *mem_segment; - int32 offset; +struct SymbolAlloc { + MemSegment *mem_segment = nullptr; + int32 offset = 0; }; // class SymbolAlloc // keeps track of the allocation of a memory segment @@ -59,7 +54,6 @@ class MemSegment { MemSegmentKind kind; int32 size; // size is negative if allocated offsets are negative - SymbolAlloc how_alloc; // this segment may be allocated inside another segment }; // class MemSegment class LMBCMemLayout { diff --git a/src/mapleall/maple_me/src/lmbc_lower.cpp b/src/mapleall/maple_me/src/lmbc_lower.cpp index f5893447ba..b56a2bf791 100644 --- a/src/mapleall/maple_me/src/lmbc_lower.cpp +++ b/src/mapleall/maple_me/src/lmbc_lower.cpp @@ -25,8 +25,8 @@ PregIdx LMBCLowerer::GetSpecialRegFromSt(const MIRSymbol *sym) { if (storageClass == kScAuto) { CHECK(sym->GetStIndex() < memlayout->sym_alloc_table.size(), "index out of range in LMBCLowerer::GetSpecialRegFromSt"); - SymbolAlloc symalloc = memlayout->sym_alloc_table[sym->GetStIndex()]; - if (symalloc.mem_segment->kind == MS_FPbased) { + SymbolAlloc *symalloc = &memlayout->sym_alloc_table[sym->GetStIndex()]; + if (symalloc->mem_segment->kind == MS_FPbased) { specreg = -kSregFp; } else { CHECK_FATAL(false, "LMBCLowerer::LowerDread: bad memory layout for local variable"); -- Gitee From 891d4c177de1737371d3f5bbc4e29ee19e6f1687 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Mon, 27 Jun 2022 14:41:54 -0700 Subject: [PATCH 038/179] Update for agg ret, caller/callee save offset. --- .../include/cg/aarch64/aarch64_cgfunc.h | 2 +- .../src/cg/aarch64/aarch64_cgfunc.cpp | 44 +++++++++++++------ .../src/cg/aarch64/aarch64_memlayout.cpp | 2 - .../src/cg/aarch64/aarch64_proepilog.cpp | 24 +++++----- 4 files changed, 45 insertions(+), 27 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index 3485c2efe1..26765eb1a9 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -130,7 +130,7 @@ class AArch64CGFunc : public CGFunc { uint32 LmbcFindTotalStkUsed(std::vector* paramList); uint32 LmbcTotalRegsUsed(); void LmbcSelectParmList(ListOperand *srcOpnds, bool isArgReturn); - bool LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src); + bool LmbcSmallAggForRet(BaseNode &bNode, Operand *src); bool LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src, std::vector **parmList); void SelectAggDassign(DassignNode &stmt) override; void SelectIassign(IassignNode &stmt) override; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 36ae400108..5fb274ba80 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1482,6 +1482,12 @@ void AArch64CGFunc::SelectRegassign(RegassignNode &stmt, Operand &opnd0) { prev->SetMOP(MOP_xldrsw); } } + if (lhsSize == PTY_agg && (stmt.Opnd(0)->GetOpCode() == OP_ireadoff || stmt.Opnd(0)->GetOpCode() == OP_ireadfpoff)) { + PregIdx pregIdx = stmt.GetRegIdx(); + if ((-pregIdx) == kSregRetval0) { + return; // Already loaded to correct return registers + } + } } RegOperand *regOpnd = nullptr; PregIdx pregIdx = stmt.GetRegIdx(); @@ -2128,7 +2134,7 @@ MIRType *AArch64CGFunc::LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector(static_cast(src)->GetRegisterNumber()); @@ -2138,9 +2144,9 @@ bool AArch64CGFunc::LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src) { /* This blkassignoff is for struct return? */ uint32 loadSize; uint32 numRegs = 0; - if (bNode.GetNext()->GetOpCode() == OP_return) { - MIRStructType *ty = static_cast( - GlobalTables::GetTypeTable().GetTypeFromTyIdx(func->GetFuncRetStructTyIdx())); + if (static_cast(bNode).GetNext()->GetOpCode() == OP_return) { + MIRStructType *ty = static_cast(func->GetReturnType()); + uint32 tySize = GetBecommon().GetTypeSize(ty->GetTypeIndex()); uint32 fpregs = FloatParamRegRequired(ty, size); if (fpregs > 0) { /* pure floating point in agg */ @@ -2159,7 +2165,7 @@ bool AArch64CGFunc::LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src) { numRegs = 2; pTy = PTY_i64; size = k4ByteSize; - switch (bNode.blockSize) { + switch (tySize) { case 1: pTy = PTY_i8; break; @@ -2177,7 +2183,7 @@ bool AArch64CGFunc::LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src) { MemOperand &mem = CreateMemOpnd(regno, 0, size * kBitsPerByte); RegOperand *res = &GetOrCreatePhysicalRegisterOperand(R0, loadSize, kRegTyInt); SelectCopy(*res, pTy, mem, pTy); - if (bNode.blockSize > static_cast(k8ByteSize)) { + if (tySize > static_cast(k8ByteSize)) { MemOperand &newMem = CreateMemOpnd(regno, k8ByteSize, size * kBitsPerByte); res = &GetOrCreatePhysicalRegisterOperand(R1, loadSize, kRegTyInt); SelectCopy(*res, pTy, newMem, pTy); @@ -3097,9 +3103,20 @@ Operand *AArch64CGFunc::SelectIreadoff(const BaseNode &parent, IreadoffNode &ire auto *baseAddr = ireadoff.Opnd(0); auto *result = &CreateRegisterOperandOfType(primType); auto *addrOpnd = HandleExpr(ireadoff, *baseAddr); - auto &memOpnd = CreateMemOpnd(LoadIntoRegister(*addrOpnd, PTY_a64), offset, bitSize); - auto mop = PickLdInsn(bitSize, primType); - GetCurBB()->AppendInsn(GetCG()->BuildInstruction(mop, *result, memOpnd)); + if (primType == PTY_agg && parent.GetOpCode() == OP_regassign) { + auto &memOpnd = CreateMemOpnd(LoadIntoRegister(*addrOpnd, PTY_a64), offset, bitSize); + auto mop = PickLdInsn(64, PTY_a64); + GetCurBB()->AppendInsn(GetCG()->BuildInstruction(mop, *result, memOpnd)); + auto ®AssignNode = static_cast(parent); + PregIdx pIdx = regAssignNode.GetRegIdx(); + CHECK_FATAL(IsSpecialPseudoRegister(pIdx), "SelectIreadfpoff of agg"); + LmbcSmallAggForRet(const_cast(parent), addrOpnd); + // result not used + } else { + auto &memOpnd = CreateMemOpnd(LoadIntoRegister(*addrOpnd, PTY_a64), offset, bitSize); + auto mop = PickLdInsn(bitSize, primType); + GetCurBB()->AppendInsn(GetCG()->BuildInstruction(mop, *result, memOpnd)); + } return result; } @@ -3152,13 +3169,11 @@ Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode int32 offset = ireadoff.GetOffset(); PrimType primType = ireadoff.GetPrimType(); uint32 bytelen = GetPrimTypeSize(primType); -#if 1 - uint32 bitlen = bytelen * kBitsPerByte; -#endif RegType regty = GetRegTyFromPrimTy(primType); RegOperand *result = nullptr; if (offset >= 0) { -#if 1 +#if OLD_LMBC // TBD + uint32 bitlen = bytelen * kBitsPerByte; LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(offset); if (info->GetPrimType() == PTY_agg) { if (info->IsOnStack()) { @@ -3180,8 +3195,9 @@ Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode result = &GetOrCreatePhysicalRegisterOperand((AArch64reg)(info->GetRegNO()), bitlen, regty); } } -#endif +#else CHECK_FATAL(0, "Invalid ireadfpoff offset"); +#endif } else { if (primType == PTY_agg) { #if OLD_LMBC // TBD diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index 9612ce2c91..c4c99f6109 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -17,8 +17,6 @@ #include "becommon.h" #include "mir_nodes.h" -#define OLD_LMBC 1 - namespace maplebe { using namespace maple; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 2a19960319..040857f33d 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -16,8 +16,6 @@ #include "cg_option.h" #include "cgfunc.h" -#define OLD_LMBC 1 - namespace maplebe { using namespace maple; @@ -1261,18 +1259,21 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; -#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { +#if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); - } else { +#else + offset = static_cast(memLayout->RealStackFrameSize() - + (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen)/* FP/LR */) - + memLayout->GetSizeOfLocals() - + memLayout->SizeOfArgsToStackPass()); #endif + } else { offset = static_cast(memLayout->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass()); -#if OLD_LMBC // TBD } -#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignment; @@ -1801,18 +1802,21 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; -#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { +#if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); - } else { +#else + offset = static_cast(memLayout->RealStackFrameSize() - + (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen)/* FP/LR */) - + memLayout->GetSizeOfLocals() - + memLayout->SizeOfArgsToStackPass()); #endif + } else { offset = static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass(); -#if OLD_LMBC // TBD } -#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignment; -- Gitee From d299c54fb55b5fdac1ddfd23e9497dca4e681a01 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 27 Jun 2022 18:36:42 -0700 Subject: [PATCH 039/179] For actual parameters corresponding to varargs, made lmbc lower struct parameters differently so as not to lose their type info --- src/mapleall/maple_me/src/lmbc_lower.cpp | 47 +++++++++++++++++++ .../maple_me/src/me_phase_manager.cpp | 3 ++ 2 files changed, 50 insertions(+) diff --git a/src/mapleall/maple_me/src/lmbc_lower.cpp b/src/mapleall/maple_me/src/lmbc_lower.cpp index b56a2bf791..7525425b79 100644 --- a/src/mapleall/maple_me/src/lmbc_lower.cpp +++ b/src/mapleall/maple_me/src/lmbc_lower.cpp @@ -411,6 +411,53 @@ BlockNode *LMBCLowerer::LowerBlock(BlockNode *block) { } break; } + case OP_call: + case OP_icallproto: { + for (size_t i = 0; i < stmt->NumOpnds(); ++i) { + if (stmt->Opnd(i)->GetPrimType() != PTY_agg) { + stmt->SetOpnd(LowerExpr(stmt->Opnd(i)), i); + } else { + bool paramInPrototype = false; + MIRFuncType *funcType = nullptr; + if (stmt->GetOpCode() == OP_icallproto) { + IcallNode *icallproto = static_cast(stmt); + funcType = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallproto->GetRetTyIdx())); + paramInPrototype = (i-1) < funcType->GetParamTypeList().size(); + } else { + CallNode *callNode = static_cast(stmt); + MIRFunction *calleeFunc = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(callNode->GetPUIdx()); + funcType = calleeFunc->GetMIRFuncType(); + paramInPrototype = i < funcType->GetParamTypeList().size(); + } + if (paramInPrototype) { + stmt->SetOpnd(LowerExpr(stmt->Opnd(i)), i); + } else { // lower to iread so the type can be provided + if (stmt->Opnd(i)->GetOpCode() == OP_iread) { + IreadNode *iread = static_cast(stmt->Opnd(i)); + iread->SetOpnd(LowerExpr(iread->Opnd(0)), 0); + } else if (stmt->Opnd(i)->GetOpCode() == OP_dread) { + AddrofNode *addrof = static_cast(stmt->Opnd(i)); + FieldID fid = addrof->GetFieldID(); + addrof->SetOpCode(OP_addrof); + addrof->SetPrimType(GetExactPtrPrimType()); + addrof->SetFieldID(0); + MIRSymbol *symbol = func->GetLocalOrGlobalSymbol(addrof->GetStIdx()); + MIRPtrType ptrType(symbol->GetTyIdx(), GetExactPtrPrimType()); + ptrType.SetTypeAttrs(symbol->GetAttrs()); + TyIdx addrTyIdx = GlobalTables::GetTypeTable().GetOrCreateMIRType(&ptrType); + if (addrTyIdx == becommon->GetSizeOfTypeSizeTable()) { + MIRType *newType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(addrTyIdx); + becommon->UpdateTypeTable(*newType); + } + IreadNode *newIread = mirModule->CurFuncCodeMemPool()->New(OP_iread, PTY_agg, addrTyIdx, fid, LowerExpr(addrof)); + stmt->SetOpnd(newIread, i); + } + } + } + } + newblk->AddStatement(stmt); + break; + } default: { for (size_t i = 0; i < stmt->NumOpnds(); ++i) { stmt->SetOpnd(LowerExpr(stmt->Opnd(i)), i); diff --git a/src/mapleall/maple_me/src/me_phase_manager.cpp b/src/mapleall/maple_me/src/me_phase_manager.cpp index a0b5419a8e..92fb5a9f53 100644 --- a/src/mapleall/maple_me/src/me_phase_manager.cpp +++ b/src/mapleall/maple_me/src/me_phase_manager.cpp @@ -149,6 +149,9 @@ bool MeFuncPM::PhaseRun(maple::MIRModule &m) { if (func->GetBody() == nullptr) { continue; } + if (!IsQuiet()) { + LogInfo::MapleLogger() << ">>>> Generating LMBC for Function < " << func->GetName() << " > [" << i - 1 << "]\n"; + } m.SetCurFunction(func); cgLower.LowerFunc(*func); MemPool *layoutMp = memPoolCtrler.NewMemPool("layout mempool", true); -- Gitee From 79ac0791f7db92be1b24efabc343c8aba0cb5a8c Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 27 Jun 2022 21:09:51 -0700 Subject: [PATCH 040/179] Deleted LmbcSelectParmList() which no longer serves any purpose --- .../include/cg/aarch64/aarch64_cgfunc.h | 1 - .../src/cg/aarch64/aarch64_cgfunc.cpp | 53 ------------------- .../maple_me/src/me_phase_manager.cpp | 2 +- 3 files changed, 1 insertion(+), 55 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index 26765eb1a9..f6fb970838 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -129,7 +129,6 @@ class AArch64CGFunc : public CGFunc { MemOperand *FixLargeMemOpnd(MOperator mOp, MemOperand &memOpnd, uint32 dSize, uint32 opndIdx); uint32 LmbcFindTotalStkUsed(std::vector* paramList); uint32 LmbcTotalRegsUsed(); - void LmbcSelectParmList(ListOperand *srcOpnds, bool isArgReturn); bool LmbcSmallAggForRet(BaseNode &bNode, Operand *src); bool LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src, std::vector **parmList); void SelectAggDassign(DassignNode &stmt) override; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 5fb274ba80..4943f25a12 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -8570,56 +8570,6 @@ void AArch64CGFunc::IntrinsifyStringIndexOf(ListOperand &srcOpnds, const MIRSymb SetCurBB(*jointBB); } -/* Lmbc calls have no argument, they are all explicit iassignspoff or - blkassign. Info collected and to be emitted here */ -void AArch64CGFunc::LmbcSelectParmList(ListOperand *srcOpnds, bool isArgReturn) { - if (GetLmbcArgInfo() == nullptr) { - return; /* no arg */ - } - CHECK_FATAL(GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc, "To be called for Lmbc model only"); - MapleVector &args = GetLmbcCallArgs(); - MapleVector &types = GetLmbcCallArgTypes(); - MapleVector &offsets = GetLmbcCallArgOffsets(); - MapleVector ®s = GetLmbcCallArgNumOfRegs(); - int iCnt = 0; - int fCnt = 0; - for (size_t i = isArgReturn ? 1 : 0; i < args.size(); i++) { - RegType ty = args[i]->GetRegisterType(); - PrimType pTy = types[i]; - AArch64reg reg; - if (args[i]->IsOfIntClass() && (iCnt + regs[i]) <= static_cast(k8ByteSize)) { - reg = static_cast(R0 + iCnt++); - RegOperand *res = &GetOrCreatePhysicalRegisterOperand( - reg, GetPrimTypeSize(pTy) * kBitsPerByte, ty); - SelectCopy(*res, pTy, *args[i], pTy); - srcOpnds->PushOpnd(*res); - } else if (!args[i]->IsOfIntClass() && (fCnt + regs[i]) <= static_cast(k8ByteSize)) { - reg = static_cast(V0 + fCnt++); - RegOperand *res = &GetOrCreatePhysicalRegisterOperand( - reg, GetPrimTypeSize(pTy) * kBitsPerByte, ty); - SelectCopy(*res, pTy, *args[i], pTy); - srcOpnds->PushOpnd(*res); - } else { - uint32 pSize = GetPrimTypeSize(pTy); - Operand &memOpd = CreateMemOpnd(RSP, offsets[i], pSize); - GetCurBB()->AppendInsn(GetCG()->BuildInstruction(PickStInsn(pSize * kBitsPerByte, pTy), - *args[i], memOpd)); - } - } - /* Load x8 if 1st arg is for agg return */ - if (isArgReturn) { - AArch64reg reg = static_cast(R8); - RegOperand *res = &GetOrCreatePhysicalRegisterOperand(reg, - GetPrimTypeSize(PTY_a64) * kBitsPerByte, - kRegTyInt); - SelectCopy(*res, PTY_a64, *args[0], PTY_a64); - srcOpnds->PushOpnd(*res); - } - ResetLmbcArgInfo(); /* reset */ - ResetLmbcArgsInRegs(); - ResetLmbcTotalArgs(); -} - void AArch64CGFunc::SelectCall(CallNode &callNode) { MIRFunction *fn = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(callNode.GetPUIdx()); MIRSymbol *fsym = GetFunction().GetLocalOrGlobalSymbol(fn->GetStIdx(), false); @@ -8633,17 +8583,14 @@ void AArch64CGFunc::SelectCall(CallNode &callNode) { ListOperand *srcOpnds = CreateListOpnd(*GetFuncScopeAllocator()); if (GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { SetLmbcCallReturnType(nullptr); - bool largeStructRet = false; if (fn->IsFirstArgReturn()) { MIRPtrType *ptrTy = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(fn->GetFormalDefVec()[0].formalTyIdx)); MIRType *sTy = GlobalTables::GetTypeTable().GetTypeFromTyIdx(ptrTy->GetPointedTyIdx()); - largeStructRet = sTy->GetSize() > k16ByteSize; SetLmbcCallReturnType(sTy); } else { MIRType *ty = fn->GetReturnType(); SetLmbcCallReturnType(ty); } - LmbcSelectParmList(srcOpnds, largeStructRet); } bool callNative = false; if ((fsym->GetName() == "MCC_CallFastNative") || (fsym->GetName() == "MCC_CallFastNativeExt") || diff --git a/src/mapleall/maple_me/src/me_phase_manager.cpp b/src/mapleall/maple_me/src/me_phase_manager.cpp index 92fb5a9f53..a9b5b3e636 100644 --- a/src/mapleall/maple_me/src/me_phase_manager.cpp +++ b/src/mapleall/maple_me/src/me_phase_manager.cpp @@ -150,7 +150,7 @@ bool MeFuncPM::PhaseRun(maple::MIRModule &m) { continue; } if (!IsQuiet()) { - LogInfo::MapleLogger() << ">>>> Generating LMBC for Function < " << func->GetName() << " > [" << i - 1 << "]\n"; + LogInfo::MapleLogger() << ">>>> Generating LMBC for Function < " << func->GetName() << " >\n"; } m.SetCurFunction(func); cgLower.LowerFunc(*func); -- Gitee From dfa7b8bd7cf22f9a2e90b26db1acddaabc13c552 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Tue, 28 Jun 2022 09:20:43 -0700 Subject: [PATCH 041/179] Fixed coredump at end of coremark. --- src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 4943f25a12..f664ab27c0 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -9545,7 +9545,7 @@ int32 AArch64CGFunc::GetBaseOffset(const SymbolAlloc &sa) { return baseOffset + sizeofFplr; } else if (sgKind == kMsSpillReg) { if (GetCG()->IsLmbc()) { - return symAlloc->GetOffset() + memLayout->SizeOfArgsToStackPass(); + return symAlloc->GetOffset() + memLayout->SizeOfArgsToStackPass() + sizeofFplr; } int32 baseOffset = symAlloc->GetOffset() + memLayout->SizeOfArgsRegisterPassed() + memLayout->GetSizeOfLocals() + memLayout->GetSizeOfRefLocals(); -- Gitee From 0d19e72140244677356f1ee520f8e2ebfe1b3f53 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Tue, 28 Jun 2022 14:08:17 -0700 Subject: [PATCH 042/179] Further changes for GetBaseOffset(). --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 20 +++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index f664ab27c0..7013f210c0 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -9535,20 +9535,32 @@ int32 AArch64CGFunc::GetBaseOffset(const SymbolAlloc &sa) { int32 offset = static_cast(symAlloc->GetOffset()); return offset; } else if (sgKind == kMsArgsRegPassed) { - int32 baseOffset = memLayout->GetSizeOfLocals() + symAlloc->GetOffset() + memLayout->GetSizeOfRefLocals(); + int32 baseOffset; + if (GetCG()->IsLmbc()) { + baseOffset = symAlloc->GetOffset() + memLayout->GetSizeOfRefLocals(); + } else { + baseOffset = memLayout->GetSizeOfLocals() + symAlloc->GetOffset() + + memLayout->GetSizeOfRefLocals(); + } return baseOffset + sizeofFplr; } else if (sgKind == kMsRefLocals) { int32 baseOffset = symAlloc->GetOffset() + memLayout->GetSizeOfLocals(); return baseOffset + sizeofFplr; } else if (sgKind == kMsLocals) { + if (GetCG()->IsLmbc()) { + CHECK_FATAL(false, "invalid lmbc's locals"); + } int32 baseOffset = symAlloc->GetOffset(); return baseOffset + sizeofFplr; } else if (sgKind == kMsSpillReg) { + int32 baseOffset; if (GetCG()->IsLmbc()) { - return symAlloc->GetOffset() + memLayout->SizeOfArgsToStackPass() + sizeofFplr; + baseOffset = symAlloc->GetOffset() + memLayout->SizeOfArgsRegisterPassed() + + memLayout->GetSizeOfRefLocals(); + } else { + baseOffset = symAlloc->GetOffset() + memLayout->SizeOfArgsRegisterPassed() + + memLayout->GetSizeOfLocals() + memLayout->GetSizeOfRefLocals(); } - int32 baseOffset = symAlloc->GetOffset() + memLayout->SizeOfArgsRegisterPassed() + memLayout->GetSizeOfLocals() + - memLayout->GetSizeOfRefLocals(); return baseOffset + sizeofFplr; } else if (sgKind == kMsArgsToStkPass) { /* this is for callers */ return static_cast(symAlloc->GetOffset()); -- Gitee From ecdb86accb90b85c7ec83b523fbf3a56f6d78f72 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Tue, 28 Jun 2022 16:17:38 -0700 Subject: [PATCH 043/179] Fix for small agg return. --- src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 7013f210c0..c422b21ba5 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1482,12 +1482,14 @@ void AArch64CGFunc::SelectRegassign(RegassignNode &stmt, Operand &opnd0) { prev->SetMOP(MOP_xldrsw); } } +#if 0 if (lhsSize == PTY_agg && (stmt.Opnd(0)->GetOpCode() == OP_ireadoff || stmt.Opnd(0)->GetOpCode() == OP_ireadfpoff)) { PregIdx pregIdx = stmt.GetRegIdx(); if ((-pregIdx) == kSregRetval0) { return; // Already loaded to correct return registers } } +#endif } RegOperand *regOpnd = nullptr; PregIdx pregIdx = stmt.GetRegIdx(); -- Gitee From d9180281c22d46296765c478f65842d44981e2b2 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Thu, 30 Jun 2022 11:24:14 -0700 Subject: [PATCH 044/179] Some fixes for lmbc vararg memlayout --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 2 ++ .../src/cg/aarch64/aarch64_memlayout.cpp | 4 ---- .../src/cg/aarch64/aarch64_proepilog.cpp | 19 +++++++++++-------- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index c422b21ba5..253c888ad2 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -10234,9 +10234,11 @@ void AArch64CGFunc::SelectCVaStart(const IntrinsiccallNode &intrnNode) { inReg++; } } +#if OLD_LMBC // TBD if (GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { stkSize += (inReg * k8ByteSize); } +#endif if (CGOptions::IsArm64ilp32()) { stkSize = static_cast(RoundUp(stkSize, k8ByteSize)); } else { diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index c4c99f6109..8dde7770ba 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -541,18 +541,14 @@ uint64 AArch64MemLayout::StackFrameSize() const { uint64 total = segArgsRegPassed.GetSize() + static_cast(cgFunc)->SizeOfCalleeSaved() + GetSizeOfRefLocals() + locals().GetSize() + GetSizeOfSpillReg(); -#if OLD_LMBC // TBD if (cgFunc->GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { -#endif if (GetSizeOfGRSaveArea() > 0) { total += RoundUp(GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); } if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } -#if OLD_LMBC // TBD } -#endif /* * if the function does not have VLA nor alloca, diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 040857f33d..3ce07cee0d 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -344,7 +344,9 @@ void AArch64GenProEpilog::GenStackGuard(BB &bb) { cgFunc.GetCurBB()->AppendInsn(insn); uint64 vArea = 0; - if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (cgFunc.GetMirModule().IsCModule() && + cgFunc.GetFunction().GetAttr(FUNCATTR_varargs) && + cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { AArch64MemLayout *ml = static_cast(cgFunc.GetMemlayout()); if (ml->GetSizeOfGRSaveArea() > 0) { vArea += RoundUp(ml->GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); @@ -401,7 +403,9 @@ BB &AArch64GenProEpilog::GenStackGuardCheckInsn(BB &bb) { cgFunc.GetCurBB()->AppendInsn(insn); uint64 vArea = 0; - if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (cgFunc.GetMirModule().IsCModule() && + cgFunc.GetFunction().GetAttr(FUNCATTR_varargs) && + cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { AArch64MemLayout *ml = static_cast(cgFunc.GetMemlayout()); if (ml->GetSizeOfGRSaveArea() > 0) { vArea += RoundUp(ml->GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); @@ -1219,9 +1223,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { Operand &spOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); -#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; -#endif if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; if (isLmbc) { @@ -1279,7 +1281,9 @@ void AArch64GenProEpilog::GeneratePushRegs() { offset -= kAarch64StackPtrAlignment; } - if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (cgFunc.GetMirModule().IsCModule() && + cgFunc.GetFunction().GetAttr(FUNCATTR_varargs) && + cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { /* GR/VR save areas are above the callee save area */ AArch64MemLayout *ml = static_cast(cgFunc.GetMemlayout()); auto saveareasize = static_cast(RoundUp(ml->GetSizeOfGRSaveArea(), kSizeOfPtr * k2BitSize) + @@ -1506,9 +1510,7 @@ void AArch64GenProEpilog::GenerateProlog(BB &bb) { } if (useFP) { Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); -#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; -#endif int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; @@ -1822,7 +1824,8 @@ void AArch64GenProEpilog::GeneratePopRegs() { offset -= kAarch64StackPtrAlignment; } - if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs) && + cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { /* GR/VR save areas are above the callee save area */ AArch64MemLayout *ml = static_cast(cgFunc.GetMemlayout()); auto saveareasize = static_cast(RoundUp(ml->GetSizeOfGRSaveArea(), kSizeOfPtr * k2BitSize) + -- Gitee From b1af2eb2f47b63f6b4cf9eb16763c90b33241a86 Mon Sep 17 00:00:00 2001 From: William Chen Date: Wed, 8 Jun 2022 16:21:12 -0700 Subject: [PATCH 045/179] Changes from mplcglmbc10 --- .../include/cg/aarch64/aarch64_cgfunc.h | 9 ++- .../src/cg/aarch64/aarch64_cgfunc.cpp | 58 +++++++++---------- .../src/cg/aarch64/aarch64_color_ra.cpp | 2 +- .../src/cg/aarch64/aarch64_proepilog.cpp | 20 +++---- src/mapleall/maple_be/src/cg/cgfunc.cpp | 15 +++-- src/mapleall/maple_be/src/cg/emit.cpp | 6 +- .../maple_ir/include/bin_mpl_export.h | 1 + src/mapleall/maple_ir/include/mir_type.h | 10 ---- src/mapleall/maple_ir/src/bin_func_export.cpp | 2 +- src/mapleall/maple_ir/src/bin_func_import.cpp | 34 +++++------ src/mapleall/maple_ir/src/bin_mpl_import.cpp | 4 +- src/mapleall/maple_ir/src/mir_lower.cpp | 8 +-- src/mapleall/maple_me/src/irmap_build.cpp | 3 +- src/mapleall/maple_me/src/irmap_emit.cpp | 3 +- .../maple_me/src/me_phase_manager.cpp | 2 +- 15 files changed, 80 insertions(+), 97 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index c17ca31eac..bf154e7657 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -38,7 +38,7 @@ class LmbcArgInfo { MapleVector lmbcCallArgTypes; MapleVector lmbcCallArgOffsets; MapleVector lmbcCallArgNumOfRegs; // # of regs needed to complete struct - uint32 lmbcTotalStkUsed = -1; // remove when explicit addr for large agg is available + uint32 lmbcTotalStkUsed = -1; // TBD: remove when explicit addr for large agg is available }; class AArch64CGFunc : public CGFunc { @@ -129,8 +129,8 @@ class AArch64CGFunc : public CGFunc { uint32 LmbcFindTotalStkUsed(std::vector* paramList); uint32 LmbcTotalRegsUsed(); void LmbcSelectParmList(ListOperand *srcOpnds, bool isArgReturn); - bool LmbcSmallAggForRet(const BlkassignoffNode &bNode, const Operand *src); - bool LmbcSmallAggForCall(BlkassignoffNode &bNode, const Operand *src, std::vector **parmList); + bool LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src); + bool LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src, std::vector **parmList); void SelectAggDassign(DassignNode &stmt) override; void SelectIassign(IassignNode &stmt) override; void SelectIassignoff(IassignoffNode &stmt) override; @@ -492,8 +492,7 @@ class AArch64CGFunc : public CGFunc { void AssignLmbcFormalParams() override; void LmbcGenSaveSpForAlloca() override; MemOperand *GenLmbcFpMemOperand(int32 offset, uint32 byteSize, AArch64reg base = RFP); - RegOperand *GenLmbcParamLoad(int32 offset, uint32 byteSize, RegType regType, - PrimType primType, AArch64reg baseRegno = RFP); + RegOperand *GenLmbcParamLoad(int32 offset, uint32 byteSize, RegType regType, PrimType primType, AArch64reg baseRegno = RFP); RegOperand *LmbcStructReturnLoad(int32 offset); Operand *GetBaseReg(const AArch64SymbolAlloc &symAlloc); int32 GetBaseOffset(const SymbolAlloc &symAlloc) override; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index b9893f7387..3ba48a2cbc 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1987,9 +1987,8 @@ void AArch64CGFunc::SelectIassignfpoff(IassignFPoffNode &stmt, Operand &opnd) { MIRType *rType = GetLmbcCallReturnType(); bool isPureFpStruct = false; uint32 numRegs = 0; - if (rType && rType->GetPrimType() == PTY_agg && opnd.IsRegister() && - static_cast(opnd).IsPhysicalRegister()) { - CHECK_FATAL(rType->GetSize() <= k16BitSize, "SelectIassignfpoff invalid agg size"); + if (rType && rType->GetPrimType() == PTY_agg && opnd.IsRegister() && static_cast(opnd).IsPhysicalRegister()) { + CHECK_FATAL(rType->GetSize() <= 16, "SelectIassignfpoff invalid agg size"); uint32 fpSize; numRegs = FloatParamRegRequired(static_cast(rType), fpSize); if (numRegs) { @@ -2000,8 +1999,8 @@ void AArch64CGFunc::SelectIassignfpoff(IassignFPoffNode &stmt, Operand &opnd) { uint32 byteSize = GetPrimTypeSize(primType); uint32 bitlen = byteSize * kBitsPerByte; if (isPureFpStruct) { - for (uint32 i = 0 ; i < numRegs; ++i) { - MemOperand *memOpnd = GenLmbcFpMemOperand(offset + static_cast(i * byteSize), byteSize); + for (int i = 0 ; i < numRegs; ++i) { + MemOperand *memOpnd = GenLmbcFpMemOperand(offset + (i * byteSize), byteSize); RegOperand &srcOpnd = GetOrCreatePhysicalRegisterOperand(AArch64reg(V0 + i), bitlen, kRegTyFloat); MOperator mOp = PickStInsn(bitlen, primType); Insn &store = GetCG()->BuildInstruction(mOp, srcOpnd, *memOpnd); @@ -2044,8 +2043,8 @@ void AArch64CGFunc::SelectIassignspoff(PrimType pTy, int32 offset, Operand &opnd } /* Search for CALL/ICALL/ICALLPROTO node, must be called from a blkassignoff node */ -MIRType *AArch64CGFunc::LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList) const { - for (; stmt != nullptr; stmt = stmt->GetNext()) { +MIRType *AArch64CGFunc::LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList) { + for ( ; stmt != nullptr; stmt = stmt->GetNext()) { if (stmt->GetOpCode() == OP_call || stmt->GetOpCode() == OP_icallproto) { break; } @@ -2161,7 +2160,7 @@ bool AArch64CGFunc::LmbcSmallAggForCall(BlkassignoffNode &bNode, const Operand * MemOperand &mem = CreateMemOpnd(regno, s, size * kBitsPerByte); RegOperand *res = &CreateVirtualRegisterOperand(NewVReg(kRegTyFloat, size)); SelectCopy(*res, pTy, mem, pTy); - SetLmbcArgInfo(res, pTy, 0, static_cast(fpregs)); + SetLmbcArgInfo(res, pTy, 0, fpregs); IncLmbcArgsInRegs(kRegTyFloat); } IncLmbcTotalArgs(); @@ -2209,7 +2208,7 @@ uint32 AArch64CGFunc::LmbcFindTotalStkUsed(std::vector *paramList) { CCLocInfo pLoc; for (TyIdx tyIdx : *paramList) { MIRType *ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(tyIdx); - (void)parmlocator.LocateNextParm(*ty, pLoc); + parmlocator.LocateNextParm(*ty, pLoc); } return 0; } @@ -2225,12 +2224,12 @@ uint32 AArch64CGFunc::LmbcTotalRegsUsed() { uint32 fCnt = 0; for (uint32 i = 0; i < regs.size(); i++) { if (IsPrimitiveInteger(types[i])) { - if ((iCnt + static_cast(regs[i])) <= k8ByteSize) { - iCnt += static_cast(regs[i]); + if ((iCnt + regs[i]) <= k8ByteSize) { + iCnt += regs[i]; }; } else { - if ((fCnt + static_cast(regs[i])) <= k8ByteSize) { - fCnt += static_cast(regs[i]); + if ((fCnt + regs[i]) <= k8ByteSize) { + fCnt += regs[i]; }; } } @@ -2277,7 +2276,7 @@ void AArch64CGFunc::SelectBlkassignoff(BlkassignoffNode &bNode, Operand *src) opndVec.push_back(regResult); /* result */ opndVec.push_back(PrepareMemcpyParamOpnd(offset, *dest)); /* param 0 */ opndVec.push_back(src); /* param 1 */ - opndVec.push_back(PrepareMemcpyParamOpnd(static_cast(static_cast(bNode.blockSize)))); /* param 2 */ + opndVec.push_back(PrepareMemcpyParamOpnd(bNode.blockSize));/* param 2 */ SelectLibCall("memcpy", opndVec, PTY_a64, PTY_a64); } @@ -2681,7 +2680,7 @@ void AArch64CGFunc::SelectReturnSendOfStructInRegs(BaseNode *x) { /* generate move to regs for agg return */ AArch64CallConvImpl parmlocator(GetBecommon()); CCLocInfo pLoc; - (void)parmlocator.LocateNextParm(*mirType, pLoc, true, GetBecommon().GetMIRModule().CurFunction()); + parmlocator.LocateNextParm(*mirType, pLoc, true, GetBecommon().GetMIRModule().CurFunction()); /* aggregates are 8 byte aligned. */ Operand *rhsmemopnd = nullptr; RegOperand *result[kFourRegister]; /* up to 2 int or 4 fp */ @@ -3203,8 +3202,8 @@ RegOperand *AArch64CGFunc::LmbcStructReturnLoad(int32 offset) { if (numFpRegs > 0) { PrimType pType = (fpSize <= k4ByteSize) ? PTY_f32 : PTY_f64; for (int32 i = (numFpRegs - kOneRegister); i > 0; --i) { - result = GenLmbcParamLoad(offset + (i * static_cast(fpSize)), fpSize, kRegTyFloat, pType); - AArch64reg regNo = static_cast(V0 + static_cast(i)); + result = GenLmbcParamLoad(offset + (i * fpSize), fpSize, kRegTyFloat, pType); + AArch64reg regNo = static_cast(V0 + i); RegOperand *reg = &GetOrCreatePhysicalRegisterOperand(regNo, fpSize * kBitsPerByte, kRegTyFloat); SelectCopy(*reg, pType, *result, pType); Insn &pseudo = GetCG()->BuildInstruction(MOP_pseudo_ret_float, *reg); @@ -3216,7 +3215,7 @@ RegOperand *AArch64CGFunc::LmbcStructReturnLoad(int32 offset) { } else if (sz <= k8ByteSize) { result = GenLmbcParamLoad(offset, k8ByteSize, kRegTyInt, PTY_i64); } else if (sz <= k16ByteSize) { - result = GenLmbcParamLoad(offset + k8ByteSizeInt, k8ByteSize, kRegTyInt, PTY_i64); + result = GenLmbcParamLoad(offset + k8ByteSize, k8ByteSize, kRegTyInt, PTY_i64); RegOperand *r1 = &GetOrCreatePhysicalRegisterOperand(R1, k8ByteSize * kBitsPerByte, kRegTyInt); SelectCopy(*r1, PTY_i64, *result, PTY_i64); Insn &pseudo = GetCG()->BuildInstruction(MOP_pseudo_ret_int, *r1); @@ -3239,8 +3238,7 @@ Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode if (info->IsOnStack()) { result = GenLmbcParamLoad(info->GetOnStackOffset(), GetPrimTypeSize(PTY_a64), kRegTyInt, PTY_a64); regno_t baseRegno = result->GetRegisterNumber(); - result = GenLmbcParamLoad(offset - static_cast(info->GetOffset()), - bytelen, regty, primType, (AArch64reg)baseRegno); + result = GenLmbcParamLoad(offset - info->GetOffset(), bytelen, regty, primType, (AArch64reg)baseRegno); } else if (primType == PTY_agg) { CHECK_FATAL(parent.GetOpCode() == OP_regassign, "SelectIreadfpoff of agg"); result = LmbcStructReturnLoad(offset); @@ -6542,10 +6540,10 @@ void AArch64CGFunc::AssignLmbcFormalParams() { param->SetRegNO(0); } else { param->SetRegNO(fpReg); - if (!param->HasRegassign()) { + if (param->HasRegassign() == false) { uint32 bytelen = GetPrimTypeSize(primType); uint32 bitlen = bytelen * kBitsPerByte; - MemOperand *mOpnd = GenLmbcFpMemOperand(static_cast(offset), bytelen); + MemOperand *mOpnd = GenLmbcFpMemOperand(offset, bytelen); RegOperand &src = GetOrCreatePhysicalRegisterOperand(AArch64reg(fpReg), bitlen, kRegTyFloat); MOperator mOp = PickStInsn(bitlen, primType); Insn &store = GetCG()->BuildInstruction(mOp, src, *mOpnd); @@ -6569,10 +6567,10 @@ void AArch64CGFunc::AssignLmbcFormalParams() { } else { param->SetRegNO(intReg); param->SetIsOnStack(); - param->SetOnStackOffset(((intReg - R0 + fpReg) - V0) * k8ByteSize); + param->SetOnStackOffset((intReg - R0 + fpReg - V0) * k8ByteSize); uint32 bytelen = GetPrimTypeSize(PTY_a64); uint32 bitlen = bytelen * kBitsPerByte; - MemOperand *mOpnd = GenLmbcFpMemOperand(static_cast(param->GetOnStackOffset()), bytelen); + MemOperand *mOpnd = GenLmbcFpMemOperand(param->GetOnStackOffset(), bytelen); RegOperand &src = GetOrCreatePhysicalRegisterOperand(AArch64reg(intReg), bitlen, kRegTyInt); MOperator mOp = PickStInsn(bitlen, PTY_a64); Insn &store = GetCG()->BuildInstruction(mOp, src, *mOpnd); @@ -6631,13 +6629,14 @@ void AArch64CGFunc::AssignLmbcFormalParams() { } void AArch64CGFunc::LmbcGenSaveSpForAlloca() { - if (GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc || !HasVLAOrAlloca()) { + if (GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc || HasVLAOrAlloca() == false) { return; } Operand &spOpnd = GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); RegOperand &spSaveOpnd = CreateVirtualRegisterOperand(NewVReg(kRegTyInt, kSizeOfPtr)); Insn &save = GetCG()->BuildInstruction(MOP_xmovrr, spSaveOpnd, spOpnd); GetFirstBB()->AppendInsn(save); + //save.SetFrameDef(true); for (auto *retBB : GetExitBBsVec()) { Insn &restore = GetCG()->BuildInstruction(MOP_xmovrr, spOpnd, spSaveOpnd); retBB->AppendInsn(restore); @@ -7952,8 +7951,7 @@ size_t AArch64CGFunc::SelectParmListGetStructReturnSize(StmtNode &naryNode) { } } else if (naryNode.GetOpCode() == OP_icallproto) { IcallNode &icallProto = static_cast(naryNode); - MIRFuncType *funcTy = static_cast( - GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallProto.GetRetTyIdx())); + MIRFuncType *funcTy = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallProto.GetRetTyIdx())); if (funcTy->FirstArgReturn()) { MIRType *ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(funcTy->GetNthParamType(0)); return GetBecommon().GetTypeSize(static_cast(ty)->GetPointedTyIdx()); @@ -8080,8 +8078,7 @@ void AArch64CGFunc::SelectParmList(StmtNode &naryNode, ListOperand &srcOpnds, bo firstArgReturn = callee->IsFirstArgReturn(); } else if (naryNode.GetOpCode() == OP_icallproto) { IcallNode *icallnode = &static_cast(naryNode); - MIRFuncType *funcType = static_cast( - GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallnode->GetRetTyIdx())); + MIRFuncType *funcType = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallnode->GetRetTyIdx())); firstArgReturn = funcType->FirstArgReturn(); } BB *curBBrecord = GetCurBB(); @@ -8630,8 +8627,7 @@ void AArch64CGFunc::SelectCall(CallNode &callNode) { SetLmbcCallReturnType(nullptr); bool largeStructRet = false; if (fn->IsFirstArgReturn()) { - MIRPtrType *ptrTy = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx( - fn->GetFormalDefVec()[0].formalTyIdx)); + MIRPtrType *ptrTy = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(fn->GetFormalDefVec()[0].formalTyIdx)); MIRType *sTy = GlobalTables::GetTypeTable().GetTypeFromTyIdx(ptrTy->GetPointedTyIdx()); largeStructRet = sTy->GetSize() > k16ByteSize; SetLmbcCallReturnType(sTy); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp index a01201e55a..e7f80e2a4b 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp @@ -4979,7 +4979,7 @@ bool GraphColorRegAllocator::AllocateRegisters() { MarkCalleeSaveRegs(); - if (!seenFP) { + if (seenFP == false) { cgFunc->UnsetSeenFP(); } if (GCRA_DUMP) { diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 5674b9107f..546c386c7e 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -1226,7 +1226,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { } else { immOpnd = &aarchCGFunc.CreateImmOperand(argsToStkPassSize, k32BitSize, true); } - if (!isLmbc || cgFunc.SeenFP() || cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (isLmbc == false || cgFunc.SeenFP() || cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { aarchCGFunc.SelectAdd(fpOpnd, spOpnd, *immOpnd, PTY_u64); } cgFunc.GetCurBB()->GetLastInsn()->SetFrameDef(true); @@ -1256,11 +1256,11 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { - offset = static_cast((memLayout->RealStackFrameSize() - - aarchCGFunc.SizeOfCalleeSaved()) - memLayout->GetSizeOfLocals()); + offset = static_cast(memLayout->RealStackFrameSize() - + aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); } else { - offset = (static_cast(memLayout->RealStackFrameSize() - - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - /* for FP/LR */ + offset = static_cast(memLayout->RealStackFrameSize() - + (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass()); } @@ -1685,7 +1685,7 @@ void AArch64GenProEpilog::AppendInstructionDeallocateCallFrameDebug(AArch64reg r bool isLmbc = (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc); if (cgFunc.HasVLAOrAlloca() || argsToStkPassSize == 0 || isLmbc) { int lmbcOffset = 0; - if (!isLmbc) { + if (isLmbc == false) { stackFrameSize -= argsToStkPassSize; } else { lmbcOffset = argsToStkPassSize - (kDivide2 * k8ByteSize); @@ -1770,11 +1770,11 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { - offset = static_cast((memLayout->RealStackFrameSize() - - aarchCGFunc.SizeOfCalleeSaved()) - memLayout->GetSizeOfLocals()); + offset = static_cast(memLayout->RealStackFrameSize() - + aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); } else { - offset = (static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - /* for FP/LR */ + offset = static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - + (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass(); } diff --git a/src/mapleall/maple_be/src/cg/cgfunc.cpp b/src/mapleall/maple_be/src/cg/cgfunc.cpp index 2a9176e373..d41db1288f 100644 --- a/src/mapleall/maple_be/src/cg/cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/cgfunc.cpp @@ -1565,16 +1565,16 @@ void CGFunc::CreateLmbcFormalParamInfo() { PrimType primType; uint32 offset; uint32 typeSize; - MIRFunction &lmbcFunc = GetFunction(); - if (lmbcFunc.GetFormalCount() > 0) { + MIRFunction &func = GetFunction(); + if (func.GetFormalCount() > 0) { /* Whenever lmbc cannot delete call type info, the prototype is available */ uint32 stackOffset = 0; - for (size_t idx = 0; idx < lmbcFunc.GetFormalCount(); ++idx) { - MIRSymbol *sym = lmbcFunc.GetFormal(idx); + for (size_t idx = 0; idx < func.GetFormalCount(); ++idx) { + MIRSymbol *sym = func.GetFormal(idx); MIRType *type; TyIdx tyIdx; if (sym) { - tyIdx = lmbcFunc.GetFormalDefVec()[idx].formalTyIdx; + tyIdx = func.GetFormalDefVec()[idx].formalTyIdx; type = GlobalTables::GetTypeTable().GetTypeFromTyIdx(tyIdx); } else { FormalDef vec = const_cast(GetBecommon().GetMIRModule().CurFunction())->GetFormalDefAt(idx); @@ -1637,7 +1637,7 @@ void CGFunc::CreateLmbcFormalParamInfo() { ); /* When a scalar param address is taken, its regassign is not in the 1st block */ - for (StmtNode *stmt = lmbcFunc.GetBody()->GetFirst(); stmt != nullptr; stmt = stmt->GetNext()) { + for (StmtNode *stmt = func.GetBody()->GetFirst(); stmt != nullptr; stmt = stmt->GetNext()) { if (stmt == nullptr) { break; } @@ -1656,8 +1656,7 @@ void CGFunc::CreateLmbcFormalParamInfo() { if (ireadNode->GetOffset() < 0) { continue; } - LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(static_cast(ireadNode->GetOffset())); - ASSERT_NOT_NULL(info); + LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(ireadNode->GetOffset()); info->SetHasRegassign(); } diff --git a/src/mapleall/maple_be/src/cg/emit.cpp b/src/mapleall/maple_be/src/cg/emit.cpp index f7be3e09bb..d7bc117c94 100644 --- a/src/mapleall/maple_be/src/cg/emit.cpp +++ b/src/mapleall/maple_be/src/cg/emit.cpp @@ -2170,9 +2170,9 @@ void Emitter::EmitGlobalVar(const MIRSymbol &globalVar) { void Emitter::EmitGlobalVars(std::vector> &globalVars) { if (GetCG()->IsLmbc() && GetCG()->GetGP() != nullptr) { - (void)Emit(asmInfo->GetLocal()).Emit("\t").Emit(GetCG()->GetGP()->GetName()).Emit("\n"); - (void)Emit(asmInfo->GetComm()).Emit("\t").Emit(GetCG()->GetGP()->GetName()); - (void)Emit(", ").Emit(GetCG()->GetMIRModule()->GetGlobalMemSize()).Emit(", ").Emit("8\n"); + Emit(asmInfo->GetLocal()).Emit("\t").Emit(GetCG()->GetGP()->GetName()).Emit("\n"); + Emit(asmInfo->GetComm()).Emit("\t").Emit(GetCG()->GetGP()->GetName()); + Emit(", ").Emit(GetCG()->GetMIRModule()->GetGlobalMemSize()).Emit(", ").Emit("8\n"); } /* load globalVars profile */ if (globalVars.empty()) { diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 918c8e04eb..9cada84eb4 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,6 +181,7 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; + MIRFunction *curFunc = nullptr; size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; diff --git a/src/mapleall/maple_ir/include/mir_type.h b/src/mapleall/maple_ir/include/mir_type.h index 43aca62561..7c3c315c39 100644 --- a/src/mapleall/maple_ir/include/mir_type.h +++ b/src/mapleall/maple_ir/include/mir_type.h @@ -1205,14 +1205,6 @@ class MIRStructType : public MIRType { isImported = flag; } - bool IsUsed() const { - return isUsed; - } - - void SetIsUsed(bool flag) { - isUsed = flag; - } - bool IsCPlusPlus() const { return isCPlusPlus; } @@ -1384,7 +1376,6 @@ class MIRStructType : public MIRType { vTableMethods.clear(); iTableMethods.clear(); isImported = false; - isUsed = false; hasVolatileField = false; hasVolatileFieldSet = false; } @@ -1487,7 +1478,6 @@ class MIRStructType : public MIRType { // implementation functions, For interfaces, they are abstact functions. // Weak indicates the actual definition is in another module. bool isImported = false; - bool isUsed = false; bool isCPlusPlus = false; // empty struct in C++ has size 1 byte mutable bool hasVolatileField = false; // for caching computed value mutable bool hasVolatileFieldSet = false; // if true, just read hasVolatileField; diff --git a/src/mapleall/maple_ir/src/bin_func_export.cpp b/src/mapleall/maple_ir/src/bin_func_export.cpp index 2015da5d32..a9e8a10e60 100644 --- a/src/mapleall/maple_ir/src/bin_func_export.cpp +++ b/src/mapleall/maple_ir/src/bin_func_export.cpp @@ -87,7 +87,7 @@ void BinaryMplExport::OutputLocalSymbol(MIRSymbol *sym) { void BinaryMplExport::OutputPreg(MIRPreg *preg) { if (preg->GetPregNo() < 0) { WriteNum(kBinSpecialReg); - Write(static_cast(-preg->GetPregNo())); + Write(-preg->GetPregNo()); return; } std::unordered_map::iterator it = localPregMark.find(preg); diff --git a/src/mapleall/maple_ir/src/bin_func_import.cpp b/src/mapleall/maple_ir/src/bin_func_import.cpp index e815c828b8..580d52abc4 100644 --- a/src/mapleall/maple_ir/src/bin_func_import.cpp +++ b/src/mapleall/maple_ir/src/bin_func_import.cpp @@ -50,8 +50,8 @@ void BinaryMplImport::ImportFuncIdInfo(MIRFunction *func) { } void BinaryMplImport::ImportBaseNode(Opcode &o, PrimType &typ) { - o = static_cast(Read()); - typ = static_cast(Read()); + o = (Opcode)Read(); + typ = (PrimType)Read(); } MIRSymbol *BinaryMplImport::ImportLocalSymbol(MIRFunction *func) { @@ -61,8 +61,8 @@ MIRSymbol *BinaryMplImport::ImportLocalSymbol(MIRFunction *func) { } if (tag < 0) { CHECK_FATAL(static_cast(-tag) < localSymTab.size(), "index out of bounds"); - return localSymTab.at(static_cast(-tag)); - } + return localSymTab.at(-tag); + } CHECK_FATAL(tag == kBinSymbol, "expecting kBinSymbol in ImportLocalSymbol()"); MIRSymbol *sym = func->GetSymTab()->CreateSymbol(kScopeLocal); localSymTab.push_back(sym); @@ -99,11 +99,11 @@ PregIdx BinaryMplImport::ImportPreg(MIRFunction *func) { } if (tag < 0) { CHECK_FATAL(static_cast(-tag) < localPregTab.size(), "index out of bounds"); - return localPregTab.at(static_cast(-tag)); + return localPregTab.at(-tag); } CHECK_FATAL(tag == kBinPreg, "expecting kBinPreg in ImportPreg()"); - PrimType primType = static_cast(Read()); + PrimType primType = (PrimType)Read(); PregIdx pidx = func->GetPregTab()->CreatePreg(primType); localPregTab.push_back(pidx); return pidx; @@ -116,7 +116,7 @@ LabelIdx BinaryMplImport::ImportLabel(MIRFunction *func) { } if (tag < 0) { CHECK_FATAL(static_cast(-tag) < localLabelTab.size(), "index out of bounds"); - return localLabelTab.at(static_cast(-tag)); + return localLabelTab.at(-tag); } CHECK_FATAL(tag == kBinLabel, "kBinLabel expected in ImportLabel()"); @@ -266,8 +266,8 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { case OP_floor: case OP_trunc: { TypeCvtNode *typecvtNode = mod.CurFuncCodeMemPool()->New(op, typ); - typecvtNode->SetFromType(static_cast(Read())); - typecvtNode->SetOpnd(ImportExpression(func), kFirstOpnd); + typecvtNode->SetFromType((PrimType)Read()); + typecvtNode->SetOpnd(ImportExpression(func), 0); return typecvtNode; } case OP_retype: { @@ -306,10 +306,10 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { } case OP_depositbits: { DepositbitsNode *dbNode = mod.CurFuncCodeMemPool()->New(op, typ); - dbNode->SetBitsOffset(static_cast(ReadNum())); - dbNode->SetBitsSize(static_cast(ReadNum())); - dbNode->SetOpnd(ImportExpression(func), kFirstOpnd); - dbNode->SetOpnd(ImportExpression(func), kSecondOpnd); + dbNode->SetBitsOffset(ReadNum()); + dbNode->SetBitsSize(ReadNum()); + dbNode->SetOpnd(ImportExpression(func), 0); + dbNode->SetOpnd(ImportExpression(func), 1); return dbNode; } case OP_gcmallocjarray: @@ -352,9 +352,9 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { case OP_cmpl: case OP_cmp: { CompareNode *cmpNode = mod.CurFuncCodeMemPool()->New(op, typ); - cmpNode->SetOpndType(static_cast(Read())); - cmpNode->SetOpnd(ImportExpression(func), kFirstOpnd); - cmpNode->SetOpnd(ImportExpression(func), kSecondOpnd); + cmpNode->SetOpndType((PrimType)Read()); + cmpNode->SetOpnd(ImportExpression(func), 0); + cmpNode->SetOpnd(ImportExpression(func), 1); return cmpNode; } case OP_resolveinterfacefunc: @@ -526,7 +526,7 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { case OP_iassignspoff: case OP_iassignfpoff: { IassignFPoffNode *s = func->GetCodeMemPool()->New(op); - s->SetPrimType(static_cast(Read())); + s->SetPrimType((PrimType)Read()); s->SetOffset(static_cast(ReadNum())); s->SetOpnd(ImportExpression(func), kFirstOpnd); stmt = s; diff --git a/src/mapleall/maple_ir/src/bin_mpl_import.cpp b/src/mapleall/maple_ir/src/bin_mpl_import.cpp index ddd38f6014..cc7bd4a2c1 100644 --- a/src/mapleall/maple_ir/src/bin_mpl_import.cpp +++ b/src/mapleall/maple_ir/src/bin_mpl_import.cpp @@ -543,7 +543,7 @@ TyIdx BinaryMplImport::ImportType(bool forPointedType) { CHECK_FATAL(static_cast(-tag) < typTab.size(), "index out of bounds"); return typTab.at(static_cast(-tag)); } - PrimType primType = static_cast(0); + PrimType primType = (PrimType)0; GStrIdx strIdx(0); bool nameIsLocal = false; ImportTypeBase(primType, strIdx, nameIsLocal); @@ -719,7 +719,7 @@ TyIdx BinaryMplImport::ImportTypeNonJava() { CHECK_FATAL(static_cast(-tag) < typTab.size(), "index out of bounds"); return typTab[static_cast(-tag)]; } - PrimType primType = static_cast(0); + PrimType primType = (PrimType)0; GStrIdx strIdx(0); bool nameIsLocal = false; ImportTypeBase(primType, strIdx, nameIsLocal); diff --git a/src/mapleall/maple_ir/src/mir_lower.cpp b/src/mapleall/maple_ir/src/mir_lower.cpp index ce085e6d1a..ddb4827535 100644 --- a/src/mapleall/maple_ir/src/mir_lower.cpp +++ b/src/mapleall/maple_ir/src/mir_lower.cpp @@ -554,7 +554,7 @@ BlockNode *MIRLower::LowerBlock(BlockNode &block) { CHECK_FATAL(funcType != nullptr, "MIRLower::LowerBlock: cannot find prototype for icall"); ic->SetRetTyIdx(funcType->GetTypeIndex()); MIRType *retType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(funcType->GetRetTyIdx()); - if (retType->GetPrimType() == PTY_agg && retType->GetSize() > k16BitSize) { + if (retType->GetPrimType() == PTY_agg && retType->GetSize() > 16) { funcType->funcAttrs.SetAttr(FUNCATTR_firstarg_return); } } @@ -1093,14 +1093,14 @@ MIRFuncType *MIRLower::FuncTypeFromFuncPtrExpr(BaseNode *x) { res = static_cast(mirType)->GetPointedFuncType(); } if (res == nullptr) { - res = FuncTypeFromFuncPtrExpr(x->Opnd(kNodeFirstOpnd)); + res = FuncTypeFromFuncPtrExpr(x->Opnd(0)); } break; } case OP_select: { - res = FuncTypeFromFuncPtrExpr(x->Opnd(kNodeSecondOpnd)); + res = FuncTypeFromFuncPtrExpr(x->Opnd(1)); if (res == nullptr) { - res = FuncTypeFromFuncPtrExpr(x->Opnd(kNodeThirdOpnd)); + res = FuncTypeFromFuncPtrExpr(x->Opnd(2)); } break; } diff --git a/src/mapleall/maple_me/src/irmap_build.cpp b/src/mapleall/maple_me/src/irmap_build.cpp index 6fd82f8500..bebf1facb0 100755 --- a/src/mapleall/maple_me/src/irmap_build.cpp +++ b/src/mapleall/maple_me/src/irmap_build.cpp @@ -808,8 +808,7 @@ MeStmt *IRMapBuild::BuildCallMeStmt(StmtNode &stmt, AccessSSANodes &ssaPart) { MeStmt *IRMapBuild::BuildNaryMeStmt(StmtNode &stmt, AccessSSANodes &ssaPart) { Opcode op = stmt.GetOpCode(); - NaryMeStmt *naryMeStmt = (op == OP_icall || op == OP_icallassigned || - op == OP_icallproto || op == OP_icallprotoassigned) + NaryMeStmt *naryMeStmt = (op == OP_icall || op == OP_icallassigned || op == OP_icallproto || op == OP_icallprotoassigned) ? static_cast(irMap->NewInPool(&stmt)) : static_cast(irMap->NewInPool(&stmt)); auto &naryStmtNode = static_cast(stmt); diff --git a/src/mapleall/maple_me/src/irmap_emit.cpp b/src/mapleall/maple_me/src/irmap_emit.cpp index 9cab595c5d..d6ca21e189 100755 --- a/src/mapleall/maple_me/src/irmap_emit.cpp +++ b/src/mapleall/maple_me/src/irmap_emit.cpp @@ -412,8 +412,7 @@ MIRFunction &CallMeStmt::GetTargetFunction() { } StmtNode &CallMeStmt::EmitStmt(SSATab &ssaTab) { - if (GetOp() != OP_icall && GetOp() != OP_icallassigned && - GetOp() != OP_icallproto && GetOp() != OP_icallprotoassigned) { + if (GetOp() != OP_icall && GetOp() != OP_icallassigned && GetOp() != OP_icallproto && GetOp() != OP_icallprotoassigned) { auto *callNode = ssaTab.GetModule().CurFunction()->GetCodeMempool()->New(ssaTab.GetModule(), Opcode(GetOp())); callNode->SetPUIdx(puIdx); diff --git a/src/mapleall/maple_me/src/me_phase_manager.cpp b/src/mapleall/maple_me/src/me_phase_manager.cpp index eef57b0aeb..a0b5419a8e 100644 --- a/src/mapleall/maple_me/src/me_phase_manager.cpp +++ b/src/mapleall/maple_me/src/me_phase_manager.cpp @@ -160,7 +160,7 @@ bool MeFuncPM::PhaseRun(maple::MIRModule &m) { func->SetFrameSize(localMemLayout.StackFrameSize()); memPoolCtrler.DeleteMemPool(layoutMp); } - globalMemLayout.seg_GPbased.size = maplebe::RoundUp(static_cast(globalMemLayout.seg_GPbased.size), GetPrimTypeSize(PTY_ptr)); + globalMemLayout.seg_GPbased.size = maplebe::RoundUp(globalMemLayout.seg_GPbased.size, GetPrimTypeSize(PTY_ptr)); m.SetGlobalMemSize(globalMemLayout.seg_GPbased.size); // output .lmbc BinaryMplt binMplt(m); -- Gitee From 61119a5f8e3e2462ad5679c24384a13701cd7c9f Mon Sep 17 00:00:00 2001 From: William Chen Date: Thu, 9 Jun 2022 15:13:55 -0700 Subject: [PATCH 046/179] Enhance ebo for extension to and 0xff 0xffff optimization --- .../maple_be/include/cg/aarch64/aarch64_ebo.h | 3 +- .../maple_be/src/cg/aarch64/aarch64_ebo.cpp | 62 +++++++++++++------ 2 files changed, 44 insertions(+), 21 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h index dc05b9c5f7..c6d5622597 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h @@ -83,7 +83,8 @@ class AArch64Ebo : public Ebo { bool SimplifyBothConst(BB &bb, Insn &insn, const ImmOperand &immOperand0, const ImmOperand &immOperand1, uint32 opndSize) const; AArch64CC_t GetReverseCond(const CondOperand &cond) const; - bool CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp) const; + bool CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp); + bool CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp, int64 immVal); }; } /* namespace maplebe */ diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp index 2c46f73631..7d298882ab 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp @@ -1058,6 +1058,38 @@ bool AArch64Ebo::CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi return false; } +bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp, int64 immVal) { + if (opndInfo.insn == nullptr) { + return false; + } + if (!cgFunc->GetMirModule().IsCModule()) { + return false; + } + Insn *prevInsn = opndInfo.insn; + InsnInfo *insnInfo = opndInfo.insnInfo; + if (insnInfo == nullptr) { + return false; + } + CHECK_NULL_FATAL(insnInfo); + MOperator opc1 = prevInsn->GetMachineOpcode(); + if (!isFp && + (((immVal == 0xff) && + (opc1 >= MOP_xsxtb32) && (opc1 <= MOP_xuxtw64)) || + ((immVal == 0xffff) && + (opc1 == MOP_xsxth32 || opc1 == MOP_xsxth64 || opc1 == MOP_xsxtw64 || + opc1 == MOP_xsxth32 || opc1 == MOP_xsxtw64)))) { + /* don't use register if it was redefined. */ + OpndInfo *opndInfo1 = insnInfo->origOpnd[kInsnSecondOpnd]; + if ((opndInfo1 != nullptr) && opndInfo1->redefined) { + return false; + } + Operand &opnd1 = prevInsn->GetOperand(kInsnSecondOpnd); + insn.SetOperand(kInsnSecondOpnd, opnd1); + return true; + } + return false; +} + /* Do some special pattern */ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origInfos) { MOperator opCode = insn.GetMachineOpcode(); @@ -1104,10 +1136,12 @@ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origI * ===> ldrb x1, [] ===> ldrb x1, [] ===> ldrsb x1, [] ===> no change * mov x1, x1 mov x1, x1 mov x1, x1 */ - case MOP_wandrri12: { + case MOP_wandrri12: + case MOP_xandrri13: { + bool is64Bits = (opCode == MOP_xandrri13); bool doAndOpt = false; if (static_cast(insn.GetOperand(kInsnThirdOpnd)).GetValue() == 0xff) { - doAndOpt = CombineExtensionAndLoad(&insn, origInfos, AND, false); + doAndOpt = CombineExtensionAndLoad(&insn, origInfos, AND, is64Bits); } if (doAndOpt) { return doAndOpt; @@ -1122,29 +1156,17 @@ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origI (static_cast(immValue) & (static_cast(immValue) + 1)) == 0) { /* immValue is (1 << n - 1) */ OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); - return CombineLsrAnd(insn, *opndInfo, false, false); - } - break; - } - case MOP_xandrri13: { - bool doAndOpt = false; - if (static_cast(insn.GetOperand(kInsnThirdOpnd)).GetValue() == 0xff) { - doAndOpt = CombineExtensionAndLoad(&insn, origInfos, AND, true); - } - if (doAndOpt) { - return doAndOpt; + return CombineLsrAnd(insn, *opndInfo, is64Bits, false); } /* - * lsr d0, d1, #6 - * and d0, d0, #1 - * ===> ubfx d0, d1, #6, #1 + * extension dest, src0 + * and dest, dest, 0xff or 0xffff + * ===> if extension is >= imm then can eliminate extension */ - int64 immValue = static_cast(insn.GetOperand(kInsnThirdOpnd)).GetValue(); - if (!beforeRegAlloc && immValue != 0 && + if (beforeRegAlloc && immValue != 0 && (static_cast(immValue) & (static_cast(immValue) + 1)) == 0) { - /* immValue is (1 << n - 1) */ OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); - return CombineLsrAnd(insn, *opndInfo, true, false); + return CombineExtAnd(insn, *opndInfo, is64Bits, false, immValue); } break; } -- Gitee From caa1ffc8b54ad9ed34b33fba36d9fea7780c67aa Mon Sep 17 00:00:00 2001 From: William Chen Date: Thu, 9 Jun 2022 16:33:38 -0700 Subject: [PATCH 047/179] Enhance ebo for back to back and optimization --- .../maple_be/src/cg/aarch64/aarch64_ebo.cpp | 44 ++++++++++++------- 1 file changed, 29 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp index 7d298882ab..dd216e9c54 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp @@ -1058,11 +1058,17 @@ bool AArch64Ebo::CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi return false; } +/* + * extension dest, src0 + * and dest, dest, 0xff or 0xffff + * ===> if extension is >= imm then can eliminate extension + * + * and dst1, src0, imm1 + * and dst2, dst1, imm2 where imm2 is 0xff or 0xffff + * ===> and dst2, src0, imm1 if imm1 <= imm2 + */ bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp, int64 immVal) { - if (opndInfo.insn == nullptr) { - return false; - } - if (!cgFunc->GetMirModule().IsCModule()) { + if (isFp || opndInfo.insn == nullptr || !cgFunc->GetMirModule().IsCModule()) { return false; } Insn *prevInsn = opndInfo.insn; @@ -1072,12 +1078,11 @@ bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi } CHECK_NULL_FATAL(insnInfo); MOperator opc1 = prevInsn->GetMachineOpcode(); - if (!isFp && - (((immVal == 0xff) && - (opc1 >= MOP_xsxtb32) && (opc1 <= MOP_xuxtw64)) || - ((immVal == 0xffff) && - (opc1 == MOP_xsxth32 || opc1 == MOP_xsxth64 || opc1 == MOP_xsxtw64 || - opc1 == MOP_xsxth32 || opc1 == MOP_xsxtw64)))) { + if (((immVal == 0xff) && + (opc1 >= MOP_xsxtb32) && (opc1 <= MOP_xuxtw64)) || + ((immVal == 0xffff) && + (opc1 == MOP_xsxth32 || opc1 == MOP_xsxth64 || opc1 == MOP_xsxtw64 || + opc1 == MOP_xsxth32 || opc1 == MOP_xsxtw64))) { /* don't use register if it was redefined. */ OpndInfo *opndInfo1 = insnInfo->origOpnd[kInsnSecondOpnd]; if ((opndInfo1 != nullptr) && opndInfo1->redefined) { @@ -1087,6 +1092,20 @@ bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi insn.SetOperand(kInsnSecondOpnd, opnd1); return true; } + if ((immVal == 0xff || immVal == 0xffff) && (opc1 == MOP_wandrri12 || opc1 == MOP_xandrri13)) { + OpndInfo *opndInfo1 = insnInfo->origOpnd[kInsnSecondOpnd]; + if ((opndInfo1 != nullptr) && opndInfo1->redefined) { + return false; + } + int64 prevImmVal = static_cast(prevInsn->GetOperand(kInsnThirdOpnd)).GetValue(); + if (prevImmVal > immVal) { + return false; + } + Operand &opnd1 = prevInsn->GetOperand(kInsnSecondOpnd); + insn.SetOperand(kInsnSecondOpnd, opnd1); + Operand &opnd2 = prevInsn->GetOperand(kInsnThirdOpnd); + insn.SetOperand(kInsnThirdOpnd, opnd2); + } return false; } @@ -1158,11 +1177,6 @@ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origI OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); return CombineLsrAnd(insn, *opndInfo, is64Bits, false); } - /* - * extension dest, src0 - * and dest, dest, 0xff or 0xffff - * ===> if extension is >= imm then can eliminate extension - */ if (beforeRegAlloc && immValue != 0 && (static_cast(immValue) & (static_cast(immValue) + 1)) == 0) { OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); -- Gitee From 94aaf41bdac03785fa0d0ae86c74ea475fab1bab Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:15:50 -0700 Subject: [PATCH 048/179] Turn off rematerialization for lmbc --- .../src/cg/aarch64/aarch64_color_ra.cpp | 20 +++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp index e7f80e2a4b..04aa668e5f 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp @@ -455,14 +455,18 @@ void GraphColorRegAllocator::CalculatePriority(LiveRange &lr) const { auto *a64CGFunc = static_cast(cgFunc); CG *cg = a64CGFunc->GetCG(); - if (cg->GetRematLevel() >= rematConst && lr.IsRematerializable(*a64CGFunc, rematConst)) { - lr.SetRematLevel(rematConst); - } else if (cg->GetRematLevel() >= rematAddr && lr.IsRematerializable(*a64CGFunc, rematAddr)) { - lr.SetRematLevel(rematAddr); - } else if (cg->GetRematLevel() >= rematDreadLocal && lr.IsRematerializable(*a64CGFunc, rematDreadLocal)) { - lr.SetRematLevel(rematDreadLocal); - } else if (cg->GetRematLevel() >= rematDreadGlobal && lr.IsRematerializable(*a64CGFunc, rematDreadGlobal)) { - lr.SetRematLevel(rematDreadGlobal); + if (cgFunc->GetCG()->IsLmbc()) { + lr.SetRematLevel(rematOff); + } else { + if (cg->GetRematLevel() >= rematConst && lr.IsRematerializable(*a64CGFunc, rematConst)) { + lr.SetRematLevel(rematConst); + } else if (cg->GetRematLevel() >= rematAddr && lr.IsRematerializable(*a64CGFunc, rematAddr)) { + lr.SetRematLevel(rematAddr); + } else if (cg->GetRematLevel() >= rematDreadLocal && lr.IsRematerializable(*a64CGFunc, rematDreadLocal)) { + lr.SetRematLevel(rematDreadLocal); + } else if (cg->GetRematLevel() >= rematDreadGlobal && lr.IsRematerializable(*a64CGFunc, rematDreadGlobal)) { + lr.SetRematLevel(rematDreadGlobal); + } } auto calculatePriorityFunc = [&lr, &bbNum, &numDefs, &numUses, &pri, this] (uint32 bbID) { -- Gitee From 3b93a146260d57a8e5562d3f574c5f9a0064fbe9 Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:16:12 -0700 Subject: [PATCH 049/179] Turn on globalopt for lmbc, but leave SSA opt off --- .../include/cg/aarch64/aarch64_phases.def | 12 ++++-------- src/mapleall/maple_be/include/cg/reaching.h | 1 + .../maple_be/src/cg/aarch64/aarch64_global.cpp | 4 +++- .../src/cg/aarch64/aarch64_reaching.cpp | 18 ++++++++++++++++++ src/mapleall/maple_be/src/cg/reaching.cpp | 10 +++++----- 5 files changed, 31 insertions(+), 14 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index ff08e81852..5595b17c0c 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -36,10 +36,8 @@ ADDTARGETPHASE("ico", CGOptions::DoICO()) ADDTARGETPHASE("cfgo", !GetMIRModule()->IsCModule() && CGOptions::DoCFGO()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); - ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); - } + ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); + ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); ADDTARGETPHASE("clearrdinfo", (CGOptions::DoStoreLoadOpt()) || CGOptions::DoGlobalOpt()); ADDTARGETPHASE("prepeephole1", CGOptions::DoPrePeephole()); @@ -49,10 +47,8 @@ ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); - } + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/include/cg/reaching.h b/src/mapleall/maple_be/include/cg/reaching.h index 55b4b666fe..13872a9122 100644 --- a/src/mapleall/maple_be/include/cg/reaching.h +++ b/src/mapleall/maple_be/include/cg/reaching.h @@ -146,6 +146,7 @@ class ReachingDefinition : public AnalysisResult { std::vector memIn; std::vector memOut; const uint32 kMaxBBNum; + uint32 stackSize = 0; private: void Initialize(); void InitDataSize(); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 4a2f257321..6b5d902cb4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,7 +412,9 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - CHECK_FATAL(false, "check case in ssa"); + if (cgFunc.GetCG()->IsLmbc() == false) { + CHECK_FATAL(false, "check case in ssa"); + } } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp index 2176568333..dc5f214b8e 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp @@ -464,6 +464,9 @@ std::vector AArch64ReachingDefinition::FindMemDefBetweenInsn( ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffset < 0) { + memOffset = stackSize - memOffset; + } if ((offset == memOffset) || (insn->IsStorePair() && offset == memOffset + GetEachMemSizeOfPair(insn->GetMachineOpcode()))) { defInsnVec.emplace_back(insn); @@ -516,6 +519,9 @@ void AArch64ReachingDefinition::FindMemDefInBB(uint32 offset, BB &bb, InsnSet &d ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffset < 0) { + memOffset = stackSize - memOffset; + } if (offset == memOffset) { (void)defInsnSet.insert(insn); break; @@ -1001,6 +1007,9 @@ bool AArch64ReachingDefinition::FindMemUseBetweenInsn(uint32 offset, Insn *start ASSERT(memOpnd.GetIndexRegister() == nullptr, "offset must not be Register for frame MemOperand"); ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetValue(); + if (memOffset < 0) { + memOffset = stackSize - memOffset; + } if (insn->IsStore() || insn->IsPseudoInstruction()) { if (memOffset == offset) { @@ -1050,6 +1059,9 @@ InsnSet AArch64ReachingDefinition::FindDefForMemOpnd(Insn &insn, uint32 indexOrO } ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffSet < 0) { + memOffSet = stackSize - memOffSet; + } } else { memOffSet = indexOrOffset; } @@ -1101,6 +1113,9 @@ InsnSet AArch64ReachingDefinition::FindUseForMemOpnd(Insn &insn, uint8 index, bo ASSERT(memOpnd.GetIndexRegister() == nullptr, "IndexRegister no nullptr"); ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffSet < 0) { + memOffSet = stackSize - memOffSet; + } if (secondMem) { ASSERT(insn.IsStorePair(), "second MemOperand can only be defined in stp insn"); memOffSet += GetEachMemSizeOfPair(insn.GetMachineOpcode()); @@ -1214,6 +1229,9 @@ void AArch64ReachingDefinition::InitInfoForMemOperand(Insn &insn, Operand &opnd, CHECK_FATAL(index == nullptr, "Existing [x29 + index] Memory Address"); ASSERT(memOpnd.GetOffsetImmediate(), "offset must be a immediate value"); int64 offsetVal = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (offsetVal < 0) { + offsetVal = stackSize - offsetVal; + } if ((offsetVal % kMemZoomSize) != 0) { SetAnalysisMode(kRDRegAnalysis); } diff --git a/src/mapleall/maple_be/src/cg/reaching.cpp b/src/mapleall/maple_be/src/cg/reaching.cpp index 72c6fa87e3..b7d95caf59 100644 --- a/src/mapleall/maple_be/src/cg/reaching.cpp +++ b/src/mapleall/maple_be/src/cg/reaching.cpp @@ -546,11 +546,10 @@ void ReachingDefinition::InitRegAndMemInfo(const BB &bb) { } if (mode & kRDMemAnalysis) { - const int32 kStackSize = GetStackSize(); - memGen[bb.GetId()] = new DataInfo((kStackSize / kMemZoomSize), rdAlloc); - memUse[bb.GetId()] = new DataInfo((kStackSize / kMemZoomSize), rdAlloc); - memIn[bb.GetId()] = new DataInfo((kStackSize / kMemZoomSize), rdAlloc); - memOut[bb.GetId()] = new DataInfo((kStackSize / kMemZoomSize), rdAlloc); + memGen[bb.GetId()] = new DataInfo((stackSize / kMemZoomSize), rdAlloc); + memUse[bb.GetId()] = new DataInfo((stackSize / kMemZoomSize), rdAlloc); + memIn[bb.GetId()] = new DataInfo((stackSize / kMemZoomSize), rdAlloc); + memOut[bb.GetId()] = new DataInfo((stackSize / kMemZoomSize), rdAlloc); } } @@ -778,6 +777,7 @@ void ReachingDefinition::AnalysisStart() { if (!cgFunc->GetFirstBB()) { return; } + stackSize = GetStackSize(); Initialize(); /* Build in/out for function body first. (Except cleanup bb) */ BuildInOutForFuncBody(); -- Gitee From 78c6860bb0ef6f05747539064a223ef93ba3e1b0 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Fri, 10 Jun 2022 17:56:05 -0700 Subject: [PATCH 050/179] delete obsolete code in SelectAggIassign() where small struct returned in regs was represented in an iassign --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 130 ------------------ 1 file changed, 130 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 3ba48a2cbc..c2f1a470e3 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -2286,15 +2286,6 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) { uint32 lhsOffset = 0; MIRType *stmtType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(stmt.GetTyIdx()); MIRPtrType *lhsPointerType = static_cast(stmtType); - bool loadToRegs4StructReturn = false; - if (mirModule.CurFunction()->StructReturnedInRegs()) { - MIRSymbol *retSt = mirModule.CurFunction()->GetFormal(0); - if (stmt.Opnd(0)->GetOpCode() == OP_dread) { - DreadNode *dread = static_cast(stmt.Opnd(0)); - MIRSymbol *addrSym = mirModule.CurFunction()->GetLocalOrGlobalSymbol(dread->GetStIdx()); - loadToRegs4StructReturn = (retSt == addrSym); - } - } MIRType *lhsType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(lhsPointerType->GetPointedTyIdx()); if (stmt.GetFieldID() != 0) { MIRStructType *structType = static_cast(lhsType); @@ -2338,91 +2329,6 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) { rhsType = structType->GetFieldType(rhsDread->GetFieldID()); rhsOffset = static_cast(GetBecommon().GetFieldOffset(*structType, rhsDread->GetFieldID()).first); } - if (loadToRegs4StructReturn) { - /* generate move to regs for agg return */ - CHECK_FATAL(lhsSize <= k16ByteSize, "SelectAggIassign: illegal struct size"); - AArch64CallConvImpl parmlocator(GetBecommon()); - CCLocInfo pLoc; - parmlocator.LocateNextParm(*lhsType, pLoc, true, GetBecommon().GetMIRModule().CurFunction()); - /* aggregates are 8 byte aligned. */ - Operand *rhsmemopnd = nullptr; - RegOperand *result[kFourRegister]; /* up to 2 int or 4 fp */ - uint32 loadSize; - uint32 numRegs; - RegType regType; - PrimType retPty; - bool fpParm = false; - if (pLoc.numFpPureRegs) { - loadSize = pLoc.fpSize; - numRegs = pLoc.numFpPureRegs; - fpParm = true; - regType = kRegTyFloat; - retPty = (pLoc.fpSize == k4ByteSize) ? PTY_f32 : PTY_f64; - } else { - if (CGOptions::IsBigEndian()) { - loadSize = k8ByteSize; - numRegs = (lhsSize <= k8ByteSize) ? kOneRegister : kTwoRegister; - regType = kRegTyInt; - retPty = PTY_u64; - } else { - loadSize = (lhsSize <= k4ByteSize) ? k4ByteSize : k8ByteSize; - numRegs = (lhsSize <= k8ByteSize) ? kOneRegister : kTwoRegister; - regType = kRegTyInt; - retPty = PTY_u32; - } - } - bool parmCopy = IsParamStructCopy(*rhsSymbol); - for (uint32 i = 0; i < numRegs; i++) { - if (parmCopy) { - rhsmemopnd = &LoadStructCopyBase(*rhsSymbol, - (rhsOffset + static_cast(i * (fpParm ? loadSize : k8ByteSize))), - static_cast(loadSize * kBitsPerByte)); - } else { - rhsmemopnd = &GetOrCreateMemOpnd(*rhsSymbol, - (rhsOffset + static_cast(i * (fpParm ? loadSize : k8ByteSize))), - (loadSize * kBitsPerByte)); - } - result[i] = &CreateVirtualRegisterOperand(NewVReg(regType, loadSize)); - MOperator mop1 = PickLdInsn(loadSize * kBitsPerByte, retPty); - Insn &ld = GetCG()->BuildInstruction(mop1, *(result[i]), *rhsmemopnd); - GetCurBB()->AppendInsn(ld); - } - AArch64reg regs[kFourRegister]; - regs[kFirstReg] = static_cast(pLoc.reg0); - regs[kSecondReg] = static_cast(pLoc.reg1); - regs[kThirdReg] = static_cast(pLoc.reg2); - regs[kFourthReg] = static_cast(pLoc.reg3); - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg; - MOperator mop2; - if (fpParm) { - preg = regs[i]; - mop2 = (loadSize == k4ByteSize) ? MOP_xvmovs : MOP_xvmovd; - } else { - preg = (i == 0 ? R0 : R1); - mop2 = (loadSize == k4ByteSize) ? MOP_wmovrr : MOP_xmovrr; - } - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, (loadSize * kBitsPerByte), regType); - Insn &mov = GetCG()->BuildInstruction(mop2, dest, *(result[i])); - GetCurBB()->AppendInsn(mov); - } - /* Create artificial dependency to extend the live range */ - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg; - MOperator mop3; - if (fpParm) { - preg = regs[i]; - mop3 = MOP_pseudo_ret_float; - } else { - preg = (i == 0 ? R0 : R1); - mop3 = MOP_pseudo_ret_int; - } - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, loadSize * kBitsPerByte, regType); - Insn &pseudo = GetCG()->BuildInstruction(mop3, dest); - GetCurBB()->AppendInsn(pseudo); - } - return; - } rhsAlign = GetBecommon().GetTypeAlign(rhsType->GetTypeIndex()); alignUsed = std::min(lhsAlign, rhsAlign); ASSERT(alignUsed != 0, "expect non-zero"); @@ -2538,42 +2444,6 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) { rhsOffset = static_cast(GetBecommon().GetFieldOffset(*rhsStructType, rhsIread->GetFieldID()).first); isRefField = GetBecommon().IsRefField(*rhsStructType, rhsIread->GetFieldID()); } - if (loadToRegs4StructReturn) { - /* generate move to regs. */ - CHECK_FATAL(lhsSize <= k16ByteSize, "SelectAggIassign: illegal struct size"); - RegOperand *result[kTwoRegister]; /* maximum 16 bytes, 2 registers */ - uint32 loadSize; - if (CGOptions::IsBigEndian()) { - loadSize = k8ByteSize; - } else { - loadSize = (lhsSize <= k4ByteSize) ? k4ByteSize : k8ByteSize; - } - uint32 numRegs = (lhsSize <= k8ByteSize) ? kOneRegister : kTwoRegister; - for (uint32 i = 0; i < numRegs; i++) { - OfstOperand *rhsOffOpnd = &GetOrCreateOfstOpnd(rhsOffset + i * loadSize, loadSize * kBitsPerByte); - Operand &rhsmemopnd = GetOrCreateMemOpnd(MemOperand::kAddrModeBOi, loadSize * kBitsPerByte, - rhsAddrOpnd, nullptr, rhsOffOpnd, nullptr); - result[i] = &CreateVirtualRegisterOperand(NewVReg(kRegTyInt, loadSize)); - MOperator mop1 = PickLdInsn(loadSize * kBitsPerByte, PTY_u32); - Insn &ld = GetCG()->BuildInstruction(mop1, *(result[i]), rhsmemopnd); - ld.MarkAsAccessRefField(isRefField); - GetCurBB()->AppendInsn(ld); - } - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg = (i == 0 ? R0 : R1); - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, loadSize * kBitsPerByte, kRegTyInt); - Insn &mov = GetCG()->BuildInstruction(MOP_xmovrr, dest, *(result[i])); - GetCurBB()->AppendInsn(mov); - } - /* Create artificial dependency to extend the live range */ - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg = (i == 0 ? R0 : R1); - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, loadSize * kBitsPerByte, kRegTyInt); - Insn &pseudo = cg->BuildInstruction(MOP_pseudo_ret_int, dest); - GetCurBB()->AppendInsn(pseudo); - } - return; - } rhsAlign = GetBecommon().GetTypeAlign(rhsType->GetTypeIndex()); alignUsed = std::min(lhsAlign, rhsAlign); ASSERT(alignUsed != 0, "expect non-zero"); -- Gitee From 61ad6234685df3d9cb44e959891eeea3725bffc3 Mon Sep 17 00:00:00 2001 From: William Chen Date: Mon, 13 Jun 2022 14:06:17 -0700 Subject: [PATCH 051/179] Do not optimize for ssa for physical regs. --- .../include/cg/aarch64/aarch64_phases.def | 22 +++++++++---------- .../src/cg/aarch64/aarch64_global.cpp | 4 +--- .../maple_be/src/cg/aarch64/aarch64_prop.cpp | 3 +++ 3 files changed, 14 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 5595b17c0c..531e7f0535 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,18 +17,16 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); - } + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 6b5d902cb4..4a2f257321 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,9 +412,7 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - if (cgFunc.GetCG()->IsLmbc() == false) { - CHECK_FATAL(false, "check case in ssa"); - } + CHECK_FATAL(false, "check case in ssa"); } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp index 6b45e3bdf6..52955cdd7d 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp @@ -1491,6 +1491,9 @@ bool ExtendMovPattern::CheckSrcReg(regno_t srcRegNo, uint32 validNum) { bool ExtendMovPattern::BitNotAffected(const Insn &insn, uint32 validNum) { RegOperand &firstOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); + if (firstOpnd.IsPhysicalRegister()) { + return false; + } RegOperand &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); regno_t desRegNo = firstOpnd.GetRegisterNumber(); regno_t srcRegNo = secondOpnd.GetRegisterNumber(); -- Gitee From 664302612db1fe7bccfcd35f4d262f4abe9d453c Mon Sep 17 00:00:00 2001 From: William Chen Date: Tue, 14 Jun 2022 09:21:24 -0700 Subject: [PATCH 052/179] Fix globalopt bug of negative offset with lmbc --- .../maple_be/src/cg/aarch64/aarch64_reaching.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp index dc5f214b8e..55b6059fd3 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp @@ -465,7 +465,7 @@ std::vector AArch64ReachingDefinition::FindMemDefBetweenInsn( ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffset < 0) { - memOffset = stackSize - memOffset; + memOffset = stackSize + memOffset; } if ((offset == memOffset) || (insn->IsStorePair() && offset == memOffset + GetEachMemSizeOfPair(insn->GetMachineOpcode()))) { @@ -520,7 +520,7 @@ void AArch64ReachingDefinition::FindMemDefInBB(uint32 offset, BB &bb, InsnSet &d ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffset < 0) { - memOffset = stackSize - memOffset; + memOffset = stackSize + memOffset; } if (offset == memOffset) { (void)defInsnSet.insert(insn); @@ -1008,7 +1008,7 @@ bool AArch64ReachingDefinition::FindMemUseBetweenInsn(uint32 offset, Insn *start ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetValue(); if (memOffset < 0) { - memOffset = stackSize - memOffset; + memOffset = stackSize + memOffset; } if (insn->IsStore() || insn->IsPseudoInstruction()) { @@ -1060,7 +1060,7 @@ InsnSet AArch64ReachingDefinition::FindDefForMemOpnd(Insn &insn, uint32 indexOrO ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffSet < 0) { - memOffSet = stackSize - memOffSet; + memOffSet = stackSize + memOffSet; } } else { memOffSet = indexOrOffset; @@ -1114,7 +1114,7 @@ InsnSet AArch64ReachingDefinition::FindUseForMemOpnd(Insn &insn, uint8 index, bo ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffSet < 0) { - memOffSet = stackSize - memOffSet; + memOffSet = stackSize + memOffSet; } if (secondMem) { ASSERT(insn.IsStorePair(), "second MemOperand can only be defined in stp insn"); @@ -1230,7 +1230,7 @@ void AArch64ReachingDefinition::InitInfoForMemOperand(Insn &insn, Operand &opnd, ASSERT(memOpnd.GetOffsetImmediate(), "offset must be a immediate value"); int64 offsetVal = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (offsetVal < 0) { - offsetVal = stackSize - offsetVal; + offsetVal = stackSize + offsetVal; } if ((offsetVal % kMemZoomSize) != 0) { SetAnalysisMode(kRDRegAnalysis); -- Gitee From 813aecc816fdbb68f4696369488b7b2b2005c928 Mon Sep 17 00:00:00 2001 From: William Chen Date: Tue, 14 Jun 2022 15:55:34 -0700 Subject: [PATCH 053/179] Merge return bb for small C functions --- src/mapleall/maple_be/include/cg/cgfunc.h | 1 + src/mapleall/maple_be/src/cg/cgbb.cpp | 1 + src/mapleall/maple_be/src/cg/cgfunc.cpp | 3 ++- 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/include/cg/cgfunc.h b/src/mapleall/maple_be/include/cg/cgfunc.h index 50e134552e..0a29d3b5a8 100644 --- a/src/mapleall/maple_be/include/cg/cgfunc.h +++ b/src/mapleall/maple_be/include/cg/cgfunc.h @@ -81,6 +81,7 @@ class SpillMemOperandSet { class LiveRange; #endif /* TARGARM32 */ constexpr uint32 kVRegisterNumber = 80; +constexpr uint32 kNumBBOptReturn = 30; class CGFunc { public: enum ShiftDirection : uint8 { diff --git a/src/mapleall/maple_be/src/cg/cgbb.cpp b/src/mapleall/maple_be/src/cg/cgbb.cpp index e1c1a8642b..d0f319df0b 100644 --- a/src/mapleall/maple_be/src/cg/cgbb.cpp +++ b/src/mapleall/maple_be/src/cg/cgbb.cpp @@ -525,6 +525,7 @@ void Bfs::ComputeBlockOrder() { done = true; } else { LogInfo::MapleLogger() << "Error: RA BFS loop " << sortedCnt << " in func " << cgfunc->GetName() << "\n"; + CHECK_FATAL(false, ""); } } sortedCnt = sortedBBs.size(); diff --git a/src/mapleall/maple_be/src/cg/cgfunc.cpp b/src/mapleall/maple_be/src/cg/cgfunc.cpp index d41db1288f..86368cbbc4 100644 --- a/src/mapleall/maple_be/src/cg/cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/cgfunc.cpp @@ -2032,7 +2032,8 @@ void CGFunc::HandleFunction() { /* select instruction */ GenerateInstruction(); /* merge multi return */ - if (!func.GetModule()->IsCModule() || CGOptions::DoRetMerge() || CGOptions::OptimizeForSize()) { + if (!func.GetModule()->IsCModule() || (func.GetModule()->IsCModule() && (NumBBs() < kNumBBOptReturn)) || + CGOptions::DoRetMerge() || CGOptions::OptimizeForSize()) { MergeReturn(); } if (func.IsJava()) { -- Gitee From ba3de7fd7387d654fa72830291db671fa468affe Mon Sep 17 00:00:00 2001 From: William Chen Date: Thu, 16 Jun 2022 10:53:55 -0700 Subject: [PATCH 054/179] Reorder back-to-back cond branch and uncond brach to loop head bb --- src/mapleall/maple_be/include/cg/cfgo.h | 24 +++++++++ src/mapleall/maple_be/include/cg/loop.h | 3 +- src/mapleall/maple_be/src/cg/cfgo.cpp | 65 ++++++++++++++++++++++++- src/mapleall/maple_be/src/cg/loop.cpp | 4 ++ 4 files changed, 93 insertions(+), 3 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/cfgo.h b/src/mapleall/maple_be/include/cg/cfgo.h index e7d6e07e14..2528f03413 100644 --- a/src/mapleall/maple_be/include/cg/cfgo.h +++ b/src/mapleall/maple_be/include/cg/cfgo.h @@ -18,6 +18,14 @@ #include "optimize_common.h" namespace maplebe { + +enum CfgoPhase : maple::uint8 { + CfgoDefault, + CfgoPreRegAlloc, + CfgoPostRegAlloc, + PostCfgo, +}; + class ChainingPattern : public OptimizationPattern { public: explicit ChainingPattern(CGFunc &func) : OptimizationPattern(func) { @@ -63,6 +71,14 @@ class FlipBRPattern : public OptimizationPattern { ~FlipBRPattern() override = default; bool Optimize(BB &curBB) override; + CfgoPhase GetPhase() const { + return phase; + } + void SetPhase(CfgoPhase val) { + phase = val; + } + CfgoPhase phase = CfgoDefault; + protected: void RelocateThrowBB(BB &curBB); }; @@ -120,6 +136,14 @@ class CFGOptimizer : public Optimizer { ~CFGOptimizer() override = default; void InitOptimizePatterns() override; + + CfgoPhase GetPhase() const { + return phase; + } + void SetPhase(CfgoPhase val) { + phase = val; + } + CfgoPhase phase = CfgoDefault; }; MAPLE_FUNC_PHASE_DECLARE_BEGIN(CgCfgo, maplebe::CGFunc) diff --git a/src/mapleall/maple_be/include/cg/loop.h b/src/mapleall/maple_be/include/cg/loop.h index 658ee83f04..eedf5bc02c 100644 --- a/src/mapleall/maple_be/include/cg/loop.h +++ b/src/mapleall/maple_be/include/cg/loop.h @@ -171,7 +171,8 @@ class CGFuncLoops { void CheckOverlappingInnerLoops(const MapleVector &iLoops, const MapleVector &loopMem) const; void CheckLoops() const; - void PrintLoops(const CGFuncLoops &funcLoop) const; + void PrintLoops(const CGFuncLoops &loops) const; + bool IsBBLoopMember(const BB *bb) const; const BB *GetHeader() const { return header; diff --git a/src/mapleall/maple_be/src/cg/cfgo.cpp b/src/mapleall/maple_be/src/cg/cfgo.cpp index 46822d45d2..4b89308ec5 100644 --- a/src/mapleall/maple_be/src/cg/cfgo.cpp +++ b/src/mapleall/maple_be/src/cg/cfgo.cpp @@ -42,7 +42,11 @@ void CFGOptimizer::InitOptimizePatterns() { diffPassPatterns.emplace_back(memPool->New(*cgFunc)); } diffPassPatterns.emplace_back(memPool->New(*cgFunc)); - diffPassPatterns.emplace_back(memPool->New(*cgFunc)); + FlipBRPattern *brOpt = memPool->New(*cgFunc); + if (GetPhase() == CfgoPostRegAlloc) { + brOpt->SetPhase(CfgoPostRegAlloc); + } + diffPassPatterns.emplace_back(brOpt); diffPassPatterns.emplace_back(memPool->New(*cgFunc)); diffPassPatterns.emplace_back(memPool->New(*cgFunc)); diffPassPatterns.emplace_back(memPool->New(*cgFunc)); @@ -547,7 +551,13 @@ void FlipBRPattern::RelocateThrowBB(BB &curBB) { * ftBB * targetBB * - * 2. relocate throw BB in RelocateThrowBB() + * loopHeaderBB: loopHeaderBB: + * ... ... + * cond_br loopExit: cond_br loopHeaderBB + * ftBB: ftBB: + * goto loopHeaderBB: goto loopExit + * + * 3. relocate throw BB in RelocateThrowBB() */ bool FlipBRPattern::Optimize(BB &curBB) { if (curBB.GetKind() == BB::kBBIf && !curBB.IsEmpty()) { @@ -647,6 +657,50 @@ bool FlipBRPattern::Optimize(BB &curBB) { ftBB->RemoveInsn(*brInsn); ftBB->SetKind(BB::kBBFallthru); } + } else if (GetPhase() == CfgoPostRegAlloc && ftBB->GetKind() == BB::kBBGoto && + curBB.GetLoop() != nullptr && curBB.GetLoop() == ftBB->GetLoop() && + ftBB->IsSoloGoto() && + ftBB->GetLoop()->GetHeader() == *(ftBB->GetSuccsBegin()) && + curBB.GetLoop()->IsBBLoopMember((curBB.GetSuccs().front() == ftBB) ? + curBB.GetSuccs().back() : curBB.GetSuccs().front()) == false) { + Insn *curBBBranchInsn = nullptr; + for (curBBBranchInsn = curBB.GetLastInsn(); curBBBranchInsn != nullptr; + curBBBranchInsn = curBBBranchInsn->GetPrev()) { + if (curBBBranchInsn->IsBranch()) { + break; + } + } + ASSERT(curBBBranchInsn != nullptr, "FlipBRPattern: curBB has no branch"); + Insn *brInsn = nullptr; + for (brInsn = ftBB->GetLastInsn(); brInsn != nullptr; brInsn = brInsn->GetPrev()) { + if (brInsn->IsGoto()) { + break; + } + } + ASSERT(brInsn != nullptr, "FlipBRPattern: ftBB has no branch"); + uint32 condTargetIdx = curBBBranchInsn->GetJumpTargetIdx(); + LabelOperand &condTarget = static_cast(curBBBranchInsn->GetOperand(condTargetIdx)); + MOperator mOp = curBBBranchInsn->FlipConditionOp(curBBBranchInsn->GetMachineOpcode(), condTargetIdx); + if (mOp == 0) { + return false; + } + uint32 gotoTargetIdx = brInsn->GetJumpTargetIdx(); + LabelOperand &gotoTarget = static_cast(brInsn->GetOperand(gotoTargetIdx)); + curBBBranchInsn->SetMOP(mOp); + curBBBranchInsn->SetOperand(condTargetIdx, gotoTarget); + brInsn->SetOperand(gotoTargetIdx, condTarget); + auto it = ftBB->GetSuccsBegin(); + BB *loopHeadBB = *it; + + curBB.RemoveSuccs(*brBB); + brBB->RemovePreds(curBB); + ftBB->RemoveSuccs(*loopHeadBB); + loopHeadBB->RemovePreds(*ftBB); + + curBB.PushBackSuccs(*loopHeadBB); + loopHeadBB->PushBackPreds(curBB); + ftBB->PushBackSuccs(*brBB); + brBB->PushBackPreds(*ftBB); } else { RelocateThrowBB(curBB); } @@ -847,6 +901,10 @@ bool DuplicateBBPattern::Optimize(BB &curBB) { /* === new pm === */ bool CgCfgo::PhaseRun(maplebe::CGFunc &f) { CFGOptimizer *cfgOptimizer = GetPhaseAllocator()->New(f, *GetPhaseMemPool()); + if (f.IsAfterRegAlloc()) { + (void)GetAnalysisInfoHook()->ForceRunAnalysisPhase, CGFunc>(&CgLoopAnalysis::id, f); + cfgOptimizer->SetPhase(CfgoPostRegAlloc); + } const std::string &funcClass = f.GetFunction().GetBaseClassName(); const std::string &funcName = f.GetFunction().GetBaseFuncName(); const std::string &name = funcClass + funcName; @@ -854,6 +912,9 @@ bool CgCfgo::PhaseRun(maplebe::CGFunc &f) { DotGenerator::GenerateDot("before-cfgo", f, f.GetMirModule()); } cfgOptimizer->Run(name); + if (f.IsAfterRegAlloc()) { + GetAnalysisInfoHook()->ForceEraseAnalysisPhase(f.GetUniqueID(), &CgLoopAnalysis::id); + } if (CFGO_DUMP_NEWPM) { DotGenerator::GenerateDot("after-cfgo", f, f.GetMirModule()); } diff --git a/src/mapleall/maple_be/src/cg/loop.cpp b/src/mapleall/maple_be/src/cg/loop.cpp index 9d50280dab..e78c1201ec 100644 --- a/src/mapleall/maple_be/src/cg/loop.cpp +++ b/src/mapleall/maple_be/src/cg/loop.cpp @@ -161,6 +161,10 @@ void CGFuncLoops::PrintLoops(const CGFuncLoops &funcLoop) const { } } +bool CGFuncLoops::IsBBLoopMember(const BB *bb) const { + return (*(std::find(loopMembers.begin(), loopMembers.end(), bb)) == bb); +} + // partial loop body found with formLoop is NOT really needed in down stream // It should be simplied later void LoopFinder::formLoop(BB* headBB, BB* backBB) { -- Gitee From c4ab3ada2a8f9d388af26fd036063868f7589eb1 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Mon, 20 Jun 2022 15:49:32 -0700 Subject: [PATCH 055/179] Updating to "new" lmbc --- .../include/cg/aarch64/aarch64_cgfunc.h | 14 +- src/mapleall/maple_be/include/cg/cgfunc.h | 4 +- .../src/cg/aarch64/aarch64_cgfunc.cpp | 127 ++++++++++++++++-- .../src/cg/aarch64/aarch64_memlayout.cpp | 24 +++- .../src/cg/aarch64/aarch64_proepilog.cpp | 35 ++++- 5 files changed, 178 insertions(+), 26 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index bf154e7657..be3a3bae62 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -104,6 +104,7 @@ class AArch64CGFunc : public CGFunc { MIRType *LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList) const; RegOperand &GetOrCreateResOperand(const BaseNode &parent, PrimType primType); + MIRStructType *GetLmbcStructArgType(BaseNode &stmt, int32 argNo); void IntrinsifyGetAndAddInt(ListOperand &srcOpnds, PrimType pty); void IntrinsifyGetAndSetInt(ListOperand &srcOpnds, PrimType pty); @@ -191,7 +192,8 @@ class AArch64CGFunc : public CGFunc { Operand *SelectIread(const BaseNode &parent, IreadNode &expr, int extraOffset = 0, PrimType finalBitFieldDestType = kPtyInvalid) override; Operand *SelectIreadoff(const BaseNode &parent, IreadoffNode &ireadoff) override; - Operand *SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff) override; + Operand *SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff /*, MIRType &ty, + ListOperand &srcOpnds, AArch64CallConvImpl &parmLocator */) override; Operand *SelectIntConst(MIRIntConst &intConst) override; Operand *HandleFmovImm(PrimType stype, int64 val, MIRConst &mirConst, const BaseNode &parent); Operand *SelectFloatConst(MIRFloatConst &floatConst, const BaseNode &parent) override; @@ -869,7 +871,7 @@ class AArch64CGFunc : public CGFunc { void SelectParmListDreadSmallAggregate(const MIRSymbol &sym, MIRType &structType, ListOperand &srcOpnds, int32 offset, AArch64CallConvImpl &parmLocator, FieldID fieldID); - void SelectParmListIreadSmallAggregate(const IreadNode &iread, MIRType &structType, ListOperand &srcOpnds, + void SelectParmListIreadSmallAggregate(BaseNode &iread, MIRType &structType, ListOperand &srcOpnds, int32 offset, AArch64CallConvImpl &parmLocator); void SelectParmListDreadLargeAggregate(const MIRSymbol &sym, MIRType &structType, ListOperand &srcOpnds, @@ -878,12 +880,12 @@ class AArch64CGFunc : public CGFunc { AArch64CallConvImpl &parmLocator, int32 &structCopyOffset, int32 fromOffset); void CreateCallStructMemcpyToParamReg(MIRType &structType, int32 structCopyOffset, AArch64CallConvImpl &parmLocator, ListOperand &srcOpnds); - void SelectParmListForAggregate(BaseNode &argExpr, ListOperand &srcOpnds, AArch64CallConvImpl &parmLocator, - int32 &structCopyOffset); + void SelectParmListForAggregate(BaseNode &parent, BaseNode &argExpr, ListOperand &srcOpnds, + AArch64CallConvImpl &parmLocator, int32 &structCopyOffset, int32 argNo); size_t SelectParmListGetStructReturnSize(StmtNode &naryNode); bool MarkParmListCall(BaseNode &expr); - void SelectParmListPreprocessLargeStruct(BaseNode &argExpr, int32 &structCopyOffset); - void SelectParmListPreprocess(const StmtNode &naryNode, size_t start, std::set &specialArgs); + void SelectParmListPreprocessLargeStruct(BaseNode &parent, BaseNode &argExpr, int32 &structCopyOffset, int32 argNo); + void SelectParmListPreprocess(StmtNode &naryNode, size_t start, std::set &specialArgs); void SelectParmList(StmtNode &naryNode, ListOperand &srcOpnds, bool isCallNative = false); Operand *SelectClearStackCallParam(const AddrofNode &expr, int64 &offsetValue); void SelectClearStackCallParmList(const StmtNode &naryNode, ListOperand &srcOpnds, diff --git a/src/mapleall/maple_be/include/cg/cgfunc.h b/src/mapleall/maple_be/include/cg/cgfunc.h index 0a29d3b5a8..21e5e938ea 100644 --- a/src/mapleall/maple_be/include/cg/cgfunc.h +++ b/src/mapleall/maple_be/include/cg/cgfunc.h @@ -1150,8 +1150,8 @@ class CGFunc { #endif MapleMap vregsToPregsMap; uint32 totalInsns = 0; - int32 structCopySize; - int32 maxParamStackSize; + int32 structCopySize = 0; + int32 maxParamStackSize = 0; static constexpr int kRegIncrStepLen = 80; /* reg number increate step length */ bool hasVLAOrAlloca = false; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index c2f1a470e3..305c9f0338 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -161,6 +161,28 @@ bool IsBlkassignForPush(const BlkassignoffNode &bNode) { return spBased; } +MIRStructType *AArch64CGFunc::GetLmbcStructArgType(BaseNode &stmt, int32 argNo) { + MIRType *ty = nullptr; + if (stmt.GetOpCode() == OP_call) { + CallNode &callNode = static_cast(stmt); + MIRFunction *callFunc = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(callNode.GetPUIdx()); + if (callFunc->GetFormalCount() < (argNo + 1)) { + return nullptr; /* formals less than actuals */ + } + ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(callFunc->GetFormalDefVec()[argNo].formalTyIdx); + } else if (stmt.GetOpCode() == OP_icallproto) { + IcallNode &icallproto = static_cast(stmt); + MIRType *type = GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallproto.GetRetTyIdx()); + MIRFuncType *fType = static_cast(type); + if (fType->GetParamTypeList().size() < (argNo + 1)) { + return nullptr; + } + ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(fType->GetNthParamType(argNo)); + } + CHECK_FATAL(ty && ty->IsStructType(), "lmbc agg arg error"); + return static_cast(ty); +} + RegOperand &AArch64CGFunc::GetOrCreateResOperand(const BaseNode &parent, PrimType primType) { RegOperand *resOpnd = nullptr; if (parent.GetOpCode() == OP_regassign) { @@ -3095,15 +3117,19 @@ RegOperand *AArch64CGFunc::LmbcStructReturnLoad(int32 offset) { return result; } -Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff) { +Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff /*, MIRType &ty, + ListOperand &srcOpnds, AArch64CallConvImpl &parmLocator*/) { int32 offset = ireadoff.GetOffset(); PrimType primType = ireadoff.GetPrimType(); uint32 bytelen = GetPrimTypeSize(primType); +#if 1 uint32 bitlen = bytelen * kBitsPerByte; +#endif RegType regty = GetRegTyFromPrimTy(primType); RegOperand *result = nullptr; if (offset >= 0) { - LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(static_cast(offset)); +#if 1 + LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(offset); if (info->GetPrimType() == PTY_agg) { if (info->IsOnStack()) { result = GenLmbcParamLoad(info->GetOnStackOffset(), GetPrimTypeSize(PTY_a64), kRegTyInt, PTY_a64); @@ -3124,10 +3150,23 @@ Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode result = &GetOrCreatePhysicalRegisterOperand(static_cast(info->GetRegNO()), bitlen, regty); } } +#endif + CHECK_FATAL(0, "Invalid ireadfpoff offset"); } else { if (primType == PTY_agg) { - CHECK_FATAL(parent.GetOpCode() == OP_regassign, "SelectIreadfpoff of agg"); - result = LmbcStructReturnLoad(offset); +#if OLD_LMBC // TBD + if (parent.GetOpCode() == OP_call || parent.GetOpCode() == OP_icallproto) { + /* ireadfpoff is now for loading locals under calls. Large agg arg is handled via + SelectParmListPreprocess, Hence only small agg is handled here */ + SelectParmListIreadSmallAggregate(ireadoff, ty, srcOpnds, 0, parmLocator); + } else { +#endif + /* agg return */ + CHECK_FATAL(parent.GetOpCode() == OP_regassign, "SelectIreadfpoff of agg"); + result = LmbcStructReturnLoad(offset); +#if OLD_LMBC // TBD + } +#endif } else { result = GenLmbcParamLoad(offset, bytelen, regty, primType); } @@ -7361,12 +7400,26 @@ void AArch64CGFunc::SelectParmListDreadSmallAggregate(const MIRSymbol &sym, MIRT } } -void AArch64CGFunc::SelectParmListIreadSmallAggregate(const IreadNode &iread, MIRType &structType, +void AArch64CGFunc::SelectParmListIreadSmallAggregate(BaseNode &iread, MIRType &structType, ListOperand &srcOpnds, int32 offset, AArch64CallConvImpl &parmLocator) { int32 symSize = GetBecommon().GetTypeSize(structType.GetTypeIndex().GetIdx()); - RegOperand *addrOpnd0 = static_cast(HandleExpr(iread, *(iread.Opnd(0)))); - RegOperand *addrOpnd1 = &LoadIntoRegister(*addrOpnd0, iread.Opnd(0)->GetPrimType()); + RegOperand *addrOpnd1; + if (iread.GetOpCode() == OP_iread) { + RegOperand *addrOpnd0 = static_cast(HandleExpr(iread, *(iread.Opnd(0)))); + addrOpnd1 = &LoadIntoRegister(*addrOpnd0, iread.Opnd(0)->GetPrimType()); + } else if (iread.GetOpCode() == OP_ireadfpoff) { + IreadFPoffNode &ireadoff = static_cast(iread); + RegOperand *rfp = &GetOrCreatePhysicalRegisterOperand(RFP, k64BitSize, kRegTyInt); + RegOperand *addrOpnd0 = &CreateRegisterOperandOfType(PTY_a64); + ImmOperand &immOpnd = CreateImmOperand(ireadoff.GetOffset(), k32BitSize, true); + GetCurBB()->AppendInsn(GetCG()->BuildInstruction(MOP_xaddrri12, *addrOpnd0, *rfp, immOpnd)); + addrOpnd1 = &LoadIntoRegister(*addrOpnd0, PTY_i64); + } else if (iread.GetOpCode() == OP_ireadoff) { + IreadoffNode &ireadoff = static_cast(iread); + RegOperand *addrOpnd0 = static_cast(HandleExpr(ireadoff, *(ireadoff.Opnd(0)))); + addrOpnd1 = &LoadIntoRegister(*addrOpnd0, PTY_i64); + } CCLocInfo ploc; parmLocator.LocateNextParm(structType, ploc); if (ploc.reg0 == 0) { @@ -7740,8 +7793,8 @@ void AArch64CGFunc::CreateCallStructMemcpyToParamReg(MIRType &structType, int32 } } -void AArch64CGFunc::SelectParmListForAggregate(BaseNode &argExpr, ListOperand &srcOpnds, - AArch64CallConvImpl &parmLocator, int32 &structCopyOffset) { +void AArch64CGFunc::SelectParmListForAggregate(BaseNode &parent, BaseNode &argExpr, ListOperand &srcOpnds, + AArch64CallConvImpl &parmLocator, int32 &structCopyOffset, int32 argNo) { uint64 symSize; int32 rhsOffset = 0; if (argExpr.GetOpCode() == OP_dread) { @@ -7789,6 +7842,32 @@ void AArch64CGFunc::SelectParmListForAggregate(BaseNode &argExpr, ListOperand &s } else { SelectParmListIreadLargeAggregate(iread, *ty, srcOpnds, parmLocator, structCopyOffset, rhsOffset); } + } else if (argExpr.GetOpCode() == OP_ireadfpoff) { + IreadFPoffNode &iread = static_cast(argExpr); + MIRStructType *ty = GetLmbcStructArgType(parent, argNo); + if (ty == nullptr) { /* param < arg */ + return; + } + symSize = GetBecommon().GetTypeSize(ty->GetTypeIndex().GetIdx()); + if (symSize <= k16ByteSize) { + SelectParmListIreadSmallAggregate(iread, *ty, srcOpnds, rhsOffset, parmLocator); + } else { + CreateCallStructMemcpyToParamReg(*ty, structCopyOffset, parmLocator, srcOpnds); + structCopyOffset += static_cast(RoundUp(symSize, kSizeOfPtr)); + } + } else if (argExpr.GetOpCode() == OP_ireadoff) { + IreadoffNode &iread = static_cast(argExpr); + MIRStructType *ty = GetLmbcStructArgType(parent, argNo); + if (ty == nullptr) { + return; + } + symSize = GetBecommon().GetTypeSize(ty->GetTypeIndex().GetIdx()); + if (symSize <= k16ByteSize) { + SelectParmListIreadSmallAggregate(iread, *ty, srcOpnds, rhsOffset, parmLocator); + } else { + CreateCallStructMemcpyToParamReg(*ty, structCopyOffset, parmLocator, srcOpnds); + structCopyOffset += static_cast(RoundUp(symSize, kSizeOfPtr)); + } } else { CHECK_FATAL(0, "NYI"); } @@ -7831,7 +7910,7 @@ size_t AArch64CGFunc::SelectParmListGetStructReturnSize(StmtNode &naryNode) { return 0; } -void AArch64CGFunc::SelectParmListPreprocessLargeStruct(BaseNode &argExpr, int32 &structCopyOffset) { +void AArch64CGFunc::SelectParmListPreprocessLargeStruct(BaseNode &parent, BaseNode &argExpr, int32 &structCopyOffset, int32 argNo) { uint64 symSize; int32 rhsOffset = 0; if (argExpr.GetOpCode() == OP_dread) { @@ -7878,6 +7957,22 @@ void AArch64CGFunc::SelectParmListPreprocessLargeStruct(BaseNode &argExpr, int32 uint32 numMemOp = static_cast(RoundUp(symSize, kSizeOfPtr) / kSizeOfPtr); structCopyOffset += static_cast(numMemOp * kSizeOfPtr); } + } else if (argExpr.GetOpCode() == OP_ireadfpoff) { + IreadFPoffNode &ireadoff = static_cast(argExpr); + MIRStructType *ty = GetLmbcStructArgType(parent, argNo); + symSize = GetBecommon().GetTypeSize(ty->GetTypeIndex()); + if (symSize > 16 /*kParmMemcpySize*/) { +#if OLD_LMBC // TBD + MemOperand *addrOpnd0 = GenLmbcFpMemOperand(ireadoff.GetOffset(), kSizeOfPtr, RFP); + RegOperand *addrOpnd1 = &LoadIntoRegister(*addrOpnd0, PTY_i64); +#endif + RegOperand *rfp = &GetOrCreatePhysicalRegisterOperand(RFP, k64BitSize, kRegTyInt); + RegOperand *addrOpnd = &CreateRegisterOperandOfType(PTY_a64); + ImmOperand &immOpnd = CreateImmOperand(ireadoff.GetOffset(), k32BitSize, true); + GetCurBB()->AppendInsn(GetCG()->BuildInstruction(MOP_xaddrri12, *addrOpnd, *rfp, immOpnd)); + CreateCallStructParamMemcpy(nullptr, addrOpnd, static_cast(symSize), structCopyOffset, 0); + structCopyOffset += static_cast(RoundUp(symSize, kSizeOfPtr)); + } } } @@ -7909,7 +8004,7 @@ bool AArch64CGFunc::MarkParmListCall(BaseNode &expr) { return false; } -void AArch64CGFunc::SelectParmListPreprocess(const StmtNode &naryNode, size_t start, std::set &specialArgs) { +void AArch64CGFunc::SelectParmListPreprocess(StmtNode &naryNode, size_t start, std::set &specialArgs) { size_t i = start; int32 structCopyOffset = GetMaxParamStackSize() - GetStructCopySize(); for (; i < naryNode.NumOpnds(); ++i) { @@ -7922,7 +8017,7 @@ void AArch64CGFunc::SelectParmListPreprocess(const StmtNode &naryNode, size_t st if (primType != PTY_agg) { continue; } - SelectParmListPreprocessLargeStruct(*argExpr, structCopyOffset); + SelectParmListPreprocessLargeStruct(naryNode, *argExpr, structCopyOffset, i); } } @@ -8022,7 +8117,7 @@ void AArch64CGFunc::SelectParmList(StmtNode &naryNode, ListOperand &srcOpnds, bo } /* use alloca */ if (primType == PTY_agg) { - SelectParmListForAggregate(*argExpr, srcOpnds, parmLocator, structCopyOffset); + SelectParmListForAggregate(naryNode, *argExpr, srcOpnds, parmLocator, structCopyOffset, i); continue; } ty = GlobalTables::GetTypeTable().GetTypeTable()[static_cast(primType)]; @@ -9428,7 +9523,11 @@ Operand *AArch64CGFunc::GetBaseReg(const AArch64SymbolAlloc &symAlloc) { } if (fsp == nullptr) { - fsp = &GetOrCreatePhysicalRegisterOperand(RFP, kSizeOfPtr * kBitsPerByte, kRegTyInt); + if (GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { + fsp = &GetOrCreatePhysicalRegisterOperand(RSP, kSizeOfPtr * kBitsPerByte, kRegTyInt); + } else { + fsp = &GetOrCreatePhysicalRegisterOperand(RFP, kSizeOfPtr * kBitsPerByte, kRegTyInt); + } } return fsp; } diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index b7403f414f..b7ef7ae1ec 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -58,7 +58,9 @@ uint32 AArch64MemLayout::ComputeStackSpaceRequirementForCall(StmtNode &stmt, in ty = GlobalTables::GetTypeTable().GetTypeTable()[static_cast(opnd->GetPrimType())]; } else { Opcode opndOpcode = opnd->GetOpCode(); - ASSERT(opndOpcode == OP_dread || opndOpcode == OP_iread, "opndOpcode should be OP_dread or OP_iread"); + if (be.GetMIRModule().GetFlavor() != kFlavorLmbc) { + ASSERT(opndOpcode == OP_dread || opndOpcode == OP_iread, "opndOpcode should be OP_dread or OP_iread"); + } if (opndOpcode == OP_dread) { DreadNode *dread = static_cast(opnd); MIRSymbol *sym = be.GetMIRModule().CurFunction()->GetLocalOrGlobalSymbol(dread->GetStIdx()); @@ -72,8 +74,7 @@ uint32 AArch64MemLayout::ComputeStackSpaceRequirementForCall(StmtNode &stmt, in ty = static_cast(ty)->GetFieldType(dread->GetFieldID()); } } - } else { - /* OP_iread */ + } else if (opndOpcode == OP_iread) { IreadNode *iread = static_cast(opnd); ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(iread->GetTyIdx()); ASSERT(ty->GetKind() == kTypePointer, "expect pointer"); @@ -87,6 +88,11 @@ uint32 AArch64MemLayout::ComputeStackSpaceRequirementForCall(StmtNode &stmt, in ty = static_cast(ty)->GetFieldType(iread->GetFieldID()); } } + } else if ((opndOpcode == OP_ireadfpoff || opndOpcode == OP_ireadoff || opndOpcode == OP_dreadoff) && opnd->GetPrimType() == PTY_agg) { + ty = static_cast(cgFunc)->GetLmbcStructArgType(stmt, i); + } + if (ty == nullptr) { /* type mismatch */ + continue; } } CCLocInfo ploc; @@ -190,6 +196,7 @@ void AArch64MemLayout::LayoutVarargParams() { } void AArch64MemLayout::LayoutFormalParams() { +#if OLD_LMBC // TBD bool isLmbc = (be.GetMIRModule().GetFlavor() == kFlavorLmbc); if (isLmbc && mirFunction->GetFormalCount() == 0) { /* @@ -201,6 +208,7 @@ void AArch64MemLayout::LayoutFormalParams() { segArgsRegPassed.SetSize(mirFunction->GetOutParmSize()); return; } +#endif AArch64CallConvImpl parmLocator(be); CCLocInfo ploc; @@ -255,8 +263,10 @@ void AArch64MemLayout::LayoutFormalParams() { segArgsRegPassed.SetSize(static_cast(RoundUp(segArgsRegPassed.GetSize(), align))); symLoc->SetOffset(segArgsRegPassed.GetSize()); segArgsRegPassed.SetSize(segArgsRegPassed.GetSize() + size); +#if OLD_LMBC // TBD } else if (isLmbc) { segArgsRegPassed.SetSize(segArgsRegPassed.GetSize() + k8ByteSize); +#endif } } else { /* stack */ uint32 size; @@ -371,11 +381,15 @@ void AArch64MemLayout::LayoutReturnRef(std::vector &returnDelays, symLoc->SetOffset(segRefLocals.GetSize()); segRefLocals.SetSize(segRefLocals.GetSize() + be.GetTypeSize(tyIdx)); } +#if OLD_LMBC // TBD if (be.GetMIRModule().GetFlavor() == kFlavorLmbc) { segArgsToStkPass.SetSize(mirFunction->GetOutParmSize() + kDivide2 * k8ByteSize); } else { segArgsToStkPass.SetSize(FindLargestActualArea(structCopySize)); } +#else + segArgsToStkPass.SetSize(FindLargestActualArea(structCopySize)); +#endif maxParmStackSize = static_cast(segArgsToStkPass.GetSize()); if (Globals::GetInstance()->GetOptimLevel() == 0) { AssignSpillLocationsToPseudoRegisters(); @@ -527,14 +541,18 @@ uint64 AArch64MemLayout::StackFrameSize() const { uint64 total = segArgsRegPassed.GetSize() + static_cast(cgFunc)->SizeOfCalleeSaved() + GetSizeOfRefLocals() + locals().GetSize() + GetSizeOfSpillReg(); +#if OLD_LMBC // TBD if (cgFunc->GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif if (GetSizeOfGRSaveArea() > 0) { total += RoundUp(GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); } if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } +#if OLD_LMBC // TBD } +#endif /* * if the function does not have VLA nor alloca, diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 546c386c7e..9a0a3456b7 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -1115,9 +1115,11 @@ void AArch64GenProEpilog::AppendInstructionAllocateCallFrameDebug(AArch64reg reg ipoint = cgFunc.GetCurBB()->GetLastInsn(); cfiOffset = stackFrameSize; (void)InsertCFIDefCfaOffset(cfiOffset, *ipoint); +#if OLD_LMBC //TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { argsToStkPassSize -= (kDivide2 * k8ByteSize); } +#endif ipoint = &CreateAndAppendInstructionForAllocateCallFrame(argsToStkPassSize, reg0, reg1, rty); CHECK_FATAL(ipoint != nullptr, "ipoint should not be nullptr at this point"); cfiOffset = GetOffsetFromCFA(); @@ -1217,7 +1219,9 @@ void AArch64GenProEpilog::GeneratePushRegs() { Operand &spOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); +#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; +#endif if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; if (isLmbc) { @@ -1255,14 +1259,18 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); } else { +#endif offset = static_cast(memLayout->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass()); +#if OLD_LMBC // TBD } +#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignment; @@ -1323,18 +1331,22 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { } uint32 dataSizeBits = size * kBitsPerByte; uint32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif offset = static_cast(memlayout->GetGRSaveAreaBaseLoc()); /* SP reference */ if (memlayout->GetSizeOfGRSaveArea() % kAarch64StackPtrAlignment) { offset += size; /* End of area should be aligned. Hole between VR and GR area */ } +#if OLD_LMBC // TBD } else { offset = (UINT32_MAX - memlayout->GetSizeOfGRSaveArea()) + 1; /* FP reference */ if (memlayout->GetSizeOfGRSaveArea() % kAarch64StackPtrAlignment) { offset -= size; } } - uint32 grSize = (UINT32_MAX - offset) + 1; + uint32 grSize = -offset; +#endif uint32 start_regno = k8BitSize - (memlayout->GetSizeOfGRSaveArea() / size); ASSERT(start_regno <= k8BitSize, "Incorrect starting GR regno for GR Save Area"); for (uint32 i = start_regno + static_cast(R0); i < static_cast(R8); i++) { @@ -1345,11 +1357,15 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { } } Operand *stackLoc; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif stackLoc = &aarchCGFunc.CreateStkTopOpnd(offset + tmpOffset, dataSizeBits); +#if OLD_LMBC // TBD } else { stackLoc = aarchCGFunc.GenLmbcFpMemOperand(offset, size); } +#endif RegOperand ® = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(static_cast(i), k64BitSize, kRegTyInt); Insn &inst = @@ -1358,11 +1374,15 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { offset += size; } if (!CGOptions::UseGeneralRegOnly()) { +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif offset = static_cast(memlayout->GetVRSaveAreaBaseLoc()); +#if OLD_LMBC // TBD } else { offset = (UINT32_MAX - (memlayout->GetSizeOfVRSaveArea() + grSize)) + 1; } +#endif start_regno = k8BitSize - (memlayout->GetSizeOfVRSaveArea() / (size * k2BitSize)); ASSERT(start_regno <= k8BitSize, "Incorrect starting GR regno for VR Save Area"); for (uint32 i = start_regno + static_cast(V0); i < static_cast(V8); i++) { @@ -1373,11 +1393,15 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { } } Operand *stackLoc; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif stackLoc = &aarchCGFunc.CreateStkTopOpnd(offset + tmpOffset, dataSizeBits); +#if OLD_LMBC // TBD } else { stackLoc = aarchCGFunc.GenLmbcFpMemOperand(offset, size); } +#endif RegOperand ® = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(static_cast(i), k64BitSize, kRegTyFloat); Insn &inst = @@ -1479,7 +1503,9 @@ void AArch64GenProEpilog::GenerateProlog(BB &bb) { } if (useFP) { Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); +#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; +#endif int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; @@ -1682,7 +1708,10 @@ void AArch64GenProEpilog::AppendInstructionDeallocateCallFrameDebug(AArch64reg r * ldp/stp's imm should be within -512 and 504; * if ldp's imm > 504, we fall back to the ldp-add version */ +#if OLD_LMBC // TBD bool isLmbc = (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc); +#endif + bool isLmbc = false; if (cgFunc.HasVLAOrAlloca() || argsToStkPassSize == 0 || isLmbc) { int lmbcOffset = 0; if (isLmbc == false) { @@ -1769,14 +1798,18 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); } else { +#endif offset = static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass(); +#if OLD_LMBC // TBD } +#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignment; -- Gitee From 7aa47aab81c7fd04f10657e6dc3e7f8e768fb47f Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 20 Jun 2022 21:57:07 -0700 Subject: [PATCH 056/179] Turned some optimizations back off under lmbc and re-enabled some old code The OLD_LMBC define-disabled code caused coremark to fail execution. I have to put #define OLD_LMBC on aarch64_memlayout.cpp and aarch64_proepilog.cpp so coremark can work again. --- .../include/cg/aarch64/aarch64_phases.def | 34 +++++++++++-------- .../src/cg/aarch64/aarch64_memlayout.cpp | 2 ++ .../src/cg/aarch64/aarch64_proepilog.cpp | 5 ++- 3 files changed, 26 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 531e7f0535..e5627ecba3 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,16 +17,18 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + } /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); @@ -34,8 +36,10 @@ ADDTARGETPHASE("ico", CGOptions::DoICO()) ADDTARGETPHASE("cfgo", !GetMIRModule()->IsCModule() && CGOptions::DoCFGO()); - ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); - ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); +if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); + ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); +} ADDTARGETPHASE("clearrdinfo", (CGOptions::DoStoreLoadOpt()) || CGOptions::DoGlobalOpt()); ADDTARGETPHASE("prepeephole1", CGOptions::DoPrePeephole()); @@ -45,8 +49,10 @@ ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + } ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index b7ef7ae1ec..c35acefa9a 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -17,6 +17,8 @@ #include "becommon.h" #include "mir_nodes.h" +#define OLD_LMBC 1 + namespace maplebe { using namespace maple; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 9a0a3456b7..4b479338dc 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -16,6 +16,8 @@ #include "cg_option.h" #include "cgfunc.h" +#define OLD_LMBC 1 + namespace maplebe { using namespace maple; @@ -1710,8 +1712,9 @@ void AArch64GenProEpilog::AppendInstructionDeallocateCallFrameDebug(AArch64reg r */ #if OLD_LMBC // TBD bool isLmbc = (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc); -#endif +#else bool isLmbc = false; +#endif if (cgFunc.HasVLAOrAlloca() || argsToStkPassSize == 0 || isLmbc) { int lmbcOffset = 0; if (isLmbc == false) { -- Gitee From f1b86bd51a6400c7d341d86ac2cc213877513e77 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Wed, 22 Jun 2022 22:07:59 -0700 Subject: [PATCH 057/179] Handle addrofoff as operand of OP_asm --- .../maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 12 ++++++++++++ src/mapleall/maple_ir/src/bin_func_import.cpp | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 305c9f0338..5ea4af649b 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1256,6 +1256,18 @@ void AArch64CGFunc::SelectAsm(AsmNode &node) { } break; } + case OP_addrofoff: { + auto &addrofoffNode = static_cast(*node.Opnd(i)); + Operand *inOpnd = SelectAddrofoff(addrofoffNode, node); + listInputOpnd->PushOpnd(static_cast(*inOpnd)); + PrimType pType = addrofoffNode.GetPrimType(); + listInRegPrefix->stringList.push_back( + static_cast(&CreateStringOperand(GetRegPrefixFromPrimType(pType, inOpnd->GetSize(), str)))); + if (isOutputTempNode) { + rPlusOpnd.emplace_back(std::make_pair(inOpnd, pType)); + } + break; + } case OP_constval: { CHECK_FATAL(!isOutputTempNode, "Unexpect"); auto &constNode = static_cast(*node.Opnd(i)); diff --git a/src/mapleall/maple_ir/src/bin_func_import.cpp b/src/mapleall/maple_ir/src/bin_func_import.cpp index 580d52abc4..2d6db2162e 100644 --- a/src/mapleall/maple_ir/src/bin_func_import.cpp +++ b/src/mapleall/maple_ir/src/bin_func_import.cpp @@ -45,7 +45,7 @@ void BinaryMplImport::ImportFuncIdInfo(MIRFunction *func) { func->SetPuidxOrigin(static_cast(ReadNum())); ImportInfoVector(func->GetInfoVector(), func->InfoIsString()); if (mod.GetFlavor() == kFlavorLmbc) { - func->SetFrameSize(static_cast(ReadNum())); + func->SetFrameSize(static_cast(ReadNum())); } } -- Gitee From 13619f628587e25a803fb32e76a9037766f42d35 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Fri, 24 Jun 2022 21:00:36 -0700 Subject: [PATCH 058/179] Handled more types of asm operands --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 5ea4af649b..c90dead0df 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1268,6 +1268,30 @@ void AArch64CGFunc::SelectAsm(AsmNode &node) { } break; } + case OP_ireadoff: { + IreadoffNode *ireadoff = static_cast(node.Opnd(i)); + Operand *inOpnd = SelectIreadoff(node, *ireadoff); + listInputOpnd->PushOpnd(static_cast(*inOpnd)); + PrimType pType = ireadoff->GetPrimType(); + listInRegPrefix->stringList.push_back( + static_cast(&CreateStringOperand(GetRegPrefixFromPrimType(pType, inOpnd->GetSize(), str)))); + if (isOutputTempNode) { + rPlusOpnd.emplace_back(std::make_pair(inOpnd, pType)); + } + break; + } + case OP_add: { + BinaryNode *addNode = static_cast(node.Opnd(i)); + Operand *inOpnd = SelectAdd(*addNode, *HandleExpr(*addNode, *addNode->Opnd(0)), *HandleExpr(*addNode, *addNode->Opnd(1)), node); + listInputOpnd->PushOpnd(static_cast(*inOpnd)); + PrimType pType = addNode->GetPrimType(); + listInRegPrefix->stringList.push_back( + static_cast(&CreateStringOperand(GetRegPrefixFromPrimType(pType, inOpnd->GetSize(), str)))); + if (isOutputTempNode) { + rPlusOpnd.emplace_back(std::make_pair(inOpnd, pType)); + } + break; + } case OP_constval: { CHECK_FATAL(!isOutputTempNode, "Unexpect"); auto &constNode = static_cast(*node.Opnd(i)); -- Gitee From 1b73c197b03d5e267b89e58271efdf7cb640ed27 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Sat, 25 Jun 2022 12:21:10 -0700 Subject: [PATCH 059/179] More edits to rebase to master branch --- src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 2 +- src/mapleall/maple_be/src/cg/cgfunc.cpp | 4 ++-- src/mapleall/maple_ir/include/bin_mpl_export.h | 1 - src/mapleall/maple_ir/src/bin_mpl_export.cpp | 3 +-- src/mapleall/maple_me/include/lmbc_memlayout.h | 4 +--- 5 files changed, 5 insertions(+), 9 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index c90dead0df..831e81a8f7 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -2133,7 +2133,7 @@ MIRType *AArch64CGFunc::LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector(static_cast(src)->GetRegisterNumber()); diff --git a/src/mapleall/maple_be/src/cg/cgfunc.cpp b/src/mapleall/maple_be/src/cg/cgfunc.cpp index 86368cbbc4..b583213e4c 100644 --- a/src/mapleall/maple_be/src/cg/cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/cgfunc.cpp @@ -1587,7 +1587,7 @@ void CGFunc::CreateLmbcFormalParamInfo() { stackOffset += (typeSize + 7) & (-8); LmbcFormalParamInfo *info = GetMemoryPool()->New(primType, offset, typeSize); lmbcParamVec.push_back(info); - if (idx == 0 && lmbcFunc.IsFirstArgReturn()) { + if (idx == 0 && func.IsFirstArgReturn()) { info->SetIsReturn(); } if (type->GetKind() == kTypeStruct) { @@ -1604,7 +1604,7 @@ void CGFunc::CreateLmbcFormalParamInfo() { } } else { /* No aggregate pass by value here */ - for (StmtNode *stmt = lmbcFunc.GetBody()->GetFirst(); stmt != nullptr; stmt = stmt->GetNext()) { + for (StmtNode *stmt = func.GetBody()->GetFirst(); stmt != nullptr; stmt = stmt->GetNext()) { if (stmt == nullptr) { break; } diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 9cada84eb4..918c8e04eb 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,7 +181,6 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; - MIRFunction *curFunc = nullptr; size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; diff --git a/src/mapleall/maple_ir/src/bin_mpl_export.cpp b/src/mapleall/maple_ir/src/bin_mpl_export.cpp index 886eaa4c39..f5fd677ce9 100644 --- a/src/mapleall/maple_ir/src/bin_mpl_export.cpp +++ b/src/mapleall/maple_ir/src/bin_mpl_export.cpp @@ -1110,7 +1110,6 @@ void BinaryMplExport::WriteSymField(uint64 contentIdx) { for (auto sit = GetMIRModule().GetSymbolDefOrder().begin(); sit != GetMIRModule().GetSymbolDefOrder().end(); ++sit) { MIRSymbol *s = GlobalTables::GetGsymTable().GetSymbolFromStidx(sit->Idx()); - ASSERT(s != nullptr, "null ptr check"); // Verify: all wpofake variables should have been deleted from globaltable ASSERT(!(s->IsWpoFakeParm() || s->IsWpoFakeRet()) || s->IsDeleted(), "wpofake var not deleted"); MIRStorageClass storageClass = s->GetStorageClass(); @@ -1242,7 +1241,7 @@ void BinaryMplExport::AppendAt(const std::string &name, int32 offset) { LogInfo::MapleLogger(kLlErr) << "Error while opening the binary file: " << name << '\n'; FATAL(kLncFatal, "Error while creating the binary file: %s\n", name.c_str()); } - int seekRet = fseek(f, static_cast(offset), SEEK_SET); + int seekRet = fseek(f, (long int)offset, SEEK_SET); CHECK_FATAL(seekRet == 0, "Call fseek failed."); size_t size = buf.size(); size_t k = fwrite(&buf[0], sizeof(uint8), size, f); diff --git a/src/mapleall/maple_me/include/lmbc_memlayout.h b/src/mapleall/maple_me/include/lmbc_memlayout.h index 833b357561..923c118665 100644 --- a/src/mapleall/maple_me/include/lmbc_memlayout.h +++ b/src/mapleall/maple_me/include/lmbc_memlayout.h @@ -42,9 +42,7 @@ class SymbolAlloc { public: SymbolAlloc() : mem_segment(nullptr), offset(0) {} - ~SymbolAlloc() { - mem_segment = nullptr; - } + ~SymbolAlloc() {} MemSegment *mem_segment; int32 offset; -- Gitee From 38726cda588edce2053718f70bf74b604d89876f Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:16:12 -0700 Subject: [PATCH 060/179] Turn on globalopt for lmbc, but leave SSA opt off --- src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def | 6 ++---- src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp | 4 +++- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index e5627ecba3..856c48e6bd 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -49,10 +49,8 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); - } + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 4a2f257321..6b5d902cb4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,7 +412,9 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - CHECK_FATAL(false, "check case in ssa"); + if (cgFunc.GetCG()->IsLmbc() == false) { + CHECK_FATAL(false, "check case in ssa"); + } } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From 4d72db280e523462409a860e5b834ff0a17de39b Mon Sep 17 00:00:00 2001 From: William Chen Date: Mon, 13 Jun 2022 14:06:17 -0700 Subject: [PATCH 061/179] Do not optimize for ssa for physical regs. --- .../include/cg/aarch64/aarch64_phases.def | 22 +++++++++---------- .../src/cg/aarch64/aarch64_global.cpp | 4 +--- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 856c48e6bd..f11ca1435e 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,18 +17,16 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); - } + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 6b5d902cb4..4a2f257321 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,9 +412,7 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - if (cgFunc.GetCG()->IsLmbc() == false) { - CHECK_FATAL(false, "check case in ssa"); - } + CHECK_FATAL(false, "check case in ssa"); } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From 0a72eab45a99aa896b518d885f8521cd22745964 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 20 Jun 2022 21:57:07 -0700 Subject: [PATCH 062/179] Turned some optimizations back off under lmbc and re-enabled some old code The OLD_LMBC define-disabled code caused coremark to fail execution. I have to put #define OLD_LMBC on aarch64_memlayout.cpp and aarch64_proepilog.cpp so coremark can work again. --- .../include/cg/aarch64/aarch64_phases.def | 28 +++++++++++-------- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index f11ca1435e..e5627ecba3 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,16 +17,18 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + } /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); @@ -47,8 +49,10 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + } ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); -- Gitee From 077851b9365ecb96245bacd6f8396e046fedb649 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Sat, 25 Jun 2022 14:55:37 -0700 Subject: [PATCH 063/179] Fixed a rebase bug --- src/mapleall/maple_me/include/lmbc_memlayout.h | 12 +++--------- src/mapleall/maple_me/src/lmbc_lower.cpp | 4 ++-- 2 files changed, 5 insertions(+), 11 deletions(-) diff --git a/src/mapleall/maple_me/include/lmbc_memlayout.h b/src/mapleall/maple_me/include/lmbc_memlayout.h index 923c118665..83b59ba69f 100644 --- a/src/mapleall/maple_me/include/lmbc_memlayout.h +++ b/src/mapleall/maple_me/include/lmbc_memlayout.h @@ -38,14 +38,9 @@ typedef enum { class MemSegment; // describes where a symbol is allocated -class SymbolAlloc { - public: - SymbolAlloc() : mem_segment(nullptr), offset(0) {} - - ~SymbolAlloc() {} - - MemSegment *mem_segment; - int32 offset; +struct SymbolAlloc { + MemSegment *mem_segment = nullptr; + int32 offset = 0; }; // class SymbolAlloc // keeps track of the allocation of a memory segment @@ -59,7 +54,6 @@ class MemSegment { MemSegmentKind kind; int32 size; // size is negative if allocated offsets are negative - SymbolAlloc how_alloc; // this segment may be allocated inside another segment }; // class MemSegment class LMBCMemLayout { diff --git a/src/mapleall/maple_me/src/lmbc_lower.cpp b/src/mapleall/maple_me/src/lmbc_lower.cpp index 9ba84151e5..8cb339f657 100644 --- a/src/mapleall/maple_me/src/lmbc_lower.cpp +++ b/src/mapleall/maple_me/src/lmbc_lower.cpp @@ -25,8 +25,8 @@ PregIdx LMBCLowerer::GetSpecialRegFromSt(const MIRSymbol *sym) { if (storageClass == kScAuto) { CHECK(sym->GetStIndex() < memlayout->sym_alloc_table.size(), "index out of range in LMBCLowerer::GetSpecialRegFromSt"); - SymbolAlloc symalloc = memlayout->sym_alloc_table[sym->GetStIndex()]; - if (symalloc.mem_segment->kind == MS_FPbased) { + SymbolAlloc *symalloc = &memlayout->sym_alloc_table[sym->GetStIndex()]; + if (symalloc->mem_segment->kind == MS_FPbased) { specreg = -kSregFp; } else { CHECK_FATAL(false, "LMBCLowerer::LowerDread: bad memory layout for local variable"); -- Gitee From 1bffb814e9d38dfbd2051e697c929d31728fd563 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Mon, 27 Jun 2022 14:41:54 -0700 Subject: [PATCH 064/179] Update for agg ret, caller/callee save offset. --- .../include/cg/aarch64/aarch64_cgfunc.h | 2 +- .../src/cg/aarch64/aarch64_cgfunc.cpp | 44 +++++++++++++------ .../src/cg/aarch64/aarch64_memlayout.cpp | 2 - .../src/cg/aarch64/aarch64_proepilog.cpp | 24 +++++----- 4 files changed, 45 insertions(+), 27 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index be3a3bae62..4d1e9370c2 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -130,7 +130,7 @@ class AArch64CGFunc : public CGFunc { uint32 LmbcFindTotalStkUsed(std::vector* paramList); uint32 LmbcTotalRegsUsed(); void LmbcSelectParmList(ListOperand *srcOpnds, bool isArgReturn); - bool LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src); + bool LmbcSmallAggForRet(BaseNode &bNode, Operand *src); bool LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src, std::vector **parmList); void SelectAggDassign(DassignNode &stmt) override; void SelectIassign(IassignNode &stmt) override; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 831e81a8f7..ae157979ef 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1487,6 +1487,12 @@ void AArch64CGFunc::SelectRegassign(RegassignNode &stmt, Operand &opnd0) { prev->SetMOP(MOP_xldrsw); } } + if (lhsSize == PTY_agg && (stmt.Opnd(0)->GetOpCode() == OP_ireadoff || stmt.Opnd(0)->GetOpCode() == OP_ireadfpoff)) { + PregIdx pregIdx = stmt.GetRegIdx(); + if ((-pregIdx) == kSregRetval0) { + return; // Already loaded to correct return registers + } + } } RegOperand *regOpnd = nullptr; PregIdx pregIdx = stmt.GetRegIdx(); @@ -2133,7 +2139,7 @@ MIRType *AArch64CGFunc::LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector(static_cast(src)->GetRegisterNumber()); @@ -2143,9 +2149,9 @@ bool AArch64CGFunc::LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src) { /* This blkassignoff is for struct return? */ uint32 loadSize; uint32 numRegs = 0; - if (bNode.GetNext()->GetOpCode() == OP_return) { - MIRStructType *ty = static_cast( - GlobalTables::GetTypeTable().GetTypeFromTyIdx(func->GetFuncRetStructTyIdx())); + if (static_cast(bNode).GetNext()->GetOpCode() == OP_return) { + MIRStructType *ty = static_cast(func->GetReturnType()); + uint32 tySize = GetBecommon().GetTypeSize(ty->GetTypeIndex()); uint32 fpregs = FloatParamRegRequired(ty, size); if (fpregs > 0) { /* pure floating point in agg */ @@ -2164,7 +2170,7 @@ bool AArch64CGFunc::LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src) { numRegs = 2; pTy = PTY_i64; size = k4ByteSize; - switch (bNode.blockSize) { + switch (tySize) { case 1: pTy = PTY_i8; break; @@ -2182,7 +2188,7 @@ bool AArch64CGFunc::LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src) { MemOperand &mem = CreateMemOpnd(regno, 0, size * kBitsPerByte); RegOperand *res = &GetOrCreatePhysicalRegisterOperand(R0, loadSize, kRegTyInt); SelectCopy(*res, pTy, mem, pTy); - if (bNode.blockSize > static_cast(k8ByteSize)) { + if (tySize > static_cast(k8ByteSize)) { MemOperand &newMem = CreateMemOpnd(regno, k8ByteSize, size * kBitsPerByte); res = &GetOrCreatePhysicalRegisterOperand(R1, loadSize, kRegTyInt); SelectCopy(*res, pTy, newMem, pTy); @@ -3103,9 +3109,20 @@ Operand *AArch64CGFunc::SelectIreadoff(const BaseNode &parent, IreadoffNode &ire auto *baseAddr = ireadoff.Opnd(0); auto *result = &CreateRegisterOperandOfType(primType); auto *addrOpnd = HandleExpr(ireadoff, *baseAddr); - auto &memOpnd = CreateMemOpnd(LoadIntoRegister(*addrOpnd, PTY_a64), offset, bitSize); - auto mop = PickLdInsn(bitSize, primType); - GetCurBB()->AppendInsn(GetCG()->BuildInstruction(mop, *result, memOpnd)); + if (primType == PTY_agg && parent.GetOpCode() == OP_regassign) { + auto &memOpnd = CreateMemOpnd(LoadIntoRegister(*addrOpnd, PTY_a64), offset, bitSize); + auto mop = PickLdInsn(64, PTY_a64); + GetCurBB()->AppendInsn(GetCG()->BuildInstruction(mop, *result, memOpnd)); + auto ®AssignNode = static_cast(parent); + PregIdx pIdx = regAssignNode.GetRegIdx(); + CHECK_FATAL(IsSpecialPseudoRegister(pIdx), "SelectIreadfpoff of agg"); + LmbcSmallAggForRet(const_cast(parent), addrOpnd); + // result not used + } else { + auto &memOpnd = CreateMemOpnd(LoadIntoRegister(*addrOpnd, PTY_a64), offset, bitSize); + auto mop = PickLdInsn(bitSize, primType); + GetCurBB()->AppendInsn(GetCG()->BuildInstruction(mop, *result, memOpnd)); + } return result; } @@ -3158,13 +3175,11 @@ Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode int32 offset = ireadoff.GetOffset(); PrimType primType = ireadoff.GetPrimType(); uint32 bytelen = GetPrimTypeSize(primType); -#if 1 - uint32 bitlen = bytelen * kBitsPerByte; -#endif RegType regty = GetRegTyFromPrimTy(primType); RegOperand *result = nullptr; if (offset >= 0) { -#if 1 +#if OLD_LMBC // TBD + uint32 bitlen = bytelen * kBitsPerByte; LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(offset); if (info->GetPrimType() == PTY_agg) { if (info->IsOnStack()) { @@ -3186,8 +3201,9 @@ Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode result = &GetOrCreatePhysicalRegisterOperand(static_cast(info->GetRegNO()), bitlen, regty); } } -#endif +#else CHECK_FATAL(0, "Invalid ireadfpoff offset"); +#endif } else { if (primType == PTY_agg) { #if OLD_LMBC // TBD diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index c35acefa9a..b7ef7ae1ec 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -17,8 +17,6 @@ #include "becommon.h" #include "mir_nodes.h" -#define OLD_LMBC 1 - namespace maplebe { using namespace maple; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 4b479338dc..5ce27d6c2d 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -16,8 +16,6 @@ #include "cg_option.h" #include "cgfunc.h" -#define OLD_LMBC 1 - namespace maplebe { using namespace maple; @@ -1261,18 +1259,21 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; -#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { +#if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); - } else { +#else + offset = static_cast(memLayout->RealStackFrameSize() - + (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen)/* FP/LR */) - + memLayout->GetSizeOfLocals() - + memLayout->SizeOfArgsToStackPass()); #endif + } else { offset = static_cast(memLayout->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass()); -#if OLD_LMBC // TBD } -#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignment; @@ -1801,18 +1802,21 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; -#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { +#if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); - } else { +#else + offset = static_cast(memLayout->RealStackFrameSize() - + (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen)/* FP/LR */) - + memLayout->GetSizeOfLocals() - + memLayout->SizeOfArgsToStackPass()); #endif + } else { offset = static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass(); -#if OLD_LMBC // TBD } -#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignment; -- Gitee From 66a34c74b4d987bb5647bf2aef13f43930af967c Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 27 Jun 2022 18:36:42 -0700 Subject: [PATCH 065/179] For actual parameters corresponding to varargs, made lmbc lower struct parameters differently so as not to lose their type info --- src/mapleall/maple_me/src/lmbc_lower.cpp | 47 +++++++++++++++++++ .../maple_me/src/me_phase_manager.cpp | 3 ++ 2 files changed, 50 insertions(+) diff --git a/src/mapleall/maple_me/src/lmbc_lower.cpp b/src/mapleall/maple_me/src/lmbc_lower.cpp index 8cb339f657..c5913b036e 100644 --- a/src/mapleall/maple_me/src/lmbc_lower.cpp +++ b/src/mapleall/maple_me/src/lmbc_lower.cpp @@ -411,6 +411,53 @@ BlockNode *LMBCLowerer::LowerBlock(BlockNode *block) { } break; } + case OP_call: + case OP_icallproto: { + for (size_t i = 0; i < stmt->NumOpnds(); ++i) { + if (stmt->Opnd(i)->GetPrimType() != PTY_agg) { + stmt->SetOpnd(LowerExpr(stmt->Opnd(i)), i); + } else { + bool paramInPrototype = false; + MIRFuncType *funcType = nullptr; + if (stmt->GetOpCode() == OP_icallproto) { + IcallNode *icallproto = static_cast(stmt); + funcType = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallproto->GetRetTyIdx())); + paramInPrototype = (i-1) < funcType->GetParamTypeList().size(); + } else { + CallNode *callNode = static_cast(stmt); + MIRFunction *calleeFunc = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(callNode->GetPUIdx()); + funcType = calleeFunc->GetMIRFuncType(); + paramInPrototype = i < funcType->GetParamTypeList().size(); + } + if (paramInPrototype) { + stmt->SetOpnd(LowerExpr(stmt->Opnd(i)), i); + } else { // lower to iread so the type can be provided + if (stmt->Opnd(i)->GetOpCode() == OP_iread) { + IreadNode *iread = static_cast(stmt->Opnd(i)); + iread->SetOpnd(LowerExpr(iread->Opnd(0)), 0); + } else if (stmt->Opnd(i)->GetOpCode() == OP_dread) { + AddrofNode *addrof = static_cast(stmt->Opnd(i)); + FieldID fid = addrof->GetFieldID(); + addrof->SetOpCode(OP_addrof); + addrof->SetPrimType(GetExactPtrPrimType()); + addrof->SetFieldID(0); + MIRSymbol *symbol = func->GetLocalOrGlobalSymbol(addrof->GetStIdx()); + MIRPtrType ptrType(symbol->GetTyIdx(), GetExactPtrPrimType()); + ptrType.SetTypeAttrs(symbol->GetAttrs()); + TyIdx addrTyIdx = GlobalTables::GetTypeTable().GetOrCreateMIRType(&ptrType); + if (addrTyIdx == becommon->GetSizeOfTypeSizeTable()) { + MIRType *newType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(addrTyIdx); + becommon->UpdateTypeTable(*newType); + } + IreadNode *newIread = mirModule->CurFuncCodeMemPool()->New(OP_iread, PTY_agg, addrTyIdx, fid, LowerExpr(addrof)); + stmt->SetOpnd(newIread, i); + } + } + } + } + newblk->AddStatement(stmt); + break; + } default: { for (size_t i = 0; i < stmt->NumOpnds(); ++i) { stmt->SetOpnd(LowerExpr(stmt->Opnd(i)), i); diff --git a/src/mapleall/maple_me/src/me_phase_manager.cpp b/src/mapleall/maple_me/src/me_phase_manager.cpp index a0b5419a8e..92fb5a9f53 100644 --- a/src/mapleall/maple_me/src/me_phase_manager.cpp +++ b/src/mapleall/maple_me/src/me_phase_manager.cpp @@ -149,6 +149,9 @@ bool MeFuncPM::PhaseRun(maple::MIRModule &m) { if (func->GetBody() == nullptr) { continue; } + if (!IsQuiet()) { + LogInfo::MapleLogger() << ">>>> Generating LMBC for Function < " << func->GetName() << " > [" << i - 1 << "]\n"; + } m.SetCurFunction(func); cgLower.LowerFunc(*func); MemPool *layoutMp = memPoolCtrler.NewMemPool("layout mempool", true); -- Gitee From 4a5a02492dfa1a18bb841f066076f76a4cc4fb51 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 27 Jun 2022 21:09:51 -0700 Subject: [PATCH 066/179] Deleted LmbcSelectParmList() which no longer serves any purpose --- .../include/cg/aarch64/aarch64_cgfunc.h | 1 - .../src/cg/aarch64/aarch64_cgfunc.cpp | 53 ------------------- .../maple_me/src/me_phase_manager.cpp | 2 +- 3 files changed, 1 insertion(+), 55 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index 4d1e9370c2..f7b6cf6824 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -129,7 +129,6 @@ class AArch64CGFunc : public CGFunc { MemOperand *FixLargeMemOpnd(MOperator mOp, MemOperand &memOpnd, uint32 dSize, uint32 opndIdx); uint32 LmbcFindTotalStkUsed(std::vector* paramList); uint32 LmbcTotalRegsUsed(); - void LmbcSelectParmList(ListOperand *srcOpnds, bool isArgReturn); bool LmbcSmallAggForRet(BaseNode &bNode, Operand *src); bool LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src, std::vector **parmList); void SelectAggDassign(DassignNode &stmt) override; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index ae157979ef..e66bb24972 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -8579,56 +8579,6 @@ void AArch64CGFunc::IntrinsifyStringIndexOf(ListOperand &srcOpnds, const MIRSymb SetCurBB(*jointBB); } -/* Lmbc calls have no argument, they are all explicit iassignspoff or - blkassign. Info collected and to be emitted here */ -void AArch64CGFunc::LmbcSelectParmList(ListOperand *srcOpnds, bool isArgReturn) { - if (GetLmbcArgInfo() == nullptr) { - return; /* no arg */ - } - CHECK_FATAL(GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc, "To be called for Lmbc model only"); - MapleVector &args = GetLmbcCallArgs(); - MapleVector &types = GetLmbcCallArgTypes(); - MapleVector &offsets = GetLmbcCallArgOffsets(); - MapleVector ®s = GetLmbcCallArgNumOfRegs(); - int iCnt = 0; - int fCnt = 0; - for (size_t i = isArgReturn ? 1 : 0; i < args.size(); i++) { - RegType ty = args[i]->GetRegisterType(); - PrimType pTy = types[i]; - AArch64reg reg; - if (args[i]->IsOfIntClass() && (iCnt + regs[i]) <= static_cast(k8ByteSize)) { - reg = static_cast(R0 + iCnt++); - RegOperand *res = &GetOrCreatePhysicalRegisterOperand( - reg, GetPrimTypeSize(pTy) * kBitsPerByte, ty); - SelectCopy(*res, pTy, *args[i], pTy); - srcOpnds->PushOpnd(*res); - } else if (!args[i]->IsOfIntClass() && (fCnt + regs[i]) <= static_cast(k8ByteSize)) { - reg = static_cast(V0 + fCnt++); - RegOperand *res = &GetOrCreatePhysicalRegisterOperand( - reg, GetPrimTypeSize(pTy) * kBitsPerByte, ty); - SelectCopy(*res, pTy, *args[i], pTy); - srcOpnds->PushOpnd(*res); - } else { - uint32 pSize = GetPrimTypeSize(pTy); - Operand &memOpd = CreateMemOpnd(RSP, offsets[i], pSize); - GetCurBB()->AppendInsn(GetCG()->BuildInstruction(PickStInsn(pSize * kBitsPerByte, pTy), - *args[i], memOpd)); - } - } - /* Load x8 if 1st arg is for agg return */ - if (isArgReturn) { - AArch64reg reg = static_cast(R8); - RegOperand *res = &GetOrCreatePhysicalRegisterOperand(reg, - GetPrimTypeSize(PTY_a64) * kBitsPerByte, - kRegTyInt); - SelectCopy(*res, PTY_a64, *args[0], PTY_a64); - srcOpnds->PushOpnd(*res); - } - ResetLmbcArgInfo(); /* reset */ - ResetLmbcArgsInRegs(); - ResetLmbcTotalArgs(); -} - void AArch64CGFunc::SelectCall(CallNode &callNode) { MIRFunction *fn = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(callNode.GetPUIdx()); MIRSymbol *fsym = GetFunction().GetLocalOrGlobalSymbol(fn->GetStIdx(), false); @@ -8642,17 +8592,14 @@ void AArch64CGFunc::SelectCall(CallNode &callNode) { ListOperand *srcOpnds = CreateListOpnd(*GetFuncScopeAllocator()); if (GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { SetLmbcCallReturnType(nullptr); - bool largeStructRet = false; if (fn->IsFirstArgReturn()) { MIRPtrType *ptrTy = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(fn->GetFormalDefVec()[0].formalTyIdx)); MIRType *sTy = GlobalTables::GetTypeTable().GetTypeFromTyIdx(ptrTy->GetPointedTyIdx()); - largeStructRet = sTy->GetSize() > k16ByteSize; SetLmbcCallReturnType(sTy); } else { MIRType *ty = fn->GetReturnType(); SetLmbcCallReturnType(ty); } - LmbcSelectParmList(srcOpnds, largeStructRet); } bool callNative = false; if ((fsym->GetName() == "MCC_CallFastNative") || (fsym->GetName() == "MCC_CallFastNativeExt") || diff --git a/src/mapleall/maple_me/src/me_phase_manager.cpp b/src/mapleall/maple_me/src/me_phase_manager.cpp index 92fb5a9f53..a9b5b3e636 100644 --- a/src/mapleall/maple_me/src/me_phase_manager.cpp +++ b/src/mapleall/maple_me/src/me_phase_manager.cpp @@ -150,7 +150,7 @@ bool MeFuncPM::PhaseRun(maple::MIRModule &m) { continue; } if (!IsQuiet()) { - LogInfo::MapleLogger() << ">>>> Generating LMBC for Function < " << func->GetName() << " > [" << i - 1 << "]\n"; + LogInfo::MapleLogger() << ">>>> Generating LMBC for Function < " << func->GetName() << " >\n"; } m.SetCurFunction(func); cgLower.LowerFunc(*func); -- Gitee From 793aadbef0c377746a78136b45828a20d48ecf33 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Tue, 28 Jun 2022 09:20:43 -0700 Subject: [PATCH 067/179] Fixed coredump at end of coremark. --- src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index e66bb24972..267fcb99b2 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -9554,7 +9554,7 @@ int32 AArch64CGFunc::GetBaseOffset(const SymbolAlloc &sa) { return baseOffset + sizeofFplr; } else if (sgKind == kMsSpillReg) { if (GetCG()->IsLmbc()) { - return symAlloc->GetOffset() + memLayout->SizeOfArgsToStackPass(); + return symAlloc->GetOffset() + memLayout->SizeOfArgsToStackPass() + sizeofFplr; } int32 baseOffset = symAlloc->GetOffset() + memLayout->SizeOfArgsRegisterPassed() + memLayout->GetSizeOfLocals() + memLayout->GetSizeOfRefLocals(); -- Gitee From 230112688328a7332e1eef7b530334e5ce0a19fc Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Tue, 28 Jun 2022 14:08:17 -0700 Subject: [PATCH 068/179] Further changes for GetBaseOffset(). --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 20 +++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 267fcb99b2..8069169dcd 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -9544,20 +9544,32 @@ int32 AArch64CGFunc::GetBaseOffset(const SymbolAlloc &sa) { int32 offset = static_cast(symAlloc->GetOffset()); return offset; } else if (sgKind == kMsArgsRegPassed) { - int32 baseOffset = memLayout->GetSizeOfLocals() + symAlloc->GetOffset() + memLayout->GetSizeOfRefLocals(); + int32 baseOffset; + if (GetCG()->IsLmbc()) { + baseOffset = symAlloc->GetOffset() + memLayout->GetSizeOfRefLocals(); + } else { + baseOffset = memLayout->GetSizeOfLocals() + symAlloc->GetOffset() + + memLayout->GetSizeOfRefLocals(); + } return baseOffset + sizeofFplr; } else if (sgKind == kMsRefLocals) { int32 baseOffset = symAlloc->GetOffset() + memLayout->GetSizeOfLocals(); return baseOffset + sizeofFplr; } else if (sgKind == kMsLocals) { + if (GetCG()->IsLmbc()) { + CHECK_FATAL(false, "invalid lmbc's locals"); + } int32 baseOffset = symAlloc->GetOffset(); return baseOffset + sizeofFplr; } else if (sgKind == kMsSpillReg) { + int32 baseOffset; if (GetCG()->IsLmbc()) { - return symAlloc->GetOffset() + memLayout->SizeOfArgsToStackPass() + sizeofFplr; + baseOffset = symAlloc->GetOffset() + memLayout->SizeOfArgsRegisterPassed() + + memLayout->GetSizeOfRefLocals(); + } else { + baseOffset = symAlloc->GetOffset() + memLayout->SizeOfArgsRegisterPassed() + + memLayout->GetSizeOfLocals() + memLayout->GetSizeOfRefLocals(); } - int32 baseOffset = symAlloc->GetOffset() + memLayout->SizeOfArgsRegisterPassed() + memLayout->GetSizeOfLocals() + - memLayout->GetSizeOfRefLocals(); return baseOffset + sizeofFplr; } else if (sgKind == kMsArgsToStkPass) { /* this is for callers */ return static_cast(symAlloc->GetOffset()); -- Gitee From 2c84c726f54bfb98d2868da871c8531565ba9a49 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Tue, 28 Jun 2022 16:17:38 -0700 Subject: [PATCH 069/179] Fix for small agg return. --- src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 8069169dcd..969c2cde44 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1487,12 +1487,14 @@ void AArch64CGFunc::SelectRegassign(RegassignNode &stmt, Operand &opnd0) { prev->SetMOP(MOP_xldrsw); } } +#if 0 if (lhsSize == PTY_agg && (stmt.Opnd(0)->GetOpCode() == OP_ireadoff || stmt.Opnd(0)->GetOpCode() == OP_ireadfpoff)) { PregIdx pregIdx = stmt.GetRegIdx(); if ((-pregIdx) == kSregRetval0) { return; // Already loaded to correct return registers } } +#endif } RegOperand *regOpnd = nullptr; PregIdx pregIdx = stmt.GetRegIdx(); -- Gitee From 09fa6532210e6077830e422717bb3046c24d1107 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Thu, 30 Jun 2022 11:24:14 -0700 Subject: [PATCH 070/179] Some fixes for lmbc vararg memlayout --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 2 ++ .../src/cg/aarch64/aarch64_memlayout.cpp | 4 ---- .../src/cg/aarch64/aarch64_proepilog.cpp | 19 +++++++++++-------- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 969c2cde44..309141a2d9 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -10243,9 +10243,11 @@ void AArch64CGFunc::SelectCVaStart(const IntrinsiccallNode &intrnNode) { inReg++; } } +#if OLD_LMBC // TBD if (GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { stkSize += (inReg * k8ByteSize); } +#endif if (CGOptions::IsArm64ilp32()) { stkSize = static_cast(RoundUp(stkSize, k8ByteSize)); } else { diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index b7ef7ae1ec..bd5ad49758 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -541,18 +541,14 @@ uint64 AArch64MemLayout::StackFrameSize() const { uint64 total = segArgsRegPassed.GetSize() + static_cast(cgFunc)->SizeOfCalleeSaved() + GetSizeOfRefLocals() + locals().GetSize() + GetSizeOfSpillReg(); -#if OLD_LMBC // TBD if (cgFunc->GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { -#endif if (GetSizeOfGRSaveArea() > 0) { total += RoundUp(GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); } if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } -#if OLD_LMBC // TBD } -#endif /* * if the function does not have VLA nor alloca, diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 5ce27d6c2d..02f27d5e08 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -344,7 +344,9 @@ void AArch64GenProEpilog::GenStackGuard(BB &bb) { cgFunc.GetCurBB()->AppendInsn(insn); uint64 vArea = 0; - if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (cgFunc.GetMirModule().IsCModule() && + cgFunc.GetFunction().GetAttr(FUNCATTR_varargs) && + cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { AArch64MemLayout *ml = static_cast(cgFunc.GetMemlayout()); if (ml->GetSizeOfGRSaveArea() > 0) { vArea += RoundUp(ml->GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); @@ -401,7 +403,9 @@ BB &AArch64GenProEpilog::GenStackGuardCheckInsn(BB &bb) { cgFunc.GetCurBB()->AppendInsn(insn); uint64 vArea = 0; - if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (cgFunc.GetMirModule().IsCModule() && + cgFunc.GetFunction().GetAttr(FUNCATTR_varargs) && + cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { AArch64MemLayout *ml = static_cast(cgFunc.GetMemlayout()); if (ml->GetSizeOfGRSaveArea() > 0) { vArea += RoundUp(ml->GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); @@ -1219,9 +1223,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { Operand &spOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); -#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; -#endif if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; if (isLmbc) { @@ -1279,7 +1281,9 @@ void AArch64GenProEpilog::GeneratePushRegs() { offset -= kAarch64StackPtrAlignment; } - if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (cgFunc.GetMirModule().IsCModule() && + cgFunc.GetFunction().GetAttr(FUNCATTR_varargs) && + cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { /* GR/VR save areas are above the callee save area */ AArch64MemLayout *ml = static_cast(cgFunc.GetMemlayout()); auto saveareasize = static_cast(RoundUp(ml->GetSizeOfGRSaveArea(), kSizeOfPtr * k2BitSize) + @@ -1506,9 +1510,7 @@ void AArch64GenProEpilog::GenerateProlog(BB &bb) { } if (useFP) { Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); -#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; -#endif int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; @@ -1822,7 +1824,8 @@ void AArch64GenProEpilog::GeneratePopRegs() { offset -= kAarch64StackPtrAlignment; } - if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs) && + cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { /* GR/VR save areas are above the callee save area */ AArch64MemLayout *ml = static_cast(cgFunc.GetMemlayout()); auto saveareasize = static_cast(RoundUp(ml->GetSizeOfGRSaveArea(), kSizeOfPtr * k2BitSize) + -- Gitee From f52d220fb39ec8d36a681dcb515e13b5af23be5a Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Thu, 30 Jun 2022 23:04:08 -0700 Subject: [PATCH 071/179] Fixed some errors from rebasing to master --- src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h | 2 +- src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 2 +- src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index f7b6cf6824..b088d90e7b 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -102,7 +102,7 @@ class AArch64CGFunc : public CGFunc { return kRFLAG; } - MIRType *LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList) const; + MIRType *LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList); RegOperand &GetOrCreateResOperand(const BaseNode &parent, PrimType primType); MIRStructType *GetLmbcStructArgType(BaseNode &stmt, int32 argNo); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 309141a2d9..8947c86692 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -2211,7 +2211,7 @@ bool AArch64CGFunc::LmbcSmallAggForRet(BaseNode &bNode, Operand *src) { } /* return true if blkassignoff for return, false otherwise */ -bool AArch64CGFunc::LmbcSmallAggForCall(BlkassignoffNode &bNode, const Operand *src, std::vector **parmList) { +bool AArch64CGFunc::LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src, std::vector **parmList) { AArch64reg regno = static_cast(static_cast(src)->GetRegisterNumber()); if (IsBlkassignForPush(bNode)) { PrimType pTy = PTY_i64; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp index dd216e9c54..f8da94fb8c 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp @@ -1016,7 +1016,7 @@ bool AArch64Ebo::CombineMultiplyNeg(Insn *insn, OpndInfo *opndInfo, bool is64bit return false; } -bool AArch64Ebo::CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp) const { +bool AArch64Ebo::CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp) { if (opndInfo.insn == nullptr) { return false; } -- Gitee From d355c4670fb8785c4f6a80931ea8e96f2fd67dea Mon Sep 17 00:00:00 2001 From: William Chen Date: Wed, 8 Jun 2022 16:21:12 -0700 Subject: [PATCH 072/179] Changes from mplcglmbc10 --- .../include/cg/aarch64/aarch64_cgfunc.h | 9 ++- .../src/cg/aarch64/aarch64_cgfunc.cpp | 58 +++++++++---------- .../src/cg/aarch64/aarch64_color_ra.cpp | 2 +- .../src/cg/aarch64/aarch64_proepilog.cpp | 20 +++---- src/mapleall/maple_be/src/cg/cgfunc.cpp | 15 +++-- src/mapleall/maple_be/src/cg/emit.cpp | 6 +- .../maple_ir/include/bin_mpl_export.h | 1 + src/mapleall/maple_ir/include/mir_type.h | 10 ---- src/mapleall/maple_ir/src/bin_func_export.cpp | 2 +- src/mapleall/maple_ir/src/bin_func_import.cpp | 34 +++++------ src/mapleall/maple_ir/src/bin_mpl_import.cpp | 4 +- src/mapleall/maple_ir/src/mir_lower.cpp | 8 +-- src/mapleall/maple_me/src/irmap_build.cpp | 3 +- src/mapleall/maple_me/src/irmap_emit.cpp | 3 +- .../maple_me/src/me_phase_manager.cpp | 2 +- 15 files changed, 80 insertions(+), 97 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index c17ca31eac..bf154e7657 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -38,7 +38,7 @@ class LmbcArgInfo { MapleVector lmbcCallArgTypes; MapleVector lmbcCallArgOffsets; MapleVector lmbcCallArgNumOfRegs; // # of regs needed to complete struct - uint32 lmbcTotalStkUsed = -1; // remove when explicit addr for large agg is available + uint32 lmbcTotalStkUsed = -1; // TBD: remove when explicit addr for large agg is available }; class AArch64CGFunc : public CGFunc { @@ -129,8 +129,8 @@ class AArch64CGFunc : public CGFunc { uint32 LmbcFindTotalStkUsed(std::vector* paramList); uint32 LmbcTotalRegsUsed(); void LmbcSelectParmList(ListOperand *srcOpnds, bool isArgReturn); - bool LmbcSmallAggForRet(const BlkassignoffNode &bNode, const Operand *src); - bool LmbcSmallAggForCall(BlkassignoffNode &bNode, const Operand *src, std::vector **parmList); + bool LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src); + bool LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src, std::vector **parmList); void SelectAggDassign(DassignNode &stmt) override; void SelectIassign(IassignNode &stmt) override; void SelectIassignoff(IassignoffNode &stmt) override; @@ -492,8 +492,7 @@ class AArch64CGFunc : public CGFunc { void AssignLmbcFormalParams() override; void LmbcGenSaveSpForAlloca() override; MemOperand *GenLmbcFpMemOperand(int32 offset, uint32 byteSize, AArch64reg base = RFP); - RegOperand *GenLmbcParamLoad(int32 offset, uint32 byteSize, RegType regType, - PrimType primType, AArch64reg baseRegno = RFP); + RegOperand *GenLmbcParamLoad(int32 offset, uint32 byteSize, RegType regType, PrimType primType, AArch64reg baseRegno = RFP); RegOperand *LmbcStructReturnLoad(int32 offset); Operand *GetBaseReg(const AArch64SymbolAlloc &symAlloc); int32 GetBaseOffset(const SymbolAlloc &symAlloc) override; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index b9893f7387..3ba48a2cbc 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1987,9 +1987,8 @@ void AArch64CGFunc::SelectIassignfpoff(IassignFPoffNode &stmt, Operand &opnd) { MIRType *rType = GetLmbcCallReturnType(); bool isPureFpStruct = false; uint32 numRegs = 0; - if (rType && rType->GetPrimType() == PTY_agg && opnd.IsRegister() && - static_cast(opnd).IsPhysicalRegister()) { - CHECK_FATAL(rType->GetSize() <= k16BitSize, "SelectIassignfpoff invalid agg size"); + if (rType && rType->GetPrimType() == PTY_agg && opnd.IsRegister() && static_cast(opnd).IsPhysicalRegister()) { + CHECK_FATAL(rType->GetSize() <= 16, "SelectIassignfpoff invalid agg size"); uint32 fpSize; numRegs = FloatParamRegRequired(static_cast(rType), fpSize); if (numRegs) { @@ -2000,8 +1999,8 @@ void AArch64CGFunc::SelectIassignfpoff(IassignFPoffNode &stmt, Operand &opnd) { uint32 byteSize = GetPrimTypeSize(primType); uint32 bitlen = byteSize * kBitsPerByte; if (isPureFpStruct) { - for (uint32 i = 0 ; i < numRegs; ++i) { - MemOperand *memOpnd = GenLmbcFpMemOperand(offset + static_cast(i * byteSize), byteSize); + for (int i = 0 ; i < numRegs; ++i) { + MemOperand *memOpnd = GenLmbcFpMemOperand(offset + (i * byteSize), byteSize); RegOperand &srcOpnd = GetOrCreatePhysicalRegisterOperand(AArch64reg(V0 + i), bitlen, kRegTyFloat); MOperator mOp = PickStInsn(bitlen, primType); Insn &store = GetCG()->BuildInstruction(mOp, srcOpnd, *memOpnd); @@ -2044,8 +2043,8 @@ void AArch64CGFunc::SelectIassignspoff(PrimType pTy, int32 offset, Operand &opnd } /* Search for CALL/ICALL/ICALLPROTO node, must be called from a blkassignoff node */ -MIRType *AArch64CGFunc::LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList) const { - for (; stmt != nullptr; stmt = stmt->GetNext()) { +MIRType *AArch64CGFunc::LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList) { + for ( ; stmt != nullptr; stmt = stmt->GetNext()) { if (stmt->GetOpCode() == OP_call || stmt->GetOpCode() == OP_icallproto) { break; } @@ -2161,7 +2160,7 @@ bool AArch64CGFunc::LmbcSmallAggForCall(BlkassignoffNode &bNode, const Operand * MemOperand &mem = CreateMemOpnd(regno, s, size * kBitsPerByte); RegOperand *res = &CreateVirtualRegisterOperand(NewVReg(kRegTyFloat, size)); SelectCopy(*res, pTy, mem, pTy); - SetLmbcArgInfo(res, pTy, 0, static_cast(fpregs)); + SetLmbcArgInfo(res, pTy, 0, fpregs); IncLmbcArgsInRegs(kRegTyFloat); } IncLmbcTotalArgs(); @@ -2209,7 +2208,7 @@ uint32 AArch64CGFunc::LmbcFindTotalStkUsed(std::vector *paramList) { CCLocInfo pLoc; for (TyIdx tyIdx : *paramList) { MIRType *ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(tyIdx); - (void)parmlocator.LocateNextParm(*ty, pLoc); + parmlocator.LocateNextParm(*ty, pLoc); } return 0; } @@ -2225,12 +2224,12 @@ uint32 AArch64CGFunc::LmbcTotalRegsUsed() { uint32 fCnt = 0; for (uint32 i = 0; i < regs.size(); i++) { if (IsPrimitiveInteger(types[i])) { - if ((iCnt + static_cast(regs[i])) <= k8ByteSize) { - iCnt += static_cast(regs[i]); + if ((iCnt + regs[i]) <= k8ByteSize) { + iCnt += regs[i]; }; } else { - if ((fCnt + static_cast(regs[i])) <= k8ByteSize) { - fCnt += static_cast(regs[i]); + if ((fCnt + regs[i]) <= k8ByteSize) { + fCnt += regs[i]; }; } } @@ -2277,7 +2276,7 @@ void AArch64CGFunc::SelectBlkassignoff(BlkassignoffNode &bNode, Operand *src) opndVec.push_back(regResult); /* result */ opndVec.push_back(PrepareMemcpyParamOpnd(offset, *dest)); /* param 0 */ opndVec.push_back(src); /* param 1 */ - opndVec.push_back(PrepareMemcpyParamOpnd(static_cast(static_cast(bNode.blockSize)))); /* param 2 */ + opndVec.push_back(PrepareMemcpyParamOpnd(bNode.blockSize));/* param 2 */ SelectLibCall("memcpy", opndVec, PTY_a64, PTY_a64); } @@ -2681,7 +2680,7 @@ void AArch64CGFunc::SelectReturnSendOfStructInRegs(BaseNode *x) { /* generate move to regs for agg return */ AArch64CallConvImpl parmlocator(GetBecommon()); CCLocInfo pLoc; - (void)parmlocator.LocateNextParm(*mirType, pLoc, true, GetBecommon().GetMIRModule().CurFunction()); + parmlocator.LocateNextParm(*mirType, pLoc, true, GetBecommon().GetMIRModule().CurFunction()); /* aggregates are 8 byte aligned. */ Operand *rhsmemopnd = nullptr; RegOperand *result[kFourRegister]; /* up to 2 int or 4 fp */ @@ -3203,8 +3202,8 @@ RegOperand *AArch64CGFunc::LmbcStructReturnLoad(int32 offset) { if (numFpRegs > 0) { PrimType pType = (fpSize <= k4ByteSize) ? PTY_f32 : PTY_f64; for (int32 i = (numFpRegs - kOneRegister); i > 0; --i) { - result = GenLmbcParamLoad(offset + (i * static_cast(fpSize)), fpSize, kRegTyFloat, pType); - AArch64reg regNo = static_cast(V0 + static_cast(i)); + result = GenLmbcParamLoad(offset + (i * fpSize), fpSize, kRegTyFloat, pType); + AArch64reg regNo = static_cast(V0 + i); RegOperand *reg = &GetOrCreatePhysicalRegisterOperand(regNo, fpSize * kBitsPerByte, kRegTyFloat); SelectCopy(*reg, pType, *result, pType); Insn &pseudo = GetCG()->BuildInstruction(MOP_pseudo_ret_float, *reg); @@ -3216,7 +3215,7 @@ RegOperand *AArch64CGFunc::LmbcStructReturnLoad(int32 offset) { } else if (sz <= k8ByteSize) { result = GenLmbcParamLoad(offset, k8ByteSize, kRegTyInt, PTY_i64); } else if (sz <= k16ByteSize) { - result = GenLmbcParamLoad(offset + k8ByteSizeInt, k8ByteSize, kRegTyInt, PTY_i64); + result = GenLmbcParamLoad(offset + k8ByteSize, k8ByteSize, kRegTyInt, PTY_i64); RegOperand *r1 = &GetOrCreatePhysicalRegisterOperand(R1, k8ByteSize * kBitsPerByte, kRegTyInt); SelectCopy(*r1, PTY_i64, *result, PTY_i64); Insn &pseudo = GetCG()->BuildInstruction(MOP_pseudo_ret_int, *r1); @@ -3239,8 +3238,7 @@ Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode if (info->IsOnStack()) { result = GenLmbcParamLoad(info->GetOnStackOffset(), GetPrimTypeSize(PTY_a64), kRegTyInt, PTY_a64); regno_t baseRegno = result->GetRegisterNumber(); - result = GenLmbcParamLoad(offset - static_cast(info->GetOffset()), - bytelen, regty, primType, (AArch64reg)baseRegno); + result = GenLmbcParamLoad(offset - info->GetOffset(), bytelen, regty, primType, (AArch64reg)baseRegno); } else if (primType == PTY_agg) { CHECK_FATAL(parent.GetOpCode() == OP_regassign, "SelectIreadfpoff of agg"); result = LmbcStructReturnLoad(offset); @@ -6542,10 +6540,10 @@ void AArch64CGFunc::AssignLmbcFormalParams() { param->SetRegNO(0); } else { param->SetRegNO(fpReg); - if (!param->HasRegassign()) { + if (param->HasRegassign() == false) { uint32 bytelen = GetPrimTypeSize(primType); uint32 bitlen = bytelen * kBitsPerByte; - MemOperand *mOpnd = GenLmbcFpMemOperand(static_cast(offset), bytelen); + MemOperand *mOpnd = GenLmbcFpMemOperand(offset, bytelen); RegOperand &src = GetOrCreatePhysicalRegisterOperand(AArch64reg(fpReg), bitlen, kRegTyFloat); MOperator mOp = PickStInsn(bitlen, primType); Insn &store = GetCG()->BuildInstruction(mOp, src, *mOpnd); @@ -6569,10 +6567,10 @@ void AArch64CGFunc::AssignLmbcFormalParams() { } else { param->SetRegNO(intReg); param->SetIsOnStack(); - param->SetOnStackOffset(((intReg - R0 + fpReg) - V0) * k8ByteSize); + param->SetOnStackOffset((intReg - R0 + fpReg - V0) * k8ByteSize); uint32 bytelen = GetPrimTypeSize(PTY_a64); uint32 bitlen = bytelen * kBitsPerByte; - MemOperand *mOpnd = GenLmbcFpMemOperand(static_cast(param->GetOnStackOffset()), bytelen); + MemOperand *mOpnd = GenLmbcFpMemOperand(param->GetOnStackOffset(), bytelen); RegOperand &src = GetOrCreatePhysicalRegisterOperand(AArch64reg(intReg), bitlen, kRegTyInt); MOperator mOp = PickStInsn(bitlen, PTY_a64); Insn &store = GetCG()->BuildInstruction(mOp, src, *mOpnd); @@ -6631,13 +6629,14 @@ void AArch64CGFunc::AssignLmbcFormalParams() { } void AArch64CGFunc::LmbcGenSaveSpForAlloca() { - if (GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc || !HasVLAOrAlloca()) { + if (GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc || HasVLAOrAlloca() == false) { return; } Operand &spOpnd = GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); RegOperand &spSaveOpnd = CreateVirtualRegisterOperand(NewVReg(kRegTyInt, kSizeOfPtr)); Insn &save = GetCG()->BuildInstruction(MOP_xmovrr, spSaveOpnd, spOpnd); GetFirstBB()->AppendInsn(save); + //save.SetFrameDef(true); for (auto *retBB : GetExitBBsVec()) { Insn &restore = GetCG()->BuildInstruction(MOP_xmovrr, spOpnd, spSaveOpnd); retBB->AppendInsn(restore); @@ -7952,8 +7951,7 @@ size_t AArch64CGFunc::SelectParmListGetStructReturnSize(StmtNode &naryNode) { } } else if (naryNode.GetOpCode() == OP_icallproto) { IcallNode &icallProto = static_cast(naryNode); - MIRFuncType *funcTy = static_cast( - GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallProto.GetRetTyIdx())); + MIRFuncType *funcTy = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallProto.GetRetTyIdx())); if (funcTy->FirstArgReturn()) { MIRType *ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(funcTy->GetNthParamType(0)); return GetBecommon().GetTypeSize(static_cast(ty)->GetPointedTyIdx()); @@ -8080,8 +8078,7 @@ void AArch64CGFunc::SelectParmList(StmtNode &naryNode, ListOperand &srcOpnds, bo firstArgReturn = callee->IsFirstArgReturn(); } else if (naryNode.GetOpCode() == OP_icallproto) { IcallNode *icallnode = &static_cast(naryNode); - MIRFuncType *funcType = static_cast( - GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallnode->GetRetTyIdx())); + MIRFuncType *funcType = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallnode->GetRetTyIdx())); firstArgReturn = funcType->FirstArgReturn(); } BB *curBBrecord = GetCurBB(); @@ -8630,8 +8627,7 @@ void AArch64CGFunc::SelectCall(CallNode &callNode) { SetLmbcCallReturnType(nullptr); bool largeStructRet = false; if (fn->IsFirstArgReturn()) { - MIRPtrType *ptrTy = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx( - fn->GetFormalDefVec()[0].formalTyIdx)); + MIRPtrType *ptrTy = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(fn->GetFormalDefVec()[0].formalTyIdx)); MIRType *sTy = GlobalTables::GetTypeTable().GetTypeFromTyIdx(ptrTy->GetPointedTyIdx()); largeStructRet = sTy->GetSize() > k16ByteSize; SetLmbcCallReturnType(sTy); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp index a01201e55a..e7f80e2a4b 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp @@ -4979,7 +4979,7 @@ bool GraphColorRegAllocator::AllocateRegisters() { MarkCalleeSaveRegs(); - if (!seenFP) { + if (seenFP == false) { cgFunc->UnsetSeenFP(); } if (GCRA_DUMP) { diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 5674b9107f..546c386c7e 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -1226,7 +1226,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { } else { immOpnd = &aarchCGFunc.CreateImmOperand(argsToStkPassSize, k32BitSize, true); } - if (!isLmbc || cgFunc.SeenFP() || cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (isLmbc == false || cgFunc.SeenFP() || cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { aarchCGFunc.SelectAdd(fpOpnd, spOpnd, *immOpnd, PTY_u64); } cgFunc.GetCurBB()->GetLastInsn()->SetFrameDef(true); @@ -1256,11 +1256,11 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { - offset = static_cast((memLayout->RealStackFrameSize() - - aarchCGFunc.SizeOfCalleeSaved()) - memLayout->GetSizeOfLocals()); + offset = static_cast(memLayout->RealStackFrameSize() - + aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); } else { - offset = (static_cast(memLayout->RealStackFrameSize() - - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - /* for FP/LR */ + offset = static_cast(memLayout->RealStackFrameSize() - + (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass()); } @@ -1685,7 +1685,7 @@ void AArch64GenProEpilog::AppendInstructionDeallocateCallFrameDebug(AArch64reg r bool isLmbc = (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc); if (cgFunc.HasVLAOrAlloca() || argsToStkPassSize == 0 || isLmbc) { int lmbcOffset = 0; - if (!isLmbc) { + if (isLmbc == false) { stackFrameSize -= argsToStkPassSize; } else { lmbcOffset = argsToStkPassSize - (kDivide2 * k8ByteSize); @@ -1770,11 +1770,11 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { - offset = static_cast((memLayout->RealStackFrameSize() - - aarchCGFunc.SizeOfCalleeSaved()) - memLayout->GetSizeOfLocals()); + offset = static_cast(memLayout->RealStackFrameSize() - + aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); } else { - offset = (static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - /* for FP/LR */ + offset = static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - + (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass(); } diff --git a/src/mapleall/maple_be/src/cg/cgfunc.cpp b/src/mapleall/maple_be/src/cg/cgfunc.cpp index 15ee3eeb3a..5b84a5d8b7 100644 --- a/src/mapleall/maple_be/src/cg/cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/cgfunc.cpp @@ -1565,16 +1565,16 @@ void CGFunc::CreateLmbcFormalParamInfo() { PrimType primType; uint32 offset; uint32 typeSize; - MIRFunction &lmbcFunc = GetFunction(); - if (lmbcFunc.GetFormalCount() > 0) { + MIRFunction &func = GetFunction(); + if (func.GetFormalCount() > 0) { /* Whenever lmbc cannot delete call type info, the prototype is available */ uint32 stackOffset = 0; - for (size_t idx = 0; idx < lmbcFunc.GetFormalCount(); ++idx) { - MIRSymbol *sym = lmbcFunc.GetFormal(idx); + for (size_t idx = 0; idx < func.GetFormalCount(); ++idx) { + MIRSymbol *sym = func.GetFormal(idx); MIRType *type; TyIdx tyIdx; if (sym) { - tyIdx = lmbcFunc.GetFormalDefVec()[idx].formalTyIdx; + tyIdx = func.GetFormalDefVec()[idx].formalTyIdx; type = GlobalTables::GetTypeTable().GetTypeFromTyIdx(tyIdx); } else { FormalDef vec = const_cast(GetBecommon().GetMIRModule().CurFunction())->GetFormalDefAt(idx); @@ -1637,7 +1637,7 @@ void CGFunc::CreateLmbcFormalParamInfo() { ); /* When a scalar param address is taken, its regassign is not in the 1st block */ - for (StmtNode *stmt = lmbcFunc.GetBody()->GetFirst(); stmt != nullptr; stmt = stmt->GetNext()) { + for (StmtNode *stmt = func.GetBody()->GetFirst(); stmt != nullptr; stmt = stmt->GetNext()) { if (stmt == nullptr) { break; } @@ -1656,8 +1656,7 @@ void CGFunc::CreateLmbcFormalParamInfo() { if (ireadNode->GetOffset() < 0) { continue; } - LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(static_cast(ireadNode->GetOffset())); - ASSERT_NOT_NULL(info); + LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(ireadNode->GetOffset()); info->SetHasRegassign(); } diff --git a/src/mapleall/maple_be/src/cg/emit.cpp b/src/mapleall/maple_be/src/cg/emit.cpp index cdbd69a491..081c098ba0 100644 --- a/src/mapleall/maple_be/src/cg/emit.cpp +++ b/src/mapleall/maple_be/src/cg/emit.cpp @@ -2170,9 +2170,9 @@ void Emitter::EmitGlobalVar(const MIRSymbol &globalVar) { void Emitter::EmitGlobalVars(std::vector> &globalVars) { if (GetCG()->IsLmbc() && GetCG()->GetGP() != nullptr) { - (void)Emit(asmInfo->GetLocal()).Emit("\t").Emit(GetCG()->GetGP()->GetName()).Emit("\n"); - (void)Emit(asmInfo->GetComm()).Emit("\t").Emit(GetCG()->GetGP()->GetName()); - (void)Emit(", ").Emit(GetCG()->GetMIRModule()->GetGlobalMemSize()).Emit(", ").Emit("8\n"); + Emit(asmInfo->GetLocal()).Emit("\t").Emit(GetCG()->GetGP()->GetName()).Emit("\n"); + Emit(asmInfo->GetComm()).Emit("\t").Emit(GetCG()->GetGP()->GetName()); + Emit(", ").Emit(GetCG()->GetMIRModule()->GetGlobalMemSize()).Emit(", ").Emit("8\n"); } /* load globalVars profile */ if (globalVars.empty()) { diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 918c8e04eb..9cada84eb4 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,6 +181,7 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; + MIRFunction *curFunc = nullptr; size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; diff --git a/src/mapleall/maple_ir/include/mir_type.h b/src/mapleall/maple_ir/include/mir_type.h index b8724b2d7e..fda53fe94b 100644 --- a/src/mapleall/maple_ir/include/mir_type.h +++ b/src/mapleall/maple_ir/include/mir_type.h @@ -1205,14 +1205,6 @@ class MIRStructType : public MIRType { isImported = flag; } - bool IsUsed() const { - return isUsed; - } - - void SetIsUsed(bool flag) { - isUsed = flag; - } - bool IsCPlusPlus() const { return isCPlusPlus; } @@ -1384,7 +1376,6 @@ class MIRStructType : public MIRType { vTableMethods.clear(); iTableMethods.clear(); isImported = false; - isUsed = false; hasVolatileField = false; hasVolatileFieldSet = false; } @@ -1487,7 +1478,6 @@ class MIRStructType : public MIRType { // implementation functions, For interfaces, they are abstact functions. // Weak indicates the actual definition is in another module. bool isImported = false; - bool isUsed = false; bool isCPlusPlus = false; // empty struct in C++ has size 1 byte mutable bool hasVolatileField = false; // for caching computed value mutable bool hasVolatileFieldSet = false; // if true, just read hasVolatileField; diff --git a/src/mapleall/maple_ir/src/bin_func_export.cpp b/src/mapleall/maple_ir/src/bin_func_export.cpp index 2015da5d32..a9e8a10e60 100644 --- a/src/mapleall/maple_ir/src/bin_func_export.cpp +++ b/src/mapleall/maple_ir/src/bin_func_export.cpp @@ -87,7 +87,7 @@ void BinaryMplExport::OutputLocalSymbol(MIRSymbol *sym) { void BinaryMplExport::OutputPreg(MIRPreg *preg) { if (preg->GetPregNo() < 0) { WriteNum(kBinSpecialReg); - Write(static_cast(-preg->GetPregNo())); + Write(-preg->GetPregNo()); return; } std::unordered_map::iterator it = localPregMark.find(preg); diff --git a/src/mapleall/maple_ir/src/bin_func_import.cpp b/src/mapleall/maple_ir/src/bin_func_import.cpp index e815c828b8..580d52abc4 100644 --- a/src/mapleall/maple_ir/src/bin_func_import.cpp +++ b/src/mapleall/maple_ir/src/bin_func_import.cpp @@ -50,8 +50,8 @@ void BinaryMplImport::ImportFuncIdInfo(MIRFunction *func) { } void BinaryMplImport::ImportBaseNode(Opcode &o, PrimType &typ) { - o = static_cast(Read()); - typ = static_cast(Read()); + o = (Opcode)Read(); + typ = (PrimType)Read(); } MIRSymbol *BinaryMplImport::ImportLocalSymbol(MIRFunction *func) { @@ -61,8 +61,8 @@ MIRSymbol *BinaryMplImport::ImportLocalSymbol(MIRFunction *func) { } if (tag < 0) { CHECK_FATAL(static_cast(-tag) < localSymTab.size(), "index out of bounds"); - return localSymTab.at(static_cast(-tag)); - } + return localSymTab.at(-tag); + } CHECK_FATAL(tag == kBinSymbol, "expecting kBinSymbol in ImportLocalSymbol()"); MIRSymbol *sym = func->GetSymTab()->CreateSymbol(kScopeLocal); localSymTab.push_back(sym); @@ -99,11 +99,11 @@ PregIdx BinaryMplImport::ImportPreg(MIRFunction *func) { } if (tag < 0) { CHECK_FATAL(static_cast(-tag) < localPregTab.size(), "index out of bounds"); - return localPregTab.at(static_cast(-tag)); + return localPregTab.at(-tag); } CHECK_FATAL(tag == kBinPreg, "expecting kBinPreg in ImportPreg()"); - PrimType primType = static_cast(Read()); + PrimType primType = (PrimType)Read(); PregIdx pidx = func->GetPregTab()->CreatePreg(primType); localPregTab.push_back(pidx); return pidx; @@ -116,7 +116,7 @@ LabelIdx BinaryMplImport::ImportLabel(MIRFunction *func) { } if (tag < 0) { CHECK_FATAL(static_cast(-tag) < localLabelTab.size(), "index out of bounds"); - return localLabelTab.at(static_cast(-tag)); + return localLabelTab.at(-tag); } CHECK_FATAL(tag == kBinLabel, "kBinLabel expected in ImportLabel()"); @@ -266,8 +266,8 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { case OP_floor: case OP_trunc: { TypeCvtNode *typecvtNode = mod.CurFuncCodeMemPool()->New(op, typ); - typecvtNode->SetFromType(static_cast(Read())); - typecvtNode->SetOpnd(ImportExpression(func), kFirstOpnd); + typecvtNode->SetFromType((PrimType)Read()); + typecvtNode->SetOpnd(ImportExpression(func), 0); return typecvtNode; } case OP_retype: { @@ -306,10 +306,10 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { } case OP_depositbits: { DepositbitsNode *dbNode = mod.CurFuncCodeMemPool()->New(op, typ); - dbNode->SetBitsOffset(static_cast(ReadNum())); - dbNode->SetBitsSize(static_cast(ReadNum())); - dbNode->SetOpnd(ImportExpression(func), kFirstOpnd); - dbNode->SetOpnd(ImportExpression(func), kSecondOpnd); + dbNode->SetBitsOffset(ReadNum()); + dbNode->SetBitsSize(ReadNum()); + dbNode->SetOpnd(ImportExpression(func), 0); + dbNode->SetOpnd(ImportExpression(func), 1); return dbNode; } case OP_gcmallocjarray: @@ -352,9 +352,9 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { case OP_cmpl: case OP_cmp: { CompareNode *cmpNode = mod.CurFuncCodeMemPool()->New(op, typ); - cmpNode->SetOpndType(static_cast(Read())); - cmpNode->SetOpnd(ImportExpression(func), kFirstOpnd); - cmpNode->SetOpnd(ImportExpression(func), kSecondOpnd); + cmpNode->SetOpndType((PrimType)Read()); + cmpNode->SetOpnd(ImportExpression(func), 0); + cmpNode->SetOpnd(ImportExpression(func), 1); return cmpNode; } case OP_resolveinterfacefunc: @@ -526,7 +526,7 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { case OP_iassignspoff: case OP_iassignfpoff: { IassignFPoffNode *s = func->GetCodeMemPool()->New(op); - s->SetPrimType(static_cast(Read())); + s->SetPrimType((PrimType)Read()); s->SetOffset(static_cast(ReadNum())); s->SetOpnd(ImportExpression(func), kFirstOpnd); stmt = s; diff --git a/src/mapleall/maple_ir/src/bin_mpl_import.cpp b/src/mapleall/maple_ir/src/bin_mpl_import.cpp index ddd38f6014..cc7bd4a2c1 100644 --- a/src/mapleall/maple_ir/src/bin_mpl_import.cpp +++ b/src/mapleall/maple_ir/src/bin_mpl_import.cpp @@ -543,7 +543,7 @@ TyIdx BinaryMplImport::ImportType(bool forPointedType) { CHECK_FATAL(static_cast(-tag) < typTab.size(), "index out of bounds"); return typTab.at(static_cast(-tag)); } - PrimType primType = static_cast(0); + PrimType primType = (PrimType)0; GStrIdx strIdx(0); bool nameIsLocal = false; ImportTypeBase(primType, strIdx, nameIsLocal); @@ -719,7 +719,7 @@ TyIdx BinaryMplImport::ImportTypeNonJava() { CHECK_FATAL(static_cast(-tag) < typTab.size(), "index out of bounds"); return typTab[static_cast(-tag)]; } - PrimType primType = static_cast(0); + PrimType primType = (PrimType)0; GStrIdx strIdx(0); bool nameIsLocal = false; ImportTypeBase(primType, strIdx, nameIsLocal); diff --git a/src/mapleall/maple_ir/src/mir_lower.cpp b/src/mapleall/maple_ir/src/mir_lower.cpp index ce085e6d1a..ddb4827535 100644 --- a/src/mapleall/maple_ir/src/mir_lower.cpp +++ b/src/mapleall/maple_ir/src/mir_lower.cpp @@ -554,7 +554,7 @@ BlockNode *MIRLower::LowerBlock(BlockNode &block) { CHECK_FATAL(funcType != nullptr, "MIRLower::LowerBlock: cannot find prototype for icall"); ic->SetRetTyIdx(funcType->GetTypeIndex()); MIRType *retType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(funcType->GetRetTyIdx()); - if (retType->GetPrimType() == PTY_agg && retType->GetSize() > k16BitSize) { + if (retType->GetPrimType() == PTY_agg && retType->GetSize() > 16) { funcType->funcAttrs.SetAttr(FUNCATTR_firstarg_return); } } @@ -1093,14 +1093,14 @@ MIRFuncType *MIRLower::FuncTypeFromFuncPtrExpr(BaseNode *x) { res = static_cast(mirType)->GetPointedFuncType(); } if (res == nullptr) { - res = FuncTypeFromFuncPtrExpr(x->Opnd(kNodeFirstOpnd)); + res = FuncTypeFromFuncPtrExpr(x->Opnd(0)); } break; } case OP_select: { - res = FuncTypeFromFuncPtrExpr(x->Opnd(kNodeSecondOpnd)); + res = FuncTypeFromFuncPtrExpr(x->Opnd(1)); if (res == nullptr) { - res = FuncTypeFromFuncPtrExpr(x->Opnd(kNodeThirdOpnd)); + res = FuncTypeFromFuncPtrExpr(x->Opnd(2)); } break; } diff --git a/src/mapleall/maple_me/src/irmap_build.cpp b/src/mapleall/maple_me/src/irmap_build.cpp index 6fd82f8500..bebf1facb0 100755 --- a/src/mapleall/maple_me/src/irmap_build.cpp +++ b/src/mapleall/maple_me/src/irmap_build.cpp @@ -808,8 +808,7 @@ MeStmt *IRMapBuild::BuildCallMeStmt(StmtNode &stmt, AccessSSANodes &ssaPart) { MeStmt *IRMapBuild::BuildNaryMeStmt(StmtNode &stmt, AccessSSANodes &ssaPart) { Opcode op = stmt.GetOpCode(); - NaryMeStmt *naryMeStmt = (op == OP_icall || op == OP_icallassigned || - op == OP_icallproto || op == OP_icallprotoassigned) + NaryMeStmt *naryMeStmt = (op == OP_icall || op == OP_icallassigned || op == OP_icallproto || op == OP_icallprotoassigned) ? static_cast(irMap->NewInPool(&stmt)) : static_cast(irMap->NewInPool(&stmt)); auto &naryStmtNode = static_cast(stmt); diff --git a/src/mapleall/maple_me/src/irmap_emit.cpp b/src/mapleall/maple_me/src/irmap_emit.cpp index 9cab595c5d..d6ca21e189 100755 --- a/src/mapleall/maple_me/src/irmap_emit.cpp +++ b/src/mapleall/maple_me/src/irmap_emit.cpp @@ -412,8 +412,7 @@ MIRFunction &CallMeStmt::GetTargetFunction() { } StmtNode &CallMeStmt::EmitStmt(SSATab &ssaTab) { - if (GetOp() != OP_icall && GetOp() != OP_icallassigned && - GetOp() != OP_icallproto && GetOp() != OP_icallprotoassigned) { + if (GetOp() != OP_icall && GetOp() != OP_icallassigned && GetOp() != OP_icallproto && GetOp() != OP_icallprotoassigned) { auto *callNode = ssaTab.GetModule().CurFunction()->GetCodeMempool()->New(ssaTab.GetModule(), Opcode(GetOp())); callNode->SetPUIdx(puIdx); diff --git a/src/mapleall/maple_me/src/me_phase_manager.cpp b/src/mapleall/maple_me/src/me_phase_manager.cpp index eef57b0aeb..a0b5419a8e 100644 --- a/src/mapleall/maple_me/src/me_phase_manager.cpp +++ b/src/mapleall/maple_me/src/me_phase_manager.cpp @@ -160,7 +160,7 @@ bool MeFuncPM::PhaseRun(maple::MIRModule &m) { func->SetFrameSize(localMemLayout.StackFrameSize()); memPoolCtrler.DeleteMemPool(layoutMp); } - globalMemLayout.seg_GPbased.size = maplebe::RoundUp(static_cast(globalMemLayout.seg_GPbased.size), GetPrimTypeSize(PTY_ptr)); + globalMemLayout.seg_GPbased.size = maplebe::RoundUp(globalMemLayout.seg_GPbased.size, GetPrimTypeSize(PTY_ptr)); m.SetGlobalMemSize(globalMemLayout.seg_GPbased.size); // output .lmbc BinaryMplt binMplt(m); -- Gitee From 297bc340ad0cefbc73e8cffc264cb73e8c543eb3 Mon Sep 17 00:00:00 2001 From: William Chen Date: Thu, 9 Jun 2022 15:13:55 -0700 Subject: [PATCH 073/179] Enhance ebo for extension to and 0xff 0xffff optimization --- .../maple_be/include/cg/aarch64/aarch64_ebo.h | 3 +- .../maple_be/src/cg/aarch64/aarch64_ebo.cpp | 62 +++++++++++++------ 2 files changed, 44 insertions(+), 21 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h index dc05b9c5f7..c6d5622597 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h @@ -83,7 +83,8 @@ class AArch64Ebo : public Ebo { bool SimplifyBothConst(BB &bb, Insn &insn, const ImmOperand &immOperand0, const ImmOperand &immOperand1, uint32 opndSize) const; AArch64CC_t GetReverseCond(const CondOperand &cond) const; - bool CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp) const; + bool CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp); + bool CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp, int64 immVal); }; } /* namespace maplebe */ diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp index 2c46f73631..7d298882ab 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp @@ -1058,6 +1058,38 @@ bool AArch64Ebo::CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi return false; } +bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp, int64 immVal) { + if (opndInfo.insn == nullptr) { + return false; + } + if (!cgFunc->GetMirModule().IsCModule()) { + return false; + } + Insn *prevInsn = opndInfo.insn; + InsnInfo *insnInfo = opndInfo.insnInfo; + if (insnInfo == nullptr) { + return false; + } + CHECK_NULL_FATAL(insnInfo); + MOperator opc1 = prevInsn->GetMachineOpcode(); + if (!isFp && + (((immVal == 0xff) && + (opc1 >= MOP_xsxtb32) && (opc1 <= MOP_xuxtw64)) || + ((immVal == 0xffff) && + (opc1 == MOP_xsxth32 || opc1 == MOP_xsxth64 || opc1 == MOP_xsxtw64 || + opc1 == MOP_xsxth32 || opc1 == MOP_xsxtw64)))) { + /* don't use register if it was redefined. */ + OpndInfo *opndInfo1 = insnInfo->origOpnd[kInsnSecondOpnd]; + if ((opndInfo1 != nullptr) && opndInfo1->redefined) { + return false; + } + Operand &opnd1 = prevInsn->GetOperand(kInsnSecondOpnd); + insn.SetOperand(kInsnSecondOpnd, opnd1); + return true; + } + return false; +} + /* Do some special pattern */ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origInfos) { MOperator opCode = insn.GetMachineOpcode(); @@ -1104,10 +1136,12 @@ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origI * ===> ldrb x1, [] ===> ldrb x1, [] ===> ldrsb x1, [] ===> no change * mov x1, x1 mov x1, x1 mov x1, x1 */ - case MOP_wandrri12: { + case MOP_wandrri12: + case MOP_xandrri13: { + bool is64Bits = (opCode == MOP_xandrri13); bool doAndOpt = false; if (static_cast(insn.GetOperand(kInsnThirdOpnd)).GetValue() == 0xff) { - doAndOpt = CombineExtensionAndLoad(&insn, origInfos, AND, false); + doAndOpt = CombineExtensionAndLoad(&insn, origInfos, AND, is64Bits); } if (doAndOpt) { return doAndOpt; @@ -1122,29 +1156,17 @@ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origI (static_cast(immValue) & (static_cast(immValue) + 1)) == 0) { /* immValue is (1 << n - 1) */ OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); - return CombineLsrAnd(insn, *opndInfo, false, false); - } - break; - } - case MOP_xandrri13: { - bool doAndOpt = false; - if (static_cast(insn.GetOperand(kInsnThirdOpnd)).GetValue() == 0xff) { - doAndOpt = CombineExtensionAndLoad(&insn, origInfos, AND, true); - } - if (doAndOpt) { - return doAndOpt; + return CombineLsrAnd(insn, *opndInfo, is64Bits, false); } /* - * lsr d0, d1, #6 - * and d0, d0, #1 - * ===> ubfx d0, d1, #6, #1 + * extension dest, src0 + * and dest, dest, 0xff or 0xffff + * ===> if extension is >= imm then can eliminate extension */ - int64 immValue = static_cast(insn.GetOperand(kInsnThirdOpnd)).GetValue(); - if (!beforeRegAlloc && immValue != 0 && + if (beforeRegAlloc && immValue != 0 && (static_cast(immValue) & (static_cast(immValue) + 1)) == 0) { - /* immValue is (1 << n - 1) */ OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); - return CombineLsrAnd(insn, *opndInfo, true, false); + return CombineExtAnd(insn, *opndInfo, is64Bits, false, immValue); } break; } -- Gitee From c30304d3c72919300d4297b73d665eb4ba5526ff Mon Sep 17 00:00:00 2001 From: William Chen Date: Thu, 9 Jun 2022 16:33:38 -0700 Subject: [PATCH 074/179] Enhance ebo for back to back and optimization --- .../maple_be/src/cg/aarch64/aarch64_ebo.cpp | 44 ++++++++++++------- 1 file changed, 29 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp index 7d298882ab..dd216e9c54 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp @@ -1058,11 +1058,17 @@ bool AArch64Ebo::CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi return false; } +/* + * extension dest, src0 + * and dest, dest, 0xff or 0xffff + * ===> if extension is >= imm then can eliminate extension + * + * and dst1, src0, imm1 + * and dst2, dst1, imm2 where imm2 is 0xff or 0xffff + * ===> and dst2, src0, imm1 if imm1 <= imm2 + */ bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp, int64 immVal) { - if (opndInfo.insn == nullptr) { - return false; - } - if (!cgFunc->GetMirModule().IsCModule()) { + if (isFp || opndInfo.insn == nullptr || !cgFunc->GetMirModule().IsCModule()) { return false; } Insn *prevInsn = opndInfo.insn; @@ -1072,12 +1078,11 @@ bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi } CHECK_NULL_FATAL(insnInfo); MOperator opc1 = prevInsn->GetMachineOpcode(); - if (!isFp && - (((immVal == 0xff) && - (opc1 >= MOP_xsxtb32) && (opc1 <= MOP_xuxtw64)) || - ((immVal == 0xffff) && - (opc1 == MOP_xsxth32 || opc1 == MOP_xsxth64 || opc1 == MOP_xsxtw64 || - opc1 == MOP_xsxth32 || opc1 == MOP_xsxtw64)))) { + if (((immVal == 0xff) && + (opc1 >= MOP_xsxtb32) && (opc1 <= MOP_xuxtw64)) || + ((immVal == 0xffff) && + (opc1 == MOP_xsxth32 || opc1 == MOP_xsxth64 || opc1 == MOP_xsxtw64 || + opc1 == MOP_xsxth32 || opc1 == MOP_xsxtw64))) { /* don't use register if it was redefined. */ OpndInfo *opndInfo1 = insnInfo->origOpnd[kInsnSecondOpnd]; if ((opndInfo1 != nullptr) && opndInfo1->redefined) { @@ -1087,6 +1092,20 @@ bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi insn.SetOperand(kInsnSecondOpnd, opnd1); return true; } + if ((immVal == 0xff || immVal == 0xffff) && (opc1 == MOP_wandrri12 || opc1 == MOP_xandrri13)) { + OpndInfo *opndInfo1 = insnInfo->origOpnd[kInsnSecondOpnd]; + if ((opndInfo1 != nullptr) && opndInfo1->redefined) { + return false; + } + int64 prevImmVal = static_cast(prevInsn->GetOperand(kInsnThirdOpnd)).GetValue(); + if (prevImmVal > immVal) { + return false; + } + Operand &opnd1 = prevInsn->GetOperand(kInsnSecondOpnd); + insn.SetOperand(kInsnSecondOpnd, opnd1); + Operand &opnd2 = prevInsn->GetOperand(kInsnThirdOpnd); + insn.SetOperand(kInsnThirdOpnd, opnd2); + } return false; } @@ -1158,11 +1177,6 @@ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origI OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); return CombineLsrAnd(insn, *opndInfo, is64Bits, false); } - /* - * extension dest, src0 - * and dest, dest, 0xff or 0xffff - * ===> if extension is >= imm then can eliminate extension - */ if (beforeRegAlloc && immValue != 0 && (static_cast(immValue) & (static_cast(immValue) + 1)) == 0) { OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); -- Gitee From 5f50709ae26a965baefc9758e08d0ad8c15758fa Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:15:50 -0700 Subject: [PATCH 075/179] Turn off rematerialization for lmbc --- .../src/cg/aarch64/aarch64_color_ra.cpp | 20 +++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp index e7f80e2a4b..04aa668e5f 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp @@ -455,14 +455,18 @@ void GraphColorRegAllocator::CalculatePriority(LiveRange &lr) const { auto *a64CGFunc = static_cast(cgFunc); CG *cg = a64CGFunc->GetCG(); - if (cg->GetRematLevel() >= rematConst && lr.IsRematerializable(*a64CGFunc, rematConst)) { - lr.SetRematLevel(rematConst); - } else if (cg->GetRematLevel() >= rematAddr && lr.IsRematerializable(*a64CGFunc, rematAddr)) { - lr.SetRematLevel(rematAddr); - } else if (cg->GetRematLevel() >= rematDreadLocal && lr.IsRematerializable(*a64CGFunc, rematDreadLocal)) { - lr.SetRematLevel(rematDreadLocal); - } else if (cg->GetRematLevel() >= rematDreadGlobal && lr.IsRematerializable(*a64CGFunc, rematDreadGlobal)) { - lr.SetRematLevel(rematDreadGlobal); + if (cgFunc->GetCG()->IsLmbc()) { + lr.SetRematLevel(rematOff); + } else { + if (cg->GetRematLevel() >= rematConst && lr.IsRematerializable(*a64CGFunc, rematConst)) { + lr.SetRematLevel(rematConst); + } else if (cg->GetRematLevel() >= rematAddr && lr.IsRematerializable(*a64CGFunc, rematAddr)) { + lr.SetRematLevel(rematAddr); + } else if (cg->GetRematLevel() >= rematDreadLocal && lr.IsRematerializable(*a64CGFunc, rematDreadLocal)) { + lr.SetRematLevel(rematDreadLocal); + } else if (cg->GetRematLevel() >= rematDreadGlobal && lr.IsRematerializable(*a64CGFunc, rematDreadGlobal)) { + lr.SetRematLevel(rematDreadGlobal); + } } auto calculatePriorityFunc = [&lr, &bbNum, &numDefs, &numUses, &pri, this] (uint32 bbID) { -- Gitee From 21964888589166494608cd29d00c8648eabf3b23 Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:16:12 -0700 Subject: [PATCH 076/179] Turn on globalopt for lmbc, but leave SSA opt off --- .../include/cg/aarch64/aarch64_phases.def | 12 ++++-------- src/mapleall/maple_be/include/cg/reaching.h | 1 + .../maple_be/src/cg/aarch64/aarch64_global.cpp | 4 +++- .../src/cg/aarch64/aarch64_reaching.cpp | 18 ++++++++++++++++++ src/mapleall/maple_be/src/cg/reaching.cpp | 1 + 5 files changed, 27 insertions(+), 9 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index ff08e81852..5595b17c0c 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -36,10 +36,8 @@ ADDTARGETPHASE("ico", CGOptions::DoICO()) ADDTARGETPHASE("cfgo", !GetMIRModule()->IsCModule() && CGOptions::DoCFGO()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); - ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); - } + ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); + ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); ADDTARGETPHASE("clearrdinfo", (CGOptions::DoStoreLoadOpt()) || CGOptions::DoGlobalOpt()); ADDTARGETPHASE("prepeephole1", CGOptions::DoPrePeephole()); @@ -49,10 +47,8 @@ ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); - } + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/include/cg/reaching.h b/src/mapleall/maple_be/include/cg/reaching.h index 55b4b666fe..13872a9122 100644 --- a/src/mapleall/maple_be/include/cg/reaching.h +++ b/src/mapleall/maple_be/include/cg/reaching.h @@ -146,6 +146,7 @@ class ReachingDefinition : public AnalysisResult { std::vector memIn; std::vector memOut; const uint32 kMaxBBNum; + uint32 stackSize = 0; private: void Initialize(); void InitDataSize(); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 4a2f257321..6b5d902cb4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,7 +412,9 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - CHECK_FATAL(false, "check case in ssa"); + if (cgFunc.GetCG()->IsLmbc() == false) { + CHECK_FATAL(false, "check case in ssa"); + } } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp index 2176568333..dc5f214b8e 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp @@ -464,6 +464,9 @@ std::vector AArch64ReachingDefinition::FindMemDefBetweenInsn( ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffset < 0) { + memOffset = stackSize - memOffset; + } if ((offset == memOffset) || (insn->IsStorePair() && offset == memOffset + GetEachMemSizeOfPair(insn->GetMachineOpcode()))) { defInsnVec.emplace_back(insn); @@ -516,6 +519,9 @@ void AArch64ReachingDefinition::FindMemDefInBB(uint32 offset, BB &bb, InsnSet &d ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffset < 0) { + memOffset = stackSize - memOffset; + } if (offset == memOffset) { (void)defInsnSet.insert(insn); break; @@ -1001,6 +1007,9 @@ bool AArch64ReachingDefinition::FindMemUseBetweenInsn(uint32 offset, Insn *start ASSERT(memOpnd.GetIndexRegister() == nullptr, "offset must not be Register for frame MemOperand"); ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetValue(); + if (memOffset < 0) { + memOffset = stackSize - memOffset; + } if (insn->IsStore() || insn->IsPseudoInstruction()) { if (memOffset == offset) { @@ -1050,6 +1059,9 @@ InsnSet AArch64ReachingDefinition::FindDefForMemOpnd(Insn &insn, uint32 indexOrO } ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffSet < 0) { + memOffSet = stackSize - memOffSet; + } } else { memOffSet = indexOrOffset; } @@ -1101,6 +1113,9 @@ InsnSet AArch64ReachingDefinition::FindUseForMemOpnd(Insn &insn, uint8 index, bo ASSERT(memOpnd.GetIndexRegister() == nullptr, "IndexRegister no nullptr"); ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffSet < 0) { + memOffSet = stackSize - memOffSet; + } if (secondMem) { ASSERT(insn.IsStorePair(), "second MemOperand can only be defined in stp insn"); memOffSet += GetEachMemSizeOfPair(insn.GetMachineOpcode()); @@ -1214,6 +1229,9 @@ void AArch64ReachingDefinition::InitInfoForMemOperand(Insn &insn, Operand &opnd, CHECK_FATAL(index == nullptr, "Existing [x29 + index] Memory Address"); ASSERT(memOpnd.GetOffsetImmediate(), "offset must be a immediate value"); int64 offsetVal = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (offsetVal < 0) { + offsetVal = stackSize - offsetVal; + } if ((offsetVal % kMemZoomSize) != 0) { SetAnalysisMode(kRDRegAnalysis); } diff --git a/src/mapleall/maple_be/src/cg/reaching.cpp b/src/mapleall/maple_be/src/cg/reaching.cpp index 77fa156845..960d820e34 100644 --- a/src/mapleall/maple_be/src/cg/reaching.cpp +++ b/src/mapleall/maple_be/src/cg/reaching.cpp @@ -778,6 +778,7 @@ void ReachingDefinition::AnalysisStart() { if (!cgFunc->GetFirstBB()) { return; } + stackSize = GetStackSize(); Initialize(); /* Build in/out for function body first. (Except cleanup bb) */ BuildInOutForFuncBody(); -- Gitee From 2c98d8fcb7177a4afc7d48c3880c23d3731489c2 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Fri, 10 Jun 2022 17:56:05 -0700 Subject: [PATCH 077/179] delete obsolete code in SelectAggIassign() where small struct returned in regs was represented in an iassign --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 130 ------------------ 1 file changed, 130 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 3ba48a2cbc..c2f1a470e3 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -2286,15 +2286,6 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) { uint32 lhsOffset = 0; MIRType *stmtType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(stmt.GetTyIdx()); MIRPtrType *lhsPointerType = static_cast(stmtType); - bool loadToRegs4StructReturn = false; - if (mirModule.CurFunction()->StructReturnedInRegs()) { - MIRSymbol *retSt = mirModule.CurFunction()->GetFormal(0); - if (stmt.Opnd(0)->GetOpCode() == OP_dread) { - DreadNode *dread = static_cast(stmt.Opnd(0)); - MIRSymbol *addrSym = mirModule.CurFunction()->GetLocalOrGlobalSymbol(dread->GetStIdx()); - loadToRegs4StructReturn = (retSt == addrSym); - } - } MIRType *lhsType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(lhsPointerType->GetPointedTyIdx()); if (stmt.GetFieldID() != 0) { MIRStructType *structType = static_cast(lhsType); @@ -2338,91 +2329,6 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) { rhsType = structType->GetFieldType(rhsDread->GetFieldID()); rhsOffset = static_cast(GetBecommon().GetFieldOffset(*structType, rhsDread->GetFieldID()).first); } - if (loadToRegs4StructReturn) { - /* generate move to regs for agg return */ - CHECK_FATAL(lhsSize <= k16ByteSize, "SelectAggIassign: illegal struct size"); - AArch64CallConvImpl parmlocator(GetBecommon()); - CCLocInfo pLoc; - parmlocator.LocateNextParm(*lhsType, pLoc, true, GetBecommon().GetMIRModule().CurFunction()); - /* aggregates are 8 byte aligned. */ - Operand *rhsmemopnd = nullptr; - RegOperand *result[kFourRegister]; /* up to 2 int or 4 fp */ - uint32 loadSize; - uint32 numRegs; - RegType regType; - PrimType retPty; - bool fpParm = false; - if (pLoc.numFpPureRegs) { - loadSize = pLoc.fpSize; - numRegs = pLoc.numFpPureRegs; - fpParm = true; - regType = kRegTyFloat; - retPty = (pLoc.fpSize == k4ByteSize) ? PTY_f32 : PTY_f64; - } else { - if (CGOptions::IsBigEndian()) { - loadSize = k8ByteSize; - numRegs = (lhsSize <= k8ByteSize) ? kOneRegister : kTwoRegister; - regType = kRegTyInt; - retPty = PTY_u64; - } else { - loadSize = (lhsSize <= k4ByteSize) ? k4ByteSize : k8ByteSize; - numRegs = (lhsSize <= k8ByteSize) ? kOneRegister : kTwoRegister; - regType = kRegTyInt; - retPty = PTY_u32; - } - } - bool parmCopy = IsParamStructCopy(*rhsSymbol); - for (uint32 i = 0; i < numRegs; i++) { - if (parmCopy) { - rhsmemopnd = &LoadStructCopyBase(*rhsSymbol, - (rhsOffset + static_cast(i * (fpParm ? loadSize : k8ByteSize))), - static_cast(loadSize * kBitsPerByte)); - } else { - rhsmemopnd = &GetOrCreateMemOpnd(*rhsSymbol, - (rhsOffset + static_cast(i * (fpParm ? loadSize : k8ByteSize))), - (loadSize * kBitsPerByte)); - } - result[i] = &CreateVirtualRegisterOperand(NewVReg(regType, loadSize)); - MOperator mop1 = PickLdInsn(loadSize * kBitsPerByte, retPty); - Insn &ld = GetCG()->BuildInstruction(mop1, *(result[i]), *rhsmemopnd); - GetCurBB()->AppendInsn(ld); - } - AArch64reg regs[kFourRegister]; - regs[kFirstReg] = static_cast(pLoc.reg0); - regs[kSecondReg] = static_cast(pLoc.reg1); - regs[kThirdReg] = static_cast(pLoc.reg2); - regs[kFourthReg] = static_cast(pLoc.reg3); - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg; - MOperator mop2; - if (fpParm) { - preg = regs[i]; - mop2 = (loadSize == k4ByteSize) ? MOP_xvmovs : MOP_xvmovd; - } else { - preg = (i == 0 ? R0 : R1); - mop2 = (loadSize == k4ByteSize) ? MOP_wmovrr : MOP_xmovrr; - } - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, (loadSize * kBitsPerByte), regType); - Insn &mov = GetCG()->BuildInstruction(mop2, dest, *(result[i])); - GetCurBB()->AppendInsn(mov); - } - /* Create artificial dependency to extend the live range */ - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg; - MOperator mop3; - if (fpParm) { - preg = regs[i]; - mop3 = MOP_pseudo_ret_float; - } else { - preg = (i == 0 ? R0 : R1); - mop3 = MOP_pseudo_ret_int; - } - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, loadSize * kBitsPerByte, regType); - Insn &pseudo = GetCG()->BuildInstruction(mop3, dest); - GetCurBB()->AppendInsn(pseudo); - } - return; - } rhsAlign = GetBecommon().GetTypeAlign(rhsType->GetTypeIndex()); alignUsed = std::min(lhsAlign, rhsAlign); ASSERT(alignUsed != 0, "expect non-zero"); @@ -2538,42 +2444,6 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) { rhsOffset = static_cast(GetBecommon().GetFieldOffset(*rhsStructType, rhsIread->GetFieldID()).first); isRefField = GetBecommon().IsRefField(*rhsStructType, rhsIread->GetFieldID()); } - if (loadToRegs4StructReturn) { - /* generate move to regs. */ - CHECK_FATAL(lhsSize <= k16ByteSize, "SelectAggIassign: illegal struct size"); - RegOperand *result[kTwoRegister]; /* maximum 16 bytes, 2 registers */ - uint32 loadSize; - if (CGOptions::IsBigEndian()) { - loadSize = k8ByteSize; - } else { - loadSize = (lhsSize <= k4ByteSize) ? k4ByteSize : k8ByteSize; - } - uint32 numRegs = (lhsSize <= k8ByteSize) ? kOneRegister : kTwoRegister; - for (uint32 i = 0; i < numRegs; i++) { - OfstOperand *rhsOffOpnd = &GetOrCreateOfstOpnd(rhsOffset + i * loadSize, loadSize * kBitsPerByte); - Operand &rhsmemopnd = GetOrCreateMemOpnd(MemOperand::kAddrModeBOi, loadSize * kBitsPerByte, - rhsAddrOpnd, nullptr, rhsOffOpnd, nullptr); - result[i] = &CreateVirtualRegisterOperand(NewVReg(kRegTyInt, loadSize)); - MOperator mop1 = PickLdInsn(loadSize * kBitsPerByte, PTY_u32); - Insn &ld = GetCG()->BuildInstruction(mop1, *(result[i]), rhsmemopnd); - ld.MarkAsAccessRefField(isRefField); - GetCurBB()->AppendInsn(ld); - } - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg = (i == 0 ? R0 : R1); - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, loadSize * kBitsPerByte, kRegTyInt); - Insn &mov = GetCG()->BuildInstruction(MOP_xmovrr, dest, *(result[i])); - GetCurBB()->AppendInsn(mov); - } - /* Create artificial dependency to extend the live range */ - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg = (i == 0 ? R0 : R1); - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, loadSize * kBitsPerByte, kRegTyInt); - Insn &pseudo = cg->BuildInstruction(MOP_pseudo_ret_int, dest); - GetCurBB()->AppendInsn(pseudo); - } - return; - } rhsAlign = GetBecommon().GetTypeAlign(rhsType->GetTypeIndex()); alignUsed = std::min(lhsAlign, rhsAlign); ASSERT(alignUsed != 0, "expect non-zero"); -- Gitee From 64a57f60b7acb51faa35b4ce5be41844a33f437c Mon Sep 17 00:00:00 2001 From: William Chen Date: Mon, 13 Jun 2022 14:06:17 -0700 Subject: [PATCH 078/179] Do not optimize for ssa for physical regs. --- .../include/cg/aarch64/aarch64_phases.def | 22 +++++++++---------- .../src/cg/aarch64/aarch64_global.cpp | 4 +--- .../maple_be/src/cg/aarch64/aarch64_prop.cpp | 3 +++ 3 files changed, 14 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 5595b17c0c..531e7f0535 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,18 +17,16 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); - } + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 6b5d902cb4..4a2f257321 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,9 +412,7 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - if (cgFunc.GetCG()->IsLmbc() == false) { - CHECK_FATAL(false, "check case in ssa"); - } + CHECK_FATAL(false, "check case in ssa"); } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp index 6b45e3bdf6..52955cdd7d 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp @@ -1491,6 +1491,9 @@ bool ExtendMovPattern::CheckSrcReg(regno_t srcRegNo, uint32 validNum) { bool ExtendMovPattern::BitNotAffected(const Insn &insn, uint32 validNum) { RegOperand &firstOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); + if (firstOpnd.IsPhysicalRegister()) { + return false; + } RegOperand &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); regno_t desRegNo = firstOpnd.GetRegisterNumber(); regno_t srcRegNo = secondOpnd.GetRegisterNumber(); -- Gitee From 445b46e189da55ece4942133402b2a29f1978ca9 Mon Sep 17 00:00:00 2001 From: William Chen Date: Tue, 14 Jun 2022 09:21:24 -0700 Subject: [PATCH 079/179] Fix globalopt bug of negative offset with lmbc --- .../maple_be/src/cg/aarch64/aarch64_reaching.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp index dc5f214b8e..55b6059fd3 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp @@ -465,7 +465,7 @@ std::vector AArch64ReachingDefinition::FindMemDefBetweenInsn( ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffset < 0) { - memOffset = stackSize - memOffset; + memOffset = stackSize + memOffset; } if ((offset == memOffset) || (insn->IsStorePair() && offset == memOffset + GetEachMemSizeOfPair(insn->GetMachineOpcode()))) { @@ -520,7 +520,7 @@ void AArch64ReachingDefinition::FindMemDefInBB(uint32 offset, BB &bb, InsnSet &d ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffset < 0) { - memOffset = stackSize - memOffset; + memOffset = stackSize + memOffset; } if (offset == memOffset) { (void)defInsnSet.insert(insn); @@ -1008,7 +1008,7 @@ bool AArch64ReachingDefinition::FindMemUseBetweenInsn(uint32 offset, Insn *start ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetValue(); if (memOffset < 0) { - memOffset = stackSize - memOffset; + memOffset = stackSize + memOffset; } if (insn->IsStore() || insn->IsPseudoInstruction()) { @@ -1060,7 +1060,7 @@ InsnSet AArch64ReachingDefinition::FindDefForMemOpnd(Insn &insn, uint32 indexOrO ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffSet < 0) { - memOffSet = stackSize - memOffSet; + memOffSet = stackSize + memOffSet; } } else { memOffSet = indexOrOffset; @@ -1114,7 +1114,7 @@ InsnSet AArch64ReachingDefinition::FindUseForMemOpnd(Insn &insn, uint8 index, bo ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffSet < 0) { - memOffSet = stackSize - memOffSet; + memOffSet = stackSize + memOffSet; } if (secondMem) { ASSERT(insn.IsStorePair(), "second MemOperand can only be defined in stp insn"); @@ -1230,7 +1230,7 @@ void AArch64ReachingDefinition::InitInfoForMemOperand(Insn &insn, Operand &opnd, ASSERT(memOpnd.GetOffsetImmediate(), "offset must be a immediate value"); int64 offsetVal = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (offsetVal < 0) { - offsetVal = stackSize - offsetVal; + offsetVal = stackSize + offsetVal; } if ((offsetVal % kMemZoomSize) != 0) { SetAnalysisMode(kRDRegAnalysis); -- Gitee From 8a74c6043c78cbf5b264d8475b484b0b89aa6575 Mon Sep 17 00:00:00 2001 From: William Chen Date: Tue, 14 Jun 2022 15:55:34 -0700 Subject: [PATCH 080/179] Merge return bb for small C functions --- src/mapleall/maple_be/include/cg/cgfunc.h | 1 + src/mapleall/maple_be/src/cg/cgbb.cpp | 1 + src/mapleall/maple_be/src/cg/cgfunc.cpp | 3 ++- 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/include/cg/cgfunc.h b/src/mapleall/maple_be/include/cg/cgfunc.h index 50e134552e..0a29d3b5a8 100644 --- a/src/mapleall/maple_be/include/cg/cgfunc.h +++ b/src/mapleall/maple_be/include/cg/cgfunc.h @@ -81,6 +81,7 @@ class SpillMemOperandSet { class LiveRange; #endif /* TARGARM32 */ constexpr uint32 kVRegisterNumber = 80; +constexpr uint32 kNumBBOptReturn = 30; class CGFunc { public: enum ShiftDirection : uint8 { diff --git a/src/mapleall/maple_be/src/cg/cgbb.cpp b/src/mapleall/maple_be/src/cg/cgbb.cpp index 502983b519..d8b5e86278 100644 --- a/src/mapleall/maple_be/src/cg/cgbb.cpp +++ b/src/mapleall/maple_be/src/cg/cgbb.cpp @@ -525,6 +525,7 @@ void Bfs::ComputeBlockOrder() { done = true; } else { LogInfo::MapleLogger() << "Error: RA BFS loop " << sortedCnt << " in func " << cgfunc->GetName() << "\n"; + CHECK_FATAL(false, ""); } } sortedCnt = sortedBBs.size(); diff --git a/src/mapleall/maple_be/src/cg/cgfunc.cpp b/src/mapleall/maple_be/src/cg/cgfunc.cpp index 5b84a5d8b7..771970e588 100644 --- a/src/mapleall/maple_be/src/cg/cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/cgfunc.cpp @@ -2032,7 +2032,8 @@ void CGFunc::HandleFunction() { /* select instruction */ GenerateInstruction(); /* merge multi return */ - if (!func.GetModule()->IsCModule() || CGOptions::DoRetMerge() || CGOptions::OptimizeForSize()) { + if (!func.GetModule()->IsCModule() || (func.GetModule()->IsCModule() && (NumBBs() < kNumBBOptReturn)) || + CGOptions::DoRetMerge() || CGOptions::OptimizeForSize()) { MergeReturn(); } if (func.IsJava()) { -- Gitee From 906c261fdf2a253a214e372975f9b0798aaca219 Mon Sep 17 00:00:00 2001 From: William Chen Date: Thu, 16 Jun 2022 10:53:55 -0700 Subject: [PATCH 081/179] Reorder back-to-back cond branch and uncond brach to loop head bb --- src/mapleall/maple_be/include/cg/cfgo.h | 24 +++++++++ src/mapleall/maple_be/include/cg/loop.h | 3 +- src/mapleall/maple_be/src/cg/cfgo.cpp | 65 ++++++++++++++++++++++++- src/mapleall/maple_be/src/cg/loop.cpp | 4 ++ 4 files changed, 93 insertions(+), 3 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/cfgo.h b/src/mapleall/maple_be/include/cg/cfgo.h index e7d6e07e14..2528f03413 100644 --- a/src/mapleall/maple_be/include/cg/cfgo.h +++ b/src/mapleall/maple_be/include/cg/cfgo.h @@ -18,6 +18,14 @@ #include "optimize_common.h" namespace maplebe { + +enum CfgoPhase : maple::uint8 { + CfgoDefault, + CfgoPreRegAlloc, + CfgoPostRegAlloc, + PostCfgo, +}; + class ChainingPattern : public OptimizationPattern { public: explicit ChainingPattern(CGFunc &func) : OptimizationPattern(func) { @@ -63,6 +71,14 @@ class FlipBRPattern : public OptimizationPattern { ~FlipBRPattern() override = default; bool Optimize(BB &curBB) override; + CfgoPhase GetPhase() const { + return phase; + } + void SetPhase(CfgoPhase val) { + phase = val; + } + CfgoPhase phase = CfgoDefault; + protected: void RelocateThrowBB(BB &curBB); }; @@ -120,6 +136,14 @@ class CFGOptimizer : public Optimizer { ~CFGOptimizer() override = default; void InitOptimizePatterns() override; + + CfgoPhase GetPhase() const { + return phase; + } + void SetPhase(CfgoPhase val) { + phase = val; + } + CfgoPhase phase = CfgoDefault; }; MAPLE_FUNC_PHASE_DECLARE_BEGIN(CgCfgo, maplebe::CGFunc) diff --git a/src/mapleall/maple_be/include/cg/loop.h b/src/mapleall/maple_be/include/cg/loop.h index 658ee83f04..eedf5bc02c 100644 --- a/src/mapleall/maple_be/include/cg/loop.h +++ b/src/mapleall/maple_be/include/cg/loop.h @@ -171,7 +171,8 @@ class CGFuncLoops { void CheckOverlappingInnerLoops(const MapleVector &iLoops, const MapleVector &loopMem) const; void CheckLoops() const; - void PrintLoops(const CGFuncLoops &funcLoop) const; + void PrintLoops(const CGFuncLoops &loops) const; + bool IsBBLoopMember(const BB *bb) const; const BB *GetHeader() const { return header; diff --git a/src/mapleall/maple_be/src/cg/cfgo.cpp b/src/mapleall/maple_be/src/cg/cfgo.cpp index 46822d45d2..4b89308ec5 100644 --- a/src/mapleall/maple_be/src/cg/cfgo.cpp +++ b/src/mapleall/maple_be/src/cg/cfgo.cpp @@ -42,7 +42,11 @@ void CFGOptimizer::InitOptimizePatterns() { diffPassPatterns.emplace_back(memPool->New(*cgFunc)); } diffPassPatterns.emplace_back(memPool->New(*cgFunc)); - diffPassPatterns.emplace_back(memPool->New(*cgFunc)); + FlipBRPattern *brOpt = memPool->New(*cgFunc); + if (GetPhase() == CfgoPostRegAlloc) { + brOpt->SetPhase(CfgoPostRegAlloc); + } + diffPassPatterns.emplace_back(brOpt); diffPassPatterns.emplace_back(memPool->New(*cgFunc)); diffPassPatterns.emplace_back(memPool->New(*cgFunc)); diffPassPatterns.emplace_back(memPool->New(*cgFunc)); @@ -547,7 +551,13 @@ void FlipBRPattern::RelocateThrowBB(BB &curBB) { * ftBB * targetBB * - * 2. relocate throw BB in RelocateThrowBB() + * loopHeaderBB: loopHeaderBB: + * ... ... + * cond_br loopExit: cond_br loopHeaderBB + * ftBB: ftBB: + * goto loopHeaderBB: goto loopExit + * + * 3. relocate throw BB in RelocateThrowBB() */ bool FlipBRPattern::Optimize(BB &curBB) { if (curBB.GetKind() == BB::kBBIf && !curBB.IsEmpty()) { @@ -647,6 +657,50 @@ bool FlipBRPattern::Optimize(BB &curBB) { ftBB->RemoveInsn(*brInsn); ftBB->SetKind(BB::kBBFallthru); } + } else if (GetPhase() == CfgoPostRegAlloc && ftBB->GetKind() == BB::kBBGoto && + curBB.GetLoop() != nullptr && curBB.GetLoop() == ftBB->GetLoop() && + ftBB->IsSoloGoto() && + ftBB->GetLoop()->GetHeader() == *(ftBB->GetSuccsBegin()) && + curBB.GetLoop()->IsBBLoopMember((curBB.GetSuccs().front() == ftBB) ? + curBB.GetSuccs().back() : curBB.GetSuccs().front()) == false) { + Insn *curBBBranchInsn = nullptr; + for (curBBBranchInsn = curBB.GetLastInsn(); curBBBranchInsn != nullptr; + curBBBranchInsn = curBBBranchInsn->GetPrev()) { + if (curBBBranchInsn->IsBranch()) { + break; + } + } + ASSERT(curBBBranchInsn != nullptr, "FlipBRPattern: curBB has no branch"); + Insn *brInsn = nullptr; + for (brInsn = ftBB->GetLastInsn(); brInsn != nullptr; brInsn = brInsn->GetPrev()) { + if (brInsn->IsGoto()) { + break; + } + } + ASSERT(brInsn != nullptr, "FlipBRPattern: ftBB has no branch"); + uint32 condTargetIdx = curBBBranchInsn->GetJumpTargetIdx(); + LabelOperand &condTarget = static_cast(curBBBranchInsn->GetOperand(condTargetIdx)); + MOperator mOp = curBBBranchInsn->FlipConditionOp(curBBBranchInsn->GetMachineOpcode(), condTargetIdx); + if (mOp == 0) { + return false; + } + uint32 gotoTargetIdx = brInsn->GetJumpTargetIdx(); + LabelOperand &gotoTarget = static_cast(brInsn->GetOperand(gotoTargetIdx)); + curBBBranchInsn->SetMOP(mOp); + curBBBranchInsn->SetOperand(condTargetIdx, gotoTarget); + brInsn->SetOperand(gotoTargetIdx, condTarget); + auto it = ftBB->GetSuccsBegin(); + BB *loopHeadBB = *it; + + curBB.RemoveSuccs(*brBB); + brBB->RemovePreds(curBB); + ftBB->RemoveSuccs(*loopHeadBB); + loopHeadBB->RemovePreds(*ftBB); + + curBB.PushBackSuccs(*loopHeadBB); + loopHeadBB->PushBackPreds(curBB); + ftBB->PushBackSuccs(*brBB); + brBB->PushBackPreds(*ftBB); } else { RelocateThrowBB(curBB); } @@ -847,6 +901,10 @@ bool DuplicateBBPattern::Optimize(BB &curBB) { /* === new pm === */ bool CgCfgo::PhaseRun(maplebe::CGFunc &f) { CFGOptimizer *cfgOptimizer = GetPhaseAllocator()->New(f, *GetPhaseMemPool()); + if (f.IsAfterRegAlloc()) { + (void)GetAnalysisInfoHook()->ForceRunAnalysisPhase, CGFunc>(&CgLoopAnalysis::id, f); + cfgOptimizer->SetPhase(CfgoPostRegAlloc); + } const std::string &funcClass = f.GetFunction().GetBaseClassName(); const std::string &funcName = f.GetFunction().GetBaseFuncName(); const std::string &name = funcClass + funcName; @@ -854,6 +912,9 @@ bool CgCfgo::PhaseRun(maplebe::CGFunc &f) { DotGenerator::GenerateDot("before-cfgo", f, f.GetMirModule()); } cfgOptimizer->Run(name); + if (f.IsAfterRegAlloc()) { + GetAnalysisInfoHook()->ForceEraseAnalysisPhase(f.GetUniqueID(), &CgLoopAnalysis::id); + } if (CFGO_DUMP_NEWPM) { DotGenerator::GenerateDot("after-cfgo", f, f.GetMirModule()); } diff --git a/src/mapleall/maple_be/src/cg/loop.cpp b/src/mapleall/maple_be/src/cg/loop.cpp index 71fb9e8edb..d37a7e0dfd 100644 --- a/src/mapleall/maple_be/src/cg/loop.cpp +++ b/src/mapleall/maple_be/src/cg/loop.cpp @@ -161,6 +161,10 @@ void CGFuncLoops::PrintLoops(const CGFuncLoops &funcLoop) const { } } +bool CGFuncLoops::IsBBLoopMember(const BB *bb) const { + return (*(std::find(loopMembers.begin(), loopMembers.end(), bb)) == bb); +} + // partial loop body found with formLoop is NOT really needed in down stream // It should be simplied later void LoopFinder::formLoop(BB* headBB, BB* backBB) { -- Gitee From effbb4b9fb6bc5b15193da185197c31e0d89a672 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Mon, 20 Jun 2022 15:49:32 -0700 Subject: [PATCH 082/179] Updating to "new" lmbc --- .../include/cg/aarch64/aarch64_cgfunc.h | 14 +- src/mapleall/maple_be/include/cg/cgfunc.h | 4 +- .../src/cg/aarch64/aarch64_cgfunc.cpp | 127 ++++++++++++++++-- .../src/cg/aarch64/aarch64_memlayout.cpp | 24 +++- .../src/cg/aarch64/aarch64_proepilog.cpp | 35 ++++- 5 files changed, 178 insertions(+), 26 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index bf154e7657..be3a3bae62 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -104,6 +104,7 @@ class AArch64CGFunc : public CGFunc { MIRType *LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList) const; RegOperand &GetOrCreateResOperand(const BaseNode &parent, PrimType primType); + MIRStructType *GetLmbcStructArgType(BaseNode &stmt, int32 argNo); void IntrinsifyGetAndAddInt(ListOperand &srcOpnds, PrimType pty); void IntrinsifyGetAndSetInt(ListOperand &srcOpnds, PrimType pty); @@ -191,7 +192,8 @@ class AArch64CGFunc : public CGFunc { Operand *SelectIread(const BaseNode &parent, IreadNode &expr, int extraOffset = 0, PrimType finalBitFieldDestType = kPtyInvalid) override; Operand *SelectIreadoff(const BaseNode &parent, IreadoffNode &ireadoff) override; - Operand *SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff) override; + Operand *SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff /*, MIRType &ty, + ListOperand &srcOpnds, AArch64CallConvImpl &parmLocator */) override; Operand *SelectIntConst(MIRIntConst &intConst) override; Operand *HandleFmovImm(PrimType stype, int64 val, MIRConst &mirConst, const BaseNode &parent); Operand *SelectFloatConst(MIRFloatConst &floatConst, const BaseNode &parent) override; @@ -869,7 +871,7 @@ class AArch64CGFunc : public CGFunc { void SelectParmListDreadSmallAggregate(const MIRSymbol &sym, MIRType &structType, ListOperand &srcOpnds, int32 offset, AArch64CallConvImpl &parmLocator, FieldID fieldID); - void SelectParmListIreadSmallAggregate(const IreadNode &iread, MIRType &structType, ListOperand &srcOpnds, + void SelectParmListIreadSmallAggregate(BaseNode &iread, MIRType &structType, ListOperand &srcOpnds, int32 offset, AArch64CallConvImpl &parmLocator); void SelectParmListDreadLargeAggregate(const MIRSymbol &sym, MIRType &structType, ListOperand &srcOpnds, @@ -878,12 +880,12 @@ class AArch64CGFunc : public CGFunc { AArch64CallConvImpl &parmLocator, int32 &structCopyOffset, int32 fromOffset); void CreateCallStructMemcpyToParamReg(MIRType &structType, int32 structCopyOffset, AArch64CallConvImpl &parmLocator, ListOperand &srcOpnds); - void SelectParmListForAggregate(BaseNode &argExpr, ListOperand &srcOpnds, AArch64CallConvImpl &parmLocator, - int32 &structCopyOffset); + void SelectParmListForAggregate(BaseNode &parent, BaseNode &argExpr, ListOperand &srcOpnds, + AArch64CallConvImpl &parmLocator, int32 &structCopyOffset, int32 argNo); size_t SelectParmListGetStructReturnSize(StmtNode &naryNode); bool MarkParmListCall(BaseNode &expr); - void SelectParmListPreprocessLargeStruct(BaseNode &argExpr, int32 &structCopyOffset); - void SelectParmListPreprocess(const StmtNode &naryNode, size_t start, std::set &specialArgs); + void SelectParmListPreprocessLargeStruct(BaseNode &parent, BaseNode &argExpr, int32 &structCopyOffset, int32 argNo); + void SelectParmListPreprocess(StmtNode &naryNode, size_t start, std::set &specialArgs); void SelectParmList(StmtNode &naryNode, ListOperand &srcOpnds, bool isCallNative = false); Operand *SelectClearStackCallParam(const AddrofNode &expr, int64 &offsetValue); void SelectClearStackCallParmList(const StmtNode &naryNode, ListOperand &srcOpnds, diff --git a/src/mapleall/maple_be/include/cg/cgfunc.h b/src/mapleall/maple_be/include/cg/cgfunc.h index 0a29d3b5a8..21e5e938ea 100644 --- a/src/mapleall/maple_be/include/cg/cgfunc.h +++ b/src/mapleall/maple_be/include/cg/cgfunc.h @@ -1150,8 +1150,8 @@ class CGFunc { #endif MapleMap vregsToPregsMap; uint32 totalInsns = 0; - int32 structCopySize; - int32 maxParamStackSize; + int32 structCopySize = 0; + int32 maxParamStackSize = 0; static constexpr int kRegIncrStepLen = 80; /* reg number increate step length */ bool hasVLAOrAlloca = false; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index c2f1a470e3..305c9f0338 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -161,6 +161,28 @@ bool IsBlkassignForPush(const BlkassignoffNode &bNode) { return spBased; } +MIRStructType *AArch64CGFunc::GetLmbcStructArgType(BaseNode &stmt, int32 argNo) { + MIRType *ty = nullptr; + if (stmt.GetOpCode() == OP_call) { + CallNode &callNode = static_cast(stmt); + MIRFunction *callFunc = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(callNode.GetPUIdx()); + if (callFunc->GetFormalCount() < (argNo + 1)) { + return nullptr; /* formals less than actuals */ + } + ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(callFunc->GetFormalDefVec()[argNo].formalTyIdx); + } else if (stmt.GetOpCode() == OP_icallproto) { + IcallNode &icallproto = static_cast(stmt); + MIRType *type = GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallproto.GetRetTyIdx()); + MIRFuncType *fType = static_cast(type); + if (fType->GetParamTypeList().size() < (argNo + 1)) { + return nullptr; + } + ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(fType->GetNthParamType(argNo)); + } + CHECK_FATAL(ty && ty->IsStructType(), "lmbc agg arg error"); + return static_cast(ty); +} + RegOperand &AArch64CGFunc::GetOrCreateResOperand(const BaseNode &parent, PrimType primType) { RegOperand *resOpnd = nullptr; if (parent.GetOpCode() == OP_regassign) { @@ -3095,15 +3117,19 @@ RegOperand *AArch64CGFunc::LmbcStructReturnLoad(int32 offset) { return result; } -Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff) { +Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff /*, MIRType &ty, + ListOperand &srcOpnds, AArch64CallConvImpl &parmLocator*/) { int32 offset = ireadoff.GetOffset(); PrimType primType = ireadoff.GetPrimType(); uint32 bytelen = GetPrimTypeSize(primType); +#if 1 uint32 bitlen = bytelen * kBitsPerByte; +#endif RegType regty = GetRegTyFromPrimTy(primType); RegOperand *result = nullptr; if (offset >= 0) { - LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(static_cast(offset)); +#if 1 + LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(offset); if (info->GetPrimType() == PTY_agg) { if (info->IsOnStack()) { result = GenLmbcParamLoad(info->GetOnStackOffset(), GetPrimTypeSize(PTY_a64), kRegTyInt, PTY_a64); @@ -3124,10 +3150,23 @@ Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode result = &GetOrCreatePhysicalRegisterOperand(static_cast(info->GetRegNO()), bitlen, regty); } } +#endif + CHECK_FATAL(0, "Invalid ireadfpoff offset"); } else { if (primType == PTY_agg) { - CHECK_FATAL(parent.GetOpCode() == OP_regassign, "SelectIreadfpoff of agg"); - result = LmbcStructReturnLoad(offset); +#if OLD_LMBC // TBD + if (parent.GetOpCode() == OP_call || parent.GetOpCode() == OP_icallproto) { + /* ireadfpoff is now for loading locals under calls. Large agg arg is handled via + SelectParmListPreprocess, Hence only small agg is handled here */ + SelectParmListIreadSmallAggregate(ireadoff, ty, srcOpnds, 0, parmLocator); + } else { +#endif + /* agg return */ + CHECK_FATAL(parent.GetOpCode() == OP_regassign, "SelectIreadfpoff of agg"); + result = LmbcStructReturnLoad(offset); +#if OLD_LMBC // TBD + } +#endif } else { result = GenLmbcParamLoad(offset, bytelen, regty, primType); } @@ -7361,12 +7400,26 @@ void AArch64CGFunc::SelectParmListDreadSmallAggregate(const MIRSymbol &sym, MIRT } } -void AArch64CGFunc::SelectParmListIreadSmallAggregate(const IreadNode &iread, MIRType &structType, +void AArch64CGFunc::SelectParmListIreadSmallAggregate(BaseNode &iread, MIRType &structType, ListOperand &srcOpnds, int32 offset, AArch64CallConvImpl &parmLocator) { int32 symSize = GetBecommon().GetTypeSize(structType.GetTypeIndex().GetIdx()); - RegOperand *addrOpnd0 = static_cast(HandleExpr(iread, *(iread.Opnd(0)))); - RegOperand *addrOpnd1 = &LoadIntoRegister(*addrOpnd0, iread.Opnd(0)->GetPrimType()); + RegOperand *addrOpnd1; + if (iread.GetOpCode() == OP_iread) { + RegOperand *addrOpnd0 = static_cast(HandleExpr(iread, *(iread.Opnd(0)))); + addrOpnd1 = &LoadIntoRegister(*addrOpnd0, iread.Opnd(0)->GetPrimType()); + } else if (iread.GetOpCode() == OP_ireadfpoff) { + IreadFPoffNode &ireadoff = static_cast(iread); + RegOperand *rfp = &GetOrCreatePhysicalRegisterOperand(RFP, k64BitSize, kRegTyInt); + RegOperand *addrOpnd0 = &CreateRegisterOperandOfType(PTY_a64); + ImmOperand &immOpnd = CreateImmOperand(ireadoff.GetOffset(), k32BitSize, true); + GetCurBB()->AppendInsn(GetCG()->BuildInstruction(MOP_xaddrri12, *addrOpnd0, *rfp, immOpnd)); + addrOpnd1 = &LoadIntoRegister(*addrOpnd0, PTY_i64); + } else if (iread.GetOpCode() == OP_ireadoff) { + IreadoffNode &ireadoff = static_cast(iread); + RegOperand *addrOpnd0 = static_cast(HandleExpr(ireadoff, *(ireadoff.Opnd(0)))); + addrOpnd1 = &LoadIntoRegister(*addrOpnd0, PTY_i64); + } CCLocInfo ploc; parmLocator.LocateNextParm(structType, ploc); if (ploc.reg0 == 0) { @@ -7740,8 +7793,8 @@ void AArch64CGFunc::CreateCallStructMemcpyToParamReg(MIRType &structType, int32 } } -void AArch64CGFunc::SelectParmListForAggregate(BaseNode &argExpr, ListOperand &srcOpnds, - AArch64CallConvImpl &parmLocator, int32 &structCopyOffset) { +void AArch64CGFunc::SelectParmListForAggregate(BaseNode &parent, BaseNode &argExpr, ListOperand &srcOpnds, + AArch64CallConvImpl &parmLocator, int32 &structCopyOffset, int32 argNo) { uint64 symSize; int32 rhsOffset = 0; if (argExpr.GetOpCode() == OP_dread) { @@ -7789,6 +7842,32 @@ void AArch64CGFunc::SelectParmListForAggregate(BaseNode &argExpr, ListOperand &s } else { SelectParmListIreadLargeAggregate(iread, *ty, srcOpnds, parmLocator, structCopyOffset, rhsOffset); } + } else if (argExpr.GetOpCode() == OP_ireadfpoff) { + IreadFPoffNode &iread = static_cast(argExpr); + MIRStructType *ty = GetLmbcStructArgType(parent, argNo); + if (ty == nullptr) { /* param < arg */ + return; + } + symSize = GetBecommon().GetTypeSize(ty->GetTypeIndex().GetIdx()); + if (symSize <= k16ByteSize) { + SelectParmListIreadSmallAggregate(iread, *ty, srcOpnds, rhsOffset, parmLocator); + } else { + CreateCallStructMemcpyToParamReg(*ty, structCopyOffset, parmLocator, srcOpnds); + structCopyOffset += static_cast(RoundUp(symSize, kSizeOfPtr)); + } + } else if (argExpr.GetOpCode() == OP_ireadoff) { + IreadoffNode &iread = static_cast(argExpr); + MIRStructType *ty = GetLmbcStructArgType(parent, argNo); + if (ty == nullptr) { + return; + } + symSize = GetBecommon().GetTypeSize(ty->GetTypeIndex().GetIdx()); + if (symSize <= k16ByteSize) { + SelectParmListIreadSmallAggregate(iread, *ty, srcOpnds, rhsOffset, parmLocator); + } else { + CreateCallStructMemcpyToParamReg(*ty, structCopyOffset, parmLocator, srcOpnds); + structCopyOffset += static_cast(RoundUp(symSize, kSizeOfPtr)); + } } else { CHECK_FATAL(0, "NYI"); } @@ -7831,7 +7910,7 @@ size_t AArch64CGFunc::SelectParmListGetStructReturnSize(StmtNode &naryNode) { return 0; } -void AArch64CGFunc::SelectParmListPreprocessLargeStruct(BaseNode &argExpr, int32 &structCopyOffset) { +void AArch64CGFunc::SelectParmListPreprocessLargeStruct(BaseNode &parent, BaseNode &argExpr, int32 &structCopyOffset, int32 argNo) { uint64 symSize; int32 rhsOffset = 0; if (argExpr.GetOpCode() == OP_dread) { @@ -7878,6 +7957,22 @@ void AArch64CGFunc::SelectParmListPreprocessLargeStruct(BaseNode &argExpr, int32 uint32 numMemOp = static_cast(RoundUp(symSize, kSizeOfPtr) / kSizeOfPtr); structCopyOffset += static_cast(numMemOp * kSizeOfPtr); } + } else if (argExpr.GetOpCode() == OP_ireadfpoff) { + IreadFPoffNode &ireadoff = static_cast(argExpr); + MIRStructType *ty = GetLmbcStructArgType(parent, argNo); + symSize = GetBecommon().GetTypeSize(ty->GetTypeIndex()); + if (symSize > 16 /*kParmMemcpySize*/) { +#if OLD_LMBC // TBD + MemOperand *addrOpnd0 = GenLmbcFpMemOperand(ireadoff.GetOffset(), kSizeOfPtr, RFP); + RegOperand *addrOpnd1 = &LoadIntoRegister(*addrOpnd0, PTY_i64); +#endif + RegOperand *rfp = &GetOrCreatePhysicalRegisterOperand(RFP, k64BitSize, kRegTyInt); + RegOperand *addrOpnd = &CreateRegisterOperandOfType(PTY_a64); + ImmOperand &immOpnd = CreateImmOperand(ireadoff.GetOffset(), k32BitSize, true); + GetCurBB()->AppendInsn(GetCG()->BuildInstruction(MOP_xaddrri12, *addrOpnd, *rfp, immOpnd)); + CreateCallStructParamMemcpy(nullptr, addrOpnd, static_cast(symSize), structCopyOffset, 0); + structCopyOffset += static_cast(RoundUp(symSize, kSizeOfPtr)); + } } } @@ -7909,7 +8004,7 @@ bool AArch64CGFunc::MarkParmListCall(BaseNode &expr) { return false; } -void AArch64CGFunc::SelectParmListPreprocess(const StmtNode &naryNode, size_t start, std::set &specialArgs) { +void AArch64CGFunc::SelectParmListPreprocess(StmtNode &naryNode, size_t start, std::set &specialArgs) { size_t i = start; int32 structCopyOffset = GetMaxParamStackSize() - GetStructCopySize(); for (; i < naryNode.NumOpnds(); ++i) { @@ -7922,7 +8017,7 @@ void AArch64CGFunc::SelectParmListPreprocess(const StmtNode &naryNode, size_t st if (primType != PTY_agg) { continue; } - SelectParmListPreprocessLargeStruct(*argExpr, structCopyOffset); + SelectParmListPreprocessLargeStruct(naryNode, *argExpr, structCopyOffset, i); } } @@ -8022,7 +8117,7 @@ void AArch64CGFunc::SelectParmList(StmtNode &naryNode, ListOperand &srcOpnds, bo } /* use alloca */ if (primType == PTY_agg) { - SelectParmListForAggregate(*argExpr, srcOpnds, parmLocator, structCopyOffset); + SelectParmListForAggregate(naryNode, *argExpr, srcOpnds, parmLocator, structCopyOffset, i); continue; } ty = GlobalTables::GetTypeTable().GetTypeTable()[static_cast(primType)]; @@ -9428,7 +9523,11 @@ Operand *AArch64CGFunc::GetBaseReg(const AArch64SymbolAlloc &symAlloc) { } if (fsp == nullptr) { - fsp = &GetOrCreatePhysicalRegisterOperand(RFP, kSizeOfPtr * kBitsPerByte, kRegTyInt); + if (GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { + fsp = &GetOrCreatePhysicalRegisterOperand(RSP, kSizeOfPtr * kBitsPerByte, kRegTyInt); + } else { + fsp = &GetOrCreatePhysicalRegisterOperand(RFP, kSizeOfPtr * kBitsPerByte, kRegTyInt); + } } return fsp; } diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index b7403f414f..b7ef7ae1ec 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -58,7 +58,9 @@ uint32 AArch64MemLayout::ComputeStackSpaceRequirementForCall(StmtNode &stmt, in ty = GlobalTables::GetTypeTable().GetTypeTable()[static_cast(opnd->GetPrimType())]; } else { Opcode opndOpcode = opnd->GetOpCode(); - ASSERT(opndOpcode == OP_dread || opndOpcode == OP_iread, "opndOpcode should be OP_dread or OP_iread"); + if (be.GetMIRModule().GetFlavor() != kFlavorLmbc) { + ASSERT(opndOpcode == OP_dread || opndOpcode == OP_iread, "opndOpcode should be OP_dread or OP_iread"); + } if (opndOpcode == OP_dread) { DreadNode *dread = static_cast(opnd); MIRSymbol *sym = be.GetMIRModule().CurFunction()->GetLocalOrGlobalSymbol(dread->GetStIdx()); @@ -72,8 +74,7 @@ uint32 AArch64MemLayout::ComputeStackSpaceRequirementForCall(StmtNode &stmt, in ty = static_cast(ty)->GetFieldType(dread->GetFieldID()); } } - } else { - /* OP_iread */ + } else if (opndOpcode == OP_iread) { IreadNode *iread = static_cast(opnd); ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(iread->GetTyIdx()); ASSERT(ty->GetKind() == kTypePointer, "expect pointer"); @@ -87,6 +88,11 @@ uint32 AArch64MemLayout::ComputeStackSpaceRequirementForCall(StmtNode &stmt, in ty = static_cast(ty)->GetFieldType(iread->GetFieldID()); } } + } else if ((opndOpcode == OP_ireadfpoff || opndOpcode == OP_ireadoff || opndOpcode == OP_dreadoff) && opnd->GetPrimType() == PTY_agg) { + ty = static_cast(cgFunc)->GetLmbcStructArgType(stmt, i); + } + if (ty == nullptr) { /* type mismatch */ + continue; } } CCLocInfo ploc; @@ -190,6 +196,7 @@ void AArch64MemLayout::LayoutVarargParams() { } void AArch64MemLayout::LayoutFormalParams() { +#if OLD_LMBC // TBD bool isLmbc = (be.GetMIRModule().GetFlavor() == kFlavorLmbc); if (isLmbc && mirFunction->GetFormalCount() == 0) { /* @@ -201,6 +208,7 @@ void AArch64MemLayout::LayoutFormalParams() { segArgsRegPassed.SetSize(mirFunction->GetOutParmSize()); return; } +#endif AArch64CallConvImpl parmLocator(be); CCLocInfo ploc; @@ -255,8 +263,10 @@ void AArch64MemLayout::LayoutFormalParams() { segArgsRegPassed.SetSize(static_cast(RoundUp(segArgsRegPassed.GetSize(), align))); symLoc->SetOffset(segArgsRegPassed.GetSize()); segArgsRegPassed.SetSize(segArgsRegPassed.GetSize() + size); +#if OLD_LMBC // TBD } else if (isLmbc) { segArgsRegPassed.SetSize(segArgsRegPassed.GetSize() + k8ByteSize); +#endif } } else { /* stack */ uint32 size; @@ -371,11 +381,15 @@ void AArch64MemLayout::LayoutReturnRef(std::vector &returnDelays, symLoc->SetOffset(segRefLocals.GetSize()); segRefLocals.SetSize(segRefLocals.GetSize() + be.GetTypeSize(tyIdx)); } +#if OLD_LMBC // TBD if (be.GetMIRModule().GetFlavor() == kFlavorLmbc) { segArgsToStkPass.SetSize(mirFunction->GetOutParmSize() + kDivide2 * k8ByteSize); } else { segArgsToStkPass.SetSize(FindLargestActualArea(structCopySize)); } +#else + segArgsToStkPass.SetSize(FindLargestActualArea(structCopySize)); +#endif maxParmStackSize = static_cast(segArgsToStkPass.GetSize()); if (Globals::GetInstance()->GetOptimLevel() == 0) { AssignSpillLocationsToPseudoRegisters(); @@ -527,14 +541,18 @@ uint64 AArch64MemLayout::StackFrameSize() const { uint64 total = segArgsRegPassed.GetSize() + static_cast(cgFunc)->SizeOfCalleeSaved() + GetSizeOfRefLocals() + locals().GetSize() + GetSizeOfSpillReg(); +#if OLD_LMBC // TBD if (cgFunc->GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif if (GetSizeOfGRSaveArea() > 0) { total += RoundUp(GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); } if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } +#if OLD_LMBC // TBD } +#endif /* * if the function does not have VLA nor alloca, diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 546c386c7e..9a0a3456b7 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -1115,9 +1115,11 @@ void AArch64GenProEpilog::AppendInstructionAllocateCallFrameDebug(AArch64reg reg ipoint = cgFunc.GetCurBB()->GetLastInsn(); cfiOffset = stackFrameSize; (void)InsertCFIDefCfaOffset(cfiOffset, *ipoint); +#if OLD_LMBC //TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { argsToStkPassSize -= (kDivide2 * k8ByteSize); } +#endif ipoint = &CreateAndAppendInstructionForAllocateCallFrame(argsToStkPassSize, reg0, reg1, rty); CHECK_FATAL(ipoint != nullptr, "ipoint should not be nullptr at this point"); cfiOffset = GetOffsetFromCFA(); @@ -1217,7 +1219,9 @@ void AArch64GenProEpilog::GeneratePushRegs() { Operand &spOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); +#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; +#endif if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; if (isLmbc) { @@ -1255,14 +1259,18 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); } else { +#endif offset = static_cast(memLayout->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass()); +#if OLD_LMBC // TBD } +#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignment; @@ -1323,18 +1331,22 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { } uint32 dataSizeBits = size * kBitsPerByte; uint32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif offset = static_cast(memlayout->GetGRSaveAreaBaseLoc()); /* SP reference */ if (memlayout->GetSizeOfGRSaveArea() % kAarch64StackPtrAlignment) { offset += size; /* End of area should be aligned. Hole between VR and GR area */ } +#if OLD_LMBC // TBD } else { offset = (UINT32_MAX - memlayout->GetSizeOfGRSaveArea()) + 1; /* FP reference */ if (memlayout->GetSizeOfGRSaveArea() % kAarch64StackPtrAlignment) { offset -= size; } } - uint32 grSize = (UINT32_MAX - offset) + 1; + uint32 grSize = -offset; +#endif uint32 start_regno = k8BitSize - (memlayout->GetSizeOfGRSaveArea() / size); ASSERT(start_regno <= k8BitSize, "Incorrect starting GR regno for GR Save Area"); for (uint32 i = start_regno + static_cast(R0); i < static_cast(R8); i++) { @@ -1345,11 +1357,15 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { } } Operand *stackLoc; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif stackLoc = &aarchCGFunc.CreateStkTopOpnd(offset + tmpOffset, dataSizeBits); +#if OLD_LMBC // TBD } else { stackLoc = aarchCGFunc.GenLmbcFpMemOperand(offset, size); } +#endif RegOperand ® = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(static_cast(i), k64BitSize, kRegTyInt); Insn &inst = @@ -1358,11 +1374,15 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { offset += size; } if (!CGOptions::UseGeneralRegOnly()) { +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif offset = static_cast(memlayout->GetVRSaveAreaBaseLoc()); +#if OLD_LMBC // TBD } else { offset = (UINT32_MAX - (memlayout->GetSizeOfVRSaveArea() + grSize)) + 1; } +#endif start_regno = k8BitSize - (memlayout->GetSizeOfVRSaveArea() / (size * k2BitSize)); ASSERT(start_regno <= k8BitSize, "Incorrect starting GR regno for VR Save Area"); for (uint32 i = start_regno + static_cast(V0); i < static_cast(V8); i++) { @@ -1373,11 +1393,15 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { } } Operand *stackLoc; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif stackLoc = &aarchCGFunc.CreateStkTopOpnd(offset + tmpOffset, dataSizeBits); +#if OLD_LMBC // TBD } else { stackLoc = aarchCGFunc.GenLmbcFpMemOperand(offset, size); } +#endif RegOperand ® = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(static_cast(i), k64BitSize, kRegTyFloat); Insn &inst = @@ -1479,7 +1503,9 @@ void AArch64GenProEpilog::GenerateProlog(BB &bb) { } if (useFP) { Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); +#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; +#endif int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; @@ -1682,7 +1708,10 @@ void AArch64GenProEpilog::AppendInstructionDeallocateCallFrameDebug(AArch64reg r * ldp/stp's imm should be within -512 and 504; * if ldp's imm > 504, we fall back to the ldp-add version */ +#if OLD_LMBC // TBD bool isLmbc = (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc); +#endif + bool isLmbc = false; if (cgFunc.HasVLAOrAlloca() || argsToStkPassSize == 0 || isLmbc) { int lmbcOffset = 0; if (isLmbc == false) { @@ -1769,14 +1798,18 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); } else { +#endif offset = static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass(); +#if OLD_LMBC // TBD } +#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignment; -- Gitee From c0bb6248bf749d760c0ee06e7f1d486aea46539f Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 20 Jun 2022 21:57:07 -0700 Subject: [PATCH 083/179] Turned some optimizations back off under lmbc and re-enabled some old code The OLD_LMBC define-disabled code caused coremark to fail execution. I have to put #define OLD_LMBC on aarch64_memlayout.cpp and aarch64_proepilog.cpp so coremark can work again. --- .../include/cg/aarch64/aarch64_phases.def | 34 +++++++++++-------- .../src/cg/aarch64/aarch64_memlayout.cpp | 2 ++ .../src/cg/aarch64/aarch64_proepilog.cpp | 5 ++- 3 files changed, 26 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 531e7f0535..e5627ecba3 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,16 +17,18 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + } /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); @@ -34,8 +36,10 @@ ADDTARGETPHASE("ico", CGOptions::DoICO()) ADDTARGETPHASE("cfgo", !GetMIRModule()->IsCModule() && CGOptions::DoCFGO()); - ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); - ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); +if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); + ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); +} ADDTARGETPHASE("clearrdinfo", (CGOptions::DoStoreLoadOpt()) || CGOptions::DoGlobalOpt()); ADDTARGETPHASE("prepeephole1", CGOptions::DoPrePeephole()); @@ -45,8 +49,10 @@ ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + } ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index b7ef7ae1ec..c35acefa9a 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -17,6 +17,8 @@ #include "becommon.h" #include "mir_nodes.h" +#define OLD_LMBC 1 + namespace maplebe { using namespace maple; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 9a0a3456b7..4b479338dc 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -16,6 +16,8 @@ #include "cg_option.h" #include "cgfunc.h" +#define OLD_LMBC 1 + namespace maplebe { using namespace maple; @@ -1710,8 +1712,9 @@ void AArch64GenProEpilog::AppendInstructionDeallocateCallFrameDebug(AArch64reg r */ #if OLD_LMBC // TBD bool isLmbc = (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc); -#endif +#else bool isLmbc = false; +#endif if (cgFunc.HasVLAOrAlloca() || argsToStkPassSize == 0 || isLmbc) { int lmbcOffset = 0; if (isLmbc == false) { -- Gitee From 119338177d30982fbfe64c5c2d6e713c5fd34168 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Wed, 22 Jun 2022 22:07:59 -0700 Subject: [PATCH 084/179] Handle addrofoff as operand of OP_asm --- .../maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 12 ++++++++++++ src/mapleall/maple_ir/src/bin_func_import.cpp | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 305c9f0338..5ea4af649b 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1256,6 +1256,18 @@ void AArch64CGFunc::SelectAsm(AsmNode &node) { } break; } + case OP_addrofoff: { + auto &addrofoffNode = static_cast(*node.Opnd(i)); + Operand *inOpnd = SelectAddrofoff(addrofoffNode, node); + listInputOpnd->PushOpnd(static_cast(*inOpnd)); + PrimType pType = addrofoffNode.GetPrimType(); + listInRegPrefix->stringList.push_back( + static_cast(&CreateStringOperand(GetRegPrefixFromPrimType(pType, inOpnd->GetSize(), str)))); + if (isOutputTempNode) { + rPlusOpnd.emplace_back(std::make_pair(inOpnd, pType)); + } + break; + } case OP_constval: { CHECK_FATAL(!isOutputTempNode, "Unexpect"); auto &constNode = static_cast(*node.Opnd(i)); diff --git a/src/mapleall/maple_ir/src/bin_func_import.cpp b/src/mapleall/maple_ir/src/bin_func_import.cpp index 580d52abc4..2d6db2162e 100644 --- a/src/mapleall/maple_ir/src/bin_func_import.cpp +++ b/src/mapleall/maple_ir/src/bin_func_import.cpp @@ -45,7 +45,7 @@ void BinaryMplImport::ImportFuncIdInfo(MIRFunction *func) { func->SetPuidxOrigin(static_cast(ReadNum())); ImportInfoVector(func->GetInfoVector(), func->InfoIsString()); if (mod.GetFlavor() == kFlavorLmbc) { - func->SetFrameSize(static_cast(ReadNum())); + func->SetFrameSize(static_cast(ReadNum())); } } -- Gitee From 1bb139a0851845aa3ee04f7d9c1b4cd2517afffd Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Fri, 24 Jun 2022 21:00:36 -0700 Subject: [PATCH 085/179] Handled more types of asm operands --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 5ea4af649b..c90dead0df 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1268,6 +1268,30 @@ void AArch64CGFunc::SelectAsm(AsmNode &node) { } break; } + case OP_ireadoff: { + IreadoffNode *ireadoff = static_cast(node.Opnd(i)); + Operand *inOpnd = SelectIreadoff(node, *ireadoff); + listInputOpnd->PushOpnd(static_cast(*inOpnd)); + PrimType pType = ireadoff->GetPrimType(); + listInRegPrefix->stringList.push_back( + static_cast(&CreateStringOperand(GetRegPrefixFromPrimType(pType, inOpnd->GetSize(), str)))); + if (isOutputTempNode) { + rPlusOpnd.emplace_back(std::make_pair(inOpnd, pType)); + } + break; + } + case OP_add: { + BinaryNode *addNode = static_cast(node.Opnd(i)); + Operand *inOpnd = SelectAdd(*addNode, *HandleExpr(*addNode, *addNode->Opnd(0)), *HandleExpr(*addNode, *addNode->Opnd(1)), node); + listInputOpnd->PushOpnd(static_cast(*inOpnd)); + PrimType pType = addNode->GetPrimType(); + listInRegPrefix->stringList.push_back( + static_cast(&CreateStringOperand(GetRegPrefixFromPrimType(pType, inOpnd->GetSize(), str)))); + if (isOutputTempNode) { + rPlusOpnd.emplace_back(std::make_pair(inOpnd, pType)); + } + break; + } case OP_constval: { CHECK_FATAL(!isOutputTempNode, "Unexpect"); auto &constNode = static_cast(*node.Opnd(i)); -- Gitee From 2c7be307da2613e8ae589d0cb00371b6f115f92d Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Sat, 25 Jun 2022 12:21:10 -0700 Subject: [PATCH 086/179] More edits to rebase to master branch --- src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 2 +- src/mapleall/maple_be/src/cg/cgfunc.cpp | 4 ++-- src/mapleall/maple_ir/include/bin_mpl_export.h | 1 - src/mapleall/maple_ir/src/bin_mpl_export.cpp | 3 +-- src/mapleall/maple_me/include/lmbc_memlayout.h | 4 +--- 5 files changed, 5 insertions(+), 9 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index c90dead0df..831e81a8f7 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -2133,7 +2133,7 @@ MIRType *AArch64CGFunc::LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector(static_cast(src)->GetRegisterNumber()); diff --git a/src/mapleall/maple_be/src/cg/cgfunc.cpp b/src/mapleall/maple_be/src/cg/cgfunc.cpp index 771970e588..0c083b7d5c 100644 --- a/src/mapleall/maple_be/src/cg/cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/cgfunc.cpp @@ -1587,7 +1587,7 @@ void CGFunc::CreateLmbcFormalParamInfo() { stackOffset += (typeSize + 7) & (-8); LmbcFormalParamInfo *info = GetMemoryPool()->New(primType, offset, typeSize); lmbcParamVec.push_back(info); - if (idx == 0 && lmbcFunc.IsFirstArgReturn()) { + if (idx == 0 && func.IsFirstArgReturn()) { info->SetIsReturn(); } if (type->GetKind() == kTypeStruct) { @@ -1604,7 +1604,7 @@ void CGFunc::CreateLmbcFormalParamInfo() { } } else { /* No aggregate pass by value here */ - for (StmtNode *stmt = lmbcFunc.GetBody()->GetFirst(); stmt != nullptr; stmt = stmt->GetNext()) { + for (StmtNode *stmt = func.GetBody()->GetFirst(); stmt != nullptr; stmt = stmt->GetNext()) { if (stmt == nullptr) { break; } diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 9cada84eb4..918c8e04eb 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,7 +181,6 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; - MIRFunction *curFunc = nullptr; size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; diff --git a/src/mapleall/maple_ir/src/bin_mpl_export.cpp b/src/mapleall/maple_ir/src/bin_mpl_export.cpp index e6f3e25d05..9bc2061fad 100644 --- a/src/mapleall/maple_ir/src/bin_mpl_export.cpp +++ b/src/mapleall/maple_ir/src/bin_mpl_export.cpp @@ -1110,7 +1110,6 @@ void BinaryMplExport::WriteSymField(uint64 contentIdx) { for (auto sit = GetMIRModule().GetSymbolDefOrder().begin(); sit != GetMIRModule().GetSymbolDefOrder().end(); ++sit) { MIRSymbol *s = GlobalTables::GetGsymTable().GetSymbolFromStidx(sit->Idx()); - ASSERT(s != nullptr, "null ptr check"); // Verify: all wpofake variables should have been deleted from globaltable ASSERT(!(s->IsWpoFakeParm() || s->IsWpoFakeRet()) || s->IsDeleted(), "wpofake var not deleted"); MIRStorageClass storageClass = s->GetStorageClass(); @@ -1242,7 +1241,7 @@ void BinaryMplExport::AppendAt(const std::string &name, int32 offset) { LogInfo::MapleLogger(kLlErr) << "Error while opening the binary file: " << name << '\n'; FATAL(kLncFatal, "Error while creating the binary file: %s\n", name.c_str()); } - int seekRet = fseek(f, static_cast(offset), SEEK_SET); + int seekRet = fseek(f, (long int)offset, SEEK_SET); CHECK_FATAL(seekRet == 0, "Call fseek failed."); size_t size = buf.size(); size_t k = fwrite(&buf[0], sizeof(uint8), size, f); diff --git a/src/mapleall/maple_me/include/lmbc_memlayout.h b/src/mapleall/maple_me/include/lmbc_memlayout.h index 833b357561..923c118665 100644 --- a/src/mapleall/maple_me/include/lmbc_memlayout.h +++ b/src/mapleall/maple_me/include/lmbc_memlayout.h @@ -42,9 +42,7 @@ class SymbolAlloc { public: SymbolAlloc() : mem_segment(nullptr), offset(0) {} - ~SymbolAlloc() { - mem_segment = nullptr; - } + ~SymbolAlloc() {} MemSegment *mem_segment; int32 offset; -- Gitee From f3a13dcc0d7e59fd69b464f97e6f89640f5e08a5 Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:16:12 -0700 Subject: [PATCH 087/179] Turn on globalopt for lmbc, but leave SSA opt off --- src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def | 6 ++---- src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp | 4 +++- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index e5627ecba3..856c48e6bd 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -49,10 +49,8 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); - } + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 4a2f257321..6b5d902cb4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,7 +412,9 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - CHECK_FATAL(false, "check case in ssa"); + if (cgFunc.GetCG()->IsLmbc() == false) { + CHECK_FATAL(false, "check case in ssa"); + } } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From 8f16dcb839618ca62885f4988d4cce283a01c701 Mon Sep 17 00:00:00 2001 From: William Chen Date: Mon, 13 Jun 2022 14:06:17 -0700 Subject: [PATCH 088/179] Do not optimize for ssa for physical regs. --- .../include/cg/aarch64/aarch64_phases.def | 22 +++++++++---------- .../src/cg/aarch64/aarch64_global.cpp | 4 +--- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 856c48e6bd..f11ca1435e 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,18 +17,16 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); - } + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 6b5d902cb4..4a2f257321 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,9 +412,7 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - if (cgFunc.GetCG()->IsLmbc() == false) { - CHECK_FATAL(false, "check case in ssa"); - } + CHECK_FATAL(false, "check case in ssa"); } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From c3a7bc0ad7ac6dde35e4c85261317a10b8633b85 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 20 Jun 2022 21:57:07 -0700 Subject: [PATCH 089/179] Turned some optimizations back off under lmbc and re-enabled some old code The OLD_LMBC define-disabled code caused coremark to fail execution. I have to put #define OLD_LMBC on aarch64_memlayout.cpp and aarch64_proepilog.cpp so coremark can work again. --- .../include/cg/aarch64/aarch64_phases.def | 28 +++++++++++-------- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index f11ca1435e..e5627ecba3 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,16 +17,18 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + } /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); @@ -47,8 +49,10 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + } ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); -- Gitee From f928387aaa8514aaf6e35543b1e3f9df20b3110a Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Sat, 25 Jun 2022 14:55:37 -0700 Subject: [PATCH 090/179] Fixed a rebase bug --- src/mapleall/maple_me/include/lmbc_memlayout.h | 12 +++--------- src/mapleall/maple_me/src/lmbc_lower.cpp | 4 ++-- 2 files changed, 5 insertions(+), 11 deletions(-) diff --git a/src/mapleall/maple_me/include/lmbc_memlayout.h b/src/mapleall/maple_me/include/lmbc_memlayout.h index 923c118665..83b59ba69f 100644 --- a/src/mapleall/maple_me/include/lmbc_memlayout.h +++ b/src/mapleall/maple_me/include/lmbc_memlayout.h @@ -38,14 +38,9 @@ typedef enum { class MemSegment; // describes where a symbol is allocated -class SymbolAlloc { - public: - SymbolAlloc() : mem_segment(nullptr), offset(0) {} - - ~SymbolAlloc() {} - - MemSegment *mem_segment; - int32 offset; +struct SymbolAlloc { + MemSegment *mem_segment = nullptr; + int32 offset = 0; }; // class SymbolAlloc // keeps track of the allocation of a memory segment @@ -59,7 +54,6 @@ class MemSegment { MemSegmentKind kind; int32 size; // size is negative if allocated offsets are negative - SymbolAlloc how_alloc; // this segment may be allocated inside another segment }; // class MemSegment class LMBCMemLayout { diff --git a/src/mapleall/maple_me/src/lmbc_lower.cpp b/src/mapleall/maple_me/src/lmbc_lower.cpp index 9ba84151e5..8cb339f657 100644 --- a/src/mapleall/maple_me/src/lmbc_lower.cpp +++ b/src/mapleall/maple_me/src/lmbc_lower.cpp @@ -25,8 +25,8 @@ PregIdx LMBCLowerer::GetSpecialRegFromSt(const MIRSymbol *sym) { if (storageClass == kScAuto) { CHECK(sym->GetStIndex() < memlayout->sym_alloc_table.size(), "index out of range in LMBCLowerer::GetSpecialRegFromSt"); - SymbolAlloc symalloc = memlayout->sym_alloc_table[sym->GetStIndex()]; - if (symalloc.mem_segment->kind == MS_FPbased) { + SymbolAlloc *symalloc = &memlayout->sym_alloc_table[sym->GetStIndex()]; + if (symalloc->mem_segment->kind == MS_FPbased) { specreg = -kSregFp; } else { CHECK_FATAL(false, "LMBCLowerer::LowerDread: bad memory layout for local variable"); -- Gitee From 983cac1d60d5893c3aceb5df159e39145f47a207 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Mon, 27 Jun 2022 14:41:54 -0700 Subject: [PATCH 091/179] Update for agg ret, caller/callee save offset. --- .../include/cg/aarch64/aarch64_cgfunc.h | 2 +- .../src/cg/aarch64/aarch64_cgfunc.cpp | 44 +++++++++++++------ .../src/cg/aarch64/aarch64_memlayout.cpp | 2 - .../src/cg/aarch64/aarch64_proepilog.cpp | 24 +++++----- 4 files changed, 45 insertions(+), 27 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index be3a3bae62..4d1e9370c2 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -130,7 +130,7 @@ class AArch64CGFunc : public CGFunc { uint32 LmbcFindTotalStkUsed(std::vector* paramList); uint32 LmbcTotalRegsUsed(); void LmbcSelectParmList(ListOperand *srcOpnds, bool isArgReturn); - bool LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src); + bool LmbcSmallAggForRet(BaseNode &bNode, Operand *src); bool LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src, std::vector **parmList); void SelectAggDassign(DassignNode &stmt) override; void SelectIassign(IassignNode &stmt) override; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 831e81a8f7..ae157979ef 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1487,6 +1487,12 @@ void AArch64CGFunc::SelectRegassign(RegassignNode &stmt, Operand &opnd0) { prev->SetMOP(MOP_xldrsw); } } + if (lhsSize == PTY_agg && (stmt.Opnd(0)->GetOpCode() == OP_ireadoff || stmt.Opnd(0)->GetOpCode() == OP_ireadfpoff)) { + PregIdx pregIdx = stmt.GetRegIdx(); + if ((-pregIdx) == kSregRetval0) { + return; // Already loaded to correct return registers + } + } } RegOperand *regOpnd = nullptr; PregIdx pregIdx = stmt.GetRegIdx(); @@ -2133,7 +2139,7 @@ MIRType *AArch64CGFunc::LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector(static_cast(src)->GetRegisterNumber()); @@ -2143,9 +2149,9 @@ bool AArch64CGFunc::LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src) { /* This blkassignoff is for struct return? */ uint32 loadSize; uint32 numRegs = 0; - if (bNode.GetNext()->GetOpCode() == OP_return) { - MIRStructType *ty = static_cast( - GlobalTables::GetTypeTable().GetTypeFromTyIdx(func->GetFuncRetStructTyIdx())); + if (static_cast(bNode).GetNext()->GetOpCode() == OP_return) { + MIRStructType *ty = static_cast(func->GetReturnType()); + uint32 tySize = GetBecommon().GetTypeSize(ty->GetTypeIndex()); uint32 fpregs = FloatParamRegRequired(ty, size); if (fpregs > 0) { /* pure floating point in agg */ @@ -2164,7 +2170,7 @@ bool AArch64CGFunc::LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src) { numRegs = 2; pTy = PTY_i64; size = k4ByteSize; - switch (bNode.blockSize) { + switch (tySize) { case 1: pTy = PTY_i8; break; @@ -2182,7 +2188,7 @@ bool AArch64CGFunc::LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src) { MemOperand &mem = CreateMemOpnd(regno, 0, size * kBitsPerByte); RegOperand *res = &GetOrCreatePhysicalRegisterOperand(R0, loadSize, kRegTyInt); SelectCopy(*res, pTy, mem, pTy); - if (bNode.blockSize > static_cast(k8ByteSize)) { + if (tySize > static_cast(k8ByteSize)) { MemOperand &newMem = CreateMemOpnd(regno, k8ByteSize, size * kBitsPerByte); res = &GetOrCreatePhysicalRegisterOperand(R1, loadSize, kRegTyInt); SelectCopy(*res, pTy, newMem, pTy); @@ -3103,9 +3109,20 @@ Operand *AArch64CGFunc::SelectIreadoff(const BaseNode &parent, IreadoffNode &ire auto *baseAddr = ireadoff.Opnd(0); auto *result = &CreateRegisterOperandOfType(primType); auto *addrOpnd = HandleExpr(ireadoff, *baseAddr); - auto &memOpnd = CreateMemOpnd(LoadIntoRegister(*addrOpnd, PTY_a64), offset, bitSize); - auto mop = PickLdInsn(bitSize, primType); - GetCurBB()->AppendInsn(GetCG()->BuildInstruction(mop, *result, memOpnd)); + if (primType == PTY_agg && parent.GetOpCode() == OP_regassign) { + auto &memOpnd = CreateMemOpnd(LoadIntoRegister(*addrOpnd, PTY_a64), offset, bitSize); + auto mop = PickLdInsn(64, PTY_a64); + GetCurBB()->AppendInsn(GetCG()->BuildInstruction(mop, *result, memOpnd)); + auto ®AssignNode = static_cast(parent); + PregIdx pIdx = regAssignNode.GetRegIdx(); + CHECK_FATAL(IsSpecialPseudoRegister(pIdx), "SelectIreadfpoff of agg"); + LmbcSmallAggForRet(const_cast(parent), addrOpnd); + // result not used + } else { + auto &memOpnd = CreateMemOpnd(LoadIntoRegister(*addrOpnd, PTY_a64), offset, bitSize); + auto mop = PickLdInsn(bitSize, primType); + GetCurBB()->AppendInsn(GetCG()->BuildInstruction(mop, *result, memOpnd)); + } return result; } @@ -3158,13 +3175,11 @@ Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode int32 offset = ireadoff.GetOffset(); PrimType primType = ireadoff.GetPrimType(); uint32 bytelen = GetPrimTypeSize(primType); -#if 1 - uint32 bitlen = bytelen * kBitsPerByte; -#endif RegType regty = GetRegTyFromPrimTy(primType); RegOperand *result = nullptr; if (offset >= 0) { -#if 1 +#if OLD_LMBC // TBD + uint32 bitlen = bytelen * kBitsPerByte; LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(offset); if (info->GetPrimType() == PTY_agg) { if (info->IsOnStack()) { @@ -3186,8 +3201,9 @@ Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode result = &GetOrCreatePhysicalRegisterOperand(static_cast(info->GetRegNO()), bitlen, regty); } } -#endif +#else CHECK_FATAL(0, "Invalid ireadfpoff offset"); +#endif } else { if (primType == PTY_agg) { #if OLD_LMBC // TBD diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index c35acefa9a..b7ef7ae1ec 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -17,8 +17,6 @@ #include "becommon.h" #include "mir_nodes.h" -#define OLD_LMBC 1 - namespace maplebe { using namespace maple; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 4b479338dc..5ce27d6c2d 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -16,8 +16,6 @@ #include "cg_option.h" #include "cgfunc.h" -#define OLD_LMBC 1 - namespace maplebe { using namespace maple; @@ -1261,18 +1259,21 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; -#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { +#if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); - } else { +#else + offset = static_cast(memLayout->RealStackFrameSize() - + (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen)/* FP/LR */) - + memLayout->GetSizeOfLocals() - + memLayout->SizeOfArgsToStackPass()); #endif + } else { offset = static_cast(memLayout->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass()); -#if OLD_LMBC // TBD } -#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignment; @@ -1801,18 +1802,21 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; -#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { +#if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); - } else { +#else + offset = static_cast(memLayout->RealStackFrameSize() - + (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen)/* FP/LR */) - + memLayout->GetSizeOfLocals() - + memLayout->SizeOfArgsToStackPass()); #endif + } else { offset = static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass(); -#if OLD_LMBC // TBD } -#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignment; -- Gitee From 8abf8317ef689bbf4eb074545c0d8f2d99768bd9 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 27 Jun 2022 18:36:42 -0700 Subject: [PATCH 092/179] For actual parameters corresponding to varargs, made lmbc lower struct parameters differently so as not to lose their type info --- src/mapleall/maple_me/src/lmbc_lower.cpp | 47 +++++++++++++++++++ .../maple_me/src/me_phase_manager.cpp | 3 ++ 2 files changed, 50 insertions(+) diff --git a/src/mapleall/maple_me/src/lmbc_lower.cpp b/src/mapleall/maple_me/src/lmbc_lower.cpp index 8cb339f657..c5913b036e 100644 --- a/src/mapleall/maple_me/src/lmbc_lower.cpp +++ b/src/mapleall/maple_me/src/lmbc_lower.cpp @@ -411,6 +411,53 @@ BlockNode *LMBCLowerer::LowerBlock(BlockNode *block) { } break; } + case OP_call: + case OP_icallproto: { + for (size_t i = 0; i < stmt->NumOpnds(); ++i) { + if (stmt->Opnd(i)->GetPrimType() != PTY_agg) { + stmt->SetOpnd(LowerExpr(stmt->Opnd(i)), i); + } else { + bool paramInPrototype = false; + MIRFuncType *funcType = nullptr; + if (stmt->GetOpCode() == OP_icallproto) { + IcallNode *icallproto = static_cast(stmt); + funcType = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallproto->GetRetTyIdx())); + paramInPrototype = (i-1) < funcType->GetParamTypeList().size(); + } else { + CallNode *callNode = static_cast(stmt); + MIRFunction *calleeFunc = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(callNode->GetPUIdx()); + funcType = calleeFunc->GetMIRFuncType(); + paramInPrototype = i < funcType->GetParamTypeList().size(); + } + if (paramInPrototype) { + stmt->SetOpnd(LowerExpr(stmt->Opnd(i)), i); + } else { // lower to iread so the type can be provided + if (stmt->Opnd(i)->GetOpCode() == OP_iread) { + IreadNode *iread = static_cast(stmt->Opnd(i)); + iread->SetOpnd(LowerExpr(iread->Opnd(0)), 0); + } else if (stmt->Opnd(i)->GetOpCode() == OP_dread) { + AddrofNode *addrof = static_cast(stmt->Opnd(i)); + FieldID fid = addrof->GetFieldID(); + addrof->SetOpCode(OP_addrof); + addrof->SetPrimType(GetExactPtrPrimType()); + addrof->SetFieldID(0); + MIRSymbol *symbol = func->GetLocalOrGlobalSymbol(addrof->GetStIdx()); + MIRPtrType ptrType(symbol->GetTyIdx(), GetExactPtrPrimType()); + ptrType.SetTypeAttrs(symbol->GetAttrs()); + TyIdx addrTyIdx = GlobalTables::GetTypeTable().GetOrCreateMIRType(&ptrType); + if (addrTyIdx == becommon->GetSizeOfTypeSizeTable()) { + MIRType *newType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(addrTyIdx); + becommon->UpdateTypeTable(*newType); + } + IreadNode *newIread = mirModule->CurFuncCodeMemPool()->New(OP_iread, PTY_agg, addrTyIdx, fid, LowerExpr(addrof)); + stmt->SetOpnd(newIread, i); + } + } + } + } + newblk->AddStatement(stmt); + break; + } default: { for (size_t i = 0; i < stmt->NumOpnds(); ++i) { stmt->SetOpnd(LowerExpr(stmt->Opnd(i)), i); diff --git a/src/mapleall/maple_me/src/me_phase_manager.cpp b/src/mapleall/maple_me/src/me_phase_manager.cpp index a0b5419a8e..92fb5a9f53 100644 --- a/src/mapleall/maple_me/src/me_phase_manager.cpp +++ b/src/mapleall/maple_me/src/me_phase_manager.cpp @@ -149,6 +149,9 @@ bool MeFuncPM::PhaseRun(maple::MIRModule &m) { if (func->GetBody() == nullptr) { continue; } + if (!IsQuiet()) { + LogInfo::MapleLogger() << ">>>> Generating LMBC for Function < " << func->GetName() << " > [" << i - 1 << "]\n"; + } m.SetCurFunction(func); cgLower.LowerFunc(*func); MemPool *layoutMp = memPoolCtrler.NewMemPool("layout mempool", true); -- Gitee From 994c33fe51c66e103821890633439d5a4a6ff48b Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 27 Jun 2022 21:09:51 -0700 Subject: [PATCH 093/179] Deleted LmbcSelectParmList() which no longer serves any purpose --- .../include/cg/aarch64/aarch64_cgfunc.h | 1 - .../src/cg/aarch64/aarch64_cgfunc.cpp | 53 ------------------- .../maple_me/src/me_phase_manager.cpp | 2 +- 3 files changed, 1 insertion(+), 55 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index 4d1e9370c2..f7b6cf6824 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -129,7 +129,6 @@ class AArch64CGFunc : public CGFunc { MemOperand *FixLargeMemOpnd(MOperator mOp, MemOperand &memOpnd, uint32 dSize, uint32 opndIdx); uint32 LmbcFindTotalStkUsed(std::vector* paramList); uint32 LmbcTotalRegsUsed(); - void LmbcSelectParmList(ListOperand *srcOpnds, bool isArgReturn); bool LmbcSmallAggForRet(BaseNode &bNode, Operand *src); bool LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src, std::vector **parmList); void SelectAggDassign(DassignNode &stmt) override; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index ae157979ef..e66bb24972 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -8579,56 +8579,6 @@ void AArch64CGFunc::IntrinsifyStringIndexOf(ListOperand &srcOpnds, const MIRSymb SetCurBB(*jointBB); } -/* Lmbc calls have no argument, they are all explicit iassignspoff or - blkassign. Info collected and to be emitted here */ -void AArch64CGFunc::LmbcSelectParmList(ListOperand *srcOpnds, bool isArgReturn) { - if (GetLmbcArgInfo() == nullptr) { - return; /* no arg */ - } - CHECK_FATAL(GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc, "To be called for Lmbc model only"); - MapleVector &args = GetLmbcCallArgs(); - MapleVector &types = GetLmbcCallArgTypes(); - MapleVector &offsets = GetLmbcCallArgOffsets(); - MapleVector ®s = GetLmbcCallArgNumOfRegs(); - int iCnt = 0; - int fCnt = 0; - for (size_t i = isArgReturn ? 1 : 0; i < args.size(); i++) { - RegType ty = args[i]->GetRegisterType(); - PrimType pTy = types[i]; - AArch64reg reg; - if (args[i]->IsOfIntClass() && (iCnt + regs[i]) <= static_cast(k8ByteSize)) { - reg = static_cast(R0 + iCnt++); - RegOperand *res = &GetOrCreatePhysicalRegisterOperand( - reg, GetPrimTypeSize(pTy) * kBitsPerByte, ty); - SelectCopy(*res, pTy, *args[i], pTy); - srcOpnds->PushOpnd(*res); - } else if (!args[i]->IsOfIntClass() && (fCnt + regs[i]) <= static_cast(k8ByteSize)) { - reg = static_cast(V0 + fCnt++); - RegOperand *res = &GetOrCreatePhysicalRegisterOperand( - reg, GetPrimTypeSize(pTy) * kBitsPerByte, ty); - SelectCopy(*res, pTy, *args[i], pTy); - srcOpnds->PushOpnd(*res); - } else { - uint32 pSize = GetPrimTypeSize(pTy); - Operand &memOpd = CreateMemOpnd(RSP, offsets[i], pSize); - GetCurBB()->AppendInsn(GetCG()->BuildInstruction(PickStInsn(pSize * kBitsPerByte, pTy), - *args[i], memOpd)); - } - } - /* Load x8 if 1st arg is for agg return */ - if (isArgReturn) { - AArch64reg reg = static_cast(R8); - RegOperand *res = &GetOrCreatePhysicalRegisterOperand(reg, - GetPrimTypeSize(PTY_a64) * kBitsPerByte, - kRegTyInt); - SelectCopy(*res, PTY_a64, *args[0], PTY_a64); - srcOpnds->PushOpnd(*res); - } - ResetLmbcArgInfo(); /* reset */ - ResetLmbcArgsInRegs(); - ResetLmbcTotalArgs(); -} - void AArch64CGFunc::SelectCall(CallNode &callNode) { MIRFunction *fn = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(callNode.GetPUIdx()); MIRSymbol *fsym = GetFunction().GetLocalOrGlobalSymbol(fn->GetStIdx(), false); @@ -8642,17 +8592,14 @@ void AArch64CGFunc::SelectCall(CallNode &callNode) { ListOperand *srcOpnds = CreateListOpnd(*GetFuncScopeAllocator()); if (GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { SetLmbcCallReturnType(nullptr); - bool largeStructRet = false; if (fn->IsFirstArgReturn()) { MIRPtrType *ptrTy = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(fn->GetFormalDefVec()[0].formalTyIdx)); MIRType *sTy = GlobalTables::GetTypeTable().GetTypeFromTyIdx(ptrTy->GetPointedTyIdx()); - largeStructRet = sTy->GetSize() > k16ByteSize; SetLmbcCallReturnType(sTy); } else { MIRType *ty = fn->GetReturnType(); SetLmbcCallReturnType(ty); } - LmbcSelectParmList(srcOpnds, largeStructRet); } bool callNative = false; if ((fsym->GetName() == "MCC_CallFastNative") || (fsym->GetName() == "MCC_CallFastNativeExt") || diff --git a/src/mapleall/maple_me/src/me_phase_manager.cpp b/src/mapleall/maple_me/src/me_phase_manager.cpp index 92fb5a9f53..a9b5b3e636 100644 --- a/src/mapleall/maple_me/src/me_phase_manager.cpp +++ b/src/mapleall/maple_me/src/me_phase_manager.cpp @@ -150,7 +150,7 @@ bool MeFuncPM::PhaseRun(maple::MIRModule &m) { continue; } if (!IsQuiet()) { - LogInfo::MapleLogger() << ">>>> Generating LMBC for Function < " << func->GetName() << " > [" << i - 1 << "]\n"; + LogInfo::MapleLogger() << ">>>> Generating LMBC for Function < " << func->GetName() << " >\n"; } m.SetCurFunction(func); cgLower.LowerFunc(*func); -- Gitee From 2a3ac3ef0a5fb195e384997816227cbe8baf15ca Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Tue, 28 Jun 2022 09:20:43 -0700 Subject: [PATCH 094/179] Fixed coredump at end of coremark. --- src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index e66bb24972..267fcb99b2 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -9554,7 +9554,7 @@ int32 AArch64CGFunc::GetBaseOffset(const SymbolAlloc &sa) { return baseOffset + sizeofFplr; } else if (sgKind == kMsSpillReg) { if (GetCG()->IsLmbc()) { - return symAlloc->GetOffset() + memLayout->SizeOfArgsToStackPass(); + return symAlloc->GetOffset() + memLayout->SizeOfArgsToStackPass() + sizeofFplr; } int32 baseOffset = symAlloc->GetOffset() + memLayout->SizeOfArgsRegisterPassed() + memLayout->GetSizeOfLocals() + memLayout->GetSizeOfRefLocals(); -- Gitee From 0da990b70ce5cd91d98b6aa11a9e330919fdb203 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Tue, 28 Jun 2022 14:08:17 -0700 Subject: [PATCH 095/179] Further changes for GetBaseOffset(). --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 20 +++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 267fcb99b2..8069169dcd 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -9544,20 +9544,32 @@ int32 AArch64CGFunc::GetBaseOffset(const SymbolAlloc &sa) { int32 offset = static_cast(symAlloc->GetOffset()); return offset; } else if (sgKind == kMsArgsRegPassed) { - int32 baseOffset = memLayout->GetSizeOfLocals() + symAlloc->GetOffset() + memLayout->GetSizeOfRefLocals(); + int32 baseOffset; + if (GetCG()->IsLmbc()) { + baseOffset = symAlloc->GetOffset() + memLayout->GetSizeOfRefLocals(); + } else { + baseOffset = memLayout->GetSizeOfLocals() + symAlloc->GetOffset() + + memLayout->GetSizeOfRefLocals(); + } return baseOffset + sizeofFplr; } else if (sgKind == kMsRefLocals) { int32 baseOffset = symAlloc->GetOffset() + memLayout->GetSizeOfLocals(); return baseOffset + sizeofFplr; } else if (sgKind == kMsLocals) { + if (GetCG()->IsLmbc()) { + CHECK_FATAL(false, "invalid lmbc's locals"); + } int32 baseOffset = symAlloc->GetOffset(); return baseOffset + sizeofFplr; } else if (sgKind == kMsSpillReg) { + int32 baseOffset; if (GetCG()->IsLmbc()) { - return symAlloc->GetOffset() + memLayout->SizeOfArgsToStackPass() + sizeofFplr; + baseOffset = symAlloc->GetOffset() + memLayout->SizeOfArgsRegisterPassed() + + memLayout->GetSizeOfRefLocals(); + } else { + baseOffset = symAlloc->GetOffset() + memLayout->SizeOfArgsRegisterPassed() + + memLayout->GetSizeOfLocals() + memLayout->GetSizeOfRefLocals(); } - int32 baseOffset = symAlloc->GetOffset() + memLayout->SizeOfArgsRegisterPassed() + memLayout->GetSizeOfLocals() + - memLayout->GetSizeOfRefLocals(); return baseOffset + sizeofFplr; } else if (sgKind == kMsArgsToStkPass) { /* this is for callers */ return static_cast(symAlloc->GetOffset()); -- Gitee From 8899caca51bff62a573ea56fed83282e5da37edd Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Tue, 28 Jun 2022 16:17:38 -0700 Subject: [PATCH 096/179] Fix for small agg return. --- src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 8069169dcd..969c2cde44 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1487,12 +1487,14 @@ void AArch64CGFunc::SelectRegassign(RegassignNode &stmt, Operand &opnd0) { prev->SetMOP(MOP_xldrsw); } } +#if 0 if (lhsSize == PTY_agg && (stmt.Opnd(0)->GetOpCode() == OP_ireadoff || stmt.Opnd(0)->GetOpCode() == OP_ireadfpoff)) { PregIdx pregIdx = stmt.GetRegIdx(); if ((-pregIdx) == kSregRetval0) { return; // Already loaded to correct return registers } } +#endif } RegOperand *regOpnd = nullptr; PregIdx pregIdx = stmt.GetRegIdx(); -- Gitee From 251578bc87eba12ef7df8aeeac767d853c2ccfca Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Thu, 30 Jun 2022 11:24:14 -0700 Subject: [PATCH 097/179] Some fixes for lmbc vararg memlayout --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 2 ++ .../src/cg/aarch64/aarch64_memlayout.cpp | 4 ---- .../src/cg/aarch64/aarch64_proepilog.cpp | 19 +++++++++++-------- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 969c2cde44..309141a2d9 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -10243,9 +10243,11 @@ void AArch64CGFunc::SelectCVaStart(const IntrinsiccallNode &intrnNode) { inReg++; } } +#if OLD_LMBC // TBD if (GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { stkSize += (inReg * k8ByteSize); } +#endif if (CGOptions::IsArm64ilp32()) { stkSize = static_cast(RoundUp(stkSize, k8ByteSize)); } else { diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index b7ef7ae1ec..bd5ad49758 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -541,18 +541,14 @@ uint64 AArch64MemLayout::StackFrameSize() const { uint64 total = segArgsRegPassed.GetSize() + static_cast(cgFunc)->SizeOfCalleeSaved() + GetSizeOfRefLocals() + locals().GetSize() + GetSizeOfSpillReg(); -#if OLD_LMBC // TBD if (cgFunc->GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { -#endif if (GetSizeOfGRSaveArea() > 0) { total += RoundUp(GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); } if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } -#if OLD_LMBC // TBD } -#endif /* * if the function does not have VLA nor alloca, diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 5ce27d6c2d..02f27d5e08 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -344,7 +344,9 @@ void AArch64GenProEpilog::GenStackGuard(BB &bb) { cgFunc.GetCurBB()->AppendInsn(insn); uint64 vArea = 0; - if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (cgFunc.GetMirModule().IsCModule() && + cgFunc.GetFunction().GetAttr(FUNCATTR_varargs) && + cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { AArch64MemLayout *ml = static_cast(cgFunc.GetMemlayout()); if (ml->GetSizeOfGRSaveArea() > 0) { vArea += RoundUp(ml->GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); @@ -401,7 +403,9 @@ BB &AArch64GenProEpilog::GenStackGuardCheckInsn(BB &bb) { cgFunc.GetCurBB()->AppendInsn(insn); uint64 vArea = 0; - if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (cgFunc.GetMirModule().IsCModule() && + cgFunc.GetFunction().GetAttr(FUNCATTR_varargs) && + cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { AArch64MemLayout *ml = static_cast(cgFunc.GetMemlayout()); if (ml->GetSizeOfGRSaveArea() > 0) { vArea += RoundUp(ml->GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); @@ -1219,9 +1223,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { Operand &spOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); -#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; -#endif if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; if (isLmbc) { @@ -1279,7 +1281,9 @@ void AArch64GenProEpilog::GeneratePushRegs() { offset -= kAarch64StackPtrAlignment; } - if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (cgFunc.GetMirModule().IsCModule() && + cgFunc.GetFunction().GetAttr(FUNCATTR_varargs) && + cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { /* GR/VR save areas are above the callee save area */ AArch64MemLayout *ml = static_cast(cgFunc.GetMemlayout()); auto saveareasize = static_cast(RoundUp(ml->GetSizeOfGRSaveArea(), kSizeOfPtr * k2BitSize) + @@ -1506,9 +1510,7 @@ void AArch64GenProEpilog::GenerateProlog(BB &bb) { } if (useFP) { Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); -#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; -#endif int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; @@ -1822,7 +1824,8 @@ void AArch64GenProEpilog::GeneratePopRegs() { offset -= kAarch64StackPtrAlignment; } - if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs) && + cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { /* GR/VR save areas are above the callee save area */ AArch64MemLayout *ml = static_cast(cgFunc.GetMemlayout()); auto saveareasize = static_cast(RoundUp(ml->GetSizeOfGRSaveArea(), kSizeOfPtr * k2BitSize) + -- Gitee From 634f730f86d28ee4578e47b141d0c7bfc90762ee Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Thu, 30 Jun 2022 23:04:08 -0700 Subject: [PATCH 098/179] Fixed some errors from rebasing to master --- src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h | 2 +- src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 2 +- src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index f7b6cf6824..b088d90e7b 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -102,7 +102,7 @@ class AArch64CGFunc : public CGFunc { return kRFLAG; } - MIRType *LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList) const; + MIRType *LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList); RegOperand &GetOrCreateResOperand(const BaseNode &parent, PrimType primType); MIRStructType *GetLmbcStructArgType(BaseNode &stmt, int32 argNo); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 309141a2d9..8947c86692 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -2211,7 +2211,7 @@ bool AArch64CGFunc::LmbcSmallAggForRet(BaseNode &bNode, Operand *src) { } /* return true if blkassignoff for return, false otherwise */ -bool AArch64CGFunc::LmbcSmallAggForCall(BlkassignoffNode &bNode, const Operand *src, std::vector **parmList) { +bool AArch64CGFunc::LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src, std::vector **parmList) { AArch64reg regno = static_cast(static_cast(src)->GetRegisterNumber()); if (IsBlkassignForPush(bNode)) { PrimType pTy = PTY_i64; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp index dd216e9c54..f8da94fb8c 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp @@ -1016,7 +1016,7 @@ bool AArch64Ebo::CombineMultiplyNeg(Insn *insn, OpndInfo *opndInfo, bool is64bit return false; } -bool AArch64Ebo::CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp) const { +bool AArch64Ebo::CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp) { if (opndInfo.insn == nullptr) { return false; } -- Gitee From d9e2d75aa0c2f4f9f1def177c238ca30de0094b6 Mon Sep 17 00:00:00 2001 From: William Chen Date: Wed, 8 Jun 2022 16:21:12 -0700 Subject: [PATCH 099/179] Changes from mplcglmbc10 --- src/mapleall/maple_ir/include/bin_mpl_export.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 918c8e04eb..9cada84eb4 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,6 +181,7 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; + MIRFunction *curFunc = nullptr; size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; -- Gitee From ad67a62a77fd484c50ce52c5174084f2d1fd17d7 Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:16:12 -0700 Subject: [PATCH 100/179] Turn on globalopt for lmbc, but leave SSA opt off --- src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def | 6 ++---- src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp | 4 +++- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index e5627ecba3..856c48e6bd 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -49,10 +49,8 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); - } + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 4a2f257321..6b5d902cb4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,7 +412,9 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - CHECK_FATAL(false, "check case in ssa"); + if (cgFunc.GetCG()->IsLmbc() == false) { + CHECK_FATAL(false, "check case in ssa"); + } } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From 9a65b2ceaa2f1f4b87919b2353a917a8eeb4c3d9 Mon Sep 17 00:00:00 2001 From: William Chen Date: Mon, 13 Jun 2022 14:06:17 -0700 Subject: [PATCH 101/179] Do not optimize for ssa for physical regs. --- .../include/cg/aarch64/aarch64_phases.def | 22 +++++++++---------- .../src/cg/aarch64/aarch64_global.cpp | 4 +--- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 856c48e6bd..f11ca1435e 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,18 +17,16 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); - } + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 6b5d902cb4..4a2f257321 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,9 +412,7 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - if (cgFunc.GetCG()->IsLmbc() == false) { - CHECK_FATAL(false, "check case in ssa"); - } + CHECK_FATAL(false, "check case in ssa"); } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From 625714f5715f077de8cf06dfb45a6a704a4cacdd Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Mon, 20 Jun 2022 15:49:32 -0700 Subject: [PATCH 102/179] Updating to "new" lmbc --- .../maple_be/src/cg/aarch64/aarch64_memlayout.cpp | 4 ++++ .../maple_be/src/cg/aarch64/aarch64_proepilog.cpp | 12 ++++++++++++ 2 files changed, 16 insertions(+) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index bd5ad49758..b7ef7ae1ec 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -541,14 +541,18 @@ uint64 AArch64MemLayout::StackFrameSize() const { uint64 total = segArgsRegPassed.GetSize() + static_cast(cgFunc)->SizeOfCalleeSaved() + GetSizeOfRefLocals() + locals().GetSize() + GetSizeOfSpillReg(); +#if OLD_LMBC // TBD if (cgFunc->GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif if (GetSizeOfGRSaveArea() > 0) { total += RoundUp(GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); } if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } +#if OLD_LMBC // TBD } +#endif /* * if the function does not have VLA nor alloca, diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 02f27d5e08..b71aab91fc 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -1223,7 +1223,9 @@ void AArch64GenProEpilog::GeneratePushRegs() { Operand &spOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); +#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; +#endif if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; if (isLmbc) { @@ -1261,6 +1263,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { #if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - @@ -1272,10 +1275,13 @@ void AArch64GenProEpilog::GeneratePushRegs() { memLayout->SizeOfArgsToStackPass()); #endif } else { +#endif offset = static_cast(memLayout->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass()); +#if OLD_LMBC // TBD } +#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignment; @@ -1510,7 +1516,9 @@ void AArch64GenProEpilog::GenerateProlog(BB &bb) { } if (useFP) { Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); +#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; +#endif int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; @@ -1804,6 +1812,7 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { #if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - @@ -1815,10 +1824,13 @@ void AArch64GenProEpilog::GeneratePopRegs() { memLayout->SizeOfArgsToStackPass()); #endif } else { +#endif offset = static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass(); +#if OLD_LMBC // TBD } +#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignment; -- Gitee From ee12596ff4474c1a2d6e02b9d1a0e2c2def31284 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 20 Jun 2022 21:57:07 -0700 Subject: [PATCH 103/179] Turned some optimizations back off under lmbc and re-enabled some old code The OLD_LMBC define-disabled code caused coremark to fail execution. I have to put #define OLD_LMBC on aarch64_memlayout.cpp and aarch64_proepilog.cpp so coremark can work again. --- .../include/cg/aarch64/aarch64_phases.def | 28 +++++++++++-------- .../src/cg/aarch64/aarch64_memlayout.cpp | 2 ++ .../src/cg/aarch64/aarch64_proepilog.cpp | 2 ++ 3 files changed, 20 insertions(+), 12 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index f11ca1435e..e5627ecba3 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,16 +17,18 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + } /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); @@ -47,8 +49,10 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + } ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index b7ef7ae1ec..c35acefa9a 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -17,6 +17,8 @@ #include "becommon.h" #include "mir_nodes.h" +#define OLD_LMBC 1 + namespace maplebe { using namespace maple; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index b71aab91fc..bf061b460f 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -16,6 +16,8 @@ #include "cg_option.h" #include "cgfunc.h" +#define OLD_LMBC 1 + namespace maplebe { using namespace maple; -- Gitee From 681a60ef6173820dedb81c0f180b7d420a2b140f Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Sat, 25 Jun 2022 12:21:10 -0700 Subject: [PATCH 104/179] More edits to rebase to master branch --- src/mapleall/maple_ir/include/bin_mpl_export.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 9cada84eb4..918c8e04eb 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,7 +181,6 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; - MIRFunction *curFunc = nullptr; size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; -- Gitee From 8ad989c5b428a1ba5dd3bd0eb44ee87bc842dd60 Mon Sep 17 00:00:00 2001 From: William Chen Date: Wed, 8 Jun 2022 16:21:12 -0700 Subject: [PATCH 105/179] Changes from mplcglmbc10 --- src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp | 1 - src/mapleall/maple_ir/include/bin_mpl_export.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index c35acefa9a..7c0610cc4f 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -552,7 +552,6 @@ uint64 AArch64MemLayout::StackFrameSize() const { if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } -#if OLD_LMBC // TBD } #endif diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 918c8e04eb..9cada84eb4 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,6 +181,7 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; + MIRFunction *curFunc = nullptr; size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; -- Gitee From ffe2f52d8ff326caee4e3c8687bb876eb0c65081 Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:16:12 -0700 Subject: [PATCH 106/179] Turn on globalopt for lmbc, but leave SSA opt off --- src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def | 6 ++---- src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp | 4 +++- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index e5627ecba3..856c48e6bd 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -49,10 +49,8 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); - } + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 4a2f257321..6b5d902cb4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,7 +412,9 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - CHECK_FATAL(false, "check case in ssa"); + if (cgFunc.GetCG()->IsLmbc() == false) { + CHECK_FATAL(false, "check case in ssa"); + } } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From a0d92cfc9c8cd7d468d3f8154f769ff61eebebf4 Mon Sep 17 00:00:00 2001 From: William Chen Date: Mon, 13 Jun 2022 14:06:17 -0700 Subject: [PATCH 107/179] Do not optimize for ssa for physical regs. --- .../include/cg/aarch64/aarch64_phases.def | 22 +++++++++---------- .../src/cg/aarch64/aarch64_global.cpp | 4 +--- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 856c48e6bd..f11ca1435e 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,18 +17,16 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); - } + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 6b5d902cb4..4a2f257321 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,9 +412,7 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - if (cgFunc.GetCG()->IsLmbc() == false) { - CHECK_FATAL(false, "check case in ssa"); - } + CHECK_FATAL(false, "check case in ssa"); } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From 0ec34c3c33ac8ba766b21a500e9af1711eb93823 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Mon, 20 Jun 2022 15:49:32 -0700 Subject: [PATCH 108/179] Updating to "new" lmbc --- src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index 7c0610cc4f..c35acefa9a 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -552,6 +552,7 @@ uint64 AArch64MemLayout::StackFrameSize() const { if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } +#if OLD_LMBC // TBD } #endif -- Gitee From b1c35ba63354563aa652b29a44da8513d13e5e30 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Fri, 17 Jun 2022 21:32:32 -0700 Subject: [PATCH 109/179] Fixed bug in importing typeAttrs field of MIRStructType Also, handle the export and import of MIRAddrofConst of local symbols properly. --- src/mapleall/maple_ir/include/bin_mpl_export.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 9cada84eb4..365a73b6a8 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,7 +181,9 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; + public: MIRFunction *curFunc = nullptr; + private: size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; -- Gitee From eb22f8bfde99c866a70a47ae045e7df29f620a4e Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 20 Jun 2022 21:57:07 -0700 Subject: [PATCH 110/179] Turned some optimizations back off under lmbc and re-enabled some old code The OLD_LMBC define-disabled code caused coremark to fail execution. I have to put #define OLD_LMBC on aarch64_memlayout.cpp and aarch64_proepilog.cpp so coremark can work again. --- .../include/cg/aarch64/aarch64_phases.def | 28 +++++++++++-------- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index f11ca1435e..e5627ecba3 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,16 +17,18 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + } /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); @@ -47,8 +49,10 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + } ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); -- Gitee From 99f3757308c8af2d77404cb3390f4c85c2881062 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Sat, 25 Jun 2022 14:55:37 -0700 Subject: [PATCH 111/179] Fixed a rebase bug --- src/mapleall/maple_ir/include/bin_mpl_export.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 365a73b6a8..17a00a9b30 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,8 +181,6 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; - public: - MIRFunction *curFunc = nullptr; private: size_t bufI = 0; std::vector buf; -- Gitee From ae2abfb0ca6062e9af07c8767f7e3e8f767b3ae5 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Mon, 27 Jun 2022 14:41:54 -0700 Subject: [PATCH 112/179] Update for agg ret, caller/callee save offset. --- .../maple_be/src/cg/aarch64/aarch64_memlayout.cpp | 2 -- .../maple_be/src/cg/aarch64/aarch64_proepilog.cpp | 10 ++-------- 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index c35acefa9a..b7ef7ae1ec 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -17,8 +17,6 @@ #include "becommon.h" #include "mir_nodes.h" -#define OLD_LMBC 1 - namespace maplebe { using namespace maple; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index bf061b460f..e397ca1fef 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -16,8 +16,6 @@ #include "cg_option.h" #include "cgfunc.h" -#define OLD_LMBC 1 - namespace maplebe { using namespace maple; @@ -1265,7 +1263,6 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; -#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { #if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - @@ -1278,12 +1275,11 @@ void AArch64GenProEpilog::GeneratePushRegs() { #endif } else { #endif + } else { offset = static_cast(memLayout->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass()); -#if OLD_LMBC // TBD } -#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignment; @@ -1814,7 +1810,6 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; -#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { #if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - @@ -1827,12 +1822,11 @@ void AArch64GenProEpilog::GeneratePopRegs() { #endif } else { #endif + } else { offset = static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen) /* for FP/LR */) - memLayout->SizeOfArgsToStackPass(); -#if OLD_LMBC // TBD } -#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignment; -- Gitee From 6b3078c14e5edf93cd7c6b3be1af8b6960702cf4 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Thu, 30 Jun 2022 11:24:14 -0700 Subject: [PATCH 113/179] Some fixes for lmbc vararg memlayout --- src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp | 4 ---- src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp | 4 ---- 2 files changed, 8 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index b7ef7ae1ec..bd5ad49758 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -541,18 +541,14 @@ uint64 AArch64MemLayout::StackFrameSize() const { uint64 total = segArgsRegPassed.GetSize() + static_cast(cgFunc)->SizeOfCalleeSaved() + GetSizeOfRefLocals() + locals().GetSize() + GetSizeOfSpillReg(); -#if OLD_LMBC // TBD if (cgFunc->GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { -#endif if (GetSizeOfGRSaveArea() > 0) { total += RoundUp(GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); } if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } -#if OLD_LMBC // TBD } -#endif /* * if the function does not have VLA nor alloca, diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index e397ca1fef..64e80fb9f5 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -1223,9 +1223,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { Operand &spOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); -#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; -#endif if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; if (isLmbc) { @@ -1514,9 +1512,7 @@ void AArch64GenProEpilog::GenerateProlog(BB &bb) { } if (useFP) { Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); -#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; -#endif int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; -- Gitee From 7c5451be8143aba0c6fc8813bc9a14cc44d447e7 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Fri, 1 Jul 2022 14:40:12 -0700 Subject: [PATCH 114/179] Fixed some rebase editing bugs --- src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 64e80fb9f5..02f27d5e08 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -1270,8 +1270,6 @@ void AArch64GenProEpilog::GeneratePushRegs() { (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen)/* FP/LR */) - memLayout->GetSizeOfLocals() - memLayout->SizeOfArgsToStackPass()); -#endif - } else { #endif } else { offset = static_cast(memLayout->RealStackFrameSize() - @@ -1815,8 +1813,6 @@ void AArch64GenProEpilog::GeneratePopRegs() { (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen)/* FP/LR */) - memLayout->GetSizeOfLocals() - memLayout->SizeOfArgsToStackPass()); -#endif - } else { #endif } else { offset = static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - -- Gitee From 28e21057ec62a699347671f75ed7a046584caf76 Mon Sep 17 00:00:00 2001 From: William Chen Date: Wed, 8 Jun 2022 16:21:12 -0700 Subject: [PATCH 115/179] Changes from mplcglmbc10 --- .../include/cg/aarch64/aarch64_cgfunc.h | 9 ++- .../src/cg/aarch64/aarch64_cgfunc.cpp | 55 +++++++++---------- .../src/cg/aarch64/aarch64_color_ra.cpp | 2 +- .../src/cg/aarch64/aarch64_proepilog.cpp | 12 ++-- src/mapleall/maple_be/src/cg/cgfunc.cpp | 15 +++-- src/mapleall/maple_be/src/cg/emit.cpp | 6 +- .../maple_ir/include/bin_mpl_export.h | 1 + src/mapleall/maple_ir/include/mir_type.h | 10 ---- src/mapleall/maple_ir/src/bin_func_export.cpp | 2 +- src/mapleall/maple_ir/src/bin_func_import.cpp | 34 ++++++------ src/mapleall/maple_ir/src/bin_mpl_import.cpp | 4 +- src/mapleall/maple_ir/src/mir_lower.cpp | 8 +-- src/mapleall/maple_me/src/irmap_build.cpp | 3 +- src/mapleall/maple_me/src/irmap_emit.cpp | 3 +- .../maple_me/src/me_phase_manager.cpp | 2 +- 15 files changed, 75 insertions(+), 91 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index 609947c35f..12c4194d5c 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -38,7 +38,7 @@ class LmbcArgInfo { MapleVector lmbcCallArgTypes; MapleVector lmbcCallArgOffsets; MapleVector lmbcCallArgNumOfRegs; // # of regs needed to complete struct - uint32 lmbcTotalStkUsed = -1; // remove when explicit addr for large agg is available + uint32 lmbcTotalStkUsed = -1; // TBD: remove when explicit addr for large agg is available }; class AArch64CGFunc : public CGFunc { @@ -129,8 +129,8 @@ class AArch64CGFunc : public CGFunc { uint32 LmbcFindTotalStkUsed(std::vector* paramList); uint32 LmbcTotalRegsUsed(); void LmbcSelectParmList(ListOperand *srcOpnds, bool isArgReturn); - bool LmbcSmallAggForRet(const BlkassignoffNode &bNode, const Operand *src); - bool LmbcSmallAggForCall(BlkassignoffNode &bNode, const Operand *src, std::vector **parmList); + bool LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src); + bool LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src, std::vector **parmList); void SelectAggDassign(DassignNode &stmt) override; void SelectIassign(IassignNode &stmt) override; void SelectIassignoff(IassignoffNode &stmt) override; @@ -492,8 +492,7 @@ class AArch64CGFunc : public CGFunc { void AssignLmbcFormalParams() override; void LmbcGenSaveSpForAlloca() override; MemOperand *GenLmbcFpMemOperand(int32 offset, uint32 byteSize, AArch64reg base = RFP); - RegOperand *GenLmbcParamLoad(int32 offset, uint32 byteSize, RegType regType, - PrimType primType, AArch64reg baseRegno = RFP); + RegOperand *GenLmbcParamLoad(int32 offset, uint32 byteSize, RegType regType, PrimType primType, AArch64reg baseRegno = RFP); RegOperand *LmbcStructReturnLoad(int32 offset); Operand *GetBaseReg(const AArch64SymbolAlloc &symAlloc); int32 GetBaseOffset(const SymbolAlloc &symAlloc) override; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index d08b9a778c..6ec89b8234 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1987,9 +1987,8 @@ void AArch64CGFunc::SelectIassignfpoff(IassignFPoffNode &stmt, Operand &opnd) { MIRType *rType = GetLmbcCallReturnType(); bool isPureFpStruct = false; uint32 numRegs = 0; - if (rType && rType->GetPrimType() == PTY_agg && opnd.IsRegister() && - static_cast(opnd).IsPhysicalRegister()) { - CHECK_FATAL(rType->GetSize() <= k16BitSize, "SelectIassignfpoff invalid agg size"); + if (rType && rType->GetPrimType() == PTY_agg && opnd.IsRegister() && static_cast(opnd).IsPhysicalRegister()) { + CHECK_FATAL(rType->GetSize() <= 16, "SelectIassignfpoff invalid agg size"); uint32 fpSize; numRegs = FloatParamRegRequired(static_cast(rType), fpSize); if (numRegs > 0) { @@ -2000,8 +1999,8 @@ void AArch64CGFunc::SelectIassignfpoff(IassignFPoffNode &stmt, Operand &opnd) { uint32 byteSize = GetPrimTypeSize(primType); uint32 bitlen = byteSize * kBitsPerByte; if (isPureFpStruct) { - for (uint32 i = 0 ; i < numRegs; ++i) { - MemOperand *memOpnd = GenLmbcFpMemOperand(offset + static_cast(i * byteSize), byteSize); + for (int i = 0 ; i < numRegs; ++i) { + MemOperand *memOpnd = GenLmbcFpMemOperand(offset + (i * byteSize), byteSize); RegOperand &srcOpnd = GetOrCreatePhysicalRegisterOperand(AArch64reg(V0 + i), bitlen, kRegTyFloat); MOperator mOp = PickStInsn(bitlen, primType); Insn &store = GetCG()->BuildInstruction(mOp, srcOpnd, *memOpnd); @@ -2044,8 +2043,8 @@ void AArch64CGFunc::SelectIassignspoff(PrimType pTy, int32 offset, Operand &opnd } /* Search for CALL/ICALL/ICALLPROTO node, must be called from a blkassignoff node */ -MIRType *AArch64CGFunc::LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList) const { - for (; stmt != nullptr; stmt = stmt->GetNext()) { +MIRType *AArch64CGFunc::LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList) { + for ( ; stmt != nullptr; stmt = stmt->GetNext()) { if (stmt->GetOpCode() == OP_call || stmt->GetOpCode() == OP_icallproto) { break; } @@ -2161,7 +2160,7 @@ bool AArch64CGFunc::LmbcSmallAggForCall(BlkassignoffNode &bNode, const Operand * MemOperand &mem = CreateMemOpnd(regno, s, size * kBitsPerByte); RegOperand *res = &CreateVirtualRegisterOperand(NewVReg(kRegTyFloat, size)); SelectCopy(*res, pTy, mem, pTy); - SetLmbcArgInfo(res, pTy, 0, static_cast(fpregs)); + SetLmbcArgInfo(res, pTy, 0, fpregs); IncLmbcArgsInRegs(kRegTyFloat); } IncLmbcTotalArgs(); @@ -2209,7 +2208,7 @@ uint32 AArch64CGFunc::LmbcFindTotalStkUsed(std::vector *paramList) { CCLocInfo pLoc; for (TyIdx tyIdx : *paramList) { MIRType *ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(tyIdx); - (void)parmlocator.LocateNextParm(*ty, pLoc); + parmlocator.LocateNextParm(*ty, pLoc); } return 0; } @@ -2225,12 +2224,12 @@ uint32 AArch64CGFunc::LmbcTotalRegsUsed() { uint32 fCnt = 0; for (uint32 i = 0; i < regs.size(); i++) { if (IsPrimitiveInteger(types[i])) { - if ((iCnt + static_cast(regs[i])) <= k8ByteSize) { - iCnt += static_cast(regs[i]); + if ((iCnt + regs[i]) <= k8ByteSize) { + iCnt += regs[i]; }; } else { - if ((fCnt + static_cast(regs[i])) <= k8ByteSize) { - fCnt += static_cast(regs[i]); + if ((fCnt + regs[i]) <= k8ByteSize) { + fCnt += regs[i]; }; } } @@ -2277,7 +2276,7 @@ void AArch64CGFunc::SelectBlkassignoff(BlkassignoffNode &bNode, Operand *src) opndVec.push_back(regResult); /* result */ opndVec.push_back(PrepareMemcpyParamOpnd(offset, *dest)); /* param 0 */ opndVec.push_back(src); /* param 1 */ - opndVec.push_back(PrepareMemcpyParamOpnd(static_cast(static_cast(bNode.blockSize)))); /* param 2 */ + opndVec.push_back(PrepareMemcpyParamOpnd(bNode.blockSize));/* param 2 */ SelectLibCall("memcpy", opndVec, PTY_a64, PTY_a64); } @@ -2681,7 +2680,7 @@ void AArch64CGFunc::SelectReturnSendOfStructInRegs(BaseNode *x) { /* generate move to regs for agg return */ AArch64CallConvImpl parmlocator(GetBecommon()); CCLocInfo pLoc; - (void)parmlocator.LocateNextParm(*mirType, pLoc, true, GetBecommon().GetMIRModule().CurFunction()); + parmlocator.LocateNextParm(*mirType, pLoc, true, GetBecommon().GetMIRModule().CurFunction()); /* aggregates are 8 byte aligned. */ Operand *rhsmemopnd = nullptr; RegOperand *result[kFourRegister]; /* up to 2 int or 4 fp */ @@ -3203,8 +3202,8 @@ RegOperand *AArch64CGFunc::LmbcStructReturnLoad(int32 offset) { if (numFpRegs > 0) { PrimType pType = (fpSize <= k4ByteSize) ? PTY_f32 : PTY_f64; for (int32 i = (numFpRegs - kOneRegister); i > 0; --i) { - result = GenLmbcParamLoad(offset + (i * static_cast(fpSize)), fpSize, kRegTyFloat, pType); - AArch64reg regNo = static_cast(V0 + static_cast(i)); + result = GenLmbcParamLoad(offset + (i * fpSize), fpSize, kRegTyFloat, pType); + AArch64reg regNo = static_cast(V0 + i); RegOperand *reg = &GetOrCreatePhysicalRegisterOperand(regNo, fpSize * kBitsPerByte, kRegTyFloat); SelectCopy(*reg, pType, *result, pType); Insn &pseudo = GetCG()->BuildInstruction(MOP_pseudo_ret_float, *reg); @@ -3216,7 +3215,7 @@ RegOperand *AArch64CGFunc::LmbcStructReturnLoad(int32 offset) { } else if (sz <= k8ByteSize) { result = GenLmbcParamLoad(offset, k8ByteSize, kRegTyInt, PTY_i64); } else if (sz <= k16ByteSize) { - result = GenLmbcParamLoad(offset + k8ByteSizeInt, k8ByteSize, kRegTyInt, PTY_i64); + result = GenLmbcParamLoad(offset + k8ByteSize, k8ByteSize, kRegTyInt, PTY_i64); RegOperand *r1 = &GetOrCreatePhysicalRegisterOperand(R1, k8ByteSize * kBitsPerByte, kRegTyInt); SelectCopy(*r1, PTY_i64, *result, PTY_i64); Insn &pseudo = GetCG()->BuildInstruction(MOP_pseudo_ret_int, *r1); @@ -6534,10 +6533,10 @@ void AArch64CGFunc::AssignLmbcFormalParams() { param->SetRegNO(0); } else { param->SetRegNO(fpReg); - if (!param->HasRegassign()) { + if (param->HasRegassign() == false) { uint32 bytelen = GetPrimTypeSize(primType); uint32 bitlen = bytelen * kBitsPerByte; - MemOperand *mOpnd = GenLmbcFpMemOperand(static_cast(offset), bytelen); + MemOperand *mOpnd = GenLmbcFpMemOperand(offset, bytelen); RegOperand &src = GetOrCreatePhysicalRegisterOperand(AArch64reg(fpReg), bitlen, kRegTyFloat); MOperator mOp = PickStInsn(bitlen, primType); Insn &store = GetCG()->BuildInstruction(mOp, src, *mOpnd); @@ -6561,10 +6560,10 @@ void AArch64CGFunc::AssignLmbcFormalParams() { } else { param->SetRegNO(intReg); param->SetIsOnStack(); - param->SetOnStackOffset(((intReg - R0 + fpReg) - V0) * k8ByteSize); + param->SetOnStackOffset((intReg - R0 + fpReg - V0) * k8ByteSize); uint32 bytelen = GetPrimTypeSize(PTY_a64); uint32 bitlen = bytelen * kBitsPerByte; - MemOperand *mOpnd = GenLmbcFpMemOperand(static_cast(param->GetOnStackOffset()), bytelen); + MemOperand *mOpnd = GenLmbcFpMemOperand(param->GetOnStackOffset(), bytelen); RegOperand &src = GetOrCreatePhysicalRegisterOperand(AArch64reg(intReg), bitlen, kRegTyInt); MOperator mOp = PickStInsn(bitlen, PTY_a64); Insn &store = GetCG()->BuildInstruction(mOp, src, *mOpnd); @@ -6623,13 +6622,14 @@ void AArch64CGFunc::AssignLmbcFormalParams() { } void AArch64CGFunc::LmbcGenSaveSpForAlloca() { - if (GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc || !HasVLAOrAlloca()) { + if (GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc || HasVLAOrAlloca() == false) { return; } Operand &spOpnd = GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); RegOperand &spSaveOpnd = CreateVirtualRegisterOperand(NewVReg(kRegTyInt, kSizeOfPtr)); Insn &save = GetCG()->BuildInstruction(MOP_xmovrr, spSaveOpnd, spOpnd); GetFirstBB()->AppendInsn(save); + //save.SetFrameDef(true); for (auto *retBB : GetExitBBsVec()) { Insn &restore = GetCG()->BuildInstruction(MOP_xmovrr, spOpnd, spSaveOpnd); retBB->AppendInsn(restore); @@ -7943,8 +7943,7 @@ size_t AArch64CGFunc::SelectParmListGetStructReturnSize(StmtNode &naryNode) { } } else if (naryNode.GetOpCode() == OP_icallproto) { IcallNode &icallProto = static_cast(naryNode); - MIRFuncType *funcTy = static_cast( - GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallProto.GetRetTyIdx())); + MIRFuncType *funcTy = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallProto.GetRetTyIdx())); if (funcTy->FirstArgReturn()) { MIRType *ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(funcTy->GetNthParamType(0)); return GetBecommon().GetTypeSize(static_cast(ty)->GetPointedTyIdx()); @@ -8071,8 +8070,7 @@ void AArch64CGFunc::SelectParmList(StmtNode &naryNode, ListOperand &srcOpnds, bo firstArgReturn = callee->IsFirstArgReturn(); } else if (naryNode.GetOpCode() == OP_icallproto) { IcallNode *icallnode = &static_cast(naryNode); - MIRFuncType *funcType = static_cast( - GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallnode->GetRetTyIdx())); + MIRFuncType *funcType = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallnode->GetRetTyIdx())); firstArgReturn = funcType->FirstArgReturn(); } BB *curBBrecord = GetCurBB(); @@ -8621,8 +8619,7 @@ void AArch64CGFunc::SelectCall(CallNode &callNode) { SetLmbcCallReturnType(nullptr); bool largeStructRet = false; if (fn->IsFirstArgReturn()) { - MIRPtrType *ptrTy = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx( - fn->GetFormalDefVec()[0].formalTyIdx)); + MIRPtrType *ptrTy = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(fn->GetFormalDefVec()[0].formalTyIdx)); MIRType *sTy = GlobalTables::GetTypeTable().GetTypeFromTyIdx(ptrTy->GetPointedTyIdx()); largeStructRet = sTy->GetSize() > k16ByteSize; SetLmbcCallReturnType(sTy); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp index 6b704c77cb..2b04790cd5 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp @@ -4979,7 +4979,7 @@ bool GraphColorRegAllocator::AllocateRegisters() { MarkCalleeSaveRegs(); - if (!seenFP) { + if (seenFP == false) { cgFunc->UnsetSeenFP(); } if (GCRA_DUMP) { diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index c305f3acab..9b4b49c699 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -1226,7 +1226,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { } else { immOpnd = &aarchCGFunc.CreateImmOperand(argsToStkPassSize, k32BitSize, true); } - if (!isLmbc || cgFunc.SeenFP() || cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (isLmbc == false || cgFunc.SeenFP() || cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { aarchCGFunc.SelectAdd(fpOpnd, spOpnd, *immOpnd, PTY_u64); } cgFunc.GetCurBB()->GetLastInsn()->SetFrameDef(true); @@ -1256,8 +1256,8 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { - offset = static_cast((memLayout->RealStackFrameSize() - - aarchCGFunc.SizeOfCalleeSaved()) - memLayout->GetSizeOfLocals()); + offset = static_cast(memLayout->RealStackFrameSize() - + aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); } else { offset = static_cast((memLayout->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - memLayout->SizeOfArgsToStackPass()); /* for FP/LR */ @@ -1684,7 +1684,7 @@ void AArch64GenProEpilog::AppendInstructionDeallocateCallFrameDebug(AArch64reg r bool isLmbc = (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc); if (cgFunc.HasVLAOrAlloca() || argsToStkPassSize == 0 || isLmbc) { int lmbcOffset = 0; - if (!isLmbc) { + if (isLmbc == false) { stackFrameSize -= argsToStkPassSize; } else { lmbcOffset = argsToStkPassSize - (kDivide2 * k8ByteSize); @@ -1768,8 +1768,8 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { - offset = static_cast((memLayout->RealStackFrameSize() - - aarchCGFunc.SizeOfCalleeSaved()) - memLayout->GetSizeOfLocals()); + offset = static_cast(memLayout->RealStackFrameSize() - + aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); } else { offset = static_cast((static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - /* for FP/LR */ diff --git a/src/mapleall/maple_be/src/cg/cgfunc.cpp b/src/mapleall/maple_be/src/cg/cgfunc.cpp index 9676b442fd..b227112c30 100644 --- a/src/mapleall/maple_be/src/cg/cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/cgfunc.cpp @@ -1565,16 +1565,16 @@ void CGFunc::CreateLmbcFormalParamInfo() { PrimType primType; uint32 offset; uint32 typeSize; - MIRFunction &lmbcFunc = GetFunction(); - if (lmbcFunc.GetFormalCount() > 0) { + MIRFunction &func = GetFunction(); + if (func.GetFormalCount() > 0) { /* Whenever lmbc cannot delete call type info, the prototype is available */ uint32 stackOffset = 0; - for (size_t idx = 0; idx < lmbcFunc.GetFormalCount(); ++idx) { - MIRSymbol *sym = lmbcFunc.GetFormal(idx); + for (size_t idx = 0; idx < func.GetFormalCount(); ++idx) { + MIRSymbol *sym = func.GetFormal(idx); MIRType *type; TyIdx tyIdx; if (sym) { - tyIdx = lmbcFunc.GetFormalDefVec()[idx].formalTyIdx; + tyIdx = func.GetFormalDefVec()[idx].formalTyIdx; type = GlobalTables::GetTypeTable().GetTypeFromTyIdx(tyIdx); } else { FormalDef vec = const_cast(GetBecommon().GetMIRModule().CurFunction())->GetFormalDefAt(idx); @@ -1637,7 +1637,7 @@ void CGFunc::CreateLmbcFormalParamInfo() { ); /* When a scalar param address is taken, its regassign is not in the 1st block */ - for (StmtNode *stmt = lmbcFunc.GetBody()->GetFirst(); stmt != nullptr; stmt = stmt->GetNext()) { + for (StmtNode *stmt = func.GetBody()->GetFirst(); stmt != nullptr; stmt = stmt->GetNext()) { if (stmt == nullptr) { break; } @@ -1656,8 +1656,7 @@ void CGFunc::CreateLmbcFormalParamInfo() { if (ireadNode->GetOffset() < 0) { continue; } - LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(static_cast(ireadNode->GetOffset())); - ASSERT_NOT_NULL(info); + LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(ireadNode->GetOffset()); info->SetHasRegassign(); } diff --git a/src/mapleall/maple_be/src/cg/emit.cpp b/src/mapleall/maple_be/src/cg/emit.cpp index f4023e2d37..7789f53216 100644 --- a/src/mapleall/maple_be/src/cg/emit.cpp +++ b/src/mapleall/maple_be/src/cg/emit.cpp @@ -2170,9 +2170,9 @@ void Emitter::EmitGlobalVar(const MIRSymbol &globalVar) { void Emitter::EmitGlobalVars(std::vector> &globalVars) { if (GetCG()->IsLmbc() && GetCG()->GetGP() != nullptr) { - (void)Emit(asmInfo->GetLocal()).Emit("\t").Emit(GetCG()->GetGP()->GetName()).Emit("\n"); - (void)Emit(asmInfo->GetComm()).Emit("\t").Emit(GetCG()->GetGP()->GetName()); - (void)Emit(", ").Emit(GetCG()->GetMIRModule()->GetGlobalMemSize()).Emit(", ").Emit("8\n"); + Emit(asmInfo->GetLocal()).Emit("\t").Emit(GetCG()->GetGP()->GetName()).Emit("\n"); + Emit(asmInfo->GetComm()).Emit("\t").Emit(GetCG()->GetGP()->GetName()); + Emit(", ").Emit(GetCG()->GetMIRModule()->GetGlobalMemSize()).Emit(", ").Emit("8\n"); } /* load globalVars profile */ if (globalVars.empty()) { diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 918c8e04eb..9cada84eb4 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,6 +181,7 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; + MIRFunction *curFunc = nullptr; size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; diff --git a/src/mapleall/maple_ir/include/mir_type.h b/src/mapleall/maple_ir/include/mir_type.h index b8724b2d7e..fda53fe94b 100644 --- a/src/mapleall/maple_ir/include/mir_type.h +++ b/src/mapleall/maple_ir/include/mir_type.h @@ -1205,14 +1205,6 @@ class MIRStructType : public MIRType { isImported = flag; } - bool IsUsed() const { - return isUsed; - } - - void SetIsUsed(bool flag) { - isUsed = flag; - } - bool IsCPlusPlus() const { return isCPlusPlus; } @@ -1384,7 +1376,6 @@ class MIRStructType : public MIRType { vTableMethods.clear(); iTableMethods.clear(); isImported = false; - isUsed = false; hasVolatileField = false; hasVolatileFieldSet = false; } @@ -1487,7 +1478,6 @@ class MIRStructType : public MIRType { // implementation functions, For interfaces, they are abstact functions. // Weak indicates the actual definition is in another module. bool isImported = false; - bool isUsed = false; bool isCPlusPlus = false; // empty struct in C++ has size 1 byte mutable bool hasVolatileField = false; // for caching computed value mutable bool hasVolatileFieldSet = false; // if true, just read hasVolatileField; diff --git a/src/mapleall/maple_ir/src/bin_func_export.cpp b/src/mapleall/maple_ir/src/bin_func_export.cpp index f558db8106..a3b0190854 100644 --- a/src/mapleall/maple_ir/src/bin_func_export.cpp +++ b/src/mapleall/maple_ir/src/bin_func_export.cpp @@ -88,7 +88,7 @@ void BinaryMplExport::OutputLocalSymbol(MIRSymbol *sym) { void BinaryMplExport::OutputPreg(MIRPreg *preg) { if (preg->GetPregNo() < 0) { WriteNum(kBinSpecialReg); - Write(static_cast(-preg->GetPregNo())); + Write(-preg->GetPregNo()); return; } std::unordered_map::iterator it = localPregMark.find(preg); diff --git a/src/mapleall/maple_ir/src/bin_func_import.cpp b/src/mapleall/maple_ir/src/bin_func_import.cpp index 500e426afe..6fdb94c85c 100644 --- a/src/mapleall/maple_ir/src/bin_func_import.cpp +++ b/src/mapleall/maple_ir/src/bin_func_import.cpp @@ -50,8 +50,8 @@ void BinaryMplImport::ImportFuncIdInfo(MIRFunction *func) { } void BinaryMplImport::ImportBaseNode(Opcode &o, PrimType &typ) { - o = static_cast(Read()); - typ = static_cast(Read()); + o = (Opcode)Read(); + typ = (PrimType)Read(); } MIRSymbol *BinaryMplImport::ImportLocalSymbol(MIRFunction *func) { @@ -61,8 +61,8 @@ MIRSymbol *BinaryMplImport::ImportLocalSymbol(MIRFunction *func) { } if (tag < 0) { CHECK_FATAL(static_cast(-tag) < localSymTab.size(), "index out of bounds"); - return localSymTab.at(static_cast(-tag)); - } + return localSymTab.at(-tag); + } CHECK_FATAL(tag == kBinSymbol, "expecting kBinSymbol in ImportLocalSymbol()"); MIRSymbol *sym = func->GetSymTab()->CreateSymbol(kScopeLocal); localSymTab.push_back(sym); @@ -99,11 +99,11 @@ PregIdx BinaryMplImport::ImportPreg(MIRFunction *func) { } if (tag < 0) { CHECK_FATAL(static_cast(-tag) < localPregTab.size(), "index out of bounds"); - return localPregTab.at(static_cast(-tag)); + return localPregTab.at(-tag); } CHECK_FATAL(tag == kBinPreg, "expecting kBinPreg in ImportPreg()"); - PrimType primType = static_cast(Read()); + PrimType primType = (PrimType)Read(); PregIdx pidx = func->GetPregTab()->CreatePreg(primType); localPregTab.push_back(pidx); return pidx; @@ -116,7 +116,7 @@ LabelIdx BinaryMplImport::ImportLabel(MIRFunction *func) { } if (tag < 0) { CHECK_FATAL(static_cast(-tag) < localLabelTab.size(), "index out of bounds"); - return localLabelTab.at(static_cast(-tag)); + return localLabelTab.at(-tag); } CHECK_FATAL(tag == kBinLabel, "kBinLabel expected in ImportLabel()"); @@ -267,8 +267,8 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { case OP_floor: case OP_trunc: { TypeCvtNode *typecvtNode = mod.CurFuncCodeMemPool()->New(op, typ); - typecvtNode->SetFromType(static_cast(Read())); - typecvtNode->SetOpnd(ImportExpression(func), kFirstOpnd); + typecvtNode->SetFromType((PrimType)Read()); + typecvtNode->SetOpnd(ImportExpression(func), 0); return typecvtNode; } case OP_retype: { @@ -307,10 +307,10 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { } case OP_depositbits: { DepositbitsNode *dbNode = mod.CurFuncCodeMemPool()->New(op, typ); - dbNode->SetBitsOffset(static_cast(ReadNum())); - dbNode->SetBitsSize(static_cast(ReadNum())); - dbNode->SetOpnd(ImportExpression(func), kFirstOpnd); - dbNode->SetOpnd(ImportExpression(func), kSecondOpnd); + dbNode->SetBitsOffset(ReadNum()); + dbNode->SetBitsSize(ReadNum()); + dbNode->SetOpnd(ImportExpression(func), 0); + dbNode->SetOpnd(ImportExpression(func), 1); return dbNode; } case OP_gcmallocjarray: @@ -353,9 +353,9 @@ BaseNode *BinaryMplImport::ImportExpression(MIRFunction *func) { case OP_cmpl: case OP_cmp: { CompareNode *cmpNode = mod.CurFuncCodeMemPool()->New(op, typ); - cmpNode->SetOpndType(static_cast(Read())); - cmpNode->SetOpnd(ImportExpression(func), kFirstOpnd); - cmpNode->SetOpnd(ImportExpression(func), kSecondOpnd); + cmpNode->SetOpndType((PrimType)Read()); + cmpNode->SetOpnd(ImportExpression(func), 0); + cmpNode->SetOpnd(ImportExpression(func), 1); return cmpNode; } case OP_resolveinterfacefunc: @@ -527,7 +527,7 @@ BlockNode *BinaryMplImport::ImportBlockNode(MIRFunction *func) { case OP_iassignspoff: case OP_iassignfpoff: { IassignFPoffNode *s = func->GetCodeMemPool()->New(op); - s->SetPrimType(static_cast(Read())); + s->SetPrimType((PrimType)Read()); s->SetOffset(static_cast(ReadNum())); s->SetOpnd(ImportExpression(func), kFirstOpnd); stmt = s; diff --git a/src/mapleall/maple_ir/src/bin_mpl_import.cpp b/src/mapleall/maple_ir/src/bin_mpl_import.cpp index 2294e72594..114ce2dde0 100644 --- a/src/mapleall/maple_ir/src/bin_mpl_import.cpp +++ b/src/mapleall/maple_ir/src/bin_mpl_import.cpp @@ -544,7 +544,7 @@ TyIdx BinaryMplImport::ImportType(bool forPointedType) { CHECK_FATAL(static_cast(-tag) < typTab.size(), "index out of bounds"); return typTab.at(static_cast(-tag)); } - PrimType primType = static_cast(0); + PrimType primType = (PrimType)0; GStrIdx strIdx(0); bool nameIsLocal = false; ImportTypeBase(primType, strIdx, nameIsLocal); @@ -720,7 +720,7 @@ TyIdx BinaryMplImport::ImportTypeNonJava() { CHECK_FATAL(static_cast(-tag) < typTab.size(), "index out of bounds"); return typTab[static_cast(-tag)]; } - PrimType primType = static_cast(0); + PrimType primType = (PrimType)0; GStrIdx strIdx(0); bool nameIsLocal = false; ImportTypeBase(primType, strIdx, nameIsLocal); diff --git a/src/mapleall/maple_ir/src/mir_lower.cpp b/src/mapleall/maple_ir/src/mir_lower.cpp index ce085e6d1a..ddb4827535 100644 --- a/src/mapleall/maple_ir/src/mir_lower.cpp +++ b/src/mapleall/maple_ir/src/mir_lower.cpp @@ -554,7 +554,7 @@ BlockNode *MIRLower::LowerBlock(BlockNode &block) { CHECK_FATAL(funcType != nullptr, "MIRLower::LowerBlock: cannot find prototype for icall"); ic->SetRetTyIdx(funcType->GetTypeIndex()); MIRType *retType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(funcType->GetRetTyIdx()); - if (retType->GetPrimType() == PTY_agg && retType->GetSize() > k16BitSize) { + if (retType->GetPrimType() == PTY_agg && retType->GetSize() > 16) { funcType->funcAttrs.SetAttr(FUNCATTR_firstarg_return); } } @@ -1093,14 +1093,14 @@ MIRFuncType *MIRLower::FuncTypeFromFuncPtrExpr(BaseNode *x) { res = static_cast(mirType)->GetPointedFuncType(); } if (res == nullptr) { - res = FuncTypeFromFuncPtrExpr(x->Opnd(kNodeFirstOpnd)); + res = FuncTypeFromFuncPtrExpr(x->Opnd(0)); } break; } case OP_select: { - res = FuncTypeFromFuncPtrExpr(x->Opnd(kNodeSecondOpnd)); + res = FuncTypeFromFuncPtrExpr(x->Opnd(1)); if (res == nullptr) { - res = FuncTypeFromFuncPtrExpr(x->Opnd(kNodeThirdOpnd)); + res = FuncTypeFromFuncPtrExpr(x->Opnd(2)); } break; } diff --git a/src/mapleall/maple_me/src/irmap_build.cpp b/src/mapleall/maple_me/src/irmap_build.cpp index 6fd82f8500..bebf1facb0 100755 --- a/src/mapleall/maple_me/src/irmap_build.cpp +++ b/src/mapleall/maple_me/src/irmap_build.cpp @@ -808,8 +808,7 @@ MeStmt *IRMapBuild::BuildCallMeStmt(StmtNode &stmt, AccessSSANodes &ssaPart) { MeStmt *IRMapBuild::BuildNaryMeStmt(StmtNode &stmt, AccessSSANodes &ssaPart) { Opcode op = stmt.GetOpCode(); - NaryMeStmt *naryMeStmt = (op == OP_icall || op == OP_icallassigned || - op == OP_icallproto || op == OP_icallprotoassigned) + NaryMeStmt *naryMeStmt = (op == OP_icall || op == OP_icallassigned || op == OP_icallproto || op == OP_icallprotoassigned) ? static_cast(irMap->NewInPool(&stmt)) : static_cast(irMap->NewInPool(&stmt)); auto &naryStmtNode = static_cast(stmt); diff --git a/src/mapleall/maple_me/src/irmap_emit.cpp b/src/mapleall/maple_me/src/irmap_emit.cpp index 9cab595c5d..d6ca21e189 100755 --- a/src/mapleall/maple_me/src/irmap_emit.cpp +++ b/src/mapleall/maple_me/src/irmap_emit.cpp @@ -412,8 +412,7 @@ MIRFunction &CallMeStmt::GetTargetFunction() { } StmtNode &CallMeStmt::EmitStmt(SSATab &ssaTab) { - if (GetOp() != OP_icall && GetOp() != OP_icallassigned && - GetOp() != OP_icallproto && GetOp() != OP_icallprotoassigned) { + if (GetOp() != OP_icall && GetOp() != OP_icallassigned && GetOp() != OP_icallproto && GetOp() != OP_icallprotoassigned) { auto *callNode = ssaTab.GetModule().CurFunction()->GetCodeMempool()->New(ssaTab.GetModule(), Opcode(GetOp())); callNode->SetPUIdx(puIdx); diff --git a/src/mapleall/maple_me/src/me_phase_manager.cpp b/src/mapleall/maple_me/src/me_phase_manager.cpp index eef57b0aeb..a0b5419a8e 100644 --- a/src/mapleall/maple_me/src/me_phase_manager.cpp +++ b/src/mapleall/maple_me/src/me_phase_manager.cpp @@ -160,7 +160,7 @@ bool MeFuncPM::PhaseRun(maple::MIRModule &m) { func->SetFrameSize(localMemLayout.StackFrameSize()); memPoolCtrler.DeleteMemPool(layoutMp); } - globalMemLayout.seg_GPbased.size = maplebe::RoundUp(static_cast(globalMemLayout.seg_GPbased.size), GetPrimTypeSize(PTY_ptr)); + globalMemLayout.seg_GPbased.size = maplebe::RoundUp(globalMemLayout.seg_GPbased.size, GetPrimTypeSize(PTY_ptr)); m.SetGlobalMemSize(globalMemLayout.seg_GPbased.size); // output .lmbc BinaryMplt binMplt(m); -- Gitee From 229cbf1693be42a1797f4d9cf41b709ef7776f59 Mon Sep 17 00:00:00 2001 From: William Chen Date: Thu, 9 Jun 2022 15:13:55 -0700 Subject: [PATCH 116/179] Enhance ebo for extension to and 0xff 0xffff optimization --- .../maple_be/include/cg/aarch64/aarch64_ebo.h | 3 +- .../maple_be/src/cg/aarch64/aarch64_ebo.cpp | 62 +++++++++++++------ 2 files changed, 44 insertions(+), 21 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h index a4fc4288b1..c23d9ac13f 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_ebo.h @@ -83,7 +83,8 @@ class AArch64Ebo : public Ebo { bool SimplifyBothConst(BB &bb, Insn &insn, const ImmOperand &immOperand0, const ImmOperand &immOperand1, uint32 opndSize) const; AArch64CC_t GetReverseCond(const CondOperand &cond) const; - bool CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp) const; + bool CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp); + bool CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp, int64 immVal); }; } /* namespace maplebe */ diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp index 003c9eda0c..ff2bd520ad 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp @@ -1058,6 +1058,38 @@ bool AArch64Ebo::CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi return false; } +bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp, int64 immVal) { + if (opndInfo.insn == nullptr) { + return false; + } + if (!cgFunc->GetMirModule().IsCModule()) { + return false; + } + Insn *prevInsn = opndInfo.insn; + InsnInfo *insnInfo = opndInfo.insnInfo; + if (insnInfo == nullptr) { + return false; + } + CHECK_NULL_FATAL(insnInfo); + MOperator opc1 = prevInsn->GetMachineOpcode(); + if (!isFp && + (((immVal == 0xff) && + (opc1 >= MOP_xsxtb32) && (opc1 <= MOP_xuxtw64)) || + ((immVal == 0xffff) && + (opc1 == MOP_xsxth32 || opc1 == MOP_xsxth64 || opc1 == MOP_xsxtw64 || + opc1 == MOP_xsxth32 || opc1 == MOP_xsxtw64)))) { + /* don't use register if it was redefined. */ + OpndInfo *opndInfo1 = insnInfo->origOpnd[kInsnSecondOpnd]; + if ((opndInfo1 != nullptr) && opndInfo1->redefined) { + return false; + } + Operand &opnd1 = prevInsn->GetOperand(kInsnSecondOpnd); + insn.SetOperand(kInsnSecondOpnd, opnd1); + return true; + } + return false; +} + /* Do some special pattern */ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origInfos) { MOperator opCode = insn.GetMachineOpcode(); @@ -1104,10 +1136,12 @@ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origI * ===> ldrb x1, [] ===> ldrb x1, [] ===> ldrsb x1, [] ===> no change * mov x1, x1 mov x1, x1 mov x1, x1 */ - case MOP_wandrri12: { + case MOP_wandrri12: + case MOP_xandrri13: { + bool is64Bits = (opCode == MOP_xandrri13); bool doAndOpt = false; if (static_cast(insn.GetOperand(kInsnThirdOpnd)).GetValue() == 0xff) { - doAndOpt = CombineExtensionAndLoad(&insn, origInfos, AND, false); + doAndOpt = CombineExtensionAndLoad(&insn, origInfos, AND, is64Bits); } if (doAndOpt) { return doAndOpt; @@ -1122,29 +1156,17 @@ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origI (static_cast(immValue) & (static_cast(immValue) + 1)) == 0) { /* immValue is (1 << n - 1) */ OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); - return CombineLsrAnd(insn, *opndInfo, false, false); - } - break; - } - case MOP_xandrri13: { - bool doAndOpt = false; - if (static_cast(insn.GetOperand(kInsnThirdOpnd)).GetValue() == 0xff) { - doAndOpt = CombineExtensionAndLoad(&insn, origInfos, AND, true); - } - if (doAndOpt) { - return doAndOpt; + return CombineLsrAnd(insn, *opndInfo, is64Bits, false); } /* - * lsr d0, d1, #6 - * and d0, d0, #1 - * ===> ubfx d0, d1, #6, #1 + * extension dest, src0 + * and dest, dest, 0xff or 0xffff + * ===> if extension is >= imm then can eliminate extension */ - int64 immValue = static_cast(insn.GetOperand(kInsnThirdOpnd)).GetValue(); - if (!beforeRegAlloc && immValue != 0 && + if (beforeRegAlloc && immValue != 0 && (static_cast(immValue) & (static_cast(immValue) + 1)) == 0) { - /* immValue is (1 << n - 1) */ OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); - return CombineLsrAnd(insn, *opndInfo, true, false); + return CombineExtAnd(insn, *opndInfo, is64Bits, false, immValue); } break; } -- Gitee From fbf763b17f4e23ac2de8a0ce17c0bf5de8034654 Mon Sep 17 00:00:00 2001 From: William Chen Date: Thu, 9 Jun 2022 16:33:38 -0700 Subject: [PATCH 117/179] Enhance ebo for back to back and optimization --- .../maple_be/src/cg/aarch64/aarch64_ebo.cpp | 44 ++++++++++++------- 1 file changed, 29 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp index ff2bd520ad..6b8bd947eb 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp @@ -1058,11 +1058,17 @@ bool AArch64Ebo::CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi return false; } +/* + * extension dest, src0 + * and dest, dest, 0xff or 0xffff + * ===> if extension is >= imm then can eliminate extension + * + * and dst1, src0, imm1 + * and dst2, dst1, imm2 where imm2 is 0xff or 0xffff + * ===> and dst2, src0, imm1 if imm1 <= imm2 + */ bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp, int64 immVal) { - if (opndInfo.insn == nullptr) { - return false; - } - if (!cgFunc->GetMirModule().IsCModule()) { + if (isFp || opndInfo.insn == nullptr || !cgFunc->GetMirModule().IsCModule()) { return false; } Insn *prevInsn = opndInfo.insn; @@ -1072,12 +1078,11 @@ bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi } CHECK_NULL_FATAL(insnInfo); MOperator opc1 = prevInsn->GetMachineOpcode(); - if (!isFp && - (((immVal == 0xff) && - (opc1 >= MOP_xsxtb32) && (opc1 <= MOP_xuxtw64)) || - ((immVal == 0xffff) && - (opc1 == MOP_xsxth32 || opc1 == MOP_xsxth64 || opc1 == MOP_xsxtw64 || - opc1 == MOP_xsxth32 || opc1 == MOP_xsxtw64)))) { + if (((immVal == 0xff) && + (opc1 >= MOP_xsxtb32) && (opc1 <= MOP_xuxtw64)) || + ((immVal == 0xffff) && + (opc1 == MOP_xsxth32 || opc1 == MOP_xsxth64 || opc1 == MOP_xsxtw64 || + opc1 == MOP_xsxth32 || opc1 == MOP_xsxtw64))) { /* don't use register if it was redefined. */ OpndInfo *opndInfo1 = insnInfo->origOpnd[kInsnSecondOpnd]; if ((opndInfo1 != nullptr) && opndInfo1->redefined) { @@ -1087,6 +1092,20 @@ bool AArch64Ebo::CombineExtAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bi insn.SetOperand(kInsnSecondOpnd, opnd1); return true; } + if ((immVal == 0xff || immVal == 0xffff) && (opc1 == MOP_wandrri12 || opc1 == MOP_xandrri13)) { + OpndInfo *opndInfo1 = insnInfo->origOpnd[kInsnSecondOpnd]; + if ((opndInfo1 != nullptr) && opndInfo1->redefined) { + return false; + } + int64 prevImmVal = static_cast(prevInsn->GetOperand(kInsnThirdOpnd)).GetValue(); + if (prevImmVal > immVal) { + return false; + } + Operand &opnd1 = prevInsn->GetOperand(kInsnSecondOpnd); + insn.SetOperand(kInsnSecondOpnd, opnd1); + Operand &opnd2 = prevInsn->GetOperand(kInsnThirdOpnd); + insn.SetOperand(kInsnThirdOpnd, opnd2); + } return false; } @@ -1158,11 +1177,6 @@ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origI OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); return CombineLsrAnd(insn, *opndInfo, is64Bits, false); } - /* - * extension dest, src0 - * and dest, dest, 0xff or 0xffff - * ===> if extension is >= imm then can eliminate extension - */ if (beforeRegAlloc && immValue != 0 && (static_cast(immValue) & (static_cast(immValue) + 1)) == 0) { OpndInfo *opndInfo = origInfos.at(kInsnSecondOpnd); -- Gitee From 1d49cafc5e347dbccf185d5dae5832df9245ac14 Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:15:50 -0700 Subject: [PATCH 118/179] Turn off rematerialization for lmbc --- .../src/cg/aarch64/aarch64_color_ra.cpp | 20 +++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp index 2b04790cd5..6cbf05629d 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_color_ra.cpp @@ -455,14 +455,18 @@ void GraphColorRegAllocator::CalculatePriority(LiveRange &lr) const { auto *a64CGFunc = static_cast(cgFunc); CG *cg = a64CGFunc->GetCG(); - if (cg->GetRematLevel() >= rematConst && lr.IsRematerializable(*a64CGFunc, rematConst)) { - lr.SetRematLevel(rematConst); - } else if (cg->GetRematLevel() >= rematAddr && lr.IsRematerializable(*a64CGFunc, rematAddr)) { - lr.SetRematLevel(rematAddr); - } else if (cg->GetRematLevel() >= rematDreadLocal && lr.IsRematerializable(*a64CGFunc, rematDreadLocal)) { - lr.SetRematLevel(rematDreadLocal); - } else if (cg->GetRematLevel() >= rematDreadGlobal && lr.IsRematerializable(*a64CGFunc, rematDreadGlobal)) { - lr.SetRematLevel(rematDreadGlobal); + if (cgFunc->GetCG()->IsLmbc()) { + lr.SetRematLevel(rematOff); + } else { + if (cg->GetRematLevel() >= rematConst && lr.IsRematerializable(*a64CGFunc, rematConst)) { + lr.SetRematLevel(rematConst); + } else if (cg->GetRematLevel() >= rematAddr && lr.IsRematerializable(*a64CGFunc, rematAddr)) { + lr.SetRematLevel(rematAddr); + } else if (cg->GetRematLevel() >= rematDreadLocal && lr.IsRematerializable(*a64CGFunc, rematDreadLocal)) { + lr.SetRematLevel(rematDreadLocal); + } else if (cg->GetRematLevel() >= rematDreadGlobal && lr.IsRematerializable(*a64CGFunc, rematDreadGlobal)) { + lr.SetRematLevel(rematDreadGlobal); + } } auto calculatePriorityFunc = [&lr, &bbNum, &numDefs, &numUses, &pri, this] (uint32 bbID) { -- Gitee From 0b99882d7fed49f99583912478667f68797fe73e Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:16:12 -0700 Subject: [PATCH 119/179] Turn on globalopt for lmbc, but leave SSA opt off --- .../include/cg/aarch64/aarch64_phases.def | 12 ++++-------- src/mapleall/maple_be/include/cg/reaching.h | 1 + .../maple_be/src/cg/aarch64/aarch64_global.cpp | 4 +++- .../src/cg/aarch64/aarch64_reaching.cpp | 18 ++++++++++++++++++ src/mapleall/maple_be/src/cg/reaching.cpp | 1 + 5 files changed, 27 insertions(+), 9 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index ff08e81852..5595b17c0c 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -36,10 +36,8 @@ ADDTARGETPHASE("ico", CGOptions::DoICO()) ADDTARGETPHASE("cfgo", !GetMIRModule()->IsCModule() && CGOptions::DoCFGO()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); - ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); - } + ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); + ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); ADDTARGETPHASE("clearrdinfo", (CGOptions::DoStoreLoadOpt()) || CGOptions::DoGlobalOpt()); ADDTARGETPHASE("prepeephole1", CGOptions::DoPrePeephole()); @@ -49,10 +47,8 @@ ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); - } + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/include/cg/reaching.h b/src/mapleall/maple_be/include/cg/reaching.h index 55b4b666fe..13872a9122 100644 --- a/src/mapleall/maple_be/include/cg/reaching.h +++ b/src/mapleall/maple_be/include/cg/reaching.h @@ -146,6 +146,7 @@ class ReachingDefinition : public AnalysisResult { std::vector memIn; std::vector memOut; const uint32 kMaxBBNum; + uint32 stackSize = 0; private: void Initialize(); void InitDataSize(); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 4a2f257321..6b5d902cb4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,7 +412,9 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - CHECK_FATAL(false, "check case in ssa"); + if (cgFunc.GetCG()->IsLmbc() == false) { + CHECK_FATAL(false, "check case in ssa"); + } } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp index d3cdffa298..5a64952e61 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp @@ -464,6 +464,9 @@ std::vector AArch64ReachingDefinition::FindMemDefBetweenInsn( ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffset < 0) { + memOffset = stackSize - memOffset; + } if ((offset == memOffset) || (insn->IsStorePair() && offset == memOffset + GetEachMemSizeOfPair(insn->GetMachineOpcode()))) { defInsnVec.emplace_back(insn); @@ -516,6 +519,9 @@ void AArch64ReachingDefinition::FindMemDefInBB(uint32 offset, BB &bb, InsnSet &d ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffset < 0) { + memOffset = stackSize - memOffset; + } if (offset == memOffset) { (void)defInsnSet.insert(insn); break; @@ -1001,6 +1007,9 @@ bool AArch64ReachingDefinition::FindMemUseBetweenInsn(uint32 offset, Insn *start ASSERT(memOpnd.GetIndexRegister() == nullptr, "offset must not be Register for frame MemOperand"); ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetValue(); + if (memOffset < 0) { + memOffset = stackSize - memOffset; + } if (insn->IsStore() || insn->IsPseudoInstruction()) { if (memOffset == offset) { @@ -1050,6 +1059,9 @@ InsnSet AArch64ReachingDefinition::FindDefForMemOpnd(Insn &insn, uint32 indexOrO } ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffSet < 0) { + memOffSet = stackSize - memOffSet; + } } else { memOffSet = indexOrOffset; } @@ -1101,6 +1113,9 @@ InsnSet AArch64ReachingDefinition::FindUseForMemOpnd(Insn &insn, uint8 index, bo ASSERT(memOpnd.GetIndexRegister() == nullptr, "IndexRegister no nullptr"); ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (memOffSet < 0) { + memOffSet = stackSize - memOffSet; + } if (secondMem) { ASSERT(insn.IsStorePair(), "second MemOperand can only be defined in stp insn"); memOffSet += GetEachMemSizeOfPair(insn.GetMachineOpcode()); @@ -1214,6 +1229,9 @@ void AArch64ReachingDefinition::InitInfoForMemOperand(Insn &insn, Operand &opnd, CHECK_FATAL(index == nullptr, "Existing [x29 + index] Memory Address"); ASSERT(memOpnd.GetOffsetImmediate(), "offset must be a immediate value"); int64 offsetVal = memOpnd.GetOffsetImmediate()->GetOffsetValue(); + if (offsetVal < 0) { + offsetVal = stackSize - offsetVal; + } if ((offsetVal % kMemZoomSize) != 0) { SetAnalysisMode(kRDRegAnalysis); } diff --git a/src/mapleall/maple_be/src/cg/reaching.cpp b/src/mapleall/maple_be/src/cg/reaching.cpp index 77fa156845..960d820e34 100644 --- a/src/mapleall/maple_be/src/cg/reaching.cpp +++ b/src/mapleall/maple_be/src/cg/reaching.cpp @@ -778,6 +778,7 @@ void ReachingDefinition::AnalysisStart() { if (!cgFunc->GetFirstBB()) { return; } + stackSize = GetStackSize(); Initialize(); /* Build in/out for function body first. (Except cleanup bb) */ BuildInOutForFuncBody(); -- Gitee From f35cb209685eb8fdb11578a33bef422843eddfc9 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Fri, 10 Jun 2022 17:56:05 -0700 Subject: [PATCH 120/179] delete obsolete code in SelectAggIassign() where small struct returned in regs was represented in an iassign --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 130 ------------------ 1 file changed, 130 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 6ec89b8234..6fdf8ddff6 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -2286,15 +2286,6 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) { uint32 lhsOffset = 0; MIRType *stmtType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(stmt.GetTyIdx()); MIRPtrType *lhsPointerType = static_cast(stmtType); - bool loadToRegs4StructReturn = false; - if (mirModule.CurFunction()->StructReturnedInRegs()) { - MIRSymbol *retSt = mirModule.CurFunction()->GetFormal(0); - if (stmt.Opnd(0)->GetOpCode() == OP_dread) { - DreadNode *dread = static_cast(stmt.Opnd(0)); - MIRSymbol *addrSym = mirModule.CurFunction()->GetLocalOrGlobalSymbol(dread->GetStIdx()); - loadToRegs4StructReturn = (retSt == addrSym); - } - } MIRType *lhsType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(lhsPointerType->GetPointedTyIdx()); if (stmt.GetFieldID() != 0) { MIRStructType *structType = static_cast(lhsType); @@ -2338,91 +2329,6 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) { rhsType = structType->GetFieldType(rhsDread->GetFieldID()); rhsOffset = static_cast(GetBecommon().GetFieldOffset(*structType, rhsDread->GetFieldID()).first); } - if (loadToRegs4StructReturn) { - /* generate move to regs for agg return */ - CHECK_FATAL(lhsSize <= k16ByteSize, "SelectAggIassign: illegal struct size"); - AArch64CallConvImpl parmlocator(GetBecommon()); - CCLocInfo pLoc; - parmlocator.LocateNextParm(*lhsType, pLoc, true, GetBecommon().GetMIRModule().CurFunction()); - /* aggregates are 8 byte aligned. */ - Operand *rhsmemopnd = nullptr; - RegOperand *result[kFourRegister]; /* up to 2 int or 4 fp */ - uint32 loadSize; - uint32 numRegs; - RegType regType; - PrimType retPty; - bool fpParm = false; - if (pLoc.numFpPureRegs > 0) { - loadSize = pLoc.fpSize; - numRegs = pLoc.numFpPureRegs; - fpParm = true; - regType = kRegTyFloat; - retPty = (pLoc.fpSize == k4ByteSize) ? PTY_f32 : PTY_f64; - } else { - if (CGOptions::IsBigEndian()) { - loadSize = k8ByteSize; - numRegs = (lhsSize <= k8ByteSize) ? kOneRegister : kTwoRegister; - regType = kRegTyInt; - retPty = PTY_u64; - } else { - loadSize = (lhsSize <= k4ByteSize) ? k4ByteSize : k8ByteSize; - numRegs = (lhsSize <= k8ByteSize) ? kOneRegister : kTwoRegister; - regType = kRegTyInt; - retPty = PTY_u32; - } - } - bool parmCopy = IsParamStructCopy(*rhsSymbol); - for (uint32 i = 0; i < numRegs; i++) { - if (parmCopy) { - rhsmemopnd = &LoadStructCopyBase(*rhsSymbol, - (rhsOffset + static_cast(i * (fpParm ? loadSize : k8ByteSize))), - static_cast(loadSize * kBitsPerByte)); - } else { - rhsmemopnd = &GetOrCreateMemOpnd(*rhsSymbol, - (rhsOffset + static_cast(i * (fpParm ? loadSize : k8ByteSize))), - (loadSize * kBitsPerByte)); - } - result[i] = &CreateVirtualRegisterOperand(NewVReg(regType, loadSize)); - MOperator mop1 = PickLdInsn(loadSize * kBitsPerByte, retPty); - Insn &ld = GetCG()->BuildInstruction(mop1, *(result[i]), *rhsmemopnd); - GetCurBB()->AppendInsn(ld); - } - AArch64reg regs[kFourRegister]; - regs[kFirstReg] = static_cast(pLoc.reg0); - regs[kSecondReg] = static_cast(pLoc.reg1); - regs[kThirdReg] = static_cast(pLoc.reg2); - regs[kFourthReg] = static_cast(pLoc.reg3); - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg; - MOperator mop2; - if (fpParm) { - preg = regs[i]; - mop2 = (loadSize == k4ByteSize) ? MOP_xvmovs : MOP_xvmovd; - } else { - preg = (i == 0 ? R0 : R1); - mop2 = (loadSize == k4ByteSize) ? MOP_wmovrr : MOP_xmovrr; - } - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, (loadSize * kBitsPerByte), regType); - Insn &mov = GetCG()->BuildInstruction(mop2, dest, *(result[i])); - GetCurBB()->AppendInsn(mov); - } - /* Create artificial dependency to extend the live range */ - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg; - MOperator mop3; - if (fpParm) { - preg = regs[i]; - mop3 = MOP_pseudo_ret_float; - } else { - preg = (i == 0 ? R0 : R1); - mop3 = MOP_pseudo_ret_int; - } - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, loadSize * kBitsPerByte, regType); - Insn &pseudo = GetCG()->BuildInstruction(mop3, dest); - GetCurBB()->AppendInsn(pseudo); - } - return; - } rhsAlign = GetBecommon().GetTypeAlign(rhsType->GetTypeIndex()); alignUsed = std::min(lhsAlign, rhsAlign); ASSERT(alignUsed != 0, "expect non-zero"); @@ -2538,42 +2444,6 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) { rhsOffset = static_cast(GetBecommon().GetFieldOffset(*rhsStructType, rhsIread->GetFieldID()).first); isRefField = GetBecommon().IsRefField(*rhsStructType, rhsIread->GetFieldID()); } - if (loadToRegs4StructReturn) { - /* generate move to regs. */ - CHECK_FATAL(lhsSize <= k16ByteSize, "SelectAggIassign: illegal struct size"); - RegOperand *result[kTwoRegister]; /* maximum 16 bytes, 2 registers */ - uint32 loadSize; - if (CGOptions::IsBigEndian()) { - loadSize = k8ByteSize; - } else { - loadSize = (lhsSize <= k4ByteSize) ? k4ByteSize : k8ByteSize; - } - uint32 numRegs = (lhsSize <= k8ByteSize) ? kOneRegister : kTwoRegister; - for (uint32 i = 0; i < numRegs; i++) { - OfstOperand *rhsOffOpnd = &GetOrCreateOfstOpnd(rhsOffset + i * loadSize, loadSize * kBitsPerByte); - Operand &rhsmemopnd = GetOrCreateMemOpnd(MemOperand::kAddrModeBOi, loadSize * kBitsPerByte, - rhsAddrOpnd, nullptr, rhsOffOpnd, nullptr); - result[i] = &CreateVirtualRegisterOperand(NewVReg(kRegTyInt, loadSize)); - MOperator mop1 = PickLdInsn(loadSize * kBitsPerByte, PTY_u32); - Insn &ld = GetCG()->BuildInstruction(mop1, *(result[i]), rhsmemopnd); - ld.MarkAsAccessRefField(isRefField); - GetCurBB()->AppendInsn(ld); - } - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg = (i == 0 ? R0 : R1); - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, loadSize * kBitsPerByte, kRegTyInt); - Insn &mov = GetCG()->BuildInstruction(MOP_xmovrr, dest, *(result[i])); - GetCurBB()->AppendInsn(mov); - } - /* Create artificial dependency to extend the live range */ - for (uint32 i = 0; i < numRegs; i++) { - AArch64reg preg = (i == 0 ? R0 : R1); - RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, loadSize * kBitsPerByte, kRegTyInt); - Insn &pseudo = cg->BuildInstruction(MOP_pseudo_ret_int, dest); - GetCurBB()->AppendInsn(pseudo); - } - return; - } rhsAlign = GetBecommon().GetTypeAlign(rhsType->GetTypeIndex()); alignUsed = std::min(lhsAlign, rhsAlign); ASSERT(alignUsed != 0, "expect non-zero"); -- Gitee From 318845781292a4d36b56e663a95f5b8f39d14254 Mon Sep 17 00:00:00 2001 From: William Chen Date: Mon, 13 Jun 2022 14:06:17 -0700 Subject: [PATCH 121/179] Do not optimize for ssa for physical regs. --- .../include/cg/aarch64/aarch64_phases.def | 22 +++++++++---------- .../src/cg/aarch64/aarch64_global.cpp | 4 +--- .../maple_be/src/cg/aarch64/aarch64_prop.cpp | 3 +++ 3 files changed, 14 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 5595b17c0c..531e7f0535 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,18 +17,16 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); - } + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 6b5d902cb4..4a2f257321 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,9 +412,7 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - if (cgFunc.GetCG()->IsLmbc() == false) { - CHECK_FATAL(false, "check case in ssa"); - } + CHECK_FATAL(false, "check case in ssa"); } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp index 4ad05acfac..4fba8ed8fc 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_prop.cpp @@ -1491,6 +1491,9 @@ bool ExtendMovPattern::CheckSrcReg(regno_t srcRegNo, uint32 validNum) { bool ExtendMovPattern::BitNotAffected(const Insn &insn, uint32 validNum) { RegOperand &firstOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); + if (firstOpnd.IsPhysicalRegister()) { + return false; + } RegOperand &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); regno_t desRegNo = firstOpnd.GetRegisterNumber(); regno_t srcRegNo = secondOpnd.GetRegisterNumber(); -- Gitee From 04e04008f59c5c1b82f7b4cb91b8d6d071890161 Mon Sep 17 00:00:00 2001 From: William Chen Date: Tue, 14 Jun 2022 09:21:24 -0700 Subject: [PATCH 122/179] Fix globalopt bug of negative offset with lmbc --- .../maple_be/src/cg/aarch64/aarch64_reaching.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp index 5a64952e61..66cf39e832 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_reaching.cpp @@ -465,7 +465,7 @@ std::vector AArch64ReachingDefinition::FindMemDefBetweenInsn( ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffset < 0) { - memOffset = stackSize - memOffset; + memOffset = stackSize + memOffset; } if ((offset == memOffset) || (insn->IsStorePair() && offset == memOffset + GetEachMemSizeOfPair(insn->GetMachineOpcode()))) { @@ -520,7 +520,7 @@ void AArch64ReachingDefinition::FindMemDefInBB(uint32 offset, BB &bb, InsnSet &d ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffset < 0) { - memOffset = stackSize - memOffset; + memOffset = stackSize + memOffset; } if (offset == memOffset) { (void)defInsnSet.insert(insn); @@ -1008,7 +1008,7 @@ bool AArch64ReachingDefinition::FindMemUseBetweenInsn(uint32 offset, Insn *start ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffset = memOpnd.GetOffsetImmediate()->GetValue(); if (memOffset < 0) { - memOffset = stackSize - memOffset; + memOffset = stackSize + memOffset; } if (insn->IsStore() || insn->IsPseudoInstruction()) { @@ -1060,7 +1060,7 @@ InsnSet AArch64ReachingDefinition::FindDefForMemOpnd(Insn &insn, uint32 indexOrO ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffSet < 0) { - memOffSet = stackSize - memOffSet; + memOffSet = stackSize + memOffSet; } } else { memOffSet = indexOrOffset; @@ -1114,7 +1114,7 @@ InsnSet AArch64ReachingDefinition::FindUseForMemOpnd(Insn &insn, uint8 index, bo ASSERT(memOpnd.GetOffsetImmediate() != nullptr, "offset must be a immediate value"); int64 memOffSet = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (memOffSet < 0) { - memOffSet = stackSize - memOffSet; + memOffSet = stackSize + memOffSet; } if (secondMem) { ASSERT(insn.IsStorePair(), "second MemOperand can only be defined in stp insn"); @@ -1230,7 +1230,7 @@ void AArch64ReachingDefinition::InitInfoForMemOperand(Insn &insn, Operand &opnd, ASSERT(memOpnd.GetOffsetImmediate(), "offset must be a immediate value"); int64 offsetVal = memOpnd.GetOffsetImmediate()->GetOffsetValue(); if (offsetVal < 0) { - offsetVal = stackSize - offsetVal; + offsetVal = stackSize + offsetVal; } if ((offsetVal % kMemZoomSize) != 0) { SetAnalysisMode(kRDRegAnalysis); -- Gitee From be533bcdb021c12006b92a53b2460b7d04d63460 Mon Sep 17 00:00:00 2001 From: William Chen Date: Tue, 14 Jun 2022 15:55:34 -0700 Subject: [PATCH 123/179] Merge return bb for small C functions --- src/mapleall/maple_be/include/cg/cgfunc.h | 1 + src/mapleall/maple_be/src/cg/cgbb.cpp | 1 + src/mapleall/maple_be/src/cg/cgfunc.cpp | 3 ++- 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/include/cg/cgfunc.h b/src/mapleall/maple_be/include/cg/cgfunc.h index 4a8ee93eb8..d10b1f8465 100644 --- a/src/mapleall/maple_be/include/cg/cgfunc.h +++ b/src/mapleall/maple_be/include/cg/cgfunc.h @@ -81,6 +81,7 @@ class SpillMemOperandSet { class LiveRange; #endif /* TARGARM32 */ constexpr uint32 kVRegisterNumber = 80; +constexpr uint32 kNumBBOptReturn = 30; class CGFunc { public: enum ShiftDirection : uint8 { diff --git a/src/mapleall/maple_be/src/cg/cgbb.cpp b/src/mapleall/maple_be/src/cg/cgbb.cpp index 502983b519..d8b5e86278 100644 --- a/src/mapleall/maple_be/src/cg/cgbb.cpp +++ b/src/mapleall/maple_be/src/cg/cgbb.cpp @@ -525,6 +525,7 @@ void Bfs::ComputeBlockOrder() { done = true; } else { LogInfo::MapleLogger() << "Error: RA BFS loop " << sortedCnt << " in func " << cgfunc->GetName() << "\n"; + CHECK_FATAL(false, ""); } } sortedCnt = sortedBBs.size(); diff --git a/src/mapleall/maple_be/src/cg/cgfunc.cpp b/src/mapleall/maple_be/src/cg/cgfunc.cpp index b227112c30..b7aa8217b4 100644 --- a/src/mapleall/maple_be/src/cg/cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/cgfunc.cpp @@ -2032,7 +2032,8 @@ void CGFunc::HandleFunction() { /* select instruction */ GenerateInstruction(); /* merge multi return */ - if (!func.GetModule()->IsCModule() || CGOptions::DoRetMerge() || CGOptions::OptimizeForSize()) { + if (!func.GetModule()->IsCModule() || (func.GetModule()->IsCModule() && (NumBBs() < kNumBBOptReturn)) || + CGOptions::DoRetMerge() || CGOptions::OptimizeForSize()) { MergeReturn(); } if (func.IsJava()) { -- Gitee From 4ddff70a3d8a3968389e10f5bd0b05f62cfb9116 Mon Sep 17 00:00:00 2001 From: William Chen Date: Thu, 16 Jun 2022 10:53:55 -0700 Subject: [PATCH 124/179] Reorder back-to-back cond branch and uncond brach to loop head bb --- src/mapleall/maple_be/include/cg/cfgo.h | 24 +++++++++ src/mapleall/maple_be/include/cg/loop.h | 3 +- src/mapleall/maple_be/src/cg/cfgo.cpp | 65 ++++++++++++++++++++++++- src/mapleall/maple_be/src/cg/loop.cpp | 4 ++ 4 files changed, 93 insertions(+), 3 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/cfgo.h b/src/mapleall/maple_be/include/cg/cfgo.h index e7d6e07e14..2528f03413 100644 --- a/src/mapleall/maple_be/include/cg/cfgo.h +++ b/src/mapleall/maple_be/include/cg/cfgo.h @@ -18,6 +18,14 @@ #include "optimize_common.h" namespace maplebe { + +enum CfgoPhase : maple::uint8 { + CfgoDefault, + CfgoPreRegAlloc, + CfgoPostRegAlloc, + PostCfgo, +}; + class ChainingPattern : public OptimizationPattern { public: explicit ChainingPattern(CGFunc &func) : OptimizationPattern(func) { @@ -63,6 +71,14 @@ class FlipBRPattern : public OptimizationPattern { ~FlipBRPattern() override = default; bool Optimize(BB &curBB) override; + CfgoPhase GetPhase() const { + return phase; + } + void SetPhase(CfgoPhase val) { + phase = val; + } + CfgoPhase phase = CfgoDefault; + protected: void RelocateThrowBB(BB &curBB); }; @@ -120,6 +136,14 @@ class CFGOptimizer : public Optimizer { ~CFGOptimizer() override = default; void InitOptimizePatterns() override; + + CfgoPhase GetPhase() const { + return phase; + } + void SetPhase(CfgoPhase val) { + phase = val; + } + CfgoPhase phase = CfgoDefault; }; MAPLE_FUNC_PHASE_DECLARE_BEGIN(CgCfgo, maplebe::CGFunc) diff --git a/src/mapleall/maple_be/include/cg/loop.h b/src/mapleall/maple_be/include/cg/loop.h index 658ee83f04..eedf5bc02c 100644 --- a/src/mapleall/maple_be/include/cg/loop.h +++ b/src/mapleall/maple_be/include/cg/loop.h @@ -171,7 +171,8 @@ class CGFuncLoops { void CheckOverlappingInnerLoops(const MapleVector &iLoops, const MapleVector &loopMem) const; void CheckLoops() const; - void PrintLoops(const CGFuncLoops &funcLoop) const; + void PrintLoops(const CGFuncLoops &loops) const; + bool IsBBLoopMember(const BB *bb) const; const BB *GetHeader() const { return header; diff --git a/src/mapleall/maple_be/src/cg/cfgo.cpp b/src/mapleall/maple_be/src/cg/cfgo.cpp index 4fce8865a7..651204ccb8 100644 --- a/src/mapleall/maple_be/src/cg/cfgo.cpp +++ b/src/mapleall/maple_be/src/cg/cfgo.cpp @@ -42,7 +42,11 @@ void CFGOptimizer::InitOptimizePatterns() { diffPassPatterns.emplace_back(memPool->New(*cgFunc)); } diffPassPatterns.emplace_back(memPool->New(*cgFunc)); - diffPassPatterns.emplace_back(memPool->New(*cgFunc)); + FlipBRPattern *brOpt = memPool->New(*cgFunc); + if (GetPhase() == CfgoPostRegAlloc) { + brOpt->SetPhase(CfgoPostRegAlloc); + } + diffPassPatterns.emplace_back(brOpt); diffPassPatterns.emplace_back(memPool->New(*cgFunc)); diffPassPatterns.emplace_back(memPool->New(*cgFunc)); diffPassPatterns.emplace_back(memPool->New(*cgFunc)); @@ -548,7 +552,13 @@ void FlipBRPattern::RelocateThrowBB(BB &curBB) { * ftBB * targetBB * - * 2. relocate throw BB in RelocateThrowBB() + * loopHeaderBB: loopHeaderBB: + * ... ... + * cond_br loopExit: cond_br loopHeaderBB + * ftBB: ftBB: + * goto loopHeaderBB: goto loopExit + * + * 3. relocate throw BB in RelocateThrowBB() */ bool FlipBRPattern::Optimize(BB &curBB) { if (curBB.GetKind() == BB::kBBIf && !curBB.IsEmpty()) { @@ -648,6 +658,50 @@ bool FlipBRPattern::Optimize(BB &curBB) { ftBB->RemoveInsn(*brInsn); ftBB->SetKind(BB::kBBFallthru); } + } else if (GetPhase() == CfgoPostRegAlloc && ftBB->GetKind() == BB::kBBGoto && + curBB.GetLoop() != nullptr && curBB.GetLoop() == ftBB->GetLoop() && + ftBB->IsSoloGoto() && + ftBB->GetLoop()->GetHeader() == *(ftBB->GetSuccsBegin()) && + curBB.GetLoop()->IsBBLoopMember((curBB.GetSuccs().front() == ftBB) ? + curBB.GetSuccs().back() : curBB.GetSuccs().front()) == false) { + Insn *curBBBranchInsn = nullptr; + for (curBBBranchInsn = curBB.GetLastInsn(); curBBBranchInsn != nullptr; + curBBBranchInsn = curBBBranchInsn->GetPrev()) { + if (curBBBranchInsn->IsBranch()) { + break; + } + } + ASSERT(curBBBranchInsn != nullptr, "FlipBRPattern: curBB has no branch"); + Insn *brInsn = nullptr; + for (brInsn = ftBB->GetLastInsn(); brInsn != nullptr; brInsn = brInsn->GetPrev()) { + if (brInsn->IsGoto()) { + break; + } + } + ASSERT(brInsn != nullptr, "FlipBRPattern: ftBB has no branch"); + uint32 condTargetIdx = curBBBranchInsn->GetJumpTargetIdx(); + LabelOperand &condTarget = static_cast(curBBBranchInsn->GetOperand(condTargetIdx)); + MOperator mOp = curBBBranchInsn->FlipConditionOp(curBBBranchInsn->GetMachineOpcode(), condTargetIdx); + if (mOp == 0) { + return false; + } + uint32 gotoTargetIdx = brInsn->GetJumpTargetIdx(); + LabelOperand &gotoTarget = static_cast(brInsn->GetOperand(gotoTargetIdx)); + curBBBranchInsn->SetMOP(mOp); + curBBBranchInsn->SetOperand(condTargetIdx, gotoTarget); + brInsn->SetOperand(gotoTargetIdx, condTarget); + auto it = ftBB->GetSuccsBegin(); + BB *loopHeadBB = *it; + + curBB.RemoveSuccs(*brBB); + brBB->RemovePreds(curBB); + ftBB->RemoveSuccs(*loopHeadBB); + loopHeadBB->RemovePreds(*ftBB); + + curBB.PushBackSuccs(*loopHeadBB); + loopHeadBB->PushBackPreds(curBB); + ftBB->PushBackSuccs(*brBB); + brBB->PushBackPreds(*ftBB); } else { RelocateThrowBB(curBB); } @@ -848,6 +902,10 @@ bool DuplicateBBPattern::Optimize(BB &curBB) { /* === new pm === */ bool CgCfgo::PhaseRun(maplebe::CGFunc &f) { CFGOptimizer *cfgOptimizer = GetPhaseAllocator()->New(f, *GetPhaseMemPool()); + if (f.IsAfterRegAlloc()) { + (void)GetAnalysisInfoHook()->ForceRunAnalysisPhase, CGFunc>(&CgLoopAnalysis::id, f); + cfgOptimizer->SetPhase(CfgoPostRegAlloc); + } const std::string &funcClass = f.GetFunction().GetBaseClassName(); const std::string &funcName = f.GetFunction().GetBaseFuncName(); const std::string &name = funcClass + funcName; @@ -855,6 +913,9 @@ bool CgCfgo::PhaseRun(maplebe::CGFunc &f) { DotGenerator::GenerateDot("before-cfgo", f, f.GetMirModule()); } cfgOptimizer->Run(name); + if (f.IsAfterRegAlloc()) { + GetAnalysisInfoHook()->ForceEraseAnalysisPhase(f.GetUniqueID(), &CgLoopAnalysis::id); + } if (CFGO_DUMP_NEWPM) { DotGenerator::GenerateDot("after-cfgo", f, f.GetMirModule()); } diff --git a/src/mapleall/maple_be/src/cg/loop.cpp b/src/mapleall/maple_be/src/cg/loop.cpp index 71fb9e8edb..d37a7e0dfd 100644 --- a/src/mapleall/maple_be/src/cg/loop.cpp +++ b/src/mapleall/maple_be/src/cg/loop.cpp @@ -161,6 +161,10 @@ void CGFuncLoops::PrintLoops(const CGFuncLoops &funcLoop) const { } } +bool CGFuncLoops::IsBBLoopMember(const BB *bb) const { + return (*(std::find(loopMembers.begin(), loopMembers.end(), bb)) == bb); +} + // partial loop body found with formLoop is NOT really needed in down stream // It should be simplied later void LoopFinder::formLoop(BB* headBB, BB* backBB) { -- Gitee From 2972cdf03c5600e7204d57cd943d51bd97f0659f Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Mon, 20 Jun 2022 15:49:32 -0700 Subject: [PATCH 125/179] Updating to "new" lmbc --- .../include/cg/aarch64/aarch64_cgfunc.h | 14 +- src/mapleall/maple_be/include/cg/cgfunc.h | 4 +- .../src/cg/aarch64/aarch64_cgfunc.cpp | 127 ++++++++++++++++-- .../src/cg/aarch64/aarch64_memlayout.cpp | 24 +++- .../src/cg/aarch64/aarch64_proepilog.cpp | 31 ++++- 5 files changed, 174 insertions(+), 26 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index 12c4194d5c..a2e3c6a0cb 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -104,6 +104,7 @@ class AArch64CGFunc : public CGFunc { MIRType *LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList) const; RegOperand &GetOrCreateResOperand(const BaseNode &parent, PrimType primType); + MIRStructType *GetLmbcStructArgType(BaseNode &stmt, int32 argNo); void IntrinsifyGetAndAddInt(ListOperand &srcOpnds, PrimType pty); void IntrinsifyGetAndSetInt(ListOperand &srcOpnds, PrimType pty); @@ -191,7 +192,8 @@ class AArch64CGFunc : public CGFunc { Operand *SelectIread(const BaseNode &parent, IreadNode &expr, int extraOffset = 0, PrimType finalBitFieldDestType = kPtyInvalid) override; Operand *SelectIreadoff(const BaseNode &parent, IreadoffNode &ireadoff) override; - Operand *SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff) override; + Operand *SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff /*, MIRType &ty, + ListOperand &srcOpnds, AArch64CallConvImpl &parmLocator */) override; Operand *SelectIntConst(MIRIntConst &intConst) override; Operand *HandleFmovImm(PrimType stype, int64 val, MIRConst &mirConst, const BaseNode &parent); Operand *SelectFloatConst(MIRFloatConst &floatConst, const BaseNode &parent) override; @@ -869,7 +871,7 @@ class AArch64CGFunc : public CGFunc { void SelectParmListDreadSmallAggregate(const MIRSymbol &sym, MIRType &structType, ListOperand &srcOpnds, int32 offset, AArch64CallConvImpl &parmLocator, FieldID fieldID); - void SelectParmListIreadSmallAggregate(const IreadNode &iread, MIRType &structType, ListOperand &srcOpnds, + void SelectParmListIreadSmallAggregate(BaseNode &iread, MIRType &structType, ListOperand &srcOpnds, int32 offset, AArch64CallConvImpl &parmLocator); void SelectParmListDreadLargeAggregate(const MIRSymbol &sym, MIRType &structType, ListOperand &srcOpnds, @@ -878,12 +880,12 @@ class AArch64CGFunc : public CGFunc { AArch64CallConvImpl &parmLocator, int32 &structCopyOffset, int32 fromOffset); void CreateCallStructMemcpyToParamReg(MIRType &structType, int32 structCopyOffset, AArch64CallConvImpl &parmLocator, ListOperand &srcOpnds); - void SelectParmListForAggregate(BaseNode &argExpr, ListOperand &srcOpnds, AArch64CallConvImpl &parmLocator, - int32 &structCopyOffset); + void SelectParmListForAggregate(BaseNode &parent, BaseNode &argExpr, ListOperand &srcOpnds, + AArch64CallConvImpl &parmLocator, int32 &structCopyOffset, int32 argNo); size_t SelectParmListGetStructReturnSize(StmtNode &naryNode); bool MarkParmListCall(BaseNode &expr); - void SelectParmListPreprocessLargeStruct(BaseNode &argExpr, int32 &structCopyOffset); - void SelectParmListPreprocess(const StmtNode &naryNode, size_t start, std::set &specialArgs); + void SelectParmListPreprocessLargeStruct(BaseNode &parent, BaseNode &argExpr, int32 &structCopyOffset, int32 argNo); + void SelectParmListPreprocess(StmtNode &naryNode, size_t start, std::set &specialArgs); void SelectParmList(StmtNode &naryNode, ListOperand &srcOpnds, bool isCallNative = false); Operand *SelectClearStackCallParam(const AddrofNode &expr, int64 &offsetValue); void SelectClearStackCallParmList(const StmtNode &naryNode, ListOperand &srcOpnds, diff --git a/src/mapleall/maple_be/include/cg/cgfunc.h b/src/mapleall/maple_be/include/cg/cgfunc.h index d10b1f8465..d1000e190c 100644 --- a/src/mapleall/maple_be/include/cg/cgfunc.h +++ b/src/mapleall/maple_be/include/cg/cgfunc.h @@ -1150,8 +1150,8 @@ class CGFunc { #endif MapleMap vregsToPregsMap; uint32 totalInsns = 0; - int32 structCopySize; - int32 maxParamStackSize; + int32 structCopySize = 0; + int32 maxParamStackSize = 0; static constexpr int kRegIncrStepLen = 80; /* reg number increate step length */ bool hasVLAOrAlloca = false; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 6fdf8ddff6..0853b46879 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -161,6 +161,28 @@ bool IsBlkassignForPush(const BlkassignoffNode &bNode) { return spBased; } +MIRStructType *AArch64CGFunc::GetLmbcStructArgType(BaseNode &stmt, int32 argNo) { + MIRType *ty = nullptr; + if (stmt.GetOpCode() == OP_call) { + CallNode &callNode = static_cast(stmt); + MIRFunction *callFunc = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(callNode.GetPUIdx()); + if (callFunc->GetFormalCount() < (argNo + 1)) { + return nullptr; /* formals less than actuals */ + } + ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(callFunc->GetFormalDefVec()[argNo].formalTyIdx); + } else if (stmt.GetOpCode() == OP_icallproto) { + IcallNode &icallproto = static_cast(stmt); + MIRType *type = GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallproto.GetRetTyIdx()); + MIRFuncType *fType = static_cast(type); + if (fType->GetParamTypeList().size() < (argNo + 1)) { + return nullptr; + } + ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(fType->GetNthParamType(argNo)); + } + CHECK_FATAL(ty && ty->IsStructType(), "lmbc agg arg error"); + return static_cast(ty); +} + RegOperand &AArch64CGFunc::GetOrCreateResOperand(const BaseNode &parent, PrimType primType) { RegOperand *resOpnd = nullptr; if (parent.GetOpCode() == OP_regassign) { @@ -3095,15 +3117,19 @@ RegOperand *AArch64CGFunc::LmbcStructReturnLoad(int32 offset) { return result; } -Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff) { +Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode &ireadoff /*, MIRType &ty, + ListOperand &srcOpnds, AArch64CallConvImpl &parmLocator*/) { int32 offset = ireadoff.GetOffset(); PrimType primType = ireadoff.GetPrimType(); uint32 bytelen = GetPrimTypeSize(primType); +#if 1 uint32 bitlen = bytelen * kBitsPerByte; +#endif RegType regty = GetRegTyFromPrimTy(primType); RegOperand *result = nullptr; if (offset >= 0) { - LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(static_cast(offset)); +#if 1 + LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(offset); if (info->GetPrimType() == PTY_agg) { if (info->IsOnStack()) { result = GenLmbcParamLoad(info->GetOnStackOffset(), GetPrimTypeSize(PTY_a64), kRegTyInt, PTY_a64); @@ -3125,10 +3151,23 @@ Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode result = &GetOrCreatePhysicalRegisterOperand(static_cast(info->GetRegNO()), bitlen, regty); } } +#endif + CHECK_FATAL(0, "Invalid ireadfpoff offset"); } else { if (primType == PTY_agg) { - CHECK_FATAL(parent.GetOpCode() == OP_regassign, "SelectIreadfpoff of agg"); - result = LmbcStructReturnLoad(offset); +#if OLD_LMBC // TBD + if (parent.GetOpCode() == OP_call || parent.GetOpCode() == OP_icallproto) { + /* ireadfpoff is now for loading locals under calls. Large agg arg is handled via + SelectParmListPreprocess, Hence only small agg is handled here */ + SelectParmListIreadSmallAggregate(ireadoff, ty, srcOpnds, 0, parmLocator); + } else { +#endif + /* agg return */ + CHECK_FATAL(parent.GetOpCode() == OP_regassign, "SelectIreadfpoff of agg"); + result = LmbcStructReturnLoad(offset); +#if OLD_LMBC // TBD + } +#endif } else { result = GenLmbcParamLoad(offset, bytelen, regty, primType); } @@ -7354,12 +7393,26 @@ void AArch64CGFunc::SelectParmListDreadSmallAggregate(const MIRSymbol &sym, MIRT } } -void AArch64CGFunc::SelectParmListIreadSmallAggregate(const IreadNode &iread, MIRType &structType, +void AArch64CGFunc::SelectParmListIreadSmallAggregate(BaseNode &iread, MIRType &structType, ListOperand &srcOpnds, int32 offset, AArch64CallConvImpl &parmLocator) { int32 symSize = GetBecommon().GetTypeSize(structType.GetTypeIndex().GetIdx()); - RegOperand *addrOpnd0 = static_cast(HandleExpr(iread, *(iread.Opnd(0)))); - RegOperand *addrOpnd1 = &LoadIntoRegister(*addrOpnd0, iread.Opnd(0)->GetPrimType()); + RegOperand *addrOpnd1; + if (iread.GetOpCode() == OP_iread) { + RegOperand *addrOpnd0 = static_cast(HandleExpr(iread, *(iread.Opnd(0)))); + addrOpnd1 = &LoadIntoRegister(*addrOpnd0, iread.Opnd(0)->GetPrimType()); + } else if (iread.GetOpCode() == OP_ireadfpoff) { + IreadFPoffNode &ireadoff = static_cast(iread); + RegOperand *rfp = &GetOrCreatePhysicalRegisterOperand(RFP, k64BitSize, kRegTyInt); + RegOperand *addrOpnd0 = &CreateRegisterOperandOfType(PTY_a64); + ImmOperand &immOpnd = CreateImmOperand(ireadoff.GetOffset(), k32BitSize, true); + GetCurBB()->AppendInsn(GetCG()->BuildInstruction(MOP_xaddrri12, *addrOpnd0, *rfp, immOpnd)); + addrOpnd1 = &LoadIntoRegister(*addrOpnd0, PTY_i64); + } else if (iread.GetOpCode() == OP_ireadoff) { + IreadoffNode &ireadoff = static_cast(iread); + RegOperand *addrOpnd0 = static_cast(HandleExpr(ireadoff, *(ireadoff.Opnd(0)))); + addrOpnd1 = &LoadIntoRegister(*addrOpnd0, PTY_i64); + } CCLocInfo ploc; parmLocator.LocateNextParm(structType, ploc); if (ploc.reg0 == 0) { @@ -7732,8 +7785,8 @@ void AArch64CGFunc::CreateCallStructMemcpyToParamReg(MIRType &structType, int32 } } -void AArch64CGFunc::SelectParmListForAggregate(BaseNode &argExpr, ListOperand &srcOpnds, - AArch64CallConvImpl &parmLocator, int32 &structCopyOffset) { +void AArch64CGFunc::SelectParmListForAggregate(BaseNode &parent, BaseNode &argExpr, ListOperand &srcOpnds, + AArch64CallConvImpl &parmLocator, int32 &structCopyOffset, int32 argNo) { uint64 symSize; int32 rhsOffset = 0; if (argExpr.GetOpCode() == OP_dread) { @@ -7781,6 +7834,32 @@ void AArch64CGFunc::SelectParmListForAggregate(BaseNode &argExpr, ListOperand &s } else { SelectParmListIreadLargeAggregate(iread, *ty, srcOpnds, parmLocator, structCopyOffset, rhsOffset); } + } else if (argExpr.GetOpCode() == OP_ireadfpoff) { + IreadFPoffNode &iread = static_cast(argExpr); + MIRStructType *ty = GetLmbcStructArgType(parent, argNo); + if (ty == nullptr) { /* param < arg */ + return; + } + symSize = GetBecommon().GetTypeSize(ty->GetTypeIndex().GetIdx()); + if (symSize <= k16ByteSize) { + SelectParmListIreadSmallAggregate(iread, *ty, srcOpnds, rhsOffset, parmLocator); + } else { + CreateCallStructMemcpyToParamReg(*ty, structCopyOffset, parmLocator, srcOpnds); + structCopyOffset += static_cast(RoundUp(symSize, kSizeOfPtr)); + } + } else if (argExpr.GetOpCode() == OP_ireadoff) { + IreadoffNode &iread = static_cast(argExpr); + MIRStructType *ty = GetLmbcStructArgType(parent, argNo); + if (ty == nullptr) { + return; + } + symSize = GetBecommon().GetTypeSize(ty->GetTypeIndex().GetIdx()); + if (symSize <= k16ByteSize) { + SelectParmListIreadSmallAggregate(iread, *ty, srcOpnds, rhsOffset, parmLocator); + } else { + CreateCallStructMemcpyToParamReg(*ty, structCopyOffset, parmLocator, srcOpnds); + structCopyOffset += static_cast(RoundUp(symSize, kSizeOfPtr)); + } } else { CHECK_FATAL(false, "NYI"); } @@ -7823,7 +7902,7 @@ size_t AArch64CGFunc::SelectParmListGetStructReturnSize(StmtNode &naryNode) { return 0; } -void AArch64CGFunc::SelectParmListPreprocessLargeStruct(BaseNode &argExpr, int32 &structCopyOffset) { +void AArch64CGFunc::SelectParmListPreprocessLargeStruct(BaseNode &parent, BaseNode &argExpr, int32 &structCopyOffset, int32 argNo) { uint64 symSize; int32 rhsOffset = 0; if (argExpr.GetOpCode() == OP_dread) { @@ -7870,6 +7949,22 @@ void AArch64CGFunc::SelectParmListPreprocessLargeStruct(BaseNode &argExpr, int32 uint32 numMemOp = static_cast(RoundUp(symSize, kSizeOfPtr) / kSizeOfPtr); structCopyOffset += static_cast(numMemOp * kSizeOfPtr); } + } else if (argExpr.GetOpCode() == OP_ireadfpoff) { + IreadFPoffNode &ireadoff = static_cast(argExpr); + MIRStructType *ty = GetLmbcStructArgType(parent, argNo); + symSize = GetBecommon().GetTypeSize(ty->GetTypeIndex()); + if (symSize > 16 /*kParmMemcpySize*/) { +#if OLD_LMBC // TBD + MemOperand *addrOpnd0 = GenLmbcFpMemOperand(ireadoff.GetOffset(), kSizeOfPtr, RFP); + RegOperand *addrOpnd1 = &LoadIntoRegister(*addrOpnd0, PTY_i64); +#endif + RegOperand *rfp = &GetOrCreatePhysicalRegisterOperand(RFP, k64BitSize, kRegTyInt); + RegOperand *addrOpnd = &CreateRegisterOperandOfType(PTY_a64); + ImmOperand &immOpnd = CreateImmOperand(ireadoff.GetOffset(), k32BitSize, true); + GetCurBB()->AppendInsn(GetCG()->BuildInstruction(MOP_xaddrri12, *addrOpnd, *rfp, immOpnd)); + CreateCallStructParamMemcpy(nullptr, addrOpnd, static_cast(symSize), structCopyOffset, 0); + structCopyOffset += static_cast(RoundUp(symSize, kSizeOfPtr)); + } } } @@ -7901,7 +7996,7 @@ bool AArch64CGFunc::MarkParmListCall(BaseNode &expr) { return false; } -void AArch64CGFunc::SelectParmListPreprocess(const StmtNode &naryNode, size_t start, std::set &specialArgs) { +void AArch64CGFunc::SelectParmListPreprocess(StmtNode &naryNode, size_t start, std::set &specialArgs) { size_t i = start; int32 structCopyOffset = GetMaxParamStackSize() - GetStructCopySize(); for (; i < naryNode.NumOpnds(); ++i) { @@ -7914,7 +8009,7 @@ void AArch64CGFunc::SelectParmListPreprocess(const StmtNode &naryNode, size_t st if (primType != PTY_agg) { continue; } - SelectParmListPreprocessLargeStruct(*argExpr, structCopyOffset); + SelectParmListPreprocessLargeStruct(naryNode, *argExpr, structCopyOffset, i); } } @@ -8014,7 +8109,7 @@ void AArch64CGFunc::SelectParmList(StmtNode &naryNode, ListOperand &srcOpnds, bo } /* use alloca */ if (primType == PTY_agg) { - SelectParmListForAggregate(*argExpr, srcOpnds, parmLocator, structCopyOffset); + SelectParmListForAggregate(naryNode, *argExpr, srcOpnds, parmLocator, structCopyOffset, i); continue; } ty = GlobalTables::GetTypeTable().GetTypeTable()[static_cast(primType)]; @@ -9418,7 +9513,11 @@ Operand *AArch64CGFunc::GetBaseReg(const AArch64SymbolAlloc &symAlloc) { } if (fsp == nullptr) { - fsp = &GetOrCreatePhysicalRegisterOperand(RFP, kSizeOfPtr * kBitsPerByte, kRegTyInt); + if (GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { + fsp = &GetOrCreatePhysicalRegisterOperand(RSP, kSizeOfPtr * kBitsPerByte, kRegTyInt); + } else { + fsp = &GetOrCreatePhysicalRegisterOperand(RFP, kSizeOfPtr * kBitsPerByte, kRegTyInt); + } } return fsp; } diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index 3d0fbd96d6..ed5342b1a4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -58,7 +58,9 @@ uint32 AArch64MemLayout::ComputeStackSpaceRequirementForCall(StmtNode &stmt, in ty = GlobalTables::GetTypeTable().GetTypeTable()[static_cast(opnd->GetPrimType())]; } else { Opcode opndOpcode = opnd->GetOpCode(); - ASSERT(opndOpcode == OP_dread || opndOpcode == OP_iread, "opndOpcode should be OP_dread or OP_iread"); + if (be.GetMIRModule().GetFlavor() != kFlavorLmbc) { + ASSERT(opndOpcode == OP_dread || opndOpcode == OP_iread, "opndOpcode should be OP_dread or OP_iread"); + } if (opndOpcode == OP_dread) { DreadNode *dread = static_cast(opnd); MIRSymbol *sym = be.GetMIRModule().CurFunction()->GetLocalOrGlobalSymbol(dread->GetStIdx()); @@ -72,8 +74,7 @@ uint32 AArch64MemLayout::ComputeStackSpaceRequirementForCall(StmtNode &stmt, in ty = static_cast(ty)->GetFieldType(dread->GetFieldID()); } } - } else { - /* OP_iread */ + } else if (opndOpcode == OP_iread) { IreadNode *iread = static_cast(opnd); ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(iread->GetTyIdx()); ASSERT(ty->GetKind() == kTypePointer, "expect pointer"); @@ -87,6 +88,11 @@ uint32 AArch64MemLayout::ComputeStackSpaceRequirementForCall(StmtNode &stmt, in ty = static_cast(ty)->GetFieldType(iread->GetFieldID()); } } + } else if ((opndOpcode == OP_ireadfpoff || opndOpcode == OP_ireadoff || opndOpcode == OP_dreadoff) && opnd->GetPrimType() == PTY_agg) { + ty = static_cast(cgFunc)->GetLmbcStructArgType(stmt, i); + } + if (ty == nullptr) { /* type mismatch */ + continue; } } CCLocInfo ploc; @@ -190,6 +196,7 @@ void AArch64MemLayout::LayoutVarargParams() { } void AArch64MemLayout::LayoutFormalParams() { +#if OLD_LMBC // TBD bool isLmbc = (be.GetMIRModule().GetFlavor() == kFlavorLmbc); if (isLmbc && mirFunction->GetFormalCount() == 0) { /* @@ -201,6 +208,7 @@ void AArch64MemLayout::LayoutFormalParams() { segArgsRegPassed.SetSize(mirFunction->GetOutParmSize()); return; } +#endif AArch64CallConvImpl parmLocator(be); CCLocInfo ploc; @@ -255,8 +263,10 @@ void AArch64MemLayout::LayoutFormalParams() { segArgsRegPassed.SetSize(static_cast(RoundUp(segArgsRegPassed.GetSize(), align))); symLoc->SetOffset(segArgsRegPassed.GetSize()); segArgsRegPassed.SetSize(segArgsRegPassed.GetSize() + size); +#if OLD_LMBC // TBD } else if (isLmbc) { segArgsRegPassed.SetSize(segArgsRegPassed.GetSize() + k8ByteSize); +#endif } } else { /* stack */ uint32 size; @@ -371,11 +381,15 @@ void AArch64MemLayout::LayoutReturnRef(std::vector &returnDelays, symLoc->SetOffset(segRefLocals.GetSize()); segRefLocals.SetSize(segRefLocals.GetSize() + be.GetTypeSize(tyIdx)); } +#if OLD_LMBC // TBD if (be.GetMIRModule().GetFlavor() == kFlavorLmbc) { segArgsToStkPass.SetSize(mirFunction->GetOutParmSize() + kDivide2 * k8ByteSize); } else { segArgsToStkPass.SetSize(FindLargestActualArea(structCopySize)); } +#else + segArgsToStkPass.SetSize(FindLargestActualArea(structCopySize)); +#endif maxParmStackSize = static_cast(segArgsToStkPass.GetSize()); if (Globals::GetInstance()->GetOptimLevel() == 0) { AssignSpillLocationsToPseudoRegisters(); @@ -527,14 +541,18 @@ uint64 AArch64MemLayout::StackFrameSize() const { uint64 total = segArgsRegPassed.GetSize() + static_cast(cgFunc)->SizeOfCalleeSaved() + GetSizeOfRefLocals() + locals().GetSize() + GetSizeOfSpillReg(); +#if OLD_LMBC // TBD if (cgFunc->GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif if (GetSizeOfGRSaveArea() > 0) { total += RoundUp(GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); } if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } +#if OLD_LMBC // TBD } +#endif /* * if the function does not have VLA nor alloca, diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 9b4b49c699..97814c0ad2 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -1115,9 +1115,11 @@ void AArch64GenProEpilog::AppendInstructionAllocateCallFrameDebug(AArch64reg reg ipoint = cgFunc.GetCurBB()->GetLastInsn(); cfiOffset = stackFrameSize; (void)InsertCFIDefCfaOffset(cfiOffset, *ipoint); +#if OLD_LMBC //TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { argsToStkPassSize -= (kDivide2 * k8ByteSize); } +#endif ipoint = &CreateAndAppendInstructionForAllocateCallFrame(argsToStkPassSize, reg0, reg1, rty); CHECK_FATAL(ipoint != nullptr, "ipoint should not be nullptr at this point"); cfiOffset = GetOffsetFromCFA(); @@ -1217,7 +1219,9 @@ void AArch64GenProEpilog::GeneratePushRegs() { Operand &spOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); +#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; +#endif if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; if (isLmbc) { @@ -1255,6 +1259,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); @@ -1262,6 +1267,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { offset = static_cast((memLayout->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - memLayout->SizeOfArgsToStackPass()); /* for FP/LR */ } +#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignmentInt; @@ -1322,18 +1328,22 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { } uint32 dataSizeBits = size * kBitsPerByte; uint32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif offset = static_cast(memlayout->GetGRSaveAreaBaseLoc()); /* SP reference */ if ((memlayout->GetSizeOfGRSaveArea() % kAarch64StackPtrAlignment) > 0) { offset += size; /* End of area should be aligned. Hole between VR and GR area */ } +#if OLD_LMBC // TBD } else { offset = (UINT32_MAX - memlayout->GetSizeOfGRSaveArea()) + 1; /* FP reference */ if ((memlayout->GetSizeOfGRSaveArea() % kAarch64StackPtrAlignment) > 0) { offset -= size; } } - uint32 grSize = (UINT32_MAX - offset) + 1; + uint32 grSize = -offset; +#endif uint32 start_regno = k8BitSize - (memlayout->GetSizeOfGRSaveArea() / size); ASSERT(start_regno <= k8BitSize, "Incorrect starting GR regno for GR Save Area"); for (uint32 i = start_regno + static_cast(R0); i < static_cast(R8); i++) { @@ -1344,11 +1354,15 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { } } Operand *stackLoc; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif stackLoc = &aarchCGFunc.CreateStkTopOpnd(offset + tmpOffset, dataSizeBits); +#if OLD_LMBC // TBD } else { stackLoc = aarchCGFunc.GenLmbcFpMemOperand(offset, size); } +#endif RegOperand ® = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(static_cast(i), k64BitSize, kRegTyInt); Insn &inst = @@ -1357,11 +1371,15 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { offset += size; } if (!CGOptions::UseGeneralRegOnly()) { +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif offset = static_cast(memlayout->GetVRSaveAreaBaseLoc()); +#if OLD_LMBC // TBD } else { offset = (UINT32_MAX - (memlayout->GetSizeOfVRSaveArea() + grSize)) + 1; } +#endif start_regno = k8BitSize - (memlayout->GetSizeOfVRSaveArea() / (size * k2BitSize)); ASSERT(start_regno <= k8BitSize, "Incorrect starting GR regno for VR Save Area"); for (uint32 i = start_regno + static_cast(V0); i < static_cast(V8); i++) { @@ -1372,11 +1390,15 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() { } } Operand *stackLoc; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif stackLoc = &aarchCGFunc.CreateStkTopOpnd(offset + tmpOffset, dataSizeBits); +#if OLD_LMBC // TBD } else { stackLoc = aarchCGFunc.GenLmbcFpMemOperand(offset, size); } +#endif RegOperand ® = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(static_cast(i), k64BitSize, kRegTyFloat); Insn &inst = @@ -1478,7 +1500,9 @@ void AArch64GenProEpilog::GenerateProlog(BB &bb) { } if (useFP) { Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); +#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; +#endif int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; @@ -1681,7 +1705,10 @@ void AArch64GenProEpilog::AppendInstructionDeallocateCallFrameDebug(AArch64reg r * ldp/stp's imm should be within -512 and 504; * if ldp's imm > 504, we fall back to the ldp-add version */ +#if OLD_LMBC // TBD bool isLmbc = (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc); +#endif + bool isLmbc = false; if (cgFunc.HasVLAOrAlloca() || argsToStkPassSize == 0 || isLmbc) { int lmbcOffset = 0; if (isLmbc == false) { @@ -1767,6 +1794,7 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); @@ -1775,6 +1803,7 @@ void AArch64GenProEpilog::GeneratePopRegs() { (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - /* for FP/LR */ memLayout->SizeOfArgsToStackPass()); } +#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignmentInt; -- Gitee From e79c7a64666a9d0edec00e86ccb3673bc61b8f7c Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 20 Jun 2022 21:57:07 -0700 Subject: [PATCH 126/179] Turned some optimizations back off under lmbc and re-enabled some old code The OLD_LMBC define-disabled code caused coremark to fail execution. I have to put #define OLD_LMBC on aarch64_memlayout.cpp and aarch64_proepilog.cpp so coremark can work again. --- .../include/cg/aarch64/aarch64_phases.def | 34 +++++++++++-------- .../src/cg/aarch64/aarch64_memlayout.cpp | 2 ++ .../src/cg/aarch64/aarch64_proepilog.cpp | 5 ++- 3 files changed, 26 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 531e7f0535..e5627ecba3 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,16 +17,18 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + } /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); @@ -34,8 +36,10 @@ ADDTARGETPHASE("ico", CGOptions::DoICO()) ADDTARGETPHASE("cfgo", !GetMIRModule()->IsCModule() && CGOptions::DoCFGO()); - ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); - ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); +if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", CGOptions::DoStoreLoadOpt() && !CGOptions::DoCGSSA()); + ADDTARGETPHASE("globalopt", CGOptions::DoGlobalOpt()); +} ADDTARGETPHASE("clearrdinfo", (CGOptions::DoStoreLoadOpt()) || CGOptions::DoGlobalOpt()); ADDTARGETPHASE("prepeephole1", CGOptions::DoPrePeephole()); @@ -45,8 +49,10 @@ ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + } ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index ed5342b1a4..19e24b2a78 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -17,6 +17,8 @@ #include "becommon.h" #include "mir_nodes.h" +#define OLD_LMBC 1 + namespace maplebe { using namespace maple; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 97814c0ad2..b1e0ad5b6d 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -16,6 +16,8 @@ #include "cg_option.h" #include "cgfunc.h" +#define OLD_LMBC 1 + namespace maplebe { using namespace maple; @@ -1707,8 +1709,9 @@ void AArch64GenProEpilog::AppendInstructionDeallocateCallFrameDebug(AArch64reg r */ #if OLD_LMBC // TBD bool isLmbc = (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc); -#endif +#else bool isLmbc = false; +#endif if (cgFunc.HasVLAOrAlloca() || argsToStkPassSize == 0 || isLmbc) { int lmbcOffset = 0; if (isLmbc == false) { -- Gitee From 0d7a1873a249f8295ad5dea4803ebd6c79b5b306 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Wed, 22 Jun 2022 22:07:59 -0700 Subject: [PATCH 127/179] Handle addrofoff as operand of OP_asm --- .../maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 12 ++++++++++++ src/mapleall/maple_ir/src/bin_func_import.cpp | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 0853b46879..ad6670a4a5 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1256,6 +1256,18 @@ void AArch64CGFunc::SelectAsm(AsmNode &node) { } break; } + case OP_addrofoff: { + auto &addrofoffNode = static_cast(*node.Opnd(i)); + Operand *inOpnd = SelectAddrofoff(addrofoffNode, node); + listInputOpnd->PushOpnd(static_cast(*inOpnd)); + PrimType pType = addrofoffNode.GetPrimType(); + listInRegPrefix->stringList.push_back( + static_cast(&CreateStringOperand(GetRegPrefixFromPrimType(pType, inOpnd->GetSize(), str)))); + if (isOutputTempNode) { + rPlusOpnd.emplace_back(std::make_pair(inOpnd, pType)); + } + break; + } case OP_constval: { CHECK_FATAL(!isOutputTempNode, "Unexpect"); auto &constNode = static_cast(*node.Opnd(i)); diff --git a/src/mapleall/maple_ir/src/bin_func_import.cpp b/src/mapleall/maple_ir/src/bin_func_import.cpp index 6fdb94c85c..ac89300f60 100644 --- a/src/mapleall/maple_ir/src/bin_func_import.cpp +++ b/src/mapleall/maple_ir/src/bin_func_import.cpp @@ -45,7 +45,7 @@ void BinaryMplImport::ImportFuncIdInfo(MIRFunction *func) { func->SetPuidxOrigin(static_cast(ReadNum())); ImportInfoVector(func->GetInfoVector(), func->InfoIsString()); if (mod.GetFlavor() == kFlavorLmbc) { - func->SetFrameSize(static_cast(ReadNum())); + func->SetFrameSize(static_cast(ReadNum())); } } -- Gitee From f4269c349ebae3907f0cfb8bbaf420a88ea80ccd Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Fri, 24 Jun 2022 21:00:36 -0700 Subject: [PATCH 128/179] Handled more types of asm operands --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index ad6670a4a5..131e0d65eb 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1268,6 +1268,30 @@ void AArch64CGFunc::SelectAsm(AsmNode &node) { } break; } + case OP_ireadoff: { + IreadoffNode *ireadoff = static_cast(node.Opnd(i)); + Operand *inOpnd = SelectIreadoff(node, *ireadoff); + listInputOpnd->PushOpnd(static_cast(*inOpnd)); + PrimType pType = ireadoff->GetPrimType(); + listInRegPrefix->stringList.push_back( + static_cast(&CreateStringOperand(GetRegPrefixFromPrimType(pType, inOpnd->GetSize(), str)))); + if (isOutputTempNode) { + rPlusOpnd.emplace_back(std::make_pair(inOpnd, pType)); + } + break; + } + case OP_add: { + BinaryNode *addNode = static_cast(node.Opnd(i)); + Operand *inOpnd = SelectAdd(*addNode, *HandleExpr(*addNode, *addNode->Opnd(0)), *HandleExpr(*addNode, *addNode->Opnd(1)), node); + listInputOpnd->PushOpnd(static_cast(*inOpnd)); + PrimType pType = addNode->GetPrimType(); + listInRegPrefix->stringList.push_back( + static_cast(&CreateStringOperand(GetRegPrefixFromPrimType(pType, inOpnd->GetSize(), str)))); + if (isOutputTempNode) { + rPlusOpnd.emplace_back(std::make_pair(inOpnd, pType)); + } + break; + } case OP_constval: { CHECK_FATAL(!isOutputTempNode, "Unexpect"); auto &constNode = static_cast(*node.Opnd(i)); -- Gitee From bd7a2c8bdd9cad0acee8de26adb449aa3382199e Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Sat, 25 Jun 2022 12:21:10 -0700 Subject: [PATCH 129/179] More edits to rebase to master branch --- src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 2 +- src/mapleall/maple_be/src/cg/cgfunc.cpp | 4 ++-- src/mapleall/maple_ir/include/bin_mpl_export.h | 1 - src/mapleall/maple_ir/src/bin_mpl_export.cpp | 3 +-- src/mapleall/maple_me/include/lmbc_memlayout.h | 4 +--- 5 files changed, 5 insertions(+), 9 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 131e0d65eb..dd8f68c2ad 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -2133,7 +2133,7 @@ MIRType *AArch64CGFunc::LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector(static_cast(src)->GetRegisterNumber()); diff --git a/src/mapleall/maple_be/src/cg/cgfunc.cpp b/src/mapleall/maple_be/src/cg/cgfunc.cpp index b7aa8217b4..6529e6a874 100644 --- a/src/mapleall/maple_be/src/cg/cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/cgfunc.cpp @@ -1587,7 +1587,7 @@ void CGFunc::CreateLmbcFormalParamInfo() { stackOffset += (typeSize + 7) & (-8); LmbcFormalParamInfo *info = GetMemoryPool()->New(primType, offset, typeSize); lmbcParamVec.push_back(info); - if (idx == 0 && lmbcFunc.IsFirstArgReturn()) { + if (idx == 0 && func.IsFirstArgReturn()) { info->SetIsReturn(); } if (type->GetKind() == kTypeStruct) { @@ -1604,7 +1604,7 @@ void CGFunc::CreateLmbcFormalParamInfo() { } } else { /* No aggregate pass by value here */ - for (StmtNode *stmt = lmbcFunc.GetBody()->GetFirst(); stmt != nullptr; stmt = stmt->GetNext()) { + for (StmtNode *stmt = func.GetBody()->GetFirst(); stmt != nullptr; stmt = stmt->GetNext()) { if (stmt == nullptr) { break; } diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 9cada84eb4..918c8e04eb 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,7 +181,6 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; - MIRFunction *curFunc = nullptr; size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; diff --git a/src/mapleall/maple_ir/src/bin_mpl_export.cpp b/src/mapleall/maple_ir/src/bin_mpl_export.cpp index e6f3e25d05..9bc2061fad 100644 --- a/src/mapleall/maple_ir/src/bin_mpl_export.cpp +++ b/src/mapleall/maple_ir/src/bin_mpl_export.cpp @@ -1110,7 +1110,6 @@ void BinaryMplExport::WriteSymField(uint64 contentIdx) { for (auto sit = GetMIRModule().GetSymbolDefOrder().begin(); sit != GetMIRModule().GetSymbolDefOrder().end(); ++sit) { MIRSymbol *s = GlobalTables::GetGsymTable().GetSymbolFromStidx(sit->Idx()); - ASSERT(s != nullptr, "null ptr check"); // Verify: all wpofake variables should have been deleted from globaltable ASSERT(!(s->IsWpoFakeParm() || s->IsWpoFakeRet()) || s->IsDeleted(), "wpofake var not deleted"); MIRStorageClass storageClass = s->GetStorageClass(); @@ -1242,7 +1241,7 @@ void BinaryMplExport::AppendAt(const std::string &name, int32 offset) { LogInfo::MapleLogger(kLlErr) << "Error while opening the binary file: " << name << '\n'; FATAL(kLncFatal, "Error while creating the binary file: %s\n", name.c_str()); } - int seekRet = fseek(f, static_cast(offset), SEEK_SET); + int seekRet = fseek(f, (long int)offset, SEEK_SET); CHECK_FATAL(seekRet == 0, "Call fseek failed."); size_t size = buf.size(); size_t k = fwrite(&buf[0], sizeof(uint8), size, f); diff --git a/src/mapleall/maple_me/include/lmbc_memlayout.h b/src/mapleall/maple_me/include/lmbc_memlayout.h index 833b357561..923c118665 100644 --- a/src/mapleall/maple_me/include/lmbc_memlayout.h +++ b/src/mapleall/maple_me/include/lmbc_memlayout.h @@ -42,9 +42,7 @@ class SymbolAlloc { public: SymbolAlloc() : mem_segment(nullptr), offset(0) {} - ~SymbolAlloc() { - mem_segment = nullptr; - } + ~SymbolAlloc() {} MemSegment *mem_segment; int32 offset; -- Gitee From 40fe10b19ffe385e03f4095453096c508e791dba Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:16:12 -0700 Subject: [PATCH 130/179] Turn on globalopt for lmbc, but leave SSA opt off --- src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def | 6 ++---- src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp | 4 +++- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index e5627ecba3..856c48e6bd 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -49,10 +49,8 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); - } + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 4a2f257321..6b5d902cb4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,7 +412,9 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - CHECK_FATAL(false, "check case in ssa"); + if (cgFunc.GetCG()->IsLmbc() == false) { + CHECK_FATAL(false, "check case in ssa"); + } } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From e6bcb30f4d2960cf69b8f43aa55b22ae9a8e8804 Mon Sep 17 00:00:00 2001 From: William Chen Date: Mon, 13 Jun 2022 14:06:17 -0700 Subject: [PATCH 131/179] Do not optimize for ssa for physical regs. --- .../include/cg/aarch64/aarch64_phases.def | 22 +++++++++---------- .../src/cg/aarch64/aarch64_global.cpp | 4 +--- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 856c48e6bd..f11ca1435e 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,18 +17,16 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); - } + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 6b5d902cb4..4a2f257321 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,9 +412,7 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - if (cgFunc.GetCG()->IsLmbc() == false) { - CHECK_FATAL(false, "check case in ssa"); - } + CHECK_FATAL(false, "check case in ssa"); } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From d8272090c68b0be71bbaa8dd199a765255a3fdf6 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 20 Jun 2022 21:57:07 -0700 Subject: [PATCH 132/179] Turned some optimizations back off under lmbc and re-enabled some old code The OLD_LMBC define-disabled code caused coremark to fail execution. I have to put #define OLD_LMBC on aarch64_memlayout.cpp and aarch64_proepilog.cpp so coremark can work again. --- .../include/cg/aarch64/aarch64_phases.def | 28 +++++++++++-------- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index f11ca1435e..e5627ecba3 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,16 +17,18 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + } /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); @@ -47,8 +49,10 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + } ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); -- Gitee From 7068312ac51fb13a737c74df09aead83d4458deb Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Sat, 25 Jun 2022 14:55:37 -0700 Subject: [PATCH 133/179] Fixed a rebase bug --- src/mapleall/maple_me/include/lmbc_memlayout.h | 12 +++--------- src/mapleall/maple_me/src/lmbc_lower.cpp | 4 ++-- 2 files changed, 5 insertions(+), 11 deletions(-) diff --git a/src/mapleall/maple_me/include/lmbc_memlayout.h b/src/mapleall/maple_me/include/lmbc_memlayout.h index 923c118665..83b59ba69f 100644 --- a/src/mapleall/maple_me/include/lmbc_memlayout.h +++ b/src/mapleall/maple_me/include/lmbc_memlayout.h @@ -38,14 +38,9 @@ typedef enum { class MemSegment; // describes where a symbol is allocated -class SymbolAlloc { - public: - SymbolAlloc() : mem_segment(nullptr), offset(0) {} - - ~SymbolAlloc() {} - - MemSegment *mem_segment; - int32 offset; +struct SymbolAlloc { + MemSegment *mem_segment = nullptr; + int32 offset = 0; }; // class SymbolAlloc // keeps track of the allocation of a memory segment @@ -59,7 +54,6 @@ class MemSegment { MemSegmentKind kind; int32 size; // size is negative if allocated offsets are negative - SymbolAlloc how_alloc; // this segment may be allocated inside another segment }; // class MemSegment class LMBCMemLayout { diff --git a/src/mapleall/maple_me/src/lmbc_lower.cpp b/src/mapleall/maple_me/src/lmbc_lower.cpp index 9ba84151e5..8cb339f657 100644 --- a/src/mapleall/maple_me/src/lmbc_lower.cpp +++ b/src/mapleall/maple_me/src/lmbc_lower.cpp @@ -25,8 +25,8 @@ PregIdx LMBCLowerer::GetSpecialRegFromSt(const MIRSymbol *sym) { if (storageClass == kScAuto) { CHECK(sym->GetStIndex() < memlayout->sym_alloc_table.size(), "index out of range in LMBCLowerer::GetSpecialRegFromSt"); - SymbolAlloc symalloc = memlayout->sym_alloc_table[sym->GetStIndex()]; - if (symalloc.mem_segment->kind == MS_FPbased) { + SymbolAlloc *symalloc = &memlayout->sym_alloc_table[sym->GetStIndex()]; + if (symalloc->mem_segment->kind == MS_FPbased) { specreg = -kSregFp; } else { CHECK_FATAL(false, "LMBCLowerer::LowerDread: bad memory layout for local variable"); -- Gitee From c23d0ddf62b6ce97826b98c0dd779ea90a71dd76 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Mon, 27 Jun 2022 14:41:54 -0700 Subject: [PATCH 134/179] Update for agg ret, caller/callee save offset. --- .../include/cg/aarch64/aarch64_cgfunc.h | 2 +- .../src/cg/aarch64/aarch64_cgfunc.cpp | 44 +++++++++++++------ .../src/cg/aarch64/aarch64_memlayout.cpp | 2 - .../src/cg/aarch64/aarch64_proepilog.cpp | 8 +--- 4 files changed, 33 insertions(+), 23 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index a2e3c6a0cb..b4aee3214c 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -130,7 +130,7 @@ class AArch64CGFunc : public CGFunc { uint32 LmbcFindTotalStkUsed(std::vector* paramList); uint32 LmbcTotalRegsUsed(); void LmbcSelectParmList(ListOperand *srcOpnds, bool isArgReturn); - bool LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src); + bool LmbcSmallAggForRet(BaseNode &bNode, Operand *src); bool LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src, std::vector **parmList); void SelectAggDassign(DassignNode &stmt) override; void SelectIassign(IassignNode &stmt) override; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index dd8f68c2ad..290035704b 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1487,6 +1487,12 @@ void AArch64CGFunc::SelectRegassign(RegassignNode &stmt, Operand &opnd0) { prev->SetMOP(MOP_xldrsw); } } + if (lhsSize == PTY_agg && (stmt.Opnd(0)->GetOpCode() == OP_ireadoff || stmt.Opnd(0)->GetOpCode() == OP_ireadfpoff)) { + PregIdx pregIdx = stmt.GetRegIdx(); + if ((-pregIdx) == kSregRetval0) { + return; // Already loaded to correct return registers + } + } } RegOperand *regOpnd = nullptr; PregIdx pregIdx = stmt.GetRegIdx(); @@ -2133,7 +2139,7 @@ MIRType *AArch64CGFunc::LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector(static_cast(src)->GetRegisterNumber()); @@ -2143,9 +2149,9 @@ bool AArch64CGFunc::LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src) { /* This blkassignoff is for struct return? */ uint32 loadSize; uint32 numRegs = 0; - if (bNode.GetNext()->GetOpCode() == OP_return) { - MIRStructType *ty = static_cast( - GlobalTables::GetTypeTable().GetTypeFromTyIdx(func->GetFuncRetStructTyIdx())); + if (static_cast(bNode).GetNext()->GetOpCode() == OP_return) { + MIRStructType *ty = static_cast(func->GetReturnType()); + uint32 tySize = GetBecommon().GetTypeSize(ty->GetTypeIndex()); uint32 fpregs = FloatParamRegRequired(ty, size); if (fpregs > 0) { /* pure floating point in agg */ @@ -2164,7 +2170,7 @@ bool AArch64CGFunc::LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src) { numRegs = 2; pTy = PTY_i64; size = k4ByteSize; - switch (bNode.blockSize) { + switch (tySize) { case 1: pTy = PTY_i8; break; @@ -2182,7 +2188,7 @@ bool AArch64CGFunc::LmbcSmallAggForRet(BlkassignoffNode &bNode, Operand *src) { MemOperand &mem = CreateMemOpnd(regno, 0, size * kBitsPerByte); RegOperand *res = &GetOrCreatePhysicalRegisterOperand(R0, loadSize, kRegTyInt); SelectCopy(*res, pTy, mem, pTy); - if (bNode.blockSize > static_cast(k8ByteSize)) { + if (tySize > static_cast(k8ByteSize)) { MemOperand &newMem = CreateMemOpnd(regno, k8ByteSize, size * kBitsPerByte); res = &GetOrCreatePhysicalRegisterOperand(R1, loadSize, kRegTyInt); SelectCopy(*res, pTy, newMem, pTy); @@ -3103,9 +3109,20 @@ Operand *AArch64CGFunc::SelectIreadoff(const BaseNode &parent, IreadoffNode &ire auto *baseAddr = ireadoff.Opnd(0); auto *result = &CreateRegisterOperandOfType(primType); auto *addrOpnd = HandleExpr(ireadoff, *baseAddr); - auto &memOpnd = CreateMemOpnd(LoadIntoRegister(*addrOpnd, PTY_a64), offset, bitSize); - auto mop = PickLdInsn(bitSize, primType); - GetCurBB()->AppendInsn(GetCG()->BuildInstruction(mop, *result, memOpnd)); + if (primType == PTY_agg && parent.GetOpCode() == OP_regassign) { + auto &memOpnd = CreateMemOpnd(LoadIntoRegister(*addrOpnd, PTY_a64), offset, bitSize); + auto mop = PickLdInsn(64, PTY_a64); + GetCurBB()->AppendInsn(GetCG()->BuildInstruction(mop, *result, memOpnd)); + auto ®AssignNode = static_cast(parent); + PregIdx pIdx = regAssignNode.GetRegIdx(); + CHECK_FATAL(IsSpecialPseudoRegister(pIdx), "SelectIreadfpoff of agg"); + LmbcSmallAggForRet(const_cast(parent), addrOpnd); + // result not used + } else { + auto &memOpnd = CreateMemOpnd(LoadIntoRegister(*addrOpnd, PTY_a64), offset, bitSize); + auto mop = PickLdInsn(bitSize, primType); + GetCurBB()->AppendInsn(GetCG()->BuildInstruction(mop, *result, memOpnd)); + } return result; } @@ -3158,13 +3175,11 @@ Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode int32 offset = ireadoff.GetOffset(); PrimType primType = ireadoff.GetPrimType(); uint32 bytelen = GetPrimTypeSize(primType); -#if 1 - uint32 bitlen = bytelen * kBitsPerByte; -#endif RegType regty = GetRegTyFromPrimTy(primType); RegOperand *result = nullptr; if (offset >= 0) { -#if 1 +#if OLD_LMBC // TBD + uint32 bitlen = bytelen * kBitsPerByte; LmbcFormalParamInfo *info = GetLmbcFormalParamInfo(offset); if (info->GetPrimType() == PTY_agg) { if (info->IsOnStack()) { @@ -3187,8 +3202,9 @@ Operand *AArch64CGFunc::SelectIreadfpoff(const BaseNode &parent, IreadFPoffNode result = &GetOrCreatePhysicalRegisterOperand(static_cast(info->GetRegNO()), bitlen, regty); } } -#endif +#else CHECK_FATAL(0, "Invalid ireadfpoff offset"); +#endif } else { if (primType == PTY_agg) { #if OLD_LMBC // TBD diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index 19e24b2a78..ed5342b1a4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -17,8 +17,6 @@ #include "becommon.h" #include "mir_nodes.h" -#define OLD_LMBC 1 - namespace maplebe { using namespace maple; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index b1e0ad5b6d..4dac987720 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -16,8 +16,6 @@ #include "cg_option.h" #include "cgfunc.h" -#define OLD_LMBC 1 - namespace maplebe { using namespace maple; @@ -1261,15 +1259,14 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; -#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { +#if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); } else { offset = static_cast((memLayout->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - memLayout->SizeOfArgsToStackPass()); /* for FP/LR */ } -#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignmentInt; @@ -1797,8 +1794,8 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; -#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { +#if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); } else { @@ -1806,7 +1803,6 @@ void AArch64GenProEpilog::GeneratePopRegs() { (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - /* for FP/LR */ memLayout->SizeOfArgsToStackPass()); } -#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignmentInt; -- Gitee From 6e525756f2cee14cebbf0ac477e6de843c12eac0 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 27 Jun 2022 18:36:42 -0700 Subject: [PATCH 135/179] For actual parameters corresponding to varargs, made lmbc lower struct parameters differently so as not to lose their type info --- src/mapleall/maple_me/src/lmbc_lower.cpp | 47 +++++++++++++++++++ .../maple_me/src/me_phase_manager.cpp | 3 ++ 2 files changed, 50 insertions(+) diff --git a/src/mapleall/maple_me/src/lmbc_lower.cpp b/src/mapleall/maple_me/src/lmbc_lower.cpp index 8cb339f657..c5913b036e 100644 --- a/src/mapleall/maple_me/src/lmbc_lower.cpp +++ b/src/mapleall/maple_me/src/lmbc_lower.cpp @@ -411,6 +411,53 @@ BlockNode *LMBCLowerer::LowerBlock(BlockNode *block) { } break; } + case OP_call: + case OP_icallproto: { + for (size_t i = 0; i < stmt->NumOpnds(); ++i) { + if (stmt->Opnd(i)->GetPrimType() != PTY_agg) { + stmt->SetOpnd(LowerExpr(stmt->Opnd(i)), i); + } else { + bool paramInPrototype = false; + MIRFuncType *funcType = nullptr; + if (stmt->GetOpCode() == OP_icallproto) { + IcallNode *icallproto = static_cast(stmt); + funcType = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(icallproto->GetRetTyIdx())); + paramInPrototype = (i-1) < funcType->GetParamTypeList().size(); + } else { + CallNode *callNode = static_cast(stmt); + MIRFunction *calleeFunc = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(callNode->GetPUIdx()); + funcType = calleeFunc->GetMIRFuncType(); + paramInPrototype = i < funcType->GetParamTypeList().size(); + } + if (paramInPrototype) { + stmt->SetOpnd(LowerExpr(stmt->Opnd(i)), i); + } else { // lower to iread so the type can be provided + if (stmt->Opnd(i)->GetOpCode() == OP_iread) { + IreadNode *iread = static_cast(stmt->Opnd(i)); + iread->SetOpnd(LowerExpr(iread->Opnd(0)), 0); + } else if (stmt->Opnd(i)->GetOpCode() == OP_dread) { + AddrofNode *addrof = static_cast(stmt->Opnd(i)); + FieldID fid = addrof->GetFieldID(); + addrof->SetOpCode(OP_addrof); + addrof->SetPrimType(GetExactPtrPrimType()); + addrof->SetFieldID(0); + MIRSymbol *symbol = func->GetLocalOrGlobalSymbol(addrof->GetStIdx()); + MIRPtrType ptrType(symbol->GetTyIdx(), GetExactPtrPrimType()); + ptrType.SetTypeAttrs(symbol->GetAttrs()); + TyIdx addrTyIdx = GlobalTables::GetTypeTable().GetOrCreateMIRType(&ptrType); + if (addrTyIdx == becommon->GetSizeOfTypeSizeTable()) { + MIRType *newType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(addrTyIdx); + becommon->UpdateTypeTable(*newType); + } + IreadNode *newIread = mirModule->CurFuncCodeMemPool()->New(OP_iread, PTY_agg, addrTyIdx, fid, LowerExpr(addrof)); + stmt->SetOpnd(newIread, i); + } + } + } + } + newblk->AddStatement(stmt); + break; + } default: { for (size_t i = 0; i < stmt->NumOpnds(); ++i) { stmt->SetOpnd(LowerExpr(stmt->Opnd(i)), i); diff --git a/src/mapleall/maple_me/src/me_phase_manager.cpp b/src/mapleall/maple_me/src/me_phase_manager.cpp index a0b5419a8e..92fb5a9f53 100644 --- a/src/mapleall/maple_me/src/me_phase_manager.cpp +++ b/src/mapleall/maple_me/src/me_phase_manager.cpp @@ -149,6 +149,9 @@ bool MeFuncPM::PhaseRun(maple::MIRModule &m) { if (func->GetBody() == nullptr) { continue; } + if (!IsQuiet()) { + LogInfo::MapleLogger() << ">>>> Generating LMBC for Function < " << func->GetName() << " > [" << i - 1 << "]\n"; + } m.SetCurFunction(func); cgLower.LowerFunc(*func); MemPool *layoutMp = memPoolCtrler.NewMemPool("layout mempool", true); -- Gitee From f1c0e461b8081091bca9a4c58b1bed26027d509a Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 27 Jun 2022 21:09:51 -0700 Subject: [PATCH 136/179] Deleted LmbcSelectParmList() which no longer serves any purpose --- .../include/cg/aarch64/aarch64_cgfunc.h | 1 - .../src/cg/aarch64/aarch64_cgfunc.cpp | 53 ------------------- .../maple_me/src/me_phase_manager.cpp | 2 +- 3 files changed, 1 insertion(+), 55 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index b4aee3214c..92c0db6ece 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -129,7 +129,6 @@ class AArch64CGFunc : public CGFunc { MemOperand *FixLargeMemOpnd(MOperator mOp, MemOperand &memOpnd, uint32 dSize, uint32 opndIdx); uint32 LmbcFindTotalStkUsed(std::vector* paramList); uint32 LmbcTotalRegsUsed(); - void LmbcSelectParmList(ListOperand *srcOpnds, bool isArgReturn); bool LmbcSmallAggForRet(BaseNode &bNode, Operand *src); bool LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src, std::vector **parmList); void SelectAggDassign(DassignNode &stmt) override; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 290035704b..fa133d802f 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -8571,56 +8571,6 @@ void AArch64CGFunc::IntrinsifyStringIndexOf(ListOperand &srcOpnds, const MIRSymb SetCurBB(*jointBB); } -/* Lmbc calls have no argument, they are all explicit iassignspoff or - blkassign. Info collected and to be emitted here */ -void AArch64CGFunc::LmbcSelectParmList(ListOperand *srcOpnds, bool isArgReturn) { - if (GetLmbcArgInfo() == nullptr) { - return; /* no arg */ - } - CHECK_FATAL(GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc, "To be called for Lmbc model only"); - MapleVector &args = GetLmbcCallArgs(); - MapleVector &types = GetLmbcCallArgTypes(); - MapleVector &offsets = GetLmbcCallArgOffsets(); - MapleVector ®s = GetLmbcCallArgNumOfRegs(); - int iCnt = 0; - int fCnt = 0; - for (size_t i = isArgReturn ? 1 : 0; i < args.size(); i++) { - RegType ty = args[i]->GetRegisterType(); - PrimType pTy = types[i]; - AArch64reg reg; - if (args[i]->IsOfIntClass() && (iCnt + regs[i]) <= static_cast(k8ByteSize)) { - reg = static_cast(R0 + iCnt++); - RegOperand *res = &GetOrCreatePhysicalRegisterOperand( - reg, GetPrimTypeSize(pTy) * kBitsPerByte, ty); - SelectCopy(*res, pTy, *args[i], pTy); - srcOpnds->PushOpnd(*res); - } else if (!args[i]->IsOfIntClass() && (fCnt + regs[i]) <= static_cast(k8ByteSize)) { - reg = static_cast(V0 + fCnt++); - RegOperand *res = &GetOrCreatePhysicalRegisterOperand( - reg, GetPrimTypeSize(pTy) * kBitsPerByte, ty); - SelectCopy(*res, pTy, *args[i], pTy); - srcOpnds->PushOpnd(*res); - } else { - uint32 pSize = GetPrimTypeSize(pTy); - Operand &memOpd = CreateMemOpnd(RSP, offsets[i], pSize); - GetCurBB()->AppendInsn(GetCG()->BuildInstruction(PickStInsn(pSize * kBitsPerByte, pTy), - *args[i], memOpd)); - } - } - /* Load x8 if 1st arg is for agg return */ - if (isArgReturn) { - AArch64reg reg = static_cast(R8); - RegOperand *res = &GetOrCreatePhysicalRegisterOperand(reg, - GetPrimTypeSize(PTY_a64) * kBitsPerByte, - kRegTyInt); - SelectCopy(*res, PTY_a64, *args[0], PTY_a64); - srcOpnds->PushOpnd(*res); - } - ResetLmbcArgInfo(); /* reset */ - ResetLmbcArgsInRegs(); - ResetLmbcTotalArgs(); -} - void AArch64CGFunc::SelectCall(CallNode &callNode) { MIRFunction *fn = GlobalTables::GetFunctionTable().GetFunctionFromPuidx(callNode.GetPUIdx()); MIRSymbol *fsym = GetFunction().GetLocalOrGlobalSymbol(fn->GetStIdx(), false); @@ -8634,17 +8584,14 @@ void AArch64CGFunc::SelectCall(CallNode &callNode) { ListOperand *srcOpnds = CreateListOpnd(*GetFuncScopeAllocator()); if (GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { SetLmbcCallReturnType(nullptr); - bool largeStructRet = false; if (fn->IsFirstArgReturn()) { MIRPtrType *ptrTy = static_cast(GlobalTables::GetTypeTable().GetTypeFromTyIdx(fn->GetFormalDefVec()[0].formalTyIdx)); MIRType *sTy = GlobalTables::GetTypeTable().GetTypeFromTyIdx(ptrTy->GetPointedTyIdx()); - largeStructRet = sTy->GetSize() > k16ByteSize; SetLmbcCallReturnType(sTy); } else { MIRType *ty = fn->GetReturnType(); SetLmbcCallReturnType(ty); } - LmbcSelectParmList(srcOpnds, largeStructRet); } bool callNative = false; if ((fsym->GetName() == "MCC_CallFastNative") || (fsym->GetName() == "MCC_CallFastNativeExt") || diff --git a/src/mapleall/maple_me/src/me_phase_manager.cpp b/src/mapleall/maple_me/src/me_phase_manager.cpp index 92fb5a9f53..a9b5b3e636 100644 --- a/src/mapleall/maple_me/src/me_phase_manager.cpp +++ b/src/mapleall/maple_me/src/me_phase_manager.cpp @@ -150,7 +150,7 @@ bool MeFuncPM::PhaseRun(maple::MIRModule &m) { continue; } if (!IsQuiet()) { - LogInfo::MapleLogger() << ">>>> Generating LMBC for Function < " << func->GetName() << " > [" << i - 1 << "]\n"; + LogInfo::MapleLogger() << ">>>> Generating LMBC for Function < " << func->GetName() << " >\n"; } m.SetCurFunction(func); cgLower.LowerFunc(*func); -- Gitee From d7ba128d9dc5575a34c0d44a310b3d52da87fd1d Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Tue, 28 Jun 2022 09:20:43 -0700 Subject: [PATCH 137/179] Fixed coredump at end of coremark. --- src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index fa133d802f..a9d44b3b1c 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -9544,7 +9544,7 @@ int32 AArch64CGFunc::GetBaseOffset(const SymbolAlloc &sa) { return baseOffset + sizeofFplr; } else if (sgKind == kMsSpillReg) { if (GetCG()->IsLmbc()) { - return symAlloc->GetOffset() + memLayout->SizeOfArgsToStackPass(); + return symAlloc->GetOffset() + memLayout->SizeOfArgsToStackPass() + sizeofFplr; } int32 baseOffset = symAlloc->GetOffset() + memLayout->SizeOfArgsRegisterPassed() + memLayout->GetSizeOfLocals() + memLayout->GetSizeOfRefLocals(); -- Gitee From bcacf416edd8f62ada4504c3bae5dc610af65440 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Tue, 28 Jun 2022 14:08:17 -0700 Subject: [PATCH 138/179] Further changes for GetBaseOffset(). --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 20 +++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index a9d44b3b1c..30b6d3b67f 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -9534,20 +9534,32 @@ int32 AArch64CGFunc::GetBaseOffset(const SymbolAlloc &sa) { int32 offset = static_cast(symAlloc->GetOffset()); return offset; } else if (sgKind == kMsArgsRegPassed) { - int32 baseOffset = memLayout->GetSizeOfLocals() + symAlloc->GetOffset() + memLayout->GetSizeOfRefLocals(); + int32 baseOffset; + if (GetCG()->IsLmbc()) { + baseOffset = symAlloc->GetOffset() + memLayout->GetSizeOfRefLocals(); + } else { + baseOffset = memLayout->GetSizeOfLocals() + symAlloc->GetOffset() + + memLayout->GetSizeOfRefLocals(); + } return baseOffset + sizeofFplr; } else if (sgKind == kMsRefLocals) { int32 baseOffset = symAlloc->GetOffset() + memLayout->GetSizeOfLocals(); return baseOffset + sizeofFplr; } else if (sgKind == kMsLocals) { + if (GetCG()->IsLmbc()) { + CHECK_FATAL(false, "invalid lmbc's locals"); + } int32 baseOffset = symAlloc->GetOffset(); return baseOffset + sizeofFplr; } else if (sgKind == kMsSpillReg) { + int32 baseOffset; if (GetCG()->IsLmbc()) { - return symAlloc->GetOffset() + memLayout->SizeOfArgsToStackPass() + sizeofFplr; + baseOffset = symAlloc->GetOffset() + memLayout->SizeOfArgsRegisterPassed() + + memLayout->GetSizeOfRefLocals(); + } else { + baseOffset = symAlloc->GetOffset() + memLayout->SizeOfArgsRegisterPassed() + + memLayout->GetSizeOfLocals() + memLayout->GetSizeOfRefLocals(); } - int32 baseOffset = symAlloc->GetOffset() + memLayout->SizeOfArgsRegisterPassed() + memLayout->GetSizeOfLocals() + - memLayout->GetSizeOfRefLocals(); return baseOffset + sizeofFplr; } else if (sgKind == kMsArgsToStkPass) { /* this is for callers */ return static_cast(symAlloc->GetOffset()); -- Gitee From 87e67d71ebac4f73d2c81c0fdc10553739793e47 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Tue, 28 Jun 2022 16:17:38 -0700 Subject: [PATCH 139/179] Fix for small agg return. --- src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 30b6d3b67f..ba00caa8ac 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1487,12 +1487,14 @@ void AArch64CGFunc::SelectRegassign(RegassignNode &stmt, Operand &opnd0) { prev->SetMOP(MOP_xldrsw); } } +#if 0 if (lhsSize == PTY_agg && (stmt.Opnd(0)->GetOpCode() == OP_ireadoff || stmt.Opnd(0)->GetOpCode() == OP_ireadfpoff)) { PregIdx pregIdx = stmt.GetRegIdx(); if ((-pregIdx) == kSregRetval0) { return; // Already loaded to correct return registers } } +#endif } RegOperand *regOpnd = nullptr; PregIdx pregIdx = stmt.GetRegIdx(); -- Gitee From 865eedfdf19880f383a10900a1ce2bd9b9ef0021 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Thu, 30 Jun 2022 11:24:14 -0700 Subject: [PATCH 140/179] Some fixes for lmbc vararg memlayout --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 2 ++ .../src/cg/aarch64/aarch64_memlayout.cpp | 4 ---- .../src/cg/aarch64/aarch64_proepilog.cpp | 19 +++++++++++-------- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index ba00caa8ac..c8383def08 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -10233,9 +10233,11 @@ void AArch64CGFunc::SelectCVaStart(const IntrinsiccallNode &intrnNode) { inReg++; } } +#if OLD_LMBC // TBD if (GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { stkSize += (inReg * k8ByteSize); } +#endif if (CGOptions::IsArm64ilp32()) { stkSize = static_cast(RoundUp(stkSize, k8ByteSize)); } else { diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index ed5342b1a4..d9fa8fb2f0 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -541,18 +541,14 @@ uint64 AArch64MemLayout::StackFrameSize() const { uint64 total = segArgsRegPassed.GetSize() + static_cast(cgFunc)->SizeOfCalleeSaved() + GetSizeOfRefLocals() + locals().GetSize() + GetSizeOfSpillReg(); -#if OLD_LMBC // TBD if (cgFunc->GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { -#endif if (GetSizeOfGRSaveArea() > 0) { total += RoundUp(GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); } if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } -#if OLD_LMBC // TBD } -#endif /* * if the function does not have VLA nor alloca, diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 4dac987720..8929c47b5c 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -344,7 +344,9 @@ void AArch64GenProEpilog::GenStackGuard(BB &bb) { cgFunc.GetCurBB()->AppendInsn(insn); uint64 vArea = 0; - if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (cgFunc.GetMirModule().IsCModule() && + cgFunc.GetFunction().GetAttr(FUNCATTR_varargs) && + cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { AArch64MemLayout *ml = static_cast(cgFunc.GetMemlayout()); if (ml->GetSizeOfGRSaveArea() > 0) { vArea += RoundUp(ml->GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); @@ -401,7 +403,9 @@ BB &AArch64GenProEpilog::GenStackGuardCheckInsn(BB &bb) { cgFunc.GetCurBB()->AppendInsn(insn); uint64 vArea = 0; - if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (cgFunc.GetMirModule().IsCModule() && + cgFunc.GetFunction().GetAttr(FUNCATTR_varargs) && + cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { AArch64MemLayout *ml = static_cast(cgFunc.GetMemlayout()); if (ml->GetSizeOfGRSaveArea() > 0) { vArea += RoundUp(ml->GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); @@ -1219,9 +1223,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { Operand &spOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); -#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; -#endif if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; if (isLmbc) { @@ -1272,7 +1274,9 @@ void AArch64GenProEpilog::GeneratePushRegs() { offset -= kAarch64StackPtrAlignmentInt; } - if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (cgFunc.GetMirModule().IsCModule() && + cgFunc.GetFunction().GetAttr(FUNCATTR_varargs) && + cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { /* GR/VR save areas are above the callee save area */ AArch64MemLayout *ml = static_cast(cgFunc.GetMemlayout()); auto saveareasize = static_cast(RoundUp(ml->GetSizeOfGRSaveArea(), kSizeOfPtr * k2BitSize) + @@ -1499,9 +1503,7 @@ void AArch64GenProEpilog::GenerateProlog(BB &bb) { } if (useFP) { Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); -#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; -#endif int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; @@ -1808,7 +1810,8 @@ void AArch64GenProEpilog::GeneratePopRegs() { offset -= kAarch64StackPtrAlignmentInt; } - if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) { + if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs) && + cgFunc.GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { /* GR/VR save areas are above the callee save area */ AArch64MemLayout *ml = static_cast(cgFunc.GetMemlayout()); auto saveareasize = static_cast(RoundUp(ml->GetSizeOfGRSaveArea(), kSizeOfPtr * k2BitSize) + -- Gitee From 4b6663212f6e2a3235e08fafed31b9c581a1e499 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Thu, 30 Jun 2022 23:04:08 -0700 Subject: [PATCH 141/179] Fixed some errors from rebasing to master --- src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h | 2 +- src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp | 2 +- src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index 92c0db6ece..56018fcd18 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -102,7 +102,7 @@ class AArch64CGFunc : public CGFunc { return kRFLAG; } - MIRType *LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList) const; + MIRType *LmbcGetAggTyFromCallSite(StmtNode *stmt, std::vector **parmList); RegOperand &GetOrCreateResOperand(const BaseNode &parent, PrimType primType); MIRStructType *GetLmbcStructArgType(BaseNode &stmt, int32 argNo); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index c8383def08..5c20002eda 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -2211,7 +2211,7 @@ bool AArch64CGFunc::LmbcSmallAggForRet(BaseNode &bNode, Operand *src) { } /* return true if blkassignoff for return, false otherwise */ -bool AArch64CGFunc::LmbcSmallAggForCall(BlkassignoffNode &bNode, const Operand *src, std::vector **parmList) { +bool AArch64CGFunc::LmbcSmallAggForCall(BlkassignoffNode &bNode, Operand *src, std::vector **parmList) { AArch64reg regno = static_cast(static_cast(src)->GetRegisterNumber()); if (IsBlkassignForPush(bNode)) { PrimType pTy = PTY_i64; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp index 6b8bd947eb..1d5b125c94 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp @@ -1016,7 +1016,7 @@ bool AArch64Ebo::CombineMultiplyNeg(Insn *insn, OpndInfo *opndInfo, bool is64bit return false; } -bool AArch64Ebo::CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp) const { +bool AArch64Ebo::CombineLsrAnd(Insn &insn, const OpndInfo &opndInfo, bool is64bits, bool isFp) { if (opndInfo.insn == nullptr) { return false; } -- Gitee From c7c2846e62752e16c2015e2c173f5d50fe7c13b3 Mon Sep 17 00:00:00 2001 From: William Chen Date: Wed, 8 Jun 2022 16:21:12 -0700 Subject: [PATCH 142/179] Changes from mplcglmbc10 --- src/mapleall/maple_ir/include/bin_mpl_export.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 918c8e04eb..9cada84eb4 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,6 +181,7 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; + MIRFunction *curFunc = nullptr; size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; -- Gitee From 71e614c6099378987be5155c07b0518349d14875 Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:16:12 -0700 Subject: [PATCH 143/179] Turn on globalopt for lmbc, but leave SSA opt off --- src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def | 6 ++---- src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp | 4 +++- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index e5627ecba3..856c48e6bd 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -49,10 +49,8 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); - } + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 4a2f257321..6b5d902cb4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,7 +412,9 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - CHECK_FATAL(false, "check case in ssa"); + if (cgFunc.GetCG()->IsLmbc() == false) { + CHECK_FATAL(false, "check case in ssa"); + } } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From 8cb2d64658f980cedac6254f526229a962656b82 Mon Sep 17 00:00:00 2001 From: William Chen Date: Mon, 13 Jun 2022 14:06:17 -0700 Subject: [PATCH 144/179] Do not optimize for ssa for physical regs. --- .../include/cg/aarch64/aarch64_phases.def | 22 +++++++++---------- .../src/cg/aarch64/aarch64_global.cpp | 4 +--- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 856c48e6bd..f11ca1435e 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,18 +17,16 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); - } + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 6b5d902cb4..4a2f257321 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,9 +412,7 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - if (cgFunc.GetCG()->IsLmbc() == false) { - CHECK_FATAL(false, "check case in ssa"); - } + CHECK_FATAL(false, "check case in ssa"); } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From 3251f8862b0643907dc81c10c1158b69fccacb4b Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Mon, 20 Jun 2022 15:49:32 -0700 Subject: [PATCH 145/179] Updating to "new" lmbc --- .../maple_be/src/cg/aarch64/aarch64_memlayout.cpp | 4 ++++ .../maple_be/src/cg/aarch64/aarch64_proepilog.cpp | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index d9fa8fb2f0..ed5342b1a4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -541,14 +541,18 @@ uint64 AArch64MemLayout::StackFrameSize() const { uint64 total = segArgsRegPassed.GetSize() + static_cast(cgFunc)->SizeOfCalleeSaved() + GetSizeOfRefLocals() + locals().GetSize() + GetSizeOfSpillReg(); +#if OLD_LMBC // TBD if (cgFunc->GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif if (GetSizeOfGRSaveArea() > 0) { total += RoundUp(GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); } if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } +#if OLD_LMBC // TBD } +#endif /* * if the function does not have VLA nor alloca, diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 8929c47b5c..4df21eb839 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -1223,7 +1223,9 @@ void AArch64GenProEpilog::GeneratePushRegs() { Operand &spOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); +#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; +#endif if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; if (isLmbc) { @@ -1261,6 +1263,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { #if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - @@ -1269,6 +1272,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { offset = static_cast((memLayout->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - memLayout->SizeOfArgsToStackPass()); /* for FP/LR */ } +#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignmentInt; @@ -1503,7 +1507,9 @@ void AArch64GenProEpilog::GenerateProlog(BB &bb) { } if (useFP) { Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); +#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; +#endif int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; @@ -1796,6 +1802,7 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { #if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - @@ -1805,6 +1812,7 @@ void AArch64GenProEpilog::GeneratePopRegs() { (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - /* for FP/LR */ memLayout->SizeOfArgsToStackPass()); } +#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignmentInt; -- Gitee From 6bc1607fc07882e46984aa524e2155862ed04a72 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 20 Jun 2022 21:57:07 -0700 Subject: [PATCH 146/179] Turned some optimizations back off under lmbc and re-enabled some old code The OLD_LMBC define-disabled code caused coremark to fail execution. I have to put #define OLD_LMBC on aarch64_memlayout.cpp and aarch64_proepilog.cpp so coremark can work again. --- .../include/cg/aarch64/aarch64_phases.def | 28 +++++++++++-------- .../src/cg/aarch64/aarch64_memlayout.cpp | 2 ++ .../src/cg/aarch64/aarch64_proepilog.cpp | 2 ++ 3 files changed, 20 insertions(+), 12 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index f11ca1435e..e5627ecba3 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,16 +17,18 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + } /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); @@ -47,8 +49,10 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + } ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index ed5342b1a4..19e24b2a78 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -17,6 +17,8 @@ #include "becommon.h" #include "mir_nodes.h" +#define OLD_LMBC 1 + namespace maplebe { using namespace maple; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 4df21eb839..e02f1883da 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -16,6 +16,8 @@ #include "cg_option.h" #include "cgfunc.h" +#define OLD_LMBC 1 + namespace maplebe { using namespace maple; -- Gitee From 225bf939e7384d4b4860c82ae29a920909e94b7a Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Sat, 25 Jun 2022 12:21:10 -0700 Subject: [PATCH 147/179] More edits to rebase to master branch --- src/mapleall/maple_ir/include/bin_mpl_export.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 9cada84eb4..918c8e04eb 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,7 +181,6 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; - MIRFunction *curFunc = nullptr; size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; -- Gitee From 94ef1bb0944371d2ea0431865494ab804024c2ec Mon Sep 17 00:00:00 2001 From: William Chen Date: Wed, 8 Jun 2022 16:21:12 -0700 Subject: [PATCH 148/179] Changes from mplcglmbc10 --- src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp | 1 - src/mapleall/maple_ir/include/bin_mpl_export.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index 19e24b2a78..abe93dbaff 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -552,7 +552,6 @@ uint64 AArch64MemLayout::StackFrameSize() const { if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } -#if OLD_LMBC // TBD } #endif diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 918c8e04eb..9cada84eb4 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,6 +181,7 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; + MIRFunction *curFunc = nullptr; size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; -- Gitee From 9b47b9f35de7e20518af87d74ec0d24eff6017a6 Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:16:12 -0700 Subject: [PATCH 149/179] Turn on globalopt for lmbc, but leave SSA opt off --- src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def | 6 ++---- src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp | 4 +++- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index e5627ecba3..856c48e6bd 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -49,10 +49,8 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); - } + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 4a2f257321..6b5d902cb4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,7 +412,9 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - CHECK_FATAL(false, "check case in ssa"); + if (cgFunc.GetCG()->IsLmbc() == false) { + CHECK_FATAL(false, "check case in ssa"); + } } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From 15e4a620865033a00ec88a30e33fa18761a7075b Mon Sep 17 00:00:00 2001 From: William Chen Date: Mon, 13 Jun 2022 14:06:17 -0700 Subject: [PATCH 150/179] Do not optimize for ssa for physical regs. --- .../include/cg/aarch64/aarch64_phases.def | 22 +++++++++---------- .../src/cg/aarch64/aarch64_global.cpp | 4 +--- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 856c48e6bd..f11ca1435e 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,18 +17,16 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); - } + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 6b5d902cb4..4a2f257321 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,9 +412,7 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - if (cgFunc.GetCG()->IsLmbc() == false) { - CHECK_FATAL(false, "check case in ssa"); - } + CHECK_FATAL(false, "check case in ssa"); } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From 1fb974df85dd35f24434d05a40c1c8e481c35473 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Mon, 20 Jun 2022 15:49:32 -0700 Subject: [PATCH 151/179] Updating to "new" lmbc --- src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index abe93dbaff..19e24b2a78 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -552,6 +552,7 @@ uint64 AArch64MemLayout::StackFrameSize() const { if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } +#if OLD_LMBC // TBD } #endif -- Gitee From 8d0dd6b196ee2448d1bc20d00a483e9e70adcfdd Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Fri, 17 Jun 2022 21:32:32 -0700 Subject: [PATCH 152/179] Fixed bug in importing typeAttrs field of MIRStructType Also, handle the export and import of MIRAddrofConst of local symbols properly. --- src/mapleall/maple_ir/include/bin_mpl_export.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 9cada84eb4..365a73b6a8 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,7 +181,9 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; + public: MIRFunction *curFunc = nullptr; + private: size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; -- Gitee From e2a9ab36263e7430dfdee871a6946058d9fed0b0 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 20 Jun 2022 21:57:07 -0700 Subject: [PATCH 153/179] Turned some optimizations back off under lmbc and re-enabled some old code The OLD_LMBC define-disabled code caused coremark to fail execution. I have to put #define OLD_LMBC on aarch64_memlayout.cpp and aarch64_proepilog.cpp so coremark can work again. --- .../include/cg/aarch64/aarch64_phases.def | 28 +++++++++++-------- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index f11ca1435e..e5627ecba3 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,16 +17,18 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + } /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); @@ -47,8 +49,10 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + } ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); -- Gitee From f88767d0428c9abf81bf062b0345a23de2e219b3 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Sat, 25 Jun 2022 14:55:37 -0700 Subject: [PATCH 154/179] Fixed a rebase bug --- src/mapleall/maple_ir/include/bin_mpl_export.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 365a73b6a8..17a00a9b30 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,8 +181,6 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; - public: - MIRFunction *curFunc = nullptr; private: size_t bufI = 0; std::vector buf; -- Gitee From e5c5e63882eb039a32fd079e385534b9fba67507 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Mon, 27 Jun 2022 14:41:54 -0700 Subject: [PATCH 155/179] Update for agg ret, caller/callee save offset. --- src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp | 2 -- src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp | 6 ------ 2 files changed, 8 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index 19e24b2a78..ed5342b1a4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -17,8 +17,6 @@ #include "becommon.h" #include "mir_nodes.h" -#define OLD_LMBC 1 - namespace maplebe { using namespace maple; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index e02f1883da..c06250a0ce 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -16,8 +16,6 @@ #include "cg_option.h" #include "cgfunc.h" -#define OLD_LMBC 1 - namespace maplebe { using namespace maple; @@ -1265,7 +1263,6 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; -#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { #if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - @@ -1274,7 +1271,6 @@ void AArch64GenProEpilog::GeneratePushRegs() { offset = static_cast((memLayout->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - memLayout->SizeOfArgsToStackPass()); /* for FP/LR */ } -#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignmentInt; @@ -1804,7 +1800,6 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; -#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { #if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - @@ -1814,7 +1809,6 @@ void AArch64GenProEpilog::GeneratePopRegs() { (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - /* for FP/LR */ memLayout->SizeOfArgsToStackPass()); } -#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignmentInt; -- Gitee From b9bc2d8cc01830a5719f587a7aeab496d832442b Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Thu, 30 Jun 2022 11:24:14 -0700 Subject: [PATCH 156/179] Some fixes for lmbc vararg memlayout --- src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp | 4 ---- src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp | 4 ---- 2 files changed, 8 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index ed5342b1a4..d9fa8fb2f0 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -541,18 +541,14 @@ uint64 AArch64MemLayout::StackFrameSize() const { uint64 total = segArgsRegPassed.GetSize() + static_cast(cgFunc)->SizeOfCalleeSaved() + GetSizeOfRefLocals() + locals().GetSize() + GetSizeOfSpillReg(); -#if OLD_LMBC // TBD if (cgFunc->GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { -#endif if (GetSizeOfGRSaveArea() > 0) { total += RoundUp(GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); } if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } -#if OLD_LMBC // TBD } -#endif /* * if the function does not have VLA nor alloca, diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index c06250a0ce..8929c47b5c 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -1223,9 +1223,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { Operand &spOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); -#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; -#endif if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; if (isLmbc) { @@ -1505,9 +1503,7 @@ void AArch64GenProEpilog::GenerateProlog(BB &bb) { } if (useFP) { Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); -#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; -#endif int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; -- Gitee From f7e3149ee8c721bc0c504ae787d3c5cb09e51dfc Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:16:12 -0700 Subject: [PATCH 157/179] Turn on globalopt for lmbc, but leave SSA opt off --- src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def | 6 ++---- src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp | 4 +++- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index e5627ecba3..856c48e6bd 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -49,10 +49,8 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); - } + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 4a2f257321..6b5d902cb4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,7 +412,9 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - CHECK_FATAL(false, "check case in ssa"); + if (cgFunc.GetCG()->IsLmbc() == false) { + CHECK_FATAL(false, "check case in ssa"); + } } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From 7907ee4d4307caf1390e0f3d31310b2e0836e6ce Mon Sep 17 00:00:00 2001 From: William Chen Date: Mon, 13 Jun 2022 14:06:17 -0700 Subject: [PATCH 158/179] Do not optimize for ssa for physical regs. --- .../include/cg/aarch64/aarch64_phases.def | 22 +++++++++---------- .../src/cg/aarch64/aarch64_global.cpp | 4 +--- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 856c48e6bd..f11ca1435e 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,18 +17,16 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); - } + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 6b5d902cb4..4a2f257321 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,9 +412,7 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - if (cgFunc.GetCG()->IsLmbc() == false) { - CHECK_FATAL(false, "check case in ssa"); - } + CHECK_FATAL(false, "check case in ssa"); } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From 3ca3e7df243adae88bc294c4d578d8bf749cd913 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Mon, 20 Jun 2022 15:49:32 -0700 Subject: [PATCH 159/179] Updating to "new" lmbc --- .../maple_be/src/cg/aarch64/aarch64_memlayout.cpp | 4 ++++ .../maple_be/src/cg/aarch64/aarch64_proepilog.cpp | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index d9fa8fb2f0..ed5342b1a4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -541,14 +541,18 @@ uint64 AArch64MemLayout::StackFrameSize() const { uint64 total = segArgsRegPassed.GetSize() + static_cast(cgFunc)->SizeOfCalleeSaved() + GetSizeOfRefLocals() + locals().GetSize() + GetSizeOfSpillReg(); +#if OLD_LMBC // TBD if (cgFunc->GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif if (GetSizeOfGRSaveArea() > 0) { total += RoundUp(GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); } if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } +#if OLD_LMBC // TBD } +#endif /* * if the function does not have VLA nor alloca, diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 8929c47b5c..4df21eb839 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -1223,7 +1223,9 @@ void AArch64GenProEpilog::GeneratePushRegs() { Operand &spOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); +#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; +#endif if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; if (isLmbc) { @@ -1261,6 +1263,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { #if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - @@ -1269,6 +1272,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { offset = static_cast((memLayout->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - memLayout->SizeOfArgsToStackPass()); /* for FP/LR */ } +#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignmentInt; @@ -1503,7 +1507,9 @@ void AArch64GenProEpilog::GenerateProlog(BB &bb) { } if (useFP) { Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); +#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; +#endif int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; @@ -1796,6 +1802,7 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { #if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - @@ -1805,6 +1812,7 @@ void AArch64GenProEpilog::GeneratePopRegs() { (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - /* for FP/LR */ memLayout->SizeOfArgsToStackPass()); } +#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignmentInt; -- Gitee From 3a0c248320bc4b2477231176fe113a01f95c3d35 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 20 Jun 2022 21:57:07 -0700 Subject: [PATCH 160/179] Turned some optimizations back off under lmbc and re-enabled some old code The OLD_LMBC define-disabled code caused coremark to fail execution. I have to put #define OLD_LMBC on aarch64_memlayout.cpp and aarch64_proepilog.cpp so coremark can work again. --- .../include/cg/aarch64/aarch64_phases.def | 28 +++++++++++-------- .../src/cg/aarch64/aarch64_memlayout.cpp | 2 ++ .../src/cg/aarch64/aarch64_proepilog.cpp | 2 ++ 3 files changed, 20 insertions(+), 12 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index f11ca1435e..e5627ecba3 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,16 +17,18 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + } /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); @@ -47,8 +49,10 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + } ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index ed5342b1a4..19e24b2a78 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -17,6 +17,8 @@ #include "becommon.h" #include "mir_nodes.h" +#define OLD_LMBC 1 + namespace maplebe { using namespace maple; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 4df21eb839..e02f1883da 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -16,6 +16,8 @@ #include "cg_option.h" #include "cgfunc.h" +#define OLD_LMBC 1 + namespace maplebe { using namespace maple; -- Gitee From 481c3d42798c738b90045ba61414964757d53845 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Fri, 24 Jun 2022 21:00:36 -0700 Subject: [PATCH 161/179] Handled more types of asm operands --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 5c20002eda..0774d9df70 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1292,6 +1292,30 @@ void AArch64CGFunc::SelectAsm(AsmNode &node) { } break; } + case OP_ireadoff: { + IreadoffNode *ireadoff = static_cast(node.Opnd(i)); + Operand *inOpnd = SelectIreadoff(node, *ireadoff); + listInputOpnd->PushOpnd(static_cast(*inOpnd)); + PrimType pType = ireadoff->GetPrimType(); + listInRegPrefix->stringList.push_back( + static_cast(&CreateStringOperand(GetRegPrefixFromPrimType(pType, inOpnd->GetSize(), str)))); + if (isOutputTempNode) { + rPlusOpnd.emplace_back(std::make_pair(inOpnd, pType)); + } + break; + } + case OP_add: { + BinaryNode *addNode = static_cast(node.Opnd(i)); + Operand *inOpnd = SelectAdd(*addNode, *HandleExpr(*addNode, *addNode->Opnd(0)), *HandleExpr(*addNode, *addNode->Opnd(1)), node); + listInputOpnd->PushOpnd(static_cast(*inOpnd)); + PrimType pType = addNode->GetPrimType(); + listInRegPrefix->stringList.push_back( + static_cast(&CreateStringOperand(GetRegPrefixFromPrimType(pType, inOpnd->GetSize(), str)))); + if (isOutputTempNode) { + rPlusOpnd.emplace_back(std::make_pair(inOpnd, pType)); + } + break; + } case OP_constval: { CHECK_FATAL(!isOutputTempNode, "Unexpect"); auto &constNode = static_cast(*node.Opnd(i)); -- Gitee From d3ac8da1ae333581f8c88438a922bcb3dba9ea08 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Sat, 25 Jun 2022 12:21:10 -0700 Subject: [PATCH 162/179] More edits to rebase to master branch --- src/mapleall/maple_ir/include/bin_mpl_export.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 17a00a9b30..918c8e04eb 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,7 +181,6 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; - private: size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; -- Gitee From 3046c3796315ae20d0cb9379f2c47bb68ba781d6 Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:16:12 -0700 Subject: [PATCH 163/179] Turn on globalopt for lmbc, but leave SSA opt off --- src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def | 6 ++---- src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp | 4 +++- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index e5627ecba3..856c48e6bd 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -49,10 +49,8 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); - } + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 4a2f257321..6b5d902cb4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,7 +412,9 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - CHECK_FATAL(false, "check case in ssa"); + if (cgFunc.GetCG()->IsLmbc() == false) { + CHECK_FATAL(false, "check case in ssa"); + } } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From 311e18693bbde1adb71652157079569b8b8d1e43 Mon Sep 17 00:00:00 2001 From: William Chen Date: Mon, 13 Jun 2022 14:06:17 -0700 Subject: [PATCH 164/179] Do not optimize for ssa for physical regs. --- .../include/cg/aarch64/aarch64_phases.def | 22 +++++++++---------- .../src/cg/aarch64/aarch64_global.cpp | 4 +--- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 856c48e6bd..f11ca1435e 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,18 +17,16 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); - } + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 6b5d902cb4..4a2f257321 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,9 +412,7 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - if (cgFunc.GetCG()->IsLmbc() == false) { - CHECK_FATAL(false, "check case in ssa"); - } + CHECK_FATAL(false, "check case in ssa"); } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From 462cb40b674a6ad245c56ac23c5ba3b726b3aaa3 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 20 Jun 2022 21:57:07 -0700 Subject: [PATCH 165/179] Turned some optimizations back off under lmbc and re-enabled some old code The OLD_LMBC define-disabled code caused coremark to fail execution. I have to put #define OLD_LMBC on aarch64_memlayout.cpp and aarch64_proepilog.cpp so coremark can work again. --- .../include/cg/aarch64/aarch64_phases.def | 28 +++++++++++-------- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index f11ca1435e..e5627ecba3 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,16 +17,18 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + } /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); @@ -47,8 +49,10 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + } ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); -- Gitee From 21cd3c5f54b2f055e43e1212968967d6caa674f4 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Mon, 27 Jun 2022 14:41:54 -0700 Subject: [PATCH 166/179] Update for agg ret, caller/callee save offset. --- src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp | 2 -- src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp | 6 ------ 2 files changed, 8 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index 19e24b2a78..ed5342b1a4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -17,8 +17,6 @@ #include "becommon.h" #include "mir_nodes.h" -#define OLD_LMBC 1 - namespace maplebe { using namespace maple; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index e02f1883da..c06250a0ce 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -16,8 +16,6 @@ #include "cg_option.h" #include "cgfunc.h" -#define OLD_LMBC 1 - namespace maplebe { using namespace maple; @@ -1265,7 +1263,6 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; -#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { #if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - @@ -1274,7 +1271,6 @@ void AArch64GenProEpilog::GeneratePushRegs() { offset = static_cast((memLayout->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - memLayout->SizeOfArgsToStackPass()); /* for FP/LR */ } -#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignmentInt; @@ -1804,7 +1800,6 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; -#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { #if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - @@ -1814,7 +1809,6 @@ void AArch64GenProEpilog::GeneratePopRegs() { (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - /* for FP/LR */ memLayout->SizeOfArgsToStackPass()); } -#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignmentInt; -- Gitee From 79f38b70348e49b2dac7f2c723173f450b1d2e96 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Thu, 30 Jun 2022 11:24:14 -0700 Subject: [PATCH 167/179] Some fixes for lmbc vararg memlayout --- src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp | 4 ---- src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp | 4 ---- 2 files changed, 8 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index ed5342b1a4..d9fa8fb2f0 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -541,18 +541,14 @@ uint64 AArch64MemLayout::StackFrameSize() const { uint64 total = segArgsRegPassed.GetSize() + static_cast(cgFunc)->SizeOfCalleeSaved() + GetSizeOfRefLocals() + locals().GetSize() + GetSizeOfSpillReg(); -#if OLD_LMBC // TBD if (cgFunc->GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { -#endif if (GetSizeOfGRSaveArea() > 0) { total += RoundUp(GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); } if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } -#if OLD_LMBC // TBD } -#endif /* * if the function does not have VLA nor alloca, diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index c06250a0ce..8929c47b5c 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -1223,9 +1223,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { Operand &spOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); -#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; -#endif if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; if (isLmbc) { @@ -1505,9 +1503,7 @@ void AArch64GenProEpilog::GenerateProlog(BB &bb) { } if (useFP) { Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); -#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; -#endif int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; -- Gitee From fb0e8e79439d8f2f150e4126a8b3bd4c70d38e68 Mon Sep 17 00:00:00 2001 From: William Chen Date: Wed, 8 Jun 2022 16:21:12 -0700 Subject: [PATCH 168/179] Changes from mplcglmbc10 --- src/mapleall/maple_ir/include/bin_mpl_export.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 918c8e04eb..9cada84eb4 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,6 +181,7 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; + MIRFunction *curFunc = nullptr; size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; -- Gitee From 18b066a1747dafbebc21a336c07e2468402c559b Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:16:12 -0700 Subject: [PATCH 169/179] Turn on globalopt for lmbc, but leave SSA opt off --- src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def | 6 ++---- src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp | 4 +++- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index e5627ecba3..856c48e6bd 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -49,10 +49,8 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); - } + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 4a2f257321..6b5d902cb4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,7 +412,9 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - CHECK_FATAL(false, "check case in ssa"); + if (cgFunc.GetCG()->IsLmbc() == false) { + CHECK_FATAL(false, "check case in ssa"); + } } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From 96624d22db7fec78764c1633c46938678dc47313 Mon Sep 17 00:00:00 2001 From: William Chen Date: Mon, 13 Jun 2022 14:06:17 -0700 Subject: [PATCH 170/179] Do not optimize for ssa for physical regs. --- .../include/cg/aarch64/aarch64_phases.def | 22 +++++++++---------- .../src/cg/aarch64/aarch64_global.cpp | 4 +--- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 856c48e6bd..f11ca1435e 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,18 +17,16 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); - } + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 6b5d902cb4..4a2f257321 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,9 +412,7 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - if (cgFunc.GetCG()->IsLmbc() == false) { - CHECK_FATAL(false, "check case in ssa"); - } + CHECK_FATAL(false, "check case in ssa"); } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From d259f9ae71ad89dab0506ebf3458340ae7edbd39 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Mon, 20 Jun 2022 15:49:32 -0700 Subject: [PATCH 171/179] Updating to "new" lmbc --- .../maple_be/src/cg/aarch64/aarch64_memlayout.cpp | 4 ++++ .../maple_be/src/cg/aarch64/aarch64_proepilog.cpp | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index d9fa8fb2f0..ed5342b1a4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -541,14 +541,18 @@ uint64 AArch64MemLayout::StackFrameSize() const { uint64 total = segArgsRegPassed.GetSize() + static_cast(cgFunc)->SizeOfCalleeSaved() + GetSizeOfRefLocals() + locals().GetSize() + GetSizeOfSpillReg(); +#if OLD_LMBC // TBD if (cgFunc->GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { +#endif if (GetSizeOfGRSaveArea() > 0) { total += RoundUp(GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); } if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } +#if OLD_LMBC // TBD } +#endif /* * if the function does not have VLA nor alloca, diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 8929c47b5c..4df21eb839 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -1223,7 +1223,9 @@ void AArch64GenProEpilog::GeneratePushRegs() { Operand &spOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); +#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; +#endif if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; if (isLmbc) { @@ -1261,6 +1263,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { #if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - @@ -1269,6 +1272,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { offset = static_cast((memLayout->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - memLayout->SizeOfArgsToStackPass()); /* for FP/LR */ } +#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignmentInt; @@ -1503,7 +1507,9 @@ void AArch64GenProEpilog::GenerateProlog(BB &bb) { } if (useFP) { Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); +#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; +#endif int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; @@ -1796,6 +1802,7 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; +#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { #if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - @@ -1805,6 +1812,7 @@ void AArch64GenProEpilog::GeneratePopRegs() { (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - /* for FP/LR */ memLayout->SizeOfArgsToStackPass()); } +#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignmentInt; -- Gitee From 5433316025d0fef1669995bdb65993cb6d0f9435 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 20 Jun 2022 21:57:07 -0700 Subject: [PATCH 172/179] Turned some optimizations back off under lmbc and re-enabled some old code The OLD_LMBC define-disabled code caused coremark to fail execution. I have to put #define OLD_LMBC on aarch64_memlayout.cpp and aarch64_proepilog.cpp so coremark can work again. --- .../include/cg/aarch64/aarch64_phases.def | 28 +++++++++++-------- .../src/cg/aarch64/aarch64_memlayout.cpp | 2 ++ .../src/cg/aarch64/aarch64_proepilog.cpp | 2 ++ 3 files changed, 20 insertions(+), 12 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index f11ca1435e..e5627ecba3 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,16 +17,18 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + } /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); @@ -47,8 +49,10 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + } ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index ed5342b1a4..19e24b2a78 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -17,6 +17,8 @@ #include "becommon.h" #include "mir_nodes.h" +#define OLD_LMBC 1 + namespace maplebe { using namespace maple; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 4df21eb839..e02f1883da 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -16,6 +16,8 @@ #include "cg_option.h" #include "cgfunc.h" +#define OLD_LMBC 1 + namespace maplebe { using namespace maple; -- Gitee From deb1e8f51eaf503aeb8c3db4577a1c7dc7f32245 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Sat, 25 Jun 2022 12:21:10 -0700 Subject: [PATCH 173/179] More edits to rebase to master branch --- src/mapleall/maple_ir/include/bin_mpl_export.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mapleall/maple_ir/include/bin_mpl_export.h b/src/mapleall/maple_ir/include/bin_mpl_export.h index 9cada84eb4..918c8e04eb 100644 --- a/src/mapleall/maple_ir/include/bin_mpl_export.h +++ b/src/mapleall/maple_ir/include/bin_mpl_export.h @@ -181,7 +181,6 @@ class BinaryMplExport { void ExpandFourBuffSize(); MIRModule &mod; - MIRFunction *curFunc = nullptr; size_t bufI = 0; std::vector buf; std::unordered_map gStrMark; -- Gitee From c30a54e11c918de9f1587d0e331a2e6d82a8dbc9 Mon Sep 17 00:00:00 2001 From: William Chen Date: Fri, 10 Jun 2022 17:16:12 -0700 Subject: [PATCH 174/179] Turn on globalopt for lmbc, but leave SSA opt off --- src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def | 6 ++---- src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp | 4 +++- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index e5627ecba3..856c48e6bd 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -49,10 +49,8 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); - } + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 4a2f257321..6b5d902cb4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,7 +412,9 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - CHECK_FATAL(false, "check case in ssa"); + if (cgFunc.GetCG()->IsLmbc() == false) { + CHECK_FATAL(false, "check case in ssa"); + } } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From 770b8c19d7eeb1cf890da598d2d2fe062a49d035 Mon Sep 17 00:00:00 2001 From: William Chen Date: Mon, 13 Jun 2022 14:06:17 -0700 Subject: [PATCH 175/179] Do not optimize for ssa for physical regs. --- .../include/cg/aarch64/aarch64_phases.def | 22 +++++++++---------- .../src/cg/aarch64/aarch64_global.cpp | 4 +--- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index 856c48e6bd..f11ca1435e 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,18 +17,16 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); - } + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp index 6b5d902cb4..4a2f257321 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_global.cpp @@ -412,9 +412,7 @@ void ForwardPropPattern::Optimize(Insn &insn) { void ForwardPropPattern::RemoveMopUxtwToMov(Insn &insn) { if (CGOptions::DoCGSSA()) { - if (cgFunc.GetCG()->IsLmbc() == false) { - CHECK_FATAL(false, "check case in ssa"); - } + CHECK_FATAL(false, "check case in ssa"); } auto &secondOpnd = static_cast(insn.GetOperand(kInsnSecondOpnd)); auto &destOpnd = static_cast(insn.GetOperand(kInsnFirstOpnd)); -- Gitee From bab66dbde091ae852926fe19d9947a1254582420 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 20 Jun 2022 21:57:07 -0700 Subject: [PATCH 176/179] Turned some optimizations back off under lmbc and re-enabled some old code The OLD_LMBC define-disabled code caused coremark to fail execution. I have to put #define OLD_LMBC on aarch64_memlayout.cpp and aarch64_proepilog.cpp so coremark can work again. --- .../include/cg/aarch64/aarch64_phases.def | 28 +++++++++++-------- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def index f11ca1435e..e5627ecba3 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_phases.def @@ -17,16 +17,18 @@ ADDTARGETPHASE("buildehfunc", true); ADDTARGETPHASE("handlefunction", true); ADDTARGETPHASE("moveargs", true); - /* SSA PHASES */ - ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); - ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + /* SSA PHASES */ + ADDTARGETPHASE("cgssaconstruct", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgcopyprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgpeephole", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgvalidbitopt", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgtargetprop", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgdeadcodeelimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgsplitcriticaledge", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgphielimination", CGOptions::DoCGSSA()); + ADDTARGETPHASE("cgregcoalesce", CGOptions::DoCGSSA()); + } /* Normal OPT PHASES */ ADDTARGETPHASE("cgprepeephole", CGOptions::DoPrePeephole()); ADDTARGETPHASE("ebo", CGOptions::DoEBO()); @@ -47,8 +49,10 @@ if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { ADDTARGETPHASE("cgsplitcriticaledge", GetMIRModule()->IsCModule()); ADDTARGETPHASE("regalloc", true); ADDTARGETPHASE("regsaves", GetMIRModule()->IsCModule() && CGOptions::DoRegSavesOpt()); - ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); - ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + if (GetMIRModule()->GetFlavor() != MIRFlavor::kFlavorLmbc) { + ADDTARGETPHASE("storeloadopt", GetMIRModule()->IsCModule() && CGOptions::DoStoreLoadOpt()); + ADDTARGETPHASE("globalopt", CGOptions::DoCGSSA()); + } ADDTARGETPHASE("clearrdinfo", GetMIRModule()->IsCModule() && (CGOptions::DoStoreLoadOpt() || CGOptions::DoGlobalOpt())); ADDTARGETPHASE("generateproepilog", true); ADDTARGETPHASE("framefinalize", true); -- Gitee From 07d4759703df30c6d261e4970693e02a7013b496 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Mon, 27 Jun 2022 14:41:54 -0700 Subject: [PATCH 177/179] Update for agg ret, caller/callee save offset. --- src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp | 2 -- src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp | 6 ------ 2 files changed, 8 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index 19e24b2a78..ed5342b1a4 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -17,8 +17,6 @@ #include "becommon.h" #include "mir_nodes.h" -#define OLD_LMBC 1 - namespace maplebe { using namespace maple; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index e02f1883da..c06250a0ce 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -16,8 +16,6 @@ #include "cg_option.h" #include "cgfunc.h" -#define OLD_LMBC 1 - namespace maplebe { using namespace maple; @@ -1265,7 +1263,6 @@ void AArch64GenProEpilog::GeneratePushRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; -#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { #if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - @@ -1274,7 +1271,6 @@ void AArch64GenProEpilog::GeneratePushRegs() { offset = static_cast((memLayout->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - memLayout->SizeOfArgsToStackPass()); /* for FP/LR */ } -#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignmentInt; @@ -1804,7 +1800,6 @@ void AArch64GenProEpilog::GeneratePopRegs() { AArch64MemLayout *memLayout = static_cast(cgFunc.GetMemlayout()); int32 offset; -#if OLD_LMBC // TBD if (cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc) { #if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - @@ -1814,7 +1809,6 @@ void AArch64GenProEpilog::GeneratePopRegs() { (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - /* for FP/LR */ memLayout->SizeOfArgsToStackPass()); } -#endif if (cgFunc.GetCG()->IsStackProtectorStrong() || cgFunc.GetCG()->IsStackProtectorAll()) { offset -= kAarch64StackPtrAlignmentInt; -- Gitee From 8b9ddc549c68e94cd6789338c561f0632998f226 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Thu, 30 Jun 2022 11:24:14 -0700 Subject: [PATCH 178/179] Some fixes for lmbc vararg memlayout --- src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp | 4 ---- src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp | 4 ---- 2 files changed, 8 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index ed5342b1a4..d9fa8fb2f0 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -541,18 +541,14 @@ uint64 AArch64MemLayout::StackFrameSize() const { uint64 total = segArgsRegPassed.GetSize() + static_cast(cgFunc)->SizeOfCalleeSaved() + GetSizeOfRefLocals() + locals().GetSize() + GetSizeOfSpillReg(); -#if OLD_LMBC // TBD if (cgFunc->GetMirModule().GetFlavor() != MIRFlavor::kFlavorLmbc) { -#endif if (GetSizeOfGRSaveArea() > 0) { total += RoundUp(GetSizeOfGRSaveArea(), kAarch64StackPtrAlignment); } if (GetSizeOfVRSaveArea() > 0) { total += RoundUp(GetSizeOfVRSaveArea(), kAarch64StackPtrAlignment); } -#if OLD_LMBC // TBD } -#endif /* * if the function does not have VLA nor alloca, diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index c06250a0ce..8929c47b5c 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -1223,9 +1223,7 @@ void AArch64GenProEpilog::GeneratePushRegs() { Operand &spOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt); Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); -#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; -#endif if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; if (isLmbc) { @@ -1505,9 +1503,7 @@ void AArch64GenProEpilog::GenerateProlog(BB &bb) { } if (useFP) { Operand &fpOpnd = aarchCGFunc.GetOrCreatePhysicalRegisterOperand(stackBaseReg, k64BitSize, kRegTyInt); -#if 1 bool isLmbc = cgFunc.GetMirModule().GetFlavor() == MIRFlavor::kFlavorLmbc; -#endif int64 argsToStkPassSize = cgFunc.GetMemlayout()->SizeOfArgsToStackPass(); if ((argsToStkPassSize > 0) || isLmbc) { Operand *immOpnd; -- Gitee From 593bb0169e459fe54e5f6405ab2a4647882a6430 Mon Sep 17 00:00:00 2001 From: Fred Chow Date: Mon, 4 Jul 2022 22:20:27 -0700 Subject: [PATCH 179/179] Fixed rebase editing bugs --- .../src/cg/aarch64/aarch64_cgfunc.cpp | 24 ------------------- .../src/cg/aarch64/aarch64_proepilog.cpp | 12 ++++++++++ 2 files changed, 12 insertions(+), 24 deletions(-) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 0774d9df70..5c20002eda 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1292,30 +1292,6 @@ void AArch64CGFunc::SelectAsm(AsmNode &node) { } break; } - case OP_ireadoff: { - IreadoffNode *ireadoff = static_cast(node.Opnd(i)); - Operand *inOpnd = SelectIreadoff(node, *ireadoff); - listInputOpnd->PushOpnd(static_cast(*inOpnd)); - PrimType pType = ireadoff->GetPrimType(); - listInRegPrefix->stringList.push_back( - static_cast(&CreateStringOperand(GetRegPrefixFromPrimType(pType, inOpnd->GetSize(), str)))); - if (isOutputTempNode) { - rPlusOpnd.emplace_back(std::make_pair(inOpnd, pType)); - } - break; - } - case OP_add: { - BinaryNode *addNode = static_cast(node.Opnd(i)); - Operand *inOpnd = SelectAdd(*addNode, *HandleExpr(*addNode, *addNode->Opnd(0)), *HandleExpr(*addNode, *addNode->Opnd(1)), node); - listInputOpnd->PushOpnd(static_cast(*inOpnd)); - PrimType pType = addNode->GetPrimType(); - listInRegPrefix->stringList.push_back( - static_cast(&CreateStringOperand(GetRegPrefixFromPrimType(pType, inOpnd->GetSize(), str)))); - if (isOutputTempNode) { - rPlusOpnd.emplace_back(std::make_pair(inOpnd, pType)); - } - break; - } case OP_constval: { CHECK_FATAL(!isOutputTempNode, "Unexpect"); auto &constNode = static_cast(*node.Opnd(i)); diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp index 8929c47b5c..73686edf1c 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp @@ -1265,6 +1265,12 @@ void AArch64GenProEpilog::GeneratePushRegs() { #if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); +#else + offset = static_cast(memLayout->RealStackFrameSize() - + (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen)/* FP/LR */) - + memLayout->GetSizeOfLocals() - + memLayout->SizeOfArgsToStackPass()); +#endif } else { offset = static_cast((memLayout->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - memLayout->SizeOfArgsToStackPass()); /* for FP/LR */ @@ -1800,6 +1806,12 @@ void AArch64GenProEpilog::GeneratePopRegs() { #if OLD_LMBC // TBD offset = static_cast(memLayout->RealStackFrameSize() - aarchCGFunc.SizeOfCalleeSaved() - memLayout->GetSizeOfLocals()); +#else + offset = static_cast(memLayout->RealStackFrameSize() - + (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen)/* FP/LR */) - + memLayout->GetSizeOfLocals() - + memLayout->SizeOfArgsToStackPass()); +#endif } else { offset = static_cast((static_cast(cgFunc.GetMemlayout())->RealStackFrameSize() - (aarchCGFunc.SizeOfCalleeSaved() - (kDivide2 * kIntregBytelen))) - /* for FP/LR */ -- Gitee