diff --git a/src/mapleall/maple_be/src/be/lower.cpp b/src/mapleall/maple_be/src/be/lower.cpp
index 83850176ef5d8399db35a8762dee00c422135020..7bbefc28a857a9f6d31a9b15734017c339cd7f76 100644
--- a/src/mapleall/maple_be/src/be/lower.cpp
+++ b/src/mapleall/maple_be/src/be/lower.cpp
@@ -783,7 +783,7 @@ StmtNode *CGLowerer::WriteBitField(const std::pair<int32, int32> &byteBitOffsets
 BaseNode *CGLowerer::ReadBitField(const std::pair<int32, int32> &byteBitOffsets, const MIRBitFieldType *fieldType,
     BaseNode *baseAddr) {
   auto bitSize = fieldType->GetFieldSize();
-  auto primType = fieldType->GetPrimType();
+  auto primType = GetRegPrimType(fieldType->GetPrimType());
   auto byteOffset = byteBitOffsets.first;
   auto bitOffset = byteBitOffsets.second;
   auto *builder = mirModule.GetMIRBuilder();
diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_offset_adjust.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_offset_adjust.cpp
index 0e6b864b75bc1703496a5cc9f2def3007162fb7a..541be510ed07cb23942745905006c1fce6a4b206 100644
--- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_offset_adjust.cpp
+++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_offset_adjust.cpp
@@ -72,9 +72,9 @@ void AArch64FPLROffsetAdjustment::AdjustmentOffsetForOpnd(Insn &insn, AArch64CGF
       if (ofstOpnd->GetVary() == kAdjustVary || ofstOpnd->GetVary() == kNotVary) {
         bool condition = aarchCGFunc.IsOperandImmValid(insn.GetMachineOpcode(), &memOpnd, i);
         if (!condition) {
-          memOpnd = (newMemOpnd1 == nullptr ? memOpnd : *newMemOpnd1);
+          auto &adjOpnd = (newMemOpnd1 == nullptr ? memOpnd : *newMemOpnd1);
           MemOperand &newMemOpnd2 = aarchCGFunc.SplitOffsetWithAddInstruction(
-              memOpnd, memOpnd.GetSize(), static_cast<AArch64reg>(R16), false, &insn, insn.IsLoadStorePair());
+              adjOpnd, adjOpnd.GetSize(), static_cast<AArch64reg>(R16), false, &insn, insn.IsLoadStorePair());
           insn.SetOperand(i, newMemOpnd2);
         }
       }