diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_isa.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_isa.h
index ae170bf012f678f12f133667f4966841c90e4bb9..3ea99dc366206480125d84e9932338ffa583433d 100644
--- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_isa.h
+++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_isa.h
@@ -161,6 +161,10 @@ static inline bool IsPseudoInstruction(MOperator mOp) {
  */
 uint32 GetJumpTargetIdx(const Insn &insn);
 
+bool IsSub(const Insn &insn);
+
+MOperator GetMopSub2Subs(const Insn &insn);
+
 MOperator FlipConditionOp(MOperator flippedOp);
 } /* namespace AArch64isa */
 
diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp
index 67fde07e027c8246da3a3d8847fcde9c91ac3945..12b79dc21ee3df43545452e08ab589ae81643c48 100644
--- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp
+++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp
@@ -5208,7 +5208,7 @@ Operand *AArch64CGFunc::SelectAbsSub(Insn &lastInsn, const UnaryNode &node, Oper
   uint32 mopCsneg = is64Bits ? MOP_xcnegrrrc : MOP_wcnegrrrc;
   /* ABS requires the operand be interpreted as a signed integer */
   CondOperand &condOpnd = GetCondOperand(CC_MI);
-  MOperator newMop = lastInsn.GetMachineOpcode() + 1;
+  MOperator newMop = AArch64isa::GetMopSub2Subs(lastInsn);
   Operand &rflag = GetOrCreateRflag();
   std::vector<Operand *> opndVec;
   opndVec.push_back(&rflag);
@@ -5239,9 +5239,16 @@ Operand *AArch64CGFunc::SelectAbs(UnaryNode &node, Operand &opnd0) {
     PrimType primType = is64Bits ? (PTY_i64) : (PTY_i32);
     Operand &newOpnd0 = LoadIntoRegister(opnd0, primType);
     Insn *lastInsn = GetCurBB()->GetLastInsn();
-    if (lastInsn != nullptr && lastInsn->GetMachineOpcode() >= MOP_xsubrrr &&
-      lastInsn->GetMachineOpcode() <= MOP_wsubrri12) {
-      return SelectAbsSub(*lastInsn, node, newOpnd0);
+    if (lastInsn != nullptr && AArch64isa::IsSub(*lastInsn)) {
+      Operand &dest = lastInsn->GetOperand(kInsnFirstOpnd);
+      Operand &opd1 = lastInsn->GetOperand(kInsnSecondOpnd);
+      Operand &opd2 = lastInsn->GetOperand(kInsnThirdOpnd);
+      regno_t absReg = static_cast<RegOperand&>(newOpnd0).GetRegisterNumber();
+      if ((dest.IsRegister() && static_cast<RegOperand&>(dest).GetRegisterNumber() == absReg) ||
+          (opd1.IsRegister() && static_cast<RegOperand&>(opd1).GetRegisterNumber() == absReg) ||
+          (opd2.IsRegister() && static_cast<RegOperand&>(opd2).GetRegisterNumber() == absReg)) {
+        return SelectAbsSub(*lastInsn, node, newOpnd0);
+      }
     }
     RegOperand &resOpnd = CreateRegisterOperandOfType(primType);
     SelectAArch64Cmp(newOpnd0, CreateImmOperand(0, is64Bits ? PTY_u64 : PTY_u32, false),
diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_isa.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_isa.cpp
index 517d7184ed2dcb8ac0ccd299a1ff84de5f798945..051e8dd0215b95f9bb86162a9c856277de1f2be0 100644
--- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_isa.cpp
+++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_isa.cpp
@@ -140,5 +140,46 @@ uint32 GetJumpTargetIdx(const Insn &insn) {
   }
   return kInsnFirstOpnd;
 }
+
+bool IsSub(const Insn &insn) {
+  MOperator curMop = insn.GetMachineOpcode();
+  switch (curMop) {
+  case MOP_xsubrrr:
+  case MOP_xsubrrrs:
+  case MOP_xsubrri24:
+  case MOP_xsubrri12:
+  case MOP_wsubrrr:
+  case MOP_wsubrrrs:
+  case MOP_wsubrri24:
+  case MOP_wsubrri12:
+    return true;
+  default:
+    return false;
+  }
+}
+
+MOperator GetMopSub2Subs(const Insn &insn) {
+  MOperator curMop = insn.GetMachineOpcode();
+  switch (curMop) {
+  case MOP_xsubrrr:
+    return MOP_xsubsrrr;
+  case MOP_xsubrrrs:
+    return MOP_xsubsrrrs;
+  case MOP_xsubrri24:
+    return MOP_xsubsrri24;
+  case MOP_xsubrri12:
+    return MOP_xsubsrri12;
+  case MOP_wsubrrr:
+    return MOP_wsubsrrr;
+  case MOP_wsubrrrs:
+    return MOP_wsubsrrrs;
+  case MOP_wsubrri24:
+    return MOP_wsubsrri24;
+  case MOP_wsubrri12:
+    return MOP_wsubsrri12;
+  default:
+    return curMop;
+  }
+}
 } /* namespace AArch64isa */
 }  /* namespace maplebe */