diff --git a/src/bin/jbc2mpl b/src/bin/jbc2mpl index b223ba678886ebc720052e7efbbe4ad8504c2994..a8555fb6200c0de412f58d1b2c0c6a4c92760739 100755 Binary files a/src/bin/jbc2mpl and b/src/bin/jbc2mpl differ diff --git a/src/bin/maple b/src/bin/maple index b1e64f533f6c48ac77ba131be64eae4f162ffd80..556f5686a2dc8b011665c0719715a99d8e9a1b2c 100755 Binary files a/src/bin/maple and b/src/bin/maple differ diff --git a/src/maple_be/include/be/common_utils.h b/src/maple_be/include/be/common_utils.h index 05c5db1897c356ecb8b68f9d0cc58b860fcce521..775795da8c91c3a52c61505f1768156c803ec7eb 100644 --- a/src/maple_be/include/be/common_utils.h +++ b/src/maple_be/include/be/common_utils.h @@ -86,12 +86,12 @@ constexpr int32 kEARetTempNameSize = 10; * Aarch64 data processing instructions have 12 bits of space for values in their instuction word * This is arranged as a four-bit rotate value and an eight-bit immediate value: */ -constexpr uint32 kMaxAarch64ImmVal12Bits = 12; - -constexpr uint32 kMaxAarch64ImmVal13Bits = 13; +constexpr uint32 kMaxImmVal8Bits = 8; +constexpr uint32 kMaxImmVal12Bits = 12; +constexpr uint32 kMaxImmVal13Bits = 13; /* aarch64 assembly takes up to 24-bits */ -constexpr uint32 kMaxAarch64ImmVal24Bits = 24; +constexpr uint32 kMaxImmVal24Bits = 24; constexpr double kMicroSecPerMilliSec = 1000.0; diff --git a/src/maple_be/include/cg/aarch64/aarch64_operand.h b/src/maple_be/include/cg/aarch64/aarch64_operand.h index de7930a63292aa1c950356cbb3345347f6a2dc67..26296b1ade891aed7082dcf5d39887290f729110 100644 --- a/src/maple_be/include/cg/aarch64/aarch64_operand.h +++ b/src/maple_be/include/cg/aarch64/aarch64_operand.h @@ -149,6 +149,14 @@ class AArch64ImmOperand : public ImmOperand { return memPool.Clone(*this); } + bool IsInBitSize(uint8 size, uint8 nLowerZeroBits) const override { + /* mask1 is a 64bits number that is all 1 shifts left size bits */ + const uint64 mask1 = 0xffffffffffffffffUL << size; + /* mask2 is a 64 bits number that nlowerZeroBits are all 1, higher bits aro all 0 */ + uint64 mask2 = (static_cast(1) << static_cast(nLowerZeroBits)) - 1UL; + return (mask2 & value) == 0UL && (mask1 & ((static_cast(value)) >> nLowerZeroBits)) == 0UL; + } + bool IsBitmaskImmediate() const { ASSERT(!IsZero(), " 0 is reserved for bitmask immediate"); ASSERT(!IsAllOnes(), " -1 is reserved for bitmask immediate"); @@ -240,6 +248,14 @@ class AArch64OfstOperand : public OfstOperand { return memPool.Clone(*this); } + bool IsInBitSize(uint8 size, uint8 nLowerZeroBits) const override { + /* mask1 is a 64bits number that is all 1 shifts left size bits */ + const uint64 mask1 = 0xffffffffffffffffUL << size; + /* mask2 is a 64 bits number that nlowerZeroBits are all 1, higher bits aro all 0 */ + uint64 mask2 = (static_cast(1) << static_cast(nLowerZeroBits)) - 1UL; + return (mask2 & value) == 0UL && (mask1 & ((static_cast(value)) >> nLowerZeroBits)) == 0UL; + } + bool IsSymOffset() const { return offsetType == kSymbolOffset; } diff --git a/src/maple_be/include/cg/ebo.h b/src/maple_be/include/cg/ebo.h index c3151581b05f7fc16969218e1421ab1b7518af25..706c34c7b77661c6425878380be0e2b693d73b01 100644 --- a/src/maple_be/include/cg/ebo.h +++ b/src/maple_be/include/cg/ebo.h @@ -50,6 +50,9 @@ struct OpndInfo { InsnInfo *insnInfo = nullptr; bool redefinedInBB = false; /* A following definition exisit in bb. */ bool redefined = false; /* A following definition exisit. */ +#if TARGARM32 + bool mayReDef = false; +#endif OpndInfo *same = nullptr; /* Other definitions of the same operand. */ OpndInfo *prev = nullptr; OpndInfo *next = nullptr; @@ -141,7 +144,10 @@ class Ebo { bool IsPhysicalReg(const Operand &opnd) const; bool HasAssignedReg(const Operand &opnd) const; bool IsOfSameClass(const Operand &op0, const Operand &op1) const; - bool OpndAvailableInBB(const BB &bb, OpndInfo &info); + bool OpndAvailableInBB(const BB &bb, OpndInfo *info); + bool ForwardPropCheck(const Operand *opndReplace, OpndInfo &opndInfo, const Operand &opnd, Insn &insn); + bool RegForwardCheck(Insn &insn, const Operand &opnd, const Operand *opndReplace, Operand &oldOpnd, + const OpndInfo *tmpInfo); bool IsNotVisited(const BB &bb) { return !visitedBBs.at(bb.GetId()); }; diff --git a/src/maple_be/include/cg/operand.h b/src/maple_be/include/cg/operand.h index d029d14d874e1203f976cb5846c50cc0660ba756..f640baa6a4697b7ff264e6b22b00dc1bf0e46a5c 100644 --- a/src/maple_be/include/cg/operand.h +++ b/src/maple_be/include/cg/operand.h @@ -328,6 +328,7 @@ class ImmOperand : public Operand { ~ImmOperand() override = default; virtual bool IsSingleInstructionMovable() const = 0; + virtual bool IsInBitSize(uint8 size, uint8 nLowerZeroBits) const = 0; int64 GetValue() const { return value; @@ -357,14 +358,6 @@ class ImmOperand : public Operand { return isSigned; } - bool IsInBitSize(uint8 size, uint8 nLowerZeroBits = 0) const { - /* mask1 is a 64bits number that is all 1 shifts left size bits */ - const uint64 mask1 = 0xffffffffffffffffUL << size; - /* mask2 is a 64 bits number that nlowerZeroBits are all 1, higher bits aro all 0 */ - uint64 mask2 = (static_cast(1) << static_cast(nLowerZeroBits)) - 1UL; - return (mask2 & value) == 0UL && (mask1 & ((static_cast(value)) >> nLowerZeroBits)) == 0UL; - } - bool IsInBitSizeRot(uint8 size) const { return IsInBitSizeRot(size, value); } diff --git a/src/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 1105b40926c75c3f9eabf246aeddadadea167a2c..c613630ef609b333138a1f7905bcb29aa599aa80 100644 --- a/src/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -1786,8 +1786,8 @@ void AArch64CGFunc::SelectCondGoto(LabelOperand &targetOpnd, Opcode jmpOp, Opcod * either cmp or cmp with shift 12 encoding */ ImmOperand *immOpnd = static_cast(opnd1); - if (immOpnd->IsInBitSize(kMaxAarch64ImmVal12Bits) || - immOpnd->IsInBitSize(kMaxAarch64ImmVal12Bits, kMaxAarch64ImmVal12Bits)) { + if (immOpnd->IsInBitSize(kMaxImmVal12Bits, 0) || + immOpnd->IsInBitSize(kMaxImmVal12Bits, kMaxImmVal12Bits)) { mOp = is64Bits ? MOP_xcmpri : MOP_wcmpri; } else { opnd1 = &SelectCopy(*opnd1, primType, primType); @@ -1958,7 +1958,7 @@ void AArch64CGFunc::SelectAdd(Operand &resOpnd, Operand &opnd0, Operand &opnd1, SelectSub(resOpnd, opnd0, *immOpnd, primType); return; } - if (immOpnd->IsInBitSize(kMaxAarch64ImmVal24Bits)) { + if (immOpnd->IsInBitSize(kMaxImmVal24Bits, 0)) { /* * ADD Wd|WSP, Wn|WSP, #imm{, shift} ; 32-bit general registers * ADD Xd|SP, Xn|SP, #imm{, shift} ; 64-bit general registers @@ -1967,15 +1967,15 @@ void AArch64CGFunc::SelectAdd(Operand &resOpnd, Operand &opnd0, Operand &opnd1, */ MOperator mOpCode = MOP_undef; Operand *newOpnd0 = &opnd0; - if (!(immOpnd->IsInBitSize(kMaxAarch64ImmVal12Bits) || - immOpnd->IsInBitSize(kMaxAarch64ImmVal12Bits, kMaxAarch64ImmVal12Bits))) { + if (!(immOpnd->IsInBitSize(kMaxImmVal12Bits, 0) || + immOpnd->IsInBitSize(kMaxImmVal12Bits, kMaxImmVal12Bits))) { /* process higher 12 bits */ - ImmOperand &immOpnd2 = CreateImmOperand(static_cast(immOpnd->GetValue()) >> kMaxAarch64ImmVal12Bits, + ImmOperand &immOpnd2 = CreateImmOperand(static_cast(immOpnd->GetValue()) >> kMaxImmVal12Bits, immOpnd->GetSize(), immOpnd->IsSignedValue()); mOpCode = is64Bits ? MOP_xaddrri24 : MOP_waddrri24; Insn &newInsn = GetCG()->BuildInstruction(mOpCode, resOpnd, opnd0, immOpnd2, addSubLslOperand); GetCurBB()->AppendInsn(newInsn); - immOpnd->ModuloByPow2(kMaxAarch64ImmVal12Bits); + immOpnd->ModuloByPow2(kMaxImmVal12Bits); newOpnd0 = &resOpnd; } /* process lower 12 bits */ @@ -2060,7 +2060,7 @@ void AArch64CGFunc::SelectSub(Operand &resOpnd, Operand &opnd0, Operand &opnd1, return; } - if (immOpnd->IsInBitSize(kMaxAarch64ImmVal24Bits)) { + if (immOpnd->IsInBitSize(kMaxImmVal24Bits, 0)) { /* * SUB Wd|WSP, Wn|WSP, #imm{, shift} ; 32-bit general registers * SUB Xd|SP, Xn|SP, #imm{, shift} ; 64-bit general registers @@ -2068,15 +2068,15 @@ void AArch64CGFunc::SelectSub(Operand &resOpnd, Operand &opnd0, Operand &opnd1, * aarch64 assembly takes up to 24-bits, if the lower 12 bits is all 0 */ MOperator mOpCode = MOP_undef; - if (!(immOpnd->IsInBitSize(kMaxAarch64ImmVal12Bits) || - immOpnd->IsInBitSize(kMaxAarch64ImmVal12Bits, kMaxAarch64ImmVal12Bits))) { + if (!(immOpnd->IsInBitSize(kMaxImmVal12Bits, 0) || + immOpnd->IsInBitSize(kMaxImmVal12Bits, kMaxImmVal12Bits))) { /* process higher 12 bits */ - ImmOperand &immOpnd2 = CreateImmOperand(static_cast(immOpnd->GetValue()) >> kMaxAarch64ImmVal12Bits, + ImmOperand &immOpnd2 = CreateImmOperand(static_cast(immOpnd->GetValue()) >> kMaxImmVal12Bits, immOpnd->GetSize(), immOpnd->IsSignedValue()); mOpCode = is64Bits ? MOP_xsubrri24 : MOP_wsubrri24; Insn &newInsn = GetCG()->BuildInstruction(mOpCode, resOpnd, *opnd0Bak, immOpnd2, addSubLslOperand); GetCurBB()->AppendInsn(newInsn); - immOpnd->ModuloByPow2(kMaxAarch64ImmVal12Bits); + immOpnd->ModuloByPow2(kMaxImmVal12Bits); opnd0Bak = &resOpnd; } /* process lower 12 bits */ @@ -2598,7 +2598,7 @@ void AArch64CGFunc::SelectAArch64Cmp(Operand &o0, Operand &o1, bool isIntType, u * imm : 0 ~ 4095, shift: none, LSL #0, or LSL #12 * aarch64 assembly takes up to 24-bits, if the lower 12 bits is all 0 */ - if (immOpnd->IsInBitSize(12) || immOpnd->IsInBitSize(12, 12)) { + if (immOpnd->IsInBitSize(kMaxImmVal12Bits, 0) || immOpnd->IsInBitSize(kMaxImmVal12Bits, kMaxImmVal12Bits)) { mOpCode = (dsize == k64BitSize) ? MOP_xcmpri : MOP_wcmpri; } else { /* load into register */ @@ -3006,7 +3006,7 @@ Operand *AArch64CGFunc::SelectExtractbits(ExtractbitsNode &node, Operand &srcOpn uint8 bitOffset = node.GetBitsOffset(); uint8 bitSize = node.GetBitsSize(); bool is64Bits = (GetPrimTypeBitSize(dtype) == k64BitSize); - uint32 immWidth = is64Bits ? kMaxAarch64ImmVal13Bits : kMaxAarch64ImmVal12Bits; + uint32 immWidth = is64Bits ? kMaxImmVal13Bits : kMaxImmVal12Bits; Operand &opnd0 = LoadIntoRegister(srcOpnd, dtype); if ((bitOffset == 0) && !isSigned && (bitSize < immWidth)) { SelectBand(resOpnd, opnd0, CreateImmOperand((static_cast(1) << bitSize) - 1, immWidth, false), dtype); @@ -5303,7 +5303,7 @@ AArch64MemOperand &AArch64CGFunc::GetOrCreateMemOpnd(AArch64MemOperand::AArch64A /* offset: base offset from FP or SP */ MemOperand &AArch64CGFunc::CreateMemOpnd(RegOperand &baseOpnd, int32 offset, uint32 size) { AArch64OfstOperand &offsetOpnd = CreateOfstOpnd(offset, k32BitSize); - if (!ImmOperand::IsInBitSizeRot(kMaxAarch64ImmVal12Bits, offset)) { + if (!ImmOperand::IsInBitSizeRot(kMaxImmVal12Bits, offset)) { Operand *resImmOpnd = &SelectCopy(CreateImmOperand(offset, k32BitSize, true), PTY_i32, PTY_i32); return *memPool->New(AArch64MemOperand::kAddrModeBOi, size, baseOpnd, static_cast(resImmOpnd), nullptr, nullptr); @@ -5317,7 +5317,7 @@ MemOperand &AArch64CGFunc::CreateMemOpnd(RegOperand &baseOpnd, int32 offset, uin /* offset: base offset + #:lo12:Label+immediate */ MemOperand &AArch64CGFunc::CreateMemOpnd(RegOperand &baseOpnd, int32 offset, uint32 size, const MIRSymbol &sym) { AArch64OfstOperand &offsetOpnd = CreateOfstOpnd(offset, k32BitSize); - ASSERT(ImmOperand::IsInBitSizeRot(kMaxAarch64ImmVal12Bits, offset), ""); + ASSERT(ImmOperand::IsInBitSizeRot(kMaxImmVal12Bits, offset), ""); return *memPool->New(AArch64MemOperand::kAddrModeBOi, size, baseOpnd, nullptr, &offsetOpnd, &sym); } @@ -5553,13 +5553,13 @@ void AArch64CGFunc::SelectAddAfterInsn(Operand &resOpnd, Operand &opnd0, Operand MOperator mOpCode = MOP_undef; /* lower 24 bits has 1, higher bits are all 0 */ - if (immOpnd->IsInBitSize(kMaxAarch64ImmVal24Bits)) { + if (immOpnd->IsInBitSize(kMaxImmVal24Bits, 0)) { /* lower 12 bits and higher 12 bits both has 1 */ Operand *newOpnd0 = &opnd0; - if (!(immOpnd->IsInBitSize(kMaxAarch64ImmVal12Bits) || - immOpnd->IsInBitSize(kMaxAarch64ImmVal12Bits, kMaxAarch64ImmVal12Bits))) { + if (!(immOpnd->IsInBitSize(kMaxImmVal12Bits, 0) || + immOpnd->IsInBitSize(kMaxImmVal12Bits, kMaxImmVal12Bits))) { /* process higher 12 bits */ - ImmOperand &immOpnd2 = CreateImmOperand(static_cast(immOpnd->GetValue()) >> kMaxAarch64ImmVal12Bits, + ImmOperand &immOpnd2 = CreateImmOperand(static_cast(immOpnd->GetValue()) >> kMaxImmVal12Bits, immOpnd->GetSize(), immOpnd->IsSignedValue()); mOpCode = is64Bits ? MOP_xaddrri24 : MOP_waddrri24; Insn &newInsn = GetCG()->BuildInstruction(mOpCode, resOpnd, opnd0, immOpnd2, addSubLslOperand); @@ -5569,7 +5569,7 @@ void AArch64CGFunc::SelectAddAfterInsn(Operand &resOpnd, Operand &opnd0, Operand insn.GetBB()->InsertInsnBefore(insn, newInsn); } /* get lower 12 bits value */ - immOpnd->ModuloByPow2(kMaxAarch64ImmVal12Bits); + immOpnd->ModuloByPow2(kMaxImmVal12Bits); newOpnd0 = &resOpnd; } /* process lower 12 bits value */ diff --git a/src/maple_be/src/cg/aarch64/aarch64_ebo.cpp b/src/maple_be/src/cg/aarch64/aarch64_ebo.cpp index 65c72c7caf5e907bed3b5184c7ade2b2a2e66399..20b209416ce9000c5a7e1a1e839c51d51d6c25f9 100644 --- a/src/maple_be/src/cg/aarch64/aarch64_ebo.cpp +++ b/src/maple_be/src/cg/aarch64/aarch64_ebo.cpp @@ -299,9 +299,8 @@ bool AArch64Ebo::DoConstProp(Insn &insn, uint32 idx, Operand &opnd) { case MOP_waddrrr: case MOP_xsubrrr: case MOP_wsubrrr: { - if ((idx != kInsnThirdOpnd) || !src->IsInBitSize(kMaxAarch64ImmVal24Bits) || - !(src->IsInBitSize(kMaxAarch64ImmVal12Bits) || - src->IsInBitSize(kMaxAarch64ImmVal12Bits, kMaxAarch64ImmVal12Bits))) { + if ((idx != kInsnThirdOpnd) || !src->IsInBitSize(kMaxImmVal24Bits, 0) || + !(src->IsInBitSize(kMaxImmVal12Bits, 0) || src->IsInBitSize(kMaxImmVal12Bits, kMaxImmVal12Bits))) { return false; } Operand &result = insn.GetOperand(0); @@ -490,15 +489,14 @@ bool AArch64Ebo::SimplifyConstOperand(Insn &insn, const MapleVector &o } if ((insn.GetMachineOpcode() == MOP_xaddrrr) || (insn.GetMachineOpcode() == MOP_waddrrr)) { - if (immOpnd->IsInBitSize(kMaxAarch64ImmVal24Bits)) { + if (immOpnd->IsInBitSize(kMaxImmVal24Bits, 0)) { /* * ADD Wd|WSP, Wn|WSP, #imm{, shift} ; 32-bit general registers * ADD Xd|SP, Xn|SP, #imm{, shift} ; 64-bit general registers * imm : 0 ~ 4095, shift: none, LSL #0, or LSL #12 * aarch64 assembly takes up to 24-bits, if the lower 12 bits is all 0 */ - if ((immOpnd->IsInBitSize(kMaxAarch64ImmVal12Bits) || - immOpnd->IsInBitSize(kMaxAarch64ImmVal12Bits, kMaxAarch64ImmVal12Bits))) { + if (immOpnd->IsInBitSize(kMaxImmVal12Bits, 0) || immOpnd->IsInBitSize(kMaxImmVal12Bits, kMaxImmVal12Bits)) { MOperator mOp = opndSize == k64BitSize ? MOP_xaddrri12 : MOP_waddrri12; Insn &newInsn = cgFunc->GetCG()->BuildInstruction(mOp, *res, *op, *immOpnd); bb->ReplaceInsn(insn, newInsn); @@ -520,8 +518,8 @@ bool AArch64Ebo::SimplifyConstOperand(Insn &insn, const MapleVector &o AArch64ImmOperand &imm0 = static_cast(prev->GetOperand(kInsnThirdOpnd)); int64_t val = imm0.GetValue() + immOpnd->GetValue(); AArch64ImmOperand &imm1 = a64CGFunc->CreateImmOperand(val, opndSize, imm0.IsSignedValue()); - if (imm1.IsInBitSize(kMaxAarch64ImmVal24Bits) && (imm1.IsInBitSize(kMaxAarch64ImmVal12Bits) || - imm1.IsInBitSize(kMaxAarch64ImmVal12Bits, kMaxAarch64ImmVal12Bits))) { + if (imm1.IsInBitSize(kMaxImmVal24Bits, 0) && (imm1.IsInBitSize(kMaxImmVal12Bits, 0) || + imm1.IsInBitSize(kMaxImmVal12Bits, kMaxImmVal12Bits))) { MOperator mOp = (opndSize == k64BitSize ? MOP_xaddrri12 : MOP_waddrri12); bb->ReplaceInsn(insn, cgFunc->GetCG()->BuildInstruction(mOp, *res, prevOpnd0, imm1)); result = true; @@ -724,8 +722,7 @@ bool AArch64Ebo::SpecialSequence(Insn &insn, const MapleVector &origI auto &res1 = static_cast(insn1->GetOperand(kInsnFirstOpnd)); if (RegistersIdentical(res1, *op1) && RegistersIdentical(res1, res2) && (GetOpndInfo(base2, -1) != nullptr) && !GetOpndInfo(base2, -1)->redefined) { - immVal = - imm0Val + imm1.GetValue() + (static_cast(immOpnd2.GetValue()) << kMaxAarch64ImmVal12Bits); + immVal = imm0Val + imm1.GetValue() + (static_cast(immOpnd2.GetValue()) << kMaxImmVal12Bits); op1 = &base2; } else { return false; diff --git a/src/maple_be/src/cg/aarch64/aarch64_peep.cpp b/src/maple_be/src/cg/aarch64/aarch64_peep.cpp index 9088c785de6f7172eae7dc9dcf23e0c77df0f006..022a84d64d9167e47bbf4e41fca4013738b36f86 100644 --- a/src/maple_be/src/cg/aarch64/aarch64_peep.cpp +++ b/src/maple_be/src/cg/aarch64/aarch64_peep.cpp @@ -2462,13 +2462,11 @@ void ComputationTreeAArch64::Run(BB &bb, Insn &insn) { if (lsl.GetShiftAmount() == lslShiftAmountCaseA) { sxtw = &aarch64CGFunc->CreateExtendShiftOperand(ExtendShiftOperand::kSXTW, lslShiftAmountCaseA + 1, lslBitLenth); - imm = &aarch64CGFunc->CreateImmOperand(oriAddEnd + (1ULL << lslShiftAmountCaseA), - kMaxAarch64ImmVal12Bits, true); + imm = &aarch64CGFunc->CreateImmOperand(oriAddEnd + (1ULL << lslShiftAmountCaseA), kMaxImmVal12Bits, true); } else if (lsl.GetShiftAmount() == lslShiftAmountCaseB) { sxtw = &aarch64CGFunc->CreateExtendShiftOperand(ExtendShiftOperand::kSXTW, lslShiftAmountCaseB + 1, lslBitLenth); - imm = &aarch64CGFunc->CreateImmOperand(oriAddEnd + (1ULL << lslShiftAmountCaseB), - kMaxAarch64ImmVal12Bits, true); + imm = &aarch64CGFunc->CreateImmOperand(oriAddEnd + (1ULL << lslShiftAmountCaseB), kMaxImmVal12Bits, true); } Insn &newInsn = cgFunc.GetCG()->BuildInstruction(MOP_xxwaddrrre, sxtwInsn->GetOperand(kInsnFirstOpnd), diff --git a/src/maple_be/src/cg/ebo.cpp b/src/maple_be/src/cg/ebo.cpp index cbb604b3f53da6026274312e03a97547fdec324c..cc67edb780474ac2d7870f18b5a07fcf22e45d3a 100644 --- a/src/maple_be/src/cg/ebo.cpp +++ b/src/maple_be/src/cg/ebo.cpp @@ -119,12 +119,15 @@ bool Ebo::IsOfSameClass(const Operand &op0, const Operand &op1) const { } /* return true if opnd of bb is available. */ -bool Ebo::OpndAvailableInBB(const BB &bb, OpndInfo &info) { - if (info.opnd == nullptr) { +bool Ebo::OpndAvailableInBB(const BB &bb, OpndInfo *info) { + if (info == nullptr) { + return false; + } + if (info->opnd == nullptr) { return false; } - Operand *op = info.opnd; + Operand *op = info->opnd; if (op->IsConstant()) { return true; } @@ -133,13 +136,13 @@ bool Ebo::OpndAvailableInBB(const BB &bb, OpndInfo &info) { if (op->IsRegShift() || op->IsRegister()) { hashVal = -1; } else { - hashVal = info.hashVal; + hashVal = info->hashVal; } - if (GetOpndInfo(*op, hashVal) != &info) { + if (GetOpndInfo(*op, hashVal) != info) { return false; } /* global operands aren't supported at low levels of optimization. */ - if ((Globals::GetInstance()->GetOptimLevel() < CGOptions::kLevel2) && (&bb != info.bb)) { + if ((Globals::GetInstance()->GetOptimLevel() < CGOptions::kLevel2) && (&bb != info->bb)) { return false; } if (beforeRegAlloc && IsPhysicalReg(*op)) { @@ -148,6 +151,54 @@ bool Ebo::OpndAvailableInBB(const BB &bb, OpndInfo &info) { return true; } +bool Ebo::ForwardPropCheck(const Operand *opndReplace, OpndInfo &opndInfo, const Operand &opnd, Insn &insn) { + if (opndReplace == nullptr) { + return false; + } + if ((opndInfo.replacementInfo != nullptr) && opndInfo.replacementInfo->redefined) { + return false; + } +#if TARGARM32 + /* for arm32, disable forwardProp in strd insn. */ + if (insn.GetMachineOpcode() == MOP_strd) { + return false; + } + if (opndInfo.mayReDef) { + return false; + } +#endif + if (!(opndReplace->IsConstant() || + ((OpndAvailableInBB(*insn.GetBB(), opndInfo.replacementInfo) || RegistersIdentical(opnd, *opndReplace)) && + (HasAssignedReg(opnd) == HasAssignedReg(*opndReplace))))) { + return false; + } + /* if beforeRA, replace op should not be PhysicalRe */ + return !beforeRegAlloc || !IsPhysicalReg(*opndReplace); +} + +bool Ebo::RegForwardCheck(Insn &insn, const Operand &opnd, const Operand *opndReplace, Operand &oldOpnd, + const OpndInfo *tmpInfo) { + if (opnd.IsConstant()) { + return false; + } + if (!(!beforeRegAlloc || (HasAssignedReg(oldOpnd) == HasAssignedReg(*opndReplace)) || opnd.IsConstReg() || + !insn.IsMove())) { + return false; + } + if (!((insn.GetResultNum() == 0) || + (((insn.GetResult(0) != nullptr) && !RegistersIdentical(opnd, *(insn.GetResult(0)))) || !beforeRegAlloc))) { + return false; + } + if (!(beforeRegAlloc || !IsFrameReg(oldOpnd))) { + return false; + } + if (insn.IsDestRegAlsoSrcReg()) { + return false; + } + return ((IsOfSameClass(oldOpnd, *opndReplace) && (oldOpnd.GetSize() <= opndReplace->GetSize())) || + ((tmpInfo != nullptr) && IsMovToSIMDVmov(insn, *tmpInfo->insn))); +} + /* For Memory Operand, its info was stored in a hash table, this function is to compute its hash value. */ int32 Ebo::ComputeOpndHash(const Operand &opnd) const { uint64 hashIdx = reinterpret_cast(&opnd) >> k4ByteSize; @@ -489,85 +540,73 @@ bool Ebo::ForwardPropagateOpnd(Insn &insn, Operand *&opnd, uint32 opndIndex, } /* forward propagation of constants */ - ASSERT(opndIndex < origInfos.size(), "SetOpndInfo hashval outof range!"); - if ((opndReplace != nullptr) && !((opndInfo->replacementInfo != nullptr) && opndInfo->replacementInfo->redefined) && - (opndReplace->IsConstant() || - ((((opndInfo->replacementInfo != nullptr) && OpndAvailableInBB(*insn.GetBB(), *opndInfo->replacementInfo)) || - RegistersIdentical(*opnd, *opndReplace)) && - (HasAssignedReg(*opnd) == HasAssignedReg(*opndReplace)))) && - (!beforeRegAlloc || (!IsPhysicalReg(*opndReplace)))) { - Operand *oldOpnd = opnd; - opnd = opndInfo->replacementOpnd; - opndInfo = opndInfo->replacementInfo; - - /* constant prop. */ - if (opnd->IsIntImmediate() && oldOpnd->IsRegister()) { - if (DoConstProp(insn, opndIndex, *opnd)) { - DecRef(*origInfos.at(opndIndex)); - /* Update the actual expression info. */ - origInfos.at(opndIndex) = opndInfo; - } - } - /* move reg, wzr, store vreg, mem ==> store wzr, mem */ -#if TARGAARCH64 - if (opnd->IsZeroRegister() && opndIndex == 0 && - (insn.GetMachineOpcode() == MOP_wstr || insn.GetMachineOpcode() == MOP_xstr)) { - if (EBO_DUMP) { - LogInfo::MapleLogger() << "===replace operand " << opndIndex << " of insn: \n"; - insn.Dump(); - LogInfo::MapleLogger() << "the new insn is:\n"; - } - insn.SetOperand(opndIndex, *opnd); + CHECK_FATAL(opndIndex < origInfos.size(), "SetOpndInfo hashval outof range!"); + if (!ForwardPropCheck(opndReplace, *opndInfo, *opnd, insn)) { + return false; + } + Operand *oldOpnd = opnd; + opnd = opndInfo->replacementOpnd; + opndInfo = opndInfo->replacementInfo; + + /* constant prop. */ + if (opnd->IsIntImmediate() && oldOpnd->IsRegister()) { + if (DoConstProp(insn, opndIndex, *opnd)) { DecRef(*origInfos.at(opndIndex)); /* Update the actual expression info. */ origInfos.at(opndIndex) = opndInfo; - if (EBO_DUMP) { - insn.Dump(); - } } + } + /* move reg, wzr, store vreg, mem ==> store wzr, mem */ +#if TARGAARCH64 + if (opnd->IsZeroRegister() && opndIndex == 0 && + (insn.GetMachineOpcode() == MOP_wstr || insn.GetMachineOpcode() == MOP_xstr)) { + if (EBO_DUMP) { + LogInfo::MapleLogger() << "===replace operand " << opndIndex << " of insn: \n"; + insn.Dump(); + LogInfo::MapleLogger() << "the new insn is:\n"; + } + insn.SetOperand(opndIndex, *opnd); + DecRef(*origInfos.at(opndIndex)); + /* Update the actual expression info. */ + origInfos.at(opndIndex) = opndInfo; + if (EBO_DUMP) { + insn.Dump(); + } + } #endif - /* forward prop for registers. */ - if (!opnd->IsConstant() && - (!beforeRegAlloc || (HasAssignedReg(*oldOpnd) == HasAssignedReg(*opndReplace)) || opnd->IsConstReg() || - !insn.IsMove()) && - (opndInfo != nullptr) && - ((insn.GetResultNum() == 0) || - (((insn.GetResult(0) != nullptr) && !RegistersIdentical(*opnd, *(insn.GetResult(0)))) || !beforeRegAlloc)) && - (beforeRegAlloc || !IsFrameReg(*oldOpnd)) && !insn.IsDestRegAlsoSrcReg() && - ((IsOfSameClass(*oldOpnd, *opndReplace) && (oldOpnd->GetSize() <= opndReplace->GetSize())) || - IsMovToSIMDVmov(insn, *origInfos.at(opndIndex)->insn))) { - /* Copies to and from the same register are not needed. */ - if (!beforeRegAlloc && insn.IsEffectiveCopy() && (insn.CopyOperands() == opndIndex) && - RegistersIdentical(*opnd, *(insn.GetResult(0)))) { - if (EBO_DUMP) { - LogInfo::MapleLogger() << "===replace operand " << opndIndex << " of insn: \n"; - insn.Dump(); - LogInfo::MapleLogger() << "===Remove the new insn because Copies to and from the same register. \n"; - } - return true; - } - - if (EBO_DUMP) { - LogInfo::MapleLogger() << "===replace operand " << opndIndex << " of insn: \n"; - insn.Dump(); - LogInfo::MapleLogger() << "the new insn is:\n"; - } - DecRef(*origInfos.at(opndIndex)); - insn.SetOperand(opndIndex, *opnd); - - if (EBO_DUMP) { - insn.Dump(); - } - IncRef(*opndInfo); - /* Update the actual expression info. */ - origInfos.at(opndIndex) = opndInfo; - /* extend the live range of the replacement operand. */ - if ((opndInfo->bb != insn.GetBB()) && opnd->IsRegister()) { - MarkOpndLiveIntoBB(*opnd, *insn.GetBB(), *opndInfo->bb); - } + /* forward prop for registers. */ + if (!RegForwardCheck(insn, *opnd, opndReplace, *oldOpnd, origInfos.at(opndIndex))) { + return false; + } + /* Copies to and from the same register are not needed. */ + if (!beforeRegAlloc && insn.IsEffectiveCopy() && (insn.CopyOperands() == opndIndex) && + RegistersIdentical(*opnd, *(insn.GetResult(0)))) { + if (EBO_DUMP) { + LogInfo::MapleLogger() << "===replace operand " << opndIndex << " of insn: \n"; + insn.Dump(); + LogInfo::MapleLogger() << "===Remove the new insn because Copies to and from the same register. \n"; } + return true; } + if (EBO_DUMP) { + LogInfo::MapleLogger() << "===replace operand " << opndIndex << " of insn: \n"; + insn.Dump(); + LogInfo::MapleLogger() << "the new insn is:\n"; + } + DecRef(*origInfos.at(opndIndex)); + insn.SetOperand(opndIndex, *opnd); + + if (EBO_DUMP) { + insn.Dump(); + } + IncRef(*opndInfo); + /* Update the actual expression info. */ + origInfos.at(opndIndex) = opndInfo; + /* extend the live range of the replacement operand. */ + if ((opndInfo->bb != insn.GetBB()) && opnd->IsRegister()) { + MarkOpndLiveIntoBB(*opnd, *insn.GetBB(), *opndInfo->bb); + } return false; } @@ -1270,7 +1309,7 @@ AnalysisResult *CgDoEbo::Run(CGFunc *cgFunc, CgFuncResultMgr *cgFuncResultMgr) { ebo = eboMp->New(*cgFunc, *eboMp, live, true, PhaseName()); #endif #if TARGARM32 - ebo = eboMp->New(*cgFunc, *eboMp, live, false, PhaseName()); + ebo = eboMp->New(*cgFunc, *eboMp, live, true, PhaseName()); #endif ebo->Run(); /* the live range info may changed, so invalid the info. */ @@ -1296,7 +1335,7 @@ AnalysisResult *CgDoEbo1::Run(CGFunc *cgFunc, CgFuncResultMgr *cgFuncResultMgr) ebo = eboMp->New(*cgFunc, *eboMp, live, true, PhaseName()); #endif #if TARGARM32 - ebo = eboMp->New(*cgFunc, *eboMp, live, false, PhaseName()); + ebo = eboMp->New(*cgFunc, *eboMp, live, true, PhaseName()); #endif ebo->Run(); /* the live range info may changed, so invalid the info. */ diff --git a/src/maple_be/src/cg/eh_func.cpp b/src/maple_be/src/cg/eh_func.cpp index 01e4554e7285dbc92c2b1602f9c472d932869f5f..64efb310c09ed6e4064cb6c27e7fff3477cb440f 100644 --- a/src/maple_be/src/cg/eh_func.cpp +++ b/src/maple_be/src/cg/eh_func.cpp @@ -297,6 +297,9 @@ void EHFunc::CreateTypeInfoSt() { } const auto *classType = static_cast(mirFunc.GetClassType()); + if (cgFunc->GetMirModule().IsCModule() && classType == nullptr) { + return; + } ASSERT(classType != nullptr, ""); if (classType->GetMethods().empty() && (classType->GetFieldsSize() == 0)) { return; diff --git a/src/maple_driver/defs/phases.def b/src/maple_driver/defs/phases.def index 0b9e0b60f2c1e0206e9392cd7f16c11bbcd2d6ab..66aa557bf7f73b80b2c3621dc612fca20cc0048e 100644 --- a/src/maple_driver/defs/phases.def +++ b/src/maple_driver/defs/phases.def @@ -18,17 +18,17 @@ ADD_PHASE("clone", true) ADD_PHASE("classhierarchy", true) ADD_PHASE("callgraph", true) ADD_PHASE("vtableanalysis", true) -ADD_PHASE("reflectionanalysis", true) -ADD_PHASE("gencheckcast", true) -ADD_PHASE("javaintrnlowering", true) +ADD_PHASE("reflectionanalysis", JAVALANG) +ADD_PHASE("gencheckcast", JAVALANG) +ADD_PHASE("javaintrnlowering", JAVALANG) ADD_PHASE("analyzector", true) // mephase begin ADD_PHASE("bypatheh", MeOption::optLevel == 2) ADD_PHASE("loopcanon", MeOption::optLevel == 2) ADD_PHASE("splitcriticaledge", MeOption::optLevel == 2) -ADD_PHASE("ssatab", true) -ADD_PHASE("aliasclass", true) -ADD_PHASE("ssa", true) +ADD_PHASE("ssatab", MeOption::optLevel == 2 || JAVALANG) +ADD_PHASE("aliasclass", MeOption::optLevel == 2 || JAVALANG) +ADD_PHASE("ssa", MeOption::optLevel == 2 || JAVALANG) ADD_PHASE("dse", MeOption::optLevel == 2) ADD_PHASE("abcopt", MeOption::optLevel == 2) ADD_PHASE("ssadevirt", MeOption::optLevel == 2) @@ -39,16 +39,16 @@ ADD_PHASE("condbasednpc", MeOption::optLevel == 2) ADD_PHASE("epre", MeOption::optLevel == 2) ADD_PHASE("stmtpre", MeOption::optLevel == 2) ADD_PHASE("analyzerc", MeOption::optLevel == 2) -ADD_PHASE("rclowering", true) +ADD_PHASE("rclowering", JAVALANG) ADD_PHASE("rename2preg", MeOption::optLevel == 2) //ADD_PHASE("lpre", MeOption::optLevel == 2) ADD_PHASE("pregrename", MeOption::optLevel == 2) -ADD_PHASE("emit", true) +ADD_PHASE("emit", MeOption::optLevel == 2 || JAVALANG) // mephase end ADD_PHASE("GenNativeStubFunc", true) ADD_PHASE("clinit", true) ADD_PHASE("VtableImpl", true) ADD_PHASE("CodeReLayout", MeOption::optLevel == 2) -ADD_PHASE("javaehlower", true) -ADD_PHASE("MUIDReplacement", true) -ADD_PHASE("ConstantFold", true) +ADD_PHASE("javaehlower", JAVALANG) +ADD_PHASE("MUIDReplacement", JAVALANG) +ADD_PHASE("ConstantFold", JAVALANG) diff --git a/src/maple_driver/include/option_parser.h b/src/maple_driver/include/option_parser.h index 4d77f95437c4cd4cc0d99f31c6b73cd696b57884..eee758260b769c292b6407d0c9b3e95327529235 100644 --- a/src/maple_driver/include/option_parser.h +++ b/src/maple_driver/include/option_parser.h @@ -56,7 +56,7 @@ class OptionParser { void PrintUsage(const std::string &helpType, const unsigned int helpLevel = kBuildTypeDefault) const; private: - bool HandleKeyValue(const std::string &key, const std::string &value, bool isValueEmpty, + bool HandleKeyValue(const std::string &key, const std::string &value, std::vector &inputOption, const std::string &exeName, bool isAllOption = true); bool CheckOpt(const std::string option, std::string &lastKey, bool &isLastMatch, @@ -71,6 +71,7 @@ class OptionParser { std::multimap usages; std::vector