diff --git a/src/mapleall/bin/dex2mpl b/src/mapleall/bin/dex2mpl
index 9ea6c7dd2f63f6568fb83d7dc956feef56671642..6e040c68fcfb4861dd36182bfc875ad202cd75de 100755
Binary files a/src/mapleall/bin/dex2mpl and b/src/mapleall/bin/dex2mpl differ
diff --git a/src/mapleall/bin/dex2mpl_android b/src/mapleall/bin/dex2mpl_android
index d603acde6e5f9bd8f7ab425f8bec336c43dff2a0..856422861ffa925617793ba0fbf48fe94fc63418 100755
Binary files a/src/mapleall/bin/dex2mpl_android and b/src/mapleall/bin/dex2mpl_android differ
diff --git a/src/mapleall/bin/jbc2mpl b/src/mapleall/bin/jbc2mpl
index e11d55a4cad3bce421a3dc6f64502240d2962d91..de92b2c81fb448c66b8dd1a24fbb3576ba3e0cc6 100755
Binary files a/src/mapleall/bin/jbc2mpl and b/src/mapleall/bin/jbc2mpl differ
diff --git a/src/mapleall/maple_be/include/be/becommon.h b/src/mapleall/maple_be/include/be/becommon.h
index 5591048061acd79cf07459dfda5cf0ef8c26b3a7..3179894ace3f7b5c60f850ae87fde3f4a775520f 100644
--- a/src/mapleall/maple_be/include/be/becommon.h
+++ b/src/mapleall/maple_be/include/be/becommon.h
@@ -122,7 +122,7 @@ class BECommon {
     return (funcReturnType.at(&func));
   }
 
-  void AddElementToFuncReturnType(MIRFunction &func, TyIdx tyIdx);
+  void AddElementToFuncReturnType(MIRFunction &func, const TyIdx tyIdx);
 
   MIRType *BeGetOrCreatePointerType(const MIRType &pointedType);
 
@@ -197,11 +197,12 @@ class BECommon {
   void AddTypeAlign(uint8 value) {
     typeAlignTable.emplace_back(value);
   }
+
   bool GetHasFlexibleArray(uint32 idx) const {
-    return typeAlignTable.at(idx);
+    return typeHasFlexibleArray.at(idx);
   }
   void SetHasFlexibleArray(uint32 idx, bool value) {
-    typeAlignTable.at(idx) = value;
+    typeHasFlexibleArray.at(idx) = value;
   }
 
   FieldID GetStructFieldCount(uint32 idx) const {
@@ -240,7 +241,7 @@ class BECommon {
    * Note: currently only for java class types.
    */
   MapleUnorderedMap<MIRClassType*, JClassLayout*> jClassLayoutTable;
-  MapleUnorderedMap<MIRFunction *, TyIdx> funcReturnType;
+  MapleUnorderedMap<MIRFunction*, TyIdx> funcReturnType;
 }; /* class BECommon */
 }  /* namespace maplebe */
 
diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h
index 977a9b7c5183bb4e6b386f6b8d485a7111066c96..9c51f64378e69815415de40d75516aa2090ccb91 100644
--- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h
+++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h
@@ -116,7 +116,8 @@ class AArch64CGFunc : public CGFunc {
   Operand *SelectAddrof(AddrofNode &expr) override;
   Operand &SelectAddrofFunc(AddroffuncNode &expr) override;
 
-  PrimType GetDestTypeFromAggSize(uint32 bitSize);
+  PrimType GetDestTypeFromAggSize(uint32 bitSize) const;
+
   Operand *SelectIread(const BaseNode &parent, IreadNode &expr) override;
 
   Operand *SelectIntConst(MIRIntConst &intConst) override;
@@ -600,7 +601,7 @@ class AArch64CGFunc : public CGFunc {
   bool GenerateCompareWithZeroInstruction(Opcode jmpOp, Opcode cmpOp, bool is64Bits,
                                           LabelOperand &targetOpnd, Operand &opnd0);
   void GenCVaStartIntrin(RegOperand &opnd, uint32 stkSize);
-  void SelectCVaStart(IntrinsiccallNode &intrnNode);
+  void SelectCVaStart(const IntrinsiccallNode &intrnNode);
   void SelectMPLClinitCheck(IntrinsiccallNode&);
   void SelectMPLProfCounterInc(IntrinsiccallNode &intrnNode);
   /* Helper functions for translating complex Maple IR instructions/inrinsics */
diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_memlayout.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_memlayout.h
index d4bfa3a21a0665326a3efee8c405ab56232602f4..7058782c48b93426c3ba72263df683b642cbaaf3 100644
--- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_memlayout.h
+++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_memlayout.h
@@ -167,7 +167,7 @@ class AArch64MemLayout : public MemLayout {
     segGrSaveArea.SetSize(sz);
   }
 
-  int32 GetSizeOfGRSaveArea() {
+  int32 GetSizeOfGRSaveArea() const {
     return segGrSaveArea.GetSize();
   }
 
@@ -175,7 +175,7 @@ class AArch64MemLayout : public MemLayout {
     segVrSaveArea.SetSize(sz);
   }
 
-  int32 GetSizeOfVRSaveArea() {
+  int32 GetSizeOfVRSaveArea() const {
     return segVrSaveArea.GetSize();
   }
 
diff --git a/src/mapleall/maple_be/include/cg/emit.h b/src/mapleall/maple_be/include/cg/emit.h
index 6b0540b44858cfa39b594d0f0555bfd5ff0a4754..3d920ec90d357a096b1129925671e6d4f30f95ac 100644
--- a/src/mapleall/maple_be/include/cg/emit.h
+++ b/src/mapleall/maple_be/include/cg/emit.h
@@ -284,7 +284,7 @@ class Emitter {
   const AsmInfo *asmInfo;
   std::ofstream outStream;
   MemPool *memPool;
-  uint16 arraySize;
+  uint32 arraySize;
   bool isFlexibleArray;
 #if 1/* REQUIRE TO SEPERATE TARGAARCH64 TARGARM32 */
 /* Following code is under TARGAARCH64 condition */
diff --git a/src/mapleall/maple_be/src/be/becommon.cpp b/src/mapleall/maple_be/src/be/becommon.cpp
index 7e8fbadd314cfe8accf184a17611623a2913d653..ba35b57fc31150765f7ac83267b2acfcd6ce19dd 100644
--- a/src/mapleall/maple_be/src/be/becommon.cpp
+++ b/src/mapleall/maple_be/src/be/becommon.cpp
@@ -160,7 +160,7 @@ void BECommon::ComputeStructTypeSizesAligns(MIRType &ty, const TyIdx &tyIdx) {
      * Last struct element of a struct with more than one member
      * is a flexible array if it is an array of size 0.
      */
-    if ((j != 0) && ((j+1) == fields.size()) &&
+    if ((j != 0) && ((j + 1) == fields.size()) &&
         (fieldType->GetKind() == kTypeArray) &&
         (GetTypeSize(fieldTyIdx.GetIdx()) == 0)) {
       SetHasFlexibleArray(tyIdx.GetIdx(), true);
@@ -611,7 +611,7 @@ void BECommon::AddElementToJClassLayout(MIRClassType &klass, JClassFieldInfo inf
   layout.emplace_back(info);
 }
 
-void BECommon::AddElementToFuncReturnType(MIRFunction &func, TyIdx tyIdx) {
+void BECommon::AddElementToFuncReturnType(MIRFunction &func, const TyIdx tyIdx) {
   TyIdx &ty = funcReturnType.at(&func);
   ty = tyIdx;
 }
diff --git a/src/mapleall/maple_be/src/be/lower.cpp b/src/mapleall/maple_be/src/be/lower.cpp
index 340f1522188e18b29d3a5b79ed0b16027c879db4..36f85a18a5354372913dae64f4ecb47558fbb1e9 100644
--- a/src/mapleall/maple_be/src/be/lower.cpp
+++ b/src/mapleall/maple_be/src/be/lower.cpp
@@ -1186,7 +1186,8 @@ StmtNode *CGLowerer::LowerCall(CallNode &callNode, StmtNode *&nextStmt, BlockNod
     MIRPtrType *pretType = static_cast<MIRPtrType*>((calleeFunc->GetNthParamType(0)));
     CHECK_FATAL(pretType != nullptr, "nullptr is not expected");
     retType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(pretType->GetPointedTyIdx());
-    CHECK_FATAL((retType->GetKind() == kTypeStruct) || (retType->GetKind() == kTypeUnion), "make sure retType is a struct type");
+    CHECK_FATAL((retType->GetKind() == kTypeStruct) || (retType->GetKind() == kTypeUnion),
+        "make sure retType is a struct type");
   }
 
   /* if return type is not of a struct, return */
diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp
index b4aa9d83b45b2ca4c5d6d246563905d07ec90bdd..eb6d4105c95ae61d05e53cce9c89b84131e8de5a 100644
--- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp
+++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp
@@ -859,7 +859,7 @@ void AArch64CGFunc::SelectDassign(StIdx stIdx, FieldID fieldId, PrimType rhsPTyp
   }
 
   ASSERT(((type->GetKind() == kTypeScalar) || (type->GetKind() == kTypePointer) ||
-      (type->GetKind() == kTypeStruct) || (type->GetKind() == kTypeArray)), "NYI dassign type");
+          (type->GetKind() == kTypeStruct) || (type->GetKind() == kTypeArray)), "NYI dassign type");
   PrimType ptyp = type->GetPrimType();
   if (ptyp == PTY_agg) {
     ptyp = PTY_a64;
@@ -1196,7 +1196,7 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) {
     bool parmCopy = IsParamStructCopy(*rhsSymbol);
     for (uint32 i = 0; i < (lhsSize / alignUsed); ++i) {
       /* generate the load */
-      Operand *rhsMemOpnd;
+      Operand *rhsMemOpnd = nullptr;
       if (parmCopy) {
         rhsMemOpnd = &LoadStructCopyBase(*rhsSymbol, rhsOffset + i * alignUsed, alignUsed * k8BitSize);
       } else {
@@ -1387,7 +1387,7 @@ void AArch64CGFunc::SelectAddrof(Operand &result, StImmOperand &stImm) {
         }
       }
     } else {
-      // Do not cache modified symbol location
+      /* Do not cache modified symbol location */
       offset = &CreateImmOperand(GetBaseOffset(*symLoc) + stImm.GetOffset(), k64BitSize, false);
     }
 
@@ -1431,8 +1431,8 @@ Operand *AArch64CGFunc::SelectAddrof(AddrofNode &expr) {
   int32 offset = 0;
   if (expr.GetFieldID() != 0) {
     MIRStructType *structType = static_cast<MIRStructType*>(symbol->GetType());
-    // with array of structs, it is possible to have nullptr
-    if (structType) {
+    /* with array of structs, it is possible to have nullptr */
+    if (structType != nullptr) {
       offset = GetBecommon().GetFieldOffset(*structType, expr.GetFieldID()).first;
     }
   }
@@ -1460,7 +1460,7 @@ Operand *AArch64CGFunc::SelectAddrof(AddrofNode &expr) {
     if (offset == 0) {
       return structAddr;
     } else {
-      // add the struct offset to the base address
+      /* add the struct offset to the base address */
       Operand *result = &CreateVirtualRegisterOperand(NewVReg(kRegTyInt, k8ByteSize));
       ImmOperand *imm = &CreateImmOperand(PTY_a64, offset);
       GetCurBB()->AppendInsn(GetCG()->BuildInstruction<AArch64Insn>(MOP_xaddrri12, *result, *structAddr, *imm));
@@ -1500,23 +1500,29 @@ Operand &AArch64CGFunc::SelectAddrofFunc(AddroffuncNode &expr) {
 }
 
 /* For an entire aggregate that can fit inside a single 8 byte register.  */
-PrimType AArch64CGFunc::GetDestTypeFromAggSize(uint32 bitSize) {
+PrimType AArch64CGFunc::GetDestTypeFromAggSize(uint32 bitSize) const {
+  PrimType primType;
   switch (bitSize) {
-  case 8:
-    return PTY_u8;
-    break;
-  case 16:
-    return PTY_u16;
-    break;
-  case 32:
-    return PTY_u32;
-    break;
-  case 64:
-    return PTY_u64;
-    break;
-  default:
-    CHECK_FATAL(false, "aggregate of unhandled size");
+    case k8BitSize: {
+      primType = PTY_u8;
+      break;
+    }
+    case k16BitSize: {
+      primType = PTY_u16;
+      break;
+    }
+    case k32BitSize: {
+      primType = PTY_u32;
+      break;
+    }
+    case k64BitSize: {
+      primType = PTY_u64;
+      break;
+    }
+    default:
+      CHECK_FATAL(false, "aggregate of unhandled size");
   }
+  return primType;
 }
 
 Operand *AArch64CGFunc::SelectIread(const BaseNode &parent, IreadNode &expr) {
@@ -4663,36 +4669,38 @@ void AArch64CGFunc::HandleRCCall(bool begin, const MIRSymbol *retRef) {
 
 void AArch64CGFunc::SelectParmListDreadSmallAggregate(MIRSymbol &sym, AArch64ListOperand &srcOpnds,
                                                       ParmLocator &parmLocator) {
-  // in two param regs if possible
-  // If struct is <= 8 bytes, then it fits into one param reg.
-  // If struct is <= 16 bytes, then it fits into two param regs.
-  // Otherwise, it goes onto the stack.
-  // If the number of available param reg is less than what is
-  // needed to fit the entire struct into them, then the param
-  // reg is skipped and the struct goes onto the stack.
-  // Example 1.
-  //  struct size == 8 bytes.
-  //  param regs x0 to x6 are used.
-  //  struct is passed in x7.
-  // Example 2.
-  //  struct is 16 bytes.
-  //  param regs x0 to x5 are used.
-  //  struct is passed in x6 and x7.
-  // Example 3.
-  //  struct is 16 bytes.
-  //  param regs x0 to x6 are used.  x7 alone is not enough to pass the struct.
-  //  struct is passed on the stack.
-  //  x7 is not used, as the following param will go onto the stack also.
+  /*
+   * in two param regs if possible
+   * If struct is <= 8 bytes, then it fits into one param reg.
+   * If struct is <= 16 bytes, then it fits into two param regs.
+   * Otherwise, it goes onto the stack.
+   * If the number of available param reg is less than what is
+   * needed to fit the entire struct into them, then the param
+   * reg is skipped and the struct goes onto the stack.
+   * Example 1.
+   *  struct size == 8 bytes.
+   *  param regs x0 to x6 are used.
+   *  struct is passed in x7.
+   * Example 2.
+   *  struct is 16 bytes.
+   *  param regs x0 to x5 are used.
+   *  struct is passed in x6 and x7.
+   * Example 3.
+   *  struct is 16 bytes.
+   *  param regs x0 to x6 are used.  x7 alone is not enough to pass the struct.
+   *  struct is passed on the stack.
+   *  x7 is not used, as the following param will go onto the stack also.
+   */
   MIRType *ty = sym.GetType();
   int32 symSize = GetBecommon().GetTypeSize(ty->GetTypeIndex().GetIdx());
   PLocInfo ploc;
   parmLocator.LocateNextParm(*ty, ploc);
   if (ploc.reg0 == 0) {
-    // No param regs available, pass on stack.
-    // If symSize is <= 8 bytes then use 1 reg, else 2
+    /* No param regs available, pass on stack. */
+    /* If symSize is <= 8 bytes then use 1 reg, else 2 */
     CreateCallStructParamPassByStack(symSize, &sym, nullptr, ploc.memOffset);
   } else {
-    // pass by param regs.
+    /* pass by param regs. */
     MemOperand &mopnd0 = GetOrCreateMemOpnd(sym, 0, k64BitSize);
     CreateCallStructParamPassByReg(ploc.reg0, mopnd0, srcOpnds);
     if (ploc.reg1) {
@@ -4716,7 +4724,7 @@ void AArch64CGFunc::SelectParmListIreadSmallAggregate(const BaseNode &argExpr, A
     /* No param regs available, pass on stack. */
     CreateCallStructParamPassByStack(symSize, nullptr, addrOpnd, ploc.memOffset);
   } else {
-    // pass by param regs.
+    /* pass by param regs. */
     AArch64OfstOperand *offopnd = &GetOrCreateOfstOpnd(0, k32BitSize);
     MemOperand *mopnd;
     mopnd = &GetOrCreateMemOpnd(AArch64MemOperand::kAddrModeBOi, k64BitSize, addrOpnd, nullptr, offopnd, nullptr);
@@ -4731,29 +4739,31 @@ void AArch64CGFunc::SelectParmListIreadSmallAggregate(const BaseNode &argExpr, A
 
 void AArch64CGFunc::SelectParmListDreadLargeAggregate(MIRSymbol &sym, AArch64ListOperand &srcOpnds,
                                                       ParmLocator &parmLocator, int32 &structCopyOffset) {
-  // Pass larger sized struct on stack.
-  // Need to copy the entire structure onto the stack.
-  // The pointer to the starting address of the copied struct is then
-  // used as the parameter for the struct.
-  // This pointer is passed as the next parameter.
-  // Example 1:
-  //  struct is 23 bytes.
-  //  param regs x0 to x5 are used.
-  //  First around up 23 to 24, so 3 of 8-byte slots.
-  //  Copy struct to a created space on the stack.
-  //  Pointer of copied struct is passed in x6.
-  // Example 2:
-  //  struct is 25 bytes.
-  //  param regs x0 to x7 are used.
-  //  First around up 25 to 32, so 4 of 8-byte slots.
-  //  Copy struct to a created space on the stack.
-  //  Pointer of copied struct is passed on stack as the 9th parameter.
+  /*
+   * Pass larger sized struct on stack.
+   * Need to copy the entire structure onto the stack.
+   * The pointer to the starting address of the copied struct is then
+   * used as the parameter for the struct.
+   * This pointer is passed as the next parameter.
+   * Example 1:
+   * struct is 23 bytes.
+   * param regs x0 to x5 are used.
+   * First around up 23 to 24, so 3 of 8-byte slots.
+   * Copy struct to a created space on the stack.
+   * Pointer of copied struct is passed in x6.
+   * Example 2:
+   * struct is 25 bytes.
+   * param regs x0 to x7 are used.
+   * First around up 25 to 32, so 4 of 8-byte slots.
+   * Copy struct to a created space on the stack.
+   * Pointer of copied struct is passed on stack as the 9th parameter.
+   */
   MIRType *ty = sym.GetType();
   int32 symSize = GetBecommon().GetTypeSize(ty->GetTypeIndex().GetIdx());
   PLocInfo ploc;
   parmLocator.LocateNextParm(*ty, ploc);
-  uint32 numMemOp = RoundUp(symSize, kSizeOfPtr) / kSizeOfPtr; // round up
-  // Create the struct copies.
+  uint32 numMemOp = static_cast<uint32>(RoundUp(symSize, kSizeOfPtr) / kSizeOfPtr); /* round up */
+  /* Create the struct copies. */
   AArch64RegOperand *parmOpnd = CreateCallStructParamCopyToStack(numMemOp, &sym, nullptr, structCopyOffset, ploc.reg0);
   srcOpnds.PushOpnd(*parmOpnd);
   structCopyOffset += (numMemOp * kSizeOfPtr);
@@ -4769,7 +4779,7 @@ void AArch64CGFunc::SelectParmListIreadLargeAggregate(const BaseNode &argExpr, A
   addrOpnd = &LoadIntoRegister(*addrOpnd, iread.Opnd(0)->GetPrimType());
   PLocInfo ploc;
   parmLocator.LocateNextParm(*ty, ploc);
-  uint32 numMemOp = RoundUp(symSize, kSizeOfPtr) / kSizeOfPtr; // round up
+  uint32 numMemOp = static_cast<uint32>(RoundUp(symSize, kSizeOfPtr) / kSizeOfPtr); /* round up */
   AArch64RegOperand *parmOpnd;
   parmOpnd = CreateCallStructParamCopyToStack(numMemOp, nullptr, addrOpnd, structCopyOffset, ploc.reg0);
   structCopyOffset += (numMemOp * kSizeOfPtr);
@@ -4779,13 +4789,13 @@ void AArch64CGFunc::SelectParmListIreadLargeAggregate(const BaseNode &argExpr, A
 void AArch64CGFunc::CreateCallStructParamPassByStack(int32 symSize, MIRSymbol *sym,
                                                      RegOperand *addrOpnd, int32 baseOffset) {
   MemOperand *ldmopnd, *stmopnd;
-  uint32 numRegNeeded = (symSize <= k8ByteSize) ? kOneRegister : kTwoRegister;
+  int numRegNeeded = (symSize <= k8ByteSize) ? kOneRegister : kTwoRegister;
   for (int j = 0; j < numRegNeeded; j++) {
     if (sym) {
-      ldmopnd = &GetOrCreateMemOpnd(*sym, (j * kSizeOfPtr), k64BitSize);
+      ldmopnd = &GetOrCreateMemOpnd(*sym, (j * static_cast<int>(kSizeOfPtr)), k64BitSize);
     } else {
       ldmopnd = &GetOrCreateMemOpnd(AArch64MemOperand::kAddrModeBOi, k64BitSize, addrOpnd, nullptr,
-                    &GetOrCreateOfstOpnd(j * kSizeOfPtr, k32BitSize), nullptr);
+          &GetOrCreateOfstOpnd(static_cast<uint32>(j) * kSizeOfPtr, k32BitSize), nullptr);
     }
     RegOperand *vreg = &CreateVirtualRegisterOperand(NewVReg(kRegTyInt, k8ByteSize));
     GetCurBB()->AppendInsn(cg->BuildInstruction<AArch64Insn>(PickLdInsn(k64BitSize, PTY_i64), *vreg, *ldmopnd));
@@ -4802,14 +4812,14 @@ void AArch64CGFunc::CreateCallStructParamPassByReg(AArch64reg reg, MemOperand &m
 
 AArch64RegOperand *AArch64CGFunc::CreateCallStructParamCopyToStack(uint32 numMemOp, MIRSymbol *sym, RegOperand *addrOpd,
                                                                    int32 copyOffset, AArch64reg reg) {
-  // Create the struct copies.
+  /* Create the struct copies. */
   MemOperand *ldmopnd, *stmopnd;
   for (int j = 0; j < numMemOp; j++) {
     if (sym) {
-      ldmopnd = &GetOrCreateMemOpnd(*sym, (j * kSizeOfPtr), k64BitSize);
+      ldmopnd = &GetOrCreateMemOpnd(*sym, (j * static_cast<int>(kSizeOfPtr)), k64BitSize);
     } else {
       ldmopnd = &GetOrCreateMemOpnd(AArch64MemOperand::kAddrModeBOi, k64BitSize, addrOpd, nullptr,
-                    &GetOrCreateOfstOpnd(j * kSizeOfPtr, k32BitSize), nullptr);
+          &GetOrCreateOfstOpnd(static_cast<uint32>(j) * kSizeOfPtr, k32BitSize), nullptr);
     }
     RegOperand *vreg = &CreateVirtualRegisterOperand(NewVReg(kRegTyInt, k8ByteSize));
     GetCurBB()->AppendInsn(cg->BuildInstruction<AArch64Insn>(PickLdInsn(k64BitSize, PTY_i64), *vreg, *ldmopnd));
@@ -4817,7 +4827,7 @@ AArch64RegOperand *AArch64CGFunc::CreateCallStructParamCopyToStack(uint32 numMem
     stmopnd = &CreateMemOpnd(RSP, (copyOffset + (j * kSizeOfPtr)), k64BitSize);
     GetCurBB()->AppendInsn(cg->BuildInstruction<AArch64Insn>(PickStInsn(k64BitSize, PTY_i64), *vreg, *stmopnd));
   }
-  // Create the copy address parameter for the struct
+  /* Create the copy address parameter for the struct */
   AArch64RegOperand *parmOpnd = &GetOrCreatePhysicalRegisterOperand(reg, k64BitSize, kRegTyInt);
   AArch64ImmOperand *offset = &CreateImmOperand(copyOffset, k64BitSize, false);
   RegOperand *fpopnd = &GetOrCreatePhysicalRegisterOperand(RSP, k64BitSize, kRegTyInt);
@@ -4828,7 +4838,7 @@ AArch64RegOperand *AArch64CGFunc::CreateCallStructParamCopyToStack(uint32 numMem
 
 void AArch64CGFunc::SelectParmListForAggregate(BaseNode &argExpr, AArch64ListOperand &srcOpnds,
                                                ParmLocator &parmLocator, int32 &structCopyOffset) {
-  int32 symSize;
+  uint64 symSize;
   if (argExpr.GetOpCode() == OP_dread) {
     DreadNode &dread = static_cast<DreadNode &>(argExpr);
     MIRSymbol *sym = GetBecommon().GetMIRModule().CurFunction()->GetLocalOrGlobalSymbol(dread.GetStIdx());
@@ -5128,10 +5138,10 @@ void AArch64CGFunc::GenerateIntrnInsnForStrIndexOf(BB &bb, RegOperand &srcString
   MOperator lsrOp = (bitSize == k64BitSize) ? MOP_xlsrrri6 : MOP_wlsrrri5;
   bb.AppendInsn(GetCG()->BuildInstruction<AArch64Insn>(lsrOp, srcLengthOpnd, srcCountOpnd, immValueOne));
 #ifdef USE_32BIT_REF
-  const int64 stringBaseObjSize = 16;  // shadow(4)+monitor(4)+count(4)+hash(4)
+  const int64 stringBaseObjSize = 16;  /* shadow(4)+monitor(4)+count(4)+hash(4) */
 #else
-  const int64 stringBaseObjSize = 20;  // shadow(8)+monitor(4)+count(4)+hash(4)
-#endif  // USE_32BIT_REF
+  const int64 stringBaseObjSize = 20;  /* shadow(8)+monitor(4)+count(4)+hash(4) */
+#endif  /* USE_32BIT_REF */
   PrimType pty = (srcString.GetSize() == k64BitSize) ? PTY_i64 : PTY_i32;
   ImmOperand &immStringBaseOffset = CreateImmOperand(pty, stringBaseObjSize);
   MOperator addOp = (pty == PTY_i64) ? MOP_xaddrri12 : MOP_waddrri12;
@@ -5576,10 +5586,10 @@ MemOperand &AArch64CGFunc::GetOrCreateMemOpnd(const MIRSymbol &symbol, int32 off
     } else {
       StImmOperand &stOpnd = CreateStImmOperand(symbol, offset, 0);
       AArch64RegOperand &stAddrOpnd = static_cast<AArch64RegOperand&>(CreateRegisterOperandOfType(PTY_u64));
-      //  adrp    x1, _PTR__cinf_Ljava_2Flang_2FSystem_3B
+      /* adrp    x1, _PTR__cinf_Ljava_2Flang_2FSystem_3B */
       Insn &insn = GetCG()->BuildInstruction<AArch64Insn>(MOP_xadrp, stAddrOpnd, stOpnd);
       GetCurBB()->AppendInsn(insn);
-      //  ldr     x1, [x1, #:lo12:_PTR__cinf_Ljava_2Flang_2FSystem_3B]
+      /* ldr     x1, [x1, #:lo12:_PTR__cinf_Ljava_2Flang_2FSystem_3B] */
       return *memPool->New<AArch64MemOperand>(AArch64MemOperand::kAddrModeLo12Li, size, stAddrOpnd, nullptr,
                                               &GetOrCreateOfstOpnd(offset, k32BitSize), &symbol);
     }
@@ -6373,13 +6383,12 @@ void AArch64CGFunc::SelectMPLClinitCheck(IntrinsiccallNode &intrnNode) {
     GetCurBB()->AppendInsn(newInsn);
   }
 }
-
 void AArch64CGFunc::GenCVaStartIntrin(RegOperand &opnd, uint32 stkSize) {
-  // FPLR only pushed in regalloc() after intrin function
+  /* FPLR only pushed in regalloc() after intrin function */
   Operand &stkOpnd = GetOrCreatePhysicalRegisterOperand(RFP, k64BitSize, kRegTyInt);
 
-  // __stack
-  AArch64ImmOperand *offsOpnd = &CreateImmOperand(0, k64BitSize, true, kUnAdjustVary); // isvary reset StackFrameSize
+  /* __stack */
+  AArch64ImmOperand *offsOpnd = &CreateImmOperand(0, k64BitSize, true, kUnAdjustVary); /* isvary reset StackFrameSize */
   AArch64ImmOperand *offsOpnd2 = &CreateImmOperand(stkSize, k64BitSize, false);
   RegOperand &vReg = CreateVirtualRegisterOperand(NewVReg(kRegTyInt, GetPrimTypeSize(PTY_a64)));
   if (stkSize) {
@@ -6389,67 +6398,70 @@ void AArch64CGFunc::GenCVaStartIntrin(RegOperand &opnd, uint32 stkSize) {
     SelectAdd(vReg, stkOpnd, *offsOpnd, PTY_a64);
   }
   AArch64OfstOperand *offOpnd = &GetOrCreateOfstOpnd(0, k64BitSize);
+  /* mem operand in va_list struct (lhs) */
   MemOperand *strOpnd = &GetOrCreateMemOpnd(AArch64MemOperand::kAddrModeBOi, k64BitSize, &opnd, nullptr,
-                         offOpnd, static_cast<MIRSymbol *>(nullptr)); // mem operand in va_list struct (lhs)
+                                            offOpnd, static_cast<MIRSymbol*>(nullptr));
   GetCurBB()->AppendInsn(GetCG()->BuildInstruction<AArch64Insn>(MOP_xstr, vReg, *strOpnd));
 
-  // __gr_top   ; it's the same as __stack before the 1st va_arg
+  /* __gr_top   ; it's the same as __stack before the 1st va_arg */
   offOpnd = &GetOrCreateOfstOpnd(k8BitSize, k64BitSize);
   strOpnd = &GetOrCreateMemOpnd(AArch64MemOperand::kAddrModeBOi, k64BitSize, &opnd, nullptr,
-                                offOpnd, static_cast<MIRSymbol *>(nullptr));
+                                offOpnd, static_cast<MIRSymbol*>(nullptr));
   SelectAdd(vReg, stkOpnd, *offsOpnd, PTY_a64);
   GetCurBB()->AppendInsn(GetCG()->BuildInstruction<AArch64Insn>(MOP_xstr, vReg, *strOpnd));
 
-  // __vr_top
-  int32 grAreaSize = static_cast<AArch64MemLayout *>(GetMemlayout())->GetSizeOfGRSaveArea();
-  offsOpnd2 = &CreateImmOperand(RoundUp(grAreaSize, kSizeOfPtr*2), k64BitSize, false);
-  SelectSub(vReg, *offsOpnd, *offsOpnd2, PTY_a64);  // if 1st opnd is register => sub
+  /* __vr_top */
+  int32 grAreaSize = static_cast<AArch64MemLayout*>(GetMemlayout())->GetSizeOfGRSaveArea();
+  offsOpnd2 = &CreateImmOperand(RoundUp(grAreaSize, kSizeOfPtr * 2), k64BitSize, false);
+  SelectSub(vReg, *offsOpnd, *offsOpnd2, PTY_a64);  /* if 1st opnd is register => sub */
   SelectAdd(vReg, stkOpnd, vReg, PTY_a64);
   offOpnd = &GetOrCreateOfstOpnd(k16BitSize, k64BitSize);
   strOpnd = &GetOrCreateMemOpnd(AArch64MemOperand::kAddrModeBOi, k64BitSize, &opnd, nullptr,
-                               offOpnd, static_cast<MIRSymbol *>(nullptr));
+                                offOpnd, static_cast<MIRSymbol*>(nullptr));
   GetCurBB()->AppendInsn(GetCG()->BuildInstruction<AArch64Insn>(MOP_xstr, vReg, *strOpnd));
 
-  // __gr_offs
+  /* __gr_offs */
   int32 offs = 0 - grAreaSize;
   offsOpnd = &CreateImmOperand(offs, k32BitSize, false);
-  RegOperand *tmpReg = &CreateRegisterOperandOfType(PTY_i32); // offs value to be assigned (rhs)
+  RegOperand *tmpReg = &CreateRegisterOperandOfType(PTY_i32); /* offs value to be assigned (rhs) */
   SelectCopyImm(*tmpReg, *offsOpnd, PTY_i32);
-  offOpnd = &GetOrCreateOfstOpnd(3*kSizeOfPtr, k32BitSize);
+  offOpnd = &GetOrCreateOfstOpnd(kSizeOfPtr * 3, k32BitSize);
   strOpnd = &GetOrCreateMemOpnd(AArch64MemOperand::kAddrModeBOi, k32BitSize, &opnd, nullptr,
-                                offOpnd, static_cast<MIRSymbol *>(nullptr));
+                                offOpnd, static_cast<MIRSymbol*>(nullptr));
   GetCurBB()->AppendInsn(GetCG()->BuildInstruction<AArch64Insn>(MOP_wstr, *tmpReg, *strOpnd));
 
-  // __vr_offs
-  offs = 0 - static_cast<AArch64MemLayout *>(GetMemlayout())->GetSizeOfVRSaveArea();
+  /* __vr_offs */
+  offs = 0 - static_cast<AArch64MemLayout*>(GetMemlayout())->GetSizeOfVRSaveArea();
   offsOpnd = &CreateImmOperand(offs, k32BitSize, false);
   tmpReg = &CreateRegisterOperandOfType(PTY_i32);
   SelectCopyImm(*tmpReg, *offsOpnd, PTY_i32);
-  offOpnd = &GetOrCreateOfstOpnd(3*kSizeOfPtr+sizeof(int32), k32BitSize);
+  offOpnd = &GetOrCreateOfstOpnd((kSizeOfPtr * 3 + sizeof(int32)), k32BitSize);
   strOpnd = &GetOrCreateMemOpnd(AArch64MemOperand::kAddrModeBOi, k32BitSize, &opnd, nullptr,
-                               offOpnd, static_cast<MIRSymbol *>(nullptr));
+                                offOpnd, static_cast<MIRSymbol*>(nullptr));
   GetCurBB()->AppendInsn(GetCG()->BuildInstruction<AArch64Insn>(MOP_wstr, *tmpReg, *strOpnd));
 }
 
-void AArch64CGFunc::SelectCVaStart(IntrinsiccallNode &intrnNode) {
+void AArch64CGFunc::SelectCVaStart(const IntrinsiccallNode &intrnNode) {
   ASSERT(intrnNode.NumOpnds() == 2, "must be 2 operands");
-  // 2 operands, but only 1 needed. Don't need to emit code for second operand
-
-  // va_list is a passed struct with an address, load its address
+  /* 2 operands, but only 1 needed. Don't need to emit code for second operand
+   *
+   * va_list is a passed struct with an address, load its address
+   */
   BaseNode *argExpr = intrnNode.Opnd(0);
   Operand *opnd = HandleExpr(intrnNode, *argExpr);
-  RegOperand &opnd0 = LoadIntoRegister(*opnd, PTY_a64);  // first argument of intrinsic
+  RegOperand &opnd0 = LoadIntoRegister(*opnd, PTY_a64);  /* first argument of intrinsic */
 
-  // Find beginning of unnamed arg on stack.
-  // Ex. void foo(int i1, int i2, ... int i8, struct S r, struct S s, ...)
-  //     where struct S has size 32, address of r and s are on stack but they are named.
+  /* Find beginning of unnamed arg on stack.
+   * Ex. void foo(int i1, int i2, ... int i8, struct S r, struct S s, ...)
+   *     where struct S has size 32, address of r and s are on stack but they are named.
+   */
   ParmLocator parmLocator(GetBecommon());
   PLocInfo pLoc;
   uint32 stkSize = 0;
   for (uint32 i = 0; i < GetFunction().GetFormalCount(); i++) {
     MIRType *ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(GetFunction().GetNthParamTyIdx(i));
     parmLocator.LocateNextParm(*ty, pLoc);
-    if (pLoc.reg0 == kRinvalid) {  // on stack
+    if (pLoc.reg0 == kRinvalid) {  /* on stack */
       stkSize = pLoc.memOffset + pLoc.memSize;
     }
   }
@@ -6676,12 +6688,12 @@ RegType AArch64CGFunc::GetRegisterType(regno_t reg) const {
 }
 
 MemOperand &AArch64CGFunc::LoadStructCopyBase(const MIRSymbol &symbol, int32 offset, int dataSize) {
-  // For struct formals > 16 bytes, this is the pointer to the struct copy.
-  // Load the base pointer first.
+  /* For struct formals > 16 bytes, this is the pointer to the struct copy. */
+  /* Load the base pointer first. */
   RegOperand *vreg = &CreateVirtualRegisterOperand(NewVReg(kRegTyInt, k8ByteSize));
   MemOperand *baseMemOpnd = &GetOrCreateMemOpnd(symbol, 0, k64BitSize);
   GetCurBB()->AppendInsn(GetCG()->BuildInstruction<AArch64Insn>(PickLdInsn(k64BitSize, PTY_i64), *vreg, *baseMemOpnd));
-  // Create the indirect load mem opnd from the base pointer.
+  /* Create the indirect load mem opnd from the base pointer. */
   return CreateMemOpnd(*vreg, offset, dataSize);
 }
 }  /* namespace maplebe */
diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp
index d1bfbb382f1d84dc87bf8cd39d927b487805b151..ed1a646e11bca89078ebe4cbfb4ffc11ca582524 100644
--- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp
+++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp
@@ -115,7 +115,7 @@ void AArch64MemLayout::LayoutVarargParams() {
       if (i == 0) {
         if (be.HasFuncReturnType(*func)) {
           TyIdx tidx = be.GetFuncReturnType(*func);
-          if (be.GetTypeSize(tidx.GetIdx()) <= 16) {
+          if (be.GetTypeSize(tidx.GetIdx()) <= k16ByteSize) {
             continue;
           }
         }
@@ -138,7 +138,7 @@ void AArch64MemLayout::LayoutVarargParams() {
       }
     }
     SetSizeOfGRSaveArea((k8BitSize - nIntRegs) * kSizeOfPtr);
-    SetSizeOfVRSaveArea((k8BitSize - nFpRegs) * kSizeOfPtr * 2);
+    SetSizeOfVRSaveArea((k8BitSize - nFpRegs) * kSizeOfPtr * k2ByteSize);
   }
 }
 
@@ -423,5 +423,4 @@ int32 AArch64MemLayout::GetVRSaveAreaBaseLoc() {
   total -= SizeOfArgsToStackPass();
   return total;
 }
-
 }  /* namespace maplebe */
diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp
index 8f2ddb4a5bd409663e5caad2aed9a1e58848aadb..df0cae410d6b0649658ddf951935fb5ae9e65172 100644
--- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp
+++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_proepilog.cpp
@@ -19,6 +19,7 @@ namespace maplebe {
 using namespace maple;
 
 namespace {
+constexpr uint32 k2BitSize = 2;
 constexpr int32 kSoeChckOffset = 8192;
 
 enum RegsPushPop : uint8 {
@@ -99,8 +100,9 @@ void AArch64GenProEpilog::GenStackGuard(BB &bb) {
 
     int32 stkSize = static_cast<AArch64MemLayout*>(cgFunc.GetMemlayout())->RealStackFrameSize() -
                     static_cast<AArch64MemLayout*>(cgFunc.GetMemlayout())->SizeOfArgsToStackPass() - vArea;
-    AArch64MemOperand *downStk = aarchCGFunc.GetMemoryPool()->New<AArch64MemOperand>(RFP,
-    stkSize - kOffset8MemPos - vArea, kSizeOfPtr * kBitsPerByte);
+    AArch64MemOperand *downStk =
+        aarchCGFunc.GetMemoryPool()->New<AArch64MemOperand>(RFP, stkSize - kOffset8MemPos - vArea,
+                                                            kSizeOfPtr * kBitsPerByte);
     if (downStk->GetMemVaryType() == kNotVary &&
         aarchCGFunc.IsImmediateOffsetOutOfRange(*downStk, k64BitSize)) {
       downStk = &aarchCGFunc.SplitOffsetWithAddInstruction(*downStk, k64BitSize, R10);
@@ -159,8 +161,9 @@ BB &AArch64GenProEpilog::GenStackGuardCheckInsn(BB &bb) {
       aarchCGFunc.GetOrCreatePhysicalRegisterOperand(R10, kSizeOfPtr * kBitsPerByte, kRegTyInt);
   int32 stkSize = static_cast<AArch64MemLayout*>(cgFunc.GetMemlayout())->RealStackFrameSize() -
                   static_cast<AArch64MemLayout*>(cgFunc.GetMemlayout())->SizeOfArgsToStackPass() - vArea;
-  AArch64MemOperand *downStk = aarchCGFunc.GetMemoryPool()->New<AArch64MemOperand>
-                               (RFP, stkSize - kOffset8MemPos - vArea, kSizeOfPtr * kBitsPerByte);
+  AArch64MemOperand *downStk =
+      aarchCGFunc.GetMemoryPool()->New<AArch64MemOperand>(RFP, stkSize - kOffset8MemPos - vArea,
+                                                          kSizeOfPtr * kBitsPerByte);
   if (downStk->GetMemVaryType() == kNotVary && aarchCGFunc.IsImmediateOffsetOutOfRange(*downStk, k64BitSize)) {
     downStk = &aarchCGFunc.SplitOffsetWithAddInstruction(*static_cast<AArch64MemOperand*>(downStk), k64BitSize, R10);
   }
@@ -573,10 +576,10 @@ void AArch64GenProEpilog::GeneratePushRegs() {
                  cgFunc.GetMemlayout()->SizeOfArgsToStackPass();
 
   if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) {
-    // GR/VR save areas are above the callee save area
+    /* GR/VR save areas are above the callee save area */
     AArch64MemLayout *ml = static_cast<AArch64MemLayout *>(cgFunc.GetMemlayout());
-    int saveareasize = RoundUp(ml->GetSizeOfGRSaveArea(), kSizeOfPtr*2) +
-                       RoundUp(ml->GetSizeOfVRSaveArea(), kSizeOfPtr*2);
+    int saveareasize = RoundUp(ml->GetSizeOfGRSaveArea(), kSizeOfPtr * k2BitSize) +
+                       RoundUp(ml->GetSizeOfVRSaveArea(), kSizeOfPtr * k2BitSize);
     offset -= saveareasize;
   }
 
@@ -623,28 +626,30 @@ void AArch64GenProEpilog::GeneratePushUnnamedVarargRegs() {
     uint32 dataSizeBits = kSizeOfPtr * kBitsPerByte;
     int32 offset = memlayout->GetGRSaveAreaBaseLoc();
     if (memlayout->GetSizeOfGRSaveArea() % kAarch64StackPtrAlignment) {
-      offset += kSizeOfPtr;  // End of area should be aligned. Hole between VR and GR area
+      offset += kSizeOfPtr;  /* End of area should be aligned. Hole between VR and GR area */
     }
-    int32 start_regno = 8 - (memlayout->GetSizeOfGRSaveArea() / kSizeOfPtr);
-    ASSERT(start_regno <= 8, "Incorrect starting GR regno for GR Save Area");
-    for (uint32 i = start_regno + (uint32)R0; i < (uint32)R8; i++) {
+    int32 start_regno = k8BitSize - (memlayout->GetSizeOfGRSaveArea() / kSizeOfPtr);
+    ASSERT(start_regno <= k8BitSize, "Incorrect starting GR regno for GR Save Area");
+    for (uint32 i = start_regno + static_cast<uint32>(R0); i < static_cast<uint32>(R8); i++) {
       Operand &stackloc = aarchCGFunc.CreateStkTopOpnd(offset, dataSizeBits);
-      RegOperand &reg = aarchCGFunc.GetOrCreatePhysicalRegisterOperand((AArch64reg)i, 64, kRegTyInt);
-      Insn &inst = currCG->BuildInstruction<AArch64Insn>(
-                     aarchCGFunc.PickStInsn(dataSizeBits, PTY_i64), reg, stackloc);
+      RegOperand &reg =
+          aarchCGFunc.GetOrCreatePhysicalRegisterOperand(static_cast<AArch64reg>(i), k64BitSize, kRegTyInt);
+      Insn &inst =
+          currCG->BuildInstruction<AArch64Insn>(aarchCGFunc.PickStInsn(dataSizeBits, PTY_i64), reg, stackloc);
       cgFunc.GetCurBB()->AppendInsn(inst);
       offset += kSizeOfPtr;
     }
     offset = memlayout->GetVRSaveAreaBaseLoc();
-    start_regno = 8 - (memlayout->GetSizeOfVRSaveArea() / (kSizeOfPtr * 2));
-    ASSERT(start_regno <= 8, "Incorrect starting GR regno for VR Save Area");
-    for (uint32 i = start_regno + (uint32)V0; i < (uint32)V8; i++) {
+    start_regno = k8BitSize - (memlayout->GetSizeOfVRSaveArea() / (kSizeOfPtr * k2BitSize));
+    ASSERT(start_regno <= k8BitSize, "Incorrect starting GR regno for VR Save Area");
+    for (uint32 i = start_regno + static_cast<uint32>(V0); i < static_cast<uint32>(V8); i++) {
       Operand &stackloc = aarchCGFunc.CreateStkTopOpnd(offset, dataSizeBits);
-      RegOperand &reg = aarchCGFunc.GetOrCreatePhysicalRegisterOperand((AArch64reg)i, 64, kRegTyInt);
-      Insn &inst = currCG->BuildInstruction<AArch64Insn>(
-                     aarchCGFunc.PickStInsn(dataSizeBits, PTY_i64), reg, stackloc);
+      RegOperand &reg =
+          aarchCGFunc.GetOrCreatePhysicalRegisterOperand(static_cast<AArch64reg>(i), k64BitSize, kRegTyInt);
+      Insn &inst =
+          currCG->BuildInstruction<AArch64Insn>(aarchCGFunc.PickStInsn(dataSizeBits, PTY_i64), reg, stackloc);
       cgFunc.GetCurBB()->AppendInsn(inst);
-      offset += (kSizeOfPtr * 2);
+      offset += (kSizeOfPtr * k2BitSize);
     }
   }
 }
@@ -956,10 +961,10 @@ void AArch64GenProEpilog::GeneratePopRegs() {
                  cgFunc.GetMemlayout()->SizeOfArgsToStackPass();
 
   if (cgFunc.GetMirModule().IsCModule() && cgFunc.GetFunction().GetAttr(FUNCATTR_varargs)) {
-    // GR/VR save areas are above the callee save area
+    /* GR/VR save areas are above the callee save area */
     AArch64MemLayout *ml = static_cast<AArch64MemLayout *>(cgFunc.GetMemlayout());
-    int saveareasize = RoundUp(ml->GetSizeOfGRSaveArea(), kSizeOfPtr*2) +
-                       RoundUp(ml->GetSizeOfVRSaveArea(), kSizeOfPtr*2);
+    int saveareasize = RoundUp(ml->GetSizeOfGRSaveArea(), kSizeOfPtr * k2BitSize) +
+                       RoundUp(ml->GetSizeOfVRSaveArea(), kSizeOfPtr * k2BitSize);
     offset -= saveareasize;
   }
 
diff --git a/src/mapleall/maple_be/src/cg/emit.cpp b/src/mapleall/maple_be/src/cg/emit.cpp
index 749761e97727893c972da6a31d9dc688bd81ea6a..89aa2bf9dc66a0db4bc48b84234095725d721577 100644
--- a/src/mapleall/maple_be/src/cg/emit.cpp
+++ b/src/mapleall/maple_be/src/cg/emit.cpp
@@ -237,6 +237,7 @@ void Emitter::EmitAsmLabel(const MIRSymbol &mirSymbol, AsmLabel label) {
   if (Globals::GetInstance()->GetBECommon()->IsEmptyOfTypeAlignTable()) {
     ASSERT(false, "container empty check");
   }
+
   switch (label) {
     case kAsmGlbl: {
       Emit(asmInfo->GetGlobal());
@@ -265,9 +266,10 @@ void Emitter::EmitAsmLabel(const MIRSymbol &mirSymbol, AsmLabel label) {
     case kAsmComm: {
       std::string size;
       if (isFlexibleArray) {
-        size = std::to_string(Globals::GetInstance()->GetBECommon()->GetTypeSize(mirType->GetTypeIndex()) + arraySize);
+          size = std::to_string(
+              Globals::GetInstance()->GetBECommon()->GetTypeSize(mirType->GetTypeIndex()) + arraySize);
       } else {
-        size = std::to_string(Globals::GetInstance()->GetBECommon()->GetTypeSize(mirType->GetTypeIndex()));
+          size = std::to_string(Globals::GetInstance()->GetBECommon()->GetTypeSize(mirType->GetTypeIndex()));
       }
       Emit(asmInfo->GetComm());
       Emit(symName);
@@ -276,7 +278,7 @@ void Emitter::EmitAsmLabel(const MIRSymbol &mirSymbol, AsmLabel label) {
       Emit(", ");
 #if PECOFF
       std::string align = std::to_string(
-          static_cast<int>(log2(Globals::GetInstance()->GetBECommon()->GetTypeAlign(mirType->GetTypeIndex()))));
+        static_cast<int>(log2(Globals::GetInstance()->GetBECommon()->GetTypeAlign(mirType->GetTypeIndex()))));
       emit(align);
 #else /* ELF */
       /* output align, symbol name begin with "classInitProtectRegion" align is 4096 */
@@ -310,9 +312,10 @@ void Emitter::EmitAsmLabel(const MIRSymbol &mirSymbol, AsmLabel label) {
     case kAsmSize: {
       std::string size;
       if (isFlexibleArray) {
-        size = std::to_string(Globals::GetInstance()->GetBECommon()->GetTypeSize(mirType->GetTypeIndex()) + arraySize);
+          size = std::to_string(
+              Globals::GetInstance()->GetBECommon()->GetTypeSize(mirType->GetTypeIndex()) + arraySize);
       } else {
-        size = std::to_string(Globals::GetInstance()->GetBECommon()->GetTypeSize(mirType->GetTypeIndex()));
+          size = std::to_string(Globals::GetInstance()->GetBECommon()->GetTypeSize(mirType->GetTypeIndex()));
       }
       Emit(asmInfo->GetSize());
       Emit(symName);
@@ -403,7 +406,7 @@ void Emitter::EmitStrConstant(const MIRStrConst &mirStrConst) {
    */
   const char *str = GlobalTables::GetUStrTable().GetStringFromStrIdx(mirStrConst.GetValue()).c_str();
   if (isFlexibleArray) {
-    arraySize += strlen(str) + k1ByteSize;
+      arraySize += static_cast<uint32>(strlen(str)) + k1ByteSize;
   }
   constexpr int bufSize = 6;
   while (*str) {
@@ -480,7 +483,7 @@ void Emitter::EmitScalarConstant(MIRConst &mirConst, bool newLine, bool flag32)
       }
       Emit(intCt.GetValue());
       if (isFlexibleArray) {
-        arraySize += (sizeInBits / kBitsPerByte);
+          arraySize += (sizeInBits / kBitsPerByte);
       }
       break;
     }
@@ -489,7 +492,7 @@ void Emitter::EmitScalarConstant(MIRConst &mirConst, bool newLine, bool flag32)
       EmitAsmLabel(asmName);
       Emit(std::to_string(floatCt.GetIntValue()));
       if (isFlexibleArray) {
-        arraySize += k4ByteFloatSize;
+          arraySize += k4ByteFloatSize;
       }
       break;
     }
@@ -498,7 +501,7 @@ void Emitter::EmitScalarConstant(MIRConst &mirConst, bool newLine, bool flag32)
       EmitAsmLabel(asmName);
       Emit(std::to_string(doubleCt.GetIntValue()));
       if (isFlexibleArray) {
-        arraySize += k8ByteDoubleSize;
+          arraySize += k8ByteDoubleSize;
       }
       break;
     }
@@ -1405,8 +1408,8 @@ void Emitter::EmitStructConstant(MIRConst &mirConst) {
   uint32 fieldIdx = 1;
   for (uint32 i = 0; i < num; ++i) {
     if (((i + 1) == num) && cg->GetMIRModule()->GetSrcLang() == kSrcLangC) {
-      isFlexibleArray = Globals::GetInstance()->GetBECommon()->GetHasFlexibleArray(mirType.GetTypeIndex().GetIdx());
-      arraySize = 0;
+        isFlexibleArray = Globals::GetInstance()->GetBECommon()->GetHasFlexibleArray(mirType.GetTypeIndex().GetIdx());
+        arraySize = 0;
     }
     MIRConst *elemConst = structCt.GetAggConstElement(fieldIdx);
     MIRType &elemType = *structType.GetElemType(i);
diff --git a/src/mapleall/maple_ir/include/mir_type.h b/src/mapleall/maple_ir/include/mir_type.h
index cfe24c8a353fa275613160bbf3ab887098872d81..7d3ff9fdd8d4b16dc2b5dde91348e251971cdd91 100755
--- a/src/mapleall/maple_ir/include/mir_type.h
+++ b/src/mapleall/maple_ir/include/mir_type.h
@@ -397,7 +397,7 @@ class GenericAttrs {
 constexpr size_t kShiftNumOfTypeKind = 8;
 constexpr size_t kShiftNumOfNameStrIdx = 6;
 
-class MIRStructType;
+class MIRStructType; // circular dependency exists, no other choice
 
 class MIRType {
  public:
@@ -522,9 +522,12 @@ class MIRType {
     constexpr uint8 idxShift = 2;
     return ((static_cast<uint32>(primType) << idxShift) + (typeKind << kShiftNumOfTypeKind)) % kTypeHashLength;
   }
+
   virtual bool HasFields() const { return false; }
-  virtual size_t NumberOfFieldIDs() { return 0; } // total number of field IDs the type is consisted of, excluding its own field ID
-  virtual MIRStructType *EmbeddedStructType() { return nullptr; }  // return any struct type directly embedded in this type
+  // total number of field IDs the type is consisted of, excluding its own field ID
+  virtual size_t NumberOfFieldIDs() const { return 0; }
+  // return any struct type directly embedded in this type
+  virtual MIRStructType *EmbeddedStructType() { return nullptr; }
 
  protected:
   MIRTypeKind typeKind;
@@ -680,8 +683,9 @@ class MIRArrayType : public MIRType {
   std::string GetMplTypeName() const override;
   std::string GetCompactMplTypeName() const override;
   bool HasFields() const override;
-  size_t NumberOfFieldIDs() override;
+  size_t NumberOfFieldIDs() const override;
   MIRStructType *EmbeddedStructType() override;
+
  private:
   TyIdx eTyIdx{ 0 };
   uint16 dim = 0;
@@ -729,7 +733,7 @@ class MIRFarrayType : public MIRType {
   std::string GetCompactMplTypeName() const override;
 
   bool HasFields() const override;
-  size_t NumberOfFieldIDs() override;
+  size_t NumberOfFieldIDs() const override;
   MIRStructType *EmbeddedStructType() override;
 
  private:
@@ -1091,7 +1095,7 @@ class MIRStructType : public MIRType {
   }
 
   bool HasFields() const override { return true; }
-  size_t NumberOfFieldIDs() override;
+  size_t NumberOfFieldIDs() const override;
   MIRStructType *EmbeddedStructType() override { return this; }
 
   virtual FieldPair TraverseToFieldRef(FieldID &fieldID) const;
@@ -1311,7 +1315,7 @@ class MIRClassType : public MIRStructType {
            kTypeHashLength;
   }
 
-  size_t NumberOfFieldIDs() override;
+  size_t NumberOfFieldIDs() const override;
 
  private:
   TyIdx parentTyIdx{ 0 };
@@ -1428,7 +1432,7 @@ class MIRInterfaceType : public MIRStructType {
   }
 
   bool HasFields() const override { return false; }
-  size_t NumberOfFieldIDs() override { return 0; }
+  size_t NumberOfFieldIDs() const override { return 0; }
   MIRStructType *EmbeddedStructType() override { return nullptr; }
 
  private:
diff --git a/src/mapleall/maple_ir/src/mir_type.cpp b/src/mapleall/maple_ir/src/mir_type.cpp
index 260f6bb7d60a3a7784024040da2e13de797b40fc..8b32577ebea129ba29ff440f094092803340116b 100755
--- a/src/mapleall/maple_ir/src/mir_type.cpp
+++ b/src/mapleall/maple_ir/src/mir_type.cpp
@@ -494,22 +494,22 @@ void MIRFuncType::Dump(int indent, bool dontUseName) const {
   LogInfo::MapleLogger() << ">";
 }
 
-static constexpr uint64 RoundUpConst(uint64 offset, uint8 align) {
+static constexpr uint64 RoundUpConst(uint64 offset, uint32 align) {
   return (-align) & (offset + align - 1);
 }
 
-static inline uint64 RoundUp(uint64 offset, uint8 align) {
+static inline uint64 RoundUp(uint64 offset, uint32 align) {
   if (align == 0) {
     return offset;
   }
   return RoundUpConst(offset, align);
 }
 
-static constexpr uint64 RoundDownConst(uint64 offset, uint8 align) {
+static constexpr uint64 RoundDownConst(uint64 offset, uint32 align) {
   return (-align) & offset;
 }
 
-static inline uint64 RoundDown(uint64 offset, uint8 align) {
+static inline uint64 RoundDown(uint64 offset, uint32 align) {
   if (align == 0) {
     return offset;
   }
@@ -523,7 +523,7 @@ size_t MIRArrayType::GetSize() const {
   }
   elemsize = RoundUp(elemsize, typeAttrs.GetAlign());
   size_t numelems = sizeArray[0];
-  for (int i = 1; i < dim; i++) {
+  for (uint16 i = 1; i < dim; i++) {
     numelems *= sizeArray[i];
   }
   return elemsize * numelems;
@@ -979,34 +979,35 @@ size_t MIRStructType::GetSize() const {
   // since there may be bitfields, perform a layout process for the fields
   size_t byteOfst = 0;
   size_t bitOfst = 0;
+  constexpr uint32 bitNumPerByte = 8;
+  constexpr uint32 shiftNum = 3;
   for (size_t i = 0; i < fields.size(); ++i) {
-    TyIdxFieldAttrPair tfap = GetFieldTyIdxAttrPair(i);
+    TyIdxFieldAttrPair tfap = GetFieldTyIdxAttrPair(static_cast<FieldID>(i));
     MIRType *fieldType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(tfap.first);
     if (fieldType->GetKind() != kTypeBitField) {
-      if (byteOfst * 8 < bitOfst) {
-        byteOfst = (bitOfst >> 3) + 1;
+      if (byteOfst * bitNumPerByte < bitOfst) {
+        byteOfst = (bitOfst >> shiftNum) + 1;
       }
       byteOfst = RoundUp(byteOfst, std::max(fieldType->GetAlign(), tfap.second.GetAlign()));
       byteOfst += fieldType->GetSize();
-      bitOfst = byteOfst * 8;
+      bitOfst = byteOfst * bitNumPerByte;
     } else {
-      MIRBitFieldType *bitfType = static_cast<MIRBitFieldType *>(fieldType);
+      MIRBitFieldType *bitfType = static_cast<MIRBitFieldType*>(fieldType);
       if (bitfType->GetFieldSize() == 0) {  // special case, for aligning purpose
         bitOfst = RoundUp(bitOfst, GetPrimTypeBitSize(bitfType->GetPrimType()));
-        byteOfst = bitOfst >> 3;
+        byteOfst = bitOfst >> shiftNum;
       } else {
         if (RoundDown(bitOfst + bitfType->GetFieldSize() - 1, GetPrimTypeBitSize(bitfType->GetPrimType())) !=
             RoundDown(bitOfst, GetPrimTypeBitSize(bitfType->GetPrimType()))) {
           bitOfst = RoundUp(bitOfst, GetPrimTypeBitSize(bitfType->GetPrimType()));
-          byteOfst = bitOfst >> 3;
         }
         bitOfst += bitfType->GetFieldSize();
-        byteOfst = bitOfst >> 3;
+        byteOfst = bitOfst >> shiftNum;
       }
     }
   }
-  if (byteOfst * 8 < bitOfst) {
-    byteOfst = (bitOfst >> 3) + 1;
+  if (byteOfst * bitNumPerByte < bitOfst) {
+    byteOfst = (bitOfst >> shiftNum) + 1;
   }
   byteOfst = RoundUp(byteOfst, GetAlign());
   if (byteOfst == 0 && isCPlusPlus) {
@@ -1019,7 +1020,7 @@ uint32 MIRStructType::GetAlign() const {
   if (fields.size() == 0) {
     return 0;
   }
-  uint8 maxAlign = 1;
+  uint32 maxAlign = 1;
   for (size_t i = 0; i < fields.size(); ++i) {
     TyIdxFieldAttrPair tfap = GetFieldTyIdxAttrPair(i);
     MIRType *fieldType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(tfap.first);
@@ -1251,7 +1252,7 @@ bool MIRArrayType::HasFields() const {
   return elemType->HasFields();
 }
 
-size_t MIRArrayType::NumberOfFieldIDs() {
+size_t MIRArrayType::NumberOfFieldIDs() const {
   MIRType *elemType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(eTyIdx);
   return elemType->NumberOfFieldIDs();
 }
@@ -1287,7 +1288,7 @@ bool MIRFarrayType::HasFields() const {
   return elemType->HasFields();
 }
 
-size_t MIRFarrayType::NumberOfFieldIDs() {
+size_t MIRFarrayType::NumberOfFieldIDs() const {
   MIRType *elemType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(elemTyIdx);
   return elemType->NumberOfFieldIDs();
 }
@@ -1318,8 +1319,12 @@ bool MIRStructType::EqualTo(const MIRType &type) const {
   if (type.GetKind() != typeKind) {
     return false;
   }
-  const MIRStructType *p = dynamic_cast<const MIRStructType*>(&type);
-  CHECK_FATAL(p != nullptr, "p is null in MIRStructType::EqualTo");
+  if (type.GetNameStrIdx() != nameStrIdx) {
+    return false;
+  }
+
+  ASSERT(type.IsStructType(), "p is null in MIRStructType::EqualTo");
+  const MIRStructType *p = static_cast<const MIRStructType*>(&type);
   if (fields != p->fields) {
     return false;
   }
@@ -1582,7 +1587,7 @@ bool MIRInterfaceType::HasTypeParam() const {
   return false;
 }
 
-size_t MIRClassType::NumberOfFieldIDs() {
+size_t MIRClassType::NumberOfFieldIDs() const {
   size_t parentFieldIDs = 0;
   if (parentTyIdx != TyIdx(0)) {
     MIRType *parentty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(parentTyIdx);
@@ -1650,7 +1655,7 @@ std::string MIRPtrType::GetCompactMplTypeName() const {
   return pointedType->GetCompactMplTypeName();
 }
 
-size_t MIRStructType::NumberOfFieldIDs() {
+size_t MIRStructType::NumberOfFieldIDs() const {
   size_t count = 0;
   for (FieldPair curpair : fields) {
     count++;
diff --git a/src/mapleall/maple_me/include/me_builder.h b/src/mapleall/maple_me/include/me_builder.h
index 603b58b85b2f3e55eff54bf53ecc097739246200..eccd25ffbc0c54a210acc6759d69879070f6fc26 100644
--- a/src/mapleall/maple_me/include/me_builder.h
+++ b/src/mapleall/maple_me/include/me_builder.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) [2019-2020] Huawei Technologies Co.,Ltd.All rights reserved.
+ * Copyright (c) [2019-2021] Huawei Technologies Co.,Ltd.All rights reserved.
  *
  * OpenArkCompiler is licensed under Mulan PSL v2.
  * You can use this software according to the terms and conditions of the Mulan PSL v2.
diff --git a/src/mapleall/maple_me/include/me_ir.h b/src/mapleall/maple_me/include/me_ir.h
index a76dea2e011cfe73ac53d46442d00529dd630072..4ef064ba4eb6b75d36f4ba218b5fc9395dcee096 100755
--- a/src/mapleall/maple_me/include/me_ir.h
+++ b/src/mapleall/maple_me/include/me_ir.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) [2019-2020] Huawei Technologies Co.,Ltd.All rights reserved.
+ * Copyright (c) [2019-2021] Huawei Technologies Co.,Ltd.All rights reserved.
  *
  * OpenArkCompiler is licensed under Mulan PSL v2.
  * You can use this software according to the terms and conditions of the Mulan PSL v2.
@@ -165,6 +165,7 @@ class MeExpr {
 
  private:
   MeExpr *FindSymAppearance(OStIdx oidx);  // find the appearance of the symbol
+  bool IsDexMerge() const;
 
   Opcode op;
   PrimType primType;
@@ -373,9 +374,17 @@ class VarMeExpr final : public ScalarMeExpr {
     noDelegateRC = noDelegateRCVal;
   }
 
+  bool GetNoSubsumeRC() const {
+    return noSubsumeRC;
+  }
+
+  void SetNoSubsumeRC(bool noSubsumeRCVal) {
+    noSubsumeRC = noSubsumeRCVal;
+  }
 
  private:
   bool noDelegateRC = false;  // true if this cannot be optimized by delegaterc
+  bool noSubsumeRC = false;   // true if this cannot be optimized by subsumrc
   FieldID fieldID = 0;
   TyIdx inferredTyIdx{ 0 }; /* Non zero if it has a known type (allocation type is seen). */
   MapleVector<TyIdx> inferredTypeCandidates;
@@ -468,7 +477,7 @@ class MePhiNode {
 
 class RegMeExpr : public ScalarMeExpr {
  public:
-  RegMeExpr(MapleAllocator *alloc, int32 exprid, PregIdx preg, PUIdx pidx, OStIdx oidx, uint32 vidx, PrimType ptyp)
+  RegMeExpr(int32 exprid, PregIdx preg, PUIdx pidx, OStIdx oidx, uint32 vidx, PrimType ptyp)
       : ScalarMeExpr(exprid, oidx, vidx, kMeOpReg, OP_regread, ptyp),
         regIdx(preg),
         puIdx(pidx) {}
@@ -503,7 +512,9 @@ class RegMeExpr : public ScalarMeExpr {
 
 class ConstMeExpr : public MeExpr {
  public:
-  ConstMeExpr(int32 exprID, MIRConst *constValParam, PrimType t) : MeExpr(exprID, kMeOpConst, OP_constval, t, 0), constVal(constValParam) {}
+  ConstMeExpr(int32 exprID, MIRConst *constValParam, PrimType t)
+      : MeExpr(exprID, kMeOpConst, OP_constval, t, 0), constVal(constValParam) {}
+
   ~ConstMeExpr() = default;
 
   void Dump(const IRMap*, int32 indent = 0) const override;
@@ -552,7 +563,8 @@ class ConstMeExpr : public MeExpr {
 
 class ConststrMeExpr : public MeExpr {
  public:
-  ConststrMeExpr(int32 exprID, UStrIdx idx, PrimType t) : MeExpr(exprID, kMeOpConststr, OP_conststr, t, 0), strIdx(idx) {}
+  ConststrMeExpr(int32 exprID, UStrIdx idx, PrimType t)
+      : MeExpr(exprID, kMeOpConststr, OP_conststr, t, 0), strIdx(idx) {}
 
   ~ConststrMeExpr() = default;
 
@@ -575,7 +587,9 @@ class ConststrMeExpr : public MeExpr {
 
 class Conststr16MeExpr : public MeExpr {
  public:
-  Conststr16MeExpr(int32 exprID, U16StrIdx idx, PrimType t) : MeExpr(exprID, kMeOpConststr16, OP_conststr16, t, 0), strIdx(idx) {}
+  Conststr16MeExpr(int32 exprID, U16StrIdx idx, PrimType t)
+      : MeExpr(exprID, kMeOpConststr16, OP_conststr16, t, 0), strIdx(idx) {}
+
   ~Conststr16MeExpr() = default;
 
   void Dump(const IRMap*, int32 indent = 0) const override;
@@ -597,7 +611,9 @@ class Conststr16MeExpr : public MeExpr {
 
 class SizeoftypeMeExpr : public MeExpr {
  public:
-  SizeoftypeMeExpr(int32 exprid, PrimType t, TyIdx idx) : MeExpr(exprid, kMeOpSizeoftype, OP_sizeoftype, t, 0), tyIdx(idx) {}
+  SizeoftypeMeExpr(int32 exprid, PrimType t, TyIdx idx)
+      : MeExpr(exprid, kMeOpSizeoftype, OP_sizeoftype, t, 0), tyIdx(idx) {}
+
   ~SizeoftypeMeExpr() = default;
 
   void Dump(const IRMap*, int32 indent = 0) const override;
@@ -654,7 +670,8 @@ class FieldsDistMeExpr : public MeExpr {
 
 class AddrofMeExpr : public MeExpr {
  public:
-  AddrofMeExpr(int32 exprid, PrimType t, OStIdx idx) : MeExpr(exprid, kMeOpAddrof, OP_addrof, t, 0), ostIdx(idx), fieldID(0) {}
+  AddrofMeExpr(int32 exprid, PrimType t, OStIdx idx)
+      : MeExpr(exprid, kMeOpAddrof, OP_addrof, t, 0), ostIdx(idx), fieldID(0) {}
 
   ~AddrofMeExpr() = default;
 
@@ -687,7 +704,8 @@ class AddrofMeExpr : public MeExpr {
 
 class AddroffuncMeExpr : public MeExpr {
  public:
-  AddroffuncMeExpr(int32 exprID, PUIdx puIdx) : MeExpr(exprID, kMeOpAddroffunc, OP_addroffunc, PTY_ptr, 0), puIdx(puIdx) {}
+  AddroffuncMeExpr(int32 exprID, PUIdx puIdx)
+      : MeExpr(exprID, kMeOpAddroffunc, OP_addroffunc, PTY_ptr, 0), puIdx(puIdx) {}
 
   ~AddroffuncMeExpr() = default;
 
@@ -712,16 +730,17 @@ class AddroflabelMeExpr : public MeExpr {
  public:
   LabelIdx labelIdx;
 
-  AddroflabelMeExpr(int32 exprid, LabelIdx lidx) : MeExpr(exprid, kMeOpAddroflabel, OP_addroflabel, PTY_ptr, 0), labelIdx(lidx) {}
+  AddroflabelMeExpr(int32 exprid, LabelIdx lidx)
+      : MeExpr(exprid, kMeOpAddroflabel, OP_addroflabel, PTY_ptr, 0), labelIdx(lidx) {}
 
   ~AddroflabelMeExpr() {}
 
   void Dump(const IRMap *, int32 indent = 0) const override;
-  bool IsIdentical(MeExpr *meexpr) {
+  bool IsIdentical(const MeExpr *meexpr) const {
     if (meexpr->GetOp() != GetOp()) {
       return false;
     }
-    const AddroflabelMeExpr *x = static_cast<const AddroflabelMeExpr *>(meexpr);
+    const AddroflabelMeExpr *x = static_cast<const AddroflabelMeExpr*>(meexpr);
     if (labelIdx != x->labelIdx) {
       return false;
     }
@@ -730,13 +749,15 @@ class AddroflabelMeExpr : public MeExpr {
   BaseNode &EmitExpr(SSATab&) override;
 
   uint32 GetHashIndex() const override {
-    return labelIdx << 4;
+    constexpr uint32 shiftNum = 4;
+    return labelIdx << shiftNum;
   }
 };
 
 class GcmallocMeExpr : public MeExpr {
  public:
-  GcmallocMeExpr(int32 exprid, Opcode o, PrimType t, TyIdx tyid) : MeExpr(exprid, kMeOpGcmalloc, o, t, 0), tyIdx(tyid) {}
+  GcmallocMeExpr(int32 exprid, Opcode o, PrimType t, TyIdx tyid)
+      : MeExpr(exprid, kMeOpGcmalloc, o, t, 0), tyIdx(tyid) {}
 
   ~GcmallocMeExpr() = default;
 
@@ -758,7 +779,8 @@ class GcmallocMeExpr : public MeExpr {
 
 class OpMeExpr : public MeExpr {
  public:
-  explicit OpMeExpr(int32 exprID, Opcode o, PrimType t, size_t n) : MeExpr(exprID, kMeOpOp, o, t, n), tyIdx(TyIdx(0)) {}
+  OpMeExpr(int32 exprID, Opcode o, PrimType t, size_t n)
+      : MeExpr(exprID, kMeOpOp, o, t, n), tyIdx(TyIdx(0)) {}
 
   OpMeExpr(const OpMeExpr &opMeExpr, int32 exprID)
       : MeExpr(exprID, kMeOpOp, opMeExpr.GetOp(), opMeExpr.GetPrimType(), opMeExpr.GetNumOpnds()),
@@ -858,7 +880,7 @@ class OpMeExpr : public MeExpr {
 
 class IvarMeExpr : public MeExpr {
  public:
-  explicit IvarMeExpr(int32 exprid, PrimType t, TyIdx tidx, FieldID fid)
+  IvarMeExpr(int32 exprid, PrimType t, TyIdx tidx, FieldID fid)
       : MeExpr(exprid, kMeOpIvar, OP_iread, t, 1), tyIdx(tidx), fieldID(fid) {}
 
   IvarMeExpr(int32 exprid, const IvarMeExpr &ivarme)
@@ -968,8 +990,13 @@ class IvarMeExpr : public MeExpr {
 // for array, intrinsicop and intrinsicopwithtype
 class NaryMeExpr : public MeExpr {
  public:
-  NaryMeExpr(MapleAllocator *alloc, int32 expID, Opcode o, PrimType t, size_t n, TyIdx tyIdx, MIRIntrinsicID intrinID, bool bCheck)
-      : MeExpr(expID, kMeOpNary, o, t, n), tyIdx(tyIdx), intrinsic(intrinID), opnds(alloc->Adapter()), boundCheck(bCheck) {}
+  NaryMeExpr(MapleAllocator *alloc, int32 expID, Opcode o, PrimType t,
+             size_t n, TyIdx tyIdx, MIRIntrinsicID intrinID, bool bCheck)
+      : MeExpr(expID, kMeOpNary, o, t, n),
+        tyIdx(tyIdx),
+        intrinsic(intrinID),
+        opnds(alloc->Adapter()),
+        boundCheck(bCheck) {}
 
   NaryMeExpr(MapleAllocator *alloc, int32 expID, const NaryMeExpr &meExpr)
       : MeExpr(expID, kMeOpNary, meExpr.GetOp(), meExpr.GetPrimType(), meExpr.GetNumOpnds()),
diff --git a/src/mapleall/maple_me/include/preg_renamer.h b/src/mapleall/maple_me/include/preg_renamer.h
index efb979494bed78047a78c92bda353f5c759d497d..a3f7d5fa9059c5e1181bd6b7a5c522aca46e4685 100644
--- a/src/mapleall/maple_me/include/preg_renamer.h
+++ b/src/mapleall/maple_me/include/preg_renamer.h
@@ -1,20 +1,33 @@
+/*
+ * Copyright (c) [2020-2021] Huawei Technologies Co.,Ltd.All rights reserved.
+ *
+ * OpenArkCompiler is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *
+ *     http://license.coscl.org.cn/MulanPSL2
+ *
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+ * FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
 #ifndef MAPLEME_INCLUDE_ME_PREGRENAMER_H
 #define MAPLEME_INCLUDE_ME_PREGRENAMER_H
 #include "me_irmap.h"
 #include "ssa_pre.h"
 
 namespace maple {
-
 class PregRenamer {
  public:
   PregRenamer(MemPool *mp, MeFunction *f, MeIRMap *hmap) : mp(mp), alloc(mp), func(f), meirmap(hmap) {}
-  void RunSelf() const;
+  void RunSelf();
 
  private:
   std::string PhaseName() const {
     return "pregrename";
   }
- private:
+
   MemPool *mp;
   MapleAllocator alloc;
   MeFunction *func;
diff --git a/src/mapleall/maple_me/src/irmap.cpp b/src/mapleall/maple_me/src/irmap.cpp
index 170f2792edad11138dea8febecb89f4da5bf050b..b089f378f5c746a5f220460870673cdb012767dd 100755
--- a/src/mapleall/maple_me/src/irmap.cpp
+++ b/src/mapleall/maple_me/src/irmap.cpp
@@ -19,7 +19,8 @@
 
 namespace maple {
 VarMeExpr *IRMap::CreateVarMeExprVersion(const VarMeExpr &origExpr) {
-  auto *varMeExpr = New<VarMeExpr>(&irMapAlloc, exprID++, origExpr.GetOStIdx(), vst2MeExprTable.size(), origExpr.GetPrimType());
+  auto *varMeExpr = New<VarMeExpr>(&irMapAlloc, exprID++, origExpr.GetOStIdx(),
+                                   vst2MeExprTable.size(), origExpr.GetPrimType());
   vst2MeExprTable.push_back(varMeExpr);
   varMeExpr->SetFieldID(origExpr.GetFieldID());
   return varMeExpr;
@@ -110,14 +111,14 @@ VarMeExpr *IRMap::CreateNewLocalRefVarTmp(GStrIdx strIdx, TyIdx tIdx) {
 }
 
 RegMeExpr *IRMap::CreateRegMeExprVersion(const OriginalSt &pregOSt) {
-  auto *regReadExpr = NewInPool<RegMeExpr>(exprID++, pregOSt.GetPregIdx(), pregOSt.GetPuIdx(),
-                                           pregOSt.GetIndex(), 0, pregOSt.GetMIRPreg()->GetPrimType());
+  auto *regReadExpr = New<RegMeExpr>(exprID++, pregOSt.GetPregIdx(), pregOSt.GetPuIdx(),
+                                     pregOSt.GetIndex(), 0, pregOSt.GetMIRPreg()->GetPrimType());
   return regReadExpr;
 }
 
 RegMeExpr *IRMap::CreateRegMeExprVersion(const RegMeExpr &origExpr) {
-  auto *regReadExpr = NewInPool<RegMeExpr>(exprID++, origExpr.GetRegIdx(), origExpr.GetPuIdx(),
-                                           origExpr.GetOstIdx(), 0, origExpr.GetPrimType());
+  auto *regReadExpr = New<RegMeExpr>(exprID++, origExpr.GetRegIdx(), origExpr.GetPuIdx(),
+                                     origExpr.GetOstIdx(), 0, origExpr.GetPrimType());
   return regReadExpr;
 }
 
@@ -133,7 +134,7 @@ RegMeExpr *IRMap::CreateRefRegMeExpr(const MIRSymbol &mirSt) {
     preg->SetNeedRC();
   }
   OriginalSt *oSt = ssaTab.GetOriginalStTable().CreatePregOriginalSt(regIdx, mirFunc->GetPuidx());
-  auto *regreadexpr = NewInPool<RegMeExpr>(exprID++, regIdx, mirFunc->GetPuidx(), oSt->GetIndex(), 0, pType);
+  auto *regreadexpr = New<RegMeExpr>(exprID++, regIdx, mirFunc->GetPuidx(), oSt->GetIndex(), 0, pType);
   return regreadexpr;
 }
 
@@ -142,7 +143,7 @@ RegMeExpr *IRMap::CreateRegMeExpr(PrimType pType) {
   PregIdx regIdx = mirFunc->GetPregTab()->CreatePreg(pType);
   ASSERT(regIdx <= 0xffff, "register oversized");
   OriginalSt *ost = ssaTab.GetOriginalStTable().CreatePregOriginalSt(regIdx, mirFunc->GetPuidx());
-  auto *regReadExpr = NewInPool<RegMeExpr>(exprID++, regIdx, mirFunc->GetPuidx(), ost->GetIndex(), 0, pType);
+  auto *regReadExpr = New<RegMeExpr>(exprID++, regIdx, mirFunc->GetPuidx(), ost->GetIndex(), 0, pType);
   return regReadExpr;
 }
 
@@ -151,8 +152,8 @@ RegMeExpr *IRMap::CreateRegRefMeExpr(MIRType &mirType) {
   PregIdx regIdx = mirFunc->GetPregTab()->CreatePreg(PTY_ref, &mirType);
   ASSERT(regIdx <= 0xffff, "register oversized");
   OriginalSt *ost = ssaTab.GetOriginalStTable().CreatePregOriginalSt(regIdx, mirFunc->GetPuidx());
-  auto *regReadExpr = NewInPool<RegMeExpr>(exprID++, regIdx, mirFunc->GetPuidx(),
-                                           ost->GetIndex(), 0, mirType.GetPrimType());
+  auto *regReadExpr = New<RegMeExpr>(exprID++, regIdx, mirFunc->GetPuidx(),
+                                     ost->GetIndex(), 0, mirType.GetPrimType());
   return regReadExpr;
 }
 
@@ -206,7 +207,8 @@ VarMeExpr *IRMap::GetOrCreateZeroVersionVarMeExpr(const OriginalSt &ost) {
     vst2MeExprTable.push_back(nullptr);
   }
   if (vst2MeExprTable[ost.GetZeroVersionIndex()] == nullptr) {
-    auto *varMeExpr = New<VarMeExpr>(&irMapAlloc, exprID++, ost.GetIndex(), ost.GetZeroVersionIndex(), GlobalTables::GetTypeTable().GetTypeFromTyIdx(ost.GetTyIdx())->GetPrimType());
+    auto *varMeExpr = New<VarMeExpr>(&irMapAlloc, exprID++, ost.GetIndex(), ost.GetZeroVersionIndex(),
+                                     GlobalTables::GetTypeTable().GetTypeFromTyIdx(ost.GetTyIdx())->GetPrimType());
     varMeExpr->SetFieldID(ost.GetFieldID());
     ASSERT(!GlobalTables::GetTypeTable().GetTypeTable().empty(), "container check");
     vst2MeExprTable[ost.GetZeroVersionIndex()] = varMeExpr;
diff --git a/src/mapleall/maple_me/src/irmap_build.cpp b/src/mapleall/maple_me/src/irmap_build.cpp
index 48e422bf68b96c04ad482a5dd2332fa03a574bb4..240394410a2a641d31190715215873621232171f 100644
--- a/src/mapleall/maple_me/src/irmap_build.cpp
+++ b/src/mapleall/maple_me/src/irmap_build.cpp
@@ -30,8 +30,8 @@ VarMeExpr *IRMapBuild::GetOrCreateVarFromVerSt(const VersionSt &vst) {
   }
   const OriginalSt *ost = vst.GetOrigSt();
   ASSERT(ost->IsSymbolOst(), "GetOrCreateVarFromVerSt: wrong ost_type");
-  auto *varx = irMap->New<VarMeExpr>(&irMap->irMapAlloc, irMap->exprID++, ost->GetIndex(), vindex,
-     GlobalTables::GetTypeTable().GetTypeTable()[ost->GetTyIdx().GetIdx()]->GetPrimType());
+  PrimType primType = GlobalTables::GetTypeTable().GetTypeTable()[ost->GetTyIdx().GetIdx()]->GetPrimType();
+  auto *varx = irMap->New<VarMeExpr>(&irMap->irMapAlloc, irMap->exprID++, ost->GetIndex(), vindex, primType);
   ASSERT(!GlobalTables::GetTypeTable().GetTypeTable().empty(), "container check");
   varx->SetFieldID(ost->GetFieldID());
   irMap->vst2MeExprTable[vindex] = varx;
@@ -47,8 +47,8 @@ RegMeExpr *IRMapBuild::GetOrCreateRegFromVerSt(const VersionSt &vst) {
   }
   const OriginalSt *ost = vst.GetOrigSt();
   ASSERT(ost->IsPregOst(), "GetOrCreateRegFromVerSt: PregOST expected");
-  auto *regx = irMap->NewInPool<RegMeExpr>(irMap->exprID++, ost->GetPregIdx(), mirModule.CurFunction()->GetPuidx(),
-                                           ost->GetIndex(), vindex, ost->GetMIRPreg()->GetPrimType());
+  auto *regx = irMap->New<RegMeExpr>(irMap->exprID++, ost->GetPregIdx(), mirModule.CurFunction()->GetPuidx(),
+                                     ost->GetIndex(), vindex, ost->GetMIRPreg()->GetPrimType());
   irMap->vst2MeExprTable[vindex] = regx;
   return regx;
 }
diff --git a/src/mapleall/maple_me/src/me_builder.cpp b/src/mapleall/maple_me/src/me_builder.cpp
index bc154054486957d457e44b6ed4a21f67f6d3f8e3..d21b82133b54d1494a0c93a65b8c42e434d35e9c 100644
--- a/src/mapleall/maple_me/src/me_builder.cpp
+++ b/src/mapleall/maple_me/src/me_builder.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) [2019-2020] Huawei Technologies Co.,Ltd.All rights reserved.
+ * Copyright (c) [2019-2021] Huawei Technologies Co.,Ltd.All rights reserved.
  *
  * OpenArkCompiler is licensed under Mulan PSL v2.
  * You can use this software according to the terms and conditions of the Mulan PSL v2.
@@ -35,14 +35,17 @@ MeExpr &MeBuilder::CreateMeExpr(int32 exprId, MeExpr &meExpr) const {
       resultExpr = New<ConststrMeExpr>(exprId, static_cast<ConststrMeExpr&>(meExpr).GetStrIdx(), meExpr.GetPrimType());
       break;
     case kMeOpConststr16:
-      resultExpr = New<Conststr16MeExpr>(exprId, static_cast<Conststr16MeExpr&>(meExpr).GetStrIdx(), meExpr.GetPrimType());
+      resultExpr = New<Conststr16MeExpr>(exprId, static_cast<Conststr16MeExpr&>(meExpr).GetStrIdx(),
+                                         meExpr.GetPrimType());
       break;
     case kMeOpSizeoftype:
-      resultExpr = New<SizeoftypeMeExpr>(exprId, meExpr.GetPrimType(), static_cast<SizeoftypeMeExpr&>(meExpr).GetTyIdx());
+      resultExpr = New<SizeoftypeMeExpr>(exprId, meExpr.GetPrimType(),
+                                         static_cast<SizeoftypeMeExpr&>(meExpr).GetTyIdx());
       break;
     case kMeOpFieldsDist: {
       auto &expr = static_cast<FieldsDistMeExpr&>(meExpr);
-      resultExpr = New<FieldsDistMeExpr>(exprId, meExpr.GetPrimType(), expr.GetTyIdx(), expr.GetFieldID1(), expr.GetFieldID2());
+      resultExpr = New<FieldsDistMeExpr>(exprId, meExpr.GetPrimType(), expr.GetTyIdx(),
+                                         expr.GetFieldID1(), expr.GetFieldID2());
       break;
     }
     case kMeOpAddrof:
@@ -56,7 +59,8 @@ MeExpr &MeBuilder::CreateMeExpr(int32 exprId, MeExpr &meExpr) const {
       resultExpr = New<AddroffuncMeExpr>(exprId, static_cast<AddroffuncMeExpr&>(meExpr).GetPuIdx());
       break;
     case kMeOpGcmalloc:
-      resultExpr = New<GcmallocMeExpr>(exprId, meExpr.GetOp(), meExpr.GetPrimType(), static_cast<GcmallocMeExpr&>(meExpr).GetTyIdx());
+      resultExpr = New<GcmallocMeExpr>(exprId, meExpr.GetOp(), meExpr.GetPrimType(),
+                                       static_cast<GcmallocMeExpr&>(meExpr).GetTyIdx());
       break;
     default:
       CHECK_FATAL(false, "not yet implement");
@@ -82,9 +86,10 @@ MeExpr *MeBuilder::BuildMeExpr(BaseNode &mirNode) const {
 
 MeExpr *MeBuilder::BuildAddrofMeExpr(BaseNode &mirNode) const {
   auto &addrofNode = static_cast<AddrofSSANode&>(mirNode);
-  AddrofMeExpr &meExpr = *New<AddrofMeExpr>(kInvalidExprID, addrofNode.GetPrimType(), addrofNode.GetSSAVar()->GetOrigSt()->GetIndex());
-  meExpr.SetFieldID(addrofNode.GetFieldID());
-  return &meExpr;
+  auto meExpr = New<AddrofMeExpr>(kInvalidExprID, addrofNode.GetPrimType(),
+                                  addrofNode.GetSSAVar()->GetOrigSt()->GetIndex());
+  meExpr->SetFieldID(addrofNode.GetFieldID());
+  return meExpr;
 }
 
 MeExpr *MeBuilder::BuildAddroffuncMeExpr(BaseNode &mirNode) const {
@@ -93,13 +98,15 @@ MeExpr *MeBuilder::BuildAddroffuncMeExpr(BaseNode &mirNode) const {
 }
 
 MeExpr *MeBuilder::BuildGCMallocMeExpr(BaseNode &mirNode) const {
-  GcmallocMeExpr &meExpr = *New<GcmallocMeExpr>(kInvalidExprID, mirNode.GetOpCode(), mirNode.GetPrimType(), static_cast<GCMallocNode&>(mirNode).GetTyIdx());
-  return &meExpr;
+  auto meExpr = New<GcmallocMeExpr>(kInvalidExprID, mirNode.GetOpCode(), mirNode.GetPrimType(),
+                                    static_cast<GCMallocNode&>(mirNode).GetTyIdx());
+  return meExpr;
 }
 
 MeExpr *MeBuilder::BuildSizeoftypeMeExpr(BaseNode &mirNode) const {
-  SizeoftypeMeExpr &meExpr = *New<SizeoftypeMeExpr>(kInvalidExprID, mirNode.GetPrimType(), static_cast<SizeoftypeNode&>(mirNode).GetTyIdx());
-  return &meExpr;
+  auto meExpr = New<SizeoftypeMeExpr>(kInvalidExprID, mirNode.GetPrimType(),
+                                      static_cast<SizeoftypeNode&>(mirNode).GetTyIdx());
+  return meExpr;
 }
 
 MeExpr *MeBuilder::BuildFieldsDistMeExpr(BaseNode &mirNode) const {
@@ -111,8 +118,9 @@ MeExpr *MeBuilder::BuildFieldsDistMeExpr(BaseNode &mirNode) const {
 
 MeExpr *MeBuilder::BuildIvarMeExpr(BaseNode &mirNode) const {
   auto &ireadSSANode = static_cast<IreadSSANode&>(mirNode);
-  IvarMeExpr &meExpr = *New<IvarMeExpr>(kInvalidExprID, mirNode.GetPrimType(), ireadSSANode.GetTyIdx(), ireadSSANode.GetFieldID());
-  return &meExpr;
+  auto meExpr = New<IvarMeExpr>(kInvalidExprID, mirNode.GetPrimType(),
+                                ireadSSANode.GetTyIdx(), ireadSSANode.GetFieldID());
+  return meExpr;
 }
 
 MeExpr *MeBuilder::BuildConstMeExpr(BaseNode &mirNode) const {
@@ -123,13 +131,15 @@ MeExpr *MeBuilder::BuildConstMeExpr(BaseNode &mirNode) const {
 }
 
 MeExpr *MeBuilder::BuildConststrMeExpr(BaseNode &mirNode) const {
-  ConststrMeExpr &meExpr = *New<ConststrMeExpr>(kInvalidExprID, static_cast<ConststrNode&>(mirNode).GetStrIdx(), mirNode.GetPrimType());
-  return &meExpr;
+  auto meExpr = New<ConststrMeExpr>(kInvalidExprID, static_cast<ConststrNode&>(mirNode).GetStrIdx(),
+                                    mirNode.GetPrimType());
+  return meExpr;
 }
 
 MeExpr *MeBuilder::BuildConststr16MeExpr(BaseNode &mirNode) const {
-  Conststr16MeExpr &meExpr = *New<Conststr16MeExpr>(kInvalidExprID, static_cast<Conststr16Node&>(mirNode).GetStrIdx(), mirNode.GetPrimType());
-  return &meExpr;
+  auto meExpr = New<Conststr16MeExpr>(kInvalidExprID, static_cast<Conststr16Node&>(mirNode).GetStrIdx(),
+                                      mirNode.GetPrimType());
+  return meExpr;
 }
 
 MeExpr *MeBuilder::BuildOpMeExprForCompare(BaseNode &mirNode) const {
@@ -182,21 +192,24 @@ MeExpr *MeBuilder::BuildOpMeExprForResolveFunc(BaseNode &mirNode) const {
 
 MeExpr *MeBuilder::BuildNaryMeExprForArray(BaseNode &mirNode) const {
   auto &arrayNode = static_cast<ArrayNode&>(mirNode);
-  NaryMeExpr &meExpr =
-      *NewInPool<NaryMeExpr>(kInvalidExprID, mirNode.GetOpCode(), mirNode.GetPrimType(), mirNode.GetNumOpnds(), arrayNode.GetTyIdx(), INTRN_UNDEFINED, arrayNode.GetBoundsCheck());
-  return &meExpr;
+  auto meExpr =
+      NewInPool<NaryMeExpr>(kInvalidExprID, mirNode.GetOpCode(), mirNode.GetPrimType(), mirNode.GetNumOpnds(),
+                            arrayNode.GetTyIdx(), INTRN_UNDEFINED, arrayNode.GetBoundsCheck());
+  return meExpr;
 }
 
 MeExpr *MeBuilder::BuildNaryMeExprForIntrinsicop(BaseNode &mirNode) const {
-  NaryMeExpr &meExpr =
-      *NewInPool<NaryMeExpr>(kInvalidExprID, mirNode.GetOpCode(), mirNode.GetPrimType(), mirNode.GetNumOpnds(), TyIdx(0), static_cast<IntrinsicopNode&>(mirNode).GetIntrinsic(), false);
-  return &meExpr;
+  auto meExpr =
+      NewInPool<NaryMeExpr>(kInvalidExprID, mirNode.GetOpCode(), mirNode.GetPrimType(), mirNode.GetNumOpnds(),
+                            TyIdx(0), static_cast<IntrinsicopNode&>(mirNode).GetIntrinsic(), false);
+  return meExpr;
 }
 
 MeExpr *MeBuilder::BuildNaryMeExprForIntrinsicWithType(BaseNode &mirNode) const {
   auto &intrinNode = static_cast<IntrinsicopNode&>(mirNode);
-  NaryMeExpr &meExpr = *NewInPool<NaryMeExpr>(kInvalidExprID, mirNode.GetOpCode(), mirNode.GetPrimType(), mirNode.GetNumOpnds(), intrinNode.GetTyIdx(), intrinNode.GetIntrinsic(), false);
-  return &meExpr;
+  auto meExpr = NewInPool<NaryMeExpr>(kInvalidExprID, mirNode.GetOpCode(), mirNode.GetPrimType(),
+                                      mirNode.GetNumOpnds(), intrinNode.GetTyIdx(), intrinNode.GetIntrinsic(), false);
+  return meExpr;
 }
 
 UnaryMeStmt &MeBuilder::BuildUnaryMeStmt(Opcode op, MeExpr &opnd, BB &bb, const SrcPosition &src) const {
diff --git a/src/mapleall/maple_me/src/me_ir.cpp b/src/mapleall/maple_me/src/me_ir.cpp
index 94be9b079bfaf3beba4ece10ba0997cc0bd83607..53063c794100d0917aeaf48562d71ad6d1a5115c 100755
--- a/src/mapleall/maple_me/src/me_ir.cpp
+++ b/src/mapleall/maple_me/src/me_ir.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) [2019-2020] Huawei Technologies Co.,Ltd.All rights reserved.
+ * Copyright (c) [2019-2021] Huawei Technologies Co.,Ltd.All rights reserved.
  *
  * OpenArkCompiler is licensed under Mulan PSL v2.
  * You can use this software according to the terms and conditions of the Mulan PSL v2.
@@ -1417,6 +1417,26 @@ bool MeExpr::HasIvar() const {
   return false;
 }
 
+bool MeExpr::IsDexMerge() const {
+  if (op != OP_intrinsicop) {
+    return false;
+  }
+  auto *naryx = static_cast<const NaryMeExpr*>(this);
+  if (naryx->GetIntrinsic() != INTRN_JAVA_MERGE) {
+    return false;
+  }
+  if (naryx->GetOpnds().size() != 1) {
+    return false;
+  }
+  if (naryx->GetOpnd(0)->GetMeOp() == kMeOpVar || naryx->GetOpnd(0)->GetMeOp() == kMeOpIvar) {
+    return true;
+  }
+  if (naryx->GetOpnd(0)->GetMeOp() == kMeOpReg) {
+    auto *r = static_cast<RegMeExpr*>(naryx->GetOpnd(0));
+    return r->GetRegIdx() >= 0;
+  }
+  return false;
+}
 
 // check if MeExpr can be a pointer to something that requires incref for its
 // assigned target
@@ -1424,6 +1444,9 @@ bool MeExpr::PointsToSomethingThatNeedsIncRef(SSATab &ssaTab) {
   if (op == OP_retype) {
     return true;
   }
+  if (IsDexMerge()) {
+    return true;
+  }
   if (meOp == kMeOpIvar) {
     return true;
   }
diff --git a/src/mapleall/maple_me/src/me_rename2preg.cpp b/src/mapleall/maple_me/src/me_rename2preg.cpp
index 004f8566e546f92a26eaae33c735b1215179819e..6cc662f84b70d6cf1f2cbce625521da3fef5eb4c 100755
--- a/src/mapleall/maple_me/src/me_rename2preg.cpp
+++ b/src/mapleall/maple_me/src/me_rename2preg.cpp
@@ -427,7 +427,7 @@ class SSARename2Preg {
   CacheProxy cacheProxy;
   FormalRenaming formal;
 };
-}  // namespace
+} // namespace
 
 namespace maple {
 
diff --git a/src/mapleall/maple_me/src/me_ssa_update.cpp b/src/mapleall/maple_me/src/me_ssa_update.cpp
index c19a2b8e47303cfb2a710adc414d14d248573942..de576c143eed84c20010933532270399f78d2f18 100755
--- a/src/mapleall/maple_me/src/me_ssa_update.cpp
+++ b/src/mapleall/maple_me/src/me_ssa_update.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) [2019-2020] Huawei Technologies Co.,Ltd.All rights reserved.
+ * Copyright (c) [2019-2021] Huawei Technologies Co.,Ltd.All rights reserved.
  *
  * OpenArkCompiler is licensed under Mulan PSL v2.
  * You can use this software according to the terms and conditions of the Mulan PSL v2.
@@ -136,7 +136,8 @@ MeExpr *MeSSAUpdate::RenameExpr(MeExpr &meExpr, bool &changed) {
     }
     case kMeOpNary: {
       auto &naryMeExpr = static_cast<NaryMeExpr&>(meExpr);
-      NaryMeExpr newMeExpr(&irMap.GetIRMapAlloc(), kInvalidExprID, meExpr.GetOp(), meExpr.GetPrimType(), meExpr.GetNumOpnds(), naryMeExpr.GetTyIdx(), naryMeExpr.GetIntrinsic(),
+      NaryMeExpr newMeExpr(&irMap.GetIRMapAlloc(), kInvalidExprID, meExpr.GetOp(), meExpr.GetPrimType(),
+                           meExpr.GetNumOpnds(), naryMeExpr.GetTyIdx(), naryMeExpr.GetIntrinsic(),
                            naryMeExpr.GetBoundCheck());
       for (size_t i = 0; i < naryMeExpr.GetOpnds().size(); ++i) {
         newMeExpr.GetOpnds().push_back(RenameExpr(*naryMeExpr.GetOpnd(i), needRehash));
diff --git a/src/mapleall/maple_me/src/me_ssi.cpp b/src/mapleall/maple_me/src/me_ssi.cpp
index 4d8b6ddf56159ee2c0c065ec448bd7e81b3ecea1..4a389699eef037ec551b6f76859e1b51e0b378c5 100644
--- a/src/mapleall/maple_me/src/me_ssi.cpp
+++ b/src/mapleall/maple_me/src/me_ssi.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) [2020] Huawei Technologies Co.,Ltd.All rights reserved.
+ * Copyright (c) [2020-2021] Huawei Technologies Co.,Ltd.All rights reserved.
  *
  * OpenArkCompiler is licensed under Mulan PSL v2.
  * You can use this software according to the terms and conditions of the Mulan PSL v2.
diff --git a/src/mapleall/maple_me/src/preg_renamer.cpp b/src/mapleall/maple_me/src/preg_renamer.cpp
index 70902ad98d422674458ddf7198d6861c760fdcef..efae88d8dc4bd9c9a5d6f34dae5046965c1a3d5c 100755
--- a/src/mapleall/maple_me/src/preg_renamer.cpp
+++ b/src/mapleall/maple_me/src/preg_renamer.cpp
@@ -1,3 +1,17 @@
+/*
+ * Copyright (c) [2020-2021] Huawei Technologies Co.,Ltd.All rights reserved.
+ *
+ * OpenArkCompiler is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *
+ *     http://license.coscl.org.cn/MulanPSL2
+ *
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+ * FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
 #include "alias_class.h"
 #include "mir_builder.h"
 #include "me_irmap.h"
@@ -5,10 +19,8 @@
 #include "union_find.h"
 
 namespace maple {
-
-void PregRenamer::RunSelf() const {
+void PregRenamer::RunSelf() {
   // BFS the graph of register phi node;
-  std::set<RegMeExpr *> curvisited;
   const MapleVector<MeExpr *> &regmeexprtable = meirmap->GetVerst2MeExprTable();
   MIRPregTable *pregtab = func->GetMirFunc()->GetPregTab();
   std::vector<bool> firstappeartable(pregtab->GetPregTable().size());
@@ -20,22 +32,21 @@ void PregRenamer::RunSelf() const {
       continue;
     }
     MapleMap<OStIdx, MePhiNode *> &mePhiList =  bb->GetMePhiList();
-    for (MapleMap<OStIdx, MePhiNode *>::iterator it = mePhiList.begin();
-      it != mePhiList.end(); it++) {
+    for (auto it = mePhiList.begin(); it != mePhiList.end(); ++it) {
       OriginalSt *ost = func->GetMeSSATab()->GetOriginalStFromID(it->first);
       if (!ost->IsPregOst()) { // only handle reg phi
         continue;
       }
       MePhiNode *meRegPhi = it->second;
-      uint32 vstIdx = meRegPhi->GetLHS()->GetVstIdx();
-      uint32 nOpnds = meRegPhi->GetOpnds().size();
-      for (uint32 i = 0; i < nOpnds; i++) {
+      size_t vstIdx = meRegPhi->GetLHS()->GetVstIdx();
+      size_t nOpnds = meRegPhi->GetOpnds().size();
+      for (size_t i = 0; i < nOpnds; ++i) {
         unionFind.Union(vstIdx, meRegPhi->GetOpnd(i)->GetVstIdx());
       }
     }
   }
   std::map<uint32, std::vector<uint32> > root2childrenMap;
-  for (uint32 i = 0; i< regmeexprtable.size(); i++) {
+  for (uint32 i = 0; i < regmeexprtable.size(); ++i) {
     MeExpr *meexpr = regmeexprtable[i];
     if (!meexpr || meexpr->GetMeOp() != kMeOpReg)
       continue;
@@ -45,7 +56,7 @@ void PregRenamer::RunSelf() const {
     }
     uint32 rootVstidx = unionFind.Root(i);
 
-    std::map<uint32, std::vector<uint32>>::iterator mpit = root2childrenMap.find(rootVstidx);
+    auto mpit = root2childrenMap.find(rootVstidx);
     if (mpit == root2childrenMap.end()) {
       std::vector<uint32> vec(1, i);
       root2childrenMap[rootVstidx] = vec;
@@ -55,11 +66,10 @@ void PregRenamer::RunSelf() const {
     }
   }
 
-  for (std::map<uint32, std::vector<uint32> >::iterator it = root2childrenMap.begin();
-         it != root2childrenMap.end(); it++) {
-     std::vector<uint32> &vec = it->second;
-     bool isIntryOrZerov = false;  // in try block or zero version
-     for (uint32 i = 0; i < vec.size(); i++) {
+  for (auto it = root2childrenMap.begin(); it != root2childrenMap.end(); ++it) {
+    std::vector<uint32> &vec = it->second;
+    bool isIntryOrZerov = false; // in try block or zero version
+    for (uint32 i = 0; i < vec.size(); ++i) {
       uint32 vstIdx = vec[i];
       ASSERT(vstIdx < regmeexprtable.size(), "over size");
       RegMeExpr *tregMeexpr = static_cast<RegMeExpr *> (regmeexprtable[vstIdx]);
@@ -68,10 +78,10 @@ void PregRenamer::RunSelf() const {
         isIntryOrZerov = true;
         break;
       }
-
     }
-    if (isIntryOrZerov)
+    if (isIntryOrZerov) {
       continue;
+    }
     // get all the nodes in candidates the same register
     RegMeExpr *regMeexpr = static_cast<RegMeExpr *>(regmeexprtable[it->first]);
     PregIdx16 newpregidx = regMeexpr->GetRegIdx();
@@ -84,30 +94,28 @@ void PregRenamer::RunSelf() const {
     newpregidx = pregtab->ClonePreg(*pregtab->PregFromPregIdx(regMeexpr->GetRegIdx()));
     renameCount++;
     if (DEBUGFUNC(func)) {
-      std::cout << "%" << pregtab->PregFromPregIdx(static_cast<uint32>(regMeexpr->GetRegIdx()))->GetPregNo();
-      std::cout << " renamed to %" << pregtab->PregFromPregIdx(static_cast<uint32>(newpregidx))->GetPregNo() << std::endl;
+      LogInfo::MapleLogger() << "%" << pregtab->PregFromPregIdx(regMeexpr->GetRegIdx())->GetPregNo();
+      LogInfo::MapleLogger() << " renamed to %" << pregtab->PregFromPregIdx(newpregidx)->GetPregNo() << std::endl;
     }
     // reneme all the register
-    for (uint32 i = 0; i < vec.size(); i++) {
+    for (uint32 i = 0; i < vec.size(); ++i) {
       RegMeExpr *canregnode =  static_cast<RegMeExpr *> (regmeexprtable[vec[i]]);
-      // std::cout << "rename %"<< canregnode->regidx << "to %" << newpregidx << std::endl;
       canregnode->SetRegIdx(newpregidx);  // rename it to a new register
     }
   }
 }
 
-AnalysisResult *MeDoPregRename::Run(MeFunction *func, MeFuncResultMgr *m, ModuleResultMgr *mrm) {
+AnalysisResult *MeDoPregRename::Run(MeFunction *func, MeFuncResultMgr *m, ModuleResultMgr*) {
   MeIRMap *irmap = static_cast<MeIRMap *>(m->GetAnalysisResult(MeFuncPhase_IRMAPBUILD, func));
   std::string renamePhaseName = PhaseName();
   MemPool *renamemp = memPoolCtrler.NewMemPool(renamePhaseName);
   PregRenamer pregrenamer(renamemp, func, irmap);
   pregrenamer.RunSelf();
   if (DEBUGFUNC(func)) {
-    std::cout << "------------after pregrename:-------------------\n";
+    LogInfo::MapleLogger() << "------------after pregrename:-------------------\n";
     func->Dump();
   }
   memPoolCtrler.DeleteMemPool(renamemp);
   return nullptr;
 }
-
 }  // namespace maple
diff --git a/src/mapleall/maple_me/src/prop.cpp b/src/mapleall/maple_me/src/prop.cpp
index 57ecacb8e95c96cd793563892aae33b2611d3627..7fe329408c0e7afa12b100abf884c81a0f7411c1 100755
--- a/src/mapleall/maple_me/src/prop.cpp
+++ b/src/mapleall/maple_me/src/prop.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) [2020] Huawei Technologies Co.,Ltd.All rights reserved.
+ * Copyright (c) [2020-2021] Huawei Technologies Co.,Ltd.All rights reserved.
  *
  * OpenArkCompiler is licensed under Mulan PSL v2.
  * You can use this software according to the terms and conditions of the Mulan PSL v2.
diff --git a/src/mapleall/maple_me/src/ssa_pre.cpp b/src/mapleall/maple_me/src/ssa_pre.cpp
index a5bda41c384840c5f2feafcc114ea14c0ffac621..5ba5d4a9fe205f287bef27192c851ecaf0d98af8 100755
--- a/src/mapleall/maple_me/src/ssa_pre.cpp
+++ b/src/mapleall/maple_me/src/ssa_pre.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) [2020] Huawei Technologies Co.,Ltd.All rights reserved.
+ * Copyright (c) [2020-2021] Huawei Technologies Co.,Ltd.All rights reserved.
  *
  * OpenArkCompiler is licensed under Mulan PSL v2.
  * You can use this software according to the terms and conditions of the Mulan PSL v2.