diff --git a/src/mapleall/bin/debug/dex2mpl.tar.gz b/src/mapleall/bin/debug/dex2mpl.tar.gz
index dde072e809536448e8127da046c12fb610a8ac4c..d170bb0eeb75863f1a57cc66638978787d0598c6 100644
Binary files a/src/mapleall/bin/debug/dex2mpl.tar.gz and b/src/mapleall/bin/debug/dex2mpl.tar.gz differ
diff --git a/src/mapleall/maple_be/include/be/becommon.h b/src/mapleall/maple_be/include/be/becommon.h
index baceed351c588b7415042fb46d601274d989fc2a..bd84b8a2c518e5eb29191adb29bc970baa39cc35 100644
--- a/src/mapleall/maple_be/include/be/becommon.h
+++ b/src/mapleall/maple_be/include/be/becommon.h
@@ -143,7 +143,7 @@ class BECommon {
   }
 
   /* Global type table might be updated during lowering for C/C++. */
-  void FinalizeTypeTable(MIRType &ty);
+  void FinalizeTypeTable(const MIRType &ty);
 
   uint32 GetFieldIdxIncrement(const MIRType &ty) const {
     if (ty.GetKind() == kTypeClass) {
diff --git a/src/mapleall/maple_be/include/be/common_utils.h b/src/mapleall/maple_be/include/be/common_utils.h
index 0789de3c41804a5caddcc11f881e1b07468a708c..68079e1b0bb19fcfcf00271f16bb709a7d8cf157 100644
--- a/src/mapleall/maple_be/include/be/common_utils.h
+++ b/src/mapleall/maple_be/include/be/common_utils.h
@@ -30,6 +30,7 @@ constexpr uint32 kBaseOffsetAlignment = 3;
  * constants.
  */
 constexpr uint32 k1FConst = 31;
+constexpr uint32 k0BitSize = 0;
 constexpr uint32 k4BitSize = 4;
 constexpr uint32 k6BitSize = 6;
 constexpr uint32 k8BitSize = 8;
@@ -54,6 +55,8 @@ constexpr uint32 k4BitShift = 2; /* 4 is 1 << 2; */
 constexpr uint32 k8BitShift = 3;  /* 8 is 1 << 3; */
 constexpr uint32 k16BitShift = 4; /* 16 is 1 << 4 */
 
+constexpr uint32 kDwordSizeTwo = 2;
+
 constexpr uint32 k4ByteFloatSize = 4;
 constexpr uint32 k8ByteDoubleSize = 8;
 
@@ -70,6 +73,7 @@ constexpr int32 kInsnEighthOpnd = 7;
 /* Number of registers */
 constexpr uint32 kOneRegister = 1;
 constexpr uint32 kTwoRegister = 2;
+constexpr uint32 kThreeRegister = 3;
 constexpr uint32 kFourRegister = 4;
 
 /* Size of struct for memcpy */
diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_abi.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_abi.h
index 6e7c2dc397c4146bf43d04b764294160bc15afc7..8fed6698f9e5578b0c541771ec88da5c1d89fbe9 100644
--- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_abi.h
+++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_abi.h
@@ -95,7 +95,7 @@ class ParmLocator {
   BECommon &beCommon;
   int32 paramNum           = 0;  /* number of all types of parameters processed so far */
   int32 nextGeneralRegNO   = 0;  /* number of integer parameters processed so far */
-  int32 nextFloatRegNO     = 0;  /* number of float parameters processed so far */
+  uint32 nextFloatRegNO    = 0;  /* number of float parameters processed so far */
   int32 nextStackArgAdress = 0;
 
   AArch64reg AllocateGPRegister() {
@@ -115,29 +115,29 @@ class ParmLocator {
     return (nextFloatRegNO < AArch64Abi::kNumFloatParmRegs) ? AArch64Abi::floatParmRegs[nextFloatRegNO++] : kRinvalid;
   }
 
-  inline void AllocateNSIMDFPRegisters(PLocInfo &ploc, uint32 num) {
+  void AllocateNSIMDFPRegisters(PLocInfo &ploc, uint32 num) {
     if ((nextFloatRegNO + num - 1) < AArch64Abi::kNumFloatParmRegs) {
       switch (num) {
-      case 1:
-        ploc.reg0 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
-        break;
-      case 2:
-        ploc.reg0 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
-        ploc.reg1 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
-        break;
-      case 3:
-        ploc.reg0 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
-        ploc.reg1 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
-        ploc.reg2 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
-        break;
-      case 4:
-        ploc.reg0 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
-        ploc.reg1 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
-        ploc.reg2 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
-        ploc.reg3 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
-        break;
-      default:
-        CHECK_FATAL(0, "AllocateNSIMDFPRegisters: unsupported");
+        case kOneRegister:
+          ploc.reg0 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
+          break;
+        case kTwoRegister:
+          ploc.reg0 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
+          ploc.reg1 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
+          break;
+        case kThreeRegister:
+          ploc.reg0 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
+          ploc.reg1 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
+          ploc.reg2 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
+          break;
+        case kFourRegister:
+          ploc.reg0 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
+          ploc.reg1 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
+          ploc.reg2 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
+          ploc.reg3 = AArch64Abi::floatParmRegs[nextFloatRegNO++];
+          break;
+        default:
+          CHECK_FATAL(0, "AllocateNSIMDFPRegisters: unsupported");
       }
     } else {
       ploc.reg0 = kRinvalid;
@@ -154,7 +154,7 @@ class ParmLocator {
 /* given the type of the return value, determines the return mechanism */
 class ReturnMechanism {
  public:
-  ReturnMechanism(MIRType &retType, BECommon &be);
+  ReturnMechanism(MIRType &retType, const BECommon &be);
 
   ~ReturnMechanism() = default;
 
diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h
index 50742c7d9fe575fb1eee08a7f9b3815b762c7ece..1f4410d0f2feb172b7e1ebc321a3b0b651cfb551 100644
--- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h
+++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h
@@ -572,7 +572,7 @@ class AArch64CGFunc : public CGFunc {
   void CreateCallStructParamMemcpy(const MIRSymbol *sym, RegOperand *addropnd,
                                    uint32 structSize, int32 copyOffset, int32 fromOffset);
   AArch64RegOperand *CreateCallStructParamCopyToStack(uint32 numMemOp, MIRSymbol *sym, RegOperand *addropnd,
-                                                      int32 copyOffset, PLocInfo &pLoc);
+                                                      int32 copyOffset, const PLocInfo &pLoc);
   void SelectParmListDreadSmallAggregate(MIRSymbol &sym, MIRType &structType, AArch64ListOperand &srcOpnds,
                                          ParmLocator &parmLocator);
   void SelectParmListIreadSmallAggregate(const IreadNode &iread, MIRType &structType, AArch64ListOperand &srcOpnds,
diff --git a/src/mapleall/maple_be/src/be/becommon.cpp b/src/mapleall/maple_be/src/be/becommon.cpp
index 08da2f0ca6e556af0e5332364dbdc157de4a7ec0..755114bf2157c16b6f94f08cedb59fe09e0a5069 100644
--- a/src/mapleall/maple_be/src/be/becommon.cpp
+++ b/src/mapleall/maple_be/src/be/becommon.cpp
@@ -117,7 +117,7 @@ void BECommon::ComputeStructTypeSizesAligns(MIRType &ty, const TyIdx &tyIdx) {
   SetStructFieldCount(structType.GetTypeIndex(), fields.size());
   if (fields.size() == 0) {
     if (structType.IsCPlusPlus()) {
-      SetTypeSize(tyIdx.GetIdx(), 1); // empty struct in C++ has size 1
+      SetTypeSize(tyIdx.GetIdx(), 1); /* empty struct in C++ has size 1 */
       SetTypeAlign(tyIdx.GetIdx(), 1);
     } else {
       SetTypeSize(tyIdx.GetIdx(), 0);
@@ -642,12 +642,12 @@ MIRType *BECommon::BeGetOrCreateFunctionType(TyIdx tyIdx, const std::vector<TyId
   return newType;
 }
 
-void BECommon::FinalizeTypeTable(MIRType &ty) {
+void BECommon::FinalizeTypeTable(const MIRType &ty) {
   if (ty.GetTypeIndex() > GetSizeOfTypeSizeTable()) {
     if (mirModule.GetSrcLang() == kSrcLangC) {
       for (uint32 i = GetSizeOfTypeSizeTable(); i < ty.GetTypeIndex(); ++i) {
-        MIRType *ty = GlobalTables::GetTypeTable().GetTypeFromTyIdx(i);
-        AddAndComputeSizeAlign(*ty);
+        MIRType *tyTmp = GlobalTables::GetTypeTable().GetTypeFromTyIdx(i);
+        AddAndComputeSizeAlign(*tyTmp);
       }
     } else {
       CHECK_FATAL(ty.GetTypeIndex() == typeSizeTable.size(), "make sure the ty idx is exactly the table size");
diff --git a/src/mapleall/maple_be/src/be/lower.cpp b/src/mapleall/maple_be/src/be/lower.cpp
index a58ec28e9f50dd92a086cc0671b5667f2c5f79c4..5ff52060dc7159c7e731a9f75fa9f82f6d5ed13d 100644
--- a/src/mapleall/maple_be/src/be/lower.cpp
+++ b/src/mapleall/maple_be/src/be/lower.cpp
@@ -661,7 +661,7 @@ BlockNode *CGLowerer::LowerReturnStruct(NaryStmtNode &retNode) {
   }
   BaseNode *opnd0 = retNode.Opnd(0);
   if (!(opnd0 && opnd0->GetPrimType() == PTY_agg)) {
-    // It is possible function never returns and have a dummy return const instead of a struct.
+    /* It is possible function never returns and have a dummy return const instead of a struct. */
     maple::LogInfo::MapleLogger(kLlWarn) << "return struct should have a kid" << std::endl;
   }
 
diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_abi.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_abi.cpp
index ebcda1c7a09ddf18b3e116a2d90a4f37b19e945f..87211148915ec814359543af26eff384ff593476 100644
--- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_abi.cpp
+++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_abi.cpp
@@ -88,14 +88,14 @@ PrimType TraverseStructFieldsForFp(MIRType *ty, uint32 &numRegs) {
   }
 }
 
-int32 ClassifyAggregate(BECommon &be, MIRType &mirType, AArch64ArgumentClass classes[kMaxRegCount],
+int32 ClassifyAggregate(const BECommon &be, MIRType &mirType, AArch64ArgumentClass classes[kMaxRegCount],
                         size_t classesLength, uint32 &fpSize);
 
-uint32 ProcessStructWhenClassifyAggregate(BECommon &be, MIRStructType &structType,
-                                        AArch64ArgumentClass classes[kMaxRegCount],
-                                        size_t classesLength, uint32 &fpSize) {
+uint32 ProcessStructWhenClassifyAggregate(const BECommon &be, MIRStructType &structType,
+                                          AArch64ArgumentClass classes[kMaxRegCount],
+                                          size_t classesLength, uint32 &fpSize) {
   CHECK_FATAL(classesLength > 0, "classLength must > 0");
-  int32 sizeOfTyInDwords = RoundUp(be.GetTypeSize(structType.GetTypeIndex()), k8ByteSize) >> k8BitShift;
+  uint32 sizeOfTyInDwords = RoundUp(be.GetTypeSize(structType.GetTypeIndex()), k8ByteSize) >> k8BitShift;
   bool isF32 = false;
   bool isF64 = false;
   uint32 numRegs = 0;
@@ -121,7 +121,7 @@ uint32 ProcessStructWhenClassifyAggregate(BECommon &be, MIRStructType &structTyp
     }
   }
   if (isF32 || isF64) {
-    for (int32 i = 0; i < numRegs; ++i) {
+    for (uint32 i = 0; i < numRegs; ++i) {
       classes[i] = kAArch64FloatClass;
     }
     fpSize = isF32 ? k4ByteSize : k8ByteSize;
@@ -129,35 +129,19 @@ uint32 ProcessStructWhenClassifyAggregate(BECommon &be, MIRStructType &structTyp
   }
 
   classes[0] = kAArch64IntegerClass;
-  if (sizeOfTyInDwords == 2) {
+  if (sizeOfTyInDwords == kDwordSizeTwo) {
     classes[1] = kAArch64IntegerClass;
   }
   return sizeOfTyInDwords;
 }
 
-void ProcessArrayWhenClassifyAggregate(BECommon &be, const MIRArrayType &mirArrayType,
-                                       AArch64ArgumentClass classes[kMaxRegCount], size_t classesLength) {
-  CHECK_FATAL(0, "Should not be here");
-  CHECK_FATAL(classesLength > 0, "classLength must > 0");
-  int32 sizeOfTyInDwords = RoundUp(be.GetTypeSize(mirArrayType.GetTypeIndex()), k8ByteSize) >> k8BitShift;
-  AArch64ArgumentClass subClasses[kMaxRegCount];
-  uint32 subNumRegs;
-  uint32 fpSize;
-  subNumRegs = ClassifyAggregate(be, *(GlobalTables::GetTypeTable().GetTypeFromTyIdx(mirArrayType.GetElemTyIdx())),
-                                 subClasses, sizeof(subClasses) / sizeof(AArch64ArgumentClass), fpSize);
-  CHECK_FATAL(subNumRegs == 1, "subnumregs should be equal to 1");
-  for (int32 i = 0; i < sizeOfTyInDwords; ++i) {
-    classes[i] = subClasses[i];
-  }
-}
-
 /*
  * Analyze the given aggregate using the rules given by the ARM 64-bit ABI and
  * return the number of doublewords to be passed in registers; the classes of
  * the doublewords are returned in parameter "classes"; if 0 is returned, it
  * means the whole aggregate is passed in memory.
  */
-int32 ClassifyAggregate(BECommon &be, MIRType &mirType, AArch64ArgumentClass classes[kMaxRegCount],
+int32 ClassifyAggregate(const BECommon &be, MIRType &mirType, AArch64ArgumentClass classes[kMaxRegCount],
                         size_t classesLength, uint32 &fpSize) {
   CHECK_FATAL(classesLength > 0, "invalid index");
   uint64 sizeOfTy = be.GetTypeSize(mirType.GetTypeIndex());
@@ -191,8 +175,7 @@ int32 ClassifyAggregate(BECommon &be, MIRType &mirType, AArch64ArgumentClass cla
     return ProcessStructWhenClassifyAggregate(be, structType, classes, classesLength, fpSize);
   } else {
     /* mirType->_kind == TYPE_ARRAY */
-    auto &mirArrayType = static_cast<MIRArrayType&>(mirType);
-    ProcessArrayWhenClassifyAggregate(be, mirArrayType, classes, classesLength);
+    CHECK_FATAL(false, "Should not be here");
   }
   /* post merger clean-up */
   for (i = 0; i < sizeOfTyInDwords; ++i) {
@@ -341,16 +324,16 @@ void ParmLocator::InitPLocInfo(PLocInfo &pLoc) const {
 
 int32 ParmLocator::LocateRetVal(MIRType &retType, PLocInfo &pLoc) {
   InitPLocInfo(pLoc);
-  int retSize = beCommon.GetTypeSize(retType.GetTypeIndex().GetIdx());
+  uint32 retSize = beCommon.GetTypeSize(retType.GetTypeIndex().GetIdx());
   if (retSize == 0) {
-    return 0;    // size 0 ret val
+    return 0;    /* size 0 ret val */
   }
   if (retSize <= k16ByteSize) {
-    // For return struct size less or equal to 16 bytes, the values
-    // are returned in register pairs.
-    AArch64ArgumentClass classes[kMaxRegCount]; // Max of four floats.
+    /* For return struct size less or equal to 16 bytes, the values */
+    /* are returned in register pairs. */
+    AArch64ArgumentClass classes[kMaxRegCount]; /* Max of four floats. */
     uint32 fpSize;
-    int32 numRegs = ClassifyAggregate(beCommon, retType, classes, sizeof(classes), fpSize);
+    uint32 numRegs = static_cast<uint32>(ClassifyAggregate(beCommon, retType, classes, sizeof(classes), fpSize));
     if (classes[0] == kAArch64FloatClass) {
       CHECK_FATAL(numRegs <= kMaxRegCount, "LocateNextParm: illegal number of regs");
       AllocateNSIMDFPRegisters(pLoc, numRegs);
@@ -367,7 +350,7 @@ int32 ParmLocator::LocateRetVal(MIRType &retType, PLocInfo &pLoc) {
       return 0;
     }
   } else {
-    // For return struct size > 16 bytes the pointer returns in x8.
+    /* For return struct size > 16 bytes the pointer returns in x8. */
     pLoc.reg0 = R8;
     return kSizeOfPtr;
   }
@@ -409,23 +392,22 @@ int32 ParmLocator::LocateNextParm(MIRType &mirType, PLocInfo &pLoc, bool isFirst
       AArch64ArgumentClass classes[kMaxRegCount];
       uint32 fpSize;
       MIRType *retType = GlobalTables::GetTypeTable().GetTypeFromTyIdx(beCommon.GetFuncReturnType(*func));
-        int32 numRegs = ClassifyAggregate(beCommon, *retType, classes, sizeof(classes), fpSize);
-        if (classes[0] == kAArch64FloatClass) {
-          CHECK_FATAL(numRegs <= kMaxRegCount, "LocateNextParm: illegal number of regs");
-          AllocateNSIMDFPRegisters(pLoc, numRegs);
-          pLoc.numFpPureRegs = numRegs;
-          pLoc.fpSize = fpSize;
-          return 0;
+      uint32 numRegs = static_cast<uint32>(ClassifyAggregate(beCommon, *retType, classes, sizeof(classes), fpSize));
+      if (classes[0] == kAArch64FloatClass) {
+        CHECK_FATAL(numRegs <= kMaxRegCount, "LocateNextParm: illegal number of regs");
+        AllocateNSIMDFPRegisters(pLoc, numRegs);
+        pLoc.numFpPureRegs = numRegs;
+        pLoc.fpSize = fpSize;
+        return 0;
+      } else {
+        CHECK_FATAL(numRegs <= kTwoRegister, "LocateNextParm: illegal number of regs");
+        if (numRegs == kOneRegister) {
+          pLoc.reg0 = AllocateGPRegister();
         } else {
-          CHECK_FATAL(numRegs <= kTwoRegister, "LocateNextParm: illegal number of regs");
-          if (numRegs == kOneRegister) {
-            pLoc.reg0 = AllocateGPRegister();
-          } else {
-            AllocateTwoGPRegisters(pLoc);
-          }
-          return 0;
+          AllocateTwoGPRegisters(pLoc);
         }
-
+        return 0;
+      }
     }
   }
   uint64 typeSize = beCommon.GetTypeSize(mirType.GetTypeIndex());
@@ -540,7 +522,8 @@ int32 ParmLocator::ProcessPtyAggWhenLocateNextParm(MIRType &mirType, PLocInfo &p
   }
 
   uint32 fpSize;
-  int32 numRegs = ClassifyAggregate(beCommon, mirType, classes, sizeof(classes) / sizeof(AArch64ArgumentClass), fpSize);
+  uint32 numRegs = static_cast<uint32>(
+      ClassifyAggregate(beCommon, mirType, classes, sizeof(classes) / sizeof(AArch64ArgumentClass), fpSize));
   if (classes[0] == kAArch64FloatClass) {
     CHECK_FATAL(numRegs <= kMaxRegCount, "LocateNextParm: illegal number of regs");
     typeSize = k8ByteSize;
@@ -551,7 +534,7 @@ int32 ParmLocator::ProcessPtyAggWhenLocateNextParm(MIRType &mirType, PLocInfo &p
     /* passing in registers */
     typeSize = k8ByteSize;
     if (classes[0] == kAArch64FloatClass) {
-      CHECK_FATAL(0, "param passing in FP reg not allowed here");
+      CHECK_FATAL(false, "param passing in FP reg not allowed here");
     } else {
       pLoc.reg0 = AllocateGPRegister();
       ASSERT(nextGeneralRegNO == saveIntParmNum, "RegNo should be saved pramRegNO");
@@ -559,7 +542,7 @@ int32 ParmLocator::ProcessPtyAggWhenLocateNextParm(MIRType &mirType, PLocInfo &p
       ASSERT((pLoc.reg0 != kRinvalid) || (nextGeneralRegNO == AArch64Abi::kNumIntParmRegs),
              "reg0 should not be kRinvalid or nextGeneralRegNO should equal kNumIntParmRegs");
     }
-  } else if (numRegs == 2) {
+  } else if (numRegs == kTwoRegister) {
     ASSERT(classes[0] == kAArch64IntegerClass, "class 0 must be integer class");
     ASSERT(classes[1] == kAArch64IntegerClass, "class 1 must be integer class");
     AllocateTwoGPRegisters(pLoc);
@@ -606,7 +589,7 @@ int32 ParmLocator::ProcessPtyAggWhenLocateNextParm(MIRType &mirType, PLocInfo &p
  *   Passing, then the result is returned in the same registers
  *   as would be used for such an argument.
  */
-ReturnMechanism::ReturnMechanism(MIRType &retTy, BECommon &be)
+ReturnMechanism::ReturnMechanism(MIRType &retTy, const BECommon &be)
     : regCount(0), reg0(kRinvalid), reg1(kRinvalid), primTypeOfReg0(kPtyInvalid), primTypeOfReg1(kPtyInvalid) {
   PrimType pType = retTy.GetPrimType();
   switch (pType) {
@@ -685,19 +668,22 @@ ReturnMechanism::ReturnMechanism(MIRType &retTy, BECommon &be)
                                                       sizeof(classes) / sizeof(AArch64ArgumentClass), fpSize));
       if (classes[0] == kAArch64FloatClass) {
         switch (regCount) {
-        case 4:
-          reg3 = AArch64Abi::floatReturnRegs[3];
-        case 3:
-          reg2 = AArch64Abi::floatReturnRegs[2];
-        case 2:
-          reg1 = AArch64Abi::floatReturnRegs[1];
-        case 1:
-          reg0 = AArch64Abi::floatReturnRegs[0];
-          break;
-        default:
-          CHECK_FATAL(0, "ReturnMechanism: unsupported");
+          case kFourRegister:
+            reg3 = AArch64Abi::floatReturnRegs[3];
+            break;
+          case kThreeRegister:
+            reg2 = AArch64Abi::floatReturnRegs[2];
+            break;
+          case kTwoRegister:
+            reg1 = AArch64Abi::floatReturnRegs[1];
+            break;
+          case kOneRegister:
+            reg0 = AArch64Abi::floatReturnRegs[0];
+            break;
+          default:
+            CHECK_FATAL(0, "ReturnMechanism: unsupported");
         }
-        if (fpSize == 4) {
+        if (fpSize == k4ByteSize) {
           primTypeOfReg0 = primTypeOfReg1 = PTY_f32;
         } else {
           primTypeOfReg0 = primTypeOfReg1 = PTY_f64;
diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_args.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_args.cpp
index 2b5b999ed17e61f3870f0674df25b265236cc524..88a0414fa39154ae735ba792e7f76dbb2c83b02b 100644
--- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_args.cpp
+++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_args.cpp
@@ -30,7 +30,7 @@ void AArch64MoveRegArgs::CollectRegisterArgs(std::map<uint32, AArch64reg> &argsL
                                              std::vector<uint32> &numFpRegs,
                                              std::vector<uint32> &fpSize) const {
   AArch64CGFunc *aarchCGFunc = static_cast<AArch64CGFunc*>(cgFunc);
-  uint32 numFormal = aarchCGFunc->GetFunction().GetFormalCount();
+  uint32 numFormal = static_cast<uint32>(aarchCGFunc->GetFunction().GetFormalCount());
   numFpRegs.resize(numFormal);
   fpSize.resize(numFormal);
   ParmLocator parmlocator(aarchCGFunc->GetBecommon());
@@ -62,7 +62,7 @@ void AArch64MoveRegArgs::CollectRegisterArgs(std::map<uint32, AArch64reg> &argsL
       continue;
     }
     if (ploc.numFpPureRegs) {
-      uint32 index = indexList.size() - 1;
+      uint32 index = static_cast<uint32>(indexList.size()) - 1;
       numFpRegs[index] = ploc.numFpPureRegs;
       fpSize[index] = ploc.fpSize;
       continue;
@@ -245,15 +245,15 @@ void AArch64MoveRegArgs::GenerateStrInsn(ArgInfo &argInfo, AArch64reg reg2, uint
     GenOneInsn(argInfo, *baseOpnd, part2BitSize, reg2, (stOffset + kSizeOfPtr));
   } else if (numFpRegs > 1) {
     uint32 fpSizeBits = fpSize * kBitsPerByte;
-    AArch64reg regFp2 = static_cast<AArch64reg>(static_cast<int>(argInfo.reg) + 1);
-    GenOneInsn(argInfo, *baseOpnd, fpSizeBits, regFp2, (stOffset + fpSize));
+    AArch64reg regFp2 = static_cast<AArch64reg>(static_cast<int>(argInfo.reg) + static_cast<int>(k4BitShift));
+    GenOneInsn(argInfo, *baseOpnd, fpSizeBits, regFp2, (stOffset + static_cast<int>(fpSize)));
     if (numFpRegs > 2) {
       AArch64reg regFp3 = static_cast<AArch64reg>(static_cast<int>(argInfo.reg) + 2);
-      GenOneInsn(argInfo, *baseOpnd, fpSizeBits, regFp3, (stOffset + (fpSize * 2)));
+      GenOneInsn(argInfo, *baseOpnd, fpSizeBits, regFp3, (stOffset + static_cast<int>(fpSize * k4BitShift)));
     }
     if (numFpRegs > 3) {
       AArch64reg regFp3 = static_cast<AArch64reg>(static_cast<int>(argInfo.reg) + 3);
-      GenOneInsn(argInfo, *baseOpnd, fpSizeBits, regFp3, (stOffset + (fpSize * 3)));
+      GenOneInsn(argInfo, *baseOpnd, fpSizeBits, regFp3, (stOffset + static_cast<int>(fpSize * k8BitShift)));
     }
   }
 }
@@ -284,8 +284,8 @@ void AArch64MoveRegArgs::MoveRegisterArgs() {
       secondArgInfo.reg = (firstArgInfo.doMemPairOpt) ? pairReg[firstIndex] : movePara[secondIndex];
       secondArgInfo.symSize = (firstArgInfo.doMemPairOpt) ? firstArgInfo.memPairSecondRegSize : secondArgInfo.symSize;
       secondArgInfo.symLoc = (firstArgInfo.doMemPairOpt) ? secondArgInfo.symLoc :
-                                 static_cast<AArch64SymbolAlloc *>(aarchCGFunc->GetMemlayout()->GetSymAllocInfo(
-                                     secondArgInfo.sym->GetStIndex()));
+          static_cast<AArch64SymbolAlloc *>(aarchCGFunc->GetMemlayout()->GetSymAllocInfo(
+              secondArgInfo.sym->GetStIndex()));
       /* Make sure they are in same segment if want to use stp */
       if (IsInSameSegment(firstArgInfo, secondArgInfo)) {
         GenerateStpInsn(firstArgInfo, secondArgInfo);
diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp
index 62b549696f821692d3b04e981f7b7ad575455549..ae4ddad5a48eb3f1e50fdda787fc0d28b53602d2 100644
--- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp
+++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp
@@ -1080,30 +1080,30 @@ void AArch64CGFunc::SelectAggDassign(DassignNode &stmt) {
           uint32 memSize;
           uint32 regSize;
           parmlocator.LocateRetVal(*lhsType, pLoc);
-          AArch64reg r[4];
+          AArch64reg r[kFourRegister];
           r[0] = pLoc.reg0;
           r[1] = pLoc.reg1;
           r[2] = pLoc.reg2;
           r[3] = pLoc.reg3;
           if (pLoc.numFpPureRegs) {
-            regSize = (pLoc.fpSize == 4) ? 32 : 64;
+            regSize = (pLoc.fpSize == k4ByteSize) ? k32BitSize : k64BitSize;
             memSize = pLoc.fpSize;
-            retPtype = (pLoc.fpSize == 4) ? PTY_f32 : PTY_f64;
+            retPtype = (pLoc.fpSize == k4ByteSize) ? PTY_f32 : PTY_f64;
             regType = kRegTyFloat;
           } else {
-            regSize = 64;
-            memSize = 8;
+            regSize = k64BitSize;
+            memSize = k8BitSize;
             retPtype = PTY_u64;
             regType = kRegTyInt;
           }
-          for (uint32 i = 0; i < 4; ++i) {
+          for (uint32 i = 0; i < kFourRegister; ++i) {
             if (r[i] == kRinvalid) {
               break;
             }
             RegOperand &parm = GetOrCreatePhysicalRegisterOperand(r[i], regSize, regType);
             Operand &mOpnd = GetOrCreateMemOpnd(*lhsSymbol, memSize * i, regSize);
             GetCurBB()->AppendInsn(GetCG()->BuildInstruction<AArch64Insn>(PickStInsn(regSize, retPtype), parm, mOpnd));
-           }
+          }
           isRet = true;
         }
       }
@@ -1246,7 +1246,7 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) {
       PLocInfo pLoc;
       MIRSymbol *retSt = GetBecommon().GetMIRModule().CurFunction()->GetFormal(0);
       if (retSt == addrSym) {
-        // return value
+        /* return value */
         parmlocator.LocateNextParm(*lhsType, pLoc, true);
       } else {
         parmlocator.InitPLocInfo(pLoc);
@@ -1274,10 +1274,12 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) {
       bool parmCopy = IsParamStructCopy(*rhsSymbol);
       for (uint32 i = 0; i < numRegs; i++) {
         if (parmCopy) {
-          rhsmemopnd = &LoadStructCopyBase(*rhsSymbol, (rhsOffset + i * (fpParm ? loadSize : k8ByteSize)),
-                                           (loadSize * kBitsPerByte));
+          rhsmemopnd = &LoadStructCopyBase(*rhsSymbol,
+                                           (rhsOffset + static_cast<int32>(i * (fpParm ? loadSize : k8ByteSize))),
+                                           static_cast<int>(loadSize * kBitsPerByte));
         } else {
-          rhsmemopnd = &GetOrCreateMemOpnd(*rhsSymbol, (rhsOffset + i * (fpParm ? loadSize : k8ByteSize)),
+          rhsmemopnd = &GetOrCreateMemOpnd(*rhsSymbol,
+                                           (rhsOffset + static_cast<int32>(i * (fpParm ? loadSize : k8ByteSize))),
                                            (loadSize * kBitsPerByte));
         }
         result[i] = &CreateVirtualRegisterOperand(NewVReg(regType, loadSize));
@@ -1298,7 +1300,7 @@ void AArch64CGFunc::SelectAggIassign(IassignNode &stmt, Operand &AddrOpnd) {
           mop2 = (loadSize == k4ByteSize) ? MOP_xvmovs : MOP_xvmovd;
         } else {
           preg = (i == 0 ? R0 : R1);
-          mop2 = (loadSize == k4ByteSize) ? MOP_wmovrr: MOP_xmovrr;
+          mop2 = (loadSize == k4ByteSize) ? MOP_wmovrr : MOP_xmovrr;
         }
         RegOperand &dest = GetOrCreatePhysicalRegisterOperand(preg, (loadSize * kBitsPerByte), regType);
         Insn &mov = GetCG()->BuildInstruction<AArch64Insn>(mop2, dest, *(result[i]));
@@ -1914,8 +1916,7 @@ Operand *SelectLiteral(T *c, MIRFunction *func, uint32 labelIdx, AArch64CGFunc *
   st->SetTyIdx(TyIdx(primType));
   uint32 typeBitSize = GetPrimTypeBitSize(primType);
 
-  if (cgFunc->GetMirModule().IsCModule() &&
-      (T::GetPrimType() == PTY_f32 || T::GetPrimType() == PTY_f64)) {
+  if (cgFunc->GetMirModule().IsCModule() && (T::GetPrimType() == PTY_f32 || T::GetPrimType() == PTY_f64)) {
     return static_cast<Operand *>(&cgFunc->GetOrCreateMemOpnd(*st, 0, typeBitSize));
   }
   if (T::GetPrimType() == PTY_f32) {
@@ -4004,8 +4005,9 @@ void AArch64CGFunc::SelectAArch64Select(Operand &dest, Operand &o0, Operand &o1,
                              : ((dsize == k64BitSize) ? MOP_dcselrrrc
                                                       : ((dsize == k32BitSize) ? MOP_scselrrrc : MOP_hcselrrrc));
   if (o1.IsImmediate()) {
-    uint32 movOp = (dsize == 64 ? MOP_xmovri64 : MOP_xmovri32);
-    RegOperand &movDest = CreateVirtualRegisterOperand(NewVReg(kRegTyInt, (dsize == k64BitSize) ? k8ByteSize : k4ByteSize));
+    uint32 movOp = (dsize == k64BitSize ? MOP_xmovri64 : MOP_xmovri32);
+    RegOperand &movDest = CreateVirtualRegisterOperand(
+        NewVReg(kRegTyInt, (dsize == k64BitSize) ? k8ByteSize : k4ByteSize));
     GetCurBB()->AppendInsn(GetCG()->BuildInstruction<AArch64Insn>(movOp, movDest, o1));
     GetCurBB()->AppendInsn(GetCG()->BuildInstruction<AArch64Insn>(mOpCode, dest, o0, movDest, cond));
     return;
@@ -5082,25 +5084,26 @@ void AArch64CGFunc::SelectParmListDreadSmallAggregate(MIRSymbol &sym, MIRType &s
     if (ploc.fpSize == 0) {
       state = kNotFp;
       memSize = k64BitSize;
-    } else if (ploc.fpSize == 4) {
+    } else if (ploc.fpSize == k4ByteSize) {
       state = kFp32Bit;
       memSize = k32BitSize;
-    } else if (ploc.fpSize == 8) {
+    } else if (ploc.fpSize == k8ByteSize) {
       state = kFp64Bit;
       memSize = k64BitSize;
     }
     MemOperand &mopnd0 = GetOrCreateMemOpnd(sym, 0, memSize);
     CreateCallStructParamPassByReg(ploc.reg0, mopnd0, srcOpnds, state);
     if (ploc.reg1) {
-      MemOperand &mopnd1 = GetOrCreateMemOpnd(sym, (ploc.fpSize ? ploc.fpSize : kSizeOfPtr), memSize);
+      MemOperand &mopnd1 = GetOrCreateMemOpnd(sym,
+          static_cast<int32>(ploc.fpSize ? ploc.fpSize : kSizeOfPtr), memSize);
       CreateCallStructParamPassByReg(ploc.reg1, mopnd1, srcOpnds, state);
     }
     if (ploc.reg2) {
-      MemOperand &mopnd2 = GetOrCreateMemOpnd(sym, (ploc.fpSize ? (ploc.fpSize * 2) : kSizeOfPtr), memSize);
+      MemOperand &mopnd2 = GetOrCreateMemOpnd(sym, (ploc.fpSize ? (ploc.fpSize * k4BitShift) : kSizeOfPtr), memSize);
       CreateCallStructParamPassByReg(ploc.reg2, mopnd2, srcOpnds, state);
     }
     if (ploc.reg3) {
-      MemOperand &mopnd3 = GetOrCreateMemOpnd(sym, (ploc.fpSize ? (ploc.fpSize * 3) : kSizeOfPtr), memSize);
+      MemOperand &mopnd3 = GetOrCreateMemOpnd(sym, (ploc.fpSize ? (ploc.fpSize * k8BitShift) : kSizeOfPtr), memSize);
       CreateCallStructParamPassByReg(ploc.reg3, mopnd3, srcOpnds, state);
     }
   }
@@ -5121,18 +5124,20 @@ void AArch64CGFunc::SelectParmListIreadSmallAggregate(const IreadNode &iread, MI
     fpParamState state = kStateUnknown;
     uint32 memSize = 0;
     switch (ploc.fpSize) {
-    case 0:
-      state = kNotFp;
-      memSize = k64BitSize;
-      break;
-    case 4:
-      state = kFp32Bit;
-      memSize = k32BitSize;
-      break;
-    case 8:
-      state = kFp64Bit;
-      memSize = k64BitSize;
-      break;
+      case k0BitSize:
+        state = kNotFp;
+        memSize = k64BitSize;
+        break;
+      case k4BitSize:
+        state = kFp32Bit;
+        memSize = k32BitSize;
+        break;
+      case k8BitSize:
+        state = kFp64Bit;
+        memSize = k64BitSize;
+        break;
+      default:
+        break;
     }
     AArch64OfstOperand *offOpnd0 = &GetOrCreateOfstOpnd(0, k32BitSize);
     MemOperand *mopnd =
@@ -5144,12 +5149,14 @@ void AArch64CGFunc::SelectParmListIreadSmallAggregate(const IreadNode &iread, MI
       CreateCallStructParamPassByReg(ploc.reg1, *mopnd, srcOpnds, state);
     }
     if (ploc.reg2) {
-      AArch64OfstOperand *offOpnd2 = &GetOrCreateOfstOpnd((ploc.fpSize ? (ploc.fpSize * 2): kSizeOfPtr), k32BitSize);
+      AArch64OfstOperand *offOpnd2 =
+          &GetOrCreateOfstOpnd((ploc.fpSize ? (ploc.fpSize * k4BitShift) : kSizeOfPtr), k32BitSize);
       mopnd = &GetOrCreateMemOpnd(AArch64MemOperand::kAddrModeBOi, memSize, addrOpnd1, nullptr, offOpnd2, nullptr);
       CreateCallStructParamPassByReg(ploc.reg2, *mopnd, srcOpnds, state);
     }
     if (ploc.reg3) {
-      AArch64OfstOperand *offOpnd3 = &GetOrCreateOfstOpnd((ploc.fpSize ? (ploc.fpSize * 3): kSizeOfPtr), k32BitSize);
+      AArch64OfstOperand *offOpnd3 =
+          &GetOrCreateOfstOpnd((ploc.fpSize ? (ploc.fpSize * k8BitShift) : kSizeOfPtr), k32BitSize);
       mopnd = &GetOrCreateMemOpnd(AArch64MemOperand::kAddrModeBOi, memSize, addrOpnd1, nullptr, offOpnd3, nullptr);
       CreateCallStructParamPassByReg(ploc.reg3, *mopnd, srcOpnds, state);
     }
@@ -5187,7 +5194,6 @@ void AArch64CGFunc::SelectParmListDreadLargeAggregate(MIRSymbol &sym, MIRType &s
     srcOpnds.PushOpnd(*parmOpnd);
   }
   structCopyOffset += (numMemOp * kSizeOfPtr);
-//GetCurBB()->Dump();
 }
 
 void AArch64CGFunc::SelectParmListIreadLargeAggregate(const IreadNode &iread, MIRType &structType,
@@ -5314,7 +5320,7 @@ void AArch64CGFunc::CreateCallStructParamMemcpy(const MIRSymbol *sym, RegOperand
 }
 
 AArch64RegOperand *AArch64CGFunc::CreateCallStructParamCopyToStack(uint32 numMemOp, MIRSymbol *sym, RegOperand *addrOpd,
-                                                                   int32 copyOffset, PLocInfo &ploc) {
+                                                                   int32 copyOffset, const PLocInfo &ploc) {
   /* Create the struct copies. */
   MemOperand *ldMopnd = nullptr;
   MemOperand *stMopnd = nullptr;
diff --git a/src/mapleall/maple_be/src/cg/emit.cpp b/src/mapleall/maple_be/src/cg/emit.cpp
index 9315c5388084d5564910e4d8205744e689922061..c73652df3540b25ad9676cd722a0ac0f0daeec76 100644
--- a/src/mapleall/maple_be/src/cg/emit.cpp
+++ b/src/mapleall/maple_be/src/cg/emit.cpp
@@ -288,10 +288,10 @@ void Emitter::EmitAsmLabel(const MIRSymbol &mirSymbol, AsmLabel label) {
 #if PECOFF
 #if TARGARM || TARGAARCH64 || TARGARK || TARGRISCV64
       std::string align = std::to_string(
-        static_cast<int>(log2(Globals::GetInstance()->GetBECommon()->GetTypeAlign(mirType->GetTypeIndex()))));
+          static_cast<int>(log2(Globals::GetInstance()->GetBECommon()->GetTypeAlign(mirType->GetTypeIndex()))));
 #else
       std::string align = std::to_string(
-        Globals::GetInstance()->GetBECommon()->GetTypeAlign(mirType->GetTypeIndex()));
+          Globals::GetInstance()->GetBECommon()->GetTypeAlign(mirType->GetTypeIndex()));
 #endif
       emit(align.c_str());
 #else /* ELF */
diff --git a/src/mapleall/maple_ir/src/mir_parser.cpp b/src/mapleall/maple_ir/src/mir_parser.cpp
index 6cc71d554060146c680a332b80808faaf5731bc7..0f0392eec4ebf63cd70345ce143fd2b1e9e5a62c 100644
--- a/src/mapleall/maple_ir/src/mir_parser.cpp
+++ b/src/mapleall/maple_ir/src/mir_parser.cpp
@@ -2606,7 +2606,7 @@ bool MIRParser::ParseScalarValue(MIRConstPtr &stype, MIRType &type) {
       Error("constant value incompatible with integer type at ");
       return false;
     }
-    stype = mod.GetMemPool()->New<MIRIntConst>(lexer.GetTheIntVal(), type);
+    stype = GlobalTables::GetIntConstTable().GetOrCreateIntConst(lexer.GetTheIntVal(), type);
   } else if (ptp == PTY_f32) {
     if (lexer.GetTokenKind() != TK_floatconst) {
       Error("constant value incompatible with single-precision float type at ");