From acf46d62674a5bd551727a7a18de92563ae4efc4 Mon Sep 17 00:00:00 2001 From: "@evian_hill" Date: Sat, 29 May 2021 17:15:07 +0800 Subject: [PATCH 1/2] use list store workList in PRE, reserve iread(add(dread/regread, constval)) in epre --- src/mapleall/maple_me/include/ssa_pre.h | 2 +- src/mapleall/maple_me/src/me_ssa_lpre.cpp | 8 ++++-- src/mapleall/maple_me/src/ssa_epre.cpp | 13 ++++++++- src/mapleall/maple_me/src/ssa_pre.cpp | 34 ++++++++++++++++------- 4 files changed, 43 insertions(+), 14 deletions(-) diff --git a/src/mapleall/maple_me/include/ssa_pre.h b/src/mapleall/maple_me/include/ssa_pre.h index f34556ed1d..8997182e44 100644 --- a/src/mapleall/maple_me/include/ssa_pre.h +++ b/src/mapleall/maple_me/include/ssa_pre.h @@ -211,7 +211,7 @@ class SSAPre { MapleAllocator ssaPreAllocator; MemPool *perCandMemPool; MapleAllocator perCandAllocator; - MapleVector workList; + MapleList workList; PreWorkCand *workCand = nullptr; // the current PreWorkCand PreKind preKind; diff --git a/src/mapleall/maple_me/src/me_ssa_lpre.cpp b/src/mapleall/maple_me/src/me_ssa_lpre.cpp index 8734c39408..5bc004bd5f 100644 --- a/src/mapleall/maple_me/src/me_ssa_lpre.cpp +++ b/src/mapleall/maple_me/src/me_ssa_lpre.cpp @@ -260,8 +260,12 @@ void MeSSALPre::BuildWorkListLHSOcc(MeStmt &meStmt, int32 seqStmt) { void MeSSALPre::CreateMembarOccAtCatch(BB &bb) { // go thru all workcands and insert a membar occurrence for each of them - for (size_t i = 0; i < workList.size() && i <= preLimit; ++i) { - PreWorkCand *workCand = workList[i]; + uint32 cnt = 0; + for (PreWorkCand *workCand : workList) { + ++cnt; + if (cnt > preLimit) { + break; + } MeRealOcc *newOcc = ssaPreMemPool->New(nullptr, 0, workCand->GetTheMeExpr()); newOcc->SetOccType(kOccMembar); newOcc->SetBB(bb); diff --git a/src/mapleall/maple_me/src/ssa_epre.cpp b/src/mapleall/maple_me/src/ssa_epre.cpp index f983a19f79..8e8860272d 100644 --- a/src/mapleall/maple_me/src/ssa_epre.cpp +++ b/src/mapleall/maple_me/src/ssa_epre.cpp @@ -372,6 +372,14 @@ void SSAEPre::BuildWorkListExpr(MeStmt &meStmt, int32 seqStmt, MeExpr &meExpr, b break; } if (!base->IsLeaf()) { + if (!isRebuild || base->IsUseSameSymbol(*tempVar)) { + if (base->GetOp() == OP_add && + (base->GetOpnd(0)->GetOp() == OP_dread || base->GetOpnd(0)->GetOp() == OP_regread) && + base->GetOpnd(1)->GetOp() == OP_constval) { + (void)CreateRealOcc(meStmt, seqStmt, meExpr, isRebuild); + break; + } + } BuildWorkListExpr(meStmt, seqStmt, *ivarMeExpr->GetBase(), isRebuild, tempVar, false); } else if (ivarMeExpr->IsVolatile()) { break; @@ -460,10 +468,13 @@ void SSAEPre::CollectVarForMeExpr(MeExpr &meExpr, std::vector &varVec) case kMeOpIvar: { auto *ivarMeExpr = static_cast(&meExpr); CHECK_FATAL(ivarMeExpr->GetBase()->GetMeOp() == kMeOpVar || ivarMeExpr->GetBase()->GetMeOp() == kMeOpConst || - ivarMeExpr->GetBase()->GetMeOp() == kMeOpAddrof || ivarMeExpr->GetBase()->GetMeOp() == kMeOpReg, + ivarMeExpr->GetBase()->GetMeOp() == kMeOpAddrof || ivarMeExpr->GetBase()->GetMeOp() == kMeOpReg || + ivarMeExpr->GetBase()->GetOp() == OP_add, "ivarMeExpr not first order expr"); if (ivarMeExpr->GetBase()->GetMeOp() == kMeOpVar || ivarMeExpr->GetBase()->GetMeOp() == kMeOpReg) { varVec.push_back(ivarMeExpr->GetBase()); + } else if (ivarMeExpr->GetBase()->GetOp() == OP_add) { + CollectVarForMeExpr(*ivarMeExpr->GetOpnd(0), varVec); } // in case of lhs occurrence, mu can be nullptr, and can use nullptr as value varVec.push_back(ivarMeExpr->GetMu()); diff --git a/src/mapleall/maple_me/src/ssa_pre.cpp b/src/mapleall/maple_me/src/ssa_pre.cpp index a393f2a43f..71de6e4a1d 100644 --- a/src/mapleall/maple_me/src/ssa_pre.cpp +++ b/src/mapleall/maple_me/src/ssa_pre.cpp @@ -1343,7 +1343,7 @@ MeRealOcc *SSAPre::CreateRealOcc(MeStmt &meStmt, int seqStmt, MeExpr &meExpr, bo bool isFinal = fldPair.second.GetAttr(FLDATTR_final); wkCand->SetNeedLocalRefVar(ty->GetPrimType() == PTY_ref && !isFinal); } - workList.push_back(wkCand); + workList.push_front(wkCand); wkCand->AddRealOccAsLast(*newOcc, GetPUIdx()); // add to bucket at workcandHashTable[hashIdx] wkCand->SetNext(*preWorkCandHashTable.GetWorkcandFromIndex(hashIdx)); @@ -1356,8 +1356,12 @@ void SSAPre::CreateMembarOcc(MeStmt &meStmt, int seqStmt) { return; } // go thru all workcands and insert a membar occurrence for each of them - for (size_t i = 0; i < workList.size() && i <= preLimit; i++) { - PreWorkCand *wkCand = workList[i]; + uint32 cnt = 0; + for (PreWorkCand *wkCand : workList) { + ++cnt; + if (cnt > preLimit) { + break; + } if (preKind == kExprPre) { if (wkCand->GetTheMeExpr()->GetMeOp() != kMeOpIvar) { continue; @@ -1375,8 +1379,12 @@ void SSAPre::CreateMembarOcc(MeStmt &meStmt, int seqStmt) { void SSAPre::CreateMembarOccAtCatch(BB &bb) { // go thru all workcands and insert a membar occurrence for each of them - for (size_t i = 0; i < workList.size() && i <= preLimit; i++) { - PreWorkCand *wkCand = workList[i]; + uint32 cnt = 0; + for (PreWorkCand *wkCand : workList) { + ++cnt; + if (cnt > preLimit) { + break; + } MeRealOcc *newOcc = ssaPreMemPool->New(nullptr, 0, wkCand->GetTheMeExpr()); newOcc->SetOccType(kOccMembar); newOcc->SetBB(bb); @@ -1595,8 +1603,7 @@ void SSAPre::DumpWorkListWrap() const { void SSAPre::DumpWorkList() const { mirModule->GetOut() << "======== in SSAPRE worklist==============\n"; - for (size_t i = 0; i < workList.size(); i++) { - PreWorkCand *workListCand = workList[i]; + for (PreWorkCand *workListCand : workList) { workListCand->Dump(*irMap); } } @@ -1614,8 +1621,14 @@ void SSAPre::ApplySSAPRE() { mirModule->GetOut() << " worklist initial size " << workList.size() << '\n'; } ConstructUseOccurMap(); - for (size_t i = 0; i < workList.size() && i <= preLimit; i++) { - workCand = workList[i]; + uint32 cnt = 0; + while (!workList.empty()) { + ++cnt; + if (cnt > preLimit) { + break; + } + workCand = workList.front(); + workList.pop_front; if (workCand->GetRealOccs().empty()) { continue; } @@ -1633,7 +1646,8 @@ void SSAPre::ApplySSAPRE() { } } if (GetSSAPreDebug()) { - mirModule->GetOut() << "||||||| SSAPRE candidate " << i << " at worklist index " << workCand->GetIndex() << ": "; + mirModule->GetOut() << "||||||| SSAPRE candidate " << cnt << " at worklist index " + << workCand->GetIndex() << ": "; workCand->DumpCand(*irMap); mirModule->GetOut() << '\n'; } -- Gitee From 826383e8a3278361a24f88e688e7406b54b9bc3e Mon Sep 17 00:00:00 2001 From: "@evian_hill" Date: Sat, 29 May 2021 17:15:07 +0800 Subject: [PATCH 2/2] use list store workList in PRE, reserve iread(add(dread/regread, constval)) in epre --- src/mapleall/maple_me/include/ssa_pre.h | 2 +- src/mapleall/maple_me/src/me_ssa_lpre.cpp | 8 ++++-- src/mapleall/maple_me/src/ssa_epre.cpp | 13 ++++++++- src/mapleall/maple_me/src/ssa_pre.cpp | 34 ++++++++++++++++------- 4 files changed, 43 insertions(+), 14 deletions(-) diff --git a/src/mapleall/maple_me/include/ssa_pre.h b/src/mapleall/maple_me/include/ssa_pre.h index f34556ed1d..8997182e44 100644 --- a/src/mapleall/maple_me/include/ssa_pre.h +++ b/src/mapleall/maple_me/include/ssa_pre.h @@ -211,7 +211,7 @@ class SSAPre { MapleAllocator ssaPreAllocator; MemPool *perCandMemPool; MapleAllocator perCandAllocator; - MapleVector workList; + MapleList workList; PreWorkCand *workCand = nullptr; // the current PreWorkCand PreKind preKind; diff --git a/src/mapleall/maple_me/src/me_ssa_lpre.cpp b/src/mapleall/maple_me/src/me_ssa_lpre.cpp index 8734c39408..5bc004bd5f 100644 --- a/src/mapleall/maple_me/src/me_ssa_lpre.cpp +++ b/src/mapleall/maple_me/src/me_ssa_lpre.cpp @@ -260,8 +260,12 @@ void MeSSALPre::BuildWorkListLHSOcc(MeStmt &meStmt, int32 seqStmt) { void MeSSALPre::CreateMembarOccAtCatch(BB &bb) { // go thru all workcands and insert a membar occurrence for each of them - for (size_t i = 0; i < workList.size() && i <= preLimit; ++i) { - PreWorkCand *workCand = workList[i]; + uint32 cnt = 0; + for (PreWorkCand *workCand : workList) { + ++cnt; + if (cnt > preLimit) { + break; + } MeRealOcc *newOcc = ssaPreMemPool->New(nullptr, 0, workCand->GetTheMeExpr()); newOcc->SetOccType(kOccMembar); newOcc->SetBB(bb); diff --git a/src/mapleall/maple_me/src/ssa_epre.cpp b/src/mapleall/maple_me/src/ssa_epre.cpp index f983a19f79..8e8860272d 100644 --- a/src/mapleall/maple_me/src/ssa_epre.cpp +++ b/src/mapleall/maple_me/src/ssa_epre.cpp @@ -372,6 +372,14 @@ void SSAEPre::BuildWorkListExpr(MeStmt &meStmt, int32 seqStmt, MeExpr &meExpr, b break; } if (!base->IsLeaf()) { + if (!isRebuild || base->IsUseSameSymbol(*tempVar)) { + if (base->GetOp() == OP_add && + (base->GetOpnd(0)->GetOp() == OP_dread || base->GetOpnd(0)->GetOp() == OP_regread) && + base->GetOpnd(1)->GetOp() == OP_constval) { + (void)CreateRealOcc(meStmt, seqStmt, meExpr, isRebuild); + break; + } + } BuildWorkListExpr(meStmt, seqStmt, *ivarMeExpr->GetBase(), isRebuild, tempVar, false); } else if (ivarMeExpr->IsVolatile()) { break; @@ -460,10 +468,13 @@ void SSAEPre::CollectVarForMeExpr(MeExpr &meExpr, std::vector &varVec) case kMeOpIvar: { auto *ivarMeExpr = static_cast(&meExpr); CHECK_FATAL(ivarMeExpr->GetBase()->GetMeOp() == kMeOpVar || ivarMeExpr->GetBase()->GetMeOp() == kMeOpConst || - ivarMeExpr->GetBase()->GetMeOp() == kMeOpAddrof || ivarMeExpr->GetBase()->GetMeOp() == kMeOpReg, + ivarMeExpr->GetBase()->GetMeOp() == kMeOpAddrof || ivarMeExpr->GetBase()->GetMeOp() == kMeOpReg || + ivarMeExpr->GetBase()->GetOp() == OP_add, "ivarMeExpr not first order expr"); if (ivarMeExpr->GetBase()->GetMeOp() == kMeOpVar || ivarMeExpr->GetBase()->GetMeOp() == kMeOpReg) { varVec.push_back(ivarMeExpr->GetBase()); + } else if (ivarMeExpr->GetBase()->GetOp() == OP_add) { + CollectVarForMeExpr(*ivarMeExpr->GetOpnd(0), varVec); } // in case of lhs occurrence, mu can be nullptr, and can use nullptr as value varVec.push_back(ivarMeExpr->GetMu()); diff --git a/src/mapleall/maple_me/src/ssa_pre.cpp b/src/mapleall/maple_me/src/ssa_pre.cpp index a393f2a43f..342297aa07 100644 --- a/src/mapleall/maple_me/src/ssa_pre.cpp +++ b/src/mapleall/maple_me/src/ssa_pre.cpp @@ -1343,7 +1343,7 @@ MeRealOcc *SSAPre::CreateRealOcc(MeStmt &meStmt, int seqStmt, MeExpr &meExpr, bo bool isFinal = fldPair.second.GetAttr(FLDATTR_final); wkCand->SetNeedLocalRefVar(ty->GetPrimType() == PTY_ref && !isFinal); } - workList.push_back(wkCand); + workList.push_front(wkCand); wkCand->AddRealOccAsLast(*newOcc, GetPUIdx()); // add to bucket at workcandHashTable[hashIdx] wkCand->SetNext(*preWorkCandHashTable.GetWorkcandFromIndex(hashIdx)); @@ -1356,8 +1356,12 @@ void SSAPre::CreateMembarOcc(MeStmt &meStmt, int seqStmt) { return; } // go thru all workcands and insert a membar occurrence for each of them - for (size_t i = 0; i < workList.size() && i <= preLimit; i++) { - PreWorkCand *wkCand = workList[i]; + uint32 cnt = 0; + for (PreWorkCand *wkCand : workList) { + ++cnt; + if (cnt > preLimit) { + break; + } if (preKind == kExprPre) { if (wkCand->GetTheMeExpr()->GetMeOp() != kMeOpIvar) { continue; @@ -1375,8 +1379,12 @@ void SSAPre::CreateMembarOcc(MeStmt &meStmt, int seqStmt) { void SSAPre::CreateMembarOccAtCatch(BB &bb) { // go thru all workcands and insert a membar occurrence for each of them - for (size_t i = 0; i < workList.size() && i <= preLimit; i++) { - PreWorkCand *wkCand = workList[i]; + uint32 cnt = 0; + for (PreWorkCand *wkCand : workList) { + ++cnt; + if (cnt > preLimit) { + break; + } MeRealOcc *newOcc = ssaPreMemPool->New(nullptr, 0, wkCand->GetTheMeExpr()); newOcc->SetOccType(kOccMembar); newOcc->SetBB(bb); @@ -1595,8 +1603,7 @@ void SSAPre::DumpWorkListWrap() const { void SSAPre::DumpWorkList() const { mirModule->GetOut() << "======== in SSAPRE worklist==============\n"; - for (size_t i = 0; i < workList.size(); i++) { - PreWorkCand *workListCand = workList[i]; + for (PreWorkCand *workListCand : workList) { workListCand->Dump(*irMap); } } @@ -1614,8 +1621,14 @@ void SSAPre::ApplySSAPRE() { mirModule->GetOut() << " worklist initial size " << workList.size() << '\n'; } ConstructUseOccurMap(); - for (size_t i = 0; i < workList.size() && i <= preLimit; i++) { - workCand = workList[i]; + uint32 cnt = 0; + while (!workList.empty()) { + ++cnt; + if (cnt > preLimit) { + break; + } + workCand = workList.front(); + workList.pop_front(); if (workCand->GetRealOccs().empty()) { continue; } @@ -1633,7 +1646,8 @@ void SSAPre::ApplySSAPRE() { } } if (GetSSAPreDebug()) { - mirModule->GetOut() << "||||||| SSAPRE candidate " << i << " at worklist index " << workCand->GetIndex() << ": "; + mirModule->GetOut() << "||||||| SSAPRE candidate " << cnt << " at worklist index " + << workCand->GetIndex() << ": "; workCand->DumpCand(*irMap); mirModule->GetOut() << '\n'; } -- Gitee