From 500ca76e118023822d03beef3be430fbeddb63f2 Mon Sep 17 00:00:00 2001
From: Alfred Huang <ahuang@futurewei.com>
Date: Wed, 25 Aug 2021 00:05:35 -0700
Subject: [PATCH] Fixed CombineMultiplyAdd/Sub/Neg() to get rid of extra
 multiply.  Added convert multiply to shift.

---
 .../include/cg/aarch64/aarch64_peep.h         |  8 +++++
 .../maple_be/src/cg/aarch64/aarch64_ebo.cpp   |  9 ++++++
 .../maple_be/src/cg/aarch64/aarch64_peep.cpp  | 32 +++++++++++++++++++
 3 files changed, 49 insertions(+)

diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_peep.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_peep.h
index b78fff7f40..6c21e60b8f 100644
--- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_peep.h
+++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_peep.h
@@ -230,6 +230,13 @@ class ReplaceDivToMultiAArch64 : public PeepPattern {
   void Run(BB &bb, Insn &insn) override;
 };
 
+class ReduceMultToShiftAArch64 : public PeepPattern {
+ public:
+  explicit ReduceMultToShiftAArch64(CGFunc &cgFunc) : PeepPattern(cgFunc) {}
+  ~ReduceMultToShiftAArch64() override = default;
+  void Run(BB &bb, Insn &insn) override;
+};
+
 /*
  * Optimize the following patterns:
  *  and  w0, w0, #imm  ====> tst  w0, #imm
@@ -800,6 +807,7 @@ class AArch64PrePeepHole1 : public PeepPatternMatch {
     kOneHoleBranchesOpt,
     kReplaceIncDecWithIncOpt,
     kAndCmpBranchesToTbzOpt,
+    kReduceMultToShiftOpt,
     kPeepholeOptsNum
   };
 };
diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp
index e43e6e17fa..576cf961e3 100644
--- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp
+++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_ebo.cpp
@@ -833,6 +833,9 @@ bool AArch64Ebo::CombineMultiplyAdd(Insn *insn, const Insn *prevInsn, InsnInfo *
   if (((opndInfo1 != nullptr) && opndInfo1->redefined) || ((opndInfo2 != nullptr) && opndInfo2->redefined)) {
     return false;
   }
+  if (OperandLiveAfterInsn(static_cast<RegOperand&>(prevInsn->GetOperand(kInsnFirstOpnd)), *insn)) {
+    return false;
+  }
   Operand &res = insn->GetOperand(kInsnFirstOpnd);
   Operand &opnd1 = prevInsn->GetOperand(kInsnSecondOpnd);
   Operand &opnd2 = prevInsn->GetOperand(kInsnThirdOpnd);
@@ -883,6 +886,9 @@ bool AArch64Ebo::CombineMultiplySub(Insn *insn, OpndInfo *opndInfo, bool is64bit
     if (((opndInfo1 != nullptr) && opndInfo1->redefined) || ((opndInfo2 != nullptr) && opndInfo2->redefined)) {
       return false;
     }
+    if (OperandLiveAfterInsn(static_cast<RegOperand&>(insn1->GetOperand(kInsnFirstOpnd)), *insn)) {
+      return false;
+    }
     Operand &res = insn->GetOperand(kInsnFirstOpnd);
     Operand &opnd1 = insn1->GetOperand(kInsnSecondOpnd);
     Operand &opnd2 = insn1->GetOperand(kInsnThirdOpnd);
@@ -915,6 +921,9 @@ bool AArch64Ebo::CombineMultiplyNeg(Insn *insn, OpndInfo *opndInfo, bool is64bit
     if (((opndInfo1 != nullptr) && opndInfo1->redefined) || ((opndInfo2 != nullptr) && opndInfo2->redefined)) {
       return false;
     }
+    if (OperandLiveAfterInsn(static_cast<RegOperand&>(insn1->GetOperand(kInsnFirstOpnd)), *insn)) {
+      return false;
+    }
     Operand &res = insn->GetOperand(kInsnFirstOpnd);
     Operand &opnd1 = insn1->GetOperand(kInsnSecondOpnd);
     Operand &opnd2 = insn1->GetOperand(kInsnThirdOpnd);
diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_peep.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_peep.cpp
index d0f80682d8..b8e414342e 100644
--- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_peep.cpp
+++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_peep.cpp
@@ -309,6 +309,7 @@ void AArch64PrePeepHole1::InitOpts() {
   optimizations[kComputationTreeOpt] = optOwnMemPool->New<ComputationTreeAArch64>(cgFunc);
   optimizations[kOneHoleBranchesOpt] = optOwnMemPool->New<OneHoleBranchesAArch64>(cgFunc);
   optimizations[kReplaceIncDecWithIncOpt] = optOwnMemPool->New<ReplaceIncDecWithIncAArch64>(cgFunc);
+  optimizations[kReduceMultToShiftOpt] = optOwnMemPool->New<ReduceMultToShiftAArch64>(cgFunc);
   optimizations[kAndCmpBranchesToTbzOpt] = optOwnMemPool->New<AndCmpBranchesToTbzAArch64>(cgFunc);
 }
 
@@ -322,6 +323,11 @@ void AArch64PrePeepHole1::Run(BB &bb, Insn &insn) {
       }
       break;
     }
+    case MOP_wmulrrr:
+    case MOP_xmulrrr: {
+      (static_cast<ReduceMultToShiftAArch64*>(optimizations[kReduceMultToShiftOpt]))->Run(bb, insn);
+      break;
+    }
     case MOP_xaddrri12: {
       (static_cast<ComputationTreeAArch64*>(optimizations[kComputationTreeOpt]))->Run(bb, insn);
       break;
@@ -1219,6 +1225,32 @@ void ReplaceDivToMultiAArch64::Run(BB &bb, Insn &insn) {
   }
 }
 
+void ReduceMultToShiftAArch64::Run(BB &bb, Insn &insn) {
+  Insn *prevInsn = insn.GetPreviousMachineInsn();
+  if (prevInsn == nullptr ||
+      (prevInsn->GetMachineOpcode() != MOP_xmovri32 && prevInsn->GetMachineOpcode() != MOP_xmovri64)) {
+    return;
+  }
+  ImmOperand &imm = static_cast<ImmOperand&>(prevInsn->GetOperand(kInsnSecondOpnd));
+  int32 val = imm.GetValue();
+  if (val != 0xffff && val != 0xfffe) {
+    return;
+  }
+  if (val == 0xffff) {
+    auto *aarch64CGFunc = static_cast<AArch64CGFunc*>(&cgFunc);
+    ImmOperand &bitPos = aarch64CGFunc->CreateImmOperand(16, k8BitSize, false);
+    auto &reg1 = static_cast<AArch64RegOperand&>(insn.GetOperand(kInsnFirstOpnd));
+    auto &reg2 = static_cast<AArch64RegOperand&>(insn.GetOperand(kInsnSecondOpnd));
+    MOperator mOp =  (reg1.GetSize() <= k32BitSize) ? MOP_wlslrri5 : MOP_xlslrri6;
+    Insn &ushiftInsn = cgFunc.GetCG()->BuildInstruction<AArch64Insn>(mOp, reg1, reg2, bitPos);
+    mOp = (reg1.GetSize() <= k32BitSize) ? MOP_wsubrrr : MOP_xsubrrr;
+    Insn &subInsn = cgFunc.GetCG()->BuildInstruction<AArch64Insn>(mOp, reg1, reg1, reg2);
+    bb.InsertInsnAfter(insn, subInsn);
+    bb.ReplaceInsn(insn, ushiftInsn);
+    bb.RemoveInsn(*prevInsn);
+  }
+}
+
 void AndCmpBranchesToCsetAArch64::Run(BB &bb, Insn &insn) {
    /* prevInsn must be "cmp" insn */
   Insn *prevInsn = insn.GetPreviousMachineInsn();
-- 
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