From 2780ff99b3be2c8d148f341e1b597b2c4df7d207 Mon Sep 17 00:00:00 2001 From: Alfred Huang Date: Fri, 22 Oct 2021 14:33:01 -0700 Subject: [PATCH] Added vector intrinsics for absolute operations --- .../include/cg/aarch64/aarch64_cgfunc.h | 1 + .../include/cg/aarch64/aarch64_md.def | 2 + src/mapleall/maple_be/include/cg/cgfunc.h | 1 + .../src/cg/aarch64/aarch64_cgfunc.cpp | 17 +++++++- src/mapleall/maple_be/src/cg/cgfunc.cpp | 9 ++++- .../maple_ir/include/intrinsic_vector.def | 39 +++++++++++++++++++ 6 files changed, 67 insertions(+), 2 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index 7adb3775a2..b0e0ee0dbb 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -266,6 +266,7 @@ class AArch64CGFunc : public CGFunc { LabelOperand &CreateFuncLabelOperand(const MIRSymbol &func); uint32 GetAggCopySize(uint32 offset1, uint32 offset2, uint32 alignment) const; + RegOperand *SelectVectorAbs(PrimType rType, Operand *o1) override; RegOperand *SelectVectorBinOp(PrimType rType, Operand *o1, PrimType oTyp1, Operand *o2, PrimType oTyp2, Opcode opc) override; RegOperand *SelectVectorBitwiseOp(PrimType rType, Operand *o1, PrimType oTyp1, Operand *opnd2, diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_md.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_md.def index fa5f313c5b..fde5306324 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_md.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_md.def @@ -811,6 +811,8 @@ DEFINE_MOP(MOP_vsmaddvvv,{mopdReg128VDS,mopdReg64VS,mopdReg64VS},ISVECTOR,kLtFpa DEFINE_MOP(MOP_vumaddvvv,{mopdReg128VDS,mopdReg64VS,mopdReg64VS},ISVECTOR,kLtFpalu,"umlal","0,1,2",1) DEFINE_MOP(MOP_vsmullvvv,{mopdReg128VD,mopdReg64VS,mopdReg64VS},ISVECTOR,kLtFpalu,"smull","0,1,2",1) DEFINE_MOP(MOP_vumullvvv,{mopdReg128VD,mopdReg64VS,mopdReg64VS},ISVECTOR,kLtFpalu,"umull","0,1,2",1) +DEFINE_MOP(MOP_vabsuu, {mopdReg64VD,mopdReg64VS},ISVECTOR,kLtFpalu,"abs","0,1",1) +DEFINE_MOP(MOP_vabsvv, {mopdReg128VD,mopdReg128VS},ISVECTOR,kLtFpalu,"abs","0,1",1) DEFINE_MOP(MOP_vadduuu, {mopdReg64VD,mopdReg64VS,mopdReg64VS},ISVECTOR,kLtFpalu,"add","0,1,2",1) DEFINE_MOP(MOP_vaddvvv, {mopdReg128VD,mopdReg128VS,mopdReg128VS},ISVECTOR,kLtFpalu,"add","0,1,2",1) DEFINE_MOP(MOP_vmuluuu, {mopdReg64VD,mopdReg64VS,mopdReg64VS},ISVECTOR,kLtFpalu,"mul","0,1,2",1) diff --git a/src/mapleall/maple_be/include/cg/cgfunc.h b/src/mapleall/maple_be/include/cg/cgfunc.h index 30a3eb2a59..44c36d9134 100644 --- a/src/mapleall/maple_be/include/cg/cgfunc.h +++ b/src/mapleall/maple_be/include/cg/cgfunc.h @@ -294,6 +294,7 @@ class CGFunc { virtual bool IsFrameReg(const RegOperand &opnd) const = 0; /* For Neon intrinsics */ + virtual RegOperand *SelectVectorAbs(PrimType rType, Operand *o1) = 0; virtual RegOperand *SelectVectorBinOp(PrimType rType, Operand *o1, PrimType oTyp1, Operand *o2, PrimType oTyp2, Opcode opc) = 0; virtual RegOperand *SelectVectorBitwiseOp(PrimType rType, Operand *o1, PrimType oty1, Operand *o2, diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 96d914cc3f..05a8ff0687 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -4378,7 +4378,9 @@ Operand *AArch64CGFunc::SelectAbsSub(Insn &lastInsn, const UnaryNode &node, Oper Operand *AArch64CGFunc::SelectAbs(UnaryNode &node, Operand &opnd0) { PrimType dtyp = node.GetPrimType(); - if (IsPrimitiveFloat(dtyp)) { + if (IsPrimitiveVector(dtyp)) { + return SelectVectorAbs(dtyp, &opnd0); + } else if (IsPrimitiveFloat(dtyp)) { CHECK_FATAL(GetPrimTypeBitSize(dtyp) >= k32BitSize, "We don't support hanf-word FP operands yet"); bool is64Bits = (GetPrimTypeBitSize(dtyp) == k64BitSize); Operand &newOpnd0 = LoadIntoRegister(opnd0, dtyp); @@ -9362,6 +9364,19 @@ RegOperand *AArch64CGFunc::SelectVectorCopy(Operand *src, PrimType sType) { return res; } +RegOperand *AArch64CGFunc::SelectVectorAbs(PrimType rType, Operand *o1) { + RegOperand *res = &CreateRegisterOperandOfType(rType); /* result operand */ + VectorRegSpec *vecSpecDest = GetMemoryPool()->New(rType); + VectorRegSpec *vecSpec1 = GetMemoryPool()->New(rType); /* vector operand 1 */ + + MOperator mOp = GetPrimTypeSize(rType) > k8ByteSize ? MOP_vabsvv : MOP_vabsuu; + Insn *insn = &GetCG()->BuildInstruction(mOp, *res, *o1); + static_cast(insn)->PushRegSpecEntry(vecSpecDest); + static_cast(insn)->PushRegSpecEntry(vecSpec1); + GetCurBB()->AppendInsn(*insn); + return res; +} + RegOperand *AArch64CGFunc::SelectVectorFromScalar(PrimType rType, Operand *src, PrimType sType) { if (!IsPrimitiveVector(rType)) { return SelectVectorCopy(src, sType); diff --git a/src/mapleall/maple_be/src/cg/cgfunc.cpp b/src/mapleall/maple_be/src/cg/cgfunc.cpp index f4edfe2c40..f08baaa93d 100644 --- a/src/mapleall/maple_be/src/cg/cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/cgfunc.cpp @@ -485,7 +485,7 @@ Operand *HandleVectorNarrow(IntrinsicopNode &intrnNode, CGFunc &cgFunc, bool isL } Operand *HandleIntrinOp(const BaseNode &parent, BaseNode &expr, CGFunc &cgFunc) { - (void)parent; +// (void)parent; auto &intrinsicopNode = static_cast(expr); switch (intrinsicopNode.GetIntrinsic()) { case INTRN_MPL_READ_OVTABLE_ENTRY_LAZY: { @@ -618,6 +618,13 @@ Operand *HandleIntrinOp(const BaseNode &parent, BaseNode &expr, CGFunc &cgFunc) case INTRN_C__builtin_return_address: case INTRN_C__builtin_extract_return_addr: return cgFunc.SelectCReturnAddress(intrinsicopNode); + + case INTRN_vector_abs_v8i8: case INTRN_vector_abs_v4i16: + case INTRN_vector_abs_v2i32: case INTRN_vector_abs_v1i64: + case INTRN_vector_abs_v16i8: case INTRN_vector_abs_v8i16: + case INTRN_vector_abs_v4i32: case INTRN_vector_abs_v2i64: + return HandleAbs(parent, intrinsicopNode, cgFunc); + case INTRN_vector_sum_v8u8: case INTRN_vector_sum_v8i8: case INTRN_vector_sum_v4u16: case INTRN_vector_sum_v4i16: case INTRN_vector_sum_v2u32: case INTRN_vector_sum_v2i32: diff --git a/src/mapleall/maple_ir/include/intrinsic_vector.def b/src/mapleall/maple_ir/include/intrinsic_vector.def index efcd2e6060..9f2042d8ef 100644 --- a/src/mapleall/maple_ir/include/intrinsic_vector.def +++ b/src/mapleall/maple_ir/include/intrinsic_vector.def @@ -16,6 +16,45 @@ // DEF_MIR_INTRINSIC(STR, NAME, INTRN_CLASS, RETURN_TYPE, // ARG0, ARG1, ARG2, ARG3, ARG4, ARG5) +// vecTy vector_abs(vecTy src) +// Create a vector by getting the absolute value of the elements in src. +DEF_MIR_INTRINSIC(vector_abs_v8i8, "vector_abs_v8i8", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV8I8, + kArgTyV8I8) +DEF_MIR_INTRINSIC(vector_abs_v4i16, "vector_abs_v4i16", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV4I16, + kArgTyV4I16) +DEF_MIR_INTRINSIC(vector_abs_v2i32, "vector_abs_v2i32", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV2I32, + kArgTyV2I32) +DEF_MIR_INTRINSIC(vector_abs_v1i64, "vector_abs_v1i64", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV1I64, + kArgTyV1I64) +DEF_MIR_INTRINSIC(vector_abs_v2f32, "vector_abs_v2f32", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV2F32, + kArgTyV2F32) +DEF_MIR_INTRINSIC(vector_abs_v1f64, "vector_abs_v1f64", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV1F64, + kArgTyV1F64) +DEF_MIR_INTRINSIC(vector_abs_v16i8, "vector_abs_v16i8", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV16I8, + kArgTyV16I8) +DEF_MIR_INTRINSIC(vector_abs_v8i16, "vector_abs_v8i16", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV8I16, + kArgTyV8I16) +DEF_MIR_INTRINSIC(vector_abs_v4i32, "vector_abs_v4i32", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV4I32, + kArgTyV4I32) +DEF_MIR_INTRINSIC(vector_abs_v2i64, "vector_abs_v2i64", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV2I64, + kArgTyV2I64) +DEF_MIR_INTRINSIC(vector_abs_v4f32, "vector_abs_v4f32", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV4F32, + kArgTyV4F32) +DEF_MIR_INTRINSIC(vector_abs_v2f64, "vector_abs_v2f64", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV2F64, + kArgTyV2F64) + // vecTy vector_from_scalar(scalarTy value) // Create a vector by repeating the scalar value for each element in the // vector. -- Gitee