diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h index ca7c344efa8785fde97e658685ac2ffff6731e59..ebf10a5a0470877cdbee475f168c9fa4c16056d5 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_cgfunc.h @@ -292,9 +292,11 @@ class AArch64CGFunc : public CGFunc { RegOperand *SelectVectorPairwiseAdd(PrimType rType, Operand *src, PrimType sType) override; RegOperand *SelectVectorReverse(PrimType rtype, Operand *src, PrimType stype, uint32 size) override; RegOperand *SelectVectorSetElement(Operand *eOp, PrimType eTyp, Operand *vOpd, PrimType vTyp, int32 lane) override; - RegOperand *SelectVectorShift(PrimType rType, Operand *o1, Operand *o2, Opcode opc) override; + RegOperand *SelectVectorShift(PrimType rType, Operand *o1, PrimType oty1, Operand *o2, PrimType oty2, Opcode opc) override; RegOperand *SelectVectorShiftImm(PrimType rType, Operand *o1, Operand *imm, int32 sVal, Opcode opc) override; RegOperand *SelectVectorShiftRNarrow(PrimType rType, Operand *o1, PrimType oTyp, Operand *o2, bool isLow) override; + RegOperand *SelectVectorSubWiden(PrimType resType, Operand *o1, PrimType otyp1, + Operand *o2, PrimType otyp2, bool isLow, bool isWide) override; RegOperand *SelectVectorSum(PrimType rtype, Operand *o1, PrimType oType) override; RegOperand *SelectVectorTableLookup(PrimType rType, Operand *o1, Operand *o2) override; RegOperand *SelectVectorWiden(PrimType rType, Operand *o1, PrimType otyp, bool isLow) override; diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_md.def b/src/mapleall/maple_be/include/cg/aarch64/aarch64_md.def index e4314d18c417f41bc77a509dfa4ffdac50394af8..f24ae69818fdf79baa1c3dc075679e770ade9ed3 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_md.def +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_md.def @@ -844,6 +844,14 @@ DEFINE_MOP(MOP_vnotuu, {mopdReg64VD,mopdReg64VS},ISVECTOR,kLtFpalu,"not","0,1", DEFINE_MOP(MOP_vnotvv, {mopdReg128VD,mopdReg128VS},ISVECTOR,kLtFpalu,"not","0,1",1) DEFINE_MOP(MOP_vneguu, {mopdReg64VD,mopdReg64VS},ISVECTOR,kLtFpalu,"neg","0,1",1) DEFINE_MOP(MOP_vnegvv, {mopdReg128VD,mopdReg128VS},ISVECTOR,kLtFpalu,"neg","0,1",1) +DEFINE_MOP(MOP_vssublvuu,{mopdReg128VD,mopdReg64VS,mopdReg64VS},ISVECTOR,kLtFpalu,"ssubl","0,1,2",1) +DEFINE_MOP(MOP_vusublvuu,{mopdReg128VD,mopdReg64VS,mopdReg64VS},ISVECTOR,kLtFpalu,"usubl","0,1,2",1) +DEFINE_MOP(MOP_vssubl2vvv,{mopdReg128VD,mopdReg128VS,mopdReg128VS},ISVECTOR,kLtFpalu,"ssubl2","0,1,2",1) +DEFINE_MOP(MOP_vusubl2vvv,{mopdReg128VD,mopdReg128VS,mopdReg128VS},ISVECTOR,kLtFpalu,"usubl2","0,1,2",1) +DEFINE_MOP(MOP_vssubwvvu,{mopdReg128VD,mopdReg128VS,mopdReg64VS},ISVECTOR,kLtFpalu,"ssubw","0,1,2",1) +DEFINE_MOP(MOP_vusubwvvu,{mopdReg128VD,mopdReg128VS,mopdReg64VS},ISVECTOR,kLtFpalu,"usubw","0,1,2",1) +DEFINE_MOP(MOP_vssubw2vvv,{mopdReg128VD,mopdReg128VS,mopdReg128VS},ISVECTOR,kLtFpalu,"ssubw2","0,1,2",1) +DEFINE_MOP(MOP_vusubw2vvv,{mopdReg128VD,mopdReg128VS,mopdReg128VS},ISVECTOR,kLtFpalu,"usubw2","0,1,2",1) DEFINE_MOP(MOP_vzip1vvv,{mopdReg64VD,mopdReg64VS,mopdReg64VS},ISVECTOR,kLtFpalu,"zip1","0,1,2",1) DEFINE_MOP(MOP_vzip2vvv,{mopdReg64VD,mopdReg64VS,mopdReg64VS},ISVECTOR,kLtFpalu,"zip2","0,1,2",1) diff --git a/src/mapleall/maple_be/include/cg/cgfunc.h b/src/mapleall/maple_be/include/cg/cgfunc.h index d20b6a38b0d84a969bab1fd4c2f50645c4a6684f..a157504c5b754c6f3935b75cac5eb5759eb18001 100644 --- a/src/mapleall/maple_be/include/cg/cgfunc.h +++ b/src/mapleall/maple_be/include/cg/cgfunc.h @@ -317,10 +317,12 @@ class CGFunc { virtual RegOperand *SelectVectorPairwiseAdd(PrimType rType, Operand *src, PrimType sType) = 0; virtual RegOperand *SelectVectorReverse(PrimType rtype, Operand *src, PrimType stype, uint32 size) = 0; virtual RegOperand *SelectVectorSetElement(Operand *eOp, PrimType eTyp, Operand *vOpd, PrimType vTyp, int32 lane) = 0; - virtual RegOperand *SelectVectorShift(PrimType rType, Operand *o1, Operand *o2, Opcode opc) = 0; + virtual RegOperand *SelectVectorShift(PrimType rType, Operand *o1, PrimType oty1, Operand *o2, PrimType oty2, Opcode opc) = 0; virtual RegOperand *SelectVectorShiftImm(PrimType rType, Operand *o1, Operand *imm, int32 sVal, Opcode opc) = 0; virtual RegOperand *SelectVectorShiftRNarrow(PrimType rType, Operand *o1, PrimType oType, Operand *o2, bool isLow) = 0; + virtual RegOperand *SelectVectorSubWiden(PrimType resType, Operand *o1, PrimType otyp1, + Operand *o2, PrimType otyp2, bool isLow, bool isWide) = 0; virtual RegOperand *SelectVectorSum(PrimType rtype, Operand *o1, PrimType oType) = 0; virtual RegOperand *SelectVectorTableLookup(PrimType rType, Operand *o1, Operand *o2) = 0; virtual RegOperand *SelectVectorWiden(PrimType rType, Operand *o1, PrimType otyp, bool isLow) = 0; diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp index 983f0ba64e170ffa78a79ef35b9825be7398c15c..c511fc214e8a8b2cb37c6954f074b63b049d3d6a 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_cgfunc.cpp @@ -4269,7 +4269,7 @@ Operand *AArch64CGFunc::SelectShift(BinaryNode &node, Operand &opnd0, Operand &o int64 sConst = static_cast(opnd1).GetValue(); resOpnd = SelectVectorShiftImm(dtype, &opnd0, &opnd1, sConst, opcode); } else if ((IsPrimitiveVector(dtype) || isOneElemVector) && !opnd1.IsConstImmediate()) { - resOpnd = SelectVectorShift(dtype, &opnd0, &opnd1, opcode); + resOpnd = SelectVectorShift(dtype, &opnd0, expr->GetPrimType(), &opnd1, node.Opnd(1)->GetPrimType(), opcode); } else { PrimType primType = isFloat ? dtype : (is64Bits ? (isSigned ? PTY_i64 : PTY_u64) : (isSigned ? PTY_i32 : PTY_u32)); resOpnd = &GetOrCreateResOperand(parent, primType); @@ -9453,9 +9453,9 @@ RegOperand *AArch64CGFunc::SelectVectorAddWiden(Operand *o1, PrimType otyp1, Ope MOperator mOp; if (isLow) { - mOp = IsUnsignedInteger(otyp1) ? MOP_vsaddwvvu : MOP_vuaddwvvu; + mOp = IsUnsignedInteger(otyp1) ? MOP_vuaddwvvu : MOP_vsaddwvvu; } else { - mOp = IsUnsignedInteger(otyp1) ? MOP_vsaddw2vvv : MOP_vuaddw2vvv; + mOp = IsUnsignedInteger(otyp1) ? MOP_vuaddw2vvv : MOP_vsaddw2vvv; } Insn *insn = &GetCG()->BuildInstruction(mOp, *res, *o1, *o2); static_cast(insn)->PushRegSpecEntry(vecSpecDest); @@ -9833,7 +9833,8 @@ RegOperand *AArch64CGFunc::SelectVectorCompare(Operand *o1, PrimType oty1, Opera return res; } -RegOperand *AArch64CGFunc::SelectVectorShift(PrimType rType, Operand *o1, Operand *o2, Opcode opc) { +RegOperand *AArch64CGFunc::SelectVectorShift(PrimType rType, Operand *o1, PrimType oty1, Operand *o2, PrimType oty2, Opcode opc) { + PrepareVectorOperands(&o1, oty1, &o2, oty2); PrimType resultType = rType; VectorRegSpec *vecSpecDest = GetMemoryPool()->New(rType); VectorRegSpec *vecSpec1 = GetMemoryPool()->New(rType); /* vector operand 1 */ @@ -9922,7 +9923,7 @@ RegOperand *AArch64CGFunc::SelectVectorShiftImm(PrimType rType, Operand *o1, Ope Insn *insn = &GetCG()->BuildInstruction(mOp, *res, *imm); static_cast(insn)->PushRegSpecEntry(vecSpecDest); GetCurBB()->AppendInsn(*insn); - res = SelectVectorShift(rType, o1, res, opc); + res = SelectVectorShift(rType, o1, rType, res, rType, opc); return res; } MOperator mOp; @@ -10117,6 +10118,35 @@ RegOperand *AArch64CGFunc::SelectVectorShiftRNarrow(PrimType rType, Operand *o1, return res; } +RegOperand *AArch64CGFunc::SelectVectorSubWiden(PrimType resType, Operand *o1, + PrimType otyp1, Operand *o2, PrimType otyp2, bool isLow, bool isWide) { + RegOperand *res = &CreateRegisterOperandOfType(resType); /* result reg */ + VectorRegSpec *vecSpecDest = GetMemoryPool()->New(resType); + VectorRegSpec *vecSpec1 = GetMemoryPool()->New(otyp1); /* vector operand 1 */ + VectorRegSpec *vecSpec2 = GetMemoryPool()->New(otyp2); /* vector operand 2 */ + + MOperator mOp; + if (!isWide) { + if (isLow) { + mOp = IsUnsignedInteger(otyp1) ? MOP_vusublvuu : MOP_vssublvuu; + } else { + mOp = IsUnsignedInteger(otyp1) ? MOP_vusubl2vvv : MOP_vssubl2vvv; + } + } else { + if (isLow) { + mOp = IsUnsignedInteger(otyp1) ? MOP_vusubwvvu : MOP_vssubwvvu; + } else { + mOp = IsUnsignedInteger(otyp1) ? MOP_vusubw2vvv : MOP_vssubw2vvv; + } + } + Insn *insn = &GetCG()->BuildInstruction(mOp, *res, *o1, *o2); + static_cast(insn)->PushRegSpecEntry(vecSpecDest); + static_cast(insn)->PushRegSpecEntry(vecSpec1); + static_cast(insn)->PushRegSpecEntry(vecSpec2); + GetCurBB()->AppendInsn(*insn); + return res; +} + void AArch64CGFunc::SelectVectorZip(PrimType rType, Operand *o1, Operand *o2) { RegOperand *res1 = &CreateRegisterOperandOfType(rType); /* result operand 1 */ RegOperand *res2 = &CreateRegisterOperandOfType(rType); /* result operand 2 */ diff --git a/src/mapleall/maple_be/src/cg/cgfunc.cpp b/src/mapleall/maple_be/src/cg/cgfunc.cpp index fa18ab883d735a61726a0caf4ae86aa99e21f5c7..e5c7e6a51358902b013e8e1216006534e30fe0cd 100644 --- a/src/mapleall/maple_be/src/cg/cgfunc.cpp +++ b/src/mapleall/maple_be/src/cg/cgfunc.cpp @@ -87,6 +87,7 @@ Operand *HandleConstStr16(const BaseNode &parent, BaseNode &expr, CGFunc &cgFunc Operand *HandleAdd(const BaseNode &parent, BaseNode &expr, CGFunc &cgFunc) { if (Globals::GetInstance()->GetOptimLevel() >= CGOptions::kLevel2 && expr.Opnd(0)->GetOpCode() == OP_mul && + !IsPrimitiveVector(expr.GetPrimType()) && !IsPrimitiveFloat(expr.GetPrimType()) && expr.Opnd(0)->Opnd(0)->GetOpCode() != OP_constval && expr.Opnd(0)->Opnd(1)->GetOpCode() != OP_constval) { return cgFunc.SelectMadd(static_cast(expr), @@ -94,6 +95,7 @@ Operand *HandleAdd(const BaseNode &parent, BaseNode &expr, CGFunc &cgFunc) { *cgFunc.HandleExpr(*expr.Opnd(0), *expr.Opnd(0)->Opnd(1)), *cgFunc.HandleExpr(expr, *expr.Opnd(1)), parent); } else if (Globals::GetInstance()->GetOptimLevel() >= CGOptions::kLevel2 && expr.Opnd(1)->GetOpCode() == OP_mul && + !IsPrimitiveVector(expr.GetPrimType()) && !IsPrimitiveFloat(expr.GetPrimType()) && expr.Opnd(1)->Opnd(0)->GetOpCode() != OP_constval && expr.Opnd(1)->Opnd(1)->GetOpCode() != OP_constval) { return cgFunc.SelectMadd(static_cast(expr), @@ -452,6 +454,14 @@ Operand *HandleVectorShiftNarrow(IntrinsicopNode &intrnNode, CGFunc &cgFunc, boo return cgFunc.SelectVectorShiftRNarrow(rType, opnd1, intrnNode.Opnd(0)->GetPrimType(), opnd2, isLow); } +Operand *HandleVectorSubWiden(IntrinsicopNode &intrnNode, CGFunc &cgFunc, bool isLow, bool isWide) { + PrimType resType = intrnNode.GetPrimType(); /* uint32_t result */ + Operand *o1 = cgFunc.HandleExpr(intrnNode, *intrnNode.Opnd(0)); + Operand *o2 = cgFunc.HandleExpr(intrnNode, *intrnNode.Opnd(1)); + return cgFunc.SelectVectorSubWiden(resType, o1, intrnNode.Opnd(0)->GetPrimType(), + o2, intrnNode.Opnd(1)->GetPrimType(), isLow, isWide); +} + Operand *HandleVectorSum(IntrinsicopNode &intrnNode, CGFunc &cgFunc) { PrimType resType = intrnNode.GetPrimType(); /* uint32_t result */ Operand *opnd1 = cgFunc.HandleExpr(intrnNode, *intrnNode.Opnd(0)); /* vector operand */ @@ -752,6 +762,26 @@ Operand *HandleIntrinOp(const BaseNode &parent, BaseNode &expr, CGFunc &cgFunc) case INTRN_vector_shr_narrow_low_v2u64: case INTRN_vector_shr_narrow_low_v2i64: return HandleVectorShiftNarrow(intrinsicopNode, cgFunc, true); + case INTRN_vector_subl_low_v8i8: case INTRN_vector_subl_low_v8u8: + case INTRN_vector_subl_low_v4i16: case INTRN_vector_subl_low_v4u16: + case INTRN_vector_subl_low_v2i32: case INTRN_vector_subl_low_v2u32: + return HandleVectorSubWiden(intrinsicopNode, cgFunc, true, false); + + case INTRN_vector_subl_high_v8i8: case INTRN_vector_subl_high_v8u8: + case INTRN_vector_subl_high_v4i16: case INTRN_vector_subl_high_v4u16: + case INTRN_vector_subl_high_v2i32: case INTRN_vector_subl_high_v2u32: + return HandleVectorSubWiden(intrinsicopNode, cgFunc, false, false); + + case INTRN_vector_subw_low_v8i8: case INTRN_vector_subw_low_v8u8: + case INTRN_vector_subw_low_v4i16: case INTRN_vector_subw_low_v4u16: + case INTRN_vector_subw_low_v2i32: case INTRN_vector_subw_low_v2u32: + return HandleVectorSubWiden(intrinsicopNode, cgFunc, true, true); + + case INTRN_vector_subw_high_v8i8: case INTRN_vector_subw_high_v8u8: + case INTRN_vector_subw_high_v4i16: case INTRN_vector_subw_high_v4u16: + case INTRN_vector_subw_high_v2i32: case INTRN_vector_subw_high_v2u32: + return HandleVectorSubWiden(intrinsicopNode, cgFunc, false, true); + case INTRN_vector_table_lookup_v8u8: case INTRN_vector_table_lookup_v8i8: case INTRN_vector_table_lookup_v16u8: case INTRN_vector_table_lookup_v16i8: return HandleVectorTableLookup(intrinsicopNode, cgFunc); diff --git a/src/mapleall/maple_ir/include/intrinsic_vector.def b/src/mapleall/maple_ir/include/intrinsic_vector.def index c1ac9525097676022fd9b9bb459670738dbde77c..91e1c16c44cb2eb288f661c717ccc0edf5d7083c 100644 --- a/src/mapleall/maple_ir/include/intrinsic_vector.def +++ b/src/mapleall/maple_ir/include/intrinsic_vector.def @@ -934,3 +934,91 @@ DEF_MIR_INTRINSIC(vector_store_v1f64, "vector_store_v1f64", INTRNISVECTOR, kArgTyVoid, kArgTyPtr, kArgTyV1F64) DEF_MIR_INTRINSIC(vector_store_v2f32, "vector_store_v2f32", INTRNISVECTOR, kArgTyVoid, kArgTyPtr, kArgTyV2F32) + +// vecTy vector_subl_low(vecTy src1, vecTy src2) +// Subtract each element of the source vector to second source +// widen the result into the destination vector. +DEF_MIR_INTRINSIC(vector_subl_low_v8i8, "vector_subl_low_v8i8", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV8I16, + kArgTyV8I8, kArgTyV8I8) +DEF_MIR_INTRINSIC(vector_subl_low_v4i16, "vector_subl_low_v4i16", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV4I32, + kArgTyV4I16, kArgTyV4I16) +DEF_MIR_INTRINSIC(vector_subl_low_v2i32, "vector_subl_low_v2i32", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV2I64, + kArgTyV2I32, kArgTyV2I32) +DEF_MIR_INTRINSIC(vector_subl_low_v8u8, "vector_subl_low_v8u8", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV8U16, + kArgTyV8U8, kArgTyV8U8) +DEF_MIR_INTRINSIC(vector_subl_low_v4u16, "vector_subl_low_v4u16", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV4U32, + kArgTyV4U16, kArgTyV4U16) +DEF_MIR_INTRINSIC(vector_subl_low_v2u32, "vector_subl_low_v2u32", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV2U64, + kArgTyV2U32, kArgTyV2U32) + +// vecTy vector_subl_high(vecTy src1, vecTy src2) +// Subtract each element of the source vector to upper half of second source +// widen the result into the destination vector. +DEF_MIR_INTRINSIC(vector_subl_high_v8i8, "vector_subl_high_v8i8", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV8I16, + kArgTyV16I8, kArgTyV16I8) +DEF_MIR_INTRINSIC(vector_subl_high_v4i16, "vector_subl_high_v4i16", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV4I32, + kArgTyV8I16, kArgTyV8I16) +DEF_MIR_INTRINSIC(vector_subl_high_v2i32, "vector_subl_high_v2i32", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV2I64, + kArgTyV4I32, kArgTyV4I32) +DEF_MIR_INTRINSIC(vector_subl_high_v8u8, "vector_subl_high_v8u8", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV8U16, + kArgTyV16U8, kArgTyV16U8) +DEF_MIR_INTRINSIC(vector_subl_high_v4u16, "vector_subl_high_v4u16", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV4U32, + kArgTyV8U16, kArgTyV8U16) +DEF_MIR_INTRINSIC(vector_subl_high_v2u32, "vector_subl_high_v2u32", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV2U64, + kArgTyV4U32, kArgTyV4U32) + +// vecTy vector_subw_low(vecTy src1, vecTy src2) +// Subtract each element of the source vector to second source +// widen the result into the destination vector. +DEF_MIR_INTRINSIC(vector_subw_low_v8i8, "vector_subw_low_v8i8", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV8I16, + kArgTyV8I16, kArgTyV8I8) +DEF_MIR_INTRINSIC(vector_subw_low_v4i16, "vector_subw_low_v4i16", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV4I32, + kArgTyV4I32, kArgTyV4I16) +DEF_MIR_INTRINSIC(vector_subw_low_v2i32, "vector_subw_low_v2i32", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV2I64, + kArgTyV2I64, kArgTyV2I32) +DEF_MIR_INTRINSIC(vector_subw_low_v8u8, "vector_subw_low_v8u8", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV8U16, + kArgTyV8U16, kArgTyV8U8) +DEF_MIR_INTRINSIC(vector_subw_low_v4u16, "vector_subw_low_v4u16", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV4U32, + kArgTyV4U32, kArgTyV4U16) +DEF_MIR_INTRINSIC(vector_subw_low_v2u32, "vector_subw_low_v2u32", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV2U64, + kArgTyV2U64, kArgTyV2U32) + +// vecTy vector_subw_high(vecTy src1, vecTy src2) +// Subtract each element of the source vector to upper half of second source +// widen the result into the destination vector. +DEF_MIR_INTRINSIC(vector_subw_high_v8i8, "vector_subw_high_v8i8", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV8I16, + kArgTyV8I16, kArgTyV16I8) +DEF_MIR_INTRINSIC(vector_subw_high_v4i16, "vector_subw_high_v4i16", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV4I32, + kArgTyV4I32, kArgTyV8I16) +DEF_MIR_INTRINSIC(vector_subw_high_v2i32, "vector_subw_high_v2i32", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV2I64, + kArgTyV2I64, kArgTyV4I32) +DEF_MIR_INTRINSIC(vector_subw_high_v8u8, "vector_subw_high_v8u8", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV8U16, + kArgTyV8U16, kArgTyV16U8) +DEF_MIR_INTRINSIC(vector_subw_high_v4u16, "vector_subw_high_v4u16", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV4U32, + kArgTyV4U32, kArgTyV8U16) +DEF_MIR_INTRINSIC(vector_subw_high_v2u32, "vector_subw_high_v2u32", + INTRNISVECTOR | INTRNISPURE | INTRNNOSIDEEFFECT, kArgTyV2U64, + kArgTyV2U64, kArgTyV4U32)