diff --git a/0019-BinaryFormat-LoongArch-Define-psABI-v2.30-relocs-770.patch b/0019-BinaryFormat-LoongArch-Define-psABI-v2.30-relocs-770.patch new file mode 100644 index 0000000000000000000000000000000000000000..bc96dbdf6c7e45e9ec2d14263fef6c524e9c411e --- /dev/null +++ b/0019-BinaryFormat-LoongArch-Define-psABI-v2.30-relocs-770.patch @@ -0,0 +1,111 @@ +From e5e25c151fc96e62950e7c645c4d2768b95e1e7a Mon Sep 17 00:00:00 2001 +From: Lu Weining +Date: Tue, 9 Jan 2024 14:58:09 +0800 +Subject: [PATCH 1/2] [BinaryFormat][LoongArch] Define psABI v2.30 relocs + (#77039) + +(cherry picked from commit 4a5ebc7f6538dbebe9d671346de6138de657cb7d) +--- + .../llvm/BinaryFormat/ELFRelocs/LoongArch.def | 23 ++++++++++++ + .../ELF/reloc-types-loongarch64.test | 36 +++++++++++++++++++ + 2 files changed, 59 insertions(+) + +diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/LoongArch.def b/llvm/include/llvm/BinaryFormat/ELFRelocs/LoongArch.def +index df3a342151fb..4859057abcbb 100644 +--- a/llvm/include/llvm/BinaryFormat/ELFRelocs/LoongArch.def ++++ b/llvm/include/llvm/BinaryFormat/ELFRelocs/LoongArch.def +@@ -126,3 +126,26 @@ ELF_RELOC(R_LARCH_64_PCREL, 109) + // + // Spec addition: https://github.com/loongson/la-abi-specs/pull/4 + ELF_RELOC(R_LARCH_CALL36, 110) ++ ++// Relocs added in ELF for the LoongArch™ Architecture v20231219, part of the ++// v2.30 LoongArch ABI specs. ++// ++// Spec addition: https://github.com/loongson/la-abi-specs/pull/5 ++ELF_RELOC(R_LARCH_TLS_DESC32, 13) ++ELF_RELOC(R_LARCH_TLS_DESC64, 14) ++ELF_RELOC(R_LARCH_TLS_DESC_PC_HI20, 111) ++ELF_RELOC(R_LARCH_TLS_DESC_PC_LO12, 112) ++ELF_RELOC(R_LARCH_TLS_DESC64_PC_LO20, 113) ++ELF_RELOC(R_LARCH_TLS_DESC64_PC_HI12, 114) ++ELF_RELOC(R_LARCH_TLS_DESC_HI20, 115) ++ELF_RELOC(R_LARCH_TLS_DESC_LO12, 116) ++ELF_RELOC(R_LARCH_TLS_DESC64_LO20, 117) ++ELF_RELOC(R_LARCH_TLS_DESC64_HI12, 118) ++ELF_RELOC(R_LARCH_TLS_DESC_LD, 119) ++ELF_RELOC(R_LARCH_TLS_DESC_CALL, 120) ++ELF_RELOC(R_LARCH_TLS_LE_HI20_R, 121) ++ELF_RELOC(R_LARCH_TLS_LE_ADD_R, 122) ++ELF_RELOC(R_LARCH_TLS_LE_LO12_R, 123) ++ELF_RELOC(R_LARCH_TLS_LD_PCREL20_S2, 124) ++ELF_RELOC(R_LARCH_TLS_GD_PCREL20_S2, 125) ++ELF_RELOC(R_LARCH_TLS_DESC_PCREL20_S2, 126) +diff --git a/llvm/test/tools/llvm-readobj/ELF/reloc-types-loongarch64.test b/llvm/test/tools/llvm-readobj/ELF/reloc-types-loongarch64.test +index 55a3e645b883..26c4e8f5ca84 100644 +--- a/llvm/test/tools/llvm-readobj/ELF/reloc-types-loongarch64.test ++++ b/llvm/test/tools/llvm-readobj/ELF/reloc-types-loongarch64.test +@@ -17,6 +17,8 @@ + # CHECK: Type: R_LARCH_TLS_TPREL32 (10) + # CHECK: Type: R_LARCH_TLS_TPREL64 (11) + # CHECK: Type: R_LARCH_IRELATIVE (12) ++# CHECK: Type: R_LARCH_TLS_DESC32 (13) ++# CHECK: Type: R_LARCH_TLS_DESC64 (14) + # CHECK: Type: R_LARCH_MARK_LA (20) + # CHECK: Type: R_LARCH_MARK_PCREL (21) + # CHECK: Type: R_LARCH_SOP_PUSH_PCREL (22) +@@ -101,6 +103,22 @@ + # CHECK: Type: R_LARCH_SUB_ULEB128 (108) + # CHECK: Type: R_LARCH_64_PCREL (109) + # CHECK: Type: R_LARCH_CALL36 (110) ++# CHECK: Type: R_LARCH_TLS_DESC_PC_HI20 (111) ++# CHECK: Type: R_LARCH_TLS_DESC_PC_LO12 (112) ++# CHECK: Type: R_LARCH_TLS_DESC64_PC_LO20 (113) ++# CHECK: Type: R_LARCH_TLS_DESC64_PC_HI12 (114) ++# CHECK: Type: R_LARCH_TLS_DESC_HI20 (115) ++# CHECK: Type: R_LARCH_TLS_DESC_LO12 (116) ++# CHECK: Type: R_LARCH_TLS_DESC64_LO20 (117) ++# CHECK: Type: R_LARCH_TLS_DESC64_HI12 (118) ++# CHECK: Type: R_LARCH_TLS_DESC_LD (119) ++# CHECK: Type: R_LARCH_TLS_DESC_CALL (120) ++# CHECK: Type: R_LARCH_TLS_LE_HI20_R (121) ++# CHECK: Type: R_LARCH_TLS_LE_ADD_R (122) ++# CHECK: Type: R_LARCH_TLS_LE_LO12_R (123) ++# CHECK: Type: R_LARCH_TLS_LD_PCREL20_S2 (124) ++# CHECK: Type: R_LARCH_TLS_GD_PCREL20_S2 (125) ++# CHECK: Type: R_LARCH_TLS_DESC_PCREL20_S2 (126) + + --- !ELF + FileHeader: +@@ -125,6 +143,8 @@ Sections: + - Type: R_LARCH_TLS_TPREL32 + - Type: R_LARCH_TLS_TPREL64 + - Type: R_LARCH_IRELATIVE ++ - Type: R_LARCH_TLS_DESC32 ++ - Type: R_LARCH_TLS_DESC64 + - Type: R_LARCH_MARK_LA + - Type: R_LARCH_MARK_PCREL + - Type: R_LARCH_SOP_PUSH_PCREL +@@ -209,3 +229,19 @@ Sections: + - Type: R_LARCH_SUB_ULEB128 + - Type: R_LARCH_64_PCREL + - Type: R_LARCH_CALL36 ++ - Type: R_LARCH_TLS_DESC_PC_HI20 ++ - Type: R_LARCH_TLS_DESC_PC_LO12 ++ - Type: R_LARCH_TLS_DESC64_PC_LO20 ++ - Type: R_LARCH_TLS_DESC64_PC_HI12 ++ - Type: R_LARCH_TLS_DESC_HI20 ++ - Type: R_LARCH_TLS_DESC_LO12 ++ - Type: R_LARCH_TLS_DESC64_LO20 ++ - Type: R_LARCH_TLS_DESC64_HI12 ++ - Type: R_LARCH_TLS_DESC_LD ++ - Type: R_LARCH_TLS_DESC_CALL ++ - Type: R_LARCH_TLS_LE_HI20_R ++ - Type: R_LARCH_TLS_LE_ADD_R ++ - Type: R_LARCH_TLS_LE_LO12_R ++ - Type: R_LARCH_TLS_LD_PCREL20_S2 ++ - Type: R_LARCH_TLS_GD_PCREL20_S2 ++ - Type: R_LARCH_TLS_DESC_PCREL20_S2 +-- +2.20.1 + diff --git a/0020-LoongArch-Pre-commit-test-for-fixing-xvshuf-instruct.patch b/0020-LoongArch-Pre-commit-test-for-fixing-xvshuf-instruct.patch new file mode 100644 index 0000000000000000000000000000000000000000..2d31e6e60f95db5ec1d38dc6f5c684be8d479670 --- /dev/null +++ b/0020-LoongArch-Pre-commit-test-for-fixing-xvshuf-instruct.patch @@ -0,0 +1,43 @@ +From 585d99dd15e46f45dbf783f2c9e34da82bab8400 Mon Sep 17 00:00:00 2001 +From: Qi Zhao +Date: Thu, 26 Jun 2025 18:42:25 +0800 +Subject: [PATCH 1/2] [LoongArch] Pre-commit test for fixing xvshuf + instructions. NFC + +For this test, the `xvshuf.d` instruction should not be generated. + +This will be fixed later. + +(cherry picked from commit a19ddff980136835fead07b346bd83e9211124a0) +--- + .../lasx/ir-instruction/fix-xvshuf.ll | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll + +diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll +new file mode 100644 +index 000000000000..081cf56b48bd +--- /dev/null ++++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll +@@ -0,0 +1,18 @@ ++; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ++; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s ++ ++;; Fix https://github.com/llvm/llvm-project/issues/137000. ++ ++define <4 x double> @shufflevector_v4f64(<4 x double> %a, <4 x double> %b) { ++; CHECK-LABEL: shufflevector_v4f64: ++; CHECK: # %bb.0: # %entry ++; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0) ++; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI0_0) ++; CHECK-NEXT: xvld $xr2, $a0, 0 ++; CHECK-NEXT: xvshuf.d $xr2, $xr1, $xr0 ++; CHECK-NEXT: xvori.b $xr0, $xr2, 0 ++; CHECK-NEXT: ret ++entry: ++ %c = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> ++ ret <4 x double> %c ++} +-- +2.20.1 + diff --git a/0021-LoongArch-Fix-xvshuf-instructions-lowering-145868.patch b/0021-LoongArch-Fix-xvshuf-instructions-lowering-145868.patch new file mode 100644 index 0000000000000000000000000000000000000000..19aa79969c23e236fffffd4446af2c1d11c28e2c --- /dev/null +++ b/0021-LoongArch-Fix-xvshuf-instructions-lowering-145868.patch @@ -0,0 +1,60 @@ +From ed46e609446dd7abc8863cdc743a7e73f6d8be33 Mon Sep 17 00:00:00 2001 +From: ZhaoQi +Date: Fri, 27 Jun 2025 10:29:32 +0800 +Subject: [PATCH 2/2] [LoongArch] Fix xvshuf instructions lowering (#145868) + +Fix https://github.com/llvm/llvm-project/issues/137000. + +(cherry picked from commit 30e519e1ad185701eb9593f6c727c808d7590d1b) +--- + .../LoongArch/LoongArchISelLowering.cpp | 2 +- + .../lasx/ir-instruction/fix-xvshuf.ll | 20 +++++++++++++++---- + 2 files changed, 17 insertions(+), 5 deletions(-) + +diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +index 618ae7056425..3c0b3410c25e 100644 +--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp ++++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +@@ -1098,7 +1098,7 @@ static SDValue lowerVECTOR_SHUFFLE_XVSHUF(const SDLoc &DL, ArrayRef Mask, + if (*it < 0) // UNDEF + MaskAlloc.push_back(DAG.getTargetConstant(0, DL, MVT::i64)); + else if ((*it >= 0 && *it < HalfSize) || +- (*it >= MaskSize && *it <= MaskSize + HalfSize)) { ++ (*it >= MaskSize && *it < MaskSize + HalfSize)) { + int M = *it < HalfSize ? *it : *it - HalfSize; + MaskAlloc.push_back(DAG.getTargetConstant(M, DL, MVT::i64)); + } else +diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll +index 081cf56b48bd..f32ba040f012 100644 +--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll ++++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll +@@ -6,10 +6,22 @@ + define <4 x double> @shufflevector_v4f64(<4 x double> %a, <4 x double> %b) { + ; CHECK-LABEL: shufflevector_v4f64: + ; CHECK: # %bb.0: # %entry +-; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0) +-; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI0_0) +-; CHECK-NEXT: xvld $xr2, $a0, 0 +-; CHECK-NEXT: xvshuf.d $xr2, $xr1, $xr0 ++; CHECK-NEXT: xvpickve2gr.d $a0, $xr0, 0 ++; CHECK-NEXT: movgr2fr.d $fa2, $a0 ++; CHECK-NEXT: movfr2gr.d $a0, $fa2 ++; CHECK-NEXT: xvinsgr2vr.d $xr2, $a0, 0 ++; CHECK-NEXT: xvpickve2gr.d $a0, $xr1, 2 ++; CHECK-NEXT: movgr2fr.d $fa3, $a0 ++; CHECK-NEXT: movfr2gr.d $a0, $fa3 ++; CHECK-NEXT: xvinsgr2vr.d $xr2, $a0, 1 ++; CHECK-NEXT: xvpickve2gr.d $a0, $xr0, 3 ++; CHECK-NEXT: movgr2fr.d $fa0, $a0 ++; CHECK-NEXT: movfr2gr.d $a0, $fa0 ++; CHECK-NEXT: xvinsgr2vr.d $xr2, $a0, 2 ++; CHECK-NEXT: xvpickve2gr.d $a0, $xr1, 3 ++; CHECK-NEXT: movgr2fr.d $fa0, $a0 ++; CHECK-NEXT: movfr2gr.d $a0, $fa0 ++; CHECK-NEXT: xvinsgr2vr.d $xr2, $a0, 3 + ; CHECK-NEXT: xvori.b $xr0, $xr2, 0 + ; CHECK-NEXT: ret + entry: +-- +2.20.1 + diff --git a/llvm.spec b/llvm.spec index 897d33903b946c62701ca009da31eac2da2bc482..1efef8869987023aaad109e2f8cf73cd4892e3b3 100644 --- a/llvm.spec +++ b/llvm.spec @@ -2,7 +2,7 @@ Name: llvm Version: 17.0.6 -Release: 10%{?dist} +Release: 11%{?dist} Summary: Low Level Virtual Machine, modular and reusable compiler and toolchain License: Apache License v2.0 with LLVM Exceptions URL: http://llvm.org @@ -31,6 +31,9 @@ Patch0015: 0014-Backport-LoongArch-fix-and-add-some-new-support.patch Patch0016: 0015-LoongArch-Precommit-test-case-to-show-bug-in-LoongAr.patch Patch0017: 0016-LoongArch-Pass-OptLevel-to-LoongArchDAGToDAGISel-cor.patch Patch0018: 0017-LoongArch-Fix-test-cases-after-2dd8460d8a36.patch +Patch0019: 0019-BinaryFormat-LoongArch-Define-psABI-v2.30-relocs-770.patch +Patch0020: 0020-LoongArch-Pre-commit-test-for-fixing-xvshuf-instruct.patch +Patch0021: 0021-LoongArch-Fix-xvshuf-instructions-lowering-145868.patch Patch3000: deprecated-recommonmark.patch Patch3001: 0001-Clear-instructions-not-recorded-in-ErasedInstrs.patch @@ -254,6 +257,10 @@ LD_LIBRARY_PATH=%{buildroot}/%{_libdir} %{__ninja} check-all -C %{_vpath_buildd %{_includedir}/llvm-gmock %changelog +* Thu Jul 10 2025 chenli - 17.0.6-11 +- LoongArch Backport: Define psABI v2.30 relocs +- LoongArch Backport: Fix xvshuf instructions lowering + * Mon Jun 23 2025 chenli - 17.0.6-10 - LoongArch Backport: Pass OptLevel to LoongArchDAGToDAGISel