From 4165401b2021cfc8a76eb0542cee6707cd3449cf Mon Sep 17 00:00:00 2001 From: liyuting Date: Fri, 18 Jul 2025 16:35:05 +0800 Subject: [PATCH] Add support for phytium live migrate and s5000c model Add interfaces to judge the cpu platform. Signed-off-by: Li Yuting Signed-off-by: Peng Mengguang --- ...phytium-live-migrate-and-s5000c-mode.patch | 476 ++++++++++++++++++ qemu.spec | 7 +- 2 files changed, 482 insertions(+), 1 deletion(-) create mode 100644 1124-qemu-Add-support-for-phytium-live-migrate-and-s5000c-mode.patch diff --git a/1124-qemu-Add-support-for-phytium-live-migrate-and-s5000c-mode.patch b/1124-qemu-Add-support-for-phytium-live-migrate-and-s5000c-mode.patch new file mode 100644 index 0000000..e01d548 --- /dev/null +++ b/1124-qemu-Add-support-for-phytium-live-migrate-and-s5000c-mode.patch @@ -0,0 +1,476 @@ +From c9c5186265f385ced976a56cc9328231bda1bc41 Mon Sep 17 00:00:00 2001 +From: liyuting +Date: Mon, 30 Jun 2025 16:31:26 +0800 +Subject: [PATCH] Add support for phytium live migrate and s5000c model + +Add interfaces to judge the cpu platform. +Signed-off-by: Li Yuting +Signed-off-by: Peng Mengguang +--- + hw/arm/virt.c | 1 + + hw/intc/arm_gicv3_common.c | 5 ++ + hw/intc/arm_gicv3_kvm.c | 8 +++ + include/hw/intc/arm_gicv3_common.h | 1 + + include/qemu/aarch64-cpuid.h | 51 +++++++++++++++ + target/arm/cpu64.c | 13 ++++ + target/arm/kvm.c | 53 ++++++++++++++- + target/arm/kvm64.c | 101 +++++++++++++++++++++++++++++ + util/aarch64-cpuid.c | 77 ++++++++++++++++++++++ + util/meson.build | 1 + + 10 files changed, 310 insertions(+), 1 deletion(-) + create mode 100644 include/qemu/aarch64-cpuid.h + create mode 100644 util/aarch64-cpuid.c + +diff --git a/hw/arm/virt.c b/hw/arm/virt.c +index be2856c01..684307d7e 100644 +--- a/hw/arm/virt.c ++++ b/hw/arm/virt.c +@@ -222,6 +222,7 @@ static const char *valid_cpus[] = { + ARM_CPU_TYPE_NAME("cortex-a57"), + ARM_CPU_TYPE_NAME("host"), + ARM_CPU_TYPE_NAME("max"), ++ ARM_CPU_TYPE_NAME("phytium-v"), + }; + + static bool cpu_type_valid(const char *cpu) +diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c +index 2ebf880ea..8b9c4b2f1 100644 +--- a/hw/intc/arm_gicv3_common.c ++++ b/hw/intc/arm_gicv3_common.c +@@ -88,6 +88,11 @@ static int gicv3_post_load(void *opaque, int version_id) + gicv3_gicd_no_migration_shift_bug_post_load(s); + + if (c->post_load) { ++ /* load origin value of reg icc_ctrl_el1 when migrate vm */ ++ for (int ncpu = 0; ncpu < s->num_cpu; ncpu++) { ++ GICv3CPUState *cs = &s->cpu[ncpu]; ++ cs->icc_ctlr_el1[GICV3_NS] = cs->icc_ctlr_el1_origin[GICV3_NS]; ++ } + c->post_load(s); + } + return 0; +diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c +index 77eb37e13..367589141 100644 +--- a/hw/intc/arm_gicv3_kvm.c ++++ b/hw/intc/arm_gicv3_kvm.c +@@ -700,6 +700,8 @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) + KVM_VGIC_ATTR(ICC_CTLR_EL1, c->gicr_typer), + &c->icc_ctlr_el1[GICV3_NS], false, &error_abort); + ++ /* save origin value of reg icc_ctrl_el1 for vm migration to use */ ++ c->icc_ctlr_el1_origin[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; + c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; + } + +@@ -720,6 +722,12 @@ static void kvm_arm_gicv3_reset_hold(Object *obj) + } + + kvm_arm_gicv3_put(s); ++ ++ /* save origin value of reg icc_ctrl_el1 */ ++ for (int ncpu = 0; ncpu < s->num_cpu; ncpu++) { ++ GICv3CPUState *c = &s->cpu[ncpu]; ++ c->icc_ctlr_el1_origin[GICV3_NS] = c->icc_ctlr_el1[GICV3_NS]; ++ } + } + + /* +diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h +index 4e2fb518e..a9b6d7f7b 100644 +--- a/include/hw/intc/arm_gicv3_common.h ++++ b/include/hw/intc/arm_gicv3_common.h +@@ -181,6 +181,7 @@ struct GICv3CPUState { + /* CPU interface */ + uint64_t icc_sre_el1; + uint64_t icc_ctlr_el1[2]; ++ uint64_t icc_ctlr_el1_origin[2]; + uint64_t icc_pmr_el1; + uint64_t icc_bpr[3]; + uint64_t icc_apr[3][4]; +diff --git a/include/qemu/aarch64-cpuid.h b/include/qemu/aarch64-cpuid.h +new file mode 100644 +index 000000000..ec68e6d57 +--- /dev/null ++++ b/include/qemu/aarch64-cpuid.h +@@ -0,0 +1,51 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * aarch64-cpuid.h: Macros to identify the MIDR of aarch64. ++ * ++ * This work is licensed under the terms of the GNU GPL, version 2 or later. ++ * See the COPYING file in the top-level directory. ++ */ ++ ++#ifndef QEMU_AARCH64_CPUID_H ++#define QEMU_AARCH64_CPUID_H ++ ++#define MIDR_REVISION_MASK 0xf ++#define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK) ++#define MIDR_PARTNUM_SHIFT 4 ++#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT) ++#define MIDR_PARTNUM(midr) \ ++ (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT) ++#define MIDR_ARCHITECTURE_SHIFT 16 ++#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) ++#define MIDR_ARCHITECTURE(midr) \ ++ (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT) ++#define MIDR_VARIANT_SHIFT 20 ++#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT) ++#define MIDR_VARIANT(midr) \ ++ (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) ++#define MIDR_IMPLEMENTOR_SHIFT 24 ++#define MIDR_IMPLEMENTOR_MASK (0xffU << MIDR_IMPLEMENTOR_SHIFT) ++#define MIDR_IMPLEMENTOR(midr) \ ++ (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) ++#define MIDR_CPU_MODEL(imp, partnum) \ ++ (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \ ++ (0xf << MIDR_ARCHITECTURE_SHIFT) | \ ++ ((partnum) << MIDR_PARTNUM_SHIFT)) ++ ++#define MIDR_CPU_VAR_REV(var, rev) \ ++ (((var) << MIDR_VARIANT_SHIFT) | (rev)) ++ ++#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ ++ MIDR_ARCHITECTURE_MASK) ++ ++#define ARM_CPU_IMP_PHYTIUM 0x70 ++#define PHYTIUM_CPU_PART_FTC662 0x662 ++#define PHYTIUM_CPU_PART_FTC663 0x663 ++#define PHYTIUM_CPU_PART_FTC862 0x862 ++ ++uint64_t qemu_read_cpuid_id(void); ++uint8_t qemu_read_cpuid_implementor(void); ++uint16_t qemu_read_cpuid_part_number(void); ++bool is_phytium_cpu(void); ++ ++#endif +diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c +index 1e9c6c85a..b4326ce8b 100644 +--- a/target/arm/cpu64.c ++++ b/target/arm/cpu64.c +@@ -741,10 +741,23 @@ static void aarch64_max_initfn(Object *obj) + } + } + ++static void aarch64_phytium_v_initfn(Object *obj) ++{ ++ ARMCPU *cpu = ARM_CPU(obj); ++ ++ if (kvm_enabled()) { ++ kvm_arm_set_cpu_features_from_host(cpu); ++ } else { ++ aarch64_a53_initfn(obj); ++ cpu->midr = 0x701f6622; ++ } ++} ++ + static const ARMCPUInfo aarch64_cpus[] = { + { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, + { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, + { .name = "max", .initfn = aarch64_max_initfn }, ++ { .name = "phytium-v", .initfn = aarch64_phytium_v_initfn }, + #if defined(CONFIG_KVM) || defined(CONFIG_HVF) + { .name = "host", .initfn = aarch64_host_initfn }, + #endif +diff --git a/target/arm/kvm.c b/target/arm/kvm.c +index 7903e2ddd..6b8ff9d41 100644 +--- a/target/arm/kvm.c ++++ b/target/arm/kvm.c +@@ -32,6 +32,7 @@ + #include "hw/irq.h" + #include "qapi/visitor.h" + #include "qemu/log.h" ++#include "qemu/aarch64-cpuid.h" + + const KVMCapabilityInfo kvm_arch_required_capabilities[] = { + KVM_CAP_LAST_INFO +@@ -469,6 +470,56 @@ static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, uint64_t regidx) + return &cpu->cpreg_values[res - cpu->cpreg_indexes]; + } + ++/* PHYTIUM: check compatibility for live migration. */ ++static bool check_compatibility_for_phytium(ARMCPU *cpu) ++{ ++ Object *obj = OBJECT(cpu); ++ ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); ++ ++ int i; ++ bool ret = true; ++ uint8_t src_impl = 0; ++ uint16_t src_partnum = 0; ++ uint64_t src_midr = 0; ++ ++ if (NULL != acc->info && 0 == strcmp(acc->info->name, "phytium-v")) ++ ret = true; ++ else { ++ for (i = 0; i < cpu->cpreg_array_len; i++) { ++ uint64_t regidx = cpu->cpreg_indexes[i]; ++ if (regidx == ARM64_SYS_REG(3, 0, 0, 0, 0)) { ++ src_midr = cpu->cpreg_values[i]; ++ src_impl = (src_midr >> 24) & 0xff; ++ src_partnum = (src_midr >> 4) & 0x0fff; ++ break; ++ } ++ } ++ ++ if (src_impl == ARM_CPU_IMP_PHYTIUM) { ++ if (is_phytium_cpu()) { ++ if (qemu_read_cpuid_part_number() >= src_partnum) { ++ ret = true; ++ } else { ++ ret = false; ++ } ++ } else if (qemu_read_cpuid_implementor() == 0x48) { ++ if (src_partnum == PHYTIUM_CPU_PART_FTC662 ++ || src_partnum == PHYTIUM_CPU_PART_FTC663) { ++ ret = true; ++ } else { ++ ret = false; ++ } ++ } else { ++ ret = false; ++ } ++ } else { ++ ret = false; ++ } ++ } ++ ++ return ret; ++} ++ + /* Initialize the ARMCPU cpreg list according to the kernel's + * definition of what CPU registers it knows about (and throw away + * the previous TCG-created cpreg list). +@@ -608,7 +659,7 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) + * "you tried to set a register which is constant with + * a different value from what it actually contains". + */ +- ok = false; ++ ok = check_compatibility_for_phytium(cpu); + } + } + return ok; +diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c +index 3c175c93a..7cf327775 100644 +--- a/target/arm/kvm64.c ++++ b/target/arm/kvm64.c +@@ -31,6 +31,7 @@ + #include "cpu-features.h" + #include "hw/acpi/acpi.h" + #include "hw/acpi/ghes.h" ++#include "qemu/aarch64-cpuid.h" + + static bool have_guest_debug; + +@@ -548,6 +549,92 @@ static int kvm_arm_sve_set_vls(CPUState *cs) + + #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 + ++#define SYS_ID_PFR0_EL1 ARM64_SYS_REG(3, 0, 0, 1, 0) ++#define SYS_ID_PFR1_EL1 ARM64_SYS_REG(3, 0, 0, 1, 1) ++#define SYS_ID_PFR2_EL1 ARM64_SYS_REG(3, 0, 0, 3, 4) ++#define SYS_ID_DFR0_EL1 ARM64_SYS_REG(3, 0, 0, 1, 2) ++#define SYS_ID_MMFR0_EL1 ARM64_SYS_REG(3, 0, 0, 1, 4) ++#define SYS_ID_MMFR1_EL1 ARM64_SYS_REG(3, 0, 0, 1, 5) ++#define SYS_ID_MMFR2_EL1 ARM64_SYS_REG(3, 0, 0, 1, 6) ++#define SYS_ID_MMFR3_EL1 ARM64_SYS_REG(3, 0, 0, 1, 7) ++#define SYS_ID_MMFR4_EL1 ARM64_SYS_REG(3, 0, 0, 2, 6) ++#define SYS_ID_ISAR0_EL1 ARM64_SYS_REG(3, 0, 0, 2, 0) ++#define SYS_ID_ISAR1_EL1 ARM64_SYS_REG(3, 0, 0, 2, 1) ++#define SYS_ID_ISAR2_EL1 ARM64_SYS_REG(3, 0, 0, 2, 2) ++#define SYS_ID_ISAR3_EL1 ARM64_SYS_REG(3, 0, 0, 2, 3) ++#define SYS_ID_ISAR4_EL1 ARM64_SYS_REG(3, 0, 0, 2, 4) ++#define SYS_ID_ISAR5_EL1 ARM64_SYS_REG(3, 0, 0, 2, 5) ++#define SYS_ID_ISAR6_EL1 ARM64_SYS_REG(3, 0, 0, 2, 7) ++#define SYS_MVFR0_EL1 ARM64_SYS_REG(3, 0, 0, 3, 0) ++#define SYS_MVFR1_EL1 ARM64_SYS_REG(3, 0, 0, 3, 1) ++#define SYS_MVFR2_EL1 ARM64_SYS_REG(3, 0, 0, 3, 2) ++#define SYS_ID_AA64PFR0_EL1 ARM64_SYS_REG(3, 0, 0, 4, 0) ++#define SYS_ID_AA64PFR1_EL1 ARM64_SYS_REG(3, 0, 0, 4, 1) ++#define SYS_ID_AA64DFR0_EL1 ARM64_SYS_REG(3, 0, 0, 5, 0) ++#define SYS_ID_AA64ISAR0_EL1 ARM64_SYS_REG(3, 0, 0, 6, 0) ++#define SYS_ID_AA64ISAR1_EL1 ARM64_SYS_REG(3, 0, 0, 6, 1) ++#define SYS_ID_AA64MMFR0_EL1 ARM64_SYS_REG(3, 0, 0, 7, 0) ++#define SYS_ID_AA64MMFR1_EL1 ARM64_SYS_REG(3, 0, 0, 7, 1) ++#define SYS_ID_AA64MMFR2_EL1 ARM64_SYS_REG(3, 0, 0, 7, 2) ++ ++struct SysRegInfo { ++ const char *name; ++ uint64_t reg; ++ uint64_t value; ++}; ++ ++const struct SysRegInfo sys_regs_info[] = { ++ { "ID_PFR0_EL1", SYS_ID_PFR0_EL1, 0 }, ++ { "ID_PFR1_EL1", SYS_ID_PFR1_EL1, 0 }, ++ { "ID_PFR2_EL1", SYS_ID_PFR2_EL1, 0 }, ++ { "ID_DFR0_EL1", SYS_ID_DFR0_EL1, 0 }, ++ { "ID_MMFR0_EL1", SYS_ID_MMFR0_EL1, 0 }, ++ { "ID_MMFR1_EL1", SYS_ID_MMFR1_EL1, 0 }, ++ { "ID_MMFR2_EL1", SYS_ID_MMFR2_EL1, 0 }, ++ { "ID_MMFR3_EL1", SYS_ID_MMFR3_EL1, 0 }, ++ { "ID_MMFR4_EL1", SYS_ID_MMFR4_EL1, 0 }, ++ { "ID_ISAR0_EL1", SYS_ID_ISAR0_EL1, 0 }, ++ { "ID_ISAR1_EL1", SYS_ID_ISAR1_EL1, 0 }, ++ { "ID_ISAR2_EL1", SYS_ID_ISAR2_EL1, 0 }, ++ { "ID_ISAR3_EL1", SYS_ID_ISAR3_EL1, 0 }, ++ { "ID_ISAR4_EL1", SYS_ID_ISAR4_EL1, 0 }, ++ { "ID_ISAR5_EL1", SYS_ID_ISAR5_EL1, 0 }, ++ { "ID_ISAR6_EL1", SYS_ID_ISAR6_EL1, 0 }, ++ { "MVFR0_EL1", SYS_MVFR0_EL1, 0 }, ++ { "MVFR1_EL1", SYS_MVFR1_EL1, 0 }, ++ { "MVFR2_EL1", SYS_MVFR2_EL1, 0 }, ++ { "ID_AA64PFR0_EL1", SYS_ID_AA64PFR0_EL1, 0x01001111 }, ++ { "ID_AA64PFR1_EL1", SYS_ID_AA64PFR1_EL1, 0 }, ++ { "ID_AA64DFR0_EL1", SYS_ID_AA64DFR0_EL1, 0x10305106 }, ++ { "ID_AA64ISAR0_EL1", SYS_ID_AA64ISAR0_EL1, 0x10000 }, ++ { "ID_AA64ISAR1_EL1", SYS_ID_AA64ISAR1_EL1, 0 }, ++ { "ID_AA64MMFR0_EL1", SYS_ID_AA64MMFR0_EL1, 0x1124 }, ++ { "ID_AA64MMFR1_EL1", SYS_ID_AA64MMFR1_EL1, 0 }, ++ { "ID_AA64MMFR2_EL1", SYS_ID_AA64MMFR2_EL1, 0 }, ++}; ++ ++/* PHYTIUM : modify sys_regs for phytium-v. */ ++static int modify_arm_vcpu_regs_for_phytium_v(ARMCPU *cpu) ++{ ++ int ret = 0; ++ CPUState *cs = CPU(cpu); ++ Object *obj = OBJECT(cpu); ++ ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); ++ ++ if (NULL != acc->info && 0 == strcmp(acc->info->name, "phytium-v")) { ++ uint64_t val = 0; ++ for (int i = 0; i < ARRAY_SIZE(sys_regs_info); i++) { ++ val = sys_regs_info[i].value; ++ ret = kvm_set_one_reg(cs, sys_regs_info[i].reg, &val); ++ if (ret) { ++ break; ++ } ++ } ++ } ++ ++ return ret; ++} ++ + int kvm_arch_init_vcpu(CPUState *cs) + { + int ret; +@@ -599,6 +686,20 @@ int kvm_arch_init_vcpu(CPUState *cs) + return ret; + } + ++ /* ++ * For Phytium only, we'll modify registers' value like ID_AA64ISAR0_EL1 ++ * before the virtual machine used for live-migration is started to ensure ++ * that the virtual machine is successfully migrated between different ++ * models of Phytium servers. ++ * Of course, the above will only happen if the CPU model "phytium-v" ++ * is selected during live migration. ++ */ ++ if (is_phytium_cpu()) { ++ ret = modify_arm_vcpu_regs_for_phytium_v(cpu); ++ if (ret < 0) ++ return ret; ++ } ++ + if (cpu_isar_feature(aa64_sve, cpu)) { + ret = kvm_arm_sve_set_vls(cs); + if (ret) { +diff --git a/util/aarch64-cpuid.c b/util/aarch64-cpuid.c +new file mode 100644 +index 000000000..568f28b28 +--- /dev/null ++++ b/util/aarch64-cpuid.c +@@ -0,0 +1,77 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Dealing with arm cpu identification information. ++ * ++ * Copyright (C) 2024 Phytium, Inc. ++ * ++ * Authors: ++ * Peng Meng Guang ++ * ++ * This work is licensed under the terms of the GNU LGPL, version 2.1 ++ * or later. See the COPYING.LIB file in the top-level directory. ++ */ ++ ++#include ++#include "qemu/osdep.h" ++#include "qemu/cutils.h" ++#include "qemu/aarch64-cpuid.h" ++ ++#if defined(__aarch64__) ++uint64_t qemu_read_cpuid_id(void) ++{ ++#ifdef CONFIG_LINUX ++ const char *file = "/sys/devices/system/cpu/cpu0/regs/identification/midr_el1"; ++ char *buf; ++ uint64_t midr = 0; ++ ++#define BUF_SIZE 32 ++ buf = g_malloc0(BUF_SIZE); ++ if (!buf) { ++ return 0; ++ } ++ ++ if (!g_file_get_contents(file, &buf, 0, NULL)) { ++ goto out; ++ } ++ ++ if (qemu_strtoul(buf, NULL, 0, &midr) < 0) { ++ goto out; ++ } ++ ++out: ++ g_free(buf); ++ ++ return midr; ++#else ++ return 0; ++#endif ++} ++ ++uint8_t qemu_read_cpuid_implementor(void) ++{ ++#ifdef CONFIG_LINUX ++ uint64_t aarch64_midr = qemu_read_cpuid_id(); ++ ++ return MIDR_IMPLEMENTOR(aarch64_midr); ++#else ++ return 0; ++#endif ++} ++ ++uint16_t qemu_read_cpuid_part_number(void) ++{ ++#ifdef CONFIG_LINUX ++ uint64_t aarch64_midr = qemu_read_cpuid_id(); ++ ++ return MIDR_PARTNUM(aarch64_midr); ++#else ++ return 0; ++#endif ++} ++ ++bool is_phytium_cpu(void) ++{ ++ return qemu_read_cpuid_implementor() == ARM_CPU_IMP_PHYTIUM; ++} ++ ++#endif +diff --git a/util/meson.build b/util/meson.build +index c2322ef6e..5ca44750d 100644 +--- a/util/meson.build ++++ b/util/meson.build +@@ -63,6 +63,7 @@ util_ss.add(files('int128.c')) + util_ss.add(files('memalign.c')) + util_ss.add(files('interval-tree.c')) + util_ss.add(files('lockcnt.c')) ++util_ss.add(files('aarch64-cpuid.c')) + + if have_user + util_ss.add(files('selfmap.c')) +-- +2.25.1 + diff --git a/qemu.spec b/qemu.spec index 6b1f5dd..82453f5 100644 --- a/qemu.spec +++ b/qemu.spec @@ -136,7 +136,7 @@ Summary: QEMU is a FAST! processor emulator Name: qemu Version: 8.2.2 -Release: 33%{?dist} +Release: 34%{?dist} License: GPLv2 and BSD and MIT and CC-BY URL: http://www.qemu.org/ Source0: https://download.qemu.org/%{name}-%{version}.tar.xz @@ -426,6 +426,8 @@ Patch1121: hw-rtc-Fixed-loongson-rtc-emulation-errors.patch Patch1122: 1122-target-i386-csv-Release-CSV3-shared-pages-after-unma.patch Patch1123: sync-header-file-from-upstream.patch +# Add Phytium S5000C cpu model +Patch1124: 1124-qemu-Add-support-for-phytium-live-migrate-and-s5000c-mode.patch BuildRequires: meson >= %{meson_version} BuildRequires: zlib-devel @@ -2132,6 +2134,9 @@ useradd -r -u 107 -g qemu -G kvm -d / -s /sbin/nologin \ %changelog +* Fri Jul 18 2025 liyuting - 8.2.2-34 +- phytium: Add support for phytium live migrate and s5000c model + * Tue Apr 29 2025 hanliyang - 8.2.2-33 - [Type] other - [DESC] sync header file from upstream and Enable the compilation of loongarch qemu on other architectures -- Gitee