From 97e030b86118bb3aa4a07cedfa294513863c8cb5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=B0=8F=E6=BB=A1?= Date: Tue, 16 Sep 2025 09:54:36 +0800 Subject: [PATCH] hi3095: add basic support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add hi3095 basic support. Signed-off-by: 小满 --- demos/hi3095/bsp/hi3095/cpu_config.h | 13 +++- demos/hi3095/bsp/mmu.c | 74 +++++++++++++++++++- demos/hi3095/config/prt_config.h | 2 +- demos/hi3095/drivers/samples/hi309x_memmap.h | 9 +-- 4 files changed, 91 insertions(+), 7 deletions(-) diff --git a/demos/hi3095/bsp/hi3095/cpu_config.h b/demos/hi3095/bsp/hi3095/cpu_config.h index 7c6d7b38..1e45fd46 100644 --- a/demos/hi3095/bsp/hi3095/cpu_config.h +++ b/demos/hi3095/bsp/hi3095/cpu_config.h @@ -11,7 +11,18 @@ #define MMU_LOG_MEM_ADDR 0xd3000000ULL #define MMU_DRIVER_ADDR1 0x0c000000ULL #define MMU_DRIVER_ADDR2 0x08600000ULL - +#define MMU_IO_CONFIG_ADDR 0x18960000ULL +#define MMU_IO_CONFIG_T_ADDR 0x8745000ULL +#define MMU_WDG_ADDR 0x18700000ULL +#define MMU_DMAC_ADDR 0x18900000ULL +#define MMU_I2C_ADDR 0x18400000ULL +#define MMU_LOCALBUS_ADDR 0x18860000ULL +#define MMU_RESERVED_ADDR 0x26000000ULL +#define MMU_SPI_ADDR 0x187B0000ULL +#define MMU_GMAC_HP_ADDR 0x1d200000ULL +#define MMU_GMAC_HOST_ADDR 0x1E810000ULL +#define MMU_MDIO_ADDR 0x183F0000ULL +#define MMU_HP_SUBSYS_ADDR 0x1C030000ULL #define UART_BASE_ADDR MMU_UART_ADDR #if defined(GUEST_OS) diff --git a/demos/hi3095/bsp/mmu.c b/demos/hi3095/bsp/mmu.c index 0a5d3034..8ff16600 100644 --- a/demos/hi3095/bsp/mmu.c +++ b/demos/hi3095/bsp/mmu.c @@ -55,7 +55,7 @@ static mmu_mmap_region_s g_mem_map_info[] = { }, { .virt = MMU_UART_ADDR, .phys = MMU_UART_ADDR, - .size = 0x2000, + .size = 0xb0000, .max_level = 0x2, .attrs = MMU_ATTR_DEVICE_NGNRNE | MMU_ACCESS_RWX, }, { @@ -76,6 +76,78 @@ static mmu_mmap_region_s g_mem_map_info[] = { .size = 0x17FFFF, .max_level = 0x2, .attrs = MMU_ATTR_DEVICE_NGNRNE | MMU_ACCESS_RWX, + }, { + .virt = MMU_IO_CONFIG_ADDR, + .phys = MMU_IO_CONFIG_ADDR, + .size = 0x10000, + .max_level = 0x2, + .attrs = MMU_ATTR_DEVICE_NGNRNE | MMU_ACCESS_RWX, + }, { + .virt = MMU_IO_CONFIG_T_ADDR, + .phys = MMU_IO_CONFIG_T_ADDR, + .size = 0x10000, + .max_level = 0x2, + .attrs = MMU_ATTR_DEVICE_NGNRNE | MMU_ACCESS_RW, + }, { + .virt = MMU_WDG_ADDR, + .phys = MMU_WDG_ADDR, + .size = 0x50000, + .max_level = 0x2, + .attrs = MMU_ATTR_DEVICE_NGNRNE | MMU_ACCESS_RW, + }, { + .virt = MMU_DMAC_ADDR, + .phys = MMU_DMAC_ADDR, + .size = 0x10000, + .max_level = 0x2, + .attrs = MMU_ATTR_DEVICE_NGNRNE | MMU_ACCESS_RW, + }, { + .virt = MMU_I2C_ADDR, + .phys = MMU_I2C_ADDR, + .size = 0x100000, + .max_level = 0x2, + .attrs = MMU_ATTR_DEVICE_NGNRNE | MMU_ACCESS_RW, + }, { + .virt = MMU_LOCALBUS_ADDR, + .phys = MMU_LOCALBUS_ADDR, + .size = 0x200, + .max_level = 0x2, + .attrs = MMU_ATTR_DEVICE_NGNRNE | MMU_ACCESS_RW, + }, { + .virt = MMU_RESERVED_ADDR, + .phys = MMU_RESERVED_ADDR, + .size = 0x40000, + .max_level = 0x2, + .attrs = MMU_ATTR_DEVICE_NGNRNE | MMU_ACCESS_RW, + }, { + .virt = MMU_SPI_ADDR, + .phys = MMU_SPI_ADDR, + .size = 0x20000, + .max_level = 0x2, + .attrs = MMU_ATTR_DEVICE_NGNRNE | MMU_ACCESS_RW, + }, { + .virt = MMU_GMAC_HP_ADDR, + .phys = MMU_GMAC_HP_ADDR, + .size = 0x40000, + .max_level = 0x2, + .attrs = MMU_ATTR_DEVICE_NGNRNE | MMU_ACCESS_RWX, + }, { + .virt = MMU_GMAC_HOST_ADDR, + .phys = 0x1E810000, + .size = 0x40000, + .max_level = 0x2, + .attrs = MMU_ATTR_DEVICE_NGNRNE | MMU_ACCESS_RWX, + }, { + .virt = MMU_MDIO_ADDR, + .phys = MMU_MDIO_ADDR, + .size = 0x10000, + .max_level = 0x2, + .attrs = MMU_ATTR_DEVICE_NGNRNE | MMU_ACCESS_RWX, + }, { + .virt = MMU_HP_SUBSYS_ADDR, + .phys = MMU_HP_SUBSYS_ADDR, + .size = 0x10000, + .max_level = 0x2, + .attrs = MMU_ATTR_DEVICE_NGNRNE | MMU_ACCESS_RWX, } }; diff --git a/demos/hi3095/config/prt_config.h b/demos/hi3095/config/prt_config.h index 8675127f..0ff693c5 100644 --- a/demos/hi3095/config/prt_config.h +++ b/demos/hi3095/config/prt_config.h @@ -95,7 +95,7 @@ extern "C" { #if defined(GUEST_OS) #define OS_MEM_FSC_PT_SIZE 0x80000 #else -#define OS_MEM_FSC_PT_SIZE 0x1d000000 +#define OS_MEM_FSC_PT_SIZE 0x80000 #endif /* ***************************** 配置信号量管理模块 ************************* */ diff --git a/demos/hi3095/drivers/samples/hi309x_memmap.h b/demos/hi3095/drivers/samples/hi309x_memmap.h index e50d4d3d..8fe0d8e1 100755 --- a/demos/hi3095/drivers/samples/hi309x_memmap.h +++ b/demos/hi3095/drivers/samples/hi309x_memmap.h @@ -4,9 +4,9 @@ #ifndef __HI309X_MEMMAP_H__ #define __HI309X_MEMMAP_H__ -#define MMU_DDR_ADDR 0x93000000ULL +#define MMU_DDR_ADDR 0xb3000000ULL #define MMU_DDR_SIZE 0x01000000ULL -#define MMU_PAGE_BEGIN 0x93800000 +#define MMU_PAGE_BEGIN 0xb3800000 #define MMU_PAGE_END (MMU_PAGE_BEGIN + 0x8000) #define MMU_DRIVER_ADDR 0x08600000ULL @@ -14,8 +14,9 @@ #define MMU_LOCALBUS_MEM_ADDR 0x30000000ULL #define MMU_LOCALBUS_MEM_SIZE 0x2FFFFFFF -#define MMU_OPENAMP_ADDR 0x90000000ULL +#define MMU_GIC_ADDR 0x24000000ULL #define MMU_OPENAMP_ADDR_SIZE 0x30000 +#define MMU_OPENAMP_ADDR 0xb0000000ULL #define CPU_RELEASE_ADDR_LEN (0x60) #define CONFIG_SYS_SDRAM_BASE (MMU_PAGE_END + CPU_RELEASE_ADDR_LEN + 0x20) @@ -29,4 +30,4 @@ #define GMAC_MDIO_SYNC (CPU_RELEASE_ADDR + 0x2c) /* 0x8727ffc8 */ #define GMAC_LOCK_SYNC (CPU_RELEASE_ADDR + 0x30) /* 0x8727ffc8 */ -#endif /* __HI309X_MEMMAP_H__ */ \ No newline at end of file +#endif /* __HI309X_MEMMAP_H__ */ -- Gitee