From f4930f05fd01007ac90b8a3dda2ba94e69fd5a5a Mon Sep 17 00:00:00 2001 From: Cathy Zhang Date: Mon, 7 Dec 2020 19:34:41 -0800 Subject: [PATCH 1/2] KVM: x86: Expose AVX512_FP16 for supported CPUID mainline inclusion from mainline-v5.11-rc1 commit 2224fc9efb2d6593fbfb57287e39ba4958b188ba category: feature feature: SPR New Instructions Virtualization bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5O6WB CVE: N/A Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ commit/?id=2224fc9efb2d6593fbfb57287e39ba4958b188ba Intel-SIG: commit 2224fc9efb2d ("KVM: x86: Expose AVX512_FP16 for supported CPUID") ------------------------------------- KVM: x86: Expose AVX512_FP16 for supported CPUID AVX512_FP16 is supported by Intel processors, like Sapphire Rapids. It could gain better performance for it's faster compared to FP32 if the precision or magnitude requirements are met. It's availability is indicated by CPUID.(EAX=7,ECX=0):EDX[bit 23]. Expose it in KVM supported CPUID, then guest could make use of it; no new registers are used, only new instructions. Signed-off-by: Cathy Zhang Signed-off-by: Kyung Min Park Acked-by: Dave Hansen Reviewed-by: Tony Luck Message-Id: <20201208033441.28207-3-kyung.min.park@intel.com> Signed-off-by: Paolo Bonzini Signed-off-by: Aichun Shi --- arch/x86/kvm/cpuid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index c957e591401c..3960f8bd0181 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -458,7 +458,7 @@ void kvm_set_cpu_caps(void) F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | - F(SERIALIZE) | F(TSXLDTRK) + F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) ); /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ -- Gitee From d2c319b2a3d76085d8c432fe7e45f23e40522c80 Mon Sep 17 00:00:00 2001 From: Yang Zhong Date: Tue, 5 Jan 2021 08:49:09 +0800 Subject: [PATCH 2/2] KVM: Expose AVX_VNNI instruction to guset mainline inclusion from mainline-v5.12-rc1 commit 1085a6b585d7d1c441cd10fdb4c7a4d96a22eba7 category: feature feature: SPR New Instructions Virtualization bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5O6WB CVE: N/A Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ commit/?id=1085a6b585d7d1c441cd10fdb4c7a4d96a22eba7 Intel-SIG: commit 1085a6b585d7 ("KVM: Expose AVX_VNNI instruction to guset") ------------------------------------- KVM: Expose AVX_VNNI instruction to guset Expose AVX (VEX-encoded) versions of the Vector Neural Network Instructions to guest. The bit definition: CPUID.(EAX=7,ECX=1):EAX[bit 4] AVX_VNNI The following instructions are available when this feature is present in the guest. 1. VPDPBUS: Multiply and Add Unsigned and Signed Bytes 2. VPDPBUSDS: Multiply and Add Unsigned and Signed Bytes with Saturation 3. VPDPWSSD: Multiply and Add Signed Word Integers 4. VPDPWSSDS: Multiply and Add Signed Integers with Saturation This instruction is currently documented in the latest "extensions" manual (ISE). It will appear in the "main" manual (SDM) in the future. Signed-off-by: Yang Zhong Reviewed-by: Tony Luck Message-Id: <20210105004909.42000-3-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini Signed-off-by: Aichun Shi --- arch/x86/kvm/cpuid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 3960f8bd0181..29a463658e67 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -473,7 +473,7 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); kvm_cpu_cap_mask(CPUID_7_1_EAX, - F(AVX512_BF16) + F(AVX_VNNI) | F(AVX512_BF16) ); kvm_cpu_cap_mask(CPUID_D_1_EAX, -- Gitee