diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index b6e5db1069e9bb3954ef03d47d8a7e2756b999ba..e48a7e2ba40ca5620bef62263a75775e9f86393f 100644
--- a/arch/x86/include/asm/amd_nb.h
+++ b/arch/x86/include/asm/amd_nb.h
@@ -85,6 +85,7 @@ bool amd_nb_has_feature(unsigned int feature);
 struct amd_northbridge *node_to_amd_nb(int node);
 
 bool hygon_f18h_m4h(void);
+bool hygon_f18h_m10h(void);
 u16 hygon_nb_num(void);
 int get_df_id(struct pci_dev *misc, u8 *id);
 
@@ -126,6 +127,7 @@ static inline bool amd_gart_present(void)
 #define amd_gart_present(x)	false
 
 #define hygon_f18h_m4h		false
+#define hygon_f18h_m10h		false
 #define hygon_nb_num(x)	0
 #define get_df_id(x, y)	NULL
 
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 2e098ea71759f1195159a260d8a106a15b68906c..4681cf9f9b3326326a899f62332144950d044d1e 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -257,6 +257,20 @@ bool hygon_f18h_m4h(void)
 }
 EXPORT_SYMBOL_GPL(hygon_f18h_m4h);
 
+bool hygon_f18h_m10h(void)
+{
+	if (boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
+		return false;
+
+	if (boot_cpu_data.x86 == 0x18 &&
+	    boot_cpu_data.x86_model >= 0x10 &&
+	    boot_cpu_data.x86_model <= 0x1f)
+		return true;
+
+	return false;
+}
+EXPORT_SYMBOL_GPL(hygon_f18h_m10h);
+
 u16 hygon_nb_num(void)
 {
 	return nb_num;
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index c9c2e0277f87899197d0cba562fc4f6699b53fbd..14bdbe126bd56f01e7197076a825dcc0ad01f3dc 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -867,12 +867,29 @@ static void debug_display_dimm_sizes_df(struct amd64_pvt *pvt, u8 ctrl)
 	}
 }
 
+static bool hygon_umc_channel_enabled(u16 nid, int channel)
+{
+	u32 enable;
+
+	if (hygon_f18h_m10h()) {
+		amd_df_indirect_read(nid, 1, 0x32c, 0xc, &enable);
+		if ((enable & BIT(channel)))
+			return true;
+		return false;
+	}
+
+	return true;
+}
+
 static void __dump_misc_regs_df(struct amd64_pvt *pvt)
 {
 	struct amd64_umc *umc;
 	u32 i, tmp, umc_base;
 
 	for_each_umc(i) {
+		if (!hygon_umc_channel_enabled(pvt->mc_node_id, i))
+			continue;
+
 		if (hygon_f18h_m4h())
 			umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, i);
 		else
@@ -1000,6 +1017,9 @@ static void read_umc_base_mask(struct amd64_pvt *pvt)
 	int cs, umc;
 
 	for_each_umc(umc) {
+		if (!hygon_umc_channel_enabled(pvt->mc_node_id, umc))
+			continue;
+
 		if (hygon_f18h_m4h())
 			umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, umc);
 		else
@@ -1113,7 +1133,9 @@ static void determine_memory_type_df(struct amd64_pvt *pvt)
 		 * Check if the system supports the "DDR Type" field in UMC Config
 		 * and has DDR5 DIMMs in use.
 		 */
-		if ((fam_type->flags.zn_regs_v2 || hygon_f18h_m4h()) &&
+		if ((fam_type->flags.zn_regs_v2 ||
+		     hygon_f18h_m4h() ||
+		     hygon_f18h_m10h()) &&
 		    ((umc->umc_cfg & GENMASK(2, 0)) == 0x1)) {
 			if (umc->dimm_cfg & BIT(5))
 				umc->dram_type = MEM_LRDDR5;
@@ -2921,6 +2943,9 @@ static void __read_mc_regs_df(struct amd64_pvt *pvt)
 
 	/* Read registers from each UMC */
 	for_each_umc(i) {
+		if (!hygon_umc_channel_enabled(pvt->mc_node_id, i))
+			continue;
+
 		if (hygon_f18h_m4h())
 			umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, i);
 		else
@@ -3383,6 +3408,9 @@ static bool ecc_enabled(struct pci_dev *F3, u16 nid)
 		for_each_umc(i) {
 			u32 base = get_umc_base(i);
 
+			if (!hygon_umc_channel_enabled(nid, i))
+				continue;
+
 			/* Only check enabled UMCs. */
 			if (amd_smn_read(nid, base + UMCCH_SDP_CTRL, &value))
 				continue;