From c405e85c90c4f48b58f66dd06fbb013b1bb8b683 Mon Sep 17 00:00:00 2001 From: Wenhui Fan Date: Fri, 14 Feb 2025 17:28:50 +0800 Subject: [PATCH 1/4] x86/MCE/AMD: Fix the calculation of cs id for Hygon family 18h model 4h hygon inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/IBMDWA CVE: NA --------------------------- Get the correct cs id in die interleave scenario for Hygon family 18h model 4h. Fixes: 08fdc64fd095 ("EDAC/amd64: Adjust address translation for Hygon family 18h model 4h") Signed-off-by: Wenhui Fan --- arch/x86/kernel/cpu/mce/amd.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 6ae54119205a..797100f8c168 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -785,12 +785,14 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) if (hygon_f18h_m4h()) { die_id_shift = (tmp >> 12) & 0xF; die_id_mask = tmp & 0x7FF; + cs_id |= (((cs_fabric_id & die_id_mask) >> die_id_shift) - 4) << + die_id_bit; } else { die_id_shift = (tmp >> 24) & 0xF; die_id_mask = (tmp >> 8) & 0xFF; + cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << + die_id_bit; } - - cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; } /* If interleaved over more than 1 socket. */ -- Gitee From 8ae8ee33969174d94e455a374572da728968548f Mon Sep 17 00:00:00 2001 From: Wenhui Fan Date: Fri, 14 Feb 2025 17:41:36 +0800 Subject: [PATCH 2/4] x86/MCE/AMD: Use u16 for some umc variables for Hygon family 18h model 4h hygon inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/IBME2Y CVE: NA --------------------------- The width of die/socket id mask and cs fabric id is extended to 11 bits since Hygon family 18h model 4h, so use u16 for those variables which are also suitable for all other older generation Hygon processors. Fixes: 08fdc64fd095 ("EDAC/amd64: Adjust address translation for Hygon family 18h model 4h") Signed-off-by: Wenhui Fan --- arch/x86/kernel/cpu/mce/amd.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 797100f8c168..29910b01aee1 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -643,7 +643,12 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) u32 tmp; - u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; + u8 die_id_shift, socket_id_shift; +#ifdef CONFIG_CPU_SUP_HYGON + u16 die_id_mask, socket_id_mask; +#else + u8 die_id_mask, socket_id_mask; +#endif u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; u8 intlv_addr_sel, intlv_addr_bit; u8 num_intlv_bits, hashed_bit; @@ -748,7 +753,12 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) if (num_intlv_bits > 0) { u64 temp_addr_x, temp_addr_i, temp_addr_y; - u8 die_id_bit, sock_id_bit, cs_fabric_id; + u8 die_id_bit, sock_id_bit; +#ifdef CONFIG_CPU_SUP_HYGON + u16 cs_fabric_id; +#else + u8 cs_fabric_id; +#endif /* * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. -- Gitee From 64ce30ee90a18ff0e1b9ea09869457317b667c9f Mon Sep 17 00:00:00 2001 From: Wenhui Fan Date: Tue, 18 Feb 2025 14:19:23 +0800 Subject: [PATCH 3/4] x86/MCE/AMD: Get intlv_num_dies from F0x60 for Hygon family 18h model 6h hygon inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/IBN1BI CVE: NA --------------------------- The intlv_num_dies should be get from F0x60[1:0] for Hygon family 18h model 6h. Fixes: 08fdc64fd095 ("EDAC/amd64: Adjust address translation for Hygon family 18h model 4h") Signed-off-by: Wenhui Fan --- arch/x86/kernel/cpu/mce/amd.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 29910b01aee1..5785fb51c9e3 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -710,6 +710,12 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) intlv_addr_bit = intlv_addr_sel + 8; + if (hygon_f18h_m4h() && boot_cpu_data.x86_model >= 0x6) { + if (amd_df_indirect_read(nid, 0, 0x60, umc, &tmp)) + goto out_err; + intlv_num_dies = tmp & 0x3; + } + /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ switch (intlv_num_chan) { case 0: intlv_num_chan = 0; break; -- Gitee From 3fa9c3e2544552719541b919e2f1090dd7683458 Mon Sep 17 00:00:00 2001 From: Wenhui Fan Date: Tue, 18 Feb 2025 15:29:35 +0800 Subject: [PATCH 4/4] EDAC/amd64: Adjust address translation for Hygon family 18h model 10h hygon inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/IBN2NP CVE: NA --------------------------- Add umc address translation support for Hygon family 18h model 10h. Signed-off-by: Wenhui Fan --- arch/x86/kernel/cpu/mce/amd.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 5785fb51c9e3..dbb3647cea24 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -657,7 +657,7 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) bool hash_enabled = false; /* Read DramOffset, check if base 1 is used. */ - if (hygon_f18h_m4h() && + if ((hygon_f18h_m4h() || hygon_f18h_m10h()) && amd_df_indirect_read(nid, 0, 0x214, umc, &tmp)) goto out_err; else if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp)) @@ -685,7 +685,7 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) } intlv_num_sockets = 0; - if (hygon_f18h_m4h()) + if (hygon_f18h_m4h() || hygon_f18h_m10h()) intlv_num_sockets = (tmp >> 2) & 0x3; lgcy_mmio_hole_en = tmp & BIT(1); intlv_num_chan = (tmp >> 4) & 0xF; @@ -703,14 +703,15 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) goto out_err; - if (!hygon_f18h_m4h()) + if (!hygon_f18h_m4h() && !hygon_f18h_m10h()) intlv_num_sockets = (tmp >> 8) & 0x1; intlv_num_dies = (tmp >> 10) & 0x3; dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); intlv_addr_bit = intlv_addr_sel + 8; - if (hygon_f18h_m4h() && boot_cpu_data.x86_model >= 0x6) { + if ((hygon_f18h_m4h() && boot_cpu_data.x86_model >= 0x6) || + hygon_f18h_m10h()) { if (amd_df_indirect_read(nid, 0, 0x60, umc, &tmp)) goto out_err; intlv_num_dies = tmp & 0x3; @@ -775,7 +776,7 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp)) goto out_err; - if (hygon_f18h_m4h()) + if (hygon_f18h_m4h() || hygon_f18h_m10h()) cs_fabric_id = (tmp >> 8) & 0x7FF; else cs_fabric_id = (tmp >> 8) & 0xFF; -- Gitee