diff --git a/Documentation/devicetree/bindings/serial/phytium,uart-2.0.yaml b/Documentation/devicetree/bindings/serial/phytium,uart-2.0.yaml
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@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/phytium,uart-v2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Phytium serial UART v2
+
+maintainers:
+  - Hengyu Lan <lanhengyu1395@phytium.com.cn>
+
+allOf:
+  - $ref: serial.yaml#
+
+# Need a custom select here or 'arm,primecell' will match on lots of nodes
+select:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - phytium,uart-2.0
+  required:
+    - compatible
+
+properties:
+  compatible:
+    items:
+      - const: phytium,uart-2.0
+
+  reg:
+    maxItems: 2
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    description:
+      When present, the first clock listed must correspond to
+      the clock named UARTCLK on the IP block, i.e. the clock
+      to the external serial line, whereas the second clock
+      must correspond to the PCLK clocking the internal logic
+      of the block. Just listing one clock (the first one) is
+      deprecated.
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: uartclk
+      - const: apb_pclk
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    uart@27011000 {
+            compatible = "phytium,uart-2.0";
+            reg = <0x0 0x27011000 0x0 0x1000>,
+            <0x0 0x26fe4000 0x0 0x1000>;
+            interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&sysclk_100mhz &sysclk_100mhz>;
+            clock-names = "uartclk", "apb_pclk";
+            status = "disabled";
+    };
+...