diff --git a/Documentation/virt/kvm/arm/hypercalls.rst b/Documentation/virt/kvm/arm/hypercalls.rst
index 3e23084644ba2aa680f1d2b232bc500f473254e2..67bd102cf43b1b09c6f3ab299e8dad01484fab11 100644
--- a/Documentation/virt/kvm/arm/hypercalls.rst
+++ b/Documentation/virt/kvm/arm/hypercalls.rst
@@ -127,6 +127,10 @@ The pseudo-firmware bitmap register are as follows:
     Bit-1: KVM_REG_ARM_VENDOR_HYP_BIT_PTP:
       The bit represents the Precision Time Protocol KVM service.
 
+    Bit-2: KVM_REG_ARM_VENDOR_HYP_BIT_IPIV:
+      The bit represents the ARM_SMCCC_VENDOR_PV_SGI_FEATURES and
+      ARM_SMCCC_VENDOR_PV_SGI_ENABLE function-ids.
+
 Errors:
 
     =======  =============================================================
diff --git a/Documentation/virt/kvm/arm/pvsgi.rst b/Documentation/virt/kvm/arm/pvsgi.rst
new file mode 100644
index 0000000000000000000000000000000000000000..5f12a3aaccd2d7f9ec24553a653b40747b13eae7
--- /dev/null
+++ b/Documentation/virt/kvm/arm/pvsgi.rst
@@ -0,0 +1,33 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+Paravirtualized SGI support for HiSilicon
+==========================================
+
+KVM/arm64 provides some hypervisor service calls to support a paravirtualized
+SGI(software generated interrupt) in HiSilicon Hip12 SoC.
+
+Some SMCCC compatible hypercalls are defined:
+
+* PV_SGI_FEATURES:      0xC6000090
+* PV_SGI_ENABLE:        0xC6000091
+
+The existence of the PV_SGI hypercall should be probed using the SMCCC 1.1
+ARCH_FEATURES mechanism before calling it.
+
+PV_SGI_FEATURES
+
+    ============= ========    ==========
+    Function ID:  (uint32)    0xC6000090
+    PV_call_id:   (uint32)    The function to query for support.
+                              Currently only PV_SGI_ENABLE is supported.
+    Return value: (int64)     NOT_SUPPORTED (-1) or SUCCESS (0) if the relevant
+                              PV-sgi feature is supported by the hypervisor.
+    ============= ========    ==========
+
+PV_SGI_ENABLE
+
+    ============= ========    ==========
+    Function ID:  (uint32)    0xC6000091
+    Return value: (int64)     NOT_SUPPORTED (-1) or SUCCESS (0) if this feature
+                              has been enabled.
+    ============= ========    ==========
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index dabbbb0e012caf233ce68738aef5a765468eb979..fed8b18fae5d06bd514403598b67c1f3a1919c6d 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -2392,6 +2392,19 @@ config ARM64_HDBSS
 
 endmenu # "ARMv9.5 architectural features"
 
+config ARM64_HISI_IPIV
+	bool "Enable support for IPIV"
+	default y
+	depends on ACPI
+	depends on ARM64
+	help
+	  IPIV optimizes vSGI on the basis of GICv4.1. The vCPU on the sending
+	  side of vSGI needs to trap to Hypervisor. IPIv sends vSGI without
+	  traping, improving performance.
+
+	  The feature will only be enabled if CPU in the system and Guest OS
+	  support this feature. If unsure, say Y.
+
 config ARM64_SVE
 	bool "ARM Scalable Vector Extension support"
 	default y
diff --git a/arch/arm64/configs/openeuler_defconfig b/arch/arm64/configs/openeuler_defconfig
index 3f9be66edece967c66e0ca25da824174d078030e..8f2aa4427a6a0c0674f958612a9eb01a848d9b7e 100644
--- a/arch/arm64/configs/openeuler_defconfig
+++ b/arch/arm64/configs/openeuler_defconfig
@@ -573,6 +573,7 @@ CONFIG_ARM64_NMI=y
 CONFIG_ARM64_HDBSS=y
 # end of ARMv9.5 architectural features
 
+CONFIG_ARM64_HISI_IPIV=y
 CONFIG_ARM64_SVE=y
 CONFIG_ARM64_SME=y
 CONFIG_ARM64_PSEUDO_NMI=y
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 80276f048aef933dc5e532276d300f7c48df205d..fd3dc6f8c3664ec8da07e809b31d34bd89ca8069 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -1294,6 +1294,9 @@ bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu);
 extern bool force_wfi_trap;
 extern bool kvm_ncsnp_support;
 extern bool kvm_dvmbm_support;
+
+#ifdef CONFIG_ARM64_HISI_IPIV
 extern bool kvm_ipiv_support;
+#endif
 
 #endif /* __ARM64_KVM_HOST_H__ */
diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
index 97941e582d83d0d0189d6a482a588290ac54df69..196231712b10975b06e929d347525d68364bae57 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -377,6 +377,11 @@ enum {
 enum {
 	KVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT	= 0,
 	KVM_REG_ARM_VENDOR_HYP_BIT_PTP		= 1,
+	/*
+	 * If the mainline conflicts, do not change the
+	 * current sequence, add in sequence.
+	 */
+	KVM_REG_ARM_VENDOR_HYP_BIT_IPIV		= 2,
 #ifdef __KERNEL__
 	KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_COUNT,
 #endif
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index 5bd31fc0e4469211c565af86f88748d2400400e2..7eb8eada1ef293c3e6334c23197816fae8536f03 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -67,9 +67,6 @@ bool kvm_ncsnp_support;
 /* Capability of DVMBM */
 bool kvm_dvmbm_support;
 
-/* Capability of IPIV */
-bool kvm_ipiv_support;
-
 static DEFINE_PER_CPU(unsigned char, kvm_hyp_initialized);
 
 bool is_kvm_arm_initialised(void)
@@ -198,6 +195,14 @@ static int kvm_cap_arm_enable_hdbss(struct kvm *kvm,
 }
 #endif
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+static int kvm_hisi_ipiv_enable_cap(struct kvm *kvm, struct kvm_enable_cap *cap)
+{
+	kvm->arch.vgic.its_vm.enable_ipiv_from_vmm = true;
+	return 0;
+}
+#endif
+
 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
 			    struct kvm_enable_cap *cap)
 {
@@ -256,6 +261,11 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
 	case KVM_CAP_ARM_HW_DIRTY_STATE_TRACK:
 		r = kvm_cap_arm_enable_hdbss(kvm, cap);
 		break;
+#endif
+#ifdef CONFIG_ARM64_HISI_IPIV
+	case KVM_CAP_ARM_HISI_IPIV:
+		r = kvm_hisi_ipiv_enable_cap(kvm, cap);
+		break;
 #endif
 	default:
 		r = -EINVAL;
@@ -386,7 +396,9 @@ void kvm_arch_destroy_vm(struct kvm *kvm)
 #endif
 }
 
+#ifdef CONFIG_ARM64_HISI_IPIV
 extern struct static_key_false ipiv_enable;
+#endif
 
 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
 {
@@ -517,12 +529,14 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
 		r = system_supports_hdbss();
 		break;
 #endif
-	case KVM_CAP_ARM_IPIV_MODE:
+#ifdef CONFIG_ARM64_HISI_IPIV
+	case KVM_CAP_ARM_HISI_IPIV:
 		if (static_branch_unlikely(&ipiv_enable))
 			r = 1;
 		else
 			r = 0;
 		break;
+#endif
 	default:
 		r = 0;
 	}
@@ -1536,6 +1550,16 @@ static int kvm_vcpu_init_check_features(struct kvm_vcpu *vcpu,
 	if (test_bit(KVM_ARM_VCPU_HAS_EL2, &features))
 		return -EINVAL;
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+	if (static_branch_unlikely(&ipiv_enable) &&
+	    vcpu->kvm->arch.vgic.its_vm.enable_ipiv_from_vmm &&
+	    vcpu->vcpu_id != vcpu->vcpu_idx) {
+		kvm_err("IPIV ERROR: vcpu_id %d != vcpu_idx %d\n",
+					vcpu->vcpu_id, vcpu->vcpu_idx);
+		return -EINVAL;
+	}
+#endif
+
 	return 0;
 }
 
@@ -2792,17 +2816,12 @@ static __init int kvm_arm_init(void)
 	probe_hisi_cpu_type();
 	kvm_ncsnp_support = hisi_ncsnp_supported();
 	kvm_dvmbm_support = hisi_dvmbm_supported();
-	kvm_ipiv_support = hisi_ipiv_supported();
 	kvm_info("KVM ncsnp %s\n", kvm_ncsnp_support ? "enabled" : "disabled");
 	kvm_info("KVM dvmbm %s\n", kvm_dvmbm_support ? "enabled" : "disabled");
-	kvm_info("KVM ipiv %s\n", kvm_ipiv_support ? "enabled" : "disabled");
 
 	if (kvm_dvmbm_support)
 		kvm_get_pg_cfg();
 
-	if (kvm_ipiv_support)
-		ipiv_gicd_init();
-
 	in_hyp_mode = is_kernel_in_hyp_mode();
 
 #ifdef CONFIG_HISI_VIRTCCA_HOST
diff --git a/arch/arm64/kvm/hisilicon/hisi_virt.c b/arch/arm64/kvm/hisilicon/hisi_virt.c
index a529c42b59c927f4a6ac957ce6b8328393797301..d9029d612697c419af516ada58234d9cc763483c 100644
--- a/arch/arm64/kvm/hisilicon/hisi_virt.c
+++ b/arch/arm64/kvm/hisilicon/hisi_virt.c
@@ -12,7 +12,10 @@
 static enum hisi_cpu_type cpu_type = UNKNOWN_HI_TYPE;
 
 static bool dvmbm_enabled;
+
+#ifdef CONFIG_ARM64_HISI_IPIV
 static bool ipiv_enabled;
+#endif
 
 static const char * const hisi_cpu_type_str[] = {
 	"Hisi1612",
@@ -158,6 +161,7 @@ static void hardware_disable_dvmbm(void *data)
 	write_sysreg_s(val, SYS_LSUDVM_CTRL_EL2);
 }
 
+#ifdef CONFIG_ARM64_HISI_IPIV
 static int __init early_ipiv_enable(char *buf)
 {
 	return strtobool(buf, &ipiv_enabled);
@@ -180,7 +184,7 @@ bool hisi_ipiv_supported(void)
 		return false;
 
 	/* Enable IPIV feature if necessary */
-	if (!is_gicv4p1()) {
+	if (!kvm_vgic_global_state.has_gicv4_1) {
 		kvm_info("Hisi ipiv needs to enable GICv4p1!\n");
 		return false;
 	}
@@ -189,10 +193,36 @@ bool hisi_ipiv_supported(void)
 	return true;
 }
 
+extern struct static_key_false ipiv_enable;
+
+bool hisi_ipiv_supported_per_vm(struct kvm_vcpu *vcpu)
+{
+	/* IPIV is supported by the hardware */
+	if (!static_branch_unlikely(&ipiv_enable))
+		return false;
+
+	/* vSGI passthrough is configured */
+	if (!vcpu->kvm->arch.vgic.nassgireq)
+		return false;
+
+	/* IPIV is enabled by the user */
+	if (!vcpu->kvm->arch.vgic.its_vm.enable_ipiv_from_vmm)
+		return false;
+
+	return true;
+}
+
+void hisi_ipiv_enable_per_vm(struct kvm_vcpu *vcpu)
+{
+	/* Enable IPIV feature */
+	vcpu->kvm->arch.vgic.its_vm.enable_ipiv_from_guest = true;
+}
+
 void ipiv_gicd_init(void)
 {
 	gic_dist_enable_ipiv();
 }
+#endif /* CONFIG_ARM64_HISI_IPIV */
 
 bool hisi_dvmbm_supported(void)
 {
diff --git a/arch/arm64/kvm/hisilicon/hisi_virt.h b/arch/arm64/kvm/hisilicon/hisi_virt.h
index f0b47c020261f58119aa354ae2964356f9cfa605..531a7522797278115351e1cb762d3da4026418c1 100644
--- a/arch/arm64/kvm/hisilicon/hisi_virt.h
+++ b/arch/arm64/kvm/hisilicon/hisi_virt.h
@@ -19,7 +19,9 @@ enum hisi_cpu_type {
 };
 
 /* HIP12 */
+#ifdef CONFIG_ARM64_HISI_IPIV
 #define AIDR_EL1_IPIV_MASK	GENMASK_ULL(17, 16)
+#endif
 /* HIP10 */
 #define AIDR_EL1_DVMBM_MASK	GENMASK_ULL(13, 12)
 #define SYS_LSUDVM_CTRL_EL2	sys_reg(3, 4, 15, 7, 4)
@@ -77,9 +79,13 @@ enum hisi_cpu_type {
 void probe_hisi_cpu_type(void);
 bool hisi_ncsnp_supported(void);
 bool hisi_dvmbm_supported(void);
+#ifdef CONFIG_ARM64_HISI_IPIV
 bool hisi_ipiv_supported(void);
-void kvm_get_pg_cfg(void);
+bool hisi_ipiv_supported_per_vm(struct kvm_vcpu *vcpu);
+void hisi_ipiv_enable_per_vm(struct kvm_vcpu *vcpu);
 void ipiv_gicd_init(void);
+#endif /* CONFIG_ARM64_HISI_IPIV */
+void kvm_get_pg_cfg(void);
 
 int kvm_sched_affinity_vcpu_init(struct kvm_vcpu *vcpu);
 void kvm_sched_affinity_vcpu_destroy(struct kvm_vcpu *vcpu);
@@ -98,12 +104,19 @@ static inline bool hisi_dvmbm_supported(void)
 {
 	return false;
 }
+#ifdef CONFIG_ARM64_HISI_IPIV
 static inline bool hisi_ipiv_supported(void)
 {
 	return false;
 }
-static inline void kvm_get_pg_cfg(void) {}
+static bool hisi_ipiv_supported_per_vm(struct kvm_vcpu *vcpu)
+{
+	return false;
+}
+static void hisi_ipiv_enable_per_vm(struct kvm_vcpu *vcpu) {}
 static inline void ipiv_gicd_init(void) {}
+#endif /* CONFIG_ARM64_HISI_IPIV */
+static inline void kvm_get_pg_cfg(void) {}
 
 static inline int kvm_sched_affinity_vcpu_init(struct kvm_vcpu *vcpu)
 {
@@ -120,6 +133,7 @@ static inline void kvm_tlbi_dvmbm_vcpu_put(struct kvm_vcpu *vcpu) {}
 static inline void kvm_hisi_reload_lsudvmbm(struct kvm *kvm) {}
 #endif /* CONFIG_KVM_HISI_VIRT */
 
+#ifdef CONFIG_ARM64_HISI_IPIV
 extern bool gic_dist_enable_ipiv(void);
-extern bool is_gicv4p1(void);
+#endif /* CONFIG_ARM64_HISI_IPIV */
 #endif /* __HISI_VIRT_H__ */
diff --git a/arch/arm64/kvm/hypercalls.c b/arch/arm64/kvm/hypercalls.c
index 4c9fc5df5142b1a8b531a57fe059609701dea393..f02c7b53c922b9198b1b2833ae51f6d1bb412e1a 100644
--- a/arch/arm64/kvm/hypercalls.c
+++ b/arch/arm64/kvm/hypercalls.c
@@ -9,6 +9,10 @@
 #include <kvm/arm_hypercalls.h>
 #include <kvm/arm_psci.h>
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+#include "hisilicon/hisi_virt.h"
+#endif
+
 #define KVM_ARM_SMCCC_STD_FEATURES				\
 	GENMASK(KVM_REG_ARM_STD_BMAP_BIT_COUNT - 1, 0)
 #define KVM_ARM_SMCCC_STD_HYP_FEATURES				\
@@ -116,6 +120,12 @@ static bool kvm_smccc_test_fw_bmap(struct kvm_vcpu *vcpu, u32 func_id)
 	case ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID:
 		return test_bit(KVM_REG_ARM_VENDOR_HYP_BIT_PTP,
 				&smccc_feat->vendor_hyp_bmap);
+#ifdef CONFIG_ARM64_HISI_IPIV
+	case ARM_SMCCC_VENDOR_PV_SGI_FEATURES:
+	case ARM_SMCCC_VENDOR_PV_SGI_ENABLE:
+		return test_bit(KVM_REG_ARM_VENDOR_HYP_BIT_IPIV,
+				&smccc_feat->vendor_hyp_bmap);
+#endif
 	default:
 		return false;
 	}
@@ -363,6 +373,22 @@ int kvm_smccc_call_handler(struct kvm_vcpu *vcpu)
 		val[0] = SMCCC_RET_SUCCESS;
 		break;
 #endif /* CONFIG_PARAVIRT_SCHED */
+#ifdef CONFIG_ARM64_HISI_IPIV
+	case ARM_SMCCC_VENDOR_PV_SGI_FEATURES:
+		if (hisi_ipiv_supported_per_vm(vcpu))
+			val[0] = SMCCC_RET_SUCCESS;
+		else
+			val[0] = SMCCC_RET_NOT_SUPPORTED;
+		break;
+	case ARM_SMCCC_VENDOR_PV_SGI_ENABLE:
+		if (hisi_ipiv_supported_per_vm(vcpu)) {
+			hisi_ipiv_enable_per_vm(vcpu);
+			val[0] = SMCCC_RET_SUCCESS;
+		} else {
+			val[0] = SMCCC_RET_NOT_SUPPORTED;
+		}
+		break;
+#endif
 	case ARM_SMCCC_VENDOR_HYP_CALL_UID_FUNC_ID:
 		val[0] = ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_0;
 		val[1] = ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_1;
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 6a3dddaddd94dcbbf2734b05e8bdee2f5eedb0f4..8cd4c95759a02df30dabff05317ccbb3c2559eba 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -711,8 +711,6 @@ static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 	return actlr;
 }
 
-extern struct static_key_false ipiv_enable;
-
 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 {
 	u64 mpidr;
@@ -728,14 +726,6 @@ static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 	mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
 	mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
 
-	if (static_branch_unlikely(&ipiv_enable)) {
-		/*
-		 * To avoid sending multi-SGIs in guest OS, make aff1/aff2 unique
-		 */
-		mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(1);
-		mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(2);
-	}
-
 	mpidr |= (1ULL << 31);
 	vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1);
 
@@ -1578,6 +1568,25 @@ static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu,
 	return val;
 }
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+extern struct static_key_false ipiv_enable;
+static int set_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
+		     u64 val)
+{
+	if (static_branch_unlikely(&ipiv_enable) &&
+	    vcpu->kvm->arch.vgic.its_vm.enable_ipiv_from_vmm) {
+		if (val != __vcpu_sys_reg(vcpu, rd->reg)) {
+			kvm_err("IPIV ERROR: MPIDR changed\n");
+			return -EINVAL;
+		}
+	}
+
+	__vcpu_sys_reg(vcpu, rd->reg) = val;
+
+	return 0;
+}
+#endif
+
 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
 			   const struct sys_reg_desc *rd,
 			   u64 val)
@@ -2083,7 +2092,12 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 
 	{ SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+	{ SYS_DESC(SYS_MPIDR_EL1),
+	  .reset = reset_mpidr, .reg = MPIDR_EL1, .set_user = set_mpidr},
+#else
 	{ SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
+#endif
 
 	/*
 	 * ID regs: all ID_SANITISED() entries here must have corresponding
diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c
index 5579ca6b1d8097129bd1b732df9be573b814baf9..9ec452bcfb13e1a51c3e7f8ab645a16782176c3b 100644
--- a/arch/arm64/kvm/vgic/vgic-init.c
+++ b/arch/arm64/kvm/vgic/vgic-init.c
@@ -13,6 +13,11 @@
 #include <asm/kvm_mmu.h>
 #include "vgic.h"
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+#include <linux/irqchip/arm-gic-v3.h>
+#include "hisilicon/hisi_virt.h"
+#endif
+
 /*
  * Initialization rules: there are multiple stages to the vgic
  * initialization, both for the distributor and the CPU interfaces.  The basic
@@ -532,7 +537,7 @@ int kvm_vgic_map_resources(struct kvm *kvm)
 	return ret;
 }
 
-#ifdef CONFIG_ACPI
+#ifdef CONFIG_ARM64_HISI_IPIV
 extern struct static_key_false ipiv_enable;
 static int ipiv_irq;
 #endif
@@ -542,7 +547,7 @@ static int ipiv_irq;
 void kvm_vgic_cpu_up(void)
 {
 	enable_percpu_irq(kvm_vgic_global_state.maint_irq, 0);
-#ifdef CONFIG_ACPI
+#ifdef CONFIG_ARM64_HISI_IPIV
 	if (static_branch_unlikely(&ipiv_enable))
 		enable_percpu_irq(ipiv_irq, 0);
 #endif
@@ -552,16 +557,34 @@ void kvm_vgic_cpu_up(void)
 void kvm_vgic_cpu_down(void)
 {
 	disable_percpu_irq(kvm_vgic_global_state.maint_irq);
-#ifdef CONFIG_ACPI
+#ifdef CONFIG_ARM64_HISI_IPIV
 	if (static_branch_unlikely(&ipiv_enable))
 		disable_percpu_irq(ipiv_irq);
 #endif
 }
 
-#ifdef CONFIG_ACPI
+#ifdef CONFIG_ARM64_HISI_IPIV
+extern void __iomem *gic_data_rdist_get_vlpi_base(void);
 static irqreturn_t vgic_ipiv_irq_handler(int irq, void *data)
 {
-	kvm_info("IPIV irq handler!\n");
+	void __iomem *vlpi_base = gic_data_rdist_get_vlpi_base();
+	u32 gicr_ipiv_st;
+	bool broadcast_err, grpbrd_err, vcpuidx_err;
+
+	gicr_ipiv_st = readl_relaxed(vlpi_base + GICR_IPIV_ST);
+
+	broadcast_err = !!(gicr_ipiv_st & GICR_IPIV_ST_IRM_ERR);
+	if (broadcast_err)
+		kvm_err("IPIV error: IRM=1 Guest broadcast error\n");
+
+	grpbrd_err = !!(gicr_ipiv_st & GICR_IPIV_ST_BRPBRD_ERR);
+	if (grpbrd_err)
+		kvm_err("IPIV error: Guest group broadcast error\n");
+
+	vcpuidx_err = !!(gicr_ipiv_st & GICR_IPIV_ST_VCPUIDX_ERR);
+	if (vcpuidx_err)
+		kvm_err("IPIV error: The VCPU index is out of range\n");
+
 	return IRQ_HANDLED;
 }
 #endif
@@ -675,7 +698,14 @@ int kvm_vgic_hyp_init(void)
 
 	kvm_info("vgic interrupt IRQ%d\n", kvm_vgic_global_state.maint_irq);
 
-#ifdef CONFIG_ACPI
+#ifdef CONFIG_ARM64_HISI_IPIV
+	if (hisi_ipiv_supported()) {
+		ipiv_gicd_init();
+		kvm_info("KVM ipiv enabled\n");
+	} else {
+		kvm_info("KVM ipiv disabled\n");
+	}
+
 	if (static_branch_unlikely(&ipiv_enable)) {
 		ipiv_irq = acpi_register_gsi(NULL, 18, ACPI_EDGE_SENSITIVE,
 			ACPI_ACTIVE_HIGH);
diff --git a/arch/arm64/kvm/vgic/vgic-its.c b/arch/arm64/kvm/vgic/vgic-its.c
index 619c007e01aff4401ea9761767d287797ca47712..f888b099cefc8010c2921cf9812b82a3119cee7f 100644
--- a/arch/arm64/kvm/vgic/vgic-its.c
+++ b/arch/arm64/kvm/vgic/vgic-its.c
@@ -533,6 +533,14 @@ static unsigned long vgic_mmio_read_its_typer(struct kvm *kvm,
 	return extract_bytes(reg, addr & 7, len);
 }
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+/*
+ * Use bit7 not used by GITS_IIDR to indicate whether IPIV is
+ * enabled for guest OS.
+ */
+#define HISI_GUEST_ENABLE_IPIV_SHIFT 7
+#endif
+
 static unsigned long vgic_mmio_read_its_iidr(struct kvm *kvm,
 					     struct vgic_its *its,
 					     gpa_t addr, unsigned int len)
@@ -553,6 +561,12 @@ static int vgic_mmio_uaccess_write_its_iidr(struct kvm *kvm,
 
 	if (rev >= NR_ITS_ABIS)
 		return -EINVAL;
+
+#ifdef CONFIG_ARM64_HISI_IPIV
+	if (val & (1UL << HISI_GUEST_ENABLE_IPIV_SHIFT))
+		kvm->arch.vgic.its_vm.enable_ipiv_from_guest = true;
+#endif
+
 	return vgic_its_set_abi(its, rev);
 }
 
@@ -2338,6 +2352,11 @@ static int vgic_its_attr_regs_access(struct kvm_device *dev,
 			region->its_write(dev->kvm, its, addr, len, *reg);
 	} else {
 		*reg = region->its_read(dev->kvm, its, addr, len);
+#ifdef CONFIG_ARM64_HISI_IPIV
+		if (dev->kvm->arch.vgic.its_vm.enable_ipiv_from_guest &&
+			    offset == GITS_IIDR)
+			*reg |= 1UL << HISI_GUEST_ENABLE_IPIV_SHIFT;
+#endif
 	}
 out:
 	mutex_unlock(&dev->kvm->arch.config_lock);
@@ -2968,6 +2987,15 @@ static void vgic_its_reset(struct kvm *kvm, struct vgic_its *its)
 	its->enabled = 0;
 	vgic_its_free_device_list(kvm, its);
 	vgic_its_free_collection_list(kvm, its);
+
+#ifdef CONFIG_ARM64_HISI_IPIV
+	/*
+	 * For the para-virtualization feature IPIV, ensure that
+	 * the flag of the guest OS is reset when the guest OS is
+	 * reset.
+	 */
+	kvm->arch.vgic.its_vm.enable_ipiv_from_guest = false;
+#endif
 }
 
 static int vgic_its_has_attr(struct kvm_device *dev,
diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-mmio-v3.c
index d55607dcd226fb5a8f432a2d1f38cc85e2b6b460..961c3a79f41d9d19a705c185686dc99d60af75b8 100644
--- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c
+++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c
@@ -136,7 +136,6 @@ static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
 
 		/* Switching HW SGIs? */
 		dist->nassgireq = val & GICD_CTLR_nASSGIreq;
-		dist->its_vm.nassgireq = dist->nassgireq;
 		if (is_hwsgi != dist->nassgireq)
 			vgic_v4_configure_vsgis(vcpu->kvm);
 
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 3121b9f4c710fd328e6a07a2e226b096a06d6697..9b5103d0e6de914bc45c1b6267939e066801dcce 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -388,7 +388,13 @@ static int alloc_devid_from_rsv_pools(struct rsv_devid_pool **devid_pool,
 #define gic_data_rdist_rd_base()	(gic_data_rdist()->rd_base)
 #define gic_data_rdist_vlpi_base()	(gic_data_rdist_rd_base() + SZ_128K)
 
-extern struct static_key_false ipiv_enable;
+#ifdef CONFIG_ARM64_HISI_IPIV
+void __iomem *gic_data_rdist_get_vlpi_base(void)
+{
+	return gic_data_rdist_vlpi_base();
+}
+EXPORT_SYMBOL(gic_data_rdist_get_vlpi_base);
+#endif
 
 #ifdef CONFIG_VIRT_PLAT_DEV
 /*
@@ -4564,6 +4570,7 @@ static void its_vpe_4_1_unmask_irq(struct irq_data *d)
 	its_vpe_4_1_send_inv(d);
 }
 
+#ifdef CONFIG_ARM64_HISI_IPIV
 /* IPIV private register */
 #define CPU_SYS_TRAP_EL2		sys_reg(3, 4, 15, 7, 2)
 #define CPU_SYS_TRAP_EL2_IPIV_ENABLE_SHIFT	0
@@ -4576,40 +4583,38 @@ static void its_vpe_4_1_unmask_irq(struct irq_data *d)
  */
 static void ipiv_disable_vsgi_trap(void)
 {
-#ifdef CONFIG_ARM64
 	u64 val;
 
 	/* disable guest access ICC_SGI1R_EL1 trap, enable ipiv */
 	val = read_sysreg_s(CPU_SYS_TRAP_EL2);
 	val |= CPU_SYS_TRAP_EL2_IPIV_ENABLE;
 	write_sysreg_s(val, CPU_SYS_TRAP_EL2);
-#endif
 }
 
 static void ipiv_enable_vsgi_trap(void)
 {
-#ifdef CONFIG_ARM64
 	u64 val;
 
 	/* enable guest access ICC_SGI1R_EL1 trap, disable ipiv */
 	val = read_sysreg_s(CPU_SYS_TRAP_EL2);
 	val &= ~CPU_SYS_TRAP_EL2_IPIV_ENABLE;
 	write_sysreg_s(val, CPU_SYS_TRAP_EL2);
-#endif
 }
+#endif /* CONFIG_ARM64_HISI_IPIV */
 
 static void its_vpe_4_1_schedule(struct its_vpe *vpe,
 				 struct its_cmd_info *info)
 {
 	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
+	u64 val = 0;
+
+#ifdef CONFIG_ARM64_HISI_IPIV
 	struct its_vm *vm = vpe->its_vm;
 	unsigned long vpeid_page_addr;
 	u64 ipiv_val = 0;
-	u64 val = 0;
 	u32 nr_vpes;
 
-	if (static_branch_unlikely(&ipiv_enable) &&
-	    vm->nassgireq) {
+	if (vm->enable_ipiv_from_guest) {
 		/* wait gicr_ipiv_busy */
 		WARN_ON_ONCE(readl_relaxed_poll_timeout_atomic(vlpi_base + GICR_IPIV_ST,
 					ipiv_val, !(ipiv_val & GICR_IPIV_ST_IPIV_BUSY), 1, 500));
@@ -4627,6 +4632,7 @@ static void its_vpe_4_1_schedule(struct its_vpe *vpe,
 
 		ipiv_disable_vsgi_trap();
 	}
+#endif /* CONFIG_ARM64_HISI_IPIV */
 
 	/* Schedule the VPE */
 	val |= GICR_VPENDBASER_Valid;
@@ -4641,9 +4647,12 @@ static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
 				   struct its_cmd_info *info)
 {
 	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
-	struct its_vm *vm = vpe->its_vm;
 	u64 val;
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+	struct its_vm *vm = vpe->its_vm;
+#endif
+
 	if (info->req_db) {
 		unsigned long flags;
 
@@ -4674,8 +4683,8 @@ static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
 		vpe->pending_last = true;
 	}
 
-	if (static_branch_unlikely(&ipiv_enable) &&
-	    vm->nassgireq) {
+#ifdef CONFIG_ARM64_HISI_IPIV
+	if (vm->enable_ipiv_from_guest) {
 		/* wait gicr_ipiv_busy */
 		WARN_ON_ONCE(readl_relaxed_poll_timeout_atomic(vlpi_base + GICR_IPIV_ST,
 					val, !(val & GICR_IPIV_ST_IPIV_BUSY), 1, 500));
@@ -4684,6 +4693,7 @@ static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
 
 		ipiv_enable_vsgi_trap();
 	}
+#endif
 }
 
 static void its_vpe_4_1_invall(struct its_vpe *vpe)
@@ -5086,10 +5096,12 @@ static void its_vpe_irq_domain_free(struct irq_domain *domain,
 	if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
 		its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
 		its_free_prop_table(vm->vprop_page);
-		if (static_branch_unlikely(&ipiv_enable)) {
+#ifdef CONFIG_ARM64_HISI_IPIV
+		if (vm->enable_ipiv_from_vmm) {
 			free_pages((unsigned long)page_address(vm->vpeid_page),
 				    get_order(nr_irqs * 2));
 		}
+#endif
 	}
 }
 
@@ -5099,10 +5111,14 @@ static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq
 	struct irq_chip *irqchip = &its_vpe_irq_chip;
 	struct its_vm *vm = args;
 	unsigned long *bitmap;
-	struct page *vprop_page, *vpeid_page;
+	struct page *vprop_page;
 	int base, nr_ids, i, err = 0;
+
+#ifdef CONFIG_ARM64_HISI_IPIV
+	struct page *vpeid_page;
 	void *vpeid_table_va;
 	u16 *vpeid_entry;
+#endif
 
 	bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
 	if (!bitmap)
@@ -5127,7 +5143,8 @@ static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq
 
 	if (gic_rdists->has_rvpeid) {
 		irqchip = &its_vpe_4_1_irq_chip;
-		if (static_branch_unlikely(&ipiv_enable)) {
+#ifdef CONFIG_ARM64_HISI_IPIV
+		if (vm->enable_ipiv_from_vmm) {
 			/*
 			 * The vpeid's size is 2 bytes, so we need to allocate 2 *
 			 * (num of vcpus). nr_irqs is equal to the number of vCPUs.
@@ -5141,6 +5158,7 @@ static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq
 			vm->vpeid_page = vpeid_page;
 			vpeid_table_va = page_address(vpeid_page);
 		}
+#endif
 	}
 
 	for (i = 0; i < nr_irqs; i++) {
@@ -5148,10 +5166,12 @@ static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq
 		err = its_vpe_init(vm->vpes[i]);
 		if (err)
 			break;
-		if (static_branch_unlikely(&ipiv_enable)) {
+#ifdef CONFIG_ARM64_HISI_IPIV
+		if (vm->enable_ipiv_from_vmm) {
 			vpeid_entry = (u16 *)vpeid_table_va + i;
 			*vpeid_entry = vm->vpes[i]->vpe_id;
 		}
+#endif
 		err = its_irq_gic_domain_alloc(domain, virq + i,
 					       vm->vpes[i]->vpe_db_lpi);
 		if (err)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 7a64d77be181d092bfaa4cb2368ab792e4fc9643..37eb995320a37a25def63c6ab6abfb963ca5de54 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -111,9 +111,15 @@ static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
 DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities);
 EXPORT_SYMBOL(gic_nonsecure_priorities);
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+/* indicate if host supports IPIv */
 DEFINE_STATIC_KEY_FALSE(ipiv_enable);
 EXPORT_SYMBOL(ipiv_enable);
 
+/* indicate if guest is using IPIv */
+static bool hisi_pv_sgi_enabled;
+#endif
+
 /*
  * When the Non-secure world has access to group 0 interrupts (as a
  * consequence of SCR_EL3.FIQ == 0), reading the ICC_RPR_EL1 register will
@@ -1514,15 +1520,7 @@ static int gic_dist_supports_lpis(void)
 		!gicv3_nolpi);
 }
 
-bool is_gicv4p1(void)
-{
-	if (!gic_data.rdists.has_rvpeid)
-		return false;
-
-	return true;
-}
-EXPORT_SYMBOL(is_gicv4p1);
-
+#ifdef CONFIG_ARM64_HISI_IPIV
 void gic_dist_enable_ipiv(void)
 {
 	u32 val;
@@ -1533,8 +1531,8 @@ void gic_dist_enable_ipiv(void)
 	static_branch_enable(&ipiv_enable);
 
 	val = (0 << GICD_IPIV_CTRL_AFF_DIRECT_VPEID_SHIFT) |
-		(0 << GICD_IPIV_CTRL_AFF1_LEFT_SHIFT_SHIFT) |
-		(4 << GICD_IPIV_CTRL_AFF2_LEFT_SHIFT_SHIFT) |
+		(4 << GICD_IPIV_CTRL_AFF1_LEFT_SHIFT_SHIFT) |
+		(12 << GICD_IPIV_CTRL_AFF2_LEFT_SHIFT_SHIFT) |
 		(7 << GICD_IPIV_CTRL_VM_TABLE_INNERCACHE_SHIFT) |
 		(2 << GICD_IPIV_CTRL_VM_TABLE_SHAREABILITY_SHIFT);
 	writel_relaxed(val, gic_data.dist_base + GICD_IPIV_CTRL);
@@ -1543,6 +1541,7 @@ void gic_dist_enable_ipiv(void)
 	writel_relaxed(0x4880, gic_data.dist_base + GICD_IPIV_ITS_TA_BASE);
 }
 EXPORT_SYMBOL(gic_dist_enable_ipiv);
+#endif /* CONFIG_ARM64_HISI_IPIV */
 
 static void gic_cpu_init(void)
 {
@@ -1652,7 +1651,15 @@ static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
 		u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(gic_cpu_to_affinity(cpu));
 		u16 tlist;
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+		if (!hisi_pv_sgi_enabled)
+			tlist = gic_compute_target_list(&cpu, mask, cluster_id);
+		else
+			tlist = 1 << (gic_cpu_to_affinity(cpu) & 0xf);
+#else
 		tlist = gic_compute_target_list(&cpu, mask, cluster_id);
+#endif
+
 		gic_send_sgi(cluster_id, tlist, d->hwirq);
 	}
 
@@ -2937,6 +2944,28 @@ static struct fwnode_handle *gic_v3_get_gsi_domain_id(u32 gsi)
 	return gsi_domain_handle;
 }
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+static void hisi_pv_sgi_init(void)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_1_1_invoke(ARM_SMCCC_VENDOR_PV_SGI_FEATURES, &res);
+	if (res.a0 != SMCCC_RET_SUCCESS) {
+		pr_info("Not Support HiSilicon PV SGI!\n");
+		return;
+	}
+
+	arm_smccc_1_1_invoke(ARM_SMCCC_VENDOR_PV_SGI_ENABLE, &res);
+	if (res.a0 != SMCCC_RET_SUCCESS) {
+		pr_info("Disable HiSilicon PV SGI!\n");
+		return;
+	}
+
+	hisi_pv_sgi_enabled = true;
+	pr_info("Enable HiSilicon PV SGI!\n");
+}
+#endif
+
 static int __init
 gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
 {
@@ -2989,6 +3018,10 @@ gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
 	if (static_branch_likely(&supports_deactivate_key))
 		gic_acpi_setup_kvm_info();
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+	hisi_pv_sgi_init();
+#endif
+
 	return 0;
 
 out_fwhandle_free:
diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h
index 9aba481603524d991ca2bdd61fe03aa8dda22d06..26ca4fe621c95e55cc41b8bc56e8b3d42b6ed56f 100644
--- a/include/linux/arm-smccc.h
+++ b/include/linux/arm-smccc.h
@@ -572,5 +572,20 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1,
 			   0x92)
 #endif /* CONFIG_PARAVIRT_SCHED */
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+/* HiSilicon paravirtualised sgi calls */
+#define ARM_SMCCC_VENDOR_PV_SGI_FEATURES					\
+	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL,				\
+			   ARM_SMCCC_SMC_64,				\
+			   ARM_SMCCC_OWNER_VENDOR_HYP,			\
+			   0x90)
+
+#define ARM_SMCCC_VENDOR_PV_SGI_ENABLE					\
+	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL,				\
+			   ARM_SMCCC_SMC_64,				\
+			   ARM_SMCCC_OWNER_VENDOR_HYP,			\
+			   0x91)
+#endif /* CONFIG_ARM64_HISI_IPIV */
+
 #endif /*__ASSEMBLY__*/
 #endif /*__LINUX_ARM_SMCCC_H*/
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 01584f2abf90365a117a36f31b3335b2ebafbbff..8e97525a3afd94f70c2cc314eba41adc48e16d49 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -113,6 +113,7 @@
 #define GIC_PAGE_SIZE_64K		2ULL
 #define GIC_PAGE_SIZE_MASK		3ULL
 
+#ifdef CONFIG_ARM64_HISI_IPIV
 #define GICD_MISC_CTRL			0x2084
 #define GICD_MISC_CTRL_CFG_IPIV_EN	(1U << 19)
 
@@ -124,6 +125,7 @@
 #define GICD_IPIV_CTRL_VM_TABLE_INNERCACHE_SHIFT 16
 #define GICD_IPIV_CTRL_VM_TABLE_SHAREABILITY_SHIFT 19
 #define GICD_IPIV_ITS_TA_BASE	0xc010
+#endif
 
 /*
  * Re-Distributor registers, offsets from RD_base
@@ -374,6 +376,7 @@
 #define GICR_VSGIPENDR_BUSY		(1U << 31)
 #define GICR_VSGIPENDR_PENDING		GENMASK(15, 0)
 
+#ifdef CONFIG_ARM64_HISI_IPIV
 /* IPIV VM table address */
 #define GICR_VM_TABLE_BAR_L		0x140
 #define GICR_VM_TABLE_BAR_H		0x144
@@ -388,6 +391,13 @@
 #define GICR_IPIV_ST		0x14c
 #define GICR_IPIV_ST_IPIV_BUSY_SHIFT 0
 #define GICR_IPIV_ST_IPIV_BUSY (1 << GICR_IPIV_ST_IPIV_BUSY_SHIFT)
+#define GICR_IPIV_ST_IRM_ERR_ST_SHIFT 1
+#define GICR_IPIV_ST_IRM_ERR   (1 << GICR_IPIV_ST_IRM_ERR_ST_SHIFT)
+#define GICR_IPIV_ST_BRPBRD_ERR_ST_SHIFT 2
+#define GICR_IPIV_ST_BRPBRD_ERR   (1 << GICR_IPIV_ST_BRPBRD_ERR_ST_SHIFT)
+#define GICR_IPIV_ST_VCPUIDX_ERR_ST_SHIFT 3
+#define GICR_IPIV_ST_VCPUIDX_ERR   (1 << GICR_IPIV_ST_VCPUIDX_ERR_ST_SHIFT)
+#endif /* CONFIG_ARM64_HISI_IPIV */
 
 /*
  * ITS registers, offsets from ITS_base
diff --git a/include/linux/irqchip/arm-gic-v4.h b/include/linux/irqchip/arm-gic-v4.h
index 9109a841c8da1ef741df4de26d0ded442c9e10e1..09477a8a915808cbe98201055232fcdf170d7b15 100644
--- a/include/linux/irqchip/arm-gic-v4.h
+++ b/include/linux/irqchip/arm-gic-v4.h
@@ -34,8 +34,11 @@ struct its_vm {
 	 */
 	raw_spinlock_t		vmapp_lock;
 	u32			vlpi_count[GICv4_ITS_LIST_MAX];
+#ifdef CONFIG_ARM64_HISI_IPIV
 	KABI_EXTEND(struct page		*vpeid_page)
-	KABI_EXTEND(bool			nassgireq)
+	KABI_EXTEND(bool			enable_ipiv_from_vmm)
+	KABI_EXTEND(bool			enable_ipiv_from_guest)
+#endif
 };
 
 /* Embedded in kvm_vcpu.arch */
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 938613c25553787c1e133a1b8b9874f5aecde4cd..fd9991b243cd3ee7f4c837f20c3db52969eb3d31 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -1211,7 +1211,7 @@ struct kvm_ppc_resize_hpt {
 #define KVM_CAP_HYGON_COCO_EXT_CSV3_INJ_SECRET    (1 << 2)
 
 #define KVM_CAP_ARM_HW_DIRTY_STATE_TRACK 502
-#define KVM_CAP_ARM_IPIV_MODE 503
+#define KVM_CAP_ARM_HISI_IPIV 503
 
 #define KVM_CAP_ARM_VIRT_MSI_BYPASS 799