From 82617f37bf9291313637116251d1412f95814ca4 Mon Sep 17 00:00:00 2001 From: Wang Zhimin Date: Mon, 9 Jun 2025 14:54:48 +0800 Subject: [PATCH] iommu: smmuv3: Not print information of SMMU 0x10 event phytium inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ICDO1M CVE: NA ------------------------------------------------------- In the Phytium PS24080 SoC platforms, when SMMU event type is 0x10 and the fault translate address is 0x0, we skip this error informfation. Due to our RC controller's inability to fully handle the MCTP protocol. Signed-off-by: Xiao Cong Signed-off-by: Wang Yinfeng Signed-off-by: Wang Zhimin --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 13 +++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 ++++ 2 files changed, 17 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 090ccda84b46..47bca2eede09 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1774,6 +1774,19 @@ static irqreturn_t arm_smmu_evtq_thread(int irq, void *dev) while (!queue_remove_raw(q, evt)) { u8 id = FIELD_GET(EVTQ_0_ID, evt[0]); +#ifdef CONFIG_ARCH_PHYTIUM +#define PHYTIUM_CPU_SOCID_PS24080 0x6 + if (read_cpuid_id() == MIDR_PHYTIUM_FTC862 && + read_sysreg_s(SYS_AIDR_EL1) == PHYTIUM_CPU_SOCID_PS24080) { + u8 type = FIELD_GET(EVTQ_0_ID, evt[0]); + u64 addr = FIELD_GET(EVTQ_2_ADDR, evt[2]); + + if (type == EVT_ID_TRANSLATION_FAULT && + addr == TRANSLATE_INVALID_ADDR) + continue; + } +#endif + ret = arm_smmu_handle_evt(smmu, evt); if (!ret || !__ratelimit(&rs)) continue; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index ece2904fd728..9c9dd03f60d7 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -437,6 +437,7 @@ #define EVTQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - EVTQ_ENT_SZ_SHIFT) #define EVTQ_0_ID GENMASK_ULL(7, 0) +#define EVTQ_2_ADDR GENMASK_ULL(63, 0) #define EVT_ID_TRANSLATION_FAULT 0x10 #define EVT_ID_ADDR_SIZE_FAULT 0x11 @@ -481,6 +482,9 @@ #define MSI_IOVA_BASE 0x8000000 #define MSI_IOVA_LENGTH 0x100000 +#define TRANSLATE_INVALID_ADDR 0x0 +#define EVT_ID_TRANSLATION_FAULT 0x10 + struct arm_smmu_cmdq_ent { /* Common fields */ u8 opcode; -- Gitee